--Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
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--Tool Version: Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019
--Date        : Wed May 27 20:47:48 2020
--Host        : LAPTOP-RJQ3H7G3 running 64-bit major release  (build 9200)
--Command     : generate_target pdm_to_pcm_wrapper.bd
--Design      : pdm_to_pcm_wrapper
--Purpose     : IP block netlist
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity pdm_to_pcm_wrapper is
  port (
    fifo_almost_empty : out STD_LOGIC;
    fifo_almost_full : out STD_LOGIC;
    fifo_rd_clk : in STD_LOGIC;
    fifo_rd_en : in STD_LOGIC;
    pcm_data : out STD_LOGIC_VECTOR ( 31 downto 0 );
    pdm_clk : out STD_LOGIC_VECTOR ( 0 to 0 );
    pdm_data : in STD_LOGIC_VECTOR ( 3 downto 0 );
    resetn : in STD_LOGIC;
    start : in STD_LOGIC;
    sys_clock : in STD_LOGIC
  );
end pdm_to_pcm_wrapper;

architecture STRUCTURE of pdm_to_pcm_wrapper is
  component pdm_to_pcm is
  port (
    resetn : in STD_LOGIC;
    pdm_clk : out STD_LOGIC_VECTOR ( 0 to 0 );
    sys_clock : in STD_LOGIC;
    start : in STD_LOGIC;
    pcm_data : out STD_LOGIC_VECTOR ( 31 downto 0 );
    fifo_almost_full : out STD_LOGIC;
    fifo_almost_empty : out STD_LOGIC;
    fifo_rd_clk : in STD_LOGIC;
    fifo_rd_en : in STD_LOGIC;
    pdm_data : in STD_LOGIC_VECTOR ( 3 downto 0 )
  );
  end component pdm_to_pcm;
begin
pdm_to_pcm_i: component pdm_to_pcm
     port map (
      fifo_almost_empty => fifo_almost_empty,
      fifo_almost_full => fifo_almost_full,
      fifo_rd_clk => fifo_rd_clk,
      fifo_rd_en => fifo_rd_en,
      pcm_data(31 downto 0) => pcm_data(31 downto 0),
      pdm_clk(0) => pdm_clk(0),
      pdm_data(3 downto 0) => pdm_data(3 downto 0),
      resetn => resetn,
      start => start,
      sys_clock => sys_clock
    );
end STRUCTURE;
