// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019
// Date        : Tue May 12 21:39:51 2020
// Host        : LAPTOP-RJQ3H7G3 running 64-bit major release  (build 9200)
// Command     : write_verilog -force -mode synth_stub -rename_top pdm_to_pcm_c_shift_ram_1_0 -prefix
//               pdm_to_pcm_c_shift_ram_1_0_ pdm_to_pcm_c_shift_ram_0_0_stub.v
// Design      : pdm_to_pcm_c_shift_ram_0_0
// Purpose     : Stub declaration of top-level module interface
// Device      : xc7a200tfbg676-2
// --------------------------------------------------------------------------------

// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "c_shift_ram_v12_0_13,Vivado 2019.1" *)
module pdm_to_pcm_c_shift_ram_1_0(A, D, CLK, CE, Q)
/* synthesis syn_black_box black_box_pad_pin="A[9:0],D[15:0],CLK,CE,Q[15:0]" */;
  input [9:0]A;
  input [15:0]D;
  input CLK;
  input CE;
  output [15:0]Q;
endmodule
