-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019
-- Date        : Tue May 26 01:42:37 2020
-- Host        : LAPTOP-RJQ3H7G3 running 64-bit major release  (build 9200)
-- Command     : write_vhdl -force -mode funcsim
--               D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/ip/pdm_to_pcm_energy_compare_0_0/pdm_to_pcm_energy_compare_0_0_sim_netlist.vhdl
-- Design      : pdm_to_pcm_energy_compare_0_0
-- Purpose     : This VHDL netlist is a functional simulation representation of the design and should not be modified or
--               synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device      : xc7a200tfbg676-2
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity pdm_to_pcm_energy_compare_0_0_energy_compare is
  port (
    max_found : out STD_LOGIC;
    start_fifo : out STD_LOGIC;
    start : in STD_LOGIC;
    clk : in STD_LOGIC;
    val_in : in STD_LOGIC_VECTOR ( 31 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of pdm_to_pcm_energy_compare_0_0_energy_compare : entity is "energy_compare";
end pdm_to_pcm_energy_compare_0_0_energy_compare;

architecture STRUCTURE of pdm_to_pcm_energy_compare_0_0_energy_compare is
  signal \FSM_sequential_state[0]_i_1_n_0\ : STD_LOGIC;
  signal \FSM_sequential_state[0]_i_2_n_0\ : STD_LOGIC;
  signal \FSM_sequential_state[1]_i_1_n_0\ : STD_LOGIC;
  signal \i__carry__0_i_1_n_0\ : STD_LOGIC;
  signal \i__carry__0_i_2_n_0\ : STD_LOGIC;
  signal \i__carry__0_i_3_n_0\ : STD_LOGIC;
  signal \i__carry__0_i_4_n_0\ : STD_LOGIC;
  signal \i__carry__0_i_5_n_0\ : STD_LOGIC;
  signal \i__carry__0_i_6_n_0\ : STD_LOGIC;
  signal \i__carry__0_i_7_n_0\ : STD_LOGIC;
  signal \i__carry__0_i_8_n_0\ : STD_LOGIC;
  signal \i__carry__1_i_1_n_0\ : STD_LOGIC;
  signal \i__carry__1_i_2_n_0\ : STD_LOGIC;
  signal \i__carry__1_i_3_n_0\ : STD_LOGIC;
  signal \i__carry__1_i_4_n_0\ : STD_LOGIC;
  signal \i__carry__1_i_5_n_0\ : STD_LOGIC;
  signal \i__carry__1_i_6_n_0\ : STD_LOGIC;
  signal \i__carry__1_i_7_n_0\ : STD_LOGIC;
  signal \i__carry__1_i_8_n_0\ : STD_LOGIC;
  signal \i__carry__2_i_1_n_0\ : STD_LOGIC;
  signal \i__carry__2_i_2_n_0\ : STD_LOGIC;
  signal \i__carry__2_i_3_n_0\ : STD_LOGIC;
  signal \i__carry__2_i_4_n_0\ : STD_LOGIC;
  signal \i__carry__2_i_5_n_0\ : STD_LOGIC;
  signal \i__carry__2_i_6_n_0\ : STD_LOGIC;
  signal \i__carry__2_i_7_n_0\ : STD_LOGIC;
  signal \i__carry__2_i_8_n_0\ : STD_LOGIC;
  signal \i__carry_i_1_n_0\ : STD_LOGIC;
  signal \i__carry_i_2_n_0\ : STD_LOGIC;
  signal \i__carry_i_3_n_0\ : STD_LOGIC;
  signal \i__carry_i_4_n_0\ : STD_LOGIC;
  signal \i__carry_i_5_n_0\ : STD_LOGIC;
  signal \i__carry_i_6_n_0\ : STD_LOGIC;
  signal \i__carry_i_7_n_0\ : STD_LOGIC;
  signal \i__carry_i_8_n_0\ : STD_LOGIC;
  signal in2 : STD_LOGIC_VECTOR ( 31 downto 1 );
  signal \j0_carry__0_n_0\ : STD_LOGIC;
  signal \j0_carry__0_n_1\ : STD_LOGIC;
  signal \j0_carry__0_n_2\ : STD_LOGIC;
  signal \j0_carry__0_n_3\ : STD_LOGIC;
  signal \j0_carry__1_n_0\ : STD_LOGIC;
  signal \j0_carry__1_n_1\ : STD_LOGIC;
  signal \j0_carry__1_n_2\ : STD_LOGIC;
  signal \j0_carry__1_n_3\ : STD_LOGIC;
  signal \j0_carry__2_n_0\ : STD_LOGIC;
  signal \j0_carry__2_n_1\ : STD_LOGIC;
  signal \j0_carry__2_n_2\ : STD_LOGIC;
  signal \j0_carry__2_n_3\ : STD_LOGIC;
  signal \j0_carry__3_n_0\ : STD_LOGIC;
  signal \j0_carry__3_n_1\ : STD_LOGIC;
  signal \j0_carry__3_n_2\ : STD_LOGIC;
  signal \j0_carry__3_n_3\ : STD_LOGIC;
  signal \j0_carry__4_n_0\ : STD_LOGIC;
  signal \j0_carry__4_n_1\ : STD_LOGIC;
  signal \j0_carry__4_n_2\ : STD_LOGIC;
  signal \j0_carry__4_n_3\ : STD_LOGIC;
  signal \j0_carry__5_n_0\ : STD_LOGIC;
  signal \j0_carry__5_n_1\ : STD_LOGIC;
  signal \j0_carry__5_n_2\ : STD_LOGIC;
  signal \j0_carry__5_n_3\ : STD_LOGIC;
  signal \j0_carry__6_n_2\ : STD_LOGIC;
  signal \j0_carry__6_n_3\ : STD_LOGIC;
  signal j0_carry_n_0 : STD_LOGIC;
  signal j0_carry_n_1 : STD_LOGIC;
  signal j0_carry_n_2 : STD_LOGIC;
  signal j0_carry_n_3 : STD_LOGIC;
  signal j1 : STD_LOGIC;
  signal \j1_carry__0_i_1_n_0\ : STD_LOGIC;
  signal \j1_carry__0_i_2_n_0\ : STD_LOGIC;
  signal \j1_carry__0_i_3_n_0\ : STD_LOGIC;
  signal \j1_carry__0_i_4_n_0\ : STD_LOGIC;
  signal \j1_carry__0_n_0\ : STD_LOGIC;
  signal \j1_carry__0_n_1\ : STD_LOGIC;
  signal \j1_carry__0_n_2\ : STD_LOGIC;
  signal \j1_carry__0_n_3\ : STD_LOGIC;
  signal \j1_carry__1_i_1_n_0\ : STD_LOGIC;
  signal \j1_carry__1_i_2_n_0\ : STD_LOGIC;
  signal \j1_carry__1_i_3_n_0\ : STD_LOGIC;
  signal \j1_carry__1_n_2\ : STD_LOGIC;
  signal \j1_carry__1_n_3\ : STD_LOGIC;
  signal j1_carry_i_1_n_0 : STD_LOGIC;
  signal j1_carry_i_2_n_0 : STD_LOGIC;
  signal j1_carry_i_3_n_0 : STD_LOGIC;
  signal j1_carry_i_4_n_0 : STD_LOGIC;
  signal j1_carry_n_0 : STD_LOGIC;
  signal j1_carry_n_1 : STD_LOGIC;
  signal j1_carry_n_2 : STD_LOGIC;
  signal j1_carry_n_3 : STD_LOGIC;
  signal \j[0]_i_1_n_0\ : STD_LOGIC;
  signal \j[10]_i_1_n_0\ : STD_LOGIC;
  signal \j[11]_i_1_n_0\ : STD_LOGIC;
  signal \j[12]_i_1_n_0\ : STD_LOGIC;
  signal \j[13]_i_1_n_0\ : STD_LOGIC;
  signal \j[14]_i_1_n_0\ : STD_LOGIC;
  signal \j[15]_i_1_n_0\ : STD_LOGIC;
  signal \j[16]_i_1_n_0\ : STD_LOGIC;
  signal \j[17]_i_1_n_0\ : STD_LOGIC;
  signal \j[18]_i_1_n_0\ : STD_LOGIC;
  signal \j[19]_i_1_n_0\ : STD_LOGIC;
  signal \j[1]_i_1_n_0\ : STD_LOGIC;
  signal \j[20]_i_1_n_0\ : STD_LOGIC;
  signal \j[21]_i_1_n_0\ : STD_LOGIC;
  signal \j[22]_i_1_n_0\ : STD_LOGIC;
  signal \j[23]_i_1_n_0\ : STD_LOGIC;
  signal \j[24]_i_1_n_0\ : STD_LOGIC;
  signal \j[25]_i_1_n_0\ : STD_LOGIC;
  signal \j[26]_i_1_n_0\ : STD_LOGIC;
  signal \j[27]_i_1_n_0\ : STD_LOGIC;
  signal \j[28]_i_1_n_0\ : STD_LOGIC;
  signal \j[29]_i_1_n_0\ : STD_LOGIC;
  signal \j[2]_i_1_n_0\ : STD_LOGIC;
  signal \j[30]_i_1_n_0\ : STD_LOGIC;
  signal \j[31]_i_1_n_0\ : STD_LOGIC;
  signal \j[31]_i_2_n_0\ : STD_LOGIC;
  signal \j[3]_i_1_n_0\ : STD_LOGIC;
  signal \j[4]_i_1_n_0\ : STD_LOGIC;
  signal \j[5]_i_1_n_0\ : STD_LOGIC;
  signal \j[6]_i_1_n_0\ : STD_LOGIC;
  signal \j[7]_i_1_n_0\ : STD_LOGIC;
  signal \j[8]_i_1_n_0\ : STD_LOGIC;
  signal \j[9]_i_1_n_0\ : STD_LOGIC;
  signal \j_reg_n_0_[0]\ : STD_LOGIC;
  signal \j_reg_n_0_[10]\ : STD_LOGIC;
  signal \j_reg_n_0_[11]\ : STD_LOGIC;
  signal \j_reg_n_0_[12]\ : STD_LOGIC;
  signal \j_reg_n_0_[13]\ : STD_LOGIC;
  signal \j_reg_n_0_[14]\ : STD_LOGIC;
  signal \j_reg_n_0_[15]\ : STD_LOGIC;
  signal \j_reg_n_0_[16]\ : STD_LOGIC;
  signal \j_reg_n_0_[17]\ : STD_LOGIC;
  signal \j_reg_n_0_[18]\ : STD_LOGIC;
  signal \j_reg_n_0_[19]\ : STD_LOGIC;
  signal \j_reg_n_0_[1]\ : STD_LOGIC;
  signal \j_reg_n_0_[20]\ : STD_LOGIC;
  signal \j_reg_n_0_[21]\ : STD_LOGIC;
  signal \j_reg_n_0_[22]\ : STD_LOGIC;
  signal \j_reg_n_0_[23]\ : STD_LOGIC;
  signal \j_reg_n_0_[24]\ : STD_LOGIC;
  signal \j_reg_n_0_[25]\ : STD_LOGIC;
  signal \j_reg_n_0_[26]\ : STD_LOGIC;
  signal \j_reg_n_0_[27]\ : STD_LOGIC;
  signal \j_reg_n_0_[28]\ : STD_LOGIC;
  signal \j_reg_n_0_[29]\ : STD_LOGIC;
  signal \j_reg_n_0_[2]\ : STD_LOGIC;
  signal \j_reg_n_0_[30]\ : STD_LOGIC;
  signal \j_reg_n_0_[31]\ : STD_LOGIC;
  signal \j_reg_n_0_[3]\ : STD_LOGIC;
  signal \j_reg_n_0_[4]\ : STD_LOGIC;
  signal \j_reg_n_0_[5]\ : STD_LOGIC;
  signal \j_reg_n_0_[6]\ : STD_LOGIC;
  signal \j_reg_n_0_[7]\ : STD_LOGIC;
  signal \j_reg_n_0_[8]\ : STD_LOGIC;
  signal \j_reg_n_0_[9]\ : STD_LOGIC;
  signal \^max_found\ : STD_LOGIC;
  signal max_found1 : STD_LOGIC;
  signal max_found12_in : STD_LOGIC;
  signal \max_found1_carry__0_i_1_n_0\ : STD_LOGIC;
  signal \max_found1_carry__0_i_2_n_0\ : STD_LOGIC;
  signal \max_found1_carry__0_i_3_n_0\ : STD_LOGIC;
  signal \max_found1_carry__0_i_4_n_0\ : STD_LOGIC;
  signal \max_found1_carry__0_i_5_n_0\ : STD_LOGIC;
  signal \max_found1_carry__0_i_6_n_0\ : STD_LOGIC;
  signal \max_found1_carry__0_i_7_n_0\ : STD_LOGIC;
  signal \max_found1_carry__0_i_8_n_0\ : STD_LOGIC;
  signal \max_found1_carry__0_n_0\ : STD_LOGIC;
  signal \max_found1_carry__0_n_1\ : STD_LOGIC;
  signal \max_found1_carry__0_n_2\ : STD_LOGIC;
  signal \max_found1_carry__0_n_3\ : STD_LOGIC;
  signal \max_found1_carry__1_i_1_n_0\ : STD_LOGIC;
  signal \max_found1_carry__1_i_2_n_0\ : STD_LOGIC;
  signal \max_found1_carry__1_i_3_n_0\ : STD_LOGIC;
  signal \max_found1_carry__1_i_4_n_0\ : STD_LOGIC;
  signal \max_found1_carry__1_i_5_n_0\ : STD_LOGIC;
  signal \max_found1_carry__1_i_6_n_0\ : STD_LOGIC;
  signal \max_found1_carry__1_i_7_n_0\ : STD_LOGIC;
  signal \max_found1_carry__1_i_8_n_0\ : STD_LOGIC;
  signal \max_found1_carry__1_n_0\ : STD_LOGIC;
  signal \max_found1_carry__1_n_1\ : STD_LOGIC;
  signal \max_found1_carry__1_n_2\ : STD_LOGIC;
  signal \max_found1_carry__1_n_3\ : STD_LOGIC;
  signal \max_found1_carry__2_i_1_n_0\ : STD_LOGIC;
  signal \max_found1_carry__2_i_2_n_0\ : STD_LOGIC;
  signal \max_found1_carry__2_i_3_n_0\ : STD_LOGIC;
  signal \max_found1_carry__2_i_4_n_0\ : STD_LOGIC;
  signal \max_found1_carry__2_i_5_n_0\ : STD_LOGIC;
  signal \max_found1_carry__2_i_6_n_0\ : STD_LOGIC;
  signal \max_found1_carry__2_i_7_n_0\ : STD_LOGIC;
  signal \max_found1_carry__2_i_8_n_0\ : STD_LOGIC;
  signal \max_found1_carry__2_n_1\ : STD_LOGIC;
  signal \max_found1_carry__2_n_2\ : STD_LOGIC;
  signal \max_found1_carry__2_n_3\ : STD_LOGIC;
  signal max_found1_carry_i_1_n_0 : STD_LOGIC;
  signal max_found1_carry_i_2_n_0 : STD_LOGIC;
  signal max_found1_carry_i_3_n_0 : STD_LOGIC;
  signal max_found1_carry_i_4_n_0 : STD_LOGIC;
  signal max_found1_carry_i_5_n_0 : STD_LOGIC;
  signal max_found1_carry_i_6_n_0 : STD_LOGIC;
  signal max_found1_carry_i_7_n_0 : STD_LOGIC;
  signal max_found1_carry_i_8_n_0 : STD_LOGIC;
  signal max_found1_carry_n_0 : STD_LOGIC;
  signal max_found1_carry_n_1 : STD_LOGIC;
  signal max_found1_carry_n_2 : STD_LOGIC;
  signal max_found1_carry_n_3 : STD_LOGIC;
  signal \max_found1_inferred__0/i__carry__0_n_0\ : STD_LOGIC;
  signal \max_found1_inferred__0/i__carry__0_n_1\ : STD_LOGIC;
  signal \max_found1_inferred__0/i__carry__0_n_2\ : STD_LOGIC;
  signal \max_found1_inferred__0/i__carry__0_n_3\ : STD_LOGIC;
  signal \max_found1_inferred__0/i__carry__1_n_0\ : STD_LOGIC;
  signal \max_found1_inferred__0/i__carry__1_n_1\ : STD_LOGIC;
  signal \max_found1_inferred__0/i__carry__1_n_2\ : STD_LOGIC;
  signal \max_found1_inferred__0/i__carry__1_n_3\ : STD_LOGIC;
  signal \max_found1_inferred__0/i__carry__2_n_1\ : STD_LOGIC;
  signal \max_found1_inferred__0/i__carry__2_n_2\ : STD_LOGIC;
  signal \max_found1_inferred__0/i__carry__2_n_3\ : STD_LOGIC;
  signal \max_found1_inferred__0/i__carry_n_0\ : STD_LOGIC;
  signal \max_found1_inferred__0/i__carry_n_1\ : STD_LOGIC;
  signal \max_found1_inferred__0/i__carry_n_2\ : STD_LOGIC;
  signal \max_found1_inferred__0/i__carry_n_3\ : STD_LOGIC;
  signal max_found_i_1_n_0 : STD_LOGIC;
  signal \^start_fifo\ : STD_LOGIC;
  signal start_fifo_i_1_n_0 : STD_LOGIC;
  signal \state0_carry__0_i_1_n_0\ : STD_LOGIC;
  signal \state0_carry__0_i_2_n_0\ : STD_LOGIC;
  signal \state0_carry__0_i_3_n_0\ : STD_LOGIC;
  signal \state0_carry__0_i_4_n_0\ : STD_LOGIC;
  signal \state0_carry__0_i_5_n_0\ : STD_LOGIC;
  signal \state0_carry__0_i_6_n_0\ : STD_LOGIC;
  signal \state0_carry__0_i_7_n_0\ : STD_LOGIC;
  signal \state0_carry__0_i_8_n_0\ : STD_LOGIC;
  signal \state0_carry__0_n_0\ : STD_LOGIC;
  signal \state0_carry__0_n_1\ : STD_LOGIC;
  signal \state0_carry__0_n_2\ : STD_LOGIC;
  signal \state0_carry__0_n_3\ : STD_LOGIC;
  signal \state0_carry__1_i_1_n_0\ : STD_LOGIC;
  signal \state0_carry__1_i_2_n_0\ : STD_LOGIC;
  signal \state0_carry__1_i_3_n_0\ : STD_LOGIC;
  signal \state0_carry__1_i_4_n_0\ : STD_LOGIC;
  signal \state0_carry__1_i_5_n_0\ : STD_LOGIC;
  signal \state0_carry__1_i_6_n_0\ : STD_LOGIC;
  signal \state0_carry__1_i_7_n_0\ : STD_LOGIC;
  signal \state0_carry__1_i_8_n_0\ : STD_LOGIC;
  signal \state0_carry__1_n_0\ : STD_LOGIC;
  signal \state0_carry__1_n_1\ : STD_LOGIC;
  signal \state0_carry__1_n_2\ : STD_LOGIC;
  signal \state0_carry__1_n_3\ : STD_LOGIC;
  signal \state0_carry__2_i_1_n_0\ : STD_LOGIC;
  signal \state0_carry__2_i_2_n_0\ : STD_LOGIC;
  signal \state0_carry__2_i_3_n_0\ : STD_LOGIC;
  signal \state0_carry__2_i_4_n_0\ : STD_LOGIC;
  signal \state0_carry__2_i_5_n_0\ : STD_LOGIC;
  signal \state0_carry__2_i_6_n_0\ : STD_LOGIC;
  signal \state0_carry__2_i_7_n_0\ : STD_LOGIC;
  signal \state0_carry__2_i_8_n_0\ : STD_LOGIC;
  signal \state0_carry__2_n_0\ : STD_LOGIC;
  signal \state0_carry__2_n_1\ : STD_LOGIC;
  signal \state0_carry__2_n_2\ : STD_LOGIC;
  signal \state0_carry__2_n_3\ : STD_LOGIC;
  signal state0_carry_i_1_n_0 : STD_LOGIC;
  signal state0_carry_i_2_n_0 : STD_LOGIC;
  signal state0_carry_i_3_n_0 : STD_LOGIC;
  signal state0_carry_i_4_n_0 : STD_LOGIC;
  signal state0_carry_i_5_n_0 : STD_LOGIC;
  signal state0_carry_i_6_n_0 : STD_LOGIC;
  signal state0_carry_i_7_n_0 : STD_LOGIC;
  signal state0_carry_i_8_n_0 : STD_LOGIC;
  signal state0_carry_n_0 : STD_LOGIC;
  signal state0_carry_n_1 : STD_LOGIC;
  signal state0_carry_n_2 : STD_LOGIC;
  signal state0_carry_n_3 : STD_LOGIC;
  signal \state__0\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \val0_reg_n_0_[0]\ : STD_LOGIC;
  signal \val0_reg_n_0_[10]\ : STD_LOGIC;
  signal \val0_reg_n_0_[11]\ : STD_LOGIC;
  signal \val0_reg_n_0_[12]\ : STD_LOGIC;
  signal \val0_reg_n_0_[13]\ : STD_LOGIC;
  signal \val0_reg_n_0_[14]\ : STD_LOGIC;
  signal \val0_reg_n_0_[15]\ : STD_LOGIC;
  signal \val0_reg_n_0_[16]\ : STD_LOGIC;
  signal \val0_reg_n_0_[17]\ : STD_LOGIC;
  signal \val0_reg_n_0_[18]\ : STD_LOGIC;
  signal \val0_reg_n_0_[19]\ : STD_LOGIC;
  signal \val0_reg_n_0_[1]\ : STD_LOGIC;
  signal \val0_reg_n_0_[20]\ : STD_LOGIC;
  signal \val0_reg_n_0_[21]\ : STD_LOGIC;
  signal \val0_reg_n_0_[22]\ : STD_LOGIC;
  signal \val0_reg_n_0_[23]\ : STD_LOGIC;
  signal \val0_reg_n_0_[24]\ : STD_LOGIC;
  signal \val0_reg_n_0_[25]\ : STD_LOGIC;
  signal \val0_reg_n_0_[26]\ : STD_LOGIC;
  signal \val0_reg_n_0_[27]\ : STD_LOGIC;
  signal \val0_reg_n_0_[28]\ : STD_LOGIC;
  signal \val0_reg_n_0_[29]\ : STD_LOGIC;
  signal \val0_reg_n_0_[2]\ : STD_LOGIC;
  signal \val0_reg_n_0_[30]\ : STD_LOGIC;
  signal \val0_reg_n_0_[31]\ : STD_LOGIC;
  signal \val0_reg_n_0_[3]\ : STD_LOGIC;
  signal \val0_reg_n_0_[4]\ : STD_LOGIC;
  signal \val0_reg_n_0_[5]\ : STD_LOGIC;
  signal \val0_reg_n_0_[6]\ : STD_LOGIC;
  signal \val0_reg_n_0_[7]\ : STD_LOGIC;
  signal \val0_reg_n_0_[8]\ : STD_LOGIC;
  signal \val0_reg_n_0_[9]\ : STD_LOGIC;
  signal \val1_reg_n_0_[0]\ : STD_LOGIC;
  signal \val1_reg_n_0_[10]\ : STD_LOGIC;
  signal \val1_reg_n_0_[11]\ : STD_LOGIC;
  signal \val1_reg_n_0_[12]\ : STD_LOGIC;
  signal \val1_reg_n_0_[13]\ : STD_LOGIC;
  signal \val1_reg_n_0_[14]\ : STD_LOGIC;
  signal \val1_reg_n_0_[15]\ : STD_LOGIC;
  signal \val1_reg_n_0_[16]\ : STD_LOGIC;
  signal \val1_reg_n_0_[17]\ : STD_LOGIC;
  signal \val1_reg_n_0_[18]\ : STD_LOGIC;
  signal \val1_reg_n_0_[19]\ : STD_LOGIC;
  signal \val1_reg_n_0_[1]\ : STD_LOGIC;
  signal \val1_reg_n_0_[20]\ : STD_LOGIC;
  signal \val1_reg_n_0_[21]\ : STD_LOGIC;
  signal \val1_reg_n_0_[22]\ : STD_LOGIC;
  signal \val1_reg_n_0_[23]\ : STD_LOGIC;
  signal \val1_reg_n_0_[24]\ : STD_LOGIC;
  signal \val1_reg_n_0_[25]\ : STD_LOGIC;
  signal \val1_reg_n_0_[26]\ : STD_LOGIC;
  signal \val1_reg_n_0_[27]\ : STD_LOGIC;
  signal \val1_reg_n_0_[28]\ : STD_LOGIC;
  signal \val1_reg_n_0_[29]\ : STD_LOGIC;
  signal \val1_reg_n_0_[2]\ : STD_LOGIC;
  signal \val1_reg_n_0_[30]\ : STD_LOGIC;
  signal \val1_reg_n_0_[31]\ : STD_LOGIC;
  signal \val1_reg_n_0_[3]\ : STD_LOGIC;
  signal \val1_reg_n_0_[4]\ : STD_LOGIC;
  signal \val1_reg_n_0_[5]\ : STD_LOGIC;
  signal \val1_reg_n_0_[6]\ : STD_LOGIC;
  signal \val1_reg_n_0_[7]\ : STD_LOGIC;
  signal \val1_reg_n_0_[8]\ : STD_LOGIC;
  signal \val1_reg_n_0_[9]\ : STD_LOGIC;
  signal \val2[31]_i_1_n_0\ : STD_LOGIC;
  signal \val2[31]_i_2_n_0\ : STD_LOGIC;
  signal \val2_reg_n_0_[0]\ : STD_LOGIC;
  signal \val2_reg_n_0_[10]\ : STD_LOGIC;
  signal \val2_reg_n_0_[11]\ : STD_LOGIC;
  signal \val2_reg_n_0_[12]\ : STD_LOGIC;
  signal \val2_reg_n_0_[13]\ : STD_LOGIC;
  signal \val2_reg_n_0_[14]\ : STD_LOGIC;
  signal \val2_reg_n_0_[15]\ : STD_LOGIC;
  signal \val2_reg_n_0_[16]\ : STD_LOGIC;
  signal \val2_reg_n_0_[17]\ : STD_LOGIC;
  signal \val2_reg_n_0_[18]\ : STD_LOGIC;
  signal \val2_reg_n_0_[19]\ : STD_LOGIC;
  signal \val2_reg_n_0_[1]\ : STD_LOGIC;
  signal \val2_reg_n_0_[20]\ : STD_LOGIC;
  signal \val2_reg_n_0_[21]\ : STD_LOGIC;
  signal \val2_reg_n_0_[22]\ : STD_LOGIC;
  signal \val2_reg_n_0_[23]\ : STD_LOGIC;
  signal \val2_reg_n_0_[24]\ : STD_LOGIC;
  signal \val2_reg_n_0_[25]\ : STD_LOGIC;
  signal \val2_reg_n_0_[26]\ : STD_LOGIC;
  signal \val2_reg_n_0_[27]\ : STD_LOGIC;
  signal \val2_reg_n_0_[28]\ : STD_LOGIC;
  signal \val2_reg_n_0_[29]\ : STD_LOGIC;
  signal \val2_reg_n_0_[2]\ : STD_LOGIC;
  signal \val2_reg_n_0_[30]\ : STD_LOGIC;
  signal \val2_reg_n_0_[31]\ : STD_LOGIC;
  signal \val2_reg_n_0_[3]\ : STD_LOGIC;
  signal \val2_reg_n_0_[4]\ : STD_LOGIC;
  signal \val2_reg_n_0_[5]\ : STD_LOGIC;
  signal \val2_reg_n_0_[6]\ : STD_LOGIC;
  signal \val2_reg_n_0_[7]\ : STD_LOGIC;
  signal \val2_reg_n_0_[8]\ : STD_LOGIC;
  signal \val2_reg_n_0_[9]\ : STD_LOGIC;
  signal \NLW_j0_carry__6_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
  signal \NLW_j0_carry__6_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
  signal NLW_j1_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \NLW_j1_carry__0_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \NLW_j1_carry__1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
  signal \NLW_j1_carry__1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal NLW_max_found1_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \NLW_max_found1_carry__0_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \NLW_max_found1_carry__1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \NLW_max_found1_carry__2_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \NLW_max_found1_inferred__0/i__carry_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \NLW_max_found1_inferred__0/i__carry__0_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \NLW_max_found1_inferred__0/i__carry__1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \NLW_max_found1_inferred__0/i__carry__2_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal NLW_state0_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \NLW_state0_carry__0_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \NLW_state0_carry__1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \NLW_state0_carry__2_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  attribute FSM_ENCODED_STATES : string;
  attribute FSM_ENCODED_STATES of \FSM_sequential_state_reg[0]\ : label is "compare:10,idle:00,store:01";
  attribute FSM_ENCODED_STATES of \FSM_sequential_state_reg[1]\ : label is "compare:10,idle:00,store:01";
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \j[0]_i_1\ : label is "soft_lutpair15";
  attribute SOFT_HLUTNM of \j[10]_i_1\ : label is "soft_lutpair10";
  attribute SOFT_HLUTNM of \j[11]_i_1\ : label is "soft_lutpair10";
  attribute SOFT_HLUTNM of \j[12]_i_1\ : label is "soft_lutpair9";
  attribute SOFT_HLUTNM of \j[13]_i_1\ : label is "soft_lutpair9";
  attribute SOFT_HLUTNM of \j[14]_i_1\ : label is "soft_lutpair8";
  attribute SOFT_HLUTNM of \j[15]_i_1\ : label is "soft_lutpair8";
  attribute SOFT_HLUTNM of \j[16]_i_1\ : label is "soft_lutpair7";
  attribute SOFT_HLUTNM of \j[17]_i_1\ : label is "soft_lutpair7";
  attribute SOFT_HLUTNM of \j[18]_i_1\ : label is "soft_lutpair6";
  attribute SOFT_HLUTNM of \j[19]_i_1\ : label is "soft_lutpair6";
  attribute SOFT_HLUTNM of \j[1]_i_1\ : label is "soft_lutpair15";
  attribute SOFT_HLUTNM of \j[20]_i_1\ : label is "soft_lutpair5";
  attribute SOFT_HLUTNM of \j[21]_i_1\ : label is "soft_lutpair5";
  attribute SOFT_HLUTNM of \j[22]_i_1\ : label is "soft_lutpair4";
  attribute SOFT_HLUTNM of \j[23]_i_1\ : label is "soft_lutpair4";
  attribute SOFT_HLUTNM of \j[24]_i_1\ : label is "soft_lutpair3";
  attribute SOFT_HLUTNM of \j[25]_i_1\ : label is "soft_lutpair2";
  attribute SOFT_HLUTNM of \j[26]_i_1\ : label is "soft_lutpair1";
  attribute SOFT_HLUTNM of \j[27]_i_1\ : label is "soft_lutpair0";
  attribute SOFT_HLUTNM of \j[28]_i_1\ : label is "soft_lutpair3";
  attribute SOFT_HLUTNM of \j[29]_i_1\ : label is "soft_lutpair2";
  attribute SOFT_HLUTNM of \j[2]_i_1\ : label is "soft_lutpair14";
  attribute SOFT_HLUTNM of \j[30]_i_1\ : label is "soft_lutpair1";
  attribute SOFT_HLUTNM of \j[31]_i_2\ : label is "soft_lutpair0";
  attribute SOFT_HLUTNM of \j[3]_i_1\ : label is "soft_lutpair14";
  attribute SOFT_HLUTNM of \j[4]_i_1\ : label is "soft_lutpair13";
  attribute SOFT_HLUTNM of \j[5]_i_1\ : label is "soft_lutpair13";
  attribute SOFT_HLUTNM of \j[6]_i_1\ : label is "soft_lutpair12";
  attribute SOFT_HLUTNM of \j[7]_i_1\ : label is "soft_lutpair12";
  attribute SOFT_HLUTNM of \j[8]_i_1\ : label is "soft_lutpair11";
  attribute SOFT_HLUTNM of \j[9]_i_1\ : label is "soft_lutpair11";
begin
  max_found <= \^max_found\;
  start_fifo <= \^start_fifo\;
\FSM_sequential_state[0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FF55CFFFFF55CF00"
    )
        port map (
      I0 => \FSM_sequential_state[0]_i_2_n_0\,
      I1 => j1,
      I2 => \state0_carry__2_n_0\,
      I3 => \state__0\(0),
      I4 => \state__0\(1),
      I5 => start,
      O => \FSM_sequential_state[0]_i_1_n_0\
    );
\FSM_sequential_state[0]_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"8F"
    )
        port map (
      I0 => max_found1,
      I1 => max_found12_in,
      I2 => start,
      O => \FSM_sequential_state[0]_i_2_n_0\
    );
\FSM_sequential_state[1]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F040"
    )
        port map (
      I0 => j1,
      I1 => \state0_carry__2_n_0\,
      I2 => \state__0\(0),
      I3 => \state__0\(1),
      O => \FSM_sequential_state[1]_i_1_n_0\
    );
\FSM_sequential_state_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => '1',
      D => \FSM_sequential_state[0]_i_1_n_0\,
      Q => \state__0\(0),
      R => '0'
    );
\FSM_sequential_state_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => '1',
      D => \FSM_sequential_state[1]_i_1_n_0\,
      Q => \state__0\(1),
      R => '0'
    );
\i__carry__0_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F02"
    )
        port map (
      I0 => \val1_reg_n_0_[14]\,
      I1 => \val0_reg_n_0_[14]\,
      I2 => \val0_reg_n_0_[15]\,
      I3 => \val1_reg_n_0_[15]\,
      O => \i__carry__0_i_1_n_0\
    );
\i__carry__0_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F02"
    )
        port map (
      I0 => \val1_reg_n_0_[12]\,
      I1 => \val0_reg_n_0_[12]\,
      I2 => \val0_reg_n_0_[13]\,
      I3 => \val1_reg_n_0_[13]\,
      O => \i__carry__0_i_2_n_0\
    );
\i__carry__0_i_3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F02"
    )
        port map (
      I0 => \val1_reg_n_0_[10]\,
      I1 => \val0_reg_n_0_[10]\,
      I2 => \val0_reg_n_0_[11]\,
      I3 => \val1_reg_n_0_[11]\,
      O => \i__carry__0_i_3_n_0\
    );
\i__carry__0_i_4\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F02"
    )
        port map (
      I0 => \val1_reg_n_0_[8]\,
      I1 => \val0_reg_n_0_[8]\,
      I2 => \val0_reg_n_0_[9]\,
      I3 => \val1_reg_n_0_[9]\,
      O => \i__carry__0_i_4_n_0\
    );
\i__carry__0_i_5\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => \val1_reg_n_0_[14]\,
      I1 => \val0_reg_n_0_[14]\,
      I2 => \val1_reg_n_0_[15]\,
      I3 => \val0_reg_n_0_[15]\,
      O => \i__carry__0_i_5_n_0\
    );
\i__carry__0_i_6\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => \val1_reg_n_0_[12]\,
      I1 => \val0_reg_n_0_[12]\,
      I2 => \val1_reg_n_0_[13]\,
      I3 => \val0_reg_n_0_[13]\,
      O => \i__carry__0_i_6_n_0\
    );
\i__carry__0_i_7\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => \val1_reg_n_0_[10]\,
      I1 => \val0_reg_n_0_[10]\,
      I2 => \val1_reg_n_0_[11]\,
      I3 => \val0_reg_n_0_[11]\,
      O => \i__carry__0_i_7_n_0\
    );
\i__carry__0_i_8\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => \val1_reg_n_0_[8]\,
      I1 => \val0_reg_n_0_[8]\,
      I2 => \val1_reg_n_0_[9]\,
      I3 => \val0_reg_n_0_[9]\,
      O => \i__carry__0_i_8_n_0\
    );
\i__carry__1_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F02"
    )
        port map (
      I0 => \val1_reg_n_0_[22]\,
      I1 => \val0_reg_n_0_[22]\,
      I2 => \val0_reg_n_0_[23]\,
      I3 => \val1_reg_n_0_[23]\,
      O => \i__carry__1_i_1_n_0\
    );
\i__carry__1_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F02"
    )
        port map (
      I0 => \val1_reg_n_0_[20]\,
      I1 => \val0_reg_n_0_[20]\,
      I2 => \val0_reg_n_0_[21]\,
      I3 => \val1_reg_n_0_[21]\,
      O => \i__carry__1_i_2_n_0\
    );
\i__carry__1_i_3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F02"
    )
        port map (
      I0 => \val1_reg_n_0_[18]\,
      I1 => \val0_reg_n_0_[18]\,
      I2 => \val0_reg_n_0_[19]\,
      I3 => \val1_reg_n_0_[19]\,
      O => \i__carry__1_i_3_n_0\
    );
\i__carry__1_i_4\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F02"
    )
        port map (
      I0 => \val1_reg_n_0_[16]\,
      I1 => \val0_reg_n_0_[16]\,
      I2 => \val0_reg_n_0_[17]\,
      I3 => \val1_reg_n_0_[17]\,
      O => \i__carry__1_i_4_n_0\
    );
\i__carry__1_i_5\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => \val1_reg_n_0_[22]\,
      I1 => \val0_reg_n_0_[22]\,
      I2 => \val1_reg_n_0_[23]\,
      I3 => \val0_reg_n_0_[23]\,
      O => \i__carry__1_i_5_n_0\
    );
\i__carry__1_i_6\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => \val1_reg_n_0_[20]\,
      I1 => \val0_reg_n_0_[20]\,
      I2 => \val1_reg_n_0_[21]\,
      I3 => \val0_reg_n_0_[21]\,
      O => \i__carry__1_i_6_n_0\
    );
\i__carry__1_i_7\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => \val1_reg_n_0_[18]\,
      I1 => \val0_reg_n_0_[18]\,
      I2 => \val1_reg_n_0_[19]\,
      I3 => \val0_reg_n_0_[19]\,
      O => \i__carry__1_i_7_n_0\
    );
\i__carry__1_i_8\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => \val1_reg_n_0_[16]\,
      I1 => \val0_reg_n_0_[16]\,
      I2 => \val1_reg_n_0_[17]\,
      I3 => \val0_reg_n_0_[17]\,
      O => \i__carry__1_i_8_n_0\
    );
\i__carry__2_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F02"
    )
        port map (
      I0 => \val1_reg_n_0_[30]\,
      I1 => \val0_reg_n_0_[30]\,
      I2 => \val1_reg_n_0_[31]\,
      I3 => \val0_reg_n_0_[31]\,
      O => \i__carry__2_i_1_n_0\
    );
\i__carry__2_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F02"
    )
        port map (
      I0 => \val1_reg_n_0_[28]\,
      I1 => \val0_reg_n_0_[28]\,
      I2 => \val0_reg_n_0_[29]\,
      I3 => \val1_reg_n_0_[29]\,
      O => \i__carry__2_i_2_n_0\
    );
\i__carry__2_i_3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F02"
    )
        port map (
      I0 => \val1_reg_n_0_[26]\,
      I1 => \val0_reg_n_0_[26]\,
      I2 => \val0_reg_n_0_[27]\,
      I3 => \val1_reg_n_0_[27]\,
      O => \i__carry__2_i_3_n_0\
    );
\i__carry__2_i_4\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F02"
    )
        port map (
      I0 => \val1_reg_n_0_[24]\,
      I1 => \val0_reg_n_0_[24]\,
      I2 => \val0_reg_n_0_[25]\,
      I3 => \val1_reg_n_0_[25]\,
      O => \i__carry__2_i_4_n_0\
    );
\i__carry__2_i_5\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => \val1_reg_n_0_[30]\,
      I1 => \val0_reg_n_0_[30]\,
      I2 => \val0_reg_n_0_[31]\,
      I3 => \val1_reg_n_0_[31]\,
      O => \i__carry__2_i_5_n_0\
    );
\i__carry__2_i_6\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => \val1_reg_n_0_[28]\,
      I1 => \val0_reg_n_0_[28]\,
      I2 => \val1_reg_n_0_[29]\,
      I3 => \val0_reg_n_0_[29]\,
      O => \i__carry__2_i_6_n_0\
    );
\i__carry__2_i_7\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => \val1_reg_n_0_[26]\,
      I1 => \val0_reg_n_0_[26]\,
      I2 => \val1_reg_n_0_[27]\,
      I3 => \val0_reg_n_0_[27]\,
      O => \i__carry__2_i_7_n_0\
    );
\i__carry__2_i_8\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => \val1_reg_n_0_[24]\,
      I1 => \val0_reg_n_0_[24]\,
      I2 => \val1_reg_n_0_[25]\,
      I3 => \val0_reg_n_0_[25]\,
      O => \i__carry__2_i_8_n_0\
    );
\i__carry_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F02"
    )
        port map (
      I0 => \val1_reg_n_0_[6]\,
      I1 => \val0_reg_n_0_[6]\,
      I2 => \val0_reg_n_0_[7]\,
      I3 => \val1_reg_n_0_[7]\,
      O => \i__carry_i_1_n_0\
    );
\i__carry_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F02"
    )
        port map (
      I0 => \val1_reg_n_0_[4]\,
      I1 => \val0_reg_n_0_[4]\,
      I2 => \val0_reg_n_0_[5]\,
      I3 => \val1_reg_n_0_[5]\,
      O => \i__carry_i_2_n_0\
    );
\i__carry_i_3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F02"
    )
        port map (
      I0 => \val1_reg_n_0_[2]\,
      I1 => \val0_reg_n_0_[2]\,
      I2 => \val0_reg_n_0_[3]\,
      I3 => \val1_reg_n_0_[3]\,
      O => \i__carry_i_3_n_0\
    );
\i__carry_i_4\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F02"
    )
        port map (
      I0 => \val1_reg_n_0_[0]\,
      I1 => \val0_reg_n_0_[0]\,
      I2 => \val0_reg_n_0_[1]\,
      I3 => \val1_reg_n_0_[1]\,
      O => \i__carry_i_4_n_0\
    );
\i__carry_i_5\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => \val1_reg_n_0_[6]\,
      I1 => \val0_reg_n_0_[6]\,
      I2 => \val1_reg_n_0_[7]\,
      I3 => \val0_reg_n_0_[7]\,
      O => \i__carry_i_5_n_0\
    );
\i__carry_i_6\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => \val1_reg_n_0_[4]\,
      I1 => \val0_reg_n_0_[4]\,
      I2 => \val1_reg_n_0_[5]\,
      I3 => \val0_reg_n_0_[5]\,
      O => \i__carry_i_6_n_0\
    );
\i__carry_i_7\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => \val1_reg_n_0_[2]\,
      I1 => \val0_reg_n_0_[2]\,
      I2 => \val1_reg_n_0_[3]\,
      I3 => \val0_reg_n_0_[3]\,
      O => \i__carry_i_7_n_0\
    );
\i__carry_i_8\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => \val1_reg_n_0_[0]\,
      I1 => \val0_reg_n_0_[0]\,
      I2 => \val1_reg_n_0_[1]\,
      I3 => \val0_reg_n_0_[1]\,
      O => \i__carry_i_8_n_0\
    );
j0_carry: unisim.vcomponents.CARRY4
     port map (
      CI => '0',
      CO(3) => j0_carry_n_0,
      CO(2) => j0_carry_n_1,
      CO(1) => j0_carry_n_2,
      CO(0) => j0_carry_n_3,
      CYINIT => \j_reg_n_0_[0]\,
      DI(3 downto 0) => B"0000",
      O(3 downto 0) => in2(4 downto 1),
      S(3) => \j_reg_n_0_[4]\,
      S(2) => \j_reg_n_0_[3]\,
      S(1) => \j_reg_n_0_[2]\,
      S(0) => \j_reg_n_0_[1]\
    );
\j0_carry__0\: unisim.vcomponents.CARRY4
     port map (
      CI => j0_carry_n_0,
      CO(3) => \j0_carry__0_n_0\,
      CO(2) => \j0_carry__0_n_1\,
      CO(1) => \j0_carry__0_n_2\,
      CO(0) => \j0_carry__0_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3 downto 0) => in2(8 downto 5),
      S(3) => \j_reg_n_0_[8]\,
      S(2) => \j_reg_n_0_[7]\,
      S(1) => \j_reg_n_0_[6]\,
      S(0) => \j_reg_n_0_[5]\
    );
\j0_carry__1\: unisim.vcomponents.CARRY4
     port map (
      CI => \j0_carry__0_n_0\,
      CO(3) => \j0_carry__1_n_0\,
      CO(2) => \j0_carry__1_n_1\,
      CO(1) => \j0_carry__1_n_2\,
      CO(0) => \j0_carry__1_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3 downto 0) => in2(12 downto 9),
      S(3) => \j_reg_n_0_[12]\,
      S(2) => \j_reg_n_0_[11]\,
      S(1) => \j_reg_n_0_[10]\,
      S(0) => \j_reg_n_0_[9]\
    );
\j0_carry__2\: unisim.vcomponents.CARRY4
     port map (
      CI => \j0_carry__1_n_0\,
      CO(3) => \j0_carry__2_n_0\,
      CO(2) => \j0_carry__2_n_1\,
      CO(1) => \j0_carry__2_n_2\,
      CO(0) => \j0_carry__2_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3 downto 0) => in2(16 downto 13),
      S(3) => \j_reg_n_0_[16]\,
      S(2) => \j_reg_n_0_[15]\,
      S(1) => \j_reg_n_0_[14]\,
      S(0) => \j_reg_n_0_[13]\
    );
\j0_carry__3\: unisim.vcomponents.CARRY4
     port map (
      CI => \j0_carry__2_n_0\,
      CO(3) => \j0_carry__3_n_0\,
      CO(2) => \j0_carry__3_n_1\,
      CO(1) => \j0_carry__3_n_2\,
      CO(0) => \j0_carry__3_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3 downto 0) => in2(20 downto 17),
      S(3) => \j_reg_n_0_[20]\,
      S(2) => \j_reg_n_0_[19]\,
      S(1) => \j_reg_n_0_[18]\,
      S(0) => \j_reg_n_0_[17]\
    );
\j0_carry__4\: unisim.vcomponents.CARRY4
     port map (
      CI => \j0_carry__3_n_0\,
      CO(3) => \j0_carry__4_n_0\,
      CO(2) => \j0_carry__4_n_1\,
      CO(1) => \j0_carry__4_n_2\,
      CO(0) => \j0_carry__4_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3 downto 0) => in2(24 downto 21),
      S(3) => \j_reg_n_0_[24]\,
      S(2) => \j_reg_n_0_[23]\,
      S(1) => \j_reg_n_0_[22]\,
      S(0) => \j_reg_n_0_[21]\
    );
\j0_carry__5\: unisim.vcomponents.CARRY4
     port map (
      CI => \j0_carry__4_n_0\,
      CO(3) => \j0_carry__5_n_0\,
      CO(2) => \j0_carry__5_n_1\,
      CO(1) => \j0_carry__5_n_2\,
      CO(0) => \j0_carry__5_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3 downto 0) => in2(28 downto 25),
      S(3) => \j_reg_n_0_[28]\,
      S(2) => \j_reg_n_0_[27]\,
      S(1) => \j_reg_n_0_[26]\,
      S(0) => \j_reg_n_0_[25]\
    );
\j0_carry__6\: unisim.vcomponents.CARRY4
     port map (
      CI => \j0_carry__5_n_0\,
      CO(3 downto 2) => \NLW_j0_carry__6_CO_UNCONNECTED\(3 downto 2),
      CO(1) => \j0_carry__6_n_2\,
      CO(0) => \j0_carry__6_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3) => \NLW_j0_carry__6_O_UNCONNECTED\(3),
      O(2 downto 0) => in2(31 downto 29),
      S(3) => '0',
      S(2) => \j_reg_n_0_[31]\,
      S(1) => \j_reg_n_0_[30]\,
      S(0) => \j_reg_n_0_[29]\
    );
j1_carry: unisim.vcomponents.CARRY4
     port map (
      CI => '0',
      CO(3) => j1_carry_n_0,
      CO(2) => j1_carry_n_1,
      CO(1) => j1_carry_n_2,
      CO(0) => j1_carry_n_3,
      CYINIT => '1',
      DI(3 downto 0) => B"0000",
      O(3 downto 0) => NLW_j1_carry_O_UNCONNECTED(3 downto 0),
      S(3) => j1_carry_i_1_n_0,
      S(2) => j1_carry_i_2_n_0,
      S(1) => j1_carry_i_3_n_0,
      S(0) => j1_carry_i_4_n_0
    );
\j1_carry__0\: unisim.vcomponents.CARRY4
     port map (
      CI => j1_carry_n_0,
      CO(3) => \j1_carry__0_n_0\,
      CO(2) => \j1_carry__0_n_1\,
      CO(1) => \j1_carry__0_n_2\,
      CO(0) => \j1_carry__0_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3 downto 0) => \NLW_j1_carry__0_O_UNCONNECTED\(3 downto 0),
      S(3) => \j1_carry__0_i_1_n_0\,
      S(2) => \j1_carry__0_i_2_n_0\,
      S(1) => \j1_carry__0_i_3_n_0\,
      S(0) => \j1_carry__0_i_4_n_0\
    );
\j1_carry__0_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"9009000000009009"
    )
        port map (
      I0 => \val2_reg_n_0_[21]\,
      I1 => val_in(21),
      I2 => val_in(23),
      I3 => \val2_reg_n_0_[23]\,
      I4 => val_in(22),
      I5 => \val2_reg_n_0_[22]\,
      O => \j1_carry__0_i_1_n_0\
    );
\j1_carry__0_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"9009000000009009"
    )
        port map (
      I0 => \val2_reg_n_0_[18]\,
      I1 => val_in(18),
      I2 => val_in(20),
      I3 => \val2_reg_n_0_[20]\,
      I4 => val_in(19),
      I5 => \val2_reg_n_0_[19]\,
      O => \j1_carry__0_i_2_n_0\
    );
\j1_carry__0_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"9009000000009009"
    )
        port map (
      I0 => \val2_reg_n_0_[15]\,
      I1 => val_in(15),
      I2 => val_in(17),
      I3 => \val2_reg_n_0_[17]\,
      I4 => val_in(16),
      I5 => \val2_reg_n_0_[16]\,
      O => \j1_carry__0_i_3_n_0\
    );
\j1_carry__0_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"9009000000009009"
    )
        port map (
      I0 => \val2_reg_n_0_[12]\,
      I1 => val_in(12),
      I2 => val_in(14),
      I3 => \val2_reg_n_0_[14]\,
      I4 => val_in(13),
      I5 => \val2_reg_n_0_[13]\,
      O => \j1_carry__0_i_4_n_0\
    );
\j1_carry__1\: unisim.vcomponents.CARRY4
     port map (
      CI => \j1_carry__0_n_0\,
      CO(3) => \NLW_j1_carry__1_CO_UNCONNECTED\(3),
      CO(2) => j1,
      CO(1) => \j1_carry__1_n_2\,
      CO(0) => \j1_carry__1_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3 downto 0) => \NLW_j1_carry__1_O_UNCONNECTED\(3 downto 0),
      S(3) => '0',
      S(2) => \j1_carry__1_i_1_n_0\,
      S(1) => \j1_carry__1_i_2_n_0\,
      S(0) => \j1_carry__1_i_3_n_0\
    );
\j1_carry__1_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => \val2_reg_n_0_[30]\,
      I1 => val_in(30),
      I2 => \val2_reg_n_0_[31]\,
      I3 => val_in(31),
      O => \j1_carry__1_i_1_n_0\
    );
\j1_carry__1_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"9009000000009009"
    )
        port map (
      I0 => \val2_reg_n_0_[27]\,
      I1 => val_in(27),
      I2 => val_in(29),
      I3 => \val2_reg_n_0_[29]\,
      I4 => val_in(28),
      I5 => \val2_reg_n_0_[28]\,
      O => \j1_carry__1_i_2_n_0\
    );
\j1_carry__1_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"9009000000009009"
    )
        port map (
      I0 => \val2_reg_n_0_[24]\,
      I1 => val_in(24),
      I2 => val_in(26),
      I3 => \val2_reg_n_0_[26]\,
      I4 => val_in(25),
      I5 => \val2_reg_n_0_[25]\,
      O => \j1_carry__1_i_3_n_0\
    );
j1_carry_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"9009000000009009"
    )
        port map (
      I0 => \val2_reg_n_0_[9]\,
      I1 => val_in(9),
      I2 => val_in(11),
      I3 => \val2_reg_n_0_[11]\,
      I4 => val_in(10),
      I5 => \val2_reg_n_0_[10]\,
      O => j1_carry_i_1_n_0
    );
j1_carry_i_2: unisim.vcomponents.LUT6
    generic map(
      INIT => X"9009000000009009"
    )
        port map (
      I0 => \val2_reg_n_0_[6]\,
      I1 => val_in(6),
      I2 => val_in(8),
      I3 => \val2_reg_n_0_[8]\,
      I4 => val_in(7),
      I5 => \val2_reg_n_0_[7]\,
      O => j1_carry_i_2_n_0
    );
j1_carry_i_3: unisim.vcomponents.LUT6
    generic map(
      INIT => X"9009000000009009"
    )
        port map (
      I0 => \val2_reg_n_0_[3]\,
      I1 => val_in(3),
      I2 => val_in(5),
      I3 => \val2_reg_n_0_[5]\,
      I4 => val_in(4),
      I5 => \val2_reg_n_0_[4]\,
      O => j1_carry_i_3_n_0
    );
j1_carry_i_4: unisim.vcomponents.LUT6
    generic map(
      INIT => X"9009000000009009"
    )
        port map (
      I0 => \val2_reg_n_0_[0]\,
      I1 => val_in(0),
      I2 => val_in(2),
      I3 => \val2_reg_n_0_[2]\,
      I4 => val_in(1),
      I5 => \val2_reg_n_0_[1]\,
      O => j1_carry_i_4_n_0
    );
\j[0]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \state__0\(0),
      I1 => \j_reg_n_0_[0]\,
      O => \j[0]_i_1_n_0\
    );
\j[10]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \state__0\(0),
      I1 => in2(10),
      O => \j[10]_i_1_n_0\
    );
\j[11]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \state__0\(0),
      I1 => in2(11),
      O => \j[11]_i_1_n_0\
    );
\j[12]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \state__0\(0),
      I1 => in2(12),
      O => \j[12]_i_1_n_0\
    );
\j[13]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \state__0\(0),
      I1 => in2(13),
      O => \j[13]_i_1_n_0\
    );
\j[14]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \state__0\(0),
      I1 => in2(14),
      O => \j[14]_i_1_n_0\
    );
\j[15]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \state__0\(0),
      I1 => in2(15),
      O => \j[15]_i_1_n_0\
    );
\j[16]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \state__0\(0),
      I1 => in2(16),
      O => \j[16]_i_1_n_0\
    );
\j[17]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \state__0\(0),
      I1 => in2(17),
      O => \j[17]_i_1_n_0\
    );
\j[18]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \state__0\(0),
      I1 => in2(18),
      O => \j[18]_i_1_n_0\
    );
\j[19]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \state__0\(0),
      I1 => in2(19),
      O => \j[19]_i_1_n_0\
    );
\j[1]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \state__0\(0),
      I1 => in2(1),
      O => \j[1]_i_1_n_0\
    );
\j[20]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \state__0\(0),
      I1 => in2(20),
      O => \j[20]_i_1_n_0\
    );
\j[21]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \state__0\(0),
      I1 => in2(21),
      O => \j[21]_i_1_n_0\
    );
\j[22]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \state__0\(0),
      I1 => in2(22),
      O => \j[22]_i_1_n_0\
    );
\j[23]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \state__0\(0),
      I1 => in2(23),
      O => \j[23]_i_1_n_0\
    );
\j[24]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \state__0\(0),
      I1 => in2(24),
      O => \j[24]_i_1_n_0\
    );
\j[25]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \state__0\(0),
      I1 => in2(25),
      O => \j[25]_i_1_n_0\
    );
\j[26]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \state__0\(0),
      I1 => in2(26),
      O => \j[26]_i_1_n_0\
    );
\j[27]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \state__0\(0),
      I1 => in2(27),
      O => \j[27]_i_1_n_0\
    );
\j[28]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \state__0\(0),
      I1 => in2(28),
      O => \j[28]_i_1_n_0\
    );
\j[29]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \state__0\(0),
      I1 => in2(29),
      O => \j[29]_i_1_n_0\
    );
\j[2]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \state__0\(0),
      I1 => in2(2),
      O => \j[2]_i_1_n_0\
    );
\j[30]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \state__0\(0),
      I1 => in2(30),
      O => \j[30]_i_1_n_0\
    );
\j[31]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"15"
    )
        port map (
      I0 => \state__0\(1),
      I1 => j1,
      I2 => \state__0\(0),
      O => \j[31]_i_1_n_0\
    );
\j[31]_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \state__0\(0),
      I1 => in2(31),
      O => \j[31]_i_2_n_0\
    );
\j[3]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \state__0\(0),
      I1 => in2(3),
      O => \j[3]_i_1_n_0\
    );
\j[4]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \state__0\(0),
      I1 => in2(4),
      O => \j[4]_i_1_n_0\
    );
\j[5]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \state__0\(0),
      I1 => in2(5),
      O => \j[5]_i_1_n_0\
    );
\j[6]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \state__0\(0),
      I1 => in2(6),
      O => \j[6]_i_1_n_0\
    );
\j[7]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \state__0\(0),
      I1 => in2(7),
      O => \j[7]_i_1_n_0\
    );
\j[8]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \state__0\(0),
      I1 => in2(8),
      O => \j[8]_i_1_n_0\
    );
\j[9]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \state__0\(0),
      I1 => in2(9),
      O => \j[9]_i_1_n_0\
    );
\j_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => \j[31]_i_1_n_0\,
      D => \j[0]_i_1_n_0\,
      Q => \j_reg_n_0_[0]\,
      R => '0'
    );
\j_reg[10]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => \j[31]_i_1_n_0\,
      D => \j[10]_i_1_n_0\,
      Q => \j_reg_n_0_[10]\,
      R => '0'
    );
\j_reg[11]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => \j[31]_i_1_n_0\,
      D => \j[11]_i_1_n_0\,
      Q => \j_reg_n_0_[11]\,
      R => '0'
    );
\j_reg[12]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => \j[31]_i_1_n_0\,
      D => \j[12]_i_1_n_0\,
      Q => \j_reg_n_0_[12]\,
      R => '0'
    );
\j_reg[13]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => \j[31]_i_1_n_0\,
      D => \j[13]_i_1_n_0\,
      Q => \j_reg_n_0_[13]\,
      R => '0'
    );
\j_reg[14]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => \j[31]_i_1_n_0\,
      D => \j[14]_i_1_n_0\,
      Q => \j_reg_n_0_[14]\,
      R => '0'
    );
\j_reg[15]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => \j[31]_i_1_n_0\,
      D => \j[15]_i_1_n_0\,
      Q => \j_reg_n_0_[15]\,
      R => '0'
    );
\j_reg[16]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => \j[31]_i_1_n_0\,
      D => \j[16]_i_1_n_0\,
      Q => \j_reg_n_0_[16]\,
      R => '0'
    );
\j_reg[17]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => \j[31]_i_1_n_0\,
      D => \j[17]_i_1_n_0\,
      Q => \j_reg_n_0_[17]\,
      R => '0'
    );
\j_reg[18]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => \j[31]_i_1_n_0\,
      D => \j[18]_i_1_n_0\,
      Q => \j_reg_n_0_[18]\,
      R => '0'
    );
\j_reg[19]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => \j[31]_i_1_n_0\,
      D => \j[19]_i_1_n_0\,
      Q => \j_reg_n_0_[19]\,
      R => '0'
    );
\j_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => \j[31]_i_1_n_0\,
      D => \j[1]_i_1_n_0\,
      Q => \j_reg_n_0_[1]\,
      R => '0'
    );
\j_reg[20]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => \j[31]_i_1_n_0\,
      D => \j[20]_i_1_n_0\,
      Q => \j_reg_n_0_[20]\,
      R => '0'
    );
\j_reg[21]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => \j[31]_i_1_n_0\,
      D => \j[21]_i_1_n_0\,
      Q => \j_reg_n_0_[21]\,
      R => '0'
    );
\j_reg[22]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => \j[31]_i_1_n_0\,
      D => \j[22]_i_1_n_0\,
      Q => \j_reg_n_0_[22]\,
      R => '0'
    );
\j_reg[23]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => \j[31]_i_1_n_0\,
      D => \j[23]_i_1_n_0\,
      Q => \j_reg_n_0_[23]\,
      R => '0'
    );
\j_reg[24]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => \j[31]_i_1_n_0\,
      D => \j[24]_i_1_n_0\,
      Q => \j_reg_n_0_[24]\,
      R => '0'
    );
\j_reg[25]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => \j[31]_i_1_n_0\,
      D => \j[25]_i_1_n_0\,
      Q => \j_reg_n_0_[25]\,
      R => '0'
    );
\j_reg[26]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => \j[31]_i_1_n_0\,
      D => \j[26]_i_1_n_0\,
      Q => \j_reg_n_0_[26]\,
      R => '0'
    );
\j_reg[27]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => \j[31]_i_1_n_0\,
      D => \j[27]_i_1_n_0\,
      Q => \j_reg_n_0_[27]\,
      R => '0'
    );
\j_reg[28]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => \j[31]_i_1_n_0\,
      D => \j[28]_i_1_n_0\,
      Q => \j_reg_n_0_[28]\,
      R => '0'
    );
\j_reg[29]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => \j[31]_i_1_n_0\,
      D => \j[29]_i_1_n_0\,
      Q => \j_reg_n_0_[29]\,
      R => '0'
    );
\j_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => \j[31]_i_1_n_0\,
      D => \j[2]_i_1_n_0\,
      Q => \j_reg_n_0_[2]\,
      R => '0'
    );
\j_reg[30]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => \j[31]_i_1_n_0\,
      D => \j[30]_i_1_n_0\,
      Q => \j_reg_n_0_[30]\,
      R => '0'
    );
\j_reg[31]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => \j[31]_i_1_n_0\,
      D => \j[31]_i_2_n_0\,
      Q => \j_reg_n_0_[31]\,
      R => '0'
    );
\j_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => \j[31]_i_1_n_0\,
      D => \j[3]_i_1_n_0\,
      Q => \j_reg_n_0_[3]\,
      R => '0'
    );
\j_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => \j[31]_i_1_n_0\,
      D => \j[4]_i_1_n_0\,
      Q => \j_reg_n_0_[4]\,
      R => '0'
    );
\j_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => \j[31]_i_1_n_0\,
      D => \j[5]_i_1_n_0\,
      Q => \j_reg_n_0_[5]\,
      R => '0'
    );
\j_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => \j[31]_i_1_n_0\,
      D => \j[6]_i_1_n_0\,
      Q => \j_reg_n_0_[6]\,
      R => '0'
    );
\j_reg[7]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => \j[31]_i_1_n_0\,
      D => \j[7]_i_1_n_0\,
      Q => \j_reg_n_0_[7]\,
      R => '0'
    );
\j_reg[8]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => \j[31]_i_1_n_0\,
      D => \j[8]_i_1_n_0\,
      Q => \j_reg_n_0_[8]\,
      R => '0'
    );
\j_reg[9]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => \j[31]_i_1_n_0\,
      D => \j[9]_i_1_n_0\,
      Q => \j_reg_n_0_[9]\,
      R => '0'
    );
max_found1_carry: unisim.vcomponents.CARRY4
     port map (
      CI => '0',
      CO(3) => max_found1_carry_n_0,
      CO(2) => max_found1_carry_n_1,
      CO(1) => max_found1_carry_n_2,
      CO(0) => max_found1_carry_n_3,
      CYINIT => '0',
      DI(3) => max_found1_carry_i_1_n_0,
      DI(2) => max_found1_carry_i_2_n_0,
      DI(1) => max_found1_carry_i_3_n_0,
      DI(0) => max_found1_carry_i_4_n_0,
      O(3 downto 0) => NLW_max_found1_carry_O_UNCONNECTED(3 downto 0),
      S(3) => max_found1_carry_i_5_n_0,
      S(2) => max_found1_carry_i_6_n_0,
      S(1) => max_found1_carry_i_7_n_0,
      S(0) => max_found1_carry_i_8_n_0
    );
\max_found1_carry__0\: unisim.vcomponents.CARRY4
     port map (
      CI => max_found1_carry_n_0,
      CO(3) => \max_found1_carry__0_n_0\,
      CO(2) => \max_found1_carry__0_n_1\,
      CO(1) => \max_found1_carry__0_n_2\,
      CO(0) => \max_found1_carry__0_n_3\,
      CYINIT => '0',
      DI(3) => \max_found1_carry__0_i_1_n_0\,
      DI(2) => \max_found1_carry__0_i_2_n_0\,
      DI(1) => \max_found1_carry__0_i_3_n_0\,
      DI(0) => \max_found1_carry__0_i_4_n_0\,
      O(3 downto 0) => \NLW_max_found1_carry__0_O_UNCONNECTED\(3 downto 0),
      S(3) => \max_found1_carry__0_i_5_n_0\,
      S(2) => \max_found1_carry__0_i_6_n_0\,
      S(1) => \max_found1_carry__0_i_7_n_0\,
      S(0) => \max_found1_carry__0_i_8_n_0\
    );
\max_found1_carry__0_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F02"
    )
        port map (
      I0 => \val1_reg_n_0_[14]\,
      I1 => \val2_reg_n_0_[14]\,
      I2 => \val2_reg_n_0_[15]\,
      I3 => \val1_reg_n_0_[15]\,
      O => \max_found1_carry__0_i_1_n_0\
    );
\max_found1_carry__0_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F02"
    )
        port map (
      I0 => \val1_reg_n_0_[12]\,
      I1 => \val2_reg_n_0_[12]\,
      I2 => \val2_reg_n_0_[13]\,
      I3 => \val1_reg_n_0_[13]\,
      O => \max_found1_carry__0_i_2_n_0\
    );
\max_found1_carry__0_i_3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F02"
    )
        port map (
      I0 => \val1_reg_n_0_[10]\,
      I1 => \val2_reg_n_0_[10]\,
      I2 => \val2_reg_n_0_[11]\,
      I3 => \val1_reg_n_0_[11]\,
      O => \max_found1_carry__0_i_3_n_0\
    );
\max_found1_carry__0_i_4\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F02"
    )
        port map (
      I0 => \val1_reg_n_0_[8]\,
      I1 => \val2_reg_n_0_[8]\,
      I2 => \val2_reg_n_0_[9]\,
      I3 => \val1_reg_n_0_[9]\,
      O => \max_found1_carry__0_i_4_n_0\
    );
\max_found1_carry__0_i_5\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => \val1_reg_n_0_[14]\,
      I1 => \val2_reg_n_0_[14]\,
      I2 => \val1_reg_n_0_[15]\,
      I3 => \val2_reg_n_0_[15]\,
      O => \max_found1_carry__0_i_5_n_0\
    );
\max_found1_carry__0_i_6\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => \val1_reg_n_0_[12]\,
      I1 => \val2_reg_n_0_[12]\,
      I2 => \val1_reg_n_0_[13]\,
      I3 => \val2_reg_n_0_[13]\,
      O => \max_found1_carry__0_i_6_n_0\
    );
\max_found1_carry__0_i_7\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => \val1_reg_n_0_[10]\,
      I1 => \val2_reg_n_0_[10]\,
      I2 => \val1_reg_n_0_[11]\,
      I3 => \val2_reg_n_0_[11]\,
      O => \max_found1_carry__0_i_7_n_0\
    );
\max_found1_carry__0_i_8\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => \val1_reg_n_0_[8]\,
      I1 => \val2_reg_n_0_[8]\,
      I2 => \val1_reg_n_0_[9]\,
      I3 => \val2_reg_n_0_[9]\,
      O => \max_found1_carry__0_i_8_n_0\
    );
\max_found1_carry__1\: unisim.vcomponents.CARRY4
     port map (
      CI => \max_found1_carry__0_n_0\,
      CO(3) => \max_found1_carry__1_n_0\,
      CO(2) => \max_found1_carry__1_n_1\,
      CO(1) => \max_found1_carry__1_n_2\,
      CO(0) => \max_found1_carry__1_n_3\,
      CYINIT => '0',
      DI(3) => \max_found1_carry__1_i_1_n_0\,
      DI(2) => \max_found1_carry__1_i_2_n_0\,
      DI(1) => \max_found1_carry__1_i_3_n_0\,
      DI(0) => \max_found1_carry__1_i_4_n_0\,
      O(3 downto 0) => \NLW_max_found1_carry__1_O_UNCONNECTED\(3 downto 0),
      S(3) => \max_found1_carry__1_i_5_n_0\,
      S(2) => \max_found1_carry__1_i_6_n_0\,
      S(1) => \max_found1_carry__1_i_7_n_0\,
      S(0) => \max_found1_carry__1_i_8_n_0\
    );
\max_found1_carry__1_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F02"
    )
        port map (
      I0 => \val1_reg_n_0_[22]\,
      I1 => \val2_reg_n_0_[22]\,
      I2 => \val2_reg_n_0_[23]\,
      I3 => \val1_reg_n_0_[23]\,
      O => \max_found1_carry__1_i_1_n_0\
    );
\max_found1_carry__1_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F02"
    )
        port map (
      I0 => \val1_reg_n_0_[20]\,
      I1 => \val2_reg_n_0_[20]\,
      I2 => \val2_reg_n_0_[21]\,
      I3 => \val1_reg_n_0_[21]\,
      O => \max_found1_carry__1_i_2_n_0\
    );
\max_found1_carry__1_i_3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F02"
    )
        port map (
      I0 => \val1_reg_n_0_[18]\,
      I1 => \val2_reg_n_0_[18]\,
      I2 => \val2_reg_n_0_[19]\,
      I3 => \val1_reg_n_0_[19]\,
      O => \max_found1_carry__1_i_3_n_0\
    );
\max_found1_carry__1_i_4\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F02"
    )
        port map (
      I0 => \val1_reg_n_0_[16]\,
      I1 => \val2_reg_n_0_[16]\,
      I2 => \val2_reg_n_0_[17]\,
      I3 => \val1_reg_n_0_[17]\,
      O => \max_found1_carry__1_i_4_n_0\
    );
\max_found1_carry__1_i_5\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => \val1_reg_n_0_[22]\,
      I1 => \val2_reg_n_0_[22]\,
      I2 => \val1_reg_n_0_[23]\,
      I3 => \val2_reg_n_0_[23]\,
      O => \max_found1_carry__1_i_5_n_0\
    );
\max_found1_carry__1_i_6\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => \val1_reg_n_0_[20]\,
      I1 => \val2_reg_n_0_[20]\,
      I2 => \val1_reg_n_0_[21]\,
      I3 => \val2_reg_n_0_[21]\,
      O => \max_found1_carry__1_i_6_n_0\
    );
\max_found1_carry__1_i_7\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => \val1_reg_n_0_[18]\,
      I1 => \val2_reg_n_0_[18]\,
      I2 => \val1_reg_n_0_[19]\,
      I3 => \val2_reg_n_0_[19]\,
      O => \max_found1_carry__1_i_7_n_0\
    );
\max_found1_carry__1_i_8\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => \val1_reg_n_0_[16]\,
      I1 => \val2_reg_n_0_[16]\,
      I2 => \val1_reg_n_0_[17]\,
      I3 => \val2_reg_n_0_[17]\,
      O => \max_found1_carry__1_i_8_n_0\
    );
\max_found1_carry__2\: unisim.vcomponents.CARRY4
     port map (
      CI => \max_found1_carry__1_n_0\,
      CO(3) => max_found1,
      CO(2) => \max_found1_carry__2_n_1\,
      CO(1) => \max_found1_carry__2_n_2\,
      CO(0) => \max_found1_carry__2_n_3\,
      CYINIT => '0',
      DI(3) => \max_found1_carry__2_i_1_n_0\,
      DI(2) => \max_found1_carry__2_i_2_n_0\,
      DI(1) => \max_found1_carry__2_i_3_n_0\,
      DI(0) => \max_found1_carry__2_i_4_n_0\,
      O(3 downto 0) => \NLW_max_found1_carry__2_O_UNCONNECTED\(3 downto 0),
      S(3) => \max_found1_carry__2_i_5_n_0\,
      S(2) => \max_found1_carry__2_i_6_n_0\,
      S(1) => \max_found1_carry__2_i_7_n_0\,
      S(0) => \max_found1_carry__2_i_8_n_0\
    );
\max_found1_carry__2_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F02"
    )
        port map (
      I0 => \val1_reg_n_0_[30]\,
      I1 => \val2_reg_n_0_[30]\,
      I2 => \val1_reg_n_0_[31]\,
      I3 => \val2_reg_n_0_[31]\,
      O => \max_found1_carry__2_i_1_n_0\
    );
\max_found1_carry__2_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F02"
    )
        port map (
      I0 => \val1_reg_n_0_[28]\,
      I1 => \val2_reg_n_0_[28]\,
      I2 => \val2_reg_n_0_[29]\,
      I3 => \val1_reg_n_0_[29]\,
      O => \max_found1_carry__2_i_2_n_0\
    );
\max_found1_carry__2_i_3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F02"
    )
        port map (
      I0 => \val1_reg_n_0_[26]\,
      I1 => \val2_reg_n_0_[26]\,
      I2 => \val2_reg_n_0_[27]\,
      I3 => \val1_reg_n_0_[27]\,
      O => \max_found1_carry__2_i_3_n_0\
    );
\max_found1_carry__2_i_4\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F02"
    )
        port map (
      I0 => \val1_reg_n_0_[24]\,
      I1 => \val2_reg_n_0_[24]\,
      I2 => \val2_reg_n_0_[25]\,
      I3 => \val1_reg_n_0_[25]\,
      O => \max_found1_carry__2_i_4_n_0\
    );
\max_found1_carry__2_i_5\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => \val1_reg_n_0_[30]\,
      I1 => \val2_reg_n_0_[30]\,
      I2 => \val2_reg_n_0_[31]\,
      I3 => \val1_reg_n_0_[31]\,
      O => \max_found1_carry__2_i_5_n_0\
    );
\max_found1_carry__2_i_6\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => \val1_reg_n_0_[28]\,
      I1 => \val2_reg_n_0_[28]\,
      I2 => \val1_reg_n_0_[29]\,
      I3 => \val2_reg_n_0_[29]\,
      O => \max_found1_carry__2_i_6_n_0\
    );
\max_found1_carry__2_i_7\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => \val1_reg_n_0_[26]\,
      I1 => \val2_reg_n_0_[26]\,
      I2 => \val1_reg_n_0_[27]\,
      I3 => \val2_reg_n_0_[27]\,
      O => \max_found1_carry__2_i_7_n_0\
    );
\max_found1_carry__2_i_8\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => \val1_reg_n_0_[24]\,
      I1 => \val2_reg_n_0_[24]\,
      I2 => \val1_reg_n_0_[25]\,
      I3 => \val2_reg_n_0_[25]\,
      O => \max_found1_carry__2_i_8_n_0\
    );
max_found1_carry_i_1: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F02"
    )
        port map (
      I0 => \val1_reg_n_0_[6]\,
      I1 => \val2_reg_n_0_[6]\,
      I2 => \val2_reg_n_0_[7]\,
      I3 => \val1_reg_n_0_[7]\,
      O => max_found1_carry_i_1_n_0
    );
max_found1_carry_i_2: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F02"
    )
        port map (
      I0 => \val1_reg_n_0_[4]\,
      I1 => \val2_reg_n_0_[4]\,
      I2 => \val2_reg_n_0_[5]\,
      I3 => \val1_reg_n_0_[5]\,
      O => max_found1_carry_i_2_n_0
    );
max_found1_carry_i_3: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F02"
    )
        port map (
      I0 => \val1_reg_n_0_[2]\,
      I1 => \val2_reg_n_0_[2]\,
      I2 => \val2_reg_n_0_[3]\,
      I3 => \val1_reg_n_0_[3]\,
      O => max_found1_carry_i_3_n_0
    );
max_found1_carry_i_4: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F02"
    )
        port map (
      I0 => \val1_reg_n_0_[0]\,
      I1 => \val2_reg_n_0_[0]\,
      I2 => \val2_reg_n_0_[1]\,
      I3 => \val1_reg_n_0_[1]\,
      O => max_found1_carry_i_4_n_0
    );
max_found1_carry_i_5: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => \val1_reg_n_0_[6]\,
      I1 => \val2_reg_n_0_[6]\,
      I2 => \val1_reg_n_0_[7]\,
      I3 => \val2_reg_n_0_[7]\,
      O => max_found1_carry_i_5_n_0
    );
max_found1_carry_i_6: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => \val1_reg_n_0_[4]\,
      I1 => \val2_reg_n_0_[4]\,
      I2 => \val1_reg_n_0_[5]\,
      I3 => \val2_reg_n_0_[5]\,
      O => max_found1_carry_i_6_n_0
    );
max_found1_carry_i_7: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => \val1_reg_n_0_[2]\,
      I1 => \val2_reg_n_0_[2]\,
      I2 => \val1_reg_n_0_[3]\,
      I3 => \val2_reg_n_0_[3]\,
      O => max_found1_carry_i_7_n_0
    );
max_found1_carry_i_8: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => \val1_reg_n_0_[0]\,
      I1 => \val2_reg_n_0_[0]\,
      I2 => \val1_reg_n_0_[1]\,
      I3 => \val2_reg_n_0_[1]\,
      O => max_found1_carry_i_8_n_0
    );
\max_found1_inferred__0/i__carry\: unisim.vcomponents.CARRY4
     port map (
      CI => '0',
      CO(3) => \max_found1_inferred__0/i__carry_n_0\,
      CO(2) => \max_found1_inferred__0/i__carry_n_1\,
      CO(1) => \max_found1_inferred__0/i__carry_n_2\,
      CO(0) => \max_found1_inferred__0/i__carry_n_3\,
      CYINIT => '0',
      DI(3) => \i__carry_i_1_n_0\,
      DI(2) => \i__carry_i_2_n_0\,
      DI(1) => \i__carry_i_3_n_0\,
      DI(0) => \i__carry_i_4_n_0\,
      O(3 downto 0) => \NLW_max_found1_inferred__0/i__carry_O_UNCONNECTED\(3 downto 0),
      S(3) => \i__carry_i_5_n_0\,
      S(2) => \i__carry_i_6_n_0\,
      S(1) => \i__carry_i_7_n_0\,
      S(0) => \i__carry_i_8_n_0\
    );
\max_found1_inferred__0/i__carry__0\: unisim.vcomponents.CARRY4
     port map (
      CI => \max_found1_inferred__0/i__carry_n_0\,
      CO(3) => \max_found1_inferred__0/i__carry__0_n_0\,
      CO(2) => \max_found1_inferred__0/i__carry__0_n_1\,
      CO(1) => \max_found1_inferred__0/i__carry__0_n_2\,
      CO(0) => \max_found1_inferred__0/i__carry__0_n_3\,
      CYINIT => '0',
      DI(3) => \i__carry__0_i_1_n_0\,
      DI(2) => \i__carry__0_i_2_n_0\,
      DI(1) => \i__carry__0_i_3_n_0\,
      DI(0) => \i__carry__0_i_4_n_0\,
      O(3 downto 0) => \NLW_max_found1_inferred__0/i__carry__0_O_UNCONNECTED\(3 downto 0),
      S(3) => \i__carry__0_i_5_n_0\,
      S(2) => \i__carry__0_i_6_n_0\,
      S(1) => \i__carry__0_i_7_n_0\,
      S(0) => \i__carry__0_i_8_n_0\
    );
\max_found1_inferred__0/i__carry__1\: unisim.vcomponents.CARRY4
     port map (
      CI => \max_found1_inferred__0/i__carry__0_n_0\,
      CO(3) => \max_found1_inferred__0/i__carry__1_n_0\,
      CO(2) => \max_found1_inferred__0/i__carry__1_n_1\,
      CO(1) => \max_found1_inferred__0/i__carry__1_n_2\,
      CO(0) => \max_found1_inferred__0/i__carry__1_n_3\,
      CYINIT => '0',
      DI(3) => \i__carry__1_i_1_n_0\,
      DI(2) => \i__carry__1_i_2_n_0\,
      DI(1) => \i__carry__1_i_3_n_0\,
      DI(0) => \i__carry__1_i_4_n_0\,
      O(3 downto 0) => \NLW_max_found1_inferred__0/i__carry__1_O_UNCONNECTED\(3 downto 0),
      S(3) => \i__carry__1_i_5_n_0\,
      S(2) => \i__carry__1_i_6_n_0\,
      S(1) => \i__carry__1_i_7_n_0\,
      S(0) => \i__carry__1_i_8_n_0\
    );
\max_found1_inferred__0/i__carry__2\: unisim.vcomponents.CARRY4
     port map (
      CI => \max_found1_inferred__0/i__carry__1_n_0\,
      CO(3) => max_found12_in,
      CO(2) => \max_found1_inferred__0/i__carry__2_n_1\,
      CO(1) => \max_found1_inferred__0/i__carry__2_n_2\,
      CO(0) => \max_found1_inferred__0/i__carry__2_n_3\,
      CYINIT => '0',
      DI(3) => \i__carry__2_i_1_n_0\,
      DI(2) => \i__carry__2_i_2_n_0\,
      DI(1) => \i__carry__2_i_3_n_0\,
      DI(0) => \i__carry__2_i_4_n_0\,
      O(3 downto 0) => \NLW_max_found1_inferred__0/i__carry__2_O_UNCONNECTED\(3 downto 0),
      S(3) => \i__carry__2_i_5_n_0\,
      S(2) => \i__carry__2_i_6_n_0\,
      S(1) => \i__carry__2_i_7_n_0\,
      S(0) => \i__carry__2_i_8_n_0\
    );
max_found_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFAAAA40000000"
    )
        port map (
      I0 => \state__0\(0),
      I1 => start,
      I2 => max_found1,
      I3 => max_found12_in,
      I4 => \state__0\(1),
      I5 => \^max_found\,
      O => max_found_i_1_n_0
    );
max_found_reg: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => '1',
      D => max_found_i_1_n_0,
      Q => \^max_found\,
      R => '0'
    );
start_fifo_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFAAAA40550000"
    )
        port map (
      I0 => \state__0\(0),
      I1 => max_found1,
      I2 => max_found12_in,
      I3 => start,
      I4 => \state__0\(1),
      I5 => \^start_fifo\,
      O => start_fifo_i_1_n_0
    );
start_fifo_reg: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => '1',
      D => start_fifo_i_1_n_0,
      Q => \^start_fifo\,
      R => '0'
    );
state0_carry: unisim.vcomponents.CARRY4
     port map (
      CI => '0',
      CO(3) => state0_carry_n_0,
      CO(2) => state0_carry_n_1,
      CO(1) => state0_carry_n_2,
      CO(0) => state0_carry_n_3,
      CYINIT => '0',
      DI(3) => state0_carry_i_1_n_0,
      DI(2) => state0_carry_i_2_n_0,
      DI(1) => state0_carry_i_3_n_0,
      DI(0) => state0_carry_i_4_n_0,
      O(3 downto 0) => NLW_state0_carry_O_UNCONNECTED(3 downto 0),
      S(3) => state0_carry_i_5_n_0,
      S(2) => state0_carry_i_6_n_0,
      S(1) => state0_carry_i_7_n_0,
      S(0) => state0_carry_i_8_n_0
    );
\state0_carry__0\: unisim.vcomponents.CARRY4
     port map (
      CI => state0_carry_n_0,
      CO(3) => \state0_carry__0_n_0\,
      CO(2) => \state0_carry__0_n_1\,
      CO(1) => \state0_carry__0_n_2\,
      CO(0) => \state0_carry__0_n_3\,
      CYINIT => '0',
      DI(3) => \state0_carry__0_i_1_n_0\,
      DI(2) => \state0_carry__0_i_2_n_0\,
      DI(1) => \state0_carry__0_i_3_n_0\,
      DI(0) => \state0_carry__0_i_4_n_0\,
      O(3 downto 0) => \NLW_state0_carry__0_O_UNCONNECTED\(3 downto 0),
      S(3) => \state0_carry__0_i_5_n_0\,
      S(2) => \state0_carry__0_i_6_n_0\,
      S(1) => \state0_carry__0_i_7_n_0\,
      S(0) => \state0_carry__0_i_8_n_0\
    );
\state0_carry__0_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => in2(14),
      I1 => in2(15),
      O => \state0_carry__0_i_1_n_0\
    );
\state0_carry__0_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => in2(12),
      I1 => in2(13),
      O => \state0_carry__0_i_2_n_0\
    );
\state0_carry__0_i_3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => in2(10),
      I1 => in2(11),
      O => \state0_carry__0_i_3_n_0\
    );
\state0_carry__0_i_4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => in2(8),
      I1 => in2(9),
      O => \state0_carry__0_i_4_n_0\
    );
\state0_carry__0_i_5\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => in2(14),
      I1 => in2(15),
      O => \state0_carry__0_i_5_n_0\
    );
\state0_carry__0_i_6\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => in2(12),
      I1 => in2(13),
      O => \state0_carry__0_i_6_n_0\
    );
\state0_carry__0_i_7\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => in2(10),
      I1 => in2(11),
      O => \state0_carry__0_i_7_n_0\
    );
\state0_carry__0_i_8\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => in2(8),
      I1 => in2(9),
      O => \state0_carry__0_i_8_n_0\
    );
\state0_carry__1\: unisim.vcomponents.CARRY4
     port map (
      CI => \state0_carry__0_n_0\,
      CO(3) => \state0_carry__1_n_0\,
      CO(2) => \state0_carry__1_n_1\,
      CO(1) => \state0_carry__1_n_2\,
      CO(0) => \state0_carry__1_n_3\,
      CYINIT => '0',
      DI(3) => \state0_carry__1_i_1_n_0\,
      DI(2) => \state0_carry__1_i_2_n_0\,
      DI(1) => \state0_carry__1_i_3_n_0\,
      DI(0) => \state0_carry__1_i_4_n_0\,
      O(3 downto 0) => \NLW_state0_carry__1_O_UNCONNECTED\(3 downto 0),
      S(3) => \state0_carry__1_i_5_n_0\,
      S(2) => \state0_carry__1_i_6_n_0\,
      S(1) => \state0_carry__1_i_7_n_0\,
      S(0) => \state0_carry__1_i_8_n_0\
    );
\state0_carry__1_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => in2(22),
      I1 => in2(23),
      O => \state0_carry__1_i_1_n_0\
    );
\state0_carry__1_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => in2(20),
      I1 => in2(21),
      O => \state0_carry__1_i_2_n_0\
    );
\state0_carry__1_i_3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => in2(18),
      I1 => in2(19),
      O => \state0_carry__1_i_3_n_0\
    );
\state0_carry__1_i_4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => in2(16),
      I1 => in2(17),
      O => \state0_carry__1_i_4_n_0\
    );
\state0_carry__1_i_5\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => in2(22),
      I1 => in2(23),
      O => \state0_carry__1_i_5_n_0\
    );
\state0_carry__1_i_6\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => in2(20),
      I1 => in2(21),
      O => \state0_carry__1_i_6_n_0\
    );
\state0_carry__1_i_7\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => in2(18),
      I1 => in2(19),
      O => \state0_carry__1_i_7_n_0\
    );
\state0_carry__1_i_8\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => in2(16),
      I1 => in2(17),
      O => \state0_carry__1_i_8_n_0\
    );
\state0_carry__2\: unisim.vcomponents.CARRY4
     port map (
      CI => \state0_carry__1_n_0\,
      CO(3) => \state0_carry__2_n_0\,
      CO(2) => \state0_carry__2_n_1\,
      CO(1) => \state0_carry__2_n_2\,
      CO(0) => \state0_carry__2_n_3\,
      CYINIT => '0',
      DI(3) => \state0_carry__2_i_1_n_0\,
      DI(2) => \state0_carry__2_i_2_n_0\,
      DI(1) => \state0_carry__2_i_3_n_0\,
      DI(0) => \state0_carry__2_i_4_n_0\,
      O(3 downto 0) => \NLW_state0_carry__2_O_UNCONNECTED\(3 downto 0),
      S(3) => \state0_carry__2_i_5_n_0\,
      S(2) => \state0_carry__2_i_6_n_0\,
      S(1) => \state0_carry__2_i_7_n_0\,
      S(0) => \state0_carry__2_i_8_n_0\
    );
\state0_carry__2_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => in2(30),
      I1 => in2(31),
      O => \state0_carry__2_i_1_n_0\
    );
\state0_carry__2_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => in2(28),
      I1 => in2(29),
      O => \state0_carry__2_i_2_n_0\
    );
\state0_carry__2_i_3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => in2(26),
      I1 => in2(27),
      O => \state0_carry__2_i_3_n_0\
    );
\state0_carry__2_i_4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => in2(24),
      I1 => in2(25),
      O => \state0_carry__2_i_4_n_0\
    );
\state0_carry__2_i_5\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => in2(30),
      I1 => in2(31),
      O => \state0_carry__2_i_5_n_0\
    );
\state0_carry__2_i_6\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => in2(28),
      I1 => in2(29),
      O => \state0_carry__2_i_6_n_0\
    );
\state0_carry__2_i_7\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => in2(26),
      I1 => in2(27),
      O => \state0_carry__2_i_7_n_0\
    );
\state0_carry__2_i_8\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => in2(24),
      I1 => in2(25),
      O => \state0_carry__2_i_8_n_0\
    );
state0_carry_i_1: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => in2(6),
      I1 => in2(7),
      O => state0_carry_i_1_n_0
    );
state0_carry_i_2: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => in2(4),
      I1 => in2(5),
      O => state0_carry_i_2_n_0
    );
state0_carry_i_3: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => in2(2),
      I1 => in2(3),
      O => state0_carry_i_3_n_0
    );
state0_carry_i_4: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => in2(1),
      I1 => \j_reg_n_0_[0]\,
      O => state0_carry_i_4_n_0
    );
state0_carry_i_5: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => in2(6),
      I1 => in2(7),
      O => state0_carry_i_5_n_0
    );
state0_carry_i_6: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => in2(4),
      I1 => in2(5),
      O => state0_carry_i_6_n_0
    );
state0_carry_i_7: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => in2(2),
      I1 => in2(3),
      O => state0_carry_i_7_n_0
    );
state0_carry_i_8: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \j_reg_n_0_[0]\,
      I1 => in2(1),
      O => state0_carry_i_8_n_0
    );
\val0_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => \val2[31]_i_2_n_0\,
      D => \val1_reg_n_0_[0]\,
      Q => \val0_reg_n_0_[0]\,
      R => \val2[31]_i_1_n_0\
    );
\val0_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => \val2[31]_i_2_n_0\,
      D => \val1_reg_n_0_[10]\,
      Q => \val0_reg_n_0_[10]\,
      R => \val2[31]_i_1_n_0\
    );
\val0_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => \val2[31]_i_2_n_0\,
      D => \val1_reg_n_0_[11]\,
      Q => \val0_reg_n_0_[11]\,
      R => \val2[31]_i_1_n_0\
    );
\val0_reg[12]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => \val2[31]_i_2_n_0\,
      D => \val1_reg_n_0_[12]\,
      Q => \val0_reg_n_0_[12]\,
      R => \val2[31]_i_1_n_0\
    );
\val0_reg[13]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => \val2[31]_i_2_n_0\,
      D => \val1_reg_n_0_[13]\,
      Q => \val0_reg_n_0_[13]\,
      R => \val2[31]_i_1_n_0\
    );
\val0_reg[14]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => \val2[31]_i_2_n_0\,
      D => \val1_reg_n_0_[14]\,
      Q => \val0_reg_n_0_[14]\,
      R => \val2[31]_i_1_n_0\
    );
\val0_reg[15]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => \val2[31]_i_2_n_0\,
      D => \val1_reg_n_0_[15]\,
      Q => \val0_reg_n_0_[15]\,
      R => \val2[31]_i_1_n_0\
    );
\val0_reg[16]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => \val2[31]_i_2_n_0\,
      D => \val1_reg_n_0_[16]\,
      Q => \val0_reg_n_0_[16]\,
      R => \val2[31]_i_1_n_0\
    );
\val0_reg[17]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => \val2[31]_i_2_n_0\,
      D => \val1_reg_n_0_[17]\,
      Q => \val0_reg_n_0_[17]\,
      R => \val2[31]_i_1_n_0\
    );
\val0_reg[18]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => \val2[31]_i_2_n_0\,
      D => \val1_reg_n_0_[18]\,
      Q => \val0_reg_n_0_[18]\,
      R => \val2[31]_i_1_n_0\
    );
\val0_reg[19]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => \val2[31]_i_2_n_0\,
      D => \val1_reg_n_0_[19]\,
      Q => \val0_reg_n_0_[19]\,
      R => \val2[31]_i_1_n_0\
    );
\val0_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => \val2[31]_i_2_n_0\,
      D => \val1_reg_n_0_[1]\,
      Q => \val0_reg_n_0_[1]\,
      R => \val2[31]_i_1_n_0\
    );
\val0_reg[20]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => \val2[31]_i_2_n_0\,
      D => \val1_reg_n_0_[20]\,
      Q => \val0_reg_n_0_[20]\,
      R => \val2[31]_i_1_n_0\
    );
\val0_reg[21]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => \val2[31]_i_2_n_0\,
      D => \val1_reg_n_0_[21]\,
      Q => \val0_reg_n_0_[21]\,
      R => \val2[31]_i_1_n_0\
    );
\val0_reg[22]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => \val2[31]_i_2_n_0\,
      D => \val1_reg_n_0_[22]\,
      Q => \val0_reg_n_0_[22]\,
      R => \val2[31]_i_1_n_0\
    );
\val0_reg[23]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => \val2[31]_i_2_n_0\,
      D => \val1_reg_n_0_[23]\,
      Q => \val0_reg_n_0_[23]\,
      R => \val2[31]_i_1_n_0\
    );
\val0_reg[24]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => \val2[31]_i_2_n_0\,
      D => \val1_reg_n_0_[24]\,
      Q => \val0_reg_n_0_[24]\,
      R => \val2[31]_i_1_n_0\
    );
\val0_reg[25]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => \val2[31]_i_2_n_0\,
      D => \val1_reg_n_0_[25]\,
      Q => \val0_reg_n_0_[25]\,
      R => \val2[31]_i_1_n_0\
    );
\val0_reg[26]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => \val2[31]_i_2_n_0\,
      D => \val1_reg_n_0_[26]\,
      Q => \val0_reg_n_0_[26]\,
      R => \val2[31]_i_1_n_0\
    );
\val0_reg[27]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => \val2[31]_i_2_n_0\,
      D => \val1_reg_n_0_[27]\,
      Q => \val0_reg_n_0_[27]\,
      R => \val2[31]_i_1_n_0\
    );
\val0_reg[28]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => \val2[31]_i_2_n_0\,
      D => \val1_reg_n_0_[28]\,
      Q => \val0_reg_n_0_[28]\,
      R => \val2[31]_i_1_n_0\
    );
\val0_reg[29]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => \val2[31]_i_2_n_0\,
      D => \val1_reg_n_0_[29]\,
      Q => \val0_reg_n_0_[29]\,
      R => \val2[31]_i_1_n_0\
    );
\val0_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => \val2[31]_i_2_n_0\,
      D => \val1_reg_n_0_[2]\,
      Q => \val0_reg_n_0_[2]\,
      R => \val2[31]_i_1_n_0\
    );
\val0_reg[30]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => \val2[31]_i_2_n_0\,
      D => \val1_reg_n_0_[30]\,
      Q => \val0_reg_n_0_[30]\,
      R => \val2[31]_i_1_n_0\
    );
\val0_reg[31]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => \val2[31]_i_2_n_0\,
      D => \val1_reg_n_0_[31]\,
      Q => \val0_reg_n_0_[31]\,
      R => \val2[31]_i_1_n_0\
    );
\val0_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => \val2[31]_i_2_n_0\,
      D => \val1_reg_n_0_[3]\,
      Q => \val0_reg_n_0_[3]\,
      R => \val2[31]_i_1_n_0\
    );
\val0_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => \val2[31]_i_2_n_0\,
      D => \val1_reg_n_0_[4]\,
      Q => \val0_reg_n_0_[4]\,
      R => \val2[31]_i_1_n_0\
    );
\val0_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => \val2[31]_i_2_n_0\,
      D => \val1_reg_n_0_[5]\,
      Q => \val0_reg_n_0_[5]\,
      R => \val2[31]_i_1_n_0\
    );
\val0_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => \val2[31]_i_2_n_0\,
      D => \val1_reg_n_0_[6]\,
      Q => \val0_reg_n_0_[6]\,
      R => \val2[31]_i_1_n_0\
    );
\val0_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => \val2[31]_i_2_n_0\,
      D => \val1_reg_n_0_[7]\,
      Q => \val0_reg_n_0_[7]\,
      R => \val2[31]_i_1_n_0\
    );
\val0_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => \val2[31]_i_2_n_0\,
      D => \val1_reg_n_0_[8]\,
      Q => \val0_reg_n_0_[8]\,
      R => \val2[31]_i_1_n_0\
    );
\val0_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => \val2[31]_i_2_n_0\,
      D => \val1_reg_n_0_[9]\,
      Q => \val0_reg_n_0_[9]\,
      R => \val2[31]_i_1_n_0\
    );
\val1_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => \val2[31]_i_2_n_0\,
      D => \val2_reg_n_0_[0]\,
      Q => \val1_reg_n_0_[0]\,
      R => \val2[31]_i_1_n_0\
    );
\val1_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => \val2[31]_i_2_n_0\,
      D => \val2_reg_n_0_[10]\,
      Q => \val1_reg_n_0_[10]\,
      R => \val2[31]_i_1_n_0\
    );
\val1_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => \val2[31]_i_2_n_0\,
      D => \val2_reg_n_0_[11]\,
      Q => \val1_reg_n_0_[11]\,
      R => \val2[31]_i_1_n_0\
    );
\val1_reg[12]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => \val2[31]_i_2_n_0\,
      D => \val2_reg_n_0_[12]\,
      Q => \val1_reg_n_0_[12]\,
      R => \val2[31]_i_1_n_0\
    );
\val1_reg[13]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => \val2[31]_i_2_n_0\,
      D => \val2_reg_n_0_[13]\,
      Q => \val1_reg_n_0_[13]\,
      R => \val2[31]_i_1_n_0\
    );
\val1_reg[14]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => \val2[31]_i_2_n_0\,
      D => \val2_reg_n_0_[14]\,
      Q => \val1_reg_n_0_[14]\,
      R => \val2[31]_i_1_n_0\
    );
\val1_reg[15]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => \val2[31]_i_2_n_0\,
      D => \val2_reg_n_0_[15]\,
      Q => \val1_reg_n_0_[15]\,
      R => \val2[31]_i_1_n_0\
    );
\val1_reg[16]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => \val2[31]_i_2_n_0\,
      D => \val2_reg_n_0_[16]\,
      Q => \val1_reg_n_0_[16]\,
      R => \val2[31]_i_1_n_0\
    );
\val1_reg[17]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => \val2[31]_i_2_n_0\,
      D => \val2_reg_n_0_[17]\,
      Q => \val1_reg_n_0_[17]\,
      R => \val2[31]_i_1_n_0\
    );
\val1_reg[18]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => \val2[31]_i_2_n_0\,
      D => \val2_reg_n_0_[18]\,
      Q => \val1_reg_n_0_[18]\,
      R => \val2[31]_i_1_n_0\
    );
\val1_reg[19]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => \val2[31]_i_2_n_0\,
      D => \val2_reg_n_0_[19]\,
      Q => \val1_reg_n_0_[19]\,
      R => \val2[31]_i_1_n_0\
    );
\val1_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => \val2[31]_i_2_n_0\,
      D => \val2_reg_n_0_[1]\,
      Q => \val1_reg_n_0_[1]\,
      R => \val2[31]_i_1_n_0\
    );
\val1_reg[20]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => \val2[31]_i_2_n_0\,
      D => \val2_reg_n_0_[20]\,
      Q => \val1_reg_n_0_[20]\,
      R => \val2[31]_i_1_n_0\
    );
\val1_reg[21]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => \val2[31]_i_2_n_0\,
      D => \val2_reg_n_0_[21]\,
      Q => \val1_reg_n_0_[21]\,
      R => \val2[31]_i_1_n_0\
    );
\val1_reg[22]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => \val2[31]_i_2_n_0\,
      D => \val2_reg_n_0_[22]\,
      Q => \val1_reg_n_0_[22]\,
      R => \val2[31]_i_1_n_0\
    );
\val1_reg[23]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => \val2[31]_i_2_n_0\,
      D => \val2_reg_n_0_[23]\,
      Q => \val1_reg_n_0_[23]\,
      R => \val2[31]_i_1_n_0\
    );
\val1_reg[24]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => \val2[31]_i_2_n_0\,
      D => \val2_reg_n_0_[24]\,
      Q => \val1_reg_n_0_[24]\,
      R => \val2[31]_i_1_n_0\
    );
\val1_reg[25]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => \val2[31]_i_2_n_0\,
      D => \val2_reg_n_0_[25]\,
      Q => \val1_reg_n_0_[25]\,
      R => \val2[31]_i_1_n_0\
    );
\val1_reg[26]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => \val2[31]_i_2_n_0\,
      D => \val2_reg_n_0_[26]\,
      Q => \val1_reg_n_0_[26]\,
      R => \val2[31]_i_1_n_0\
    );
\val1_reg[27]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => \val2[31]_i_2_n_0\,
      D => \val2_reg_n_0_[27]\,
      Q => \val1_reg_n_0_[27]\,
      R => \val2[31]_i_1_n_0\
    );
\val1_reg[28]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => \val2[31]_i_2_n_0\,
      D => \val2_reg_n_0_[28]\,
      Q => \val1_reg_n_0_[28]\,
      R => \val2[31]_i_1_n_0\
    );
\val1_reg[29]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => \val2[31]_i_2_n_0\,
      D => \val2_reg_n_0_[29]\,
      Q => \val1_reg_n_0_[29]\,
      R => \val2[31]_i_1_n_0\
    );
\val1_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => \val2[31]_i_2_n_0\,
      D => \val2_reg_n_0_[2]\,
      Q => \val1_reg_n_0_[2]\,
      R => \val2[31]_i_1_n_0\
    );
\val1_reg[30]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => \val2[31]_i_2_n_0\,
      D => \val2_reg_n_0_[30]\,
      Q => \val1_reg_n_0_[30]\,
      R => \val2[31]_i_1_n_0\
    );
\val1_reg[31]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => \val2[31]_i_2_n_0\,
      D => \val2_reg_n_0_[31]\,
      Q => \val1_reg_n_0_[31]\,
      R => \val2[31]_i_1_n_0\
    );
\val1_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => \val2[31]_i_2_n_0\,
      D => \val2_reg_n_0_[3]\,
      Q => \val1_reg_n_0_[3]\,
      R => \val2[31]_i_1_n_0\
    );
\val1_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => \val2[31]_i_2_n_0\,
      D => \val2_reg_n_0_[4]\,
      Q => \val1_reg_n_0_[4]\,
      R => \val2[31]_i_1_n_0\
    );
\val1_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => \val2[31]_i_2_n_0\,
      D => \val2_reg_n_0_[5]\,
      Q => \val1_reg_n_0_[5]\,
      R => \val2[31]_i_1_n_0\
    );
\val1_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => \val2[31]_i_2_n_0\,
      D => \val2_reg_n_0_[6]\,
      Q => \val1_reg_n_0_[6]\,
      R => \val2[31]_i_1_n_0\
    );
\val1_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => \val2[31]_i_2_n_0\,
      D => \val2_reg_n_0_[7]\,
      Q => \val1_reg_n_0_[7]\,
      R => \val2[31]_i_1_n_0\
    );
\val1_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => \val2[31]_i_2_n_0\,
      D => \val2_reg_n_0_[8]\,
      Q => \val1_reg_n_0_[8]\,
      R => \val2[31]_i_1_n_0\
    );
\val1_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => \val2[31]_i_2_n_0\,
      D => \val2_reg_n_0_[9]\,
      Q => \val1_reg_n_0_[9]\,
      R => \val2[31]_i_1_n_0\
    );
\val2[31]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000A222"
    )
        port map (
      I0 => \state__0\(1),
      I1 => start,
      I2 => max_found12_in,
      I3 => max_found1,
      I4 => \state__0\(0),
      O => \val2[31]_i_1_n_0\
    );
\val2[31]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"3000333344444444"
    )
        port map (
      I0 => j1,
      I1 => \state__0\(0),
      I2 => max_found1,
      I3 => max_found12_in,
      I4 => start,
      I5 => \state__0\(1),
      O => \val2[31]_i_2_n_0\
    );
\val2_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => \val2[31]_i_2_n_0\,
      D => val_in(0),
      Q => \val2_reg_n_0_[0]\,
      R => \val2[31]_i_1_n_0\
    );
\val2_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => \val2[31]_i_2_n_0\,
      D => val_in(10),
      Q => \val2_reg_n_0_[10]\,
      R => \val2[31]_i_1_n_0\
    );
\val2_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => \val2[31]_i_2_n_0\,
      D => val_in(11),
      Q => \val2_reg_n_0_[11]\,
      R => \val2[31]_i_1_n_0\
    );
\val2_reg[12]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => \val2[31]_i_2_n_0\,
      D => val_in(12),
      Q => \val2_reg_n_0_[12]\,
      R => \val2[31]_i_1_n_0\
    );
\val2_reg[13]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => \val2[31]_i_2_n_0\,
      D => val_in(13),
      Q => \val2_reg_n_0_[13]\,
      R => \val2[31]_i_1_n_0\
    );
\val2_reg[14]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => \val2[31]_i_2_n_0\,
      D => val_in(14),
      Q => \val2_reg_n_0_[14]\,
      R => \val2[31]_i_1_n_0\
    );
\val2_reg[15]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => \val2[31]_i_2_n_0\,
      D => val_in(15),
      Q => \val2_reg_n_0_[15]\,
      R => \val2[31]_i_1_n_0\
    );
\val2_reg[16]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => \val2[31]_i_2_n_0\,
      D => val_in(16),
      Q => \val2_reg_n_0_[16]\,
      R => \val2[31]_i_1_n_0\
    );
\val2_reg[17]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => \val2[31]_i_2_n_0\,
      D => val_in(17),
      Q => \val2_reg_n_0_[17]\,
      R => \val2[31]_i_1_n_0\
    );
\val2_reg[18]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => \val2[31]_i_2_n_0\,
      D => val_in(18),
      Q => \val2_reg_n_0_[18]\,
      R => \val2[31]_i_1_n_0\
    );
\val2_reg[19]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => \val2[31]_i_2_n_0\,
      D => val_in(19),
      Q => \val2_reg_n_0_[19]\,
      R => \val2[31]_i_1_n_0\
    );
\val2_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => \val2[31]_i_2_n_0\,
      D => val_in(1),
      Q => \val2_reg_n_0_[1]\,
      R => \val2[31]_i_1_n_0\
    );
\val2_reg[20]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => \val2[31]_i_2_n_0\,
      D => val_in(20),
      Q => \val2_reg_n_0_[20]\,
      R => \val2[31]_i_1_n_0\
    );
\val2_reg[21]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => \val2[31]_i_2_n_0\,
      D => val_in(21),
      Q => \val2_reg_n_0_[21]\,
      R => \val2[31]_i_1_n_0\
    );
\val2_reg[22]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => \val2[31]_i_2_n_0\,
      D => val_in(22),
      Q => \val2_reg_n_0_[22]\,
      R => \val2[31]_i_1_n_0\
    );
\val2_reg[23]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => \val2[31]_i_2_n_0\,
      D => val_in(23),
      Q => \val2_reg_n_0_[23]\,
      R => \val2[31]_i_1_n_0\
    );
\val2_reg[24]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => \val2[31]_i_2_n_0\,
      D => val_in(24),
      Q => \val2_reg_n_0_[24]\,
      R => \val2[31]_i_1_n_0\
    );
\val2_reg[25]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => \val2[31]_i_2_n_0\,
      D => val_in(25),
      Q => \val2_reg_n_0_[25]\,
      R => \val2[31]_i_1_n_0\
    );
\val2_reg[26]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => \val2[31]_i_2_n_0\,
      D => val_in(26),
      Q => \val2_reg_n_0_[26]\,
      R => \val2[31]_i_1_n_0\
    );
\val2_reg[27]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => \val2[31]_i_2_n_0\,
      D => val_in(27),
      Q => \val2_reg_n_0_[27]\,
      R => \val2[31]_i_1_n_0\
    );
\val2_reg[28]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => \val2[31]_i_2_n_0\,
      D => val_in(28),
      Q => \val2_reg_n_0_[28]\,
      R => \val2[31]_i_1_n_0\
    );
\val2_reg[29]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => \val2[31]_i_2_n_0\,
      D => val_in(29),
      Q => \val2_reg_n_0_[29]\,
      R => \val2[31]_i_1_n_0\
    );
\val2_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => \val2[31]_i_2_n_0\,
      D => val_in(2),
      Q => \val2_reg_n_0_[2]\,
      R => \val2[31]_i_1_n_0\
    );
\val2_reg[30]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => \val2[31]_i_2_n_0\,
      D => val_in(30),
      Q => \val2_reg_n_0_[30]\,
      R => \val2[31]_i_1_n_0\
    );
\val2_reg[31]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => \val2[31]_i_2_n_0\,
      D => val_in(31),
      Q => \val2_reg_n_0_[31]\,
      R => \val2[31]_i_1_n_0\
    );
\val2_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => \val2[31]_i_2_n_0\,
      D => val_in(3),
      Q => \val2_reg_n_0_[3]\,
      R => \val2[31]_i_1_n_0\
    );
\val2_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => \val2[31]_i_2_n_0\,
      D => val_in(4),
      Q => \val2_reg_n_0_[4]\,
      R => \val2[31]_i_1_n_0\
    );
\val2_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => \val2[31]_i_2_n_0\,
      D => val_in(5),
      Q => \val2_reg_n_0_[5]\,
      R => \val2[31]_i_1_n_0\
    );
\val2_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => \val2[31]_i_2_n_0\,
      D => val_in(6),
      Q => \val2_reg_n_0_[6]\,
      R => \val2[31]_i_1_n_0\
    );
\val2_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => \val2[31]_i_2_n_0\,
      D => val_in(7),
      Q => \val2_reg_n_0_[7]\,
      R => \val2[31]_i_1_n_0\
    );
\val2_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => \val2[31]_i_2_n_0\,
      D => val_in(8),
      Q => \val2_reg_n_0_[8]\,
      R => \val2[31]_i_1_n_0\
    );
\val2_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => \val2[31]_i_2_n_0\,
      D => val_in(9),
      Q => \val2_reg_n_0_[9]\,
      R => \val2[31]_i_1_n_0\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity pdm_to_pcm_energy_compare_0_0 is
  port (
    clk : in STD_LOGIC;
    start : in STD_LOGIC;
    val_in : in STD_LOGIC_VECTOR ( 31 downto 0 );
    max_found : out STD_LOGIC;
    start_fifo : out STD_LOGIC;
    val_out : out STD_LOGIC_VECTOR ( 31 downto 0 )
  );
  attribute NotValidForBitStream : boolean;
  attribute NotValidForBitStream of pdm_to_pcm_energy_compare_0_0 : entity is true;
  attribute CHECK_LICENSE_TYPE : string;
  attribute CHECK_LICENSE_TYPE of pdm_to_pcm_energy_compare_0_0 : entity is "pdm_to_pcm_energy_compare_0_0,energy_compare,{}";
  attribute downgradeipidentifiedwarnings : string;
  attribute downgradeipidentifiedwarnings of pdm_to_pcm_energy_compare_0_0 : entity is "yes";
  attribute ip_definition_source : string;
  attribute ip_definition_source of pdm_to_pcm_energy_compare_0_0 : entity is "module_ref";
  attribute x_core_info : string;
  attribute x_core_info of pdm_to_pcm_energy_compare_0_0 : entity is "energy_compare,Vivado 2019.1";
end pdm_to_pcm_energy_compare_0_0;

architecture STRUCTURE of pdm_to_pcm_energy_compare_0_0 is
  signal \<const0>\ : STD_LOGIC;
  attribute x_interface_info : string;
  attribute x_interface_info of clk : signal is "xilinx.com:signal:clock:1.0 clk CLK";
  attribute x_interface_parameter : string;
  attribute x_interface_parameter of clk : signal is "XIL_INTERFACENAME clk, FREQ_HZ 100000000, PHASE 0.000, INSERT_VIP 0";
begin
  val_out(31) <= \<const0>\;
  val_out(30) <= \<const0>\;
  val_out(29) <= \<const0>\;
  val_out(28) <= \<const0>\;
  val_out(27) <= \<const0>\;
  val_out(26) <= \<const0>\;
  val_out(25) <= \<const0>\;
  val_out(24) <= \<const0>\;
  val_out(23) <= \<const0>\;
  val_out(22) <= \<const0>\;
  val_out(21) <= \<const0>\;
  val_out(20) <= \<const0>\;
  val_out(19) <= \<const0>\;
  val_out(18) <= \<const0>\;
  val_out(17) <= \<const0>\;
  val_out(16) <= \<const0>\;
  val_out(15) <= \<const0>\;
  val_out(14) <= \<const0>\;
  val_out(13) <= \<const0>\;
  val_out(12) <= \<const0>\;
  val_out(11) <= \<const0>\;
  val_out(10) <= \<const0>\;
  val_out(9) <= \<const0>\;
  val_out(8) <= \<const0>\;
  val_out(7) <= \<const0>\;
  val_out(6) <= \<const0>\;
  val_out(5) <= \<const0>\;
  val_out(4) <= \<const0>\;
  val_out(3) <= \<const0>\;
  val_out(2) <= \<const0>\;
  val_out(1) <= \<const0>\;
  val_out(0) <= \<const0>\;
GND: unisim.vcomponents.GND
     port map (
      G => \<const0>\
    );
U0: entity work.pdm_to_pcm_energy_compare_0_0_energy_compare
     port map (
      clk => clk,
      max_found => max_found,
      start => start,
      start_fifo => start_fifo,
      val_in(31 downto 0) => val_in(31 downto 0)
    );
end STRUCTURE;
