LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
USE ieee.math_real.ALL;

ENTITY delay_tb IS
    
END delay_tb;

ARCHITECTURE arch OF delay_tb IS
  COMPONENT delay IS
    Port ( 
                   clk: in std_logic;     
               address: out std_logic_vector(4 downto 0));
end component delay;


signal  clk_tb :  STD_LOGIC:='0';
signal address_tb : std_logic_vector(4 downto 0);

begin

   instance1:COMPONENT delay
  PORT MAP(            clk => clk_tb, 
                       address => address_tb);

clk_process: process
    begin
             wait for 50 ns;
             clk_tb<=NOT(clk_tb);
    end process;

END ARCHITECTURE arch;


