Vivado Simulator 2019.1
Copyright 1986-1999, 2001-2019 Xilinx, Inc. All Rights Reserved.
Running: C:/xilinx/Vivado/2019.1/bin/unwrapped/win64.o/xelab.exe -wto e28594f732a0486499082ea7bbfdcf60 --incr --debug typical --relax --mt 2 -L work -L xil_defaultlib -L xbip_utils_v3_0_10 -L axi_utils_v2_0_6 -L cic_compiler_v4_0_14 -L fir_compiler_v7_2_12 -L fifo_generator_v13_2_4 -L util_vector_logic_v2_0_1 -L c_reg_fd_v12_0_6 -L xbip_dsp48_wrapper_v3_0_4 -L xbip_pipe_v3_0_6 -L xbip_dsp48_addsub_v3_0_6 -L xbip_addsub_v3_0_6 -L c_addsub_v12_0_13 -L blk_mem_gen_v8_4_3 -L c_mux_bit_v12_0_6 -L c_shift_ram_v12_0_13 -L xbip_bram18k_v3_0_6 -L mult_gen_v12_0_15 -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot test_pdm_to_pcm_behav xil_defaultlib.test_pdm_to_pcm xil_defaultlib.glbl -log elaborate.log 
Using 2 slave threads.
Starting static elaboration
WARNING: [VRFC 10-516] comparison between unequal length arrays always returns FALSE [/wrk/2019.1/continuous/2019_05_24_2552052/packages/customer/vivado/data/ip/xilinx/xbip_utils_v3_0/hdl/xbip_utils_v3_0_vh_rfs.vhd:2056]
WARNING: [VRFC 10-516] comparison between unequal length arrays always returns FALSE [/wrk/2019.1/continuous/2019_05_24_2552052/packages/customer/vivado/data/ip/xilinx/xbip_utils_v3_0/hdl/xbip_utils_v3_0_vh_rfs.vhd:2058]
WARNING: [VRFC 10-516] comparison between unequal length arrays always returns FALSE [/wrk/2019.1/continuous/2019_05_24_2552052/packages/customer/vivado/data/ip/xilinx/xbip_utils_v3_0/hdl/xbip_utils_v3_0_vh_rfs.vhd:2059]
WARNING: [VRFC 10-516] comparison between unequal length arrays always returns FALSE [/wrk/2019.1/continuous/2019_05_24_2552052/packages/customer/vivado/data/ip/xilinx/xbip_utils_v3_0/hdl/xbip_utils_v3_0_vh_rfs.vhd:2060]
WARNING: [VRFC 10-516] comparison between unequal length arrays always returns FALSE [/wrk/2019.1/continuous/2019_05_24_2552052/packages/customer/vivado/data/ip/xilinx/xbip_utils_v3_0/hdl/xbip_utils_v3_0_vh_rfs.vhd:2046]
WARNING: [VRFC 10-516] comparison between unequal length arrays always returns FALSE [/wrk/2019.1/continuous/2019_05_24_2552052/packages/customer/vivado/data/ip/xilinx/xbip_utils_v3_0/hdl/xbip_utils_v3_0_vh_rfs.vhd:2047]
WARNING: [VRFC 10-516] comparison between unequal length arrays always returns FALSE [/wrk/2019.1/continuous/2019_05_24_2552052/packages/customer/vivado/data/ip/xilinx/xbip_utils_v3_0/hdl/xbip_utils_v3_0_vh_rfs.vhd:2049]
WARNING: [VRFC 10-516] comparison between unequal length arrays always returns FALSE [/wrk/2019.1/continuous/2019_05_24_2552052/packages/customer/vivado/data/ip/xilinx/xbip_utils_v3_0/hdl/xbip_utils_v3_0_vh_rfs.vhd:2050]
WARNING: [VRFC 10-516] comparison between unequal length arrays always returns FALSE [/wrk/2019.1/continuous/2019_05_24_2552052/packages/customer/vivado/data/ip/xilinx/xbip_utils_v3_0/hdl/xbip_utils_v3_0_vh_rfs.vhd:2056]
WARNING: [VRFC 10-516] comparison between unequal length arrays always returns FALSE [/wrk/2019.1/continuous/2019_05_24_2552052/packages/customer/vivado/data/ip/xilinx/xbip_utils_v3_0/hdl/xbip_utils_v3_0_vh_rfs.vhd:2058]
WARNING: [VRFC 10-516] comparison between unequal length arrays always returns FALSE [/wrk/2019.1/continuous/2019_05_24_2552052/packages/customer/vivado/data/ip/xilinx/xbip_utils_v3_0/hdl/xbip_utils_v3_0_vh_rfs.vhd:2059]
WARNING: [VRFC 10-516] comparison between unequal length arrays always returns FALSE [/wrk/2019.1/continuous/2019_05_24_2552052/packages/customer/vivado/data/ip/xilinx/xbip_utils_v3_0/hdl/xbip_utils_v3_0_vh_rfs.vhd:2060]
WARNING: [VRFC 10-516] comparison between unequal length arrays always returns FALSE [/wrk/2019.1/continuous/2019_05_24_2552052/packages/customer/vivado/data/ip/xilinx/xbip_utils_v3_0/hdl/xbip_utils_v3_0_vh_rfs.vhd:2046]
WARNING: [VRFC 10-516] comparison between unequal length arrays always returns FALSE [/wrk/2019.1/continuous/2019_05_24_2552052/packages/customer/vivado/data/ip/xilinx/xbip_utils_v3_0/hdl/xbip_utils_v3_0_vh_rfs.vhd:2047]
WARNING: [VRFC 10-516] comparison between unequal length arrays always returns FALSE [/wrk/2019.1/continuous/2019_05_24_2552052/packages/customer/vivado/data/ip/xilinx/xbip_utils_v3_0/hdl/xbip_utils_v3_0_vh_rfs.vhd:2049]
WARNING: [VRFC 10-516] comparison between unequal length arrays always returns FALSE [/wrk/2019.1/continuous/2019_05_24_2552052/packages/customer/vivado/data/ip/xilinx/xbip_utils_v3_0/hdl/xbip_utils_v3_0_vh_rfs.vhd:2050]
WARNING: [VRFC 10-516] comparison between unequal length arrays always returns FALSE [/wrk/2019.1/continuous/2019_05_24_2552052/packages/customer/vivado/data/ip/xilinx/xbip_utils_v3_0/hdl/xbip_utils_v3_0_vh_rfs.vhd:2056]
WARNING: [VRFC 10-516] comparison between unequal length arrays always returns FALSE [/wrk/2019.1/continuous/2019_05_24_2552052/packages/customer/vivado/data/ip/xilinx/xbip_utils_v3_0/hdl/xbip_utils_v3_0_vh_rfs.vhd:2058]
WARNING: [VRFC 10-516] comparison between unequal length arrays always returns FALSE [/wrk/2019.1/continuous/2019_05_24_2552052/packages/customer/vivado/data/ip/xilinx/xbip_utils_v3_0/hdl/xbip_utils_v3_0_vh_rfs.vhd:2059]
WARNING: [VRFC 10-516] comparison between unequal length arrays always returns FALSE [/wrk/2019.1/continuous/2019_05_24_2552052/packages/customer/vivado/data/ip/xilinx/xbip_utils_v3_0/hdl/xbip_utils_v3_0_vh_rfs.vhd:2060]
WARNING: [VRFC 10-516] comparison between unequal length arrays always returns FALSE [/wrk/2019.1/continuous/2019_05_24_2552052/packages/customer/vivado/data/ip/xilinx/xbip_utils_v3_0/hdl/xbip_utils_v3_0_vh_rfs.vhd:2046]
WARNING: [VRFC 10-516] comparison between unequal length arrays always returns FALSE [/wrk/2019.1/continuous/2019_05_24_2552052/packages/customer/vivado/data/ip/xilinx/xbip_utils_v3_0/hdl/xbip_utils_v3_0_vh_rfs.vhd:2047]
WARNING: [VRFC 10-516] comparison between unequal length arrays always returns FALSE [/wrk/2019.1/continuous/2019_05_24_2552052/packages/customer/vivado/data/ip/xilinx/xbip_utils_v3_0/hdl/xbip_utils_v3_0_vh_rfs.vhd:2049]
WARNING: [VRFC 10-516] comparison between unequal length arrays always returns FALSE [/wrk/2019.1/continuous/2019_05_24_2552052/packages/customer/vivado/data/ip/xilinx/xbip_utils_v3_0/hdl/xbip_utils_v3_0_vh_rfs.vhd:2050]
WARNING: [VRFC 10-516] comparison between unequal length arrays always returns FALSE [/wrk/2019.1/continuous/2019_05_24_2552052/packages/customer/vivado/data/ip/xilinx/xbip_utils_v3_0/hdl/xbip_utils_v3_0_vh_rfs.vhd:2056]
WARNING: [VRFC 10-516] comparison between unequal length arrays always returns FALSE [/wrk/2019.1/continuous/2019_05_24_2552052/packages/customer/vivado/data/ip/xilinx/xbip_utils_v3_0/hdl/xbip_utils_v3_0_vh_rfs.vhd:2058]
WARNING: [VRFC 10-516] comparison between unequal length arrays always returns FALSE [/wrk/2019.1/continuous/2019_05_24_2552052/packages/customer/vivado/data/ip/xilinx/xbip_utils_v3_0/hdl/xbip_utils_v3_0_vh_rfs.vhd:2059]
WARNING: [VRFC 10-516] comparison between unequal length arrays always returns FALSE [/wrk/2019.1/continuous/2019_05_24_2552052/packages/customer/vivado/data/ip/xilinx/xbip_utils_v3_0/hdl/xbip_utils_v3_0_vh_rfs.vhd:2060]
WARNING: [VRFC 10-516] comparison between unequal length arrays always returns FALSE [/wrk/2019.1/continuous/2019_05_24_2552052/packages/customer/vivado/data/ip/xilinx/xbip_utils_v3_0/hdl/xbip_utils_v3_0_vh_rfs.vhd:2046]
WARNING: [VRFC 10-516] comparison between unequal length arrays always returns FALSE [/wrk/2019.1/continuous/2019_05_24_2552052/packages/customer/vivado/data/ip/xilinx/xbip_utils_v3_0/hdl/xbip_utils_v3_0_vh_rfs.vhd:2047]
WARNING: [VRFC 10-516] comparison between unequal length arrays always returns FALSE [/wrk/2019.1/continuous/2019_05_24_2552052/packages/customer/vivado/data/ip/xilinx/xbip_utils_v3_0/hdl/xbip_utils_v3_0_vh_rfs.vhd:2049]
WARNING: [VRFC 10-516] comparison between unequal length arrays always returns FALSE [/wrk/2019.1/continuous/2019_05_24_2552052/packages/customer/vivado/data/ip/xilinx/xbip_utils_v3_0/hdl/xbip_utils_v3_0_vh_rfs.vhd:2050]
WARNING: [VRFC 10-516] comparison between unequal length arrays always returns FALSE [/wrk/2019.1/continuous/2019_05_24_2552052/packages/customer/vivado/data/ip/xilinx/xbip_utils_v3_0/hdl/xbip_utils_v3_0_vh_rfs.vhd:2056]
WARNING: [VRFC 10-516] comparison between unequal length arrays always returns FALSE [/wrk/2019.1/continuous/2019_05_24_2552052/packages/customer/vivado/data/ip/xilinx/xbip_utils_v3_0/hdl/xbip_utils_v3_0_vh_rfs.vhd:2058]
WARNING: [VRFC 10-516] comparison between unequal length arrays always returns FALSE [/wrk/2019.1/continuous/2019_05_24_2552052/packages/customer/vivado/data/ip/xilinx/xbip_utils_v3_0/hdl/xbip_utils_v3_0_vh_rfs.vhd:2059]
WARNING: [VRFC 10-516] comparison between unequal length arrays always returns FALSE [/wrk/2019.1/continuous/2019_05_24_2552052/packages/customer/vivado/data/ip/xilinx/xbip_utils_v3_0/hdl/xbip_utils_v3_0_vh_rfs.vhd:2060]
WARNING: [VRFC 10-516] comparison between unequal length arrays always returns FALSE [/wrk/2019.1/continuous/2019_05_24_2552052/packages/customer/vivado/data/ip/xilinx/xbip_utils_v3_0/hdl/xbip_utils_v3_0_vh_rfs.vhd:2046]
WARNING: [VRFC 10-516] comparison between unequal length arrays always returns FALSE [/wrk/2019.1/continuous/2019_05_24_2552052/packages/customer/vivado/data/ip/xilinx/xbip_utils_v3_0/hdl/xbip_utils_v3_0_vh_rfs.vhd:2047]
WARNING: [VRFC 10-516] comparison between unequal length arrays always returns FALSE [/wrk/2019.1/continuous/2019_05_24_2552052/packages/customer/vivado/data/ip/xilinx/xbip_utils_v3_0/hdl/xbip_utils_v3_0_vh_rfs.vhd:2049]
WARNING: [VRFC 10-516] comparison between unequal length arrays always returns FALSE [/wrk/2019.1/continuous/2019_05_24_2552052/packages/customer/vivado/data/ip/xilinx/xbip_utils_v3_0/hdl/xbip_utils_v3_0_vh_rfs.vhd:2050]
WARNING: [VRFC 10-516] comparison between unequal length arrays always returns FALSE [/wrk/2019.1/continuous/2019_05_24_2552052/packages/customer/vivado/data/ip/xilinx/xbip_utils_v3_0/hdl/xbip_utils_v3_0_vh_rfs.vhd:2056]
WARNING: [VRFC 10-516] comparison between unequal length arrays always returns FALSE [/wrk/2019.1/continuous/2019_05_24_2552052/packages/customer/vivado/data/ip/xilinx/xbip_utils_v3_0/hdl/xbip_utils_v3_0_vh_rfs.vhd:2058]
WARNING: [VRFC 10-516] comparison between unequal length arrays always returns FALSE [/wrk/2019.1/continuous/2019_05_24_2552052/packages/customer/vivado/data/ip/xilinx/xbip_utils_v3_0/hdl/xbip_utils_v3_0_vh_rfs.vhd:2059]
WARNING: [VRFC 10-516] comparison between unequal length arrays always returns FALSE [/wrk/2019.1/continuous/2019_05_24_2552052/packages/customer/vivado/data/ip/xilinx/xbip_utils_v3_0/hdl/xbip_utils_v3_0_vh_rfs.vhd:2060]
WARNING: [VRFC 10-516] comparison between unequal length arrays always returns FALSE [/wrk/2019.1/continuous/2019_05_24_2552052/packages/customer/vivado/data/ip/xilinx/xbip_utils_v3_0/hdl/xbip_utils_v3_0_vh_rfs.vhd:2046]
WARNING: [VRFC 10-516] comparison between unequal length arrays always returns FALSE [/wrk/2019.1/continuous/2019_05_24_2552052/packages/customer/vivado/data/ip/xilinx/xbip_utils_v3_0/hdl/xbip_utils_v3_0_vh_rfs.vhd:2047]
WARNING: [VRFC 10-516] comparison between unequal length arrays always returns FALSE [/wrk/2019.1/continuous/2019_05_24_2552052/packages/customer/vivado/data/ip/xilinx/xbip_utils_v3_0/hdl/xbip_utils_v3_0_vh_rfs.vhd:2049]
WARNING: [VRFC 10-516] comparison between unequal length arrays always returns FALSE [/wrk/2019.1/continuous/2019_05_24_2552052/packages/customer/vivado/data/ip/xilinx/xbip_utils_v3_0/hdl/xbip_utils_v3_0_vh_rfs.vhd:2050]
Completed static elaboration
Starting simulation data flow analysis
Completed simulation data flow analysis
Time Resolution for simulation is 1ps
Compiling package std.standard
Compiling package std.textio
Compiling package ieee.std_logic_1164
Compiling package ieee.numeric_std
Compiling package unisim.vcomponents
Compiling package c_addsub_v12_0_13.c_addsub_v12_0_13_viv_comp
Compiling package xbip_utils_v3_0_10.xbip_utils_v3_0_10_pkg
Compiling package xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv_comp
Compiling package xbip_addsub_v3_0_6.xbip_addsub_v3_0_6_viv_comp
Compiling package c_addsub_v12_0_13.c_addsub_v12_0_13_pkg
Compiling package c_addsub_v12_0_13.c_addsub_v12_0_13_pkg_legacy
Compiling package c_reg_fd_v12_0_6.c_reg_fd_v12_0_6_viv_comp
Compiling package c_shift_ram_v12_0_13.c_shift_ram_v12_0_13_viv_comp
Compiling package c_shift_ram_v12_0_13.c_shift_ram_v12_0_13_pkg
Compiling package c_mux_bit_v12_0_6.c_mux_bit_v12_0_6_viv_comp
Compiling package cic_compiler_v4_0_14.cic_compiler_v4_0_14_viv_comp
Compiling package ieee.std_logic_arith
Compiling package ieee.std_logic_signed
Compiling package ieee.math_real
Compiling package ieee.std_logic_textio
Compiling package cic_compiler_v4_0_14.toolbox_pkg
Compiling package cic_compiler_v4_0_14.cic_compiler_v4_0_14_pkg
Compiling package cic_compiler_v4_0_14.cic_compiler_v4_0_14_hdl_comps
Compiling package axi_utils_v2_0_6.global_util_pkg
Compiling package axi_utils_v2_0_6.axi_utils_comps
Compiling package ieee.vital_timing
Compiling package ieee.vital_primitives
Compiling package unisim.vpkg
Compiling package fir_compiler_v7_2_12.fir_compiler_v7_2_12_viv_comp
Compiling package fir_compiler_v7_2_12.globals_pkg
Compiling package fir_compiler_v7_2_12.components
Compiling package mult_gen_v12_0_15.mult_gen_v12_0_15_viv_comp
Compiling package mult_gen_v12_0_15.mult_gen_v12_0_15_pkg
Compiling package ieee.std_logic_unsigned
Compiling package vl.vl_types
Compiling module xil_defaultlib.glbl
Compiling module blk_mem_gen_v8_4_3.blk_mem_gen_v8_4_3_output_stage(...
Compiling module blk_mem_gen_v8_4_3.blk_mem_gen_v8_4_3_softecc_outpu...
Compiling module blk_mem_gen_v8_4_3.blk_mem_gen_v8_4_3_mem_module(C_...
Compiling module blk_mem_gen_v8_4_3.blk_mem_gen_v8_4_3(C_FAMILY="art...
Compiling module xil_defaultlib.pdm_to_pcm_blk_mem_gen_0_0
Compiling module blk_mem_gen_v8_4_3.blk_mem_gen_v8_4_3_output_stage(...
Compiling module blk_mem_gen_v8_4_3.blk_mem_gen_v8_4_3_mem_module(C_...
Compiling module blk_mem_gen_v8_4_3.blk_mem_gen_v8_4_3(C_FAMILY="art...
Compiling module xil_defaultlib.pdm_to_pcm_blk_mem_gen_1_0
Compiling module blk_mem_gen_v8_4_3.blk_mem_gen_v8_4_3_mem_module(C_...
Compiling module blk_mem_gen_v8_4_3.blk_mem_gen_v8_4_3(C_FAMILY="art...
Compiling module xil_defaultlib.pdm_to_pcm_blk_mem_gen_1_1
Compiling module blk_mem_gen_v8_4_3.blk_mem_gen_v8_4_3_mem_module(C_...
Compiling module blk_mem_gen_v8_4_3.blk_mem_gen_v8_4_3(C_FAMILY="art...
Compiling module xil_defaultlib.pdm_to_pcm_blk_mem_gen_2_0
Compiling architecture structural of entity c_reg_fd_v12_0_6.c_reg_fd_v12_0_6_viv [\c_reg_fd_v12_0_6_viv(c_width=16...]
Compiling architecture muxcy_v of entity unisim.MUXCY [muxcy_default]
Compiling architecture xorcy_v of entity unisim.XORCY [xorcy_default]
Compiling architecture rtl of entity c_addsub_v12_0_13.c_addsub_v12_0_13_lut6_legacy [\c_addsub_v12_0_13_lut6_legacy(c...]
Compiling architecture synth of entity c_addsub_v12_0_13.c_addsub_v12_0_13_fabric_legacy [\c_addsub_v12_0_13_fabric_legacy...]
Compiling architecture synth of entity c_addsub_v12_0_13.c_addsub_v12_0_13_legacy [\c_addsub_v12_0_13_legacy(c_fami...]
Compiling architecture synth of entity c_addsub_v12_0_13.c_addsub_v12_0_13_viv [\c_addsub_v12_0_13_viv(c_xdevice...]
Compiling architecture xilinx of entity c_addsub_v12_0_13.c_addsub_v12_0_13 [\c_addsub_v12_0_13(c_xdevicefami...]
Compiling architecture pdm_to_pcm_c_addsub_0_0_arch of entity xil_defaultlib.pdm_to_pcm_c_addsub_0_0 [pdm_to_pcm_c_addsub_0_0_default]
Compiling architecture pdm_to_pcm_c_addsub_0_1_arch of entity xil_defaultlib.pdm_to_pcm_c_addsub_0_1 [pdm_to_pcm_c_addsub_0_1_default]
Compiling architecture pdm_to_pcm_c_addsub_1_0_arch of entity xil_defaultlib.pdm_to_pcm_c_addsub_1_0 [pdm_to_pcm_c_addsub_1_0_default]
Compiling architecture structural of entity c_reg_fd_v12_0_6.c_reg_fd_v12_0_6_viv [\c_reg_fd_v12_0_6_viv(c_width=16...]
Compiling architecture struct of entity c_shift_ram_v12_0_13.c_shift_ram_v12_0_13_legacy [\c_shift_ram_v12_0_13_legacy(c_x...]
Compiling architecture synth of entity c_shift_ram_v12_0_13.c_shift_ram_v12_0_13_viv [\c_shift_ram_v12_0_13_viv(c_xdev...]
Compiling architecture xilinx of entity c_shift_ram_v12_0_13.c_shift_ram_v12_0_13 [\c_shift_ram_v12_0_13(c_xdevicef...]
Compiling architecture pdm_to_pcm_c_shift_ram_0_0_arch of entity xil_defaultlib.pdm_to_pcm_c_shift_ram_0_0 [pdm_to_pcm_c_shift_ram_0_0_defau...]
Compiling architecture pdm_to_pcm_c_shift_ram_1_0_arch of entity xil_defaultlib.pdm_to_pcm_c_shift_ram_1_0 [pdm_to_pcm_c_shift_ram_1_0_defau...]
Compiling architecture pdm_to_pcm_c_shift_ram_1_1_arch of entity xil_defaultlib.pdm_to_pcm_c_shift_ram_1_1 [pdm_to_pcm_c_shift_ram_1_1_defau...]
Compiling architecture pdm_to_pcm_c_shift_ram_1_2_arch of entity xil_defaultlib.pdm_to_pcm_c_shift_ram_1_2 [pdm_to_pcm_c_shift_ram_1_2_defau...]
Compiling architecture xilinx of entity axi_utils_v2_0_6.axi_slave_2to1 [\axi_slave_2to1(c_a_tdata_width=...]
Compiling architecture xilinx of entity axi_utils_v2_0_6.glb_srl_fifo [\glb_srl_fifo(width=26,has_uvpro...]
Compiling architecture xilinx of entity axi_utils_v2_0_6.glb_ifx_master [\glb_ifx_master(width=26,afull_t...]
Compiling architecture struct_all of entity cic_compiler_v4_0_14.delay [\delay(delay_len=1,family=(p_dsp...]
Compiling architecture implementation of entity cic_compiler_v4_0_14.dpr_ram [\dpr_ram(param=((p_dsp48e1,false...]
Compiling architecture muxcy_l_v of entity unisim.MUXCY_L [muxcy_l_default]
Compiling architecture lut4_v of entity unisim.LUT4 [\LUT4(init="1111111111001010")(0...]
Compiling architecture fdre_v of entity unisim.FDRE [fdre_default]
Compiling architecture fdrse_v of entity unisim.FDRSE [fdrse_default]
Compiling architecture muxcy_d_v of entity unisim.MUXCY_D [muxcy_d_default]
Compiling architecture rtl of entity cic_compiler_v4_0_14.counter [\counter(width=3,const_vals=(-7,...]
Compiling architecture arch1 of entity cic_compiler_v4_0_14.compare_dualval [\compare_dualval(value1=2,value2...]
Compiling architecture struct_all of entity cic_compiler_v4_0_14.twopage_address [\twopage_address(param=((p_dsp48...]
Compiling architecture rtl of entity cic_compiler_v4_0_14.counter [\counter(width=2,const_vals=(-3,...]
Compiling architecture arch1 of entity cic_compiler_v4_0_14.compare [\compare(value=2,family=(p_dsp48...]
Compiling architecture rtl of entity cic_compiler_v4_0_14.counter [\counter(width=2,const_vals=(0,-...]
Compiling architecture struct_all of entity cic_compiler_v4_0_14.chan_cnt [\chan_cnt(family=(p_dsp48e1,fals...]
Compiling architecture dsp48e1_v of entity unisim.DSP48E1 [\DSP48E1(adreg=0,dreg=0,inmodere...]
Compiling architecture struct_all of entity cic_compiler_v4_0_14.delay [\delay(delay_len=0,family=(p_dsp...]
Compiling architecture struct_all of entity cic_compiler_v4_0_14.delay [\delay(delay_len=0,family=(p_dsp...]
Compiling architecture struct_all of entity cic_compiler_v4_0_14.emb_calc [\emb_calc(param=((p_dsp48e1,fals...]
Compiling architecture struct_all of entity cic_compiler_v4_0_14.delay_bit [\delay_bit(delay_len=0,family=(p...]
Compiling architecture struct_all of entity cic_compiler_v4_0_14.delay [\delay(delay_len=0,family=(p_dsp...]
Compiling architecture struct_all of entity cic_compiler_v4_0_14.delay_bit [\delay_bit(delay_len=2,family=(p...]
Compiling architecture struct_all of entity cic_compiler_v4_0_14.delay [\delay(delay_len=2,family=(p_dsp...]
Compiling architecture synth of entity cic_compiler_v4_0_14.int_comb_stage_unfolded [\int_comb_stage_unfolded(c_int_o...]
Compiling architecture struct_all of entity cic_compiler_v4_0_14.delay_bit [\delay_bit(delay_len=3,family=(p...]
Compiling architecture synth of entity cic_compiler_v4_0_14.int_comb_stage_unfolded [\int_comb_stage_unfolded(c_int_o...]
Compiling architecture synth of entity cic_compiler_v4_0_14.int_comb_section [\int_comb_section(c_int_or_comb=...]
Compiling architecture struct_all of entity cic_compiler_v4_0_14.delay_bit [\delay_bit(delay_len=1,family=(p...]
Compiling architecture struct_all of entity cic_compiler_v4_0_14.delay [\delay(delay_len=1,family=(p_dsp...]
Compiling architecture struct_all of entity cic_compiler_v4_0_14.emb_calc [\emb_calc(param=((p_dsp48e1,fals...]
Compiling architecture struct_all of entity cic_compiler_v4_0_14.delay [\delay(delay_len=18,family=(p_ds...]
Compiling architecture struct_all of entity cic_compiler_v4_0_14.delay_bit [\delay_bit(delay_len=7,family=(p...]
Compiling architecture synth of entity cic_compiler_v4_0_14.int_comb_stage_folded [\int_comb_stage_folded(c_int_or_...]
Compiling architecture synth of entity cic_compiler_v4_0_14.int_comb_section [\int_comb_section(c_int_or_comb=...]
Compiling architecture synth of entity cic_compiler_v4_0_14.decimate [\decimate(c_num_stages=5,c_rate=...]
Compiling architecture synth of entity cic_compiler_v4_0_14.cic_compiler_v4_0_14_viv [\cic_compiler_v4_0_14_viv(c_comp...]
Compiling architecture xilinx of entity cic_compiler_v4_0_14.cic_compiler_v4_0_14 [\cic_compiler_v4_0_14(c_componen...]
Compiling architecture pdm_to_pcm_cic_compiler_0_0_arch of entity xil_defaultlib.pdm_to_pcm_cic_compiler_0_0 [pdm_to_pcm_cic_compiler_0_0_defa...]
Compiling architecture bufr_v of entity unisim.BUFR [\BUFR(bufr_divide="2")(1,1)(1,7)...]
Compiling architecture behavioral of entity work.clk_div [clk_div_default]
Compiling architecture pdm_to_pcm_clk_div_0_0_arch of entity xil_defaultlib.pdm_to_pcm_clk_div_0_0 [pdm_to_pcm_clk_div_0_0_default]
Compiling architecture pdm_to_pcm_clk_div_1_0_arch of entity xil_defaultlib.pdm_to_pcm_clk_div_1_0 [pdm_to_pcm_clk_div_1_0_default]
Compiling module unisims_ver.IBUF
Compiling module unisims_ver.MMCME2_ADV(CLKFBOUT_MULT_F=10.0,...
Compiling module unisims_ver.BUFG
Compiling module xil_defaultlib.pdm_to_pcm_clk_wiz_0_0_clk_wiz
Compiling module xil_defaultlib.pdm_to_pcm_clk_wiz_0_0
Compiling architecture arch of entity work.demux_16 [demux_16_default]
Compiling architecture arch_demux16 of entity work.demux16_sync [demux16_sync_default]
Compiling architecture pdm_to_pcm_demux16_sync_0_0_arch of entity xil_defaultlib.pdm_to_pcm_demux16_sync_0_0 [pdm_to_pcm_demux16_sync_0_0_defa...]
Compiling architecture behavior of entity work.energy_compare [energy_compare_default]
Compiling architecture pdm_to_pcm_energy_compare_0_0_arch of entity xil_defaultlib.pdm_to_pcm_energy_compare_0_0 [pdm_to_pcm_energy_compare_0_0_de...]
Compiling module fifo_generator_v13_2_4.fifo_generator_v13_2_4_sync_stag...
Compiling module fifo_generator_v13_2_4.fifo_generator_v13_2_4_bhv_ver_a...
Compiling module fifo_generator_v13_2_4.fifo_generator_v13_2_4_bhv_ver_p...
Compiling module fifo_generator_v13_2_4.fifo_generator_v13_2_4_CONV_VER(...
Compiling module fifo_generator_v13_2_4.fifo_generator_vlog_beh(C_DATA_C...
Compiling module xil_defaultlib.pdm_to_pcm_fifo_generator_0_0
Compiling architecture xilinx of entity axi_utils_v2_0_6.glb_srl_fifo [\glb_srl_fifo(width=23,has_ifx=t...]
Compiling architecture xilinx of entity axi_utils_v2_0_6.glb_ifx_slave [\glb_ifx_slave(width=23,has_ifx=...]
Compiling architecture synth of entity fir_compiler_v7_2_12.delay [\delay(c_delay_len=0,c_xdevicefa...]
Compiling architecture synth of entity fir_compiler_v7_2_12.dpr_mem [\dpr_mem(c_xdevicefamily="artix7...]
Compiling architecture synth of entity fir_compiler_v7_2_12.delay [\delay(c_delay_len=0,c_xdevicefa...]
Compiling architecture synth of entity fir_compiler_v7_2_12.delay [\delay(c_delay_len=1,c_xdevicefa...]
Compiling architecture synth of entity fir_compiler_v7_2_12.delay [\delay(c_delay_len=3,c_xdevicefa...]
Compiling architecture synth of entity fir_compiler_v7_2_12.delay [\delay(c_delay_len=2,c_xdevicefa...]
Compiling architecture synth of entity fir_compiler_v7_2_12.sp_mem [\sp_mem(c_xdevicefamily="artix7"...]
Compiling architecture synth of entity fir_compiler_v7_2_12.filt_mem [\filt_mem(c_xdevicefamily="artix...]
Compiling architecture synth of entity fir_compiler_v7_2_12.sp_mem [\sp_mem(c_xdevicefamily="artix7"...]
Compiling architecture synth of entity fir_compiler_v7_2_12.filt_mem [\filt_mem(c_xdevicefamily="artix...]
Compiling architecture synth of entity fir_compiler_v7_2_12.cntrl_delay [\cntrl_delay(c_delay_len=0,c_mem...]
Compiling architecture synth of entity fir_compiler_v7_2_12.delay [\delay(c_delay_len=7,c_xdevicefa...]
Compiling architecture synth of entity fir_compiler_v7_2_12.buff [\buff(c_xdevicefamily="artix7",c...]
Compiling architecture synth of entity fir_compiler_v7_2_12.delay [\delay(c_delay_len=0,c_xdevicefa...]
Compiling architecture synth of entity fir_compiler_v7_2_12.delay [\delay(c_delay_len=0,c_xdevicefa...]
Compiling architecture synth of entity fir_compiler_v7_2_12.delay [\delay(c_delay_len=0,c_xdevicefa...]
Compiling architecture dsp48e1_v of entity unisim.DSP48E1 [\DSP48E1(mask="11111111111111111...]
Compiling architecture synth of entity fir_compiler_v7_2_12.calc [\calc(c_xdevicefamily="artix7",c...]
Compiling architecture synth of entity fir_compiler_v7_2_12.addsub_mult_accum [\addsub_mult_accum(c_xdevicefami...]
Compiling architecture synth of entity fir_compiler_v7_2_12.delay [\delay(c_delay_len=0,c_xdevicefa...]
Compiling architecture synth of entity fir_compiler_v7_2_12.delay [\delay(c_delay_len=0,c_xdevicefa...]
Compiling architecture synth of entity fir_compiler_v7_2_12.delay [\delay(c_delay_len=2,c_xdevicefa...]
Compiling architecture synth of entity fir_compiler_v7_2_12.delay [\delay(c_delay_len=5,c_xdevicefa...]
Compiling architecture synth of entity fir_compiler_v7_2_12.delay [\delay(c_delay_len=2,c_xdevicefa...]
Compiling architecture synth of entity fir_compiler_v7_2_12.dpr_mem [\dpr_mem(c_xdevicefamily="artix7...]
Compiling architecture synth of entity fir_compiler_v7_2_12.delay [\delay(c_delay_len=2,c_xdevicefa...]
Compiling architecture synth of entity fir_compiler_v7_2_12.delay [\delay(c_delay_len=6,c_xdevicefa...]
Compiling architecture synth of entity fir_compiler_v7_2_12.delay [\delay(c_delay_len=7,c_xdevicefa...]
Compiling architecture synth of entity fir_compiler_v7_2_12.delay [\delay(c_delay_len=9,c_xdevicefa...]
Compiling architecture xilinx of entity axi_utils_v2_0_6.glb_srl_fifo [\glb_srl_fifo(width=23,has_uvpro...]
Compiling architecture xilinx of entity axi_utils_v2_0_6.glb_ifx_master [\glb_ifx_master(width=23)\]
Compiling architecture synth of entity fir_compiler_v7_2_12.halfband_decimation [\halfband_decimation(c_xdevicefa...]
Compiling architecture synth of entity fir_compiler_v7_2_12.fir_compiler_v7_2_12_viv [\fir_compiler_v7_2_12_viv(c_xdev...]
Compiling architecture xilinx of entity fir_compiler_v7_2_12.fir_compiler_v7_2_12 [\fir_compiler_v7_2_12(c_xdevicef...]
Compiling architecture pdm_to_pcm_fir_compiler_0_0_arch of entity xil_defaultlib.pdm_to_pcm_fir_compiler_0_0 [pdm_to_pcm_fir_compiler_0_0_defa...]
Compiling architecture synth of entity fir_compiler_v7_2_12.delay [\delay(c_delay_len=4,c_xdevicefa...]
Compiling architecture synth of entity fir_compiler_v7_2_12.cntrl_delay [\cntrl_delay(c_delay_len=0,c_mem...]
Compiling architecture synth of entity fir_compiler_v7_2_12.dpt_mem [\dpt_mem(c_xdevicefamily="artix7...]
Compiling architecture synth of entity fir_compiler_v7_2_12.filt_mem [\filt_mem(c_xdevicefamily="artix...]
Compiling architecture synth of entity fir_compiler_v7_2_12.filt_mem [\filt_mem(c_xdevicefamily="artix...]
Compiling architecture synth of entity fir_compiler_v7_2_12.filt_mem [\filt_mem(c_xdevicefamily="artix...]
Compiling architecture synth of entity fir_compiler_v7_2_12.sp_mem [\sp_mem(c_xdevicefamily="artix7"...]
Compiling architecture synth of entity fir_compiler_v7_2_12.sp_mem [\sp_mem(c_xdevicefamily="artix7"...]
Compiling architecture synth of entity fir_compiler_v7_2_12.filt_mem [\filt_mem(c_xdevicefamily="artix...]
Compiling architecture synth of entity fir_compiler_v7_2_12.sp_mem [\sp_mem(c_xdevicefamily="artix7"...]
Compiling architecture synth of entity fir_compiler_v7_2_12.filt_mem [\filt_mem(c_xdevicefamily="artix...]
Compiling architecture synth of entity fir_compiler_v7_2_12.cntrl_delay [\cntrl_delay(c_delay_len=0,c_mem...]
Compiling architecture synth of entity fir_compiler_v7_2_12.delay [\delay(c_delay_len=3,c_xdevicefa...]
Compiling architecture synth of entity fir_compiler_v7_2_12.buff [\buff(c_xdevicefamily="artix7",c...]
Compiling architecture synth of entity fir_compiler_v7_2_12.delay [\delay(c_delay_len=5,c_xdevicefa...]
Compiling architecture synth of entity fir_compiler_v7_2_12.buff [\buff(c_xdevicefamily="artix7",c...]
Compiling architecture synth of entity fir_compiler_v7_2_12.delay [\delay(c_delay_len=4,c_xdevicefa...]
Compiling architecture synth of entity fir_compiler_v7_2_12.buff [\buff(c_xdevicefamily="artix7",c...]
Compiling architecture synth of entity fir_compiler_v7_2_12.delay [\delay(c_delay_len=0,c_xdevicefa...]
Compiling architecture synth of entity fir_compiler_v7_2_12.delay [\delay(c_delay_len=0,c_xdevicefa...]
Compiling architecture synth of entity fir_compiler_v7_2_12.delay [\delay(c_delay_len=0,c_xdevicefa...]
Compiling architecture synth of entity fir_compiler_v7_2_12.delay [\delay(c_delay_len=0,c_xdevicefa...]
Compiling architecture synth of entity fir_compiler_v7_2_12.delay [\delay(c_delay_len=0,c_xdevicefa...]
Compiling architecture structural of entity fir_compiler_v7_2_12.add_sub [\add_sub(c_xdevicefamily="artix7...]
Compiling architecture dsp48e1_v of entity unisim.DSP48E1 [\DSP48E1(inmodereg=0,mask="11111...]
Compiling architecture synth of entity fir_compiler_v7_2_12.calc [\calc(c_xdevicefamily="artix7",c...]
WARNING: [VRFC 10-516] comparison between unequal length arrays always returns FALSE [/wrk/2019.1/continuous/2019_05_24_2552052/packages/customer/vivado/data/ip/xilinx/xbip_utils_v3_0/hdl/xbip_utils_v3_0_vh_rfs.vhd:2056]
WARNING: [VRFC 10-516] comparison between unequal length arrays always returns FALSE [/wrk/2019.1/continuous/2019_05_24_2552052/packages/customer/vivado/data/ip/xilinx/xbip_utils_v3_0/hdl/xbip_utils_v3_0_vh_rfs.vhd:2058]
WARNING: [VRFC 10-516] comparison between unequal length arrays always returns FALSE [/wrk/2019.1/continuous/2019_05_24_2552052/packages/customer/vivado/data/ip/xilinx/xbip_utils_v3_0/hdl/xbip_utils_v3_0_vh_rfs.vhd:2059]
WARNING: [VRFC 10-516] comparison between unequal length arrays always returns FALSE [/wrk/2019.1/continuous/2019_05_24_2552052/packages/customer/vivado/data/ip/xilinx/xbip_utils_v3_0/hdl/xbip_utils_v3_0_vh_rfs.vhd:2060]
WARNING: [VRFC 10-516] comparison between unequal length arrays always returns FALSE [/wrk/2019.1/continuous/2019_05_24_2552052/packages/customer/vivado/data/ip/xilinx/xbip_utils_v3_0/hdl/xbip_utils_v3_0_vh_rfs.vhd:2046]
WARNING: [VRFC 10-516] comparison between unequal length arrays always returns FALSE [/wrk/2019.1/continuous/2019_05_24_2552052/packages/customer/vivado/data/ip/xilinx/xbip_utils_v3_0/hdl/xbip_utils_v3_0_vh_rfs.vhd:2047]
WARNING: [VRFC 10-516] comparison between unequal length arrays always returns FALSE [/wrk/2019.1/continuous/2019_05_24_2552052/packages/customer/vivado/data/ip/xilinx/xbip_utils_v3_0/hdl/xbip_utils_v3_0_vh_rfs.vhd:2049]
WARNING: [VRFC 10-516] comparison between unequal length arrays always returns FALSE [/wrk/2019.1/continuous/2019_05_24_2552052/packages/customer/vivado/data/ip/xilinx/xbip_utils_v3_0/hdl/xbip_utils_v3_0_vh_rfs.vhd:2050]
Compiling architecture synth of entity fir_compiler_v7_2_12.addsub_mult_add [\addsub_mult_add(c_xdevicefamily...]
WARNING: [VRFC 10-516] comparison between unequal length arrays always returns FALSE [/wrk/2019.1/continuous/2019_05_24_2552052/packages/customer/vivado/data/ip/xilinx/xbip_utils_v3_0/hdl/xbip_utils_v3_0_vh_rfs.vhd:2056]
WARNING: [VRFC 10-516] comparison between unequal length arrays always returns FALSE [/wrk/2019.1/continuous/2019_05_24_2552052/packages/customer/vivado/data/ip/xilinx/xbip_utils_v3_0/hdl/xbip_utils_v3_0_vh_rfs.vhd:2058]
WARNING: [VRFC 10-516] comparison between unequal length arrays always returns FALSE [/wrk/2019.1/continuous/2019_05_24_2552052/packages/customer/vivado/data/ip/xilinx/xbip_utils_v3_0/hdl/xbip_utils_v3_0_vh_rfs.vhd:2059]
WARNING: [VRFC 10-516] comparison between unequal length arrays always returns FALSE [/wrk/2019.1/continuous/2019_05_24_2552052/packages/customer/vivado/data/ip/xilinx/xbip_utils_v3_0/hdl/xbip_utils_v3_0_vh_rfs.vhd:2060]
WARNING: [VRFC 10-516] comparison between unequal length arrays always returns FALSE [/wrk/2019.1/continuous/2019_05_24_2552052/packages/customer/vivado/data/ip/xilinx/xbip_utils_v3_0/hdl/xbip_utils_v3_0_vh_rfs.vhd:2046]
WARNING: [VRFC 10-516] comparison between unequal length arrays always returns FALSE [/wrk/2019.1/continuous/2019_05_24_2552052/packages/customer/vivado/data/ip/xilinx/xbip_utils_v3_0/hdl/xbip_utils_v3_0_vh_rfs.vhd:2047]
WARNING: [VRFC 10-516] comparison between unequal length arrays always returns FALSE [/wrk/2019.1/continuous/2019_05_24_2552052/packages/customer/vivado/data/ip/xilinx/xbip_utils_v3_0/hdl/xbip_utils_v3_0_vh_rfs.vhd:2049]
WARNING: [VRFC 10-516] comparison between unequal length arrays always returns FALSE [/wrk/2019.1/continuous/2019_05_24_2552052/packages/customer/vivado/data/ip/xilinx/xbip_utils_v3_0/hdl/xbip_utils_v3_0_vh_rfs.vhd:2050]
Compiling architecture synth of entity fir_compiler_v7_2_12.addsub_mult_add [\addsub_mult_add(c_xdevicefamily...]
WARNING: [VRFC 10-516] comparison between unequal length arrays always returns FALSE [/wrk/2019.1/continuous/2019_05_24_2552052/packages/customer/vivado/data/ip/xilinx/xbip_utils_v3_0/hdl/xbip_utils_v3_0_vh_rfs.vhd:2056]
WARNING: [VRFC 10-516] comparison between unequal length arrays always returns FALSE [/wrk/2019.1/continuous/2019_05_24_2552052/packages/customer/vivado/data/ip/xilinx/xbip_utils_v3_0/hdl/xbip_utils_v3_0_vh_rfs.vhd:2058]
WARNING: [VRFC 10-516] comparison between unequal length arrays always returns FALSE [/wrk/2019.1/continuous/2019_05_24_2552052/packages/customer/vivado/data/ip/xilinx/xbip_utils_v3_0/hdl/xbip_utils_v3_0_vh_rfs.vhd:2059]
WARNING: [VRFC 10-516] comparison between unequal length arrays always returns FALSE [/wrk/2019.1/continuous/2019_05_24_2552052/packages/customer/vivado/data/ip/xilinx/xbip_utils_v3_0/hdl/xbip_utils_v3_0_vh_rfs.vhd:2060]
WARNING: [VRFC 10-516] comparison between unequal length arrays always returns FALSE [/wrk/2019.1/continuous/2019_05_24_2552052/packages/customer/vivado/data/ip/xilinx/xbip_utils_v3_0/hdl/xbip_utils_v3_0_vh_rfs.vhd:2046]
WARNING: [VRFC 10-516] comparison between unequal length arrays always returns FALSE [/wrk/2019.1/continuous/2019_05_24_2552052/packages/customer/vivado/data/ip/xilinx/xbip_utils_v3_0/hdl/xbip_utils_v3_0_vh_rfs.vhd:2047]
WARNING: [VRFC 10-516] comparison between unequal length arrays always returns FALSE [/wrk/2019.1/continuous/2019_05_24_2552052/packages/customer/vivado/data/ip/xilinx/xbip_utils_v3_0/hdl/xbip_utils_v3_0_vh_rfs.vhd:2049]
WARNING: [VRFC 10-516] comparison between unequal length arrays always returns FALSE [/wrk/2019.1/continuous/2019_05_24_2552052/packages/customer/vivado/data/ip/xilinx/xbip_utils_v3_0/hdl/xbip_utils_v3_0_vh_rfs.vhd:2050]
Compiling architecture synth of entity fir_compiler_v7_2_12.delay [\delay(c_delay_len=0,c_xdevicefa...]
Compiling architecture dsp48e1_v of entity unisim.DSP48E1 [\DSP48E1(inmodereg=0,mask="11111...]
Compiling architecture synth of entity fir_compiler_v7_2_12.delay [\delay(c_delay_len=0,c_xdevicefa...]
Compiling architecture synth of entity fir_compiler_v7_2_12.delay [\delay(c_delay_len=0,c_xdevicefa...]
Compiling architecture synth of entity fir_compiler_v7_2_12.calc [\calc(c_xdevicefamily="artix7",c...]
Compiling architecture synth of entity fir_compiler_v7_2_12.add_accum [\add_accum(c_xdevicefamily="arti...]
Compiling architecture synth of entity fir_compiler_v7_2_12.calc [\calc(c_xdevicefamily="artix7",c...]
WARNING: [VRFC 10-516] comparison between unequal length arrays always returns FALSE [/wrk/2019.1/continuous/2019_05_24_2552052/packages/customer/vivado/data/ip/xilinx/xbip_utils_v3_0/hdl/xbip_utils_v3_0_vh_rfs.vhd:2056]
WARNING: [VRFC 10-516] comparison between unequal length arrays always returns FALSE [/wrk/2019.1/continuous/2019_05_24_2552052/packages/customer/vivado/data/ip/xilinx/xbip_utils_v3_0/hdl/xbip_utils_v3_0_vh_rfs.vhd:2058]
WARNING: [VRFC 10-516] comparison between unequal length arrays always returns FALSE [/wrk/2019.1/continuous/2019_05_24_2552052/packages/customer/vivado/data/ip/xilinx/xbip_utils_v3_0/hdl/xbip_utils_v3_0_vh_rfs.vhd:2059]
WARNING: [VRFC 10-516] comparison between unequal length arrays always returns FALSE [/wrk/2019.1/continuous/2019_05_24_2552052/packages/customer/vivado/data/ip/xilinx/xbip_utils_v3_0/hdl/xbip_utils_v3_0_vh_rfs.vhd:2060]
WARNING: [VRFC 10-516] comparison between unequal length arrays always returns FALSE [/wrk/2019.1/continuous/2019_05_24_2552052/packages/customer/vivado/data/ip/xilinx/xbip_utils_v3_0/hdl/xbip_utils_v3_0_vh_rfs.vhd:2046]
WARNING: [VRFC 10-516] comparison between unequal length arrays always returns FALSE [/wrk/2019.1/continuous/2019_05_24_2552052/packages/customer/vivado/data/ip/xilinx/xbip_utils_v3_0/hdl/xbip_utils_v3_0_vh_rfs.vhd:2047]
WARNING: [VRFC 10-516] comparison between unequal length arrays always returns FALSE [/wrk/2019.1/continuous/2019_05_24_2552052/packages/customer/vivado/data/ip/xilinx/xbip_utils_v3_0/hdl/xbip_utils_v3_0_vh_rfs.vhd:2049]
WARNING: [VRFC 10-516] comparison between unequal length arrays always returns FALSE [/wrk/2019.1/continuous/2019_05_24_2552052/packages/customer/vivado/data/ip/xilinx/xbip_utils_v3_0/hdl/xbip_utils_v3_0_vh_rfs.vhd:2050]
Compiling architecture synth of entity fir_compiler_v7_2_12.addsub_mult_add [\addsub_mult_add(c_xdevicefamily...]
WARNING: [VRFC 10-516] comparison between unequal length arrays always returns FALSE [/wrk/2019.1/continuous/2019_05_24_2552052/packages/customer/vivado/data/ip/xilinx/xbip_utils_v3_0/hdl/xbip_utils_v3_0_vh_rfs.vhd:2056]
WARNING: [VRFC 10-516] comparison between unequal length arrays always returns FALSE [/wrk/2019.1/continuous/2019_05_24_2552052/packages/customer/vivado/data/ip/xilinx/xbip_utils_v3_0/hdl/xbip_utils_v3_0_vh_rfs.vhd:2058]
WARNING: [VRFC 10-516] comparison between unequal length arrays always returns FALSE [/wrk/2019.1/continuous/2019_05_24_2552052/packages/customer/vivado/data/ip/xilinx/xbip_utils_v3_0/hdl/xbip_utils_v3_0_vh_rfs.vhd:2059]
WARNING: [VRFC 10-516] comparison between unequal length arrays always returns FALSE [/wrk/2019.1/continuous/2019_05_24_2552052/packages/customer/vivado/data/ip/xilinx/xbip_utils_v3_0/hdl/xbip_utils_v3_0_vh_rfs.vhd:2060]
WARNING: [VRFC 10-516] comparison between unequal length arrays always returns FALSE [/wrk/2019.1/continuous/2019_05_24_2552052/packages/customer/vivado/data/ip/xilinx/xbip_utils_v3_0/hdl/xbip_utils_v3_0_vh_rfs.vhd:2046]
WARNING: [VRFC 10-516] comparison between unequal length arrays always returns FALSE [/wrk/2019.1/continuous/2019_05_24_2552052/packages/customer/vivado/data/ip/xilinx/xbip_utils_v3_0/hdl/xbip_utils_v3_0_vh_rfs.vhd:2047]
WARNING: [VRFC 10-516] comparison between unequal length arrays always returns FALSE [/wrk/2019.1/continuous/2019_05_24_2552052/packages/customer/vivado/data/ip/xilinx/xbip_utils_v3_0/hdl/xbip_utils_v3_0_vh_rfs.vhd:2049]
WARNING: [VRFC 10-516] comparison between unequal length arrays always returns FALSE [/wrk/2019.1/continuous/2019_05_24_2552052/packages/customer/vivado/data/ip/xilinx/xbip_utils_v3_0/hdl/xbip_utils_v3_0_vh_rfs.vhd:2050]
Compiling architecture synth of entity fir_compiler_v7_2_12.addsub_mult_add [\addsub_mult_add(c_xdevicefamily...]
WARNING: [VRFC 10-516] comparison between unequal length arrays always returns FALSE [/wrk/2019.1/continuous/2019_05_24_2552052/packages/customer/vivado/data/ip/xilinx/xbip_utils_v3_0/hdl/xbip_utils_v3_0_vh_rfs.vhd:2056]
WARNING: [VRFC 10-516] comparison between unequal length arrays always returns FALSE [/wrk/2019.1/continuous/2019_05_24_2552052/packages/customer/vivado/data/ip/xilinx/xbip_utils_v3_0/hdl/xbip_utils_v3_0_vh_rfs.vhd:2058]
WARNING: [VRFC 10-516] comparison between unequal length arrays always returns FALSE [/wrk/2019.1/continuous/2019_05_24_2552052/packages/customer/vivado/data/ip/xilinx/xbip_utils_v3_0/hdl/xbip_utils_v3_0_vh_rfs.vhd:2059]
WARNING: [VRFC 10-516] comparison between unequal length arrays always returns FALSE [/wrk/2019.1/continuous/2019_05_24_2552052/packages/customer/vivado/data/ip/xilinx/xbip_utils_v3_0/hdl/xbip_utils_v3_0_vh_rfs.vhd:2060]
WARNING: [VRFC 10-516] comparison between unequal length arrays always returns FALSE [/wrk/2019.1/continuous/2019_05_24_2552052/packages/customer/vivado/data/ip/xilinx/xbip_utils_v3_0/hdl/xbip_utils_v3_0_vh_rfs.vhd:2046]
WARNING: [VRFC 10-516] comparison between unequal length arrays always returns FALSE [/wrk/2019.1/continuous/2019_05_24_2552052/packages/customer/vivado/data/ip/xilinx/xbip_utils_v3_0/hdl/xbip_utils_v3_0_vh_rfs.vhd:2047]
WARNING: [VRFC 10-516] comparison between unequal length arrays always returns FALSE [/wrk/2019.1/continuous/2019_05_24_2552052/packages/customer/vivado/data/ip/xilinx/xbip_utils_v3_0/hdl/xbip_utils_v3_0_vh_rfs.vhd:2049]
WARNING: [VRFC 10-516] comparison between unequal length arrays always returns FALSE [/wrk/2019.1/continuous/2019_05_24_2552052/packages/customer/vivado/data/ip/xilinx/xbip_utils_v3_0/hdl/xbip_utils_v3_0_vh_rfs.vhd:2050]
Compiling architecture synth of entity fir_compiler_v7_2_12.calc [\calc(c_xdevicefamily="artix7",c...]
Compiling architecture synth of entity fir_compiler_v7_2_12.add_accum [\add_accum(c_xdevicefamily="arti...]
Compiling architecture synth of entity fir_compiler_v7_2_12.delay [\delay(c_delay_len=1,c_xdevicefa...]
Compiling architecture synth of entity fir_compiler_v7_2_12.delay [\delay(c_delay_len=0,c_xdevicefa...]
Compiling architecture synth of entity fir_compiler_v7_2_12.delay [\delay(c_delay_len=0,c_xdevicefa...]
Compiling architecture synth of entity fir_compiler_v7_2_12.delay [\delay(c_delay_len=3,c_xdevicefa...]
Compiling architecture synth of entity fir_compiler_v7_2_12.delay [\delay(c_delay_len=0,c_xdevicefa...]
Compiling architecture synth of entity fir_compiler_v7_2_12.delay [\delay(c_delay_len=1,c_xdevicefa...]
Compiling architecture synth of entity fir_compiler_v7_2_12.delay [\delay(c_delay_len=12,c_xdevicef...]
Compiling architecture synth of entity fir_compiler_v7_2_12.delay [\delay(c_delay_len=0,c_xdevicefa...]
Compiling architecture synth of entity fir_compiler_v7_2_12.delay [\delay(c_delay_len=0,c_xdevicefa...]
Compiling architecture synth of entity fir_compiler_v7_2_12.calc [\calc(c_xdevicefamily="artix7",c...]
Compiling architecture synth of entity fir_compiler_v7_2_12.add_accum [\add_accum(c_xdevicefamily="arti...]
Compiling architecture synth of entity fir_compiler_v7_2_12.delay [\delay(c_delay_len=2,c_xdevicefa...]
Compiling architecture synth of entity fir_compiler_v7_2_12.ext_mult [\ext_mult(c_xdevicefamily="artix...]
Compiling architecture synth of entity fir_compiler_v7_2_12.single_rate [\single_rate(c_xdevicefamily="ar...]
Compiling architecture synth of entity fir_compiler_v7_2_12.fir_compiler_v7_2_12_viv [\fir_compiler_v7_2_12_viv(c_xdev...]
Compiling architecture xilinx of entity fir_compiler_v7_2_12.fir_compiler_v7_2_12 [\fir_compiler_v7_2_12(c_xdevicef...]
Compiling architecture pdm_to_pcm_fir_compiler_1_0_arch of entity xil_defaultlib.pdm_to_pcm_fir_compiler_1_0 [pdm_to_pcm_fir_compiler_1_0_defa...]
Compiling architecture behavioral of entity work.hp_filter [hp_filter_default]
Compiling architecture pdm_to_pcm_hp_filter_0_0_arch of entity xil_defaultlib.pdm_to_pcm_hp_filter_0_0 [pdm_to_pcm_hp_filter_0_0_default]
Compiling architecture lut2_v of entity unisim.LUT2 [\LUT2(init="1000")(0,3)\]
Compiling architecture mult_and_v of entity unisim.MULT_AND [mult_and_default]
Compiling architecture xilinx of entity mult_gen_v12_0_15.op_resize [\op_resize(ao_width=19,bo_width=...]
Compiling architecture xilinx of entity mult_gen_v12_0_15.luts [\luts(c_xdevicefamily="artix7",c...]
Compiling architecture xilinx of entity mult_gen_v12_0_15.mult_gen_v12_0_15_viv [\mult_gen_v12_0_15_viv(c_verbosi...]
Compiling architecture xilinx of entity mult_gen_v12_0_15.mult_gen_v12_0_15 [\mult_gen_v12_0_15(c_xdevicefami...]
Compiling architecture pdm_to_pcm_mult_gen_0_0_arch of entity xil_defaultlib.pdm_to_pcm_mult_gen_0_0 [pdm_to_pcm_mult_gen_0_0_default]
Compiling architecture behavior of entity work.scan [scan_default]
Compiling architecture pdm_to_pcm_scan_0_0_arch of entity xil_defaultlib.pdm_to_pcm_scan_0_0 [pdm_to_pcm_scan_0_0_default]
Compiling architecture arch of entity xil_defaultlib.timemux [timemux_default]
Compiling architecture pdm_to_pcm_timemux_0_2_arch of entity xil_defaultlib.pdm_to_pcm_timemux_0_2 [pdm_to_pcm_timemux_0_2_default]
Compiling architecture bufg_v of entity unisim.BUFG [bufg_default]
Compiling architecture imp of entity xil_defaultlib.util_ds_buf [\util_ds_buf(c_buf_type="BUFG",c...]
Compiling architecture pdm_to_pcm_util_ds_buf_0_0_arch of entity xil_defaultlib.pdm_to_pcm_util_ds_buf_0_0 [pdm_to_pcm_util_ds_buf_0_0_defau...]
Compiling module util_vector_logic_v2_0_1.util_vector_logic_v2_0_1_util_ve...
Compiling module xil_defaultlib.pdm_to_pcm_util_vector_logic_0_0
Compiling module xil_defaultlib.pdm_to_pcm_util_vector_logic_0_2
Compiling architecture structure of entity xil_defaultlib.pdm_to_pcm [pdm_to_pcm_default]
Compiling architecture tb of entity xil_defaultlib.test_pdm_to_pcm
Built simulation snapshot test_pdm_to_pcm_behav
