-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019
-- Date        : Wed Apr  8 23:04:42 2020
-- Host        : LAPTOP-RJQ3H7G3 running 64-bit major release  (build 9200)
-- Command     : write_vhdl -force -mode funcsim
--               D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/ip/mig/mig_sim_netlist.vhdl
-- Design      : mig
-- Purpose     : This VHDL netlist is a functional simulation representation of the design and should not be modified or
--               synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device      : xc7a200tfbg676-2
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mig_mig_7series_v4_2_arb_select is
  port (
    \col_mux.col_periodic_rd_r\ : out STD_LOGIC;
    col_rd_wr_r : out STD_LOGIC;
    cke_r : out STD_LOGIC;
    \rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][5]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
    \rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][0]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    \rank_final_loop[0].bank_final_loop[1].final_data_offset_mc_reg[0][11]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
    \rank_final_loop[0].bank_final_loop[1].final_data_offset_mc_reg[0][6]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    \rank_final_loop[0].bank_final_loop[2].final_data_offset_mc_reg[0][17]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
    O : out STD_LOGIC_VECTOR ( 0 to 0 );
    DIC : in STD_LOGIC_VECTOR ( 0 to 0 );
    cke_r_reg_0 : in STD_LOGIC;
    col_rd_wr : in STD_LOGIC;
    cke_r_reg_1 : in STD_LOGIC;
    mc_cke_ns : in STD_LOGIC_VECTOR ( 0 to 0 );
    \cmd_pipe_plus.mc_data_offset_reg[5]\ : in STD_LOGIC_VECTOR ( 5 downto 0 );
    \cmd_pipe_plus.mc_data_offset_1_reg[5]\ : in STD_LOGIC_VECTOR ( 5 downto 0 );
    \cmd_pipe_plus.mc_data_offset_2_reg[5]\ : in STD_LOGIC_VECTOR ( 5 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of mig_mig_7series_v4_2_arb_select : entity is "mig_7series_v4_2_arb_select";
end mig_mig_7series_v4_2_arb_select;

architecture STRUCTURE of mig_mig_7series_v4_2_arb_select is
  signal \mc_data_offset1_inferred__0/i__carry_n_0\ : STD_LOGIC;
  signal \mc_data_offset1_inferred__0/i__carry_n_1\ : STD_LOGIC;
  signal \mc_data_offset1_inferred__0/i__carry_n_2\ : STD_LOGIC;
  signal \mc_data_offset1_inferred__0/i__carry_n_3\ : STD_LOGIC;
  signal mc_data_offset_11_carry_n_0 : STD_LOGIC;
  signal mc_data_offset_11_carry_n_1 : STD_LOGIC;
  signal mc_data_offset_11_carry_n_2 : STD_LOGIC;
  signal mc_data_offset_11_carry_n_3 : STD_LOGIC;
  signal mc_data_offset_21_carry_n_0 : STD_LOGIC;
  signal mc_data_offset_21_carry_n_1 : STD_LOGIC;
  signal mc_data_offset_21_carry_n_2 : STD_LOGIC;
  signal mc_data_offset_21_carry_n_3 : STD_LOGIC;
  signal \NLW_mc_data_offset1_inferred__0/i__carry__0_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \NLW_mc_data_offset1_inferred__0/i__carry__0_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
  signal \NLW_mc_data_offset_11_carry__0_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \NLW_mc_data_offset_11_carry__0_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
  signal \NLW_mc_data_offset_21_carry__0_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \NLW_mc_data_offset_21_carry__0_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
begin
cke_r_reg: unisim.vcomponents.FDSE
     port map (
      C => cke_r_reg_0,
      CE => '1',
      D => mc_cke_ns(0),
      Q => cke_r,
      S => cke_r_reg_1
    );
\col_mux.col_periodic_rd_r_reg\: unisim.vcomponents.FDRE
     port map (
      C => cke_r_reg_0,
      CE => '1',
      D => DIC(0),
      Q => \col_mux.col_periodic_rd_r\,
      R => '0'
    );
\col_mux.col_rd_wr_r_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => cke_r_reg_0,
      CE => '1',
      D => col_rd_wr,
      Q => col_rd_wr_r,
      R => '0'
    );
\mc_data_offset1_inferred__0/i__carry\: unisim.vcomponents.CARRY4
     port map (
      CI => '0',
      CO(3) => \mc_data_offset1_inferred__0/i__carry_n_0\,
      CO(2) => \mc_data_offset1_inferred__0/i__carry_n_1\,
      CO(1) => \mc_data_offset1_inferred__0/i__carry_n_2\,
      CO(0) => \mc_data_offset1_inferred__0/i__carry_n_3\,
      CYINIT => \cmd_pipe_plus.mc_data_offset_reg[5]\(0),
      DI(3 downto 0) => \cmd_pipe_plus.mc_data_offset_reg[5]\(4 downto 1),
      O(3) => \rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][5]\(2),
      O(2) => \rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][0]\(0),
      O(1 downto 0) => \rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][5]\(1 downto 0),
      S(3 downto 0) => \cmd_pipe_plus.mc_data_offset_reg[5]\(4 downto 1)
    );
\mc_data_offset1_inferred__0/i__carry__0\: unisim.vcomponents.CARRY4
     port map (
      CI => \mc_data_offset1_inferred__0/i__carry_n_0\,
      CO(3 downto 0) => \NLW_mc_data_offset1_inferred__0/i__carry__0_CO_UNCONNECTED\(3 downto 0),
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3 downto 1) => \NLW_mc_data_offset1_inferred__0/i__carry__0_O_UNCONNECTED\(3 downto 1),
      O(0) => \rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][5]\(3),
      S(3 downto 1) => B"000",
      S(0) => \cmd_pipe_plus.mc_data_offset_reg[5]\(5)
    );
mc_data_offset_11_carry: unisim.vcomponents.CARRY4
     port map (
      CI => '0',
      CO(3) => mc_data_offset_11_carry_n_0,
      CO(2) => mc_data_offset_11_carry_n_1,
      CO(1) => mc_data_offset_11_carry_n_2,
      CO(0) => mc_data_offset_11_carry_n_3,
      CYINIT => \cmd_pipe_plus.mc_data_offset_1_reg[5]\(0),
      DI(3 downto 0) => \cmd_pipe_plus.mc_data_offset_1_reg[5]\(4 downto 1),
      O(3) => \rank_final_loop[0].bank_final_loop[1].final_data_offset_mc_reg[0][11]\(2),
      O(2) => \rank_final_loop[0].bank_final_loop[1].final_data_offset_mc_reg[0][6]\(0),
      O(1 downto 0) => \rank_final_loop[0].bank_final_loop[1].final_data_offset_mc_reg[0][11]\(1 downto 0),
      S(3 downto 0) => \cmd_pipe_plus.mc_data_offset_1_reg[5]\(4 downto 1)
    );
\mc_data_offset_11_carry__0\: unisim.vcomponents.CARRY4
     port map (
      CI => mc_data_offset_11_carry_n_0,
      CO(3 downto 0) => \NLW_mc_data_offset_11_carry__0_CO_UNCONNECTED\(3 downto 0),
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3 downto 1) => \NLW_mc_data_offset_11_carry__0_O_UNCONNECTED\(3 downto 1),
      O(0) => \rank_final_loop[0].bank_final_loop[1].final_data_offset_mc_reg[0][11]\(3),
      S(3 downto 1) => B"000",
      S(0) => \cmd_pipe_plus.mc_data_offset_1_reg[5]\(5)
    );
mc_data_offset_21_carry: unisim.vcomponents.CARRY4
     port map (
      CI => '0',
      CO(3) => mc_data_offset_21_carry_n_0,
      CO(2) => mc_data_offset_21_carry_n_1,
      CO(1) => mc_data_offset_21_carry_n_2,
      CO(0) => mc_data_offset_21_carry_n_3,
      CYINIT => \cmd_pipe_plus.mc_data_offset_2_reg[5]\(0),
      DI(3 downto 0) => \cmd_pipe_plus.mc_data_offset_2_reg[5]\(4 downto 1),
      O(3) => \rank_final_loop[0].bank_final_loop[2].final_data_offset_mc_reg[0][17]\(2),
      O(2) => O(0),
      O(1 downto 0) => \rank_final_loop[0].bank_final_loop[2].final_data_offset_mc_reg[0][17]\(1 downto 0),
      S(3 downto 0) => \cmd_pipe_plus.mc_data_offset_2_reg[5]\(4 downto 1)
    );
\mc_data_offset_21_carry__0\: unisim.vcomponents.CARRY4
     port map (
      CI => mc_data_offset_21_carry_n_0,
      CO(3 downto 0) => \NLW_mc_data_offset_21_carry__0_CO_UNCONNECTED\(3 downto 0),
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3 downto 1) => \NLW_mc_data_offset_21_carry__0_O_UNCONNECTED\(3 downto 1),
      O(0) => \rank_final_loop[0].bank_final_loop[2].final_data_offset_mc_reg[0][17]\(3),
      S(3 downto 1) => B"000",
      S(0) => \cmd_pipe_plus.mc_data_offset_2_reg[5]\(5)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mig_mig_7series_v4_2_bank_common is
  port (
    accept_internal_r_reg_0 : out STD_LOGIC;
    periodic_rd_ack_r_lcl_reg_0 : out STD_LOGIC;
    accept_r_reg_0 : out STD_LOGIC;
    accept_ns : out STD_LOGIC;
    was_wr : out STD_LOGIC;
    hi_priority : out STD_LOGIC;
    \generate_maint_cmds.insert_maint_r_lcl_reg_0\ : out STD_LOGIC;
    \maint_controller.maint_wip_r_lcl_reg_0\ : out STD_LOGIC;
    periodic_rd_cntr_r_reg_0 : out STD_LOGIC;
    req_wr_r_lcl0 : out STD_LOGIC;
    clear_periodic_rd_request : out STD_LOGIC;
    accept_r_reg_1 : out STD_LOGIC;
    set_order_q : out STD_LOGIC;
    accept_r_reg_2 : out STD_LOGIC;
    set_order_q_22 : out STD_LOGIC;
    accept_r_reg_3 : out STD_LOGIC;
    set_order_q_23 : out STD_LOGIC;
    accept_r_reg_4 : out STD_LOGIC;
    set_order_q_24 : out STD_LOGIC;
    periodic_rd_insert : out STD_LOGIC;
    Q : out STD_LOGIC_VECTOR ( 3 downto 0 );
    q_has_priority_r_reg : out STD_LOGIC;
    q_has_priority_r_reg_0 : out STD_LOGIC;
    idle_r_lcl_reg : out STD_LOGIC;
    periodic_rd_ack_r_lcl_reg_1 : out STD_LOGIC;
    q_has_priority_r_reg_1 : out STD_LOGIC;
    rb_hit_busy_r_reg : out STD_LOGIC;
    q_has_priority_r_reg_2 : out STD_LOGIC;
    rb_hit_busy_r_reg_0 : out STD_LOGIC;
    \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[4]_0\ : out STD_LOGIC;
    \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[7]_0\ : out STD_LOGIC;
    \maint_controller.maint_hit_busies_r_reg[3]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
    p_9_in : in STD_LOGIC;
    \maint_controller.maint_wip_r_lcl_reg_1\ : in STD_LOGIC;
    maint_srx_r : in STD_LOGIC;
    \maint_controller.maint_wip_r_lcl_reg_2\ : in STD_LOGIC;
    \maint_controller.maint_wip_r_lcl_reg_3\ : in STD_LOGIC;
    periodic_rd_cntr_r_reg_1 : in STD_LOGIC;
    periodic_rd_cntr_r_reg_2 : in STD_LOGIC;
    periodic_rd_r : in STD_LOGIC;
    cmd : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \periodic_read_request.periodic_rd_grant_r\ : in STD_LOGIC;
    \maint_controller.maint_hit_busies_r_reg[3]_1\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
    \i___6_i_1\ : in STD_LOGIC;
    use_addr : in STD_LOGIC;
    E : in STD_LOGIC_VECTOR ( 0 to 0 );
    \i___5_i_1\ : in STD_LOGIC;
    \q_entry_r_reg[0]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \i___3_i_2\ : in STD_LOGIC;
    \q_entry_r_reg[0]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \i___4_i_1\ : in STD_LOGIC;
    \q_entry_r_reg[0]_1\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    head_r : in STD_LOGIC_VECTOR ( 3 downto 0 );
    \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[3]_0\ : in STD_LOGIC;
    \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[1]_0\ : in STD_LOGIC;
    \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[3]_1\ : in STD_LOGIC;
    maint_req_r : in STD_LOGIC;
    q_has_priority : in STD_LOGIC;
    rb_hit_busy_r : in STD_LOGIC_VECTOR ( 3 downto 0 );
    q_has_priority_0 : in STD_LOGIC;
    q_has_priority_1 : in STD_LOGIC;
    q_has_priority_2 : in STD_LOGIC;
    \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[0]_0\ : in STD_LOGIC;
    \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[4]_1\ : in STD_LOGIC;
    maint_zq_r : in STD_LOGIC;
    was_priority_reg_0 : in STD_LOGIC;
    \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[7]_1\ : in STD_LOGIC_VECTOR ( 1 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of mig_mig_7series_v4_2_bank_common : entity is "mig_7series_v4_2_bank_common";
end mig_mig_7series_v4_2_bank_common;

architecture STRUCTURE of mig_mig_7series_v4_2_bank_common is
  signal \^q\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \^accept_internal_r_reg_0\ : STD_LOGIC;
  signal \^accept_ns\ : STD_LOGIC;
  signal \^accept_r_reg_0\ : STD_LOGIC;
  signal \generate_maint_cmds.insert_maint_ns\ : STD_LOGIC;
  signal \^generate_maint_cmds.insert_maint_r_lcl_reg_0\ : STD_LOGIC;
  signal \^hi_priority\ : STD_LOGIC;
  signal \maint_controller.maint_rdy\ : STD_LOGIC;
  signal \maint_controller.maint_rdy_r1\ : STD_LOGIC;
  signal \maint_controller.maint_rdy_r1_i_2_n_0\ : STD_LOGIC;
  signal \maint_controller.maint_srx_r1\ : STD_LOGIC;
  signal \^maint_controller.maint_wip_r_lcl_reg_0\ : STD_LOGIC;
  signal periodic_rd_ack_ns : STD_LOGIC;
  signal \^periodic_rd_ack_r_lcl_reg_0\ : STD_LOGIC;
  signal \^periodic_rd_ack_r_lcl_reg_1\ : STD_LOGIC;
  signal \^periodic_rd_cntr_r_reg_0\ : STD_LOGIC;
  signal \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_ns\ : STD_LOGIC_VECTOR ( 6 downto 1 );
  signal \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r\ : STD_LOGIC_VECTOR ( 7 downto 4 );
  signal \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r[7]_i_1_n_0\ : STD_LOGIC;
  signal \^rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[4]_0\ : STD_LOGIC;
  signal \^set_order_q\ : STD_LOGIC;
  signal \^set_order_q_22\ : STD_LOGIC;
  signal \^set_order_q_23\ : STD_LOGIC;
  signal \^set_order_q_24\ : STD_LOGIC;
  signal was_priority : STD_LOGIC;
  signal was_wr0 : STD_LOGIC;
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of accept_r_i_1 : label is "soft_lutpair1192";
  attribute SOFT_HLUTNM of \i___20_i_3\ : label is "soft_lutpair1194";
  attribute SOFT_HLUTNM of \i___34_i_2\ : label is "soft_lutpair1193";
  attribute SOFT_HLUTNM of \i___7_i_2\ : label is "soft_lutpair1194";
  attribute SOFT_HLUTNM of \i___8_i_2\ : label is "soft_lutpair1193";
  attribute SOFT_HLUTNM of periodic_rd_ack_r_lcl_i_1 : label is "soft_lutpair1192";
  attribute SOFT_HLUTNM of req_periodic_rd_r_lcl_i_1 : label is "soft_lutpair1191";
  attribute SOFT_HLUTNM of req_wr_r_lcl_i_1 : label is "soft_lutpair1191";
begin
  Q(3 downto 0) <= \^q\(3 downto 0);
  accept_internal_r_reg_0 <= \^accept_internal_r_reg_0\;
  accept_ns <= \^accept_ns\;
  accept_r_reg_0 <= \^accept_r_reg_0\;
  \generate_maint_cmds.insert_maint_r_lcl_reg_0\ <= \^generate_maint_cmds.insert_maint_r_lcl_reg_0\;
  hi_priority <= \^hi_priority\;
  \maint_controller.maint_wip_r_lcl_reg_0\ <= \^maint_controller.maint_wip_r_lcl_reg_0\;
  periodic_rd_ack_r_lcl_reg_0 <= \^periodic_rd_ack_r_lcl_reg_0\;
  periodic_rd_ack_r_lcl_reg_1 <= \^periodic_rd_ack_r_lcl_reg_1\;
  periodic_rd_cntr_r_reg_0 <= \^periodic_rd_cntr_r_reg_0\;
  \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[4]_0\ <= \^rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[4]_0\;
  set_order_q <= \^set_order_q\;
  set_order_q_22 <= \^set_order_q_22\;
  set_order_q_23 <= \^set_order_q_23\;
  set_order_q_24 <= \^set_order_q_24\;
accept_internal_r_reg: unisim.vcomponents.FDRE
     port map (
      C => \maint_controller.maint_wip_r_lcl_reg_1\,
      CE => '1',
      D => p_9_in,
      Q => \^accept_internal_r_reg_0\,
      R => '0'
    );
accept_r_i_1: unisim.vcomponents.LUT4
    generic map(
      INIT => X"80AA"
    )
        port map (
      I0 => p_9_in,
      I1 => \^periodic_rd_ack_r_lcl_reg_0\,
      I2 => \^periodic_rd_cntr_r_reg_0\,
      I3 => periodic_rd_r,
      O => \^accept_ns\
    );
accept_r_reg: unisim.vcomponents.FDRE
     port map (
      C => \maint_controller.maint_wip_r_lcl_reg_1\,
      CE => '1',
      D => \^accept_ns\,
      Q => \^accept_r_reg_0\,
      R => '0'
    );
\generate_maint_cmds.insert_maint_r_lcl_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4F44"
    )
        port map (
      I0 => \maint_controller.maint_srx_r1\,
      I1 => maint_srx_r,
      I2 => \maint_controller.maint_rdy_r1\,
      I3 => \maint_controller.maint_rdy\,
      O => \generate_maint_cmds.insert_maint_ns\
    );
\generate_maint_cmds.insert_maint_r_lcl_reg\: unisim.vcomponents.FDRE
     port map (
      C => \maint_controller.maint_wip_r_lcl_reg_1\,
      CE => '1',
      D => \generate_maint_cmds.insert_maint_ns\,
      Q => \^generate_maint_cmds.insert_maint_r_lcl_reg_0\,
      R => '0'
    );
\i___20_i_3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^periodic_rd_ack_r_lcl_reg_0\,
      I1 => \periodic_read_request.periodic_rd_grant_r\,
      O => clear_periodic_rd_request
    );
\i___2_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"E0000000"
    )
        port map (
      I0 => use_addr,
      I1 => \^periodic_rd_ack_r_lcl_reg_0\,
      I2 => head_r(0),
      I3 => \q_entry_r_reg[0]_0\(0),
      I4 => \^accept_internal_r_reg_0\,
      O => \^set_order_q_23\
    );
\i___34_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"EA"
    )
        port map (
      I0 => \^periodic_rd_ack_r_lcl_reg_0\,
      I1 => \^accept_r_reg_0\,
      I2 => use_addr,
      O => \^periodic_rd_ack_r_lcl_reg_1\
    );
\i___3_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"3333300055555555"
    )
        port map (
      I0 => \i___3_i_2\,
      I1 => \^set_order_q_23\,
      I2 => use_addr,
      I3 => \^accept_r_reg_0\,
      I4 => \^periodic_rd_ack_r_lcl_reg_0\,
      I5 => \q_entry_r_reg[0]_0\(0),
      O => accept_r_reg_3
    );
\i___4_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"CCCCCFFFAAAAAAAA"
    )
        port map (
      I0 => \i___4_i_1\,
      I1 => \^set_order_q_24\,
      I2 => use_addr,
      I3 => \^accept_r_reg_0\,
      I4 => \^periodic_rd_ack_r_lcl_reg_0\,
      I5 => \q_entry_r_reg[0]_1\(0),
      O => accept_r_reg_4
    );
\i___5_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"CCCCCFFFAAAAAAAA"
    )
        port map (
      I0 => \i___5_i_1\,
      I1 => \^set_order_q_22\,
      I2 => use_addr,
      I3 => \^accept_r_reg_0\,
      I4 => \^periodic_rd_ack_r_lcl_reg_0\,
      I5 => \q_entry_r_reg[0]\(0),
      O => accept_r_reg_2
    );
\i___60_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"55555556"
    )
        port map (
      I0 => \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r\(7),
      I1 => \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r\(4),
      I2 => \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r\(5),
      I3 => \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[4]_1\,
      I4 => \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r\(6),
      O => \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[7]_0\
    );
\i___6_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"3333300055555555"
    )
        port map (
      I0 => \i___6_i_1\,
      I1 => \^set_order_q\,
      I2 => use_addr,
      I3 => \^accept_r_reg_0\,
      I4 => \^periodic_rd_ack_r_lcl_reg_0\,
      I5 => E(0),
      O => accept_r_reg_1
    );
\i___7_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"E0000000"
    )
        port map (
      I0 => use_addr,
      I1 => \^periodic_rd_ack_r_lcl_reg_0\,
      I2 => head_r(1),
      I3 => \q_entry_r_reg[0]_1\(0),
      I4 => \^accept_internal_r_reg_0\,
      O => \^set_order_q_24\
    );
\i___7_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"AA80"
    )
        port map (
      I0 => rb_hit_busy_r(1),
      I1 => use_addr,
      I2 => \^accept_r_reg_0\,
      I3 => \^periodic_rd_ack_r_lcl_reg_0\,
      O => rb_hit_busy_r_reg_0
    );
\i___82_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000001"
    )
        port map (
      I0 => \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r\(4),
      I1 => \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r\(5),
      I2 => \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r\(7),
      I3 => \^q\(3),
      I4 => \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r\(6),
      O => \^rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[4]_0\
    );
\i___8_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"E0000000"
    )
        port map (
      I0 => use_addr,
      I1 => \^periodic_rd_ack_r_lcl_reg_0\,
      I2 => head_r(2),
      I3 => \q_entry_r_reg[0]\(0),
      I4 => \^accept_internal_r_reg_0\,
      O => \^set_order_q_22\
    );
\i___8_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"AA80"
    )
        port map (
      I0 => rb_hit_busy_r(2),
      I1 => use_addr,
      I2 => \^accept_r_reg_0\,
      I3 => \^periodic_rd_ack_r_lcl_reg_0\,
      O => rb_hit_busy_r_reg
    );
\i___9_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"E0000000"
    )
        port map (
      I0 => use_addr,
      I1 => \^periodic_rd_ack_r_lcl_reg_0\,
      I2 => head_r(3),
      I3 => E(0),
      I4 => \^accept_internal_r_reg_0\,
      O => \^set_order_q\
    );
\maint_controller.maint_hit_busies_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \maint_controller.maint_wip_r_lcl_reg_1\,
      CE => '1',
      D => \maint_controller.maint_hit_busies_r_reg[3]_1\(0),
      Q => \maint_controller.maint_hit_busies_r_reg[3]_0\(0),
      R => '0'
    );
\maint_controller.maint_hit_busies_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \maint_controller.maint_wip_r_lcl_reg_1\,
      CE => '1',
      D => \maint_controller.maint_hit_busies_r_reg[3]_1\(1),
      Q => \maint_controller.maint_hit_busies_r_reg[3]_0\(1),
      R => '0'
    );
\maint_controller.maint_hit_busies_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \maint_controller.maint_wip_r_lcl_reg_1\,
      CE => '1',
      D => \maint_controller.maint_hit_busies_r_reg[3]_1\(2),
      Q => \maint_controller.maint_hit_busies_r_reg[3]_0\(2),
      R => '0'
    );
\maint_controller.maint_hit_busies_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => \maint_controller.maint_wip_r_lcl_reg_1\,
      CE => '1',
      D => \maint_controller.maint_hit_busies_r_reg[3]_1\(3),
      Q => \maint_controller.maint_hit_busies_r_reg[3]_0\(3),
      R => '0'
    );
\maint_controller.maint_rdy_r1_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000004"
    )
        port map (
      I0 => \maint_controller.maint_hit_busies_r_reg[3]_1\(1),
      I1 => \maint_controller.maint_rdy_r1_i_2_n_0\,
      I2 => \maint_controller.maint_hit_busies_r_reg[3]_1\(0),
      I3 => \maint_controller.maint_hit_busies_r_reg[3]_1\(2),
      I4 => \maint_controller.maint_hit_busies_r_reg[3]_1\(3),
      O => \maint_controller.maint_rdy\
    );
\maint_controller.maint_rdy_r1_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"BA"
    )
        port map (
      I0 => \^maint_controller.maint_wip_r_lcl_reg_0\,
      I1 => \^periodic_rd_cntr_r_reg_0\,
      I2 => maint_req_r,
      O => \maint_controller.maint_rdy_r1_i_2_n_0\
    );
\maint_controller.maint_rdy_r1_reg\: unisim.vcomponents.FDRE
     port map (
      C => \maint_controller.maint_wip_r_lcl_reg_1\,
      CE => '1',
      D => \maint_controller.maint_rdy\,
      Q => \maint_controller.maint_rdy_r1\,
      R => '0'
    );
\maint_controller.maint_srx_r1_reg\: unisim.vcomponents.FDRE
     port map (
      C => \maint_controller.maint_wip_r_lcl_reg_1\,
      CE => '1',
      D => maint_srx_r,
      Q => \maint_controller.maint_srx_r1\,
      R => '0'
    );
\maint_controller.maint_wip_r_lcl_reg\: unisim.vcomponents.FDRE
     port map (
      C => \maint_controller.maint_wip_r_lcl_reg_1\,
      CE => '1',
      D => \maint_controller.maint_wip_r_lcl_reg_3\,
      Q => \^maint_controller.maint_wip_r_lcl_reg_0\,
      R => \maint_controller.maint_wip_r_lcl_reg_2\
    );
periodic_rd_ack_r_lcl_i_1: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2A00"
    )
        port map (
      I0 => p_9_in,
      I1 => \^periodic_rd_ack_r_lcl_reg_0\,
      I2 => \^periodic_rd_cntr_r_reg_0\,
      I3 => periodic_rd_r,
      O => periodic_rd_ack_ns
    );
periodic_rd_ack_r_lcl_reg: unisim.vcomponents.FDRE
     port map (
      C => \maint_controller.maint_wip_r_lcl_reg_1\,
      CE => '1',
      D => periodic_rd_ack_ns,
      Q => \^periodic_rd_ack_r_lcl_reg_0\,
      R => '0'
    );
periodic_rd_cntr_r_reg: unisim.vcomponents.FDRE
     port map (
      C => \maint_controller.maint_wip_r_lcl_reg_1\,
      CE => '1',
      D => periodic_rd_cntr_r_reg_2,
      Q => \^periodic_rd_cntr_r_reg_0\,
      R => periodic_rd_cntr_r_reg_1
    );
\q_entry_r[0]_i_2__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"96696996"
    )
        port map (
      I0 => \^periodic_rd_ack_r_lcl_reg_1\,
      I1 => E(0),
      I2 => \q_entry_r_reg[0]\(0),
      I3 => \q_entry_r_reg[0]_1\(0),
      I4 => \q_entry_r_reg[0]_0\(0),
      O => idle_r_lcl_reg
    );
q_has_priority_r_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFEAAAAAAAAAAAAA"
    )
        port map (
      I0 => q_has_priority,
      I1 => use_addr,
      I2 => \^accept_r_reg_0\,
      I3 => \^periodic_rd_ack_r_lcl_reg_0\,
      I4 => rb_hit_busy_r(3),
      I5 => was_priority,
      O => q_has_priority_r_reg
    );
\q_has_priority_r_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFEAAAAAAAAAAAAA"
    )
        port map (
      I0 => q_has_priority_0,
      I1 => use_addr,
      I2 => \^accept_r_reg_0\,
      I3 => \^periodic_rd_ack_r_lcl_reg_0\,
      I4 => rb_hit_busy_r(0),
      I5 => was_priority,
      O => q_has_priority_r_reg_0
    );
\q_has_priority_r_i_1__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"EEEEEAAAAAAAAAAA"
    )
        port map (
      I0 => q_has_priority_1,
      I1 => rb_hit_busy_r(2),
      I2 => use_addr,
      I3 => \^accept_r_reg_0\,
      I4 => \^periodic_rd_ack_r_lcl_reg_0\,
      I5 => was_priority,
      O => q_has_priority_r_reg_1
    );
\q_has_priority_r_i_1__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"EEEEEAAAAAAAAAAA"
    )
        port map (
      I0 => q_has_priority_2,
      I1 => rb_hit_busy_r(1),
      I2 => use_addr,
      I3 => \^accept_r_reg_0\,
      I4 => \^periodic_rd_ack_r_lcl_reg_0\,
      I5 => was_priority,
      O => q_has_priority_r_reg_2
    );
req_periodic_rd_r_lcl_i_1: unisim.vcomponents.LUT3
    generic map(
      INIT => X"2A"
    )
        port map (
      I0 => periodic_rd_r,
      I1 => \^periodic_rd_cntr_r_reg_0\,
      I2 => \^periodic_rd_ack_r_lcl_reg_0\,
      O => periodic_rd_insert
    );
req_wr_r_lcl_i_1: unisim.vcomponents.LUT5
    generic map(
      INIT => X"D500D5D5"
    )
        port map (
      I0 => periodic_rd_r,
      I1 => \^periodic_rd_cntr_r_reg_0\,
      I2 => \^periodic_rd_ack_r_lcl_reg_0\,
      I3 => cmd(1),
      I4 => cmd(0),
      O => req_wr_r_lcl0
    );
\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r[1]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AAAAAAEB"
    )
        port map (
      I0 => \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[3]_0\,
      I1 => \^q\(1),
      I2 => \^q\(0),
      I3 => \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[1]_0\,
      I4 => \^generate_maint_cmds.insert_maint_r_lcl_reg_0\,
      O => \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_ns\(1)
    );
\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r[2]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"11100001"
    )
        port map (
      I0 => \^generate_maint_cmds.insert_maint_r_lcl_reg_0\,
      I1 => \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[0]_0\,
      I2 => \^q\(1),
      I3 => \^q\(0),
      I4 => \^q\(2),
      O => \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_ns\(2)
    );
\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r[3]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"EEEEEEEBAAAAAAAA"
    )
        port map (
      I0 => \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[3]_0\,
      I1 => \^q\(3),
      I2 => \^q\(2),
      I3 => \^q\(1),
      I4 => \^q\(0),
      I5 => \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[3]_1\,
      O => \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_ns\(3)
    );
\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r[4]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000F909"
    )
        port map (
      I0 => \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r\(4),
      I1 => \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[4]_1\,
      I2 => \^generate_maint_cmds.insert_maint_r_lcl_reg_0\,
      I3 => maint_zq_r,
      I4 => \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[0]_0\,
      O => \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_ns\(4)
    );
\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r[5]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"11100001"
    )
        port map (
      I0 => \^generate_maint_cmds.insert_maint_r_lcl_reg_0\,
      I1 => \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[0]_0\,
      I2 => \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r\(4),
      I3 => \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[4]_1\,
      I4 => \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r\(5),
      O => \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_ns\(5)
    );
\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r[6]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"1111111000000001"
    )
        port map (
      I0 => \^generate_maint_cmds.insert_maint_r_lcl_reg_0\,
      I1 => \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[0]_0\,
      I2 => \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r\(4),
      I3 => \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r\(5),
      I4 => \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[4]_1\,
      I5 => \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r\(6),
      O => \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_ns\(6)
    );
\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r[7]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFEFFFFFFFF"
    )
        port map (
      I0 => \^q\(0),
      I1 => \^q\(1),
      I2 => \^q\(2),
      I3 => \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[0]_0\,
      I4 => \^generate_maint_cmds.insert_maint_r_lcl_reg_0\,
      I5 => \^rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[4]_0\,
      O => \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r[7]_i_1_n_0\
    );
\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \maint_controller.maint_wip_r_lcl_reg_1\,
      CE => \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r[7]_i_1_n_0\,
      D => \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[7]_1\(0),
      Q => \^q\(0),
      R => '0'
    );
\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \maint_controller.maint_wip_r_lcl_reg_1\,
      CE => \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r[7]_i_1_n_0\,
      D => \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_ns\(1),
      Q => \^q\(1),
      R => '0'
    );
\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \maint_controller.maint_wip_r_lcl_reg_1\,
      CE => \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r[7]_i_1_n_0\,
      D => \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_ns\(2),
      Q => \^q\(2),
      R => '0'
    );
\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => \maint_controller.maint_wip_r_lcl_reg_1\,
      CE => \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r[7]_i_1_n_0\,
      D => \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_ns\(3),
      Q => \^q\(3),
      R => '0'
    );
\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => \maint_controller.maint_wip_r_lcl_reg_1\,
      CE => \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r[7]_i_1_n_0\,
      D => \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_ns\(4),
      Q => \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r\(4),
      R => '0'
    );
\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => \maint_controller.maint_wip_r_lcl_reg_1\,
      CE => \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r[7]_i_1_n_0\,
      D => \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_ns\(5),
      Q => \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r\(5),
      R => '0'
    );
\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => \maint_controller.maint_wip_r_lcl_reg_1\,
      CE => \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r[7]_i_1_n_0\,
      D => \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_ns\(6),
      Q => \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r\(6),
      R => '0'
    );
\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => \maint_controller.maint_wip_r_lcl_reg_1\,
      CE => \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r[7]_i_1_n_0\,
      D => \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[7]_1\(1),
      Q => \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r\(7),
      R => '0'
    );
was_priority_i_1: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => was_priority,
      I1 => was_priority_reg_0,
      O => \^hi_priority\
    );
was_priority_reg: unisim.vcomponents.FDRE
     port map (
      C => \maint_controller.maint_wip_r_lcl_reg_1\,
      CE => '1',
      D => \^hi_priority\,
      Q => was_priority,
      R => '0'
    );
was_wr_i_1: unisim.vcomponents.LUT3
    generic map(
      INIT => X"8A"
    )
        port map (
      I0 => cmd(0),
      I1 => \^periodic_rd_ack_r_lcl_reg_0\,
      I2 => periodic_rd_r,
      O => was_wr0
    );
was_wr_reg: unisim.vcomponents.FDRE
     port map (
      C => \maint_controller.maint_wip_r_lcl_reg_1\,
      CE => '1',
      D => was_wr0,
      Q => was_wr,
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mig_mig_7series_v4_2_bank_compare is
  port (
    rb_hit_busy_r_reg_0 : out STD_LOGIC;
    req_periodic_rd_r : out STD_LOGIC_VECTOR ( 0 to 0 );
    rd_wr_r_lcl_reg_0 : out STD_LOGIC;
    req_wr_r_lcl_reg_0 : out STD_LOGIC;
    req_priority_r : out STD_LOGIC;
    \grant_r_reg[3]\ : out STD_LOGIC;
    row_hit_r_reg_0 : out STD_LOGIC;
    start_wtp_timer0 : out STD_LOGIC;
    \req_row_r_lcl_reg[13]_0\ : out STD_LOGIC_VECTOR ( 13 downto 0 );
    \req_data_buf_addr_r_reg[3]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
    \req_bank_r_lcl_reg[2]_0\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
    \req_col_r_reg[9]_0\ : out STD_LOGIC_VECTOR ( 9 downto 0 );
    p_28_out : in STD_LOGIC;
    row_hit_r_reg_1 : in STD_LOGIC;
    E : in STD_LOGIC_VECTOR ( 0 to 0 );
    periodic_rd_insert : in STD_LOGIC;
    req_wr_r_lcl0 : in STD_LOGIC;
    hi_priority : in STD_LOGIC;
    row_hit_r_reg_2 : in STD_LOGIC_VECTOR ( 0 to 0 );
    Q : in STD_LOGIC_VECTOR ( 0 to 0 );
    rd_wr_r_lcl_reg_1 : in STD_LOGIC;
    rd_wr_r_lcl_reg_2 : in STD_LOGIC;
    ordered_r_lcl_reg : in STD_LOGIC;
    ordered_r_lcl_reg_0 : in STD_LOGIC;
    ordered_r_lcl_reg_1 : in STD_LOGIC;
    maint_req_r : in STD_LOGIC;
    pass_open_bank_r_lcl_reg : in STD_LOGIC;
    pass_open_bank_r_lcl_reg_0 : in STD_LOGIC;
    wait_for_maint_r_15 : in STD_LOGIC;
    \req_row_r_lcl_reg[13]_1\ : in STD_LOGIC_VECTOR ( 13 downto 0 );
    \req_data_buf_addr_r_reg[3]_1\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \req_data_buf_addr_r_reg[3]_2\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
    \req_bank_r_lcl_reg[2]_1\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
    \req_col_r_reg[9]_1\ : in STD_LOGIC_VECTOR ( 9 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of mig_mig_7series_v4_2_bank_compare : entity is "mig_7series_v4_2_bank_compare";
end mig_mig_7series_v4_2_bank_compare;

architecture STRUCTURE of mig_mig_7series_v4_2_bank_compare is
  signal rd_wr_ns : STD_LOGIC;
  signal \^rd_wr_r_lcl_reg_0\ : STD_LOGIC;
  signal \^req_row_r_lcl_reg[13]_0\ : STD_LOGIC_VECTOR ( 13 downto 0 );
  signal \^req_wr_r_lcl_reg_0\ : STD_LOGIC;
  signal \row_hit_ns_carry__0_n_3\ : STD_LOGIC;
  signal \row_hit_ns_carry_i_1__2_n_0\ : STD_LOGIC;
  signal \row_hit_ns_carry_i_2__2_n_0\ : STD_LOGIC;
  signal \row_hit_ns_carry_i_3__2_n_0\ : STD_LOGIC;
  signal \row_hit_ns_carry_i_4__2_n_0\ : STD_LOGIC;
  signal row_hit_ns_carry_n_0 : STD_LOGIC;
  signal row_hit_ns_carry_n_1 : STD_LOGIC;
  signal row_hit_ns_carry_n_2 : STD_LOGIC;
  signal row_hit_ns_carry_n_3 : STD_LOGIC;
  signal row_hit_r : STD_LOGIC;
  signal NLW_row_hit_ns_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \NLW_row_hit_ns_carry__0_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
  signal \NLW_row_hit_ns_carry__0_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \rd_wr_r_lcl_i_1__0\ : label is "soft_lutpair1180";
  attribute SOFT_HLUTNM of \wr_this_rank_r[0]_i_1__2\ : label is "soft_lutpair1180";
begin
  rd_wr_r_lcl_reg_0 <= \^rd_wr_r_lcl_reg_0\;
  \req_row_r_lcl_reg[13]_0\(13 downto 0) <= \^req_row_r_lcl_reg[13]_0\(13 downto 0);
  req_wr_r_lcl_reg_0 <= \^req_wr_r_lcl_reg_0\;
\i___64_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AAAA00A2"
    )
        port map (
      I0 => row_hit_r,
      I1 => maint_req_r,
      I2 => pass_open_bank_r_lcl_reg,
      I3 => pass_open_bank_r_lcl_reg_0,
      I4 => wait_for_maint_r_15,
      O => row_hit_r_reg_0
    );
\ordered_r_lcl_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000D5D5D500"
    )
        port map (
      I0 => Q(0),
      I1 => \^rd_wr_r_lcl_reg_0\,
      I2 => \^req_wr_r_lcl_reg_0\,
      I3 => ordered_r_lcl_reg,
      I4 => ordered_r_lcl_reg_0,
      I5 => ordered_r_lcl_reg_1,
      O => \grant_r_reg[3]\
    );
rb_hit_busy_r_reg: unisim.vcomponents.FDRE
     port map (
      C => row_hit_r_reg_1,
      CE => '1',
      D => p_28_out,
      Q => rb_hit_busy_r_reg_0,
      R => '0'
    );
\rd_wr_r_lcl_i_1__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F20"
    )
        port map (
      I0 => \^rd_wr_r_lcl_reg_0\,
      I1 => Q(0),
      I2 => rd_wr_r_lcl_reg_1,
      I3 => rd_wr_r_lcl_reg_2,
      O => rd_wr_ns
    );
rd_wr_r_lcl_reg: unisim.vcomponents.FDRE
     port map (
      C => row_hit_r_reg_1,
      CE => '1',
      D => rd_wr_ns,
      Q => \^rd_wr_r_lcl_reg_0\,
      R => '0'
    );
\req_bank_r_lcl_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => row_hit_r_reg_1,
      CE => E(0),
      D => \req_bank_r_lcl_reg[2]_1\(0),
      Q => \req_bank_r_lcl_reg[2]_0\(0),
      R => '0'
    );
\req_bank_r_lcl_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => row_hit_r_reg_1,
      CE => E(0),
      D => \req_bank_r_lcl_reg[2]_1\(1),
      Q => \req_bank_r_lcl_reg[2]_0\(1),
      R => '0'
    );
\req_bank_r_lcl_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => row_hit_r_reg_1,
      CE => E(0),
      D => \req_bank_r_lcl_reg[2]_1\(2),
      Q => \req_bank_r_lcl_reg[2]_0\(2),
      R => '0'
    );
\req_col_r_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => row_hit_r_reg_1,
      CE => E(0),
      D => \req_col_r_reg[9]_1\(0),
      Q => \req_col_r_reg[9]_0\(0),
      R => '0'
    );
\req_col_r_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => row_hit_r_reg_1,
      CE => E(0),
      D => \req_col_r_reg[9]_1\(1),
      Q => \req_col_r_reg[9]_0\(1),
      R => '0'
    );
\req_col_r_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => row_hit_r_reg_1,
      CE => E(0),
      D => \req_col_r_reg[9]_1\(2),
      Q => \req_col_r_reg[9]_0\(2),
      R => '0'
    );
\req_col_r_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => row_hit_r_reg_1,
      CE => E(0),
      D => \req_col_r_reg[9]_1\(3),
      Q => \req_col_r_reg[9]_0\(3),
      R => '0'
    );
\req_col_r_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => row_hit_r_reg_1,
      CE => E(0),
      D => \req_col_r_reg[9]_1\(4),
      Q => \req_col_r_reg[9]_0\(4),
      R => '0'
    );
\req_col_r_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => row_hit_r_reg_1,
      CE => E(0),
      D => \req_col_r_reg[9]_1\(5),
      Q => \req_col_r_reg[9]_0\(5),
      R => '0'
    );
\req_col_r_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => row_hit_r_reg_1,
      CE => E(0),
      D => \req_col_r_reg[9]_1\(6),
      Q => \req_col_r_reg[9]_0\(6),
      R => '0'
    );
\req_col_r_reg[7]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => row_hit_r_reg_1,
      CE => E(0),
      D => \req_col_r_reg[9]_1\(7),
      Q => \req_col_r_reg[9]_0\(7),
      R => '0'
    );
\req_col_r_reg[8]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => row_hit_r_reg_1,
      CE => E(0),
      D => \req_col_r_reg[9]_1\(8),
      Q => \req_col_r_reg[9]_0\(8),
      R => '0'
    );
\req_col_r_reg[9]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => row_hit_r_reg_1,
      CE => E(0),
      D => \req_col_r_reg[9]_1\(9),
      Q => \req_col_r_reg[9]_0\(9),
      R => '0'
    );
\req_data_buf_addr_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => row_hit_r_reg_1,
      CE => \req_data_buf_addr_r_reg[3]_1\(0),
      D => \req_data_buf_addr_r_reg[3]_2\(0),
      Q => \req_data_buf_addr_r_reg[3]_0\(0),
      R => '0'
    );
\req_data_buf_addr_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => row_hit_r_reg_1,
      CE => \req_data_buf_addr_r_reg[3]_1\(0),
      D => \req_data_buf_addr_r_reg[3]_2\(1),
      Q => \req_data_buf_addr_r_reg[3]_0\(1),
      R => '0'
    );
\req_data_buf_addr_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => row_hit_r_reg_1,
      CE => \req_data_buf_addr_r_reg[3]_1\(0),
      D => \req_data_buf_addr_r_reg[3]_2\(2),
      Q => \req_data_buf_addr_r_reg[3]_0\(2),
      R => '0'
    );
\req_data_buf_addr_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => row_hit_r_reg_1,
      CE => \req_data_buf_addr_r_reg[3]_1\(0),
      D => \req_data_buf_addr_r_reg[3]_2\(3),
      Q => \req_data_buf_addr_r_reg[3]_0\(3),
      R => '0'
    );
req_periodic_rd_r_lcl_reg: unisim.vcomponents.FDRE
     port map (
      C => row_hit_r_reg_1,
      CE => E(0),
      D => periodic_rd_insert,
      Q => req_periodic_rd_r(0),
      R => '0'
    );
req_priority_r_reg: unisim.vcomponents.FDRE
     port map (
      C => row_hit_r_reg_1,
      CE => E(0),
      D => hi_priority,
      Q => req_priority_r,
      R => '0'
    );
\req_row_r_lcl_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => row_hit_r_reg_1,
      CE => E(0),
      D => \req_row_r_lcl_reg[13]_1\(0),
      Q => \^req_row_r_lcl_reg[13]_0\(0),
      R => '0'
    );
\req_row_r_lcl_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => row_hit_r_reg_1,
      CE => E(0),
      D => \req_row_r_lcl_reg[13]_1\(10),
      Q => \^req_row_r_lcl_reg[13]_0\(10),
      R => '0'
    );
\req_row_r_lcl_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => row_hit_r_reg_1,
      CE => E(0),
      D => \req_row_r_lcl_reg[13]_1\(11),
      Q => \^req_row_r_lcl_reg[13]_0\(11),
      R => '0'
    );
\req_row_r_lcl_reg[12]\: unisim.vcomponents.FDRE
     port map (
      C => row_hit_r_reg_1,
      CE => E(0),
      D => \req_row_r_lcl_reg[13]_1\(12),
      Q => \^req_row_r_lcl_reg[13]_0\(12),
      R => '0'
    );
\req_row_r_lcl_reg[13]\: unisim.vcomponents.FDRE
     port map (
      C => row_hit_r_reg_1,
      CE => E(0),
      D => \req_row_r_lcl_reg[13]_1\(13),
      Q => \^req_row_r_lcl_reg[13]_0\(13),
      R => '0'
    );
\req_row_r_lcl_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => row_hit_r_reg_1,
      CE => E(0),
      D => \req_row_r_lcl_reg[13]_1\(1),
      Q => \^req_row_r_lcl_reg[13]_0\(1),
      R => '0'
    );
\req_row_r_lcl_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => row_hit_r_reg_1,
      CE => E(0),
      D => \req_row_r_lcl_reg[13]_1\(2),
      Q => \^req_row_r_lcl_reg[13]_0\(2),
      R => '0'
    );
\req_row_r_lcl_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => row_hit_r_reg_1,
      CE => E(0),
      D => \req_row_r_lcl_reg[13]_1\(3),
      Q => \^req_row_r_lcl_reg[13]_0\(3),
      R => '0'
    );
\req_row_r_lcl_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => row_hit_r_reg_1,
      CE => E(0),
      D => \req_row_r_lcl_reg[13]_1\(4),
      Q => \^req_row_r_lcl_reg[13]_0\(4),
      R => '0'
    );
\req_row_r_lcl_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => row_hit_r_reg_1,
      CE => E(0),
      D => \req_row_r_lcl_reg[13]_1\(5),
      Q => \^req_row_r_lcl_reg[13]_0\(5),
      R => '0'
    );
\req_row_r_lcl_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => row_hit_r_reg_1,
      CE => E(0),
      D => \req_row_r_lcl_reg[13]_1\(6),
      Q => \^req_row_r_lcl_reg[13]_0\(6),
      R => '0'
    );
\req_row_r_lcl_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => row_hit_r_reg_1,
      CE => E(0),
      D => \req_row_r_lcl_reg[13]_1\(7),
      Q => \^req_row_r_lcl_reg[13]_0\(7),
      R => '0'
    );
\req_row_r_lcl_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => row_hit_r_reg_1,
      CE => E(0),
      D => \req_row_r_lcl_reg[13]_1\(8),
      Q => \^req_row_r_lcl_reg[13]_0\(8),
      R => '0'
    );
\req_row_r_lcl_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => row_hit_r_reg_1,
      CE => E(0),
      D => \req_row_r_lcl_reg[13]_1\(9),
      Q => \^req_row_r_lcl_reg[13]_0\(9),
      R => '0'
    );
req_wr_r_lcl_reg: unisim.vcomponents.FDRE
     port map (
      C => row_hit_r_reg_1,
      CE => E(0),
      D => req_wr_r_lcl0,
      Q => \^req_wr_r_lcl_reg_0\,
      R => '0'
    );
row_hit_ns_carry: unisim.vcomponents.CARRY4
     port map (
      CI => '0',
      CO(3) => row_hit_ns_carry_n_0,
      CO(2) => row_hit_ns_carry_n_1,
      CO(1) => row_hit_ns_carry_n_2,
      CO(0) => row_hit_ns_carry_n_3,
      CYINIT => '1',
      DI(3 downto 0) => B"0000",
      O(3 downto 0) => NLW_row_hit_ns_carry_O_UNCONNECTED(3 downto 0),
      S(3) => \row_hit_ns_carry_i_1__2_n_0\,
      S(2) => \row_hit_ns_carry_i_2__2_n_0\,
      S(1) => \row_hit_ns_carry_i_3__2_n_0\,
      S(0) => \row_hit_ns_carry_i_4__2_n_0\
    );
\row_hit_ns_carry__0\: unisim.vcomponents.CARRY4
     port map (
      CI => row_hit_ns_carry_n_0,
      CO(3 downto 1) => \NLW_row_hit_ns_carry__0_CO_UNCONNECTED\(3 downto 1),
      CO(0) => \row_hit_ns_carry__0_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3 downto 0) => \NLW_row_hit_ns_carry__0_O_UNCONNECTED\(3 downto 0),
      S(3 downto 1) => B"000",
      S(0) => row_hit_r_reg_2(0)
    );
\row_hit_ns_carry_i_1__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"9009000000009009"
    )
        port map (
      I0 => \^req_row_r_lcl_reg[13]_0\(11),
      I1 => \req_row_r_lcl_reg[13]_1\(11),
      I2 => \^req_row_r_lcl_reg[13]_0\(9),
      I3 => \req_row_r_lcl_reg[13]_1\(9),
      I4 => \req_row_r_lcl_reg[13]_1\(10),
      I5 => \^req_row_r_lcl_reg[13]_0\(10),
      O => \row_hit_ns_carry_i_1__2_n_0\
    );
\row_hit_ns_carry_i_2__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"9009000000009009"
    )
        port map (
      I0 => \^req_row_r_lcl_reg[13]_0\(8),
      I1 => \req_row_r_lcl_reg[13]_1\(8),
      I2 => \^req_row_r_lcl_reg[13]_0\(7),
      I3 => \req_row_r_lcl_reg[13]_1\(7),
      I4 => \req_row_r_lcl_reg[13]_1\(6),
      I5 => \^req_row_r_lcl_reg[13]_0\(6),
      O => \row_hit_ns_carry_i_2__2_n_0\
    );
\row_hit_ns_carry_i_3__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"9009000000009009"
    )
        port map (
      I0 => \^req_row_r_lcl_reg[13]_0\(5),
      I1 => \req_row_r_lcl_reg[13]_1\(5),
      I2 => \^req_row_r_lcl_reg[13]_0\(3),
      I3 => \req_row_r_lcl_reg[13]_1\(3),
      I4 => \req_row_r_lcl_reg[13]_1\(4),
      I5 => \^req_row_r_lcl_reg[13]_0\(4),
      O => \row_hit_ns_carry_i_3__2_n_0\
    );
\row_hit_ns_carry_i_4__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"9009000000009009"
    )
        port map (
      I0 => \^req_row_r_lcl_reg[13]_0\(2),
      I1 => \req_row_r_lcl_reg[13]_1\(2),
      I2 => \^req_row_r_lcl_reg[13]_0\(1),
      I3 => \req_row_r_lcl_reg[13]_1\(1),
      I4 => \req_row_r_lcl_reg[13]_1\(0),
      I5 => \^req_row_r_lcl_reg[13]_0\(0),
      O => \row_hit_ns_carry_i_4__2_n_0\
    );
row_hit_r_reg: unisim.vcomponents.FDRE
     port map (
      C => row_hit_r_reg_1,
      CE => '1',
      D => \row_hit_ns_carry__0_n_3\,
      Q => row_hit_r,
      R => '0'
    );
\wr_this_rank_r[0]_i_1__2\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \^rd_wr_r_lcl_reg_0\,
      O => start_wtp_timer0
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mig_mig_7series_v4_2_bank_compare_0 is
  port (
    rb_hit_busy_r_reg_0 : out STD_LOGIC;
    req_periodic_rd_r : out STD_LOGIC_VECTOR ( 0 to 0 );
    rd_wr_r_lcl_reg_0 : out STD_LOGIC;
    req_wr_r_lcl_reg_0 : out STD_LOGIC;
    req_priority_r : out STD_LOGIC;
    \grant_r_reg[2]\ : out STD_LOGIC;
    row_hit_r_reg_0 : out STD_LOGIC;
    start_wtp_timer0 : out STD_LOGIC;
    \req_row_r_lcl_reg[13]_0\ : out STD_LOGIC_VECTOR ( 13 downto 0 );
    \req_data_buf_addr_r_reg[3]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
    \req_bank_r_lcl_reg[2]_0\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
    \req_col_r_reg[9]_0\ : out STD_LOGIC_VECTOR ( 9 downto 0 );
    p_67_out : in STD_LOGIC;
    \req_col_r_reg[9]_1\ : in STD_LOGIC;
    E : in STD_LOGIC_VECTOR ( 0 to 0 );
    periodic_rd_insert : in STD_LOGIC;
    req_wr_r_lcl0 : in STD_LOGIC;
    hi_priority : in STD_LOGIC;
    row_hit_r_reg_1 : in STD_LOGIC_VECTOR ( 0 to 0 );
    Q : in STD_LOGIC_VECTOR ( 0 to 0 );
    rd_wr_r_lcl_reg_1 : in STD_LOGIC;
    rd_wr_r_lcl_reg_2 : in STD_LOGIC;
    ordered_r_lcl_reg : in STD_LOGIC;
    ordered_r_lcl_reg_0 : in STD_LOGIC;
    ordered_r_lcl_reg_1 : in STD_LOGIC;
    maint_req_r : in STD_LOGIC;
    pass_open_bank_r_lcl_reg : in STD_LOGIC;
    pass_open_bank_r_lcl_reg_0 : in STD_LOGIC;
    wait_for_maint_r_14 : in STD_LOGIC;
    \req_row_r_lcl_reg[13]_1\ : in STD_LOGIC_VECTOR ( 13 downto 0 );
    \req_data_buf_addr_r_reg[3]_1\ : in STD_LOGIC;
    \req_data_buf_addr_r_reg[3]_2\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
    \req_bank_r_lcl_reg[2]_1\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
    \req_col_r_reg[9]_2\ : in STD_LOGIC_VECTOR ( 9 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of mig_mig_7series_v4_2_bank_compare_0 : entity is "mig_7series_v4_2_bank_compare";
end mig_mig_7series_v4_2_bank_compare_0;

architecture STRUCTURE of mig_mig_7series_v4_2_bank_compare_0 is
  signal rd_wr_ns : STD_LOGIC;
  signal \^rd_wr_r_lcl_reg_0\ : STD_LOGIC;
  signal \^req_row_r_lcl_reg[13]_0\ : STD_LOGIC_VECTOR ( 13 downto 0 );
  signal \^req_wr_r_lcl_reg_0\ : STD_LOGIC;
  signal \row_hit_ns_carry__0_n_3\ : STD_LOGIC;
  signal \row_hit_ns_carry_i_1__1_n_0\ : STD_LOGIC;
  signal \row_hit_ns_carry_i_2__1_n_0\ : STD_LOGIC;
  signal \row_hit_ns_carry_i_3__1_n_0\ : STD_LOGIC;
  signal \row_hit_ns_carry_i_4__1_n_0\ : STD_LOGIC;
  signal row_hit_ns_carry_n_0 : STD_LOGIC;
  signal row_hit_ns_carry_n_1 : STD_LOGIC;
  signal row_hit_ns_carry_n_2 : STD_LOGIC;
  signal row_hit_ns_carry_n_3 : STD_LOGIC;
  signal row_hit_r : STD_LOGIC;
  signal NLW_row_hit_ns_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \NLW_row_hit_ns_carry__0_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
  signal \NLW_row_hit_ns_carry__0_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \rd_wr_r_lcl_i_1__1\ : label is "soft_lutpair1172";
  attribute SOFT_HLUTNM of \wr_this_rank_r[0]_i_1__1\ : label is "soft_lutpair1172";
begin
  rd_wr_r_lcl_reg_0 <= \^rd_wr_r_lcl_reg_0\;
  \req_row_r_lcl_reg[13]_0\(13 downto 0) <= \^req_row_r_lcl_reg[13]_0\(13 downto 0);
  req_wr_r_lcl_reg_0 <= \^req_wr_r_lcl_reg_0\;
\i___63_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AAAA00A2"
    )
        port map (
      I0 => row_hit_r,
      I1 => maint_req_r,
      I2 => pass_open_bank_r_lcl_reg,
      I3 => pass_open_bank_r_lcl_reg_0,
      I4 => wait_for_maint_r_14,
      O => row_hit_r_reg_0
    );
\ordered_r_lcl_i_1__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000D5D5D500"
    )
        port map (
      I0 => Q(0),
      I1 => \^rd_wr_r_lcl_reg_0\,
      I2 => \^req_wr_r_lcl_reg_0\,
      I3 => ordered_r_lcl_reg,
      I4 => ordered_r_lcl_reg_0,
      I5 => ordered_r_lcl_reg_1,
      O => \grant_r_reg[2]\
    );
rb_hit_busy_r_reg: unisim.vcomponents.FDRE
     port map (
      C => \req_col_r_reg[9]_1\,
      CE => '1',
      D => p_67_out,
      Q => rb_hit_busy_r_reg_0,
      R => '0'
    );
\rd_wr_r_lcl_i_1__1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F20"
    )
        port map (
      I0 => \^rd_wr_r_lcl_reg_0\,
      I1 => Q(0),
      I2 => rd_wr_r_lcl_reg_1,
      I3 => rd_wr_r_lcl_reg_2,
      O => rd_wr_ns
    );
rd_wr_r_lcl_reg: unisim.vcomponents.FDRE
     port map (
      C => \req_col_r_reg[9]_1\,
      CE => '1',
      D => rd_wr_ns,
      Q => \^rd_wr_r_lcl_reg_0\,
      R => '0'
    );
\req_bank_r_lcl_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \req_col_r_reg[9]_1\,
      CE => E(0),
      D => \req_bank_r_lcl_reg[2]_1\(0),
      Q => \req_bank_r_lcl_reg[2]_0\(0),
      R => '0'
    );
\req_bank_r_lcl_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \req_col_r_reg[9]_1\,
      CE => E(0),
      D => \req_bank_r_lcl_reg[2]_1\(1),
      Q => \req_bank_r_lcl_reg[2]_0\(1),
      R => '0'
    );
\req_bank_r_lcl_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \req_col_r_reg[9]_1\,
      CE => E(0),
      D => \req_bank_r_lcl_reg[2]_1\(2),
      Q => \req_bank_r_lcl_reg[2]_0\(2),
      R => '0'
    );
\req_col_r_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \req_col_r_reg[9]_1\,
      CE => E(0),
      D => \req_col_r_reg[9]_2\(0),
      Q => \req_col_r_reg[9]_0\(0),
      R => '0'
    );
\req_col_r_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \req_col_r_reg[9]_1\,
      CE => E(0),
      D => \req_col_r_reg[9]_2\(1),
      Q => \req_col_r_reg[9]_0\(1),
      R => '0'
    );
\req_col_r_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \req_col_r_reg[9]_1\,
      CE => E(0),
      D => \req_col_r_reg[9]_2\(2),
      Q => \req_col_r_reg[9]_0\(2),
      R => '0'
    );
\req_col_r_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \req_col_r_reg[9]_1\,
      CE => E(0),
      D => \req_col_r_reg[9]_2\(3),
      Q => \req_col_r_reg[9]_0\(3),
      R => '0'
    );
\req_col_r_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \req_col_r_reg[9]_1\,
      CE => E(0),
      D => \req_col_r_reg[9]_2\(4),
      Q => \req_col_r_reg[9]_0\(4),
      R => '0'
    );
\req_col_r_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \req_col_r_reg[9]_1\,
      CE => E(0),
      D => \req_col_r_reg[9]_2\(5),
      Q => \req_col_r_reg[9]_0\(5),
      R => '0'
    );
\req_col_r_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \req_col_r_reg[9]_1\,
      CE => E(0),
      D => \req_col_r_reg[9]_2\(6),
      Q => \req_col_r_reg[9]_0\(6),
      R => '0'
    );
\req_col_r_reg[7]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \req_col_r_reg[9]_1\,
      CE => E(0),
      D => \req_col_r_reg[9]_2\(7),
      Q => \req_col_r_reg[9]_0\(7),
      R => '0'
    );
\req_col_r_reg[8]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \req_col_r_reg[9]_1\,
      CE => E(0),
      D => \req_col_r_reg[9]_2\(8),
      Q => \req_col_r_reg[9]_0\(8),
      R => '0'
    );
\req_col_r_reg[9]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \req_col_r_reg[9]_1\,
      CE => E(0),
      D => \req_col_r_reg[9]_2\(9),
      Q => \req_col_r_reg[9]_0\(9),
      R => '0'
    );
\req_data_buf_addr_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \req_col_r_reg[9]_1\,
      CE => \req_data_buf_addr_r_reg[3]_1\,
      D => \req_data_buf_addr_r_reg[3]_2\(0),
      Q => \req_data_buf_addr_r_reg[3]_0\(0),
      R => '0'
    );
\req_data_buf_addr_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \req_col_r_reg[9]_1\,
      CE => \req_data_buf_addr_r_reg[3]_1\,
      D => \req_data_buf_addr_r_reg[3]_2\(1),
      Q => \req_data_buf_addr_r_reg[3]_0\(1),
      R => '0'
    );
\req_data_buf_addr_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \req_col_r_reg[9]_1\,
      CE => \req_data_buf_addr_r_reg[3]_1\,
      D => \req_data_buf_addr_r_reg[3]_2\(2),
      Q => \req_data_buf_addr_r_reg[3]_0\(2),
      R => '0'
    );
\req_data_buf_addr_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => \req_col_r_reg[9]_1\,
      CE => \req_data_buf_addr_r_reg[3]_1\,
      D => \req_data_buf_addr_r_reg[3]_2\(3),
      Q => \req_data_buf_addr_r_reg[3]_0\(3),
      R => '0'
    );
req_periodic_rd_r_lcl_reg: unisim.vcomponents.FDRE
     port map (
      C => \req_col_r_reg[9]_1\,
      CE => E(0),
      D => periodic_rd_insert,
      Q => req_periodic_rd_r(0),
      R => '0'
    );
req_priority_r_reg: unisim.vcomponents.FDRE
     port map (
      C => \req_col_r_reg[9]_1\,
      CE => E(0),
      D => hi_priority,
      Q => req_priority_r,
      R => '0'
    );
\req_row_r_lcl_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \req_col_r_reg[9]_1\,
      CE => E(0),
      D => \req_row_r_lcl_reg[13]_1\(0),
      Q => \^req_row_r_lcl_reg[13]_0\(0),
      R => '0'
    );
\req_row_r_lcl_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => \req_col_r_reg[9]_1\,
      CE => E(0),
      D => \req_row_r_lcl_reg[13]_1\(10),
      Q => \^req_row_r_lcl_reg[13]_0\(10),
      R => '0'
    );
\req_row_r_lcl_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => \req_col_r_reg[9]_1\,
      CE => E(0),
      D => \req_row_r_lcl_reg[13]_1\(11),
      Q => \^req_row_r_lcl_reg[13]_0\(11),
      R => '0'
    );
\req_row_r_lcl_reg[12]\: unisim.vcomponents.FDRE
     port map (
      C => \req_col_r_reg[9]_1\,
      CE => E(0),
      D => \req_row_r_lcl_reg[13]_1\(12),
      Q => \^req_row_r_lcl_reg[13]_0\(12),
      R => '0'
    );
\req_row_r_lcl_reg[13]\: unisim.vcomponents.FDRE
     port map (
      C => \req_col_r_reg[9]_1\,
      CE => E(0),
      D => \req_row_r_lcl_reg[13]_1\(13),
      Q => \^req_row_r_lcl_reg[13]_0\(13),
      R => '0'
    );
\req_row_r_lcl_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \req_col_r_reg[9]_1\,
      CE => E(0),
      D => \req_row_r_lcl_reg[13]_1\(1),
      Q => \^req_row_r_lcl_reg[13]_0\(1),
      R => '0'
    );
\req_row_r_lcl_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \req_col_r_reg[9]_1\,
      CE => E(0),
      D => \req_row_r_lcl_reg[13]_1\(2),
      Q => \^req_row_r_lcl_reg[13]_0\(2),
      R => '0'
    );
\req_row_r_lcl_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => \req_col_r_reg[9]_1\,
      CE => E(0),
      D => \req_row_r_lcl_reg[13]_1\(3),
      Q => \^req_row_r_lcl_reg[13]_0\(3),
      R => '0'
    );
\req_row_r_lcl_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => \req_col_r_reg[9]_1\,
      CE => E(0),
      D => \req_row_r_lcl_reg[13]_1\(4),
      Q => \^req_row_r_lcl_reg[13]_0\(4),
      R => '0'
    );
\req_row_r_lcl_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => \req_col_r_reg[9]_1\,
      CE => E(0),
      D => \req_row_r_lcl_reg[13]_1\(5),
      Q => \^req_row_r_lcl_reg[13]_0\(5),
      R => '0'
    );
\req_row_r_lcl_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => \req_col_r_reg[9]_1\,
      CE => E(0),
      D => \req_row_r_lcl_reg[13]_1\(6),
      Q => \^req_row_r_lcl_reg[13]_0\(6),
      R => '0'
    );
\req_row_r_lcl_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => \req_col_r_reg[9]_1\,
      CE => E(0),
      D => \req_row_r_lcl_reg[13]_1\(7),
      Q => \^req_row_r_lcl_reg[13]_0\(7),
      R => '0'
    );
\req_row_r_lcl_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => \req_col_r_reg[9]_1\,
      CE => E(0),
      D => \req_row_r_lcl_reg[13]_1\(8),
      Q => \^req_row_r_lcl_reg[13]_0\(8),
      R => '0'
    );
\req_row_r_lcl_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => \req_col_r_reg[9]_1\,
      CE => E(0),
      D => \req_row_r_lcl_reg[13]_1\(9),
      Q => \^req_row_r_lcl_reg[13]_0\(9),
      R => '0'
    );
req_wr_r_lcl_reg: unisim.vcomponents.FDRE
     port map (
      C => \req_col_r_reg[9]_1\,
      CE => E(0),
      D => req_wr_r_lcl0,
      Q => \^req_wr_r_lcl_reg_0\,
      R => '0'
    );
row_hit_ns_carry: unisim.vcomponents.CARRY4
     port map (
      CI => '0',
      CO(3) => row_hit_ns_carry_n_0,
      CO(2) => row_hit_ns_carry_n_1,
      CO(1) => row_hit_ns_carry_n_2,
      CO(0) => row_hit_ns_carry_n_3,
      CYINIT => '1',
      DI(3 downto 0) => B"0000",
      O(3 downto 0) => NLW_row_hit_ns_carry_O_UNCONNECTED(3 downto 0),
      S(3) => \row_hit_ns_carry_i_1__1_n_0\,
      S(2) => \row_hit_ns_carry_i_2__1_n_0\,
      S(1) => \row_hit_ns_carry_i_3__1_n_0\,
      S(0) => \row_hit_ns_carry_i_4__1_n_0\
    );
\row_hit_ns_carry__0\: unisim.vcomponents.CARRY4
     port map (
      CI => row_hit_ns_carry_n_0,
      CO(3 downto 1) => \NLW_row_hit_ns_carry__0_CO_UNCONNECTED\(3 downto 1),
      CO(0) => \row_hit_ns_carry__0_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3 downto 0) => \NLW_row_hit_ns_carry__0_O_UNCONNECTED\(3 downto 0),
      S(3 downto 1) => B"000",
      S(0) => row_hit_r_reg_1(0)
    );
\row_hit_ns_carry_i_1__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"9009000000009009"
    )
        port map (
      I0 => \^req_row_r_lcl_reg[13]_0\(11),
      I1 => \req_row_r_lcl_reg[13]_1\(11),
      I2 => \^req_row_r_lcl_reg[13]_0\(9),
      I3 => \req_row_r_lcl_reg[13]_1\(9),
      I4 => \req_row_r_lcl_reg[13]_1\(10),
      I5 => \^req_row_r_lcl_reg[13]_0\(10),
      O => \row_hit_ns_carry_i_1__1_n_0\
    );
\row_hit_ns_carry_i_2__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"9009000000009009"
    )
        port map (
      I0 => \^req_row_r_lcl_reg[13]_0\(8),
      I1 => \req_row_r_lcl_reg[13]_1\(8),
      I2 => \^req_row_r_lcl_reg[13]_0\(6),
      I3 => \req_row_r_lcl_reg[13]_1\(6),
      I4 => \req_row_r_lcl_reg[13]_1\(7),
      I5 => \^req_row_r_lcl_reg[13]_0\(7),
      O => \row_hit_ns_carry_i_2__1_n_0\
    );
\row_hit_ns_carry_i_3__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"9009000000009009"
    )
        port map (
      I0 => \^req_row_r_lcl_reg[13]_0\(5),
      I1 => \req_row_r_lcl_reg[13]_1\(5),
      I2 => \^req_row_r_lcl_reg[13]_0\(4),
      I3 => \req_row_r_lcl_reg[13]_1\(4),
      I4 => \req_row_r_lcl_reg[13]_1\(3),
      I5 => \^req_row_r_lcl_reg[13]_0\(3),
      O => \row_hit_ns_carry_i_3__1_n_0\
    );
\row_hit_ns_carry_i_4__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"9009000000009009"
    )
        port map (
      I0 => \^req_row_r_lcl_reg[13]_0\(2),
      I1 => \req_row_r_lcl_reg[13]_1\(2),
      I2 => \^req_row_r_lcl_reg[13]_0\(1),
      I3 => \req_row_r_lcl_reg[13]_1\(1),
      I4 => \req_row_r_lcl_reg[13]_1\(0),
      I5 => \^req_row_r_lcl_reg[13]_0\(0),
      O => \row_hit_ns_carry_i_4__1_n_0\
    );
row_hit_r_reg: unisim.vcomponents.FDRE
     port map (
      C => \req_col_r_reg[9]_1\,
      CE => '1',
      D => \row_hit_ns_carry__0_n_3\,
      Q => row_hit_r,
      R => '0'
    );
\wr_this_rank_r[0]_i_1__1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \^rd_wr_r_lcl_reg_0\,
      O => start_wtp_timer0
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mig_mig_7series_v4_2_bank_compare_1 is
  port (
    rb_hit_busy_r_reg_0 : out STD_LOGIC;
    req_periodic_rd_r : out STD_LOGIC_VECTOR ( 0 to 0 );
    rd_wr_r_lcl_reg_0 : out STD_LOGIC;
    req_wr_r_lcl_reg_0 : out STD_LOGIC;
    req_priority_r : out STD_LOGIC;
    \grant_r_reg[1]\ : out STD_LOGIC;
    row_hit_r_reg_0 : out STD_LOGIC;
    start_wtp_timer0 : out STD_LOGIC;
    \req_row_r_lcl_reg[13]_0\ : out STD_LOGIC_VECTOR ( 13 downto 0 );
    \req_data_buf_addr_r_reg[3]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
    \req_bank_r_lcl_reg[2]_0\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
    \req_col_r_reg[9]_0\ : out STD_LOGIC_VECTOR ( 9 downto 0 );
    p_106_out : in STD_LOGIC;
    row_hit_r_reg_1 : in STD_LOGIC;
    E : in STD_LOGIC_VECTOR ( 0 to 0 );
    periodic_rd_insert : in STD_LOGIC;
    req_wr_r_lcl0 : in STD_LOGIC;
    hi_priority : in STD_LOGIC;
    row_hit_r_reg_2 : in STD_LOGIC_VECTOR ( 0 to 0 );
    row_hit_r_reg_3 : in STD_LOGIC_VECTOR ( 0 to 0 );
    Q : in STD_LOGIC_VECTOR ( 0 to 0 );
    rd_wr_r_lcl_reg_1 : in STD_LOGIC;
    rd_wr_r_lcl_reg_2 : in STD_LOGIC;
    ordered_r_lcl_reg : in STD_LOGIC;
    ordered_r_lcl_reg_0 : in STD_LOGIC;
    ordered_r_lcl_reg_1 : in STD_LOGIC;
    maint_req_r : in STD_LOGIC;
    pass_open_bank_r_lcl_reg : in STD_LOGIC;
    pass_open_bank_r_lcl_reg_0 : in STD_LOGIC;
    wait_for_maint_r_13 : in STD_LOGIC;
    \req_row_r_lcl_reg[13]_1\ : in STD_LOGIC_VECTOR ( 13 downto 0 );
    \req_data_buf_addr_r_reg[3]_1\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \req_data_buf_addr_r_reg[3]_2\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
    \req_bank_r_lcl_reg[2]_1\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
    \req_col_r_reg[9]_1\ : in STD_LOGIC_VECTOR ( 9 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of mig_mig_7series_v4_2_bank_compare_1 : entity is "mig_7series_v4_2_bank_compare";
end mig_mig_7series_v4_2_bank_compare_1;

architecture STRUCTURE of mig_mig_7series_v4_2_bank_compare_1 is
  signal rd_wr_ns : STD_LOGIC;
  signal \^rd_wr_r_lcl_reg_0\ : STD_LOGIC;
  signal \^req_row_r_lcl_reg[13]_0\ : STD_LOGIC_VECTOR ( 13 downto 0 );
  signal \^req_wr_r_lcl_reg_0\ : STD_LOGIC;
  signal \row_hit_ns_carry__0_n_3\ : STD_LOGIC;
  signal \row_hit_ns_carry_i_2__0_n_0\ : STD_LOGIC;
  signal \row_hit_ns_carry_i_3__0_n_0\ : STD_LOGIC;
  signal \row_hit_ns_carry_i_4__0_n_0\ : STD_LOGIC;
  signal row_hit_ns_carry_n_0 : STD_LOGIC;
  signal row_hit_ns_carry_n_1 : STD_LOGIC;
  signal row_hit_ns_carry_n_2 : STD_LOGIC;
  signal row_hit_ns_carry_n_3 : STD_LOGIC;
  signal row_hit_r : STD_LOGIC;
  signal NLW_row_hit_ns_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \NLW_row_hit_ns_carry__0_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
  signal \NLW_row_hit_ns_carry__0_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of rd_wr_r_lcl_i_1 : label is "soft_lutpair1164";
  attribute SOFT_HLUTNM of \wr_this_rank_r[0]_i_1__0\ : label is "soft_lutpair1164";
begin
  rd_wr_r_lcl_reg_0 <= \^rd_wr_r_lcl_reg_0\;
  \req_row_r_lcl_reg[13]_0\(13 downto 0) <= \^req_row_r_lcl_reg[13]_0\(13 downto 0);
  req_wr_r_lcl_reg_0 <= \^req_wr_r_lcl_reg_0\;
\i___62_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AAAA00A2"
    )
        port map (
      I0 => row_hit_r,
      I1 => maint_req_r,
      I2 => pass_open_bank_r_lcl_reg,
      I3 => pass_open_bank_r_lcl_reg_0,
      I4 => wait_for_maint_r_13,
      O => row_hit_r_reg_0
    );
ordered_r_lcl_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000D5D5D500"
    )
        port map (
      I0 => Q(0),
      I1 => \^rd_wr_r_lcl_reg_0\,
      I2 => \^req_wr_r_lcl_reg_0\,
      I3 => ordered_r_lcl_reg,
      I4 => ordered_r_lcl_reg_0,
      I5 => ordered_r_lcl_reg_1,
      O => \grant_r_reg[1]\
    );
rb_hit_busy_r_reg: unisim.vcomponents.FDRE
     port map (
      C => row_hit_r_reg_1,
      CE => '1',
      D => p_106_out,
      Q => rb_hit_busy_r_reg_0,
      R => '0'
    );
rd_wr_r_lcl_i_1: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F20"
    )
        port map (
      I0 => \^rd_wr_r_lcl_reg_0\,
      I1 => Q(0),
      I2 => rd_wr_r_lcl_reg_1,
      I3 => rd_wr_r_lcl_reg_2,
      O => rd_wr_ns
    );
rd_wr_r_lcl_reg: unisim.vcomponents.FDRE
     port map (
      C => row_hit_r_reg_1,
      CE => '1',
      D => rd_wr_ns,
      Q => \^rd_wr_r_lcl_reg_0\,
      R => '0'
    );
\req_bank_r_lcl_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => row_hit_r_reg_1,
      CE => E(0),
      D => \req_bank_r_lcl_reg[2]_1\(0),
      Q => \req_bank_r_lcl_reg[2]_0\(0),
      R => '0'
    );
\req_bank_r_lcl_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => row_hit_r_reg_1,
      CE => E(0),
      D => \req_bank_r_lcl_reg[2]_1\(1),
      Q => \req_bank_r_lcl_reg[2]_0\(1),
      R => '0'
    );
\req_bank_r_lcl_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => row_hit_r_reg_1,
      CE => E(0),
      D => \req_bank_r_lcl_reg[2]_1\(2),
      Q => \req_bank_r_lcl_reg[2]_0\(2),
      R => '0'
    );
\req_col_r_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => row_hit_r_reg_1,
      CE => E(0),
      D => \req_col_r_reg[9]_1\(0),
      Q => \req_col_r_reg[9]_0\(0),
      R => '0'
    );
\req_col_r_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => row_hit_r_reg_1,
      CE => E(0),
      D => \req_col_r_reg[9]_1\(1),
      Q => \req_col_r_reg[9]_0\(1),
      R => '0'
    );
\req_col_r_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => row_hit_r_reg_1,
      CE => E(0),
      D => \req_col_r_reg[9]_1\(2),
      Q => \req_col_r_reg[9]_0\(2),
      R => '0'
    );
\req_col_r_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => row_hit_r_reg_1,
      CE => E(0),
      D => \req_col_r_reg[9]_1\(3),
      Q => \req_col_r_reg[9]_0\(3),
      R => '0'
    );
\req_col_r_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => row_hit_r_reg_1,
      CE => E(0),
      D => \req_col_r_reg[9]_1\(4),
      Q => \req_col_r_reg[9]_0\(4),
      R => '0'
    );
\req_col_r_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => row_hit_r_reg_1,
      CE => E(0),
      D => \req_col_r_reg[9]_1\(5),
      Q => \req_col_r_reg[9]_0\(5),
      R => '0'
    );
\req_col_r_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => row_hit_r_reg_1,
      CE => E(0),
      D => \req_col_r_reg[9]_1\(6),
      Q => \req_col_r_reg[9]_0\(6),
      R => '0'
    );
\req_col_r_reg[7]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => row_hit_r_reg_1,
      CE => E(0),
      D => \req_col_r_reg[9]_1\(7),
      Q => \req_col_r_reg[9]_0\(7),
      R => '0'
    );
\req_col_r_reg[8]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => row_hit_r_reg_1,
      CE => E(0),
      D => \req_col_r_reg[9]_1\(8),
      Q => \req_col_r_reg[9]_0\(8),
      R => '0'
    );
\req_col_r_reg[9]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => row_hit_r_reg_1,
      CE => E(0),
      D => \req_col_r_reg[9]_1\(9),
      Q => \req_col_r_reg[9]_0\(9),
      R => '0'
    );
\req_data_buf_addr_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => row_hit_r_reg_1,
      CE => \req_data_buf_addr_r_reg[3]_1\(0),
      D => \req_data_buf_addr_r_reg[3]_2\(0),
      Q => \req_data_buf_addr_r_reg[3]_0\(0),
      R => '0'
    );
\req_data_buf_addr_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => row_hit_r_reg_1,
      CE => \req_data_buf_addr_r_reg[3]_1\(0),
      D => \req_data_buf_addr_r_reg[3]_2\(1),
      Q => \req_data_buf_addr_r_reg[3]_0\(1),
      R => '0'
    );
\req_data_buf_addr_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => row_hit_r_reg_1,
      CE => \req_data_buf_addr_r_reg[3]_1\(0),
      D => \req_data_buf_addr_r_reg[3]_2\(2),
      Q => \req_data_buf_addr_r_reg[3]_0\(2),
      R => '0'
    );
\req_data_buf_addr_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => row_hit_r_reg_1,
      CE => \req_data_buf_addr_r_reg[3]_1\(0),
      D => \req_data_buf_addr_r_reg[3]_2\(3),
      Q => \req_data_buf_addr_r_reg[3]_0\(3),
      R => '0'
    );
req_periodic_rd_r_lcl_reg: unisim.vcomponents.FDRE
     port map (
      C => row_hit_r_reg_1,
      CE => E(0),
      D => periodic_rd_insert,
      Q => req_periodic_rd_r(0),
      R => '0'
    );
req_priority_r_reg: unisim.vcomponents.FDRE
     port map (
      C => row_hit_r_reg_1,
      CE => E(0),
      D => hi_priority,
      Q => req_priority_r,
      R => '0'
    );
\req_row_r_lcl_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => row_hit_r_reg_1,
      CE => E(0),
      D => \req_row_r_lcl_reg[13]_1\(0),
      Q => \^req_row_r_lcl_reg[13]_0\(0),
      R => '0'
    );
\req_row_r_lcl_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => row_hit_r_reg_1,
      CE => E(0),
      D => \req_row_r_lcl_reg[13]_1\(10),
      Q => \^req_row_r_lcl_reg[13]_0\(10),
      R => '0'
    );
\req_row_r_lcl_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => row_hit_r_reg_1,
      CE => E(0),
      D => \req_row_r_lcl_reg[13]_1\(11),
      Q => \^req_row_r_lcl_reg[13]_0\(11),
      R => '0'
    );
\req_row_r_lcl_reg[12]\: unisim.vcomponents.FDRE
     port map (
      C => row_hit_r_reg_1,
      CE => E(0),
      D => \req_row_r_lcl_reg[13]_1\(12),
      Q => \^req_row_r_lcl_reg[13]_0\(12),
      R => '0'
    );
\req_row_r_lcl_reg[13]\: unisim.vcomponents.FDRE
     port map (
      C => row_hit_r_reg_1,
      CE => E(0),
      D => \req_row_r_lcl_reg[13]_1\(13),
      Q => \^req_row_r_lcl_reg[13]_0\(13),
      R => '0'
    );
\req_row_r_lcl_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => row_hit_r_reg_1,
      CE => E(0),
      D => \req_row_r_lcl_reg[13]_1\(1),
      Q => \^req_row_r_lcl_reg[13]_0\(1),
      R => '0'
    );
\req_row_r_lcl_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => row_hit_r_reg_1,
      CE => E(0),
      D => \req_row_r_lcl_reg[13]_1\(2),
      Q => \^req_row_r_lcl_reg[13]_0\(2),
      R => '0'
    );
\req_row_r_lcl_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => row_hit_r_reg_1,
      CE => E(0),
      D => \req_row_r_lcl_reg[13]_1\(3),
      Q => \^req_row_r_lcl_reg[13]_0\(3),
      R => '0'
    );
\req_row_r_lcl_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => row_hit_r_reg_1,
      CE => E(0),
      D => \req_row_r_lcl_reg[13]_1\(4),
      Q => \^req_row_r_lcl_reg[13]_0\(4),
      R => '0'
    );
\req_row_r_lcl_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => row_hit_r_reg_1,
      CE => E(0),
      D => \req_row_r_lcl_reg[13]_1\(5),
      Q => \^req_row_r_lcl_reg[13]_0\(5),
      R => '0'
    );
\req_row_r_lcl_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => row_hit_r_reg_1,
      CE => E(0),
      D => \req_row_r_lcl_reg[13]_1\(6),
      Q => \^req_row_r_lcl_reg[13]_0\(6),
      R => '0'
    );
\req_row_r_lcl_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => row_hit_r_reg_1,
      CE => E(0),
      D => \req_row_r_lcl_reg[13]_1\(7),
      Q => \^req_row_r_lcl_reg[13]_0\(7),
      R => '0'
    );
\req_row_r_lcl_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => row_hit_r_reg_1,
      CE => E(0),
      D => \req_row_r_lcl_reg[13]_1\(8),
      Q => \^req_row_r_lcl_reg[13]_0\(8),
      R => '0'
    );
\req_row_r_lcl_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => row_hit_r_reg_1,
      CE => E(0),
      D => \req_row_r_lcl_reg[13]_1\(9),
      Q => \^req_row_r_lcl_reg[13]_0\(9),
      R => '0'
    );
req_wr_r_lcl_reg: unisim.vcomponents.FDRE
     port map (
      C => row_hit_r_reg_1,
      CE => E(0),
      D => req_wr_r_lcl0,
      Q => \^req_wr_r_lcl_reg_0\,
      R => '0'
    );
row_hit_ns_carry: unisim.vcomponents.CARRY4
     port map (
      CI => '0',
      CO(3) => row_hit_ns_carry_n_0,
      CO(2) => row_hit_ns_carry_n_1,
      CO(1) => row_hit_ns_carry_n_2,
      CO(0) => row_hit_ns_carry_n_3,
      CYINIT => '1',
      DI(3 downto 0) => B"0000",
      O(3 downto 0) => NLW_row_hit_ns_carry_O_UNCONNECTED(3 downto 0),
      S(3) => row_hit_r_reg_2(0),
      S(2) => \row_hit_ns_carry_i_2__0_n_0\,
      S(1) => \row_hit_ns_carry_i_3__0_n_0\,
      S(0) => \row_hit_ns_carry_i_4__0_n_0\
    );
\row_hit_ns_carry__0\: unisim.vcomponents.CARRY4
     port map (
      CI => row_hit_ns_carry_n_0,
      CO(3 downto 1) => \NLW_row_hit_ns_carry__0_CO_UNCONNECTED\(3 downto 1),
      CO(0) => \row_hit_ns_carry__0_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3 downto 0) => \NLW_row_hit_ns_carry__0_O_UNCONNECTED\(3 downto 0),
      S(3 downto 1) => B"000",
      S(0) => row_hit_r_reg_3(0)
    );
\row_hit_ns_carry_i_2__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"9009000000009009"
    )
        port map (
      I0 => \^req_row_r_lcl_reg[13]_0\(8),
      I1 => \req_row_r_lcl_reg[13]_1\(8),
      I2 => \^req_row_r_lcl_reg[13]_0\(7),
      I3 => \req_row_r_lcl_reg[13]_1\(7),
      I4 => \req_row_r_lcl_reg[13]_1\(6),
      I5 => \^req_row_r_lcl_reg[13]_0\(6),
      O => \row_hit_ns_carry_i_2__0_n_0\
    );
\row_hit_ns_carry_i_3__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"9009000000009009"
    )
        port map (
      I0 => \^req_row_r_lcl_reg[13]_0\(5),
      I1 => \req_row_r_lcl_reg[13]_1\(5),
      I2 => \^req_row_r_lcl_reg[13]_0\(4),
      I3 => \req_row_r_lcl_reg[13]_1\(4),
      I4 => \req_row_r_lcl_reg[13]_1\(3),
      I5 => \^req_row_r_lcl_reg[13]_0\(3),
      O => \row_hit_ns_carry_i_3__0_n_0\
    );
\row_hit_ns_carry_i_4__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"9009000000009009"
    )
        port map (
      I0 => \^req_row_r_lcl_reg[13]_0\(2),
      I1 => \req_row_r_lcl_reg[13]_1\(2),
      I2 => \^req_row_r_lcl_reg[13]_0\(1),
      I3 => \req_row_r_lcl_reg[13]_1\(1),
      I4 => \req_row_r_lcl_reg[13]_1\(0),
      I5 => \^req_row_r_lcl_reg[13]_0\(0),
      O => \row_hit_ns_carry_i_4__0_n_0\
    );
row_hit_r_reg: unisim.vcomponents.FDRE
     port map (
      C => row_hit_r_reg_1,
      CE => '1',
      D => \row_hit_ns_carry__0_n_3\,
      Q => row_hit_r,
      R => '0'
    );
\wr_this_rank_r[0]_i_1__0\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \^rd_wr_r_lcl_reg_0\,
      O => start_wtp_timer0
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mig_mig_7series_v4_2_bank_compare_2 is
  port (
    rb_hit_busy_r_reg_0 : out STD_LOGIC;
    req_periodic_rd_r : out STD_LOGIC_VECTOR ( 0 to 0 );
    rd_wr_r_lcl_reg_0 : out STD_LOGIC;
    req_wr_r : out STD_LOGIC_VECTOR ( 0 to 0 );
    req_priority_r : out STD_LOGIC;
    ordered_r_lcl_reg : out STD_LOGIC;
    rd_wr_r_lcl_reg_1 : out STD_LOGIC;
    \grant_r_reg[0]\ : out STD_LOGIC;
    rd_wr_r_lcl_reg_2 : out STD_LOGIC;
    rd_wr_r_lcl_reg_3 : out STD_LOGIC;
    row_hit_r_reg_0 : out STD_LOGIC;
    start_wtp_timer0 : out STD_LOGIC;
    \req_row_r_lcl_reg[13]_0\ : out STD_LOGIC_VECTOR ( 13 downto 0 );
    rb_hit_busy_r_reg_1 : out STD_LOGIC;
    rb_hit_busy_r_reg_2 : out STD_LOGIC;
    \req_data_buf_addr_r_reg[3]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
    \req_bank_r_lcl_reg[2]_0\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
    \req_col_r_reg[9]_0\ : out STD_LOGIC_VECTOR ( 9 downto 0 );
    p_145_out : in STD_LOGIC;
    \req_col_r_reg[9]_1\ : in STD_LOGIC;
    E : in STD_LOGIC_VECTOR ( 0 to 0 );
    periodic_rd_insert : in STD_LOGIC;
    req_wr_r_lcl0 : in STD_LOGIC;
    hi_priority : in STD_LOGIC;
    S : in STD_LOGIC_VECTOR ( 2 downto 0 );
    row_hit_r_reg_1 : in STD_LOGIC_VECTOR ( 0 to 0 );
    ordered_r_lcl : in STD_LOGIC;
    \order_q_r_reg[1]\ : in STD_LOGIC;
    \order_q_r_reg[1]_0\ : in STD_LOGIC;
    \order_q_r_reg[1]_1\ : in STD_LOGIC;
    req_bank_rdy_r_reg : in STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 0 to 0 );
    req_bank_rdy_r_reg_0 : in STD_LOGIC;
    req_bank_rdy_r_reg_1 : in STD_LOGIC;
    rd_wr_r_lcl_reg_4 : in STD_LOGIC;
    rd_wr_r_lcl_reg_5 : in STD_LOGIC;
    ordered_r_lcl_reg_0 : in STD_LOGIC;
    ordered_r_lcl_reg_1 : in STD_LOGIC;
    maint_req_r : in STD_LOGIC;
    pass_open_bank_r_lcl_reg : in STD_LOGIC;
    pass_open_bank_r_lcl_reg_0 : in STD_LOGIC;
    wait_for_maint_r : in STD_LOGIC;
    \req_row_r_lcl_reg[13]_1\ : in STD_LOGIC_VECTOR ( 13 downto 0 );
    \q_entry_r[0]_i_2__1\ : in STD_LOGIC;
    \q_entry_r[0]_i_2__1_0\ : in STD_LOGIC;
    \q_entry_r[0]_i_2__1_1\ : in STD_LOGIC;
    \req_data_buf_addr_r_reg[3]_1\ : in STD_LOGIC;
    \req_data_buf_addr_r_reg[3]_2\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
    \req_bank_r_lcl_reg[2]_1\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
    \req_col_r_reg[9]_2\ : in STD_LOGIC_VECTOR ( 9 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of mig_mig_7series_v4_2_bank_compare_2 : entity is "mig_7series_v4_2_bank_compare";
end mig_mig_7series_v4_2_bank_compare_2;

architecture STRUCTURE of mig_mig_7series_v4_2_bank_compare_2 is
  signal \^rb_hit_busy_r_reg_0\ : STD_LOGIC;
  signal rd_wr_ns : STD_LOGIC;
  signal \^rd_wr_r_lcl_reg_0\ : STD_LOGIC;
  signal \^rd_wr_r_lcl_reg_1\ : STD_LOGIC;
  signal \^req_row_r_lcl_reg[13]_0\ : STD_LOGIC_VECTOR ( 13 downto 0 );
  signal \^req_wr_r\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal row_hit_ns : STD_LOGIC;
  signal row_hit_ns_carry_i_1_n_0 : STD_LOGIC;
  signal row_hit_ns_carry_n_0 : STD_LOGIC;
  signal row_hit_ns_carry_n_1 : STD_LOGIC;
  signal row_hit_ns_carry_n_2 : STD_LOGIC;
  signal row_hit_ns_carry_n_3 : STD_LOGIC;
  signal row_hit_r : STD_LOGIC;
  signal NLW_row_hit_ns_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \NLW_row_hit_ns_carry__0_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
  signal \NLW_row_hit_ns_carry__0_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \grant_r[3]_i_15\ : label is "soft_lutpair1150";
  attribute SOFT_HLUTNM of \i___3_i_5\ : label is "soft_lutpair1151";
  attribute SOFT_HLUTNM of \i___3_i_7\ : label is "soft_lutpair1151";
  attribute SOFT_HLUTNM of \ras_timer_r[1]_i_5\ : label is "soft_lutpair1152";
  attribute SOFT_HLUTNM of \rd_wr_r_lcl_i_1__2\ : label is "soft_lutpair1150";
  attribute SOFT_HLUTNM of \wr_this_rank_r[0]_i_1\ : label is "soft_lutpair1152";
begin
  rb_hit_busy_r_reg_0 <= \^rb_hit_busy_r_reg_0\;
  rd_wr_r_lcl_reg_0 <= \^rd_wr_r_lcl_reg_0\;
  rd_wr_r_lcl_reg_1 <= \^rd_wr_r_lcl_reg_1\;
  \req_row_r_lcl_reg[13]_0\(13 downto 0) <= \^req_row_r_lcl_reg[13]_0\(13 downto 0);
  req_wr_r(0) <= \^req_wr_r\(0);
\grant_r[3]_i_15\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"8F"
    )
        port map (
      I0 => \^rd_wr_r_lcl_reg_0\,
      I1 => \^req_wr_r\(0),
      I2 => Q(0),
      O => rd_wr_r_lcl_reg_2
    );
\i___3_i_5\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6996"
    )
        port map (
      I0 => \^rb_hit_busy_r_reg_0\,
      I1 => \q_entry_r[0]_i_2__1_1\,
      I2 => \q_entry_r[0]_i_2__1_0\,
      I3 => \q_entry_r[0]_i_2__1\,
      O => rb_hit_busy_r_reg_2
    );
\i___3_i_7\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7EE8"
    )
        port map (
      I0 => \^rb_hit_busy_r_reg_0\,
      I1 => \q_entry_r[0]_i_2__1\,
      I2 => \q_entry_r[0]_i_2__1_0\,
      I3 => \q_entry_r[0]_i_2__1_1\,
      O => rb_hit_busy_r_reg_1
    );
\i___61_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AAAA00A2"
    )
        port map (
      I0 => row_hit_r,
      I1 => maint_req_r,
      I2 => pass_open_bank_r_lcl_reg,
      I3 => pass_open_bank_r_lcl_reg_0,
      I4 => wait_for_maint_r,
      O => row_hit_r_reg_0
    );
\order_q_r[1]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"BDD4D442"
    )
        port map (
      I0 => \^rd_wr_r_lcl_reg_1\,
      I1 => ordered_r_lcl,
      I2 => \order_q_r_reg[1]\,
      I3 => \order_q_r_reg[1]_0\,
      I4 => \order_q_r_reg[1]_1\,
      O => ordered_r_lcl_reg
    );
\ordered_r_lcl_i_1__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000D5D5D500"
    )
        port map (
      I0 => Q(0),
      I1 => \^req_wr_r\(0),
      I2 => \^rd_wr_r_lcl_reg_0\,
      I3 => ordered_r_lcl_reg_0,
      I4 => ordered_r_lcl,
      I5 => ordered_r_lcl_reg_1,
      O => \grant_r_reg[0]\
    );
\ras_timer_r[1]_i_5\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => \^rd_wr_r_lcl_reg_0\,
      I1 => Q(0),
      O => rd_wr_r_lcl_reg_3
    );
rb_hit_busy_r_reg: unisim.vcomponents.FDRE
     port map (
      C => \req_col_r_reg[9]_1\,
      CE => '1',
      D => p_145_out,
      Q => \^rb_hit_busy_r_reg_0\,
      R => '0'
    );
\rd_wr_r_lcl_i_1__2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F20"
    )
        port map (
      I0 => \^rd_wr_r_lcl_reg_0\,
      I1 => Q(0),
      I2 => rd_wr_r_lcl_reg_4,
      I3 => rd_wr_r_lcl_reg_5,
      O => rd_wr_ns
    );
rd_wr_r_lcl_reg: unisim.vcomponents.FDRE
     port map (
      C => \req_col_r_reg[9]_1\,
      CE => '1',
      D => rd_wr_ns,
      Q => \^rd_wr_r_lcl_reg_0\,
      R => '0'
    );
\req_bank_r_lcl_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \req_col_r_reg[9]_1\,
      CE => E(0),
      D => \req_bank_r_lcl_reg[2]_1\(0),
      Q => \req_bank_r_lcl_reg[2]_0\(0),
      R => '0'
    );
\req_bank_r_lcl_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \req_col_r_reg[9]_1\,
      CE => E(0),
      D => \req_bank_r_lcl_reg[2]_1\(1),
      Q => \req_bank_r_lcl_reg[2]_0\(1),
      R => '0'
    );
\req_bank_r_lcl_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \req_col_r_reg[9]_1\,
      CE => E(0),
      D => \req_bank_r_lcl_reg[2]_1\(2),
      Q => \req_bank_r_lcl_reg[2]_0\(2),
      R => '0'
    );
req_bank_rdy_r_i_2: unisim.vcomponents.LUT6
    generic map(
      INIT => X"7F55FFFFFFFFFFFF"
    )
        port map (
      I0 => req_bank_rdy_r_reg,
      I1 => \^rd_wr_r_lcl_reg_0\,
      I2 => \^req_wr_r\(0),
      I3 => Q(0),
      I4 => req_bank_rdy_r_reg_0,
      I5 => req_bank_rdy_r_reg_1,
      O => \^rd_wr_r_lcl_reg_1\
    );
\req_col_r_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \req_col_r_reg[9]_1\,
      CE => E(0),
      D => \req_col_r_reg[9]_2\(0),
      Q => \req_col_r_reg[9]_0\(0),
      R => '0'
    );
\req_col_r_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \req_col_r_reg[9]_1\,
      CE => E(0),
      D => \req_col_r_reg[9]_2\(1),
      Q => \req_col_r_reg[9]_0\(1),
      R => '0'
    );
\req_col_r_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \req_col_r_reg[9]_1\,
      CE => E(0),
      D => \req_col_r_reg[9]_2\(2),
      Q => \req_col_r_reg[9]_0\(2),
      R => '0'
    );
\req_col_r_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \req_col_r_reg[9]_1\,
      CE => E(0),
      D => \req_col_r_reg[9]_2\(3),
      Q => \req_col_r_reg[9]_0\(3),
      R => '0'
    );
\req_col_r_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \req_col_r_reg[9]_1\,
      CE => E(0),
      D => \req_col_r_reg[9]_2\(4),
      Q => \req_col_r_reg[9]_0\(4),
      R => '0'
    );
\req_col_r_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \req_col_r_reg[9]_1\,
      CE => E(0),
      D => \req_col_r_reg[9]_2\(5),
      Q => \req_col_r_reg[9]_0\(5),
      R => '0'
    );
\req_col_r_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \req_col_r_reg[9]_1\,
      CE => E(0),
      D => \req_col_r_reg[9]_2\(6),
      Q => \req_col_r_reg[9]_0\(6),
      R => '0'
    );
\req_col_r_reg[7]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \req_col_r_reg[9]_1\,
      CE => E(0),
      D => \req_col_r_reg[9]_2\(7),
      Q => \req_col_r_reg[9]_0\(7),
      R => '0'
    );
\req_col_r_reg[8]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \req_col_r_reg[9]_1\,
      CE => E(0),
      D => \req_col_r_reg[9]_2\(8),
      Q => \req_col_r_reg[9]_0\(8),
      R => '0'
    );
\req_col_r_reg[9]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \req_col_r_reg[9]_1\,
      CE => E(0),
      D => \req_col_r_reg[9]_2\(9),
      Q => \req_col_r_reg[9]_0\(9),
      R => '0'
    );
\req_data_buf_addr_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \req_col_r_reg[9]_1\,
      CE => \req_data_buf_addr_r_reg[3]_1\,
      D => \req_data_buf_addr_r_reg[3]_2\(0),
      Q => \req_data_buf_addr_r_reg[3]_0\(0),
      R => '0'
    );
\req_data_buf_addr_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \req_col_r_reg[9]_1\,
      CE => \req_data_buf_addr_r_reg[3]_1\,
      D => \req_data_buf_addr_r_reg[3]_2\(1),
      Q => \req_data_buf_addr_r_reg[3]_0\(1),
      R => '0'
    );
\req_data_buf_addr_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \req_col_r_reg[9]_1\,
      CE => \req_data_buf_addr_r_reg[3]_1\,
      D => \req_data_buf_addr_r_reg[3]_2\(2),
      Q => \req_data_buf_addr_r_reg[3]_0\(2),
      R => '0'
    );
\req_data_buf_addr_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => \req_col_r_reg[9]_1\,
      CE => \req_data_buf_addr_r_reg[3]_1\,
      D => \req_data_buf_addr_r_reg[3]_2\(3),
      Q => \req_data_buf_addr_r_reg[3]_0\(3),
      R => '0'
    );
req_periodic_rd_r_lcl_reg: unisim.vcomponents.FDRE
     port map (
      C => \req_col_r_reg[9]_1\,
      CE => E(0),
      D => periodic_rd_insert,
      Q => req_periodic_rd_r(0),
      R => '0'
    );
req_priority_r_reg: unisim.vcomponents.FDRE
     port map (
      C => \req_col_r_reg[9]_1\,
      CE => E(0),
      D => hi_priority,
      Q => req_priority_r,
      R => '0'
    );
\req_row_r_lcl_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \req_col_r_reg[9]_1\,
      CE => E(0),
      D => \req_row_r_lcl_reg[13]_1\(0),
      Q => \^req_row_r_lcl_reg[13]_0\(0),
      R => '0'
    );
\req_row_r_lcl_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => \req_col_r_reg[9]_1\,
      CE => E(0),
      D => \req_row_r_lcl_reg[13]_1\(10),
      Q => \^req_row_r_lcl_reg[13]_0\(10),
      R => '0'
    );
\req_row_r_lcl_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => \req_col_r_reg[9]_1\,
      CE => E(0),
      D => \req_row_r_lcl_reg[13]_1\(11),
      Q => \^req_row_r_lcl_reg[13]_0\(11),
      R => '0'
    );
\req_row_r_lcl_reg[12]\: unisim.vcomponents.FDRE
     port map (
      C => \req_col_r_reg[9]_1\,
      CE => E(0),
      D => \req_row_r_lcl_reg[13]_1\(12),
      Q => \^req_row_r_lcl_reg[13]_0\(12),
      R => '0'
    );
\req_row_r_lcl_reg[13]\: unisim.vcomponents.FDRE
     port map (
      C => \req_col_r_reg[9]_1\,
      CE => E(0),
      D => \req_row_r_lcl_reg[13]_1\(13),
      Q => \^req_row_r_lcl_reg[13]_0\(13),
      R => '0'
    );
\req_row_r_lcl_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \req_col_r_reg[9]_1\,
      CE => E(0),
      D => \req_row_r_lcl_reg[13]_1\(1),
      Q => \^req_row_r_lcl_reg[13]_0\(1),
      R => '0'
    );
\req_row_r_lcl_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \req_col_r_reg[9]_1\,
      CE => E(0),
      D => \req_row_r_lcl_reg[13]_1\(2),
      Q => \^req_row_r_lcl_reg[13]_0\(2),
      R => '0'
    );
\req_row_r_lcl_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => \req_col_r_reg[9]_1\,
      CE => E(0),
      D => \req_row_r_lcl_reg[13]_1\(3),
      Q => \^req_row_r_lcl_reg[13]_0\(3),
      R => '0'
    );
\req_row_r_lcl_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => \req_col_r_reg[9]_1\,
      CE => E(0),
      D => \req_row_r_lcl_reg[13]_1\(4),
      Q => \^req_row_r_lcl_reg[13]_0\(4),
      R => '0'
    );
\req_row_r_lcl_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => \req_col_r_reg[9]_1\,
      CE => E(0),
      D => \req_row_r_lcl_reg[13]_1\(5),
      Q => \^req_row_r_lcl_reg[13]_0\(5),
      R => '0'
    );
\req_row_r_lcl_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => \req_col_r_reg[9]_1\,
      CE => E(0),
      D => \req_row_r_lcl_reg[13]_1\(6),
      Q => \^req_row_r_lcl_reg[13]_0\(6),
      R => '0'
    );
\req_row_r_lcl_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => \req_col_r_reg[9]_1\,
      CE => E(0),
      D => \req_row_r_lcl_reg[13]_1\(7),
      Q => \^req_row_r_lcl_reg[13]_0\(7),
      R => '0'
    );
\req_row_r_lcl_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => \req_col_r_reg[9]_1\,
      CE => E(0),
      D => \req_row_r_lcl_reg[13]_1\(8),
      Q => \^req_row_r_lcl_reg[13]_0\(8),
      R => '0'
    );
\req_row_r_lcl_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => \req_col_r_reg[9]_1\,
      CE => E(0),
      D => \req_row_r_lcl_reg[13]_1\(9),
      Q => \^req_row_r_lcl_reg[13]_0\(9),
      R => '0'
    );
req_wr_r_lcl_reg: unisim.vcomponents.FDRE
     port map (
      C => \req_col_r_reg[9]_1\,
      CE => E(0),
      D => req_wr_r_lcl0,
      Q => \^req_wr_r\(0),
      R => '0'
    );
row_hit_ns_carry: unisim.vcomponents.CARRY4
     port map (
      CI => '0',
      CO(3) => row_hit_ns_carry_n_0,
      CO(2) => row_hit_ns_carry_n_1,
      CO(1) => row_hit_ns_carry_n_2,
      CO(0) => row_hit_ns_carry_n_3,
      CYINIT => '1',
      DI(3 downto 0) => B"0000",
      O(3 downto 0) => NLW_row_hit_ns_carry_O_UNCONNECTED(3 downto 0),
      S(3) => row_hit_ns_carry_i_1_n_0,
      S(2 downto 0) => S(2 downto 0)
    );
\row_hit_ns_carry__0\: unisim.vcomponents.CARRY4
     port map (
      CI => row_hit_ns_carry_n_0,
      CO(3 downto 1) => \NLW_row_hit_ns_carry__0_CO_UNCONNECTED\(3 downto 1),
      CO(0) => row_hit_ns,
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3 downto 0) => \NLW_row_hit_ns_carry__0_O_UNCONNECTED\(3 downto 0),
      S(3 downto 1) => B"000",
      S(0) => row_hit_r_reg_1(0)
    );
row_hit_ns_carry_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"9009000000009009"
    )
        port map (
      I0 => \^req_row_r_lcl_reg[13]_0\(11),
      I1 => \req_row_r_lcl_reg[13]_1\(11),
      I2 => \^req_row_r_lcl_reg[13]_0\(9),
      I3 => \req_row_r_lcl_reg[13]_1\(9),
      I4 => \req_row_r_lcl_reg[13]_1\(10),
      I5 => \^req_row_r_lcl_reg[13]_0\(10),
      O => row_hit_ns_carry_i_1_n_0
    );
row_hit_r_reg: unisim.vcomponents.FDRE
     port map (
      C => \req_col_r_reg[9]_1\,
      CE => '1',
      D => row_hit_ns,
      Q => row_hit_r,
      R => '0'
    );
\wr_this_rank_r[0]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \^rd_wr_r_lcl_reg_0\,
      O => start_wtp_timer0
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mig_mig_7series_v4_2_bank_queue is
  port (
    idle_r_lcl_reg_0 : out STD_LOGIC;
    E : out STD_LOGIC_VECTOR ( 0 to 0 );
    pass_open_bank_r : out STD_LOGIC;
    pass_open_bank_ns : out STD_LOGIC;
    q_has_rd : out STD_LOGIC;
    q_has_priority : out STD_LOGIC;
    pass_open_bank_r_lcl_reg_0 : out STD_LOGIC;
    wait_for_maint_r : out STD_LOGIC;
    tail_r : out STD_LOGIC;
    head_r_lcl_reg_0 : out STD_LOGIC;
    ordered_r_lcl : out STD_LOGIC;
    auto_pre_r_lcl_reg_0 : out STD_LOGIC;
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[1]_0\ : out STD_LOGIC;
    idle_r_lcl_reg_1 : out STD_LOGIC;
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_0\ : out STD_LOGIC;
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_0\ : out STD_LOGIC;
    rd_wr_r_lcl_reg : out STD_LOGIC;
    D : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_1\ : out STD_LOGIC;
    idle_r_lcl_reg_2 : out STD_LOGIC;
    pre_bm_end_r_reg_0 : out STD_LOGIC;
    idle_r_lcl_reg_3 : out STD_LOGIC;
    idle_r_lcl_reg_4 : out STD_LOGIC;
    q_entry_ns : out STD_LOGIC_VECTOR ( 0 to 0 );
    p_9_in : out STD_LOGIC;
    idle_r_lcl_reg_5 : out STD_LOGIC;
    idle_r_lcl_reg_6 : out STD_LOGIC;
    \q_entry_r_reg[0]_0\ : out STD_LOGIC;
    \q_entry_r_reg[0]_1\ : out STD_LOGIC;
    \q_entry_r_reg[1]_0\ : out STD_LOGIC;
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_1\ : out STD_LOGIC;
    idle_r_lcl_reg_7 : out STD_LOGIC;
    ordered_r_lcl_reg_0 : out STD_LOGIC;
    \order_q_r_reg[0]_0\ : out STD_LOGIC;
    req_bank_rdy_ns : out STD_LOGIC;
    p_145_out : out STD_LOGIC;
    pre_passing_open_bank_r_reg_0 : out STD_LOGIC;
    idle_r_lcl_reg_8 : out STD_LOGIC;
    act_wait_r_lcl_reg : out STD_LOGIC;
    \compute_tail.tail_r_lcl_reg_0\ : out STD_LOGIC;
    idle_r_lcl_reg_9 : out STD_LOGIC;
    q_has_rd_r_reg_0 : in STD_LOGIC;
    pre_bm_end_ns : in STD_LOGIC;
    pre_passing_open_bank_ns : in STD_LOGIC;
    q_has_rd_r_reg_1 : in STD_LOGIC;
    q_has_priority_r_reg_0 : in STD_LOGIC;
    wait_for_maint_r_lcl_reg_0 : in STD_LOGIC;
    wait_for_maint_r_lcl_reg_1 : in STD_LOGIC;
    head_r_lcl_reg_1 : in STD_LOGIC;
    \compute_tail.tail_r_lcl_reg_1\ : in STD_LOGIC;
    head_r_lcl_reg_2 : in STD_LOGIC;
    ordered_r_lcl_reg_1 : in STD_LOGIC;
    auto_pre_r_lcl_reg_1 : in STD_LOGIC;
    accept_internal_r_reg : in STD_LOGIC;
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[1]_1\ : in STD_LOGIC;
    accept_internal_r_reg_0 : in STD_LOGIC;
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_2\ : in STD_LOGIC;
    accept_internal_r_reg_1 : in STD_LOGIC;
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_2\ : in STD_LOGIC;
    granted_col_r_reg : in STD_LOGIC;
    granted_col_r_reg_0 : in STD_LOGIC;
    bm_end_r1_reg : in STD_LOGIC;
    granted_col_r_reg_1 : in STD_LOGIC;
    granted_col_r_reg_2 : in STD_LOGIC;
    \ras_timer_r_reg[0]\ : in STD_LOGIC;
    \ras_timer_r_reg[1]\ : in STD_LOGIC;
    \ras_timer_r_reg[0]_0\ : in STD_LOGIC;
    \ras_timer_r_reg[0]_1\ : in STD_LOGIC;
    \ras_timer_r_reg[0]_2\ : in STD_LOGIC;
    \ras_timer_r_reg[0]_3\ : in STD_LOGIC;
    \q_entry_r_reg[1]_1\ : in STD_LOGIC;
    \q_entry_r_reg[1]_2\ : in STD_LOGIC;
    \q_entry_r_reg[1]_3\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \q_entry_r_reg[1]_4\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \q_entry_r_reg[1]_5\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \q_entry_r_reg[1]_6\ : in STD_LOGIC;
    \q_entry_r_reg[1]_7\ : in STD_LOGIC;
    \q_entry_r_reg[1]_8\ : in STD_LOGIC;
    accept_internal_r_reg_2 : in STD_LOGIC;
    head_r_lcl_reg_3 : in STD_LOGIC;
    \q_entry_r_reg[1]_9\ : in STD_LOGIC;
    \q_entry_r_reg[1]_10\ : in STD_LOGIC;
    \q_entry_r_reg[0]_2\ : in STD_LOGIC;
    \q_entry_r_reg[0]_3\ : in STD_LOGIC;
    \q_entry_r_reg[0]_4\ : in STD_LOGIC;
    \q_entry_r_reg[0]_5\ : in STD_LOGIC;
    \q_entry_r_reg[0]_6\ : in STD_LOGIC;
    \i___3_i_4\ : in STD_LOGIC;
    \order_q_r_reg[0]_1\ : in STD_LOGIC;
    \order_q_r_reg[0]_2\ : in STD_LOGIC;
    \order_q_r_reg[0]_3\ : in STD_LOGIC;
    req_bank_rdy_r_reg : in STD_LOGIC;
    req_priority_r : in STD_LOGIC;
    req_bank_rdy_r_reg_0 : in STD_LOGIC;
    \grant_r[2]_i_3_0\ : in STD_LOGIC;
    \grant_r[2]_i_3_1\ : in STD_LOGIC;
    \grant_r[2]_i_3_2\ : in STD_LOGIC;
    \grant_r[2]_i_3_3\ : in STD_LOGIC;
    rb_hit_busy_r_reg : in STD_LOGIC;
    use_addr : in STD_LOGIC;
    accept_internal_r_reg_3 : in STD_LOGIC;
    accept_internal_r_reg_4 : in STD_LOGIC;
    req_wr_r : in STD_LOGIC_VECTOR ( 0 to 0 );
    Q : in STD_LOGIC_VECTOR ( 0 to 0 );
    pass_open_bank_r_lcl_reg_1 : in STD_LOGIC;
    pre_wait_r : in STD_LOGIC;
    pass_open_bank_r_lcl_reg_2 : in STD_LOGIC;
    q_has_priority_r_reg_1 : in STD_LOGIC;
    \i___70\ : in STD_LOGIC;
    ras_timer_zero_r : in STD_LOGIC;
    auto_pre_r_lcl_reg_2 : in STD_LOGIC;
    \ras_timer_r_reg[0]_4\ : in STD_LOGIC;
    \ras_timer_r_reg[0]_5\ : in STD_LOGIC;
    \ras_timer_r_reg[0]_6\ : in STD_LOGIC;
    \ras_timer_r_reg[1]_0\ : in STD_LOGIC;
    \ras_timer_r_reg[1]_1\ : in STD_LOGIC;
    \ras_timer_r_reg[1]_2\ : in STD_LOGIC;
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_3\ : in STD_LOGIC;
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_3\ : in STD_LOGIC;
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[1]_2\ : in STD_LOGIC;
    \q_entry_r_reg[0]_7\ : in STD_LOGIC;
    \order_q_r_reg[1]_0\ : in STD_LOGIC;
    \order_q_r_reg[0]_4\ : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of mig_mig_7series_v4_2_bank_queue : entity is "mig_7series_v4_2_bank_queue";
end mig_mig_7series_v4_2_bank_queue;

architecture STRUCTURE of mig_mig_7series_v4_2_bank_queue is
  signal \^e\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \grant_r[2]_i_5_n_0\ : STD_LOGIC;
  signal \^head_r_lcl_reg_0\ : STD_LOGIC;
  signal \^idle_r_lcl_reg_0\ : STD_LOGIC;
  signal \^idle_r_lcl_reg_1\ : STD_LOGIC;
  signal \^idle_r_lcl_reg_7\ : STD_LOGIC;
  signal order_q_r : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \order_q_r[0]_i_1_n_0\ : STD_LOGIC;
  signal \order_q_r[1]_i_1_n_0\ : STD_LOGIC;
  signal \^ordered_r_lcl\ : STD_LOGIC;
  signal \^ordered_r_lcl_reg_0\ : STD_LOGIC;
  signal \^pass_open_bank_ns\ : STD_LOGIC;
  signal \^pass_open_bank_r\ : STD_LOGIC;
  signal \^pass_open_bank_r_lcl_reg_0\ : STD_LOGIC;
  signal pre_bm_end_r : STD_LOGIC;
  signal \^pre_bm_end_r_reg_0\ : STD_LOGIC;
  signal pre_passing_open_bank_r : STD_LOGIC;
  signal \q_entry_r[0]_i_1_n_0\ : STD_LOGIC;
  signal \q_entry_r[0]_i_3__0_n_0\ : STD_LOGIC;
  signal \q_entry_r[1]_i_1_n_0\ : STD_LOGIC;
  signal \q_entry_r[1]_i_2__2_n_0\ : STD_LOGIC;
  signal \q_entry_r[1]_i_3__2_n_0\ : STD_LOGIC;
  signal \q_entry_r[1]_i_4__1_n_0\ : STD_LOGIC;
  signal \q_entry_r[1]_i_5_n_0\ : STD_LOGIC;
  signal \^q_entry_r_reg[0]_1\ : STD_LOGIC;
  signal \^q_entry_r_reg[1]_0\ : STD_LOGIC;
  signal \^q_has_priority\ : STD_LOGIC;
  signal \ras_timer_r[0]_i_2__2_n_0\ : STD_LOGIC;
  signal \ras_timer_r[1]_i_2__2_n_0\ : STD_LOGIC;
  signal \rb_hit_busies.rb_hit_busies_r_lcl[1]_i_1_n_0\ : STD_LOGIC;
  signal \rb_hit_busies.rb_hit_busies_r_lcl[2]_i_2_n_0\ : STD_LOGIC;
  signal \rb_hit_busies.rb_hit_busies_r_lcl[3]_i_1__0_n_0\ : STD_LOGIC;
  signal \^rb_hit_busies.rb_hit_busies_r_lcl_reg[1]_0\ : STD_LOGIC;
  signal \^rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_0\ : STD_LOGIC;
  signal \^rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_1\ : STD_LOGIC;
  signal \^rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_0\ : STD_LOGIC;
  signal \^rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_1\ : STD_LOGIC;
  signal \^tail_r\ : STD_LOGIC;
  signal \^wait_for_maint_r\ : STD_LOGIC;
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of accept_internal_r_i_1 : label is "soft_lutpair1153";
  attribute SOFT_HLUTNM of \i___3_i_1\ : label is "soft_lutpair1154";
  attribute SOFT_HLUTNM of \idle_r_lcl_i_1__2\ : label is "soft_lutpair1153";
  attribute SOFT_HLUTNM of \q_entry_r[0]_i_3__1\ : label is "soft_lutpair1155";
  attribute SOFT_HLUTNM of \q_entry_r[1]_i_2__1\ : label is "soft_lutpair1156";
  attribute SOFT_HLUTNM of \q_entry_r[1]_i_4\ : label is "soft_lutpair1156";
  attribute SOFT_HLUTNM of \q_entry_r[1]_i_4__1\ : label is "soft_lutpair1154";
  attribute SOFT_HLUTNM of \q_entry_r[1]_i_5\ : label is "soft_lutpair1155";
  attribute SOFT_HLUTNM of \ras_timer_r[0]_i_1__0\ : label is "soft_lutpair1158";
  attribute SOFT_HLUTNM of \ras_timer_r[1]_i_1__0\ : label is "soft_lutpair1158";
  attribute SOFT_HLUTNM of \rb_hit_busies.rb_hit_busies_r_lcl[3]_i_1__0\ : label is "soft_lutpair1157";
  attribute SOFT_HLUTNM of \rb_hit_busy_r_i_1__2\ : label is "soft_lutpair1157";
begin
  E(0) <= \^e\(0);
  head_r_lcl_reg_0 <= \^head_r_lcl_reg_0\;
  idle_r_lcl_reg_0 <= \^idle_r_lcl_reg_0\;
  idle_r_lcl_reg_1 <= \^idle_r_lcl_reg_1\;
  idle_r_lcl_reg_7 <= \^idle_r_lcl_reg_7\;
  ordered_r_lcl <= \^ordered_r_lcl\;
  ordered_r_lcl_reg_0 <= \^ordered_r_lcl_reg_0\;
  pass_open_bank_ns <= \^pass_open_bank_ns\;
  pass_open_bank_r <= \^pass_open_bank_r\;
  pass_open_bank_r_lcl_reg_0 <= \^pass_open_bank_r_lcl_reg_0\;
  pre_bm_end_r_reg_0 <= \^pre_bm_end_r_reg_0\;
  \q_entry_r_reg[0]_1\ <= \^q_entry_r_reg[0]_1\;
  \q_entry_r_reg[1]_0\ <= \^q_entry_r_reg[1]_0\;
  q_has_priority <= \^q_has_priority\;
  \rb_hit_busies.rb_hit_busies_r_lcl_reg[1]_0\ <= \^rb_hit_busies.rb_hit_busies_r_lcl_reg[1]_0\;
  \rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_0\ <= \^rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_0\;
  \rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_1\ <= \^rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_1\;
  \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_0\ <= \^rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_0\;
  \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_1\ <= \^rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_1\;
  tail_r <= \^tail_r\;
  wait_for_maint_r <= \^wait_for_maint_r\;
accept_internal_r_i_1: unisim.vcomponents.LUT5
    generic map(
      INIT => X"2AAAAAAA"
    )
        port map (
      I0 => accept_internal_r_reg_2,
      I1 => \^idle_r_lcl_reg_1\,
      I2 => accept_internal_r_reg,
      I3 => accept_internal_r_reg_0,
      I4 => accept_internal_r_reg_1,
      O => p_9_in
    );
auto_pre_r_lcl_reg: unisim.vcomponents.FDRE
     port map (
      C => q_has_rd_r_reg_0,
      CE => '1',
      D => auto_pre_r_lcl_reg_1,
      Q => auto_pre_r_lcl_reg_0,
      R => \^pass_open_bank_r_lcl_reg_0\
    );
\bm_end_r1_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"BFAAAAAA"
    )
        port map (
      I0 => pre_bm_end_r,
      I1 => bm_end_r1_reg,
      I2 => req_wr_r(0),
      I3 => Q(0),
      I4 => \^pass_open_bank_r\,
      O => \^pre_bm_end_r_reg_0\
    );
\compute_tail.tail_r_lcl_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '1'
    )
        port map (
      C => q_has_rd_r_reg_0,
      CE => '1',
      D => \compute_tail.tail_r_lcl_reg_1\,
      Q => \^tail_r\,
      R => head_r_lcl_reg_1
    );
\demand_priority_r_i_2__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"F2F2F2FF"
    )
        port map (
      I0 => order_q_r(0),
      I1 => req_bank_rdy_r_reg,
      I2 => order_q_r(1),
      I3 => \^q_has_priority\,
      I4 => req_priority_r,
      O => \order_q_r_reg[0]_0\
    );
\grant_r[2]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFBAFFFFFFBF"
    )
        port map (
      I0 => granted_col_r_reg,
      I1 => granted_col_r_reg_0,
      I2 => bm_end_r1_reg,
      I3 => granted_col_r_reg_1,
      I4 => \grant_r[2]_i_5_n_0\,
      I5 => granted_col_r_reg_2,
      O => rd_wr_r_lcl_reg
    );
\grant_r[2]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"EAAAAAAAAAAAAAAA"
    )
        port map (
      I0 => order_q_r(1),
      I1 => \grant_r[2]_i_3_0\,
      I2 => \grant_r[2]_i_3_1\,
      I3 => \grant_r[2]_i_3_2\,
      I4 => \grant_r[2]_i_3_3\,
      I5 => order_q_r(0),
      O => \grant_r[2]_i_5_n_0\
    );
head_r_lcl_reg: unisim.vcomponents.FDSE
     port map (
      C => q_has_rd_r_reg_0,
      CE => '1',
      D => head_r_lcl_reg_2,
      Q => \^head_r_lcl_reg_0\,
      S => head_r_lcl_reg_1
    );
\i___26_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000F4F4FFF4"
    )
        port map (
      I0 => \ras_timer_r_reg[0]_0\,
      I1 => \^rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_0\,
      I2 => \ras_timer_r_reg[0]_1\,
      I3 => \^rb_hit_busies.rb_hit_busies_r_lcl_reg[1]_0\,
      I4 => \ras_timer_r_reg[0]_2\,
      I5 => \ras_timer_r_reg[0]_3\,
      O => \^rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_1\
    );
\i___29_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"40555555"
    )
        port map (
      I0 => pre_passing_open_bank_r,
      I1 => bm_end_r1_reg,
      I2 => req_wr_r(0),
      I3 => Q(0),
      I4 => \^pass_open_bank_r\,
      O => pre_passing_open_bank_r_reg_0
    );
\i___3_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"01168001"
    )
        port map (
      I0 => \^idle_r_lcl_reg_0\,
      I1 => \q_entry_r_reg[1]_3\(0),
      I2 => \q_entry_r_reg[1]_4\(0),
      I3 => \q_entry_r_reg[1]_5\(0),
      I4 => \q_entry_r_reg[1]_7\,
      O => idle_r_lcl_reg_9
    );
\i___3_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"20202020202F2F20"
    )
        port map (
      I0 => \^q_entry_r_reg[0]_1\,
      I1 => \^q_entry_r_reg[1]_0\,
      I2 => head_r_lcl_reg_3,
      I3 => \q_entry_r_reg[1]_9\,
      I4 => \^rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_1\,
      I5 => \q_entry_r_reg[1]_10\,
      O => \q_entry_r_reg[0]_0\
    );
\i___3_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFAFBFB"
    )
        port map (
      I0 => \^pre_bm_end_r_reg_0\,
      I1 => \^rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_1\,
      I2 => \q_entry_r_reg[0]_2\,
      I3 => \q_entry_r_reg[1]_7\,
      I4 => \^idle_r_lcl_reg_0\,
      O => \^idle_r_lcl_reg_7\
    );
\i___3_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0DDD0DDD00000DDD"
    )
        port map (
      I0 => \^rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_0\,
      I1 => \i___3_i_4\,
      I2 => \^rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_0\,
      I3 => \q_entry_r_reg[1]_2\,
      I4 => \^rb_hit_busies.rb_hit_busies_r_lcl_reg[1]_0\,
      I5 => \q_entry_r_reg[1]_1\,
      O => \^rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_1\
    );
\i___48_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000FD555555"
    )
        port map (
      I0 => \^idle_r_lcl_reg_0\,
      I1 => use_addr,
      I2 => accept_internal_r_reg_3,
      I3 => \^head_r_lcl_reg_0\,
      I4 => accept_internal_r_reg_4,
      I5 => \^pass_open_bank_r_lcl_reg_0\,
      O => \^idle_r_lcl_reg_1\
    );
\i___61_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"777F7F7F"
    )
        port map (
      I0 => \^tail_r\,
      I1 => \q_entry_r_reg[0]_6\,
      I2 => accept_internal_r_reg_3,
      I3 => auto_pre_r_lcl_reg_2,
      I4 => use_addr,
      O => \compute_tail.tail_r_lcl_reg_0\
    );
\i___70_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFDFFFFF"
    )
        port map (
      I0 => \i___70\,
      I1 => \^idle_r_lcl_reg_0\,
      I2 => \^head_r_lcl_reg_0\,
      I3 => \^wait_for_maint_r\,
      I4 => ras_timer_zero_r,
      O => act_wait_r_lcl_reg
    );
\idle_r_lcl_i_1__2\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \^idle_r_lcl_reg_1\,
      O => \^e\(0)
    );
idle_r_lcl_reg: unisim.vcomponents.FDRE
     port map (
      C => q_has_rd_r_reg_0,
      CE => '1',
      D => \^e\(0),
      Q => \^idle_r_lcl_reg_0\,
      R => '0'
    );
\order_q_r[0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0D550C000D550CF0"
    )
        port map (
      I0 => \^ordered_r_lcl_reg_0\,
      I1 => order_q_r(1),
      I2 => order_q_r(0),
      I3 => req_bank_rdy_r_reg,
      I4 => \q_entry_r_reg[0]_2\,
      I5 => \order_q_r_reg[0]_4\,
      O => \order_q_r[0]_i_1_n_0\
    );
\order_q_r[0]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"69969669"
    )
        port map (
      I0 => \^ordered_r_lcl\,
      I1 => \order_q_r_reg[0]_1\,
      I2 => \order_q_r_reg[0]_2\,
      I3 => \order_q_r_reg[0]_3\,
      I4 => req_bank_rdy_r_reg,
      O => \^ordered_r_lcl_reg_0\
    );
\order_q_r[1]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"C2AAC000C2AAC0CC"
    )
        port map (
      I0 => \order_q_r_reg[1]_0\,
      I1 => order_q_r(1),
      I2 => order_q_r(0),
      I3 => req_bank_rdy_r_reg,
      I4 => \q_entry_r_reg[0]_2\,
      I5 => \order_q_r_reg[0]_4\,
      O => \order_q_r[1]_i_1_n_0\
    );
\order_q_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => q_has_rd_r_reg_0,
      CE => '1',
      D => \order_q_r[0]_i_1_n_0\,
      Q => order_q_r(0),
      R => '0'
    );
\order_q_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => q_has_rd_r_reg_0,
      CE => '1',
      D => \order_q_r[1]_i_1_n_0\,
      Q => order_q_r(1),
      R => '0'
    );
ordered_r_lcl_reg: unisim.vcomponents.FDRE
     port map (
      C => q_has_rd_r_reg_0,
      CE => '1',
      D => ordered_r_lcl_reg_1,
      Q => \^ordered_r_lcl\,
      R => '0'
    );
\pass_open_bank_r_lcl_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"4444544444444444"
    )
        port map (
      I0 => \^pass_open_bank_r_lcl_reg_0\,
      I1 => \^pass_open_bank_r\,
      I2 => \^tail_r\,
      I3 => pass_open_bank_r_lcl_reg_1,
      I4 => pre_wait_r,
      I5 => pass_open_bank_r_lcl_reg_2,
      O => \^pass_open_bank_ns\
    );
pass_open_bank_r_lcl_reg: unisim.vcomponents.FDRE
     port map (
      C => q_has_rd_r_reg_0,
      CE => '1',
      D => \^pass_open_bank_ns\,
      Q => \^pass_open_bank_r\,
      R => '0'
    );
pre_bm_end_r_reg: unisim.vcomponents.FDRE
     port map (
      C => q_has_rd_r_reg_0,
      CE => '1',
      D => pre_bm_end_ns,
      Q => pre_bm_end_r,
      R => '0'
    );
pre_passing_open_bank_r_reg: unisim.vcomponents.FDRE
     port map (
      C => q_has_rd_r_reg_0,
      CE => '1',
      D => pre_passing_open_bank_ns,
      Q => pre_passing_open_bank_r,
      R => '0'
    );
\q_entry_r[0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"88B8FFFF8BBB0000"
    )
        port map (
      I0 => \q_entry_r_reg[0]_7\,
      I1 => \^pre_bm_end_r_reg_0\,
      I2 => \q_entry_r_reg[0]_2\,
      I3 => \q_entry_r[0]_i_3__0_n_0\,
      I4 => \^idle_r_lcl_reg_7\,
      I5 => \^q_entry_r_reg[0]_1\,
      O => \q_entry_r[0]_i_1_n_0\
    );
\q_entry_r[0]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6996"
    )
        port map (
      I0 => \q_entry_r[1]_i_5_n_0\,
      I1 => \^pre_bm_end_r_reg_0\,
      I2 => \q_entry_r_reg[1]_1\,
      I3 => \q_entry_r_reg[1]_2\,
      O => idle_r_lcl_reg_5
    );
\q_entry_r[0]_i_3__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"96696996"
    )
        port map (
      I0 => \^rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_1\,
      I1 => \q_entry_r_reg[0]_3\,
      I2 => \q_entry_r_reg[0]_4\,
      I3 => \q_entry_r_reg[0]_5\,
      I4 => \q_entry_r_reg[0]_6\,
      O => \q_entry_r[0]_i_3__0_n_0\
    );
\q_entry_r[0]_i_3__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"96696996"
    )
        port map (
      I0 => \^pre_bm_end_r_reg_0\,
      I1 => \q_entry_r_reg[1]_5\(0),
      I2 => \q_entry_r_reg[1]_4\(0),
      I3 => \q_entry_r_reg[1]_3\(0),
      I4 => \^idle_r_lcl_reg_0\,
      O => idle_r_lcl_reg_8
    );
\q_entry_r[1]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"F1FFF100"
    )
        port map (
      I0 => \q_entry_r[1]_i_2__2_n_0\,
      I1 => \^pre_bm_end_r_reg_0\,
      I2 => \q_entry_r[1]_i_3__2_n_0\,
      I3 => \^idle_r_lcl_reg_7\,
      I4 => \^q_entry_r_reg[1]_0\,
      O => \q_entry_r[1]_i_1_n_0\
    );
\q_entry_r[1]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"7EE8E881177E7EE8"
    )
        port map (
      I0 => \^idle_r_lcl_reg_0\,
      I1 => \q_entry_r_reg[1]_3\(0),
      I2 => \q_entry_r_reg[1]_4\(0),
      I3 => \q_entry_r_reg[1]_5\(0),
      I4 => \^pre_bm_end_r_reg_0\,
      I5 => \q_entry_r_reg[1]_1\,
      O => idle_r_lcl_reg_3
    );
\q_entry_r[1]_i_2__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"E2D1F3C0F3C0D1E2"
    )
        port map (
      I0 => \q_entry_r_reg[1]_7\,
      I1 => \q_entry_r_reg[1]_1\,
      I2 => \q_entry_r_reg[1]_8\,
      I3 => \q_entry_r[1]_i_4__1_n_0\,
      I4 => \q_entry_r[1]_i_5_n_0\,
      I5 => \^pre_bm_end_r_reg_0\,
      O => q_entry_ns(0)
    );
\q_entry_r[1]_i_2__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"65A6A69A"
    )
        port map (
      I0 => \q_entry_r[1]_i_4__1_n_0\,
      I1 => \q_entry_r_reg[1]_2\,
      I2 => \q_entry_r_reg[1]_1\,
      I3 => \^pre_bm_end_r_reg_0\,
      I4 => \q_entry_r[1]_i_5_n_0\,
      O => idle_r_lcl_reg_6
    );
\q_entry_r[1]_i_2__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"560056FF56FF5600"
    )
        port map (
      I0 => \q_entry_r_reg[1]_10\,
      I1 => \q_entry_r_reg[1]_9\,
      I2 => \^rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_1\,
      I3 => \q_entry_r_reg[0]_2\,
      I4 => \^q_entry_r_reg[1]_0\,
      I5 => \^q_entry_r_reg[0]_1\,
      O => \q_entry_r[1]_i_2__2_n_0\
    );
\q_entry_r[1]_i_3__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"599A599A0000FFFF"
    )
        port map (
      I0 => \q_entry_r[1]_i_4__1_n_0\,
      I1 => \q_entry_r_reg[1]_1\,
      I2 => \q_entry_r[1]_i_5_n_0\,
      I3 => \^pre_bm_end_r_reg_0\,
      I4 => \q_entry_r_reg[1]_6\,
      I5 => \q_entry_r_reg[1]_2\,
      O => idle_r_lcl_reg_4
    );
\q_entry_r[1]_i_3__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"BDD4D44200000000"
    )
        port map (
      I0 => \q_entry_r_reg[1]_7\,
      I1 => \q_entry_r_reg[1]_3\(0),
      I2 => \q_entry_r_reg[1]_4\(0),
      I3 => \q_entry_r_reg[1]_5\(0),
      I4 => \^idle_r_lcl_reg_0\,
      I5 => \^pre_bm_end_r_reg_0\,
      O => \q_entry_r[1]_i_3__2_n_0\
    );
\q_entry_r[1]_i_4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"E78E1871"
    )
        port map (
      I0 => \q_entry_r[1]_i_5_n_0\,
      I1 => \^pre_bm_end_r_reg_0\,
      I2 => \q_entry_r_reg[1]_1\,
      I3 => \q_entry_r_reg[1]_2\,
      I4 => \q_entry_r[1]_i_4__1_n_0\,
      O => idle_r_lcl_reg_2
    );
\q_entry_r[1]_i_4__1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7EE8"
    )
        port map (
      I0 => \^idle_r_lcl_reg_0\,
      I1 => \q_entry_r_reg[1]_5\(0),
      I2 => \q_entry_r_reg[1]_4\(0),
      I3 => \q_entry_r_reg[1]_3\(0),
      O => \q_entry_r[1]_i_4__1_n_0\
    );
\q_entry_r[1]_i_5\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6996"
    )
        port map (
      I0 => \^idle_r_lcl_reg_0\,
      I1 => \q_entry_r_reg[1]_3\(0),
      I2 => \q_entry_r_reg[1]_4\(0),
      I3 => \q_entry_r_reg[1]_5\(0),
      O => \q_entry_r[1]_i_5_n_0\
    );
\q_entry_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => q_has_rd_r_reg_0,
      CE => '1',
      D => \q_entry_r[0]_i_1_n_0\,
      Q => \^q_entry_r_reg[0]_1\,
      R => head_r_lcl_reg_1
    );
\q_entry_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => q_has_rd_r_reg_0,
      CE => '1',
      D => \q_entry_r[1]_i_1_n_0\,
      Q => \^q_entry_r_reg[1]_0\,
      R => head_r_lcl_reg_1
    );
q_has_priority_r_reg: unisim.vcomponents.FDRE
     port map (
      C => q_has_rd_r_reg_0,
      CE => '1',
      D => q_has_priority_r_reg_0,
      Q => \^q_has_priority\,
      R => \^pass_open_bank_r_lcl_reg_0\
    );
q_has_rd_r_reg: unisim.vcomponents.FDRE
     port map (
      C => q_has_rd_r_reg_0,
      CE => '1',
      D => q_has_rd_r_reg_1,
      Q => q_has_rd,
      R => '0'
    );
\ras_timer_r[0]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \ras_timer_r[0]_i_2__2_n_0\,
      I1 => \^rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_1\,
      I2 => \ras_timer_r_reg[0]\,
      O => D(0)
    );
\ras_timer_r[0]_i_2__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"B8BBB888B888B888"
    )
        port map (
      I0 => \ras_timer_r_reg[0]_4\,
      I1 => \^rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_0\,
      I2 => \ras_timer_r_reg[0]_5\,
      I3 => \^rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_0\,
      I4 => \^rb_hit_busies.rb_hit_busies_r_lcl_reg[1]_0\,
      I5 => \ras_timer_r_reg[0]_6\,
      O => \ras_timer_r[0]_i_2__2_n_0\
    );
\ras_timer_r[1]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \ras_timer_r[1]_i_2__2_n_0\,
      I1 => \^rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_1\,
      I2 => \ras_timer_r_reg[1]\,
      O => D(1)
    );
\ras_timer_r[1]_i_2__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"B8BBB888B888B888"
    )
        port map (
      I0 => \ras_timer_r_reg[1]_0\,
      I1 => \^rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_0\,
      I2 => \ras_timer_r_reg[1]_1\,
      I3 => \^rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_0\,
      I4 => \^rb_hit_busies.rb_hit_busies_r_lcl_reg[1]_0\,
      I5 => \ras_timer_r_reg[1]_2\,
      O => \ras_timer_r[1]_i_2__2_n_0\
    );
\rb_hit_busies.rb_hit_busies_r_lcl[1]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F022"
    )
        port map (
      I0 => accept_internal_r_reg,
      I1 => \rb_hit_busies.rb_hit_busies_r_lcl_reg[1]_1\,
      I2 => \^rb_hit_busies.rb_hit_busies_r_lcl_reg[1]_0\,
      I3 => \^idle_r_lcl_reg_1\,
      O => \rb_hit_busies.rb_hit_busies_r_lcl[1]_i_1_n_0\
    );
\rb_hit_busies.rb_hit_busies_r_lcl[2]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F022"
    )
        port map (
      I0 => accept_internal_r_reg_1,
      I1 => \rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_2\,
      I2 => \^rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_0\,
      I3 => \^idle_r_lcl_reg_1\,
      O => \rb_hit_busies.rb_hit_busies_r_lcl[2]_i_2_n_0\
    );
\rb_hit_busies.rb_hit_busies_r_lcl[3]_i_1__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F022"
    )
        port map (
      I0 => accept_internal_r_reg_0,
      I1 => \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_2\,
      I2 => \^rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_0\,
      I3 => \^idle_r_lcl_reg_1\,
      O => \rb_hit_busies.rb_hit_busies_r_lcl[3]_i_1__0_n_0\
    );
\rb_hit_busies.rb_hit_busies_r_lcl[4]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFAAEAEAEA"
    )
        port map (
      I0 => q_has_priority_r_reg_1,
      I1 => \^pass_open_bank_r\,
      I2 => Q(0),
      I3 => req_wr_r(0),
      I4 => bm_end_r1_reg,
      I5 => pre_bm_end_r,
      O => \^pass_open_bank_r_lcl_reg_0\
    );
\rb_hit_busies.rb_hit_busies_r_lcl_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => q_has_rd_r_reg_0,
      CE => '1',
      D => \rb_hit_busies.rb_hit_busies_r_lcl[1]_i_1_n_0\,
      Q => \^rb_hit_busies.rb_hit_busies_r_lcl_reg[1]_0\,
      R => \rb_hit_busies.rb_hit_busies_r_lcl_reg[1]_2\
    );
\rb_hit_busies.rb_hit_busies_r_lcl_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => q_has_rd_r_reg_0,
      CE => '1',
      D => \rb_hit_busies.rb_hit_busies_r_lcl[2]_i_2_n_0\,
      Q => \^rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_0\,
      R => \rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_3\
    );
\rb_hit_busies.rb_hit_busies_r_lcl_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => q_has_rd_r_reg_0,
      CE => '1',
      D => \rb_hit_busies.rb_hit_busies_r_lcl[3]_i_1__0_n_0\,
      Q => \^rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_0\,
      R => \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_3\
    );
\rb_hit_busy_r_i_1__2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \^idle_r_lcl_reg_1\,
      I1 => rb_hit_busy_r_reg,
      O => p_145_out
    );
\req_bank_rdy_r_i_1__2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"00A2"
    )
        port map (
      I0 => req_bank_rdy_r_reg_0,
      I1 => order_q_r(0),
      I2 => req_bank_rdy_r_reg,
      I3 => order_q_r(1),
      O => req_bank_rdy_ns
    );
wait_for_maint_r_lcl_reg: unisim.vcomponents.FDRE
     port map (
      C => q_has_rd_r_reg_0,
      CE => '1',
      D => wait_for_maint_r_lcl_reg_1,
      Q => \^wait_for_maint_r\,
      R => wait_for_maint_r_lcl_reg_0
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \mig_mig_7series_v4_2_bank_queue__parameterized0\ is
  port (
    idle_r_lcl_reg_0 : out STD_LOGIC_VECTOR ( 0 to 0 );
    E : out STD_LOGIC_VECTOR ( 0 to 0 );
    pass_open_bank_r_lcl_reg_0 : out STD_LOGIC;
    pass_open_bank_ns : out STD_LOGIC;
    pre_bm_end_r : out STD_LOGIC;
    q_has_rd_3 : out STD_LOGIC;
    q_has_priority : out STD_LOGIC;
    wait_for_maint_r_13 : out STD_LOGIC;
    head_r_lcl_reg_0 : out STD_LOGIC;
    ordered_r_lcl_reg_0 : out STD_LOGIC;
    tail_r_16 : out STD_LOGIC;
    auto_pre_r_lcl_reg_0 : out STD_LOGIC;
    granted_col_ns : out STD_LOGIC;
    rd_wr_r_lcl_reg : out STD_LOGIC;
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_0\ : out STD_LOGIC;
    idle_r_lcl_reg_1 : out STD_LOGIC;
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_0\ : out STD_LOGIC;
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[5]\ : out STD_LOGIC;
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_0\ : out STD_LOGIC;
    pre_passing_open_bank_r_reg_0 : out STD_LOGIC;
    p_106_out : out STD_LOGIC;
    p_91_out : out STD_LOGIC;
    pre_bm_end_r_reg_0 : out STD_LOGIC;
    \order_q_r_reg[0]_0\ : out STD_LOGIC;
    req_bank_rdy_ns : out STD_LOGIC;
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_1\ : out STD_LOGIC;
    \q_entry_r_reg[0]_0\ : out STD_LOGIC;
    \q_entry_r_reg[0]_1\ : out STD_LOGIC;
    \q_entry_r_reg[1]_0\ : out STD_LOGIC;
    \q_entry_r_reg[1]_1\ : out STD_LOGIC;
    D : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_2\ : out STD_LOGIC;
    \compute_tail.tail_r_lcl_reg_0\ : out STD_LOGIC;
    act_wait_r_lcl_reg : out STD_LOGIC;
    \order_q_r_reg[1]_0\ : in STD_LOGIC;
    pre_bm_end_ns : in STD_LOGIC;
    pre_passing_open_bank_ns : in STD_LOGIC;
    q_has_rd_r_reg_0 : in STD_LOGIC;
    auto_pre_r_lcl_reg_1 : in STD_LOGIC;
    q_has_priority_r_reg_0 : in STD_LOGIC;
    wait_for_maint_r_lcl_reg_0 : in STD_LOGIC;
    wait_for_maint_r_lcl_reg_1 : in STD_LOGIC;
    head_r_lcl_reg_1 : in STD_LOGIC;
    head_r_lcl_reg_2 : in STD_LOGIC;
    ordered_r_lcl_reg_1 : in STD_LOGIC;
    \compute_tail.tail_r_lcl_reg_1\ : in STD_LOGIC;
    auto_pre_r_lcl_reg_2 : in STD_LOGIC;
    granted_col_r_reg : in STD_LOGIC;
    granted_col_r_reg_0 : in STD_LOGIC;
    granted_col_r_reg_1 : in STD_LOGIC;
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_1\ : in STD_LOGIC;
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_2\ : in STD_LOGIC;
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_3\ : in STD_LOGIC;
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_4\ : in STD_LOGIC;
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_0\ : in STD_LOGIC;
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_1\ : in STD_LOGIC;
    granted_col_r_reg_2 : in STD_LOGIC;
    bm_end_r1_reg : in STD_LOGIC;
    granted_col_r_reg_3 : in STD_LOGIC;
    granted_col_r_reg_4 : in STD_LOGIC;
    rb_hit_busies_r : in STD_LOGIC_VECTOR ( 0 to 0 );
    Q : in STD_LOGIC_VECTOR ( 0 to 0 );
    bm_end_r1_reg_0 : in STD_LOGIC;
    rb_hit_busies_r_0 : in STD_LOGIC_VECTOR ( 0 to 0 );
    rb_hit_busy_r_reg : in STD_LOGIC;
    use_addr : in STD_LOGIC;
    rb_hit_busy_r_reg_0 : in STD_LOGIC;
    rb_hit_busy_r_reg_1 : in STD_LOGIC;
    pass_open_bank_r_lcl_reg_1 : in STD_LOGIC;
    pre_wait_r : in STD_LOGIC;
    pass_open_bank_r_lcl_reg_2 : in STD_LOGIC;
    req_bank_rdy_r_reg : in STD_LOGIC;
    req_priority_r : in STD_LOGIC;
    \grant_r[3]_i_2_0\ : in STD_LOGIC;
    \grant_r[3]_i_2_1\ : in STD_LOGIC;
    \grant_r[3]_i_2_2\ : in STD_LOGIC;
    \grant_r[3]_i_2_3\ : in STD_LOGIC;
    req_bank_rdy_r_reg_0 : in STD_LOGIC;
    head_r_lcl_reg_3 : in STD_LOGIC;
    \order_q_r_reg[1]_1\ : in STD_LOGIC;
    head_r_lcl_reg_4 : in STD_LOGIC;
    head_r_lcl_reg_5 : in STD_LOGIC;
    \ras_timer_r_reg[0]\ : in STD_LOGIC;
    \ras_timer_r_reg[1]\ : in STD_LOGIC;
    \ras_timer_r_reg[0]_0\ : in STD_LOGIC;
    \ras_timer_r_reg[0]_1\ : in STD_LOGIC;
    \ras_timer_r_reg[0]_2\ : in STD_LOGIC;
    \grant_r[3]_i_2_4\ : in STD_LOGIC;
    \ras_timer_r_reg[0]_3\ : in STD_LOGIC;
    \i___34\ : in STD_LOGIC;
    \i___34_0\ : in STD_LOGIC;
    \i___34_1\ : in STD_LOGIC;
    \ras_timer_r_reg[1]_0\ : in STD_LOGIC;
    \ras_timer_r_reg[1]_1\ : in STD_LOGIC;
    \ras_timer_r_reg[1]_2\ : in STD_LOGIC;
    \ras_timer_r_reg[0]_4\ : in STD_LOGIC;
    \ras_timer_r_reg[0]_5\ : in STD_LOGIC;
    \ras_timer_r_reg[0]_6\ : in STD_LOGIC;
    auto_pre_r_lcl_reg_3 : in STD_LOGIC;
    auto_pre_r_lcl_reg_4 : in STD_LOGIC;
    \i___73\ : in STD_LOGIC;
    ras_timer_zero_r : in STD_LOGIC;
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_3\ : in STD_LOGIC;
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_5\ : in STD_LOGIC;
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_2\ : in STD_LOGIC;
    q_entry_ns : in STD_LOGIC_VECTOR ( 0 to 0 );
    \q_entry_r_reg[1]_2\ : in STD_LOGIC;
    \q_entry_r_reg[0]_2\ : in STD_LOGIC;
    \q_entry_r_reg[0]_3\ : in STD_LOGIC;
    \order_q_r_reg[1]_2\ : in STD_LOGIC;
    \order_q_r_reg[1]_3\ : in STD_LOGIC;
    \order_q_r_reg[0]_1\ : in STD_LOGIC;
    \order_q_r_reg[0]_2\ : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \mig_mig_7series_v4_2_bank_queue__parameterized0\ : entity is "mig_7series_v4_2_bank_queue";
end \mig_mig_7series_v4_2_bank_queue__parameterized0\;

architecture STRUCTURE of \mig_mig_7series_v4_2_bank_queue__parameterized0\ is
  signal \^e\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \grant_r[3]_i_6_n_0\ : STD_LOGIC;
  signal \grant_r[3]_i_8_n_0\ : STD_LOGIC;
  signal \^head_r_lcl_reg_0\ : STD_LOGIC;
  signal \^idle_r_lcl_reg_0\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \^idle_r_lcl_reg_1\ : STD_LOGIC;
  signal order_q_r : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \order_q_r[0]_i_1_n_0\ : STD_LOGIC;
  signal \order_q_r[1]_i_1_n_0\ : STD_LOGIC;
  signal \^pass_open_bank_ns\ : STD_LOGIC;
  signal \^pass_open_bank_r_lcl_reg_0\ : STD_LOGIC;
  signal \^pre_bm_end_r\ : STD_LOGIC;
  signal \^pre_bm_end_r_reg_0\ : STD_LOGIC;
  signal pre_passing_open_bank_r : STD_LOGIC;
  signal \q_entry_r[0]_i_1_n_0\ : STD_LOGIC;
  signal \q_entry_r[0]_i_2__1_n_0\ : STD_LOGIC;
  signal \q_entry_r[1]_i_1_n_0\ : STD_LOGIC;
  signal \^q_entry_r_reg[0]_0\ : STD_LOGIC;
  signal \^q_entry_r_reg[1]_0\ : STD_LOGIC;
  signal \^q_has_priority\ : STD_LOGIC;
  signal \ras_timer_r[0]_i_2__1_n_0\ : STD_LOGIC;
  signal \ras_timer_r[1]_i_2__1_n_0\ : STD_LOGIC;
  signal \rb_hit_busies.rb_hit_busies_r_lcl[2]_i_1__0_n_0\ : STD_LOGIC;
  signal \rb_hit_busies.rb_hit_busies_r_lcl[3]_i_1__1_n_0\ : STD_LOGIC;
  signal \rb_hit_busies.rb_hit_busies_r_lcl[4]_i_2_n_0\ : STD_LOGIC;
  signal \^rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_0\ : STD_LOGIC;
  signal \^rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_1\ : STD_LOGIC;
  signal \^rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_2\ : STD_LOGIC;
  signal \^rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_0\ : STD_LOGIC;
  signal rb_hit_busies_r_1 : STD_LOGIC_VECTOR ( 4 to 4 );
  signal \^rd_wr_r_lcl_reg\ : STD_LOGIC;
  signal \^tail_r_16\ : STD_LOGIC;
  signal \^wait_for_maint_r_13\ : STD_LOGIC;
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of bm_end_r1_i_1 : label is "soft_lutpair1165";
  attribute SOFT_HLUTNM of \i___4_i_2\ : label is "soft_lutpair1165";
  attribute SOFT_HLUTNM of idle_r_lcl_i_1 : label is "soft_lutpair1166";
  attribute SOFT_HLUTNM of \ras_timer_r[0]_i_1__2\ : label is "soft_lutpair1168";
  attribute SOFT_HLUTNM of \ras_timer_r[1]_i_1__2\ : label is "soft_lutpair1168";
  attribute SOFT_HLUTNM of \rb_hit_busies.rb_hit_busies_r_lcl[2]_i_1__0\ : label is "soft_lutpair1167";
  attribute SOFT_HLUTNM of \rb_hit_busies.rb_hit_busies_r_lcl[4]_i_2\ : label is "soft_lutpair1166";
  attribute SOFT_HLUTNM of rb_hit_busy_r_i_1 : label is "soft_lutpair1167";
begin
  E(0) <= \^e\(0);
  head_r_lcl_reg_0 <= \^head_r_lcl_reg_0\;
  idle_r_lcl_reg_0(0) <= \^idle_r_lcl_reg_0\(0);
  idle_r_lcl_reg_1 <= \^idle_r_lcl_reg_1\;
  pass_open_bank_ns <= \^pass_open_bank_ns\;
  pass_open_bank_r_lcl_reg_0 <= \^pass_open_bank_r_lcl_reg_0\;
  pre_bm_end_r <= \^pre_bm_end_r\;
  pre_bm_end_r_reg_0 <= \^pre_bm_end_r_reg_0\;
  \q_entry_r_reg[0]_0\ <= \^q_entry_r_reg[0]_0\;
  \q_entry_r_reg[1]_0\ <= \^q_entry_r_reg[1]_0\;
  q_has_priority <= \^q_has_priority\;
  \rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_0\ <= \^rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_0\;
  \rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_1\ <= \^rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_1\;
  \rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_2\ <= \^rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_2\;
  \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_0\ <= \^rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_0\;
  rd_wr_r_lcl_reg <= \^rd_wr_r_lcl_reg\;
  tail_r_16 <= \^tail_r_16\;
  wait_for_maint_r_13 <= \^wait_for_maint_r_13\;
auto_pre_r_lcl_reg: unisim.vcomponents.FDRE
     port map (
      C => \order_q_r_reg[1]_0\,
      CE => '1',
      D => auto_pre_r_lcl_reg_2,
      Q => auto_pre_r_lcl_reg_0,
      R => auto_pre_r_lcl_reg_1
    );
bm_end_r1_i_1: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFF0888"
    )
        port map (
      I0 => \^pass_open_bank_r_lcl_reg_0\,
      I1 => Q(0),
      I2 => bm_end_r1_reg,
      I3 => bm_end_r1_reg_0,
      I4 => \^pre_bm_end_r\,
      O => p_91_out
    );
\compute_tail.tail_r_lcl_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '1'
    )
        port map (
      C => \order_q_r_reg[1]_0\,
      CE => '1',
      D => \compute_tail.tail_r_lcl_reg_1\,
      Q => \^tail_r_16\,
      R => head_r_lcl_reg_1
    );
\demand_priority_r_i_2__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"F2F2F2FF"
    )
        port map (
      I0 => order_q_r(0),
      I1 => req_bank_rdy_r_reg,
      I2 => order_q_r(1),
      I3 => \^q_has_priority\,
      I4 => req_priority_r,
      O => \order_q_r_reg[0]_0\
    );
\grant_r[3]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000008A00000080"
    )
        port map (
      I0 => \grant_r[3]_i_6_n_0\,
      I1 => granted_col_r_reg_2,
      I2 => bm_end_r1_reg,
      I3 => \grant_r[3]_i_8_n_0\,
      I4 => granted_col_r_reg_3,
      I5 => granted_col_r_reg_4,
      O => \^rd_wr_r_lcl_reg\
    );
\grant_r[3]_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"BBBBBBBBBBBBABAA"
    )
        port map (
      I0 => req_bank_rdy_r_reg_0,
      I1 => \ras_timer_r_reg[0]_0\,
      I2 => \ras_timer_r_reg[0]_1\,
      I3 => rb_hit_busies_r_1(4),
      I4 => \ras_timer_r_reg[0]_2\,
      I5 => \grant_r[3]_i_2_4\,
      O => \grant_r[3]_i_6_n_0\
    );
\grant_r[3]_i_8\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFF2000"
    )
        port map (
      I0 => order_q_r(0),
      I1 => \grant_r[3]_i_2_0\,
      I2 => \grant_r[3]_i_2_1\,
      I3 => \grant_r[3]_i_2_2\,
      I4 => order_q_r(1),
      I5 => \grant_r[3]_i_2_3\,
      O => \grant_r[3]_i_8_n_0\
    );
granted_col_r_i_1: unisim.vcomponents.LUT4
    generic map(
      INIT => X"BFFF"
    )
        port map (
      I0 => \^rd_wr_r_lcl_reg\,
      I1 => granted_col_r_reg,
      I2 => granted_col_r_reg_0,
      I3 => granted_col_r_reg_1,
      O => granted_col_ns
    );
head_r_lcl_reg: unisim.vcomponents.FDRE
     port map (
      C => \order_q_r_reg[1]_0\,
      CE => '1',
      D => head_r_lcl_reg_2,
      Q => \^head_r_lcl_reg_0\,
      R => head_r_lcl_reg_1
    );
\i___25_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAAA00808080"
    )
        port map (
      I0 => rb_hit_busies_r(0),
      I1 => \^pass_open_bank_r_lcl_reg_0\,
      I2 => Q(0),
      I3 => bm_end_r1_reg,
      I4 => bm_end_r1_reg_0,
      I5 => pre_passing_open_bank_r,
      O => \rb_hit_busies.rb_hit_busies_r_lcl_reg[5]\
    );
\i___28_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"40555555"
    )
        port map (
      I0 => pre_passing_open_bank_r,
      I1 => bm_end_r1_reg_0,
      I2 => bm_end_r1_reg,
      I3 => Q(0),
      I4 => \^pass_open_bank_r_lcl_reg_0\,
      O => pre_passing_open_bank_r_reg_0
    );
\i___29_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAAA00808080"
    )
        port map (
      I0 => rb_hit_busies_r_0(0),
      I1 => \^pass_open_bank_r_lcl_reg_0\,
      I2 => Q(0),
      I3 => bm_end_r1_reg,
      I4 => bm_end_r1_reg_0,
      I5 => pre_passing_open_bank_r,
      O => \rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_0\
    );
\i___34_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0777077700000777"
    )
        port map (
      I0 => \i___34\,
      I1 => \^rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_0\,
      I2 => rb_hit_busies_r_1(4),
      I3 => \i___34_0\,
      I4 => \^rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_0\,
      I5 => \i___34_1\,
      O => \^rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_1\
    );
\i___35_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000FD555555"
    )
        port map (
      I0 => \^idle_r_lcl_reg_0\(0),
      I1 => use_addr,
      I2 => rb_hit_busy_r_reg_0,
      I3 => \^head_r_lcl_reg_0\,
      I4 => rb_hit_busy_r_reg_1,
      I5 => auto_pre_r_lcl_reg_1,
      O => \^idle_r_lcl_reg_1\
    );
\i___49_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000F4F4FFF4"
    )
        port map (
      I0 => \ras_timer_r_reg[0]_3\,
      I1 => \^rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_0\,
      I2 => \ras_timer_r_reg[0]_2\,
      I3 => rb_hit_busies_r_1(4),
      I4 => \ras_timer_r_reg[0]_1\,
      I5 => \ras_timer_r_reg[0]_0\,
      O => \^rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_2\
    );
\i___4_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"1400140014FF1400"
    )
        port map (
      I0 => head_r_lcl_reg_4,
      I1 => \^rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_1\,
      I2 => head_r_lcl_reg_3,
      I3 => head_r_lcl_reg_5,
      I4 => \^q_entry_r_reg[0]_0\,
      I5 => \^q_entry_r_reg[1]_0\,
      O => \q_entry_r_reg[0]_1\
    );
\i___4_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"40555555"
    )
        port map (
      I0 => \^pre_bm_end_r\,
      I1 => bm_end_r1_reg_0,
      I2 => bm_end_r1_reg,
      I3 => Q(0),
      I4 => \^pass_open_bank_r_lcl_reg_0\,
      O => \^pre_bm_end_r_reg_0\
    );
\i___62_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"5777FFFF"
    )
        port map (
      I0 => \^tail_r_16\,
      I1 => rb_hit_busy_r_reg_0,
      I2 => auto_pre_r_lcl_reg_3,
      I3 => use_addr,
      I4 => auto_pre_r_lcl_reg_4,
      O => \compute_tail.tail_r_lcl_reg_0\
    );
\i___73_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFDFFFFF"
    )
        port map (
      I0 => \i___73\,
      I1 => \^idle_r_lcl_reg_0\(0),
      I2 => \^head_r_lcl_reg_0\,
      I3 => \^wait_for_maint_r_13\,
      I4 => ras_timer_zero_r,
      O => act_wait_r_lcl_reg
    );
idle_r_lcl_i_1: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \^idle_r_lcl_reg_1\,
      O => \^e\(0)
    );
idle_r_lcl_reg: unisim.vcomponents.FDRE
     port map (
      C => \order_q_r_reg[1]_0\,
      CE => '1',
      D => \^e\(0),
      Q => \^idle_r_lcl_reg_0\(0),
      R => '0'
    );
\order_q_r[0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0D550C000D550CF0"
    )
        port map (
      I0 => \order_q_r_reg[0]_1\,
      I1 => order_q_r(1),
      I2 => order_q_r(0),
      I3 => req_bank_rdy_r_reg,
      I4 => \order_q_r_reg[1]_1\,
      I5 => \order_q_r_reg[0]_2\,
      O => \order_q_r[0]_i_1_n_0\
    );
\order_q_r[1]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"C2AAC000C2AAC0CC"
    )
        port map (
      I0 => \order_q_r_reg[1]_2\,
      I1 => order_q_r(1),
      I2 => order_q_r(0),
      I3 => req_bank_rdy_r_reg,
      I4 => \order_q_r_reg[1]_1\,
      I5 => \order_q_r_reg[1]_3\,
      O => \order_q_r[1]_i_1_n_0\
    );
\order_q_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \order_q_r_reg[1]_0\,
      CE => '1',
      D => \order_q_r[0]_i_1_n_0\,
      Q => order_q_r(0),
      R => '0'
    );
\order_q_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \order_q_r_reg[1]_0\,
      CE => '1',
      D => \order_q_r[1]_i_1_n_0\,
      Q => order_q_r(1),
      R => '0'
    );
ordered_r_lcl_reg: unisim.vcomponents.FDRE
     port map (
      C => \order_q_r_reg[1]_0\,
      CE => '1',
      D => ordered_r_lcl_reg_1,
      Q => ordered_r_lcl_reg_0,
      R => '0'
    );
pass_open_bank_r_lcl_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"4444544444444444"
    )
        port map (
      I0 => auto_pre_r_lcl_reg_1,
      I1 => \^pass_open_bank_r_lcl_reg_0\,
      I2 => \^tail_r_16\,
      I3 => pass_open_bank_r_lcl_reg_1,
      I4 => pre_wait_r,
      I5 => pass_open_bank_r_lcl_reg_2,
      O => \^pass_open_bank_ns\
    );
pass_open_bank_r_lcl_reg: unisim.vcomponents.FDRE
     port map (
      C => \order_q_r_reg[1]_0\,
      CE => '1',
      D => \^pass_open_bank_ns\,
      Q => \^pass_open_bank_r_lcl_reg_0\,
      R => '0'
    );
pre_bm_end_r_reg: unisim.vcomponents.FDRE
     port map (
      C => \order_q_r_reg[1]_0\,
      CE => '1',
      D => pre_bm_end_ns,
      Q => \^pre_bm_end_r\,
      R => '0'
    );
pre_passing_open_bank_r_reg: unisim.vcomponents.FDRE
     port map (
      C => \order_q_r_reg[1]_0\,
      CE => '1',
      D => pre_passing_open_bank_ns,
      Q => pre_passing_open_bank_r,
      R => '0'
    );
\q_entry_r[0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AA3CFFFFAA3C0000"
    )
        port map (
      I0 => \q_entry_r[0]_i_2__1_n_0\,
      I1 => \q_entry_r_reg[0]_2\,
      I2 => \q_entry_r_reg[0]_3\,
      I3 => \^pre_bm_end_r_reg_0\,
      I4 => \q_entry_r_reg[1]_2\,
      I5 => \^q_entry_r_reg[0]_0\,
      O => \q_entry_r[0]_i_1_n_0\
    );
\q_entry_r[0]_i_2__1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"909F"
    )
        port map (
      I0 => head_r_lcl_reg_3,
      I1 => \^rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_1\,
      I2 => \order_q_r_reg[1]_1\,
      I3 => \^q_entry_r_reg[0]_0\,
      O => \q_entry_r[0]_i_2__1_n_0\
    );
\q_entry_r[1]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => q_entry_ns(0),
      I1 => \q_entry_r_reg[1]_2\,
      I2 => \^q_entry_r_reg[1]_0\,
      O => \q_entry_r[1]_i_1_n_0\
    );
\q_entry_r[1]_i_3__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"A9A9A9A9FF0000FF"
    )
        port map (
      I0 => head_r_lcl_reg_4,
      I1 => \^rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_1\,
      I2 => head_r_lcl_reg_3,
      I3 => \^q_entry_r_reg[1]_0\,
      I4 => \^q_entry_r_reg[0]_0\,
      I5 => \order_q_r_reg[1]_1\,
      O => \q_entry_r_reg[1]_1\
    );
\q_entry_r_reg[0]\: unisim.vcomponents.FDSE
     port map (
      C => \order_q_r_reg[1]_0\,
      CE => '1',
      D => \q_entry_r[0]_i_1_n_0\,
      Q => \^q_entry_r_reg[0]_0\,
      S => head_r_lcl_reg_1
    );
\q_entry_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \order_q_r_reg[1]_0\,
      CE => '1',
      D => \q_entry_r[1]_i_1_n_0\,
      Q => \^q_entry_r_reg[1]_0\,
      R => head_r_lcl_reg_1
    );
q_has_priority_r_reg: unisim.vcomponents.FDRE
     port map (
      C => \order_q_r_reg[1]_0\,
      CE => '1',
      D => q_has_priority_r_reg_0,
      Q => \^q_has_priority\,
      R => auto_pre_r_lcl_reg_1
    );
q_has_rd_r_reg: unisim.vcomponents.FDRE
     port map (
      C => \order_q_r_reg[1]_0\,
      CE => '1',
      D => q_has_rd_r_reg_0,
      Q => q_has_rd_3,
      R => '0'
    );
\ras_timer_r[0]_i_1__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \ras_timer_r[0]_i_2__1_n_0\,
      I1 => \^rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_2\,
      I2 => \ras_timer_r_reg[0]\,
      O => D(0)
    );
\ras_timer_r[0]_i_2__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"BBBB8888B888B888"
    )
        port map (
      I0 => \ras_timer_r_reg[0]_4\,
      I1 => rb_hit_busies_r_1(4),
      I2 => \^rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_0\,
      I3 => \ras_timer_r_reg[0]_5\,
      I4 => \ras_timer_r_reg[0]_6\,
      I5 => \^rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_0\,
      O => \ras_timer_r[0]_i_2__1_n_0\
    );
\ras_timer_r[1]_i_1__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \ras_timer_r[1]_i_2__1_n_0\,
      I1 => \^rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_2\,
      I2 => \ras_timer_r_reg[1]\,
      O => D(1)
    );
\ras_timer_r[1]_i_2__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"B8BBB888B888B888"
    )
        port map (
      I0 => \ras_timer_r_reg[1]_0\,
      I1 => rb_hit_busies_r_1(4),
      I2 => \ras_timer_r_reg[1]_1\,
      I3 => \^rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_0\,
      I4 => \^rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_0\,
      I5 => \ras_timer_r_reg[1]_2\,
      O => \ras_timer_r[1]_i_2__1_n_0\
    );
\rb_hit_busies.rb_hit_busies_r_lcl[2]_i_1__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F022"
    )
        port map (
      I0 => \rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_3\,
      I1 => \rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_4\,
      I2 => \^rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_0\,
      I3 => \^idle_r_lcl_reg_1\,
      O => \rb_hit_busies.rb_hit_busies_r_lcl[2]_i_1__0_n_0\
    );
\rb_hit_busies.rb_hit_busies_r_lcl[3]_i_1__1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F022"
    )
        port map (
      I0 => \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_1\,
      I1 => \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_2\,
      I2 => \^rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_0\,
      I3 => \^idle_r_lcl_reg_1\,
      O => \rb_hit_busies.rb_hit_busies_r_lcl[3]_i_1__1_n_0\
    );
\rb_hit_busies.rb_hit_busies_r_lcl[4]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F022"
    )
        port map (
      I0 => \rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_0\,
      I1 => \rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_1\,
      I2 => rb_hit_busies_r_1(4),
      I3 => \^idle_r_lcl_reg_1\,
      O => \rb_hit_busies.rb_hit_busies_r_lcl[4]_i_2_n_0\
    );
\rb_hit_busies.rb_hit_busies_r_lcl_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \order_q_r_reg[1]_0\,
      CE => '1',
      D => \rb_hit_busies.rb_hit_busies_r_lcl[2]_i_1__0_n_0\,
      Q => \^rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_0\,
      R => \rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_5\
    );
\rb_hit_busies.rb_hit_busies_r_lcl_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \order_q_r_reg[1]_0\,
      CE => '1',
      D => \rb_hit_busies.rb_hit_busies_r_lcl[3]_i_1__1_n_0\,
      Q => \^rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_0\,
      R => \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_3\
    );
\rb_hit_busies.rb_hit_busies_r_lcl_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \order_q_r_reg[1]_0\,
      CE => '1',
      D => \rb_hit_busies.rb_hit_busies_r_lcl[4]_i_2_n_0\,
      Q => rb_hit_busies_r_1(4),
      R => \rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_2\
    );
rb_hit_busy_r_i_1: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \^idle_r_lcl_reg_1\,
      I1 => rb_hit_busy_r_reg,
      O => p_106_out
    );
\req_bank_rdy_r_i_1__1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"00A2"
    )
        port map (
      I0 => req_bank_rdy_r_reg_0,
      I1 => order_q_r(0),
      I2 => req_bank_rdy_r_reg,
      I3 => order_q_r(1),
      O => req_bank_rdy_ns
    );
wait_for_maint_r_lcl_reg: unisim.vcomponents.FDRE
     port map (
      C => \order_q_r_reg[1]_0\,
      CE => '1',
      D => wait_for_maint_r_lcl_reg_1,
      Q => \^wait_for_maint_r_13\,
      R => wait_for_maint_r_lcl_reg_0
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \mig_mig_7series_v4_2_bank_queue__parameterized1\ is
  port (
    idle_r_lcl_reg_0 : out STD_LOGIC;
    E : out STD_LOGIC_VECTOR ( 0 to 0 );
    pass_open_bank_r : out STD_LOGIC;
    pass_open_bank_ns : out STD_LOGIC;
    q_has_rd_7 : out STD_LOGIC;
    q_has_priority : out STD_LOGIC;
    pass_open_bank_r_lcl_reg_0 : out STD_LOGIC;
    wait_for_maint_r_14 : out STD_LOGIC;
    head_r_lcl_reg_0 : out STD_LOGIC;
    ordered_r_lcl_reg_0 : out STD_LOGIC;
    tail_r_17 : out STD_LOGIC;
    auto_pre_r_lcl_reg_0 : out STD_LOGIC;
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_0\ : out STD_LOGIC;
    idle_r_lcl_reg_1 : out STD_LOGIC;
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_0\ : out STD_LOGIC;
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_0\ : out STD_LOGIC;
    rd_wr_r_lcl_reg : out STD_LOGIC;
    D : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_1\ : out STD_LOGIC;
    \q_entry_r_reg[1]_0\ : out STD_LOGIC;
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_1\ : out STD_LOGIC;
    \q_entry_r_reg[1]_1\ : out STD_LOGIC;
    \q_entry_r_reg[0]_0\ : out STD_LOGIC;
    pre_bm_end_r_reg_0 : out STD_LOGIC;
    \q_entry_r_reg[0]_1\ : out STD_LOGIC;
    idle_r_lcl_reg_2 : out STD_LOGIC;
    \order_q_r_reg[0]_0\ : out STD_LOGIC;
    \order_q_r_reg[1]_0\ : out STD_LOGIC;
    req_bank_rdy_ns : out STD_LOGIC;
    p_67_out : out STD_LOGIC;
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[2]\ : out STD_LOGIC;
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[6]\ : out STD_LOGIC;
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_0\ : out STD_LOGIC;
    pre_passing_open_bank_r_reg_0 : out STD_LOGIC;
    \compute_tail.tail_r_lcl_reg_0\ : out STD_LOGIC;
    act_wait_r_lcl_reg : out STD_LOGIC;
    q_has_rd_r_reg_0 : in STD_LOGIC;
    pre_bm_end_ns : in STD_LOGIC;
    pre_passing_open_bank_ns : in STD_LOGIC;
    q_has_rd_r_reg_1 : in STD_LOGIC;
    q_has_priority_r_reg_0 : in STD_LOGIC;
    wait_for_maint_r_lcl_reg_0 : in STD_LOGIC;
    wait_for_maint_r_lcl_reg_1 : in STD_LOGIC;
    head_r_lcl_reg_1 : in STD_LOGIC;
    head_r_lcl_reg_2 : in STD_LOGIC;
    ordered_r_lcl_reg_1 : in STD_LOGIC;
    \compute_tail.tail_r_lcl_reg_1\ : in STD_LOGIC;
    auto_pre_r_lcl_reg_1 : in STD_LOGIC;
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_2\ : in STD_LOGIC;
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_3\ : in STD_LOGIC;
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_2\ : in STD_LOGIC;
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_3\ : in STD_LOGIC;
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_1\ : in STD_LOGIC;
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_2\ : in STD_LOGIC;
    granted_col_r_reg : in STD_LOGIC;
    granted_col_r_reg_0 : in STD_LOGIC;
    q_has_priority_r_reg_1 : in STD_LOGIC;
    granted_col_r_reg_1 : in STD_LOGIC;
    granted_col_r_reg_2 : in STD_LOGIC;
    \ras_timer_r_reg[0]\ : in STD_LOGIC;
    \ras_timer_r_reg[1]\ : in STD_LOGIC;
    \ras_timer_r_reg[0]_0\ : in STD_LOGIC;
    \ras_timer_r_reg[0]_1\ : in STD_LOGIC;
    \ras_timer_r_reg[0]_2\ : in STD_LOGIC;
    \ras_timer_r_reg[0]_3\ : in STD_LOGIC;
    head_r_lcl_reg_3 : in STD_LOGIC;
    head_r_lcl_reg_4 : in STD_LOGIC;
    \order_q_r_reg[1]_1\ : in STD_LOGIC;
    head_r_lcl_reg_5 : in STD_LOGIC;
    \q_entry_r_reg[1]_2\ : in STD_LOGIC;
    \i___5_i_4\ : in STD_LOGIC;
    \i___5_i_4_0\ : in STD_LOGIC;
    \i___5_i_4_1\ : in STD_LOGIC;
    req_bank_rdy_r_reg : in STD_LOGIC;
    req_priority_r : in STD_LOGIC;
    \grant_r[3]_i_3_0\ : in STD_LOGIC;
    \grant_r[3]_i_3_1\ : in STD_LOGIC;
    \grant_r[3]_i_3_2\ : in STD_LOGIC;
    \grant_r[3]_i_3_3\ : in STD_LOGIC;
    rnk_config_valid_r_lcl_reg : in STD_LOGIC;
    rnk_config_valid_r_lcl_reg_0 : in STD_LOGIC;
    req_bank_rdy_r_reg_0 : in STD_LOGIC;
    rb_hit_busy_r_reg : in STD_LOGIC;
    use_addr : in STD_LOGIC;
    rb_hit_busy_r_reg_0 : in STD_LOGIC;
    rb_hit_busy_r_reg_1 : in STD_LOGIC;
    \ras_timer_r_reg[1]_0\ : in STD_LOGIC;
    \ras_timer_r_reg[1]_1\ : in STD_LOGIC;
    \ras_timer_r_reg[1]_2\ : in STD_LOGIC;
    \ras_timer_r_reg[0]_4\ : in STD_LOGIC;
    \ras_timer_r_reg[0]_5\ : in STD_LOGIC;
    \ras_timer_r_reg[0]_6\ : in STD_LOGIC;
    \grant_r[3]_i_6\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    Q : in STD_LOGIC_VECTOR ( 0 to 0 );
    q_has_priority_r_reg_2 : in STD_LOGIC;
    rb_hit_busies_r_0 : in STD_LOGIC_VECTOR ( 0 to 0 );
    rb_hit_busies_r_1 : in STD_LOGIC_VECTOR ( 0 to 0 );
    pass_open_bank_r_lcl_reg_1 : in STD_LOGIC;
    pre_wait_r : in STD_LOGIC;
    pass_open_bank_r_lcl_reg_2 : in STD_LOGIC;
    q_has_priority_r_reg_3 : in STD_LOGIC;
    auto_pre_r_lcl_reg_2 : in STD_LOGIC;
    auto_pre_r_lcl_reg_3 : in STD_LOGIC;
    \grant_r[3]_i_2__0\ : in STD_LOGIC;
    ras_timer_zero_r : in STD_LOGIC;
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_4\ : in STD_LOGIC;
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_4\ : in STD_LOGIC;
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_3\ : in STD_LOGIC;
    \q_entry_r_reg[1]_3\ : in STD_LOGIC;
    \q_entry_r_reg[1]_4\ : in STD_LOGIC;
    \q_entry_r_reg[0]_2\ : in STD_LOGIC;
    \order_q_r_reg[1]_2\ : in STD_LOGIC;
    \order_q_r_reg[0]_1\ : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \mig_mig_7series_v4_2_bank_queue__parameterized1\ : entity is "mig_7series_v4_2_bank_queue";
end \mig_mig_7series_v4_2_bank_queue__parameterized1\;

architecture STRUCTURE of \mig_mig_7series_v4_2_bank_queue__parameterized1\ is
  signal \^e\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \grant_r[3]_i_10_n_0\ : STD_LOGIC;
  signal \^head_r_lcl_reg_0\ : STD_LOGIC;
  signal \^idle_r_lcl_reg_0\ : STD_LOGIC;
  signal \^idle_r_lcl_reg_1\ : STD_LOGIC;
  signal \^idle_r_lcl_reg_2\ : STD_LOGIC;
  signal order_q_r : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \order_q_r[0]_i_1_n_0\ : STD_LOGIC;
  signal \order_q_r[1]_i_1_n_0\ : STD_LOGIC;
  signal \^pass_open_bank_ns\ : STD_LOGIC;
  signal \^pass_open_bank_r\ : STD_LOGIC;
  signal \^pass_open_bank_r_lcl_reg_0\ : STD_LOGIC;
  signal pre_bm_end_r : STD_LOGIC;
  signal \^pre_bm_end_r_reg_0\ : STD_LOGIC;
  signal pre_passing_open_bank_r : STD_LOGIC;
  signal \q_entry_r[0]_i_1_n_0\ : STD_LOGIC;
  signal \q_entry_r[0]_i_2__0_n_0\ : STD_LOGIC;
  signal \q_entry_r[1]_i_1_n_0\ : STD_LOGIC;
  signal \^q_entry_r_reg[0]_0\ : STD_LOGIC;
  signal \^q_entry_r_reg[1]_1\ : STD_LOGIC;
  signal \^q_has_priority\ : STD_LOGIC;
  signal \ras_timer_r[0]_i_2__0_n_0\ : STD_LOGIC;
  signal \ras_timer_r[1]_i_2__0_n_0\ : STD_LOGIC;
  signal \rb_hit_busies.rb_hit_busies_r_lcl[3]_i_1_n_0\ : STD_LOGIC;
  signal \rb_hit_busies.rb_hit_busies_r_lcl[4]_i_1__0_n_0\ : STD_LOGIC;
  signal \rb_hit_busies.rb_hit_busies_r_lcl[5]_i_1__0_n_0\ : STD_LOGIC;
  signal \^rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_0\ : STD_LOGIC;
  signal \^rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_1\ : STD_LOGIC;
  signal \^rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_0\ : STD_LOGIC;
  signal \^rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_0\ : STD_LOGIC;
  signal \^rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_1\ : STD_LOGIC;
  signal \^tail_r_17\ : STD_LOGIC;
  signal \^wait_for_maint_r_14\ : STD_LOGIC;
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \idle_r_lcl_i_1__1\ : label is "soft_lutpair1173";
  attribute SOFT_HLUTNM of \ras_timer_r[0]_i_1__1\ : label is "soft_lutpair1175";
  attribute SOFT_HLUTNM of \ras_timer_r[1]_i_1__1\ : label is "soft_lutpair1175";
  attribute SOFT_HLUTNM of \rb_hit_busies.rb_hit_busies_r_lcl[4]_i_1__0\ : label is "soft_lutpair1173";
  attribute SOFT_HLUTNM of \rb_hit_busies.rb_hit_busies_r_lcl[5]_i_1__0\ : label is "soft_lutpair1174";
  attribute SOFT_HLUTNM of \rb_hit_busy_r_i_1__1\ : label is "soft_lutpair1174";
begin
  E(0) <= \^e\(0);
  head_r_lcl_reg_0 <= \^head_r_lcl_reg_0\;
  idle_r_lcl_reg_0 <= \^idle_r_lcl_reg_0\;
  idle_r_lcl_reg_1 <= \^idle_r_lcl_reg_1\;
  idle_r_lcl_reg_2 <= \^idle_r_lcl_reg_2\;
  pass_open_bank_ns <= \^pass_open_bank_ns\;
  pass_open_bank_r <= \^pass_open_bank_r\;
  pass_open_bank_r_lcl_reg_0 <= \^pass_open_bank_r_lcl_reg_0\;
  pre_bm_end_r_reg_0 <= \^pre_bm_end_r_reg_0\;
  \q_entry_r_reg[0]_0\ <= \^q_entry_r_reg[0]_0\;
  \q_entry_r_reg[1]_1\ <= \^q_entry_r_reg[1]_1\;
  q_has_priority <= \^q_has_priority\;
  \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_0\ <= \^rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_0\;
  \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_1\ <= \^rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_1\;
  \rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_0\ <= \^rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_0\;
  \rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_0\ <= \^rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_0\;
  \rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_1\ <= \^rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_1\;
  tail_r_17 <= \^tail_r_17\;
  wait_for_maint_r_14 <= \^wait_for_maint_r_14\;
auto_pre_r_lcl_reg: unisim.vcomponents.FDRE
     port map (
      C => q_has_rd_r_reg_0,
      CE => '1',
      D => auto_pre_r_lcl_reg_1,
      Q => auto_pre_r_lcl_reg_0,
      R => \^pass_open_bank_r_lcl_reg_0\
    );
\bm_end_r1_i_1__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"BFAAAAAA"
    )
        port map (
      I0 => pre_bm_end_r,
      I1 => q_has_priority_r_reg_2,
      I2 => q_has_priority_r_reg_1,
      I3 => Q(0),
      I4 => \^pass_open_bank_r\,
      O => \^pre_bm_end_r_reg_0\
    );
\compute_tail.tail_r_lcl_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '1'
    )
        port map (
      C => q_has_rd_r_reg_0,
      CE => '1',
      D => \compute_tail.tail_r_lcl_reg_1\,
      Q => \^tail_r_17\,
      R => head_r_lcl_reg_1
    );
\demand_priority_r_i_2__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"F2F2F2FF"
    )
        port map (
      I0 => order_q_r(0),
      I1 => req_bank_rdy_r_reg,
      I2 => order_q_r(1),
      I3 => \^q_has_priority\,
      I4 => req_priority_r,
      O => \order_q_r_reg[0]_0\
    );
\grant_r[3]_i_10\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFF2000"
    )
        port map (
      I0 => order_q_r(0),
      I1 => \grant_r[3]_i_3_0\,
      I2 => \grant_r[3]_i_3_1\,
      I3 => \grant_r[3]_i_3_2\,
      I4 => order_q_r(1),
      I5 => \grant_r[3]_i_3_3\,
      O => \grant_r[3]_i_10_n_0\
    );
\grant_r[3]_i_13\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAAA00808080"
    )
        port map (
      I0 => \grant_r[3]_i_6\(0),
      I1 => \^pass_open_bank_r\,
      I2 => Q(0),
      I3 => q_has_priority_r_reg_1,
      I4 => q_has_priority_r_reg_2,
      I5 => pre_passing_open_bank_r,
      O => \rb_hit_busies.rb_hit_busies_r_lcl_reg[2]\
    );
\grant_r[3]_i_20\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAAA00808080"
    )
        port map (
      I0 => rb_hit_busies_r_0(0),
      I1 => \^pass_open_bank_r\,
      I2 => Q(0),
      I3 => q_has_priority_r_reg_1,
      I4 => q_has_priority_r_reg_2,
      I5 => pre_passing_open_bank_r,
      O => \rb_hit_busies.rb_hit_busies_r_lcl_reg[6]\
    );
\grant_r[3]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFBAFFFFFFBF"
    )
        port map (
      I0 => granted_col_r_reg,
      I1 => granted_col_r_reg_0,
      I2 => q_has_priority_r_reg_1,
      I3 => \grant_r[3]_i_10_n_0\,
      I4 => granted_col_r_reg_1,
      I5 => granted_col_r_reg_2,
      O => rd_wr_r_lcl_reg
    );
\grant_r[3]_i_4__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFDFFFFF"
    )
        port map (
      I0 => \grant_r[3]_i_2__0\,
      I1 => \^idle_r_lcl_reg_0\,
      I2 => \^head_r_lcl_reg_0\,
      I3 => \^wait_for_maint_r_14\,
      I4 => ras_timer_zero_r,
      O => act_wait_r_lcl_reg
    );
head_r_lcl_reg: unisim.vcomponents.FDRE
     port map (
      C => q_has_rd_r_reg_0,
      CE => '1',
      D => head_r_lcl_reg_2,
      Q => \^head_r_lcl_reg_0\,
      R => head_r_lcl_reg_1
    );
\i___25_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"40555555"
    )
        port map (
      I0 => pre_passing_open_bank_r,
      I1 => q_has_priority_r_reg_2,
      I2 => q_has_priority_r_reg_1,
      I3 => Q(0),
      I4 => \^pass_open_bank_r\,
      O => pre_passing_open_bank_r_reg_0
    );
\i___28_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAAA00808080"
    )
        port map (
      I0 => rb_hit_busies_r_1(0),
      I1 => \^pass_open_bank_r\,
      I2 => Q(0),
      I3 => q_has_priority_r_reg_1,
      I4 => q_has_priority_r_reg_2,
      I5 => pre_passing_open_bank_r,
      O => \rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_0\
    );
\i___30_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000F4F4FFF4"
    )
        port map (
      I0 => \ras_timer_r_reg[0]_0\,
      I1 => \^rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_0\,
      I2 => \ras_timer_r_reg[0]_1\,
      I3 => \^rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_0\,
      I4 => \ras_timer_r_reg[0]_2\,
      I5 => \ras_timer_r_reg[0]_3\,
      O => \^rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_1\
    );
\i___40_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FDFFFDFDFFFFFFFF"
    )
        port map (
      I0 => rnk_config_valid_r_lcl_reg,
      I1 => rnk_config_valid_r_lcl_reg_0,
      I2 => order_q_r(1),
      I3 => req_bank_rdy_r_reg,
      I4 => order_q_r(0),
      I5 => req_bank_rdy_r_reg_0,
      O => \order_q_r_reg[1]_0\
    );
\i___46_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000FD555555"
    )
        port map (
      I0 => \^idle_r_lcl_reg_0\,
      I1 => use_addr,
      I2 => rb_hit_busy_r_reg_0,
      I3 => \^head_r_lcl_reg_0\,
      I4 => rb_hit_busy_r_reg_1,
      I5 => \^pass_open_bank_r_lcl_reg_0\,
      O => \^idle_r_lcl_reg_1\
    );
\i___5_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"1400140014FF1400"
    )
        port map (
      I0 => head_r_lcl_reg_3,
      I1 => \^rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_1\,
      I2 => head_r_lcl_reg_4,
      I3 => head_r_lcl_reg_5,
      I4 => \^q_entry_r_reg[0]_0\,
      I5 => \^q_entry_r_reg[1]_1\,
      O => \q_entry_r_reg[0]_1\
    );
\i___5_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFAFBFB"
    )
        port map (
      I0 => \^pre_bm_end_r_reg_0\,
      I1 => \^rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_1\,
      I2 => \order_q_r_reg[1]_1\,
      I3 => \q_entry_r_reg[1]_2\,
      I4 => \^idle_r_lcl_reg_0\,
      O => \^idle_r_lcl_reg_2\
    );
\i___5_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0DDD0DDD00000DDD"
    )
        port map (
      I0 => \^rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_0\,
      I1 => \i___5_i_4\,
      I2 => \^rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_0\,
      I3 => \i___5_i_4_0\,
      I4 => \^rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_0\,
      I5 => \i___5_i_4_1\,
      O => \^rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_1\
    );
\i___63_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"5777FFFF"
    )
        port map (
      I0 => \^tail_r_17\,
      I1 => rb_hit_busy_r_reg_0,
      I2 => auto_pre_r_lcl_reg_2,
      I3 => use_addr,
      I4 => auto_pre_r_lcl_reg_3,
      O => \compute_tail.tail_r_lcl_reg_0\
    );
\idle_r_lcl_i_1__1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \^idle_r_lcl_reg_1\,
      O => \^e\(0)
    );
idle_r_lcl_reg: unisim.vcomponents.FDRE
     port map (
      C => q_has_rd_r_reg_0,
      CE => '1',
      D => \^e\(0),
      Q => \^idle_r_lcl_reg_0\,
      R => '0'
    );
\order_q_r[0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0D550C000D550CF0"
    )
        port map (
      I0 => \order_q_r_reg[0]_1\,
      I1 => order_q_r(1),
      I2 => order_q_r(0),
      I3 => req_bank_rdy_r_reg,
      I4 => \order_q_r_reg[1]_1\,
      I5 => q_has_priority_r_reg_3,
      O => \order_q_r[0]_i_1_n_0\
    );
\order_q_r[1]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"C2AAC000C2AAC0CC"
    )
        port map (
      I0 => \order_q_r_reg[1]_2\,
      I1 => order_q_r(1),
      I2 => order_q_r(0),
      I3 => req_bank_rdy_r_reg,
      I4 => \order_q_r_reg[1]_1\,
      I5 => q_has_priority_r_reg_3,
      O => \order_q_r[1]_i_1_n_0\
    );
\order_q_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => q_has_rd_r_reg_0,
      CE => '1',
      D => \order_q_r[0]_i_1_n_0\,
      Q => order_q_r(0),
      R => '0'
    );
\order_q_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => q_has_rd_r_reg_0,
      CE => '1',
      D => \order_q_r[1]_i_1_n_0\,
      Q => order_q_r(1),
      R => '0'
    );
ordered_r_lcl_reg: unisim.vcomponents.FDRE
     port map (
      C => q_has_rd_r_reg_0,
      CE => '1',
      D => ordered_r_lcl_reg_1,
      Q => ordered_r_lcl_reg_0,
      R => '0'
    );
\pass_open_bank_r_lcl_i_1__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"4444544444444444"
    )
        port map (
      I0 => \^pass_open_bank_r_lcl_reg_0\,
      I1 => \^pass_open_bank_r\,
      I2 => \^tail_r_17\,
      I3 => pass_open_bank_r_lcl_reg_1,
      I4 => pre_wait_r,
      I5 => pass_open_bank_r_lcl_reg_2,
      O => \^pass_open_bank_ns\
    );
pass_open_bank_r_lcl_reg: unisim.vcomponents.FDRE
     port map (
      C => q_has_rd_r_reg_0,
      CE => '1',
      D => \^pass_open_bank_ns\,
      Q => \^pass_open_bank_r\,
      R => '0'
    );
pre_bm_end_r_reg: unisim.vcomponents.FDRE
     port map (
      C => q_has_rd_r_reg_0,
      CE => '1',
      D => pre_bm_end_ns,
      Q => pre_bm_end_r,
      R => '0'
    );
pre_passing_open_bank_r_reg: unisim.vcomponents.FDRE
     port map (
      C => q_has_rd_r_reg_0,
      CE => '1',
      D => pre_passing_open_bank_ns,
      Q => pre_passing_open_bank_r,
      R => '0'
    );
\q_entry_r[0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FF48FFFFFF480000"
    )
        port map (
      I0 => \q_entry_r_reg[1]_2\,
      I1 => \^pre_bm_end_r_reg_0\,
      I2 => \q_entry_r_reg[0]_2\,
      I3 => \q_entry_r[0]_i_2__0_n_0\,
      I4 => \^idle_r_lcl_reg_2\,
      I5 => \^q_entry_r_reg[0]_0\,
      O => \q_entry_r[0]_i_1_n_0\
    );
\q_entry_r[0]_i_2__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000990F"
    )
        port map (
      I0 => head_r_lcl_reg_4,
      I1 => \^rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_1\,
      I2 => \^q_entry_r_reg[0]_0\,
      I3 => \order_q_r_reg[1]_1\,
      I4 => \^pre_bm_end_r_reg_0\,
      O => \q_entry_r[0]_i_2__0_n_0\
    );
\q_entry_r[1]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"BF80FFFFBF800000"
    )
        port map (
      I0 => \q_entry_r_reg[1]_3\,
      I1 => \^pre_bm_end_r_reg_0\,
      I2 => \q_entry_r_reg[1]_2\,
      I3 => \q_entry_r_reg[1]_4\,
      I4 => \^idle_r_lcl_reg_2\,
      I5 => \^q_entry_r_reg[1]_1\,
      O => \q_entry_r[1]_i_1_n_0\
    );
\q_entry_r[1]_i_4__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"560056FF56FF5600"
    )
        port map (
      I0 => head_r_lcl_reg_3,
      I1 => \^rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_1\,
      I2 => head_r_lcl_reg_4,
      I3 => \order_q_r_reg[1]_1\,
      I4 => \^q_entry_r_reg[1]_1\,
      I5 => \^q_entry_r_reg[0]_0\,
      O => \q_entry_r_reg[1]_0\
    );
\q_entry_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => q_has_rd_r_reg_0,
      CE => '1',
      D => \q_entry_r[0]_i_1_n_0\,
      Q => \^q_entry_r_reg[0]_0\,
      R => head_r_lcl_reg_1
    );
\q_entry_r_reg[1]\: unisim.vcomponents.FDSE
     port map (
      C => q_has_rd_r_reg_0,
      CE => '1',
      D => \q_entry_r[1]_i_1_n_0\,
      Q => \^q_entry_r_reg[1]_1\,
      S => head_r_lcl_reg_1
    );
q_has_priority_r_reg: unisim.vcomponents.FDRE
     port map (
      C => q_has_rd_r_reg_0,
      CE => '1',
      D => q_has_priority_r_reg_0,
      Q => \^q_has_priority\,
      R => \^pass_open_bank_r_lcl_reg_0\
    );
q_has_rd_r_reg: unisim.vcomponents.FDRE
     port map (
      C => q_has_rd_r_reg_0,
      CE => '1',
      D => q_has_rd_r_reg_1,
      Q => q_has_rd_7,
      R => '0'
    );
\ras_timer_r[0]_i_1__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \ras_timer_r[0]_i_2__0_n_0\,
      I1 => \^rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_1\,
      I2 => \ras_timer_r_reg[0]\,
      O => D(0)
    );
\ras_timer_r[0]_i_2__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"B8BBB888B888B888"
    )
        port map (
      I0 => \ras_timer_r_reg[0]_4\,
      I1 => \^rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_0\,
      I2 => \ras_timer_r_reg[0]_5\,
      I3 => \^rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_0\,
      I4 => \^rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_0\,
      I5 => \ras_timer_r_reg[0]_6\,
      O => \ras_timer_r[0]_i_2__0_n_0\
    );
\ras_timer_r[1]_i_1__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \ras_timer_r[1]_i_2__0_n_0\,
      I1 => \^rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_1\,
      I2 => \ras_timer_r_reg[1]\,
      O => D(1)
    );
\ras_timer_r[1]_i_2__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"B8BBB888B888B888"
    )
        port map (
      I0 => \ras_timer_r_reg[1]_0\,
      I1 => \^rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_0\,
      I2 => \ras_timer_r_reg[1]_1\,
      I3 => \^rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_0\,
      I4 => \^rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_0\,
      I5 => \ras_timer_r_reg[1]_2\,
      O => \ras_timer_r[1]_i_2__0_n_0\
    );
\rb_hit_busies.rb_hit_busies_r_lcl[2]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFAAEAEAEA"
    )
        port map (
      I0 => q_has_priority_r_reg_3,
      I1 => \^pass_open_bank_r\,
      I2 => Q(0),
      I3 => q_has_priority_r_reg_1,
      I4 => q_has_priority_r_reg_2,
      I5 => pre_bm_end_r,
      O => \^pass_open_bank_r_lcl_reg_0\
    );
\rb_hit_busies.rb_hit_busies_r_lcl[3]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F022"
    )
        port map (
      I0 => \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_2\,
      I1 => \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_3\,
      I2 => \^rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_0\,
      I3 => \^idle_r_lcl_reg_1\,
      O => \rb_hit_busies.rb_hit_busies_r_lcl[3]_i_1_n_0\
    );
\rb_hit_busies.rb_hit_busies_r_lcl[4]_i_1__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F022"
    )
        port map (
      I0 => \rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_1\,
      I1 => \rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_2\,
      I2 => \^rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_0\,
      I3 => \^idle_r_lcl_reg_1\,
      O => \rb_hit_busies.rb_hit_busies_r_lcl[4]_i_1__0_n_0\
    );
\rb_hit_busies.rb_hit_busies_r_lcl[5]_i_1__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F022"
    )
        port map (
      I0 => \rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_2\,
      I1 => \rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_3\,
      I2 => \^rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_0\,
      I3 => \^idle_r_lcl_reg_1\,
      O => \rb_hit_busies.rb_hit_busies_r_lcl[5]_i_1__0_n_0\
    );
\rb_hit_busies.rb_hit_busies_r_lcl_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => q_has_rd_r_reg_0,
      CE => '1',
      D => \rb_hit_busies.rb_hit_busies_r_lcl[3]_i_1_n_0\,
      Q => \^rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_0\,
      R => \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_4\
    );
\rb_hit_busies.rb_hit_busies_r_lcl_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => q_has_rd_r_reg_0,
      CE => '1',
      D => \rb_hit_busies.rb_hit_busies_r_lcl[4]_i_1__0_n_0\,
      Q => \^rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_0\,
      R => \rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_3\
    );
\rb_hit_busies.rb_hit_busies_r_lcl_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => q_has_rd_r_reg_0,
      CE => '1',
      D => \rb_hit_busies.rb_hit_busies_r_lcl[5]_i_1__0_n_0\,
      Q => \^rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_0\,
      R => \rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_4\
    );
\rb_hit_busy_r_i_1__1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \^idle_r_lcl_reg_1\,
      I1 => rb_hit_busy_r_reg,
      O => p_67_out
    );
\req_bank_rdy_r_i_1__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"00A2"
    )
        port map (
      I0 => req_bank_rdy_r_reg_0,
      I1 => order_q_r(0),
      I2 => req_bank_rdy_r_reg,
      I3 => order_q_r(1),
      O => req_bank_rdy_ns
    );
wait_for_maint_r_lcl_reg: unisim.vcomponents.FDRE
     port map (
      C => q_has_rd_r_reg_0,
      CE => '1',
      D => wait_for_maint_r_lcl_reg_1,
      Q => \^wait_for_maint_r_14\,
      R => wait_for_maint_r_lcl_reg_0
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \mig_mig_7series_v4_2_bank_queue__parameterized2\ is
  port (
    idle_r_lcl_reg_0 : out STD_LOGIC_VECTOR ( 0 to 0 );
    E : out STD_LOGIC_VECTOR ( 0 to 0 );
    pass_open_bank_r_lcl_reg_0 : out STD_LOGIC;
    pass_open_bank_ns : out STD_LOGIC;
    pre_bm_end_r_11 : out STD_LOGIC;
    q_has_rd_12 : out STD_LOGIC;
    q_has_priority : out STD_LOGIC;
    wait_for_maint_r_15 : out STD_LOGIC;
    head_r_lcl_reg_0 : out STD_LOGIC;
    ordered_r_lcl_reg_0 : out STD_LOGIC;
    tail_r_18 : out STD_LOGIC;
    auto_pre_r_lcl_reg_0 : out STD_LOGIC;
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_0\ : out STD_LOGIC;
    idle_r_lcl_reg_1 : out STD_LOGIC;
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[6]_0\ : out STD_LOGIC;
    rd_wr_r_lcl_reg : out STD_LOGIC;
    D : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[6]_1\ : out STD_LOGIC;
    pre_bm_end_r_reg_0 : out STD_LOGIC;
    pre_bm_end_r_reg_1 : out STD_LOGIC;
    \q_entry_r_reg[1]_0\ : out STD_LOGIC;
    \q_entry_r_reg[0]_0\ : out STD_LOGIC;
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_0\ : out STD_LOGIC;
    \q_entry_r_reg[0]_1\ : out STD_LOGIC;
    pre_bm_end_r_reg_2 : out STD_LOGIC;
    \order_q_r_reg[0]_0\ : out STD_LOGIC;
    req_bank_rdy_ns : out STD_LOGIC;
    p_28_out : out STD_LOGIC;
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]\ : out STD_LOGIC;
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_0\ : out STD_LOGIC;
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_1\ : out STD_LOGIC;
    pre_passing_open_bank_r_reg_0 : out STD_LOGIC;
    p_13_out : out STD_LOGIC;
    \compute_tail.tail_r_lcl_reg_0\ : out STD_LOGIC;
    act_wait_r_lcl_reg : out STD_LOGIC;
    \order_q_r_reg[1]_0\ : in STD_LOGIC;
    pre_bm_end_ns : in STD_LOGIC;
    pre_passing_open_bank_ns : in STD_LOGIC;
    q_has_rd_r_reg_0 : in STD_LOGIC;
    auto_pre_r_lcl_reg_1 : in STD_LOGIC;
    q_has_priority_r_reg_0 : in STD_LOGIC;
    wait_for_maint_r_lcl_reg_0 : in STD_LOGIC;
    wait_for_maint_r_lcl_reg_1 : in STD_LOGIC;
    head_r_lcl_reg_1 : in STD_LOGIC;
    head_r_lcl_reg_2 : in STD_LOGIC;
    ordered_r_lcl_reg_1 : in STD_LOGIC;
    \compute_tail.tail_r_lcl_reg_1\ : in STD_LOGIC;
    auto_pre_r_lcl_reg_2 : in STD_LOGIC;
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_1\ : in STD_LOGIC;
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_2\ : in STD_LOGIC;
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[6]_2\ : in STD_LOGIC;
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[6]_3\ : in STD_LOGIC;
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_1\ : in STD_LOGIC;
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_2\ : in STD_LOGIC;
    granted_col_r_reg : in STD_LOGIC;
    bm_end_r1_reg : in STD_LOGIC;
    granted_col_r_reg_0 : in STD_LOGIC;
    granted_col_r_reg_1 : in STD_LOGIC;
    \ras_timer_r_reg[0]\ : in STD_LOGIC;
    \ras_timer_r_reg[1]\ : in STD_LOGIC;
    req_bank_rdy_r_reg : in STD_LOGIC;
    \ras_timer_r_reg[0]_0\ : in STD_LOGIC;
    \ras_timer_r_reg[0]_1\ : in STD_LOGIC;
    \ras_timer_r_reg[0]_2\ : in STD_LOGIC;
    \grant_r[3]_i_5_0\ : in STD_LOGIC;
    \ras_timer_r_reg[0]_3\ : in STD_LOGIC;
    \compute_tail.tail_r_lcl_reg_2\ : in STD_LOGIC;
    \compute_tail.tail_r_lcl_reg_3\ : in STD_LOGIC;
    \q_entry_r_reg[1]_1\ : in STD_LOGIC;
    \q_entry_r_reg[1]_2\ : in STD_LOGIC;
    \order_q_r_reg[1]_1\ : in STD_LOGIC;
    head_r_lcl_reg_3 : in STD_LOGIC;
    head_r_lcl_reg_4 : in STD_LOGIC;
    head_r_lcl_reg_5 : in STD_LOGIC;
    \compute_tail.tail_r_lcl_reg_4\ : in STD_LOGIC;
    req_bank_rdy_r_reg_0 : in STD_LOGIC;
    req_priority_r : in STD_LOGIC;
    \grant_r[3]_i_5_1\ : in STD_LOGIC;
    \grant_r[3]_i_5_2\ : in STD_LOGIC;
    \grant_r[3]_i_5_3\ : in STD_LOGIC;
    \grant_r[3]_i_5_4\ : in STD_LOGIC;
    rb_hit_busy_r_reg : in STD_LOGIC;
    use_addr : in STD_LOGIC;
    rb_hit_busy_r_reg_0 : in STD_LOGIC;
    rb_hit_busy_r_reg_1 : in STD_LOGIC;
    \ras_timer_r_reg[1]_0\ : in STD_LOGIC;
    \ras_timer_r_reg[1]_1\ : in STD_LOGIC;
    \ras_timer_r_reg[1]_2\ : in STD_LOGIC;
    \ras_timer_r_reg[0]_4\ : in STD_LOGIC;
    \ras_timer_r_reg[0]_5\ : in STD_LOGIC;
    \ras_timer_r_reg[0]_6\ : in STD_LOGIC;
    \grant_r[3]_i_6\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    Q : in STD_LOGIC_VECTOR ( 0 to 0 );
    bm_end_r1_reg_0 : in STD_LOGIC;
    rb_hit_busies_r : in STD_LOGIC_VECTOR ( 0 to 0 );
    rb_hit_busies_r_1 : in STD_LOGIC_VECTOR ( 0 to 0 );
    pass_open_bank_r_lcl_reg_1 : in STD_LOGIC;
    pre_wait_r : in STD_LOGIC;
    pass_open_bank_r_lcl_reg_2 : in STD_LOGIC;
    auto_pre_r_lcl_reg_3 : in STD_LOGIC;
    auto_pre_r_lcl_reg_4 : in STD_LOGIC;
    \i___74\ : in STD_LOGIC;
    ras_timer_zero_r : in STD_LOGIC;
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[6]_4\ : in STD_LOGIC;
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_3\ : in STD_LOGIC;
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_3\ : in STD_LOGIC;
    \q_entry_r_reg[1]_3\ : in STD_LOGIC;
    \q_entry_r_reg[1]_4\ : in STD_LOGIC;
    \q_entry_r_reg[1]_5\ : in STD_LOGIC;
    \q_entry_r_reg[0]_2\ : in STD_LOGIC;
    \order_q_r_reg[1]_2\ : in STD_LOGIC;
    \order_q_r_reg[0]_1\ : in STD_LOGIC;
    \order_q_r_reg[0]_2\ : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \mig_mig_7series_v4_2_bank_queue__parameterized2\ : entity is "mig_7series_v4_2_bank_queue";
end \mig_mig_7series_v4_2_bank_queue__parameterized2\;

architecture STRUCTURE of \mig_mig_7series_v4_2_bank_queue__parameterized2\ is
  signal \^e\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \grant_r[3]_i_11_n_0\ : STD_LOGIC;
  signal \grant_r[3]_i_12_n_0\ : STD_LOGIC;
  signal \^head_r_lcl_reg_0\ : STD_LOGIC;
  signal \^idle_r_lcl_reg_0\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \^idle_r_lcl_reg_1\ : STD_LOGIC;
  signal order_q_r : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \order_q_r[0]_i_1_n_0\ : STD_LOGIC;
  signal \order_q_r[1]_i_1_n_0\ : STD_LOGIC;
  signal \^pass_open_bank_ns\ : STD_LOGIC;
  signal \^pass_open_bank_r_lcl_reg_0\ : STD_LOGIC;
  signal \^pre_bm_end_r_11\ : STD_LOGIC;
  signal \^pre_bm_end_r_reg_1\ : STD_LOGIC;
  signal pre_passing_open_bank_r : STD_LOGIC;
  signal \q_entry_r[0]_i_1_n_0\ : STD_LOGIC;
  signal \q_entry_r[0]_i_3_n_0\ : STD_LOGIC;
  signal \q_entry_r[1]_i_1_n_0\ : STD_LOGIC;
  signal \q_entry_r[1]_i_3_n_0\ : STD_LOGIC;
  signal \^q_entry_r_reg[0]_0\ : STD_LOGIC;
  signal \^q_entry_r_reg[1]_0\ : STD_LOGIC;
  signal \^q_has_priority\ : STD_LOGIC;
  signal \ras_timer_r[0]_i_2_n_0\ : STD_LOGIC;
  signal \ras_timer_r[1]_i_2_n_0\ : STD_LOGIC;
  signal \rb_hit_busies.rb_hit_busies_r_lcl[4]_i_1__1_n_0\ : STD_LOGIC;
  signal \rb_hit_busies.rb_hit_busies_r_lcl[5]_i_1_n_0\ : STD_LOGIC;
  signal \rb_hit_busies.rb_hit_busies_r_lcl[6]_i_1_n_0\ : STD_LOGIC;
  signal \^rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_0\ : STD_LOGIC;
  signal \^rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_0\ : STD_LOGIC;
  signal \^rb_hit_busies.rb_hit_busies_r_lcl_reg[6]_0\ : STD_LOGIC;
  signal \^rb_hit_busies.rb_hit_busies_r_lcl_reg[6]_1\ : STD_LOGIC;
  signal rb_hit_busies_r_0 : STD_LOGIC_VECTOR ( 4 to 4 );
  signal \^tail_r_18\ : STD_LOGIC;
  signal \^wait_for_maint_r_15\ : STD_LOGIC;
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \bm_end_r1_i_1__2\ : label is "soft_lutpair1181";
  attribute SOFT_HLUTNM of \i___2_i_2\ : label is "soft_lutpair1184";
  attribute SOFT_HLUTNM of \i___6_i_2\ : label is "soft_lutpair1181";
  attribute SOFT_HLUTNM of \i___8_i_3\ : label is "soft_lutpair1184";
  attribute SOFT_HLUTNM of \idle_r_lcl_i_1__0\ : label is "soft_lutpair1182";
  attribute SOFT_HLUTNM of \ras_timer_r[0]_i_1\ : label is "soft_lutpair1185";
  attribute SOFT_HLUTNM of \ras_timer_r[1]_i_1\ : label is "soft_lutpair1185";
  attribute SOFT_HLUTNM of \rb_hit_busies.rb_hit_busies_r_lcl[4]_i_1__1\ : label is "soft_lutpair1183";
  attribute SOFT_HLUTNM of \rb_hit_busies.rb_hit_busies_r_lcl[6]_i_1\ : label is "soft_lutpair1182";
  attribute SOFT_HLUTNM of \rb_hit_busy_r_i_1__0\ : label is "soft_lutpair1183";
begin
  E(0) <= \^e\(0);
  head_r_lcl_reg_0 <= \^head_r_lcl_reg_0\;
  idle_r_lcl_reg_0(0) <= \^idle_r_lcl_reg_0\(0);
  idle_r_lcl_reg_1 <= \^idle_r_lcl_reg_1\;
  pass_open_bank_ns <= \^pass_open_bank_ns\;
  pass_open_bank_r_lcl_reg_0 <= \^pass_open_bank_r_lcl_reg_0\;
  pre_bm_end_r_11 <= \^pre_bm_end_r_11\;
  pre_bm_end_r_reg_1 <= \^pre_bm_end_r_reg_1\;
  \q_entry_r_reg[0]_0\ <= \^q_entry_r_reg[0]_0\;
  \q_entry_r_reg[1]_0\ <= \^q_entry_r_reg[1]_0\;
  q_has_priority <= \^q_has_priority\;
  \rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_0\ <= \^rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_0\;
  \rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_0\ <= \^rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_0\;
  \rb_hit_busies.rb_hit_busies_r_lcl_reg[6]_0\ <= \^rb_hit_busies.rb_hit_busies_r_lcl_reg[6]_0\;
  \rb_hit_busies.rb_hit_busies_r_lcl_reg[6]_1\ <= \^rb_hit_busies.rb_hit_busies_r_lcl_reg[6]_1\;
  tail_r_18 <= \^tail_r_18\;
  wait_for_maint_r_15 <= \^wait_for_maint_r_15\;
auto_pre_r_lcl_reg: unisim.vcomponents.FDRE
     port map (
      C => \order_q_r_reg[1]_0\,
      CE => '1',
      D => auto_pre_r_lcl_reg_2,
      Q => auto_pre_r_lcl_reg_0,
      R => auto_pre_r_lcl_reg_1
    );
\bm_end_r1_i_1__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFF0888"
    )
        port map (
      I0 => \^pass_open_bank_r_lcl_reg_0\,
      I1 => Q(0),
      I2 => bm_end_r1_reg,
      I3 => bm_end_r1_reg_0,
      I4 => \^pre_bm_end_r_11\,
      O => p_13_out
    );
\compute_tail.tail_r_lcl_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '1'
    )
        port map (
      C => \order_q_r_reg[1]_0\,
      CE => '1',
      D => \compute_tail.tail_r_lcl_reg_1\,
      Q => \^tail_r_18\,
      R => head_r_lcl_reg_1
    );
demand_priority_r_i_2: unisim.vcomponents.LUT5
    generic map(
      INIT => X"F2F2F2FF"
    )
        port map (
      I0 => order_q_r(0),
      I1 => req_bank_rdy_r_reg_0,
      I2 => order_q_r(1),
      I3 => \^q_has_priority\,
      I4 => req_priority_r,
      O => \order_q_r_reg[0]_0\
    );
\grant_r[3]_i_11\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFF2000"
    )
        port map (
      I0 => order_q_r(0),
      I1 => \grant_r[3]_i_5_1\,
      I2 => \grant_r[3]_i_5_2\,
      I3 => \grant_r[3]_i_5_3\,
      I4 => order_q_r(1),
      I5 => \grant_r[3]_i_5_4\,
      O => \grant_r[3]_i_11_n_0\
    );
\grant_r[3]_i_12\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"BBBBBBBBBBBBABAA"
    )
        port map (
      I0 => req_bank_rdy_r_reg,
      I1 => \ras_timer_r_reg[0]_0\,
      I2 => \ras_timer_r_reg[0]_1\,
      I3 => rb_hit_busies_r_0(4),
      I4 => \ras_timer_r_reg[0]_2\,
      I5 => \grant_r[3]_i_5_0\,
      O => \grant_r[3]_i_12_n_0\
    );
\grant_r[3]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFF4FFF7FFFFFFFF"
    )
        port map (
      I0 => granted_col_r_reg,
      I1 => bm_end_r1_reg,
      I2 => \grant_r[3]_i_11_n_0\,
      I3 => granted_col_r_reg_0,
      I4 => granted_col_r_reg_1,
      I5 => \grant_r[3]_i_12_n_0\,
      O => rd_wr_r_lcl_reg
    );
head_r_lcl_reg: unisim.vcomponents.FDRE
     port map (
      C => \order_q_r_reg[1]_0\,
      CE => '1',
      D => head_r_lcl_reg_2,
      Q => \^head_r_lcl_reg_0\,
      R => head_r_lcl_reg_1
    );
\i___25_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000F4F4FFF4"
    )
        port map (
      I0 => \ras_timer_r_reg[0]_3\,
      I1 => \^rb_hit_busies.rb_hit_busies_r_lcl_reg[6]_0\,
      I2 => \ras_timer_r_reg[0]_2\,
      I3 => rb_hit_busies_r_0(4),
      I4 => \ras_timer_r_reg[0]_1\,
      I5 => \ras_timer_r_reg[0]_0\,
      O => \^rb_hit_busies.rb_hit_busies_r_lcl_reg[6]_1\
    );
\i___28_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAAA00808080"
    )
        port map (
      I0 => rb_hit_busies_r(0),
      I1 => \^pass_open_bank_r_lcl_reg_0\,
      I2 => Q(0),
      I3 => bm_end_r1_reg,
      I4 => bm_end_r1_reg_0,
      I5 => pre_passing_open_bank_r,
      O => \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_0\
    );
\i___29_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAAA00808080"
    )
        port map (
      I0 => rb_hit_busies_r_1(0),
      I1 => \^pass_open_bank_r_lcl_reg_0\,
      I2 => Q(0),
      I3 => bm_end_r1_reg,
      I4 => bm_end_r1_reg_0,
      I5 => pre_passing_open_bank_r,
      O => \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_1\
    );
\i___2_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"08"
    )
        port map (
      I0 => \^pre_bm_end_r_reg_1\,
      I1 => \compute_tail.tail_r_lcl_reg_2\,
      I2 => \compute_tail.tail_r_lcl_reg_4\,
      O => pre_bm_end_r_reg_2
    );
\i___30_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"40555555"
    )
        port map (
      I0 => pre_passing_open_bank_r,
      I1 => bm_end_r1_reg_0,
      I2 => bm_end_r1_reg,
      I3 => Q(0),
      I4 => \^pass_open_bank_r_lcl_reg_0\,
      O => pre_passing_open_bank_r_reg_0
    );
\i___38_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0777077700000777"
    )
        port map (
      I0 => \compute_tail.tail_r_lcl_reg_3\,
      I1 => rb_hit_busies_r_0(4),
      I2 => \^rb_hit_busies.rb_hit_busies_r_lcl_reg[6]_0\,
      I3 => \compute_tail.tail_r_lcl_reg_4\,
      I4 => \^rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_0\,
      I5 => \compute_tail.tail_r_lcl_reg_2\,
      O => \^rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_0\
    );
\i___44_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000FD555555"
    )
        port map (
      I0 => \^idle_r_lcl_reg_0\(0),
      I1 => use_addr,
      I2 => rb_hit_busy_r_reg_0,
      I3 => \^head_r_lcl_reg_0\,
      I4 => rb_hit_busy_r_reg_1,
      I5 => auto_pre_r_lcl_reg_1,
      O => \^idle_r_lcl_reg_1\
    );
\i___49_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAAA00808080"
    )
        port map (
      I0 => \grant_r[3]_i_6\(0),
      I1 => \^pass_open_bank_r_lcl_reg_0\,
      I2 => Q(0),
      I3 => bm_end_r1_reg,
      I4 => bm_end_r1_reg_0,
      I5 => pre_passing_open_bank_r,
      O => \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]\
    );
\i___64_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"777F7F7F"
    )
        port map (
      I0 => \^tail_r_18\,
      I1 => auto_pre_r_lcl_reg_3,
      I2 => rb_hit_busy_r_reg_0,
      I3 => auto_pre_r_lcl_reg_4,
      I4 => use_addr,
      O => \compute_tail.tail_r_lcl_reg_0\
    );
\i___6_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"2020202F202F2020"
    )
        port map (
      I0 => \^q_entry_r_reg[0]_0\,
      I1 => \^q_entry_r_reg[1]_0\,
      I2 => head_r_lcl_reg_4,
      I3 => head_r_lcl_reg_5,
      I4 => \^rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_0\,
      I5 => head_r_lcl_reg_3,
      O => \q_entry_r_reg[0]_1\
    );
\i___6_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"40555555"
    )
        port map (
      I0 => \^pre_bm_end_r_11\,
      I1 => bm_end_r1_reg_0,
      I2 => bm_end_r1_reg,
      I3 => Q(0),
      I4 => \^pass_open_bank_r_lcl_reg_0\,
      O => \^pre_bm_end_r_reg_1\
    );
\i___74_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFDFFFFF"
    )
        port map (
      I0 => \i___74\,
      I1 => \^idle_r_lcl_reg_0\(0),
      I2 => \^head_r_lcl_reg_0\,
      I3 => \^wait_for_maint_r_15\,
      I4 => ras_timer_zero_r,
      O => act_wait_r_lcl_reg
    );
\i___8_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"08"
    )
        port map (
      I0 => \^pre_bm_end_r_reg_1\,
      I1 => \compute_tail.tail_r_lcl_reg_2\,
      I2 => \compute_tail.tail_r_lcl_reg_3\,
      O => pre_bm_end_r_reg_0
    );
\idle_r_lcl_i_1__0\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \^idle_r_lcl_reg_1\,
      O => \^e\(0)
    );
idle_r_lcl_reg: unisim.vcomponents.FDRE
     port map (
      C => \order_q_r_reg[1]_0\,
      CE => '1',
      D => \^e\(0),
      Q => \^idle_r_lcl_reg_0\(0),
      R => '0'
    );
\order_q_r[0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0D550C000D550CF0"
    )
        port map (
      I0 => \order_q_r_reg[0]_2\,
      I1 => order_q_r(1),
      I2 => order_q_r(0),
      I3 => req_bank_rdy_r_reg_0,
      I4 => \order_q_r_reg[1]_1\,
      I5 => \order_q_r_reg[0]_1\,
      O => \order_q_r[0]_i_1_n_0\
    );
\order_q_r[1]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"C2AAC000C2AAC0CC"
    )
        port map (
      I0 => \order_q_r_reg[1]_2\,
      I1 => order_q_r(1),
      I2 => order_q_r(0),
      I3 => req_bank_rdy_r_reg_0,
      I4 => \order_q_r_reg[1]_1\,
      I5 => \order_q_r_reg[0]_1\,
      O => \order_q_r[1]_i_1_n_0\
    );
\order_q_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \order_q_r_reg[1]_0\,
      CE => '1',
      D => \order_q_r[0]_i_1_n_0\,
      Q => order_q_r(0),
      R => '0'
    );
\order_q_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \order_q_r_reg[1]_0\,
      CE => '1',
      D => \order_q_r[1]_i_1_n_0\,
      Q => order_q_r(1),
      R => '0'
    );
ordered_r_lcl_reg: unisim.vcomponents.FDRE
     port map (
      C => \order_q_r_reg[1]_0\,
      CE => '1',
      D => ordered_r_lcl_reg_1,
      Q => ordered_r_lcl_reg_0,
      R => '0'
    );
\pass_open_bank_r_lcl_i_1__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"4444544444444444"
    )
        port map (
      I0 => auto_pre_r_lcl_reg_1,
      I1 => \^pass_open_bank_r_lcl_reg_0\,
      I2 => \^tail_r_18\,
      I3 => pass_open_bank_r_lcl_reg_1,
      I4 => pre_wait_r,
      I5 => pass_open_bank_r_lcl_reg_2,
      O => \^pass_open_bank_ns\
    );
pass_open_bank_r_lcl_reg: unisim.vcomponents.FDRE
     port map (
      C => \order_q_r_reg[1]_0\,
      CE => '1',
      D => \^pass_open_bank_ns\,
      Q => \^pass_open_bank_r_lcl_reg_0\,
      R => '0'
    );
pre_bm_end_r_reg: unisim.vcomponents.FDRE
     port map (
      C => \order_q_r_reg[1]_0\,
      CE => '1',
      D => pre_bm_end_ns,
      Q => \^pre_bm_end_r_11\,
      R => '0'
    );
pre_passing_open_bank_r_reg: unisim.vcomponents.FDRE
     port map (
      C => \order_q_r_reg[1]_0\,
      CE => '1',
      D => pre_passing_open_bank_ns,
      Q => pre_passing_open_bank_r,
      R => '0'
    );
\q_entry_r[0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FD21FFFFFD210000"
    )
        port map (
      I0 => \q_entry_r_reg[1]_4\,
      I1 => \^pre_bm_end_r_reg_1\,
      I2 => \q_entry_r_reg[0]_2\,
      I3 => \q_entry_r[0]_i_3_n_0\,
      I4 => \q_entry_r_reg[1]_5\,
      I5 => \^q_entry_r_reg[0]_0\,
      O => \q_entry_r[0]_i_1_n_0\
    );
\q_entry_r[0]_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"909F0000"
    )
        port map (
      I0 => head_r_lcl_reg_3,
      I1 => \^rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_0\,
      I2 => \order_q_r_reg[1]_1\,
      I3 => \^q_entry_r_reg[0]_0\,
      I4 => \^pre_bm_end_r_reg_1\,
      O => \q_entry_r[0]_i_3_n_0\
    );
\q_entry_r[1]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FB08FFFFFB080000"
    )
        port map (
      I0 => \q_entry_r_reg[1]_3\,
      I1 => \q_entry_r_reg[1]_4\,
      I2 => \^pre_bm_end_r_reg_1\,
      I3 => \q_entry_r[1]_i_3_n_0\,
      I4 => \q_entry_r_reg[1]_5\,
      I5 => \^q_entry_r_reg[1]_0\,
      O => \q_entry_r[1]_i_1_n_0\
    );
\q_entry_r[1]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"1DDD1D111D111DDD"
    )
        port map (
      I0 => \q_entry_r_reg[1]_1\,
      I1 => \^pre_bm_end_r_reg_1\,
      I2 => \q_entry_r_reg[1]_2\,
      I3 => \order_q_r_reg[1]_1\,
      I4 => \^q_entry_r_reg[1]_0\,
      I5 => \^q_entry_r_reg[0]_0\,
      O => \q_entry_r[1]_i_3_n_0\
    );
\q_entry_r_reg[0]\: unisim.vcomponents.FDSE
     port map (
      C => \order_q_r_reg[1]_0\,
      CE => '1',
      D => \q_entry_r[0]_i_1_n_0\,
      Q => \^q_entry_r_reg[0]_0\,
      S => head_r_lcl_reg_1
    );
\q_entry_r_reg[1]\: unisim.vcomponents.FDSE
     port map (
      C => \order_q_r_reg[1]_0\,
      CE => '1',
      D => \q_entry_r[1]_i_1_n_0\,
      Q => \^q_entry_r_reg[1]_0\,
      S => head_r_lcl_reg_1
    );
q_has_priority_r_reg: unisim.vcomponents.FDRE
     port map (
      C => \order_q_r_reg[1]_0\,
      CE => '1',
      D => q_has_priority_r_reg_0,
      Q => \^q_has_priority\,
      R => auto_pre_r_lcl_reg_1
    );
q_has_rd_r_reg: unisim.vcomponents.FDRE
     port map (
      C => \order_q_r_reg[1]_0\,
      CE => '1',
      D => q_has_rd_r_reg_0,
      Q => q_has_rd_12,
      R => '0'
    );
\ras_timer_r[0]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \ras_timer_r[0]_i_2_n_0\,
      I1 => \^rb_hit_busies.rb_hit_busies_r_lcl_reg[6]_1\,
      I2 => \ras_timer_r_reg[0]\,
      O => D(0)
    );
\ras_timer_r[0]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"B8BBB888B888B888"
    )
        port map (
      I0 => \ras_timer_r_reg[0]_4\,
      I1 => \^rb_hit_busies.rb_hit_busies_r_lcl_reg[6]_0\,
      I2 => \ras_timer_r_reg[0]_5\,
      I3 => \^rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_0\,
      I4 => \ras_timer_r_reg[0]_6\,
      I5 => rb_hit_busies_r_0(4),
      O => \ras_timer_r[0]_i_2_n_0\
    );
\ras_timer_r[1]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \ras_timer_r[1]_i_2_n_0\,
      I1 => \^rb_hit_busies.rb_hit_busies_r_lcl_reg[6]_1\,
      I2 => \ras_timer_r_reg[1]\,
      O => D(1)
    );
\ras_timer_r[1]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"B8BBB888B888B888"
    )
        port map (
      I0 => \ras_timer_r_reg[1]_0\,
      I1 => \^rb_hit_busies.rb_hit_busies_r_lcl_reg[6]_0\,
      I2 => \ras_timer_r_reg[1]_1\,
      I3 => \^rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_0\,
      I4 => \ras_timer_r_reg[1]_2\,
      I5 => rb_hit_busies_r_0(4),
      O => \ras_timer_r[1]_i_2_n_0\
    );
\rb_hit_busies.rb_hit_busies_r_lcl[4]_i_1__1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F022"
    )
        port map (
      I0 => \rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_1\,
      I1 => \rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_2\,
      I2 => rb_hit_busies_r_0(4),
      I3 => \^idle_r_lcl_reg_1\,
      O => \rb_hit_busies.rb_hit_busies_r_lcl[4]_i_1__1_n_0\
    );
\rb_hit_busies.rb_hit_busies_r_lcl[5]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F022"
    )
        port map (
      I0 => \rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_1\,
      I1 => \rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_2\,
      I2 => \^rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_0\,
      I3 => \^idle_r_lcl_reg_1\,
      O => \rb_hit_busies.rb_hit_busies_r_lcl[5]_i_1_n_0\
    );
\rb_hit_busies.rb_hit_busies_r_lcl[6]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F022"
    )
        port map (
      I0 => \rb_hit_busies.rb_hit_busies_r_lcl_reg[6]_2\,
      I1 => \rb_hit_busies.rb_hit_busies_r_lcl_reg[6]_3\,
      I2 => \^rb_hit_busies.rb_hit_busies_r_lcl_reg[6]_0\,
      I3 => \^idle_r_lcl_reg_1\,
      O => \rb_hit_busies.rb_hit_busies_r_lcl[6]_i_1_n_0\
    );
\rb_hit_busies.rb_hit_busies_r_lcl_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \order_q_r_reg[1]_0\,
      CE => '1',
      D => \rb_hit_busies.rb_hit_busies_r_lcl[4]_i_1__1_n_0\,
      Q => rb_hit_busies_r_0(4),
      R => \rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_3\
    );
\rb_hit_busies.rb_hit_busies_r_lcl_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \order_q_r_reg[1]_0\,
      CE => '1',
      D => \rb_hit_busies.rb_hit_busies_r_lcl[5]_i_1_n_0\,
      Q => \^rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_0\,
      R => \rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_3\
    );
\rb_hit_busies.rb_hit_busies_r_lcl_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \order_q_r_reg[1]_0\,
      CE => '1',
      D => \rb_hit_busies.rb_hit_busies_r_lcl[6]_i_1_n_0\,
      Q => \^rb_hit_busies.rb_hit_busies_r_lcl_reg[6]_0\,
      R => \rb_hit_busies.rb_hit_busies_r_lcl_reg[6]_4\
    );
\rb_hit_busy_r_i_1__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \^idle_r_lcl_reg_1\,
      I1 => rb_hit_busy_r_reg,
      O => p_28_out
    );
req_bank_rdy_r_i_1: unisim.vcomponents.LUT4
    generic map(
      INIT => X"00A2"
    )
        port map (
      I0 => req_bank_rdy_r_reg,
      I1 => order_q_r(0),
      I2 => req_bank_rdy_r_reg_0,
      I3 => order_q_r(1),
      O => req_bank_rdy_ns
    );
wait_for_maint_r_lcl_reg: unisim.vcomponents.FDRE
     port map (
      C => \order_q_r_reg[1]_0\,
      CE => '1',
      D => wait_for_maint_r_lcl_reg_1,
      Q => \^wait_for_maint_r_15\,
      R => wait_for_maint_r_lcl_reg_0
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mig_mig_7series_v4_2_bank_state is
  port (
    act_wait_r_lcl_reg_0 : out STD_LOGIC;
    ras_timer_zero_r : out STD_LOGIC;
    pre_wait_r : out STD_LOGIC;
    col_wait_r_reg_0 : out STD_LOGIC;
    act_this_rank_r : out STD_LOGIC_VECTOR ( 0 to 0 );
    demand_priority_r_reg_0 : out STD_LOGIC;
    demanded_prior_r_reg_0 : out STD_LOGIC;
    ofs_rdy_r : out STD_LOGIC;
    wr_this_rank_r : out STD_LOGIC_VECTOR ( 0 to 0 );
    rd_this_rank_r : out STD_LOGIC_VECTOR ( 0 to 0 );
    rnk_config_valid_r_lcl_reg : out STD_LOGIC;
    pre_bm_end_ns : out STD_LOGIC;
    pre_passing_open_bank_ns : out STD_LOGIC;
    bm_end_r1_reg_0 : out STD_LOGIC;
    bm_end_r1_reg_1 : out STD_LOGIC;
    auto_pre_r_lcl_reg : out STD_LOGIC;
    demand_priority_r_reg_1 : out STD_LOGIC;
    demanded_prior_r_reg_1 : out STD_LOGIC;
    ofs_rdy_r0 : out STD_LOGIC;
    ofs_rdy_r0_0 : out STD_LOGIC;
    ofs_rdy_r0_1 : out STD_LOGIC;
    bm_end_r1_reg_2 : in STD_LOGIC;
    ofs_rdy_r_reg_0 : in STD_LOGIC;
    col_wait_r_reg_1 : in STD_LOGIC;
    req_bank_rdy_ns_0 : in STD_LOGIC;
    phy_mc_ctl_full_r_reg_0 : in STD_LOGIC;
    phy_mc_ctl_full : in STD_LOGIC;
    phy_mc_cmd_full_r_reg_0 : in STD_LOGIC;
    of_ctl_full_v : in STD_LOGIC_VECTOR ( 0 to 0 );
    start_wtp_timer0 : in STD_LOGIC;
    \rd_this_rank_r_reg[0]_0\ : in STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 1 downto 0 );
    pass_open_bank_r : in STD_LOGIC;
    \rtp_timer_r_reg[1]_0\ : in STD_LOGIC;
    act_wait_r_lcl_reg_1 : in STD_LOGIC;
    pre_wait_r_reg_0 : in STD_LOGIC;
    demand_priority_r_reg_2 : in STD_LOGIC;
    demand_priority_r_reg_3 : in STD_LOGIC;
    req_bank_rdy_ns : in STD_LOGIC;
    rnk_config_valid_r : in STD_LOGIC;
    override_demand_ns : in STD_LOGIC;
    \rnk_config_strobe_r_reg[0]\ : in STD_LOGIC;
    pre_bm_end_r_reg : in STD_LOGIC_VECTOR ( 0 to 0 );
    pre_bm_end_r_reg_0 : in STD_LOGIC;
    pass_open_bank_ns : in STD_LOGIC;
    ras_timer_zero_r_reg_0 : in STD_LOGIC;
    pre_wait_r_reg_1 : in STD_LOGIC;
    demanded_prior_r_reg_2 : in STD_LOGIC;
    \grant_r[2]_i_3\ : in STD_LOGIC;
    override_demand_r : in STD_LOGIC;
    \grant_r[2]_i_3_0\ : in STD_LOGIC;
    \ras_timer_r[1]_i_3_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    demanded_prior_r_reg_3 : in STD_LOGIC;
    demanded_prior_r : in STD_LOGIC;
    demand_priority_r_reg_4 : in STD_LOGIC;
    req_wr_r : in STD_LOGIC_VECTOR ( 0 to 0 );
    q_has_rd : in STD_LOGIC;
    phy_mc_data_full : in STD_LOGIC;
    ofs_rdy_r_reg_1 : in STD_LOGIC;
    ofs_rdy_r_reg_2 : in STD_LOGIC;
    ofs_rdy_r_reg_3 : in STD_LOGIC;
    \rtp_timer_r_reg[0]_0\ : in STD_LOGIC;
    D : in STD_LOGIC_VECTOR ( 1 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of mig_mig_7series_v4_2_bank_state : entity is "mig_7series_v4_2_bank_state";
end mig_mig_7series_v4_2_bank_state;

architecture STRUCTURE of mig_mig_7series_v4_2_bank_state is
  signal act_wait_ns : STD_LOGIC;
  signal \^act_wait_r_lcl_reg_0\ : STD_LOGIC;
  signal \bank_cntrl[3].bank0/bank_state0/phy_mc_cmd_full_r\ : STD_LOGIC;
  signal \bank_cntrl[3].bank0/bank_state0/phy_mc_ctl_full_r\ : STD_LOGIC;
  signal bm_end_r1 : STD_LOGIC;
  signal \^bm_end_r1_reg_0\ : STD_LOGIC;
  signal \^bm_end_r1_reg_1\ : STD_LOGIC;
  signal \^col_wait_r_reg_0\ : STD_LOGIC;
  signal demand_priority_ns : STD_LOGIC;
  signal demand_priority_r_i_3_n_0 : STD_LOGIC;
  signal demand_priority_r_i_4_n_0 : STD_LOGIC;
  signal \^demand_priority_r_reg_0\ : STD_LOGIC;
  signal demanded_prior_ns : STD_LOGIC;
  signal \^demanded_prior_r_reg_0\ : STD_LOGIC;
  signal \i___40_i_4_n_0\ : STD_LOGIC;
  signal ofs_rdy_r0_2 : STD_LOGIC;
  signal \^pre_passing_open_bank_ns\ : STD_LOGIC;
  signal pre_wait_ns : STD_LOGIC;
  signal \^pre_wait_r\ : STD_LOGIC;
  signal pre_wait_r_i_2_n_0 : STD_LOGIC;
  signal ras_timer_r : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \ras_timer_r[1]_i_4_n_0\ : STD_LOGIC;
  signal ras_timer_zero_ns : STD_LOGIC;
  signal \^ras_timer_zero_r\ : STD_LOGIC;
  signal req_bank_rdy_r : STD_LOGIC;
  signal rtp_timer_r : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \rtp_timer_r[0]_i_1_n_0\ : STD_LOGIC;
  signal \rtp_timer_r[1]_i_1_n_0\ : STD_LOGIC;
  signal starve_limit_cntr_r : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal starve_limit_cntr_r0 : STD_LOGIC;
  signal \starve_limit_cntr_r[0]_i_1_n_0\ : STD_LOGIC;
  signal \starve_limit_cntr_r[1]_i_1_n_0\ : STD_LOGIC;
  signal \starve_limit_cntr_r[2]_i_1_n_0\ : STD_LOGIC;
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of demand_priority_r_i_4 : label is "soft_lutpair1163";
  attribute SOFT_HLUTNM of \grant_r[2]_i_3__0\ : label is "soft_lutpair1159";
  attribute SOFT_HLUTNM of ofs_rdy_r_i_1 : label is "soft_lutpair1161";
  attribute SOFT_HLUTNM of \ofs_rdy_r_i_1__0\ : label is "soft_lutpair1161";
  attribute SOFT_HLUTNM of \ofs_rdy_r_i_1__1\ : label is "soft_lutpair1162";
  attribute SOFT_HLUTNM of \ofs_rdy_r_i_1__2\ : label is "soft_lutpair1162";
  attribute SOFT_HLUTNM of \pre_bm_end_r_i_1__0\ : label is "soft_lutpair1159";
  attribute SOFT_HLUTNM of \starve_limit_cntr_r[0]_i_1\ : label is "soft_lutpair1163";
  attribute SOFT_HLUTNM of \starve_limit_cntr_r[1]_i_1\ : label is "soft_lutpair1160";
  attribute SOFT_HLUTNM of \starve_limit_cntr_r[2]_i_1\ : label is "soft_lutpair1160";
begin
  act_wait_r_lcl_reg_0 <= \^act_wait_r_lcl_reg_0\;
  bm_end_r1_reg_0 <= \^bm_end_r1_reg_0\;
  bm_end_r1_reg_1 <= \^bm_end_r1_reg_1\;
  col_wait_r_reg_0 <= \^col_wait_r_reg_0\;
  demand_priority_r_reg_0 <= \^demand_priority_r_reg_0\;
  demanded_prior_r_reg_0 <= \^demanded_prior_r_reg_0\;
  pre_passing_open_bank_ns <= \^pre_passing_open_bank_ns\;
  pre_wait_r <= \^pre_wait_r\;
  ras_timer_zero_r <= \^ras_timer_zero_r\;
\act_this_rank_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => ofs_rdy_r_reg_0,
      CE => '1',
      D => \^act_wait_r_lcl_reg_0\,
      Q => act_this_rank_r(0),
      R => '0'
    );
\act_wait_r_lcl_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFF888"
    )
        port map (
      I0 => \^act_wait_r_lcl_reg_0\,
      I1 => act_wait_r_lcl_reg_1,
      I2 => pass_open_bank_r,
      I3 => bm_end_r1_reg_2,
      I4 => pre_wait_r_reg_0,
      I5 => bm_end_r1,
      O => act_wait_ns
    );
act_wait_r_lcl_reg: unisim.vcomponents.FDRE
     port map (
      C => ofs_rdy_r_reg_0,
      CE => '1',
      D => act_wait_ns,
      Q => \^act_wait_r_lcl_reg_0\,
      R => '0'
    );
bm_end_r1_reg: unisim.vcomponents.FDRE
     port map (
      C => ofs_rdy_r_reg_0,
      CE => '1',
      D => bm_end_r1_reg_2,
      Q => bm_end_r1,
      R => '0'
    );
col_wait_r_reg: unisim.vcomponents.FDRE
     port map (
      C => ofs_rdy_r_reg_0,
      CE => '1',
      D => col_wait_r_reg_1,
      Q => \^col_wait_r_reg_0\,
      R => '0'
    );
\demand_priority_r_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888808"
    )
        port map (
      I0 => col_wait_r_reg_1,
      I1 => demand_priority_r_reg_2,
      I2 => demand_priority_r_reg_3,
      I3 => demand_priority_r_i_3_n_0,
      I4 => \^demand_priority_r_reg_0\,
      O => demand_priority_ns
    );
demand_priority_r_i_3: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000040400040"
    )
        port map (
      I0 => Q(0),
      I1 => demand_priority_r_reg_4,
      I2 => req_bank_rdy_r,
      I3 => req_wr_r(0),
      I4 => q_has_rd,
      I5 => demand_priority_r_i_4_n_0,
      O => demand_priority_r_i_3_n_0
    );
demand_priority_r_i_4: unisim.vcomponents.LUT3
    generic map(
      INIT => X"7F"
    )
        port map (
      I0 => starve_limit_cntr_r(2),
      I1 => starve_limit_cntr_r(1),
      I2 => starve_limit_cntr_r(0),
      O => demand_priority_r_i_4_n_0
    );
demand_priority_r_reg: unisim.vcomponents.FDRE
     port map (
      C => ofs_rdy_r_reg_0,
      CE => '1',
      D => demand_priority_ns,
      Q => \^demand_priority_r_reg_0\,
      R => '0'
    );
\demanded_prior_r_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"D0D0D0D0D0DDD0D0"
    )
        port map (
      I0 => \^demand_priority_r_reg_0\,
      I1 => \^demanded_prior_r_reg_0\,
      I2 => demanded_prior_r_reg_2,
      I3 => Q(1),
      I4 => demanded_prior_r_reg_3,
      I5 => demanded_prior_r,
      O => demanded_prior_ns
    );
demanded_prior_r_reg: unisim.vcomponents.FDRE
     port map (
      C => ofs_rdy_r_reg_0,
      CE => '1',
      D => demanded_prior_ns,
      Q => \^demanded_prior_r_reg_0\,
      R => '0'
    );
\grant_r[2]_i_3__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"1000"
    )
        port map (
      I0 => pre_bm_end_r_reg_0,
      I1 => pre_bm_end_r_reg(0),
      I2 => \^pre_wait_r\,
      I3 => \^ras_timer_zero_r\,
      O => auto_pre_r_lcl_reg
    );
\grant_r[2]_i_4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFF0045"
    )
        port map (
      I0 => \^demand_priority_r_reg_0\,
      I1 => demanded_prior_r_reg_2,
      I2 => \grant_r[2]_i_3\,
      I3 => override_demand_r,
      I4 => \grant_r[2]_i_3_0\,
      O => demand_priority_r_reg_1
    );
\i___40_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"000F000800080008"
    )
        port map (
      I0 => \i___40_i_4_n_0\,
      I1 => req_bank_rdy_ns,
      I2 => rnk_config_valid_r,
      I3 => override_demand_ns,
      I4 => \rnk_config_strobe_r_reg[0]\,
      I5 => req_bank_rdy_ns_0,
      O => rnk_config_valid_r_lcl_reg
    );
\i___40_i_4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"BBBBBABB"
    )
        port map (
      I0 => demanded_prior_r_reg_3,
      I1 => demanded_prior_r_reg_2,
      I2 => Q(0),
      I3 => \^demand_priority_r_reg_0\,
      I4 => \^demanded_prior_r_reg_0\,
      O => \i___40_i_4_n_0\
    );
\i___85_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FBFBFBFBFB00FBFB"
    )
        port map (
      I0 => \^demanded_prior_r_reg_0\,
      I1 => \^demand_priority_r_reg_0\,
      I2 => Q(0),
      I3 => demanded_prior_r,
      I4 => demanded_prior_r_reg_3,
      I5 => Q(1),
      O => demanded_prior_r_reg_1
    );
ofs_rdy_r_i_1: unisim.vcomponents.LUT4
    generic map(
      INIT => X"1011"
    )
        port map (
      I0 => \bank_cntrl[3].bank0/bank_state0/phy_mc_cmd_full_r\,
      I1 => \bank_cntrl[3].bank0/bank_state0/phy_mc_ctl_full_r\,
      I2 => \rd_this_rank_r_reg[0]_0\,
      I3 => phy_mc_data_full,
      O => ofs_rdy_r0_2
    );
\ofs_rdy_r_i_1__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"1011"
    )
        port map (
      I0 => \bank_cntrl[3].bank0/bank_state0/phy_mc_cmd_full_r\,
      I1 => \bank_cntrl[3].bank0/bank_state0/phy_mc_ctl_full_r\,
      I2 => ofs_rdy_r_reg_1,
      I3 => phy_mc_data_full,
      O => ofs_rdy_r0
    );
\ofs_rdy_r_i_1__1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"1011"
    )
        port map (
      I0 => \bank_cntrl[3].bank0/bank_state0/phy_mc_cmd_full_r\,
      I1 => \bank_cntrl[3].bank0/bank_state0/phy_mc_ctl_full_r\,
      I2 => ofs_rdy_r_reg_2,
      I3 => phy_mc_data_full,
      O => ofs_rdy_r0_0
    );
\ofs_rdy_r_i_1__2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"1011"
    )
        port map (
      I0 => \bank_cntrl[3].bank0/bank_state0/phy_mc_cmd_full_r\,
      I1 => \bank_cntrl[3].bank0/bank_state0/phy_mc_ctl_full_r\,
      I2 => ofs_rdy_r_reg_3,
      I3 => phy_mc_data_full,
      O => ofs_rdy_r0_1
    );
ofs_rdy_r_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => ofs_rdy_r_reg_0,
      CE => '1',
      D => ofs_rdy_r0_2,
      Q => ofs_rdy_r,
      R => phy_mc_cmd_full_r_reg_0
    );
phy_mc_cmd_full_r_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => ofs_rdy_r_reg_0,
      CE => '1',
      D => of_ctl_full_v(0),
      Q => \bank_cntrl[3].bank0/bank_state0/phy_mc_cmd_full_r\,
      R => phy_mc_cmd_full_r_reg_0
    );
phy_mc_ctl_full_r_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => ofs_rdy_r_reg_0,
      CE => '1',
      D => phy_mc_ctl_full,
      Q => \bank_cntrl[3].bank0/bank_state0/phy_mc_ctl_full_r\,
      R => phy_mc_ctl_full_r_reg_0
    );
\pre_bm_end_r_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"EAEAEAAA"
    )
        port map (
      I0 => \^pre_passing_open_bank_ns\,
      I1 => \^ras_timer_zero_r\,
      I2 => \^pre_wait_r\,
      I3 => pre_bm_end_r_reg(0),
      I4 => pre_bm_end_r_reg_0,
      O => pre_bm_end_ns
    );
\pre_passing_open_bank_r_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAA8AAAAAAA8AAA8"
    )
        port map (
      I0 => pass_open_bank_ns,
      I1 => Q(0),
      I2 => rtp_timer_r(0),
      I3 => rtp_timer_r(1),
      I4 => \^ras_timer_zero_r\,
      I5 => \^pre_wait_r\,
      O => \^pre_passing_open_bank_ns\
    );
\pre_wait_r_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"4444444444454444"
    )
        port map (
      I0 => pass_open_bank_ns,
      I1 => pre_wait_r_i_2_n_0,
      I2 => pass_open_bank_r,
      I3 => pre_wait_r_reg_0,
      I4 => rtp_timer_r(0),
      I5 => rtp_timer_r(1),
      O => pre_wait_ns
    );
pre_wait_r_i_2: unisim.vcomponents.LUT5
    generic map(
      INIT => X"10101050"
    )
        port map (
      I0 => pre_wait_r_reg_1,
      I1 => \^ras_timer_zero_r\,
      I2 => \^pre_wait_r\,
      I3 => pre_bm_end_r_reg(0),
      I4 => pre_bm_end_r_reg_0,
      O => pre_wait_r_i_2_n_0
    );
pre_wait_r_reg: unisim.vcomponents.FDRE
     port map (
      C => ofs_rdy_r_reg_0,
      CE => '1',
      D => pre_wait_ns,
      Q => \^pre_wait_r\,
      R => '0'
    );
\ras_timer_r[0]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0010111100100010"
    )
        port map (
      I0 => bm_end_r1,
      I1 => pre_wait_r_reg_0,
      I2 => ras_timer_r(1),
      I3 => ras_timer_r(0),
      I4 => \rd_this_rank_r_reg[0]_0\,
      I5 => Q(0),
      O => \^bm_end_r1_reg_1\
    );
\ras_timer_r[1]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"1010010011111111"
    )
        port map (
      I0 => bm_end_r1,
      I1 => pre_wait_r_reg_0,
      I2 => ras_timer_r(1),
      I3 => \ras_timer_r[1]_i_4_n_0\,
      I4 => ras_timer_r(0),
      I5 => ras_timer_zero_r_reg_0,
      O => \^bm_end_r1_reg_0\
    );
\ras_timer_r[1]_i_4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^act_wait_r_lcl_reg_0\,
      I1 => \ras_timer_r[1]_i_3_0\(0),
      O => \ras_timer_r[1]_i_4_n_0\
    );
\ras_timer_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => ofs_rdy_r_reg_0,
      CE => '1',
      D => D(0),
      Q => ras_timer_r(0),
      R => '0'
    );
\ras_timer_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => ofs_rdy_r_reg_0,
      CE => '1',
      D => D(1),
      Q => ras_timer_r(1),
      R => '0'
    );
ras_timer_zero_r_i_1: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \^bm_end_r1_reg_0\,
      I1 => \^bm_end_r1_reg_1\,
      O => ras_timer_zero_ns
    );
ras_timer_zero_r_reg: unisim.vcomponents.FDRE
     port map (
      C => ofs_rdy_r_reg_0,
      CE => '1',
      D => ras_timer_zero_ns,
      Q => \^ras_timer_zero_r\,
      R => '0'
    );
\rd_this_rank_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => ofs_rdy_r_reg_0,
      CE => '1',
      D => \rd_this_rank_r_reg[0]_0\,
      Q => rd_this_rank_r(0),
      R => '0'
    );
req_bank_rdy_r_reg: unisim.vcomponents.FDRE
     port map (
      C => ofs_rdy_r_reg_0,
      CE => '1',
      D => req_bank_rdy_ns_0,
      Q => req_bank_rdy_r,
      R => '0'
    );
\rtp_timer_r[0]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0010"
    )
        port map (
      I0 => \rtp_timer_r_reg[0]_0\,
      I1 => pass_open_bank_r,
      I2 => rtp_timer_r(1),
      I3 => rtp_timer_r(0),
      O => \rtp_timer_r[0]_i_1_n_0\
    );
\rtp_timer_r[1]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"000000C2"
    )
        port map (
      I0 => Q(0),
      I1 => rtp_timer_r(0),
      I2 => rtp_timer_r(1),
      I3 => pass_open_bank_r,
      I4 => \rtp_timer_r_reg[1]_0\,
      O => \rtp_timer_r[1]_i_1_n_0\
    );
\rtp_timer_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => ofs_rdy_r_reg_0,
      CE => '1',
      D => \rtp_timer_r[0]_i_1_n_0\,
      Q => rtp_timer_r(0),
      R => '0'
    );
\rtp_timer_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => ofs_rdy_r_reg_0,
      CE => '1',
      D => \rtp_timer_r[1]_i_1_n_0\,
      Q => rtp_timer_r(1),
      R => '0'
    );
\starve_limit_cntr_r[0]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"60"
    )
        port map (
      I0 => starve_limit_cntr_r(0),
      I1 => starve_limit_cntr_r0,
      I2 => \^col_wait_r_reg_0\,
      O => \starve_limit_cntr_r[0]_i_1_n_0\
    );
\starve_limit_cntr_r[1]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6A00"
    )
        port map (
      I0 => starve_limit_cntr_r(1),
      I1 => starve_limit_cntr_r0,
      I2 => starve_limit_cntr_r(0),
      I3 => \^col_wait_r_reg_0\,
      O => \starve_limit_cntr_r[1]_i_1_n_0\
    );
\starve_limit_cntr_r[2]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"6AAA0000"
    )
        port map (
      I0 => starve_limit_cntr_r(2),
      I1 => starve_limit_cntr_r0,
      I2 => starve_limit_cntr_r(0),
      I3 => starve_limit_cntr_r(1),
      I4 => \^col_wait_r_reg_0\,
      O => \starve_limit_cntr_r[2]_i_1_n_0\
    );
\starve_limit_cntr_r[2]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"007F000000000000"
    )
        port map (
      I0 => starve_limit_cntr_r(0),
      I1 => starve_limit_cntr_r(1),
      I2 => starve_limit_cntr_r(2),
      I3 => Q(0),
      I4 => demand_priority_r_reg_4,
      I5 => req_bank_rdy_r,
      O => starve_limit_cntr_r0
    );
\starve_limit_cntr_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => ofs_rdy_r_reg_0,
      CE => '1',
      D => \starve_limit_cntr_r[0]_i_1_n_0\,
      Q => starve_limit_cntr_r(0),
      R => '0'
    );
\starve_limit_cntr_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => ofs_rdy_r_reg_0,
      CE => '1',
      D => \starve_limit_cntr_r[1]_i_1_n_0\,
      Q => starve_limit_cntr_r(1),
      R => '0'
    );
\starve_limit_cntr_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => ofs_rdy_r_reg_0,
      CE => '1',
      D => \starve_limit_cntr_r[2]_i_1_n_0\,
      Q => starve_limit_cntr_r(2),
      R => '0'
    );
\wr_this_rank_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => ofs_rdy_r_reg_0,
      CE => '1',
      D => start_wtp_timer0,
      Q => wr_this_rank_r(0),
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \mig_mig_7series_v4_2_bank_state__parameterized0\ is
  port (
    act_wait_r_lcl_reg_0 : out STD_LOGIC;
    act_this_rank_r : out STD_LOGIC_VECTOR ( 0 to 0 );
    wr_this_rank_r : out STD_LOGIC_VECTOR ( 0 to 0 );
    rd_this_rank_r : out STD_LOGIC_VECTOR ( 0 to 0 );
    bm_end_r1 : out STD_LOGIC;
    ras_timer_zero_r : out STD_LOGIC;
    pre_wait_r : out STD_LOGIC;
    col_wait_r_reg_0 : out STD_LOGIC;
    req_bank_rdy_r : out STD_LOGIC;
    demand_priority_r_reg_0 : out STD_LOGIC;
    demanded_prior_r_reg_0 : out STD_LOGIC;
    ofs_rdy_r : out STD_LOGIC;
    pre_bm_end_ns : out STD_LOGIC;
    pre_passing_open_bank_ns : out STD_LOGIC;
    rnk_config_strobe_ns : out STD_LOGIC;
    demand_priority_r_reg_1 : out STD_LOGIC;
    auto_pre_r_lcl_reg : out STD_LOGIC;
    \ras_timer_r_reg[1]_0\ : out STD_LOGIC;
    bm_end_r1_reg_0 : out STD_LOGIC;
    demanded_prior_r_reg_1 : out STD_LOGIC;
    demand_priority_r_reg_2 : in STD_LOGIC;
    start_wtp_timer0 : in STD_LOGIC;
    \rd_this_rank_r_reg[0]_0\ : in STD_LOGIC;
    p_91_out : in STD_LOGIC;
    col_wait_r_reg_1 : in STD_LOGIC;
    req_bank_rdy_ns : in STD_LOGIC;
    ofs_rdy_r_reg_0 : in STD_LOGIC;
    ofs_rdy_r0 : in STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \rtp_timer_r_reg[1]_0\ : in STD_LOGIC;
    \rtp_timer_r_reg[1]_1\ : in STD_LOGIC;
    demand_priority_r_reg_3 : in STD_LOGIC;
    demand_priority_r_reg_4 : in STD_LOGIC;
    pre_bm_end_r_reg : in STD_LOGIC_VECTOR ( 0 to 0 );
    pre_bm_end_r_reg_0 : in STD_LOGIC;
    pass_open_bank_ns : in STD_LOGIC;
    act_wait_r_lcl_reg_1 : in STD_LOGIC;
    act_wait_r_lcl_reg_2 : in STD_LOGIC;
    \rnk_config_strobe_r_reg[0]\ : in STD_LOGIC;
    req_bank_rdy_ns_1 : in STD_LOGIC;
    \rnk_config_strobe_r_reg[0]_0\ : in STD_LOGIC;
    \rnk_config_strobe_r_reg[0]_1\ : in STD_LOGIC;
    act_wait_r_lcl_reg_3 : in STD_LOGIC_VECTOR ( 0 to 0 );
    act_wait_r_lcl_reg_4 : in STD_LOGIC;
    ras_timer_zero_r_reg_0 : in STD_LOGIC;
    ras_timer_zero_r_reg_1 : in STD_LOGIC;
    demanded_prior_r_reg_2 : in STD_LOGIC;
    demanded_prior_r_reg_3 : in STD_LOGIC;
    demanded_prior_r_reg_4 : in STD_LOGIC;
    demand_priority_r_reg_5 : in STD_LOGIC;
    q_has_rd_3 : in STD_LOGIC;
    demand_priority_r_reg_6 : in STD_LOGIC;
    \starve_limit_cntr_r_reg[0]_0\ : in STD_LOGIC;
    \rtp_timer_r_reg[0]_0\ : in STD_LOGIC;
    D : in STD_LOGIC_VECTOR ( 1 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \mig_mig_7series_v4_2_bank_state__parameterized0\ : entity is "mig_7series_v4_2_bank_state";
end \mig_mig_7series_v4_2_bank_state__parameterized0\;

architecture STRUCTURE of \mig_mig_7series_v4_2_bank_state__parameterized0\ is
  signal act_wait_ns : STD_LOGIC;
  signal \act_wait_r_lcl_i_2__1_n_0\ : STD_LOGIC;
  signal \^act_wait_r_lcl_reg_0\ : STD_LOGIC;
  signal \^bm_end_r1\ : STD_LOGIC;
  signal \^bm_end_r1_reg_0\ : STD_LOGIC;
  signal \^col_wait_r_reg_0\ : STD_LOGIC;
  signal demand_priority_ns : STD_LOGIC;
  signal \demand_priority_r_i_3__0_n_0\ : STD_LOGIC;
  signal \^demand_priority_r_reg_0\ : STD_LOGIC;
  signal \^demand_priority_r_reg_1\ : STD_LOGIC;
  signal demanded_prior_ns : STD_LOGIC;
  signal \^demanded_prior_r_reg_0\ : STD_LOGIC;
  signal \^pre_passing_open_bank_ns\ : STD_LOGIC;
  signal pre_wait_ns : STD_LOGIC;
  signal \^pre_wait_r\ : STD_LOGIC;
  signal \pre_wait_r_i_2__0_n_0\ : STD_LOGIC;
  signal \ras_timer_r[1]_i_5__0_n_0\ : STD_LOGIC;
  signal \^ras_timer_r_reg[1]_0\ : STD_LOGIC;
  signal \ras_timer_r_reg_n_0_[0]\ : STD_LOGIC;
  signal \ras_timer_r_reg_n_0_[1]\ : STD_LOGIC;
  signal \^ras_timer_zero_r\ : STD_LOGIC;
  signal \ras_timer_zero_r_i_1__0_n_0\ : STD_LOGIC;
  signal \^req_bank_rdy_r\ : STD_LOGIC;
  signal rtp_timer_r : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \rtp_timer_r[0]_i_1__0_n_0\ : STD_LOGIC;
  signal \rtp_timer_r[1]_i_1__0_n_0\ : STD_LOGIC;
  signal starve_limit_cntr_r : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal starve_limit_cntr_r0 : STD_LOGIC;
  signal \starve_limit_cntr_r[0]_i_1_n_0\ : STD_LOGIC;
  signal \starve_limit_cntr_r[1]_i_1_n_0\ : STD_LOGIC;
  signal \starve_limit_cntr_r[2]_i_1_n_0\ : STD_LOGIC;
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \act_wait_r_lcl_i_2__1\ : label is "soft_lutpair1171";
  attribute SOFT_HLUTNM of \grant_r[3]_i_3__1\ : label is "soft_lutpair1169";
  attribute SOFT_HLUTNM of pre_bm_end_r_i_1 : label is "soft_lutpair1169";
  attribute SOFT_HLUTNM of \ras_timer_r[1]_i_5__0\ : label is "soft_lutpair1171";
  attribute SOFT_HLUTNM of \starve_limit_cntr_r[1]_i_1\ : label is "soft_lutpair1170";
  attribute SOFT_HLUTNM of \starve_limit_cntr_r[2]_i_1\ : label is "soft_lutpair1170";
begin
  act_wait_r_lcl_reg_0 <= \^act_wait_r_lcl_reg_0\;
  bm_end_r1 <= \^bm_end_r1\;
  bm_end_r1_reg_0 <= \^bm_end_r1_reg_0\;
  col_wait_r_reg_0 <= \^col_wait_r_reg_0\;
  demand_priority_r_reg_0 <= \^demand_priority_r_reg_0\;
  demand_priority_r_reg_1 <= \^demand_priority_r_reg_1\;
  demanded_prior_r_reg_0 <= \^demanded_prior_r_reg_0\;
  pre_passing_open_bank_ns <= \^pre_passing_open_bank_ns\;
  pre_wait_r <= \^pre_wait_r\;
  \ras_timer_r_reg[1]_0\ <= \^ras_timer_r_reg[1]_0\;
  ras_timer_zero_r <= \^ras_timer_zero_r\;
  req_bank_rdy_r <= \^req_bank_rdy_r\;
\act_this_rank_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => demand_priority_r_reg_2,
      CE => '1',
      D => \^act_wait_r_lcl_reg_0\,
      Q => act_this_rank_r(0),
      R => '0'
    );
\act_wait_r_lcl_i_1__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFF88F8"
    )
        port map (
      I0 => \^act_wait_r_lcl_reg_0\,
      I1 => \act_wait_r_lcl_i_2__1_n_0\,
      I2 => \rtp_timer_r_reg[1]_0\,
      I3 => act_wait_r_lcl_reg_2,
      I4 => act_wait_r_lcl_reg_1,
      I5 => \^bm_end_r1\,
      O => act_wait_ns
    );
\act_wait_r_lcl_i_2__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"07"
    )
        port map (
      I0 => act_wait_r_lcl_reg_3(0),
      I1 => \^act_wait_r_lcl_reg_0\,
      I2 => act_wait_r_lcl_reg_4,
      O => \act_wait_r_lcl_i_2__1_n_0\
    );
act_wait_r_lcl_reg: unisim.vcomponents.FDRE
     port map (
      C => demand_priority_r_reg_2,
      CE => '1',
      D => act_wait_ns,
      Q => \^act_wait_r_lcl_reg_0\,
      R => '0'
    );
bm_end_r1_reg: unisim.vcomponents.FDRE
     port map (
      C => demand_priority_r_reg_2,
      CE => '1',
      D => p_91_out,
      Q => \^bm_end_r1\,
      R => '0'
    );
col_wait_r_reg: unisim.vcomponents.FDRE
     port map (
      C => demand_priority_r_reg_2,
      CE => '1',
      D => col_wait_r_reg_1,
      Q => \^col_wait_r_reg_0\,
      R => '0'
    );
\demand_priority_r_i_1__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888808"
    )
        port map (
      I0 => col_wait_r_reg_1,
      I1 => demand_priority_r_reg_3,
      I2 => demand_priority_r_reg_4,
      I3 => \demand_priority_r_i_3__0_n_0\,
      I4 => \^demand_priority_r_reg_0\,
      O => demand_priority_ns
    );
\demand_priority_r_i_3__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000080800080"
    )
        port map (
      I0 => starve_limit_cntr_r(0),
      I1 => starve_limit_cntr_r(1),
      I2 => starve_limit_cntr_r(2),
      I3 => demand_priority_r_reg_5,
      I4 => q_has_rd_3,
      I5 => demand_priority_r_reg_6,
      O => \demand_priority_r_i_3__0_n_0\
    );
demand_priority_r_reg: unisim.vcomponents.FDRE
     port map (
      C => demand_priority_r_reg_2,
      CE => '1',
      D => demand_priority_ns,
      Q => \^demand_priority_r_reg_0\,
      R => '0'
    );
\demanded_prior_r_i_1__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000D00DDDDDDDD"
    )
        port map (
      I0 => \^demand_priority_r_reg_0\,
      I1 => \^demanded_prior_r_reg_0\,
      I2 => Q(1),
      I3 => demanded_prior_r_reg_3,
      I4 => demanded_prior_r_reg_2,
      I5 => demanded_prior_r_reg_4,
      O => demanded_prior_ns
    );
demanded_prior_r_reg: unisim.vcomponents.FDRE
     port map (
      C => demand_priority_r_reg_2,
      CE => '1',
      D => demanded_prior_ns,
      Q => \^demanded_prior_r_reg_0\,
      R => '0'
    );
\grant_r[3]_i_3__1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"1000"
    )
        port map (
      I0 => pre_bm_end_r_reg_0,
      I1 => pre_bm_end_r_reg(0),
      I2 => \^pre_wait_r\,
      I3 => \^ras_timer_zero_r\,
      O => auto_pre_r_lcl_reg
    );
\i___84_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0404040404FF0404"
    )
        port map (
      I0 => \^demanded_prior_r_reg_0\,
      I1 => \^demand_priority_r_reg_0\,
      I2 => Q(0),
      I3 => demanded_prior_r_reg_2,
      I4 => demanded_prior_r_reg_3,
      I5 => Q(1),
      O => demanded_prior_r_reg_1
    );
ofs_rdy_r_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => demand_priority_r_reg_2,
      CE => '1',
      D => ofs_rdy_r0,
      Q => ofs_rdy_r,
      R => ofs_rdy_r_reg_0
    );
pre_bm_end_r_i_1: unisim.vcomponents.LUT5
    generic map(
      INIT => X"EAEAEAAA"
    )
        port map (
      I0 => \^pre_passing_open_bank_ns\,
      I1 => \^ras_timer_zero_r\,
      I2 => \^pre_wait_r\,
      I3 => pre_bm_end_r_reg(0),
      I4 => pre_bm_end_r_reg_0,
      O => pre_bm_end_ns
    );
pre_passing_open_bank_r_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAA8AAAAAAA8AAA8"
    )
        port map (
      I0 => pass_open_bank_ns,
      I1 => Q(0),
      I2 => rtp_timer_r(0),
      I3 => rtp_timer_r(1),
      I4 => \^ras_timer_zero_r\,
      I5 => \^pre_wait_r\,
      O => \^pre_passing_open_bank_ns\
    );
pre_wait_r_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"4444444444454444"
    )
        port map (
      I0 => pass_open_bank_ns,
      I1 => \pre_wait_r_i_2__0_n_0\,
      I2 => \rtp_timer_r_reg[1]_0\,
      I3 => act_wait_r_lcl_reg_1,
      I4 => rtp_timer_r(0),
      I5 => rtp_timer_r(1),
      O => pre_wait_ns
    );
\pre_wait_r_i_2__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"10101050"
    )
        port map (
      I0 => ras_timer_zero_r_reg_0,
      I1 => \^ras_timer_zero_r\,
      I2 => \^pre_wait_r\,
      I3 => pre_bm_end_r_reg(0),
      I4 => pre_bm_end_r_reg_0,
      O => \pre_wait_r_i_2__0_n_0\
    );
pre_wait_r_reg: unisim.vcomponents.FDRE
     port map (
      C => demand_priority_r_reg_2,
      CE => '1',
      D => pre_wait_ns,
      Q => \^pre_wait_r\,
      R => '0'
    );
\ras_timer_r[0]_i_3__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0010111100100010"
    )
        port map (
      I0 => \^bm_end_r1\,
      I1 => ras_timer_zero_r_reg_0,
      I2 => \ras_timer_r_reg_n_0_[1]\,
      I3 => \ras_timer_r_reg_n_0_[0]\,
      I4 => \rd_this_rank_r_reg[0]_0\,
      I5 => Q(0),
      O => \^bm_end_r1_reg_0\
    );
\ras_timer_r[1]_i_3__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"4410555544104410"
    )
        port map (
      I0 => ras_timer_zero_r_reg_1,
      I1 => \ras_timer_r_reg_n_0_[1]\,
      I2 => \ras_timer_r[1]_i_5__0_n_0\,
      I3 => \ras_timer_r_reg_n_0_[0]\,
      I4 => \rd_this_rank_r_reg[0]_0\,
      I5 => Q(0),
      O => \^ras_timer_r_reg[1]_0\
    );
\ras_timer_r[1]_i_5__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^act_wait_r_lcl_reg_0\,
      I1 => act_wait_r_lcl_reg_3(0),
      O => \ras_timer_r[1]_i_5__0_n_0\
    );
\ras_timer_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => demand_priority_r_reg_2,
      CE => '1',
      D => D(0),
      Q => \ras_timer_r_reg_n_0_[0]\,
      R => '0'
    );
\ras_timer_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => demand_priority_r_reg_2,
      CE => '1',
      D => D(1),
      Q => \ras_timer_r_reg_n_0_[1]\,
      R => '0'
    );
\ras_timer_zero_r_i_1__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \^ras_timer_r_reg[1]_0\,
      I1 => \^bm_end_r1_reg_0\,
      O => \ras_timer_zero_r_i_1__0_n_0\
    );
ras_timer_zero_r_reg: unisim.vcomponents.FDRE
     port map (
      C => demand_priority_r_reg_2,
      CE => '1',
      D => \ras_timer_zero_r_i_1__0_n_0\,
      Q => \^ras_timer_zero_r\,
      R => '0'
    );
\rd_this_rank_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => demand_priority_r_reg_2,
      CE => '1',
      D => \rd_this_rank_r_reg[0]_0\,
      Q => rd_this_rank_r(0),
      R => '0'
    );
req_bank_rdy_r_reg: unisim.vcomponents.FDRE
     port map (
      C => demand_priority_r_reg_2,
      CE => '1',
      D => req_bank_rdy_ns,
      Q => \^req_bank_rdy_r\,
      R => '0'
    );
\rnk_config_strobe_r[0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFF33202020"
    )
        port map (
      I0 => \^demand_priority_r_reg_1\,
      I1 => \rnk_config_strobe_r_reg[0]\,
      I2 => req_bank_rdy_ns_1,
      I3 => req_bank_rdy_ns,
      I4 => \rnk_config_strobe_r_reg[0]_0\,
      I5 => \rnk_config_strobe_r_reg[0]_1\,
      O => rnk_config_strobe_ns
    );
\rnk_config_strobe_r[0]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFEFAAAA"
    )
        port map (
      I0 => demanded_prior_r_reg_3,
      I1 => Q(0),
      I2 => \^demand_priority_r_reg_0\,
      I3 => \^demanded_prior_r_reg_0\,
      I4 => demanded_prior_r_reg_4,
      O => \^demand_priority_r_reg_1\
    );
\rtp_timer_r[0]_i_1__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0010"
    )
        port map (
      I0 => \rtp_timer_r_reg[0]_0\,
      I1 => \rtp_timer_r_reg[1]_0\,
      I2 => rtp_timer_r(1),
      I3 => rtp_timer_r(0),
      O => \rtp_timer_r[0]_i_1__0_n_0\
    );
\rtp_timer_r[1]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"000000C2"
    )
        port map (
      I0 => Q(0),
      I1 => rtp_timer_r(0),
      I2 => rtp_timer_r(1),
      I3 => \rtp_timer_r_reg[1]_0\,
      I4 => \rtp_timer_r_reg[1]_1\,
      O => \rtp_timer_r[1]_i_1__0_n_0\
    );
\rtp_timer_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => demand_priority_r_reg_2,
      CE => '1',
      D => \rtp_timer_r[0]_i_1__0_n_0\,
      Q => rtp_timer_r(0),
      R => '0'
    );
\rtp_timer_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => demand_priority_r_reg_2,
      CE => '1',
      D => \rtp_timer_r[1]_i_1__0_n_0\,
      Q => rtp_timer_r(1),
      R => '0'
    );
\starve_limit_cntr_r[0]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"60"
    )
        port map (
      I0 => starve_limit_cntr_r(0),
      I1 => starve_limit_cntr_r0,
      I2 => \^col_wait_r_reg_0\,
      O => \starve_limit_cntr_r[0]_i_1_n_0\
    );
\starve_limit_cntr_r[1]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6A00"
    )
        port map (
      I0 => starve_limit_cntr_r(1),
      I1 => starve_limit_cntr_r0,
      I2 => starve_limit_cntr_r(0),
      I3 => \^col_wait_r_reg_0\,
      O => \starve_limit_cntr_r[1]_i_1_n_0\
    );
\starve_limit_cntr_r[2]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"6AAA0000"
    )
        port map (
      I0 => starve_limit_cntr_r(2),
      I1 => starve_limit_cntr_r0,
      I2 => starve_limit_cntr_r(0),
      I3 => starve_limit_cntr_r(1),
      I4 => \^col_wait_r_reg_0\,
      O => \starve_limit_cntr_r[2]_i_1_n_0\
    );
\starve_limit_cntr_r[2]_i_2__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00007F0000000000"
    )
        port map (
      I0 => starve_limit_cntr_r(0),
      I1 => starve_limit_cntr_r(1),
      I2 => starve_limit_cntr_r(2),
      I3 => \starve_limit_cntr_r_reg[0]_0\,
      I4 => Q(0),
      I5 => \^req_bank_rdy_r\,
      O => starve_limit_cntr_r0
    );
\starve_limit_cntr_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => demand_priority_r_reg_2,
      CE => '1',
      D => \starve_limit_cntr_r[0]_i_1_n_0\,
      Q => starve_limit_cntr_r(0),
      R => '0'
    );
\starve_limit_cntr_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => demand_priority_r_reg_2,
      CE => '1',
      D => \starve_limit_cntr_r[1]_i_1_n_0\,
      Q => starve_limit_cntr_r(1),
      R => '0'
    );
\starve_limit_cntr_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => demand_priority_r_reg_2,
      CE => '1',
      D => \starve_limit_cntr_r[2]_i_1_n_0\,
      Q => starve_limit_cntr_r(2),
      R => '0'
    );
\wr_this_rank_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => demand_priority_r_reg_2,
      CE => '1',
      D => start_wtp_timer0,
      Q => wr_this_rank_r(0),
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \mig_mig_7series_v4_2_bank_state__parameterized1\ is
  port (
    act_wait_r_lcl_reg_0 : out STD_LOGIC;
    act_this_rank_r : out STD_LOGIC_VECTOR ( 0 to 0 );
    wr_this_rank_r : out STD_LOGIC_VECTOR ( 0 to 0 );
    rd_this_rank_r : out STD_LOGIC_VECTOR ( 0 to 0 );
    bm_end_r1_0 : out STD_LOGIC;
    ras_timer_zero_r : out STD_LOGIC;
    pre_wait_r : out STD_LOGIC;
    col_wait_r_reg_0 : out STD_LOGIC;
    demand_priority_r_reg_0 : out STD_LOGIC;
    demanded_prior_r_reg_0 : out STD_LOGIC;
    override_demand_r : out STD_LOGIC;
    ofs_rdy_r : out STD_LOGIC;
    pre_bm_end_ns : out STD_LOGIC;
    pre_passing_open_bank_ns : out STD_LOGIC;
    ras_timer_zero_r_reg_0 : out STD_LOGIC;
    auto_pre_r_lcl_reg : out STD_LOGIC;
    \ras_timer_r_reg[1]_0\ : out STD_LOGIC;
    bm_end_r1_reg_0 : out STD_LOGIC;
    demand_priority_r_reg_1 : out STD_LOGIC;
    act_wait_r_lcl_reg_1 : out STD_LOGIC;
    ofs_rdy_r_reg_0 : in STD_LOGIC;
    start_wtp_timer0 : in STD_LOGIC;
    \rd_this_rank_r_reg[0]_0\ : in STD_LOGIC;
    bm_end_r1_reg_1 : in STD_LOGIC;
    col_wait_r_reg_1 : in STD_LOGIC;
    req_bank_rdy_ns : in STD_LOGIC;
    override_demand_ns : in STD_LOGIC;
    ofs_rdy_r_reg_1 : in STD_LOGIC;
    ofs_rdy_r0 : in STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 1 downto 0 );
    pass_open_bank_r : in STD_LOGIC;
    pre_wait_r_reg_0 : in STD_LOGIC;
    demand_priority_r_reg_2 : in STD_LOGIC;
    demand_priority_r_reg_3 : in STD_LOGIC;
    act_wait_r_lcl_reg_2 : in STD_LOGIC_VECTOR ( 0 to 0 );
    act_wait_r_lcl_reg_3 : in STD_LOGIC;
    pre_bm_end_r_reg : in STD_LOGIC_VECTOR ( 1 downto 0 );
    pre_bm_end_r_reg_0 : in STD_LOGIC;
    pass_open_bank_ns : in STD_LOGIC;
    \pre_4_1_1T_arb.granted_pre_r_reg\ : in STD_LOGIC;
    ras_timer_zero_r_reg_1 : in STD_LOGIC;
    ras_timer_zero_r_reg_2 : in STD_LOGIC;
    demand_priority_r_1 : in STD_LOGIC;
    demanded_prior_r_reg_1 : in STD_LOGIC;
    demanded_prior_r_2 : in STD_LOGIC;
    \cmd_pipe_plus.mc_address_reg[38]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \cmd_pipe_plus.mc_address_reg[38]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    row_cmd_wr : in STD_LOGIC_VECTOR ( 0 to 0 );
    demand_priority_r_reg_4 : in STD_LOGIC;
    demand_priority_r_reg_5 : in STD_LOGIC;
    q_has_rd_7 : in STD_LOGIC;
    \rtp_timer_r_reg[0]_0\ : in STD_LOGIC;
    D : in STD_LOGIC_VECTOR ( 1 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \mig_mig_7series_v4_2_bank_state__parameterized1\ : entity is "mig_7series_v4_2_bank_state";
end \mig_mig_7series_v4_2_bank_state__parameterized1\;

architecture STRUCTURE of \mig_mig_7series_v4_2_bank_state__parameterized1\ is
  signal act_wait_ns : STD_LOGIC;
  signal \act_wait_r_lcl_i_2__0_n_0\ : STD_LOGIC;
  signal \^act_wait_r_lcl_reg_0\ : STD_LOGIC;
  signal \^bm_end_r1_0\ : STD_LOGIC;
  signal \^bm_end_r1_reg_0\ : STD_LOGIC;
  signal \^col_wait_r_reg_0\ : STD_LOGIC;
  signal demand_priority_ns : STD_LOGIC;
  signal \demand_priority_r_i_3__1_n_0\ : STD_LOGIC;
  signal \demand_priority_r_i_4__1_n_0\ : STD_LOGIC;
  signal \^demand_priority_r_reg_0\ : STD_LOGIC;
  signal demanded_prior_ns : STD_LOGIC;
  signal \^demanded_prior_r_reg_0\ : STD_LOGIC;
  signal \^pre_passing_open_bank_ns\ : STD_LOGIC;
  signal pre_wait_ns : STD_LOGIC;
  signal \^pre_wait_r\ : STD_LOGIC;
  signal \pre_wait_r_i_2__1_n_0\ : STD_LOGIC;
  signal \ras_timer_r[1]_i_5__1_n_0\ : STD_LOGIC;
  signal \^ras_timer_r_reg[1]_0\ : STD_LOGIC;
  signal \ras_timer_r_reg_n_0_[0]\ : STD_LOGIC;
  signal \ras_timer_r_reg_n_0_[1]\ : STD_LOGIC;
  signal \^ras_timer_zero_r\ : STD_LOGIC;
  signal \ras_timer_zero_r_i_1__1_n_0\ : STD_LOGIC;
  signal req_bank_rdy_r : STD_LOGIC;
  signal rtp_timer_r : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \rtp_timer_r[0]_i_1__1_n_0\ : STD_LOGIC;
  signal \rtp_timer_r[1]_i_1__1_n_0\ : STD_LOGIC;
  signal starve_limit_cntr_r : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal starve_limit_cntr_r0 : STD_LOGIC;
  signal \starve_limit_cntr_r[0]_i_1_n_0\ : STD_LOGIC;
  signal \starve_limit_cntr_r[1]_i_1_n_0\ : STD_LOGIC;
  signal \starve_limit_cntr_r[2]_i_1_n_0\ : STD_LOGIC;
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \act_wait_r_lcl_i_2__0\ : label is "soft_lutpair1179";
  attribute SOFT_HLUTNM of \demand_priority_r_i_4__1\ : label is "soft_lutpair1178";
  attribute SOFT_HLUTNM of \grant_r[3]_i_2__1\ : label is "soft_lutpair1176";
  attribute SOFT_HLUTNM of \pre_wait_r_i_2__1\ : label is "soft_lutpair1176";
  attribute SOFT_HLUTNM of \ras_timer_r[1]_i_5__1\ : label is "soft_lutpair1179";
  attribute SOFT_HLUTNM of \starve_limit_cntr_r[0]_i_1\ : label is "soft_lutpair1178";
  attribute SOFT_HLUTNM of \starve_limit_cntr_r[1]_i_1\ : label is "soft_lutpair1177";
  attribute SOFT_HLUTNM of \starve_limit_cntr_r[2]_i_1\ : label is "soft_lutpair1177";
begin
  act_wait_r_lcl_reg_0 <= \^act_wait_r_lcl_reg_0\;
  bm_end_r1_0 <= \^bm_end_r1_0\;
  bm_end_r1_reg_0 <= \^bm_end_r1_reg_0\;
  col_wait_r_reg_0 <= \^col_wait_r_reg_0\;
  demand_priority_r_reg_0 <= \^demand_priority_r_reg_0\;
  demanded_prior_r_reg_0 <= \^demanded_prior_r_reg_0\;
  pre_passing_open_bank_ns <= \^pre_passing_open_bank_ns\;
  pre_wait_r <= \^pre_wait_r\;
  \ras_timer_r_reg[1]_0\ <= \^ras_timer_r_reg[1]_0\;
  ras_timer_zero_r <= \^ras_timer_zero_r\;
\act_this_rank_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => ofs_rdy_r_reg_0,
      CE => '1',
      D => \^act_wait_r_lcl_reg_0\,
      Q => act_this_rank_r(0),
      R => '0'
    );
\act_wait_r_lcl_i_1__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFF888"
    )
        port map (
      I0 => \^act_wait_r_lcl_reg_0\,
      I1 => \act_wait_r_lcl_i_2__0_n_0\,
      I2 => pass_open_bank_r,
      I3 => bm_end_r1_reg_1,
      I4 => pre_wait_r_reg_0,
      I5 => \^bm_end_r1_0\,
      O => act_wait_ns
    );
\act_wait_r_lcl_i_2__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"07"
    )
        port map (
      I0 => act_wait_r_lcl_reg_2(0),
      I1 => \^act_wait_r_lcl_reg_0\,
      I2 => act_wait_r_lcl_reg_3,
      O => \act_wait_r_lcl_i_2__0_n_0\
    );
act_wait_r_lcl_reg: unisim.vcomponents.FDRE
     port map (
      C => ofs_rdy_r_reg_0,
      CE => '1',
      D => act_wait_ns,
      Q => \^act_wait_r_lcl_reg_0\,
      R => '0'
    );
bm_end_r1_reg: unisim.vcomponents.FDRE
     port map (
      C => ofs_rdy_r_reg_0,
      CE => '1',
      D => bm_end_r1_reg_1,
      Q => \^bm_end_r1_0\,
      R => '0'
    );
\cmd_pipe_plus.mc_address[38]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"88888888F0000000"
    )
        port map (
      I0 => \^act_wait_r_lcl_reg_0\,
      I1 => \cmd_pipe_plus.mc_address_reg[38]\(0),
      I2 => \cmd_pipe_plus.mc_address_reg[38]_0\(0),
      I3 => row_cmd_wr(0),
      I4 => pre_bm_end_r_reg(0),
      I5 => pre_bm_end_r_reg(1),
      O => act_wait_r_lcl_reg_1
    );
col_wait_r_reg: unisim.vcomponents.FDRE
     port map (
      C => ofs_rdy_r_reg_0,
      CE => '1',
      D => col_wait_r_reg_1,
      Q => \^col_wait_r_reg_0\,
      R => '0'
    );
\demand_priority_r_i_1__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888808"
    )
        port map (
      I0 => col_wait_r_reg_1,
      I1 => demand_priority_r_reg_2,
      I2 => demand_priority_r_reg_3,
      I3 => \demand_priority_r_i_3__1_n_0\,
      I4 => \^demand_priority_r_reg_0\,
      O => demand_priority_ns
    );
\demand_priority_r_i_3__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000040400040"
    )
        port map (
      I0 => Q(1),
      I1 => demand_priority_r_reg_4,
      I2 => req_bank_rdy_r,
      I3 => demand_priority_r_reg_5,
      I4 => q_has_rd_7,
      I5 => \demand_priority_r_i_4__1_n_0\,
      O => \demand_priority_r_i_3__1_n_0\
    );
\demand_priority_r_i_4__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"7F"
    )
        port map (
      I0 => starve_limit_cntr_r(2),
      I1 => starve_limit_cntr_r(1),
      I2 => starve_limit_cntr_r(0),
      O => \demand_priority_r_i_4__1_n_0\
    );
demand_priority_r_reg: unisim.vcomponents.FDRE
     port map (
      C => ofs_rdy_r_reg_0,
      CE => '1',
      D => demand_priority_ns,
      Q => \^demand_priority_r_reg_0\,
      R => '0'
    );
\demanded_prior_r_i_1__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000D00DDDDDDDD"
    )
        port map (
      I0 => \^demand_priority_r_reg_0\,
      I1 => \^demanded_prior_r_reg_0\,
      I2 => Q(0),
      I3 => demand_priority_r_1,
      I4 => demanded_prior_r_2,
      I5 => demanded_prior_r_reg_1,
      O => demanded_prior_ns
    );
demanded_prior_r_reg: unisim.vcomponents.FDRE
     port map (
      C => ofs_rdy_r_reg_0,
      CE => '1',
      D => demanded_prior_ns,
      Q => \^demanded_prior_r_reg_0\,
      R => '0'
    );
\grant_r[3]_i_2__1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"1000"
    )
        port map (
      I0 => pre_bm_end_r_reg_0,
      I1 => pre_bm_end_r_reg(1),
      I2 => \^pre_wait_r\,
      I3 => \^ras_timer_zero_r\,
      O => auto_pre_r_lcl_reg
    );
\i___40_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFEFAAAA"
    )
        port map (
      I0 => demand_priority_r_1,
      I1 => Q(1),
      I2 => \^demand_priority_r_reg_0\,
      I3 => \^demanded_prior_r_reg_0\,
      I4 => demanded_prior_r_reg_1,
      O => demand_priority_r_reg_1
    );
ofs_rdy_r_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => ofs_rdy_r_reg_0,
      CE => '1',
      D => ofs_rdy_r0,
      Q => ofs_rdy_r,
      R => ofs_rdy_r_reg_1
    );
override_demand_r_reg: unisim.vcomponents.FDRE
     port map (
      C => ofs_rdy_r_reg_0,
      CE => '1',
      D => override_demand_ns,
      Q => override_demand_r,
      R => '0'
    );
\pre_4_1_1T_arb.granted_pre_r_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000FFF7"
    )
        port map (
      I0 => \^ras_timer_zero_r\,
      I1 => \^pre_wait_r\,
      I2 => pre_bm_end_r_reg(1),
      I3 => pre_bm_end_r_reg_0,
      I4 => \pre_4_1_1T_arb.granted_pre_r_reg\,
      O => ras_timer_zero_r_reg_0
    );
\pre_bm_end_r_i_1__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"EAEAEAAA"
    )
        port map (
      I0 => \^pre_passing_open_bank_ns\,
      I1 => \^ras_timer_zero_r\,
      I2 => \^pre_wait_r\,
      I3 => pre_bm_end_r_reg(1),
      I4 => pre_bm_end_r_reg_0,
      O => pre_bm_end_ns
    );
\pre_passing_open_bank_r_i_1__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAA8AAAAAAA8AAA8"
    )
        port map (
      I0 => pass_open_bank_ns,
      I1 => Q(1),
      I2 => rtp_timer_r(0),
      I3 => rtp_timer_r(1),
      I4 => \^ras_timer_zero_r\,
      I5 => \^pre_wait_r\,
      O => \^pre_passing_open_bank_ns\
    );
\pre_wait_r_i_1__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"4444444444454444"
    )
        port map (
      I0 => pass_open_bank_ns,
      I1 => \pre_wait_r_i_2__1_n_0\,
      I2 => pass_open_bank_r,
      I3 => pre_wait_r_reg_0,
      I4 => rtp_timer_r(0),
      I5 => rtp_timer_r(1),
      O => pre_wait_ns
    );
\pre_wait_r_i_2__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"10101050"
    )
        port map (
      I0 => ras_timer_zero_r_reg_1,
      I1 => \^ras_timer_zero_r\,
      I2 => \^pre_wait_r\,
      I3 => pre_bm_end_r_reg(1),
      I4 => pre_bm_end_r_reg_0,
      O => \pre_wait_r_i_2__1_n_0\
    );
pre_wait_r_reg: unisim.vcomponents.FDRE
     port map (
      C => ofs_rdy_r_reg_0,
      CE => '1',
      D => pre_wait_ns,
      Q => \^pre_wait_r\,
      R => '0'
    );
\ras_timer_r[0]_i_3__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0010111100100010"
    )
        port map (
      I0 => \^bm_end_r1_0\,
      I1 => ras_timer_zero_r_reg_1,
      I2 => \ras_timer_r_reg_n_0_[1]\,
      I3 => \ras_timer_r_reg_n_0_[0]\,
      I4 => \rd_this_rank_r_reg[0]_0\,
      I5 => Q(1),
      O => \^bm_end_r1_reg_0\
    );
\ras_timer_r[1]_i_3__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"4041555540414041"
    )
        port map (
      I0 => ras_timer_zero_r_reg_2,
      I1 => \ras_timer_r_reg_n_0_[1]\,
      I2 => \ras_timer_r_reg_n_0_[0]\,
      I3 => \ras_timer_r[1]_i_5__1_n_0\,
      I4 => \rd_this_rank_r_reg[0]_0\,
      I5 => Q(1),
      O => \^ras_timer_r_reg[1]_0\
    );
\ras_timer_r[1]_i_5__1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"7"
    )
        port map (
      I0 => \^act_wait_r_lcl_reg_0\,
      I1 => act_wait_r_lcl_reg_2(0),
      O => \ras_timer_r[1]_i_5__1_n_0\
    );
\ras_timer_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => ofs_rdy_r_reg_0,
      CE => '1',
      D => D(0),
      Q => \ras_timer_r_reg_n_0_[0]\,
      R => '0'
    );
\ras_timer_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => ofs_rdy_r_reg_0,
      CE => '1',
      D => D(1),
      Q => \ras_timer_r_reg_n_0_[1]\,
      R => '0'
    );
\ras_timer_zero_r_i_1__1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \^ras_timer_r_reg[1]_0\,
      I1 => \^bm_end_r1_reg_0\,
      O => \ras_timer_zero_r_i_1__1_n_0\
    );
ras_timer_zero_r_reg: unisim.vcomponents.FDRE
     port map (
      C => ofs_rdy_r_reg_0,
      CE => '1',
      D => \ras_timer_zero_r_i_1__1_n_0\,
      Q => \^ras_timer_zero_r\,
      R => '0'
    );
\rd_this_rank_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => ofs_rdy_r_reg_0,
      CE => '1',
      D => \rd_this_rank_r_reg[0]_0\,
      Q => rd_this_rank_r(0),
      R => '0'
    );
req_bank_rdy_r_reg: unisim.vcomponents.FDRE
     port map (
      C => ofs_rdy_r_reg_0,
      CE => '1',
      D => req_bank_rdy_ns,
      Q => req_bank_rdy_r,
      R => '0'
    );
\rtp_timer_r[0]_i_1__1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0010"
    )
        port map (
      I0 => \rtp_timer_r_reg[0]_0\,
      I1 => pass_open_bank_r,
      I2 => rtp_timer_r(1),
      I3 => rtp_timer_r(0),
      O => \rtp_timer_r[0]_i_1__1_n_0\
    );
\rtp_timer_r[1]_i_1__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"000000C2"
    )
        port map (
      I0 => Q(1),
      I1 => rtp_timer_r(0),
      I2 => rtp_timer_r(1),
      I3 => pass_open_bank_r,
      I4 => pre_wait_r_reg_0,
      O => \rtp_timer_r[1]_i_1__1_n_0\
    );
\rtp_timer_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => ofs_rdy_r_reg_0,
      CE => '1',
      D => \rtp_timer_r[0]_i_1__1_n_0\,
      Q => rtp_timer_r(0),
      R => '0'
    );
\rtp_timer_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => ofs_rdy_r_reg_0,
      CE => '1',
      D => \rtp_timer_r[1]_i_1__1_n_0\,
      Q => rtp_timer_r(1),
      R => '0'
    );
\starve_limit_cntr_r[0]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"60"
    )
        port map (
      I0 => starve_limit_cntr_r(0),
      I1 => starve_limit_cntr_r0,
      I2 => \^col_wait_r_reg_0\,
      O => \starve_limit_cntr_r[0]_i_1_n_0\
    );
\starve_limit_cntr_r[1]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6A00"
    )
        port map (
      I0 => starve_limit_cntr_r(1),
      I1 => starve_limit_cntr_r0,
      I2 => starve_limit_cntr_r(0),
      I3 => \^col_wait_r_reg_0\,
      O => \starve_limit_cntr_r[1]_i_1_n_0\
    );
\starve_limit_cntr_r[2]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"6AAA0000"
    )
        port map (
      I0 => starve_limit_cntr_r(2),
      I1 => starve_limit_cntr_r0,
      I2 => starve_limit_cntr_r(0),
      I3 => starve_limit_cntr_r(1),
      I4 => \^col_wait_r_reg_0\,
      O => \starve_limit_cntr_r[2]_i_1_n_0\
    );
\starve_limit_cntr_r[2]_i_2__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"007F000000000000"
    )
        port map (
      I0 => starve_limit_cntr_r(0),
      I1 => starve_limit_cntr_r(1),
      I2 => starve_limit_cntr_r(2),
      I3 => Q(1),
      I4 => demand_priority_r_reg_4,
      I5 => req_bank_rdy_r,
      O => starve_limit_cntr_r0
    );
\starve_limit_cntr_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => ofs_rdy_r_reg_0,
      CE => '1',
      D => \starve_limit_cntr_r[0]_i_1_n_0\,
      Q => starve_limit_cntr_r(0),
      R => '0'
    );
\starve_limit_cntr_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => ofs_rdy_r_reg_0,
      CE => '1',
      D => \starve_limit_cntr_r[1]_i_1_n_0\,
      Q => starve_limit_cntr_r(1),
      R => '0'
    );
\starve_limit_cntr_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => ofs_rdy_r_reg_0,
      CE => '1',
      D => \starve_limit_cntr_r[2]_i_1_n_0\,
      Q => starve_limit_cntr_r(2),
      R => '0'
    );
\wr_this_rank_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => ofs_rdy_r_reg_0,
      CE => '1',
      D => start_wtp_timer0,
      Q => wr_this_rank_r(0),
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \mig_mig_7series_v4_2_bank_state__parameterized2\ is
  port (
    act_wait_r_lcl_reg_0 : out STD_LOGIC;
    act_this_rank_r : out STD_LOGIC_VECTOR ( 0 to 0 );
    wr_this_rank_r : out STD_LOGIC_VECTOR ( 0 to 0 );
    rd_this_rank_r : out STD_LOGIC_VECTOR ( 0 to 0 );
    bm_end_r1_1 : out STD_LOGIC;
    ras_timer_zero_r : out STD_LOGIC;
    pre_wait_r : out STD_LOGIC;
    col_wait_r_reg_0 : out STD_LOGIC;
    demand_priority_r_reg_0 : out STD_LOGIC;
    demanded_prior_r_reg_0 : out STD_LOGIC;
    ofs_rdy_r : out STD_LOGIC;
    pre_bm_end_ns : out STD_LOGIC;
    pre_passing_open_bank_ns : out STD_LOGIC;
    \pre_4_1_1T_arb.granted_pre_ns\ : out STD_LOGIC;
    auto_pre_r_lcl_reg : out STD_LOGIC;
    act_wait_r_lcl_reg_1 : out STD_LOGIC;
    \ras_timer_r_reg[1]_0\ : out STD_LOGIC;
    bm_end_r1_reg_0 : out STD_LOGIC;
    demand_priority_r_reg_1 : out STD_LOGIC;
    \grant_r_reg[3]\ : out STD_LOGIC;
    demand_priority_r_reg_2 : in STD_LOGIC;
    start_wtp_timer0 : in STD_LOGIC;
    \rd_this_rank_r_reg[0]_0\ : in STD_LOGIC;
    p_13_out : in STD_LOGIC;
    col_wait_r_reg_1 : in STD_LOGIC;
    req_bank_rdy_ns : in STD_LOGIC;
    ofs_rdy_r_reg_0 : in STD_LOGIC;
    ofs_rdy_r0 : in STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \rtp_timer_r_reg[1]_0\ : in STD_LOGIC;
    pre_wait_r_reg_0 : in STD_LOGIC;
    act_wait_r_lcl_reg_2 : in STD_LOGIC;
    demand_priority_r_reg_3 : in STD_LOGIC;
    demand_priority_r_reg_4 : in STD_LOGIC;
    act_wait_r_lcl_reg_3 : in STD_LOGIC_VECTOR ( 1 downto 0 );
    act_wait_r_lcl_reg_4 : in STD_LOGIC;
    pre_bm_end_r_reg : in STD_LOGIC_VECTOR ( 0 to 0 );
    pre_bm_end_r_reg_0 : in STD_LOGIC;
    pass_open_bank_ns : in STD_LOGIC;
    \pre_4_1_1T_arb.granted_pre_r_reg\ : in STD_LOGIC;
    \pre_4_1_1T_arb.granted_pre_r_reg_0\ : in STD_LOGIC;
    \ras_timer_r_reg[0]_0\ : in STD_LOGIC;
    \cmd_pipe_plus.mc_address[10]_i_2\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    row_cmd_wr : in STD_LOGIC_VECTOR ( 0 to 0 );
    \cmd_pipe_plus.mc_address[10]_i_2_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    ras_timer_zero_r_reg_0 : in STD_LOGIC;
    demanded_prior_r_reg_1 : in STD_LOGIC;
    demand_priority_r : in STD_LOGIC;
    demanded_prior_r : in STD_LOGIC;
    demand_priority_r_reg_5 : in STD_LOGIC;
    demand_priority_r_reg_6 : in STD_LOGIC;
    q_has_rd_12 : in STD_LOGIC;
    \rtp_timer_r_reg[0]_0\ : in STD_LOGIC;
    D : in STD_LOGIC_VECTOR ( 1 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \mig_mig_7series_v4_2_bank_state__parameterized2\ : entity is "mig_7series_v4_2_bank_state";
end \mig_mig_7series_v4_2_bank_state__parameterized2\;

architecture STRUCTURE of \mig_mig_7series_v4_2_bank_state__parameterized2\ is
  signal act_wait_ns : STD_LOGIC;
  signal act_wait_r_lcl_i_2_n_0 : STD_LOGIC;
  signal \^act_wait_r_lcl_reg_0\ : STD_LOGIC;
  signal \^bm_end_r1_1\ : STD_LOGIC;
  signal \^col_wait_r_reg_0\ : STD_LOGIC;
  signal demand_priority_ns : STD_LOGIC;
  signal \demand_priority_r_i_3__2_n_0\ : STD_LOGIC;
  signal \demand_priority_r_i_4__2_n_0\ : STD_LOGIC;
  signal \^demand_priority_r_reg_0\ : STD_LOGIC;
  signal demanded_prior_ns : STD_LOGIC;
  signal \^demanded_prior_r_reg_0\ : STD_LOGIC;
  signal \^pre_passing_open_bank_ns\ : STD_LOGIC;
  signal pre_wait_ns : STD_LOGIC;
  signal \^pre_wait_r\ : STD_LOGIC;
  signal \pre_wait_r_i_2__2_n_0\ : STD_LOGIC;
  signal \ras_timer_r_reg_n_0_[0]\ : STD_LOGIC;
  signal \ras_timer_r_reg_n_0_[1]\ : STD_LOGIC;
  signal \^ras_timer_zero_r\ : STD_LOGIC;
  signal \ras_timer_zero_r_i_1__2_n_0\ : STD_LOGIC;
  signal ras_timer_zero_r_i_2_n_0 : STD_LOGIC;
  signal req_bank_rdy_r : STD_LOGIC;
  signal rtp_timer_r : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \rtp_timer_r[0]_i_1__2_n_0\ : STD_LOGIC;
  signal \rtp_timer_r[1]_i_1__2_n_0\ : STD_LOGIC;
  signal starve_limit_cntr_r : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal starve_limit_cntr_r0 : STD_LOGIC;
  signal \starve_limit_cntr_r[0]_i_1_n_0\ : STD_LOGIC;
  signal \starve_limit_cntr_r[1]_i_1_n_0\ : STD_LOGIC;
  signal \starve_limit_cntr_r[2]_i_1_n_0\ : STD_LOGIC;
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of act_wait_r_lcl_i_2 : label is "soft_lutpair1190";
  attribute SOFT_HLUTNM of \demand_priority_r_i_4__2\ : label is "soft_lutpair1189";
  attribute SOFT_HLUTNM of \grant_r[2]_i_6\ : label is "soft_lutpair1187";
  attribute SOFT_HLUTNM of \grant_r[3]_i_5__0\ : label is "soft_lutpair1186";
  attribute SOFT_HLUTNM of \i___40_i_5\ : label is "soft_lutpair1187";
  attribute SOFT_HLUTNM of \pre_bm_end_r_i_1__2\ : label is "soft_lutpair1186";
  attribute SOFT_HLUTNM of ras_timer_zero_r_i_2 : label is "soft_lutpair1190";
  attribute SOFT_HLUTNM of \starve_limit_cntr_r[0]_i_1\ : label is "soft_lutpair1189";
  attribute SOFT_HLUTNM of \starve_limit_cntr_r[1]_i_1\ : label is "soft_lutpair1188";
  attribute SOFT_HLUTNM of \starve_limit_cntr_r[2]_i_1\ : label is "soft_lutpair1188";
begin
  act_wait_r_lcl_reg_0 <= \^act_wait_r_lcl_reg_0\;
  bm_end_r1_1 <= \^bm_end_r1_1\;
  col_wait_r_reg_0 <= \^col_wait_r_reg_0\;
  demand_priority_r_reg_0 <= \^demand_priority_r_reg_0\;
  demanded_prior_r_reg_0 <= \^demanded_prior_r_reg_0\;
  pre_passing_open_bank_ns <= \^pre_passing_open_bank_ns\;
  pre_wait_r <= \^pre_wait_r\;
  ras_timer_zero_r <= \^ras_timer_zero_r\;
\act_this_rank_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => demand_priority_r_reg_2,
      CE => '1',
      D => \^act_wait_r_lcl_reg_0\,
      Q => act_this_rank_r(0),
      R => '0'
    );
act_wait_r_lcl_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFF88F8"
    )
        port map (
      I0 => \^act_wait_r_lcl_reg_0\,
      I1 => act_wait_r_lcl_i_2_n_0,
      I2 => \rtp_timer_r_reg[1]_0\,
      I3 => act_wait_r_lcl_reg_2,
      I4 => pre_wait_r_reg_0,
      I5 => \^bm_end_r1_1\,
      O => act_wait_ns
    );
act_wait_r_lcl_i_2: unisim.vcomponents.LUT3
    generic map(
      INIT => X"07"
    )
        port map (
      I0 => act_wait_r_lcl_reg_3(1),
      I1 => \^act_wait_r_lcl_reg_0\,
      I2 => act_wait_r_lcl_reg_4,
      O => act_wait_r_lcl_i_2_n_0
    );
act_wait_r_lcl_reg: unisim.vcomponents.FDRE
     port map (
      C => demand_priority_r_reg_2,
      CE => '1',
      D => act_wait_ns,
      Q => \^act_wait_r_lcl_reg_0\,
      R => '0'
    );
bm_end_r1_reg: unisim.vcomponents.FDRE
     port map (
      C => demand_priority_r_reg_2,
      CE => '1',
      D => p_13_out,
      Q => \^bm_end_r1_1\,
      R => '0'
    );
\cmd_pipe_plus.mc_address[10]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8888F00088880000"
    )
        port map (
      I0 => \^act_wait_r_lcl_reg_0\,
      I1 => \cmd_pipe_plus.mc_address[10]_i_2\(0),
      I2 => row_cmd_wr(0),
      I3 => act_wait_r_lcl_reg_3(0),
      I4 => act_wait_r_lcl_reg_3(1),
      I5 => \cmd_pipe_plus.mc_address[10]_i_2_0\(0),
      O => act_wait_r_lcl_reg_1
    );
col_wait_r_reg: unisim.vcomponents.FDRE
     port map (
      C => demand_priority_r_reg_2,
      CE => '1',
      D => col_wait_r_reg_1,
      Q => \^col_wait_r_reg_0\,
      R => '0'
    );
demand_priority_r_i_1: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888808"
    )
        port map (
      I0 => col_wait_r_reg_1,
      I1 => demand_priority_r_reg_3,
      I2 => demand_priority_r_reg_4,
      I3 => \demand_priority_r_i_3__2_n_0\,
      I4 => \^demand_priority_r_reg_0\,
      O => demand_priority_ns
    );
\demand_priority_r_i_3__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000040400040"
    )
        port map (
      I0 => Q(1),
      I1 => demand_priority_r_reg_5,
      I2 => req_bank_rdy_r,
      I3 => demand_priority_r_reg_6,
      I4 => q_has_rd_12,
      I5 => \demand_priority_r_i_4__2_n_0\,
      O => \demand_priority_r_i_3__2_n_0\
    );
\demand_priority_r_i_4__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"7F"
    )
        port map (
      I0 => starve_limit_cntr_r(2),
      I1 => starve_limit_cntr_r(1),
      I2 => starve_limit_cntr_r(0),
      O => \demand_priority_r_i_4__2_n_0\
    );
demand_priority_r_reg: unisim.vcomponents.FDRE
     port map (
      C => demand_priority_r_reg_2,
      CE => '1',
      D => demand_priority_ns,
      Q => \^demand_priority_r_reg_0\,
      R => '0'
    );
demanded_prior_r_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"D0D0D0D0D0DDD0D0"
    )
        port map (
      I0 => \^demand_priority_r_reg_0\,
      I1 => \^demanded_prior_r_reg_0\,
      I2 => demanded_prior_r_reg_1,
      I3 => Q(0),
      I4 => demand_priority_r,
      I5 => demanded_prior_r,
      O => demanded_prior_ns
    );
demanded_prior_r_reg: unisim.vcomponents.FDRE
     port map (
      C => demand_priority_r_reg_2,
      CE => '1',
      D => demanded_prior_ns,
      Q => \^demanded_prior_r_reg_0\,
      R => '0'
    );
\grant_r[2]_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"FB"
    )
        port map (
      I0 => Q(1),
      I1 => \^demand_priority_r_reg_0\,
      I2 => \^demanded_prior_r_reg_0\,
      O => \grant_r_reg[3]\
    );
\grant_r[3]_i_5__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"1000"
    )
        port map (
      I0 => pre_bm_end_r_reg_0,
      I1 => pre_bm_end_r_reg(0),
      I2 => \^pre_wait_r\,
      I3 => \^ras_timer_zero_r\,
      O => auto_pre_r_lcl_reg
    );
\i___40_i_5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"BBBBBABB"
    )
        port map (
      I0 => demand_priority_r,
      I1 => demanded_prior_r_reg_1,
      I2 => Q(1),
      I3 => \^demand_priority_r_reg_0\,
      I4 => \^demanded_prior_r_reg_0\,
      O => demand_priority_r_reg_1
    );
ofs_rdy_r_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => demand_priority_r_reg_2,
      CE => '1',
      D => ofs_rdy_r0,
      Q => ofs_rdy_r,
      R => ofs_rdy_r_reg_0
    );
\pre_4_1_1T_arb.granted_pre_r_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"ABAAAAAAFFFFFFFF"
    )
        port map (
      I0 => \pre_4_1_1T_arb.granted_pre_r_reg\,
      I1 => pre_bm_end_r_reg_0,
      I2 => pre_bm_end_r_reg(0),
      I3 => \^pre_wait_r\,
      I4 => \^ras_timer_zero_r\,
      I5 => \pre_4_1_1T_arb.granted_pre_r_reg_0\,
      O => \pre_4_1_1T_arb.granted_pre_ns\
    );
\pre_bm_end_r_i_1__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"EAEAEAAA"
    )
        port map (
      I0 => \^pre_passing_open_bank_ns\,
      I1 => \^ras_timer_zero_r\,
      I2 => \^pre_wait_r\,
      I3 => pre_bm_end_r_reg(0),
      I4 => pre_bm_end_r_reg_0,
      O => pre_bm_end_ns
    );
\pre_passing_open_bank_r_i_1__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAA8AAAAAAA8AAA8"
    )
        port map (
      I0 => pass_open_bank_ns,
      I1 => Q(1),
      I2 => rtp_timer_r(0),
      I3 => rtp_timer_r(1),
      I4 => \^ras_timer_zero_r\,
      I5 => \^pre_wait_r\,
      O => \^pre_passing_open_bank_ns\
    );
\pre_wait_r_i_1__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"4444444444454444"
    )
        port map (
      I0 => pass_open_bank_ns,
      I1 => \pre_wait_r_i_2__2_n_0\,
      I2 => \rtp_timer_r_reg[1]_0\,
      I3 => pre_wait_r_reg_0,
      I4 => rtp_timer_r(0),
      I5 => rtp_timer_r(1),
      O => pre_wait_ns
    );
\pre_wait_r_i_2__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"10101050"
    )
        port map (
      I0 => \ras_timer_r_reg[0]_0\,
      I1 => \^ras_timer_zero_r\,
      I2 => \^pre_wait_r\,
      I3 => pre_bm_end_r_reg(0),
      I4 => pre_bm_end_r_reg_0,
      O => \pre_wait_r_i_2__2_n_0\
    );
pre_wait_r_reg: unisim.vcomponents.FDRE
     port map (
      C => demand_priority_r_reg_2,
      CE => '1',
      D => pre_wait_ns,
      Q => \^pre_wait_r\,
      R => '0'
    );
\ras_timer_r[0]_i_3__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0010111100100010"
    )
        port map (
      I0 => \^bm_end_r1_1\,
      I1 => \ras_timer_r_reg[0]_0\,
      I2 => \ras_timer_r_reg_n_0_[1]\,
      I3 => \ras_timer_r_reg_n_0_[0]\,
      I4 => \rd_this_rank_r_reg[0]_0\,
      I5 => Q(1),
      O => bm_end_r1_reg_0
    );
\ras_timer_r[1]_i_3__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"4041555540414041"
    )
        port map (
      I0 => ras_timer_zero_r_reg_0,
      I1 => \ras_timer_r_reg_n_0_[1]\,
      I2 => \ras_timer_r_reg_n_0_[0]\,
      I3 => ras_timer_zero_r_i_2_n_0,
      I4 => \rd_this_rank_r_reg[0]_0\,
      I5 => Q(1),
      O => \ras_timer_r_reg[1]_0\
    );
\ras_timer_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => demand_priority_r_reg_2,
      CE => '1',
      D => D(0),
      Q => \ras_timer_r_reg_n_0_[0]\,
      R => '0'
    );
\ras_timer_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => demand_priority_r_reg_2,
      CE => '1',
      D => D(1),
      Q => \ras_timer_r_reg_n_0_[1]\,
      R => '0'
    );
\ras_timer_zero_r_i_1__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFF0000DDD0"
    )
        port map (
      I0 => Q(1),
      I1 => \rd_this_rank_r_reg[0]_0\,
      I2 => ras_timer_zero_r_i_2_n_0,
      I3 => \ras_timer_r_reg_n_0_[0]\,
      I4 => \ras_timer_r_reg_n_0_[1]\,
      I5 => ras_timer_zero_r_reg_0,
      O => \ras_timer_zero_r_i_1__2_n_0\
    );
ras_timer_zero_r_i_2: unisim.vcomponents.LUT2
    generic map(
      INIT => X"7"
    )
        port map (
      I0 => \^act_wait_r_lcl_reg_0\,
      I1 => act_wait_r_lcl_reg_3(1),
      O => ras_timer_zero_r_i_2_n_0
    );
ras_timer_zero_r_reg: unisim.vcomponents.FDRE
     port map (
      C => demand_priority_r_reg_2,
      CE => '1',
      D => \ras_timer_zero_r_i_1__2_n_0\,
      Q => \^ras_timer_zero_r\,
      R => '0'
    );
\rd_this_rank_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => demand_priority_r_reg_2,
      CE => '1',
      D => \rd_this_rank_r_reg[0]_0\,
      Q => rd_this_rank_r(0),
      R => '0'
    );
req_bank_rdy_r_reg: unisim.vcomponents.FDRE
     port map (
      C => demand_priority_r_reg_2,
      CE => '1',
      D => req_bank_rdy_ns,
      Q => req_bank_rdy_r,
      R => '0'
    );
\rtp_timer_r[0]_i_1__2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0010"
    )
        port map (
      I0 => \rtp_timer_r_reg[0]_0\,
      I1 => \rtp_timer_r_reg[1]_0\,
      I2 => rtp_timer_r(1),
      I3 => rtp_timer_r(0),
      O => \rtp_timer_r[0]_i_1__2_n_0\
    );
\rtp_timer_r[1]_i_1__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"000000C2"
    )
        port map (
      I0 => Q(1),
      I1 => rtp_timer_r(0),
      I2 => rtp_timer_r(1),
      I3 => \rtp_timer_r_reg[1]_0\,
      I4 => pre_wait_r_reg_0,
      O => \rtp_timer_r[1]_i_1__2_n_0\
    );
\rtp_timer_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => demand_priority_r_reg_2,
      CE => '1',
      D => \rtp_timer_r[0]_i_1__2_n_0\,
      Q => rtp_timer_r(0),
      R => '0'
    );
\rtp_timer_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => demand_priority_r_reg_2,
      CE => '1',
      D => \rtp_timer_r[1]_i_1__2_n_0\,
      Q => rtp_timer_r(1),
      R => '0'
    );
\starve_limit_cntr_r[0]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"60"
    )
        port map (
      I0 => starve_limit_cntr_r(0),
      I1 => starve_limit_cntr_r0,
      I2 => \^col_wait_r_reg_0\,
      O => \starve_limit_cntr_r[0]_i_1_n_0\
    );
\starve_limit_cntr_r[1]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6A00"
    )
        port map (
      I0 => starve_limit_cntr_r(1),
      I1 => starve_limit_cntr_r0,
      I2 => starve_limit_cntr_r(0),
      I3 => \^col_wait_r_reg_0\,
      O => \starve_limit_cntr_r[1]_i_1_n_0\
    );
\starve_limit_cntr_r[2]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"6AAA0000"
    )
        port map (
      I0 => starve_limit_cntr_r(2),
      I1 => starve_limit_cntr_r0,
      I2 => starve_limit_cntr_r(0),
      I3 => starve_limit_cntr_r(1),
      I4 => \^col_wait_r_reg_0\,
      O => \starve_limit_cntr_r[2]_i_1_n_0\
    );
\starve_limit_cntr_r[2]_i_2__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"007F000000000000"
    )
        port map (
      I0 => starve_limit_cntr_r(0),
      I1 => starve_limit_cntr_r(1),
      I2 => starve_limit_cntr_r(2),
      I3 => Q(1),
      I4 => demand_priority_r_reg_5,
      I5 => req_bank_rdy_r,
      O => starve_limit_cntr_r0
    );
\starve_limit_cntr_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => demand_priority_r_reg_2,
      CE => '1',
      D => \starve_limit_cntr_r[0]_i_1_n_0\,
      Q => starve_limit_cntr_r(0),
      R => '0'
    );
\starve_limit_cntr_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => demand_priority_r_reg_2,
      CE => '1',
      D => \starve_limit_cntr_r[1]_i_1_n_0\,
      Q => starve_limit_cntr_r(1),
      R => '0'
    );
\starve_limit_cntr_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => demand_priority_r_reg_2,
      CE => '1',
      D => \starve_limit_cntr_r[2]_i_1_n_0\,
      Q => starve_limit_cntr_r(2),
      R => '0'
    );
\wr_this_rank_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => demand_priority_r_reg_2,
      CE => '1',
      D => start_wtp_timer0,
      Q => wr_this_rank_r(0),
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mig_mig_7series_v4_2_clk_ibuf is
  port (
    \out\ : out STD_LOGIC;
    sys_clk_p : in STD_LOGIC;
    sys_clk_n : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of mig_mig_7series_v4_2_clk_ibuf : entity is "mig_7series_v4_2_clk_ibuf";
end mig_mig_7series_v4_2_clk_ibuf;

architecture STRUCTURE of mig_mig_7series_v4_2_clk_ibuf is
  signal sys_clk_ibufg : STD_LOGIC;
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of sys_clk_ibufg : signal is "true";
  attribute syn_keep : string;
  attribute syn_keep of sys_clk_ibufg : signal is "true";
  attribute BOX_TYPE : string;
  attribute BOX_TYPE of \diff_input_clk.u_ibufg_sys_clk\ : label is "PRIMITIVE";
  attribute CAPACITANCE : string;
  attribute CAPACITANCE of \diff_input_clk.u_ibufg_sys_clk\ : label is "DONT_CARE";
  attribute IBUF_DELAY_VALUE : string;
  attribute IBUF_DELAY_VALUE of \diff_input_clk.u_ibufg_sys_clk\ : label is "0";
  attribute XILINX_LEGACY_PRIM : string;
  attribute XILINX_LEGACY_PRIM of \diff_input_clk.u_ibufg_sys_clk\ : label is "IBUFGDS";
begin
  \out\ <= sys_clk_ibufg;
\diff_input_clk.u_ibufg_sys_clk\: unisim.vcomponents.IBUFDS
    generic map(
      IOSTANDARD => "DEFAULT"
    )
        port map (
      I => sys_clk_p,
      IB => sys_clk_n,
      O => sys_clk_ibufg
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mig_mig_7series_v4_2_col_mach is
  port (
    col_rd_wr_r1 : out STD_LOGIC;
    col_rd_wr_r2 : out STD_LOGIC;
    sent_col_r2 : out STD_LOGIC;
    D : out STD_LOGIC_VECTOR ( 3 downto 0 );
    \read_fifo.tail_r_reg[4]_0\ : out STD_LOGIC;
    \read_fifo.tail_r_reg[2]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    mc_ref_zq_wip_ns : out STD_LOGIC;
    \read_fifo.tail_r_reg[0]_0\ : out STD_LOGIC;
    \read_fifo.tail_r_reg[4]_1\ : out STD_LOGIC;
    \read_fifo.fifo_out_data_r_reg[7]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \read_fifo.head_r_reg[4]_0\ : in STD_LOGIC;
    DIC : in STD_LOGIC_VECTOR ( 0 to 0 );
    ADDRA : in STD_LOGIC_VECTOR ( 2 downto 0 );
    col_rd_wr : in STD_LOGIC;
    mc_cmd : in STD_LOGIC_VECTOR ( 0 to 0 );
    col_wr_data_buf_addr : in STD_LOGIC_VECTOR ( 3 downto 0 );
    maint_ref_zq_wip : in STD_LOGIC;
    \read_fifo.tail_r_reg[2]_1\ : in STD_LOGIC;
    \read_fifo.fifo_out_data_r_reg[7]_1\ : in STD_LOGIC;
    \read_fifo.tail_r_reg[1]_0\ : in STD_LOGIC;
    \read_fifo.tail_r_reg[0]_1\ : in STD_LOGIC;
    \read_fifo.head_r_reg[0]_0\ : in STD_LOGIC;
    E : in STD_LOGIC_VECTOR ( 0 to 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of mig_mig_7series_v4_2_col_mach : entity is "mig_7series_v4_2_col_mach";
end mig_mig_7series_v4_2_col_mach;

architecture STRUCTURE of mig_mig_7series_v4_2_col_mach is
  signal \^col_rd_wr_r1\ : STD_LOGIC;
  signal mc_ref_zq_wip_r_i_2_n_0 : STD_LOGIC;
  signal p_0_in : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal \read_fifo.fifo_out_data_ns\ : STD_LOGIC_VECTOR ( 7 downto 6 );
  signal \read_fifo.head_r\ : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal \read_fifo.tail_ns\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \read_fifo.tail_r\ : STD_LOGIC_VECTOR ( 4 downto 3 );
  signal \read_fifo.tail_r[1]_i_1_n_0\ : STD_LOGIC;
  signal \read_fifo.tail_r[2]_i_1_n_0\ : STD_LOGIC;
  signal \read_fifo.tail_r[3]_i_1_n_0\ : STD_LOGIC;
  signal \read_fifo.tail_r[4]_i_1_n_0\ : STD_LOGIC;
  signal \^read_fifo.tail_r_reg[0]_0\ : STD_LOGIC;
  signal \^read_fifo.tail_r_reg[2]_0\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_read_fifo.fifo_ram[1].RAM32M0_DOA_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_read_fifo.fifo_ram[1].RAM32M0_DOB_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_read_fifo.fifo_ram[1].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  attribute BOX_TYPE : string;
  attribute BOX_TYPE of \read_fifo.fifo_ram[1].RAM32M0\ : label is "PRIMITIVE";
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \read_fifo.head_r[1]_i_1\ : label is "soft_lutpair1197";
  attribute SOFT_HLUTNM of \read_fifo.head_r[2]_i_1\ : label is "soft_lutpair1197";
  attribute SOFT_HLUTNM of \read_fifo.head_r[3]_i_1\ : label is "soft_lutpair1196";
  attribute SOFT_HLUTNM of \read_fifo.head_r[4]_i_1\ : label is "soft_lutpair1196";
  attribute SOFT_HLUTNM of \read_fifo.tail_r[2]_i_1\ : label is "soft_lutpair1195";
  attribute SOFT_HLUTNM of \read_fifo.tail_r[3]_i_1\ : label is "soft_lutpair1195";
begin
  col_rd_wr_r1 <= \^col_rd_wr_r1\;
  \read_fifo.tail_r_reg[0]_0\ <= \^read_fifo.tail_r_reg[0]_0\;
  \read_fifo.tail_r_reg[2]_0\(1 downto 0) <= \^read_fifo.tail_r_reg[2]_0\(1 downto 0);
\delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \read_fifo.head_r_reg[4]_0\,
      CE => '1',
      D => col_wr_data_buf_addr(0),
      Q => D(0),
      R => '0'
    );
\delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \read_fifo.head_r_reg[4]_0\,
      CE => '1',
      D => col_wr_data_buf_addr(1),
      Q => D(1),
      R => '0'
    );
\delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \read_fifo.head_r_reg[4]_0\,
      CE => '1',
      D => col_wr_data_buf_addr(2),
      Q => D(2),
      R => '0'
    );
\delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => \read_fifo.head_r_reg[4]_0\,
      CE => '1',
      D => col_wr_data_buf_addr(3),
      Q => D(3),
      R => '0'
    );
\i___92_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"9555555555555555"
    )
        port map (
      I0 => \read_fifo.tail_r\(4),
      I1 => \^read_fifo.tail_r_reg[2]_0\(0),
      I2 => \read_fifo.tail_r_reg[2]_1\,
      I3 => \^read_fifo.tail_r_reg[0]_0\,
      I4 => \^read_fifo.tail_r_reg[2]_0\(1),
      I5 => \read_fifo.tail_r\(3),
      O => \read_fifo.tail_r_reg[4]_1\
    );
mc_read_idle_r_i_2: unisim.vcomponents.LUT5
    generic map(
      INIT => X"09000009"
    )
        port map (
      I0 => \read_fifo.tail_r\(4),
      I1 => \read_fifo.head_r\(4),
      I2 => mc_ref_zq_wip_r_i_2_n_0,
      I3 => \read_fifo.head_r\(3),
      I4 => \read_fifo.tail_r\(3),
      O => \read_fifo.tail_r_reg[4]_0\
    );
mc_ref_zq_wip_r_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0082000000000082"
    )
        port map (
      I0 => maint_ref_zq_wip,
      I1 => \read_fifo.tail_r\(4),
      I2 => \read_fifo.head_r\(4),
      I3 => mc_ref_zq_wip_r_i_2_n_0,
      I4 => \read_fifo.head_r\(3),
      I5 => \read_fifo.tail_r\(3),
      O => mc_ref_zq_wip_ns
    );
mc_ref_zq_wip_r_i_2: unisim.vcomponents.LUT6
    generic map(
      INIT => X"6FF6FFFFFFFF6FF6"
    )
        port map (
      I0 => \read_fifo.head_r\(1),
      I1 => \^read_fifo.tail_r_reg[2]_0\(0),
      I2 => \read_fifo.head_r\(2),
      I3 => \^read_fifo.tail_r_reg[2]_0\(1),
      I4 => \^read_fifo.tail_r_reg[0]_0\,
      I5 => \read_fifo.head_r\(0),
      O => mc_ref_zq_wip_r_i_2_n_0
    );
\offset_pipe_0.col_rd_wr_r1_reg\: unisim.vcomponents.FDRE
     port map (
      C => \read_fifo.head_r_reg[4]_0\,
      CE => '1',
      D => col_rd_wr,
      Q => \^col_rd_wr_r1\,
      R => '0'
    );
\offset_pipe_1.col_rd_wr_r2_reg\: unisim.vcomponents.FDRE
     port map (
      C => \read_fifo.head_r_reg[4]_0\,
      CE => '1',
      D => \^col_rd_wr_r1\,
      Q => col_rd_wr_r2,
      R => '0'
    );
\read_fifo.fifo_out_data_r_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => \read_fifo.head_r_reg[4]_0\,
      CE => '1',
      D => \read_fifo.fifo_out_data_ns\(6),
      Q => \read_fifo.fifo_out_data_r_reg[7]_0\(0),
      R => '0'
    );
\read_fifo.fifo_out_data_r_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => \read_fifo.head_r_reg[4]_0\,
      CE => '1',
      D => \read_fifo.fifo_out_data_ns\(7),
      Q => \read_fifo.fifo_out_data_r_reg[7]_0\(1),
      R => '0'
    );
\read_fifo.fifo_ram[1].RAM32M0\: unisim.vcomponents.RAM32M
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      IS_WCLK_INVERTED => '0'
    )
        port map (
      ADDRA(4) => ADDRA(2),
      ADDRA(3) => \read_fifo.tail_ns\(3),
      ADDRA(2 downto 1) => ADDRA(1 downto 0),
      ADDRA(0) => \read_fifo.tail_ns\(0),
      ADDRB(4) => ADDRA(2),
      ADDRB(3) => \read_fifo.tail_ns\(3),
      ADDRB(2 downto 1) => ADDRA(1 downto 0),
      ADDRB(0) => \read_fifo.tail_ns\(0),
      ADDRC(4) => ADDRA(2),
      ADDRC(3) => \read_fifo.tail_ns\(3),
      ADDRC(2 downto 1) => ADDRA(1 downto 0),
      ADDRC(0) => \read_fifo.tail_ns\(0),
      ADDRD(4 downto 0) => \read_fifo.head_r\(4 downto 0),
      DIA(1 downto 0) => B"00",
      DIB(1 downto 0) => B"00",
      DIC(1) => '1',
      DIC(0) => DIC(0),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => \NLW_read_fifo.fifo_ram[1].RAM32M0_DOA_UNCONNECTED\(1 downto 0),
      DOB(1 downto 0) => \NLW_read_fifo.fifo_ram[1].RAM32M0_DOB_UNCONNECTED\(1 downto 0),
      DOC(1 downto 0) => \read_fifo.fifo_out_data_ns\(7 downto 6),
      DOD(1 downto 0) => \NLW_read_fifo.fifo_ram[1].RAM32M0_DOD_UNCONNECTED\(1 downto 0),
      WCLK => \read_fifo.head_r_reg[4]_0\,
      WE => '1'
    );
\read_fifo.fifo_ram[1].RAM32M0_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"000000007FFF8000"
    )
        port map (
      I0 => \^read_fifo.tail_r_reg[2]_0\(0),
      I1 => \read_fifo.tail_r_reg[2]_1\,
      I2 => \^read_fifo.tail_r_reg[0]_0\,
      I3 => \^read_fifo.tail_r_reg[2]_0\(1),
      I4 => \read_fifo.tail_r\(3),
      I5 => \read_fifo.fifo_out_data_r_reg[7]_1\,
      O => \read_fifo.tail_ns\(3)
    );
\read_fifo.fifo_ram[1].RAM32M0_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"06"
    )
        port map (
      I0 => \^read_fifo.tail_r_reg[0]_0\,
      I1 => \read_fifo.tail_r_reg[2]_1\,
      I2 => \read_fifo.fifo_out_data_r_reg[7]_1\,
      O => \read_fifo.tail_ns\(0)
    );
\read_fifo.head_r[0]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \read_fifo.head_r\(0),
      O => p_0_in(0)
    );
\read_fifo.head_r[1]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \read_fifo.head_r\(0),
      I1 => \read_fifo.head_r\(1),
      O => p_0_in(1)
    );
\read_fifo.head_r[2]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"6A"
    )
        port map (
      I0 => \read_fifo.head_r\(2),
      I1 => \read_fifo.head_r\(1),
      I2 => \read_fifo.head_r\(0),
      O => p_0_in(2)
    );
\read_fifo.head_r[3]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6AAA"
    )
        port map (
      I0 => \read_fifo.head_r\(3),
      I1 => \read_fifo.head_r\(0),
      I2 => \read_fifo.head_r\(1),
      I3 => \read_fifo.head_r\(2),
      O => p_0_in(3)
    );
\read_fifo.head_r[4]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"6AAAAAAA"
    )
        port map (
      I0 => \read_fifo.head_r\(4),
      I1 => \read_fifo.head_r\(2),
      I2 => \read_fifo.head_r\(1),
      I3 => \read_fifo.head_r\(0),
      I4 => \read_fifo.head_r\(3),
      O => p_0_in(4)
    );
\read_fifo.head_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \read_fifo.head_r_reg[4]_0\,
      CE => E(0),
      D => p_0_in(0),
      Q => \read_fifo.head_r\(0),
      R => \read_fifo.head_r_reg[0]_0\
    );
\read_fifo.head_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \read_fifo.head_r_reg[4]_0\,
      CE => E(0),
      D => p_0_in(1),
      Q => \read_fifo.head_r\(1),
      R => \read_fifo.head_r_reg[0]_0\
    );
\read_fifo.head_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \read_fifo.head_r_reg[4]_0\,
      CE => E(0),
      D => p_0_in(2),
      Q => \read_fifo.head_r\(2),
      R => \read_fifo.head_r_reg[0]_0\
    );
\read_fifo.head_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => \read_fifo.head_r_reg[4]_0\,
      CE => E(0),
      D => p_0_in(3),
      Q => \read_fifo.head_r\(3),
      R => \read_fifo.head_r_reg[0]_0\
    );
\read_fifo.head_r_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => \read_fifo.head_r_reg[4]_0\,
      CE => E(0),
      D => p_0_in(4),
      Q => \read_fifo.head_r\(4),
      R => \read_fifo.head_r_reg[0]_0\
    );
\read_fifo.tail_r[1]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"78"
    )
        port map (
      I0 => \read_fifo.tail_r_reg[2]_1\,
      I1 => \^read_fifo.tail_r_reg[0]_0\,
      I2 => \^read_fifo.tail_r_reg[2]_0\(0),
      O => \read_fifo.tail_r[1]_i_1_n_0\
    );
\read_fifo.tail_r[2]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7F80"
    )
        port map (
      I0 => \^read_fifo.tail_r_reg[0]_0\,
      I1 => \read_fifo.tail_r_reg[2]_1\,
      I2 => \^read_fifo.tail_r_reg[2]_0\(0),
      I3 => \^read_fifo.tail_r_reg[2]_0\(1),
      O => \read_fifo.tail_r[2]_i_1_n_0\
    );
\read_fifo.tail_r[3]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"6AAAAAAA"
    )
        port map (
      I0 => \read_fifo.tail_r\(3),
      I1 => \^read_fifo.tail_r_reg[2]_0\(1),
      I2 => \^read_fifo.tail_r_reg[0]_0\,
      I3 => \read_fifo.tail_r_reg[2]_1\,
      I4 => \^read_fifo.tail_r_reg[2]_0\(0),
      O => \read_fifo.tail_r[3]_i_1_n_0\
    );
\read_fifo.tail_r[4]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"7FFFFFFF80000000"
    )
        port map (
      I0 => \read_fifo.tail_r\(3),
      I1 => \^read_fifo.tail_r_reg[2]_0\(1),
      I2 => \^read_fifo.tail_r_reg[0]_0\,
      I3 => \read_fifo.tail_r_reg[2]_1\,
      I4 => \^read_fifo.tail_r_reg[2]_0\(0),
      I5 => \read_fifo.tail_r\(4),
      O => \read_fifo.tail_r[4]_i_1_n_0\
    );
\read_fifo.tail_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \read_fifo.head_r_reg[4]_0\,
      CE => '1',
      D => \read_fifo.tail_r_reg[0]_1\,
      Q => \^read_fifo.tail_r_reg[0]_0\,
      R => \read_fifo.tail_r_reg[1]_0\
    );
\read_fifo.tail_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \read_fifo.head_r_reg[4]_0\,
      CE => '1',
      D => \read_fifo.tail_r[1]_i_1_n_0\,
      Q => \^read_fifo.tail_r_reg[2]_0\(0),
      R => \read_fifo.tail_r_reg[1]_0\
    );
\read_fifo.tail_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \read_fifo.head_r_reg[4]_0\,
      CE => '1',
      D => \read_fifo.tail_r[2]_i_1_n_0\,
      Q => \^read_fifo.tail_r_reg[2]_0\(1),
      R => \read_fifo.tail_r_reg[1]_0\
    );
\read_fifo.tail_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => \read_fifo.head_r_reg[4]_0\,
      CE => '1',
      D => \read_fifo.tail_r[3]_i_1_n_0\,
      Q => \read_fifo.tail_r\(3),
      R => \read_fifo.tail_r_reg[1]_0\
    );
\read_fifo.tail_r_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => \read_fifo.head_r_reg[4]_0\,
      CE => '1',
      D => \read_fifo.tail_r[4]_i_1_n_0\,
      Q => \read_fifo.tail_r\(4),
      R => \read_fifo.tail_r_reg[1]_0\
    );
sent_col_r2_reg: unisim.vcomponents.FDRE
     port map (
      C => \read_fifo.head_r_reg[4]_0\,
      CE => '1',
      D => mc_cmd(0),
      Q => sent_col_r2,
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mig_mig_7series_v4_2_ddr_byte_group_io is
  port (
    out_dqs_0 : out STD_LOGIC;
    ts_dqs_0 : out STD_LOGIC;
    D1 : out STD_LOGIC_VECTOR ( 3 downto 0 );
    D2 : out STD_LOGIC_VECTOR ( 3 downto 0 );
    D3 : out STD_LOGIC_VECTOR ( 3 downto 0 );
    D4 : out STD_LOGIC_VECTOR ( 3 downto 0 );
    D5 : out STD_LOGIC_VECTOR ( 3 downto 0 );
    D6 : out STD_LOGIC_VECTOR ( 3 downto 0 );
    D7 : out STD_LOGIC_VECTOR ( 3 downto 0 );
    D9 : out STD_LOGIC_VECTOR ( 3 downto 0 );
    mem_dq_out : out STD_LOGIC_VECTOR ( 8 downto 0 );
    mem_dq_ts : out STD_LOGIC_VECTOR ( 8 downto 0 );
    idelay_ld_rst_3 : out STD_LOGIC;
    oserdes_clk : in STD_LOGIC;
    oserdes_clkdiv : in STD_LOGIC;
    po_oserdes_rst : in STD_LOGIC;
    DTSBUS : in STD_LOGIC_VECTOR ( 1 downto 0 );
    oserdes_clk_delayed : in STD_LOGIC;
    DQSBUS : in STD_LOGIC_VECTOR ( 1 downto 0 );
    CTSBUS : in STD_LOGIC_VECTOR ( 0 to 0 );
    idelay_ld_rst_reg_0 : in STD_LOGIC;
    \input_[9].iserdes_dq_.iserdesdq_0\ : in STD_LOGIC;
    mem_dq_in : in STD_LOGIC_VECTOR ( 7 downto 0 );
    idelay_inc : in STD_LOGIC;
    LD0_10 : in STD_LOGIC;
    A_rst_primitives : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]\ : in STD_LOGIC;
    CLKB0_10 : in STD_LOGIC;
    iserdes_clkdiv : in STD_LOGIC;
    of_dqbus : in STD_LOGIC_VECTOR ( 35 downto 0 );
    rst_r4 : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of mig_mig_7series_v4_2_ddr_byte_group_io : entity is "mig_7series_v4_2_ddr_byte_group_io";
end mig_mig_7series_v4_2_ddr_byte_group_io;

architecture STRUCTURE of mig_mig_7series_v4_2_ddr_byte_group_io is
  signal data_in_dly_1 : STD_LOGIC;
  signal data_in_dly_2 : STD_LOGIC;
  signal data_in_dly_3 : STD_LOGIC;
  signal data_in_dly_4 : STD_LOGIC;
  signal data_in_dly_5 : STD_LOGIC;
  signal data_in_dly_6 : STD_LOGIC;
  signal data_in_dly_7 : STD_LOGIC;
  signal data_in_dly_9 : STD_LOGIC;
  signal \^idelay_ld_rst_3\ : STD_LOGIC;
  signal \idelay_ld_rst_i_1__3_n_0\ : STD_LOGIC;
  signal tbyte_out : STD_LOGIC;
  signal \NLW_dqs_gen.oddr_dqs_S_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_dqs_gen.oddr_dqsts_R_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[1].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal \NLW_input_[1].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[1].iserdes_dq_.iserdesdq_O_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[1].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[1].iserdes_dq_.iserdesdq_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[1].iserdes_dq_.iserdesdq_Q5_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[1].iserdes_dq_.iserdesdq_Q6_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[1].iserdes_dq_.iserdesdq_Q7_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[1].iserdes_dq_.iserdesdq_Q8_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[1].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[1].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[2].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal \NLW_input_[2].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[2].iserdes_dq_.iserdesdq_O_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[2].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[2].iserdes_dq_.iserdesdq_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[2].iserdes_dq_.iserdesdq_Q5_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[2].iserdes_dq_.iserdesdq_Q6_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[2].iserdes_dq_.iserdesdq_Q7_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[2].iserdes_dq_.iserdesdq_Q8_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[2].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[2].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[3].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal \NLW_input_[3].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[3].iserdes_dq_.iserdesdq_O_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[3].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[3].iserdes_dq_.iserdesdq_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[3].iserdes_dq_.iserdesdq_Q5_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[3].iserdes_dq_.iserdesdq_Q6_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[3].iserdes_dq_.iserdesdq_Q7_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[3].iserdes_dq_.iserdesdq_Q8_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[3].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[3].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[4].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal \NLW_input_[4].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[4].iserdes_dq_.iserdesdq_O_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[4].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[4].iserdes_dq_.iserdesdq_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[4].iserdes_dq_.iserdesdq_Q5_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[4].iserdes_dq_.iserdesdq_Q6_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[4].iserdes_dq_.iserdesdq_Q7_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[4].iserdes_dq_.iserdesdq_Q8_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[4].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[4].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[5].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal \NLW_input_[5].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[5].iserdes_dq_.iserdesdq_O_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[5].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[5].iserdes_dq_.iserdesdq_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[5].iserdes_dq_.iserdesdq_Q5_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[5].iserdes_dq_.iserdesdq_Q6_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[5].iserdes_dq_.iserdesdq_Q7_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[5].iserdes_dq_.iserdesdq_Q8_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[5].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[5].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[6].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal \NLW_input_[6].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[6].iserdes_dq_.iserdesdq_O_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[6].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[6].iserdes_dq_.iserdesdq_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[6].iserdes_dq_.iserdesdq_Q5_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[6].iserdes_dq_.iserdesdq_Q6_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[6].iserdes_dq_.iserdesdq_Q7_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[6].iserdes_dq_.iserdesdq_Q8_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[6].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[6].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[7].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal \NLW_input_[7].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[7].iserdes_dq_.iserdesdq_O_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[7].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[7].iserdes_dq_.iserdesdq_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[7].iserdes_dq_.iserdesdq_Q5_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[7].iserdes_dq_.iserdesdq_Q6_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[7].iserdes_dq_.iserdesdq_Q7_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[7].iserdes_dq_.iserdesdq_Q8_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[7].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[7].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[9].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal \NLW_input_[9].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[9].iserdes_dq_.iserdesdq_O_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[9].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[9].iserdes_dq_.iserdesdq_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[9].iserdes_dq_.iserdesdq_Q5_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[9].iserdes_dq_.iserdesdq_Q6_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[9].iserdes_dq_.iserdesdq_Q7_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[9].iserdes_dq_.iserdesdq_Q8_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[9].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[9].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[0].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[0].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[0].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[0].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[0].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[0].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[0].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_slave_ts.oserdes_slave_ts_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_slave_ts.oserdes_slave_ts_OQ_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_slave_ts.oserdes_slave_ts_SHIFTIN1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_slave_ts.oserdes_slave_ts_SHIFTIN2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_slave_ts.oserdes_slave_ts_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_slave_ts.oserdes_slave_ts_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_slave_ts.oserdes_slave_ts_TFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_slave_ts.oserdes_slave_ts_TQ_UNCONNECTED\ : STD_LOGIC;
  attribute BOX_TYPE : string;
  attribute BOX_TYPE of \dqs_gen.oddr_dqs\ : label is "PRIMITIVE";
  attribute \__SRVAL\ : string;
  attribute \__SRVAL\ of \dqs_gen.oddr_dqs\ : label is "FALSE";
  attribute BOX_TYPE of \dqs_gen.oddr_dqsts\ : label is "PRIMITIVE";
  attribute \__SRVAL\ of \dqs_gen.oddr_dqsts\ : label is "TRUE";
  attribute BOX_TYPE of \input_[1].iserdes_dq_.idelay_dq.idelaye2\ : label is "PRIMITIVE";
  attribute IODELAY_GROUP : string;
  attribute IODELAY_GROUP of \input_[1].iserdes_dq_.idelay_dq.idelaye2\ : label is "MIG_IODELAY_MIG0";
  attribute SIM_DELAY_D : integer;
  attribute SIM_DELAY_D of \input_[1].iserdes_dq_.idelay_dq.idelaye2\ : label is 0;
  attribute BOX_TYPE of \input_[1].iserdes_dq_.iserdesdq\ : label is "PRIMITIVE";
  attribute OPT_MODIFIED : string;
  attribute OPT_MODIFIED of \input_[1].iserdes_dq_.iserdesdq\ : label is "MLO";
  attribute BOX_TYPE of \input_[2].iserdes_dq_.idelay_dq.idelaye2\ : label is "PRIMITIVE";
  attribute IODELAY_GROUP of \input_[2].iserdes_dq_.idelay_dq.idelaye2\ : label is "MIG_IODELAY_MIG0";
  attribute SIM_DELAY_D of \input_[2].iserdes_dq_.idelay_dq.idelaye2\ : label is 0;
  attribute BOX_TYPE of \input_[2].iserdes_dq_.iserdesdq\ : label is "PRIMITIVE";
  attribute OPT_MODIFIED of \input_[2].iserdes_dq_.iserdesdq\ : label is "MLO";
  attribute BOX_TYPE of \input_[3].iserdes_dq_.idelay_dq.idelaye2\ : label is "PRIMITIVE";
  attribute IODELAY_GROUP of \input_[3].iserdes_dq_.idelay_dq.idelaye2\ : label is "MIG_IODELAY_MIG0";
  attribute SIM_DELAY_D of \input_[3].iserdes_dq_.idelay_dq.idelaye2\ : label is 0;
  attribute BOX_TYPE of \input_[3].iserdes_dq_.iserdesdq\ : label is "PRIMITIVE";
  attribute OPT_MODIFIED of \input_[3].iserdes_dq_.iserdesdq\ : label is "MLO";
  attribute BOX_TYPE of \input_[4].iserdes_dq_.idelay_dq.idelaye2\ : label is "PRIMITIVE";
  attribute IODELAY_GROUP of \input_[4].iserdes_dq_.idelay_dq.idelaye2\ : label is "MIG_IODELAY_MIG0";
  attribute SIM_DELAY_D of \input_[4].iserdes_dq_.idelay_dq.idelaye2\ : label is 0;
  attribute BOX_TYPE of \input_[4].iserdes_dq_.iserdesdq\ : label is "PRIMITIVE";
  attribute OPT_MODIFIED of \input_[4].iserdes_dq_.iserdesdq\ : label is "MLO";
  attribute BOX_TYPE of \input_[5].iserdes_dq_.idelay_dq.idelaye2\ : label is "PRIMITIVE";
  attribute IODELAY_GROUP of \input_[5].iserdes_dq_.idelay_dq.idelaye2\ : label is "MIG_IODELAY_MIG0";
  attribute SIM_DELAY_D of \input_[5].iserdes_dq_.idelay_dq.idelaye2\ : label is 0;
  attribute BOX_TYPE of \input_[5].iserdes_dq_.iserdesdq\ : label is "PRIMITIVE";
  attribute OPT_MODIFIED of \input_[5].iserdes_dq_.iserdesdq\ : label is "MLO";
  attribute BOX_TYPE of \input_[6].iserdes_dq_.idelay_dq.idelaye2\ : label is "PRIMITIVE";
  attribute IODELAY_GROUP of \input_[6].iserdes_dq_.idelay_dq.idelaye2\ : label is "MIG_IODELAY_MIG0";
  attribute SIM_DELAY_D of \input_[6].iserdes_dq_.idelay_dq.idelaye2\ : label is 0;
  attribute BOX_TYPE of \input_[6].iserdes_dq_.iserdesdq\ : label is "PRIMITIVE";
  attribute OPT_MODIFIED of \input_[6].iserdes_dq_.iserdesdq\ : label is "MLO";
  attribute BOX_TYPE of \input_[7].iserdes_dq_.idelay_dq.idelaye2\ : label is "PRIMITIVE";
  attribute IODELAY_GROUP of \input_[7].iserdes_dq_.idelay_dq.idelaye2\ : label is "MIG_IODELAY_MIG0";
  attribute SIM_DELAY_D of \input_[7].iserdes_dq_.idelay_dq.idelaye2\ : label is 0;
  attribute BOX_TYPE of \input_[7].iserdes_dq_.iserdesdq\ : label is "PRIMITIVE";
  attribute OPT_MODIFIED of \input_[7].iserdes_dq_.iserdesdq\ : label is "MLO";
  attribute BOX_TYPE of \input_[9].iserdes_dq_.idelay_dq.idelaye2\ : label is "PRIMITIVE";
  attribute IODELAY_GROUP of \input_[9].iserdes_dq_.idelay_dq.idelaye2\ : label is "MIG_IODELAY_MIG0";
  attribute SIM_DELAY_D of \input_[9].iserdes_dq_.idelay_dq.idelaye2\ : label is 0;
  attribute BOX_TYPE of \input_[9].iserdes_dq_.iserdesdq\ : label is "PRIMITIVE";
  attribute OPT_MODIFIED of \input_[9].iserdes_dq_.iserdesdq\ : label is "MLO";
  attribute BOX_TYPE of \output_[0].oserdes_dq_.ddr.oserdes_dq_i\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \output_[1].oserdes_dq_.ddr.oserdes_dq_i\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \output_[2].oserdes_dq_.ddr.oserdes_dq_i\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \output_[3].oserdes_dq_.ddr.oserdes_dq_i\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \output_[4].oserdes_dq_.ddr.oserdes_dq_i\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \output_[5].oserdes_dq_.ddr.oserdes_dq_i\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \output_[6].oserdes_dq_.ddr.oserdes_dq_i\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \output_[7].oserdes_dq_.ddr.oserdes_dq_i\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \output_[9].oserdes_dq_.ddr.oserdes_dq_i\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \slave_ts.oserdes_slave_ts\ : label is "PRIMITIVE";
begin
  idelay_ld_rst_3 <= \^idelay_ld_rst_3\;
\dqs_gen.oddr_dqs\: unisim.vcomponents.ODDR
    generic map(
      DDR_CLK_EDGE => "SAME_EDGE",
      INIT => '0',
      IS_C_INVERTED => '0',
      IS_D1_INVERTED => '0',
      IS_D2_INVERTED => '0',
      SRTYPE => "SYNC"
    )
        port map (
      C => oserdes_clk_delayed,
      CE => '1',
      D1 => DQSBUS(0),
      D2 => DQSBUS(1),
      Q => out_dqs_0,
      R => '0',
      S => \NLW_dqs_gen.oddr_dqs_S_UNCONNECTED\
    );
\dqs_gen.oddr_dqsts\: unisim.vcomponents.ODDR
    generic map(
      DDR_CLK_EDGE => "SAME_EDGE",
      INIT => '0',
      IS_C_INVERTED => '0',
      IS_D1_INVERTED => '0',
      IS_D2_INVERTED => '0',
      SRTYPE => "SYNC"
    )
        port map (
      C => oserdes_clk_delayed,
      CE => '1',
      D1 => CTSBUS(0),
      D2 => CTSBUS(0),
      Q => ts_dqs_0,
      R => \NLW_dqs_gen.oddr_dqsts_R_UNCONNECTED\,
      S => '0'
    );
\idelay_ld_rst_i_1__3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \^idelay_ld_rst_3\,
      I1 => rst_r4,
      O => \idelay_ld_rst_i_1__3_n_0\
    );
idelay_ld_rst_reg: unisim.vcomponents.FDSE
     port map (
      C => idelay_ld_rst_reg_0,
      CE => '1',
      D => \idelay_ld_rst_i_1__3_n_0\,
      Q => \^idelay_ld_rst_3\,
      S => A_rst_primitives
    );
\input_[1].iserdes_dq_.idelay_dq.idelaye2\: unisim.vcomponents.IDELAYE2
    generic map(
      CINVCTRL_SEL => "FALSE",
      DELAY_SRC => "IDATAIN",
      HIGH_PERFORMANCE_MODE => "TRUE",
      IDELAY_TYPE => "VARIABLE",
      IDELAY_VALUE => 0,
      IS_C_INVERTED => '0',
      IS_DATAIN_INVERTED => '0',
      IS_IDATAIN_INVERTED => '0',
      PIPE_SEL => "FALSE",
      REFCLK_FREQUENCY => 200.000000,
      SIGNAL_PATTERN => "DATA"
    )
        port map (
      C => idelay_ld_rst_reg_0,
      CE => \input_[9].iserdes_dq_.iserdesdq_0\,
      CINVCTRL => '0',
      CNTVALUEIN(4 downto 0) => B"00000",
      CNTVALUEOUT(4 downto 0) => \NLW_input_[1].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED\(4 downto 0),
      DATAIN => '0',
      DATAOUT => data_in_dly_1,
      IDATAIN => mem_dq_in(0),
      INC => idelay_inc,
      LD => LD0_10,
      LDPIPEEN => '0',
      REGRST => A_rst_primitives
    );
\input_[1].iserdes_dq_.iserdesdq\: unisim.vcomponents.ISERDESE2
    generic map(
      DATA_RATE => "DDR",
      DATA_WIDTH => 4,
      DYN_CLKDIV_INV_EN => "FALSE",
      DYN_CLK_INV_EN => "FALSE",
      INIT_Q1 => '0',
      INIT_Q2 => '0',
      INIT_Q3 => '0',
      INIT_Q4 => '0',
      INTERFACE_TYPE => "MEMORY_DDR3",
      IOBDELAY => "IFD",
      IS_CLKB_INVERTED => '1',
      IS_CLKDIVP_INVERTED => '0',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D_INVERTED => '0',
      IS_OCLKB_INVERTED => '0',
      IS_OCLK_INVERTED => '0',
      NUM_CE => 2,
      OFB_USED => "FALSE",
      SERDES_MODE => "MASTER",
      SRVAL_Q1 => '0',
      SRVAL_Q2 => '0',
      SRVAL_Q3 => '0',
      SRVAL_Q4 => '0'
    )
        port map (
      BITSLIP => '0',
      CE1 => '1',
      CE2 => '1',
      CLK => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]\,
      CLKB => CLKB0_10,
      CLKDIV => \NLW_input_[1].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED\,
      CLKDIVP => iserdes_clkdiv,
      D => mem_dq_in(0),
      DDLY => data_in_dly_1,
      DYNCLKDIVSEL => '0',
      DYNCLKSEL => '0',
      O => \NLW_input_[1].iserdes_dq_.iserdesdq_O_UNCONNECTED\,
      OCLK => oserdes_clk,
      OCLKB => \NLW_input_[1].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED\,
      OFB => \NLW_input_[1].iserdes_dq_.iserdesdq_OFB_UNCONNECTED\,
      Q1 => D1(3),
      Q2 => D1(2),
      Q3 => D1(1),
      Q4 => D1(0),
      Q5 => \NLW_input_[1].iserdes_dq_.iserdesdq_Q5_UNCONNECTED\,
      Q6 => \NLW_input_[1].iserdes_dq_.iserdesdq_Q6_UNCONNECTED\,
      Q7 => \NLW_input_[1].iserdes_dq_.iserdesdq_Q7_UNCONNECTED\,
      Q8 => \NLW_input_[1].iserdes_dq_.iserdesdq_Q8_UNCONNECTED\,
      RST => '0',
      SHIFTIN1 => '0',
      SHIFTIN2 => '0',
      SHIFTOUT1 => \NLW_input_[1].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_input_[1].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED\
    );
\input_[2].iserdes_dq_.idelay_dq.idelaye2\: unisim.vcomponents.IDELAYE2
    generic map(
      CINVCTRL_SEL => "FALSE",
      DELAY_SRC => "IDATAIN",
      HIGH_PERFORMANCE_MODE => "TRUE",
      IDELAY_TYPE => "VARIABLE",
      IDELAY_VALUE => 0,
      IS_C_INVERTED => '0',
      IS_DATAIN_INVERTED => '0',
      IS_IDATAIN_INVERTED => '0',
      PIPE_SEL => "FALSE",
      REFCLK_FREQUENCY => 200.000000,
      SIGNAL_PATTERN => "DATA"
    )
        port map (
      C => idelay_ld_rst_reg_0,
      CE => \input_[9].iserdes_dq_.iserdesdq_0\,
      CINVCTRL => '0',
      CNTVALUEIN(4 downto 0) => B"00000",
      CNTVALUEOUT(4 downto 0) => \NLW_input_[2].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED\(4 downto 0),
      DATAIN => '0',
      DATAOUT => data_in_dly_2,
      IDATAIN => mem_dq_in(1),
      INC => idelay_inc,
      LD => LD0_10,
      LDPIPEEN => '0',
      REGRST => A_rst_primitives
    );
\input_[2].iserdes_dq_.iserdesdq\: unisim.vcomponents.ISERDESE2
    generic map(
      DATA_RATE => "DDR",
      DATA_WIDTH => 4,
      DYN_CLKDIV_INV_EN => "FALSE",
      DYN_CLK_INV_EN => "FALSE",
      INIT_Q1 => '0',
      INIT_Q2 => '0',
      INIT_Q3 => '0',
      INIT_Q4 => '0',
      INTERFACE_TYPE => "MEMORY_DDR3",
      IOBDELAY => "IFD",
      IS_CLKB_INVERTED => '1',
      IS_CLKDIVP_INVERTED => '0',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D_INVERTED => '0',
      IS_OCLKB_INVERTED => '0',
      IS_OCLK_INVERTED => '0',
      NUM_CE => 2,
      OFB_USED => "FALSE",
      SERDES_MODE => "MASTER",
      SRVAL_Q1 => '0',
      SRVAL_Q2 => '0',
      SRVAL_Q3 => '0',
      SRVAL_Q4 => '0'
    )
        port map (
      BITSLIP => '0',
      CE1 => '1',
      CE2 => '1',
      CLK => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]\,
      CLKB => CLKB0_10,
      CLKDIV => \NLW_input_[2].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED\,
      CLKDIVP => iserdes_clkdiv,
      D => mem_dq_in(1),
      DDLY => data_in_dly_2,
      DYNCLKDIVSEL => '0',
      DYNCLKSEL => '0',
      O => \NLW_input_[2].iserdes_dq_.iserdesdq_O_UNCONNECTED\,
      OCLK => oserdes_clk,
      OCLKB => \NLW_input_[2].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED\,
      OFB => \NLW_input_[2].iserdes_dq_.iserdesdq_OFB_UNCONNECTED\,
      Q1 => D2(3),
      Q2 => D2(2),
      Q3 => D2(1),
      Q4 => D2(0),
      Q5 => \NLW_input_[2].iserdes_dq_.iserdesdq_Q5_UNCONNECTED\,
      Q6 => \NLW_input_[2].iserdes_dq_.iserdesdq_Q6_UNCONNECTED\,
      Q7 => \NLW_input_[2].iserdes_dq_.iserdesdq_Q7_UNCONNECTED\,
      Q8 => \NLW_input_[2].iserdes_dq_.iserdesdq_Q8_UNCONNECTED\,
      RST => '0',
      SHIFTIN1 => '0',
      SHIFTIN2 => '0',
      SHIFTOUT1 => \NLW_input_[2].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_input_[2].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED\
    );
\input_[3].iserdes_dq_.idelay_dq.idelaye2\: unisim.vcomponents.IDELAYE2
    generic map(
      CINVCTRL_SEL => "FALSE",
      DELAY_SRC => "IDATAIN",
      HIGH_PERFORMANCE_MODE => "TRUE",
      IDELAY_TYPE => "VARIABLE",
      IDELAY_VALUE => 0,
      IS_C_INVERTED => '0',
      IS_DATAIN_INVERTED => '0',
      IS_IDATAIN_INVERTED => '0',
      PIPE_SEL => "FALSE",
      REFCLK_FREQUENCY => 200.000000,
      SIGNAL_PATTERN => "DATA"
    )
        port map (
      C => idelay_ld_rst_reg_0,
      CE => \input_[9].iserdes_dq_.iserdesdq_0\,
      CINVCTRL => '0',
      CNTVALUEIN(4 downto 0) => B"00000",
      CNTVALUEOUT(4 downto 0) => \NLW_input_[3].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED\(4 downto 0),
      DATAIN => '0',
      DATAOUT => data_in_dly_3,
      IDATAIN => mem_dq_in(2),
      INC => idelay_inc,
      LD => LD0_10,
      LDPIPEEN => '0',
      REGRST => A_rst_primitives
    );
\input_[3].iserdes_dq_.iserdesdq\: unisim.vcomponents.ISERDESE2
    generic map(
      DATA_RATE => "DDR",
      DATA_WIDTH => 4,
      DYN_CLKDIV_INV_EN => "FALSE",
      DYN_CLK_INV_EN => "FALSE",
      INIT_Q1 => '0',
      INIT_Q2 => '0',
      INIT_Q3 => '0',
      INIT_Q4 => '0',
      INTERFACE_TYPE => "MEMORY_DDR3",
      IOBDELAY => "IFD",
      IS_CLKB_INVERTED => '1',
      IS_CLKDIVP_INVERTED => '0',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D_INVERTED => '0',
      IS_OCLKB_INVERTED => '0',
      IS_OCLK_INVERTED => '0',
      NUM_CE => 2,
      OFB_USED => "FALSE",
      SERDES_MODE => "MASTER",
      SRVAL_Q1 => '0',
      SRVAL_Q2 => '0',
      SRVAL_Q3 => '0',
      SRVAL_Q4 => '0'
    )
        port map (
      BITSLIP => '0',
      CE1 => '1',
      CE2 => '1',
      CLK => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]\,
      CLKB => CLKB0_10,
      CLKDIV => \NLW_input_[3].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED\,
      CLKDIVP => iserdes_clkdiv,
      D => mem_dq_in(2),
      DDLY => data_in_dly_3,
      DYNCLKDIVSEL => '0',
      DYNCLKSEL => '0',
      O => \NLW_input_[3].iserdes_dq_.iserdesdq_O_UNCONNECTED\,
      OCLK => oserdes_clk,
      OCLKB => \NLW_input_[3].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED\,
      OFB => \NLW_input_[3].iserdes_dq_.iserdesdq_OFB_UNCONNECTED\,
      Q1 => D3(3),
      Q2 => D3(2),
      Q3 => D3(1),
      Q4 => D3(0),
      Q5 => \NLW_input_[3].iserdes_dq_.iserdesdq_Q5_UNCONNECTED\,
      Q6 => \NLW_input_[3].iserdes_dq_.iserdesdq_Q6_UNCONNECTED\,
      Q7 => \NLW_input_[3].iserdes_dq_.iserdesdq_Q7_UNCONNECTED\,
      Q8 => \NLW_input_[3].iserdes_dq_.iserdesdq_Q8_UNCONNECTED\,
      RST => '0',
      SHIFTIN1 => '0',
      SHIFTIN2 => '0',
      SHIFTOUT1 => \NLW_input_[3].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_input_[3].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED\
    );
\input_[4].iserdes_dq_.idelay_dq.idelaye2\: unisim.vcomponents.IDELAYE2
    generic map(
      CINVCTRL_SEL => "FALSE",
      DELAY_SRC => "IDATAIN",
      HIGH_PERFORMANCE_MODE => "TRUE",
      IDELAY_TYPE => "VARIABLE",
      IDELAY_VALUE => 0,
      IS_C_INVERTED => '0',
      IS_DATAIN_INVERTED => '0',
      IS_IDATAIN_INVERTED => '0',
      PIPE_SEL => "FALSE",
      REFCLK_FREQUENCY => 200.000000,
      SIGNAL_PATTERN => "DATA"
    )
        port map (
      C => idelay_ld_rst_reg_0,
      CE => \input_[9].iserdes_dq_.iserdesdq_0\,
      CINVCTRL => '0',
      CNTVALUEIN(4 downto 0) => B"00000",
      CNTVALUEOUT(4 downto 0) => \NLW_input_[4].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED\(4 downto 0),
      DATAIN => '0',
      DATAOUT => data_in_dly_4,
      IDATAIN => mem_dq_in(3),
      INC => idelay_inc,
      LD => LD0_10,
      LDPIPEEN => '0',
      REGRST => A_rst_primitives
    );
\input_[4].iserdes_dq_.iserdesdq\: unisim.vcomponents.ISERDESE2
    generic map(
      DATA_RATE => "DDR",
      DATA_WIDTH => 4,
      DYN_CLKDIV_INV_EN => "FALSE",
      DYN_CLK_INV_EN => "FALSE",
      INIT_Q1 => '0',
      INIT_Q2 => '0',
      INIT_Q3 => '0',
      INIT_Q4 => '0',
      INTERFACE_TYPE => "MEMORY_DDR3",
      IOBDELAY => "IFD",
      IS_CLKB_INVERTED => '1',
      IS_CLKDIVP_INVERTED => '0',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D_INVERTED => '0',
      IS_OCLKB_INVERTED => '0',
      IS_OCLK_INVERTED => '0',
      NUM_CE => 2,
      OFB_USED => "FALSE",
      SERDES_MODE => "MASTER",
      SRVAL_Q1 => '0',
      SRVAL_Q2 => '0',
      SRVAL_Q3 => '0',
      SRVAL_Q4 => '0'
    )
        port map (
      BITSLIP => '0',
      CE1 => '1',
      CE2 => '1',
      CLK => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]\,
      CLKB => CLKB0_10,
      CLKDIV => \NLW_input_[4].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED\,
      CLKDIVP => iserdes_clkdiv,
      D => mem_dq_in(3),
      DDLY => data_in_dly_4,
      DYNCLKDIVSEL => '0',
      DYNCLKSEL => '0',
      O => \NLW_input_[4].iserdes_dq_.iserdesdq_O_UNCONNECTED\,
      OCLK => oserdes_clk,
      OCLKB => \NLW_input_[4].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED\,
      OFB => \NLW_input_[4].iserdes_dq_.iserdesdq_OFB_UNCONNECTED\,
      Q1 => D4(3),
      Q2 => D4(2),
      Q3 => D4(1),
      Q4 => D4(0),
      Q5 => \NLW_input_[4].iserdes_dq_.iserdesdq_Q5_UNCONNECTED\,
      Q6 => \NLW_input_[4].iserdes_dq_.iserdesdq_Q6_UNCONNECTED\,
      Q7 => \NLW_input_[4].iserdes_dq_.iserdesdq_Q7_UNCONNECTED\,
      Q8 => \NLW_input_[4].iserdes_dq_.iserdesdq_Q8_UNCONNECTED\,
      RST => '0',
      SHIFTIN1 => '0',
      SHIFTIN2 => '0',
      SHIFTOUT1 => \NLW_input_[4].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_input_[4].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED\
    );
\input_[5].iserdes_dq_.idelay_dq.idelaye2\: unisim.vcomponents.IDELAYE2
    generic map(
      CINVCTRL_SEL => "FALSE",
      DELAY_SRC => "IDATAIN",
      HIGH_PERFORMANCE_MODE => "TRUE",
      IDELAY_TYPE => "VARIABLE",
      IDELAY_VALUE => 0,
      IS_C_INVERTED => '0',
      IS_DATAIN_INVERTED => '0',
      IS_IDATAIN_INVERTED => '0',
      PIPE_SEL => "FALSE",
      REFCLK_FREQUENCY => 200.000000,
      SIGNAL_PATTERN => "DATA"
    )
        port map (
      C => idelay_ld_rst_reg_0,
      CE => \input_[9].iserdes_dq_.iserdesdq_0\,
      CINVCTRL => '0',
      CNTVALUEIN(4 downto 0) => B"00000",
      CNTVALUEOUT(4 downto 0) => \NLW_input_[5].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED\(4 downto 0),
      DATAIN => '0',
      DATAOUT => data_in_dly_5,
      IDATAIN => mem_dq_in(4),
      INC => idelay_inc,
      LD => LD0_10,
      LDPIPEEN => '0',
      REGRST => A_rst_primitives
    );
\input_[5].iserdes_dq_.iserdesdq\: unisim.vcomponents.ISERDESE2
    generic map(
      DATA_RATE => "DDR",
      DATA_WIDTH => 4,
      DYN_CLKDIV_INV_EN => "FALSE",
      DYN_CLK_INV_EN => "FALSE",
      INIT_Q1 => '0',
      INIT_Q2 => '0',
      INIT_Q3 => '0',
      INIT_Q4 => '0',
      INTERFACE_TYPE => "MEMORY_DDR3",
      IOBDELAY => "IFD",
      IS_CLKB_INVERTED => '1',
      IS_CLKDIVP_INVERTED => '0',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D_INVERTED => '0',
      IS_OCLKB_INVERTED => '0',
      IS_OCLK_INVERTED => '0',
      NUM_CE => 2,
      OFB_USED => "FALSE",
      SERDES_MODE => "MASTER",
      SRVAL_Q1 => '0',
      SRVAL_Q2 => '0',
      SRVAL_Q3 => '0',
      SRVAL_Q4 => '0'
    )
        port map (
      BITSLIP => '0',
      CE1 => '1',
      CE2 => '1',
      CLK => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]\,
      CLKB => CLKB0_10,
      CLKDIV => \NLW_input_[5].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED\,
      CLKDIVP => iserdes_clkdiv,
      D => mem_dq_in(4),
      DDLY => data_in_dly_5,
      DYNCLKDIVSEL => '0',
      DYNCLKSEL => '0',
      O => \NLW_input_[5].iserdes_dq_.iserdesdq_O_UNCONNECTED\,
      OCLK => oserdes_clk,
      OCLKB => \NLW_input_[5].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED\,
      OFB => \NLW_input_[5].iserdes_dq_.iserdesdq_OFB_UNCONNECTED\,
      Q1 => D5(3),
      Q2 => D5(2),
      Q3 => D5(1),
      Q4 => D5(0),
      Q5 => \NLW_input_[5].iserdes_dq_.iserdesdq_Q5_UNCONNECTED\,
      Q6 => \NLW_input_[5].iserdes_dq_.iserdesdq_Q6_UNCONNECTED\,
      Q7 => \NLW_input_[5].iserdes_dq_.iserdesdq_Q7_UNCONNECTED\,
      Q8 => \NLW_input_[5].iserdes_dq_.iserdesdq_Q8_UNCONNECTED\,
      RST => '0',
      SHIFTIN1 => '0',
      SHIFTIN2 => '0',
      SHIFTOUT1 => \NLW_input_[5].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_input_[5].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED\
    );
\input_[6].iserdes_dq_.idelay_dq.idelaye2\: unisim.vcomponents.IDELAYE2
    generic map(
      CINVCTRL_SEL => "FALSE",
      DELAY_SRC => "IDATAIN",
      HIGH_PERFORMANCE_MODE => "TRUE",
      IDELAY_TYPE => "VARIABLE",
      IDELAY_VALUE => 0,
      IS_C_INVERTED => '0',
      IS_DATAIN_INVERTED => '0',
      IS_IDATAIN_INVERTED => '0',
      PIPE_SEL => "FALSE",
      REFCLK_FREQUENCY => 200.000000,
      SIGNAL_PATTERN => "DATA"
    )
        port map (
      C => idelay_ld_rst_reg_0,
      CE => \input_[9].iserdes_dq_.iserdesdq_0\,
      CINVCTRL => '0',
      CNTVALUEIN(4 downto 0) => B"00000",
      CNTVALUEOUT(4 downto 0) => \NLW_input_[6].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED\(4 downto 0),
      DATAIN => '0',
      DATAOUT => data_in_dly_6,
      IDATAIN => mem_dq_in(5),
      INC => idelay_inc,
      LD => LD0_10,
      LDPIPEEN => '0',
      REGRST => A_rst_primitives
    );
\input_[6].iserdes_dq_.iserdesdq\: unisim.vcomponents.ISERDESE2
    generic map(
      DATA_RATE => "DDR",
      DATA_WIDTH => 4,
      DYN_CLKDIV_INV_EN => "FALSE",
      DYN_CLK_INV_EN => "FALSE",
      INIT_Q1 => '0',
      INIT_Q2 => '0',
      INIT_Q3 => '0',
      INIT_Q4 => '0',
      INTERFACE_TYPE => "MEMORY_DDR3",
      IOBDELAY => "IFD",
      IS_CLKB_INVERTED => '1',
      IS_CLKDIVP_INVERTED => '0',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D_INVERTED => '0',
      IS_OCLKB_INVERTED => '0',
      IS_OCLK_INVERTED => '0',
      NUM_CE => 2,
      OFB_USED => "FALSE",
      SERDES_MODE => "MASTER",
      SRVAL_Q1 => '0',
      SRVAL_Q2 => '0',
      SRVAL_Q3 => '0',
      SRVAL_Q4 => '0'
    )
        port map (
      BITSLIP => '0',
      CE1 => '1',
      CE2 => '1',
      CLK => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]\,
      CLKB => CLKB0_10,
      CLKDIV => \NLW_input_[6].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED\,
      CLKDIVP => iserdes_clkdiv,
      D => mem_dq_in(5),
      DDLY => data_in_dly_6,
      DYNCLKDIVSEL => '0',
      DYNCLKSEL => '0',
      O => \NLW_input_[6].iserdes_dq_.iserdesdq_O_UNCONNECTED\,
      OCLK => oserdes_clk,
      OCLKB => \NLW_input_[6].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED\,
      OFB => \NLW_input_[6].iserdes_dq_.iserdesdq_OFB_UNCONNECTED\,
      Q1 => D6(3),
      Q2 => D6(2),
      Q3 => D6(1),
      Q4 => D6(0),
      Q5 => \NLW_input_[6].iserdes_dq_.iserdesdq_Q5_UNCONNECTED\,
      Q6 => \NLW_input_[6].iserdes_dq_.iserdesdq_Q6_UNCONNECTED\,
      Q7 => \NLW_input_[6].iserdes_dq_.iserdesdq_Q7_UNCONNECTED\,
      Q8 => \NLW_input_[6].iserdes_dq_.iserdesdq_Q8_UNCONNECTED\,
      RST => '0',
      SHIFTIN1 => '0',
      SHIFTIN2 => '0',
      SHIFTOUT1 => \NLW_input_[6].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_input_[6].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED\
    );
\input_[7].iserdes_dq_.idelay_dq.idelaye2\: unisim.vcomponents.IDELAYE2
    generic map(
      CINVCTRL_SEL => "FALSE",
      DELAY_SRC => "IDATAIN",
      HIGH_PERFORMANCE_MODE => "TRUE",
      IDELAY_TYPE => "VARIABLE",
      IDELAY_VALUE => 0,
      IS_C_INVERTED => '0',
      IS_DATAIN_INVERTED => '0',
      IS_IDATAIN_INVERTED => '0',
      PIPE_SEL => "FALSE",
      REFCLK_FREQUENCY => 200.000000,
      SIGNAL_PATTERN => "DATA"
    )
        port map (
      C => idelay_ld_rst_reg_0,
      CE => \input_[9].iserdes_dq_.iserdesdq_0\,
      CINVCTRL => '0',
      CNTVALUEIN(4 downto 0) => B"00000",
      CNTVALUEOUT(4 downto 0) => \NLW_input_[7].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED\(4 downto 0),
      DATAIN => '0',
      DATAOUT => data_in_dly_7,
      IDATAIN => mem_dq_in(6),
      INC => idelay_inc,
      LD => LD0_10,
      LDPIPEEN => '0',
      REGRST => A_rst_primitives
    );
\input_[7].iserdes_dq_.iserdesdq\: unisim.vcomponents.ISERDESE2
    generic map(
      DATA_RATE => "DDR",
      DATA_WIDTH => 4,
      DYN_CLKDIV_INV_EN => "FALSE",
      DYN_CLK_INV_EN => "FALSE",
      INIT_Q1 => '0',
      INIT_Q2 => '0',
      INIT_Q3 => '0',
      INIT_Q4 => '0',
      INTERFACE_TYPE => "MEMORY_DDR3",
      IOBDELAY => "IFD",
      IS_CLKB_INVERTED => '1',
      IS_CLKDIVP_INVERTED => '0',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D_INVERTED => '0',
      IS_OCLKB_INVERTED => '0',
      IS_OCLK_INVERTED => '0',
      NUM_CE => 2,
      OFB_USED => "FALSE",
      SERDES_MODE => "MASTER",
      SRVAL_Q1 => '0',
      SRVAL_Q2 => '0',
      SRVAL_Q3 => '0',
      SRVAL_Q4 => '0'
    )
        port map (
      BITSLIP => '0',
      CE1 => '1',
      CE2 => '1',
      CLK => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]\,
      CLKB => CLKB0_10,
      CLKDIV => \NLW_input_[7].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED\,
      CLKDIVP => iserdes_clkdiv,
      D => mem_dq_in(6),
      DDLY => data_in_dly_7,
      DYNCLKDIVSEL => '0',
      DYNCLKSEL => '0',
      O => \NLW_input_[7].iserdes_dq_.iserdesdq_O_UNCONNECTED\,
      OCLK => oserdes_clk,
      OCLKB => \NLW_input_[7].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED\,
      OFB => \NLW_input_[7].iserdes_dq_.iserdesdq_OFB_UNCONNECTED\,
      Q1 => D7(3),
      Q2 => D7(2),
      Q3 => D7(1),
      Q4 => D7(0),
      Q5 => \NLW_input_[7].iserdes_dq_.iserdesdq_Q5_UNCONNECTED\,
      Q6 => \NLW_input_[7].iserdes_dq_.iserdesdq_Q6_UNCONNECTED\,
      Q7 => \NLW_input_[7].iserdes_dq_.iserdesdq_Q7_UNCONNECTED\,
      Q8 => \NLW_input_[7].iserdes_dq_.iserdesdq_Q8_UNCONNECTED\,
      RST => '0',
      SHIFTIN1 => '0',
      SHIFTIN2 => '0',
      SHIFTOUT1 => \NLW_input_[7].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_input_[7].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED\
    );
\input_[9].iserdes_dq_.idelay_dq.idelaye2\: unisim.vcomponents.IDELAYE2
    generic map(
      CINVCTRL_SEL => "FALSE",
      DELAY_SRC => "IDATAIN",
      HIGH_PERFORMANCE_MODE => "TRUE",
      IDELAY_TYPE => "VARIABLE",
      IDELAY_VALUE => 0,
      IS_C_INVERTED => '0',
      IS_DATAIN_INVERTED => '0',
      IS_IDATAIN_INVERTED => '0',
      PIPE_SEL => "FALSE",
      REFCLK_FREQUENCY => 200.000000,
      SIGNAL_PATTERN => "DATA"
    )
        port map (
      C => idelay_ld_rst_reg_0,
      CE => \input_[9].iserdes_dq_.iserdesdq_0\,
      CINVCTRL => '0',
      CNTVALUEIN(4 downto 0) => B"00000",
      CNTVALUEOUT(4 downto 0) => \NLW_input_[9].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED\(4 downto 0),
      DATAIN => '0',
      DATAOUT => data_in_dly_9,
      IDATAIN => mem_dq_in(7),
      INC => idelay_inc,
      LD => LD0_10,
      LDPIPEEN => '0',
      REGRST => A_rst_primitives
    );
\input_[9].iserdes_dq_.iserdesdq\: unisim.vcomponents.ISERDESE2
    generic map(
      DATA_RATE => "DDR",
      DATA_WIDTH => 4,
      DYN_CLKDIV_INV_EN => "FALSE",
      DYN_CLK_INV_EN => "FALSE",
      INIT_Q1 => '0',
      INIT_Q2 => '0',
      INIT_Q3 => '0',
      INIT_Q4 => '0',
      INTERFACE_TYPE => "MEMORY_DDR3",
      IOBDELAY => "IFD",
      IS_CLKB_INVERTED => '1',
      IS_CLKDIVP_INVERTED => '0',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D_INVERTED => '0',
      IS_OCLKB_INVERTED => '0',
      IS_OCLK_INVERTED => '0',
      NUM_CE => 2,
      OFB_USED => "FALSE",
      SERDES_MODE => "MASTER",
      SRVAL_Q1 => '0',
      SRVAL_Q2 => '0',
      SRVAL_Q3 => '0',
      SRVAL_Q4 => '0'
    )
        port map (
      BITSLIP => '0',
      CE1 => '1',
      CE2 => '1',
      CLK => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]\,
      CLKB => CLKB0_10,
      CLKDIV => \NLW_input_[9].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED\,
      CLKDIVP => iserdes_clkdiv,
      D => mem_dq_in(7),
      DDLY => data_in_dly_9,
      DYNCLKDIVSEL => '0',
      DYNCLKSEL => '0',
      O => \NLW_input_[9].iserdes_dq_.iserdesdq_O_UNCONNECTED\,
      OCLK => oserdes_clk,
      OCLKB => \NLW_input_[9].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED\,
      OFB => \NLW_input_[9].iserdes_dq_.iserdesdq_OFB_UNCONNECTED\,
      Q1 => D9(3),
      Q2 => D9(2),
      Q3 => D9(1),
      Q4 => D9(0),
      Q5 => \NLW_input_[9].iserdes_dq_.iserdesdq_Q5_UNCONNECTED\,
      Q6 => \NLW_input_[9].iserdes_dq_.iserdesdq_Q6_UNCONNECTED\,
      Q7 => \NLW_input_[9].iserdes_dq_.iserdesdq_Q7_UNCONNECTED\,
      Q8 => \NLW_input_[9].iserdes_dq_.iserdesdq_Q8_UNCONNECTED\,
      RST => '0',
      SHIFTIN1 => '0',
      SHIFTIN2 => '0',
      SHIFTOUT1 => \NLW_input_[9].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_input_[9].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED\
    );
\output_[0].oserdes_dq_.ddr.oserdes_dq_i\: unisim.vcomponents.OSERDESE2
    generic map(
      DATA_RATE_OQ => "DDR",
      DATA_RATE_TQ => "DDR",
      DATA_WIDTH => 4,
      INIT_OQ => '1',
      INIT_TQ => '1',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D1_INVERTED => '0',
      IS_D2_INVERTED => '0',
      IS_D3_INVERTED => '0',
      IS_D4_INVERTED => '0',
      IS_D5_INVERTED => '0',
      IS_D6_INVERTED => '0',
      IS_D7_INVERTED => '0',
      IS_D8_INVERTED => '0',
      IS_T1_INVERTED => '0',
      IS_T2_INVERTED => '0',
      IS_T3_INVERTED => '0',
      IS_T4_INVERTED => '0',
      SERDES_MODE => "MASTER",
      SRVAL_OQ => '1',
      SRVAL_TQ => '1',
      TBYTE_CTL => "TRUE",
      TBYTE_SRC => "FALSE",
      TRISTATE_WIDTH => 4
    )
        port map (
      CLK => oserdes_clk,
      CLKDIV => oserdes_clkdiv,
      D1 => of_dqbus(0),
      D2 => of_dqbus(1),
      D3 => of_dqbus(2),
      D4 => of_dqbus(3),
      D5 => '0',
      D6 => '0',
      D7 => '0',
      D8 => '0',
      OCE => '1',
      OFB => \NLW_output_[0].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\,
      OQ => mem_dq_out(0),
      RST => po_oserdes_rst,
      SHIFTIN1 => \NLW_output_[0].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\,
      SHIFTIN2 => \NLW_output_[0].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\,
      SHIFTOUT1 => \NLW_output_[0].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_output_[0].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\,
      T1 => '0',
      T2 => '0',
      T3 => '0',
      T4 => '0',
      TBYTEIN => tbyte_out,
      TBYTEOUT => \NLW_output_[0].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\,
      TCE => '1',
      TFB => \NLW_output_[0].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\,
      TQ => mem_dq_ts(0)
    );
\output_[1].oserdes_dq_.ddr.oserdes_dq_i\: unisim.vcomponents.OSERDESE2
    generic map(
      DATA_RATE_OQ => "DDR",
      DATA_RATE_TQ => "DDR",
      DATA_WIDTH => 4,
      INIT_OQ => '1',
      INIT_TQ => '1',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D1_INVERTED => '0',
      IS_D2_INVERTED => '0',
      IS_D3_INVERTED => '0',
      IS_D4_INVERTED => '0',
      IS_D5_INVERTED => '0',
      IS_D6_INVERTED => '0',
      IS_D7_INVERTED => '0',
      IS_D8_INVERTED => '0',
      IS_T1_INVERTED => '0',
      IS_T2_INVERTED => '0',
      IS_T3_INVERTED => '0',
      IS_T4_INVERTED => '0',
      SERDES_MODE => "MASTER",
      SRVAL_OQ => '1',
      SRVAL_TQ => '1',
      TBYTE_CTL => "TRUE",
      TBYTE_SRC => "FALSE",
      TRISTATE_WIDTH => 4
    )
        port map (
      CLK => oserdes_clk,
      CLKDIV => oserdes_clkdiv,
      D1 => of_dqbus(4),
      D2 => of_dqbus(5),
      D3 => of_dqbus(6),
      D4 => of_dqbus(7),
      D5 => '0',
      D6 => '0',
      D7 => '0',
      D8 => '0',
      OCE => '1',
      OFB => \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\,
      OQ => mem_dq_out(1),
      RST => po_oserdes_rst,
      SHIFTIN1 => \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\,
      SHIFTIN2 => \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\,
      SHIFTOUT1 => \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\,
      T1 => '0',
      T2 => '0',
      T3 => '0',
      T4 => '0',
      TBYTEIN => tbyte_out,
      TBYTEOUT => \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\,
      TCE => '1',
      TFB => \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\,
      TQ => mem_dq_ts(1)
    );
\output_[2].oserdes_dq_.ddr.oserdes_dq_i\: unisim.vcomponents.OSERDESE2
    generic map(
      DATA_RATE_OQ => "DDR",
      DATA_RATE_TQ => "DDR",
      DATA_WIDTH => 4,
      INIT_OQ => '1',
      INIT_TQ => '1',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D1_INVERTED => '0',
      IS_D2_INVERTED => '0',
      IS_D3_INVERTED => '0',
      IS_D4_INVERTED => '0',
      IS_D5_INVERTED => '0',
      IS_D6_INVERTED => '0',
      IS_D7_INVERTED => '0',
      IS_D8_INVERTED => '0',
      IS_T1_INVERTED => '0',
      IS_T2_INVERTED => '0',
      IS_T3_INVERTED => '0',
      IS_T4_INVERTED => '0',
      SERDES_MODE => "MASTER",
      SRVAL_OQ => '1',
      SRVAL_TQ => '1',
      TBYTE_CTL => "TRUE",
      TBYTE_SRC => "FALSE",
      TRISTATE_WIDTH => 4
    )
        port map (
      CLK => oserdes_clk,
      CLKDIV => oserdes_clkdiv,
      D1 => of_dqbus(8),
      D2 => of_dqbus(9),
      D3 => of_dqbus(10),
      D4 => of_dqbus(11),
      D5 => '0',
      D6 => '0',
      D7 => '0',
      D8 => '0',
      OCE => '1',
      OFB => \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\,
      OQ => mem_dq_out(2),
      RST => po_oserdes_rst,
      SHIFTIN1 => \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\,
      SHIFTIN2 => \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\,
      SHIFTOUT1 => \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\,
      T1 => '0',
      T2 => '0',
      T3 => '0',
      T4 => '0',
      TBYTEIN => tbyte_out,
      TBYTEOUT => \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\,
      TCE => '1',
      TFB => \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\,
      TQ => mem_dq_ts(2)
    );
\output_[3].oserdes_dq_.ddr.oserdes_dq_i\: unisim.vcomponents.OSERDESE2
    generic map(
      DATA_RATE_OQ => "DDR",
      DATA_RATE_TQ => "DDR",
      DATA_WIDTH => 4,
      INIT_OQ => '1',
      INIT_TQ => '1',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D1_INVERTED => '0',
      IS_D2_INVERTED => '0',
      IS_D3_INVERTED => '0',
      IS_D4_INVERTED => '0',
      IS_D5_INVERTED => '0',
      IS_D6_INVERTED => '0',
      IS_D7_INVERTED => '0',
      IS_D8_INVERTED => '0',
      IS_T1_INVERTED => '0',
      IS_T2_INVERTED => '0',
      IS_T3_INVERTED => '0',
      IS_T4_INVERTED => '0',
      SERDES_MODE => "MASTER",
      SRVAL_OQ => '1',
      SRVAL_TQ => '1',
      TBYTE_CTL => "TRUE",
      TBYTE_SRC => "FALSE",
      TRISTATE_WIDTH => 4
    )
        port map (
      CLK => oserdes_clk,
      CLKDIV => oserdes_clkdiv,
      D1 => of_dqbus(12),
      D2 => of_dqbus(13),
      D3 => of_dqbus(14),
      D4 => of_dqbus(15),
      D5 => '0',
      D6 => '0',
      D7 => '0',
      D8 => '0',
      OCE => '1',
      OFB => \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\,
      OQ => mem_dq_out(3),
      RST => po_oserdes_rst,
      SHIFTIN1 => \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\,
      SHIFTIN2 => \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\,
      SHIFTOUT1 => \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\,
      T1 => '0',
      T2 => '0',
      T3 => '0',
      T4 => '0',
      TBYTEIN => tbyte_out,
      TBYTEOUT => \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\,
      TCE => '1',
      TFB => \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\,
      TQ => mem_dq_ts(3)
    );
\output_[4].oserdes_dq_.ddr.oserdes_dq_i\: unisim.vcomponents.OSERDESE2
    generic map(
      DATA_RATE_OQ => "DDR",
      DATA_RATE_TQ => "DDR",
      DATA_WIDTH => 4,
      INIT_OQ => '1',
      INIT_TQ => '1',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D1_INVERTED => '0',
      IS_D2_INVERTED => '0',
      IS_D3_INVERTED => '0',
      IS_D4_INVERTED => '0',
      IS_D5_INVERTED => '0',
      IS_D6_INVERTED => '0',
      IS_D7_INVERTED => '0',
      IS_D8_INVERTED => '0',
      IS_T1_INVERTED => '0',
      IS_T2_INVERTED => '0',
      IS_T3_INVERTED => '0',
      IS_T4_INVERTED => '0',
      SERDES_MODE => "MASTER",
      SRVAL_OQ => '1',
      SRVAL_TQ => '1',
      TBYTE_CTL => "TRUE",
      TBYTE_SRC => "FALSE",
      TRISTATE_WIDTH => 4
    )
        port map (
      CLK => oserdes_clk,
      CLKDIV => oserdes_clkdiv,
      D1 => of_dqbus(16),
      D2 => of_dqbus(17),
      D3 => of_dqbus(18),
      D4 => of_dqbus(19),
      D5 => '0',
      D6 => '0',
      D7 => '0',
      D8 => '0',
      OCE => '1',
      OFB => \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\,
      OQ => mem_dq_out(4),
      RST => po_oserdes_rst,
      SHIFTIN1 => \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\,
      SHIFTIN2 => \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\,
      SHIFTOUT1 => \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\,
      T1 => '0',
      T2 => '0',
      T3 => '0',
      T4 => '0',
      TBYTEIN => tbyte_out,
      TBYTEOUT => \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\,
      TCE => '1',
      TFB => \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\,
      TQ => mem_dq_ts(4)
    );
\output_[5].oserdes_dq_.ddr.oserdes_dq_i\: unisim.vcomponents.OSERDESE2
    generic map(
      DATA_RATE_OQ => "DDR",
      DATA_RATE_TQ => "DDR",
      DATA_WIDTH => 4,
      INIT_OQ => '1',
      INIT_TQ => '1',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D1_INVERTED => '0',
      IS_D2_INVERTED => '0',
      IS_D3_INVERTED => '0',
      IS_D4_INVERTED => '0',
      IS_D5_INVERTED => '0',
      IS_D6_INVERTED => '0',
      IS_D7_INVERTED => '0',
      IS_D8_INVERTED => '0',
      IS_T1_INVERTED => '0',
      IS_T2_INVERTED => '0',
      IS_T3_INVERTED => '0',
      IS_T4_INVERTED => '0',
      SERDES_MODE => "MASTER",
      SRVAL_OQ => '1',
      SRVAL_TQ => '1',
      TBYTE_CTL => "TRUE",
      TBYTE_SRC => "FALSE",
      TRISTATE_WIDTH => 4
    )
        port map (
      CLK => oserdes_clk,
      CLKDIV => oserdes_clkdiv,
      D1 => of_dqbus(20),
      D2 => of_dqbus(21),
      D3 => of_dqbus(22),
      D4 => of_dqbus(23),
      D5 => '0',
      D6 => '0',
      D7 => '0',
      D8 => '0',
      OCE => '1',
      OFB => \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\,
      OQ => mem_dq_out(5),
      RST => po_oserdes_rst,
      SHIFTIN1 => \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\,
      SHIFTIN2 => \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\,
      SHIFTOUT1 => \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\,
      T1 => '0',
      T2 => '0',
      T3 => '0',
      T4 => '0',
      TBYTEIN => tbyte_out,
      TBYTEOUT => \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\,
      TCE => '1',
      TFB => \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\,
      TQ => mem_dq_ts(5)
    );
\output_[6].oserdes_dq_.ddr.oserdes_dq_i\: unisim.vcomponents.OSERDESE2
    generic map(
      DATA_RATE_OQ => "DDR",
      DATA_RATE_TQ => "DDR",
      DATA_WIDTH => 4,
      INIT_OQ => '1',
      INIT_TQ => '1',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D1_INVERTED => '0',
      IS_D2_INVERTED => '0',
      IS_D3_INVERTED => '0',
      IS_D4_INVERTED => '0',
      IS_D5_INVERTED => '0',
      IS_D6_INVERTED => '0',
      IS_D7_INVERTED => '0',
      IS_D8_INVERTED => '0',
      IS_T1_INVERTED => '0',
      IS_T2_INVERTED => '0',
      IS_T3_INVERTED => '0',
      IS_T4_INVERTED => '0',
      SERDES_MODE => "MASTER",
      SRVAL_OQ => '1',
      SRVAL_TQ => '1',
      TBYTE_CTL => "TRUE",
      TBYTE_SRC => "FALSE",
      TRISTATE_WIDTH => 4
    )
        port map (
      CLK => oserdes_clk,
      CLKDIV => oserdes_clkdiv,
      D1 => of_dqbus(24),
      D2 => of_dqbus(25),
      D3 => of_dqbus(26),
      D4 => of_dqbus(27),
      D5 => '0',
      D6 => '0',
      D7 => '0',
      D8 => '0',
      OCE => '1',
      OFB => \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\,
      OQ => mem_dq_out(6),
      RST => po_oserdes_rst,
      SHIFTIN1 => \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\,
      SHIFTIN2 => \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\,
      SHIFTOUT1 => \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\,
      T1 => '0',
      T2 => '0',
      T3 => '0',
      T4 => '0',
      TBYTEIN => tbyte_out,
      TBYTEOUT => \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\,
      TCE => '1',
      TFB => \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\,
      TQ => mem_dq_ts(6)
    );
\output_[7].oserdes_dq_.ddr.oserdes_dq_i\: unisim.vcomponents.OSERDESE2
    generic map(
      DATA_RATE_OQ => "DDR",
      DATA_RATE_TQ => "DDR",
      DATA_WIDTH => 4,
      INIT_OQ => '1',
      INIT_TQ => '1',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D1_INVERTED => '0',
      IS_D2_INVERTED => '0',
      IS_D3_INVERTED => '0',
      IS_D4_INVERTED => '0',
      IS_D5_INVERTED => '0',
      IS_D6_INVERTED => '0',
      IS_D7_INVERTED => '0',
      IS_D8_INVERTED => '0',
      IS_T1_INVERTED => '0',
      IS_T2_INVERTED => '0',
      IS_T3_INVERTED => '0',
      IS_T4_INVERTED => '0',
      SERDES_MODE => "MASTER",
      SRVAL_OQ => '1',
      SRVAL_TQ => '1',
      TBYTE_CTL => "TRUE",
      TBYTE_SRC => "FALSE",
      TRISTATE_WIDTH => 4
    )
        port map (
      CLK => oserdes_clk,
      CLKDIV => oserdes_clkdiv,
      D1 => of_dqbus(28),
      D2 => of_dqbus(29),
      D3 => of_dqbus(30),
      D4 => of_dqbus(31),
      D5 => '0',
      D6 => '0',
      D7 => '0',
      D8 => '0',
      OCE => '1',
      OFB => \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\,
      OQ => mem_dq_out(7),
      RST => po_oserdes_rst,
      SHIFTIN1 => \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\,
      SHIFTIN2 => \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\,
      SHIFTOUT1 => \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\,
      T1 => '0',
      T2 => '0',
      T3 => '0',
      T4 => '0',
      TBYTEIN => tbyte_out,
      TBYTEOUT => \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\,
      TCE => '1',
      TFB => \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\,
      TQ => mem_dq_ts(7)
    );
\output_[9].oserdes_dq_.ddr.oserdes_dq_i\: unisim.vcomponents.OSERDESE2
    generic map(
      DATA_RATE_OQ => "DDR",
      DATA_RATE_TQ => "DDR",
      DATA_WIDTH => 4,
      INIT_OQ => '1',
      INIT_TQ => '1',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D1_INVERTED => '0',
      IS_D2_INVERTED => '0',
      IS_D3_INVERTED => '0',
      IS_D4_INVERTED => '0',
      IS_D5_INVERTED => '0',
      IS_D6_INVERTED => '0',
      IS_D7_INVERTED => '0',
      IS_D8_INVERTED => '0',
      IS_T1_INVERTED => '0',
      IS_T2_INVERTED => '0',
      IS_T3_INVERTED => '0',
      IS_T4_INVERTED => '0',
      SERDES_MODE => "MASTER",
      SRVAL_OQ => '1',
      SRVAL_TQ => '1',
      TBYTE_CTL => "TRUE",
      TBYTE_SRC => "FALSE",
      TRISTATE_WIDTH => 4
    )
        port map (
      CLK => oserdes_clk,
      CLKDIV => oserdes_clkdiv,
      D1 => of_dqbus(32),
      D2 => of_dqbus(33),
      D3 => of_dqbus(34),
      D4 => of_dqbus(35),
      D5 => '0',
      D6 => '0',
      D7 => '0',
      D8 => '0',
      OCE => '1',
      OFB => \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\,
      OQ => mem_dq_out(8),
      RST => po_oserdes_rst,
      SHIFTIN1 => \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\,
      SHIFTIN2 => \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\,
      SHIFTOUT1 => \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\,
      T1 => '0',
      T2 => '0',
      T3 => '0',
      T4 => '0',
      TBYTEIN => tbyte_out,
      TBYTEOUT => \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\,
      TCE => '1',
      TFB => \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\,
      TQ => mem_dq_ts(8)
    );
\slave_ts.oserdes_slave_ts\: unisim.vcomponents.OSERDESE2
    generic map(
      DATA_RATE_OQ => "DDR",
      DATA_RATE_TQ => "DDR",
      DATA_WIDTH => 4,
      INIT_OQ => '1',
      INIT_TQ => '1',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D1_INVERTED => '0',
      IS_D2_INVERTED => '0',
      IS_D3_INVERTED => '0',
      IS_D4_INVERTED => '0',
      IS_D5_INVERTED => '0',
      IS_D6_INVERTED => '0',
      IS_D7_INVERTED => '0',
      IS_D8_INVERTED => '0',
      IS_T1_INVERTED => '0',
      IS_T2_INVERTED => '0',
      IS_T3_INVERTED => '0',
      IS_T4_INVERTED => '0',
      SERDES_MODE => "MASTER",
      SRVAL_OQ => '1',
      SRVAL_TQ => '1',
      TBYTE_CTL => "TRUE",
      TBYTE_SRC => "TRUE",
      TRISTATE_WIDTH => 4
    )
        port map (
      CLK => oserdes_clk,
      CLKDIV => oserdes_clkdiv,
      D1 => '0',
      D2 => '0',
      D3 => '0',
      D4 => '0',
      D5 => '0',
      D6 => '0',
      D7 => '0',
      D8 => '0',
      OCE => '1',
      OFB => \NLW_slave_ts.oserdes_slave_ts_OFB_UNCONNECTED\,
      OQ => \NLW_slave_ts.oserdes_slave_ts_OQ_UNCONNECTED\,
      RST => po_oserdes_rst,
      SHIFTIN1 => \NLW_slave_ts.oserdes_slave_ts_SHIFTIN1_UNCONNECTED\,
      SHIFTIN2 => \NLW_slave_ts.oserdes_slave_ts_SHIFTIN2_UNCONNECTED\,
      SHIFTOUT1 => \NLW_slave_ts.oserdes_slave_ts_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_slave_ts.oserdes_slave_ts_SHIFTOUT2_UNCONNECTED\,
      T1 => DTSBUS(0),
      T2 => DTSBUS(0),
      T3 => DTSBUS(1),
      T4 => DTSBUS(1),
      TBYTEIN => tbyte_out,
      TBYTEOUT => tbyte_out,
      TCE => '1',
      TFB => \NLW_slave_ts.oserdes_slave_ts_TFB_UNCONNECTED\,
      TQ => \NLW_slave_ts.oserdes_slave_ts_TQ_UNCONNECTED\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mig_mig_7series_v4_2_ddr_byte_group_io_38 is
  port (
    out_dqs_4 : out STD_LOGIC;
    ts_dqs_4 : out STD_LOGIC;
    D1 : out STD_LOGIC_VECTOR ( 3 downto 0 );
    D2 : out STD_LOGIC_VECTOR ( 3 downto 0 );
    D3 : out STD_LOGIC_VECTOR ( 3 downto 0 );
    D4 : out STD_LOGIC_VECTOR ( 3 downto 0 );
    D5 : out STD_LOGIC_VECTOR ( 3 downto 0 );
    D6 : out STD_LOGIC_VECTOR ( 3 downto 0 );
    D7 : out STD_LOGIC_VECTOR ( 3 downto 0 );
    D9 : out STD_LOGIC_VECTOR ( 3 downto 0 );
    mem_dq_out : out STD_LOGIC_VECTOR ( 8 downto 0 );
    mem_dq_ts : out STD_LOGIC_VECTOR ( 8 downto 0 );
    idelay_ld_rst : out STD_LOGIC;
    oserdes_clk : in STD_LOGIC;
    oserdes_clkdiv : in STD_LOGIC;
    po_oserdes_rst : in STD_LOGIC;
    DTSBUS : in STD_LOGIC_VECTOR ( 1 downto 0 );
    oserdes_clk_delayed : in STD_LOGIC;
    DQSBUS : in STD_LOGIC_VECTOR ( 1 downto 0 );
    CTSBUS : in STD_LOGIC_VECTOR ( 0 to 0 );
    idelay_ld_rst_reg_0 : in STD_LOGIC;
    \input_[9].iserdes_dq_.iserdesdq_0\ : in STD_LOGIC;
    mem_dq_in : in STD_LOGIC_VECTOR ( 7 downto 0 );
    idelay_inc : in STD_LOGIC;
    LD0 : in STD_LOGIC;
    A_rst_primitives : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]\ : in STD_LOGIC;
    CLKB0 : in STD_LOGIC;
    iserdes_clkdiv : in STD_LOGIC;
    of_dqbus : in STD_LOGIC_VECTOR ( 35 downto 0 );
    rst_r4 : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of mig_mig_7series_v4_2_ddr_byte_group_io_38 : entity is "mig_7series_v4_2_ddr_byte_group_io";
end mig_mig_7series_v4_2_ddr_byte_group_io_38;

architecture STRUCTURE of mig_mig_7series_v4_2_ddr_byte_group_io_38 is
  signal data_in_dly_1 : STD_LOGIC;
  signal data_in_dly_2 : STD_LOGIC;
  signal data_in_dly_3 : STD_LOGIC;
  signal data_in_dly_4 : STD_LOGIC;
  signal data_in_dly_5 : STD_LOGIC;
  signal data_in_dly_6 : STD_LOGIC;
  signal data_in_dly_7 : STD_LOGIC;
  signal data_in_dly_9 : STD_LOGIC;
  signal \^idelay_ld_rst\ : STD_LOGIC;
  signal idelay_ld_rst_i_1_n_0 : STD_LOGIC;
  signal tbyte_out : STD_LOGIC;
  signal \NLW_dqs_gen.oddr_dqs_S_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_dqs_gen.oddr_dqsts_R_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[1].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal \NLW_input_[1].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[1].iserdes_dq_.iserdesdq_O_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[1].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[1].iserdes_dq_.iserdesdq_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[1].iserdes_dq_.iserdesdq_Q5_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[1].iserdes_dq_.iserdesdq_Q6_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[1].iserdes_dq_.iserdesdq_Q7_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[1].iserdes_dq_.iserdesdq_Q8_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[1].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[1].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[2].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal \NLW_input_[2].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[2].iserdes_dq_.iserdesdq_O_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[2].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[2].iserdes_dq_.iserdesdq_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[2].iserdes_dq_.iserdesdq_Q5_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[2].iserdes_dq_.iserdesdq_Q6_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[2].iserdes_dq_.iserdesdq_Q7_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[2].iserdes_dq_.iserdesdq_Q8_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[2].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[2].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[3].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal \NLW_input_[3].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[3].iserdes_dq_.iserdesdq_O_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[3].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[3].iserdes_dq_.iserdesdq_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[3].iserdes_dq_.iserdesdq_Q5_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[3].iserdes_dq_.iserdesdq_Q6_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[3].iserdes_dq_.iserdesdq_Q7_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[3].iserdes_dq_.iserdesdq_Q8_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[3].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[3].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[4].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal \NLW_input_[4].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[4].iserdes_dq_.iserdesdq_O_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[4].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[4].iserdes_dq_.iserdesdq_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[4].iserdes_dq_.iserdesdq_Q5_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[4].iserdes_dq_.iserdesdq_Q6_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[4].iserdes_dq_.iserdesdq_Q7_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[4].iserdes_dq_.iserdesdq_Q8_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[4].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[4].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[5].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal \NLW_input_[5].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[5].iserdes_dq_.iserdesdq_O_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[5].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[5].iserdes_dq_.iserdesdq_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[5].iserdes_dq_.iserdesdq_Q5_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[5].iserdes_dq_.iserdesdq_Q6_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[5].iserdes_dq_.iserdesdq_Q7_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[5].iserdes_dq_.iserdesdq_Q8_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[5].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[5].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[6].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal \NLW_input_[6].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[6].iserdes_dq_.iserdesdq_O_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[6].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[6].iserdes_dq_.iserdesdq_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[6].iserdes_dq_.iserdesdq_Q5_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[6].iserdes_dq_.iserdesdq_Q6_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[6].iserdes_dq_.iserdesdq_Q7_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[6].iserdes_dq_.iserdesdq_Q8_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[6].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[6].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[7].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal \NLW_input_[7].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[7].iserdes_dq_.iserdesdq_O_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[7].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[7].iserdes_dq_.iserdesdq_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[7].iserdes_dq_.iserdesdq_Q5_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[7].iserdes_dq_.iserdesdq_Q6_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[7].iserdes_dq_.iserdesdq_Q7_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[7].iserdes_dq_.iserdesdq_Q8_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[7].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[7].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[9].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal \NLW_input_[9].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[9].iserdes_dq_.iserdesdq_O_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[9].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[9].iserdes_dq_.iserdesdq_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[9].iserdes_dq_.iserdesdq_Q5_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[9].iserdes_dq_.iserdesdq_Q6_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[9].iserdes_dq_.iserdesdq_Q7_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[9].iserdes_dq_.iserdesdq_Q8_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[9].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[9].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[0].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[0].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[0].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[0].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[0].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[0].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[0].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_slave_ts.oserdes_slave_ts_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_slave_ts.oserdes_slave_ts_OQ_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_slave_ts.oserdes_slave_ts_SHIFTIN1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_slave_ts.oserdes_slave_ts_SHIFTIN2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_slave_ts.oserdes_slave_ts_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_slave_ts.oserdes_slave_ts_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_slave_ts.oserdes_slave_ts_TFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_slave_ts.oserdes_slave_ts_TQ_UNCONNECTED\ : STD_LOGIC;
  attribute BOX_TYPE : string;
  attribute BOX_TYPE of \dqs_gen.oddr_dqs\ : label is "PRIMITIVE";
  attribute \__SRVAL\ : string;
  attribute \__SRVAL\ of \dqs_gen.oddr_dqs\ : label is "FALSE";
  attribute BOX_TYPE of \dqs_gen.oddr_dqsts\ : label is "PRIMITIVE";
  attribute \__SRVAL\ of \dqs_gen.oddr_dqsts\ : label is "TRUE";
  attribute BOX_TYPE of \input_[1].iserdes_dq_.idelay_dq.idelaye2\ : label is "PRIMITIVE";
  attribute IODELAY_GROUP : string;
  attribute IODELAY_GROUP of \input_[1].iserdes_dq_.idelay_dq.idelaye2\ : label is "MIG_IODELAY_MIG0";
  attribute SIM_DELAY_D : integer;
  attribute SIM_DELAY_D of \input_[1].iserdes_dq_.idelay_dq.idelaye2\ : label is 0;
  attribute BOX_TYPE of \input_[1].iserdes_dq_.iserdesdq\ : label is "PRIMITIVE";
  attribute OPT_MODIFIED : string;
  attribute OPT_MODIFIED of \input_[1].iserdes_dq_.iserdesdq\ : label is "MLO";
  attribute BOX_TYPE of \input_[2].iserdes_dq_.idelay_dq.idelaye2\ : label is "PRIMITIVE";
  attribute IODELAY_GROUP of \input_[2].iserdes_dq_.idelay_dq.idelaye2\ : label is "MIG_IODELAY_MIG0";
  attribute SIM_DELAY_D of \input_[2].iserdes_dq_.idelay_dq.idelaye2\ : label is 0;
  attribute BOX_TYPE of \input_[2].iserdes_dq_.iserdesdq\ : label is "PRIMITIVE";
  attribute OPT_MODIFIED of \input_[2].iserdes_dq_.iserdesdq\ : label is "MLO";
  attribute BOX_TYPE of \input_[3].iserdes_dq_.idelay_dq.idelaye2\ : label is "PRIMITIVE";
  attribute IODELAY_GROUP of \input_[3].iserdes_dq_.idelay_dq.idelaye2\ : label is "MIG_IODELAY_MIG0";
  attribute SIM_DELAY_D of \input_[3].iserdes_dq_.idelay_dq.idelaye2\ : label is 0;
  attribute BOX_TYPE of \input_[3].iserdes_dq_.iserdesdq\ : label is "PRIMITIVE";
  attribute OPT_MODIFIED of \input_[3].iserdes_dq_.iserdesdq\ : label is "MLO";
  attribute BOX_TYPE of \input_[4].iserdes_dq_.idelay_dq.idelaye2\ : label is "PRIMITIVE";
  attribute IODELAY_GROUP of \input_[4].iserdes_dq_.idelay_dq.idelaye2\ : label is "MIG_IODELAY_MIG0";
  attribute SIM_DELAY_D of \input_[4].iserdes_dq_.idelay_dq.idelaye2\ : label is 0;
  attribute BOX_TYPE of \input_[4].iserdes_dq_.iserdesdq\ : label is "PRIMITIVE";
  attribute OPT_MODIFIED of \input_[4].iserdes_dq_.iserdesdq\ : label is "MLO";
  attribute BOX_TYPE of \input_[5].iserdes_dq_.idelay_dq.idelaye2\ : label is "PRIMITIVE";
  attribute IODELAY_GROUP of \input_[5].iserdes_dq_.idelay_dq.idelaye2\ : label is "MIG_IODELAY_MIG0";
  attribute SIM_DELAY_D of \input_[5].iserdes_dq_.idelay_dq.idelaye2\ : label is 0;
  attribute BOX_TYPE of \input_[5].iserdes_dq_.iserdesdq\ : label is "PRIMITIVE";
  attribute OPT_MODIFIED of \input_[5].iserdes_dq_.iserdesdq\ : label is "MLO";
  attribute BOX_TYPE of \input_[6].iserdes_dq_.idelay_dq.idelaye2\ : label is "PRIMITIVE";
  attribute IODELAY_GROUP of \input_[6].iserdes_dq_.idelay_dq.idelaye2\ : label is "MIG_IODELAY_MIG0";
  attribute SIM_DELAY_D of \input_[6].iserdes_dq_.idelay_dq.idelaye2\ : label is 0;
  attribute BOX_TYPE of \input_[6].iserdes_dq_.iserdesdq\ : label is "PRIMITIVE";
  attribute OPT_MODIFIED of \input_[6].iserdes_dq_.iserdesdq\ : label is "MLO";
  attribute BOX_TYPE of \input_[7].iserdes_dq_.idelay_dq.idelaye2\ : label is "PRIMITIVE";
  attribute IODELAY_GROUP of \input_[7].iserdes_dq_.idelay_dq.idelaye2\ : label is "MIG_IODELAY_MIG0";
  attribute SIM_DELAY_D of \input_[7].iserdes_dq_.idelay_dq.idelaye2\ : label is 0;
  attribute BOX_TYPE of \input_[7].iserdes_dq_.iserdesdq\ : label is "PRIMITIVE";
  attribute OPT_MODIFIED of \input_[7].iserdes_dq_.iserdesdq\ : label is "MLO";
  attribute BOX_TYPE of \input_[9].iserdes_dq_.idelay_dq.idelaye2\ : label is "PRIMITIVE";
  attribute IODELAY_GROUP of \input_[9].iserdes_dq_.idelay_dq.idelaye2\ : label is "MIG_IODELAY_MIG0";
  attribute SIM_DELAY_D of \input_[9].iserdes_dq_.idelay_dq.idelaye2\ : label is 0;
  attribute BOX_TYPE of \input_[9].iserdes_dq_.iserdesdq\ : label is "PRIMITIVE";
  attribute OPT_MODIFIED of \input_[9].iserdes_dq_.iserdesdq\ : label is "MLO";
  attribute BOX_TYPE of \output_[0].oserdes_dq_.ddr.oserdes_dq_i\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \output_[1].oserdes_dq_.ddr.oserdes_dq_i\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \output_[2].oserdes_dq_.ddr.oserdes_dq_i\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \output_[3].oserdes_dq_.ddr.oserdes_dq_i\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \output_[4].oserdes_dq_.ddr.oserdes_dq_i\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \output_[5].oserdes_dq_.ddr.oserdes_dq_i\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \output_[6].oserdes_dq_.ddr.oserdes_dq_i\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \output_[7].oserdes_dq_.ddr.oserdes_dq_i\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \output_[9].oserdes_dq_.ddr.oserdes_dq_i\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \slave_ts.oserdes_slave_ts\ : label is "PRIMITIVE";
begin
  idelay_ld_rst <= \^idelay_ld_rst\;
\dqs_gen.oddr_dqs\: unisim.vcomponents.ODDR
    generic map(
      DDR_CLK_EDGE => "SAME_EDGE",
      INIT => '0',
      IS_C_INVERTED => '0',
      IS_D1_INVERTED => '0',
      IS_D2_INVERTED => '0',
      SRTYPE => "SYNC"
    )
        port map (
      C => oserdes_clk_delayed,
      CE => '1',
      D1 => DQSBUS(0),
      D2 => DQSBUS(1),
      Q => out_dqs_4,
      R => '0',
      S => \NLW_dqs_gen.oddr_dqs_S_UNCONNECTED\
    );
\dqs_gen.oddr_dqsts\: unisim.vcomponents.ODDR
    generic map(
      DDR_CLK_EDGE => "SAME_EDGE",
      INIT => '0',
      IS_C_INVERTED => '0',
      IS_D1_INVERTED => '0',
      IS_D2_INVERTED => '0',
      SRTYPE => "SYNC"
    )
        port map (
      C => oserdes_clk_delayed,
      CE => '1',
      D1 => CTSBUS(0),
      D2 => CTSBUS(0),
      Q => ts_dqs_4,
      R => \NLW_dqs_gen.oddr_dqsts_R_UNCONNECTED\,
      S => '0'
    );
idelay_ld_rst_i_1: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \^idelay_ld_rst\,
      I1 => rst_r4,
      O => idelay_ld_rst_i_1_n_0
    );
idelay_ld_rst_reg: unisim.vcomponents.FDSE
     port map (
      C => idelay_ld_rst_reg_0,
      CE => '1',
      D => idelay_ld_rst_i_1_n_0,
      Q => \^idelay_ld_rst\,
      S => A_rst_primitives
    );
\input_[1].iserdes_dq_.idelay_dq.idelaye2\: unisim.vcomponents.IDELAYE2
    generic map(
      CINVCTRL_SEL => "FALSE",
      DELAY_SRC => "IDATAIN",
      HIGH_PERFORMANCE_MODE => "TRUE",
      IDELAY_TYPE => "VARIABLE",
      IDELAY_VALUE => 0,
      IS_C_INVERTED => '0',
      IS_DATAIN_INVERTED => '0',
      IS_IDATAIN_INVERTED => '0',
      PIPE_SEL => "FALSE",
      REFCLK_FREQUENCY => 200.000000,
      SIGNAL_PATTERN => "DATA"
    )
        port map (
      C => idelay_ld_rst_reg_0,
      CE => \input_[9].iserdes_dq_.iserdesdq_0\,
      CINVCTRL => '0',
      CNTVALUEIN(4 downto 0) => B"00000",
      CNTVALUEOUT(4 downto 0) => \NLW_input_[1].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED\(4 downto 0),
      DATAIN => '0',
      DATAOUT => data_in_dly_1,
      IDATAIN => mem_dq_in(0),
      INC => idelay_inc,
      LD => LD0,
      LDPIPEEN => '0',
      REGRST => A_rst_primitives
    );
\input_[1].iserdes_dq_.iserdesdq\: unisim.vcomponents.ISERDESE2
    generic map(
      DATA_RATE => "DDR",
      DATA_WIDTH => 4,
      DYN_CLKDIV_INV_EN => "FALSE",
      DYN_CLK_INV_EN => "FALSE",
      INIT_Q1 => '0',
      INIT_Q2 => '0',
      INIT_Q3 => '0',
      INIT_Q4 => '0',
      INTERFACE_TYPE => "MEMORY_DDR3",
      IOBDELAY => "IFD",
      IS_CLKB_INVERTED => '1',
      IS_CLKDIVP_INVERTED => '0',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D_INVERTED => '0',
      IS_OCLKB_INVERTED => '0',
      IS_OCLK_INVERTED => '0',
      NUM_CE => 2,
      OFB_USED => "FALSE",
      SERDES_MODE => "MASTER",
      SRVAL_Q1 => '0',
      SRVAL_Q2 => '0',
      SRVAL_Q3 => '0',
      SRVAL_Q4 => '0'
    )
        port map (
      BITSLIP => '0',
      CE1 => '1',
      CE2 => '1',
      CLK => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]\,
      CLKB => CLKB0,
      CLKDIV => \NLW_input_[1].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED\,
      CLKDIVP => iserdes_clkdiv,
      D => mem_dq_in(0),
      DDLY => data_in_dly_1,
      DYNCLKDIVSEL => '0',
      DYNCLKSEL => '0',
      O => \NLW_input_[1].iserdes_dq_.iserdesdq_O_UNCONNECTED\,
      OCLK => oserdes_clk,
      OCLKB => \NLW_input_[1].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED\,
      OFB => \NLW_input_[1].iserdes_dq_.iserdesdq_OFB_UNCONNECTED\,
      Q1 => D1(3),
      Q2 => D1(2),
      Q3 => D1(1),
      Q4 => D1(0),
      Q5 => \NLW_input_[1].iserdes_dq_.iserdesdq_Q5_UNCONNECTED\,
      Q6 => \NLW_input_[1].iserdes_dq_.iserdesdq_Q6_UNCONNECTED\,
      Q7 => \NLW_input_[1].iserdes_dq_.iserdesdq_Q7_UNCONNECTED\,
      Q8 => \NLW_input_[1].iserdes_dq_.iserdesdq_Q8_UNCONNECTED\,
      RST => '0',
      SHIFTIN1 => '0',
      SHIFTIN2 => '0',
      SHIFTOUT1 => \NLW_input_[1].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_input_[1].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED\
    );
\input_[2].iserdes_dq_.idelay_dq.idelaye2\: unisim.vcomponents.IDELAYE2
    generic map(
      CINVCTRL_SEL => "FALSE",
      DELAY_SRC => "IDATAIN",
      HIGH_PERFORMANCE_MODE => "TRUE",
      IDELAY_TYPE => "VARIABLE",
      IDELAY_VALUE => 0,
      IS_C_INVERTED => '0',
      IS_DATAIN_INVERTED => '0',
      IS_IDATAIN_INVERTED => '0',
      PIPE_SEL => "FALSE",
      REFCLK_FREQUENCY => 200.000000,
      SIGNAL_PATTERN => "DATA"
    )
        port map (
      C => idelay_ld_rst_reg_0,
      CE => \input_[9].iserdes_dq_.iserdesdq_0\,
      CINVCTRL => '0',
      CNTVALUEIN(4 downto 0) => B"00000",
      CNTVALUEOUT(4 downto 0) => \NLW_input_[2].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED\(4 downto 0),
      DATAIN => '0',
      DATAOUT => data_in_dly_2,
      IDATAIN => mem_dq_in(1),
      INC => idelay_inc,
      LD => LD0,
      LDPIPEEN => '0',
      REGRST => A_rst_primitives
    );
\input_[2].iserdes_dq_.iserdesdq\: unisim.vcomponents.ISERDESE2
    generic map(
      DATA_RATE => "DDR",
      DATA_WIDTH => 4,
      DYN_CLKDIV_INV_EN => "FALSE",
      DYN_CLK_INV_EN => "FALSE",
      INIT_Q1 => '0',
      INIT_Q2 => '0',
      INIT_Q3 => '0',
      INIT_Q4 => '0',
      INTERFACE_TYPE => "MEMORY_DDR3",
      IOBDELAY => "IFD",
      IS_CLKB_INVERTED => '1',
      IS_CLKDIVP_INVERTED => '0',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D_INVERTED => '0',
      IS_OCLKB_INVERTED => '0',
      IS_OCLK_INVERTED => '0',
      NUM_CE => 2,
      OFB_USED => "FALSE",
      SERDES_MODE => "MASTER",
      SRVAL_Q1 => '0',
      SRVAL_Q2 => '0',
      SRVAL_Q3 => '0',
      SRVAL_Q4 => '0'
    )
        port map (
      BITSLIP => '0',
      CE1 => '1',
      CE2 => '1',
      CLK => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]\,
      CLKB => CLKB0,
      CLKDIV => \NLW_input_[2].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED\,
      CLKDIVP => iserdes_clkdiv,
      D => mem_dq_in(1),
      DDLY => data_in_dly_2,
      DYNCLKDIVSEL => '0',
      DYNCLKSEL => '0',
      O => \NLW_input_[2].iserdes_dq_.iserdesdq_O_UNCONNECTED\,
      OCLK => oserdes_clk,
      OCLKB => \NLW_input_[2].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED\,
      OFB => \NLW_input_[2].iserdes_dq_.iserdesdq_OFB_UNCONNECTED\,
      Q1 => D2(3),
      Q2 => D2(2),
      Q3 => D2(1),
      Q4 => D2(0),
      Q5 => \NLW_input_[2].iserdes_dq_.iserdesdq_Q5_UNCONNECTED\,
      Q6 => \NLW_input_[2].iserdes_dq_.iserdesdq_Q6_UNCONNECTED\,
      Q7 => \NLW_input_[2].iserdes_dq_.iserdesdq_Q7_UNCONNECTED\,
      Q8 => \NLW_input_[2].iserdes_dq_.iserdesdq_Q8_UNCONNECTED\,
      RST => '0',
      SHIFTIN1 => '0',
      SHIFTIN2 => '0',
      SHIFTOUT1 => \NLW_input_[2].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_input_[2].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED\
    );
\input_[3].iserdes_dq_.idelay_dq.idelaye2\: unisim.vcomponents.IDELAYE2
    generic map(
      CINVCTRL_SEL => "FALSE",
      DELAY_SRC => "IDATAIN",
      HIGH_PERFORMANCE_MODE => "TRUE",
      IDELAY_TYPE => "VARIABLE",
      IDELAY_VALUE => 0,
      IS_C_INVERTED => '0',
      IS_DATAIN_INVERTED => '0',
      IS_IDATAIN_INVERTED => '0',
      PIPE_SEL => "FALSE",
      REFCLK_FREQUENCY => 200.000000,
      SIGNAL_PATTERN => "DATA"
    )
        port map (
      C => idelay_ld_rst_reg_0,
      CE => \input_[9].iserdes_dq_.iserdesdq_0\,
      CINVCTRL => '0',
      CNTVALUEIN(4 downto 0) => B"00000",
      CNTVALUEOUT(4 downto 0) => \NLW_input_[3].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED\(4 downto 0),
      DATAIN => '0',
      DATAOUT => data_in_dly_3,
      IDATAIN => mem_dq_in(2),
      INC => idelay_inc,
      LD => LD0,
      LDPIPEEN => '0',
      REGRST => A_rst_primitives
    );
\input_[3].iserdes_dq_.iserdesdq\: unisim.vcomponents.ISERDESE2
    generic map(
      DATA_RATE => "DDR",
      DATA_WIDTH => 4,
      DYN_CLKDIV_INV_EN => "FALSE",
      DYN_CLK_INV_EN => "FALSE",
      INIT_Q1 => '0',
      INIT_Q2 => '0',
      INIT_Q3 => '0',
      INIT_Q4 => '0',
      INTERFACE_TYPE => "MEMORY_DDR3",
      IOBDELAY => "IFD",
      IS_CLKB_INVERTED => '1',
      IS_CLKDIVP_INVERTED => '0',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D_INVERTED => '0',
      IS_OCLKB_INVERTED => '0',
      IS_OCLK_INVERTED => '0',
      NUM_CE => 2,
      OFB_USED => "FALSE",
      SERDES_MODE => "MASTER",
      SRVAL_Q1 => '0',
      SRVAL_Q2 => '0',
      SRVAL_Q3 => '0',
      SRVAL_Q4 => '0'
    )
        port map (
      BITSLIP => '0',
      CE1 => '1',
      CE2 => '1',
      CLK => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]\,
      CLKB => CLKB0,
      CLKDIV => \NLW_input_[3].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED\,
      CLKDIVP => iserdes_clkdiv,
      D => mem_dq_in(2),
      DDLY => data_in_dly_3,
      DYNCLKDIVSEL => '0',
      DYNCLKSEL => '0',
      O => \NLW_input_[3].iserdes_dq_.iserdesdq_O_UNCONNECTED\,
      OCLK => oserdes_clk,
      OCLKB => \NLW_input_[3].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED\,
      OFB => \NLW_input_[3].iserdes_dq_.iserdesdq_OFB_UNCONNECTED\,
      Q1 => D3(3),
      Q2 => D3(2),
      Q3 => D3(1),
      Q4 => D3(0),
      Q5 => \NLW_input_[3].iserdes_dq_.iserdesdq_Q5_UNCONNECTED\,
      Q6 => \NLW_input_[3].iserdes_dq_.iserdesdq_Q6_UNCONNECTED\,
      Q7 => \NLW_input_[3].iserdes_dq_.iserdesdq_Q7_UNCONNECTED\,
      Q8 => \NLW_input_[3].iserdes_dq_.iserdesdq_Q8_UNCONNECTED\,
      RST => '0',
      SHIFTIN1 => '0',
      SHIFTIN2 => '0',
      SHIFTOUT1 => \NLW_input_[3].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_input_[3].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED\
    );
\input_[4].iserdes_dq_.idelay_dq.idelaye2\: unisim.vcomponents.IDELAYE2
    generic map(
      CINVCTRL_SEL => "FALSE",
      DELAY_SRC => "IDATAIN",
      HIGH_PERFORMANCE_MODE => "TRUE",
      IDELAY_TYPE => "VARIABLE",
      IDELAY_VALUE => 0,
      IS_C_INVERTED => '0',
      IS_DATAIN_INVERTED => '0',
      IS_IDATAIN_INVERTED => '0',
      PIPE_SEL => "FALSE",
      REFCLK_FREQUENCY => 200.000000,
      SIGNAL_PATTERN => "DATA"
    )
        port map (
      C => idelay_ld_rst_reg_0,
      CE => \input_[9].iserdes_dq_.iserdesdq_0\,
      CINVCTRL => '0',
      CNTVALUEIN(4 downto 0) => B"00000",
      CNTVALUEOUT(4 downto 0) => \NLW_input_[4].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED\(4 downto 0),
      DATAIN => '0',
      DATAOUT => data_in_dly_4,
      IDATAIN => mem_dq_in(3),
      INC => idelay_inc,
      LD => LD0,
      LDPIPEEN => '0',
      REGRST => A_rst_primitives
    );
\input_[4].iserdes_dq_.iserdesdq\: unisim.vcomponents.ISERDESE2
    generic map(
      DATA_RATE => "DDR",
      DATA_WIDTH => 4,
      DYN_CLKDIV_INV_EN => "FALSE",
      DYN_CLK_INV_EN => "FALSE",
      INIT_Q1 => '0',
      INIT_Q2 => '0',
      INIT_Q3 => '0',
      INIT_Q4 => '0',
      INTERFACE_TYPE => "MEMORY_DDR3",
      IOBDELAY => "IFD",
      IS_CLKB_INVERTED => '1',
      IS_CLKDIVP_INVERTED => '0',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D_INVERTED => '0',
      IS_OCLKB_INVERTED => '0',
      IS_OCLK_INVERTED => '0',
      NUM_CE => 2,
      OFB_USED => "FALSE",
      SERDES_MODE => "MASTER",
      SRVAL_Q1 => '0',
      SRVAL_Q2 => '0',
      SRVAL_Q3 => '0',
      SRVAL_Q4 => '0'
    )
        port map (
      BITSLIP => '0',
      CE1 => '1',
      CE2 => '1',
      CLK => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]\,
      CLKB => CLKB0,
      CLKDIV => \NLW_input_[4].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED\,
      CLKDIVP => iserdes_clkdiv,
      D => mem_dq_in(3),
      DDLY => data_in_dly_4,
      DYNCLKDIVSEL => '0',
      DYNCLKSEL => '0',
      O => \NLW_input_[4].iserdes_dq_.iserdesdq_O_UNCONNECTED\,
      OCLK => oserdes_clk,
      OCLKB => \NLW_input_[4].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED\,
      OFB => \NLW_input_[4].iserdes_dq_.iserdesdq_OFB_UNCONNECTED\,
      Q1 => D4(3),
      Q2 => D4(2),
      Q3 => D4(1),
      Q4 => D4(0),
      Q5 => \NLW_input_[4].iserdes_dq_.iserdesdq_Q5_UNCONNECTED\,
      Q6 => \NLW_input_[4].iserdes_dq_.iserdesdq_Q6_UNCONNECTED\,
      Q7 => \NLW_input_[4].iserdes_dq_.iserdesdq_Q7_UNCONNECTED\,
      Q8 => \NLW_input_[4].iserdes_dq_.iserdesdq_Q8_UNCONNECTED\,
      RST => '0',
      SHIFTIN1 => '0',
      SHIFTIN2 => '0',
      SHIFTOUT1 => \NLW_input_[4].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_input_[4].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED\
    );
\input_[5].iserdes_dq_.idelay_dq.idelaye2\: unisim.vcomponents.IDELAYE2
    generic map(
      CINVCTRL_SEL => "FALSE",
      DELAY_SRC => "IDATAIN",
      HIGH_PERFORMANCE_MODE => "TRUE",
      IDELAY_TYPE => "VARIABLE",
      IDELAY_VALUE => 0,
      IS_C_INVERTED => '0',
      IS_DATAIN_INVERTED => '0',
      IS_IDATAIN_INVERTED => '0',
      PIPE_SEL => "FALSE",
      REFCLK_FREQUENCY => 200.000000,
      SIGNAL_PATTERN => "DATA"
    )
        port map (
      C => idelay_ld_rst_reg_0,
      CE => \input_[9].iserdes_dq_.iserdesdq_0\,
      CINVCTRL => '0',
      CNTVALUEIN(4 downto 0) => B"00000",
      CNTVALUEOUT(4 downto 0) => \NLW_input_[5].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED\(4 downto 0),
      DATAIN => '0',
      DATAOUT => data_in_dly_5,
      IDATAIN => mem_dq_in(4),
      INC => idelay_inc,
      LD => LD0,
      LDPIPEEN => '0',
      REGRST => A_rst_primitives
    );
\input_[5].iserdes_dq_.iserdesdq\: unisim.vcomponents.ISERDESE2
    generic map(
      DATA_RATE => "DDR",
      DATA_WIDTH => 4,
      DYN_CLKDIV_INV_EN => "FALSE",
      DYN_CLK_INV_EN => "FALSE",
      INIT_Q1 => '0',
      INIT_Q2 => '0',
      INIT_Q3 => '0',
      INIT_Q4 => '0',
      INTERFACE_TYPE => "MEMORY_DDR3",
      IOBDELAY => "IFD",
      IS_CLKB_INVERTED => '1',
      IS_CLKDIVP_INVERTED => '0',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D_INVERTED => '0',
      IS_OCLKB_INVERTED => '0',
      IS_OCLK_INVERTED => '0',
      NUM_CE => 2,
      OFB_USED => "FALSE",
      SERDES_MODE => "MASTER",
      SRVAL_Q1 => '0',
      SRVAL_Q2 => '0',
      SRVAL_Q3 => '0',
      SRVAL_Q4 => '0'
    )
        port map (
      BITSLIP => '0',
      CE1 => '1',
      CE2 => '1',
      CLK => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]\,
      CLKB => CLKB0,
      CLKDIV => \NLW_input_[5].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED\,
      CLKDIVP => iserdes_clkdiv,
      D => mem_dq_in(4),
      DDLY => data_in_dly_5,
      DYNCLKDIVSEL => '0',
      DYNCLKSEL => '0',
      O => \NLW_input_[5].iserdes_dq_.iserdesdq_O_UNCONNECTED\,
      OCLK => oserdes_clk,
      OCLKB => \NLW_input_[5].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED\,
      OFB => \NLW_input_[5].iserdes_dq_.iserdesdq_OFB_UNCONNECTED\,
      Q1 => D5(3),
      Q2 => D5(2),
      Q3 => D5(1),
      Q4 => D5(0),
      Q5 => \NLW_input_[5].iserdes_dq_.iserdesdq_Q5_UNCONNECTED\,
      Q6 => \NLW_input_[5].iserdes_dq_.iserdesdq_Q6_UNCONNECTED\,
      Q7 => \NLW_input_[5].iserdes_dq_.iserdesdq_Q7_UNCONNECTED\,
      Q8 => \NLW_input_[5].iserdes_dq_.iserdesdq_Q8_UNCONNECTED\,
      RST => '0',
      SHIFTIN1 => '0',
      SHIFTIN2 => '0',
      SHIFTOUT1 => \NLW_input_[5].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_input_[5].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED\
    );
\input_[6].iserdes_dq_.idelay_dq.idelaye2\: unisim.vcomponents.IDELAYE2
    generic map(
      CINVCTRL_SEL => "FALSE",
      DELAY_SRC => "IDATAIN",
      HIGH_PERFORMANCE_MODE => "TRUE",
      IDELAY_TYPE => "VARIABLE",
      IDELAY_VALUE => 0,
      IS_C_INVERTED => '0',
      IS_DATAIN_INVERTED => '0',
      IS_IDATAIN_INVERTED => '0',
      PIPE_SEL => "FALSE",
      REFCLK_FREQUENCY => 200.000000,
      SIGNAL_PATTERN => "DATA"
    )
        port map (
      C => idelay_ld_rst_reg_0,
      CE => \input_[9].iserdes_dq_.iserdesdq_0\,
      CINVCTRL => '0',
      CNTVALUEIN(4 downto 0) => B"00000",
      CNTVALUEOUT(4 downto 0) => \NLW_input_[6].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED\(4 downto 0),
      DATAIN => '0',
      DATAOUT => data_in_dly_6,
      IDATAIN => mem_dq_in(5),
      INC => idelay_inc,
      LD => LD0,
      LDPIPEEN => '0',
      REGRST => A_rst_primitives
    );
\input_[6].iserdes_dq_.iserdesdq\: unisim.vcomponents.ISERDESE2
    generic map(
      DATA_RATE => "DDR",
      DATA_WIDTH => 4,
      DYN_CLKDIV_INV_EN => "FALSE",
      DYN_CLK_INV_EN => "FALSE",
      INIT_Q1 => '0',
      INIT_Q2 => '0',
      INIT_Q3 => '0',
      INIT_Q4 => '0',
      INTERFACE_TYPE => "MEMORY_DDR3",
      IOBDELAY => "IFD",
      IS_CLKB_INVERTED => '1',
      IS_CLKDIVP_INVERTED => '0',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D_INVERTED => '0',
      IS_OCLKB_INVERTED => '0',
      IS_OCLK_INVERTED => '0',
      NUM_CE => 2,
      OFB_USED => "FALSE",
      SERDES_MODE => "MASTER",
      SRVAL_Q1 => '0',
      SRVAL_Q2 => '0',
      SRVAL_Q3 => '0',
      SRVAL_Q4 => '0'
    )
        port map (
      BITSLIP => '0',
      CE1 => '1',
      CE2 => '1',
      CLK => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]\,
      CLKB => CLKB0,
      CLKDIV => \NLW_input_[6].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED\,
      CLKDIVP => iserdes_clkdiv,
      D => mem_dq_in(5),
      DDLY => data_in_dly_6,
      DYNCLKDIVSEL => '0',
      DYNCLKSEL => '0',
      O => \NLW_input_[6].iserdes_dq_.iserdesdq_O_UNCONNECTED\,
      OCLK => oserdes_clk,
      OCLKB => \NLW_input_[6].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED\,
      OFB => \NLW_input_[6].iserdes_dq_.iserdesdq_OFB_UNCONNECTED\,
      Q1 => D6(3),
      Q2 => D6(2),
      Q3 => D6(1),
      Q4 => D6(0),
      Q5 => \NLW_input_[6].iserdes_dq_.iserdesdq_Q5_UNCONNECTED\,
      Q6 => \NLW_input_[6].iserdes_dq_.iserdesdq_Q6_UNCONNECTED\,
      Q7 => \NLW_input_[6].iserdes_dq_.iserdesdq_Q7_UNCONNECTED\,
      Q8 => \NLW_input_[6].iserdes_dq_.iserdesdq_Q8_UNCONNECTED\,
      RST => '0',
      SHIFTIN1 => '0',
      SHIFTIN2 => '0',
      SHIFTOUT1 => \NLW_input_[6].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_input_[6].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED\
    );
\input_[7].iserdes_dq_.idelay_dq.idelaye2\: unisim.vcomponents.IDELAYE2
    generic map(
      CINVCTRL_SEL => "FALSE",
      DELAY_SRC => "IDATAIN",
      HIGH_PERFORMANCE_MODE => "TRUE",
      IDELAY_TYPE => "VARIABLE",
      IDELAY_VALUE => 0,
      IS_C_INVERTED => '0',
      IS_DATAIN_INVERTED => '0',
      IS_IDATAIN_INVERTED => '0',
      PIPE_SEL => "FALSE",
      REFCLK_FREQUENCY => 200.000000,
      SIGNAL_PATTERN => "DATA"
    )
        port map (
      C => idelay_ld_rst_reg_0,
      CE => \input_[9].iserdes_dq_.iserdesdq_0\,
      CINVCTRL => '0',
      CNTVALUEIN(4 downto 0) => B"00000",
      CNTVALUEOUT(4 downto 0) => \NLW_input_[7].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED\(4 downto 0),
      DATAIN => '0',
      DATAOUT => data_in_dly_7,
      IDATAIN => mem_dq_in(6),
      INC => idelay_inc,
      LD => LD0,
      LDPIPEEN => '0',
      REGRST => A_rst_primitives
    );
\input_[7].iserdes_dq_.iserdesdq\: unisim.vcomponents.ISERDESE2
    generic map(
      DATA_RATE => "DDR",
      DATA_WIDTH => 4,
      DYN_CLKDIV_INV_EN => "FALSE",
      DYN_CLK_INV_EN => "FALSE",
      INIT_Q1 => '0',
      INIT_Q2 => '0',
      INIT_Q3 => '0',
      INIT_Q4 => '0',
      INTERFACE_TYPE => "MEMORY_DDR3",
      IOBDELAY => "IFD",
      IS_CLKB_INVERTED => '1',
      IS_CLKDIVP_INVERTED => '0',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D_INVERTED => '0',
      IS_OCLKB_INVERTED => '0',
      IS_OCLK_INVERTED => '0',
      NUM_CE => 2,
      OFB_USED => "FALSE",
      SERDES_MODE => "MASTER",
      SRVAL_Q1 => '0',
      SRVAL_Q2 => '0',
      SRVAL_Q3 => '0',
      SRVAL_Q4 => '0'
    )
        port map (
      BITSLIP => '0',
      CE1 => '1',
      CE2 => '1',
      CLK => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]\,
      CLKB => CLKB0,
      CLKDIV => \NLW_input_[7].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED\,
      CLKDIVP => iserdes_clkdiv,
      D => mem_dq_in(6),
      DDLY => data_in_dly_7,
      DYNCLKDIVSEL => '0',
      DYNCLKSEL => '0',
      O => \NLW_input_[7].iserdes_dq_.iserdesdq_O_UNCONNECTED\,
      OCLK => oserdes_clk,
      OCLKB => \NLW_input_[7].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED\,
      OFB => \NLW_input_[7].iserdes_dq_.iserdesdq_OFB_UNCONNECTED\,
      Q1 => D7(3),
      Q2 => D7(2),
      Q3 => D7(1),
      Q4 => D7(0),
      Q5 => \NLW_input_[7].iserdes_dq_.iserdesdq_Q5_UNCONNECTED\,
      Q6 => \NLW_input_[7].iserdes_dq_.iserdesdq_Q6_UNCONNECTED\,
      Q7 => \NLW_input_[7].iserdes_dq_.iserdesdq_Q7_UNCONNECTED\,
      Q8 => \NLW_input_[7].iserdes_dq_.iserdesdq_Q8_UNCONNECTED\,
      RST => '0',
      SHIFTIN1 => '0',
      SHIFTIN2 => '0',
      SHIFTOUT1 => \NLW_input_[7].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_input_[7].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED\
    );
\input_[9].iserdes_dq_.idelay_dq.idelaye2\: unisim.vcomponents.IDELAYE2
    generic map(
      CINVCTRL_SEL => "FALSE",
      DELAY_SRC => "IDATAIN",
      HIGH_PERFORMANCE_MODE => "TRUE",
      IDELAY_TYPE => "VARIABLE",
      IDELAY_VALUE => 0,
      IS_C_INVERTED => '0',
      IS_DATAIN_INVERTED => '0',
      IS_IDATAIN_INVERTED => '0',
      PIPE_SEL => "FALSE",
      REFCLK_FREQUENCY => 200.000000,
      SIGNAL_PATTERN => "DATA"
    )
        port map (
      C => idelay_ld_rst_reg_0,
      CE => \input_[9].iserdes_dq_.iserdesdq_0\,
      CINVCTRL => '0',
      CNTVALUEIN(4 downto 0) => B"00000",
      CNTVALUEOUT(4 downto 0) => \NLW_input_[9].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED\(4 downto 0),
      DATAIN => '0',
      DATAOUT => data_in_dly_9,
      IDATAIN => mem_dq_in(7),
      INC => idelay_inc,
      LD => LD0,
      LDPIPEEN => '0',
      REGRST => A_rst_primitives
    );
\input_[9].iserdes_dq_.iserdesdq\: unisim.vcomponents.ISERDESE2
    generic map(
      DATA_RATE => "DDR",
      DATA_WIDTH => 4,
      DYN_CLKDIV_INV_EN => "FALSE",
      DYN_CLK_INV_EN => "FALSE",
      INIT_Q1 => '0',
      INIT_Q2 => '0',
      INIT_Q3 => '0',
      INIT_Q4 => '0',
      INTERFACE_TYPE => "MEMORY_DDR3",
      IOBDELAY => "IFD",
      IS_CLKB_INVERTED => '1',
      IS_CLKDIVP_INVERTED => '0',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D_INVERTED => '0',
      IS_OCLKB_INVERTED => '0',
      IS_OCLK_INVERTED => '0',
      NUM_CE => 2,
      OFB_USED => "FALSE",
      SERDES_MODE => "MASTER",
      SRVAL_Q1 => '0',
      SRVAL_Q2 => '0',
      SRVAL_Q3 => '0',
      SRVAL_Q4 => '0'
    )
        port map (
      BITSLIP => '0',
      CE1 => '1',
      CE2 => '1',
      CLK => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]\,
      CLKB => CLKB0,
      CLKDIV => \NLW_input_[9].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED\,
      CLKDIVP => iserdes_clkdiv,
      D => mem_dq_in(7),
      DDLY => data_in_dly_9,
      DYNCLKDIVSEL => '0',
      DYNCLKSEL => '0',
      O => \NLW_input_[9].iserdes_dq_.iserdesdq_O_UNCONNECTED\,
      OCLK => oserdes_clk,
      OCLKB => \NLW_input_[9].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED\,
      OFB => \NLW_input_[9].iserdes_dq_.iserdesdq_OFB_UNCONNECTED\,
      Q1 => D9(3),
      Q2 => D9(2),
      Q3 => D9(1),
      Q4 => D9(0),
      Q5 => \NLW_input_[9].iserdes_dq_.iserdesdq_Q5_UNCONNECTED\,
      Q6 => \NLW_input_[9].iserdes_dq_.iserdesdq_Q6_UNCONNECTED\,
      Q7 => \NLW_input_[9].iserdes_dq_.iserdesdq_Q7_UNCONNECTED\,
      Q8 => \NLW_input_[9].iserdes_dq_.iserdesdq_Q8_UNCONNECTED\,
      RST => '0',
      SHIFTIN1 => '0',
      SHIFTIN2 => '0',
      SHIFTOUT1 => \NLW_input_[9].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_input_[9].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED\
    );
\output_[0].oserdes_dq_.ddr.oserdes_dq_i\: unisim.vcomponents.OSERDESE2
    generic map(
      DATA_RATE_OQ => "DDR",
      DATA_RATE_TQ => "DDR",
      DATA_WIDTH => 4,
      INIT_OQ => '1',
      INIT_TQ => '1',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D1_INVERTED => '0',
      IS_D2_INVERTED => '0',
      IS_D3_INVERTED => '0',
      IS_D4_INVERTED => '0',
      IS_D5_INVERTED => '0',
      IS_D6_INVERTED => '0',
      IS_D7_INVERTED => '0',
      IS_D8_INVERTED => '0',
      IS_T1_INVERTED => '0',
      IS_T2_INVERTED => '0',
      IS_T3_INVERTED => '0',
      IS_T4_INVERTED => '0',
      SERDES_MODE => "MASTER",
      SRVAL_OQ => '1',
      SRVAL_TQ => '1',
      TBYTE_CTL => "TRUE",
      TBYTE_SRC => "FALSE",
      TRISTATE_WIDTH => 4
    )
        port map (
      CLK => oserdes_clk,
      CLKDIV => oserdes_clkdiv,
      D1 => of_dqbus(0),
      D2 => of_dqbus(1),
      D3 => of_dqbus(2),
      D4 => of_dqbus(3),
      D5 => '0',
      D6 => '0',
      D7 => '0',
      D8 => '0',
      OCE => '1',
      OFB => \NLW_output_[0].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\,
      OQ => mem_dq_out(0),
      RST => po_oserdes_rst,
      SHIFTIN1 => \NLW_output_[0].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\,
      SHIFTIN2 => \NLW_output_[0].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\,
      SHIFTOUT1 => \NLW_output_[0].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_output_[0].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\,
      T1 => '0',
      T2 => '0',
      T3 => '0',
      T4 => '0',
      TBYTEIN => tbyte_out,
      TBYTEOUT => \NLW_output_[0].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\,
      TCE => '1',
      TFB => \NLW_output_[0].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\,
      TQ => mem_dq_ts(0)
    );
\output_[1].oserdes_dq_.ddr.oserdes_dq_i\: unisim.vcomponents.OSERDESE2
    generic map(
      DATA_RATE_OQ => "DDR",
      DATA_RATE_TQ => "DDR",
      DATA_WIDTH => 4,
      INIT_OQ => '1',
      INIT_TQ => '1',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D1_INVERTED => '0',
      IS_D2_INVERTED => '0',
      IS_D3_INVERTED => '0',
      IS_D4_INVERTED => '0',
      IS_D5_INVERTED => '0',
      IS_D6_INVERTED => '0',
      IS_D7_INVERTED => '0',
      IS_D8_INVERTED => '0',
      IS_T1_INVERTED => '0',
      IS_T2_INVERTED => '0',
      IS_T3_INVERTED => '0',
      IS_T4_INVERTED => '0',
      SERDES_MODE => "MASTER",
      SRVAL_OQ => '1',
      SRVAL_TQ => '1',
      TBYTE_CTL => "TRUE",
      TBYTE_SRC => "FALSE",
      TRISTATE_WIDTH => 4
    )
        port map (
      CLK => oserdes_clk,
      CLKDIV => oserdes_clkdiv,
      D1 => of_dqbus(4),
      D2 => of_dqbus(5),
      D3 => of_dqbus(6),
      D4 => of_dqbus(7),
      D5 => '0',
      D6 => '0',
      D7 => '0',
      D8 => '0',
      OCE => '1',
      OFB => \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\,
      OQ => mem_dq_out(1),
      RST => po_oserdes_rst,
      SHIFTIN1 => \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\,
      SHIFTIN2 => \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\,
      SHIFTOUT1 => \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\,
      T1 => '0',
      T2 => '0',
      T3 => '0',
      T4 => '0',
      TBYTEIN => tbyte_out,
      TBYTEOUT => \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\,
      TCE => '1',
      TFB => \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\,
      TQ => mem_dq_ts(1)
    );
\output_[2].oserdes_dq_.ddr.oserdes_dq_i\: unisim.vcomponents.OSERDESE2
    generic map(
      DATA_RATE_OQ => "DDR",
      DATA_RATE_TQ => "DDR",
      DATA_WIDTH => 4,
      INIT_OQ => '1',
      INIT_TQ => '1',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D1_INVERTED => '0',
      IS_D2_INVERTED => '0',
      IS_D3_INVERTED => '0',
      IS_D4_INVERTED => '0',
      IS_D5_INVERTED => '0',
      IS_D6_INVERTED => '0',
      IS_D7_INVERTED => '0',
      IS_D8_INVERTED => '0',
      IS_T1_INVERTED => '0',
      IS_T2_INVERTED => '0',
      IS_T3_INVERTED => '0',
      IS_T4_INVERTED => '0',
      SERDES_MODE => "MASTER",
      SRVAL_OQ => '1',
      SRVAL_TQ => '1',
      TBYTE_CTL => "TRUE",
      TBYTE_SRC => "FALSE",
      TRISTATE_WIDTH => 4
    )
        port map (
      CLK => oserdes_clk,
      CLKDIV => oserdes_clkdiv,
      D1 => of_dqbus(8),
      D2 => of_dqbus(9),
      D3 => of_dqbus(10),
      D4 => of_dqbus(11),
      D5 => '0',
      D6 => '0',
      D7 => '0',
      D8 => '0',
      OCE => '1',
      OFB => \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\,
      OQ => mem_dq_out(2),
      RST => po_oserdes_rst,
      SHIFTIN1 => \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\,
      SHIFTIN2 => \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\,
      SHIFTOUT1 => \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\,
      T1 => '0',
      T2 => '0',
      T3 => '0',
      T4 => '0',
      TBYTEIN => tbyte_out,
      TBYTEOUT => \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\,
      TCE => '1',
      TFB => \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\,
      TQ => mem_dq_ts(2)
    );
\output_[3].oserdes_dq_.ddr.oserdes_dq_i\: unisim.vcomponents.OSERDESE2
    generic map(
      DATA_RATE_OQ => "DDR",
      DATA_RATE_TQ => "DDR",
      DATA_WIDTH => 4,
      INIT_OQ => '1',
      INIT_TQ => '1',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D1_INVERTED => '0',
      IS_D2_INVERTED => '0',
      IS_D3_INVERTED => '0',
      IS_D4_INVERTED => '0',
      IS_D5_INVERTED => '0',
      IS_D6_INVERTED => '0',
      IS_D7_INVERTED => '0',
      IS_D8_INVERTED => '0',
      IS_T1_INVERTED => '0',
      IS_T2_INVERTED => '0',
      IS_T3_INVERTED => '0',
      IS_T4_INVERTED => '0',
      SERDES_MODE => "MASTER",
      SRVAL_OQ => '1',
      SRVAL_TQ => '1',
      TBYTE_CTL => "TRUE",
      TBYTE_SRC => "FALSE",
      TRISTATE_WIDTH => 4
    )
        port map (
      CLK => oserdes_clk,
      CLKDIV => oserdes_clkdiv,
      D1 => of_dqbus(12),
      D2 => of_dqbus(13),
      D3 => of_dqbus(14),
      D4 => of_dqbus(15),
      D5 => '0',
      D6 => '0',
      D7 => '0',
      D8 => '0',
      OCE => '1',
      OFB => \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\,
      OQ => mem_dq_out(3),
      RST => po_oserdes_rst,
      SHIFTIN1 => \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\,
      SHIFTIN2 => \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\,
      SHIFTOUT1 => \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\,
      T1 => '0',
      T2 => '0',
      T3 => '0',
      T4 => '0',
      TBYTEIN => tbyte_out,
      TBYTEOUT => \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\,
      TCE => '1',
      TFB => \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\,
      TQ => mem_dq_ts(3)
    );
\output_[4].oserdes_dq_.ddr.oserdes_dq_i\: unisim.vcomponents.OSERDESE2
    generic map(
      DATA_RATE_OQ => "DDR",
      DATA_RATE_TQ => "DDR",
      DATA_WIDTH => 4,
      INIT_OQ => '1',
      INIT_TQ => '1',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D1_INVERTED => '0',
      IS_D2_INVERTED => '0',
      IS_D3_INVERTED => '0',
      IS_D4_INVERTED => '0',
      IS_D5_INVERTED => '0',
      IS_D6_INVERTED => '0',
      IS_D7_INVERTED => '0',
      IS_D8_INVERTED => '0',
      IS_T1_INVERTED => '0',
      IS_T2_INVERTED => '0',
      IS_T3_INVERTED => '0',
      IS_T4_INVERTED => '0',
      SERDES_MODE => "MASTER",
      SRVAL_OQ => '1',
      SRVAL_TQ => '1',
      TBYTE_CTL => "TRUE",
      TBYTE_SRC => "FALSE",
      TRISTATE_WIDTH => 4
    )
        port map (
      CLK => oserdes_clk,
      CLKDIV => oserdes_clkdiv,
      D1 => of_dqbus(16),
      D2 => of_dqbus(17),
      D3 => of_dqbus(18),
      D4 => of_dqbus(19),
      D5 => '0',
      D6 => '0',
      D7 => '0',
      D8 => '0',
      OCE => '1',
      OFB => \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\,
      OQ => mem_dq_out(4),
      RST => po_oserdes_rst,
      SHIFTIN1 => \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\,
      SHIFTIN2 => \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\,
      SHIFTOUT1 => \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\,
      T1 => '0',
      T2 => '0',
      T3 => '0',
      T4 => '0',
      TBYTEIN => tbyte_out,
      TBYTEOUT => \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\,
      TCE => '1',
      TFB => \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\,
      TQ => mem_dq_ts(4)
    );
\output_[5].oserdes_dq_.ddr.oserdes_dq_i\: unisim.vcomponents.OSERDESE2
    generic map(
      DATA_RATE_OQ => "DDR",
      DATA_RATE_TQ => "DDR",
      DATA_WIDTH => 4,
      INIT_OQ => '1',
      INIT_TQ => '1',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D1_INVERTED => '0',
      IS_D2_INVERTED => '0',
      IS_D3_INVERTED => '0',
      IS_D4_INVERTED => '0',
      IS_D5_INVERTED => '0',
      IS_D6_INVERTED => '0',
      IS_D7_INVERTED => '0',
      IS_D8_INVERTED => '0',
      IS_T1_INVERTED => '0',
      IS_T2_INVERTED => '0',
      IS_T3_INVERTED => '0',
      IS_T4_INVERTED => '0',
      SERDES_MODE => "MASTER",
      SRVAL_OQ => '1',
      SRVAL_TQ => '1',
      TBYTE_CTL => "TRUE",
      TBYTE_SRC => "FALSE",
      TRISTATE_WIDTH => 4
    )
        port map (
      CLK => oserdes_clk,
      CLKDIV => oserdes_clkdiv,
      D1 => of_dqbus(20),
      D2 => of_dqbus(21),
      D3 => of_dqbus(22),
      D4 => of_dqbus(23),
      D5 => '0',
      D6 => '0',
      D7 => '0',
      D8 => '0',
      OCE => '1',
      OFB => \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\,
      OQ => mem_dq_out(5),
      RST => po_oserdes_rst,
      SHIFTIN1 => \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\,
      SHIFTIN2 => \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\,
      SHIFTOUT1 => \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\,
      T1 => '0',
      T2 => '0',
      T3 => '0',
      T4 => '0',
      TBYTEIN => tbyte_out,
      TBYTEOUT => \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\,
      TCE => '1',
      TFB => \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\,
      TQ => mem_dq_ts(5)
    );
\output_[6].oserdes_dq_.ddr.oserdes_dq_i\: unisim.vcomponents.OSERDESE2
    generic map(
      DATA_RATE_OQ => "DDR",
      DATA_RATE_TQ => "DDR",
      DATA_WIDTH => 4,
      INIT_OQ => '1',
      INIT_TQ => '1',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D1_INVERTED => '0',
      IS_D2_INVERTED => '0',
      IS_D3_INVERTED => '0',
      IS_D4_INVERTED => '0',
      IS_D5_INVERTED => '0',
      IS_D6_INVERTED => '0',
      IS_D7_INVERTED => '0',
      IS_D8_INVERTED => '0',
      IS_T1_INVERTED => '0',
      IS_T2_INVERTED => '0',
      IS_T3_INVERTED => '0',
      IS_T4_INVERTED => '0',
      SERDES_MODE => "MASTER",
      SRVAL_OQ => '1',
      SRVAL_TQ => '1',
      TBYTE_CTL => "TRUE",
      TBYTE_SRC => "FALSE",
      TRISTATE_WIDTH => 4
    )
        port map (
      CLK => oserdes_clk,
      CLKDIV => oserdes_clkdiv,
      D1 => of_dqbus(24),
      D2 => of_dqbus(25),
      D3 => of_dqbus(26),
      D4 => of_dqbus(27),
      D5 => '0',
      D6 => '0',
      D7 => '0',
      D8 => '0',
      OCE => '1',
      OFB => \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\,
      OQ => mem_dq_out(6),
      RST => po_oserdes_rst,
      SHIFTIN1 => \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\,
      SHIFTIN2 => \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\,
      SHIFTOUT1 => \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\,
      T1 => '0',
      T2 => '0',
      T3 => '0',
      T4 => '0',
      TBYTEIN => tbyte_out,
      TBYTEOUT => \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\,
      TCE => '1',
      TFB => \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\,
      TQ => mem_dq_ts(6)
    );
\output_[7].oserdes_dq_.ddr.oserdes_dq_i\: unisim.vcomponents.OSERDESE2
    generic map(
      DATA_RATE_OQ => "DDR",
      DATA_RATE_TQ => "DDR",
      DATA_WIDTH => 4,
      INIT_OQ => '1',
      INIT_TQ => '1',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D1_INVERTED => '0',
      IS_D2_INVERTED => '0',
      IS_D3_INVERTED => '0',
      IS_D4_INVERTED => '0',
      IS_D5_INVERTED => '0',
      IS_D6_INVERTED => '0',
      IS_D7_INVERTED => '0',
      IS_D8_INVERTED => '0',
      IS_T1_INVERTED => '0',
      IS_T2_INVERTED => '0',
      IS_T3_INVERTED => '0',
      IS_T4_INVERTED => '0',
      SERDES_MODE => "MASTER",
      SRVAL_OQ => '1',
      SRVAL_TQ => '1',
      TBYTE_CTL => "TRUE",
      TBYTE_SRC => "FALSE",
      TRISTATE_WIDTH => 4
    )
        port map (
      CLK => oserdes_clk,
      CLKDIV => oserdes_clkdiv,
      D1 => of_dqbus(28),
      D2 => of_dqbus(29),
      D3 => of_dqbus(30),
      D4 => of_dqbus(31),
      D5 => '0',
      D6 => '0',
      D7 => '0',
      D8 => '0',
      OCE => '1',
      OFB => \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\,
      OQ => mem_dq_out(7),
      RST => po_oserdes_rst,
      SHIFTIN1 => \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\,
      SHIFTIN2 => \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\,
      SHIFTOUT1 => \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\,
      T1 => '0',
      T2 => '0',
      T3 => '0',
      T4 => '0',
      TBYTEIN => tbyte_out,
      TBYTEOUT => \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\,
      TCE => '1',
      TFB => \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\,
      TQ => mem_dq_ts(7)
    );
\output_[9].oserdes_dq_.ddr.oserdes_dq_i\: unisim.vcomponents.OSERDESE2
    generic map(
      DATA_RATE_OQ => "DDR",
      DATA_RATE_TQ => "DDR",
      DATA_WIDTH => 4,
      INIT_OQ => '1',
      INIT_TQ => '1',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D1_INVERTED => '0',
      IS_D2_INVERTED => '0',
      IS_D3_INVERTED => '0',
      IS_D4_INVERTED => '0',
      IS_D5_INVERTED => '0',
      IS_D6_INVERTED => '0',
      IS_D7_INVERTED => '0',
      IS_D8_INVERTED => '0',
      IS_T1_INVERTED => '0',
      IS_T2_INVERTED => '0',
      IS_T3_INVERTED => '0',
      IS_T4_INVERTED => '0',
      SERDES_MODE => "MASTER",
      SRVAL_OQ => '1',
      SRVAL_TQ => '1',
      TBYTE_CTL => "TRUE",
      TBYTE_SRC => "FALSE",
      TRISTATE_WIDTH => 4
    )
        port map (
      CLK => oserdes_clk,
      CLKDIV => oserdes_clkdiv,
      D1 => of_dqbus(32),
      D2 => of_dqbus(33),
      D3 => of_dqbus(34),
      D4 => of_dqbus(35),
      D5 => '0',
      D6 => '0',
      D7 => '0',
      D8 => '0',
      OCE => '1',
      OFB => \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\,
      OQ => mem_dq_out(8),
      RST => po_oserdes_rst,
      SHIFTIN1 => \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\,
      SHIFTIN2 => \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\,
      SHIFTOUT1 => \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\,
      T1 => '0',
      T2 => '0',
      T3 => '0',
      T4 => '0',
      TBYTEIN => tbyte_out,
      TBYTEOUT => \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\,
      TCE => '1',
      TFB => \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\,
      TQ => mem_dq_ts(8)
    );
\slave_ts.oserdes_slave_ts\: unisim.vcomponents.OSERDESE2
    generic map(
      DATA_RATE_OQ => "DDR",
      DATA_RATE_TQ => "DDR",
      DATA_WIDTH => 4,
      INIT_OQ => '1',
      INIT_TQ => '1',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D1_INVERTED => '0',
      IS_D2_INVERTED => '0',
      IS_D3_INVERTED => '0',
      IS_D4_INVERTED => '0',
      IS_D5_INVERTED => '0',
      IS_D6_INVERTED => '0',
      IS_D7_INVERTED => '0',
      IS_D8_INVERTED => '0',
      IS_T1_INVERTED => '0',
      IS_T2_INVERTED => '0',
      IS_T3_INVERTED => '0',
      IS_T4_INVERTED => '0',
      SERDES_MODE => "MASTER",
      SRVAL_OQ => '1',
      SRVAL_TQ => '1',
      TBYTE_CTL => "TRUE",
      TBYTE_SRC => "TRUE",
      TRISTATE_WIDTH => 4
    )
        port map (
      CLK => oserdes_clk,
      CLKDIV => oserdes_clkdiv,
      D1 => '0',
      D2 => '0',
      D3 => '0',
      D4 => '0',
      D5 => '0',
      D6 => '0',
      D7 => '0',
      D8 => '0',
      OCE => '1',
      OFB => \NLW_slave_ts.oserdes_slave_ts_OFB_UNCONNECTED\,
      OQ => \NLW_slave_ts.oserdes_slave_ts_OQ_UNCONNECTED\,
      RST => po_oserdes_rst,
      SHIFTIN1 => \NLW_slave_ts.oserdes_slave_ts_SHIFTIN1_UNCONNECTED\,
      SHIFTIN2 => \NLW_slave_ts.oserdes_slave_ts_SHIFTIN2_UNCONNECTED\,
      SHIFTOUT1 => \NLW_slave_ts.oserdes_slave_ts_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_slave_ts.oserdes_slave_ts_SHIFTOUT2_UNCONNECTED\,
      T1 => DTSBUS(0),
      T2 => DTSBUS(0),
      T3 => DTSBUS(1),
      T4 => DTSBUS(1),
      TBYTEIN => tbyte_out,
      TBYTEOUT => tbyte_out,
      TCE => '1',
      TFB => \NLW_slave_ts.oserdes_slave_ts_TFB_UNCONNECTED\,
      TQ => \NLW_slave_ts.oserdes_slave_ts_TQ_UNCONNECTED\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \mig_mig_7series_v4_2_ddr_byte_group_io__parameterized0\ is
  port (
    out_dqs_3 : out STD_LOGIC;
    ts_dqs_3 : out STD_LOGIC;
    D2 : out STD_LOGIC_VECTOR ( 3 downto 0 );
    D3 : out STD_LOGIC_VECTOR ( 3 downto 0 );
    D4 : out STD_LOGIC_VECTOR ( 3 downto 0 );
    D5 : out STD_LOGIC_VECTOR ( 3 downto 0 );
    D6 : out STD_LOGIC_VECTOR ( 3 downto 0 );
    D7 : out STD_LOGIC_VECTOR ( 3 downto 0 );
    D8 : out STD_LOGIC_VECTOR ( 3 downto 0 );
    D9 : out STD_LOGIC_VECTOR ( 3 downto 0 );
    mem_dq_out : out STD_LOGIC_VECTOR ( 8 downto 0 );
    mem_dq_ts : out STD_LOGIC_VECTOR ( 8 downto 0 );
    idelay_ld_rst_6 : out STD_LOGIC;
    rst_r4 : out STD_LOGIC;
    oserdes_clk : in STD_LOGIC;
    oserdes_clkdiv : in STD_LOGIC;
    po_oserdes_rst : in STD_LOGIC;
    DTSBUS : in STD_LOGIC_VECTOR ( 1 downto 0 );
    oserdes_clk_delayed : in STD_LOGIC;
    DQSBUS : in STD_LOGIC_VECTOR ( 1 downto 0 );
    CTSBUS : in STD_LOGIC_VECTOR ( 0 to 0 );
    idelay_ld_rst_reg_0 : in STD_LOGIC;
    \input_[9].iserdes_dq_.iserdesdq_0\ : in STD_LOGIC;
    mem_dq_in : in STD_LOGIC_VECTOR ( 7 downto 0 );
    idelay_inc : in STD_LOGIC;
    LD0_13 : in STD_LOGIC;
    A_rst_primitives : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]\ : in STD_LOGIC;
    CLKB0_13 : in STD_LOGIC;
    iserdes_clkdiv : in STD_LOGIC;
    of_dqbus : in STD_LOGIC_VECTOR ( 35 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \mig_mig_7series_v4_2_ddr_byte_group_io__parameterized0\ : entity is "mig_7series_v4_2_ddr_byte_group_io";
end \mig_mig_7series_v4_2_ddr_byte_group_io__parameterized0\;

architecture STRUCTURE of \mig_mig_7series_v4_2_ddr_byte_group_io__parameterized0\ is
  signal data_in_dly_2 : STD_LOGIC;
  signal data_in_dly_3 : STD_LOGIC;
  signal data_in_dly_4 : STD_LOGIC;
  signal data_in_dly_5 : STD_LOGIC;
  signal data_in_dly_6 : STD_LOGIC;
  signal data_in_dly_7 : STD_LOGIC;
  signal data_in_dly_8 : STD_LOGIC;
  signal data_in_dly_9 : STD_LOGIC;
  signal \^idelay_ld_rst_6\ : STD_LOGIC;
  signal \idelay_ld_rst_i_1__6_n_0\ : STD_LOGIC;
  signal rst_r3_reg_srl3_n_0 : STD_LOGIC;
  signal \^rst_r4\ : STD_LOGIC;
  signal tbyte_out : STD_LOGIC;
  signal \NLW_dqs_gen.oddr_dqs_S_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_dqs_gen.oddr_dqsts_R_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[2].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal \NLW_input_[2].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[2].iserdes_dq_.iserdesdq_O_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[2].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[2].iserdes_dq_.iserdesdq_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[2].iserdes_dq_.iserdesdq_Q5_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[2].iserdes_dq_.iserdesdq_Q6_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[2].iserdes_dq_.iserdesdq_Q7_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[2].iserdes_dq_.iserdesdq_Q8_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[2].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[2].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[3].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal \NLW_input_[3].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[3].iserdes_dq_.iserdesdq_O_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[3].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[3].iserdes_dq_.iserdesdq_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[3].iserdes_dq_.iserdesdq_Q5_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[3].iserdes_dq_.iserdesdq_Q6_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[3].iserdes_dq_.iserdesdq_Q7_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[3].iserdes_dq_.iserdesdq_Q8_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[3].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[3].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[4].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal \NLW_input_[4].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[4].iserdes_dq_.iserdesdq_O_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[4].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[4].iserdes_dq_.iserdesdq_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[4].iserdes_dq_.iserdesdq_Q5_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[4].iserdes_dq_.iserdesdq_Q6_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[4].iserdes_dq_.iserdesdq_Q7_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[4].iserdes_dq_.iserdesdq_Q8_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[4].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[4].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[5].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal \NLW_input_[5].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[5].iserdes_dq_.iserdesdq_O_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[5].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[5].iserdes_dq_.iserdesdq_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[5].iserdes_dq_.iserdesdq_Q5_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[5].iserdes_dq_.iserdesdq_Q6_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[5].iserdes_dq_.iserdesdq_Q7_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[5].iserdes_dq_.iserdesdq_Q8_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[5].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[5].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[6].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal \NLW_input_[6].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[6].iserdes_dq_.iserdesdq_O_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[6].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[6].iserdes_dq_.iserdesdq_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[6].iserdes_dq_.iserdesdq_Q5_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[6].iserdes_dq_.iserdesdq_Q6_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[6].iserdes_dq_.iserdesdq_Q7_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[6].iserdes_dq_.iserdesdq_Q8_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[6].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[6].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[7].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal \NLW_input_[7].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[7].iserdes_dq_.iserdesdq_O_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[7].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[7].iserdes_dq_.iserdesdq_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[7].iserdes_dq_.iserdesdq_Q5_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[7].iserdes_dq_.iserdesdq_Q6_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[7].iserdes_dq_.iserdesdq_Q7_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[7].iserdes_dq_.iserdesdq_Q8_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[7].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[7].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[8].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal \NLW_input_[8].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[8].iserdes_dq_.iserdesdq_O_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[8].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[8].iserdes_dq_.iserdesdq_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[8].iserdes_dq_.iserdesdq_Q5_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[8].iserdes_dq_.iserdesdq_Q6_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[8].iserdes_dq_.iserdesdq_Q7_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[8].iserdes_dq_.iserdesdq_Q8_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[8].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[8].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[9].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal \NLW_input_[9].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[9].iserdes_dq_.iserdesdq_O_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[9].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[9].iserdes_dq_.iserdesdq_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[9].iserdes_dq_.iserdesdq_Q5_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[9].iserdes_dq_.iserdesdq_Q6_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[9].iserdes_dq_.iserdesdq_Q7_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[9].iserdes_dq_.iserdesdq_Q8_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[9].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[9].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_slave_ts.oserdes_slave_ts_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_slave_ts.oserdes_slave_ts_OQ_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_slave_ts.oserdes_slave_ts_SHIFTIN1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_slave_ts.oserdes_slave_ts_SHIFTIN2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_slave_ts.oserdes_slave_ts_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_slave_ts.oserdes_slave_ts_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_slave_ts.oserdes_slave_ts_TFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_slave_ts.oserdes_slave_ts_TQ_UNCONNECTED\ : STD_LOGIC;
  attribute BOX_TYPE : string;
  attribute BOX_TYPE of \dqs_gen.oddr_dqs\ : label is "PRIMITIVE";
  attribute \__SRVAL\ : string;
  attribute \__SRVAL\ of \dqs_gen.oddr_dqs\ : label is "FALSE";
  attribute BOX_TYPE of \dqs_gen.oddr_dqsts\ : label is "PRIMITIVE";
  attribute \__SRVAL\ of \dqs_gen.oddr_dqsts\ : label is "TRUE";
  attribute BOX_TYPE of \input_[2].iserdes_dq_.idelay_dq.idelaye2\ : label is "PRIMITIVE";
  attribute IODELAY_GROUP : string;
  attribute IODELAY_GROUP of \input_[2].iserdes_dq_.idelay_dq.idelaye2\ : label is "MIG_IODELAY_MIG0";
  attribute SIM_DELAY_D : integer;
  attribute SIM_DELAY_D of \input_[2].iserdes_dq_.idelay_dq.idelaye2\ : label is 0;
  attribute BOX_TYPE of \input_[2].iserdes_dq_.iserdesdq\ : label is "PRIMITIVE";
  attribute OPT_MODIFIED : string;
  attribute OPT_MODIFIED of \input_[2].iserdes_dq_.iserdesdq\ : label is "MLO";
  attribute BOX_TYPE of \input_[3].iserdes_dq_.idelay_dq.idelaye2\ : label is "PRIMITIVE";
  attribute IODELAY_GROUP of \input_[3].iserdes_dq_.idelay_dq.idelaye2\ : label is "MIG_IODELAY_MIG0";
  attribute SIM_DELAY_D of \input_[3].iserdes_dq_.idelay_dq.idelaye2\ : label is 0;
  attribute BOX_TYPE of \input_[3].iserdes_dq_.iserdesdq\ : label is "PRIMITIVE";
  attribute OPT_MODIFIED of \input_[3].iserdes_dq_.iserdesdq\ : label is "MLO";
  attribute BOX_TYPE of \input_[4].iserdes_dq_.idelay_dq.idelaye2\ : label is "PRIMITIVE";
  attribute IODELAY_GROUP of \input_[4].iserdes_dq_.idelay_dq.idelaye2\ : label is "MIG_IODELAY_MIG0";
  attribute SIM_DELAY_D of \input_[4].iserdes_dq_.idelay_dq.idelaye2\ : label is 0;
  attribute BOX_TYPE of \input_[4].iserdes_dq_.iserdesdq\ : label is "PRIMITIVE";
  attribute OPT_MODIFIED of \input_[4].iserdes_dq_.iserdesdq\ : label is "MLO";
  attribute BOX_TYPE of \input_[5].iserdes_dq_.idelay_dq.idelaye2\ : label is "PRIMITIVE";
  attribute IODELAY_GROUP of \input_[5].iserdes_dq_.idelay_dq.idelaye2\ : label is "MIG_IODELAY_MIG0";
  attribute SIM_DELAY_D of \input_[5].iserdes_dq_.idelay_dq.idelaye2\ : label is 0;
  attribute BOX_TYPE of \input_[5].iserdes_dq_.iserdesdq\ : label is "PRIMITIVE";
  attribute OPT_MODIFIED of \input_[5].iserdes_dq_.iserdesdq\ : label is "MLO";
  attribute BOX_TYPE of \input_[6].iserdes_dq_.idelay_dq.idelaye2\ : label is "PRIMITIVE";
  attribute IODELAY_GROUP of \input_[6].iserdes_dq_.idelay_dq.idelaye2\ : label is "MIG_IODELAY_MIG0";
  attribute SIM_DELAY_D of \input_[6].iserdes_dq_.idelay_dq.idelaye2\ : label is 0;
  attribute BOX_TYPE of \input_[6].iserdes_dq_.iserdesdq\ : label is "PRIMITIVE";
  attribute OPT_MODIFIED of \input_[6].iserdes_dq_.iserdesdq\ : label is "MLO";
  attribute BOX_TYPE of \input_[7].iserdes_dq_.idelay_dq.idelaye2\ : label is "PRIMITIVE";
  attribute IODELAY_GROUP of \input_[7].iserdes_dq_.idelay_dq.idelaye2\ : label is "MIG_IODELAY_MIG0";
  attribute SIM_DELAY_D of \input_[7].iserdes_dq_.idelay_dq.idelaye2\ : label is 0;
  attribute BOX_TYPE of \input_[7].iserdes_dq_.iserdesdq\ : label is "PRIMITIVE";
  attribute OPT_MODIFIED of \input_[7].iserdes_dq_.iserdesdq\ : label is "MLO";
  attribute BOX_TYPE of \input_[8].iserdes_dq_.idelay_dq.idelaye2\ : label is "PRIMITIVE";
  attribute IODELAY_GROUP of \input_[8].iserdes_dq_.idelay_dq.idelaye2\ : label is "MIG_IODELAY_MIG0";
  attribute SIM_DELAY_D of \input_[8].iserdes_dq_.idelay_dq.idelaye2\ : label is 0;
  attribute BOX_TYPE of \input_[8].iserdes_dq_.iserdesdq\ : label is "PRIMITIVE";
  attribute OPT_MODIFIED of \input_[8].iserdes_dq_.iserdesdq\ : label is "MLO";
  attribute BOX_TYPE of \input_[9].iserdes_dq_.idelay_dq.idelaye2\ : label is "PRIMITIVE";
  attribute IODELAY_GROUP of \input_[9].iserdes_dq_.idelay_dq.idelaye2\ : label is "MIG_IODELAY_MIG0";
  attribute SIM_DELAY_D of \input_[9].iserdes_dq_.idelay_dq.idelaye2\ : label is 0;
  attribute BOX_TYPE of \input_[9].iserdes_dq_.iserdesdq\ : label is "PRIMITIVE";
  attribute OPT_MODIFIED of \input_[9].iserdes_dq_.iserdesdq\ : label is "MLO";
  attribute BOX_TYPE of \output_[1].oserdes_dq_.ddr.oserdes_dq_i\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \output_[2].oserdes_dq_.ddr.oserdes_dq_i\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \output_[3].oserdes_dq_.ddr.oserdes_dq_i\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \output_[4].oserdes_dq_.ddr.oserdes_dq_i\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \output_[5].oserdes_dq_.ddr.oserdes_dq_i\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \output_[6].oserdes_dq_.ddr.oserdes_dq_i\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \output_[7].oserdes_dq_.ddr.oserdes_dq_i\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \output_[8].oserdes_dq_.ddr.oserdes_dq_i\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \output_[9].oserdes_dq_.ddr.oserdes_dq_i\ : label is "PRIMITIVE";
  attribute srl_name : string;
  attribute srl_name of rst_r3_reg_srl3 : label is "\u_mig_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/rst_r3_reg_srl3 ";
  attribute BOX_TYPE of \slave_ts.oserdes_slave_ts\ : label is "PRIMITIVE";
begin
  idelay_ld_rst_6 <= \^idelay_ld_rst_6\;
  rst_r4 <= \^rst_r4\;
\dqs_gen.oddr_dqs\: unisim.vcomponents.ODDR
    generic map(
      DDR_CLK_EDGE => "SAME_EDGE",
      INIT => '0',
      IS_C_INVERTED => '0',
      IS_D1_INVERTED => '0',
      IS_D2_INVERTED => '0',
      SRTYPE => "SYNC"
    )
        port map (
      C => oserdes_clk_delayed,
      CE => '1',
      D1 => DQSBUS(0),
      D2 => DQSBUS(1),
      Q => out_dqs_3,
      R => '0',
      S => \NLW_dqs_gen.oddr_dqs_S_UNCONNECTED\
    );
\dqs_gen.oddr_dqsts\: unisim.vcomponents.ODDR
    generic map(
      DDR_CLK_EDGE => "SAME_EDGE",
      INIT => '0',
      IS_C_INVERTED => '0',
      IS_D1_INVERTED => '0',
      IS_D2_INVERTED => '0',
      SRTYPE => "SYNC"
    )
        port map (
      C => oserdes_clk_delayed,
      CE => '1',
      D1 => CTSBUS(0),
      D2 => CTSBUS(0),
      Q => ts_dqs_3,
      R => \NLW_dqs_gen.oddr_dqsts_R_UNCONNECTED\,
      S => '0'
    );
\idelay_ld_rst_i_1__6\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \^idelay_ld_rst_6\,
      I1 => \^rst_r4\,
      O => \idelay_ld_rst_i_1__6_n_0\
    );
idelay_ld_rst_reg: unisim.vcomponents.FDSE
     port map (
      C => idelay_ld_rst_reg_0,
      CE => '1',
      D => \idelay_ld_rst_i_1__6_n_0\,
      Q => \^idelay_ld_rst_6\,
      S => A_rst_primitives
    );
\input_[2].iserdes_dq_.idelay_dq.idelaye2\: unisim.vcomponents.IDELAYE2
    generic map(
      CINVCTRL_SEL => "FALSE",
      DELAY_SRC => "IDATAIN",
      HIGH_PERFORMANCE_MODE => "TRUE",
      IDELAY_TYPE => "VARIABLE",
      IDELAY_VALUE => 0,
      IS_C_INVERTED => '0',
      IS_DATAIN_INVERTED => '0',
      IS_IDATAIN_INVERTED => '0',
      PIPE_SEL => "FALSE",
      REFCLK_FREQUENCY => 200.000000,
      SIGNAL_PATTERN => "DATA"
    )
        port map (
      C => idelay_ld_rst_reg_0,
      CE => \input_[9].iserdes_dq_.iserdesdq_0\,
      CINVCTRL => '0',
      CNTVALUEIN(4 downto 0) => B"00000",
      CNTVALUEOUT(4 downto 0) => \NLW_input_[2].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED\(4 downto 0),
      DATAIN => '0',
      DATAOUT => data_in_dly_2,
      IDATAIN => mem_dq_in(0),
      INC => idelay_inc,
      LD => LD0_13,
      LDPIPEEN => '0',
      REGRST => A_rst_primitives
    );
\input_[2].iserdes_dq_.iserdesdq\: unisim.vcomponents.ISERDESE2
    generic map(
      DATA_RATE => "DDR",
      DATA_WIDTH => 4,
      DYN_CLKDIV_INV_EN => "FALSE",
      DYN_CLK_INV_EN => "FALSE",
      INIT_Q1 => '0',
      INIT_Q2 => '0',
      INIT_Q3 => '0',
      INIT_Q4 => '0',
      INTERFACE_TYPE => "MEMORY_DDR3",
      IOBDELAY => "IFD",
      IS_CLKB_INVERTED => '1',
      IS_CLKDIVP_INVERTED => '0',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D_INVERTED => '0',
      IS_OCLKB_INVERTED => '0',
      IS_OCLK_INVERTED => '0',
      NUM_CE => 2,
      OFB_USED => "FALSE",
      SERDES_MODE => "MASTER",
      SRVAL_Q1 => '0',
      SRVAL_Q2 => '0',
      SRVAL_Q3 => '0',
      SRVAL_Q4 => '0'
    )
        port map (
      BITSLIP => '0',
      CE1 => '1',
      CE2 => '1',
      CLK => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]\,
      CLKB => CLKB0_13,
      CLKDIV => \NLW_input_[2].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED\,
      CLKDIVP => iserdes_clkdiv,
      D => mem_dq_in(0),
      DDLY => data_in_dly_2,
      DYNCLKDIVSEL => '0',
      DYNCLKSEL => '0',
      O => \NLW_input_[2].iserdes_dq_.iserdesdq_O_UNCONNECTED\,
      OCLK => oserdes_clk,
      OCLKB => \NLW_input_[2].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED\,
      OFB => \NLW_input_[2].iserdes_dq_.iserdesdq_OFB_UNCONNECTED\,
      Q1 => D2(3),
      Q2 => D2(2),
      Q3 => D2(1),
      Q4 => D2(0),
      Q5 => \NLW_input_[2].iserdes_dq_.iserdesdq_Q5_UNCONNECTED\,
      Q6 => \NLW_input_[2].iserdes_dq_.iserdesdq_Q6_UNCONNECTED\,
      Q7 => \NLW_input_[2].iserdes_dq_.iserdesdq_Q7_UNCONNECTED\,
      Q8 => \NLW_input_[2].iserdes_dq_.iserdesdq_Q8_UNCONNECTED\,
      RST => '0',
      SHIFTIN1 => '0',
      SHIFTIN2 => '0',
      SHIFTOUT1 => \NLW_input_[2].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_input_[2].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED\
    );
\input_[3].iserdes_dq_.idelay_dq.idelaye2\: unisim.vcomponents.IDELAYE2
    generic map(
      CINVCTRL_SEL => "FALSE",
      DELAY_SRC => "IDATAIN",
      HIGH_PERFORMANCE_MODE => "TRUE",
      IDELAY_TYPE => "VARIABLE",
      IDELAY_VALUE => 0,
      IS_C_INVERTED => '0',
      IS_DATAIN_INVERTED => '0',
      IS_IDATAIN_INVERTED => '0',
      PIPE_SEL => "FALSE",
      REFCLK_FREQUENCY => 200.000000,
      SIGNAL_PATTERN => "DATA"
    )
        port map (
      C => idelay_ld_rst_reg_0,
      CE => \input_[9].iserdes_dq_.iserdesdq_0\,
      CINVCTRL => '0',
      CNTVALUEIN(4 downto 0) => B"00000",
      CNTVALUEOUT(4 downto 0) => \NLW_input_[3].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED\(4 downto 0),
      DATAIN => '0',
      DATAOUT => data_in_dly_3,
      IDATAIN => mem_dq_in(1),
      INC => idelay_inc,
      LD => LD0_13,
      LDPIPEEN => '0',
      REGRST => A_rst_primitives
    );
\input_[3].iserdes_dq_.iserdesdq\: unisim.vcomponents.ISERDESE2
    generic map(
      DATA_RATE => "DDR",
      DATA_WIDTH => 4,
      DYN_CLKDIV_INV_EN => "FALSE",
      DYN_CLK_INV_EN => "FALSE",
      INIT_Q1 => '0',
      INIT_Q2 => '0',
      INIT_Q3 => '0',
      INIT_Q4 => '0',
      INTERFACE_TYPE => "MEMORY_DDR3",
      IOBDELAY => "IFD",
      IS_CLKB_INVERTED => '1',
      IS_CLKDIVP_INVERTED => '0',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D_INVERTED => '0',
      IS_OCLKB_INVERTED => '0',
      IS_OCLK_INVERTED => '0',
      NUM_CE => 2,
      OFB_USED => "FALSE",
      SERDES_MODE => "MASTER",
      SRVAL_Q1 => '0',
      SRVAL_Q2 => '0',
      SRVAL_Q3 => '0',
      SRVAL_Q4 => '0'
    )
        port map (
      BITSLIP => '0',
      CE1 => '1',
      CE2 => '1',
      CLK => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]\,
      CLKB => CLKB0_13,
      CLKDIV => \NLW_input_[3].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED\,
      CLKDIVP => iserdes_clkdiv,
      D => mem_dq_in(1),
      DDLY => data_in_dly_3,
      DYNCLKDIVSEL => '0',
      DYNCLKSEL => '0',
      O => \NLW_input_[3].iserdes_dq_.iserdesdq_O_UNCONNECTED\,
      OCLK => oserdes_clk,
      OCLKB => \NLW_input_[3].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED\,
      OFB => \NLW_input_[3].iserdes_dq_.iserdesdq_OFB_UNCONNECTED\,
      Q1 => D3(3),
      Q2 => D3(2),
      Q3 => D3(1),
      Q4 => D3(0),
      Q5 => \NLW_input_[3].iserdes_dq_.iserdesdq_Q5_UNCONNECTED\,
      Q6 => \NLW_input_[3].iserdes_dq_.iserdesdq_Q6_UNCONNECTED\,
      Q7 => \NLW_input_[3].iserdes_dq_.iserdesdq_Q7_UNCONNECTED\,
      Q8 => \NLW_input_[3].iserdes_dq_.iserdesdq_Q8_UNCONNECTED\,
      RST => '0',
      SHIFTIN1 => '0',
      SHIFTIN2 => '0',
      SHIFTOUT1 => \NLW_input_[3].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_input_[3].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED\
    );
\input_[4].iserdes_dq_.idelay_dq.idelaye2\: unisim.vcomponents.IDELAYE2
    generic map(
      CINVCTRL_SEL => "FALSE",
      DELAY_SRC => "IDATAIN",
      HIGH_PERFORMANCE_MODE => "TRUE",
      IDELAY_TYPE => "VARIABLE",
      IDELAY_VALUE => 0,
      IS_C_INVERTED => '0',
      IS_DATAIN_INVERTED => '0',
      IS_IDATAIN_INVERTED => '0',
      PIPE_SEL => "FALSE",
      REFCLK_FREQUENCY => 200.000000,
      SIGNAL_PATTERN => "DATA"
    )
        port map (
      C => idelay_ld_rst_reg_0,
      CE => \input_[9].iserdes_dq_.iserdesdq_0\,
      CINVCTRL => '0',
      CNTVALUEIN(4 downto 0) => B"00000",
      CNTVALUEOUT(4 downto 0) => \NLW_input_[4].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED\(4 downto 0),
      DATAIN => '0',
      DATAOUT => data_in_dly_4,
      IDATAIN => mem_dq_in(2),
      INC => idelay_inc,
      LD => LD0_13,
      LDPIPEEN => '0',
      REGRST => A_rst_primitives
    );
\input_[4].iserdes_dq_.iserdesdq\: unisim.vcomponents.ISERDESE2
    generic map(
      DATA_RATE => "DDR",
      DATA_WIDTH => 4,
      DYN_CLKDIV_INV_EN => "FALSE",
      DYN_CLK_INV_EN => "FALSE",
      INIT_Q1 => '0',
      INIT_Q2 => '0',
      INIT_Q3 => '0',
      INIT_Q4 => '0',
      INTERFACE_TYPE => "MEMORY_DDR3",
      IOBDELAY => "IFD",
      IS_CLKB_INVERTED => '1',
      IS_CLKDIVP_INVERTED => '0',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D_INVERTED => '0',
      IS_OCLKB_INVERTED => '0',
      IS_OCLK_INVERTED => '0',
      NUM_CE => 2,
      OFB_USED => "FALSE",
      SERDES_MODE => "MASTER",
      SRVAL_Q1 => '0',
      SRVAL_Q2 => '0',
      SRVAL_Q3 => '0',
      SRVAL_Q4 => '0'
    )
        port map (
      BITSLIP => '0',
      CE1 => '1',
      CE2 => '1',
      CLK => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]\,
      CLKB => CLKB0_13,
      CLKDIV => \NLW_input_[4].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED\,
      CLKDIVP => iserdes_clkdiv,
      D => mem_dq_in(2),
      DDLY => data_in_dly_4,
      DYNCLKDIVSEL => '0',
      DYNCLKSEL => '0',
      O => \NLW_input_[4].iserdes_dq_.iserdesdq_O_UNCONNECTED\,
      OCLK => oserdes_clk,
      OCLKB => \NLW_input_[4].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED\,
      OFB => \NLW_input_[4].iserdes_dq_.iserdesdq_OFB_UNCONNECTED\,
      Q1 => D4(3),
      Q2 => D4(2),
      Q3 => D4(1),
      Q4 => D4(0),
      Q5 => \NLW_input_[4].iserdes_dq_.iserdesdq_Q5_UNCONNECTED\,
      Q6 => \NLW_input_[4].iserdes_dq_.iserdesdq_Q6_UNCONNECTED\,
      Q7 => \NLW_input_[4].iserdes_dq_.iserdesdq_Q7_UNCONNECTED\,
      Q8 => \NLW_input_[4].iserdes_dq_.iserdesdq_Q8_UNCONNECTED\,
      RST => '0',
      SHIFTIN1 => '0',
      SHIFTIN2 => '0',
      SHIFTOUT1 => \NLW_input_[4].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_input_[4].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED\
    );
\input_[5].iserdes_dq_.idelay_dq.idelaye2\: unisim.vcomponents.IDELAYE2
    generic map(
      CINVCTRL_SEL => "FALSE",
      DELAY_SRC => "IDATAIN",
      HIGH_PERFORMANCE_MODE => "TRUE",
      IDELAY_TYPE => "VARIABLE",
      IDELAY_VALUE => 0,
      IS_C_INVERTED => '0',
      IS_DATAIN_INVERTED => '0',
      IS_IDATAIN_INVERTED => '0',
      PIPE_SEL => "FALSE",
      REFCLK_FREQUENCY => 200.000000,
      SIGNAL_PATTERN => "DATA"
    )
        port map (
      C => idelay_ld_rst_reg_0,
      CE => \input_[9].iserdes_dq_.iserdesdq_0\,
      CINVCTRL => '0',
      CNTVALUEIN(4 downto 0) => B"00000",
      CNTVALUEOUT(4 downto 0) => \NLW_input_[5].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED\(4 downto 0),
      DATAIN => '0',
      DATAOUT => data_in_dly_5,
      IDATAIN => mem_dq_in(3),
      INC => idelay_inc,
      LD => LD0_13,
      LDPIPEEN => '0',
      REGRST => A_rst_primitives
    );
\input_[5].iserdes_dq_.iserdesdq\: unisim.vcomponents.ISERDESE2
    generic map(
      DATA_RATE => "DDR",
      DATA_WIDTH => 4,
      DYN_CLKDIV_INV_EN => "FALSE",
      DYN_CLK_INV_EN => "FALSE",
      INIT_Q1 => '0',
      INIT_Q2 => '0',
      INIT_Q3 => '0',
      INIT_Q4 => '0',
      INTERFACE_TYPE => "MEMORY_DDR3",
      IOBDELAY => "IFD",
      IS_CLKB_INVERTED => '1',
      IS_CLKDIVP_INVERTED => '0',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D_INVERTED => '0',
      IS_OCLKB_INVERTED => '0',
      IS_OCLK_INVERTED => '0',
      NUM_CE => 2,
      OFB_USED => "FALSE",
      SERDES_MODE => "MASTER",
      SRVAL_Q1 => '0',
      SRVAL_Q2 => '0',
      SRVAL_Q3 => '0',
      SRVAL_Q4 => '0'
    )
        port map (
      BITSLIP => '0',
      CE1 => '1',
      CE2 => '1',
      CLK => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]\,
      CLKB => CLKB0_13,
      CLKDIV => \NLW_input_[5].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED\,
      CLKDIVP => iserdes_clkdiv,
      D => mem_dq_in(3),
      DDLY => data_in_dly_5,
      DYNCLKDIVSEL => '0',
      DYNCLKSEL => '0',
      O => \NLW_input_[5].iserdes_dq_.iserdesdq_O_UNCONNECTED\,
      OCLK => oserdes_clk,
      OCLKB => \NLW_input_[5].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED\,
      OFB => \NLW_input_[5].iserdes_dq_.iserdesdq_OFB_UNCONNECTED\,
      Q1 => D5(3),
      Q2 => D5(2),
      Q3 => D5(1),
      Q4 => D5(0),
      Q5 => \NLW_input_[5].iserdes_dq_.iserdesdq_Q5_UNCONNECTED\,
      Q6 => \NLW_input_[5].iserdes_dq_.iserdesdq_Q6_UNCONNECTED\,
      Q7 => \NLW_input_[5].iserdes_dq_.iserdesdq_Q7_UNCONNECTED\,
      Q8 => \NLW_input_[5].iserdes_dq_.iserdesdq_Q8_UNCONNECTED\,
      RST => '0',
      SHIFTIN1 => '0',
      SHIFTIN2 => '0',
      SHIFTOUT1 => \NLW_input_[5].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_input_[5].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED\
    );
\input_[6].iserdes_dq_.idelay_dq.idelaye2\: unisim.vcomponents.IDELAYE2
    generic map(
      CINVCTRL_SEL => "FALSE",
      DELAY_SRC => "IDATAIN",
      HIGH_PERFORMANCE_MODE => "TRUE",
      IDELAY_TYPE => "VARIABLE",
      IDELAY_VALUE => 0,
      IS_C_INVERTED => '0',
      IS_DATAIN_INVERTED => '0',
      IS_IDATAIN_INVERTED => '0',
      PIPE_SEL => "FALSE",
      REFCLK_FREQUENCY => 200.000000,
      SIGNAL_PATTERN => "DATA"
    )
        port map (
      C => idelay_ld_rst_reg_0,
      CE => \input_[9].iserdes_dq_.iserdesdq_0\,
      CINVCTRL => '0',
      CNTVALUEIN(4 downto 0) => B"00000",
      CNTVALUEOUT(4 downto 0) => \NLW_input_[6].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED\(4 downto 0),
      DATAIN => '0',
      DATAOUT => data_in_dly_6,
      IDATAIN => mem_dq_in(4),
      INC => idelay_inc,
      LD => LD0_13,
      LDPIPEEN => '0',
      REGRST => A_rst_primitives
    );
\input_[6].iserdes_dq_.iserdesdq\: unisim.vcomponents.ISERDESE2
    generic map(
      DATA_RATE => "DDR",
      DATA_WIDTH => 4,
      DYN_CLKDIV_INV_EN => "FALSE",
      DYN_CLK_INV_EN => "FALSE",
      INIT_Q1 => '0',
      INIT_Q2 => '0',
      INIT_Q3 => '0',
      INIT_Q4 => '0',
      INTERFACE_TYPE => "MEMORY_DDR3",
      IOBDELAY => "IFD",
      IS_CLKB_INVERTED => '1',
      IS_CLKDIVP_INVERTED => '0',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D_INVERTED => '0',
      IS_OCLKB_INVERTED => '0',
      IS_OCLK_INVERTED => '0',
      NUM_CE => 2,
      OFB_USED => "FALSE",
      SERDES_MODE => "MASTER",
      SRVAL_Q1 => '0',
      SRVAL_Q2 => '0',
      SRVAL_Q3 => '0',
      SRVAL_Q4 => '0'
    )
        port map (
      BITSLIP => '0',
      CE1 => '1',
      CE2 => '1',
      CLK => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]\,
      CLKB => CLKB0_13,
      CLKDIV => \NLW_input_[6].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED\,
      CLKDIVP => iserdes_clkdiv,
      D => mem_dq_in(4),
      DDLY => data_in_dly_6,
      DYNCLKDIVSEL => '0',
      DYNCLKSEL => '0',
      O => \NLW_input_[6].iserdes_dq_.iserdesdq_O_UNCONNECTED\,
      OCLK => oserdes_clk,
      OCLKB => \NLW_input_[6].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED\,
      OFB => \NLW_input_[6].iserdes_dq_.iserdesdq_OFB_UNCONNECTED\,
      Q1 => D6(3),
      Q2 => D6(2),
      Q3 => D6(1),
      Q4 => D6(0),
      Q5 => \NLW_input_[6].iserdes_dq_.iserdesdq_Q5_UNCONNECTED\,
      Q6 => \NLW_input_[6].iserdes_dq_.iserdesdq_Q6_UNCONNECTED\,
      Q7 => \NLW_input_[6].iserdes_dq_.iserdesdq_Q7_UNCONNECTED\,
      Q8 => \NLW_input_[6].iserdes_dq_.iserdesdq_Q8_UNCONNECTED\,
      RST => '0',
      SHIFTIN1 => '0',
      SHIFTIN2 => '0',
      SHIFTOUT1 => \NLW_input_[6].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_input_[6].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED\
    );
\input_[7].iserdes_dq_.idelay_dq.idelaye2\: unisim.vcomponents.IDELAYE2
    generic map(
      CINVCTRL_SEL => "FALSE",
      DELAY_SRC => "IDATAIN",
      HIGH_PERFORMANCE_MODE => "TRUE",
      IDELAY_TYPE => "VARIABLE",
      IDELAY_VALUE => 0,
      IS_C_INVERTED => '0',
      IS_DATAIN_INVERTED => '0',
      IS_IDATAIN_INVERTED => '0',
      PIPE_SEL => "FALSE",
      REFCLK_FREQUENCY => 200.000000,
      SIGNAL_PATTERN => "DATA"
    )
        port map (
      C => idelay_ld_rst_reg_0,
      CE => \input_[9].iserdes_dq_.iserdesdq_0\,
      CINVCTRL => '0',
      CNTVALUEIN(4 downto 0) => B"00000",
      CNTVALUEOUT(4 downto 0) => \NLW_input_[7].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED\(4 downto 0),
      DATAIN => '0',
      DATAOUT => data_in_dly_7,
      IDATAIN => mem_dq_in(5),
      INC => idelay_inc,
      LD => LD0_13,
      LDPIPEEN => '0',
      REGRST => A_rst_primitives
    );
\input_[7].iserdes_dq_.iserdesdq\: unisim.vcomponents.ISERDESE2
    generic map(
      DATA_RATE => "DDR",
      DATA_WIDTH => 4,
      DYN_CLKDIV_INV_EN => "FALSE",
      DYN_CLK_INV_EN => "FALSE",
      INIT_Q1 => '0',
      INIT_Q2 => '0',
      INIT_Q3 => '0',
      INIT_Q4 => '0',
      INTERFACE_TYPE => "MEMORY_DDR3",
      IOBDELAY => "IFD",
      IS_CLKB_INVERTED => '1',
      IS_CLKDIVP_INVERTED => '0',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D_INVERTED => '0',
      IS_OCLKB_INVERTED => '0',
      IS_OCLK_INVERTED => '0',
      NUM_CE => 2,
      OFB_USED => "FALSE",
      SERDES_MODE => "MASTER",
      SRVAL_Q1 => '0',
      SRVAL_Q2 => '0',
      SRVAL_Q3 => '0',
      SRVAL_Q4 => '0'
    )
        port map (
      BITSLIP => '0',
      CE1 => '1',
      CE2 => '1',
      CLK => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]\,
      CLKB => CLKB0_13,
      CLKDIV => \NLW_input_[7].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED\,
      CLKDIVP => iserdes_clkdiv,
      D => mem_dq_in(5),
      DDLY => data_in_dly_7,
      DYNCLKDIVSEL => '0',
      DYNCLKSEL => '0',
      O => \NLW_input_[7].iserdes_dq_.iserdesdq_O_UNCONNECTED\,
      OCLK => oserdes_clk,
      OCLKB => \NLW_input_[7].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED\,
      OFB => \NLW_input_[7].iserdes_dq_.iserdesdq_OFB_UNCONNECTED\,
      Q1 => D7(3),
      Q2 => D7(2),
      Q3 => D7(1),
      Q4 => D7(0),
      Q5 => \NLW_input_[7].iserdes_dq_.iserdesdq_Q5_UNCONNECTED\,
      Q6 => \NLW_input_[7].iserdes_dq_.iserdesdq_Q6_UNCONNECTED\,
      Q7 => \NLW_input_[7].iserdes_dq_.iserdesdq_Q7_UNCONNECTED\,
      Q8 => \NLW_input_[7].iserdes_dq_.iserdesdq_Q8_UNCONNECTED\,
      RST => '0',
      SHIFTIN1 => '0',
      SHIFTIN2 => '0',
      SHIFTOUT1 => \NLW_input_[7].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_input_[7].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED\
    );
\input_[8].iserdes_dq_.idelay_dq.idelaye2\: unisim.vcomponents.IDELAYE2
    generic map(
      CINVCTRL_SEL => "FALSE",
      DELAY_SRC => "IDATAIN",
      HIGH_PERFORMANCE_MODE => "TRUE",
      IDELAY_TYPE => "VARIABLE",
      IDELAY_VALUE => 0,
      IS_C_INVERTED => '0',
      IS_DATAIN_INVERTED => '0',
      IS_IDATAIN_INVERTED => '0',
      PIPE_SEL => "FALSE",
      REFCLK_FREQUENCY => 200.000000,
      SIGNAL_PATTERN => "DATA"
    )
        port map (
      C => idelay_ld_rst_reg_0,
      CE => \input_[9].iserdes_dq_.iserdesdq_0\,
      CINVCTRL => '0',
      CNTVALUEIN(4 downto 0) => B"00000",
      CNTVALUEOUT(4 downto 0) => \NLW_input_[8].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED\(4 downto 0),
      DATAIN => '0',
      DATAOUT => data_in_dly_8,
      IDATAIN => mem_dq_in(6),
      INC => idelay_inc,
      LD => LD0_13,
      LDPIPEEN => '0',
      REGRST => A_rst_primitives
    );
\input_[8].iserdes_dq_.iserdesdq\: unisim.vcomponents.ISERDESE2
    generic map(
      DATA_RATE => "DDR",
      DATA_WIDTH => 4,
      DYN_CLKDIV_INV_EN => "FALSE",
      DYN_CLK_INV_EN => "FALSE",
      INIT_Q1 => '0',
      INIT_Q2 => '0',
      INIT_Q3 => '0',
      INIT_Q4 => '0',
      INTERFACE_TYPE => "MEMORY_DDR3",
      IOBDELAY => "IFD",
      IS_CLKB_INVERTED => '1',
      IS_CLKDIVP_INVERTED => '0',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D_INVERTED => '0',
      IS_OCLKB_INVERTED => '0',
      IS_OCLK_INVERTED => '0',
      NUM_CE => 2,
      OFB_USED => "FALSE",
      SERDES_MODE => "MASTER",
      SRVAL_Q1 => '0',
      SRVAL_Q2 => '0',
      SRVAL_Q3 => '0',
      SRVAL_Q4 => '0'
    )
        port map (
      BITSLIP => '0',
      CE1 => '1',
      CE2 => '1',
      CLK => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]\,
      CLKB => CLKB0_13,
      CLKDIV => \NLW_input_[8].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED\,
      CLKDIVP => iserdes_clkdiv,
      D => mem_dq_in(6),
      DDLY => data_in_dly_8,
      DYNCLKDIVSEL => '0',
      DYNCLKSEL => '0',
      O => \NLW_input_[8].iserdes_dq_.iserdesdq_O_UNCONNECTED\,
      OCLK => oserdes_clk,
      OCLKB => \NLW_input_[8].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED\,
      OFB => \NLW_input_[8].iserdes_dq_.iserdesdq_OFB_UNCONNECTED\,
      Q1 => D8(3),
      Q2 => D8(2),
      Q3 => D8(1),
      Q4 => D8(0),
      Q5 => \NLW_input_[8].iserdes_dq_.iserdesdq_Q5_UNCONNECTED\,
      Q6 => \NLW_input_[8].iserdes_dq_.iserdesdq_Q6_UNCONNECTED\,
      Q7 => \NLW_input_[8].iserdes_dq_.iserdesdq_Q7_UNCONNECTED\,
      Q8 => \NLW_input_[8].iserdes_dq_.iserdesdq_Q8_UNCONNECTED\,
      RST => '0',
      SHIFTIN1 => '0',
      SHIFTIN2 => '0',
      SHIFTOUT1 => \NLW_input_[8].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_input_[8].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED\
    );
\input_[9].iserdes_dq_.idelay_dq.idelaye2\: unisim.vcomponents.IDELAYE2
    generic map(
      CINVCTRL_SEL => "FALSE",
      DELAY_SRC => "IDATAIN",
      HIGH_PERFORMANCE_MODE => "TRUE",
      IDELAY_TYPE => "VARIABLE",
      IDELAY_VALUE => 0,
      IS_C_INVERTED => '0',
      IS_DATAIN_INVERTED => '0',
      IS_IDATAIN_INVERTED => '0',
      PIPE_SEL => "FALSE",
      REFCLK_FREQUENCY => 200.000000,
      SIGNAL_PATTERN => "DATA"
    )
        port map (
      C => idelay_ld_rst_reg_0,
      CE => \input_[9].iserdes_dq_.iserdesdq_0\,
      CINVCTRL => '0',
      CNTVALUEIN(4 downto 0) => B"00000",
      CNTVALUEOUT(4 downto 0) => \NLW_input_[9].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED\(4 downto 0),
      DATAIN => '0',
      DATAOUT => data_in_dly_9,
      IDATAIN => mem_dq_in(7),
      INC => idelay_inc,
      LD => LD0_13,
      LDPIPEEN => '0',
      REGRST => A_rst_primitives
    );
\input_[9].iserdes_dq_.iserdesdq\: unisim.vcomponents.ISERDESE2
    generic map(
      DATA_RATE => "DDR",
      DATA_WIDTH => 4,
      DYN_CLKDIV_INV_EN => "FALSE",
      DYN_CLK_INV_EN => "FALSE",
      INIT_Q1 => '0',
      INIT_Q2 => '0',
      INIT_Q3 => '0',
      INIT_Q4 => '0',
      INTERFACE_TYPE => "MEMORY_DDR3",
      IOBDELAY => "IFD",
      IS_CLKB_INVERTED => '1',
      IS_CLKDIVP_INVERTED => '0',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D_INVERTED => '0',
      IS_OCLKB_INVERTED => '0',
      IS_OCLK_INVERTED => '0',
      NUM_CE => 2,
      OFB_USED => "FALSE",
      SERDES_MODE => "MASTER",
      SRVAL_Q1 => '0',
      SRVAL_Q2 => '0',
      SRVAL_Q3 => '0',
      SRVAL_Q4 => '0'
    )
        port map (
      BITSLIP => '0',
      CE1 => '1',
      CE2 => '1',
      CLK => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]\,
      CLKB => CLKB0_13,
      CLKDIV => \NLW_input_[9].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED\,
      CLKDIVP => iserdes_clkdiv,
      D => mem_dq_in(7),
      DDLY => data_in_dly_9,
      DYNCLKDIVSEL => '0',
      DYNCLKSEL => '0',
      O => \NLW_input_[9].iserdes_dq_.iserdesdq_O_UNCONNECTED\,
      OCLK => oserdes_clk,
      OCLKB => \NLW_input_[9].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED\,
      OFB => \NLW_input_[9].iserdes_dq_.iserdesdq_OFB_UNCONNECTED\,
      Q1 => D9(3),
      Q2 => D9(2),
      Q3 => D9(1),
      Q4 => D9(0),
      Q5 => \NLW_input_[9].iserdes_dq_.iserdesdq_Q5_UNCONNECTED\,
      Q6 => \NLW_input_[9].iserdes_dq_.iserdesdq_Q6_UNCONNECTED\,
      Q7 => \NLW_input_[9].iserdes_dq_.iserdesdq_Q7_UNCONNECTED\,
      Q8 => \NLW_input_[9].iserdes_dq_.iserdesdq_Q8_UNCONNECTED\,
      RST => '0',
      SHIFTIN1 => '0',
      SHIFTIN2 => '0',
      SHIFTOUT1 => \NLW_input_[9].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_input_[9].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED\
    );
\output_[1].oserdes_dq_.ddr.oserdes_dq_i\: unisim.vcomponents.OSERDESE2
    generic map(
      DATA_RATE_OQ => "DDR",
      DATA_RATE_TQ => "DDR",
      DATA_WIDTH => 4,
      INIT_OQ => '1',
      INIT_TQ => '1',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D1_INVERTED => '0',
      IS_D2_INVERTED => '0',
      IS_D3_INVERTED => '0',
      IS_D4_INVERTED => '0',
      IS_D5_INVERTED => '0',
      IS_D6_INVERTED => '0',
      IS_D7_INVERTED => '0',
      IS_D8_INVERTED => '0',
      IS_T1_INVERTED => '0',
      IS_T2_INVERTED => '0',
      IS_T3_INVERTED => '0',
      IS_T4_INVERTED => '0',
      SERDES_MODE => "MASTER",
      SRVAL_OQ => '1',
      SRVAL_TQ => '1',
      TBYTE_CTL => "TRUE",
      TBYTE_SRC => "FALSE",
      TRISTATE_WIDTH => 4
    )
        port map (
      CLK => oserdes_clk,
      CLKDIV => oserdes_clkdiv,
      D1 => of_dqbus(0),
      D2 => of_dqbus(1),
      D3 => of_dqbus(2),
      D4 => of_dqbus(3),
      D5 => '0',
      D6 => '0',
      D7 => '0',
      D8 => '0',
      OCE => '1',
      OFB => \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\,
      OQ => mem_dq_out(0),
      RST => po_oserdes_rst,
      SHIFTIN1 => \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\,
      SHIFTIN2 => \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\,
      SHIFTOUT1 => \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\,
      T1 => '0',
      T2 => '0',
      T3 => '0',
      T4 => '0',
      TBYTEIN => tbyte_out,
      TBYTEOUT => \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\,
      TCE => '1',
      TFB => \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\,
      TQ => mem_dq_ts(0)
    );
\output_[2].oserdes_dq_.ddr.oserdes_dq_i\: unisim.vcomponents.OSERDESE2
    generic map(
      DATA_RATE_OQ => "DDR",
      DATA_RATE_TQ => "DDR",
      DATA_WIDTH => 4,
      INIT_OQ => '1',
      INIT_TQ => '1',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D1_INVERTED => '0',
      IS_D2_INVERTED => '0',
      IS_D3_INVERTED => '0',
      IS_D4_INVERTED => '0',
      IS_D5_INVERTED => '0',
      IS_D6_INVERTED => '0',
      IS_D7_INVERTED => '0',
      IS_D8_INVERTED => '0',
      IS_T1_INVERTED => '0',
      IS_T2_INVERTED => '0',
      IS_T3_INVERTED => '0',
      IS_T4_INVERTED => '0',
      SERDES_MODE => "MASTER",
      SRVAL_OQ => '1',
      SRVAL_TQ => '1',
      TBYTE_CTL => "TRUE",
      TBYTE_SRC => "FALSE",
      TRISTATE_WIDTH => 4
    )
        port map (
      CLK => oserdes_clk,
      CLKDIV => oserdes_clkdiv,
      D1 => of_dqbus(4),
      D2 => of_dqbus(5),
      D3 => of_dqbus(6),
      D4 => of_dqbus(7),
      D5 => '0',
      D6 => '0',
      D7 => '0',
      D8 => '0',
      OCE => '1',
      OFB => \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\,
      OQ => mem_dq_out(1),
      RST => po_oserdes_rst,
      SHIFTIN1 => \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\,
      SHIFTIN2 => \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\,
      SHIFTOUT1 => \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\,
      T1 => '0',
      T2 => '0',
      T3 => '0',
      T4 => '0',
      TBYTEIN => tbyte_out,
      TBYTEOUT => \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\,
      TCE => '1',
      TFB => \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\,
      TQ => mem_dq_ts(1)
    );
\output_[3].oserdes_dq_.ddr.oserdes_dq_i\: unisim.vcomponents.OSERDESE2
    generic map(
      DATA_RATE_OQ => "DDR",
      DATA_RATE_TQ => "DDR",
      DATA_WIDTH => 4,
      INIT_OQ => '1',
      INIT_TQ => '1',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D1_INVERTED => '0',
      IS_D2_INVERTED => '0',
      IS_D3_INVERTED => '0',
      IS_D4_INVERTED => '0',
      IS_D5_INVERTED => '0',
      IS_D6_INVERTED => '0',
      IS_D7_INVERTED => '0',
      IS_D8_INVERTED => '0',
      IS_T1_INVERTED => '0',
      IS_T2_INVERTED => '0',
      IS_T3_INVERTED => '0',
      IS_T4_INVERTED => '0',
      SERDES_MODE => "MASTER",
      SRVAL_OQ => '1',
      SRVAL_TQ => '1',
      TBYTE_CTL => "TRUE",
      TBYTE_SRC => "FALSE",
      TRISTATE_WIDTH => 4
    )
        port map (
      CLK => oserdes_clk,
      CLKDIV => oserdes_clkdiv,
      D1 => of_dqbus(8),
      D2 => of_dqbus(9),
      D3 => of_dqbus(10),
      D4 => of_dqbus(11),
      D5 => '0',
      D6 => '0',
      D7 => '0',
      D8 => '0',
      OCE => '1',
      OFB => \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\,
      OQ => mem_dq_out(2),
      RST => po_oserdes_rst,
      SHIFTIN1 => \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\,
      SHIFTIN2 => \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\,
      SHIFTOUT1 => \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\,
      T1 => '0',
      T2 => '0',
      T3 => '0',
      T4 => '0',
      TBYTEIN => tbyte_out,
      TBYTEOUT => \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\,
      TCE => '1',
      TFB => \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\,
      TQ => mem_dq_ts(2)
    );
\output_[4].oserdes_dq_.ddr.oserdes_dq_i\: unisim.vcomponents.OSERDESE2
    generic map(
      DATA_RATE_OQ => "DDR",
      DATA_RATE_TQ => "DDR",
      DATA_WIDTH => 4,
      INIT_OQ => '1',
      INIT_TQ => '1',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D1_INVERTED => '0',
      IS_D2_INVERTED => '0',
      IS_D3_INVERTED => '0',
      IS_D4_INVERTED => '0',
      IS_D5_INVERTED => '0',
      IS_D6_INVERTED => '0',
      IS_D7_INVERTED => '0',
      IS_D8_INVERTED => '0',
      IS_T1_INVERTED => '0',
      IS_T2_INVERTED => '0',
      IS_T3_INVERTED => '0',
      IS_T4_INVERTED => '0',
      SERDES_MODE => "MASTER",
      SRVAL_OQ => '1',
      SRVAL_TQ => '1',
      TBYTE_CTL => "TRUE",
      TBYTE_SRC => "FALSE",
      TRISTATE_WIDTH => 4
    )
        port map (
      CLK => oserdes_clk,
      CLKDIV => oserdes_clkdiv,
      D1 => of_dqbus(12),
      D2 => of_dqbus(13),
      D3 => of_dqbus(14),
      D4 => of_dqbus(15),
      D5 => '0',
      D6 => '0',
      D7 => '0',
      D8 => '0',
      OCE => '1',
      OFB => \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\,
      OQ => mem_dq_out(3),
      RST => po_oserdes_rst,
      SHIFTIN1 => \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\,
      SHIFTIN2 => \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\,
      SHIFTOUT1 => \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\,
      T1 => '0',
      T2 => '0',
      T3 => '0',
      T4 => '0',
      TBYTEIN => tbyte_out,
      TBYTEOUT => \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\,
      TCE => '1',
      TFB => \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\,
      TQ => mem_dq_ts(3)
    );
\output_[5].oserdes_dq_.ddr.oserdes_dq_i\: unisim.vcomponents.OSERDESE2
    generic map(
      DATA_RATE_OQ => "DDR",
      DATA_RATE_TQ => "DDR",
      DATA_WIDTH => 4,
      INIT_OQ => '1',
      INIT_TQ => '1',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D1_INVERTED => '0',
      IS_D2_INVERTED => '0',
      IS_D3_INVERTED => '0',
      IS_D4_INVERTED => '0',
      IS_D5_INVERTED => '0',
      IS_D6_INVERTED => '0',
      IS_D7_INVERTED => '0',
      IS_D8_INVERTED => '0',
      IS_T1_INVERTED => '0',
      IS_T2_INVERTED => '0',
      IS_T3_INVERTED => '0',
      IS_T4_INVERTED => '0',
      SERDES_MODE => "MASTER",
      SRVAL_OQ => '1',
      SRVAL_TQ => '1',
      TBYTE_CTL => "TRUE",
      TBYTE_SRC => "FALSE",
      TRISTATE_WIDTH => 4
    )
        port map (
      CLK => oserdes_clk,
      CLKDIV => oserdes_clkdiv,
      D1 => of_dqbus(16),
      D2 => of_dqbus(17),
      D3 => of_dqbus(18),
      D4 => of_dqbus(19),
      D5 => '0',
      D6 => '0',
      D7 => '0',
      D8 => '0',
      OCE => '1',
      OFB => \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\,
      OQ => mem_dq_out(4),
      RST => po_oserdes_rst,
      SHIFTIN1 => \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\,
      SHIFTIN2 => \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\,
      SHIFTOUT1 => \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\,
      T1 => '0',
      T2 => '0',
      T3 => '0',
      T4 => '0',
      TBYTEIN => tbyte_out,
      TBYTEOUT => \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\,
      TCE => '1',
      TFB => \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\,
      TQ => mem_dq_ts(4)
    );
\output_[6].oserdes_dq_.ddr.oserdes_dq_i\: unisim.vcomponents.OSERDESE2
    generic map(
      DATA_RATE_OQ => "DDR",
      DATA_RATE_TQ => "DDR",
      DATA_WIDTH => 4,
      INIT_OQ => '1',
      INIT_TQ => '1',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D1_INVERTED => '0',
      IS_D2_INVERTED => '0',
      IS_D3_INVERTED => '0',
      IS_D4_INVERTED => '0',
      IS_D5_INVERTED => '0',
      IS_D6_INVERTED => '0',
      IS_D7_INVERTED => '0',
      IS_D8_INVERTED => '0',
      IS_T1_INVERTED => '0',
      IS_T2_INVERTED => '0',
      IS_T3_INVERTED => '0',
      IS_T4_INVERTED => '0',
      SERDES_MODE => "MASTER",
      SRVAL_OQ => '1',
      SRVAL_TQ => '1',
      TBYTE_CTL => "TRUE",
      TBYTE_SRC => "FALSE",
      TRISTATE_WIDTH => 4
    )
        port map (
      CLK => oserdes_clk,
      CLKDIV => oserdes_clkdiv,
      D1 => of_dqbus(20),
      D2 => of_dqbus(21),
      D3 => of_dqbus(22),
      D4 => of_dqbus(23),
      D5 => '0',
      D6 => '0',
      D7 => '0',
      D8 => '0',
      OCE => '1',
      OFB => \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\,
      OQ => mem_dq_out(5),
      RST => po_oserdes_rst,
      SHIFTIN1 => \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\,
      SHIFTIN2 => \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\,
      SHIFTOUT1 => \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\,
      T1 => '0',
      T2 => '0',
      T3 => '0',
      T4 => '0',
      TBYTEIN => tbyte_out,
      TBYTEOUT => \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\,
      TCE => '1',
      TFB => \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\,
      TQ => mem_dq_ts(5)
    );
\output_[7].oserdes_dq_.ddr.oserdes_dq_i\: unisim.vcomponents.OSERDESE2
    generic map(
      DATA_RATE_OQ => "DDR",
      DATA_RATE_TQ => "DDR",
      DATA_WIDTH => 4,
      INIT_OQ => '1',
      INIT_TQ => '1',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D1_INVERTED => '0',
      IS_D2_INVERTED => '0',
      IS_D3_INVERTED => '0',
      IS_D4_INVERTED => '0',
      IS_D5_INVERTED => '0',
      IS_D6_INVERTED => '0',
      IS_D7_INVERTED => '0',
      IS_D8_INVERTED => '0',
      IS_T1_INVERTED => '0',
      IS_T2_INVERTED => '0',
      IS_T3_INVERTED => '0',
      IS_T4_INVERTED => '0',
      SERDES_MODE => "MASTER",
      SRVAL_OQ => '1',
      SRVAL_TQ => '1',
      TBYTE_CTL => "TRUE",
      TBYTE_SRC => "FALSE",
      TRISTATE_WIDTH => 4
    )
        port map (
      CLK => oserdes_clk,
      CLKDIV => oserdes_clkdiv,
      D1 => of_dqbus(24),
      D2 => of_dqbus(25),
      D3 => of_dqbus(26),
      D4 => of_dqbus(27),
      D5 => '0',
      D6 => '0',
      D7 => '0',
      D8 => '0',
      OCE => '1',
      OFB => \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\,
      OQ => mem_dq_out(6),
      RST => po_oserdes_rst,
      SHIFTIN1 => \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\,
      SHIFTIN2 => \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\,
      SHIFTOUT1 => \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\,
      T1 => '0',
      T2 => '0',
      T3 => '0',
      T4 => '0',
      TBYTEIN => tbyte_out,
      TBYTEOUT => \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\,
      TCE => '1',
      TFB => \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\,
      TQ => mem_dq_ts(6)
    );
\output_[8].oserdes_dq_.ddr.oserdes_dq_i\: unisim.vcomponents.OSERDESE2
    generic map(
      DATA_RATE_OQ => "DDR",
      DATA_RATE_TQ => "DDR",
      DATA_WIDTH => 4,
      INIT_OQ => '1',
      INIT_TQ => '1',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D1_INVERTED => '0',
      IS_D2_INVERTED => '0',
      IS_D3_INVERTED => '0',
      IS_D4_INVERTED => '0',
      IS_D5_INVERTED => '0',
      IS_D6_INVERTED => '0',
      IS_D7_INVERTED => '0',
      IS_D8_INVERTED => '0',
      IS_T1_INVERTED => '0',
      IS_T2_INVERTED => '0',
      IS_T3_INVERTED => '0',
      IS_T4_INVERTED => '0',
      SERDES_MODE => "MASTER",
      SRVAL_OQ => '1',
      SRVAL_TQ => '1',
      TBYTE_CTL => "TRUE",
      TBYTE_SRC => "FALSE",
      TRISTATE_WIDTH => 4
    )
        port map (
      CLK => oserdes_clk,
      CLKDIV => oserdes_clkdiv,
      D1 => of_dqbus(28),
      D2 => of_dqbus(29),
      D3 => of_dqbus(30),
      D4 => of_dqbus(31),
      D5 => '0',
      D6 => '0',
      D7 => '0',
      D8 => '0',
      OCE => '1',
      OFB => \NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\,
      OQ => mem_dq_out(7),
      RST => po_oserdes_rst,
      SHIFTIN1 => \NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\,
      SHIFTIN2 => \NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\,
      SHIFTOUT1 => \NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\,
      T1 => '0',
      T2 => '0',
      T3 => '0',
      T4 => '0',
      TBYTEIN => tbyte_out,
      TBYTEOUT => \NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\,
      TCE => '1',
      TFB => \NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\,
      TQ => mem_dq_ts(7)
    );
\output_[9].oserdes_dq_.ddr.oserdes_dq_i\: unisim.vcomponents.OSERDESE2
    generic map(
      DATA_RATE_OQ => "DDR",
      DATA_RATE_TQ => "DDR",
      DATA_WIDTH => 4,
      INIT_OQ => '1',
      INIT_TQ => '1',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D1_INVERTED => '0',
      IS_D2_INVERTED => '0',
      IS_D3_INVERTED => '0',
      IS_D4_INVERTED => '0',
      IS_D5_INVERTED => '0',
      IS_D6_INVERTED => '0',
      IS_D7_INVERTED => '0',
      IS_D8_INVERTED => '0',
      IS_T1_INVERTED => '0',
      IS_T2_INVERTED => '0',
      IS_T3_INVERTED => '0',
      IS_T4_INVERTED => '0',
      SERDES_MODE => "MASTER",
      SRVAL_OQ => '1',
      SRVAL_TQ => '1',
      TBYTE_CTL => "TRUE",
      TBYTE_SRC => "FALSE",
      TRISTATE_WIDTH => 4
    )
        port map (
      CLK => oserdes_clk,
      CLKDIV => oserdes_clkdiv,
      D1 => of_dqbus(32),
      D2 => of_dqbus(33),
      D3 => of_dqbus(34),
      D4 => of_dqbus(35),
      D5 => '0',
      D6 => '0',
      D7 => '0',
      D8 => '0',
      OCE => '1',
      OFB => \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\,
      OQ => mem_dq_out(8),
      RST => po_oserdes_rst,
      SHIFTIN1 => \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\,
      SHIFTIN2 => \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\,
      SHIFTOUT1 => \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\,
      T1 => '0',
      T2 => '0',
      T3 => '0',
      T4 => '0',
      TBYTEIN => tbyte_out,
      TBYTEOUT => \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\,
      TCE => '1',
      TFB => \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\,
      TQ => mem_dq_ts(8)
    );
rst_r3_reg_srl3: unisim.vcomponents.SRL16E
     port map (
      A0 => '0',
      A1 => '1',
      A2 => '0',
      A3 => '0',
      CE => '1',
      CLK => idelay_ld_rst_reg_0,
      D => A_rst_primitives,
      Q => rst_r3_reg_srl3_n_0
    );
rst_r4_reg: unisim.vcomponents.FDRE
     port map (
      C => idelay_ld_rst_reg_0,
      CE => '1',
      D => rst_r3_reg_srl3_n_0,
      Q => \^rst_r4\,
      R => '0'
    );
\slave_ts.oserdes_slave_ts\: unisim.vcomponents.OSERDESE2
    generic map(
      DATA_RATE_OQ => "DDR",
      DATA_RATE_TQ => "DDR",
      DATA_WIDTH => 4,
      INIT_OQ => '1',
      INIT_TQ => '1',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D1_INVERTED => '0',
      IS_D2_INVERTED => '0',
      IS_D3_INVERTED => '0',
      IS_D4_INVERTED => '0',
      IS_D5_INVERTED => '0',
      IS_D6_INVERTED => '0',
      IS_D7_INVERTED => '0',
      IS_D8_INVERTED => '0',
      IS_T1_INVERTED => '0',
      IS_T2_INVERTED => '0',
      IS_T3_INVERTED => '0',
      IS_T4_INVERTED => '0',
      SERDES_MODE => "MASTER",
      SRVAL_OQ => '1',
      SRVAL_TQ => '1',
      TBYTE_CTL => "TRUE",
      TBYTE_SRC => "TRUE",
      TRISTATE_WIDTH => 4
    )
        port map (
      CLK => oserdes_clk,
      CLKDIV => oserdes_clkdiv,
      D1 => '0',
      D2 => '0',
      D3 => '0',
      D4 => '0',
      D5 => '0',
      D6 => '0',
      D7 => '0',
      D8 => '0',
      OCE => '1',
      OFB => \NLW_slave_ts.oserdes_slave_ts_OFB_UNCONNECTED\,
      OQ => \NLW_slave_ts.oserdes_slave_ts_OQ_UNCONNECTED\,
      RST => po_oserdes_rst,
      SHIFTIN1 => \NLW_slave_ts.oserdes_slave_ts_SHIFTIN1_UNCONNECTED\,
      SHIFTIN2 => \NLW_slave_ts.oserdes_slave_ts_SHIFTIN2_UNCONNECTED\,
      SHIFTOUT1 => \NLW_slave_ts.oserdes_slave_ts_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_slave_ts.oserdes_slave_ts_SHIFTOUT2_UNCONNECTED\,
      T1 => DTSBUS(0),
      T2 => DTSBUS(0),
      T3 => DTSBUS(1),
      T4 => DTSBUS(1),
      TBYTEIN => tbyte_out,
      TBYTEOUT => tbyte_out,
      TCE => '1',
      TFB => \NLW_slave_ts.oserdes_slave_ts_TFB_UNCONNECTED\,
      TQ => \NLW_slave_ts.oserdes_slave_ts_TQ_UNCONNECTED\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \mig_mig_7series_v4_2_ddr_byte_group_io__parameterized0_14\ is
  port (
    out_dqs_2 : out STD_LOGIC;
    ts_dqs_2 : out STD_LOGIC;
    D2 : out STD_LOGIC_VECTOR ( 3 downto 0 );
    D3 : out STD_LOGIC_VECTOR ( 3 downto 0 );
    D4 : out STD_LOGIC_VECTOR ( 3 downto 0 );
    D5 : out STD_LOGIC_VECTOR ( 3 downto 0 );
    D6 : out STD_LOGIC_VECTOR ( 3 downto 0 );
    D7 : out STD_LOGIC_VECTOR ( 3 downto 0 );
    D8 : out STD_LOGIC_VECTOR ( 3 downto 0 );
    D9 : out STD_LOGIC_VECTOR ( 3 downto 0 );
    mem_dq_out : out STD_LOGIC_VECTOR ( 8 downto 0 );
    mem_dq_ts : out STD_LOGIC_VECTOR ( 8 downto 0 );
    idelay_ld_rst_5 : out STD_LOGIC;
    oserdes_clk : in STD_LOGIC;
    oserdes_clkdiv : in STD_LOGIC;
    po_oserdes_rst : in STD_LOGIC;
    DTSBUS : in STD_LOGIC_VECTOR ( 1 downto 0 );
    oserdes_clk_delayed : in STD_LOGIC;
    DQSBUS : in STD_LOGIC_VECTOR ( 1 downto 0 );
    CTSBUS : in STD_LOGIC_VECTOR ( 0 to 0 );
    idelay_ld_rst_reg_0 : in STD_LOGIC;
    \input_[9].iserdes_dq_.iserdesdq_0\ : in STD_LOGIC;
    mem_dq_in : in STD_LOGIC_VECTOR ( 7 downto 0 );
    idelay_inc : in STD_LOGIC;
    LD0_12 : in STD_LOGIC;
    A_rst_primitives : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]\ : in STD_LOGIC;
    CLKB0_12 : in STD_LOGIC;
    iserdes_clkdiv : in STD_LOGIC;
    of_dqbus : in STD_LOGIC_VECTOR ( 35 downto 0 );
    rst_r4 : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \mig_mig_7series_v4_2_ddr_byte_group_io__parameterized0_14\ : entity is "mig_7series_v4_2_ddr_byte_group_io";
end \mig_mig_7series_v4_2_ddr_byte_group_io__parameterized0_14\;

architecture STRUCTURE of \mig_mig_7series_v4_2_ddr_byte_group_io__parameterized0_14\ is
  signal data_in_dly_2 : STD_LOGIC;
  signal data_in_dly_3 : STD_LOGIC;
  signal data_in_dly_4 : STD_LOGIC;
  signal data_in_dly_5 : STD_LOGIC;
  signal data_in_dly_6 : STD_LOGIC;
  signal data_in_dly_7 : STD_LOGIC;
  signal data_in_dly_8 : STD_LOGIC;
  signal data_in_dly_9 : STD_LOGIC;
  signal \^idelay_ld_rst_5\ : STD_LOGIC;
  signal \idelay_ld_rst_i_1__5_n_0\ : STD_LOGIC;
  signal tbyte_out : STD_LOGIC;
  signal \NLW_dqs_gen.oddr_dqs_S_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_dqs_gen.oddr_dqsts_R_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[2].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal \NLW_input_[2].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[2].iserdes_dq_.iserdesdq_O_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[2].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[2].iserdes_dq_.iserdesdq_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[2].iserdes_dq_.iserdesdq_Q5_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[2].iserdes_dq_.iserdesdq_Q6_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[2].iserdes_dq_.iserdesdq_Q7_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[2].iserdes_dq_.iserdesdq_Q8_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[2].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[2].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[3].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal \NLW_input_[3].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[3].iserdes_dq_.iserdesdq_O_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[3].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[3].iserdes_dq_.iserdesdq_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[3].iserdes_dq_.iserdesdq_Q5_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[3].iserdes_dq_.iserdesdq_Q6_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[3].iserdes_dq_.iserdesdq_Q7_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[3].iserdes_dq_.iserdesdq_Q8_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[3].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[3].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[4].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal \NLW_input_[4].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[4].iserdes_dq_.iserdesdq_O_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[4].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[4].iserdes_dq_.iserdesdq_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[4].iserdes_dq_.iserdesdq_Q5_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[4].iserdes_dq_.iserdesdq_Q6_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[4].iserdes_dq_.iserdesdq_Q7_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[4].iserdes_dq_.iserdesdq_Q8_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[4].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[4].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[5].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal \NLW_input_[5].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[5].iserdes_dq_.iserdesdq_O_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[5].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[5].iserdes_dq_.iserdesdq_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[5].iserdes_dq_.iserdesdq_Q5_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[5].iserdes_dq_.iserdesdq_Q6_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[5].iserdes_dq_.iserdesdq_Q7_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[5].iserdes_dq_.iserdesdq_Q8_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[5].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[5].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[6].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal \NLW_input_[6].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[6].iserdes_dq_.iserdesdq_O_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[6].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[6].iserdes_dq_.iserdesdq_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[6].iserdes_dq_.iserdesdq_Q5_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[6].iserdes_dq_.iserdesdq_Q6_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[6].iserdes_dq_.iserdesdq_Q7_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[6].iserdes_dq_.iserdesdq_Q8_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[6].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[6].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[7].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal \NLW_input_[7].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[7].iserdes_dq_.iserdesdq_O_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[7].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[7].iserdes_dq_.iserdesdq_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[7].iserdes_dq_.iserdesdq_Q5_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[7].iserdes_dq_.iserdesdq_Q6_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[7].iserdes_dq_.iserdesdq_Q7_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[7].iserdes_dq_.iserdesdq_Q8_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[7].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[7].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[8].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal \NLW_input_[8].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[8].iserdes_dq_.iserdesdq_O_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[8].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[8].iserdes_dq_.iserdesdq_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[8].iserdes_dq_.iserdesdq_Q5_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[8].iserdes_dq_.iserdesdq_Q6_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[8].iserdes_dq_.iserdesdq_Q7_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[8].iserdes_dq_.iserdesdq_Q8_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[8].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[8].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[9].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal \NLW_input_[9].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[9].iserdes_dq_.iserdesdq_O_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[9].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[9].iserdes_dq_.iserdesdq_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[9].iserdes_dq_.iserdesdq_Q5_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[9].iserdes_dq_.iserdesdq_Q6_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[9].iserdes_dq_.iserdesdq_Q7_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[9].iserdes_dq_.iserdesdq_Q8_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[9].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[9].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_slave_ts.oserdes_slave_ts_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_slave_ts.oserdes_slave_ts_OQ_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_slave_ts.oserdes_slave_ts_SHIFTIN1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_slave_ts.oserdes_slave_ts_SHIFTIN2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_slave_ts.oserdes_slave_ts_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_slave_ts.oserdes_slave_ts_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_slave_ts.oserdes_slave_ts_TFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_slave_ts.oserdes_slave_ts_TQ_UNCONNECTED\ : STD_LOGIC;
  attribute BOX_TYPE : string;
  attribute BOX_TYPE of \dqs_gen.oddr_dqs\ : label is "PRIMITIVE";
  attribute \__SRVAL\ : string;
  attribute \__SRVAL\ of \dqs_gen.oddr_dqs\ : label is "FALSE";
  attribute BOX_TYPE of \dqs_gen.oddr_dqsts\ : label is "PRIMITIVE";
  attribute \__SRVAL\ of \dqs_gen.oddr_dqsts\ : label is "TRUE";
  attribute BOX_TYPE of \input_[2].iserdes_dq_.idelay_dq.idelaye2\ : label is "PRIMITIVE";
  attribute IODELAY_GROUP : string;
  attribute IODELAY_GROUP of \input_[2].iserdes_dq_.idelay_dq.idelaye2\ : label is "MIG_IODELAY_MIG0";
  attribute SIM_DELAY_D : integer;
  attribute SIM_DELAY_D of \input_[2].iserdes_dq_.idelay_dq.idelaye2\ : label is 0;
  attribute BOX_TYPE of \input_[2].iserdes_dq_.iserdesdq\ : label is "PRIMITIVE";
  attribute OPT_MODIFIED : string;
  attribute OPT_MODIFIED of \input_[2].iserdes_dq_.iserdesdq\ : label is "MLO";
  attribute BOX_TYPE of \input_[3].iserdes_dq_.idelay_dq.idelaye2\ : label is "PRIMITIVE";
  attribute IODELAY_GROUP of \input_[3].iserdes_dq_.idelay_dq.idelaye2\ : label is "MIG_IODELAY_MIG0";
  attribute SIM_DELAY_D of \input_[3].iserdes_dq_.idelay_dq.idelaye2\ : label is 0;
  attribute BOX_TYPE of \input_[3].iserdes_dq_.iserdesdq\ : label is "PRIMITIVE";
  attribute OPT_MODIFIED of \input_[3].iserdes_dq_.iserdesdq\ : label is "MLO";
  attribute BOX_TYPE of \input_[4].iserdes_dq_.idelay_dq.idelaye2\ : label is "PRIMITIVE";
  attribute IODELAY_GROUP of \input_[4].iserdes_dq_.idelay_dq.idelaye2\ : label is "MIG_IODELAY_MIG0";
  attribute SIM_DELAY_D of \input_[4].iserdes_dq_.idelay_dq.idelaye2\ : label is 0;
  attribute BOX_TYPE of \input_[4].iserdes_dq_.iserdesdq\ : label is "PRIMITIVE";
  attribute OPT_MODIFIED of \input_[4].iserdes_dq_.iserdesdq\ : label is "MLO";
  attribute BOX_TYPE of \input_[5].iserdes_dq_.idelay_dq.idelaye2\ : label is "PRIMITIVE";
  attribute IODELAY_GROUP of \input_[5].iserdes_dq_.idelay_dq.idelaye2\ : label is "MIG_IODELAY_MIG0";
  attribute SIM_DELAY_D of \input_[5].iserdes_dq_.idelay_dq.idelaye2\ : label is 0;
  attribute BOX_TYPE of \input_[5].iserdes_dq_.iserdesdq\ : label is "PRIMITIVE";
  attribute OPT_MODIFIED of \input_[5].iserdes_dq_.iserdesdq\ : label is "MLO";
  attribute BOX_TYPE of \input_[6].iserdes_dq_.idelay_dq.idelaye2\ : label is "PRIMITIVE";
  attribute IODELAY_GROUP of \input_[6].iserdes_dq_.idelay_dq.idelaye2\ : label is "MIG_IODELAY_MIG0";
  attribute SIM_DELAY_D of \input_[6].iserdes_dq_.idelay_dq.idelaye2\ : label is 0;
  attribute BOX_TYPE of \input_[6].iserdes_dq_.iserdesdq\ : label is "PRIMITIVE";
  attribute OPT_MODIFIED of \input_[6].iserdes_dq_.iserdesdq\ : label is "MLO";
  attribute BOX_TYPE of \input_[7].iserdes_dq_.idelay_dq.idelaye2\ : label is "PRIMITIVE";
  attribute IODELAY_GROUP of \input_[7].iserdes_dq_.idelay_dq.idelaye2\ : label is "MIG_IODELAY_MIG0";
  attribute SIM_DELAY_D of \input_[7].iserdes_dq_.idelay_dq.idelaye2\ : label is 0;
  attribute BOX_TYPE of \input_[7].iserdes_dq_.iserdesdq\ : label is "PRIMITIVE";
  attribute OPT_MODIFIED of \input_[7].iserdes_dq_.iserdesdq\ : label is "MLO";
  attribute BOX_TYPE of \input_[8].iserdes_dq_.idelay_dq.idelaye2\ : label is "PRIMITIVE";
  attribute IODELAY_GROUP of \input_[8].iserdes_dq_.idelay_dq.idelaye2\ : label is "MIG_IODELAY_MIG0";
  attribute SIM_DELAY_D of \input_[8].iserdes_dq_.idelay_dq.idelaye2\ : label is 0;
  attribute BOX_TYPE of \input_[8].iserdes_dq_.iserdesdq\ : label is "PRIMITIVE";
  attribute OPT_MODIFIED of \input_[8].iserdes_dq_.iserdesdq\ : label is "MLO";
  attribute BOX_TYPE of \input_[9].iserdes_dq_.idelay_dq.idelaye2\ : label is "PRIMITIVE";
  attribute IODELAY_GROUP of \input_[9].iserdes_dq_.idelay_dq.idelaye2\ : label is "MIG_IODELAY_MIG0";
  attribute SIM_DELAY_D of \input_[9].iserdes_dq_.idelay_dq.idelaye2\ : label is 0;
  attribute BOX_TYPE of \input_[9].iserdes_dq_.iserdesdq\ : label is "PRIMITIVE";
  attribute OPT_MODIFIED of \input_[9].iserdes_dq_.iserdesdq\ : label is "MLO";
  attribute BOX_TYPE of \output_[1].oserdes_dq_.ddr.oserdes_dq_i\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \output_[2].oserdes_dq_.ddr.oserdes_dq_i\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \output_[3].oserdes_dq_.ddr.oserdes_dq_i\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \output_[4].oserdes_dq_.ddr.oserdes_dq_i\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \output_[5].oserdes_dq_.ddr.oserdes_dq_i\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \output_[6].oserdes_dq_.ddr.oserdes_dq_i\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \output_[7].oserdes_dq_.ddr.oserdes_dq_i\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \output_[8].oserdes_dq_.ddr.oserdes_dq_i\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \output_[9].oserdes_dq_.ddr.oserdes_dq_i\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \slave_ts.oserdes_slave_ts\ : label is "PRIMITIVE";
begin
  idelay_ld_rst_5 <= \^idelay_ld_rst_5\;
\dqs_gen.oddr_dqs\: unisim.vcomponents.ODDR
    generic map(
      DDR_CLK_EDGE => "SAME_EDGE",
      INIT => '0',
      IS_C_INVERTED => '0',
      IS_D1_INVERTED => '0',
      IS_D2_INVERTED => '0',
      SRTYPE => "SYNC"
    )
        port map (
      C => oserdes_clk_delayed,
      CE => '1',
      D1 => DQSBUS(0),
      D2 => DQSBUS(1),
      Q => out_dqs_2,
      R => '0',
      S => \NLW_dqs_gen.oddr_dqs_S_UNCONNECTED\
    );
\dqs_gen.oddr_dqsts\: unisim.vcomponents.ODDR
    generic map(
      DDR_CLK_EDGE => "SAME_EDGE",
      INIT => '0',
      IS_C_INVERTED => '0',
      IS_D1_INVERTED => '0',
      IS_D2_INVERTED => '0',
      SRTYPE => "SYNC"
    )
        port map (
      C => oserdes_clk_delayed,
      CE => '1',
      D1 => CTSBUS(0),
      D2 => CTSBUS(0),
      Q => ts_dqs_2,
      R => \NLW_dqs_gen.oddr_dqsts_R_UNCONNECTED\,
      S => '0'
    );
\idelay_ld_rst_i_1__5\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \^idelay_ld_rst_5\,
      I1 => rst_r4,
      O => \idelay_ld_rst_i_1__5_n_0\
    );
idelay_ld_rst_reg: unisim.vcomponents.FDSE
     port map (
      C => idelay_ld_rst_reg_0,
      CE => '1',
      D => \idelay_ld_rst_i_1__5_n_0\,
      Q => \^idelay_ld_rst_5\,
      S => A_rst_primitives
    );
\input_[2].iserdes_dq_.idelay_dq.idelaye2\: unisim.vcomponents.IDELAYE2
    generic map(
      CINVCTRL_SEL => "FALSE",
      DELAY_SRC => "IDATAIN",
      HIGH_PERFORMANCE_MODE => "TRUE",
      IDELAY_TYPE => "VARIABLE",
      IDELAY_VALUE => 0,
      IS_C_INVERTED => '0',
      IS_DATAIN_INVERTED => '0',
      IS_IDATAIN_INVERTED => '0',
      PIPE_SEL => "FALSE",
      REFCLK_FREQUENCY => 200.000000,
      SIGNAL_PATTERN => "DATA"
    )
        port map (
      C => idelay_ld_rst_reg_0,
      CE => \input_[9].iserdes_dq_.iserdesdq_0\,
      CINVCTRL => '0',
      CNTVALUEIN(4 downto 0) => B"00000",
      CNTVALUEOUT(4 downto 0) => \NLW_input_[2].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED\(4 downto 0),
      DATAIN => '0',
      DATAOUT => data_in_dly_2,
      IDATAIN => mem_dq_in(0),
      INC => idelay_inc,
      LD => LD0_12,
      LDPIPEEN => '0',
      REGRST => A_rst_primitives
    );
\input_[2].iserdes_dq_.iserdesdq\: unisim.vcomponents.ISERDESE2
    generic map(
      DATA_RATE => "DDR",
      DATA_WIDTH => 4,
      DYN_CLKDIV_INV_EN => "FALSE",
      DYN_CLK_INV_EN => "FALSE",
      INIT_Q1 => '0',
      INIT_Q2 => '0',
      INIT_Q3 => '0',
      INIT_Q4 => '0',
      INTERFACE_TYPE => "MEMORY_DDR3",
      IOBDELAY => "IFD",
      IS_CLKB_INVERTED => '1',
      IS_CLKDIVP_INVERTED => '0',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D_INVERTED => '0',
      IS_OCLKB_INVERTED => '0',
      IS_OCLK_INVERTED => '0',
      NUM_CE => 2,
      OFB_USED => "FALSE",
      SERDES_MODE => "MASTER",
      SRVAL_Q1 => '0',
      SRVAL_Q2 => '0',
      SRVAL_Q3 => '0',
      SRVAL_Q4 => '0'
    )
        port map (
      BITSLIP => '0',
      CE1 => '1',
      CE2 => '1',
      CLK => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]\,
      CLKB => CLKB0_12,
      CLKDIV => \NLW_input_[2].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED\,
      CLKDIVP => iserdes_clkdiv,
      D => mem_dq_in(0),
      DDLY => data_in_dly_2,
      DYNCLKDIVSEL => '0',
      DYNCLKSEL => '0',
      O => \NLW_input_[2].iserdes_dq_.iserdesdq_O_UNCONNECTED\,
      OCLK => oserdes_clk,
      OCLKB => \NLW_input_[2].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED\,
      OFB => \NLW_input_[2].iserdes_dq_.iserdesdq_OFB_UNCONNECTED\,
      Q1 => D2(3),
      Q2 => D2(2),
      Q3 => D2(1),
      Q4 => D2(0),
      Q5 => \NLW_input_[2].iserdes_dq_.iserdesdq_Q5_UNCONNECTED\,
      Q6 => \NLW_input_[2].iserdes_dq_.iserdesdq_Q6_UNCONNECTED\,
      Q7 => \NLW_input_[2].iserdes_dq_.iserdesdq_Q7_UNCONNECTED\,
      Q8 => \NLW_input_[2].iserdes_dq_.iserdesdq_Q8_UNCONNECTED\,
      RST => '0',
      SHIFTIN1 => '0',
      SHIFTIN2 => '0',
      SHIFTOUT1 => \NLW_input_[2].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_input_[2].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED\
    );
\input_[3].iserdes_dq_.idelay_dq.idelaye2\: unisim.vcomponents.IDELAYE2
    generic map(
      CINVCTRL_SEL => "FALSE",
      DELAY_SRC => "IDATAIN",
      HIGH_PERFORMANCE_MODE => "TRUE",
      IDELAY_TYPE => "VARIABLE",
      IDELAY_VALUE => 0,
      IS_C_INVERTED => '0',
      IS_DATAIN_INVERTED => '0',
      IS_IDATAIN_INVERTED => '0',
      PIPE_SEL => "FALSE",
      REFCLK_FREQUENCY => 200.000000,
      SIGNAL_PATTERN => "DATA"
    )
        port map (
      C => idelay_ld_rst_reg_0,
      CE => \input_[9].iserdes_dq_.iserdesdq_0\,
      CINVCTRL => '0',
      CNTVALUEIN(4 downto 0) => B"00000",
      CNTVALUEOUT(4 downto 0) => \NLW_input_[3].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED\(4 downto 0),
      DATAIN => '0',
      DATAOUT => data_in_dly_3,
      IDATAIN => mem_dq_in(1),
      INC => idelay_inc,
      LD => LD0_12,
      LDPIPEEN => '0',
      REGRST => A_rst_primitives
    );
\input_[3].iserdes_dq_.iserdesdq\: unisim.vcomponents.ISERDESE2
    generic map(
      DATA_RATE => "DDR",
      DATA_WIDTH => 4,
      DYN_CLKDIV_INV_EN => "FALSE",
      DYN_CLK_INV_EN => "FALSE",
      INIT_Q1 => '0',
      INIT_Q2 => '0',
      INIT_Q3 => '0',
      INIT_Q4 => '0',
      INTERFACE_TYPE => "MEMORY_DDR3",
      IOBDELAY => "IFD",
      IS_CLKB_INVERTED => '1',
      IS_CLKDIVP_INVERTED => '0',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D_INVERTED => '0',
      IS_OCLKB_INVERTED => '0',
      IS_OCLK_INVERTED => '0',
      NUM_CE => 2,
      OFB_USED => "FALSE",
      SERDES_MODE => "MASTER",
      SRVAL_Q1 => '0',
      SRVAL_Q2 => '0',
      SRVAL_Q3 => '0',
      SRVAL_Q4 => '0'
    )
        port map (
      BITSLIP => '0',
      CE1 => '1',
      CE2 => '1',
      CLK => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]\,
      CLKB => CLKB0_12,
      CLKDIV => \NLW_input_[3].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED\,
      CLKDIVP => iserdes_clkdiv,
      D => mem_dq_in(1),
      DDLY => data_in_dly_3,
      DYNCLKDIVSEL => '0',
      DYNCLKSEL => '0',
      O => \NLW_input_[3].iserdes_dq_.iserdesdq_O_UNCONNECTED\,
      OCLK => oserdes_clk,
      OCLKB => \NLW_input_[3].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED\,
      OFB => \NLW_input_[3].iserdes_dq_.iserdesdq_OFB_UNCONNECTED\,
      Q1 => D3(3),
      Q2 => D3(2),
      Q3 => D3(1),
      Q4 => D3(0),
      Q5 => \NLW_input_[3].iserdes_dq_.iserdesdq_Q5_UNCONNECTED\,
      Q6 => \NLW_input_[3].iserdes_dq_.iserdesdq_Q6_UNCONNECTED\,
      Q7 => \NLW_input_[3].iserdes_dq_.iserdesdq_Q7_UNCONNECTED\,
      Q8 => \NLW_input_[3].iserdes_dq_.iserdesdq_Q8_UNCONNECTED\,
      RST => '0',
      SHIFTIN1 => '0',
      SHIFTIN2 => '0',
      SHIFTOUT1 => \NLW_input_[3].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_input_[3].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED\
    );
\input_[4].iserdes_dq_.idelay_dq.idelaye2\: unisim.vcomponents.IDELAYE2
    generic map(
      CINVCTRL_SEL => "FALSE",
      DELAY_SRC => "IDATAIN",
      HIGH_PERFORMANCE_MODE => "TRUE",
      IDELAY_TYPE => "VARIABLE",
      IDELAY_VALUE => 0,
      IS_C_INVERTED => '0',
      IS_DATAIN_INVERTED => '0',
      IS_IDATAIN_INVERTED => '0',
      PIPE_SEL => "FALSE",
      REFCLK_FREQUENCY => 200.000000,
      SIGNAL_PATTERN => "DATA"
    )
        port map (
      C => idelay_ld_rst_reg_0,
      CE => \input_[9].iserdes_dq_.iserdesdq_0\,
      CINVCTRL => '0',
      CNTVALUEIN(4 downto 0) => B"00000",
      CNTVALUEOUT(4 downto 0) => \NLW_input_[4].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED\(4 downto 0),
      DATAIN => '0',
      DATAOUT => data_in_dly_4,
      IDATAIN => mem_dq_in(2),
      INC => idelay_inc,
      LD => LD0_12,
      LDPIPEEN => '0',
      REGRST => A_rst_primitives
    );
\input_[4].iserdes_dq_.iserdesdq\: unisim.vcomponents.ISERDESE2
    generic map(
      DATA_RATE => "DDR",
      DATA_WIDTH => 4,
      DYN_CLKDIV_INV_EN => "FALSE",
      DYN_CLK_INV_EN => "FALSE",
      INIT_Q1 => '0',
      INIT_Q2 => '0',
      INIT_Q3 => '0',
      INIT_Q4 => '0',
      INTERFACE_TYPE => "MEMORY_DDR3",
      IOBDELAY => "IFD",
      IS_CLKB_INVERTED => '1',
      IS_CLKDIVP_INVERTED => '0',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D_INVERTED => '0',
      IS_OCLKB_INVERTED => '0',
      IS_OCLK_INVERTED => '0',
      NUM_CE => 2,
      OFB_USED => "FALSE",
      SERDES_MODE => "MASTER",
      SRVAL_Q1 => '0',
      SRVAL_Q2 => '0',
      SRVAL_Q3 => '0',
      SRVAL_Q4 => '0'
    )
        port map (
      BITSLIP => '0',
      CE1 => '1',
      CE2 => '1',
      CLK => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]\,
      CLKB => CLKB0_12,
      CLKDIV => \NLW_input_[4].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED\,
      CLKDIVP => iserdes_clkdiv,
      D => mem_dq_in(2),
      DDLY => data_in_dly_4,
      DYNCLKDIVSEL => '0',
      DYNCLKSEL => '0',
      O => \NLW_input_[4].iserdes_dq_.iserdesdq_O_UNCONNECTED\,
      OCLK => oserdes_clk,
      OCLKB => \NLW_input_[4].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED\,
      OFB => \NLW_input_[4].iserdes_dq_.iserdesdq_OFB_UNCONNECTED\,
      Q1 => D4(3),
      Q2 => D4(2),
      Q3 => D4(1),
      Q4 => D4(0),
      Q5 => \NLW_input_[4].iserdes_dq_.iserdesdq_Q5_UNCONNECTED\,
      Q6 => \NLW_input_[4].iserdes_dq_.iserdesdq_Q6_UNCONNECTED\,
      Q7 => \NLW_input_[4].iserdes_dq_.iserdesdq_Q7_UNCONNECTED\,
      Q8 => \NLW_input_[4].iserdes_dq_.iserdesdq_Q8_UNCONNECTED\,
      RST => '0',
      SHIFTIN1 => '0',
      SHIFTIN2 => '0',
      SHIFTOUT1 => \NLW_input_[4].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_input_[4].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED\
    );
\input_[5].iserdes_dq_.idelay_dq.idelaye2\: unisim.vcomponents.IDELAYE2
    generic map(
      CINVCTRL_SEL => "FALSE",
      DELAY_SRC => "IDATAIN",
      HIGH_PERFORMANCE_MODE => "TRUE",
      IDELAY_TYPE => "VARIABLE",
      IDELAY_VALUE => 0,
      IS_C_INVERTED => '0',
      IS_DATAIN_INVERTED => '0',
      IS_IDATAIN_INVERTED => '0',
      PIPE_SEL => "FALSE",
      REFCLK_FREQUENCY => 200.000000,
      SIGNAL_PATTERN => "DATA"
    )
        port map (
      C => idelay_ld_rst_reg_0,
      CE => \input_[9].iserdes_dq_.iserdesdq_0\,
      CINVCTRL => '0',
      CNTVALUEIN(4 downto 0) => B"00000",
      CNTVALUEOUT(4 downto 0) => \NLW_input_[5].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED\(4 downto 0),
      DATAIN => '0',
      DATAOUT => data_in_dly_5,
      IDATAIN => mem_dq_in(3),
      INC => idelay_inc,
      LD => LD0_12,
      LDPIPEEN => '0',
      REGRST => A_rst_primitives
    );
\input_[5].iserdes_dq_.iserdesdq\: unisim.vcomponents.ISERDESE2
    generic map(
      DATA_RATE => "DDR",
      DATA_WIDTH => 4,
      DYN_CLKDIV_INV_EN => "FALSE",
      DYN_CLK_INV_EN => "FALSE",
      INIT_Q1 => '0',
      INIT_Q2 => '0',
      INIT_Q3 => '0',
      INIT_Q4 => '0',
      INTERFACE_TYPE => "MEMORY_DDR3",
      IOBDELAY => "IFD",
      IS_CLKB_INVERTED => '1',
      IS_CLKDIVP_INVERTED => '0',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D_INVERTED => '0',
      IS_OCLKB_INVERTED => '0',
      IS_OCLK_INVERTED => '0',
      NUM_CE => 2,
      OFB_USED => "FALSE",
      SERDES_MODE => "MASTER",
      SRVAL_Q1 => '0',
      SRVAL_Q2 => '0',
      SRVAL_Q3 => '0',
      SRVAL_Q4 => '0'
    )
        port map (
      BITSLIP => '0',
      CE1 => '1',
      CE2 => '1',
      CLK => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]\,
      CLKB => CLKB0_12,
      CLKDIV => \NLW_input_[5].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED\,
      CLKDIVP => iserdes_clkdiv,
      D => mem_dq_in(3),
      DDLY => data_in_dly_5,
      DYNCLKDIVSEL => '0',
      DYNCLKSEL => '0',
      O => \NLW_input_[5].iserdes_dq_.iserdesdq_O_UNCONNECTED\,
      OCLK => oserdes_clk,
      OCLKB => \NLW_input_[5].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED\,
      OFB => \NLW_input_[5].iserdes_dq_.iserdesdq_OFB_UNCONNECTED\,
      Q1 => D5(3),
      Q2 => D5(2),
      Q3 => D5(1),
      Q4 => D5(0),
      Q5 => \NLW_input_[5].iserdes_dq_.iserdesdq_Q5_UNCONNECTED\,
      Q6 => \NLW_input_[5].iserdes_dq_.iserdesdq_Q6_UNCONNECTED\,
      Q7 => \NLW_input_[5].iserdes_dq_.iserdesdq_Q7_UNCONNECTED\,
      Q8 => \NLW_input_[5].iserdes_dq_.iserdesdq_Q8_UNCONNECTED\,
      RST => '0',
      SHIFTIN1 => '0',
      SHIFTIN2 => '0',
      SHIFTOUT1 => \NLW_input_[5].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_input_[5].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED\
    );
\input_[6].iserdes_dq_.idelay_dq.idelaye2\: unisim.vcomponents.IDELAYE2
    generic map(
      CINVCTRL_SEL => "FALSE",
      DELAY_SRC => "IDATAIN",
      HIGH_PERFORMANCE_MODE => "TRUE",
      IDELAY_TYPE => "VARIABLE",
      IDELAY_VALUE => 0,
      IS_C_INVERTED => '0',
      IS_DATAIN_INVERTED => '0',
      IS_IDATAIN_INVERTED => '0',
      PIPE_SEL => "FALSE",
      REFCLK_FREQUENCY => 200.000000,
      SIGNAL_PATTERN => "DATA"
    )
        port map (
      C => idelay_ld_rst_reg_0,
      CE => \input_[9].iserdes_dq_.iserdesdq_0\,
      CINVCTRL => '0',
      CNTVALUEIN(4 downto 0) => B"00000",
      CNTVALUEOUT(4 downto 0) => \NLW_input_[6].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED\(4 downto 0),
      DATAIN => '0',
      DATAOUT => data_in_dly_6,
      IDATAIN => mem_dq_in(4),
      INC => idelay_inc,
      LD => LD0_12,
      LDPIPEEN => '0',
      REGRST => A_rst_primitives
    );
\input_[6].iserdes_dq_.iserdesdq\: unisim.vcomponents.ISERDESE2
    generic map(
      DATA_RATE => "DDR",
      DATA_WIDTH => 4,
      DYN_CLKDIV_INV_EN => "FALSE",
      DYN_CLK_INV_EN => "FALSE",
      INIT_Q1 => '0',
      INIT_Q2 => '0',
      INIT_Q3 => '0',
      INIT_Q4 => '0',
      INTERFACE_TYPE => "MEMORY_DDR3",
      IOBDELAY => "IFD",
      IS_CLKB_INVERTED => '1',
      IS_CLKDIVP_INVERTED => '0',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D_INVERTED => '0',
      IS_OCLKB_INVERTED => '0',
      IS_OCLK_INVERTED => '0',
      NUM_CE => 2,
      OFB_USED => "FALSE",
      SERDES_MODE => "MASTER",
      SRVAL_Q1 => '0',
      SRVAL_Q2 => '0',
      SRVAL_Q3 => '0',
      SRVAL_Q4 => '0'
    )
        port map (
      BITSLIP => '0',
      CE1 => '1',
      CE2 => '1',
      CLK => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]\,
      CLKB => CLKB0_12,
      CLKDIV => \NLW_input_[6].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED\,
      CLKDIVP => iserdes_clkdiv,
      D => mem_dq_in(4),
      DDLY => data_in_dly_6,
      DYNCLKDIVSEL => '0',
      DYNCLKSEL => '0',
      O => \NLW_input_[6].iserdes_dq_.iserdesdq_O_UNCONNECTED\,
      OCLK => oserdes_clk,
      OCLKB => \NLW_input_[6].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED\,
      OFB => \NLW_input_[6].iserdes_dq_.iserdesdq_OFB_UNCONNECTED\,
      Q1 => D6(3),
      Q2 => D6(2),
      Q3 => D6(1),
      Q4 => D6(0),
      Q5 => \NLW_input_[6].iserdes_dq_.iserdesdq_Q5_UNCONNECTED\,
      Q6 => \NLW_input_[6].iserdes_dq_.iserdesdq_Q6_UNCONNECTED\,
      Q7 => \NLW_input_[6].iserdes_dq_.iserdesdq_Q7_UNCONNECTED\,
      Q8 => \NLW_input_[6].iserdes_dq_.iserdesdq_Q8_UNCONNECTED\,
      RST => '0',
      SHIFTIN1 => '0',
      SHIFTIN2 => '0',
      SHIFTOUT1 => \NLW_input_[6].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_input_[6].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED\
    );
\input_[7].iserdes_dq_.idelay_dq.idelaye2\: unisim.vcomponents.IDELAYE2
    generic map(
      CINVCTRL_SEL => "FALSE",
      DELAY_SRC => "IDATAIN",
      HIGH_PERFORMANCE_MODE => "TRUE",
      IDELAY_TYPE => "VARIABLE",
      IDELAY_VALUE => 0,
      IS_C_INVERTED => '0',
      IS_DATAIN_INVERTED => '0',
      IS_IDATAIN_INVERTED => '0',
      PIPE_SEL => "FALSE",
      REFCLK_FREQUENCY => 200.000000,
      SIGNAL_PATTERN => "DATA"
    )
        port map (
      C => idelay_ld_rst_reg_0,
      CE => \input_[9].iserdes_dq_.iserdesdq_0\,
      CINVCTRL => '0',
      CNTVALUEIN(4 downto 0) => B"00000",
      CNTVALUEOUT(4 downto 0) => \NLW_input_[7].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED\(4 downto 0),
      DATAIN => '0',
      DATAOUT => data_in_dly_7,
      IDATAIN => mem_dq_in(5),
      INC => idelay_inc,
      LD => LD0_12,
      LDPIPEEN => '0',
      REGRST => A_rst_primitives
    );
\input_[7].iserdes_dq_.iserdesdq\: unisim.vcomponents.ISERDESE2
    generic map(
      DATA_RATE => "DDR",
      DATA_WIDTH => 4,
      DYN_CLKDIV_INV_EN => "FALSE",
      DYN_CLK_INV_EN => "FALSE",
      INIT_Q1 => '0',
      INIT_Q2 => '0',
      INIT_Q3 => '0',
      INIT_Q4 => '0',
      INTERFACE_TYPE => "MEMORY_DDR3",
      IOBDELAY => "IFD",
      IS_CLKB_INVERTED => '1',
      IS_CLKDIVP_INVERTED => '0',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D_INVERTED => '0',
      IS_OCLKB_INVERTED => '0',
      IS_OCLK_INVERTED => '0',
      NUM_CE => 2,
      OFB_USED => "FALSE",
      SERDES_MODE => "MASTER",
      SRVAL_Q1 => '0',
      SRVAL_Q2 => '0',
      SRVAL_Q3 => '0',
      SRVAL_Q4 => '0'
    )
        port map (
      BITSLIP => '0',
      CE1 => '1',
      CE2 => '1',
      CLK => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]\,
      CLKB => CLKB0_12,
      CLKDIV => \NLW_input_[7].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED\,
      CLKDIVP => iserdes_clkdiv,
      D => mem_dq_in(5),
      DDLY => data_in_dly_7,
      DYNCLKDIVSEL => '0',
      DYNCLKSEL => '0',
      O => \NLW_input_[7].iserdes_dq_.iserdesdq_O_UNCONNECTED\,
      OCLK => oserdes_clk,
      OCLKB => \NLW_input_[7].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED\,
      OFB => \NLW_input_[7].iserdes_dq_.iserdesdq_OFB_UNCONNECTED\,
      Q1 => D7(3),
      Q2 => D7(2),
      Q3 => D7(1),
      Q4 => D7(0),
      Q5 => \NLW_input_[7].iserdes_dq_.iserdesdq_Q5_UNCONNECTED\,
      Q6 => \NLW_input_[7].iserdes_dq_.iserdesdq_Q6_UNCONNECTED\,
      Q7 => \NLW_input_[7].iserdes_dq_.iserdesdq_Q7_UNCONNECTED\,
      Q8 => \NLW_input_[7].iserdes_dq_.iserdesdq_Q8_UNCONNECTED\,
      RST => '0',
      SHIFTIN1 => '0',
      SHIFTIN2 => '0',
      SHIFTOUT1 => \NLW_input_[7].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_input_[7].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED\
    );
\input_[8].iserdes_dq_.idelay_dq.idelaye2\: unisim.vcomponents.IDELAYE2
    generic map(
      CINVCTRL_SEL => "FALSE",
      DELAY_SRC => "IDATAIN",
      HIGH_PERFORMANCE_MODE => "TRUE",
      IDELAY_TYPE => "VARIABLE",
      IDELAY_VALUE => 0,
      IS_C_INVERTED => '0',
      IS_DATAIN_INVERTED => '0',
      IS_IDATAIN_INVERTED => '0',
      PIPE_SEL => "FALSE",
      REFCLK_FREQUENCY => 200.000000,
      SIGNAL_PATTERN => "DATA"
    )
        port map (
      C => idelay_ld_rst_reg_0,
      CE => \input_[9].iserdes_dq_.iserdesdq_0\,
      CINVCTRL => '0',
      CNTVALUEIN(4 downto 0) => B"00000",
      CNTVALUEOUT(4 downto 0) => \NLW_input_[8].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED\(4 downto 0),
      DATAIN => '0',
      DATAOUT => data_in_dly_8,
      IDATAIN => mem_dq_in(6),
      INC => idelay_inc,
      LD => LD0_12,
      LDPIPEEN => '0',
      REGRST => A_rst_primitives
    );
\input_[8].iserdes_dq_.iserdesdq\: unisim.vcomponents.ISERDESE2
    generic map(
      DATA_RATE => "DDR",
      DATA_WIDTH => 4,
      DYN_CLKDIV_INV_EN => "FALSE",
      DYN_CLK_INV_EN => "FALSE",
      INIT_Q1 => '0',
      INIT_Q2 => '0',
      INIT_Q3 => '0',
      INIT_Q4 => '0',
      INTERFACE_TYPE => "MEMORY_DDR3",
      IOBDELAY => "IFD",
      IS_CLKB_INVERTED => '1',
      IS_CLKDIVP_INVERTED => '0',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D_INVERTED => '0',
      IS_OCLKB_INVERTED => '0',
      IS_OCLK_INVERTED => '0',
      NUM_CE => 2,
      OFB_USED => "FALSE",
      SERDES_MODE => "MASTER",
      SRVAL_Q1 => '0',
      SRVAL_Q2 => '0',
      SRVAL_Q3 => '0',
      SRVAL_Q4 => '0'
    )
        port map (
      BITSLIP => '0',
      CE1 => '1',
      CE2 => '1',
      CLK => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]\,
      CLKB => CLKB0_12,
      CLKDIV => \NLW_input_[8].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED\,
      CLKDIVP => iserdes_clkdiv,
      D => mem_dq_in(6),
      DDLY => data_in_dly_8,
      DYNCLKDIVSEL => '0',
      DYNCLKSEL => '0',
      O => \NLW_input_[8].iserdes_dq_.iserdesdq_O_UNCONNECTED\,
      OCLK => oserdes_clk,
      OCLKB => \NLW_input_[8].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED\,
      OFB => \NLW_input_[8].iserdes_dq_.iserdesdq_OFB_UNCONNECTED\,
      Q1 => D8(3),
      Q2 => D8(2),
      Q3 => D8(1),
      Q4 => D8(0),
      Q5 => \NLW_input_[8].iserdes_dq_.iserdesdq_Q5_UNCONNECTED\,
      Q6 => \NLW_input_[8].iserdes_dq_.iserdesdq_Q6_UNCONNECTED\,
      Q7 => \NLW_input_[8].iserdes_dq_.iserdesdq_Q7_UNCONNECTED\,
      Q8 => \NLW_input_[8].iserdes_dq_.iserdesdq_Q8_UNCONNECTED\,
      RST => '0',
      SHIFTIN1 => '0',
      SHIFTIN2 => '0',
      SHIFTOUT1 => \NLW_input_[8].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_input_[8].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED\
    );
\input_[9].iserdes_dq_.idelay_dq.idelaye2\: unisim.vcomponents.IDELAYE2
    generic map(
      CINVCTRL_SEL => "FALSE",
      DELAY_SRC => "IDATAIN",
      HIGH_PERFORMANCE_MODE => "TRUE",
      IDELAY_TYPE => "VARIABLE",
      IDELAY_VALUE => 0,
      IS_C_INVERTED => '0',
      IS_DATAIN_INVERTED => '0',
      IS_IDATAIN_INVERTED => '0',
      PIPE_SEL => "FALSE",
      REFCLK_FREQUENCY => 200.000000,
      SIGNAL_PATTERN => "DATA"
    )
        port map (
      C => idelay_ld_rst_reg_0,
      CE => \input_[9].iserdes_dq_.iserdesdq_0\,
      CINVCTRL => '0',
      CNTVALUEIN(4 downto 0) => B"00000",
      CNTVALUEOUT(4 downto 0) => \NLW_input_[9].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED\(4 downto 0),
      DATAIN => '0',
      DATAOUT => data_in_dly_9,
      IDATAIN => mem_dq_in(7),
      INC => idelay_inc,
      LD => LD0_12,
      LDPIPEEN => '0',
      REGRST => A_rst_primitives
    );
\input_[9].iserdes_dq_.iserdesdq\: unisim.vcomponents.ISERDESE2
    generic map(
      DATA_RATE => "DDR",
      DATA_WIDTH => 4,
      DYN_CLKDIV_INV_EN => "FALSE",
      DYN_CLK_INV_EN => "FALSE",
      INIT_Q1 => '0',
      INIT_Q2 => '0',
      INIT_Q3 => '0',
      INIT_Q4 => '0',
      INTERFACE_TYPE => "MEMORY_DDR3",
      IOBDELAY => "IFD",
      IS_CLKB_INVERTED => '1',
      IS_CLKDIVP_INVERTED => '0',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D_INVERTED => '0',
      IS_OCLKB_INVERTED => '0',
      IS_OCLK_INVERTED => '0',
      NUM_CE => 2,
      OFB_USED => "FALSE",
      SERDES_MODE => "MASTER",
      SRVAL_Q1 => '0',
      SRVAL_Q2 => '0',
      SRVAL_Q3 => '0',
      SRVAL_Q4 => '0'
    )
        port map (
      BITSLIP => '0',
      CE1 => '1',
      CE2 => '1',
      CLK => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]\,
      CLKB => CLKB0_12,
      CLKDIV => \NLW_input_[9].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED\,
      CLKDIVP => iserdes_clkdiv,
      D => mem_dq_in(7),
      DDLY => data_in_dly_9,
      DYNCLKDIVSEL => '0',
      DYNCLKSEL => '0',
      O => \NLW_input_[9].iserdes_dq_.iserdesdq_O_UNCONNECTED\,
      OCLK => oserdes_clk,
      OCLKB => \NLW_input_[9].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED\,
      OFB => \NLW_input_[9].iserdes_dq_.iserdesdq_OFB_UNCONNECTED\,
      Q1 => D9(3),
      Q2 => D9(2),
      Q3 => D9(1),
      Q4 => D9(0),
      Q5 => \NLW_input_[9].iserdes_dq_.iserdesdq_Q5_UNCONNECTED\,
      Q6 => \NLW_input_[9].iserdes_dq_.iserdesdq_Q6_UNCONNECTED\,
      Q7 => \NLW_input_[9].iserdes_dq_.iserdesdq_Q7_UNCONNECTED\,
      Q8 => \NLW_input_[9].iserdes_dq_.iserdesdq_Q8_UNCONNECTED\,
      RST => '0',
      SHIFTIN1 => '0',
      SHIFTIN2 => '0',
      SHIFTOUT1 => \NLW_input_[9].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_input_[9].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED\
    );
\output_[1].oserdes_dq_.ddr.oserdes_dq_i\: unisim.vcomponents.OSERDESE2
    generic map(
      DATA_RATE_OQ => "DDR",
      DATA_RATE_TQ => "DDR",
      DATA_WIDTH => 4,
      INIT_OQ => '1',
      INIT_TQ => '1',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D1_INVERTED => '0',
      IS_D2_INVERTED => '0',
      IS_D3_INVERTED => '0',
      IS_D4_INVERTED => '0',
      IS_D5_INVERTED => '0',
      IS_D6_INVERTED => '0',
      IS_D7_INVERTED => '0',
      IS_D8_INVERTED => '0',
      IS_T1_INVERTED => '0',
      IS_T2_INVERTED => '0',
      IS_T3_INVERTED => '0',
      IS_T4_INVERTED => '0',
      SERDES_MODE => "MASTER",
      SRVAL_OQ => '1',
      SRVAL_TQ => '1',
      TBYTE_CTL => "TRUE",
      TBYTE_SRC => "FALSE",
      TRISTATE_WIDTH => 4
    )
        port map (
      CLK => oserdes_clk,
      CLKDIV => oserdes_clkdiv,
      D1 => of_dqbus(0),
      D2 => of_dqbus(1),
      D3 => of_dqbus(2),
      D4 => of_dqbus(3),
      D5 => '0',
      D6 => '0',
      D7 => '0',
      D8 => '0',
      OCE => '1',
      OFB => \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\,
      OQ => mem_dq_out(0),
      RST => po_oserdes_rst,
      SHIFTIN1 => \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\,
      SHIFTIN2 => \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\,
      SHIFTOUT1 => \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\,
      T1 => '0',
      T2 => '0',
      T3 => '0',
      T4 => '0',
      TBYTEIN => tbyte_out,
      TBYTEOUT => \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\,
      TCE => '1',
      TFB => \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\,
      TQ => mem_dq_ts(0)
    );
\output_[2].oserdes_dq_.ddr.oserdes_dq_i\: unisim.vcomponents.OSERDESE2
    generic map(
      DATA_RATE_OQ => "DDR",
      DATA_RATE_TQ => "DDR",
      DATA_WIDTH => 4,
      INIT_OQ => '1',
      INIT_TQ => '1',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D1_INVERTED => '0',
      IS_D2_INVERTED => '0',
      IS_D3_INVERTED => '0',
      IS_D4_INVERTED => '0',
      IS_D5_INVERTED => '0',
      IS_D6_INVERTED => '0',
      IS_D7_INVERTED => '0',
      IS_D8_INVERTED => '0',
      IS_T1_INVERTED => '0',
      IS_T2_INVERTED => '0',
      IS_T3_INVERTED => '0',
      IS_T4_INVERTED => '0',
      SERDES_MODE => "MASTER",
      SRVAL_OQ => '1',
      SRVAL_TQ => '1',
      TBYTE_CTL => "TRUE",
      TBYTE_SRC => "FALSE",
      TRISTATE_WIDTH => 4
    )
        port map (
      CLK => oserdes_clk,
      CLKDIV => oserdes_clkdiv,
      D1 => of_dqbus(4),
      D2 => of_dqbus(5),
      D3 => of_dqbus(6),
      D4 => of_dqbus(7),
      D5 => '0',
      D6 => '0',
      D7 => '0',
      D8 => '0',
      OCE => '1',
      OFB => \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\,
      OQ => mem_dq_out(1),
      RST => po_oserdes_rst,
      SHIFTIN1 => \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\,
      SHIFTIN2 => \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\,
      SHIFTOUT1 => \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\,
      T1 => '0',
      T2 => '0',
      T3 => '0',
      T4 => '0',
      TBYTEIN => tbyte_out,
      TBYTEOUT => \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\,
      TCE => '1',
      TFB => \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\,
      TQ => mem_dq_ts(1)
    );
\output_[3].oserdes_dq_.ddr.oserdes_dq_i\: unisim.vcomponents.OSERDESE2
    generic map(
      DATA_RATE_OQ => "DDR",
      DATA_RATE_TQ => "DDR",
      DATA_WIDTH => 4,
      INIT_OQ => '1',
      INIT_TQ => '1',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D1_INVERTED => '0',
      IS_D2_INVERTED => '0',
      IS_D3_INVERTED => '0',
      IS_D4_INVERTED => '0',
      IS_D5_INVERTED => '0',
      IS_D6_INVERTED => '0',
      IS_D7_INVERTED => '0',
      IS_D8_INVERTED => '0',
      IS_T1_INVERTED => '0',
      IS_T2_INVERTED => '0',
      IS_T3_INVERTED => '0',
      IS_T4_INVERTED => '0',
      SERDES_MODE => "MASTER",
      SRVAL_OQ => '1',
      SRVAL_TQ => '1',
      TBYTE_CTL => "TRUE",
      TBYTE_SRC => "FALSE",
      TRISTATE_WIDTH => 4
    )
        port map (
      CLK => oserdes_clk,
      CLKDIV => oserdes_clkdiv,
      D1 => of_dqbus(8),
      D2 => of_dqbus(9),
      D3 => of_dqbus(10),
      D4 => of_dqbus(11),
      D5 => '0',
      D6 => '0',
      D7 => '0',
      D8 => '0',
      OCE => '1',
      OFB => \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\,
      OQ => mem_dq_out(2),
      RST => po_oserdes_rst,
      SHIFTIN1 => \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\,
      SHIFTIN2 => \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\,
      SHIFTOUT1 => \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\,
      T1 => '0',
      T2 => '0',
      T3 => '0',
      T4 => '0',
      TBYTEIN => tbyte_out,
      TBYTEOUT => \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\,
      TCE => '1',
      TFB => \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\,
      TQ => mem_dq_ts(2)
    );
\output_[4].oserdes_dq_.ddr.oserdes_dq_i\: unisim.vcomponents.OSERDESE2
    generic map(
      DATA_RATE_OQ => "DDR",
      DATA_RATE_TQ => "DDR",
      DATA_WIDTH => 4,
      INIT_OQ => '1',
      INIT_TQ => '1',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D1_INVERTED => '0',
      IS_D2_INVERTED => '0',
      IS_D3_INVERTED => '0',
      IS_D4_INVERTED => '0',
      IS_D5_INVERTED => '0',
      IS_D6_INVERTED => '0',
      IS_D7_INVERTED => '0',
      IS_D8_INVERTED => '0',
      IS_T1_INVERTED => '0',
      IS_T2_INVERTED => '0',
      IS_T3_INVERTED => '0',
      IS_T4_INVERTED => '0',
      SERDES_MODE => "MASTER",
      SRVAL_OQ => '1',
      SRVAL_TQ => '1',
      TBYTE_CTL => "TRUE",
      TBYTE_SRC => "FALSE",
      TRISTATE_WIDTH => 4
    )
        port map (
      CLK => oserdes_clk,
      CLKDIV => oserdes_clkdiv,
      D1 => of_dqbus(12),
      D2 => of_dqbus(13),
      D3 => of_dqbus(14),
      D4 => of_dqbus(15),
      D5 => '0',
      D6 => '0',
      D7 => '0',
      D8 => '0',
      OCE => '1',
      OFB => \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\,
      OQ => mem_dq_out(3),
      RST => po_oserdes_rst,
      SHIFTIN1 => \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\,
      SHIFTIN2 => \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\,
      SHIFTOUT1 => \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\,
      T1 => '0',
      T2 => '0',
      T3 => '0',
      T4 => '0',
      TBYTEIN => tbyte_out,
      TBYTEOUT => \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\,
      TCE => '1',
      TFB => \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\,
      TQ => mem_dq_ts(3)
    );
\output_[5].oserdes_dq_.ddr.oserdes_dq_i\: unisim.vcomponents.OSERDESE2
    generic map(
      DATA_RATE_OQ => "DDR",
      DATA_RATE_TQ => "DDR",
      DATA_WIDTH => 4,
      INIT_OQ => '1',
      INIT_TQ => '1',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D1_INVERTED => '0',
      IS_D2_INVERTED => '0',
      IS_D3_INVERTED => '0',
      IS_D4_INVERTED => '0',
      IS_D5_INVERTED => '0',
      IS_D6_INVERTED => '0',
      IS_D7_INVERTED => '0',
      IS_D8_INVERTED => '0',
      IS_T1_INVERTED => '0',
      IS_T2_INVERTED => '0',
      IS_T3_INVERTED => '0',
      IS_T4_INVERTED => '0',
      SERDES_MODE => "MASTER",
      SRVAL_OQ => '1',
      SRVAL_TQ => '1',
      TBYTE_CTL => "TRUE",
      TBYTE_SRC => "FALSE",
      TRISTATE_WIDTH => 4
    )
        port map (
      CLK => oserdes_clk,
      CLKDIV => oserdes_clkdiv,
      D1 => of_dqbus(16),
      D2 => of_dqbus(17),
      D3 => of_dqbus(18),
      D4 => of_dqbus(19),
      D5 => '0',
      D6 => '0',
      D7 => '0',
      D8 => '0',
      OCE => '1',
      OFB => \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\,
      OQ => mem_dq_out(4),
      RST => po_oserdes_rst,
      SHIFTIN1 => \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\,
      SHIFTIN2 => \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\,
      SHIFTOUT1 => \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\,
      T1 => '0',
      T2 => '0',
      T3 => '0',
      T4 => '0',
      TBYTEIN => tbyte_out,
      TBYTEOUT => \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\,
      TCE => '1',
      TFB => \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\,
      TQ => mem_dq_ts(4)
    );
\output_[6].oserdes_dq_.ddr.oserdes_dq_i\: unisim.vcomponents.OSERDESE2
    generic map(
      DATA_RATE_OQ => "DDR",
      DATA_RATE_TQ => "DDR",
      DATA_WIDTH => 4,
      INIT_OQ => '1',
      INIT_TQ => '1',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D1_INVERTED => '0',
      IS_D2_INVERTED => '0',
      IS_D3_INVERTED => '0',
      IS_D4_INVERTED => '0',
      IS_D5_INVERTED => '0',
      IS_D6_INVERTED => '0',
      IS_D7_INVERTED => '0',
      IS_D8_INVERTED => '0',
      IS_T1_INVERTED => '0',
      IS_T2_INVERTED => '0',
      IS_T3_INVERTED => '0',
      IS_T4_INVERTED => '0',
      SERDES_MODE => "MASTER",
      SRVAL_OQ => '1',
      SRVAL_TQ => '1',
      TBYTE_CTL => "TRUE",
      TBYTE_SRC => "FALSE",
      TRISTATE_WIDTH => 4
    )
        port map (
      CLK => oserdes_clk,
      CLKDIV => oserdes_clkdiv,
      D1 => of_dqbus(20),
      D2 => of_dqbus(21),
      D3 => of_dqbus(22),
      D4 => of_dqbus(23),
      D5 => '0',
      D6 => '0',
      D7 => '0',
      D8 => '0',
      OCE => '1',
      OFB => \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\,
      OQ => mem_dq_out(5),
      RST => po_oserdes_rst,
      SHIFTIN1 => \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\,
      SHIFTIN2 => \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\,
      SHIFTOUT1 => \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\,
      T1 => '0',
      T2 => '0',
      T3 => '0',
      T4 => '0',
      TBYTEIN => tbyte_out,
      TBYTEOUT => \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\,
      TCE => '1',
      TFB => \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\,
      TQ => mem_dq_ts(5)
    );
\output_[7].oserdes_dq_.ddr.oserdes_dq_i\: unisim.vcomponents.OSERDESE2
    generic map(
      DATA_RATE_OQ => "DDR",
      DATA_RATE_TQ => "DDR",
      DATA_WIDTH => 4,
      INIT_OQ => '1',
      INIT_TQ => '1',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D1_INVERTED => '0',
      IS_D2_INVERTED => '0',
      IS_D3_INVERTED => '0',
      IS_D4_INVERTED => '0',
      IS_D5_INVERTED => '0',
      IS_D6_INVERTED => '0',
      IS_D7_INVERTED => '0',
      IS_D8_INVERTED => '0',
      IS_T1_INVERTED => '0',
      IS_T2_INVERTED => '0',
      IS_T3_INVERTED => '0',
      IS_T4_INVERTED => '0',
      SERDES_MODE => "MASTER",
      SRVAL_OQ => '1',
      SRVAL_TQ => '1',
      TBYTE_CTL => "TRUE",
      TBYTE_SRC => "FALSE",
      TRISTATE_WIDTH => 4
    )
        port map (
      CLK => oserdes_clk,
      CLKDIV => oserdes_clkdiv,
      D1 => of_dqbus(24),
      D2 => of_dqbus(25),
      D3 => of_dqbus(26),
      D4 => of_dqbus(27),
      D5 => '0',
      D6 => '0',
      D7 => '0',
      D8 => '0',
      OCE => '1',
      OFB => \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\,
      OQ => mem_dq_out(6),
      RST => po_oserdes_rst,
      SHIFTIN1 => \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\,
      SHIFTIN2 => \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\,
      SHIFTOUT1 => \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\,
      T1 => '0',
      T2 => '0',
      T3 => '0',
      T4 => '0',
      TBYTEIN => tbyte_out,
      TBYTEOUT => \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\,
      TCE => '1',
      TFB => \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\,
      TQ => mem_dq_ts(6)
    );
\output_[8].oserdes_dq_.ddr.oserdes_dq_i\: unisim.vcomponents.OSERDESE2
    generic map(
      DATA_RATE_OQ => "DDR",
      DATA_RATE_TQ => "DDR",
      DATA_WIDTH => 4,
      INIT_OQ => '1',
      INIT_TQ => '1',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D1_INVERTED => '0',
      IS_D2_INVERTED => '0',
      IS_D3_INVERTED => '0',
      IS_D4_INVERTED => '0',
      IS_D5_INVERTED => '0',
      IS_D6_INVERTED => '0',
      IS_D7_INVERTED => '0',
      IS_D8_INVERTED => '0',
      IS_T1_INVERTED => '0',
      IS_T2_INVERTED => '0',
      IS_T3_INVERTED => '0',
      IS_T4_INVERTED => '0',
      SERDES_MODE => "MASTER",
      SRVAL_OQ => '1',
      SRVAL_TQ => '1',
      TBYTE_CTL => "TRUE",
      TBYTE_SRC => "FALSE",
      TRISTATE_WIDTH => 4
    )
        port map (
      CLK => oserdes_clk,
      CLKDIV => oserdes_clkdiv,
      D1 => of_dqbus(28),
      D2 => of_dqbus(29),
      D3 => of_dqbus(30),
      D4 => of_dqbus(31),
      D5 => '0',
      D6 => '0',
      D7 => '0',
      D8 => '0',
      OCE => '1',
      OFB => \NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\,
      OQ => mem_dq_out(7),
      RST => po_oserdes_rst,
      SHIFTIN1 => \NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\,
      SHIFTIN2 => \NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\,
      SHIFTOUT1 => \NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\,
      T1 => '0',
      T2 => '0',
      T3 => '0',
      T4 => '0',
      TBYTEIN => tbyte_out,
      TBYTEOUT => \NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\,
      TCE => '1',
      TFB => \NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\,
      TQ => mem_dq_ts(7)
    );
\output_[9].oserdes_dq_.ddr.oserdes_dq_i\: unisim.vcomponents.OSERDESE2
    generic map(
      DATA_RATE_OQ => "DDR",
      DATA_RATE_TQ => "DDR",
      DATA_WIDTH => 4,
      INIT_OQ => '1',
      INIT_TQ => '1',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D1_INVERTED => '0',
      IS_D2_INVERTED => '0',
      IS_D3_INVERTED => '0',
      IS_D4_INVERTED => '0',
      IS_D5_INVERTED => '0',
      IS_D6_INVERTED => '0',
      IS_D7_INVERTED => '0',
      IS_D8_INVERTED => '0',
      IS_T1_INVERTED => '0',
      IS_T2_INVERTED => '0',
      IS_T3_INVERTED => '0',
      IS_T4_INVERTED => '0',
      SERDES_MODE => "MASTER",
      SRVAL_OQ => '1',
      SRVAL_TQ => '1',
      TBYTE_CTL => "TRUE",
      TBYTE_SRC => "FALSE",
      TRISTATE_WIDTH => 4
    )
        port map (
      CLK => oserdes_clk,
      CLKDIV => oserdes_clkdiv,
      D1 => of_dqbus(32),
      D2 => of_dqbus(33),
      D3 => of_dqbus(34),
      D4 => of_dqbus(35),
      D5 => '0',
      D6 => '0',
      D7 => '0',
      D8 => '0',
      OCE => '1',
      OFB => \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\,
      OQ => mem_dq_out(8),
      RST => po_oserdes_rst,
      SHIFTIN1 => \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\,
      SHIFTIN2 => \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\,
      SHIFTOUT1 => \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\,
      T1 => '0',
      T2 => '0',
      T3 => '0',
      T4 => '0',
      TBYTEIN => tbyte_out,
      TBYTEOUT => \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\,
      TCE => '1',
      TFB => \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\,
      TQ => mem_dq_ts(8)
    );
\slave_ts.oserdes_slave_ts\: unisim.vcomponents.OSERDESE2
    generic map(
      DATA_RATE_OQ => "DDR",
      DATA_RATE_TQ => "DDR",
      DATA_WIDTH => 4,
      INIT_OQ => '1',
      INIT_TQ => '1',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D1_INVERTED => '0',
      IS_D2_INVERTED => '0',
      IS_D3_INVERTED => '0',
      IS_D4_INVERTED => '0',
      IS_D5_INVERTED => '0',
      IS_D6_INVERTED => '0',
      IS_D7_INVERTED => '0',
      IS_D8_INVERTED => '0',
      IS_T1_INVERTED => '0',
      IS_T2_INVERTED => '0',
      IS_T3_INVERTED => '0',
      IS_T4_INVERTED => '0',
      SERDES_MODE => "MASTER",
      SRVAL_OQ => '1',
      SRVAL_TQ => '1',
      TBYTE_CTL => "TRUE",
      TBYTE_SRC => "TRUE",
      TRISTATE_WIDTH => 4
    )
        port map (
      CLK => oserdes_clk,
      CLKDIV => oserdes_clkdiv,
      D1 => '0',
      D2 => '0',
      D3 => '0',
      D4 => '0',
      D5 => '0',
      D6 => '0',
      D7 => '0',
      D8 => '0',
      OCE => '1',
      OFB => \NLW_slave_ts.oserdes_slave_ts_OFB_UNCONNECTED\,
      OQ => \NLW_slave_ts.oserdes_slave_ts_OQ_UNCONNECTED\,
      RST => po_oserdes_rst,
      SHIFTIN1 => \NLW_slave_ts.oserdes_slave_ts_SHIFTIN1_UNCONNECTED\,
      SHIFTIN2 => \NLW_slave_ts.oserdes_slave_ts_SHIFTIN2_UNCONNECTED\,
      SHIFTOUT1 => \NLW_slave_ts.oserdes_slave_ts_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_slave_ts.oserdes_slave_ts_SHIFTOUT2_UNCONNECTED\,
      T1 => DTSBUS(0),
      T2 => DTSBUS(0),
      T3 => DTSBUS(1),
      T4 => DTSBUS(1),
      TBYTEIN => tbyte_out,
      TBYTEOUT => tbyte_out,
      TCE => '1',
      TFB => \NLW_slave_ts.oserdes_slave_ts_TFB_UNCONNECTED\,
      TQ => \NLW_slave_ts.oserdes_slave_ts_TQ_UNCONNECTED\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \mig_mig_7series_v4_2_ddr_byte_group_io__parameterized0_17\ is
  port (
    out_dqs_1 : out STD_LOGIC;
    ts_dqs_1 : out STD_LOGIC;
    D2 : out STD_LOGIC_VECTOR ( 3 downto 0 );
    D3 : out STD_LOGIC_VECTOR ( 3 downto 0 );
    D4 : out STD_LOGIC_VECTOR ( 3 downto 0 );
    D5 : out STD_LOGIC_VECTOR ( 3 downto 0 );
    D6 : out STD_LOGIC_VECTOR ( 3 downto 0 );
    D7 : out STD_LOGIC_VECTOR ( 3 downto 0 );
    D8 : out STD_LOGIC_VECTOR ( 3 downto 0 );
    D9 : out STD_LOGIC_VECTOR ( 3 downto 0 );
    mem_dq_out : out STD_LOGIC_VECTOR ( 8 downto 0 );
    mem_dq_ts : out STD_LOGIC_VECTOR ( 8 downto 0 );
    idelay_ld_rst_4 : out STD_LOGIC;
    oserdes_clk : in STD_LOGIC;
    oserdes_clkdiv : in STD_LOGIC;
    po_oserdes_rst : in STD_LOGIC;
    DTSBUS : in STD_LOGIC_VECTOR ( 1 downto 0 );
    oserdes_clk_delayed : in STD_LOGIC;
    DQSBUS : in STD_LOGIC_VECTOR ( 1 downto 0 );
    CTSBUS : in STD_LOGIC_VECTOR ( 0 to 0 );
    idelay_ld_rst_reg_0 : in STD_LOGIC;
    \input_[9].iserdes_dq_.iserdesdq_0\ : in STD_LOGIC;
    mem_dq_in : in STD_LOGIC_VECTOR ( 7 downto 0 );
    idelay_inc : in STD_LOGIC;
    LD0_11 : in STD_LOGIC;
    A_rst_primitives : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]\ : in STD_LOGIC;
    CLKB0_11 : in STD_LOGIC;
    iserdes_clkdiv : in STD_LOGIC;
    of_dqbus : in STD_LOGIC_VECTOR ( 35 downto 0 );
    rst_r4 : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \mig_mig_7series_v4_2_ddr_byte_group_io__parameterized0_17\ : entity is "mig_7series_v4_2_ddr_byte_group_io";
end \mig_mig_7series_v4_2_ddr_byte_group_io__parameterized0_17\;

architecture STRUCTURE of \mig_mig_7series_v4_2_ddr_byte_group_io__parameterized0_17\ is
  signal data_in_dly_2 : STD_LOGIC;
  signal data_in_dly_3 : STD_LOGIC;
  signal data_in_dly_4 : STD_LOGIC;
  signal data_in_dly_5 : STD_LOGIC;
  signal data_in_dly_6 : STD_LOGIC;
  signal data_in_dly_7 : STD_LOGIC;
  signal data_in_dly_8 : STD_LOGIC;
  signal data_in_dly_9 : STD_LOGIC;
  signal \^idelay_ld_rst_4\ : STD_LOGIC;
  signal \idelay_ld_rst_i_1__4_n_0\ : STD_LOGIC;
  signal tbyte_out : STD_LOGIC;
  signal \NLW_dqs_gen.oddr_dqs_S_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_dqs_gen.oddr_dqsts_R_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[2].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal \NLW_input_[2].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[2].iserdes_dq_.iserdesdq_O_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[2].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[2].iserdes_dq_.iserdesdq_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[2].iserdes_dq_.iserdesdq_Q5_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[2].iserdes_dq_.iserdesdq_Q6_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[2].iserdes_dq_.iserdesdq_Q7_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[2].iserdes_dq_.iserdesdq_Q8_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[2].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[2].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[3].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal \NLW_input_[3].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[3].iserdes_dq_.iserdesdq_O_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[3].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[3].iserdes_dq_.iserdesdq_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[3].iserdes_dq_.iserdesdq_Q5_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[3].iserdes_dq_.iserdesdq_Q6_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[3].iserdes_dq_.iserdesdq_Q7_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[3].iserdes_dq_.iserdesdq_Q8_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[3].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[3].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[4].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal \NLW_input_[4].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[4].iserdes_dq_.iserdesdq_O_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[4].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[4].iserdes_dq_.iserdesdq_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[4].iserdes_dq_.iserdesdq_Q5_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[4].iserdes_dq_.iserdesdq_Q6_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[4].iserdes_dq_.iserdesdq_Q7_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[4].iserdes_dq_.iserdesdq_Q8_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[4].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[4].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[5].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal \NLW_input_[5].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[5].iserdes_dq_.iserdesdq_O_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[5].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[5].iserdes_dq_.iserdesdq_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[5].iserdes_dq_.iserdesdq_Q5_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[5].iserdes_dq_.iserdesdq_Q6_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[5].iserdes_dq_.iserdesdq_Q7_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[5].iserdes_dq_.iserdesdq_Q8_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[5].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[5].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[6].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal \NLW_input_[6].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[6].iserdes_dq_.iserdesdq_O_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[6].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[6].iserdes_dq_.iserdesdq_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[6].iserdes_dq_.iserdesdq_Q5_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[6].iserdes_dq_.iserdesdq_Q6_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[6].iserdes_dq_.iserdesdq_Q7_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[6].iserdes_dq_.iserdesdq_Q8_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[6].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[6].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[7].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal \NLW_input_[7].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[7].iserdes_dq_.iserdesdq_O_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[7].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[7].iserdes_dq_.iserdesdq_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[7].iserdes_dq_.iserdesdq_Q5_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[7].iserdes_dq_.iserdesdq_Q6_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[7].iserdes_dq_.iserdesdq_Q7_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[7].iserdes_dq_.iserdesdq_Q8_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[7].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[7].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[8].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal \NLW_input_[8].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[8].iserdes_dq_.iserdesdq_O_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[8].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[8].iserdes_dq_.iserdesdq_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[8].iserdes_dq_.iserdesdq_Q5_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[8].iserdes_dq_.iserdesdq_Q6_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[8].iserdes_dq_.iserdesdq_Q7_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[8].iserdes_dq_.iserdesdq_Q8_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[8].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[8].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[9].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal \NLW_input_[9].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[9].iserdes_dq_.iserdesdq_O_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[9].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[9].iserdes_dq_.iserdesdq_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[9].iserdes_dq_.iserdesdq_Q5_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[9].iserdes_dq_.iserdesdq_Q6_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[9].iserdes_dq_.iserdesdq_Q7_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[9].iserdes_dq_.iserdesdq_Q8_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[9].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[9].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_slave_ts.oserdes_slave_ts_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_slave_ts.oserdes_slave_ts_OQ_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_slave_ts.oserdes_slave_ts_SHIFTIN1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_slave_ts.oserdes_slave_ts_SHIFTIN2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_slave_ts.oserdes_slave_ts_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_slave_ts.oserdes_slave_ts_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_slave_ts.oserdes_slave_ts_TFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_slave_ts.oserdes_slave_ts_TQ_UNCONNECTED\ : STD_LOGIC;
  attribute BOX_TYPE : string;
  attribute BOX_TYPE of \dqs_gen.oddr_dqs\ : label is "PRIMITIVE";
  attribute \__SRVAL\ : string;
  attribute \__SRVAL\ of \dqs_gen.oddr_dqs\ : label is "FALSE";
  attribute BOX_TYPE of \dqs_gen.oddr_dqsts\ : label is "PRIMITIVE";
  attribute \__SRVAL\ of \dqs_gen.oddr_dqsts\ : label is "TRUE";
  attribute BOX_TYPE of \input_[2].iserdes_dq_.idelay_dq.idelaye2\ : label is "PRIMITIVE";
  attribute IODELAY_GROUP : string;
  attribute IODELAY_GROUP of \input_[2].iserdes_dq_.idelay_dq.idelaye2\ : label is "MIG_IODELAY_MIG0";
  attribute SIM_DELAY_D : integer;
  attribute SIM_DELAY_D of \input_[2].iserdes_dq_.idelay_dq.idelaye2\ : label is 0;
  attribute BOX_TYPE of \input_[2].iserdes_dq_.iserdesdq\ : label is "PRIMITIVE";
  attribute OPT_MODIFIED : string;
  attribute OPT_MODIFIED of \input_[2].iserdes_dq_.iserdesdq\ : label is "MLO";
  attribute BOX_TYPE of \input_[3].iserdes_dq_.idelay_dq.idelaye2\ : label is "PRIMITIVE";
  attribute IODELAY_GROUP of \input_[3].iserdes_dq_.idelay_dq.idelaye2\ : label is "MIG_IODELAY_MIG0";
  attribute SIM_DELAY_D of \input_[3].iserdes_dq_.idelay_dq.idelaye2\ : label is 0;
  attribute BOX_TYPE of \input_[3].iserdes_dq_.iserdesdq\ : label is "PRIMITIVE";
  attribute OPT_MODIFIED of \input_[3].iserdes_dq_.iserdesdq\ : label is "MLO";
  attribute BOX_TYPE of \input_[4].iserdes_dq_.idelay_dq.idelaye2\ : label is "PRIMITIVE";
  attribute IODELAY_GROUP of \input_[4].iserdes_dq_.idelay_dq.idelaye2\ : label is "MIG_IODELAY_MIG0";
  attribute SIM_DELAY_D of \input_[4].iserdes_dq_.idelay_dq.idelaye2\ : label is 0;
  attribute BOX_TYPE of \input_[4].iserdes_dq_.iserdesdq\ : label is "PRIMITIVE";
  attribute OPT_MODIFIED of \input_[4].iserdes_dq_.iserdesdq\ : label is "MLO";
  attribute BOX_TYPE of \input_[5].iserdes_dq_.idelay_dq.idelaye2\ : label is "PRIMITIVE";
  attribute IODELAY_GROUP of \input_[5].iserdes_dq_.idelay_dq.idelaye2\ : label is "MIG_IODELAY_MIG0";
  attribute SIM_DELAY_D of \input_[5].iserdes_dq_.idelay_dq.idelaye2\ : label is 0;
  attribute BOX_TYPE of \input_[5].iserdes_dq_.iserdesdq\ : label is "PRIMITIVE";
  attribute OPT_MODIFIED of \input_[5].iserdes_dq_.iserdesdq\ : label is "MLO";
  attribute BOX_TYPE of \input_[6].iserdes_dq_.idelay_dq.idelaye2\ : label is "PRIMITIVE";
  attribute IODELAY_GROUP of \input_[6].iserdes_dq_.idelay_dq.idelaye2\ : label is "MIG_IODELAY_MIG0";
  attribute SIM_DELAY_D of \input_[6].iserdes_dq_.idelay_dq.idelaye2\ : label is 0;
  attribute BOX_TYPE of \input_[6].iserdes_dq_.iserdesdq\ : label is "PRIMITIVE";
  attribute OPT_MODIFIED of \input_[6].iserdes_dq_.iserdesdq\ : label is "MLO";
  attribute BOX_TYPE of \input_[7].iserdes_dq_.idelay_dq.idelaye2\ : label is "PRIMITIVE";
  attribute IODELAY_GROUP of \input_[7].iserdes_dq_.idelay_dq.idelaye2\ : label is "MIG_IODELAY_MIG0";
  attribute SIM_DELAY_D of \input_[7].iserdes_dq_.idelay_dq.idelaye2\ : label is 0;
  attribute BOX_TYPE of \input_[7].iserdes_dq_.iserdesdq\ : label is "PRIMITIVE";
  attribute OPT_MODIFIED of \input_[7].iserdes_dq_.iserdesdq\ : label is "MLO";
  attribute BOX_TYPE of \input_[8].iserdes_dq_.idelay_dq.idelaye2\ : label is "PRIMITIVE";
  attribute IODELAY_GROUP of \input_[8].iserdes_dq_.idelay_dq.idelaye2\ : label is "MIG_IODELAY_MIG0";
  attribute SIM_DELAY_D of \input_[8].iserdes_dq_.idelay_dq.idelaye2\ : label is 0;
  attribute BOX_TYPE of \input_[8].iserdes_dq_.iserdesdq\ : label is "PRIMITIVE";
  attribute OPT_MODIFIED of \input_[8].iserdes_dq_.iserdesdq\ : label is "MLO";
  attribute BOX_TYPE of \input_[9].iserdes_dq_.idelay_dq.idelaye2\ : label is "PRIMITIVE";
  attribute IODELAY_GROUP of \input_[9].iserdes_dq_.idelay_dq.idelaye2\ : label is "MIG_IODELAY_MIG0";
  attribute SIM_DELAY_D of \input_[9].iserdes_dq_.idelay_dq.idelaye2\ : label is 0;
  attribute BOX_TYPE of \input_[9].iserdes_dq_.iserdesdq\ : label is "PRIMITIVE";
  attribute OPT_MODIFIED of \input_[9].iserdes_dq_.iserdesdq\ : label is "MLO";
  attribute BOX_TYPE of \output_[1].oserdes_dq_.ddr.oserdes_dq_i\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \output_[2].oserdes_dq_.ddr.oserdes_dq_i\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \output_[3].oserdes_dq_.ddr.oserdes_dq_i\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \output_[4].oserdes_dq_.ddr.oserdes_dq_i\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \output_[5].oserdes_dq_.ddr.oserdes_dq_i\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \output_[6].oserdes_dq_.ddr.oserdes_dq_i\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \output_[7].oserdes_dq_.ddr.oserdes_dq_i\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \output_[8].oserdes_dq_.ddr.oserdes_dq_i\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \output_[9].oserdes_dq_.ddr.oserdes_dq_i\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \slave_ts.oserdes_slave_ts\ : label is "PRIMITIVE";
begin
  idelay_ld_rst_4 <= \^idelay_ld_rst_4\;
\dqs_gen.oddr_dqs\: unisim.vcomponents.ODDR
    generic map(
      DDR_CLK_EDGE => "SAME_EDGE",
      INIT => '0',
      IS_C_INVERTED => '0',
      IS_D1_INVERTED => '0',
      IS_D2_INVERTED => '0',
      SRTYPE => "SYNC"
    )
        port map (
      C => oserdes_clk_delayed,
      CE => '1',
      D1 => DQSBUS(0),
      D2 => DQSBUS(1),
      Q => out_dqs_1,
      R => '0',
      S => \NLW_dqs_gen.oddr_dqs_S_UNCONNECTED\
    );
\dqs_gen.oddr_dqsts\: unisim.vcomponents.ODDR
    generic map(
      DDR_CLK_EDGE => "SAME_EDGE",
      INIT => '0',
      IS_C_INVERTED => '0',
      IS_D1_INVERTED => '0',
      IS_D2_INVERTED => '0',
      SRTYPE => "SYNC"
    )
        port map (
      C => oserdes_clk_delayed,
      CE => '1',
      D1 => CTSBUS(0),
      D2 => CTSBUS(0),
      Q => ts_dqs_1,
      R => \NLW_dqs_gen.oddr_dqsts_R_UNCONNECTED\,
      S => '0'
    );
\idelay_ld_rst_i_1__4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \^idelay_ld_rst_4\,
      I1 => rst_r4,
      O => \idelay_ld_rst_i_1__4_n_0\
    );
idelay_ld_rst_reg: unisim.vcomponents.FDSE
     port map (
      C => idelay_ld_rst_reg_0,
      CE => '1',
      D => \idelay_ld_rst_i_1__4_n_0\,
      Q => \^idelay_ld_rst_4\,
      S => A_rst_primitives
    );
\input_[2].iserdes_dq_.idelay_dq.idelaye2\: unisim.vcomponents.IDELAYE2
    generic map(
      CINVCTRL_SEL => "FALSE",
      DELAY_SRC => "IDATAIN",
      HIGH_PERFORMANCE_MODE => "TRUE",
      IDELAY_TYPE => "VARIABLE",
      IDELAY_VALUE => 0,
      IS_C_INVERTED => '0',
      IS_DATAIN_INVERTED => '0',
      IS_IDATAIN_INVERTED => '0',
      PIPE_SEL => "FALSE",
      REFCLK_FREQUENCY => 200.000000,
      SIGNAL_PATTERN => "DATA"
    )
        port map (
      C => idelay_ld_rst_reg_0,
      CE => \input_[9].iserdes_dq_.iserdesdq_0\,
      CINVCTRL => '0',
      CNTVALUEIN(4 downto 0) => B"00000",
      CNTVALUEOUT(4 downto 0) => \NLW_input_[2].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED\(4 downto 0),
      DATAIN => '0',
      DATAOUT => data_in_dly_2,
      IDATAIN => mem_dq_in(0),
      INC => idelay_inc,
      LD => LD0_11,
      LDPIPEEN => '0',
      REGRST => A_rst_primitives
    );
\input_[2].iserdes_dq_.iserdesdq\: unisim.vcomponents.ISERDESE2
    generic map(
      DATA_RATE => "DDR",
      DATA_WIDTH => 4,
      DYN_CLKDIV_INV_EN => "FALSE",
      DYN_CLK_INV_EN => "FALSE",
      INIT_Q1 => '0',
      INIT_Q2 => '0',
      INIT_Q3 => '0',
      INIT_Q4 => '0',
      INTERFACE_TYPE => "MEMORY_DDR3",
      IOBDELAY => "IFD",
      IS_CLKB_INVERTED => '1',
      IS_CLKDIVP_INVERTED => '0',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D_INVERTED => '0',
      IS_OCLKB_INVERTED => '0',
      IS_OCLK_INVERTED => '0',
      NUM_CE => 2,
      OFB_USED => "FALSE",
      SERDES_MODE => "MASTER",
      SRVAL_Q1 => '0',
      SRVAL_Q2 => '0',
      SRVAL_Q3 => '0',
      SRVAL_Q4 => '0'
    )
        port map (
      BITSLIP => '0',
      CE1 => '1',
      CE2 => '1',
      CLK => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]\,
      CLKB => CLKB0_11,
      CLKDIV => \NLW_input_[2].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED\,
      CLKDIVP => iserdes_clkdiv,
      D => mem_dq_in(0),
      DDLY => data_in_dly_2,
      DYNCLKDIVSEL => '0',
      DYNCLKSEL => '0',
      O => \NLW_input_[2].iserdes_dq_.iserdesdq_O_UNCONNECTED\,
      OCLK => oserdes_clk,
      OCLKB => \NLW_input_[2].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED\,
      OFB => \NLW_input_[2].iserdes_dq_.iserdesdq_OFB_UNCONNECTED\,
      Q1 => D2(3),
      Q2 => D2(2),
      Q3 => D2(1),
      Q4 => D2(0),
      Q5 => \NLW_input_[2].iserdes_dq_.iserdesdq_Q5_UNCONNECTED\,
      Q6 => \NLW_input_[2].iserdes_dq_.iserdesdq_Q6_UNCONNECTED\,
      Q7 => \NLW_input_[2].iserdes_dq_.iserdesdq_Q7_UNCONNECTED\,
      Q8 => \NLW_input_[2].iserdes_dq_.iserdesdq_Q8_UNCONNECTED\,
      RST => '0',
      SHIFTIN1 => '0',
      SHIFTIN2 => '0',
      SHIFTOUT1 => \NLW_input_[2].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_input_[2].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED\
    );
\input_[3].iserdes_dq_.idelay_dq.idelaye2\: unisim.vcomponents.IDELAYE2
    generic map(
      CINVCTRL_SEL => "FALSE",
      DELAY_SRC => "IDATAIN",
      HIGH_PERFORMANCE_MODE => "TRUE",
      IDELAY_TYPE => "VARIABLE",
      IDELAY_VALUE => 0,
      IS_C_INVERTED => '0',
      IS_DATAIN_INVERTED => '0',
      IS_IDATAIN_INVERTED => '0',
      PIPE_SEL => "FALSE",
      REFCLK_FREQUENCY => 200.000000,
      SIGNAL_PATTERN => "DATA"
    )
        port map (
      C => idelay_ld_rst_reg_0,
      CE => \input_[9].iserdes_dq_.iserdesdq_0\,
      CINVCTRL => '0',
      CNTVALUEIN(4 downto 0) => B"00000",
      CNTVALUEOUT(4 downto 0) => \NLW_input_[3].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED\(4 downto 0),
      DATAIN => '0',
      DATAOUT => data_in_dly_3,
      IDATAIN => mem_dq_in(1),
      INC => idelay_inc,
      LD => LD0_11,
      LDPIPEEN => '0',
      REGRST => A_rst_primitives
    );
\input_[3].iserdes_dq_.iserdesdq\: unisim.vcomponents.ISERDESE2
    generic map(
      DATA_RATE => "DDR",
      DATA_WIDTH => 4,
      DYN_CLKDIV_INV_EN => "FALSE",
      DYN_CLK_INV_EN => "FALSE",
      INIT_Q1 => '0',
      INIT_Q2 => '0',
      INIT_Q3 => '0',
      INIT_Q4 => '0',
      INTERFACE_TYPE => "MEMORY_DDR3",
      IOBDELAY => "IFD",
      IS_CLKB_INVERTED => '1',
      IS_CLKDIVP_INVERTED => '0',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D_INVERTED => '0',
      IS_OCLKB_INVERTED => '0',
      IS_OCLK_INVERTED => '0',
      NUM_CE => 2,
      OFB_USED => "FALSE",
      SERDES_MODE => "MASTER",
      SRVAL_Q1 => '0',
      SRVAL_Q2 => '0',
      SRVAL_Q3 => '0',
      SRVAL_Q4 => '0'
    )
        port map (
      BITSLIP => '0',
      CE1 => '1',
      CE2 => '1',
      CLK => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]\,
      CLKB => CLKB0_11,
      CLKDIV => \NLW_input_[3].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED\,
      CLKDIVP => iserdes_clkdiv,
      D => mem_dq_in(1),
      DDLY => data_in_dly_3,
      DYNCLKDIVSEL => '0',
      DYNCLKSEL => '0',
      O => \NLW_input_[3].iserdes_dq_.iserdesdq_O_UNCONNECTED\,
      OCLK => oserdes_clk,
      OCLKB => \NLW_input_[3].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED\,
      OFB => \NLW_input_[3].iserdes_dq_.iserdesdq_OFB_UNCONNECTED\,
      Q1 => D3(3),
      Q2 => D3(2),
      Q3 => D3(1),
      Q4 => D3(0),
      Q5 => \NLW_input_[3].iserdes_dq_.iserdesdq_Q5_UNCONNECTED\,
      Q6 => \NLW_input_[3].iserdes_dq_.iserdesdq_Q6_UNCONNECTED\,
      Q7 => \NLW_input_[3].iserdes_dq_.iserdesdq_Q7_UNCONNECTED\,
      Q8 => \NLW_input_[3].iserdes_dq_.iserdesdq_Q8_UNCONNECTED\,
      RST => '0',
      SHIFTIN1 => '0',
      SHIFTIN2 => '0',
      SHIFTOUT1 => \NLW_input_[3].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_input_[3].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED\
    );
\input_[4].iserdes_dq_.idelay_dq.idelaye2\: unisim.vcomponents.IDELAYE2
    generic map(
      CINVCTRL_SEL => "FALSE",
      DELAY_SRC => "IDATAIN",
      HIGH_PERFORMANCE_MODE => "TRUE",
      IDELAY_TYPE => "VARIABLE",
      IDELAY_VALUE => 0,
      IS_C_INVERTED => '0',
      IS_DATAIN_INVERTED => '0',
      IS_IDATAIN_INVERTED => '0',
      PIPE_SEL => "FALSE",
      REFCLK_FREQUENCY => 200.000000,
      SIGNAL_PATTERN => "DATA"
    )
        port map (
      C => idelay_ld_rst_reg_0,
      CE => \input_[9].iserdes_dq_.iserdesdq_0\,
      CINVCTRL => '0',
      CNTVALUEIN(4 downto 0) => B"00000",
      CNTVALUEOUT(4 downto 0) => \NLW_input_[4].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED\(4 downto 0),
      DATAIN => '0',
      DATAOUT => data_in_dly_4,
      IDATAIN => mem_dq_in(2),
      INC => idelay_inc,
      LD => LD0_11,
      LDPIPEEN => '0',
      REGRST => A_rst_primitives
    );
\input_[4].iserdes_dq_.iserdesdq\: unisim.vcomponents.ISERDESE2
    generic map(
      DATA_RATE => "DDR",
      DATA_WIDTH => 4,
      DYN_CLKDIV_INV_EN => "FALSE",
      DYN_CLK_INV_EN => "FALSE",
      INIT_Q1 => '0',
      INIT_Q2 => '0',
      INIT_Q3 => '0',
      INIT_Q4 => '0',
      INTERFACE_TYPE => "MEMORY_DDR3",
      IOBDELAY => "IFD",
      IS_CLKB_INVERTED => '1',
      IS_CLKDIVP_INVERTED => '0',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D_INVERTED => '0',
      IS_OCLKB_INVERTED => '0',
      IS_OCLK_INVERTED => '0',
      NUM_CE => 2,
      OFB_USED => "FALSE",
      SERDES_MODE => "MASTER",
      SRVAL_Q1 => '0',
      SRVAL_Q2 => '0',
      SRVAL_Q3 => '0',
      SRVAL_Q4 => '0'
    )
        port map (
      BITSLIP => '0',
      CE1 => '1',
      CE2 => '1',
      CLK => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]\,
      CLKB => CLKB0_11,
      CLKDIV => \NLW_input_[4].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED\,
      CLKDIVP => iserdes_clkdiv,
      D => mem_dq_in(2),
      DDLY => data_in_dly_4,
      DYNCLKDIVSEL => '0',
      DYNCLKSEL => '0',
      O => \NLW_input_[4].iserdes_dq_.iserdesdq_O_UNCONNECTED\,
      OCLK => oserdes_clk,
      OCLKB => \NLW_input_[4].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED\,
      OFB => \NLW_input_[4].iserdes_dq_.iserdesdq_OFB_UNCONNECTED\,
      Q1 => D4(3),
      Q2 => D4(2),
      Q3 => D4(1),
      Q4 => D4(0),
      Q5 => \NLW_input_[4].iserdes_dq_.iserdesdq_Q5_UNCONNECTED\,
      Q6 => \NLW_input_[4].iserdes_dq_.iserdesdq_Q6_UNCONNECTED\,
      Q7 => \NLW_input_[4].iserdes_dq_.iserdesdq_Q7_UNCONNECTED\,
      Q8 => \NLW_input_[4].iserdes_dq_.iserdesdq_Q8_UNCONNECTED\,
      RST => '0',
      SHIFTIN1 => '0',
      SHIFTIN2 => '0',
      SHIFTOUT1 => \NLW_input_[4].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_input_[4].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED\
    );
\input_[5].iserdes_dq_.idelay_dq.idelaye2\: unisim.vcomponents.IDELAYE2
    generic map(
      CINVCTRL_SEL => "FALSE",
      DELAY_SRC => "IDATAIN",
      HIGH_PERFORMANCE_MODE => "TRUE",
      IDELAY_TYPE => "VARIABLE",
      IDELAY_VALUE => 0,
      IS_C_INVERTED => '0',
      IS_DATAIN_INVERTED => '0',
      IS_IDATAIN_INVERTED => '0',
      PIPE_SEL => "FALSE",
      REFCLK_FREQUENCY => 200.000000,
      SIGNAL_PATTERN => "DATA"
    )
        port map (
      C => idelay_ld_rst_reg_0,
      CE => \input_[9].iserdes_dq_.iserdesdq_0\,
      CINVCTRL => '0',
      CNTVALUEIN(4 downto 0) => B"00000",
      CNTVALUEOUT(4 downto 0) => \NLW_input_[5].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED\(4 downto 0),
      DATAIN => '0',
      DATAOUT => data_in_dly_5,
      IDATAIN => mem_dq_in(3),
      INC => idelay_inc,
      LD => LD0_11,
      LDPIPEEN => '0',
      REGRST => A_rst_primitives
    );
\input_[5].iserdes_dq_.iserdesdq\: unisim.vcomponents.ISERDESE2
    generic map(
      DATA_RATE => "DDR",
      DATA_WIDTH => 4,
      DYN_CLKDIV_INV_EN => "FALSE",
      DYN_CLK_INV_EN => "FALSE",
      INIT_Q1 => '0',
      INIT_Q2 => '0',
      INIT_Q3 => '0',
      INIT_Q4 => '0',
      INTERFACE_TYPE => "MEMORY_DDR3",
      IOBDELAY => "IFD",
      IS_CLKB_INVERTED => '1',
      IS_CLKDIVP_INVERTED => '0',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D_INVERTED => '0',
      IS_OCLKB_INVERTED => '0',
      IS_OCLK_INVERTED => '0',
      NUM_CE => 2,
      OFB_USED => "FALSE",
      SERDES_MODE => "MASTER",
      SRVAL_Q1 => '0',
      SRVAL_Q2 => '0',
      SRVAL_Q3 => '0',
      SRVAL_Q4 => '0'
    )
        port map (
      BITSLIP => '0',
      CE1 => '1',
      CE2 => '1',
      CLK => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]\,
      CLKB => CLKB0_11,
      CLKDIV => \NLW_input_[5].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED\,
      CLKDIVP => iserdes_clkdiv,
      D => mem_dq_in(3),
      DDLY => data_in_dly_5,
      DYNCLKDIVSEL => '0',
      DYNCLKSEL => '0',
      O => \NLW_input_[5].iserdes_dq_.iserdesdq_O_UNCONNECTED\,
      OCLK => oserdes_clk,
      OCLKB => \NLW_input_[5].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED\,
      OFB => \NLW_input_[5].iserdes_dq_.iserdesdq_OFB_UNCONNECTED\,
      Q1 => D5(3),
      Q2 => D5(2),
      Q3 => D5(1),
      Q4 => D5(0),
      Q5 => \NLW_input_[5].iserdes_dq_.iserdesdq_Q5_UNCONNECTED\,
      Q6 => \NLW_input_[5].iserdes_dq_.iserdesdq_Q6_UNCONNECTED\,
      Q7 => \NLW_input_[5].iserdes_dq_.iserdesdq_Q7_UNCONNECTED\,
      Q8 => \NLW_input_[5].iserdes_dq_.iserdesdq_Q8_UNCONNECTED\,
      RST => '0',
      SHIFTIN1 => '0',
      SHIFTIN2 => '0',
      SHIFTOUT1 => \NLW_input_[5].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_input_[5].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED\
    );
\input_[6].iserdes_dq_.idelay_dq.idelaye2\: unisim.vcomponents.IDELAYE2
    generic map(
      CINVCTRL_SEL => "FALSE",
      DELAY_SRC => "IDATAIN",
      HIGH_PERFORMANCE_MODE => "TRUE",
      IDELAY_TYPE => "VARIABLE",
      IDELAY_VALUE => 0,
      IS_C_INVERTED => '0',
      IS_DATAIN_INVERTED => '0',
      IS_IDATAIN_INVERTED => '0',
      PIPE_SEL => "FALSE",
      REFCLK_FREQUENCY => 200.000000,
      SIGNAL_PATTERN => "DATA"
    )
        port map (
      C => idelay_ld_rst_reg_0,
      CE => \input_[9].iserdes_dq_.iserdesdq_0\,
      CINVCTRL => '0',
      CNTVALUEIN(4 downto 0) => B"00000",
      CNTVALUEOUT(4 downto 0) => \NLW_input_[6].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED\(4 downto 0),
      DATAIN => '0',
      DATAOUT => data_in_dly_6,
      IDATAIN => mem_dq_in(4),
      INC => idelay_inc,
      LD => LD0_11,
      LDPIPEEN => '0',
      REGRST => A_rst_primitives
    );
\input_[6].iserdes_dq_.iserdesdq\: unisim.vcomponents.ISERDESE2
    generic map(
      DATA_RATE => "DDR",
      DATA_WIDTH => 4,
      DYN_CLKDIV_INV_EN => "FALSE",
      DYN_CLK_INV_EN => "FALSE",
      INIT_Q1 => '0',
      INIT_Q2 => '0',
      INIT_Q3 => '0',
      INIT_Q4 => '0',
      INTERFACE_TYPE => "MEMORY_DDR3",
      IOBDELAY => "IFD",
      IS_CLKB_INVERTED => '1',
      IS_CLKDIVP_INVERTED => '0',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D_INVERTED => '0',
      IS_OCLKB_INVERTED => '0',
      IS_OCLK_INVERTED => '0',
      NUM_CE => 2,
      OFB_USED => "FALSE",
      SERDES_MODE => "MASTER",
      SRVAL_Q1 => '0',
      SRVAL_Q2 => '0',
      SRVAL_Q3 => '0',
      SRVAL_Q4 => '0'
    )
        port map (
      BITSLIP => '0',
      CE1 => '1',
      CE2 => '1',
      CLK => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]\,
      CLKB => CLKB0_11,
      CLKDIV => \NLW_input_[6].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED\,
      CLKDIVP => iserdes_clkdiv,
      D => mem_dq_in(4),
      DDLY => data_in_dly_6,
      DYNCLKDIVSEL => '0',
      DYNCLKSEL => '0',
      O => \NLW_input_[6].iserdes_dq_.iserdesdq_O_UNCONNECTED\,
      OCLK => oserdes_clk,
      OCLKB => \NLW_input_[6].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED\,
      OFB => \NLW_input_[6].iserdes_dq_.iserdesdq_OFB_UNCONNECTED\,
      Q1 => D6(3),
      Q2 => D6(2),
      Q3 => D6(1),
      Q4 => D6(0),
      Q5 => \NLW_input_[6].iserdes_dq_.iserdesdq_Q5_UNCONNECTED\,
      Q6 => \NLW_input_[6].iserdes_dq_.iserdesdq_Q6_UNCONNECTED\,
      Q7 => \NLW_input_[6].iserdes_dq_.iserdesdq_Q7_UNCONNECTED\,
      Q8 => \NLW_input_[6].iserdes_dq_.iserdesdq_Q8_UNCONNECTED\,
      RST => '0',
      SHIFTIN1 => '0',
      SHIFTIN2 => '0',
      SHIFTOUT1 => \NLW_input_[6].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_input_[6].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED\
    );
\input_[7].iserdes_dq_.idelay_dq.idelaye2\: unisim.vcomponents.IDELAYE2
    generic map(
      CINVCTRL_SEL => "FALSE",
      DELAY_SRC => "IDATAIN",
      HIGH_PERFORMANCE_MODE => "TRUE",
      IDELAY_TYPE => "VARIABLE",
      IDELAY_VALUE => 0,
      IS_C_INVERTED => '0',
      IS_DATAIN_INVERTED => '0',
      IS_IDATAIN_INVERTED => '0',
      PIPE_SEL => "FALSE",
      REFCLK_FREQUENCY => 200.000000,
      SIGNAL_PATTERN => "DATA"
    )
        port map (
      C => idelay_ld_rst_reg_0,
      CE => \input_[9].iserdes_dq_.iserdesdq_0\,
      CINVCTRL => '0',
      CNTVALUEIN(4 downto 0) => B"00000",
      CNTVALUEOUT(4 downto 0) => \NLW_input_[7].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED\(4 downto 0),
      DATAIN => '0',
      DATAOUT => data_in_dly_7,
      IDATAIN => mem_dq_in(5),
      INC => idelay_inc,
      LD => LD0_11,
      LDPIPEEN => '0',
      REGRST => A_rst_primitives
    );
\input_[7].iserdes_dq_.iserdesdq\: unisim.vcomponents.ISERDESE2
    generic map(
      DATA_RATE => "DDR",
      DATA_WIDTH => 4,
      DYN_CLKDIV_INV_EN => "FALSE",
      DYN_CLK_INV_EN => "FALSE",
      INIT_Q1 => '0',
      INIT_Q2 => '0',
      INIT_Q3 => '0',
      INIT_Q4 => '0',
      INTERFACE_TYPE => "MEMORY_DDR3",
      IOBDELAY => "IFD",
      IS_CLKB_INVERTED => '1',
      IS_CLKDIVP_INVERTED => '0',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D_INVERTED => '0',
      IS_OCLKB_INVERTED => '0',
      IS_OCLK_INVERTED => '0',
      NUM_CE => 2,
      OFB_USED => "FALSE",
      SERDES_MODE => "MASTER",
      SRVAL_Q1 => '0',
      SRVAL_Q2 => '0',
      SRVAL_Q3 => '0',
      SRVAL_Q4 => '0'
    )
        port map (
      BITSLIP => '0',
      CE1 => '1',
      CE2 => '1',
      CLK => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]\,
      CLKB => CLKB0_11,
      CLKDIV => \NLW_input_[7].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED\,
      CLKDIVP => iserdes_clkdiv,
      D => mem_dq_in(5),
      DDLY => data_in_dly_7,
      DYNCLKDIVSEL => '0',
      DYNCLKSEL => '0',
      O => \NLW_input_[7].iserdes_dq_.iserdesdq_O_UNCONNECTED\,
      OCLK => oserdes_clk,
      OCLKB => \NLW_input_[7].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED\,
      OFB => \NLW_input_[7].iserdes_dq_.iserdesdq_OFB_UNCONNECTED\,
      Q1 => D7(3),
      Q2 => D7(2),
      Q3 => D7(1),
      Q4 => D7(0),
      Q5 => \NLW_input_[7].iserdes_dq_.iserdesdq_Q5_UNCONNECTED\,
      Q6 => \NLW_input_[7].iserdes_dq_.iserdesdq_Q6_UNCONNECTED\,
      Q7 => \NLW_input_[7].iserdes_dq_.iserdesdq_Q7_UNCONNECTED\,
      Q8 => \NLW_input_[7].iserdes_dq_.iserdesdq_Q8_UNCONNECTED\,
      RST => '0',
      SHIFTIN1 => '0',
      SHIFTIN2 => '0',
      SHIFTOUT1 => \NLW_input_[7].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_input_[7].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED\
    );
\input_[8].iserdes_dq_.idelay_dq.idelaye2\: unisim.vcomponents.IDELAYE2
    generic map(
      CINVCTRL_SEL => "FALSE",
      DELAY_SRC => "IDATAIN",
      HIGH_PERFORMANCE_MODE => "TRUE",
      IDELAY_TYPE => "VARIABLE",
      IDELAY_VALUE => 0,
      IS_C_INVERTED => '0',
      IS_DATAIN_INVERTED => '0',
      IS_IDATAIN_INVERTED => '0',
      PIPE_SEL => "FALSE",
      REFCLK_FREQUENCY => 200.000000,
      SIGNAL_PATTERN => "DATA"
    )
        port map (
      C => idelay_ld_rst_reg_0,
      CE => \input_[9].iserdes_dq_.iserdesdq_0\,
      CINVCTRL => '0',
      CNTVALUEIN(4 downto 0) => B"00000",
      CNTVALUEOUT(4 downto 0) => \NLW_input_[8].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED\(4 downto 0),
      DATAIN => '0',
      DATAOUT => data_in_dly_8,
      IDATAIN => mem_dq_in(6),
      INC => idelay_inc,
      LD => LD0_11,
      LDPIPEEN => '0',
      REGRST => A_rst_primitives
    );
\input_[8].iserdes_dq_.iserdesdq\: unisim.vcomponents.ISERDESE2
    generic map(
      DATA_RATE => "DDR",
      DATA_WIDTH => 4,
      DYN_CLKDIV_INV_EN => "FALSE",
      DYN_CLK_INV_EN => "FALSE",
      INIT_Q1 => '0',
      INIT_Q2 => '0',
      INIT_Q3 => '0',
      INIT_Q4 => '0',
      INTERFACE_TYPE => "MEMORY_DDR3",
      IOBDELAY => "IFD",
      IS_CLKB_INVERTED => '1',
      IS_CLKDIVP_INVERTED => '0',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D_INVERTED => '0',
      IS_OCLKB_INVERTED => '0',
      IS_OCLK_INVERTED => '0',
      NUM_CE => 2,
      OFB_USED => "FALSE",
      SERDES_MODE => "MASTER",
      SRVAL_Q1 => '0',
      SRVAL_Q2 => '0',
      SRVAL_Q3 => '0',
      SRVAL_Q4 => '0'
    )
        port map (
      BITSLIP => '0',
      CE1 => '1',
      CE2 => '1',
      CLK => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]\,
      CLKB => CLKB0_11,
      CLKDIV => \NLW_input_[8].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED\,
      CLKDIVP => iserdes_clkdiv,
      D => mem_dq_in(6),
      DDLY => data_in_dly_8,
      DYNCLKDIVSEL => '0',
      DYNCLKSEL => '0',
      O => \NLW_input_[8].iserdes_dq_.iserdesdq_O_UNCONNECTED\,
      OCLK => oserdes_clk,
      OCLKB => \NLW_input_[8].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED\,
      OFB => \NLW_input_[8].iserdes_dq_.iserdesdq_OFB_UNCONNECTED\,
      Q1 => D8(3),
      Q2 => D8(2),
      Q3 => D8(1),
      Q4 => D8(0),
      Q5 => \NLW_input_[8].iserdes_dq_.iserdesdq_Q5_UNCONNECTED\,
      Q6 => \NLW_input_[8].iserdes_dq_.iserdesdq_Q6_UNCONNECTED\,
      Q7 => \NLW_input_[8].iserdes_dq_.iserdesdq_Q7_UNCONNECTED\,
      Q8 => \NLW_input_[8].iserdes_dq_.iserdesdq_Q8_UNCONNECTED\,
      RST => '0',
      SHIFTIN1 => '0',
      SHIFTIN2 => '0',
      SHIFTOUT1 => \NLW_input_[8].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_input_[8].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED\
    );
\input_[9].iserdes_dq_.idelay_dq.idelaye2\: unisim.vcomponents.IDELAYE2
    generic map(
      CINVCTRL_SEL => "FALSE",
      DELAY_SRC => "IDATAIN",
      HIGH_PERFORMANCE_MODE => "TRUE",
      IDELAY_TYPE => "VARIABLE",
      IDELAY_VALUE => 0,
      IS_C_INVERTED => '0',
      IS_DATAIN_INVERTED => '0',
      IS_IDATAIN_INVERTED => '0',
      PIPE_SEL => "FALSE",
      REFCLK_FREQUENCY => 200.000000,
      SIGNAL_PATTERN => "DATA"
    )
        port map (
      C => idelay_ld_rst_reg_0,
      CE => \input_[9].iserdes_dq_.iserdesdq_0\,
      CINVCTRL => '0',
      CNTVALUEIN(4 downto 0) => B"00000",
      CNTVALUEOUT(4 downto 0) => \NLW_input_[9].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED\(4 downto 0),
      DATAIN => '0',
      DATAOUT => data_in_dly_9,
      IDATAIN => mem_dq_in(7),
      INC => idelay_inc,
      LD => LD0_11,
      LDPIPEEN => '0',
      REGRST => A_rst_primitives
    );
\input_[9].iserdes_dq_.iserdesdq\: unisim.vcomponents.ISERDESE2
    generic map(
      DATA_RATE => "DDR",
      DATA_WIDTH => 4,
      DYN_CLKDIV_INV_EN => "FALSE",
      DYN_CLK_INV_EN => "FALSE",
      INIT_Q1 => '0',
      INIT_Q2 => '0',
      INIT_Q3 => '0',
      INIT_Q4 => '0',
      INTERFACE_TYPE => "MEMORY_DDR3",
      IOBDELAY => "IFD",
      IS_CLKB_INVERTED => '1',
      IS_CLKDIVP_INVERTED => '0',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D_INVERTED => '0',
      IS_OCLKB_INVERTED => '0',
      IS_OCLK_INVERTED => '0',
      NUM_CE => 2,
      OFB_USED => "FALSE",
      SERDES_MODE => "MASTER",
      SRVAL_Q1 => '0',
      SRVAL_Q2 => '0',
      SRVAL_Q3 => '0',
      SRVAL_Q4 => '0'
    )
        port map (
      BITSLIP => '0',
      CE1 => '1',
      CE2 => '1',
      CLK => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]\,
      CLKB => CLKB0_11,
      CLKDIV => \NLW_input_[9].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED\,
      CLKDIVP => iserdes_clkdiv,
      D => mem_dq_in(7),
      DDLY => data_in_dly_9,
      DYNCLKDIVSEL => '0',
      DYNCLKSEL => '0',
      O => \NLW_input_[9].iserdes_dq_.iserdesdq_O_UNCONNECTED\,
      OCLK => oserdes_clk,
      OCLKB => \NLW_input_[9].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED\,
      OFB => \NLW_input_[9].iserdes_dq_.iserdesdq_OFB_UNCONNECTED\,
      Q1 => D9(3),
      Q2 => D9(2),
      Q3 => D9(1),
      Q4 => D9(0),
      Q5 => \NLW_input_[9].iserdes_dq_.iserdesdq_Q5_UNCONNECTED\,
      Q6 => \NLW_input_[9].iserdes_dq_.iserdesdq_Q6_UNCONNECTED\,
      Q7 => \NLW_input_[9].iserdes_dq_.iserdesdq_Q7_UNCONNECTED\,
      Q8 => \NLW_input_[9].iserdes_dq_.iserdesdq_Q8_UNCONNECTED\,
      RST => '0',
      SHIFTIN1 => '0',
      SHIFTIN2 => '0',
      SHIFTOUT1 => \NLW_input_[9].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_input_[9].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED\
    );
\output_[1].oserdes_dq_.ddr.oserdes_dq_i\: unisim.vcomponents.OSERDESE2
    generic map(
      DATA_RATE_OQ => "DDR",
      DATA_RATE_TQ => "DDR",
      DATA_WIDTH => 4,
      INIT_OQ => '1',
      INIT_TQ => '1',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D1_INVERTED => '0',
      IS_D2_INVERTED => '0',
      IS_D3_INVERTED => '0',
      IS_D4_INVERTED => '0',
      IS_D5_INVERTED => '0',
      IS_D6_INVERTED => '0',
      IS_D7_INVERTED => '0',
      IS_D8_INVERTED => '0',
      IS_T1_INVERTED => '0',
      IS_T2_INVERTED => '0',
      IS_T3_INVERTED => '0',
      IS_T4_INVERTED => '0',
      SERDES_MODE => "MASTER",
      SRVAL_OQ => '1',
      SRVAL_TQ => '1',
      TBYTE_CTL => "TRUE",
      TBYTE_SRC => "FALSE",
      TRISTATE_WIDTH => 4
    )
        port map (
      CLK => oserdes_clk,
      CLKDIV => oserdes_clkdiv,
      D1 => of_dqbus(0),
      D2 => of_dqbus(1),
      D3 => of_dqbus(2),
      D4 => of_dqbus(3),
      D5 => '0',
      D6 => '0',
      D7 => '0',
      D8 => '0',
      OCE => '1',
      OFB => \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\,
      OQ => mem_dq_out(0),
      RST => po_oserdes_rst,
      SHIFTIN1 => \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\,
      SHIFTIN2 => \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\,
      SHIFTOUT1 => \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\,
      T1 => '0',
      T2 => '0',
      T3 => '0',
      T4 => '0',
      TBYTEIN => tbyte_out,
      TBYTEOUT => \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\,
      TCE => '1',
      TFB => \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\,
      TQ => mem_dq_ts(0)
    );
\output_[2].oserdes_dq_.ddr.oserdes_dq_i\: unisim.vcomponents.OSERDESE2
    generic map(
      DATA_RATE_OQ => "DDR",
      DATA_RATE_TQ => "DDR",
      DATA_WIDTH => 4,
      INIT_OQ => '1',
      INIT_TQ => '1',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D1_INVERTED => '0',
      IS_D2_INVERTED => '0',
      IS_D3_INVERTED => '0',
      IS_D4_INVERTED => '0',
      IS_D5_INVERTED => '0',
      IS_D6_INVERTED => '0',
      IS_D7_INVERTED => '0',
      IS_D8_INVERTED => '0',
      IS_T1_INVERTED => '0',
      IS_T2_INVERTED => '0',
      IS_T3_INVERTED => '0',
      IS_T4_INVERTED => '0',
      SERDES_MODE => "MASTER",
      SRVAL_OQ => '1',
      SRVAL_TQ => '1',
      TBYTE_CTL => "TRUE",
      TBYTE_SRC => "FALSE",
      TRISTATE_WIDTH => 4
    )
        port map (
      CLK => oserdes_clk,
      CLKDIV => oserdes_clkdiv,
      D1 => of_dqbus(4),
      D2 => of_dqbus(5),
      D3 => of_dqbus(6),
      D4 => of_dqbus(7),
      D5 => '0',
      D6 => '0',
      D7 => '0',
      D8 => '0',
      OCE => '1',
      OFB => \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\,
      OQ => mem_dq_out(1),
      RST => po_oserdes_rst,
      SHIFTIN1 => \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\,
      SHIFTIN2 => \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\,
      SHIFTOUT1 => \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\,
      T1 => '0',
      T2 => '0',
      T3 => '0',
      T4 => '0',
      TBYTEIN => tbyte_out,
      TBYTEOUT => \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\,
      TCE => '1',
      TFB => \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\,
      TQ => mem_dq_ts(1)
    );
\output_[3].oserdes_dq_.ddr.oserdes_dq_i\: unisim.vcomponents.OSERDESE2
    generic map(
      DATA_RATE_OQ => "DDR",
      DATA_RATE_TQ => "DDR",
      DATA_WIDTH => 4,
      INIT_OQ => '1',
      INIT_TQ => '1',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D1_INVERTED => '0',
      IS_D2_INVERTED => '0',
      IS_D3_INVERTED => '0',
      IS_D4_INVERTED => '0',
      IS_D5_INVERTED => '0',
      IS_D6_INVERTED => '0',
      IS_D7_INVERTED => '0',
      IS_D8_INVERTED => '0',
      IS_T1_INVERTED => '0',
      IS_T2_INVERTED => '0',
      IS_T3_INVERTED => '0',
      IS_T4_INVERTED => '0',
      SERDES_MODE => "MASTER",
      SRVAL_OQ => '1',
      SRVAL_TQ => '1',
      TBYTE_CTL => "TRUE",
      TBYTE_SRC => "FALSE",
      TRISTATE_WIDTH => 4
    )
        port map (
      CLK => oserdes_clk,
      CLKDIV => oserdes_clkdiv,
      D1 => of_dqbus(8),
      D2 => of_dqbus(9),
      D3 => of_dqbus(10),
      D4 => of_dqbus(11),
      D5 => '0',
      D6 => '0',
      D7 => '0',
      D8 => '0',
      OCE => '1',
      OFB => \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\,
      OQ => mem_dq_out(2),
      RST => po_oserdes_rst,
      SHIFTIN1 => \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\,
      SHIFTIN2 => \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\,
      SHIFTOUT1 => \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\,
      T1 => '0',
      T2 => '0',
      T3 => '0',
      T4 => '0',
      TBYTEIN => tbyte_out,
      TBYTEOUT => \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\,
      TCE => '1',
      TFB => \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\,
      TQ => mem_dq_ts(2)
    );
\output_[4].oserdes_dq_.ddr.oserdes_dq_i\: unisim.vcomponents.OSERDESE2
    generic map(
      DATA_RATE_OQ => "DDR",
      DATA_RATE_TQ => "DDR",
      DATA_WIDTH => 4,
      INIT_OQ => '1',
      INIT_TQ => '1',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D1_INVERTED => '0',
      IS_D2_INVERTED => '0',
      IS_D3_INVERTED => '0',
      IS_D4_INVERTED => '0',
      IS_D5_INVERTED => '0',
      IS_D6_INVERTED => '0',
      IS_D7_INVERTED => '0',
      IS_D8_INVERTED => '0',
      IS_T1_INVERTED => '0',
      IS_T2_INVERTED => '0',
      IS_T3_INVERTED => '0',
      IS_T4_INVERTED => '0',
      SERDES_MODE => "MASTER",
      SRVAL_OQ => '1',
      SRVAL_TQ => '1',
      TBYTE_CTL => "TRUE",
      TBYTE_SRC => "FALSE",
      TRISTATE_WIDTH => 4
    )
        port map (
      CLK => oserdes_clk,
      CLKDIV => oserdes_clkdiv,
      D1 => of_dqbus(12),
      D2 => of_dqbus(13),
      D3 => of_dqbus(14),
      D4 => of_dqbus(15),
      D5 => '0',
      D6 => '0',
      D7 => '0',
      D8 => '0',
      OCE => '1',
      OFB => \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\,
      OQ => mem_dq_out(3),
      RST => po_oserdes_rst,
      SHIFTIN1 => \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\,
      SHIFTIN2 => \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\,
      SHIFTOUT1 => \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\,
      T1 => '0',
      T2 => '0',
      T3 => '0',
      T4 => '0',
      TBYTEIN => tbyte_out,
      TBYTEOUT => \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\,
      TCE => '1',
      TFB => \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\,
      TQ => mem_dq_ts(3)
    );
\output_[5].oserdes_dq_.ddr.oserdes_dq_i\: unisim.vcomponents.OSERDESE2
    generic map(
      DATA_RATE_OQ => "DDR",
      DATA_RATE_TQ => "DDR",
      DATA_WIDTH => 4,
      INIT_OQ => '1',
      INIT_TQ => '1',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D1_INVERTED => '0',
      IS_D2_INVERTED => '0',
      IS_D3_INVERTED => '0',
      IS_D4_INVERTED => '0',
      IS_D5_INVERTED => '0',
      IS_D6_INVERTED => '0',
      IS_D7_INVERTED => '0',
      IS_D8_INVERTED => '0',
      IS_T1_INVERTED => '0',
      IS_T2_INVERTED => '0',
      IS_T3_INVERTED => '0',
      IS_T4_INVERTED => '0',
      SERDES_MODE => "MASTER",
      SRVAL_OQ => '1',
      SRVAL_TQ => '1',
      TBYTE_CTL => "TRUE",
      TBYTE_SRC => "FALSE",
      TRISTATE_WIDTH => 4
    )
        port map (
      CLK => oserdes_clk,
      CLKDIV => oserdes_clkdiv,
      D1 => of_dqbus(16),
      D2 => of_dqbus(17),
      D3 => of_dqbus(18),
      D4 => of_dqbus(19),
      D5 => '0',
      D6 => '0',
      D7 => '0',
      D8 => '0',
      OCE => '1',
      OFB => \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\,
      OQ => mem_dq_out(4),
      RST => po_oserdes_rst,
      SHIFTIN1 => \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\,
      SHIFTIN2 => \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\,
      SHIFTOUT1 => \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\,
      T1 => '0',
      T2 => '0',
      T3 => '0',
      T4 => '0',
      TBYTEIN => tbyte_out,
      TBYTEOUT => \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\,
      TCE => '1',
      TFB => \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\,
      TQ => mem_dq_ts(4)
    );
\output_[6].oserdes_dq_.ddr.oserdes_dq_i\: unisim.vcomponents.OSERDESE2
    generic map(
      DATA_RATE_OQ => "DDR",
      DATA_RATE_TQ => "DDR",
      DATA_WIDTH => 4,
      INIT_OQ => '1',
      INIT_TQ => '1',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D1_INVERTED => '0',
      IS_D2_INVERTED => '0',
      IS_D3_INVERTED => '0',
      IS_D4_INVERTED => '0',
      IS_D5_INVERTED => '0',
      IS_D6_INVERTED => '0',
      IS_D7_INVERTED => '0',
      IS_D8_INVERTED => '0',
      IS_T1_INVERTED => '0',
      IS_T2_INVERTED => '0',
      IS_T3_INVERTED => '0',
      IS_T4_INVERTED => '0',
      SERDES_MODE => "MASTER",
      SRVAL_OQ => '1',
      SRVAL_TQ => '1',
      TBYTE_CTL => "TRUE",
      TBYTE_SRC => "FALSE",
      TRISTATE_WIDTH => 4
    )
        port map (
      CLK => oserdes_clk,
      CLKDIV => oserdes_clkdiv,
      D1 => of_dqbus(20),
      D2 => of_dqbus(21),
      D3 => of_dqbus(22),
      D4 => of_dqbus(23),
      D5 => '0',
      D6 => '0',
      D7 => '0',
      D8 => '0',
      OCE => '1',
      OFB => \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\,
      OQ => mem_dq_out(5),
      RST => po_oserdes_rst,
      SHIFTIN1 => \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\,
      SHIFTIN2 => \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\,
      SHIFTOUT1 => \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\,
      T1 => '0',
      T2 => '0',
      T3 => '0',
      T4 => '0',
      TBYTEIN => tbyte_out,
      TBYTEOUT => \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\,
      TCE => '1',
      TFB => \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\,
      TQ => mem_dq_ts(5)
    );
\output_[7].oserdes_dq_.ddr.oserdes_dq_i\: unisim.vcomponents.OSERDESE2
    generic map(
      DATA_RATE_OQ => "DDR",
      DATA_RATE_TQ => "DDR",
      DATA_WIDTH => 4,
      INIT_OQ => '1',
      INIT_TQ => '1',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D1_INVERTED => '0',
      IS_D2_INVERTED => '0',
      IS_D3_INVERTED => '0',
      IS_D4_INVERTED => '0',
      IS_D5_INVERTED => '0',
      IS_D6_INVERTED => '0',
      IS_D7_INVERTED => '0',
      IS_D8_INVERTED => '0',
      IS_T1_INVERTED => '0',
      IS_T2_INVERTED => '0',
      IS_T3_INVERTED => '0',
      IS_T4_INVERTED => '0',
      SERDES_MODE => "MASTER",
      SRVAL_OQ => '1',
      SRVAL_TQ => '1',
      TBYTE_CTL => "TRUE",
      TBYTE_SRC => "FALSE",
      TRISTATE_WIDTH => 4
    )
        port map (
      CLK => oserdes_clk,
      CLKDIV => oserdes_clkdiv,
      D1 => of_dqbus(24),
      D2 => of_dqbus(25),
      D3 => of_dqbus(26),
      D4 => of_dqbus(27),
      D5 => '0',
      D6 => '0',
      D7 => '0',
      D8 => '0',
      OCE => '1',
      OFB => \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\,
      OQ => mem_dq_out(6),
      RST => po_oserdes_rst,
      SHIFTIN1 => \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\,
      SHIFTIN2 => \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\,
      SHIFTOUT1 => \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\,
      T1 => '0',
      T2 => '0',
      T3 => '0',
      T4 => '0',
      TBYTEIN => tbyte_out,
      TBYTEOUT => \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\,
      TCE => '1',
      TFB => \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\,
      TQ => mem_dq_ts(6)
    );
\output_[8].oserdes_dq_.ddr.oserdes_dq_i\: unisim.vcomponents.OSERDESE2
    generic map(
      DATA_RATE_OQ => "DDR",
      DATA_RATE_TQ => "DDR",
      DATA_WIDTH => 4,
      INIT_OQ => '1',
      INIT_TQ => '1',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D1_INVERTED => '0',
      IS_D2_INVERTED => '0',
      IS_D3_INVERTED => '0',
      IS_D4_INVERTED => '0',
      IS_D5_INVERTED => '0',
      IS_D6_INVERTED => '0',
      IS_D7_INVERTED => '0',
      IS_D8_INVERTED => '0',
      IS_T1_INVERTED => '0',
      IS_T2_INVERTED => '0',
      IS_T3_INVERTED => '0',
      IS_T4_INVERTED => '0',
      SERDES_MODE => "MASTER",
      SRVAL_OQ => '1',
      SRVAL_TQ => '1',
      TBYTE_CTL => "TRUE",
      TBYTE_SRC => "FALSE",
      TRISTATE_WIDTH => 4
    )
        port map (
      CLK => oserdes_clk,
      CLKDIV => oserdes_clkdiv,
      D1 => of_dqbus(28),
      D2 => of_dqbus(29),
      D3 => of_dqbus(30),
      D4 => of_dqbus(31),
      D5 => '0',
      D6 => '0',
      D7 => '0',
      D8 => '0',
      OCE => '1',
      OFB => \NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\,
      OQ => mem_dq_out(7),
      RST => po_oserdes_rst,
      SHIFTIN1 => \NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\,
      SHIFTIN2 => \NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\,
      SHIFTOUT1 => \NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\,
      T1 => '0',
      T2 => '0',
      T3 => '0',
      T4 => '0',
      TBYTEIN => tbyte_out,
      TBYTEOUT => \NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\,
      TCE => '1',
      TFB => \NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\,
      TQ => mem_dq_ts(7)
    );
\output_[9].oserdes_dq_.ddr.oserdes_dq_i\: unisim.vcomponents.OSERDESE2
    generic map(
      DATA_RATE_OQ => "DDR",
      DATA_RATE_TQ => "DDR",
      DATA_WIDTH => 4,
      INIT_OQ => '1',
      INIT_TQ => '1',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D1_INVERTED => '0',
      IS_D2_INVERTED => '0',
      IS_D3_INVERTED => '0',
      IS_D4_INVERTED => '0',
      IS_D5_INVERTED => '0',
      IS_D6_INVERTED => '0',
      IS_D7_INVERTED => '0',
      IS_D8_INVERTED => '0',
      IS_T1_INVERTED => '0',
      IS_T2_INVERTED => '0',
      IS_T3_INVERTED => '0',
      IS_T4_INVERTED => '0',
      SERDES_MODE => "MASTER",
      SRVAL_OQ => '1',
      SRVAL_TQ => '1',
      TBYTE_CTL => "TRUE",
      TBYTE_SRC => "FALSE",
      TRISTATE_WIDTH => 4
    )
        port map (
      CLK => oserdes_clk,
      CLKDIV => oserdes_clkdiv,
      D1 => of_dqbus(32),
      D2 => of_dqbus(33),
      D3 => of_dqbus(34),
      D4 => of_dqbus(35),
      D5 => '0',
      D6 => '0',
      D7 => '0',
      D8 => '0',
      OCE => '1',
      OFB => \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\,
      OQ => mem_dq_out(8),
      RST => po_oserdes_rst,
      SHIFTIN1 => \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\,
      SHIFTIN2 => \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\,
      SHIFTOUT1 => \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\,
      T1 => '0',
      T2 => '0',
      T3 => '0',
      T4 => '0',
      TBYTEIN => tbyte_out,
      TBYTEOUT => \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\,
      TCE => '1',
      TFB => \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\,
      TQ => mem_dq_ts(8)
    );
\slave_ts.oserdes_slave_ts\: unisim.vcomponents.OSERDESE2
    generic map(
      DATA_RATE_OQ => "DDR",
      DATA_RATE_TQ => "DDR",
      DATA_WIDTH => 4,
      INIT_OQ => '1',
      INIT_TQ => '1',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D1_INVERTED => '0',
      IS_D2_INVERTED => '0',
      IS_D3_INVERTED => '0',
      IS_D4_INVERTED => '0',
      IS_D5_INVERTED => '0',
      IS_D6_INVERTED => '0',
      IS_D7_INVERTED => '0',
      IS_D8_INVERTED => '0',
      IS_T1_INVERTED => '0',
      IS_T2_INVERTED => '0',
      IS_T3_INVERTED => '0',
      IS_T4_INVERTED => '0',
      SERDES_MODE => "MASTER",
      SRVAL_OQ => '1',
      SRVAL_TQ => '1',
      TBYTE_CTL => "TRUE",
      TBYTE_SRC => "TRUE",
      TRISTATE_WIDTH => 4
    )
        port map (
      CLK => oserdes_clk,
      CLKDIV => oserdes_clkdiv,
      D1 => '0',
      D2 => '0',
      D3 => '0',
      D4 => '0',
      D5 => '0',
      D6 => '0',
      D7 => '0',
      D8 => '0',
      OCE => '1',
      OFB => \NLW_slave_ts.oserdes_slave_ts_OFB_UNCONNECTED\,
      OQ => \NLW_slave_ts.oserdes_slave_ts_OQ_UNCONNECTED\,
      RST => po_oserdes_rst,
      SHIFTIN1 => \NLW_slave_ts.oserdes_slave_ts_SHIFTIN1_UNCONNECTED\,
      SHIFTIN2 => \NLW_slave_ts.oserdes_slave_ts_SHIFTIN2_UNCONNECTED\,
      SHIFTOUT1 => \NLW_slave_ts.oserdes_slave_ts_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_slave_ts.oserdes_slave_ts_SHIFTOUT2_UNCONNECTED\,
      T1 => DTSBUS(0),
      T2 => DTSBUS(0),
      T3 => DTSBUS(1),
      T4 => DTSBUS(1),
      TBYTEIN => tbyte_out,
      TBYTEOUT => tbyte_out,
      TCE => '1',
      TFB => \NLW_slave_ts.oserdes_slave_ts_TFB_UNCONNECTED\,
      TQ => \NLW_slave_ts.oserdes_slave_ts_TQ_UNCONNECTED\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \mig_mig_7series_v4_2_ddr_byte_group_io__parameterized0_29\ is
  port (
    out_dqs_7 : out STD_LOGIC;
    ts_dqs_7 : out STD_LOGIC;
    D2 : out STD_LOGIC_VECTOR ( 3 downto 0 );
    D3 : out STD_LOGIC_VECTOR ( 3 downto 0 );
    D4 : out STD_LOGIC_VECTOR ( 3 downto 0 );
    D5 : out STD_LOGIC_VECTOR ( 3 downto 0 );
    D6 : out STD_LOGIC_VECTOR ( 3 downto 0 );
    D7 : out STD_LOGIC_VECTOR ( 3 downto 0 );
    D8 : out STD_LOGIC_VECTOR ( 3 downto 0 );
    D9 : out STD_LOGIC_VECTOR ( 3 downto 0 );
    mem_dq_out : out STD_LOGIC_VECTOR ( 8 downto 0 );
    mem_dq_ts : out STD_LOGIC_VECTOR ( 8 downto 0 );
    idelay_ld_rst_2 : out STD_LOGIC;
    rst_r4 : out STD_LOGIC;
    oserdes_clk : in STD_LOGIC;
    oserdes_clkdiv : in STD_LOGIC;
    po_oserdes_rst : in STD_LOGIC;
    DTSBUS : in STD_LOGIC_VECTOR ( 1 downto 0 );
    oserdes_clk_delayed : in STD_LOGIC;
    DQSBUS : in STD_LOGIC_VECTOR ( 1 downto 0 );
    CTSBUS : in STD_LOGIC_VECTOR ( 0 to 0 );
    idelay_ld_rst_reg_0 : in STD_LOGIC;
    \input_[9].iserdes_dq_.iserdesdq_0\ : in STD_LOGIC;
    mem_dq_in : in STD_LOGIC_VECTOR ( 7 downto 0 );
    idelay_inc : in STD_LOGIC;
    LD0_9 : in STD_LOGIC;
    A_rst_primitives : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]\ : in STD_LOGIC;
    CLKB0_9 : in STD_LOGIC;
    iserdes_clkdiv : in STD_LOGIC;
    of_dqbus : in STD_LOGIC_VECTOR ( 35 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \mig_mig_7series_v4_2_ddr_byte_group_io__parameterized0_29\ : entity is "mig_7series_v4_2_ddr_byte_group_io";
end \mig_mig_7series_v4_2_ddr_byte_group_io__parameterized0_29\;

architecture STRUCTURE of \mig_mig_7series_v4_2_ddr_byte_group_io__parameterized0_29\ is
  signal data_in_dly_2 : STD_LOGIC;
  signal data_in_dly_3 : STD_LOGIC;
  signal data_in_dly_4 : STD_LOGIC;
  signal data_in_dly_5 : STD_LOGIC;
  signal data_in_dly_6 : STD_LOGIC;
  signal data_in_dly_7 : STD_LOGIC;
  signal data_in_dly_8 : STD_LOGIC;
  signal data_in_dly_9 : STD_LOGIC;
  signal \^idelay_ld_rst_2\ : STD_LOGIC;
  signal \idelay_ld_rst_i_1__2_n_0\ : STD_LOGIC;
  signal rst_r3_reg_srl3_n_0 : STD_LOGIC;
  signal \^rst_r4\ : STD_LOGIC;
  signal tbyte_out : STD_LOGIC;
  signal \NLW_dqs_gen.oddr_dqs_S_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_dqs_gen.oddr_dqsts_R_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[2].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal \NLW_input_[2].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[2].iserdes_dq_.iserdesdq_O_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[2].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[2].iserdes_dq_.iserdesdq_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[2].iserdes_dq_.iserdesdq_Q5_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[2].iserdes_dq_.iserdesdq_Q6_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[2].iserdes_dq_.iserdesdq_Q7_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[2].iserdes_dq_.iserdesdq_Q8_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[2].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[2].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[3].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal \NLW_input_[3].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[3].iserdes_dq_.iserdesdq_O_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[3].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[3].iserdes_dq_.iserdesdq_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[3].iserdes_dq_.iserdesdq_Q5_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[3].iserdes_dq_.iserdesdq_Q6_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[3].iserdes_dq_.iserdesdq_Q7_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[3].iserdes_dq_.iserdesdq_Q8_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[3].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[3].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[4].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal \NLW_input_[4].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[4].iserdes_dq_.iserdesdq_O_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[4].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[4].iserdes_dq_.iserdesdq_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[4].iserdes_dq_.iserdesdq_Q5_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[4].iserdes_dq_.iserdesdq_Q6_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[4].iserdes_dq_.iserdesdq_Q7_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[4].iserdes_dq_.iserdesdq_Q8_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[4].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[4].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[5].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal \NLW_input_[5].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[5].iserdes_dq_.iserdesdq_O_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[5].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[5].iserdes_dq_.iserdesdq_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[5].iserdes_dq_.iserdesdq_Q5_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[5].iserdes_dq_.iserdesdq_Q6_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[5].iserdes_dq_.iserdesdq_Q7_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[5].iserdes_dq_.iserdesdq_Q8_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[5].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[5].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[6].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal \NLW_input_[6].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[6].iserdes_dq_.iserdesdq_O_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[6].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[6].iserdes_dq_.iserdesdq_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[6].iserdes_dq_.iserdesdq_Q5_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[6].iserdes_dq_.iserdesdq_Q6_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[6].iserdes_dq_.iserdesdq_Q7_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[6].iserdes_dq_.iserdesdq_Q8_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[6].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[6].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[7].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal \NLW_input_[7].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[7].iserdes_dq_.iserdesdq_O_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[7].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[7].iserdes_dq_.iserdesdq_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[7].iserdes_dq_.iserdesdq_Q5_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[7].iserdes_dq_.iserdesdq_Q6_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[7].iserdes_dq_.iserdesdq_Q7_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[7].iserdes_dq_.iserdesdq_Q8_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[7].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[7].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[8].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal \NLW_input_[8].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[8].iserdes_dq_.iserdesdq_O_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[8].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[8].iserdes_dq_.iserdesdq_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[8].iserdes_dq_.iserdesdq_Q5_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[8].iserdes_dq_.iserdesdq_Q6_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[8].iserdes_dq_.iserdesdq_Q7_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[8].iserdes_dq_.iserdesdq_Q8_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[8].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[8].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[9].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal \NLW_input_[9].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[9].iserdes_dq_.iserdesdq_O_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[9].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[9].iserdes_dq_.iserdesdq_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[9].iserdes_dq_.iserdesdq_Q5_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[9].iserdes_dq_.iserdesdq_Q6_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[9].iserdes_dq_.iserdesdq_Q7_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[9].iserdes_dq_.iserdesdq_Q8_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[9].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[9].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_slave_ts.oserdes_slave_ts_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_slave_ts.oserdes_slave_ts_OQ_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_slave_ts.oserdes_slave_ts_SHIFTIN1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_slave_ts.oserdes_slave_ts_SHIFTIN2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_slave_ts.oserdes_slave_ts_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_slave_ts.oserdes_slave_ts_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_slave_ts.oserdes_slave_ts_TFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_slave_ts.oserdes_slave_ts_TQ_UNCONNECTED\ : STD_LOGIC;
  attribute BOX_TYPE : string;
  attribute BOX_TYPE of \dqs_gen.oddr_dqs\ : label is "PRIMITIVE";
  attribute \__SRVAL\ : string;
  attribute \__SRVAL\ of \dqs_gen.oddr_dqs\ : label is "FALSE";
  attribute BOX_TYPE of \dqs_gen.oddr_dqsts\ : label is "PRIMITIVE";
  attribute \__SRVAL\ of \dqs_gen.oddr_dqsts\ : label is "TRUE";
  attribute BOX_TYPE of \input_[2].iserdes_dq_.idelay_dq.idelaye2\ : label is "PRIMITIVE";
  attribute IODELAY_GROUP : string;
  attribute IODELAY_GROUP of \input_[2].iserdes_dq_.idelay_dq.idelaye2\ : label is "MIG_IODELAY_MIG0";
  attribute SIM_DELAY_D : integer;
  attribute SIM_DELAY_D of \input_[2].iserdes_dq_.idelay_dq.idelaye2\ : label is 0;
  attribute BOX_TYPE of \input_[2].iserdes_dq_.iserdesdq\ : label is "PRIMITIVE";
  attribute OPT_MODIFIED : string;
  attribute OPT_MODIFIED of \input_[2].iserdes_dq_.iserdesdq\ : label is "MLO";
  attribute BOX_TYPE of \input_[3].iserdes_dq_.idelay_dq.idelaye2\ : label is "PRIMITIVE";
  attribute IODELAY_GROUP of \input_[3].iserdes_dq_.idelay_dq.idelaye2\ : label is "MIG_IODELAY_MIG0";
  attribute SIM_DELAY_D of \input_[3].iserdes_dq_.idelay_dq.idelaye2\ : label is 0;
  attribute BOX_TYPE of \input_[3].iserdes_dq_.iserdesdq\ : label is "PRIMITIVE";
  attribute OPT_MODIFIED of \input_[3].iserdes_dq_.iserdesdq\ : label is "MLO";
  attribute BOX_TYPE of \input_[4].iserdes_dq_.idelay_dq.idelaye2\ : label is "PRIMITIVE";
  attribute IODELAY_GROUP of \input_[4].iserdes_dq_.idelay_dq.idelaye2\ : label is "MIG_IODELAY_MIG0";
  attribute SIM_DELAY_D of \input_[4].iserdes_dq_.idelay_dq.idelaye2\ : label is 0;
  attribute BOX_TYPE of \input_[4].iserdes_dq_.iserdesdq\ : label is "PRIMITIVE";
  attribute OPT_MODIFIED of \input_[4].iserdes_dq_.iserdesdq\ : label is "MLO";
  attribute BOX_TYPE of \input_[5].iserdes_dq_.idelay_dq.idelaye2\ : label is "PRIMITIVE";
  attribute IODELAY_GROUP of \input_[5].iserdes_dq_.idelay_dq.idelaye2\ : label is "MIG_IODELAY_MIG0";
  attribute SIM_DELAY_D of \input_[5].iserdes_dq_.idelay_dq.idelaye2\ : label is 0;
  attribute BOX_TYPE of \input_[5].iserdes_dq_.iserdesdq\ : label is "PRIMITIVE";
  attribute OPT_MODIFIED of \input_[5].iserdes_dq_.iserdesdq\ : label is "MLO";
  attribute BOX_TYPE of \input_[6].iserdes_dq_.idelay_dq.idelaye2\ : label is "PRIMITIVE";
  attribute IODELAY_GROUP of \input_[6].iserdes_dq_.idelay_dq.idelaye2\ : label is "MIG_IODELAY_MIG0";
  attribute SIM_DELAY_D of \input_[6].iserdes_dq_.idelay_dq.idelaye2\ : label is 0;
  attribute BOX_TYPE of \input_[6].iserdes_dq_.iserdesdq\ : label is "PRIMITIVE";
  attribute OPT_MODIFIED of \input_[6].iserdes_dq_.iserdesdq\ : label is "MLO";
  attribute BOX_TYPE of \input_[7].iserdes_dq_.idelay_dq.idelaye2\ : label is "PRIMITIVE";
  attribute IODELAY_GROUP of \input_[7].iserdes_dq_.idelay_dq.idelaye2\ : label is "MIG_IODELAY_MIG0";
  attribute SIM_DELAY_D of \input_[7].iserdes_dq_.idelay_dq.idelaye2\ : label is 0;
  attribute BOX_TYPE of \input_[7].iserdes_dq_.iserdesdq\ : label is "PRIMITIVE";
  attribute OPT_MODIFIED of \input_[7].iserdes_dq_.iserdesdq\ : label is "MLO";
  attribute BOX_TYPE of \input_[8].iserdes_dq_.idelay_dq.idelaye2\ : label is "PRIMITIVE";
  attribute IODELAY_GROUP of \input_[8].iserdes_dq_.idelay_dq.idelaye2\ : label is "MIG_IODELAY_MIG0";
  attribute SIM_DELAY_D of \input_[8].iserdes_dq_.idelay_dq.idelaye2\ : label is 0;
  attribute BOX_TYPE of \input_[8].iserdes_dq_.iserdesdq\ : label is "PRIMITIVE";
  attribute OPT_MODIFIED of \input_[8].iserdes_dq_.iserdesdq\ : label is "MLO";
  attribute BOX_TYPE of \input_[9].iserdes_dq_.idelay_dq.idelaye2\ : label is "PRIMITIVE";
  attribute IODELAY_GROUP of \input_[9].iserdes_dq_.idelay_dq.idelaye2\ : label is "MIG_IODELAY_MIG0";
  attribute SIM_DELAY_D of \input_[9].iserdes_dq_.idelay_dq.idelaye2\ : label is 0;
  attribute BOX_TYPE of \input_[9].iserdes_dq_.iserdesdq\ : label is "PRIMITIVE";
  attribute OPT_MODIFIED of \input_[9].iserdes_dq_.iserdesdq\ : label is "MLO";
  attribute BOX_TYPE of \output_[1].oserdes_dq_.ddr.oserdes_dq_i\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \output_[2].oserdes_dq_.ddr.oserdes_dq_i\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \output_[3].oserdes_dq_.ddr.oserdes_dq_i\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \output_[4].oserdes_dq_.ddr.oserdes_dq_i\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \output_[5].oserdes_dq_.ddr.oserdes_dq_i\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \output_[6].oserdes_dq_.ddr.oserdes_dq_i\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \output_[7].oserdes_dq_.ddr.oserdes_dq_i\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \output_[8].oserdes_dq_.ddr.oserdes_dq_i\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \output_[9].oserdes_dq_.ddr.oserdes_dq_i\ : label is "PRIMITIVE";
  attribute srl_name : string;
  attribute srl_name of rst_r3_reg_srl3 : label is "\u_mig_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/rst_r3_reg_srl3 ";
  attribute BOX_TYPE of \slave_ts.oserdes_slave_ts\ : label is "PRIMITIVE";
begin
  idelay_ld_rst_2 <= \^idelay_ld_rst_2\;
  rst_r4 <= \^rst_r4\;
\dqs_gen.oddr_dqs\: unisim.vcomponents.ODDR
    generic map(
      DDR_CLK_EDGE => "SAME_EDGE",
      INIT => '0',
      IS_C_INVERTED => '0',
      IS_D1_INVERTED => '0',
      IS_D2_INVERTED => '0',
      SRTYPE => "SYNC"
    )
        port map (
      C => oserdes_clk_delayed,
      CE => '1',
      D1 => DQSBUS(0),
      D2 => DQSBUS(1),
      Q => out_dqs_7,
      R => '0',
      S => \NLW_dqs_gen.oddr_dqs_S_UNCONNECTED\
    );
\dqs_gen.oddr_dqsts\: unisim.vcomponents.ODDR
    generic map(
      DDR_CLK_EDGE => "SAME_EDGE",
      INIT => '0',
      IS_C_INVERTED => '0',
      IS_D1_INVERTED => '0',
      IS_D2_INVERTED => '0',
      SRTYPE => "SYNC"
    )
        port map (
      C => oserdes_clk_delayed,
      CE => '1',
      D1 => CTSBUS(0),
      D2 => CTSBUS(0),
      Q => ts_dqs_7,
      R => \NLW_dqs_gen.oddr_dqsts_R_UNCONNECTED\,
      S => '0'
    );
\idelay_ld_rst_i_1__2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \^idelay_ld_rst_2\,
      I1 => \^rst_r4\,
      O => \idelay_ld_rst_i_1__2_n_0\
    );
idelay_ld_rst_reg: unisim.vcomponents.FDSE
     port map (
      C => idelay_ld_rst_reg_0,
      CE => '1',
      D => \idelay_ld_rst_i_1__2_n_0\,
      Q => \^idelay_ld_rst_2\,
      S => A_rst_primitives
    );
\input_[2].iserdes_dq_.idelay_dq.idelaye2\: unisim.vcomponents.IDELAYE2
    generic map(
      CINVCTRL_SEL => "FALSE",
      DELAY_SRC => "IDATAIN",
      HIGH_PERFORMANCE_MODE => "TRUE",
      IDELAY_TYPE => "VARIABLE",
      IDELAY_VALUE => 0,
      IS_C_INVERTED => '0',
      IS_DATAIN_INVERTED => '0',
      IS_IDATAIN_INVERTED => '0',
      PIPE_SEL => "FALSE",
      REFCLK_FREQUENCY => 200.000000,
      SIGNAL_PATTERN => "DATA"
    )
        port map (
      C => idelay_ld_rst_reg_0,
      CE => \input_[9].iserdes_dq_.iserdesdq_0\,
      CINVCTRL => '0',
      CNTVALUEIN(4 downto 0) => B"00000",
      CNTVALUEOUT(4 downto 0) => \NLW_input_[2].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED\(4 downto 0),
      DATAIN => '0',
      DATAOUT => data_in_dly_2,
      IDATAIN => mem_dq_in(0),
      INC => idelay_inc,
      LD => LD0_9,
      LDPIPEEN => '0',
      REGRST => A_rst_primitives
    );
\input_[2].iserdes_dq_.iserdesdq\: unisim.vcomponents.ISERDESE2
    generic map(
      DATA_RATE => "DDR",
      DATA_WIDTH => 4,
      DYN_CLKDIV_INV_EN => "FALSE",
      DYN_CLK_INV_EN => "FALSE",
      INIT_Q1 => '0',
      INIT_Q2 => '0',
      INIT_Q3 => '0',
      INIT_Q4 => '0',
      INTERFACE_TYPE => "MEMORY_DDR3",
      IOBDELAY => "IFD",
      IS_CLKB_INVERTED => '1',
      IS_CLKDIVP_INVERTED => '0',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D_INVERTED => '0',
      IS_OCLKB_INVERTED => '0',
      IS_OCLK_INVERTED => '0',
      NUM_CE => 2,
      OFB_USED => "FALSE",
      SERDES_MODE => "MASTER",
      SRVAL_Q1 => '0',
      SRVAL_Q2 => '0',
      SRVAL_Q3 => '0',
      SRVAL_Q4 => '0'
    )
        port map (
      BITSLIP => '0',
      CE1 => '1',
      CE2 => '1',
      CLK => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]\,
      CLKB => CLKB0_9,
      CLKDIV => \NLW_input_[2].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED\,
      CLKDIVP => iserdes_clkdiv,
      D => mem_dq_in(0),
      DDLY => data_in_dly_2,
      DYNCLKDIVSEL => '0',
      DYNCLKSEL => '0',
      O => \NLW_input_[2].iserdes_dq_.iserdesdq_O_UNCONNECTED\,
      OCLK => oserdes_clk,
      OCLKB => \NLW_input_[2].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED\,
      OFB => \NLW_input_[2].iserdes_dq_.iserdesdq_OFB_UNCONNECTED\,
      Q1 => D2(3),
      Q2 => D2(2),
      Q3 => D2(1),
      Q4 => D2(0),
      Q5 => \NLW_input_[2].iserdes_dq_.iserdesdq_Q5_UNCONNECTED\,
      Q6 => \NLW_input_[2].iserdes_dq_.iserdesdq_Q6_UNCONNECTED\,
      Q7 => \NLW_input_[2].iserdes_dq_.iserdesdq_Q7_UNCONNECTED\,
      Q8 => \NLW_input_[2].iserdes_dq_.iserdesdq_Q8_UNCONNECTED\,
      RST => '0',
      SHIFTIN1 => '0',
      SHIFTIN2 => '0',
      SHIFTOUT1 => \NLW_input_[2].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_input_[2].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED\
    );
\input_[3].iserdes_dq_.idelay_dq.idelaye2\: unisim.vcomponents.IDELAYE2
    generic map(
      CINVCTRL_SEL => "FALSE",
      DELAY_SRC => "IDATAIN",
      HIGH_PERFORMANCE_MODE => "TRUE",
      IDELAY_TYPE => "VARIABLE",
      IDELAY_VALUE => 0,
      IS_C_INVERTED => '0',
      IS_DATAIN_INVERTED => '0',
      IS_IDATAIN_INVERTED => '0',
      PIPE_SEL => "FALSE",
      REFCLK_FREQUENCY => 200.000000,
      SIGNAL_PATTERN => "DATA"
    )
        port map (
      C => idelay_ld_rst_reg_0,
      CE => \input_[9].iserdes_dq_.iserdesdq_0\,
      CINVCTRL => '0',
      CNTVALUEIN(4 downto 0) => B"00000",
      CNTVALUEOUT(4 downto 0) => \NLW_input_[3].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED\(4 downto 0),
      DATAIN => '0',
      DATAOUT => data_in_dly_3,
      IDATAIN => mem_dq_in(1),
      INC => idelay_inc,
      LD => LD0_9,
      LDPIPEEN => '0',
      REGRST => A_rst_primitives
    );
\input_[3].iserdes_dq_.iserdesdq\: unisim.vcomponents.ISERDESE2
    generic map(
      DATA_RATE => "DDR",
      DATA_WIDTH => 4,
      DYN_CLKDIV_INV_EN => "FALSE",
      DYN_CLK_INV_EN => "FALSE",
      INIT_Q1 => '0',
      INIT_Q2 => '0',
      INIT_Q3 => '0',
      INIT_Q4 => '0',
      INTERFACE_TYPE => "MEMORY_DDR3",
      IOBDELAY => "IFD",
      IS_CLKB_INVERTED => '1',
      IS_CLKDIVP_INVERTED => '0',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D_INVERTED => '0',
      IS_OCLKB_INVERTED => '0',
      IS_OCLK_INVERTED => '0',
      NUM_CE => 2,
      OFB_USED => "FALSE",
      SERDES_MODE => "MASTER",
      SRVAL_Q1 => '0',
      SRVAL_Q2 => '0',
      SRVAL_Q3 => '0',
      SRVAL_Q4 => '0'
    )
        port map (
      BITSLIP => '0',
      CE1 => '1',
      CE2 => '1',
      CLK => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]\,
      CLKB => CLKB0_9,
      CLKDIV => \NLW_input_[3].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED\,
      CLKDIVP => iserdes_clkdiv,
      D => mem_dq_in(1),
      DDLY => data_in_dly_3,
      DYNCLKDIVSEL => '0',
      DYNCLKSEL => '0',
      O => \NLW_input_[3].iserdes_dq_.iserdesdq_O_UNCONNECTED\,
      OCLK => oserdes_clk,
      OCLKB => \NLW_input_[3].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED\,
      OFB => \NLW_input_[3].iserdes_dq_.iserdesdq_OFB_UNCONNECTED\,
      Q1 => D3(3),
      Q2 => D3(2),
      Q3 => D3(1),
      Q4 => D3(0),
      Q5 => \NLW_input_[3].iserdes_dq_.iserdesdq_Q5_UNCONNECTED\,
      Q6 => \NLW_input_[3].iserdes_dq_.iserdesdq_Q6_UNCONNECTED\,
      Q7 => \NLW_input_[3].iserdes_dq_.iserdesdq_Q7_UNCONNECTED\,
      Q8 => \NLW_input_[3].iserdes_dq_.iserdesdq_Q8_UNCONNECTED\,
      RST => '0',
      SHIFTIN1 => '0',
      SHIFTIN2 => '0',
      SHIFTOUT1 => \NLW_input_[3].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_input_[3].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED\
    );
\input_[4].iserdes_dq_.idelay_dq.idelaye2\: unisim.vcomponents.IDELAYE2
    generic map(
      CINVCTRL_SEL => "FALSE",
      DELAY_SRC => "IDATAIN",
      HIGH_PERFORMANCE_MODE => "TRUE",
      IDELAY_TYPE => "VARIABLE",
      IDELAY_VALUE => 0,
      IS_C_INVERTED => '0',
      IS_DATAIN_INVERTED => '0',
      IS_IDATAIN_INVERTED => '0',
      PIPE_SEL => "FALSE",
      REFCLK_FREQUENCY => 200.000000,
      SIGNAL_PATTERN => "DATA"
    )
        port map (
      C => idelay_ld_rst_reg_0,
      CE => \input_[9].iserdes_dq_.iserdesdq_0\,
      CINVCTRL => '0',
      CNTVALUEIN(4 downto 0) => B"00000",
      CNTVALUEOUT(4 downto 0) => \NLW_input_[4].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED\(4 downto 0),
      DATAIN => '0',
      DATAOUT => data_in_dly_4,
      IDATAIN => mem_dq_in(2),
      INC => idelay_inc,
      LD => LD0_9,
      LDPIPEEN => '0',
      REGRST => A_rst_primitives
    );
\input_[4].iserdes_dq_.iserdesdq\: unisim.vcomponents.ISERDESE2
    generic map(
      DATA_RATE => "DDR",
      DATA_WIDTH => 4,
      DYN_CLKDIV_INV_EN => "FALSE",
      DYN_CLK_INV_EN => "FALSE",
      INIT_Q1 => '0',
      INIT_Q2 => '0',
      INIT_Q3 => '0',
      INIT_Q4 => '0',
      INTERFACE_TYPE => "MEMORY_DDR3",
      IOBDELAY => "IFD",
      IS_CLKB_INVERTED => '1',
      IS_CLKDIVP_INVERTED => '0',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D_INVERTED => '0',
      IS_OCLKB_INVERTED => '0',
      IS_OCLK_INVERTED => '0',
      NUM_CE => 2,
      OFB_USED => "FALSE",
      SERDES_MODE => "MASTER",
      SRVAL_Q1 => '0',
      SRVAL_Q2 => '0',
      SRVAL_Q3 => '0',
      SRVAL_Q4 => '0'
    )
        port map (
      BITSLIP => '0',
      CE1 => '1',
      CE2 => '1',
      CLK => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]\,
      CLKB => CLKB0_9,
      CLKDIV => \NLW_input_[4].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED\,
      CLKDIVP => iserdes_clkdiv,
      D => mem_dq_in(2),
      DDLY => data_in_dly_4,
      DYNCLKDIVSEL => '0',
      DYNCLKSEL => '0',
      O => \NLW_input_[4].iserdes_dq_.iserdesdq_O_UNCONNECTED\,
      OCLK => oserdes_clk,
      OCLKB => \NLW_input_[4].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED\,
      OFB => \NLW_input_[4].iserdes_dq_.iserdesdq_OFB_UNCONNECTED\,
      Q1 => D4(3),
      Q2 => D4(2),
      Q3 => D4(1),
      Q4 => D4(0),
      Q5 => \NLW_input_[4].iserdes_dq_.iserdesdq_Q5_UNCONNECTED\,
      Q6 => \NLW_input_[4].iserdes_dq_.iserdesdq_Q6_UNCONNECTED\,
      Q7 => \NLW_input_[4].iserdes_dq_.iserdesdq_Q7_UNCONNECTED\,
      Q8 => \NLW_input_[4].iserdes_dq_.iserdesdq_Q8_UNCONNECTED\,
      RST => '0',
      SHIFTIN1 => '0',
      SHIFTIN2 => '0',
      SHIFTOUT1 => \NLW_input_[4].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_input_[4].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED\
    );
\input_[5].iserdes_dq_.idelay_dq.idelaye2\: unisim.vcomponents.IDELAYE2
    generic map(
      CINVCTRL_SEL => "FALSE",
      DELAY_SRC => "IDATAIN",
      HIGH_PERFORMANCE_MODE => "TRUE",
      IDELAY_TYPE => "VARIABLE",
      IDELAY_VALUE => 0,
      IS_C_INVERTED => '0',
      IS_DATAIN_INVERTED => '0',
      IS_IDATAIN_INVERTED => '0',
      PIPE_SEL => "FALSE",
      REFCLK_FREQUENCY => 200.000000,
      SIGNAL_PATTERN => "DATA"
    )
        port map (
      C => idelay_ld_rst_reg_0,
      CE => \input_[9].iserdes_dq_.iserdesdq_0\,
      CINVCTRL => '0',
      CNTVALUEIN(4 downto 0) => B"00000",
      CNTVALUEOUT(4 downto 0) => \NLW_input_[5].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED\(4 downto 0),
      DATAIN => '0',
      DATAOUT => data_in_dly_5,
      IDATAIN => mem_dq_in(3),
      INC => idelay_inc,
      LD => LD0_9,
      LDPIPEEN => '0',
      REGRST => A_rst_primitives
    );
\input_[5].iserdes_dq_.iserdesdq\: unisim.vcomponents.ISERDESE2
    generic map(
      DATA_RATE => "DDR",
      DATA_WIDTH => 4,
      DYN_CLKDIV_INV_EN => "FALSE",
      DYN_CLK_INV_EN => "FALSE",
      INIT_Q1 => '0',
      INIT_Q2 => '0',
      INIT_Q3 => '0',
      INIT_Q4 => '0',
      INTERFACE_TYPE => "MEMORY_DDR3",
      IOBDELAY => "IFD",
      IS_CLKB_INVERTED => '1',
      IS_CLKDIVP_INVERTED => '0',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D_INVERTED => '0',
      IS_OCLKB_INVERTED => '0',
      IS_OCLK_INVERTED => '0',
      NUM_CE => 2,
      OFB_USED => "FALSE",
      SERDES_MODE => "MASTER",
      SRVAL_Q1 => '0',
      SRVAL_Q2 => '0',
      SRVAL_Q3 => '0',
      SRVAL_Q4 => '0'
    )
        port map (
      BITSLIP => '0',
      CE1 => '1',
      CE2 => '1',
      CLK => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]\,
      CLKB => CLKB0_9,
      CLKDIV => \NLW_input_[5].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED\,
      CLKDIVP => iserdes_clkdiv,
      D => mem_dq_in(3),
      DDLY => data_in_dly_5,
      DYNCLKDIVSEL => '0',
      DYNCLKSEL => '0',
      O => \NLW_input_[5].iserdes_dq_.iserdesdq_O_UNCONNECTED\,
      OCLK => oserdes_clk,
      OCLKB => \NLW_input_[5].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED\,
      OFB => \NLW_input_[5].iserdes_dq_.iserdesdq_OFB_UNCONNECTED\,
      Q1 => D5(3),
      Q2 => D5(2),
      Q3 => D5(1),
      Q4 => D5(0),
      Q5 => \NLW_input_[5].iserdes_dq_.iserdesdq_Q5_UNCONNECTED\,
      Q6 => \NLW_input_[5].iserdes_dq_.iserdesdq_Q6_UNCONNECTED\,
      Q7 => \NLW_input_[5].iserdes_dq_.iserdesdq_Q7_UNCONNECTED\,
      Q8 => \NLW_input_[5].iserdes_dq_.iserdesdq_Q8_UNCONNECTED\,
      RST => '0',
      SHIFTIN1 => '0',
      SHIFTIN2 => '0',
      SHIFTOUT1 => \NLW_input_[5].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_input_[5].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED\
    );
\input_[6].iserdes_dq_.idelay_dq.idelaye2\: unisim.vcomponents.IDELAYE2
    generic map(
      CINVCTRL_SEL => "FALSE",
      DELAY_SRC => "IDATAIN",
      HIGH_PERFORMANCE_MODE => "TRUE",
      IDELAY_TYPE => "VARIABLE",
      IDELAY_VALUE => 0,
      IS_C_INVERTED => '0',
      IS_DATAIN_INVERTED => '0',
      IS_IDATAIN_INVERTED => '0',
      PIPE_SEL => "FALSE",
      REFCLK_FREQUENCY => 200.000000,
      SIGNAL_PATTERN => "DATA"
    )
        port map (
      C => idelay_ld_rst_reg_0,
      CE => \input_[9].iserdes_dq_.iserdesdq_0\,
      CINVCTRL => '0',
      CNTVALUEIN(4 downto 0) => B"00000",
      CNTVALUEOUT(4 downto 0) => \NLW_input_[6].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED\(4 downto 0),
      DATAIN => '0',
      DATAOUT => data_in_dly_6,
      IDATAIN => mem_dq_in(4),
      INC => idelay_inc,
      LD => LD0_9,
      LDPIPEEN => '0',
      REGRST => A_rst_primitives
    );
\input_[6].iserdes_dq_.iserdesdq\: unisim.vcomponents.ISERDESE2
    generic map(
      DATA_RATE => "DDR",
      DATA_WIDTH => 4,
      DYN_CLKDIV_INV_EN => "FALSE",
      DYN_CLK_INV_EN => "FALSE",
      INIT_Q1 => '0',
      INIT_Q2 => '0',
      INIT_Q3 => '0',
      INIT_Q4 => '0',
      INTERFACE_TYPE => "MEMORY_DDR3",
      IOBDELAY => "IFD",
      IS_CLKB_INVERTED => '1',
      IS_CLKDIVP_INVERTED => '0',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D_INVERTED => '0',
      IS_OCLKB_INVERTED => '0',
      IS_OCLK_INVERTED => '0',
      NUM_CE => 2,
      OFB_USED => "FALSE",
      SERDES_MODE => "MASTER",
      SRVAL_Q1 => '0',
      SRVAL_Q2 => '0',
      SRVAL_Q3 => '0',
      SRVAL_Q4 => '0'
    )
        port map (
      BITSLIP => '0',
      CE1 => '1',
      CE2 => '1',
      CLK => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]\,
      CLKB => CLKB0_9,
      CLKDIV => \NLW_input_[6].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED\,
      CLKDIVP => iserdes_clkdiv,
      D => mem_dq_in(4),
      DDLY => data_in_dly_6,
      DYNCLKDIVSEL => '0',
      DYNCLKSEL => '0',
      O => \NLW_input_[6].iserdes_dq_.iserdesdq_O_UNCONNECTED\,
      OCLK => oserdes_clk,
      OCLKB => \NLW_input_[6].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED\,
      OFB => \NLW_input_[6].iserdes_dq_.iserdesdq_OFB_UNCONNECTED\,
      Q1 => D6(3),
      Q2 => D6(2),
      Q3 => D6(1),
      Q4 => D6(0),
      Q5 => \NLW_input_[6].iserdes_dq_.iserdesdq_Q5_UNCONNECTED\,
      Q6 => \NLW_input_[6].iserdes_dq_.iserdesdq_Q6_UNCONNECTED\,
      Q7 => \NLW_input_[6].iserdes_dq_.iserdesdq_Q7_UNCONNECTED\,
      Q8 => \NLW_input_[6].iserdes_dq_.iserdesdq_Q8_UNCONNECTED\,
      RST => '0',
      SHIFTIN1 => '0',
      SHIFTIN2 => '0',
      SHIFTOUT1 => \NLW_input_[6].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_input_[6].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED\
    );
\input_[7].iserdes_dq_.idelay_dq.idelaye2\: unisim.vcomponents.IDELAYE2
    generic map(
      CINVCTRL_SEL => "FALSE",
      DELAY_SRC => "IDATAIN",
      HIGH_PERFORMANCE_MODE => "TRUE",
      IDELAY_TYPE => "VARIABLE",
      IDELAY_VALUE => 0,
      IS_C_INVERTED => '0',
      IS_DATAIN_INVERTED => '0',
      IS_IDATAIN_INVERTED => '0',
      PIPE_SEL => "FALSE",
      REFCLK_FREQUENCY => 200.000000,
      SIGNAL_PATTERN => "DATA"
    )
        port map (
      C => idelay_ld_rst_reg_0,
      CE => \input_[9].iserdes_dq_.iserdesdq_0\,
      CINVCTRL => '0',
      CNTVALUEIN(4 downto 0) => B"00000",
      CNTVALUEOUT(4 downto 0) => \NLW_input_[7].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED\(4 downto 0),
      DATAIN => '0',
      DATAOUT => data_in_dly_7,
      IDATAIN => mem_dq_in(5),
      INC => idelay_inc,
      LD => LD0_9,
      LDPIPEEN => '0',
      REGRST => A_rst_primitives
    );
\input_[7].iserdes_dq_.iserdesdq\: unisim.vcomponents.ISERDESE2
    generic map(
      DATA_RATE => "DDR",
      DATA_WIDTH => 4,
      DYN_CLKDIV_INV_EN => "FALSE",
      DYN_CLK_INV_EN => "FALSE",
      INIT_Q1 => '0',
      INIT_Q2 => '0',
      INIT_Q3 => '0',
      INIT_Q4 => '0',
      INTERFACE_TYPE => "MEMORY_DDR3",
      IOBDELAY => "IFD",
      IS_CLKB_INVERTED => '1',
      IS_CLKDIVP_INVERTED => '0',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D_INVERTED => '0',
      IS_OCLKB_INVERTED => '0',
      IS_OCLK_INVERTED => '0',
      NUM_CE => 2,
      OFB_USED => "FALSE",
      SERDES_MODE => "MASTER",
      SRVAL_Q1 => '0',
      SRVAL_Q2 => '0',
      SRVAL_Q3 => '0',
      SRVAL_Q4 => '0'
    )
        port map (
      BITSLIP => '0',
      CE1 => '1',
      CE2 => '1',
      CLK => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]\,
      CLKB => CLKB0_9,
      CLKDIV => \NLW_input_[7].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED\,
      CLKDIVP => iserdes_clkdiv,
      D => mem_dq_in(5),
      DDLY => data_in_dly_7,
      DYNCLKDIVSEL => '0',
      DYNCLKSEL => '0',
      O => \NLW_input_[7].iserdes_dq_.iserdesdq_O_UNCONNECTED\,
      OCLK => oserdes_clk,
      OCLKB => \NLW_input_[7].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED\,
      OFB => \NLW_input_[7].iserdes_dq_.iserdesdq_OFB_UNCONNECTED\,
      Q1 => D7(3),
      Q2 => D7(2),
      Q3 => D7(1),
      Q4 => D7(0),
      Q5 => \NLW_input_[7].iserdes_dq_.iserdesdq_Q5_UNCONNECTED\,
      Q6 => \NLW_input_[7].iserdes_dq_.iserdesdq_Q6_UNCONNECTED\,
      Q7 => \NLW_input_[7].iserdes_dq_.iserdesdq_Q7_UNCONNECTED\,
      Q8 => \NLW_input_[7].iserdes_dq_.iserdesdq_Q8_UNCONNECTED\,
      RST => '0',
      SHIFTIN1 => '0',
      SHIFTIN2 => '0',
      SHIFTOUT1 => \NLW_input_[7].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_input_[7].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED\
    );
\input_[8].iserdes_dq_.idelay_dq.idelaye2\: unisim.vcomponents.IDELAYE2
    generic map(
      CINVCTRL_SEL => "FALSE",
      DELAY_SRC => "IDATAIN",
      HIGH_PERFORMANCE_MODE => "TRUE",
      IDELAY_TYPE => "VARIABLE",
      IDELAY_VALUE => 0,
      IS_C_INVERTED => '0',
      IS_DATAIN_INVERTED => '0',
      IS_IDATAIN_INVERTED => '0',
      PIPE_SEL => "FALSE",
      REFCLK_FREQUENCY => 200.000000,
      SIGNAL_PATTERN => "DATA"
    )
        port map (
      C => idelay_ld_rst_reg_0,
      CE => \input_[9].iserdes_dq_.iserdesdq_0\,
      CINVCTRL => '0',
      CNTVALUEIN(4 downto 0) => B"00000",
      CNTVALUEOUT(4 downto 0) => \NLW_input_[8].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED\(4 downto 0),
      DATAIN => '0',
      DATAOUT => data_in_dly_8,
      IDATAIN => mem_dq_in(6),
      INC => idelay_inc,
      LD => LD0_9,
      LDPIPEEN => '0',
      REGRST => A_rst_primitives
    );
\input_[8].iserdes_dq_.iserdesdq\: unisim.vcomponents.ISERDESE2
    generic map(
      DATA_RATE => "DDR",
      DATA_WIDTH => 4,
      DYN_CLKDIV_INV_EN => "FALSE",
      DYN_CLK_INV_EN => "FALSE",
      INIT_Q1 => '0',
      INIT_Q2 => '0',
      INIT_Q3 => '0',
      INIT_Q4 => '0',
      INTERFACE_TYPE => "MEMORY_DDR3",
      IOBDELAY => "IFD",
      IS_CLKB_INVERTED => '1',
      IS_CLKDIVP_INVERTED => '0',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D_INVERTED => '0',
      IS_OCLKB_INVERTED => '0',
      IS_OCLK_INVERTED => '0',
      NUM_CE => 2,
      OFB_USED => "FALSE",
      SERDES_MODE => "MASTER",
      SRVAL_Q1 => '0',
      SRVAL_Q2 => '0',
      SRVAL_Q3 => '0',
      SRVAL_Q4 => '0'
    )
        port map (
      BITSLIP => '0',
      CE1 => '1',
      CE2 => '1',
      CLK => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]\,
      CLKB => CLKB0_9,
      CLKDIV => \NLW_input_[8].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED\,
      CLKDIVP => iserdes_clkdiv,
      D => mem_dq_in(6),
      DDLY => data_in_dly_8,
      DYNCLKDIVSEL => '0',
      DYNCLKSEL => '0',
      O => \NLW_input_[8].iserdes_dq_.iserdesdq_O_UNCONNECTED\,
      OCLK => oserdes_clk,
      OCLKB => \NLW_input_[8].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED\,
      OFB => \NLW_input_[8].iserdes_dq_.iserdesdq_OFB_UNCONNECTED\,
      Q1 => D8(3),
      Q2 => D8(2),
      Q3 => D8(1),
      Q4 => D8(0),
      Q5 => \NLW_input_[8].iserdes_dq_.iserdesdq_Q5_UNCONNECTED\,
      Q6 => \NLW_input_[8].iserdes_dq_.iserdesdq_Q6_UNCONNECTED\,
      Q7 => \NLW_input_[8].iserdes_dq_.iserdesdq_Q7_UNCONNECTED\,
      Q8 => \NLW_input_[8].iserdes_dq_.iserdesdq_Q8_UNCONNECTED\,
      RST => '0',
      SHIFTIN1 => '0',
      SHIFTIN2 => '0',
      SHIFTOUT1 => \NLW_input_[8].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_input_[8].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED\
    );
\input_[9].iserdes_dq_.idelay_dq.idelaye2\: unisim.vcomponents.IDELAYE2
    generic map(
      CINVCTRL_SEL => "FALSE",
      DELAY_SRC => "IDATAIN",
      HIGH_PERFORMANCE_MODE => "TRUE",
      IDELAY_TYPE => "VARIABLE",
      IDELAY_VALUE => 0,
      IS_C_INVERTED => '0',
      IS_DATAIN_INVERTED => '0',
      IS_IDATAIN_INVERTED => '0',
      PIPE_SEL => "FALSE",
      REFCLK_FREQUENCY => 200.000000,
      SIGNAL_PATTERN => "DATA"
    )
        port map (
      C => idelay_ld_rst_reg_0,
      CE => \input_[9].iserdes_dq_.iserdesdq_0\,
      CINVCTRL => '0',
      CNTVALUEIN(4 downto 0) => B"00000",
      CNTVALUEOUT(4 downto 0) => \NLW_input_[9].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED\(4 downto 0),
      DATAIN => '0',
      DATAOUT => data_in_dly_9,
      IDATAIN => mem_dq_in(7),
      INC => idelay_inc,
      LD => LD0_9,
      LDPIPEEN => '0',
      REGRST => A_rst_primitives
    );
\input_[9].iserdes_dq_.iserdesdq\: unisim.vcomponents.ISERDESE2
    generic map(
      DATA_RATE => "DDR",
      DATA_WIDTH => 4,
      DYN_CLKDIV_INV_EN => "FALSE",
      DYN_CLK_INV_EN => "FALSE",
      INIT_Q1 => '0',
      INIT_Q2 => '0',
      INIT_Q3 => '0',
      INIT_Q4 => '0',
      INTERFACE_TYPE => "MEMORY_DDR3",
      IOBDELAY => "IFD",
      IS_CLKB_INVERTED => '1',
      IS_CLKDIVP_INVERTED => '0',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D_INVERTED => '0',
      IS_OCLKB_INVERTED => '0',
      IS_OCLK_INVERTED => '0',
      NUM_CE => 2,
      OFB_USED => "FALSE",
      SERDES_MODE => "MASTER",
      SRVAL_Q1 => '0',
      SRVAL_Q2 => '0',
      SRVAL_Q3 => '0',
      SRVAL_Q4 => '0'
    )
        port map (
      BITSLIP => '0',
      CE1 => '1',
      CE2 => '1',
      CLK => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]\,
      CLKB => CLKB0_9,
      CLKDIV => \NLW_input_[9].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED\,
      CLKDIVP => iserdes_clkdiv,
      D => mem_dq_in(7),
      DDLY => data_in_dly_9,
      DYNCLKDIVSEL => '0',
      DYNCLKSEL => '0',
      O => \NLW_input_[9].iserdes_dq_.iserdesdq_O_UNCONNECTED\,
      OCLK => oserdes_clk,
      OCLKB => \NLW_input_[9].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED\,
      OFB => \NLW_input_[9].iserdes_dq_.iserdesdq_OFB_UNCONNECTED\,
      Q1 => D9(3),
      Q2 => D9(2),
      Q3 => D9(1),
      Q4 => D9(0),
      Q5 => \NLW_input_[9].iserdes_dq_.iserdesdq_Q5_UNCONNECTED\,
      Q6 => \NLW_input_[9].iserdes_dq_.iserdesdq_Q6_UNCONNECTED\,
      Q7 => \NLW_input_[9].iserdes_dq_.iserdesdq_Q7_UNCONNECTED\,
      Q8 => \NLW_input_[9].iserdes_dq_.iserdesdq_Q8_UNCONNECTED\,
      RST => '0',
      SHIFTIN1 => '0',
      SHIFTIN2 => '0',
      SHIFTOUT1 => \NLW_input_[9].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_input_[9].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED\
    );
\output_[1].oserdes_dq_.ddr.oserdes_dq_i\: unisim.vcomponents.OSERDESE2
    generic map(
      DATA_RATE_OQ => "DDR",
      DATA_RATE_TQ => "DDR",
      DATA_WIDTH => 4,
      INIT_OQ => '1',
      INIT_TQ => '1',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D1_INVERTED => '0',
      IS_D2_INVERTED => '0',
      IS_D3_INVERTED => '0',
      IS_D4_INVERTED => '0',
      IS_D5_INVERTED => '0',
      IS_D6_INVERTED => '0',
      IS_D7_INVERTED => '0',
      IS_D8_INVERTED => '0',
      IS_T1_INVERTED => '0',
      IS_T2_INVERTED => '0',
      IS_T3_INVERTED => '0',
      IS_T4_INVERTED => '0',
      SERDES_MODE => "MASTER",
      SRVAL_OQ => '1',
      SRVAL_TQ => '1',
      TBYTE_CTL => "TRUE",
      TBYTE_SRC => "FALSE",
      TRISTATE_WIDTH => 4
    )
        port map (
      CLK => oserdes_clk,
      CLKDIV => oserdes_clkdiv,
      D1 => of_dqbus(0),
      D2 => of_dqbus(1),
      D3 => of_dqbus(2),
      D4 => of_dqbus(3),
      D5 => '0',
      D6 => '0',
      D7 => '0',
      D8 => '0',
      OCE => '1',
      OFB => \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\,
      OQ => mem_dq_out(0),
      RST => po_oserdes_rst,
      SHIFTIN1 => \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\,
      SHIFTIN2 => \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\,
      SHIFTOUT1 => \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\,
      T1 => '0',
      T2 => '0',
      T3 => '0',
      T4 => '0',
      TBYTEIN => tbyte_out,
      TBYTEOUT => \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\,
      TCE => '1',
      TFB => \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\,
      TQ => mem_dq_ts(0)
    );
\output_[2].oserdes_dq_.ddr.oserdes_dq_i\: unisim.vcomponents.OSERDESE2
    generic map(
      DATA_RATE_OQ => "DDR",
      DATA_RATE_TQ => "DDR",
      DATA_WIDTH => 4,
      INIT_OQ => '1',
      INIT_TQ => '1',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D1_INVERTED => '0',
      IS_D2_INVERTED => '0',
      IS_D3_INVERTED => '0',
      IS_D4_INVERTED => '0',
      IS_D5_INVERTED => '0',
      IS_D6_INVERTED => '0',
      IS_D7_INVERTED => '0',
      IS_D8_INVERTED => '0',
      IS_T1_INVERTED => '0',
      IS_T2_INVERTED => '0',
      IS_T3_INVERTED => '0',
      IS_T4_INVERTED => '0',
      SERDES_MODE => "MASTER",
      SRVAL_OQ => '1',
      SRVAL_TQ => '1',
      TBYTE_CTL => "TRUE",
      TBYTE_SRC => "FALSE",
      TRISTATE_WIDTH => 4
    )
        port map (
      CLK => oserdes_clk,
      CLKDIV => oserdes_clkdiv,
      D1 => of_dqbus(4),
      D2 => of_dqbus(5),
      D3 => of_dqbus(6),
      D4 => of_dqbus(7),
      D5 => '0',
      D6 => '0',
      D7 => '0',
      D8 => '0',
      OCE => '1',
      OFB => \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\,
      OQ => mem_dq_out(1),
      RST => po_oserdes_rst,
      SHIFTIN1 => \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\,
      SHIFTIN2 => \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\,
      SHIFTOUT1 => \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\,
      T1 => '0',
      T2 => '0',
      T3 => '0',
      T4 => '0',
      TBYTEIN => tbyte_out,
      TBYTEOUT => \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\,
      TCE => '1',
      TFB => \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\,
      TQ => mem_dq_ts(1)
    );
\output_[3].oserdes_dq_.ddr.oserdes_dq_i\: unisim.vcomponents.OSERDESE2
    generic map(
      DATA_RATE_OQ => "DDR",
      DATA_RATE_TQ => "DDR",
      DATA_WIDTH => 4,
      INIT_OQ => '1',
      INIT_TQ => '1',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D1_INVERTED => '0',
      IS_D2_INVERTED => '0',
      IS_D3_INVERTED => '0',
      IS_D4_INVERTED => '0',
      IS_D5_INVERTED => '0',
      IS_D6_INVERTED => '0',
      IS_D7_INVERTED => '0',
      IS_D8_INVERTED => '0',
      IS_T1_INVERTED => '0',
      IS_T2_INVERTED => '0',
      IS_T3_INVERTED => '0',
      IS_T4_INVERTED => '0',
      SERDES_MODE => "MASTER",
      SRVAL_OQ => '1',
      SRVAL_TQ => '1',
      TBYTE_CTL => "TRUE",
      TBYTE_SRC => "FALSE",
      TRISTATE_WIDTH => 4
    )
        port map (
      CLK => oserdes_clk,
      CLKDIV => oserdes_clkdiv,
      D1 => of_dqbus(8),
      D2 => of_dqbus(9),
      D3 => of_dqbus(10),
      D4 => of_dqbus(11),
      D5 => '0',
      D6 => '0',
      D7 => '0',
      D8 => '0',
      OCE => '1',
      OFB => \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\,
      OQ => mem_dq_out(2),
      RST => po_oserdes_rst,
      SHIFTIN1 => \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\,
      SHIFTIN2 => \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\,
      SHIFTOUT1 => \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\,
      T1 => '0',
      T2 => '0',
      T3 => '0',
      T4 => '0',
      TBYTEIN => tbyte_out,
      TBYTEOUT => \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\,
      TCE => '1',
      TFB => \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\,
      TQ => mem_dq_ts(2)
    );
\output_[4].oserdes_dq_.ddr.oserdes_dq_i\: unisim.vcomponents.OSERDESE2
    generic map(
      DATA_RATE_OQ => "DDR",
      DATA_RATE_TQ => "DDR",
      DATA_WIDTH => 4,
      INIT_OQ => '1',
      INIT_TQ => '1',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D1_INVERTED => '0',
      IS_D2_INVERTED => '0',
      IS_D3_INVERTED => '0',
      IS_D4_INVERTED => '0',
      IS_D5_INVERTED => '0',
      IS_D6_INVERTED => '0',
      IS_D7_INVERTED => '0',
      IS_D8_INVERTED => '0',
      IS_T1_INVERTED => '0',
      IS_T2_INVERTED => '0',
      IS_T3_INVERTED => '0',
      IS_T4_INVERTED => '0',
      SERDES_MODE => "MASTER",
      SRVAL_OQ => '1',
      SRVAL_TQ => '1',
      TBYTE_CTL => "TRUE",
      TBYTE_SRC => "FALSE",
      TRISTATE_WIDTH => 4
    )
        port map (
      CLK => oserdes_clk,
      CLKDIV => oserdes_clkdiv,
      D1 => of_dqbus(12),
      D2 => of_dqbus(13),
      D3 => of_dqbus(14),
      D4 => of_dqbus(15),
      D5 => '0',
      D6 => '0',
      D7 => '0',
      D8 => '0',
      OCE => '1',
      OFB => \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\,
      OQ => mem_dq_out(3),
      RST => po_oserdes_rst,
      SHIFTIN1 => \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\,
      SHIFTIN2 => \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\,
      SHIFTOUT1 => \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\,
      T1 => '0',
      T2 => '0',
      T3 => '0',
      T4 => '0',
      TBYTEIN => tbyte_out,
      TBYTEOUT => \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\,
      TCE => '1',
      TFB => \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\,
      TQ => mem_dq_ts(3)
    );
\output_[5].oserdes_dq_.ddr.oserdes_dq_i\: unisim.vcomponents.OSERDESE2
    generic map(
      DATA_RATE_OQ => "DDR",
      DATA_RATE_TQ => "DDR",
      DATA_WIDTH => 4,
      INIT_OQ => '1',
      INIT_TQ => '1',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D1_INVERTED => '0',
      IS_D2_INVERTED => '0',
      IS_D3_INVERTED => '0',
      IS_D4_INVERTED => '0',
      IS_D5_INVERTED => '0',
      IS_D6_INVERTED => '0',
      IS_D7_INVERTED => '0',
      IS_D8_INVERTED => '0',
      IS_T1_INVERTED => '0',
      IS_T2_INVERTED => '0',
      IS_T3_INVERTED => '0',
      IS_T4_INVERTED => '0',
      SERDES_MODE => "MASTER",
      SRVAL_OQ => '1',
      SRVAL_TQ => '1',
      TBYTE_CTL => "TRUE",
      TBYTE_SRC => "FALSE",
      TRISTATE_WIDTH => 4
    )
        port map (
      CLK => oserdes_clk,
      CLKDIV => oserdes_clkdiv,
      D1 => of_dqbus(16),
      D2 => of_dqbus(17),
      D3 => of_dqbus(18),
      D4 => of_dqbus(19),
      D5 => '0',
      D6 => '0',
      D7 => '0',
      D8 => '0',
      OCE => '1',
      OFB => \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\,
      OQ => mem_dq_out(4),
      RST => po_oserdes_rst,
      SHIFTIN1 => \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\,
      SHIFTIN2 => \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\,
      SHIFTOUT1 => \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\,
      T1 => '0',
      T2 => '0',
      T3 => '0',
      T4 => '0',
      TBYTEIN => tbyte_out,
      TBYTEOUT => \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\,
      TCE => '1',
      TFB => \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\,
      TQ => mem_dq_ts(4)
    );
\output_[6].oserdes_dq_.ddr.oserdes_dq_i\: unisim.vcomponents.OSERDESE2
    generic map(
      DATA_RATE_OQ => "DDR",
      DATA_RATE_TQ => "DDR",
      DATA_WIDTH => 4,
      INIT_OQ => '1',
      INIT_TQ => '1',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D1_INVERTED => '0',
      IS_D2_INVERTED => '0',
      IS_D3_INVERTED => '0',
      IS_D4_INVERTED => '0',
      IS_D5_INVERTED => '0',
      IS_D6_INVERTED => '0',
      IS_D7_INVERTED => '0',
      IS_D8_INVERTED => '0',
      IS_T1_INVERTED => '0',
      IS_T2_INVERTED => '0',
      IS_T3_INVERTED => '0',
      IS_T4_INVERTED => '0',
      SERDES_MODE => "MASTER",
      SRVAL_OQ => '1',
      SRVAL_TQ => '1',
      TBYTE_CTL => "TRUE",
      TBYTE_SRC => "FALSE",
      TRISTATE_WIDTH => 4
    )
        port map (
      CLK => oserdes_clk,
      CLKDIV => oserdes_clkdiv,
      D1 => of_dqbus(20),
      D2 => of_dqbus(21),
      D3 => of_dqbus(22),
      D4 => of_dqbus(23),
      D5 => '0',
      D6 => '0',
      D7 => '0',
      D8 => '0',
      OCE => '1',
      OFB => \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\,
      OQ => mem_dq_out(5),
      RST => po_oserdes_rst,
      SHIFTIN1 => \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\,
      SHIFTIN2 => \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\,
      SHIFTOUT1 => \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\,
      T1 => '0',
      T2 => '0',
      T3 => '0',
      T4 => '0',
      TBYTEIN => tbyte_out,
      TBYTEOUT => \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\,
      TCE => '1',
      TFB => \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\,
      TQ => mem_dq_ts(5)
    );
\output_[7].oserdes_dq_.ddr.oserdes_dq_i\: unisim.vcomponents.OSERDESE2
    generic map(
      DATA_RATE_OQ => "DDR",
      DATA_RATE_TQ => "DDR",
      DATA_WIDTH => 4,
      INIT_OQ => '1',
      INIT_TQ => '1',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D1_INVERTED => '0',
      IS_D2_INVERTED => '0',
      IS_D3_INVERTED => '0',
      IS_D4_INVERTED => '0',
      IS_D5_INVERTED => '0',
      IS_D6_INVERTED => '0',
      IS_D7_INVERTED => '0',
      IS_D8_INVERTED => '0',
      IS_T1_INVERTED => '0',
      IS_T2_INVERTED => '0',
      IS_T3_INVERTED => '0',
      IS_T4_INVERTED => '0',
      SERDES_MODE => "MASTER",
      SRVAL_OQ => '1',
      SRVAL_TQ => '1',
      TBYTE_CTL => "TRUE",
      TBYTE_SRC => "FALSE",
      TRISTATE_WIDTH => 4
    )
        port map (
      CLK => oserdes_clk,
      CLKDIV => oserdes_clkdiv,
      D1 => of_dqbus(24),
      D2 => of_dqbus(25),
      D3 => of_dqbus(26),
      D4 => of_dqbus(27),
      D5 => '0',
      D6 => '0',
      D7 => '0',
      D8 => '0',
      OCE => '1',
      OFB => \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\,
      OQ => mem_dq_out(6),
      RST => po_oserdes_rst,
      SHIFTIN1 => \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\,
      SHIFTIN2 => \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\,
      SHIFTOUT1 => \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\,
      T1 => '0',
      T2 => '0',
      T3 => '0',
      T4 => '0',
      TBYTEIN => tbyte_out,
      TBYTEOUT => \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\,
      TCE => '1',
      TFB => \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\,
      TQ => mem_dq_ts(6)
    );
\output_[8].oserdes_dq_.ddr.oserdes_dq_i\: unisim.vcomponents.OSERDESE2
    generic map(
      DATA_RATE_OQ => "DDR",
      DATA_RATE_TQ => "DDR",
      DATA_WIDTH => 4,
      INIT_OQ => '1',
      INIT_TQ => '1',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D1_INVERTED => '0',
      IS_D2_INVERTED => '0',
      IS_D3_INVERTED => '0',
      IS_D4_INVERTED => '0',
      IS_D5_INVERTED => '0',
      IS_D6_INVERTED => '0',
      IS_D7_INVERTED => '0',
      IS_D8_INVERTED => '0',
      IS_T1_INVERTED => '0',
      IS_T2_INVERTED => '0',
      IS_T3_INVERTED => '0',
      IS_T4_INVERTED => '0',
      SERDES_MODE => "MASTER",
      SRVAL_OQ => '1',
      SRVAL_TQ => '1',
      TBYTE_CTL => "TRUE",
      TBYTE_SRC => "FALSE",
      TRISTATE_WIDTH => 4
    )
        port map (
      CLK => oserdes_clk,
      CLKDIV => oserdes_clkdiv,
      D1 => of_dqbus(28),
      D2 => of_dqbus(29),
      D3 => of_dqbus(30),
      D4 => of_dqbus(31),
      D5 => '0',
      D6 => '0',
      D7 => '0',
      D8 => '0',
      OCE => '1',
      OFB => \NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\,
      OQ => mem_dq_out(7),
      RST => po_oserdes_rst,
      SHIFTIN1 => \NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\,
      SHIFTIN2 => \NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\,
      SHIFTOUT1 => \NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\,
      T1 => '0',
      T2 => '0',
      T3 => '0',
      T4 => '0',
      TBYTEIN => tbyte_out,
      TBYTEOUT => \NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\,
      TCE => '1',
      TFB => \NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\,
      TQ => mem_dq_ts(7)
    );
\output_[9].oserdes_dq_.ddr.oserdes_dq_i\: unisim.vcomponents.OSERDESE2
    generic map(
      DATA_RATE_OQ => "DDR",
      DATA_RATE_TQ => "DDR",
      DATA_WIDTH => 4,
      INIT_OQ => '1',
      INIT_TQ => '1',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D1_INVERTED => '0',
      IS_D2_INVERTED => '0',
      IS_D3_INVERTED => '0',
      IS_D4_INVERTED => '0',
      IS_D5_INVERTED => '0',
      IS_D6_INVERTED => '0',
      IS_D7_INVERTED => '0',
      IS_D8_INVERTED => '0',
      IS_T1_INVERTED => '0',
      IS_T2_INVERTED => '0',
      IS_T3_INVERTED => '0',
      IS_T4_INVERTED => '0',
      SERDES_MODE => "MASTER",
      SRVAL_OQ => '1',
      SRVAL_TQ => '1',
      TBYTE_CTL => "TRUE",
      TBYTE_SRC => "FALSE",
      TRISTATE_WIDTH => 4
    )
        port map (
      CLK => oserdes_clk,
      CLKDIV => oserdes_clkdiv,
      D1 => of_dqbus(32),
      D2 => of_dqbus(33),
      D3 => of_dqbus(34),
      D4 => of_dqbus(35),
      D5 => '0',
      D6 => '0',
      D7 => '0',
      D8 => '0',
      OCE => '1',
      OFB => \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\,
      OQ => mem_dq_out(8),
      RST => po_oserdes_rst,
      SHIFTIN1 => \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\,
      SHIFTIN2 => \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\,
      SHIFTOUT1 => \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\,
      T1 => '0',
      T2 => '0',
      T3 => '0',
      T4 => '0',
      TBYTEIN => tbyte_out,
      TBYTEOUT => \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\,
      TCE => '1',
      TFB => \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\,
      TQ => mem_dq_ts(8)
    );
rst_r3_reg_srl3: unisim.vcomponents.SRL16E
     port map (
      A0 => '0',
      A1 => '1',
      A2 => '0',
      A3 => '0',
      CE => '1',
      CLK => idelay_ld_rst_reg_0,
      D => A_rst_primitives,
      Q => rst_r3_reg_srl3_n_0
    );
rst_r4_reg: unisim.vcomponents.FDRE
     port map (
      C => idelay_ld_rst_reg_0,
      CE => '1',
      D => rst_r3_reg_srl3_n_0,
      Q => \^rst_r4\,
      R => '0'
    );
\slave_ts.oserdes_slave_ts\: unisim.vcomponents.OSERDESE2
    generic map(
      DATA_RATE_OQ => "DDR",
      DATA_RATE_TQ => "DDR",
      DATA_WIDTH => 4,
      INIT_OQ => '1',
      INIT_TQ => '1',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D1_INVERTED => '0',
      IS_D2_INVERTED => '0',
      IS_D3_INVERTED => '0',
      IS_D4_INVERTED => '0',
      IS_D5_INVERTED => '0',
      IS_D6_INVERTED => '0',
      IS_D7_INVERTED => '0',
      IS_D8_INVERTED => '0',
      IS_T1_INVERTED => '0',
      IS_T2_INVERTED => '0',
      IS_T3_INVERTED => '0',
      IS_T4_INVERTED => '0',
      SERDES_MODE => "MASTER",
      SRVAL_OQ => '1',
      SRVAL_TQ => '1',
      TBYTE_CTL => "TRUE",
      TBYTE_SRC => "TRUE",
      TRISTATE_WIDTH => 4
    )
        port map (
      CLK => oserdes_clk,
      CLKDIV => oserdes_clkdiv,
      D1 => '0',
      D2 => '0',
      D3 => '0',
      D4 => '0',
      D5 => '0',
      D6 => '0',
      D7 => '0',
      D8 => '0',
      OCE => '1',
      OFB => \NLW_slave_ts.oserdes_slave_ts_OFB_UNCONNECTED\,
      OQ => \NLW_slave_ts.oserdes_slave_ts_OQ_UNCONNECTED\,
      RST => po_oserdes_rst,
      SHIFTIN1 => \NLW_slave_ts.oserdes_slave_ts_SHIFTIN1_UNCONNECTED\,
      SHIFTIN2 => \NLW_slave_ts.oserdes_slave_ts_SHIFTIN2_UNCONNECTED\,
      SHIFTOUT1 => \NLW_slave_ts.oserdes_slave_ts_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_slave_ts.oserdes_slave_ts_SHIFTOUT2_UNCONNECTED\,
      T1 => DTSBUS(0),
      T2 => DTSBUS(0),
      T3 => DTSBUS(1),
      T4 => DTSBUS(1),
      TBYTEIN => tbyte_out,
      TBYTEOUT => tbyte_out,
      TCE => '1',
      TFB => \NLW_slave_ts.oserdes_slave_ts_TFB_UNCONNECTED\,
      TQ => \NLW_slave_ts.oserdes_slave_ts_TQ_UNCONNECTED\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \mig_mig_7series_v4_2_ddr_byte_group_io__parameterized0_32\ is
  port (
    out_dqs_6 : out STD_LOGIC;
    ts_dqs_6 : out STD_LOGIC;
    D2 : out STD_LOGIC_VECTOR ( 3 downto 0 );
    D3 : out STD_LOGIC_VECTOR ( 3 downto 0 );
    D4 : out STD_LOGIC_VECTOR ( 3 downto 0 );
    D5 : out STD_LOGIC_VECTOR ( 3 downto 0 );
    D6 : out STD_LOGIC_VECTOR ( 3 downto 0 );
    D7 : out STD_LOGIC_VECTOR ( 3 downto 0 );
    D8 : out STD_LOGIC_VECTOR ( 3 downto 0 );
    D9 : out STD_LOGIC_VECTOR ( 3 downto 0 );
    mem_dq_out : out STD_LOGIC_VECTOR ( 8 downto 0 );
    mem_dq_ts : out STD_LOGIC_VECTOR ( 8 downto 0 );
    idelay_ld_rst_1 : out STD_LOGIC;
    oserdes_clk : in STD_LOGIC;
    oserdes_clkdiv : in STD_LOGIC;
    po_oserdes_rst : in STD_LOGIC;
    DTSBUS : in STD_LOGIC_VECTOR ( 1 downto 0 );
    oserdes_clk_delayed : in STD_LOGIC;
    DQSBUS : in STD_LOGIC_VECTOR ( 1 downto 0 );
    CTSBUS : in STD_LOGIC_VECTOR ( 0 to 0 );
    idelay_ld_rst_reg_0 : in STD_LOGIC;
    \input_[9].iserdes_dq_.iserdesdq_0\ : in STD_LOGIC;
    mem_dq_in : in STD_LOGIC_VECTOR ( 7 downto 0 );
    idelay_inc : in STD_LOGIC;
    LD0_8 : in STD_LOGIC;
    A_rst_primitives : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]\ : in STD_LOGIC;
    CLKB0_8 : in STD_LOGIC;
    iserdes_clkdiv : in STD_LOGIC;
    of_dqbus : in STD_LOGIC_VECTOR ( 35 downto 0 );
    rst_r4 : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \mig_mig_7series_v4_2_ddr_byte_group_io__parameterized0_32\ : entity is "mig_7series_v4_2_ddr_byte_group_io";
end \mig_mig_7series_v4_2_ddr_byte_group_io__parameterized0_32\;

architecture STRUCTURE of \mig_mig_7series_v4_2_ddr_byte_group_io__parameterized0_32\ is
  signal data_in_dly_2 : STD_LOGIC;
  signal data_in_dly_3 : STD_LOGIC;
  signal data_in_dly_4 : STD_LOGIC;
  signal data_in_dly_5 : STD_LOGIC;
  signal data_in_dly_6 : STD_LOGIC;
  signal data_in_dly_7 : STD_LOGIC;
  signal data_in_dly_8 : STD_LOGIC;
  signal data_in_dly_9 : STD_LOGIC;
  signal \^idelay_ld_rst_1\ : STD_LOGIC;
  signal \idelay_ld_rst_i_1__1_n_0\ : STD_LOGIC;
  signal tbyte_out : STD_LOGIC;
  signal \NLW_dqs_gen.oddr_dqs_S_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_dqs_gen.oddr_dqsts_R_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[2].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal \NLW_input_[2].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[2].iserdes_dq_.iserdesdq_O_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[2].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[2].iserdes_dq_.iserdesdq_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[2].iserdes_dq_.iserdesdq_Q5_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[2].iserdes_dq_.iserdesdq_Q6_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[2].iserdes_dq_.iserdesdq_Q7_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[2].iserdes_dq_.iserdesdq_Q8_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[2].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[2].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[3].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal \NLW_input_[3].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[3].iserdes_dq_.iserdesdq_O_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[3].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[3].iserdes_dq_.iserdesdq_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[3].iserdes_dq_.iserdesdq_Q5_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[3].iserdes_dq_.iserdesdq_Q6_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[3].iserdes_dq_.iserdesdq_Q7_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[3].iserdes_dq_.iserdesdq_Q8_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[3].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[3].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[4].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal \NLW_input_[4].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[4].iserdes_dq_.iserdesdq_O_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[4].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[4].iserdes_dq_.iserdesdq_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[4].iserdes_dq_.iserdesdq_Q5_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[4].iserdes_dq_.iserdesdq_Q6_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[4].iserdes_dq_.iserdesdq_Q7_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[4].iserdes_dq_.iserdesdq_Q8_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[4].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[4].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[5].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal \NLW_input_[5].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[5].iserdes_dq_.iserdesdq_O_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[5].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[5].iserdes_dq_.iserdesdq_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[5].iserdes_dq_.iserdesdq_Q5_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[5].iserdes_dq_.iserdesdq_Q6_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[5].iserdes_dq_.iserdesdq_Q7_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[5].iserdes_dq_.iserdesdq_Q8_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[5].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[5].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[6].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal \NLW_input_[6].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[6].iserdes_dq_.iserdesdq_O_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[6].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[6].iserdes_dq_.iserdesdq_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[6].iserdes_dq_.iserdesdq_Q5_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[6].iserdes_dq_.iserdesdq_Q6_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[6].iserdes_dq_.iserdesdq_Q7_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[6].iserdes_dq_.iserdesdq_Q8_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[6].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[6].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[7].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal \NLW_input_[7].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[7].iserdes_dq_.iserdesdq_O_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[7].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[7].iserdes_dq_.iserdesdq_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[7].iserdes_dq_.iserdesdq_Q5_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[7].iserdes_dq_.iserdesdq_Q6_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[7].iserdes_dq_.iserdesdq_Q7_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[7].iserdes_dq_.iserdesdq_Q8_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[7].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[7].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[8].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal \NLW_input_[8].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[8].iserdes_dq_.iserdesdq_O_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[8].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[8].iserdes_dq_.iserdesdq_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[8].iserdes_dq_.iserdesdq_Q5_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[8].iserdes_dq_.iserdesdq_Q6_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[8].iserdes_dq_.iserdesdq_Q7_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[8].iserdes_dq_.iserdesdq_Q8_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[8].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[8].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[9].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal \NLW_input_[9].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[9].iserdes_dq_.iserdesdq_O_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[9].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[9].iserdes_dq_.iserdesdq_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[9].iserdes_dq_.iserdesdq_Q5_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[9].iserdes_dq_.iserdesdq_Q6_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[9].iserdes_dq_.iserdesdq_Q7_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[9].iserdes_dq_.iserdesdq_Q8_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[9].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[9].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_slave_ts.oserdes_slave_ts_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_slave_ts.oserdes_slave_ts_OQ_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_slave_ts.oserdes_slave_ts_SHIFTIN1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_slave_ts.oserdes_slave_ts_SHIFTIN2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_slave_ts.oserdes_slave_ts_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_slave_ts.oserdes_slave_ts_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_slave_ts.oserdes_slave_ts_TFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_slave_ts.oserdes_slave_ts_TQ_UNCONNECTED\ : STD_LOGIC;
  attribute BOX_TYPE : string;
  attribute BOX_TYPE of \dqs_gen.oddr_dqs\ : label is "PRIMITIVE";
  attribute \__SRVAL\ : string;
  attribute \__SRVAL\ of \dqs_gen.oddr_dqs\ : label is "FALSE";
  attribute BOX_TYPE of \dqs_gen.oddr_dqsts\ : label is "PRIMITIVE";
  attribute \__SRVAL\ of \dqs_gen.oddr_dqsts\ : label is "TRUE";
  attribute BOX_TYPE of \input_[2].iserdes_dq_.idelay_dq.idelaye2\ : label is "PRIMITIVE";
  attribute IODELAY_GROUP : string;
  attribute IODELAY_GROUP of \input_[2].iserdes_dq_.idelay_dq.idelaye2\ : label is "MIG_IODELAY_MIG0";
  attribute SIM_DELAY_D : integer;
  attribute SIM_DELAY_D of \input_[2].iserdes_dq_.idelay_dq.idelaye2\ : label is 0;
  attribute BOX_TYPE of \input_[2].iserdes_dq_.iserdesdq\ : label is "PRIMITIVE";
  attribute OPT_MODIFIED : string;
  attribute OPT_MODIFIED of \input_[2].iserdes_dq_.iserdesdq\ : label is "MLO";
  attribute BOX_TYPE of \input_[3].iserdes_dq_.idelay_dq.idelaye2\ : label is "PRIMITIVE";
  attribute IODELAY_GROUP of \input_[3].iserdes_dq_.idelay_dq.idelaye2\ : label is "MIG_IODELAY_MIG0";
  attribute SIM_DELAY_D of \input_[3].iserdes_dq_.idelay_dq.idelaye2\ : label is 0;
  attribute BOX_TYPE of \input_[3].iserdes_dq_.iserdesdq\ : label is "PRIMITIVE";
  attribute OPT_MODIFIED of \input_[3].iserdes_dq_.iserdesdq\ : label is "MLO";
  attribute BOX_TYPE of \input_[4].iserdes_dq_.idelay_dq.idelaye2\ : label is "PRIMITIVE";
  attribute IODELAY_GROUP of \input_[4].iserdes_dq_.idelay_dq.idelaye2\ : label is "MIG_IODELAY_MIG0";
  attribute SIM_DELAY_D of \input_[4].iserdes_dq_.idelay_dq.idelaye2\ : label is 0;
  attribute BOX_TYPE of \input_[4].iserdes_dq_.iserdesdq\ : label is "PRIMITIVE";
  attribute OPT_MODIFIED of \input_[4].iserdes_dq_.iserdesdq\ : label is "MLO";
  attribute BOX_TYPE of \input_[5].iserdes_dq_.idelay_dq.idelaye2\ : label is "PRIMITIVE";
  attribute IODELAY_GROUP of \input_[5].iserdes_dq_.idelay_dq.idelaye2\ : label is "MIG_IODELAY_MIG0";
  attribute SIM_DELAY_D of \input_[5].iserdes_dq_.idelay_dq.idelaye2\ : label is 0;
  attribute BOX_TYPE of \input_[5].iserdes_dq_.iserdesdq\ : label is "PRIMITIVE";
  attribute OPT_MODIFIED of \input_[5].iserdes_dq_.iserdesdq\ : label is "MLO";
  attribute BOX_TYPE of \input_[6].iserdes_dq_.idelay_dq.idelaye2\ : label is "PRIMITIVE";
  attribute IODELAY_GROUP of \input_[6].iserdes_dq_.idelay_dq.idelaye2\ : label is "MIG_IODELAY_MIG0";
  attribute SIM_DELAY_D of \input_[6].iserdes_dq_.idelay_dq.idelaye2\ : label is 0;
  attribute BOX_TYPE of \input_[6].iserdes_dq_.iserdesdq\ : label is "PRIMITIVE";
  attribute OPT_MODIFIED of \input_[6].iserdes_dq_.iserdesdq\ : label is "MLO";
  attribute BOX_TYPE of \input_[7].iserdes_dq_.idelay_dq.idelaye2\ : label is "PRIMITIVE";
  attribute IODELAY_GROUP of \input_[7].iserdes_dq_.idelay_dq.idelaye2\ : label is "MIG_IODELAY_MIG0";
  attribute SIM_DELAY_D of \input_[7].iserdes_dq_.idelay_dq.idelaye2\ : label is 0;
  attribute BOX_TYPE of \input_[7].iserdes_dq_.iserdesdq\ : label is "PRIMITIVE";
  attribute OPT_MODIFIED of \input_[7].iserdes_dq_.iserdesdq\ : label is "MLO";
  attribute BOX_TYPE of \input_[8].iserdes_dq_.idelay_dq.idelaye2\ : label is "PRIMITIVE";
  attribute IODELAY_GROUP of \input_[8].iserdes_dq_.idelay_dq.idelaye2\ : label is "MIG_IODELAY_MIG0";
  attribute SIM_DELAY_D of \input_[8].iserdes_dq_.idelay_dq.idelaye2\ : label is 0;
  attribute BOX_TYPE of \input_[8].iserdes_dq_.iserdesdq\ : label is "PRIMITIVE";
  attribute OPT_MODIFIED of \input_[8].iserdes_dq_.iserdesdq\ : label is "MLO";
  attribute BOX_TYPE of \input_[9].iserdes_dq_.idelay_dq.idelaye2\ : label is "PRIMITIVE";
  attribute IODELAY_GROUP of \input_[9].iserdes_dq_.idelay_dq.idelaye2\ : label is "MIG_IODELAY_MIG0";
  attribute SIM_DELAY_D of \input_[9].iserdes_dq_.idelay_dq.idelaye2\ : label is 0;
  attribute BOX_TYPE of \input_[9].iserdes_dq_.iserdesdq\ : label is "PRIMITIVE";
  attribute OPT_MODIFIED of \input_[9].iserdes_dq_.iserdesdq\ : label is "MLO";
  attribute BOX_TYPE of \output_[1].oserdes_dq_.ddr.oserdes_dq_i\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \output_[2].oserdes_dq_.ddr.oserdes_dq_i\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \output_[3].oserdes_dq_.ddr.oserdes_dq_i\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \output_[4].oserdes_dq_.ddr.oserdes_dq_i\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \output_[5].oserdes_dq_.ddr.oserdes_dq_i\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \output_[6].oserdes_dq_.ddr.oserdes_dq_i\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \output_[7].oserdes_dq_.ddr.oserdes_dq_i\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \output_[8].oserdes_dq_.ddr.oserdes_dq_i\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \output_[9].oserdes_dq_.ddr.oserdes_dq_i\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \slave_ts.oserdes_slave_ts\ : label is "PRIMITIVE";
begin
  idelay_ld_rst_1 <= \^idelay_ld_rst_1\;
\dqs_gen.oddr_dqs\: unisim.vcomponents.ODDR
    generic map(
      DDR_CLK_EDGE => "SAME_EDGE",
      INIT => '0',
      IS_C_INVERTED => '0',
      IS_D1_INVERTED => '0',
      IS_D2_INVERTED => '0',
      SRTYPE => "SYNC"
    )
        port map (
      C => oserdes_clk_delayed,
      CE => '1',
      D1 => DQSBUS(0),
      D2 => DQSBUS(1),
      Q => out_dqs_6,
      R => '0',
      S => \NLW_dqs_gen.oddr_dqs_S_UNCONNECTED\
    );
\dqs_gen.oddr_dqsts\: unisim.vcomponents.ODDR
    generic map(
      DDR_CLK_EDGE => "SAME_EDGE",
      INIT => '0',
      IS_C_INVERTED => '0',
      IS_D1_INVERTED => '0',
      IS_D2_INVERTED => '0',
      SRTYPE => "SYNC"
    )
        port map (
      C => oserdes_clk_delayed,
      CE => '1',
      D1 => CTSBUS(0),
      D2 => CTSBUS(0),
      Q => ts_dqs_6,
      R => \NLW_dqs_gen.oddr_dqsts_R_UNCONNECTED\,
      S => '0'
    );
\idelay_ld_rst_i_1__1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \^idelay_ld_rst_1\,
      I1 => rst_r4,
      O => \idelay_ld_rst_i_1__1_n_0\
    );
idelay_ld_rst_reg: unisim.vcomponents.FDSE
     port map (
      C => idelay_ld_rst_reg_0,
      CE => '1',
      D => \idelay_ld_rst_i_1__1_n_0\,
      Q => \^idelay_ld_rst_1\,
      S => A_rst_primitives
    );
\input_[2].iserdes_dq_.idelay_dq.idelaye2\: unisim.vcomponents.IDELAYE2
    generic map(
      CINVCTRL_SEL => "FALSE",
      DELAY_SRC => "IDATAIN",
      HIGH_PERFORMANCE_MODE => "TRUE",
      IDELAY_TYPE => "VARIABLE",
      IDELAY_VALUE => 0,
      IS_C_INVERTED => '0',
      IS_DATAIN_INVERTED => '0',
      IS_IDATAIN_INVERTED => '0',
      PIPE_SEL => "FALSE",
      REFCLK_FREQUENCY => 200.000000,
      SIGNAL_PATTERN => "DATA"
    )
        port map (
      C => idelay_ld_rst_reg_0,
      CE => \input_[9].iserdes_dq_.iserdesdq_0\,
      CINVCTRL => '0',
      CNTVALUEIN(4 downto 0) => B"00000",
      CNTVALUEOUT(4 downto 0) => \NLW_input_[2].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED\(4 downto 0),
      DATAIN => '0',
      DATAOUT => data_in_dly_2,
      IDATAIN => mem_dq_in(0),
      INC => idelay_inc,
      LD => LD0_8,
      LDPIPEEN => '0',
      REGRST => A_rst_primitives
    );
\input_[2].iserdes_dq_.iserdesdq\: unisim.vcomponents.ISERDESE2
    generic map(
      DATA_RATE => "DDR",
      DATA_WIDTH => 4,
      DYN_CLKDIV_INV_EN => "FALSE",
      DYN_CLK_INV_EN => "FALSE",
      INIT_Q1 => '0',
      INIT_Q2 => '0',
      INIT_Q3 => '0',
      INIT_Q4 => '0',
      INTERFACE_TYPE => "MEMORY_DDR3",
      IOBDELAY => "IFD",
      IS_CLKB_INVERTED => '1',
      IS_CLKDIVP_INVERTED => '0',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D_INVERTED => '0',
      IS_OCLKB_INVERTED => '0',
      IS_OCLK_INVERTED => '0',
      NUM_CE => 2,
      OFB_USED => "FALSE",
      SERDES_MODE => "MASTER",
      SRVAL_Q1 => '0',
      SRVAL_Q2 => '0',
      SRVAL_Q3 => '0',
      SRVAL_Q4 => '0'
    )
        port map (
      BITSLIP => '0',
      CE1 => '1',
      CE2 => '1',
      CLK => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]\,
      CLKB => CLKB0_8,
      CLKDIV => \NLW_input_[2].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED\,
      CLKDIVP => iserdes_clkdiv,
      D => mem_dq_in(0),
      DDLY => data_in_dly_2,
      DYNCLKDIVSEL => '0',
      DYNCLKSEL => '0',
      O => \NLW_input_[2].iserdes_dq_.iserdesdq_O_UNCONNECTED\,
      OCLK => oserdes_clk,
      OCLKB => \NLW_input_[2].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED\,
      OFB => \NLW_input_[2].iserdes_dq_.iserdesdq_OFB_UNCONNECTED\,
      Q1 => D2(3),
      Q2 => D2(2),
      Q3 => D2(1),
      Q4 => D2(0),
      Q5 => \NLW_input_[2].iserdes_dq_.iserdesdq_Q5_UNCONNECTED\,
      Q6 => \NLW_input_[2].iserdes_dq_.iserdesdq_Q6_UNCONNECTED\,
      Q7 => \NLW_input_[2].iserdes_dq_.iserdesdq_Q7_UNCONNECTED\,
      Q8 => \NLW_input_[2].iserdes_dq_.iserdesdq_Q8_UNCONNECTED\,
      RST => '0',
      SHIFTIN1 => '0',
      SHIFTIN2 => '0',
      SHIFTOUT1 => \NLW_input_[2].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_input_[2].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED\
    );
\input_[3].iserdes_dq_.idelay_dq.idelaye2\: unisim.vcomponents.IDELAYE2
    generic map(
      CINVCTRL_SEL => "FALSE",
      DELAY_SRC => "IDATAIN",
      HIGH_PERFORMANCE_MODE => "TRUE",
      IDELAY_TYPE => "VARIABLE",
      IDELAY_VALUE => 0,
      IS_C_INVERTED => '0',
      IS_DATAIN_INVERTED => '0',
      IS_IDATAIN_INVERTED => '0',
      PIPE_SEL => "FALSE",
      REFCLK_FREQUENCY => 200.000000,
      SIGNAL_PATTERN => "DATA"
    )
        port map (
      C => idelay_ld_rst_reg_0,
      CE => \input_[9].iserdes_dq_.iserdesdq_0\,
      CINVCTRL => '0',
      CNTVALUEIN(4 downto 0) => B"00000",
      CNTVALUEOUT(4 downto 0) => \NLW_input_[3].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED\(4 downto 0),
      DATAIN => '0',
      DATAOUT => data_in_dly_3,
      IDATAIN => mem_dq_in(1),
      INC => idelay_inc,
      LD => LD0_8,
      LDPIPEEN => '0',
      REGRST => A_rst_primitives
    );
\input_[3].iserdes_dq_.iserdesdq\: unisim.vcomponents.ISERDESE2
    generic map(
      DATA_RATE => "DDR",
      DATA_WIDTH => 4,
      DYN_CLKDIV_INV_EN => "FALSE",
      DYN_CLK_INV_EN => "FALSE",
      INIT_Q1 => '0',
      INIT_Q2 => '0',
      INIT_Q3 => '0',
      INIT_Q4 => '0',
      INTERFACE_TYPE => "MEMORY_DDR3",
      IOBDELAY => "IFD",
      IS_CLKB_INVERTED => '1',
      IS_CLKDIVP_INVERTED => '0',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D_INVERTED => '0',
      IS_OCLKB_INVERTED => '0',
      IS_OCLK_INVERTED => '0',
      NUM_CE => 2,
      OFB_USED => "FALSE",
      SERDES_MODE => "MASTER",
      SRVAL_Q1 => '0',
      SRVAL_Q2 => '0',
      SRVAL_Q3 => '0',
      SRVAL_Q4 => '0'
    )
        port map (
      BITSLIP => '0',
      CE1 => '1',
      CE2 => '1',
      CLK => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]\,
      CLKB => CLKB0_8,
      CLKDIV => \NLW_input_[3].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED\,
      CLKDIVP => iserdes_clkdiv,
      D => mem_dq_in(1),
      DDLY => data_in_dly_3,
      DYNCLKDIVSEL => '0',
      DYNCLKSEL => '0',
      O => \NLW_input_[3].iserdes_dq_.iserdesdq_O_UNCONNECTED\,
      OCLK => oserdes_clk,
      OCLKB => \NLW_input_[3].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED\,
      OFB => \NLW_input_[3].iserdes_dq_.iserdesdq_OFB_UNCONNECTED\,
      Q1 => D3(3),
      Q2 => D3(2),
      Q3 => D3(1),
      Q4 => D3(0),
      Q5 => \NLW_input_[3].iserdes_dq_.iserdesdq_Q5_UNCONNECTED\,
      Q6 => \NLW_input_[3].iserdes_dq_.iserdesdq_Q6_UNCONNECTED\,
      Q7 => \NLW_input_[3].iserdes_dq_.iserdesdq_Q7_UNCONNECTED\,
      Q8 => \NLW_input_[3].iserdes_dq_.iserdesdq_Q8_UNCONNECTED\,
      RST => '0',
      SHIFTIN1 => '0',
      SHIFTIN2 => '0',
      SHIFTOUT1 => \NLW_input_[3].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_input_[3].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED\
    );
\input_[4].iserdes_dq_.idelay_dq.idelaye2\: unisim.vcomponents.IDELAYE2
    generic map(
      CINVCTRL_SEL => "FALSE",
      DELAY_SRC => "IDATAIN",
      HIGH_PERFORMANCE_MODE => "TRUE",
      IDELAY_TYPE => "VARIABLE",
      IDELAY_VALUE => 0,
      IS_C_INVERTED => '0',
      IS_DATAIN_INVERTED => '0',
      IS_IDATAIN_INVERTED => '0',
      PIPE_SEL => "FALSE",
      REFCLK_FREQUENCY => 200.000000,
      SIGNAL_PATTERN => "DATA"
    )
        port map (
      C => idelay_ld_rst_reg_0,
      CE => \input_[9].iserdes_dq_.iserdesdq_0\,
      CINVCTRL => '0',
      CNTVALUEIN(4 downto 0) => B"00000",
      CNTVALUEOUT(4 downto 0) => \NLW_input_[4].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED\(4 downto 0),
      DATAIN => '0',
      DATAOUT => data_in_dly_4,
      IDATAIN => mem_dq_in(2),
      INC => idelay_inc,
      LD => LD0_8,
      LDPIPEEN => '0',
      REGRST => A_rst_primitives
    );
\input_[4].iserdes_dq_.iserdesdq\: unisim.vcomponents.ISERDESE2
    generic map(
      DATA_RATE => "DDR",
      DATA_WIDTH => 4,
      DYN_CLKDIV_INV_EN => "FALSE",
      DYN_CLK_INV_EN => "FALSE",
      INIT_Q1 => '0',
      INIT_Q2 => '0',
      INIT_Q3 => '0',
      INIT_Q4 => '0',
      INTERFACE_TYPE => "MEMORY_DDR3",
      IOBDELAY => "IFD",
      IS_CLKB_INVERTED => '1',
      IS_CLKDIVP_INVERTED => '0',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D_INVERTED => '0',
      IS_OCLKB_INVERTED => '0',
      IS_OCLK_INVERTED => '0',
      NUM_CE => 2,
      OFB_USED => "FALSE",
      SERDES_MODE => "MASTER",
      SRVAL_Q1 => '0',
      SRVAL_Q2 => '0',
      SRVAL_Q3 => '0',
      SRVAL_Q4 => '0'
    )
        port map (
      BITSLIP => '0',
      CE1 => '1',
      CE2 => '1',
      CLK => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]\,
      CLKB => CLKB0_8,
      CLKDIV => \NLW_input_[4].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED\,
      CLKDIVP => iserdes_clkdiv,
      D => mem_dq_in(2),
      DDLY => data_in_dly_4,
      DYNCLKDIVSEL => '0',
      DYNCLKSEL => '0',
      O => \NLW_input_[4].iserdes_dq_.iserdesdq_O_UNCONNECTED\,
      OCLK => oserdes_clk,
      OCLKB => \NLW_input_[4].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED\,
      OFB => \NLW_input_[4].iserdes_dq_.iserdesdq_OFB_UNCONNECTED\,
      Q1 => D4(3),
      Q2 => D4(2),
      Q3 => D4(1),
      Q4 => D4(0),
      Q5 => \NLW_input_[4].iserdes_dq_.iserdesdq_Q5_UNCONNECTED\,
      Q6 => \NLW_input_[4].iserdes_dq_.iserdesdq_Q6_UNCONNECTED\,
      Q7 => \NLW_input_[4].iserdes_dq_.iserdesdq_Q7_UNCONNECTED\,
      Q8 => \NLW_input_[4].iserdes_dq_.iserdesdq_Q8_UNCONNECTED\,
      RST => '0',
      SHIFTIN1 => '0',
      SHIFTIN2 => '0',
      SHIFTOUT1 => \NLW_input_[4].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_input_[4].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED\
    );
\input_[5].iserdes_dq_.idelay_dq.idelaye2\: unisim.vcomponents.IDELAYE2
    generic map(
      CINVCTRL_SEL => "FALSE",
      DELAY_SRC => "IDATAIN",
      HIGH_PERFORMANCE_MODE => "TRUE",
      IDELAY_TYPE => "VARIABLE",
      IDELAY_VALUE => 0,
      IS_C_INVERTED => '0',
      IS_DATAIN_INVERTED => '0',
      IS_IDATAIN_INVERTED => '0',
      PIPE_SEL => "FALSE",
      REFCLK_FREQUENCY => 200.000000,
      SIGNAL_PATTERN => "DATA"
    )
        port map (
      C => idelay_ld_rst_reg_0,
      CE => \input_[9].iserdes_dq_.iserdesdq_0\,
      CINVCTRL => '0',
      CNTVALUEIN(4 downto 0) => B"00000",
      CNTVALUEOUT(4 downto 0) => \NLW_input_[5].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED\(4 downto 0),
      DATAIN => '0',
      DATAOUT => data_in_dly_5,
      IDATAIN => mem_dq_in(3),
      INC => idelay_inc,
      LD => LD0_8,
      LDPIPEEN => '0',
      REGRST => A_rst_primitives
    );
\input_[5].iserdes_dq_.iserdesdq\: unisim.vcomponents.ISERDESE2
    generic map(
      DATA_RATE => "DDR",
      DATA_WIDTH => 4,
      DYN_CLKDIV_INV_EN => "FALSE",
      DYN_CLK_INV_EN => "FALSE",
      INIT_Q1 => '0',
      INIT_Q2 => '0',
      INIT_Q3 => '0',
      INIT_Q4 => '0',
      INTERFACE_TYPE => "MEMORY_DDR3",
      IOBDELAY => "IFD",
      IS_CLKB_INVERTED => '1',
      IS_CLKDIVP_INVERTED => '0',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D_INVERTED => '0',
      IS_OCLKB_INVERTED => '0',
      IS_OCLK_INVERTED => '0',
      NUM_CE => 2,
      OFB_USED => "FALSE",
      SERDES_MODE => "MASTER",
      SRVAL_Q1 => '0',
      SRVAL_Q2 => '0',
      SRVAL_Q3 => '0',
      SRVAL_Q4 => '0'
    )
        port map (
      BITSLIP => '0',
      CE1 => '1',
      CE2 => '1',
      CLK => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]\,
      CLKB => CLKB0_8,
      CLKDIV => \NLW_input_[5].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED\,
      CLKDIVP => iserdes_clkdiv,
      D => mem_dq_in(3),
      DDLY => data_in_dly_5,
      DYNCLKDIVSEL => '0',
      DYNCLKSEL => '0',
      O => \NLW_input_[5].iserdes_dq_.iserdesdq_O_UNCONNECTED\,
      OCLK => oserdes_clk,
      OCLKB => \NLW_input_[5].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED\,
      OFB => \NLW_input_[5].iserdes_dq_.iserdesdq_OFB_UNCONNECTED\,
      Q1 => D5(3),
      Q2 => D5(2),
      Q3 => D5(1),
      Q4 => D5(0),
      Q5 => \NLW_input_[5].iserdes_dq_.iserdesdq_Q5_UNCONNECTED\,
      Q6 => \NLW_input_[5].iserdes_dq_.iserdesdq_Q6_UNCONNECTED\,
      Q7 => \NLW_input_[5].iserdes_dq_.iserdesdq_Q7_UNCONNECTED\,
      Q8 => \NLW_input_[5].iserdes_dq_.iserdesdq_Q8_UNCONNECTED\,
      RST => '0',
      SHIFTIN1 => '0',
      SHIFTIN2 => '0',
      SHIFTOUT1 => \NLW_input_[5].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_input_[5].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED\
    );
\input_[6].iserdes_dq_.idelay_dq.idelaye2\: unisim.vcomponents.IDELAYE2
    generic map(
      CINVCTRL_SEL => "FALSE",
      DELAY_SRC => "IDATAIN",
      HIGH_PERFORMANCE_MODE => "TRUE",
      IDELAY_TYPE => "VARIABLE",
      IDELAY_VALUE => 0,
      IS_C_INVERTED => '0',
      IS_DATAIN_INVERTED => '0',
      IS_IDATAIN_INVERTED => '0',
      PIPE_SEL => "FALSE",
      REFCLK_FREQUENCY => 200.000000,
      SIGNAL_PATTERN => "DATA"
    )
        port map (
      C => idelay_ld_rst_reg_0,
      CE => \input_[9].iserdes_dq_.iserdesdq_0\,
      CINVCTRL => '0',
      CNTVALUEIN(4 downto 0) => B"00000",
      CNTVALUEOUT(4 downto 0) => \NLW_input_[6].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED\(4 downto 0),
      DATAIN => '0',
      DATAOUT => data_in_dly_6,
      IDATAIN => mem_dq_in(4),
      INC => idelay_inc,
      LD => LD0_8,
      LDPIPEEN => '0',
      REGRST => A_rst_primitives
    );
\input_[6].iserdes_dq_.iserdesdq\: unisim.vcomponents.ISERDESE2
    generic map(
      DATA_RATE => "DDR",
      DATA_WIDTH => 4,
      DYN_CLKDIV_INV_EN => "FALSE",
      DYN_CLK_INV_EN => "FALSE",
      INIT_Q1 => '0',
      INIT_Q2 => '0',
      INIT_Q3 => '0',
      INIT_Q4 => '0',
      INTERFACE_TYPE => "MEMORY_DDR3",
      IOBDELAY => "IFD",
      IS_CLKB_INVERTED => '1',
      IS_CLKDIVP_INVERTED => '0',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D_INVERTED => '0',
      IS_OCLKB_INVERTED => '0',
      IS_OCLK_INVERTED => '0',
      NUM_CE => 2,
      OFB_USED => "FALSE",
      SERDES_MODE => "MASTER",
      SRVAL_Q1 => '0',
      SRVAL_Q2 => '0',
      SRVAL_Q3 => '0',
      SRVAL_Q4 => '0'
    )
        port map (
      BITSLIP => '0',
      CE1 => '1',
      CE2 => '1',
      CLK => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]\,
      CLKB => CLKB0_8,
      CLKDIV => \NLW_input_[6].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED\,
      CLKDIVP => iserdes_clkdiv,
      D => mem_dq_in(4),
      DDLY => data_in_dly_6,
      DYNCLKDIVSEL => '0',
      DYNCLKSEL => '0',
      O => \NLW_input_[6].iserdes_dq_.iserdesdq_O_UNCONNECTED\,
      OCLK => oserdes_clk,
      OCLKB => \NLW_input_[6].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED\,
      OFB => \NLW_input_[6].iserdes_dq_.iserdesdq_OFB_UNCONNECTED\,
      Q1 => D6(3),
      Q2 => D6(2),
      Q3 => D6(1),
      Q4 => D6(0),
      Q5 => \NLW_input_[6].iserdes_dq_.iserdesdq_Q5_UNCONNECTED\,
      Q6 => \NLW_input_[6].iserdes_dq_.iserdesdq_Q6_UNCONNECTED\,
      Q7 => \NLW_input_[6].iserdes_dq_.iserdesdq_Q7_UNCONNECTED\,
      Q8 => \NLW_input_[6].iserdes_dq_.iserdesdq_Q8_UNCONNECTED\,
      RST => '0',
      SHIFTIN1 => '0',
      SHIFTIN2 => '0',
      SHIFTOUT1 => \NLW_input_[6].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_input_[6].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED\
    );
\input_[7].iserdes_dq_.idelay_dq.idelaye2\: unisim.vcomponents.IDELAYE2
    generic map(
      CINVCTRL_SEL => "FALSE",
      DELAY_SRC => "IDATAIN",
      HIGH_PERFORMANCE_MODE => "TRUE",
      IDELAY_TYPE => "VARIABLE",
      IDELAY_VALUE => 0,
      IS_C_INVERTED => '0',
      IS_DATAIN_INVERTED => '0',
      IS_IDATAIN_INVERTED => '0',
      PIPE_SEL => "FALSE",
      REFCLK_FREQUENCY => 200.000000,
      SIGNAL_PATTERN => "DATA"
    )
        port map (
      C => idelay_ld_rst_reg_0,
      CE => \input_[9].iserdes_dq_.iserdesdq_0\,
      CINVCTRL => '0',
      CNTVALUEIN(4 downto 0) => B"00000",
      CNTVALUEOUT(4 downto 0) => \NLW_input_[7].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED\(4 downto 0),
      DATAIN => '0',
      DATAOUT => data_in_dly_7,
      IDATAIN => mem_dq_in(5),
      INC => idelay_inc,
      LD => LD0_8,
      LDPIPEEN => '0',
      REGRST => A_rst_primitives
    );
\input_[7].iserdes_dq_.iserdesdq\: unisim.vcomponents.ISERDESE2
    generic map(
      DATA_RATE => "DDR",
      DATA_WIDTH => 4,
      DYN_CLKDIV_INV_EN => "FALSE",
      DYN_CLK_INV_EN => "FALSE",
      INIT_Q1 => '0',
      INIT_Q2 => '0',
      INIT_Q3 => '0',
      INIT_Q4 => '0',
      INTERFACE_TYPE => "MEMORY_DDR3",
      IOBDELAY => "IFD",
      IS_CLKB_INVERTED => '1',
      IS_CLKDIVP_INVERTED => '0',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D_INVERTED => '0',
      IS_OCLKB_INVERTED => '0',
      IS_OCLK_INVERTED => '0',
      NUM_CE => 2,
      OFB_USED => "FALSE",
      SERDES_MODE => "MASTER",
      SRVAL_Q1 => '0',
      SRVAL_Q2 => '0',
      SRVAL_Q3 => '0',
      SRVAL_Q4 => '0'
    )
        port map (
      BITSLIP => '0',
      CE1 => '1',
      CE2 => '1',
      CLK => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]\,
      CLKB => CLKB0_8,
      CLKDIV => \NLW_input_[7].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED\,
      CLKDIVP => iserdes_clkdiv,
      D => mem_dq_in(5),
      DDLY => data_in_dly_7,
      DYNCLKDIVSEL => '0',
      DYNCLKSEL => '0',
      O => \NLW_input_[7].iserdes_dq_.iserdesdq_O_UNCONNECTED\,
      OCLK => oserdes_clk,
      OCLKB => \NLW_input_[7].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED\,
      OFB => \NLW_input_[7].iserdes_dq_.iserdesdq_OFB_UNCONNECTED\,
      Q1 => D7(3),
      Q2 => D7(2),
      Q3 => D7(1),
      Q4 => D7(0),
      Q5 => \NLW_input_[7].iserdes_dq_.iserdesdq_Q5_UNCONNECTED\,
      Q6 => \NLW_input_[7].iserdes_dq_.iserdesdq_Q6_UNCONNECTED\,
      Q7 => \NLW_input_[7].iserdes_dq_.iserdesdq_Q7_UNCONNECTED\,
      Q8 => \NLW_input_[7].iserdes_dq_.iserdesdq_Q8_UNCONNECTED\,
      RST => '0',
      SHIFTIN1 => '0',
      SHIFTIN2 => '0',
      SHIFTOUT1 => \NLW_input_[7].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_input_[7].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED\
    );
\input_[8].iserdes_dq_.idelay_dq.idelaye2\: unisim.vcomponents.IDELAYE2
    generic map(
      CINVCTRL_SEL => "FALSE",
      DELAY_SRC => "IDATAIN",
      HIGH_PERFORMANCE_MODE => "TRUE",
      IDELAY_TYPE => "VARIABLE",
      IDELAY_VALUE => 0,
      IS_C_INVERTED => '0',
      IS_DATAIN_INVERTED => '0',
      IS_IDATAIN_INVERTED => '0',
      PIPE_SEL => "FALSE",
      REFCLK_FREQUENCY => 200.000000,
      SIGNAL_PATTERN => "DATA"
    )
        port map (
      C => idelay_ld_rst_reg_0,
      CE => \input_[9].iserdes_dq_.iserdesdq_0\,
      CINVCTRL => '0',
      CNTVALUEIN(4 downto 0) => B"00000",
      CNTVALUEOUT(4 downto 0) => \NLW_input_[8].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED\(4 downto 0),
      DATAIN => '0',
      DATAOUT => data_in_dly_8,
      IDATAIN => mem_dq_in(6),
      INC => idelay_inc,
      LD => LD0_8,
      LDPIPEEN => '0',
      REGRST => A_rst_primitives
    );
\input_[8].iserdes_dq_.iserdesdq\: unisim.vcomponents.ISERDESE2
    generic map(
      DATA_RATE => "DDR",
      DATA_WIDTH => 4,
      DYN_CLKDIV_INV_EN => "FALSE",
      DYN_CLK_INV_EN => "FALSE",
      INIT_Q1 => '0',
      INIT_Q2 => '0',
      INIT_Q3 => '0',
      INIT_Q4 => '0',
      INTERFACE_TYPE => "MEMORY_DDR3",
      IOBDELAY => "IFD",
      IS_CLKB_INVERTED => '1',
      IS_CLKDIVP_INVERTED => '0',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D_INVERTED => '0',
      IS_OCLKB_INVERTED => '0',
      IS_OCLK_INVERTED => '0',
      NUM_CE => 2,
      OFB_USED => "FALSE",
      SERDES_MODE => "MASTER",
      SRVAL_Q1 => '0',
      SRVAL_Q2 => '0',
      SRVAL_Q3 => '0',
      SRVAL_Q4 => '0'
    )
        port map (
      BITSLIP => '0',
      CE1 => '1',
      CE2 => '1',
      CLK => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]\,
      CLKB => CLKB0_8,
      CLKDIV => \NLW_input_[8].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED\,
      CLKDIVP => iserdes_clkdiv,
      D => mem_dq_in(6),
      DDLY => data_in_dly_8,
      DYNCLKDIVSEL => '0',
      DYNCLKSEL => '0',
      O => \NLW_input_[8].iserdes_dq_.iserdesdq_O_UNCONNECTED\,
      OCLK => oserdes_clk,
      OCLKB => \NLW_input_[8].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED\,
      OFB => \NLW_input_[8].iserdes_dq_.iserdesdq_OFB_UNCONNECTED\,
      Q1 => D8(3),
      Q2 => D8(2),
      Q3 => D8(1),
      Q4 => D8(0),
      Q5 => \NLW_input_[8].iserdes_dq_.iserdesdq_Q5_UNCONNECTED\,
      Q6 => \NLW_input_[8].iserdes_dq_.iserdesdq_Q6_UNCONNECTED\,
      Q7 => \NLW_input_[8].iserdes_dq_.iserdesdq_Q7_UNCONNECTED\,
      Q8 => \NLW_input_[8].iserdes_dq_.iserdesdq_Q8_UNCONNECTED\,
      RST => '0',
      SHIFTIN1 => '0',
      SHIFTIN2 => '0',
      SHIFTOUT1 => \NLW_input_[8].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_input_[8].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED\
    );
\input_[9].iserdes_dq_.idelay_dq.idelaye2\: unisim.vcomponents.IDELAYE2
    generic map(
      CINVCTRL_SEL => "FALSE",
      DELAY_SRC => "IDATAIN",
      HIGH_PERFORMANCE_MODE => "TRUE",
      IDELAY_TYPE => "VARIABLE",
      IDELAY_VALUE => 0,
      IS_C_INVERTED => '0',
      IS_DATAIN_INVERTED => '0',
      IS_IDATAIN_INVERTED => '0',
      PIPE_SEL => "FALSE",
      REFCLK_FREQUENCY => 200.000000,
      SIGNAL_PATTERN => "DATA"
    )
        port map (
      C => idelay_ld_rst_reg_0,
      CE => \input_[9].iserdes_dq_.iserdesdq_0\,
      CINVCTRL => '0',
      CNTVALUEIN(4 downto 0) => B"00000",
      CNTVALUEOUT(4 downto 0) => \NLW_input_[9].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED\(4 downto 0),
      DATAIN => '0',
      DATAOUT => data_in_dly_9,
      IDATAIN => mem_dq_in(7),
      INC => idelay_inc,
      LD => LD0_8,
      LDPIPEEN => '0',
      REGRST => A_rst_primitives
    );
\input_[9].iserdes_dq_.iserdesdq\: unisim.vcomponents.ISERDESE2
    generic map(
      DATA_RATE => "DDR",
      DATA_WIDTH => 4,
      DYN_CLKDIV_INV_EN => "FALSE",
      DYN_CLK_INV_EN => "FALSE",
      INIT_Q1 => '0',
      INIT_Q2 => '0',
      INIT_Q3 => '0',
      INIT_Q4 => '0',
      INTERFACE_TYPE => "MEMORY_DDR3",
      IOBDELAY => "IFD",
      IS_CLKB_INVERTED => '1',
      IS_CLKDIVP_INVERTED => '0',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D_INVERTED => '0',
      IS_OCLKB_INVERTED => '0',
      IS_OCLK_INVERTED => '0',
      NUM_CE => 2,
      OFB_USED => "FALSE",
      SERDES_MODE => "MASTER",
      SRVAL_Q1 => '0',
      SRVAL_Q2 => '0',
      SRVAL_Q3 => '0',
      SRVAL_Q4 => '0'
    )
        port map (
      BITSLIP => '0',
      CE1 => '1',
      CE2 => '1',
      CLK => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]\,
      CLKB => CLKB0_8,
      CLKDIV => \NLW_input_[9].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED\,
      CLKDIVP => iserdes_clkdiv,
      D => mem_dq_in(7),
      DDLY => data_in_dly_9,
      DYNCLKDIVSEL => '0',
      DYNCLKSEL => '0',
      O => \NLW_input_[9].iserdes_dq_.iserdesdq_O_UNCONNECTED\,
      OCLK => oserdes_clk,
      OCLKB => \NLW_input_[9].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED\,
      OFB => \NLW_input_[9].iserdes_dq_.iserdesdq_OFB_UNCONNECTED\,
      Q1 => D9(3),
      Q2 => D9(2),
      Q3 => D9(1),
      Q4 => D9(0),
      Q5 => \NLW_input_[9].iserdes_dq_.iserdesdq_Q5_UNCONNECTED\,
      Q6 => \NLW_input_[9].iserdes_dq_.iserdesdq_Q6_UNCONNECTED\,
      Q7 => \NLW_input_[9].iserdes_dq_.iserdesdq_Q7_UNCONNECTED\,
      Q8 => \NLW_input_[9].iserdes_dq_.iserdesdq_Q8_UNCONNECTED\,
      RST => '0',
      SHIFTIN1 => '0',
      SHIFTIN2 => '0',
      SHIFTOUT1 => \NLW_input_[9].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_input_[9].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED\
    );
\output_[1].oserdes_dq_.ddr.oserdes_dq_i\: unisim.vcomponents.OSERDESE2
    generic map(
      DATA_RATE_OQ => "DDR",
      DATA_RATE_TQ => "DDR",
      DATA_WIDTH => 4,
      INIT_OQ => '1',
      INIT_TQ => '1',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D1_INVERTED => '0',
      IS_D2_INVERTED => '0',
      IS_D3_INVERTED => '0',
      IS_D4_INVERTED => '0',
      IS_D5_INVERTED => '0',
      IS_D6_INVERTED => '0',
      IS_D7_INVERTED => '0',
      IS_D8_INVERTED => '0',
      IS_T1_INVERTED => '0',
      IS_T2_INVERTED => '0',
      IS_T3_INVERTED => '0',
      IS_T4_INVERTED => '0',
      SERDES_MODE => "MASTER",
      SRVAL_OQ => '1',
      SRVAL_TQ => '1',
      TBYTE_CTL => "TRUE",
      TBYTE_SRC => "FALSE",
      TRISTATE_WIDTH => 4
    )
        port map (
      CLK => oserdes_clk,
      CLKDIV => oserdes_clkdiv,
      D1 => of_dqbus(0),
      D2 => of_dqbus(1),
      D3 => of_dqbus(2),
      D4 => of_dqbus(3),
      D5 => '0',
      D6 => '0',
      D7 => '0',
      D8 => '0',
      OCE => '1',
      OFB => \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\,
      OQ => mem_dq_out(0),
      RST => po_oserdes_rst,
      SHIFTIN1 => \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\,
      SHIFTIN2 => \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\,
      SHIFTOUT1 => \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\,
      T1 => '0',
      T2 => '0',
      T3 => '0',
      T4 => '0',
      TBYTEIN => tbyte_out,
      TBYTEOUT => \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\,
      TCE => '1',
      TFB => \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\,
      TQ => mem_dq_ts(0)
    );
\output_[2].oserdes_dq_.ddr.oserdes_dq_i\: unisim.vcomponents.OSERDESE2
    generic map(
      DATA_RATE_OQ => "DDR",
      DATA_RATE_TQ => "DDR",
      DATA_WIDTH => 4,
      INIT_OQ => '1',
      INIT_TQ => '1',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D1_INVERTED => '0',
      IS_D2_INVERTED => '0',
      IS_D3_INVERTED => '0',
      IS_D4_INVERTED => '0',
      IS_D5_INVERTED => '0',
      IS_D6_INVERTED => '0',
      IS_D7_INVERTED => '0',
      IS_D8_INVERTED => '0',
      IS_T1_INVERTED => '0',
      IS_T2_INVERTED => '0',
      IS_T3_INVERTED => '0',
      IS_T4_INVERTED => '0',
      SERDES_MODE => "MASTER",
      SRVAL_OQ => '1',
      SRVAL_TQ => '1',
      TBYTE_CTL => "TRUE",
      TBYTE_SRC => "FALSE",
      TRISTATE_WIDTH => 4
    )
        port map (
      CLK => oserdes_clk,
      CLKDIV => oserdes_clkdiv,
      D1 => of_dqbus(4),
      D2 => of_dqbus(5),
      D3 => of_dqbus(6),
      D4 => of_dqbus(7),
      D5 => '0',
      D6 => '0',
      D7 => '0',
      D8 => '0',
      OCE => '1',
      OFB => \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\,
      OQ => mem_dq_out(1),
      RST => po_oserdes_rst,
      SHIFTIN1 => \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\,
      SHIFTIN2 => \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\,
      SHIFTOUT1 => \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\,
      T1 => '0',
      T2 => '0',
      T3 => '0',
      T4 => '0',
      TBYTEIN => tbyte_out,
      TBYTEOUT => \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\,
      TCE => '1',
      TFB => \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\,
      TQ => mem_dq_ts(1)
    );
\output_[3].oserdes_dq_.ddr.oserdes_dq_i\: unisim.vcomponents.OSERDESE2
    generic map(
      DATA_RATE_OQ => "DDR",
      DATA_RATE_TQ => "DDR",
      DATA_WIDTH => 4,
      INIT_OQ => '1',
      INIT_TQ => '1',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D1_INVERTED => '0',
      IS_D2_INVERTED => '0',
      IS_D3_INVERTED => '0',
      IS_D4_INVERTED => '0',
      IS_D5_INVERTED => '0',
      IS_D6_INVERTED => '0',
      IS_D7_INVERTED => '0',
      IS_D8_INVERTED => '0',
      IS_T1_INVERTED => '0',
      IS_T2_INVERTED => '0',
      IS_T3_INVERTED => '0',
      IS_T4_INVERTED => '0',
      SERDES_MODE => "MASTER",
      SRVAL_OQ => '1',
      SRVAL_TQ => '1',
      TBYTE_CTL => "TRUE",
      TBYTE_SRC => "FALSE",
      TRISTATE_WIDTH => 4
    )
        port map (
      CLK => oserdes_clk,
      CLKDIV => oserdes_clkdiv,
      D1 => of_dqbus(8),
      D2 => of_dqbus(9),
      D3 => of_dqbus(10),
      D4 => of_dqbus(11),
      D5 => '0',
      D6 => '0',
      D7 => '0',
      D8 => '0',
      OCE => '1',
      OFB => \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\,
      OQ => mem_dq_out(2),
      RST => po_oserdes_rst,
      SHIFTIN1 => \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\,
      SHIFTIN2 => \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\,
      SHIFTOUT1 => \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\,
      T1 => '0',
      T2 => '0',
      T3 => '0',
      T4 => '0',
      TBYTEIN => tbyte_out,
      TBYTEOUT => \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\,
      TCE => '1',
      TFB => \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\,
      TQ => mem_dq_ts(2)
    );
\output_[4].oserdes_dq_.ddr.oserdes_dq_i\: unisim.vcomponents.OSERDESE2
    generic map(
      DATA_RATE_OQ => "DDR",
      DATA_RATE_TQ => "DDR",
      DATA_WIDTH => 4,
      INIT_OQ => '1',
      INIT_TQ => '1',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D1_INVERTED => '0',
      IS_D2_INVERTED => '0',
      IS_D3_INVERTED => '0',
      IS_D4_INVERTED => '0',
      IS_D5_INVERTED => '0',
      IS_D6_INVERTED => '0',
      IS_D7_INVERTED => '0',
      IS_D8_INVERTED => '0',
      IS_T1_INVERTED => '0',
      IS_T2_INVERTED => '0',
      IS_T3_INVERTED => '0',
      IS_T4_INVERTED => '0',
      SERDES_MODE => "MASTER",
      SRVAL_OQ => '1',
      SRVAL_TQ => '1',
      TBYTE_CTL => "TRUE",
      TBYTE_SRC => "FALSE",
      TRISTATE_WIDTH => 4
    )
        port map (
      CLK => oserdes_clk,
      CLKDIV => oserdes_clkdiv,
      D1 => of_dqbus(12),
      D2 => of_dqbus(13),
      D3 => of_dqbus(14),
      D4 => of_dqbus(15),
      D5 => '0',
      D6 => '0',
      D7 => '0',
      D8 => '0',
      OCE => '1',
      OFB => \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\,
      OQ => mem_dq_out(3),
      RST => po_oserdes_rst,
      SHIFTIN1 => \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\,
      SHIFTIN2 => \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\,
      SHIFTOUT1 => \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\,
      T1 => '0',
      T2 => '0',
      T3 => '0',
      T4 => '0',
      TBYTEIN => tbyte_out,
      TBYTEOUT => \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\,
      TCE => '1',
      TFB => \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\,
      TQ => mem_dq_ts(3)
    );
\output_[5].oserdes_dq_.ddr.oserdes_dq_i\: unisim.vcomponents.OSERDESE2
    generic map(
      DATA_RATE_OQ => "DDR",
      DATA_RATE_TQ => "DDR",
      DATA_WIDTH => 4,
      INIT_OQ => '1',
      INIT_TQ => '1',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D1_INVERTED => '0',
      IS_D2_INVERTED => '0',
      IS_D3_INVERTED => '0',
      IS_D4_INVERTED => '0',
      IS_D5_INVERTED => '0',
      IS_D6_INVERTED => '0',
      IS_D7_INVERTED => '0',
      IS_D8_INVERTED => '0',
      IS_T1_INVERTED => '0',
      IS_T2_INVERTED => '0',
      IS_T3_INVERTED => '0',
      IS_T4_INVERTED => '0',
      SERDES_MODE => "MASTER",
      SRVAL_OQ => '1',
      SRVAL_TQ => '1',
      TBYTE_CTL => "TRUE",
      TBYTE_SRC => "FALSE",
      TRISTATE_WIDTH => 4
    )
        port map (
      CLK => oserdes_clk,
      CLKDIV => oserdes_clkdiv,
      D1 => of_dqbus(16),
      D2 => of_dqbus(17),
      D3 => of_dqbus(18),
      D4 => of_dqbus(19),
      D5 => '0',
      D6 => '0',
      D7 => '0',
      D8 => '0',
      OCE => '1',
      OFB => \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\,
      OQ => mem_dq_out(4),
      RST => po_oserdes_rst,
      SHIFTIN1 => \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\,
      SHIFTIN2 => \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\,
      SHIFTOUT1 => \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\,
      T1 => '0',
      T2 => '0',
      T3 => '0',
      T4 => '0',
      TBYTEIN => tbyte_out,
      TBYTEOUT => \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\,
      TCE => '1',
      TFB => \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\,
      TQ => mem_dq_ts(4)
    );
\output_[6].oserdes_dq_.ddr.oserdes_dq_i\: unisim.vcomponents.OSERDESE2
    generic map(
      DATA_RATE_OQ => "DDR",
      DATA_RATE_TQ => "DDR",
      DATA_WIDTH => 4,
      INIT_OQ => '1',
      INIT_TQ => '1',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D1_INVERTED => '0',
      IS_D2_INVERTED => '0',
      IS_D3_INVERTED => '0',
      IS_D4_INVERTED => '0',
      IS_D5_INVERTED => '0',
      IS_D6_INVERTED => '0',
      IS_D7_INVERTED => '0',
      IS_D8_INVERTED => '0',
      IS_T1_INVERTED => '0',
      IS_T2_INVERTED => '0',
      IS_T3_INVERTED => '0',
      IS_T4_INVERTED => '0',
      SERDES_MODE => "MASTER",
      SRVAL_OQ => '1',
      SRVAL_TQ => '1',
      TBYTE_CTL => "TRUE",
      TBYTE_SRC => "FALSE",
      TRISTATE_WIDTH => 4
    )
        port map (
      CLK => oserdes_clk,
      CLKDIV => oserdes_clkdiv,
      D1 => of_dqbus(20),
      D2 => of_dqbus(21),
      D3 => of_dqbus(22),
      D4 => of_dqbus(23),
      D5 => '0',
      D6 => '0',
      D7 => '0',
      D8 => '0',
      OCE => '1',
      OFB => \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\,
      OQ => mem_dq_out(5),
      RST => po_oserdes_rst,
      SHIFTIN1 => \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\,
      SHIFTIN2 => \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\,
      SHIFTOUT1 => \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\,
      T1 => '0',
      T2 => '0',
      T3 => '0',
      T4 => '0',
      TBYTEIN => tbyte_out,
      TBYTEOUT => \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\,
      TCE => '1',
      TFB => \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\,
      TQ => mem_dq_ts(5)
    );
\output_[7].oserdes_dq_.ddr.oserdes_dq_i\: unisim.vcomponents.OSERDESE2
    generic map(
      DATA_RATE_OQ => "DDR",
      DATA_RATE_TQ => "DDR",
      DATA_WIDTH => 4,
      INIT_OQ => '1',
      INIT_TQ => '1',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D1_INVERTED => '0',
      IS_D2_INVERTED => '0',
      IS_D3_INVERTED => '0',
      IS_D4_INVERTED => '0',
      IS_D5_INVERTED => '0',
      IS_D6_INVERTED => '0',
      IS_D7_INVERTED => '0',
      IS_D8_INVERTED => '0',
      IS_T1_INVERTED => '0',
      IS_T2_INVERTED => '0',
      IS_T3_INVERTED => '0',
      IS_T4_INVERTED => '0',
      SERDES_MODE => "MASTER",
      SRVAL_OQ => '1',
      SRVAL_TQ => '1',
      TBYTE_CTL => "TRUE",
      TBYTE_SRC => "FALSE",
      TRISTATE_WIDTH => 4
    )
        port map (
      CLK => oserdes_clk,
      CLKDIV => oserdes_clkdiv,
      D1 => of_dqbus(24),
      D2 => of_dqbus(25),
      D3 => of_dqbus(26),
      D4 => of_dqbus(27),
      D5 => '0',
      D6 => '0',
      D7 => '0',
      D8 => '0',
      OCE => '1',
      OFB => \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\,
      OQ => mem_dq_out(6),
      RST => po_oserdes_rst,
      SHIFTIN1 => \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\,
      SHIFTIN2 => \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\,
      SHIFTOUT1 => \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\,
      T1 => '0',
      T2 => '0',
      T3 => '0',
      T4 => '0',
      TBYTEIN => tbyte_out,
      TBYTEOUT => \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\,
      TCE => '1',
      TFB => \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\,
      TQ => mem_dq_ts(6)
    );
\output_[8].oserdes_dq_.ddr.oserdes_dq_i\: unisim.vcomponents.OSERDESE2
    generic map(
      DATA_RATE_OQ => "DDR",
      DATA_RATE_TQ => "DDR",
      DATA_WIDTH => 4,
      INIT_OQ => '1',
      INIT_TQ => '1',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D1_INVERTED => '0',
      IS_D2_INVERTED => '0',
      IS_D3_INVERTED => '0',
      IS_D4_INVERTED => '0',
      IS_D5_INVERTED => '0',
      IS_D6_INVERTED => '0',
      IS_D7_INVERTED => '0',
      IS_D8_INVERTED => '0',
      IS_T1_INVERTED => '0',
      IS_T2_INVERTED => '0',
      IS_T3_INVERTED => '0',
      IS_T4_INVERTED => '0',
      SERDES_MODE => "MASTER",
      SRVAL_OQ => '1',
      SRVAL_TQ => '1',
      TBYTE_CTL => "TRUE",
      TBYTE_SRC => "FALSE",
      TRISTATE_WIDTH => 4
    )
        port map (
      CLK => oserdes_clk,
      CLKDIV => oserdes_clkdiv,
      D1 => of_dqbus(28),
      D2 => of_dqbus(29),
      D3 => of_dqbus(30),
      D4 => of_dqbus(31),
      D5 => '0',
      D6 => '0',
      D7 => '0',
      D8 => '0',
      OCE => '1',
      OFB => \NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\,
      OQ => mem_dq_out(7),
      RST => po_oserdes_rst,
      SHIFTIN1 => \NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\,
      SHIFTIN2 => \NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\,
      SHIFTOUT1 => \NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\,
      T1 => '0',
      T2 => '0',
      T3 => '0',
      T4 => '0',
      TBYTEIN => tbyte_out,
      TBYTEOUT => \NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\,
      TCE => '1',
      TFB => \NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\,
      TQ => mem_dq_ts(7)
    );
\output_[9].oserdes_dq_.ddr.oserdes_dq_i\: unisim.vcomponents.OSERDESE2
    generic map(
      DATA_RATE_OQ => "DDR",
      DATA_RATE_TQ => "DDR",
      DATA_WIDTH => 4,
      INIT_OQ => '1',
      INIT_TQ => '1',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D1_INVERTED => '0',
      IS_D2_INVERTED => '0',
      IS_D3_INVERTED => '0',
      IS_D4_INVERTED => '0',
      IS_D5_INVERTED => '0',
      IS_D6_INVERTED => '0',
      IS_D7_INVERTED => '0',
      IS_D8_INVERTED => '0',
      IS_T1_INVERTED => '0',
      IS_T2_INVERTED => '0',
      IS_T3_INVERTED => '0',
      IS_T4_INVERTED => '0',
      SERDES_MODE => "MASTER",
      SRVAL_OQ => '1',
      SRVAL_TQ => '1',
      TBYTE_CTL => "TRUE",
      TBYTE_SRC => "FALSE",
      TRISTATE_WIDTH => 4
    )
        port map (
      CLK => oserdes_clk,
      CLKDIV => oserdes_clkdiv,
      D1 => of_dqbus(32),
      D2 => of_dqbus(33),
      D3 => of_dqbus(34),
      D4 => of_dqbus(35),
      D5 => '0',
      D6 => '0',
      D7 => '0',
      D8 => '0',
      OCE => '1',
      OFB => \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\,
      OQ => mem_dq_out(8),
      RST => po_oserdes_rst,
      SHIFTIN1 => \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\,
      SHIFTIN2 => \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\,
      SHIFTOUT1 => \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\,
      T1 => '0',
      T2 => '0',
      T3 => '0',
      T4 => '0',
      TBYTEIN => tbyte_out,
      TBYTEOUT => \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\,
      TCE => '1',
      TFB => \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\,
      TQ => mem_dq_ts(8)
    );
\slave_ts.oserdes_slave_ts\: unisim.vcomponents.OSERDESE2
    generic map(
      DATA_RATE_OQ => "DDR",
      DATA_RATE_TQ => "DDR",
      DATA_WIDTH => 4,
      INIT_OQ => '1',
      INIT_TQ => '1',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D1_INVERTED => '0',
      IS_D2_INVERTED => '0',
      IS_D3_INVERTED => '0',
      IS_D4_INVERTED => '0',
      IS_D5_INVERTED => '0',
      IS_D6_INVERTED => '0',
      IS_D7_INVERTED => '0',
      IS_D8_INVERTED => '0',
      IS_T1_INVERTED => '0',
      IS_T2_INVERTED => '0',
      IS_T3_INVERTED => '0',
      IS_T4_INVERTED => '0',
      SERDES_MODE => "MASTER",
      SRVAL_OQ => '1',
      SRVAL_TQ => '1',
      TBYTE_CTL => "TRUE",
      TBYTE_SRC => "TRUE",
      TRISTATE_WIDTH => 4
    )
        port map (
      CLK => oserdes_clk,
      CLKDIV => oserdes_clkdiv,
      D1 => '0',
      D2 => '0',
      D3 => '0',
      D4 => '0',
      D5 => '0',
      D6 => '0',
      D7 => '0',
      D8 => '0',
      OCE => '1',
      OFB => \NLW_slave_ts.oserdes_slave_ts_OFB_UNCONNECTED\,
      OQ => \NLW_slave_ts.oserdes_slave_ts_OQ_UNCONNECTED\,
      RST => po_oserdes_rst,
      SHIFTIN1 => \NLW_slave_ts.oserdes_slave_ts_SHIFTIN1_UNCONNECTED\,
      SHIFTIN2 => \NLW_slave_ts.oserdes_slave_ts_SHIFTIN2_UNCONNECTED\,
      SHIFTOUT1 => \NLW_slave_ts.oserdes_slave_ts_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_slave_ts.oserdes_slave_ts_SHIFTOUT2_UNCONNECTED\,
      T1 => DTSBUS(0),
      T2 => DTSBUS(0),
      T3 => DTSBUS(1),
      T4 => DTSBUS(1),
      TBYTEIN => tbyte_out,
      TBYTEOUT => tbyte_out,
      TCE => '1',
      TFB => \NLW_slave_ts.oserdes_slave_ts_TFB_UNCONNECTED\,
      TQ => \NLW_slave_ts.oserdes_slave_ts_TQ_UNCONNECTED\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \mig_mig_7series_v4_2_ddr_byte_group_io__parameterized0_35\ is
  port (
    out_dqs_5 : out STD_LOGIC;
    ts_dqs_5 : out STD_LOGIC;
    D2 : out STD_LOGIC_VECTOR ( 3 downto 0 );
    D3 : out STD_LOGIC_VECTOR ( 3 downto 0 );
    D4 : out STD_LOGIC_VECTOR ( 3 downto 0 );
    D5 : out STD_LOGIC_VECTOR ( 3 downto 0 );
    D6 : out STD_LOGIC_VECTOR ( 3 downto 0 );
    D7 : out STD_LOGIC_VECTOR ( 3 downto 0 );
    D8 : out STD_LOGIC_VECTOR ( 3 downto 0 );
    D9 : out STD_LOGIC_VECTOR ( 3 downto 0 );
    mem_dq_out : out STD_LOGIC_VECTOR ( 8 downto 0 );
    mem_dq_ts : out STD_LOGIC_VECTOR ( 8 downto 0 );
    idelay_ld_rst_0 : out STD_LOGIC;
    oserdes_clk : in STD_LOGIC;
    oserdes_clkdiv : in STD_LOGIC;
    po_oserdes_rst : in STD_LOGIC;
    DTSBUS : in STD_LOGIC_VECTOR ( 1 downto 0 );
    oserdes_clk_delayed : in STD_LOGIC;
    DQSBUS : in STD_LOGIC_VECTOR ( 1 downto 0 );
    CTSBUS : in STD_LOGIC_VECTOR ( 0 to 0 );
    idelay_ld_rst_reg_0 : in STD_LOGIC;
    \input_[9].iserdes_dq_.iserdesdq_0\ : in STD_LOGIC;
    mem_dq_in : in STD_LOGIC_VECTOR ( 7 downto 0 );
    idelay_inc : in STD_LOGIC;
    LD0_7 : in STD_LOGIC;
    A_rst_primitives : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]\ : in STD_LOGIC;
    CLKB0_7 : in STD_LOGIC;
    iserdes_clkdiv : in STD_LOGIC;
    of_dqbus : in STD_LOGIC_VECTOR ( 35 downto 0 );
    rst_r4 : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \mig_mig_7series_v4_2_ddr_byte_group_io__parameterized0_35\ : entity is "mig_7series_v4_2_ddr_byte_group_io";
end \mig_mig_7series_v4_2_ddr_byte_group_io__parameterized0_35\;

architecture STRUCTURE of \mig_mig_7series_v4_2_ddr_byte_group_io__parameterized0_35\ is
  signal data_in_dly_2 : STD_LOGIC;
  signal data_in_dly_3 : STD_LOGIC;
  signal data_in_dly_4 : STD_LOGIC;
  signal data_in_dly_5 : STD_LOGIC;
  signal data_in_dly_6 : STD_LOGIC;
  signal data_in_dly_7 : STD_LOGIC;
  signal data_in_dly_8 : STD_LOGIC;
  signal data_in_dly_9 : STD_LOGIC;
  signal \^idelay_ld_rst_0\ : STD_LOGIC;
  signal \idelay_ld_rst_i_1__0_n_0\ : STD_LOGIC;
  signal tbyte_out : STD_LOGIC;
  signal \NLW_dqs_gen.oddr_dqs_S_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_dqs_gen.oddr_dqsts_R_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[2].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal \NLW_input_[2].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[2].iserdes_dq_.iserdesdq_O_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[2].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[2].iserdes_dq_.iserdesdq_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[2].iserdes_dq_.iserdesdq_Q5_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[2].iserdes_dq_.iserdesdq_Q6_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[2].iserdes_dq_.iserdesdq_Q7_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[2].iserdes_dq_.iserdesdq_Q8_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[2].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[2].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[3].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal \NLW_input_[3].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[3].iserdes_dq_.iserdesdq_O_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[3].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[3].iserdes_dq_.iserdesdq_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[3].iserdes_dq_.iserdesdq_Q5_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[3].iserdes_dq_.iserdesdq_Q6_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[3].iserdes_dq_.iserdesdq_Q7_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[3].iserdes_dq_.iserdesdq_Q8_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[3].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[3].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[4].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal \NLW_input_[4].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[4].iserdes_dq_.iserdesdq_O_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[4].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[4].iserdes_dq_.iserdesdq_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[4].iserdes_dq_.iserdesdq_Q5_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[4].iserdes_dq_.iserdesdq_Q6_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[4].iserdes_dq_.iserdesdq_Q7_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[4].iserdes_dq_.iserdesdq_Q8_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[4].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[4].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[5].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal \NLW_input_[5].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[5].iserdes_dq_.iserdesdq_O_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[5].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[5].iserdes_dq_.iserdesdq_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[5].iserdes_dq_.iserdesdq_Q5_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[5].iserdes_dq_.iserdesdq_Q6_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[5].iserdes_dq_.iserdesdq_Q7_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[5].iserdes_dq_.iserdesdq_Q8_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[5].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[5].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[6].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal \NLW_input_[6].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[6].iserdes_dq_.iserdesdq_O_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[6].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[6].iserdes_dq_.iserdesdq_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[6].iserdes_dq_.iserdesdq_Q5_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[6].iserdes_dq_.iserdesdq_Q6_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[6].iserdes_dq_.iserdesdq_Q7_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[6].iserdes_dq_.iserdesdq_Q8_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[6].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[6].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[7].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal \NLW_input_[7].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[7].iserdes_dq_.iserdesdq_O_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[7].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[7].iserdes_dq_.iserdesdq_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[7].iserdes_dq_.iserdesdq_Q5_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[7].iserdes_dq_.iserdesdq_Q6_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[7].iserdes_dq_.iserdesdq_Q7_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[7].iserdes_dq_.iserdesdq_Q8_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[7].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[7].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[8].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal \NLW_input_[8].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[8].iserdes_dq_.iserdesdq_O_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[8].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[8].iserdes_dq_.iserdesdq_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[8].iserdes_dq_.iserdesdq_Q5_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[8].iserdes_dq_.iserdesdq_Q6_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[8].iserdes_dq_.iserdesdq_Q7_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[8].iserdes_dq_.iserdesdq_Q8_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[8].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[8].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[9].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal \NLW_input_[9].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[9].iserdes_dq_.iserdesdq_O_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[9].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[9].iserdes_dq_.iserdesdq_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[9].iserdes_dq_.iserdesdq_Q5_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[9].iserdes_dq_.iserdesdq_Q6_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[9].iserdes_dq_.iserdesdq_Q7_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[9].iserdes_dq_.iserdesdq_Q8_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[9].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[9].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_slave_ts.oserdes_slave_ts_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_slave_ts.oserdes_slave_ts_OQ_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_slave_ts.oserdes_slave_ts_SHIFTIN1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_slave_ts.oserdes_slave_ts_SHIFTIN2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_slave_ts.oserdes_slave_ts_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_slave_ts.oserdes_slave_ts_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_slave_ts.oserdes_slave_ts_TFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_slave_ts.oserdes_slave_ts_TQ_UNCONNECTED\ : STD_LOGIC;
  attribute BOX_TYPE : string;
  attribute BOX_TYPE of \dqs_gen.oddr_dqs\ : label is "PRIMITIVE";
  attribute \__SRVAL\ : string;
  attribute \__SRVAL\ of \dqs_gen.oddr_dqs\ : label is "FALSE";
  attribute BOX_TYPE of \dqs_gen.oddr_dqsts\ : label is "PRIMITIVE";
  attribute \__SRVAL\ of \dqs_gen.oddr_dqsts\ : label is "TRUE";
  attribute BOX_TYPE of \input_[2].iserdes_dq_.idelay_dq.idelaye2\ : label is "PRIMITIVE";
  attribute IODELAY_GROUP : string;
  attribute IODELAY_GROUP of \input_[2].iserdes_dq_.idelay_dq.idelaye2\ : label is "MIG_IODELAY_MIG0";
  attribute SIM_DELAY_D : integer;
  attribute SIM_DELAY_D of \input_[2].iserdes_dq_.idelay_dq.idelaye2\ : label is 0;
  attribute BOX_TYPE of \input_[2].iserdes_dq_.iserdesdq\ : label is "PRIMITIVE";
  attribute OPT_MODIFIED : string;
  attribute OPT_MODIFIED of \input_[2].iserdes_dq_.iserdesdq\ : label is "MLO";
  attribute BOX_TYPE of \input_[3].iserdes_dq_.idelay_dq.idelaye2\ : label is "PRIMITIVE";
  attribute IODELAY_GROUP of \input_[3].iserdes_dq_.idelay_dq.idelaye2\ : label is "MIG_IODELAY_MIG0";
  attribute SIM_DELAY_D of \input_[3].iserdes_dq_.idelay_dq.idelaye2\ : label is 0;
  attribute BOX_TYPE of \input_[3].iserdes_dq_.iserdesdq\ : label is "PRIMITIVE";
  attribute OPT_MODIFIED of \input_[3].iserdes_dq_.iserdesdq\ : label is "MLO";
  attribute BOX_TYPE of \input_[4].iserdes_dq_.idelay_dq.idelaye2\ : label is "PRIMITIVE";
  attribute IODELAY_GROUP of \input_[4].iserdes_dq_.idelay_dq.idelaye2\ : label is "MIG_IODELAY_MIG0";
  attribute SIM_DELAY_D of \input_[4].iserdes_dq_.idelay_dq.idelaye2\ : label is 0;
  attribute BOX_TYPE of \input_[4].iserdes_dq_.iserdesdq\ : label is "PRIMITIVE";
  attribute OPT_MODIFIED of \input_[4].iserdes_dq_.iserdesdq\ : label is "MLO";
  attribute BOX_TYPE of \input_[5].iserdes_dq_.idelay_dq.idelaye2\ : label is "PRIMITIVE";
  attribute IODELAY_GROUP of \input_[5].iserdes_dq_.idelay_dq.idelaye2\ : label is "MIG_IODELAY_MIG0";
  attribute SIM_DELAY_D of \input_[5].iserdes_dq_.idelay_dq.idelaye2\ : label is 0;
  attribute BOX_TYPE of \input_[5].iserdes_dq_.iserdesdq\ : label is "PRIMITIVE";
  attribute OPT_MODIFIED of \input_[5].iserdes_dq_.iserdesdq\ : label is "MLO";
  attribute BOX_TYPE of \input_[6].iserdes_dq_.idelay_dq.idelaye2\ : label is "PRIMITIVE";
  attribute IODELAY_GROUP of \input_[6].iserdes_dq_.idelay_dq.idelaye2\ : label is "MIG_IODELAY_MIG0";
  attribute SIM_DELAY_D of \input_[6].iserdes_dq_.idelay_dq.idelaye2\ : label is 0;
  attribute BOX_TYPE of \input_[6].iserdes_dq_.iserdesdq\ : label is "PRIMITIVE";
  attribute OPT_MODIFIED of \input_[6].iserdes_dq_.iserdesdq\ : label is "MLO";
  attribute BOX_TYPE of \input_[7].iserdes_dq_.idelay_dq.idelaye2\ : label is "PRIMITIVE";
  attribute IODELAY_GROUP of \input_[7].iserdes_dq_.idelay_dq.idelaye2\ : label is "MIG_IODELAY_MIG0";
  attribute SIM_DELAY_D of \input_[7].iserdes_dq_.idelay_dq.idelaye2\ : label is 0;
  attribute BOX_TYPE of \input_[7].iserdes_dq_.iserdesdq\ : label is "PRIMITIVE";
  attribute OPT_MODIFIED of \input_[7].iserdes_dq_.iserdesdq\ : label is "MLO";
  attribute BOX_TYPE of \input_[8].iserdes_dq_.idelay_dq.idelaye2\ : label is "PRIMITIVE";
  attribute IODELAY_GROUP of \input_[8].iserdes_dq_.idelay_dq.idelaye2\ : label is "MIG_IODELAY_MIG0";
  attribute SIM_DELAY_D of \input_[8].iserdes_dq_.idelay_dq.idelaye2\ : label is 0;
  attribute BOX_TYPE of \input_[8].iserdes_dq_.iserdesdq\ : label is "PRIMITIVE";
  attribute OPT_MODIFIED of \input_[8].iserdes_dq_.iserdesdq\ : label is "MLO";
  attribute BOX_TYPE of \input_[9].iserdes_dq_.idelay_dq.idelaye2\ : label is "PRIMITIVE";
  attribute IODELAY_GROUP of \input_[9].iserdes_dq_.idelay_dq.idelaye2\ : label is "MIG_IODELAY_MIG0";
  attribute SIM_DELAY_D of \input_[9].iserdes_dq_.idelay_dq.idelaye2\ : label is 0;
  attribute BOX_TYPE of \input_[9].iserdes_dq_.iserdesdq\ : label is "PRIMITIVE";
  attribute OPT_MODIFIED of \input_[9].iserdes_dq_.iserdesdq\ : label is "MLO";
  attribute BOX_TYPE of \output_[1].oserdes_dq_.ddr.oserdes_dq_i\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \output_[2].oserdes_dq_.ddr.oserdes_dq_i\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \output_[3].oserdes_dq_.ddr.oserdes_dq_i\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \output_[4].oserdes_dq_.ddr.oserdes_dq_i\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \output_[5].oserdes_dq_.ddr.oserdes_dq_i\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \output_[6].oserdes_dq_.ddr.oserdes_dq_i\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \output_[7].oserdes_dq_.ddr.oserdes_dq_i\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \output_[8].oserdes_dq_.ddr.oserdes_dq_i\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \output_[9].oserdes_dq_.ddr.oserdes_dq_i\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \slave_ts.oserdes_slave_ts\ : label is "PRIMITIVE";
begin
  idelay_ld_rst_0 <= \^idelay_ld_rst_0\;
\dqs_gen.oddr_dqs\: unisim.vcomponents.ODDR
    generic map(
      DDR_CLK_EDGE => "SAME_EDGE",
      INIT => '0',
      IS_C_INVERTED => '0',
      IS_D1_INVERTED => '0',
      IS_D2_INVERTED => '0',
      SRTYPE => "SYNC"
    )
        port map (
      C => oserdes_clk_delayed,
      CE => '1',
      D1 => DQSBUS(0),
      D2 => DQSBUS(1),
      Q => out_dqs_5,
      R => '0',
      S => \NLW_dqs_gen.oddr_dqs_S_UNCONNECTED\
    );
\dqs_gen.oddr_dqsts\: unisim.vcomponents.ODDR
    generic map(
      DDR_CLK_EDGE => "SAME_EDGE",
      INIT => '0',
      IS_C_INVERTED => '0',
      IS_D1_INVERTED => '0',
      IS_D2_INVERTED => '0',
      SRTYPE => "SYNC"
    )
        port map (
      C => oserdes_clk_delayed,
      CE => '1',
      D1 => CTSBUS(0),
      D2 => CTSBUS(0),
      Q => ts_dqs_5,
      R => \NLW_dqs_gen.oddr_dqsts_R_UNCONNECTED\,
      S => '0'
    );
\idelay_ld_rst_i_1__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \^idelay_ld_rst_0\,
      I1 => rst_r4,
      O => \idelay_ld_rst_i_1__0_n_0\
    );
idelay_ld_rst_reg: unisim.vcomponents.FDSE
     port map (
      C => idelay_ld_rst_reg_0,
      CE => '1',
      D => \idelay_ld_rst_i_1__0_n_0\,
      Q => \^idelay_ld_rst_0\,
      S => A_rst_primitives
    );
\input_[2].iserdes_dq_.idelay_dq.idelaye2\: unisim.vcomponents.IDELAYE2
    generic map(
      CINVCTRL_SEL => "FALSE",
      DELAY_SRC => "IDATAIN",
      HIGH_PERFORMANCE_MODE => "TRUE",
      IDELAY_TYPE => "VARIABLE",
      IDELAY_VALUE => 0,
      IS_C_INVERTED => '0',
      IS_DATAIN_INVERTED => '0',
      IS_IDATAIN_INVERTED => '0',
      PIPE_SEL => "FALSE",
      REFCLK_FREQUENCY => 200.000000,
      SIGNAL_PATTERN => "DATA"
    )
        port map (
      C => idelay_ld_rst_reg_0,
      CE => \input_[9].iserdes_dq_.iserdesdq_0\,
      CINVCTRL => '0',
      CNTVALUEIN(4 downto 0) => B"00000",
      CNTVALUEOUT(4 downto 0) => \NLW_input_[2].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED\(4 downto 0),
      DATAIN => '0',
      DATAOUT => data_in_dly_2,
      IDATAIN => mem_dq_in(0),
      INC => idelay_inc,
      LD => LD0_7,
      LDPIPEEN => '0',
      REGRST => A_rst_primitives
    );
\input_[2].iserdes_dq_.iserdesdq\: unisim.vcomponents.ISERDESE2
    generic map(
      DATA_RATE => "DDR",
      DATA_WIDTH => 4,
      DYN_CLKDIV_INV_EN => "FALSE",
      DYN_CLK_INV_EN => "FALSE",
      INIT_Q1 => '0',
      INIT_Q2 => '0',
      INIT_Q3 => '0',
      INIT_Q4 => '0',
      INTERFACE_TYPE => "MEMORY_DDR3",
      IOBDELAY => "IFD",
      IS_CLKB_INVERTED => '1',
      IS_CLKDIVP_INVERTED => '0',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D_INVERTED => '0',
      IS_OCLKB_INVERTED => '0',
      IS_OCLK_INVERTED => '0',
      NUM_CE => 2,
      OFB_USED => "FALSE",
      SERDES_MODE => "MASTER",
      SRVAL_Q1 => '0',
      SRVAL_Q2 => '0',
      SRVAL_Q3 => '0',
      SRVAL_Q4 => '0'
    )
        port map (
      BITSLIP => '0',
      CE1 => '1',
      CE2 => '1',
      CLK => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]\,
      CLKB => CLKB0_7,
      CLKDIV => \NLW_input_[2].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED\,
      CLKDIVP => iserdes_clkdiv,
      D => mem_dq_in(0),
      DDLY => data_in_dly_2,
      DYNCLKDIVSEL => '0',
      DYNCLKSEL => '0',
      O => \NLW_input_[2].iserdes_dq_.iserdesdq_O_UNCONNECTED\,
      OCLK => oserdes_clk,
      OCLKB => \NLW_input_[2].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED\,
      OFB => \NLW_input_[2].iserdes_dq_.iserdesdq_OFB_UNCONNECTED\,
      Q1 => D2(3),
      Q2 => D2(2),
      Q3 => D2(1),
      Q4 => D2(0),
      Q5 => \NLW_input_[2].iserdes_dq_.iserdesdq_Q5_UNCONNECTED\,
      Q6 => \NLW_input_[2].iserdes_dq_.iserdesdq_Q6_UNCONNECTED\,
      Q7 => \NLW_input_[2].iserdes_dq_.iserdesdq_Q7_UNCONNECTED\,
      Q8 => \NLW_input_[2].iserdes_dq_.iserdesdq_Q8_UNCONNECTED\,
      RST => '0',
      SHIFTIN1 => '0',
      SHIFTIN2 => '0',
      SHIFTOUT1 => \NLW_input_[2].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_input_[2].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED\
    );
\input_[3].iserdes_dq_.idelay_dq.idelaye2\: unisim.vcomponents.IDELAYE2
    generic map(
      CINVCTRL_SEL => "FALSE",
      DELAY_SRC => "IDATAIN",
      HIGH_PERFORMANCE_MODE => "TRUE",
      IDELAY_TYPE => "VARIABLE",
      IDELAY_VALUE => 0,
      IS_C_INVERTED => '0',
      IS_DATAIN_INVERTED => '0',
      IS_IDATAIN_INVERTED => '0',
      PIPE_SEL => "FALSE",
      REFCLK_FREQUENCY => 200.000000,
      SIGNAL_PATTERN => "DATA"
    )
        port map (
      C => idelay_ld_rst_reg_0,
      CE => \input_[9].iserdes_dq_.iserdesdq_0\,
      CINVCTRL => '0',
      CNTVALUEIN(4 downto 0) => B"00000",
      CNTVALUEOUT(4 downto 0) => \NLW_input_[3].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED\(4 downto 0),
      DATAIN => '0',
      DATAOUT => data_in_dly_3,
      IDATAIN => mem_dq_in(1),
      INC => idelay_inc,
      LD => LD0_7,
      LDPIPEEN => '0',
      REGRST => A_rst_primitives
    );
\input_[3].iserdes_dq_.iserdesdq\: unisim.vcomponents.ISERDESE2
    generic map(
      DATA_RATE => "DDR",
      DATA_WIDTH => 4,
      DYN_CLKDIV_INV_EN => "FALSE",
      DYN_CLK_INV_EN => "FALSE",
      INIT_Q1 => '0',
      INIT_Q2 => '0',
      INIT_Q3 => '0',
      INIT_Q4 => '0',
      INTERFACE_TYPE => "MEMORY_DDR3",
      IOBDELAY => "IFD",
      IS_CLKB_INVERTED => '1',
      IS_CLKDIVP_INVERTED => '0',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D_INVERTED => '0',
      IS_OCLKB_INVERTED => '0',
      IS_OCLK_INVERTED => '0',
      NUM_CE => 2,
      OFB_USED => "FALSE",
      SERDES_MODE => "MASTER",
      SRVAL_Q1 => '0',
      SRVAL_Q2 => '0',
      SRVAL_Q3 => '0',
      SRVAL_Q4 => '0'
    )
        port map (
      BITSLIP => '0',
      CE1 => '1',
      CE2 => '1',
      CLK => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]\,
      CLKB => CLKB0_7,
      CLKDIV => \NLW_input_[3].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED\,
      CLKDIVP => iserdes_clkdiv,
      D => mem_dq_in(1),
      DDLY => data_in_dly_3,
      DYNCLKDIVSEL => '0',
      DYNCLKSEL => '0',
      O => \NLW_input_[3].iserdes_dq_.iserdesdq_O_UNCONNECTED\,
      OCLK => oserdes_clk,
      OCLKB => \NLW_input_[3].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED\,
      OFB => \NLW_input_[3].iserdes_dq_.iserdesdq_OFB_UNCONNECTED\,
      Q1 => D3(3),
      Q2 => D3(2),
      Q3 => D3(1),
      Q4 => D3(0),
      Q5 => \NLW_input_[3].iserdes_dq_.iserdesdq_Q5_UNCONNECTED\,
      Q6 => \NLW_input_[3].iserdes_dq_.iserdesdq_Q6_UNCONNECTED\,
      Q7 => \NLW_input_[3].iserdes_dq_.iserdesdq_Q7_UNCONNECTED\,
      Q8 => \NLW_input_[3].iserdes_dq_.iserdesdq_Q8_UNCONNECTED\,
      RST => '0',
      SHIFTIN1 => '0',
      SHIFTIN2 => '0',
      SHIFTOUT1 => \NLW_input_[3].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_input_[3].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED\
    );
\input_[4].iserdes_dq_.idelay_dq.idelaye2\: unisim.vcomponents.IDELAYE2
    generic map(
      CINVCTRL_SEL => "FALSE",
      DELAY_SRC => "IDATAIN",
      HIGH_PERFORMANCE_MODE => "TRUE",
      IDELAY_TYPE => "VARIABLE",
      IDELAY_VALUE => 0,
      IS_C_INVERTED => '0',
      IS_DATAIN_INVERTED => '0',
      IS_IDATAIN_INVERTED => '0',
      PIPE_SEL => "FALSE",
      REFCLK_FREQUENCY => 200.000000,
      SIGNAL_PATTERN => "DATA"
    )
        port map (
      C => idelay_ld_rst_reg_0,
      CE => \input_[9].iserdes_dq_.iserdesdq_0\,
      CINVCTRL => '0',
      CNTVALUEIN(4 downto 0) => B"00000",
      CNTVALUEOUT(4 downto 0) => \NLW_input_[4].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED\(4 downto 0),
      DATAIN => '0',
      DATAOUT => data_in_dly_4,
      IDATAIN => mem_dq_in(2),
      INC => idelay_inc,
      LD => LD0_7,
      LDPIPEEN => '0',
      REGRST => A_rst_primitives
    );
\input_[4].iserdes_dq_.iserdesdq\: unisim.vcomponents.ISERDESE2
    generic map(
      DATA_RATE => "DDR",
      DATA_WIDTH => 4,
      DYN_CLKDIV_INV_EN => "FALSE",
      DYN_CLK_INV_EN => "FALSE",
      INIT_Q1 => '0',
      INIT_Q2 => '0',
      INIT_Q3 => '0',
      INIT_Q4 => '0',
      INTERFACE_TYPE => "MEMORY_DDR3",
      IOBDELAY => "IFD",
      IS_CLKB_INVERTED => '1',
      IS_CLKDIVP_INVERTED => '0',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D_INVERTED => '0',
      IS_OCLKB_INVERTED => '0',
      IS_OCLK_INVERTED => '0',
      NUM_CE => 2,
      OFB_USED => "FALSE",
      SERDES_MODE => "MASTER",
      SRVAL_Q1 => '0',
      SRVAL_Q2 => '0',
      SRVAL_Q3 => '0',
      SRVAL_Q4 => '0'
    )
        port map (
      BITSLIP => '0',
      CE1 => '1',
      CE2 => '1',
      CLK => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]\,
      CLKB => CLKB0_7,
      CLKDIV => \NLW_input_[4].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED\,
      CLKDIVP => iserdes_clkdiv,
      D => mem_dq_in(2),
      DDLY => data_in_dly_4,
      DYNCLKDIVSEL => '0',
      DYNCLKSEL => '0',
      O => \NLW_input_[4].iserdes_dq_.iserdesdq_O_UNCONNECTED\,
      OCLK => oserdes_clk,
      OCLKB => \NLW_input_[4].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED\,
      OFB => \NLW_input_[4].iserdes_dq_.iserdesdq_OFB_UNCONNECTED\,
      Q1 => D4(3),
      Q2 => D4(2),
      Q3 => D4(1),
      Q4 => D4(0),
      Q5 => \NLW_input_[4].iserdes_dq_.iserdesdq_Q5_UNCONNECTED\,
      Q6 => \NLW_input_[4].iserdes_dq_.iserdesdq_Q6_UNCONNECTED\,
      Q7 => \NLW_input_[4].iserdes_dq_.iserdesdq_Q7_UNCONNECTED\,
      Q8 => \NLW_input_[4].iserdes_dq_.iserdesdq_Q8_UNCONNECTED\,
      RST => '0',
      SHIFTIN1 => '0',
      SHIFTIN2 => '0',
      SHIFTOUT1 => \NLW_input_[4].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_input_[4].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED\
    );
\input_[5].iserdes_dq_.idelay_dq.idelaye2\: unisim.vcomponents.IDELAYE2
    generic map(
      CINVCTRL_SEL => "FALSE",
      DELAY_SRC => "IDATAIN",
      HIGH_PERFORMANCE_MODE => "TRUE",
      IDELAY_TYPE => "VARIABLE",
      IDELAY_VALUE => 0,
      IS_C_INVERTED => '0',
      IS_DATAIN_INVERTED => '0',
      IS_IDATAIN_INVERTED => '0',
      PIPE_SEL => "FALSE",
      REFCLK_FREQUENCY => 200.000000,
      SIGNAL_PATTERN => "DATA"
    )
        port map (
      C => idelay_ld_rst_reg_0,
      CE => \input_[9].iserdes_dq_.iserdesdq_0\,
      CINVCTRL => '0',
      CNTVALUEIN(4 downto 0) => B"00000",
      CNTVALUEOUT(4 downto 0) => \NLW_input_[5].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED\(4 downto 0),
      DATAIN => '0',
      DATAOUT => data_in_dly_5,
      IDATAIN => mem_dq_in(3),
      INC => idelay_inc,
      LD => LD0_7,
      LDPIPEEN => '0',
      REGRST => A_rst_primitives
    );
\input_[5].iserdes_dq_.iserdesdq\: unisim.vcomponents.ISERDESE2
    generic map(
      DATA_RATE => "DDR",
      DATA_WIDTH => 4,
      DYN_CLKDIV_INV_EN => "FALSE",
      DYN_CLK_INV_EN => "FALSE",
      INIT_Q1 => '0',
      INIT_Q2 => '0',
      INIT_Q3 => '0',
      INIT_Q4 => '0',
      INTERFACE_TYPE => "MEMORY_DDR3",
      IOBDELAY => "IFD",
      IS_CLKB_INVERTED => '1',
      IS_CLKDIVP_INVERTED => '0',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D_INVERTED => '0',
      IS_OCLKB_INVERTED => '0',
      IS_OCLK_INVERTED => '0',
      NUM_CE => 2,
      OFB_USED => "FALSE",
      SERDES_MODE => "MASTER",
      SRVAL_Q1 => '0',
      SRVAL_Q2 => '0',
      SRVAL_Q3 => '0',
      SRVAL_Q4 => '0'
    )
        port map (
      BITSLIP => '0',
      CE1 => '1',
      CE2 => '1',
      CLK => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]\,
      CLKB => CLKB0_7,
      CLKDIV => \NLW_input_[5].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED\,
      CLKDIVP => iserdes_clkdiv,
      D => mem_dq_in(3),
      DDLY => data_in_dly_5,
      DYNCLKDIVSEL => '0',
      DYNCLKSEL => '0',
      O => \NLW_input_[5].iserdes_dq_.iserdesdq_O_UNCONNECTED\,
      OCLK => oserdes_clk,
      OCLKB => \NLW_input_[5].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED\,
      OFB => \NLW_input_[5].iserdes_dq_.iserdesdq_OFB_UNCONNECTED\,
      Q1 => D5(3),
      Q2 => D5(2),
      Q3 => D5(1),
      Q4 => D5(0),
      Q5 => \NLW_input_[5].iserdes_dq_.iserdesdq_Q5_UNCONNECTED\,
      Q6 => \NLW_input_[5].iserdes_dq_.iserdesdq_Q6_UNCONNECTED\,
      Q7 => \NLW_input_[5].iserdes_dq_.iserdesdq_Q7_UNCONNECTED\,
      Q8 => \NLW_input_[5].iserdes_dq_.iserdesdq_Q8_UNCONNECTED\,
      RST => '0',
      SHIFTIN1 => '0',
      SHIFTIN2 => '0',
      SHIFTOUT1 => \NLW_input_[5].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_input_[5].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED\
    );
\input_[6].iserdes_dq_.idelay_dq.idelaye2\: unisim.vcomponents.IDELAYE2
    generic map(
      CINVCTRL_SEL => "FALSE",
      DELAY_SRC => "IDATAIN",
      HIGH_PERFORMANCE_MODE => "TRUE",
      IDELAY_TYPE => "VARIABLE",
      IDELAY_VALUE => 0,
      IS_C_INVERTED => '0',
      IS_DATAIN_INVERTED => '0',
      IS_IDATAIN_INVERTED => '0',
      PIPE_SEL => "FALSE",
      REFCLK_FREQUENCY => 200.000000,
      SIGNAL_PATTERN => "DATA"
    )
        port map (
      C => idelay_ld_rst_reg_0,
      CE => \input_[9].iserdes_dq_.iserdesdq_0\,
      CINVCTRL => '0',
      CNTVALUEIN(4 downto 0) => B"00000",
      CNTVALUEOUT(4 downto 0) => \NLW_input_[6].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED\(4 downto 0),
      DATAIN => '0',
      DATAOUT => data_in_dly_6,
      IDATAIN => mem_dq_in(4),
      INC => idelay_inc,
      LD => LD0_7,
      LDPIPEEN => '0',
      REGRST => A_rst_primitives
    );
\input_[6].iserdes_dq_.iserdesdq\: unisim.vcomponents.ISERDESE2
    generic map(
      DATA_RATE => "DDR",
      DATA_WIDTH => 4,
      DYN_CLKDIV_INV_EN => "FALSE",
      DYN_CLK_INV_EN => "FALSE",
      INIT_Q1 => '0',
      INIT_Q2 => '0',
      INIT_Q3 => '0',
      INIT_Q4 => '0',
      INTERFACE_TYPE => "MEMORY_DDR3",
      IOBDELAY => "IFD",
      IS_CLKB_INVERTED => '1',
      IS_CLKDIVP_INVERTED => '0',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D_INVERTED => '0',
      IS_OCLKB_INVERTED => '0',
      IS_OCLK_INVERTED => '0',
      NUM_CE => 2,
      OFB_USED => "FALSE",
      SERDES_MODE => "MASTER",
      SRVAL_Q1 => '0',
      SRVAL_Q2 => '0',
      SRVAL_Q3 => '0',
      SRVAL_Q4 => '0'
    )
        port map (
      BITSLIP => '0',
      CE1 => '1',
      CE2 => '1',
      CLK => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]\,
      CLKB => CLKB0_7,
      CLKDIV => \NLW_input_[6].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED\,
      CLKDIVP => iserdes_clkdiv,
      D => mem_dq_in(4),
      DDLY => data_in_dly_6,
      DYNCLKDIVSEL => '0',
      DYNCLKSEL => '0',
      O => \NLW_input_[6].iserdes_dq_.iserdesdq_O_UNCONNECTED\,
      OCLK => oserdes_clk,
      OCLKB => \NLW_input_[6].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED\,
      OFB => \NLW_input_[6].iserdes_dq_.iserdesdq_OFB_UNCONNECTED\,
      Q1 => D6(3),
      Q2 => D6(2),
      Q3 => D6(1),
      Q4 => D6(0),
      Q5 => \NLW_input_[6].iserdes_dq_.iserdesdq_Q5_UNCONNECTED\,
      Q6 => \NLW_input_[6].iserdes_dq_.iserdesdq_Q6_UNCONNECTED\,
      Q7 => \NLW_input_[6].iserdes_dq_.iserdesdq_Q7_UNCONNECTED\,
      Q8 => \NLW_input_[6].iserdes_dq_.iserdesdq_Q8_UNCONNECTED\,
      RST => '0',
      SHIFTIN1 => '0',
      SHIFTIN2 => '0',
      SHIFTOUT1 => \NLW_input_[6].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_input_[6].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED\
    );
\input_[7].iserdes_dq_.idelay_dq.idelaye2\: unisim.vcomponents.IDELAYE2
    generic map(
      CINVCTRL_SEL => "FALSE",
      DELAY_SRC => "IDATAIN",
      HIGH_PERFORMANCE_MODE => "TRUE",
      IDELAY_TYPE => "VARIABLE",
      IDELAY_VALUE => 0,
      IS_C_INVERTED => '0',
      IS_DATAIN_INVERTED => '0',
      IS_IDATAIN_INVERTED => '0',
      PIPE_SEL => "FALSE",
      REFCLK_FREQUENCY => 200.000000,
      SIGNAL_PATTERN => "DATA"
    )
        port map (
      C => idelay_ld_rst_reg_0,
      CE => \input_[9].iserdes_dq_.iserdesdq_0\,
      CINVCTRL => '0',
      CNTVALUEIN(4 downto 0) => B"00000",
      CNTVALUEOUT(4 downto 0) => \NLW_input_[7].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED\(4 downto 0),
      DATAIN => '0',
      DATAOUT => data_in_dly_7,
      IDATAIN => mem_dq_in(5),
      INC => idelay_inc,
      LD => LD0_7,
      LDPIPEEN => '0',
      REGRST => A_rst_primitives
    );
\input_[7].iserdes_dq_.iserdesdq\: unisim.vcomponents.ISERDESE2
    generic map(
      DATA_RATE => "DDR",
      DATA_WIDTH => 4,
      DYN_CLKDIV_INV_EN => "FALSE",
      DYN_CLK_INV_EN => "FALSE",
      INIT_Q1 => '0',
      INIT_Q2 => '0',
      INIT_Q3 => '0',
      INIT_Q4 => '0',
      INTERFACE_TYPE => "MEMORY_DDR3",
      IOBDELAY => "IFD",
      IS_CLKB_INVERTED => '1',
      IS_CLKDIVP_INVERTED => '0',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D_INVERTED => '0',
      IS_OCLKB_INVERTED => '0',
      IS_OCLK_INVERTED => '0',
      NUM_CE => 2,
      OFB_USED => "FALSE",
      SERDES_MODE => "MASTER",
      SRVAL_Q1 => '0',
      SRVAL_Q2 => '0',
      SRVAL_Q3 => '0',
      SRVAL_Q4 => '0'
    )
        port map (
      BITSLIP => '0',
      CE1 => '1',
      CE2 => '1',
      CLK => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]\,
      CLKB => CLKB0_7,
      CLKDIV => \NLW_input_[7].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED\,
      CLKDIVP => iserdes_clkdiv,
      D => mem_dq_in(5),
      DDLY => data_in_dly_7,
      DYNCLKDIVSEL => '0',
      DYNCLKSEL => '0',
      O => \NLW_input_[7].iserdes_dq_.iserdesdq_O_UNCONNECTED\,
      OCLK => oserdes_clk,
      OCLKB => \NLW_input_[7].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED\,
      OFB => \NLW_input_[7].iserdes_dq_.iserdesdq_OFB_UNCONNECTED\,
      Q1 => D7(3),
      Q2 => D7(2),
      Q3 => D7(1),
      Q4 => D7(0),
      Q5 => \NLW_input_[7].iserdes_dq_.iserdesdq_Q5_UNCONNECTED\,
      Q6 => \NLW_input_[7].iserdes_dq_.iserdesdq_Q6_UNCONNECTED\,
      Q7 => \NLW_input_[7].iserdes_dq_.iserdesdq_Q7_UNCONNECTED\,
      Q8 => \NLW_input_[7].iserdes_dq_.iserdesdq_Q8_UNCONNECTED\,
      RST => '0',
      SHIFTIN1 => '0',
      SHIFTIN2 => '0',
      SHIFTOUT1 => \NLW_input_[7].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_input_[7].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED\
    );
\input_[8].iserdes_dq_.idelay_dq.idelaye2\: unisim.vcomponents.IDELAYE2
    generic map(
      CINVCTRL_SEL => "FALSE",
      DELAY_SRC => "IDATAIN",
      HIGH_PERFORMANCE_MODE => "TRUE",
      IDELAY_TYPE => "VARIABLE",
      IDELAY_VALUE => 0,
      IS_C_INVERTED => '0',
      IS_DATAIN_INVERTED => '0',
      IS_IDATAIN_INVERTED => '0',
      PIPE_SEL => "FALSE",
      REFCLK_FREQUENCY => 200.000000,
      SIGNAL_PATTERN => "DATA"
    )
        port map (
      C => idelay_ld_rst_reg_0,
      CE => \input_[9].iserdes_dq_.iserdesdq_0\,
      CINVCTRL => '0',
      CNTVALUEIN(4 downto 0) => B"00000",
      CNTVALUEOUT(4 downto 0) => \NLW_input_[8].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED\(4 downto 0),
      DATAIN => '0',
      DATAOUT => data_in_dly_8,
      IDATAIN => mem_dq_in(6),
      INC => idelay_inc,
      LD => LD0_7,
      LDPIPEEN => '0',
      REGRST => A_rst_primitives
    );
\input_[8].iserdes_dq_.iserdesdq\: unisim.vcomponents.ISERDESE2
    generic map(
      DATA_RATE => "DDR",
      DATA_WIDTH => 4,
      DYN_CLKDIV_INV_EN => "FALSE",
      DYN_CLK_INV_EN => "FALSE",
      INIT_Q1 => '0',
      INIT_Q2 => '0',
      INIT_Q3 => '0',
      INIT_Q4 => '0',
      INTERFACE_TYPE => "MEMORY_DDR3",
      IOBDELAY => "IFD",
      IS_CLKB_INVERTED => '1',
      IS_CLKDIVP_INVERTED => '0',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D_INVERTED => '0',
      IS_OCLKB_INVERTED => '0',
      IS_OCLK_INVERTED => '0',
      NUM_CE => 2,
      OFB_USED => "FALSE",
      SERDES_MODE => "MASTER",
      SRVAL_Q1 => '0',
      SRVAL_Q2 => '0',
      SRVAL_Q3 => '0',
      SRVAL_Q4 => '0'
    )
        port map (
      BITSLIP => '0',
      CE1 => '1',
      CE2 => '1',
      CLK => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]\,
      CLKB => CLKB0_7,
      CLKDIV => \NLW_input_[8].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED\,
      CLKDIVP => iserdes_clkdiv,
      D => mem_dq_in(6),
      DDLY => data_in_dly_8,
      DYNCLKDIVSEL => '0',
      DYNCLKSEL => '0',
      O => \NLW_input_[8].iserdes_dq_.iserdesdq_O_UNCONNECTED\,
      OCLK => oserdes_clk,
      OCLKB => \NLW_input_[8].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED\,
      OFB => \NLW_input_[8].iserdes_dq_.iserdesdq_OFB_UNCONNECTED\,
      Q1 => D8(3),
      Q2 => D8(2),
      Q3 => D8(1),
      Q4 => D8(0),
      Q5 => \NLW_input_[8].iserdes_dq_.iserdesdq_Q5_UNCONNECTED\,
      Q6 => \NLW_input_[8].iserdes_dq_.iserdesdq_Q6_UNCONNECTED\,
      Q7 => \NLW_input_[8].iserdes_dq_.iserdesdq_Q7_UNCONNECTED\,
      Q8 => \NLW_input_[8].iserdes_dq_.iserdesdq_Q8_UNCONNECTED\,
      RST => '0',
      SHIFTIN1 => '0',
      SHIFTIN2 => '0',
      SHIFTOUT1 => \NLW_input_[8].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_input_[8].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED\
    );
\input_[9].iserdes_dq_.idelay_dq.idelaye2\: unisim.vcomponents.IDELAYE2
    generic map(
      CINVCTRL_SEL => "FALSE",
      DELAY_SRC => "IDATAIN",
      HIGH_PERFORMANCE_MODE => "TRUE",
      IDELAY_TYPE => "VARIABLE",
      IDELAY_VALUE => 0,
      IS_C_INVERTED => '0',
      IS_DATAIN_INVERTED => '0',
      IS_IDATAIN_INVERTED => '0',
      PIPE_SEL => "FALSE",
      REFCLK_FREQUENCY => 200.000000,
      SIGNAL_PATTERN => "DATA"
    )
        port map (
      C => idelay_ld_rst_reg_0,
      CE => \input_[9].iserdes_dq_.iserdesdq_0\,
      CINVCTRL => '0',
      CNTVALUEIN(4 downto 0) => B"00000",
      CNTVALUEOUT(4 downto 0) => \NLW_input_[9].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED\(4 downto 0),
      DATAIN => '0',
      DATAOUT => data_in_dly_9,
      IDATAIN => mem_dq_in(7),
      INC => idelay_inc,
      LD => LD0_7,
      LDPIPEEN => '0',
      REGRST => A_rst_primitives
    );
\input_[9].iserdes_dq_.iserdesdq\: unisim.vcomponents.ISERDESE2
    generic map(
      DATA_RATE => "DDR",
      DATA_WIDTH => 4,
      DYN_CLKDIV_INV_EN => "FALSE",
      DYN_CLK_INV_EN => "FALSE",
      INIT_Q1 => '0',
      INIT_Q2 => '0',
      INIT_Q3 => '0',
      INIT_Q4 => '0',
      INTERFACE_TYPE => "MEMORY_DDR3",
      IOBDELAY => "IFD",
      IS_CLKB_INVERTED => '1',
      IS_CLKDIVP_INVERTED => '0',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D_INVERTED => '0',
      IS_OCLKB_INVERTED => '0',
      IS_OCLK_INVERTED => '0',
      NUM_CE => 2,
      OFB_USED => "FALSE",
      SERDES_MODE => "MASTER",
      SRVAL_Q1 => '0',
      SRVAL_Q2 => '0',
      SRVAL_Q3 => '0',
      SRVAL_Q4 => '0'
    )
        port map (
      BITSLIP => '0',
      CE1 => '1',
      CE2 => '1',
      CLK => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]\,
      CLKB => CLKB0_7,
      CLKDIV => \NLW_input_[9].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED\,
      CLKDIVP => iserdes_clkdiv,
      D => mem_dq_in(7),
      DDLY => data_in_dly_9,
      DYNCLKDIVSEL => '0',
      DYNCLKSEL => '0',
      O => \NLW_input_[9].iserdes_dq_.iserdesdq_O_UNCONNECTED\,
      OCLK => oserdes_clk,
      OCLKB => \NLW_input_[9].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED\,
      OFB => \NLW_input_[9].iserdes_dq_.iserdesdq_OFB_UNCONNECTED\,
      Q1 => D9(3),
      Q2 => D9(2),
      Q3 => D9(1),
      Q4 => D9(0),
      Q5 => \NLW_input_[9].iserdes_dq_.iserdesdq_Q5_UNCONNECTED\,
      Q6 => \NLW_input_[9].iserdes_dq_.iserdesdq_Q6_UNCONNECTED\,
      Q7 => \NLW_input_[9].iserdes_dq_.iserdesdq_Q7_UNCONNECTED\,
      Q8 => \NLW_input_[9].iserdes_dq_.iserdesdq_Q8_UNCONNECTED\,
      RST => '0',
      SHIFTIN1 => '0',
      SHIFTIN2 => '0',
      SHIFTOUT1 => \NLW_input_[9].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_input_[9].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED\
    );
\output_[1].oserdes_dq_.ddr.oserdes_dq_i\: unisim.vcomponents.OSERDESE2
    generic map(
      DATA_RATE_OQ => "DDR",
      DATA_RATE_TQ => "DDR",
      DATA_WIDTH => 4,
      INIT_OQ => '1',
      INIT_TQ => '1',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D1_INVERTED => '0',
      IS_D2_INVERTED => '0',
      IS_D3_INVERTED => '0',
      IS_D4_INVERTED => '0',
      IS_D5_INVERTED => '0',
      IS_D6_INVERTED => '0',
      IS_D7_INVERTED => '0',
      IS_D8_INVERTED => '0',
      IS_T1_INVERTED => '0',
      IS_T2_INVERTED => '0',
      IS_T3_INVERTED => '0',
      IS_T4_INVERTED => '0',
      SERDES_MODE => "MASTER",
      SRVAL_OQ => '1',
      SRVAL_TQ => '1',
      TBYTE_CTL => "TRUE",
      TBYTE_SRC => "FALSE",
      TRISTATE_WIDTH => 4
    )
        port map (
      CLK => oserdes_clk,
      CLKDIV => oserdes_clkdiv,
      D1 => of_dqbus(0),
      D2 => of_dqbus(1),
      D3 => of_dqbus(2),
      D4 => of_dqbus(3),
      D5 => '0',
      D6 => '0',
      D7 => '0',
      D8 => '0',
      OCE => '1',
      OFB => \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\,
      OQ => mem_dq_out(0),
      RST => po_oserdes_rst,
      SHIFTIN1 => \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\,
      SHIFTIN2 => \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\,
      SHIFTOUT1 => \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\,
      T1 => '0',
      T2 => '0',
      T3 => '0',
      T4 => '0',
      TBYTEIN => tbyte_out,
      TBYTEOUT => \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\,
      TCE => '1',
      TFB => \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\,
      TQ => mem_dq_ts(0)
    );
\output_[2].oserdes_dq_.ddr.oserdes_dq_i\: unisim.vcomponents.OSERDESE2
    generic map(
      DATA_RATE_OQ => "DDR",
      DATA_RATE_TQ => "DDR",
      DATA_WIDTH => 4,
      INIT_OQ => '1',
      INIT_TQ => '1',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D1_INVERTED => '0',
      IS_D2_INVERTED => '0',
      IS_D3_INVERTED => '0',
      IS_D4_INVERTED => '0',
      IS_D5_INVERTED => '0',
      IS_D6_INVERTED => '0',
      IS_D7_INVERTED => '0',
      IS_D8_INVERTED => '0',
      IS_T1_INVERTED => '0',
      IS_T2_INVERTED => '0',
      IS_T3_INVERTED => '0',
      IS_T4_INVERTED => '0',
      SERDES_MODE => "MASTER",
      SRVAL_OQ => '1',
      SRVAL_TQ => '1',
      TBYTE_CTL => "TRUE",
      TBYTE_SRC => "FALSE",
      TRISTATE_WIDTH => 4
    )
        port map (
      CLK => oserdes_clk,
      CLKDIV => oserdes_clkdiv,
      D1 => of_dqbus(4),
      D2 => of_dqbus(5),
      D3 => of_dqbus(6),
      D4 => of_dqbus(7),
      D5 => '0',
      D6 => '0',
      D7 => '0',
      D8 => '0',
      OCE => '1',
      OFB => \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\,
      OQ => mem_dq_out(1),
      RST => po_oserdes_rst,
      SHIFTIN1 => \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\,
      SHIFTIN2 => \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\,
      SHIFTOUT1 => \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\,
      T1 => '0',
      T2 => '0',
      T3 => '0',
      T4 => '0',
      TBYTEIN => tbyte_out,
      TBYTEOUT => \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\,
      TCE => '1',
      TFB => \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\,
      TQ => mem_dq_ts(1)
    );
\output_[3].oserdes_dq_.ddr.oserdes_dq_i\: unisim.vcomponents.OSERDESE2
    generic map(
      DATA_RATE_OQ => "DDR",
      DATA_RATE_TQ => "DDR",
      DATA_WIDTH => 4,
      INIT_OQ => '1',
      INIT_TQ => '1',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D1_INVERTED => '0',
      IS_D2_INVERTED => '0',
      IS_D3_INVERTED => '0',
      IS_D4_INVERTED => '0',
      IS_D5_INVERTED => '0',
      IS_D6_INVERTED => '0',
      IS_D7_INVERTED => '0',
      IS_D8_INVERTED => '0',
      IS_T1_INVERTED => '0',
      IS_T2_INVERTED => '0',
      IS_T3_INVERTED => '0',
      IS_T4_INVERTED => '0',
      SERDES_MODE => "MASTER",
      SRVAL_OQ => '1',
      SRVAL_TQ => '1',
      TBYTE_CTL => "TRUE",
      TBYTE_SRC => "FALSE",
      TRISTATE_WIDTH => 4
    )
        port map (
      CLK => oserdes_clk,
      CLKDIV => oserdes_clkdiv,
      D1 => of_dqbus(8),
      D2 => of_dqbus(9),
      D3 => of_dqbus(10),
      D4 => of_dqbus(11),
      D5 => '0',
      D6 => '0',
      D7 => '0',
      D8 => '0',
      OCE => '1',
      OFB => \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\,
      OQ => mem_dq_out(2),
      RST => po_oserdes_rst,
      SHIFTIN1 => \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\,
      SHIFTIN2 => \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\,
      SHIFTOUT1 => \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\,
      T1 => '0',
      T2 => '0',
      T3 => '0',
      T4 => '0',
      TBYTEIN => tbyte_out,
      TBYTEOUT => \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\,
      TCE => '1',
      TFB => \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\,
      TQ => mem_dq_ts(2)
    );
\output_[4].oserdes_dq_.ddr.oserdes_dq_i\: unisim.vcomponents.OSERDESE2
    generic map(
      DATA_RATE_OQ => "DDR",
      DATA_RATE_TQ => "DDR",
      DATA_WIDTH => 4,
      INIT_OQ => '1',
      INIT_TQ => '1',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D1_INVERTED => '0',
      IS_D2_INVERTED => '0',
      IS_D3_INVERTED => '0',
      IS_D4_INVERTED => '0',
      IS_D5_INVERTED => '0',
      IS_D6_INVERTED => '0',
      IS_D7_INVERTED => '0',
      IS_D8_INVERTED => '0',
      IS_T1_INVERTED => '0',
      IS_T2_INVERTED => '0',
      IS_T3_INVERTED => '0',
      IS_T4_INVERTED => '0',
      SERDES_MODE => "MASTER",
      SRVAL_OQ => '1',
      SRVAL_TQ => '1',
      TBYTE_CTL => "TRUE",
      TBYTE_SRC => "FALSE",
      TRISTATE_WIDTH => 4
    )
        port map (
      CLK => oserdes_clk,
      CLKDIV => oserdes_clkdiv,
      D1 => of_dqbus(12),
      D2 => of_dqbus(13),
      D3 => of_dqbus(14),
      D4 => of_dqbus(15),
      D5 => '0',
      D6 => '0',
      D7 => '0',
      D8 => '0',
      OCE => '1',
      OFB => \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\,
      OQ => mem_dq_out(3),
      RST => po_oserdes_rst,
      SHIFTIN1 => \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\,
      SHIFTIN2 => \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\,
      SHIFTOUT1 => \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\,
      T1 => '0',
      T2 => '0',
      T3 => '0',
      T4 => '0',
      TBYTEIN => tbyte_out,
      TBYTEOUT => \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\,
      TCE => '1',
      TFB => \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\,
      TQ => mem_dq_ts(3)
    );
\output_[5].oserdes_dq_.ddr.oserdes_dq_i\: unisim.vcomponents.OSERDESE2
    generic map(
      DATA_RATE_OQ => "DDR",
      DATA_RATE_TQ => "DDR",
      DATA_WIDTH => 4,
      INIT_OQ => '1',
      INIT_TQ => '1',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D1_INVERTED => '0',
      IS_D2_INVERTED => '0',
      IS_D3_INVERTED => '0',
      IS_D4_INVERTED => '0',
      IS_D5_INVERTED => '0',
      IS_D6_INVERTED => '0',
      IS_D7_INVERTED => '0',
      IS_D8_INVERTED => '0',
      IS_T1_INVERTED => '0',
      IS_T2_INVERTED => '0',
      IS_T3_INVERTED => '0',
      IS_T4_INVERTED => '0',
      SERDES_MODE => "MASTER",
      SRVAL_OQ => '1',
      SRVAL_TQ => '1',
      TBYTE_CTL => "TRUE",
      TBYTE_SRC => "FALSE",
      TRISTATE_WIDTH => 4
    )
        port map (
      CLK => oserdes_clk,
      CLKDIV => oserdes_clkdiv,
      D1 => of_dqbus(16),
      D2 => of_dqbus(17),
      D3 => of_dqbus(18),
      D4 => of_dqbus(19),
      D5 => '0',
      D6 => '0',
      D7 => '0',
      D8 => '0',
      OCE => '1',
      OFB => \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\,
      OQ => mem_dq_out(4),
      RST => po_oserdes_rst,
      SHIFTIN1 => \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\,
      SHIFTIN2 => \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\,
      SHIFTOUT1 => \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\,
      T1 => '0',
      T2 => '0',
      T3 => '0',
      T4 => '0',
      TBYTEIN => tbyte_out,
      TBYTEOUT => \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\,
      TCE => '1',
      TFB => \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\,
      TQ => mem_dq_ts(4)
    );
\output_[6].oserdes_dq_.ddr.oserdes_dq_i\: unisim.vcomponents.OSERDESE2
    generic map(
      DATA_RATE_OQ => "DDR",
      DATA_RATE_TQ => "DDR",
      DATA_WIDTH => 4,
      INIT_OQ => '1',
      INIT_TQ => '1',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D1_INVERTED => '0',
      IS_D2_INVERTED => '0',
      IS_D3_INVERTED => '0',
      IS_D4_INVERTED => '0',
      IS_D5_INVERTED => '0',
      IS_D6_INVERTED => '0',
      IS_D7_INVERTED => '0',
      IS_D8_INVERTED => '0',
      IS_T1_INVERTED => '0',
      IS_T2_INVERTED => '0',
      IS_T3_INVERTED => '0',
      IS_T4_INVERTED => '0',
      SERDES_MODE => "MASTER",
      SRVAL_OQ => '1',
      SRVAL_TQ => '1',
      TBYTE_CTL => "TRUE",
      TBYTE_SRC => "FALSE",
      TRISTATE_WIDTH => 4
    )
        port map (
      CLK => oserdes_clk,
      CLKDIV => oserdes_clkdiv,
      D1 => of_dqbus(20),
      D2 => of_dqbus(21),
      D3 => of_dqbus(22),
      D4 => of_dqbus(23),
      D5 => '0',
      D6 => '0',
      D7 => '0',
      D8 => '0',
      OCE => '1',
      OFB => \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\,
      OQ => mem_dq_out(5),
      RST => po_oserdes_rst,
      SHIFTIN1 => \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\,
      SHIFTIN2 => \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\,
      SHIFTOUT1 => \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\,
      T1 => '0',
      T2 => '0',
      T3 => '0',
      T4 => '0',
      TBYTEIN => tbyte_out,
      TBYTEOUT => \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\,
      TCE => '1',
      TFB => \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\,
      TQ => mem_dq_ts(5)
    );
\output_[7].oserdes_dq_.ddr.oserdes_dq_i\: unisim.vcomponents.OSERDESE2
    generic map(
      DATA_RATE_OQ => "DDR",
      DATA_RATE_TQ => "DDR",
      DATA_WIDTH => 4,
      INIT_OQ => '1',
      INIT_TQ => '1',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D1_INVERTED => '0',
      IS_D2_INVERTED => '0',
      IS_D3_INVERTED => '0',
      IS_D4_INVERTED => '0',
      IS_D5_INVERTED => '0',
      IS_D6_INVERTED => '0',
      IS_D7_INVERTED => '0',
      IS_D8_INVERTED => '0',
      IS_T1_INVERTED => '0',
      IS_T2_INVERTED => '0',
      IS_T3_INVERTED => '0',
      IS_T4_INVERTED => '0',
      SERDES_MODE => "MASTER",
      SRVAL_OQ => '1',
      SRVAL_TQ => '1',
      TBYTE_CTL => "TRUE",
      TBYTE_SRC => "FALSE",
      TRISTATE_WIDTH => 4
    )
        port map (
      CLK => oserdes_clk,
      CLKDIV => oserdes_clkdiv,
      D1 => of_dqbus(24),
      D2 => of_dqbus(25),
      D3 => of_dqbus(26),
      D4 => of_dqbus(27),
      D5 => '0',
      D6 => '0',
      D7 => '0',
      D8 => '0',
      OCE => '1',
      OFB => \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\,
      OQ => mem_dq_out(6),
      RST => po_oserdes_rst,
      SHIFTIN1 => \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\,
      SHIFTIN2 => \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\,
      SHIFTOUT1 => \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\,
      T1 => '0',
      T2 => '0',
      T3 => '0',
      T4 => '0',
      TBYTEIN => tbyte_out,
      TBYTEOUT => \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\,
      TCE => '1',
      TFB => \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\,
      TQ => mem_dq_ts(6)
    );
\output_[8].oserdes_dq_.ddr.oserdes_dq_i\: unisim.vcomponents.OSERDESE2
    generic map(
      DATA_RATE_OQ => "DDR",
      DATA_RATE_TQ => "DDR",
      DATA_WIDTH => 4,
      INIT_OQ => '1',
      INIT_TQ => '1',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D1_INVERTED => '0',
      IS_D2_INVERTED => '0',
      IS_D3_INVERTED => '0',
      IS_D4_INVERTED => '0',
      IS_D5_INVERTED => '0',
      IS_D6_INVERTED => '0',
      IS_D7_INVERTED => '0',
      IS_D8_INVERTED => '0',
      IS_T1_INVERTED => '0',
      IS_T2_INVERTED => '0',
      IS_T3_INVERTED => '0',
      IS_T4_INVERTED => '0',
      SERDES_MODE => "MASTER",
      SRVAL_OQ => '1',
      SRVAL_TQ => '1',
      TBYTE_CTL => "TRUE",
      TBYTE_SRC => "FALSE",
      TRISTATE_WIDTH => 4
    )
        port map (
      CLK => oserdes_clk,
      CLKDIV => oserdes_clkdiv,
      D1 => of_dqbus(28),
      D2 => of_dqbus(29),
      D3 => of_dqbus(30),
      D4 => of_dqbus(31),
      D5 => '0',
      D6 => '0',
      D7 => '0',
      D8 => '0',
      OCE => '1',
      OFB => \NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\,
      OQ => mem_dq_out(7),
      RST => po_oserdes_rst,
      SHIFTIN1 => \NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\,
      SHIFTIN2 => \NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\,
      SHIFTOUT1 => \NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\,
      T1 => '0',
      T2 => '0',
      T3 => '0',
      T4 => '0',
      TBYTEIN => tbyte_out,
      TBYTEOUT => \NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\,
      TCE => '1',
      TFB => \NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\,
      TQ => mem_dq_ts(7)
    );
\output_[9].oserdes_dq_.ddr.oserdes_dq_i\: unisim.vcomponents.OSERDESE2
    generic map(
      DATA_RATE_OQ => "DDR",
      DATA_RATE_TQ => "DDR",
      DATA_WIDTH => 4,
      INIT_OQ => '1',
      INIT_TQ => '1',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D1_INVERTED => '0',
      IS_D2_INVERTED => '0',
      IS_D3_INVERTED => '0',
      IS_D4_INVERTED => '0',
      IS_D5_INVERTED => '0',
      IS_D6_INVERTED => '0',
      IS_D7_INVERTED => '0',
      IS_D8_INVERTED => '0',
      IS_T1_INVERTED => '0',
      IS_T2_INVERTED => '0',
      IS_T3_INVERTED => '0',
      IS_T4_INVERTED => '0',
      SERDES_MODE => "MASTER",
      SRVAL_OQ => '1',
      SRVAL_TQ => '1',
      TBYTE_CTL => "TRUE",
      TBYTE_SRC => "FALSE",
      TRISTATE_WIDTH => 4
    )
        port map (
      CLK => oserdes_clk,
      CLKDIV => oserdes_clkdiv,
      D1 => of_dqbus(32),
      D2 => of_dqbus(33),
      D3 => of_dqbus(34),
      D4 => of_dqbus(35),
      D5 => '0',
      D6 => '0',
      D7 => '0',
      D8 => '0',
      OCE => '1',
      OFB => \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\,
      OQ => mem_dq_out(8),
      RST => po_oserdes_rst,
      SHIFTIN1 => \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\,
      SHIFTIN2 => \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\,
      SHIFTOUT1 => \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\,
      T1 => '0',
      T2 => '0',
      T3 => '0',
      T4 => '0',
      TBYTEIN => tbyte_out,
      TBYTEOUT => \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\,
      TCE => '1',
      TFB => \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\,
      TQ => mem_dq_ts(8)
    );
\slave_ts.oserdes_slave_ts\: unisim.vcomponents.OSERDESE2
    generic map(
      DATA_RATE_OQ => "DDR",
      DATA_RATE_TQ => "DDR",
      DATA_WIDTH => 4,
      INIT_OQ => '1',
      INIT_TQ => '1',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D1_INVERTED => '0',
      IS_D2_INVERTED => '0',
      IS_D3_INVERTED => '0',
      IS_D4_INVERTED => '0',
      IS_D5_INVERTED => '0',
      IS_D6_INVERTED => '0',
      IS_D7_INVERTED => '0',
      IS_D8_INVERTED => '0',
      IS_T1_INVERTED => '0',
      IS_T2_INVERTED => '0',
      IS_T3_INVERTED => '0',
      IS_T4_INVERTED => '0',
      SERDES_MODE => "MASTER",
      SRVAL_OQ => '1',
      SRVAL_TQ => '1',
      TBYTE_CTL => "TRUE",
      TBYTE_SRC => "TRUE",
      TRISTATE_WIDTH => 4
    )
        port map (
      CLK => oserdes_clk,
      CLKDIV => oserdes_clkdiv,
      D1 => '0',
      D2 => '0',
      D3 => '0',
      D4 => '0',
      D5 => '0',
      D6 => '0',
      D7 => '0',
      D8 => '0',
      OCE => '1',
      OFB => \NLW_slave_ts.oserdes_slave_ts_OFB_UNCONNECTED\,
      OQ => \NLW_slave_ts.oserdes_slave_ts_OQ_UNCONNECTED\,
      RST => po_oserdes_rst,
      SHIFTIN1 => \NLW_slave_ts.oserdes_slave_ts_SHIFTIN1_UNCONNECTED\,
      SHIFTIN2 => \NLW_slave_ts.oserdes_slave_ts_SHIFTIN2_UNCONNECTED\,
      SHIFTOUT1 => \NLW_slave_ts.oserdes_slave_ts_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_slave_ts.oserdes_slave_ts_SHIFTOUT2_UNCONNECTED\,
      T1 => DTSBUS(0),
      T2 => DTSBUS(0),
      T3 => DTSBUS(1),
      T4 => DTSBUS(1),
      TBYTEIN => tbyte_out,
      TBYTEOUT => tbyte_out,
      TCE => '1',
      TFB => \NLW_slave_ts.oserdes_slave_ts_TFB_UNCONNECTED\,
      TQ => \NLW_slave_ts.oserdes_slave_ts_TQ_UNCONNECTED\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \mig_mig_7series_v4_2_ddr_byte_group_io__parameterized1\ is
  port (
    mem_dq_out : out STD_LOGIC_VECTOR ( 5 downto 0 );
    oserdes_clk : in STD_LOGIC;
    oserdes_clkdiv : in STD_LOGIC;
    oserdes_dq : in STD_LOGIC_VECTOR ( 23 downto 0 );
    po_oserdes_rst : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \mig_mig_7series_v4_2_ddr_byte_group_io__parameterized1\ : entity is "mig_7series_v4_2_ddr_byte_group_io";
end \mig_mig_7series_v4_2_ddr_byte_group_io__parameterized1\;

architecture STRUCTURE of \mig_mig_7series_v4_2_ddr_byte_group_io__parameterized1\ is
  signal \NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED\ : STD_LOGIC;
  attribute BOX_TYPE : string;
  attribute BOX_TYPE of \output_[10].oserdes_dq_.sdr.oserdes_dq_i\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \output_[11].oserdes_dq_.sdr.oserdes_dq_i\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \output_[2].oserdes_dq_.sdr.oserdes_dq_i\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \output_[4].oserdes_dq_.sdr.oserdes_dq_i\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \output_[5].oserdes_dq_.sdr.oserdes_dq_i\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \output_[7].oserdes_dq_.sdr.oserdes_dq_i\ : label is "PRIMITIVE";
begin
\output_[10].oserdes_dq_.sdr.oserdes_dq_i\: unisim.vcomponents.OSERDESE2
    generic map(
      DATA_RATE_OQ => "SDR",
      DATA_RATE_TQ => "SDR",
      DATA_WIDTH => 4,
      INIT_OQ => '0',
      INIT_TQ => '1',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D1_INVERTED => '0',
      IS_D2_INVERTED => '0',
      IS_D3_INVERTED => '0',
      IS_D4_INVERTED => '0',
      IS_D5_INVERTED => '0',
      IS_D6_INVERTED => '0',
      IS_D7_INVERTED => '0',
      IS_D8_INVERTED => '0',
      IS_T1_INVERTED => '0',
      IS_T2_INVERTED => '0',
      IS_T3_INVERTED => '0',
      IS_T4_INVERTED => '0',
      SERDES_MODE => "MASTER",
      SRVAL_OQ => '0',
      SRVAL_TQ => '1',
      TBYTE_CTL => "FALSE",
      TBYTE_SRC => "FALSE",
      TRISTATE_WIDTH => 1
    )
        port map (
      CLK => oserdes_clk,
      CLKDIV => oserdes_clkdiv,
      D1 => oserdes_dq(16),
      D2 => oserdes_dq(17),
      D3 => oserdes_dq(18),
      D4 => oserdes_dq(19),
      D5 => '0',
      D6 => '0',
      D7 => '0',
      D8 => '0',
      OCE => '1',
      OFB => \NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED\,
      OQ => mem_dq_out(4),
      RST => po_oserdes_rst,
      SHIFTIN1 => \NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\,
      SHIFTIN2 => \NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\,
      SHIFTOUT1 => \NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\,
      T1 => '0',
      T2 => '0',
      T3 => '0',
      T4 => '0',
      TBYTEIN => \NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED\,
      TBYTEOUT => \NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\,
      TCE => '1',
      TFB => \NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED\,
      TQ => \NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED\
    );
\output_[11].oserdes_dq_.sdr.oserdes_dq_i\: unisim.vcomponents.OSERDESE2
    generic map(
      DATA_RATE_OQ => "SDR",
      DATA_RATE_TQ => "SDR",
      DATA_WIDTH => 4,
      INIT_OQ => '0',
      INIT_TQ => '1',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D1_INVERTED => '0',
      IS_D2_INVERTED => '0',
      IS_D3_INVERTED => '0',
      IS_D4_INVERTED => '0',
      IS_D5_INVERTED => '0',
      IS_D6_INVERTED => '0',
      IS_D7_INVERTED => '0',
      IS_D8_INVERTED => '0',
      IS_T1_INVERTED => '0',
      IS_T2_INVERTED => '0',
      IS_T3_INVERTED => '0',
      IS_T4_INVERTED => '0',
      SERDES_MODE => "MASTER",
      SRVAL_OQ => '0',
      SRVAL_TQ => '1',
      TBYTE_CTL => "FALSE",
      TBYTE_SRC => "FALSE",
      TRISTATE_WIDTH => 1
    )
        port map (
      CLK => oserdes_clk,
      CLKDIV => oserdes_clkdiv,
      D1 => oserdes_dq(20),
      D2 => oserdes_dq(21),
      D3 => oserdes_dq(22),
      D4 => oserdes_dq(23),
      D5 => '0',
      D6 => '0',
      D7 => '0',
      D8 => '0',
      OCE => '1',
      OFB => \NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED\,
      OQ => mem_dq_out(5),
      RST => po_oserdes_rst,
      SHIFTIN1 => \NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\,
      SHIFTIN2 => \NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\,
      SHIFTOUT1 => \NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\,
      T1 => '0',
      T2 => '0',
      T3 => '0',
      T4 => '0',
      TBYTEIN => \NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED\,
      TBYTEOUT => \NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\,
      TCE => '1',
      TFB => \NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED\,
      TQ => \NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED\
    );
\output_[2].oserdes_dq_.sdr.oserdes_dq_i\: unisim.vcomponents.OSERDESE2
    generic map(
      DATA_RATE_OQ => "SDR",
      DATA_RATE_TQ => "SDR",
      DATA_WIDTH => 4,
      INIT_OQ => '0',
      INIT_TQ => '1',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D1_INVERTED => '0',
      IS_D2_INVERTED => '0',
      IS_D3_INVERTED => '0',
      IS_D4_INVERTED => '0',
      IS_D5_INVERTED => '0',
      IS_D6_INVERTED => '0',
      IS_D7_INVERTED => '0',
      IS_D8_INVERTED => '0',
      IS_T1_INVERTED => '0',
      IS_T2_INVERTED => '0',
      IS_T3_INVERTED => '0',
      IS_T4_INVERTED => '0',
      SERDES_MODE => "MASTER",
      SRVAL_OQ => '0',
      SRVAL_TQ => '1',
      TBYTE_CTL => "FALSE",
      TBYTE_SRC => "FALSE",
      TRISTATE_WIDTH => 1
    )
        port map (
      CLK => oserdes_clk,
      CLKDIV => oserdes_clkdiv,
      D1 => oserdes_dq(0),
      D2 => oserdes_dq(1),
      D3 => oserdes_dq(2),
      D4 => oserdes_dq(3),
      D5 => '0',
      D6 => '0',
      D7 => '0',
      D8 => '0',
      OCE => '1',
      OFB => \NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED\,
      OQ => mem_dq_out(0),
      RST => po_oserdes_rst,
      SHIFTIN1 => \NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\,
      SHIFTIN2 => \NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\,
      SHIFTOUT1 => \NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\,
      T1 => '0',
      T2 => '0',
      T3 => '0',
      T4 => '0',
      TBYTEIN => \NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED\,
      TBYTEOUT => \NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\,
      TCE => '1',
      TFB => \NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED\,
      TQ => \NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED\
    );
\output_[4].oserdes_dq_.sdr.oserdes_dq_i\: unisim.vcomponents.OSERDESE2
    generic map(
      DATA_RATE_OQ => "SDR",
      DATA_RATE_TQ => "SDR",
      DATA_WIDTH => 4,
      INIT_OQ => '0',
      INIT_TQ => '1',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D1_INVERTED => '0',
      IS_D2_INVERTED => '0',
      IS_D3_INVERTED => '0',
      IS_D4_INVERTED => '0',
      IS_D5_INVERTED => '0',
      IS_D6_INVERTED => '0',
      IS_D7_INVERTED => '0',
      IS_D8_INVERTED => '0',
      IS_T1_INVERTED => '0',
      IS_T2_INVERTED => '0',
      IS_T3_INVERTED => '0',
      IS_T4_INVERTED => '0',
      SERDES_MODE => "MASTER",
      SRVAL_OQ => '0',
      SRVAL_TQ => '1',
      TBYTE_CTL => "FALSE",
      TBYTE_SRC => "FALSE",
      TRISTATE_WIDTH => 1
    )
        port map (
      CLK => oserdes_clk,
      CLKDIV => oserdes_clkdiv,
      D1 => oserdes_dq(4),
      D2 => oserdes_dq(5),
      D3 => oserdes_dq(6),
      D4 => oserdes_dq(7),
      D5 => '0',
      D6 => '0',
      D7 => '0',
      D8 => '0',
      OCE => '1',
      OFB => \NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED\,
      OQ => mem_dq_out(1),
      RST => po_oserdes_rst,
      SHIFTIN1 => \NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\,
      SHIFTIN2 => \NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\,
      SHIFTOUT1 => \NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\,
      T1 => '0',
      T2 => '0',
      T3 => '0',
      T4 => '0',
      TBYTEIN => \NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED\,
      TBYTEOUT => \NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\,
      TCE => '1',
      TFB => \NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED\,
      TQ => \NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED\
    );
\output_[5].oserdes_dq_.sdr.oserdes_dq_i\: unisim.vcomponents.OSERDESE2
    generic map(
      DATA_RATE_OQ => "SDR",
      DATA_RATE_TQ => "SDR",
      DATA_WIDTH => 4,
      INIT_OQ => '0',
      INIT_TQ => '1',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D1_INVERTED => '0',
      IS_D2_INVERTED => '0',
      IS_D3_INVERTED => '0',
      IS_D4_INVERTED => '0',
      IS_D5_INVERTED => '0',
      IS_D6_INVERTED => '0',
      IS_D7_INVERTED => '0',
      IS_D8_INVERTED => '0',
      IS_T1_INVERTED => '0',
      IS_T2_INVERTED => '0',
      IS_T3_INVERTED => '0',
      IS_T4_INVERTED => '0',
      SERDES_MODE => "MASTER",
      SRVAL_OQ => '0',
      SRVAL_TQ => '1',
      TBYTE_CTL => "FALSE",
      TBYTE_SRC => "FALSE",
      TRISTATE_WIDTH => 1
    )
        port map (
      CLK => oserdes_clk,
      CLKDIV => oserdes_clkdiv,
      D1 => oserdes_dq(8),
      D2 => oserdes_dq(9),
      D3 => oserdes_dq(10),
      D4 => oserdes_dq(11),
      D5 => '0',
      D6 => '0',
      D7 => '0',
      D8 => '0',
      OCE => '1',
      OFB => \NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED\,
      OQ => mem_dq_out(2),
      RST => po_oserdes_rst,
      SHIFTIN1 => \NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\,
      SHIFTIN2 => \NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\,
      SHIFTOUT1 => \NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\,
      T1 => '0',
      T2 => '0',
      T3 => '0',
      T4 => '0',
      TBYTEIN => \NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED\,
      TBYTEOUT => \NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\,
      TCE => '1',
      TFB => \NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED\,
      TQ => \NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED\
    );
\output_[7].oserdes_dq_.sdr.oserdes_dq_i\: unisim.vcomponents.OSERDESE2
    generic map(
      DATA_RATE_OQ => "SDR",
      DATA_RATE_TQ => "SDR",
      DATA_WIDTH => 4,
      INIT_OQ => '0',
      INIT_TQ => '1',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D1_INVERTED => '0',
      IS_D2_INVERTED => '0',
      IS_D3_INVERTED => '0',
      IS_D4_INVERTED => '0',
      IS_D5_INVERTED => '0',
      IS_D6_INVERTED => '0',
      IS_D7_INVERTED => '0',
      IS_D8_INVERTED => '0',
      IS_T1_INVERTED => '0',
      IS_T2_INVERTED => '0',
      IS_T3_INVERTED => '0',
      IS_T4_INVERTED => '0',
      SERDES_MODE => "MASTER",
      SRVAL_OQ => '0',
      SRVAL_TQ => '1',
      TBYTE_CTL => "FALSE",
      TBYTE_SRC => "FALSE",
      TRISTATE_WIDTH => 1
    )
        port map (
      CLK => oserdes_clk,
      CLKDIV => oserdes_clkdiv,
      D1 => oserdes_dq(12),
      D2 => oserdes_dq(13),
      D3 => oserdes_dq(14),
      D4 => oserdes_dq(15),
      D5 => '0',
      D6 => '0',
      D7 => '0',
      D8 => '0',
      OCE => '1',
      OFB => \NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED\,
      OQ => mem_dq_out(3),
      RST => po_oserdes_rst,
      SHIFTIN1 => \NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\,
      SHIFTIN2 => \NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\,
      SHIFTOUT1 => \NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\,
      T1 => '0',
      T2 => '0',
      T3 => '0',
      T4 => '0',
      TBYTEIN => \NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED\,
      TBYTEOUT => \NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\,
      TCE => '1',
      TFB => \NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED\,
      TQ => \NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \mig_mig_7series_v4_2_ddr_byte_group_io__parameterized2\ is
  port (
    mem_dq_out : out STD_LOGIC_VECTOR ( 5 downto 0 );
    oserdes_clk : in STD_LOGIC;
    oserdes_clkdiv : in STD_LOGIC;
    oserdes_dq : in STD_LOGIC_VECTOR ( 23 downto 0 );
    po_oserdes_rst : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \mig_mig_7series_v4_2_ddr_byte_group_io__parameterized2\ : entity is "mig_7series_v4_2_ddr_byte_group_io";
end \mig_mig_7series_v4_2_ddr_byte_group_io__parameterized2\;

architecture STRUCTURE of \mig_mig_7series_v4_2_ddr_byte_group_io__parameterized2\ is
  signal \NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED\ : STD_LOGIC;
  attribute BOX_TYPE : string;
  attribute BOX_TYPE of \output_[10].oserdes_dq_.sdr.oserdes_dq_i\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \output_[11].oserdes_dq_.sdr.oserdes_dq_i\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \output_[4].oserdes_dq_.sdr.oserdes_dq_i\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \output_[5].oserdes_dq_.sdr.oserdes_dq_i\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \output_[8].oserdes_dq_.sdr.oserdes_dq_i\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \output_[9].oserdes_dq_.sdr.oserdes_dq_i\ : label is "PRIMITIVE";
begin
\output_[10].oserdes_dq_.sdr.oserdes_dq_i\: unisim.vcomponents.OSERDESE2
    generic map(
      DATA_RATE_OQ => "SDR",
      DATA_RATE_TQ => "SDR",
      DATA_WIDTH => 4,
      INIT_OQ => '0',
      INIT_TQ => '1',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D1_INVERTED => '0',
      IS_D2_INVERTED => '0',
      IS_D3_INVERTED => '0',
      IS_D4_INVERTED => '0',
      IS_D5_INVERTED => '0',
      IS_D6_INVERTED => '0',
      IS_D7_INVERTED => '0',
      IS_D8_INVERTED => '0',
      IS_T1_INVERTED => '0',
      IS_T2_INVERTED => '0',
      IS_T3_INVERTED => '0',
      IS_T4_INVERTED => '0',
      SERDES_MODE => "MASTER",
      SRVAL_OQ => '0',
      SRVAL_TQ => '1',
      TBYTE_CTL => "FALSE",
      TBYTE_SRC => "FALSE",
      TRISTATE_WIDTH => 1
    )
        port map (
      CLK => oserdes_clk,
      CLKDIV => oserdes_clkdiv,
      D1 => oserdes_dq(16),
      D2 => oserdes_dq(17),
      D3 => oserdes_dq(18),
      D4 => oserdes_dq(19),
      D5 => '0',
      D6 => '0',
      D7 => '0',
      D8 => '0',
      OCE => '1',
      OFB => \NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED\,
      OQ => mem_dq_out(4),
      RST => po_oserdes_rst,
      SHIFTIN1 => \NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\,
      SHIFTIN2 => \NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\,
      SHIFTOUT1 => \NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\,
      T1 => '0',
      T2 => '0',
      T3 => '0',
      T4 => '0',
      TBYTEIN => \NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED\,
      TBYTEOUT => \NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\,
      TCE => '1',
      TFB => \NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED\,
      TQ => \NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED\
    );
\output_[11].oserdes_dq_.sdr.oserdes_dq_i\: unisim.vcomponents.OSERDESE2
    generic map(
      DATA_RATE_OQ => "SDR",
      DATA_RATE_TQ => "SDR",
      DATA_WIDTH => 4,
      INIT_OQ => '0',
      INIT_TQ => '1',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D1_INVERTED => '0',
      IS_D2_INVERTED => '0',
      IS_D3_INVERTED => '0',
      IS_D4_INVERTED => '0',
      IS_D5_INVERTED => '0',
      IS_D6_INVERTED => '0',
      IS_D7_INVERTED => '0',
      IS_D8_INVERTED => '0',
      IS_T1_INVERTED => '0',
      IS_T2_INVERTED => '0',
      IS_T3_INVERTED => '0',
      IS_T4_INVERTED => '0',
      SERDES_MODE => "MASTER",
      SRVAL_OQ => '0',
      SRVAL_TQ => '1',
      TBYTE_CTL => "FALSE",
      TBYTE_SRC => "FALSE",
      TRISTATE_WIDTH => 1
    )
        port map (
      CLK => oserdes_clk,
      CLKDIV => oserdes_clkdiv,
      D1 => oserdes_dq(20),
      D2 => oserdes_dq(21),
      D3 => oserdes_dq(22),
      D4 => oserdes_dq(23),
      D5 => '0',
      D6 => '0',
      D7 => '0',
      D8 => '0',
      OCE => '1',
      OFB => \NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED\,
      OQ => mem_dq_out(5),
      RST => po_oserdes_rst,
      SHIFTIN1 => \NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\,
      SHIFTIN2 => \NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\,
      SHIFTOUT1 => \NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\,
      T1 => '0',
      T2 => '0',
      T3 => '0',
      T4 => '0',
      TBYTEIN => \NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED\,
      TBYTEOUT => \NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\,
      TCE => '1',
      TFB => \NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED\,
      TQ => \NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED\
    );
\output_[4].oserdes_dq_.sdr.oserdes_dq_i\: unisim.vcomponents.OSERDESE2
    generic map(
      DATA_RATE_OQ => "SDR",
      DATA_RATE_TQ => "SDR",
      DATA_WIDTH => 4,
      INIT_OQ => '0',
      INIT_TQ => '1',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D1_INVERTED => '0',
      IS_D2_INVERTED => '0',
      IS_D3_INVERTED => '0',
      IS_D4_INVERTED => '0',
      IS_D5_INVERTED => '0',
      IS_D6_INVERTED => '0',
      IS_D7_INVERTED => '0',
      IS_D8_INVERTED => '0',
      IS_T1_INVERTED => '0',
      IS_T2_INVERTED => '0',
      IS_T3_INVERTED => '0',
      IS_T4_INVERTED => '0',
      SERDES_MODE => "MASTER",
      SRVAL_OQ => '0',
      SRVAL_TQ => '1',
      TBYTE_CTL => "FALSE",
      TBYTE_SRC => "FALSE",
      TRISTATE_WIDTH => 1
    )
        port map (
      CLK => oserdes_clk,
      CLKDIV => oserdes_clkdiv,
      D1 => oserdes_dq(0),
      D2 => oserdes_dq(1),
      D3 => oserdes_dq(2),
      D4 => oserdes_dq(3),
      D5 => '0',
      D6 => '0',
      D7 => '0',
      D8 => '0',
      OCE => '1',
      OFB => \NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED\,
      OQ => mem_dq_out(0),
      RST => po_oserdes_rst,
      SHIFTIN1 => \NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\,
      SHIFTIN2 => \NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\,
      SHIFTOUT1 => \NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\,
      T1 => '0',
      T2 => '0',
      T3 => '0',
      T4 => '0',
      TBYTEIN => \NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED\,
      TBYTEOUT => \NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\,
      TCE => '1',
      TFB => \NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED\,
      TQ => \NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED\
    );
\output_[5].oserdes_dq_.sdr.oserdes_dq_i\: unisim.vcomponents.OSERDESE2
    generic map(
      DATA_RATE_OQ => "SDR",
      DATA_RATE_TQ => "SDR",
      DATA_WIDTH => 4,
      INIT_OQ => '0',
      INIT_TQ => '1',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D1_INVERTED => '0',
      IS_D2_INVERTED => '0',
      IS_D3_INVERTED => '0',
      IS_D4_INVERTED => '0',
      IS_D5_INVERTED => '0',
      IS_D6_INVERTED => '0',
      IS_D7_INVERTED => '0',
      IS_D8_INVERTED => '0',
      IS_T1_INVERTED => '0',
      IS_T2_INVERTED => '0',
      IS_T3_INVERTED => '0',
      IS_T4_INVERTED => '0',
      SERDES_MODE => "MASTER",
      SRVAL_OQ => '0',
      SRVAL_TQ => '1',
      TBYTE_CTL => "FALSE",
      TBYTE_SRC => "FALSE",
      TRISTATE_WIDTH => 1
    )
        port map (
      CLK => oserdes_clk,
      CLKDIV => oserdes_clkdiv,
      D1 => oserdes_dq(4),
      D2 => oserdes_dq(5),
      D3 => oserdes_dq(6),
      D4 => oserdes_dq(7),
      D5 => '0',
      D6 => '0',
      D7 => '0',
      D8 => '0',
      OCE => '1',
      OFB => \NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED\,
      OQ => mem_dq_out(1),
      RST => po_oserdes_rst,
      SHIFTIN1 => \NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\,
      SHIFTIN2 => \NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\,
      SHIFTOUT1 => \NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\,
      T1 => '0',
      T2 => '0',
      T3 => '0',
      T4 => '0',
      TBYTEIN => \NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED\,
      TBYTEOUT => \NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\,
      TCE => '1',
      TFB => \NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED\,
      TQ => \NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED\
    );
\output_[8].oserdes_dq_.sdr.oserdes_dq_i\: unisim.vcomponents.OSERDESE2
    generic map(
      DATA_RATE_OQ => "SDR",
      DATA_RATE_TQ => "SDR",
      DATA_WIDTH => 4,
      INIT_OQ => '0',
      INIT_TQ => '1',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D1_INVERTED => '0',
      IS_D2_INVERTED => '0',
      IS_D3_INVERTED => '0',
      IS_D4_INVERTED => '0',
      IS_D5_INVERTED => '0',
      IS_D6_INVERTED => '0',
      IS_D7_INVERTED => '0',
      IS_D8_INVERTED => '0',
      IS_T1_INVERTED => '0',
      IS_T2_INVERTED => '0',
      IS_T3_INVERTED => '0',
      IS_T4_INVERTED => '0',
      SERDES_MODE => "MASTER",
      SRVAL_OQ => '0',
      SRVAL_TQ => '1',
      TBYTE_CTL => "FALSE",
      TBYTE_SRC => "FALSE",
      TRISTATE_WIDTH => 1
    )
        port map (
      CLK => oserdes_clk,
      CLKDIV => oserdes_clkdiv,
      D1 => oserdes_dq(8),
      D2 => oserdes_dq(9),
      D3 => oserdes_dq(10),
      D4 => oserdes_dq(11),
      D5 => '0',
      D6 => '0',
      D7 => '0',
      D8 => '0',
      OCE => '1',
      OFB => \NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED\,
      OQ => mem_dq_out(2),
      RST => po_oserdes_rst,
      SHIFTIN1 => \NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\,
      SHIFTIN2 => \NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\,
      SHIFTOUT1 => \NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\,
      T1 => '0',
      T2 => '0',
      T3 => '0',
      T4 => '0',
      TBYTEIN => \NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED\,
      TBYTEOUT => \NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\,
      TCE => '1',
      TFB => \NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED\,
      TQ => \NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED\
    );
\output_[9].oserdes_dq_.sdr.oserdes_dq_i\: unisim.vcomponents.OSERDESE2
    generic map(
      DATA_RATE_OQ => "SDR",
      DATA_RATE_TQ => "SDR",
      DATA_WIDTH => 4,
      INIT_OQ => '0',
      INIT_TQ => '1',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D1_INVERTED => '0',
      IS_D2_INVERTED => '0',
      IS_D3_INVERTED => '0',
      IS_D4_INVERTED => '0',
      IS_D5_INVERTED => '0',
      IS_D6_INVERTED => '0',
      IS_D7_INVERTED => '0',
      IS_D8_INVERTED => '0',
      IS_T1_INVERTED => '0',
      IS_T2_INVERTED => '0',
      IS_T3_INVERTED => '0',
      IS_T4_INVERTED => '0',
      SERDES_MODE => "MASTER",
      SRVAL_OQ => '0',
      SRVAL_TQ => '1',
      TBYTE_CTL => "FALSE",
      TBYTE_SRC => "FALSE",
      TRISTATE_WIDTH => 1
    )
        port map (
      CLK => oserdes_clk,
      CLKDIV => oserdes_clkdiv,
      D1 => oserdes_dq(12),
      D2 => oserdes_dq(13),
      D3 => oserdes_dq(14),
      D4 => oserdes_dq(15),
      D5 => '0',
      D6 => '0',
      D7 => '0',
      D8 => '0',
      OCE => '1',
      OFB => \NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED\,
      OQ => mem_dq_out(3),
      RST => po_oserdes_rst,
      SHIFTIN1 => \NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\,
      SHIFTIN2 => \NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\,
      SHIFTOUT1 => \NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\,
      T1 => '0',
      T2 => '0',
      T3 => '0',
      T4 => '0',
      TBYTEIN => \NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED\,
      TBYTEOUT => \NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\,
      TCE => '1',
      TFB => \NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED\,
      TQ => \NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \mig_mig_7series_v4_2_ddr_byte_group_io__parameterized3\ is
  port (
    mem_dq_out : out STD_LOGIC_VECTOR ( 10 downto 0 );
    oserdes_clk : in STD_LOGIC;
    oserdes_clkdiv : in STD_LOGIC;
    oserdes_dq : in STD_LOGIC_VECTOR ( 43 downto 0 );
    po_oserdes_rst : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \mig_mig_7series_v4_2_ddr_byte_group_io__parameterized3\ : entity is "mig_7series_v4_2_ddr_byte_group_io";
end \mig_mig_7series_v4_2_ddr_byte_group_io__parameterized3\;

architecture STRUCTURE of \mig_mig_7series_v4_2_ddr_byte_group_io__parameterized3\ is
  signal \NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[6].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[6].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[6].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[6].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[6].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[6].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[6].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[6].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[6].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED\ : STD_LOGIC;
  attribute BOX_TYPE : string;
  attribute BOX_TYPE of \output_[10].oserdes_dq_.sdr.oserdes_dq_i\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \output_[11].oserdes_dq_.sdr.oserdes_dq_i\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \output_[1].oserdes_dq_.sdr.oserdes_dq_i\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \output_[2].oserdes_dq_.sdr.oserdes_dq_i\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \output_[3].oserdes_dq_.sdr.oserdes_dq_i\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \output_[4].oserdes_dq_.sdr.oserdes_dq_i\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \output_[5].oserdes_dq_.sdr.oserdes_dq_i\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \output_[6].oserdes_dq_.sdr.oserdes_dq_i\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \output_[7].oserdes_dq_.sdr.oserdes_dq_i\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \output_[8].oserdes_dq_.sdr.oserdes_dq_i\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \output_[9].oserdes_dq_.sdr.oserdes_dq_i\ : label is "PRIMITIVE";
begin
\output_[10].oserdes_dq_.sdr.oserdes_dq_i\: unisim.vcomponents.OSERDESE2
    generic map(
      DATA_RATE_OQ => "SDR",
      DATA_RATE_TQ => "SDR",
      DATA_WIDTH => 4,
      INIT_OQ => '0',
      INIT_TQ => '1',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D1_INVERTED => '0',
      IS_D2_INVERTED => '0',
      IS_D3_INVERTED => '0',
      IS_D4_INVERTED => '0',
      IS_D5_INVERTED => '0',
      IS_D6_INVERTED => '0',
      IS_D7_INVERTED => '0',
      IS_D8_INVERTED => '0',
      IS_T1_INVERTED => '0',
      IS_T2_INVERTED => '0',
      IS_T3_INVERTED => '0',
      IS_T4_INVERTED => '0',
      SERDES_MODE => "MASTER",
      SRVAL_OQ => '0',
      SRVAL_TQ => '1',
      TBYTE_CTL => "FALSE",
      TBYTE_SRC => "FALSE",
      TRISTATE_WIDTH => 1
    )
        port map (
      CLK => oserdes_clk,
      CLKDIV => oserdes_clkdiv,
      D1 => oserdes_dq(36),
      D2 => oserdes_dq(37),
      D3 => oserdes_dq(38),
      D4 => oserdes_dq(39),
      D5 => '0',
      D6 => '0',
      D7 => '0',
      D8 => '0',
      OCE => '1',
      OFB => \NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED\,
      OQ => mem_dq_out(9),
      RST => po_oserdes_rst,
      SHIFTIN1 => \NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\,
      SHIFTIN2 => \NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\,
      SHIFTOUT1 => \NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\,
      T1 => '0',
      T2 => '0',
      T3 => '0',
      T4 => '0',
      TBYTEIN => \NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED\,
      TBYTEOUT => \NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\,
      TCE => '1',
      TFB => \NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED\,
      TQ => \NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED\
    );
\output_[11].oserdes_dq_.sdr.oserdes_dq_i\: unisim.vcomponents.OSERDESE2
    generic map(
      DATA_RATE_OQ => "SDR",
      DATA_RATE_TQ => "SDR",
      DATA_WIDTH => 4,
      INIT_OQ => '0',
      INIT_TQ => '1',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D1_INVERTED => '0',
      IS_D2_INVERTED => '0',
      IS_D3_INVERTED => '0',
      IS_D4_INVERTED => '0',
      IS_D5_INVERTED => '0',
      IS_D6_INVERTED => '0',
      IS_D7_INVERTED => '0',
      IS_D8_INVERTED => '0',
      IS_T1_INVERTED => '0',
      IS_T2_INVERTED => '0',
      IS_T3_INVERTED => '0',
      IS_T4_INVERTED => '0',
      SERDES_MODE => "MASTER",
      SRVAL_OQ => '0',
      SRVAL_TQ => '1',
      TBYTE_CTL => "FALSE",
      TBYTE_SRC => "FALSE",
      TRISTATE_WIDTH => 1
    )
        port map (
      CLK => oserdes_clk,
      CLKDIV => oserdes_clkdiv,
      D1 => oserdes_dq(40),
      D2 => oserdes_dq(41),
      D3 => oserdes_dq(42),
      D4 => oserdes_dq(43),
      D5 => '0',
      D6 => '0',
      D7 => '0',
      D8 => '0',
      OCE => '1',
      OFB => \NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED\,
      OQ => mem_dq_out(10),
      RST => po_oserdes_rst,
      SHIFTIN1 => \NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\,
      SHIFTIN2 => \NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\,
      SHIFTOUT1 => \NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\,
      T1 => '0',
      T2 => '0',
      T3 => '0',
      T4 => '0',
      TBYTEIN => \NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED\,
      TBYTEOUT => \NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\,
      TCE => '1',
      TFB => \NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED\,
      TQ => \NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED\
    );
\output_[1].oserdes_dq_.sdr.oserdes_dq_i\: unisim.vcomponents.OSERDESE2
    generic map(
      DATA_RATE_OQ => "SDR",
      DATA_RATE_TQ => "SDR",
      DATA_WIDTH => 4,
      INIT_OQ => '0',
      INIT_TQ => '1',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D1_INVERTED => '0',
      IS_D2_INVERTED => '0',
      IS_D3_INVERTED => '0',
      IS_D4_INVERTED => '0',
      IS_D5_INVERTED => '0',
      IS_D6_INVERTED => '0',
      IS_D7_INVERTED => '0',
      IS_D8_INVERTED => '0',
      IS_T1_INVERTED => '0',
      IS_T2_INVERTED => '0',
      IS_T3_INVERTED => '0',
      IS_T4_INVERTED => '0',
      SERDES_MODE => "MASTER",
      SRVAL_OQ => '0',
      SRVAL_TQ => '1',
      TBYTE_CTL => "FALSE",
      TBYTE_SRC => "FALSE",
      TRISTATE_WIDTH => 1
    )
        port map (
      CLK => oserdes_clk,
      CLKDIV => oserdes_clkdiv,
      D1 => oserdes_dq(0),
      D2 => oserdes_dq(1),
      D3 => oserdes_dq(2),
      D4 => oserdes_dq(3),
      D5 => '0',
      D6 => '0',
      D7 => '0',
      D8 => '0',
      OCE => '1',
      OFB => \NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED\,
      OQ => mem_dq_out(0),
      RST => po_oserdes_rst,
      SHIFTIN1 => \NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\,
      SHIFTIN2 => \NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\,
      SHIFTOUT1 => \NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\,
      T1 => '0',
      T2 => '0',
      T3 => '0',
      T4 => '0',
      TBYTEIN => \NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED\,
      TBYTEOUT => \NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\,
      TCE => '1',
      TFB => \NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED\,
      TQ => \NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED\
    );
\output_[2].oserdes_dq_.sdr.oserdes_dq_i\: unisim.vcomponents.OSERDESE2
    generic map(
      DATA_RATE_OQ => "SDR",
      DATA_RATE_TQ => "SDR",
      DATA_WIDTH => 4,
      INIT_OQ => '0',
      INIT_TQ => '1',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D1_INVERTED => '0',
      IS_D2_INVERTED => '0',
      IS_D3_INVERTED => '0',
      IS_D4_INVERTED => '0',
      IS_D5_INVERTED => '0',
      IS_D6_INVERTED => '0',
      IS_D7_INVERTED => '0',
      IS_D8_INVERTED => '0',
      IS_T1_INVERTED => '0',
      IS_T2_INVERTED => '0',
      IS_T3_INVERTED => '0',
      IS_T4_INVERTED => '0',
      SERDES_MODE => "MASTER",
      SRVAL_OQ => '0',
      SRVAL_TQ => '1',
      TBYTE_CTL => "FALSE",
      TBYTE_SRC => "FALSE",
      TRISTATE_WIDTH => 1
    )
        port map (
      CLK => oserdes_clk,
      CLKDIV => oserdes_clkdiv,
      D1 => oserdes_dq(4),
      D2 => oserdes_dq(5),
      D3 => oserdes_dq(6),
      D4 => oserdes_dq(7),
      D5 => '0',
      D6 => '0',
      D7 => '0',
      D8 => '0',
      OCE => '1',
      OFB => \NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED\,
      OQ => mem_dq_out(1),
      RST => po_oserdes_rst,
      SHIFTIN1 => \NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\,
      SHIFTIN2 => \NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\,
      SHIFTOUT1 => \NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\,
      T1 => '0',
      T2 => '0',
      T3 => '0',
      T4 => '0',
      TBYTEIN => \NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED\,
      TBYTEOUT => \NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\,
      TCE => '1',
      TFB => \NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED\,
      TQ => \NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED\
    );
\output_[3].oserdes_dq_.sdr.oserdes_dq_i\: unisim.vcomponents.OSERDESE2
    generic map(
      DATA_RATE_OQ => "SDR",
      DATA_RATE_TQ => "SDR",
      DATA_WIDTH => 4,
      INIT_OQ => '0',
      INIT_TQ => '1',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D1_INVERTED => '0',
      IS_D2_INVERTED => '0',
      IS_D3_INVERTED => '0',
      IS_D4_INVERTED => '0',
      IS_D5_INVERTED => '0',
      IS_D6_INVERTED => '0',
      IS_D7_INVERTED => '0',
      IS_D8_INVERTED => '0',
      IS_T1_INVERTED => '0',
      IS_T2_INVERTED => '0',
      IS_T3_INVERTED => '0',
      IS_T4_INVERTED => '0',
      SERDES_MODE => "MASTER",
      SRVAL_OQ => '0',
      SRVAL_TQ => '1',
      TBYTE_CTL => "FALSE",
      TBYTE_SRC => "FALSE",
      TRISTATE_WIDTH => 1
    )
        port map (
      CLK => oserdes_clk,
      CLKDIV => oserdes_clkdiv,
      D1 => oserdes_dq(8),
      D2 => oserdes_dq(9),
      D3 => oserdes_dq(10),
      D4 => oserdes_dq(11),
      D5 => '0',
      D6 => '0',
      D7 => '0',
      D8 => '0',
      OCE => '1',
      OFB => \NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED\,
      OQ => mem_dq_out(2),
      RST => po_oserdes_rst,
      SHIFTIN1 => \NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\,
      SHIFTIN2 => \NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\,
      SHIFTOUT1 => \NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\,
      T1 => '0',
      T2 => '0',
      T3 => '0',
      T4 => '0',
      TBYTEIN => \NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED\,
      TBYTEOUT => \NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\,
      TCE => '1',
      TFB => \NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED\,
      TQ => \NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED\
    );
\output_[4].oserdes_dq_.sdr.oserdes_dq_i\: unisim.vcomponents.OSERDESE2
    generic map(
      DATA_RATE_OQ => "SDR",
      DATA_RATE_TQ => "SDR",
      DATA_WIDTH => 4,
      INIT_OQ => '0',
      INIT_TQ => '1',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D1_INVERTED => '0',
      IS_D2_INVERTED => '0',
      IS_D3_INVERTED => '0',
      IS_D4_INVERTED => '0',
      IS_D5_INVERTED => '0',
      IS_D6_INVERTED => '0',
      IS_D7_INVERTED => '0',
      IS_D8_INVERTED => '0',
      IS_T1_INVERTED => '0',
      IS_T2_INVERTED => '0',
      IS_T3_INVERTED => '0',
      IS_T4_INVERTED => '0',
      SERDES_MODE => "MASTER",
      SRVAL_OQ => '0',
      SRVAL_TQ => '1',
      TBYTE_CTL => "FALSE",
      TBYTE_SRC => "FALSE",
      TRISTATE_WIDTH => 1
    )
        port map (
      CLK => oserdes_clk,
      CLKDIV => oserdes_clkdiv,
      D1 => oserdes_dq(12),
      D2 => oserdes_dq(13),
      D3 => oserdes_dq(14),
      D4 => oserdes_dq(15),
      D5 => '0',
      D6 => '0',
      D7 => '0',
      D8 => '0',
      OCE => '1',
      OFB => \NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED\,
      OQ => mem_dq_out(3),
      RST => po_oserdes_rst,
      SHIFTIN1 => \NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\,
      SHIFTIN2 => \NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\,
      SHIFTOUT1 => \NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\,
      T1 => '0',
      T2 => '0',
      T3 => '0',
      T4 => '0',
      TBYTEIN => \NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED\,
      TBYTEOUT => \NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\,
      TCE => '1',
      TFB => \NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED\,
      TQ => \NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED\
    );
\output_[5].oserdes_dq_.sdr.oserdes_dq_i\: unisim.vcomponents.OSERDESE2
    generic map(
      DATA_RATE_OQ => "SDR",
      DATA_RATE_TQ => "SDR",
      DATA_WIDTH => 4,
      INIT_OQ => '0',
      INIT_TQ => '1',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D1_INVERTED => '0',
      IS_D2_INVERTED => '0',
      IS_D3_INVERTED => '0',
      IS_D4_INVERTED => '0',
      IS_D5_INVERTED => '0',
      IS_D6_INVERTED => '0',
      IS_D7_INVERTED => '0',
      IS_D8_INVERTED => '0',
      IS_T1_INVERTED => '0',
      IS_T2_INVERTED => '0',
      IS_T3_INVERTED => '0',
      IS_T4_INVERTED => '0',
      SERDES_MODE => "MASTER",
      SRVAL_OQ => '0',
      SRVAL_TQ => '1',
      TBYTE_CTL => "FALSE",
      TBYTE_SRC => "FALSE",
      TRISTATE_WIDTH => 1
    )
        port map (
      CLK => oserdes_clk,
      CLKDIV => oserdes_clkdiv,
      D1 => oserdes_dq(16),
      D2 => oserdes_dq(17),
      D3 => oserdes_dq(18),
      D4 => oserdes_dq(19),
      D5 => '0',
      D6 => '0',
      D7 => '0',
      D8 => '0',
      OCE => '1',
      OFB => \NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED\,
      OQ => mem_dq_out(4),
      RST => po_oserdes_rst,
      SHIFTIN1 => \NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\,
      SHIFTIN2 => \NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\,
      SHIFTOUT1 => \NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\,
      T1 => '0',
      T2 => '0',
      T3 => '0',
      T4 => '0',
      TBYTEIN => \NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED\,
      TBYTEOUT => \NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\,
      TCE => '1',
      TFB => \NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED\,
      TQ => \NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED\
    );
\output_[6].oserdes_dq_.sdr.oserdes_dq_i\: unisim.vcomponents.OSERDESE2
    generic map(
      DATA_RATE_OQ => "SDR",
      DATA_RATE_TQ => "SDR",
      DATA_WIDTH => 4,
      INIT_OQ => '0',
      INIT_TQ => '1',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D1_INVERTED => '0',
      IS_D2_INVERTED => '0',
      IS_D3_INVERTED => '0',
      IS_D4_INVERTED => '0',
      IS_D5_INVERTED => '0',
      IS_D6_INVERTED => '0',
      IS_D7_INVERTED => '0',
      IS_D8_INVERTED => '0',
      IS_T1_INVERTED => '0',
      IS_T2_INVERTED => '0',
      IS_T3_INVERTED => '0',
      IS_T4_INVERTED => '0',
      SERDES_MODE => "MASTER",
      SRVAL_OQ => '0',
      SRVAL_TQ => '1',
      TBYTE_CTL => "FALSE",
      TBYTE_SRC => "FALSE",
      TRISTATE_WIDTH => 1
    )
        port map (
      CLK => oserdes_clk,
      CLKDIV => oserdes_clkdiv,
      D1 => oserdes_dq(20),
      D2 => oserdes_dq(21),
      D3 => oserdes_dq(22),
      D4 => oserdes_dq(23),
      D5 => '0',
      D6 => '0',
      D7 => '0',
      D8 => '0',
      OCE => '1',
      OFB => \NLW_output_[6].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED\,
      OQ => mem_dq_out(5),
      RST => po_oserdes_rst,
      SHIFTIN1 => \NLW_output_[6].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\,
      SHIFTIN2 => \NLW_output_[6].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\,
      SHIFTOUT1 => \NLW_output_[6].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_output_[6].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\,
      T1 => '0',
      T2 => '0',
      T3 => '0',
      T4 => '0',
      TBYTEIN => \NLW_output_[6].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED\,
      TBYTEOUT => \NLW_output_[6].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\,
      TCE => '1',
      TFB => \NLW_output_[6].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED\,
      TQ => \NLW_output_[6].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED\
    );
\output_[7].oserdes_dq_.sdr.oserdes_dq_i\: unisim.vcomponents.OSERDESE2
    generic map(
      DATA_RATE_OQ => "SDR",
      DATA_RATE_TQ => "SDR",
      DATA_WIDTH => 4,
      INIT_OQ => '0',
      INIT_TQ => '1',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D1_INVERTED => '0',
      IS_D2_INVERTED => '0',
      IS_D3_INVERTED => '0',
      IS_D4_INVERTED => '0',
      IS_D5_INVERTED => '0',
      IS_D6_INVERTED => '0',
      IS_D7_INVERTED => '0',
      IS_D8_INVERTED => '0',
      IS_T1_INVERTED => '0',
      IS_T2_INVERTED => '0',
      IS_T3_INVERTED => '0',
      IS_T4_INVERTED => '0',
      SERDES_MODE => "MASTER",
      SRVAL_OQ => '0',
      SRVAL_TQ => '1',
      TBYTE_CTL => "FALSE",
      TBYTE_SRC => "FALSE",
      TRISTATE_WIDTH => 1
    )
        port map (
      CLK => oserdes_clk,
      CLKDIV => oserdes_clkdiv,
      D1 => oserdes_dq(24),
      D2 => oserdes_dq(25),
      D3 => oserdes_dq(26),
      D4 => oserdes_dq(27),
      D5 => '0',
      D6 => '0',
      D7 => '0',
      D8 => '0',
      OCE => '1',
      OFB => \NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED\,
      OQ => mem_dq_out(6),
      RST => po_oserdes_rst,
      SHIFTIN1 => \NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\,
      SHIFTIN2 => \NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\,
      SHIFTOUT1 => \NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\,
      T1 => '0',
      T2 => '0',
      T3 => '0',
      T4 => '0',
      TBYTEIN => \NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED\,
      TBYTEOUT => \NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\,
      TCE => '1',
      TFB => \NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED\,
      TQ => \NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED\
    );
\output_[8].oserdes_dq_.sdr.oserdes_dq_i\: unisim.vcomponents.OSERDESE2
    generic map(
      DATA_RATE_OQ => "SDR",
      DATA_RATE_TQ => "SDR",
      DATA_WIDTH => 4,
      INIT_OQ => '0',
      INIT_TQ => '1',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D1_INVERTED => '0',
      IS_D2_INVERTED => '0',
      IS_D3_INVERTED => '0',
      IS_D4_INVERTED => '0',
      IS_D5_INVERTED => '0',
      IS_D6_INVERTED => '0',
      IS_D7_INVERTED => '0',
      IS_D8_INVERTED => '0',
      IS_T1_INVERTED => '0',
      IS_T2_INVERTED => '0',
      IS_T3_INVERTED => '0',
      IS_T4_INVERTED => '0',
      SERDES_MODE => "MASTER",
      SRVAL_OQ => '0',
      SRVAL_TQ => '1',
      TBYTE_CTL => "FALSE",
      TBYTE_SRC => "FALSE",
      TRISTATE_WIDTH => 1
    )
        port map (
      CLK => oserdes_clk,
      CLKDIV => oserdes_clkdiv,
      D1 => oserdes_dq(28),
      D2 => oserdes_dq(29),
      D3 => oserdes_dq(30),
      D4 => oserdes_dq(31),
      D5 => '0',
      D6 => '0',
      D7 => '0',
      D8 => '0',
      OCE => '1',
      OFB => \NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED\,
      OQ => mem_dq_out(7),
      RST => po_oserdes_rst,
      SHIFTIN1 => \NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\,
      SHIFTIN2 => \NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\,
      SHIFTOUT1 => \NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\,
      T1 => '0',
      T2 => '0',
      T3 => '0',
      T4 => '0',
      TBYTEIN => \NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED\,
      TBYTEOUT => \NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\,
      TCE => '1',
      TFB => \NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED\,
      TQ => \NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED\
    );
\output_[9].oserdes_dq_.sdr.oserdes_dq_i\: unisim.vcomponents.OSERDESE2
    generic map(
      DATA_RATE_OQ => "SDR",
      DATA_RATE_TQ => "SDR",
      DATA_WIDTH => 4,
      INIT_OQ => '0',
      INIT_TQ => '1',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D1_INVERTED => '0',
      IS_D2_INVERTED => '0',
      IS_D3_INVERTED => '0',
      IS_D4_INVERTED => '0',
      IS_D5_INVERTED => '0',
      IS_D6_INVERTED => '0',
      IS_D7_INVERTED => '0',
      IS_D8_INVERTED => '0',
      IS_T1_INVERTED => '0',
      IS_T2_INVERTED => '0',
      IS_T3_INVERTED => '0',
      IS_T4_INVERTED => '0',
      SERDES_MODE => "MASTER",
      SRVAL_OQ => '0',
      SRVAL_TQ => '1',
      TBYTE_CTL => "FALSE",
      TBYTE_SRC => "FALSE",
      TRISTATE_WIDTH => 1
    )
        port map (
      CLK => oserdes_clk,
      CLKDIV => oserdes_clkdiv,
      D1 => oserdes_dq(32),
      D2 => oserdes_dq(33),
      D3 => oserdes_dq(34),
      D4 => oserdes_dq(35),
      D5 => '0',
      D6 => '0',
      D7 => '0',
      D8 => '0',
      OCE => '1',
      OFB => \NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED\,
      OQ => mem_dq_out(8),
      RST => po_oserdes_rst,
      SHIFTIN1 => \NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\,
      SHIFTIN2 => \NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\,
      SHIFTOUT1 => \NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\,
      T1 => '0',
      T2 => '0',
      T3 => '0',
      T4 => '0',
      TBYTEIN => \NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED\,
      TBYTEOUT => \NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\,
      TCE => '1',
      TFB => \NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED\,
      TQ => \NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mig_mig_7series_v4_2_ddr_if_post_fifo is
  port (
    \rd_mux_sel_r_reg[2]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_5\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_6\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_7\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_8\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_9\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_10\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_11\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_12\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_13\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_14\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_15\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_16\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_17\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_18\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_19\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_20\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_21\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_22\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_23\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_24\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_25\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_26\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_27\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_28\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_29\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_30\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_31\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_32\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_33\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_34\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_35\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_36\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_37\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_38\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_39\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_40\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_41\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_42\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_43\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_44\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_45\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_46\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_47\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_48\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_49\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_50\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_51\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_52\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_53\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_54\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_55\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_56\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_57\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_58\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_59\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_60\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_61\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_62\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]\ : out STD_LOGIC;
    p_0_out : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_0\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_1\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_2\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_3\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_4\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_5\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_6\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_7\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_8\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_9\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_10\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_11\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_12\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_13\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_14\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_15\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_16\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_17\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_18\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_19\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_20\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_21\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_22\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_23\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_24\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_25\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_26\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_27\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_28\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_29\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_30\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_31\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_32\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_33\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_34\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_35\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_36\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_37\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_38\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_39\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_40\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_41\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_42\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_43\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_44\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_45\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_46\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_47\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_48\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_49\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_50\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_51\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_52\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_53\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_54\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_55\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_56\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_57\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_58\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_59\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_60\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_61\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_2\ : out STD_LOGIC;
    if_empty_v : out STD_LOGIC_VECTOR ( 0 to 0 );
    ififo_rst : in STD_LOGIC;
    \rd_ptr_timing_reg[1]_0\ : in STD_LOGIC;
    if_empty_r_0 : in STD_LOGIC_VECTOR ( 0 to 0 );
    \my_full_reg[1]_0\ : in STD_LOGIC;
    \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
    \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg[0]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg[0]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg[0]_1\ : in STD_LOGIC;
    \gen_mux_rd[1].mux_rd_rise0_r1_reg[1]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg[1]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg[1]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg[1]_1\ : in STD_LOGIC;
    \gen_mux_rd[2].mux_rd_rise0_r1_reg[2]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg[2]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg[2]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg[2]_1\ : in STD_LOGIC;
    \gen_mux_rd[3].mux_rd_rise0_r1_reg[3]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg[3]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg[3]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg[3]_1\ : in STD_LOGIC;
    \gen_mux_rd[4].mux_rd_rise0_r1_reg[4]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg[4]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg[4]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg[4]_1\ : in STD_LOGIC;
    \gen_mux_rd[5].mux_rd_rise0_r1_reg[5]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg[5]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg[5]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg[5]_1\ : in STD_LOGIC;
    \gen_mux_rd[6].mux_rd_rise0_r1_reg[6]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg[6]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg[6]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg[6]_1\ : in STD_LOGIC;
    \gen_mux_rd[7].mux_rd_rise0_r1_reg[7]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg[7]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg[7]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg[7]_1\ : in STD_LOGIC;
    \gen_mux_rd[0].mux_rd_fall0_r1_reg[0]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg[0]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg[0]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg[0]_1\ : in STD_LOGIC;
    \gen_mux_rd[1].mux_rd_fall0_r1_reg[1]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg[1]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg[1]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg[1]_1\ : in STD_LOGIC;
    \gen_mux_rd[2].mux_rd_fall0_r1_reg[2]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg[2]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg[2]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg[2]_1\ : in STD_LOGIC;
    \gen_mux_rd[3].mux_rd_fall0_r1_reg[3]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg[3]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg[3]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg[3]_1\ : in STD_LOGIC;
    \gen_mux_rd[4].mux_rd_fall0_r1_reg[4]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg[4]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg[4]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg[4]_1\ : in STD_LOGIC;
    \gen_mux_rd[5].mux_rd_fall0_r1_reg[5]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg[5]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg[5]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg[5]_1\ : in STD_LOGIC;
    \gen_mux_rd[6].mux_rd_fall0_r1_reg[6]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg[6]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg[6]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg[6]_1\ : in STD_LOGIC;
    \gen_mux_rd[7].mux_rd_fall0_r1_reg[7]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg[7]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg[7]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg[7]_1\ : in STD_LOGIC;
    \gen_mux_rd[0].mux_rd_rise1_r1_reg[0]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_1\ : in STD_LOGIC;
    \gen_mux_rd[1].mux_rd_rise1_r1_reg[1]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg[1]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg[1]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg[1]_1\ : in STD_LOGIC;
    \gen_mux_rd[2].mux_rd_rise1_r1_reg[2]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg[2]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg[2]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg[2]_1\ : in STD_LOGIC;
    \gen_mux_rd[3].mux_rd_rise1_r1_reg[3]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg[3]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg[3]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg[3]_1\ : in STD_LOGIC;
    \gen_mux_rd[4].mux_rd_rise1_r1_reg[4]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg[4]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg[4]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg[4]_1\ : in STD_LOGIC;
    \gen_mux_rd[5].mux_rd_rise1_r1_reg[5]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg[5]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg[5]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg[5]_1\ : in STD_LOGIC;
    \gen_mux_rd[6].mux_rd_rise1_r1_reg[6]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg[6]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg[6]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg[6]_1\ : in STD_LOGIC;
    \gen_mux_rd[7].mux_rd_rise1_r1_reg[7]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg[7]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg[7]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg[7]_1\ : in STD_LOGIC;
    \gen_mux_rd[0].mux_rd_fall1_r1_reg[0]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg[0]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg[0]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg[0]_1\ : in STD_LOGIC;
    \gen_mux_rd[1].mux_rd_fall1_r1_reg[1]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg[1]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg[1]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg[1]_1\ : in STD_LOGIC;
    \gen_mux_rd[2].mux_rd_fall1_r1_reg[2]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg[2]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg[2]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg[2]_1\ : in STD_LOGIC;
    \gen_mux_rd[3].mux_rd_fall1_r1_reg[3]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg[3]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg[3]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg[3]_1\ : in STD_LOGIC;
    \gen_mux_rd[4].mux_rd_fall1_r1_reg[4]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg[4]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg[4]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg[4]_1\ : in STD_LOGIC;
    \gen_mux_rd[5].mux_rd_fall1_r1_reg[5]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg[5]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg[5]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg[5]_1\ : in STD_LOGIC;
    \gen_mux_rd[6].mux_rd_fall1_r1_reg[6]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg[6]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg[6]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg[6]_1\ : in STD_LOGIC;
    \gen_mux_rd[7].mux_rd_fall1_r1_reg[7]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg[7]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg[7]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg[7]_1\ : in STD_LOGIC;
    \gen_mux_rd[0].mux_rd_rise2_r1_reg[0]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise2_r_reg[0]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise2_r_reg[0]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise2_r_reg[0]_1\ : in STD_LOGIC;
    \gen_mux_rd[1].mux_rd_rise2_r1_reg[1]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg[1]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg[1]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg[1]_1\ : in STD_LOGIC;
    \gen_mux_rd[2].mux_rd_rise2_r1_reg[2]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg[2]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg[2]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg[2]_1\ : in STD_LOGIC;
    \gen_mux_rd[3].mux_rd_rise2_r1_reg[3]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg[3]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg[3]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg[3]_1\ : in STD_LOGIC;
    \gen_mux_rd[4].mux_rd_rise2_r1_reg[4]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise2_r_reg[4]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise2_r_reg[4]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise2_r_reg[4]_1\ : in STD_LOGIC;
    \gen_mux_rd[5].mux_rd_rise2_r1_reg[5]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg[5]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg[5]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg[5]_1\ : in STD_LOGIC;
    \gen_mux_rd[6].mux_rd_rise2_r1_reg[6]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg[6]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg[6]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg[6]_1\ : in STD_LOGIC;
    \gen_mux_rd[7].mux_rd_rise2_r1_reg[7]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg[7]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg[7]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg[7]_1\ : in STD_LOGIC;
    \gen_mux_rd[0].mux_rd_fall2_r1_reg[0]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg[0]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg[0]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg[0]_1\ : in STD_LOGIC;
    \gen_mux_rd[1].mux_rd_fall2_r1_reg[1]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg[1]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg[1]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg[1]_1\ : in STD_LOGIC;
    \gen_mux_rd[2].mux_rd_fall2_r1_reg[2]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg[2]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg[2]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg[2]_1\ : in STD_LOGIC;
    \gen_mux_rd[3].mux_rd_fall2_r1_reg[3]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg[3]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg[3]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg[3]_1\ : in STD_LOGIC;
    \gen_mux_rd[4].mux_rd_fall2_r1_reg[4]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg[4]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg[4]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg[4]_1\ : in STD_LOGIC;
    \gen_mux_rd[5].mux_rd_fall2_r1_reg[5]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg[5]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg[5]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg[5]_1\ : in STD_LOGIC;
    \gen_mux_rd[6].mux_rd_fall2_r1_reg[6]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg[6]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg[6]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg[6]_1\ : in STD_LOGIC;
    \gen_mux_rd[7].mux_rd_fall2_r1_reg[7]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg[7]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg[7]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg[7]_1\ : in STD_LOGIC;
    \gen_mux_rd[0].mux_rd_rise3_r1_reg[0]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg[0]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg[0]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg[0]_1\ : in STD_LOGIC;
    \gen_mux_rd[1].mux_rd_rise3_r1_reg[1]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg[1]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg[1]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg[1]_1\ : in STD_LOGIC;
    \gen_mux_rd[2].mux_rd_rise3_r1_reg[2]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg[2]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg[2]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg[2]_1\ : in STD_LOGIC;
    \gen_mux_rd[3].mux_rd_rise3_r1_reg[3]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise3_r_reg[3]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise3_r_reg[3]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise3_r_reg[3]_1\ : in STD_LOGIC;
    \gen_mux_rd[4].mux_rd_rise3_r1_reg[4]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg[4]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg[4]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg[4]_1\ : in STD_LOGIC;
    \gen_mux_rd[5].mux_rd_rise3_r1_reg[5]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg[5]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg[5]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg[5]_1\ : in STD_LOGIC;
    \gen_mux_rd[6].mux_rd_rise3_r1_reg[6]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg[6]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg[6]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg[6]_1\ : in STD_LOGIC;
    \gen_mux_rd[7].mux_rd_rise3_r1_reg[7]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise3_r_reg[7]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise3_r_reg[7]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise3_r_reg[7]_1\ : in STD_LOGIC;
    \gen_mux_rd[0].mux_rd_fall3_r1_reg[0]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg[0]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg[0]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg[0]_1\ : in STD_LOGIC;
    \gen_mux_rd[1].mux_rd_fall3_r1_reg[1]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg[1]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg[1]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg[1]_1\ : in STD_LOGIC;
    \gen_mux_rd[2].mux_rd_fall3_r1_reg[2]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg[2]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg[2]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg[2]_1\ : in STD_LOGIC;
    \gen_mux_rd[3].mux_rd_fall3_r1_reg[3]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg[3]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg[3]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg[3]_1\ : in STD_LOGIC;
    \gen_mux_rd[4].mux_rd_fall3_r1_reg[4]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg[4]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg[4]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg[4]_1\ : in STD_LOGIC;
    \gen_mux_rd[5].mux_rd_fall3_r1_reg[5]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg[5]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg[5]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg[5]_1\ : in STD_LOGIC;
    \gen_mux_rd[6].mux_rd_fall3_r1_reg[6]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg[6]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg[6]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg[6]_1\ : in STD_LOGIC;
    \gen_mux_rd[7].mux_rd_fall3_r1_reg[7]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7]_1\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_3\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg[1]_2\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg[2]_2\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg[3]_2\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg[4]_2\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg[5]_2\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg[6]_2\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg[7]_2\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg[0]_2\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg[1]_2\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg[2]_2\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg[3]_2\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg[4]_2\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg[5]_2\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg[6]_2\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7]_2\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg[0]_2\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg[1]_2\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg[2]_2\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg[3]_2\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg[4]_2\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg[5]_2\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg[6]_2\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg[7]_2\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise2_r_reg[0]_2\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg[1]_2\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg[2]_2\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg[3]_2\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise2_r_reg[4]_2\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg[5]_2\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg[6]_2\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg[7]_2\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg[0]_2\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg[1]_2\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg[2]_2\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg[3]_2\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg[4]_2\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg[5]_2\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg[6]_2\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg[7]_2\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg[0]_2\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg[1]_2\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg[2]_2\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise3_r_reg[3]_2\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg[4]_2\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg[5]_2\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg[6]_2\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise3_r_reg[7]_2\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg[0]_2\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg[1]_2\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg[2]_2\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg[3]_2\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg[4]_2\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg[5]_2\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg[6]_2\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg[7]_2\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg[0]_2\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg[1]_2\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg[2]_2\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg[3]_2\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg[4]_2\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg[5]_2\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg[6]_2\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg[7]_2\ : in STD_LOGIC;
    \my_full_reg[1]_1\ : in STD_LOGIC;
    \my_full_reg[1]_2\ : in STD_LOGIC;
    \my_full_reg[1]_3\ : in STD_LOGIC;
    \my_full_reg[1]_4\ : in STD_LOGIC;
    \my_full_reg[1]_5\ : in STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 67 downto 0 );
    phy_if_empty_r_reg : in STD_LOGIC_VECTOR ( 0 to 0 );
    if_empty_r : in STD_LOGIC_VECTOR ( 0 to 0 );
    phy_if_empty_r_reg_0 : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of mig_mig_7series_v4_2_ddr_if_post_fifo : entity is "mig_7series_v4_2_ddr_if_post_fifo";
end mig_mig_7series_v4_2_ddr_if_post_fifo;

architecture STRUCTURE of mig_mig_7series_v4_2_ddr_if_post_fifo is
  signal \^dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]\ : STD_LOGIC;
  signal \gen_mux_rd[0].mux_rd_fall0_r1[0]_i_2_n_0\ : STD_LOGIC;
  signal \gen_mux_rd[0].mux_rd_fall1_r1[0]_i_2_n_0\ : STD_LOGIC;
  signal \gen_mux_rd[0].mux_rd_fall2_r1[0]_i_2_n_0\ : STD_LOGIC;
  signal \gen_mux_rd[0].mux_rd_fall3_r1[0]_i_2_n_0\ : STD_LOGIC;
  signal \gen_mux_rd[0].mux_rd_rise0_r1[0]_i_2_n_0\ : STD_LOGIC;
  signal \gen_mux_rd[0].mux_rd_rise1_r1[0]_i_2_n_0\ : STD_LOGIC;
  signal \gen_mux_rd[0].mux_rd_rise2_r1[0]_i_2_n_0\ : STD_LOGIC;
  signal \gen_mux_rd[0].mux_rd_rise3_r1[0]_i_2_n_0\ : STD_LOGIC;
  signal \gen_mux_rd[1].mux_rd_fall0_r1[1]_i_2_n_0\ : STD_LOGIC;
  signal \gen_mux_rd[1].mux_rd_fall1_r1[1]_i_2_n_0\ : STD_LOGIC;
  signal \gen_mux_rd[1].mux_rd_fall2_r1[1]_i_2_n_0\ : STD_LOGIC;
  signal \gen_mux_rd[1].mux_rd_fall3_r1[1]_i_2_n_0\ : STD_LOGIC;
  signal \gen_mux_rd[1].mux_rd_rise0_r1[1]_i_2_n_0\ : STD_LOGIC;
  signal \gen_mux_rd[1].mux_rd_rise1_r1[1]_i_2_n_0\ : STD_LOGIC;
  signal \gen_mux_rd[1].mux_rd_rise2_r1[1]_i_2_n_0\ : STD_LOGIC;
  signal \gen_mux_rd[1].mux_rd_rise3_r1[1]_i_2_n_0\ : STD_LOGIC;
  signal \gen_mux_rd[2].mux_rd_fall0_r1[2]_i_2_n_0\ : STD_LOGIC;
  signal \gen_mux_rd[2].mux_rd_fall1_r1[2]_i_2_n_0\ : STD_LOGIC;
  signal \gen_mux_rd[2].mux_rd_fall2_r1[2]_i_2_n_0\ : STD_LOGIC;
  signal \gen_mux_rd[2].mux_rd_fall3_r1[2]_i_2_n_0\ : STD_LOGIC;
  signal \gen_mux_rd[2].mux_rd_rise0_r1[2]_i_2_n_0\ : STD_LOGIC;
  signal \gen_mux_rd[2].mux_rd_rise1_r1[2]_i_2_n_0\ : STD_LOGIC;
  signal \gen_mux_rd[2].mux_rd_rise2_r1[2]_i_2_n_0\ : STD_LOGIC;
  signal \gen_mux_rd[2].mux_rd_rise3_r1[2]_i_2_n_0\ : STD_LOGIC;
  signal \gen_mux_rd[3].mux_rd_fall0_r1[3]_i_2_n_0\ : STD_LOGIC;
  signal \gen_mux_rd[3].mux_rd_fall1_r1[3]_i_2_n_0\ : STD_LOGIC;
  signal \gen_mux_rd[3].mux_rd_fall2_r1[3]_i_2_n_0\ : STD_LOGIC;
  signal \gen_mux_rd[3].mux_rd_fall3_r1[3]_i_2_n_0\ : STD_LOGIC;
  signal \gen_mux_rd[3].mux_rd_rise0_r1[3]_i_2_n_0\ : STD_LOGIC;
  signal \gen_mux_rd[3].mux_rd_rise1_r1[3]_i_2_n_0\ : STD_LOGIC;
  signal \gen_mux_rd[3].mux_rd_rise2_r1[3]_i_2_n_0\ : STD_LOGIC;
  signal \gen_mux_rd[3].mux_rd_rise3_r1[3]_i_2_n_0\ : STD_LOGIC;
  signal \gen_mux_rd[4].mux_rd_fall0_r1[4]_i_2_n_0\ : STD_LOGIC;
  signal \gen_mux_rd[4].mux_rd_fall1_r1[4]_i_2_n_0\ : STD_LOGIC;
  signal \gen_mux_rd[4].mux_rd_fall2_r1[4]_i_2_n_0\ : STD_LOGIC;
  signal \gen_mux_rd[4].mux_rd_fall3_r1[4]_i_2_n_0\ : STD_LOGIC;
  signal \gen_mux_rd[4].mux_rd_rise0_r1[4]_i_2_n_0\ : STD_LOGIC;
  signal \gen_mux_rd[4].mux_rd_rise1_r1[4]_i_2_n_0\ : STD_LOGIC;
  signal \gen_mux_rd[4].mux_rd_rise2_r1[4]_i_2_n_0\ : STD_LOGIC;
  signal \gen_mux_rd[4].mux_rd_rise3_r1[4]_i_2_n_0\ : STD_LOGIC;
  signal \gen_mux_rd[5].mux_rd_fall0_r1[5]_i_2_n_0\ : STD_LOGIC;
  signal \gen_mux_rd[5].mux_rd_fall1_r1[5]_i_2_n_0\ : STD_LOGIC;
  signal \gen_mux_rd[5].mux_rd_fall2_r1[5]_i_2_n_0\ : STD_LOGIC;
  signal \gen_mux_rd[5].mux_rd_fall3_r1[5]_i_2_n_0\ : STD_LOGIC;
  signal \gen_mux_rd[5].mux_rd_rise0_r1[5]_i_2_n_0\ : STD_LOGIC;
  signal \gen_mux_rd[5].mux_rd_rise1_r1[5]_i_2_n_0\ : STD_LOGIC;
  signal \gen_mux_rd[5].mux_rd_rise2_r1[5]_i_2_n_0\ : STD_LOGIC;
  signal \gen_mux_rd[5].mux_rd_rise3_r1[5]_i_2_n_0\ : STD_LOGIC;
  signal \gen_mux_rd[6].mux_rd_fall0_r1[6]_i_2_n_0\ : STD_LOGIC;
  signal \gen_mux_rd[6].mux_rd_fall1_r1[6]_i_2_n_0\ : STD_LOGIC;
  signal \gen_mux_rd[6].mux_rd_fall2_r1[6]_i_2_n_0\ : STD_LOGIC;
  signal \gen_mux_rd[6].mux_rd_fall3_r1[6]_i_2_n_0\ : STD_LOGIC;
  signal \gen_mux_rd[6].mux_rd_rise0_r1[6]_i_2_n_0\ : STD_LOGIC;
  signal \gen_mux_rd[6].mux_rd_rise1_r1[6]_i_2_n_0\ : STD_LOGIC;
  signal \gen_mux_rd[6].mux_rd_rise2_r1[6]_i_2_n_0\ : STD_LOGIC;
  signal \gen_mux_rd[6].mux_rd_rise3_r1[6]_i_2_n_0\ : STD_LOGIC;
  signal \gen_mux_rd[7].mux_rd_fall0_r1[7]_i_2_n_0\ : STD_LOGIC;
  signal \gen_mux_rd[7].mux_rd_fall1_r1[7]_i_2_n_0\ : STD_LOGIC;
  signal \gen_mux_rd[7].mux_rd_fall2_r1[7]_i_2_n_0\ : STD_LOGIC;
  signal \gen_mux_rd[7].mux_rd_fall3_r1[7]_i_2_n_0\ : STD_LOGIC;
  signal \gen_mux_rd[7].mux_rd_rise0_r1[7]_i_2_n_0\ : STD_LOGIC;
  signal \gen_mux_rd[7].mux_rd_rise1_r1[7]_i_2_n_0\ : STD_LOGIC;
  signal \gen_mux_rd[7].mux_rd_rise2_r1[7]_i_2_n_0\ : STD_LOGIC;
  signal \gen_mux_rd[7].mux_rd_rise3_r1[7]_i_2_n_0\ : STD_LOGIC;
  signal \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r[0]_i_2_n_0\ : STD_LOGIC;
  signal \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r[0]_i_2_n_0\ : STD_LOGIC;
  signal \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r[0]_i_2_n_0\ : STD_LOGIC;
  signal \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r[0]_i_2_n_0\ : STD_LOGIC;
  signal \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r[0]_i_2_n_0\ : STD_LOGIC;
  signal \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r[0]_i_2_n_0\ : STD_LOGIC;
  signal \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise2_r[0]_i_2_n_0\ : STD_LOGIC;
  signal \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r[0]_i_2_n_0\ : STD_LOGIC;
  signal \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r[1]_i_2_n_0\ : STD_LOGIC;
  signal \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r[1]_i_2_n_0\ : STD_LOGIC;
  signal \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r[1]_i_2_n_0\ : STD_LOGIC;
  signal \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r[1]_i_2_n_0\ : STD_LOGIC;
  signal \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r[1]_i_2_n_0\ : STD_LOGIC;
  signal \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r[1]_i_2_n_0\ : STD_LOGIC;
  signal \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r[1]_i_2_n_0\ : STD_LOGIC;
  signal \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r[1]_i_2_n_0\ : STD_LOGIC;
  signal \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r[2]_i_2_n_0\ : STD_LOGIC;
  signal \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r[2]_i_2_n_0\ : STD_LOGIC;
  signal \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r[2]_i_2_n_0\ : STD_LOGIC;
  signal \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r[2]_i_2_n_0\ : STD_LOGIC;
  signal \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r[2]_i_2_n_0\ : STD_LOGIC;
  signal \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r[2]_i_2_n_0\ : STD_LOGIC;
  signal \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r[2]_i_2_n_0\ : STD_LOGIC;
  signal \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r[2]_i_2_n_0\ : STD_LOGIC;
  signal \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r[3]_i_2_n_0\ : STD_LOGIC;
  signal \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r[3]_i_2_n_0\ : STD_LOGIC;
  signal \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r[3]_i_2_n_0\ : STD_LOGIC;
  signal \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r[3]_i_2_n_0\ : STD_LOGIC;
  signal \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r[3]_i_2_n_0\ : STD_LOGIC;
  signal \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r[3]_i_2_n_0\ : STD_LOGIC;
  signal \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r[3]_i_2_n_0\ : STD_LOGIC;
  signal \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise3_r[3]_i_2_n_0\ : STD_LOGIC;
  signal \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r[4]_i_2_n_0\ : STD_LOGIC;
  signal \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r[4]_i_2_n_0\ : STD_LOGIC;
  signal \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r[4]_i_2_n_0\ : STD_LOGIC;
  signal \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r[4]_i_2_n_0\ : STD_LOGIC;
  signal \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r[4]_i_2_n_0\ : STD_LOGIC;
  signal \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r[4]_i_2_n_0\ : STD_LOGIC;
  signal \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise2_r[4]_i_2_n_0\ : STD_LOGIC;
  signal \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r[4]_i_2_n_0\ : STD_LOGIC;
  signal \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r[5]_i_2_n_0\ : STD_LOGIC;
  signal \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r[5]_i_2_n_0\ : STD_LOGIC;
  signal \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r[5]_i_2_n_0\ : STD_LOGIC;
  signal \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r[5]_i_2_n_0\ : STD_LOGIC;
  signal \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r[5]_i_2_n_0\ : STD_LOGIC;
  signal \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r[5]_i_2_n_0\ : STD_LOGIC;
  signal \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r[5]_i_2_n_0\ : STD_LOGIC;
  signal \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r[5]_i_2_n_0\ : STD_LOGIC;
  signal \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r[6]_i_2_n_0\ : STD_LOGIC;
  signal \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r[6]_i_2_n_0\ : STD_LOGIC;
  signal \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r[6]_i_2_n_0\ : STD_LOGIC;
  signal \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r[6]_i_2_n_0\ : STD_LOGIC;
  signal \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r[6]_i_2_n_0\ : STD_LOGIC;
  signal \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r[6]_i_2_n_0\ : STD_LOGIC;
  signal \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r[6]_i_2_n_0\ : STD_LOGIC;
  signal \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r[6]_i_2_n_0\ : STD_LOGIC;
  signal \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r[7]_i_2_n_0\ : STD_LOGIC;
  signal \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r[7]_i_2_n_0\ : STD_LOGIC;
  signal \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r[7]_i_2_n_0\ : STD_LOGIC;
  signal \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r[7]_i_2_n_0\ : STD_LOGIC;
  signal \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r[7]_i_2_n_0\ : STD_LOGIC;
  signal \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r[7]_i_2_n_0\ : STD_LOGIC;
  signal \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r[7]_i_2_n_0\ : STD_LOGIC;
  signal \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise3_r[7]_i_2_n_0\ : STD_LOGIC;
  signal mem_out : STD_LOGIC_VECTOR ( 79 downto 16 );
  signal mem_reg_0_3_12_17_n_0 : STD_LOGIC;
  signal mem_reg_0_3_12_17_n_1 : STD_LOGIC;
  signal mem_reg_0_3_12_17_n_2 : STD_LOGIC;
  signal mem_reg_0_3_12_17_n_3 : STD_LOGIC;
  signal my_empty : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal \my_empty[4]_i_1__2_n_0\ : STD_LOGIC;
  signal \my_empty[4]_i_2__6_n_0\ : STD_LOGIC;
  signal \my_empty_inst_rep__6_n_0\ : STD_LOGIC;
  signal \my_empty_reg[4]_rep__0_n_0\ : STD_LOGIC;
  signal \my_empty_reg[4]_rep_n_0\ : STD_LOGIC;
  signal my_full : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \my_full[0]_i_1__6_n_0\ : STD_LOGIC;
  signal \my_full[1]_i_1__6_n_0\ : STD_LOGIC;
  signal \my_full[1]_i_2__6_n_0\ : STD_LOGIC;
  signal rd_ptr : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \rd_ptr[0]_i_1__6_n_0\ : STD_LOGIC;
  signal \rd_ptr[1]_i_1__6_n_0\ : STD_LOGIC;
  signal rd_ptr_timing : STD_LOGIC_VECTOR ( 1 downto 0 );
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of rd_ptr_timing : signal is "true";
  attribute syn_maxfan : string;
  attribute syn_maxfan of rd_ptr_timing : signal is "10";
  signal \rd_ptr_timing[0]_i_1__14_n_0\ : STD_LOGIC;
  signal \rd_ptr_timing[1]_i_1__14_n_0\ : STD_LOGIC;
  signal wr_en : STD_LOGIC;
  attribute MAX_FANOUT : string;
  attribute MAX_FANOUT of wr_en : signal is "40";
  attribute RTL_MAX_FANOUT : string;
  attribute RTL_MAX_FANOUT of wr_en : signal is "found";
  attribute syn_maxfan of wr_en : signal is "10";
  signal wr_ptr : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \wr_ptr[0]_i_1__14_n_0\ : STD_LOGIC;
  signal \wr_ptr[1]_i_1__14_n_0\ : STD_LOGIC;
  signal NLW_mem_reg_0_3_12_17_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_3_18_23_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_3_24_29_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_3_30_35_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_3_36_41_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_3_42_47_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_3_48_53_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_3_54_59_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_3_60_65_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_3_66_71_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_3_72_77_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_3_78_79_DOB_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_3_78_79_DOC_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_3_78_79_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \app_rd_data[152]_INST_0\ : label is "soft_lutpair1103";
  attribute SOFT_HLUTNM of \app_rd_data[153]_INST_0\ : label is "soft_lutpair1098";
  attribute SOFT_HLUTNM of \app_rd_data[154]_INST_0\ : label is "soft_lutpair1107";
  attribute SOFT_HLUTNM of \app_rd_data[155]_INST_0\ : label is "soft_lutpair1101";
  attribute SOFT_HLUTNM of \app_rd_data[156]_INST_0\ : label is "soft_lutpair1096";
  attribute SOFT_HLUTNM of \app_rd_data[157]_INST_0\ : label is "soft_lutpair1105";
  attribute SOFT_HLUTNM of \app_rd_data[158]_INST_0\ : label is "soft_lutpair1099";
  attribute SOFT_HLUTNM of \app_rd_data[159]_INST_0\ : label is "soft_lutpair1095";
  attribute SOFT_HLUTNM of \app_rd_data[216]_INST_0\ : label is "soft_lutpair1122";
  attribute SOFT_HLUTNM of \app_rd_data[217]_INST_0\ : label is "soft_lutpair1112";
  attribute SOFT_HLUTNM of \app_rd_data[218]_INST_0\ : label is "soft_lutpair1118";
  attribute SOFT_HLUTNM of \app_rd_data[219]_INST_0\ : label is "soft_lutpair1118";
  attribute SOFT_HLUTNM of \app_rd_data[220]_INST_0\ : label is "soft_lutpair1110";
  attribute SOFT_HLUTNM of \app_rd_data[221]_INST_0\ : label is "soft_lutpair1117";
  attribute SOFT_HLUTNM of \app_rd_data[222]_INST_0\ : label is "soft_lutpair1116";
  attribute SOFT_HLUTNM of \app_rd_data[223]_INST_0\ : label is "soft_lutpair1106";
  attribute SOFT_HLUTNM of \app_rd_data[24]_INST_0\ : label is "soft_lutpair1108";
  attribute SOFT_HLUTNM of \app_rd_data[25]_INST_0\ : label is "soft_lutpair1102";
  attribute SOFT_HLUTNM of \app_rd_data[26]_INST_0\ : label is "soft_lutpair1097";
  attribute SOFT_HLUTNM of \app_rd_data[27]_INST_0\ : label is "soft_lutpair1092";
  attribute SOFT_HLUTNM of \app_rd_data[280]_INST_0\ : label is "soft_lutpair1098";
  attribute SOFT_HLUTNM of \app_rd_data[281]_INST_0\ : label is "soft_lutpair1107";
  attribute SOFT_HLUTNM of \app_rd_data[282]_INST_0\ : label is "soft_lutpair1101";
  attribute SOFT_HLUTNM of \app_rd_data[283]_INST_0\ : label is "soft_lutpair1092";
  attribute SOFT_HLUTNM of \app_rd_data[284]_INST_0\ : label is "soft_lutpair1105";
  attribute SOFT_HLUTNM of \app_rd_data[285]_INST_0\ : label is "soft_lutpair1100";
  attribute SOFT_HLUTNM of \app_rd_data[286]_INST_0\ : label is "soft_lutpair1095";
  attribute SOFT_HLUTNM of \app_rd_data[287]_INST_0\ : label is "soft_lutpair1104";
  attribute SOFT_HLUTNM of \app_rd_data[28]_INST_0\ : label is "soft_lutpair1094";
  attribute SOFT_HLUTNM of \app_rd_data[29]_INST_0\ : label is "soft_lutpair1093";
  attribute SOFT_HLUTNM of \app_rd_data[30]_INST_0\ : label is "soft_lutpair1094";
  attribute SOFT_HLUTNM of \app_rd_data[31]_INST_0\ : label is "soft_lutpair1093";
  attribute SOFT_HLUTNM of \app_rd_data[344]_INST_0\ : label is "soft_lutpair1113";
  attribute SOFT_HLUTNM of \app_rd_data[345]_INST_0\ : label is "soft_lutpair1121";
  attribute SOFT_HLUTNM of \app_rd_data[346]_INST_0\ : label is "soft_lutpair1120";
  attribute SOFT_HLUTNM of \app_rd_data[347]_INST_0\ : label is "soft_lutpair1111";
  attribute SOFT_HLUTNM of \app_rd_data[348]_INST_0\ : label is "soft_lutpair1119";
  attribute SOFT_HLUTNM of \app_rd_data[349]_INST_0\ : label is "soft_lutpair1116";
  attribute SOFT_HLUTNM of \app_rd_data[350]_INST_0\ : label is "soft_lutpair1106";
  attribute SOFT_HLUTNM of \app_rd_data[351]_INST_0\ : label is "soft_lutpair1114";
  attribute SOFT_HLUTNM of \app_rd_data[408]_INST_0\ : label is "soft_lutpair1108";
  attribute SOFT_HLUTNM of \app_rd_data[409]_INST_0\ : label is "soft_lutpair1102";
  attribute SOFT_HLUTNM of \app_rd_data[410]_INST_0\ : label is "soft_lutpair1097";
  attribute SOFT_HLUTNM of \app_rd_data[411]_INST_0\ : label is "soft_lutpair1103";
  attribute SOFT_HLUTNM of \app_rd_data[412]_INST_0\ : label is "soft_lutpair1100";
  attribute SOFT_HLUTNM of \app_rd_data[413]_INST_0\ : label is "soft_lutpair1096";
  attribute SOFT_HLUTNM of \app_rd_data[414]_INST_0\ : label is "soft_lutpair1104";
  attribute SOFT_HLUTNM of \app_rd_data[415]_INST_0\ : label is "soft_lutpair1099";
  attribute SOFT_HLUTNM of \app_rd_data[472]_INST_0\ : label is "soft_lutpair1123";
  attribute SOFT_HLUTNM of \app_rd_data[473]_INST_0\ : label is "soft_lutpair1121";
  attribute SOFT_HLUTNM of \app_rd_data[474]_INST_0\ : label is "soft_lutpair1111";
  attribute SOFT_HLUTNM of \app_rd_data[475]_INST_0\ : label is "soft_lutpair1113";
  attribute SOFT_HLUTNM of \app_rd_data[476]_INST_0\ : label is "soft_lutpair1117";
  attribute SOFT_HLUTNM of \app_rd_data[477]_INST_0\ : label is "soft_lutpair1109";
  attribute SOFT_HLUTNM of \app_rd_data[478]_INST_0\ : label is "soft_lutpair1115";
  attribute SOFT_HLUTNM of \app_rd_data[479]_INST_0\ : label is "soft_lutpair1114";
  attribute SOFT_HLUTNM of \app_rd_data[88]_INST_0\ : label is "soft_lutpair1123";
  attribute SOFT_HLUTNM of \app_rd_data[89]_INST_0\ : label is "soft_lutpair1122";
  attribute SOFT_HLUTNM of \app_rd_data[90]_INST_0\ : label is "soft_lutpair1112";
  attribute SOFT_HLUTNM of \app_rd_data[91]_INST_0\ : label is "soft_lutpair1120";
  attribute SOFT_HLUTNM of \app_rd_data[92]_INST_0\ : label is "soft_lutpair1119";
  attribute SOFT_HLUTNM of \app_rd_data[93]_INST_0\ : label is "soft_lutpair1110";
  attribute SOFT_HLUTNM of \app_rd_data[94]_INST_0\ : label is "soft_lutpair1109";
  attribute SOFT_HLUTNM of \app_rd_data[95]_INST_0\ : label is "soft_lutpair1115";
  attribute METHODOLOGY_DRC_VIOS : string;
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_3_12_17 : label is "";
  attribute RTL_RAM_BITS : integer;
  attribute RTL_RAM_BITS of mem_reg_0_3_12_17 : label is 320;
  attribute RTL_RAM_NAME : string;
  attribute RTL_RAM_NAME of mem_reg_0_3_12_17 : label is "dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem";
  attribute ram_addr_begin : integer;
  attribute ram_addr_begin of mem_reg_0_3_12_17 : label is 0;
  attribute ram_addr_end : integer;
  attribute ram_addr_end of mem_reg_0_3_12_17 : label is 3;
  attribute ram_offset : integer;
  attribute ram_offset of mem_reg_0_3_12_17 : label is 0;
  attribute ram_slice_begin : integer;
  attribute ram_slice_begin of mem_reg_0_3_12_17 : label is 12;
  attribute ram_slice_end : integer;
  attribute ram_slice_end of mem_reg_0_3_12_17 : label is 17;
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_3_18_23 : label is "";
  attribute RTL_RAM_BITS of mem_reg_0_3_18_23 : label is 320;
  attribute RTL_RAM_NAME of mem_reg_0_3_18_23 : label is "dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem";
  attribute ram_addr_begin of mem_reg_0_3_18_23 : label is 0;
  attribute ram_addr_end of mem_reg_0_3_18_23 : label is 3;
  attribute ram_offset of mem_reg_0_3_18_23 : label is 0;
  attribute ram_slice_begin of mem_reg_0_3_18_23 : label is 18;
  attribute ram_slice_end of mem_reg_0_3_18_23 : label is 23;
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_3_24_29 : label is "";
  attribute RTL_RAM_BITS of mem_reg_0_3_24_29 : label is 320;
  attribute RTL_RAM_NAME of mem_reg_0_3_24_29 : label is "dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem";
  attribute ram_addr_begin of mem_reg_0_3_24_29 : label is 0;
  attribute ram_addr_end of mem_reg_0_3_24_29 : label is 3;
  attribute ram_offset of mem_reg_0_3_24_29 : label is 0;
  attribute ram_slice_begin of mem_reg_0_3_24_29 : label is 24;
  attribute ram_slice_end of mem_reg_0_3_24_29 : label is 29;
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_3_30_35 : label is "";
  attribute RTL_RAM_BITS of mem_reg_0_3_30_35 : label is 320;
  attribute RTL_RAM_NAME of mem_reg_0_3_30_35 : label is "dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem";
  attribute ram_addr_begin of mem_reg_0_3_30_35 : label is 0;
  attribute ram_addr_end of mem_reg_0_3_30_35 : label is 3;
  attribute ram_offset of mem_reg_0_3_30_35 : label is 0;
  attribute ram_slice_begin of mem_reg_0_3_30_35 : label is 30;
  attribute ram_slice_end of mem_reg_0_3_30_35 : label is 35;
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_3_36_41 : label is "";
  attribute RTL_RAM_BITS of mem_reg_0_3_36_41 : label is 320;
  attribute RTL_RAM_NAME of mem_reg_0_3_36_41 : label is "dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem";
  attribute ram_addr_begin of mem_reg_0_3_36_41 : label is 0;
  attribute ram_addr_end of mem_reg_0_3_36_41 : label is 3;
  attribute ram_offset of mem_reg_0_3_36_41 : label is 0;
  attribute ram_slice_begin of mem_reg_0_3_36_41 : label is 36;
  attribute ram_slice_end of mem_reg_0_3_36_41 : label is 41;
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_3_42_47 : label is "";
  attribute RTL_RAM_BITS of mem_reg_0_3_42_47 : label is 320;
  attribute RTL_RAM_NAME of mem_reg_0_3_42_47 : label is "dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem";
  attribute ram_addr_begin of mem_reg_0_3_42_47 : label is 0;
  attribute ram_addr_end of mem_reg_0_3_42_47 : label is 3;
  attribute ram_offset of mem_reg_0_3_42_47 : label is 0;
  attribute ram_slice_begin of mem_reg_0_3_42_47 : label is 42;
  attribute ram_slice_end of mem_reg_0_3_42_47 : label is 47;
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_3_48_53 : label is "";
  attribute RTL_RAM_BITS of mem_reg_0_3_48_53 : label is 320;
  attribute RTL_RAM_NAME of mem_reg_0_3_48_53 : label is "dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem";
  attribute ram_addr_begin of mem_reg_0_3_48_53 : label is 0;
  attribute ram_addr_end of mem_reg_0_3_48_53 : label is 3;
  attribute ram_offset of mem_reg_0_3_48_53 : label is 0;
  attribute ram_slice_begin of mem_reg_0_3_48_53 : label is 48;
  attribute ram_slice_end of mem_reg_0_3_48_53 : label is 53;
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_3_54_59 : label is "";
  attribute RTL_RAM_BITS of mem_reg_0_3_54_59 : label is 320;
  attribute RTL_RAM_NAME of mem_reg_0_3_54_59 : label is "dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem";
  attribute ram_addr_begin of mem_reg_0_3_54_59 : label is 0;
  attribute ram_addr_end of mem_reg_0_3_54_59 : label is 3;
  attribute ram_offset of mem_reg_0_3_54_59 : label is 0;
  attribute ram_slice_begin of mem_reg_0_3_54_59 : label is 54;
  attribute ram_slice_end of mem_reg_0_3_54_59 : label is 59;
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_3_60_65 : label is "";
  attribute RTL_RAM_BITS of mem_reg_0_3_60_65 : label is 320;
  attribute RTL_RAM_NAME of mem_reg_0_3_60_65 : label is "dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem";
  attribute ram_addr_begin of mem_reg_0_3_60_65 : label is 0;
  attribute ram_addr_end of mem_reg_0_3_60_65 : label is 3;
  attribute ram_offset of mem_reg_0_3_60_65 : label is 0;
  attribute ram_slice_begin of mem_reg_0_3_60_65 : label is 60;
  attribute ram_slice_end of mem_reg_0_3_60_65 : label is 65;
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_3_66_71 : label is "";
  attribute RTL_RAM_BITS of mem_reg_0_3_66_71 : label is 320;
  attribute RTL_RAM_NAME of mem_reg_0_3_66_71 : label is "dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem";
  attribute ram_addr_begin of mem_reg_0_3_66_71 : label is 0;
  attribute ram_addr_end of mem_reg_0_3_66_71 : label is 3;
  attribute ram_offset of mem_reg_0_3_66_71 : label is 0;
  attribute ram_slice_begin of mem_reg_0_3_66_71 : label is 66;
  attribute ram_slice_end of mem_reg_0_3_66_71 : label is 71;
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_3_72_77 : label is "";
  attribute RTL_RAM_BITS of mem_reg_0_3_72_77 : label is 320;
  attribute RTL_RAM_NAME of mem_reg_0_3_72_77 : label is "dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem";
  attribute ram_addr_begin of mem_reg_0_3_72_77 : label is 0;
  attribute ram_addr_end of mem_reg_0_3_72_77 : label is 3;
  attribute ram_offset of mem_reg_0_3_72_77 : label is 0;
  attribute ram_slice_begin of mem_reg_0_3_72_77 : label is 72;
  attribute ram_slice_end of mem_reg_0_3_72_77 : label is 77;
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_3_78_79 : label is "";
  attribute RTL_RAM_BITS of mem_reg_0_3_78_79 : label is 320;
  attribute RTL_RAM_NAME of mem_reg_0_3_78_79 : label is "dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem";
  attribute ram_addr_begin of mem_reg_0_3_78_79 : label is 0;
  attribute ram_addr_end of mem_reg_0_3_78_79 : label is 3;
  attribute ram_offset of mem_reg_0_3_78_79 : label is 0;
  attribute ram_slice_begin of mem_reg_0_3_78_79 : label is 78;
  attribute ram_slice_end of mem_reg_0_3_78_79 : label is 79;
  attribute SOFT_HLUTNM of \my_empty_inst__28\ : label is "soft_lutpair1090";
  attribute SOFT_HLUTNM of \my_empty_inst__29\ : label is "soft_lutpair1124";
  attribute SOFT_HLUTNM of \my_empty_inst__30\ : label is "soft_lutpair1124";
  attribute IS_FANOUT_CONSTRAINED : integer;
  attribute IS_FANOUT_CONSTRAINED of \my_empty_inst_rep__6\ : label is 1;
  attribute ORIG_CELL_NAME : string;
  attribute ORIG_CELL_NAME of \my_empty_reg[4]\ : label is "my_empty_reg[4]";
  attribute ORIG_CELL_NAME of \my_empty_reg[4]_rep\ : label is "my_empty_reg[4]";
  attribute ORIG_CELL_NAME of \my_empty_reg[4]_rep__0\ : label is "my_empty_reg[4]";
  attribute SOFT_HLUTNM of phy_if_empty_r_i_3 : label is "soft_lutpair1090";
  attribute SOFT_HLUTNM of \rd_ptr[0]_i_1__6\ : label is "soft_lutpair1091";
  attribute SOFT_HLUTNM of \rd_ptr[1]_i_1__6\ : label is "soft_lutpair1091";
  attribute syn_maxfan of \rd_ptr_reg[0]\ : label is "10";
  attribute syn_maxfan of \rd_ptr_reg[1]\ : label is "10";
  attribute KEEP : string;
  attribute KEEP of \rd_ptr_timing_reg[0]\ : label is "yes";
  attribute syn_maxfan of \rd_ptr_timing_reg[0]\ : label is "10";
  attribute KEEP of \rd_ptr_timing_reg[1]\ : label is "yes";
  attribute syn_maxfan of \rd_ptr_timing_reg[1]\ : label is "10";
  attribute syn_maxfan of \wr_ptr_reg[0]\ : label is "10";
  attribute syn_maxfan of \wr_ptr_reg[1]\ : label is "10";
begin
  \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0\ <= \^dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]\;
\app_rd_data[152]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(6),
      I1 => \my_empty_inst_rep__6_n_0\,
      I2 => mem_out(18),
      O => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]\
    );
\app_rd_data[153]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(14),
      I1 => \my_empty_inst_rep__6_n_0\,
      I2 => mem_out(26),
      O => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]\
    );
\app_rd_data[154]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(22),
      I1 => \my_empty_inst_rep__6_n_0\,
      I2 => mem_out(34),
      O => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]\
    );
\app_rd_data[155]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(30),
      I1 => \my_empty_inst_rep__6_n_0\,
      I2 => mem_out(42),
      O => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]\
    );
\app_rd_data[156]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(38),
      I1 => my_empty(4),
      I2 => mem_out(50),
      O => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]\
    );
\app_rd_data[157]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(46),
      I1 => my_empty(4),
      I2 => mem_out(58),
      O => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]\
    );
\app_rd_data[158]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(54),
      I1 => my_empty(4),
      I2 => mem_out(66),
      O => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]\
    );
\app_rd_data[159]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(62),
      I1 => my_empty(4),
      I2 => mem_out(74),
      O => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]\
    );
\app_rd_data[216]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(7),
      I1 => \my_empty_inst_rep__6_n_0\,
      I2 => mem_out(19),
      O => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]\
    );
\app_rd_data[217]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(15),
      I1 => \my_empty_inst_rep__6_n_0\,
      I2 => mem_out(27),
      O => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]\
    );
\app_rd_data[218]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(23),
      I1 => \my_empty_inst_rep__6_n_0\,
      I2 => mem_out(35),
      O => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]\
    );
\app_rd_data[219]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(31),
      I1 => \my_empty_inst_rep__6_n_0\,
      I2 => mem_out(43),
      O => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]\
    );
\app_rd_data[220]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(39),
      I1 => my_empty(4),
      I2 => mem_out(51),
      O => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]\
    );
\app_rd_data[221]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(47),
      I1 => my_empty(4),
      I2 => mem_out(59),
      O => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]\
    );
\app_rd_data[222]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(55),
      I1 => my_empty(4),
      I2 => mem_out(67),
      O => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]\
    );
\app_rd_data[223]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(63),
      I1 => my_empty(4),
      I2 => mem_out(75),
      O => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]\
    );
\app_rd_data[24]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(4),
      I1 => \my_empty_inst_rep__6_n_0\,
      I2 => mem_out(16),
      O => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]\
    );
\app_rd_data[25]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(12),
      I1 => \my_empty_inst_rep__6_n_0\,
      I2 => mem_out(24),
      O => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]\
    );
\app_rd_data[26]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(20),
      I1 => \my_empty_inst_rep__6_n_0\,
      I2 => mem_out(32),
      O => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]\
    );
\app_rd_data[27]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(28),
      I1 => \my_empty_inst_rep__6_n_0\,
      I2 => mem_out(40),
      O => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]\
    );
\app_rd_data[280]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(8),
      I1 => \my_empty_inst_rep__6_n_0\,
      I2 => mem_out(20),
      O => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]\
    );
\app_rd_data[281]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(16),
      I1 => \my_empty_inst_rep__6_n_0\,
      I2 => mem_out(28),
      O => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]\
    );
\app_rd_data[282]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(24),
      I1 => \my_empty_inst_rep__6_n_0\,
      I2 => mem_out(36),
      O => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]\
    );
\app_rd_data[283]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(32),
      I1 => \my_empty_inst_rep__6_n_0\,
      I2 => mem_out(44),
      O => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]\
    );
\app_rd_data[284]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(40),
      I1 => my_empty(4),
      I2 => mem_out(52),
      O => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]\
    );
\app_rd_data[285]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(48),
      I1 => my_empty(4),
      I2 => mem_out(60),
      O => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]\
    );
\app_rd_data[286]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(56),
      I1 => my_empty(4),
      I2 => mem_out(68),
      O => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]\
    );
\app_rd_data[287]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(64),
      I1 => my_empty(4),
      I2 => mem_out(76),
      O => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]\
    );
\app_rd_data[28]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(36),
      I1 => my_empty(4),
      I2 => mem_out(48),
      O => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]\
    );
\app_rd_data[29]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(44),
      I1 => my_empty(4),
      I2 => mem_out(56),
      O => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]\
    );
\app_rd_data[30]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(52),
      I1 => my_empty(4),
      I2 => mem_out(64),
      O => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]\
    );
\app_rd_data[31]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(60),
      I1 => my_empty(4),
      I2 => mem_out(72),
      O => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]\
    );
\app_rd_data[344]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(9),
      I1 => \my_empty_inst_rep__6_n_0\,
      I2 => mem_out(21),
      O => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]\
    );
\app_rd_data[345]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(17),
      I1 => \my_empty_inst_rep__6_n_0\,
      I2 => mem_out(29),
      O => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]\
    );
\app_rd_data[346]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(25),
      I1 => \my_empty_inst_rep__6_n_0\,
      I2 => mem_out(37),
      O => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]\
    );
\app_rd_data[347]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(33),
      I1 => \my_empty_inst_rep__6_n_0\,
      I2 => mem_out(45),
      O => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]\
    );
\app_rd_data[348]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(41),
      I1 => my_empty(4),
      I2 => mem_out(53),
      O => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]\
    );
\app_rd_data[349]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(49),
      I1 => my_empty(4),
      I2 => mem_out(61),
      O => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]\
    );
\app_rd_data[350]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(57),
      I1 => my_empty(4),
      I2 => mem_out(69),
      O => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]\
    );
\app_rd_data[351]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(65),
      I1 => my_empty(4),
      I2 => mem_out(77),
      O => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]\
    );
\app_rd_data[408]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(10),
      I1 => \my_empty_inst_rep__6_n_0\,
      I2 => mem_out(22),
      O => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]\
    );
\app_rd_data[409]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(18),
      I1 => \my_empty_inst_rep__6_n_0\,
      I2 => mem_out(30),
      O => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]\
    );
\app_rd_data[410]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(26),
      I1 => \my_empty_inst_rep__6_n_0\,
      I2 => mem_out(38),
      O => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]\
    );
\app_rd_data[411]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(34),
      I1 => \my_empty_inst_rep__6_n_0\,
      I2 => mem_out(46),
      O => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]\
    );
\app_rd_data[412]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(42),
      I1 => my_empty(4),
      I2 => mem_out(54),
      O => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]\
    );
\app_rd_data[413]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(50),
      I1 => my_empty(4),
      I2 => mem_out(62),
      O => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]\
    );
\app_rd_data[414]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(58),
      I1 => my_empty(4),
      I2 => mem_out(70),
      O => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]\
    );
\app_rd_data[415]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(66),
      I1 => my_empty(4),
      I2 => mem_out(78),
      O => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]\
    );
\app_rd_data[472]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(11),
      I1 => \my_empty_inst_rep__6_n_0\,
      I2 => mem_out(23),
      O => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]\
    );
\app_rd_data[473]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(19),
      I1 => \my_empty_inst_rep__6_n_0\,
      I2 => mem_out(31),
      O => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]\
    );
\app_rd_data[474]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(27),
      I1 => \my_empty_inst_rep__6_n_0\,
      I2 => mem_out(39),
      O => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]\
    );
\app_rd_data[475]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(35),
      I1 => \my_empty_inst_rep__6_n_0\,
      I2 => mem_out(47),
      O => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]\
    );
\app_rd_data[476]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(43),
      I1 => my_empty(4),
      I2 => mem_out(55),
      O => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]\
    );
\app_rd_data[477]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(51),
      I1 => my_empty(4),
      I2 => mem_out(63),
      O => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]\
    );
\app_rd_data[478]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(59),
      I1 => my_empty(4),
      I2 => mem_out(71),
      O => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]\
    );
\app_rd_data[479]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(67),
      I1 => my_empty(4),
      I2 => mem_out(79),
      O => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]\
    );
\app_rd_data[88]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(5),
      I1 => \my_empty_inst_rep__6_n_0\,
      I2 => mem_out(17),
      O => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]\
    );
\app_rd_data[89]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(13),
      I1 => \my_empty_inst_rep__6_n_0\,
      I2 => mem_out(25),
      O => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]\
    );
\app_rd_data[90]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(21),
      I1 => \my_empty_inst_rep__6_n_0\,
      I2 => mem_out(33),
      O => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]\
    );
\app_rd_data[91]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(29),
      I1 => \my_empty_inst_rep__6_n_0\,
      I2 => mem_out(41),
      O => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]\
    );
\app_rd_data[92]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(37),
      I1 => my_empty(4),
      I2 => mem_out(49),
      O => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]\
    );
\app_rd_data[93]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(45),
      I1 => my_empty(4),
      I2 => mem_out(57),
      O => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]\
    );
\app_rd_data[94]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(53),
      I1 => my_empty(4),
      I2 => mem_out(65),
      O => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]\
    );
\app_rd_data[95]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(61),
      I1 => my_empty(4),
      I2 => mem_out(73),
      O => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]\
    );
\gen_mux_rd[0].mux_rd_fall0_r1[0]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]\,
      I1 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg[0]\,
      I2 => \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]\(1),
      I3 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg[0]_0\,
      I4 => \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]\(0),
      I5 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg[0]_1\,
      O => \gen_mux_rd[0].mux_rd_fall0_r1[0]_i_2_n_0\
    );
\gen_mux_rd[0].mux_rd_fall0_r1_reg[0]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gen_mux_rd[0].mux_rd_fall0_r1[0]_i_2_n_0\,
      I1 => \gen_mux_rd[0].mux_rd_fall0_r1_reg[0]\,
      O => \rd_mux_sel_r_reg[2]_7\,
      S => \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]\(2)
    );
\gen_mux_rd[0].mux_rd_fall1_r1[0]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]\,
      I1 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg[0]\,
      I2 => \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]\(1),
      I3 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg[0]_0\,
      I4 => \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]\(0),
      I5 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg[0]_1\,
      O => \gen_mux_rd[0].mux_rd_fall1_r1[0]_i_2_n_0\
    );
\gen_mux_rd[0].mux_rd_fall1_r1_reg[0]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gen_mux_rd[0].mux_rd_fall1_r1[0]_i_2_n_0\,
      I1 => \gen_mux_rd[0].mux_rd_fall1_r1_reg[0]\,
      O => \rd_mux_sel_r_reg[2]_23\,
      S => \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]\(2)
    );
\gen_mux_rd[0].mux_rd_fall2_r1[0]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]\,
      I1 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg[0]\,
      I2 => \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]\(1),
      I3 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg[0]_0\,
      I4 => \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]\(0),
      I5 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg[0]_1\,
      O => \gen_mux_rd[0].mux_rd_fall2_r1[0]_i_2_n_0\
    );
\gen_mux_rd[0].mux_rd_fall2_r1_reg[0]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gen_mux_rd[0].mux_rd_fall2_r1[0]_i_2_n_0\,
      I1 => \gen_mux_rd[0].mux_rd_fall2_r1_reg[0]\,
      O => \rd_mux_sel_r_reg[2]_39\,
      S => \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]\(2)
    );
\gen_mux_rd[0].mux_rd_fall3_r1[0]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]\,
      I1 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg[0]\,
      I2 => \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]\(1),
      I3 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg[0]_0\,
      I4 => \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]\(0),
      I5 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg[0]_1\,
      O => \gen_mux_rd[0].mux_rd_fall3_r1[0]_i_2_n_0\
    );
\gen_mux_rd[0].mux_rd_fall3_r1_reg[0]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gen_mux_rd[0].mux_rd_fall3_r1[0]_i_2_n_0\,
      I1 => \gen_mux_rd[0].mux_rd_fall3_r1_reg[0]\,
      O => \rd_mux_sel_r_reg[2]_55\,
      S => \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]\(2)
    );
\gen_mux_rd[0].mux_rd_rise0_r1[0]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]\,
      I1 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg[0]\,
      I2 => \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]\(1),
      I3 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg[0]_0\,
      I4 => \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]\(0),
      I5 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg[0]_1\,
      O => \gen_mux_rd[0].mux_rd_rise0_r1[0]_i_2_n_0\
    );
\gen_mux_rd[0].mux_rd_rise0_r1_reg[0]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gen_mux_rd[0].mux_rd_rise0_r1[0]_i_2_n_0\,
      I1 => \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]_0\,
      O => \rd_mux_sel_r_reg[2]\,
      S => \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]\(2)
    );
\gen_mux_rd[0].mux_rd_rise1_r1[0]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]\,
      I1 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]\,
      I2 => \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]\(1),
      I3 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_0\,
      I4 => \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]\(0),
      I5 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_1\,
      O => \gen_mux_rd[0].mux_rd_rise1_r1[0]_i_2_n_0\
    );
\gen_mux_rd[0].mux_rd_rise1_r1_reg[0]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gen_mux_rd[0].mux_rd_rise1_r1[0]_i_2_n_0\,
      I1 => \gen_mux_rd[0].mux_rd_rise1_r1_reg[0]\,
      O => \rd_mux_sel_r_reg[2]_15\,
      S => \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]\(2)
    );
\gen_mux_rd[0].mux_rd_rise2_r1[0]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]\,
      I1 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise2_r_reg[0]\,
      I2 => \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]\(1),
      I3 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise2_r_reg[0]_0\,
      I4 => \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]\(0),
      I5 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise2_r_reg[0]_1\,
      O => \gen_mux_rd[0].mux_rd_rise2_r1[0]_i_2_n_0\
    );
\gen_mux_rd[0].mux_rd_rise2_r1_reg[0]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gen_mux_rd[0].mux_rd_rise2_r1[0]_i_2_n_0\,
      I1 => \gen_mux_rd[0].mux_rd_rise2_r1_reg[0]\,
      O => \rd_mux_sel_r_reg[2]_31\,
      S => \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]\(2)
    );
\gen_mux_rd[0].mux_rd_rise3_r1[0]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]\,
      I1 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg[0]\,
      I2 => \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]\(1),
      I3 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg[0]_0\,
      I4 => \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]\(0),
      I5 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg[0]_1\,
      O => \gen_mux_rd[0].mux_rd_rise3_r1[0]_i_2_n_0\
    );
\gen_mux_rd[0].mux_rd_rise3_r1_reg[0]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gen_mux_rd[0].mux_rd_rise3_r1[0]_i_2_n_0\,
      I1 => \gen_mux_rd[0].mux_rd_rise3_r1_reg[0]\,
      O => \rd_mux_sel_r_reg[2]_47\,
      S => \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]\(2)
    );
\gen_mux_rd[1].mux_rd_fall0_r1[1]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]\,
      I1 => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg[1]\,
      I2 => \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]\(1),
      I3 => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg[1]_0\,
      I4 => \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]\(0),
      I5 => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg[1]_1\,
      O => \gen_mux_rd[1].mux_rd_fall0_r1[1]_i_2_n_0\
    );
\gen_mux_rd[1].mux_rd_fall0_r1_reg[1]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gen_mux_rd[1].mux_rd_fall0_r1[1]_i_2_n_0\,
      I1 => \gen_mux_rd[1].mux_rd_fall0_r1_reg[1]\,
      O => \rd_mux_sel_r_reg[2]_8\,
      S => \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]\(2)
    );
\gen_mux_rd[1].mux_rd_fall1_r1[1]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]\,
      I1 => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg[1]\,
      I2 => \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]\(1),
      I3 => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg[1]_0\,
      I4 => \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]\(0),
      I5 => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg[1]_1\,
      O => \gen_mux_rd[1].mux_rd_fall1_r1[1]_i_2_n_0\
    );
\gen_mux_rd[1].mux_rd_fall1_r1_reg[1]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gen_mux_rd[1].mux_rd_fall1_r1[1]_i_2_n_0\,
      I1 => \gen_mux_rd[1].mux_rd_fall1_r1_reg[1]\,
      O => \rd_mux_sel_r_reg[2]_24\,
      S => \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]\(2)
    );
\gen_mux_rd[1].mux_rd_fall2_r1[1]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]\,
      I1 => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg[1]\,
      I2 => \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]\(1),
      I3 => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg[1]_0\,
      I4 => \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]\(0),
      I5 => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg[1]_1\,
      O => \gen_mux_rd[1].mux_rd_fall2_r1[1]_i_2_n_0\
    );
\gen_mux_rd[1].mux_rd_fall2_r1_reg[1]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gen_mux_rd[1].mux_rd_fall2_r1[1]_i_2_n_0\,
      I1 => \gen_mux_rd[1].mux_rd_fall2_r1_reg[1]\,
      O => \rd_mux_sel_r_reg[2]_40\,
      S => \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]\(2)
    );
\gen_mux_rd[1].mux_rd_fall3_r1[1]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]\,
      I1 => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg[1]\,
      I2 => \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]\(1),
      I3 => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg[1]_0\,
      I4 => \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]\(0),
      I5 => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg[1]_1\,
      O => \gen_mux_rd[1].mux_rd_fall3_r1[1]_i_2_n_0\
    );
\gen_mux_rd[1].mux_rd_fall3_r1_reg[1]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gen_mux_rd[1].mux_rd_fall3_r1[1]_i_2_n_0\,
      I1 => \gen_mux_rd[1].mux_rd_fall3_r1_reg[1]\,
      O => \rd_mux_sel_r_reg[2]_56\,
      S => \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]\(2)
    );
\gen_mux_rd[1].mux_rd_rise0_r1[1]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]\,
      I1 => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg[1]\,
      I2 => \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]\(1),
      I3 => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg[1]_0\,
      I4 => \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]\(0),
      I5 => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg[1]_1\,
      O => \gen_mux_rd[1].mux_rd_rise0_r1[1]_i_2_n_0\
    );
\gen_mux_rd[1].mux_rd_rise0_r1_reg[1]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gen_mux_rd[1].mux_rd_rise0_r1[1]_i_2_n_0\,
      I1 => \gen_mux_rd[1].mux_rd_rise0_r1_reg[1]\,
      O => \rd_mux_sel_r_reg[2]_0\,
      S => \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]\(2)
    );
\gen_mux_rd[1].mux_rd_rise1_r1[1]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]\,
      I1 => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg[1]\,
      I2 => \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]\(1),
      I3 => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg[1]_0\,
      I4 => \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]\(0),
      I5 => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg[1]_1\,
      O => \gen_mux_rd[1].mux_rd_rise1_r1[1]_i_2_n_0\
    );
\gen_mux_rd[1].mux_rd_rise1_r1_reg[1]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gen_mux_rd[1].mux_rd_rise1_r1[1]_i_2_n_0\,
      I1 => \gen_mux_rd[1].mux_rd_rise1_r1_reg[1]\,
      O => \rd_mux_sel_r_reg[2]_16\,
      S => \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]\(2)
    );
\gen_mux_rd[1].mux_rd_rise2_r1[1]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]\,
      I1 => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg[1]\,
      I2 => \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]\(1),
      I3 => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg[1]_0\,
      I4 => \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]\(0),
      I5 => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg[1]_1\,
      O => \gen_mux_rd[1].mux_rd_rise2_r1[1]_i_2_n_0\
    );
\gen_mux_rd[1].mux_rd_rise2_r1_reg[1]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gen_mux_rd[1].mux_rd_rise2_r1[1]_i_2_n_0\,
      I1 => \gen_mux_rd[1].mux_rd_rise2_r1_reg[1]\,
      O => \rd_mux_sel_r_reg[2]_32\,
      S => \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]\(2)
    );
\gen_mux_rd[1].mux_rd_rise3_r1[1]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]\,
      I1 => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg[1]\,
      I2 => \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]\(1),
      I3 => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg[1]_0\,
      I4 => \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]\(0),
      I5 => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg[1]_1\,
      O => \gen_mux_rd[1].mux_rd_rise3_r1[1]_i_2_n_0\
    );
\gen_mux_rd[1].mux_rd_rise3_r1_reg[1]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gen_mux_rd[1].mux_rd_rise3_r1[1]_i_2_n_0\,
      I1 => \gen_mux_rd[1].mux_rd_rise3_r1_reg[1]\,
      O => \rd_mux_sel_r_reg[2]_48\,
      S => \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]\(2)
    );
\gen_mux_rd[2].mux_rd_fall0_r1[2]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]\,
      I1 => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg[2]\,
      I2 => \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]\(1),
      I3 => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg[2]_0\,
      I4 => \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]\(0),
      I5 => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg[2]_1\,
      O => \gen_mux_rd[2].mux_rd_fall0_r1[2]_i_2_n_0\
    );
\gen_mux_rd[2].mux_rd_fall0_r1_reg[2]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gen_mux_rd[2].mux_rd_fall0_r1[2]_i_2_n_0\,
      I1 => \gen_mux_rd[2].mux_rd_fall0_r1_reg[2]\,
      O => \rd_mux_sel_r_reg[2]_9\,
      S => \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]\(2)
    );
\gen_mux_rd[2].mux_rd_fall1_r1[2]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]\,
      I1 => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg[2]\,
      I2 => \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]\(1),
      I3 => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg[2]_0\,
      I4 => \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]\(0),
      I5 => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg[2]_1\,
      O => \gen_mux_rd[2].mux_rd_fall1_r1[2]_i_2_n_0\
    );
\gen_mux_rd[2].mux_rd_fall1_r1_reg[2]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gen_mux_rd[2].mux_rd_fall1_r1[2]_i_2_n_0\,
      I1 => \gen_mux_rd[2].mux_rd_fall1_r1_reg[2]\,
      O => \rd_mux_sel_r_reg[2]_25\,
      S => \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]\(2)
    );
\gen_mux_rd[2].mux_rd_fall2_r1[2]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]\,
      I1 => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg[2]\,
      I2 => \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]\(1),
      I3 => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg[2]_0\,
      I4 => \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]\(0),
      I5 => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg[2]_1\,
      O => \gen_mux_rd[2].mux_rd_fall2_r1[2]_i_2_n_0\
    );
\gen_mux_rd[2].mux_rd_fall2_r1_reg[2]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gen_mux_rd[2].mux_rd_fall2_r1[2]_i_2_n_0\,
      I1 => \gen_mux_rd[2].mux_rd_fall2_r1_reg[2]\,
      O => \rd_mux_sel_r_reg[2]_41\,
      S => \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]\(2)
    );
\gen_mux_rd[2].mux_rd_fall3_r1[2]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]\,
      I1 => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg[2]\,
      I2 => \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]\(1),
      I3 => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg[2]_0\,
      I4 => \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]\(0),
      I5 => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg[2]_1\,
      O => \gen_mux_rd[2].mux_rd_fall3_r1[2]_i_2_n_0\
    );
\gen_mux_rd[2].mux_rd_fall3_r1_reg[2]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gen_mux_rd[2].mux_rd_fall3_r1[2]_i_2_n_0\,
      I1 => \gen_mux_rd[2].mux_rd_fall3_r1_reg[2]\,
      O => \rd_mux_sel_r_reg[2]_57\,
      S => \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]\(2)
    );
\gen_mux_rd[2].mux_rd_rise0_r1[2]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]\,
      I1 => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg[2]\,
      I2 => \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]\(1),
      I3 => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg[2]_0\,
      I4 => \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]\(0),
      I5 => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg[2]_1\,
      O => \gen_mux_rd[2].mux_rd_rise0_r1[2]_i_2_n_0\
    );
\gen_mux_rd[2].mux_rd_rise0_r1_reg[2]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gen_mux_rd[2].mux_rd_rise0_r1[2]_i_2_n_0\,
      I1 => \gen_mux_rd[2].mux_rd_rise0_r1_reg[2]\,
      O => \rd_mux_sel_r_reg[2]_1\,
      S => \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]\(2)
    );
\gen_mux_rd[2].mux_rd_rise1_r1[2]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]\,
      I1 => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg[2]\,
      I2 => \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]\(1),
      I3 => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg[2]_0\,
      I4 => \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]\(0),
      I5 => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg[2]_1\,
      O => \gen_mux_rd[2].mux_rd_rise1_r1[2]_i_2_n_0\
    );
\gen_mux_rd[2].mux_rd_rise1_r1_reg[2]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gen_mux_rd[2].mux_rd_rise1_r1[2]_i_2_n_0\,
      I1 => \gen_mux_rd[2].mux_rd_rise1_r1_reg[2]\,
      O => \rd_mux_sel_r_reg[2]_17\,
      S => \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]\(2)
    );
\gen_mux_rd[2].mux_rd_rise2_r1[2]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]\,
      I1 => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg[2]\,
      I2 => \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]\(1),
      I3 => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg[2]_0\,
      I4 => \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]\(0),
      I5 => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg[2]_1\,
      O => \gen_mux_rd[2].mux_rd_rise2_r1[2]_i_2_n_0\
    );
\gen_mux_rd[2].mux_rd_rise2_r1_reg[2]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gen_mux_rd[2].mux_rd_rise2_r1[2]_i_2_n_0\,
      I1 => \gen_mux_rd[2].mux_rd_rise2_r1_reg[2]\,
      O => \rd_mux_sel_r_reg[2]_33\,
      S => \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]\(2)
    );
\gen_mux_rd[2].mux_rd_rise3_r1[2]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]\,
      I1 => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg[2]\,
      I2 => \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]\(1),
      I3 => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg[2]_0\,
      I4 => \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]\(0),
      I5 => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg[2]_1\,
      O => \gen_mux_rd[2].mux_rd_rise3_r1[2]_i_2_n_0\
    );
\gen_mux_rd[2].mux_rd_rise3_r1_reg[2]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gen_mux_rd[2].mux_rd_rise3_r1[2]_i_2_n_0\,
      I1 => \gen_mux_rd[2].mux_rd_rise3_r1_reg[2]\,
      O => \rd_mux_sel_r_reg[2]_49\,
      S => \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]\(2)
    );
\gen_mux_rd[3].mux_rd_fall0_r1[3]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]\,
      I1 => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg[3]\,
      I2 => \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]\(1),
      I3 => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg[3]_0\,
      I4 => \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]\(0),
      I5 => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg[3]_1\,
      O => \gen_mux_rd[3].mux_rd_fall0_r1[3]_i_2_n_0\
    );
\gen_mux_rd[3].mux_rd_fall0_r1_reg[3]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gen_mux_rd[3].mux_rd_fall0_r1[3]_i_2_n_0\,
      I1 => \gen_mux_rd[3].mux_rd_fall0_r1_reg[3]\,
      O => \rd_mux_sel_r_reg[2]_10\,
      S => \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]\(2)
    );
\gen_mux_rd[3].mux_rd_fall1_r1[3]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]\,
      I1 => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg[3]\,
      I2 => \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]\(1),
      I3 => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg[3]_0\,
      I4 => \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]\(0),
      I5 => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg[3]_1\,
      O => \gen_mux_rd[3].mux_rd_fall1_r1[3]_i_2_n_0\
    );
\gen_mux_rd[3].mux_rd_fall1_r1_reg[3]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gen_mux_rd[3].mux_rd_fall1_r1[3]_i_2_n_0\,
      I1 => \gen_mux_rd[3].mux_rd_fall1_r1_reg[3]\,
      O => \rd_mux_sel_r_reg[2]_26\,
      S => \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]\(2)
    );
\gen_mux_rd[3].mux_rd_fall2_r1[3]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]\,
      I1 => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg[3]\,
      I2 => \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]\(1),
      I3 => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg[3]_0\,
      I4 => \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]\(0),
      I5 => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg[3]_1\,
      O => \gen_mux_rd[3].mux_rd_fall2_r1[3]_i_2_n_0\
    );
\gen_mux_rd[3].mux_rd_fall2_r1_reg[3]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gen_mux_rd[3].mux_rd_fall2_r1[3]_i_2_n_0\,
      I1 => \gen_mux_rd[3].mux_rd_fall2_r1_reg[3]\,
      O => \rd_mux_sel_r_reg[2]_42\,
      S => \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]\(2)
    );
\gen_mux_rd[3].mux_rd_fall3_r1[3]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]\,
      I1 => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg[3]\,
      I2 => \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]\(1),
      I3 => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg[3]_0\,
      I4 => \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]\(0),
      I5 => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg[3]_1\,
      O => \gen_mux_rd[3].mux_rd_fall3_r1[3]_i_2_n_0\
    );
\gen_mux_rd[3].mux_rd_fall3_r1_reg[3]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gen_mux_rd[3].mux_rd_fall3_r1[3]_i_2_n_0\,
      I1 => \gen_mux_rd[3].mux_rd_fall3_r1_reg[3]\,
      O => \rd_mux_sel_r_reg[2]_58\,
      S => \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]\(2)
    );
\gen_mux_rd[3].mux_rd_rise0_r1[3]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]\,
      I1 => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg[3]\,
      I2 => \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]\(1),
      I3 => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg[3]_0\,
      I4 => \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]\(0),
      I5 => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg[3]_1\,
      O => \gen_mux_rd[3].mux_rd_rise0_r1[3]_i_2_n_0\
    );
\gen_mux_rd[3].mux_rd_rise0_r1_reg[3]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gen_mux_rd[3].mux_rd_rise0_r1[3]_i_2_n_0\,
      I1 => \gen_mux_rd[3].mux_rd_rise0_r1_reg[3]\,
      O => \rd_mux_sel_r_reg[2]_2\,
      S => \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]\(2)
    );
\gen_mux_rd[3].mux_rd_rise1_r1[3]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]\,
      I1 => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg[3]\,
      I2 => \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]\(1),
      I3 => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg[3]_0\,
      I4 => \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]\(0),
      I5 => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg[3]_1\,
      O => \gen_mux_rd[3].mux_rd_rise1_r1[3]_i_2_n_0\
    );
\gen_mux_rd[3].mux_rd_rise1_r1_reg[3]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gen_mux_rd[3].mux_rd_rise1_r1[3]_i_2_n_0\,
      I1 => \gen_mux_rd[3].mux_rd_rise1_r1_reg[3]\,
      O => \rd_mux_sel_r_reg[2]_18\,
      S => \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]\(2)
    );
\gen_mux_rd[3].mux_rd_rise2_r1[3]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]\,
      I1 => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg[3]\,
      I2 => \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]\(1),
      I3 => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg[3]_0\,
      I4 => \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]\(0),
      I5 => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg[3]_1\,
      O => \gen_mux_rd[3].mux_rd_rise2_r1[3]_i_2_n_0\
    );
\gen_mux_rd[3].mux_rd_rise2_r1_reg[3]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gen_mux_rd[3].mux_rd_rise2_r1[3]_i_2_n_0\,
      I1 => \gen_mux_rd[3].mux_rd_rise2_r1_reg[3]\,
      O => \rd_mux_sel_r_reg[2]_34\,
      S => \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]\(2)
    );
\gen_mux_rd[3].mux_rd_rise3_r1[3]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]\,
      I1 => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise3_r_reg[3]\,
      I2 => \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]\(1),
      I3 => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise3_r_reg[3]_0\,
      I4 => \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]\(0),
      I5 => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise3_r_reg[3]_1\,
      O => \gen_mux_rd[3].mux_rd_rise3_r1[3]_i_2_n_0\
    );
\gen_mux_rd[3].mux_rd_rise3_r1_reg[3]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gen_mux_rd[3].mux_rd_rise3_r1[3]_i_2_n_0\,
      I1 => \gen_mux_rd[3].mux_rd_rise3_r1_reg[3]\,
      O => \rd_mux_sel_r_reg[2]_50\,
      S => \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]\(2)
    );
\gen_mux_rd[4].mux_rd_fall0_r1[4]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]\,
      I1 => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg[4]\,
      I2 => \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]\(1),
      I3 => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg[4]_0\,
      I4 => \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]\(0),
      I5 => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg[4]_1\,
      O => \gen_mux_rd[4].mux_rd_fall0_r1[4]_i_2_n_0\
    );
\gen_mux_rd[4].mux_rd_fall0_r1_reg[4]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gen_mux_rd[4].mux_rd_fall0_r1[4]_i_2_n_0\,
      I1 => \gen_mux_rd[4].mux_rd_fall0_r1_reg[4]\,
      O => \rd_mux_sel_r_reg[2]_11\,
      S => \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]\(2)
    );
\gen_mux_rd[4].mux_rd_fall1_r1[4]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]\,
      I1 => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg[4]\,
      I2 => \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]\(1),
      I3 => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg[4]_0\,
      I4 => \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]\(0),
      I5 => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg[4]_1\,
      O => \gen_mux_rd[4].mux_rd_fall1_r1[4]_i_2_n_0\
    );
\gen_mux_rd[4].mux_rd_fall1_r1_reg[4]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gen_mux_rd[4].mux_rd_fall1_r1[4]_i_2_n_0\,
      I1 => \gen_mux_rd[4].mux_rd_fall1_r1_reg[4]\,
      O => \rd_mux_sel_r_reg[2]_27\,
      S => \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]\(2)
    );
\gen_mux_rd[4].mux_rd_fall2_r1[4]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]\,
      I1 => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg[4]\,
      I2 => \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]\(1),
      I3 => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg[4]_0\,
      I4 => \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]\(0),
      I5 => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg[4]_1\,
      O => \gen_mux_rd[4].mux_rd_fall2_r1[4]_i_2_n_0\
    );
\gen_mux_rd[4].mux_rd_fall2_r1_reg[4]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gen_mux_rd[4].mux_rd_fall2_r1[4]_i_2_n_0\,
      I1 => \gen_mux_rd[4].mux_rd_fall2_r1_reg[4]\,
      O => \rd_mux_sel_r_reg[2]_43\,
      S => \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]\(2)
    );
\gen_mux_rd[4].mux_rd_fall3_r1[4]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]\,
      I1 => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg[4]\,
      I2 => \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]\(1),
      I3 => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg[4]_0\,
      I4 => \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]\(0),
      I5 => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg[4]_1\,
      O => \gen_mux_rd[4].mux_rd_fall3_r1[4]_i_2_n_0\
    );
\gen_mux_rd[4].mux_rd_fall3_r1_reg[4]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gen_mux_rd[4].mux_rd_fall3_r1[4]_i_2_n_0\,
      I1 => \gen_mux_rd[4].mux_rd_fall3_r1_reg[4]\,
      O => \rd_mux_sel_r_reg[2]_59\,
      S => \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]\(2)
    );
\gen_mux_rd[4].mux_rd_rise0_r1[4]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]\,
      I1 => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg[4]\,
      I2 => \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]\(1),
      I3 => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg[4]_0\,
      I4 => \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]\(0),
      I5 => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg[4]_1\,
      O => \gen_mux_rd[4].mux_rd_rise0_r1[4]_i_2_n_0\
    );
\gen_mux_rd[4].mux_rd_rise0_r1_reg[4]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gen_mux_rd[4].mux_rd_rise0_r1[4]_i_2_n_0\,
      I1 => \gen_mux_rd[4].mux_rd_rise0_r1_reg[4]\,
      O => \rd_mux_sel_r_reg[2]_3\,
      S => \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]\(2)
    );
\gen_mux_rd[4].mux_rd_rise1_r1[4]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]\,
      I1 => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg[4]\,
      I2 => \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]\(1),
      I3 => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg[4]_0\,
      I4 => \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]\(0),
      I5 => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg[4]_1\,
      O => \gen_mux_rd[4].mux_rd_rise1_r1[4]_i_2_n_0\
    );
\gen_mux_rd[4].mux_rd_rise1_r1_reg[4]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gen_mux_rd[4].mux_rd_rise1_r1[4]_i_2_n_0\,
      I1 => \gen_mux_rd[4].mux_rd_rise1_r1_reg[4]\,
      O => \rd_mux_sel_r_reg[2]_19\,
      S => \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]\(2)
    );
\gen_mux_rd[4].mux_rd_rise2_r1[4]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]\,
      I1 => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise2_r_reg[4]\,
      I2 => \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]\(1),
      I3 => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise2_r_reg[4]_0\,
      I4 => \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]\(0),
      I5 => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise2_r_reg[4]_1\,
      O => \gen_mux_rd[4].mux_rd_rise2_r1[4]_i_2_n_0\
    );
\gen_mux_rd[4].mux_rd_rise2_r1_reg[4]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gen_mux_rd[4].mux_rd_rise2_r1[4]_i_2_n_0\,
      I1 => \gen_mux_rd[4].mux_rd_rise2_r1_reg[4]\,
      O => \rd_mux_sel_r_reg[2]_35\,
      S => \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]\(2)
    );
\gen_mux_rd[4].mux_rd_rise3_r1[4]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]\,
      I1 => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg[4]\,
      I2 => \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]\(1),
      I3 => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg[4]_0\,
      I4 => \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]\(0),
      I5 => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg[4]_1\,
      O => \gen_mux_rd[4].mux_rd_rise3_r1[4]_i_2_n_0\
    );
\gen_mux_rd[4].mux_rd_rise3_r1_reg[4]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gen_mux_rd[4].mux_rd_rise3_r1[4]_i_2_n_0\,
      I1 => \gen_mux_rd[4].mux_rd_rise3_r1_reg[4]\,
      O => \rd_mux_sel_r_reg[2]_51\,
      S => \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]\(2)
    );
\gen_mux_rd[5].mux_rd_fall0_r1[5]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]\,
      I1 => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg[5]\,
      I2 => \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]\(1),
      I3 => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg[5]_0\,
      I4 => \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]\(0),
      I5 => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg[5]_1\,
      O => \gen_mux_rd[5].mux_rd_fall0_r1[5]_i_2_n_0\
    );
\gen_mux_rd[5].mux_rd_fall0_r1_reg[5]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gen_mux_rd[5].mux_rd_fall0_r1[5]_i_2_n_0\,
      I1 => \gen_mux_rd[5].mux_rd_fall0_r1_reg[5]\,
      O => \rd_mux_sel_r_reg[2]_12\,
      S => \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]\(2)
    );
\gen_mux_rd[5].mux_rd_fall1_r1[5]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]\,
      I1 => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg[5]\,
      I2 => \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]\(1),
      I3 => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg[5]_0\,
      I4 => \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]\(0),
      I5 => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg[5]_1\,
      O => \gen_mux_rd[5].mux_rd_fall1_r1[5]_i_2_n_0\
    );
\gen_mux_rd[5].mux_rd_fall1_r1_reg[5]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gen_mux_rd[5].mux_rd_fall1_r1[5]_i_2_n_0\,
      I1 => \gen_mux_rd[5].mux_rd_fall1_r1_reg[5]\,
      O => \rd_mux_sel_r_reg[2]_28\,
      S => \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]\(2)
    );
\gen_mux_rd[5].mux_rd_fall2_r1[5]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]\,
      I1 => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg[5]\,
      I2 => \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]\(1),
      I3 => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg[5]_0\,
      I4 => \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]\(0),
      I5 => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg[5]_1\,
      O => \gen_mux_rd[5].mux_rd_fall2_r1[5]_i_2_n_0\
    );
\gen_mux_rd[5].mux_rd_fall2_r1_reg[5]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gen_mux_rd[5].mux_rd_fall2_r1[5]_i_2_n_0\,
      I1 => \gen_mux_rd[5].mux_rd_fall2_r1_reg[5]\,
      O => \rd_mux_sel_r_reg[2]_44\,
      S => \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]\(2)
    );
\gen_mux_rd[5].mux_rd_fall3_r1[5]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]\,
      I1 => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg[5]\,
      I2 => \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]\(1),
      I3 => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg[5]_0\,
      I4 => \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]\(0),
      I5 => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg[5]_1\,
      O => \gen_mux_rd[5].mux_rd_fall3_r1[5]_i_2_n_0\
    );
\gen_mux_rd[5].mux_rd_fall3_r1_reg[5]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gen_mux_rd[5].mux_rd_fall3_r1[5]_i_2_n_0\,
      I1 => \gen_mux_rd[5].mux_rd_fall3_r1_reg[5]\,
      O => \rd_mux_sel_r_reg[2]_60\,
      S => \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]\(2)
    );
\gen_mux_rd[5].mux_rd_rise0_r1[5]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]\,
      I1 => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg[5]\,
      I2 => \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]\(1),
      I3 => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg[5]_0\,
      I4 => \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]\(0),
      I5 => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg[5]_1\,
      O => \gen_mux_rd[5].mux_rd_rise0_r1[5]_i_2_n_0\
    );
\gen_mux_rd[5].mux_rd_rise0_r1_reg[5]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gen_mux_rd[5].mux_rd_rise0_r1[5]_i_2_n_0\,
      I1 => \gen_mux_rd[5].mux_rd_rise0_r1_reg[5]\,
      O => \rd_mux_sel_r_reg[2]_4\,
      S => \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]\(2)
    );
\gen_mux_rd[5].mux_rd_rise1_r1[5]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]\,
      I1 => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg[5]\,
      I2 => \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]\(1),
      I3 => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg[5]_0\,
      I4 => \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]\(0),
      I5 => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg[5]_1\,
      O => \gen_mux_rd[5].mux_rd_rise1_r1[5]_i_2_n_0\
    );
\gen_mux_rd[5].mux_rd_rise1_r1_reg[5]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gen_mux_rd[5].mux_rd_rise1_r1[5]_i_2_n_0\,
      I1 => \gen_mux_rd[5].mux_rd_rise1_r1_reg[5]\,
      O => \rd_mux_sel_r_reg[2]_20\,
      S => \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]\(2)
    );
\gen_mux_rd[5].mux_rd_rise2_r1[5]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]\,
      I1 => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg[5]\,
      I2 => \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]\(1),
      I3 => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg[5]_0\,
      I4 => \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]\(0),
      I5 => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg[5]_1\,
      O => \gen_mux_rd[5].mux_rd_rise2_r1[5]_i_2_n_0\
    );
\gen_mux_rd[5].mux_rd_rise2_r1_reg[5]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gen_mux_rd[5].mux_rd_rise2_r1[5]_i_2_n_0\,
      I1 => \gen_mux_rd[5].mux_rd_rise2_r1_reg[5]\,
      O => \rd_mux_sel_r_reg[2]_36\,
      S => \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]\(2)
    );
\gen_mux_rd[5].mux_rd_rise3_r1[5]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]\,
      I1 => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg[5]\,
      I2 => \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]\(1),
      I3 => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg[5]_0\,
      I4 => \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]\(0),
      I5 => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg[5]_1\,
      O => \gen_mux_rd[5].mux_rd_rise3_r1[5]_i_2_n_0\
    );
\gen_mux_rd[5].mux_rd_rise3_r1_reg[5]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gen_mux_rd[5].mux_rd_rise3_r1[5]_i_2_n_0\,
      I1 => \gen_mux_rd[5].mux_rd_rise3_r1_reg[5]\,
      O => \rd_mux_sel_r_reg[2]_52\,
      S => \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]\(2)
    );
\gen_mux_rd[6].mux_rd_fall0_r1[6]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]\,
      I1 => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg[6]\,
      I2 => \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]\(1),
      I3 => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg[6]_0\,
      I4 => \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]\(0),
      I5 => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg[6]_1\,
      O => \gen_mux_rd[6].mux_rd_fall0_r1[6]_i_2_n_0\
    );
\gen_mux_rd[6].mux_rd_fall0_r1_reg[6]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gen_mux_rd[6].mux_rd_fall0_r1[6]_i_2_n_0\,
      I1 => \gen_mux_rd[6].mux_rd_fall0_r1_reg[6]\,
      O => \rd_mux_sel_r_reg[2]_13\,
      S => \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]\(2)
    );
\gen_mux_rd[6].mux_rd_fall1_r1[6]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]\,
      I1 => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg[6]\,
      I2 => \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]\(1),
      I3 => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg[6]_0\,
      I4 => \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]\(0),
      I5 => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg[6]_1\,
      O => \gen_mux_rd[6].mux_rd_fall1_r1[6]_i_2_n_0\
    );
\gen_mux_rd[6].mux_rd_fall1_r1_reg[6]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gen_mux_rd[6].mux_rd_fall1_r1[6]_i_2_n_0\,
      I1 => \gen_mux_rd[6].mux_rd_fall1_r1_reg[6]\,
      O => \rd_mux_sel_r_reg[2]_29\,
      S => \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]\(2)
    );
\gen_mux_rd[6].mux_rd_fall2_r1[6]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]\,
      I1 => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg[6]\,
      I2 => \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]\(1),
      I3 => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg[6]_0\,
      I4 => \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]\(0),
      I5 => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg[6]_1\,
      O => \gen_mux_rd[6].mux_rd_fall2_r1[6]_i_2_n_0\
    );
\gen_mux_rd[6].mux_rd_fall2_r1_reg[6]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gen_mux_rd[6].mux_rd_fall2_r1[6]_i_2_n_0\,
      I1 => \gen_mux_rd[6].mux_rd_fall2_r1_reg[6]\,
      O => \rd_mux_sel_r_reg[2]_45\,
      S => \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]\(2)
    );
\gen_mux_rd[6].mux_rd_fall3_r1[6]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]\,
      I1 => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg[6]\,
      I2 => \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]\(1),
      I3 => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg[6]_0\,
      I4 => \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]\(0),
      I5 => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg[6]_1\,
      O => \gen_mux_rd[6].mux_rd_fall3_r1[6]_i_2_n_0\
    );
\gen_mux_rd[6].mux_rd_fall3_r1_reg[6]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gen_mux_rd[6].mux_rd_fall3_r1[6]_i_2_n_0\,
      I1 => \gen_mux_rd[6].mux_rd_fall3_r1_reg[6]\,
      O => \rd_mux_sel_r_reg[2]_61\,
      S => \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]\(2)
    );
\gen_mux_rd[6].mux_rd_rise0_r1[6]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]\,
      I1 => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg[6]\,
      I2 => \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]\(1),
      I3 => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg[6]_0\,
      I4 => \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]\(0),
      I5 => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg[6]_1\,
      O => \gen_mux_rd[6].mux_rd_rise0_r1[6]_i_2_n_0\
    );
\gen_mux_rd[6].mux_rd_rise0_r1_reg[6]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gen_mux_rd[6].mux_rd_rise0_r1[6]_i_2_n_0\,
      I1 => \gen_mux_rd[6].mux_rd_rise0_r1_reg[6]\,
      O => \rd_mux_sel_r_reg[2]_5\,
      S => \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]\(2)
    );
\gen_mux_rd[6].mux_rd_rise1_r1[6]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]\,
      I1 => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg[6]\,
      I2 => \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]\(1),
      I3 => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg[6]_0\,
      I4 => \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]\(0),
      I5 => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg[6]_1\,
      O => \gen_mux_rd[6].mux_rd_rise1_r1[6]_i_2_n_0\
    );
\gen_mux_rd[6].mux_rd_rise1_r1_reg[6]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gen_mux_rd[6].mux_rd_rise1_r1[6]_i_2_n_0\,
      I1 => \gen_mux_rd[6].mux_rd_rise1_r1_reg[6]\,
      O => \rd_mux_sel_r_reg[2]_21\,
      S => \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]\(2)
    );
\gen_mux_rd[6].mux_rd_rise2_r1[6]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]\,
      I1 => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg[6]\,
      I2 => \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]\(1),
      I3 => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg[6]_0\,
      I4 => \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]\(0),
      I5 => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg[6]_1\,
      O => \gen_mux_rd[6].mux_rd_rise2_r1[6]_i_2_n_0\
    );
\gen_mux_rd[6].mux_rd_rise2_r1_reg[6]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gen_mux_rd[6].mux_rd_rise2_r1[6]_i_2_n_0\,
      I1 => \gen_mux_rd[6].mux_rd_rise2_r1_reg[6]\,
      O => \rd_mux_sel_r_reg[2]_37\,
      S => \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]\(2)
    );
\gen_mux_rd[6].mux_rd_rise3_r1[6]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]\,
      I1 => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg[6]\,
      I2 => \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]\(1),
      I3 => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg[6]_0\,
      I4 => \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]\(0),
      I5 => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg[6]_1\,
      O => \gen_mux_rd[6].mux_rd_rise3_r1[6]_i_2_n_0\
    );
\gen_mux_rd[6].mux_rd_rise3_r1_reg[6]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gen_mux_rd[6].mux_rd_rise3_r1[6]_i_2_n_0\,
      I1 => \gen_mux_rd[6].mux_rd_rise3_r1_reg[6]\,
      O => \rd_mux_sel_r_reg[2]_53\,
      S => \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]\(2)
    );
\gen_mux_rd[7].mux_rd_fall0_r1[7]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]\,
      I1 => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg[7]\,
      I2 => \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]\(1),
      I3 => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg[7]_0\,
      I4 => \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]\(0),
      I5 => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg[7]_1\,
      O => \gen_mux_rd[7].mux_rd_fall0_r1[7]_i_2_n_0\
    );
\gen_mux_rd[7].mux_rd_fall0_r1_reg[7]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gen_mux_rd[7].mux_rd_fall0_r1[7]_i_2_n_0\,
      I1 => \gen_mux_rd[7].mux_rd_fall0_r1_reg[7]\,
      O => \rd_mux_sel_r_reg[2]_14\,
      S => \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]\(2)
    );
\gen_mux_rd[7].mux_rd_fall1_r1[7]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]\,
      I1 => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg[7]\,
      I2 => \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]\(1),
      I3 => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg[7]_0\,
      I4 => \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]\(0),
      I5 => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg[7]_1\,
      O => \gen_mux_rd[7].mux_rd_fall1_r1[7]_i_2_n_0\
    );
\gen_mux_rd[7].mux_rd_fall1_r1_reg[7]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gen_mux_rd[7].mux_rd_fall1_r1[7]_i_2_n_0\,
      I1 => \gen_mux_rd[7].mux_rd_fall1_r1_reg[7]\,
      O => \rd_mux_sel_r_reg[2]_30\,
      S => \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]\(2)
    );
\gen_mux_rd[7].mux_rd_fall2_r1[7]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]\,
      I1 => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg[7]\,
      I2 => \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]\(1),
      I3 => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg[7]_0\,
      I4 => \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]\(0),
      I5 => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg[7]_1\,
      O => \gen_mux_rd[7].mux_rd_fall2_r1[7]_i_2_n_0\
    );
\gen_mux_rd[7].mux_rd_fall2_r1_reg[7]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gen_mux_rd[7].mux_rd_fall2_r1[7]_i_2_n_0\,
      I1 => \gen_mux_rd[7].mux_rd_fall2_r1_reg[7]\,
      O => \rd_mux_sel_r_reg[2]_46\,
      S => \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]\(2)
    );
\gen_mux_rd[7].mux_rd_fall3_r1[7]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]\,
      I1 => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7]\,
      I2 => \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]\(1),
      I3 => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7]_0\,
      I4 => \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]\(0),
      I5 => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7]_1\,
      O => \gen_mux_rd[7].mux_rd_fall3_r1[7]_i_2_n_0\
    );
\gen_mux_rd[7].mux_rd_fall3_r1_reg[7]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gen_mux_rd[7].mux_rd_fall3_r1[7]_i_2_n_0\,
      I1 => \gen_mux_rd[7].mux_rd_fall3_r1_reg[7]\,
      O => \rd_mux_sel_r_reg[2]_62\,
      S => \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]\(2)
    );
\gen_mux_rd[7].mux_rd_rise0_r1[7]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]\,
      I1 => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg[7]\,
      I2 => \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]\(1),
      I3 => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg[7]_0\,
      I4 => \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]\(0),
      I5 => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg[7]_1\,
      O => \gen_mux_rd[7].mux_rd_rise0_r1[7]_i_2_n_0\
    );
\gen_mux_rd[7].mux_rd_rise0_r1_reg[7]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gen_mux_rd[7].mux_rd_rise0_r1[7]_i_2_n_0\,
      I1 => \gen_mux_rd[7].mux_rd_rise0_r1_reg[7]\,
      O => \rd_mux_sel_r_reg[2]_6\,
      S => \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]\(2)
    );
\gen_mux_rd[7].mux_rd_rise1_r1[7]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]\,
      I1 => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg[7]\,
      I2 => \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]\(1),
      I3 => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg[7]_0\,
      I4 => \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]\(0),
      I5 => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg[7]_1\,
      O => \gen_mux_rd[7].mux_rd_rise1_r1[7]_i_2_n_0\
    );
\gen_mux_rd[7].mux_rd_rise1_r1_reg[7]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gen_mux_rd[7].mux_rd_rise1_r1[7]_i_2_n_0\,
      I1 => \gen_mux_rd[7].mux_rd_rise1_r1_reg[7]\,
      O => \rd_mux_sel_r_reg[2]_22\,
      S => \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]\(2)
    );
\gen_mux_rd[7].mux_rd_rise2_r1[7]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]\,
      I1 => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg[7]\,
      I2 => \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]\(1),
      I3 => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg[7]_0\,
      I4 => \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]\(0),
      I5 => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg[7]_1\,
      O => \gen_mux_rd[7].mux_rd_rise2_r1[7]_i_2_n_0\
    );
\gen_mux_rd[7].mux_rd_rise2_r1_reg[7]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gen_mux_rd[7].mux_rd_rise2_r1[7]_i_2_n_0\,
      I1 => \gen_mux_rd[7].mux_rd_rise2_r1_reg[7]\,
      O => \rd_mux_sel_r_reg[2]_38\,
      S => \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]\(2)
    );
\gen_mux_rd[7].mux_rd_rise3_r1[7]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]\,
      I1 => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise3_r_reg[7]\,
      I2 => \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]\(1),
      I3 => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise3_r_reg[7]_0\,
      I4 => \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]\(0),
      I5 => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise3_r_reg[7]_1\,
      O => \gen_mux_rd[7].mux_rd_rise3_r1[7]_i_2_n_0\
    );
\gen_mux_rd[7].mux_rd_rise3_r1_reg[7]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gen_mux_rd[7].mux_rd_rise3_r1[7]_i_2_n_0\,
      I1 => \gen_mux_rd[7].mux_rd_rise3_r1_reg[7]\,
      O => \rd_mux_sel_r_reg[2]_54\,
      S => \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]\(2)
    );
\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r[0]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]\,
      I1 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg[0]\,
      I2 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2\(1),
      I3 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg[0]_0\,
      I4 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2\(0),
      I5 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg[0]_1\,
      O => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r[0]_i_2_n_0\
    );
\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg[0]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r[0]_i_2_n_0\,
      I1 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg[0]_2\,
      O => \po_stg2_wrcal_cnt_reg[2]_14\,
      S => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2\(2)
    );
\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r[0]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]\,
      I1 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg[0]\,
      I2 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2\(1),
      I3 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg[0]_0\,
      I4 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2\(0),
      I5 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg[0]_1\,
      O => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r[0]_i_2_n_0\
    );
\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg[0]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r[0]_i_2_n_0\,
      I1 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg[0]_2\,
      O => \po_stg2_wrcal_cnt_reg[2]_54\,
      S => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2\(2)
    );
\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r[0]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]\,
      I1 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg[0]\,
      I2 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2\(1),
      I3 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg[0]_0\,
      I4 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2\(0),
      I5 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg[0]_1\,
      O => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r[0]_i_2_n_0\
    );
\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg[0]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r[0]_i_2_n_0\,
      I1 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg[0]_2\,
      O => \po_stg2_wrcal_cnt_reg[2]_30\,
      S => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2\(2)
    );
\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r[0]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]\,
      I1 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg[0]\,
      I2 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2\(1),
      I3 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg[0]_0\,
      I4 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2\(0),
      I5 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg[0]_1\,
      O => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r[0]_i_2_n_0\
    );
\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg[0]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r[0]_i_2_n_0\,
      I1 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg[0]_2\,
      O => \po_stg2_wrcal_cnt_reg[2]_6\,
      S => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2\(2)
    );
\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r[0]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]\,
      I1 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg[0]\,
      I2 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2\(1),
      I3 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg[0]_0\,
      I4 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2\(0),
      I5 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg[0]_1\,
      O => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r[0]_i_2_n_0\
    );
\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg[0]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r[0]_i_2_n_0\,
      I1 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg[0]_2\,
      O => \po_stg2_wrcal_cnt_reg[2]_46\,
      S => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2\(2)
    );
\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r[0]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]\,
      I1 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]\,
      I2 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2\(1),
      I3 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_0\,
      I4 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2\(0),
      I5 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_1\,
      O => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r[0]_i_2_n_0\
    );
\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r[0]_i_2_n_0\,
      I1 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_3\,
      O => p_0_out,
      S => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2\(2)
    );
\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise2_r[0]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]\,
      I1 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise2_r_reg[0]\,
      I2 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2\(1),
      I3 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise2_r_reg[0]_0\,
      I4 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2\(0),
      I5 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise2_r_reg[0]_1\,
      O => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise2_r[0]_i_2_n_0\
    );
\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise2_r_reg[0]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise2_r[0]_i_2_n_0\,
      I1 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise2_r_reg[0]_2\,
      O => \po_stg2_wrcal_cnt_reg[2]_22\,
      S => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2\(2)
    );
\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r[0]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]\,
      I1 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg[0]\,
      I2 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2\(1),
      I3 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg[0]_0\,
      I4 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2\(0),
      I5 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg[0]_1\,
      O => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r[0]_i_2_n_0\
    );
\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg[0]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r[0]_i_2_n_0\,
      I1 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg[0]_2\,
      O => \po_stg2_wrcal_cnt_reg[2]_38\,
      S => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2\(2)
    );
\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r[1]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]\,
      I1 => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg[1]\,
      I2 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2\(1),
      I3 => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg[1]_0\,
      I4 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2\(0),
      I5 => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg[1]_1\,
      O => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r[1]_i_2_n_0\
    );
\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg[1]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r[1]_i_2_n_0\,
      I1 => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg[1]_2\,
      O => \po_stg2_wrcal_cnt_reg[2]_15\,
      S => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2\(2)
    );
\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r[1]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]\,
      I1 => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg[1]\,
      I2 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2\(1),
      I3 => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg[1]_0\,
      I4 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2\(0),
      I5 => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg[1]_1\,
      O => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r[1]_i_2_n_0\
    );
\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg[1]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r[1]_i_2_n_0\,
      I1 => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg[1]_2\,
      O => \po_stg2_wrcal_cnt_reg[2]_55\,
      S => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2\(2)
    );
\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r[1]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]\,
      I1 => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg[1]\,
      I2 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2\(1),
      I3 => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg[1]_0\,
      I4 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2\(0),
      I5 => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg[1]_1\,
      O => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r[1]_i_2_n_0\
    );
\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg[1]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r[1]_i_2_n_0\,
      I1 => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg[1]_2\,
      O => \po_stg2_wrcal_cnt_reg[2]_31\,
      S => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2\(2)
    );
\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r[1]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]\,
      I1 => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg[1]\,
      I2 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2\(1),
      I3 => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg[1]_0\,
      I4 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2\(0),
      I5 => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg[1]_1\,
      O => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r[1]_i_2_n_0\
    );
\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg[1]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r[1]_i_2_n_0\,
      I1 => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg[1]_2\,
      O => \po_stg2_wrcal_cnt_reg[2]_7\,
      S => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2\(2)
    );
\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r[1]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]\,
      I1 => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg[1]\,
      I2 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2\(1),
      I3 => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg[1]_0\,
      I4 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2\(0),
      I5 => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg[1]_1\,
      O => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r[1]_i_2_n_0\
    );
\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg[1]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r[1]_i_2_n_0\,
      I1 => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg[1]_2\,
      O => \po_stg2_wrcal_cnt_reg[2]_47\,
      S => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2\(2)
    );
\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r[1]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]\,
      I1 => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg[1]\,
      I2 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2\(1),
      I3 => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg[1]_0\,
      I4 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2\(0),
      I5 => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg[1]_1\,
      O => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r[1]_i_2_n_0\
    );
\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg[1]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r[1]_i_2_n_0\,
      I1 => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg[1]_2\,
      O => \po_stg2_wrcal_cnt_reg[2]\,
      S => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2\(2)
    );
\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r[1]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]\,
      I1 => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg[1]\,
      I2 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2\(1),
      I3 => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg[1]_0\,
      I4 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2\(0),
      I5 => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg[1]_1\,
      O => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r[1]_i_2_n_0\
    );
\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg[1]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r[1]_i_2_n_0\,
      I1 => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg[1]_2\,
      O => \po_stg2_wrcal_cnt_reg[2]_23\,
      S => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2\(2)
    );
\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r[1]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]\,
      I1 => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg[1]\,
      I2 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2\(1),
      I3 => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg[1]_0\,
      I4 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2\(0),
      I5 => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg[1]_1\,
      O => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r[1]_i_2_n_0\
    );
\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg[1]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r[1]_i_2_n_0\,
      I1 => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg[1]_2\,
      O => \po_stg2_wrcal_cnt_reg[2]_39\,
      S => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2\(2)
    );
\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r[2]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]\,
      I1 => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg[2]\,
      I2 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2\(1),
      I3 => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg[2]_0\,
      I4 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2\(0),
      I5 => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg[2]_1\,
      O => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r[2]_i_2_n_0\
    );
\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg[2]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r[2]_i_2_n_0\,
      I1 => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg[2]_2\,
      O => \po_stg2_wrcal_cnt_reg[2]_16\,
      S => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2\(2)
    );
\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r[2]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]\,
      I1 => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg[2]\,
      I2 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2\(1),
      I3 => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg[2]_0\,
      I4 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2\(0),
      I5 => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg[2]_1\,
      O => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r[2]_i_2_n_0\
    );
\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg[2]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r[2]_i_2_n_0\,
      I1 => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg[2]_2\,
      O => \po_stg2_wrcal_cnt_reg[2]_56\,
      S => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2\(2)
    );
\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r[2]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]\,
      I1 => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg[2]\,
      I2 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2\(1),
      I3 => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg[2]_0\,
      I4 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2\(0),
      I5 => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg[2]_1\,
      O => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r[2]_i_2_n_0\
    );
\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg[2]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r[2]_i_2_n_0\,
      I1 => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg[2]_2\,
      O => \po_stg2_wrcal_cnt_reg[2]_32\,
      S => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2\(2)
    );
\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r[2]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]\,
      I1 => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg[2]\,
      I2 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2\(1),
      I3 => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg[2]_0\,
      I4 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2\(0),
      I5 => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg[2]_1\,
      O => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r[2]_i_2_n_0\
    );
\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg[2]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r[2]_i_2_n_0\,
      I1 => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg[2]_2\,
      O => \po_stg2_wrcal_cnt_reg[2]_8\,
      S => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2\(2)
    );
\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r[2]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]\,
      I1 => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg[2]\,
      I2 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2\(1),
      I3 => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg[2]_0\,
      I4 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2\(0),
      I5 => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg[2]_1\,
      O => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r[2]_i_2_n_0\
    );
\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg[2]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r[2]_i_2_n_0\,
      I1 => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg[2]_2\,
      O => \po_stg2_wrcal_cnt_reg[2]_48\,
      S => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2\(2)
    );
\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r[2]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]\,
      I1 => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg[2]\,
      I2 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2\(1),
      I3 => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg[2]_0\,
      I4 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2\(0),
      I5 => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg[2]_1\,
      O => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r[2]_i_2_n_0\
    );
\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg[2]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r[2]_i_2_n_0\,
      I1 => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg[2]_2\,
      O => \po_stg2_wrcal_cnt_reg[2]_0\,
      S => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2\(2)
    );
\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r[2]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]\,
      I1 => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg[2]\,
      I2 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2\(1),
      I3 => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg[2]_0\,
      I4 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2\(0),
      I5 => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg[2]_1\,
      O => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r[2]_i_2_n_0\
    );
\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg[2]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r[2]_i_2_n_0\,
      I1 => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg[2]_2\,
      O => \po_stg2_wrcal_cnt_reg[2]_24\,
      S => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2\(2)
    );
\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r[2]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]\,
      I1 => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg[2]\,
      I2 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2\(1),
      I3 => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg[2]_0\,
      I4 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2\(0),
      I5 => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg[2]_1\,
      O => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r[2]_i_2_n_0\
    );
\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg[2]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r[2]_i_2_n_0\,
      I1 => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg[2]_2\,
      O => \po_stg2_wrcal_cnt_reg[2]_40\,
      S => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2\(2)
    );
\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r[3]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]\,
      I1 => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg[3]\,
      I2 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2\(1),
      I3 => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg[3]_0\,
      I4 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2\(0),
      I5 => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg[3]_1\,
      O => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r[3]_i_2_n_0\
    );
\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg[3]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r[3]_i_2_n_0\,
      I1 => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg[3]_2\,
      O => \po_stg2_wrcal_cnt_reg[2]_17\,
      S => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2\(2)
    );
\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r[3]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]\,
      I1 => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg[3]\,
      I2 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2\(1),
      I3 => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg[3]_0\,
      I4 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2\(0),
      I5 => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg[3]_1\,
      O => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r[3]_i_2_n_0\
    );
\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg[3]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r[3]_i_2_n_0\,
      I1 => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg[3]_2\,
      O => \po_stg2_wrcal_cnt_reg[2]_57\,
      S => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2\(2)
    );
\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r[3]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]\,
      I1 => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg[3]\,
      I2 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2\(1),
      I3 => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg[3]_0\,
      I4 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2\(0),
      I5 => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg[3]_1\,
      O => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r[3]_i_2_n_0\
    );
\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg[3]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r[3]_i_2_n_0\,
      I1 => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg[3]_2\,
      O => \po_stg2_wrcal_cnt_reg[2]_33\,
      S => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2\(2)
    );
\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r[3]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]\,
      I1 => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg[3]\,
      I2 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2\(1),
      I3 => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg[3]_0\,
      I4 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2\(0),
      I5 => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg[3]_1\,
      O => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r[3]_i_2_n_0\
    );
\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg[3]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r[3]_i_2_n_0\,
      I1 => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg[3]_2\,
      O => \po_stg2_wrcal_cnt_reg[2]_9\,
      S => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2\(2)
    );
\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r[3]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]\,
      I1 => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg[3]\,
      I2 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2\(1),
      I3 => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg[3]_0\,
      I4 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2\(0),
      I5 => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg[3]_1\,
      O => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r[3]_i_2_n_0\
    );
\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg[3]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r[3]_i_2_n_0\,
      I1 => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg[3]_2\,
      O => \po_stg2_wrcal_cnt_reg[2]_49\,
      S => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2\(2)
    );
\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r[3]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]\,
      I1 => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg[3]\,
      I2 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2\(1),
      I3 => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg[3]_0\,
      I4 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2\(0),
      I5 => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg[3]_1\,
      O => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r[3]_i_2_n_0\
    );
\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg[3]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r[3]_i_2_n_0\,
      I1 => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg[3]_2\,
      O => \po_stg2_wrcal_cnt_reg[2]_1\,
      S => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2\(2)
    );
\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r[3]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]\,
      I1 => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg[3]\,
      I2 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2\(1),
      I3 => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg[3]_0\,
      I4 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2\(0),
      I5 => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg[3]_1\,
      O => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r[3]_i_2_n_0\
    );
\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg[3]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r[3]_i_2_n_0\,
      I1 => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg[3]_2\,
      O => \po_stg2_wrcal_cnt_reg[2]_25\,
      S => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2\(2)
    );
\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise3_r[3]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]\,
      I1 => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise3_r_reg[3]\,
      I2 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2\(1),
      I3 => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise3_r_reg[3]_0\,
      I4 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2\(0),
      I5 => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise3_r_reg[3]_1\,
      O => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise3_r[3]_i_2_n_0\
    );
\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise3_r_reg[3]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise3_r[3]_i_2_n_0\,
      I1 => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise3_r_reg[3]_2\,
      O => \po_stg2_wrcal_cnt_reg[2]_41\,
      S => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2\(2)
    );
\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r[4]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]\,
      I1 => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg[4]\,
      I2 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2\(1),
      I3 => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg[4]_0\,
      I4 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2\(0),
      I5 => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg[4]_1\,
      O => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r[4]_i_2_n_0\
    );
\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg[4]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r[4]_i_2_n_0\,
      I1 => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg[4]_2\,
      O => \po_stg2_wrcal_cnt_reg[2]_18\,
      S => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2\(2)
    );
\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r[4]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]\,
      I1 => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg[4]\,
      I2 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2\(1),
      I3 => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg[4]_0\,
      I4 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2\(0),
      I5 => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg[4]_1\,
      O => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r[4]_i_2_n_0\
    );
\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg[4]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r[4]_i_2_n_0\,
      I1 => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg[4]_2\,
      O => \po_stg2_wrcal_cnt_reg[2]_58\,
      S => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2\(2)
    );
\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r[4]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]\,
      I1 => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg[4]\,
      I2 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2\(1),
      I3 => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg[4]_0\,
      I4 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2\(0),
      I5 => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg[4]_1\,
      O => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r[4]_i_2_n_0\
    );
\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg[4]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r[4]_i_2_n_0\,
      I1 => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg[4]_2\,
      O => \po_stg2_wrcal_cnt_reg[2]_34\,
      S => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2\(2)
    );
\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r[4]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]\,
      I1 => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg[4]\,
      I2 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2\(1),
      I3 => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg[4]_0\,
      I4 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2\(0),
      I5 => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg[4]_1\,
      O => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r[4]_i_2_n_0\
    );
\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg[4]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r[4]_i_2_n_0\,
      I1 => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg[4]_2\,
      O => \po_stg2_wrcal_cnt_reg[2]_10\,
      S => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2\(2)
    );
\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r[4]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]\,
      I1 => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg[4]\,
      I2 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2\(1),
      I3 => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg[4]_0\,
      I4 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2\(0),
      I5 => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg[4]_1\,
      O => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r[4]_i_2_n_0\
    );
\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg[4]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r[4]_i_2_n_0\,
      I1 => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg[4]_2\,
      O => \po_stg2_wrcal_cnt_reg[2]_50\,
      S => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2\(2)
    );
\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r[4]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]\,
      I1 => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg[4]\,
      I2 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2\(1),
      I3 => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg[4]_0\,
      I4 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2\(0),
      I5 => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg[4]_1\,
      O => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r[4]_i_2_n_0\
    );
\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg[4]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r[4]_i_2_n_0\,
      I1 => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg[4]_2\,
      O => \po_stg2_wrcal_cnt_reg[2]_2\,
      S => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2\(2)
    );
\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise2_r[4]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]\,
      I1 => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise2_r_reg[4]\,
      I2 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2\(1),
      I3 => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise2_r_reg[4]_0\,
      I4 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2\(0),
      I5 => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise2_r_reg[4]_1\,
      O => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise2_r[4]_i_2_n_0\
    );
\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise2_r_reg[4]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise2_r[4]_i_2_n_0\,
      I1 => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise2_r_reg[4]_2\,
      O => \po_stg2_wrcal_cnt_reg[2]_26\,
      S => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2\(2)
    );
\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r[4]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]\,
      I1 => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg[4]\,
      I2 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2\(1),
      I3 => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg[4]_0\,
      I4 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2\(0),
      I5 => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg[4]_1\,
      O => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r[4]_i_2_n_0\
    );
\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg[4]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r[4]_i_2_n_0\,
      I1 => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg[4]_2\,
      O => \po_stg2_wrcal_cnt_reg[2]_42\,
      S => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2\(2)
    );
\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r[5]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]\,
      I1 => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg[5]\,
      I2 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2\(1),
      I3 => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg[5]_0\,
      I4 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2\(0),
      I5 => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg[5]_1\,
      O => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r[5]_i_2_n_0\
    );
\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg[5]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r[5]_i_2_n_0\,
      I1 => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg[5]_2\,
      O => \po_stg2_wrcal_cnt_reg[2]_19\,
      S => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2\(2)
    );
\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r[5]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]\,
      I1 => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg[5]\,
      I2 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2\(1),
      I3 => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg[5]_0\,
      I4 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2\(0),
      I5 => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg[5]_1\,
      O => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r[5]_i_2_n_0\
    );
\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg[5]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r[5]_i_2_n_0\,
      I1 => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg[5]_2\,
      O => \po_stg2_wrcal_cnt_reg[2]_59\,
      S => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2\(2)
    );
\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r[5]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]\,
      I1 => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg[5]\,
      I2 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2\(1),
      I3 => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg[5]_0\,
      I4 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2\(0),
      I5 => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg[5]_1\,
      O => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r[5]_i_2_n_0\
    );
\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg[5]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r[5]_i_2_n_0\,
      I1 => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg[5]_2\,
      O => \po_stg2_wrcal_cnt_reg[2]_35\,
      S => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2\(2)
    );
\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r[5]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]\,
      I1 => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg[5]\,
      I2 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2\(1),
      I3 => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg[5]_0\,
      I4 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2\(0),
      I5 => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg[5]_1\,
      O => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r[5]_i_2_n_0\
    );
\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg[5]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r[5]_i_2_n_0\,
      I1 => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg[5]_2\,
      O => \po_stg2_wrcal_cnt_reg[2]_11\,
      S => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2\(2)
    );
\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r[5]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]\,
      I1 => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg[5]\,
      I2 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2\(1),
      I3 => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg[5]_0\,
      I4 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2\(0),
      I5 => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg[5]_1\,
      O => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r[5]_i_2_n_0\
    );
\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg[5]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r[5]_i_2_n_0\,
      I1 => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg[5]_2\,
      O => \po_stg2_wrcal_cnt_reg[2]_51\,
      S => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2\(2)
    );
\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r[5]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]\,
      I1 => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg[5]\,
      I2 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2\(1),
      I3 => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg[5]_0\,
      I4 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2\(0),
      I5 => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg[5]_1\,
      O => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r[5]_i_2_n_0\
    );
\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg[5]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r[5]_i_2_n_0\,
      I1 => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg[5]_2\,
      O => \po_stg2_wrcal_cnt_reg[2]_3\,
      S => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2\(2)
    );
\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r[5]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]\,
      I1 => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg[5]\,
      I2 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2\(1),
      I3 => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg[5]_0\,
      I4 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2\(0),
      I5 => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg[5]_1\,
      O => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r[5]_i_2_n_0\
    );
\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg[5]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r[5]_i_2_n_0\,
      I1 => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg[5]_2\,
      O => \po_stg2_wrcal_cnt_reg[2]_27\,
      S => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2\(2)
    );
\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r[5]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]\,
      I1 => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg[5]\,
      I2 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2\(1),
      I3 => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg[5]_0\,
      I4 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2\(0),
      I5 => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg[5]_1\,
      O => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r[5]_i_2_n_0\
    );
\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg[5]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r[5]_i_2_n_0\,
      I1 => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg[5]_2\,
      O => \po_stg2_wrcal_cnt_reg[2]_43\,
      S => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2\(2)
    );
\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r[6]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]\,
      I1 => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg[6]\,
      I2 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2\(1),
      I3 => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg[6]_0\,
      I4 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2\(0),
      I5 => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg[6]_1\,
      O => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r[6]_i_2_n_0\
    );
\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg[6]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r[6]_i_2_n_0\,
      I1 => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg[6]_2\,
      O => \po_stg2_wrcal_cnt_reg[2]_20\,
      S => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2\(2)
    );
\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r[6]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]\,
      I1 => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg[6]\,
      I2 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2\(1),
      I3 => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg[6]_0\,
      I4 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2\(0),
      I5 => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg[6]_1\,
      O => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r[6]_i_2_n_0\
    );
\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg[6]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r[6]_i_2_n_0\,
      I1 => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg[6]_2\,
      O => \po_stg2_wrcal_cnt_reg[2]_60\,
      S => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2\(2)
    );
\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r[6]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]\,
      I1 => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg[6]\,
      I2 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2\(1),
      I3 => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg[6]_0\,
      I4 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2\(0),
      I5 => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg[6]_1\,
      O => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r[6]_i_2_n_0\
    );
\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg[6]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r[6]_i_2_n_0\,
      I1 => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg[6]_2\,
      O => \po_stg2_wrcal_cnt_reg[2]_36\,
      S => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2\(2)
    );
\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r[6]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]\,
      I1 => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg[6]\,
      I2 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2\(1),
      I3 => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg[6]_0\,
      I4 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2\(0),
      I5 => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg[6]_1\,
      O => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r[6]_i_2_n_0\
    );
\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg[6]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r[6]_i_2_n_0\,
      I1 => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg[6]_2\,
      O => \po_stg2_wrcal_cnt_reg[2]_12\,
      S => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2\(2)
    );
\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r[6]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]\,
      I1 => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg[6]\,
      I2 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2\(1),
      I3 => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg[6]_0\,
      I4 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2\(0),
      I5 => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg[6]_1\,
      O => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r[6]_i_2_n_0\
    );
\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg[6]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r[6]_i_2_n_0\,
      I1 => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg[6]_2\,
      O => \po_stg2_wrcal_cnt_reg[2]_52\,
      S => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2\(2)
    );
\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r[6]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]\,
      I1 => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg[6]\,
      I2 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2\(1),
      I3 => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg[6]_0\,
      I4 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2\(0),
      I5 => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg[6]_1\,
      O => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r[6]_i_2_n_0\
    );
\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg[6]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r[6]_i_2_n_0\,
      I1 => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg[6]_2\,
      O => \po_stg2_wrcal_cnt_reg[2]_4\,
      S => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2\(2)
    );
\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r[6]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]\,
      I1 => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg[6]\,
      I2 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2\(1),
      I3 => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg[6]_0\,
      I4 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2\(0),
      I5 => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg[6]_1\,
      O => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r[6]_i_2_n_0\
    );
\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg[6]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r[6]_i_2_n_0\,
      I1 => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg[6]_2\,
      O => \po_stg2_wrcal_cnt_reg[2]_28\,
      S => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2\(2)
    );
\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r[6]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]\,
      I1 => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg[6]\,
      I2 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2\(1),
      I3 => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg[6]_0\,
      I4 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2\(0),
      I5 => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg[6]_1\,
      O => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r[6]_i_2_n_0\
    );
\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg[6]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r[6]_i_2_n_0\,
      I1 => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg[6]_2\,
      O => \po_stg2_wrcal_cnt_reg[2]_44\,
      S => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2\(2)
    );
\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r[7]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]\,
      I1 => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg[7]\,
      I2 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2\(1),
      I3 => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg[7]_0\,
      I4 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2\(0),
      I5 => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg[7]_1\,
      O => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r[7]_i_2_n_0\
    );
\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg[7]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r[7]_i_2_n_0\,
      I1 => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg[7]_2\,
      O => \po_stg2_wrcal_cnt_reg[2]_21\,
      S => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2\(2)
    );
\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r[7]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]\,
      I1 => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg[7]\,
      I2 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2\(1),
      I3 => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg[7]_0\,
      I4 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2\(0),
      I5 => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg[7]_1\,
      O => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r[7]_i_2_n_0\
    );
\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg[7]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r[7]_i_2_n_0\,
      I1 => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg[7]_2\,
      O => \po_stg2_wrcal_cnt_reg[2]_61\,
      S => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2\(2)
    );
\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r[7]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]\,
      I1 => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg[7]\,
      I2 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2\(1),
      I3 => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg[7]_0\,
      I4 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2\(0),
      I5 => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg[7]_1\,
      O => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r[7]_i_2_n_0\
    );
\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg[7]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r[7]_i_2_n_0\,
      I1 => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg[7]_2\,
      O => \po_stg2_wrcal_cnt_reg[2]_37\,
      S => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2\(2)
    );
\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r[7]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]\,
      I1 => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7]\,
      I2 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2\(1),
      I3 => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7]_0\,
      I4 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2\(0),
      I5 => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7]_1\,
      O => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r[7]_i_2_n_0\
    );
\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r[7]_i_2_n_0\,
      I1 => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7]_2\,
      O => \po_stg2_wrcal_cnt_reg[2]_13\,
      S => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2\(2)
    );
\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r[7]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]\,
      I1 => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg[7]\,
      I2 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2\(1),
      I3 => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg[7]_0\,
      I4 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2\(0),
      I5 => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg[7]_1\,
      O => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r[7]_i_2_n_0\
    );
\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg[7]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r[7]_i_2_n_0\,
      I1 => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg[7]_2\,
      O => \po_stg2_wrcal_cnt_reg[2]_53\,
      S => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2\(2)
    );
\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r[7]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]\,
      I1 => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg[7]\,
      I2 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2\(1),
      I3 => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg[7]_0\,
      I4 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2\(0),
      I5 => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg[7]_1\,
      O => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r[7]_i_2_n_0\
    );
\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg[7]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r[7]_i_2_n_0\,
      I1 => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg[7]_2\,
      O => \po_stg2_wrcal_cnt_reg[2]_5\,
      S => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2\(2)
    );
\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r[7]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]\,
      I1 => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg[7]\,
      I2 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2\(1),
      I3 => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg[7]_0\,
      I4 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2\(0),
      I5 => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg[7]_1\,
      O => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r[7]_i_2_n_0\
    );
\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg[7]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r[7]_i_2_n_0\,
      I1 => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg[7]_2\,
      O => \po_stg2_wrcal_cnt_reg[2]_29\,
      S => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2\(2)
    );
\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise3_r[7]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]\,
      I1 => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise3_r_reg[7]\,
      I2 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2\(1),
      I3 => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise3_r_reg[7]_0\,
      I4 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2\(0),
      I5 => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise3_r_reg[7]_1\,
      O => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise3_r[7]_i_2_n_0\
    );
\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise3_r_reg[7]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise3_r[7]_i_2_n_0\,
      I1 => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise3_r_reg[7]_2\,
      O => \po_stg2_wrcal_cnt_reg[2]_45\,
      S => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2\(2)
    );
mem_reg_0_3_12_17: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 2) => B"000",
      ADDRA(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRB(4 downto 2) => B"000",
      ADDRB(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRC(4 downto 2) => B"000",
      ADDRC(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRD(4 downto 2) => B"000",
      ADDRD(1 downto 0) => wr_ptr(1 downto 0),
      DIA(1 downto 0) => Q(1 downto 0),
      DIB(1 downto 0) => Q(3 downto 2),
      DIC(1 downto 0) => Q(5 downto 4),
      DID(1 downto 0) => B"00",
      DOA(1) => mem_reg_0_3_12_17_n_0,
      DOA(0) => mem_reg_0_3_12_17_n_1,
      DOB(1) => mem_reg_0_3_12_17_n_2,
      DOB(0) => mem_reg_0_3_12_17_n_3,
      DOC(1 downto 0) => mem_out(17 downto 16),
      DOD(1 downto 0) => NLW_mem_reg_0_3_12_17_DOD_UNCONNECTED(1 downto 0),
      WCLK => \rd_ptr_timing_reg[1]_0\,
      WE => wr_en
    );
\mem_reg_0_3_12_17_i_1__1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0151"
    )
        port map (
      I0 => if_empty_r_0(0),
      I1 => my_full(0),
      I2 => \my_full_reg[1]_0\,
      I3 => my_empty(2),
      O => wr_en
    );
mem_reg_0_3_18_23: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 2) => B"000",
      ADDRA(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRB(4 downto 2) => B"000",
      ADDRB(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRC(4 downto 2) => B"000",
      ADDRC(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRD(4 downto 2) => B"000",
      ADDRD(1 downto 0) => wr_ptr(1 downto 0),
      DIA(1 downto 0) => Q(7 downto 6),
      DIB(1 downto 0) => Q(9 downto 8),
      DIC(1 downto 0) => Q(11 downto 10),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => mem_out(19 downto 18),
      DOB(1 downto 0) => mem_out(21 downto 20),
      DOC(1 downto 0) => mem_out(23 downto 22),
      DOD(1 downto 0) => NLW_mem_reg_0_3_18_23_DOD_UNCONNECTED(1 downto 0),
      WCLK => \rd_ptr_timing_reg[1]_0\,
      WE => wr_en
    );
mem_reg_0_3_24_29: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 2) => B"000",
      ADDRA(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRB(4 downto 2) => B"000",
      ADDRB(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRC(4 downto 2) => B"000",
      ADDRC(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRD(4 downto 2) => B"000",
      ADDRD(1 downto 0) => wr_ptr(1 downto 0),
      DIA(1 downto 0) => Q(13 downto 12),
      DIB(1 downto 0) => Q(15 downto 14),
      DIC(1 downto 0) => Q(17 downto 16),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => mem_out(25 downto 24),
      DOB(1 downto 0) => mem_out(27 downto 26),
      DOC(1 downto 0) => mem_out(29 downto 28),
      DOD(1 downto 0) => NLW_mem_reg_0_3_24_29_DOD_UNCONNECTED(1 downto 0),
      WCLK => \rd_ptr_timing_reg[1]_0\,
      WE => wr_en
    );
mem_reg_0_3_30_35: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 2) => B"000",
      ADDRA(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRB(4 downto 2) => B"000",
      ADDRB(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRC(4 downto 2) => B"000",
      ADDRC(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRD(4 downto 2) => B"000",
      ADDRD(1 downto 0) => wr_ptr(1 downto 0),
      DIA(1 downto 0) => Q(19 downto 18),
      DIB(1 downto 0) => Q(21 downto 20),
      DIC(1 downto 0) => Q(23 downto 22),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => mem_out(31 downto 30),
      DOB(1 downto 0) => mem_out(33 downto 32),
      DOC(1 downto 0) => mem_out(35 downto 34),
      DOD(1 downto 0) => NLW_mem_reg_0_3_30_35_DOD_UNCONNECTED(1 downto 0),
      WCLK => \rd_ptr_timing_reg[1]_0\,
      WE => wr_en
    );
mem_reg_0_3_36_41: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 2) => B"000",
      ADDRA(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRB(4 downto 2) => B"000",
      ADDRB(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRC(4 downto 2) => B"000",
      ADDRC(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRD(4 downto 2) => B"000",
      ADDRD(1 downto 0) => wr_ptr(1 downto 0),
      DIA(1 downto 0) => Q(25 downto 24),
      DIB(1 downto 0) => Q(27 downto 26),
      DIC(1 downto 0) => Q(29 downto 28),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => mem_out(37 downto 36),
      DOB(1 downto 0) => mem_out(39 downto 38),
      DOC(1 downto 0) => mem_out(41 downto 40),
      DOD(1 downto 0) => NLW_mem_reg_0_3_36_41_DOD_UNCONNECTED(1 downto 0),
      WCLK => \rd_ptr_timing_reg[1]_0\,
      WE => wr_en
    );
mem_reg_0_3_42_47: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 2) => B"000",
      ADDRA(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRB(4 downto 2) => B"000",
      ADDRB(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRC(4 downto 2) => B"000",
      ADDRC(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRD(4 downto 2) => B"000",
      ADDRD(1 downto 0) => wr_ptr(1 downto 0),
      DIA(1 downto 0) => Q(31 downto 30),
      DIB(1 downto 0) => Q(33 downto 32),
      DIC(1 downto 0) => Q(35 downto 34),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => mem_out(43 downto 42),
      DOB(1 downto 0) => mem_out(45 downto 44),
      DOC(1 downto 0) => mem_out(47 downto 46),
      DOD(1 downto 0) => NLW_mem_reg_0_3_42_47_DOD_UNCONNECTED(1 downto 0),
      WCLK => \rd_ptr_timing_reg[1]_0\,
      WE => wr_en
    );
mem_reg_0_3_48_53: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 2) => B"000",
      ADDRA(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRB(4 downto 2) => B"000",
      ADDRB(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRC(4 downto 2) => B"000",
      ADDRC(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRD(4 downto 2) => B"000",
      ADDRD(1 downto 0) => wr_ptr(1 downto 0),
      DIA(1 downto 0) => Q(37 downto 36),
      DIB(1 downto 0) => Q(39 downto 38),
      DIC(1 downto 0) => Q(41 downto 40),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => mem_out(49 downto 48),
      DOB(1 downto 0) => mem_out(51 downto 50),
      DOC(1 downto 0) => mem_out(53 downto 52),
      DOD(1 downto 0) => NLW_mem_reg_0_3_48_53_DOD_UNCONNECTED(1 downto 0),
      WCLK => \rd_ptr_timing_reg[1]_0\,
      WE => wr_en
    );
mem_reg_0_3_54_59: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 2) => B"000",
      ADDRA(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRB(4 downto 2) => B"000",
      ADDRB(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRC(4 downto 2) => B"000",
      ADDRC(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRD(4 downto 2) => B"000",
      ADDRD(1 downto 0) => wr_ptr(1 downto 0),
      DIA(1 downto 0) => Q(43 downto 42),
      DIB(1 downto 0) => Q(45 downto 44),
      DIC(1 downto 0) => Q(47 downto 46),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => mem_out(55 downto 54),
      DOB(1 downto 0) => mem_out(57 downto 56),
      DOC(1 downto 0) => mem_out(59 downto 58),
      DOD(1 downto 0) => NLW_mem_reg_0_3_54_59_DOD_UNCONNECTED(1 downto 0),
      WCLK => \rd_ptr_timing_reg[1]_0\,
      WE => wr_en
    );
mem_reg_0_3_60_65: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 2) => B"000",
      ADDRA(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRB(4 downto 2) => B"000",
      ADDRB(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRC(4 downto 2) => B"000",
      ADDRC(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRD(4 downto 2) => B"000",
      ADDRD(1 downto 0) => wr_ptr(1 downto 0),
      DIA(1 downto 0) => Q(49 downto 48),
      DIB(1 downto 0) => Q(51 downto 50),
      DIC(1 downto 0) => Q(53 downto 52),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => mem_out(61 downto 60),
      DOB(1 downto 0) => mem_out(63 downto 62),
      DOC(1 downto 0) => mem_out(65 downto 64),
      DOD(1 downto 0) => NLW_mem_reg_0_3_60_65_DOD_UNCONNECTED(1 downto 0),
      WCLK => \rd_ptr_timing_reg[1]_0\,
      WE => wr_en
    );
mem_reg_0_3_66_71: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 2) => B"000",
      ADDRA(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRB(4 downto 2) => B"000",
      ADDRB(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRC(4 downto 2) => B"000",
      ADDRC(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRD(4 downto 2) => B"000",
      ADDRD(1 downto 0) => wr_ptr(1 downto 0),
      DIA(1 downto 0) => Q(55 downto 54),
      DIB(1 downto 0) => Q(57 downto 56),
      DIC(1 downto 0) => Q(59 downto 58),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => mem_out(67 downto 66),
      DOB(1 downto 0) => mem_out(69 downto 68),
      DOC(1 downto 0) => mem_out(71 downto 70),
      DOD(1 downto 0) => NLW_mem_reg_0_3_66_71_DOD_UNCONNECTED(1 downto 0),
      WCLK => \rd_ptr_timing_reg[1]_0\,
      WE => wr_en
    );
mem_reg_0_3_72_77: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 2) => B"000",
      ADDRA(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRB(4 downto 2) => B"000",
      ADDRB(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRC(4 downto 2) => B"000",
      ADDRC(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRD(4 downto 2) => B"000",
      ADDRD(1 downto 0) => wr_ptr(1 downto 0),
      DIA(1 downto 0) => Q(61 downto 60),
      DIB(1 downto 0) => Q(63 downto 62),
      DIC(1 downto 0) => Q(65 downto 64),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => mem_out(73 downto 72),
      DOB(1 downto 0) => mem_out(75 downto 74),
      DOC(1 downto 0) => mem_out(77 downto 76),
      DOD(1 downto 0) => NLW_mem_reg_0_3_72_77_DOD_UNCONNECTED(1 downto 0),
      WCLK => \rd_ptr_timing_reg[1]_0\,
      WE => wr_en
    );
mem_reg_0_3_78_79: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 2) => B"000",
      ADDRA(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRB(4 downto 2) => B"000",
      ADDRB(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRC(4 downto 2) => B"000",
      ADDRC(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRD(4 downto 2) => B"000",
      ADDRD(1 downto 0) => wr_ptr(1 downto 0),
      DIA(1 downto 0) => Q(67 downto 66),
      DIB(1 downto 0) => B"00",
      DIC(1 downto 0) => B"00",
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => mem_out(79 downto 78),
      DOB(1 downto 0) => NLW_mem_reg_0_3_78_79_DOB_UNCONNECTED(1 downto 0),
      DOC(1 downto 0) => NLW_mem_reg_0_3_78_79_DOC_UNCONNECTED(1 downto 0),
      DOD(1 downto 0) => NLW_mem_reg_0_3_78_79_DOD_UNCONNECTED(1 downto 0),
      WCLK => \rd_ptr_timing_reg[1]_0\,
      WE => wr_en
    );
\my_empty[4]_i_1__2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0018"
    )
        port map (
      I0 => \my_full_reg[1]_0\,
      I1 => if_empty_r_0(0),
      I2 => my_empty(1),
      I3 => my_full(1),
      O => \my_empty[4]_i_1__2_n_0\
    );
\my_empty[4]_i_2__6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00411400"
    )
        port map (
      I0 => my_empty(1),
      I1 => wr_ptr(1),
      I2 => rd_ptr(1),
      I3 => rd_ptr(0),
      I4 => wr_ptr(0),
      O => \my_empty[4]_i_2__6_n_0\
    );
\my_empty_inst__27\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \my_empty_reg[4]_rep_n_0\,
      O => my_empty(4)
    );
\my_empty_inst__28\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => my_empty(0),
      O => my_empty(3)
    );
\my_empty_inst__29\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => my_empty(0),
      O => my_empty(2)
    );
\my_empty_inst__30\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => my_empty(0),
      O => my_empty(1)
    );
\my_empty_inst_rep__6\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \my_empty_reg[4]_rep__0_n_0\,
      O => \my_empty_inst_rep__6_n_0\
    );
\my_empty_reg[4]\: unisim.vcomponents.FDSE
     port map (
      C => \rd_ptr_timing_reg[1]_0\,
      CE => \my_empty[4]_i_1__2_n_0\,
      D => \my_empty[4]_i_2__6_n_0\,
      Q => my_empty(0),
      S => ififo_rst
    );
\my_empty_reg[4]_rep\: unisim.vcomponents.FDSE
     port map (
      C => \rd_ptr_timing_reg[1]_0\,
      CE => \my_empty[4]_i_1__2_n_0\,
      D => \my_empty[4]_i_2__6_n_0\,
      Q => \my_empty_reg[4]_rep_n_0\,
      S => ififo_rst
    );
\my_empty_reg[4]_rep__0\: unisim.vcomponents.FDSE
     port map (
      C => \rd_ptr_timing_reg[1]_0\,
      CE => \my_empty[4]_i_1__2_n_0\,
      D => \my_empty[4]_i_2__6_n_0\,
      Q => \my_empty_reg[4]_rep__0_n_0\,
      S => ififo_rst
    );
\my_full[0]_i_1__6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAEAABAAAA2AA8"
    )
        port map (
      I0 => my_full(0),
      I1 => \my_full_reg[1]_0\,
      I2 => if_empty_r_0(0),
      I3 => my_full(1),
      I4 => my_empty(1),
      I5 => \my_full[1]_i_2__6_n_0\,
      O => \my_full[0]_i_1__6_n_0\
    );
\my_full[1]_i_1__6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"F0F1F070"
    )
        port map (
      I0 => \my_full_reg[1]_0\,
      I1 => if_empty_r_0(0),
      I2 => my_full(1),
      I3 => my_empty(1),
      I4 => \my_full[1]_i_2__6_n_0\,
      O => \my_full[1]_i_1__6_n_0\
    );
\my_full[1]_i_2__6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00411400"
    )
        port map (
      I0 => my_full(1),
      I1 => rd_ptr(1),
      I2 => wr_ptr(1),
      I3 => wr_ptr(0),
      I4 => rd_ptr(0),
      O => \my_full[1]_i_2__6_n_0\
    );
\my_full_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \rd_ptr_timing_reg[1]_0\,
      CE => '1',
      D => \my_full[0]_i_1__6_n_0\,
      Q => my_full(0),
      R => ififo_rst
    );
\my_full_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \rd_ptr_timing_reg[1]_0\,
      CE => '1',
      D => \my_full[1]_i_1__6_n_0\,
      Q => my_full(1),
      R => ififo_rst
    );
phy_if_empty_r_i_3: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFF888"
    )
        port map (
      I0 => my_empty(0),
      I1 => if_empty_r_0(0),
      I2 => phy_if_empty_r_reg(0),
      I3 => if_empty_r(0),
      I4 => phy_if_empty_r_reg_0,
      O => if_empty_v(0)
    );
\rd_ptr[0]_i_1__6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"D2"
    )
        port map (
      I0 => \my_full_reg[1]_0\,
      I1 => my_empty(1),
      I2 => rd_ptr(0),
      O => \rd_ptr[0]_i_1__6_n_0\
    );
\rd_ptr[1]_i_1__6\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F708"
    )
        port map (
      I0 => rd_ptr(0),
      I1 => \my_full_reg[1]_0\,
      I2 => my_empty(1),
      I3 => rd_ptr(1),
      O => \rd_ptr[1]_i_1__6_n_0\
    );
\rd_ptr_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \rd_ptr_timing_reg[1]_0\,
      CE => '1',
      D => \rd_ptr[0]_i_1__6_n_0\,
      Q => rd_ptr(0),
      R => ififo_rst
    );
\rd_ptr_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \rd_ptr_timing_reg[1]_0\,
      CE => '1',
      D => \rd_ptr[1]_i_1__6_n_0\,
      Q => rd_ptr(1),
      R => ififo_rst
    );
\rd_ptr_timing[0]_i_1__14\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F704"
    )
        port map (
      I0 => rd_ptr(0),
      I1 => \my_full_reg[1]_0\,
      I2 => my_empty(1),
      I3 => rd_ptr_timing(0),
      O => \rd_ptr_timing[0]_i_1__14_n_0\
    );
\rd_ptr_timing[1]_i_1__14\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FF6F0060"
    )
        port map (
      I0 => rd_ptr(0),
      I1 => rd_ptr(1),
      I2 => \my_full_reg[1]_0\,
      I3 => my_empty(1),
      I4 => rd_ptr_timing(1),
      O => \rd_ptr_timing[1]_i_1__14_n_0\
    );
\rd_ptr_timing_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \rd_ptr_timing_reg[1]_0\,
      CE => '1',
      D => \rd_ptr_timing[0]_i_1__14_n_0\,
      Q => rd_ptr_timing(0),
      R => ififo_rst
    );
\rd_ptr_timing_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \rd_ptr_timing_reg[1]_0\,
      CE => '1',
      D => \rd_ptr_timing[1]_i_1__14_n_0\,
      Q => rd_ptr_timing(1),
      R => ififo_rst
    );
\wr_ptr[0]_i_1__14\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FECE0131"
    )
        port map (
      I0 => my_full(1),
      I1 => if_empty_r_0(0),
      I2 => \my_full_reg[1]_0\,
      I3 => my_empty(1),
      I4 => wr_ptr(0),
      O => \wr_ptr[0]_i_1__14_n_0\
    );
\wr_ptr[1]_i_1__14\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFDF5FD00020A02"
    )
        port map (
      I0 => wr_ptr(0),
      I1 => my_full(1),
      I2 => if_empty_r_0(0),
      I3 => \my_full_reg[1]_0\,
      I4 => my_empty(1),
      I5 => wr_ptr(1),
      O => \wr_ptr[1]_i_1__14_n_0\
    );
\wr_ptr[1]_i_2__3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000000001"
    )
        port map (
      I0 => \^dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0\,
      I1 => \my_full_reg[1]_1\,
      I2 => \my_full_reg[1]_2\,
      I3 => \my_full_reg[1]_3\,
      I4 => \my_full_reg[1]_4\,
      I5 => \my_full_reg[1]_5\,
      O => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]\
    );
\wr_ptr[1]_i_2__4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000000001"
    )
        port map (
      I0 => \^dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0\,
      I1 => \my_full_reg[1]_5\,
      I2 => \my_full_reg[1]_2\,
      I3 => \my_full_reg[1]_3\,
      I4 => \my_full_reg[1]_4\,
      I5 => \my_full_reg[1]_1\,
      O => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1\
    );
\wr_ptr[1]_i_2__5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000000001"
    )
        port map (
      I0 => \^dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0\,
      I1 => \my_full_reg[1]_5\,
      I2 => \my_full_reg[1]_1\,
      I3 => \my_full_reg[1]_3\,
      I4 => \my_full_reg[1]_4\,
      I5 => \my_full_reg[1]_2\,
      O => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_2\
    );
\wr_ptr[1]_i_6\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => if_empty_r_0(0),
      I1 => my_empty(3),
      O => \^dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0\
    );
\wr_ptr_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \rd_ptr_timing_reg[1]_0\,
      CE => '1',
      D => \wr_ptr[0]_i_1__14_n_0\,
      Q => wr_ptr(0),
      R => ififo_rst
    );
\wr_ptr_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \rd_ptr_timing_reg[1]_0\,
      CE => '1',
      D => \wr_ptr[1]_i_1__14_n_0\,
      Q => wr_ptr(1),
      R => ififo_rst
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mig_mig_7series_v4_2_ddr_if_post_fifo_15 is
  port (
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_2\ : out STD_LOGIC;
    ififo_rst : in STD_LOGIC;
    \rd_ptr_reg[1]_0\ : in STD_LOGIC;
    if_empty_r_0 : in STD_LOGIC_VECTOR ( 0 to 0 );
    \my_full_reg[1]_0\ : in STD_LOGIC;
    \wr_ptr[1]_i_2__2\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    if_empty_r : in STD_LOGIC_VECTOR ( 0 to 0 );
    Q : in STD_LOGIC_VECTOR ( 67 downto 0 );
    \my_full_reg[1]_1\ : in STD_LOGIC;
    \my_full_reg[1]_2\ : in STD_LOGIC;
    \my_full_reg[1]_3\ : in STD_LOGIC;
    \my_full_reg[1]_4\ : in STD_LOGIC;
    \my_full_reg[1]_5\ : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of mig_mig_7series_v4_2_ddr_if_post_fifo_15 : entity is "mig_7series_v4_2_ddr_if_post_fifo";
end mig_mig_7series_v4_2_ddr_if_post_fifo_15;

architecture STRUCTURE of mig_mig_7series_v4_2_ddr_if_post_fifo_15 is
  signal \^dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0\ : STD_LOGIC;
  signal mem_out : STD_LOGIC_VECTOR ( 79 downto 16 );
  signal mem_reg_0_3_12_17_n_0 : STD_LOGIC;
  signal mem_reg_0_3_12_17_n_1 : STD_LOGIC;
  signal mem_reg_0_3_12_17_n_2 : STD_LOGIC;
  signal mem_reg_0_3_12_17_n_3 : STD_LOGIC;
  signal my_empty : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal \my_empty[4]_i_1__1_n_0\ : STD_LOGIC;
  signal \my_empty[4]_i_2__5_n_0\ : STD_LOGIC;
  signal \my_empty_inst_rep__5_n_0\ : STD_LOGIC;
  signal \my_empty_reg[4]_rep__0_n_0\ : STD_LOGIC;
  signal \my_empty_reg[4]_rep_n_0\ : STD_LOGIC;
  signal my_full : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \my_full[0]_i_1__5_n_0\ : STD_LOGIC;
  signal \my_full[1]_i_1__5_n_0\ : STD_LOGIC;
  signal \my_full[1]_i_2__5_n_0\ : STD_LOGIC;
  signal rd_ptr : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \rd_ptr[0]_i_1__5_n_0\ : STD_LOGIC;
  signal \rd_ptr[1]_i_1__5_n_0\ : STD_LOGIC;
  signal rd_ptr_timing : STD_LOGIC_VECTOR ( 1 downto 0 );
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of rd_ptr_timing : signal is "true";
  attribute syn_maxfan : string;
  attribute syn_maxfan of rd_ptr_timing : signal is "10";
  signal \rd_ptr_timing[0]_i_1__12_n_0\ : STD_LOGIC;
  signal \rd_ptr_timing[1]_i_1__12_n_0\ : STD_LOGIC;
  signal wr_en : STD_LOGIC;
  attribute MAX_FANOUT : string;
  attribute MAX_FANOUT of wr_en : signal is "40";
  attribute RTL_MAX_FANOUT : string;
  attribute RTL_MAX_FANOUT of wr_en : signal is "found";
  attribute syn_maxfan of wr_en : signal is "10";
  signal wr_ptr : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \wr_ptr[0]_i_1__12_n_0\ : STD_LOGIC;
  signal \wr_ptr[1]_i_1__12_n_0\ : STD_LOGIC;
  signal NLW_mem_reg_0_3_12_17_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_3_18_23_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_3_24_29_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_3_30_35_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_3_36_41_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_3_42_47_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_3_48_53_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_3_54_59_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_3_60_65_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_3_66_71_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_3_72_77_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_3_78_79_DOB_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_3_78_79_DOC_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_3_78_79_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \app_rd_data[144]_INST_0\ : label is "soft_lutpair1052";
  attribute SOFT_HLUTNM of \app_rd_data[145]_INST_0\ : label is "soft_lutpair1047";
  attribute SOFT_HLUTNM of \app_rd_data[146]_INST_0\ : label is "soft_lutpair1056";
  attribute SOFT_HLUTNM of \app_rd_data[147]_INST_0\ : label is "soft_lutpair1050";
  attribute SOFT_HLUTNM of \app_rd_data[148]_INST_0\ : label is "soft_lutpair1045";
  attribute SOFT_HLUTNM of \app_rd_data[149]_INST_0\ : label is "soft_lutpair1054";
  attribute SOFT_HLUTNM of \app_rd_data[150]_INST_0\ : label is "soft_lutpair1048";
  attribute SOFT_HLUTNM of \app_rd_data[151]_INST_0\ : label is "soft_lutpair1044";
  attribute SOFT_HLUTNM of \app_rd_data[16]_INST_0\ : label is "soft_lutpair1058";
  attribute SOFT_HLUTNM of \app_rd_data[17]_INST_0\ : label is "soft_lutpair1051";
  attribute SOFT_HLUTNM of \app_rd_data[18]_INST_0\ : label is "soft_lutpair1046";
  attribute SOFT_HLUTNM of \app_rd_data[19]_INST_0\ : label is "soft_lutpair1056";
  attribute SOFT_HLUTNM of \app_rd_data[208]_INST_0\ : label is "soft_lutpair1071";
  attribute SOFT_HLUTNM of \app_rd_data[209]_INST_0\ : label is "soft_lutpair1062";
  attribute SOFT_HLUTNM of \app_rd_data[20]_INST_0\ : label is "soft_lutpair1043";
  attribute SOFT_HLUTNM of \app_rd_data[210]_INST_0\ : label is "soft_lutpair1067";
  attribute SOFT_HLUTNM of \app_rd_data[211]_INST_0\ : label is "soft_lutpair1067";
  attribute SOFT_HLUTNM of \app_rd_data[212]_INST_0\ : label is "soft_lutpair1060";
  attribute SOFT_HLUTNM of \app_rd_data[213]_INST_0\ : label is "soft_lutpair1066";
  attribute SOFT_HLUTNM of \app_rd_data[214]_INST_0\ : label is "soft_lutpair1065";
  attribute SOFT_HLUTNM of \app_rd_data[215]_INST_0\ : label is "soft_lutpair1055";
  attribute SOFT_HLUTNM of \app_rd_data[21]_INST_0\ : label is "soft_lutpair1042";
  attribute SOFT_HLUTNM of \app_rd_data[22]_INST_0\ : label is "soft_lutpair1043";
  attribute SOFT_HLUTNM of \app_rd_data[23]_INST_0\ : label is "soft_lutpair1042";
  attribute SOFT_HLUTNM of \app_rd_data[272]_INST_0\ : label is "soft_lutpair1047";
  attribute SOFT_HLUTNM of \app_rd_data[273]_INST_0\ : label is "soft_lutpair1041";
  attribute SOFT_HLUTNM of \app_rd_data[274]_INST_0\ : label is "soft_lutpair1050";
  attribute SOFT_HLUTNM of \app_rd_data[275]_INST_0\ : label is "soft_lutpair1041";
  attribute SOFT_HLUTNM of \app_rd_data[276]_INST_0\ : label is "soft_lutpair1054";
  attribute SOFT_HLUTNM of \app_rd_data[277]_INST_0\ : label is "soft_lutpair1049";
  attribute SOFT_HLUTNM of \app_rd_data[278]_INST_0\ : label is "soft_lutpair1044";
  attribute SOFT_HLUTNM of \app_rd_data[279]_INST_0\ : label is "soft_lutpair1053";
  attribute SOFT_HLUTNM of \app_rd_data[336]_INST_0\ : label is "soft_lutpair1063";
  attribute SOFT_HLUTNM of \app_rd_data[337]_INST_0\ : label is "soft_lutpair1070";
  attribute SOFT_HLUTNM of \app_rd_data[338]_INST_0\ : label is "soft_lutpair1070";
  attribute SOFT_HLUTNM of \app_rd_data[339]_INST_0\ : label is "soft_lutpair1061";
  attribute SOFT_HLUTNM of \app_rd_data[340]_INST_0\ : label is "soft_lutpair1069";
  attribute SOFT_HLUTNM of \app_rd_data[341]_INST_0\ : label is "soft_lutpair1059";
  attribute SOFT_HLUTNM of \app_rd_data[342]_INST_0\ : label is "soft_lutpair1055";
  attribute SOFT_HLUTNM of \app_rd_data[343]_INST_0\ : label is "soft_lutpair1064";
  attribute SOFT_HLUTNM of \app_rd_data[400]_INST_0\ : label is "soft_lutpair1058";
  attribute SOFT_HLUTNM of \app_rd_data[401]_INST_0\ : label is "soft_lutpair1051";
  attribute SOFT_HLUTNM of \app_rd_data[402]_INST_0\ : label is "soft_lutpair1046";
  attribute SOFT_HLUTNM of \app_rd_data[403]_INST_0\ : label is "soft_lutpair1052";
  attribute SOFT_HLUTNM of \app_rd_data[404]_INST_0\ : label is "soft_lutpair1049";
  attribute SOFT_HLUTNM of \app_rd_data[405]_INST_0\ : label is "soft_lutpair1045";
  attribute SOFT_HLUTNM of \app_rd_data[406]_INST_0\ : label is "soft_lutpair1053";
  attribute SOFT_HLUTNM of \app_rd_data[407]_INST_0\ : label is "soft_lutpair1048";
  attribute SOFT_HLUTNM of \app_rd_data[464]_INST_0\ : label is "soft_lutpair1072";
  attribute SOFT_HLUTNM of \app_rd_data[465]_INST_0\ : label is "soft_lutpair1068";
  attribute SOFT_HLUTNM of \app_rd_data[466]_INST_0\ : label is "soft_lutpair1061";
  attribute SOFT_HLUTNM of \app_rd_data[467]_INST_0\ : label is "soft_lutpair1063";
  attribute SOFT_HLUTNM of \app_rd_data[468]_INST_0\ : label is "soft_lutpair1066";
  attribute SOFT_HLUTNM of \app_rd_data[469]_INST_0\ : label is "soft_lutpair1057";
  attribute SOFT_HLUTNM of \app_rd_data[470]_INST_0\ : label is "soft_lutpair1065";
  attribute SOFT_HLUTNM of \app_rd_data[471]_INST_0\ : label is "soft_lutpair1060";
  attribute SOFT_HLUTNM of \app_rd_data[80]_INST_0\ : label is "soft_lutpair1072";
  attribute SOFT_HLUTNM of \app_rd_data[81]_INST_0\ : label is "soft_lutpair1071";
  attribute SOFT_HLUTNM of \app_rd_data[82]_INST_0\ : label is "soft_lutpair1062";
  attribute SOFT_HLUTNM of \app_rd_data[83]_INST_0\ : label is "soft_lutpair1068";
  attribute SOFT_HLUTNM of \app_rd_data[84]_INST_0\ : label is "soft_lutpair1069";
  attribute SOFT_HLUTNM of \app_rd_data[85]_INST_0\ : label is "soft_lutpair1059";
  attribute SOFT_HLUTNM of \app_rd_data[86]_INST_0\ : label is "soft_lutpair1057";
  attribute SOFT_HLUTNM of \app_rd_data[87]_INST_0\ : label is "soft_lutpair1064";
  attribute METHODOLOGY_DRC_VIOS : string;
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_3_12_17 : label is "";
  attribute RTL_RAM_BITS : integer;
  attribute RTL_RAM_BITS of mem_reg_0_3_12_17 : label is 320;
  attribute RTL_RAM_NAME : string;
  attribute RTL_RAM_NAME of mem_reg_0_3_12_17 : label is "dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem";
  attribute ram_addr_begin : integer;
  attribute ram_addr_begin of mem_reg_0_3_12_17 : label is 0;
  attribute ram_addr_end : integer;
  attribute ram_addr_end of mem_reg_0_3_12_17 : label is 3;
  attribute ram_offset : integer;
  attribute ram_offset of mem_reg_0_3_12_17 : label is 0;
  attribute ram_slice_begin : integer;
  attribute ram_slice_begin of mem_reg_0_3_12_17 : label is 12;
  attribute ram_slice_end : integer;
  attribute ram_slice_end of mem_reg_0_3_12_17 : label is 17;
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_3_18_23 : label is "";
  attribute RTL_RAM_BITS of mem_reg_0_3_18_23 : label is 320;
  attribute RTL_RAM_NAME of mem_reg_0_3_18_23 : label is "dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem";
  attribute ram_addr_begin of mem_reg_0_3_18_23 : label is 0;
  attribute ram_addr_end of mem_reg_0_3_18_23 : label is 3;
  attribute ram_offset of mem_reg_0_3_18_23 : label is 0;
  attribute ram_slice_begin of mem_reg_0_3_18_23 : label is 18;
  attribute ram_slice_end of mem_reg_0_3_18_23 : label is 23;
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_3_24_29 : label is "";
  attribute RTL_RAM_BITS of mem_reg_0_3_24_29 : label is 320;
  attribute RTL_RAM_NAME of mem_reg_0_3_24_29 : label is "dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem";
  attribute ram_addr_begin of mem_reg_0_3_24_29 : label is 0;
  attribute ram_addr_end of mem_reg_0_3_24_29 : label is 3;
  attribute ram_offset of mem_reg_0_3_24_29 : label is 0;
  attribute ram_slice_begin of mem_reg_0_3_24_29 : label is 24;
  attribute ram_slice_end of mem_reg_0_3_24_29 : label is 29;
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_3_30_35 : label is "";
  attribute RTL_RAM_BITS of mem_reg_0_3_30_35 : label is 320;
  attribute RTL_RAM_NAME of mem_reg_0_3_30_35 : label is "dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem";
  attribute ram_addr_begin of mem_reg_0_3_30_35 : label is 0;
  attribute ram_addr_end of mem_reg_0_3_30_35 : label is 3;
  attribute ram_offset of mem_reg_0_3_30_35 : label is 0;
  attribute ram_slice_begin of mem_reg_0_3_30_35 : label is 30;
  attribute ram_slice_end of mem_reg_0_3_30_35 : label is 35;
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_3_36_41 : label is "";
  attribute RTL_RAM_BITS of mem_reg_0_3_36_41 : label is 320;
  attribute RTL_RAM_NAME of mem_reg_0_3_36_41 : label is "dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem";
  attribute ram_addr_begin of mem_reg_0_3_36_41 : label is 0;
  attribute ram_addr_end of mem_reg_0_3_36_41 : label is 3;
  attribute ram_offset of mem_reg_0_3_36_41 : label is 0;
  attribute ram_slice_begin of mem_reg_0_3_36_41 : label is 36;
  attribute ram_slice_end of mem_reg_0_3_36_41 : label is 41;
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_3_42_47 : label is "";
  attribute RTL_RAM_BITS of mem_reg_0_3_42_47 : label is 320;
  attribute RTL_RAM_NAME of mem_reg_0_3_42_47 : label is "dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem";
  attribute ram_addr_begin of mem_reg_0_3_42_47 : label is 0;
  attribute ram_addr_end of mem_reg_0_3_42_47 : label is 3;
  attribute ram_offset of mem_reg_0_3_42_47 : label is 0;
  attribute ram_slice_begin of mem_reg_0_3_42_47 : label is 42;
  attribute ram_slice_end of mem_reg_0_3_42_47 : label is 47;
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_3_48_53 : label is "";
  attribute RTL_RAM_BITS of mem_reg_0_3_48_53 : label is 320;
  attribute RTL_RAM_NAME of mem_reg_0_3_48_53 : label is "dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem";
  attribute ram_addr_begin of mem_reg_0_3_48_53 : label is 0;
  attribute ram_addr_end of mem_reg_0_3_48_53 : label is 3;
  attribute ram_offset of mem_reg_0_3_48_53 : label is 0;
  attribute ram_slice_begin of mem_reg_0_3_48_53 : label is 48;
  attribute ram_slice_end of mem_reg_0_3_48_53 : label is 53;
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_3_54_59 : label is "";
  attribute RTL_RAM_BITS of mem_reg_0_3_54_59 : label is 320;
  attribute RTL_RAM_NAME of mem_reg_0_3_54_59 : label is "dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem";
  attribute ram_addr_begin of mem_reg_0_3_54_59 : label is 0;
  attribute ram_addr_end of mem_reg_0_3_54_59 : label is 3;
  attribute ram_offset of mem_reg_0_3_54_59 : label is 0;
  attribute ram_slice_begin of mem_reg_0_3_54_59 : label is 54;
  attribute ram_slice_end of mem_reg_0_3_54_59 : label is 59;
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_3_60_65 : label is "";
  attribute RTL_RAM_BITS of mem_reg_0_3_60_65 : label is 320;
  attribute RTL_RAM_NAME of mem_reg_0_3_60_65 : label is "dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem";
  attribute ram_addr_begin of mem_reg_0_3_60_65 : label is 0;
  attribute ram_addr_end of mem_reg_0_3_60_65 : label is 3;
  attribute ram_offset of mem_reg_0_3_60_65 : label is 0;
  attribute ram_slice_begin of mem_reg_0_3_60_65 : label is 60;
  attribute ram_slice_end of mem_reg_0_3_60_65 : label is 65;
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_3_66_71 : label is "";
  attribute RTL_RAM_BITS of mem_reg_0_3_66_71 : label is 320;
  attribute RTL_RAM_NAME of mem_reg_0_3_66_71 : label is "dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem";
  attribute ram_addr_begin of mem_reg_0_3_66_71 : label is 0;
  attribute ram_addr_end of mem_reg_0_3_66_71 : label is 3;
  attribute ram_offset of mem_reg_0_3_66_71 : label is 0;
  attribute ram_slice_begin of mem_reg_0_3_66_71 : label is 66;
  attribute ram_slice_end of mem_reg_0_3_66_71 : label is 71;
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_3_72_77 : label is "";
  attribute RTL_RAM_BITS of mem_reg_0_3_72_77 : label is 320;
  attribute RTL_RAM_NAME of mem_reg_0_3_72_77 : label is "dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem";
  attribute ram_addr_begin of mem_reg_0_3_72_77 : label is 0;
  attribute ram_addr_end of mem_reg_0_3_72_77 : label is 3;
  attribute ram_offset of mem_reg_0_3_72_77 : label is 0;
  attribute ram_slice_begin of mem_reg_0_3_72_77 : label is 72;
  attribute ram_slice_end of mem_reg_0_3_72_77 : label is 77;
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_3_78_79 : label is "";
  attribute RTL_RAM_BITS of mem_reg_0_3_78_79 : label is 320;
  attribute RTL_RAM_NAME of mem_reg_0_3_78_79 : label is "dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem";
  attribute ram_addr_begin of mem_reg_0_3_78_79 : label is 0;
  attribute ram_addr_end of mem_reg_0_3_78_79 : label is 3;
  attribute ram_offset of mem_reg_0_3_78_79 : label is 0;
  attribute ram_slice_begin of mem_reg_0_3_78_79 : label is 78;
  attribute ram_slice_end of mem_reg_0_3_78_79 : label is 79;
  attribute SOFT_HLUTNM of \my_empty_inst__24\ : label is "soft_lutpair1039";
  attribute SOFT_HLUTNM of \my_empty_inst__25\ : label is "soft_lutpair1073";
  attribute SOFT_HLUTNM of \my_empty_inst__26\ : label is "soft_lutpair1073";
  attribute IS_FANOUT_CONSTRAINED : integer;
  attribute IS_FANOUT_CONSTRAINED of \my_empty_inst_rep__5\ : label is 1;
  attribute ORIG_CELL_NAME : string;
  attribute ORIG_CELL_NAME of \my_empty_reg[4]\ : label is "my_empty_reg[4]";
  attribute ORIG_CELL_NAME of \my_empty_reg[4]_rep\ : label is "my_empty_reg[4]";
  attribute ORIG_CELL_NAME of \my_empty_reg[4]_rep__0\ : label is "my_empty_reg[4]";
  attribute SOFT_HLUTNM of phy_if_empty_r_i_4 : label is "soft_lutpair1039";
  attribute SOFT_HLUTNM of \rd_ptr[0]_i_1__5\ : label is "soft_lutpair1040";
  attribute SOFT_HLUTNM of \rd_ptr[1]_i_1__5\ : label is "soft_lutpair1040";
  attribute syn_maxfan of \rd_ptr_reg[0]\ : label is "10";
  attribute syn_maxfan of \rd_ptr_reg[1]\ : label is "10";
  attribute KEEP : string;
  attribute KEEP of \rd_ptr_timing_reg[0]\ : label is "yes";
  attribute syn_maxfan of \rd_ptr_timing_reg[0]\ : label is "10";
  attribute KEEP of \rd_ptr_timing_reg[1]\ : label is "yes";
  attribute syn_maxfan of \rd_ptr_timing_reg[1]\ : label is "10";
  attribute SOFT_HLUTNM of \wr_ptr[1]_i_4__0\ : label is "soft_lutpair1038";
  attribute SOFT_HLUTNM of \wr_ptr[1]_i_4__2\ : label is "soft_lutpair1038";
  attribute syn_maxfan of \wr_ptr_reg[0]\ : label is "10";
  attribute syn_maxfan of \wr_ptr_reg[1]\ : label is "10";
begin
  \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0\ <= \^dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0\;
\app_rd_data[144]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(6),
      I1 => \my_empty_inst_rep__5_n_0\,
      I2 => mem_out(18),
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]\
    );
\app_rd_data[145]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(14),
      I1 => \my_empty_inst_rep__5_n_0\,
      I2 => mem_out(26),
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]\
    );
\app_rd_data[146]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(22),
      I1 => \my_empty_inst_rep__5_n_0\,
      I2 => mem_out(34),
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]\
    );
\app_rd_data[147]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(30),
      I1 => \my_empty_inst_rep__5_n_0\,
      I2 => mem_out(42),
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]\
    );
\app_rd_data[148]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(38),
      I1 => my_empty(4),
      I2 => mem_out(50),
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]\
    );
\app_rd_data[149]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(46),
      I1 => my_empty(4),
      I2 => mem_out(58),
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]\
    );
\app_rd_data[150]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(54),
      I1 => my_empty(4),
      I2 => mem_out(66),
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]\
    );
\app_rd_data[151]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(62),
      I1 => my_empty(4),
      I2 => mem_out(74),
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]\
    );
\app_rd_data[16]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(4),
      I1 => \my_empty_inst_rep__5_n_0\,
      I2 => mem_out(16),
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]\
    );
\app_rd_data[17]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(12),
      I1 => \my_empty_inst_rep__5_n_0\,
      I2 => mem_out(24),
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]\
    );
\app_rd_data[18]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(20),
      I1 => \my_empty_inst_rep__5_n_0\,
      I2 => mem_out(32),
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]\
    );
\app_rd_data[19]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(28),
      I1 => \my_empty_inst_rep__5_n_0\,
      I2 => mem_out(40),
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]\
    );
\app_rd_data[208]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(7),
      I1 => \my_empty_inst_rep__5_n_0\,
      I2 => mem_out(19),
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]\
    );
\app_rd_data[209]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(15),
      I1 => \my_empty_inst_rep__5_n_0\,
      I2 => mem_out(27),
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]\
    );
\app_rd_data[20]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(36),
      I1 => my_empty(4),
      I2 => mem_out(48),
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]\
    );
\app_rd_data[210]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(23),
      I1 => \my_empty_inst_rep__5_n_0\,
      I2 => mem_out(35),
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]\
    );
\app_rd_data[211]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(31),
      I1 => \my_empty_inst_rep__5_n_0\,
      I2 => mem_out(43),
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]\
    );
\app_rd_data[212]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(39),
      I1 => my_empty(4),
      I2 => mem_out(51),
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]\
    );
\app_rd_data[213]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(47),
      I1 => my_empty(4),
      I2 => mem_out(59),
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]\
    );
\app_rd_data[214]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(55),
      I1 => my_empty(4),
      I2 => mem_out(67),
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]\
    );
\app_rd_data[215]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(63),
      I1 => my_empty(4),
      I2 => mem_out(75),
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]\
    );
\app_rd_data[21]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(44),
      I1 => my_empty(4),
      I2 => mem_out(56),
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]\
    );
\app_rd_data[22]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(52),
      I1 => my_empty(4),
      I2 => mem_out(64),
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]\
    );
\app_rd_data[23]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(60),
      I1 => my_empty(4),
      I2 => mem_out(72),
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]\
    );
\app_rd_data[272]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(8),
      I1 => \my_empty_inst_rep__5_n_0\,
      I2 => mem_out(20),
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]\
    );
\app_rd_data[273]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(16),
      I1 => \my_empty_inst_rep__5_n_0\,
      I2 => mem_out(28),
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]\
    );
\app_rd_data[274]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(24),
      I1 => \my_empty_inst_rep__5_n_0\,
      I2 => mem_out(36),
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]\
    );
\app_rd_data[275]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(32),
      I1 => \my_empty_inst_rep__5_n_0\,
      I2 => mem_out(44),
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]\
    );
\app_rd_data[276]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(40),
      I1 => my_empty(4),
      I2 => mem_out(52),
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]\
    );
\app_rd_data[277]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(48),
      I1 => my_empty(4),
      I2 => mem_out(60),
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]\
    );
\app_rd_data[278]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(56),
      I1 => my_empty(4),
      I2 => mem_out(68),
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]\
    );
\app_rd_data[279]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(64),
      I1 => my_empty(4),
      I2 => mem_out(76),
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]\
    );
\app_rd_data[336]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(9),
      I1 => \my_empty_inst_rep__5_n_0\,
      I2 => mem_out(21),
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]\
    );
\app_rd_data[337]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(17),
      I1 => \my_empty_inst_rep__5_n_0\,
      I2 => mem_out(29),
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]\
    );
\app_rd_data[338]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(25),
      I1 => \my_empty_inst_rep__5_n_0\,
      I2 => mem_out(37),
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]\
    );
\app_rd_data[339]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(33),
      I1 => \my_empty_inst_rep__5_n_0\,
      I2 => mem_out(45),
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]\
    );
\app_rd_data[340]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(41),
      I1 => my_empty(4),
      I2 => mem_out(53),
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]\
    );
\app_rd_data[341]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(49),
      I1 => my_empty(4),
      I2 => mem_out(61),
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]\
    );
\app_rd_data[342]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(57),
      I1 => my_empty(4),
      I2 => mem_out(69),
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]\
    );
\app_rd_data[343]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(65),
      I1 => my_empty(4),
      I2 => mem_out(77),
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]\
    );
\app_rd_data[400]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(10),
      I1 => \my_empty_inst_rep__5_n_0\,
      I2 => mem_out(22),
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]\
    );
\app_rd_data[401]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(18),
      I1 => \my_empty_inst_rep__5_n_0\,
      I2 => mem_out(30),
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]\
    );
\app_rd_data[402]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(26),
      I1 => \my_empty_inst_rep__5_n_0\,
      I2 => mem_out(38),
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]\
    );
\app_rd_data[403]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(34),
      I1 => \my_empty_inst_rep__5_n_0\,
      I2 => mem_out(46),
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]\
    );
\app_rd_data[404]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(42),
      I1 => my_empty(4),
      I2 => mem_out(54),
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]\
    );
\app_rd_data[405]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(50),
      I1 => my_empty(4),
      I2 => mem_out(62),
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]\
    );
\app_rd_data[406]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(58),
      I1 => my_empty(4),
      I2 => mem_out(70),
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]\
    );
\app_rd_data[407]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(66),
      I1 => my_empty(4),
      I2 => mem_out(78),
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]\
    );
\app_rd_data[464]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(11),
      I1 => \my_empty_inst_rep__5_n_0\,
      I2 => mem_out(23),
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]\
    );
\app_rd_data[465]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(19),
      I1 => \my_empty_inst_rep__5_n_0\,
      I2 => mem_out(31),
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]\
    );
\app_rd_data[466]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(27),
      I1 => \my_empty_inst_rep__5_n_0\,
      I2 => mem_out(39),
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]\
    );
\app_rd_data[467]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(35),
      I1 => \my_empty_inst_rep__5_n_0\,
      I2 => mem_out(47),
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]\
    );
\app_rd_data[468]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(43),
      I1 => my_empty(4),
      I2 => mem_out(55),
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]\
    );
\app_rd_data[469]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(51),
      I1 => my_empty(4),
      I2 => mem_out(63),
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]\
    );
\app_rd_data[470]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(59),
      I1 => my_empty(4),
      I2 => mem_out(71),
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]\
    );
\app_rd_data[471]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(67),
      I1 => my_empty(4),
      I2 => mem_out(79),
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]\
    );
\app_rd_data[80]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(5),
      I1 => \my_empty_inst_rep__5_n_0\,
      I2 => mem_out(17),
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]\
    );
\app_rd_data[81]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(13),
      I1 => \my_empty_inst_rep__5_n_0\,
      I2 => mem_out(25),
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]\
    );
\app_rd_data[82]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(21),
      I1 => \my_empty_inst_rep__5_n_0\,
      I2 => mem_out(33),
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]\
    );
\app_rd_data[83]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(29),
      I1 => \my_empty_inst_rep__5_n_0\,
      I2 => mem_out(41),
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]\
    );
\app_rd_data[84]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(37),
      I1 => my_empty(4),
      I2 => mem_out(49),
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]\
    );
\app_rd_data[85]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(45),
      I1 => my_empty(4),
      I2 => mem_out(57),
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]\
    );
\app_rd_data[86]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(53),
      I1 => my_empty(4),
      I2 => mem_out(65),
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]\
    );
\app_rd_data[87]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(61),
      I1 => my_empty(4),
      I2 => mem_out(73),
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]\
    );
mem_reg_0_3_12_17: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 2) => B"000",
      ADDRA(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRB(4 downto 2) => B"000",
      ADDRB(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRC(4 downto 2) => B"000",
      ADDRC(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRD(4 downto 2) => B"000",
      ADDRD(1 downto 0) => wr_ptr(1 downto 0),
      DIA(1 downto 0) => Q(1 downto 0),
      DIB(1 downto 0) => Q(3 downto 2),
      DIC(1 downto 0) => Q(5 downto 4),
      DID(1 downto 0) => B"00",
      DOA(1) => mem_reg_0_3_12_17_n_0,
      DOA(0) => mem_reg_0_3_12_17_n_1,
      DOB(1) => mem_reg_0_3_12_17_n_2,
      DOB(0) => mem_reg_0_3_12_17_n_3,
      DOC(1 downto 0) => mem_out(17 downto 16),
      DOD(1 downto 0) => NLW_mem_reg_0_3_12_17_DOD_UNCONNECTED(1 downto 0),
      WCLK => \rd_ptr_reg[1]_0\,
      WE => wr_en
    );
\mem_reg_0_3_12_17_i_1__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0151"
    )
        port map (
      I0 => if_empty_r_0(0),
      I1 => my_full(0),
      I2 => \my_full_reg[1]_0\,
      I3 => my_empty(2),
      O => wr_en
    );
mem_reg_0_3_18_23: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 2) => B"000",
      ADDRA(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRB(4 downto 2) => B"000",
      ADDRB(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRC(4 downto 2) => B"000",
      ADDRC(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRD(4 downto 2) => B"000",
      ADDRD(1 downto 0) => wr_ptr(1 downto 0),
      DIA(1 downto 0) => Q(7 downto 6),
      DIB(1 downto 0) => Q(9 downto 8),
      DIC(1 downto 0) => Q(11 downto 10),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => mem_out(19 downto 18),
      DOB(1 downto 0) => mem_out(21 downto 20),
      DOC(1 downto 0) => mem_out(23 downto 22),
      DOD(1 downto 0) => NLW_mem_reg_0_3_18_23_DOD_UNCONNECTED(1 downto 0),
      WCLK => \rd_ptr_reg[1]_0\,
      WE => wr_en
    );
mem_reg_0_3_24_29: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 2) => B"000",
      ADDRA(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRB(4 downto 2) => B"000",
      ADDRB(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRC(4 downto 2) => B"000",
      ADDRC(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRD(4 downto 2) => B"000",
      ADDRD(1 downto 0) => wr_ptr(1 downto 0),
      DIA(1 downto 0) => Q(13 downto 12),
      DIB(1 downto 0) => Q(15 downto 14),
      DIC(1 downto 0) => Q(17 downto 16),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => mem_out(25 downto 24),
      DOB(1 downto 0) => mem_out(27 downto 26),
      DOC(1 downto 0) => mem_out(29 downto 28),
      DOD(1 downto 0) => NLW_mem_reg_0_3_24_29_DOD_UNCONNECTED(1 downto 0),
      WCLK => \rd_ptr_reg[1]_0\,
      WE => wr_en
    );
mem_reg_0_3_30_35: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 2) => B"000",
      ADDRA(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRB(4 downto 2) => B"000",
      ADDRB(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRC(4 downto 2) => B"000",
      ADDRC(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRD(4 downto 2) => B"000",
      ADDRD(1 downto 0) => wr_ptr(1 downto 0),
      DIA(1 downto 0) => Q(19 downto 18),
      DIB(1 downto 0) => Q(21 downto 20),
      DIC(1 downto 0) => Q(23 downto 22),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => mem_out(31 downto 30),
      DOB(1 downto 0) => mem_out(33 downto 32),
      DOC(1 downto 0) => mem_out(35 downto 34),
      DOD(1 downto 0) => NLW_mem_reg_0_3_30_35_DOD_UNCONNECTED(1 downto 0),
      WCLK => \rd_ptr_reg[1]_0\,
      WE => wr_en
    );
mem_reg_0_3_36_41: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 2) => B"000",
      ADDRA(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRB(4 downto 2) => B"000",
      ADDRB(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRC(4 downto 2) => B"000",
      ADDRC(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRD(4 downto 2) => B"000",
      ADDRD(1 downto 0) => wr_ptr(1 downto 0),
      DIA(1 downto 0) => Q(25 downto 24),
      DIB(1 downto 0) => Q(27 downto 26),
      DIC(1 downto 0) => Q(29 downto 28),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => mem_out(37 downto 36),
      DOB(1 downto 0) => mem_out(39 downto 38),
      DOC(1 downto 0) => mem_out(41 downto 40),
      DOD(1 downto 0) => NLW_mem_reg_0_3_36_41_DOD_UNCONNECTED(1 downto 0),
      WCLK => \rd_ptr_reg[1]_0\,
      WE => wr_en
    );
mem_reg_0_3_42_47: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 2) => B"000",
      ADDRA(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRB(4 downto 2) => B"000",
      ADDRB(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRC(4 downto 2) => B"000",
      ADDRC(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRD(4 downto 2) => B"000",
      ADDRD(1 downto 0) => wr_ptr(1 downto 0),
      DIA(1 downto 0) => Q(31 downto 30),
      DIB(1 downto 0) => Q(33 downto 32),
      DIC(1 downto 0) => Q(35 downto 34),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => mem_out(43 downto 42),
      DOB(1 downto 0) => mem_out(45 downto 44),
      DOC(1 downto 0) => mem_out(47 downto 46),
      DOD(1 downto 0) => NLW_mem_reg_0_3_42_47_DOD_UNCONNECTED(1 downto 0),
      WCLK => \rd_ptr_reg[1]_0\,
      WE => wr_en
    );
mem_reg_0_3_48_53: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 2) => B"000",
      ADDRA(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRB(4 downto 2) => B"000",
      ADDRB(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRC(4 downto 2) => B"000",
      ADDRC(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRD(4 downto 2) => B"000",
      ADDRD(1 downto 0) => wr_ptr(1 downto 0),
      DIA(1 downto 0) => Q(37 downto 36),
      DIB(1 downto 0) => Q(39 downto 38),
      DIC(1 downto 0) => Q(41 downto 40),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => mem_out(49 downto 48),
      DOB(1 downto 0) => mem_out(51 downto 50),
      DOC(1 downto 0) => mem_out(53 downto 52),
      DOD(1 downto 0) => NLW_mem_reg_0_3_48_53_DOD_UNCONNECTED(1 downto 0),
      WCLK => \rd_ptr_reg[1]_0\,
      WE => wr_en
    );
mem_reg_0_3_54_59: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 2) => B"000",
      ADDRA(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRB(4 downto 2) => B"000",
      ADDRB(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRC(4 downto 2) => B"000",
      ADDRC(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRD(4 downto 2) => B"000",
      ADDRD(1 downto 0) => wr_ptr(1 downto 0),
      DIA(1 downto 0) => Q(43 downto 42),
      DIB(1 downto 0) => Q(45 downto 44),
      DIC(1 downto 0) => Q(47 downto 46),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => mem_out(55 downto 54),
      DOB(1 downto 0) => mem_out(57 downto 56),
      DOC(1 downto 0) => mem_out(59 downto 58),
      DOD(1 downto 0) => NLW_mem_reg_0_3_54_59_DOD_UNCONNECTED(1 downto 0),
      WCLK => \rd_ptr_reg[1]_0\,
      WE => wr_en
    );
mem_reg_0_3_60_65: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 2) => B"000",
      ADDRA(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRB(4 downto 2) => B"000",
      ADDRB(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRC(4 downto 2) => B"000",
      ADDRC(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRD(4 downto 2) => B"000",
      ADDRD(1 downto 0) => wr_ptr(1 downto 0),
      DIA(1 downto 0) => Q(49 downto 48),
      DIB(1 downto 0) => Q(51 downto 50),
      DIC(1 downto 0) => Q(53 downto 52),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => mem_out(61 downto 60),
      DOB(1 downto 0) => mem_out(63 downto 62),
      DOC(1 downto 0) => mem_out(65 downto 64),
      DOD(1 downto 0) => NLW_mem_reg_0_3_60_65_DOD_UNCONNECTED(1 downto 0),
      WCLK => \rd_ptr_reg[1]_0\,
      WE => wr_en
    );
mem_reg_0_3_66_71: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 2) => B"000",
      ADDRA(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRB(4 downto 2) => B"000",
      ADDRB(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRC(4 downto 2) => B"000",
      ADDRC(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRD(4 downto 2) => B"000",
      ADDRD(1 downto 0) => wr_ptr(1 downto 0),
      DIA(1 downto 0) => Q(55 downto 54),
      DIB(1 downto 0) => Q(57 downto 56),
      DIC(1 downto 0) => Q(59 downto 58),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => mem_out(67 downto 66),
      DOB(1 downto 0) => mem_out(69 downto 68),
      DOC(1 downto 0) => mem_out(71 downto 70),
      DOD(1 downto 0) => NLW_mem_reg_0_3_66_71_DOD_UNCONNECTED(1 downto 0),
      WCLK => \rd_ptr_reg[1]_0\,
      WE => wr_en
    );
mem_reg_0_3_72_77: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 2) => B"000",
      ADDRA(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRB(4 downto 2) => B"000",
      ADDRB(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRC(4 downto 2) => B"000",
      ADDRC(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRD(4 downto 2) => B"000",
      ADDRD(1 downto 0) => wr_ptr(1 downto 0),
      DIA(1 downto 0) => Q(61 downto 60),
      DIB(1 downto 0) => Q(63 downto 62),
      DIC(1 downto 0) => Q(65 downto 64),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => mem_out(73 downto 72),
      DOB(1 downto 0) => mem_out(75 downto 74),
      DOC(1 downto 0) => mem_out(77 downto 76),
      DOD(1 downto 0) => NLW_mem_reg_0_3_72_77_DOD_UNCONNECTED(1 downto 0),
      WCLK => \rd_ptr_reg[1]_0\,
      WE => wr_en
    );
mem_reg_0_3_78_79: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 2) => B"000",
      ADDRA(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRB(4 downto 2) => B"000",
      ADDRB(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRC(4 downto 2) => B"000",
      ADDRC(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRD(4 downto 2) => B"000",
      ADDRD(1 downto 0) => wr_ptr(1 downto 0),
      DIA(1 downto 0) => Q(67 downto 66),
      DIB(1 downto 0) => B"00",
      DIC(1 downto 0) => B"00",
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => mem_out(79 downto 78),
      DOB(1 downto 0) => NLW_mem_reg_0_3_78_79_DOB_UNCONNECTED(1 downto 0),
      DOC(1 downto 0) => NLW_mem_reg_0_3_78_79_DOC_UNCONNECTED(1 downto 0),
      DOD(1 downto 0) => NLW_mem_reg_0_3_78_79_DOD_UNCONNECTED(1 downto 0),
      WCLK => \rd_ptr_reg[1]_0\,
      WE => wr_en
    );
\my_empty[4]_i_1__1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0018"
    )
        port map (
      I0 => \my_full_reg[1]_0\,
      I1 => if_empty_r_0(0),
      I2 => my_empty(1),
      I3 => my_full(1),
      O => \my_empty[4]_i_1__1_n_0\
    );
\my_empty[4]_i_2__5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00411400"
    )
        port map (
      I0 => my_empty(1),
      I1 => wr_ptr(1),
      I2 => rd_ptr(1),
      I3 => rd_ptr(0),
      I4 => wr_ptr(0),
      O => \my_empty[4]_i_2__5_n_0\
    );
\my_empty_inst__23\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \my_empty_reg[4]_rep_n_0\,
      O => my_empty(4)
    );
\my_empty_inst__24\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => my_empty(0),
      O => my_empty(3)
    );
\my_empty_inst__25\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => my_empty(0),
      O => my_empty(2)
    );
\my_empty_inst__26\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => my_empty(0),
      O => my_empty(1)
    );
\my_empty_inst_rep__5\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \my_empty_reg[4]_rep__0_n_0\,
      O => \my_empty_inst_rep__5_n_0\
    );
\my_empty_reg[4]\: unisim.vcomponents.FDSE
     port map (
      C => \rd_ptr_reg[1]_0\,
      CE => \my_empty[4]_i_1__1_n_0\,
      D => \my_empty[4]_i_2__5_n_0\,
      Q => my_empty(0),
      S => ififo_rst
    );
\my_empty_reg[4]_rep\: unisim.vcomponents.FDSE
     port map (
      C => \rd_ptr_reg[1]_0\,
      CE => \my_empty[4]_i_1__1_n_0\,
      D => \my_empty[4]_i_2__5_n_0\,
      Q => \my_empty_reg[4]_rep_n_0\,
      S => ififo_rst
    );
\my_empty_reg[4]_rep__0\: unisim.vcomponents.FDSE
     port map (
      C => \rd_ptr_reg[1]_0\,
      CE => \my_empty[4]_i_1__1_n_0\,
      D => \my_empty[4]_i_2__5_n_0\,
      Q => \my_empty_reg[4]_rep__0_n_0\,
      S => ififo_rst
    );
\my_full[0]_i_1__5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAEAABAAAA2AA8"
    )
        port map (
      I0 => my_full(0),
      I1 => \my_full_reg[1]_0\,
      I2 => if_empty_r_0(0),
      I3 => my_full(1),
      I4 => my_empty(1),
      I5 => \my_full[1]_i_2__5_n_0\,
      O => \my_full[0]_i_1__5_n_0\
    );
\my_full[1]_i_1__5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"F0F1F070"
    )
        port map (
      I0 => \my_full_reg[1]_0\,
      I1 => if_empty_r_0(0),
      I2 => my_full(1),
      I3 => my_empty(1),
      I4 => \my_full[1]_i_2__5_n_0\,
      O => \my_full[1]_i_1__5_n_0\
    );
\my_full[1]_i_2__5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00411400"
    )
        port map (
      I0 => my_full(1),
      I1 => rd_ptr(1),
      I2 => wr_ptr(1),
      I3 => wr_ptr(0),
      I4 => rd_ptr(0),
      O => \my_full[1]_i_2__5_n_0\
    );
\my_full_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \rd_ptr_reg[1]_0\,
      CE => '1',
      D => \my_full[0]_i_1__5_n_0\,
      Q => my_full(0),
      R => ififo_rst
    );
\my_full_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \rd_ptr_reg[1]_0\,
      CE => '1',
      D => \my_full[1]_i_1__5_n_0\,
      Q => my_full(1),
      R => ififo_rst
    );
phy_if_empty_r_i_4: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F888"
    )
        port map (
      I0 => if_empty_r_0(0),
      I1 => my_empty(0),
      I2 => if_empty_r(0),
      I3 => \wr_ptr[1]_i_2__2\(0),
      O => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_2\
    );
\rd_ptr[0]_i_1__5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"D2"
    )
        port map (
      I0 => \my_full_reg[1]_0\,
      I1 => my_empty(1),
      I2 => rd_ptr(0),
      O => \rd_ptr[0]_i_1__5_n_0\
    );
\rd_ptr[1]_i_1__5\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F708"
    )
        port map (
      I0 => rd_ptr(0),
      I1 => \my_full_reg[1]_0\,
      I2 => my_empty(1),
      I3 => rd_ptr(1),
      O => \rd_ptr[1]_i_1__5_n_0\
    );
\rd_ptr_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \rd_ptr_reg[1]_0\,
      CE => '1',
      D => \rd_ptr[0]_i_1__5_n_0\,
      Q => rd_ptr(0),
      R => ififo_rst
    );
\rd_ptr_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \rd_ptr_reg[1]_0\,
      CE => '1',
      D => \rd_ptr[1]_i_1__5_n_0\,
      Q => rd_ptr(1),
      R => ififo_rst
    );
\rd_ptr_timing[0]_i_1__12\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F704"
    )
        port map (
      I0 => rd_ptr(0),
      I1 => \my_full_reg[1]_0\,
      I2 => my_empty(1),
      I3 => rd_ptr_timing(0),
      O => \rd_ptr_timing[0]_i_1__12_n_0\
    );
\rd_ptr_timing[1]_i_1__12\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FF6F0060"
    )
        port map (
      I0 => rd_ptr(0),
      I1 => rd_ptr(1),
      I2 => \my_full_reg[1]_0\,
      I3 => my_empty(1),
      I4 => rd_ptr_timing(1),
      O => \rd_ptr_timing[1]_i_1__12_n_0\
    );
\rd_ptr_timing_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \rd_ptr_reg[1]_0\,
      CE => '1',
      D => \rd_ptr_timing[0]_i_1__12_n_0\,
      Q => rd_ptr_timing(0),
      R => ififo_rst
    );
\rd_ptr_timing_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \rd_ptr_reg[1]_0\,
      CE => '1',
      D => \rd_ptr_timing[1]_i_1__12_n_0\,
      Q => rd_ptr_timing(1),
      R => ififo_rst
    );
\wr_ptr[0]_i_1__12\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FECE0131"
    )
        port map (
      I0 => my_full(1),
      I1 => if_empty_r_0(0),
      I2 => \my_full_reg[1]_0\,
      I3 => my_empty(1),
      I4 => wr_ptr(0),
      O => \wr_ptr[0]_i_1__12_n_0\
    );
\wr_ptr[1]_i_1__12\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFDF5FD00020A02"
    )
        port map (
      I0 => wr_ptr(0),
      I1 => my_full(1),
      I2 => if_empty_r_0(0),
      I3 => \my_full_reg[1]_0\,
      I4 => my_empty(1),
      I5 => wr_ptr(1),
      O => \wr_ptr[1]_i_1__12_n_0\
    );
\wr_ptr[1]_i_2__6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000000001"
    )
        port map (
      I0 => \^dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0\,
      I1 => \my_full_reg[1]_1\,
      I2 => \my_full_reg[1]_2\,
      I3 => \my_full_reg[1]_3\,
      I4 => \my_full_reg[1]_4\,
      I5 => \my_full_reg[1]_5\,
      O => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1\
    );
\wr_ptr[1]_i_4__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => if_empty_r_0(0),
      I1 => my_empty(3),
      O => \^dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0\
    );
\wr_ptr[1]_i_4__2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F888"
    )
        port map (
      I0 => my_empty(3),
      I1 => if_empty_r_0(0),
      I2 => \wr_ptr[1]_i_2__2\(1),
      I3 => if_empty_r(0),
      O => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]\
    );
\wr_ptr_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \rd_ptr_reg[1]_0\,
      CE => '1',
      D => \wr_ptr[0]_i_1__12_n_0\,
      Q => wr_ptr(0),
      R => ififo_rst
    );
\wr_ptr_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \rd_ptr_reg[1]_0\,
      CE => '1',
      D => \wr_ptr[1]_i_1__12_n_0\,
      Q => wr_ptr(1),
      R => ififo_rst
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mig_mig_7series_v4_2_ddr_if_post_fifo_18 is
  port (
    \my_empty_reg[4]_0\ : out STD_LOGIC;
    \my_empty_reg[4]_1\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    \rd_mux_sel_r_reg[0]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[0]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[0]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[0]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[0]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[0]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[0]_5\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[0]_6\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[0]_7\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[0]_8\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[0]_9\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[0]_10\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[0]_11\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[0]_12\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[0]_13\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[0]_14\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[0]_15\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[0]_16\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[0]_17\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[0]_18\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[0]_19\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[0]_20\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[0]_21\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[0]_22\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[0]_23\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[0]_24\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[0]_25\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[0]_26\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[0]_27\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[0]_28\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[0]_29\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[0]_30\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[0]_31\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[0]_32\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[0]_33\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[0]_34\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[0]_35\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[0]_36\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[0]_37\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[0]_38\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[0]_39\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[0]_40\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[0]_41\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[0]_42\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[0]_43\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[0]_44\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[0]_45\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[0]_46\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[0]_47\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[0]_48\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[0]_49\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[0]_50\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[0]_51\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[0]_52\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[0]_53\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[0]_54\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[0]_55\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[0]_56\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[0]_57\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[0]_58\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[0]_59\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[0]_60\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[0]_61\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[0]_62\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]\ : out STD_LOGIC;
    ififo_rst : in STD_LOGIC;
    \rd_ptr_timing_reg[1]_0\ : in STD_LOGIC;
    \my_full_reg[1]_0\ : in STD_LOGIC;
    \my_full_reg[1]_1\ : in STD_LOGIC;
    \gen_mux_rd[0].mux_rd_rise0_r_reg[0]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \gen_mux_rd[0].mux_rd_rise0_r_reg[0]_0\ : in STD_LOGIC;
    \gen_mux_rd[0].mux_rd_rise0_r_reg[0]_1\ : in STD_LOGIC;
    \gen_mux_rd[0].mux_rd_rise0_r_reg[0]_2\ : in STD_LOGIC;
    \gen_mux_rd[1].mux_rd_rise0_r_reg[1]\ : in STD_LOGIC;
    \gen_mux_rd[1].mux_rd_rise0_r_reg[1]_0\ : in STD_LOGIC;
    \gen_mux_rd[1].mux_rd_rise0_r_reg[1]_1\ : in STD_LOGIC;
    \gen_mux_rd[2].mux_rd_rise0_r_reg[2]\ : in STD_LOGIC;
    \gen_mux_rd[2].mux_rd_rise0_r_reg[2]_0\ : in STD_LOGIC;
    \gen_mux_rd[2].mux_rd_rise0_r_reg[2]_1\ : in STD_LOGIC;
    \gen_mux_rd[3].mux_rd_rise0_r_reg[3]\ : in STD_LOGIC;
    \gen_mux_rd[3].mux_rd_rise0_r_reg[3]_0\ : in STD_LOGIC;
    \gen_mux_rd[3].mux_rd_rise0_r_reg[3]_1\ : in STD_LOGIC;
    \gen_mux_rd[4].mux_rd_rise0_r_reg[4]\ : in STD_LOGIC;
    \gen_mux_rd[4].mux_rd_rise0_r_reg[4]_0\ : in STD_LOGIC;
    \gen_mux_rd[4].mux_rd_rise0_r_reg[4]_1\ : in STD_LOGIC;
    \gen_mux_rd[5].mux_rd_rise0_r_reg[5]\ : in STD_LOGIC;
    \gen_mux_rd[5].mux_rd_rise0_r_reg[5]_0\ : in STD_LOGIC;
    \gen_mux_rd[5].mux_rd_rise0_r_reg[5]_1\ : in STD_LOGIC;
    \gen_mux_rd[6].mux_rd_rise0_r_reg[6]\ : in STD_LOGIC;
    \gen_mux_rd[6].mux_rd_rise0_r_reg[6]_0\ : in STD_LOGIC;
    \gen_mux_rd[6].mux_rd_rise0_r_reg[6]_1\ : in STD_LOGIC;
    \gen_mux_rd[7].mux_rd_rise0_r_reg[7]\ : in STD_LOGIC;
    \gen_mux_rd[7].mux_rd_rise0_r_reg[7]_0\ : in STD_LOGIC;
    \gen_mux_rd[7].mux_rd_rise0_r_reg[7]_1\ : in STD_LOGIC;
    \gen_mux_rd[0].mux_rd_fall0_r_reg[0]\ : in STD_LOGIC;
    \gen_mux_rd[0].mux_rd_fall0_r_reg[0]_0\ : in STD_LOGIC;
    \gen_mux_rd[0].mux_rd_fall0_r_reg[0]_1\ : in STD_LOGIC;
    \gen_mux_rd[1].mux_rd_fall0_r_reg[1]\ : in STD_LOGIC;
    \gen_mux_rd[1].mux_rd_fall0_r_reg[1]_0\ : in STD_LOGIC;
    \gen_mux_rd[1].mux_rd_fall0_r_reg[1]_1\ : in STD_LOGIC;
    \gen_mux_rd[2].mux_rd_fall0_r_reg[2]\ : in STD_LOGIC;
    \gen_mux_rd[2].mux_rd_fall0_r_reg[2]_0\ : in STD_LOGIC;
    \gen_mux_rd[2].mux_rd_fall0_r_reg[2]_1\ : in STD_LOGIC;
    \gen_mux_rd[3].mux_rd_fall0_r_reg[3]\ : in STD_LOGIC;
    \gen_mux_rd[3].mux_rd_fall0_r_reg[3]_0\ : in STD_LOGIC;
    \gen_mux_rd[3].mux_rd_fall0_r_reg[3]_1\ : in STD_LOGIC;
    \gen_mux_rd[4].mux_rd_fall0_r_reg[4]\ : in STD_LOGIC;
    \gen_mux_rd[4].mux_rd_fall0_r_reg[4]_0\ : in STD_LOGIC;
    \gen_mux_rd[4].mux_rd_fall0_r_reg[4]_1\ : in STD_LOGIC;
    \gen_mux_rd[5].mux_rd_fall0_r_reg[5]\ : in STD_LOGIC;
    \gen_mux_rd[5].mux_rd_fall0_r_reg[5]_0\ : in STD_LOGIC;
    \gen_mux_rd[5].mux_rd_fall0_r_reg[5]_1\ : in STD_LOGIC;
    \gen_mux_rd[6].mux_rd_fall0_r_reg[6]\ : in STD_LOGIC;
    \gen_mux_rd[6].mux_rd_fall0_r_reg[6]_0\ : in STD_LOGIC;
    \gen_mux_rd[6].mux_rd_fall0_r_reg[6]_1\ : in STD_LOGIC;
    \gen_mux_rd[7].mux_rd_fall0_r_reg[7]\ : in STD_LOGIC;
    \gen_mux_rd[7].mux_rd_fall0_r_reg[7]_0\ : in STD_LOGIC;
    \gen_mux_rd[7].mux_rd_fall0_r_reg[7]_1\ : in STD_LOGIC;
    \gen_mux_rd[0].mux_rd_rise1_r_reg[0]\ : in STD_LOGIC;
    \gen_mux_rd[0].mux_rd_rise1_r_reg[0]_0\ : in STD_LOGIC;
    \gen_mux_rd[0].mux_rd_rise1_r_reg[0]_1\ : in STD_LOGIC;
    \gen_mux_rd[1].mux_rd_rise1_r_reg[1]\ : in STD_LOGIC;
    \gen_mux_rd[1].mux_rd_rise1_r_reg[1]_0\ : in STD_LOGIC;
    \gen_mux_rd[1].mux_rd_rise1_r_reg[1]_1\ : in STD_LOGIC;
    \gen_mux_rd[2].mux_rd_rise1_r_reg[2]\ : in STD_LOGIC;
    \gen_mux_rd[2].mux_rd_rise1_r_reg[2]_0\ : in STD_LOGIC;
    \gen_mux_rd[2].mux_rd_rise1_r_reg[2]_1\ : in STD_LOGIC;
    \gen_mux_rd[3].mux_rd_rise1_r_reg[3]\ : in STD_LOGIC;
    \gen_mux_rd[3].mux_rd_rise1_r_reg[3]_0\ : in STD_LOGIC;
    \gen_mux_rd[3].mux_rd_rise1_r_reg[3]_1\ : in STD_LOGIC;
    \gen_mux_rd[4].mux_rd_rise1_r_reg[4]\ : in STD_LOGIC;
    \gen_mux_rd[4].mux_rd_rise1_r_reg[4]_0\ : in STD_LOGIC;
    \gen_mux_rd[4].mux_rd_rise1_r_reg[4]_1\ : in STD_LOGIC;
    \gen_mux_rd[5].mux_rd_rise1_r_reg[5]\ : in STD_LOGIC;
    \gen_mux_rd[5].mux_rd_rise1_r_reg[5]_0\ : in STD_LOGIC;
    \gen_mux_rd[5].mux_rd_rise1_r_reg[5]_1\ : in STD_LOGIC;
    \gen_mux_rd[6].mux_rd_rise1_r_reg[6]\ : in STD_LOGIC;
    \gen_mux_rd[6].mux_rd_rise1_r_reg[6]_0\ : in STD_LOGIC;
    \gen_mux_rd[6].mux_rd_rise1_r_reg[6]_1\ : in STD_LOGIC;
    \gen_mux_rd[7].mux_rd_rise1_r_reg[7]\ : in STD_LOGIC;
    \gen_mux_rd[7].mux_rd_rise1_r_reg[7]_0\ : in STD_LOGIC;
    \gen_mux_rd[7].mux_rd_rise1_r_reg[7]_1\ : in STD_LOGIC;
    \gen_mux_rd[0].mux_rd_fall1_r_reg[0]\ : in STD_LOGIC;
    \gen_mux_rd[0].mux_rd_fall1_r_reg[0]_0\ : in STD_LOGIC;
    \gen_mux_rd[0].mux_rd_fall1_r_reg[0]_1\ : in STD_LOGIC;
    \gen_mux_rd[1].mux_rd_fall1_r_reg[1]\ : in STD_LOGIC;
    \gen_mux_rd[1].mux_rd_fall1_r_reg[1]_0\ : in STD_LOGIC;
    \gen_mux_rd[1].mux_rd_fall1_r_reg[1]_1\ : in STD_LOGIC;
    \gen_mux_rd[2].mux_rd_fall1_r_reg[2]\ : in STD_LOGIC;
    \gen_mux_rd[2].mux_rd_fall1_r_reg[2]_0\ : in STD_LOGIC;
    \gen_mux_rd[2].mux_rd_fall1_r_reg[2]_1\ : in STD_LOGIC;
    \gen_mux_rd[3].mux_rd_fall1_r_reg[3]\ : in STD_LOGIC;
    \gen_mux_rd[3].mux_rd_fall1_r_reg[3]_0\ : in STD_LOGIC;
    \gen_mux_rd[3].mux_rd_fall1_r_reg[3]_1\ : in STD_LOGIC;
    \gen_mux_rd[4].mux_rd_fall1_r_reg[4]\ : in STD_LOGIC;
    \gen_mux_rd[4].mux_rd_fall1_r_reg[4]_0\ : in STD_LOGIC;
    \gen_mux_rd[4].mux_rd_fall1_r_reg[4]_1\ : in STD_LOGIC;
    \gen_mux_rd[5].mux_rd_fall1_r_reg[5]\ : in STD_LOGIC;
    \gen_mux_rd[5].mux_rd_fall1_r_reg[5]_0\ : in STD_LOGIC;
    \gen_mux_rd[5].mux_rd_fall1_r_reg[5]_1\ : in STD_LOGIC;
    \gen_mux_rd[6].mux_rd_fall1_r_reg[6]\ : in STD_LOGIC;
    \gen_mux_rd[6].mux_rd_fall1_r_reg[6]_0\ : in STD_LOGIC;
    \gen_mux_rd[6].mux_rd_fall1_r_reg[6]_1\ : in STD_LOGIC;
    \gen_mux_rd[7].mux_rd_fall1_r_reg[7]\ : in STD_LOGIC;
    \gen_mux_rd[7].mux_rd_fall1_r_reg[7]_0\ : in STD_LOGIC;
    \gen_mux_rd[7].mux_rd_fall1_r_reg[7]_1\ : in STD_LOGIC;
    \gen_mux_rd[0].mux_rd_rise2_r_reg[0]\ : in STD_LOGIC;
    \gen_mux_rd[0].mux_rd_rise2_r_reg[0]_0\ : in STD_LOGIC;
    \gen_mux_rd[0].mux_rd_rise2_r_reg[0]_1\ : in STD_LOGIC;
    \gen_mux_rd[1].mux_rd_rise2_r_reg[1]\ : in STD_LOGIC;
    \gen_mux_rd[1].mux_rd_rise2_r_reg[1]_0\ : in STD_LOGIC;
    \gen_mux_rd[1].mux_rd_rise2_r_reg[1]_1\ : in STD_LOGIC;
    \gen_mux_rd[2].mux_rd_rise2_r_reg[2]\ : in STD_LOGIC;
    \gen_mux_rd[2].mux_rd_rise2_r_reg[2]_0\ : in STD_LOGIC;
    \gen_mux_rd[2].mux_rd_rise2_r_reg[2]_1\ : in STD_LOGIC;
    \gen_mux_rd[3].mux_rd_rise2_r_reg[3]\ : in STD_LOGIC;
    \gen_mux_rd[3].mux_rd_rise2_r_reg[3]_0\ : in STD_LOGIC;
    \gen_mux_rd[3].mux_rd_rise2_r_reg[3]_1\ : in STD_LOGIC;
    \gen_mux_rd[4].mux_rd_rise2_r_reg[4]\ : in STD_LOGIC;
    \gen_mux_rd[4].mux_rd_rise2_r_reg[4]_0\ : in STD_LOGIC;
    \gen_mux_rd[4].mux_rd_rise2_r_reg[4]_1\ : in STD_LOGIC;
    \gen_mux_rd[5].mux_rd_rise2_r_reg[5]\ : in STD_LOGIC;
    \gen_mux_rd[5].mux_rd_rise2_r_reg[5]_0\ : in STD_LOGIC;
    \gen_mux_rd[5].mux_rd_rise2_r_reg[5]_1\ : in STD_LOGIC;
    \gen_mux_rd[6].mux_rd_rise2_r_reg[6]\ : in STD_LOGIC;
    \gen_mux_rd[6].mux_rd_rise2_r_reg[6]_0\ : in STD_LOGIC;
    \gen_mux_rd[6].mux_rd_rise2_r_reg[6]_1\ : in STD_LOGIC;
    \gen_mux_rd[7].mux_rd_rise2_r_reg[7]\ : in STD_LOGIC;
    \gen_mux_rd[7].mux_rd_rise2_r_reg[7]_0\ : in STD_LOGIC;
    \gen_mux_rd[7].mux_rd_rise2_r_reg[7]_1\ : in STD_LOGIC;
    \gen_mux_rd[0].mux_rd_fall2_r_reg[0]\ : in STD_LOGIC;
    \gen_mux_rd[0].mux_rd_fall2_r_reg[0]_0\ : in STD_LOGIC;
    \gen_mux_rd[0].mux_rd_fall2_r_reg[0]_1\ : in STD_LOGIC;
    \gen_mux_rd[1].mux_rd_fall2_r_reg[1]\ : in STD_LOGIC;
    \gen_mux_rd[1].mux_rd_fall2_r_reg[1]_0\ : in STD_LOGIC;
    \gen_mux_rd[1].mux_rd_fall2_r_reg[1]_1\ : in STD_LOGIC;
    \gen_mux_rd[2].mux_rd_fall2_r_reg[2]\ : in STD_LOGIC;
    \gen_mux_rd[2].mux_rd_fall2_r_reg[2]_0\ : in STD_LOGIC;
    \gen_mux_rd[2].mux_rd_fall2_r_reg[2]_1\ : in STD_LOGIC;
    \gen_mux_rd[3].mux_rd_fall2_r_reg[3]\ : in STD_LOGIC;
    \gen_mux_rd[3].mux_rd_fall2_r_reg[3]_0\ : in STD_LOGIC;
    \gen_mux_rd[3].mux_rd_fall2_r_reg[3]_1\ : in STD_LOGIC;
    \gen_mux_rd[4].mux_rd_fall2_r_reg[4]\ : in STD_LOGIC;
    \gen_mux_rd[4].mux_rd_fall2_r_reg[4]_0\ : in STD_LOGIC;
    \gen_mux_rd[4].mux_rd_fall2_r_reg[4]_1\ : in STD_LOGIC;
    \gen_mux_rd[5].mux_rd_fall2_r_reg[5]\ : in STD_LOGIC;
    \gen_mux_rd[5].mux_rd_fall2_r_reg[5]_0\ : in STD_LOGIC;
    \gen_mux_rd[5].mux_rd_fall2_r_reg[5]_1\ : in STD_LOGIC;
    \gen_mux_rd[6].mux_rd_fall2_r_reg[6]\ : in STD_LOGIC;
    \gen_mux_rd[6].mux_rd_fall2_r_reg[6]_0\ : in STD_LOGIC;
    \gen_mux_rd[6].mux_rd_fall2_r_reg[6]_1\ : in STD_LOGIC;
    \gen_mux_rd[7].mux_rd_fall2_r_reg[7]\ : in STD_LOGIC;
    \gen_mux_rd[7].mux_rd_fall2_r_reg[7]_0\ : in STD_LOGIC;
    \gen_mux_rd[7].mux_rd_fall2_r_reg[7]_1\ : in STD_LOGIC;
    \gen_mux_rd[0].mux_rd_rise3_r_reg[0]\ : in STD_LOGIC;
    \gen_mux_rd[0].mux_rd_rise3_r_reg[0]_0\ : in STD_LOGIC;
    \gen_mux_rd[0].mux_rd_rise3_r_reg[0]_1\ : in STD_LOGIC;
    \gen_mux_rd[1].mux_rd_rise3_r_reg[1]\ : in STD_LOGIC;
    \gen_mux_rd[1].mux_rd_rise3_r_reg[1]_0\ : in STD_LOGIC;
    \gen_mux_rd[1].mux_rd_rise3_r_reg[1]_1\ : in STD_LOGIC;
    \gen_mux_rd[2].mux_rd_rise3_r_reg[2]\ : in STD_LOGIC;
    \gen_mux_rd[2].mux_rd_rise3_r_reg[2]_0\ : in STD_LOGIC;
    \gen_mux_rd[2].mux_rd_rise3_r_reg[2]_1\ : in STD_LOGIC;
    \gen_mux_rd[3].mux_rd_rise3_r_reg[3]\ : in STD_LOGIC;
    \gen_mux_rd[3].mux_rd_rise3_r_reg[3]_0\ : in STD_LOGIC;
    \gen_mux_rd[3].mux_rd_rise3_r_reg[3]_1\ : in STD_LOGIC;
    \gen_mux_rd[4].mux_rd_rise3_r_reg[4]\ : in STD_LOGIC;
    \gen_mux_rd[4].mux_rd_rise3_r_reg[4]_0\ : in STD_LOGIC;
    \gen_mux_rd[4].mux_rd_rise3_r_reg[4]_1\ : in STD_LOGIC;
    \gen_mux_rd[5].mux_rd_rise3_r_reg[5]\ : in STD_LOGIC;
    \gen_mux_rd[5].mux_rd_rise3_r_reg[5]_0\ : in STD_LOGIC;
    \gen_mux_rd[5].mux_rd_rise3_r_reg[5]_1\ : in STD_LOGIC;
    \gen_mux_rd[6].mux_rd_rise3_r_reg[6]\ : in STD_LOGIC;
    \gen_mux_rd[6].mux_rd_rise3_r_reg[6]_0\ : in STD_LOGIC;
    \gen_mux_rd[6].mux_rd_rise3_r_reg[6]_1\ : in STD_LOGIC;
    \gen_mux_rd[7].mux_rd_rise3_r_reg[7]\ : in STD_LOGIC;
    \gen_mux_rd[7].mux_rd_rise3_r_reg[7]_0\ : in STD_LOGIC;
    \gen_mux_rd[7].mux_rd_rise3_r_reg[7]_1\ : in STD_LOGIC;
    \gen_mux_rd[0].mux_rd_fall3_r_reg[0]\ : in STD_LOGIC;
    \gen_mux_rd[0].mux_rd_fall3_r_reg[0]_0\ : in STD_LOGIC;
    \gen_mux_rd[0].mux_rd_fall3_r_reg[0]_1\ : in STD_LOGIC;
    \gen_mux_rd[1].mux_rd_fall3_r_reg[1]\ : in STD_LOGIC;
    \gen_mux_rd[1].mux_rd_fall3_r_reg[1]_0\ : in STD_LOGIC;
    \gen_mux_rd[1].mux_rd_fall3_r_reg[1]_1\ : in STD_LOGIC;
    \gen_mux_rd[2].mux_rd_fall3_r_reg[2]\ : in STD_LOGIC;
    \gen_mux_rd[2].mux_rd_fall3_r_reg[2]_0\ : in STD_LOGIC;
    \gen_mux_rd[2].mux_rd_fall3_r_reg[2]_1\ : in STD_LOGIC;
    \gen_mux_rd[3].mux_rd_fall3_r_reg[3]\ : in STD_LOGIC;
    \gen_mux_rd[3].mux_rd_fall3_r_reg[3]_0\ : in STD_LOGIC;
    \gen_mux_rd[3].mux_rd_fall3_r_reg[3]_1\ : in STD_LOGIC;
    \gen_mux_rd[4].mux_rd_fall3_r_reg[4]\ : in STD_LOGIC;
    \gen_mux_rd[4].mux_rd_fall3_r_reg[4]_0\ : in STD_LOGIC;
    \gen_mux_rd[4].mux_rd_fall3_r_reg[4]_1\ : in STD_LOGIC;
    \gen_mux_rd[5].mux_rd_fall3_r_reg[5]\ : in STD_LOGIC;
    \gen_mux_rd[5].mux_rd_fall3_r_reg[5]_0\ : in STD_LOGIC;
    \gen_mux_rd[5].mux_rd_fall3_r_reg[5]_1\ : in STD_LOGIC;
    \gen_mux_rd[6].mux_rd_fall3_r_reg[6]\ : in STD_LOGIC;
    \gen_mux_rd[6].mux_rd_fall3_r_reg[6]_0\ : in STD_LOGIC;
    \gen_mux_rd[6].mux_rd_fall3_r_reg[6]_1\ : in STD_LOGIC;
    \gen_mux_rd[7].mux_rd_fall3_r_reg[7]\ : in STD_LOGIC;
    \gen_mux_rd[7].mux_rd_fall3_r_reg[7]_0\ : in STD_LOGIC;
    \gen_mux_rd[7].mux_rd_fall3_r_reg[7]_1\ : in STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 67 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of mig_mig_7series_v4_2_ddr_if_post_fifo_18 : entity is "mig_7series_v4_2_ddr_if_post_fifo";
end mig_mig_7series_v4_2_ddr_if_post_fifo_18;

architecture STRUCTURE of mig_mig_7series_v4_2_ddr_if_post_fifo_18 is
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]\ : STD_LOGIC;
  signal mem_out : STD_LOGIC_VECTOR ( 79 downto 16 );
  signal mem_reg_0_3_12_17_n_0 : STD_LOGIC;
  signal mem_reg_0_3_12_17_n_1 : STD_LOGIC;
  signal mem_reg_0_3_12_17_n_2 : STD_LOGIC;
  signal mem_reg_0_3_12_17_n_3 : STD_LOGIC;
  signal my_empty : STD_LOGIC_VECTOR ( 4 downto 1 );
  signal \my_empty[4]_i_1__0_n_0\ : STD_LOGIC;
  signal \my_empty[4]_i_2__4_n_0\ : STD_LOGIC;
  signal \my_empty_inst_rep__4_n_0\ : STD_LOGIC;
  signal \^my_empty_reg[4]_0\ : STD_LOGIC;
  signal \^my_empty_reg[4]_1\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \my_empty_reg[4]_rep__0_n_0\ : STD_LOGIC;
  signal \my_empty_reg[4]_rep_n_0\ : STD_LOGIC;
  signal my_full : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \my_full[0]_i_1__4_n_0\ : STD_LOGIC;
  signal \my_full[1]_i_1__4_n_0\ : STD_LOGIC;
  signal \my_full[1]_i_2__4_n_0\ : STD_LOGIC;
  signal rd_ptr : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \rd_ptr[0]_i_1__4_n_0\ : STD_LOGIC;
  signal \rd_ptr[1]_i_1__4_n_0\ : STD_LOGIC;
  signal rd_ptr_timing : STD_LOGIC_VECTOR ( 1 downto 0 );
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of rd_ptr_timing : signal is "true";
  attribute syn_maxfan : string;
  attribute syn_maxfan of rd_ptr_timing : signal is "10";
  signal \rd_ptr_timing[0]_i_1__10_n_0\ : STD_LOGIC;
  signal \rd_ptr_timing[1]_i_1__10_n_0\ : STD_LOGIC;
  signal wr_en : STD_LOGIC;
  attribute MAX_FANOUT : string;
  attribute MAX_FANOUT of wr_en : signal is "40";
  attribute RTL_MAX_FANOUT : string;
  attribute RTL_MAX_FANOUT of wr_en : signal is "found";
  attribute syn_maxfan of wr_en : signal is "10";
  signal wr_ptr : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \wr_ptr[0]_i_1__10_n_0\ : STD_LOGIC;
  signal \wr_ptr[1]_i_1__10_n_0\ : STD_LOGIC;
  signal NLW_mem_reg_0_3_12_17_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_3_18_23_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_3_24_29_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_3_30_35_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_3_36_41_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_3_42_47_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_3_48_53_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_3_54_59_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_3_60_65_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_3_66_71_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_3_72_77_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_3_78_79_DOB_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_3_78_79_DOC_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_3_78_79_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \app_rd_data[10]_INST_0\ : label is "soft_lutpair994";
  attribute SOFT_HLUTNM of \app_rd_data[11]_INST_0\ : label is "soft_lutpair1003";
  attribute SOFT_HLUTNM of \app_rd_data[12]_INST_0\ : label is "soft_lutpair991";
  attribute SOFT_HLUTNM of \app_rd_data[136]_INST_0\ : label is "soft_lutpair1000";
  attribute SOFT_HLUTNM of \app_rd_data[137]_INST_0\ : label is "soft_lutpair995";
  attribute SOFT_HLUTNM of \app_rd_data[138]_INST_0\ : label is "soft_lutpair1003";
  attribute SOFT_HLUTNM of \app_rd_data[139]_INST_0\ : label is "soft_lutpair998";
  attribute SOFT_HLUTNM of \app_rd_data[13]_INST_0\ : label is "soft_lutpair990";
  attribute SOFT_HLUTNM of \app_rd_data[140]_INST_0\ : label is "soft_lutpair993";
  attribute SOFT_HLUTNM of \app_rd_data[141]_INST_0\ : label is "soft_lutpair1002";
  attribute SOFT_HLUTNM of \app_rd_data[142]_INST_0\ : label is "soft_lutpair996";
  attribute SOFT_HLUTNM of \app_rd_data[143]_INST_0\ : label is "soft_lutpair992";
  attribute SOFT_HLUTNM of \app_rd_data[14]_INST_0\ : label is "soft_lutpair991";
  attribute SOFT_HLUTNM of \app_rd_data[15]_INST_0\ : label is "soft_lutpair990";
  attribute SOFT_HLUTNM of \app_rd_data[200]_INST_0\ : label is "soft_lutpair1020";
  attribute SOFT_HLUTNM of \app_rd_data[201]_INST_0\ : label is "soft_lutpair1009";
  attribute SOFT_HLUTNM of \app_rd_data[202]_INST_0\ : label is "soft_lutpair1018";
  attribute SOFT_HLUTNM of \app_rd_data[203]_INST_0\ : label is "soft_lutpair1015";
  attribute SOFT_HLUTNM of \app_rd_data[204]_INST_0\ : label is "soft_lutpair1007";
  attribute SOFT_HLUTNM of \app_rd_data[205]_INST_0\ : label is "soft_lutpair1014";
  attribute SOFT_HLUTNM of \app_rd_data[206]_INST_0\ : label is "soft_lutpair1013";
  attribute SOFT_HLUTNM of \app_rd_data[207]_INST_0\ : label is "soft_lutpair1004";
  attribute SOFT_HLUTNM of \app_rd_data[264]_INST_0\ : label is "soft_lutpair995";
  attribute SOFT_HLUTNM of \app_rd_data[265]_INST_0\ : label is "soft_lutpair989";
  attribute SOFT_HLUTNM of \app_rd_data[266]_INST_0\ : label is "soft_lutpair998";
  attribute SOFT_HLUTNM of \app_rd_data[267]_INST_0\ : label is "soft_lutpair989";
  attribute SOFT_HLUTNM of \app_rd_data[268]_INST_0\ : label is "soft_lutpair1002";
  attribute SOFT_HLUTNM of \app_rd_data[269]_INST_0\ : label is "soft_lutpair997";
  attribute SOFT_HLUTNM of \app_rd_data[270]_INST_0\ : label is "soft_lutpair992";
  attribute SOFT_HLUTNM of \app_rd_data[271]_INST_0\ : label is "soft_lutpair1001";
  attribute SOFT_HLUTNM of \app_rd_data[328]_INST_0\ : label is "soft_lutpair1010";
  attribute SOFT_HLUTNM of \app_rd_data[329]_INST_0\ : label is "soft_lutpair1018";
  attribute SOFT_HLUTNM of \app_rd_data[330]_INST_0\ : label is "soft_lutpair1017";
  attribute SOFT_HLUTNM of \app_rd_data[331]_INST_0\ : label is "soft_lutpair1008";
  attribute SOFT_HLUTNM of \app_rd_data[332]_INST_0\ : label is "soft_lutpair1016";
  attribute SOFT_HLUTNM of \app_rd_data[333]_INST_0\ : label is "soft_lutpair1006";
  attribute SOFT_HLUTNM of \app_rd_data[334]_INST_0\ : label is "soft_lutpair1004";
  attribute SOFT_HLUTNM of \app_rd_data[335]_INST_0\ : label is "soft_lutpair1011";
  attribute SOFT_HLUTNM of \app_rd_data[392]_INST_0\ : label is "soft_lutpair1005";
  attribute SOFT_HLUTNM of \app_rd_data[393]_INST_0\ : label is "soft_lutpair999";
  attribute SOFT_HLUTNM of \app_rd_data[394]_INST_0\ : label is "soft_lutpair994";
  attribute SOFT_HLUTNM of \app_rd_data[395]_INST_0\ : label is "soft_lutpair1000";
  attribute SOFT_HLUTNM of \app_rd_data[396]_INST_0\ : label is "soft_lutpair997";
  attribute SOFT_HLUTNM of \app_rd_data[397]_INST_0\ : label is "soft_lutpair993";
  attribute SOFT_HLUTNM of \app_rd_data[398]_INST_0\ : label is "soft_lutpair1001";
  attribute SOFT_HLUTNM of \app_rd_data[399]_INST_0\ : label is "soft_lutpair996";
  attribute SOFT_HLUTNM of \app_rd_data[456]_INST_0\ : label is "soft_lutpair1020";
  attribute SOFT_HLUTNM of \app_rd_data[457]_INST_0\ : label is "soft_lutpair1015";
  attribute SOFT_HLUTNM of \app_rd_data[458]_INST_0\ : label is "soft_lutpair1008";
  attribute SOFT_HLUTNM of \app_rd_data[459]_INST_0\ : label is "soft_lutpair1010";
  attribute SOFT_HLUTNM of \app_rd_data[460]_INST_0\ : label is "soft_lutpair1014";
  attribute SOFT_HLUTNM of \app_rd_data[461]_INST_0\ : label is "soft_lutpair1006";
  attribute SOFT_HLUTNM of \app_rd_data[462]_INST_0\ : label is "soft_lutpair1012";
  attribute SOFT_HLUTNM of \app_rd_data[463]_INST_0\ : label is "soft_lutpair1011";
  attribute SOFT_HLUTNM of \app_rd_data[72]_INST_0\ : label is "soft_lutpair1019";
  attribute SOFT_HLUTNM of \app_rd_data[73]_INST_0\ : label is "soft_lutpair1019";
  attribute SOFT_HLUTNM of \app_rd_data[74]_INST_0\ : label is "soft_lutpair1009";
  attribute SOFT_HLUTNM of \app_rd_data[75]_INST_0\ : label is "soft_lutpair1017";
  attribute SOFT_HLUTNM of \app_rd_data[76]_INST_0\ : label is "soft_lutpair1016";
  attribute SOFT_HLUTNM of \app_rd_data[77]_INST_0\ : label is "soft_lutpair1007";
  attribute SOFT_HLUTNM of \app_rd_data[78]_INST_0\ : label is "soft_lutpair1013";
  attribute SOFT_HLUTNM of \app_rd_data[79]_INST_0\ : label is "soft_lutpair1012";
  attribute SOFT_HLUTNM of \app_rd_data[8]_INST_0\ : label is "soft_lutpair1005";
  attribute SOFT_HLUTNM of \app_rd_data[9]_INST_0\ : label is "soft_lutpair999";
  attribute METHODOLOGY_DRC_VIOS : string;
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_3_12_17 : label is "";
  attribute RTL_RAM_BITS : integer;
  attribute RTL_RAM_BITS of mem_reg_0_3_12_17 : label is 320;
  attribute RTL_RAM_NAME : string;
  attribute RTL_RAM_NAME of mem_reg_0_3_12_17 : label is "dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem";
  attribute ram_addr_begin : integer;
  attribute ram_addr_begin of mem_reg_0_3_12_17 : label is 0;
  attribute ram_addr_end : integer;
  attribute ram_addr_end of mem_reg_0_3_12_17 : label is 3;
  attribute ram_offset : integer;
  attribute ram_offset of mem_reg_0_3_12_17 : label is 0;
  attribute ram_slice_begin : integer;
  attribute ram_slice_begin of mem_reg_0_3_12_17 : label is 12;
  attribute ram_slice_end : integer;
  attribute ram_slice_end of mem_reg_0_3_12_17 : label is 17;
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_3_18_23 : label is "";
  attribute RTL_RAM_BITS of mem_reg_0_3_18_23 : label is 320;
  attribute RTL_RAM_NAME of mem_reg_0_3_18_23 : label is "dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem";
  attribute ram_addr_begin of mem_reg_0_3_18_23 : label is 0;
  attribute ram_addr_end of mem_reg_0_3_18_23 : label is 3;
  attribute ram_offset of mem_reg_0_3_18_23 : label is 0;
  attribute ram_slice_begin of mem_reg_0_3_18_23 : label is 18;
  attribute ram_slice_end of mem_reg_0_3_18_23 : label is 23;
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_3_24_29 : label is "";
  attribute RTL_RAM_BITS of mem_reg_0_3_24_29 : label is 320;
  attribute RTL_RAM_NAME of mem_reg_0_3_24_29 : label is "dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem";
  attribute ram_addr_begin of mem_reg_0_3_24_29 : label is 0;
  attribute ram_addr_end of mem_reg_0_3_24_29 : label is 3;
  attribute ram_offset of mem_reg_0_3_24_29 : label is 0;
  attribute ram_slice_begin of mem_reg_0_3_24_29 : label is 24;
  attribute ram_slice_end of mem_reg_0_3_24_29 : label is 29;
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_3_30_35 : label is "";
  attribute RTL_RAM_BITS of mem_reg_0_3_30_35 : label is 320;
  attribute RTL_RAM_NAME of mem_reg_0_3_30_35 : label is "dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem";
  attribute ram_addr_begin of mem_reg_0_3_30_35 : label is 0;
  attribute ram_addr_end of mem_reg_0_3_30_35 : label is 3;
  attribute ram_offset of mem_reg_0_3_30_35 : label is 0;
  attribute ram_slice_begin of mem_reg_0_3_30_35 : label is 30;
  attribute ram_slice_end of mem_reg_0_3_30_35 : label is 35;
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_3_36_41 : label is "";
  attribute RTL_RAM_BITS of mem_reg_0_3_36_41 : label is 320;
  attribute RTL_RAM_NAME of mem_reg_0_3_36_41 : label is "dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem";
  attribute ram_addr_begin of mem_reg_0_3_36_41 : label is 0;
  attribute ram_addr_end of mem_reg_0_3_36_41 : label is 3;
  attribute ram_offset of mem_reg_0_3_36_41 : label is 0;
  attribute ram_slice_begin of mem_reg_0_3_36_41 : label is 36;
  attribute ram_slice_end of mem_reg_0_3_36_41 : label is 41;
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_3_42_47 : label is "";
  attribute RTL_RAM_BITS of mem_reg_0_3_42_47 : label is 320;
  attribute RTL_RAM_NAME of mem_reg_0_3_42_47 : label is "dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem";
  attribute ram_addr_begin of mem_reg_0_3_42_47 : label is 0;
  attribute ram_addr_end of mem_reg_0_3_42_47 : label is 3;
  attribute ram_offset of mem_reg_0_3_42_47 : label is 0;
  attribute ram_slice_begin of mem_reg_0_3_42_47 : label is 42;
  attribute ram_slice_end of mem_reg_0_3_42_47 : label is 47;
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_3_48_53 : label is "";
  attribute RTL_RAM_BITS of mem_reg_0_3_48_53 : label is 320;
  attribute RTL_RAM_NAME of mem_reg_0_3_48_53 : label is "dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem";
  attribute ram_addr_begin of mem_reg_0_3_48_53 : label is 0;
  attribute ram_addr_end of mem_reg_0_3_48_53 : label is 3;
  attribute ram_offset of mem_reg_0_3_48_53 : label is 0;
  attribute ram_slice_begin of mem_reg_0_3_48_53 : label is 48;
  attribute ram_slice_end of mem_reg_0_3_48_53 : label is 53;
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_3_54_59 : label is "";
  attribute RTL_RAM_BITS of mem_reg_0_3_54_59 : label is 320;
  attribute RTL_RAM_NAME of mem_reg_0_3_54_59 : label is "dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem";
  attribute ram_addr_begin of mem_reg_0_3_54_59 : label is 0;
  attribute ram_addr_end of mem_reg_0_3_54_59 : label is 3;
  attribute ram_offset of mem_reg_0_3_54_59 : label is 0;
  attribute ram_slice_begin of mem_reg_0_3_54_59 : label is 54;
  attribute ram_slice_end of mem_reg_0_3_54_59 : label is 59;
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_3_60_65 : label is "";
  attribute RTL_RAM_BITS of mem_reg_0_3_60_65 : label is 320;
  attribute RTL_RAM_NAME of mem_reg_0_3_60_65 : label is "dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem";
  attribute ram_addr_begin of mem_reg_0_3_60_65 : label is 0;
  attribute ram_addr_end of mem_reg_0_3_60_65 : label is 3;
  attribute ram_offset of mem_reg_0_3_60_65 : label is 0;
  attribute ram_slice_begin of mem_reg_0_3_60_65 : label is 60;
  attribute ram_slice_end of mem_reg_0_3_60_65 : label is 65;
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_3_66_71 : label is "";
  attribute RTL_RAM_BITS of mem_reg_0_3_66_71 : label is 320;
  attribute RTL_RAM_NAME of mem_reg_0_3_66_71 : label is "dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem";
  attribute ram_addr_begin of mem_reg_0_3_66_71 : label is 0;
  attribute ram_addr_end of mem_reg_0_3_66_71 : label is 3;
  attribute ram_offset of mem_reg_0_3_66_71 : label is 0;
  attribute ram_slice_begin of mem_reg_0_3_66_71 : label is 66;
  attribute ram_slice_end of mem_reg_0_3_66_71 : label is 71;
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_3_72_77 : label is "";
  attribute RTL_RAM_BITS of mem_reg_0_3_72_77 : label is 320;
  attribute RTL_RAM_NAME of mem_reg_0_3_72_77 : label is "dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem";
  attribute ram_addr_begin of mem_reg_0_3_72_77 : label is 0;
  attribute ram_addr_end of mem_reg_0_3_72_77 : label is 3;
  attribute ram_offset of mem_reg_0_3_72_77 : label is 0;
  attribute ram_slice_begin of mem_reg_0_3_72_77 : label is 72;
  attribute ram_slice_end of mem_reg_0_3_72_77 : label is 77;
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_3_78_79 : label is "";
  attribute RTL_RAM_BITS of mem_reg_0_3_78_79 : label is 320;
  attribute RTL_RAM_NAME of mem_reg_0_3_78_79 : label is "dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem";
  attribute ram_addr_begin of mem_reg_0_3_78_79 : label is 0;
  attribute ram_addr_end of mem_reg_0_3_78_79 : label is 3;
  attribute ram_offset of mem_reg_0_3_78_79 : label is 0;
  attribute ram_slice_begin of mem_reg_0_3_78_79 : label is 78;
  attribute ram_slice_end of mem_reg_0_3_78_79 : label is 79;
  attribute SOFT_HLUTNM of \my_empty_inst__20\ : label is "soft_lutpair1021";
  attribute SOFT_HLUTNM of \my_empty_inst__21\ : label is "soft_lutpair1021";
  attribute IS_FANOUT_CONSTRAINED : integer;
  attribute IS_FANOUT_CONSTRAINED of \my_empty_inst_rep__4\ : label is 1;
  attribute ORIG_CELL_NAME : string;
  attribute ORIG_CELL_NAME of \my_empty_reg[4]\ : label is "my_empty_reg[4]";
  attribute ORIG_CELL_NAME of \my_empty_reg[4]_rep\ : label is "my_empty_reg[4]";
  attribute ORIG_CELL_NAME of \my_empty_reg[4]_rep__0\ : label is "my_empty_reg[4]";
  attribute SOFT_HLUTNM of \rd_ptr[0]_i_1__4\ : label is "soft_lutpair988";
  attribute SOFT_HLUTNM of \rd_ptr[1]_i_1__4\ : label is "soft_lutpair988";
  attribute syn_maxfan of \rd_ptr_reg[0]\ : label is "10";
  attribute syn_maxfan of \rd_ptr_reg[1]\ : label is "10";
  attribute KEEP : string;
  attribute KEEP of \rd_ptr_timing_reg[0]\ : label is "yes";
  attribute syn_maxfan of \rd_ptr_timing_reg[0]\ : label is "10";
  attribute KEEP of \rd_ptr_timing_reg[1]\ : label is "yes";
  attribute syn_maxfan of \rd_ptr_timing_reg[1]\ : label is "10";
  attribute syn_maxfan of \wr_ptr_reg[0]\ : label is "10";
  attribute syn_maxfan of \wr_ptr_reg[1]\ : label is "10";
begin
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]\;
  \my_empty_reg[4]_0\ <= \^my_empty_reg[4]_0\;
  \my_empty_reg[4]_1\(0) <= \^my_empty_reg[4]_1\(0);
\app_rd_data[10]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(20),
      I1 => \my_empty_inst_rep__4_n_0\,
      I2 => mem_out(32),
      O => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]\
    );
\app_rd_data[11]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(28),
      I1 => \my_empty_inst_rep__4_n_0\,
      I2 => mem_out(40),
      O => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]\
    );
\app_rd_data[12]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(36),
      I1 => my_empty(4),
      I2 => mem_out(48),
      O => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]\
    );
\app_rd_data[136]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(6),
      I1 => \my_empty_inst_rep__4_n_0\,
      I2 => mem_out(18),
      O => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]\
    );
\app_rd_data[137]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(14),
      I1 => \my_empty_inst_rep__4_n_0\,
      I2 => mem_out(26),
      O => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]\
    );
\app_rd_data[138]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(22),
      I1 => \my_empty_inst_rep__4_n_0\,
      I2 => mem_out(34),
      O => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]\
    );
\app_rd_data[139]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(30),
      I1 => \my_empty_inst_rep__4_n_0\,
      I2 => mem_out(42),
      O => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]\
    );
\app_rd_data[13]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(44),
      I1 => my_empty(4),
      I2 => mem_out(56),
      O => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]\
    );
\app_rd_data[140]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(38),
      I1 => my_empty(4),
      I2 => mem_out(50),
      O => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]\
    );
\app_rd_data[141]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(46),
      I1 => my_empty(4),
      I2 => mem_out(58),
      O => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]\
    );
\app_rd_data[142]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(54),
      I1 => my_empty(4),
      I2 => mem_out(66),
      O => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]\
    );
\app_rd_data[143]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(62),
      I1 => my_empty(4),
      I2 => mem_out(74),
      O => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]\
    );
\app_rd_data[14]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(52),
      I1 => my_empty(4),
      I2 => mem_out(64),
      O => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]\
    );
\app_rd_data[15]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(60),
      I1 => my_empty(4),
      I2 => mem_out(72),
      O => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]\
    );
\app_rd_data[200]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(7),
      I1 => \my_empty_inst_rep__4_n_0\,
      I2 => mem_out(19),
      O => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]\
    );
\app_rd_data[201]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(15),
      I1 => \my_empty_inst_rep__4_n_0\,
      I2 => mem_out(27),
      O => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]\
    );
\app_rd_data[202]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(23),
      I1 => \my_empty_inst_rep__4_n_0\,
      I2 => mem_out(35),
      O => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]\
    );
\app_rd_data[203]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(31),
      I1 => \my_empty_inst_rep__4_n_0\,
      I2 => mem_out(43),
      O => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]\
    );
\app_rd_data[204]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(39),
      I1 => my_empty(4),
      I2 => mem_out(51),
      O => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]\
    );
\app_rd_data[205]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(47),
      I1 => my_empty(4),
      I2 => mem_out(59),
      O => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]\
    );
\app_rd_data[206]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(55),
      I1 => my_empty(4),
      I2 => mem_out(67),
      O => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]\
    );
\app_rd_data[207]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(63),
      I1 => my_empty(4),
      I2 => mem_out(75),
      O => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]\
    );
\app_rd_data[264]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(8),
      I1 => \my_empty_inst_rep__4_n_0\,
      I2 => mem_out(20),
      O => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]\
    );
\app_rd_data[265]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(16),
      I1 => \my_empty_inst_rep__4_n_0\,
      I2 => mem_out(28),
      O => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]\
    );
\app_rd_data[266]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(24),
      I1 => \my_empty_inst_rep__4_n_0\,
      I2 => mem_out(36),
      O => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]\
    );
\app_rd_data[267]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(32),
      I1 => \my_empty_inst_rep__4_n_0\,
      I2 => mem_out(44),
      O => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]\
    );
\app_rd_data[268]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(40),
      I1 => my_empty(4),
      I2 => mem_out(52),
      O => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]\
    );
\app_rd_data[269]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(48),
      I1 => my_empty(4),
      I2 => mem_out(60),
      O => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]\
    );
\app_rd_data[270]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(56),
      I1 => my_empty(4),
      I2 => mem_out(68),
      O => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]\
    );
\app_rd_data[271]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(64),
      I1 => my_empty(4),
      I2 => mem_out(76),
      O => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]\
    );
\app_rd_data[328]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(9),
      I1 => \my_empty_inst_rep__4_n_0\,
      I2 => mem_out(21),
      O => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]\
    );
\app_rd_data[329]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(17),
      I1 => \my_empty_inst_rep__4_n_0\,
      I2 => mem_out(29),
      O => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]\
    );
\app_rd_data[330]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(25),
      I1 => \my_empty_inst_rep__4_n_0\,
      I2 => mem_out(37),
      O => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]\
    );
\app_rd_data[331]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(33),
      I1 => \my_empty_inst_rep__4_n_0\,
      I2 => mem_out(45),
      O => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]\
    );
\app_rd_data[332]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(41),
      I1 => my_empty(4),
      I2 => mem_out(53),
      O => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]\
    );
\app_rd_data[333]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(49),
      I1 => my_empty(4),
      I2 => mem_out(61),
      O => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]\
    );
\app_rd_data[334]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(57),
      I1 => my_empty(4),
      I2 => mem_out(69),
      O => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]\
    );
\app_rd_data[335]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(65),
      I1 => my_empty(4),
      I2 => mem_out(77),
      O => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]\
    );
\app_rd_data[392]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(10),
      I1 => \my_empty_inst_rep__4_n_0\,
      I2 => mem_out(22),
      O => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]\
    );
\app_rd_data[393]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(18),
      I1 => \my_empty_inst_rep__4_n_0\,
      I2 => mem_out(30),
      O => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]\
    );
\app_rd_data[394]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(26),
      I1 => \my_empty_inst_rep__4_n_0\,
      I2 => mem_out(38),
      O => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]\
    );
\app_rd_data[395]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(34),
      I1 => \my_empty_inst_rep__4_n_0\,
      I2 => mem_out(46),
      O => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]\
    );
\app_rd_data[396]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(42),
      I1 => my_empty(4),
      I2 => mem_out(54),
      O => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]\
    );
\app_rd_data[397]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(50),
      I1 => my_empty(4),
      I2 => mem_out(62),
      O => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]\
    );
\app_rd_data[398]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(58),
      I1 => my_empty(4),
      I2 => mem_out(70),
      O => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]\
    );
\app_rd_data[399]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(66),
      I1 => my_empty(4),
      I2 => mem_out(78),
      O => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]\
    );
\app_rd_data[456]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(11),
      I1 => \my_empty_inst_rep__4_n_0\,
      I2 => mem_out(23),
      O => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]\
    );
\app_rd_data[457]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(19),
      I1 => \my_empty_inst_rep__4_n_0\,
      I2 => mem_out(31),
      O => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]\
    );
\app_rd_data[458]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(27),
      I1 => \my_empty_inst_rep__4_n_0\,
      I2 => mem_out(39),
      O => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]\
    );
\app_rd_data[459]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(35),
      I1 => \my_empty_inst_rep__4_n_0\,
      I2 => mem_out(47),
      O => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]\
    );
\app_rd_data[460]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(43),
      I1 => my_empty(4),
      I2 => mem_out(55),
      O => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]\
    );
\app_rd_data[461]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(51),
      I1 => my_empty(4),
      I2 => mem_out(63),
      O => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]\
    );
\app_rd_data[462]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(59),
      I1 => my_empty(4),
      I2 => mem_out(71),
      O => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]\
    );
\app_rd_data[463]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(67),
      I1 => my_empty(4),
      I2 => mem_out(79),
      O => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]\
    );
\app_rd_data[72]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(5),
      I1 => \my_empty_inst_rep__4_n_0\,
      I2 => mem_out(17),
      O => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]\
    );
\app_rd_data[73]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(13),
      I1 => \my_empty_inst_rep__4_n_0\,
      I2 => mem_out(25),
      O => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]\
    );
\app_rd_data[74]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(21),
      I1 => \my_empty_inst_rep__4_n_0\,
      I2 => mem_out(33),
      O => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]\
    );
\app_rd_data[75]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(29),
      I1 => \my_empty_inst_rep__4_n_0\,
      I2 => mem_out(41),
      O => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]\
    );
\app_rd_data[76]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(37),
      I1 => my_empty(4),
      I2 => mem_out(49),
      O => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]\
    );
\app_rd_data[77]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(45),
      I1 => my_empty(4),
      I2 => mem_out(57),
      O => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]\
    );
\app_rd_data[78]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(53),
      I1 => my_empty(4),
      I2 => mem_out(65),
      O => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]\
    );
\app_rd_data[79]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(61),
      I1 => my_empty(4),
      I2 => mem_out(73),
      O => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]\
    );
\app_rd_data[8]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(4),
      I1 => \my_empty_inst_rep__4_n_0\,
      I2 => mem_out(16),
      O => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]\
    );
\app_rd_data[9]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(12),
      I1 => \my_empty_inst_rep__4_n_0\,
      I2 => mem_out(24),
      O => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]\
    );
\gen_mux_rd[0].mux_rd_fall0_r[0]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FDB97531ECA86420"
    )
        port map (
      I0 => \gen_mux_rd[0].mux_rd_rise0_r_reg[0]\(0),
      I1 => \gen_mux_rd[0].mux_rd_rise0_r_reg[0]\(1),
      I2 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]\,
      I3 => \gen_mux_rd[0].mux_rd_fall0_r_reg[0]\,
      I4 => \gen_mux_rd[0].mux_rd_fall0_r_reg[0]_0\,
      I5 => \gen_mux_rd[0].mux_rd_fall0_r_reg[0]_1\,
      O => \rd_mux_sel_r_reg[0]_7\
    );
\gen_mux_rd[0].mux_rd_fall1_r[0]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FDB97531ECA86420"
    )
        port map (
      I0 => \gen_mux_rd[0].mux_rd_rise0_r_reg[0]\(0),
      I1 => \gen_mux_rd[0].mux_rd_rise0_r_reg[0]\(1),
      I2 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]\,
      I3 => \gen_mux_rd[0].mux_rd_fall1_r_reg[0]\,
      I4 => \gen_mux_rd[0].mux_rd_fall1_r_reg[0]_0\,
      I5 => \gen_mux_rd[0].mux_rd_fall1_r_reg[0]_1\,
      O => \rd_mux_sel_r_reg[0]_23\
    );
\gen_mux_rd[0].mux_rd_fall2_r[0]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FDB97531ECA86420"
    )
        port map (
      I0 => \gen_mux_rd[0].mux_rd_rise0_r_reg[0]\(0),
      I1 => \gen_mux_rd[0].mux_rd_rise0_r_reg[0]\(1),
      I2 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]\,
      I3 => \gen_mux_rd[0].mux_rd_fall2_r_reg[0]\,
      I4 => \gen_mux_rd[0].mux_rd_fall2_r_reg[0]_0\,
      I5 => \gen_mux_rd[0].mux_rd_fall2_r_reg[0]_1\,
      O => \rd_mux_sel_r_reg[0]_39\
    );
\gen_mux_rd[0].mux_rd_fall3_r[0]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FDB97531ECA86420"
    )
        port map (
      I0 => \gen_mux_rd[0].mux_rd_rise0_r_reg[0]\(0),
      I1 => \gen_mux_rd[0].mux_rd_rise0_r_reg[0]\(1),
      I2 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]\,
      I3 => \gen_mux_rd[0].mux_rd_fall3_r_reg[0]\,
      I4 => \gen_mux_rd[0].mux_rd_fall3_r_reg[0]_0\,
      I5 => \gen_mux_rd[0].mux_rd_fall3_r_reg[0]_1\,
      O => \rd_mux_sel_r_reg[0]_55\
    );
\gen_mux_rd[0].mux_rd_rise0_r[0]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FDB97531ECA86420"
    )
        port map (
      I0 => \gen_mux_rd[0].mux_rd_rise0_r_reg[0]\(0),
      I1 => \gen_mux_rd[0].mux_rd_rise0_r_reg[0]\(1),
      I2 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]\,
      I3 => \gen_mux_rd[0].mux_rd_rise0_r_reg[0]_0\,
      I4 => \gen_mux_rd[0].mux_rd_rise0_r_reg[0]_1\,
      I5 => \gen_mux_rd[0].mux_rd_rise0_r_reg[0]_2\,
      O => \rd_mux_sel_r_reg[0]\
    );
\gen_mux_rd[0].mux_rd_rise1_r[0]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FDB97531ECA86420"
    )
        port map (
      I0 => \gen_mux_rd[0].mux_rd_rise0_r_reg[0]\(0),
      I1 => \gen_mux_rd[0].mux_rd_rise0_r_reg[0]\(1),
      I2 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]\,
      I3 => \gen_mux_rd[0].mux_rd_rise1_r_reg[0]\,
      I4 => \gen_mux_rd[0].mux_rd_rise1_r_reg[0]_0\,
      I5 => \gen_mux_rd[0].mux_rd_rise1_r_reg[0]_1\,
      O => \rd_mux_sel_r_reg[0]_15\
    );
\gen_mux_rd[0].mux_rd_rise2_r[0]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FDB97531ECA86420"
    )
        port map (
      I0 => \gen_mux_rd[0].mux_rd_rise0_r_reg[0]\(0),
      I1 => \gen_mux_rd[0].mux_rd_rise0_r_reg[0]\(1),
      I2 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]\,
      I3 => \gen_mux_rd[0].mux_rd_rise2_r_reg[0]\,
      I4 => \gen_mux_rd[0].mux_rd_rise2_r_reg[0]_0\,
      I5 => \gen_mux_rd[0].mux_rd_rise2_r_reg[0]_1\,
      O => \rd_mux_sel_r_reg[0]_31\
    );
\gen_mux_rd[0].mux_rd_rise3_r[0]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FDB97531ECA86420"
    )
        port map (
      I0 => \gen_mux_rd[0].mux_rd_rise0_r_reg[0]\(0),
      I1 => \gen_mux_rd[0].mux_rd_rise0_r_reg[0]\(1),
      I2 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]\,
      I3 => \gen_mux_rd[0].mux_rd_rise3_r_reg[0]\,
      I4 => \gen_mux_rd[0].mux_rd_rise3_r_reg[0]_0\,
      I5 => \gen_mux_rd[0].mux_rd_rise3_r_reg[0]_1\,
      O => \rd_mux_sel_r_reg[0]_47\
    );
\gen_mux_rd[1].mux_rd_fall0_r[1]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FDB97531ECA86420"
    )
        port map (
      I0 => \gen_mux_rd[0].mux_rd_rise0_r_reg[0]\(0),
      I1 => \gen_mux_rd[0].mux_rd_rise0_r_reg[0]\(1),
      I2 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]\,
      I3 => \gen_mux_rd[1].mux_rd_fall0_r_reg[1]\,
      I4 => \gen_mux_rd[1].mux_rd_fall0_r_reg[1]_0\,
      I5 => \gen_mux_rd[1].mux_rd_fall0_r_reg[1]_1\,
      O => \rd_mux_sel_r_reg[0]_8\
    );
\gen_mux_rd[1].mux_rd_fall1_r[1]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FDB97531ECA86420"
    )
        port map (
      I0 => \gen_mux_rd[0].mux_rd_rise0_r_reg[0]\(0),
      I1 => \gen_mux_rd[0].mux_rd_rise0_r_reg[0]\(1),
      I2 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]\,
      I3 => \gen_mux_rd[1].mux_rd_fall1_r_reg[1]\,
      I4 => \gen_mux_rd[1].mux_rd_fall1_r_reg[1]_0\,
      I5 => \gen_mux_rd[1].mux_rd_fall1_r_reg[1]_1\,
      O => \rd_mux_sel_r_reg[0]_24\
    );
\gen_mux_rd[1].mux_rd_fall2_r[1]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FDB97531ECA86420"
    )
        port map (
      I0 => \gen_mux_rd[0].mux_rd_rise0_r_reg[0]\(0),
      I1 => \gen_mux_rd[0].mux_rd_rise0_r_reg[0]\(1),
      I2 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]\,
      I3 => \gen_mux_rd[1].mux_rd_fall2_r_reg[1]\,
      I4 => \gen_mux_rd[1].mux_rd_fall2_r_reg[1]_0\,
      I5 => \gen_mux_rd[1].mux_rd_fall2_r_reg[1]_1\,
      O => \rd_mux_sel_r_reg[0]_40\
    );
\gen_mux_rd[1].mux_rd_fall3_r[1]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FDB97531ECA86420"
    )
        port map (
      I0 => \gen_mux_rd[0].mux_rd_rise0_r_reg[0]\(0),
      I1 => \gen_mux_rd[0].mux_rd_rise0_r_reg[0]\(1),
      I2 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]\,
      I3 => \gen_mux_rd[1].mux_rd_fall3_r_reg[1]\,
      I4 => \gen_mux_rd[1].mux_rd_fall3_r_reg[1]_0\,
      I5 => \gen_mux_rd[1].mux_rd_fall3_r_reg[1]_1\,
      O => \rd_mux_sel_r_reg[0]_56\
    );
\gen_mux_rd[1].mux_rd_rise0_r[1]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FDB97531ECA86420"
    )
        port map (
      I0 => \gen_mux_rd[0].mux_rd_rise0_r_reg[0]\(0),
      I1 => \gen_mux_rd[0].mux_rd_rise0_r_reg[0]\(1),
      I2 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]\,
      I3 => \gen_mux_rd[1].mux_rd_rise0_r_reg[1]\,
      I4 => \gen_mux_rd[1].mux_rd_rise0_r_reg[1]_0\,
      I5 => \gen_mux_rd[1].mux_rd_rise0_r_reg[1]_1\,
      O => \rd_mux_sel_r_reg[0]_0\
    );
\gen_mux_rd[1].mux_rd_rise1_r[1]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FDB97531ECA86420"
    )
        port map (
      I0 => \gen_mux_rd[0].mux_rd_rise0_r_reg[0]\(0),
      I1 => \gen_mux_rd[0].mux_rd_rise0_r_reg[0]\(1),
      I2 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]\,
      I3 => \gen_mux_rd[1].mux_rd_rise1_r_reg[1]\,
      I4 => \gen_mux_rd[1].mux_rd_rise1_r_reg[1]_0\,
      I5 => \gen_mux_rd[1].mux_rd_rise1_r_reg[1]_1\,
      O => \rd_mux_sel_r_reg[0]_16\
    );
\gen_mux_rd[1].mux_rd_rise2_r[1]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FDB97531ECA86420"
    )
        port map (
      I0 => \gen_mux_rd[0].mux_rd_rise0_r_reg[0]\(0),
      I1 => \gen_mux_rd[0].mux_rd_rise0_r_reg[0]\(1),
      I2 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]\,
      I3 => \gen_mux_rd[1].mux_rd_rise2_r_reg[1]\,
      I4 => \gen_mux_rd[1].mux_rd_rise2_r_reg[1]_0\,
      I5 => \gen_mux_rd[1].mux_rd_rise2_r_reg[1]_1\,
      O => \rd_mux_sel_r_reg[0]_32\
    );
\gen_mux_rd[1].mux_rd_rise3_r[1]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FDB97531ECA86420"
    )
        port map (
      I0 => \gen_mux_rd[0].mux_rd_rise0_r_reg[0]\(0),
      I1 => \gen_mux_rd[0].mux_rd_rise0_r_reg[0]\(1),
      I2 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]\,
      I3 => \gen_mux_rd[1].mux_rd_rise3_r_reg[1]\,
      I4 => \gen_mux_rd[1].mux_rd_rise3_r_reg[1]_0\,
      I5 => \gen_mux_rd[1].mux_rd_rise3_r_reg[1]_1\,
      O => \rd_mux_sel_r_reg[0]_48\
    );
\gen_mux_rd[2].mux_rd_fall0_r[2]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FDB97531ECA86420"
    )
        port map (
      I0 => \gen_mux_rd[0].mux_rd_rise0_r_reg[0]\(0),
      I1 => \gen_mux_rd[0].mux_rd_rise0_r_reg[0]\(1),
      I2 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]\,
      I3 => \gen_mux_rd[2].mux_rd_fall0_r_reg[2]\,
      I4 => \gen_mux_rd[2].mux_rd_fall0_r_reg[2]_0\,
      I5 => \gen_mux_rd[2].mux_rd_fall0_r_reg[2]_1\,
      O => \rd_mux_sel_r_reg[0]_9\
    );
\gen_mux_rd[2].mux_rd_fall1_r[2]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FDB97531ECA86420"
    )
        port map (
      I0 => \gen_mux_rd[0].mux_rd_rise0_r_reg[0]\(0),
      I1 => \gen_mux_rd[0].mux_rd_rise0_r_reg[0]\(1),
      I2 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]\,
      I3 => \gen_mux_rd[2].mux_rd_fall1_r_reg[2]\,
      I4 => \gen_mux_rd[2].mux_rd_fall1_r_reg[2]_0\,
      I5 => \gen_mux_rd[2].mux_rd_fall1_r_reg[2]_1\,
      O => \rd_mux_sel_r_reg[0]_25\
    );
\gen_mux_rd[2].mux_rd_fall2_r[2]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FDB97531ECA86420"
    )
        port map (
      I0 => \gen_mux_rd[0].mux_rd_rise0_r_reg[0]\(0),
      I1 => \gen_mux_rd[0].mux_rd_rise0_r_reg[0]\(1),
      I2 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]\,
      I3 => \gen_mux_rd[2].mux_rd_fall2_r_reg[2]\,
      I4 => \gen_mux_rd[2].mux_rd_fall2_r_reg[2]_0\,
      I5 => \gen_mux_rd[2].mux_rd_fall2_r_reg[2]_1\,
      O => \rd_mux_sel_r_reg[0]_41\
    );
\gen_mux_rd[2].mux_rd_fall3_r[2]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FDB97531ECA86420"
    )
        port map (
      I0 => \gen_mux_rd[0].mux_rd_rise0_r_reg[0]\(0),
      I1 => \gen_mux_rd[0].mux_rd_rise0_r_reg[0]\(1),
      I2 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]\,
      I3 => \gen_mux_rd[2].mux_rd_fall3_r_reg[2]\,
      I4 => \gen_mux_rd[2].mux_rd_fall3_r_reg[2]_0\,
      I5 => \gen_mux_rd[2].mux_rd_fall3_r_reg[2]_1\,
      O => \rd_mux_sel_r_reg[0]_57\
    );
\gen_mux_rd[2].mux_rd_rise0_r[2]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FDB97531ECA86420"
    )
        port map (
      I0 => \gen_mux_rd[0].mux_rd_rise0_r_reg[0]\(0),
      I1 => \gen_mux_rd[0].mux_rd_rise0_r_reg[0]\(1),
      I2 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]\,
      I3 => \gen_mux_rd[2].mux_rd_rise0_r_reg[2]\,
      I4 => \gen_mux_rd[2].mux_rd_rise0_r_reg[2]_0\,
      I5 => \gen_mux_rd[2].mux_rd_rise0_r_reg[2]_1\,
      O => \rd_mux_sel_r_reg[0]_1\
    );
\gen_mux_rd[2].mux_rd_rise1_r[2]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FDB97531ECA86420"
    )
        port map (
      I0 => \gen_mux_rd[0].mux_rd_rise0_r_reg[0]\(0),
      I1 => \gen_mux_rd[0].mux_rd_rise0_r_reg[0]\(1),
      I2 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]\,
      I3 => \gen_mux_rd[2].mux_rd_rise1_r_reg[2]\,
      I4 => \gen_mux_rd[2].mux_rd_rise1_r_reg[2]_0\,
      I5 => \gen_mux_rd[2].mux_rd_rise1_r_reg[2]_1\,
      O => \rd_mux_sel_r_reg[0]_17\
    );
\gen_mux_rd[2].mux_rd_rise2_r[2]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FDB97531ECA86420"
    )
        port map (
      I0 => \gen_mux_rd[0].mux_rd_rise0_r_reg[0]\(0),
      I1 => \gen_mux_rd[0].mux_rd_rise0_r_reg[0]\(1),
      I2 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]\,
      I3 => \gen_mux_rd[2].mux_rd_rise2_r_reg[2]\,
      I4 => \gen_mux_rd[2].mux_rd_rise2_r_reg[2]_0\,
      I5 => \gen_mux_rd[2].mux_rd_rise2_r_reg[2]_1\,
      O => \rd_mux_sel_r_reg[0]_33\
    );
\gen_mux_rd[2].mux_rd_rise3_r[2]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FDB97531ECA86420"
    )
        port map (
      I0 => \gen_mux_rd[0].mux_rd_rise0_r_reg[0]\(0),
      I1 => \gen_mux_rd[0].mux_rd_rise0_r_reg[0]\(1),
      I2 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]\,
      I3 => \gen_mux_rd[2].mux_rd_rise3_r_reg[2]\,
      I4 => \gen_mux_rd[2].mux_rd_rise3_r_reg[2]_0\,
      I5 => \gen_mux_rd[2].mux_rd_rise3_r_reg[2]_1\,
      O => \rd_mux_sel_r_reg[0]_49\
    );
\gen_mux_rd[3].mux_rd_fall0_r[3]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FDB97531ECA86420"
    )
        port map (
      I0 => \gen_mux_rd[0].mux_rd_rise0_r_reg[0]\(0),
      I1 => \gen_mux_rd[0].mux_rd_rise0_r_reg[0]\(1),
      I2 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]\,
      I3 => \gen_mux_rd[3].mux_rd_fall0_r_reg[3]\,
      I4 => \gen_mux_rd[3].mux_rd_fall0_r_reg[3]_0\,
      I5 => \gen_mux_rd[3].mux_rd_fall0_r_reg[3]_1\,
      O => \rd_mux_sel_r_reg[0]_10\
    );
\gen_mux_rd[3].mux_rd_fall1_r[3]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FDB97531ECA86420"
    )
        port map (
      I0 => \gen_mux_rd[0].mux_rd_rise0_r_reg[0]\(0),
      I1 => \gen_mux_rd[0].mux_rd_rise0_r_reg[0]\(1),
      I2 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]\,
      I3 => \gen_mux_rd[3].mux_rd_fall1_r_reg[3]\,
      I4 => \gen_mux_rd[3].mux_rd_fall1_r_reg[3]_0\,
      I5 => \gen_mux_rd[3].mux_rd_fall1_r_reg[3]_1\,
      O => \rd_mux_sel_r_reg[0]_26\
    );
\gen_mux_rd[3].mux_rd_fall2_r[3]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FDB97531ECA86420"
    )
        port map (
      I0 => \gen_mux_rd[0].mux_rd_rise0_r_reg[0]\(0),
      I1 => \gen_mux_rd[0].mux_rd_rise0_r_reg[0]\(1),
      I2 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]\,
      I3 => \gen_mux_rd[3].mux_rd_fall2_r_reg[3]\,
      I4 => \gen_mux_rd[3].mux_rd_fall2_r_reg[3]_0\,
      I5 => \gen_mux_rd[3].mux_rd_fall2_r_reg[3]_1\,
      O => \rd_mux_sel_r_reg[0]_42\
    );
\gen_mux_rd[3].mux_rd_fall3_r[3]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FDB97531ECA86420"
    )
        port map (
      I0 => \gen_mux_rd[0].mux_rd_rise0_r_reg[0]\(0),
      I1 => \gen_mux_rd[0].mux_rd_rise0_r_reg[0]\(1),
      I2 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]\,
      I3 => \gen_mux_rd[3].mux_rd_fall3_r_reg[3]\,
      I4 => \gen_mux_rd[3].mux_rd_fall3_r_reg[3]_0\,
      I5 => \gen_mux_rd[3].mux_rd_fall3_r_reg[3]_1\,
      O => \rd_mux_sel_r_reg[0]_58\
    );
\gen_mux_rd[3].mux_rd_rise0_r[3]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FDB97531ECA86420"
    )
        port map (
      I0 => \gen_mux_rd[0].mux_rd_rise0_r_reg[0]\(0),
      I1 => \gen_mux_rd[0].mux_rd_rise0_r_reg[0]\(1),
      I2 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]\,
      I3 => \gen_mux_rd[3].mux_rd_rise0_r_reg[3]\,
      I4 => \gen_mux_rd[3].mux_rd_rise0_r_reg[3]_0\,
      I5 => \gen_mux_rd[3].mux_rd_rise0_r_reg[3]_1\,
      O => \rd_mux_sel_r_reg[0]_2\
    );
\gen_mux_rd[3].mux_rd_rise1_r[3]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FDB97531ECA86420"
    )
        port map (
      I0 => \gen_mux_rd[0].mux_rd_rise0_r_reg[0]\(0),
      I1 => \gen_mux_rd[0].mux_rd_rise0_r_reg[0]\(1),
      I2 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]\,
      I3 => \gen_mux_rd[3].mux_rd_rise1_r_reg[3]\,
      I4 => \gen_mux_rd[3].mux_rd_rise1_r_reg[3]_0\,
      I5 => \gen_mux_rd[3].mux_rd_rise1_r_reg[3]_1\,
      O => \rd_mux_sel_r_reg[0]_18\
    );
\gen_mux_rd[3].mux_rd_rise2_r[3]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FDB97531ECA86420"
    )
        port map (
      I0 => \gen_mux_rd[0].mux_rd_rise0_r_reg[0]\(0),
      I1 => \gen_mux_rd[0].mux_rd_rise0_r_reg[0]\(1),
      I2 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]\,
      I3 => \gen_mux_rd[3].mux_rd_rise2_r_reg[3]\,
      I4 => \gen_mux_rd[3].mux_rd_rise2_r_reg[3]_0\,
      I5 => \gen_mux_rd[3].mux_rd_rise2_r_reg[3]_1\,
      O => \rd_mux_sel_r_reg[0]_34\
    );
\gen_mux_rd[3].mux_rd_rise3_r[3]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FDB97531ECA86420"
    )
        port map (
      I0 => \gen_mux_rd[0].mux_rd_rise0_r_reg[0]\(0),
      I1 => \gen_mux_rd[0].mux_rd_rise0_r_reg[0]\(1),
      I2 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]\,
      I3 => \gen_mux_rd[3].mux_rd_rise3_r_reg[3]\,
      I4 => \gen_mux_rd[3].mux_rd_rise3_r_reg[3]_0\,
      I5 => \gen_mux_rd[3].mux_rd_rise3_r_reg[3]_1\,
      O => \rd_mux_sel_r_reg[0]_50\
    );
\gen_mux_rd[4].mux_rd_fall0_r[4]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FDB97531ECA86420"
    )
        port map (
      I0 => \gen_mux_rd[0].mux_rd_rise0_r_reg[0]\(0),
      I1 => \gen_mux_rd[0].mux_rd_rise0_r_reg[0]\(1),
      I2 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]\,
      I3 => \gen_mux_rd[4].mux_rd_fall0_r_reg[4]\,
      I4 => \gen_mux_rd[4].mux_rd_fall0_r_reg[4]_0\,
      I5 => \gen_mux_rd[4].mux_rd_fall0_r_reg[4]_1\,
      O => \rd_mux_sel_r_reg[0]_11\
    );
\gen_mux_rd[4].mux_rd_fall1_r[4]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FDB97531ECA86420"
    )
        port map (
      I0 => \gen_mux_rd[0].mux_rd_rise0_r_reg[0]\(0),
      I1 => \gen_mux_rd[0].mux_rd_rise0_r_reg[0]\(1),
      I2 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]\,
      I3 => \gen_mux_rd[4].mux_rd_fall1_r_reg[4]\,
      I4 => \gen_mux_rd[4].mux_rd_fall1_r_reg[4]_0\,
      I5 => \gen_mux_rd[4].mux_rd_fall1_r_reg[4]_1\,
      O => \rd_mux_sel_r_reg[0]_27\
    );
\gen_mux_rd[4].mux_rd_fall2_r[4]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FDB97531ECA86420"
    )
        port map (
      I0 => \gen_mux_rd[0].mux_rd_rise0_r_reg[0]\(0),
      I1 => \gen_mux_rd[0].mux_rd_rise0_r_reg[0]\(1),
      I2 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]\,
      I3 => \gen_mux_rd[4].mux_rd_fall2_r_reg[4]\,
      I4 => \gen_mux_rd[4].mux_rd_fall2_r_reg[4]_0\,
      I5 => \gen_mux_rd[4].mux_rd_fall2_r_reg[4]_1\,
      O => \rd_mux_sel_r_reg[0]_43\
    );
\gen_mux_rd[4].mux_rd_fall3_r[4]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FDB97531ECA86420"
    )
        port map (
      I0 => \gen_mux_rd[0].mux_rd_rise0_r_reg[0]\(0),
      I1 => \gen_mux_rd[0].mux_rd_rise0_r_reg[0]\(1),
      I2 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]\,
      I3 => \gen_mux_rd[4].mux_rd_fall3_r_reg[4]\,
      I4 => \gen_mux_rd[4].mux_rd_fall3_r_reg[4]_0\,
      I5 => \gen_mux_rd[4].mux_rd_fall3_r_reg[4]_1\,
      O => \rd_mux_sel_r_reg[0]_59\
    );
\gen_mux_rd[4].mux_rd_rise0_r[4]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FDB97531ECA86420"
    )
        port map (
      I0 => \gen_mux_rd[0].mux_rd_rise0_r_reg[0]\(0),
      I1 => \gen_mux_rd[0].mux_rd_rise0_r_reg[0]\(1),
      I2 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]\,
      I3 => \gen_mux_rd[4].mux_rd_rise0_r_reg[4]\,
      I4 => \gen_mux_rd[4].mux_rd_rise0_r_reg[4]_0\,
      I5 => \gen_mux_rd[4].mux_rd_rise0_r_reg[4]_1\,
      O => \rd_mux_sel_r_reg[0]_3\
    );
\gen_mux_rd[4].mux_rd_rise1_r[4]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FDB97531ECA86420"
    )
        port map (
      I0 => \gen_mux_rd[0].mux_rd_rise0_r_reg[0]\(0),
      I1 => \gen_mux_rd[0].mux_rd_rise0_r_reg[0]\(1),
      I2 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]\,
      I3 => \gen_mux_rd[4].mux_rd_rise1_r_reg[4]\,
      I4 => \gen_mux_rd[4].mux_rd_rise1_r_reg[4]_0\,
      I5 => \gen_mux_rd[4].mux_rd_rise1_r_reg[4]_1\,
      O => \rd_mux_sel_r_reg[0]_19\
    );
\gen_mux_rd[4].mux_rd_rise2_r[4]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FDB97531ECA86420"
    )
        port map (
      I0 => \gen_mux_rd[0].mux_rd_rise0_r_reg[0]\(0),
      I1 => \gen_mux_rd[0].mux_rd_rise0_r_reg[0]\(1),
      I2 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]\,
      I3 => \gen_mux_rd[4].mux_rd_rise2_r_reg[4]\,
      I4 => \gen_mux_rd[4].mux_rd_rise2_r_reg[4]_0\,
      I5 => \gen_mux_rd[4].mux_rd_rise2_r_reg[4]_1\,
      O => \rd_mux_sel_r_reg[0]_35\
    );
\gen_mux_rd[4].mux_rd_rise3_r[4]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FDB97531ECA86420"
    )
        port map (
      I0 => \gen_mux_rd[0].mux_rd_rise0_r_reg[0]\(0),
      I1 => \gen_mux_rd[0].mux_rd_rise0_r_reg[0]\(1),
      I2 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]\,
      I3 => \gen_mux_rd[4].mux_rd_rise3_r_reg[4]\,
      I4 => \gen_mux_rd[4].mux_rd_rise3_r_reg[4]_0\,
      I5 => \gen_mux_rd[4].mux_rd_rise3_r_reg[4]_1\,
      O => \rd_mux_sel_r_reg[0]_51\
    );
\gen_mux_rd[5].mux_rd_fall0_r[5]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FDB97531ECA86420"
    )
        port map (
      I0 => \gen_mux_rd[0].mux_rd_rise0_r_reg[0]\(0),
      I1 => \gen_mux_rd[0].mux_rd_rise0_r_reg[0]\(1),
      I2 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]\,
      I3 => \gen_mux_rd[5].mux_rd_fall0_r_reg[5]\,
      I4 => \gen_mux_rd[5].mux_rd_fall0_r_reg[5]_0\,
      I5 => \gen_mux_rd[5].mux_rd_fall0_r_reg[5]_1\,
      O => \rd_mux_sel_r_reg[0]_12\
    );
\gen_mux_rd[5].mux_rd_fall1_r[5]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FDB97531ECA86420"
    )
        port map (
      I0 => \gen_mux_rd[0].mux_rd_rise0_r_reg[0]\(0),
      I1 => \gen_mux_rd[0].mux_rd_rise0_r_reg[0]\(1),
      I2 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]\,
      I3 => \gen_mux_rd[5].mux_rd_fall1_r_reg[5]\,
      I4 => \gen_mux_rd[5].mux_rd_fall1_r_reg[5]_0\,
      I5 => \gen_mux_rd[5].mux_rd_fall1_r_reg[5]_1\,
      O => \rd_mux_sel_r_reg[0]_28\
    );
\gen_mux_rd[5].mux_rd_fall2_r[5]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FDB97531ECA86420"
    )
        port map (
      I0 => \gen_mux_rd[0].mux_rd_rise0_r_reg[0]\(0),
      I1 => \gen_mux_rd[0].mux_rd_rise0_r_reg[0]\(1),
      I2 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]\,
      I3 => \gen_mux_rd[5].mux_rd_fall2_r_reg[5]\,
      I4 => \gen_mux_rd[5].mux_rd_fall2_r_reg[5]_0\,
      I5 => \gen_mux_rd[5].mux_rd_fall2_r_reg[5]_1\,
      O => \rd_mux_sel_r_reg[0]_44\
    );
\gen_mux_rd[5].mux_rd_fall3_r[5]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FDB97531ECA86420"
    )
        port map (
      I0 => \gen_mux_rd[0].mux_rd_rise0_r_reg[0]\(0),
      I1 => \gen_mux_rd[0].mux_rd_rise0_r_reg[0]\(1),
      I2 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]\,
      I3 => \gen_mux_rd[5].mux_rd_fall3_r_reg[5]\,
      I4 => \gen_mux_rd[5].mux_rd_fall3_r_reg[5]_0\,
      I5 => \gen_mux_rd[5].mux_rd_fall3_r_reg[5]_1\,
      O => \rd_mux_sel_r_reg[0]_60\
    );
\gen_mux_rd[5].mux_rd_rise0_r[5]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FDB97531ECA86420"
    )
        port map (
      I0 => \gen_mux_rd[0].mux_rd_rise0_r_reg[0]\(0),
      I1 => \gen_mux_rd[0].mux_rd_rise0_r_reg[0]\(1),
      I2 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]\,
      I3 => \gen_mux_rd[5].mux_rd_rise0_r_reg[5]\,
      I4 => \gen_mux_rd[5].mux_rd_rise0_r_reg[5]_0\,
      I5 => \gen_mux_rd[5].mux_rd_rise0_r_reg[5]_1\,
      O => \rd_mux_sel_r_reg[0]_4\
    );
\gen_mux_rd[5].mux_rd_rise1_r[5]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FDB97531ECA86420"
    )
        port map (
      I0 => \gen_mux_rd[0].mux_rd_rise0_r_reg[0]\(0),
      I1 => \gen_mux_rd[0].mux_rd_rise0_r_reg[0]\(1),
      I2 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]\,
      I3 => \gen_mux_rd[5].mux_rd_rise1_r_reg[5]\,
      I4 => \gen_mux_rd[5].mux_rd_rise1_r_reg[5]_0\,
      I5 => \gen_mux_rd[5].mux_rd_rise1_r_reg[5]_1\,
      O => \rd_mux_sel_r_reg[0]_20\
    );
\gen_mux_rd[5].mux_rd_rise2_r[5]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FDB97531ECA86420"
    )
        port map (
      I0 => \gen_mux_rd[0].mux_rd_rise0_r_reg[0]\(0),
      I1 => \gen_mux_rd[0].mux_rd_rise0_r_reg[0]\(1),
      I2 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]\,
      I3 => \gen_mux_rd[5].mux_rd_rise2_r_reg[5]\,
      I4 => \gen_mux_rd[5].mux_rd_rise2_r_reg[5]_0\,
      I5 => \gen_mux_rd[5].mux_rd_rise2_r_reg[5]_1\,
      O => \rd_mux_sel_r_reg[0]_36\
    );
\gen_mux_rd[5].mux_rd_rise3_r[5]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FDB97531ECA86420"
    )
        port map (
      I0 => \gen_mux_rd[0].mux_rd_rise0_r_reg[0]\(0),
      I1 => \gen_mux_rd[0].mux_rd_rise0_r_reg[0]\(1),
      I2 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]\,
      I3 => \gen_mux_rd[5].mux_rd_rise3_r_reg[5]\,
      I4 => \gen_mux_rd[5].mux_rd_rise3_r_reg[5]_0\,
      I5 => \gen_mux_rd[5].mux_rd_rise3_r_reg[5]_1\,
      O => \rd_mux_sel_r_reg[0]_52\
    );
\gen_mux_rd[6].mux_rd_fall0_r[6]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FDB97531ECA86420"
    )
        port map (
      I0 => \gen_mux_rd[0].mux_rd_rise0_r_reg[0]\(0),
      I1 => \gen_mux_rd[0].mux_rd_rise0_r_reg[0]\(1),
      I2 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]\,
      I3 => \gen_mux_rd[6].mux_rd_fall0_r_reg[6]\,
      I4 => \gen_mux_rd[6].mux_rd_fall0_r_reg[6]_0\,
      I5 => \gen_mux_rd[6].mux_rd_fall0_r_reg[6]_1\,
      O => \rd_mux_sel_r_reg[0]_13\
    );
\gen_mux_rd[6].mux_rd_fall1_r[6]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FDB97531ECA86420"
    )
        port map (
      I0 => \gen_mux_rd[0].mux_rd_rise0_r_reg[0]\(0),
      I1 => \gen_mux_rd[0].mux_rd_rise0_r_reg[0]\(1),
      I2 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]\,
      I3 => \gen_mux_rd[6].mux_rd_fall1_r_reg[6]\,
      I4 => \gen_mux_rd[6].mux_rd_fall1_r_reg[6]_0\,
      I5 => \gen_mux_rd[6].mux_rd_fall1_r_reg[6]_1\,
      O => \rd_mux_sel_r_reg[0]_29\
    );
\gen_mux_rd[6].mux_rd_fall2_r[6]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FDB97531ECA86420"
    )
        port map (
      I0 => \gen_mux_rd[0].mux_rd_rise0_r_reg[0]\(0),
      I1 => \gen_mux_rd[0].mux_rd_rise0_r_reg[0]\(1),
      I2 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]\,
      I3 => \gen_mux_rd[6].mux_rd_fall2_r_reg[6]\,
      I4 => \gen_mux_rd[6].mux_rd_fall2_r_reg[6]_0\,
      I5 => \gen_mux_rd[6].mux_rd_fall2_r_reg[6]_1\,
      O => \rd_mux_sel_r_reg[0]_45\
    );
\gen_mux_rd[6].mux_rd_fall3_r[6]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FDB97531ECA86420"
    )
        port map (
      I0 => \gen_mux_rd[0].mux_rd_rise0_r_reg[0]\(0),
      I1 => \gen_mux_rd[0].mux_rd_rise0_r_reg[0]\(1),
      I2 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]\,
      I3 => \gen_mux_rd[6].mux_rd_fall3_r_reg[6]\,
      I4 => \gen_mux_rd[6].mux_rd_fall3_r_reg[6]_0\,
      I5 => \gen_mux_rd[6].mux_rd_fall3_r_reg[6]_1\,
      O => \rd_mux_sel_r_reg[0]_61\
    );
\gen_mux_rd[6].mux_rd_rise0_r[6]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FDB97531ECA86420"
    )
        port map (
      I0 => \gen_mux_rd[0].mux_rd_rise0_r_reg[0]\(0),
      I1 => \gen_mux_rd[0].mux_rd_rise0_r_reg[0]\(1),
      I2 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]\,
      I3 => \gen_mux_rd[6].mux_rd_rise0_r_reg[6]\,
      I4 => \gen_mux_rd[6].mux_rd_rise0_r_reg[6]_0\,
      I5 => \gen_mux_rd[6].mux_rd_rise0_r_reg[6]_1\,
      O => \rd_mux_sel_r_reg[0]_5\
    );
\gen_mux_rd[6].mux_rd_rise1_r[6]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FDB97531ECA86420"
    )
        port map (
      I0 => \gen_mux_rd[0].mux_rd_rise0_r_reg[0]\(0),
      I1 => \gen_mux_rd[0].mux_rd_rise0_r_reg[0]\(1),
      I2 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]\,
      I3 => \gen_mux_rd[6].mux_rd_rise1_r_reg[6]\,
      I4 => \gen_mux_rd[6].mux_rd_rise1_r_reg[6]_0\,
      I5 => \gen_mux_rd[6].mux_rd_rise1_r_reg[6]_1\,
      O => \rd_mux_sel_r_reg[0]_21\
    );
\gen_mux_rd[6].mux_rd_rise2_r[6]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FDB97531ECA86420"
    )
        port map (
      I0 => \gen_mux_rd[0].mux_rd_rise0_r_reg[0]\(0),
      I1 => \gen_mux_rd[0].mux_rd_rise0_r_reg[0]\(1),
      I2 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]\,
      I3 => \gen_mux_rd[6].mux_rd_rise2_r_reg[6]\,
      I4 => \gen_mux_rd[6].mux_rd_rise2_r_reg[6]_0\,
      I5 => \gen_mux_rd[6].mux_rd_rise2_r_reg[6]_1\,
      O => \rd_mux_sel_r_reg[0]_37\
    );
\gen_mux_rd[6].mux_rd_rise3_r[6]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FDB97531ECA86420"
    )
        port map (
      I0 => \gen_mux_rd[0].mux_rd_rise0_r_reg[0]\(0),
      I1 => \gen_mux_rd[0].mux_rd_rise0_r_reg[0]\(1),
      I2 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]\,
      I3 => \gen_mux_rd[6].mux_rd_rise3_r_reg[6]\,
      I4 => \gen_mux_rd[6].mux_rd_rise3_r_reg[6]_0\,
      I5 => \gen_mux_rd[6].mux_rd_rise3_r_reg[6]_1\,
      O => \rd_mux_sel_r_reg[0]_53\
    );
\gen_mux_rd[7].mux_rd_fall0_r[7]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FDB97531ECA86420"
    )
        port map (
      I0 => \gen_mux_rd[0].mux_rd_rise0_r_reg[0]\(0),
      I1 => \gen_mux_rd[0].mux_rd_rise0_r_reg[0]\(1),
      I2 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]\,
      I3 => \gen_mux_rd[7].mux_rd_fall0_r_reg[7]\,
      I4 => \gen_mux_rd[7].mux_rd_fall0_r_reg[7]_0\,
      I5 => \gen_mux_rd[7].mux_rd_fall0_r_reg[7]_1\,
      O => \rd_mux_sel_r_reg[0]_14\
    );
\gen_mux_rd[7].mux_rd_fall1_r[7]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FDB97531ECA86420"
    )
        port map (
      I0 => \gen_mux_rd[0].mux_rd_rise0_r_reg[0]\(0),
      I1 => \gen_mux_rd[0].mux_rd_rise0_r_reg[0]\(1),
      I2 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]\,
      I3 => \gen_mux_rd[7].mux_rd_fall1_r_reg[7]\,
      I4 => \gen_mux_rd[7].mux_rd_fall1_r_reg[7]_0\,
      I5 => \gen_mux_rd[7].mux_rd_fall1_r_reg[7]_1\,
      O => \rd_mux_sel_r_reg[0]_30\
    );
\gen_mux_rd[7].mux_rd_fall2_r[7]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FDB97531ECA86420"
    )
        port map (
      I0 => \gen_mux_rd[0].mux_rd_rise0_r_reg[0]\(0),
      I1 => \gen_mux_rd[0].mux_rd_rise0_r_reg[0]\(1),
      I2 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]\,
      I3 => \gen_mux_rd[7].mux_rd_fall2_r_reg[7]\,
      I4 => \gen_mux_rd[7].mux_rd_fall2_r_reg[7]_0\,
      I5 => \gen_mux_rd[7].mux_rd_fall2_r_reg[7]_1\,
      O => \rd_mux_sel_r_reg[0]_46\
    );
\gen_mux_rd[7].mux_rd_fall3_r[7]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FDB97531ECA86420"
    )
        port map (
      I0 => \gen_mux_rd[0].mux_rd_rise0_r_reg[0]\(0),
      I1 => \gen_mux_rd[0].mux_rd_rise0_r_reg[0]\(1),
      I2 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]\,
      I3 => \gen_mux_rd[7].mux_rd_fall3_r_reg[7]\,
      I4 => \gen_mux_rd[7].mux_rd_fall3_r_reg[7]_0\,
      I5 => \gen_mux_rd[7].mux_rd_fall3_r_reg[7]_1\,
      O => \rd_mux_sel_r_reg[0]_62\
    );
\gen_mux_rd[7].mux_rd_rise0_r[7]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FDB97531ECA86420"
    )
        port map (
      I0 => \gen_mux_rd[0].mux_rd_rise0_r_reg[0]\(0),
      I1 => \gen_mux_rd[0].mux_rd_rise0_r_reg[0]\(1),
      I2 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]\,
      I3 => \gen_mux_rd[7].mux_rd_rise0_r_reg[7]\,
      I4 => \gen_mux_rd[7].mux_rd_rise0_r_reg[7]_0\,
      I5 => \gen_mux_rd[7].mux_rd_rise0_r_reg[7]_1\,
      O => \rd_mux_sel_r_reg[0]_6\
    );
\gen_mux_rd[7].mux_rd_rise1_r[7]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FDB97531ECA86420"
    )
        port map (
      I0 => \gen_mux_rd[0].mux_rd_rise0_r_reg[0]\(0),
      I1 => \gen_mux_rd[0].mux_rd_rise0_r_reg[0]\(1),
      I2 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]\,
      I3 => \gen_mux_rd[7].mux_rd_rise1_r_reg[7]\,
      I4 => \gen_mux_rd[7].mux_rd_rise1_r_reg[7]_0\,
      I5 => \gen_mux_rd[7].mux_rd_rise1_r_reg[7]_1\,
      O => \rd_mux_sel_r_reg[0]_22\
    );
\gen_mux_rd[7].mux_rd_rise2_r[7]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FDB97531ECA86420"
    )
        port map (
      I0 => \gen_mux_rd[0].mux_rd_rise0_r_reg[0]\(0),
      I1 => \gen_mux_rd[0].mux_rd_rise0_r_reg[0]\(1),
      I2 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]\,
      I3 => \gen_mux_rd[7].mux_rd_rise2_r_reg[7]\,
      I4 => \gen_mux_rd[7].mux_rd_rise2_r_reg[7]_0\,
      I5 => \gen_mux_rd[7].mux_rd_rise2_r_reg[7]_1\,
      O => \rd_mux_sel_r_reg[0]_38\
    );
\gen_mux_rd[7].mux_rd_rise3_r[7]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FDB97531ECA86420"
    )
        port map (
      I0 => \gen_mux_rd[0].mux_rd_rise0_r_reg[0]\(0),
      I1 => \gen_mux_rd[0].mux_rd_rise0_r_reg[0]\(1),
      I2 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]\,
      I3 => \gen_mux_rd[7].mux_rd_rise3_r_reg[7]\,
      I4 => \gen_mux_rd[7].mux_rd_rise3_r_reg[7]_0\,
      I5 => \gen_mux_rd[7].mux_rd_rise3_r_reg[7]_1\,
      O => \rd_mux_sel_r_reg[0]_54\
    );
mem_reg_0_3_12_17: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 2) => B"000",
      ADDRA(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRB(4 downto 2) => B"000",
      ADDRB(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRC(4 downto 2) => B"000",
      ADDRC(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRD(4 downto 2) => B"000",
      ADDRD(1 downto 0) => wr_ptr(1 downto 0),
      DIA(1 downto 0) => Q(1 downto 0),
      DIB(1 downto 0) => Q(3 downto 2),
      DIC(1 downto 0) => Q(5 downto 4),
      DID(1 downto 0) => B"00",
      DOA(1) => mem_reg_0_3_12_17_n_0,
      DOA(0) => mem_reg_0_3_12_17_n_1,
      DOB(1) => mem_reg_0_3_12_17_n_2,
      DOB(0) => mem_reg_0_3_12_17_n_3,
      DOC(1 downto 0) => mem_out(17 downto 16),
      DOD(1 downto 0) => NLW_mem_reg_0_3_12_17_DOD_UNCONNECTED(1 downto 0),
      WCLK => \rd_ptr_timing_reg[1]_0\,
      WE => wr_en
    );
mem_reg_0_3_12_17_i_1: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0151"
    )
        port map (
      I0 => \my_full_reg[1]_0\,
      I1 => my_full(0),
      I2 => \my_full_reg[1]_1\,
      I3 => my_empty(2),
      O => wr_en
    );
mem_reg_0_3_18_23: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 2) => B"000",
      ADDRA(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRB(4 downto 2) => B"000",
      ADDRB(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRC(4 downto 2) => B"000",
      ADDRC(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRD(4 downto 2) => B"000",
      ADDRD(1 downto 0) => wr_ptr(1 downto 0),
      DIA(1 downto 0) => Q(7 downto 6),
      DIB(1 downto 0) => Q(9 downto 8),
      DIC(1 downto 0) => Q(11 downto 10),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => mem_out(19 downto 18),
      DOB(1 downto 0) => mem_out(21 downto 20),
      DOC(1 downto 0) => mem_out(23 downto 22),
      DOD(1 downto 0) => NLW_mem_reg_0_3_18_23_DOD_UNCONNECTED(1 downto 0),
      WCLK => \rd_ptr_timing_reg[1]_0\,
      WE => wr_en
    );
mem_reg_0_3_24_29: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 2) => B"000",
      ADDRA(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRB(4 downto 2) => B"000",
      ADDRB(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRC(4 downto 2) => B"000",
      ADDRC(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRD(4 downto 2) => B"000",
      ADDRD(1 downto 0) => wr_ptr(1 downto 0),
      DIA(1 downto 0) => Q(13 downto 12),
      DIB(1 downto 0) => Q(15 downto 14),
      DIC(1 downto 0) => Q(17 downto 16),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => mem_out(25 downto 24),
      DOB(1 downto 0) => mem_out(27 downto 26),
      DOC(1 downto 0) => mem_out(29 downto 28),
      DOD(1 downto 0) => NLW_mem_reg_0_3_24_29_DOD_UNCONNECTED(1 downto 0),
      WCLK => \rd_ptr_timing_reg[1]_0\,
      WE => wr_en
    );
mem_reg_0_3_30_35: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 2) => B"000",
      ADDRA(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRB(4 downto 2) => B"000",
      ADDRB(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRC(4 downto 2) => B"000",
      ADDRC(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRD(4 downto 2) => B"000",
      ADDRD(1 downto 0) => wr_ptr(1 downto 0),
      DIA(1 downto 0) => Q(19 downto 18),
      DIB(1 downto 0) => Q(21 downto 20),
      DIC(1 downto 0) => Q(23 downto 22),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => mem_out(31 downto 30),
      DOB(1 downto 0) => mem_out(33 downto 32),
      DOC(1 downto 0) => mem_out(35 downto 34),
      DOD(1 downto 0) => NLW_mem_reg_0_3_30_35_DOD_UNCONNECTED(1 downto 0),
      WCLK => \rd_ptr_timing_reg[1]_0\,
      WE => wr_en
    );
mem_reg_0_3_36_41: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 2) => B"000",
      ADDRA(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRB(4 downto 2) => B"000",
      ADDRB(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRC(4 downto 2) => B"000",
      ADDRC(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRD(4 downto 2) => B"000",
      ADDRD(1 downto 0) => wr_ptr(1 downto 0),
      DIA(1 downto 0) => Q(25 downto 24),
      DIB(1 downto 0) => Q(27 downto 26),
      DIC(1 downto 0) => Q(29 downto 28),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => mem_out(37 downto 36),
      DOB(1 downto 0) => mem_out(39 downto 38),
      DOC(1 downto 0) => mem_out(41 downto 40),
      DOD(1 downto 0) => NLW_mem_reg_0_3_36_41_DOD_UNCONNECTED(1 downto 0),
      WCLK => \rd_ptr_timing_reg[1]_0\,
      WE => wr_en
    );
mem_reg_0_3_42_47: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 2) => B"000",
      ADDRA(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRB(4 downto 2) => B"000",
      ADDRB(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRC(4 downto 2) => B"000",
      ADDRC(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRD(4 downto 2) => B"000",
      ADDRD(1 downto 0) => wr_ptr(1 downto 0),
      DIA(1 downto 0) => Q(31 downto 30),
      DIB(1 downto 0) => Q(33 downto 32),
      DIC(1 downto 0) => Q(35 downto 34),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => mem_out(43 downto 42),
      DOB(1 downto 0) => mem_out(45 downto 44),
      DOC(1 downto 0) => mem_out(47 downto 46),
      DOD(1 downto 0) => NLW_mem_reg_0_3_42_47_DOD_UNCONNECTED(1 downto 0),
      WCLK => \rd_ptr_timing_reg[1]_0\,
      WE => wr_en
    );
mem_reg_0_3_48_53: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 2) => B"000",
      ADDRA(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRB(4 downto 2) => B"000",
      ADDRB(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRC(4 downto 2) => B"000",
      ADDRC(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRD(4 downto 2) => B"000",
      ADDRD(1 downto 0) => wr_ptr(1 downto 0),
      DIA(1 downto 0) => Q(37 downto 36),
      DIB(1 downto 0) => Q(39 downto 38),
      DIC(1 downto 0) => Q(41 downto 40),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => mem_out(49 downto 48),
      DOB(1 downto 0) => mem_out(51 downto 50),
      DOC(1 downto 0) => mem_out(53 downto 52),
      DOD(1 downto 0) => NLW_mem_reg_0_3_48_53_DOD_UNCONNECTED(1 downto 0),
      WCLK => \rd_ptr_timing_reg[1]_0\,
      WE => wr_en
    );
mem_reg_0_3_54_59: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 2) => B"000",
      ADDRA(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRB(4 downto 2) => B"000",
      ADDRB(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRC(4 downto 2) => B"000",
      ADDRC(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRD(4 downto 2) => B"000",
      ADDRD(1 downto 0) => wr_ptr(1 downto 0),
      DIA(1 downto 0) => Q(43 downto 42),
      DIB(1 downto 0) => Q(45 downto 44),
      DIC(1 downto 0) => Q(47 downto 46),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => mem_out(55 downto 54),
      DOB(1 downto 0) => mem_out(57 downto 56),
      DOC(1 downto 0) => mem_out(59 downto 58),
      DOD(1 downto 0) => NLW_mem_reg_0_3_54_59_DOD_UNCONNECTED(1 downto 0),
      WCLK => \rd_ptr_timing_reg[1]_0\,
      WE => wr_en
    );
mem_reg_0_3_60_65: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 2) => B"000",
      ADDRA(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRB(4 downto 2) => B"000",
      ADDRB(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRC(4 downto 2) => B"000",
      ADDRC(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRD(4 downto 2) => B"000",
      ADDRD(1 downto 0) => wr_ptr(1 downto 0),
      DIA(1 downto 0) => Q(49 downto 48),
      DIB(1 downto 0) => Q(51 downto 50),
      DIC(1 downto 0) => Q(53 downto 52),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => mem_out(61 downto 60),
      DOB(1 downto 0) => mem_out(63 downto 62),
      DOC(1 downto 0) => mem_out(65 downto 64),
      DOD(1 downto 0) => NLW_mem_reg_0_3_60_65_DOD_UNCONNECTED(1 downto 0),
      WCLK => \rd_ptr_timing_reg[1]_0\,
      WE => wr_en
    );
mem_reg_0_3_66_71: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 2) => B"000",
      ADDRA(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRB(4 downto 2) => B"000",
      ADDRB(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRC(4 downto 2) => B"000",
      ADDRC(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRD(4 downto 2) => B"000",
      ADDRD(1 downto 0) => wr_ptr(1 downto 0),
      DIA(1 downto 0) => Q(55 downto 54),
      DIB(1 downto 0) => Q(57 downto 56),
      DIC(1 downto 0) => Q(59 downto 58),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => mem_out(67 downto 66),
      DOB(1 downto 0) => mem_out(69 downto 68),
      DOC(1 downto 0) => mem_out(71 downto 70),
      DOD(1 downto 0) => NLW_mem_reg_0_3_66_71_DOD_UNCONNECTED(1 downto 0),
      WCLK => \rd_ptr_timing_reg[1]_0\,
      WE => wr_en
    );
mem_reg_0_3_72_77: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 2) => B"000",
      ADDRA(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRB(4 downto 2) => B"000",
      ADDRB(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRC(4 downto 2) => B"000",
      ADDRC(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRD(4 downto 2) => B"000",
      ADDRD(1 downto 0) => wr_ptr(1 downto 0),
      DIA(1 downto 0) => Q(61 downto 60),
      DIB(1 downto 0) => Q(63 downto 62),
      DIC(1 downto 0) => Q(65 downto 64),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => mem_out(73 downto 72),
      DOB(1 downto 0) => mem_out(75 downto 74),
      DOC(1 downto 0) => mem_out(77 downto 76),
      DOD(1 downto 0) => NLW_mem_reg_0_3_72_77_DOD_UNCONNECTED(1 downto 0),
      WCLK => \rd_ptr_timing_reg[1]_0\,
      WE => wr_en
    );
mem_reg_0_3_78_79: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 2) => B"000",
      ADDRA(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRB(4 downto 2) => B"000",
      ADDRB(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRC(4 downto 2) => B"000",
      ADDRC(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRD(4 downto 2) => B"000",
      ADDRD(1 downto 0) => wr_ptr(1 downto 0),
      DIA(1 downto 0) => Q(67 downto 66),
      DIB(1 downto 0) => B"00",
      DIC(1 downto 0) => B"00",
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => mem_out(79 downto 78),
      DOB(1 downto 0) => NLW_mem_reg_0_3_78_79_DOB_UNCONNECTED(1 downto 0),
      DOC(1 downto 0) => NLW_mem_reg_0_3_78_79_DOC_UNCONNECTED(1 downto 0),
      DOD(1 downto 0) => NLW_mem_reg_0_3_78_79_DOD_UNCONNECTED(1 downto 0),
      WCLK => \rd_ptr_timing_reg[1]_0\,
      WE => wr_en
    );
\my_empty[4]_i_1__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0018"
    )
        port map (
      I0 => \my_full_reg[1]_1\,
      I1 => \my_full_reg[1]_0\,
      I2 => my_empty(1),
      I3 => my_full(1),
      O => \my_empty[4]_i_1__0_n_0\
    );
\my_empty[4]_i_2__4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00411400"
    )
        port map (
      I0 => my_empty(1),
      I1 => wr_ptr(1),
      I2 => rd_ptr(1),
      I3 => rd_ptr(0),
      I4 => wr_ptr(0),
      O => \my_empty[4]_i_2__4_n_0\
    );
\my_empty_inst__19\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \my_empty_reg[4]_rep_n_0\,
      O => my_empty(4)
    );
\my_empty_inst__20\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \^my_empty_reg[4]_0\,
      O => \^my_empty_reg[4]_1\(0)
    );
\my_empty_inst__21\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \^my_empty_reg[4]_0\,
      O => my_empty(2)
    );
\my_empty_inst__22\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \^my_empty_reg[4]_0\,
      O => my_empty(1)
    );
\my_empty_inst_rep__4\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \my_empty_reg[4]_rep__0_n_0\,
      O => \my_empty_inst_rep__4_n_0\
    );
\my_empty_reg[4]\: unisim.vcomponents.FDSE
     port map (
      C => \rd_ptr_timing_reg[1]_0\,
      CE => \my_empty[4]_i_1__0_n_0\,
      D => \my_empty[4]_i_2__4_n_0\,
      Q => \^my_empty_reg[4]_0\,
      S => ififo_rst
    );
\my_empty_reg[4]_rep\: unisim.vcomponents.FDSE
     port map (
      C => \rd_ptr_timing_reg[1]_0\,
      CE => \my_empty[4]_i_1__0_n_0\,
      D => \my_empty[4]_i_2__4_n_0\,
      Q => \my_empty_reg[4]_rep_n_0\,
      S => ififo_rst
    );
\my_empty_reg[4]_rep__0\: unisim.vcomponents.FDSE
     port map (
      C => \rd_ptr_timing_reg[1]_0\,
      CE => \my_empty[4]_i_1__0_n_0\,
      D => \my_empty[4]_i_2__4_n_0\,
      Q => \my_empty_reg[4]_rep__0_n_0\,
      S => ififo_rst
    );
\my_full[0]_i_1__4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAEAABAAAA2AA8"
    )
        port map (
      I0 => my_full(0),
      I1 => \my_full_reg[1]_1\,
      I2 => \my_full_reg[1]_0\,
      I3 => my_full(1),
      I4 => my_empty(1),
      I5 => \my_full[1]_i_2__4_n_0\,
      O => \my_full[0]_i_1__4_n_0\
    );
\my_full[1]_i_1__4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"F0F1F070"
    )
        port map (
      I0 => \my_full_reg[1]_1\,
      I1 => \my_full_reg[1]_0\,
      I2 => my_full(1),
      I3 => my_empty(1),
      I4 => \my_full[1]_i_2__4_n_0\,
      O => \my_full[1]_i_1__4_n_0\
    );
\my_full[1]_i_2__4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00411400"
    )
        port map (
      I0 => my_full(1),
      I1 => rd_ptr(1),
      I2 => wr_ptr(1),
      I3 => wr_ptr(0),
      I4 => rd_ptr(0),
      O => \my_full[1]_i_2__4_n_0\
    );
\my_full_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \rd_ptr_timing_reg[1]_0\,
      CE => '1',
      D => \my_full[0]_i_1__4_n_0\,
      Q => my_full(0),
      R => ififo_rst
    );
\my_full_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \rd_ptr_timing_reg[1]_0\,
      CE => '1',
      D => \my_full[1]_i_1__4_n_0\,
      Q => my_full(1),
      R => ififo_rst
    );
\rd_ptr[0]_i_1__4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"D2"
    )
        port map (
      I0 => \my_full_reg[1]_1\,
      I1 => my_empty(1),
      I2 => rd_ptr(0),
      O => \rd_ptr[0]_i_1__4_n_0\
    );
\rd_ptr[1]_i_1__4\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F708"
    )
        port map (
      I0 => rd_ptr(0),
      I1 => \my_full_reg[1]_1\,
      I2 => my_empty(1),
      I3 => rd_ptr(1),
      O => \rd_ptr[1]_i_1__4_n_0\
    );
\rd_ptr_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \rd_ptr_timing_reg[1]_0\,
      CE => '1',
      D => \rd_ptr[0]_i_1__4_n_0\,
      Q => rd_ptr(0),
      R => ififo_rst
    );
\rd_ptr_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \rd_ptr_timing_reg[1]_0\,
      CE => '1',
      D => \rd_ptr[1]_i_1__4_n_0\,
      Q => rd_ptr(1),
      R => ififo_rst
    );
\rd_ptr_timing[0]_i_1__10\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F704"
    )
        port map (
      I0 => rd_ptr(0),
      I1 => \my_full_reg[1]_1\,
      I2 => my_empty(1),
      I3 => rd_ptr_timing(0),
      O => \rd_ptr_timing[0]_i_1__10_n_0\
    );
\rd_ptr_timing[1]_i_1__10\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FF6F0060"
    )
        port map (
      I0 => rd_ptr(0),
      I1 => rd_ptr(1),
      I2 => \my_full_reg[1]_1\,
      I3 => my_empty(1),
      I4 => rd_ptr_timing(1),
      O => \rd_ptr_timing[1]_i_1__10_n_0\
    );
\rd_ptr_timing_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \rd_ptr_timing_reg[1]_0\,
      CE => '1',
      D => \rd_ptr_timing[0]_i_1__10_n_0\,
      Q => rd_ptr_timing(0),
      R => ififo_rst
    );
\rd_ptr_timing_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \rd_ptr_timing_reg[1]_0\,
      CE => '1',
      D => \rd_ptr_timing[1]_i_1__10_n_0\,
      Q => rd_ptr_timing(1),
      R => ififo_rst
    );
\wr_ptr[0]_i_1__10\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FECE0131"
    )
        port map (
      I0 => my_full(1),
      I1 => \my_full_reg[1]_0\,
      I2 => \my_full_reg[1]_1\,
      I3 => my_empty(1),
      I4 => wr_ptr(0),
      O => \wr_ptr[0]_i_1__10_n_0\
    );
\wr_ptr[1]_i_1__10\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFDF5FD00020A02"
    )
        port map (
      I0 => wr_ptr(0),
      I1 => my_full(1),
      I2 => \my_full_reg[1]_0\,
      I3 => \my_full_reg[1]_1\,
      I4 => my_empty(1),
      I5 => wr_ptr(1),
      O => \wr_ptr[1]_i_1__10_n_0\
    );
\wr_ptr[1]_i_3__2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \my_full_reg[1]_0\,
      I1 => \^my_empty_reg[4]_1\(0),
      O => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]\
    );
\wr_ptr_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \rd_ptr_timing_reg[1]_0\,
      CE => '1',
      D => \wr_ptr[0]_i_1__10_n_0\,
      Q => wr_ptr(0),
      R => ififo_rst
    );
\wr_ptr_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \rd_ptr_timing_reg[1]_0\,
      CE => '1',
      D => \wr_ptr[1]_i_1__10_n_0\,
      Q => wr_ptr(1),
      R => ififo_rst
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mig_mig_7series_v4_2_ddr_if_post_fifo_20 is
  port (
    \my_empty_reg[4]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]\ : out STD_LOGIC;
    ififo_rst : in STD_LOGIC;
    \rd_ptr_reg[1]_0\ : in STD_LOGIC;
    \my_full_reg[1]_0\ : in STD_LOGIC;
    \my_full_reg[1]_1\ : in STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 67 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of mig_mig_7series_v4_2_ddr_if_post_fifo_20 : entity is "mig_7series_v4_2_ddr_if_post_fifo";
end mig_mig_7series_v4_2_ddr_if_post_fifo_20;

architecture STRUCTURE of mig_mig_7series_v4_2_ddr_if_post_fifo_20 is
  signal mem_out : STD_LOGIC_VECTOR ( 79 downto 8 );
  signal mem_reg_0_3_60_65_n_4 : STD_LOGIC;
  signal mem_reg_0_3_60_65_n_5 : STD_LOGIC;
  signal mem_reg_0_3_6_11_n_0 : STD_LOGIC;
  signal mem_reg_0_3_6_11_n_1 : STD_LOGIC;
  signal my_empty : STD_LOGIC_VECTOR ( 4 downto 1 );
  signal \my_empty[4]_i_1_n_0\ : STD_LOGIC;
  signal \my_empty[4]_i_2__3_n_0\ : STD_LOGIC;
  signal \my_empty_inst_rep__3_n_0\ : STD_LOGIC;
  signal \^my_empty_reg[4]_0\ : STD_LOGIC;
  signal \my_empty_reg[4]_rep__0_n_0\ : STD_LOGIC;
  signal \my_empty_reg[4]_rep_n_0\ : STD_LOGIC;
  signal my_full : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \my_full[0]_i_1__3_n_0\ : STD_LOGIC;
  signal \my_full[1]_i_1__3_n_0\ : STD_LOGIC;
  signal \my_full[1]_i_2__3_n_0\ : STD_LOGIC;
  signal rd_ptr : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \rd_ptr[0]_i_1__3_n_0\ : STD_LOGIC;
  signal \rd_ptr[1]_i_1__3_n_0\ : STD_LOGIC;
  signal rd_ptr_timing : STD_LOGIC_VECTOR ( 1 downto 0 );
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of rd_ptr_timing : signal is "true";
  attribute syn_maxfan : string;
  attribute syn_maxfan of rd_ptr_timing : signal is "10";
  signal \rd_ptr_timing[0]_i_1__8_n_0\ : STD_LOGIC;
  signal \rd_ptr_timing[1]_i_1__8_n_0\ : STD_LOGIC;
  signal wr_en : STD_LOGIC;
  attribute MAX_FANOUT : string;
  attribute MAX_FANOUT of wr_en : signal is "40";
  attribute RTL_MAX_FANOUT : string;
  attribute RTL_MAX_FANOUT of wr_en : signal is "found";
  attribute syn_maxfan of wr_en : signal is "10";
  signal wr_ptr : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \wr_ptr[0]_i_1__8_n_0\ : STD_LOGIC;
  signal \wr_ptr[1]_i_1__8_n_0\ : STD_LOGIC;
  signal NLW_mem_reg_0_3_12_17_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_3_18_23_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_3_24_29_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_3_30_35_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_3_36_41_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_3_42_47_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_3_48_53_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_3_54_59_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_3_60_65_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_3_6_11_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_3_72_77_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_3_78_79_DOB_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_3_78_79_DOC_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_3_78_79_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \app_rd_data[0]_INST_0\ : label is "soft_lutpair946";
  attribute SOFT_HLUTNM of \app_rd_data[128]_INST_0\ : label is "soft_lutpair955";
  attribute SOFT_HLUTNM of \app_rd_data[129]_INST_0\ : label is "soft_lutpair950";
  attribute SOFT_HLUTNM of \app_rd_data[130]_INST_0\ : label is "soft_lutpair944";
  attribute SOFT_HLUTNM of \app_rd_data[131]_INST_0\ : label is "soft_lutpair953";
  attribute SOFT_HLUTNM of \app_rd_data[132]_INST_0\ : label is "soft_lutpair948";
  attribute SOFT_HLUTNM of \app_rd_data[133]_INST_0\ : label is "soft_lutpair943";
  attribute SOFT_HLUTNM of \app_rd_data[134]_INST_0\ : label is "soft_lutpair951";
  attribute SOFT_HLUTNM of \app_rd_data[135]_INST_0\ : label is "soft_lutpair942";
  attribute SOFT_HLUTNM of \app_rd_data[192]_INST_0\ : label is "soft_lutpair969";
  attribute SOFT_HLUTNM of \app_rd_data[193]_INST_0\ : label is "soft_lutpair969";
  attribute SOFT_HLUTNM of \app_rd_data[194]_INST_0\ : label is "soft_lutpair959";
  attribute SOFT_HLUTNM of \app_rd_data[195]_INST_0\ : label is "soft_lutpair967";
  attribute SOFT_HLUTNM of \app_rd_data[196]_INST_0\ : label is "soft_lutpair966";
  attribute SOFT_HLUTNM of \app_rd_data[197]_INST_0\ : label is "soft_lutpair957";
  attribute SOFT_HLUTNM of \app_rd_data[198]_INST_0\ : label is "soft_lutpair963";
  attribute SOFT_HLUTNM of \app_rd_data[199]_INST_0\ : label is "soft_lutpair954";
  attribute SOFT_HLUTNM of \app_rd_data[1]_INST_0\ : label is "soft_lutpair955";
  attribute SOFT_HLUTNM of \app_rd_data[256]_INST_0\ : label is "soft_lutpair950";
  attribute SOFT_HLUTNM of \app_rd_data[257]_INST_0\ : label is "soft_lutpair945";
  attribute SOFT_HLUTNM of \app_rd_data[258]_INST_0\ : label is "soft_lutpair953";
  attribute SOFT_HLUTNM of \app_rd_data[259]_INST_0\ : label is "soft_lutpair946";
  attribute SOFT_HLUTNM of \app_rd_data[260]_INST_0\ : label is "soft_lutpair943";
  attribute SOFT_HLUTNM of \app_rd_data[261]_INST_0\ : label is "soft_lutpair952";
  attribute SOFT_HLUTNM of \app_rd_data[262]_INST_0\ : label is "soft_lutpair947";
  attribute SOFT_HLUTNM of \app_rd_data[263]_INST_0\ : label is "soft_lutpair951";
  attribute SOFT_HLUTNM of \app_rd_data[2]_INST_0\ : label is "soft_lutpair949";
  attribute SOFT_HLUTNM of \app_rd_data[320]_INST_0\ : label is "soft_lutpair970";
  attribute SOFT_HLUTNM of \app_rd_data[321]_INST_0\ : label is "soft_lutpair959";
  attribute SOFT_HLUTNM of \app_rd_data[322]_INST_0\ : label is "soft_lutpair968";
  attribute SOFT_HLUTNM of \app_rd_data[323]_INST_0\ : label is "soft_lutpair965";
  attribute SOFT_HLUTNM of \app_rd_data[324]_INST_0\ : label is "soft_lutpair957";
  attribute SOFT_HLUTNM of \app_rd_data[325]_INST_0\ : label is "soft_lutpair963";
  attribute SOFT_HLUTNM of \app_rd_data[326]_INST_0\ : label is "soft_lutpair962";
  attribute SOFT_HLUTNM of \app_rd_data[327]_INST_0\ : label is "soft_lutpair961";
  attribute SOFT_HLUTNM of \app_rd_data[384]_INST_0\ : label is "soft_lutpair945";
  attribute SOFT_HLUTNM of \app_rd_data[385]_INST_0\ : label is "soft_lutpair939";
  attribute SOFT_HLUTNM of \app_rd_data[386]_INST_0\ : label is "soft_lutpair949";
  attribute SOFT_HLUTNM of \app_rd_data[387]_INST_0\ : label is "soft_lutpair939";
  attribute SOFT_HLUTNM of \app_rd_data[388]_INST_0\ : label is "soft_lutpair952";
  attribute SOFT_HLUTNM of \app_rd_data[389]_INST_0\ : label is "soft_lutpair948";
  attribute SOFT_HLUTNM of \app_rd_data[390]_INST_0\ : label is "soft_lutpair942";
  attribute SOFT_HLUTNM of \app_rd_data[391]_INST_0\ : label is "soft_lutpair947";
  attribute SOFT_HLUTNM of \app_rd_data[3]_INST_0\ : label is "soft_lutpair944";
  attribute SOFT_HLUTNM of \app_rd_data[448]_INST_0\ : label is "soft_lutpair960";
  attribute SOFT_HLUTNM of \app_rd_data[449]_INST_0\ : label is "soft_lutpair968";
  attribute SOFT_HLUTNM of \app_rd_data[450]_INST_0\ : label is "soft_lutpair967";
  attribute SOFT_HLUTNM of \app_rd_data[451]_INST_0\ : label is "soft_lutpair958";
  attribute SOFT_HLUTNM of \app_rd_data[452]_INST_0\ : label is "soft_lutpair964";
  attribute SOFT_HLUTNM of \app_rd_data[453]_INST_0\ : label is "soft_lutpair956";
  attribute SOFT_HLUTNM of \app_rd_data[454]_INST_0\ : label is "soft_lutpair954";
  attribute SOFT_HLUTNM of \app_rd_data[455]_INST_0\ : label is "soft_lutpair961";
  attribute SOFT_HLUTNM of \app_rd_data[4]_INST_0\ : label is "soft_lutpair941";
  attribute SOFT_HLUTNM of \app_rd_data[5]_INST_0\ : label is "soft_lutpair941";
  attribute SOFT_HLUTNM of \app_rd_data[64]_INST_0\ : label is "soft_lutpair960";
  attribute SOFT_HLUTNM of \app_rd_data[65]_INST_0\ : label is "soft_lutpair970";
  attribute SOFT_HLUTNM of \app_rd_data[66]_INST_0\ : label is "soft_lutpair965";
  attribute SOFT_HLUTNM of \app_rd_data[67]_INST_0\ : label is "soft_lutpair958";
  attribute SOFT_HLUTNM of \app_rd_data[68]_INST_0\ : label is "soft_lutpair966";
  attribute SOFT_HLUTNM of \app_rd_data[69]_INST_0\ : label is "soft_lutpair964";
  attribute SOFT_HLUTNM of \app_rd_data[6]_INST_0\ : label is "soft_lutpair940";
  attribute SOFT_HLUTNM of \app_rd_data[70]_INST_0\ : label is "soft_lutpair956";
  attribute SOFT_HLUTNM of \app_rd_data[71]_INST_0\ : label is "soft_lutpair962";
  attribute SOFT_HLUTNM of \app_rd_data[7]_INST_0\ : label is "soft_lutpair940";
  attribute METHODOLOGY_DRC_VIOS : string;
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_3_12_17 : label is "";
  attribute RTL_RAM_BITS : integer;
  attribute RTL_RAM_BITS of mem_reg_0_3_12_17 : label is 320;
  attribute RTL_RAM_NAME : string;
  attribute RTL_RAM_NAME of mem_reg_0_3_12_17 : label is "dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem";
  attribute ram_addr_begin : integer;
  attribute ram_addr_begin of mem_reg_0_3_12_17 : label is 0;
  attribute ram_addr_end : integer;
  attribute ram_addr_end of mem_reg_0_3_12_17 : label is 3;
  attribute ram_offset : integer;
  attribute ram_offset of mem_reg_0_3_12_17 : label is 0;
  attribute ram_slice_begin : integer;
  attribute ram_slice_begin of mem_reg_0_3_12_17 : label is 12;
  attribute ram_slice_end : integer;
  attribute ram_slice_end of mem_reg_0_3_12_17 : label is 17;
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_3_18_23 : label is "";
  attribute RTL_RAM_BITS of mem_reg_0_3_18_23 : label is 320;
  attribute RTL_RAM_NAME of mem_reg_0_3_18_23 : label is "dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem";
  attribute ram_addr_begin of mem_reg_0_3_18_23 : label is 0;
  attribute ram_addr_end of mem_reg_0_3_18_23 : label is 3;
  attribute ram_offset of mem_reg_0_3_18_23 : label is 0;
  attribute ram_slice_begin of mem_reg_0_3_18_23 : label is 18;
  attribute ram_slice_end of mem_reg_0_3_18_23 : label is 23;
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_3_24_29 : label is "";
  attribute RTL_RAM_BITS of mem_reg_0_3_24_29 : label is 320;
  attribute RTL_RAM_NAME of mem_reg_0_3_24_29 : label is "dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem";
  attribute ram_addr_begin of mem_reg_0_3_24_29 : label is 0;
  attribute ram_addr_end of mem_reg_0_3_24_29 : label is 3;
  attribute ram_offset of mem_reg_0_3_24_29 : label is 0;
  attribute ram_slice_begin of mem_reg_0_3_24_29 : label is 24;
  attribute ram_slice_end of mem_reg_0_3_24_29 : label is 29;
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_3_30_35 : label is "";
  attribute RTL_RAM_BITS of mem_reg_0_3_30_35 : label is 320;
  attribute RTL_RAM_NAME of mem_reg_0_3_30_35 : label is "dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem";
  attribute ram_addr_begin of mem_reg_0_3_30_35 : label is 0;
  attribute ram_addr_end of mem_reg_0_3_30_35 : label is 3;
  attribute ram_offset of mem_reg_0_3_30_35 : label is 0;
  attribute ram_slice_begin of mem_reg_0_3_30_35 : label is 30;
  attribute ram_slice_end of mem_reg_0_3_30_35 : label is 35;
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_3_36_41 : label is "";
  attribute RTL_RAM_BITS of mem_reg_0_3_36_41 : label is 320;
  attribute RTL_RAM_NAME of mem_reg_0_3_36_41 : label is "dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem";
  attribute ram_addr_begin of mem_reg_0_3_36_41 : label is 0;
  attribute ram_addr_end of mem_reg_0_3_36_41 : label is 3;
  attribute ram_offset of mem_reg_0_3_36_41 : label is 0;
  attribute ram_slice_begin of mem_reg_0_3_36_41 : label is 36;
  attribute ram_slice_end of mem_reg_0_3_36_41 : label is 41;
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_3_42_47 : label is "";
  attribute RTL_RAM_BITS of mem_reg_0_3_42_47 : label is 320;
  attribute RTL_RAM_NAME of mem_reg_0_3_42_47 : label is "dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem";
  attribute ram_addr_begin of mem_reg_0_3_42_47 : label is 0;
  attribute ram_addr_end of mem_reg_0_3_42_47 : label is 3;
  attribute ram_offset of mem_reg_0_3_42_47 : label is 0;
  attribute ram_slice_begin of mem_reg_0_3_42_47 : label is 42;
  attribute ram_slice_end of mem_reg_0_3_42_47 : label is 47;
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_3_48_53 : label is "";
  attribute RTL_RAM_BITS of mem_reg_0_3_48_53 : label is 320;
  attribute RTL_RAM_NAME of mem_reg_0_3_48_53 : label is "dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem";
  attribute ram_addr_begin of mem_reg_0_3_48_53 : label is 0;
  attribute ram_addr_end of mem_reg_0_3_48_53 : label is 3;
  attribute ram_offset of mem_reg_0_3_48_53 : label is 0;
  attribute ram_slice_begin of mem_reg_0_3_48_53 : label is 48;
  attribute ram_slice_end of mem_reg_0_3_48_53 : label is 53;
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_3_54_59 : label is "";
  attribute RTL_RAM_BITS of mem_reg_0_3_54_59 : label is 320;
  attribute RTL_RAM_NAME of mem_reg_0_3_54_59 : label is "dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem";
  attribute ram_addr_begin of mem_reg_0_3_54_59 : label is 0;
  attribute ram_addr_end of mem_reg_0_3_54_59 : label is 3;
  attribute ram_offset of mem_reg_0_3_54_59 : label is 0;
  attribute ram_slice_begin of mem_reg_0_3_54_59 : label is 54;
  attribute ram_slice_end of mem_reg_0_3_54_59 : label is 59;
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_3_60_65 : label is "";
  attribute RTL_RAM_BITS of mem_reg_0_3_60_65 : label is 320;
  attribute RTL_RAM_NAME of mem_reg_0_3_60_65 : label is "dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem";
  attribute ram_addr_begin of mem_reg_0_3_60_65 : label is 0;
  attribute ram_addr_end of mem_reg_0_3_60_65 : label is 3;
  attribute ram_offset of mem_reg_0_3_60_65 : label is 0;
  attribute ram_slice_begin of mem_reg_0_3_60_65 : label is 60;
  attribute ram_slice_end of mem_reg_0_3_60_65 : label is 65;
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_3_6_11 : label is "";
  attribute RTL_RAM_BITS of mem_reg_0_3_6_11 : label is 320;
  attribute RTL_RAM_NAME of mem_reg_0_3_6_11 : label is "dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem";
  attribute ram_addr_begin of mem_reg_0_3_6_11 : label is 0;
  attribute ram_addr_end of mem_reg_0_3_6_11 : label is 3;
  attribute ram_offset of mem_reg_0_3_6_11 : label is 0;
  attribute ram_slice_begin of mem_reg_0_3_6_11 : label is 6;
  attribute ram_slice_end of mem_reg_0_3_6_11 : label is 11;
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_3_72_77 : label is "";
  attribute RTL_RAM_BITS of mem_reg_0_3_72_77 : label is 320;
  attribute RTL_RAM_NAME of mem_reg_0_3_72_77 : label is "dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem";
  attribute ram_addr_begin of mem_reg_0_3_72_77 : label is 0;
  attribute ram_addr_end of mem_reg_0_3_72_77 : label is 3;
  attribute ram_offset of mem_reg_0_3_72_77 : label is 0;
  attribute ram_slice_begin of mem_reg_0_3_72_77 : label is 72;
  attribute ram_slice_end of mem_reg_0_3_72_77 : label is 77;
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_3_78_79 : label is "";
  attribute RTL_RAM_BITS of mem_reg_0_3_78_79 : label is 320;
  attribute RTL_RAM_NAME of mem_reg_0_3_78_79 : label is "dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem";
  attribute ram_addr_begin of mem_reg_0_3_78_79 : label is 0;
  attribute ram_addr_end of mem_reg_0_3_78_79 : label is 3;
  attribute ram_offset of mem_reg_0_3_78_79 : label is 0;
  attribute ram_slice_begin of mem_reg_0_3_78_79 : label is 78;
  attribute ram_slice_end of mem_reg_0_3_78_79 : label is 79;
  attribute SOFT_HLUTNM of \my_empty_inst__16\ : label is "soft_lutpair971";
  attribute SOFT_HLUTNM of \my_empty_inst__17\ : label is "soft_lutpair971";
  attribute IS_FANOUT_CONSTRAINED : integer;
  attribute IS_FANOUT_CONSTRAINED of \my_empty_inst_rep__3\ : label is 1;
  attribute ORIG_CELL_NAME : string;
  attribute ORIG_CELL_NAME of \my_empty_reg[4]\ : label is "my_empty_reg[4]";
  attribute ORIG_CELL_NAME of \my_empty_reg[4]_rep\ : label is "my_empty_reg[4]";
  attribute ORIG_CELL_NAME of \my_empty_reg[4]_rep__0\ : label is "my_empty_reg[4]";
  attribute SOFT_HLUTNM of \rd_ptr[0]_i_1__3\ : label is "soft_lutpair938";
  attribute SOFT_HLUTNM of \rd_ptr[1]_i_1__3\ : label is "soft_lutpair938";
  attribute syn_maxfan of \rd_ptr_reg[0]\ : label is "10";
  attribute syn_maxfan of \rd_ptr_reg[1]\ : label is "10";
  attribute KEEP : string;
  attribute KEEP of \rd_ptr_timing_reg[0]\ : label is "yes";
  attribute syn_maxfan of \rd_ptr_timing_reg[0]\ : label is "10";
  attribute KEEP of \rd_ptr_timing_reg[1]\ : label is "yes";
  attribute syn_maxfan of \rd_ptr_timing_reg[1]\ : label is "10";
  attribute syn_maxfan of \wr_ptr_reg[0]\ : label is "10";
  attribute syn_maxfan of \wr_ptr_reg[1]\ : label is "10";
begin
  \my_empty_reg[4]_0\ <= \^my_empty_reg[4]_0\;
\app_rd_data[0]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(2),
      I1 => \my_empty_inst_rep__3_n_0\,
      I2 => mem_out(8),
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]\
    );
\app_rd_data[128]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(4),
      I1 => \my_empty_inst_rep__3_n_0\,
      I2 => mem_out(10),
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]\
    );
\app_rd_data[129]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(12),
      I1 => \my_empty_inst_rep__3_n_0\,
      I2 => mem_out(18),
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]\
    );
\app_rd_data[130]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(20),
      I1 => \my_empty_inst_rep__3_n_0\,
      I2 => mem_out(26),
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]\
    );
\app_rd_data[131]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(28),
      I1 => \my_empty_inst_rep__3_n_0\,
      I2 => mem_out(34),
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]\
    );
\app_rd_data[132]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(36),
      I1 => my_empty(4),
      I2 => mem_out(42),
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]\
    );
\app_rd_data[133]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(44),
      I1 => my_empty(4),
      I2 => mem_out(50),
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]\
    );
\app_rd_data[134]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(52),
      I1 => my_empty(4),
      I2 => mem_out(58),
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]\
    );
\app_rd_data[135]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(62),
      I1 => my_empty(4),
      I2 => mem_out(74),
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]\
    );
\app_rd_data[192]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(5),
      I1 => \my_empty_inst_rep__3_n_0\,
      I2 => mem_out(11),
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]\
    );
\app_rd_data[193]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(13),
      I1 => \my_empty_inst_rep__3_n_0\,
      I2 => mem_out(19),
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]\
    );
\app_rd_data[194]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(21),
      I1 => \my_empty_inst_rep__3_n_0\,
      I2 => mem_out(27),
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]\
    );
\app_rd_data[195]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(29),
      I1 => \my_empty_inst_rep__3_n_0\,
      I2 => mem_out(35),
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]\
    );
\app_rd_data[196]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(37),
      I1 => my_empty(4),
      I2 => mem_out(43),
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]\
    );
\app_rd_data[197]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(45),
      I1 => my_empty(4),
      I2 => mem_out(51),
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]\
    );
\app_rd_data[198]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(53),
      I1 => my_empty(4),
      I2 => mem_out(59),
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]\
    );
\app_rd_data[199]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(63),
      I1 => my_empty(4),
      I2 => mem_out(75),
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]\
    );
\app_rd_data[1]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(10),
      I1 => \my_empty_inst_rep__3_n_0\,
      I2 => mem_out(16),
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]\
    );
\app_rd_data[256]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(6),
      I1 => \my_empty_inst_rep__3_n_0\,
      I2 => mem_out(12),
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]\
    );
\app_rd_data[257]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(14),
      I1 => \my_empty_inst_rep__3_n_0\,
      I2 => mem_out(20),
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]\
    );
\app_rd_data[258]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(22),
      I1 => \my_empty_inst_rep__3_n_0\,
      I2 => mem_out(28),
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]\
    );
\app_rd_data[259]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(30),
      I1 => \my_empty_inst_rep__3_n_0\,
      I2 => mem_out(36),
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]\
    );
\app_rd_data[260]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(38),
      I1 => my_empty(4),
      I2 => mem_out(44),
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]\
    );
\app_rd_data[261]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(46),
      I1 => my_empty(4),
      I2 => mem_out(52),
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]\
    );
\app_rd_data[262]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(54),
      I1 => my_empty(4),
      I2 => mem_out(60),
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]\
    );
\app_rd_data[263]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(64),
      I1 => my_empty(4),
      I2 => mem_out(76),
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]\
    );
\app_rd_data[2]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(18),
      I1 => \my_empty_inst_rep__3_n_0\,
      I2 => mem_out(24),
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]\
    );
\app_rd_data[320]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(7),
      I1 => \my_empty_inst_rep__3_n_0\,
      I2 => mem_out(13),
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]\
    );
\app_rd_data[321]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(15),
      I1 => \my_empty_inst_rep__3_n_0\,
      I2 => mem_out(21),
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]\
    );
\app_rd_data[322]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(23),
      I1 => \my_empty_inst_rep__3_n_0\,
      I2 => mem_out(29),
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]\
    );
\app_rd_data[323]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(31),
      I1 => \my_empty_inst_rep__3_n_0\,
      I2 => mem_out(37),
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]\
    );
\app_rd_data[324]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(39),
      I1 => my_empty(4),
      I2 => mem_out(45),
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]\
    );
\app_rd_data[325]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(47),
      I1 => my_empty(4),
      I2 => mem_out(53),
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]\
    );
\app_rd_data[326]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(55),
      I1 => my_empty(4),
      I2 => mem_out(61),
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]\
    );
\app_rd_data[327]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(65),
      I1 => my_empty(4),
      I2 => mem_out(77),
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]\
    );
\app_rd_data[384]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(8),
      I1 => \my_empty_inst_rep__3_n_0\,
      I2 => mem_out(14),
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]\
    );
\app_rd_data[385]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(16),
      I1 => \my_empty_inst_rep__3_n_0\,
      I2 => mem_out(22),
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]\
    );
\app_rd_data[386]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(24),
      I1 => \my_empty_inst_rep__3_n_0\,
      I2 => mem_out(30),
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]\
    );
\app_rd_data[387]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(32),
      I1 => \my_empty_inst_rep__3_n_0\,
      I2 => mem_out(38),
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]\
    );
\app_rd_data[388]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(40),
      I1 => my_empty(4),
      I2 => mem_out(46),
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]\
    );
\app_rd_data[389]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(48),
      I1 => my_empty(4),
      I2 => mem_out(54),
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]\
    );
\app_rd_data[390]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(56),
      I1 => my_empty(4),
      I2 => mem_out(62),
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]\
    );
\app_rd_data[391]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(66),
      I1 => my_empty(4),
      I2 => mem_out(78),
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]\
    );
\app_rd_data[3]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(26),
      I1 => \my_empty_inst_rep__3_n_0\,
      I2 => mem_out(32),
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]\
    );
\app_rd_data[448]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(9),
      I1 => \my_empty_inst_rep__3_n_0\,
      I2 => mem_out(15),
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]\
    );
\app_rd_data[449]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(17),
      I1 => \my_empty_inst_rep__3_n_0\,
      I2 => mem_out(23),
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]\
    );
\app_rd_data[450]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(25),
      I1 => \my_empty_inst_rep__3_n_0\,
      I2 => mem_out(31),
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]\
    );
\app_rd_data[451]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(33),
      I1 => \my_empty_inst_rep__3_n_0\,
      I2 => mem_out(39),
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]\
    );
\app_rd_data[452]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(41),
      I1 => my_empty(4),
      I2 => mem_out(47),
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]\
    );
\app_rd_data[453]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(49),
      I1 => my_empty(4),
      I2 => mem_out(55),
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]\
    );
\app_rd_data[454]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(57),
      I1 => my_empty(4),
      I2 => mem_out(63),
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]\
    );
\app_rd_data[455]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(67),
      I1 => my_empty(4),
      I2 => mem_out(79),
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]\
    );
\app_rd_data[4]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(34),
      I1 => my_empty(4),
      I2 => mem_out(40),
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]\
    );
\app_rd_data[5]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(42),
      I1 => my_empty(4),
      I2 => mem_out(48),
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]\
    );
\app_rd_data[64]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(3),
      I1 => \my_empty_inst_rep__3_n_0\,
      I2 => mem_out(9),
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]\
    );
\app_rd_data[65]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(11),
      I1 => \my_empty_inst_rep__3_n_0\,
      I2 => mem_out(17),
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]\
    );
\app_rd_data[66]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(19),
      I1 => \my_empty_inst_rep__3_n_0\,
      I2 => mem_out(25),
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]\
    );
\app_rd_data[67]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(27),
      I1 => \my_empty_inst_rep__3_n_0\,
      I2 => mem_out(33),
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]\
    );
\app_rd_data[68]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(35),
      I1 => my_empty(4),
      I2 => mem_out(41),
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]\
    );
\app_rd_data[69]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(43),
      I1 => my_empty(4),
      I2 => mem_out(49),
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]\
    );
\app_rd_data[6]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(50),
      I1 => my_empty(4),
      I2 => mem_out(56),
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]\
    );
\app_rd_data[70]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(51),
      I1 => my_empty(4),
      I2 => mem_out(57),
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]\
    );
\app_rd_data[71]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(61),
      I1 => my_empty(4),
      I2 => mem_out(73),
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]\
    );
\app_rd_data[7]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(60),
      I1 => my_empty(4),
      I2 => mem_out(72),
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]\
    );
mem_reg_0_3_12_17: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 2) => B"000",
      ADDRA(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRB(4 downto 2) => B"000",
      ADDRB(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRC(4 downto 2) => B"000",
      ADDRC(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRD(4 downto 2) => B"000",
      ADDRD(1 downto 0) => wr_ptr(1 downto 0),
      DIA(1 downto 0) => Q(7 downto 6),
      DIB(1 downto 0) => Q(9 downto 8),
      DIC(1 downto 0) => Q(11 downto 10),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => mem_out(13 downto 12),
      DOB(1 downto 0) => mem_out(15 downto 14),
      DOC(1 downto 0) => mem_out(17 downto 16),
      DOD(1 downto 0) => NLW_mem_reg_0_3_12_17_DOD_UNCONNECTED(1 downto 0),
      WCLK => \rd_ptr_reg[1]_0\,
      WE => wr_en
    );
mem_reg_0_3_18_23: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 2) => B"000",
      ADDRA(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRB(4 downto 2) => B"000",
      ADDRB(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRC(4 downto 2) => B"000",
      ADDRC(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRD(4 downto 2) => B"000",
      ADDRD(1 downto 0) => wr_ptr(1 downto 0),
      DIA(1 downto 0) => Q(13 downto 12),
      DIB(1 downto 0) => Q(15 downto 14),
      DIC(1 downto 0) => Q(17 downto 16),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => mem_out(19 downto 18),
      DOB(1 downto 0) => mem_out(21 downto 20),
      DOC(1 downto 0) => mem_out(23 downto 22),
      DOD(1 downto 0) => NLW_mem_reg_0_3_18_23_DOD_UNCONNECTED(1 downto 0),
      WCLK => \rd_ptr_reg[1]_0\,
      WE => wr_en
    );
mem_reg_0_3_24_29: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 2) => B"000",
      ADDRA(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRB(4 downto 2) => B"000",
      ADDRB(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRC(4 downto 2) => B"000",
      ADDRC(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRD(4 downto 2) => B"000",
      ADDRD(1 downto 0) => wr_ptr(1 downto 0),
      DIA(1 downto 0) => Q(19 downto 18),
      DIB(1 downto 0) => Q(21 downto 20),
      DIC(1 downto 0) => Q(23 downto 22),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => mem_out(25 downto 24),
      DOB(1 downto 0) => mem_out(27 downto 26),
      DOC(1 downto 0) => mem_out(29 downto 28),
      DOD(1 downto 0) => NLW_mem_reg_0_3_24_29_DOD_UNCONNECTED(1 downto 0),
      WCLK => \rd_ptr_reg[1]_0\,
      WE => wr_en
    );
mem_reg_0_3_30_35: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 2) => B"000",
      ADDRA(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRB(4 downto 2) => B"000",
      ADDRB(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRC(4 downto 2) => B"000",
      ADDRC(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRD(4 downto 2) => B"000",
      ADDRD(1 downto 0) => wr_ptr(1 downto 0),
      DIA(1 downto 0) => Q(25 downto 24),
      DIB(1 downto 0) => Q(27 downto 26),
      DIC(1 downto 0) => Q(29 downto 28),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => mem_out(31 downto 30),
      DOB(1 downto 0) => mem_out(33 downto 32),
      DOC(1 downto 0) => mem_out(35 downto 34),
      DOD(1 downto 0) => NLW_mem_reg_0_3_30_35_DOD_UNCONNECTED(1 downto 0),
      WCLK => \rd_ptr_reg[1]_0\,
      WE => wr_en
    );
mem_reg_0_3_36_41: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 2) => B"000",
      ADDRA(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRB(4 downto 2) => B"000",
      ADDRB(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRC(4 downto 2) => B"000",
      ADDRC(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRD(4 downto 2) => B"000",
      ADDRD(1 downto 0) => wr_ptr(1 downto 0),
      DIA(1 downto 0) => Q(31 downto 30),
      DIB(1 downto 0) => Q(33 downto 32),
      DIC(1 downto 0) => Q(35 downto 34),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => mem_out(37 downto 36),
      DOB(1 downto 0) => mem_out(39 downto 38),
      DOC(1 downto 0) => mem_out(41 downto 40),
      DOD(1 downto 0) => NLW_mem_reg_0_3_36_41_DOD_UNCONNECTED(1 downto 0),
      WCLK => \rd_ptr_reg[1]_0\,
      WE => wr_en
    );
mem_reg_0_3_42_47: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 2) => B"000",
      ADDRA(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRB(4 downto 2) => B"000",
      ADDRB(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRC(4 downto 2) => B"000",
      ADDRC(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRD(4 downto 2) => B"000",
      ADDRD(1 downto 0) => wr_ptr(1 downto 0),
      DIA(1 downto 0) => Q(37 downto 36),
      DIB(1 downto 0) => Q(39 downto 38),
      DIC(1 downto 0) => Q(41 downto 40),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => mem_out(43 downto 42),
      DOB(1 downto 0) => mem_out(45 downto 44),
      DOC(1 downto 0) => mem_out(47 downto 46),
      DOD(1 downto 0) => NLW_mem_reg_0_3_42_47_DOD_UNCONNECTED(1 downto 0),
      WCLK => \rd_ptr_reg[1]_0\,
      WE => wr_en
    );
mem_reg_0_3_48_53: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 2) => B"000",
      ADDRA(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRB(4 downto 2) => B"000",
      ADDRB(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRC(4 downto 2) => B"000",
      ADDRC(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRD(4 downto 2) => B"000",
      ADDRD(1 downto 0) => wr_ptr(1 downto 0),
      DIA(1 downto 0) => Q(43 downto 42),
      DIB(1 downto 0) => Q(45 downto 44),
      DIC(1 downto 0) => Q(47 downto 46),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => mem_out(49 downto 48),
      DOB(1 downto 0) => mem_out(51 downto 50),
      DOC(1 downto 0) => mem_out(53 downto 52),
      DOD(1 downto 0) => NLW_mem_reg_0_3_48_53_DOD_UNCONNECTED(1 downto 0),
      WCLK => \rd_ptr_reg[1]_0\,
      WE => wr_en
    );
mem_reg_0_3_54_59: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 2) => B"000",
      ADDRA(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRB(4 downto 2) => B"000",
      ADDRB(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRC(4 downto 2) => B"000",
      ADDRC(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRD(4 downto 2) => B"000",
      ADDRD(1 downto 0) => wr_ptr(1 downto 0),
      DIA(1 downto 0) => Q(49 downto 48),
      DIB(1 downto 0) => Q(51 downto 50),
      DIC(1 downto 0) => Q(53 downto 52),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => mem_out(55 downto 54),
      DOB(1 downto 0) => mem_out(57 downto 56),
      DOC(1 downto 0) => mem_out(59 downto 58),
      DOD(1 downto 0) => NLW_mem_reg_0_3_54_59_DOD_UNCONNECTED(1 downto 0),
      WCLK => \rd_ptr_reg[1]_0\,
      WE => wr_en
    );
mem_reg_0_3_60_65: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 2) => B"000",
      ADDRA(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRB(4 downto 2) => B"000",
      ADDRB(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRC(4 downto 2) => B"000",
      ADDRC(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRD(4 downto 2) => B"000",
      ADDRD(1 downto 0) => wr_ptr(1 downto 0),
      DIA(1 downto 0) => Q(55 downto 54),
      DIB(1 downto 0) => Q(57 downto 56),
      DIC(1 downto 0) => Q(59 downto 58),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => mem_out(61 downto 60),
      DOB(1 downto 0) => mem_out(63 downto 62),
      DOC(1) => mem_reg_0_3_60_65_n_4,
      DOC(0) => mem_reg_0_3_60_65_n_5,
      DOD(1 downto 0) => NLW_mem_reg_0_3_60_65_DOD_UNCONNECTED(1 downto 0),
      WCLK => \rd_ptr_reg[1]_0\,
      WE => wr_en
    );
mem_reg_0_3_6_11: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 2) => B"000",
      ADDRA(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRB(4 downto 2) => B"000",
      ADDRB(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRC(4 downto 2) => B"000",
      ADDRC(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRD(4 downto 2) => B"000",
      ADDRD(1 downto 0) => wr_ptr(1 downto 0),
      DIA(1 downto 0) => Q(1 downto 0),
      DIB(1 downto 0) => Q(3 downto 2),
      DIC(1 downto 0) => Q(5 downto 4),
      DID(1 downto 0) => B"00",
      DOA(1) => mem_reg_0_3_6_11_n_0,
      DOA(0) => mem_reg_0_3_6_11_n_1,
      DOB(1 downto 0) => mem_out(9 downto 8),
      DOC(1 downto 0) => mem_out(11 downto 10),
      DOD(1 downto 0) => NLW_mem_reg_0_3_6_11_DOD_UNCONNECTED(1 downto 0),
      WCLK => \rd_ptr_reg[1]_0\,
      WE => wr_en
    );
mem_reg_0_3_6_11_i_1: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0151"
    )
        port map (
      I0 => \my_full_reg[1]_0\,
      I1 => my_full(0),
      I2 => \my_full_reg[1]_1\,
      I3 => my_empty(2),
      O => wr_en
    );
mem_reg_0_3_72_77: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 2) => B"000",
      ADDRA(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRB(4 downto 2) => B"000",
      ADDRB(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRC(4 downto 2) => B"000",
      ADDRC(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRD(4 downto 2) => B"000",
      ADDRD(1 downto 0) => wr_ptr(1 downto 0),
      DIA(1 downto 0) => Q(61 downto 60),
      DIB(1 downto 0) => Q(63 downto 62),
      DIC(1 downto 0) => Q(65 downto 64),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => mem_out(73 downto 72),
      DOB(1 downto 0) => mem_out(75 downto 74),
      DOC(1 downto 0) => mem_out(77 downto 76),
      DOD(1 downto 0) => NLW_mem_reg_0_3_72_77_DOD_UNCONNECTED(1 downto 0),
      WCLK => \rd_ptr_reg[1]_0\,
      WE => wr_en
    );
mem_reg_0_3_78_79: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 2) => B"000",
      ADDRA(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRB(4 downto 2) => B"000",
      ADDRB(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRC(4 downto 2) => B"000",
      ADDRC(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRD(4 downto 2) => B"000",
      ADDRD(1 downto 0) => wr_ptr(1 downto 0),
      DIA(1 downto 0) => Q(67 downto 66),
      DIB(1 downto 0) => B"00",
      DIC(1 downto 0) => B"00",
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => mem_out(79 downto 78),
      DOB(1 downto 0) => NLW_mem_reg_0_3_78_79_DOB_UNCONNECTED(1 downto 0),
      DOC(1 downto 0) => NLW_mem_reg_0_3_78_79_DOC_UNCONNECTED(1 downto 0),
      DOD(1 downto 0) => NLW_mem_reg_0_3_78_79_DOD_UNCONNECTED(1 downto 0),
      WCLK => \rd_ptr_reg[1]_0\,
      WE => wr_en
    );
\my_empty[4]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0018"
    )
        port map (
      I0 => \my_full_reg[1]_1\,
      I1 => \my_full_reg[1]_0\,
      I2 => my_empty(1),
      I3 => my_full(1),
      O => \my_empty[4]_i_1_n_0\
    );
\my_empty[4]_i_2__3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00411400"
    )
        port map (
      I0 => my_empty(1),
      I1 => wr_ptr(1),
      I2 => rd_ptr(1),
      I3 => rd_ptr(0),
      I4 => wr_ptr(0),
      O => \my_empty[4]_i_2__3_n_0\
    );
\my_empty_inst__15\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \my_empty_reg[4]_rep_n_0\,
      O => my_empty(4)
    );
\my_empty_inst__16\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \^my_empty_reg[4]_0\,
      O => my_empty(3)
    );
\my_empty_inst__17\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \^my_empty_reg[4]_0\,
      O => my_empty(2)
    );
\my_empty_inst__18\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \^my_empty_reg[4]_0\,
      O => my_empty(1)
    );
\my_empty_inst_rep__3\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \my_empty_reg[4]_rep__0_n_0\,
      O => \my_empty_inst_rep__3_n_0\
    );
\my_empty_reg[4]\: unisim.vcomponents.FDSE
     port map (
      C => \rd_ptr_reg[1]_0\,
      CE => \my_empty[4]_i_1_n_0\,
      D => \my_empty[4]_i_2__3_n_0\,
      Q => \^my_empty_reg[4]_0\,
      S => ififo_rst
    );
\my_empty_reg[4]_rep\: unisim.vcomponents.FDSE
     port map (
      C => \rd_ptr_reg[1]_0\,
      CE => \my_empty[4]_i_1_n_0\,
      D => \my_empty[4]_i_2__3_n_0\,
      Q => \my_empty_reg[4]_rep_n_0\,
      S => ififo_rst
    );
\my_empty_reg[4]_rep__0\: unisim.vcomponents.FDSE
     port map (
      C => \rd_ptr_reg[1]_0\,
      CE => \my_empty[4]_i_1_n_0\,
      D => \my_empty[4]_i_2__3_n_0\,
      Q => \my_empty_reg[4]_rep__0_n_0\,
      S => ififo_rst
    );
\my_full[0]_i_1__3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAEAABAAAA2AA8"
    )
        port map (
      I0 => my_full(0),
      I1 => \my_full_reg[1]_1\,
      I2 => \my_full_reg[1]_0\,
      I3 => my_full(1),
      I4 => my_empty(1),
      I5 => \my_full[1]_i_2__3_n_0\,
      O => \my_full[0]_i_1__3_n_0\
    );
\my_full[1]_i_1__3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"F0F1F070"
    )
        port map (
      I0 => \my_full_reg[1]_1\,
      I1 => \my_full_reg[1]_0\,
      I2 => my_full(1),
      I3 => my_empty(1),
      I4 => \my_full[1]_i_2__3_n_0\,
      O => \my_full[1]_i_1__3_n_0\
    );
\my_full[1]_i_2__3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00411400"
    )
        port map (
      I0 => my_full(1),
      I1 => rd_ptr(1),
      I2 => wr_ptr(1),
      I3 => wr_ptr(0),
      I4 => rd_ptr(0),
      O => \my_full[1]_i_2__3_n_0\
    );
\my_full_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \rd_ptr_reg[1]_0\,
      CE => '1',
      D => \my_full[0]_i_1__3_n_0\,
      Q => my_full(0),
      R => ififo_rst
    );
\my_full_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \rd_ptr_reg[1]_0\,
      CE => '1',
      D => \my_full[1]_i_1__3_n_0\,
      Q => my_full(1),
      R => ififo_rst
    );
\rd_ptr[0]_i_1__3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"D2"
    )
        port map (
      I0 => \my_full_reg[1]_1\,
      I1 => my_empty(1),
      I2 => rd_ptr(0),
      O => \rd_ptr[0]_i_1__3_n_0\
    );
\rd_ptr[1]_i_1__3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F708"
    )
        port map (
      I0 => rd_ptr(0),
      I1 => \my_full_reg[1]_1\,
      I2 => my_empty(1),
      I3 => rd_ptr(1),
      O => \rd_ptr[1]_i_1__3_n_0\
    );
\rd_ptr_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \rd_ptr_reg[1]_0\,
      CE => '1',
      D => \rd_ptr[0]_i_1__3_n_0\,
      Q => rd_ptr(0),
      R => ififo_rst
    );
\rd_ptr_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \rd_ptr_reg[1]_0\,
      CE => '1',
      D => \rd_ptr[1]_i_1__3_n_0\,
      Q => rd_ptr(1),
      R => ififo_rst
    );
\rd_ptr_timing[0]_i_1__8\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F704"
    )
        port map (
      I0 => rd_ptr(0),
      I1 => \my_full_reg[1]_1\,
      I2 => my_empty(1),
      I3 => rd_ptr_timing(0),
      O => \rd_ptr_timing[0]_i_1__8_n_0\
    );
\rd_ptr_timing[1]_i_1__8\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FF6F0060"
    )
        port map (
      I0 => rd_ptr(0),
      I1 => rd_ptr(1),
      I2 => \my_full_reg[1]_1\,
      I3 => my_empty(1),
      I4 => rd_ptr_timing(1),
      O => \rd_ptr_timing[1]_i_1__8_n_0\
    );
\rd_ptr_timing_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \rd_ptr_reg[1]_0\,
      CE => '1',
      D => \rd_ptr_timing[0]_i_1__8_n_0\,
      Q => rd_ptr_timing(0),
      R => ififo_rst
    );
\rd_ptr_timing_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \rd_ptr_reg[1]_0\,
      CE => '1',
      D => \rd_ptr_timing[1]_i_1__8_n_0\,
      Q => rd_ptr_timing(1),
      R => ififo_rst
    );
\wr_ptr[0]_i_1__8\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FECE0131"
    )
        port map (
      I0 => my_full(1),
      I1 => \my_full_reg[1]_0\,
      I2 => \my_full_reg[1]_1\,
      I3 => my_empty(1),
      I4 => wr_ptr(0),
      O => \wr_ptr[0]_i_1__8_n_0\
    );
\wr_ptr[1]_i_1__8\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFDF5FD00020A02"
    )
        port map (
      I0 => wr_ptr(0),
      I1 => my_full(1),
      I2 => \my_full_reg[1]_0\,
      I3 => \my_full_reg[1]_1\,
      I4 => my_empty(1),
      I5 => wr_ptr(1),
      O => \wr_ptr[1]_i_1__8_n_0\
    );
\wr_ptr[1]_i_5\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \my_full_reg[1]_0\,
      I1 => my_empty(3),
      O => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]\
    );
\wr_ptr_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \rd_ptr_reg[1]_0\,
      CE => '1',
      D => \wr_ptr[0]_i_1__8_n_0\,
      Q => wr_ptr(0),
      R => ififo_rst
    );
\wr_ptr_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \rd_ptr_reg[1]_0\,
      CE => '1',
      D => \wr_ptr[1]_i_1__8_n_0\,
      Q => wr_ptr(1),
      R => ififo_rst
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mig_mig_7series_v4_2_ddr_if_post_fifo_30 is
  port (
    \my_empty_reg[4]_0\ : out STD_LOGIC;
    \my_empty_reg[4]_1\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    \rd_mux_sel_r_reg[1]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[1]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[1]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[1]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[1]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[1]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[1]_5\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[1]_6\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[1]_7\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[1]_8\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[1]_9\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[1]_10\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[1]_11\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[1]_12\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[1]_13\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[1]_14\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[1]_15\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[1]_16\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[1]_17\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[1]_18\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[1]_19\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[1]_20\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[1]_21\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[1]_22\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[1]_23\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[1]_24\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[1]_25\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[1]_26\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[1]_27\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[1]_28\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[1]_29\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[1]_30\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[1]_31\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[1]_32\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[1]_33\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[1]_34\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[1]_35\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[1]_36\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[1]_37\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[1]_38\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[1]_39\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[1]_40\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[1]_41\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[1]_42\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[1]_43\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[1]_44\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[1]_45\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[1]_46\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[1]_47\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[1]_48\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[1]_49\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[1]_50\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[1]_51\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[1]_52\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[1]_53\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[1]_54\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[1]_55\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[1]_56\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[1]_57\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[1]_58\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[1]_59\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[1]_60\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[1]_61\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[1]_62\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_0\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_1\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_2\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_3\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_4\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_5\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_6\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_7\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_8\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_9\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_10\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_11\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_12\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_13\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_14\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_15\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_16\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_17\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_18\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_19\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_20\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_21\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_22\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_23\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_24\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_25\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_26\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_27\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_28\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_29\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_30\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_31\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_32\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_33\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_34\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_35\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_36\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_37\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_38\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_39\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_40\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_41\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_42\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_43\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_44\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_45\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_46\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_47\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_48\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_49\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_50\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_51\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_52\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_53\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_54\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_55\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_56\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_57\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_58\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_59\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_60\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_61\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_62\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_2\ : out STD_LOGIC;
    ififo_rst : in STD_LOGIC;
    \rd_ptr_reg[1]_0\ : in STD_LOGIC;
    \my_full_reg[1]_0\ : in STD_LOGIC;
    \my_full_reg[1]_1\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg[0]\ : in STD_LOGIC;
    \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg[0]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg[0]_1\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg[1]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg[1]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg[1]_1\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg[2]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg[2]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg[2]_1\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg[3]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg[3]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg[3]_1\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg[4]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg[4]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg[4]_1\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg[5]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg[5]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg[5]_1\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg[6]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg[6]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg[6]_1\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg[7]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg[7]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg[7]_1\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg[0]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg[0]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg[0]_1\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg[1]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg[1]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg[1]_1\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg[2]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg[2]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg[2]_1\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg[3]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg[3]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg[3]_1\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg[4]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg[4]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg[4]_1\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg[5]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg[5]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg[5]_1\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg[6]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg[6]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg[6]_1\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg[7]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg[7]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg[7]_1\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_1\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg[1]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg[1]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg[1]_1\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg[2]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg[2]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg[2]_1\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg[3]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg[3]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg[3]_1\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg[4]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg[4]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg[4]_1\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg[5]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg[5]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg[5]_1\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg[6]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg[6]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg[6]_1\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg[7]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg[7]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg[7]_1\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg[0]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg[0]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg[0]_1\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg[1]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg[1]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg[1]_1\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg[2]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg[2]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg[2]_1\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg[3]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg[3]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg[3]_1\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg[4]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg[4]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg[4]_1\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg[5]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg[5]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg[5]_1\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg[6]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg[6]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg[6]_1\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg[7]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg[7]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg[7]_1\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise2_r_reg[0]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise2_r_reg[0]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise2_r_reg[0]_1\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg[1]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg[1]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg[1]_1\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg[2]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg[2]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg[2]_1\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg[3]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg[3]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg[3]_1\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise2_r_reg[4]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise2_r_reg[4]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise2_r_reg[4]_1\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg[5]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg[5]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg[5]_1\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg[6]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg[6]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg[6]_1\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg[7]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg[7]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg[7]_1\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg[0]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg[0]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg[0]_1\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg[1]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg[1]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg[1]_1\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg[2]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg[2]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg[2]_1\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg[3]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg[3]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg[3]_1\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg[4]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg[4]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg[4]_1\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg[5]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg[5]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg[5]_1\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg[6]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg[6]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg[6]_1\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg[7]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg[7]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg[7]_1\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg[0]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg[0]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg[0]_1\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg[1]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg[1]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg[1]_1\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg[2]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg[2]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg[2]_1\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise3_r_reg[3]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise3_r_reg[3]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise3_r_reg[3]_1\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg[4]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg[4]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg[4]_1\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg[5]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg[5]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg[5]_1\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg[6]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg[6]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg[6]_1\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise3_r_reg[7]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise3_r_reg[7]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise3_r_reg[7]_1\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg[0]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg[0]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg[0]_1\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg[1]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg[1]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg[1]_1\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg[2]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg[2]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg[2]_1\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg[3]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg[3]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg[3]_1\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg[4]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg[4]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg[4]_1\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg[5]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg[5]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg[5]_1\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg[6]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg[6]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg[6]_1\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7]_1\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \my_full_reg[1]_2\ : in STD_LOGIC;
    \my_full_reg[1]_3\ : in STD_LOGIC;
    \my_full_reg[1]_4\ : in STD_LOGIC;
    \my_full_reg[1]_5\ : in STD_LOGIC;
    \my_full_reg[1]_6\ : in STD_LOGIC;
    \my_full_reg[1]_7\ : in STD_LOGIC;
    \my_full_reg[1]_8\ : in STD_LOGIC;
    \my_full_reg[1]_9\ : in STD_LOGIC;
    \wr_ptr[1]_i_2__2\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    if_empty_r : in STD_LOGIC_VECTOR ( 0 to 0 );
    Q : in STD_LOGIC_VECTOR ( 67 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of mig_mig_7series_v4_2_ddr_if_post_fifo_30 : entity is "mig_7series_v4_2_ddr_if_post_fifo";
end mig_mig_7series_v4_2_ddr_if_post_fifo_30;

architecture STRUCTURE of mig_mig_7series_v4_2_ddr_if_post_fifo_30 is
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]\ : STD_LOGIC;
  signal mem_out : STD_LOGIC_VECTOR ( 79 downto 16 );
  signal mem_reg_0_3_12_17_n_0 : STD_LOGIC;
  signal mem_reg_0_3_12_17_n_1 : STD_LOGIC;
  signal mem_reg_0_3_12_17_n_2 : STD_LOGIC;
  signal mem_reg_0_3_12_17_n_3 : STD_LOGIC;
  signal my_empty : STD_LOGIC_VECTOR ( 4 downto 1 );
  signal \my_empty[4]_i_1__6_n_0\ : STD_LOGIC;
  signal \my_empty[4]_i_2__2_n_0\ : STD_LOGIC;
  signal \my_empty_inst_rep__2_n_0\ : STD_LOGIC;
  signal \^my_empty_reg[4]_0\ : STD_LOGIC;
  signal \^my_empty_reg[4]_1\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \my_empty_reg[4]_rep__0_n_0\ : STD_LOGIC;
  signal \my_empty_reg[4]_rep_n_0\ : STD_LOGIC;
  signal my_full : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \my_full[0]_i_1__2_n_0\ : STD_LOGIC;
  signal \my_full[1]_i_1__2_n_0\ : STD_LOGIC;
  signal \my_full[1]_i_2__2_n_0\ : STD_LOGIC;
  signal rd_ptr : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \rd_ptr[0]_i_1__2_n_0\ : STD_LOGIC;
  signal \rd_ptr[1]_i_1__2_n_0\ : STD_LOGIC;
  signal rd_ptr_timing : STD_LOGIC_VECTOR ( 1 downto 0 );
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of rd_ptr_timing : signal is "true";
  attribute syn_maxfan : string;
  attribute syn_maxfan of rd_ptr_timing : signal is "10";
  signal \rd_ptr_timing[0]_i_1__6_n_0\ : STD_LOGIC;
  signal \rd_ptr_timing[1]_i_1__6_n_0\ : STD_LOGIC;
  signal wr_en : STD_LOGIC;
  attribute MAX_FANOUT : string;
  attribute MAX_FANOUT of wr_en : signal is "40";
  attribute RTL_MAX_FANOUT : string;
  attribute RTL_MAX_FANOUT of wr_en : signal is "found";
  attribute syn_maxfan of wr_en : signal is "10";
  signal wr_ptr : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \wr_ptr[0]_i_1__6_n_0\ : STD_LOGIC;
  signal \wr_ptr[1]_i_1__6_n_0\ : STD_LOGIC;
  signal \wr_ptr[1]_i_3__1_n_0\ : STD_LOGIC;
  signal NLW_mem_reg_0_3_12_17_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_3_18_23_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_3_24_29_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_3_30_35_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_3_36_41_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_3_42_47_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_3_48_53_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_3_54_59_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_3_60_65_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_3_66_71_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_3_72_77_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_3_78_79_DOB_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_3_78_79_DOC_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_3_78_79_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \app_rd_data[120]_INST_0\ : label is "soft_lutpair846";
  attribute SOFT_HLUTNM of \app_rd_data[121]_INST_0\ : label is "soft_lutpair845";
  attribute SOFT_HLUTNM of \app_rd_data[122]_INST_0\ : label is "soft_lutpair836";
  attribute SOFT_HLUTNM of \app_rd_data[123]_INST_0\ : label is "soft_lutpair842";
  attribute SOFT_HLUTNM of \app_rd_data[124]_INST_0\ : label is "soft_lutpair843";
  attribute SOFT_HLUTNM of \app_rd_data[125]_INST_0\ : label is "soft_lutpair833";
  attribute SOFT_HLUTNM of \app_rd_data[126]_INST_0\ : label is "soft_lutpair832";
  attribute SOFT_HLUTNM of \app_rd_data[127]_INST_0\ : label is "soft_lutpair838";
  attribute SOFT_HLUTNM of \app_rd_data[184]_INST_0\ : label is "soft_lutpair826";
  attribute SOFT_HLUTNM of \app_rd_data[185]_INST_0\ : label is "soft_lutpair821";
  attribute SOFT_HLUTNM of \app_rd_data[186]_INST_0\ : label is "soft_lutpair830";
  attribute SOFT_HLUTNM of \app_rd_data[187]_INST_0\ : label is "soft_lutpair824";
  attribute SOFT_HLUTNM of \app_rd_data[188]_INST_0\ : label is "soft_lutpair819";
  attribute SOFT_HLUTNM of \app_rd_data[189]_INST_0\ : label is "soft_lutpair828";
  attribute SOFT_HLUTNM of \app_rd_data[190]_INST_0\ : label is "soft_lutpair822";
  attribute SOFT_HLUTNM of \app_rd_data[191]_INST_0\ : label is "soft_lutpair818";
  attribute SOFT_HLUTNM of \app_rd_data[248]_INST_0\ : label is "soft_lutpair845";
  attribute SOFT_HLUTNM of \app_rd_data[249]_INST_0\ : label is "soft_lutpair836";
  attribute SOFT_HLUTNM of \app_rd_data[250]_INST_0\ : label is "soft_lutpair841";
  attribute SOFT_HLUTNM of \app_rd_data[251]_INST_0\ : label is "soft_lutpair841";
  attribute SOFT_HLUTNM of \app_rd_data[252]_INST_0\ : label is "soft_lutpair834";
  attribute SOFT_HLUTNM of \app_rd_data[253]_INST_0\ : label is "soft_lutpair833";
  attribute SOFT_HLUTNM of \app_rd_data[254]_INST_0\ : label is "soft_lutpair839";
  attribute SOFT_HLUTNM of \app_rd_data[255]_INST_0\ : label is "soft_lutpair829";
  attribute SOFT_HLUTNM of \app_rd_data[312]_INST_0\ : label is "soft_lutpair821";
  attribute SOFT_HLUTNM of \app_rd_data[313]_INST_0\ : label is "soft_lutpair831";
  attribute SOFT_HLUTNM of \app_rd_data[314]_INST_0\ : label is "soft_lutpair824";
  attribute SOFT_HLUTNM of \app_rd_data[315]_INST_0\ : label is "soft_lutpair815";
  attribute SOFT_HLUTNM of \app_rd_data[316]_INST_0\ : label is "soft_lutpair828";
  attribute SOFT_HLUTNM of \app_rd_data[317]_INST_0\ : label is "soft_lutpair823";
  attribute SOFT_HLUTNM of \app_rd_data[318]_INST_0\ : label is "soft_lutpair818";
  attribute SOFT_HLUTNM of \app_rd_data[319]_INST_0\ : label is "soft_lutpair827";
  attribute SOFT_HLUTNM of \app_rd_data[376]_INST_0\ : label is "soft_lutpair837";
  attribute SOFT_HLUTNM of \app_rd_data[377]_INST_0\ : label is "soft_lutpair844";
  attribute SOFT_HLUTNM of \app_rd_data[378]_INST_0\ : label is "soft_lutpair844";
  attribute SOFT_HLUTNM of \app_rd_data[379]_INST_0\ : label is "soft_lutpair835";
  attribute SOFT_HLUTNM of \app_rd_data[380]_INST_0\ : label is "soft_lutpair843";
  attribute SOFT_HLUTNM of \app_rd_data[381]_INST_0\ : label is "soft_lutpair840";
  attribute SOFT_HLUTNM of \app_rd_data[382]_INST_0\ : label is "soft_lutpair829";
  attribute SOFT_HLUTNM of \app_rd_data[383]_INST_0\ : label is "soft_lutpair838";
  attribute SOFT_HLUTNM of \app_rd_data[440]_INST_0\ : label is "soft_lutpair815";
  attribute SOFT_HLUTNM of \app_rd_data[441]_INST_0\ : label is "soft_lutpair825";
  attribute SOFT_HLUTNM of \app_rd_data[442]_INST_0\ : label is "soft_lutpair820";
  attribute SOFT_HLUTNM of \app_rd_data[443]_INST_0\ : label is "soft_lutpair826";
  attribute SOFT_HLUTNM of \app_rd_data[444]_INST_0\ : label is "soft_lutpair823";
  attribute SOFT_HLUTNM of \app_rd_data[445]_INST_0\ : label is "soft_lutpair819";
  attribute SOFT_HLUTNM of \app_rd_data[446]_INST_0\ : label is "soft_lutpair827";
  attribute SOFT_HLUTNM of \app_rd_data[447]_INST_0\ : label is "soft_lutpair822";
  attribute SOFT_HLUTNM of \app_rd_data[504]_INST_0\ : label is "soft_lutpair846";
  attribute SOFT_HLUTNM of \app_rd_data[505]_INST_0\ : label is "soft_lutpair842";
  attribute SOFT_HLUTNM of \app_rd_data[506]_INST_0\ : label is "soft_lutpair835";
  attribute SOFT_HLUTNM of \app_rd_data[507]_INST_0\ : label is "soft_lutpair837";
  attribute SOFT_HLUTNM of \app_rd_data[508]_INST_0\ : label is "soft_lutpair840";
  attribute SOFT_HLUTNM of \app_rd_data[509]_INST_0\ : label is "soft_lutpair832";
  attribute SOFT_HLUTNM of \app_rd_data[510]_INST_0\ : label is "soft_lutpair839";
  attribute SOFT_HLUTNM of \app_rd_data[511]_INST_0\ : label is "soft_lutpair834";
  attribute SOFT_HLUTNM of \app_rd_data[56]_INST_0\ : label is "soft_lutpair831";
  attribute SOFT_HLUTNM of \app_rd_data[57]_INST_0\ : label is "soft_lutpair825";
  attribute SOFT_HLUTNM of \app_rd_data[58]_INST_0\ : label is "soft_lutpair820";
  attribute SOFT_HLUTNM of \app_rd_data[59]_INST_0\ : label is "soft_lutpair830";
  attribute SOFT_HLUTNM of \app_rd_data[60]_INST_0\ : label is "soft_lutpair817";
  attribute SOFT_HLUTNM of \app_rd_data[61]_INST_0\ : label is "soft_lutpair816";
  attribute SOFT_HLUTNM of \app_rd_data[62]_INST_0\ : label is "soft_lutpair817";
  attribute SOFT_HLUTNM of \app_rd_data[63]_INST_0\ : label is "soft_lutpair816";
  attribute METHODOLOGY_DRC_VIOS : string;
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_3_12_17 : label is "";
  attribute RTL_RAM_BITS : integer;
  attribute RTL_RAM_BITS of mem_reg_0_3_12_17 : label is 320;
  attribute RTL_RAM_NAME : string;
  attribute RTL_RAM_NAME of mem_reg_0_3_12_17 : label is "dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem";
  attribute ram_addr_begin : integer;
  attribute ram_addr_begin of mem_reg_0_3_12_17 : label is 0;
  attribute ram_addr_end : integer;
  attribute ram_addr_end of mem_reg_0_3_12_17 : label is 3;
  attribute ram_offset : integer;
  attribute ram_offset of mem_reg_0_3_12_17 : label is 0;
  attribute ram_slice_begin : integer;
  attribute ram_slice_begin of mem_reg_0_3_12_17 : label is 12;
  attribute ram_slice_end : integer;
  attribute ram_slice_end of mem_reg_0_3_12_17 : label is 17;
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_3_18_23 : label is "";
  attribute RTL_RAM_BITS of mem_reg_0_3_18_23 : label is 320;
  attribute RTL_RAM_NAME of mem_reg_0_3_18_23 : label is "dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem";
  attribute ram_addr_begin of mem_reg_0_3_18_23 : label is 0;
  attribute ram_addr_end of mem_reg_0_3_18_23 : label is 3;
  attribute ram_offset of mem_reg_0_3_18_23 : label is 0;
  attribute ram_slice_begin of mem_reg_0_3_18_23 : label is 18;
  attribute ram_slice_end of mem_reg_0_3_18_23 : label is 23;
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_3_24_29 : label is "";
  attribute RTL_RAM_BITS of mem_reg_0_3_24_29 : label is 320;
  attribute RTL_RAM_NAME of mem_reg_0_3_24_29 : label is "dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem";
  attribute ram_addr_begin of mem_reg_0_3_24_29 : label is 0;
  attribute ram_addr_end of mem_reg_0_3_24_29 : label is 3;
  attribute ram_offset of mem_reg_0_3_24_29 : label is 0;
  attribute ram_slice_begin of mem_reg_0_3_24_29 : label is 24;
  attribute ram_slice_end of mem_reg_0_3_24_29 : label is 29;
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_3_30_35 : label is "";
  attribute RTL_RAM_BITS of mem_reg_0_3_30_35 : label is 320;
  attribute RTL_RAM_NAME of mem_reg_0_3_30_35 : label is "dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem";
  attribute ram_addr_begin of mem_reg_0_3_30_35 : label is 0;
  attribute ram_addr_end of mem_reg_0_3_30_35 : label is 3;
  attribute ram_offset of mem_reg_0_3_30_35 : label is 0;
  attribute ram_slice_begin of mem_reg_0_3_30_35 : label is 30;
  attribute ram_slice_end of mem_reg_0_3_30_35 : label is 35;
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_3_36_41 : label is "";
  attribute RTL_RAM_BITS of mem_reg_0_3_36_41 : label is 320;
  attribute RTL_RAM_NAME of mem_reg_0_3_36_41 : label is "dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem";
  attribute ram_addr_begin of mem_reg_0_3_36_41 : label is 0;
  attribute ram_addr_end of mem_reg_0_3_36_41 : label is 3;
  attribute ram_offset of mem_reg_0_3_36_41 : label is 0;
  attribute ram_slice_begin of mem_reg_0_3_36_41 : label is 36;
  attribute ram_slice_end of mem_reg_0_3_36_41 : label is 41;
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_3_42_47 : label is "";
  attribute RTL_RAM_BITS of mem_reg_0_3_42_47 : label is 320;
  attribute RTL_RAM_NAME of mem_reg_0_3_42_47 : label is "dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem";
  attribute ram_addr_begin of mem_reg_0_3_42_47 : label is 0;
  attribute ram_addr_end of mem_reg_0_3_42_47 : label is 3;
  attribute ram_offset of mem_reg_0_3_42_47 : label is 0;
  attribute ram_slice_begin of mem_reg_0_3_42_47 : label is 42;
  attribute ram_slice_end of mem_reg_0_3_42_47 : label is 47;
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_3_48_53 : label is "";
  attribute RTL_RAM_BITS of mem_reg_0_3_48_53 : label is 320;
  attribute RTL_RAM_NAME of mem_reg_0_3_48_53 : label is "dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem";
  attribute ram_addr_begin of mem_reg_0_3_48_53 : label is 0;
  attribute ram_addr_end of mem_reg_0_3_48_53 : label is 3;
  attribute ram_offset of mem_reg_0_3_48_53 : label is 0;
  attribute ram_slice_begin of mem_reg_0_3_48_53 : label is 48;
  attribute ram_slice_end of mem_reg_0_3_48_53 : label is 53;
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_3_54_59 : label is "";
  attribute RTL_RAM_BITS of mem_reg_0_3_54_59 : label is 320;
  attribute RTL_RAM_NAME of mem_reg_0_3_54_59 : label is "dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem";
  attribute ram_addr_begin of mem_reg_0_3_54_59 : label is 0;
  attribute ram_addr_end of mem_reg_0_3_54_59 : label is 3;
  attribute ram_offset of mem_reg_0_3_54_59 : label is 0;
  attribute ram_slice_begin of mem_reg_0_3_54_59 : label is 54;
  attribute ram_slice_end of mem_reg_0_3_54_59 : label is 59;
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_3_60_65 : label is "";
  attribute RTL_RAM_BITS of mem_reg_0_3_60_65 : label is 320;
  attribute RTL_RAM_NAME of mem_reg_0_3_60_65 : label is "dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem";
  attribute ram_addr_begin of mem_reg_0_3_60_65 : label is 0;
  attribute ram_addr_end of mem_reg_0_3_60_65 : label is 3;
  attribute ram_offset of mem_reg_0_3_60_65 : label is 0;
  attribute ram_slice_begin of mem_reg_0_3_60_65 : label is 60;
  attribute ram_slice_end of mem_reg_0_3_60_65 : label is 65;
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_3_66_71 : label is "";
  attribute RTL_RAM_BITS of mem_reg_0_3_66_71 : label is 320;
  attribute RTL_RAM_NAME of mem_reg_0_3_66_71 : label is "dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem";
  attribute ram_addr_begin of mem_reg_0_3_66_71 : label is 0;
  attribute ram_addr_end of mem_reg_0_3_66_71 : label is 3;
  attribute ram_offset of mem_reg_0_3_66_71 : label is 0;
  attribute ram_slice_begin of mem_reg_0_3_66_71 : label is 66;
  attribute ram_slice_end of mem_reg_0_3_66_71 : label is 71;
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_3_72_77 : label is "";
  attribute RTL_RAM_BITS of mem_reg_0_3_72_77 : label is 320;
  attribute RTL_RAM_NAME of mem_reg_0_3_72_77 : label is "dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem";
  attribute ram_addr_begin of mem_reg_0_3_72_77 : label is 0;
  attribute ram_addr_end of mem_reg_0_3_72_77 : label is 3;
  attribute ram_offset of mem_reg_0_3_72_77 : label is 0;
  attribute ram_slice_begin of mem_reg_0_3_72_77 : label is 72;
  attribute ram_slice_end of mem_reg_0_3_72_77 : label is 77;
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_3_78_79 : label is "";
  attribute RTL_RAM_BITS of mem_reg_0_3_78_79 : label is 320;
  attribute RTL_RAM_NAME of mem_reg_0_3_78_79 : label is "dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem";
  attribute ram_addr_begin of mem_reg_0_3_78_79 : label is 0;
  attribute ram_addr_end of mem_reg_0_3_78_79 : label is 3;
  attribute ram_offset of mem_reg_0_3_78_79 : label is 0;
  attribute ram_slice_begin of mem_reg_0_3_78_79 : label is 78;
  attribute ram_slice_end of mem_reg_0_3_78_79 : label is 79;
  attribute SOFT_HLUTNM of \my_empty_inst__12\ : label is "soft_lutpair847";
  attribute SOFT_HLUTNM of \my_empty_inst__14\ : label is "soft_lutpair847";
  attribute IS_FANOUT_CONSTRAINED : integer;
  attribute IS_FANOUT_CONSTRAINED of \my_empty_inst_rep__2\ : label is 1;
  attribute ORIG_CELL_NAME : string;
  attribute ORIG_CELL_NAME of \my_empty_reg[4]\ : label is "my_empty_reg[4]";
  attribute ORIG_CELL_NAME of \my_empty_reg[4]_rep\ : label is "my_empty_reg[4]";
  attribute ORIG_CELL_NAME of \my_empty_reg[4]_rep__0\ : label is "my_empty_reg[4]";
  attribute SOFT_HLUTNM of \rd_ptr[0]_i_1__2\ : label is "soft_lutpair814";
  attribute SOFT_HLUTNM of \rd_ptr[1]_i_1__2\ : label is "soft_lutpair814";
  attribute syn_maxfan of \rd_ptr_reg[0]\ : label is "10";
  attribute syn_maxfan of \rd_ptr_reg[1]\ : label is "10";
  attribute KEEP : string;
  attribute KEEP of \rd_ptr_timing_reg[0]\ : label is "yes";
  attribute syn_maxfan of \rd_ptr_timing_reg[0]\ : label is "10";
  attribute KEEP of \rd_ptr_timing_reg[1]\ : label is "yes";
  attribute syn_maxfan of \rd_ptr_timing_reg[1]\ : label is "10";
  attribute SOFT_HLUTNM of \wr_ptr[1]_i_3__1\ : label is "soft_lutpair813";
  attribute SOFT_HLUTNM of \wr_ptr[1]_i_4\ : label is "soft_lutpair813";
  attribute syn_maxfan of \wr_ptr_reg[0]\ : label is "10";
  attribute syn_maxfan of \wr_ptr_reg[1]\ : label is "10";
begin
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]\;
  \my_empty_reg[4]_0\ <= \^my_empty_reg[4]_0\;
  \my_empty_reg[4]_1\(0) <= \^my_empty_reg[4]_1\(0);
\app_rd_data[120]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(5),
      I1 => \my_empty_inst_rep__2_n_0\,
      I2 => mem_out(17),
      O => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]\
    );
\app_rd_data[121]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(13),
      I1 => \my_empty_inst_rep__2_n_0\,
      I2 => mem_out(25),
      O => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]\
    );
\app_rd_data[122]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(21),
      I1 => \my_empty_inst_rep__2_n_0\,
      I2 => mem_out(33),
      O => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]\
    );
\app_rd_data[123]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(29),
      I1 => \my_empty_inst_rep__2_n_0\,
      I2 => mem_out(41),
      O => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]\
    );
\app_rd_data[124]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(37),
      I1 => my_empty(4),
      I2 => mem_out(49),
      O => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]\
    );
\app_rd_data[125]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(45),
      I1 => my_empty(4),
      I2 => mem_out(57),
      O => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]\
    );
\app_rd_data[126]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(53),
      I1 => my_empty(4),
      I2 => mem_out(65),
      O => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]\
    );
\app_rd_data[127]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(61),
      I1 => my_empty(4),
      I2 => mem_out(73),
      O => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]\
    );
\app_rd_data[184]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(6),
      I1 => \my_empty_inst_rep__2_n_0\,
      I2 => mem_out(18),
      O => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]\
    );
\app_rd_data[185]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(14),
      I1 => \my_empty_inst_rep__2_n_0\,
      I2 => mem_out(26),
      O => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]\
    );
\app_rd_data[186]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(22),
      I1 => \my_empty_inst_rep__2_n_0\,
      I2 => mem_out(34),
      O => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]\
    );
\app_rd_data[187]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(30),
      I1 => \my_empty_inst_rep__2_n_0\,
      I2 => mem_out(42),
      O => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]\
    );
\app_rd_data[188]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(38),
      I1 => my_empty(4),
      I2 => mem_out(50),
      O => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]\
    );
\app_rd_data[189]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(46),
      I1 => my_empty(4),
      I2 => mem_out(58),
      O => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]\
    );
\app_rd_data[190]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(54),
      I1 => my_empty(4),
      I2 => mem_out(66),
      O => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]\
    );
\app_rd_data[191]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(62),
      I1 => my_empty(4),
      I2 => mem_out(74),
      O => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]\
    );
\app_rd_data[248]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(7),
      I1 => \my_empty_inst_rep__2_n_0\,
      I2 => mem_out(19),
      O => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]\
    );
\app_rd_data[249]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(15),
      I1 => \my_empty_inst_rep__2_n_0\,
      I2 => mem_out(27),
      O => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]\
    );
\app_rd_data[250]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(23),
      I1 => \my_empty_inst_rep__2_n_0\,
      I2 => mem_out(35),
      O => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]\
    );
\app_rd_data[251]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(31),
      I1 => \my_empty_inst_rep__2_n_0\,
      I2 => mem_out(43),
      O => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]\
    );
\app_rd_data[252]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(39),
      I1 => my_empty(4),
      I2 => mem_out(51),
      O => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]\
    );
\app_rd_data[253]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(47),
      I1 => my_empty(4),
      I2 => mem_out(59),
      O => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]\
    );
\app_rd_data[254]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(55),
      I1 => my_empty(4),
      I2 => mem_out(67),
      O => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]\
    );
\app_rd_data[255]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(63),
      I1 => my_empty(4),
      I2 => mem_out(75),
      O => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]\
    );
\app_rd_data[312]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(8),
      I1 => \my_empty_inst_rep__2_n_0\,
      I2 => mem_out(20),
      O => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]\
    );
\app_rd_data[313]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(16),
      I1 => \my_empty_inst_rep__2_n_0\,
      I2 => mem_out(28),
      O => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]\
    );
\app_rd_data[314]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(24),
      I1 => \my_empty_inst_rep__2_n_0\,
      I2 => mem_out(36),
      O => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]\
    );
\app_rd_data[315]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(32),
      I1 => \my_empty_inst_rep__2_n_0\,
      I2 => mem_out(44),
      O => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]\
    );
\app_rd_data[316]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(40),
      I1 => my_empty(4),
      I2 => mem_out(52),
      O => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]\
    );
\app_rd_data[317]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(48),
      I1 => my_empty(4),
      I2 => mem_out(60),
      O => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]\
    );
\app_rd_data[318]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(56),
      I1 => my_empty(4),
      I2 => mem_out(68),
      O => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]\
    );
\app_rd_data[319]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(64),
      I1 => my_empty(4),
      I2 => mem_out(76),
      O => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]\
    );
\app_rd_data[376]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(9),
      I1 => \my_empty_inst_rep__2_n_0\,
      I2 => mem_out(21),
      O => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]\
    );
\app_rd_data[377]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(17),
      I1 => \my_empty_inst_rep__2_n_0\,
      I2 => mem_out(29),
      O => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]\
    );
\app_rd_data[378]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(25),
      I1 => \my_empty_inst_rep__2_n_0\,
      I2 => mem_out(37),
      O => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]\
    );
\app_rd_data[379]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(33),
      I1 => \my_empty_inst_rep__2_n_0\,
      I2 => mem_out(45),
      O => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]\
    );
\app_rd_data[380]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(41),
      I1 => my_empty(4),
      I2 => mem_out(53),
      O => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]\
    );
\app_rd_data[381]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(49),
      I1 => my_empty(4),
      I2 => mem_out(61),
      O => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]\
    );
\app_rd_data[382]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(57),
      I1 => my_empty(4),
      I2 => mem_out(69),
      O => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]\
    );
\app_rd_data[383]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(65),
      I1 => my_empty(4),
      I2 => mem_out(77),
      O => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]\
    );
\app_rd_data[440]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(10),
      I1 => \my_empty_inst_rep__2_n_0\,
      I2 => mem_out(22),
      O => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]\
    );
\app_rd_data[441]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(18),
      I1 => \my_empty_inst_rep__2_n_0\,
      I2 => mem_out(30),
      O => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]\
    );
\app_rd_data[442]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(26),
      I1 => \my_empty_inst_rep__2_n_0\,
      I2 => mem_out(38),
      O => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]\
    );
\app_rd_data[443]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(34),
      I1 => \my_empty_inst_rep__2_n_0\,
      I2 => mem_out(46),
      O => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]\
    );
\app_rd_data[444]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(42),
      I1 => my_empty(4),
      I2 => mem_out(54),
      O => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]\
    );
\app_rd_data[445]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(50),
      I1 => my_empty(4),
      I2 => mem_out(62),
      O => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]\
    );
\app_rd_data[446]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(58),
      I1 => my_empty(4),
      I2 => mem_out(70),
      O => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]\
    );
\app_rd_data[447]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(66),
      I1 => my_empty(4),
      I2 => mem_out(78),
      O => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]\
    );
\app_rd_data[504]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(11),
      I1 => \my_empty_inst_rep__2_n_0\,
      I2 => mem_out(23),
      O => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]\
    );
\app_rd_data[505]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(19),
      I1 => \my_empty_inst_rep__2_n_0\,
      I2 => mem_out(31),
      O => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]\
    );
\app_rd_data[506]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(27),
      I1 => \my_empty_inst_rep__2_n_0\,
      I2 => mem_out(39),
      O => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]\
    );
\app_rd_data[507]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(35),
      I1 => \my_empty_inst_rep__2_n_0\,
      I2 => mem_out(47),
      O => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]\
    );
\app_rd_data[508]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(43),
      I1 => my_empty(4),
      I2 => mem_out(55),
      O => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]\
    );
\app_rd_data[509]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(51),
      I1 => my_empty(4),
      I2 => mem_out(63),
      O => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]\
    );
\app_rd_data[510]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(59),
      I1 => my_empty(4),
      I2 => mem_out(71),
      O => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]\
    );
\app_rd_data[511]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(67),
      I1 => my_empty(4),
      I2 => mem_out(79),
      O => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]\
    );
\app_rd_data[56]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(4),
      I1 => \my_empty_inst_rep__2_n_0\,
      I2 => mem_out(16),
      O => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]\
    );
\app_rd_data[57]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(12),
      I1 => \my_empty_inst_rep__2_n_0\,
      I2 => mem_out(24),
      O => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]\
    );
\app_rd_data[58]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(20),
      I1 => \my_empty_inst_rep__2_n_0\,
      I2 => mem_out(32),
      O => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]\
    );
\app_rd_data[59]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(28),
      I1 => \my_empty_inst_rep__2_n_0\,
      I2 => mem_out(40),
      O => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]\
    );
\app_rd_data[60]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(36),
      I1 => my_empty(4),
      I2 => mem_out(48),
      O => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]\
    );
\app_rd_data[61]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(44),
      I1 => my_empty(4),
      I2 => mem_out(56),
      O => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]\
    );
\app_rd_data[62]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(52),
      I1 => my_empty(4),
      I2 => mem_out(64),
      O => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]\
    );
\app_rd_data[63]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(60),
      I1 => my_empty(4),
      I2 => mem_out(72),
      O => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]\
    );
\gen_mux_rd[0].mux_rd_fall0_r1[0]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]\,
      I1 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg[0]\,
      I2 => \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]\(1),
      I3 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg[0]_0\,
      I4 => \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]\(0),
      I5 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg[0]_1\,
      O => \rd_mux_sel_r_reg[1]_7\
    );
\gen_mux_rd[0].mux_rd_fall1_r1[0]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]\,
      I1 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg[0]\,
      I2 => \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]\(1),
      I3 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg[0]_0\,
      I4 => \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]\(0),
      I5 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg[0]_1\,
      O => \rd_mux_sel_r_reg[1]_23\
    );
\gen_mux_rd[0].mux_rd_fall2_r1[0]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]\,
      I1 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg[0]\,
      I2 => \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]\(1),
      I3 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg[0]_0\,
      I4 => \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]\(0),
      I5 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg[0]_1\,
      O => \rd_mux_sel_r_reg[1]_39\
    );
\gen_mux_rd[0].mux_rd_fall3_r1[0]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]\,
      I1 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg[0]\,
      I2 => \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]\(1),
      I3 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg[0]_0\,
      I4 => \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]\(0),
      I5 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg[0]_1\,
      O => \rd_mux_sel_r_reg[1]_55\
    );
\gen_mux_rd[0].mux_rd_rise0_r1[0]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]\,
      I1 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg[0]\,
      I2 => \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]\(1),
      I3 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg[0]_0\,
      I4 => \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]\(0),
      I5 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg[0]_1\,
      O => \rd_mux_sel_r_reg[1]\
    );
\gen_mux_rd[0].mux_rd_rise1_r1[0]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]\,
      I1 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]\,
      I2 => \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]\(1),
      I3 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_0\,
      I4 => \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]\(0),
      I5 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_1\,
      O => \rd_mux_sel_r_reg[1]_15\
    );
\gen_mux_rd[0].mux_rd_rise2_r1[0]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]\,
      I1 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise2_r_reg[0]\,
      I2 => \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]\(1),
      I3 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise2_r_reg[0]_0\,
      I4 => \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]\(0),
      I5 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise2_r_reg[0]_1\,
      O => \rd_mux_sel_r_reg[1]_31\
    );
\gen_mux_rd[0].mux_rd_rise3_r1[0]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]\,
      I1 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg[0]\,
      I2 => \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]\(1),
      I3 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg[0]_0\,
      I4 => \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]\(0),
      I5 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg[0]_1\,
      O => \rd_mux_sel_r_reg[1]_47\
    );
\gen_mux_rd[1].mux_rd_fall0_r1[1]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]\,
      I1 => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg[1]\,
      I2 => \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]\(1),
      I3 => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg[1]_0\,
      I4 => \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]\(0),
      I5 => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg[1]_1\,
      O => \rd_mux_sel_r_reg[1]_8\
    );
\gen_mux_rd[1].mux_rd_fall1_r1[1]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]\,
      I1 => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg[1]\,
      I2 => \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]\(1),
      I3 => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg[1]_0\,
      I4 => \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]\(0),
      I5 => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg[1]_1\,
      O => \rd_mux_sel_r_reg[1]_24\
    );
\gen_mux_rd[1].mux_rd_fall2_r1[1]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]\,
      I1 => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg[1]\,
      I2 => \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]\(1),
      I3 => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg[1]_0\,
      I4 => \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]\(0),
      I5 => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg[1]_1\,
      O => \rd_mux_sel_r_reg[1]_40\
    );
\gen_mux_rd[1].mux_rd_fall3_r1[1]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]\,
      I1 => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg[1]\,
      I2 => \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]\(1),
      I3 => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg[1]_0\,
      I4 => \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]\(0),
      I5 => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg[1]_1\,
      O => \rd_mux_sel_r_reg[1]_56\
    );
\gen_mux_rd[1].mux_rd_rise0_r1[1]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]\,
      I1 => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg[1]\,
      I2 => \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]\(1),
      I3 => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg[1]_0\,
      I4 => \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]\(0),
      I5 => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg[1]_1\,
      O => \rd_mux_sel_r_reg[1]_0\
    );
\gen_mux_rd[1].mux_rd_rise1_r1[1]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]\,
      I1 => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg[1]\,
      I2 => \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]\(1),
      I3 => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg[1]_0\,
      I4 => \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]\(0),
      I5 => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg[1]_1\,
      O => \rd_mux_sel_r_reg[1]_16\
    );
\gen_mux_rd[1].mux_rd_rise2_r1[1]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]\,
      I1 => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg[1]\,
      I2 => \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]\(1),
      I3 => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg[1]_0\,
      I4 => \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]\(0),
      I5 => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg[1]_1\,
      O => \rd_mux_sel_r_reg[1]_32\
    );
\gen_mux_rd[1].mux_rd_rise3_r1[1]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]\,
      I1 => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg[1]\,
      I2 => \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]\(1),
      I3 => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg[1]_0\,
      I4 => \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]\(0),
      I5 => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg[1]_1\,
      O => \rd_mux_sel_r_reg[1]_48\
    );
\gen_mux_rd[2].mux_rd_fall0_r1[2]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]\,
      I1 => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg[2]\,
      I2 => \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]\(1),
      I3 => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg[2]_0\,
      I4 => \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]\(0),
      I5 => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg[2]_1\,
      O => \rd_mux_sel_r_reg[1]_9\
    );
\gen_mux_rd[2].mux_rd_fall1_r1[2]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]\,
      I1 => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg[2]\,
      I2 => \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]\(1),
      I3 => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg[2]_0\,
      I4 => \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]\(0),
      I5 => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg[2]_1\,
      O => \rd_mux_sel_r_reg[1]_25\
    );
\gen_mux_rd[2].mux_rd_fall2_r1[2]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]\,
      I1 => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg[2]\,
      I2 => \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]\(1),
      I3 => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg[2]_0\,
      I4 => \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]\(0),
      I5 => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg[2]_1\,
      O => \rd_mux_sel_r_reg[1]_41\
    );
\gen_mux_rd[2].mux_rd_fall3_r1[2]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]\,
      I1 => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg[2]\,
      I2 => \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]\(1),
      I3 => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg[2]_0\,
      I4 => \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]\(0),
      I5 => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg[2]_1\,
      O => \rd_mux_sel_r_reg[1]_57\
    );
\gen_mux_rd[2].mux_rd_rise0_r1[2]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]\,
      I1 => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg[2]\,
      I2 => \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]\(1),
      I3 => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg[2]_0\,
      I4 => \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]\(0),
      I5 => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg[2]_1\,
      O => \rd_mux_sel_r_reg[1]_1\
    );
\gen_mux_rd[2].mux_rd_rise1_r1[2]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]\,
      I1 => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg[2]\,
      I2 => \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]\(1),
      I3 => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg[2]_0\,
      I4 => \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]\(0),
      I5 => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg[2]_1\,
      O => \rd_mux_sel_r_reg[1]_17\
    );
\gen_mux_rd[2].mux_rd_rise2_r1[2]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]\,
      I1 => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg[2]\,
      I2 => \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]\(1),
      I3 => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg[2]_0\,
      I4 => \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]\(0),
      I5 => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg[2]_1\,
      O => \rd_mux_sel_r_reg[1]_33\
    );
\gen_mux_rd[2].mux_rd_rise3_r1[2]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]\,
      I1 => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg[2]\,
      I2 => \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]\(1),
      I3 => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg[2]_0\,
      I4 => \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]\(0),
      I5 => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg[2]_1\,
      O => \rd_mux_sel_r_reg[1]_49\
    );
\gen_mux_rd[3].mux_rd_fall0_r1[3]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]\,
      I1 => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg[3]\,
      I2 => \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]\(1),
      I3 => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg[3]_0\,
      I4 => \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]\(0),
      I5 => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg[3]_1\,
      O => \rd_mux_sel_r_reg[1]_10\
    );
\gen_mux_rd[3].mux_rd_fall1_r1[3]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]\,
      I1 => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg[3]\,
      I2 => \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]\(1),
      I3 => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg[3]_0\,
      I4 => \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]\(0),
      I5 => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg[3]_1\,
      O => \rd_mux_sel_r_reg[1]_26\
    );
\gen_mux_rd[3].mux_rd_fall2_r1[3]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]\,
      I1 => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg[3]\,
      I2 => \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]\(1),
      I3 => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg[3]_0\,
      I4 => \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]\(0),
      I5 => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg[3]_1\,
      O => \rd_mux_sel_r_reg[1]_42\
    );
\gen_mux_rd[3].mux_rd_fall3_r1[3]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]\,
      I1 => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg[3]\,
      I2 => \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]\(1),
      I3 => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg[3]_0\,
      I4 => \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]\(0),
      I5 => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg[3]_1\,
      O => \rd_mux_sel_r_reg[1]_58\
    );
\gen_mux_rd[3].mux_rd_rise0_r1[3]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]\,
      I1 => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg[3]\,
      I2 => \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]\(1),
      I3 => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg[3]_0\,
      I4 => \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]\(0),
      I5 => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg[3]_1\,
      O => \rd_mux_sel_r_reg[1]_2\
    );
\gen_mux_rd[3].mux_rd_rise1_r1[3]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]\,
      I1 => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg[3]\,
      I2 => \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]\(1),
      I3 => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg[3]_0\,
      I4 => \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]\(0),
      I5 => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg[3]_1\,
      O => \rd_mux_sel_r_reg[1]_18\
    );
\gen_mux_rd[3].mux_rd_rise2_r1[3]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]\,
      I1 => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg[3]\,
      I2 => \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]\(1),
      I3 => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg[3]_0\,
      I4 => \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]\(0),
      I5 => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg[3]_1\,
      O => \rd_mux_sel_r_reg[1]_34\
    );
\gen_mux_rd[3].mux_rd_rise3_r1[3]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]\,
      I1 => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise3_r_reg[3]\,
      I2 => \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]\(1),
      I3 => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise3_r_reg[3]_0\,
      I4 => \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]\(0),
      I5 => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise3_r_reg[3]_1\,
      O => \rd_mux_sel_r_reg[1]_50\
    );
\gen_mux_rd[4].mux_rd_fall0_r1[4]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]\,
      I1 => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg[4]\,
      I2 => \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]\(1),
      I3 => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg[4]_0\,
      I4 => \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]\(0),
      I5 => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg[4]_1\,
      O => \rd_mux_sel_r_reg[1]_11\
    );
\gen_mux_rd[4].mux_rd_fall1_r1[4]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]\,
      I1 => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg[4]\,
      I2 => \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]\(1),
      I3 => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg[4]_0\,
      I4 => \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]\(0),
      I5 => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg[4]_1\,
      O => \rd_mux_sel_r_reg[1]_27\
    );
\gen_mux_rd[4].mux_rd_fall2_r1[4]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]\,
      I1 => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg[4]\,
      I2 => \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]\(1),
      I3 => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg[4]_0\,
      I4 => \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]\(0),
      I5 => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg[4]_1\,
      O => \rd_mux_sel_r_reg[1]_43\
    );
\gen_mux_rd[4].mux_rd_fall3_r1[4]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]\,
      I1 => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg[4]\,
      I2 => \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]\(1),
      I3 => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg[4]_0\,
      I4 => \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]\(0),
      I5 => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg[4]_1\,
      O => \rd_mux_sel_r_reg[1]_59\
    );
\gen_mux_rd[4].mux_rd_rise0_r1[4]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]\,
      I1 => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg[4]\,
      I2 => \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]\(1),
      I3 => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg[4]_0\,
      I4 => \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]\(0),
      I5 => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg[4]_1\,
      O => \rd_mux_sel_r_reg[1]_3\
    );
\gen_mux_rd[4].mux_rd_rise1_r1[4]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]\,
      I1 => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg[4]\,
      I2 => \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]\(1),
      I3 => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg[4]_0\,
      I4 => \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]\(0),
      I5 => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg[4]_1\,
      O => \rd_mux_sel_r_reg[1]_19\
    );
\gen_mux_rd[4].mux_rd_rise2_r1[4]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]\,
      I1 => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise2_r_reg[4]\,
      I2 => \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]\(1),
      I3 => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise2_r_reg[4]_0\,
      I4 => \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]\(0),
      I5 => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise2_r_reg[4]_1\,
      O => \rd_mux_sel_r_reg[1]_35\
    );
\gen_mux_rd[4].mux_rd_rise3_r1[4]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]\,
      I1 => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg[4]\,
      I2 => \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]\(1),
      I3 => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg[4]_0\,
      I4 => \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]\(0),
      I5 => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg[4]_1\,
      O => \rd_mux_sel_r_reg[1]_51\
    );
\gen_mux_rd[5].mux_rd_fall0_r1[5]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]\,
      I1 => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg[5]\,
      I2 => \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]\(1),
      I3 => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg[5]_0\,
      I4 => \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]\(0),
      I5 => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg[5]_1\,
      O => \rd_mux_sel_r_reg[1]_12\
    );
\gen_mux_rd[5].mux_rd_fall1_r1[5]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]\,
      I1 => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg[5]\,
      I2 => \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]\(1),
      I3 => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg[5]_0\,
      I4 => \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]\(0),
      I5 => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg[5]_1\,
      O => \rd_mux_sel_r_reg[1]_28\
    );
\gen_mux_rd[5].mux_rd_fall2_r1[5]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]\,
      I1 => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg[5]\,
      I2 => \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]\(1),
      I3 => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg[5]_0\,
      I4 => \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]\(0),
      I5 => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg[5]_1\,
      O => \rd_mux_sel_r_reg[1]_44\
    );
\gen_mux_rd[5].mux_rd_fall3_r1[5]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]\,
      I1 => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg[5]\,
      I2 => \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]\(1),
      I3 => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg[5]_0\,
      I4 => \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]\(0),
      I5 => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg[5]_1\,
      O => \rd_mux_sel_r_reg[1]_60\
    );
\gen_mux_rd[5].mux_rd_rise0_r1[5]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]\,
      I1 => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg[5]\,
      I2 => \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]\(1),
      I3 => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg[5]_0\,
      I4 => \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]\(0),
      I5 => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg[5]_1\,
      O => \rd_mux_sel_r_reg[1]_4\
    );
\gen_mux_rd[5].mux_rd_rise1_r1[5]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]\,
      I1 => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg[5]\,
      I2 => \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]\(1),
      I3 => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg[5]_0\,
      I4 => \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]\(0),
      I5 => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg[5]_1\,
      O => \rd_mux_sel_r_reg[1]_20\
    );
\gen_mux_rd[5].mux_rd_rise2_r1[5]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]\,
      I1 => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg[5]\,
      I2 => \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]\(1),
      I3 => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg[5]_0\,
      I4 => \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]\(0),
      I5 => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg[5]_1\,
      O => \rd_mux_sel_r_reg[1]_36\
    );
\gen_mux_rd[5].mux_rd_rise3_r1[5]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]\,
      I1 => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg[5]\,
      I2 => \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]\(1),
      I3 => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg[5]_0\,
      I4 => \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]\(0),
      I5 => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg[5]_1\,
      O => \rd_mux_sel_r_reg[1]_52\
    );
\gen_mux_rd[6].mux_rd_fall0_r1[6]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]\,
      I1 => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg[6]\,
      I2 => \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]\(1),
      I3 => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg[6]_0\,
      I4 => \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]\(0),
      I5 => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg[6]_1\,
      O => \rd_mux_sel_r_reg[1]_13\
    );
\gen_mux_rd[6].mux_rd_fall1_r1[6]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]\,
      I1 => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg[6]\,
      I2 => \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]\(1),
      I3 => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg[6]_0\,
      I4 => \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]\(0),
      I5 => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg[6]_1\,
      O => \rd_mux_sel_r_reg[1]_29\
    );
\gen_mux_rd[6].mux_rd_fall2_r1[6]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]\,
      I1 => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg[6]\,
      I2 => \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]\(1),
      I3 => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg[6]_0\,
      I4 => \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]\(0),
      I5 => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg[6]_1\,
      O => \rd_mux_sel_r_reg[1]_45\
    );
\gen_mux_rd[6].mux_rd_fall3_r1[6]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]\,
      I1 => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg[6]\,
      I2 => \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]\(1),
      I3 => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg[6]_0\,
      I4 => \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]\(0),
      I5 => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg[6]_1\,
      O => \rd_mux_sel_r_reg[1]_61\
    );
\gen_mux_rd[6].mux_rd_rise0_r1[6]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]\,
      I1 => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg[6]\,
      I2 => \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]\(1),
      I3 => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg[6]_0\,
      I4 => \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]\(0),
      I5 => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg[6]_1\,
      O => \rd_mux_sel_r_reg[1]_5\
    );
\gen_mux_rd[6].mux_rd_rise1_r1[6]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]\,
      I1 => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg[6]\,
      I2 => \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]\(1),
      I3 => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg[6]_0\,
      I4 => \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]\(0),
      I5 => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg[6]_1\,
      O => \rd_mux_sel_r_reg[1]_21\
    );
\gen_mux_rd[6].mux_rd_rise2_r1[6]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]\,
      I1 => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg[6]\,
      I2 => \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]\(1),
      I3 => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg[6]_0\,
      I4 => \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]\(0),
      I5 => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg[6]_1\,
      O => \rd_mux_sel_r_reg[1]_37\
    );
\gen_mux_rd[6].mux_rd_rise3_r1[6]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]\,
      I1 => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg[6]\,
      I2 => \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]\(1),
      I3 => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg[6]_0\,
      I4 => \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]\(0),
      I5 => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg[6]_1\,
      O => \rd_mux_sel_r_reg[1]_53\
    );
\gen_mux_rd[7].mux_rd_fall0_r1[7]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]\,
      I1 => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg[7]\,
      I2 => \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]\(1),
      I3 => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg[7]_0\,
      I4 => \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]\(0),
      I5 => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg[7]_1\,
      O => \rd_mux_sel_r_reg[1]_14\
    );
\gen_mux_rd[7].mux_rd_fall1_r1[7]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]\,
      I1 => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg[7]\,
      I2 => \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]\(1),
      I3 => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg[7]_0\,
      I4 => \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]\(0),
      I5 => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg[7]_1\,
      O => \rd_mux_sel_r_reg[1]_30\
    );
\gen_mux_rd[7].mux_rd_fall2_r1[7]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]\,
      I1 => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg[7]\,
      I2 => \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]\(1),
      I3 => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg[7]_0\,
      I4 => \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]\(0),
      I5 => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg[7]_1\,
      O => \rd_mux_sel_r_reg[1]_46\
    );
\gen_mux_rd[7].mux_rd_fall3_r1[7]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]\,
      I1 => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7]\,
      I2 => \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]\(1),
      I3 => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7]_0\,
      I4 => \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]\(0),
      I5 => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7]_1\,
      O => \rd_mux_sel_r_reg[1]_62\
    );
\gen_mux_rd[7].mux_rd_rise0_r1[7]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]\,
      I1 => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg[7]\,
      I2 => \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]\(1),
      I3 => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg[7]_0\,
      I4 => \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]\(0),
      I5 => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg[7]_1\,
      O => \rd_mux_sel_r_reg[1]_6\
    );
\gen_mux_rd[7].mux_rd_rise1_r1[7]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]\,
      I1 => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg[7]\,
      I2 => \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]\(1),
      I3 => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg[7]_0\,
      I4 => \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]\(0),
      I5 => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg[7]_1\,
      O => \rd_mux_sel_r_reg[1]_22\
    );
\gen_mux_rd[7].mux_rd_rise2_r1[7]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]\,
      I1 => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg[7]\,
      I2 => \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]\(1),
      I3 => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg[7]_0\,
      I4 => \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]\(0),
      I5 => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg[7]_1\,
      O => \rd_mux_sel_r_reg[1]_38\
    );
\gen_mux_rd[7].mux_rd_rise3_r1[7]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]\,
      I1 => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise3_r_reg[7]\,
      I2 => \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]\(1),
      I3 => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise3_r_reg[7]_0\,
      I4 => \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]\(0),
      I5 => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise3_r_reg[7]_1\,
      O => \rd_mux_sel_r_reg[1]_54\
    );
\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r[0]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]\,
      I1 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg[0]\,
      I2 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2\(1),
      I3 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg[0]_0\,
      I4 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2\(0),
      I5 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg[0]_1\,
      O => \po_stg2_wrcal_cnt_reg[1]_15\
    );
\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r[0]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]\,
      I1 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg[0]\,
      I2 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2\(1),
      I3 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg[0]_0\,
      I4 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2\(0),
      I5 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg[0]_1\,
      O => \po_stg2_wrcal_cnt_reg[1]_55\
    );
\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r[0]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]\,
      I1 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg[0]\,
      I2 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2\(1),
      I3 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg[0]_0\,
      I4 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2\(0),
      I5 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg[0]_1\,
      O => \po_stg2_wrcal_cnt_reg[1]_31\
    );
\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r[0]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]\,
      I1 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg[0]\,
      I2 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2\(1),
      I3 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg[0]_0\,
      I4 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2\(0),
      I5 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg[0]_1\,
      O => \po_stg2_wrcal_cnt_reg[1]_7\
    );
\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r[0]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]\,
      I1 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg[0]\,
      I2 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2\(1),
      I3 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg[0]_0\,
      I4 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2\(0),
      I5 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg[0]_1\,
      O => \po_stg2_wrcal_cnt_reg[1]_47\
    );
\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r[0]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]\,
      I1 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]\,
      I2 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2\(1),
      I3 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_0\,
      I4 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2\(0),
      I5 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_1\,
      O => \po_stg2_wrcal_cnt_reg[1]\
    );
\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise2_r[0]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]\,
      I1 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise2_r_reg[0]\,
      I2 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2\(1),
      I3 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise2_r_reg[0]_0\,
      I4 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2\(0),
      I5 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise2_r_reg[0]_1\,
      O => \po_stg2_wrcal_cnt_reg[1]_23\
    );
\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r[0]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]\,
      I1 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg[0]\,
      I2 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2\(1),
      I3 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg[0]_0\,
      I4 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2\(0),
      I5 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg[0]_1\,
      O => \po_stg2_wrcal_cnt_reg[1]_39\
    );
\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r[1]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]\,
      I1 => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg[1]\,
      I2 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2\(1),
      I3 => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg[1]_0\,
      I4 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2\(0),
      I5 => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg[1]_1\,
      O => \po_stg2_wrcal_cnt_reg[1]_16\
    );
\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r[1]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]\,
      I1 => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg[1]\,
      I2 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2\(1),
      I3 => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg[1]_0\,
      I4 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2\(0),
      I5 => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg[1]_1\,
      O => \po_stg2_wrcal_cnt_reg[1]_56\
    );
\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r[1]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]\,
      I1 => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg[1]\,
      I2 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2\(1),
      I3 => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg[1]_0\,
      I4 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2\(0),
      I5 => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg[1]_1\,
      O => \po_stg2_wrcal_cnt_reg[1]_32\
    );
\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r[1]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]\,
      I1 => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg[1]\,
      I2 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2\(1),
      I3 => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg[1]_0\,
      I4 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2\(0),
      I5 => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg[1]_1\,
      O => \po_stg2_wrcal_cnt_reg[1]_8\
    );
\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r[1]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]\,
      I1 => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg[1]\,
      I2 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2\(1),
      I3 => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg[1]_0\,
      I4 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2\(0),
      I5 => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg[1]_1\,
      O => \po_stg2_wrcal_cnt_reg[1]_48\
    );
\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r[1]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]\,
      I1 => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg[1]\,
      I2 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2\(1),
      I3 => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg[1]_0\,
      I4 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2\(0),
      I5 => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg[1]_1\,
      O => \po_stg2_wrcal_cnt_reg[1]_0\
    );
\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r[1]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]\,
      I1 => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg[1]\,
      I2 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2\(1),
      I3 => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg[1]_0\,
      I4 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2\(0),
      I5 => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg[1]_1\,
      O => \po_stg2_wrcal_cnt_reg[1]_24\
    );
\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r[1]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]\,
      I1 => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg[1]\,
      I2 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2\(1),
      I3 => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg[1]_0\,
      I4 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2\(0),
      I5 => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg[1]_1\,
      O => \po_stg2_wrcal_cnt_reg[1]_40\
    );
\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r[2]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]\,
      I1 => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg[2]\,
      I2 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2\(1),
      I3 => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg[2]_0\,
      I4 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2\(0),
      I5 => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg[2]_1\,
      O => \po_stg2_wrcal_cnt_reg[1]_17\
    );
\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r[2]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]\,
      I1 => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg[2]\,
      I2 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2\(1),
      I3 => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg[2]_0\,
      I4 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2\(0),
      I5 => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg[2]_1\,
      O => \po_stg2_wrcal_cnt_reg[1]_57\
    );
\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r[2]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]\,
      I1 => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg[2]\,
      I2 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2\(1),
      I3 => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg[2]_0\,
      I4 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2\(0),
      I5 => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg[2]_1\,
      O => \po_stg2_wrcal_cnt_reg[1]_33\
    );
\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r[2]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]\,
      I1 => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg[2]\,
      I2 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2\(1),
      I3 => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg[2]_0\,
      I4 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2\(0),
      I5 => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg[2]_1\,
      O => \po_stg2_wrcal_cnt_reg[1]_9\
    );
\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r[2]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]\,
      I1 => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg[2]\,
      I2 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2\(1),
      I3 => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg[2]_0\,
      I4 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2\(0),
      I5 => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg[2]_1\,
      O => \po_stg2_wrcal_cnt_reg[1]_49\
    );
\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r[2]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]\,
      I1 => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg[2]\,
      I2 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2\(1),
      I3 => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg[2]_0\,
      I4 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2\(0),
      I5 => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg[2]_1\,
      O => \po_stg2_wrcal_cnt_reg[1]_1\
    );
\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r[2]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]\,
      I1 => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg[2]\,
      I2 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2\(1),
      I3 => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg[2]_0\,
      I4 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2\(0),
      I5 => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg[2]_1\,
      O => \po_stg2_wrcal_cnt_reg[1]_25\
    );
\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r[2]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]\,
      I1 => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg[2]\,
      I2 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2\(1),
      I3 => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg[2]_0\,
      I4 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2\(0),
      I5 => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg[2]_1\,
      O => \po_stg2_wrcal_cnt_reg[1]_41\
    );
\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r[3]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]\,
      I1 => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg[3]\,
      I2 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2\(1),
      I3 => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg[3]_0\,
      I4 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2\(0),
      I5 => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg[3]_1\,
      O => \po_stg2_wrcal_cnt_reg[1]_18\
    );
\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r[3]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]\,
      I1 => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg[3]\,
      I2 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2\(1),
      I3 => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg[3]_0\,
      I4 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2\(0),
      I5 => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg[3]_1\,
      O => \po_stg2_wrcal_cnt_reg[1]_58\
    );
\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r[3]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]\,
      I1 => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg[3]\,
      I2 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2\(1),
      I3 => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg[3]_0\,
      I4 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2\(0),
      I5 => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg[3]_1\,
      O => \po_stg2_wrcal_cnt_reg[1]_34\
    );
\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r[3]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]\,
      I1 => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg[3]\,
      I2 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2\(1),
      I3 => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg[3]_0\,
      I4 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2\(0),
      I5 => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg[3]_1\,
      O => \po_stg2_wrcal_cnt_reg[1]_10\
    );
\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r[3]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]\,
      I1 => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg[3]\,
      I2 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2\(1),
      I3 => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg[3]_0\,
      I4 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2\(0),
      I5 => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg[3]_1\,
      O => \po_stg2_wrcal_cnt_reg[1]_50\
    );
\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r[3]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]\,
      I1 => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg[3]\,
      I2 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2\(1),
      I3 => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg[3]_0\,
      I4 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2\(0),
      I5 => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg[3]_1\,
      O => \po_stg2_wrcal_cnt_reg[1]_2\
    );
\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r[3]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]\,
      I1 => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg[3]\,
      I2 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2\(1),
      I3 => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg[3]_0\,
      I4 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2\(0),
      I5 => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg[3]_1\,
      O => \po_stg2_wrcal_cnt_reg[1]_26\
    );
\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise3_r[3]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]\,
      I1 => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise3_r_reg[3]\,
      I2 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2\(1),
      I3 => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise3_r_reg[3]_0\,
      I4 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2\(0),
      I5 => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise3_r_reg[3]_1\,
      O => \po_stg2_wrcal_cnt_reg[1]_42\
    );
\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r[4]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]\,
      I1 => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg[4]\,
      I2 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2\(1),
      I3 => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg[4]_0\,
      I4 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2\(0),
      I5 => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg[4]_1\,
      O => \po_stg2_wrcal_cnt_reg[1]_19\
    );
\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r[4]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]\,
      I1 => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg[4]\,
      I2 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2\(1),
      I3 => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg[4]_0\,
      I4 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2\(0),
      I5 => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg[4]_1\,
      O => \po_stg2_wrcal_cnt_reg[1]_59\
    );
\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r[4]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]\,
      I1 => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg[4]\,
      I2 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2\(1),
      I3 => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg[4]_0\,
      I4 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2\(0),
      I5 => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg[4]_1\,
      O => \po_stg2_wrcal_cnt_reg[1]_35\
    );
\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r[4]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]\,
      I1 => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg[4]\,
      I2 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2\(1),
      I3 => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg[4]_0\,
      I4 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2\(0),
      I5 => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg[4]_1\,
      O => \po_stg2_wrcal_cnt_reg[1]_11\
    );
\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r[4]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]\,
      I1 => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg[4]\,
      I2 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2\(1),
      I3 => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg[4]_0\,
      I4 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2\(0),
      I5 => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg[4]_1\,
      O => \po_stg2_wrcal_cnt_reg[1]_51\
    );
\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r[4]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]\,
      I1 => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg[4]\,
      I2 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2\(1),
      I3 => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg[4]_0\,
      I4 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2\(0),
      I5 => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg[4]_1\,
      O => \po_stg2_wrcal_cnt_reg[1]_3\
    );
\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise2_r[4]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]\,
      I1 => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise2_r_reg[4]\,
      I2 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2\(1),
      I3 => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise2_r_reg[4]_0\,
      I4 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2\(0),
      I5 => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise2_r_reg[4]_1\,
      O => \po_stg2_wrcal_cnt_reg[1]_27\
    );
\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r[4]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]\,
      I1 => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg[4]\,
      I2 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2\(1),
      I3 => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg[4]_0\,
      I4 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2\(0),
      I5 => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg[4]_1\,
      O => \po_stg2_wrcal_cnt_reg[1]_43\
    );
\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r[5]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]\,
      I1 => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg[5]\,
      I2 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2\(1),
      I3 => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg[5]_0\,
      I4 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2\(0),
      I5 => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg[5]_1\,
      O => \po_stg2_wrcal_cnt_reg[1]_20\
    );
\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r[5]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]\,
      I1 => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg[5]\,
      I2 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2\(1),
      I3 => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg[5]_0\,
      I4 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2\(0),
      I5 => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg[5]_1\,
      O => \po_stg2_wrcal_cnt_reg[1]_60\
    );
\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r[5]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]\,
      I1 => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg[5]\,
      I2 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2\(1),
      I3 => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg[5]_0\,
      I4 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2\(0),
      I5 => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg[5]_1\,
      O => \po_stg2_wrcal_cnt_reg[1]_36\
    );
\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r[5]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]\,
      I1 => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg[5]\,
      I2 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2\(1),
      I3 => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg[5]_0\,
      I4 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2\(0),
      I5 => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg[5]_1\,
      O => \po_stg2_wrcal_cnt_reg[1]_12\
    );
\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r[5]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]\,
      I1 => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg[5]\,
      I2 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2\(1),
      I3 => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg[5]_0\,
      I4 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2\(0),
      I5 => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg[5]_1\,
      O => \po_stg2_wrcal_cnt_reg[1]_52\
    );
\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r[5]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]\,
      I1 => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg[5]\,
      I2 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2\(1),
      I3 => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg[5]_0\,
      I4 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2\(0),
      I5 => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg[5]_1\,
      O => \po_stg2_wrcal_cnt_reg[1]_4\
    );
\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r[5]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]\,
      I1 => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg[5]\,
      I2 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2\(1),
      I3 => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg[5]_0\,
      I4 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2\(0),
      I5 => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg[5]_1\,
      O => \po_stg2_wrcal_cnt_reg[1]_28\
    );
\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r[5]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]\,
      I1 => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg[5]\,
      I2 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2\(1),
      I3 => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg[5]_0\,
      I4 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2\(0),
      I5 => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg[5]_1\,
      O => \po_stg2_wrcal_cnt_reg[1]_44\
    );
\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r[6]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]\,
      I1 => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg[6]\,
      I2 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2\(1),
      I3 => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg[6]_0\,
      I4 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2\(0),
      I5 => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg[6]_1\,
      O => \po_stg2_wrcal_cnt_reg[1]_21\
    );
\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r[6]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]\,
      I1 => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg[6]\,
      I2 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2\(1),
      I3 => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg[6]_0\,
      I4 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2\(0),
      I5 => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg[6]_1\,
      O => \po_stg2_wrcal_cnt_reg[1]_61\
    );
\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r[6]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]\,
      I1 => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg[6]\,
      I2 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2\(1),
      I3 => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg[6]_0\,
      I4 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2\(0),
      I5 => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg[6]_1\,
      O => \po_stg2_wrcal_cnt_reg[1]_37\
    );
\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r[6]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]\,
      I1 => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg[6]\,
      I2 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2\(1),
      I3 => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg[6]_0\,
      I4 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2\(0),
      I5 => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg[6]_1\,
      O => \po_stg2_wrcal_cnt_reg[1]_13\
    );
\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r[6]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]\,
      I1 => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg[6]\,
      I2 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2\(1),
      I3 => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg[6]_0\,
      I4 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2\(0),
      I5 => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg[6]_1\,
      O => \po_stg2_wrcal_cnt_reg[1]_53\
    );
\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r[6]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]\,
      I1 => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg[6]\,
      I2 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2\(1),
      I3 => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg[6]_0\,
      I4 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2\(0),
      I5 => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg[6]_1\,
      O => \po_stg2_wrcal_cnt_reg[1]_5\
    );
\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r[6]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]\,
      I1 => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg[6]\,
      I2 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2\(1),
      I3 => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg[6]_0\,
      I4 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2\(0),
      I5 => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg[6]_1\,
      O => \po_stg2_wrcal_cnt_reg[1]_29\
    );
\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r[6]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]\,
      I1 => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg[6]\,
      I2 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2\(1),
      I3 => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg[6]_0\,
      I4 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2\(0),
      I5 => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg[6]_1\,
      O => \po_stg2_wrcal_cnt_reg[1]_45\
    );
\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r[7]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]\,
      I1 => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg[7]\,
      I2 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2\(1),
      I3 => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg[7]_0\,
      I4 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2\(0),
      I5 => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg[7]_1\,
      O => \po_stg2_wrcal_cnt_reg[1]_22\
    );
\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r[7]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]\,
      I1 => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg[7]\,
      I2 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2\(1),
      I3 => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg[7]_0\,
      I4 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2\(0),
      I5 => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg[7]_1\,
      O => \po_stg2_wrcal_cnt_reg[1]_62\
    );
\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r[7]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]\,
      I1 => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg[7]\,
      I2 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2\(1),
      I3 => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg[7]_0\,
      I4 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2\(0),
      I5 => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg[7]_1\,
      O => \po_stg2_wrcal_cnt_reg[1]_38\
    );
\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r[7]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]\,
      I1 => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7]\,
      I2 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2\(1),
      I3 => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7]_0\,
      I4 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2\(0),
      I5 => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7]_1\,
      O => \po_stg2_wrcal_cnt_reg[1]_14\
    );
\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r[7]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]\,
      I1 => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg[7]\,
      I2 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2\(1),
      I3 => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg[7]_0\,
      I4 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2\(0),
      I5 => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg[7]_1\,
      O => \po_stg2_wrcal_cnt_reg[1]_54\
    );
\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r[7]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]\,
      I1 => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg[7]\,
      I2 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2\(1),
      I3 => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg[7]_0\,
      I4 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2\(0),
      I5 => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg[7]_1\,
      O => \po_stg2_wrcal_cnt_reg[1]_6\
    );
\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r[7]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]\,
      I1 => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg[7]\,
      I2 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2\(1),
      I3 => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg[7]_0\,
      I4 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2\(0),
      I5 => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg[7]_1\,
      O => \po_stg2_wrcal_cnt_reg[1]_30\
    );
\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise3_r[7]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]\,
      I1 => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise3_r_reg[7]\,
      I2 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2\(1),
      I3 => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise3_r_reg[7]_0\,
      I4 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2\(0),
      I5 => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise3_r_reg[7]_1\,
      O => \po_stg2_wrcal_cnt_reg[1]_46\
    );
mem_reg_0_3_12_17: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 2) => B"000",
      ADDRA(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRB(4 downto 2) => B"000",
      ADDRB(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRC(4 downto 2) => B"000",
      ADDRC(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRD(4 downto 2) => B"000",
      ADDRD(1 downto 0) => wr_ptr(1 downto 0),
      DIA(1 downto 0) => Q(1 downto 0),
      DIB(1 downto 0) => Q(3 downto 2),
      DIC(1 downto 0) => Q(5 downto 4),
      DID(1 downto 0) => B"00",
      DOA(1) => mem_reg_0_3_12_17_n_0,
      DOA(0) => mem_reg_0_3_12_17_n_1,
      DOB(1) => mem_reg_0_3_12_17_n_2,
      DOB(0) => mem_reg_0_3_12_17_n_3,
      DOC(1 downto 0) => mem_out(17 downto 16),
      DOD(1 downto 0) => NLW_mem_reg_0_3_12_17_DOD_UNCONNECTED(1 downto 0),
      WCLK => \rd_ptr_reg[1]_0\,
      WE => wr_en
    );
\mem_reg_0_3_12_17_i_1__4\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0151"
    )
        port map (
      I0 => \my_full_reg[1]_0\,
      I1 => my_full(0),
      I2 => \my_full_reg[1]_1\,
      I3 => my_empty(2),
      O => wr_en
    );
mem_reg_0_3_18_23: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 2) => B"000",
      ADDRA(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRB(4 downto 2) => B"000",
      ADDRB(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRC(4 downto 2) => B"000",
      ADDRC(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRD(4 downto 2) => B"000",
      ADDRD(1 downto 0) => wr_ptr(1 downto 0),
      DIA(1 downto 0) => Q(7 downto 6),
      DIB(1 downto 0) => Q(9 downto 8),
      DIC(1 downto 0) => Q(11 downto 10),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => mem_out(19 downto 18),
      DOB(1 downto 0) => mem_out(21 downto 20),
      DOC(1 downto 0) => mem_out(23 downto 22),
      DOD(1 downto 0) => NLW_mem_reg_0_3_18_23_DOD_UNCONNECTED(1 downto 0),
      WCLK => \rd_ptr_reg[1]_0\,
      WE => wr_en
    );
mem_reg_0_3_24_29: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 2) => B"000",
      ADDRA(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRB(4 downto 2) => B"000",
      ADDRB(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRC(4 downto 2) => B"000",
      ADDRC(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRD(4 downto 2) => B"000",
      ADDRD(1 downto 0) => wr_ptr(1 downto 0),
      DIA(1 downto 0) => Q(13 downto 12),
      DIB(1 downto 0) => Q(15 downto 14),
      DIC(1 downto 0) => Q(17 downto 16),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => mem_out(25 downto 24),
      DOB(1 downto 0) => mem_out(27 downto 26),
      DOC(1 downto 0) => mem_out(29 downto 28),
      DOD(1 downto 0) => NLW_mem_reg_0_3_24_29_DOD_UNCONNECTED(1 downto 0),
      WCLK => \rd_ptr_reg[1]_0\,
      WE => wr_en
    );
mem_reg_0_3_30_35: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 2) => B"000",
      ADDRA(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRB(4 downto 2) => B"000",
      ADDRB(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRC(4 downto 2) => B"000",
      ADDRC(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRD(4 downto 2) => B"000",
      ADDRD(1 downto 0) => wr_ptr(1 downto 0),
      DIA(1 downto 0) => Q(19 downto 18),
      DIB(1 downto 0) => Q(21 downto 20),
      DIC(1 downto 0) => Q(23 downto 22),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => mem_out(31 downto 30),
      DOB(1 downto 0) => mem_out(33 downto 32),
      DOC(1 downto 0) => mem_out(35 downto 34),
      DOD(1 downto 0) => NLW_mem_reg_0_3_30_35_DOD_UNCONNECTED(1 downto 0),
      WCLK => \rd_ptr_reg[1]_0\,
      WE => wr_en
    );
mem_reg_0_3_36_41: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 2) => B"000",
      ADDRA(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRB(4 downto 2) => B"000",
      ADDRB(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRC(4 downto 2) => B"000",
      ADDRC(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRD(4 downto 2) => B"000",
      ADDRD(1 downto 0) => wr_ptr(1 downto 0),
      DIA(1 downto 0) => Q(25 downto 24),
      DIB(1 downto 0) => Q(27 downto 26),
      DIC(1 downto 0) => Q(29 downto 28),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => mem_out(37 downto 36),
      DOB(1 downto 0) => mem_out(39 downto 38),
      DOC(1 downto 0) => mem_out(41 downto 40),
      DOD(1 downto 0) => NLW_mem_reg_0_3_36_41_DOD_UNCONNECTED(1 downto 0),
      WCLK => \rd_ptr_reg[1]_0\,
      WE => wr_en
    );
mem_reg_0_3_42_47: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 2) => B"000",
      ADDRA(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRB(4 downto 2) => B"000",
      ADDRB(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRC(4 downto 2) => B"000",
      ADDRC(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRD(4 downto 2) => B"000",
      ADDRD(1 downto 0) => wr_ptr(1 downto 0),
      DIA(1 downto 0) => Q(31 downto 30),
      DIB(1 downto 0) => Q(33 downto 32),
      DIC(1 downto 0) => Q(35 downto 34),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => mem_out(43 downto 42),
      DOB(1 downto 0) => mem_out(45 downto 44),
      DOC(1 downto 0) => mem_out(47 downto 46),
      DOD(1 downto 0) => NLW_mem_reg_0_3_42_47_DOD_UNCONNECTED(1 downto 0),
      WCLK => \rd_ptr_reg[1]_0\,
      WE => wr_en
    );
mem_reg_0_3_48_53: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 2) => B"000",
      ADDRA(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRB(4 downto 2) => B"000",
      ADDRB(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRC(4 downto 2) => B"000",
      ADDRC(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRD(4 downto 2) => B"000",
      ADDRD(1 downto 0) => wr_ptr(1 downto 0),
      DIA(1 downto 0) => Q(37 downto 36),
      DIB(1 downto 0) => Q(39 downto 38),
      DIC(1 downto 0) => Q(41 downto 40),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => mem_out(49 downto 48),
      DOB(1 downto 0) => mem_out(51 downto 50),
      DOC(1 downto 0) => mem_out(53 downto 52),
      DOD(1 downto 0) => NLW_mem_reg_0_3_48_53_DOD_UNCONNECTED(1 downto 0),
      WCLK => \rd_ptr_reg[1]_0\,
      WE => wr_en
    );
mem_reg_0_3_54_59: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 2) => B"000",
      ADDRA(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRB(4 downto 2) => B"000",
      ADDRB(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRC(4 downto 2) => B"000",
      ADDRC(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRD(4 downto 2) => B"000",
      ADDRD(1 downto 0) => wr_ptr(1 downto 0),
      DIA(1 downto 0) => Q(43 downto 42),
      DIB(1 downto 0) => Q(45 downto 44),
      DIC(1 downto 0) => Q(47 downto 46),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => mem_out(55 downto 54),
      DOB(1 downto 0) => mem_out(57 downto 56),
      DOC(1 downto 0) => mem_out(59 downto 58),
      DOD(1 downto 0) => NLW_mem_reg_0_3_54_59_DOD_UNCONNECTED(1 downto 0),
      WCLK => \rd_ptr_reg[1]_0\,
      WE => wr_en
    );
mem_reg_0_3_60_65: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 2) => B"000",
      ADDRA(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRB(4 downto 2) => B"000",
      ADDRB(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRC(4 downto 2) => B"000",
      ADDRC(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRD(4 downto 2) => B"000",
      ADDRD(1 downto 0) => wr_ptr(1 downto 0),
      DIA(1 downto 0) => Q(49 downto 48),
      DIB(1 downto 0) => Q(51 downto 50),
      DIC(1 downto 0) => Q(53 downto 52),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => mem_out(61 downto 60),
      DOB(1 downto 0) => mem_out(63 downto 62),
      DOC(1 downto 0) => mem_out(65 downto 64),
      DOD(1 downto 0) => NLW_mem_reg_0_3_60_65_DOD_UNCONNECTED(1 downto 0),
      WCLK => \rd_ptr_reg[1]_0\,
      WE => wr_en
    );
mem_reg_0_3_66_71: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 2) => B"000",
      ADDRA(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRB(4 downto 2) => B"000",
      ADDRB(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRC(4 downto 2) => B"000",
      ADDRC(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRD(4 downto 2) => B"000",
      ADDRD(1 downto 0) => wr_ptr(1 downto 0),
      DIA(1 downto 0) => Q(55 downto 54),
      DIB(1 downto 0) => Q(57 downto 56),
      DIC(1 downto 0) => Q(59 downto 58),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => mem_out(67 downto 66),
      DOB(1 downto 0) => mem_out(69 downto 68),
      DOC(1 downto 0) => mem_out(71 downto 70),
      DOD(1 downto 0) => NLW_mem_reg_0_3_66_71_DOD_UNCONNECTED(1 downto 0),
      WCLK => \rd_ptr_reg[1]_0\,
      WE => wr_en
    );
mem_reg_0_3_72_77: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 2) => B"000",
      ADDRA(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRB(4 downto 2) => B"000",
      ADDRB(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRC(4 downto 2) => B"000",
      ADDRC(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRD(4 downto 2) => B"000",
      ADDRD(1 downto 0) => wr_ptr(1 downto 0),
      DIA(1 downto 0) => Q(61 downto 60),
      DIB(1 downto 0) => Q(63 downto 62),
      DIC(1 downto 0) => Q(65 downto 64),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => mem_out(73 downto 72),
      DOB(1 downto 0) => mem_out(75 downto 74),
      DOC(1 downto 0) => mem_out(77 downto 76),
      DOD(1 downto 0) => NLW_mem_reg_0_3_72_77_DOD_UNCONNECTED(1 downto 0),
      WCLK => \rd_ptr_reg[1]_0\,
      WE => wr_en
    );
mem_reg_0_3_78_79: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 2) => B"000",
      ADDRA(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRB(4 downto 2) => B"000",
      ADDRB(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRC(4 downto 2) => B"000",
      ADDRC(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRD(4 downto 2) => B"000",
      ADDRD(1 downto 0) => wr_ptr(1 downto 0),
      DIA(1 downto 0) => Q(67 downto 66),
      DIB(1 downto 0) => B"00",
      DIC(1 downto 0) => B"00",
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => mem_out(79 downto 78),
      DOB(1 downto 0) => NLW_mem_reg_0_3_78_79_DOB_UNCONNECTED(1 downto 0),
      DOC(1 downto 0) => NLW_mem_reg_0_3_78_79_DOC_UNCONNECTED(1 downto 0),
      DOD(1 downto 0) => NLW_mem_reg_0_3_78_79_DOD_UNCONNECTED(1 downto 0),
      WCLK => \rd_ptr_reg[1]_0\,
      WE => wr_en
    );
\my_empty[4]_i_1__6\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0018"
    )
        port map (
      I0 => \my_full_reg[1]_1\,
      I1 => \my_full_reg[1]_0\,
      I2 => my_empty(1),
      I3 => my_full(1),
      O => \my_empty[4]_i_1__6_n_0\
    );
\my_empty[4]_i_2__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00411400"
    )
        port map (
      I0 => my_empty(1),
      I1 => wr_ptr(1),
      I2 => rd_ptr(1),
      I3 => rd_ptr(0),
      I4 => wr_ptr(0),
      O => \my_empty[4]_i_2__2_n_0\
    );
\my_empty_inst__11\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \my_empty_reg[4]_rep_n_0\,
      O => my_empty(4)
    );
\my_empty_inst__12\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \^my_empty_reg[4]_0\,
      O => \^my_empty_reg[4]_1\(0)
    );
\my_empty_inst__13\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \^my_empty_reg[4]_0\,
      O => my_empty(2)
    );
\my_empty_inst__14\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \^my_empty_reg[4]_0\,
      O => my_empty(1)
    );
\my_empty_inst_rep__2\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \my_empty_reg[4]_rep__0_n_0\,
      O => \my_empty_inst_rep__2_n_0\
    );
\my_empty_reg[4]\: unisim.vcomponents.FDSE
     port map (
      C => \rd_ptr_reg[1]_0\,
      CE => \my_empty[4]_i_1__6_n_0\,
      D => \my_empty[4]_i_2__2_n_0\,
      Q => \^my_empty_reg[4]_0\,
      S => ififo_rst
    );
\my_empty_reg[4]_rep\: unisim.vcomponents.FDSE
     port map (
      C => \rd_ptr_reg[1]_0\,
      CE => \my_empty[4]_i_1__6_n_0\,
      D => \my_empty[4]_i_2__2_n_0\,
      Q => \my_empty_reg[4]_rep_n_0\,
      S => ififo_rst
    );
\my_empty_reg[4]_rep__0\: unisim.vcomponents.FDSE
     port map (
      C => \rd_ptr_reg[1]_0\,
      CE => \my_empty[4]_i_1__6_n_0\,
      D => \my_empty[4]_i_2__2_n_0\,
      Q => \my_empty_reg[4]_rep__0_n_0\,
      S => ififo_rst
    );
\my_full[0]_i_1__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAEAABAAAA2AA8"
    )
        port map (
      I0 => my_full(0),
      I1 => \my_full_reg[1]_1\,
      I2 => \my_full_reg[1]_0\,
      I3 => my_full(1),
      I4 => my_empty(1),
      I5 => \my_full[1]_i_2__2_n_0\,
      O => \my_full[0]_i_1__2_n_0\
    );
\my_full[1]_i_1__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"F0F1F070"
    )
        port map (
      I0 => \my_full_reg[1]_1\,
      I1 => \my_full_reg[1]_0\,
      I2 => my_full(1),
      I3 => my_empty(1),
      I4 => \my_full[1]_i_2__2_n_0\,
      O => \my_full[1]_i_1__2_n_0\
    );
\my_full[1]_i_2__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00411400"
    )
        port map (
      I0 => my_full(1),
      I1 => rd_ptr(1),
      I2 => wr_ptr(1),
      I3 => wr_ptr(0),
      I4 => rd_ptr(0),
      O => \my_full[1]_i_2__2_n_0\
    );
\my_full_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \rd_ptr_reg[1]_0\,
      CE => '1',
      D => \my_full[0]_i_1__2_n_0\,
      Q => my_full(0),
      R => ififo_rst
    );
\my_full_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \rd_ptr_reg[1]_0\,
      CE => '1',
      D => \my_full[1]_i_1__2_n_0\,
      Q => my_full(1),
      R => ififo_rst
    );
\rd_ptr[0]_i_1__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"D2"
    )
        port map (
      I0 => \my_full_reg[1]_1\,
      I1 => my_empty(1),
      I2 => rd_ptr(0),
      O => \rd_ptr[0]_i_1__2_n_0\
    );
\rd_ptr[1]_i_1__2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F708"
    )
        port map (
      I0 => rd_ptr(0),
      I1 => \my_full_reg[1]_1\,
      I2 => my_empty(1),
      I3 => rd_ptr(1),
      O => \rd_ptr[1]_i_1__2_n_0\
    );
\rd_ptr_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \rd_ptr_reg[1]_0\,
      CE => '1',
      D => \rd_ptr[0]_i_1__2_n_0\,
      Q => rd_ptr(0),
      R => ififo_rst
    );
\rd_ptr_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \rd_ptr_reg[1]_0\,
      CE => '1',
      D => \rd_ptr[1]_i_1__2_n_0\,
      Q => rd_ptr(1),
      R => ififo_rst
    );
\rd_ptr_timing[0]_i_1__6\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F704"
    )
        port map (
      I0 => rd_ptr(0),
      I1 => \my_full_reg[1]_1\,
      I2 => my_empty(1),
      I3 => rd_ptr_timing(0),
      O => \rd_ptr_timing[0]_i_1__6_n_0\
    );
\rd_ptr_timing[1]_i_1__6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FF6F0060"
    )
        port map (
      I0 => rd_ptr(0),
      I1 => rd_ptr(1),
      I2 => \my_full_reg[1]_1\,
      I3 => my_empty(1),
      I4 => rd_ptr_timing(1),
      O => \rd_ptr_timing[1]_i_1__6_n_0\
    );
\rd_ptr_timing_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \rd_ptr_reg[1]_0\,
      CE => '1',
      D => \rd_ptr_timing[0]_i_1__6_n_0\,
      Q => rd_ptr_timing(0),
      R => ififo_rst
    );
\rd_ptr_timing_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \rd_ptr_reg[1]_0\,
      CE => '1',
      D => \rd_ptr_timing[1]_i_1__6_n_0\,
      Q => rd_ptr_timing(1),
      R => ififo_rst
    );
\wr_ptr[0]_i_1__6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FECE0131"
    )
        port map (
      I0 => my_full(1),
      I1 => \my_full_reg[1]_0\,
      I2 => \my_full_reg[1]_1\,
      I3 => my_empty(1),
      I4 => wr_ptr(0),
      O => \wr_ptr[0]_i_1__6_n_0\
    );
\wr_ptr[1]_i_1__6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFDF5FD00020A02"
    )
        port map (
      I0 => wr_ptr(0),
      I1 => my_full(1),
      I2 => \my_full_reg[1]_0\,
      I3 => \my_full_reg[1]_1\,
      I4 => my_empty(1),
      I5 => wr_ptr(1),
      O => \wr_ptr[1]_i_1__6_n_0\
    );
\wr_ptr[1]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000000001"
    )
        port map (
      I0 => \wr_ptr[1]_i_3__1_n_0\,
      I1 => \my_full_reg[1]_2\,
      I2 => \my_full_reg[1]_3\,
      I3 => \my_full_reg[1]_4\,
      I4 => \my_full_reg[1]_5\,
      I5 => \my_full_reg[1]_6\,
      O => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]\
    );
\wr_ptr[1]_i_2__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000000001"
    )
        port map (
      I0 => \wr_ptr[1]_i_3__1_n_0\,
      I1 => \my_full_reg[1]_2\,
      I2 => \my_full_reg[1]_3\,
      I3 => \my_full_reg[1]_4\,
      I4 => \my_full_reg[1]_7\,
      I5 => \my_full_reg[1]_8\,
      O => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0\
    );
\wr_ptr[1]_i_2__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000000001"
    )
        port map (
      I0 => \wr_ptr[1]_i_3__1_n_0\,
      I1 => \my_full_reg[1]_2\,
      I2 => \my_full_reg[1]_3\,
      I3 => \my_full_reg[1]_4\,
      I4 => \my_full_reg[1]_7\,
      I5 => \my_full_reg[1]_9\,
      O => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1\
    );
\wr_ptr[1]_i_3__1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \my_full_reg[1]_0\,
      I1 => \^my_empty_reg[4]_1\(0),
      O => \wr_ptr[1]_i_3__1_n_0\
    );
\wr_ptr[1]_i_4\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F888"
    )
        port map (
      I0 => \^my_empty_reg[4]_1\(0),
      I1 => \my_full_reg[1]_0\,
      I2 => \wr_ptr[1]_i_2__2\(0),
      I3 => if_empty_r(0),
      O => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_2\
    );
\wr_ptr_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \rd_ptr_reg[1]_0\,
      CE => '1',
      D => \wr_ptr[0]_i_1__6_n_0\,
      Q => wr_ptr(0),
      R => ififo_rst
    );
\wr_ptr_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \rd_ptr_reg[1]_0\,
      CE => '1',
      D => \wr_ptr[1]_i_1__6_n_0\,
      Q => wr_ptr(1),
      R => ififo_rst
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mig_mig_7series_v4_2_ddr_if_post_fifo_33 is
  port (
    \my_empty_reg[4]_0\ : out STD_LOGIC;
    \my_empty_reg[4]_1\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0\ : out STD_LOGIC;
    ififo_rst : in STD_LOGIC;
    \rd_ptr_timing_reg[1]_0\ : in STD_LOGIC;
    \wr_ptr_reg[0]_0\ : in STD_LOGIC;
    \my_full_reg[1]_0\ : in STD_LOGIC;
    \wr_ptr[1]_i_2__6\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    if_empty_r : in STD_LOGIC_VECTOR ( 0 to 0 );
    Q : in STD_LOGIC_VECTOR ( 67 downto 0 );
    \my_full_reg[1]_1\ : in STD_LOGIC;
    \my_full_reg[1]_2\ : in STD_LOGIC;
    \my_full_reg[1]_3\ : in STD_LOGIC;
    \my_full_reg[1]_4\ : in STD_LOGIC;
    \my_full_reg[1]_5\ : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of mig_mig_7series_v4_2_ddr_if_post_fifo_33 : entity is "mig_7series_v4_2_ddr_if_post_fifo";
end mig_mig_7series_v4_2_ddr_if_post_fifo_33;

architecture STRUCTURE of mig_mig_7series_v4_2_ddr_if_post_fifo_33 is
  signal mem_out : STD_LOGIC_VECTOR ( 79 downto 16 );
  signal mem_reg_0_3_12_17_n_0 : STD_LOGIC;
  signal mem_reg_0_3_12_17_n_1 : STD_LOGIC;
  signal mem_reg_0_3_12_17_n_2 : STD_LOGIC;
  signal mem_reg_0_3_12_17_n_3 : STD_LOGIC;
  signal my_empty : STD_LOGIC_VECTOR ( 4 downto 1 );
  signal \my_empty[4]_i_1__5_n_0\ : STD_LOGIC;
  signal \my_empty[4]_i_2__1_n_0\ : STD_LOGIC;
  signal \my_empty_inst_rep__1_n_0\ : STD_LOGIC;
  signal \^my_empty_reg[4]_0\ : STD_LOGIC;
  signal \^my_empty_reg[4]_1\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \my_empty_reg[4]_rep__0_n_0\ : STD_LOGIC;
  signal \my_empty_reg[4]_rep_n_0\ : STD_LOGIC;
  signal my_full : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \my_full[0]_i_1__1_n_0\ : STD_LOGIC;
  signal \my_full[1]_i_1__1_n_0\ : STD_LOGIC;
  signal \my_full[1]_i_2__1_n_0\ : STD_LOGIC;
  signal rd_ptr : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \rd_ptr[0]_i_1__1_n_0\ : STD_LOGIC;
  signal \rd_ptr[1]_i_1__1_n_0\ : STD_LOGIC;
  signal rd_ptr_timing : STD_LOGIC_VECTOR ( 1 downto 0 );
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of rd_ptr_timing : signal is "true";
  attribute syn_maxfan : string;
  attribute syn_maxfan of rd_ptr_timing : signal is "10";
  signal \rd_ptr_timing[0]_i_1__4_n_0\ : STD_LOGIC;
  signal \rd_ptr_timing[1]_i_1__4_n_0\ : STD_LOGIC;
  signal wr_en : STD_LOGIC;
  attribute MAX_FANOUT : string;
  attribute MAX_FANOUT of wr_en : signal is "40";
  attribute RTL_MAX_FANOUT : string;
  attribute RTL_MAX_FANOUT of wr_en : signal is "found";
  attribute syn_maxfan of wr_en : signal is "10";
  signal wr_ptr : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \wr_ptr[0]_i_1__4_n_0\ : STD_LOGIC;
  signal \wr_ptr[1]_i_1__4_n_0\ : STD_LOGIC;
  signal \wr_ptr[1]_i_3__0_n_0\ : STD_LOGIC;
  signal NLW_mem_reg_0_3_12_17_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_3_18_23_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_3_24_29_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_3_30_35_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_3_36_41_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_3_42_47_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_3_48_53_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_3_54_59_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_3_60_65_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_3_66_71_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_3_72_77_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_3_78_79_DOB_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_3_78_79_DOC_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_3_78_79_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \app_rd_data[112]_INST_0\ : label is "soft_lutpair794";
  attribute SOFT_HLUTNM of \app_rd_data[113]_INST_0\ : label is "soft_lutpair794";
  attribute SOFT_HLUTNM of \app_rd_data[114]_INST_0\ : label is "soft_lutpair785";
  attribute SOFT_HLUTNM of \app_rd_data[115]_INST_0\ : label is "soft_lutpair792";
  attribute SOFT_HLUTNM of \app_rd_data[116]_INST_0\ : label is "soft_lutpair791";
  attribute SOFT_HLUTNM of \app_rd_data[117]_INST_0\ : label is "soft_lutpair782";
  attribute SOFT_HLUTNM of \app_rd_data[118]_INST_0\ : label is "soft_lutpair789";
  attribute SOFT_HLUTNM of \app_rd_data[119]_INST_0\ : label is "soft_lutpair787";
  attribute SOFT_HLUTNM of \app_rd_data[176]_INST_0\ : label is "soft_lutpair775";
  attribute SOFT_HLUTNM of \app_rd_data[177]_INST_0\ : label is "soft_lutpair770";
  attribute SOFT_HLUTNM of \app_rd_data[178]_INST_0\ : label is "soft_lutpair778";
  attribute SOFT_HLUTNM of \app_rd_data[179]_INST_0\ : label is "soft_lutpair773";
  attribute SOFT_HLUTNM of \app_rd_data[180]_INST_0\ : label is "soft_lutpair768";
  attribute SOFT_HLUTNM of \app_rd_data[181]_INST_0\ : label is "soft_lutpair777";
  attribute SOFT_HLUTNM of \app_rd_data[182]_INST_0\ : label is "soft_lutpair771";
  attribute SOFT_HLUTNM of \app_rd_data[183]_INST_0\ : label is "soft_lutpair767";
  attribute SOFT_HLUTNM of \app_rd_data[240]_INST_0\ : label is "soft_lutpair795";
  attribute SOFT_HLUTNM of \app_rd_data[241]_INST_0\ : label is "soft_lutpair785";
  attribute SOFT_HLUTNM of \app_rd_data[242]_INST_0\ : label is "soft_lutpair793";
  attribute SOFT_HLUTNM of \app_rd_data[243]_INST_0\ : label is "soft_lutpair790";
  attribute SOFT_HLUTNM of \app_rd_data[244]_INST_0\ : label is "soft_lutpair783";
  attribute SOFT_HLUTNM of \app_rd_data[245]_INST_0\ : label is "soft_lutpair782";
  attribute SOFT_HLUTNM of \app_rd_data[246]_INST_0\ : label is "soft_lutpair788";
  attribute SOFT_HLUTNM of \app_rd_data[247]_INST_0\ : label is "soft_lutpair779";
  attribute SOFT_HLUTNM of \app_rd_data[304]_INST_0\ : label is "soft_lutpair770";
  attribute SOFT_HLUTNM of \app_rd_data[305]_INST_0\ : label is "soft_lutpair780";
  attribute SOFT_HLUTNM of \app_rd_data[306]_INST_0\ : label is "soft_lutpair773";
  attribute SOFT_HLUTNM of \app_rd_data[307]_INST_0\ : label is "soft_lutpair764";
  attribute SOFT_HLUTNM of \app_rd_data[308]_INST_0\ : label is "soft_lutpair777";
  attribute SOFT_HLUTNM of \app_rd_data[309]_INST_0\ : label is "soft_lutpair772";
  attribute SOFT_HLUTNM of \app_rd_data[310]_INST_0\ : label is "soft_lutpair767";
  attribute SOFT_HLUTNM of \app_rd_data[311]_INST_0\ : label is "soft_lutpair776";
  attribute SOFT_HLUTNM of \app_rd_data[368]_INST_0\ : label is "soft_lutpair786";
  attribute SOFT_HLUTNM of \app_rd_data[369]_INST_0\ : label is "soft_lutpair793";
  attribute SOFT_HLUTNM of \app_rd_data[370]_INST_0\ : label is "soft_lutpair792";
  attribute SOFT_HLUTNM of \app_rd_data[371]_INST_0\ : label is "soft_lutpair784";
  attribute SOFT_HLUTNM of \app_rd_data[372]_INST_0\ : label is "soft_lutpair791";
  attribute SOFT_HLUTNM of \app_rd_data[373]_INST_0\ : label is "soft_lutpair781";
  attribute SOFT_HLUTNM of \app_rd_data[374]_INST_0\ : label is "soft_lutpair779";
  attribute SOFT_HLUTNM of \app_rd_data[375]_INST_0\ : label is "soft_lutpair787";
  attribute SOFT_HLUTNM of \app_rd_data[432]_INST_0\ : label is "soft_lutpair764";
  attribute SOFT_HLUTNM of \app_rd_data[433]_INST_0\ : label is "soft_lutpair774";
  attribute SOFT_HLUTNM of \app_rd_data[434]_INST_0\ : label is "soft_lutpair769";
  attribute SOFT_HLUTNM of \app_rd_data[435]_INST_0\ : label is "soft_lutpair775";
  attribute SOFT_HLUTNM of \app_rd_data[436]_INST_0\ : label is "soft_lutpair772";
  attribute SOFT_HLUTNM of \app_rd_data[437]_INST_0\ : label is "soft_lutpair768";
  attribute SOFT_HLUTNM of \app_rd_data[438]_INST_0\ : label is "soft_lutpair776";
  attribute SOFT_HLUTNM of \app_rd_data[439]_INST_0\ : label is "soft_lutpair771";
  attribute SOFT_HLUTNM of \app_rd_data[48]_INST_0\ : label is "soft_lutpair780";
  attribute SOFT_HLUTNM of \app_rd_data[496]_INST_0\ : label is "soft_lutpair795";
  attribute SOFT_HLUTNM of \app_rd_data[497]_INST_0\ : label is "soft_lutpair790";
  attribute SOFT_HLUTNM of \app_rd_data[498]_INST_0\ : label is "soft_lutpair784";
  attribute SOFT_HLUTNM of \app_rd_data[499]_INST_0\ : label is "soft_lutpair786";
  attribute SOFT_HLUTNM of \app_rd_data[49]_INST_0\ : label is "soft_lutpair774";
  attribute SOFT_HLUTNM of \app_rd_data[500]_INST_0\ : label is "soft_lutpair789";
  attribute SOFT_HLUTNM of \app_rd_data[501]_INST_0\ : label is "soft_lutpair781";
  attribute SOFT_HLUTNM of \app_rd_data[502]_INST_0\ : label is "soft_lutpair788";
  attribute SOFT_HLUTNM of \app_rd_data[503]_INST_0\ : label is "soft_lutpair783";
  attribute SOFT_HLUTNM of \app_rd_data[50]_INST_0\ : label is "soft_lutpair769";
  attribute SOFT_HLUTNM of \app_rd_data[51]_INST_0\ : label is "soft_lutpair778";
  attribute SOFT_HLUTNM of \app_rd_data[52]_INST_0\ : label is "soft_lutpair766";
  attribute SOFT_HLUTNM of \app_rd_data[53]_INST_0\ : label is "soft_lutpair765";
  attribute SOFT_HLUTNM of \app_rd_data[54]_INST_0\ : label is "soft_lutpair766";
  attribute SOFT_HLUTNM of \app_rd_data[55]_INST_0\ : label is "soft_lutpair765";
  attribute METHODOLOGY_DRC_VIOS : string;
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_3_12_17 : label is "";
  attribute RTL_RAM_BITS : integer;
  attribute RTL_RAM_BITS of mem_reg_0_3_12_17 : label is 320;
  attribute RTL_RAM_NAME : string;
  attribute RTL_RAM_NAME of mem_reg_0_3_12_17 : label is "dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem";
  attribute ram_addr_begin : integer;
  attribute ram_addr_begin of mem_reg_0_3_12_17 : label is 0;
  attribute ram_addr_end : integer;
  attribute ram_addr_end of mem_reg_0_3_12_17 : label is 3;
  attribute ram_offset : integer;
  attribute ram_offset of mem_reg_0_3_12_17 : label is 0;
  attribute ram_slice_begin : integer;
  attribute ram_slice_begin of mem_reg_0_3_12_17 : label is 12;
  attribute ram_slice_end : integer;
  attribute ram_slice_end of mem_reg_0_3_12_17 : label is 17;
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_3_18_23 : label is "";
  attribute RTL_RAM_BITS of mem_reg_0_3_18_23 : label is 320;
  attribute RTL_RAM_NAME of mem_reg_0_3_18_23 : label is "dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem";
  attribute ram_addr_begin of mem_reg_0_3_18_23 : label is 0;
  attribute ram_addr_end of mem_reg_0_3_18_23 : label is 3;
  attribute ram_offset of mem_reg_0_3_18_23 : label is 0;
  attribute ram_slice_begin of mem_reg_0_3_18_23 : label is 18;
  attribute ram_slice_end of mem_reg_0_3_18_23 : label is 23;
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_3_24_29 : label is "";
  attribute RTL_RAM_BITS of mem_reg_0_3_24_29 : label is 320;
  attribute RTL_RAM_NAME of mem_reg_0_3_24_29 : label is "dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem";
  attribute ram_addr_begin of mem_reg_0_3_24_29 : label is 0;
  attribute ram_addr_end of mem_reg_0_3_24_29 : label is 3;
  attribute ram_offset of mem_reg_0_3_24_29 : label is 0;
  attribute ram_slice_begin of mem_reg_0_3_24_29 : label is 24;
  attribute ram_slice_end of mem_reg_0_3_24_29 : label is 29;
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_3_30_35 : label is "";
  attribute RTL_RAM_BITS of mem_reg_0_3_30_35 : label is 320;
  attribute RTL_RAM_NAME of mem_reg_0_3_30_35 : label is "dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem";
  attribute ram_addr_begin of mem_reg_0_3_30_35 : label is 0;
  attribute ram_addr_end of mem_reg_0_3_30_35 : label is 3;
  attribute ram_offset of mem_reg_0_3_30_35 : label is 0;
  attribute ram_slice_begin of mem_reg_0_3_30_35 : label is 30;
  attribute ram_slice_end of mem_reg_0_3_30_35 : label is 35;
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_3_36_41 : label is "";
  attribute RTL_RAM_BITS of mem_reg_0_3_36_41 : label is 320;
  attribute RTL_RAM_NAME of mem_reg_0_3_36_41 : label is "dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem";
  attribute ram_addr_begin of mem_reg_0_3_36_41 : label is 0;
  attribute ram_addr_end of mem_reg_0_3_36_41 : label is 3;
  attribute ram_offset of mem_reg_0_3_36_41 : label is 0;
  attribute ram_slice_begin of mem_reg_0_3_36_41 : label is 36;
  attribute ram_slice_end of mem_reg_0_3_36_41 : label is 41;
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_3_42_47 : label is "";
  attribute RTL_RAM_BITS of mem_reg_0_3_42_47 : label is 320;
  attribute RTL_RAM_NAME of mem_reg_0_3_42_47 : label is "dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem";
  attribute ram_addr_begin of mem_reg_0_3_42_47 : label is 0;
  attribute ram_addr_end of mem_reg_0_3_42_47 : label is 3;
  attribute ram_offset of mem_reg_0_3_42_47 : label is 0;
  attribute ram_slice_begin of mem_reg_0_3_42_47 : label is 42;
  attribute ram_slice_end of mem_reg_0_3_42_47 : label is 47;
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_3_48_53 : label is "";
  attribute RTL_RAM_BITS of mem_reg_0_3_48_53 : label is 320;
  attribute RTL_RAM_NAME of mem_reg_0_3_48_53 : label is "dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem";
  attribute ram_addr_begin of mem_reg_0_3_48_53 : label is 0;
  attribute ram_addr_end of mem_reg_0_3_48_53 : label is 3;
  attribute ram_offset of mem_reg_0_3_48_53 : label is 0;
  attribute ram_slice_begin of mem_reg_0_3_48_53 : label is 48;
  attribute ram_slice_end of mem_reg_0_3_48_53 : label is 53;
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_3_54_59 : label is "";
  attribute RTL_RAM_BITS of mem_reg_0_3_54_59 : label is 320;
  attribute RTL_RAM_NAME of mem_reg_0_3_54_59 : label is "dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem";
  attribute ram_addr_begin of mem_reg_0_3_54_59 : label is 0;
  attribute ram_addr_end of mem_reg_0_3_54_59 : label is 3;
  attribute ram_offset of mem_reg_0_3_54_59 : label is 0;
  attribute ram_slice_begin of mem_reg_0_3_54_59 : label is 54;
  attribute ram_slice_end of mem_reg_0_3_54_59 : label is 59;
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_3_60_65 : label is "";
  attribute RTL_RAM_BITS of mem_reg_0_3_60_65 : label is 320;
  attribute RTL_RAM_NAME of mem_reg_0_3_60_65 : label is "dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem";
  attribute ram_addr_begin of mem_reg_0_3_60_65 : label is 0;
  attribute ram_addr_end of mem_reg_0_3_60_65 : label is 3;
  attribute ram_offset of mem_reg_0_3_60_65 : label is 0;
  attribute ram_slice_begin of mem_reg_0_3_60_65 : label is 60;
  attribute ram_slice_end of mem_reg_0_3_60_65 : label is 65;
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_3_66_71 : label is "";
  attribute RTL_RAM_BITS of mem_reg_0_3_66_71 : label is 320;
  attribute RTL_RAM_NAME of mem_reg_0_3_66_71 : label is "dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem";
  attribute ram_addr_begin of mem_reg_0_3_66_71 : label is 0;
  attribute ram_addr_end of mem_reg_0_3_66_71 : label is 3;
  attribute ram_offset of mem_reg_0_3_66_71 : label is 0;
  attribute ram_slice_begin of mem_reg_0_3_66_71 : label is 66;
  attribute ram_slice_end of mem_reg_0_3_66_71 : label is 71;
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_3_72_77 : label is "";
  attribute RTL_RAM_BITS of mem_reg_0_3_72_77 : label is 320;
  attribute RTL_RAM_NAME of mem_reg_0_3_72_77 : label is "dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem";
  attribute ram_addr_begin of mem_reg_0_3_72_77 : label is 0;
  attribute ram_addr_end of mem_reg_0_3_72_77 : label is 3;
  attribute ram_offset of mem_reg_0_3_72_77 : label is 0;
  attribute ram_slice_begin of mem_reg_0_3_72_77 : label is 72;
  attribute ram_slice_end of mem_reg_0_3_72_77 : label is 77;
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_3_78_79 : label is "";
  attribute RTL_RAM_BITS of mem_reg_0_3_78_79 : label is 320;
  attribute RTL_RAM_NAME of mem_reg_0_3_78_79 : label is "dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem";
  attribute ram_addr_begin of mem_reg_0_3_78_79 : label is 0;
  attribute ram_addr_end of mem_reg_0_3_78_79 : label is 3;
  attribute ram_offset of mem_reg_0_3_78_79 : label is 0;
  attribute ram_slice_begin of mem_reg_0_3_78_79 : label is 78;
  attribute ram_slice_end of mem_reg_0_3_78_79 : label is 79;
  attribute SOFT_HLUTNM of \my_empty_inst__8\ : label is "soft_lutpair796";
  attribute SOFT_HLUTNM of \my_empty_inst__9\ : label is "soft_lutpair796";
  attribute IS_FANOUT_CONSTRAINED : integer;
  attribute IS_FANOUT_CONSTRAINED of \my_empty_inst_rep__1\ : label is 1;
  attribute ORIG_CELL_NAME : string;
  attribute ORIG_CELL_NAME of \my_empty_reg[4]\ : label is "my_empty_reg[4]";
  attribute ORIG_CELL_NAME of \my_empty_reg[4]_rep\ : label is "my_empty_reg[4]";
  attribute ORIG_CELL_NAME of \my_empty_reg[4]_rep__0\ : label is "my_empty_reg[4]";
  attribute SOFT_HLUTNM of \rd_ptr[0]_i_1__1\ : label is "soft_lutpair763";
  attribute SOFT_HLUTNM of \rd_ptr[1]_i_1__1\ : label is "soft_lutpair763";
  attribute syn_maxfan of \rd_ptr_reg[0]\ : label is "10";
  attribute syn_maxfan of \rd_ptr_reg[1]\ : label is "10";
  attribute KEEP : string;
  attribute KEEP of \rd_ptr_timing_reg[0]\ : label is "yes";
  attribute syn_maxfan of \rd_ptr_timing_reg[0]\ : label is "10";
  attribute KEEP of \rd_ptr_timing_reg[1]\ : label is "yes";
  attribute syn_maxfan of \rd_ptr_timing_reg[1]\ : label is "10";
  attribute SOFT_HLUTNM of \wr_ptr[1]_i_3__0\ : label is "soft_lutpair762";
  attribute SOFT_HLUTNM of \wr_ptr[1]_i_3__3\ : label is "soft_lutpair762";
  attribute syn_maxfan of \wr_ptr_reg[0]\ : label is "10";
  attribute syn_maxfan of \wr_ptr_reg[1]\ : label is "10";
begin
  \my_empty_reg[4]_0\ <= \^my_empty_reg[4]_0\;
  \my_empty_reg[4]_1\(0) <= \^my_empty_reg[4]_1\(0);
\app_rd_data[112]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(5),
      I1 => \my_empty_inst_rep__1_n_0\,
      I2 => mem_out(17),
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]\
    );
\app_rd_data[113]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(13),
      I1 => \my_empty_inst_rep__1_n_0\,
      I2 => mem_out(25),
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]\
    );
\app_rd_data[114]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(21),
      I1 => \my_empty_inst_rep__1_n_0\,
      I2 => mem_out(33),
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]\
    );
\app_rd_data[115]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(29),
      I1 => \my_empty_inst_rep__1_n_0\,
      I2 => mem_out(41),
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]\
    );
\app_rd_data[116]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(37),
      I1 => my_empty(4),
      I2 => mem_out(49),
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]\
    );
\app_rd_data[117]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(45),
      I1 => my_empty(4),
      I2 => mem_out(57),
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]\
    );
\app_rd_data[118]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(53),
      I1 => my_empty(4),
      I2 => mem_out(65),
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]\
    );
\app_rd_data[119]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(61),
      I1 => my_empty(4),
      I2 => mem_out(73),
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]\
    );
\app_rd_data[176]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(6),
      I1 => \my_empty_inst_rep__1_n_0\,
      I2 => mem_out(18),
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]\
    );
\app_rd_data[177]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(14),
      I1 => \my_empty_inst_rep__1_n_0\,
      I2 => mem_out(26),
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]\
    );
\app_rd_data[178]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(22),
      I1 => \my_empty_inst_rep__1_n_0\,
      I2 => mem_out(34),
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]\
    );
\app_rd_data[179]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(30),
      I1 => \my_empty_inst_rep__1_n_0\,
      I2 => mem_out(42),
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]\
    );
\app_rd_data[180]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(38),
      I1 => my_empty(4),
      I2 => mem_out(50),
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]\
    );
\app_rd_data[181]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(46),
      I1 => my_empty(4),
      I2 => mem_out(58),
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]\
    );
\app_rd_data[182]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(54),
      I1 => my_empty(4),
      I2 => mem_out(66),
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]\
    );
\app_rd_data[183]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(62),
      I1 => my_empty(4),
      I2 => mem_out(74),
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]\
    );
\app_rd_data[240]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(7),
      I1 => \my_empty_inst_rep__1_n_0\,
      I2 => mem_out(19),
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]\
    );
\app_rd_data[241]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(15),
      I1 => \my_empty_inst_rep__1_n_0\,
      I2 => mem_out(27),
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]\
    );
\app_rd_data[242]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(23),
      I1 => \my_empty_inst_rep__1_n_0\,
      I2 => mem_out(35),
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]\
    );
\app_rd_data[243]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(31),
      I1 => \my_empty_inst_rep__1_n_0\,
      I2 => mem_out(43),
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]\
    );
\app_rd_data[244]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(39),
      I1 => my_empty(4),
      I2 => mem_out(51),
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]\
    );
\app_rd_data[245]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(47),
      I1 => my_empty(4),
      I2 => mem_out(59),
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]\
    );
\app_rd_data[246]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(55),
      I1 => my_empty(4),
      I2 => mem_out(67),
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]\
    );
\app_rd_data[247]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(63),
      I1 => my_empty(4),
      I2 => mem_out(75),
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]\
    );
\app_rd_data[304]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(8),
      I1 => \my_empty_inst_rep__1_n_0\,
      I2 => mem_out(20),
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]\
    );
\app_rd_data[305]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(16),
      I1 => \my_empty_inst_rep__1_n_0\,
      I2 => mem_out(28),
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]\
    );
\app_rd_data[306]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(24),
      I1 => \my_empty_inst_rep__1_n_0\,
      I2 => mem_out(36),
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]\
    );
\app_rd_data[307]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(32),
      I1 => \my_empty_inst_rep__1_n_0\,
      I2 => mem_out(44),
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]\
    );
\app_rd_data[308]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(40),
      I1 => my_empty(4),
      I2 => mem_out(52),
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]\
    );
\app_rd_data[309]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(48),
      I1 => my_empty(4),
      I2 => mem_out(60),
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]\
    );
\app_rd_data[310]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(56),
      I1 => my_empty(4),
      I2 => mem_out(68),
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]\
    );
\app_rd_data[311]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(64),
      I1 => my_empty(4),
      I2 => mem_out(76),
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]\
    );
\app_rd_data[368]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(9),
      I1 => \my_empty_inst_rep__1_n_0\,
      I2 => mem_out(21),
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]\
    );
\app_rd_data[369]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(17),
      I1 => \my_empty_inst_rep__1_n_0\,
      I2 => mem_out(29),
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]\
    );
\app_rd_data[370]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(25),
      I1 => \my_empty_inst_rep__1_n_0\,
      I2 => mem_out(37),
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]\
    );
\app_rd_data[371]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(33),
      I1 => \my_empty_inst_rep__1_n_0\,
      I2 => mem_out(45),
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]\
    );
\app_rd_data[372]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(41),
      I1 => my_empty(4),
      I2 => mem_out(53),
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]\
    );
\app_rd_data[373]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(49),
      I1 => my_empty(4),
      I2 => mem_out(61),
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]\
    );
\app_rd_data[374]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(57),
      I1 => my_empty(4),
      I2 => mem_out(69),
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]\
    );
\app_rd_data[375]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(65),
      I1 => my_empty(4),
      I2 => mem_out(77),
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]\
    );
\app_rd_data[432]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(10),
      I1 => \my_empty_inst_rep__1_n_0\,
      I2 => mem_out(22),
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]\
    );
\app_rd_data[433]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(18),
      I1 => \my_empty_inst_rep__1_n_0\,
      I2 => mem_out(30),
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]\
    );
\app_rd_data[434]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(26),
      I1 => \my_empty_inst_rep__1_n_0\,
      I2 => mem_out(38),
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]\
    );
\app_rd_data[435]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(34),
      I1 => \my_empty_inst_rep__1_n_0\,
      I2 => mem_out(46),
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]\
    );
\app_rd_data[436]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(42),
      I1 => my_empty(4),
      I2 => mem_out(54),
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]\
    );
\app_rd_data[437]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(50),
      I1 => my_empty(4),
      I2 => mem_out(62),
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]\
    );
\app_rd_data[438]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(58),
      I1 => my_empty(4),
      I2 => mem_out(70),
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]\
    );
\app_rd_data[439]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(66),
      I1 => my_empty(4),
      I2 => mem_out(78),
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]\
    );
\app_rd_data[48]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(4),
      I1 => \my_empty_inst_rep__1_n_0\,
      I2 => mem_out(16),
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]\
    );
\app_rd_data[496]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(11),
      I1 => \my_empty_inst_rep__1_n_0\,
      I2 => mem_out(23),
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]\
    );
\app_rd_data[497]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(19),
      I1 => \my_empty_inst_rep__1_n_0\,
      I2 => mem_out(31),
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]\
    );
\app_rd_data[498]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(27),
      I1 => \my_empty_inst_rep__1_n_0\,
      I2 => mem_out(39),
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]\
    );
\app_rd_data[499]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(35),
      I1 => \my_empty_inst_rep__1_n_0\,
      I2 => mem_out(47),
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]\
    );
\app_rd_data[49]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(12),
      I1 => \my_empty_inst_rep__1_n_0\,
      I2 => mem_out(24),
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]\
    );
\app_rd_data[500]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(43),
      I1 => my_empty(4),
      I2 => mem_out(55),
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]\
    );
\app_rd_data[501]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(51),
      I1 => my_empty(4),
      I2 => mem_out(63),
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]\
    );
\app_rd_data[502]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(59),
      I1 => my_empty(4),
      I2 => mem_out(71),
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]\
    );
\app_rd_data[503]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(67),
      I1 => my_empty(4),
      I2 => mem_out(79),
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]\
    );
\app_rd_data[50]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(20),
      I1 => \my_empty_inst_rep__1_n_0\,
      I2 => mem_out(32),
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]\
    );
\app_rd_data[51]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(28),
      I1 => \my_empty_inst_rep__1_n_0\,
      I2 => mem_out(40),
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]\
    );
\app_rd_data[52]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(36),
      I1 => my_empty(4),
      I2 => mem_out(48),
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]\
    );
\app_rd_data[53]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(44),
      I1 => my_empty(4),
      I2 => mem_out(56),
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]\
    );
\app_rd_data[54]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(52),
      I1 => my_empty(4),
      I2 => mem_out(64),
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]\
    );
\app_rd_data[55]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(60),
      I1 => my_empty(4),
      I2 => mem_out(72),
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]\
    );
mem_reg_0_3_12_17: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 2) => B"000",
      ADDRA(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRB(4 downto 2) => B"000",
      ADDRB(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRC(4 downto 2) => B"000",
      ADDRC(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRD(4 downto 2) => B"000",
      ADDRD(1 downto 0) => wr_ptr(1 downto 0),
      DIA(1 downto 0) => Q(1 downto 0),
      DIB(1 downto 0) => Q(3 downto 2),
      DIC(1 downto 0) => Q(5 downto 4),
      DID(1 downto 0) => B"00",
      DOA(1) => mem_reg_0_3_12_17_n_0,
      DOA(0) => mem_reg_0_3_12_17_n_1,
      DOB(1) => mem_reg_0_3_12_17_n_2,
      DOB(0) => mem_reg_0_3_12_17_n_3,
      DOC(1 downto 0) => mem_out(17 downto 16),
      DOD(1 downto 0) => NLW_mem_reg_0_3_12_17_DOD_UNCONNECTED(1 downto 0),
      WCLK => \rd_ptr_timing_reg[1]_0\,
      WE => wr_en
    );
\mem_reg_0_3_12_17_i_1__3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0151"
    )
        port map (
      I0 => \wr_ptr_reg[0]_0\,
      I1 => my_full(0),
      I2 => \my_full_reg[1]_0\,
      I3 => my_empty(2),
      O => wr_en
    );
mem_reg_0_3_18_23: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 2) => B"000",
      ADDRA(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRB(4 downto 2) => B"000",
      ADDRB(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRC(4 downto 2) => B"000",
      ADDRC(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRD(4 downto 2) => B"000",
      ADDRD(1 downto 0) => wr_ptr(1 downto 0),
      DIA(1 downto 0) => Q(7 downto 6),
      DIB(1 downto 0) => Q(9 downto 8),
      DIC(1 downto 0) => Q(11 downto 10),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => mem_out(19 downto 18),
      DOB(1 downto 0) => mem_out(21 downto 20),
      DOC(1 downto 0) => mem_out(23 downto 22),
      DOD(1 downto 0) => NLW_mem_reg_0_3_18_23_DOD_UNCONNECTED(1 downto 0),
      WCLK => \rd_ptr_timing_reg[1]_0\,
      WE => wr_en
    );
mem_reg_0_3_24_29: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 2) => B"000",
      ADDRA(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRB(4 downto 2) => B"000",
      ADDRB(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRC(4 downto 2) => B"000",
      ADDRC(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRD(4 downto 2) => B"000",
      ADDRD(1 downto 0) => wr_ptr(1 downto 0),
      DIA(1 downto 0) => Q(13 downto 12),
      DIB(1 downto 0) => Q(15 downto 14),
      DIC(1 downto 0) => Q(17 downto 16),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => mem_out(25 downto 24),
      DOB(1 downto 0) => mem_out(27 downto 26),
      DOC(1 downto 0) => mem_out(29 downto 28),
      DOD(1 downto 0) => NLW_mem_reg_0_3_24_29_DOD_UNCONNECTED(1 downto 0),
      WCLK => \rd_ptr_timing_reg[1]_0\,
      WE => wr_en
    );
mem_reg_0_3_30_35: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 2) => B"000",
      ADDRA(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRB(4 downto 2) => B"000",
      ADDRB(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRC(4 downto 2) => B"000",
      ADDRC(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRD(4 downto 2) => B"000",
      ADDRD(1 downto 0) => wr_ptr(1 downto 0),
      DIA(1 downto 0) => Q(19 downto 18),
      DIB(1 downto 0) => Q(21 downto 20),
      DIC(1 downto 0) => Q(23 downto 22),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => mem_out(31 downto 30),
      DOB(1 downto 0) => mem_out(33 downto 32),
      DOC(1 downto 0) => mem_out(35 downto 34),
      DOD(1 downto 0) => NLW_mem_reg_0_3_30_35_DOD_UNCONNECTED(1 downto 0),
      WCLK => \rd_ptr_timing_reg[1]_0\,
      WE => wr_en
    );
mem_reg_0_3_36_41: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 2) => B"000",
      ADDRA(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRB(4 downto 2) => B"000",
      ADDRB(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRC(4 downto 2) => B"000",
      ADDRC(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRD(4 downto 2) => B"000",
      ADDRD(1 downto 0) => wr_ptr(1 downto 0),
      DIA(1 downto 0) => Q(25 downto 24),
      DIB(1 downto 0) => Q(27 downto 26),
      DIC(1 downto 0) => Q(29 downto 28),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => mem_out(37 downto 36),
      DOB(1 downto 0) => mem_out(39 downto 38),
      DOC(1 downto 0) => mem_out(41 downto 40),
      DOD(1 downto 0) => NLW_mem_reg_0_3_36_41_DOD_UNCONNECTED(1 downto 0),
      WCLK => \rd_ptr_timing_reg[1]_0\,
      WE => wr_en
    );
mem_reg_0_3_42_47: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 2) => B"000",
      ADDRA(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRB(4 downto 2) => B"000",
      ADDRB(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRC(4 downto 2) => B"000",
      ADDRC(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRD(4 downto 2) => B"000",
      ADDRD(1 downto 0) => wr_ptr(1 downto 0),
      DIA(1 downto 0) => Q(31 downto 30),
      DIB(1 downto 0) => Q(33 downto 32),
      DIC(1 downto 0) => Q(35 downto 34),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => mem_out(43 downto 42),
      DOB(1 downto 0) => mem_out(45 downto 44),
      DOC(1 downto 0) => mem_out(47 downto 46),
      DOD(1 downto 0) => NLW_mem_reg_0_3_42_47_DOD_UNCONNECTED(1 downto 0),
      WCLK => \rd_ptr_timing_reg[1]_0\,
      WE => wr_en
    );
mem_reg_0_3_48_53: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 2) => B"000",
      ADDRA(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRB(4 downto 2) => B"000",
      ADDRB(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRC(4 downto 2) => B"000",
      ADDRC(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRD(4 downto 2) => B"000",
      ADDRD(1 downto 0) => wr_ptr(1 downto 0),
      DIA(1 downto 0) => Q(37 downto 36),
      DIB(1 downto 0) => Q(39 downto 38),
      DIC(1 downto 0) => Q(41 downto 40),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => mem_out(49 downto 48),
      DOB(1 downto 0) => mem_out(51 downto 50),
      DOC(1 downto 0) => mem_out(53 downto 52),
      DOD(1 downto 0) => NLW_mem_reg_0_3_48_53_DOD_UNCONNECTED(1 downto 0),
      WCLK => \rd_ptr_timing_reg[1]_0\,
      WE => wr_en
    );
mem_reg_0_3_54_59: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 2) => B"000",
      ADDRA(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRB(4 downto 2) => B"000",
      ADDRB(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRC(4 downto 2) => B"000",
      ADDRC(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRD(4 downto 2) => B"000",
      ADDRD(1 downto 0) => wr_ptr(1 downto 0),
      DIA(1 downto 0) => Q(43 downto 42),
      DIB(1 downto 0) => Q(45 downto 44),
      DIC(1 downto 0) => Q(47 downto 46),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => mem_out(55 downto 54),
      DOB(1 downto 0) => mem_out(57 downto 56),
      DOC(1 downto 0) => mem_out(59 downto 58),
      DOD(1 downto 0) => NLW_mem_reg_0_3_54_59_DOD_UNCONNECTED(1 downto 0),
      WCLK => \rd_ptr_timing_reg[1]_0\,
      WE => wr_en
    );
mem_reg_0_3_60_65: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 2) => B"000",
      ADDRA(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRB(4 downto 2) => B"000",
      ADDRB(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRC(4 downto 2) => B"000",
      ADDRC(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRD(4 downto 2) => B"000",
      ADDRD(1 downto 0) => wr_ptr(1 downto 0),
      DIA(1 downto 0) => Q(49 downto 48),
      DIB(1 downto 0) => Q(51 downto 50),
      DIC(1 downto 0) => Q(53 downto 52),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => mem_out(61 downto 60),
      DOB(1 downto 0) => mem_out(63 downto 62),
      DOC(1 downto 0) => mem_out(65 downto 64),
      DOD(1 downto 0) => NLW_mem_reg_0_3_60_65_DOD_UNCONNECTED(1 downto 0),
      WCLK => \rd_ptr_timing_reg[1]_0\,
      WE => wr_en
    );
mem_reg_0_3_66_71: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 2) => B"000",
      ADDRA(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRB(4 downto 2) => B"000",
      ADDRB(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRC(4 downto 2) => B"000",
      ADDRC(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRD(4 downto 2) => B"000",
      ADDRD(1 downto 0) => wr_ptr(1 downto 0),
      DIA(1 downto 0) => Q(55 downto 54),
      DIB(1 downto 0) => Q(57 downto 56),
      DIC(1 downto 0) => Q(59 downto 58),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => mem_out(67 downto 66),
      DOB(1 downto 0) => mem_out(69 downto 68),
      DOC(1 downto 0) => mem_out(71 downto 70),
      DOD(1 downto 0) => NLW_mem_reg_0_3_66_71_DOD_UNCONNECTED(1 downto 0),
      WCLK => \rd_ptr_timing_reg[1]_0\,
      WE => wr_en
    );
mem_reg_0_3_72_77: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 2) => B"000",
      ADDRA(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRB(4 downto 2) => B"000",
      ADDRB(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRC(4 downto 2) => B"000",
      ADDRC(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRD(4 downto 2) => B"000",
      ADDRD(1 downto 0) => wr_ptr(1 downto 0),
      DIA(1 downto 0) => Q(61 downto 60),
      DIB(1 downto 0) => Q(63 downto 62),
      DIC(1 downto 0) => Q(65 downto 64),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => mem_out(73 downto 72),
      DOB(1 downto 0) => mem_out(75 downto 74),
      DOC(1 downto 0) => mem_out(77 downto 76),
      DOD(1 downto 0) => NLW_mem_reg_0_3_72_77_DOD_UNCONNECTED(1 downto 0),
      WCLK => \rd_ptr_timing_reg[1]_0\,
      WE => wr_en
    );
mem_reg_0_3_78_79: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 2) => B"000",
      ADDRA(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRB(4 downto 2) => B"000",
      ADDRB(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRC(4 downto 2) => B"000",
      ADDRC(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRD(4 downto 2) => B"000",
      ADDRD(1 downto 0) => wr_ptr(1 downto 0),
      DIA(1 downto 0) => Q(67 downto 66),
      DIB(1 downto 0) => B"00",
      DIC(1 downto 0) => B"00",
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => mem_out(79 downto 78),
      DOB(1 downto 0) => NLW_mem_reg_0_3_78_79_DOB_UNCONNECTED(1 downto 0),
      DOC(1 downto 0) => NLW_mem_reg_0_3_78_79_DOC_UNCONNECTED(1 downto 0),
      DOD(1 downto 0) => NLW_mem_reg_0_3_78_79_DOD_UNCONNECTED(1 downto 0),
      WCLK => \rd_ptr_timing_reg[1]_0\,
      WE => wr_en
    );
\my_empty[4]_i_1__5\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0018"
    )
        port map (
      I0 => \my_full_reg[1]_0\,
      I1 => \wr_ptr_reg[0]_0\,
      I2 => my_empty(1),
      I3 => my_full(1),
      O => \my_empty[4]_i_1__5_n_0\
    );
\my_empty[4]_i_2__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00411400"
    )
        port map (
      I0 => my_empty(1),
      I1 => wr_ptr(1),
      I2 => rd_ptr(1),
      I3 => rd_ptr(0),
      I4 => wr_ptr(0),
      O => \my_empty[4]_i_2__1_n_0\
    );
\my_empty_inst__10\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \^my_empty_reg[4]_0\,
      O => my_empty(1)
    );
\my_empty_inst__7\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \my_empty_reg[4]_rep_n_0\,
      O => my_empty(4)
    );
\my_empty_inst__8\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \^my_empty_reg[4]_0\,
      O => \^my_empty_reg[4]_1\(0)
    );
\my_empty_inst__9\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \^my_empty_reg[4]_0\,
      O => my_empty(2)
    );
\my_empty_inst_rep__1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \my_empty_reg[4]_rep__0_n_0\,
      O => \my_empty_inst_rep__1_n_0\
    );
\my_empty_reg[4]\: unisim.vcomponents.FDSE
     port map (
      C => \rd_ptr_timing_reg[1]_0\,
      CE => \my_empty[4]_i_1__5_n_0\,
      D => \my_empty[4]_i_2__1_n_0\,
      Q => \^my_empty_reg[4]_0\,
      S => ififo_rst
    );
\my_empty_reg[4]_rep\: unisim.vcomponents.FDSE
     port map (
      C => \rd_ptr_timing_reg[1]_0\,
      CE => \my_empty[4]_i_1__5_n_0\,
      D => \my_empty[4]_i_2__1_n_0\,
      Q => \my_empty_reg[4]_rep_n_0\,
      S => ififo_rst
    );
\my_empty_reg[4]_rep__0\: unisim.vcomponents.FDSE
     port map (
      C => \rd_ptr_timing_reg[1]_0\,
      CE => \my_empty[4]_i_1__5_n_0\,
      D => \my_empty[4]_i_2__1_n_0\,
      Q => \my_empty_reg[4]_rep__0_n_0\,
      S => ififo_rst
    );
\my_full[0]_i_1__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAEAABAAAA2AA8"
    )
        port map (
      I0 => my_full(0),
      I1 => \my_full_reg[1]_0\,
      I2 => \wr_ptr_reg[0]_0\,
      I3 => my_full(1),
      I4 => my_empty(1),
      I5 => \my_full[1]_i_2__1_n_0\,
      O => \my_full[0]_i_1__1_n_0\
    );
\my_full[1]_i_1__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"F0F1F070"
    )
        port map (
      I0 => \my_full_reg[1]_0\,
      I1 => \wr_ptr_reg[0]_0\,
      I2 => my_full(1),
      I3 => my_empty(1),
      I4 => \my_full[1]_i_2__1_n_0\,
      O => \my_full[1]_i_1__1_n_0\
    );
\my_full[1]_i_2__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00411400"
    )
        port map (
      I0 => my_full(1),
      I1 => rd_ptr(1),
      I2 => wr_ptr(1),
      I3 => wr_ptr(0),
      I4 => rd_ptr(0),
      O => \my_full[1]_i_2__1_n_0\
    );
\my_full_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \rd_ptr_timing_reg[1]_0\,
      CE => '1',
      D => \my_full[0]_i_1__1_n_0\,
      Q => my_full(0),
      R => ififo_rst
    );
\my_full_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \rd_ptr_timing_reg[1]_0\,
      CE => '1',
      D => \my_full[1]_i_1__1_n_0\,
      Q => my_full(1),
      R => ififo_rst
    );
\rd_ptr[0]_i_1__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"D2"
    )
        port map (
      I0 => \my_full_reg[1]_0\,
      I1 => my_empty(1),
      I2 => rd_ptr(0),
      O => \rd_ptr[0]_i_1__1_n_0\
    );
\rd_ptr[1]_i_1__1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F708"
    )
        port map (
      I0 => rd_ptr(0),
      I1 => \my_full_reg[1]_0\,
      I2 => my_empty(1),
      I3 => rd_ptr(1),
      O => \rd_ptr[1]_i_1__1_n_0\
    );
\rd_ptr_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \rd_ptr_timing_reg[1]_0\,
      CE => '1',
      D => \rd_ptr[0]_i_1__1_n_0\,
      Q => rd_ptr(0),
      R => ififo_rst
    );
\rd_ptr_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \rd_ptr_timing_reg[1]_0\,
      CE => '1',
      D => \rd_ptr[1]_i_1__1_n_0\,
      Q => rd_ptr(1),
      R => ififo_rst
    );
\rd_ptr_timing[0]_i_1__4\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F704"
    )
        port map (
      I0 => rd_ptr(0),
      I1 => \my_full_reg[1]_0\,
      I2 => my_empty(1),
      I3 => rd_ptr_timing(0),
      O => \rd_ptr_timing[0]_i_1__4_n_0\
    );
\rd_ptr_timing[1]_i_1__4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FF6F0060"
    )
        port map (
      I0 => rd_ptr(0),
      I1 => rd_ptr(1),
      I2 => \my_full_reg[1]_0\,
      I3 => my_empty(1),
      I4 => rd_ptr_timing(1),
      O => \rd_ptr_timing[1]_i_1__4_n_0\
    );
\rd_ptr_timing_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \rd_ptr_timing_reg[1]_0\,
      CE => '1',
      D => \rd_ptr_timing[0]_i_1__4_n_0\,
      Q => rd_ptr_timing(0),
      R => ififo_rst
    );
\rd_ptr_timing_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \rd_ptr_timing_reg[1]_0\,
      CE => '1',
      D => \rd_ptr_timing[1]_i_1__4_n_0\,
      Q => rd_ptr_timing(1),
      R => ififo_rst
    );
\wr_ptr[0]_i_1__4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FECE0131"
    )
        port map (
      I0 => my_full(1),
      I1 => \wr_ptr_reg[0]_0\,
      I2 => \my_full_reg[1]_0\,
      I3 => my_empty(1),
      I4 => wr_ptr(0),
      O => \wr_ptr[0]_i_1__4_n_0\
    );
\wr_ptr[1]_i_1__4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFDF5FD00020A02"
    )
        port map (
      I0 => wr_ptr(0),
      I1 => my_full(1),
      I2 => \wr_ptr_reg[0]_0\,
      I3 => \my_full_reg[1]_0\,
      I4 => my_empty(1),
      I5 => wr_ptr(1),
      O => \wr_ptr[1]_i_1__4_n_0\
    );
\wr_ptr[1]_i_2__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000000001"
    )
        port map (
      I0 => \wr_ptr[1]_i_3__0_n_0\,
      I1 => \my_full_reg[1]_1\,
      I2 => \my_full_reg[1]_2\,
      I3 => \my_full_reg[1]_3\,
      I4 => \my_full_reg[1]_4\,
      I5 => \my_full_reg[1]_5\,
      O => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0\
    );
\wr_ptr[1]_i_3__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \wr_ptr_reg[0]_0\,
      I1 => \^my_empty_reg[4]_1\(0),
      O => \wr_ptr[1]_i_3__0_n_0\
    );
\wr_ptr[1]_i_3__3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F888"
    )
        port map (
      I0 => \^my_empty_reg[4]_1\(0),
      I1 => \wr_ptr_reg[0]_0\,
      I2 => \wr_ptr[1]_i_2__6\(0),
      I3 => if_empty_r(0),
      O => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]\
    );
\wr_ptr_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \rd_ptr_timing_reg[1]_0\,
      CE => '1',
      D => \wr_ptr[0]_i_1__4_n_0\,
      Q => wr_ptr(0),
      R => ififo_rst
    );
\wr_ptr_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \rd_ptr_timing_reg[1]_0\,
      CE => '1',
      D => \wr_ptr[1]_i_1__4_n_0\,
      Q => wr_ptr(1),
      R => ififo_rst
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mig_mig_7series_v4_2_ddr_if_post_fifo_36 is
  port (
    \my_empty_reg[4]_0\ : out STD_LOGIC;
    \my_empty_reg[4]_1\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_0\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_1\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_2\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_3\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_4\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_5\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_6\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_7\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_8\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_9\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_10\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_11\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_12\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_13\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_14\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_15\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_16\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_17\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_18\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_19\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_20\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_21\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_22\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_23\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_24\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_25\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_26\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_27\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_28\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_29\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_30\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_31\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_32\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_33\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_34\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_35\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_36\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_37\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_38\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_39\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_40\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_41\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_42\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_43\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_44\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_45\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_46\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_47\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_48\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_49\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_50\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_51\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_52\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_53\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_54\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_55\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_56\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_57\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_58\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_59\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_60\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_61\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_62\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0\ : out STD_LOGIC;
    ififo_rst : in STD_LOGIC;
    \rd_ptr_reg[1]_0\ : in STD_LOGIC;
    \wr_ptr_reg[0]_0\ : in STD_LOGIC;
    \my_full_reg[1]_0\ : in STD_LOGIC;
    my_empty : in STD_LOGIC_VECTOR ( 0 to 0 );
    \wr_ptr[1]_i_2__0\ : in STD_LOGIC;
    \gen_mux_rd[0].mux_rd_rise0_r_reg[0]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \gen_mux_rd[0].mux_rd_rise0_r_reg[0]_0\ : in STD_LOGIC;
    \gen_mux_rd[0].mux_rd_rise0_r_reg[0]_1\ : in STD_LOGIC;
    \gen_mux_rd[0].mux_rd_rise0_r_reg[0]_2\ : in STD_LOGIC;
    \gen_mux_rd[1].mux_rd_rise0_r_reg[1]\ : in STD_LOGIC;
    \gen_mux_rd[1].mux_rd_rise0_r_reg[1]_0\ : in STD_LOGIC;
    \gen_mux_rd[1].mux_rd_rise0_r_reg[1]_1\ : in STD_LOGIC;
    \gen_mux_rd[2].mux_rd_rise0_r_reg[2]\ : in STD_LOGIC;
    \gen_mux_rd[2].mux_rd_rise0_r_reg[2]_0\ : in STD_LOGIC;
    \gen_mux_rd[2].mux_rd_rise0_r_reg[2]_1\ : in STD_LOGIC;
    \gen_mux_rd[3].mux_rd_rise0_r_reg[3]\ : in STD_LOGIC;
    \gen_mux_rd[3].mux_rd_rise0_r_reg[3]_0\ : in STD_LOGIC;
    \gen_mux_rd[3].mux_rd_rise0_r_reg[3]_1\ : in STD_LOGIC;
    \gen_mux_rd[4].mux_rd_rise0_r_reg[4]\ : in STD_LOGIC;
    \gen_mux_rd[4].mux_rd_rise0_r_reg[4]_0\ : in STD_LOGIC;
    \gen_mux_rd[4].mux_rd_rise0_r_reg[4]_1\ : in STD_LOGIC;
    \gen_mux_rd[5].mux_rd_rise0_r_reg[5]\ : in STD_LOGIC;
    \gen_mux_rd[5].mux_rd_rise0_r_reg[5]_0\ : in STD_LOGIC;
    \gen_mux_rd[5].mux_rd_rise0_r_reg[5]_1\ : in STD_LOGIC;
    \gen_mux_rd[6].mux_rd_rise0_r_reg[6]\ : in STD_LOGIC;
    \gen_mux_rd[6].mux_rd_rise0_r_reg[6]_0\ : in STD_LOGIC;
    \gen_mux_rd[6].mux_rd_rise0_r_reg[6]_1\ : in STD_LOGIC;
    \gen_mux_rd[7].mux_rd_rise0_r_reg[7]\ : in STD_LOGIC;
    \gen_mux_rd[7].mux_rd_rise0_r_reg[7]_0\ : in STD_LOGIC;
    \gen_mux_rd[7].mux_rd_rise0_r_reg[7]_1\ : in STD_LOGIC;
    \gen_mux_rd[0].mux_rd_fall0_r_reg[0]\ : in STD_LOGIC;
    \gen_mux_rd[0].mux_rd_fall0_r_reg[0]_0\ : in STD_LOGIC;
    \gen_mux_rd[0].mux_rd_fall0_r_reg[0]_1\ : in STD_LOGIC;
    \gen_mux_rd[1].mux_rd_fall0_r_reg[1]\ : in STD_LOGIC;
    \gen_mux_rd[1].mux_rd_fall0_r_reg[1]_0\ : in STD_LOGIC;
    \gen_mux_rd[1].mux_rd_fall0_r_reg[1]_1\ : in STD_LOGIC;
    \gen_mux_rd[2].mux_rd_fall0_r_reg[2]\ : in STD_LOGIC;
    \gen_mux_rd[2].mux_rd_fall0_r_reg[2]_0\ : in STD_LOGIC;
    \gen_mux_rd[2].mux_rd_fall0_r_reg[2]_1\ : in STD_LOGIC;
    \gen_mux_rd[3].mux_rd_fall0_r_reg[3]\ : in STD_LOGIC;
    \gen_mux_rd[3].mux_rd_fall0_r_reg[3]_0\ : in STD_LOGIC;
    \gen_mux_rd[3].mux_rd_fall0_r_reg[3]_1\ : in STD_LOGIC;
    \gen_mux_rd[4].mux_rd_fall0_r_reg[4]\ : in STD_LOGIC;
    \gen_mux_rd[4].mux_rd_fall0_r_reg[4]_0\ : in STD_LOGIC;
    \gen_mux_rd[4].mux_rd_fall0_r_reg[4]_1\ : in STD_LOGIC;
    \gen_mux_rd[5].mux_rd_fall0_r_reg[5]\ : in STD_LOGIC;
    \gen_mux_rd[5].mux_rd_fall0_r_reg[5]_0\ : in STD_LOGIC;
    \gen_mux_rd[5].mux_rd_fall0_r_reg[5]_1\ : in STD_LOGIC;
    \gen_mux_rd[6].mux_rd_fall0_r_reg[6]\ : in STD_LOGIC;
    \gen_mux_rd[6].mux_rd_fall0_r_reg[6]_0\ : in STD_LOGIC;
    \gen_mux_rd[6].mux_rd_fall0_r_reg[6]_1\ : in STD_LOGIC;
    \gen_mux_rd[7].mux_rd_fall0_r_reg[7]\ : in STD_LOGIC;
    \gen_mux_rd[7].mux_rd_fall0_r_reg[7]_0\ : in STD_LOGIC;
    \gen_mux_rd[7].mux_rd_fall0_r_reg[7]_1\ : in STD_LOGIC;
    \gen_mux_rd[0].mux_rd_rise1_r_reg[0]\ : in STD_LOGIC;
    \gen_mux_rd[0].mux_rd_rise1_r_reg[0]_0\ : in STD_LOGIC;
    \gen_mux_rd[0].mux_rd_rise1_r_reg[0]_1\ : in STD_LOGIC;
    \gen_mux_rd[1].mux_rd_rise1_r_reg[1]\ : in STD_LOGIC;
    \gen_mux_rd[1].mux_rd_rise1_r_reg[1]_0\ : in STD_LOGIC;
    \gen_mux_rd[1].mux_rd_rise1_r_reg[1]_1\ : in STD_LOGIC;
    \gen_mux_rd[2].mux_rd_rise1_r_reg[2]\ : in STD_LOGIC;
    \gen_mux_rd[2].mux_rd_rise1_r_reg[2]_0\ : in STD_LOGIC;
    \gen_mux_rd[2].mux_rd_rise1_r_reg[2]_1\ : in STD_LOGIC;
    \gen_mux_rd[3].mux_rd_rise1_r_reg[3]\ : in STD_LOGIC;
    \gen_mux_rd[3].mux_rd_rise1_r_reg[3]_0\ : in STD_LOGIC;
    \gen_mux_rd[3].mux_rd_rise1_r_reg[3]_1\ : in STD_LOGIC;
    \gen_mux_rd[4].mux_rd_rise1_r_reg[4]\ : in STD_LOGIC;
    \gen_mux_rd[4].mux_rd_rise1_r_reg[4]_0\ : in STD_LOGIC;
    \gen_mux_rd[4].mux_rd_rise1_r_reg[4]_1\ : in STD_LOGIC;
    \gen_mux_rd[5].mux_rd_rise1_r_reg[5]\ : in STD_LOGIC;
    \gen_mux_rd[5].mux_rd_rise1_r_reg[5]_0\ : in STD_LOGIC;
    \gen_mux_rd[5].mux_rd_rise1_r_reg[5]_1\ : in STD_LOGIC;
    \gen_mux_rd[6].mux_rd_rise1_r_reg[6]\ : in STD_LOGIC;
    \gen_mux_rd[6].mux_rd_rise1_r_reg[6]_0\ : in STD_LOGIC;
    \gen_mux_rd[6].mux_rd_rise1_r_reg[6]_1\ : in STD_LOGIC;
    \gen_mux_rd[7].mux_rd_rise1_r_reg[7]\ : in STD_LOGIC;
    \gen_mux_rd[7].mux_rd_rise1_r_reg[7]_0\ : in STD_LOGIC;
    \gen_mux_rd[7].mux_rd_rise1_r_reg[7]_1\ : in STD_LOGIC;
    \gen_mux_rd[0].mux_rd_fall1_r_reg[0]\ : in STD_LOGIC;
    \gen_mux_rd[0].mux_rd_fall1_r_reg[0]_0\ : in STD_LOGIC;
    \gen_mux_rd[0].mux_rd_fall1_r_reg[0]_1\ : in STD_LOGIC;
    \gen_mux_rd[1].mux_rd_fall1_r_reg[1]\ : in STD_LOGIC;
    \gen_mux_rd[1].mux_rd_fall1_r_reg[1]_0\ : in STD_LOGIC;
    \gen_mux_rd[1].mux_rd_fall1_r_reg[1]_1\ : in STD_LOGIC;
    \gen_mux_rd[2].mux_rd_fall1_r_reg[2]\ : in STD_LOGIC;
    \gen_mux_rd[2].mux_rd_fall1_r_reg[2]_0\ : in STD_LOGIC;
    \gen_mux_rd[2].mux_rd_fall1_r_reg[2]_1\ : in STD_LOGIC;
    \gen_mux_rd[3].mux_rd_fall1_r_reg[3]\ : in STD_LOGIC;
    \gen_mux_rd[3].mux_rd_fall1_r_reg[3]_0\ : in STD_LOGIC;
    \gen_mux_rd[3].mux_rd_fall1_r_reg[3]_1\ : in STD_LOGIC;
    \gen_mux_rd[4].mux_rd_fall1_r_reg[4]\ : in STD_LOGIC;
    \gen_mux_rd[4].mux_rd_fall1_r_reg[4]_0\ : in STD_LOGIC;
    \gen_mux_rd[4].mux_rd_fall1_r_reg[4]_1\ : in STD_LOGIC;
    \gen_mux_rd[5].mux_rd_fall1_r_reg[5]\ : in STD_LOGIC;
    \gen_mux_rd[5].mux_rd_fall1_r_reg[5]_0\ : in STD_LOGIC;
    \gen_mux_rd[5].mux_rd_fall1_r_reg[5]_1\ : in STD_LOGIC;
    \gen_mux_rd[6].mux_rd_fall1_r_reg[6]\ : in STD_LOGIC;
    \gen_mux_rd[6].mux_rd_fall1_r_reg[6]_0\ : in STD_LOGIC;
    \gen_mux_rd[6].mux_rd_fall1_r_reg[6]_1\ : in STD_LOGIC;
    \gen_mux_rd[7].mux_rd_fall1_r_reg[7]\ : in STD_LOGIC;
    \gen_mux_rd[7].mux_rd_fall1_r_reg[7]_0\ : in STD_LOGIC;
    \gen_mux_rd[7].mux_rd_fall1_r_reg[7]_1\ : in STD_LOGIC;
    \gen_mux_rd[0].mux_rd_rise2_r_reg[0]\ : in STD_LOGIC;
    \gen_mux_rd[0].mux_rd_rise2_r_reg[0]_0\ : in STD_LOGIC;
    \gen_mux_rd[0].mux_rd_rise2_r_reg[0]_1\ : in STD_LOGIC;
    \gen_mux_rd[1].mux_rd_rise2_r_reg[1]\ : in STD_LOGIC;
    \gen_mux_rd[1].mux_rd_rise2_r_reg[1]_0\ : in STD_LOGIC;
    \gen_mux_rd[1].mux_rd_rise2_r_reg[1]_1\ : in STD_LOGIC;
    \gen_mux_rd[2].mux_rd_rise2_r_reg[2]\ : in STD_LOGIC;
    \gen_mux_rd[2].mux_rd_rise2_r_reg[2]_0\ : in STD_LOGIC;
    \gen_mux_rd[2].mux_rd_rise2_r_reg[2]_1\ : in STD_LOGIC;
    \gen_mux_rd[3].mux_rd_rise2_r_reg[3]\ : in STD_LOGIC;
    \gen_mux_rd[3].mux_rd_rise2_r_reg[3]_0\ : in STD_LOGIC;
    \gen_mux_rd[3].mux_rd_rise2_r_reg[3]_1\ : in STD_LOGIC;
    \gen_mux_rd[4].mux_rd_rise2_r_reg[4]\ : in STD_LOGIC;
    \gen_mux_rd[4].mux_rd_rise2_r_reg[4]_0\ : in STD_LOGIC;
    \gen_mux_rd[4].mux_rd_rise2_r_reg[4]_1\ : in STD_LOGIC;
    \gen_mux_rd[5].mux_rd_rise2_r_reg[5]\ : in STD_LOGIC;
    \gen_mux_rd[5].mux_rd_rise2_r_reg[5]_0\ : in STD_LOGIC;
    \gen_mux_rd[5].mux_rd_rise2_r_reg[5]_1\ : in STD_LOGIC;
    \gen_mux_rd[6].mux_rd_rise2_r_reg[6]\ : in STD_LOGIC;
    \gen_mux_rd[6].mux_rd_rise2_r_reg[6]_0\ : in STD_LOGIC;
    \gen_mux_rd[6].mux_rd_rise2_r_reg[6]_1\ : in STD_LOGIC;
    \gen_mux_rd[7].mux_rd_rise2_r_reg[7]\ : in STD_LOGIC;
    \gen_mux_rd[7].mux_rd_rise2_r_reg[7]_0\ : in STD_LOGIC;
    \gen_mux_rd[7].mux_rd_rise2_r_reg[7]_1\ : in STD_LOGIC;
    \gen_mux_rd[0].mux_rd_fall2_r_reg[0]\ : in STD_LOGIC;
    \gen_mux_rd[0].mux_rd_fall2_r_reg[0]_0\ : in STD_LOGIC;
    \gen_mux_rd[0].mux_rd_fall2_r_reg[0]_1\ : in STD_LOGIC;
    \gen_mux_rd[1].mux_rd_fall2_r_reg[1]\ : in STD_LOGIC;
    \gen_mux_rd[1].mux_rd_fall2_r_reg[1]_0\ : in STD_LOGIC;
    \gen_mux_rd[1].mux_rd_fall2_r_reg[1]_1\ : in STD_LOGIC;
    \gen_mux_rd[2].mux_rd_fall2_r_reg[2]\ : in STD_LOGIC;
    \gen_mux_rd[2].mux_rd_fall2_r_reg[2]_0\ : in STD_LOGIC;
    \gen_mux_rd[2].mux_rd_fall2_r_reg[2]_1\ : in STD_LOGIC;
    \gen_mux_rd[3].mux_rd_fall2_r_reg[3]\ : in STD_LOGIC;
    \gen_mux_rd[3].mux_rd_fall2_r_reg[3]_0\ : in STD_LOGIC;
    \gen_mux_rd[3].mux_rd_fall2_r_reg[3]_1\ : in STD_LOGIC;
    \gen_mux_rd[4].mux_rd_fall2_r_reg[4]\ : in STD_LOGIC;
    \gen_mux_rd[4].mux_rd_fall2_r_reg[4]_0\ : in STD_LOGIC;
    \gen_mux_rd[4].mux_rd_fall2_r_reg[4]_1\ : in STD_LOGIC;
    \gen_mux_rd[5].mux_rd_fall2_r_reg[5]\ : in STD_LOGIC;
    \gen_mux_rd[5].mux_rd_fall2_r_reg[5]_0\ : in STD_LOGIC;
    \gen_mux_rd[5].mux_rd_fall2_r_reg[5]_1\ : in STD_LOGIC;
    \gen_mux_rd[6].mux_rd_fall2_r_reg[6]\ : in STD_LOGIC;
    \gen_mux_rd[6].mux_rd_fall2_r_reg[6]_0\ : in STD_LOGIC;
    \gen_mux_rd[6].mux_rd_fall2_r_reg[6]_1\ : in STD_LOGIC;
    \gen_mux_rd[7].mux_rd_fall2_r_reg[7]\ : in STD_LOGIC;
    \gen_mux_rd[7].mux_rd_fall2_r_reg[7]_0\ : in STD_LOGIC;
    \gen_mux_rd[7].mux_rd_fall2_r_reg[7]_1\ : in STD_LOGIC;
    \gen_mux_rd[0].mux_rd_rise3_r_reg[0]\ : in STD_LOGIC;
    \gen_mux_rd[0].mux_rd_rise3_r_reg[0]_0\ : in STD_LOGIC;
    \gen_mux_rd[0].mux_rd_rise3_r_reg[0]_1\ : in STD_LOGIC;
    \gen_mux_rd[1].mux_rd_rise3_r_reg[1]\ : in STD_LOGIC;
    \gen_mux_rd[1].mux_rd_rise3_r_reg[1]_0\ : in STD_LOGIC;
    \gen_mux_rd[1].mux_rd_rise3_r_reg[1]_1\ : in STD_LOGIC;
    \gen_mux_rd[2].mux_rd_rise3_r_reg[2]\ : in STD_LOGIC;
    \gen_mux_rd[2].mux_rd_rise3_r_reg[2]_0\ : in STD_LOGIC;
    \gen_mux_rd[2].mux_rd_rise3_r_reg[2]_1\ : in STD_LOGIC;
    \gen_mux_rd[3].mux_rd_rise3_r_reg[3]\ : in STD_LOGIC;
    \gen_mux_rd[3].mux_rd_rise3_r_reg[3]_0\ : in STD_LOGIC;
    \gen_mux_rd[3].mux_rd_rise3_r_reg[3]_1\ : in STD_LOGIC;
    \gen_mux_rd[4].mux_rd_rise3_r_reg[4]\ : in STD_LOGIC;
    \gen_mux_rd[4].mux_rd_rise3_r_reg[4]_0\ : in STD_LOGIC;
    \gen_mux_rd[4].mux_rd_rise3_r_reg[4]_1\ : in STD_LOGIC;
    \gen_mux_rd[5].mux_rd_rise3_r_reg[5]\ : in STD_LOGIC;
    \gen_mux_rd[5].mux_rd_rise3_r_reg[5]_0\ : in STD_LOGIC;
    \gen_mux_rd[5].mux_rd_rise3_r_reg[5]_1\ : in STD_LOGIC;
    \gen_mux_rd[6].mux_rd_rise3_r_reg[6]\ : in STD_LOGIC;
    \gen_mux_rd[6].mux_rd_rise3_r_reg[6]_0\ : in STD_LOGIC;
    \gen_mux_rd[6].mux_rd_rise3_r_reg[6]_1\ : in STD_LOGIC;
    \gen_mux_rd[7].mux_rd_rise3_r_reg[7]\ : in STD_LOGIC;
    \gen_mux_rd[7].mux_rd_rise3_r_reg[7]_0\ : in STD_LOGIC;
    \gen_mux_rd[7].mux_rd_rise3_r_reg[7]_1\ : in STD_LOGIC;
    \gen_mux_rd[0].mux_rd_fall3_r_reg[0]\ : in STD_LOGIC;
    \gen_mux_rd[0].mux_rd_fall3_r_reg[0]_0\ : in STD_LOGIC;
    \gen_mux_rd[0].mux_rd_fall3_r_reg[0]_1\ : in STD_LOGIC;
    \gen_mux_rd[1].mux_rd_fall3_r_reg[1]\ : in STD_LOGIC;
    \gen_mux_rd[1].mux_rd_fall3_r_reg[1]_0\ : in STD_LOGIC;
    \gen_mux_rd[1].mux_rd_fall3_r_reg[1]_1\ : in STD_LOGIC;
    \gen_mux_rd[2].mux_rd_fall3_r_reg[2]\ : in STD_LOGIC;
    \gen_mux_rd[2].mux_rd_fall3_r_reg[2]_0\ : in STD_LOGIC;
    \gen_mux_rd[2].mux_rd_fall3_r_reg[2]_1\ : in STD_LOGIC;
    \gen_mux_rd[3].mux_rd_fall3_r_reg[3]\ : in STD_LOGIC;
    \gen_mux_rd[3].mux_rd_fall3_r_reg[3]_0\ : in STD_LOGIC;
    \gen_mux_rd[3].mux_rd_fall3_r_reg[3]_1\ : in STD_LOGIC;
    \gen_mux_rd[4].mux_rd_fall3_r_reg[4]\ : in STD_LOGIC;
    \gen_mux_rd[4].mux_rd_fall3_r_reg[4]_0\ : in STD_LOGIC;
    \gen_mux_rd[4].mux_rd_fall3_r_reg[4]_1\ : in STD_LOGIC;
    \gen_mux_rd[5].mux_rd_fall3_r_reg[5]\ : in STD_LOGIC;
    \gen_mux_rd[5].mux_rd_fall3_r_reg[5]_0\ : in STD_LOGIC;
    \gen_mux_rd[5].mux_rd_fall3_r_reg[5]_1\ : in STD_LOGIC;
    \gen_mux_rd[6].mux_rd_fall3_r_reg[6]\ : in STD_LOGIC;
    \gen_mux_rd[6].mux_rd_fall3_r_reg[6]_0\ : in STD_LOGIC;
    \gen_mux_rd[6].mux_rd_fall3_r_reg[6]_1\ : in STD_LOGIC;
    \gen_mux_rd[7].mux_rd_fall3_r_reg[7]\ : in STD_LOGIC;
    \gen_mux_rd[7].mux_rd_fall3_r_reg[7]_0\ : in STD_LOGIC;
    \gen_mux_rd[7].mux_rd_fall3_r_reg[7]_1\ : in STD_LOGIC;
    \gen_mux_rd[1].mux_rd_rise0_r_reg[1]_2\ : in STD_LOGIC;
    \gen_mux_rd[1].mux_rd_rise0_r_reg[1]_3\ : in STD_LOGIC;
    \gen_mux_rd[2].mux_rd_rise0_r_reg[2]_2\ : in STD_LOGIC;
    \gen_mux_rd[3].mux_rd_rise0_r_reg[3]_2\ : in STD_LOGIC;
    \gen_mux_rd[5].mux_rd_rise0_r_reg[5]_2\ : in STD_LOGIC;
    \gen_mux_rd[6].mux_rd_rise0_r_reg[6]_2\ : in STD_LOGIC;
    \gen_mux_rd[7].mux_rd_rise0_r_reg[7]_2\ : in STD_LOGIC;
    \gen_mux_rd[1].mux_rd_fall0_r_reg[1]_2\ : in STD_LOGIC;
    \gen_mux_rd[3].mux_rd_fall0_r_reg[3]_2\ : in STD_LOGIC;
    \gen_mux_rd[5].mux_rd_fall0_r_reg[5]_2\ : in STD_LOGIC;
    \gen_mux_rd[6].mux_rd_fall0_r_reg[6]_2\ : in STD_LOGIC;
    \gen_mux_rd[7].mux_rd_fall0_r_reg[7]_2\ : in STD_LOGIC;
    \gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2\ : in STD_LOGIC;
    \gen_mux_rd[1].mux_rd_rise1_r_reg[1]_2\ : in STD_LOGIC;
    \gen_mux_rd[3].mux_rd_rise1_r_reg[3]_2\ : in STD_LOGIC;
    \gen_mux_rd[5].mux_rd_rise1_r_reg[5]_2\ : in STD_LOGIC;
    \gen_mux_rd[6].mux_rd_rise1_r_reg[6]_2\ : in STD_LOGIC;
    \gen_mux_rd[7].mux_rd_rise1_r_reg[7]_2\ : in STD_LOGIC;
    \gen_mux_rd[1].mux_rd_fall1_r_reg[1]_2\ : in STD_LOGIC;
    \gen_mux_rd[3].mux_rd_fall1_r_reg[3]_2\ : in STD_LOGIC;
    \gen_mux_rd[5].mux_rd_fall1_r_reg[5]_2\ : in STD_LOGIC;
    \gen_mux_rd[6].mux_rd_fall1_r_reg[6]_2\ : in STD_LOGIC;
    \gen_mux_rd[7].mux_rd_fall1_r_reg[7]_2\ : in STD_LOGIC;
    \gen_mux_rd[0].mux_rd_rise2_r_reg[0]_2\ : in STD_LOGIC;
    \gen_mux_rd[1].mux_rd_rise2_r_reg[1]_2\ : in STD_LOGIC;
    \gen_mux_rd[2].mux_rd_rise2_r_reg[2]_2\ : in STD_LOGIC;
    \gen_mux_rd[3].mux_rd_rise2_r_reg[3]_2\ : in STD_LOGIC;
    \gen_mux_rd[5].mux_rd_rise2_r_reg[5]_2\ : in STD_LOGIC;
    \gen_mux_rd[6].mux_rd_rise2_r_reg[6]_2\ : in STD_LOGIC;
    \gen_mux_rd[7].mux_rd_rise2_r_reg[7]_2\ : in STD_LOGIC;
    \gen_mux_rd[1].mux_rd_fall2_r_reg[1]_2\ : in STD_LOGIC;
    \gen_mux_rd[2].mux_rd_fall2_r_reg[2]_2\ : in STD_LOGIC;
    \gen_mux_rd[3].mux_rd_fall2_r_reg[3]_2\ : in STD_LOGIC;
    \gen_mux_rd[5].mux_rd_fall2_r_reg[5]_2\ : in STD_LOGIC;
    \gen_mux_rd[6].mux_rd_fall2_r_reg[6]_2\ : in STD_LOGIC;
    \gen_mux_rd[7].mux_rd_fall2_r_reg[7]_2\ : in STD_LOGIC;
    \gen_mux_rd[1].mux_rd_rise3_r_reg[1]_2\ : in STD_LOGIC;
    \gen_mux_rd[2].mux_rd_rise3_r_reg[2]_2\ : in STD_LOGIC;
    \gen_mux_rd[3].mux_rd_rise3_r_reg[3]_2\ : in STD_LOGIC;
    \gen_mux_rd[5].mux_rd_rise3_r_reg[5]_2\ : in STD_LOGIC;
    \gen_mux_rd[6].mux_rd_rise3_r_reg[6]_2\ : in STD_LOGIC;
    \gen_mux_rd[7].mux_rd_rise3_r_reg[7]_2\ : in STD_LOGIC;
    \gen_mux_rd[0].mux_rd_fall3_r_reg[0]_2\ : in STD_LOGIC;
    \gen_mux_rd[1].mux_rd_fall3_r_reg[1]_2\ : in STD_LOGIC;
    \gen_mux_rd[2].mux_rd_fall3_r_reg[2]_2\ : in STD_LOGIC;
    \gen_mux_rd[3].mux_rd_fall3_r_reg[3]_2\ : in STD_LOGIC;
    \gen_mux_rd[4].mux_rd_fall3_r_reg[4]_2\ : in STD_LOGIC;
    \gen_mux_rd[5].mux_rd_fall3_r_reg[5]_2\ : in STD_LOGIC;
    \gen_mux_rd[6].mux_rd_fall3_r_reg[6]_2\ : in STD_LOGIC;
    \gen_mux_rd[7].mux_rd_fall3_r_reg[7]_2\ : in STD_LOGIC;
    \gen_mux_rd[0].mux_rd_rise0_r_reg[0]_3\ : in STD_LOGIC;
    \gen_mux_rd[4].mux_rd_rise0_r_reg[4]_2\ : in STD_LOGIC;
    \gen_mux_rd[0].mux_rd_fall0_r_reg[0]_2\ : in STD_LOGIC;
    \gen_mux_rd[2].mux_rd_fall0_r_reg[2]_2\ : in STD_LOGIC;
    \gen_mux_rd[4].mux_rd_fall0_r_reg[4]_2\ : in STD_LOGIC;
    \gen_mux_rd[2].mux_rd_rise1_r_reg[2]_2\ : in STD_LOGIC;
    \gen_mux_rd[4].mux_rd_rise1_r_reg[4]_2\ : in STD_LOGIC;
    \gen_mux_rd[0].mux_rd_fall1_r_reg[0]_2\ : in STD_LOGIC;
    \gen_mux_rd[2].mux_rd_fall1_r_reg[2]_2\ : in STD_LOGIC;
    \gen_mux_rd[4].mux_rd_fall1_r_reg[4]_2\ : in STD_LOGIC;
    \gen_mux_rd[4].mux_rd_rise2_r_reg[4]_2\ : in STD_LOGIC;
    \gen_mux_rd[0].mux_rd_fall2_r_reg[0]_2\ : in STD_LOGIC;
    \gen_mux_rd[4].mux_rd_fall2_r_reg[4]_2\ : in STD_LOGIC;
    \gen_mux_rd[0].mux_rd_rise3_r_reg[0]_2\ : in STD_LOGIC;
    \gen_mux_rd[4].mux_rd_rise3_r_reg[4]_2\ : in STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 67 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of mig_mig_7series_v4_2_ddr_if_post_fifo_36 : entity is "mig_7series_v4_2_ddr_if_post_fifo";
end mig_mig_7series_v4_2_ddr_if_post_fifo_36;

architecture STRUCTURE of mig_mig_7series_v4_2_ddr_if_post_fifo_36 is
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]\ : STD_LOGIC;
  signal \gen_mux_rd[0].mux_rd_fall0_r[0]_i_2_n_0\ : STD_LOGIC;
  signal \gen_mux_rd[0].mux_rd_fall1_r[0]_i_2_n_0\ : STD_LOGIC;
  signal \gen_mux_rd[0].mux_rd_fall2_r[0]_i_2_n_0\ : STD_LOGIC;
  signal \gen_mux_rd[0].mux_rd_fall3_r[0]_i_2_n_0\ : STD_LOGIC;
  signal \gen_mux_rd[0].mux_rd_rise0_r[0]_i_3_n_0\ : STD_LOGIC;
  signal \gen_mux_rd[0].mux_rd_rise1_r[0]_i_2_n_0\ : STD_LOGIC;
  signal \gen_mux_rd[0].mux_rd_rise2_r[0]_i_2_n_0\ : STD_LOGIC;
  signal \gen_mux_rd[0].mux_rd_rise3_r[0]_i_2_n_0\ : STD_LOGIC;
  signal \gen_mux_rd[1].mux_rd_fall0_r[1]_i_2_n_0\ : STD_LOGIC;
  signal \gen_mux_rd[1].mux_rd_fall1_r[1]_i_2_n_0\ : STD_LOGIC;
  signal \gen_mux_rd[1].mux_rd_fall2_r[1]_i_2_n_0\ : STD_LOGIC;
  signal \gen_mux_rd[1].mux_rd_fall3_r[1]_i_2_n_0\ : STD_LOGIC;
  signal \gen_mux_rd[1].mux_rd_rise0_r[1]_i_2_n_0\ : STD_LOGIC;
  signal \gen_mux_rd[1].mux_rd_rise1_r[1]_i_2_n_0\ : STD_LOGIC;
  signal \gen_mux_rd[1].mux_rd_rise2_r[1]_i_2_n_0\ : STD_LOGIC;
  signal \gen_mux_rd[1].mux_rd_rise3_r[1]_i_2_n_0\ : STD_LOGIC;
  signal \gen_mux_rd[2].mux_rd_fall0_r[2]_i_2_n_0\ : STD_LOGIC;
  signal \gen_mux_rd[2].mux_rd_fall1_r[2]_i_2_n_0\ : STD_LOGIC;
  signal \gen_mux_rd[2].mux_rd_fall2_r[2]_i_2_n_0\ : STD_LOGIC;
  signal \gen_mux_rd[2].mux_rd_fall3_r[2]_i_2_n_0\ : STD_LOGIC;
  signal \gen_mux_rd[2].mux_rd_rise0_r[2]_i_2_n_0\ : STD_LOGIC;
  signal \gen_mux_rd[2].mux_rd_rise1_r[2]_i_2_n_0\ : STD_LOGIC;
  signal \gen_mux_rd[2].mux_rd_rise2_r[2]_i_2_n_0\ : STD_LOGIC;
  signal \gen_mux_rd[2].mux_rd_rise3_r[2]_i_2_n_0\ : STD_LOGIC;
  signal \gen_mux_rd[3].mux_rd_fall0_r[3]_i_2_n_0\ : STD_LOGIC;
  signal \gen_mux_rd[3].mux_rd_fall1_r[3]_i_2_n_0\ : STD_LOGIC;
  signal \gen_mux_rd[3].mux_rd_fall2_r[3]_i_2_n_0\ : STD_LOGIC;
  signal \gen_mux_rd[3].mux_rd_fall3_r[3]_i_2_n_0\ : STD_LOGIC;
  signal \gen_mux_rd[3].mux_rd_rise0_r[3]_i_2_n_0\ : STD_LOGIC;
  signal \gen_mux_rd[3].mux_rd_rise1_r[3]_i_2_n_0\ : STD_LOGIC;
  signal \gen_mux_rd[3].mux_rd_rise2_r[3]_i_2_n_0\ : STD_LOGIC;
  signal \gen_mux_rd[3].mux_rd_rise3_r[3]_i_2_n_0\ : STD_LOGIC;
  signal \gen_mux_rd[4].mux_rd_fall0_r[4]_i_2_n_0\ : STD_LOGIC;
  signal \gen_mux_rd[4].mux_rd_fall1_r[4]_i_2_n_0\ : STD_LOGIC;
  signal \gen_mux_rd[4].mux_rd_fall2_r[4]_i_2_n_0\ : STD_LOGIC;
  signal \gen_mux_rd[4].mux_rd_fall3_r[4]_i_2_n_0\ : STD_LOGIC;
  signal \gen_mux_rd[4].mux_rd_rise0_r[4]_i_2_n_0\ : STD_LOGIC;
  signal \gen_mux_rd[4].mux_rd_rise1_r[4]_i_2_n_0\ : STD_LOGIC;
  signal \gen_mux_rd[4].mux_rd_rise2_r[4]_i_2_n_0\ : STD_LOGIC;
  signal \gen_mux_rd[4].mux_rd_rise3_r[4]_i_2_n_0\ : STD_LOGIC;
  signal \gen_mux_rd[5].mux_rd_fall0_r[5]_i_2_n_0\ : STD_LOGIC;
  signal \gen_mux_rd[5].mux_rd_fall1_r[5]_i_2_n_0\ : STD_LOGIC;
  signal \gen_mux_rd[5].mux_rd_fall2_r[5]_i_2_n_0\ : STD_LOGIC;
  signal \gen_mux_rd[5].mux_rd_fall3_r[5]_i_2_n_0\ : STD_LOGIC;
  signal \gen_mux_rd[5].mux_rd_rise0_r[5]_i_2_n_0\ : STD_LOGIC;
  signal \gen_mux_rd[5].mux_rd_rise1_r[5]_i_2_n_0\ : STD_LOGIC;
  signal \gen_mux_rd[5].mux_rd_rise2_r[5]_i_2_n_0\ : STD_LOGIC;
  signal \gen_mux_rd[5].mux_rd_rise3_r[5]_i_2_n_0\ : STD_LOGIC;
  signal \gen_mux_rd[6].mux_rd_fall0_r[6]_i_2_n_0\ : STD_LOGIC;
  signal \gen_mux_rd[6].mux_rd_fall1_r[6]_i_2_n_0\ : STD_LOGIC;
  signal \gen_mux_rd[6].mux_rd_fall2_r[6]_i_2_n_0\ : STD_LOGIC;
  signal \gen_mux_rd[6].mux_rd_fall3_r[6]_i_2_n_0\ : STD_LOGIC;
  signal \gen_mux_rd[6].mux_rd_rise0_r[6]_i_2_n_0\ : STD_LOGIC;
  signal \gen_mux_rd[6].mux_rd_rise1_r[6]_i_2_n_0\ : STD_LOGIC;
  signal \gen_mux_rd[6].mux_rd_rise2_r[6]_i_2_n_0\ : STD_LOGIC;
  signal \gen_mux_rd[6].mux_rd_rise3_r[6]_i_2_n_0\ : STD_LOGIC;
  signal \gen_mux_rd[7].mux_rd_fall0_r[7]_i_2_n_0\ : STD_LOGIC;
  signal \gen_mux_rd[7].mux_rd_fall1_r[7]_i_2_n_0\ : STD_LOGIC;
  signal \gen_mux_rd[7].mux_rd_fall2_r[7]_i_2_n_0\ : STD_LOGIC;
  signal \gen_mux_rd[7].mux_rd_fall3_r[7]_i_2_n_0\ : STD_LOGIC;
  signal \gen_mux_rd[7].mux_rd_rise0_r[7]_i_2_n_0\ : STD_LOGIC;
  signal \gen_mux_rd[7].mux_rd_rise1_r[7]_i_2_n_0\ : STD_LOGIC;
  signal \gen_mux_rd[7].mux_rd_rise2_r[7]_i_2_n_0\ : STD_LOGIC;
  signal \gen_mux_rd[7].mux_rd_rise3_r[7]_i_2_n_0\ : STD_LOGIC;
  signal mem_out : STD_LOGIC_VECTOR ( 79 downto 16 );
  signal mem_reg_0_3_12_17_n_0 : STD_LOGIC;
  signal mem_reg_0_3_12_17_n_1 : STD_LOGIC;
  signal mem_reg_0_3_12_17_n_2 : STD_LOGIC;
  signal mem_reg_0_3_12_17_n_3 : STD_LOGIC;
  signal \my_empty[4]_i_1__4_n_0\ : STD_LOGIC;
  signal \my_empty[4]_i_2__0_n_0\ : STD_LOGIC;
  signal my_empty_0 : STD_LOGIC_VECTOR ( 4 downto 1 );
  signal \my_empty_inst_rep__0_n_0\ : STD_LOGIC;
  signal \^my_empty_reg[4]_0\ : STD_LOGIC;
  signal \^my_empty_reg[4]_1\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \my_empty_reg[4]_rep__0_n_0\ : STD_LOGIC;
  signal \my_empty_reg[4]_rep_n_0\ : STD_LOGIC;
  signal my_full : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \my_full[0]_i_1__0_n_0\ : STD_LOGIC;
  signal \my_full[1]_i_1__0_n_0\ : STD_LOGIC;
  signal \my_full[1]_i_2__0_n_0\ : STD_LOGIC;
  signal rd_ptr : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \rd_ptr[0]_i_1__0_n_0\ : STD_LOGIC;
  signal \rd_ptr[1]_i_1__0_n_0\ : STD_LOGIC;
  signal rd_ptr_timing : STD_LOGIC_VECTOR ( 1 downto 0 );
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of rd_ptr_timing : signal is "true";
  attribute syn_maxfan : string;
  attribute syn_maxfan of rd_ptr_timing : signal is "10";
  signal \rd_ptr_timing[0]_i_1__2_n_0\ : STD_LOGIC;
  signal \rd_ptr_timing[1]_i_1__2_n_0\ : STD_LOGIC;
  signal wr_en : STD_LOGIC;
  attribute MAX_FANOUT : string;
  attribute MAX_FANOUT of wr_en : signal is "40";
  attribute RTL_MAX_FANOUT : string;
  attribute RTL_MAX_FANOUT of wr_en : signal is "found";
  attribute syn_maxfan of wr_en : signal is "10";
  signal wr_ptr : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \wr_ptr[0]_i_1__2_n_0\ : STD_LOGIC;
  signal \wr_ptr[1]_i_1__2_n_0\ : STD_LOGIC;
  signal NLW_mem_reg_0_3_12_17_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_3_18_23_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_3_24_29_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_3_30_35_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_3_36_41_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_3_42_47_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_3_48_53_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_3_54_59_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_3_60_65_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_3_66_71_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_3_72_77_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_3_78_79_DOB_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_3_78_79_DOC_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_3_78_79_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \app_rd_data[104]_INST_0\ : label is "soft_lutpair743";
  attribute SOFT_HLUTNM of \app_rd_data[105]_INST_0\ : label is "soft_lutpair743";
  attribute SOFT_HLUTNM of \app_rd_data[106]_INST_0\ : label is "soft_lutpair733";
  attribute SOFT_HLUTNM of \app_rd_data[107]_INST_0\ : label is "soft_lutpair741";
  attribute SOFT_HLUTNM of \app_rd_data[108]_INST_0\ : label is "soft_lutpair740";
  attribute SOFT_HLUTNM of \app_rd_data[109]_INST_0\ : label is "soft_lutpair731";
  attribute SOFT_HLUTNM of \app_rd_data[110]_INST_0\ : label is "soft_lutpair737";
  attribute SOFT_HLUTNM of \app_rd_data[111]_INST_0\ : label is "soft_lutpair736";
  attribute SOFT_HLUTNM of \app_rd_data[168]_INST_0\ : label is "soft_lutpair724";
  attribute SOFT_HLUTNM of \app_rd_data[169]_INST_0\ : label is "soft_lutpair719";
  attribute SOFT_HLUTNM of \app_rd_data[170]_INST_0\ : label is "soft_lutpair713";
  attribute SOFT_HLUTNM of \app_rd_data[171]_INST_0\ : label is "soft_lutpair722";
  attribute SOFT_HLUTNM of \app_rd_data[172]_INST_0\ : label is "soft_lutpair717";
  attribute SOFT_HLUTNM of \app_rd_data[173]_INST_0\ : label is "soft_lutpair726";
  attribute SOFT_HLUTNM of \app_rd_data[174]_INST_0\ : label is "soft_lutpair720";
  attribute SOFT_HLUTNM of \app_rd_data[175]_INST_0\ : label is "soft_lutpair716";
  attribute SOFT_HLUTNM of \app_rd_data[232]_INST_0\ : label is "soft_lutpair744";
  attribute SOFT_HLUTNM of \app_rd_data[233]_INST_0\ : label is "soft_lutpair733";
  attribute SOFT_HLUTNM of \app_rd_data[234]_INST_0\ : label is "soft_lutpair742";
  attribute SOFT_HLUTNM of \app_rd_data[235]_INST_0\ : label is "soft_lutpair739";
  attribute SOFT_HLUTNM of \app_rd_data[236]_INST_0\ : label is "soft_lutpair731";
  attribute SOFT_HLUTNM of \app_rd_data[237]_INST_0\ : label is "soft_lutpair738";
  attribute SOFT_HLUTNM of \app_rd_data[238]_INST_0\ : label is "soft_lutpair737";
  attribute SOFT_HLUTNM of \app_rd_data[239]_INST_0\ : label is "soft_lutpair728";
  attribute SOFT_HLUTNM of \app_rd_data[296]_INST_0\ : label is "soft_lutpair719";
  attribute SOFT_HLUTNM of \app_rd_data[297]_INST_0\ : label is "soft_lutpair727";
  attribute SOFT_HLUTNM of \app_rd_data[298]_INST_0\ : label is "soft_lutpair722";
  attribute SOFT_HLUTNM of \app_rd_data[299]_INST_0\ : label is "soft_lutpair713";
  attribute SOFT_HLUTNM of \app_rd_data[300]_INST_0\ : label is "soft_lutpair726";
  attribute SOFT_HLUTNM of \app_rd_data[301]_INST_0\ : label is "soft_lutpair721";
  attribute SOFT_HLUTNM of \app_rd_data[302]_INST_0\ : label is "soft_lutpair716";
  attribute SOFT_HLUTNM of \app_rd_data[303]_INST_0\ : label is "soft_lutpair725";
  attribute SOFT_HLUTNM of \app_rd_data[360]_INST_0\ : label is "soft_lutpair734";
  attribute SOFT_HLUTNM of \app_rd_data[361]_INST_0\ : label is "soft_lutpair742";
  attribute SOFT_HLUTNM of \app_rd_data[362]_INST_0\ : label is "soft_lutpair741";
  attribute SOFT_HLUTNM of \app_rd_data[363]_INST_0\ : label is "soft_lutpair732";
  attribute SOFT_HLUTNM of \app_rd_data[364]_INST_0\ : label is "soft_lutpair740";
  attribute SOFT_HLUTNM of \app_rd_data[365]_INST_0\ : label is "soft_lutpair730";
  attribute SOFT_HLUTNM of \app_rd_data[366]_INST_0\ : label is "soft_lutpair728";
  attribute SOFT_HLUTNM of \app_rd_data[367]_INST_0\ : label is "soft_lutpair735";
  attribute SOFT_HLUTNM of \app_rd_data[40]_INST_0\ : label is "soft_lutpair729";
  attribute SOFT_HLUTNM of \app_rd_data[41]_INST_0\ : label is "soft_lutpair723";
  attribute SOFT_HLUTNM of \app_rd_data[424]_INST_0\ : label is "soft_lutpair729";
  attribute SOFT_HLUTNM of \app_rd_data[425]_INST_0\ : label is "soft_lutpair723";
  attribute SOFT_HLUTNM of \app_rd_data[426]_INST_0\ : label is "soft_lutpair718";
  attribute SOFT_HLUTNM of \app_rd_data[427]_INST_0\ : label is "soft_lutpair724";
  attribute SOFT_HLUTNM of \app_rd_data[428]_INST_0\ : label is "soft_lutpair721";
  attribute SOFT_HLUTNM of \app_rd_data[429]_INST_0\ : label is "soft_lutpair717";
  attribute SOFT_HLUTNM of \app_rd_data[42]_INST_0\ : label is "soft_lutpair718";
  attribute SOFT_HLUTNM of \app_rd_data[430]_INST_0\ : label is "soft_lutpair725";
  attribute SOFT_HLUTNM of \app_rd_data[431]_INST_0\ : label is "soft_lutpair720";
  attribute SOFT_HLUTNM of \app_rd_data[43]_INST_0\ : label is "soft_lutpair727";
  attribute SOFT_HLUTNM of \app_rd_data[44]_INST_0\ : label is "soft_lutpair715";
  attribute SOFT_HLUTNM of \app_rd_data[45]_INST_0\ : label is "soft_lutpair714";
  attribute SOFT_HLUTNM of \app_rd_data[46]_INST_0\ : label is "soft_lutpair715";
  attribute SOFT_HLUTNM of \app_rd_data[47]_INST_0\ : label is "soft_lutpair714";
  attribute SOFT_HLUTNM of \app_rd_data[488]_INST_0\ : label is "soft_lutpair744";
  attribute SOFT_HLUTNM of \app_rd_data[489]_INST_0\ : label is "soft_lutpair739";
  attribute SOFT_HLUTNM of \app_rd_data[490]_INST_0\ : label is "soft_lutpair732";
  attribute SOFT_HLUTNM of \app_rd_data[491]_INST_0\ : label is "soft_lutpair734";
  attribute SOFT_HLUTNM of \app_rd_data[492]_INST_0\ : label is "soft_lutpair738";
  attribute SOFT_HLUTNM of \app_rd_data[493]_INST_0\ : label is "soft_lutpair730";
  attribute SOFT_HLUTNM of \app_rd_data[494]_INST_0\ : label is "soft_lutpair736";
  attribute SOFT_HLUTNM of \app_rd_data[495]_INST_0\ : label is "soft_lutpair735";
  attribute METHODOLOGY_DRC_VIOS : string;
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_3_12_17 : label is "";
  attribute RTL_RAM_BITS : integer;
  attribute RTL_RAM_BITS of mem_reg_0_3_12_17 : label is 320;
  attribute RTL_RAM_NAME : string;
  attribute RTL_RAM_NAME of mem_reg_0_3_12_17 : label is "dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem";
  attribute ram_addr_begin : integer;
  attribute ram_addr_begin of mem_reg_0_3_12_17 : label is 0;
  attribute ram_addr_end : integer;
  attribute ram_addr_end of mem_reg_0_3_12_17 : label is 3;
  attribute ram_offset : integer;
  attribute ram_offset of mem_reg_0_3_12_17 : label is 0;
  attribute ram_slice_begin : integer;
  attribute ram_slice_begin of mem_reg_0_3_12_17 : label is 12;
  attribute ram_slice_end : integer;
  attribute ram_slice_end of mem_reg_0_3_12_17 : label is 17;
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_3_18_23 : label is "";
  attribute RTL_RAM_BITS of mem_reg_0_3_18_23 : label is 320;
  attribute RTL_RAM_NAME of mem_reg_0_3_18_23 : label is "dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem";
  attribute ram_addr_begin of mem_reg_0_3_18_23 : label is 0;
  attribute ram_addr_end of mem_reg_0_3_18_23 : label is 3;
  attribute ram_offset of mem_reg_0_3_18_23 : label is 0;
  attribute ram_slice_begin of mem_reg_0_3_18_23 : label is 18;
  attribute ram_slice_end of mem_reg_0_3_18_23 : label is 23;
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_3_24_29 : label is "";
  attribute RTL_RAM_BITS of mem_reg_0_3_24_29 : label is 320;
  attribute RTL_RAM_NAME of mem_reg_0_3_24_29 : label is "dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem";
  attribute ram_addr_begin of mem_reg_0_3_24_29 : label is 0;
  attribute ram_addr_end of mem_reg_0_3_24_29 : label is 3;
  attribute ram_offset of mem_reg_0_3_24_29 : label is 0;
  attribute ram_slice_begin of mem_reg_0_3_24_29 : label is 24;
  attribute ram_slice_end of mem_reg_0_3_24_29 : label is 29;
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_3_30_35 : label is "";
  attribute RTL_RAM_BITS of mem_reg_0_3_30_35 : label is 320;
  attribute RTL_RAM_NAME of mem_reg_0_3_30_35 : label is "dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem";
  attribute ram_addr_begin of mem_reg_0_3_30_35 : label is 0;
  attribute ram_addr_end of mem_reg_0_3_30_35 : label is 3;
  attribute ram_offset of mem_reg_0_3_30_35 : label is 0;
  attribute ram_slice_begin of mem_reg_0_3_30_35 : label is 30;
  attribute ram_slice_end of mem_reg_0_3_30_35 : label is 35;
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_3_36_41 : label is "";
  attribute RTL_RAM_BITS of mem_reg_0_3_36_41 : label is 320;
  attribute RTL_RAM_NAME of mem_reg_0_3_36_41 : label is "dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem";
  attribute ram_addr_begin of mem_reg_0_3_36_41 : label is 0;
  attribute ram_addr_end of mem_reg_0_3_36_41 : label is 3;
  attribute ram_offset of mem_reg_0_3_36_41 : label is 0;
  attribute ram_slice_begin of mem_reg_0_3_36_41 : label is 36;
  attribute ram_slice_end of mem_reg_0_3_36_41 : label is 41;
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_3_42_47 : label is "";
  attribute RTL_RAM_BITS of mem_reg_0_3_42_47 : label is 320;
  attribute RTL_RAM_NAME of mem_reg_0_3_42_47 : label is "dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem";
  attribute ram_addr_begin of mem_reg_0_3_42_47 : label is 0;
  attribute ram_addr_end of mem_reg_0_3_42_47 : label is 3;
  attribute ram_offset of mem_reg_0_3_42_47 : label is 0;
  attribute ram_slice_begin of mem_reg_0_3_42_47 : label is 42;
  attribute ram_slice_end of mem_reg_0_3_42_47 : label is 47;
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_3_48_53 : label is "";
  attribute RTL_RAM_BITS of mem_reg_0_3_48_53 : label is 320;
  attribute RTL_RAM_NAME of mem_reg_0_3_48_53 : label is "dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem";
  attribute ram_addr_begin of mem_reg_0_3_48_53 : label is 0;
  attribute ram_addr_end of mem_reg_0_3_48_53 : label is 3;
  attribute ram_offset of mem_reg_0_3_48_53 : label is 0;
  attribute ram_slice_begin of mem_reg_0_3_48_53 : label is 48;
  attribute ram_slice_end of mem_reg_0_3_48_53 : label is 53;
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_3_54_59 : label is "";
  attribute RTL_RAM_BITS of mem_reg_0_3_54_59 : label is 320;
  attribute RTL_RAM_NAME of mem_reg_0_3_54_59 : label is "dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem";
  attribute ram_addr_begin of mem_reg_0_3_54_59 : label is 0;
  attribute ram_addr_end of mem_reg_0_3_54_59 : label is 3;
  attribute ram_offset of mem_reg_0_3_54_59 : label is 0;
  attribute ram_slice_begin of mem_reg_0_3_54_59 : label is 54;
  attribute ram_slice_end of mem_reg_0_3_54_59 : label is 59;
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_3_60_65 : label is "";
  attribute RTL_RAM_BITS of mem_reg_0_3_60_65 : label is 320;
  attribute RTL_RAM_NAME of mem_reg_0_3_60_65 : label is "dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem";
  attribute ram_addr_begin of mem_reg_0_3_60_65 : label is 0;
  attribute ram_addr_end of mem_reg_0_3_60_65 : label is 3;
  attribute ram_offset of mem_reg_0_3_60_65 : label is 0;
  attribute ram_slice_begin of mem_reg_0_3_60_65 : label is 60;
  attribute ram_slice_end of mem_reg_0_3_60_65 : label is 65;
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_3_66_71 : label is "";
  attribute RTL_RAM_BITS of mem_reg_0_3_66_71 : label is 320;
  attribute RTL_RAM_NAME of mem_reg_0_3_66_71 : label is "dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem";
  attribute ram_addr_begin of mem_reg_0_3_66_71 : label is 0;
  attribute ram_addr_end of mem_reg_0_3_66_71 : label is 3;
  attribute ram_offset of mem_reg_0_3_66_71 : label is 0;
  attribute ram_slice_begin of mem_reg_0_3_66_71 : label is 66;
  attribute ram_slice_end of mem_reg_0_3_66_71 : label is 71;
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_3_72_77 : label is "";
  attribute RTL_RAM_BITS of mem_reg_0_3_72_77 : label is 320;
  attribute RTL_RAM_NAME of mem_reg_0_3_72_77 : label is "dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem";
  attribute ram_addr_begin of mem_reg_0_3_72_77 : label is 0;
  attribute ram_addr_end of mem_reg_0_3_72_77 : label is 3;
  attribute ram_offset of mem_reg_0_3_72_77 : label is 0;
  attribute ram_slice_begin of mem_reg_0_3_72_77 : label is 72;
  attribute ram_slice_end of mem_reg_0_3_72_77 : label is 77;
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_3_78_79 : label is "";
  attribute RTL_RAM_BITS of mem_reg_0_3_78_79 : label is 320;
  attribute RTL_RAM_NAME of mem_reg_0_3_78_79 : label is "dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem";
  attribute ram_addr_begin of mem_reg_0_3_78_79 : label is 0;
  attribute ram_addr_end of mem_reg_0_3_78_79 : label is 3;
  attribute ram_offset of mem_reg_0_3_78_79 : label is 0;
  attribute ram_slice_begin of mem_reg_0_3_78_79 : label is 78;
  attribute ram_slice_end of mem_reg_0_3_78_79 : label is 79;
  attribute SOFT_HLUTNM of \my_empty_inst__4\ : label is "soft_lutpair745";
  attribute SOFT_HLUTNM of \my_empty_inst__5\ : label is "soft_lutpair745";
  attribute IS_FANOUT_CONSTRAINED : integer;
  attribute IS_FANOUT_CONSTRAINED of \my_empty_inst_rep__0\ : label is 1;
  attribute ORIG_CELL_NAME : string;
  attribute ORIG_CELL_NAME of \my_empty_reg[4]\ : label is "my_empty_reg[4]";
  attribute ORIG_CELL_NAME of \my_empty_reg[4]_rep\ : label is "my_empty_reg[4]";
  attribute ORIG_CELL_NAME of \my_empty_reg[4]_rep__0\ : label is "my_empty_reg[4]";
  attribute SOFT_HLUTNM of \rd_ptr[0]_i_1__0\ : label is "soft_lutpair712";
  attribute SOFT_HLUTNM of \rd_ptr[1]_i_1__0\ : label is "soft_lutpair712";
  attribute syn_maxfan of \rd_ptr_reg[0]\ : label is "10";
  attribute syn_maxfan of \rd_ptr_reg[1]\ : label is "10";
  attribute KEEP : string;
  attribute KEEP of \rd_ptr_timing_reg[0]\ : label is "yes";
  attribute syn_maxfan of \rd_ptr_timing_reg[0]\ : label is "10";
  attribute KEEP of \rd_ptr_timing_reg[1]\ : label is "yes";
  attribute syn_maxfan of \rd_ptr_timing_reg[1]\ : label is "10";
  attribute SOFT_HLUTNM of \wr_ptr[1]_i_4__1\ : label is "soft_lutpair711";
  attribute SOFT_HLUTNM of \wr_ptr[1]_i_7\ : label is "soft_lutpair711";
  attribute syn_maxfan of \wr_ptr_reg[0]\ : label is "10";
  attribute syn_maxfan of \wr_ptr_reg[1]\ : label is "10";
begin
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]\;
  \my_empty_reg[4]_0\ <= \^my_empty_reg[4]_0\;
  \my_empty_reg[4]_1\(0) <= \^my_empty_reg[4]_1\(0);
\app_rd_data[104]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(5),
      I1 => \my_empty_inst_rep__0_n_0\,
      I2 => mem_out(17),
      O => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]\
    );
\app_rd_data[105]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(13),
      I1 => \my_empty_inst_rep__0_n_0\,
      I2 => mem_out(25),
      O => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]\
    );
\app_rd_data[106]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(21),
      I1 => \my_empty_inst_rep__0_n_0\,
      I2 => mem_out(33),
      O => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]\
    );
\app_rd_data[107]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(29),
      I1 => \my_empty_inst_rep__0_n_0\,
      I2 => mem_out(41),
      O => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]\
    );
\app_rd_data[108]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(37),
      I1 => my_empty_0(4),
      I2 => mem_out(49),
      O => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]\
    );
\app_rd_data[109]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(45),
      I1 => my_empty_0(4),
      I2 => mem_out(57),
      O => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]\
    );
\app_rd_data[110]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(53),
      I1 => my_empty_0(4),
      I2 => mem_out(65),
      O => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]\
    );
\app_rd_data[111]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(61),
      I1 => my_empty_0(4),
      I2 => mem_out(73),
      O => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]\
    );
\app_rd_data[168]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(6),
      I1 => \my_empty_inst_rep__0_n_0\,
      I2 => mem_out(18),
      O => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]\
    );
\app_rd_data[169]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(14),
      I1 => \my_empty_inst_rep__0_n_0\,
      I2 => mem_out(26),
      O => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]\
    );
\app_rd_data[170]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(22),
      I1 => \my_empty_inst_rep__0_n_0\,
      I2 => mem_out(34),
      O => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]\
    );
\app_rd_data[171]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(30),
      I1 => \my_empty_inst_rep__0_n_0\,
      I2 => mem_out(42),
      O => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]\
    );
\app_rd_data[172]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(38),
      I1 => my_empty_0(4),
      I2 => mem_out(50),
      O => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]\
    );
\app_rd_data[173]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(46),
      I1 => my_empty_0(4),
      I2 => mem_out(58),
      O => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]\
    );
\app_rd_data[174]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(54),
      I1 => my_empty_0(4),
      I2 => mem_out(66),
      O => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]\
    );
\app_rd_data[175]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(62),
      I1 => my_empty_0(4),
      I2 => mem_out(74),
      O => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]\
    );
\app_rd_data[232]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(7),
      I1 => \my_empty_inst_rep__0_n_0\,
      I2 => mem_out(19),
      O => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]\
    );
\app_rd_data[233]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(15),
      I1 => \my_empty_inst_rep__0_n_0\,
      I2 => mem_out(27),
      O => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]\
    );
\app_rd_data[234]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(23),
      I1 => \my_empty_inst_rep__0_n_0\,
      I2 => mem_out(35),
      O => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]\
    );
\app_rd_data[235]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(31),
      I1 => \my_empty_inst_rep__0_n_0\,
      I2 => mem_out(43),
      O => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]\
    );
\app_rd_data[236]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(39),
      I1 => my_empty_0(4),
      I2 => mem_out(51),
      O => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]\
    );
\app_rd_data[237]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(47),
      I1 => my_empty_0(4),
      I2 => mem_out(59),
      O => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]\
    );
\app_rd_data[238]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(55),
      I1 => my_empty_0(4),
      I2 => mem_out(67),
      O => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]\
    );
\app_rd_data[239]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(63),
      I1 => my_empty_0(4),
      I2 => mem_out(75),
      O => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]\
    );
\app_rd_data[296]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(8),
      I1 => \my_empty_inst_rep__0_n_0\,
      I2 => mem_out(20),
      O => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]\
    );
\app_rd_data[297]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(16),
      I1 => \my_empty_inst_rep__0_n_0\,
      I2 => mem_out(28),
      O => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]\
    );
\app_rd_data[298]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(24),
      I1 => \my_empty_inst_rep__0_n_0\,
      I2 => mem_out(36),
      O => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]\
    );
\app_rd_data[299]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(32),
      I1 => \my_empty_inst_rep__0_n_0\,
      I2 => mem_out(44),
      O => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]\
    );
\app_rd_data[300]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(40),
      I1 => my_empty_0(4),
      I2 => mem_out(52),
      O => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]\
    );
\app_rd_data[301]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(48),
      I1 => my_empty_0(4),
      I2 => mem_out(60),
      O => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]\
    );
\app_rd_data[302]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(56),
      I1 => my_empty_0(4),
      I2 => mem_out(68),
      O => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]\
    );
\app_rd_data[303]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(64),
      I1 => my_empty_0(4),
      I2 => mem_out(76),
      O => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]\
    );
\app_rd_data[360]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(9),
      I1 => \my_empty_inst_rep__0_n_0\,
      I2 => mem_out(21),
      O => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]\
    );
\app_rd_data[361]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(17),
      I1 => \my_empty_inst_rep__0_n_0\,
      I2 => mem_out(29),
      O => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]\
    );
\app_rd_data[362]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(25),
      I1 => \my_empty_inst_rep__0_n_0\,
      I2 => mem_out(37),
      O => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]\
    );
\app_rd_data[363]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(33),
      I1 => \my_empty_inst_rep__0_n_0\,
      I2 => mem_out(45),
      O => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]\
    );
\app_rd_data[364]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(41),
      I1 => my_empty_0(4),
      I2 => mem_out(53),
      O => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]\
    );
\app_rd_data[365]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(49),
      I1 => my_empty_0(4),
      I2 => mem_out(61),
      O => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]\
    );
\app_rd_data[366]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(57),
      I1 => my_empty_0(4),
      I2 => mem_out(69),
      O => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]\
    );
\app_rd_data[367]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(65),
      I1 => my_empty_0(4),
      I2 => mem_out(77),
      O => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]\
    );
\app_rd_data[40]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(4),
      I1 => \my_empty_inst_rep__0_n_0\,
      I2 => mem_out(16),
      O => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]\
    );
\app_rd_data[41]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(12),
      I1 => \my_empty_inst_rep__0_n_0\,
      I2 => mem_out(24),
      O => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]\
    );
\app_rd_data[424]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(10),
      I1 => \my_empty_inst_rep__0_n_0\,
      I2 => mem_out(22),
      O => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]\
    );
\app_rd_data[425]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(18),
      I1 => \my_empty_inst_rep__0_n_0\,
      I2 => mem_out(30),
      O => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]\
    );
\app_rd_data[426]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(26),
      I1 => \my_empty_inst_rep__0_n_0\,
      I2 => mem_out(38),
      O => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]\
    );
\app_rd_data[427]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(34),
      I1 => \my_empty_inst_rep__0_n_0\,
      I2 => mem_out(46),
      O => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]\
    );
\app_rd_data[428]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(42),
      I1 => my_empty_0(4),
      I2 => mem_out(54),
      O => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]\
    );
\app_rd_data[429]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(50),
      I1 => my_empty_0(4),
      I2 => mem_out(62),
      O => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]\
    );
\app_rd_data[42]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(20),
      I1 => \my_empty_inst_rep__0_n_0\,
      I2 => mem_out(32),
      O => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]\
    );
\app_rd_data[430]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(58),
      I1 => my_empty_0(4),
      I2 => mem_out(70),
      O => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]\
    );
\app_rd_data[431]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(66),
      I1 => my_empty_0(4),
      I2 => mem_out(78),
      O => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]\
    );
\app_rd_data[43]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(28),
      I1 => \my_empty_inst_rep__0_n_0\,
      I2 => mem_out(40),
      O => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]\
    );
\app_rd_data[44]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(36),
      I1 => my_empty_0(4),
      I2 => mem_out(48),
      O => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]\
    );
\app_rd_data[45]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(44),
      I1 => my_empty_0(4),
      I2 => mem_out(56),
      O => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]\
    );
\app_rd_data[46]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(52),
      I1 => my_empty_0(4),
      I2 => mem_out(64),
      O => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]\
    );
\app_rd_data[47]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(60),
      I1 => my_empty_0(4),
      I2 => mem_out(72),
      O => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]\
    );
\app_rd_data[488]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(11),
      I1 => \my_empty_inst_rep__0_n_0\,
      I2 => mem_out(23),
      O => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]\
    );
\app_rd_data[489]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(19),
      I1 => \my_empty_inst_rep__0_n_0\,
      I2 => mem_out(31),
      O => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]\
    );
\app_rd_data[490]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(27),
      I1 => \my_empty_inst_rep__0_n_0\,
      I2 => mem_out(39),
      O => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]\
    );
\app_rd_data[491]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(35),
      I1 => \my_empty_inst_rep__0_n_0\,
      I2 => mem_out(47),
      O => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]\
    );
\app_rd_data[492]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(43),
      I1 => my_empty_0(4),
      I2 => mem_out(55),
      O => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]\
    );
\app_rd_data[493]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(51),
      I1 => my_empty_0(4),
      I2 => mem_out(63),
      O => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]\
    );
\app_rd_data[494]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(59),
      I1 => my_empty_0(4),
      I2 => mem_out(71),
      O => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]\
    );
\app_rd_data[495]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(67),
      I1 => my_empty_0(4),
      I2 => mem_out(79),
      O => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]\
    );
\gen_mux_rd[0].mux_rd_fall0_r[0]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FDB97531ECA86420"
    )
        port map (
      I0 => \gen_mux_rd[0].mux_rd_rise0_r_reg[0]\(0),
      I1 => \gen_mux_rd[0].mux_rd_rise0_r_reg[0]\(1),
      I2 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]\,
      I3 => \gen_mux_rd[0].mux_rd_fall0_r_reg[0]\,
      I4 => \gen_mux_rd[0].mux_rd_fall0_r_reg[0]_0\,
      I5 => \gen_mux_rd[0].mux_rd_fall0_r_reg[0]_1\,
      O => \gen_mux_rd[0].mux_rd_fall0_r[0]_i_2_n_0\
    );
\gen_mux_rd[0].mux_rd_fall0_r_reg[0]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gen_mux_rd[0].mux_rd_fall0_r[0]_i_2_n_0\,
      I1 => \gen_mux_rd[0].mux_rd_fall0_r_reg[0]_2\,
      O => \rd_mux_sel_r_reg[2]_50\,
      S => \gen_mux_rd[1].mux_rd_rise0_r_reg[1]_2\
    );
\gen_mux_rd[0].mux_rd_fall1_r[0]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FDB97531ECA86420"
    )
        port map (
      I0 => \gen_mux_rd[0].mux_rd_rise0_r_reg[0]\(0),
      I1 => \gen_mux_rd[0].mux_rd_rise0_r_reg[0]\(1),
      I2 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]\,
      I3 => \gen_mux_rd[0].mux_rd_fall1_r_reg[0]\,
      I4 => \gen_mux_rd[0].mux_rd_fall1_r_reg[0]_0\,
      I5 => \gen_mux_rd[0].mux_rd_fall1_r_reg[0]_1\,
      O => \gen_mux_rd[0].mux_rd_fall1_r[0]_i_2_n_0\
    );
\gen_mux_rd[0].mux_rd_fall1_r_reg[0]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gen_mux_rd[0].mux_rd_fall1_r[0]_i_2_n_0\,
      I1 => \gen_mux_rd[0].mux_rd_fall1_r_reg[0]_2\,
      O => \rd_mux_sel_r_reg[2]_55\,
      S => \gen_mux_rd[1].mux_rd_rise0_r_reg[1]_2\
    );
\gen_mux_rd[0].mux_rd_fall2_r[0]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FDB97531ECA86420"
    )
        port map (
      I0 => \gen_mux_rd[0].mux_rd_rise0_r_reg[0]\(0),
      I1 => \gen_mux_rd[0].mux_rd_rise0_r_reg[0]\(1),
      I2 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]\,
      I3 => \gen_mux_rd[0].mux_rd_fall2_r_reg[0]\,
      I4 => \gen_mux_rd[0].mux_rd_fall2_r_reg[0]_0\,
      I5 => \gen_mux_rd[0].mux_rd_fall2_r_reg[0]_1\,
      O => \gen_mux_rd[0].mux_rd_fall2_r[0]_i_2_n_0\
    );
\gen_mux_rd[0].mux_rd_fall2_r_reg[0]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gen_mux_rd[0].mux_rd_fall2_r[0]_i_2_n_0\,
      I1 => \gen_mux_rd[0].mux_rd_fall2_r_reg[0]_2\,
      O => \rd_mux_sel_r_reg[2]_59\,
      S => \gen_mux_rd[1].mux_rd_rise0_r_reg[1]_2\
    );
\gen_mux_rd[0].mux_rd_fall3_r[0]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FDB97531ECA86420"
    )
        port map (
      I0 => \gen_mux_rd[0].mux_rd_rise0_r_reg[0]\(0),
      I1 => \gen_mux_rd[0].mux_rd_rise0_r_reg[0]\(1),
      I2 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]\,
      I3 => \gen_mux_rd[0].mux_rd_fall3_r_reg[0]\,
      I4 => \gen_mux_rd[0].mux_rd_fall3_r_reg[0]_0\,
      I5 => \gen_mux_rd[0].mux_rd_fall3_r_reg[0]_1\,
      O => \gen_mux_rd[0].mux_rd_fall3_r[0]_i_2_n_0\
    );
\gen_mux_rd[0].mux_rd_fall3_r_reg[0]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gen_mux_rd[0].mux_rd_fall3_r[0]_i_2_n_0\,
      I1 => \gen_mux_rd[0].mux_rd_fall3_r_reg[0]_2\,
      O => \rd_mux_sel_r_reg[2]_40\,
      S => \gen_mux_rd[1].mux_rd_rise0_r_reg[1]_2\
    );
\gen_mux_rd[0].mux_rd_rise0_r[0]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FDB97531ECA86420"
    )
        port map (
      I0 => \gen_mux_rd[0].mux_rd_rise0_r_reg[0]\(0),
      I1 => \gen_mux_rd[0].mux_rd_rise0_r_reg[0]\(1),
      I2 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]\,
      I3 => \gen_mux_rd[0].mux_rd_rise0_r_reg[0]_0\,
      I4 => \gen_mux_rd[0].mux_rd_rise0_r_reg[0]_1\,
      I5 => \gen_mux_rd[0].mux_rd_rise0_r_reg[0]_2\,
      O => \gen_mux_rd[0].mux_rd_rise0_r[0]_i_3_n_0\
    );
\gen_mux_rd[0].mux_rd_rise0_r_reg[0]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gen_mux_rd[0].mux_rd_rise0_r[0]_i_3_n_0\,
      I1 => \gen_mux_rd[0].mux_rd_rise0_r_reg[0]_3\,
      O => \rd_mux_sel_r_reg[2]_48\,
      S => \gen_mux_rd[1].mux_rd_rise0_r_reg[1]_2\
    );
\gen_mux_rd[0].mux_rd_rise1_r[0]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FDB97531ECA86420"
    )
        port map (
      I0 => \gen_mux_rd[0].mux_rd_rise0_r_reg[0]\(0),
      I1 => \gen_mux_rd[0].mux_rd_rise0_r_reg[0]\(1),
      I2 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]\,
      I3 => \gen_mux_rd[0].mux_rd_rise1_r_reg[0]\,
      I4 => \gen_mux_rd[0].mux_rd_rise1_r_reg[0]_0\,
      I5 => \gen_mux_rd[0].mux_rd_rise1_r_reg[0]_1\,
      O => \gen_mux_rd[0].mux_rd_rise1_r[0]_i_2_n_0\
    );
\gen_mux_rd[0].mux_rd_rise1_r_reg[0]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gen_mux_rd[0].mux_rd_rise1_r[0]_i_2_n_0\,
      I1 => \gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2\,
      O => \rd_mux_sel_r_reg[2]_10\,
      S => \gen_mux_rd[1].mux_rd_rise0_r_reg[1]_2\
    );
\gen_mux_rd[0].mux_rd_rise2_r[0]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FDB97531ECA86420"
    )
        port map (
      I0 => \gen_mux_rd[0].mux_rd_rise0_r_reg[0]\(0),
      I1 => \gen_mux_rd[0].mux_rd_rise0_r_reg[0]\(1),
      I2 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]\,
      I3 => \gen_mux_rd[0].mux_rd_rise2_r_reg[0]\,
      I4 => \gen_mux_rd[0].mux_rd_rise2_r_reg[0]_0\,
      I5 => \gen_mux_rd[0].mux_rd_rise2_r_reg[0]_1\,
      O => \gen_mux_rd[0].mux_rd_rise2_r[0]_i_2_n_0\
    );
\gen_mux_rd[0].mux_rd_rise2_r_reg[0]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gen_mux_rd[0].mux_rd_rise2_r[0]_i_2_n_0\,
      I1 => \gen_mux_rd[0].mux_rd_rise2_r_reg[0]_2\,
      O => \rd_mux_sel_r_reg[2]_21\,
      S => \gen_mux_rd[1].mux_rd_rise0_r_reg[1]_2\
    );
\gen_mux_rd[0].mux_rd_rise3_r[0]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FDB97531ECA86420"
    )
        port map (
      I0 => \gen_mux_rd[0].mux_rd_rise0_r_reg[0]\(0),
      I1 => \gen_mux_rd[0].mux_rd_rise0_r_reg[0]\(1),
      I2 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]\,
      I3 => \gen_mux_rd[0].mux_rd_rise3_r_reg[0]\,
      I4 => \gen_mux_rd[0].mux_rd_rise3_r_reg[0]_0\,
      I5 => \gen_mux_rd[0].mux_rd_rise3_r_reg[0]_1\,
      O => \gen_mux_rd[0].mux_rd_rise3_r[0]_i_2_n_0\
    );
\gen_mux_rd[0].mux_rd_rise3_r_reg[0]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gen_mux_rd[0].mux_rd_rise3_r[0]_i_2_n_0\,
      I1 => \gen_mux_rd[0].mux_rd_rise3_r_reg[0]_2\,
      O => \rd_mux_sel_r_reg[2]_61\,
      S => \gen_mux_rd[1].mux_rd_rise0_r_reg[1]_2\
    );
\gen_mux_rd[1].mux_rd_fall0_r[1]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FDB97531ECA86420"
    )
        port map (
      I0 => \gen_mux_rd[0].mux_rd_rise0_r_reg[0]\(0),
      I1 => \gen_mux_rd[0].mux_rd_rise0_r_reg[0]\(1),
      I2 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]\,
      I3 => \gen_mux_rd[1].mux_rd_fall0_r_reg[1]\,
      I4 => \gen_mux_rd[1].mux_rd_fall0_r_reg[1]_0\,
      I5 => \gen_mux_rd[1].mux_rd_fall0_r_reg[1]_1\,
      O => \gen_mux_rd[1].mux_rd_fall0_r[1]_i_2_n_0\
    );
\gen_mux_rd[1].mux_rd_fall0_r_reg[1]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gen_mux_rd[1].mux_rd_fall0_r[1]_i_2_n_0\,
      I1 => \gen_mux_rd[1].mux_rd_fall0_r_reg[1]_2\,
      O => \rd_mux_sel_r_reg[2]_5\,
      S => \gen_mux_rd[1].mux_rd_rise0_r_reg[1]_2\
    );
\gen_mux_rd[1].mux_rd_fall1_r[1]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FDB97531ECA86420"
    )
        port map (
      I0 => \gen_mux_rd[0].mux_rd_rise0_r_reg[0]\(0),
      I1 => \gen_mux_rd[0].mux_rd_rise0_r_reg[0]\(1),
      I2 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]\,
      I3 => \gen_mux_rd[1].mux_rd_fall1_r_reg[1]\,
      I4 => \gen_mux_rd[1].mux_rd_fall1_r_reg[1]_0\,
      I5 => \gen_mux_rd[1].mux_rd_fall1_r_reg[1]_1\,
      O => \gen_mux_rd[1].mux_rd_fall1_r[1]_i_2_n_0\
    );
\gen_mux_rd[1].mux_rd_fall1_r_reg[1]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gen_mux_rd[1].mux_rd_fall1_r[1]_i_2_n_0\,
      I1 => \gen_mux_rd[1].mux_rd_fall1_r_reg[1]_2\,
      O => \rd_mux_sel_r_reg[2]_16\,
      S => \gen_mux_rd[1].mux_rd_rise0_r_reg[1]_2\
    );
\gen_mux_rd[1].mux_rd_fall2_r[1]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FDB97531ECA86420"
    )
        port map (
      I0 => \gen_mux_rd[0].mux_rd_rise0_r_reg[0]\(0),
      I1 => \gen_mux_rd[0].mux_rd_rise0_r_reg[0]\(1),
      I2 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]\,
      I3 => \gen_mux_rd[1].mux_rd_fall2_r_reg[1]\,
      I4 => \gen_mux_rd[1].mux_rd_fall2_r_reg[1]_0\,
      I5 => \gen_mux_rd[1].mux_rd_fall2_r_reg[1]_1\,
      O => \gen_mux_rd[1].mux_rd_fall2_r[1]_i_2_n_0\
    );
\gen_mux_rd[1].mux_rd_fall2_r_reg[1]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gen_mux_rd[1].mux_rd_fall2_r[1]_i_2_n_0\,
      I1 => \gen_mux_rd[1].mux_rd_fall2_r_reg[1]_2\,
      O => \rd_mux_sel_r_reg[2]_28\,
      S => \gen_mux_rd[1].mux_rd_rise0_r_reg[1]_2\
    );
\gen_mux_rd[1].mux_rd_fall3_r[1]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FDB97531ECA86420"
    )
        port map (
      I0 => \gen_mux_rd[0].mux_rd_rise0_r_reg[0]\(0),
      I1 => \gen_mux_rd[0].mux_rd_rise0_r_reg[0]\(1),
      I2 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]\,
      I3 => \gen_mux_rd[1].mux_rd_fall3_r_reg[1]\,
      I4 => \gen_mux_rd[1].mux_rd_fall3_r_reg[1]_0\,
      I5 => \gen_mux_rd[1].mux_rd_fall3_r_reg[1]_1\,
      O => \gen_mux_rd[1].mux_rd_fall3_r[1]_i_2_n_0\
    );
\gen_mux_rd[1].mux_rd_fall3_r_reg[1]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gen_mux_rd[1].mux_rd_fall3_r[1]_i_2_n_0\,
      I1 => \gen_mux_rd[1].mux_rd_fall3_r_reg[1]_2\,
      O => \rd_mux_sel_r_reg[2]_41\,
      S => \gen_mux_rd[1].mux_rd_rise0_r_reg[1]_2\
    );
\gen_mux_rd[1].mux_rd_rise0_r[1]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FDB97531ECA86420"
    )
        port map (
      I0 => \gen_mux_rd[0].mux_rd_rise0_r_reg[0]\(0),
      I1 => \gen_mux_rd[0].mux_rd_rise0_r_reg[0]\(1),
      I2 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]\,
      I3 => \gen_mux_rd[1].mux_rd_rise0_r_reg[1]\,
      I4 => \gen_mux_rd[1].mux_rd_rise0_r_reg[1]_0\,
      I5 => \gen_mux_rd[1].mux_rd_rise0_r_reg[1]_1\,
      O => \gen_mux_rd[1].mux_rd_rise0_r[1]_i_2_n_0\
    );
\gen_mux_rd[1].mux_rd_rise0_r_reg[1]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gen_mux_rd[1].mux_rd_rise0_r[1]_i_2_n_0\,
      I1 => \gen_mux_rd[1].mux_rd_rise0_r_reg[1]_3\,
      O => \rd_mux_sel_r_reg[2]\,
      S => \gen_mux_rd[1].mux_rd_rise0_r_reg[1]_2\
    );
\gen_mux_rd[1].mux_rd_rise1_r[1]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FDB97531ECA86420"
    )
        port map (
      I0 => \gen_mux_rd[0].mux_rd_rise0_r_reg[0]\(0),
      I1 => \gen_mux_rd[0].mux_rd_rise0_r_reg[0]\(1),
      I2 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]\,
      I3 => \gen_mux_rd[1].mux_rd_rise1_r_reg[1]\,
      I4 => \gen_mux_rd[1].mux_rd_rise1_r_reg[1]_0\,
      I5 => \gen_mux_rd[1].mux_rd_rise1_r_reg[1]_1\,
      O => \gen_mux_rd[1].mux_rd_rise1_r[1]_i_2_n_0\
    );
\gen_mux_rd[1].mux_rd_rise1_r_reg[1]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gen_mux_rd[1].mux_rd_rise1_r[1]_i_2_n_0\,
      I1 => \gen_mux_rd[1].mux_rd_rise1_r_reg[1]_2\,
      O => \rd_mux_sel_r_reg[2]_11\,
      S => \gen_mux_rd[1].mux_rd_rise0_r_reg[1]_2\
    );
\gen_mux_rd[1].mux_rd_rise2_r[1]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FDB97531ECA86420"
    )
        port map (
      I0 => \gen_mux_rd[0].mux_rd_rise0_r_reg[0]\(0),
      I1 => \gen_mux_rd[0].mux_rd_rise0_r_reg[0]\(1),
      I2 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]\,
      I3 => \gen_mux_rd[1].mux_rd_rise2_r_reg[1]\,
      I4 => \gen_mux_rd[1].mux_rd_rise2_r_reg[1]_0\,
      I5 => \gen_mux_rd[1].mux_rd_rise2_r_reg[1]_1\,
      O => \gen_mux_rd[1].mux_rd_rise2_r[1]_i_2_n_0\
    );
\gen_mux_rd[1].mux_rd_rise2_r_reg[1]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gen_mux_rd[1].mux_rd_rise2_r[1]_i_2_n_0\,
      I1 => \gen_mux_rd[1].mux_rd_rise2_r_reg[1]_2\,
      O => \rd_mux_sel_r_reg[2]_22\,
      S => \gen_mux_rd[1].mux_rd_rise0_r_reg[1]_2\
    );
\gen_mux_rd[1].mux_rd_rise3_r[1]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FDB97531ECA86420"
    )
        port map (
      I0 => \gen_mux_rd[0].mux_rd_rise0_r_reg[0]\(0),
      I1 => \gen_mux_rd[0].mux_rd_rise0_r_reg[0]\(1),
      I2 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]\,
      I3 => \gen_mux_rd[1].mux_rd_rise3_r_reg[1]\,
      I4 => \gen_mux_rd[1].mux_rd_rise3_r_reg[1]_0\,
      I5 => \gen_mux_rd[1].mux_rd_rise3_r_reg[1]_1\,
      O => \gen_mux_rd[1].mux_rd_rise3_r[1]_i_2_n_0\
    );
\gen_mux_rd[1].mux_rd_rise3_r_reg[1]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gen_mux_rd[1].mux_rd_rise3_r[1]_i_2_n_0\,
      I1 => \gen_mux_rd[1].mux_rd_rise3_r_reg[1]_2\,
      O => \rd_mux_sel_r_reg[2]_34\,
      S => \gen_mux_rd[1].mux_rd_rise0_r_reg[1]_2\
    );
\gen_mux_rd[2].mux_rd_fall0_r[2]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FDB97531ECA86420"
    )
        port map (
      I0 => \gen_mux_rd[0].mux_rd_rise0_r_reg[0]\(0),
      I1 => \gen_mux_rd[0].mux_rd_rise0_r_reg[0]\(1),
      I2 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]\,
      I3 => \gen_mux_rd[2].mux_rd_fall0_r_reg[2]\,
      I4 => \gen_mux_rd[2].mux_rd_fall0_r_reg[2]_0\,
      I5 => \gen_mux_rd[2].mux_rd_fall0_r_reg[2]_1\,
      O => \gen_mux_rd[2].mux_rd_fall0_r[2]_i_2_n_0\
    );
\gen_mux_rd[2].mux_rd_fall0_r_reg[2]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gen_mux_rd[2].mux_rd_fall0_r[2]_i_2_n_0\,
      I1 => \gen_mux_rd[2].mux_rd_fall0_r_reg[2]_2\,
      O => \rd_mux_sel_r_reg[2]_51\,
      S => \gen_mux_rd[1].mux_rd_rise0_r_reg[1]_2\
    );
\gen_mux_rd[2].mux_rd_fall1_r[2]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FDB97531ECA86420"
    )
        port map (
      I0 => \gen_mux_rd[0].mux_rd_rise0_r_reg[0]\(0),
      I1 => \gen_mux_rd[0].mux_rd_rise0_r_reg[0]\(1),
      I2 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]\,
      I3 => \gen_mux_rd[2].mux_rd_fall1_r_reg[2]\,
      I4 => \gen_mux_rd[2].mux_rd_fall1_r_reg[2]_0\,
      I5 => \gen_mux_rd[2].mux_rd_fall1_r_reg[2]_1\,
      O => \gen_mux_rd[2].mux_rd_fall1_r[2]_i_2_n_0\
    );
\gen_mux_rd[2].mux_rd_fall1_r_reg[2]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gen_mux_rd[2].mux_rd_fall1_r[2]_i_2_n_0\,
      I1 => \gen_mux_rd[2].mux_rd_fall1_r_reg[2]_2\,
      O => \rd_mux_sel_r_reg[2]_56\,
      S => \gen_mux_rd[1].mux_rd_rise0_r_reg[1]_2\
    );
\gen_mux_rd[2].mux_rd_fall2_r[2]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FDB97531ECA86420"
    )
        port map (
      I0 => \gen_mux_rd[0].mux_rd_rise0_r_reg[0]\(0),
      I1 => \gen_mux_rd[0].mux_rd_rise0_r_reg[0]\(1),
      I2 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]\,
      I3 => \gen_mux_rd[2].mux_rd_fall2_r_reg[2]\,
      I4 => \gen_mux_rd[2].mux_rd_fall2_r_reg[2]_0\,
      I5 => \gen_mux_rd[2].mux_rd_fall2_r_reg[2]_1\,
      O => \gen_mux_rd[2].mux_rd_fall2_r[2]_i_2_n_0\
    );
\gen_mux_rd[2].mux_rd_fall2_r_reg[2]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gen_mux_rd[2].mux_rd_fall2_r[2]_i_2_n_0\,
      I1 => \gen_mux_rd[2].mux_rd_fall2_r_reg[2]_2\,
      O => \rd_mux_sel_r_reg[2]_29\,
      S => \gen_mux_rd[1].mux_rd_rise0_r_reg[1]_2\
    );
\gen_mux_rd[2].mux_rd_fall3_r[2]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FDB97531ECA86420"
    )
        port map (
      I0 => \gen_mux_rd[0].mux_rd_rise0_r_reg[0]\(0),
      I1 => \gen_mux_rd[0].mux_rd_rise0_r_reg[0]\(1),
      I2 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]\,
      I3 => \gen_mux_rd[2].mux_rd_fall3_r_reg[2]\,
      I4 => \gen_mux_rd[2].mux_rd_fall3_r_reg[2]_0\,
      I5 => \gen_mux_rd[2].mux_rd_fall3_r_reg[2]_1\,
      O => \gen_mux_rd[2].mux_rd_fall3_r[2]_i_2_n_0\
    );
\gen_mux_rd[2].mux_rd_fall3_r_reg[2]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gen_mux_rd[2].mux_rd_fall3_r[2]_i_2_n_0\,
      I1 => \gen_mux_rd[2].mux_rd_fall3_r_reg[2]_2\,
      O => \rd_mux_sel_r_reg[2]_42\,
      S => \gen_mux_rd[1].mux_rd_rise0_r_reg[1]_2\
    );
\gen_mux_rd[2].mux_rd_rise0_r[2]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FDB97531ECA86420"
    )
        port map (
      I0 => \gen_mux_rd[0].mux_rd_rise0_r_reg[0]\(0),
      I1 => \gen_mux_rd[0].mux_rd_rise0_r_reg[0]\(1),
      I2 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]\,
      I3 => \gen_mux_rd[2].mux_rd_rise0_r_reg[2]\,
      I4 => \gen_mux_rd[2].mux_rd_rise0_r_reg[2]_0\,
      I5 => \gen_mux_rd[2].mux_rd_rise0_r_reg[2]_1\,
      O => \gen_mux_rd[2].mux_rd_rise0_r[2]_i_2_n_0\
    );
\gen_mux_rd[2].mux_rd_rise0_r_reg[2]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gen_mux_rd[2].mux_rd_rise0_r[2]_i_2_n_0\,
      I1 => \gen_mux_rd[2].mux_rd_rise0_r_reg[2]_2\,
      O => \rd_mux_sel_r_reg[2]_0\,
      S => \gen_mux_rd[1].mux_rd_rise0_r_reg[1]_2\
    );
\gen_mux_rd[2].mux_rd_rise1_r[2]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FDB97531ECA86420"
    )
        port map (
      I0 => \gen_mux_rd[0].mux_rd_rise0_r_reg[0]\(0),
      I1 => \gen_mux_rd[0].mux_rd_rise0_r_reg[0]\(1),
      I2 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]\,
      I3 => \gen_mux_rd[2].mux_rd_rise1_r_reg[2]\,
      I4 => \gen_mux_rd[2].mux_rd_rise1_r_reg[2]_0\,
      I5 => \gen_mux_rd[2].mux_rd_rise1_r_reg[2]_1\,
      O => \gen_mux_rd[2].mux_rd_rise1_r[2]_i_2_n_0\
    );
\gen_mux_rd[2].mux_rd_rise1_r_reg[2]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gen_mux_rd[2].mux_rd_rise1_r[2]_i_2_n_0\,
      I1 => \gen_mux_rd[2].mux_rd_rise1_r_reg[2]_2\,
      O => \rd_mux_sel_r_reg[2]_53\,
      S => \gen_mux_rd[1].mux_rd_rise0_r_reg[1]_2\
    );
\gen_mux_rd[2].mux_rd_rise2_r[2]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FDB97531ECA86420"
    )
        port map (
      I0 => \gen_mux_rd[0].mux_rd_rise0_r_reg[0]\(0),
      I1 => \gen_mux_rd[0].mux_rd_rise0_r_reg[0]\(1),
      I2 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]\,
      I3 => \gen_mux_rd[2].mux_rd_rise2_r_reg[2]\,
      I4 => \gen_mux_rd[2].mux_rd_rise2_r_reg[2]_0\,
      I5 => \gen_mux_rd[2].mux_rd_rise2_r_reg[2]_1\,
      O => \gen_mux_rd[2].mux_rd_rise2_r[2]_i_2_n_0\
    );
\gen_mux_rd[2].mux_rd_rise2_r_reg[2]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gen_mux_rd[2].mux_rd_rise2_r[2]_i_2_n_0\,
      I1 => \gen_mux_rd[2].mux_rd_rise2_r_reg[2]_2\,
      O => \rd_mux_sel_r_reg[2]_23\,
      S => \gen_mux_rd[1].mux_rd_rise0_r_reg[1]_2\
    );
\gen_mux_rd[2].mux_rd_rise3_r[2]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FDB97531ECA86420"
    )
        port map (
      I0 => \gen_mux_rd[0].mux_rd_rise0_r_reg[0]\(0),
      I1 => \gen_mux_rd[0].mux_rd_rise0_r_reg[0]\(1),
      I2 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]\,
      I3 => \gen_mux_rd[2].mux_rd_rise3_r_reg[2]\,
      I4 => \gen_mux_rd[2].mux_rd_rise3_r_reg[2]_0\,
      I5 => \gen_mux_rd[2].mux_rd_rise3_r_reg[2]_1\,
      O => \gen_mux_rd[2].mux_rd_rise3_r[2]_i_2_n_0\
    );
\gen_mux_rd[2].mux_rd_rise3_r_reg[2]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gen_mux_rd[2].mux_rd_rise3_r[2]_i_2_n_0\,
      I1 => \gen_mux_rd[2].mux_rd_rise3_r_reg[2]_2\,
      O => \rd_mux_sel_r_reg[2]_35\,
      S => \gen_mux_rd[1].mux_rd_rise0_r_reg[1]_2\
    );
\gen_mux_rd[3].mux_rd_fall0_r[3]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FDB97531ECA86420"
    )
        port map (
      I0 => \gen_mux_rd[0].mux_rd_rise0_r_reg[0]\(0),
      I1 => \gen_mux_rd[0].mux_rd_rise0_r_reg[0]\(1),
      I2 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]\,
      I3 => \gen_mux_rd[3].mux_rd_fall0_r_reg[3]\,
      I4 => \gen_mux_rd[3].mux_rd_fall0_r_reg[3]_0\,
      I5 => \gen_mux_rd[3].mux_rd_fall0_r_reg[3]_1\,
      O => \gen_mux_rd[3].mux_rd_fall0_r[3]_i_2_n_0\
    );
\gen_mux_rd[3].mux_rd_fall0_r_reg[3]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gen_mux_rd[3].mux_rd_fall0_r[3]_i_2_n_0\,
      I1 => \gen_mux_rd[3].mux_rd_fall0_r_reg[3]_2\,
      O => \rd_mux_sel_r_reg[2]_6\,
      S => \gen_mux_rd[1].mux_rd_rise0_r_reg[1]_2\
    );
\gen_mux_rd[3].mux_rd_fall1_r[3]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FDB97531ECA86420"
    )
        port map (
      I0 => \gen_mux_rd[0].mux_rd_rise0_r_reg[0]\(0),
      I1 => \gen_mux_rd[0].mux_rd_rise0_r_reg[0]\(1),
      I2 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]\,
      I3 => \gen_mux_rd[3].mux_rd_fall1_r_reg[3]\,
      I4 => \gen_mux_rd[3].mux_rd_fall1_r_reg[3]_0\,
      I5 => \gen_mux_rd[3].mux_rd_fall1_r_reg[3]_1\,
      O => \gen_mux_rd[3].mux_rd_fall1_r[3]_i_2_n_0\
    );
\gen_mux_rd[3].mux_rd_fall1_r_reg[3]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gen_mux_rd[3].mux_rd_fall1_r[3]_i_2_n_0\,
      I1 => \gen_mux_rd[3].mux_rd_fall1_r_reg[3]_2\,
      O => \rd_mux_sel_r_reg[2]_17\,
      S => \gen_mux_rd[1].mux_rd_rise0_r_reg[1]_2\
    );
\gen_mux_rd[3].mux_rd_fall2_r[3]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FDB97531ECA86420"
    )
        port map (
      I0 => \gen_mux_rd[0].mux_rd_rise0_r_reg[0]\(0),
      I1 => \gen_mux_rd[0].mux_rd_rise0_r_reg[0]\(1),
      I2 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]\,
      I3 => \gen_mux_rd[3].mux_rd_fall2_r_reg[3]\,
      I4 => \gen_mux_rd[3].mux_rd_fall2_r_reg[3]_0\,
      I5 => \gen_mux_rd[3].mux_rd_fall2_r_reg[3]_1\,
      O => \gen_mux_rd[3].mux_rd_fall2_r[3]_i_2_n_0\
    );
\gen_mux_rd[3].mux_rd_fall2_r_reg[3]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gen_mux_rd[3].mux_rd_fall2_r[3]_i_2_n_0\,
      I1 => \gen_mux_rd[3].mux_rd_fall2_r_reg[3]_2\,
      O => \rd_mux_sel_r_reg[2]_30\,
      S => \gen_mux_rd[1].mux_rd_rise0_r_reg[1]_2\
    );
\gen_mux_rd[3].mux_rd_fall3_r[3]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FDB97531ECA86420"
    )
        port map (
      I0 => \gen_mux_rd[0].mux_rd_rise0_r_reg[0]\(0),
      I1 => \gen_mux_rd[0].mux_rd_rise0_r_reg[0]\(1),
      I2 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]\,
      I3 => \gen_mux_rd[3].mux_rd_fall3_r_reg[3]\,
      I4 => \gen_mux_rd[3].mux_rd_fall3_r_reg[3]_0\,
      I5 => \gen_mux_rd[3].mux_rd_fall3_r_reg[3]_1\,
      O => \gen_mux_rd[3].mux_rd_fall3_r[3]_i_2_n_0\
    );
\gen_mux_rd[3].mux_rd_fall3_r_reg[3]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gen_mux_rd[3].mux_rd_fall3_r[3]_i_2_n_0\,
      I1 => \gen_mux_rd[3].mux_rd_fall3_r_reg[3]_2\,
      O => \rd_mux_sel_r_reg[2]_43\,
      S => \gen_mux_rd[1].mux_rd_rise0_r_reg[1]_2\
    );
\gen_mux_rd[3].mux_rd_rise0_r[3]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FDB97531ECA86420"
    )
        port map (
      I0 => \gen_mux_rd[0].mux_rd_rise0_r_reg[0]\(0),
      I1 => \gen_mux_rd[0].mux_rd_rise0_r_reg[0]\(1),
      I2 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]\,
      I3 => \gen_mux_rd[3].mux_rd_rise0_r_reg[3]\,
      I4 => \gen_mux_rd[3].mux_rd_rise0_r_reg[3]_0\,
      I5 => \gen_mux_rd[3].mux_rd_rise0_r_reg[3]_1\,
      O => \gen_mux_rd[3].mux_rd_rise0_r[3]_i_2_n_0\
    );
\gen_mux_rd[3].mux_rd_rise0_r_reg[3]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gen_mux_rd[3].mux_rd_rise0_r[3]_i_2_n_0\,
      I1 => \gen_mux_rd[3].mux_rd_rise0_r_reg[3]_2\,
      O => \rd_mux_sel_r_reg[2]_1\,
      S => \gen_mux_rd[1].mux_rd_rise0_r_reg[1]_2\
    );
\gen_mux_rd[3].mux_rd_rise1_r[3]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FDB97531ECA86420"
    )
        port map (
      I0 => \gen_mux_rd[0].mux_rd_rise0_r_reg[0]\(0),
      I1 => \gen_mux_rd[0].mux_rd_rise0_r_reg[0]\(1),
      I2 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]\,
      I3 => \gen_mux_rd[3].mux_rd_rise1_r_reg[3]\,
      I4 => \gen_mux_rd[3].mux_rd_rise1_r_reg[3]_0\,
      I5 => \gen_mux_rd[3].mux_rd_rise1_r_reg[3]_1\,
      O => \gen_mux_rd[3].mux_rd_rise1_r[3]_i_2_n_0\
    );
\gen_mux_rd[3].mux_rd_rise1_r_reg[3]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gen_mux_rd[3].mux_rd_rise1_r[3]_i_2_n_0\,
      I1 => \gen_mux_rd[3].mux_rd_rise1_r_reg[3]_2\,
      O => \rd_mux_sel_r_reg[2]_12\,
      S => \gen_mux_rd[1].mux_rd_rise0_r_reg[1]_2\
    );
\gen_mux_rd[3].mux_rd_rise2_r[3]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FDB97531ECA86420"
    )
        port map (
      I0 => \gen_mux_rd[0].mux_rd_rise0_r_reg[0]\(0),
      I1 => \gen_mux_rd[0].mux_rd_rise0_r_reg[0]\(1),
      I2 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]\,
      I3 => \gen_mux_rd[3].mux_rd_rise2_r_reg[3]\,
      I4 => \gen_mux_rd[3].mux_rd_rise2_r_reg[3]_0\,
      I5 => \gen_mux_rd[3].mux_rd_rise2_r_reg[3]_1\,
      O => \gen_mux_rd[3].mux_rd_rise2_r[3]_i_2_n_0\
    );
\gen_mux_rd[3].mux_rd_rise2_r_reg[3]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gen_mux_rd[3].mux_rd_rise2_r[3]_i_2_n_0\,
      I1 => \gen_mux_rd[3].mux_rd_rise2_r_reg[3]_2\,
      O => \rd_mux_sel_r_reg[2]_24\,
      S => \gen_mux_rd[1].mux_rd_rise0_r_reg[1]_2\
    );
\gen_mux_rd[3].mux_rd_rise3_r[3]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FDB97531ECA86420"
    )
        port map (
      I0 => \gen_mux_rd[0].mux_rd_rise0_r_reg[0]\(0),
      I1 => \gen_mux_rd[0].mux_rd_rise0_r_reg[0]\(1),
      I2 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]\,
      I3 => \gen_mux_rd[3].mux_rd_rise3_r_reg[3]\,
      I4 => \gen_mux_rd[3].mux_rd_rise3_r_reg[3]_0\,
      I5 => \gen_mux_rd[3].mux_rd_rise3_r_reg[3]_1\,
      O => \gen_mux_rd[3].mux_rd_rise3_r[3]_i_2_n_0\
    );
\gen_mux_rd[3].mux_rd_rise3_r_reg[3]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gen_mux_rd[3].mux_rd_rise3_r[3]_i_2_n_0\,
      I1 => \gen_mux_rd[3].mux_rd_rise3_r_reg[3]_2\,
      O => \rd_mux_sel_r_reg[2]_36\,
      S => \gen_mux_rd[1].mux_rd_rise0_r_reg[1]_2\
    );
\gen_mux_rd[4].mux_rd_fall0_r[4]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FDB97531ECA86420"
    )
        port map (
      I0 => \gen_mux_rd[0].mux_rd_rise0_r_reg[0]\(0),
      I1 => \gen_mux_rd[0].mux_rd_rise0_r_reg[0]\(1),
      I2 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]\,
      I3 => \gen_mux_rd[4].mux_rd_fall0_r_reg[4]\,
      I4 => \gen_mux_rd[4].mux_rd_fall0_r_reg[4]_0\,
      I5 => \gen_mux_rd[4].mux_rd_fall0_r_reg[4]_1\,
      O => \gen_mux_rd[4].mux_rd_fall0_r[4]_i_2_n_0\
    );
\gen_mux_rd[4].mux_rd_fall0_r_reg[4]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gen_mux_rd[4].mux_rd_fall0_r[4]_i_2_n_0\,
      I1 => \gen_mux_rd[4].mux_rd_fall0_r_reg[4]_2\,
      O => \rd_mux_sel_r_reg[2]_52\,
      S => \gen_mux_rd[1].mux_rd_rise0_r_reg[1]_2\
    );
\gen_mux_rd[4].mux_rd_fall1_r[4]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FDB97531ECA86420"
    )
        port map (
      I0 => \gen_mux_rd[0].mux_rd_rise0_r_reg[0]\(0),
      I1 => \gen_mux_rd[0].mux_rd_rise0_r_reg[0]\(1),
      I2 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]\,
      I3 => \gen_mux_rd[4].mux_rd_fall1_r_reg[4]\,
      I4 => \gen_mux_rd[4].mux_rd_fall1_r_reg[4]_0\,
      I5 => \gen_mux_rd[4].mux_rd_fall1_r_reg[4]_1\,
      O => \gen_mux_rd[4].mux_rd_fall1_r[4]_i_2_n_0\
    );
\gen_mux_rd[4].mux_rd_fall1_r_reg[4]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gen_mux_rd[4].mux_rd_fall1_r[4]_i_2_n_0\,
      I1 => \gen_mux_rd[4].mux_rd_fall1_r_reg[4]_2\,
      O => \rd_mux_sel_r_reg[2]_57\,
      S => \gen_mux_rd[1].mux_rd_rise0_r_reg[1]_2\
    );
\gen_mux_rd[4].mux_rd_fall2_r[4]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FDB97531ECA86420"
    )
        port map (
      I0 => \gen_mux_rd[0].mux_rd_rise0_r_reg[0]\(0),
      I1 => \gen_mux_rd[0].mux_rd_rise0_r_reg[0]\(1),
      I2 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]\,
      I3 => \gen_mux_rd[4].mux_rd_fall2_r_reg[4]\,
      I4 => \gen_mux_rd[4].mux_rd_fall2_r_reg[4]_0\,
      I5 => \gen_mux_rd[4].mux_rd_fall2_r_reg[4]_1\,
      O => \gen_mux_rd[4].mux_rd_fall2_r[4]_i_2_n_0\
    );
\gen_mux_rd[4].mux_rd_fall2_r_reg[4]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gen_mux_rd[4].mux_rd_fall2_r[4]_i_2_n_0\,
      I1 => \gen_mux_rd[4].mux_rd_fall2_r_reg[4]_2\,
      O => \rd_mux_sel_r_reg[2]_60\,
      S => \gen_mux_rd[1].mux_rd_rise0_r_reg[1]_2\
    );
\gen_mux_rd[4].mux_rd_fall3_r[4]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FDB97531ECA86420"
    )
        port map (
      I0 => \gen_mux_rd[0].mux_rd_rise0_r_reg[0]\(0),
      I1 => \gen_mux_rd[0].mux_rd_rise0_r_reg[0]\(1),
      I2 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]\,
      I3 => \gen_mux_rd[4].mux_rd_fall3_r_reg[4]\,
      I4 => \gen_mux_rd[4].mux_rd_fall3_r_reg[4]_0\,
      I5 => \gen_mux_rd[4].mux_rd_fall3_r_reg[4]_1\,
      O => \gen_mux_rd[4].mux_rd_fall3_r[4]_i_2_n_0\
    );
\gen_mux_rd[4].mux_rd_fall3_r_reg[4]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gen_mux_rd[4].mux_rd_fall3_r[4]_i_2_n_0\,
      I1 => \gen_mux_rd[4].mux_rd_fall3_r_reg[4]_2\,
      O => \rd_mux_sel_r_reg[2]_44\,
      S => \gen_mux_rd[1].mux_rd_rise0_r_reg[1]_2\
    );
\gen_mux_rd[4].mux_rd_rise0_r[4]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FDB97531ECA86420"
    )
        port map (
      I0 => \gen_mux_rd[0].mux_rd_rise0_r_reg[0]\(0),
      I1 => \gen_mux_rd[0].mux_rd_rise0_r_reg[0]\(1),
      I2 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]\,
      I3 => \gen_mux_rd[4].mux_rd_rise0_r_reg[4]\,
      I4 => \gen_mux_rd[4].mux_rd_rise0_r_reg[4]_0\,
      I5 => \gen_mux_rd[4].mux_rd_rise0_r_reg[4]_1\,
      O => \gen_mux_rd[4].mux_rd_rise0_r[4]_i_2_n_0\
    );
\gen_mux_rd[4].mux_rd_rise0_r_reg[4]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gen_mux_rd[4].mux_rd_rise0_r[4]_i_2_n_0\,
      I1 => \gen_mux_rd[4].mux_rd_rise0_r_reg[4]_2\,
      O => \rd_mux_sel_r_reg[2]_49\,
      S => \gen_mux_rd[1].mux_rd_rise0_r_reg[1]_2\
    );
\gen_mux_rd[4].mux_rd_rise1_r[4]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FDB97531ECA86420"
    )
        port map (
      I0 => \gen_mux_rd[0].mux_rd_rise0_r_reg[0]\(0),
      I1 => \gen_mux_rd[0].mux_rd_rise0_r_reg[0]\(1),
      I2 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]\,
      I3 => \gen_mux_rd[4].mux_rd_rise1_r_reg[4]\,
      I4 => \gen_mux_rd[4].mux_rd_rise1_r_reg[4]_0\,
      I5 => \gen_mux_rd[4].mux_rd_rise1_r_reg[4]_1\,
      O => \gen_mux_rd[4].mux_rd_rise1_r[4]_i_2_n_0\
    );
\gen_mux_rd[4].mux_rd_rise1_r_reg[4]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gen_mux_rd[4].mux_rd_rise1_r[4]_i_2_n_0\,
      I1 => \gen_mux_rd[4].mux_rd_rise1_r_reg[4]_2\,
      O => \rd_mux_sel_r_reg[2]_54\,
      S => \gen_mux_rd[1].mux_rd_rise0_r_reg[1]_2\
    );
\gen_mux_rd[4].mux_rd_rise2_r[4]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FDB97531ECA86420"
    )
        port map (
      I0 => \gen_mux_rd[0].mux_rd_rise0_r_reg[0]\(0),
      I1 => \gen_mux_rd[0].mux_rd_rise0_r_reg[0]\(1),
      I2 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]\,
      I3 => \gen_mux_rd[4].mux_rd_rise2_r_reg[4]\,
      I4 => \gen_mux_rd[4].mux_rd_rise2_r_reg[4]_0\,
      I5 => \gen_mux_rd[4].mux_rd_rise2_r_reg[4]_1\,
      O => \gen_mux_rd[4].mux_rd_rise2_r[4]_i_2_n_0\
    );
\gen_mux_rd[4].mux_rd_rise2_r_reg[4]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gen_mux_rd[4].mux_rd_rise2_r[4]_i_2_n_0\,
      I1 => \gen_mux_rd[4].mux_rd_rise2_r_reg[4]_2\,
      O => \rd_mux_sel_r_reg[2]_58\,
      S => \gen_mux_rd[1].mux_rd_rise0_r_reg[1]_2\
    );
\gen_mux_rd[4].mux_rd_rise3_r[4]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FDB97531ECA86420"
    )
        port map (
      I0 => \gen_mux_rd[0].mux_rd_rise0_r_reg[0]\(0),
      I1 => \gen_mux_rd[0].mux_rd_rise0_r_reg[0]\(1),
      I2 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]\,
      I3 => \gen_mux_rd[4].mux_rd_rise3_r_reg[4]\,
      I4 => \gen_mux_rd[4].mux_rd_rise3_r_reg[4]_0\,
      I5 => \gen_mux_rd[4].mux_rd_rise3_r_reg[4]_1\,
      O => \gen_mux_rd[4].mux_rd_rise3_r[4]_i_2_n_0\
    );
\gen_mux_rd[4].mux_rd_rise3_r_reg[4]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gen_mux_rd[4].mux_rd_rise3_r[4]_i_2_n_0\,
      I1 => \gen_mux_rd[4].mux_rd_rise3_r_reg[4]_2\,
      O => \rd_mux_sel_r_reg[2]_62\,
      S => \gen_mux_rd[1].mux_rd_rise0_r_reg[1]_2\
    );
\gen_mux_rd[5].mux_rd_fall0_r[5]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FDB97531ECA86420"
    )
        port map (
      I0 => \gen_mux_rd[0].mux_rd_rise0_r_reg[0]\(0),
      I1 => \gen_mux_rd[0].mux_rd_rise0_r_reg[0]\(1),
      I2 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]\,
      I3 => \gen_mux_rd[5].mux_rd_fall0_r_reg[5]\,
      I4 => \gen_mux_rd[5].mux_rd_fall0_r_reg[5]_0\,
      I5 => \gen_mux_rd[5].mux_rd_fall0_r_reg[5]_1\,
      O => \gen_mux_rd[5].mux_rd_fall0_r[5]_i_2_n_0\
    );
\gen_mux_rd[5].mux_rd_fall0_r_reg[5]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gen_mux_rd[5].mux_rd_fall0_r[5]_i_2_n_0\,
      I1 => \gen_mux_rd[5].mux_rd_fall0_r_reg[5]_2\,
      O => \rd_mux_sel_r_reg[2]_7\,
      S => \gen_mux_rd[1].mux_rd_rise0_r_reg[1]_2\
    );
\gen_mux_rd[5].mux_rd_fall1_r[5]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FDB97531ECA86420"
    )
        port map (
      I0 => \gen_mux_rd[0].mux_rd_rise0_r_reg[0]\(0),
      I1 => \gen_mux_rd[0].mux_rd_rise0_r_reg[0]\(1),
      I2 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]\,
      I3 => \gen_mux_rd[5].mux_rd_fall1_r_reg[5]\,
      I4 => \gen_mux_rd[5].mux_rd_fall1_r_reg[5]_0\,
      I5 => \gen_mux_rd[5].mux_rd_fall1_r_reg[5]_1\,
      O => \gen_mux_rd[5].mux_rd_fall1_r[5]_i_2_n_0\
    );
\gen_mux_rd[5].mux_rd_fall1_r_reg[5]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gen_mux_rd[5].mux_rd_fall1_r[5]_i_2_n_0\,
      I1 => \gen_mux_rd[5].mux_rd_fall1_r_reg[5]_2\,
      O => \rd_mux_sel_r_reg[2]_18\,
      S => \gen_mux_rd[1].mux_rd_rise0_r_reg[1]_2\
    );
\gen_mux_rd[5].mux_rd_fall2_r[5]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FDB97531ECA86420"
    )
        port map (
      I0 => \gen_mux_rd[0].mux_rd_rise0_r_reg[0]\(0),
      I1 => \gen_mux_rd[0].mux_rd_rise0_r_reg[0]\(1),
      I2 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]\,
      I3 => \gen_mux_rd[5].mux_rd_fall2_r_reg[5]\,
      I4 => \gen_mux_rd[5].mux_rd_fall2_r_reg[5]_0\,
      I5 => \gen_mux_rd[5].mux_rd_fall2_r_reg[5]_1\,
      O => \gen_mux_rd[5].mux_rd_fall2_r[5]_i_2_n_0\
    );
\gen_mux_rd[5].mux_rd_fall2_r_reg[5]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gen_mux_rd[5].mux_rd_fall2_r[5]_i_2_n_0\,
      I1 => \gen_mux_rd[5].mux_rd_fall2_r_reg[5]_2\,
      O => \rd_mux_sel_r_reg[2]_31\,
      S => \gen_mux_rd[1].mux_rd_rise0_r_reg[1]_2\
    );
\gen_mux_rd[5].mux_rd_fall3_r[5]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FDB97531ECA86420"
    )
        port map (
      I0 => \gen_mux_rd[0].mux_rd_rise0_r_reg[0]\(0),
      I1 => \gen_mux_rd[0].mux_rd_rise0_r_reg[0]\(1),
      I2 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]\,
      I3 => \gen_mux_rd[5].mux_rd_fall3_r_reg[5]\,
      I4 => \gen_mux_rd[5].mux_rd_fall3_r_reg[5]_0\,
      I5 => \gen_mux_rd[5].mux_rd_fall3_r_reg[5]_1\,
      O => \gen_mux_rd[5].mux_rd_fall3_r[5]_i_2_n_0\
    );
\gen_mux_rd[5].mux_rd_fall3_r_reg[5]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gen_mux_rd[5].mux_rd_fall3_r[5]_i_2_n_0\,
      I1 => \gen_mux_rd[5].mux_rd_fall3_r_reg[5]_2\,
      O => \rd_mux_sel_r_reg[2]_45\,
      S => \gen_mux_rd[1].mux_rd_rise0_r_reg[1]_2\
    );
\gen_mux_rd[5].mux_rd_rise0_r[5]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FDB97531ECA86420"
    )
        port map (
      I0 => \gen_mux_rd[0].mux_rd_rise0_r_reg[0]\(0),
      I1 => \gen_mux_rd[0].mux_rd_rise0_r_reg[0]\(1),
      I2 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]\,
      I3 => \gen_mux_rd[5].mux_rd_rise0_r_reg[5]\,
      I4 => \gen_mux_rd[5].mux_rd_rise0_r_reg[5]_0\,
      I5 => \gen_mux_rd[5].mux_rd_rise0_r_reg[5]_1\,
      O => \gen_mux_rd[5].mux_rd_rise0_r[5]_i_2_n_0\
    );
\gen_mux_rd[5].mux_rd_rise0_r_reg[5]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gen_mux_rd[5].mux_rd_rise0_r[5]_i_2_n_0\,
      I1 => \gen_mux_rd[5].mux_rd_rise0_r_reg[5]_2\,
      O => \rd_mux_sel_r_reg[2]_2\,
      S => \gen_mux_rd[1].mux_rd_rise0_r_reg[1]_2\
    );
\gen_mux_rd[5].mux_rd_rise1_r[5]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FDB97531ECA86420"
    )
        port map (
      I0 => \gen_mux_rd[0].mux_rd_rise0_r_reg[0]\(0),
      I1 => \gen_mux_rd[0].mux_rd_rise0_r_reg[0]\(1),
      I2 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]\,
      I3 => \gen_mux_rd[5].mux_rd_rise1_r_reg[5]\,
      I4 => \gen_mux_rd[5].mux_rd_rise1_r_reg[5]_0\,
      I5 => \gen_mux_rd[5].mux_rd_rise1_r_reg[5]_1\,
      O => \gen_mux_rd[5].mux_rd_rise1_r[5]_i_2_n_0\
    );
\gen_mux_rd[5].mux_rd_rise1_r_reg[5]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gen_mux_rd[5].mux_rd_rise1_r[5]_i_2_n_0\,
      I1 => \gen_mux_rd[5].mux_rd_rise1_r_reg[5]_2\,
      O => \rd_mux_sel_r_reg[2]_13\,
      S => \gen_mux_rd[1].mux_rd_rise0_r_reg[1]_2\
    );
\gen_mux_rd[5].mux_rd_rise2_r[5]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FDB97531ECA86420"
    )
        port map (
      I0 => \gen_mux_rd[0].mux_rd_rise0_r_reg[0]\(0),
      I1 => \gen_mux_rd[0].mux_rd_rise0_r_reg[0]\(1),
      I2 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]\,
      I3 => \gen_mux_rd[5].mux_rd_rise2_r_reg[5]\,
      I4 => \gen_mux_rd[5].mux_rd_rise2_r_reg[5]_0\,
      I5 => \gen_mux_rd[5].mux_rd_rise2_r_reg[5]_1\,
      O => \gen_mux_rd[5].mux_rd_rise2_r[5]_i_2_n_0\
    );
\gen_mux_rd[5].mux_rd_rise2_r_reg[5]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gen_mux_rd[5].mux_rd_rise2_r[5]_i_2_n_0\,
      I1 => \gen_mux_rd[5].mux_rd_rise2_r_reg[5]_2\,
      O => \rd_mux_sel_r_reg[2]_25\,
      S => \gen_mux_rd[1].mux_rd_rise0_r_reg[1]_2\
    );
\gen_mux_rd[5].mux_rd_rise3_r[5]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FDB97531ECA86420"
    )
        port map (
      I0 => \gen_mux_rd[0].mux_rd_rise0_r_reg[0]\(0),
      I1 => \gen_mux_rd[0].mux_rd_rise0_r_reg[0]\(1),
      I2 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]\,
      I3 => \gen_mux_rd[5].mux_rd_rise3_r_reg[5]\,
      I4 => \gen_mux_rd[5].mux_rd_rise3_r_reg[5]_0\,
      I5 => \gen_mux_rd[5].mux_rd_rise3_r_reg[5]_1\,
      O => \gen_mux_rd[5].mux_rd_rise3_r[5]_i_2_n_0\
    );
\gen_mux_rd[5].mux_rd_rise3_r_reg[5]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gen_mux_rd[5].mux_rd_rise3_r[5]_i_2_n_0\,
      I1 => \gen_mux_rd[5].mux_rd_rise3_r_reg[5]_2\,
      O => \rd_mux_sel_r_reg[2]_37\,
      S => \gen_mux_rd[1].mux_rd_rise0_r_reg[1]_2\
    );
\gen_mux_rd[6].mux_rd_fall0_r[6]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FDB97531ECA86420"
    )
        port map (
      I0 => \gen_mux_rd[0].mux_rd_rise0_r_reg[0]\(0),
      I1 => \gen_mux_rd[0].mux_rd_rise0_r_reg[0]\(1),
      I2 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]\,
      I3 => \gen_mux_rd[6].mux_rd_fall0_r_reg[6]\,
      I4 => \gen_mux_rd[6].mux_rd_fall0_r_reg[6]_0\,
      I5 => \gen_mux_rd[6].mux_rd_fall0_r_reg[6]_1\,
      O => \gen_mux_rd[6].mux_rd_fall0_r[6]_i_2_n_0\
    );
\gen_mux_rd[6].mux_rd_fall0_r_reg[6]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gen_mux_rd[6].mux_rd_fall0_r[6]_i_2_n_0\,
      I1 => \gen_mux_rd[6].mux_rd_fall0_r_reg[6]_2\,
      O => \rd_mux_sel_r_reg[2]_8\,
      S => \gen_mux_rd[1].mux_rd_rise0_r_reg[1]_2\
    );
\gen_mux_rd[6].mux_rd_fall1_r[6]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FDB97531ECA86420"
    )
        port map (
      I0 => \gen_mux_rd[0].mux_rd_rise0_r_reg[0]\(0),
      I1 => \gen_mux_rd[0].mux_rd_rise0_r_reg[0]\(1),
      I2 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]\,
      I3 => \gen_mux_rd[6].mux_rd_fall1_r_reg[6]\,
      I4 => \gen_mux_rd[6].mux_rd_fall1_r_reg[6]_0\,
      I5 => \gen_mux_rd[6].mux_rd_fall1_r_reg[6]_1\,
      O => \gen_mux_rd[6].mux_rd_fall1_r[6]_i_2_n_0\
    );
\gen_mux_rd[6].mux_rd_fall1_r_reg[6]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gen_mux_rd[6].mux_rd_fall1_r[6]_i_2_n_0\,
      I1 => \gen_mux_rd[6].mux_rd_fall1_r_reg[6]_2\,
      O => \rd_mux_sel_r_reg[2]_19\,
      S => \gen_mux_rd[1].mux_rd_rise0_r_reg[1]_2\
    );
\gen_mux_rd[6].mux_rd_fall2_r[6]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FDB97531ECA86420"
    )
        port map (
      I0 => \gen_mux_rd[0].mux_rd_rise0_r_reg[0]\(0),
      I1 => \gen_mux_rd[0].mux_rd_rise0_r_reg[0]\(1),
      I2 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]\,
      I3 => \gen_mux_rd[6].mux_rd_fall2_r_reg[6]\,
      I4 => \gen_mux_rd[6].mux_rd_fall2_r_reg[6]_0\,
      I5 => \gen_mux_rd[6].mux_rd_fall2_r_reg[6]_1\,
      O => \gen_mux_rd[6].mux_rd_fall2_r[6]_i_2_n_0\
    );
\gen_mux_rd[6].mux_rd_fall2_r_reg[6]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gen_mux_rd[6].mux_rd_fall2_r[6]_i_2_n_0\,
      I1 => \gen_mux_rd[6].mux_rd_fall2_r_reg[6]_2\,
      O => \rd_mux_sel_r_reg[2]_32\,
      S => \gen_mux_rd[1].mux_rd_rise0_r_reg[1]_2\
    );
\gen_mux_rd[6].mux_rd_fall3_r[6]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FDB97531ECA86420"
    )
        port map (
      I0 => \gen_mux_rd[0].mux_rd_rise0_r_reg[0]\(0),
      I1 => \gen_mux_rd[0].mux_rd_rise0_r_reg[0]\(1),
      I2 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]\,
      I3 => \gen_mux_rd[6].mux_rd_fall3_r_reg[6]\,
      I4 => \gen_mux_rd[6].mux_rd_fall3_r_reg[6]_0\,
      I5 => \gen_mux_rd[6].mux_rd_fall3_r_reg[6]_1\,
      O => \gen_mux_rd[6].mux_rd_fall3_r[6]_i_2_n_0\
    );
\gen_mux_rd[6].mux_rd_fall3_r_reg[6]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gen_mux_rd[6].mux_rd_fall3_r[6]_i_2_n_0\,
      I1 => \gen_mux_rd[6].mux_rd_fall3_r_reg[6]_2\,
      O => \rd_mux_sel_r_reg[2]_46\,
      S => \gen_mux_rd[1].mux_rd_rise0_r_reg[1]_2\
    );
\gen_mux_rd[6].mux_rd_rise0_r[6]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FDB97531ECA86420"
    )
        port map (
      I0 => \gen_mux_rd[0].mux_rd_rise0_r_reg[0]\(0),
      I1 => \gen_mux_rd[0].mux_rd_rise0_r_reg[0]\(1),
      I2 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]\,
      I3 => \gen_mux_rd[6].mux_rd_rise0_r_reg[6]\,
      I4 => \gen_mux_rd[6].mux_rd_rise0_r_reg[6]_0\,
      I5 => \gen_mux_rd[6].mux_rd_rise0_r_reg[6]_1\,
      O => \gen_mux_rd[6].mux_rd_rise0_r[6]_i_2_n_0\
    );
\gen_mux_rd[6].mux_rd_rise0_r_reg[6]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gen_mux_rd[6].mux_rd_rise0_r[6]_i_2_n_0\,
      I1 => \gen_mux_rd[6].mux_rd_rise0_r_reg[6]_2\,
      O => \rd_mux_sel_r_reg[2]_3\,
      S => \gen_mux_rd[1].mux_rd_rise0_r_reg[1]_2\
    );
\gen_mux_rd[6].mux_rd_rise1_r[6]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FDB97531ECA86420"
    )
        port map (
      I0 => \gen_mux_rd[0].mux_rd_rise0_r_reg[0]\(0),
      I1 => \gen_mux_rd[0].mux_rd_rise0_r_reg[0]\(1),
      I2 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]\,
      I3 => \gen_mux_rd[6].mux_rd_rise1_r_reg[6]\,
      I4 => \gen_mux_rd[6].mux_rd_rise1_r_reg[6]_0\,
      I5 => \gen_mux_rd[6].mux_rd_rise1_r_reg[6]_1\,
      O => \gen_mux_rd[6].mux_rd_rise1_r[6]_i_2_n_0\
    );
\gen_mux_rd[6].mux_rd_rise1_r_reg[6]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gen_mux_rd[6].mux_rd_rise1_r[6]_i_2_n_0\,
      I1 => \gen_mux_rd[6].mux_rd_rise1_r_reg[6]_2\,
      O => \rd_mux_sel_r_reg[2]_14\,
      S => \gen_mux_rd[1].mux_rd_rise0_r_reg[1]_2\
    );
\gen_mux_rd[6].mux_rd_rise2_r[6]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FDB97531ECA86420"
    )
        port map (
      I0 => \gen_mux_rd[0].mux_rd_rise0_r_reg[0]\(0),
      I1 => \gen_mux_rd[0].mux_rd_rise0_r_reg[0]\(1),
      I2 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]\,
      I3 => \gen_mux_rd[6].mux_rd_rise2_r_reg[6]\,
      I4 => \gen_mux_rd[6].mux_rd_rise2_r_reg[6]_0\,
      I5 => \gen_mux_rd[6].mux_rd_rise2_r_reg[6]_1\,
      O => \gen_mux_rd[6].mux_rd_rise2_r[6]_i_2_n_0\
    );
\gen_mux_rd[6].mux_rd_rise2_r_reg[6]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gen_mux_rd[6].mux_rd_rise2_r[6]_i_2_n_0\,
      I1 => \gen_mux_rd[6].mux_rd_rise2_r_reg[6]_2\,
      O => \rd_mux_sel_r_reg[2]_26\,
      S => \gen_mux_rd[1].mux_rd_rise0_r_reg[1]_2\
    );
\gen_mux_rd[6].mux_rd_rise3_r[6]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FDB97531ECA86420"
    )
        port map (
      I0 => \gen_mux_rd[0].mux_rd_rise0_r_reg[0]\(0),
      I1 => \gen_mux_rd[0].mux_rd_rise0_r_reg[0]\(1),
      I2 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]\,
      I3 => \gen_mux_rd[6].mux_rd_rise3_r_reg[6]\,
      I4 => \gen_mux_rd[6].mux_rd_rise3_r_reg[6]_0\,
      I5 => \gen_mux_rd[6].mux_rd_rise3_r_reg[6]_1\,
      O => \gen_mux_rd[6].mux_rd_rise3_r[6]_i_2_n_0\
    );
\gen_mux_rd[6].mux_rd_rise3_r_reg[6]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gen_mux_rd[6].mux_rd_rise3_r[6]_i_2_n_0\,
      I1 => \gen_mux_rd[6].mux_rd_rise3_r_reg[6]_2\,
      O => \rd_mux_sel_r_reg[2]_38\,
      S => \gen_mux_rd[1].mux_rd_rise0_r_reg[1]_2\
    );
\gen_mux_rd[7].mux_rd_fall0_r[7]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FDB97531ECA86420"
    )
        port map (
      I0 => \gen_mux_rd[0].mux_rd_rise0_r_reg[0]\(0),
      I1 => \gen_mux_rd[0].mux_rd_rise0_r_reg[0]\(1),
      I2 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]\,
      I3 => \gen_mux_rd[7].mux_rd_fall0_r_reg[7]\,
      I4 => \gen_mux_rd[7].mux_rd_fall0_r_reg[7]_0\,
      I5 => \gen_mux_rd[7].mux_rd_fall0_r_reg[7]_1\,
      O => \gen_mux_rd[7].mux_rd_fall0_r[7]_i_2_n_0\
    );
\gen_mux_rd[7].mux_rd_fall0_r_reg[7]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gen_mux_rd[7].mux_rd_fall0_r[7]_i_2_n_0\,
      I1 => \gen_mux_rd[7].mux_rd_fall0_r_reg[7]_2\,
      O => \rd_mux_sel_r_reg[2]_9\,
      S => \gen_mux_rd[1].mux_rd_rise0_r_reg[1]_2\
    );
\gen_mux_rd[7].mux_rd_fall1_r[7]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FDB97531ECA86420"
    )
        port map (
      I0 => \gen_mux_rd[0].mux_rd_rise0_r_reg[0]\(0),
      I1 => \gen_mux_rd[0].mux_rd_rise0_r_reg[0]\(1),
      I2 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]\,
      I3 => \gen_mux_rd[7].mux_rd_fall1_r_reg[7]\,
      I4 => \gen_mux_rd[7].mux_rd_fall1_r_reg[7]_0\,
      I5 => \gen_mux_rd[7].mux_rd_fall1_r_reg[7]_1\,
      O => \gen_mux_rd[7].mux_rd_fall1_r[7]_i_2_n_0\
    );
\gen_mux_rd[7].mux_rd_fall1_r_reg[7]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gen_mux_rd[7].mux_rd_fall1_r[7]_i_2_n_0\,
      I1 => \gen_mux_rd[7].mux_rd_fall1_r_reg[7]_2\,
      O => \rd_mux_sel_r_reg[2]_20\,
      S => \gen_mux_rd[1].mux_rd_rise0_r_reg[1]_2\
    );
\gen_mux_rd[7].mux_rd_fall2_r[7]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FDB97531ECA86420"
    )
        port map (
      I0 => \gen_mux_rd[0].mux_rd_rise0_r_reg[0]\(0),
      I1 => \gen_mux_rd[0].mux_rd_rise0_r_reg[0]\(1),
      I2 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]\,
      I3 => \gen_mux_rd[7].mux_rd_fall2_r_reg[7]\,
      I4 => \gen_mux_rd[7].mux_rd_fall2_r_reg[7]_0\,
      I5 => \gen_mux_rd[7].mux_rd_fall2_r_reg[7]_1\,
      O => \gen_mux_rd[7].mux_rd_fall2_r[7]_i_2_n_0\
    );
\gen_mux_rd[7].mux_rd_fall2_r_reg[7]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gen_mux_rd[7].mux_rd_fall2_r[7]_i_2_n_0\,
      I1 => \gen_mux_rd[7].mux_rd_fall2_r_reg[7]_2\,
      O => \rd_mux_sel_r_reg[2]_33\,
      S => \gen_mux_rd[1].mux_rd_rise0_r_reg[1]_2\
    );
\gen_mux_rd[7].mux_rd_fall3_r[7]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FDB97531ECA86420"
    )
        port map (
      I0 => \gen_mux_rd[0].mux_rd_rise0_r_reg[0]\(0),
      I1 => \gen_mux_rd[0].mux_rd_rise0_r_reg[0]\(1),
      I2 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]\,
      I3 => \gen_mux_rd[7].mux_rd_fall3_r_reg[7]\,
      I4 => \gen_mux_rd[7].mux_rd_fall3_r_reg[7]_0\,
      I5 => \gen_mux_rd[7].mux_rd_fall3_r_reg[7]_1\,
      O => \gen_mux_rd[7].mux_rd_fall3_r[7]_i_2_n_0\
    );
\gen_mux_rd[7].mux_rd_fall3_r_reg[7]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gen_mux_rd[7].mux_rd_fall3_r[7]_i_2_n_0\,
      I1 => \gen_mux_rd[7].mux_rd_fall3_r_reg[7]_2\,
      O => \rd_mux_sel_r_reg[2]_47\,
      S => \gen_mux_rd[1].mux_rd_rise0_r_reg[1]_2\
    );
\gen_mux_rd[7].mux_rd_rise0_r[7]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FDB97531ECA86420"
    )
        port map (
      I0 => \gen_mux_rd[0].mux_rd_rise0_r_reg[0]\(0),
      I1 => \gen_mux_rd[0].mux_rd_rise0_r_reg[0]\(1),
      I2 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]\,
      I3 => \gen_mux_rd[7].mux_rd_rise0_r_reg[7]\,
      I4 => \gen_mux_rd[7].mux_rd_rise0_r_reg[7]_0\,
      I5 => \gen_mux_rd[7].mux_rd_rise0_r_reg[7]_1\,
      O => \gen_mux_rd[7].mux_rd_rise0_r[7]_i_2_n_0\
    );
\gen_mux_rd[7].mux_rd_rise0_r_reg[7]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gen_mux_rd[7].mux_rd_rise0_r[7]_i_2_n_0\,
      I1 => \gen_mux_rd[7].mux_rd_rise0_r_reg[7]_2\,
      O => \rd_mux_sel_r_reg[2]_4\,
      S => \gen_mux_rd[1].mux_rd_rise0_r_reg[1]_2\
    );
\gen_mux_rd[7].mux_rd_rise1_r[7]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FDB97531ECA86420"
    )
        port map (
      I0 => \gen_mux_rd[0].mux_rd_rise0_r_reg[0]\(0),
      I1 => \gen_mux_rd[0].mux_rd_rise0_r_reg[0]\(1),
      I2 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]\,
      I3 => \gen_mux_rd[7].mux_rd_rise1_r_reg[7]\,
      I4 => \gen_mux_rd[7].mux_rd_rise1_r_reg[7]_0\,
      I5 => \gen_mux_rd[7].mux_rd_rise1_r_reg[7]_1\,
      O => \gen_mux_rd[7].mux_rd_rise1_r[7]_i_2_n_0\
    );
\gen_mux_rd[7].mux_rd_rise1_r_reg[7]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gen_mux_rd[7].mux_rd_rise1_r[7]_i_2_n_0\,
      I1 => \gen_mux_rd[7].mux_rd_rise1_r_reg[7]_2\,
      O => \rd_mux_sel_r_reg[2]_15\,
      S => \gen_mux_rd[1].mux_rd_rise0_r_reg[1]_2\
    );
\gen_mux_rd[7].mux_rd_rise2_r[7]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FDB97531ECA86420"
    )
        port map (
      I0 => \gen_mux_rd[0].mux_rd_rise0_r_reg[0]\(0),
      I1 => \gen_mux_rd[0].mux_rd_rise0_r_reg[0]\(1),
      I2 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]\,
      I3 => \gen_mux_rd[7].mux_rd_rise2_r_reg[7]\,
      I4 => \gen_mux_rd[7].mux_rd_rise2_r_reg[7]_0\,
      I5 => \gen_mux_rd[7].mux_rd_rise2_r_reg[7]_1\,
      O => \gen_mux_rd[7].mux_rd_rise2_r[7]_i_2_n_0\
    );
\gen_mux_rd[7].mux_rd_rise2_r_reg[7]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gen_mux_rd[7].mux_rd_rise2_r[7]_i_2_n_0\,
      I1 => \gen_mux_rd[7].mux_rd_rise2_r_reg[7]_2\,
      O => \rd_mux_sel_r_reg[2]_27\,
      S => \gen_mux_rd[1].mux_rd_rise0_r_reg[1]_2\
    );
\gen_mux_rd[7].mux_rd_rise3_r[7]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FDB97531ECA86420"
    )
        port map (
      I0 => \gen_mux_rd[0].mux_rd_rise0_r_reg[0]\(0),
      I1 => \gen_mux_rd[0].mux_rd_rise0_r_reg[0]\(1),
      I2 => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]\,
      I3 => \gen_mux_rd[7].mux_rd_rise3_r_reg[7]\,
      I4 => \gen_mux_rd[7].mux_rd_rise3_r_reg[7]_0\,
      I5 => \gen_mux_rd[7].mux_rd_rise3_r_reg[7]_1\,
      O => \gen_mux_rd[7].mux_rd_rise3_r[7]_i_2_n_0\
    );
\gen_mux_rd[7].mux_rd_rise3_r_reg[7]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gen_mux_rd[7].mux_rd_rise3_r[7]_i_2_n_0\,
      I1 => \gen_mux_rd[7].mux_rd_rise3_r_reg[7]_2\,
      O => \rd_mux_sel_r_reg[2]_39\,
      S => \gen_mux_rd[1].mux_rd_rise0_r_reg[1]_2\
    );
mem_reg_0_3_12_17: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 2) => B"000",
      ADDRA(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRB(4 downto 2) => B"000",
      ADDRB(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRC(4 downto 2) => B"000",
      ADDRC(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRD(4 downto 2) => B"000",
      ADDRD(1 downto 0) => wr_ptr(1 downto 0),
      DIA(1 downto 0) => Q(1 downto 0),
      DIB(1 downto 0) => Q(3 downto 2),
      DIC(1 downto 0) => Q(5 downto 4),
      DID(1 downto 0) => B"00",
      DOA(1) => mem_reg_0_3_12_17_n_0,
      DOA(0) => mem_reg_0_3_12_17_n_1,
      DOB(1) => mem_reg_0_3_12_17_n_2,
      DOB(0) => mem_reg_0_3_12_17_n_3,
      DOC(1 downto 0) => mem_out(17 downto 16),
      DOD(1 downto 0) => NLW_mem_reg_0_3_12_17_DOD_UNCONNECTED(1 downto 0),
      WCLK => \rd_ptr_reg[1]_0\,
      WE => wr_en
    );
\mem_reg_0_3_12_17_i_1__2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0151"
    )
        port map (
      I0 => \wr_ptr_reg[0]_0\,
      I1 => my_full(0),
      I2 => \my_full_reg[1]_0\,
      I3 => my_empty_0(2),
      O => wr_en
    );
mem_reg_0_3_18_23: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 2) => B"000",
      ADDRA(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRB(4 downto 2) => B"000",
      ADDRB(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRC(4 downto 2) => B"000",
      ADDRC(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRD(4 downto 2) => B"000",
      ADDRD(1 downto 0) => wr_ptr(1 downto 0),
      DIA(1 downto 0) => Q(7 downto 6),
      DIB(1 downto 0) => Q(9 downto 8),
      DIC(1 downto 0) => Q(11 downto 10),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => mem_out(19 downto 18),
      DOB(1 downto 0) => mem_out(21 downto 20),
      DOC(1 downto 0) => mem_out(23 downto 22),
      DOD(1 downto 0) => NLW_mem_reg_0_3_18_23_DOD_UNCONNECTED(1 downto 0),
      WCLK => \rd_ptr_reg[1]_0\,
      WE => wr_en
    );
mem_reg_0_3_24_29: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 2) => B"000",
      ADDRA(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRB(4 downto 2) => B"000",
      ADDRB(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRC(4 downto 2) => B"000",
      ADDRC(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRD(4 downto 2) => B"000",
      ADDRD(1 downto 0) => wr_ptr(1 downto 0),
      DIA(1 downto 0) => Q(13 downto 12),
      DIB(1 downto 0) => Q(15 downto 14),
      DIC(1 downto 0) => Q(17 downto 16),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => mem_out(25 downto 24),
      DOB(1 downto 0) => mem_out(27 downto 26),
      DOC(1 downto 0) => mem_out(29 downto 28),
      DOD(1 downto 0) => NLW_mem_reg_0_3_24_29_DOD_UNCONNECTED(1 downto 0),
      WCLK => \rd_ptr_reg[1]_0\,
      WE => wr_en
    );
mem_reg_0_3_30_35: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 2) => B"000",
      ADDRA(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRB(4 downto 2) => B"000",
      ADDRB(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRC(4 downto 2) => B"000",
      ADDRC(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRD(4 downto 2) => B"000",
      ADDRD(1 downto 0) => wr_ptr(1 downto 0),
      DIA(1 downto 0) => Q(19 downto 18),
      DIB(1 downto 0) => Q(21 downto 20),
      DIC(1 downto 0) => Q(23 downto 22),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => mem_out(31 downto 30),
      DOB(1 downto 0) => mem_out(33 downto 32),
      DOC(1 downto 0) => mem_out(35 downto 34),
      DOD(1 downto 0) => NLW_mem_reg_0_3_30_35_DOD_UNCONNECTED(1 downto 0),
      WCLK => \rd_ptr_reg[1]_0\,
      WE => wr_en
    );
mem_reg_0_3_36_41: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 2) => B"000",
      ADDRA(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRB(4 downto 2) => B"000",
      ADDRB(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRC(4 downto 2) => B"000",
      ADDRC(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRD(4 downto 2) => B"000",
      ADDRD(1 downto 0) => wr_ptr(1 downto 0),
      DIA(1 downto 0) => Q(25 downto 24),
      DIB(1 downto 0) => Q(27 downto 26),
      DIC(1 downto 0) => Q(29 downto 28),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => mem_out(37 downto 36),
      DOB(1 downto 0) => mem_out(39 downto 38),
      DOC(1 downto 0) => mem_out(41 downto 40),
      DOD(1 downto 0) => NLW_mem_reg_0_3_36_41_DOD_UNCONNECTED(1 downto 0),
      WCLK => \rd_ptr_reg[1]_0\,
      WE => wr_en
    );
mem_reg_0_3_42_47: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 2) => B"000",
      ADDRA(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRB(4 downto 2) => B"000",
      ADDRB(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRC(4 downto 2) => B"000",
      ADDRC(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRD(4 downto 2) => B"000",
      ADDRD(1 downto 0) => wr_ptr(1 downto 0),
      DIA(1 downto 0) => Q(31 downto 30),
      DIB(1 downto 0) => Q(33 downto 32),
      DIC(1 downto 0) => Q(35 downto 34),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => mem_out(43 downto 42),
      DOB(1 downto 0) => mem_out(45 downto 44),
      DOC(1 downto 0) => mem_out(47 downto 46),
      DOD(1 downto 0) => NLW_mem_reg_0_3_42_47_DOD_UNCONNECTED(1 downto 0),
      WCLK => \rd_ptr_reg[1]_0\,
      WE => wr_en
    );
mem_reg_0_3_48_53: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 2) => B"000",
      ADDRA(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRB(4 downto 2) => B"000",
      ADDRB(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRC(4 downto 2) => B"000",
      ADDRC(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRD(4 downto 2) => B"000",
      ADDRD(1 downto 0) => wr_ptr(1 downto 0),
      DIA(1 downto 0) => Q(37 downto 36),
      DIB(1 downto 0) => Q(39 downto 38),
      DIC(1 downto 0) => Q(41 downto 40),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => mem_out(49 downto 48),
      DOB(1 downto 0) => mem_out(51 downto 50),
      DOC(1 downto 0) => mem_out(53 downto 52),
      DOD(1 downto 0) => NLW_mem_reg_0_3_48_53_DOD_UNCONNECTED(1 downto 0),
      WCLK => \rd_ptr_reg[1]_0\,
      WE => wr_en
    );
mem_reg_0_3_54_59: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 2) => B"000",
      ADDRA(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRB(4 downto 2) => B"000",
      ADDRB(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRC(4 downto 2) => B"000",
      ADDRC(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRD(4 downto 2) => B"000",
      ADDRD(1 downto 0) => wr_ptr(1 downto 0),
      DIA(1 downto 0) => Q(43 downto 42),
      DIB(1 downto 0) => Q(45 downto 44),
      DIC(1 downto 0) => Q(47 downto 46),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => mem_out(55 downto 54),
      DOB(1 downto 0) => mem_out(57 downto 56),
      DOC(1 downto 0) => mem_out(59 downto 58),
      DOD(1 downto 0) => NLW_mem_reg_0_3_54_59_DOD_UNCONNECTED(1 downto 0),
      WCLK => \rd_ptr_reg[1]_0\,
      WE => wr_en
    );
mem_reg_0_3_60_65: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 2) => B"000",
      ADDRA(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRB(4 downto 2) => B"000",
      ADDRB(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRC(4 downto 2) => B"000",
      ADDRC(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRD(4 downto 2) => B"000",
      ADDRD(1 downto 0) => wr_ptr(1 downto 0),
      DIA(1 downto 0) => Q(49 downto 48),
      DIB(1 downto 0) => Q(51 downto 50),
      DIC(1 downto 0) => Q(53 downto 52),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => mem_out(61 downto 60),
      DOB(1 downto 0) => mem_out(63 downto 62),
      DOC(1 downto 0) => mem_out(65 downto 64),
      DOD(1 downto 0) => NLW_mem_reg_0_3_60_65_DOD_UNCONNECTED(1 downto 0),
      WCLK => \rd_ptr_reg[1]_0\,
      WE => wr_en
    );
mem_reg_0_3_66_71: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 2) => B"000",
      ADDRA(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRB(4 downto 2) => B"000",
      ADDRB(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRC(4 downto 2) => B"000",
      ADDRC(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRD(4 downto 2) => B"000",
      ADDRD(1 downto 0) => wr_ptr(1 downto 0),
      DIA(1 downto 0) => Q(55 downto 54),
      DIB(1 downto 0) => Q(57 downto 56),
      DIC(1 downto 0) => Q(59 downto 58),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => mem_out(67 downto 66),
      DOB(1 downto 0) => mem_out(69 downto 68),
      DOC(1 downto 0) => mem_out(71 downto 70),
      DOD(1 downto 0) => NLW_mem_reg_0_3_66_71_DOD_UNCONNECTED(1 downto 0),
      WCLK => \rd_ptr_reg[1]_0\,
      WE => wr_en
    );
mem_reg_0_3_72_77: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 2) => B"000",
      ADDRA(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRB(4 downto 2) => B"000",
      ADDRB(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRC(4 downto 2) => B"000",
      ADDRC(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRD(4 downto 2) => B"000",
      ADDRD(1 downto 0) => wr_ptr(1 downto 0),
      DIA(1 downto 0) => Q(61 downto 60),
      DIB(1 downto 0) => Q(63 downto 62),
      DIC(1 downto 0) => Q(65 downto 64),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => mem_out(73 downto 72),
      DOB(1 downto 0) => mem_out(75 downto 74),
      DOC(1 downto 0) => mem_out(77 downto 76),
      DOD(1 downto 0) => NLW_mem_reg_0_3_72_77_DOD_UNCONNECTED(1 downto 0),
      WCLK => \rd_ptr_reg[1]_0\,
      WE => wr_en
    );
mem_reg_0_3_78_79: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 2) => B"000",
      ADDRA(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRB(4 downto 2) => B"000",
      ADDRB(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRC(4 downto 2) => B"000",
      ADDRC(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRD(4 downto 2) => B"000",
      ADDRD(1 downto 0) => wr_ptr(1 downto 0),
      DIA(1 downto 0) => Q(67 downto 66),
      DIB(1 downto 0) => B"00",
      DIC(1 downto 0) => B"00",
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => mem_out(79 downto 78),
      DOB(1 downto 0) => NLW_mem_reg_0_3_78_79_DOB_UNCONNECTED(1 downto 0),
      DOC(1 downto 0) => NLW_mem_reg_0_3_78_79_DOC_UNCONNECTED(1 downto 0),
      DOD(1 downto 0) => NLW_mem_reg_0_3_78_79_DOD_UNCONNECTED(1 downto 0),
      WCLK => \rd_ptr_reg[1]_0\,
      WE => wr_en
    );
\my_empty[4]_i_1__4\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0018"
    )
        port map (
      I0 => \my_full_reg[1]_0\,
      I1 => \wr_ptr_reg[0]_0\,
      I2 => my_empty_0(1),
      I3 => my_full(1),
      O => \my_empty[4]_i_1__4_n_0\
    );
\my_empty[4]_i_2__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00411400"
    )
        port map (
      I0 => my_empty_0(1),
      I1 => wr_ptr(1),
      I2 => rd_ptr(1),
      I3 => rd_ptr(0),
      I4 => wr_ptr(0),
      O => \my_empty[4]_i_2__0_n_0\
    );
\my_empty_inst__3\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \my_empty_reg[4]_rep_n_0\,
      O => my_empty_0(4)
    );
\my_empty_inst__4\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \^my_empty_reg[4]_0\,
      O => \^my_empty_reg[4]_1\(0)
    );
\my_empty_inst__5\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \^my_empty_reg[4]_0\,
      O => my_empty_0(2)
    );
\my_empty_inst__6\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \^my_empty_reg[4]_0\,
      O => my_empty_0(1)
    );
\my_empty_inst_rep__0\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \my_empty_reg[4]_rep__0_n_0\,
      O => \my_empty_inst_rep__0_n_0\
    );
\my_empty_reg[4]\: unisim.vcomponents.FDSE
     port map (
      C => \rd_ptr_reg[1]_0\,
      CE => \my_empty[4]_i_1__4_n_0\,
      D => \my_empty[4]_i_2__0_n_0\,
      Q => \^my_empty_reg[4]_0\,
      S => ififo_rst
    );
\my_empty_reg[4]_rep\: unisim.vcomponents.FDSE
     port map (
      C => \rd_ptr_reg[1]_0\,
      CE => \my_empty[4]_i_1__4_n_0\,
      D => \my_empty[4]_i_2__0_n_0\,
      Q => \my_empty_reg[4]_rep_n_0\,
      S => ififo_rst
    );
\my_empty_reg[4]_rep__0\: unisim.vcomponents.FDSE
     port map (
      C => \rd_ptr_reg[1]_0\,
      CE => \my_empty[4]_i_1__4_n_0\,
      D => \my_empty[4]_i_2__0_n_0\,
      Q => \my_empty_reg[4]_rep__0_n_0\,
      S => ififo_rst
    );
\my_full[0]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAEAABAAAA2AA8"
    )
        port map (
      I0 => my_full(0),
      I1 => \my_full_reg[1]_0\,
      I2 => \wr_ptr_reg[0]_0\,
      I3 => my_full(1),
      I4 => my_empty_0(1),
      I5 => \my_full[1]_i_2__0_n_0\,
      O => \my_full[0]_i_1__0_n_0\
    );
\my_full[1]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"F0F1F070"
    )
        port map (
      I0 => \my_full_reg[1]_0\,
      I1 => \wr_ptr_reg[0]_0\,
      I2 => my_full(1),
      I3 => my_empty_0(1),
      I4 => \my_full[1]_i_2__0_n_0\,
      O => \my_full[1]_i_1__0_n_0\
    );
\my_full[1]_i_2__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00411400"
    )
        port map (
      I0 => my_full(1),
      I1 => rd_ptr(1),
      I2 => wr_ptr(1),
      I3 => wr_ptr(0),
      I4 => rd_ptr(0),
      O => \my_full[1]_i_2__0_n_0\
    );
\my_full_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \rd_ptr_reg[1]_0\,
      CE => '1',
      D => \my_full[0]_i_1__0_n_0\,
      Q => my_full(0),
      R => ififo_rst
    );
\my_full_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \rd_ptr_reg[1]_0\,
      CE => '1',
      D => \my_full[1]_i_1__0_n_0\,
      Q => my_full(1),
      R => ififo_rst
    );
\rd_ptr[0]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"D2"
    )
        port map (
      I0 => \my_full_reg[1]_0\,
      I1 => my_empty_0(1),
      I2 => rd_ptr(0),
      O => \rd_ptr[0]_i_1__0_n_0\
    );
\rd_ptr[1]_i_1__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F708"
    )
        port map (
      I0 => rd_ptr(0),
      I1 => \my_full_reg[1]_0\,
      I2 => my_empty_0(1),
      I3 => rd_ptr(1),
      O => \rd_ptr[1]_i_1__0_n_0\
    );
\rd_ptr_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \rd_ptr_reg[1]_0\,
      CE => '1',
      D => \rd_ptr[0]_i_1__0_n_0\,
      Q => rd_ptr(0),
      R => ififo_rst
    );
\rd_ptr_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \rd_ptr_reg[1]_0\,
      CE => '1',
      D => \rd_ptr[1]_i_1__0_n_0\,
      Q => rd_ptr(1),
      R => ififo_rst
    );
\rd_ptr_timing[0]_i_1__2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F704"
    )
        port map (
      I0 => rd_ptr(0),
      I1 => \my_full_reg[1]_0\,
      I2 => my_empty_0(1),
      I3 => rd_ptr_timing(0),
      O => \rd_ptr_timing[0]_i_1__2_n_0\
    );
\rd_ptr_timing[1]_i_1__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FF6F0060"
    )
        port map (
      I0 => rd_ptr(0),
      I1 => rd_ptr(1),
      I2 => \my_full_reg[1]_0\,
      I3 => my_empty_0(1),
      I4 => rd_ptr_timing(1),
      O => \rd_ptr_timing[1]_i_1__2_n_0\
    );
\rd_ptr_timing_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \rd_ptr_reg[1]_0\,
      CE => '1',
      D => \rd_ptr_timing[0]_i_1__2_n_0\,
      Q => rd_ptr_timing(0),
      R => ififo_rst
    );
\rd_ptr_timing_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \rd_ptr_reg[1]_0\,
      CE => '1',
      D => \rd_ptr_timing[1]_i_1__2_n_0\,
      Q => rd_ptr_timing(1),
      R => ififo_rst
    );
\wr_ptr[0]_i_1__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FECE0131"
    )
        port map (
      I0 => my_full(1),
      I1 => \wr_ptr_reg[0]_0\,
      I2 => \my_full_reg[1]_0\,
      I3 => my_empty_0(1),
      I4 => wr_ptr(0),
      O => \wr_ptr[0]_i_1__2_n_0\
    );
\wr_ptr[1]_i_1__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFDF5FD00020A02"
    )
        port map (
      I0 => wr_ptr(0),
      I1 => my_full(1),
      I2 => \wr_ptr_reg[0]_0\,
      I3 => \my_full_reg[1]_0\,
      I4 => my_empty_0(1),
      I5 => wr_ptr(1),
      O => \wr_ptr[1]_i_1__2_n_0\
    );
\wr_ptr[1]_i_4__1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F888"
    )
        port map (
      I0 => \^my_empty_reg[4]_1\(0),
      I1 => \wr_ptr_reg[0]_0\,
      I2 => my_empty(0),
      I3 => \wr_ptr[1]_i_2__0\,
      O => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]\
    );
\wr_ptr[1]_i_7\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \wr_ptr_reg[0]_0\,
      I1 => \^my_empty_reg[4]_1\(0),
      O => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0\
    );
\wr_ptr_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \rd_ptr_reg[1]_0\,
      CE => '1',
      D => \wr_ptr[0]_i_1__2_n_0\,
      Q => wr_ptr(0),
      R => ififo_rst
    );
\wr_ptr_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \rd_ptr_reg[1]_0\,
      CE => '1',
      D => \wr_ptr[1]_i_1__2_n_0\,
      Q => wr_ptr(1),
      R => ififo_rst
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mig_mig_7series_v4_2_ddr_if_post_fifo_39 is
  port (
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0\ : out STD_LOGIC;
    if_empty : out STD_LOGIC;
    phy_rddata_en : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]\ : out STD_LOGIC;
    ififo_rst : in STD_LOGIC;
    \rd_ptr_timing_reg[1]_0\ : in STD_LOGIC;
    if_empty_r_0 : in STD_LOGIC_VECTOR ( 0 to 0 );
    my_empty : in STD_LOGIC_VECTOR ( 1 downto 0 );
    if_empty_r : in STD_LOGIC_VECTOR ( 0 to 0 );
    \my_full_reg[1]_0\ : in STD_LOGIC;
    my_empty_0 : in STD_LOGIC_VECTOR ( 0 to 0 );
    \wr_ptr[1]_i_2\ : in STD_LOGIC;
    phy_if_empty_r_reg : in STD_LOGIC;
    if_empty_v : in STD_LOGIC_VECTOR ( 0 to 0 );
    Q : in STD_LOGIC_VECTOR ( 67 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of mig_mig_7series_v4_2_ddr_if_post_fifo_39 : entity is "mig_7series_v4_2_ddr_if_post_fifo";
end mig_mig_7series_v4_2_ddr_if_post_fifo_39;

architecture STRUCTURE of mig_mig_7series_v4_2_ddr_if_post_fifo_39 is
  signal \^if_empty\ : STD_LOGIC;
  signal mem_out : STD_LOGIC_VECTOR ( 79 downto 8 );
  signal mem_reg_0_3_60_65_n_4 : STD_LOGIC;
  signal mem_reg_0_3_60_65_n_5 : STD_LOGIC;
  signal mem_reg_0_3_6_11_n_0 : STD_LOGIC;
  signal mem_reg_0_3_6_11_n_1 : STD_LOGIC;
  signal \my_empty[4]_i_1__3_n_0\ : STD_LOGIC;
  signal \my_empty[4]_i_2_n_0\ : STD_LOGIC;
  signal my_empty_1 : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal my_empty_inst_rep_n_0 : STD_LOGIC;
  signal \my_empty_reg[4]_rep__0_n_0\ : STD_LOGIC;
  signal \my_empty_reg[4]_rep_n_0\ : STD_LOGIC;
  signal my_full : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \my_full[0]_i_1_n_0\ : STD_LOGIC;
  signal \my_full[1]_i_1_n_0\ : STD_LOGIC;
  signal \my_full[1]_i_2_n_0\ : STD_LOGIC;
  signal rd_ptr : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \rd_ptr[0]_i_1_n_0\ : STD_LOGIC;
  signal \rd_ptr[1]_i_1_n_0\ : STD_LOGIC;
  signal rd_ptr_timing : STD_LOGIC_VECTOR ( 1 downto 0 );
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of rd_ptr_timing : signal is "true";
  attribute syn_maxfan : string;
  attribute syn_maxfan of rd_ptr_timing : signal is "10";
  signal \rd_ptr_timing[0]_i_1__0_n_0\ : STD_LOGIC;
  signal \rd_ptr_timing[1]_i_1__0_n_0\ : STD_LOGIC;
  signal wr_en : STD_LOGIC;
  attribute MAX_FANOUT : string;
  attribute MAX_FANOUT of wr_en : signal is "40";
  attribute RTL_MAX_FANOUT : string;
  attribute RTL_MAX_FANOUT of wr_en : signal is "found";
  attribute syn_maxfan of wr_en : signal is "10";
  signal wr_ptr : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \wr_ptr[0]_i_1__0_n_0\ : STD_LOGIC;
  signal \wr_ptr[1]_i_1__0_n_0\ : STD_LOGIC;
  signal NLW_mem_reg_0_3_12_17_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_3_18_23_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_3_24_29_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_3_30_35_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_3_36_41_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_3_42_47_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_3_48_53_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_3_54_59_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_3_60_65_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_3_6_11_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_3_72_77_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_3_78_79_DOB_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_3_78_79_DOC_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_3_78_79_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \app_rd_data[100]_INST_0\ : label is "soft_lutpair690";
  attribute SOFT_HLUTNM of \app_rd_data[101]_INST_0\ : label is "soft_lutpair687";
  attribute SOFT_HLUTNM of \app_rd_data[102]_INST_0\ : label is "soft_lutpair677";
  attribute SOFT_HLUTNM of \app_rd_data[103]_INST_0\ : label is "soft_lutpair685";
  attribute SOFT_HLUTNM of \app_rd_data[160]_INST_0\ : label is "soft_lutpair678";
  attribute SOFT_HLUTNM of \app_rd_data[161]_INST_0\ : label is "soft_lutpair673";
  attribute SOFT_HLUTNM of \app_rd_data[162]_INST_0\ : label is "soft_lutpair667";
  attribute SOFT_HLUTNM of \app_rd_data[163]_INST_0\ : label is "soft_lutpair676";
  attribute SOFT_HLUTNM of \app_rd_data[164]_INST_0\ : label is "soft_lutpair671";
  attribute SOFT_HLUTNM of \app_rd_data[165]_INST_0\ : label is "soft_lutpair666";
  attribute SOFT_HLUTNM of \app_rd_data[166]_INST_0\ : label is "soft_lutpair674";
  attribute SOFT_HLUTNM of \app_rd_data[167]_INST_0\ : label is "soft_lutpair665";
  attribute SOFT_HLUTNM of \app_rd_data[224]_INST_0\ : label is "soft_lutpair693";
  attribute SOFT_HLUTNM of \app_rd_data[225]_INST_0\ : label is "soft_lutpair692";
  attribute SOFT_HLUTNM of \app_rd_data[226]_INST_0\ : label is "soft_lutpair683";
  attribute SOFT_HLUTNM of \app_rd_data[227]_INST_0\ : label is "soft_lutpair689";
  attribute SOFT_HLUTNM of \app_rd_data[228]_INST_0\ : label is "soft_lutpair690";
  attribute SOFT_HLUTNM of \app_rd_data[229]_INST_0\ : label is "soft_lutpair680";
  attribute SOFT_HLUTNM of \app_rd_data[230]_INST_0\ : label is "soft_lutpair686";
  attribute SOFT_HLUTNM of \app_rd_data[231]_INST_0\ : label is "soft_lutpair677";
  attribute SOFT_HLUTNM of \app_rd_data[288]_INST_0\ : label is "soft_lutpair673";
  attribute SOFT_HLUTNM of \app_rd_data[289]_INST_0\ : label is "soft_lutpair668";
  attribute SOFT_HLUTNM of \app_rd_data[290]_INST_0\ : label is "soft_lutpair676";
  attribute SOFT_HLUTNM of \app_rd_data[291]_INST_0\ : label is "soft_lutpair669";
  attribute SOFT_HLUTNM of \app_rd_data[292]_INST_0\ : label is "soft_lutpair666";
  attribute SOFT_HLUTNM of \app_rd_data[293]_INST_0\ : label is "soft_lutpair675";
  attribute SOFT_HLUTNM of \app_rd_data[294]_INST_0\ : label is "soft_lutpair670";
  attribute SOFT_HLUTNM of \app_rd_data[295]_INST_0\ : label is "soft_lutpair674";
  attribute SOFT_HLUTNM of \app_rd_data[32]_INST_0\ : label is "soft_lutpair669";
  attribute SOFT_HLUTNM of \app_rd_data[33]_INST_0\ : label is "soft_lutpair662";
  attribute SOFT_HLUTNM of \app_rd_data[34]_INST_0\ : label is "soft_lutpair672";
  attribute SOFT_HLUTNM of \app_rd_data[352]_INST_0\ : label is "soft_lutpair693";
  attribute SOFT_HLUTNM of \app_rd_data[353]_INST_0\ : label is "soft_lutpair683";
  attribute SOFT_HLUTNM of \app_rd_data[354]_INST_0\ : label is "soft_lutpair691";
  attribute SOFT_HLUTNM of \app_rd_data[355]_INST_0\ : label is "soft_lutpair688";
  attribute SOFT_HLUTNM of \app_rd_data[356]_INST_0\ : label is "soft_lutpair681";
  attribute SOFT_HLUTNM of \app_rd_data[357]_INST_0\ : label is "soft_lutpair680";
  attribute SOFT_HLUTNM of \app_rd_data[358]_INST_0\ : label is "soft_lutpair686";
  attribute SOFT_HLUTNM of \app_rd_data[359]_INST_0\ : label is "soft_lutpair685";
  attribute SOFT_HLUTNM of \app_rd_data[35]_INST_0\ : label is "soft_lutpair667";
  attribute SOFT_HLUTNM of \app_rd_data[36]_INST_0\ : label is "soft_lutpair664";
  attribute SOFT_HLUTNM of \app_rd_data[37]_INST_0\ : label is "soft_lutpair664";
  attribute SOFT_HLUTNM of \app_rd_data[38]_INST_0\ : label is "soft_lutpair663";
  attribute SOFT_HLUTNM of \app_rd_data[39]_INST_0\ : label is "soft_lutpair663";
  attribute SOFT_HLUTNM of \app_rd_data[416]_INST_0\ : label is "soft_lutpair668";
  attribute SOFT_HLUTNM of \app_rd_data[417]_INST_0\ : label is "soft_lutpair678";
  attribute SOFT_HLUTNM of \app_rd_data[418]_INST_0\ : label is "soft_lutpair672";
  attribute SOFT_HLUTNM of \app_rd_data[419]_INST_0\ : label is "soft_lutpair662";
  attribute SOFT_HLUTNM of \app_rd_data[420]_INST_0\ : label is "soft_lutpair675";
  attribute SOFT_HLUTNM of \app_rd_data[421]_INST_0\ : label is "soft_lutpair671";
  attribute SOFT_HLUTNM of \app_rd_data[422]_INST_0\ : label is "soft_lutpair665";
  attribute SOFT_HLUTNM of \app_rd_data[423]_INST_0\ : label is "soft_lutpair670";
  attribute SOFT_HLUTNM of \app_rd_data[480]_INST_0\ : label is "soft_lutpair684";
  attribute SOFT_HLUTNM of \app_rd_data[481]_INST_0\ : label is "soft_lutpair689";
  attribute SOFT_HLUTNM of \app_rd_data[482]_INST_0\ : label is "soft_lutpair691";
  attribute SOFT_HLUTNM of \app_rd_data[483]_INST_0\ : label is "soft_lutpair682";
  attribute SOFT_HLUTNM of \app_rd_data[484]_INST_0\ : label is "soft_lutpair687";
  attribute SOFT_HLUTNM of \app_rd_data[485]_INST_0\ : label is "soft_lutpair679";
  attribute SOFT_HLUTNM of \app_rd_data[486]_INST_0\ : label is "soft_lutpair679";
  attribute SOFT_HLUTNM of \app_rd_data[487]_INST_0\ : label is "soft_lutpair681";
  attribute SOFT_HLUTNM of \app_rd_data[96]_INST_0\ : label is "soft_lutpair684";
  attribute SOFT_HLUTNM of \app_rd_data[97]_INST_0\ : label is "soft_lutpair692";
  attribute SOFT_HLUTNM of \app_rd_data[98]_INST_0\ : label is "soft_lutpair688";
  attribute SOFT_HLUTNM of \app_rd_data[99]_INST_0\ : label is "soft_lutpair682";
  attribute METHODOLOGY_DRC_VIOS : string;
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_3_12_17 : label is "";
  attribute RTL_RAM_BITS : integer;
  attribute RTL_RAM_BITS of mem_reg_0_3_12_17 : label is 320;
  attribute RTL_RAM_NAME : string;
  attribute RTL_RAM_NAME of mem_reg_0_3_12_17 : label is "dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem";
  attribute ram_addr_begin : integer;
  attribute ram_addr_begin of mem_reg_0_3_12_17 : label is 0;
  attribute ram_addr_end : integer;
  attribute ram_addr_end of mem_reg_0_3_12_17 : label is 3;
  attribute ram_offset : integer;
  attribute ram_offset of mem_reg_0_3_12_17 : label is 0;
  attribute ram_slice_begin : integer;
  attribute ram_slice_begin of mem_reg_0_3_12_17 : label is 12;
  attribute ram_slice_end : integer;
  attribute ram_slice_end of mem_reg_0_3_12_17 : label is 17;
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_3_18_23 : label is "";
  attribute RTL_RAM_BITS of mem_reg_0_3_18_23 : label is 320;
  attribute RTL_RAM_NAME of mem_reg_0_3_18_23 : label is "dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem";
  attribute ram_addr_begin of mem_reg_0_3_18_23 : label is 0;
  attribute ram_addr_end of mem_reg_0_3_18_23 : label is 3;
  attribute ram_offset of mem_reg_0_3_18_23 : label is 0;
  attribute ram_slice_begin of mem_reg_0_3_18_23 : label is 18;
  attribute ram_slice_end of mem_reg_0_3_18_23 : label is 23;
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_3_24_29 : label is "";
  attribute RTL_RAM_BITS of mem_reg_0_3_24_29 : label is 320;
  attribute RTL_RAM_NAME of mem_reg_0_3_24_29 : label is "dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem";
  attribute ram_addr_begin of mem_reg_0_3_24_29 : label is 0;
  attribute ram_addr_end of mem_reg_0_3_24_29 : label is 3;
  attribute ram_offset of mem_reg_0_3_24_29 : label is 0;
  attribute ram_slice_begin of mem_reg_0_3_24_29 : label is 24;
  attribute ram_slice_end of mem_reg_0_3_24_29 : label is 29;
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_3_30_35 : label is "";
  attribute RTL_RAM_BITS of mem_reg_0_3_30_35 : label is 320;
  attribute RTL_RAM_NAME of mem_reg_0_3_30_35 : label is "dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem";
  attribute ram_addr_begin of mem_reg_0_3_30_35 : label is 0;
  attribute ram_addr_end of mem_reg_0_3_30_35 : label is 3;
  attribute ram_offset of mem_reg_0_3_30_35 : label is 0;
  attribute ram_slice_begin of mem_reg_0_3_30_35 : label is 30;
  attribute ram_slice_end of mem_reg_0_3_30_35 : label is 35;
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_3_36_41 : label is "";
  attribute RTL_RAM_BITS of mem_reg_0_3_36_41 : label is 320;
  attribute RTL_RAM_NAME of mem_reg_0_3_36_41 : label is "dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem";
  attribute ram_addr_begin of mem_reg_0_3_36_41 : label is 0;
  attribute ram_addr_end of mem_reg_0_3_36_41 : label is 3;
  attribute ram_offset of mem_reg_0_3_36_41 : label is 0;
  attribute ram_slice_begin of mem_reg_0_3_36_41 : label is 36;
  attribute ram_slice_end of mem_reg_0_3_36_41 : label is 41;
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_3_42_47 : label is "";
  attribute RTL_RAM_BITS of mem_reg_0_3_42_47 : label is 320;
  attribute RTL_RAM_NAME of mem_reg_0_3_42_47 : label is "dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem";
  attribute ram_addr_begin of mem_reg_0_3_42_47 : label is 0;
  attribute ram_addr_end of mem_reg_0_3_42_47 : label is 3;
  attribute ram_offset of mem_reg_0_3_42_47 : label is 0;
  attribute ram_slice_begin of mem_reg_0_3_42_47 : label is 42;
  attribute ram_slice_end of mem_reg_0_3_42_47 : label is 47;
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_3_48_53 : label is "";
  attribute RTL_RAM_BITS of mem_reg_0_3_48_53 : label is 320;
  attribute RTL_RAM_NAME of mem_reg_0_3_48_53 : label is "dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem";
  attribute ram_addr_begin of mem_reg_0_3_48_53 : label is 0;
  attribute ram_addr_end of mem_reg_0_3_48_53 : label is 3;
  attribute ram_offset of mem_reg_0_3_48_53 : label is 0;
  attribute ram_slice_begin of mem_reg_0_3_48_53 : label is 48;
  attribute ram_slice_end of mem_reg_0_3_48_53 : label is 53;
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_3_54_59 : label is "";
  attribute RTL_RAM_BITS of mem_reg_0_3_54_59 : label is 320;
  attribute RTL_RAM_NAME of mem_reg_0_3_54_59 : label is "dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem";
  attribute ram_addr_begin of mem_reg_0_3_54_59 : label is 0;
  attribute ram_addr_end of mem_reg_0_3_54_59 : label is 3;
  attribute ram_offset of mem_reg_0_3_54_59 : label is 0;
  attribute ram_slice_begin of mem_reg_0_3_54_59 : label is 54;
  attribute ram_slice_end of mem_reg_0_3_54_59 : label is 59;
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_3_60_65 : label is "";
  attribute RTL_RAM_BITS of mem_reg_0_3_60_65 : label is 320;
  attribute RTL_RAM_NAME of mem_reg_0_3_60_65 : label is "dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem";
  attribute ram_addr_begin of mem_reg_0_3_60_65 : label is 0;
  attribute ram_addr_end of mem_reg_0_3_60_65 : label is 3;
  attribute ram_offset of mem_reg_0_3_60_65 : label is 0;
  attribute ram_slice_begin of mem_reg_0_3_60_65 : label is 60;
  attribute ram_slice_end of mem_reg_0_3_60_65 : label is 65;
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_3_6_11 : label is "";
  attribute RTL_RAM_BITS of mem_reg_0_3_6_11 : label is 320;
  attribute RTL_RAM_NAME of mem_reg_0_3_6_11 : label is "dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem";
  attribute ram_addr_begin of mem_reg_0_3_6_11 : label is 0;
  attribute ram_addr_end of mem_reg_0_3_6_11 : label is 3;
  attribute ram_offset of mem_reg_0_3_6_11 : label is 0;
  attribute ram_slice_begin of mem_reg_0_3_6_11 : label is 6;
  attribute ram_slice_end of mem_reg_0_3_6_11 : label is 11;
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_3_72_77 : label is "";
  attribute RTL_RAM_BITS of mem_reg_0_3_72_77 : label is 320;
  attribute RTL_RAM_NAME of mem_reg_0_3_72_77 : label is "dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem";
  attribute ram_addr_begin of mem_reg_0_3_72_77 : label is 0;
  attribute ram_addr_end of mem_reg_0_3_72_77 : label is 3;
  attribute ram_offset of mem_reg_0_3_72_77 : label is 0;
  attribute ram_slice_begin of mem_reg_0_3_72_77 : label is 72;
  attribute ram_slice_end of mem_reg_0_3_72_77 : label is 77;
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_3_78_79 : label is "";
  attribute RTL_RAM_BITS of mem_reg_0_3_78_79 : label is 320;
  attribute RTL_RAM_NAME of mem_reg_0_3_78_79 : label is "dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem";
  attribute ram_addr_begin of mem_reg_0_3_78_79 : label is 0;
  attribute ram_addr_end of mem_reg_0_3_78_79 : label is 3;
  attribute ram_offset of mem_reg_0_3_78_79 : label is 0;
  attribute ram_slice_begin of mem_reg_0_3_78_79 : label is 78;
  attribute ram_slice_end of mem_reg_0_3_78_79 : label is 79;
  attribute SOFT_HLUTNM of \my_empty_inst__0\ : label is "soft_lutpair694";
  attribute SOFT_HLUTNM of \my_empty_inst__2\ : label is "soft_lutpair694";
  attribute IS_FANOUT_CONSTRAINED : integer;
  attribute IS_FANOUT_CONSTRAINED of my_empty_inst_rep : label is 1;
  attribute ORIG_CELL_NAME : string;
  attribute ORIG_CELL_NAME of \my_empty_reg[4]\ : label is "my_empty_reg[4]";
  attribute ORIG_CELL_NAME of \my_empty_reg[4]_rep\ : label is "my_empty_reg[4]";
  attribute ORIG_CELL_NAME of \my_empty_reg[4]_rep__0\ : label is "my_empty_reg[4]";
  attribute SOFT_HLUTNM of \rd_ptr[0]_i_1\ : label is "soft_lutpair661";
  attribute SOFT_HLUTNM of \rd_ptr[1]_i_1\ : label is "soft_lutpair661";
  attribute syn_maxfan of \rd_ptr_reg[0]\ : label is "10";
  attribute syn_maxfan of \rd_ptr_reg[1]\ : label is "10";
  attribute KEEP : string;
  attribute KEEP of \rd_ptr_timing_reg[0]\ : label is "yes";
  attribute syn_maxfan of \rd_ptr_timing_reg[0]\ : label is "10";
  attribute KEEP of \rd_ptr_timing_reg[1]\ : label is "yes";
  attribute syn_maxfan of \rd_ptr_timing_reg[1]\ : label is "10";
  attribute SOFT_HLUTNM of \wr_ptr[1]_i_3\ : label is "soft_lutpair660";
  attribute SOFT_HLUTNM of \wr_ptr[1]_i_8\ : label is "soft_lutpair660";
  attribute syn_maxfan of \wr_ptr_reg[0]\ : label is "10";
  attribute syn_maxfan of \wr_ptr_reg[1]\ : label is "10";
begin
  if_empty <= \^if_empty\;
\app_rd_data[100]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(35),
      I1 => my_empty_1(4),
      I2 => mem_out(41),
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]\
    );
\app_rd_data[101]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(43),
      I1 => my_empty_1(4),
      I2 => mem_out(49),
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]\
    );
\app_rd_data[102]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(51),
      I1 => my_empty_1(4),
      I2 => mem_out(57),
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]\
    );
\app_rd_data[103]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(61),
      I1 => my_empty_1(4),
      I2 => mem_out(73),
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]\
    );
\app_rd_data[160]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(4),
      I1 => my_empty_inst_rep_n_0,
      I2 => mem_out(10),
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]\
    );
\app_rd_data[161]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(12),
      I1 => my_empty_inst_rep_n_0,
      I2 => mem_out(18),
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]\
    );
\app_rd_data[162]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(20),
      I1 => my_empty_inst_rep_n_0,
      I2 => mem_out(26),
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]\
    );
\app_rd_data[163]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(28),
      I1 => my_empty_inst_rep_n_0,
      I2 => mem_out(34),
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]\
    );
\app_rd_data[164]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(36),
      I1 => my_empty_1(4),
      I2 => mem_out(42),
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]\
    );
\app_rd_data[165]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(44),
      I1 => my_empty_1(4),
      I2 => mem_out(50),
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]\
    );
\app_rd_data[166]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(52),
      I1 => my_empty_1(4),
      I2 => mem_out(58),
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]\
    );
\app_rd_data[167]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(62),
      I1 => my_empty_1(4),
      I2 => mem_out(74),
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]\
    );
\app_rd_data[224]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(5),
      I1 => my_empty_inst_rep_n_0,
      I2 => mem_out(11),
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]\
    );
\app_rd_data[225]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(13),
      I1 => my_empty_inst_rep_n_0,
      I2 => mem_out(19),
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]\
    );
\app_rd_data[226]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(21),
      I1 => my_empty_inst_rep_n_0,
      I2 => mem_out(27),
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]\
    );
\app_rd_data[227]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(29),
      I1 => my_empty_inst_rep_n_0,
      I2 => mem_out(35),
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]\
    );
\app_rd_data[228]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(37),
      I1 => my_empty_1(4),
      I2 => mem_out(43),
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]\
    );
\app_rd_data[229]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(45),
      I1 => my_empty_1(4),
      I2 => mem_out(51),
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]\
    );
\app_rd_data[230]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(53),
      I1 => my_empty_1(4),
      I2 => mem_out(59),
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]\
    );
\app_rd_data[231]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(63),
      I1 => my_empty_1(4),
      I2 => mem_out(75),
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]\
    );
\app_rd_data[288]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(6),
      I1 => my_empty_inst_rep_n_0,
      I2 => mem_out(12),
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]\
    );
\app_rd_data[289]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(14),
      I1 => my_empty_inst_rep_n_0,
      I2 => mem_out(20),
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]\
    );
\app_rd_data[290]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(22),
      I1 => my_empty_inst_rep_n_0,
      I2 => mem_out(28),
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]\
    );
\app_rd_data[291]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(30),
      I1 => my_empty_inst_rep_n_0,
      I2 => mem_out(36),
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]\
    );
\app_rd_data[292]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(38),
      I1 => my_empty_1(4),
      I2 => mem_out(44),
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]\
    );
\app_rd_data[293]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(46),
      I1 => my_empty_1(4),
      I2 => mem_out(52),
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]\
    );
\app_rd_data[294]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(54),
      I1 => my_empty_1(4),
      I2 => mem_out(60),
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]\
    );
\app_rd_data[295]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(64),
      I1 => my_empty_1(4),
      I2 => mem_out(76),
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]\
    );
\app_rd_data[32]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(2),
      I1 => my_empty_inst_rep_n_0,
      I2 => mem_out(8),
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]\
    );
\app_rd_data[33]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(10),
      I1 => my_empty_inst_rep_n_0,
      I2 => mem_out(16),
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]\
    );
\app_rd_data[34]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(18),
      I1 => my_empty_inst_rep_n_0,
      I2 => mem_out(24),
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]\
    );
\app_rd_data[352]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(7),
      I1 => my_empty_inst_rep_n_0,
      I2 => mem_out(13),
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]\
    );
\app_rd_data[353]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(15),
      I1 => my_empty_inst_rep_n_0,
      I2 => mem_out(21),
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]\
    );
\app_rd_data[354]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(23),
      I1 => my_empty_inst_rep_n_0,
      I2 => mem_out(29),
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]\
    );
\app_rd_data[355]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(31),
      I1 => my_empty_inst_rep_n_0,
      I2 => mem_out(37),
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]\
    );
\app_rd_data[356]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(39),
      I1 => my_empty_1(4),
      I2 => mem_out(45),
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]\
    );
\app_rd_data[357]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(47),
      I1 => my_empty_1(4),
      I2 => mem_out(53),
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]\
    );
\app_rd_data[358]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(55),
      I1 => my_empty_1(4),
      I2 => mem_out(61),
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]\
    );
\app_rd_data[359]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(65),
      I1 => my_empty_1(4),
      I2 => mem_out(77),
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]\
    );
\app_rd_data[35]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(26),
      I1 => my_empty_inst_rep_n_0,
      I2 => mem_out(32),
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]\
    );
\app_rd_data[36]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(34),
      I1 => my_empty_1(4),
      I2 => mem_out(40),
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]\
    );
\app_rd_data[37]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(42),
      I1 => my_empty_1(4),
      I2 => mem_out(48),
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]\
    );
\app_rd_data[38]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(50),
      I1 => my_empty_1(4),
      I2 => mem_out(56),
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]\
    );
\app_rd_data[39]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(60),
      I1 => my_empty_1(4),
      I2 => mem_out(72),
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]\
    );
\app_rd_data[416]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(8),
      I1 => my_empty_inst_rep_n_0,
      I2 => mem_out(14),
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]\
    );
\app_rd_data[417]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(16),
      I1 => my_empty_inst_rep_n_0,
      I2 => mem_out(22),
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]\
    );
\app_rd_data[418]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(24),
      I1 => my_empty_inst_rep_n_0,
      I2 => mem_out(30),
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]\
    );
\app_rd_data[419]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(32),
      I1 => my_empty_inst_rep_n_0,
      I2 => mem_out(38),
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]\
    );
\app_rd_data[420]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(40),
      I1 => my_empty_1(4),
      I2 => mem_out(46),
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]\
    );
\app_rd_data[421]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(48),
      I1 => my_empty_1(4),
      I2 => mem_out(54),
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]\
    );
\app_rd_data[422]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(56),
      I1 => my_empty_1(4),
      I2 => mem_out(62),
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]\
    );
\app_rd_data[423]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(66),
      I1 => my_empty_1(4),
      I2 => mem_out(78),
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]\
    );
\app_rd_data[480]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(9),
      I1 => my_empty_inst_rep_n_0,
      I2 => mem_out(15),
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]\
    );
\app_rd_data[481]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(17),
      I1 => my_empty_inst_rep_n_0,
      I2 => mem_out(23),
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]\
    );
\app_rd_data[482]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(25),
      I1 => my_empty_inst_rep_n_0,
      I2 => mem_out(31),
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]\
    );
\app_rd_data[483]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(33),
      I1 => my_empty_inst_rep_n_0,
      I2 => mem_out(39),
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]\
    );
\app_rd_data[484]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(41),
      I1 => my_empty_1(4),
      I2 => mem_out(47),
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]\
    );
\app_rd_data[485]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(49),
      I1 => my_empty_1(4),
      I2 => mem_out(55),
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]\
    );
\app_rd_data[486]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(57),
      I1 => my_empty_1(4),
      I2 => mem_out(63),
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]\
    );
\app_rd_data[487]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(67),
      I1 => my_empty_1(4),
      I2 => mem_out(79),
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]\
    );
\app_rd_data[96]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(3),
      I1 => my_empty_inst_rep_n_0,
      I2 => mem_out(9),
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]\
    );
\app_rd_data[97]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(11),
      I1 => my_empty_inst_rep_n_0,
      I2 => mem_out(17),
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]\
    );
\app_rd_data[98]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(19),
      I1 => my_empty_inst_rep_n_0,
      I2 => mem_out(25),
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]\
    );
\app_rd_data[99]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(27),
      I1 => my_empty_inst_rep_n_0,
      I2 => mem_out(33),
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]\
    );
mem_reg_0_3_12_17: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 2) => B"000",
      ADDRA(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRB(4 downto 2) => B"000",
      ADDRB(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRC(4 downto 2) => B"000",
      ADDRC(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRD(4 downto 2) => B"000",
      ADDRD(1 downto 0) => wr_ptr(1 downto 0),
      DIA(1 downto 0) => Q(7 downto 6),
      DIB(1 downto 0) => Q(9 downto 8),
      DIC(1 downto 0) => Q(11 downto 10),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => mem_out(13 downto 12),
      DOB(1 downto 0) => mem_out(15 downto 14),
      DOC(1 downto 0) => mem_out(17 downto 16),
      DOD(1 downto 0) => NLW_mem_reg_0_3_12_17_DOD_UNCONNECTED(1 downto 0),
      WCLK => \rd_ptr_timing_reg[1]_0\,
      WE => wr_en
    );
mem_reg_0_3_18_23: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 2) => B"000",
      ADDRA(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRB(4 downto 2) => B"000",
      ADDRB(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRC(4 downto 2) => B"000",
      ADDRC(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRD(4 downto 2) => B"000",
      ADDRD(1 downto 0) => wr_ptr(1 downto 0),
      DIA(1 downto 0) => Q(13 downto 12),
      DIB(1 downto 0) => Q(15 downto 14),
      DIC(1 downto 0) => Q(17 downto 16),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => mem_out(19 downto 18),
      DOB(1 downto 0) => mem_out(21 downto 20),
      DOC(1 downto 0) => mem_out(23 downto 22),
      DOD(1 downto 0) => NLW_mem_reg_0_3_18_23_DOD_UNCONNECTED(1 downto 0),
      WCLK => \rd_ptr_timing_reg[1]_0\,
      WE => wr_en
    );
mem_reg_0_3_24_29: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 2) => B"000",
      ADDRA(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRB(4 downto 2) => B"000",
      ADDRB(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRC(4 downto 2) => B"000",
      ADDRC(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRD(4 downto 2) => B"000",
      ADDRD(1 downto 0) => wr_ptr(1 downto 0),
      DIA(1 downto 0) => Q(19 downto 18),
      DIB(1 downto 0) => Q(21 downto 20),
      DIC(1 downto 0) => Q(23 downto 22),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => mem_out(25 downto 24),
      DOB(1 downto 0) => mem_out(27 downto 26),
      DOC(1 downto 0) => mem_out(29 downto 28),
      DOD(1 downto 0) => NLW_mem_reg_0_3_24_29_DOD_UNCONNECTED(1 downto 0),
      WCLK => \rd_ptr_timing_reg[1]_0\,
      WE => wr_en
    );
mem_reg_0_3_30_35: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 2) => B"000",
      ADDRA(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRB(4 downto 2) => B"000",
      ADDRB(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRC(4 downto 2) => B"000",
      ADDRC(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRD(4 downto 2) => B"000",
      ADDRD(1 downto 0) => wr_ptr(1 downto 0),
      DIA(1 downto 0) => Q(25 downto 24),
      DIB(1 downto 0) => Q(27 downto 26),
      DIC(1 downto 0) => Q(29 downto 28),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => mem_out(31 downto 30),
      DOB(1 downto 0) => mem_out(33 downto 32),
      DOC(1 downto 0) => mem_out(35 downto 34),
      DOD(1 downto 0) => NLW_mem_reg_0_3_30_35_DOD_UNCONNECTED(1 downto 0),
      WCLK => \rd_ptr_timing_reg[1]_0\,
      WE => wr_en
    );
mem_reg_0_3_36_41: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 2) => B"000",
      ADDRA(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRB(4 downto 2) => B"000",
      ADDRB(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRC(4 downto 2) => B"000",
      ADDRC(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRD(4 downto 2) => B"000",
      ADDRD(1 downto 0) => wr_ptr(1 downto 0),
      DIA(1 downto 0) => Q(31 downto 30),
      DIB(1 downto 0) => Q(33 downto 32),
      DIC(1 downto 0) => Q(35 downto 34),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => mem_out(37 downto 36),
      DOB(1 downto 0) => mem_out(39 downto 38),
      DOC(1 downto 0) => mem_out(41 downto 40),
      DOD(1 downto 0) => NLW_mem_reg_0_3_36_41_DOD_UNCONNECTED(1 downto 0),
      WCLK => \rd_ptr_timing_reg[1]_0\,
      WE => wr_en
    );
mem_reg_0_3_42_47: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 2) => B"000",
      ADDRA(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRB(4 downto 2) => B"000",
      ADDRB(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRC(4 downto 2) => B"000",
      ADDRC(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRD(4 downto 2) => B"000",
      ADDRD(1 downto 0) => wr_ptr(1 downto 0),
      DIA(1 downto 0) => Q(37 downto 36),
      DIB(1 downto 0) => Q(39 downto 38),
      DIC(1 downto 0) => Q(41 downto 40),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => mem_out(43 downto 42),
      DOB(1 downto 0) => mem_out(45 downto 44),
      DOC(1 downto 0) => mem_out(47 downto 46),
      DOD(1 downto 0) => NLW_mem_reg_0_3_42_47_DOD_UNCONNECTED(1 downto 0),
      WCLK => \rd_ptr_timing_reg[1]_0\,
      WE => wr_en
    );
mem_reg_0_3_48_53: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 2) => B"000",
      ADDRA(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRB(4 downto 2) => B"000",
      ADDRB(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRC(4 downto 2) => B"000",
      ADDRC(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRD(4 downto 2) => B"000",
      ADDRD(1 downto 0) => wr_ptr(1 downto 0),
      DIA(1 downto 0) => Q(43 downto 42),
      DIB(1 downto 0) => Q(45 downto 44),
      DIC(1 downto 0) => Q(47 downto 46),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => mem_out(49 downto 48),
      DOB(1 downto 0) => mem_out(51 downto 50),
      DOC(1 downto 0) => mem_out(53 downto 52),
      DOD(1 downto 0) => NLW_mem_reg_0_3_48_53_DOD_UNCONNECTED(1 downto 0),
      WCLK => \rd_ptr_timing_reg[1]_0\,
      WE => wr_en
    );
mem_reg_0_3_54_59: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 2) => B"000",
      ADDRA(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRB(4 downto 2) => B"000",
      ADDRB(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRC(4 downto 2) => B"000",
      ADDRC(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRD(4 downto 2) => B"000",
      ADDRD(1 downto 0) => wr_ptr(1 downto 0),
      DIA(1 downto 0) => Q(49 downto 48),
      DIB(1 downto 0) => Q(51 downto 50),
      DIC(1 downto 0) => Q(53 downto 52),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => mem_out(55 downto 54),
      DOB(1 downto 0) => mem_out(57 downto 56),
      DOC(1 downto 0) => mem_out(59 downto 58),
      DOD(1 downto 0) => NLW_mem_reg_0_3_54_59_DOD_UNCONNECTED(1 downto 0),
      WCLK => \rd_ptr_timing_reg[1]_0\,
      WE => wr_en
    );
mem_reg_0_3_60_65: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 2) => B"000",
      ADDRA(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRB(4 downto 2) => B"000",
      ADDRB(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRC(4 downto 2) => B"000",
      ADDRC(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRD(4 downto 2) => B"000",
      ADDRD(1 downto 0) => wr_ptr(1 downto 0),
      DIA(1 downto 0) => Q(55 downto 54),
      DIB(1 downto 0) => Q(57 downto 56),
      DIC(1 downto 0) => Q(59 downto 58),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => mem_out(61 downto 60),
      DOB(1 downto 0) => mem_out(63 downto 62),
      DOC(1) => mem_reg_0_3_60_65_n_4,
      DOC(0) => mem_reg_0_3_60_65_n_5,
      DOD(1 downto 0) => NLW_mem_reg_0_3_60_65_DOD_UNCONNECTED(1 downto 0),
      WCLK => \rd_ptr_timing_reg[1]_0\,
      WE => wr_en
    );
mem_reg_0_3_6_11: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 2) => B"000",
      ADDRA(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRB(4 downto 2) => B"000",
      ADDRB(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRC(4 downto 2) => B"000",
      ADDRC(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRD(4 downto 2) => B"000",
      ADDRD(1 downto 0) => wr_ptr(1 downto 0),
      DIA(1 downto 0) => Q(1 downto 0),
      DIB(1 downto 0) => Q(3 downto 2),
      DIC(1 downto 0) => Q(5 downto 4),
      DID(1 downto 0) => B"00",
      DOA(1) => mem_reg_0_3_6_11_n_0,
      DOA(0) => mem_reg_0_3_6_11_n_1,
      DOB(1 downto 0) => mem_out(9 downto 8),
      DOC(1 downto 0) => mem_out(11 downto 10),
      DOD(1 downto 0) => NLW_mem_reg_0_3_6_11_DOD_UNCONNECTED(1 downto 0),
      WCLK => \rd_ptr_timing_reg[1]_0\,
      WE => wr_en
    );
\mem_reg_0_3_6_11_i_1__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0151"
    )
        port map (
      I0 => if_empty_r_0(0),
      I1 => my_full(0),
      I2 => \my_full_reg[1]_0\,
      I3 => my_empty_1(2),
      O => wr_en
    );
mem_reg_0_3_72_77: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 2) => B"000",
      ADDRA(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRB(4 downto 2) => B"000",
      ADDRB(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRC(4 downto 2) => B"000",
      ADDRC(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRD(4 downto 2) => B"000",
      ADDRD(1 downto 0) => wr_ptr(1 downto 0),
      DIA(1 downto 0) => Q(61 downto 60),
      DIB(1 downto 0) => Q(63 downto 62),
      DIC(1 downto 0) => Q(65 downto 64),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => mem_out(73 downto 72),
      DOB(1 downto 0) => mem_out(75 downto 74),
      DOC(1 downto 0) => mem_out(77 downto 76),
      DOD(1 downto 0) => NLW_mem_reg_0_3_72_77_DOD_UNCONNECTED(1 downto 0),
      WCLK => \rd_ptr_timing_reg[1]_0\,
      WE => wr_en
    );
mem_reg_0_3_78_79: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 2) => B"000",
      ADDRA(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRB(4 downto 2) => B"000",
      ADDRB(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRC(4 downto 2) => B"000",
      ADDRC(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRD(4 downto 2) => B"000",
      ADDRD(1 downto 0) => wr_ptr(1 downto 0),
      DIA(1 downto 0) => Q(67 downto 66),
      DIB(1 downto 0) => B"00",
      DIC(1 downto 0) => B"00",
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => mem_out(79 downto 78),
      DOB(1 downto 0) => NLW_mem_reg_0_3_78_79_DOB_UNCONNECTED(1 downto 0),
      DOC(1 downto 0) => NLW_mem_reg_0_3_78_79_DOC_UNCONNECTED(1 downto 0),
      DOD(1 downto 0) => NLW_mem_reg_0_3_78_79_DOD_UNCONNECTED(1 downto 0),
      WCLK => \rd_ptr_timing_reg[1]_0\,
      WE => wr_en
    );
\my_empty[4]_i_1__3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0018"
    )
        port map (
      I0 => \my_full_reg[1]_0\,
      I1 => if_empty_r_0(0),
      I2 => my_empty_1(1),
      I3 => my_full(1),
      O => \my_empty[4]_i_1__3_n_0\
    );
\my_empty[4]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00411400"
    )
        port map (
      I0 => my_empty_1(1),
      I1 => wr_ptr(1),
      I2 => rd_ptr(1),
      I3 => rd_ptr(0),
      I4 => wr_ptr(0),
      O => \my_empty[4]_i_2_n_0\
    );
my_empty_inst: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \my_empty_reg[4]_rep_n_0\,
      O => my_empty_1(4)
    );
\my_empty_inst__0\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => my_empty_1(0),
      O => my_empty_1(3)
    );
\my_empty_inst__1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => my_empty_1(0),
      O => my_empty_1(2)
    );
\my_empty_inst__2\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => my_empty_1(0),
      O => my_empty_1(1)
    );
my_empty_inst_rep: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \my_empty_reg[4]_rep__0_n_0\,
      O => my_empty_inst_rep_n_0
    );
\my_empty_reg[4]\: unisim.vcomponents.FDSE
     port map (
      C => \rd_ptr_timing_reg[1]_0\,
      CE => \my_empty[4]_i_1__3_n_0\,
      D => \my_empty[4]_i_2_n_0\,
      Q => my_empty_1(0),
      S => ififo_rst
    );
\my_empty_reg[4]_rep\: unisim.vcomponents.FDSE
     port map (
      C => \rd_ptr_timing_reg[1]_0\,
      CE => \my_empty[4]_i_1__3_n_0\,
      D => \my_empty[4]_i_2_n_0\,
      Q => \my_empty_reg[4]_rep_n_0\,
      S => ififo_rst
    );
\my_empty_reg[4]_rep__0\: unisim.vcomponents.FDSE
     port map (
      C => \rd_ptr_timing_reg[1]_0\,
      CE => \my_empty[4]_i_1__3_n_0\,
      D => \my_empty[4]_i_2_n_0\,
      Q => \my_empty_reg[4]_rep__0_n_0\,
      S => ififo_rst
    );
\my_full[0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAEAABAAAA2AA8"
    )
        port map (
      I0 => my_full(0),
      I1 => \my_full_reg[1]_0\,
      I2 => if_empty_r_0(0),
      I3 => my_full(1),
      I4 => my_empty_1(1),
      I5 => \my_full[1]_i_2_n_0\,
      O => \my_full[0]_i_1_n_0\
    );
\my_full[1]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"F0F1F070"
    )
        port map (
      I0 => \my_full_reg[1]_0\,
      I1 => if_empty_r_0(0),
      I2 => my_full(1),
      I3 => my_empty_1(1),
      I4 => \my_full[1]_i_2_n_0\,
      O => \my_full[1]_i_1_n_0\
    );
\my_full[1]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00411400"
    )
        port map (
      I0 => my_full(1),
      I1 => rd_ptr(1),
      I2 => wr_ptr(1),
      I3 => wr_ptr(0),
      I4 => rd_ptr(0),
      O => \my_full[1]_i_2_n_0\
    );
\my_full_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \rd_ptr_timing_reg[1]_0\,
      CE => '1',
      D => \my_full[0]_i_1_n_0\,
      Q => my_full(0),
      R => ififo_rst
    );
\my_full_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \rd_ptr_timing_reg[1]_0\,
      CE => '1',
      D => \my_full[1]_i_1_n_0\,
      Q => my_full(1),
      R => ififo_rst
    );
phy_if_empty_r_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFEAEAEA"
    )
        port map (
      I0 => phy_if_empty_r_reg,
      I1 => if_empty_r_0(0),
      I2 => my_empty_1(0),
      I3 => if_empty_r(0),
      I4 => my_empty(0),
      I5 => if_empty_v(0),
      O => \^if_empty\
    );
rd_active_r_i_1: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \^if_empty\,
      O => phy_rddata_en
    );
\rd_ptr[0]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"D2"
    )
        port map (
      I0 => \my_full_reg[1]_0\,
      I1 => my_empty_1(1),
      I2 => rd_ptr(0),
      O => \rd_ptr[0]_i_1_n_0\
    );
\rd_ptr[1]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F708"
    )
        port map (
      I0 => rd_ptr(0),
      I1 => \my_full_reg[1]_0\,
      I2 => my_empty_1(1),
      I3 => rd_ptr(1),
      O => \rd_ptr[1]_i_1_n_0\
    );
\rd_ptr_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \rd_ptr_timing_reg[1]_0\,
      CE => '1',
      D => \rd_ptr[0]_i_1_n_0\,
      Q => rd_ptr(0),
      R => ififo_rst
    );
\rd_ptr_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \rd_ptr_timing_reg[1]_0\,
      CE => '1',
      D => \rd_ptr[1]_i_1_n_0\,
      Q => rd_ptr(1),
      R => ififo_rst
    );
\rd_ptr_timing[0]_i_1__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F704"
    )
        port map (
      I0 => rd_ptr(0),
      I1 => \my_full_reg[1]_0\,
      I2 => my_empty_1(1),
      I3 => rd_ptr_timing(0),
      O => \rd_ptr_timing[0]_i_1__0_n_0\
    );
\rd_ptr_timing[1]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FF6F0060"
    )
        port map (
      I0 => rd_ptr(0),
      I1 => rd_ptr(1),
      I2 => \my_full_reg[1]_0\,
      I3 => my_empty_1(1),
      I4 => rd_ptr_timing(1),
      O => \rd_ptr_timing[1]_i_1__0_n_0\
    );
\rd_ptr_timing_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \rd_ptr_timing_reg[1]_0\,
      CE => '1',
      D => \rd_ptr_timing[0]_i_1__0_n_0\,
      Q => rd_ptr_timing(0),
      R => ififo_rst
    );
\rd_ptr_timing_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \rd_ptr_timing_reg[1]_0\,
      CE => '1',
      D => \rd_ptr_timing[1]_i_1__0_n_0\,
      Q => rd_ptr_timing(1),
      R => ififo_rst
    );
\wr_ptr[0]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FECE0131"
    )
        port map (
      I0 => my_full(1),
      I1 => if_empty_r_0(0),
      I2 => \my_full_reg[1]_0\,
      I3 => my_empty_1(1),
      I4 => wr_ptr(0),
      O => \wr_ptr[0]_i_1__0_n_0\
    );
\wr_ptr[1]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFDF5FD00020A02"
    )
        port map (
      I0 => wr_ptr(0),
      I1 => my_full(1),
      I2 => if_empty_r_0(0),
      I3 => \my_full_reg[1]_0\,
      I4 => my_empty_1(1),
      I5 => wr_ptr(1),
      O => \wr_ptr[1]_i_1__0_n_0\
    );
\wr_ptr[1]_i_3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => if_empty_r_0(0),
      I1 => my_empty_1(3),
      O => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1\
    );
\wr_ptr[1]_i_5__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F888"
    )
        port map (
      I0 => my_empty_1(3),
      I1 => if_empty_r_0(0),
      I2 => my_empty(1),
      I3 => if_empty_r(0),
      O => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]\
    );
\wr_ptr[1]_i_8\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F888"
    )
        port map (
      I0 => my_empty_1(3),
      I1 => if_empty_r_0(0),
      I2 => my_empty_0(0),
      I3 => \wr_ptr[1]_i_2\,
      O => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0\
    );
\wr_ptr_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \rd_ptr_timing_reg[1]_0\,
      CE => '1',
      D => \wr_ptr[0]_i_1__0_n_0\,
      Q => wr_ptr(0),
      R => ififo_rst
    );
\wr_ptr_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \rd_ptr_timing_reg[1]_0\,
      CE => '1',
      D => \wr_ptr[1]_i_1__0_n_0\,
      Q => wr_ptr(1),
      R => ififo_rst
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mig_mig_7series_v4_2_ddr_of_pre_fifo is
  port (
    SR : in STD_LOGIC_VECTOR ( 0 to 0 );
    \rd_ptr_timing_reg[0]_0\ : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of mig_mig_7series_v4_2_ddr_of_pre_fifo : entity is "mig_7series_v4_2_ddr_of_pre_fifo";
end mig_mig_7series_v4_2_ddr_of_pre_fifo;

architecture STRUCTURE of mig_mig_7series_v4_2_ddr_of_pre_fifo is
  signal rd_ptr_timing : STD_LOGIC_VECTOR ( 2 downto 0 );
  attribute MAX_FANOUT : string;
  attribute MAX_FANOUT of rd_ptr_timing : signal is "50";
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of rd_ptr_timing : signal is "true";
  attribute RTL_MAX_FANOUT : string;
  attribute RTL_MAX_FANOUT of rd_ptr_timing : signal is "found";
  attribute syn_maxfan : string;
  attribute syn_maxfan of rd_ptr_timing : signal is "10";
  signal wr_en : STD_LOGIC;
  attribute MAX_FANOUT of wr_en : signal is "50";
  attribute RTL_MAX_FANOUT of wr_en : signal is "found";
  signal wr_ptr_timing : STD_LOGIC_VECTOR ( 2 downto 0 );
  attribute MAX_FANOUT of wr_ptr_timing : signal is "50";
  attribute RTL_KEEP of wr_ptr_timing : signal is "true";
  attribute RTL_MAX_FANOUT of wr_ptr_timing : signal is "found";
  attribute syn_maxfan of wr_ptr_timing : signal is "10";
  attribute KEEP : string;
  attribute KEEP of \rd_ptr_timing_reg[0]\ : label is "yes";
  attribute RTL_MAX_FANOUT of \rd_ptr_timing_reg[0]\ : label is "found";
  attribute syn_maxfan of \rd_ptr_timing_reg[0]\ : label is "10";
  attribute KEEP of \rd_ptr_timing_reg[1]\ : label is "yes";
  attribute RTL_MAX_FANOUT of \rd_ptr_timing_reg[1]\ : label is "found";
  attribute syn_maxfan of \rd_ptr_timing_reg[1]\ : label is "10";
  attribute KEEP of \rd_ptr_timing_reg[2]\ : label is "yes";
  attribute RTL_MAX_FANOUT of \rd_ptr_timing_reg[2]\ : label is "found";
  attribute syn_maxfan of \rd_ptr_timing_reg[2]\ : label is "10";
  attribute KEEP of \wr_ptr_timing_reg[0]\ : label is "yes";
  attribute RTL_MAX_FANOUT of \wr_ptr_timing_reg[0]\ : label is "found";
  attribute syn_maxfan of \wr_ptr_timing_reg[0]\ : label is "10";
  attribute KEEP of \wr_ptr_timing_reg[1]\ : label is "yes";
  attribute RTL_MAX_FANOUT of \wr_ptr_timing_reg[1]\ : label is "found";
  attribute syn_maxfan of \wr_ptr_timing_reg[1]\ : label is "10";
  attribute KEEP of \wr_ptr_timing_reg[2]\ : label is "yes";
  attribute RTL_MAX_FANOUT of \wr_ptr_timing_reg[2]\ : label is "found";
  attribute syn_maxfan of \wr_ptr_timing_reg[2]\ : label is "10";
begin
i_0: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => wr_en
    );
\rd_ptr_timing_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \rd_ptr_timing_reg[0]_0\,
      CE => '0',
      D => '1',
      Q => rd_ptr_timing(0),
      R => SR(0)
    );
\rd_ptr_timing_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \rd_ptr_timing_reg[0]_0\,
      CE => '0',
      D => '0',
      Q => rd_ptr_timing(1),
      R => SR(0)
    );
\rd_ptr_timing_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \rd_ptr_timing_reg[0]_0\,
      CE => '0',
      D => '0',
      Q => rd_ptr_timing(2),
      R => SR(0)
    );
\wr_ptr_timing_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \rd_ptr_timing_reg[0]_0\,
      CE => '0',
      D => '1',
      Q => wr_ptr_timing(0),
      R => SR(0)
    );
\wr_ptr_timing_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \rd_ptr_timing_reg[0]_0\,
      CE => '0',
      D => '0',
      Q => wr_ptr_timing(1),
      R => SR(0)
    );
\wr_ptr_timing_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \rd_ptr_timing_reg[0]_0\,
      CE => '0',
      D => '0',
      Q => wr_ptr_timing(2),
      R => SR(0)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \mig_mig_7series_v4_2_ddr_of_pre_fifo__parameterized0\ is
  port (
    SR : in STD_LOGIC_VECTOR ( 0 to 0 );
    \rd_ptr_timing_reg[0]_0\ : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \mig_mig_7series_v4_2_ddr_of_pre_fifo__parameterized0\ : entity is "mig_7series_v4_2_ddr_of_pre_fifo";
end \mig_mig_7series_v4_2_ddr_of_pre_fifo__parameterized0\;

architecture STRUCTURE of \mig_mig_7series_v4_2_ddr_of_pre_fifo__parameterized0\ is
  signal rd_ptr_timing : STD_LOGIC_VECTOR ( 2 downto 0 );
  attribute MAX_FANOUT : string;
  attribute MAX_FANOUT of rd_ptr_timing : signal is "50";
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of rd_ptr_timing : signal is "true";
  attribute RTL_MAX_FANOUT : string;
  attribute RTL_MAX_FANOUT of rd_ptr_timing : signal is "found";
  attribute syn_maxfan : string;
  attribute syn_maxfan of rd_ptr_timing : signal is "10";
  signal wr_en : STD_LOGIC;
  attribute MAX_FANOUT of wr_en : signal is "50";
  attribute RTL_MAX_FANOUT of wr_en : signal is "found";
  signal wr_ptr_timing : STD_LOGIC_VECTOR ( 2 downto 0 );
  attribute MAX_FANOUT of wr_ptr_timing : signal is "50";
  attribute RTL_KEEP of wr_ptr_timing : signal is "true";
  attribute RTL_MAX_FANOUT of wr_ptr_timing : signal is "found";
  attribute syn_maxfan of wr_ptr_timing : signal is "10";
  attribute KEEP : string;
  attribute KEEP of \rd_ptr_timing_reg[0]\ : label is "yes";
  attribute RTL_MAX_FANOUT of \rd_ptr_timing_reg[0]\ : label is "found";
  attribute syn_maxfan of \rd_ptr_timing_reg[0]\ : label is "10";
  attribute KEEP of \rd_ptr_timing_reg[1]\ : label is "yes";
  attribute RTL_MAX_FANOUT of \rd_ptr_timing_reg[1]\ : label is "found";
  attribute syn_maxfan of \rd_ptr_timing_reg[1]\ : label is "10";
  attribute KEEP of \rd_ptr_timing_reg[2]\ : label is "yes";
  attribute RTL_MAX_FANOUT of \rd_ptr_timing_reg[2]\ : label is "found";
  attribute syn_maxfan of \rd_ptr_timing_reg[2]\ : label is "10";
  attribute KEEP of \wr_ptr_timing_reg[0]\ : label is "yes";
  attribute RTL_MAX_FANOUT of \wr_ptr_timing_reg[0]\ : label is "found";
  attribute syn_maxfan of \wr_ptr_timing_reg[0]\ : label is "10";
  attribute KEEP of \wr_ptr_timing_reg[1]\ : label is "yes";
  attribute RTL_MAX_FANOUT of \wr_ptr_timing_reg[1]\ : label is "found";
  attribute syn_maxfan of \wr_ptr_timing_reg[1]\ : label is "10";
  attribute KEEP of \wr_ptr_timing_reg[2]\ : label is "yes";
  attribute RTL_MAX_FANOUT of \wr_ptr_timing_reg[2]\ : label is "found";
  attribute syn_maxfan of \wr_ptr_timing_reg[2]\ : label is "10";
begin
i_0: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => wr_en
    );
\rd_ptr_timing_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \rd_ptr_timing_reg[0]_0\,
      CE => '0',
      D => '1',
      Q => rd_ptr_timing(0),
      R => SR(0)
    );
\rd_ptr_timing_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \rd_ptr_timing_reg[0]_0\,
      CE => '0',
      D => '0',
      Q => rd_ptr_timing(1),
      R => SR(0)
    );
\rd_ptr_timing_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \rd_ptr_timing_reg[0]_0\,
      CE => '0',
      D => '0',
      Q => rd_ptr_timing(2),
      R => SR(0)
    );
\wr_ptr_timing_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \rd_ptr_timing_reg[0]_0\,
      CE => '0',
      D => '1',
      Q => wr_ptr_timing(0),
      R => SR(0)
    );
\wr_ptr_timing_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \rd_ptr_timing_reg[0]_0\,
      CE => '0',
      D => '0',
      Q => wr_ptr_timing(1),
      R => SR(0)
    );
\wr_ptr_timing_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \rd_ptr_timing_reg[0]_0\,
      CE => '0',
      D => '0',
      Q => wr_ptr_timing(2),
      R => SR(0)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \mig_mig_7series_v4_2_ddr_of_pre_fifo__parameterized0_12\ is
  port (
    SR : in STD_LOGIC_VECTOR ( 0 to 0 );
    \rd_ptr_timing_reg[0]_0\ : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \mig_mig_7series_v4_2_ddr_of_pre_fifo__parameterized0_12\ : entity is "mig_7series_v4_2_ddr_of_pre_fifo";
end \mig_mig_7series_v4_2_ddr_of_pre_fifo__parameterized0_12\;

architecture STRUCTURE of \mig_mig_7series_v4_2_ddr_of_pre_fifo__parameterized0_12\ is
  signal rd_ptr_timing : STD_LOGIC_VECTOR ( 2 downto 0 );
  attribute MAX_FANOUT : string;
  attribute MAX_FANOUT of rd_ptr_timing : signal is "50";
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of rd_ptr_timing : signal is "true";
  attribute RTL_MAX_FANOUT : string;
  attribute RTL_MAX_FANOUT of rd_ptr_timing : signal is "found";
  attribute syn_maxfan : string;
  attribute syn_maxfan of rd_ptr_timing : signal is "10";
  signal wr_en : STD_LOGIC;
  attribute MAX_FANOUT of wr_en : signal is "50";
  attribute RTL_MAX_FANOUT of wr_en : signal is "found";
  signal wr_ptr_timing : STD_LOGIC_VECTOR ( 2 downto 0 );
  attribute MAX_FANOUT of wr_ptr_timing : signal is "50";
  attribute RTL_KEEP of wr_ptr_timing : signal is "true";
  attribute RTL_MAX_FANOUT of wr_ptr_timing : signal is "found";
  attribute syn_maxfan of wr_ptr_timing : signal is "10";
  attribute KEEP : string;
  attribute KEEP of \rd_ptr_timing_reg[0]\ : label is "yes";
  attribute RTL_MAX_FANOUT of \rd_ptr_timing_reg[0]\ : label is "found";
  attribute syn_maxfan of \rd_ptr_timing_reg[0]\ : label is "10";
  attribute KEEP of \rd_ptr_timing_reg[1]\ : label is "yes";
  attribute RTL_MAX_FANOUT of \rd_ptr_timing_reg[1]\ : label is "found";
  attribute syn_maxfan of \rd_ptr_timing_reg[1]\ : label is "10";
  attribute KEEP of \rd_ptr_timing_reg[2]\ : label is "yes";
  attribute RTL_MAX_FANOUT of \rd_ptr_timing_reg[2]\ : label is "found";
  attribute syn_maxfan of \rd_ptr_timing_reg[2]\ : label is "10";
  attribute KEEP of \wr_ptr_timing_reg[0]\ : label is "yes";
  attribute RTL_MAX_FANOUT of \wr_ptr_timing_reg[0]\ : label is "found";
  attribute syn_maxfan of \wr_ptr_timing_reg[0]\ : label is "10";
  attribute KEEP of \wr_ptr_timing_reg[1]\ : label is "yes";
  attribute RTL_MAX_FANOUT of \wr_ptr_timing_reg[1]\ : label is "found";
  attribute syn_maxfan of \wr_ptr_timing_reg[1]\ : label is "10";
  attribute KEEP of \wr_ptr_timing_reg[2]\ : label is "yes";
  attribute RTL_MAX_FANOUT of \wr_ptr_timing_reg[2]\ : label is "found";
  attribute syn_maxfan of \wr_ptr_timing_reg[2]\ : label is "10";
begin
i_0: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => wr_en
    );
\rd_ptr_timing_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \rd_ptr_timing_reg[0]_0\,
      CE => '0',
      D => '1',
      Q => rd_ptr_timing(0),
      R => SR(0)
    );
\rd_ptr_timing_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \rd_ptr_timing_reg[0]_0\,
      CE => '0',
      D => '0',
      Q => rd_ptr_timing(1),
      R => SR(0)
    );
\rd_ptr_timing_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \rd_ptr_timing_reg[0]_0\,
      CE => '0',
      D => '0',
      Q => rd_ptr_timing(2),
      R => SR(0)
    );
\wr_ptr_timing_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \rd_ptr_timing_reg[0]_0\,
      CE => '0',
      D => '1',
      Q => wr_ptr_timing(0),
      R => SR(0)
    );
\wr_ptr_timing_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \rd_ptr_timing_reg[0]_0\,
      CE => '0',
      D => '0',
      Q => wr_ptr_timing(1),
      R => SR(0)
    );
\wr_ptr_timing_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \rd_ptr_timing_reg[0]_0\,
      CE => '0',
      D => '0',
      Q => wr_ptr_timing(2),
      R => SR(0)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \mig_mig_7series_v4_2_ddr_of_pre_fifo__parameterized1\ is
  port (
    \my_empty_reg[1]_0\ : out STD_LOGIC;
    \my_empty_reg[1]_1\ : out STD_LOGIC;
    D0 : out STD_LOGIC_VECTOR ( 7 downto 0 );
    D1 : out STD_LOGIC_VECTOR ( 7 downto 0 );
    \rd_ptr_reg[3]_0\ : out STD_LOGIC_VECTOR ( 63 downto 0 );
    Q : out STD_LOGIC_VECTOR ( 2 downto 0 );
    ofifo_rst : in STD_LOGIC;
    \entry_cnt_reg[4]_0\ : in STD_LOGIC;
    \my_empty_reg[7]_0\ : in STD_LOGIC;
    phy_data_wr_en : in STD_LOGIC;
    out_fifo : in STD_LOGIC;
    out_fifo_0 : in STD_LOGIC_VECTOR ( 7 downto 0 );
    out_fifo_1 : in STD_LOGIC;
    \out_fifo_i_75__3\ : in STD_LOGIC_VECTOR ( 71 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \mig_mig_7series_v4_2_ddr_of_pre_fifo__parameterized1\ : entity is "mig_7series_v4_2_ddr_of_pre_fifo";
end \mig_mig_7series_v4_2_ddr_of_pre_fifo__parameterized1\;

architecture STRUCTURE of \mig_mig_7series_v4_2_ddr_of_pre_fifo__parameterized1\ is
  signal \^q\ : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal \entry_cnt10_out__0\ : STD_LOGIC;
  signal \entry_cnt[0]_i_1__6_n_0\ : STD_LOGIC;
  signal \entry_cnt[1]_i_1__6_n_0\ : STD_LOGIC;
  signal \entry_cnt[2]_i_1__6_n_0\ : STD_LOGIC;
  signal \entry_cnt[3]_i_1__6_n_0\ : STD_LOGIC;
  signal \entry_cnt[4]_i_1__6_n_0\ : STD_LOGIC;
  signal \entry_cnt[4]_i_2__6_n_0\ : STD_LOGIC;
  signal \entry_cnt_reg_n_0_[0]\ : STD_LOGIC;
  signal \entry_cnt_reg_n_0_[1]\ : STD_LOGIC;
  signal mem_reg_0_15_0_5_n_0 : STD_LOGIC;
  signal mem_reg_0_15_0_5_n_1 : STD_LOGIC;
  signal mem_reg_0_15_0_5_n_2 : STD_LOGIC;
  signal mem_reg_0_15_0_5_n_3 : STD_LOGIC;
  signal mem_reg_0_15_0_5_n_4 : STD_LOGIC;
  signal mem_reg_0_15_0_5_n_5 : STD_LOGIC;
  signal mem_reg_0_15_12_17_n_0 : STD_LOGIC;
  signal mem_reg_0_15_12_17_n_1 : STD_LOGIC;
  signal mem_reg_0_15_12_17_n_2 : STD_LOGIC;
  signal mem_reg_0_15_12_17_n_3 : STD_LOGIC;
  signal mem_reg_0_15_6_11_n_0 : STD_LOGIC;
  signal mem_reg_0_15_6_11_n_1 : STD_LOGIC;
  signal mem_reg_0_15_6_11_n_2 : STD_LOGIC;
  signal mem_reg_0_15_6_11_n_3 : STD_LOGIC;
  signal mem_reg_0_15_6_11_n_4 : STD_LOGIC;
  signal mem_reg_0_15_6_11_n_5 : STD_LOGIC;
  signal my_empty0 : STD_LOGIC;
  signal \my_empty[1]_i_1__7_n_0\ : STD_LOGIC;
  signal \my_empty[7]_i_1__7_n_0\ : STD_LOGIC;
  signal \my_empty[7]_i_3__7_n_0\ : STD_LOGIC;
  signal \my_empty[7]_i_4__7_n_0\ : STD_LOGIC;
  signal \^my_empty_reg[1]_1\ : STD_LOGIC;
  signal \my_empty_reg_n_0_[7]\ : STD_LOGIC;
  signal my_full0 : STD_LOGIC;
  signal \my_full[4]_i_1__7_n_0\ : STD_LOGIC;
  signal \my_full[4]_i_3__7_n_0\ : STD_LOGIC;
  signal \my_full[4]_i_4__7_n_0\ : STD_LOGIC;
  signal \my_full_reg_n_0_[4]\ : STD_LOGIC;
  signal nxt_rd_ptr : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal nxt_wr_ptr : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \rd_ptr_reg_n_0_[0]\ : STD_LOGIC;
  signal \rd_ptr_reg_n_0_[1]\ : STD_LOGIC;
  signal \rd_ptr_reg_n_0_[2]\ : STD_LOGIC;
  signal \rd_ptr_reg_n_0_[3]\ : STD_LOGIC;
  signal rd_ptr_timing : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \rd_ptr_timing[3]_i_1__7_n_0\ : STD_LOGIC;
  signal wr_en : STD_LOGIC;
  attribute MAX_FANOUT : string;
  attribute MAX_FANOUT of wr_en : signal is "50";
  attribute RTL_MAX_FANOUT : string;
  attribute RTL_MAX_FANOUT of wr_en : signal is "found";
  signal wr_ptr : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal wr_ptr0 : STD_LOGIC;
  signal wr_ptr_timing : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal NLW_mem_reg_0_15_0_5_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_15_12_17_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_15_18_23_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_15_24_29_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_15_30_35_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_15_36_41_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_15_42_47_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_15_48_53_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_15_54_59_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_15_60_65_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_15_66_71_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_15_6_11_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_15_72_77_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_15_78_79_DOB_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_15_78_79_DOC_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_15_78_79_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \entry_cnt[0]_i_1__6\ : label is "soft_lutpair1126";
  attribute SOFT_HLUTNM of \entry_cnt[1]_i_1__6\ : label is "soft_lutpair1125";
  attribute SOFT_HLUTNM of \entry_cnt[3]_i_1__6\ : label is "soft_lutpair1126";
  attribute SOFT_HLUTNM of \entry_cnt[4]_i_3__6\ : label is "soft_lutpair1125";
  attribute METHODOLOGY_DRC_VIOS : string;
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_15_0_5 : label is "";
  attribute RTL_RAM_BITS : integer;
  attribute RTL_RAM_BITS of mem_reg_0_15_0_5 : label is 720;
  attribute RTL_RAM_NAME : string;
  attribute RTL_RAM_NAME of mem_reg_0_15_0_5 : label is "of_pre_fifo_gen.u_ddr_of_pre_fifo/mem";
  attribute ram_addr_begin : integer;
  attribute ram_addr_begin of mem_reg_0_15_0_5 : label is 0;
  attribute ram_addr_end : integer;
  attribute ram_addr_end of mem_reg_0_15_0_5 : label is 8;
  attribute ram_offset : integer;
  attribute ram_offset of mem_reg_0_15_0_5 : label is 0;
  attribute ram_slice_begin : integer;
  attribute ram_slice_begin of mem_reg_0_15_0_5 : label is 0;
  attribute ram_slice_end : integer;
  attribute ram_slice_end of mem_reg_0_15_0_5 : label is 5;
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_15_12_17 : label is "";
  attribute RTL_RAM_BITS of mem_reg_0_15_12_17 : label is 720;
  attribute RTL_RAM_NAME of mem_reg_0_15_12_17 : label is "of_pre_fifo_gen.u_ddr_of_pre_fifo/mem";
  attribute ram_addr_begin of mem_reg_0_15_12_17 : label is 0;
  attribute ram_addr_end of mem_reg_0_15_12_17 : label is 8;
  attribute ram_offset of mem_reg_0_15_12_17 : label is 0;
  attribute ram_slice_begin of mem_reg_0_15_12_17 : label is 12;
  attribute ram_slice_end of mem_reg_0_15_12_17 : label is 17;
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_15_18_23 : label is "";
  attribute RTL_RAM_BITS of mem_reg_0_15_18_23 : label is 720;
  attribute RTL_RAM_NAME of mem_reg_0_15_18_23 : label is "of_pre_fifo_gen.u_ddr_of_pre_fifo/mem";
  attribute ram_addr_begin of mem_reg_0_15_18_23 : label is 0;
  attribute ram_addr_end of mem_reg_0_15_18_23 : label is 8;
  attribute ram_offset of mem_reg_0_15_18_23 : label is 0;
  attribute ram_slice_begin of mem_reg_0_15_18_23 : label is 18;
  attribute ram_slice_end of mem_reg_0_15_18_23 : label is 23;
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_15_24_29 : label is "";
  attribute RTL_RAM_BITS of mem_reg_0_15_24_29 : label is 720;
  attribute RTL_RAM_NAME of mem_reg_0_15_24_29 : label is "of_pre_fifo_gen.u_ddr_of_pre_fifo/mem";
  attribute ram_addr_begin of mem_reg_0_15_24_29 : label is 0;
  attribute ram_addr_end of mem_reg_0_15_24_29 : label is 8;
  attribute ram_offset of mem_reg_0_15_24_29 : label is 0;
  attribute ram_slice_begin of mem_reg_0_15_24_29 : label is 24;
  attribute ram_slice_end of mem_reg_0_15_24_29 : label is 29;
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_15_30_35 : label is "";
  attribute RTL_RAM_BITS of mem_reg_0_15_30_35 : label is 720;
  attribute RTL_RAM_NAME of mem_reg_0_15_30_35 : label is "of_pre_fifo_gen.u_ddr_of_pre_fifo/mem";
  attribute ram_addr_begin of mem_reg_0_15_30_35 : label is 0;
  attribute ram_addr_end of mem_reg_0_15_30_35 : label is 8;
  attribute ram_offset of mem_reg_0_15_30_35 : label is 0;
  attribute ram_slice_begin of mem_reg_0_15_30_35 : label is 30;
  attribute ram_slice_end of mem_reg_0_15_30_35 : label is 35;
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_15_36_41 : label is "";
  attribute RTL_RAM_BITS of mem_reg_0_15_36_41 : label is 720;
  attribute RTL_RAM_NAME of mem_reg_0_15_36_41 : label is "of_pre_fifo_gen.u_ddr_of_pre_fifo/mem";
  attribute ram_addr_begin of mem_reg_0_15_36_41 : label is 0;
  attribute ram_addr_end of mem_reg_0_15_36_41 : label is 8;
  attribute ram_offset of mem_reg_0_15_36_41 : label is 0;
  attribute ram_slice_begin of mem_reg_0_15_36_41 : label is 36;
  attribute ram_slice_end of mem_reg_0_15_36_41 : label is 41;
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_15_42_47 : label is "";
  attribute RTL_RAM_BITS of mem_reg_0_15_42_47 : label is 720;
  attribute RTL_RAM_NAME of mem_reg_0_15_42_47 : label is "of_pre_fifo_gen.u_ddr_of_pre_fifo/mem";
  attribute ram_addr_begin of mem_reg_0_15_42_47 : label is 0;
  attribute ram_addr_end of mem_reg_0_15_42_47 : label is 8;
  attribute ram_offset of mem_reg_0_15_42_47 : label is 0;
  attribute ram_slice_begin of mem_reg_0_15_42_47 : label is 42;
  attribute ram_slice_end of mem_reg_0_15_42_47 : label is 47;
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_15_48_53 : label is "";
  attribute RTL_RAM_BITS of mem_reg_0_15_48_53 : label is 720;
  attribute RTL_RAM_NAME of mem_reg_0_15_48_53 : label is "of_pre_fifo_gen.u_ddr_of_pre_fifo/mem";
  attribute ram_addr_begin of mem_reg_0_15_48_53 : label is 0;
  attribute ram_addr_end of mem_reg_0_15_48_53 : label is 8;
  attribute ram_offset of mem_reg_0_15_48_53 : label is 0;
  attribute ram_slice_begin of mem_reg_0_15_48_53 : label is 48;
  attribute ram_slice_end of mem_reg_0_15_48_53 : label is 53;
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_15_54_59 : label is "";
  attribute RTL_RAM_BITS of mem_reg_0_15_54_59 : label is 720;
  attribute RTL_RAM_NAME of mem_reg_0_15_54_59 : label is "of_pre_fifo_gen.u_ddr_of_pre_fifo/mem";
  attribute ram_addr_begin of mem_reg_0_15_54_59 : label is 0;
  attribute ram_addr_end of mem_reg_0_15_54_59 : label is 8;
  attribute ram_offset of mem_reg_0_15_54_59 : label is 0;
  attribute ram_slice_begin of mem_reg_0_15_54_59 : label is 54;
  attribute ram_slice_end of mem_reg_0_15_54_59 : label is 59;
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_15_60_65 : label is "";
  attribute RTL_RAM_BITS of mem_reg_0_15_60_65 : label is 720;
  attribute RTL_RAM_NAME of mem_reg_0_15_60_65 : label is "of_pre_fifo_gen.u_ddr_of_pre_fifo/mem";
  attribute ram_addr_begin of mem_reg_0_15_60_65 : label is 0;
  attribute ram_addr_end of mem_reg_0_15_60_65 : label is 8;
  attribute ram_offset of mem_reg_0_15_60_65 : label is 0;
  attribute ram_slice_begin of mem_reg_0_15_60_65 : label is 60;
  attribute ram_slice_end of mem_reg_0_15_60_65 : label is 65;
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_15_66_71 : label is "";
  attribute RTL_RAM_BITS of mem_reg_0_15_66_71 : label is 720;
  attribute RTL_RAM_NAME of mem_reg_0_15_66_71 : label is "of_pre_fifo_gen.u_ddr_of_pre_fifo/mem";
  attribute ram_addr_begin of mem_reg_0_15_66_71 : label is 0;
  attribute ram_addr_end of mem_reg_0_15_66_71 : label is 8;
  attribute ram_offset of mem_reg_0_15_66_71 : label is 0;
  attribute ram_slice_begin of mem_reg_0_15_66_71 : label is 66;
  attribute ram_slice_end of mem_reg_0_15_66_71 : label is 71;
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_15_6_11 : label is "";
  attribute RTL_RAM_BITS of mem_reg_0_15_6_11 : label is 720;
  attribute RTL_RAM_NAME of mem_reg_0_15_6_11 : label is "of_pre_fifo_gen.u_ddr_of_pre_fifo/mem";
  attribute ram_addr_begin of mem_reg_0_15_6_11 : label is 0;
  attribute ram_addr_end of mem_reg_0_15_6_11 : label is 8;
  attribute ram_offset of mem_reg_0_15_6_11 : label is 0;
  attribute ram_slice_begin of mem_reg_0_15_6_11 : label is 6;
  attribute ram_slice_end of mem_reg_0_15_6_11 : label is 11;
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_15_72_77 : label is "";
  attribute RTL_RAM_BITS of mem_reg_0_15_72_77 : label is 720;
  attribute RTL_RAM_NAME of mem_reg_0_15_72_77 : label is "of_pre_fifo_gen.u_ddr_of_pre_fifo/mem";
  attribute ram_addr_begin of mem_reg_0_15_72_77 : label is 0;
  attribute ram_addr_end of mem_reg_0_15_72_77 : label is 8;
  attribute ram_offset of mem_reg_0_15_72_77 : label is 0;
  attribute ram_slice_begin of mem_reg_0_15_72_77 : label is 72;
  attribute ram_slice_end of mem_reg_0_15_72_77 : label is 77;
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_15_78_79 : label is "";
  attribute RTL_RAM_BITS of mem_reg_0_15_78_79 : label is 720;
  attribute RTL_RAM_NAME of mem_reg_0_15_78_79 : label is "of_pre_fifo_gen.u_ddr_of_pre_fifo/mem";
  attribute ram_addr_begin of mem_reg_0_15_78_79 : label is 0;
  attribute ram_addr_end of mem_reg_0_15_78_79 : label is 8;
  attribute ram_offset of mem_reg_0_15_78_79 : label is 0;
  attribute ram_slice_begin of mem_reg_0_15_78_79 : label is 78;
  attribute ram_slice_end of mem_reg_0_15_78_79 : label is 79;
  attribute SOFT_HLUTNM of \my_empty[7]_i_3__7\ : label is "soft_lutpair1128";
  attribute SOFT_HLUTNM of \my_empty[7]_i_4__7\ : label is "soft_lutpair1128";
  attribute syn_maxfan : string;
  attribute syn_maxfan of \my_empty_reg[1]\ : label is "3";
  attribute syn_maxfan of \my_empty_reg[7]\ : label is "3";
  attribute SOFT_HLUTNM of \my_full[4]_i_3__7\ : label is "soft_lutpair1127";
  attribute SOFT_HLUTNM of \my_full[4]_i_4__7\ : label is "soft_lutpair1127";
  attribute syn_maxfan of \my_full_reg[4]\ : label is "3";
  attribute SOFT_HLUTNM of \out_fifo_i_10__6\ : label is "soft_lutpair1129";
  attribute SOFT_HLUTNM of \out_fifo_i_11__6\ : label is "soft_lutpair1136";
  attribute SOFT_HLUTNM of \out_fifo_i_12__6\ : label is "soft_lutpair1131";
  attribute SOFT_HLUTNM of \out_fifo_i_13__6\ : label is "soft_lutpair1134";
  attribute SOFT_HLUTNM of \out_fifo_i_14__6\ : label is "soft_lutpair1132";
  attribute SOFT_HLUTNM of \out_fifo_i_15__6\ : label is "soft_lutpair1133";
  attribute SOFT_HLUTNM of \out_fifo_i_16__6\ : label is "soft_lutpair1130";
  attribute SOFT_HLUTNM of \out_fifo_i_17__6\ : label is "soft_lutpair1138";
  attribute SOFT_HLUTNM of \out_fifo_i_2__5\ : label is "soft_lutpair1134";
  attribute SOFT_HLUTNM of \out_fifo_i_3__5\ : label is "soft_lutpair1130";
  attribute SOFT_HLUTNM of \out_fifo_i_4__5\ : label is "soft_lutpair1136";
  attribute SOFT_HLUTNM of \out_fifo_i_5__5\ : label is "soft_lutpair1132";
  attribute SOFT_HLUTNM of \out_fifo_i_6__5\ : label is "soft_lutpair1133";
  attribute SOFT_HLUTNM of \out_fifo_i_7__5\ : label is "soft_lutpair1129";
  attribute SOFT_HLUTNM of \out_fifo_i_8__5\ : label is "soft_lutpair1138";
  attribute SOFT_HLUTNM of \out_fifo_i_9__5\ : label is "soft_lutpair1131";
  attribute syn_maxfan of \rd_ptr_reg[0]\ : label is "10";
  attribute syn_maxfan of \rd_ptr_reg[1]\ : label is "10";
  attribute syn_maxfan of \rd_ptr_reg[2]\ : label is "10";
  attribute syn_maxfan of \rd_ptr_reg[3]\ : label is "10";
  attribute SOFT_HLUTNM of \rd_ptr_timing[0]_i_1__15\ : label is "soft_lutpair1140";
  attribute SOFT_HLUTNM of \rd_ptr_timing[1]_i_1__15\ : label is "soft_lutpair1140";
  attribute SOFT_HLUTNM of \rd_ptr_timing[2]_i_1__7\ : label is "soft_lutpair1137";
  attribute SOFT_HLUTNM of \rd_ptr_timing[3]_i_2__7\ : label is "soft_lutpair1137";
  attribute KEEP : string;
  attribute KEEP of \rd_ptr_timing_reg[0]\ : label is "yes";
  attribute KEEP of \rd_ptr_timing_reg[1]\ : label is "yes";
  attribute KEEP of \rd_ptr_timing_reg[2]\ : label is "yes";
  attribute KEEP of \rd_ptr_timing_reg[3]\ : label is "yes";
  attribute SOFT_HLUTNM of \wr_ptr[0]_i_1__15\ : label is "soft_lutpair1139";
  attribute SOFT_HLUTNM of \wr_ptr[1]_i_1__15\ : label is "soft_lutpair1139";
  attribute SOFT_HLUTNM of \wr_ptr[2]_i_1__7\ : label is "soft_lutpair1135";
  attribute SOFT_HLUTNM of \wr_ptr[3]_i_2__6\ : label is "soft_lutpair1135";
  attribute syn_maxfan of \wr_ptr_reg[0]\ : label is "10";
  attribute syn_maxfan of \wr_ptr_reg[1]\ : label is "10";
  attribute syn_maxfan of \wr_ptr_reg[2]\ : label is "10";
  attribute syn_maxfan of \wr_ptr_reg[3]\ : label is "10";
  attribute KEEP of \wr_ptr_timing_reg[0]\ : label is "yes";
  attribute KEEP of \wr_ptr_timing_reg[1]\ : label is "yes";
  attribute KEEP of \wr_ptr_timing_reg[2]\ : label is "yes";
  attribute KEEP of \wr_ptr_timing_reg[3]\ : label is "yes";
begin
  Q(2 downto 0) <= \^q\(2 downto 0);
  \my_empty_reg[1]_1\ <= \^my_empty_reg[1]_1\;
\entry_cnt[0]_i_1__6\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \entry_cnt_reg_n_0_[0]\,
      O => \entry_cnt[0]_i_1__6_n_0\
    );
\entry_cnt[1]_i_1__6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AA6A5595"
    )
        port map (
      I0 => \entry_cnt_reg_n_0_[0]\,
      I1 => \my_empty_reg[7]_0\,
      I2 => phy_data_wr_en,
      I3 => \my_full_reg_n_0_[4]\,
      I4 => \entry_cnt_reg_n_0_[1]\,
      O => \entry_cnt[1]_i_1__6_n_0\
    );
\entry_cnt[2]_i_1__6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FF7F0080AAEA5515"
    )
        port map (
      I0 => \entry_cnt_reg_n_0_[0]\,
      I1 => \my_empty_reg[7]_0\,
      I2 => phy_data_wr_en,
      I3 => \my_full_reg_n_0_[4]\,
      I4 => \^q\(0),
      I5 => \entry_cnt_reg_n_0_[1]\,
      O => \entry_cnt[2]_i_1__6_n_0\
    );
\entry_cnt[3]_i_1__6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"7F80FE01"
    )
        port map (
      I0 => \entry_cnt10_out__0\,
      I1 => \entry_cnt_reg_n_0_[0]\,
      I2 => \entry_cnt_reg_n_0_[1]\,
      I3 => \^q\(1),
      I4 => \^q\(0),
      O => \entry_cnt[3]_i_1__6_n_0\
    );
\entry_cnt[4]_i_1__6\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"5003"
    )
        port map (
      I0 => \my_full_reg_n_0_[4]\,
      I1 => \my_empty_reg_n_0_[7]\,
      I2 => \my_empty_reg[7]_0\,
      I3 => phy_data_wr_en,
      O => \entry_cnt[4]_i_1__6_n_0\
    );
\entry_cnt[4]_i_2__6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"7FFF8000FFFE0001"
    )
        port map (
      I0 => \entry_cnt_reg_n_0_[1]\,
      I1 => \entry_cnt_reg_n_0_[0]\,
      I2 => \entry_cnt10_out__0\,
      I3 => \^q\(0),
      I4 => \^q\(2),
      I5 => \^q\(1),
      O => \entry_cnt[4]_i_2__6_n_0\
    );
\entry_cnt[4]_i_3__6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"08"
    )
        port map (
      I0 => \my_empty_reg[7]_0\,
      I1 => phy_data_wr_en,
      I2 => \my_full_reg_n_0_[4]\,
      O => \entry_cnt10_out__0\
    );
\entry_cnt_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]_0\,
      CE => \entry_cnt[4]_i_1__6_n_0\,
      D => \entry_cnt[0]_i_1__6_n_0\,
      Q => \entry_cnt_reg_n_0_[0]\,
      R => ofifo_rst
    );
\entry_cnt_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]_0\,
      CE => \entry_cnt[4]_i_1__6_n_0\,
      D => \entry_cnt[1]_i_1__6_n_0\,
      Q => \entry_cnt_reg_n_0_[1]\,
      R => ofifo_rst
    );
\entry_cnt_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]_0\,
      CE => \entry_cnt[4]_i_1__6_n_0\,
      D => \entry_cnt[2]_i_1__6_n_0\,
      Q => \^q\(0),
      R => ofifo_rst
    );
\entry_cnt_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]_0\,
      CE => \entry_cnt[4]_i_1__6_n_0\,
      D => \entry_cnt[3]_i_1__6_n_0\,
      Q => \^q\(1),
      R => ofifo_rst
    );
\entry_cnt_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]_0\,
      CE => \entry_cnt[4]_i_1__6_n_0\,
      D => \entry_cnt[4]_i_2__6_n_0\,
      Q => \^q\(2),
      R => ofifo_rst
    );
mem_reg_0_15_0_5: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4) => '0',
      ADDRA(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRA(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRA(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRA(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRB(4) => '0',
      ADDRB(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRB(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRB(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRB(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRC(4) => '0',
      ADDRC(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRC(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRC(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRC(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRD(4) => '0',
      ADDRD(3 downto 0) => wr_ptr(3 downto 0),
      DIA(1 downto 0) => B"00",
      DIB(1 downto 0) => B"00",
      DIC(1 downto 0) => B"00",
      DID(1 downto 0) => B"00",
      DOA(1) => mem_reg_0_15_0_5_n_0,
      DOA(0) => mem_reg_0_15_0_5_n_1,
      DOB(1) => mem_reg_0_15_0_5_n_2,
      DOB(0) => mem_reg_0_15_0_5_n_3,
      DOC(1) => mem_reg_0_15_0_5_n_4,
      DOC(0) => mem_reg_0_15_0_5_n_5,
      DOD(1 downto 0) => NLW_mem_reg_0_15_0_5_DOD_UNCONNECTED(1 downto 0),
      WCLK => \entry_cnt_reg[4]_0\,
      WE => wr_en
    );
\mem_reg_0_15_0_5_i_1__6\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2700"
    )
        port map (
      I0 => \my_empty_reg[7]_0\,
      I1 => \my_full_reg_n_0_[4]\,
      I2 => \^my_empty_reg[1]_1\,
      I3 => phy_data_wr_en,
      O => wr_en
    );
mem_reg_0_15_12_17: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4) => '0',
      ADDRA(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRA(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRA(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRA(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRB(4) => '0',
      ADDRB(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRB(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRB(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRB(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRC(4) => '0',
      ADDRC(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRC(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRC(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRC(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRD(4) => '0',
      ADDRD(3 downto 0) => wr_ptr(3 downto 0),
      DIA(1 downto 0) => \out_fifo_i_75__3\(5 downto 4),
      DIB(1 downto 0) => \out_fifo_i_75__3\(7 downto 6),
      DIC(1 downto 0) => \out_fifo_i_75__3\(9 downto 8),
      DID(1 downto 0) => B"00",
      DOA(1) => mem_reg_0_15_12_17_n_0,
      DOA(0) => mem_reg_0_15_12_17_n_1,
      DOB(1) => mem_reg_0_15_12_17_n_2,
      DOB(0) => mem_reg_0_15_12_17_n_3,
      DOC(1 downto 0) => \rd_ptr_reg[3]_0\(1 downto 0),
      DOD(1 downto 0) => NLW_mem_reg_0_15_12_17_DOD_UNCONNECTED(1 downto 0),
      WCLK => \entry_cnt_reg[4]_0\,
      WE => wr_en
    );
mem_reg_0_15_18_23: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4) => '0',
      ADDRA(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRA(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRA(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRA(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRB(4) => '0',
      ADDRB(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRB(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRB(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRB(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRC(4) => '0',
      ADDRC(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRC(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRC(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRC(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRD(4) => '0',
      ADDRD(3 downto 0) => wr_ptr(3 downto 0),
      DIA(1 downto 0) => \out_fifo_i_75__3\(11 downto 10),
      DIB(1 downto 0) => \out_fifo_i_75__3\(13 downto 12),
      DIC(1 downto 0) => \out_fifo_i_75__3\(15 downto 14),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => \rd_ptr_reg[3]_0\(3 downto 2),
      DOB(1 downto 0) => \rd_ptr_reg[3]_0\(5 downto 4),
      DOC(1 downto 0) => \rd_ptr_reg[3]_0\(7 downto 6),
      DOD(1 downto 0) => NLW_mem_reg_0_15_18_23_DOD_UNCONNECTED(1 downto 0),
      WCLK => \entry_cnt_reg[4]_0\,
      WE => wr_en
    );
mem_reg_0_15_24_29: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4) => '0',
      ADDRA(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRA(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRA(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRA(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRB(4) => '0',
      ADDRB(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRB(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRB(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRB(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRC(4) => '0',
      ADDRC(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRC(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRC(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRC(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRD(4) => '0',
      ADDRD(3 downto 0) => wr_ptr(3 downto 0),
      DIA(1 downto 0) => \out_fifo_i_75__3\(17 downto 16),
      DIB(1 downto 0) => \out_fifo_i_75__3\(19 downto 18),
      DIC(1 downto 0) => \out_fifo_i_75__3\(21 downto 20),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => \rd_ptr_reg[3]_0\(9 downto 8),
      DOB(1 downto 0) => \rd_ptr_reg[3]_0\(11 downto 10),
      DOC(1 downto 0) => \rd_ptr_reg[3]_0\(13 downto 12),
      DOD(1 downto 0) => NLW_mem_reg_0_15_24_29_DOD_UNCONNECTED(1 downto 0),
      WCLK => \entry_cnt_reg[4]_0\,
      WE => wr_en
    );
mem_reg_0_15_30_35: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4) => '0',
      ADDRA(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRA(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRA(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRA(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRB(4) => '0',
      ADDRB(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRB(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRB(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRB(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRC(4) => '0',
      ADDRC(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRC(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRC(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRC(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRD(4) => '0',
      ADDRD(3 downto 0) => wr_ptr(3 downto 0),
      DIA(1 downto 0) => \out_fifo_i_75__3\(23 downto 22),
      DIB(1 downto 0) => \out_fifo_i_75__3\(25 downto 24),
      DIC(1 downto 0) => \out_fifo_i_75__3\(27 downto 26),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => \rd_ptr_reg[3]_0\(15 downto 14),
      DOB(1 downto 0) => \rd_ptr_reg[3]_0\(17 downto 16),
      DOC(1 downto 0) => \rd_ptr_reg[3]_0\(19 downto 18),
      DOD(1 downto 0) => NLW_mem_reg_0_15_30_35_DOD_UNCONNECTED(1 downto 0),
      WCLK => \entry_cnt_reg[4]_0\,
      WE => wr_en
    );
mem_reg_0_15_36_41: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4) => '0',
      ADDRA(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRA(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRA(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRA(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRB(4) => '0',
      ADDRB(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRB(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRB(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRB(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRC(4) => '0',
      ADDRC(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRC(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRC(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRC(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRD(4) => '0',
      ADDRD(3 downto 0) => wr_ptr(3 downto 0),
      DIA(1 downto 0) => \out_fifo_i_75__3\(29 downto 28),
      DIB(1 downto 0) => \out_fifo_i_75__3\(31 downto 30),
      DIC(1 downto 0) => \out_fifo_i_75__3\(33 downto 32),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => \rd_ptr_reg[3]_0\(21 downto 20),
      DOB(1 downto 0) => \rd_ptr_reg[3]_0\(23 downto 22),
      DOC(1 downto 0) => \rd_ptr_reg[3]_0\(25 downto 24),
      DOD(1 downto 0) => NLW_mem_reg_0_15_36_41_DOD_UNCONNECTED(1 downto 0),
      WCLK => \entry_cnt_reg[4]_0\,
      WE => wr_en
    );
mem_reg_0_15_42_47: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4) => '0',
      ADDRA(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRA(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRA(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRA(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRB(4) => '0',
      ADDRB(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRB(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRB(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRB(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRC(4) => '0',
      ADDRC(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRC(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRC(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRC(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRD(4) => '0',
      ADDRD(3 downto 0) => wr_ptr(3 downto 0),
      DIA(1 downto 0) => \out_fifo_i_75__3\(35 downto 34),
      DIB(1 downto 0) => \out_fifo_i_75__3\(37 downto 36),
      DIC(1 downto 0) => \out_fifo_i_75__3\(39 downto 38),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => \rd_ptr_reg[3]_0\(27 downto 26),
      DOB(1 downto 0) => \rd_ptr_reg[3]_0\(29 downto 28),
      DOC(1 downto 0) => \rd_ptr_reg[3]_0\(31 downto 30),
      DOD(1 downto 0) => NLW_mem_reg_0_15_42_47_DOD_UNCONNECTED(1 downto 0),
      WCLK => \entry_cnt_reg[4]_0\,
      WE => wr_en
    );
mem_reg_0_15_48_53: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4) => '0',
      ADDRA(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRA(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRA(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRA(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRB(4) => '0',
      ADDRB(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRB(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRB(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRB(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRC(4) => '0',
      ADDRC(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRC(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRC(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRC(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRD(4) => '0',
      ADDRD(3 downto 0) => wr_ptr(3 downto 0),
      DIA(1 downto 0) => \out_fifo_i_75__3\(41 downto 40),
      DIB(1 downto 0) => \out_fifo_i_75__3\(43 downto 42),
      DIC(1 downto 0) => \out_fifo_i_75__3\(45 downto 44),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => \rd_ptr_reg[3]_0\(33 downto 32),
      DOB(1 downto 0) => \rd_ptr_reg[3]_0\(35 downto 34),
      DOC(1 downto 0) => \rd_ptr_reg[3]_0\(37 downto 36),
      DOD(1 downto 0) => NLW_mem_reg_0_15_48_53_DOD_UNCONNECTED(1 downto 0),
      WCLK => \entry_cnt_reg[4]_0\,
      WE => wr_en
    );
mem_reg_0_15_54_59: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4) => '0',
      ADDRA(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRA(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRA(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRA(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRB(4) => '0',
      ADDRB(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRB(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRB(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRB(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRC(4) => '0',
      ADDRC(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRC(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRC(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRC(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRD(4) => '0',
      ADDRD(3 downto 0) => wr_ptr(3 downto 0),
      DIA(1 downto 0) => \out_fifo_i_75__3\(47 downto 46),
      DIB(1 downto 0) => \out_fifo_i_75__3\(49 downto 48),
      DIC(1 downto 0) => \out_fifo_i_75__3\(51 downto 50),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => \rd_ptr_reg[3]_0\(39 downto 38),
      DOB(1 downto 0) => \rd_ptr_reg[3]_0\(41 downto 40),
      DOC(1 downto 0) => \rd_ptr_reg[3]_0\(43 downto 42),
      DOD(1 downto 0) => NLW_mem_reg_0_15_54_59_DOD_UNCONNECTED(1 downto 0),
      WCLK => \entry_cnt_reg[4]_0\,
      WE => wr_en
    );
mem_reg_0_15_60_65: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4) => '0',
      ADDRA(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRA(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRA(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRA(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRB(4) => '0',
      ADDRB(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRB(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRB(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRB(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRC(4) => '0',
      ADDRC(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRC(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRC(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRC(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRD(4) => '0',
      ADDRD(3 downto 0) => wr_ptr(3 downto 0),
      DIA(1 downto 0) => \out_fifo_i_75__3\(53 downto 52),
      DIB(1 downto 0) => \out_fifo_i_75__3\(55 downto 54),
      DIC(1 downto 0) => \out_fifo_i_75__3\(57 downto 56),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => \rd_ptr_reg[3]_0\(45 downto 44),
      DOB(1 downto 0) => \rd_ptr_reg[3]_0\(47 downto 46),
      DOC(1 downto 0) => \rd_ptr_reg[3]_0\(49 downto 48),
      DOD(1 downto 0) => NLW_mem_reg_0_15_60_65_DOD_UNCONNECTED(1 downto 0),
      WCLK => \entry_cnt_reg[4]_0\,
      WE => wr_en
    );
mem_reg_0_15_66_71: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4) => '0',
      ADDRA(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRA(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRA(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRA(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRB(4) => '0',
      ADDRB(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRB(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRB(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRB(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRC(4) => '0',
      ADDRC(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRC(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRC(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRC(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRD(4) => '0',
      ADDRD(3 downto 0) => wr_ptr(3 downto 0),
      DIA(1 downto 0) => \out_fifo_i_75__3\(59 downto 58),
      DIB(1 downto 0) => \out_fifo_i_75__3\(61 downto 60),
      DIC(1 downto 0) => \out_fifo_i_75__3\(63 downto 62),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => \rd_ptr_reg[3]_0\(51 downto 50),
      DOB(1 downto 0) => \rd_ptr_reg[3]_0\(53 downto 52),
      DOC(1 downto 0) => \rd_ptr_reg[3]_0\(55 downto 54),
      DOD(1 downto 0) => NLW_mem_reg_0_15_66_71_DOD_UNCONNECTED(1 downto 0),
      WCLK => \entry_cnt_reg[4]_0\,
      WE => wr_en
    );
mem_reg_0_15_6_11: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4) => '0',
      ADDRA(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRA(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRA(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRA(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRB(4) => '0',
      ADDRB(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRB(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRB(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRB(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRC(4) => '0',
      ADDRC(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRC(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRC(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRC(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRD(4) => '0',
      ADDRD(3 downto 0) => wr_ptr(3 downto 0),
      DIA(1 downto 0) => B"00",
      DIB(1 downto 0) => \out_fifo_i_75__3\(1 downto 0),
      DIC(1 downto 0) => \out_fifo_i_75__3\(3 downto 2),
      DID(1 downto 0) => B"00",
      DOA(1) => mem_reg_0_15_6_11_n_0,
      DOA(0) => mem_reg_0_15_6_11_n_1,
      DOB(1) => mem_reg_0_15_6_11_n_2,
      DOB(0) => mem_reg_0_15_6_11_n_3,
      DOC(1) => mem_reg_0_15_6_11_n_4,
      DOC(0) => mem_reg_0_15_6_11_n_5,
      DOD(1 downto 0) => NLW_mem_reg_0_15_6_11_DOD_UNCONNECTED(1 downto 0),
      WCLK => \entry_cnt_reg[4]_0\,
      WE => wr_en
    );
mem_reg_0_15_72_77: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4) => '0',
      ADDRA(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRA(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRA(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRA(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRB(4) => '0',
      ADDRB(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRB(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRB(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRB(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRC(4) => '0',
      ADDRC(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRC(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRC(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRC(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRD(4) => '0',
      ADDRD(3 downto 0) => wr_ptr(3 downto 0),
      DIA(1 downto 0) => \out_fifo_i_75__3\(65 downto 64),
      DIB(1 downto 0) => \out_fifo_i_75__3\(67 downto 66),
      DIC(1 downto 0) => \out_fifo_i_75__3\(69 downto 68),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => \rd_ptr_reg[3]_0\(57 downto 56),
      DOB(1 downto 0) => \rd_ptr_reg[3]_0\(59 downto 58),
      DOC(1 downto 0) => \rd_ptr_reg[3]_0\(61 downto 60),
      DOD(1 downto 0) => NLW_mem_reg_0_15_72_77_DOD_UNCONNECTED(1 downto 0),
      WCLK => \entry_cnt_reg[4]_0\,
      WE => wr_en
    );
mem_reg_0_15_78_79: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4) => '0',
      ADDRA(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRA(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRA(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRA(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRB(4) => '0',
      ADDRB(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRB(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRB(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRB(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRC(4) => '0',
      ADDRC(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRC(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRC(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRC(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRD(4) => '0',
      ADDRD(3 downto 0) => wr_ptr(3 downto 0),
      DIA(1 downto 0) => \out_fifo_i_75__3\(71 downto 70),
      DIB(1 downto 0) => B"00",
      DIC(1 downto 0) => B"00",
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => \rd_ptr_reg[3]_0\(63 downto 62),
      DOB(1 downto 0) => NLW_mem_reg_0_15_78_79_DOB_UNCONNECTED(1 downto 0),
      DOC(1 downto 0) => NLW_mem_reg_0_15_78_79_DOC_UNCONNECTED(1 downto 0),
      DOD(1 downto 0) => NLW_mem_reg_0_15_78_79_DOD_UNCONNECTED(1 downto 0),
      WCLK => \entry_cnt_reg[4]_0\,
      WE => wr_en
    );
\my_empty[1]_i_1__7\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFF701F700"
    )
        port map (
      I0 => \my_empty_reg[7]_0\,
      I1 => phy_data_wr_en,
      I2 => \my_full_reg_n_0_[4]\,
      I3 => \^my_empty_reg[1]_1\,
      I4 => my_empty0,
      I5 => ofifo_rst,
      O => \my_empty[1]_i_1__7_n_0\
    );
\my_empty[7]_i_1__7\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFF701F700"
    )
        port map (
      I0 => \my_empty_reg[7]_0\,
      I1 => phy_data_wr_en,
      I2 => \my_full_reg_n_0_[4]\,
      I3 => \my_empty_reg_n_0_[7]\,
      I4 => my_empty0,
      I5 => ofifo_rst,
      O => \my_empty[7]_i_1__7_n_0\
    );
\my_empty[7]_i_2__7\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"4A400D08"
    )
        port map (
      I0 => wr_ptr_timing(2),
      I1 => \my_empty[7]_i_3__7_n_0\,
      I2 => wr_ptr_timing(3),
      I3 => \my_empty[7]_i_4__7_n_0\,
      I4 => \rd_ptr_reg_n_0_[2]\,
      O => my_empty0
    );
\my_empty[7]_i_3__7\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000040"
    )
        port map (
      I0 => wr_ptr_timing(1),
      I1 => \rd_ptr_reg_n_0_[0]\,
      I2 => \rd_ptr_reg_n_0_[1]\,
      I3 => \rd_ptr_reg_n_0_[3]\,
      I4 => wr_ptr_timing(0),
      O => \my_empty[7]_i_3__7_n_0\
    );
\my_empty[7]_i_4__7\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"84210842"
    )
        port map (
      I0 => wr_ptr_timing(0),
      I1 => wr_ptr_timing(1),
      I2 => \rd_ptr_reg_n_0_[0]\,
      I3 => \rd_ptr_reg_n_0_[1]\,
      I4 => \rd_ptr_reg_n_0_[3]\,
      O => \my_empty[7]_i_4__7_n_0\
    );
\my_empty_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]_0\,
      CE => '1',
      D => \my_empty[1]_i_1__7_n_0\,
      Q => \^my_empty_reg[1]_1\,
      R => '0'
    );
\my_empty_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]_0\,
      CE => '1',
      D => \my_empty[7]_i_1__7_n_0\,
      Q => \my_empty_reg_n_0_[7]\,
      R => '0'
    );
\my_full[4]_i_1__7\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000FFFC0080"
    )
        port map (
      I0 => my_full0,
      I1 => phy_data_wr_en,
      I2 => \my_empty_reg[7]_0\,
      I3 => \my_empty_reg_n_0_[7]\,
      I4 => \my_full_reg_n_0_[4]\,
      I5 => ofifo_rst,
      O => \my_full[4]_i_1__7_n_0\
    );
\my_full[4]_i_2__7\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"4A400D08"
    )
        port map (
      I0 => rd_ptr_timing(2),
      I1 => \my_full[4]_i_3__7_n_0\,
      I2 => rd_ptr_timing(3),
      I3 => \my_full[4]_i_4__7_n_0\,
      I4 => wr_ptr(2),
      O => my_full0
    );
\my_full[4]_i_3__7\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000040"
    )
        port map (
      I0 => rd_ptr_timing(1),
      I1 => wr_ptr(0),
      I2 => wr_ptr(1),
      I3 => wr_ptr(3),
      I4 => rd_ptr_timing(0),
      O => \my_full[4]_i_3__7_n_0\
    );
\my_full[4]_i_4__7\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"84210842"
    )
        port map (
      I0 => rd_ptr_timing(0),
      I1 => rd_ptr_timing(1),
      I2 => wr_ptr(0),
      I3 => wr_ptr(1),
      I4 => wr_ptr(3),
      O => \my_full[4]_i_4__7_n_0\
    );
\my_full_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]_0\,
      CE => '1',
      D => \my_full[4]_i_1__7_n_0\,
      Q => \my_full_reg_n_0_[4]\,
      R => '0'
    );
\out_fifo_i_10__6\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"88F0"
    )
        port map (
      I0 => out_fifo_1,
      I1 => out_fifo_0(7),
      I2 => mem_reg_0_15_12_17_n_2,
      I3 => \^my_empty_reg[1]_1\,
      O => D1(7)
    );
\out_fifo_i_11__6\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"88F0"
    )
        port map (
      I0 => out_fifo_1,
      I1 => out_fifo_0(6),
      I2 => mem_reg_0_15_12_17_n_3,
      I3 => \^my_empty_reg[1]_1\,
      O => D1(6)
    );
\out_fifo_i_12__6\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"88F0"
    )
        port map (
      I0 => out_fifo_1,
      I1 => out_fifo_0(5),
      I2 => mem_reg_0_15_12_17_n_0,
      I3 => \^my_empty_reg[1]_1\,
      O => D1(5)
    );
\out_fifo_i_13__6\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"88F0"
    )
        port map (
      I0 => out_fifo_1,
      I1 => out_fifo_0(4),
      I2 => mem_reg_0_15_12_17_n_1,
      I3 => \^my_empty_reg[1]_1\,
      O => D1(4)
    );
\out_fifo_i_14__6\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"88F0"
    )
        port map (
      I0 => out_fifo_1,
      I1 => out_fifo_0(3),
      I2 => mem_reg_0_15_6_11_n_4,
      I3 => \^my_empty_reg[1]_1\,
      O => D1(3)
    );
\out_fifo_i_15__6\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"88F0"
    )
        port map (
      I0 => out_fifo_1,
      I1 => out_fifo_0(2),
      I2 => mem_reg_0_15_6_11_n_5,
      I3 => \^my_empty_reg[1]_1\,
      O => D1(2)
    );
\out_fifo_i_16__6\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"88F0"
    )
        port map (
      I0 => out_fifo,
      I1 => out_fifo_0(1),
      I2 => mem_reg_0_15_6_11_n_2,
      I3 => \^my_empty_reg[1]_1\,
      O => D1(1)
    );
\out_fifo_i_17__6\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"88F0"
    )
        port map (
      I0 => out_fifo,
      I1 => out_fifo_0(0),
      I2 => mem_reg_0_15_6_11_n_3,
      I3 => \^my_empty_reg[1]_1\,
      O => D1(0)
    );
\out_fifo_i_1__7\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"0D"
    )
        port map (
      I0 => \^my_empty_reg[1]_1\,
      I1 => phy_data_wr_en,
      I2 => \my_empty_reg[7]_0\,
      O => \my_empty_reg[1]_0\
    );
\out_fifo_i_2__5\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => mem_reg_0_15_6_11_n_0,
      I1 => \^my_empty_reg[1]_1\,
      O => D0(7)
    );
\out_fifo_i_3__5\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => mem_reg_0_15_6_11_n_1,
      I1 => \^my_empty_reg[1]_1\,
      O => D0(6)
    );
\out_fifo_i_4__5\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => mem_reg_0_15_0_5_n_4,
      I1 => \^my_empty_reg[1]_1\,
      O => D0(5)
    );
\out_fifo_i_5__5\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => mem_reg_0_15_0_5_n_5,
      I1 => \^my_empty_reg[1]_1\,
      O => D0(4)
    );
\out_fifo_i_6__5\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => mem_reg_0_15_0_5_n_2,
      I1 => \^my_empty_reg[1]_1\,
      O => D0(3)
    );
\out_fifo_i_7__5\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => mem_reg_0_15_0_5_n_3,
      I1 => \^my_empty_reg[1]_1\,
      O => D0(2)
    );
\out_fifo_i_8__5\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => mem_reg_0_15_0_5_n_0,
      I1 => \^my_empty_reg[1]_1\,
      O => D0(1)
    );
\out_fifo_i_9__5\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => mem_reg_0_15_0_5_n_1,
      I1 => \^my_empty_reg[1]_1\,
      O => D0(0)
    );
\rd_ptr_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]_0\,
      CE => \rd_ptr_timing[3]_i_1__7_n_0\,
      D => nxt_rd_ptr(0),
      Q => \rd_ptr_reg_n_0_[0]\,
      R => ofifo_rst
    );
\rd_ptr_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]_0\,
      CE => \rd_ptr_timing[3]_i_1__7_n_0\,
      D => nxt_rd_ptr(1),
      Q => \rd_ptr_reg_n_0_[1]\,
      R => ofifo_rst
    );
\rd_ptr_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]_0\,
      CE => \rd_ptr_timing[3]_i_1__7_n_0\,
      D => nxt_rd_ptr(2),
      Q => \rd_ptr_reg_n_0_[2]\,
      R => ofifo_rst
    );
\rd_ptr_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]_0\,
      CE => \rd_ptr_timing[3]_i_1__7_n_0\,
      D => nxt_rd_ptr(3),
      Q => \rd_ptr_reg_n_0_[3]\,
      R => ofifo_rst
    );
\rd_ptr_timing[0]_i_1__15\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => \rd_ptr_reg_n_0_[3]\,
      I1 => \rd_ptr_reg_n_0_[0]\,
      O => nxt_rd_ptr(0)
    );
\rd_ptr_timing[1]_i_1__15\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B4"
    )
        port map (
      I0 => \rd_ptr_reg_n_0_[3]\,
      I1 => \rd_ptr_reg_n_0_[0]\,
      I2 => \rd_ptr_reg_n_0_[1]\,
      O => nxt_rd_ptr(1)
    );
\rd_ptr_timing[2]_i_1__7\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"AA6A"
    )
        port map (
      I0 => \rd_ptr_reg_n_0_[2]\,
      I1 => \rd_ptr_reg_n_0_[0]\,
      I2 => \rd_ptr_reg_n_0_[1]\,
      I3 => \rd_ptr_reg_n_0_[3]\,
      O => nxt_rd_ptr(2)
    );
\rd_ptr_timing[3]_i_1__7\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \my_empty_reg[7]_0\,
      I1 => \my_empty_reg_n_0_[7]\,
      O => \rd_ptr_timing[3]_i_1__7_n_0\
    );
\rd_ptr_timing[3]_i_2__7\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4000"
    )
        port map (
      I0 => \rd_ptr_reg_n_0_[3]\,
      I1 => \rd_ptr_reg_n_0_[1]\,
      I2 => \rd_ptr_reg_n_0_[0]\,
      I3 => \rd_ptr_reg_n_0_[2]\,
      O => nxt_rd_ptr(3)
    );
\rd_ptr_timing_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]_0\,
      CE => \rd_ptr_timing[3]_i_1__7_n_0\,
      D => nxt_rd_ptr(0),
      Q => rd_ptr_timing(0),
      R => ofifo_rst
    );
\rd_ptr_timing_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]_0\,
      CE => \rd_ptr_timing[3]_i_1__7_n_0\,
      D => nxt_rd_ptr(1),
      Q => rd_ptr_timing(1),
      R => ofifo_rst
    );
\rd_ptr_timing_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]_0\,
      CE => \rd_ptr_timing[3]_i_1__7_n_0\,
      D => nxt_rd_ptr(2),
      Q => rd_ptr_timing(2),
      R => ofifo_rst
    );
\rd_ptr_timing_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]_0\,
      CE => \rd_ptr_timing[3]_i_1__7_n_0\,
      D => nxt_rd_ptr(3),
      Q => rd_ptr_timing(3),
      R => ofifo_rst
    );
\wr_ptr[0]_i_1__15\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => wr_ptr(3),
      I1 => wr_ptr(0),
      O => nxt_wr_ptr(0)
    );
\wr_ptr[1]_i_1__15\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B4"
    )
        port map (
      I0 => wr_ptr(3),
      I1 => wr_ptr(0),
      I2 => wr_ptr(1),
      O => nxt_wr_ptr(1)
    );
\wr_ptr[2]_i_1__7\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"AA6A"
    )
        port map (
      I0 => wr_ptr(2),
      I1 => wr_ptr(0),
      I2 => wr_ptr(1),
      I3 => wr_ptr(3),
      O => nxt_wr_ptr(2)
    );
\wr_ptr[3]_i_1__7\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"082A"
    )
        port map (
      I0 => phy_data_wr_en,
      I1 => \my_empty_reg[7]_0\,
      I2 => \my_full_reg_n_0_[4]\,
      I3 => \my_empty_reg_n_0_[7]\,
      O => wr_ptr0
    );
\wr_ptr[3]_i_2__6\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4000"
    )
        port map (
      I0 => wr_ptr(3),
      I1 => wr_ptr(1),
      I2 => wr_ptr(0),
      I3 => wr_ptr(2),
      O => nxt_wr_ptr(3)
    );
\wr_ptr_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]_0\,
      CE => wr_ptr0,
      D => nxt_wr_ptr(0),
      Q => wr_ptr(0),
      R => ofifo_rst
    );
\wr_ptr_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]_0\,
      CE => wr_ptr0,
      D => nxt_wr_ptr(1),
      Q => wr_ptr(1),
      R => ofifo_rst
    );
\wr_ptr_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]_0\,
      CE => wr_ptr0,
      D => nxt_wr_ptr(2),
      Q => wr_ptr(2),
      R => ofifo_rst
    );
\wr_ptr_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]_0\,
      CE => wr_ptr0,
      D => nxt_wr_ptr(3),
      Q => wr_ptr(3),
      R => ofifo_rst
    );
\wr_ptr_timing_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]_0\,
      CE => wr_ptr0,
      D => nxt_wr_ptr(0),
      Q => wr_ptr_timing(0),
      R => ofifo_rst
    );
\wr_ptr_timing_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]_0\,
      CE => wr_ptr0,
      D => nxt_wr_ptr(1),
      Q => wr_ptr_timing(1),
      R => ofifo_rst
    );
\wr_ptr_timing_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]_0\,
      CE => wr_ptr0,
      D => nxt_wr_ptr(2),
      Q => wr_ptr_timing(2),
      R => ofifo_rst
    );
\wr_ptr_timing_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]_0\,
      CE => wr_ptr0,
      D => nxt_wr_ptr(3),
      Q => wr_ptr_timing(3),
      R => ofifo_rst
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \mig_mig_7series_v4_2_ddr_of_pre_fifo__parameterized1_16\ is
  port (
    \my_empty_reg[1]_0\ : out STD_LOGIC;
    \my_empty_reg[1]_1\ : out STD_LOGIC;
    D0 : out STD_LOGIC_VECTOR ( 7 downto 0 );
    D1 : out STD_LOGIC_VECTOR ( 7 downto 0 );
    \rd_ptr_reg[3]_0\ : out STD_LOGIC_VECTOR ( 63 downto 0 );
    Q : out STD_LOGIC_VECTOR ( 2 downto 0 );
    ofifo_rst : in STD_LOGIC;
    \wr_ptr_timing_reg[3]_0\ : in STD_LOGIC;
    \my_empty_reg[7]_0\ : in STD_LOGIC;
    phy_data_wr_en : in STD_LOGIC;
    out_fifo : in STD_LOGIC;
    out_fifo_0 : in STD_LOGIC_VECTOR ( 7 downto 0 );
    out_fifo_1 : in STD_LOGIC;
    \out_fifo_i_75__2\ : in STD_LOGIC_VECTOR ( 71 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \mig_mig_7series_v4_2_ddr_of_pre_fifo__parameterized1_16\ : entity is "mig_7series_v4_2_ddr_of_pre_fifo";
end \mig_mig_7series_v4_2_ddr_of_pre_fifo__parameterized1_16\;

architecture STRUCTURE of \mig_mig_7series_v4_2_ddr_of_pre_fifo__parameterized1_16\ is
  signal \^q\ : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal \entry_cnt10_out__0\ : STD_LOGIC;
  signal \entry_cnt[0]_i_1__5_n_0\ : STD_LOGIC;
  signal \entry_cnt[1]_i_1__5_n_0\ : STD_LOGIC;
  signal \entry_cnt[2]_i_1__5_n_0\ : STD_LOGIC;
  signal \entry_cnt[3]_i_1__5_n_0\ : STD_LOGIC;
  signal \entry_cnt[4]_i_1__5_n_0\ : STD_LOGIC;
  signal \entry_cnt[4]_i_2__5_n_0\ : STD_LOGIC;
  signal \entry_cnt_reg_n_0_[0]\ : STD_LOGIC;
  signal \entry_cnt_reg_n_0_[1]\ : STD_LOGIC;
  signal mem_reg_0_15_0_5_n_0 : STD_LOGIC;
  signal mem_reg_0_15_0_5_n_1 : STD_LOGIC;
  signal mem_reg_0_15_0_5_n_2 : STD_LOGIC;
  signal mem_reg_0_15_0_5_n_3 : STD_LOGIC;
  signal mem_reg_0_15_0_5_n_4 : STD_LOGIC;
  signal mem_reg_0_15_0_5_n_5 : STD_LOGIC;
  signal mem_reg_0_15_12_17_n_0 : STD_LOGIC;
  signal mem_reg_0_15_12_17_n_1 : STD_LOGIC;
  signal mem_reg_0_15_12_17_n_2 : STD_LOGIC;
  signal mem_reg_0_15_12_17_n_3 : STD_LOGIC;
  signal mem_reg_0_15_6_11_n_0 : STD_LOGIC;
  signal mem_reg_0_15_6_11_n_1 : STD_LOGIC;
  signal mem_reg_0_15_6_11_n_2 : STD_LOGIC;
  signal mem_reg_0_15_6_11_n_3 : STD_LOGIC;
  signal mem_reg_0_15_6_11_n_4 : STD_LOGIC;
  signal mem_reg_0_15_6_11_n_5 : STD_LOGIC;
  signal my_empty0 : STD_LOGIC;
  signal \my_empty[1]_i_1__6_n_0\ : STD_LOGIC;
  signal \my_empty[7]_i_1__6_n_0\ : STD_LOGIC;
  signal \my_empty[7]_i_3__6_n_0\ : STD_LOGIC;
  signal \my_empty[7]_i_4__6_n_0\ : STD_LOGIC;
  signal \^my_empty_reg[1]_1\ : STD_LOGIC;
  signal \my_empty_reg_n_0_[7]\ : STD_LOGIC;
  signal my_full0 : STD_LOGIC;
  signal \my_full[4]_i_1__6_n_0\ : STD_LOGIC;
  signal \my_full[4]_i_3__6_n_0\ : STD_LOGIC;
  signal \my_full[4]_i_4__6_n_0\ : STD_LOGIC;
  signal \my_full_reg_n_0_[4]\ : STD_LOGIC;
  signal nxt_rd_ptr : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal nxt_wr_ptr : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \rd_ptr_reg_n_0_[0]\ : STD_LOGIC;
  signal \rd_ptr_reg_n_0_[1]\ : STD_LOGIC;
  signal \rd_ptr_reg_n_0_[2]\ : STD_LOGIC;
  signal \rd_ptr_reg_n_0_[3]\ : STD_LOGIC;
  signal rd_ptr_timing : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \rd_ptr_timing[3]_i_1__6_n_0\ : STD_LOGIC;
  signal wr_en : STD_LOGIC;
  attribute MAX_FANOUT : string;
  attribute MAX_FANOUT of wr_en : signal is "50";
  attribute RTL_MAX_FANOUT : string;
  attribute RTL_MAX_FANOUT of wr_en : signal is "found";
  signal wr_ptr : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal wr_ptr0 : STD_LOGIC;
  signal wr_ptr_timing : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal NLW_mem_reg_0_15_0_5_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_15_12_17_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_15_18_23_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_15_24_29_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_15_30_35_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_15_36_41_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_15_42_47_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_15_48_53_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_15_54_59_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_15_60_65_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_15_66_71_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_15_6_11_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_15_72_77_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_15_78_79_DOB_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_15_78_79_DOC_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_15_78_79_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \entry_cnt[0]_i_1__5\ : label is "soft_lutpair1075";
  attribute SOFT_HLUTNM of \entry_cnt[1]_i_1__5\ : label is "soft_lutpair1074";
  attribute SOFT_HLUTNM of \entry_cnt[3]_i_1__5\ : label is "soft_lutpair1075";
  attribute SOFT_HLUTNM of \entry_cnt[4]_i_3__5\ : label is "soft_lutpair1074";
  attribute METHODOLOGY_DRC_VIOS : string;
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_15_0_5 : label is "";
  attribute RTL_RAM_BITS : integer;
  attribute RTL_RAM_BITS of mem_reg_0_15_0_5 : label is 720;
  attribute RTL_RAM_NAME : string;
  attribute RTL_RAM_NAME of mem_reg_0_15_0_5 : label is "of_pre_fifo_gen.u_ddr_of_pre_fifo/mem";
  attribute ram_addr_begin : integer;
  attribute ram_addr_begin of mem_reg_0_15_0_5 : label is 0;
  attribute ram_addr_end : integer;
  attribute ram_addr_end of mem_reg_0_15_0_5 : label is 8;
  attribute ram_offset : integer;
  attribute ram_offset of mem_reg_0_15_0_5 : label is 0;
  attribute ram_slice_begin : integer;
  attribute ram_slice_begin of mem_reg_0_15_0_5 : label is 0;
  attribute ram_slice_end : integer;
  attribute ram_slice_end of mem_reg_0_15_0_5 : label is 5;
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_15_12_17 : label is "";
  attribute RTL_RAM_BITS of mem_reg_0_15_12_17 : label is 720;
  attribute RTL_RAM_NAME of mem_reg_0_15_12_17 : label is "of_pre_fifo_gen.u_ddr_of_pre_fifo/mem";
  attribute ram_addr_begin of mem_reg_0_15_12_17 : label is 0;
  attribute ram_addr_end of mem_reg_0_15_12_17 : label is 8;
  attribute ram_offset of mem_reg_0_15_12_17 : label is 0;
  attribute ram_slice_begin of mem_reg_0_15_12_17 : label is 12;
  attribute ram_slice_end of mem_reg_0_15_12_17 : label is 17;
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_15_18_23 : label is "";
  attribute RTL_RAM_BITS of mem_reg_0_15_18_23 : label is 720;
  attribute RTL_RAM_NAME of mem_reg_0_15_18_23 : label is "of_pre_fifo_gen.u_ddr_of_pre_fifo/mem";
  attribute ram_addr_begin of mem_reg_0_15_18_23 : label is 0;
  attribute ram_addr_end of mem_reg_0_15_18_23 : label is 8;
  attribute ram_offset of mem_reg_0_15_18_23 : label is 0;
  attribute ram_slice_begin of mem_reg_0_15_18_23 : label is 18;
  attribute ram_slice_end of mem_reg_0_15_18_23 : label is 23;
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_15_24_29 : label is "";
  attribute RTL_RAM_BITS of mem_reg_0_15_24_29 : label is 720;
  attribute RTL_RAM_NAME of mem_reg_0_15_24_29 : label is "of_pre_fifo_gen.u_ddr_of_pre_fifo/mem";
  attribute ram_addr_begin of mem_reg_0_15_24_29 : label is 0;
  attribute ram_addr_end of mem_reg_0_15_24_29 : label is 8;
  attribute ram_offset of mem_reg_0_15_24_29 : label is 0;
  attribute ram_slice_begin of mem_reg_0_15_24_29 : label is 24;
  attribute ram_slice_end of mem_reg_0_15_24_29 : label is 29;
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_15_30_35 : label is "";
  attribute RTL_RAM_BITS of mem_reg_0_15_30_35 : label is 720;
  attribute RTL_RAM_NAME of mem_reg_0_15_30_35 : label is "of_pre_fifo_gen.u_ddr_of_pre_fifo/mem";
  attribute ram_addr_begin of mem_reg_0_15_30_35 : label is 0;
  attribute ram_addr_end of mem_reg_0_15_30_35 : label is 8;
  attribute ram_offset of mem_reg_0_15_30_35 : label is 0;
  attribute ram_slice_begin of mem_reg_0_15_30_35 : label is 30;
  attribute ram_slice_end of mem_reg_0_15_30_35 : label is 35;
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_15_36_41 : label is "";
  attribute RTL_RAM_BITS of mem_reg_0_15_36_41 : label is 720;
  attribute RTL_RAM_NAME of mem_reg_0_15_36_41 : label is "of_pre_fifo_gen.u_ddr_of_pre_fifo/mem";
  attribute ram_addr_begin of mem_reg_0_15_36_41 : label is 0;
  attribute ram_addr_end of mem_reg_0_15_36_41 : label is 8;
  attribute ram_offset of mem_reg_0_15_36_41 : label is 0;
  attribute ram_slice_begin of mem_reg_0_15_36_41 : label is 36;
  attribute ram_slice_end of mem_reg_0_15_36_41 : label is 41;
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_15_42_47 : label is "";
  attribute RTL_RAM_BITS of mem_reg_0_15_42_47 : label is 720;
  attribute RTL_RAM_NAME of mem_reg_0_15_42_47 : label is "of_pre_fifo_gen.u_ddr_of_pre_fifo/mem";
  attribute ram_addr_begin of mem_reg_0_15_42_47 : label is 0;
  attribute ram_addr_end of mem_reg_0_15_42_47 : label is 8;
  attribute ram_offset of mem_reg_0_15_42_47 : label is 0;
  attribute ram_slice_begin of mem_reg_0_15_42_47 : label is 42;
  attribute ram_slice_end of mem_reg_0_15_42_47 : label is 47;
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_15_48_53 : label is "";
  attribute RTL_RAM_BITS of mem_reg_0_15_48_53 : label is 720;
  attribute RTL_RAM_NAME of mem_reg_0_15_48_53 : label is "of_pre_fifo_gen.u_ddr_of_pre_fifo/mem";
  attribute ram_addr_begin of mem_reg_0_15_48_53 : label is 0;
  attribute ram_addr_end of mem_reg_0_15_48_53 : label is 8;
  attribute ram_offset of mem_reg_0_15_48_53 : label is 0;
  attribute ram_slice_begin of mem_reg_0_15_48_53 : label is 48;
  attribute ram_slice_end of mem_reg_0_15_48_53 : label is 53;
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_15_54_59 : label is "";
  attribute RTL_RAM_BITS of mem_reg_0_15_54_59 : label is 720;
  attribute RTL_RAM_NAME of mem_reg_0_15_54_59 : label is "of_pre_fifo_gen.u_ddr_of_pre_fifo/mem";
  attribute ram_addr_begin of mem_reg_0_15_54_59 : label is 0;
  attribute ram_addr_end of mem_reg_0_15_54_59 : label is 8;
  attribute ram_offset of mem_reg_0_15_54_59 : label is 0;
  attribute ram_slice_begin of mem_reg_0_15_54_59 : label is 54;
  attribute ram_slice_end of mem_reg_0_15_54_59 : label is 59;
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_15_60_65 : label is "";
  attribute RTL_RAM_BITS of mem_reg_0_15_60_65 : label is 720;
  attribute RTL_RAM_NAME of mem_reg_0_15_60_65 : label is "of_pre_fifo_gen.u_ddr_of_pre_fifo/mem";
  attribute ram_addr_begin of mem_reg_0_15_60_65 : label is 0;
  attribute ram_addr_end of mem_reg_0_15_60_65 : label is 8;
  attribute ram_offset of mem_reg_0_15_60_65 : label is 0;
  attribute ram_slice_begin of mem_reg_0_15_60_65 : label is 60;
  attribute ram_slice_end of mem_reg_0_15_60_65 : label is 65;
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_15_66_71 : label is "";
  attribute RTL_RAM_BITS of mem_reg_0_15_66_71 : label is 720;
  attribute RTL_RAM_NAME of mem_reg_0_15_66_71 : label is "of_pre_fifo_gen.u_ddr_of_pre_fifo/mem";
  attribute ram_addr_begin of mem_reg_0_15_66_71 : label is 0;
  attribute ram_addr_end of mem_reg_0_15_66_71 : label is 8;
  attribute ram_offset of mem_reg_0_15_66_71 : label is 0;
  attribute ram_slice_begin of mem_reg_0_15_66_71 : label is 66;
  attribute ram_slice_end of mem_reg_0_15_66_71 : label is 71;
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_15_6_11 : label is "";
  attribute RTL_RAM_BITS of mem_reg_0_15_6_11 : label is 720;
  attribute RTL_RAM_NAME of mem_reg_0_15_6_11 : label is "of_pre_fifo_gen.u_ddr_of_pre_fifo/mem";
  attribute ram_addr_begin of mem_reg_0_15_6_11 : label is 0;
  attribute ram_addr_end of mem_reg_0_15_6_11 : label is 8;
  attribute ram_offset of mem_reg_0_15_6_11 : label is 0;
  attribute ram_slice_begin of mem_reg_0_15_6_11 : label is 6;
  attribute ram_slice_end of mem_reg_0_15_6_11 : label is 11;
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_15_72_77 : label is "";
  attribute RTL_RAM_BITS of mem_reg_0_15_72_77 : label is 720;
  attribute RTL_RAM_NAME of mem_reg_0_15_72_77 : label is "of_pre_fifo_gen.u_ddr_of_pre_fifo/mem";
  attribute ram_addr_begin of mem_reg_0_15_72_77 : label is 0;
  attribute ram_addr_end of mem_reg_0_15_72_77 : label is 8;
  attribute ram_offset of mem_reg_0_15_72_77 : label is 0;
  attribute ram_slice_begin of mem_reg_0_15_72_77 : label is 72;
  attribute ram_slice_end of mem_reg_0_15_72_77 : label is 77;
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_15_78_79 : label is "";
  attribute RTL_RAM_BITS of mem_reg_0_15_78_79 : label is 720;
  attribute RTL_RAM_NAME of mem_reg_0_15_78_79 : label is "of_pre_fifo_gen.u_ddr_of_pre_fifo/mem";
  attribute ram_addr_begin of mem_reg_0_15_78_79 : label is 0;
  attribute ram_addr_end of mem_reg_0_15_78_79 : label is 8;
  attribute ram_offset of mem_reg_0_15_78_79 : label is 0;
  attribute ram_slice_begin of mem_reg_0_15_78_79 : label is 78;
  attribute ram_slice_end of mem_reg_0_15_78_79 : label is 79;
  attribute SOFT_HLUTNM of \my_empty[7]_i_3__6\ : label is "soft_lutpair1077";
  attribute SOFT_HLUTNM of \my_empty[7]_i_4__6\ : label is "soft_lutpair1077";
  attribute syn_maxfan : string;
  attribute syn_maxfan of \my_empty_reg[1]\ : label is "3";
  attribute syn_maxfan of \my_empty_reg[7]\ : label is "3";
  attribute SOFT_HLUTNM of \my_full[4]_i_3__6\ : label is "soft_lutpair1076";
  attribute SOFT_HLUTNM of \my_full[4]_i_4__6\ : label is "soft_lutpair1076";
  attribute syn_maxfan of \my_full_reg[4]\ : label is "3";
  attribute SOFT_HLUTNM of \out_fifo_i_10__5\ : label is "soft_lutpair1078";
  attribute SOFT_HLUTNM of \out_fifo_i_11__5\ : label is "soft_lutpair1085";
  attribute SOFT_HLUTNM of \out_fifo_i_12__5\ : label is "soft_lutpair1080";
  attribute SOFT_HLUTNM of \out_fifo_i_13__5\ : label is "soft_lutpair1083";
  attribute SOFT_HLUTNM of \out_fifo_i_14__5\ : label is "soft_lutpair1081";
  attribute SOFT_HLUTNM of \out_fifo_i_15__5\ : label is "soft_lutpair1082";
  attribute SOFT_HLUTNM of \out_fifo_i_16__5\ : label is "soft_lutpair1079";
  attribute SOFT_HLUTNM of \out_fifo_i_17__5\ : label is "soft_lutpair1087";
  attribute SOFT_HLUTNM of \out_fifo_i_2__4\ : label is "soft_lutpair1083";
  attribute SOFT_HLUTNM of \out_fifo_i_3__4\ : label is "soft_lutpair1079";
  attribute SOFT_HLUTNM of \out_fifo_i_4__4\ : label is "soft_lutpair1085";
  attribute SOFT_HLUTNM of \out_fifo_i_5__4\ : label is "soft_lutpair1081";
  attribute SOFT_HLUTNM of \out_fifo_i_6__4\ : label is "soft_lutpair1082";
  attribute SOFT_HLUTNM of \out_fifo_i_7__4\ : label is "soft_lutpair1078";
  attribute SOFT_HLUTNM of \out_fifo_i_8__4\ : label is "soft_lutpair1087";
  attribute SOFT_HLUTNM of \out_fifo_i_9__4\ : label is "soft_lutpair1080";
  attribute syn_maxfan of \rd_ptr_reg[0]\ : label is "10";
  attribute syn_maxfan of \rd_ptr_reg[1]\ : label is "10";
  attribute syn_maxfan of \rd_ptr_reg[2]\ : label is "10";
  attribute syn_maxfan of \rd_ptr_reg[3]\ : label is "10";
  attribute SOFT_HLUTNM of \rd_ptr_timing[0]_i_1__13\ : label is "soft_lutpair1089";
  attribute SOFT_HLUTNM of \rd_ptr_timing[1]_i_1__13\ : label is "soft_lutpair1089";
  attribute SOFT_HLUTNM of \rd_ptr_timing[2]_i_1__6\ : label is "soft_lutpair1086";
  attribute SOFT_HLUTNM of \rd_ptr_timing[3]_i_2__6\ : label is "soft_lutpair1086";
  attribute KEEP : string;
  attribute KEEP of \rd_ptr_timing_reg[0]\ : label is "yes";
  attribute KEEP of \rd_ptr_timing_reg[1]\ : label is "yes";
  attribute KEEP of \rd_ptr_timing_reg[2]\ : label is "yes";
  attribute KEEP of \rd_ptr_timing_reg[3]\ : label is "yes";
  attribute SOFT_HLUTNM of \wr_ptr[0]_i_1__13\ : label is "soft_lutpair1088";
  attribute SOFT_HLUTNM of \wr_ptr[1]_i_1__13\ : label is "soft_lutpair1088";
  attribute SOFT_HLUTNM of \wr_ptr[2]_i_1__6\ : label is "soft_lutpair1084";
  attribute SOFT_HLUTNM of \wr_ptr[3]_i_2__5\ : label is "soft_lutpair1084";
  attribute syn_maxfan of \wr_ptr_reg[0]\ : label is "10";
  attribute syn_maxfan of \wr_ptr_reg[1]\ : label is "10";
  attribute syn_maxfan of \wr_ptr_reg[2]\ : label is "10";
  attribute syn_maxfan of \wr_ptr_reg[3]\ : label is "10";
  attribute KEEP of \wr_ptr_timing_reg[0]\ : label is "yes";
  attribute KEEP of \wr_ptr_timing_reg[1]\ : label is "yes";
  attribute KEEP of \wr_ptr_timing_reg[2]\ : label is "yes";
  attribute KEEP of \wr_ptr_timing_reg[3]\ : label is "yes";
begin
  Q(2 downto 0) <= \^q\(2 downto 0);
  \my_empty_reg[1]_1\ <= \^my_empty_reg[1]_1\;
\entry_cnt[0]_i_1__5\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \entry_cnt_reg_n_0_[0]\,
      O => \entry_cnt[0]_i_1__5_n_0\
    );
\entry_cnt[1]_i_1__5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AA6A5595"
    )
        port map (
      I0 => \entry_cnt_reg_n_0_[0]\,
      I1 => \my_empty_reg[7]_0\,
      I2 => phy_data_wr_en,
      I3 => \my_full_reg_n_0_[4]\,
      I4 => \entry_cnt_reg_n_0_[1]\,
      O => \entry_cnt[1]_i_1__5_n_0\
    );
\entry_cnt[2]_i_1__5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FF7F0080AAEA5515"
    )
        port map (
      I0 => \entry_cnt_reg_n_0_[0]\,
      I1 => \my_empty_reg[7]_0\,
      I2 => phy_data_wr_en,
      I3 => \my_full_reg_n_0_[4]\,
      I4 => \^q\(0),
      I5 => \entry_cnt_reg_n_0_[1]\,
      O => \entry_cnt[2]_i_1__5_n_0\
    );
\entry_cnt[3]_i_1__5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"7F80FE01"
    )
        port map (
      I0 => \entry_cnt10_out__0\,
      I1 => \entry_cnt_reg_n_0_[0]\,
      I2 => \entry_cnt_reg_n_0_[1]\,
      I3 => \^q\(1),
      I4 => \^q\(0),
      O => \entry_cnt[3]_i_1__5_n_0\
    );
\entry_cnt[4]_i_1__5\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"5003"
    )
        port map (
      I0 => \my_full_reg_n_0_[4]\,
      I1 => \my_empty_reg_n_0_[7]\,
      I2 => \my_empty_reg[7]_0\,
      I3 => phy_data_wr_en,
      O => \entry_cnt[4]_i_1__5_n_0\
    );
\entry_cnt[4]_i_2__5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"7FFF8000FFFE0001"
    )
        port map (
      I0 => \entry_cnt_reg_n_0_[1]\,
      I1 => \entry_cnt_reg_n_0_[0]\,
      I2 => \entry_cnt10_out__0\,
      I3 => \^q\(0),
      I4 => \^q\(2),
      I5 => \^q\(1),
      O => \entry_cnt[4]_i_2__5_n_0\
    );
\entry_cnt[4]_i_3__5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"08"
    )
        port map (
      I0 => \my_empty_reg[7]_0\,
      I1 => phy_data_wr_en,
      I2 => \my_full_reg_n_0_[4]\,
      O => \entry_cnt10_out__0\
    );
\entry_cnt_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_ptr_timing_reg[3]_0\,
      CE => \entry_cnt[4]_i_1__5_n_0\,
      D => \entry_cnt[0]_i_1__5_n_0\,
      Q => \entry_cnt_reg_n_0_[0]\,
      R => ofifo_rst
    );
\entry_cnt_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_ptr_timing_reg[3]_0\,
      CE => \entry_cnt[4]_i_1__5_n_0\,
      D => \entry_cnt[1]_i_1__5_n_0\,
      Q => \entry_cnt_reg_n_0_[1]\,
      R => ofifo_rst
    );
\entry_cnt_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_ptr_timing_reg[3]_0\,
      CE => \entry_cnt[4]_i_1__5_n_0\,
      D => \entry_cnt[2]_i_1__5_n_0\,
      Q => \^q\(0),
      R => ofifo_rst
    );
\entry_cnt_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_ptr_timing_reg[3]_0\,
      CE => \entry_cnt[4]_i_1__5_n_0\,
      D => \entry_cnt[3]_i_1__5_n_0\,
      Q => \^q\(1),
      R => ofifo_rst
    );
\entry_cnt_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_ptr_timing_reg[3]_0\,
      CE => \entry_cnt[4]_i_1__5_n_0\,
      D => \entry_cnt[4]_i_2__5_n_0\,
      Q => \^q\(2),
      R => ofifo_rst
    );
mem_reg_0_15_0_5: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4) => '0',
      ADDRA(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRA(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRA(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRA(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRB(4) => '0',
      ADDRB(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRB(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRB(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRB(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRC(4) => '0',
      ADDRC(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRC(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRC(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRC(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRD(4) => '0',
      ADDRD(3 downto 0) => wr_ptr(3 downto 0),
      DIA(1 downto 0) => B"00",
      DIB(1 downto 0) => B"00",
      DIC(1 downto 0) => B"00",
      DID(1 downto 0) => B"00",
      DOA(1) => mem_reg_0_15_0_5_n_0,
      DOA(0) => mem_reg_0_15_0_5_n_1,
      DOB(1) => mem_reg_0_15_0_5_n_2,
      DOB(0) => mem_reg_0_15_0_5_n_3,
      DOC(1) => mem_reg_0_15_0_5_n_4,
      DOC(0) => mem_reg_0_15_0_5_n_5,
      DOD(1 downto 0) => NLW_mem_reg_0_15_0_5_DOD_UNCONNECTED(1 downto 0),
      WCLK => \wr_ptr_timing_reg[3]_0\,
      WE => wr_en
    );
\mem_reg_0_15_0_5_i_1__5\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2700"
    )
        port map (
      I0 => \my_empty_reg[7]_0\,
      I1 => \my_full_reg_n_0_[4]\,
      I2 => \^my_empty_reg[1]_1\,
      I3 => phy_data_wr_en,
      O => wr_en
    );
mem_reg_0_15_12_17: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4) => '0',
      ADDRA(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRA(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRA(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRA(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRB(4) => '0',
      ADDRB(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRB(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRB(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRB(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRC(4) => '0',
      ADDRC(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRC(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRC(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRC(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRD(4) => '0',
      ADDRD(3 downto 0) => wr_ptr(3 downto 0),
      DIA(1 downto 0) => \out_fifo_i_75__2\(5 downto 4),
      DIB(1 downto 0) => \out_fifo_i_75__2\(7 downto 6),
      DIC(1 downto 0) => \out_fifo_i_75__2\(9 downto 8),
      DID(1 downto 0) => B"00",
      DOA(1) => mem_reg_0_15_12_17_n_0,
      DOA(0) => mem_reg_0_15_12_17_n_1,
      DOB(1) => mem_reg_0_15_12_17_n_2,
      DOB(0) => mem_reg_0_15_12_17_n_3,
      DOC(1 downto 0) => \rd_ptr_reg[3]_0\(1 downto 0),
      DOD(1 downto 0) => NLW_mem_reg_0_15_12_17_DOD_UNCONNECTED(1 downto 0),
      WCLK => \wr_ptr_timing_reg[3]_0\,
      WE => wr_en
    );
mem_reg_0_15_18_23: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4) => '0',
      ADDRA(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRA(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRA(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRA(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRB(4) => '0',
      ADDRB(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRB(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRB(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRB(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRC(4) => '0',
      ADDRC(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRC(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRC(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRC(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRD(4) => '0',
      ADDRD(3 downto 0) => wr_ptr(3 downto 0),
      DIA(1 downto 0) => \out_fifo_i_75__2\(11 downto 10),
      DIB(1 downto 0) => \out_fifo_i_75__2\(13 downto 12),
      DIC(1 downto 0) => \out_fifo_i_75__2\(15 downto 14),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => \rd_ptr_reg[3]_0\(3 downto 2),
      DOB(1 downto 0) => \rd_ptr_reg[3]_0\(5 downto 4),
      DOC(1 downto 0) => \rd_ptr_reg[3]_0\(7 downto 6),
      DOD(1 downto 0) => NLW_mem_reg_0_15_18_23_DOD_UNCONNECTED(1 downto 0),
      WCLK => \wr_ptr_timing_reg[3]_0\,
      WE => wr_en
    );
mem_reg_0_15_24_29: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4) => '0',
      ADDRA(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRA(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRA(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRA(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRB(4) => '0',
      ADDRB(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRB(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRB(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRB(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRC(4) => '0',
      ADDRC(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRC(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRC(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRC(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRD(4) => '0',
      ADDRD(3 downto 0) => wr_ptr(3 downto 0),
      DIA(1 downto 0) => \out_fifo_i_75__2\(17 downto 16),
      DIB(1 downto 0) => \out_fifo_i_75__2\(19 downto 18),
      DIC(1 downto 0) => \out_fifo_i_75__2\(21 downto 20),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => \rd_ptr_reg[3]_0\(9 downto 8),
      DOB(1 downto 0) => \rd_ptr_reg[3]_0\(11 downto 10),
      DOC(1 downto 0) => \rd_ptr_reg[3]_0\(13 downto 12),
      DOD(1 downto 0) => NLW_mem_reg_0_15_24_29_DOD_UNCONNECTED(1 downto 0),
      WCLK => \wr_ptr_timing_reg[3]_0\,
      WE => wr_en
    );
mem_reg_0_15_30_35: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4) => '0',
      ADDRA(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRA(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRA(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRA(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRB(4) => '0',
      ADDRB(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRB(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRB(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRB(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRC(4) => '0',
      ADDRC(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRC(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRC(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRC(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRD(4) => '0',
      ADDRD(3 downto 0) => wr_ptr(3 downto 0),
      DIA(1 downto 0) => \out_fifo_i_75__2\(23 downto 22),
      DIB(1 downto 0) => \out_fifo_i_75__2\(25 downto 24),
      DIC(1 downto 0) => \out_fifo_i_75__2\(27 downto 26),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => \rd_ptr_reg[3]_0\(15 downto 14),
      DOB(1 downto 0) => \rd_ptr_reg[3]_0\(17 downto 16),
      DOC(1 downto 0) => \rd_ptr_reg[3]_0\(19 downto 18),
      DOD(1 downto 0) => NLW_mem_reg_0_15_30_35_DOD_UNCONNECTED(1 downto 0),
      WCLK => \wr_ptr_timing_reg[3]_0\,
      WE => wr_en
    );
mem_reg_0_15_36_41: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4) => '0',
      ADDRA(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRA(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRA(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRA(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRB(4) => '0',
      ADDRB(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRB(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRB(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRB(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRC(4) => '0',
      ADDRC(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRC(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRC(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRC(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRD(4) => '0',
      ADDRD(3 downto 0) => wr_ptr(3 downto 0),
      DIA(1 downto 0) => \out_fifo_i_75__2\(29 downto 28),
      DIB(1 downto 0) => \out_fifo_i_75__2\(31 downto 30),
      DIC(1 downto 0) => \out_fifo_i_75__2\(33 downto 32),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => \rd_ptr_reg[3]_0\(21 downto 20),
      DOB(1 downto 0) => \rd_ptr_reg[3]_0\(23 downto 22),
      DOC(1 downto 0) => \rd_ptr_reg[3]_0\(25 downto 24),
      DOD(1 downto 0) => NLW_mem_reg_0_15_36_41_DOD_UNCONNECTED(1 downto 0),
      WCLK => \wr_ptr_timing_reg[3]_0\,
      WE => wr_en
    );
mem_reg_0_15_42_47: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4) => '0',
      ADDRA(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRA(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRA(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRA(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRB(4) => '0',
      ADDRB(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRB(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRB(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRB(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRC(4) => '0',
      ADDRC(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRC(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRC(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRC(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRD(4) => '0',
      ADDRD(3 downto 0) => wr_ptr(3 downto 0),
      DIA(1 downto 0) => \out_fifo_i_75__2\(35 downto 34),
      DIB(1 downto 0) => \out_fifo_i_75__2\(37 downto 36),
      DIC(1 downto 0) => \out_fifo_i_75__2\(39 downto 38),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => \rd_ptr_reg[3]_0\(27 downto 26),
      DOB(1 downto 0) => \rd_ptr_reg[3]_0\(29 downto 28),
      DOC(1 downto 0) => \rd_ptr_reg[3]_0\(31 downto 30),
      DOD(1 downto 0) => NLW_mem_reg_0_15_42_47_DOD_UNCONNECTED(1 downto 0),
      WCLK => \wr_ptr_timing_reg[3]_0\,
      WE => wr_en
    );
mem_reg_0_15_48_53: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4) => '0',
      ADDRA(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRA(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRA(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRA(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRB(4) => '0',
      ADDRB(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRB(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRB(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRB(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRC(4) => '0',
      ADDRC(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRC(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRC(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRC(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRD(4) => '0',
      ADDRD(3 downto 0) => wr_ptr(3 downto 0),
      DIA(1 downto 0) => \out_fifo_i_75__2\(41 downto 40),
      DIB(1 downto 0) => \out_fifo_i_75__2\(43 downto 42),
      DIC(1 downto 0) => \out_fifo_i_75__2\(45 downto 44),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => \rd_ptr_reg[3]_0\(33 downto 32),
      DOB(1 downto 0) => \rd_ptr_reg[3]_0\(35 downto 34),
      DOC(1 downto 0) => \rd_ptr_reg[3]_0\(37 downto 36),
      DOD(1 downto 0) => NLW_mem_reg_0_15_48_53_DOD_UNCONNECTED(1 downto 0),
      WCLK => \wr_ptr_timing_reg[3]_0\,
      WE => wr_en
    );
mem_reg_0_15_54_59: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4) => '0',
      ADDRA(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRA(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRA(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRA(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRB(4) => '0',
      ADDRB(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRB(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRB(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRB(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRC(4) => '0',
      ADDRC(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRC(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRC(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRC(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRD(4) => '0',
      ADDRD(3 downto 0) => wr_ptr(3 downto 0),
      DIA(1 downto 0) => \out_fifo_i_75__2\(47 downto 46),
      DIB(1 downto 0) => \out_fifo_i_75__2\(49 downto 48),
      DIC(1 downto 0) => \out_fifo_i_75__2\(51 downto 50),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => \rd_ptr_reg[3]_0\(39 downto 38),
      DOB(1 downto 0) => \rd_ptr_reg[3]_0\(41 downto 40),
      DOC(1 downto 0) => \rd_ptr_reg[3]_0\(43 downto 42),
      DOD(1 downto 0) => NLW_mem_reg_0_15_54_59_DOD_UNCONNECTED(1 downto 0),
      WCLK => \wr_ptr_timing_reg[3]_0\,
      WE => wr_en
    );
mem_reg_0_15_60_65: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4) => '0',
      ADDRA(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRA(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRA(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRA(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRB(4) => '0',
      ADDRB(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRB(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRB(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRB(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRC(4) => '0',
      ADDRC(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRC(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRC(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRC(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRD(4) => '0',
      ADDRD(3 downto 0) => wr_ptr(3 downto 0),
      DIA(1 downto 0) => \out_fifo_i_75__2\(53 downto 52),
      DIB(1 downto 0) => \out_fifo_i_75__2\(55 downto 54),
      DIC(1 downto 0) => \out_fifo_i_75__2\(57 downto 56),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => \rd_ptr_reg[3]_0\(45 downto 44),
      DOB(1 downto 0) => \rd_ptr_reg[3]_0\(47 downto 46),
      DOC(1 downto 0) => \rd_ptr_reg[3]_0\(49 downto 48),
      DOD(1 downto 0) => NLW_mem_reg_0_15_60_65_DOD_UNCONNECTED(1 downto 0),
      WCLK => \wr_ptr_timing_reg[3]_0\,
      WE => wr_en
    );
mem_reg_0_15_66_71: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4) => '0',
      ADDRA(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRA(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRA(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRA(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRB(4) => '0',
      ADDRB(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRB(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRB(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRB(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRC(4) => '0',
      ADDRC(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRC(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRC(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRC(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRD(4) => '0',
      ADDRD(3 downto 0) => wr_ptr(3 downto 0),
      DIA(1 downto 0) => \out_fifo_i_75__2\(59 downto 58),
      DIB(1 downto 0) => \out_fifo_i_75__2\(61 downto 60),
      DIC(1 downto 0) => \out_fifo_i_75__2\(63 downto 62),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => \rd_ptr_reg[3]_0\(51 downto 50),
      DOB(1 downto 0) => \rd_ptr_reg[3]_0\(53 downto 52),
      DOC(1 downto 0) => \rd_ptr_reg[3]_0\(55 downto 54),
      DOD(1 downto 0) => NLW_mem_reg_0_15_66_71_DOD_UNCONNECTED(1 downto 0),
      WCLK => \wr_ptr_timing_reg[3]_0\,
      WE => wr_en
    );
mem_reg_0_15_6_11: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4) => '0',
      ADDRA(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRA(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRA(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRA(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRB(4) => '0',
      ADDRB(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRB(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRB(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRB(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRC(4) => '0',
      ADDRC(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRC(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRC(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRC(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRD(4) => '0',
      ADDRD(3 downto 0) => wr_ptr(3 downto 0),
      DIA(1 downto 0) => B"00",
      DIB(1 downto 0) => \out_fifo_i_75__2\(1 downto 0),
      DIC(1 downto 0) => \out_fifo_i_75__2\(3 downto 2),
      DID(1 downto 0) => B"00",
      DOA(1) => mem_reg_0_15_6_11_n_0,
      DOA(0) => mem_reg_0_15_6_11_n_1,
      DOB(1) => mem_reg_0_15_6_11_n_2,
      DOB(0) => mem_reg_0_15_6_11_n_3,
      DOC(1) => mem_reg_0_15_6_11_n_4,
      DOC(0) => mem_reg_0_15_6_11_n_5,
      DOD(1 downto 0) => NLW_mem_reg_0_15_6_11_DOD_UNCONNECTED(1 downto 0),
      WCLK => \wr_ptr_timing_reg[3]_0\,
      WE => wr_en
    );
mem_reg_0_15_72_77: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4) => '0',
      ADDRA(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRA(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRA(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRA(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRB(4) => '0',
      ADDRB(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRB(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRB(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRB(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRC(4) => '0',
      ADDRC(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRC(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRC(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRC(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRD(4) => '0',
      ADDRD(3 downto 0) => wr_ptr(3 downto 0),
      DIA(1 downto 0) => \out_fifo_i_75__2\(65 downto 64),
      DIB(1 downto 0) => \out_fifo_i_75__2\(67 downto 66),
      DIC(1 downto 0) => \out_fifo_i_75__2\(69 downto 68),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => \rd_ptr_reg[3]_0\(57 downto 56),
      DOB(1 downto 0) => \rd_ptr_reg[3]_0\(59 downto 58),
      DOC(1 downto 0) => \rd_ptr_reg[3]_0\(61 downto 60),
      DOD(1 downto 0) => NLW_mem_reg_0_15_72_77_DOD_UNCONNECTED(1 downto 0),
      WCLK => \wr_ptr_timing_reg[3]_0\,
      WE => wr_en
    );
mem_reg_0_15_78_79: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4) => '0',
      ADDRA(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRA(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRA(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRA(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRB(4) => '0',
      ADDRB(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRB(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRB(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRB(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRC(4) => '0',
      ADDRC(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRC(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRC(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRC(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRD(4) => '0',
      ADDRD(3 downto 0) => wr_ptr(3 downto 0),
      DIA(1 downto 0) => \out_fifo_i_75__2\(71 downto 70),
      DIB(1 downto 0) => B"00",
      DIC(1 downto 0) => B"00",
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => \rd_ptr_reg[3]_0\(63 downto 62),
      DOB(1 downto 0) => NLW_mem_reg_0_15_78_79_DOB_UNCONNECTED(1 downto 0),
      DOC(1 downto 0) => NLW_mem_reg_0_15_78_79_DOC_UNCONNECTED(1 downto 0),
      DOD(1 downto 0) => NLW_mem_reg_0_15_78_79_DOD_UNCONNECTED(1 downto 0),
      WCLK => \wr_ptr_timing_reg[3]_0\,
      WE => wr_en
    );
\my_empty[1]_i_1__6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFF701F700"
    )
        port map (
      I0 => \my_empty_reg[7]_0\,
      I1 => phy_data_wr_en,
      I2 => \my_full_reg_n_0_[4]\,
      I3 => \^my_empty_reg[1]_1\,
      I4 => my_empty0,
      I5 => ofifo_rst,
      O => \my_empty[1]_i_1__6_n_0\
    );
\my_empty[7]_i_1__6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFF701F700"
    )
        port map (
      I0 => \my_empty_reg[7]_0\,
      I1 => phy_data_wr_en,
      I2 => \my_full_reg_n_0_[4]\,
      I3 => \my_empty_reg_n_0_[7]\,
      I4 => my_empty0,
      I5 => ofifo_rst,
      O => \my_empty[7]_i_1__6_n_0\
    );
\my_empty[7]_i_2__6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"4A400D08"
    )
        port map (
      I0 => wr_ptr_timing(2),
      I1 => \my_empty[7]_i_3__6_n_0\,
      I2 => wr_ptr_timing(3),
      I3 => \my_empty[7]_i_4__6_n_0\,
      I4 => \rd_ptr_reg_n_0_[2]\,
      O => my_empty0
    );
\my_empty[7]_i_3__6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000040"
    )
        port map (
      I0 => wr_ptr_timing(1),
      I1 => \rd_ptr_reg_n_0_[0]\,
      I2 => \rd_ptr_reg_n_0_[1]\,
      I3 => \rd_ptr_reg_n_0_[3]\,
      I4 => wr_ptr_timing(0),
      O => \my_empty[7]_i_3__6_n_0\
    );
\my_empty[7]_i_4__6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"84210842"
    )
        port map (
      I0 => wr_ptr_timing(0),
      I1 => wr_ptr_timing(1),
      I2 => \rd_ptr_reg_n_0_[0]\,
      I3 => \rd_ptr_reg_n_0_[1]\,
      I4 => \rd_ptr_reg_n_0_[3]\,
      O => \my_empty[7]_i_4__6_n_0\
    );
\my_empty_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_ptr_timing_reg[3]_0\,
      CE => '1',
      D => \my_empty[1]_i_1__6_n_0\,
      Q => \^my_empty_reg[1]_1\,
      R => '0'
    );
\my_empty_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_ptr_timing_reg[3]_0\,
      CE => '1',
      D => \my_empty[7]_i_1__6_n_0\,
      Q => \my_empty_reg_n_0_[7]\,
      R => '0'
    );
\my_full[4]_i_1__6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000FFFC0080"
    )
        port map (
      I0 => my_full0,
      I1 => phy_data_wr_en,
      I2 => \my_empty_reg[7]_0\,
      I3 => \my_empty_reg_n_0_[7]\,
      I4 => \my_full_reg_n_0_[4]\,
      I5 => ofifo_rst,
      O => \my_full[4]_i_1__6_n_0\
    );
\my_full[4]_i_2__6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"4A400D08"
    )
        port map (
      I0 => rd_ptr_timing(2),
      I1 => \my_full[4]_i_3__6_n_0\,
      I2 => rd_ptr_timing(3),
      I3 => \my_full[4]_i_4__6_n_0\,
      I4 => wr_ptr(2),
      O => my_full0
    );
\my_full[4]_i_3__6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000040"
    )
        port map (
      I0 => rd_ptr_timing(1),
      I1 => wr_ptr(0),
      I2 => wr_ptr(1),
      I3 => wr_ptr(3),
      I4 => rd_ptr_timing(0),
      O => \my_full[4]_i_3__6_n_0\
    );
\my_full[4]_i_4__6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"84210842"
    )
        port map (
      I0 => rd_ptr_timing(0),
      I1 => rd_ptr_timing(1),
      I2 => wr_ptr(0),
      I3 => wr_ptr(1),
      I4 => wr_ptr(3),
      O => \my_full[4]_i_4__6_n_0\
    );
\my_full_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_ptr_timing_reg[3]_0\,
      CE => '1',
      D => \my_full[4]_i_1__6_n_0\,
      Q => \my_full_reg_n_0_[4]\,
      R => '0'
    );
\out_fifo_i_10__5\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"88F0"
    )
        port map (
      I0 => out_fifo_1,
      I1 => out_fifo_0(7),
      I2 => mem_reg_0_15_12_17_n_2,
      I3 => \^my_empty_reg[1]_1\,
      O => D1(7)
    );
\out_fifo_i_11__5\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"88F0"
    )
        port map (
      I0 => out_fifo_1,
      I1 => out_fifo_0(6),
      I2 => mem_reg_0_15_12_17_n_3,
      I3 => \^my_empty_reg[1]_1\,
      O => D1(6)
    );
\out_fifo_i_12__5\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"88F0"
    )
        port map (
      I0 => out_fifo_1,
      I1 => out_fifo_0(5),
      I2 => mem_reg_0_15_12_17_n_0,
      I3 => \^my_empty_reg[1]_1\,
      O => D1(5)
    );
\out_fifo_i_13__5\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"88F0"
    )
        port map (
      I0 => out_fifo_1,
      I1 => out_fifo_0(4),
      I2 => mem_reg_0_15_12_17_n_1,
      I3 => \^my_empty_reg[1]_1\,
      O => D1(4)
    );
\out_fifo_i_14__5\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"88F0"
    )
        port map (
      I0 => out_fifo_1,
      I1 => out_fifo_0(3),
      I2 => mem_reg_0_15_6_11_n_4,
      I3 => \^my_empty_reg[1]_1\,
      O => D1(3)
    );
\out_fifo_i_15__5\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"88F0"
    )
        port map (
      I0 => out_fifo_1,
      I1 => out_fifo_0(2),
      I2 => mem_reg_0_15_6_11_n_5,
      I3 => \^my_empty_reg[1]_1\,
      O => D1(2)
    );
\out_fifo_i_16__5\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"88F0"
    )
        port map (
      I0 => out_fifo,
      I1 => out_fifo_0(1),
      I2 => mem_reg_0_15_6_11_n_2,
      I3 => \^my_empty_reg[1]_1\,
      O => D1(1)
    );
\out_fifo_i_17__5\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"88F0"
    )
        port map (
      I0 => out_fifo,
      I1 => out_fifo_0(0),
      I2 => mem_reg_0_15_6_11_n_3,
      I3 => \^my_empty_reg[1]_1\,
      O => D1(0)
    );
\out_fifo_i_1__6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"0D"
    )
        port map (
      I0 => \^my_empty_reg[1]_1\,
      I1 => phy_data_wr_en,
      I2 => \my_empty_reg[7]_0\,
      O => \my_empty_reg[1]_0\
    );
\out_fifo_i_2__4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => mem_reg_0_15_6_11_n_0,
      I1 => \^my_empty_reg[1]_1\,
      O => D0(7)
    );
\out_fifo_i_3__4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => mem_reg_0_15_6_11_n_1,
      I1 => \^my_empty_reg[1]_1\,
      O => D0(6)
    );
\out_fifo_i_4__4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => mem_reg_0_15_0_5_n_4,
      I1 => \^my_empty_reg[1]_1\,
      O => D0(5)
    );
\out_fifo_i_5__4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => mem_reg_0_15_0_5_n_5,
      I1 => \^my_empty_reg[1]_1\,
      O => D0(4)
    );
\out_fifo_i_6__4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => mem_reg_0_15_0_5_n_2,
      I1 => \^my_empty_reg[1]_1\,
      O => D0(3)
    );
\out_fifo_i_7__4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => mem_reg_0_15_0_5_n_3,
      I1 => \^my_empty_reg[1]_1\,
      O => D0(2)
    );
\out_fifo_i_8__4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => mem_reg_0_15_0_5_n_0,
      I1 => \^my_empty_reg[1]_1\,
      O => D0(1)
    );
\out_fifo_i_9__4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => mem_reg_0_15_0_5_n_1,
      I1 => \^my_empty_reg[1]_1\,
      O => D0(0)
    );
\rd_ptr_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_ptr_timing_reg[3]_0\,
      CE => \rd_ptr_timing[3]_i_1__6_n_0\,
      D => nxt_rd_ptr(0),
      Q => \rd_ptr_reg_n_0_[0]\,
      R => ofifo_rst
    );
\rd_ptr_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_ptr_timing_reg[3]_0\,
      CE => \rd_ptr_timing[3]_i_1__6_n_0\,
      D => nxt_rd_ptr(1),
      Q => \rd_ptr_reg_n_0_[1]\,
      R => ofifo_rst
    );
\rd_ptr_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_ptr_timing_reg[3]_0\,
      CE => \rd_ptr_timing[3]_i_1__6_n_0\,
      D => nxt_rd_ptr(2),
      Q => \rd_ptr_reg_n_0_[2]\,
      R => ofifo_rst
    );
\rd_ptr_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_ptr_timing_reg[3]_0\,
      CE => \rd_ptr_timing[3]_i_1__6_n_0\,
      D => nxt_rd_ptr(3),
      Q => \rd_ptr_reg_n_0_[3]\,
      R => ofifo_rst
    );
\rd_ptr_timing[0]_i_1__13\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => \rd_ptr_reg_n_0_[3]\,
      I1 => \rd_ptr_reg_n_0_[0]\,
      O => nxt_rd_ptr(0)
    );
\rd_ptr_timing[1]_i_1__13\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B4"
    )
        port map (
      I0 => \rd_ptr_reg_n_0_[3]\,
      I1 => \rd_ptr_reg_n_0_[0]\,
      I2 => \rd_ptr_reg_n_0_[1]\,
      O => nxt_rd_ptr(1)
    );
\rd_ptr_timing[2]_i_1__6\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"AA6A"
    )
        port map (
      I0 => \rd_ptr_reg_n_0_[2]\,
      I1 => \rd_ptr_reg_n_0_[0]\,
      I2 => \rd_ptr_reg_n_0_[1]\,
      I3 => \rd_ptr_reg_n_0_[3]\,
      O => nxt_rd_ptr(2)
    );
\rd_ptr_timing[3]_i_1__6\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \my_empty_reg[7]_0\,
      I1 => \my_empty_reg_n_0_[7]\,
      O => \rd_ptr_timing[3]_i_1__6_n_0\
    );
\rd_ptr_timing[3]_i_2__6\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4000"
    )
        port map (
      I0 => \rd_ptr_reg_n_0_[3]\,
      I1 => \rd_ptr_reg_n_0_[1]\,
      I2 => \rd_ptr_reg_n_0_[0]\,
      I3 => \rd_ptr_reg_n_0_[2]\,
      O => nxt_rd_ptr(3)
    );
\rd_ptr_timing_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_ptr_timing_reg[3]_0\,
      CE => \rd_ptr_timing[3]_i_1__6_n_0\,
      D => nxt_rd_ptr(0),
      Q => rd_ptr_timing(0),
      R => ofifo_rst
    );
\rd_ptr_timing_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_ptr_timing_reg[3]_0\,
      CE => \rd_ptr_timing[3]_i_1__6_n_0\,
      D => nxt_rd_ptr(1),
      Q => rd_ptr_timing(1),
      R => ofifo_rst
    );
\rd_ptr_timing_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_ptr_timing_reg[3]_0\,
      CE => \rd_ptr_timing[3]_i_1__6_n_0\,
      D => nxt_rd_ptr(2),
      Q => rd_ptr_timing(2),
      R => ofifo_rst
    );
\rd_ptr_timing_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_ptr_timing_reg[3]_0\,
      CE => \rd_ptr_timing[3]_i_1__6_n_0\,
      D => nxt_rd_ptr(3),
      Q => rd_ptr_timing(3),
      R => ofifo_rst
    );
\wr_ptr[0]_i_1__13\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => wr_ptr(3),
      I1 => wr_ptr(0),
      O => nxt_wr_ptr(0)
    );
\wr_ptr[1]_i_1__13\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B4"
    )
        port map (
      I0 => wr_ptr(3),
      I1 => wr_ptr(0),
      I2 => wr_ptr(1),
      O => nxt_wr_ptr(1)
    );
\wr_ptr[2]_i_1__6\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"AA6A"
    )
        port map (
      I0 => wr_ptr(2),
      I1 => wr_ptr(0),
      I2 => wr_ptr(1),
      I3 => wr_ptr(3),
      O => nxt_wr_ptr(2)
    );
\wr_ptr[3]_i_1__6\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"082A"
    )
        port map (
      I0 => phy_data_wr_en,
      I1 => \my_empty_reg[7]_0\,
      I2 => \my_full_reg_n_0_[4]\,
      I3 => \my_empty_reg_n_0_[7]\,
      O => wr_ptr0
    );
\wr_ptr[3]_i_2__5\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4000"
    )
        port map (
      I0 => wr_ptr(3),
      I1 => wr_ptr(1),
      I2 => wr_ptr(0),
      I3 => wr_ptr(2),
      O => nxt_wr_ptr(3)
    );
\wr_ptr_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_ptr_timing_reg[3]_0\,
      CE => wr_ptr0,
      D => nxt_wr_ptr(0),
      Q => wr_ptr(0),
      R => ofifo_rst
    );
\wr_ptr_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_ptr_timing_reg[3]_0\,
      CE => wr_ptr0,
      D => nxt_wr_ptr(1),
      Q => wr_ptr(1),
      R => ofifo_rst
    );
\wr_ptr_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_ptr_timing_reg[3]_0\,
      CE => wr_ptr0,
      D => nxt_wr_ptr(2),
      Q => wr_ptr(2),
      R => ofifo_rst
    );
\wr_ptr_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_ptr_timing_reg[3]_0\,
      CE => wr_ptr0,
      D => nxt_wr_ptr(3),
      Q => wr_ptr(3),
      R => ofifo_rst
    );
\wr_ptr_timing_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_ptr_timing_reg[3]_0\,
      CE => wr_ptr0,
      D => nxt_wr_ptr(0),
      Q => wr_ptr_timing(0),
      R => ofifo_rst
    );
\wr_ptr_timing_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_ptr_timing_reg[3]_0\,
      CE => wr_ptr0,
      D => nxt_wr_ptr(1),
      Q => wr_ptr_timing(1),
      R => ofifo_rst
    );
\wr_ptr_timing_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_ptr_timing_reg[3]_0\,
      CE => wr_ptr0,
      D => nxt_wr_ptr(2),
      Q => wr_ptr_timing(2),
      R => ofifo_rst
    );
\wr_ptr_timing_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_ptr_timing_reg[3]_0\,
      CE => wr_ptr0,
      D => nxt_wr_ptr(3),
      Q => wr_ptr_timing(3),
      R => ofifo_rst
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \mig_mig_7series_v4_2_ddr_of_pre_fifo__parameterized1_19\ is
  port (
    \my_empty_reg[1]_0\ : out STD_LOGIC;
    \my_empty_reg[1]_1\ : out STD_LOGIC;
    D0 : out STD_LOGIC_VECTOR ( 7 downto 0 );
    D1 : out STD_LOGIC_VECTOR ( 7 downto 0 );
    \rd_ptr_reg[3]_0\ : out STD_LOGIC_VECTOR ( 63 downto 0 );
    Q : out STD_LOGIC_VECTOR ( 2 downto 0 );
    ofifo_rst : in STD_LOGIC;
    \entry_cnt_reg[4]_0\ : in STD_LOGIC;
    \my_empty_reg[7]_0\ : in STD_LOGIC;
    phy_data_wr_en : in STD_LOGIC;
    out_fifo : in STD_LOGIC;
    out_fifo_0 : in STD_LOGIC_VECTOR ( 7 downto 0 );
    out_fifo_1 : in STD_LOGIC;
    \out_fifo_i_75__1\ : in STD_LOGIC_VECTOR ( 71 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \mig_mig_7series_v4_2_ddr_of_pre_fifo__parameterized1_19\ : entity is "mig_7series_v4_2_ddr_of_pre_fifo";
end \mig_mig_7series_v4_2_ddr_of_pre_fifo__parameterized1_19\;

architecture STRUCTURE of \mig_mig_7series_v4_2_ddr_of_pre_fifo__parameterized1_19\ is
  signal \^q\ : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal \entry_cnt10_out__0\ : STD_LOGIC;
  signal \entry_cnt[0]_i_1__4_n_0\ : STD_LOGIC;
  signal \entry_cnt[1]_i_1__4_n_0\ : STD_LOGIC;
  signal \entry_cnt[2]_i_1__4_n_0\ : STD_LOGIC;
  signal \entry_cnt[3]_i_1__4_n_0\ : STD_LOGIC;
  signal \entry_cnt[4]_i_1__4_n_0\ : STD_LOGIC;
  signal \entry_cnt[4]_i_2__4_n_0\ : STD_LOGIC;
  signal \entry_cnt_reg_n_0_[0]\ : STD_LOGIC;
  signal \entry_cnt_reg_n_0_[1]\ : STD_LOGIC;
  signal mem_reg_0_15_0_5_n_0 : STD_LOGIC;
  signal mem_reg_0_15_0_5_n_1 : STD_LOGIC;
  signal mem_reg_0_15_0_5_n_2 : STD_LOGIC;
  signal mem_reg_0_15_0_5_n_3 : STD_LOGIC;
  signal mem_reg_0_15_0_5_n_4 : STD_LOGIC;
  signal mem_reg_0_15_0_5_n_5 : STD_LOGIC;
  signal mem_reg_0_15_12_17_n_0 : STD_LOGIC;
  signal mem_reg_0_15_12_17_n_1 : STD_LOGIC;
  signal mem_reg_0_15_12_17_n_2 : STD_LOGIC;
  signal mem_reg_0_15_12_17_n_3 : STD_LOGIC;
  signal mem_reg_0_15_6_11_n_0 : STD_LOGIC;
  signal mem_reg_0_15_6_11_n_1 : STD_LOGIC;
  signal mem_reg_0_15_6_11_n_2 : STD_LOGIC;
  signal mem_reg_0_15_6_11_n_3 : STD_LOGIC;
  signal mem_reg_0_15_6_11_n_4 : STD_LOGIC;
  signal mem_reg_0_15_6_11_n_5 : STD_LOGIC;
  signal my_empty0 : STD_LOGIC;
  signal \my_empty[1]_i_1__5_n_0\ : STD_LOGIC;
  signal \my_empty[7]_i_1__5_n_0\ : STD_LOGIC;
  signal \my_empty[7]_i_3__5_n_0\ : STD_LOGIC;
  signal \my_empty[7]_i_4__5_n_0\ : STD_LOGIC;
  signal \^my_empty_reg[1]_1\ : STD_LOGIC;
  signal \my_empty_reg_n_0_[7]\ : STD_LOGIC;
  signal my_full0 : STD_LOGIC;
  signal \my_full[4]_i_1__5_n_0\ : STD_LOGIC;
  signal \my_full[4]_i_3__5_n_0\ : STD_LOGIC;
  signal \my_full[4]_i_4__5_n_0\ : STD_LOGIC;
  signal \my_full_reg_n_0_[4]\ : STD_LOGIC;
  signal nxt_rd_ptr : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal nxt_wr_ptr : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \rd_ptr_reg_n_0_[0]\ : STD_LOGIC;
  signal \rd_ptr_reg_n_0_[1]\ : STD_LOGIC;
  signal \rd_ptr_reg_n_0_[2]\ : STD_LOGIC;
  signal \rd_ptr_reg_n_0_[3]\ : STD_LOGIC;
  signal rd_ptr_timing : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \rd_ptr_timing[3]_i_1__5_n_0\ : STD_LOGIC;
  signal wr_en : STD_LOGIC;
  attribute MAX_FANOUT : string;
  attribute MAX_FANOUT of wr_en : signal is "50";
  attribute RTL_MAX_FANOUT : string;
  attribute RTL_MAX_FANOUT of wr_en : signal is "found";
  signal wr_ptr : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal wr_ptr0 : STD_LOGIC;
  signal wr_ptr_timing : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal NLW_mem_reg_0_15_0_5_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_15_12_17_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_15_18_23_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_15_24_29_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_15_30_35_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_15_36_41_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_15_42_47_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_15_48_53_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_15_54_59_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_15_60_65_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_15_66_71_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_15_6_11_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_15_72_77_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_15_78_79_DOB_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_15_78_79_DOC_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_15_78_79_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \entry_cnt[0]_i_1__4\ : label is "soft_lutpair1023";
  attribute SOFT_HLUTNM of \entry_cnt[1]_i_1__4\ : label is "soft_lutpair1022";
  attribute SOFT_HLUTNM of \entry_cnt[3]_i_1__4\ : label is "soft_lutpair1023";
  attribute SOFT_HLUTNM of \entry_cnt[4]_i_3__4\ : label is "soft_lutpair1022";
  attribute METHODOLOGY_DRC_VIOS : string;
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_15_0_5 : label is "";
  attribute RTL_RAM_BITS : integer;
  attribute RTL_RAM_BITS of mem_reg_0_15_0_5 : label is 720;
  attribute RTL_RAM_NAME : string;
  attribute RTL_RAM_NAME of mem_reg_0_15_0_5 : label is "of_pre_fifo_gen.u_ddr_of_pre_fifo/mem";
  attribute ram_addr_begin : integer;
  attribute ram_addr_begin of mem_reg_0_15_0_5 : label is 0;
  attribute ram_addr_end : integer;
  attribute ram_addr_end of mem_reg_0_15_0_5 : label is 8;
  attribute ram_offset : integer;
  attribute ram_offset of mem_reg_0_15_0_5 : label is 0;
  attribute ram_slice_begin : integer;
  attribute ram_slice_begin of mem_reg_0_15_0_5 : label is 0;
  attribute ram_slice_end : integer;
  attribute ram_slice_end of mem_reg_0_15_0_5 : label is 5;
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_15_12_17 : label is "";
  attribute RTL_RAM_BITS of mem_reg_0_15_12_17 : label is 720;
  attribute RTL_RAM_NAME of mem_reg_0_15_12_17 : label is "of_pre_fifo_gen.u_ddr_of_pre_fifo/mem";
  attribute ram_addr_begin of mem_reg_0_15_12_17 : label is 0;
  attribute ram_addr_end of mem_reg_0_15_12_17 : label is 8;
  attribute ram_offset of mem_reg_0_15_12_17 : label is 0;
  attribute ram_slice_begin of mem_reg_0_15_12_17 : label is 12;
  attribute ram_slice_end of mem_reg_0_15_12_17 : label is 17;
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_15_18_23 : label is "";
  attribute RTL_RAM_BITS of mem_reg_0_15_18_23 : label is 720;
  attribute RTL_RAM_NAME of mem_reg_0_15_18_23 : label is "of_pre_fifo_gen.u_ddr_of_pre_fifo/mem";
  attribute ram_addr_begin of mem_reg_0_15_18_23 : label is 0;
  attribute ram_addr_end of mem_reg_0_15_18_23 : label is 8;
  attribute ram_offset of mem_reg_0_15_18_23 : label is 0;
  attribute ram_slice_begin of mem_reg_0_15_18_23 : label is 18;
  attribute ram_slice_end of mem_reg_0_15_18_23 : label is 23;
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_15_24_29 : label is "";
  attribute RTL_RAM_BITS of mem_reg_0_15_24_29 : label is 720;
  attribute RTL_RAM_NAME of mem_reg_0_15_24_29 : label is "of_pre_fifo_gen.u_ddr_of_pre_fifo/mem";
  attribute ram_addr_begin of mem_reg_0_15_24_29 : label is 0;
  attribute ram_addr_end of mem_reg_0_15_24_29 : label is 8;
  attribute ram_offset of mem_reg_0_15_24_29 : label is 0;
  attribute ram_slice_begin of mem_reg_0_15_24_29 : label is 24;
  attribute ram_slice_end of mem_reg_0_15_24_29 : label is 29;
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_15_30_35 : label is "";
  attribute RTL_RAM_BITS of mem_reg_0_15_30_35 : label is 720;
  attribute RTL_RAM_NAME of mem_reg_0_15_30_35 : label is "of_pre_fifo_gen.u_ddr_of_pre_fifo/mem";
  attribute ram_addr_begin of mem_reg_0_15_30_35 : label is 0;
  attribute ram_addr_end of mem_reg_0_15_30_35 : label is 8;
  attribute ram_offset of mem_reg_0_15_30_35 : label is 0;
  attribute ram_slice_begin of mem_reg_0_15_30_35 : label is 30;
  attribute ram_slice_end of mem_reg_0_15_30_35 : label is 35;
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_15_36_41 : label is "";
  attribute RTL_RAM_BITS of mem_reg_0_15_36_41 : label is 720;
  attribute RTL_RAM_NAME of mem_reg_0_15_36_41 : label is "of_pre_fifo_gen.u_ddr_of_pre_fifo/mem";
  attribute ram_addr_begin of mem_reg_0_15_36_41 : label is 0;
  attribute ram_addr_end of mem_reg_0_15_36_41 : label is 8;
  attribute ram_offset of mem_reg_0_15_36_41 : label is 0;
  attribute ram_slice_begin of mem_reg_0_15_36_41 : label is 36;
  attribute ram_slice_end of mem_reg_0_15_36_41 : label is 41;
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_15_42_47 : label is "";
  attribute RTL_RAM_BITS of mem_reg_0_15_42_47 : label is 720;
  attribute RTL_RAM_NAME of mem_reg_0_15_42_47 : label is "of_pre_fifo_gen.u_ddr_of_pre_fifo/mem";
  attribute ram_addr_begin of mem_reg_0_15_42_47 : label is 0;
  attribute ram_addr_end of mem_reg_0_15_42_47 : label is 8;
  attribute ram_offset of mem_reg_0_15_42_47 : label is 0;
  attribute ram_slice_begin of mem_reg_0_15_42_47 : label is 42;
  attribute ram_slice_end of mem_reg_0_15_42_47 : label is 47;
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_15_48_53 : label is "";
  attribute RTL_RAM_BITS of mem_reg_0_15_48_53 : label is 720;
  attribute RTL_RAM_NAME of mem_reg_0_15_48_53 : label is "of_pre_fifo_gen.u_ddr_of_pre_fifo/mem";
  attribute ram_addr_begin of mem_reg_0_15_48_53 : label is 0;
  attribute ram_addr_end of mem_reg_0_15_48_53 : label is 8;
  attribute ram_offset of mem_reg_0_15_48_53 : label is 0;
  attribute ram_slice_begin of mem_reg_0_15_48_53 : label is 48;
  attribute ram_slice_end of mem_reg_0_15_48_53 : label is 53;
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_15_54_59 : label is "";
  attribute RTL_RAM_BITS of mem_reg_0_15_54_59 : label is 720;
  attribute RTL_RAM_NAME of mem_reg_0_15_54_59 : label is "of_pre_fifo_gen.u_ddr_of_pre_fifo/mem";
  attribute ram_addr_begin of mem_reg_0_15_54_59 : label is 0;
  attribute ram_addr_end of mem_reg_0_15_54_59 : label is 8;
  attribute ram_offset of mem_reg_0_15_54_59 : label is 0;
  attribute ram_slice_begin of mem_reg_0_15_54_59 : label is 54;
  attribute ram_slice_end of mem_reg_0_15_54_59 : label is 59;
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_15_60_65 : label is "";
  attribute RTL_RAM_BITS of mem_reg_0_15_60_65 : label is 720;
  attribute RTL_RAM_NAME of mem_reg_0_15_60_65 : label is "of_pre_fifo_gen.u_ddr_of_pre_fifo/mem";
  attribute ram_addr_begin of mem_reg_0_15_60_65 : label is 0;
  attribute ram_addr_end of mem_reg_0_15_60_65 : label is 8;
  attribute ram_offset of mem_reg_0_15_60_65 : label is 0;
  attribute ram_slice_begin of mem_reg_0_15_60_65 : label is 60;
  attribute ram_slice_end of mem_reg_0_15_60_65 : label is 65;
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_15_66_71 : label is "";
  attribute RTL_RAM_BITS of mem_reg_0_15_66_71 : label is 720;
  attribute RTL_RAM_NAME of mem_reg_0_15_66_71 : label is "of_pre_fifo_gen.u_ddr_of_pre_fifo/mem";
  attribute ram_addr_begin of mem_reg_0_15_66_71 : label is 0;
  attribute ram_addr_end of mem_reg_0_15_66_71 : label is 8;
  attribute ram_offset of mem_reg_0_15_66_71 : label is 0;
  attribute ram_slice_begin of mem_reg_0_15_66_71 : label is 66;
  attribute ram_slice_end of mem_reg_0_15_66_71 : label is 71;
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_15_6_11 : label is "";
  attribute RTL_RAM_BITS of mem_reg_0_15_6_11 : label is 720;
  attribute RTL_RAM_NAME of mem_reg_0_15_6_11 : label is "of_pre_fifo_gen.u_ddr_of_pre_fifo/mem";
  attribute ram_addr_begin of mem_reg_0_15_6_11 : label is 0;
  attribute ram_addr_end of mem_reg_0_15_6_11 : label is 8;
  attribute ram_offset of mem_reg_0_15_6_11 : label is 0;
  attribute ram_slice_begin of mem_reg_0_15_6_11 : label is 6;
  attribute ram_slice_end of mem_reg_0_15_6_11 : label is 11;
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_15_72_77 : label is "";
  attribute RTL_RAM_BITS of mem_reg_0_15_72_77 : label is 720;
  attribute RTL_RAM_NAME of mem_reg_0_15_72_77 : label is "of_pre_fifo_gen.u_ddr_of_pre_fifo/mem";
  attribute ram_addr_begin of mem_reg_0_15_72_77 : label is 0;
  attribute ram_addr_end of mem_reg_0_15_72_77 : label is 8;
  attribute ram_offset of mem_reg_0_15_72_77 : label is 0;
  attribute ram_slice_begin of mem_reg_0_15_72_77 : label is 72;
  attribute ram_slice_end of mem_reg_0_15_72_77 : label is 77;
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_15_78_79 : label is "";
  attribute RTL_RAM_BITS of mem_reg_0_15_78_79 : label is 720;
  attribute RTL_RAM_NAME of mem_reg_0_15_78_79 : label is "of_pre_fifo_gen.u_ddr_of_pre_fifo/mem";
  attribute ram_addr_begin of mem_reg_0_15_78_79 : label is 0;
  attribute ram_addr_end of mem_reg_0_15_78_79 : label is 8;
  attribute ram_offset of mem_reg_0_15_78_79 : label is 0;
  attribute ram_slice_begin of mem_reg_0_15_78_79 : label is 78;
  attribute ram_slice_end of mem_reg_0_15_78_79 : label is 79;
  attribute SOFT_HLUTNM of \my_empty[7]_i_3__5\ : label is "soft_lutpair1025";
  attribute SOFT_HLUTNM of \my_empty[7]_i_4__5\ : label is "soft_lutpair1025";
  attribute syn_maxfan : string;
  attribute syn_maxfan of \my_empty_reg[1]\ : label is "3";
  attribute syn_maxfan of \my_empty_reg[7]\ : label is "3";
  attribute SOFT_HLUTNM of \my_full[4]_i_3__5\ : label is "soft_lutpair1024";
  attribute SOFT_HLUTNM of \my_full[4]_i_4__5\ : label is "soft_lutpair1024";
  attribute syn_maxfan of \my_full_reg[4]\ : label is "3";
  attribute SOFT_HLUTNM of \out_fifo_i_10__4\ : label is "soft_lutpair1026";
  attribute SOFT_HLUTNM of \out_fifo_i_11__4\ : label is "soft_lutpair1033";
  attribute SOFT_HLUTNM of \out_fifo_i_12__4\ : label is "soft_lutpair1028";
  attribute SOFT_HLUTNM of \out_fifo_i_13__4\ : label is "soft_lutpair1031";
  attribute SOFT_HLUTNM of \out_fifo_i_14__4\ : label is "soft_lutpair1029";
  attribute SOFT_HLUTNM of \out_fifo_i_15__4\ : label is "soft_lutpair1030";
  attribute SOFT_HLUTNM of \out_fifo_i_16__4\ : label is "soft_lutpair1027";
  attribute SOFT_HLUTNM of \out_fifo_i_17__4\ : label is "soft_lutpair1035";
  attribute SOFT_HLUTNM of \out_fifo_i_2__3\ : label is "soft_lutpair1031";
  attribute SOFT_HLUTNM of \out_fifo_i_3__3\ : label is "soft_lutpair1027";
  attribute SOFT_HLUTNM of \out_fifo_i_4__3\ : label is "soft_lutpair1033";
  attribute SOFT_HLUTNM of \out_fifo_i_5__3\ : label is "soft_lutpair1029";
  attribute SOFT_HLUTNM of \out_fifo_i_6__3\ : label is "soft_lutpair1030";
  attribute SOFT_HLUTNM of \out_fifo_i_7__3\ : label is "soft_lutpair1026";
  attribute SOFT_HLUTNM of \out_fifo_i_8__3\ : label is "soft_lutpair1035";
  attribute SOFT_HLUTNM of \out_fifo_i_9__3\ : label is "soft_lutpair1028";
  attribute syn_maxfan of \rd_ptr_reg[0]\ : label is "10";
  attribute syn_maxfan of \rd_ptr_reg[1]\ : label is "10";
  attribute syn_maxfan of \rd_ptr_reg[2]\ : label is "10";
  attribute syn_maxfan of \rd_ptr_reg[3]\ : label is "10";
  attribute SOFT_HLUTNM of \rd_ptr_timing[0]_i_1__11\ : label is "soft_lutpair1037";
  attribute SOFT_HLUTNM of \rd_ptr_timing[1]_i_1__11\ : label is "soft_lutpair1037";
  attribute SOFT_HLUTNM of \rd_ptr_timing[2]_i_1__5\ : label is "soft_lutpair1034";
  attribute SOFT_HLUTNM of \rd_ptr_timing[3]_i_2__5\ : label is "soft_lutpair1034";
  attribute KEEP : string;
  attribute KEEP of \rd_ptr_timing_reg[0]\ : label is "yes";
  attribute KEEP of \rd_ptr_timing_reg[1]\ : label is "yes";
  attribute KEEP of \rd_ptr_timing_reg[2]\ : label is "yes";
  attribute KEEP of \rd_ptr_timing_reg[3]\ : label is "yes";
  attribute SOFT_HLUTNM of \wr_ptr[0]_i_1__11\ : label is "soft_lutpair1036";
  attribute SOFT_HLUTNM of \wr_ptr[1]_i_1__11\ : label is "soft_lutpair1036";
  attribute SOFT_HLUTNM of \wr_ptr[2]_i_1__5\ : label is "soft_lutpair1032";
  attribute SOFT_HLUTNM of \wr_ptr[3]_i_2__4\ : label is "soft_lutpair1032";
  attribute syn_maxfan of \wr_ptr_reg[0]\ : label is "10";
  attribute syn_maxfan of \wr_ptr_reg[1]\ : label is "10";
  attribute syn_maxfan of \wr_ptr_reg[2]\ : label is "10";
  attribute syn_maxfan of \wr_ptr_reg[3]\ : label is "10";
  attribute KEEP of \wr_ptr_timing_reg[0]\ : label is "yes";
  attribute KEEP of \wr_ptr_timing_reg[1]\ : label is "yes";
  attribute KEEP of \wr_ptr_timing_reg[2]\ : label is "yes";
  attribute KEEP of \wr_ptr_timing_reg[3]\ : label is "yes";
begin
  Q(2 downto 0) <= \^q\(2 downto 0);
  \my_empty_reg[1]_1\ <= \^my_empty_reg[1]_1\;
\entry_cnt[0]_i_1__4\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \entry_cnt_reg_n_0_[0]\,
      O => \entry_cnt[0]_i_1__4_n_0\
    );
\entry_cnt[1]_i_1__4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AA6A5595"
    )
        port map (
      I0 => \entry_cnt_reg_n_0_[0]\,
      I1 => \my_empty_reg[7]_0\,
      I2 => phy_data_wr_en,
      I3 => \my_full_reg_n_0_[4]\,
      I4 => \entry_cnt_reg_n_0_[1]\,
      O => \entry_cnt[1]_i_1__4_n_0\
    );
\entry_cnt[2]_i_1__4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FF7F0080AAEA5515"
    )
        port map (
      I0 => \entry_cnt_reg_n_0_[0]\,
      I1 => \my_empty_reg[7]_0\,
      I2 => phy_data_wr_en,
      I3 => \my_full_reg_n_0_[4]\,
      I4 => \^q\(0),
      I5 => \entry_cnt_reg_n_0_[1]\,
      O => \entry_cnt[2]_i_1__4_n_0\
    );
\entry_cnt[3]_i_1__4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"7F80FE01"
    )
        port map (
      I0 => \entry_cnt10_out__0\,
      I1 => \entry_cnt_reg_n_0_[0]\,
      I2 => \entry_cnt_reg_n_0_[1]\,
      I3 => \^q\(1),
      I4 => \^q\(0),
      O => \entry_cnt[3]_i_1__4_n_0\
    );
\entry_cnt[4]_i_1__4\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"5003"
    )
        port map (
      I0 => \my_full_reg_n_0_[4]\,
      I1 => \my_empty_reg_n_0_[7]\,
      I2 => \my_empty_reg[7]_0\,
      I3 => phy_data_wr_en,
      O => \entry_cnt[4]_i_1__4_n_0\
    );
\entry_cnt[4]_i_2__4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"7FFF8000FFFE0001"
    )
        port map (
      I0 => \entry_cnt_reg_n_0_[1]\,
      I1 => \entry_cnt_reg_n_0_[0]\,
      I2 => \entry_cnt10_out__0\,
      I3 => \^q\(0),
      I4 => \^q\(2),
      I5 => \^q\(1),
      O => \entry_cnt[4]_i_2__4_n_0\
    );
\entry_cnt[4]_i_3__4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"08"
    )
        port map (
      I0 => \my_empty_reg[7]_0\,
      I1 => phy_data_wr_en,
      I2 => \my_full_reg_n_0_[4]\,
      O => \entry_cnt10_out__0\
    );
\entry_cnt_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]_0\,
      CE => \entry_cnt[4]_i_1__4_n_0\,
      D => \entry_cnt[0]_i_1__4_n_0\,
      Q => \entry_cnt_reg_n_0_[0]\,
      R => ofifo_rst
    );
\entry_cnt_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]_0\,
      CE => \entry_cnt[4]_i_1__4_n_0\,
      D => \entry_cnt[1]_i_1__4_n_0\,
      Q => \entry_cnt_reg_n_0_[1]\,
      R => ofifo_rst
    );
\entry_cnt_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]_0\,
      CE => \entry_cnt[4]_i_1__4_n_0\,
      D => \entry_cnt[2]_i_1__4_n_0\,
      Q => \^q\(0),
      R => ofifo_rst
    );
\entry_cnt_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]_0\,
      CE => \entry_cnt[4]_i_1__4_n_0\,
      D => \entry_cnt[3]_i_1__4_n_0\,
      Q => \^q\(1),
      R => ofifo_rst
    );
\entry_cnt_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]_0\,
      CE => \entry_cnt[4]_i_1__4_n_0\,
      D => \entry_cnt[4]_i_2__4_n_0\,
      Q => \^q\(2),
      R => ofifo_rst
    );
mem_reg_0_15_0_5: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4) => '0',
      ADDRA(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRA(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRA(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRA(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRB(4) => '0',
      ADDRB(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRB(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRB(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRB(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRC(4) => '0',
      ADDRC(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRC(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRC(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRC(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRD(4) => '0',
      ADDRD(3 downto 0) => wr_ptr(3 downto 0),
      DIA(1 downto 0) => B"00",
      DIB(1 downto 0) => B"00",
      DIC(1 downto 0) => B"00",
      DID(1 downto 0) => B"00",
      DOA(1) => mem_reg_0_15_0_5_n_0,
      DOA(0) => mem_reg_0_15_0_5_n_1,
      DOB(1) => mem_reg_0_15_0_5_n_2,
      DOB(0) => mem_reg_0_15_0_5_n_3,
      DOC(1) => mem_reg_0_15_0_5_n_4,
      DOC(0) => mem_reg_0_15_0_5_n_5,
      DOD(1 downto 0) => NLW_mem_reg_0_15_0_5_DOD_UNCONNECTED(1 downto 0),
      WCLK => \entry_cnt_reg[4]_0\,
      WE => wr_en
    );
\mem_reg_0_15_0_5_i_1__4\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2700"
    )
        port map (
      I0 => \my_empty_reg[7]_0\,
      I1 => \my_full_reg_n_0_[4]\,
      I2 => \^my_empty_reg[1]_1\,
      I3 => phy_data_wr_en,
      O => wr_en
    );
mem_reg_0_15_12_17: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4) => '0',
      ADDRA(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRA(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRA(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRA(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRB(4) => '0',
      ADDRB(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRB(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRB(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRB(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRC(4) => '0',
      ADDRC(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRC(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRC(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRC(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRD(4) => '0',
      ADDRD(3 downto 0) => wr_ptr(3 downto 0),
      DIA(1 downto 0) => \out_fifo_i_75__1\(5 downto 4),
      DIB(1 downto 0) => \out_fifo_i_75__1\(7 downto 6),
      DIC(1 downto 0) => \out_fifo_i_75__1\(9 downto 8),
      DID(1 downto 0) => B"00",
      DOA(1) => mem_reg_0_15_12_17_n_0,
      DOA(0) => mem_reg_0_15_12_17_n_1,
      DOB(1) => mem_reg_0_15_12_17_n_2,
      DOB(0) => mem_reg_0_15_12_17_n_3,
      DOC(1 downto 0) => \rd_ptr_reg[3]_0\(1 downto 0),
      DOD(1 downto 0) => NLW_mem_reg_0_15_12_17_DOD_UNCONNECTED(1 downto 0),
      WCLK => \entry_cnt_reg[4]_0\,
      WE => wr_en
    );
mem_reg_0_15_18_23: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4) => '0',
      ADDRA(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRA(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRA(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRA(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRB(4) => '0',
      ADDRB(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRB(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRB(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRB(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRC(4) => '0',
      ADDRC(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRC(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRC(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRC(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRD(4) => '0',
      ADDRD(3 downto 0) => wr_ptr(3 downto 0),
      DIA(1 downto 0) => \out_fifo_i_75__1\(11 downto 10),
      DIB(1 downto 0) => \out_fifo_i_75__1\(13 downto 12),
      DIC(1 downto 0) => \out_fifo_i_75__1\(15 downto 14),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => \rd_ptr_reg[3]_0\(3 downto 2),
      DOB(1 downto 0) => \rd_ptr_reg[3]_0\(5 downto 4),
      DOC(1 downto 0) => \rd_ptr_reg[3]_0\(7 downto 6),
      DOD(1 downto 0) => NLW_mem_reg_0_15_18_23_DOD_UNCONNECTED(1 downto 0),
      WCLK => \entry_cnt_reg[4]_0\,
      WE => wr_en
    );
mem_reg_0_15_24_29: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4) => '0',
      ADDRA(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRA(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRA(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRA(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRB(4) => '0',
      ADDRB(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRB(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRB(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRB(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRC(4) => '0',
      ADDRC(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRC(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRC(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRC(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRD(4) => '0',
      ADDRD(3 downto 0) => wr_ptr(3 downto 0),
      DIA(1 downto 0) => \out_fifo_i_75__1\(17 downto 16),
      DIB(1 downto 0) => \out_fifo_i_75__1\(19 downto 18),
      DIC(1 downto 0) => \out_fifo_i_75__1\(21 downto 20),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => \rd_ptr_reg[3]_0\(9 downto 8),
      DOB(1 downto 0) => \rd_ptr_reg[3]_0\(11 downto 10),
      DOC(1 downto 0) => \rd_ptr_reg[3]_0\(13 downto 12),
      DOD(1 downto 0) => NLW_mem_reg_0_15_24_29_DOD_UNCONNECTED(1 downto 0),
      WCLK => \entry_cnt_reg[4]_0\,
      WE => wr_en
    );
mem_reg_0_15_30_35: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4) => '0',
      ADDRA(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRA(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRA(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRA(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRB(4) => '0',
      ADDRB(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRB(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRB(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRB(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRC(4) => '0',
      ADDRC(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRC(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRC(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRC(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRD(4) => '0',
      ADDRD(3 downto 0) => wr_ptr(3 downto 0),
      DIA(1 downto 0) => \out_fifo_i_75__1\(23 downto 22),
      DIB(1 downto 0) => \out_fifo_i_75__1\(25 downto 24),
      DIC(1 downto 0) => \out_fifo_i_75__1\(27 downto 26),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => \rd_ptr_reg[3]_0\(15 downto 14),
      DOB(1 downto 0) => \rd_ptr_reg[3]_0\(17 downto 16),
      DOC(1 downto 0) => \rd_ptr_reg[3]_0\(19 downto 18),
      DOD(1 downto 0) => NLW_mem_reg_0_15_30_35_DOD_UNCONNECTED(1 downto 0),
      WCLK => \entry_cnt_reg[4]_0\,
      WE => wr_en
    );
mem_reg_0_15_36_41: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4) => '0',
      ADDRA(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRA(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRA(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRA(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRB(4) => '0',
      ADDRB(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRB(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRB(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRB(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRC(4) => '0',
      ADDRC(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRC(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRC(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRC(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRD(4) => '0',
      ADDRD(3 downto 0) => wr_ptr(3 downto 0),
      DIA(1 downto 0) => \out_fifo_i_75__1\(29 downto 28),
      DIB(1 downto 0) => \out_fifo_i_75__1\(31 downto 30),
      DIC(1 downto 0) => \out_fifo_i_75__1\(33 downto 32),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => \rd_ptr_reg[3]_0\(21 downto 20),
      DOB(1 downto 0) => \rd_ptr_reg[3]_0\(23 downto 22),
      DOC(1 downto 0) => \rd_ptr_reg[3]_0\(25 downto 24),
      DOD(1 downto 0) => NLW_mem_reg_0_15_36_41_DOD_UNCONNECTED(1 downto 0),
      WCLK => \entry_cnt_reg[4]_0\,
      WE => wr_en
    );
mem_reg_0_15_42_47: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4) => '0',
      ADDRA(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRA(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRA(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRA(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRB(4) => '0',
      ADDRB(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRB(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRB(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRB(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRC(4) => '0',
      ADDRC(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRC(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRC(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRC(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRD(4) => '0',
      ADDRD(3 downto 0) => wr_ptr(3 downto 0),
      DIA(1 downto 0) => \out_fifo_i_75__1\(35 downto 34),
      DIB(1 downto 0) => \out_fifo_i_75__1\(37 downto 36),
      DIC(1 downto 0) => \out_fifo_i_75__1\(39 downto 38),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => \rd_ptr_reg[3]_0\(27 downto 26),
      DOB(1 downto 0) => \rd_ptr_reg[3]_0\(29 downto 28),
      DOC(1 downto 0) => \rd_ptr_reg[3]_0\(31 downto 30),
      DOD(1 downto 0) => NLW_mem_reg_0_15_42_47_DOD_UNCONNECTED(1 downto 0),
      WCLK => \entry_cnt_reg[4]_0\,
      WE => wr_en
    );
mem_reg_0_15_48_53: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4) => '0',
      ADDRA(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRA(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRA(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRA(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRB(4) => '0',
      ADDRB(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRB(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRB(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRB(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRC(4) => '0',
      ADDRC(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRC(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRC(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRC(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRD(4) => '0',
      ADDRD(3 downto 0) => wr_ptr(3 downto 0),
      DIA(1 downto 0) => \out_fifo_i_75__1\(41 downto 40),
      DIB(1 downto 0) => \out_fifo_i_75__1\(43 downto 42),
      DIC(1 downto 0) => \out_fifo_i_75__1\(45 downto 44),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => \rd_ptr_reg[3]_0\(33 downto 32),
      DOB(1 downto 0) => \rd_ptr_reg[3]_0\(35 downto 34),
      DOC(1 downto 0) => \rd_ptr_reg[3]_0\(37 downto 36),
      DOD(1 downto 0) => NLW_mem_reg_0_15_48_53_DOD_UNCONNECTED(1 downto 0),
      WCLK => \entry_cnt_reg[4]_0\,
      WE => wr_en
    );
mem_reg_0_15_54_59: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4) => '0',
      ADDRA(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRA(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRA(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRA(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRB(4) => '0',
      ADDRB(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRB(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRB(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRB(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRC(4) => '0',
      ADDRC(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRC(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRC(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRC(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRD(4) => '0',
      ADDRD(3 downto 0) => wr_ptr(3 downto 0),
      DIA(1 downto 0) => \out_fifo_i_75__1\(47 downto 46),
      DIB(1 downto 0) => \out_fifo_i_75__1\(49 downto 48),
      DIC(1 downto 0) => \out_fifo_i_75__1\(51 downto 50),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => \rd_ptr_reg[3]_0\(39 downto 38),
      DOB(1 downto 0) => \rd_ptr_reg[3]_0\(41 downto 40),
      DOC(1 downto 0) => \rd_ptr_reg[3]_0\(43 downto 42),
      DOD(1 downto 0) => NLW_mem_reg_0_15_54_59_DOD_UNCONNECTED(1 downto 0),
      WCLK => \entry_cnt_reg[4]_0\,
      WE => wr_en
    );
mem_reg_0_15_60_65: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4) => '0',
      ADDRA(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRA(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRA(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRA(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRB(4) => '0',
      ADDRB(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRB(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRB(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRB(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRC(4) => '0',
      ADDRC(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRC(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRC(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRC(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRD(4) => '0',
      ADDRD(3 downto 0) => wr_ptr(3 downto 0),
      DIA(1 downto 0) => \out_fifo_i_75__1\(53 downto 52),
      DIB(1 downto 0) => \out_fifo_i_75__1\(55 downto 54),
      DIC(1 downto 0) => \out_fifo_i_75__1\(57 downto 56),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => \rd_ptr_reg[3]_0\(45 downto 44),
      DOB(1 downto 0) => \rd_ptr_reg[3]_0\(47 downto 46),
      DOC(1 downto 0) => \rd_ptr_reg[3]_0\(49 downto 48),
      DOD(1 downto 0) => NLW_mem_reg_0_15_60_65_DOD_UNCONNECTED(1 downto 0),
      WCLK => \entry_cnt_reg[4]_0\,
      WE => wr_en
    );
mem_reg_0_15_66_71: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4) => '0',
      ADDRA(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRA(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRA(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRA(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRB(4) => '0',
      ADDRB(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRB(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRB(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRB(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRC(4) => '0',
      ADDRC(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRC(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRC(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRC(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRD(4) => '0',
      ADDRD(3 downto 0) => wr_ptr(3 downto 0),
      DIA(1 downto 0) => \out_fifo_i_75__1\(59 downto 58),
      DIB(1 downto 0) => \out_fifo_i_75__1\(61 downto 60),
      DIC(1 downto 0) => \out_fifo_i_75__1\(63 downto 62),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => \rd_ptr_reg[3]_0\(51 downto 50),
      DOB(1 downto 0) => \rd_ptr_reg[3]_0\(53 downto 52),
      DOC(1 downto 0) => \rd_ptr_reg[3]_0\(55 downto 54),
      DOD(1 downto 0) => NLW_mem_reg_0_15_66_71_DOD_UNCONNECTED(1 downto 0),
      WCLK => \entry_cnt_reg[4]_0\,
      WE => wr_en
    );
mem_reg_0_15_6_11: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4) => '0',
      ADDRA(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRA(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRA(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRA(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRB(4) => '0',
      ADDRB(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRB(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRB(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRB(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRC(4) => '0',
      ADDRC(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRC(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRC(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRC(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRD(4) => '0',
      ADDRD(3 downto 0) => wr_ptr(3 downto 0),
      DIA(1 downto 0) => B"00",
      DIB(1 downto 0) => \out_fifo_i_75__1\(1 downto 0),
      DIC(1 downto 0) => \out_fifo_i_75__1\(3 downto 2),
      DID(1 downto 0) => B"00",
      DOA(1) => mem_reg_0_15_6_11_n_0,
      DOA(0) => mem_reg_0_15_6_11_n_1,
      DOB(1) => mem_reg_0_15_6_11_n_2,
      DOB(0) => mem_reg_0_15_6_11_n_3,
      DOC(1) => mem_reg_0_15_6_11_n_4,
      DOC(0) => mem_reg_0_15_6_11_n_5,
      DOD(1 downto 0) => NLW_mem_reg_0_15_6_11_DOD_UNCONNECTED(1 downto 0),
      WCLK => \entry_cnt_reg[4]_0\,
      WE => wr_en
    );
mem_reg_0_15_72_77: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4) => '0',
      ADDRA(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRA(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRA(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRA(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRB(4) => '0',
      ADDRB(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRB(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRB(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRB(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRC(4) => '0',
      ADDRC(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRC(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRC(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRC(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRD(4) => '0',
      ADDRD(3 downto 0) => wr_ptr(3 downto 0),
      DIA(1 downto 0) => \out_fifo_i_75__1\(65 downto 64),
      DIB(1 downto 0) => \out_fifo_i_75__1\(67 downto 66),
      DIC(1 downto 0) => \out_fifo_i_75__1\(69 downto 68),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => \rd_ptr_reg[3]_0\(57 downto 56),
      DOB(1 downto 0) => \rd_ptr_reg[3]_0\(59 downto 58),
      DOC(1 downto 0) => \rd_ptr_reg[3]_0\(61 downto 60),
      DOD(1 downto 0) => NLW_mem_reg_0_15_72_77_DOD_UNCONNECTED(1 downto 0),
      WCLK => \entry_cnt_reg[4]_0\,
      WE => wr_en
    );
mem_reg_0_15_78_79: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4) => '0',
      ADDRA(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRA(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRA(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRA(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRB(4) => '0',
      ADDRB(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRB(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRB(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRB(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRC(4) => '0',
      ADDRC(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRC(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRC(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRC(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRD(4) => '0',
      ADDRD(3 downto 0) => wr_ptr(3 downto 0),
      DIA(1 downto 0) => \out_fifo_i_75__1\(71 downto 70),
      DIB(1 downto 0) => B"00",
      DIC(1 downto 0) => B"00",
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => \rd_ptr_reg[3]_0\(63 downto 62),
      DOB(1 downto 0) => NLW_mem_reg_0_15_78_79_DOB_UNCONNECTED(1 downto 0),
      DOC(1 downto 0) => NLW_mem_reg_0_15_78_79_DOC_UNCONNECTED(1 downto 0),
      DOD(1 downto 0) => NLW_mem_reg_0_15_78_79_DOD_UNCONNECTED(1 downto 0),
      WCLK => \entry_cnt_reg[4]_0\,
      WE => wr_en
    );
\my_empty[1]_i_1__5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFF701F700"
    )
        port map (
      I0 => \my_empty_reg[7]_0\,
      I1 => phy_data_wr_en,
      I2 => \my_full_reg_n_0_[4]\,
      I3 => \^my_empty_reg[1]_1\,
      I4 => my_empty0,
      I5 => ofifo_rst,
      O => \my_empty[1]_i_1__5_n_0\
    );
\my_empty[7]_i_1__5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFF701F700"
    )
        port map (
      I0 => \my_empty_reg[7]_0\,
      I1 => phy_data_wr_en,
      I2 => \my_full_reg_n_0_[4]\,
      I3 => \my_empty_reg_n_0_[7]\,
      I4 => my_empty0,
      I5 => ofifo_rst,
      O => \my_empty[7]_i_1__5_n_0\
    );
\my_empty[7]_i_2__5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"4A400D08"
    )
        port map (
      I0 => wr_ptr_timing(2),
      I1 => \my_empty[7]_i_3__5_n_0\,
      I2 => wr_ptr_timing(3),
      I3 => \my_empty[7]_i_4__5_n_0\,
      I4 => \rd_ptr_reg_n_0_[2]\,
      O => my_empty0
    );
\my_empty[7]_i_3__5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000040"
    )
        port map (
      I0 => wr_ptr_timing(1),
      I1 => \rd_ptr_reg_n_0_[0]\,
      I2 => \rd_ptr_reg_n_0_[1]\,
      I3 => \rd_ptr_reg_n_0_[3]\,
      I4 => wr_ptr_timing(0),
      O => \my_empty[7]_i_3__5_n_0\
    );
\my_empty[7]_i_4__5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"84210842"
    )
        port map (
      I0 => wr_ptr_timing(0),
      I1 => wr_ptr_timing(1),
      I2 => \rd_ptr_reg_n_0_[0]\,
      I3 => \rd_ptr_reg_n_0_[1]\,
      I4 => \rd_ptr_reg_n_0_[3]\,
      O => \my_empty[7]_i_4__5_n_0\
    );
\my_empty_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]_0\,
      CE => '1',
      D => \my_empty[1]_i_1__5_n_0\,
      Q => \^my_empty_reg[1]_1\,
      R => '0'
    );
\my_empty_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]_0\,
      CE => '1',
      D => \my_empty[7]_i_1__5_n_0\,
      Q => \my_empty_reg_n_0_[7]\,
      R => '0'
    );
\my_full[4]_i_1__5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000FFFC0080"
    )
        port map (
      I0 => my_full0,
      I1 => phy_data_wr_en,
      I2 => \my_empty_reg[7]_0\,
      I3 => \my_empty_reg_n_0_[7]\,
      I4 => \my_full_reg_n_0_[4]\,
      I5 => ofifo_rst,
      O => \my_full[4]_i_1__5_n_0\
    );
\my_full[4]_i_2__5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"4A400D08"
    )
        port map (
      I0 => rd_ptr_timing(2),
      I1 => \my_full[4]_i_3__5_n_0\,
      I2 => rd_ptr_timing(3),
      I3 => \my_full[4]_i_4__5_n_0\,
      I4 => wr_ptr(2),
      O => my_full0
    );
\my_full[4]_i_3__5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000040"
    )
        port map (
      I0 => rd_ptr_timing(1),
      I1 => wr_ptr(0),
      I2 => wr_ptr(1),
      I3 => wr_ptr(3),
      I4 => rd_ptr_timing(0),
      O => \my_full[4]_i_3__5_n_0\
    );
\my_full[4]_i_4__5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"84210842"
    )
        port map (
      I0 => rd_ptr_timing(0),
      I1 => rd_ptr_timing(1),
      I2 => wr_ptr(0),
      I3 => wr_ptr(1),
      I4 => wr_ptr(3),
      O => \my_full[4]_i_4__5_n_0\
    );
\my_full_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]_0\,
      CE => '1',
      D => \my_full[4]_i_1__5_n_0\,
      Q => \my_full_reg_n_0_[4]\,
      R => '0'
    );
\out_fifo_i_10__4\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"88F0"
    )
        port map (
      I0 => out_fifo_1,
      I1 => out_fifo_0(7),
      I2 => mem_reg_0_15_12_17_n_2,
      I3 => \^my_empty_reg[1]_1\,
      O => D1(7)
    );
\out_fifo_i_11__4\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"88F0"
    )
        port map (
      I0 => out_fifo_1,
      I1 => out_fifo_0(6),
      I2 => mem_reg_0_15_12_17_n_3,
      I3 => \^my_empty_reg[1]_1\,
      O => D1(6)
    );
\out_fifo_i_12__4\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"88F0"
    )
        port map (
      I0 => out_fifo_1,
      I1 => out_fifo_0(5),
      I2 => mem_reg_0_15_12_17_n_0,
      I3 => \^my_empty_reg[1]_1\,
      O => D1(5)
    );
\out_fifo_i_13__4\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"88F0"
    )
        port map (
      I0 => out_fifo_1,
      I1 => out_fifo_0(4),
      I2 => mem_reg_0_15_12_17_n_1,
      I3 => \^my_empty_reg[1]_1\,
      O => D1(4)
    );
\out_fifo_i_14__4\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"88F0"
    )
        port map (
      I0 => out_fifo_1,
      I1 => out_fifo_0(3),
      I2 => mem_reg_0_15_6_11_n_4,
      I3 => \^my_empty_reg[1]_1\,
      O => D1(3)
    );
\out_fifo_i_15__4\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"88F0"
    )
        port map (
      I0 => out_fifo_1,
      I1 => out_fifo_0(2),
      I2 => mem_reg_0_15_6_11_n_5,
      I3 => \^my_empty_reg[1]_1\,
      O => D1(2)
    );
\out_fifo_i_16__4\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"88F0"
    )
        port map (
      I0 => out_fifo,
      I1 => out_fifo_0(1),
      I2 => mem_reg_0_15_6_11_n_2,
      I3 => \^my_empty_reg[1]_1\,
      O => D1(1)
    );
\out_fifo_i_17__4\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"88F0"
    )
        port map (
      I0 => out_fifo,
      I1 => out_fifo_0(0),
      I2 => mem_reg_0_15_6_11_n_3,
      I3 => \^my_empty_reg[1]_1\,
      O => D1(0)
    );
\out_fifo_i_1__5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"0D"
    )
        port map (
      I0 => \^my_empty_reg[1]_1\,
      I1 => phy_data_wr_en,
      I2 => \my_empty_reg[7]_0\,
      O => \my_empty_reg[1]_0\
    );
\out_fifo_i_2__3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => mem_reg_0_15_6_11_n_0,
      I1 => \^my_empty_reg[1]_1\,
      O => D0(7)
    );
\out_fifo_i_3__3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => mem_reg_0_15_6_11_n_1,
      I1 => \^my_empty_reg[1]_1\,
      O => D0(6)
    );
\out_fifo_i_4__3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => mem_reg_0_15_0_5_n_4,
      I1 => \^my_empty_reg[1]_1\,
      O => D0(5)
    );
\out_fifo_i_5__3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => mem_reg_0_15_0_5_n_5,
      I1 => \^my_empty_reg[1]_1\,
      O => D0(4)
    );
\out_fifo_i_6__3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => mem_reg_0_15_0_5_n_2,
      I1 => \^my_empty_reg[1]_1\,
      O => D0(3)
    );
\out_fifo_i_7__3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => mem_reg_0_15_0_5_n_3,
      I1 => \^my_empty_reg[1]_1\,
      O => D0(2)
    );
\out_fifo_i_8__3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => mem_reg_0_15_0_5_n_0,
      I1 => \^my_empty_reg[1]_1\,
      O => D0(1)
    );
\out_fifo_i_9__3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => mem_reg_0_15_0_5_n_1,
      I1 => \^my_empty_reg[1]_1\,
      O => D0(0)
    );
\rd_ptr_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]_0\,
      CE => \rd_ptr_timing[3]_i_1__5_n_0\,
      D => nxt_rd_ptr(0),
      Q => \rd_ptr_reg_n_0_[0]\,
      R => ofifo_rst
    );
\rd_ptr_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]_0\,
      CE => \rd_ptr_timing[3]_i_1__5_n_0\,
      D => nxt_rd_ptr(1),
      Q => \rd_ptr_reg_n_0_[1]\,
      R => ofifo_rst
    );
\rd_ptr_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]_0\,
      CE => \rd_ptr_timing[3]_i_1__5_n_0\,
      D => nxt_rd_ptr(2),
      Q => \rd_ptr_reg_n_0_[2]\,
      R => ofifo_rst
    );
\rd_ptr_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]_0\,
      CE => \rd_ptr_timing[3]_i_1__5_n_0\,
      D => nxt_rd_ptr(3),
      Q => \rd_ptr_reg_n_0_[3]\,
      R => ofifo_rst
    );
\rd_ptr_timing[0]_i_1__11\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => \rd_ptr_reg_n_0_[3]\,
      I1 => \rd_ptr_reg_n_0_[0]\,
      O => nxt_rd_ptr(0)
    );
\rd_ptr_timing[1]_i_1__11\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B4"
    )
        port map (
      I0 => \rd_ptr_reg_n_0_[3]\,
      I1 => \rd_ptr_reg_n_0_[0]\,
      I2 => \rd_ptr_reg_n_0_[1]\,
      O => nxt_rd_ptr(1)
    );
\rd_ptr_timing[2]_i_1__5\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"AA6A"
    )
        port map (
      I0 => \rd_ptr_reg_n_0_[2]\,
      I1 => \rd_ptr_reg_n_0_[0]\,
      I2 => \rd_ptr_reg_n_0_[1]\,
      I3 => \rd_ptr_reg_n_0_[3]\,
      O => nxt_rd_ptr(2)
    );
\rd_ptr_timing[3]_i_1__5\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \my_empty_reg[7]_0\,
      I1 => \my_empty_reg_n_0_[7]\,
      O => \rd_ptr_timing[3]_i_1__5_n_0\
    );
\rd_ptr_timing[3]_i_2__5\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4000"
    )
        port map (
      I0 => \rd_ptr_reg_n_0_[3]\,
      I1 => \rd_ptr_reg_n_0_[1]\,
      I2 => \rd_ptr_reg_n_0_[0]\,
      I3 => \rd_ptr_reg_n_0_[2]\,
      O => nxt_rd_ptr(3)
    );
\rd_ptr_timing_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]_0\,
      CE => \rd_ptr_timing[3]_i_1__5_n_0\,
      D => nxt_rd_ptr(0),
      Q => rd_ptr_timing(0),
      R => ofifo_rst
    );
\rd_ptr_timing_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]_0\,
      CE => \rd_ptr_timing[3]_i_1__5_n_0\,
      D => nxt_rd_ptr(1),
      Q => rd_ptr_timing(1),
      R => ofifo_rst
    );
\rd_ptr_timing_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]_0\,
      CE => \rd_ptr_timing[3]_i_1__5_n_0\,
      D => nxt_rd_ptr(2),
      Q => rd_ptr_timing(2),
      R => ofifo_rst
    );
\rd_ptr_timing_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]_0\,
      CE => \rd_ptr_timing[3]_i_1__5_n_0\,
      D => nxt_rd_ptr(3),
      Q => rd_ptr_timing(3),
      R => ofifo_rst
    );
\wr_ptr[0]_i_1__11\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => wr_ptr(3),
      I1 => wr_ptr(0),
      O => nxt_wr_ptr(0)
    );
\wr_ptr[1]_i_1__11\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B4"
    )
        port map (
      I0 => wr_ptr(3),
      I1 => wr_ptr(0),
      I2 => wr_ptr(1),
      O => nxt_wr_ptr(1)
    );
\wr_ptr[2]_i_1__5\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"AA6A"
    )
        port map (
      I0 => wr_ptr(2),
      I1 => wr_ptr(0),
      I2 => wr_ptr(1),
      I3 => wr_ptr(3),
      O => nxt_wr_ptr(2)
    );
\wr_ptr[3]_i_1__5\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"082A"
    )
        port map (
      I0 => phy_data_wr_en,
      I1 => \my_empty_reg[7]_0\,
      I2 => \my_full_reg_n_0_[4]\,
      I3 => \my_empty_reg_n_0_[7]\,
      O => wr_ptr0
    );
\wr_ptr[3]_i_2__4\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4000"
    )
        port map (
      I0 => wr_ptr(3),
      I1 => wr_ptr(1),
      I2 => wr_ptr(0),
      I3 => wr_ptr(2),
      O => nxt_wr_ptr(3)
    );
\wr_ptr_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]_0\,
      CE => wr_ptr0,
      D => nxt_wr_ptr(0),
      Q => wr_ptr(0),
      R => ofifo_rst
    );
\wr_ptr_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]_0\,
      CE => wr_ptr0,
      D => nxt_wr_ptr(1),
      Q => wr_ptr(1),
      R => ofifo_rst
    );
\wr_ptr_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]_0\,
      CE => wr_ptr0,
      D => nxt_wr_ptr(2),
      Q => wr_ptr(2),
      R => ofifo_rst
    );
\wr_ptr_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]_0\,
      CE => wr_ptr0,
      D => nxt_wr_ptr(3),
      Q => wr_ptr(3),
      R => ofifo_rst
    );
\wr_ptr_timing_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]_0\,
      CE => wr_ptr0,
      D => nxt_wr_ptr(0),
      Q => wr_ptr_timing(0),
      R => ofifo_rst
    );
\wr_ptr_timing_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]_0\,
      CE => wr_ptr0,
      D => nxt_wr_ptr(1),
      Q => wr_ptr_timing(1),
      R => ofifo_rst
    );
\wr_ptr_timing_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]_0\,
      CE => wr_ptr0,
      D => nxt_wr_ptr(2),
      Q => wr_ptr_timing(2),
      R => ofifo_rst
    );
\wr_ptr_timing_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]_0\,
      CE => wr_ptr0,
      D => nxt_wr_ptr(3),
      Q => wr_ptr_timing(3),
      R => ofifo_rst
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \mig_mig_7series_v4_2_ddr_of_pre_fifo__parameterized1_21\ is
  port (
    \my_empty_reg[1]_0\ : out STD_LOGIC;
    \my_empty_reg[1]_1\ : out STD_LOGIC;
    D8 : out STD_LOGIC_VECTOR ( 7 downto 0 );
    D0 : out STD_LOGIC_VECTOR ( 7 downto 0 );
    \rd_ptr_reg[3]_0\ : out STD_LOGIC_VECTOR ( 63 downto 0 );
    Q : out STD_LOGIC_VECTOR ( 2 downto 0 );
    ofifo_rst : in STD_LOGIC;
    \wr_ptr_timing_reg[3]_0\ : in STD_LOGIC;
    \my_empty_reg[7]_0\ : in STD_LOGIC;
    phy_data_wr_en : in STD_LOGIC;
    out_fifo : in STD_LOGIC;
    out_fifo_0 : in STD_LOGIC_VECTOR ( 7 downto 0 );
    out_fifo_1 : in STD_LOGIC;
    \out_fifo_i_75__0\ : in STD_LOGIC_VECTOR ( 71 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \mig_mig_7series_v4_2_ddr_of_pre_fifo__parameterized1_21\ : entity is "mig_7series_v4_2_ddr_of_pre_fifo";
end \mig_mig_7series_v4_2_ddr_of_pre_fifo__parameterized1_21\;

architecture STRUCTURE of \mig_mig_7series_v4_2_ddr_of_pre_fifo__parameterized1_21\ is
  signal \^q\ : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal \entry_cnt10_out__0\ : STD_LOGIC;
  signal \entry_cnt[0]_i_1__3_n_0\ : STD_LOGIC;
  signal \entry_cnt[1]_i_1__3_n_0\ : STD_LOGIC;
  signal \entry_cnt[2]_i_1__3_n_0\ : STD_LOGIC;
  signal \entry_cnt[3]_i_1__3_n_0\ : STD_LOGIC;
  signal \entry_cnt[4]_i_1__3_n_0\ : STD_LOGIC;
  signal \entry_cnt[4]_i_2__3_n_0\ : STD_LOGIC;
  signal \entry_cnt_reg_n_0_[0]\ : STD_LOGIC;
  signal \entry_cnt_reg_n_0_[1]\ : STD_LOGIC;
  signal mem_reg_0_15_0_5_n_0 : STD_LOGIC;
  signal mem_reg_0_15_0_5_n_1 : STD_LOGIC;
  signal mem_reg_0_15_0_5_n_2 : STD_LOGIC;
  signal mem_reg_0_15_0_5_n_3 : STD_LOGIC;
  signal mem_reg_0_15_0_5_n_4 : STD_LOGIC;
  signal mem_reg_0_15_0_5_n_5 : STD_LOGIC;
  signal mem_reg_0_15_60_65_n_4 : STD_LOGIC;
  signal mem_reg_0_15_60_65_n_5 : STD_LOGIC;
  signal mem_reg_0_15_66_71_n_0 : STD_LOGIC;
  signal mem_reg_0_15_66_71_n_1 : STD_LOGIC;
  signal mem_reg_0_15_66_71_n_2 : STD_LOGIC;
  signal mem_reg_0_15_66_71_n_3 : STD_LOGIC;
  signal mem_reg_0_15_66_71_n_4 : STD_LOGIC;
  signal mem_reg_0_15_66_71_n_5 : STD_LOGIC;
  signal mem_reg_0_15_6_11_n_0 : STD_LOGIC;
  signal mem_reg_0_15_6_11_n_1 : STD_LOGIC;
  signal my_empty0 : STD_LOGIC;
  signal \my_empty[1]_i_1__4_n_0\ : STD_LOGIC;
  signal \my_empty[7]_i_1__4_n_0\ : STD_LOGIC;
  signal \my_empty[7]_i_3__4_n_0\ : STD_LOGIC;
  signal \my_empty[7]_i_4__4_n_0\ : STD_LOGIC;
  signal \^my_empty_reg[1]_1\ : STD_LOGIC;
  signal \my_empty_reg_n_0_[7]\ : STD_LOGIC;
  signal my_full0 : STD_LOGIC;
  signal \my_full[4]_i_1__4_n_0\ : STD_LOGIC;
  signal \my_full[4]_i_3__4_n_0\ : STD_LOGIC;
  signal \my_full[4]_i_4__4_n_0\ : STD_LOGIC;
  signal \my_full_reg_n_0_[4]\ : STD_LOGIC;
  signal nxt_rd_ptr : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal nxt_wr_ptr : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \rd_ptr_reg_n_0_[0]\ : STD_LOGIC;
  signal \rd_ptr_reg_n_0_[1]\ : STD_LOGIC;
  signal \rd_ptr_reg_n_0_[2]\ : STD_LOGIC;
  signal \rd_ptr_reg_n_0_[3]\ : STD_LOGIC;
  signal rd_ptr_timing : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \rd_ptr_timing[3]_i_1__4_n_0\ : STD_LOGIC;
  signal wr_en : STD_LOGIC;
  attribute MAX_FANOUT : string;
  attribute MAX_FANOUT of wr_en : signal is "50";
  attribute RTL_MAX_FANOUT : string;
  attribute RTL_MAX_FANOUT of wr_en : signal is "found";
  signal wr_ptr : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal wr_ptr0 : STD_LOGIC;
  signal wr_ptr_timing : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal NLW_mem_reg_0_15_0_5_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_15_12_17_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_15_18_23_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_15_24_29_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_15_30_35_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_15_36_41_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_15_42_47_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_15_48_53_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_15_54_59_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_15_60_65_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_15_66_71_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_15_6_11_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_15_72_77_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_15_78_79_DOB_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_15_78_79_DOC_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_15_78_79_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \entry_cnt[0]_i_1__3\ : label is "soft_lutpair975";
  attribute SOFT_HLUTNM of \entry_cnt[1]_i_1__3\ : label is "soft_lutpair972";
  attribute SOFT_HLUTNM of \entry_cnt[3]_i_1__3\ : label is "soft_lutpair975";
  attribute SOFT_HLUTNM of \entry_cnt[4]_i_3__3\ : label is "soft_lutpair972";
  attribute METHODOLOGY_DRC_VIOS : string;
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_15_0_5 : label is "";
  attribute RTL_RAM_BITS : integer;
  attribute RTL_RAM_BITS of mem_reg_0_15_0_5 : label is 720;
  attribute RTL_RAM_NAME : string;
  attribute RTL_RAM_NAME of mem_reg_0_15_0_5 : label is "of_pre_fifo_gen.u_ddr_of_pre_fifo/mem";
  attribute ram_addr_begin : integer;
  attribute ram_addr_begin of mem_reg_0_15_0_5 : label is 0;
  attribute ram_addr_end : integer;
  attribute ram_addr_end of mem_reg_0_15_0_5 : label is 8;
  attribute ram_offset : integer;
  attribute ram_offset of mem_reg_0_15_0_5 : label is 0;
  attribute ram_slice_begin : integer;
  attribute ram_slice_begin of mem_reg_0_15_0_5 : label is 0;
  attribute ram_slice_end : integer;
  attribute ram_slice_end of mem_reg_0_15_0_5 : label is 5;
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_15_12_17 : label is "";
  attribute RTL_RAM_BITS of mem_reg_0_15_12_17 : label is 720;
  attribute RTL_RAM_NAME of mem_reg_0_15_12_17 : label is "of_pre_fifo_gen.u_ddr_of_pre_fifo/mem";
  attribute ram_addr_begin of mem_reg_0_15_12_17 : label is 0;
  attribute ram_addr_end of mem_reg_0_15_12_17 : label is 8;
  attribute ram_offset of mem_reg_0_15_12_17 : label is 0;
  attribute ram_slice_begin of mem_reg_0_15_12_17 : label is 12;
  attribute ram_slice_end of mem_reg_0_15_12_17 : label is 17;
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_15_18_23 : label is "";
  attribute RTL_RAM_BITS of mem_reg_0_15_18_23 : label is 720;
  attribute RTL_RAM_NAME of mem_reg_0_15_18_23 : label is "of_pre_fifo_gen.u_ddr_of_pre_fifo/mem";
  attribute ram_addr_begin of mem_reg_0_15_18_23 : label is 0;
  attribute ram_addr_end of mem_reg_0_15_18_23 : label is 8;
  attribute ram_offset of mem_reg_0_15_18_23 : label is 0;
  attribute ram_slice_begin of mem_reg_0_15_18_23 : label is 18;
  attribute ram_slice_end of mem_reg_0_15_18_23 : label is 23;
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_15_24_29 : label is "";
  attribute RTL_RAM_BITS of mem_reg_0_15_24_29 : label is 720;
  attribute RTL_RAM_NAME of mem_reg_0_15_24_29 : label is "of_pre_fifo_gen.u_ddr_of_pre_fifo/mem";
  attribute ram_addr_begin of mem_reg_0_15_24_29 : label is 0;
  attribute ram_addr_end of mem_reg_0_15_24_29 : label is 8;
  attribute ram_offset of mem_reg_0_15_24_29 : label is 0;
  attribute ram_slice_begin of mem_reg_0_15_24_29 : label is 24;
  attribute ram_slice_end of mem_reg_0_15_24_29 : label is 29;
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_15_30_35 : label is "";
  attribute RTL_RAM_BITS of mem_reg_0_15_30_35 : label is 720;
  attribute RTL_RAM_NAME of mem_reg_0_15_30_35 : label is "of_pre_fifo_gen.u_ddr_of_pre_fifo/mem";
  attribute ram_addr_begin of mem_reg_0_15_30_35 : label is 0;
  attribute ram_addr_end of mem_reg_0_15_30_35 : label is 8;
  attribute ram_offset of mem_reg_0_15_30_35 : label is 0;
  attribute ram_slice_begin of mem_reg_0_15_30_35 : label is 30;
  attribute ram_slice_end of mem_reg_0_15_30_35 : label is 35;
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_15_36_41 : label is "";
  attribute RTL_RAM_BITS of mem_reg_0_15_36_41 : label is 720;
  attribute RTL_RAM_NAME of mem_reg_0_15_36_41 : label is "of_pre_fifo_gen.u_ddr_of_pre_fifo/mem";
  attribute ram_addr_begin of mem_reg_0_15_36_41 : label is 0;
  attribute ram_addr_end of mem_reg_0_15_36_41 : label is 8;
  attribute ram_offset of mem_reg_0_15_36_41 : label is 0;
  attribute ram_slice_begin of mem_reg_0_15_36_41 : label is 36;
  attribute ram_slice_end of mem_reg_0_15_36_41 : label is 41;
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_15_42_47 : label is "";
  attribute RTL_RAM_BITS of mem_reg_0_15_42_47 : label is 720;
  attribute RTL_RAM_NAME of mem_reg_0_15_42_47 : label is "of_pre_fifo_gen.u_ddr_of_pre_fifo/mem";
  attribute ram_addr_begin of mem_reg_0_15_42_47 : label is 0;
  attribute ram_addr_end of mem_reg_0_15_42_47 : label is 8;
  attribute ram_offset of mem_reg_0_15_42_47 : label is 0;
  attribute ram_slice_begin of mem_reg_0_15_42_47 : label is 42;
  attribute ram_slice_end of mem_reg_0_15_42_47 : label is 47;
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_15_48_53 : label is "";
  attribute RTL_RAM_BITS of mem_reg_0_15_48_53 : label is 720;
  attribute RTL_RAM_NAME of mem_reg_0_15_48_53 : label is "of_pre_fifo_gen.u_ddr_of_pre_fifo/mem";
  attribute ram_addr_begin of mem_reg_0_15_48_53 : label is 0;
  attribute ram_addr_end of mem_reg_0_15_48_53 : label is 8;
  attribute ram_offset of mem_reg_0_15_48_53 : label is 0;
  attribute ram_slice_begin of mem_reg_0_15_48_53 : label is 48;
  attribute ram_slice_end of mem_reg_0_15_48_53 : label is 53;
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_15_54_59 : label is "";
  attribute RTL_RAM_BITS of mem_reg_0_15_54_59 : label is 720;
  attribute RTL_RAM_NAME of mem_reg_0_15_54_59 : label is "of_pre_fifo_gen.u_ddr_of_pre_fifo/mem";
  attribute ram_addr_begin of mem_reg_0_15_54_59 : label is 0;
  attribute ram_addr_end of mem_reg_0_15_54_59 : label is 8;
  attribute ram_offset of mem_reg_0_15_54_59 : label is 0;
  attribute ram_slice_begin of mem_reg_0_15_54_59 : label is 54;
  attribute ram_slice_end of mem_reg_0_15_54_59 : label is 59;
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_15_60_65 : label is "";
  attribute RTL_RAM_BITS of mem_reg_0_15_60_65 : label is 720;
  attribute RTL_RAM_NAME of mem_reg_0_15_60_65 : label is "of_pre_fifo_gen.u_ddr_of_pre_fifo/mem";
  attribute ram_addr_begin of mem_reg_0_15_60_65 : label is 0;
  attribute ram_addr_end of mem_reg_0_15_60_65 : label is 8;
  attribute ram_offset of mem_reg_0_15_60_65 : label is 0;
  attribute ram_slice_begin of mem_reg_0_15_60_65 : label is 60;
  attribute ram_slice_end of mem_reg_0_15_60_65 : label is 65;
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_15_66_71 : label is "";
  attribute RTL_RAM_BITS of mem_reg_0_15_66_71 : label is 720;
  attribute RTL_RAM_NAME of mem_reg_0_15_66_71 : label is "of_pre_fifo_gen.u_ddr_of_pre_fifo/mem";
  attribute ram_addr_begin of mem_reg_0_15_66_71 : label is 0;
  attribute ram_addr_end of mem_reg_0_15_66_71 : label is 8;
  attribute ram_offset of mem_reg_0_15_66_71 : label is 0;
  attribute ram_slice_begin of mem_reg_0_15_66_71 : label is 66;
  attribute ram_slice_end of mem_reg_0_15_66_71 : label is 71;
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_15_6_11 : label is "";
  attribute RTL_RAM_BITS of mem_reg_0_15_6_11 : label is 720;
  attribute RTL_RAM_NAME of mem_reg_0_15_6_11 : label is "of_pre_fifo_gen.u_ddr_of_pre_fifo/mem";
  attribute ram_addr_begin of mem_reg_0_15_6_11 : label is 0;
  attribute ram_addr_end of mem_reg_0_15_6_11 : label is 8;
  attribute ram_offset of mem_reg_0_15_6_11 : label is 0;
  attribute ram_slice_begin of mem_reg_0_15_6_11 : label is 6;
  attribute ram_slice_end of mem_reg_0_15_6_11 : label is 11;
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_15_72_77 : label is "";
  attribute RTL_RAM_BITS of mem_reg_0_15_72_77 : label is 720;
  attribute RTL_RAM_NAME of mem_reg_0_15_72_77 : label is "of_pre_fifo_gen.u_ddr_of_pre_fifo/mem";
  attribute ram_addr_begin of mem_reg_0_15_72_77 : label is 0;
  attribute ram_addr_end of mem_reg_0_15_72_77 : label is 8;
  attribute ram_offset of mem_reg_0_15_72_77 : label is 0;
  attribute ram_slice_begin of mem_reg_0_15_72_77 : label is 72;
  attribute ram_slice_end of mem_reg_0_15_72_77 : label is 77;
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_15_78_79 : label is "";
  attribute RTL_RAM_BITS of mem_reg_0_15_78_79 : label is 720;
  attribute RTL_RAM_NAME of mem_reg_0_15_78_79 : label is "of_pre_fifo_gen.u_ddr_of_pre_fifo/mem";
  attribute ram_addr_begin of mem_reg_0_15_78_79 : label is 0;
  attribute ram_addr_end of mem_reg_0_15_78_79 : label is 8;
  attribute ram_offset of mem_reg_0_15_78_79 : label is 0;
  attribute ram_slice_begin of mem_reg_0_15_78_79 : label is 78;
  attribute ram_slice_end of mem_reg_0_15_78_79 : label is 79;
  attribute SOFT_HLUTNM of \my_empty[7]_i_3__4\ : label is "soft_lutpair974";
  attribute SOFT_HLUTNM of \my_empty[7]_i_4__4\ : label is "soft_lutpair974";
  attribute syn_maxfan : string;
  attribute syn_maxfan of \my_empty_reg[1]\ : label is "3";
  attribute syn_maxfan of \my_empty_reg[7]\ : label is "3";
  attribute SOFT_HLUTNM of \my_full[4]_i_3__4\ : label is "soft_lutpair973";
  attribute SOFT_HLUTNM of \my_full[4]_i_4__4\ : label is "soft_lutpair973";
  attribute syn_maxfan of \my_full_reg[4]\ : label is "3";
  attribute SOFT_HLUTNM of \out_fifo_i_2__8\ : label is "soft_lutpair981";
  attribute SOFT_HLUTNM of \out_fifo_i_3__8\ : label is "soft_lutpair980";
  attribute SOFT_HLUTNM of \out_fifo_i_4__8\ : label is "soft_lutpair976";
  attribute SOFT_HLUTNM of \out_fifo_i_5__8\ : label is "soft_lutpair979";
  attribute SOFT_HLUTNM of \out_fifo_i_66__0\ : label is "soft_lutpair981";
  attribute SOFT_HLUTNM of \out_fifo_i_67__0\ : label is "soft_lutpair978";
  attribute SOFT_HLUTNM of \out_fifo_i_68__0\ : label is "soft_lutpair980";
  attribute SOFT_HLUTNM of \out_fifo_i_69__0\ : label is "soft_lutpair976";
  attribute SOFT_HLUTNM of \out_fifo_i_6__8\ : label is "soft_lutpair978";
  attribute SOFT_HLUTNM of \out_fifo_i_70__0\ : label is "soft_lutpair982";
  attribute SOFT_HLUTNM of \out_fifo_i_71__0\ : label is "soft_lutpair977";
  attribute SOFT_HLUTNM of \out_fifo_i_72__0\ : label is "soft_lutpair983";
  attribute SOFT_HLUTNM of \out_fifo_i_73__0\ : label is "soft_lutpair979";
  attribute SOFT_HLUTNM of \out_fifo_i_7__8\ : label is "soft_lutpair983";
  attribute SOFT_HLUTNM of \out_fifo_i_8__8\ : label is "soft_lutpair977";
  attribute SOFT_HLUTNM of \out_fifo_i_9__8\ : label is "soft_lutpair982";
  attribute syn_maxfan of \rd_ptr_reg[0]\ : label is "10";
  attribute syn_maxfan of \rd_ptr_reg[1]\ : label is "10";
  attribute syn_maxfan of \rd_ptr_reg[2]\ : label is "10";
  attribute syn_maxfan of \rd_ptr_reg[3]\ : label is "10";
  attribute SOFT_HLUTNM of \rd_ptr_timing[0]_i_1__9\ : label is "soft_lutpair987";
  attribute SOFT_HLUTNM of \rd_ptr_timing[1]_i_1__9\ : label is "soft_lutpair987";
  attribute SOFT_HLUTNM of \rd_ptr_timing[2]_i_1__4\ : label is "soft_lutpair985";
  attribute SOFT_HLUTNM of \rd_ptr_timing[3]_i_2__4\ : label is "soft_lutpair985";
  attribute KEEP : string;
  attribute KEEP of \rd_ptr_timing_reg[0]\ : label is "yes";
  attribute KEEP of \rd_ptr_timing_reg[1]\ : label is "yes";
  attribute KEEP of \rd_ptr_timing_reg[2]\ : label is "yes";
  attribute KEEP of \rd_ptr_timing_reg[3]\ : label is "yes";
  attribute SOFT_HLUTNM of \wr_ptr[0]_i_1__9\ : label is "soft_lutpair986";
  attribute SOFT_HLUTNM of \wr_ptr[1]_i_1__9\ : label is "soft_lutpair986";
  attribute SOFT_HLUTNM of \wr_ptr[2]_i_1__4\ : label is "soft_lutpair984";
  attribute SOFT_HLUTNM of \wr_ptr[3]_i_2__3\ : label is "soft_lutpair984";
  attribute syn_maxfan of \wr_ptr_reg[0]\ : label is "10";
  attribute syn_maxfan of \wr_ptr_reg[1]\ : label is "10";
  attribute syn_maxfan of \wr_ptr_reg[2]\ : label is "10";
  attribute syn_maxfan of \wr_ptr_reg[3]\ : label is "10";
  attribute KEEP of \wr_ptr_timing_reg[0]\ : label is "yes";
  attribute KEEP of \wr_ptr_timing_reg[1]\ : label is "yes";
  attribute KEEP of \wr_ptr_timing_reg[2]\ : label is "yes";
  attribute KEEP of \wr_ptr_timing_reg[3]\ : label is "yes";
begin
  Q(2 downto 0) <= \^q\(2 downto 0);
  \my_empty_reg[1]_1\ <= \^my_empty_reg[1]_1\;
\entry_cnt[0]_i_1__3\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \entry_cnt_reg_n_0_[0]\,
      O => \entry_cnt[0]_i_1__3_n_0\
    );
\entry_cnt[1]_i_1__3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AA6A5595"
    )
        port map (
      I0 => \entry_cnt_reg_n_0_[0]\,
      I1 => \my_empty_reg[7]_0\,
      I2 => phy_data_wr_en,
      I3 => \my_full_reg_n_0_[4]\,
      I4 => \entry_cnt_reg_n_0_[1]\,
      O => \entry_cnt[1]_i_1__3_n_0\
    );
\entry_cnt[2]_i_1__3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FF7F0080AAEA5515"
    )
        port map (
      I0 => \entry_cnt_reg_n_0_[0]\,
      I1 => \my_empty_reg[7]_0\,
      I2 => phy_data_wr_en,
      I3 => \my_full_reg_n_0_[4]\,
      I4 => \^q\(0),
      I5 => \entry_cnt_reg_n_0_[1]\,
      O => \entry_cnt[2]_i_1__3_n_0\
    );
\entry_cnt[3]_i_1__3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"7F80FE01"
    )
        port map (
      I0 => \entry_cnt10_out__0\,
      I1 => \entry_cnt_reg_n_0_[0]\,
      I2 => \entry_cnt_reg_n_0_[1]\,
      I3 => \^q\(1),
      I4 => \^q\(0),
      O => \entry_cnt[3]_i_1__3_n_0\
    );
\entry_cnt[4]_i_1__3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"5003"
    )
        port map (
      I0 => \my_full_reg_n_0_[4]\,
      I1 => \my_empty_reg_n_0_[7]\,
      I2 => \my_empty_reg[7]_0\,
      I3 => phy_data_wr_en,
      O => \entry_cnt[4]_i_1__3_n_0\
    );
\entry_cnt[4]_i_2__3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"7FFF8000FFFE0001"
    )
        port map (
      I0 => \entry_cnt_reg_n_0_[1]\,
      I1 => \entry_cnt_reg_n_0_[0]\,
      I2 => \entry_cnt10_out__0\,
      I3 => \^q\(0),
      I4 => \^q\(2),
      I5 => \^q\(1),
      O => \entry_cnt[4]_i_2__3_n_0\
    );
\entry_cnt[4]_i_3__3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"08"
    )
        port map (
      I0 => \my_empty_reg[7]_0\,
      I1 => phy_data_wr_en,
      I2 => \my_full_reg_n_0_[4]\,
      O => \entry_cnt10_out__0\
    );
\entry_cnt_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_ptr_timing_reg[3]_0\,
      CE => \entry_cnt[4]_i_1__3_n_0\,
      D => \entry_cnt[0]_i_1__3_n_0\,
      Q => \entry_cnt_reg_n_0_[0]\,
      R => ofifo_rst
    );
\entry_cnt_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_ptr_timing_reg[3]_0\,
      CE => \entry_cnt[4]_i_1__3_n_0\,
      D => \entry_cnt[1]_i_1__3_n_0\,
      Q => \entry_cnt_reg_n_0_[1]\,
      R => ofifo_rst
    );
\entry_cnt_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_ptr_timing_reg[3]_0\,
      CE => \entry_cnt[4]_i_1__3_n_0\,
      D => \entry_cnt[2]_i_1__3_n_0\,
      Q => \^q\(0),
      R => ofifo_rst
    );
\entry_cnt_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_ptr_timing_reg[3]_0\,
      CE => \entry_cnt[4]_i_1__3_n_0\,
      D => \entry_cnt[3]_i_1__3_n_0\,
      Q => \^q\(1),
      R => ofifo_rst
    );
\entry_cnt_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_ptr_timing_reg[3]_0\,
      CE => \entry_cnt[4]_i_1__3_n_0\,
      D => \entry_cnt[4]_i_2__3_n_0\,
      Q => \^q\(2),
      R => ofifo_rst
    );
mem_reg_0_15_0_5: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4) => '0',
      ADDRA(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRA(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRA(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRA(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRB(4) => '0',
      ADDRB(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRB(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRB(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRB(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRC(4) => '0',
      ADDRC(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRC(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRC(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRC(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRD(4) => '0',
      ADDRD(3 downto 0) => wr_ptr(3 downto 0),
      DIA(1 downto 0) => \out_fifo_i_75__0\(1 downto 0),
      DIB(1 downto 0) => \out_fifo_i_75__0\(3 downto 2),
      DIC(1 downto 0) => \out_fifo_i_75__0\(5 downto 4),
      DID(1 downto 0) => B"00",
      DOA(1) => mem_reg_0_15_0_5_n_0,
      DOA(0) => mem_reg_0_15_0_5_n_1,
      DOB(1) => mem_reg_0_15_0_5_n_2,
      DOB(0) => mem_reg_0_15_0_5_n_3,
      DOC(1) => mem_reg_0_15_0_5_n_4,
      DOC(0) => mem_reg_0_15_0_5_n_5,
      DOD(1 downto 0) => NLW_mem_reg_0_15_0_5_DOD_UNCONNECTED(1 downto 0),
      WCLK => \wr_ptr_timing_reg[3]_0\,
      WE => wr_en
    );
\mem_reg_0_15_0_5_i_1__3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2700"
    )
        port map (
      I0 => \my_empty_reg[7]_0\,
      I1 => \my_full_reg_n_0_[4]\,
      I2 => \^my_empty_reg[1]_1\,
      I3 => phy_data_wr_en,
      O => wr_en
    );
mem_reg_0_15_12_17: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4) => '0',
      ADDRA(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRA(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRA(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRA(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRB(4) => '0',
      ADDRB(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRB(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRB(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRB(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRC(4) => '0',
      ADDRC(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRC(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRC(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRC(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRD(4) => '0',
      ADDRD(3 downto 0) => wr_ptr(3 downto 0),
      DIA(1 downto 0) => \out_fifo_i_75__0\(13 downto 12),
      DIB(1 downto 0) => \out_fifo_i_75__0\(15 downto 14),
      DIC(1 downto 0) => \out_fifo_i_75__0\(17 downto 16),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => \rd_ptr_reg[3]_0\(5 downto 4),
      DOB(1 downto 0) => \rd_ptr_reg[3]_0\(7 downto 6),
      DOC(1 downto 0) => \rd_ptr_reg[3]_0\(9 downto 8),
      DOD(1 downto 0) => NLW_mem_reg_0_15_12_17_DOD_UNCONNECTED(1 downto 0),
      WCLK => \wr_ptr_timing_reg[3]_0\,
      WE => wr_en
    );
mem_reg_0_15_18_23: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4) => '0',
      ADDRA(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRA(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRA(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRA(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRB(4) => '0',
      ADDRB(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRB(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRB(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRB(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRC(4) => '0',
      ADDRC(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRC(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRC(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRC(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRD(4) => '0',
      ADDRD(3 downto 0) => wr_ptr(3 downto 0),
      DIA(1 downto 0) => \out_fifo_i_75__0\(19 downto 18),
      DIB(1 downto 0) => \out_fifo_i_75__0\(21 downto 20),
      DIC(1 downto 0) => \out_fifo_i_75__0\(23 downto 22),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => \rd_ptr_reg[3]_0\(11 downto 10),
      DOB(1 downto 0) => \rd_ptr_reg[3]_0\(13 downto 12),
      DOC(1 downto 0) => \rd_ptr_reg[3]_0\(15 downto 14),
      DOD(1 downto 0) => NLW_mem_reg_0_15_18_23_DOD_UNCONNECTED(1 downto 0),
      WCLK => \wr_ptr_timing_reg[3]_0\,
      WE => wr_en
    );
mem_reg_0_15_24_29: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4) => '0',
      ADDRA(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRA(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRA(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRA(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRB(4) => '0',
      ADDRB(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRB(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRB(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRB(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRC(4) => '0',
      ADDRC(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRC(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRC(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRC(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRD(4) => '0',
      ADDRD(3 downto 0) => wr_ptr(3 downto 0),
      DIA(1 downto 0) => \out_fifo_i_75__0\(25 downto 24),
      DIB(1 downto 0) => \out_fifo_i_75__0\(27 downto 26),
      DIC(1 downto 0) => \out_fifo_i_75__0\(29 downto 28),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => \rd_ptr_reg[3]_0\(17 downto 16),
      DOB(1 downto 0) => \rd_ptr_reg[3]_0\(19 downto 18),
      DOC(1 downto 0) => \rd_ptr_reg[3]_0\(21 downto 20),
      DOD(1 downto 0) => NLW_mem_reg_0_15_24_29_DOD_UNCONNECTED(1 downto 0),
      WCLK => \wr_ptr_timing_reg[3]_0\,
      WE => wr_en
    );
mem_reg_0_15_30_35: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4) => '0',
      ADDRA(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRA(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRA(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRA(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRB(4) => '0',
      ADDRB(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRB(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRB(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRB(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRC(4) => '0',
      ADDRC(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRC(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRC(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRC(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRD(4) => '0',
      ADDRD(3 downto 0) => wr_ptr(3 downto 0),
      DIA(1 downto 0) => \out_fifo_i_75__0\(31 downto 30),
      DIB(1 downto 0) => \out_fifo_i_75__0\(33 downto 32),
      DIC(1 downto 0) => \out_fifo_i_75__0\(35 downto 34),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => \rd_ptr_reg[3]_0\(23 downto 22),
      DOB(1 downto 0) => \rd_ptr_reg[3]_0\(25 downto 24),
      DOC(1 downto 0) => \rd_ptr_reg[3]_0\(27 downto 26),
      DOD(1 downto 0) => NLW_mem_reg_0_15_30_35_DOD_UNCONNECTED(1 downto 0),
      WCLK => \wr_ptr_timing_reg[3]_0\,
      WE => wr_en
    );
mem_reg_0_15_36_41: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4) => '0',
      ADDRA(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRA(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRA(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRA(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRB(4) => '0',
      ADDRB(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRB(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRB(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRB(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRC(4) => '0',
      ADDRC(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRC(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRC(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRC(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRD(4) => '0',
      ADDRD(3 downto 0) => wr_ptr(3 downto 0),
      DIA(1 downto 0) => \out_fifo_i_75__0\(37 downto 36),
      DIB(1 downto 0) => \out_fifo_i_75__0\(39 downto 38),
      DIC(1 downto 0) => \out_fifo_i_75__0\(41 downto 40),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => \rd_ptr_reg[3]_0\(29 downto 28),
      DOB(1 downto 0) => \rd_ptr_reg[3]_0\(31 downto 30),
      DOC(1 downto 0) => \rd_ptr_reg[3]_0\(33 downto 32),
      DOD(1 downto 0) => NLW_mem_reg_0_15_36_41_DOD_UNCONNECTED(1 downto 0),
      WCLK => \wr_ptr_timing_reg[3]_0\,
      WE => wr_en
    );
mem_reg_0_15_42_47: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4) => '0',
      ADDRA(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRA(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRA(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRA(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRB(4) => '0',
      ADDRB(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRB(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRB(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRB(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRC(4) => '0',
      ADDRC(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRC(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRC(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRC(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRD(4) => '0',
      ADDRD(3 downto 0) => wr_ptr(3 downto 0),
      DIA(1 downto 0) => \out_fifo_i_75__0\(43 downto 42),
      DIB(1 downto 0) => \out_fifo_i_75__0\(45 downto 44),
      DIC(1 downto 0) => \out_fifo_i_75__0\(47 downto 46),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => \rd_ptr_reg[3]_0\(35 downto 34),
      DOB(1 downto 0) => \rd_ptr_reg[3]_0\(37 downto 36),
      DOC(1 downto 0) => \rd_ptr_reg[3]_0\(39 downto 38),
      DOD(1 downto 0) => NLW_mem_reg_0_15_42_47_DOD_UNCONNECTED(1 downto 0),
      WCLK => \wr_ptr_timing_reg[3]_0\,
      WE => wr_en
    );
mem_reg_0_15_48_53: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4) => '0',
      ADDRA(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRA(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRA(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRA(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRB(4) => '0',
      ADDRB(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRB(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRB(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRB(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRC(4) => '0',
      ADDRC(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRC(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRC(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRC(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRD(4) => '0',
      ADDRD(3 downto 0) => wr_ptr(3 downto 0),
      DIA(1 downto 0) => \out_fifo_i_75__0\(49 downto 48),
      DIB(1 downto 0) => \out_fifo_i_75__0\(51 downto 50),
      DIC(1 downto 0) => \out_fifo_i_75__0\(53 downto 52),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => \rd_ptr_reg[3]_0\(41 downto 40),
      DOB(1 downto 0) => \rd_ptr_reg[3]_0\(43 downto 42),
      DOC(1 downto 0) => \rd_ptr_reg[3]_0\(45 downto 44),
      DOD(1 downto 0) => NLW_mem_reg_0_15_48_53_DOD_UNCONNECTED(1 downto 0),
      WCLK => \wr_ptr_timing_reg[3]_0\,
      WE => wr_en
    );
mem_reg_0_15_54_59: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4) => '0',
      ADDRA(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRA(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRA(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRA(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRB(4) => '0',
      ADDRB(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRB(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRB(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRB(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRC(4) => '0',
      ADDRC(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRC(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRC(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRC(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRD(4) => '0',
      ADDRD(3 downto 0) => wr_ptr(3 downto 0),
      DIA(1 downto 0) => \out_fifo_i_75__0\(55 downto 54),
      DIB(1 downto 0) => \out_fifo_i_75__0\(57 downto 56),
      DIC(1 downto 0) => \out_fifo_i_75__0\(59 downto 58),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => \rd_ptr_reg[3]_0\(47 downto 46),
      DOB(1 downto 0) => \rd_ptr_reg[3]_0\(49 downto 48),
      DOC(1 downto 0) => \rd_ptr_reg[3]_0\(51 downto 50),
      DOD(1 downto 0) => NLW_mem_reg_0_15_54_59_DOD_UNCONNECTED(1 downto 0),
      WCLK => \wr_ptr_timing_reg[3]_0\,
      WE => wr_en
    );
mem_reg_0_15_60_65: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4) => '0',
      ADDRA(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRA(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRA(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRA(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRB(4) => '0',
      ADDRB(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRB(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRB(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRB(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRC(4) => '0',
      ADDRC(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRC(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRC(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRC(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRD(4) => '0',
      ADDRD(3 downto 0) => wr_ptr(3 downto 0),
      DIA(1 downto 0) => \out_fifo_i_75__0\(61 downto 60),
      DIB(1 downto 0) => \out_fifo_i_75__0\(63 downto 62),
      DIC(1 downto 0) => B"00",
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => \rd_ptr_reg[3]_0\(53 downto 52),
      DOB(1 downto 0) => \rd_ptr_reg[3]_0\(55 downto 54),
      DOC(1) => mem_reg_0_15_60_65_n_4,
      DOC(0) => mem_reg_0_15_60_65_n_5,
      DOD(1 downto 0) => NLW_mem_reg_0_15_60_65_DOD_UNCONNECTED(1 downto 0),
      WCLK => \wr_ptr_timing_reg[3]_0\,
      WE => wr_en
    );
mem_reg_0_15_66_71: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4) => '0',
      ADDRA(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRA(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRA(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRA(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRB(4) => '0',
      ADDRB(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRB(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRB(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRB(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRC(4) => '0',
      ADDRC(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRC(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRC(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRC(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRD(4) => '0',
      ADDRD(3 downto 0) => wr_ptr(3 downto 0),
      DIA(1 downto 0) => B"00",
      DIB(1 downto 0) => B"00",
      DIC(1 downto 0) => B"00",
      DID(1 downto 0) => B"00",
      DOA(1) => mem_reg_0_15_66_71_n_0,
      DOA(0) => mem_reg_0_15_66_71_n_1,
      DOB(1) => mem_reg_0_15_66_71_n_2,
      DOB(0) => mem_reg_0_15_66_71_n_3,
      DOC(1) => mem_reg_0_15_66_71_n_4,
      DOC(0) => mem_reg_0_15_66_71_n_5,
      DOD(1 downto 0) => NLW_mem_reg_0_15_66_71_DOD_UNCONNECTED(1 downto 0),
      WCLK => \wr_ptr_timing_reg[3]_0\,
      WE => wr_en
    );
mem_reg_0_15_6_11: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4) => '0',
      ADDRA(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRA(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRA(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRA(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRB(4) => '0',
      ADDRB(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRB(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRB(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRB(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRC(4) => '0',
      ADDRC(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRC(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRC(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRC(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRD(4) => '0',
      ADDRD(3 downto 0) => wr_ptr(3 downto 0),
      DIA(1 downto 0) => \out_fifo_i_75__0\(7 downto 6),
      DIB(1 downto 0) => \out_fifo_i_75__0\(9 downto 8),
      DIC(1 downto 0) => \out_fifo_i_75__0\(11 downto 10),
      DID(1 downto 0) => B"00",
      DOA(1) => mem_reg_0_15_6_11_n_0,
      DOA(0) => mem_reg_0_15_6_11_n_1,
      DOB(1 downto 0) => \rd_ptr_reg[3]_0\(1 downto 0),
      DOC(1 downto 0) => \rd_ptr_reg[3]_0\(3 downto 2),
      DOD(1 downto 0) => NLW_mem_reg_0_15_6_11_DOD_UNCONNECTED(1 downto 0),
      WCLK => \wr_ptr_timing_reg[3]_0\,
      WE => wr_en
    );
mem_reg_0_15_72_77: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4) => '0',
      ADDRA(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRA(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRA(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRA(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRB(4) => '0',
      ADDRB(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRB(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRB(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRB(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRC(4) => '0',
      ADDRC(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRC(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRC(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRC(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRD(4) => '0',
      ADDRD(3 downto 0) => wr_ptr(3 downto 0),
      DIA(1 downto 0) => \out_fifo_i_75__0\(65 downto 64),
      DIB(1 downto 0) => \out_fifo_i_75__0\(67 downto 66),
      DIC(1 downto 0) => \out_fifo_i_75__0\(69 downto 68),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => \rd_ptr_reg[3]_0\(57 downto 56),
      DOB(1 downto 0) => \rd_ptr_reg[3]_0\(59 downto 58),
      DOC(1 downto 0) => \rd_ptr_reg[3]_0\(61 downto 60),
      DOD(1 downto 0) => NLW_mem_reg_0_15_72_77_DOD_UNCONNECTED(1 downto 0),
      WCLK => \wr_ptr_timing_reg[3]_0\,
      WE => wr_en
    );
mem_reg_0_15_78_79: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4) => '0',
      ADDRA(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRA(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRA(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRA(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRB(4) => '0',
      ADDRB(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRB(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRB(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRB(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRC(4) => '0',
      ADDRC(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRC(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRC(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRC(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRD(4) => '0',
      ADDRD(3 downto 0) => wr_ptr(3 downto 0),
      DIA(1 downto 0) => \out_fifo_i_75__0\(71 downto 70),
      DIB(1 downto 0) => B"00",
      DIC(1 downto 0) => B"00",
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => \rd_ptr_reg[3]_0\(63 downto 62),
      DOB(1 downto 0) => NLW_mem_reg_0_15_78_79_DOB_UNCONNECTED(1 downto 0),
      DOC(1 downto 0) => NLW_mem_reg_0_15_78_79_DOC_UNCONNECTED(1 downto 0),
      DOD(1 downto 0) => NLW_mem_reg_0_15_78_79_DOD_UNCONNECTED(1 downto 0),
      WCLK => \wr_ptr_timing_reg[3]_0\,
      WE => wr_en
    );
\my_empty[1]_i_1__4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFF701F700"
    )
        port map (
      I0 => \my_empty_reg[7]_0\,
      I1 => phy_data_wr_en,
      I2 => \my_full_reg_n_0_[4]\,
      I3 => \^my_empty_reg[1]_1\,
      I4 => my_empty0,
      I5 => ofifo_rst,
      O => \my_empty[1]_i_1__4_n_0\
    );
\my_empty[7]_i_1__4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFF701F700"
    )
        port map (
      I0 => \my_empty_reg[7]_0\,
      I1 => phy_data_wr_en,
      I2 => \my_full_reg_n_0_[4]\,
      I3 => \my_empty_reg_n_0_[7]\,
      I4 => my_empty0,
      I5 => ofifo_rst,
      O => \my_empty[7]_i_1__4_n_0\
    );
\my_empty[7]_i_2__4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"4A400D08"
    )
        port map (
      I0 => wr_ptr_timing(2),
      I1 => \my_empty[7]_i_3__4_n_0\,
      I2 => wr_ptr_timing(3),
      I3 => \my_empty[7]_i_4__4_n_0\,
      I4 => \rd_ptr_reg_n_0_[2]\,
      O => my_empty0
    );
\my_empty[7]_i_3__4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000040"
    )
        port map (
      I0 => wr_ptr_timing(1),
      I1 => \rd_ptr_reg_n_0_[0]\,
      I2 => \rd_ptr_reg_n_0_[1]\,
      I3 => \rd_ptr_reg_n_0_[3]\,
      I4 => wr_ptr_timing(0),
      O => \my_empty[7]_i_3__4_n_0\
    );
\my_empty[7]_i_4__4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"84210842"
    )
        port map (
      I0 => wr_ptr_timing(0),
      I1 => wr_ptr_timing(1),
      I2 => \rd_ptr_reg_n_0_[0]\,
      I3 => \rd_ptr_reg_n_0_[1]\,
      I4 => \rd_ptr_reg_n_0_[3]\,
      O => \my_empty[7]_i_4__4_n_0\
    );
\my_empty_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_ptr_timing_reg[3]_0\,
      CE => '1',
      D => \my_empty[1]_i_1__4_n_0\,
      Q => \^my_empty_reg[1]_1\,
      R => '0'
    );
\my_empty_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_ptr_timing_reg[3]_0\,
      CE => '1',
      D => \my_empty[7]_i_1__4_n_0\,
      Q => \my_empty_reg_n_0_[7]\,
      R => '0'
    );
\my_full[4]_i_1__4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000FFFC0080"
    )
        port map (
      I0 => my_full0,
      I1 => phy_data_wr_en,
      I2 => \my_empty_reg[7]_0\,
      I3 => \my_empty_reg_n_0_[7]\,
      I4 => \my_full_reg_n_0_[4]\,
      I5 => ofifo_rst,
      O => \my_full[4]_i_1__4_n_0\
    );
\my_full[4]_i_2__4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"4A400D08"
    )
        port map (
      I0 => rd_ptr_timing(2),
      I1 => \my_full[4]_i_3__4_n_0\,
      I2 => rd_ptr_timing(3),
      I3 => \my_full[4]_i_4__4_n_0\,
      I4 => wr_ptr(2),
      O => my_full0
    );
\my_full[4]_i_3__4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000040"
    )
        port map (
      I0 => rd_ptr_timing(1),
      I1 => wr_ptr(0),
      I2 => wr_ptr(1),
      I3 => wr_ptr(3),
      I4 => rd_ptr_timing(0),
      O => \my_full[4]_i_3__4_n_0\
    );
\my_full[4]_i_4__4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"84210842"
    )
        port map (
      I0 => rd_ptr_timing(0),
      I1 => rd_ptr_timing(1),
      I2 => wr_ptr(0),
      I3 => wr_ptr(1),
      I4 => wr_ptr(3),
      O => \my_full[4]_i_4__4_n_0\
    );
\my_full_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_ptr_timing_reg[3]_0\,
      CE => '1',
      D => \my_full[4]_i_1__4_n_0\,
      Q => \my_full_reg_n_0_[4]\,
      R => '0'
    );
\out_fifo_i_1__4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"0D"
    )
        port map (
      I0 => \^my_empty_reg[1]_1\,
      I1 => phy_data_wr_en,
      I2 => \my_empty_reg[7]_0\,
      O => \my_empty_reg[1]_0\
    );
\out_fifo_i_2__8\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"88F0"
    )
        port map (
      I0 => out_fifo_1,
      I1 => out_fifo_0(7),
      I2 => mem_reg_0_15_6_11_n_0,
      I3 => \^my_empty_reg[1]_1\,
      O => D0(7)
    );
\out_fifo_i_3__8\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"88F0"
    )
        port map (
      I0 => out_fifo_1,
      I1 => out_fifo_0(6),
      I2 => mem_reg_0_15_6_11_n_1,
      I3 => \^my_empty_reg[1]_1\,
      O => D0(6)
    );
\out_fifo_i_4__8\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"88F0"
    )
        port map (
      I0 => out_fifo_1,
      I1 => out_fifo_0(5),
      I2 => mem_reg_0_15_0_5_n_4,
      I3 => \^my_empty_reg[1]_1\,
      O => D0(5)
    );
\out_fifo_i_5__8\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"88F0"
    )
        port map (
      I0 => out_fifo_1,
      I1 => out_fifo_0(4),
      I2 => mem_reg_0_15_0_5_n_5,
      I3 => \^my_empty_reg[1]_1\,
      O => D0(4)
    );
\out_fifo_i_66__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => mem_reg_0_15_66_71_n_4,
      I1 => \^my_empty_reg[1]_1\,
      O => D8(7)
    );
\out_fifo_i_67__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => mem_reg_0_15_66_71_n_5,
      I1 => \^my_empty_reg[1]_1\,
      O => D8(6)
    );
\out_fifo_i_68__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => mem_reg_0_15_66_71_n_2,
      I1 => \^my_empty_reg[1]_1\,
      O => D8(5)
    );
\out_fifo_i_69__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => mem_reg_0_15_66_71_n_3,
      I1 => \^my_empty_reg[1]_1\,
      O => D8(4)
    );
\out_fifo_i_6__8\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"88F0"
    )
        port map (
      I0 => out_fifo_1,
      I1 => out_fifo_0(3),
      I2 => mem_reg_0_15_0_5_n_2,
      I3 => \^my_empty_reg[1]_1\,
      O => D0(3)
    );
\out_fifo_i_70__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => mem_reg_0_15_66_71_n_0,
      I1 => \^my_empty_reg[1]_1\,
      O => D8(3)
    );
\out_fifo_i_71__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => mem_reg_0_15_66_71_n_1,
      I1 => \^my_empty_reg[1]_1\,
      O => D8(2)
    );
\out_fifo_i_72__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => mem_reg_0_15_60_65_n_4,
      I1 => \^my_empty_reg[1]_1\,
      O => D8(1)
    );
\out_fifo_i_73__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => mem_reg_0_15_60_65_n_5,
      I1 => \^my_empty_reg[1]_1\,
      O => D8(0)
    );
\out_fifo_i_7__8\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"88F0"
    )
        port map (
      I0 => out_fifo_1,
      I1 => out_fifo_0(2),
      I2 => mem_reg_0_15_0_5_n_3,
      I3 => \^my_empty_reg[1]_1\,
      O => D0(2)
    );
\out_fifo_i_8__8\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"88F0"
    )
        port map (
      I0 => out_fifo,
      I1 => out_fifo_0(1),
      I2 => mem_reg_0_15_0_5_n_0,
      I3 => \^my_empty_reg[1]_1\,
      O => D0(1)
    );
\out_fifo_i_9__8\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"88F0"
    )
        port map (
      I0 => out_fifo,
      I1 => out_fifo_0(0),
      I2 => mem_reg_0_15_0_5_n_1,
      I3 => \^my_empty_reg[1]_1\,
      O => D0(0)
    );
\rd_ptr_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_ptr_timing_reg[3]_0\,
      CE => \rd_ptr_timing[3]_i_1__4_n_0\,
      D => nxt_rd_ptr(0),
      Q => \rd_ptr_reg_n_0_[0]\,
      R => ofifo_rst
    );
\rd_ptr_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_ptr_timing_reg[3]_0\,
      CE => \rd_ptr_timing[3]_i_1__4_n_0\,
      D => nxt_rd_ptr(1),
      Q => \rd_ptr_reg_n_0_[1]\,
      R => ofifo_rst
    );
\rd_ptr_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_ptr_timing_reg[3]_0\,
      CE => \rd_ptr_timing[3]_i_1__4_n_0\,
      D => nxt_rd_ptr(2),
      Q => \rd_ptr_reg_n_0_[2]\,
      R => ofifo_rst
    );
\rd_ptr_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_ptr_timing_reg[3]_0\,
      CE => \rd_ptr_timing[3]_i_1__4_n_0\,
      D => nxt_rd_ptr(3),
      Q => \rd_ptr_reg_n_0_[3]\,
      R => ofifo_rst
    );
\rd_ptr_timing[0]_i_1__9\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => \rd_ptr_reg_n_0_[3]\,
      I1 => \rd_ptr_reg_n_0_[0]\,
      O => nxt_rd_ptr(0)
    );
\rd_ptr_timing[1]_i_1__9\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B4"
    )
        port map (
      I0 => \rd_ptr_reg_n_0_[3]\,
      I1 => \rd_ptr_reg_n_0_[0]\,
      I2 => \rd_ptr_reg_n_0_[1]\,
      O => nxt_rd_ptr(1)
    );
\rd_ptr_timing[2]_i_1__4\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"AA6A"
    )
        port map (
      I0 => \rd_ptr_reg_n_0_[2]\,
      I1 => \rd_ptr_reg_n_0_[0]\,
      I2 => \rd_ptr_reg_n_0_[1]\,
      I3 => \rd_ptr_reg_n_0_[3]\,
      O => nxt_rd_ptr(2)
    );
\rd_ptr_timing[3]_i_1__4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \my_empty_reg[7]_0\,
      I1 => \my_empty_reg_n_0_[7]\,
      O => \rd_ptr_timing[3]_i_1__4_n_0\
    );
\rd_ptr_timing[3]_i_2__4\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4000"
    )
        port map (
      I0 => \rd_ptr_reg_n_0_[3]\,
      I1 => \rd_ptr_reg_n_0_[1]\,
      I2 => \rd_ptr_reg_n_0_[0]\,
      I3 => \rd_ptr_reg_n_0_[2]\,
      O => nxt_rd_ptr(3)
    );
\rd_ptr_timing_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_ptr_timing_reg[3]_0\,
      CE => \rd_ptr_timing[3]_i_1__4_n_0\,
      D => nxt_rd_ptr(0),
      Q => rd_ptr_timing(0),
      R => ofifo_rst
    );
\rd_ptr_timing_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_ptr_timing_reg[3]_0\,
      CE => \rd_ptr_timing[3]_i_1__4_n_0\,
      D => nxt_rd_ptr(1),
      Q => rd_ptr_timing(1),
      R => ofifo_rst
    );
\rd_ptr_timing_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_ptr_timing_reg[3]_0\,
      CE => \rd_ptr_timing[3]_i_1__4_n_0\,
      D => nxt_rd_ptr(2),
      Q => rd_ptr_timing(2),
      R => ofifo_rst
    );
\rd_ptr_timing_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_ptr_timing_reg[3]_0\,
      CE => \rd_ptr_timing[3]_i_1__4_n_0\,
      D => nxt_rd_ptr(3),
      Q => rd_ptr_timing(3),
      R => ofifo_rst
    );
\wr_ptr[0]_i_1__9\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => wr_ptr(3),
      I1 => wr_ptr(0),
      O => nxt_wr_ptr(0)
    );
\wr_ptr[1]_i_1__9\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B4"
    )
        port map (
      I0 => wr_ptr(3),
      I1 => wr_ptr(0),
      I2 => wr_ptr(1),
      O => nxt_wr_ptr(1)
    );
\wr_ptr[2]_i_1__4\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"AA6A"
    )
        port map (
      I0 => wr_ptr(2),
      I1 => wr_ptr(0),
      I2 => wr_ptr(1),
      I3 => wr_ptr(3),
      O => nxt_wr_ptr(2)
    );
\wr_ptr[3]_i_1__4\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"082A"
    )
        port map (
      I0 => phy_data_wr_en,
      I1 => \my_empty_reg[7]_0\,
      I2 => \my_full_reg_n_0_[4]\,
      I3 => \my_empty_reg_n_0_[7]\,
      O => wr_ptr0
    );
\wr_ptr[3]_i_2__3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4000"
    )
        port map (
      I0 => wr_ptr(3),
      I1 => wr_ptr(1),
      I2 => wr_ptr(0),
      I3 => wr_ptr(2),
      O => nxt_wr_ptr(3)
    );
\wr_ptr_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_ptr_timing_reg[3]_0\,
      CE => wr_ptr0,
      D => nxt_wr_ptr(0),
      Q => wr_ptr(0),
      R => ofifo_rst
    );
\wr_ptr_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_ptr_timing_reg[3]_0\,
      CE => wr_ptr0,
      D => nxt_wr_ptr(1),
      Q => wr_ptr(1),
      R => ofifo_rst
    );
\wr_ptr_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_ptr_timing_reg[3]_0\,
      CE => wr_ptr0,
      D => nxt_wr_ptr(2),
      Q => wr_ptr(2),
      R => ofifo_rst
    );
\wr_ptr_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_ptr_timing_reg[3]_0\,
      CE => wr_ptr0,
      D => nxt_wr_ptr(3),
      Q => wr_ptr(3),
      R => ofifo_rst
    );
\wr_ptr_timing_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_ptr_timing_reg[3]_0\,
      CE => wr_ptr0,
      D => nxt_wr_ptr(0),
      Q => wr_ptr_timing(0),
      R => ofifo_rst
    );
\wr_ptr_timing_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_ptr_timing_reg[3]_0\,
      CE => wr_ptr0,
      D => nxt_wr_ptr(1),
      Q => wr_ptr_timing(1),
      R => ofifo_rst
    );
\wr_ptr_timing_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_ptr_timing_reg[3]_0\,
      CE => wr_ptr0,
      D => nxt_wr_ptr(2),
      Q => wr_ptr_timing(2),
      R => ofifo_rst
    );
\wr_ptr_timing_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_ptr_timing_reg[3]_0\,
      CE => wr_ptr0,
      D => nxt_wr_ptr(3),
      Q => wr_ptr_timing(3),
      R => ofifo_rst
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \mig_mig_7series_v4_2_ddr_of_pre_fifo__parameterized1_22\ is
  port (
    \my_empty_reg[1]_0\ : out STD_LOGIC;
    \my_empty_reg[1]_1\ : out STD_LOGIC;
    D0 : out STD_LOGIC_VECTOR ( 7 downto 0 );
    D1 : out STD_LOGIC_VECTOR ( 3 downto 0 );
    D2 : out STD_LOGIC_VECTOR ( 7 downto 0 );
    D3 : out STD_LOGIC_VECTOR ( 3 downto 0 );
    D4 : out STD_LOGIC_VECTOR ( 3 downto 0 );
    D7 : out STD_LOGIC_VECTOR ( 3 downto 0 );
    D8 : out STD_LOGIC_VECTOR ( 3 downto 0 );
    D9 : out STD_LOGIC_VECTOR ( 1 downto 0 );
    D5 : out STD_LOGIC_VECTOR ( 3 downto 0 );
    \rd_ptr_reg[3]_0\ : out STD_LOGIC_VECTOR ( 35 downto 0 );
    SR : in STD_LOGIC_VECTOR ( 0 to 0 );
    \wr_ptr_timing_reg[3]_0\ : in STD_LOGIC;
    phy_cmd_wr_en : in STD_LOGIC;
    \rd_ptr_reg[3]_1\ : in STD_LOGIC;
    out_fifo : in STD_LOGIC;
    mc_cas_n : in STD_LOGIC_VECTOR ( 0 to 0 );
    mc_address : in STD_LOGIC_VECTOR ( 3 downto 0 );
    out_fifo_0 : in STD_LOGIC;
    d_in : in STD_LOGIC_VECTOR ( 41 downto 0 );
    out_fifo_1 : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \mig_mig_7series_v4_2_ddr_of_pre_fifo__parameterized1_22\ : entity is "mig_7series_v4_2_ddr_of_pre_fifo";
end \mig_mig_7series_v4_2_ddr_of_pre_fifo__parameterized1_22\;

architecture STRUCTURE of \mig_mig_7series_v4_2_ddr_of_pre_fifo__parameterized1_22\ is
  signal mem_reg_0_15_0_5_n_0 : STD_LOGIC;
  signal mem_reg_0_15_0_5_n_1 : STD_LOGIC;
  signal mem_reg_0_15_0_5_n_2 : STD_LOGIC;
  signal mem_reg_0_15_0_5_n_3 : STD_LOGIC;
  signal mem_reg_0_15_0_5_n_4 : STD_LOGIC;
  signal mem_reg_0_15_0_5_n_5 : STD_LOGIC;
  signal mem_reg_0_15_12_17_n_0 : STD_LOGIC;
  signal mem_reg_0_15_12_17_n_1 : STD_LOGIC;
  signal mem_reg_0_15_12_17_n_2 : STD_LOGIC;
  signal mem_reg_0_15_12_17_n_3 : STD_LOGIC;
  signal mem_reg_0_15_12_17_n_4 : STD_LOGIC;
  signal mem_reg_0_15_12_17_n_5 : STD_LOGIC;
  signal mem_reg_0_15_18_23_n_0 : STD_LOGIC;
  signal mem_reg_0_15_18_23_n_1 : STD_LOGIC;
  signal mem_reg_0_15_18_23_n_2 : STD_LOGIC;
  signal mem_reg_0_15_18_23_n_3 : STD_LOGIC;
  signal mem_reg_0_15_18_23_n_4 : STD_LOGIC;
  signal mem_reg_0_15_18_23_n_5 : STD_LOGIC;
  signal mem_reg_0_15_24_29_n_4 : STD_LOGIC;
  signal mem_reg_0_15_24_29_n_5 : STD_LOGIC;
  signal mem_reg_0_15_30_35_n_0 : STD_LOGIC;
  signal mem_reg_0_15_30_35_n_1 : STD_LOGIC;
  signal mem_reg_0_15_36_41_n_0 : STD_LOGIC;
  signal mem_reg_0_15_36_41_n_1 : STD_LOGIC;
  signal mem_reg_0_15_36_41_n_2 : STD_LOGIC;
  signal mem_reg_0_15_36_41_n_3 : STD_LOGIC;
  signal mem_reg_0_15_36_41_n_4 : STD_LOGIC;
  signal mem_reg_0_15_36_41_n_5 : STD_LOGIC;
  signal mem_reg_0_15_42_47_n_0 : STD_LOGIC;
  signal mem_reg_0_15_42_47_n_1 : STD_LOGIC;
  signal mem_reg_0_15_60_65_n_0 : STD_LOGIC;
  signal mem_reg_0_15_60_65_n_1 : STD_LOGIC;
  signal mem_reg_0_15_60_65_n_2 : STD_LOGIC;
  signal mem_reg_0_15_60_65_n_3 : STD_LOGIC;
  signal mem_reg_0_15_66_71_n_2 : STD_LOGIC;
  signal mem_reg_0_15_66_71_n_3 : STD_LOGIC;
  signal mem_reg_0_15_66_71_n_4 : STD_LOGIC;
  signal mem_reg_0_15_66_71_n_5 : STD_LOGIC;
  signal mem_reg_0_15_6_11_n_0 : STD_LOGIC;
  signal mem_reg_0_15_6_11_n_1 : STD_LOGIC;
  signal mem_reg_0_15_72_77_n_4 : STD_LOGIC;
  signal mem_reg_0_15_72_77_n_5 : STD_LOGIC;
  signal \my_empty[1]_i_1_n_0\ : STD_LOGIC;
  signal \my_empty[6]_i_1_n_0\ : STD_LOGIC;
  signal \my_empty[6]_i_2__0_n_0\ : STD_LOGIC;
  signal \my_empty[6]_i_3__0_n_0\ : STD_LOGIC;
  signal \my_empty[6]_i_4__0_n_0\ : STD_LOGIC;
  signal \^my_empty_reg[1]_0\ : STD_LOGIC;
  signal \my_empty_reg_n_0_[6]\ : STD_LOGIC;
  signal \my_full[3]_i_1__0_n_0\ : STD_LOGIC;
  signal \my_full[3]_i_2__0_n_0\ : STD_LOGIC;
  signal \my_full[3]_i_3__0_n_0\ : STD_LOGIC;
  signal \my_full[3]_i_4__0_n_0\ : STD_LOGIC;
  signal \my_full_reg_n_0_[3]\ : STD_LOGIC;
  signal nxt_rd_ptr : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal nxt_wr_ptr : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \rd_ptr[0]_i_1__0_n_0\ : STD_LOGIC;
  signal \rd_ptr_reg_n_0_[0]\ : STD_LOGIC;
  signal \rd_ptr_reg_n_0_[1]\ : STD_LOGIC;
  signal \rd_ptr_reg_n_0_[2]\ : STD_LOGIC;
  signal \rd_ptr_reg_n_0_[3]\ : STD_LOGIC;
  signal rd_ptr_timing : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal wr_en : STD_LOGIC;
  attribute MAX_FANOUT : string;
  attribute MAX_FANOUT of wr_en : signal is "50";
  attribute RTL_MAX_FANOUT : string;
  attribute RTL_MAX_FANOUT of wr_en : signal is "found";
  signal wr_ptr : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \wr_ptr0__0\ : STD_LOGIC;
  signal wr_ptr_timing : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal NLW_mem_reg_0_15_0_5_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_15_12_17_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_15_18_23_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_15_24_29_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_15_30_35_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_15_36_41_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_15_42_47_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_15_48_53_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_15_54_59_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_15_60_65_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_15_66_71_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_15_6_11_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_15_72_77_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  attribute METHODOLOGY_DRC_VIOS : string;
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_15_0_5 : label is "";
  attribute RTL_RAM_BITS : integer;
  attribute RTL_RAM_BITS of mem_reg_0_15_0_5 : label is 720;
  attribute RTL_RAM_NAME : string;
  attribute RTL_RAM_NAME of mem_reg_0_15_0_5 : label is "ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem";
  attribute ram_addr_begin : integer;
  attribute ram_addr_begin of mem_reg_0_15_0_5 : label is 0;
  attribute ram_addr_end : integer;
  attribute ram_addr_end of mem_reg_0_15_0_5 : label is 8;
  attribute ram_offset : integer;
  attribute ram_offset of mem_reg_0_15_0_5 : label is 0;
  attribute ram_slice_begin : integer;
  attribute ram_slice_begin of mem_reg_0_15_0_5 : label is 0;
  attribute ram_slice_end : integer;
  attribute ram_slice_end of mem_reg_0_15_0_5 : label is 5;
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_15_12_17 : label is "";
  attribute RTL_RAM_BITS of mem_reg_0_15_12_17 : label is 720;
  attribute RTL_RAM_NAME of mem_reg_0_15_12_17 : label is "ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem";
  attribute ram_addr_begin of mem_reg_0_15_12_17 : label is 0;
  attribute ram_addr_end of mem_reg_0_15_12_17 : label is 8;
  attribute ram_offset of mem_reg_0_15_12_17 : label is 0;
  attribute ram_slice_begin of mem_reg_0_15_12_17 : label is 12;
  attribute ram_slice_end of mem_reg_0_15_12_17 : label is 17;
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_15_18_23 : label is "";
  attribute RTL_RAM_BITS of mem_reg_0_15_18_23 : label is 720;
  attribute RTL_RAM_NAME of mem_reg_0_15_18_23 : label is "ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem";
  attribute ram_addr_begin of mem_reg_0_15_18_23 : label is 0;
  attribute ram_addr_end of mem_reg_0_15_18_23 : label is 8;
  attribute ram_offset of mem_reg_0_15_18_23 : label is 0;
  attribute ram_slice_begin of mem_reg_0_15_18_23 : label is 18;
  attribute ram_slice_end of mem_reg_0_15_18_23 : label is 23;
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_15_24_29 : label is "";
  attribute RTL_RAM_BITS of mem_reg_0_15_24_29 : label is 720;
  attribute RTL_RAM_NAME of mem_reg_0_15_24_29 : label is "ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem";
  attribute ram_addr_begin of mem_reg_0_15_24_29 : label is 0;
  attribute ram_addr_end of mem_reg_0_15_24_29 : label is 8;
  attribute ram_offset of mem_reg_0_15_24_29 : label is 0;
  attribute ram_slice_begin of mem_reg_0_15_24_29 : label is 24;
  attribute ram_slice_end of mem_reg_0_15_24_29 : label is 29;
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_15_30_35 : label is "";
  attribute RTL_RAM_BITS of mem_reg_0_15_30_35 : label is 720;
  attribute RTL_RAM_NAME of mem_reg_0_15_30_35 : label is "ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem";
  attribute ram_addr_begin of mem_reg_0_15_30_35 : label is 0;
  attribute ram_addr_end of mem_reg_0_15_30_35 : label is 8;
  attribute ram_offset of mem_reg_0_15_30_35 : label is 0;
  attribute ram_slice_begin of mem_reg_0_15_30_35 : label is 30;
  attribute ram_slice_end of mem_reg_0_15_30_35 : label is 35;
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_15_36_41 : label is "";
  attribute RTL_RAM_BITS of mem_reg_0_15_36_41 : label is 720;
  attribute RTL_RAM_NAME of mem_reg_0_15_36_41 : label is "ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem";
  attribute ram_addr_begin of mem_reg_0_15_36_41 : label is 0;
  attribute ram_addr_end of mem_reg_0_15_36_41 : label is 8;
  attribute ram_offset of mem_reg_0_15_36_41 : label is 0;
  attribute ram_slice_begin of mem_reg_0_15_36_41 : label is 36;
  attribute ram_slice_end of mem_reg_0_15_36_41 : label is 41;
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_15_42_47 : label is "";
  attribute RTL_RAM_BITS of mem_reg_0_15_42_47 : label is 720;
  attribute RTL_RAM_NAME of mem_reg_0_15_42_47 : label is "ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem";
  attribute ram_addr_begin of mem_reg_0_15_42_47 : label is 0;
  attribute ram_addr_end of mem_reg_0_15_42_47 : label is 8;
  attribute ram_offset of mem_reg_0_15_42_47 : label is 0;
  attribute ram_slice_begin of mem_reg_0_15_42_47 : label is 42;
  attribute ram_slice_end of mem_reg_0_15_42_47 : label is 47;
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_15_48_53 : label is "";
  attribute RTL_RAM_BITS of mem_reg_0_15_48_53 : label is 720;
  attribute RTL_RAM_NAME of mem_reg_0_15_48_53 : label is "ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem";
  attribute ram_addr_begin of mem_reg_0_15_48_53 : label is 0;
  attribute ram_addr_end of mem_reg_0_15_48_53 : label is 8;
  attribute ram_offset of mem_reg_0_15_48_53 : label is 0;
  attribute ram_slice_begin of mem_reg_0_15_48_53 : label is 48;
  attribute ram_slice_end of mem_reg_0_15_48_53 : label is 53;
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_15_54_59 : label is "";
  attribute RTL_RAM_BITS of mem_reg_0_15_54_59 : label is 720;
  attribute RTL_RAM_NAME of mem_reg_0_15_54_59 : label is "ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem";
  attribute ram_addr_begin of mem_reg_0_15_54_59 : label is 0;
  attribute ram_addr_end of mem_reg_0_15_54_59 : label is 8;
  attribute ram_offset of mem_reg_0_15_54_59 : label is 0;
  attribute ram_slice_begin of mem_reg_0_15_54_59 : label is 54;
  attribute ram_slice_end of mem_reg_0_15_54_59 : label is 59;
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_15_60_65 : label is "";
  attribute RTL_RAM_BITS of mem_reg_0_15_60_65 : label is 720;
  attribute RTL_RAM_NAME of mem_reg_0_15_60_65 : label is "ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem";
  attribute ram_addr_begin of mem_reg_0_15_60_65 : label is 0;
  attribute ram_addr_end of mem_reg_0_15_60_65 : label is 8;
  attribute ram_offset of mem_reg_0_15_60_65 : label is 0;
  attribute ram_slice_begin of mem_reg_0_15_60_65 : label is 60;
  attribute ram_slice_end of mem_reg_0_15_60_65 : label is 65;
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_15_66_71 : label is "";
  attribute RTL_RAM_BITS of mem_reg_0_15_66_71 : label is 720;
  attribute RTL_RAM_NAME of mem_reg_0_15_66_71 : label is "ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem";
  attribute ram_addr_begin of mem_reg_0_15_66_71 : label is 0;
  attribute ram_addr_end of mem_reg_0_15_66_71 : label is 8;
  attribute ram_offset of mem_reg_0_15_66_71 : label is 0;
  attribute ram_slice_begin of mem_reg_0_15_66_71 : label is 66;
  attribute ram_slice_end of mem_reg_0_15_66_71 : label is 71;
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_15_6_11 : label is "";
  attribute RTL_RAM_BITS of mem_reg_0_15_6_11 : label is 720;
  attribute RTL_RAM_NAME of mem_reg_0_15_6_11 : label is "ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem";
  attribute ram_addr_begin of mem_reg_0_15_6_11 : label is 0;
  attribute ram_addr_end of mem_reg_0_15_6_11 : label is 8;
  attribute ram_offset of mem_reg_0_15_6_11 : label is 0;
  attribute ram_slice_begin of mem_reg_0_15_6_11 : label is 6;
  attribute ram_slice_end of mem_reg_0_15_6_11 : label is 11;
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_15_72_77 : label is "";
  attribute RTL_RAM_BITS of mem_reg_0_15_72_77 : label is 720;
  attribute RTL_RAM_NAME of mem_reg_0_15_72_77 : label is "ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem";
  attribute ram_addr_begin of mem_reg_0_15_72_77 : label is 0;
  attribute ram_addr_end of mem_reg_0_15_72_77 : label is 8;
  attribute ram_offset of mem_reg_0_15_72_77 : label is 0;
  attribute ram_slice_begin of mem_reg_0_15_72_77 : label is 72;
  attribute ram_slice_end of mem_reg_0_15_72_77 : label is 77;
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \my_empty[1]_i_1\ : label is "soft_lutpair912";
  attribute SOFT_HLUTNM of \my_empty[6]_i_3__0\ : label is "soft_lutpair911";
  attribute SOFT_HLUTNM of \my_empty[6]_i_4__0\ : label is "soft_lutpair911";
  attribute syn_maxfan : string;
  attribute syn_maxfan of \my_empty_reg[1]\ : label is "3";
  attribute syn_maxfan of \my_empty_reg[6]\ : label is "3";
  attribute SOFT_HLUTNM of \my_full[3]_i_3__0\ : label is "soft_lutpair910";
  attribute SOFT_HLUTNM of \my_full[3]_i_4__0\ : label is "soft_lutpair910";
  attribute syn_maxfan of \my_full_reg[3]\ : label is "3";
  attribute SOFT_HLUTNM of \out_fifo_i_10__1\ : label is "soft_lutpair927";
  attribute SOFT_HLUTNM of \out_fifo_i_11__1\ : label is "soft_lutpair915";
  attribute SOFT_HLUTNM of \out_fifo_i_12__1\ : label is "soft_lutpair928";
  attribute SOFT_HLUTNM of \out_fifo_i_13__1\ : label is "soft_lutpair923";
  attribute SOFT_HLUTNM of out_fifo_i_18 : label is "soft_lutpair925";
  attribute SOFT_HLUTNM of out_fifo_i_19 : label is "soft_lutpair928";
  attribute SOFT_HLUTNM of \out_fifo_i_1__9\ : label is "soft_lutpair912";
  attribute SOFT_HLUTNM of \out_fifo_i_20__0\ : label is "soft_lutpair929";
  attribute SOFT_HLUTNM of \out_fifo_i_21__0\ : label is "soft_lutpair925";
  attribute SOFT_HLUTNM of out_fifo_i_22 : label is "soft_lutpair921";
  attribute SOFT_HLUTNM of \out_fifo_i_23__9\ : label is "soft_lutpair913";
  attribute SOFT_HLUTNM of \out_fifo_i_24__0\ : label is "soft_lutpair916";
  attribute SOFT_HLUTNM of \out_fifo_i_25__9\ : label is "soft_lutpair915";
  attribute SOFT_HLUTNM of \out_fifo_i_26__0\ : label is "soft_lutpair932";
  attribute SOFT_HLUTNM of out_fifo_i_27 : label is "soft_lutpair927";
  attribute SOFT_HLUTNM of out_fifo_i_28 : label is "soft_lutpair930";
  attribute SOFT_HLUTNM of out_fifo_i_29 : label is "soft_lutpair924";
  attribute SOFT_HLUTNM of \out_fifo_i_2__7\ : label is "soft_lutpair929";
  attribute SOFT_HLUTNM of \out_fifo_i_34__1\ : label is "soft_lutpair937";
  attribute SOFT_HLUTNM of \out_fifo_i_35__0\ : label is "soft_lutpair923";
  attribute SOFT_HLUTNM of \out_fifo_i_36__0\ : label is "soft_lutpair937";
  attribute SOFT_HLUTNM of \out_fifo_i_37__0\ : label is "soft_lutpair933";
  attribute SOFT_HLUTNM of \out_fifo_i_3__7\ : label is "soft_lutpair918";
  attribute SOFT_HLUTNM of out_fifo_i_46 : label is "soft_lutpair921";
  attribute SOFT_HLUTNM of \out_fifo_i_47__9\ : label is "soft_lutpair918";
  attribute SOFT_HLUTNM of \out_fifo_i_48__0\ : label is "soft_lutpair916";
  attribute SOFT_HLUTNM of \out_fifo_i_49__9\ : label is "soft_lutpair919";
  attribute SOFT_HLUTNM of \out_fifo_i_4__7\ : label is "soft_lutpair930";
  attribute SOFT_HLUTNM of out_fifo_i_58 : label is "soft_lutpair933";
  attribute SOFT_HLUTNM of out_fifo_i_59 : label is "soft_lutpair931";
  attribute SOFT_HLUTNM of \out_fifo_i_5__7\ : label is "soft_lutpair924";
  attribute SOFT_HLUTNM of out_fifo_i_60 : label is "soft_lutpair935";
  attribute SOFT_HLUTNM of out_fifo_i_61 : label is "soft_lutpair932";
  attribute SOFT_HLUTNM of \out_fifo_i_66__1\ : label is "soft_lutpair936";
  attribute SOFT_HLUTNM of \out_fifo_i_67__1\ : label is "soft_lutpair934";
  attribute SOFT_HLUTNM of \out_fifo_i_68__1\ : label is "soft_lutpair934";
  attribute SOFT_HLUTNM of \out_fifo_i_69__1\ : label is "soft_lutpair926";
  attribute SOFT_HLUTNM of \out_fifo_i_6__7\ : label is "soft_lutpair926";
  attribute SOFT_HLUTNM of out_fifo_i_74 : label is "soft_lutpair936";
  attribute SOFT_HLUTNM of out_fifo_i_75 : label is "soft_lutpair935";
  attribute SOFT_HLUTNM of \out_fifo_i_7__7\ : label is "soft_lutpair913";
  attribute SOFT_HLUTNM of \out_fifo_i_8__7\ : label is "soft_lutpair931";
  attribute SOFT_HLUTNM of \out_fifo_i_9__7\ : label is "soft_lutpair919";
  attribute SOFT_HLUTNM of \rd_ptr[0]_i_2__0\ : label is "soft_lutpair920";
  attribute SOFT_HLUTNM of \rd_ptr[1]_i_1__0\ : label is "soft_lutpair920";
  attribute SOFT_HLUTNM of \rd_ptr[2]_i_1__0\ : label is "soft_lutpair917";
  attribute SOFT_HLUTNM of \rd_ptr[3]_i_1__0\ : label is "soft_lutpair917";
  attribute syn_maxfan of \rd_ptr_reg[0]\ : label is "10";
  attribute syn_maxfan of \rd_ptr_reg[1]\ : label is "10";
  attribute syn_maxfan of \rd_ptr_reg[2]\ : label is "10";
  attribute syn_maxfan of \rd_ptr_reg[3]\ : label is "10";
  attribute KEEP : string;
  attribute KEEP of \rd_ptr_timing_reg[0]\ : label is "yes";
  attribute KEEP of \rd_ptr_timing_reg[1]\ : label is "yes";
  attribute KEEP of \rd_ptr_timing_reg[2]\ : label is "yes";
  attribute KEEP of \rd_ptr_timing_reg[3]\ : label is "yes";
  attribute SOFT_HLUTNM of \wr_ptr[0]_i_1__17\ : label is "soft_lutpair922";
  attribute SOFT_HLUTNM of \wr_ptr[1]_i_1__17\ : label is "soft_lutpair922";
  attribute SOFT_HLUTNM of \wr_ptr[2]_i_1__9\ : label is "soft_lutpair914";
  attribute SOFT_HLUTNM of \wr_ptr[3]_i_1__9\ : label is "soft_lutpair914";
  attribute syn_maxfan of \wr_ptr_reg[0]\ : label is "10";
  attribute syn_maxfan of \wr_ptr_reg[1]\ : label is "10";
  attribute syn_maxfan of \wr_ptr_reg[2]\ : label is "10";
  attribute syn_maxfan of \wr_ptr_reg[3]\ : label is "10";
  attribute KEEP of \wr_ptr_timing_reg[0]\ : label is "yes";
  attribute KEEP of \wr_ptr_timing_reg[1]\ : label is "yes";
  attribute KEEP of \wr_ptr_timing_reg[2]\ : label is "yes";
  attribute KEEP of \wr_ptr_timing_reg[3]\ : label is "yes";
begin
  \my_empty_reg[1]_0\ <= \^my_empty_reg[1]_0\;
mem_reg_0_15_0_5: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4) => '0',
      ADDRA(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRA(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRA(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRA(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRB(4) => '0',
      ADDRB(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRB(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRB(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRB(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRC(4) => '0',
      ADDRC(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRC(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRC(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRC(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRD(4) => '0',
      ADDRD(3 downto 0) => wr_ptr(3 downto 0),
      DIA(1 downto 0) => B"00",
      DIB(1 downto 0) => B"00",
      DIC(1 downto 0) => B"00",
      DID(1 downto 0) => B"00",
      DOA(1) => mem_reg_0_15_0_5_n_0,
      DOA(0) => mem_reg_0_15_0_5_n_1,
      DOB(1) => mem_reg_0_15_0_5_n_2,
      DOB(0) => mem_reg_0_15_0_5_n_3,
      DOC(1) => mem_reg_0_15_0_5_n_4,
      DOC(0) => mem_reg_0_15_0_5_n_5,
      DOD(1 downto 0) => NLW_mem_reg_0_15_0_5_DOD_UNCONNECTED(1 downto 0),
      WCLK => \wr_ptr_timing_reg[3]_0\,
      WE => wr_en
    );
mem_reg_0_15_12_17: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4) => '0',
      ADDRA(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRA(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRA(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRA(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRB(4) => '0',
      ADDRB(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRB(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRB(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRB(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRC(4) => '0',
      ADDRC(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRC(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRC(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRC(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRD(4) => '0',
      ADDRD(3 downto 0) => wr_ptr(3 downto 0),
      DIA(1 downto 0) => B"00",
      DIB(1 downto 0) => B"00",
      DIC(1) => d_in(15),
      DIC(0) => d_in(4),
      DID(1 downto 0) => B"00",
      DOA(1) => mem_reg_0_15_12_17_n_0,
      DOA(0) => mem_reg_0_15_12_17_n_1,
      DOB(1) => mem_reg_0_15_12_17_n_2,
      DOB(0) => mem_reg_0_15_12_17_n_3,
      DOC(1) => mem_reg_0_15_12_17_n_4,
      DOC(0) => mem_reg_0_15_12_17_n_5,
      DOD(1 downto 0) => NLW_mem_reg_0_15_12_17_DOD_UNCONNECTED(1 downto 0),
      WCLK => \wr_ptr_timing_reg[3]_0\,
      WE => wr_en
    );
mem_reg_0_15_18_23: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4) => '0',
      ADDRA(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRA(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRA(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRA(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRB(4) => '0',
      ADDRB(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRB(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRB(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRB(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRC(4) => '0',
      ADDRC(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRC(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRC(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRC(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRD(4) => '0',
      ADDRD(3 downto 0) => wr_ptr(3 downto 0),
      DIA(1) => d_in(17),
      DIA(0) => d_in(5),
      DIB(1 downto 0) => B"00",
      DIC(1 downto 0) => B"00",
      DID(1 downto 0) => B"00",
      DOA(1) => mem_reg_0_15_18_23_n_0,
      DOA(0) => mem_reg_0_15_18_23_n_1,
      DOB(1) => mem_reg_0_15_18_23_n_2,
      DOB(0) => mem_reg_0_15_18_23_n_3,
      DOC(1) => mem_reg_0_15_18_23_n_4,
      DOC(0) => mem_reg_0_15_18_23_n_5,
      DOD(1 downto 0) => NLW_mem_reg_0_15_18_23_DOD_UNCONNECTED(1 downto 0),
      WCLK => \wr_ptr_timing_reg[3]_0\,
      WE => wr_en
    );
mem_reg_0_15_24_29: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4) => '0',
      ADDRA(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRA(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRA(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRA(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRB(4) => '0',
      ADDRB(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRB(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRB(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRB(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRC(4) => '0',
      ADDRC(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRC(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRC(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRC(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRD(4) => '0',
      ADDRD(3 downto 0) => wr_ptr(3 downto 0),
      DIA(1 downto 0) => d_in(7 downto 6),
      DIB(1 downto 0) => d_in(9 downto 8),
      DIC(1 downto 0) => B"00",
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => \rd_ptr_reg[3]_0\(5 downto 4),
      DOB(1 downto 0) => \rd_ptr_reg[3]_0\(7 downto 6),
      DOC(1) => mem_reg_0_15_24_29_n_4,
      DOC(0) => mem_reg_0_15_24_29_n_5,
      DOD(1 downto 0) => NLW_mem_reg_0_15_24_29_DOD_UNCONNECTED(1 downto 0),
      WCLK => \wr_ptr_timing_reg[3]_0\,
      WE => wr_en
    );
mem_reg_0_15_30_35: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4) => '0',
      ADDRA(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRA(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRA(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRA(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRB(4) => '0',
      ADDRB(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRB(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRB(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRB(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRC(4) => '0',
      ADDRC(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRC(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRC(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRC(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRD(4) => '0',
      ADDRD(3 downto 0) => wr_ptr(3 downto 0),
      DIA(1 downto 0) => B"00",
      DIB(1 downto 0) => d_in(11 downto 10),
      DIC(1 downto 0) => d_in(13 downto 12),
      DID(1 downto 0) => B"00",
      DOA(1) => mem_reg_0_15_30_35_n_0,
      DOA(0) => mem_reg_0_15_30_35_n_1,
      DOB(1 downto 0) => \rd_ptr_reg[3]_0\(9 downto 8),
      DOC(1 downto 0) => \rd_ptr_reg[3]_0\(11 downto 10),
      DOD(1 downto 0) => NLW_mem_reg_0_15_30_35_DOD_UNCONNECTED(1 downto 0),
      WCLK => \wr_ptr_timing_reg[3]_0\,
      WE => wr_en
    );
mem_reg_0_15_36_41: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4) => '0',
      ADDRA(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRA(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRA(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRA(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRB(4) => '0',
      ADDRB(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRB(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRB(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRB(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRC(4) => '0',
      ADDRC(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRC(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRC(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRC(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRD(4) => '0',
      ADDRD(3 downto 0) => wr_ptr(3 downto 0),
      DIA(1 downto 0) => B"00",
      DIB(1 downto 0) => B"00",
      DIC(1 downto 0) => d_in(15 downto 14),
      DID(1 downto 0) => B"00",
      DOA(1) => mem_reg_0_15_36_41_n_0,
      DOA(0) => mem_reg_0_15_36_41_n_1,
      DOB(1) => mem_reg_0_15_36_41_n_2,
      DOB(0) => mem_reg_0_15_36_41_n_3,
      DOC(1) => mem_reg_0_15_36_41_n_4,
      DOC(0) => mem_reg_0_15_36_41_n_5,
      DOD(1 downto 0) => NLW_mem_reg_0_15_36_41_DOD_UNCONNECTED(1 downto 0),
      WCLK => \wr_ptr_timing_reg[3]_0\,
      WE => wr_en
    );
mem_reg_0_15_42_47: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4) => '0',
      ADDRA(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRA(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRA(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRA(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRB(4) => '0',
      ADDRB(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRB(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRB(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRB(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRC(4) => '0',
      ADDRC(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRC(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRC(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRC(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRD(4) => '0',
      ADDRD(3 downto 0) => wr_ptr(3 downto 0),
      DIA(1 downto 0) => d_in(17 downto 16),
      DIB(1 downto 0) => d_in(19 downto 18),
      DIC(1 downto 0) => d_in(21 downto 20),
      DID(1 downto 0) => B"00",
      DOA(1) => mem_reg_0_15_42_47_n_0,
      DOA(0) => mem_reg_0_15_42_47_n_1,
      DOB(1 downto 0) => \rd_ptr_reg[3]_0\(13 downto 12),
      DOC(1 downto 0) => \rd_ptr_reg[3]_0\(15 downto 14),
      DOD(1 downto 0) => NLW_mem_reg_0_15_42_47_DOD_UNCONNECTED(1 downto 0),
      WCLK => \wr_ptr_timing_reg[3]_0\,
      WE => wr_en
    );
mem_reg_0_15_48_53: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4) => '0',
      ADDRA(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRA(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRA(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRA(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRB(4) => '0',
      ADDRB(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRB(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRB(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRB(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRC(4) => '0',
      ADDRC(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRC(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRC(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRC(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRD(4) => '0',
      ADDRD(3 downto 0) => wr_ptr(3 downto 0),
      DIA(1 downto 0) => d_in(23 downto 22),
      DIB(1 downto 0) => d_in(25 downto 24),
      DIC(1 downto 0) => d_in(27 downto 26),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => \rd_ptr_reg[3]_0\(17 downto 16),
      DOB(1 downto 0) => \rd_ptr_reg[3]_0\(19 downto 18),
      DOC(1 downto 0) => \rd_ptr_reg[3]_0\(21 downto 20),
      DOD(1 downto 0) => NLW_mem_reg_0_15_48_53_DOD_UNCONNECTED(1 downto 0),
      WCLK => \wr_ptr_timing_reg[3]_0\,
      WE => wr_en
    );
mem_reg_0_15_54_59: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4) => '0',
      ADDRA(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRA(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRA(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRA(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRB(4) => '0',
      ADDRB(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRB(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRB(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRB(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRC(4) => '0',
      ADDRC(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRC(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRC(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRC(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRD(4) => '0',
      ADDRD(3 downto 0) => wr_ptr(3 downto 0),
      DIA(1 downto 0) => d_in(29 downto 28),
      DIB(1 downto 0) => d_in(31 downto 30),
      DIC(1 downto 0) => d_in(33 downto 32),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => \rd_ptr_reg[3]_0\(23 downto 22),
      DOB(1 downto 0) => \rd_ptr_reg[3]_0\(25 downto 24),
      DOC(1 downto 0) => \rd_ptr_reg[3]_0\(27 downto 26),
      DOD(1 downto 0) => NLW_mem_reg_0_15_54_59_DOD_UNCONNECTED(1 downto 0),
      WCLK => \wr_ptr_timing_reg[3]_0\,
      WE => wr_en
    );
mem_reg_0_15_60_65: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4) => '0',
      ADDRA(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRA(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRA(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRA(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRB(4) => '0',
      ADDRB(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRB(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRB(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRB(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRC(4) => '0',
      ADDRC(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRC(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRC(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRC(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRD(4) => '0',
      ADDRD(3 downto 0) => wr_ptr(3 downto 0),
      DIA(1 downto 0) => B"00",
      DIB(1 downto 0) => B"00",
      DIC(1 downto 0) => d_in(35 downto 34),
      DID(1 downto 0) => B"00",
      DOA(1) => mem_reg_0_15_60_65_n_0,
      DOA(0) => mem_reg_0_15_60_65_n_1,
      DOB(1) => mem_reg_0_15_60_65_n_2,
      DOB(0) => mem_reg_0_15_60_65_n_3,
      DOC(1 downto 0) => \rd_ptr_reg[3]_0\(29 downto 28),
      DOD(1 downto 0) => NLW_mem_reg_0_15_60_65_DOD_UNCONNECTED(1 downto 0),
      WCLK => \wr_ptr_timing_reg[3]_0\,
      WE => wr_en
    );
mem_reg_0_15_66_71: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4) => '0',
      ADDRA(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRA(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRA(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRA(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRB(4) => '0',
      ADDRB(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRB(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRB(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRB(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRC(4) => '0',
      ADDRC(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRC(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRC(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRC(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRD(4) => '0',
      ADDRD(3 downto 0) => wr_ptr(3 downto 0),
      DIA(1 downto 0) => d_in(37 downto 36),
      DIB(1 downto 0) => B"00",
      DIC(1 downto 0) => B"00",
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => \rd_ptr_reg[3]_0\(31 downto 30),
      DOB(1) => mem_reg_0_15_66_71_n_2,
      DOB(0) => mem_reg_0_15_66_71_n_3,
      DOC(1) => mem_reg_0_15_66_71_n_4,
      DOC(0) => mem_reg_0_15_66_71_n_5,
      DOD(1 downto 0) => NLW_mem_reg_0_15_66_71_DOD_UNCONNECTED(1 downto 0),
      WCLK => \wr_ptr_timing_reg[3]_0\,
      WE => wr_en
    );
mem_reg_0_15_6_11: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4) => '0',
      ADDRA(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRA(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRA(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRA(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRB(4) => '0',
      ADDRB(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRB(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRB(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRB(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRC(4) => '0',
      ADDRC(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRC(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRC(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRC(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRD(4) => '0',
      ADDRD(3 downto 0) => wr_ptr(3 downto 0),
      DIA(1 downto 0) => B"00",
      DIB(1 downto 0) => d_in(1 downto 0),
      DIC(1 downto 0) => d_in(3 downto 2),
      DID(1 downto 0) => B"00",
      DOA(1) => mem_reg_0_15_6_11_n_0,
      DOA(0) => mem_reg_0_15_6_11_n_1,
      DOB(1 downto 0) => \rd_ptr_reg[3]_0\(1 downto 0),
      DOC(1 downto 0) => \rd_ptr_reg[3]_0\(3 downto 2),
      DOD(1 downto 0) => NLW_mem_reg_0_15_6_11_DOD_UNCONNECTED(1 downto 0),
      WCLK => \wr_ptr_timing_reg[3]_0\,
      WE => wr_en
    );
mem_reg_0_15_72_77: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4) => '0',
      ADDRA(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRA(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRA(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRA(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRB(4) => '0',
      ADDRB(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRB(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRB(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRB(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRC(4) => '0',
      ADDRC(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRC(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRC(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRC(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRD(4) => '0',
      ADDRD(3 downto 0) => wr_ptr(3 downto 0),
      DIA(1 downto 0) => d_in(39 downto 38),
      DIB(1 downto 0) => d_in(41 downto 40),
      DIC(1 downto 0) => B"00",
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => \rd_ptr_reg[3]_0\(33 downto 32),
      DOB(1 downto 0) => \rd_ptr_reg[3]_0\(35 downto 34),
      DOC(1) => mem_reg_0_15_72_77_n_4,
      DOC(0) => mem_reg_0_15_72_77_n_5,
      DOD(1 downto 0) => NLW_mem_reg_0_15_72_77_DOD_UNCONNECTED(1 downto 0),
      WCLK => \wr_ptr_timing_reg[3]_0\,
      WE => wr_en
    );
\my_empty[1]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"C0CCCCCE"
    )
        port map (
      I0 => \my_empty[6]_i_2__0_n_0\,
      I1 => \^my_empty_reg[1]_0\,
      I2 => \my_full_reg_n_0_[3]\,
      I3 => phy_cmd_wr_en,
      I4 => \rd_ptr_reg[3]_1\,
      O => \my_empty[1]_i_1_n_0\
    );
\my_empty[6]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"C0CCCCCE"
    )
        port map (
      I0 => \my_empty[6]_i_2__0_n_0\,
      I1 => \my_empty_reg_n_0_[6]\,
      I2 => \my_full_reg_n_0_[3]\,
      I3 => phy_cmd_wr_en,
      I4 => \rd_ptr_reg[3]_1\,
      O => \my_empty[6]_i_1_n_0\
    );
\my_empty[6]_i_2__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"4A400D08"
    )
        port map (
      I0 => wr_ptr_timing(2),
      I1 => \my_empty[6]_i_3__0_n_0\,
      I2 => wr_ptr_timing(3),
      I3 => \my_empty[6]_i_4__0_n_0\,
      I4 => \rd_ptr_reg_n_0_[2]\,
      O => \my_empty[6]_i_2__0_n_0\
    );
\my_empty[6]_i_3__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000040"
    )
        port map (
      I0 => wr_ptr_timing(1),
      I1 => \rd_ptr_reg_n_0_[0]\,
      I2 => \rd_ptr_reg_n_0_[1]\,
      I3 => \rd_ptr_reg_n_0_[3]\,
      I4 => wr_ptr_timing(0),
      O => \my_empty[6]_i_3__0_n_0\
    );
\my_empty[6]_i_4__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"84210842"
    )
        port map (
      I0 => wr_ptr_timing(0),
      I1 => wr_ptr_timing(1),
      I2 => \rd_ptr_reg_n_0_[0]\,
      I3 => \rd_ptr_reg_n_0_[1]\,
      I4 => \rd_ptr_reg_n_0_[3]\,
      O => \my_empty[6]_i_4__0_n_0\
    );
\my_empty_reg[1]\: unisim.vcomponents.FDSE
     port map (
      C => \wr_ptr_timing_reg[3]_0\,
      CE => '1',
      D => \my_empty[1]_i_1_n_0\,
      Q => \^my_empty_reg[1]_0\,
      S => SR(0)
    );
\my_empty_reg[6]\: unisim.vcomponents.FDSE
     port map (
      C => \wr_ptr_timing_reg[3]_0\,
      CE => '1',
      D => \my_empty[6]_i_1_n_0\,
      Q => \my_empty_reg_n_0_[6]\,
      S => SR(0)
    );
\my_full[3]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000FFFC0080"
    )
        port map (
      I0 => \my_full[3]_i_2__0_n_0\,
      I1 => phy_cmd_wr_en,
      I2 => \rd_ptr_reg[3]_1\,
      I3 => \my_empty_reg_n_0_[6]\,
      I4 => \my_full_reg_n_0_[3]\,
      I5 => SR(0),
      O => \my_full[3]_i_1__0_n_0\
    );
\my_full[3]_i_2__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"4A400D08"
    )
        port map (
      I0 => rd_ptr_timing(2),
      I1 => \my_full[3]_i_3__0_n_0\,
      I2 => rd_ptr_timing(3),
      I3 => \my_full[3]_i_4__0_n_0\,
      I4 => wr_ptr(2),
      O => \my_full[3]_i_2__0_n_0\
    );
\my_full[3]_i_3__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000040"
    )
        port map (
      I0 => rd_ptr_timing(1),
      I1 => wr_ptr(0),
      I2 => wr_ptr(1),
      I3 => wr_ptr(3),
      I4 => rd_ptr_timing(0),
      O => \my_full[3]_i_3__0_n_0\
    );
\my_full[3]_i_4__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"84210842"
    )
        port map (
      I0 => rd_ptr_timing(0),
      I1 => rd_ptr_timing(1),
      I2 => wr_ptr(0),
      I3 => wr_ptr(1),
      I4 => wr_ptr(3),
      O => \my_full[3]_i_4__0_n_0\
    );
\my_full_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_ptr_timing_reg[3]_0\,
      CE => '1',
      D => \my_full[3]_i_1__0_n_0\,
      Q => \my_full_reg_n_0_[3]\,
      R => '0'
    );
\out_fifo_i_10__1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => mem_reg_0_15_12_17_n_2,
      I1 => \^my_empty_reg[1]_0\,
      O => D1(3)
    );
\out_fifo_i_11__1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => mem_reg_0_15_12_17_n_3,
      I1 => \^my_empty_reg[1]_0\,
      O => D1(2)
    );
\out_fifo_i_12__1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => mem_reg_0_15_12_17_n_0,
      I1 => \^my_empty_reg[1]_0\,
      O => D1(1)
    );
\out_fifo_i_13__1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => mem_reg_0_15_12_17_n_1,
      I1 => \^my_empty_reg[1]_0\,
      O => D1(0)
    );
out_fifo_i_18: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => mem_reg_0_15_18_23_n_4,
      I1 => \^my_empty_reg[1]_0\,
      O => D2(7)
    );
out_fifo_i_19: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => mem_reg_0_15_18_23_n_5,
      I1 => \^my_empty_reg[1]_0\,
      O => D2(6)
    );
\out_fifo_i_1__9\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"0D"
    )
        port map (
      I0 => \^my_empty_reg[1]_0\,
      I1 => phy_cmd_wr_en,
      I2 => \rd_ptr_reg[3]_1\,
      O => \my_empty_reg[1]_1\
    );
\out_fifo_i_20__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => mem_reg_0_15_18_23_n_2,
      I1 => \^my_empty_reg[1]_0\,
      O => D2(5)
    );
\out_fifo_i_21__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => mem_reg_0_15_18_23_n_3,
      I1 => \^my_empty_reg[1]_0\,
      O => D2(4)
    );
out_fifo_i_22: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => out_fifo_1,
      I1 => mem_reg_0_15_18_23_n_0,
      I2 => \^my_empty_reg[1]_0\,
      O => D2(3)
    );
\out_fifo_i_23__9\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"88F0"
    )
        port map (
      I0 => mc_address(3),
      I1 => out_fifo_0,
      I2 => mem_reg_0_15_18_23_n_1,
      I3 => \^my_empty_reg[1]_0\,
      O => D2(2)
    );
\out_fifo_i_24__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"88F0"
    )
        port map (
      I0 => out_fifo,
      I1 => mc_cas_n(0),
      I2 => mem_reg_0_15_12_17_n_4,
      I3 => \^my_empty_reg[1]_0\,
      O => D2(1)
    );
\out_fifo_i_25__9\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"88F0"
    )
        port map (
      I0 => mc_address(1),
      I1 => out_fifo_0,
      I2 => mem_reg_0_15_12_17_n_5,
      I3 => \^my_empty_reg[1]_0\,
      O => D2(0)
    );
\out_fifo_i_26__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => mem_reg_0_15_30_35_n_0,
      I1 => \^my_empty_reg[1]_0\,
      O => D3(3)
    );
out_fifo_i_27: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => mem_reg_0_15_30_35_n_1,
      I1 => \^my_empty_reg[1]_0\,
      O => D3(2)
    );
out_fifo_i_28: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => mem_reg_0_15_24_29_n_4,
      I1 => \^my_empty_reg[1]_0\,
      O => D3(1)
    );
out_fifo_i_29: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => mem_reg_0_15_24_29_n_5,
      I1 => \^my_empty_reg[1]_0\,
      O => D3(0)
    );
\out_fifo_i_2__7\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => mem_reg_0_15_6_11_n_0,
      I1 => \^my_empty_reg[1]_0\,
      O => D0(7)
    );
\out_fifo_i_34__1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => mem_reg_0_15_36_41_n_2,
      I1 => \^my_empty_reg[1]_0\,
      O => D4(3)
    );
\out_fifo_i_35__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => mem_reg_0_15_36_41_n_3,
      I1 => \^my_empty_reg[1]_0\,
      O => D4(2)
    );
\out_fifo_i_36__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => mem_reg_0_15_36_41_n_0,
      I1 => \^my_empty_reg[1]_0\,
      O => D4(1)
    );
\out_fifo_i_37__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => mem_reg_0_15_36_41_n_1,
      I1 => \^my_empty_reg[1]_0\,
      O => D4(0)
    );
\out_fifo_i_3__7\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => mem_reg_0_15_6_11_n_1,
      I1 => \^my_empty_reg[1]_0\,
      O => D0(6)
    );
out_fifo_i_46: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => out_fifo_1,
      I1 => mem_reg_0_15_42_47_n_0,
      I2 => \^my_empty_reg[1]_0\,
      O => D5(3)
    );
\out_fifo_i_47__9\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"88F0"
    )
        port map (
      I0 => mc_address(2),
      I1 => out_fifo_0,
      I2 => mem_reg_0_15_42_47_n_1,
      I3 => \^my_empty_reg[1]_0\,
      O => D5(2)
    );
\out_fifo_i_48__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"88F0"
    )
        port map (
      I0 => out_fifo,
      I1 => mc_cas_n(0),
      I2 => mem_reg_0_15_36_41_n_4,
      I3 => \^my_empty_reg[1]_0\,
      O => D5(1)
    );
\out_fifo_i_49__9\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"88F0"
    )
        port map (
      I0 => mc_address(0),
      I1 => out_fifo_0,
      I2 => mem_reg_0_15_36_41_n_5,
      I3 => \^my_empty_reg[1]_0\,
      O => D5(0)
    );
\out_fifo_i_4__7\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => mem_reg_0_15_0_5_n_4,
      I1 => \^my_empty_reg[1]_0\,
      O => D0(5)
    );
out_fifo_i_58: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => mem_reg_0_15_60_65_n_2,
      I1 => \^my_empty_reg[1]_0\,
      O => D7(3)
    );
out_fifo_i_59: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => mem_reg_0_15_60_65_n_3,
      I1 => \^my_empty_reg[1]_0\,
      O => D7(2)
    );
\out_fifo_i_5__7\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => mem_reg_0_15_0_5_n_5,
      I1 => \^my_empty_reg[1]_0\,
      O => D0(4)
    );
out_fifo_i_60: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => mem_reg_0_15_60_65_n_0,
      I1 => \^my_empty_reg[1]_0\,
      O => D7(1)
    );
out_fifo_i_61: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => mem_reg_0_15_60_65_n_1,
      I1 => \^my_empty_reg[1]_0\,
      O => D7(0)
    );
\out_fifo_i_66__1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => mem_reg_0_15_66_71_n_4,
      I1 => \^my_empty_reg[1]_0\,
      O => D8(3)
    );
\out_fifo_i_67__1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => mem_reg_0_15_66_71_n_5,
      I1 => \^my_empty_reg[1]_0\,
      O => D8(2)
    );
\out_fifo_i_68__1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => mem_reg_0_15_66_71_n_2,
      I1 => \^my_empty_reg[1]_0\,
      O => D8(1)
    );
\out_fifo_i_69__1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => mem_reg_0_15_66_71_n_3,
      I1 => \^my_empty_reg[1]_0\,
      O => D8(0)
    );
\out_fifo_i_6__7\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => mem_reg_0_15_0_5_n_2,
      I1 => \^my_empty_reg[1]_0\,
      O => D0(3)
    );
out_fifo_i_74: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => mem_reg_0_15_72_77_n_4,
      I1 => \^my_empty_reg[1]_0\,
      O => D9(1)
    );
out_fifo_i_75: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => mem_reg_0_15_72_77_n_5,
      I1 => \^my_empty_reg[1]_0\,
      O => D9(0)
    );
\out_fifo_i_7__7\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => mem_reg_0_15_0_5_n_3,
      I1 => \^my_empty_reg[1]_0\,
      O => D0(2)
    );
\out_fifo_i_8__7\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => mem_reg_0_15_0_5_n_0,
      I1 => \^my_empty_reg[1]_0\,
      O => D0(1)
    );
\out_fifo_i_9__7\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => mem_reg_0_15_0_5_n_1,
      I1 => \^my_empty_reg[1]_0\,
      O => D0(0)
    );
p_17_out: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2700"
    )
        port map (
      I0 => \rd_ptr_reg[3]_1\,
      I1 => \my_full_reg_n_0_[3]\,
      I2 => \^my_empty_reg[1]_0\,
      I3 => phy_cmd_wr_en,
      O => wr_en
    );
\rd_ptr[0]_i_1__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \rd_ptr_reg[3]_1\,
      I1 => \my_empty_reg_n_0_[6]\,
      O => \rd_ptr[0]_i_1__0_n_0\
    );
\rd_ptr[0]_i_2__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => \rd_ptr_reg_n_0_[3]\,
      I1 => \rd_ptr_reg_n_0_[0]\,
      O => nxt_rd_ptr(0)
    );
\rd_ptr[1]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B4"
    )
        port map (
      I0 => \rd_ptr_reg_n_0_[3]\,
      I1 => \rd_ptr_reg_n_0_[0]\,
      I2 => \rd_ptr_reg_n_0_[1]\,
      O => nxt_rd_ptr(1)
    );
\rd_ptr[2]_i_1__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"AA6A"
    )
        port map (
      I0 => \rd_ptr_reg_n_0_[2]\,
      I1 => \rd_ptr_reg_n_0_[0]\,
      I2 => \rd_ptr_reg_n_0_[1]\,
      I3 => \rd_ptr_reg_n_0_[3]\,
      O => nxt_rd_ptr(2)
    );
\rd_ptr[3]_i_1__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4000"
    )
        port map (
      I0 => \rd_ptr_reg_n_0_[3]\,
      I1 => \rd_ptr_reg_n_0_[1]\,
      I2 => \rd_ptr_reg_n_0_[0]\,
      I3 => \rd_ptr_reg_n_0_[2]\,
      O => nxt_rd_ptr(3)
    );
\rd_ptr_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_ptr_timing_reg[3]_0\,
      CE => \rd_ptr[0]_i_1__0_n_0\,
      D => nxt_rd_ptr(0),
      Q => \rd_ptr_reg_n_0_[0]\,
      R => SR(0)
    );
\rd_ptr_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_ptr_timing_reg[3]_0\,
      CE => \rd_ptr[0]_i_1__0_n_0\,
      D => nxt_rd_ptr(1),
      Q => \rd_ptr_reg_n_0_[1]\,
      R => SR(0)
    );
\rd_ptr_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_ptr_timing_reg[3]_0\,
      CE => \rd_ptr[0]_i_1__0_n_0\,
      D => nxt_rd_ptr(2),
      Q => \rd_ptr_reg_n_0_[2]\,
      R => SR(0)
    );
\rd_ptr_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_ptr_timing_reg[3]_0\,
      CE => \rd_ptr[0]_i_1__0_n_0\,
      D => nxt_rd_ptr(3),
      Q => \rd_ptr_reg_n_0_[3]\,
      R => SR(0)
    );
\rd_ptr_timing_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_ptr_timing_reg[3]_0\,
      CE => \rd_ptr[0]_i_1__0_n_0\,
      D => nxt_rd_ptr(0),
      Q => rd_ptr_timing(0),
      R => SR(0)
    );
\rd_ptr_timing_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_ptr_timing_reg[3]_0\,
      CE => \rd_ptr[0]_i_1__0_n_0\,
      D => nxt_rd_ptr(1),
      Q => rd_ptr_timing(1),
      R => SR(0)
    );
\rd_ptr_timing_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_ptr_timing_reg[3]_0\,
      CE => \rd_ptr[0]_i_1__0_n_0\,
      D => nxt_rd_ptr(2),
      Q => rd_ptr_timing(2),
      R => SR(0)
    );
\rd_ptr_timing_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_ptr_timing_reg[3]_0\,
      CE => \rd_ptr[0]_i_1__0_n_0\,
      D => nxt_rd_ptr(3),
      Q => rd_ptr_timing(3),
      R => SR(0)
    );
wr_ptr0: unisim.vcomponents.LUT4
    generic map(
      INIT => X"082A"
    )
        port map (
      I0 => phy_cmd_wr_en,
      I1 => \rd_ptr_reg[3]_1\,
      I2 => \my_full_reg_n_0_[3]\,
      I3 => \my_empty_reg_n_0_[6]\,
      O => \wr_ptr0__0\
    );
\wr_ptr[0]_i_1__17\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => wr_ptr(3),
      I1 => wr_ptr(0),
      O => nxt_wr_ptr(0)
    );
\wr_ptr[1]_i_1__17\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B4"
    )
        port map (
      I0 => wr_ptr(3),
      I1 => wr_ptr(0),
      I2 => wr_ptr(1),
      O => nxt_wr_ptr(1)
    );
\wr_ptr[2]_i_1__9\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"AA6A"
    )
        port map (
      I0 => wr_ptr(2),
      I1 => wr_ptr(0),
      I2 => wr_ptr(1),
      I3 => wr_ptr(3),
      O => nxt_wr_ptr(2)
    );
\wr_ptr[3]_i_1__9\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4000"
    )
        port map (
      I0 => wr_ptr(3),
      I1 => wr_ptr(1),
      I2 => wr_ptr(0),
      I3 => wr_ptr(2),
      O => nxt_wr_ptr(3)
    );
\wr_ptr_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_ptr_timing_reg[3]_0\,
      CE => \wr_ptr0__0\,
      D => nxt_wr_ptr(0),
      Q => wr_ptr(0),
      R => SR(0)
    );
\wr_ptr_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_ptr_timing_reg[3]_0\,
      CE => \wr_ptr0__0\,
      D => nxt_wr_ptr(1),
      Q => wr_ptr(1),
      R => SR(0)
    );
\wr_ptr_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_ptr_timing_reg[3]_0\,
      CE => \wr_ptr0__0\,
      D => nxt_wr_ptr(2),
      Q => wr_ptr(2),
      R => SR(0)
    );
\wr_ptr_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_ptr_timing_reg[3]_0\,
      CE => \wr_ptr0__0\,
      D => nxt_wr_ptr(3),
      Q => wr_ptr(3),
      R => SR(0)
    );
\wr_ptr_timing_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_ptr_timing_reg[3]_0\,
      CE => \wr_ptr0__0\,
      D => nxt_wr_ptr(0),
      Q => wr_ptr_timing(0),
      R => SR(0)
    );
\wr_ptr_timing_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_ptr_timing_reg[3]_0\,
      CE => \wr_ptr0__0\,
      D => nxt_wr_ptr(1),
      Q => wr_ptr_timing(1),
      R => SR(0)
    );
\wr_ptr_timing_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_ptr_timing_reg[3]_0\,
      CE => \wr_ptr0__0\,
      D => nxt_wr_ptr(2),
      Q => wr_ptr_timing(2),
      R => SR(0)
    );
\wr_ptr_timing_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_ptr_timing_reg[3]_0\,
      CE => \wr_ptr0__0\,
      D => nxt_wr_ptr(3),
      Q => wr_ptr_timing(3),
      R => SR(0)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \mig_mig_7series_v4_2_ddr_of_pre_fifo__parameterized1_23\ is
  port (
    \my_empty_reg[1]_0\ : out STD_LOGIC;
    \my_empty_reg[1]_1\ : out STD_LOGIC;
    D0 : out STD_LOGIC_VECTOR ( 5 downto 0 );
    D3 : out STD_LOGIC_VECTOR ( 1 downto 0 );
    D4 : out STD_LOGIC_VECTOR ( 3 downto 0 );
    D6 : out STD_LOGIC_VECTOR ( 3 downto 0 );
    D7 : out STD_LOGIC_VECTOR ( 7 downto 0 );
    D8 : out STD_LOGIC_VECTOR ( 3 downto 0 );
    D9 : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \rd_ptr_reg[3]_0\ : out STD_LOGIC_VECTOR ( 23 downto 0 );
    SR : in STD_LOGIC_VECTOR ( 0 to 0 );
    \wr_ptr_timing_reg[3]_0\ : in STD_LOGIC;
    phy_cmd_wr_en : in STD_LOGIC;
    \my_empty_reg[7]_0\ : in STD_LOGIC;
    phy_dout : in STD_LOGIC_VECTOR ( 23 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \mig_mig_7series_v4_2_ddr_of_pre_fifo__parameterized1_23\ : entity is "mig_7series_v4_2_ddr_of_pre_fifo";
end \mig_mig_7series_v4_2_ddr_of_pre_fifo__parameterized1_23\;

architecture STRUCTURE of \mig_mig_7series_v4_2_ddr_of_pre_fifo__parameterized1_23\ is
  signal mem_out : STD_LOGIC_VECTOR ( 77 downto 2 );
  signal my_empty0 : STD_LOGIC;
  signal \my_empty[1]_i_1_n_0\ : STD_LOGIC;
  signal \my_empty[7]_i_1_n_0\ : STD_LOGIC;
  signal \my_empty[7]_i_3_n_0\ : STD_LOGIC;
  signal \my_empty[7]_i_4_n_0\ : STD_LOGIC;
  signal \^my_empty_reg[1]_1\ : STD_LOGIC;
  signal \my_empty_reg_n_0_[7]\ : STD_LOGIC;
  signal my_full0 : STD_LOGIC;
  signal \my_full[4]_i_1_n_0\ : STD_LOGIC;
  signal \my_full[4]_i_3_n_0\ : STD_LOGIC;
  signal \my_full[4]_i_4_n_0\ : STD_LOGIC;
  signal \my_full_reg_n_0_[4]\ : STD_LOGIC;
  signal nxt_rd_ptr : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal nxt_wr_ptr : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal rd_ptr : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal rd_ptr_timing : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \rd_ptr_timing[3]_i_1_n_0\ : STD_LOGIC;
  signal wr_en : STD_LOGIC;
  attribute MAX_FANOUT : string;
  attribute MAX_FANOUT of wr_en : signal is "50";
  attribute RTL_MAX_FANOUT : string;
  attribute RTL_MAX_FANOUT of wr_en : signal is "found";
  signal wr_ptr : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \wr_ptr0__0\ : STD_LOGIC;
  signal wr_ptr_timing : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal NLW_mem_reg_0_15_30_35_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_15_36_41_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_15_42_47_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_15_48_53_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_15_54_59_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_15_60_65_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_15_66_71_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_15_6_11_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_15_72_77_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  attribute METHODOLOGY_DRC_VIOS : string;
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_15_30_35 : label is "";
  attribute RTL_RAM_BITS : integer;
  attribute RTL_RAM_BITS of mem_reg_0_15_30_35 : label is 720;
  attribute RTL_RAM_NAME : string;
  attribute RTL_RAM_NAME of mem_reg_0_15_30_35 : label is "of_pre_fifo_gen.u_ddr_of_pre_fifo/mem";
  attribute ram_addr_begin : integer;
  attribute ram_addr_begin of mem_reg_0_15_30_35 : label is 0;
  attribute ram_addr_end : integer;
  attribute ram_addr_end of mem_reg_0_15_30_35 : label is 8;
  attribute ram_offset : integer;
  attribute ram_offset of mem_reg_0_15_30_35 : label is 0;
  attribute ram_slice_begin : integer;
  attribute ram_slice_begin of mem_reg_0_15_30_35 : label is 30;
  attribute ram_slice_end : integer;
  attribute ram_slice_end of mem_reg_0_15_30_35 : label is 35;
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_15_36_41 : label is "";
  attribute RTL_RAM_BITS of mem_reg_0_15_36_41 : label is 720;
  attribute RTL_RAM_NAME of mem_reg_0_15_36_41 : label is "of_pre_fifo_gen.u_ddr_of_pre_fifo/mem";
  attribute ram_addr_begin of mem_reg_0_15_36_41 : label is 0;
  attribute ram_addr_end of mem_reg_0_15_36_41 : label is 8;
  attribute ram_offset of mem_reg_0_15_36_41 : label is 0;
  attribute ram_slice_begin of mem_reg_0_15_36_41 : label is 36;
  attribute ram_slice_end of mem_reg_0_15_36_41 : label is 41;
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_15_42_47 : label is "";
  attribute RTL_RAM_BITS of mem_reg_0_15_42_47 : label is 720;
  attribute RTL_RAM_NAME of mem_reg_0_15_42_47 : label is "of_pre_fifo_gen.u_ddr_of_pre_fifo/mem";
  attribute ram_addr_begin of mem_reg_0_15_42_47 : label is 0;
  attribute ram_addr_end of mem_reg_0_15_42_47 : label is 8;
  attribute ram_offset of mem_reg_0_15_42_47 : label is 0;
  attribute ram_slice_begin of mem_reg_0_15_42_47 : label is 42;
  attribute ram_slice_end of mem_reg_0_15_42_47 : label is 47;
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_15_48_53 : label is "";
  attribute RTL_RAM_BITS of mem_reg_0_15_48_53 : label is 720;
  attribute RTL_RAM_NAME of mem_reg_0_15_48_53 : label is "of_pre_fifo_gen.u_ddr_of_pre_fifo/mem";
  attribute ram_addr_begin of mem_reg_0_15_48_53 : label is 0;
  attribute ram_addr_end of mem_reg_0_15_48_53 : label is 8;
  attribute ram_offset of mem_reg_0_15_48_53 : label is 0;
  attribute ram_slice_begin of mem_reg_0_15_48_53 : label is 48;
  attribute ram_slice_end of mem_reg_0_15_48_53 : label is 53;
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_15_54_59 : label is "";
  attribute RTL_RAM_BITS of mem_reg_0_15_54_59 : label is 720;
  attribute RTL_RAM_NAME of mem_reg_0_15_54_59 : label is "of_pre_fifo_gen.u_ddr_of_pre_fifo/mem";
  attribute ram_addr_begin of mem_reg_0_15_54_59 : label is 0;
  attribute ram_addr_end of mem_reg_0_15_54_59 : label is 8;
  attribute ram_offset of mem_reg_0_15_54_59 : label is 0;
  attribute ram_slice_begin of mem_reg_0_15_54_59 : label is 54;
  attribute ram_slice_end of mem_reg_0_15_54_59 : label is 59;
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_15_60_65 : label is "";
  attribute RTL_RAM_BITS of mem_reg_0_15_60_65 : label is 720;
  attribute RTL_RAM_NAME of mem_reg_0_15_60_65 : label is "of_pre_fifo_gen.u_ddr_of_pre_fifo/mem";
  attribute ram_addr_begin of mem_reg_0_15_60_65 : label is 0;
  attribute ram_addr_end of mem_reg_0_15_60_65 : label is 8;
  attribute ram_offset of mem_reg_0_15_60_65 : label is 0;
  attribute ram_slice_begin of mem_reg_0_15_60_65 : label is 60;
  attribute ram_slice_end of mem_reg_0_15_60_65 : label is 65;
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_15_66_71 : label is "";
  attribute RTL_RAM_BITS of mem_reg_0_15_66_71 : label is 720;
  attribute RTL_RAM_NAME of mem_reg_0_15_66_71 : label is "of_pre_fifo_gen.u_ddr_of_pre_fifo/mem";
  attribute ram_addr_begin of mem_reg_0_15_66_71 : label is 0;
  attribute ram_addr_end of mem_reg_0_15_66_71 : label is 8;
  attribute ram_offset of mem_reg_0_15_66_71 : label is 0;
  attribute ram_slice_begin of mem_reg_0_15_66_71 : label is 66;
  attribute ram_slice_end of mem_reg_0_15_66_71 : label is 71;
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_15_6_11 : label is "";
  attribute RTL_RAM_BITS of mem_reg_0_15_6_11 : label is 720;
  attribute RTL_RAM_NAME of mem_reg_0_15_6_11 : label is "of_pre_fifo_gen.u_ddr_of_pre_fifo/mem";
  attribute ram_addr_begin of mem_reg_0_15_6_11 : label is 0;
  attribute ram_addr_end of mem_reg_0_15_6_11 : label is 8;
  attribute ram_offset of mem_reg_0_15_6_11 : label is 0;
  attribute ram_slice_begin of mem_reg_0_15_6_11 : label is 6;
  attribute ram_slice_end of mem_reg_0_15_6_11 : label is 11;
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_15_72_77 : label is "";
  attribute RTL_RAM_BITS of mem_reg_0_15_72_77 : label is 720;
  attribute RTL_RAM_NAME of mem_reg_0_15_72_77 : label is "of_pre_fifo_gen.u_ddr_of_pre_fifo/mem";
  attribute ram_addr_begin of mem_reg_0_15_72_77 : label is 0;
  attribute ram_addr_end of mem_reg_0_15_72_77 : label is 8;
  attribute ram_offset of mem_reg_0_15_72_77 : label is 0;
  attribute ram_slice_begin of mem_reg_0_15_72_77 : label is 72;
  attribute ram_slice_end of mem_reg_0_15_72_77 : label is 77;
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \my_empty[7]_i_3\ : label is "soft_lutpair889";
  attribute SOFT_HLUTNM of \my_empty[7]_i_4\ : label is "soft_lutpair889";
  attribute syn_maxfan : string;
  attribute syn_maxfan of \my_empty_reg[1]\ : label is "3";
  attribute syn_maxfan of \my_empty_reg[7]\ : label is "3";
  attribute SOFT_HLUTNM of \my_full[4]_i_3\ : label is "soft_lutpair890";
  attribute SOFT_HLUTNM of \my_full[4]_i_4\ : label is "soft_lutpair890";
  attribute syn_maxfan of \my_full_reg[4]\ : label is "3";
  attribute SOFT_HLUTNM of out_fifo_i_1 : label is "soft_lutpair893";
  attribute SOFT_HLUTNM of out_fifo_i_10 : label is "soft_lutpair907";
  attribute SOFT_HLUTNM of out_fifo_i_11 : label is "soft_lutpair903";
  attribute SOFT_HLUTNM of out_fifo_i_12 : label is "soft_lutpair908";
  attribute SOFT_HLUTNM of out_fifo_i_13 : label is "soft_lutpair899";
  attribute SOFT_HLUTNM of out_fifo_i_2 : label is "soft_lutpair899";
  attribute SOFT_HLUTNM of out_fifo_i_3 : label is "soft_lutpair896";
  attribute SOFT_HLUTNM of out_fifo_i_30 : label is "soft_lutpair902";
  attribute SOFT_HLUTNM of out_fifo_i_31 : label is "soft_lutpair902";
  attribute SOFT_HLUTNM of out_fifo_i_32 : label is "soft_lutpair908";
  attribute SOFT_HLUTNM of out_fifo_i_33 : label is "soft_lutpair904";
  attribute SOFT_HLUTNM of out_fifo_i_34 : label is "soft_lutpair905";
  attribute SOFT_HLUTNM of out_fifo_i_35 : label is "soft_lutpair903";
  attribute SOFT_HLUTNM of out_fifo_i_36 : label is "soft_lutpair909";
  attribute SOFT_HLUTNM of out_fifo_i_37 : label is "soft_lutpair900";
  attribute SOFT_HLUTNM of out_fifo_i_38 : label is "soft_lutpair909";
  attribute SOFT_HLUTNM of out_fifo_i_39 : label is "soft_lutpair896";
  attribute SOFT_HLUTNM of out_fifo_i_4 : label is "soft_lutpair900";
  attribute SOFT_HLUTNM of out_fifo_i_40 : label is "soft_lutpair906";
  attribute SOFT_HLUTNM of out_fifo_i_41 : label is "soft_lutpair901";
  attribute SOFT_HLUTNM of out_fifo_i_43 : label is "soft_lutpair898";
  attribute SOFT_HLUTNM of out_fifo_i_44 : label is "soft_lutpair907";
  attribute SOFT_HLUTNM of out_fifo_i_45 : label is "soft_lutpair904";
  attribute SOFT_HLUTNM of out_fifo_i_5 : label is "soft_lutpair897";
  attribute SOFT_HLUTNM of out_fifo_i_50 : label is "soft_lutpair906";
  attribute SOFT_HLUTNM of out_fifo_i_51 : label is "soft_lutpair897";
  attribute SOFT_HLUTNM of out_fifo_i_6 : label is "soft_lutpair898";
  attribute SOFT_HLUTNM of out_fifo_i_7 : label is "soft_lutpair893";
  attribute SOFT_HLUTNM of out_fifo_i_8 : label is "soft_lutpair905";
  attribute SOFT_HLUTNM of out_fifo_i_9 : label is "soft_lutpair901";
  attribute syn_maxfan of \rd_ptr_reg[0]\ : label is "10";
  attribute syn_maxfan of \rd_ptr_reg[1]\ : label is "10";
  attribute syn_maxfan of \rd_ptr_reg[2]\ : label is "10";
  attribute syn_maxfan of \rd_ptr_reg[3]\ : label is "10";
  attribute SOFT_HLUTNM of \rd_ptr_timing[0]_i_1\ : label is "soft_lutpair895";
  attribute SOFT_HLUTNM of \rd_ptr_timing[1]_i_1\ : label is "soft_lutpair895";
  attribute SOFT_HLUTNM of \rd_ptr_timing[2]_i_1\ : label is "soft_lutpair892";
  attribute SOFT_HLUTNM of \rd_ptr_timing[3]_i_2\ : label is "soft_lutpair892";
  attribute KEEP : string;
  attribute KEEP of \rd_ptr_timing_reg[0]\ : label is "yes";
  attribute KEEP of \rd_ptr_timing_reg[1]\ : label is "yes";
  attribute KEEP of \rd_ptr_timing_reg[2]\ : label is "yes";
  attribute KEEP of \rd_ptr_timing_reg[3]\ : label is "yes";
  attribute SOFT_HLUTNM of \wr_ptr[0]_i_1\ : label is "soft_lutpair894";
  attribute SOFT_HLUTNM of \wr_ptr[1]_i_1\ : label is "soft_lutpair894";
  attribute SOFT_HLUTNM of \wr_ptr[2]_i_1\ : label is "soft_lutpair891";
  attribute SOFT_HLUTNM of \wr_ptr[3]_i_1\ : label is "soft_lutpair891";
  attribute syn_maxfan of \wr_ptr_reg[0]\ : label is "10";
  attribute syn_maxfan of \wr_ptr_reg[1]\ : label is "10";
  attribute syn_maxfan of \wr_ptr_reg[2]\ : label is "10";
  attribute syn_maxfan of \wr_ptr_reg[3]\ : label is "10";
  attribute KEEP of \wr_ptr_timing_reg[0]\ : label is "yes";
  attribute KEEP of \wr_ptr_timing_reg[1]\ : label is "yes";
  attribute KEEP of \wr_ptr_timing_reg[2]\ : label is "yes";
  attribute KEEP of \wr_ptr_timing_reg[3]\ : label is "yes";
begin
  \my_empty_reg[1]_1\ <= \^my_empty_reg[1]_1\;
mem_reg_0_15_30_35: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4) => '0',
      ADDRA(3 downto 0) => rd_ptr(3 downto 0),
      ADDRB(4) => '0',
      ADDRB(3 downto 0) => rd_ptr(3 downto 0),
      ADDRC(4) => '0',
      ADDRC(3 downto 0) => rd_ptr(3 downto 0),
      ADDRD(4) => '0',
      ADDRD(3 downto 0) => wr_ptr(3 downto 0),
      DIA(1 downto 0) => B"00",
      DIB(1 downto 0) => phy_dout(1 downto 0),
      DIC(1 downto 0) => phy_dout(3 downto 2),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => mem_out(31 downto 30),
      DOB(1 downto 0) => \rd_ptr_reg[3]_0\(1 downto 0),
      DOC(1 downto 0) => \rd_ptr_reg[3]_0\(3 downto 2),
      DOD(1 downto 0) => NLW_mem_reg_0_15_30_35_DOD_UNCONNECTED(1 downto 0),
      WCLK => \wr_ptr_timing_reg[3]_0\,
      WE => wr_en
    );
mem_reg_0_15_36_41: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4) => '0',
      ADDRA(3 downto 0) => rd_ptr(3 downto 0),
      ADDRB(4) => '0',
      ADDRB(3 downto 0) => rd_ptr(3 downto 0),
      ADDRC(4) => '0',
      ADDRC(3 downto 0) => rd_ptr(3 downto 0),
      ADDRD(4) => '0',
      ADDRD(3 downto 0) => wr_ptr(3 downto 0),
      DIA(1 downto 0) => B"00",
      DIB(1 downto 0) => B"00",
      DIC(1 downto 0) => phy_dout(5 downto 4),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => mem_out(37 downto 36),
      DOB(1 downto 0) => mem_out(39 downto 38),
      DOC(1 downto 0) => \rd_ptr_reg[3]_0\(5 downto 4),
      DOD(1 downto 0) => NLW_mem_reg_0_15_36_41_DOD_UNCONNECTED(1 downto 0),
      WCLK => \wr_ptr_timing_reg[3]_0\,
      WE => wr_en
    );
mem_reg_0_15_42_47: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4) => '0',
      ADDRA(3 downto 0) => rd_ptr(3 downto 0),
      ADDRB(4) => '0',
      ADDRB(3 downto 0) => rd_ptr(3 downto 0),
      ADDRC(4) => '0',
      ADDRC(3 downto 0) => rd_ptr(3 downto 0),
      ADDRD(4) => '0',
      ADDRD(3 downto 0) => wr_ptr(3 downto 0),
      DIA(1 downto 0) => phy_dout(7 downto 6),
      DIB(1 downto 0) => phy_dout(9 downto 8),
      DIC(1 downto 0) => phy_dout(11 downto 10),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => \rd_ptr_reg[3]_0\(7 downto 6),
      DOB(1 downto 0) => \rd_ptr_reg[3]_0\(9 downto 8),
      DOC(1 downto 0) => \rd_ptr_reg[3]_0\(11 downto 10),
      DOD(1 downto 0) => NLW_mem_reg_0_15_42_47_DOD_UNCONNECTED(1 downto 0),
      WCLK => \wr_ptr_timing_reg[3]_0\,
      WE => wr_en
    );
mem_reg_0_15_48_53: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4) => '0',
      ADDRA(3 downto 0) => rd_ptr(3 downto 0),
      ADDRB(4) => '0',
      ADDRB(3 downto 0) => rd_ptr(3 downto 0),
      ADDRC(4) => '0',
      ADDRC(3 downto 0) => rd_ptr(3 downto 0),
      ADDRD(4) => '0',
      ADDRD(3 downto 0) => wr_ptr(3 downto 0),
      DIA(1 downto 0) => B"00",
      DIB(1 downto 0) => B"00",
      DIC(1 downto 0) => phy_dout(13 downto 12),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => mem_out(49 downto 48),
      DOB(1 downto 0) => mem_out(51 downto 50),
      DOC(1 downto 0) => \rd_ptr_reg[3]_0\(13 downto 12),
      DOD(1 downto 0) => NLW_mem_reg_0_15_48_53_DOD_UNCONNECTED(1 downto 0),
      WCLK => \wr_ptr_timing_reg[3]_0\,
      WE => wr_en
    );
mem_reg_0_15_54_59: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4) => '0',
      ADDRA(3 downto 0) => rd_ptr(3 downto 0),
      ADDRB(4) => '0',
      ADDRB(3 downto 0) => rd_ptr(3 downto 0),
      ADDRC(4) => '0',
      ADDRC(3 downto 0) => rd_ptr(3 downto 0),
      ADDRD(4) => '0',
      ADDRD(3 downto 0) => wr_ptr(3 downto 0),
      DIA(1 downto 0) => phy_dout(15 downto 14),
      DIB(1 downto 0) => B"00",
      DIC(1 downto 0) => B"00",
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => \rd_ptr_reg[3]_0\(15 downto 14),
      DOB(1 downto 0) => mem_out(57 downto 56),
      DOC(1 downto 0) => mem_out(59 downto 58),
      DOD(1 downto 0) => NLW_mem_reg_0_15_54_59_DOD_UNCONNECTED(1 downto 0),
      WCLK => \wr_ptr_timing_reg[3]_0\,
      WE => wr_en
    );
mem_reg_0_15_60_65: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4) => '0',
      ADDRA(3 downto 0) => rd_ptr(3 downto 0),
      ADDRB(4) => '0',
      ADDRB(3 downto 0) => rd_ptr(3 downto 0),
      ADDRC(4) => '0',
      ADDRC(3 downto 0) => rd_ptr(3 downto 0),
      ADDRD(4) => '0',
      ADDRD(3 downto 0) => wr_ptr(3 downto 0),
      DIA(1 downto 0) => B"00",
      DIB(1 downto 0) => B"00",
      DIC(1 downto 0) => phy_dout(17 downto 16),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => mem_out(61 downto 60),
      DOB(1 downto 0) => mem_out(63 downto 62),
      DOC(1 downto 0) => \rd_ptr_reg[3]_0\(17 downto 16),
      DOD(1 downto 0) => NLW_mem_reg_0_15_60_65_DOD_UNCONNECTED(1 downto 0),
      WCLK => \wr_ptr_timing_reg[3]_0\,
      WE => wr_en
    );
mem_reg_0_15_66_71: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4) => '0',
      ADDRA(3 downto 0) => rd_ptr(3 downto 0),
      ADDRB(4) => '0',
      ADDRB(3 downto 0) => rd_ptr(3 downto 0),
      ADDRC(4) => '0',
      ADDRC(3 downto 0) => rd_ptr(3 downto 0),
      ADDRD(4) => '0',
      ADDRD(3 downto 0) => wr_ptr(3 downto 0),
      DIA(1 downto 0) => phy_dout(19 downto 18),
      DIB(1 downto 0) => B"00",
      DIC(1 downto 0) => B"00",
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => \rd_ptr_reg[3]_0\(19 downto 18),
      DOB(1 downto 0) => mem_out(69 downto 68),
      DOC(1 downto 0) => mem_out(71 downto 70),
      DOD(1 downto 0) => NLW_mem_reg_0_15_66_71_DOD_UNCONNECTED(1 downto 0),
      WCLK => \wr_ptr_timing_reg[3]_0\,
      WE => wr_en
    );
mem_reg_0_15_6_11: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4) => '0',
      ADDRA(3 downto 0) => rd_ptr(3 downto 0),
      ADDRB(4) => '0',
      ADDRB(3 downto 0) => rd_ptr(3 downto 0),
      ADDRC(4) => '0',
      ADDRC(3 downto 0) => rd_ptr(3 downto 0),
      ADDRD(4) => '0',
      ADDRD(3 downto 0) => wr_ptr(3 downto 0),
      DIA(1 downto 0) => B"00",
      DIB(1 downto 0) => B"00",
      DIC(1 downto 0) => B"00",
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => mem_out(7 downto 6),
      DOB(1 downto 0) => mem_out(3 downto 2),
      DOC(1 downto 0) => mem_out(5 downto 4),
      DOD(1 downto 0) => NLW_mem_reg_0_15_6_11_DOD_UNCONNECTED(1 downto 0),
      WCLK => \wr_ptr_timing_reg[3]_0\,
      WE => wr_en
    );
mem_reg_0_15_72_77: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4) => '0',
      ADDRA(3 downto 0) => rd_ptr(3 downto 0),
      ADDRB(4) => '0',
      ADDRB(3 downto 0) => rd_ptr(3 downto 0),
      ADDRC(4) => '0',
      ADDRC(3 downto 0) => rd_ptr(3 downto 0),
      ADDRD(4) => '0',
      ADDRD(3 downto 0) => wr_ptr(3 downto 0),
      DIA(1 downto 0) => phy_dout(21 downto 20),
      DIB(1 downto 0) => phy_dout(23 downto 22),
      DIC(1 downto 0) => B"00",
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => \rd_ptr_reg[3]_0\(21 downto 20),
      DOB(1 downto 0) => \rd_ptr_reg[3]_0\(23 downto 22),
      DOC(1 downto 0) => mem_out(77 downto 76),
      DOD(1 downto 0) => NLW_mem_reg_0_15_72_77_DOD_UNCONNECTED(1 downto 0),
      WCLK => \wr_ptr_timing_reg[3]_0\,
      WE => wr_en
    );
\my_empty[1]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFF701F700"
    )
        port map (
      I0 => \my_empty_reg[7]_0\,
      I1 => phy_cmd_wr_en,
      I2 => \my_full_reg_n_0_[4]\,
      I3 => \^my_empty_reg[1]_1\,
      I4 => my_empty0,
      I5 => SR(0),
      O => \my_empty[1]_i_1_n_0\
    );
\my_empty[7]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFF701F700"
    )
        port map (
      I0 => \my_empty_reg[7]_0\,
      I1 => phy_cmd_wr_en,
      I2 => \my_full_reg_n_0_[4]\,
      I3 => \my_empty_reg_n_0_[7]\,
      I4 => my_empty0,
      I5 => SR(0),
      O => \my_empty[7]_i_1_n_0\
    );
\my_empty[7]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"4A400D08"
    )
        port map (
      I0 => wr_ptr_timing(2),
      I1 => \my_empty[7]_i_3_n_0\,
      I2 => wr_ptr_timing(3),
      I3 => \my_empty[7]_i_4_n_0\,
      I4 => rd_ptr(2),
      O => my_empty0
    );
\my_empty[7]_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000040"
    )
        port map (
      I0 => wr_ptr_timing(1),
      I1 => rd_ptr(0),
      I2 => rd_ptr(1),
      I3 => rd_ptr(3),
      I4 => wr_ptr_timing(0),
      O => \my_empty[7]_i_3_n_0\
    );
\my_empty[7]_i_4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"84210842"
    )
        port map (
      I0 => wr_ptr_timing(0),
      I1 => wr_ptr_timing(1),
      I2 => rd_ptr(0),
      I3 => rd_ptr(1),
      I4 => rd_ptr(3),
      O => \my_empty[7]_i_4_n_0\
    );
\my_empty_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_ptr_timing_reg[3]_0\,
      CE => '1',
      D => \my_empty[1]_i_1_n_0\,
      Q => \^my_empty_reg[1]_1\,
      R => '0'
    );
\my_empty_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_ptr_timing_reg[3]_0\,
      CE => '1',
      D => \my_empty[7]_i_1_n_0\,
      Q => \my_empty_reg_n_0_[7]\,
      R => '0'
    );
\my_full[4]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000FFFC0080"
    )
        port map (
      I0 => my_full0,
      I1 => phy_cmd_wr_en,
      I2 => \my_empty_reg[7]_0\,
      I3 => \my_empty_reg_n_0_[7]\,
      I4 => \my_full_reg_n_0_[4]\,
      I5 => SR(0),
      O => \my_full[4]_i_1_n_0\
    );
\my_full[4]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"4A400D08"
    )
        port map (
      I0 => rd_ptr_timing(2),
      I1 => \my_full[4]_i_3_n_0\,
      I2 => rd_ptr_timing(3),
      I3 => \my_full[4]_i_4_n_0\,
      I4 => wr_ptr(2),
      O => my_full0
    );
\my_full[4]_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000040"
    )
        port map (
      I0 => rd_ptr_timing(1),
      I1 => wr_ptr(0),
      I2 => wr_ptr(1),
      I3 => wr_ptr(3),
      I4 => rd_ptr_timing(0),
      O => \my_full[4]_i_3_n_0\
    );
\my_full[4]_i_4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"84210842"
    )
        port map (
      I0 => rd_ptr_timing(0),
      I1 => rd_ptr_timing(1),
      I2 => wr_ptr(0),
      I3 => wr_ptr(1),
      I4 => wr_ptr(3),
      O => \my_full[4]_i_4_n_0\
    );
\my_full_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_ptr_timing_reg[3]_0\,
      CE => '1',
      D => \my_full[4]_i_1_n_0\,
      Q => \my_full_reg_n_0_[4]\,
      R => '0'
    );
out_fifo_i_1: unisim.vcomponents.LUT3
    generic map(
      INIT => X"0D"
    )
        port map (
      I0 => \^my_empty_reg[1]_1\,
      I1 => phy_cmd_wr_en,
      I2 => \my_empty_reg[7]_0\,
      O => \my_empty_reg[1]_0\
    );
out_fifo_i_10: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => mem_out(39),
      I1 => \^my_empty_reg[1]_1\,
      O => D4(3)
    );
out_fifo_i_11: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => mem_out(38),
      I1 => \^my_empty_reg[1]_1\,
      O => D4(2)
    );
out_fifo_i_12: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => mem_out(37),
      I1 => \^my_empty_reg[1]_1\,
      O => D4(1)
    );
out_fifo_i_13: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => mem_out(36),
      I1 => \^my_empty_reg[1]_1\,
      O => D4(0)
    );
out_fifo_i_2: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => mem_out(7),
      I1 => \^my_empty_reg[1]_1\,
      O => D0(5)
    );
out_fifo_i_3: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => mem_out(6),
      I1 => \^my_empty_reg[1]_1\,
      O => D0(4)
    );
out_fifo_i_30: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => mem_out(51),
      I1 => \^my_empty_reg[1]_1\,
      O => D6(3)
    );
out_fifo_i_31: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => mem_out(50),
      I1 => \^my_empty_reg[1]_1\,
      O => D6(2)
    );
out_fifo_i_32: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => mem_out(49),
      I1 => \^my_empty_reg[1]_1\,
      O => D6(1)
    );
out_fifo_i_33: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => mem_out(48),
      I1 => \^my_empty_reg[1]_1\,
      O => D6(0)
    );
out_fifo_i_34: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => mem_out(63),
      I1 => \^my_empty_reg[1]_1\,
      O => D7(7)
    );
out_fifo_i_35: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => mem_out(62),
      I1 => \^my_empty_reg[1]_1\,
      O => D7(6)
    );
out_fifo_i_36: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => mem_out(61),
      I1 => \^my_empty_reg[1]_1\,
      O => D7(5)
    );
out_fifo_i_37: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => mem_out(60),
      I1 => \^my_empty_reg[1]_1\,
      O => D7(4)
    );
out_fifo_i_38: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => mem_out(59),
      I1 => \^my_empty_reg[1]_1\,
      O => D7(3)
    );
out_fifo_i_39: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => mem_out(58),
      I1 => \^my_empty_reg[1]_1\,
      O => D7(2)
    );
out_fifo_i_4: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => mem_out(5),
      I1 => \^my_empty_reg[1]_1\,
      O => D0(3)
    );
out_fifo_i_40: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => mem_out(57),
      I1 => \^my_empty_reg[1]_1\,
      O => D7(1)
    );
out_fifo_i_41: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => mem_out(56),
      I1 => \^my_empty_reg[1]_1\,
      O => D7(0)
    );
out_fifo_i_42: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => mem_out(71),
      I1 => \^my_empty_reg[1]_1\,
      O => D8(3)
    );
out_fifo_i_43: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => mem_out(70),
      I1 => \^my_empty_reg[1]_1\,
      O => D8(2)
    );
out_fifo_i_44: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => mem_out(69),
      I1 => \^my_empty_reg[1]_1\,
      O => D8(1)
    );
out_fifo_i_45: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => mem_out(68),
      I1 => \^my_empty_reg[1]_1\,
      O => D8(0)
    );
out_fifo_i_5: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => mem_out(4),
      I1 => \^my_empty_reg[1]_1\,
      O => D0(2)
    );
out_fifo_i_50: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => mem_out(77),
      I1 => \^my_empty_reg[1]_1\,
      O => D9(1)
    );
out_fifo_i_51: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => mem_out(76),
      I1 => \^my_empty_reg[1]_1\,
      O => D9(0)
    );
out_fifo_i_6: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => mem_out(3),
      I1 => \^my_empty_reg[1]_1\,
      O => D0(1)
    );
out_fifo_i_7: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => mem_out(2),
      I1 => \^my_empty_reg[1]_1\,
      O => D0(0)
    );
out_fifo_i_8: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => mem_out(31),
      I1 => \^my_empty_reg[1]_1\,
      O => D3(1)
    );
out_fifo_i_9: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => mem_out(30),
      I1 => \^my_empty_reg[1]_1\,
      O => D3(0)
    );
p_17_out: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2700"
    )
        port map (
      I0 => \my_empty_reg[7]_0\,
      I1 => \my_full_reg_n_0_[4]\,
      I2 => \^my_empty_reg[1]_1\,
      I3 => phy_cmd_wr_en,
      O => wr_en
    );
\rd_ptr_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_ptr_timing_reg[3]_0\,
      CE => \rd_ptr_timing[3]_i_1_n_0\,
      D => nxt_rd_ptr(0),
      Q => rd_ptr(0),
      R => SR(0)
    );
\rd_ptr_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_ptr_timing_reg[3]_0\,
      CE => \rd_ptr_timing[3]_i_1_n_0\,
      D => nxt_rd_ptr(1),
      Q => rd_ptr(1),
      R => SR(0)
    );
\rd_ptr_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_ptr_timing_reg[3]_0\,
      CE => \rd_ptr_timing[3]_i_1_n_0\,
      D => nxt_rd_ptr(2),
      Q => rd_ptr(2),
      R => SR(0)
    );
\rd_ptr_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_ptr_timing_reg[3]_0\,
      CE => \rd_ptr_timing[3]_i_1_n_0\,
      D => nxt_rd_ptr(3),
      Q => rd_ptr(3),
      R => SR(0)
    );
\rd_ptr_timing[0]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => rd_ptr(3),
      I1 => rd_ptr(0),
      O => nxt_rd_ptr(0)
    );
\rd_ptr_timing[1]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B4"
    )
        port map (
      I0 => rd_ptr(3),
      I1 => rd_ptr(0),
      I2 => rd_ptr(1),
      O => nxt_rd_ptr(1)
    );
\rd_ptr_timing[2]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"AA6A"
    )
        port map (
      I0 => rd_ptr(2),
      I1 => rd_ptr(0),
      I2 => rd_ptr(1),
      I3 => rd_ptr(3),
      O => nxt_rd_ptr(2)
    );
\rd_ptr_timing[3]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \my_empty_reg[7]_0\,
      I1 => \my_empty_reg_n_0_[7]\,
      O => \rd_ptr_timing[3]_i_1_n_0\
    );
\rd_ptr_timing[3]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4000"
    )
        port map (
      I0 => rd_ptr(3),
      I1 => rd_ptr(1),
      I2 => rd_ptr(0),
      I3 => rd_ptr(2),
      O => nxt_rd_ptr(3)
    );
\rd_ptr_timing_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_ptr_timing_reg[3]_0\,
      CE => \rd_ptr_timing[3]_i_1_n_0\,
      D => nxt_rd_ptr(0),
      Q => rd_ptr_timing(0),
      R => SR(0)
    );
\rd_ptr_timing_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_ptr_timing_reg[3]_0\,
      CE => \rd_ptr_timing[3]_i_1_n_0\,
      D => nxt_rd_ptr(1),
      Q => rd_ptr_timing(1),
      R => SR(0)
    );
\rd_ptr_timing_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_ptr_timing_reg[3]_0\,
      CE => \rd_ptr_timing[3]_i_1_n_0\,
      D => nxt_rd_ptr(2),
      Q => rd_ptr_timing(2),
      R => SR(0)
    );
\rd_ptr_timing_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_ptr_timing_reg[3]_0\,
      CE => \rd_ptr_timing[3]_i_1_n_0\,
      D => nxt_rd_ptr(3),
      Q => rd_ptr_timing(3),
      R => SR(0)
    );
wr_ptr0: unisim.vcomponents.LUT4
    generic map(
      INIT => X"082A"
    )
        port map (
      I0 => phy_cmd_wr_en,
      I1 => \my_empty_reg[7]_0\,
      I2 => \my_full_reg_n_0_[4]\,
      I3 => \my_empty_reg_n_0_[7]\,
      O => \wr_ptr0__0\
    );
\wr_ptr[0]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => wr_ptr(3),
      I1 => wr_ptr(0),
      O => nxt_wr_ptr(0)
    );
\wr_ptr[1]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B4"
    )
        port map (
      I0 => wr_ptr(3),
      I1 => wr_ptr(0),
      I2 => wr_ptr(1),
      O => nxt_wr_ptr(1)
    );
\wr_ptr[2]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"AA6A"
    )
        port map (
      I0 => wr_ptr(2),
      I1 => wr_ptr(0),
      I2 => wr_ptr(1),
      I3 => wr_ptr(3),
      O => nxt_wr_ptr(2)
    );
\wr_ptr[3]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4000"
    )
        port map (
      I0 => wr_ptr(3),
      I1 => wr_ptr(1),
      I2 => wr_ptr(0),
      I3 => wr_ptr(2),
      O => nxt_wr_ptr(3)
    );
\wr_ptr_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_ptr_timing_reg[3]_0\,
      CE => \wr_ptr0__0\,
      D => nxt_wr_ptr(0),
      Q => wr_ptr(0),
      R => SR(0)
    );
\wr_ptr_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_ptr_timing_reg[3]_0\,
      CE => \wr_ptr0__0\,
      D => nxt_wr_ptr(1),
      Q => wr_ptr(1),
      R => SR(0)
    );
\wr_ptr_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_ptr_timing_reg[3]_0\,
      CE => \wr_ptr0__0\,
      D => nxt_wr_ptr(2),
      Q => wr_ptr(2),
      R => SR(0)
    );
\wr_ptr_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_ptr_timing_reg[3]_0\,
      CE => \wr_ptr0__0\,
      D => nxt_wr_ptr(3),
      Q => wr_ptr(3),
      R => SR(0)
    );
\wr_ptr_timing_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_ptr_timing_reg[3]_0\,
      CE => \wr_ptr0__0\,
      D => nxt_wr_ptr(0),
      Q => wr_ptr_timing(0),
      R => SR(0)
    );
\wr_ptr_timing_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_ptr_timing_reg[3]_0\,
      CE => \wr_ptr0__0\,
      D => nxt_wr_ptr(1),
      Q => wr_ptr_timing(1),
      R => SR(0)
    );
\wr_ptr_timing_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_ptr_timing_reg[3]_0\,
      CE => \wr_ptr0__0\,
      D => nxt_wr_ptr(2),
      Q => wr_ptr_timing(2),
      R => SR(0)
    );
\wr_ptr_timing_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_ptr_timing_reg[3]_0\,
      CE => \wr_ptr0__0\,
      D => nxt_wr_ptr(3),
      Q => wr_ptr_timing(3),
      R => SR(0)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \mig_mig_7series_v4_2_ddr_of_pre_fifo__parameterized1_24\ is
  port (
    \my_empty_reg[1]_0\ : out STD_LOGIC;
    \my_empty_reg[1]_1\ : out STD_LOGIC;
    D4 : out STD_LOGIC_VECTOR ( 6 downto 0 );
    D5 : out STD_LOGIC_VECTOR ( 5 downto 0 );
    D6 : out STD_LOGIC_VECTOR ( 6 downto 0 );
    D3 : out STD_LOGIC_VECTOR ( 7 downto 0 );
    D1 : out STD_LOGIC_VECTOR ( 3 downto 0 );
    D2 : out STD_LOGIC_VECTOR ( 3 downto 0 );
    mem_out : out STD_LOGIC_VECTOR ( 11 downto 0 );
    SR : in STD_LOGIC_VECTOR ( 0 to 0 );
    \my_full_reg[3]_0\ : in STD_LOGIC;
    phy_cmd_wr_en : in STD_LOGIC;
    B_of_full : in STD_LOGIC;
    mc_we_n : in STD_LOGIC_VECTOR ( 1 downto 0 );
    out_fifo : in STD_LOGIC;
    mc_ras_n : in STD_LOGIC_VECTOR ( 1 downto 0 );
    mc_cs_n : in STD_LOGIC_VECTOR ( 0 to 0 );
    mc_cas_n : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \out_fifo_i_47__8\ : in STD_LOGIC_VECTOR ( 12 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \mig_mig_7series_v4_2_ddr_of_pre_fifo__parameterized1_24\ : entity is "mig_7series_v4_2_ddr_of_pre_fifo";
end \mig_mig_7series_v4_2_ddr_of_pre_fifo__parameterized1_24\;

architecture STRUCTURE of \mig_mig_7series_v4_2_ddr_of_pre_fifo__parameterized1_24\ is
  signal mem_out_0 : STD_LOGIC_VECTOR ( 55 downto 2 );
  signal my_empty0 : STD_LOGIC;
  signal \my_empty[1]_i_1_n_0\ : STD_LOGIC;
  signal \my_empty[6]_i_1_n_0\ : STD_LOGIC;
  signal \my_empty[6]_i_3_n_0\ : STD_LOGIC;
  signal \my_empty[6]_i_4_n_0\ : STD_LOGIC;
  signal \^my_empty_reg[1]_0\ : STD_LOGIC;
  signal \my_empty_reg_n_0_[6]\ : STD_LOGIC;
  signal my_full0 : STD_LOGIC;
  signal \my_full[3]_i_1_n_0\ : STD_LOGIC;
  signal \my_full[3]_i_3_n_0\ : STD_LOGIC;
  signal \my_full[3]_i_4_n_0\ : STD_LOGIC;
  signal \my_full_reg_n_0_[3]\ : STD_LOGIC;
  signal nxt_rd_ptr : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal nxt_wr_ptr : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal rd_ptr : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \rd_ptr[0]_i_1_n_0\ : STD_LOGIC;
  signal rd_ptr_timing : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal wr_en : STD_LOGIC;
  attribute MAX_FANOUT : string;
  attribute MAX_FANOUT of wr_en : signal is "50";
  attribute RTL_MAX_FANOUT : string;
  attribute RTL_MAX_FANOUT of wr_en : signal is "found";
  signal wr_ptr : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \wr_ptr0__0\ : STD_LOGIC;
  signal wr_ptr_timing : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal NLW_mem_reg_0_15_12_17_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_15_18_23_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_15_30_35_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_15_36_41_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_15_42_47_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_15_48_53_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_15_54_59_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_15_6_11_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  attribute METHODOLOGY_DRC_VIOS : string;
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_15_12_17 : label is "";
  attribute RTL_RAM_BITS : integer;
  attribute RTL_RAM_BITS of mem_reg_0_15_12_17 : label is 720;
  attribute RTL_RAM_NAME : string;
  attribute RTL_RAM_NAME of mem_reg_0_15_12_17 : label is "ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem";
  attribute ram_addr_begin : integer;
  attribute ram_addr_begin of mem_reg_0_15_12_17 : label is 0;
  attribute ram_addr_end : integer;
  attribute ram_addr_end of mem_reg_0_15_12_17 : label is 8;
  attribute ram_offset : integer;
  attribute ram_offset of mem_reg_0_15_12_17 : label is 0;
  attribute ram_slice_begin : integer;
  attribute ram_slice_begin of mem_reg_0_15_12_17 : label is 12;
  attribute ram_slice_end : integer;
  attribute ram_slice_end of mem_reg_0_15_12_17 : label is 17;
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_15_18_23 : label is "";
  attribute RTL_RAM_BITS of mem_reg_0_15_18_23 : label is 720;
  attribute RTL_RAM_NAME of mem_reg_0_15_18_23 : label is "ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem";
  attribute ram_addr_begin of mem_reg_0_15_18_23 : label is 0;
  attribute ram_addr_end of mem_reg_0_15_18_23 : label is 8;
  attribute ram_offset of mem_reg_0_15_18_23 : label is 0;
  attribute ram_slice_begin of mem_reg_0_15_18_23 : label is 18;
  attribute ram_slice_end of mem_reg_0_15_18_23 : label is 23;
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_15_30_35 : label is "";
  attribute RTL_RAM_BITS of mem_reg_0_15_30_35 : label is 720;
  attribute RTL_RAM_NAME of mem_reg_0_15_30_35 : label is "ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem";
  attribute ram_addr_begin of mem_reg_0_15_30_35 : label is 0;
  attribute ram_addr_end of mem_reg_0_15_30_35 : label is 8;
  attribute ram_offset of mem_reg_0_15_30_35 : label is 0;
  attribute ram_slice_begin of mem_reg_0_15_30_35 : label is 30;
  attribute ram_slice_end of mem_reg_0_15_30_35 : label is 35;
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_15_36_41 : label is "";
  attribute RTL_RAM_BITS of mem_reg_0_15_36_41 : label is 720;
  attribute RTL_RAM_NAME of mem_reg_0_15_36_41 : label is "ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem";
  attribute ram_addr_begin of mem_reg_0_15_36_41 : label is 0;
  attribute ram_addr_end of mem_reg_0_15_36_41 : label is 8;
  attribute ram_offset of mem_reg_0_15_36_41 : label is 0;
  attribute ram_slice_begin of mem_reg_0_15_36_41 : label is 36;
  attribute ram_slice_end of mem_reg_0_15_36_41 : label is 41;
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_15_42_47 : label is "";
  attribute RTL_RAM_BITS of mem_reg_0_15_42_47 : label is 720;
  attribute RTL_RAM_NAME of mem_reg_0_15_42_47 : label is "ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem";
  attribute ram_addr_begin of mem_reg_0_15_42_47 : label is 0;
  attribute ram_addr_end of mem_reg_0_15_42_47 : label is 8;
  attribute ram_offset of mem_reg_0_15_42_47 : label is 0;
  attribute ram_slice_begin of mem_reg_0_15_42_47 : label is 42;
  attribute ram_slice_end of mem_reg_0_15_42_47 : label is 47;
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_15_48_53 : label is "";
  attribute RTL_RAM_BITS of mem_reg_0_15_48_53 : label is 720;
  attribute RTL_RAM_NAME of mem_reg_0_15_48_53 : label is "ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem";
  attribute ram_addr_begin of mem_reg_0_15_48_53 : label is 0;
  attribute ram_addr_end of mem_reg_0_15_48_53 : label is 8;
  attribute ram_offset of mem_reg_0_15_48_53 : label is 0;
  attribute ram_slice_begin of mem_reg_0_15_48_53 : label is 48;
  attribute ram_slice_end of mem_reg_0_15_48_53 : label is 53;
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_15_54_59 : label is "";
  attribute RTL_RAM_BITS of mem_reg_0_15_54_59 : label is 720;
  attribute RTL_RAM_NAME of mem_reg_0_15_54_59 : label is "ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem";
  attribute ram_addr_begin of mem_reg_0_15_54_59 : label is 0;
  attribute ram_addr_end of mem_reg_0_15_54_59 : label is 8;
  attribute ram_offset of mem_reg_0_15_54_59 : label is 0;
  attribute ram_slice_begin of mem_reg_0_15_54_59 : label is 54;
  attribute ram_slice_end of mem_reg_0_15_54_59 : label is 59;
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_15_6_11 : label is "";
  attribute RTL_RAM_BITS of mem_reg_0_15_6_11 : label is 720;
  attribute RTL_RAM_NAME of mem_reg_0_15_6_11 : label is "ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem";
  attribute ram_addr_begin of mem_reg_0_15_6_11 : label is 0;
  attribute ram_addr_end of mem_reg_0_15_6_11 : label is 8;
  attribute ram_offset of mem_reg_0_15_6_11 : label is 0;
  attribute ram_slice_begin of mem_reg_0_15_6_11 : label is 6;
  attribute ram_slice_end of mem_reg_0_15_6_11 : label is 11;
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \my_empty[1]_i_1\ : label is "soft_lutpair866";
  attribute SOFT_HLUTNM of \my_empty[6]_i_3\ : label is "soft_lutpair865";
  attribute SOFT_HLUTNM of \my_empty[6]_i_4\ : label is "soft_lutpair865";
  attribute syn_maxfan : string;
  attribute syn_maxfan of \my_empty_reg[1]\ : label is "3";
  attribute syn_maxfan of \my_empty_reg[6]\ : label is "3";
  attribute SOFT_HLUTNM of \my_full[3]_i_3\ : label is "soft_lutpair864";
  attribute SOFT_HLUTNM of \my_full[3]_i_4\ : label is "soft_lutpair864";
  attribute syn_maxfan of \my_full_reg[3]\ : label is "3";
  attribute SOFT_HLUTNM of \out_fifo_i_10__0\ : label is "soft_lutpair882";
  attribute SOFT_HLUTNM of \out_fifo_i_11__0\ : label is "soft_lutpair873";
  attribute SOFT_HLUTNM of \out_fifo_i_12__0\ : label is "soft_lutpair879";
  attribute SOFT_HLUTNM of \out_fifo_i_13__0\ : label is "soft_lutpair880";
  attribute SOFT_HLUTNM of out_fifo_i_14 : label is "soft_lutpair884";
  attribute SOFT_HLUTNM of out_fifo_i_15 : label is "soft_lutpair875";
  attribute SOFT_HLUTNM of \out_fifo_i_1__8\ : label is "soft_lutpair866";
  attribute SOFT_HLUTNM of out_fifo_i_20 : label is "soft_lutpair886";
  attribute SOFT_HLUTNM of out_fifo_i_21 : label is "soft_lutpair883";
  attribute SOFT_HLUTNM of out_fifo_i_22 : label is "soft_lutpair886";
  attribute SOFT_HLUTNM of out_fifo_i_23 : label is "soft_lutpair881";
  attribute SOFT_HLUTNM of out_fifo_i_24 : label is "soft_lutpair887";
  attribute SOFT_HLUTNM of out_fifo_i_25 : label is "soft_lutpair878";
  attribute SOFT_HLUTNM of out_fifo_i_26 : label is "soft_lutpair888";
  attribute SOFT_HLUTNM of \out_fifo_i_27__9\ : label is "soft_lutpair867";
  attribute SOFT_HLUTNM of \out_fifo_i_29__9\ : label is "soft_lutpair875";
  attribute SOFT_HLUTNM of \out_fifo_i_2__6\ : label is "soft_lutpair880";
  attribute SOFT_HLUTNM of \out_fifo_i_30__0\ : label is "soft_lutpair883";
  attribute SOFT_HLUTNM of \out_fifo_i_31__9\ : label is "soft_lutpair867";
  attribute SOFT_HLUTNM of \out_fifo_i_33__9\ : label is "soft_lutpair870";
  attribute SOFT_HLUTNM of \out_fifo_i_34__0\ : label is "soft_lutpair885";
  attribute SOFT_HLUTNM of \out_fifo_i_35__9\ : label is "soft_lutpair871";
  attribute SOFT_HLUTNM of \out_fifo_i_37__9\ : label is "soft_lutpair872";
  attribute SOFT_HLUTNM of \out_fifo_i_38__0\ : label is "soft_lutpair888";
  attribute SOFT_HLUTNM of \out_fifo_i_39__9\ : label is "soft_lutpair874";
  attribute SOFT_HLUTNM of \out_fifo_i_3__6\ : label is "soft_lutpair872";
  attribute SOFT_HLUTNM of \out_fifo_i_41__9\ : label is "soft_lutpair873";
  attribute SOFT_HLUTNM of \out_fifo_i_42__0\ : label is "soft_lutpair887";
  attribute SOFT_HLUTNM of \out_fifo_i_43__0\ : label is "soft_lutpair884";
  attribute SOFT_HLUTNM of \out_fifo_i_44__0\ : label is "soft_lutpair885";
  attribute SOFT_HLUTNM of \out_fifo_i_45__0\ : label is "soft_lutpair882";
  attribute SOFT_HLUTNM of \out_fifo_i_4__6\ : label is "soft_lutpair881";
  attribute SOFT_HLUTNM of \out_fifo_i_5__6\ : label is "soft_lutpair874";
  attribute SOFT_HLUTNM of \out_fifo_i_6__6\ : label is "soft_lutpair878";
  attribute SOFT_HLUTNM of \out_fifo_i_7__6\ : label is "soft_lutpair870";
  attribute SOFT_HLUTNM of \out_fifo_i_8__6\ : label is "soft_lutpair879";
  attribute SOFT_HLUTNM of \out_fifo_i_9__6\ : label is "soft_lutpair871";
  attribute SOFT_HLUTNM of \rd_ptr[0]_i_2\ : label is "soft_lutpair876";
  attribute SOFT_HLUTNM of \rd_ptr[1]_i_1\ : label is "soft_lutpair876";
  attribute SOFT_HLUTNM of \rd_ptr[2]_i_1\ : label is "soft_lutpair869";
  attribute SOFT_HLUTNM of \rd_ptr[3]_i_1\ : label is "soft_lutpair869";
  attribute syn_maxfan of \rd_ptr_reg[0]\ : label is "10";
  attribute syn_maxfan of \rd_ptr_reg[1]\ : label is "10";
  attribute syn_maxfan of \rd_ptr_reg[2]\ : label is "10";
  attribute syn_maxfan of \rd_ptr_reg[3]\ : label is "10";
  attribute KEEP : string;
  attribute KEEP of \rd_ptr_timing_reg[0]\ : label is "yes";
  attribute KEEP of \rd_ptr_timing_reg[1]\ : label is "yes";
  attribute KEEP of \rd_ptr_timing_reg[2]\ : label is "yes";
  attribute KEEP of \rd_ptr_timing_reg[3]\ : label is "yes";
  attribute SOFT_HLUTNM of \wr_ptr[0]_i_1__16\ : label is "soft_lutpair877";
  attribute SOFT_HLUTNM of \wr_ptr[1]_i_1__16\ : label is "soft_lutpair877";
  attribute SOFT_HLUTNM of \wr_ptr[2]_i_1__8\ : label is "soft_lutpair868";
  attribute SOFT_HLUTNM of \wr_ptr[3]_i_1__8\ : label is "soft_lutpair868";
  attribute syn_maxfan of \wr_ptr_reg[0]\ : label is "10";
  attribute syn_maxfan of \wr_ptr_reg[1]\ : label is "10";
  attribute syn_maxfan of \wr_ptr_reg[2]\ : label is "10";
  attribute syn_maxfan of \wr_ptr_reg[3]\ : label is "10";
  attribute KEEP of \wr_ptr_timing_reg[0]\ : label is "yes";
  attribute KEEP of \wr_ptr_timing_reg[1]\ : label is "yes";
  attribute KEEP of \wr_ptr_timing_reg[2]\ : label is "yes";
  attribute KEEP of \wr_ptr_timing_reg[3]\ : label is "yes";
begin
  \my_empty_reg[1]_0\ <= \^my_empty_reg[1]_0\;
mem_reg_0_15_12_17: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4) => '0',
      ADDRA(3 downto 0) => rd_ptr(3 downto 0),
      ADDRB(4) => '0',
      ADDRB(3 downto 0) => rd_ptr(3 downto 0),
      ADDRC(4) => '0',
      ADDRC(3 downto 0) => rd_ptr(3 downto 0),
      ADDRD(4) => '0',
      ADDRD(3 downto 0) => wr_ptr(3 downto 0),
      DIA(1 downto 0) => B"00",
      DIB(1 downto 0) => B"00",
      DIC(1) => \out_fifo_i_47__8\(0),
      DIC(0) => \out_fifo_i_47__8\(0),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => mem_out_0(13 downto 12),
      DOB(1 downto 0) => mem_out_0(15 downto 14),
      DOC(1 downto 0) => mem_out(1 downto 0),
      DOD(1 downto 0) => NLW_mem_reg_0_15_12_17_DOD_UNCONNECTED(1 downto 0),
      WCLK => \my_full_reg[3]_0\,
      WE => wr_en
    );
mem_reg_0_15_18_23: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4) => '0',
      ADDRA(3 downto 0) => rd_ptr(3 downto 0),
      ADDRB(4) => '0',
      ADDRB(3 downto 0) => rd_ptr(3 downto 0),
      ADDRC(4) => '0',
      ADDRC(3 downto 0) => rd_ptr(3 downto 0),
      ADDRD(4) => '0',
      ADDRD(3 downto 0) => wr_ptr(3 downto 0),
      DIA(1) => \out_fifo_i_47__8\(0),
      DIA(0) => \out_fifo_i_47__8\(0),
      DIB(1 downto 0) => B"00",
      DIC(1 downto 0) => B"00",
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => mem_out(3 downto 2),
      DOB(1 downto 0) => mem_out_0(21 downto 20),
      DOC(1 downto 0) => mem_out_0(23 downto 22),
      DOD(1 downto 0) => NLW_mem_reg_0_15_18_23_DOD_UNCONNECTED(1 downto 0),
      WCLK => \my_full_reg[3]_0\,
      WE => wr_en
    );
mem_reg_0_15_30_35: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4) => '0',
      ADDRA(3 downto 0) => rd_ptr(3 downto 0),
      ADDRB(4) => '0',
      ADDRB(3 downto 0) => rd_ptr(3 downto 0),
      ADDRC(4) => '0',
      ADDRC(3 downto 0) => rd_ptr(3 downto 0),
      ADDRD(4) => '0',
      ADDRD(3 downto 0) => wr_ptr(3 downto 0),
      DIA(1 downto 0) => B"00",
      DIB(1 downto 0) => \out_fifo_i_47__8\(2 downto 1),
      DIC(1) => '1',
      DIC(0) => \out_fifo_i_47__8\(8),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => mem_out_0(31 downto 30),
      DOB(1) => mem_out(4),
      DOB(0) => mem_out_0(32),
      DOC(1 downto 0) => mem_out_0(35 downto 34),
      DOD(1 downto 0) => NLW_mem_reg_0_15_30_35_DOD_UNCONNECTED(1 downto 0),
      WCLK => \my_full_reg[3]_0\,
      WE => wr_en
    );
mem_reg_0_15_36_41: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4) => '0',
      ADDRA(3 downto 0) => rd_ptr(3 downto 0),
      ADDRB(4) => '0',
      ADDRB(3 downto 0) => rd_ptr(3 downto 0),
      ADDRC(4) => '0',
      ADDRC(3 downto 0) => rd_ptr(3 downto 0),
      ADDRD(4) => '0',
      ADDRD(3 downto 0) => wr_ptr(3 downto 0),
      DIA(1 downto 0) => B"00",
      DIB(1 downto 0) => B"00",
      DIC(1 downto 0) => \out_fifo_i_47__8\(4 downto 3),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => mem_out_0(37 downto 36),
      DOB(1 downto 0) => mem_out_0(39 downto 38),
      DOC(1) => mem_out(5),
      DOC(0) => mem_out_0(40),
      DOD(1 downto 0) => NLW_mem_reg_0_15_36_41_DOD_UNCONNECTED(1 downto 0),
      WCLK => \my_full_reg[3]_0\,
      WE => wr_en
    );
mem_reg_0_15_42_47: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4) => '0',
      ADDRA(3 downto 0) => rd_ptr(3 downto 0),
      ADDRB(4) => '0',
      ADDRB(3 downto 0) => rd_ptr(3 downto 0),
      ADDRC(4) => '0',
      ADDRC(3 downto 0) => rd_ptr(3 downto 0),
      ADDRD(4) => '0',
      ADDRD(3 downto 0) => wr_ptr(3 downto 0),
      DIA(1) => '1',
      DIA(0) => \out_fifo_i_47__8\(5),
      DIB(1 downto 0) => \out_fifo_i_47__8\(7 downto 6),
      DIC(1) => '1',
      DIC(0) => \out_fifo_i_47__8\(8),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => mem_out_0(43 downto 42),
      DOB(1) => mem_out(6),
      DOB(0) => mem_out_0(44),
      DOC(1 downto 0) => mem_out_0(47 downto 46),
      DOD(1 downto 0) => NLW_mem_reg_0_15_42_47_DOD_UNCONNECTED(1 downto 0),
      WCLK => \my_full_reg[3]_0\,
      WE => wr_en
    );
mem_reg_0_15_48_53: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4) => '0',
      ADDRA(3 downto 0) => rd_ptr(3 downto 0),
      ADDRB(4) => '0',
      ADDRB(3 downto 0) => rd_ptr(3 downto 0),
      ADDRC(4) => '0',
      ADDRC(3 downto 0) => rd_ptr(3 downto 0),
      ADDRD(4) => '0',
      ADDRD(3 downto 0) => wr_ptr(3 downto 0),
      DIA(1 downto 0) => B"00",
      DIB(1 downto 0) => B"00",
      DIC(1 downto 0) => \out_fifo_i_47__8\(10 downto 9),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => mem_out_0(49 downto 48),
      DOB(1 downto 0) => mem_out_0(51 downto 50),
      DOC(1) => mem_out(7),
      DOC(0) => mem_out_0(52),
      DOD(1 downto 0) => NLW_mem_reg_0_15_48_53_DOD_UNCONNECTED(1 downto 0),
      WCLK => \my_full_reg[3]_0\,
      WE => wr_en
    );
mem_reg_0_15_54_59: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4) => '0',
      ADDRA(3 downto 0) => rd_ptr(3 downto 0),
      ADDRB(4) => '0',
      ADDRB(3 downto 0) => rd_ptr(3 downto 0),
      ADDRC(4) => '0',
      ADDRC(3 downto 0) => rd_ptr(3 downto 0),
      ADDRD(4) => '0',
      ADDRD(3 downto 0) => wr_ptr(3 downto 0),
      DIA(1) => '1',
      DIA(0) => \out_fifo_i_47__8\(11),
      DIB(1) => \out_fifo_i_47__8\(12),
      DIB(0) => \out_fifo_i_47__8\(12),
      DIC(1) => \out_fifo_i_47__8\(12),
      DIC(0) => \out_fifo_i_47__8\(12),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => mem_out_0(55 downto 54),
      DOB(1 downto 0) => mem_out(9 downto 8),
      DOC(1 downto 0) => mem_out(11 downto 10),
      DOD(1 downto 0) => NLW_mem_reg_0_15_54_59_DOD_UNCONNECTED(1 downto 0),
      WCLK => \my_full_reg[3]_0\,
      WE => wr_en
    );
mem_reg_0_15_6_11: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4) => '0',
      ADDRA(3 downto 0) => rd_ptr(3 downto 0),
      ADDRB(4) => '0',
      ADDRB(3 downto 0) => rd_ptr(3 downto 0),
      ADDRC(4) => '0',
      ADDRC(3 downto 0) => rd_ptr(3 downto 0),
      ADDRD(4) => '0',
      ADDRD(3 downto 0) => wr_ptr(3 downto 0),
      DIA(1 downto 0) => B"00",
      DIB(1 downto 0) => B"00",
      DIC(1 downto 0) => B"00",
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => mem_out_0(7 downto 6),
      DOB(1 downto 0) => mem_out_0(3 downto 2),
      DOC(1 downto 0) => mem_out_0(5 downto 4),
      DOD(1 downto 0) => NLW_mem_reg_0_15_6_11_DOD_UNCONNECTED(1 downto 0),
      WCLK => \my_full_reg[3]_0\,
      WE => wr_en
    );
\my_empty[1]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"C0CCCCCE"
    )
        port map (
      I0 => my_empty0,
      I1 => \^my_empty_reg[1]_0\,
      I2 => \my_full_reg_n_0_[3]\,
      I3 => phy_cmd_wr_en,
      I4 => B_of_full,
      O => \my_empty[1]_i_1_n_0\
    );
\my_empty[6]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"C0CCCCCE"
    )
        port map (
      I0 => my_empty0,
      I1 => \my_empty_reg_n_0_[6]\,
      I2 => \my_full_reg_n_0_[3]\,
      I3 => phy_cmd_wr_en,
      I4 => B_of_full,
      O => \my_empty[6]_i_1_n_0\
    );
\my_empty[6]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"4A400D08"
    )
        port map (
      I0 => wr_ptr_timing(2),
      I1 => \my_empty[6]_i_3_n_0\,
      I2 => wr_ptr_timing(3),
      I3 => \my_empty[6]_i_4_n_0\,
      I4 => rd_ptr(2),
      O => my_empty0
    );
\my_empty[6]_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000040"
    )
        port map (
      I0 => wr_ptr_timing(1),
      I1 => rd_ptr(0),
      I2 => rd_ptr(1),
      I3 => rd_ptr(3),
      I4 => wr_ptr_timing(0),
      O => \my_empty[6]_i_3_n_0\
    );
\my_empty[6]_i_4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"84210842"
    )
        port map (
      I0 => wr_ptr_timing(0),
      I1 => wr_ptr_timing(1),
      I2 => rd_ptr(0),
      I3 => rd_ptr(1),
      I4 => rd_ptr(3),
      O => \my_empty[6]_i_4_n_0\
    );
\my_empty_reg[1]\: unisim.vcomponents.FDSE
     port map (
      C => \my_full_reg[3]_0\,
      CE => '1',
      D => \my_empty[1]_i_1_n_0\,
      Q => \^my_empty_reg[1]_0\,
      S => SR(0)
    );
\my_empty_reg[6]\: unisim.vcomponents.FDSE
     port map (
      C => \my_full_reg[3]_0\,
      CE => '1',
      D => \my_empty[6]_i_1_n_0\,
      Q => \my_empty_reg_n_0_[6]\,
      S => SR(0)
    );
\my_full[3]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000FFFC0080"
    )
        port map (
      I0 => my_full0,
      I1 => phy_cmd_wr_en,
      I2 => B_of_full,
      I3 => \my_empty_reg_n_0_[6]\,
      I4 => \my_full_reg_n_0_[3]\,
      I5 => SR(0),
      O => \my_full[3]_i_1_n_0\
    );
\my_full[3]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"4A400D08"
    )
        port map (
      I0 => rd_ptr_timing(2),
      I1 => \my_full[3]_i_3_n_0\,
      I2 => rd_ptr_timing(3),
      I3 => \my_full[3]_i_4_n_0\,
      I4 => wr_ptr(2),
      O => my_full0
    );
\my_full[3]_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000040"
    )
        port map (
      I0 => rd_ptr_timing(1),
      I1 => wr_ptr(0),
      I2 => wr_ptr(1),
      I3 => wr_ptr(3),
      I4 => rd_ptr_timing(0),
      O => \my_full[3]_i_3_n_0\
    );
\my_full[3]_i_4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"84210842"
    )
        port map (
      I0 => rd_ptr_timing(0),
      I1 => rd_ptr_timing(1),
      I2 => wr_ptr(0),
      I3 => wr_ptr(1),
      I4 => wr_ptr(3),
      O => \my_full[3]_i_4_n_0\
    );
\my_full_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => \my_full_reg[3]_0\,
      CE => '1',
      D => \my_full[3]_i_1_n_0\,
      Q => \my_full_reg_n_0_[3]\,
      R => '0'
    );
\out_fifo_i_10__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => mem_out_0(13),
      I1 => \^my_empty_reg[1]_0\,
      O => D1(1)
    );
\out_fifo_i_11__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => mem_out_0(12),
      I1 => \^my_empty_reg[1]_0\,
      O => D1(0)
    );
\out_fifo_i_12__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => mem_out_0(23),
      I1 => \^my_empty_reg[1]_0\,
      O => D2(3)
    );
\out_fifo_i_13__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => mem_out_0(22),
      I1 => \^my_empty_reg[1]_0\,
      O => D2(2)
    );
out_fifo_i_14: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => mem_out_0(21),
      I1 => \^my_empty_reg[1]_0\,
      O => D2(1)
    );
out_fifo_i_15: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => mem_out_0(20),
      I1 => \^my_empty_reg[1]_0\,
      O => D2(0)
    );
\out_fifo_i_1__8\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"0D"
    )
        port map (
      I0 => \^my_empty_reg[1]_0\,
      I1 => phy_cmd_wr_en,
      I2 => B_of_full,
      O => \my_empty_reg[1]_1\
    );
out_fifo_i_20: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => mem_out_0(31),
      I1 => \^my_empty_reg[1]_0\,
      O => D3(7)
    );
out_fifo_i_21: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => mem_out_0(30),
      I1 => \^my_empty_reg[1]_0\,
      O => D3(6)
    );
out_fifo_i_22: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => mem_out_0(39),
      I1 => \^my_empty_reg[1]_0\,
      O => D4(6)
    );
out_fifo_i_23: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => mem_out_0(38),
      I1 => \^my_empty_reg[1]_0\,
      O => D4(5)
    );
out_fifo_i_24: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => mem_out_0(37),
      I1 => \^my_empty_reg[1]_0\,
      O => D4(4)
    );
out_fifo_i_25: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => mem_out_0(36),
      I1 => \^my_empty_reg[1]_0\,
      O => D4(3)
    );
out_fifo_i_26: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => mem_out_0(35),
      I1 => \^my_empty_reg[1]_0\,
      O => D4(2)
    );
\out_fifo_i_27__9\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"BBF0"
    )
        port map (
      I0 => mc_ras_n(1),
      I1 => out_fifo,
      I2 => mem_out_0(34),
      I3 => \^my_empty_reg[1]_0\,
      O => D4(1)
    );
\out_fifo_i_29__9\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"BBF0"
    )
        port map (
      I0 => mc_cs_n(0),
      I1 => out_fifo,
      I2 => mem_out_0(32),
      I3 => \^my_empty_reg[1]_0\,
      O => D4(0)
    );
\out_fifo_i_2__6\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => mem_out_0(7),
      I1 => \^my_empty_reg[1]_0\,
      O => D3(1)
    );
\out_fifo_i_30__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => mem_out_0(47),
      I1 => \^my_empty_reg[1]_0\,
      O => D5(5)
    );
\out_fifo_i_31__9\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"BBF0"
    )
        port map (
      I0 => mc_ras_n(1),
      I1 => out_fifo,
      I2 => mem_out_0(46),
      I3 => \^my_empty_reg[1]_0\,
      O => D5(4)
    );
\out_fifo_i_33__9\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"BBF0"
    )
        port map (
      I0 => mc_ras_n(0),
      I1 => out_fifo,
      I2 => mem_out_0(44),
      I3 => \^my_empty_reg[1]_0\,
      O => D5(3)
    );
\out_fifo_i_34__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => mem_out_0(43),
      I1 => \^my_empty_reg[1]_0\,
      O => D5(2)
    );
\out_fifo_i_35__9\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"BBF0"
    )
        port map (
      I0 => mc_cas_n(1),
      I1 => out_fifo,
      I2 => mem_out_0(42),
      I3 => \^my_empty_reg[1]_0\,
      O => D5(1)
    );
\out_fifo_i_37__9\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"BBF0"
    )
        port map (
      I0 => mc_cas_n(0),
      I1 => out_fifo,
      I2 => mem_out_0(40),
      I3 => \^my_empty_reg[1]_0\,
      O => D5(0)
    );
\out_fifo_i_38__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => mem_out_0(55),
      I1 => \^my_empty_reg[1]_0\,
      O => D6(6)
    );
\out_fifo_i_39__9\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"BBF0"
    )
        port map (
      I0 => mc_we_n(1),
      I1 => out_fifo,
      I2 => mem_out_0(54),
      I3 => \^my_empty_reg[1]_0\,
      O => D6(5)
    );
\out_fifo_i_3__6\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => mem_out_0(6),
      I1 => \^my_empty_reg[1]_0\,
      O => D3(0)
    );
\out_fifo_i_41__9\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"BBF0"
    )
        port map (
      I0 => mc_we_n(0),
      I1 => out_fifo,
      I2 => mem_out_0(52),
      I3 => \^my_empty_reg[1]_0\,
      O => D6(4)
    );
\out_fifo_i_42__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => mem_out_0(51),
      I1 => \^my_empty_reg[1]_0\,
      O => D6(3)
    );
\out_fifo_i_43__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => mem_out_0(50),
      I1 => \^my_empty_reg[1]_0\,
      O => D6(2)
    );
\out_fifo_i_44__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => mem_out_0(49),
      I1 => \^my_empty_reg[1]_0\,
      O => D6(1)
    );
\out_fifo_i_45__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => mem_out_0(48),
      I1 => \^my_empty_reg[1]_0\,
      O => D6(0)
    );
\out_fifo_i_4__6\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => mem_out_0(5),
      I1 => \^my_empty_reg[1]_0\,
      O => D3(5)
    );
\out_fifo_i_5__6\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => mem_out_0(4),
      I1 => \^my_empty_reg[1]_0\,
      O => D3(4)
    );
\out_fifo_i_6__6\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => mem_out_0(3),
      I1 => \^my_empty_reg[1]_0\,
      O => D3(3)
    );
\out_fifo_i_7__6\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => mem_out_0(2),
      I1 => \^my_empty_reg[1]_0\,
      O => D3(2)
    );
\out_fifo_i_8__6\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => mem_out_0(15),
      I1 => \^my_empty_reg[1]_0\,
      O => D1(3)
    );
\out_fifo_i_9__6\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => mem_out_0(14),
      I1 => \^my_empty_reg[1]_0\,
      O => D1(2)
    );
p_17_out: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2700"
    )
        port map (
      I0 => B_of_full,
      I1 => \my_full_reg_n_0_[3]\,
      I2 => \^my_empty_reg[1]_0\,
      I3 => phy_cmd_wr_en,
      O => wr_en
    );
\rd_ptr[0]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => B_of_full,
      I1 => \my_empty_reg_n_0_[6]\,
      O => \rd_ptr[0]_i_1_n_0\
    );
\rd_ptr[0]_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => rd_ptr(3),
      I1 => rd_ptr(0),
      O => nxt_rd_ptr(0)
    );
\rd_ptr[1]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B4"
    )
        port map (
      I0 => rd_ptr(3),
      I1 => rd_ptr(0),
      I2 => rd_ptr(1),
      O => nxt_rd_ptr(1)
    );
\rd_ptr[2]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"AA6A"
    )
        port map (
      I0 => rd_ptr(2),
      I1 => rd_ptr(0),
      I2 => rd_ptr(1),
      I3 => rd_ptr(3),
      O => nxt_rd_ptr(2)
    );
\rd_ptr[3]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4000"
    )
        port map (
      I0 => rd_ptr(3),
      I1 => rd_ptr(1),
      I2 => rd_ptr(0),
      I3 => rd_ptr(2),
      O => nxt_rd_ptr(3)
    );
\rd_ptr_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \my_full_reg[3]_0\,
      CE => \rd_ptr[0]_i_1_n_0\,
      D => nxt_rd_ptr(0),
      Q => rd_ptr(0),
      R => SR(0)
    );
\rd_ptr_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \my_full_reg[3]_0\,
      CE => \rd_ptr[0]_i_1_n_0\,
      D => nxt_rd_ptr(1),
      Q => rd_ptr(1),
      R => SR(0)
    );
\rd_ptr_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \my_full_reg[3]_0\,
      CE => \rd_ptr[0]_i_1_n_0\,
      D => nxt_rd_ptr(2),
      Q => rd_ptr(2),
      R => SR(0)
    );
\rd_ptr_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => \my_full_reg[3]_0\,
      CE => \rd_ptr[0]_i_1_n_0\,
      D => nxt_rd_ptr(3),
      Q => rd_ptr(3),
      R => SR(0)
    );
\rd_ptr_timing_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \my_full_reg[3]_0\,
      CE => \rd_ptr[0]_i_1_n_0\,
      D => nxt_rd_ptr(0),
      Q => rd_ptr_timing(0),
      R => SR(0)
    );
\rd_ptr_timing_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \my_full_reg[3]_0\,
      CE => \rd_ptr[0]_i_1_n_0\,
      D => nxt_rd_ptr(1),
      Q => rd_ptr_timing(1),
      R => SR(0)
    );
\rd_ptr_timing_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \my_full_reg[3]_0\,
      CE => \rd_ptr[0]_i_1_n_0\,
      D => nxt_rd_ptr(2),
      Q => rd_ptr_timing(2),
      R => SR(0)
    );
\rd_ptr_timing_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => \my_full_reg[3]_0\,
      CE => \rd_ptr[0]_i_1_n_0\,
      D => nxt_rd_ptr(3),
      Q => rd_ptr_timing(3),
      R => SR(0)
    );
wr_ptr0: unisim.vcomponents.LUT4
    generic map(
      INIT => X"082A"
    )
        port map (
      I0 => phy_cmd_wr_en,
      I1 => B_of_full,
      I2 => \my_full_reg_n_0_[3]\,
      I3 => \my_empty_reg_n_0_[6]\,
      O => \wr_ptr0__0\
    );
\wr_ptr[0]_i_1__16\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => wr_ptr(3),
      I1 => wr_ptr(0),
      O => nxt_wr_ptr(0)
    );
\wr_ptr[1]_i_1__16\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B4"
    )
        port map (
      I0 => wr_ptr(3),
      I1 => wr_ptr(0),
      I2 => wr_ptr(1),
      O => nxt_wr_ptr(1)
    );
\wr_ptr[2]_i_1__8\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"AA6A"
    )
        port map (
      I0 => wr_ptr(2),
      I1 => wr_ptr(0),
      I2 => wr_ptr(1),
      I3 => wr_ptr(3),
      O => nxt_wr_ptr(2)
    );
\wr_ptr[3]_i_1__8\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4000"
    )
        port map (
      I0 => wr_ptr(3),
      I1 => wr_ptr(1),
      I2 => wr_ptr(0),
      I3 => wr_ptr(2),
      O => nxt_wr_ptr(3)
    );
\wr_ptr_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \my_full_reg[3]_0\,
      CE => \wr_ptr0__0\,
      D => nxt_wr_ptr(0),
      Q => wr_ptr(0),
      R => SR(0)
    );
\wr_ptr_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \my_full_reg[3]_0\,
      CE => \wr_ptr0__0\,
      D => nxt_wr_ptr(1),
      Q => wr_ptr(1),
      R => SR(0)
    );
\wr_ptr_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \my_full_reg[3]_0\,
      CE => \wr_ptr0__0\,
      D => nxt_wr_ptr(2),
      Q => wr_ptr(2),
      R => SR(0)
    );
\wr_ptr_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => \my_full_reg[3]_0\,
      CE => \wr_ptr0__0\,
      D => nxt_wr_ptr(3),
      Q => wr_ptr(3),
      R => SR(0)
    );
\wr_ptr_timing_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \my_full_reg[3]_0\,
      CE => \wr_ptr0__0\,
      D => nxt_wr_ptr(0),
      Q => wr_ptr_timing(0),
      R => SR(0)
    );
\wr_ptr_timing_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \my_full_reg[3]_0\,
      CE => \wr_ptr0__0\,
      D => nxt_wr_ptr(1),
      Q => wr_ptr_timing(1),
      R => SR(0)
    );
\wr_ptr_timing_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \my_full_reg[3]_0\,
      CE => \wr_ptr0__0\,
      D => nxt_wr_ptr(2),
      Q => wr_ptr_timing(2),
      R => SR(0)
    );
\wr_ptr_timing_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => \my_full_reg[3]_0\,
      CE => \wr_ptr0__0\,
      D => nxt_wr_ptr(3),
      Q => wr_ptr_timing(3),
      R => SR(0)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \mig_mig_7series_v4_2_ddr_of_pre_fifo__parameterized1_31\ is
  port (
    \my_empty_reg[1]_0\ : out STD_LOGIC;
    \my_empty_reg[1]_1\ : out STD_LOGIC;
    D0 : out STD_LOGIC_VECTOR ( 7 downto 0 );
    D1 : out STD_LOGIC_VECTOR ( 7 downto 0 );
    \rd_ptr_reg[3]_0\ : out STD_LOGIC_VECTOR ( 63 downto 0 );
    Q : out STD_LOGIC_VECTOR ( 2 downto 0 );
    ofifo_rst : in STD_LOGIC;
    \entry_cnt_reg[4]_0\ : in STD_LOGIC;
    \my_empty_reg[7]_0\ : in STD_LOGIC;
    phy_data_wr_en : in STD_LOGIC;
    out_fifo : in STD_LOGIC;
    out_fifo_0 : in STD_LOGIC_VECTOR ( 7 downto 0 );
    out_fifo_1 : in STD_LOGIC;
    \out_fifo_i_75__7\ : in STD_LOGIC_VECTOR ( 71 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \mig_mig_7series_v4_2_ddr_of_pre_fifo__parameterized1_31\ : entity is "mig_7series_v4_2_ddr_of_pre_fifo";
end \mig_mig_7series_v4_2_ddr_of_pre_fifo__parameterized1_31\;

architecture STRUCTURE of \mig_mig_7series_v4_2_ddr_of_pre_fifo__parameterized1_31\ is
  signal \^q\ : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal \entry_cnt10_out__0\ : STD_LOGIC;
  signal \entry_cnt[0]_i_1__2_n_0\ : STD_LOGIC;
  signal \entry_cnt[1]_i_1__2_n_0\ : STD_LOGIC;
  signal \entry_cnt[2]_i_1__2_n_0\ : STD_LOGIC;
  signal \entry_cnt[3]_i_1__2_n_0\ : STD_LOGIC;
  signal \entry_cnt[4]_i_1__2_n_0\ : STD_LOGIC;
  signal \entry_cnt[4]_i_2__2_n_0\ : STD_LOGIC;
  signal \entry_cnt_reg_n_0_[0]\ : STD_LOGIC;
  signal \entry_cnt_reg_n_0_[1]\ : STD_LOGIC;
  signal mem_reg_0_15_0_5_n_0 : STD_LOGIC;
  signal mem_reg_0_15_0_5_n_1 : STD_LOGIC;
  signal mem_reg_0_15_0_5_n_2 : STD_LOGIC;
  signal mem_reg_0_15_0_5_n_3 : STD_LOGIC;
  signal mem_reg_0_15_0_5_n_4 : STD_LOGIC;
  signal mem_reg_0_15_0_5_n_5 : STD_LOGIC;
  signal mem_reg_0_15_12_17_n_0 : STD_LOGIC;
  signal mem_reg_0_15_12_17_n_1 : STD_LOGIC;
  signal mem_reg_0_15_12_17_n_2 : STD_LOGIC;
  signal mem_reg_0_15_12_17_n_3 : STD_LOGIC;
  signal mem_reg_0_15_6_11_n_0 : STD_LOGIC;
  signal mem_reg_0_15_6_11_n_1 : STD_LOGIC;
  signal mem_reg_0_15_6_11_n_2 : STD_LOGIC;
  signal mem_reg_0_15_6_11_n_3 : STD_LOGIC;
  signal mem_reg_0_15_6_11_n_4 : STD_LOGIC;
  signal mem_reg_0_15_6_11_n_5 : STD_LOGIC;
  signal my_empty0 : STD_LOGIC;
  signal \my_empty[1]_i_1__3_n_0\ : STD_LOGIC;
  signal \my_empty[7]_i_1__3_n_0\ : STD_LOGIC;
  signal \my_empty[7]_i_3__3_n_0\ : STD_LOGIC;
  signal \my_empty[7]_i_4__3_n_0\ : STD_LOGIC;
  signal \^my_empty_reg[1]_1\ : STD_LOGIC;
  signal \my_empty_reg_n_0_[7]\ : STD_LOGIC;
  signal my_full0 : STD_LOGIC;
  signal \my_full[4]_i_1__3_n_0\ : STD_LOGIC;
  signal \my_full[4]_i_3__3_n_0\ : STD_LOGIC;
  signal \my_full[4]_i_4__3_n_0\ : STD_LOGIC;
  signal \my_full_reg_n_0_[4]\ : STD_LOGIC;
  signal nxt_rd_ptr : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal nxt_wr_ptr : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \rd_ptr_reg_n_0_[0]\ : STD_LOGIC;
  signal \rd_ptr_reg_n_0_[1]\ : STD_LOGIC;
  signal \rd_ptr_reg_n_0_[2]\ : STD_LOGIC;
  signal \rd_ptr_reg_n_0_[3]\ : STD_LOGIC;
  signal rd_ptr_timing : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \rd_ptr_timing[3]_i_1__3_n_0\ : STD_LOGIC;
  signal wr_en : STD_LOGIC;
  attribute MAX_FANOUT : string;
  attribute MAX_FANOUT of wr_en : signal is "50";
  attribute RTL_MAX_FANOUT : string;
  attribute RTL_MAX_FANOUT of wr_en : signal is "found";
  signal wr_ptr : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal wr_ptr0 : STD_LOGIC;
  signal wr_ptr_timing : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal NLW_mem_reg_0_15_0_5_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_15_12_17_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_15_18_23_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_15_24_29_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_15_30_35_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_15_36_41_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_15_42_47_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_15_48_53_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_15_54_59_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_15_60_65_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_15_66_71_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_15_6_11_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_15_72_77_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_15_78_79_DOB_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_15_78_79_DOC_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_15_78_79_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \entry_cnt[0]_i_1__2\ : label is "soft_lutpair849";
  attribute SOFT_HLUTNM of \entry_cnt[1]_i_1__2\ : label is "soft_lutpair848";
  attribute SOFT_HLUTNM of \entry_cnt[3]_i_1__2\ : label is "soft_lutpair849";
  attribute SOFT_HLUTNM of \entry_cnt[4]_i_3__2\ : label is "soft_lutpair848";
  attribute METHODOLOGY_DRC_VIOS : string;
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_15_0_5 : label is "";
  attribute RTL_RAM_BITS : integer;
  attribute RTL_RAM_BITS of mem_reg_0_15_0_5 : label is 720;
  attribute RTL_RAM_NAME : string;
  attribute RTL_RAM_NAME of mem_reg_0_15_0_5 : label is "of_pre_fifo_gen.u_ddr_of_pre_fifo/mem";
  attribute ram_addr_begin : integer;
  attribute ram_addr_begin of mem_reg_0_15_0_5 : label is 0;
  attribute ram_addr_end : integer;
  attribute ram_addr_end of mem_reg_0_15_0_5 : label is 8;
  attribute ram_offset : integer;
  attribute ram_offset of mem_reg_0_15_0_5 : label is 0;
  attribute ram_slice_begin : integer;
  attribute ram_slice_begin of mem_reg_0_15_0_5 : label is 0;
  attribute ram_slice_end : integer;
  attribute ram_slice_end of mem_reg_0_15_0_5 : label is 5;
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_15_12_17 : label is "";
  attribute RTL_RAM_BITS of mem_reg_0_15_12_17 : label is 720;
  attribute RTL_RAM_NAME of mem_reg_0_15_12_17 : label is "of_pre_fifo_gen.u_ddr_of_pre_fifo/mem";
  attribute ram_addr_begin of mem_reg_0_15_12_17 : label is 0;
  attribute ram_addr_end of mem_reg_0_15_12_17 : label is 8;
  attribute ram_offset of mem_reg_0_15_12_17 : label is 0;
  attribute ram_slice_begin of mem_reg_0_15_12_17 : label is 12;
  attribute ram_slice_end of mem_reg_0_15_12_17 : label is 17;
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_15_18_23 : label is "";
  attribute RTL_RAM_BITS of mem_reg_0_15_18_23 : label is 720;
  attribute RTL_RAM_NAME of mem_reg_0_15_18_23 : label is "of_pre_fifo_gen.u_ddr_of_pre_fifo/mem";
  attribute ram_addr_begin of mem_reg_0_15_18_23 : label is 0;
  attribute ram_addr_end of mem_reg_0_15_18_23 : label is 8;
  attribute ram_offset of mem_reg_0_15_18_23 : label is 0;
  attribute ram_slice_begin of mem_reg_0_15_18_23 : label is 18;
  attribute ram_slice_end of mem_reg_0_15_18_23 : label is 23;
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_15_24_29 : label is "";
  attribute RTL_RAM_BITS of mem_reg_0_15_24_29 : label is 720;
  attribute RTL_RAM_NAME of mem_reg_0_15_24_29 : label is "of_pre_fifo_gen.u_ddr_of_pre_fifo/mem";
  attribute ram_addr_begin of mem_reg_0_15_24_29 : label is 0;
  attribute ram_addr_end of mem_reg_0_15_24_29 : label is 8;
  attribute ram_offset of mem_reg_0_15_24_29 : label is 0;
  attribute ram_slice_begin of mem_reg_0_15_24_29 : label is 24;
  attribute ram_slice_end of mem_reg_0_15_24_29 : label is 29;
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_15_30_35 : label is "";
  attribute RTL_RAM_BITS of mem_reg_0_15_30_35 : label is 720;
  attribute RTL_RAM_NAME of mem_reg_0_15_30_35 : label is "of_pre_fifo_gen.u_ddr_of_pre_fifo/mem";
  attribute ram_addr_begin of mem_reg_0_15_30_35 : label is 0;
  attribute ram_addr_end of mem_reg_0_15_30_35 : label is 8;
  attribute ram_offset of mem_reg_0_15_30_35 : label is 0;
  attribute ram_slice_begin of mem_reg_0_15_30_35 : label is 30;
  attribute ram_slice_end of mem_reg_0_15_30_35 : label is 35;
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_15_36_41 : label is "";
  attribute RTL_RAM_BITS of mem_reg_0_15_36_41 : label is 720;
  attribute RTL_RAM_NAME of mem_reg_0_15_36_41 : label is "of_pre_fifo_gen.u_ddr_of_pre_fifo/mem";
  attribute ram_addr_begin of mem_reg_0_15_36_41 : label is 0;
  attribute ram_addr_end of mem_reg_0_15_36_41 : label is 8;
  attribute ram_offset of mem_reg_0_15_36_41 : label is 0;
  attribute ram_slice_begin of mem_reg_0_15_36_41 : label is 36;
  attribute ram_slice_end of mem_reg_0_15_36_41 : label is 41;
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_15_42_47 : label is "";
  attribute RTL_RAM_BITS of mem_reg_0_15_42_47 : label is 720;
  attribute RTL_RAM_NAME of mem_reg_0_15_42_47 : label is "of_pre_fifo_gen.u_ddr_of_pre_fifo/mem";
  attribute ram_addr_begin of mem_reg_0_15_42_47 : label is 0;
  attribute ram_addr_end of mem_reg_0_15_42_47 : label is 8;
  attribute ram_offset of mem_reg_0_15_42_47 : label is 0;
  attribute ram_slice_begin of mem_reg_0_15_42_47 : label is 42;
  attribute ram_slice_end of mem_reg_0_15_42_47 : label is 47;
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_15_48_53 : label is "";
  attribute RTL_RAM_BITS of mem_reg_0_15_48_53 : label is 720;
  attribute RTL_RAM_NAME of mem_reg_0_15_48_53 : label is "of_pre_fifo_gen.u_ddr_of_pre_fifo/mem";
  attribute ram_addr_begin of mem_reg_0_15_48_53 : label is 0;
  attribute ram_addr_end of mem_reg_0_15_48_53 : label is 8;
  attribute ram_offset of mem_reg_0_15_48_53 : label is 0;
  attribute ram_slice_begin of mem_reg_0_15_48_53 : label is 48;
  attribute ram_slice_end of mem_reg_0_15_48_53 : label is 53;
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_15_54_59 : label is "";
  attribute RTL_RAM_BITS of mem_reg_0_15_54_59 : label is 720;
  attribute RTL_RAM_NAME of mem_reg_0_15_54_59 : label is "of_pre_fifo_gen.u_ddr_of_pre_fifo/mem";
  attribute ram_addr_begin of mem_reg_0_15_54_59 : label is 0;
  attribute ram_addr_end of mem_reg_0_15_54_59 : label is 8;
  attribute ram_offset of mem_reg_0_15_54_59 : label is 0;
  attribute ram_slice_begin of mem_reg_0_15_54_59 : label is 54;
  attribute ram_slice_end of mem_reg_0_15_54_59 : label is 59;
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_15_60_65 : label is "";
  attribute RTL_RAM_BITS of mem_reg_0_15_60_65 : label is 720;
  attribute RTL_RAM_NAME of mem_reg_0_15_60_65 : label is "of_pre_fifo_gen.u_ddr_of_pre_fifo/mem";
  attribute ram_addr_begin of mem_reg_0_15_60_65 : label is 0;
  attribute ram_addr_end of mem_reg_0_15_60_65 : label is 8;
  attribute ram_offset of mem_reg_0_15_60_65 : label is 0;
  attribute ram_slice_begin of mem_reg_0_15_60_65 : label is 60;
  attribute ram_slice_end of mem_reg_0_15_60_65 : label is 65;
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_15_66_71 : label is "";
  attribute RTL_RAM_BITS of mem_reg_0_15_66_71 : label is 720;
  attribute RTL_RAM_NAME of mem_reg_0_15_66_71 : label is "of_pre_fifo_gen.u_ddr_of_pre_fifo/mem";
  attribute ram_addr_begin of mem_reg_0_15_66_71 : label is 0;
  attribute ram_addr_end of mem_reg_0_15_66_71 : label is 8;
  attribute ram_offset of mem_reg_0_15_66_71 : label is 0;
  attribute ram_slice_begin of mem_reg_0_15_66_71 : label is 66;
  attribute ram_slice_end of mem_reg_0_15_66_71 : label is 71;
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_15_6_11 : label is "";
  attribute RTL_RAM_BITS of mem_reg_0_15_6_11 : label is 720;
  attribute RTL_RAM_NAME of mem_reg_0_15_6_11 : label is "of_pre_fifo_gen.u_ddr_of_pre_fifo/mem";
  attribute ram_addr_begin of mem_reg_0_15_6_11 : label is 0;
  attribute ram_addr_end of mem_reg_0_15_6_11 : label is 8;
  attribute ram_offset of mem_reg_0_15_6_11 : label is 0;
  attribute ram_slice_begin of mem_reg_0_15_6_11 : label is 6;
  attribute ram_slice_end of mem_reg_0_15_6_11 : label is 11;
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_15_72_77 : label is "";
  attribute RTL_RAM_BITS of mem_reg_0_15_72_77 : label is 720;
  attribute RTL_RAM_NAME of mem_reg_0_15_72_77 : label is "of_pre_fifo_gen.u_ddr_of_pre_fifo/mem";
  attribute ram_addr_begin of mem_reg_0_15_72_77 : label is 0;
  attribute ram_addr_end of mem_reg_0_15_72_77 : label is 8;
  attribute ram_offset of mem_reg_0_15_72_77 : label is 0;
  attribute ram_slice_begin of mem_reg_0_15_72_77 : label is 72;
  attribute ram_slice_end of mem_reg_0_15_72_77 : label is 77;
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_15_78_79 : label is "";
  attribute RTL_RAM_BITS of mem_reg_0_15_78_79 : label is 720;
  attribute RTL_RAM_NAME of mem_reg_0_15_78_79 : label is "of_pre_fifo_gen.u_ddr_of_pre_fifo/mem";
  attribute ram_addr_begin of mem_reg_0_15_78_79 : label is 0;
  attribute ram_addr_end of mem_reg_0_15_78_79 : label is 8;
  attribute ram_offset of mem_reg_0_15_78_79 : label is 0;
  attribute ram_slice_begin of mem_reg_0_15_78_79 : label is 78;
  attribute ram_slice_end of mem_reg_0_15_78_79 : label is 79;
  attribute SOFT_HLUTNM of \my_empty[7]_i_3__3\ : label is "soft_lutpair851";
  attribute SOFT_HLUTNM of \my_empty[7]_i_4__3\ : label is "soft_lutpair851";
  attribute syn_maxfan : string;
  attribute syn_maxfan of \my_empty_reg[1]\ : label is "3";
  attribute syn_maxfan of \my_empty_reg[7]\ : label is "3";
  attribute SOFT_HLUTNM of \my_full[4]_i_3__3\ : label is "soft_lutpair850";
  attribute SOFT_HLUTNM of \my_full[4]_i_4__3\ : label is "soft_lutpair850";
  attribute syn_maxfan of \my_full_reg[4]\ : label is "3";
  attribute SOFT_HLUTNM of \out_fifo_i_10__9\ : label is "soft_lutpair852";
  attribute SOFT_HLUTNM of \out_fifo_i_11__9\ : label is "soft_lutpair859";
  attribute SOFT_HLUTNM of \out_fifo_i_12__9\ : label is "soft_lutpair854";
  attribute SOFT_HLUTNM of \out_fifo_i_13__9\ : label is "soft_lutpair857";
  attribute SOFT_HLUTNM of \out_fifo_i_14__9\ : label is "soft_lutpair855";
  attribute SOFT_HLUTNM of \out_fifo_i_15__9\ : label is "soft_lutpair856";
  attribute SOFT_HLUTNM of \out_fifo_i_16__9\ : label is "soft_lutpair853";
  attribute SOFT_HLUTNM of \out_fifo_i_17__9\ : label is "soft_lutpair861";
  attribute SOFT_HLUTNM of \out_fifo_i_2__2\ : label is "soft_lutpair857";
  attribute SOFT_HLUTNM of \out_fifo_i_3__2\ : label is "soft_lutpair853";
  attribute SOFT_HLUTNM of \out_fifo_i_4__2\ : label is "soft_lutpair859";
  attribute SOFT_HLUTNM of \out_fifo_i_5__2\ : label is "soft_lutpair855";
  attribute SOFT_HLUTNM of \out_fifo_i_6__2\ : label is "soft_lutpair856";
  attribute SOFT_HLUTNM of \out_fifo_i_7__2\ : label is "soft_lutpair852";
  attribute SOFT_HLUTNM of \out_fifo_i_8__2\ : label is "soft_lutpair861";
  attribute SOFT_HLUTNM of \out_fifo_i_9__2\ : label is "soft_lutpair854";
  attribute syn_maxfan of \rd_ptr_reg[0]\ : label is "10";
  attribute syn_maxfan of \rd_ptr_reg[1]\ : label is "10";
  attribute syn_maxfan of \rd_ptr_reg[2]\ : label is "10";
  attribute syn_maxfan of \rd_ptr_reg[3]\ : label is "10";
  attribute SOFT_HLUTNM of \rd_ptr_timing[0]_i_1__7\ : label is "soft_lutpair863";
  attribute SOFT_HLUTNM of \rd_ptr_timing[1]_i_1__7\ : label is "soft_lutpair863";
  attribute SOFT_HLUTNM of \rd_ptr_timing[2]_i_1__3\ : label is "soft_lutpair860";
  attribute SOFT_HLUTNM of \rd_ptr_timing[3]_i_2__3\ : label is "soft_lutpair860";
  attribute KEEP : string;
  attribute KEEP of \rd_ptr_timing_reg[0]\ : label is "yes";
  attribute KEEP of \rd_ptr_timing_reg[1]\ : label is "yes";
  attribute KEEP of \rd_ptr_timing_reg[2]\ : label is "yes";
  attribute KEEP of \rd_ptr_timing_reg[3]\ : label is "yes";
  attribute SOFT_HLUTNM of \wr_ptr[0]_i_1__7\ : label is "soft_lutpair862";
  attribute SOFT_HLUTNM of \wr_ptr[1]_i_1__7\ : label is "soft_lutpair862";
  attribute SOFT_HLUTNM of \wr_ptr[2]_i_1__3\ : label is "soft_lutpair858";
  attribute SOFT_HLUTNM of \wr_ptr[3]_i_2__2\ : label is "soft_lutpair858";
  attribute syn_maxfan of \wr_ptr_reg[0]\ : label is "10";
  attribute syn_maxfan of \wr_ptr_reg[1]\ : label is "10";
  attribute syn_maxfan of \wr_ptr_reg[2]\ : label is "10";
  attribute syn_maxfan of \wr_ptr_reg[3]\ : label is "10";
  attribute KEEP of \wr_ptr_timing_reg[0]\ : label is "yes";
  attribute KEEP of \wr_ptr_timing_reg[1]\ : label is "yes";
  attribute KEEP of \wr_ptr_timing_reg[2]\ : label is "yes";
  attribute KEEP of \wr_ptr_timing_reg[3]\ : label is "yes";
begin
  Q(2 downto 0) <= \^q\(2 downto 0);
  \my_empty_reg[1]_1\ <= \^my_empty_reg[1]_1\;
\entry_cnt[0]_i_1__2\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \entry_cnt_reg_n_0_[0]\,
      O => \entry_cnt[0]_i_1__2_n_0\
    );
\entry_cnt[1]_i_1__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AA6A5595"
    )
        port map (
      I0 => \entry_cnt_reg_n_0_[0]\,
      I1 => \my_empty_reg[7]_0\,
      I2 => phy_data_wr_en,
      I3 => \my_full_reg_n_0_[4]\,
      I4 => \entry_cnt_reg_n_0_[1]\,
      O => \entry_cnt[1]_i_1__2_n_0\
    );
\entry_cnt[2]_i_1__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FF7F0080AAEA5515"
    )
        port map (
      I0 => \entry_cnt_reg_n_0_[0]\,
      I1 => \my_empty_reg[7]_0\,
      I2 => phy_data_wr_en,
      I3 => \my_full_reg_n_0_[4]\,
      I4 => \^q\(0),
      I5 => \entry_cnt_reg_n_0_[1]\,
      O => \entry_cnt[2]_i_1__2_n_0\
    );
\entry_cnt[3]_i_1__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"7F80FE01"
    )
        port map (
      I0 => \entry_cnt10_out__0\,
      I1 => \entry_cnt_reg_n_0_[0]\,
      I2 => \entry_cnt_reg_n_0_[1]\,
      I3 => \^q\(1),
      I4 => \^q\(0),
      O => \entry_cnt[3]_i_1__2_n_0\
    );
\entry_cnt[4]_i_1__2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"5003"
    )
        port map (
      I0 => \my_full_reg_n_0_[4]\,
      I1 => \my_empty_reg_n_0_[7]\,
      I2 => \my_empty_reg[7]_0\,
      I3 => phy_data_wr_en,
      O => \entry_cnt[4]_i_1__2_n_0\
    );
\entry_cnt[4]_i_2__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"7FFF8000FFFE0001"
    )
        port map (
      I0 => \entry_cnt_reg_n_0_[1]\,
      I1 => \entry_cnt_reg_n_0_[0]\,
      I2 => \entry_cnt10_out__0\,
      I3 => \^q\(0),
      I4 => \^q\(2),
      I5 => \^q\(1),
      O => \entry_cnt[4]_i_2__2_n_0\
    );
\entry_cnt[4]_i_3__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"08"
    )
        port map (
      I0 => \my_empty_reg[7]_0\,
      I1 => phy_data_wr_en,
      I2 => \my_full_reg_n_0_[4]\,
      O => \entry_cnt10_out__0\
    );
\entry_cnt_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]_0\,
      CE => \entry_cnt[4]_i_1__2_n_0\,
      D => \entry_cnt[0]_i_1__2_n_0\,
      Q => \entry_cnt_reg_n_0_[0]\,
      R => ofifo_rst
    );
\entry_cnt_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]_0\,
      CE => \entry_cnt[4]_i_1__2_n_0\,
      D => \entry_cnt[1]_i_1__2_n_0\,
      Q => \entry_cnt_reg_n_0_[1]\,
      R => ofifo_rst
    );
\entry_cnt_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]_0\,
      CE => \entry_cnt[4]_i_1__2_n_0\,
      D => \entry_cnt[2]_i_1__2_n_0\,
      Q => \^q\(0),
      R => ofifo_rst
    );
\entry_cnt_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]_0\,
      CE => \entry_cnt[4]_i_1__2_n_0\,
      D => \entry_cnt[3]_i_1__2_n_0\,
      Q => \^q\(1),
      R => ofifo_rst
    );
\entry_cnt_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]_0\,
      CE => \entry_cnt[4]_i_1__2_n_0\,
      D => \entry_cnt[4]_i_2__2_n_0\,
      Q => \^q\(2),
      R => ofifo_rst
    );
mem_reg_0_15_0_5: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4) => '0',
      ADDRA(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRA(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRA(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRA(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRB(4) => '0',
      ADDRB(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRB(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRB(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRB(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRC(4) => '0',
      ADDRC(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRC(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRC(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRC(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRD(4) => '0',
      ADDRD(3 downto 0) => wr_ptr(3 downto 0),
      DIA(1 downto 0) => B"00",
      DIB(1 downto 0) => B"00",
      DIC(1 downto 0) => B"00",
      DID(1 downto 0) => B"00",
      DOA(1) => mem_reg_0_15_0_5_n_0,
      DOA(0) => mem_reg_0_15_0_5_n_1,
      DOB(1) => mem_reg_0_15_0_5_n_2,
      DOB(0) => mem_reg_0_15_0_5_n_3,
      DOC(1) => mem_reg_0_15_0_5_n_4,
      DOC(0) => mem_reg_0_15_0_5_n_5,
      DOD(1 downto 0) => NLW_mem_reg_0_15_0_5_DOD_UNCONNECTED(1 downto 0),
      WCLK => \entry_cnt_reg[4]_0\,
      WE => wr_en
    );
\mem_reg_0_15_0_5_i_1__2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2700"
    )
        port map (
      I0 => \my_empty_reg[7]_0\,
      I1 => \my_full_reg_n_0_[4]\,
      I2 => \^my_empty_reg[1]_1\,
      I3 => phy_data_wr_en,
      O => wr_en
    );
mem_reg_0_15_12_17: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4) => '0',
      ADDRA(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRA(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRA(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRA(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRB(4) => '0',
      ADDRB(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRB(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRB(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRB(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRC(4) => '0',
      ADDRC(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRC(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRC(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRC(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRD(4) => '0',
      ADDRD(3 downto 0) => wr_ptr(3 downto 0),
      DIA(1 downto 0) => \out_fifo_i_75__7\(5 downto 4),
      DIB(1 downto 0) => \out_fifo_i_75__7\(7 downto 6),
      DIC(1 downto 0) => \out_fifo_i_75__7\(9 downto 8),
      DID(1 downto 0) => B"00",
      DOA(1) => mem_reg_0_15_12_17_n_0,
      DOA(0) => mem_reg_0_15_12_17_n_1,
      DOB(1) => mem_reg_0_15_12_17_n_2,
      DOB(0) => mem_reg_0_15_12_17_n_3,
      DOC(1 downto 0) => \rd_ptr_reg[3]_0\(1 downto 0),
      DOD(1 downto 0) => NLW_mem_reg_0_15_12_17_DOD_UNCONNECTED(1 downto 0),
      WCLK => \entry_cnt_reg[4]_0\,
      WE => wr_en
    );
mem_reg_0_15_18_23: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4) => '0',
      ADDRA(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRA(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRA(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRA(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRB(4) => '0',
      ADDRB(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRB(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRB(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRB(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRC(4) => '0',
      ADDRC(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRC(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRC(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRC(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRD(4) => '0',
      ADDRD(3 downto 0) => wr_ptr(3 downto 0),
      DIA(1 downto 0) => \out_fifo_i_75__7\(11 downto 10),
      DIB(1 downto 0) => \out_fifo_i_75__7\(13 downto 12),
      DIC(1 downto 0) => \out_fifo_i_75__7\(15 downto 14),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => \rd_ptr_reg[3]_0\(3 downto 2),
      DOB(1 downto 0) => \rd_ptr_reg[3]_0\(5 downto 4),
      DOC(1 downto 0) => \rd_ptr_reg[3]_0\(7 downto 6),
      DOD(1 downto 0) => NLW_mem_reg_0_15_18_23_DOD_UNCONNECTED(1 downto 0),
      WCLK => \entry_cnt_reg[4]_0\,
      WE => wr_en
    );
mem_reg_0_15_24_29: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4) => '0',
      ADDRA(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRA(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRA(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRA(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRB(4) => '0',
      ADDRB(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRB(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRB(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRB(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRC(4) => '0',
      ADDRC(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRC(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRC(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRC(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRD(4) => '0',
      ADDRD(3 downto 0) => wr_ptr(3 downto 0),
      DIA(1 downto 0) => \out_fifo_i_75__7\(17 downto 16),
      DIB(1 downto 0) => \out_fifo_i_75__7\(19 downto 18),
      DIC(1 downto 0) => \out_fifo_i_75__7\(21 downto 20),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => \rd_ptr_reg[3]_0\(9 downto 8),
      DOB(1 downto 0) => \rd_ptr_reg[3]_0\(11 downto 10),
      DOC(1 downto 0) => \rd_ptr_reg[3]_0\(13 downto 12),
      DOD(1 downto 0) => NLW_mem_reg_0_15_24_29_DOD_UNCONNECTED(1 downto 0),
      WCLK => \entry_cnt_reg[4]_0\,
      WE => wr_en
    );
mem_reg_0_15_30_35: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4) => '0',
      ADDRA(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRA(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRA(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRA(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRB(4) => '0',
      ADDRB(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRB(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRB(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRB(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRC(4) => '0',
      ADDRC(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRC(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRC(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRC(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRD(4) => '0',
      ADDRD(3 downto 0) => wr_ptr(3 downto 0),
      DIA(1 downto 0) => \out_fifo_i_75__7\(23 downto 22),
      DIB(1 downto 0) => \out_fifo_i_75__7\(25 downto 24),
      DIC(1 downto 0) => \out_fifo_i_75__7\(27 downto 26),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => \rd_ptr_reg[3]_0\(15 downto 14),
      DOB(1 downto 0) => \rd_ptr_reg[3]_0\(17 downto 16),
      DOC(1 downto 0) => \rd_ptr_reg[3]_0\(19 downto 18),
      DOD(1 downto 0) => NLW_mem_reg_0_15_30_35_DOD_UNCONNECTED(1 downto 0),
      WCLK => \entry_cnt_reg[4]_0\,
      WE => wr_en
    );
mem_reg_0_15_36_41: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4) => '0',
      ADDRA(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRA(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRA(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRA(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRB(4) => '0',
      ADDRB(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRB(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRB(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRB(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRC(4) => '0',
      ADDRC(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRC(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRC(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRC(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRD(4) => '0',
      ADDRD(3 downto 0) => wr_ptr(3 downto 0),
      DIA(1 downto 0) => \out_fifo_i_75__7\(29 downto 28),
      DIB(1 downto 0) => \out_fifo_i_75__7\(31 downto 30),
      DIC(1 downto 0) => \out_fifo_i_75__7\(33 downto 32),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => \rd_ptr_reg[3]_0\(21 downto 20),
      DOB(1 downto 0) => \rd_ptr_reg[3]_0\(23 downto 22),
      DOC(1 downto 0) => \rd_ptr_reg[3]_0\(25 downto 24),
      DOD(1 downto 0) => NLW_mem_reg_0_15_36_41_DOD_UNCONNECTED(1 downto 0),
      WCLK => \entry_cnt_reg[4]_0\,
      WE => wr_en
    );
mem_reg_0_15_42_47: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4) => '0',
      ADDRA(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRA(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRA(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRA(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRB(4) => '0',
      ADDRB(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRB(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRB(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRB(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRC(4) => '0',
      ADDRC(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRC(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRC(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRC(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRD(4) => '0',
      ADDRD(3 downto 0) => wr_ptr(3 downto 0),
      DIA(1 downto 0) => \out_fifo_i_75__7\(35 downto 34),
      DIB(1 downto 0) => \out_fifo_i_75__7\(37 downto 36),
      DIC(1 downto 0) => \out_fifo_i_75__7\(39 downto 38),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => \rd_ptr_reg[3]_0\(27 downto 26),
      DOB(1 downto 0) => \rd_ptr_reg[3]_0\(29 downto 28),
      DOC(1 downto 0) => \rd_ptr_reg[3]_0\(31 downto 30),
      DOD(1 downto 0) => NLW_mem_reg_0_15_42_47_DOD_UNCONNECTED(1 downto 0),
      WCLK => \entry_cnt_reg[4]_0\,
      WE => wr_en
    );
mem_reg_0_15_48_53: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4) => '0',
      ADDRA(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRA(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRA(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRA(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRB(4) => '0',
      ADDRB(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRB(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRB(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRB(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRC(4) => '0',
      ADDRC(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRC(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRC(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRC(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRD(4) => '0',
      ADDRD(3 downto 0) => wr_ptr(3 downto 0),
      DIA(1 downto 0) => \out_fifo_i_75__7\(41 downto 40),
      DIB(1 downto 0) => \out_fifo_i_75__7\(43 downto 42),
      DIC(1 downto 0) => \out_fifo_i_75__7\(45 downto 44),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => \rd_ptr_reg[3]_0\(33 downto 32),
      DOB(1 downto 0) => \rd_ptr_reg[3]_0\(35 downto 34),
      DOC(1 downto 0) => \rd_ptr_reg[3]_0\(37 downto 36),
      DOD(1 downto 0) => NLW_mem_reg_0_15_48_53_DOD_UNCONNECTED(1 downto 0),
      WCLK => \entry_cnt_reg[4]_0\,
      WE => wr_en
    );
mem_reg_0_15_54_59: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4) => '0',
      ADDRA(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRA(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRA(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRA(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRB(4) => '0',
      ADDRB(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRB(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRB(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRB(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRC(4) => '0',
      ADDRC(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRC(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRC(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRC(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRD(4) => '0',
      ADDRD(3 downto 0) => wr_ptr(3 downto 0),
      DIA(1 downto 0) => \out_fifo_i_75__7\(47 downto 46),
      DIB(1 downto 0) => \out_fifo_i_75__7\(49 downto 48),
      DIC(1 downto 0) => \out_fifo_i_75__7\(51 downto 50),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => \rd_ptr_reg[3]_0\(39 downto 38),
      DOB(1 downto 0) => \rd_ptr_reg[3]_0\(41 downto 40),
      DOC(1 downto 0) => \rd_ptr_reg[3]_0\(43 downto 42),
      DOD(1 downto 0) => NLW_mem_reg_0_15_54_59_DOD_UNCONNECTED(1 downto 0),
      WCLK => \entry_cnt_reg[4]_0\,
      WE => wr_en
    );
mem_reg_0_15_60_65: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4) => '0',
      ADDRA(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRA(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRA(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRA(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRB(4) => '0',
      ADDRB(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRB(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRB(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRB(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRC(4) => '0',
      ADDRC(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRC(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRC(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRC(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRD(4) => '0',
      ADDRD(3 downto 0) => wr_ptr(3 downto 0),
      DIA(1 downto 0) => \out_fifo_i_75__7\(53 downto 52),
      DIB(1 downto 0) => \out_fifo_i_75__7\(55 downto 54),
      DIC(1 downto 0) => \out_fifo_i_75__7\(57 downto 56),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => \rd_ptr_reg[3]_0\(45 downto 44),
      DOB(1 downto 0) => \rd_ptr_reg[3]_0\(47 downto 46),
      DOC(1 downto 0) => \rd_ptr_reg[3]_0\(49 downto 48),
      DOD(1 downto 0) => NLW_mem_reg_0_15_60_65_DOD_UNCONNECTED(1 downto 0),
      WCLK => \entry_cnt_reg[4]_0\,
      WE => wr_en
    );
mem_reg_0_15_66_71: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4) => '0',
      ADDRA(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRA(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRA(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRA(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRB(4) => '0',
      ADDRB(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRB(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRB(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRB(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRC(4) => '0',
      ADDRC(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRC(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRC(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRC(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRD(4) => '0',
      ADDRD(3 downto 0) => wr_ptr(3 downto 0),
      DIA(1 downto 0) => \out_fifo_i_75__7\(59 downto 58),
      DIB(1 downto 0) => \out_fifo_i_75__7\(61 downto 60),
      DIC(1 downto 0) => \out_fifo_i_75__7\(63 downto 62),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => \rd_ptr_reg[3]_0\(51 downto 50),
      DOB(1 downto 0) => \rd_ptr_reg[3]_0\(53 downto 52),
      DOC(1 downto 0) => \rd_ptr_reg[3]_0\(55 downto 54),
      DOD(1 downto 0) => NLW_mem_reg_0_15_66_71_DOD_UNCONNECTED(1 downto 0),
      WCLK => \entry_cnt_reg[4]_0\,
      WE => wr_en
    );
mem_reg_0_15_6_11: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4) => '0',
      ADDRA(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRA(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRA(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRA(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRB(4) => '0',
      ADDRB(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRB(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRB(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRB(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRC(4) => '0',
      ADDRC(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRC(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRC(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRC(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRD(4) => '0',
      ADDRD(3 downto 0) => wr_ptr(3 downto 0),
      DIA(1 downto 0) => B"00",
      DIB(1 downto 0) => \out_fifo_i_75__7\(1 downto 0),
      DIC(1 downto 0) => \out_fifo_i_75__7\(3 downto 2),
      DID(1 downto 0) => B"00",
      DOA(1) => mem_reg_0_15_6_11_n_0,
      DOA(0) => mem_reg_0_15_6_11_n_1,
      DOB(1) => mem_reg_0_15_6_11_n_2,
      DOB(0) => mem_reg_0_15_6_11_n_3,
      DOC(1) => mem_reg_0_15_6_11_n_4,
      DOC(0) => mem_reg_0_15_6_11_n_5,
      DOD(1 downto 0) => NLW_mem_reg_0_15_6_11_DOD_UNCONNECTED(1 downto 0),
      WCLK => \entry_cnt_reg[4]_0\,
      WE => wr_en
    );
mem_reg_0_15_72_77: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4) => '0',
      ADDRA(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRA(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRA(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRA(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRB(4) => '0',
      ADDRB(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRB(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRB(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRB(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRC(4) => '0',
      ADDRC(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRC(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRC(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRC(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRD(4) => '0',
      ADDRD(3 downto 0) => wr_ptr(3 downto 0),
      DIA(1 downto 0) => \out_fifo_i_75__7\(65 downto 64),
      DIB(1 downto 0) => \out_fifo_i_75__7\(67 downto 66),
      DIC(1 downto 0) => \out_fifo_i_75__7\(69 downto 68),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => \rd_ptr_reg[3]_0\(57 downto 56),
      DOB(1 downto 0) => \rd_ptr_reg[3]_0\(59 downto 58),
      DOC(1 downto 0) => \rd_ptr_reg[3]_0\(61 downto 60),
      DOD(1 downto 0) => NLW_mem_reg_0_15_72_77_DOD_UNCONNECTED(1 downto 0),
      WCLK => \entry_cnt_reg[4]_0\,
      WE => wr_en
    );
mem_reg_0_15_78_79: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4) => '0',
      ADDRA(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRA(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRA(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRA(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRB(4) => '0',
      ADDRB(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRB(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRB(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRB(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRC(4) => '0',
      ADDRC(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRC(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRC(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRC(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRD(4) => '0',
      ADDRD(3 downto 0) => wr_ptr(3 downto 0),
      DIA(1 downto 0) => \out_fifo_i_75__7\(71 downto 70),
      DIB(1 downto 0) => B"00",
      DIC(1 downto 0) => B"00",
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => \rd_ptr_reg[3]_0\(63 downto 62),
      DOB(1 downto 0) => NLW_mem_reg_0_15_78_79_DOB_UNCONNECTED(1 downto 0),
      DOC(1 downto 0) => NLW_mem_reg_0_15_78_79_DOC_UNCONNECTED(1 downto 0),
      DOD(1 downto 0) => NLW_mem_reg_0_15_78_79_DOD_UNCONNECTED(1 downto 0),
      WCLK => \entry_cnt_reg[4]_0\,
      WE => wr_en
    );
\my_empty[1]_i_1__3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFF701F700"
    )
        port map (
      I0 => \my_empty_reg[7]_0\,
      I1 => phy_data_wr_en,
      I2 => \my_full_reg_n_0_[4]\,
      I3 => \^my_empty_reg[1]_1\,
      I4 => my_empty0,
      I5 => ofifo_rst,
      O => \my_empty[1]_i_1__3_n_0\
    );
\my_empty[7]_i_1__3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFF701F700"
    )
        port map (
      I0 => \my_empty_reg[7]_0\,
      I1 => phy_data_wr_en,
      I2 => \my_full_reg_n_0_[4]\,
      I3 => \my_empty_reg_n_0_[7]\,
      I4 => my_empty0,
      I5 => ofifo_rst,
      O => \my_empty[7]_i_1__3_n_0\
    );
\my_empty[7]_i_2__3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"4A400D08"
    )
        port map (
      I0 => wr_ptr_timing(2),
      I1 => \my_empty[7]_i_3__3_n_0\,
      I2 => wr_ptr_timing(3),
      I3 => \my_empty[7]_i_4__3_n_0\,
      I4 => \rd_ptr_reg_n_0_[2]\,
      O => my_empty0
    );
\my_empty[7]_i_3__3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000040"
    )
        port map (
      I0 => wr_ptr_timing(1),
      I1 => \rd_ptr_reg_n_0_[0]\,
      I2 => \rd_ptr_reg_n_0_[1]\,
      I3 => \rd_ptr_reg_n_0_[3]\,
      I4 => wr_ptr_timing(0),
      O => \my_empty[7]_i_3__3_n_0\
    );
\my_empty[7]_i_4__3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"84210842"
    )
        port map (
      I0 => wr_ptr_timing(0),
      I1 => wr_ptr_timing(1),
      I2 => \rd_ptr_reg_n_0_[0]\,
      I3 => \rd_ptr_reg_n_0_[1]\,
      I4 => \rd_ptr_reg_n_0_[3]\,
      O => \my_empty[7]_i_4__3_n_0\
    );
\my_empty_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]_0\,
      CE => '1',
      D => \my_empty[1]_i_1__3_n_0\,
      Q => \^my_empty_reg[1]_1\,
      R => '0'
    );
\my_empty_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]_0\,
      CE => '1',
      D => \my_empty[7]_i_1__3_n_0\,
      Q => \my_empty_reg_n_0_[7]\,
      R => '0'
    );
\my_full[4]_i_1__3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000FFFC0080"
    )
        port map (
      I0 => my_full0,
      I1 => phy_data_wr_en,
      I2 => \my_empty_reg[7]_0\,
      I3 => \my_empty_reg_n_0_[7]\,
      I4 => \my_full_reg_n_0_[4]\,
      I5 => ofifo_rst,
      O => \my_full[4]_i_1__3_n_0\
    );
\my_full[4]_i_2__3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"4A400D08"
    )
        port map (
      I0 => rd_ptr_timing(2),
      I1 => \my_full[4]_i_3__3_n_0\,
      I2 => rd_ptr_timing(3),
      I3 => \my_full[4]_i_4__3_n_0\,
      I4 => wr_ptr(2),
      O => my_full0
    );
\my_full[4]_i_3__3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000040"
    )
        port map (
      I0 => rd_ptr_timing(1),
      I1 => wr_ptr(0),
      I2 => wr_ptr(1),
      I3 => wr_ptr(3),
      I4 => rd_ptr_timing(0),
      O => \my_full[4]_i_3__3_n_0\
    );
\my_full[4]_i_4__3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"84210842"
    )
        port map (
      I0 => rd_ptr_timing(0),
      I1 => rd_ptr_timing(1),
      I2 => wr_ptr(0),
      I3 => wr_ptr(1),
      I4 => wr_ptr(3),
      O => \my_full[4]_i_4__3_n_0\
    );
\my_full_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]_0\,
      CE => '1',
      D => \my_full[4]_i_1__3_n_0\,
      Q => \my_full_reg_n_0_[4]\,
      R => '0'
    );
\out_fifo_i_10__9\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"88F0"
    )
        port map (
      I0 => out_fifo_1,
      I1 => out_fifo_0(7),
      I2 => mem_reg_0_15_12_17_n_2,
      I3 => \^my_empty_reg[1]_1\,
      O => D1(7)
    );
\out_fifo_i_11__9\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"88F0"
    )
        port map (
      I0 => out_fifo_1,
      I1 => out_fifo_0(6),
      I2 => mem_reg_0_15_12_17_n_3,
      I3 => \^my_empty_reg[1]_1\,
      O => D1(6)
    );
\out_fifo_i_12__9\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"88F0"
    )
        port map (
      I0 => out_fifo_1,
      I1 => out_fifo_0(5),
      I2 => mem_reg_0_15_12_17_n_0,
      I3 => \^my_empty_reg[1]_1\,
      O => D1(5)
    );
\out_fifo_i_13__9\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"88F0"
    )
        port map (
      I0 => out_fifo_1,
      I1 => out_fifo_0(4),
      I2 => mem_reg_0_15_12_17_n_1,
      I3 => \^my_empty_reg[1]_1\,
      O => D1(4)
    );
\out_fifo_i_14__9\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"88F0"
    )
        port map (
      I0 => out_fifo_1,
      I1 => out_fifo_0(3),
      I2 => mem_reg_0_15_6_11_n_4,
      I3 => \^my_empty_reg[1]_1\,
      O => D1(3)
    );
\out_fifo_i_15__9\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"88F0"
    )
        port map (
      I0 => out_fifo_1,
      I1 => out_fifo_0(2),
      I2 => mem_reg_0_15_6_11_n_5,
      I3 => \^my_empty_reg[1]_1\,
      O => D1(2)
    );
\out_fifo_i_16__9\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"88F0"
    )
        port map (
      I0 => out_fifo_1,
      I1 => out_fifo_0(1),
      I2 => mem_reg_0_15_6_11_n_2,
      I3 => \^my_empty_reg[1]_1\,
      O => D1(1)
    );
\out_fifo_i_17__9\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"88F0"
    )
        port map (
      I0 => out_fifo,
      I1 => out_fifo_0(0),
      I2 => mem_reg_0_15_6_11_n_3,
      I3 => \^my_empty_reg[1]_1\,
      O => D1(0)
    );
\out_fifo_i_1__3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"0D"
    )
        port map (
      I0 => \^my_empty_reg[1]_1\,
      I1 => phy_data_wr_en,
      I2 => \my_empty_reg[7]_0\,
      O => \my_empty_reg[1]_0\
    );
\out_fifo_i_2__2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => mem_reg_0_15_6_11_n_0,
      I1 => \^my_empty_reg[1]_1\,
      O => D0(7)
    );
\out_fifo_i_3__2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => mem_reg_0_15_6_11_n_1,
      I1 => \^my_empty_reg[1]_1\,
      O => D0(6)
    );
\out_fifo_i_4__2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => mem_reg_0_15_0_5_n_4,
      I1 => \^my_empty_reg[1]_1\,
      O => D0(5)
    );
\out_fifo_i_5__2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => mem_reg_0_15_0_5_n_5,
      I1 => \^my_empty_reg[1]_1\,
      O => D0(4)
    );
\out_fifo_i_6__2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => mem_reg_0_15_0_5_n_2,
      I1 => \^my_empty_reg[1]_1\,
      O => D0(3)
    );
\out_fifo_i_7__2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => mem_reg_0_15_0_5_n_3,
      I1 => \^my_empty_reg[1]_1\,
      O => D0(2)
    );
\out_fifo_i_8__2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => mem_reg_0_15_0_5_n_0,
      I1 => \^my_empty_reg[1]_1\,
      O => D0(1)
    );
\out_fifo_i_9__2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => mem_reg_0_15_0_5_n_1,
      I1 => \^my_empty_reg[1]_1\,
      O => D0(0)
    );
\rd_ptr_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]_0\,
      CE => \rd_ptr_timing[3]_i_1__3_n_0\,
      D => nxt_rd_ptr(0),
      Q => \rd_ptr_reg_n_0_[0]\,
      R => ofifo_rst
    );
\rd_ptr_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]_0\,
      CE => \rd_ptr_timing[3]_i_1__3_n_0\,
      D => nxt_rd_ptr(1),
      Q => \rd_ptr_reg_n_0_[1]\,
      R => ofifo_rst
    );
\rd_ptr_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]_0\,
      CE => \rd_ptr_timing[3]_i_1__3_n_0\,
      D => nxt_rd_ptr(2),
      Q => \rd_ptr_reg_n_0_[2]\,
      R => ofifo_rst
    );
\rd_ptr_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]_0\,
      CE => \rd_ptr_timing[3]_i_1__3_n_0\,
      D => nxt_rd_ptr(3),
      Q => \rd_ptr_reg_n_0_[3]\,
      R => ofifo_rst
    );
\rd_ptr_timing[0]_i_1__7\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => \rd_ptr_reg_n_0_[3]\,
      I1 => \rd_ptr_reg_n_0_[0]\,
      O => nxt_rd_ptr(0)
    );
\rd_ptr_timing[1]_i_1__7\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B4"
    )
        port map (
      I0 => \rd_ptr_reg_n_0_[3]\,
      I1 => \rd_ptr_reg_n_0_[0]\,
      I2 => \rd_ptr_reg_n_0_[1]\,
      O => nxt_rd_ptr(1)
    );
\rd_ptr_timing[2]_i_1__3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"AA6A"
    )
        port map (
      I0 => \rd_ptr_reg_n_0_[2]\,
      I1 => \rd_ptr_reg_n_0_[0]\,
      I2 => \rd_ptr_reg_n_0_[1]\,
      I3 => \rd_ptr_reg_n_0_[3]\,
      O => nxt_rd_ptr(2)
    );
\rd_ptr_timing[3]_i_1__3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \my_empty_reg[7]_0\,
      I1 => \my_empty_reg_n_0_[7]\,
      O => \rd_ptr_timing[3]_i_1__3_n_0\
    );
\rd_ptr_timing[3]_i_2__3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4000"
    )
        port map (
      I0 => \rd_ptr_reg_n_0_[3]\,
      I1 => \rd_ptr_reg_n_0_[1]\,
      I2 => \rd_ptr_reg_n_0_[0]\,
      I3 => \rd_ptr_reg_n_0_[2]\,
      O => nxt_rd_ptr(3)
    );
\rd_ptr_timing_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]_0\,
      CE => \rd_ptr_timing[3]_i_1__3_n_0\,
      D => nxt_rd_ptr(0),
      Q => rd_ptr_timing(0),
      R => ofifo_rst
    );
\rd_ptr_timing_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]_0\,
      CE => \rd_ptr_timing[3]_i_1__3_n_0\,
      D => nxt_rd_ptr(1),
      Q => rd_ptr_timing(1),
      R => ofifo_rst
    );
\rd_ptr_timing_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]_0\,
      CE => \rd_ptr_timing[3]_i_1__3_n_0\,
      D => nxt_rd_ptr(2),
      Q => rd_ptr_timing(2),
      R => ofifo_rst
    );
\rd_ptr_timing_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]_0\,
      CE => \rd_ptr_timing[3]_i_1__3_n_0\,
      D => nxt_rd_ptr(3),
      Q => rd_ptr_timing(3),
      R => ofifo_rst
    );
\wr_ptr[0]_i_1__7\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => wr_ptr(3),
      I1 => wr_ptr(0),
      O => nxt_wr_ptr(0)
    );
\wr_ptr[1]_i_1__7\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B4"
    )
        port map (
      I0 => wr_ptr(3),
      I1 => wr_ptr(0),
      I2 => wr_ptr(1),
      O => nxt_wr_ptr(1)
    );
\wr_ptr[2]_i_1__3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"AA6A"
    )
        port map (
      I0 => wr_ptr(2),
      I1 => wr_ptr(0),
      I2 => wr_ptr(1),
      I3 => wr_ptr(3),
      O => nxt_wr_ptr(2)
    );
\wr_ptr[3]_i_1__3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"082A"
    )
        port map (
      I0 => phy_data_wr_en,
      I1 => \my_empty_reg[7]_0\,
      I2 => \my_full_reg_n_0_[4]\,
      I3 => \my_empty_reg_n_0_[7]\,
      O => wr_ptr0
    );
\wr_ptr[3]_i_2__2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4000"
    )
        port map (
      I0 => wr_ptr(3),
      I1 => wr_ptr(1),
      I2 => wr_ptr(0),
      I3 => wr_ptr(2),
      O => nxt_wr_ptr(3)
    );
\wr_ptr_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]_0\,
      CE => wr_ptr0,
      D => nxt_wr_ptr(0),
      Q => wr_ptr(0),
      R => ofifo_rst
    );
\wr_ptr_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]_0\,
      CE => wr_ptr0,
      D => nxt_wr_ptr(1),
      Q => wr_ptr(1),
      R => ofifo_rst
    );
\wr_ptr_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]_0\,
      CE => wr_ptr0,
      D => nxt_wr_ptr(2),
      Q => wr_ptr(2),
      R => ofifo_rst
    );
\wr_ptr_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]_0\,
      CE => wr_ptr0,
      D => nxt_wr_ptr(3),
      Q => wr_ptr(3),
      R => ofifo_rst
    );
\wr_ptr_timing_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]_0\,
      CE => wr_ptr0,
      D => nxt_wr_ptr(0),
      Q => wr_ptr_timing(0),
      R => ofifo_rst
    );
\wr_ptr_timing_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]_0\,
      CE => wr_ptr0,
      D => nxt_wr_ptr(1),
      Q => wr_ptr_timing(1),
      R => ofifo_rst
    );
\wr_ptr_timing_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]_0\,
      CE => wr_ptr0,
      D => nxt_wr_ptr(2),
      Q => wr_ptr_timing(2),
      R => ofifo_rst
    );
\wr_ptr_timing_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]_0\,
      CE => wr_ptr0,
      D => nxt_wr_ptr(3),
      Q => wr_ptr_timing(3),
      R => ofifo_rst
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \mig_mig_7series_v4_2_ddr_of_pre_fifo__parameterized1_34\ is
  port (
    phy_mc_data_full : out STD_LOGIC;
    \my_empty_reg[1]_0\ : out STD_LOGIC;
    \my_empty_reg[1]_1\ : out STD_LOGIC;
    D0 : out STD_LOGIC_VECTOR ( 7 downto 0 );
    D1 : out STD_LOGIC_VECTOR ( 7 downto 0 );
    \rd_ptr_reg[3]_0\ : out STD_LOGIC_VECTOR ( 63 downto 0 );
    Q : out STD_LOGIC_VECTOR ( 2 downto 0 );
    ofifo_rst : in STD_LOGIC;
    \my_full_reg[4]_0\ : in STD_LOGIC;
    ofs_rdy_r_reg : in STD_LOGIC;
    ofs_rdy_r_reg_0 : in STD_LOGIC;
    ofs_rdy_r_reg_1 : in STD_LOGIC;
    ofs_rdy_r_reg_2 : in STD_LOGIC;
    \my_empty_reg[7]_0\ : in STD_LOGIC;
    phy_data_wr_en : in STD_LOGIC;
    out_fifo : in STD_LOGIC;
    out_fifo_0 : in STD_LOGIC_VECTOR ( 7 downto 0 );
    out_fifo_1 : in STD_LOGIC;
    \out_fifo_i_75__6\ : in STD_LOGIC_VECTOR ( 71 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \mig_mig_7series_v4_2_ddr_of_pre_fifo__parameterized1_34\ : entity is "mig_7series_v4_2_ddr_of_pre_fifo";
end \mig_mig_7series_v4_2_ddr_of_pre_fifo__parameterized1_34\;

architecture STRUCTURE of \mig_mig_7series_v4_2_ddr_of_pre_fifo__parameterized1_34\ is
  signal \^q\ : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal \entry_cnt10_out__0\ : STD_LOGIC;
  signal \entry_cnt[0]_i_1__1_n_0\ : STD_LOGIC;
  signal \entry_cnt[1]_i_1__1_n_0\ : STD_LOGIC;
  signal \entry_cnt[2]_i_1__1_n_0\ : STD_LOGIC;
  signal \entry_cnt[3]_i_1__1_n_0\ : STD_LOGIC;
  signal \entry_cnt[4]_i_1__1_n_0\ : STD_LOGIC;
  signal \entry_cnt[4]_i_2__1_n_0\ : STD_LOGIC;
  signal \entry_cnt_reg_n_0_[0]\ : STD_LOGIC;
  signal \entry_cnt_reg_n_0_[1]\ : STD_LOGIC;
  signal mem_reg_0_15_0_5_n_0 : STD_LOGIC;
  signal mem_reg_0_15_0_5_n_1 : STD_LOGIC;
  signal mem_reg_0_15_0_5_n_2 : STD_LOGIC;
  signal mem_reg_0_15_0_5_n_3 : STD_LOGIC;
  signal mem_reg_0_15_0_5_n_4 : STD_LOGIC;
  signal mem_reg_0_15_0_5_n_5 : STD_LOGIC;
  signal mem_reg_0_15_12_17_n_0 : STD_LOGIC;
  signal mem_reg_0_15_12_17_n_1 : STD_LOGIC;
  signal mem_reg_0_15_12_17_n_2 : STD_LOGIC;
  signal mem_reg_0_15_12_17_n_3 : STD_LOGIC;
  signal mem_reg_0_15_6_11_n_0 : STD_LOGIC;
  signal mem_reg_0_15_6_11_n_1 : STD_LOGIC;
  signal mem_reg_0_15_6_11_n_2 : STD_LOGIC;
  signal mem_reg_0_15_6_11_n_3 : STD_LOGIC;
  signal mem_reg_0_15_6_11_n_4 : STD_LOGIC;
  signal mem_reg_0_15_6_11_n_5 : STD_LOGIC;
  signal my_empty0 : STD_LOGIC;
  signal \my_empty[1]_i_1__2_n_0\ : STD_LOGIC;
  signal \my_empty[7]_i_1__2_n_0\ : STD_LOGIC;
  signal \my_empty[7]_i_3__2_n_0\ : STD_LOGIC;
  signal \my_empty[7]_i_4__2_n_0\ : STD_LOGIC;
  signal \^my_empty_reg[1]_1\ : STD_LOGIC;
  signal \my_empty_reg_n_0_[7]\ : STD_LOGIC;
  signal my_full0 : STD_LOGIC;
  signal \my_full[4]_i_1__2_n_0\ : STD_LOGIC;
  signal \my_full[4]_i_3__2_n_0\ : STD_LOGIC;
  signal \my_full[4]_i_4__2_n_0\ : STD_LOGIC;
  signal \my_full_reg_n_0_[4]\ : STD_LOGIC;
  signal nxt_rd_ptr : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal nxt_wr_ptr : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \rd_ptr_reg_n_0_[0]\ : STD_LOGIC;
  signal \rd_ptr_reg_n_0_[1]\ : STD_LOGIC;
  signal \rd_ptr_reg_n_0_[2]\ : STD_LOGIC;
  signal \rd_ptr_reg_n_0_[3]\ : STD_LOGIC;
  signal rd_ptr_timing : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \rd_ptr_timing[3]_i_1__2_n_0\ : STD_LOGIC;
  signal wr_en : STD_LOGIC;
  attribute MAX_FANOUT : string;
  attribute MAX_FANOUT of wr_en : signal is "50";
  attribute RTL_MAX_FANOUT : string;
  attribute RTL_MAX_FANOUT of wr_en : signal is "found";
  signal wr_ptr : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal wr_ptr0 : STD_LOGIC;
  signal wr_ptr_timing : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal NLW_mem_reg_0_15_0_5_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_15_12_17_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_15_18_23_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_15_24_29_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_15_30_35_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_15_36_41_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_15_42_47_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_15_48_53_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_15_54_59_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_15_60_65_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_15_66_71_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_15_6_11_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_15_72_77_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_15_78_79_DOB_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_15_78_79_DOC_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_15_78_79_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \entry_cnt[0]_i_1__1\ : label is "soft_lutpair800";
  attribute SOFT_HLUTNM of \entry_cnt[1]_i_1__1\ : label is "soft_lutpair799";
  attribute SOFT_HLUTNM of \entry_cnt[3]_i_1__1\ : label is "soft_lutpair800";
  attribute SOFT_HLUTNM of \entry_cnt[4]_i_3__1\ : label is "soft_lutpair799";
  attribute METHODOLOGY_DRC_VIOS : string;
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_15_0_5 : label is "";
  attribute RTL_RAM_BITS : integer;
  attribute RTL_RAM_BITS of mem_reg_0_15_0_5 : label is 720;
  attribute RTL_RAM_NAME : string;
  attribute RTL_RAM_NAME of mem_reg_0_15_0_5 : label is "of_pre_fifo_gen.u_ddr_of_pre_fifo/mem";
  attribute ram_addr_begin : integer;
  attribute ram_addr_begin of mem_reg_0_15_0_5 : label is 0;
  attribute ram_addr_end : integer;
  attribute ram_addr_end of mem_reg_0_15_0_5 : label is 8;
  attribute ram_offset : integer;
  attribute ram_offset of mem_reg_0_15_0_5 : label is 0;
  attribute ram_slice_begin : integer;
  attribute ram_slice_begin of mem_reg_0_15_0_5 : label is 0;
  attribute ram_slice_end : integer;
  attribute ram_slice_end of mem_reg_0_15_0_5 : label is 5;
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_15_12_17 : label is "";
  attribute RTL_RAM_BITS of mem_reg_0_15_12_17 : label is 720;
  attribute RTL_RAM_NAME of mem_reg_0_15_12_17 : label is "of_pre_fifo_gen.u_ddr_of_pre_fifo/mem";
  attribute ram_addr_begin of mem_reg_0_15_12_17 : label is 0;
  attribute ram_addr_end of mem_reg_0_15_12_17 : label is 8;
  attribute ram_offset of mem_reg_0_15_12_17 : label is 0;
  attribute ram_slice_begin of mem_reg_0_15_12_17 : label is 12;
  attribute ram_slice_end of mem_reg_0_15_12_17 : label is 17;
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_15_18_23 : label is "";
  attribute RTL_RAM_BITS of mem_reg_0_15_18_23 : label is 720;
  attribute RTL_RAM_NAME of mem_reg_0_15_18_23 : label is "of_pre_fifo_gen.u_ddr_of_pre_fifo/mem";
  attribute ram_addr_begin of mem_reg_0_15_18_23 : label is 0;
  attribute ram_addr_end of mem_reg_0_15_18_23 : label is 8;
  attribute ram_offset of mem_reg_0_15_18_23 : label is 0;
  attribute ram_slice_begin of mem_reg_0_15_18_23 : label is 18;
  attribute ram_slice_end of mem_reg_0_15_18_23 : label is 23;
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_15_24_29 : label is "";
  attribute RTL_RAM_BITS of mem_reg_0_15_24_29 : label is 720;
  attribute RTL_RAM_NAME of mem_reg_0_15_24_29 : label is "of_pre_fifo_gen.u_ddr_of_pre_fifo/mem";
  attribute ram_addr_begin of mem_reg_0_15_24_29 : label is 0;
  attribute ram_addr_end of mem_reg_0_15_24_29 : label is 8;
  attribute ram_offset of mem_reg_0_15_24_29 : label is 0;
  attribute ram_slice_begin of mem_reg_0_15_24_29 : label is 24;
  attribute ram_slice_end of mem_reg_0_15_24_29 : label is 29;
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_15_30_35 : label is "";
  attribute RTL_RAM_BITS of mem_reg_0_15_30_35 : label is 720;
  attribute RTL_RAM_NAME of mem_reg_0_15_30_35 : label is "of_pre_fifo_gen.u_ddr_of_pre_fifo/mem";
  attribute ram_addr_begin of mem_reg_0_15_30_35 : label is 0;
  attribute ram_addr_end of mem_reg_0_15_30_35 : label is 8;
  attribute ram_offset of mem_reg_0_15_30_35 : label is 0;
  attribute ram_slice_begin of mem_reg_0_15_30_35 : label is 30;
  attribute ram_slice_end of mem_reg_0_15_30_35 : label is 35;
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_15_36_41 : label is "";
  attribute RTL_RAM_BITS of mem_reg_0_15_36_41 : label is 720;
  attribute RTL_RAM_NAME of mem_reg_0_15_36_41 : label is "of_pre_fifo_gen.u_ddr_of_pre_fifo/mem";
  attribute ram_addr_begin of mem_reg_0_15_36_41 : label is 0;
  attribute ram_addr_end of mem_reg_0_15_36_41 : label is 8;
  attribute ram_offset of mem_reg_0_15_36_41 : label is 0;
  attribute ram_slice_begin of mem_reg_0_15_36_41 : label is 36;
  attribute ram_slice_end of mem_reg_0_15_36_41 : label is 41;
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_15_42_47 : label is "";
  attribute RTL_RAM_BITS of mem_reg_0_15_42_47 : label is 720;
  attribute RTL_RAM_NAME of mem_reg_0_15_42_47 : label is "of_pre_fifo_gen.u_ddr_of_pre_fifo/mem";
  attribute ram_addr_begin of mem_reg_0_15_42_47 : label is 0;
  attribute ram_addr_end of mem_reg_0_15_42_47 : label is 8;
  attribute ram_offset of mem_reg_0_15_42_47 : label is 0;
  attribute ram_slice_begin of mem_reg_0_15_42_47 : label is 42;
  attribute ram_slice_end of mem_reg_0_15_42_47 : label is 47;
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_15_48_53 : label is "";
  attribute RTL_RAM_BITS of mem_reg_0_15_48_53 : label is 720;
  attribute RTL_RAM_NAME of mem_reg_0_15_48_53 : label is "of_pre_fifo_gen.u_ddr_of_pre_fifo/mem";
  attribute ram_addr_begin of mem_reg_0_15_48_53 : label is 0;
  attribute ram_addr_end of mem_reg_0_15_48_53 : label is 8;
  attribute ram_offset of mem_reg_0_15_48_53 : label is 0;
  attribute ram_slice_begin of mem_reg_0_15_48_53 : label is 48;
  attribute ram_slice_end of mem_reg_0_15_48_53 : label is 53;
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_15_54_59 : label is "";
  attribute RTL_RAM_BITS of mem_reg_0_15_54_59 : label is 720;
  attribute RTL_RAM_NAME of mem_reg_0_15_54_59 : label is "of_pre_fifo_gen.u_ddr_of_pre_fifo/mem";
  attribute ram_addr_begin of mem_reg_0_15_54_59 : label is 0;
  attribute ram_addr_end of mem_reg_0_15_54_59 : label is 8;
  attribute ram_offset of mem_reg_0_15_54_59 : label is 0;
  attribute ram_slice_begin of mem_reg_0_15_54_59 : label is 54;
  attribute ram_slice_end of mem_reg_0_15_54_59 : label is 59;
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_15_60_65 : label is "";
  attribute RTL_RAM_BITS of mem_reg_0_15_60_65 : label is 720;
  attribute RTL_RAM_NAME of mem_reg_0_15_60_65 : label is "of_pre_fifo_gen.u_ddr_of_pre_fifo/mem";
  attribute ram_addr_begin of mem_reg_0_15_60_65 : label is 0;
  attribute ram_addr_end of mem_reg_0_15_60_65 : label is 8;
  attribute ram_offset of mem_reg_0_15_60_65 : label is 0;
  attribute ram_slice_begin of mem_reg_0_15_60_65 : label is 60;
  attribute ram_slice_end of mem_reg_0_15_60_65 : label is 65;
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_15_66_71 : label is "";
  attribute RTL_RAM_BITS of mem_reg_0_15_66_71 : label is 720;
  attribute RTL_RAM_NAME of mem_reg_0_15_66_71 : label is "of_pre_fifo_gen.u_ddr_of_pre_fifo/mem";
  attribute ram_addr_begin of mem_reg_0_15_66_71 : label is 0;
  attribute ram_addr_end of mem_reg_0_15_66_71 : label is 8;
  attribute ram_offset of mem_reg_0_15_66_71 : label is 0;
  attribute ram_slice_begin of mem_reg_0_15_66_71 : label is 66;
  attribute ram_slice_end of mem_reg_0_15_66_71 : label is 71;
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_15_6_11 : label is "";
  attribute RTL_RAM_BITS of mem_reg_0_15_6_11 : label is 720;
  attribute RTL_RAM_NAME of mem_reg_0_15_6_11 : label is "of_pre_fifo_gen.u_ddr_of_pre_fifo/mem";
  attribute ram_addr_begin of mem_reg_0_15_6_11 : label is 0;
  attribute ram_addr_end of mem_reg_0_15_6_11 : label is 8;
  attribute ram_offset of mem_reg_0_15_6_11 : label is 0;
  attribute ram_slice_begin of mem_reg_0_15_6_11 : label is 6;
  attribute ram_slice_end of mem_reg_0_15_6_11 : label is 11;
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_15_72_77 : label is "";
  attribute RTL_RAM_BITS of mem_reg_0_15_72_77 : label is 720;
  attribute RTL_RAM_NAME of mem_reg_0_15_72_77 : label is "of_pre_fifo_gen.u_ddr_of_pre_fifo/mem";
  attribute ram_addr_begin of mem_reg_0_15_72_77 : label is 0;
  attribute ram_addr_end of mem_reg_0_15_72_77 : label is 8;
  attribute ram_offset of mem_reg_0_15_72_77 : label is 0;
  attribute ram_slice_begin of mem_reg_0_15_72_77 : label is 72;
  attribute ram_slice_end of mem_reg_0_15_72_77 : label is 77;
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_15_78_79 : label is "";
  attribute RTL_RAM_BITS of mem_reg_0_15_78_79 : label is 720;
  attribute RTL_RAM_NAME of mem_reg_0_15_78_79 : label is "of_pre_fifo_gen.u_ddr_of_pre_fifo/mem";
  attribute ram_addr_begin of mem_reg_0_15_78_79 : label is 0;
  attribute ram_addr_end of mem_reg_0_15_78_79 : label is 8;
  attribute ram_offset of mem_reg_0_15_78_79 : label is 0;
  attribute ram_slice_begin of mem_reg_0_15_78_79 : label is 78;
  attribute ram_slice_end of mem_reg_0_15_78_79 : label is 79;
  attribute SOFT_HLUTNM of \my_empty[7]_i_3__2\ : label is "soft_lutpair798";
  attribute SOFT_HLUTNM of \my_empty[7]_i_4__2\ : label is "soft_lutpair798";
  attribute syn_maxfan : string;
  attribute syn_maxfan of \my_empty_reg[1]\ : label is "3";
  attribute syn_maxfan of \my_empty_reg[7]\ : label is "3";
  attribute SOFT_HLUTNM of \my_full[4]_i_3__2\ : label is "soft_lutpair797";
  attribute SOFT_HLUTNM of \my_full[4]_i_4__2\ : label is "soft_lutpair797";
  attribute syn_maxfan of \my_full_reg[4]\ : label is "3";
  attribute SOFT_HLUTNM of \out_fifo_i_10__8\ : label is "soft_lutpair808";
  attribute SOFT_HLUTNM of \out_fifo_i_11__8\ : label is "soft_lutpair805";
  attribute SOFT_HLUTNM of \out_fifo_i_12__8\ : label is "soft_lutpair806";
  attribute SOFT_HLUTNM of \out_fifo_i_13__8\ : label is "soft_lutpair804";
  attribute SOFT_HLUTNM of \out_fifo_i_14__8\ : label is "soft_lutpair803";
  attribute SOFT_HLUTNM of \out_fifo_i_15__8\ : label is "soft_lutpair802";
  attribute SOFT_HLUTNM of \out_fifo_i_16__8\ : label is "soft_lutpair801";
  attribute SOFT_HLUTNM of \out_fifo_i_17__8\ : label is "soft_lutpair807";
  attribute SOFT_HLUTNM of \out_fifo_i_2__1\ : label is "soft_lutpair806";
  attribute SOFT_HLUTNM of \out_fifo_i_3__1\ : label is "soft_lutpair802";
  attribute SOFT_HLUTNM of \out_fifo_i_4__1\ : label is "soft_lutpair807";
  attribute SOFT_HLUTNM of \out_fifo_i_5__1\ : label is "soft_lutpair804";
  attribute SOFT_HLUTNM of \out_fifo_i_6__1\ : label is "soft_lutpair805";
  attribute SOFT_HLUTNM of \out_fifo_i_7__1\ : label is "soft_lutpair801";
  attribute SOFT_HLUTNM of \out_fifo_i_8__1\ : label is "soft_lutpair808";
  attribute SOFT_HLUTNM of \out_fifo_i_9__1\ : label is "soft_lutpair803";
  attribute syn_maxfan of \rd_ptr_reg[0]\ : label is "10";
  attribute syn_maxfan of \rd_ptr_reg[1]\ : label is "10";
  attribute syn_maxfan of \rd_ptr_reg[2]\ : label is "10";
  attribute syn_maxfan of \rd_ptr_reg[3]\ : label is "10";
  attribute SOFT_HLUTNM of \rd_ptr_timing[0]_i_1__5\ : label is "soft_lutpair812";
  attribute SOFT_HLUTNM of \rd_ptr_timing[1]_i_1__5\ : label is "soft_lutpair812";
  attribute SOFT_HLUTNM of \rd_ptr_timing[2]_i_1__2\ : label is "soft_lutpair810";
  attribute SOFT_HLUTNM of \rd_ptr_timing[3]_i_2__2\ : label is "soft_lutpair810";
  attribute KEEP : string;
  attribute KEEP of \rd_ptr_timing_reg[0]\ : label is "yes";
  attribute KEEP of \rd_ptr_timing_reg[1]\ : label is "yes";
  attribute KEEP of \rd_ptr_timing_reg[2]\ : label is "yes";
  attribute KEEP of \rd_ptr_timing_reg[3]\ : label is "yes";
  attribute SOFT_HLUTNM of \wr_ptr[0]_i_1__5\ : label is "soft_lutpair811";
  attribute SOFT_HLUTNM of \wr_ptr[1]_i_1__5\ : label is "soft_lutpair811";
  attribute SOFT_HLUTNM of \wr_ptr[2]_i_1__2\ : label is "soft_lutpair809";
  attribute SOFT_HLUTNM of \wr_ptr[3]_i_2__1\ : label is "soft_lutpair809";
  attribute syn_maxfan of \wr_ptr_reg[0]\ : label is "10";
  attribute syn_maxfan of \wr_ptr_reg[1]\ : label is "10";
  attribute syn_maxfan of \wr_ptr_reg[2]\ : label is "10";
  attribute syn_maxfan of \wr_ptr_reg[3]\ : label is "10";
  attribute KEEP of \wr_ptr_timing_reg[0]\ : label is "yes";
  attribute KEEP of \wr_ptr_timing_reg[1]\ : label is "yes";
  attribute KEEP of \wr_ptr_timing_reg[2]\ : label is "yes";
  attribute KEEP of \wr_ptr_timing_reg[3]\ : label is "yes";
begin
  Q(2 downto 0) <= \^q\(2 downto 0);
  \my_empty_reg[1]_1\ <= \^my_empty_reg[1]_1\;
\entry_cnt[0]_i_1__1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \entry_cnt_reg_n_0_[0]\,
      O => \entry_cnt[0]_i_1__1_n_0\
    );
\entry_cnt[1]_i_1__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AA6A5595"
    )
        port map (
      I0 => \entry_cnt_reg_n_0_[0]\,
      I1 => \my_empty_reg[7]_0\,
      I2 => phy_data_wr_en,
      I3 => \my_full_reg_n_0_[4]\,
      I4 => \entry_cnt_reg_n_0_[1]\,
      O => \entry_cnt[1]_i_1__1_n_0\
    );
\entry_cnt[2]_i_1__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FF7F0080AAEA5515"
    )
        port map (
      I0 => \entry_cnt_reg_n_0_[0]\,
      I1 => \my_empty_reg[7]_0\,
      I2 => phy_data_wr_en,
      I3 => \my_full_reg_n_0_[4]\,
      I4 => \^q\(0),
      I5 => \entry_cnt_reg_n_0_[1]\,
      O => \entry_cnt[2]_i_1__1_n_0\
    );
\entry_cnt[3]_i_1__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"7F80FE01"
    )
        port map (
      I0 => \entry_cnt10_out__0\,
      I1 => \entry_cnt_reg_n_0_[0]\,
      I2 => \entry_cnt_reg_n_0_[1]\,
      I3 => \^q\(1),
      I4 => \^q\(0),
      O => \entry_cnt[3]_i_1__1_n_0\
    );
\entry_cnt[4]_i_1__1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"5003"
    )
        port map (
      I0 => \my_full_reg_n_0_[4]\,
      I1 => \my_empty_reg_n_0_[7]\,
      I2 => \my_empty_reg[7]_0\,
      I3 => phy_data_wr_en,
      O => \entry_cnt[4]_i_1__1_n_0\
    );
\entry_cnt[4]_i_2__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"7FFF8000FFFE0001"
    )
        port map (
      I0 => \entry_cnt_reg_n_0_[1]\,
      I1 => \entry_cnt_reg_n_0_[0]\,
      I2 => \entry_cnt10_out__0\,
      I3 => \^q\(0),
      I4 => \^q\(2),
      I5 => \^q\(1),
      O => \entry_cnt[4]_i_2__1_n_0\
    );
\entry_cnt[4]_i_3__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"08"
    )
        port map (
      I0 => \my_empty_reg[7]_0\,
      I1 => phy_data_wr_en,
      I2 => \my_full_reg_n_0_[4]\,
      O => \entry_cnt10_out__0\
    );
\entry_cnt_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \my_full_reg[4]_0\,
      CE => \entry_cnt[4]_i_1__1_n_0\,
      D => \entry_cnt[0]_i_1__1_n_0\,
      Q => \entry_cnt_reg_n_0_[0]\,
      R => ofifo_rst
    );
\entry_cnt_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \my_full_reg[4]_0\,
      CE => \entry_cnt[4]_i_1__1_n_0\,
      D => \entry_cnt[1]_i_1__1_n_0\,
      Q => \entry_cnt_reg_n_0_[1]\,
      R => ofifo_rst
    );
\entry_cnt_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \my_full_reg[4]_0\,
      CE => \entry_cnt[4]_i_1__1_n_0\,
      D => \entry_cnt[2]_i_1__1_n_0\,
      Q => \^q\(0),
      R => ofifo_rst
    );
\entry_cnt_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => \my_full_reg[4]_0\,
      CE => \entry_cnt[4]_i_1__1_n_0\,
      D => \entry_cnt[3]_i_1__1_n_0\,
      Q => \^q\(1),
      R => ofifo_rst
    );
\entry_cnt_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => \my_full_reg[4]_0\,
      CE => \entry_cnt[4]_i_1__1_n_0\,
      D => \entry_cnt[4]_i_2__1_n_0\,
      Q => \^q\(2),
      R => ofifo_rst
    );
mem_reg_0_15_0_5: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4) => '0',
      ADDRA(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRA(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRA(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRA(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRB(4) => '0',
      ADDRB(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRB(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRB(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRB(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRC(4) => '0',
      ADDRC(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRC(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRC(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRC(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRD(4) => '0',
      ADDRD(3 downto 0) => wr_ptr(3 downto 0),
      DIA(1 downto 0) => B"00",
      DIB(1 downto 0) => B"00",
      DIC(1 downto 0) => B"00",
      DID(1 downto 0) => B"00",
      DOA(1) => mem_reg_0_15_0_5_n_0,
      DOA(0) => mem_reg_0_15_0_5_n_1,
      DOB(1) => mem_reg_0_15_0_5_n_2,
      DOB(0) => mem_reg_0_15_0_5_n_3,
      DOC(1) => mem_reg_0_15_0_5_n_4,
      DOC(0) => mem_reg_0_15_0_5_n_5,
      DOD(1 downto 0) => NLW_mem_reg_0_15_0_5_DOD_UNCONNECTED(1 downto 0),
      WCLK => \my_full_reg[4]_0\,
      WE => wr_en
    );
\mem_reg_0_15_0_5_i_1__1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2700"
    )
        port map (
      I0 => \my_empty_reg[7]_0\,
      I1 => \my_full_reg_n_0_[4]\,
      I2 => \^my_empty_reg[1]_1\,
      I3 => phy_data_wr_en,
      O => wr_en
    );
mem_reg_0_15_12_17: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4) => '0',
      ADDRA(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRA(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRA(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRA(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRB(4) => '0',
      ADDRB(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRB(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRB(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRB(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRC(4) => '0',
      ADDRC(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRC(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRC(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRC(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRD(4) => '0',
      ADDRD(3 downto 0) => wr_ptr(3 downto 0),
      DIA(1 downto 0) => \out_fifo_i_75__6\(5 downto 4),
      DIB(1 downto 0) => \out_fifo_i_75__6\(7 downto 6),
      DIC(1 downto 0) => \out_fifo_i_75__6\(9 downto 8),
      DID(1 downto 0) => B"00",
      DOA(1) => mem_reg_0_15_12_17_n_0,
      DOA(0) => mem_reg_0_15_12_17_n_1,
      DOB(1) => mem_reg_0_15_12_17_n_2,
      DOB(0) => mem_reg_0_15_12_17_n_3,
      DOC(1 downto 0) => \rd_ptr_reg[3]_0\(1 downto 0),
      DOD(1 downto 0) => NLW_mem_reg_0_15_12_17_DOD_UNCONNECTED(1 downto 0),
      WCLK => \my_full_reg[4]_0\,
      WE => wr_en
    );
mem_reg_0_15_18_23: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4) => '0',
      ADDRA(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRA(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRA(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRA(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRB(4) => '0',
      ADDRB(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRB(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRB(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRB(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRC(4) => '0',
      ADDRC(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRC(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRC(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRC(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRD(4) => '0',
      ADDRD(3 downto 0) => wr_ptr(3 downto 0),
      DIA(1 downto 0) => \out_fifo_i_75__6\(11 downto 10),
      DIB(1 downto 0) => \out_fifo_i_75__6\(13 downto 12),
      DIC(1 downto 0) => \out_fifo_i_75__6\(15 downto 14),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => \rd_ptr_reg[3]_0\(3 downto 2),
      DOB(1 downto 0) => \rd_ptr_reg[3]_0\(5 downto 4),
      DOC(1 downto 0) => \rd_ptr_reg[3]_0\(7 downto 6),
      DOD(1 downto 0) => NLW_mem_reg_0_15_18_23_DOD_UNCONNECTED(1 downto 0),
      WCLK => \my_full_reg[4]_0\,
      WE => wr_en
    );
mem_reg_0_15_24_29: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4) => '0',
      ADDRA(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRA(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRA(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRA(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRB(4) => '0',
      ADDRB(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRB(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRB(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRB(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRC(4) => '0',
      ADDRC(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRC(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRC(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRC(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRD(4) => '0',
      ADDRD(3 downto 0) => wr_ptr(3 downto 0),
      DIA(1 downto 0) => \out_fifo_i_75__6\(17 downto 16),
      DIB(1 downto 0) => \out_fifo_i_75__6\(19 downto 18),
      DIC(1 downto 0) => \out_fifo_i_75__6\(21 downto 20),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => \rd_ptr_reg[3]_0\(9 downto 8),
      DOB(1 downto 0) => \rd_ptr_reg[3]_0\(11 downto 10),
      DOC(1 downto 0) => \rd_ptr_reg[3]_0\(13 downto 12),
      DOD(1 downto 0) => NLW_mem_reg_0_15_24_29_DOD_UNCONNECTED(1 downto 0),
      WCLK => \my_full_reg[4]_0\,
      WE => wr_en
    );
mem_reg_0_15_30_35: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4) => '0',
      ADDRA(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRA(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRA(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRA(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRB(4) => '0',
      ADDRB(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRB(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRB(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRB(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRC(4) => '0',
      ADDRC(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRC(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRC(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRC(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRD(4) => '0',
      ADDRD(3 downto 0) => wr_ptr(3 downto 0),
      DIA(1 downto 0) => \out_fifo_i_75__6\(23 downto 22),
      DIB(1 downto 0) => \out_fifo_i_75__6\(25 downto 24),
      DIC(1 downto 0) => \out_fifo_i_75__6\(27 downto 26),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => \rd_ptr_reg[3]_0\(15 downto 14),
      DOB(1 downto 0) => \rd_ptr_reg[3]_0\(17 downto 16),
      DOC(1 downto 0) => \rd_ptr_reg[3]_0\(19 downto 18),
      DOD(1 downto 0) => NLW_mem_reg_0_15_30_35_DOD_UNCONNECTED(1 downto 0),
      WCLK => \my_full_reg[4]_0\,
      WE => wr_en
    );
mem_reg_0_15_36_41: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4) => '0',
      ADDRA(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRA(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRA(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRA(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRB(4) => '0',
      ADDRB(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRB(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRB(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRB(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRC(4) => '0',
      ADDRC(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRC(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRC(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRC(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRD(4) => '0',
      ADDRD(3 downto 0) => wr_ptr(3 downto 0),
      DIA(1 downto 0) => \out_fifo_i_75__6\(29 downto 28),
      DIB(1 downto 0) => \out_fifo_i_75__6\(31 downto 30),
      DIC(1 downto 0) => \out_fifo_i_75__6\(33 downto 32),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => \rd_ptr_reg[3]_0\(21 downto 20),
      DOB(1 downto 0) => \rd_ptr_reg[3]_0\(23 downto 22),
      DOC(1 downto 0) => \rd_ptr_reg[3]_0\(25 downto 24),
      DOD(1 downto 0) => NLW_mem_reg_0_15_36_41_DOD_UNCONNECTED(1 downto 0),
      WCLK => \my_full_reg[4]_0\,
      WE => wr_en
    );
mem_reg_0_15_42_47: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4) => '0',
      ADDRA(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRA(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRA(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRA(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRB(4) => '0',
      ADDRB(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRB(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRB(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRB(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRC(4) => '0',
      ADDRC(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRC(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRC(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRC(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRD(4) => '0',
      ADDRD(3 downto 0) => wr_ptr(3 downto 0),
      DIA(1 downto 0) => \out_fifo_i_75__6\(35 downto 34),
      DIB(1 downto 0) => \out_fifo_i_75__6\(37 downto 36),
      DIC(1 downto 0) => \out_fifo_i_75__6\(39 downto 38),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => \rd_ptr_reg[3]_0\(27 downto 26),
      DOB(1 downto 0) => \rd_ptr_reg[3]_0\(29 downto 28),
      DOC(1 downto 0) => \rd_ptr_reg[3]_0\(31 downto 30),
      DOD(1 downto 0) => NLW_mem_reg_0_15_42_47_DOD_UNCONNECTED(1 downto 0),
      WCLK => \my_full_reg[4]_0\,
      WE => wr_en
    );
mem_reg_0_15_48_53: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4) => '0',
      ADDRA(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRA(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRA(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRA(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRB(4) => '0',
      ADDRB(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRB(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRB(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRB(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRC(4) => '0',
      ADDRC(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRC(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRC(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRC(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRD(4) => '0',
      ADDRD(3 downto 0) => wr_ptr(3 downto 0),
      DIA(1 downto 0) => \out_fifo_i_75__6\(41 downto 40),
      DIB(1 downto 0) => \out_fifo_i_75__6\(43 downto 42),
      DIC(1 downto 0) => \out_fifo_i_75__6\(45 downto 44),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => \rd_ptr_reg[3]_0\(33 downto 32),
      DOB(1 downto 0) => \rd_ptr_reg[3]_0\(35 downto 34),
      DOC(1 downto 0) => \rd_ptr_reg[3]_0\(37 downto 36),
      DOD(1 downto 0) => NLW_mem_reg_0_15_48_53_DOD_UNCONNECTED(1 downto 0),
      WCLK => \my_full_reg[4]_0\,
      WE => wr_en
    );
mem_reg_0_15_54_59: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4) => '0',
      ADDRA(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRA(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRA(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRA(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRB(4) => '0',
      ADDRB(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRB(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRB(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRB(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRC(4) => '0',
      ADDRC(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRC(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRC(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRC(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRD(4) => '0',
      ADDRD(3 downto 0) => wr_ptr(3 downto 0),
      DIA(1 downto 0) => \out_fifo_i_75__6\(47 downto 46),
      DIB(1 downto 0) => \out_fifo_i_75__6\(49 downto 48),
      DIC(1 downto 0) => \out_fifo_i_75__6\(51 downto 50),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => \rd_ptr_reg[3]_0\(39 downto 38),
      DOB(1 downto 0) => \rd_ptr_reg[3]_0\(41 downto 40),
      DOC(1 downto 0) => \rd_ptr_reg[3]_0\(43 downto 42),
      DOD(1 downto 0) => NLW_mem_reg_0_15_54_59_DOD_UNCONNECTED(1 downto 0),
      WCLK => \my_full_reg[4]_0\,
      WE => wr_en
    );
mem_reg_0_15_60_65: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4) => '0',
      ADDRA(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRA(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRA(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRA(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRB(4) => '0',
      ADDRB(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRB(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRB(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRB(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRC(4) => '0',
      ADDRC(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRC(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRC(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRC(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRD(4) => '0',
      ADDRD(3 downto 0) => wr_ptr(3 downto 0),
      DIA(1 downto 0) => \out_fifo_i_75__6\(53 downto 52),
      DIB(1 downto 0) => \out_fifo_i_75__6\(55 downto 54),
      DIC(1 downto 0) => \out_fifo_i_75__6\(57 downto 56),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => \rd_ptr_reg[3]_0\(45 downto 44),
      DOB(1 downto 0) => \rd_ptr_reg[3]_0\(47 downto 46),
      DOC(1 downto 0) => \rd_ptr_reg[3]_0\(49 downto 48),
      DOD(1 downto 0) => NLW_mem_reg_0_15_60_65_DOD_UNCONNECTED(1 downto 0),
      WCLK => \my_full_reg[4]_0\,
      WE => wr_en
    );
mem_reg_0_15_66_71: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4) => '0',
      ADDRA(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRA(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRA(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRA(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRB(4) => '0',
      ADDRB(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRB(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRB(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRB(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRC(4) => '0',
      ADDRC(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRC(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRC(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRC(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRD(4) => '0',
      ADDRD(3 downto 0) => wr_ptr(3 downto 0),
      DIA(1 downto 0) => \out_fifo_i_75__6\(59 downto 58),
      DIB(1 downto 0) => \out_fifo_i_75__6\(61 downto 60),
      DIC(1 downto 0) => \out_fifo_i_75__6\(63 downto 62),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => \rd_ptr_reg[3]_0\(51 downto 50),
      DOB(1 downto 0) => \rd_ptr_reg[3]_0\(53 downto 52),
      DOC(1 downto 0) => \rd_ptr_reg[3]_0\(55 downto 54),
      DOD(1 downto 0) => NLW_mem_reg_0_15_66_71_DOD_UNCONNECTED(1 downto 0),
      WCLK => \my_full_reg[4]_0\,
      WE => wr_en
    );
mem_reg_0_15_6_11: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4) => '0',
      ADDRA(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRA(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRA(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRA(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRB(4) => '0',
      ADDRB(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRB(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRB(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRB(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRC(4) => '0',
      ADDRC(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRC(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRC(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRC(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRD(4) => '0',
      ADDRD(3 downto 0) => wr_ptr(3 downto 0),
      DIA(1 downto 0) => B"00",
      DIB(1 downto 0) => \out_fifo_i_75__6\(1 downto 0),
      DIC(1 downto 0) => \out_fifo_i_75__6\(3 downto 2),
      DID(1 downto 0) => B"00",
      DOA(1) => mem_reg_0_15_6_11_n_0,
      DOA(0) => mem_reg_0_15_6_11_n_1,
      DOB(1) => mem_reg_0_15_6_11_n_2,
      DOB(0) => mem_reg_0_15_6_11_n_3,
      DOC(1) => mem_reg_0_15_6_11_n_4,
      DOC(0) => mem_reg_0_15_6_11_n_5,
      DOD(1 downto 0) => NLW_mem_reg_0_15_6_11_DOD_UNCONNECTED(1 downto 0),
      WCLK => \my_full_reg[4]_0\,
      WE => wr_en
    );
mem_reg_0_15_72_77: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4) => '0',
      ADDRA(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRA(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRA(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRA(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRB(4) => '0',
      ADDRB(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRB(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRB(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRB(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRC(4) => '0',
      ADDRC(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRC(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRC(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRC(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRD(4) => '0',
      ADDRD(3 downto 0) => wr_ptr(3 downto 0),
      DIA(1 downto 0) => \out_fifo_i_75__6\(65 downto 64),
      DIB(1 downto 0) => \out_fifo_i_75__6\(67 downto 66),
      DIC(1 downto 0) => \out_fifo_i_75__6\(69 downto 68),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => \rd_ptr_reg[3]_0\(57 downto 56),
      DOB(1 downto 0) => \rd_ptr_reg[3]_0\(59 downto 58),
      DOC(1 downto 0) => \rd_ptr_reg[3]_0\(61 downto 60),
      DOD(1 downto 0) => NLW_mem_reg_0_15_72_77_DOD_UNCONNECTED(1 downto 0),
      WCLK => \my_full_reg[4]_0\,
      WE => wr_en
    );
mem_reg_0_15_78_79: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4) => '0',
      ADDRA(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRA(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRA(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRA(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRB(4) => '0',
      ADDRB(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRB(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRB(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRB(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRC(4) => '0',
      ADDRC(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRC(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRC(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRC(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRD(4) => '0',
      ADDRD(3 downto 0) => wr_ptr(3 downto 0),
      DIA(1 downto 0) => \out_fifo_i_75__6\(71 downto 70),
      DIB(1 downto 0) => B"00",
      DIC(1 downto 0) => B"00",
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => \rd_ptr_reg[3]_0\(63 downto 62),
      DOB(1 downto 0) => NLW_mem_reg_0_15_78_79_DOB_UNCONNECTED(1 downto 0),
      DOC(1 downto 0) => NLW_mem_reg_0_15_78_79_DOC_UNCONNECTED(1 downto 0),
      DOD(1 downto 0) => NLW_mem_reg_0_15_78_79_DOD_UNCONNECTED(1 downto 0),
      WCLK => \my_full_reg[4]_0\,
      WE => wr_en
    );
\my_empty[1]_i_1__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFF701F700"
    )
        port map (
      I0 => \my_empty_reg[7]_0\,
      I1 => phy_data_wr_en,
      I2 => \my_full_reg_n_0_[4]\,
      I3 => \^my_empty_reg[1]_1\,
      I4 => my_empty0,
      I5 => ofifo_rst,
      O => \my_empty[1]_i_1__2_n_0\
    );
\my_empty[7]_i_1__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFF701F700"
    )
        port map (
      I0 => \my_empty_reg[7]_0\,
      I1 => phy_data_wr_en,
      I2 => \my_full_reg_n_0_[4]\,
      I3 => \my_empty_reg_n_0_[7]\,
      I4 => my_empty0,
      I5 => ofifo_rst,
      O => \my_empty[7]_i_1__2_n_0\
    );
\my_empty[7]_i_2__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"4A400D08"
    )
        port map (
      I0 => wr_ptr_timing(2),
      I1 => \my_empty[7]_i_3__2_n_0\,
      I2 => wr_ptr_timing(3),
      I3 => \my_empty[7]_i_4__2_n_0\,
      I4 => \rd_ptr_reg_n_0_[2]\,
      O => my_empty0
    );
\my_empty[7]_i_3__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000040"
    )
        port map (
      I0 => wr_ptr_timing(1),
      I1 => \rd_ptr_reg_n_0_[0]\,
      I2 => \rd_ptr_reg_n_0_[1]\,
      I3 => \rd_ptr_reg_n_0_[3]\,
      I4 => wr_ptr_timing(0),
      O => \my_empty[7]_i_3__2_n_0\
    );
\my_empty[7]_i_4__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"84210842"
    )
        port map (
      I0 => wr_ptr_timing(0),
      I1 => wr_ptr_timing(1),
      I2 => \rd_ptr_reg_n_0_[0]\,
      I3 => \rd_ptr_reg_n_0_[1]\,
      I4 => \rd_ptr_reg_n_0_[3]\,
      O => \my_empty[7]_i_4__2_n_0\
    );
\my_empty_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \my_full_reg[4]_0\,
      CE => '1',
      D => \my_empty[1]_i_1__2_n_0\,
      Q => \^my_empty_reg[1]_1\,
      R => '0'
    );
\my_empty_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => \my_full_reg[4]_0\,
      CE => '1',
      D => \my_empty[7]_i_1__2_n_0\,
      Q => \my_empty_reg_n_0_[7]\,
      R => '0'
    );
\my_full[4]_i_1__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000FFFC0080"
    )
        port map (
      I0 => my_full0,
      I1 => phy_data_wr_en,
      I2 => \my_empty_reg[7]_0\,
      I3 => \my_empty_reg_n_0_[7]\,
      I4 => \my_full_reg_n_0_[4]\,
      I5 => ofifo_rst,
      O => \my_full[4]_i_1__2_n_0\
    );
\my_full[4]_i_2__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"4A400D08"
    )
        port map (
      I0 => rd_ptr_timing(2),
      I1 => \my_full[4]_i_3__2_n_0\,
      I2 => rd_ptr_timing(3),
      I3 => \my_full[4]_i_4__2_n_0\,
      I4 => wr_ptr(2),
      O => my_full0
    );
\my_full[4]_i_3__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000040"
    )
        port map (
      I0 => rd_ptr_timing(1),
      I1 => wr_ptr(0),
      I2 => wr_ptr(1),
      I3 => wr_ptr(3),
      I4 => rd_ptr_timing(0),
      O => \my_full[4]_i_3__2_n_0\
    );
\my_full[4]_i_4__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"84210842"
    )
        port map (
      I0 => rd_ptr_timing(0),
      I1 => rd_ptr_timing(1),
      I2 => wr_ptr(0),
      I3 => wr_ptr(1),
      I4 => wr_ptr(3),
      O => \my_full[4]_i_4__2_n_0\
    );
\my_full_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => \my_full_reg[4]_0\,
      CE => '1',
      D => \my_full[4]_i_1__2_n_0\,
      Q => \my_full_reg_n_0_[4]\,
      R => '0'
    );
ofs_rdy_r_i_2: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFFE"
    )
        port map (
      I0 => ofs_rdy_r_reg,
      I1 => ofs_rdy_r_reg_0,
      I2 => ofs_rdy_r_reg_1,
      I3 => ofs_rdy_r_reg_2,
      O => phy_mc_data_full
    );
\out_fifo_i_10__8\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"88F0"
    )
        port map (
      I0 => out_fifo_1,
      I1 => out_fifo_0(7),
      I2 => mem_reg_0_15_12_17_n_2,
      I3 => \^my_empty_reg[1]_1\,
      O => D1(7)
    );
\out_fifo_i_11__8\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"88F0"
    )
        port map (
      I0 => out_fifo_1,
      I1 => out_fifo_0(6),
      I2 => mem_reg_0_15_12_17_n_3,
      I3 => \^my_empty_reg[1]_1\,
      O => D1(6)
    );
\out_fifo_i_12__8\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"88F0"
    )
        port map (
      I0 => out_fifo_1,
      I1 => out_fifo_0(5),
      I2 => mem_reg_0_15_12_17_n_0,
      I3 => \^my_empty_reg[1]_1\,
      O => D1(5)
    );
\out_fifo_i_13__8\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"88F0"
    )
        port map (
      I0 => out_fifo_1,
      I1 => out_fifo_0(4),
      I2 => mem_reg_0_15_12_17_n_1,
      I3 => \^my_empty_reg[1]_1\,
      O => D1(4)
    );
\out_fifo_i_14__8\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"88F0"
    )
        port map (
      I0 => out_fifo_1,
      I1 => out_fifo_0(3),
      I2 => mem_reg_0_15_6_11_n_4,
      I3 => \^my_empty_reg[1]_1\,
      O => D1(3)
    );
\out_fifo_i_15__8\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"88F0"
    )
        port map (
      I0 => out_fifo_1,
      I1 => out_fifo_0(2),
      I2 => mem_reg_0_15_6_11_n_5,
      I3 => \^my_empty_reg[1]_1\,
      O => D1(2)
    );
\out_fifo_i_16__8\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"88F0"
    )
        port map (
      I0 => out_fifo,
      I1 => out_fifo_0(1),
      I2 => mem_reg_0_15_6_11_n_2,
      I3 => \^my_empty_reg[1]_1\,
      O => D1(1)
    );
\out_fifo_i_17__8\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"88F0"
    )
        port map (
      I0 => out_fifo,
      I1 => out_fifo_0(0),
      I2 => mem_reg_0_15_6_11_n_3,
      I3 => \^my_empty_reg[1]_1\,
      O => D1(0)
    );
\out_fifo_i_1__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"0D"
    )
        port map (
      I0 => \^my_empty_reg[1]_1\,
      I1 => phy_data_wr_en,
      I2 => \my_empty_reg[7]_0\,
      O => \my_empty_reg[1]_0\
    );
\out_fifo_i_2__1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => mem_reg_0_15_6_11_n_0,
      I1 => \^my_empty_reg[1]_1\,
      O => D0(7)
    );
\out_fifo_i_3__1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => mem_reg_0_15_6_11_n_1,
      I1 => \^my_empty_reg[1]_1\,
      O => D0(6)
    );
\out_fifo_i_4__1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => mem_reg_0_15_0_5_n_4,
      I1 => \^my_empty_reg[1]_1\,
      O => D0(5)
    );
\out_fifo_i_5__1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => mem_reg_0_15_0_5_n_5,
      I1 => \^my_empty_reg[1]_1\,
      O => D0(4)
    );
\out_fifo_i_6__1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => mem_reg_0_15_0_5_n_2,
      I1 => \^my_empty_reg[1]_1\,
      O => D0(3)
    );
\out_fifo_i_7__1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => mem_reg_0_15_0_5_n_3,
      I1 => \^my_empty_reg[1]_1\,
      O => D0(2)
    );
\out_fifo_i_8__1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => mem_reg_0_15_0_5_n_0,
      I1 => \^my_empty_reg[1]_1\,
      O => D0(1)
    );
\out_fifo_i_9__1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => mem_reg_0_15_0_5_n_1,
      I1 => \^my_empty_reg[1]_1\,
      O => D0(0)
    );
\rd_ptr_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \my_full_reg[4]_0\,
      CE => \rd_ptr_timing[3]_i_1__2_n_0\,
      D => nxt_rd_ptr(0),
      Q => \rd_ptr_reg_n_0_[0]\,
      R => ofifo_rst
    );
\rd_ptr_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \my_full_reg[4]_0\,
      CE => \rd_ptr_timing[3]_i_1__2_n_0\,
      D => nxt_rd_ptr(1),
      Q => \rd_ptr_reg_n_0_[1]\,
      R => ofifo_rst
    );
\rd_ptr_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \my_full_reg[4]_0\,
      CE => \rd_ptr_timing[3]_i_1__2_n_0\,
      D => nxt_rd_ptr(2),
      Q => \rd_ptr_reg_n_0_[2]\,
      R => ofifo_rst
    );
\rd_ptr_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => \my_full_reg[4]_0\,
      CE => \rd_ptr_timing[3]_i_1__2_n_0\,
      D => nxt_rd_ptr(3),
      Q => \rd_ptr_reg_n_0_[3]\,
      R => ofifo_rst
    );
\rd_ptr_timing[0]_i_1__5\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => \rd_ptr_reg_n_0_[3]\,
      I1 => \rd_ptr_reg_n_0_[0]\,
      O => nxt_rd_ptr(0)
    );
\rd_ptr_timing[1]_i_1__5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B4"
    )
        port map (
      I0 => \rd_ptr_reg_n_0_[3]\,
      I1 => \rd_ptr_reg_n_0_[0]\,
      I2 => \rd_ptr_reg_n_0_[1]\,
      O => nxt_rd_ptr(1)
    );
\rd_ptr_timing[2]_i_1__2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"AA6A"
    )
        port map (
      I0 => \rd_ptr_reg_n_0_[2]\,
      I1 => \rd_ptr_reg_n_0_[0]\,
      I2 => \rd_ptr_reg_n_0_[1]\,
      I3 => \rd_ptr_reg_n_0_[3]\,
      O => nxt_rd_ptr(2)
    );
\rd_ptr_timing[3]_i_1__2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \my_empty_reg[7]_0\,
      I1 => \my_empty_reg_n_0_[7]\,
      O => \rd_ptr_timing[3]_i_1__2_n_0\
    );
\rd_ptr_timing[3]_i_2__2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4000"
    )
        port map (
      I0 => \rd_ptr_reg_n_0_[3]\,
      I1 => \rd_ptr_reg_n_0_[1]\,
      I2 => \rd_ptr_reg_n_0_[0]\,
      I3 => \rd_ptr_reg_n_0_[2]\,
      O => nxt_rd_ptr(3)
    );
\rd_ptr_timing_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \my_full_reg[4]_0\,
      CE => \rd_ptr_timing[3]_i_1__2_n_0\,
      D => nxt_rd_ptr(0),
      Q => rd_ptr_timing(0),
      R => ofifo_rst
    );
\rd_ptr_timing_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \my_full_reg[4]_0\,
      CE => \rd_ptr_timing[3]_i_1__2_n_0\,
      D => nxt_rd_ptr(1),
      Q => rd_ptr_timing(1),
      R => ofifo_rst
    );
\rd_ptr_timing_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \my_full_reg[4]_0\,
      CE => \rd_ptr_timing[3]_i_1__2_n_0\,
      D => nxt_rd_ptr(2),
      Q => rd_ptr_timing(2),
      R => ofifo_rst
    );
\rd_ptr_timing_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => \my_full_reg[4]_0\,
      CE => \rd_ptr_timing[3]_i_1__2_n_0\,
      D => nxt_rd_ptr(3),
      Q => rd_ptr_timing(3),
      R => ofifo_rst
    );
\wr_ptr[0]_i_1__5\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => wr_ptr(3),
      I1 => wr_ptr(0),
      O => nxt_wr_ptr(0)
    );
\wr_ptr[1]_i_1__5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B4"
    )
        port map (
      I0 => wr_ptr(3),
      I1 => wr_ptr(0),
      I2 => wr_ptr(1),
      O => nxt_wr_ptr(1)
    );
\wr_ptr[2]_i_1__2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"AA6A"
    )
        port map (
      I0 => wr_ptr(2),
      I1 => wr_ptr(0),
      I2 => wr_ptr(1),
      I3 => wr_ptr(3),
      O => nxt_wr_ptr(2)
    );
\wr_ptr[3]_i_1__2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"082A"
    )
        port map (
      I0 => phy_data_wr_en,
      I1 => \my_empty_reg[7]_0\,
      I2 => \my_full_reg_n_0_[4]\,
      I3 => \my_empty_reg_n_0_[7]\,
      O => wr_ptr0
    );
\wr_ptr[3]_i_2__1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4000"
    )
        port map (
      I0 => wr_ptr(3),
      I1 => wr_ptr(1),
      I2 => wr_ptr(0),
      I3 => wr_ptr(2),
      O => nxt_wr_ptr(3)
    );
\wr_ptr_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \my_full_reg[4]_0\,
      CE => wr_ptr0,
      D => nxt_wr_ptr(0),
      Q => wr_ptr(0),
      R => ofifo_rst
    );
\wr_ptr_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \my_full_reg[4]_0\,
      CE => wr_ptr0,
      D => nxt_wr_ptr(1),
      Q => wr_ptr(1),
      R => ofifo_rst
    );
\wr_ptr_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \my_full_reg[4]_0\,
      CE => wr_ptr0,
      D => nxt_wr_ptr(2),
      Q => wr_ptr(2),
      R => ofifo_rst
    );
\wr_ptr_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => \my_full_reg[4]_0\,
      CE => wr_ptr0,
      D => nxt_wr_ptr(3),
      Q => wr_ptr(3),
      R => ofifo_rst
    );
\wr_ptr_timing_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \my_full_reg[4]_0\,
      CE => wr_ptr0,
      D => nxt_wr_ptr(0),
      Q => wr_ptr_timing(0),
      R => ofifo_rst
    );
\wr_ptr_timing_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \my_full_reg[4]_0\,
      CE => wr_ptr0,
      D => nxt_wr_ptr(1),
      Q => wr_ptr_timing(1),
      R => ofifo_rst
    );
\wr_ptr_timing_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \my_full_reg[4]_0\,
      CE => wr_ptr0,
      D => nxt_wr_ptr(2),
      Q => wr_ptr_timing(2),
      R => ofifo_rst
    );
\wr_ptr_timing_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => \my_full_reg[4]_0\,
      CE => wr_ptr0,
      D => nxt_wr_ptr(3),
      Q => wr_ptr_timing(3),
      R => ofifo_rst
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \mig_mig_7series_v4_2_ddr_of_pre_fifo__parameterized1_37\ is
  port (
    \my_empty_reg[1]_0\ : out STD_LOGIC;
    \my_empty_reg[1]_1\ : out STD_LOGIC;
    D0 : out STD_LOGIC_VECTOR ( 7 downto 0 );
    D1 : out STD_LOGIC_VECTOR ( 7 downto 0 );
    \rd_ptr_reg[3]_0\ : out STD_LOGIC_VECTOR ( 63 downto 0 );
    Q : out STD_LOGIC_VECTOR ( 2 downto 0 );
    ofifo_rst : in STD_LOGIC;
    \entry_cnt_reg[4]_0\ : in STD_LOGIC;
    \my_empty_reg[7]_0\ : in STD_LOGIC;
    phy_data_wr_en : in STD_LOGIC;
    out_fifo : in STD_LOGIC;
    out_fifo_0 : in STD_LOGIC_VECTOR ( 7 downto 0 );
    out_fifo_1 : in STD_LOGIC;
    \out_fifo_i_75__5\ : in STD_LOGIC_VECTOR ( 71 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \mig_mig_7series_v4_2_ddr_of_pre_fifo__parameterized1_37\ : entity is "mig_7series_v4_2_ddr_of_pre_fifo";
end \mig_mig_7series_v4_2_ddr_of_pre_fifo__parameterized1_37\;

architecture STRUCTURE of \mig_mig_7series_v4_2_ddr_of_pre_fifo__parameterized1_37\ is
  signal \^q\ : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal \entry_cnt10_out__0\ : STD_LOGIC;
  signal \entry_cnt[0]_i_1__0_n_0\ : STD_LOGIC;
  signal \entry_cnt[1]_i_1__0_n_0\ : STD_LOGIC;
  signal \entry_cnt[2]_i_1__0_n_0\ : STD_LOGIC;
  signal \entry_cnt[3]_i_1__0_n_0\ : STD_LOGIC;
  signal \entry_cnt[4]_i_1__0_n_0\ : STD_LOGIC;
  signal \entry_cnt[4]_i_2__0_n_0\ : STD_LOGIC;
  signal \entry_cnt_reg_n_0_[0]\ : STD_LOGIC;
  signal \entry_cnt_reg_n_0_[1]\ : STD_LOGIC;
  signal mem_reg_0_15_0_5_n_0 : STD_LOGIC;
  signal mem_reg_0_15_0_5_n_1 : STD_LOGIC;
  signal mem_reg_0_15_0_5_n_2 : STD_LOGIC;
  signal mem_reg_0_15_0_5_n_3 : STD_LOGIC;
  signal mem_reg_0_15_0_5_n_4 : STD_LOGIC;
  signal mem_reg_0_15_0_5_n_5 : STD_LOGIC;
  signal mem_reg_0_15_12_17_n_0 : STD_LOGIC;
  signal mem_reg_0_15_12_17_n_1 : STD_LOGIC;
  signal mem_reg_0_15_12_17_n_2 : STD_LOGIC;
  signal mem_reg_0_15_12_17_n_3 : STD_LOGIC;
  signal mem_reg_0_15_6_11_n_0 : STD_LOGIC;
  signal mem_reg_0_15_6_11_n_1 : STD_LOGIC;
  signal mem_reg_0_15_6_11_n_2 : STD_LOGIC;
  signal mem_reg_0_15_6_11_n_3 : STD_LOGIC;
  signal mem_reg_0_15_6_11_n_4 : STD_LOGIC;
  signal mem_reg_0_15_6_11_n_5 : STD_LOGIC;
  signal my_empty0 : STD_LOGIC;
  signal \my_empty[1]_i_1__1_n_0\ : STD_LOGIC;
  signal \my_empty[7]_i_1__1_n_0\ : STD_LOGIC;
  signal \my_empty[7]_i_3__1_n_0\ : STD_LOGIC;
  signal \my_empty[7]_i_4__1_n_0\ : STD_LOGIC;
  signal \^my_empty_reg[1]_1\ : STD_LOGIC;
  signal \my_empty_reg_n_0_[7]\ : STD_LOGIC;
  signal my_full0 : STD_LOGIC;
  signal \my_full[4]_i_1__1_n_0\ : STD_LOGIC;
  signal \my_full[4]_i_3__1_n_0\ : STD_LOGIC;
  signal \my_full[4]_i_4__1_n_0\ : STD_LOGIC;
  signal \my_full_reg_n_0_[4]\ : STD_LOGIC;
  signal nxt_rd_ptr : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal nxt_wr_ptr : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \rd_ptr_reg_n_0_[0]\ : STD_LOGIC;
  signal \rd_ptr_reg_n_0_[1]\ : STD_LOGIC;
  signal \rd_ptr_reg_n_0_[2]\ : STD_LOGIC;
  signal \rd_ptr_reg_n_0_[3]\ : STD_LOGIC;
  signal rd_ptr_timing : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \rd_ptr_timing[3]_i_1__1_n_0\ : STD_LOGIC;
  signal wr_en : STD_LOGIC;
  attribute MAX_FANOUT : string;
  attribute MAX_FANOUT of wr_en : signal is "50";
  attribute RTL_MAX_FANOUT : string;
  attribute RTL_MAX_FANOUT of wr_en : signal is "found";
  signal wr_ptr : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal wr_ptr0 : STD_LOGIC;
  signal wr_ptr_timing : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal NLW_mem_reg_0_15_0_5_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_15_12_17_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_15_18_23_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_15_24_29_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_15_30_35_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_15_36_41_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_15_42_47_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_15_48_53_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_15_54_59_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_15_60_65_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_15_66_71_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_15_6_11_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_15_72_77_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_15_78_79_DOB_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_15_78_79_DOC_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_15_78_79_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \entry_cnt[0]_i_1__0\ : label is "soft_lutpair747";
  attribute SOFT_HLUTNM of \entry_cnt[1]_i_1__0\ : label is "soft_lutpair746";
  attribute SOFT_HLUTNM of \entry_cnt[3]_i_1__0\ : label is "soft_lutpair747";
  attribute SOFT_HLUTNM of \entry_cnt[4]_i_3__0\ : label is "soft_lutpair746";
  attribute METHODOLOGY_DRC_VIOS : string;
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_15_0_5 : label is "";
  attribute RTL_RAM_BITS : integer;
  attribute RTL_RAM_BITS of mem_reg_0_15_0_5 : label is 720;
  attribute RTL_RAM_NAME : string;
  attribute RTL_RAM_NAME of mem_reg_0_15_0_5 : label is "of_pre_fifo_gen.u_ddr_of_pre_fifo/mem";
  attribute ram_addr_begin : integer;
  attribute ram_addr_begin of mem_reg_0_15_0_5 : label is 0;
  attribute ram_addr_end : integer;
  attribute ram_addr_end of mem_reg_0_15_0_5 : label is 8;
  attribute ram_offset : integer;
  attribute ram_offset of mem_reg_0_15_0_5 : label is 0;
  attribute ram_slice_begin : integer;
  attribute ram_slice_begin of mem_reg_0_15_0_5 : label is 0;
  attribute ram_slice_end : integer;
  attribute ram_slice_end of mem_reg_0_15_0_5 : label is 5;
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_15_12_17 : label is "";
  attribute RTL_RAM_BITS of mem_reg_0_15_12_17 : label is 720;
  attribute RTL_RAM_NAME of mem_reg_0_15_12_17 : label is "of_pre_fifo_gen.u_ddr_of_pre_fifo/mem";
  attribute ram_addr_begin of mem_reg_0_15_12_17 : label is 0;
  attribute ram_addr_end of mem_reg_0_15_12_17 : label is 8;
  attribute ram_offset of mem_reg_0_15_12_17 : label is 0;
  attribute ram_slice_begin of mem_reg_0_15_12_17 : label is 12;
  attribute ram_slice_end of mem_reg_0_15_12_17 : label is 17;
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_15_18_23 : label is "";
  attribute RTL_RAM_BITS of mem_reg_0_15_18_23 : label is 720;
  attribute RTL_RAM_NAME of mem_reg_0_15_18_23 : label is "of_pre_fifo_gen.u_ddr_of_pre_fifo/mem";
  attribute ram_addr_begin of mem_reg_0_15_18_23 : label is 0;
  attribute ram_addr_end of mem_reg_0_15_18_23 : label is 8;
  attribute ram_offset of mem_reg_0_15_18_23 : label is 0;
  attribute ram_slice_begin of mem_reg_0_15_18_23 : label is 18;
  attribute ram_slice_end of mem_reg_0_15_18_23 : label is 23;
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_15_24_29 : label is "";
  attribute RTL_RAM_BITS of mem_reg_0_15_24_29 : label is 720;
  attribute RTL_RAM_NAME of mem_reg_0_15_24_29 : label is "of_pre_fifo_gen.u_ddr_of_pre_fifo/mem";
  attribute ram_addr_begin of mem_reg_0_15_24_29 : label is 0;
  attribute ram_addr_end of mem_reg_0_15_24_29 : label is 8;
  attribute ram_offset of mem_reg_0_15_24_29 : label is 0;
  attribute ram_slice_begin of mem_reg_0_15_24_29 : label is 24;
  attribute ram_slice_end of mem_reg_0_15_24_29 : label is 29;
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_15_30_35 : label is "";
  attribute RTL_RAM_BITS of mem_reg_0_15_30_35 : label is 720;
  attribute RTL_RAM_NAME of mem_reg_0_15_30_35 : label is "of_pre_fifo_gen.u_ddr_of_pre_fifo/mem";
  attribute ram_addr_begin of mem_reg_0_15_30_35 : label is 0;
  attribute ram_addr_end of mem_reg_0_15_30_35 : label is 8;
  attribute ram_offset of mem_reg_0_15_30_35 : label is 0;
  attribute ram_slice_begin of mem_reg_0_15_30_35 : label is 30;
  attribute ram_slice_end of mem_reg_0_15_30_35 : label is 35;
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_15_36_41 : label is "";
  attribute RTL_RAM_BITS of mem_reg_0_15_36_41 : label is 720;
  attribute RTL_RAM_NAME of mem_reg_0_15_36_41 : label is "of_pre_fifo_gen.u_ddr_of_pre_fifo/mem";
  attribute ram_addr_begin of mem_reg_0_15_36_41 : label is 0;
  attribute ram_addr_end of mem_reg_0_15_36_41 : label is 8;
  attribute ram_offset of mem_reg_0_15_36_41 : label is 0;
  attribute ram_slice_begin of mem_reg_0_15_36_41 : label is 36;
  attribute ram_slice_end of mem_reg_0_15_36_41 : label is 41;
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_15_42_47 : label is "";
  attribute RTL_RAM_BITS of mem_reg_0_15_42_47 : label is 720;
  attribute RTL_RAM_NAME of mem_reg_0_15_42_47 : label is "of_pre_fifo_gen.u_ddr_of_pre_fifo/mem";
  attribute ram_addr_begin of mem_reg_0_15_42_47 : label is 0;
  attribute ram_addr_end of mem_reg_0_15_42_47 : label is 8;
  attribute ram_offset of mem_reg_0_15_42_47 : label is 0;
  attribute ram_slice_begin of mem_reg_0_15_42_47 : label is 42;
  attribute ram_slice_end of mem_reg_0_15_42_47 : label is 47;
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_15_48_53 : label is "";
  attribute RTL_RAM_BITS of mem_reg_0_15_48_53 : label is 720;
  attribute RTL_RAM_NAME of mem_reg_0_15_48_53 : label is "of_pre_fifo_gen.u_ddr_of_pre_fifo/mem";
  attribute ram_addr_begin of mem_reg_0_15_48_53 : label is 0;
  attribute ram_addr_end of mem_reg_0_15_48_53 : label is 8;
  attribute ram_offset of mem_reg_0_15_48_53 : label is 0;
  attribute ram_slice_begin of mem_reg_0_15_48_53 : label is 48;
  attribute ram_slice_end of mem_reg_0_15_48_53 : label is 53;
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_15_54_59 : label is "";
  attribute RTL_RAM_BITS of mem_reg_0_15_54_59 : label is 720;
  attribute RTL_RAM_NAME of mem_reg_0_15_54_59 : label is "of_pre_fifo_gen.u_ddr_of_pre_fifo/mem";
  attribute ram_addr_begin of mem_reg_0_15_54_59 : label is 0;
  attribute ram_addr_end of mem_reg_0_15_54_59 : label is 8;
  attribute ram_offset of mem_reg_0_15_54_59 : label is 0;
  attribute ram_slice_begin of mem_reg_0_15_54_59 : label is 54;
  attribute ram_slice_end of mem_reg_0_15_54_59 : label is 59;
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_15_60_65 : label is "";
  attribute RTL_RAM_BITS of mem_reg_0_15_60_65 : label is 720;
  attribute RTL_RAM_NAME of mem_reg_0_15_60_65 : label is "of_pre_fifo_gen.u_ddr_of_pre_fifo/mem";
  attribute ram_addr_begin of mem_reg_0_15_60_65 : label is 0;
  attribute ram_addr_end of mem_reg_0_15_60_65 : label is 8;
  attribute ram_offset of mem_reg_0_15_60_65 : label is 0;
  attribute ram_slice_begin of mem_reg_0_15_60_65 : label is 60;
  attribute ram_slice_end of mem_reg_0_15_60_65 : label is 65;
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_15_66_71 : label is "";
  attribute RTL_RAM_BITS of mem_reg_0_15_66_71 : label is 720;
  attribute RTL_RAM_NAME of mem_reg_0_15_66_71 : label is "of_pre_fifo_gen.u_ddr_of_pre_fifo/mem";
  attribute ram_addr_begin of mem_reg_0_15_66_71 : label is 0;
  attribute ram_addr_end of mem_reg_0_15_66_71 : label is 8;
  attribute ram_offset of mem_reg_0_15_66_71 : label is 0;
  attribute ram_slice_begin of mem_reg_0_15_66_71 : label is 66;
  attribute ram_slice_end of mem_reg_0_15_66_71 : label is 71;
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_15_6_11 : label is "";
  attribute RTL_RAM_BITS of mem_reg_0_15_6_11 : label is 720;
  attribute RTL_RAM_NAME of mem_reg_0_15_6_11 : label is "of_pre_fifo_gen.u_ddr_of_pre_fifo/mem";
  attribute ram_addr_begin of mem_reg_0_15_6_11 : label is 0;
  attribute ram_addr_end of mem_reg_0_15_6_11 : label is 8;
  attribute ram_offset of mem_reg_0_15_6_11 : label is 0;
  attribute ram_slice_begin of mem_reg_0_15_6_11 : label is 6;
  attribute ram_slice_end of mem_reg_0_15_6_11 : label is 11;
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_15_72_77 : label is "";
  attribute RTL_RAM_BITS of mem_reg_0_15_72_77 : label is 720;
  attribute RTL_RAM_NAME of mem_reg_0_15_72_77 : label is "of_pre_fifo_gen.u_ddr_of_pre_fifo/mem";
  attribute ram_addr_begin of mem_reg_0_15_72_77 : label is 0;
  attribute ram_addr_end of mem_reg_0_15_72_77 : label is 8;
  attribute ram_offset of mem_reg_0_15_72_77 : label is 0;
  attribute ram_slice_begin of mem_reg_0_15_72_77 : label is 72;
  attribute ram_slice_end of mem_reg_0_15_72_77 : label is 77;
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_15_78_79 : label is "";
  attribute RTL_RAM_BITS of mem_reg_0_15_78_79 : label is 720;
  attribute RTL_RAM_NAME of mem_reg_0_15_78_79 : label is "of_pre_fifo_gen.u_ddr_of_pre_fifo/mem";
  attribute ram_addr_begin of mem_reg_0_15_78_79 : label is 0;
  attribute ram_addr_end of mem_reg_0_15_78_79 : label is 8;
  attribute ram_offset of mem_reg_0_15_78_79 : label is 0;
  attribute ram_slice_begin of mem_reg_0_15_78_79 : label is 78;
  attribute ram_slice_end of mem_reg_0_15_78_79 : label is 79;
  attribute SOFT_HLUTNM of \my_empty[7]_i_3__1\ : label is "soft_lutpair749";
  attribute SOFT_HLUTNM of \my_empty[7]_i_4__1\ : label is "soft_lutpair749";
  attribute syn_maxfan : string;
  attribute syn_maxfan of \my_empty_reg[1]\ : label is "3";
  attribute syn_maxfan of \my_empty_reg[7]\ : label is "3";
  attribute SOFT_HLUTNM of \my_full[4]_i_3__1\ : label is "soft_lutpair748";
  attribute SOFT_HLUTNM of \my_full[4]_i_4__1\ : label is "soft_lutpair748";
  attribute syn_maxfan of \my_full_reg[4]\ : label is "3";
  attribute SOFT_HLUTNM of \out_fifo_i_10__7\ : label is "soft_lutpair750";
  attribute SOFT_HLUTNM of \out_fifo_i_11__7\ : label is "soft_lutpair757";
  attribute SOFT_HLUTNM of \out_fifo_i_12__7\ : label is "soft_lutpair752";
  attribute SOFT_HLUTNM of \out_fifo_i_13__7\ : label is "soft_lutpair755";
  attribute SOFT_HLUTNM of \out_fifo_i_14__7\ : label is "soft_lutpair753";
  attribute SOFT_HLUTNM of \out_fifo_i_15__7\ : label is "soft_lutpair754";
  attribute SOFT_HLUTNM of \out_fifo_i_16__7\ : label is "soft_lutpair751";
  attribute SOFT_HLUTNM of \out_fifo_i_17__7\ : label is "soft_lutpair759";
  attribute SOFT_HLUTNM of \out_fifo_i_2__0\ : label is "soft_lutpair755";
  attribute SOFT_HLUTNM of \out_fifo_i_3__0\ : label is "soft_lutpair751";
  attribute SOFT_HLUTNM of \out_fifo_i_4__0\ : label is "soft_lutpair757";
  attribute SOFT_HLUTNM of \out_fifo_i_5__0\ : label is "soft_lutpair753";
  attribute SOFT_HLUTNM of \out_fifo_i_6__0\ : label is "soft_lutpair754";
  attribute SOFT_HLUTNM of \out_fifo_i_7__0\ : label is "soft_lutpair750";
  attribute SOFT_HLUTNM of \out_fifo_i_8__0\ : label is "soft_lutpair759";
  attribute SOFT_HLUTNM of \out_fifo_i_9__0\ : label is "soft_lutpair752";
  attribute syn_maxfan of \rd_ptr_reg[0]\ : label is "10";
  attribute syn_maxfan of \rd_ptr_reg[1]\ : label is "10";
  attribute syn_maxfan of \rd_ptr_reg[2]\ : label is "10";
  attribute syn_maxfan of \rd_ptr_reg[3]\ : label is "10";
  attribute SOFT_HLUTNM of \rd_ptr_timing[0]_i_1__3\ : label is "soft_lutpair761";
  attribute SOFT_HLUTNM of \rd_ptr_timing[1]_i_1__3\ : label is "soft_lutpair761";
  attribute SOFT_HLUTNM of \rd_ptr_timing[2]_i_1__1\ : label is "soft_lutpair758";
  attribute SOFT_HLUTNM of \rd_ptr_timing[3]_i_2__1\ : label is "soft_lutpair758";
  attribute KEEP : string;
  attribute KEEP of \rd_ptr_timing_reg[0]\ : label is "yes";
  attribute KEEP of \rd_ptr_timing_reg[1]\ : label is "yes";
  attribute KEEP of \rd_ptr_timing_reg[2]\ : label is "yes";
  attribute KEEP of \rd_ptr_timing_reg[3]\ : label is "yes";
  attribute SOFT_HLUTNM of \wr_ptr[0]_i_1__3\ : label is "soft_lutpair760";
  attribute SOFT_HLUTNM of \wr_ptr[1]_i_1__3\ : label is "soft_lutpair760";
  attribute SOFT_HLUTNM of \wr_ptr[2]_i_1__1\ : label is "soft_lutpair756";
  attribute SOFT_HLUTNM of \wr_ptr[3]_i_2__0\ : label is "soft_lutpair756";
  attribute syn_maxfan of \wr_ptr_reg[0]\ : label is "10";
  attribute syn_maxfan of \wr_ptr_reg[1]\ : label is "10";
  attribute syn_maxfan of \wr_ptr_reg[2]\ : label is "10";
  attribute syn_maxfan of \wr_ptr_reg[3]\ : label is "10";
  attribute KEEP of \wr_ptr_timing_reg[0]\ : label is "yes";
  attribute KEEP of \wr_ptr_timing_reg[1]\ : label is "yes";
  attribute KEEP of \wr_ptr_timing_reg[2]\ : label is "yes";
  attribute KEEP of \wr_ptr_timing_reg[3]\ : label is "yes";
begin
  Q(2 downto 0) <= \^q\(2 downto 0);
  \my_empty_reg[1]_1\ <= \^my_empty_reg[1]_1\;
\entry_cnt[0]_i_1__0\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \entry_cnt_reg_n_0_[0]\,
      O => \entry_cnt[0]_i_1__0_n_0\
    );
\entry_cnt[1]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AA6A5595"
    )
        port map (
      I0 => \entry_cnt_reg_n_0_[0]\,
      I1 => \my_empty_reg[7]_0\,
      I2 => phy_data_wr_en,
      I3 => \my_full_reg_n_0_[4]\,
      I4 => \entry_cnt_reg_n_0_[1]\,
      O => \entry_cnt[1]_i_1__0_n_0\
    );
\entry_cnt[2]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FF7F0080AAEA5515"
    )
        port map (
      I0 => \entry_cnt_reg_n_0_[0]\,
      I1 => \my_empty_reg[7]_0\,
      I2 => phy_data_wr_en,
      I3 => \my_full_reg_n_0_[4]\,
      I4 => \^q\(0),
      I5 => \entry_cnt_reg_n_0_[1]\,
      O => \entry_cnt[2]_i_1__0_n_0\
    );
\entry_cnt[3]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"7F80FE01"
    )
        port map (
      I0 => \entry_cnt10_out__0\,
      I1 => \entry_cnt_reg_n_0_[0]\,
      I2 => \entry_cnt_reg_n_0_[1]\,
      I3 => \^q\(1),
      I4 => \^q\(0),
      O => \entry_cnt[3]_i_1__0_n_0\
    );
\entry_cnt[4]_i_1__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"5003"
    )
        port map (
      I0 => \my_full_reg_n_0_[4]\,
      I1 => \my_empty_reg_n_0_[7]\,
      I2 => \my_empty_reg[7]_0\,
      I3 => phy_data_wr_en,
      O => \entry_cnt[4]_i_1__0_n_0\
    );
\entry_cnt[4]_i_2__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"7FFF8000FFFE0001"
    )
        port map (
      I0 => \entry_cnt_reg_n_0_[1]\,
      I1 => \entry_cnt_reg_n_0_[0]\,
      I2 => \entry_cnt10_out__0\,
      I3 => \^q\(0),
      I4 => \^q\(2),
      I5 => \^q\(1),
      O => \entry_cnt[4]_i_2__0_n_0\
    );
\entry_cnt[4]_i_3__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"08"
    )
        port map (
      I0 => \my_empty_reg[7]_0\,
      I1 => phy_data_wr_en,
      I2 => \my_full_reg_n_0_[4]\,
      O => \entry_cnt10_out__0\
    );
\entry_cnt_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]_0\,
      CE => \entry_cnt[4]_i_1__0_n_0\,
      D => \entry_cnt[0]_i_1__0_n_0\,
      Q => \entry_cnt_reg_n_0_[0]\,
      R => ofifo_rst
    );
\entry_cnt_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]_0\,
      CE => \entry_cnt[4]_i_1__0_n_0\,
      D => \entry_cnt[1]_i_1__0_n_0\,
      Q => \entry_cnt_reg_n_0_[1]\,
      R => ofifo_rst
    );
\entry_cnt_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]_0\,
      CE => \entry_cnt[4]_i_1__0_n_0\,
      D => \entry_cnt[2]_i_1__0_n_0\,
      Q => \^q\(0),
      R => ofifo_rst
    );
\entry_cnt_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]_0\,
      CE => \entry_cnt[4]_i_1__0_n_0\,
      D => \entry_cnt[3]_i_1__0_n_0\,
      Q => \^q\(1),
      R => ofifo_rst
    );
\entry_cnt_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]_0\,
      CE => \entry_cnt[4]_i_1__0_n_0\,
      D => \entry_cnt[4]_i_2__0_n_0\,
      Q => \^q\(2),
      R => ofifo_rst
    );
mem_reg_0_15_0_5: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4) => '0',
      ADDRA(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRA(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRA(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRA(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRB(4) => '0',
      ADDRB(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRB(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRB(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRB(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRC(4) => '0',
      ADDRC(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRC(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRC(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRC(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRD(4) => '0',
      ADDRD(3 downto 0) => wr_ptr(3 downto 0),
      DIA(1 downto 0) => B"00",
      DIB(1 downto 0) => B"00",
      DIC(1 downto 0) => B"00",
      DID(1 downto 0) => B"00",
      DOA(1) => mem_reg_0_15_0_5_n_0,
      DOA(0) => mem_reg_0_15_0_5_n_1,
      DOB(1) => mem_reg_0_15_0_5_n_2,
      DOB(0) => mem_reg_0_15_0_5_n_3,
      DOC(1) => mem_reg_0_15_0_5_n_4,
      DOC(0) => mem_reg_0_15_0_5_n_5,
      DOD(1 downto 0) => NLW_mem_reg_0_15_0_5_DOD_UNCONNECTED(1 downto 0),
      WCLK => \entry_cnt_reg[4]_0\,
      WE => wr_en
    );
\mem_reg_0_15_0_5_i_1__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2700"
    )
        port map (
      I0 => \my_empty_reg[7]_0\,
      I1 => \my_full_reg_n_0_[4]\,
      I2 => \^my_empty_reg[1]_1\,
      I3 => phy_data_wr_en,
      O => wr_en
    );
mem_reg_0_15_12_17: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4) => '0',
      ADDRA(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRA(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRA(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRA(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRB(4) => '0',
      ADDRB(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRB(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRB(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRB(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRC(4) => '0',
      ADDRC(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRC(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRC(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRC(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRD(4) => '0',
      ADDRD(3 downto 0) => wr_ptr(3 downto 0),
      DIA(1 downto 0) => \out_fifo_i_75__5\(5 downto 4),
      DIB(1 downto 0) => \out_fifo_i_75__5\(7 downto 6),
      DIC(1 downto 0) => \out_fifo_i_75__5\(9 downto 8),
      DID(1 downto 0) => B"00",
      DOA(1) => mem_reg_0_15_12_17_n_0,
      DOA(0) => mem_reg_0_15_12_17_n_1,
      DOB(1) => mem_reg_0_15_12_17_n_2,
      DOB(0) => mem_reg_0_15_12_17_n_3,
      DOC(1 downto 0) => \rd_ptr_reg[3]_0\(1 downto 0),
      DOD(1 downto 0) => NLW_mem_reg_0_15_12_17_DOD_UNCONNECTED(1 downto 0),
      WCLK => \entry_cnt_reg[4]_0\,
      WE => wr_en
    );
mem_reg_0_15_18_23: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4) => '0',
      ADDRA(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRA(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRA(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRA(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRB(4) => '0',
      ADDRB(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRB(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRB(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRB(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRC(4) => '0',
      ADDRC(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRC(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRC(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRC(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRD(4) => '0',
      ADDRD(3 downto 0) => wr_ptr(3 downto 0),
      DIA(1 downto 0) => \out_fifo_i_75__5\(11 downto 10),
      DIB(1 downto 0) => \out_fifo_i_75__5\(13 downto 12),
      DIC(1 downto 0) => \out_fifo_i_75__5\(15 downto 14),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => \rd_ptr_reg[3]_0\(3 downto 2),
      DOB(1 downto 0) => \rd_ptr_reg[3]_0\(5 downto 4),
      DOC(1 downto 0) => \rd_ptr_reg[3]_0\(7 downto 6),
      DOD(1 downto 0) => NLW_mem_reg_0_15_18_23_DOD_UNCONNECTED(1 downto 0),
      WCLK => \entry_cnt_reg[4]_0\,
      WE => wr_en
    );
mem_reg_0_15_24_29: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4) => '0',
      ADDRA(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRA(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRA(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRA(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRB(4) => '0',
      ADDRB(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRB(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRB(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRB(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRC(4) => '0',
      ADDRC(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRC(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRC(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRC(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRD(4) => '0',
      ADDRD(3 downto 0) => wr_ptr(3 downto 0),
      DIA(1 downto 0) => \out_fifo_i_75__5\(17 downto 16),
      DIB(1 downto 0) => \out_fifo_i_75__5\(19 downto 18),
      DIC(1 downto 0) => \out_fifo_i_75__5\(21 downto 20),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => \rd_ptr_reg[3]_0\(9 downto 8),
      DOB(1 downto 0) => \rd_ptr_reg[3]_0\(11 downto 10),
      DOC(1 downto 0) => \rd_ptr_reg[3]_0\(13 downto 12),
      DOD(1 downto 0) => NLW_mem_reg_0_15_24_29_DOD_UNCONNECTED(1 downto 0),
      WCLK => \entry_cnt_reg[4]_0\,
      WE => wr_en
    );
mem_reg_0_15_30_35: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4) => '0',
      ADDRA(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRA(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRA(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRA(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRB(4) => '0',
      ADDRB(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRB(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRB(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRB(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRC(4) => '0',
      ADDRC(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRC(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRC(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRC(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRD(4) => '0',
      ADDRD(3 downto 0) => wr_ptr(3 downto 0),
      DIA(1 downto 0) => \out_fifo_i_75__5\(23 downto 22),
      DIB(1 downto 0) => \out_fifo_i_75__5\(25 downto 24),
      DIC(1 downto 0) => \out_fifo_i_75__5\(27 downto 26),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => \rd_ptr_reg[3]_0\(15 downto 14),
      DOB(1 downto 0) => \rd_ptr_reg[3]_0\(17 downto 16),
      DOC(1 downto 0) => \rd_ptr_reg[3]_0\(19 downto 18),
      DOD(1 downto 0) => NLW_mem_reg_0_15_30_35_DOD_UNCONNECTED(1 downto 0),
      WCLK => \entry_cnt_reg[4]_0\,
      WE => wr_en
    );
mem_reg_0_15_36_41: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4) => '0',
      ADDRA(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRA(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRA(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRA(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRB(4) => '0',
      ADDRB(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRB(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRB(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRB(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRC(4) => '0',
      ADDRC(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRC(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRC(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRC(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRD(4) => '0',
      ADDRD(3 downto 0) => wr_ptr(3 downto 0),
      DIA(1 downto 0) => \out_fifo_i_75__5\(29 downto 28),
      DIB(1 downto 0) => \out_fifo_i_75__5\(31 downto 30),
      DIC(1 downto 0) => \out_fifo_i_75__5\(33 downto 32),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => \rd_ptr_reg[3]_0\(21 downto 20),
      DOB(1 downto 0) => \rd_ptr_reg[3]_0\(23 downto 22),
      DOC(1 downto 0) => \rd_ptr_reg[3]_0\(25 downto 24),
      DOD(1 downto 0) => NLW_mem_reg_0_15_36_41_DOD_UNCONNECTED(1 downto 0),
      WCLK => \entry_cnt_reg[4]_0\,
      WE => wr_en
    );
mem_reg_0_15_42_47: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4) => '0',
      ADDRA(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRA(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRA(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRA(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRB(4) => '0',
      ADDRB(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRB(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRB(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRB(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRC(4) => '0',
      ADDRC(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRC(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRC(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRC(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRD(4) => '0',
      ADDRD(3 downto 0) => wr_ptr(3 downto 0),
      DIA(1 downto 0) => \out_fifo_i_75__5\(35 downto 34),
      DIB(1 downto 0) => \out_fifo_i_75__5\(37 downto 36),
      DIC(1 downto 0) => \out_fifo_i_75__5\(39 downto 38),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => \rd_ptr_reg[3]_0\(27 downto 26),
      DOB(1 downto 0) => \rd_ptr_reg[3]_0\(29 downto 28),
      DOC(1 downto 0) => \rd_ptr_reg[3]_0\(31 downto 30),
      DOD(1 downto 0) => NLW_mem_reg_0_15_42_47_DOD_UNCONNECTED(1 downto 0),
      WCLK => \entry_cnt_reg[4]_0\,
      WE => wr_en
    );
mem_reg_0_15_48_53: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4) => '0',
      ADDRA(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRA(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRA(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRA(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRB(4) => '0',
      ADDRB(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRB(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRB(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRB(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRC(4) => '0',
      ADDRC(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRC(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRC(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRC(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRD(4) => '0',
      ADDRD(3 downto 0) => wr_ptr(3 downto 0),
      DIA(1 downto 0) => \out_fifo_i_75__5\(41 downto 40),
      DIB(1 downto 0) => \out_fifo_i_75__5\(43 downto 42),
      DIC(1 downto 0) => \out_fifo_i_75__5\(45 downto 44),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => \rd_ptr_reg[3]_0\(33 downto 32),
      DOB(1 downto 0) => \rd_ptr_reg[3]_0\(35 downto 34),
      DOC(1 downto 0) => \rd_ptr_reg[3]_0\(37 downto 36),
      DOD(1 downto 0) => NLW_mem_reg_0_15_48_53_DOD_UNCONNECTED(1 downto 0),
      WCLK => \entry_cnt_reg[4]_0\,
      WE => wr_en
    );
mem_reg_0_15_54_59: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4) => '0',
      ADDRA(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRA(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRA(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRA(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRB(4) => '0',
      ADDRB(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRB(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRB(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRB(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRC(4) => '0',
      ADDRC(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRC(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRC(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRC(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRD(4) => '0',
      ADDRD(3 downto 0) => wr_ptr(3 downto 0),
      DIA(1 downto 0) => \out_fifo_i_75__5\(47 downto 46),
      DIB(1 downto 0) => \out_fifo_i_75__5\(49 downto 48),
      DIC(1 downto 0) => \out_fifo_i_75__5\(51 downto 50),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => \rd_ptr_reg[3]_0\(39 downto 38),
      DOB(1 downto 0) => \rd_ptr_reg[3]_0\(41 downto 40),
      DOC(1 downto 0) => \rd_ptr_reg[3]_0\(43 downto 42),
      DOD(1 downto 0) => NLW_mem_reg_0_15_54_59_DOD_UNCONNECTED(1 downto 0),
      WCLK => \entry_cnt_reg[4]_0\,
      WE => wr_en
    );
mem_reg_0_15_60_65: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4) => '0',
      ADDRA(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRA(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRA(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRA(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRB(4) => '0',
      ADDRB(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRB(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRB(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRB(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRC(4) => '0',
      ADDRC(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRC(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRC(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRC(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRD(4) => '0',
      ADDRD(3 downto 0) => wr_ptr(3 downto 0),
      DIA(1 downto 0) => \out_fifo_i_75__5\(53 downto 52),
      DIB(1 downto 0) => \out_fifo_i_75__5\(55 downto 54),
      DIC(1 downto 0) => \out_fifo_i_75__5\(57 downto 56),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => \rd_ptr_reg[3]_0\(45 downto 44),
      DOB(1 downto 0) => \rd_ptr_reg[3]_0\(47 downto 46),
      DOC(1 downto 0) => \rd_ptr_reg[3]_0\(49 downto 48),
      DOD(1 downto 0) => NLW_mem_reg_0_15_60_65_DOD_UNCONNECTED(1 downto 0),
      WCLK => \entry_cnt_reg[4]_0\,
      WE => wr_en
    );
mem_reg_0_15_66_71: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4) => '0',
      ADDRA(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRA(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRA(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRA(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRB(4) => '0',
      ADDRB(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRB(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRB(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRB(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRC(4) => '0',
      ADDRC(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRC(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRC(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRC(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRD(4) => '0',
      ADDRD(3 downto 0) => wr_ptr(3 downto 0),
      DIA(1 downto 0) => \out_fifo_i_75__5\(59 downto 58),
      DIB(1 downto 0) => \out_fifo_i_75__5\(61 downto 60),
      DIC(1 downto 0) => \out_fifo_i_75__5\(63 downto 62),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => \rd_ptr_reg[3]_0\(51 downto 50),
      DOB(1 downto 0) => \rd_ptr_reg[3]_0\(53 downto 52),
      DOC(1 downto 0) => \rd_ptr_reg[3]_0\(55 downto 54),
      DOD(1 downto 0) => NLW_mem_reg_0_15_66_71_DOD_UNCONNECTED(1 downto 0),
      WCLK => \entry_cnt_reg[4]_0\,
      WE => wr_en
    );
mem_reg_0_15_6_11: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4) => '0',
      ADDRA(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRA(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRA(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRA(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRB(4) => '0',
      ADDRB(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRB(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRB(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRB(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRC(4) => '0',
      ADDRC(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRC(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRC(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRC(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRD(4) => '0',
      ADDRD(3 downto 0) => wr_ptr(3 downto 0),
      DIA(1 downto 0) => B"00",
      DIB(1 downto 0) => \out_fifo_i_75__5\(1 downto 0),
      DIC(1 downto 0) => \out_fifo_i_75__5\(3 downto 2),
      DID(1 downto 0) => B"00",
      DOA(1) => mem_reg_0_15_6_11_n_0,
      DOA(0) => mem_reg_0_15_6_11_n_1,
      DOB(1) => mem_reg_0_15_6_11_n_2,
      DOB(0) => mem_reg_0_15_6_11_n_3,
      DOC(1) => mem_reg_0_15_6_11_n_4,
      DOC(0) => mem_reg_0_15_6_11_n_5,
      DOD(1 downto 0) => NLW_mem_reg_0_15_6_11_DOD_UNCONNECTED(1 downto 0),
      WCLK => \entry_cnt_reg[4]_0\,
      WE => wr_en
    );
mem_reg_0_15_72_77: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4) => '0',
      ADDRA(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRA(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRA(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRA(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRB(4) => '0',
      ADDRB(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRB(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRB(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRB(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRC(4) => '0',
      ADDRC(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRC(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRC(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRC(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRD(4) => '0',
      ADDRD(3 downto 0) => wr_ptr(3 downto 0),
      DIA(1 downto 0) => \out_fifo_i_75__5\(65 downto 64),
      DIB(1 downto 0) => \out_fifo_i_75__5\(67 downto 66),
      DIC(1 downto 0) => \out_fifo_i_75__5\(69 downto 68),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => \rd_ptr_reg[3]_0\(57 downto 56),
      DOB(1 downto 0) => \rd_ptr_reg[3]_0\(59 downto 58),
      DOC(1 downto 0) => \rd_ptr_reg[3]_0\(61 downto 60),
      DOD(1 downto 0) => NLW_mem_reg_0_15_72_77_DOD_UNCONNECTED(1 downto 0),
      WCLK => \entry_cnt_reg[4]_0\,
      WE => wr_en
    );
mem_reg_0_15_78_79: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4) => '0',
      ADDRA(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRA(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRA(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRA(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRB(4) => '0',
      ADDRB(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRB(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRB(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRB(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRC(4) => '0',
      ADDRC(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRC(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRC(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRC(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRD(4) => '0',
      ADDRD(3 downto 0) => wr_ptr(3 downto 0),
      DIA(1 downto 0) => \out_fifo_i_75__5\(71 downto 70),
      DIB(1 downto 0) => B"00",
      DIC(1 downto 0) => B"00",
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => \rd_ptr_reg[3]_0\(63 downto 62),
      DOB(1 downto 0) => NLW_mem_reg_0_15_78_79_DOB_UNCONNECTED(1 downto 0),
      DOC(1 downto 0) => NLW_mem_reg_0_15_78_79_DOC_UNCONNECTED(1 downto 0),
      DOD(1 downto 0) => NLW_mem_reg_0_15_78_79_DOD_UNCONNECTED(1 downto 0),
      WCLK => \entry_cnt_reg[4]_0\,
      WE => wr_en
    );
\my_empty[1]_i_1__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFF701F700"
    )
        port map (
      I0 => \my_empty_reg[7]_0\,
      I1 => phy_data_wr_en,
      I2 => \my_full_reg_n_0_[4]\,
      I3 => \^my_empty_reg[1]_1\,
      I4 => my_empty0,
      I5 => ofifo_rst,
      O => \my_empty[1]_i_1__1_n_0\
    );
\my_empty[7]_i_1__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFF701F700"
    )
        port map (
      I0 => \my_empty_reg[7]_0\,
      I1 => phy_data_wr_en,
      I2 => \my_full_reg_n_0_[4]\,
      I3 => \my_empty_reg_n_0_[7]\,
      I4 => my_empty0,
      I5 => ofifo_rst,
      O => \my_empty[7]_i_1__1_n_0\
    );
\my_empty[7]_i_2__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"4A400D08"
    )
        port map (
      I0 => wr_ptr_timing(2),
      I1 => \my_empty[7]_i_3__1_n_0\,
      I2 => wr_ptr_timing(3),
      I3 => \my_empty[7]_i_4__1_n_0\,
      I4 => \rd_ptr_reg_n_0_[2]\,
      O => my_empty0
    );
\my_empty[7]_i_3__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000040"
    )
        port map (
      I0 => wr_ptr_timing(1),
      I1 => \rd_ptr_reg_n_0_[0]\,
      I2 => \rd_ptr_reg_n_0_[1]\,
      I3 => \rd_ptr_reg_n_0_[3]\,
      I4 => wr_ptr_timing(0),
      O => \my_empty[7]_i_3__1_n_0\
    );
\my_empty[7]_i_4__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"84210842"
    )
        port map (
      I0 => wr_ptr_timing(0),
      I1 => wr_ptr_timing(1),
      I2 => \rd_ptr_reg_n_0_[0]\,
      I3 => \rd_ptr_reg_n_0_[1]\,
      I4 => \rd_ptr_reg_n_0_[3]\,
      O => \my_empty[7]_i_4__1_n_0\
    );
\my_empty_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]_0\,
      CE => '1',
      D => \my_empty[1]_i_1__1_n_0\,
      Q => \^my_empty_reg[1]_1\,
      R => '0'
    );
\my_empty_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]_0\,
      CE => '1',
      D => \my_empty[7]_i_1__1_n_0\,
      Q => \my_empty_reg_n_0_[7]\,
      R => '0'
    );
\my_full[4]_i_1__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000FFFC0080"
    )
        port map (
      I0 => my_full0,
      I1 => phy_data_wr_en,
      I2 => \my_empty_reg[7]_0\,
      I3 => \my_empty_reg_n_0_[7]\,
      I4 => \my_full_reg_n_0_[4]\,
      I5 => ofifo_rst,
      O => \my_full[4]_i_1__1_n_0\
    );
\my_full[4]_i_2__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"4A400D08"
    )
        port map (
      I0 => rd_ptr_timing(2),
      I1 => \my_full[4]_i_3__1_n_0\,
      I2 => rd_ptr_timing(3),
      I3 => \my_full[4]_i_4__1_n_0\,
      I4 => wr_ptr(2),
      O => my_full0
    );
\my_full[4]_i_3__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000040"
    )
        port map (
      I0 => rd_ptr_timing(1),
      I1 => wr_ptr(0),
      I2 => wr_ptr(1),
      I3 => wr_ptr(3),
      I4 => rd_ptr_timing(0),
      O => \my_full[4]_i_3__1_n_0\
    );
\my_full[4]_i_4__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"84210842"
    )
        port map (
      I0 => rd_ptr_timing(0),
      I1 => rd_ptr_timing(1),
      I2 => wr_ptr(0),
      I3 => wr_ptr(1),
      I4 => wr_ptr(3),
      O => \my_full[4]_i_4__1_n_0\
    );
\my_full_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]_0\,
      CE => '1',
      D => \my_full[4]_i_1__1_n_0\,
      Q => \my_full_reg_n_0_[4]\,
      R => '0'
    );
\out_fifo_i_10__7\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"88F0"
    )
        port map (
      I0 => out_fifo_1,
      I1 => out_fifo_0(7),
      I2 => mem_reg_0_15_12_17_n_2,
      I3 => \^my_empty_reg[1]_1\,
      O => D1(7)
    );
\out_fifo_i_11__7\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"88F0"
    )
        port map (
      I0 => out_fifo_1,
      I1 => out_fifo_0(6),
      I2 => mem_reg_0_15_12_17_n_3,
      I3 => \^my_empty_reg[1]_1\,
      O => D1(6)
    );
\out_fifo_i_12__7\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"88F0"
    )
        port map (
      I0 => out_fifo_1,
      I1 => out_fifo_0(5),
      I2 => mem_reg_0_15_12_17_n_0,
      I3 => \^my_empty_reg[1]_1\,
      O => D1(5)
    );
\out_fifo_i_13__7\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"88F0"
    )
        port map (
      I0 => out_fifo_1,
      I1 => out_fifo_0(4),
      I2 => mem_reg_0_15_12_17_n_1,
      I3 => \^my_empty_reg[1]_1\,
      O => D1(4)
    );
\out_fifo_i_14__7\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"88F0"
    )
        port map (
      I0 => out_fifo_1,
      I1 => out_fifo_0(3),
      I2 => mem_reg_0_15_6_11_n_4,
      I3 => \^my_empty_reg[1]_1\,
      O => D1(3)
    );
\out_fifo_i_15__7\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"88F0"
    )
        port map (
      I0 => out_fifo_1,
      I1 => out_fifo_0(2),
      I2 => mem_reg_0_15_6_11_n_5,
      I3 => \^my_empty_reg[1]_1\,
      O => D1(2)
    );
\out_fifo_i_16__7\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"88F0"
    )
        port map (
      I0 => out_fifo,
      I1 => out_fifo_0(1),
      I2 => mem_reg_0_15_6_11_n_2,
      I3 => \^my_empty_reg[1]_1\,
      O => D1(1)
    );
\out_fifo_i_17__7\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"88F0"
    )
        port map (
      I0 => out_fifo,
      I1 => out_fifo_0(0),
      I2 => mem_reg_0_15_6_11_n_3,
      I3 => \^my_empty_reg[1]_1\,
      O => D1(0)
    );
\out_fifo_i_1__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"0D"
    )
        port map (
      I0 => \^my_empty_reg[1]_1\,
      I1 => phy_data_wr_en,
      I2 => \my_empty_reg[7]_0\,
      O => \my_empty_reg[1]_0\
    );
\out_fifo_i_2__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => mem_reg_0_15_6_11_n_0,
      I1 => \^my_empty_reg[1]_1\,
      O => D0(7)
    );
\out_fifo_i_3__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => mem_reg_0_15_6_11_n_1,
      I1 => \^my_empty_reg[1]_1\,
      O => D0(6)
    );
\out_fifo_i_4__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => mem_reg_0_15_0_5_n_4,
      I1 => \^my_empty_reg[1]_1\,
      O => D0(5)
    );
\out_fifo_i_5__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => mem_reg_0_15_0_5_n_5,
      I1 => \^my_empty_reg[1]_1\,
      O => D0(4)
    );
\out_fifo_i_6__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => mem_reg_0_15_0_5_n_2,
      I1 => \^my_empty_reg[1]_1\,
      O => D0(3)
    );
\out_fifo_i_7__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => mem_reg_0_15_0_5_n_3,
      I1 => \^my_empty_reg[1]_1\,
      O => D0(2)
    );
\out_fifo_i_8__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => mem_reg_0_15_0_5_n_0,
      I1 => \^my_empty_reg[1]_1\,
      O => D0(1)
    );
\out_fifo_i_9__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => mem_reg_0_15_0_5_n_1,
      I1 => \^my_empty_reg[1]_1\,
      O => D0(0)
    );
\rd_ptr_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]_0\,
      CE => \rd_ptr_timing[3]_i_1__1_n_0\,
      D => nxt_rd_ptr(0),
      Q => \rd_ptr_reg_n_0_[0]\,
      R => ofifo_rst
    );
\rd_ptr_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]_0\,
      CE => \rd_ptr_timing[3]_i_1__1_n_0\,
      D => nxt_rd_ptr(1),
      Q => \rd_ptr_reg_n_0_[1]\,
      R => ofifo_rst
    );
\rd_ptr_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]_0\,
      CE => \rd_ptr_timing[3]_i_1__1_n_0\,
      D => nxt_rd_ptr(2),
      Q => \rd_ptr_reg_n_0_[2]\,
      R => ofifo_rst
    );
\rd_ptr_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]_0\,
      CE => \rd_ptr_timing[3]_i_1__1_n_0\,
      D => nxt_rd_ptr(3),
      Q => \rd_ptr_reg_n_0_[3]\,
      R => ofifo_rst
    );
\rd_ptr_timing[0]_i_1__3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => \rd_ptr_reg_n_0_[3]\,
      I1 => \rd_ptr_reg_n_0_[0]\,
      O => nxt_rd_ptr(0)
    );
\rd_ptr_timing[1]_i_1__3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B4"
    )
        port map (
      I0 => \rd_ptr_reg_n_0_[3]\,
      I1 => \rd_ptr_reg_n_0_[0]\,
      I2 => \rd_ptr_reg_n_0_[1]\,
      O => nxt_rd_ptr(1)
    );
\rd_ptr_timing[2]_i_1__1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"AA6A"
    )
        port map (
      I0 => \rd_ptr_reg_n_0_[2]\,
      I1 => \rd_ptr_reg_n_0_[0]\,
      I2 => \rd_ptr_reg_n_0_[1]\,
      I3 => \rd_ptr_reg_n_0_[3]\,
      O => nxt_rd_ptr(2)
    );
\rd_ptr_timing[3]_i_1__1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \my_empty_reg[7]_0\,
      I1 => \my_empty_reg_n_0_[7]\,
      O => \rd_ptr_timing[3]_i_1__1_n_0\
    );
\rd_ptr_timing[3]_i_2__1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4000"
    )
        port map (
      I0 => \rd_ptr_reg_n_0_[3]\,
      I1 => \rd_ptr_reg_n_0_[1]\,
      I2 => \rd_ptr_reg_n_0_[0]\,
      I3 => \rd_ptr_reg_n_0_[2]\,
      O => nxt_rd_ptr(3)
    );
\rd_ptr_timing_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]_0\,
      CE => \rd_ptr_timing[3]_i_1__1_n_0\,
      D => nxt_rd_ptr(0),
      Q => rd_ptr_timing(0),
      R => ofifo_rst
    );
\rd_ptr_timing_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]_0\,
      CE => \rd_ptr_timing[3]_i_1__1_n_0\,
      D => nxt_rd_ptr(1),
      Q => rd_ptr_timing(1),
      R => ofifo_rst
    );
\rd_ptr_timing_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]_0\,
      CE => \rd_ptr_timing[3]_i_1__1_n_0\,
      D => nxt_rd_ptr(2),
      Q => rd_ptr_timing(2),
      R => ofifo_rst
    );
\rd_ptr_timing_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]_0\,
      CE => \rd_ptr_timing[3]_i_1__1_n_0\,
      D => nxt_rd_ptr(3),
      Q => rd_ptr_timing(3),
      R => ofifo_rst
    );
\wr_ptr[0]_i_1__3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => wr_ptr(3),
      I1 => wr_ptr(0),
      O => nxt_wr_ptr(0)
    );
\wr_ptr[1]_i_1__3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B4"
    )
        port map (
      I0 => wr_ptr(3),
      I1 => wr_ptr(0),
      I2 => wr_ptr(1),
      O => nxt_wr_ptr(1)
    );
\wr_ptr[2]_i_1__1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"AA6A"
    )
        port map (
      I0 => wr_ptr(2),
      I1 => wr_ptr(0),
      I2 => wr_ptr(1),
      I3 => wr_ptr(3),
      O => nxt_wr_ptr(2)
    );
\wr_ptr[3]_i_1__1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"082A"
    )
        port map (
      I0 => phy_data_wr_en,
      I1 => \my_empty_reg[7]_0\,
      I2 => \my_full_reg_n_0_[4]\,
      I3 => \my_empty_reg_n_0_[7]\,
      O => wr_ptr0
    );
\wr_ptr[3]_i_2__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4000"
    )
        port map (
      I0 => wr_ptr(3),
      I1 => wr_ptr(1),
      I2 => wr_ptr(0),
      I3 => wr_ptr(2),
      O => nxt_wr_ptr(3)
    );
\wr_ptr_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]_0\,
      CE => wr_ptr0,
      D => nxt_wr_ptr(0),
      Q => wr_ptr(0),
      R => ofifo_rst
    );
\wr_ptr_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]_0\,
      CE => wr_ptr0,
      D => nxt_wr_ptr(1),
      Q => wr_ptr(1),
      R => ofifo_rst
    );
\wr_ptr_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]_0\,
      CE => wr_ptr0,
      D => nxt_wr_ptr(2),
      Q => wr_ptr(2),
      R => ofifo_rst
    );
\wr_ptr_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]_0\,
      CE => wr_ptr0,
      D => nxt_wr_ptr(3),
      Q => wr_ptr(3),
      R => ofifo_rst
    );
\wr_ptr_timing_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]_0\,
      CE => wr_ptr0,
      D => nxt_wr_ptr(0),
      Q => wr_ptr_timing(0),
      R => ofifo_rst
    );
\wr_ptr_timing_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]_0\,
      CE => wr_ptr0,
      D => nxt_wr_ptr(1),
      Q => wr_ptr_timing(1),
      R => ofifo_rst
    );
\wr_ptr_timing_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]_0\,
      CE => wr_ptr0,
      D => nxt_wr_ptr(2),
      Q => wr_ptr_timing(2),
      R => ofifo_rst
    );
\wr_ptr_timing_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]_0\,
      CE => wr_ptr0,
      D => nxt_wr_ptr(3),
      Q => wr_ptr_timing(3),
      R => ofifo_rst
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \mig_mig_7series_v4_2_ddr_of_pre_fifo__parameterized1_40\ is
  port (
    \my_empty_reg[1]_0\ : out STD_LOGIC;
    \my_empty_reg[1]_1\ : out STD_LOGIC;
    D8 : out STD_LOGIC_VECTOR ( 7 downto 0 );
    D0 : out STD_LOGIC_VECTOR ( 7 downto 0 );
    \rd_ptr_reg[3]_0\ : out STD_LOGIC_VECTOR ( 63 downto 0 );
    Q : out STD_LOGIC_VECTOR ( 2 downto 0 );
    ofifo_rst : in STD_LOGIC;
    \my_full_reg[4]_0\ : in STD_LOGIC;
    \my_empty_reg[7]_0\ : in STD_LOGIC;
    phy_data_wr_en : in STD_LOGIC;
    out_fifo : in STD_LOGIC;
    out_fifo_0 : in STD_LOGIC_VECTOR ( 7 downto 0 );
    out_fifo_1 : in STD_LOGIC;
    phy_dout : in STD_LOGIC_VECTOR ( 71 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \mig_mig_7series_v4_2_ddr_of_pre_fifo__parameterized1_40\ : entity is "mig_7series_v4_2_ddr_of_pre_fifo";
end \mig_mig_7series_v4_2_ddr_of_pre_fifo__parameterized1_40\;

architecture STRUCTURE of \mig_mig_7series_v4_2_ddr_of_pre_fifo__parameterized1_40\ is
  signal \^q\ : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal \entry_cnt10_out__0\ : STD_LOGIC;
  signal \entry_cnt[0]_i_1_n_0\ : STD_LOGIC;
  signal \entry_cnt[1]_i_1_n_0\ : STD_LOGIC;
  signal \entry_cnt[2]_i_1_n_0\ : STD_LOGIC;
  signal \entry_cnt[3]_i_1_n_0\ : STD_LOGIC;
  signal \entry_cnt[4]_i_1_n_0\ : STD_LOGIC;
  signal \entry_cnt[4]_i_2_n_0\ : STD_LOGIC;
  signal \entry_cnt_reg_n_0_[0]\ : STD_LOGIC;
  signal \entry_cnt_reg_n_0_[1]\ : STD_LOGIC;
  signal mem_reg_0_15_0_5_n_0 : STD_LOGIC;
  signal mem_reg_0_15_0_5_n_1 : STD_LOGIC;
  signal mem_reg_0_15_0_5_n_2 : STD_LOGIC;
  signal mem_reg_0_15_0_5_n_3 : STD_LOGIC;
  signal mem_reg_0_15_0_5_n_4 : STD_LOGIC;
  signal mem_reg_0_15_0_5_n_5 : STD_LOGIC;
  signal mem_reg_0_15_60_65_n_4 : STD_LOGIC;
  signal mem_reg_0_15_60_65_n_5 : STD_LOGIC;
  signal mem_reg_0_15_66_71_n_0 : STD_LOGIC;
  signal mem_reg_0_15_66_71_n_1 : STD_LOGIC;
  signal mem_reg_0_15_66_71_n_2 : STD_LOGIC;
  signal mem_reg_0_15_66_71_n_3 : STD_LOGIC;
  signal mem_reg_0_15_66_71_n_4 : STD_LOGIC;
  signal mem_reg_0_15_66_71_n_5 : STD_LOGIC;
  signal mem_reg_0_15_6_11_n_0 : STD_LOGIC;
  signal mem_reg_0_15_6_11_n_1 : STD_LOGIC;
  signal my_empty0 : STD_LOGIC;
  signal \my_empty[1]_i_1__0_n_0\ : STD_LOGIC;
  signal \my_empty[7]_i_1__0_n_0\ : STD_LOGIC;
  signal \my_empty[7]_i_3__0_n_0\ : STD_LOGIC;
  signal \my_empty[7]_i_4__0_n_0\ : STD_LOGIC;
  signal \^my_empty_reg[1]_1\ : STD_LOGIC;
  signal \my_empty_reg_n_0_[7]\ : STD_LOGIC;
  signal my_full0 : STD_LOGIC;
  signal \my_full[4]_i_1__0_n_0\ : STD_LOGIC;
  signal \my_full[4]_i_3__0_n_0\ : STD_LOGIC;
  signal \my_full[4]_i_4__0_n_0\ : STD_LOGIC;
  signal \my_full_reg_n_0_[4]\ : STD_LOGIC;
  signal nxt_rd_ptr : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal nxt_wr_ptr : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \rd_ptr_reg_n_0_[0]\ : STD_LOGIC;
  signal \rd_ptr_reg_n_0_[1]\ : STD_LOGIC;
  signal \rd_ptr_reg_n_0_[2]\ : STD_LOGIC;
  signal \rd_ptr_reg_n_0_[3]\ : STD_LOGIC;
  signal rd_ptr_timing : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \rd_ptr_timing[3]_i_1__0_n_0\ : STD_LOGIC;
  signal wr_en : STD_LOGIC;
  attribute MAX_FANOUT : string;
  attribute MAX_FANOUT of wr_en : signal is "50";
  attribute RTL_MAX_FANOUT : string;
  attribute RTL_MAX_FANOUT of wr_en : signal is "found";
  signal wr_ptr : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal wr_ptr0 : STD_LOGIC;
  signal wr_ptr_timing : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal NLW_mem_reg_0_15_0_5_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_15_12_17_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_15_18_23_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_15_24_29_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_15_30_35_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_15_36_41_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_15_42_47_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_15_48_53_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_15_54_59_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_15_60_65_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_15_66_71_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_15_6_11_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_15_72_77_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_15_78_79_DOB_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_15_78_79_DOC_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_15_78_79_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \entry_cnt[0]_i_1\ : label is "soft_lutpair698";
  attribute SOFT_HLUTNM of \entry_cnt[1]_i_1\ : label is "soft_lutpair695";
  attribute SOFT_HLUTNM of \entry_cnt[3]_i_1\ : label is "soft_lutpair698";
  attribute SOFT_HLUTNM of \entry_cnt[4]_i_3\ : label is "soft_lutpair695";
  attribute METHODOLOGY_DRC_VIOS : string;
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_15_0_5 : label is "";
  attribute RTL_RAM_BITS : integer;
  attribute RTL_RAM_BITS of mem_reg_0_15_0_5 : label is 720;
  attribute RTL_RAM_NAME : string;
  attribute RTL_RAM_NAME of mem_reg_0_15_0_5 : label is "of_pre_fifo_gen.u_ddr_of_pre_fifo/mem";
  attribute ram_addr_begin : integer;
  attribute ram_addr_begin of mem_reg_0_15_0_5 : label is 0;
  attribute ram_addr_end : integer;
  attribute ram_addr_end of mem_reg_0_15_0_5 : label is 8;
  attribute ram_offset : integer;
  attribute ram_offset of mem_reg_0_15_0_5 : label is 0;
  attribute ram_slice_begin : integer;
  attribute ram_slice_begin of mem_reg_0_15_0_5 : label is 0;
  attribute ram_slice_end : integer;
  attribute ram_slice_end of mem_reg_0_15_0_5 : label is 5;
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_15_12_17 : label is "";
  attribute RTL_RAM_BITS of mem_reg_0_15_12_17 : label is 720;
  attribute RTL_RAM_NAME of mem_reg_0_15_12_17 : label is "of_pre_fifo_gen.u_ddr_of_pre_fifo/mem";
  attribute ram_addr_begin of mem_reg_0_15_12_17 : label is 0;
  attribute ram_addr_end of mem_reg_0_15_12_17 : label is 8;
  attribute ram_offset of mem_reg_0_15_12_17 : label is 0;
  attribute ram_slice_begin of mem_reg_0_15_12_17 : label is 12;
  attribute ram_slice_end of mem_reg_0_15_12_17 : label is 17;
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_15_18_23 : label is "";
  attribute RTL_RAM_BITS of mem_reg_0_15_18_23 : label is 720;
  attribute RTL_RAM_NAME of mem_reg_0_15_18_23 : label is "of_pre_fifo_gen.u_ddr_of_pre_fifo/mem";
  attribute ram_addr_begin of mem_reg_0_15_18_23 : label is 0;
  attribute ram_addr_end of mem_reg_0_15_18_23 : label is 8;
  attribute ram_offset of mem_reg_0_15_18_23 : label is 0;
  attribute ram_slice_begin of mem_reg_0_15_18_23 : label is 18;
  attribute ram_slice_end of mem_reg_0_15_18_23 : label is 23;
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_15_24_29 : label is "";
  attribute RTL_RAM_BITS of mem_reg_0_15_24_29 : label is 720;
  attribute RTL_RAM_NAME of mem_reg_0_15_24_29 : label is "of_pre_fifo_gen.u_ddr_of_pre_fifo/mem";
  attribute ram_addr_begin of mem_reg_0_15_24_29 : label is 0;
  attribute ram_addr_end of mem_reg_0_15_24_29 : label is 8;
  attribute ram_offset of mem_reg_0_15_24_29 : label is 0;
  attribute ram_slice_begin of mem_reg_0_15_24_29 : label is 24;
  attribute ram_slice_end of mem_reg_0_15_24_29 : label is 29;
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_15_30_35 : label is "";
  attribute RTL_RAM_BITS of mem_reg_0_15_30_35 : label is 720;
  attribute RTL_RAM_NAME of mem_reg_0_15_30_35 : label is "of_pre_fifo_gen.u_ddr_of_pre_fifo/mem";
  attribute ram_addr_begin of mem_reg_0_15_30_35 : label is 0;
  attribute ram_addr_end of mem_reg_0_15_30_35 : label is 8;
  attribute ram_offset of mem_reg_0_15_30_35 : label is 0;
  attribute ram_slice_begin of mem_reg_0_15_30_35 : label is 30;
  attribute ram_slice_end of mem_reg_0_15_30_35 : label is 35;
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_15_36_41 : label is "";
  attribute RTL_RAM_BITS of mem_reg_0_15_36_41 : label is 720;
  attribute RTL_RAM_NAME of mem_reg_0_15_36_41 : label is "of_pre_fifo_gen.u_ddr_of_pre_fifo/mem";
  attribute ram_addr_begin of mem_reg_0_15_36_41 : label is 0;
  attribute ram_addr_end of mem_reg_0_15_36_41 : label is 8;
  attribute ram_offset of mem_reg_0_15_36_41 : label is 0;
  attribute ram_slice_begin of mem_reg_0_15_36_41 : label is 36;
  attribute ram_slice_end of mem_reg_0_15_36_41 : label is 41;
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_15_42_47 : label is "";
  attribute RTL_RAM_BITS of mem_reg_0_15_42_47 : label is 720;
  attribute RTL_RAM_NAME of mem_reg_0_15_42_47 : label is "of_pre_fifo_gen.u_ddr_of_pre_fifo/mem";
  attribute ram_addr_begin of mem_reg_0_15_42_47 : label is 0;
  attribute ram_addr_end of mem_reg_0_15_42_47 : label is 8;
  attribute ram_offset of mem_reg_0_15_42_47 : label is 0;
  attribute ram_slice_begin of mem_reg_0_15_42_47 : label is 42;
  attribute ram_slice_end of mem_reg_0_15_42_47 : label is 47;
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_15_48_53 : label is "";
  attribute RTL_RAM_BITS of mem_reg_0_15_48_53 : label is 720;
  attribute RTL_RAM_NAME of mem_reg_0_15_48_53 : label is "of_pre_fifo_gen.u_ddr_of_pre_fifo/mem";
  attribute ram_addr_begin of mem_reg_0_15_48_53 : label is 0;
  attribute ram_addr_end of mem_reg_0_15_48_53 : label is 8;
  attribute ram_offset of mem_reg_0_15_48_53 : label is 0;
  attribute ram_slice_begin of mem_reg_0_15_48_53 : label is 48;
  attribute ram_slice_end of mem_reg_0_15_48_53 : label is 53;
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_15_54_59 : label is "";
  attribute RTL_RAM_BITS of mem_reg_0_15_54_59 : label is 720;
  attribute RTL_RAM_NAME of mem_reg_0_15_54_59 : label is "of_pre_fifo_gen.u_ddr_of_pre_fifo/mem";
  attribute ram_addr_begin of mem_reg_0_15_54_59 : label is 0;
  attribute ram_addr_end of mem_reg_0_15_54_59 : label is 8;
  attribute ram_offset of mem_reg_0_15_54_59 : label is 0;
  attribute ram_slice_begin of mem_reg_0_15_54_59 : label is 54;
  attribute ram_slice_end of mem_reg_0_15_54_59 : label is 59;
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_15_60_65 : label is "";
  attribute RTL_RAM_BITS of mem_reg_0_15_60_65 : label is 720;
  attribute RTL_RAM_NAME of mem_reg_0_15_60_65 : label is "of_pre_fifo_gen.u_ddr_of_pre_fifo/mem";
  attribute ram_addr_begin of mem_reg_0_15_60_65 : label is 0;
  attribute ram_addr_end of mem_reg_0_15_60_65 : label is 8;
  attribute ram_offset of mem_reg_0_15_60_65 : label is 0;
  attribute ram_slice_begin of mem_reg_0_15_60_65 : label is 60;
  attribute ram_slice_end of mem_reg_0_15_60_65 : label is 65;
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_15_66_71 : label is "";
  attribute RTL_RAM_BITS of mem_reg_0_15_66_71 : label is 720;
  attribute RTL_RAM_NAME of mem_reg_0_15_66_71 : label is "of_pre_fifo_gen.u_ddr_of_pre_fifo/mem";
  attribute ram_addr_begin of mem_reg_0_15_66_71 : label is 0;
  attribute ram_addr_end of mem_reg_0_15_66_71 : label is 8;
  attribute ram_offset of mem_reg_0_15_66_71 : label is 0;
  attribute ram_slice_begin of mem_reg_0_15_66_71 : label is 66;
  attribute ram_slice_end of mem_reg_0_15_66_71 : label is 71;
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_15_6_11 : label is "";
  attribute RTL_RAM_BITS of mem_reg_0_15_6_11 : label is 720;
  attribute RTL_RAM_NAME of mem_reg_0_15_6_11 : label is "of_pre_fifo_gen.u_ddr_of_pre_fifo/mem";
  attribute ram_addr_begin of mem_reg_0_15_6_11 : label is 0;
  attribute ram_addr_end of mem_reg_0_15_6_11 : label is 8;
  attribute ram_offset of mem_reg_0_15_6_11 : label is 0;
  attribute ram_slice_begin of mem_reg_0_15_6_11 : label is 6;
  attribute ram_slice_end of mem_reg_0_15_6_11 : label is 11;
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_15_72_77 : label is "";
  attribute RTL_RAM_BITS of mem_reg_0_15_72_77 : label is 720;
  attribute RTL_RAM_NAME of mem_reg_0_15_72_77 : label is "of_pre_fifo_gen.u_ddr_of_pre_fifo/mem";
  attribute ram_addr_begin of mem_reg_0_15_72_77 : label is 0;
  attribute ram_addr_end of mem_reg_0_15_72_77 : label is 8;
  attribute ram_offset of mem_reg_0_15_72_77 : label is 0;
  attribute ram_slice_begin of mem_reg_0_15_72_77 : label is 72;
  attribute ram_slice_end of mem_reg_0_15_72_77 : label is 77;
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_15_78_79 : label is "";
  attribute RTL_RAM_BITS of mem_reg_0_15_78_79 : label is 720;
  attribute RTL_RAM_NAME of mem_reg_0_15_78_79 : label is "of_pre_fifo_gen.u_ddr_of_pre_fifo/mem";
  attribute ram_addr_begin of mem_reg_0_15_78_79 : label is 0;
  attribute ram_addr_end of mem_reg_0_15_78_79 : label is 8;
  attribute ram_offset of mem_reg_0_15_78_79 : label is 0;
  attribute ram_slice_begin of mem_reg_0_15_78_79 : label is 78;
  attribute ram_slice_end of mem_reg_0_15_78_79 : label is 79;
  attribute SOFT_HLUTNM of \my_empty[7]_i_3__0\ : label is "soft_lutpair697";
  attribute SOFT_HLUTNM of \my_empty[7]_i_4__0\ : label is "soft_lutpair697";
  attribute syn_maxfan : string;
  attribute syn_maxfan of \my_empty_reg[1]\ : label is "3";
  attribute syn_maxfan of \my_empty_reg[7]\ : label is "3";
  attribute SOFT_HLUTNM of \my_full[4]_i_3__0\ : label is "soft_lutpair696";
  attribute SOFT_HLUTNM of \my_full[4]_i_4__0\ : label is "soft_lutpair696";
  attribute syn_maxfan of \my_full_reg[4]\ : label is "3";
  attribute SOFT_HLUTNM of \out_fifo_i_2__9\ : label is "soft_lutpair704";
  attribute SOFT_HLUTNM of \out_fifo_i_3__9\ : label is "soft_lutpair703";
  attribute SOFT_HLUTNM of \out_fifo_i_4__9\ : label is "soft_lutpair699";
  attribute SOFT_HLUTNM of \out_fifo_i_5__9\ : label is "soft_lutpair702";
  attribute SOFT_HLUTNM of out_fifo_i_66 : label is "soft_lutpair704";
  attribute SOFT_HLUTNM of out_fifo_i_67 : label is "soft_lutpair701";
  attribute SOFT_HLUTNM of out_fifo_i_68 : label is "soft_lutpair703";
  attribute SOFT_HLUTNM of out_fifo_i_69 : label is "soft_lutpair699";
  attribute SOFT_HLUTNM of \out_fifo_i_6__9\ : label is "soft_lutpair701";
  attribute SOFT_HLUTNM of out_fifo_i_70 : label is "soft_lutpair705";
  attribute SOFT_HLUTNM of out_fifo_i_71 : label is "soft_lutpair700";
  attribute SOFT_HLUTNM of out_fifo_i_72 : label is "soft_lutpair706";
  attribute SOFT_HLUTNM of out_fifo_i_73 : label is "soft_lutpair702";
  attribute SOFT_HLUTNM of \out_fifo_i_7__9\ : label is "soft_lutpair706";
  attribute SOFT_HLUTNM of \out_fifo_i_8__9\ : label is "soft_lutpair700";
  attribute SOFT_HLUTNM of \out_fifo_i_9__9\ : label is "soft_lutpair705";
  attribute syn_maxfan of \rd_ptr_reg[0]\ : label is "10";
  attribute syn_maxfan of \rd_ptr_reg[1]\ : label is "10";
  attribute syn_maxfan of \rd_ptr_reg[2]\ : label is "10";
  attribute syn_maxfan of \rd_ptr_reg[3]\ : label is "10";
  attribute SOFT_HLUTNM of \rd_ptr_timing[0]_i_1__1\ : label is "soft_lutpair710";
  attribute SOFT_HLUTNM of \rd_ptr_timing[1]_i_1__1\ : label is "soft_lutpair710";
  attribute SOFT_HLUTNM of \rd_ptr_timing[2]_i_1__0\ : label is "soft_lutpair708";
  attribute SOFT_HLUTNM of \rd_ptr_timing[3]_i_2__0\ : label is "soft_lutpair708";
  attribute KEEP : string;
  attribute KEEP of \rd_ptr_timing_reg[0]\ : label is "yes";
  attribute KEEP of \rd_ptr_timing_reg[1]\ : label is "yes";
  attribute KEEP of \rd_ptr_timing_reg[2]\ : label is "yes";
  attribute KEEP of \rd_ptr_timing_reg[3]\ : label is "yes";
  attribute SOFT_HLUTNM of \wr_ptr[0]_i_1__1\ : label is "soft_lutpair709";
  attribute SOFT_HLUTNM of \wr_ptr[1]_i_1__1\ : label is "soft_lutpair709";
  attribute SOFT_HLUTNM of \wr_ptr[2]_i_1__0\ : label is "soft_lutpair707";
  attribute SOFT_HLUTNM of \wr_ptr[3]_i_2\ : label is "soft_lutpair707";
  attribute syn_maxfan of \wr_ptr_reg[0]\ : label is "10";
  attribute syn_maxfan of \wr_ptr_reg[1]\ : label is "10";
  attribute syn_maxfan of \wr_ptr_reg[2]\ : label is "10";
  attribute syn_maxfan of \wr_ptr_reg[3]\ : label is "10";
  attribute KEEP of \wr_ptr_timing_reg[0]\ : label is "yes";
  attribute KEEP of \wr_ptr_timing_reg[1]\ : label is "yes";
  attribute KEEP of \wr_ptr_timing_reg[2]\ : label is "yes";
  attribute KEEP of \wr_ptr_timing_reg[3]\ : label is "yes";
begin
  Q(2 downto 0) <= \^q\(2 downto 0);
  \my_empty_reg[1]_1\ <= \^my_empty_reg[1]_1\;
\entry_cnt[0]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \entry_cnt_reg_n_0_[0]\,
      O => \entry_cnt[0]_i_1_n_0\
    );
\entry_cnt[1]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AA6A5595"
    )
        port map (
      I0 => \entry_cnt_reg_n_0_[0]\,
      I1 => \my_empty_reg[7]_0\,
      I2 => phy_data_wr_en,
      I3 => \my_full_reg_n_0_[4]\,
      I4 => \entry_cnt_reg_n_0_[1]\,
      O => \entry_cnt[1]_i_1_n_0\
    );
\entry_cnt[2]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FF7F0080AAEA5515"
    )
        port map (
      I0 => \entry_cnt_reg_n_0_[0]\,
      I1 => \my_empty_reg[7]_0\,
      I2 => phy_data_wr_en,
      I3 => \my_full_reg_n_0_[4]\,
      I4 => \^q\(0),
      I5 => \entry_cnt_reg_n_0_[1]\,
      O => \entry_cnt[2]_i_1_n_0\
    );
\entry_cnt[3]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"7F80FE01"
    )
        port map (
      I0 => \entry_cnt10_out__0\,
      I1 => \entry_cnt_reg_n_0_[0]\,
      I2 => \entry_cnt_reg_n_0_[1]\,
      I3 => \^q\(1),
      I4 => \^q\(0),
      O => \entry_cnt[3]_i_1_n_0\
    );
\entry_cnt[4]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"5003"
    )
        port map (
      I0 => \my_full_reg_n_0_[4]\,
      I1 => \my_empty_reg_n_0_[7]\,
      I2 => \my_empty_reg[7]_0\,
      I3 => phy_data_wr_en,
      O => \entry_cnt[4]_i_1_n_0\
    );
\entry_cnt[4]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"7FFF8000FFFE0001"
    )
        port map (
      I0 => \entry_cnt_reg_n_0_[1]\,
      I1 => \entry_cnt_reg_n_0_[0]\,
      I2 => \entry_cnt10_out__0\,
      I3 => \^q\(0),
      I4 => \^q\(2),
      I5 => \^q\(1),
      O => \entry_cnt[4]_i_2_n_0\
    );
\entry_cnt[4]_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"08"
    )
        port map (
      I0 => \my_empty_reg[7]_0\,
      I1 => phy_data_wr_en,
      I2 => \my_full_reg_n_0_[4]\,
      O => \entry_cnt10_out__0\
    );
\entry_cnt_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \my_full_reg[4]_0\,
      CE => \entry_cnt[4]_i_1_n_0\,
      D => \entry_cnt[0]_i_1_n_0\,
      Q => \entry_cnt_reg_n_0_[0]\,
      R => ofifo_rst
    );
\entry_cnt_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \my_full_reg[4]_0\,
      CE => \entry_cnt[4]_i_1_n_0\,
      D => \entry_cnt[1]_i_1_n_0\,
      Q => \entry_cnt_reg_n_0_[1]\,
      R => ofifo_rst
    );
\entry_cnt_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \my_full_reg[4]_0\,
      CE => \entry_cnt[4]_i_1_n_0\,
      D => \entry_cnt[2]_i_1_n_0\,
      Q => \^q\(0),
      R => ofifo_rst
    );
\entry_cnt_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => \my_full_reg[4]_0\,
      CE => \entry_cnt[4]_i_1_n_0\,
      D => \entry_cnt[3]_i_1_n_0\,
      Q => \^q\(1),
      R => ofifo_rst
    );
\entry_cnt_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => \my_full_reg[4]_0\,
      CE => \entry_cnt[4]_i_1_n_0\,
      D => \entry_cnt[4]_i_2_n_0\,
      Q => \^q\(2),
      R => ofifo_rst
    );
mem_reg_0_15_0_5: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4) => '0',
      ADDRA(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRA(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRA(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRA(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRB(4) => '0',
      ADDRB(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRB(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRB(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRB(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRC(4) => '0',
      ADDRC(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRC(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRC(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRC(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRD(4) => '0',
      ADDRD(3 downto 0) => wr_ptr(3 downto 0),
      DIA(1 downto 0) => phy_dout(1 downto 0),
      DIB(1 downto 0) => phy_dout(3 downto 2),
      DIC(1 downto 0) => phy_dout(5 downto 4),
      DID(1 downto 0) => B"00",
      DOA(1) => mem_reg_0_15_0_5_n_0,
      DOA(0) => mem_reg_0_15_0_5_n_1,
      DOB(1) => mem_reg_0_15_0_5_n_2,
      DOB(0) => mem_reg_0_15_0_5_n_3,
      DOC(1) => mem_reg_0_15_0_5_n_4,
      DOC(0) => mem_reg_0_15_0_5_n_5,
      DOD(1 downto 0) => NLW_mem_reg_0_15_0_5_DOD_UNCONNECTED(1 downto 0),
      WCLK => \my_full_reg[4]_0\,
      WE => wr_en
    );
mem_reg_0_15_0_5_i_1: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2700"
    )
        port map (
      I0 => \my_empty_reg[7]_0\,
      I1 => \my_full_reg_n_0_[4]\,
      I2 => \^my_empty_reg[1]_1\,
      I3 => phy_data_wr_en,
      O => wr_en
    );
mem_reg_0_15_12_17: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4) => '0',
      ADDRA(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRA(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRA(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRA(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRB(4) => '0',
      ADDRB(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRB(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRB(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRB(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRC(4) => '0',
      ADDRC(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRC(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRC(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRC(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRD(4) => '0',
      ADDRD(3 downto 0) => wr_ptr(3 downto 0),
      DIA(1 downto 0) => phy_dout(13 downto 12),
      DIB(1 downto 0) => phy_dout(15 downto 14),
      DIC(1 downto 0) => phy_dout(17 downto 16),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => \rd_ptr_reg[3]_0\(5 downto 4),
      DOB(1 downto 0) => \rd_ptr_reg[3]_0\(7 downto 6),
      DOC(1 downto 0) => \rd_ptr_reg[3]_0\(9 downto 8),
      DOD(1 downto 0) => NLW_mem_reg_0_15_12_17_DOD_UNCONNECTED(1 downto 0),
      WCLK => \my_full_reg[4]_0\,
      WE => wr_en
    );
mem_reg_0_15_18_23: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4) => '0',
      ADDRA(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRA(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRA(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRA(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRB(4) => '0',
      ADDRB(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRB(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRB(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRB(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRC(4) => '0',
      ADDRC(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRC(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRC(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRC(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRD(4) => '0',
      ADDRD(3 downto 0) => wr_ptr(3 downto 0),
      DIA(1 downto 0) => phy_dout(19 downto 18),
      DIB(1 downto 0) => phy_dout(21 downto 20),
      DIC(1 downto 0) => phy_dout(23 downto 22),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => \rd_ptr_reg[3]_0\(11 downto 10),
      DOB(1 downto 0) => \rd_ptr_reg[3]_0\(13 downto 12),
      DOC(1 downto 0) => \rd_ptr_reg[3]_0\(15 downto 14),
      DOD(1 downto 0) => NLW_mem_reg_0_15_18_23_DOD_UNCONNECTED(1 downto 0),
      WCLK => \my_full_reg[4]_0\,
      WE => wr_en
    );
mem_reg_0_15_24_29: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4) => '0',
      ADDRA(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRA(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRA(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRA(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRB(4) => '0',
      ADDRB(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRB(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRB(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRB(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRC(4) => '0',
      ADDRC(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRC(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRC(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRC(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRD(4) => '0',
      ADDRD(3 downto 0) => wr_ptr(3 downto 0),
      DIA(1 downto 0) => phy_dout(25 downto 24),
      DIB(1 downto 0) => phy_dout(27 downto 26),
      DIC(1 downto 0) => phy_dout(29 downto 28),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => \rd_ptr_reg[3]_0\(17 downto 16),
      DOB(1 downto 0) => \rd_ptr_reg[3]_0\(19 downto 18),
      DOC(1 downto 0) => \rd_ptr_reg[3]_0\(21 downto 20),
      DOD(1 downto 0) => NLW_mem_reg_0_15_24_29_DOD_UNCONNECTED(1 downto 0),
      WCLK => \my_full_reg[4]_0\,
      WE => wr_en
    );
mem_reg_0_15_30_35: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4) => '0',
      ADDRA(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRA(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRA(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRA(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRB(4) => '0',
      ADDRB(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRB(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRB(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRB(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRC(4) => '0',
      ADDRC(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRC(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRC(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRC(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRD(4) => '0',
      ADDRD(3 downto 0) => wr_ptr(3 downto 0),
      DIA(1 downto 0) => phy_dout(31 downto 30),
      DIB(1 downto 0) => phy_dout(33 downto 32),
      DIC(1 downto 0) => phy_dout(35 downto 34),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => \rd_ptr_reg[3]_0\(23 downto 22),
      DOB(1 downto 0) => \rd_ptr_reg[3]_0\(25 downto 24),
      DOC(1 downto 0) => \rd_ptr_reg[3]_0\(27 downto 26),
      DOD(1 downto 0) => NLW_mem_reg_0_15_30_35_DOD_UNCONNECTED(1 downto 0),
      WCLK => \my_full_reg[4]_0\,
      WE => wr_en
    );
mem_reg_0_15_36_41: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4) => '0',
      ADDRA(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRA(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRA(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRA(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRB(4) => '0',
      ADDRB(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRB(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRB(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRB(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRC(4) => '0',
      ADDRC(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRC(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRC(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRC(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRD(4) => '0',
      ADDRD(3 downto 0) => wr_ptr(3 downto 0),
      DIA(1 downto 0) => phy_dout(37 downto 36),
      DIB(1 downto 0) => phy_dout(39 downto 38),
      DIC(1 downto 0) => phy_dout(41 downto 40),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => \rd_ptr_reg[3]_0\(29 downto 28),
      DOB(1 downto 0) => \rd_ptr_reg[3]_0\(31 downto 30),
      DOC(1 downto 0) => \rd_ptr_reg[3]_0\(33 downto 32),
      DOD(1 downto 0) => NLW_mem_reg_0_15_36_41_DOD_UNCONNECTED(1 downto 0),
      WCLK => \my_full_reg[4]_0\,
      WE => wr_en
    );
mem_reg_0_15_42_47: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4) => '0',
      ADDRA(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRA(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRA(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRA(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRB(4) => '0',
      ADDRB(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRB(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRB(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRB(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRC(4) => '0',
      ADDRC(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRC(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRC(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRC(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRD(4) => '0',
      ADDRD(3 downto 0) => wr_ptr(3 downto 0),
      DIA(1 downto 0) => phy_dout(43 downto 42),
      DIB(1 downto 0) => phy_dout(45 downto 44),
      DIC(1 downto 0) => phy_dout(47 downto 46),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => \rd_ptr_reg[3]_0\(35 downto 34),
      DOB(1 downto 0) => \rd_ptr_reg[3]_0\(37 downto 36),
      DOC(1 downto 0) => \rd_ptr_reg[3]_0\(39 downto 38),
      DOD(1 downto 0) => NLW_mem_reg_0_15_42_47_DOD_UNCONNECTED(1 downto 0),
      WCLK => \my_full_reg[4]_0\,
      WE => wr_en
    );
mem_reg_0_15_48_53: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4) => '0',
      ADDRA(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRA(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRA(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRA(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRB(4) => '0',
      ADDRB(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRB(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRB(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRB(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRC(4) => '0',
      ADDRC(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRC(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRC(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRC(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRD(4) => '0',
      ADDRD(3 downto 0) => wr_ptr(3 downto 0),
      DIA(1 downto 0) => phy_dout(49 downto 48),
      DIB(1 downto 0) => phy_dout(51 downto 50),
      DIC(1 downto 0) => phy_dout(53 downto 52),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => \rd_ptr_reg[3]_0\(41 downto 40),
      DOB(1 downto 0) => \rd_ptr_reg[3]_0\(43 downto 42),
      DOC(1 downto 0) => \rd_ptr_reg[3]_0\(45 downto 44),
      DOD(1 downto 0) => NLW_mem_reg_0_15_48_53_DOD_UNCONNECTED(1 downto 0),
      WCLK => \my_full_reg[4]_0\,
      WE => wr_en
    );
mem_reg_0_15_54_59: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4) => '0',
      ADDRA(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRA(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRA(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRA(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRB(4) => '0',
      ADDRB(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRB(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRB(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRB(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRC(4) => '0',
      ADDRC(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRC(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRC(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRC(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRD(4) => '0',
      ADDRD(3 downto 0) => wr_ptr(3 downto 0),
      DIA(1 downto 0) => phy_dout(55 downto 54),
      DIB(1 downto 0) => phy_dout(57 downto 56),
      DIC(1 downto 0) => phy_dout(59 downto 58),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => \rd_ptr_reg[3]_0\(47 downto 46),
      DOB(1 downto 0) => \rd_ptr_reg[3]_0\(49 downto 48),
      DOC(1 downto 0) => \rd_ptr_reg[3]_0\(51 downto 50),
      DOD(1 downto 0) => NLW_mem_reg_0_15_54_59_DOD_UNCONNECTED(1 downto 0),
      WCLK => \my_full_reg[4]_0\,
      WE => wr_en
    );
mem_reg_0_15_60_65: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4) => '0',
      ADDRA(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRA(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRA(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRA(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRB(4) => '0',
      ADDRB(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRB(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRB(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRB(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRC(4) => '0',
      ADDRC(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRC(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRC(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRC(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRD(4) => '0',
      ADDRD(3 downto 0) => wr_ptr(3 downto 0),
      DIA(1 downto 0) => phy_dout(61 downto 60),
      DIB(1 downto 0) => phy_dout(63 downto 62),
      DIC(1 downto 0) => B"00",
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => \rd_ptr_reg[3]_0\(53 downto 52),
      DOB(1 downto 0) => \rd_ptr_reg[3]_0\(55 downto 54),
      DOC(1) => mem_reg_0_15_60_65_n_4,
      DOC(0) => mem_reg_0_15_60_65_n_5,
      DOD(1 downto 0) => NLW_mem_reg_0_15_60_65_DOD_UNCONNECTED(1 downto 0),
      WCLK => \my_full_reg[4]_0\,
      WE => wr_en
    );
mem_reg_0_15_66_71: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4) => '0',
      ADDRA(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRA(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRA(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRA(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRB(4) => '0',
      ADDRB(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRB(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRB(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRB(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRC(4) => '0',
      ADDRC(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRC(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRC(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRC(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRD(4) => '0',
      ADDRD(3 downto 0) => wr_ptr(3 downto 0),
      DIA(1 downto 0) => B"00",
      DIB(1 downto 0) => B"00",
      DIC(1 downto 0) => B"00",
      DID(1 downto 0) => B"00",
      DOA(1) => mem_reg_0_15_66_71_n_0,
      DOA(0) => mem_reg_0_15_66_71_n_1,
      DOB(1) => mem_reg_0_15_66_71_n_2,
      DOB(0) => mem_reg_0_15_66_71_n_3,
      DOC(1) => mem_reg_0_15_66_71_n_4,
      DOC(0) => mem_reg_0_15_66_71_n_5,
      DOD(1 downto 0) => NLW_mem_reg_0_15_66_71_DOD_UNCONNECTED(1 downto 0),
      WCLK => \my_full_reg[4]_0\,
      WE => wr_en
    );
mem_reg_0_15_6_11: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4) => '0',
      ADDRA(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRA(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRA(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRA(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRB(4) => '0',
      ADDRB(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRB(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRB(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRB(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRC(4) => '0',
      ADDRC(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRC(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRC(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRC(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRD(4) => '0',
      ADDRD(3 downto 0) => wr_ptr(3 downto 0),
      DIA(1 downto 0) => phy_dout(7 downto 6),
      DIB(1 downto 0) => phy_dout(9 downto 8),
      DIC(1 downto 0) => phy_dout(11 downto 10),
      DID(1 downto 0) => B"00",
      DOA(1) => mem_reg_0_15_6_11_n_0,
      DOA(0) => mem_reg_0_15_6_11_n_1,
      DOB(1 downto 0) => \rd_ptr_reg[3]_0\(1 downto 0),
      DOC(1 downto 0) => \rd_ptr_reg[3]_0\(3 downto 2),
      DOD(1 downto 0) => NLW_mem_reg_0_15_6_11_DOD_UNCONNECTED(1 downto 0),
      WCLK => \my_full_reg[4]_0\,
      WE => wr_en
    );
mem_reg_0_15_72_77: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4) => '0',
      ADDRA(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRA(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRA(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRA(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRB(4) => '0',
      ADDRB(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRB(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRB(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRB(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRC(4) => '0',
      ADDRC(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRC(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRC(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRC(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRD(4) => '0',
      ADDRD(3 downto 0) => wr_ptr(3 downto 0),
      DIA(1 downto 0) => phy_dout(65 downto 64),
      DIB(1 downto 0) => phy_dout(67 downto 66),
      DIC(1 downto 0) => phy_dout(69 downto 68),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => \rd_ptr_reg[3]_0\(57 downto 56),
      DOB(1 downto 0) => \rd_ptr_reg[3]_0\(59 downto 58),
      DOC(1 downto 0) => \rd_ptr_reg[3]_0\(61 downto 60),
      DOD(1 downto 0) => NLW_mem_reg_0_15_72_77_DOD_UNCONNECTED(1 downto 0),
      WCLK => \my_full_reg[4]_0\,
      WE => wr_en
    );
mem_reg_0_15_78_79: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4) => '0',
      ADDRA(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRA(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRA(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRA(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRB(4) => '0',
      ADDRB(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRB(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRB(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRB(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRC(4) => '0',
      ADDRC(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRC(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRC(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRC(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRD(4) => '0',
      ADDRD(3 downto 0) => wr_ptr(3 downto 0),
      DIA(1 downto 0) => phy_dout(71 downto 70),
      DIB(1 downto 0) => B"00",
      DIC(1 downto 0) => B"00",
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => \rd_ptr_reg[3]_0\(63 downto 62),
      DOB(1 downto 0) => NLW_mem_reg_0_15_78_79_DOB_UNCONNECTED(1 downto 0),
      DOC(1 downto 0) => NLW_mem_reg_0_15_78_79_DOC_UNCONNECTED(1 downto 0),
      DOD(1 downto 0) => NLW_mem_reg_0_15_78_79_DOD_UNCONNECTED(1 downto 0),
      WCLK => \my_full_reg[4]_0\,
      WE => wr_en
    );
\my_empty[1]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFF701F700"
    )
        port map (
      I0 => \my_empty_reg[7]_0\,
      I1 => phy_data_wr_en,
      I2 => \my_full_reg_n_0_[4]\,
      I3 => \^my_empty_reg[1]_1\,
      I4 => my_empty0,
      I5 => ofifo_rst,
      O => \my_empty[1]_i_1__0_n_0\
    );
\my_empty[7]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFF701F700"
    )
        port map (
      I0 => \my_empty_reg[7]_0\,
      I1 => phy_data_wr_en,
      I2 => \my_full_reg_n_0_[4]\,
      I3 => \my_empty_reg_n_0_[7]\,
      I4 => my_empty0,
      I5 => ofifo_rst,
      O => \my_empty[7]_i_1__0_n_0\
    );
\my_empty[7]_i_2__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"4A400D08"
    )
        port map (
      I0 => wr_ptr_timing(2),
      I1 => \my_empty[7]_i_3__0_n_0\,
      I2 => wr_ptr_timing(3),
      I3 => \my_empty[7]_i_4__0_n_0\,
      I4 => \rd_ptr_reg_n_0_[2]\,
      O => my_empty0
    );
\my_empty[7]_i_3__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000040"
    )
        port map (
      I0 => wr_ptr_timing(1),
      I1 => \rd_ptr_reg_n_0_[0]\,
      I2 => \rd_ptr_reg_n_0_[1]\,
      I3 => \rd_ptr_reg_n_0_[3]\,
      I4 => wr_ptr_timing(0),
      O => \my_empty[7]_i_3__0_n_0\
    );
\my_empty[7]_i_4__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"84210842"
    )
        port map (
      I0 => wr_ptr_timing(0),
      I1 => wr_ptr_timing(1),
      I2 => \rd_ptr_reg_n_0_[0]\,
      I3 => \rd_ptr_reg_n_0_[1]\,
      I4 => \rd_ptr_reg_n_0_[3]\,
      O => \my_empty[7]_i_4__0_n_0\
    );
\my_empty_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \my_full_reg[4]_0\,
      CE => '1',
      D => \my_empty[1]_i_1__0_n_0\,
      Q => \^my_empty_reg[1]_1\,
      R => '0'
    );
\my_empty_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => \my_full_reg[4]_0\,
      CE => '1',
      D => \my_empty[7]_i_1__0_n_0\,
      Q => \my_empty_reg_n_0_[7]\,
      R => '0'
    );
\my_full[4]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000FFFC0080"
    )
        port map (
      I0 => my_full0,
      I1 => phy_data_wr_en,
      I2 => \my_empty_reg[7]_0\,
      I3 => \my_empty_reg_n_0_[7]\,
      I4 => \my_full_reg_n_0_[4]\,
      I5 => ofifo_rst,
      O => \my_full[4]_i_1__0_n_0\
    );
\my_full[4]_i_2__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"4A400D08"
    )
        port map (
      I0 => rd_ptr_timing(2),
      I1 => \my_full[4]_i_3__0_n_0\,
      I2 => rd_ptr_timing(3),
      I3 => \my_full[4]_i_4__0_n_0\,
      I4 => wr_ptr(2),
      O => my_full0
    );
\my_full[4]_i_3__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000040"
    )
        port map (
      I0 => rd_ptr_timing(1),
      I1 => wr_ptr(0),
      I2 => wr_ptr(1),
      I3 => wr_ptr(3),
      I4 => rd_ptr_timing(0),
      O => \my_full[4]_i_3__0_n_0\
    );
\my_full[4]_i_4__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"84210842"
    )
        port map (
      I0 => rd_ptr_timing(0),
      I1 => rd_ptr_timing(1),
      I2 => wr_ptr(0),
      I3 => wr_ptr(1),
      I4 => wr_ptr(3),
      O => \my_full[4]_i_4__0_n_0\
    );
\my_full_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => \my_full_reg[4]_0\,
      CE => '1',
      D => \my_full[4]_i_1__0_n_0\,
      Q => \my_full_reg_n_0_[4]\,
      R => '0'
    );
\out_fifo_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"0D"
    )
        port map (
      I0 => \^my_empty_reg[1]_1\,
      I1 => phy_data_wr_en,
      I2 => \my_empty_reg[7]_0\,
      O => \my_empty_reg[1]_0\
    );
\out_fifo_i_2__9\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"88F0"
    )
        port map (
      I0 => out_fifo_1,
      I1 => out_fifo_0(7),
      I2 => mem_reg_0_15_6_11_n_0,
      I3 => \^my_empty_reg[1]_1\,
      O => D0(7)
    );
\out_fifo_i_3__9\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"88F0"
    )
        port map (
      I0 => out_fifo_1,
      I1 => out_fifo_0(6),
      I2 => mem_reg_0_15_6_11_n_1,
      I3 => \^my_empty_reg[1]_1\,
      O => D0(6)
    );
\out_fifo_i_4__9\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"88F0"
    )
        port map (
      I0 => out_fifo_1,
      I1 => out_fifo_0(5),
      I2 => mem_reg_0_15_0_5_n_4,
      I3 => \^my_empty_reg[1]_1\,
      O => D0(5)
    );
\out_fifo_i_5__9\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"88F0"
    )
        port map (
      I0 => out_fifo_1,
      I1 => out_fifo_0(4),
      I2 => mem_reg_0_15_0_5_n_5,
      I3 => \^my_empty_reg[1]_1\,
      O => D0(4)
    );
out_fifo_i_66: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => mem_reg_0_15_66_71_n_4,
      I1 => \^my_empty_reg[1]_1\,
      O => D8(7)
    );
out_fifo_i_67: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => mem_reg_0_15_66_71_n_5,
      I1 => \^my_empty_reg[1]_1\,
      O => D8(6)
    );
out_fifo_i_68: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => mem_reg_0_15_66_71_n_2,
      I1 => \^my_empty_reg[1]_1\,
      O => D8(5)
    );
out_fifo_i_69: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => mem_reg_0_15_66_71_n_3,
      I1 => \^my_empty_reg[1]_1\,
      O => D8(4)
    );
\out_fifo_i_6__9\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"88F0"
    )
        port map (
      I0 => out_fifo_1,
      I1 => out_fifo_0(3),
      I2 => mem_reg_0_15_0_5_n_2,
      I3 => \^my_empty_reg[1]_1\,
      O => D0(3)
    );
out_fifo_i_70: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => mem_reg_0_15_66_71_n_0,
      I1 => \^my_empty_reg[1]_1\,
      O => D8(3)
    );
out_fifo_i_71: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => mem_reg_0_15_66_71_n_1,
      I1 => \^my_empty_reg[1]_1\,
      O => D8(2)
    );
out_fifo_i_72: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => mem_reg_0_15_60_65_n_4,
      I1 => \^my_empty_reg[1]_1\,
      O => D8(1)
    );
out_fifo_i_73: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => mem_reg_0_15_60_65_n_5,
      I1 => \^my_empty_reg[1]_1\,
      O => D8(0)
    );
\out_fifo_i_7__9\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"88F0"
    )
        port map (
      I0 => out_fifo_1,
      I1 => out_fifo_0(2),
      I2 => mem_reg_0_15_0_5_n_3,
      I3 => \^my_empty_reg[1]_1\,
      O => D0(2)
    );
\out_fifo_i_8__9\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"88F0"
    )
        port map (
      I0 => out_fifo,
      I1 => out_fifo_0(1),
      I2 => mem_reg_0_15_0_5_n_0,
      I3 => \^my_empty_reg[1]_1\,
      O => D0(1)
    );
\out_fifo_i_9__9\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"88F0"
    )
        port map (
      I0 => out_fifo,
      I1 => out_fifo_0(0),
      I2 => mem_reg_0_15_0_5_n_1,
      I3 => \^my_empty_reg[1]_1\,
      O => D0(0)
    );
\rd_ptr_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \my_full_reg[4]_0\,
      CE => \rd_ptr_timing[3]_i_1__0_n_0\,
      D => nxt_rd_ptr(0),
      Q => \rd_ptr_reg_n_0_[0]\,
      R => ofifo_rst
    );
\rd_ptr_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \my_full_reg[4]_0\,
      CE => \rd_ptr_timing[3]_i_1__0_n_0\,
      D => nxt_rd_ptr(1),
      Q => \rd_ptr_reg_n_0_[1]\,
      R => ofifo_rst
    );
\rd_ptr_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \my_full_reg[4]_0\,
      CE => \rd_ptr_timing[3]_i_1__0_n_0\,
      D => nxt_rd_ptr(2),
      Q => \rd_ptr_reg_n_0_[2]\,
      R => ofifo_rst
    );
\rd_ptr_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => \my_full_reg[4]_0\,
      CE => \rd_ptr_timing[3]_i_1__0_n_0\,
      D => nxt_rd_ptr(3),
      Q => \rd_ptr_reg_n_0_[3]\,
      R => ofifo_rst
    );
\rd_ptr_timing[0]_i_1__1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => \rd_ptr_reg_n_0_[3]\,
      I1 => \rd_ptr_reg_n_0_[0]\,
      O => nxt_rd_ptr(0)
    );
\rd_ptr_timing[1]_i_1__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B4"
    )
        port map (
      I0 => \rd_ptr_reg_n_0_[3]\,
      I1 => \rd_ptr_reg_n_0_[0]\,
      I2 => \rd_ptr_reg_n_0_[1]\,
      O => nxt_rd_ptr(1)
    );
\rd_ptr_timing[2]_i_1__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"AA6A"
    )
        port map (
      I0 => \rd_ptr_reg_n_0_[2]\,
      I1 => \rd_ptr_reg_n_0_[0]\,
      I2 => \rd_ptr_reg_n_0_[1]\,
      I3 => \rd_ptr_reg_n_0_[3]\,
      O => nxt_rd_ptr(2)
    );
\rd_ptr_timing[3]_i_1__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \my_empty_reg[7]_0\,
      I1 => \my_empty_reg_n_0_[7]\,
      O => \rd_ptr_timing[3]_i_1__0_n_0\
    );
\rd_ptr_timing[3]_i_2__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4000"
    )
        port map (
      I0 => \rd_ptr_reg_n_0_[3]\,
      I1 => \rd_ptr_reg_n_0_[1]\,
      I2 => \rd_ptr_reg_n_0_[0]\,
      I3 => \rd_ptr_reg_n_0_[2]\,
      O => nxt_rd_ptr(3)
    );
\rd_ptr_timing_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \my_full_reg[4]_0\,
      CE => \rd_ptr_timing[3]_i_1__0_n_0\,
      D => nxt_rd_ptr(0),
      Q => rd_ptr_timing(0),
      R => ofifo_rst
    );
\rd_ptr_timing_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \my_full_reg[4]_0\,
      CE => \rd_ptr_timing[3]_i_1__0_n_0\,
      D => nxt_rd_ptr(1),
      Q => rd_ptr_timing(1),
      R => ofifo_rst
    );
\rd_ptr_timing_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \my_full_reg[4]_0\,
      CE => \rd_ptr_timing[3]_i_1__0_n_0\,
      D => nxt_rd_ptr(2),
      Q => rd_ptr_timing(2),
      R => ofifo_rst
    );
\rd_ptr_timing_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => \my_full_reg[4]_0\,
      CE => \rd_ptr_timing[3]_i_1__0_n_0\,
      D => nxt_rd_ptr(3),
      Q => rd_ptr_timing(3),
      R => ofifo_rst
    );
\wr_ptr[0]_i_1__1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => wr_ptr(3),
      I1 => wr_ptr(0),
      O => nxt_wr_ptr(0)
    );
\wr_ptr[1]_i_1__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B4"
    )
        port map (
      I0 => wr_ptr(3),
      I1 => wr_ptr(0),
      I2 => wr_ptr(1),
      O => nxt_wr_ptr(1)
    );
\wr_ptr[2]_i_1__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"AA6A"
    )
        port map (
      I0 => wr_ptr(2),
      I1 => wr_ptr(0),
      I2 => wr_ptr(1),
      I3 => wr_ptr(3),
      O => nxt_wr_ptr(2)
    );
\wr_ptr[3]_i_1__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"082A"
    )
        port map (
      I0 => phy_data_wr_en,
      I1 => \my_empty_reg[7]_0\,
      I2 => \my_full_reg_n_0_[4]\,
      I3 => \my_empty_reg_n_0_[7]\,
      O => wr_ptr0
    );
\wr_ptr[3]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4000"
    )
        port map (
      I0 => wr_ptr(3),
      I1 => wr_ptr(1),
      I2 => wr_ptr(0),
      I3 => wr_ptr(2),
      O => nxt_wr_ptr(3)
    );
\wr_ptr_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \my_full_reg[4]_0\,
      CE => wr_ptr0,
      D => nxt_wr_ptr(0),
      Q => wr_ptr(0),
      R => ofifo_rst
    );
\wr_ptr_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \my_full_reg[4]_0\,
      CE => wr_ptr0,
      D => nxt_wr_ptr(1),
      Q => wr_ptr(1),
      R => ofifo_rst
    );
\wr_ptr_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \my_full_reg[4]_0\,
      CE => wr_ptr0,
      D => nxt_wr_ptr(2),
      Q => wr_ptr(2),
      R => ofifo_rst
    );
\wr_ptr_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => \my_full_reg[4]_0\,
      CE => wr_ptr0,
      D => nxt_wr_ptr(3),
      Q => wr_ptr(3),
      R => ofifo_rst
    );
\wr_ptr_timing_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \my_full_reg[4]_0\,
      CE => wr_ptr0,
      D => nxt_wr_ptr(0),
      Q => wr_ptr_timing(0),
      R => ofifo_rst
    );
\wr_ptr_timing_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \my_full_reg[4]_0\,
      CE => wr_ptr0,
      D => nxt_wr_ptr(1),
      Q => wr_ptr_timing(1),
      R => ofifo_rst
    );
\wr_ptr_timing_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \my_full_reg[4]_0\,
      CE => wr_ptr0,
      D => nxt_wr_ptr(2),
      Q => wr_ptr_timing(2),
      R => ofifo_rst
    );
\wr_ptr_timing_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => \my_full_reg[4]_0\,
      CE => wr_ptr0,
      D => nxt_wr_ptr(3),
      Q => wr_ptr_timing(3),
      R => ofifo_rst
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mig_mig_7series_v4_2_ddr_phy_ck_addr_cmd_delay is
  port (
    ck_addr_cmd_delay_done : out STD_LOGIC;
    cmd_po_en_stg2_f : out STD_LOGIC;
    po_cnt_dec_2 : out STD_LOGIC;
    delaydec_cnt_r10_in : out STD_LOGIC;
    ctl_lane_cnt : out STD_LOGIC_VECTOR ( 2 downto 0 );
    E : out STD_LOGIC_VECTOR ( 0 to 0 );
    delay_done_r4_reg_0 : in STD_LOGIC;
    po_en_stg2_f_reg_0 : in STD_LOGIC;
    pi_fine_dly_dec_done : in STD_LOGIC;
    dqs_po_dec_done : in STD_LOGIC;
    \ctl_lane_cnt_reg[1]_0\ : in STD_LOGIC;
    \gen_byte_sel_div2.byte_sel_cnt_reg[0]\ : in STD_LOGIC;
    tempmon_sel_pi_incdec : in STD_LOGIC;
    \gen_byte_sel_div2.byte_sel_cnt_reg[0]_0\ : in STD_LOGIC;
    \gen_byte_sel_div2.byte_sel_cnt_reg[0]_1\ : in STD_LOGIC;
    \gen_byte_sel_div2.byte_sel_cnt_reg[0]_2\ : in STD_LOGIC;
    cmd_delay_start0 : in STD_LOGIC;
    p_1_in : in STD_LOGIC;
    SS : in STD_LOGIC_VECTOR ( 0 to 0 );
    \wait_cnt_r_reg[0]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of mig_mig_7series_v4_2_ddr_phy_ck_addr_cmd_delay : entity is "mig_7series_v4_2_ddr_phy_ck_addr_cmd_delay";
end mig_mig_7series_v4_2_ddr_phy_ck_addr_cmd_delay;

architecture STRUCTURE of mig_mig_7series_v4_2_ddr_phy_ck_addr_cmd_delay is
  signal \^ck_addr_cmd_delay_done\ : STD_LOGIC;
  signal \^ctl_lane_cnt\ : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal ctl_lane_cnt1 : STD_LOGIC;
  signal \ctl_lane_cnt[0]_i_1_n_0\ : STD_LOGIC;
  signal \ctl_lane_cnt[1]_i_1_n_0\ : STD_LOGIC;
  signal \ctl_lane_cnt[2]_i_1_n_0\ : STD_LOGIC;
  signal \ctl_lane_cnt[2]_i_5_n_0\ : STD_LOGIC;
  signal delay_dec_done : STD_LOGIC;
  signal delay_dec_done_i_1_n_0 : STD_LOGIC;
  signal delay_dec_done_i_2_n_0 : STD_LOGIC;
  signal delay_done_r3_reg_srl3_n_0 : STD_LOGIC;
  signal delaydec_cnt_r0 : STD_LOGIC;
  signal \^delaydec_cnt_r10_in\ : STD_LOGIC;
  signal \delaydec_cnt_r[0]_i_1_n_0\ : STD_LOGIC;
  signal \delaydec_cnt_r[1]_i_1_n_0\ : STD_LOGIC;
  signal \delaydec_cnt_r[2]_i_1_n_0\ : STD_LOGIC;
  signal \delaydec_cnt_r[3]_i_1_n_0\ : STD_LOGIC;
  signal \delaydec_cnt_r[4]_i_1_n_0\ : STD_LOGIC;
  signal \delaydec_cnt_r[5]_i_3_n_0\ : STD_LOGIC;
  signal delaydec_cnt_r_reg : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal \^po_cnt_dec_2\ : STD_LOGIC;
  signal \po_cnt_dec_i_1__0_n_0\ : STD_LOGIC;
  signal po_cnt_inc1 : STD_LOGIC;
  signal po_cnt_inc2 : STD_LOGIC;
  signal wait_cnt_r0 : STD_LOGIC;
  signal \wait_cnt_r0__0\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \wait_cnt_r[1]_i_1_n_0\ : STD_LOGIC;
  signal \wait_cnt_r[2]_i_1__0_n_0\ : STD_LOGIC;
  signal \wait_cnt_r[3]_i_3__0_n_0\ : STD_LOGIC;
  signal wait_cnt_r_reg : STD_LOGIC_VECTOR ( 3 downto 0 );
  attribute srl_name : string;
  attribute srl_name of delay_done_r3_reg_srl3 : label is "\u_mig_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/mb_wrlvl_inst.u_ddr_phy_ck_addr_cmd_delay/delay_done_r3_reg_srl3 ";
  attribute syn_maxfan : string;
  attribute syn_maxfan of delay_done_r4_reg : label is "10";
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \delaydec_cnt_r[0]_i_1\ : label is "soft_lutpair297";
  attribute SOFT_HLUTNM of \delaydec_cnt_r[2]_i_1\ : label is "soft_lutpair297";
  attribute SOFT_HLUTNM of \delaydec_cnt_r[3]_i_1\ : label is "soft_lutpair295";
  attribute SOFT_HLUTNM of \delaydec_cnt_r[4]_i_1\ : label is "soft_lutpair295";
  attribute SOFT_HLUTNM of \po_cnt_dec_i_2__0\ : label is "soft_lutpair296";
  attribute SOFT_HLUTNM of \wait_cnt_r[1]_i_1\ : label is "soft_lutpair298";
  attribute SOFT_HLUTNM of \wait_cnt_r[2]_i_1__0\ : label is "soft_lutpair298";
  attribute SOFT_HLUTNM of \wait_cnt_r[3]_i_3__0\ : label is "soft_lutpair296";
begin
  ck_addr_cmd_delay_done <= \^ck_addr_cmd_delay_done\;
  ctl_lane_cnt(2 downto 0) <= \^ctl_lane_cnt\(2 downto 0);
  delaydec_cnt_r10_in <= \^delaydec_cnt_r10_in\;
  po_cnt_dec_2 <= \^po_cnt_dec_2\;
\ctl_lane_cnt[0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000006000000"
    )
        port map (
      I0 => \^ctl_lane_cnt\(0),
      I1 => \^delaydec_cnt_r10_in\,
      I2 => \ctl_lane_cnt_reg[1]_0\,
      I3 => pi_fine_dly_dec_done,
      I4 => dqs_po_dec_done,
      I5 => ctl_lane_cnt1,
      O => \ctl_lane_cnt[0]_i_1_n_0\
    );
\ctl_lane_cnt[1]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000DEEE0000"
    )
        port map (
      I0 => \^ctl_lane_cnt\(1),
      I1 => ctl_lane_cnt1,
      I2 => \^delaydec_cnt_r10_in\,
      I3 => \^ctl_lane_cnt\(0),
      I4 => cmd_delay_start0,
      I5 => \ctl_lane_cnt_reg[1]_0\,
      O => \ctl_lane_cnt[1]_i_1_n_0\
    );
\ctl_lane_cnt[2]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000006AAA"
    )
        port map (
      I0 => \^ctl_lane_cnt\(2),
      I1 => \^delaydec_cnt_r10_in\,
      I2 => \^ctl_lane_cnt\(1),
      I3 => \^ctl_lane_cnt\(0),
      I4 => p_1_in,
      I5 => ctl_lane_cnt1,
      O => \ctl_lane_cnt[2]_i_1_n_0\
    );
\ctl_lane_cnt[2]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"A8AA"
    )
        port map (
      I0 => delay_dec_done_i_2_n_0,
      I1 => \^ctl_lane_cnt\(2),
      I2 => \^ctl_lane_cnt\(0),
      I3 => \^ctl_lane_cnt\(1),
      O => \^delaydec_cnt_r10_in\
    );
\ctl_lane_cnt[2]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000040000"
    )
        port map (
      I0 => \ctl_lane_cnt[2]_i_5_n_0\,
      I1 => delaydec_cnt_r_reg(0),
      I2 => delay_dec_done,
      I3 => \^ctl_lane_cnt\(0),
      I4 => \^ctl_lane_cnt\(1),
      I5 => \^ctl_lane_cnt\(2),
      O => ctl_lane_cnt1
    );
\ctl_lane_cnt[2]_i_5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFFFFE"
    )
        port map (
      I0 => delaydec_cnt_r_reg(1),
      I1 => delaydec_cnt_r_reg(4),
      I2 => delaydec_cnt_r_reg(5),
      I3 => delaydec_cnt_r_reg(2),
      I4 => delaydec_cnt_r_reg(3),
      O => \ctl_lane_cnt[2]_i_5_n_0\
    );
\ctl_lane_cnt_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => delay_done_r4_reg_0,
      CE => '1',
      D => \ctl_lane_cnt[0]_i_1_n_0\,
      Q => \^ctl_lane_cnt\(0),
      R => '0'
    );
\ctl_lane_cnt_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => delay_done_r4_reg_0,
      CE => '1',
      D => \ctl_lane_cnt[1]_i_1_n_0\,
      Q => \^ctl_lane_cnt\(1),
      R => '0'
    );
\ctl_lane_cnt_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => delay_done_r4_reg_0,
      CE => '1',
      D => \ctl_lane_cnt[2]_i_1_n_0\,
      Q => \^ctl_lane_cnt\(2),
      R => '0'
    );
delay_dec_done_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000AAAAAEAA"
    )
        port map (
      I0 => delay_dec_done,
      I1 => delay_dec_done_i_2_n_0,
      I2 => \^ctl_lane_cnt\(2),
      I3 => \^ctl_lane_cnt\(1),
      I4 => \^ctl_lane_cnt\(0),
      I5 => p_1_in,
      O => delay_dec_done_i_1_n_0
    );
delay_dec_done_i_2: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000000001"
    )
        port map (
      I0 => delaydec_cnt_r_reg(3),
      I1 => delaydec_cnt_r_reg(2),
      I2 => delaydec_cnt_r_reg(5),
      I3 => delaydec_cnt_r_reg(4),
      I4 => delaydec_cnt_r_reg(1),
      I5 => delaydec_cnt_r_reg(0),
      O => delay_dec_done_i_2_n_0
    );
delay_dec_done_reg: unisim.vcomponents.FDRE
     port map (
      C => delay_done_r4_reg_0,
      CE => '1',
      D => delay_dec_done_i_1_n_0,
      Q => delay_dec_done,
      R => '0'
    );
delay_done_r3_reg_srl3: unisim.vcomponents.SRL16E
     port map (
      A0 => '0',
      A1 => '1',
      A2 => '0',
      A3 => '0',
      CE => '1',
      CLK => delay_done_r4_reg_0,
      D => delay_dec_done,
      Q => delay_done_r3_reg_srl3_n_0
    );
delay_done_r4_reg: unisim.vcomponents.FDRE
     port map (
      C => delay_done_r4_reg_0,
      CE => '1',
      D => delay_done_r3_reg_srl3_n_0,
      Q => \^ck_addr_cmd_delay_done\,
      R => '0'
    );
\delaydec_cnt_r[0]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => delaydec_cnt_r_reg(0),
      O => \delaydec_cnt_r[0]_i_1_n_0\
    );
\delaydec_cnt_r[1]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => delaydec_cnt_r_reg(0),
      I1 => delaydec_cnt_r_reg(1),
      O => \delaydec_cnt_r[1]_i_1_n_0\
    );
\delaydec_cnt_r[2]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"E1"
    )
        port map (
      I0 => delaydec_cnt_r_reg(1),
      I1 => delaydec_cnt_r_reg(0),
      I2 => delaydec_cnt_r_reg(2),
      O => \delaydec_cnt_r[2]_i_1_n_0\
    );
\delaydec_cnt_r[3]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FE01"
    )
        port map (
      I0 => delaydec_cnt_r_reg(2),
      I1 => delaydec_cnt_r_reg(0),
      I2 => delaydec_cnt_r_reg(1),
      I3 => delaydec_cnt_r_reg(3),
      O => \delaydec_cnt_r[3]_i_1_n_0\
    );
\delaydec_cnt_r[4]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFE0001"
    )
        port map (
      I0 => delaydec_cnt_r_reg(3),
      I1 => delaydec_cnt_r_reg(1),
      I2 => delaydec_cnt_r_reg(0),
      I3 => delaydec_cnt_r_reg(2),
      I4 => delaydec_cnt_r_reg(4),
      O => \delaydec_cnt_r[4]_i_1_n_0\
    );
\delaydec_cnt_r[5]_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^po_cnt_dec_2\,
      I1 => po_cnt_inc2,
      O => delaydec_cnt_r0
    );
\delaydec_cnt_r[5]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFE00000001"
    )
        port map (
      I0 => delaydec_cnt_r_reg(4),
      I1 => delaydec_cnt_r_reg(2),
      I2 => delaydec_cnt_r_reg(0),
      I3 => delaydec_cnt_r_reg(1),
      I4 => delaydec_cnt_r_reg(3),
      I5 => delaydec_cnt_r_reg(5),
      O => \delaydec_cnt_r[5]_i_3_n_0\
    );
\delaydec_cnt_r[5]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFFFE"
    )
        port map (
      I0 => delaydec_cnt_r_reg(2),
      I1 => delaydec_cnt_r_reg(1),
      I2 => delaydec_cnt_r_reg(5),
      I3 => delaydec_cnt_r_reg(0),
      I4 => delaydec_cnt_r_reg(3),
      I5 => delaydec_cnt_r_reg(4),
      O => po_cnt_inc2
    );
\delaydec_cnt_r_reg[0]\: unisim.vcomponents.FDSE
     port map (
      C => delay_done_r4_reg_0,
      CE => delaydec_cnt_r0,
      D => \delaydec_cnt_r[0]_i_1_n_0\,
      Q => delaydec_cnt_r_reg(0),
      S => SS(0)
    );
\delaydec_cnt_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => delay_done_r4_reg_0,
      CE => delaydec_cnt_r0,
      D => \delaydec_cnt_r[1]_i_1_n_0\,
      Q => delaydec_cnt_r_reg(1),
      R => SS(0)
    );
\delaydec_cnt_r_reg[2]\: unisim.vcomponents.FDSE
     port map (
      C => delay_done_r4_reg_0,
      CE => delaydec_cnt_r0,
      D => \delaydec_cnt_r[2]_i_1_n_0\,
      Q => delaydec_cnt_r_reg(2),
      S => SS(0)
    );
\delaydec_cnt_r_reg[3]\: unisim.vcomponents.FDSE
     port map (
      C => delay_done_r4_reg_0,
      CE => delaydec_cnt_r0,
      D => \delaydec_cnt_r[3]_i_1_n_0\,
      Q => delaydec_cnt_r_reg(3),
      S => SS(0)
    );
\delaydec_cnt_r_reg[4]\: unisim.vcomponents.FDSE
     port map (
      C => delay_done_r4_reg_0,
      CE => delaydec_cnt_r0,
      D => \delaydec_cnt_r[4]_i_1_n_0\,
      Q => delaydec_cnt_r_reg(4),
      S => SS(0)
    );
\delaydec_cnt_r_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => delay_done_r4_reg_0,
      CE => delaydec_cnt_r0,
      D => \delaydec_cnt_r[5]_i_3_n_0\,
      Q => delaydec_cnt_r_reg(5),
      R => SS(0)
    );
\gen_byte_sel_div2.byte_sel_cnt[3]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"A2AAAAAAAAAAAAAA"
    )
        port map (
      I0 => \^ck_addr_cmd_delay_done\,
      I1 => \gen_byte_sel_div2.byte_sel_cnt_reg[0]\,
      I2 => tempmon_sel_pi_incdec,
      I3 => \gen_byte_sel_div2.byte_sel_cnt_reg[0]_0\,
      I4 => \gen_byte_sel_div2.byte_sel_cnt_reg[0]_1\,
      I5 => \gen_byte_sel_div2.byte_sel_cnt_reg[0]_2\,
      O => E(0)
    );
\po_cnt_dec_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000008000"
    )
        port map (
      I0 => pi_fine_dly_dec_done,
      I1 => dqs_po_dec_done,
      I2 => po_cnt_inc2,
      I3 => po_cnt_inc1,
      I4 => delay_dec_done_i_2_n_0,
      I5 => \ctl_lane_cnt_reg[1]_0\,
      O => \po_cnt_dec_i_1__0_n_0\
    );
\po_cnt_dec_i_2__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0010"
    )
        port map (
      I0 => wait_cnt_r_reg(2),
      I1 => wait_cnt_r_reg(3),
      I2 => wait_cnt_r_reg(0),
      I3 => wait_cnt_r_reg(1),
      O => po_cnt_inc1
    );
po_cnt_dec_reg: unisim.vcomponents.FDRE
     port map (
      C => delay_done_r4_reg_0,
      CE => '1',
      D => \po_cnt_dec_i_1__0_n_0\,
      Q => \^po_cnt_dec_2\,
      R => '0'
    );
po_en_stg2_f_reg: unisim.vcomponents.FDRE
     port map (
      C => delay_done_r4_reg_0,
      CE => '1',
      D => \^po_cnt_dec_2\,
      Q => cmd_po_en_stg2_f,
      R => po_en_stg2_f_reg_0
    );
\wait_cnt_r[0]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => wait_cnt_r_reg(0),
      O => \wait_cnt_r0__0\(0)
    );
\wait_cnt_r[1]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => wait_cnt_r_reg(0),
      I1 => wait_cnt_r_reg(1),
      O => \wait_cnt_r[1]_i_1_n_0\
    );
\wait_cnt_r[2]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"E1"
    )
        port map (
      I0 => wait_cnt_r_reg(1),
      I1 => wait_cnt_r_reg(0),
      I2 => wait_cnt_r_reg(2),
      O => \wait_cnt_r[2]_i_1__0_n_0\
    );
\wait_cnt_r[3]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8888888888888880"
    )
        port map (
      I0 => pi_fine_dly_dec_done,
      I1 => dqs_po_dec_done,
      I2 => wait_cnt_r_reg(3),
      I3 => wait_cnt_r_reg(0),
      I4 => wait_cnt_r_reg(1),
      I5 => wait_cnt_r_reg(2),
      O => wait_cnt_r0
    );
\wait_cnt_r[3]_i_3__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FE01"
    )
        port map (
      I0 => wait_cnt_r_reg(2),
      I1 => wait_cnt_r_reg(0),
      I2 => wait_cnt_r_reg(1),
      I3 => wait_cnt_r_reg(3),
      O => \wait_cnt_r[3]_i_3__0_n_0\
    );
\wait_cnt_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => delay_done_r4_reg_0,
      CE => wait_cnt_r0,
      D => \wait_cnt_r0__0\(0),
      Q => wait_cnt_r_reg(0),
      R => \wait_cnt_r_reg[0]_0\(0)
    );
\wait_cnt_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => delay_done_r4_reg_0,
      CE => wait_cnt_r0,
      D => \wait_cnt_r[1]_i_1_n_0\,
      Q => wait_cnt_r_reg(1),
      R => \wait_cnt_r_reg[0]_0\(0)
    );
\wait_cnt_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => delay_done_r4_reg_0,
      CE => wait_cnt_r0,
      D => \wait_cnt_r[2]_i_1__0_n_0\,
      Q => wait_cnt_r_reg(2),
      R => \wait_cnt_r_reg[0]_0\(0)
    );
\wait_cnt_r_reg[3]\: unisim.vcomponents.FDSE
     port map (
      C => delay_done_r4_reg_0,
      CE => wait_cnt_r0,
      D => \wait_cnt_r[3]_i_3__0_n_0\,
      Q => wait_cnt_r_reg(3),
      S => \wait_cnt_r_reg[0]_0\(0)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mig_mig_7series_v4_2_ddr_phy_dqs_found_cal_hr is
  port (
    init_dqsfound_done_r2 : out STD_LOGIC;
    pi_dqs_found_rank_done : out STD_LOGIC;
    dqs_found_done_r_reg_0 : out STD_LOGIC;
    fine_adjust_reg_0 : out STD_LOGIC;
    dqs_found_prech_req : out STD_LOGIC;
    ck_po_stg2_f_indec : out STD_LOGIC;
    ck_po_stg2_f_en : out STD_LOGIC;
    \rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][0]_0\ : out STD_LOGIC;
    \rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][5]_0\ : out STD_LOGIC_VECTOR ( 5 downto 0 );
    \rank_final_loop[0].bank_final_loop[1].final_data_offset_mc_reg[0][6]_0\ : out STD_LOGIC;
    \rank_final_loop[0].bank_final_loop[1].final_data_offset_mc_reg[0][11]_0\ : out STD_LOGIC_VECTOR ( 5 downto 0 );
    \rank_final_loop[0].bank_final_loop[2].final_data_offset_mc_reg[0][12]_0\ : out STD_LOGIC;
    \rank_final_loop[0].bank_final_loop[2].final_data_offset_mc_reg[0][17]_0\ : out STD_LOGIC_VECTOR ( 5 downto 0 );
    Q : out STD_LOGIC_VECTOR ( 0 to 0 );
    \rd_byte_data_offset_reg[0][9]_0\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    \rd_byte_data_offset_reg[0][15]_0\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    \rank_final_loop[0].bank_final_loop[1].final_data_offset_reg[0][9]_0\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    \rank_final_loop[0].bank_final_loop[2].final_data_offset_reg[0][15]_0\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    \rank_final_loop[0].bank_final_loop[0].final_data_offset_reg[0][3]_0\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    pi_dqs_found_done_r1_reg : out STD_LOGIC;
    pi_dqs_found_done_r1_reg_0 : out STD_LOGIC;
    pi_dqs_found_done_r1_reg_1 : out STD_LOGIC;
    pi_dqs_found_done_r1_reg_2 : out STD_LOGIC;
    pi_dqs_found_done_r1_reg_3 : out STD_LOGIC;
    pi_dqs_found_done_r1_reg_4 : out STD_LOGIC;
    pi_dqs_found_done_r1_reg_5 : out STD_LOGIC;
    pi_dqs_found_done_r1_reg_6 : out STD_LOGIC;
    pi_dqs_found_done_r1_reg_7 : out STD_LOGIC;
    pi_dqs_found_done_r1_reg_8 : out STD_LOGIC;
    pi_dqs_found_done_r1_reg_9 : out STD_LOGIC;
    pi_dqs_found_done_r1_reg_10 : out STD_LOGIC;
    pi_dqs_found_done_r1_reg_11 : out STD_LOGIC;
    pi_dqs_found_done_r1_reg_12 : out STD_LOGIC;
    pi_dqs_found_done_r1_reg_13 : out STD_LOGIC;
    dqs_found_done_r_reg_1 : out STD_LOGIC;
    dqs_found_done_r_reg_2 : out STD_LOGIC;
    rank_done_r_reg_0 : out STD_LOGIC;
    delay_done_r4_reg : out STD_LOGIC;
    \ctl_lane_cnt_reg[2]_0\ : out STD_LOGIC;
    \pi_rst_stg1_cal_reg[0]_0\ : out STD_LOGIC;
    ctl_lane_sel : out STD_LOGIC;
    \ctl_lane_cnt_reg[1]_0\ : out STD_LOGIC;
    \ctl_lane_cnt_reg[0]_0\ : out STD_LOGIC;
    SR : out STD_LOGIC_VECTOR ( 0 to 0 );
    \gen_byte_sel_div2.ctl_lane_sel_reg[2]\ : out STD_LOGIC;
    \calib_sel1__1\ : out STD_LOGIC;
    \gen_byte_sel_div2.ctl_lane_sel_reg[2]_0\ : out STD_LOGIC;
    delay_done_r4_reg_0 : out STD_LOGIC;
    \pi_rst_stg1_cal_reg[2]_0\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
    init_dqsfound_done_r5_reg_0 : in STD_LOGIC;
    in0 : in STD_LOGIC_VECTOR ( 7 downto 0 );
    dqs_found_start_r_reg_0 : in STD_LOGIC;
    \pi_dqs_found_any_bank_reg[0]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    first_fail_detect_reg_0 : in STD_LOGIC;
    detect_pi_found_dqs : in STD_LOGIC;
    init_dqsfound_done_r_reg_0 : in STD_LOGIC;
    prech_done : in STD_LOGIC;
    \pi_rst_stg1_cal_r_reg[1]_0\ : in STD_LOGIC;
    pi_dqs_found_done_r1 : in STD_LOGIC;
    \gen_no_mirror.div_clk_loop[0].phy_address_reg[10]\ : in STD_LOGIC;
    \gen_no_mirror.div_clk_loop[0].phy_address_reg[10]_0\ : in STD_LOGIC;
    \init_state_r[2]_i_10\ : in STD_LOGIC;
    \init_state_r[0]_i_10\ : in STD_LOGIC;
    ck_addr_cmd_delay_done : in STD_LOGIC;
    pi_fine_dly_dec_done : in STD_LOGIC;
    dqs_po_dec_done : in STD_LOGIC;
    calib_in_common : in STD_LOGIC;
    ctl_lane_cnt : in STD_LOGIC_VECTOR ( 2 downto 0 );
    \gen_byte_sel_div2.ctl_lane_sel_reg[2]_1\ : in STD_LOGIC;
    \gen_byte_sel_div2.ctl_lane_sel_reg[1]\ : in STD_LOGIC;
    \gen_byte_sel_div2.ctl_lane_sel_reg[0]\ : in STD_LOGIC;
    \gen_byte_sel_div2.calib_in_common_reg\ : in STD_LOGIC;
    pi_calib_done : in STD_LOGIC;
    calib_in_common4_out : in STD_LOGIC;
    \gen_byte_sel_div2.byte_sel_cnt_reg[0]\ : in STD_LOGIC;
    cmd_delay_start0 : in STD_LOGIC;
    \calib_sel_reg[0]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
    \calib_sel_reg[1]\ : in STD_LOGIC;
    \stable_pass_cnt_reg[0]_0\ : in STD_LOGIC;
    \init_dec_cnt_reg[4]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of mig_mig_7series_v4_2_ddr_phy_dqs_found_cal_hr : entity is "mig_7series_v4_2_ddr_phy_dqs_found_cal_hr";
end mig_mig_7series_v4_2_ddr_phy_dqs_found_cal_hr;

architecture STRUCTURE of mig_mig_7series_v4_2_ddr_phy_dqs_found_cal_hr is
  signal \FSM_sequential_fine_adj_state_r[0]_i_1_n_0\ : STD_LOGIC;
  signal \FSM_sequential_fine_adj_state_r[0]_i_2_n_0\ : STD_LOGIC;
  signal \FSM_sequential_fine_adj_state_r[0]_i_3_n_0\ : STD_LOGIC;
  signal \FSM_sequential_fine_adj_state_r[0]_i_4_n_0\ : STD_LOGIC;
  signal \FSM_sequential_fine_adj_state_r[0]_i_5_n_0\ : STD_LOGIC;
  signal \FSM_sequential_fine_adj_state_r[0]_i_6_n_0\ : STD_LOGIC;
  signal \FSM_sequential_fine_adj_state_r[1]_i_10_n_0\ : STD_LOGIC;
  signal \FSM_sequential_fine_adj_state_r[1]_i_11_n_0\ : STD_LOGIC;
  signal \FSM_sequential_fine_adj_state_r[1]_i_12_n_0\ : STD_LOGIC;
  signal \FSM_sequential_fine_adj_state_r[1]_i_13_n_0\ : STD_LOGIC;
  signal \FSM_sequential_fine_adj_state_r[1]_i_14_n_0\ : STD_LOGIC;
  signal \FSM_sequential_fine_adj_state_r[1]_i_1_n_0\ : STD_LOGIC;
  signal \FSM_sequential_fine_adj_state_r[1]_i_2_n_0\ : STD_LOGIC;
  signal \FSM_sequential_fine_adj_state_r[1]_i_3_n_0\ : STD_LOGIC;
  signal \FSM_sequential_fine_adj_state_r[1]_i_4_n_0\ : STD_LOGIC;
  signal \FSM_sequential_fine_adj_state_r[1]_i_5_n_0\ : STD_LOGIC;
  signal \FSM_sequential_fine_adj_state_r[1]_i_6_n_0\ : STD_LOGIC;
  signal \FSM_sequential_fine_adj_state_r[1]_i_7_n_0\ : STD_LOGIC;
  signal \FSM_sequential_fine_adj_state_r[1]_i_8_n_0\ : STD_LOGIC;
  signal \FSM_sequential_fine_adj_state_r[1]_i_9_n_0\ : STD_LOGIC;
  signal \FSM_sequential_fine_adj_state_r[2]_i_1_n_0\ : STD_LOGIC;
  signal \FSM_sequential_fine_adj_state_r[2]_i_2_n_0\ : STD_LOGIC;
  signal \FSM_sequential_fine_adj_state_r[2]_i_3_n_0\ : STD_LOGIC;
  signal \FSM_sequential_fine_adj_state_r[2]_i_4_n_0\ : STD_LOGIC;
  signal \FSM_sequential_fine_adj_state_r[2]_i_5_n_0\ : STD_LOGIC;
  signal \FSM_sequential_fine_adj_state_r[3]_i_1_n_0\ : STD_LOGIC;
  signal \FSM_sequential_fine_adj_state_r[3]_i_2_n_0\ : STD_LOGIC;
  signal \FSM_sequential_fine_adj_state_r[3]_i_3_n_0\ : STD_LOGIC;
  signal \FSM_sequential_fine_adj_state_r[3]_i_4_n_0\ : STD_LOGIC;
  signal \FSM_sequential_fine_adj_state_r[3]_i_5_n_0\ : STD_LOGIC;
  signal \FSM_sequential_fine_adj_state_r[3]_i_6_n_0\ : STD_LOGIC;
  signal \FSM_sequential_fine_adj_state_r[3]_i_7_n_0\ : STD_LOGIC;
  signal \FSM_sequential_fine_adj_state_r[3]_i_8_n_0\ : STD_LOGIC;
  signal \FSM_sequential_fine_adj_state_r[3]_i_9_n_0\ : STD_LOGIC;
  signal \^q\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal byte_sel_cnt1 : STD_LOGIC;
  signal \^calib_sel1__1\ : STD_LOGIC;
  signal \^ck_po_stg2_f_en\ : STD_LOGIC;
  signal ck_po_stg2_f_en_i_1_n_0 : STD_LOGIC;
  signal \^ck_po_stg2_f_indec\ : STD_LOGIC;
  signal ck_po_stg2_f_indec_i_1_n_0 : STD_LOGIC;
  signal \ctl_lane_cnt[0]_i_1__0_n_0\ : STD_LOGIC;
  signal \ctl_lane_cnt[1]_i_1__0_n_0\ : STD_LOGIC;
  signal \ctl_lane_cnt[2]_i_1__0_n_0\ : STD_LOGIC;
  signal ctl_lane_cnt_0 : STD_LOGIC;
  signal \^ctl_lane_sel\ : STD_LOGIC;
  signal dec_cnt : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal \dec_cnt[0]_i_2_n_0\ : STD_LOGIC;
  signal \dec_cnt[1]_i_2_n_0\ : STD_LOGIC;
  signal \dec_cnt[1]_i_3_n_0\ : STD_LOGIC;
  signal \dec_cnt[2]_i_3_n_0\ : STD_LOGIC;
  signal \dec_cnt[2]_i_4_n_0\ : STD_LOGIC;
  signal \dec_cnt[2]_i_5_n_0\ : STD_LOGIC;
  signal \dec_cnt[2]_i_6_n_0\ : STD_LOGIC;
  signal \dec_cnt[2]_i_7_n_0\ : STD_LOGIC;
  signal \dec_cnt[2]_i_8_n_0\ : STD_LOGIC;
  signal \dec_cnt[2]_i_9_n_0\ : STD_LOGIC;
  signal \dec_cnt[3]_i_2_n_0\ : STD_LOGIC;
  signal \dec_cnt[3]_i_3_n_0\ : STD_LOGIC;
  signal \dec_cnt[3]_i_4_n_0\ : STD_LOGIC;
  signal \dec_cnt[4]_i_2_n_0\ : STD_LOGIC;
  signal \dec_cnt[4]_i_3_n_0\ : STD_LOGIC;
  signal \dec_cnt[4]_i_5_n_0\ : STD_LOGIC;
  signal \dec_cnt[4]_i_6_n_0\ : STD_LOGIC;
  signal \dec_cnt[4]_i_7_n_0\ : STD_LOGIC;
  signal \dec_cnt[4]_i_8_n_0\ : STD_LOGIC;
  signal \dec_cnt[4]_i_9_n_0\ : STD_LOGIC;
  signal \dec_cnt[5]_i_10_n_0\ : STD_LOGIC;
  signal \dec_cnt[5]_i_11_n_0\ : STD_LOGIC;
  signal \dec_cnt[5]_i_12_n_0\ : STD_LOGIC;
  signal \dec_cnt[5]_i_1_n_0\ : STD_LOGIC;
  signal \dec_cnt[5]_i_3_n_0\ : STD_LOGIC;
  signal \dec_cnt[5]_i_4_n_0\ : STD_LOGIC;
  signal \dec_cnt[5]_i_5_n_0\ : STD_LOGIC;
  signal \dec_cnt[5]_i_6_n_0\ : STD_LOGIC;
  signal \dec_cnt[5]_i_7_n_0\ : STD_LOGIC;
  signal \dec_cnt[5]_i_8_n_0\ : STD_LOGIC;
  signal \dec_cnt[5]_i_9_n_0\ : STD_LOGIC;
  signal \dec_cnt_reg[2]_i_2_n_0\ : STD_LOGIC;
  signal \dec_cnt_reg[2]_i_2_n_1\ : STD_LOGIC;
  signal \dec_cnt_reg[2]_i_2_n_2\ : STD_LOGIC;
  signal \dec_cnt_reg[2]_i_2_n_3\ : STD_LOGIC;
  signal \dec_cnt_reg[2]_i_2_n_4\ : STD_LOGIC;
  signal \dec_cnt_reg[2]_i_2_n_5\ : STD_LOGIC;
  signal \dec_cnt_reg[2]_i_2_n_6\ : STD_LOGIC;
  signal \dec_cnt_reg[4]_i_4_n_3\ : STD_LOGIC;
  signal \dec_cnt_reg[4]_i_4_n_6\ : STD_LOGIC;
  signal \dec_cnt_reg[4]_i_4_n_7\ : STD_LOGIC;
  signal \dec_cnt_reg_n_0_[0]\ : STD_LOGIC;
  signal \dec_cnt_reg_n_0_[1]\ : STD_LOGIC;
  signal \dec_cnt_reg_n_0_[2]\ : STD_LOGIC;
  signal \dec_cnt_reg_n_0_[3]\ : STD_LOGIC;
  signal \dec_cnt_reg_n_0_[4]\ : STD_LOGIC;
  signal \dec_cnt_reg_n_0_[5]\ : STD_LOGIC;
  signal detect_rd_cnt0 : STD_LOGIC;
  signal \detect_rd_cnt0__0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \detect_rd_cnt[1]_i_1_n_0\ : STD_LOGIC;
  signal \detect_rd_cnt[3]_i_1_n_0\ : STD_LOGIC;
  signal detect_rd_cnt_reg : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal dqs_found_done_r0 : STD_LOGIC;
  signal dqs_found_done_r_i_4_n_0 : STD_LOGIC;
  signal \^dqs_found_done_r_reg_0\ : STD_LOGIC;
  signal \^dqs_found_prech_req\ : STD_LOGIC;
  signal dqs_found_prech_req_i_1_n_0 : STD_LOGIC;
  signal dqs_found_prech_req_i_2_n_0 : STD_LOGIC;
  signal dqs_found_prech_req_i_3_n_0 : STD_LOGIC;
  signal dqs_found_prech_req_i_4_n_0 : STD_LOGIC;
  signal dqs_found_start_r : STD_LOGIC;
  signal final_data_offset : STD_LOGIC;
  signal final_data_offset_mc : STD_LOGIC;
  signal final_dec_done_i_1_n_0 : STD_LOGIC;
  signal final_dec_done_reg_n_0 : STD_LOGIC;
  signal fine_adj_state_r : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal fine_adjust_done_r_i_1_n_0 : STD_LOGIC;
  signal fine_adjust_done_r_reg_n_0 : STD_LOGIC;
  signal fine_adjust_i_1_n_0 : STD_LOGIC;
  signal fine_adjust_lane_cnt : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal \^fine_adjust_reg_0\ : STD_LOGIC;
  signal first_fail_detect : STD_LOGIC;
  signal first_fail_detect_i_1_n_0 : STD_LOGIC;
  signal first_fail_detect_reg_n_0 : STD_LOGIC;
  signal \first_fail_taps[0]_i_1_n_0\ : STD_LOGIC;
  signal \first_fail_taps[1]_i_1_n_0\ : STD_LOGIC;
  signal \first_fail_taps[2]_i_1_n_0\ : STD_LOGIC;
  signal \first_fail_taps[3]_i_1_n_0\ : STD_LOGIC;
  signal \first_fail_taps[4]_i_1_n_0\ : STD_LOGIC;
  signal \first_fail_taps[5]_i_2_n_0\ : STD_LOGIC;
  signal \first_fail_taps[5]_i_3_n_0\ : STD_LOGIC;
  signal \first_fail_taps[5]_i_4_n_0\ : STD_LOGIC;
  signal \first_fail_taps[5]_i_5_n_0\ : STD_LOGIC;
  signal \first_fail_taps_reg_n_0_[0]\ : STD_LOGIC;
  signal \first_fail_taps_reg_n_0_[1]\ : STD_LOGIC;
  signal \first_fail_taps_reg_n_0_[2]\ : STD_LOGIC;
  signal \first_fail_taps_reg_n_0_[3]\ : STD_LOGIC;
  signal \first_fail_taps_reg_n_0_[4]\ : STD_LOGIC;
  signal \first_fail_taps_reg_n_0_[5]\ : STD_LOGIC;
  signal \gen_byte_sel_div2.calib_in_common_i_2_n_0\ : STD_LOGIC;
  signal \gen_byte_sel_div2.calib_in_common_i_3_n_0\ : STD_LOGIC;
  signal inc_cnt : STD_LOGIC;
  signal \inc_cnt[5]_i_3_n_0\ : STD_LOGIC;
  signal \inc_cnt_reg_n_0_[0]\ : STD_LOGIC;
  signal \inc_cnt_reg_n_0_[1]\ : STD_LOGIC;
  signal \inc_cnt_reg_n_0_[2]\ : STD_LOGIC;
  signal \inc_cnt_reg_n_0_[3]\ : STD_LOGIC;
  signal \inc_cnt_reg_n_0_[4]\ : STD_LOGIC;
  signal \inc_cnt_reg_n_0_[5]\ : STD_LOGIC;
  signal init_dec_cnt : STD_LOGIC;
  signal init_dec_cnt0 : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal \init_dec_cnt[1]_i_1_n_0\ : STD_LOGIC;
  signal \init_dec_cnt[5]_i_3_n_0\ : STD_LOGIC;
  signal init_dec_cnt_reg : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal init_dec_done_i_1_n_0 : STD_LOGIC;
  signal init_dec_done_reg_n_0 : STD_LOGIC;
  signal init_dqsfound_done_r1_reg_n_0 : STD_LOGIC;
  signal \^init_dqsfound_done_r2\ : STD_LOGIC;
  signal init_dqsfound_done_r4_reg_srl2_n_0 : STD_LOGIC;
  signal init_dqsfound_done_r5 : STD_LOGIC;
  signal init_dqsfound_done_r_i_1_n_0 : STD_LOGIC;
  signal init_dqsfound_done_r_i_2_n_0 : STD_LOGIC;
  signal n_0_0 : STD_LOGIC;
  signal n_0_1 : STD_LOGIC;
  signal n_0_2 : STD_LOGIC;
  signal n_0_3 : STD_LOGIC;
  signal p_0_in : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal p_0_in17_in : STD_LOGIC;
  signal p_0_in22_in : STD_LOGIC;
  signal p_0_in62_in : STD_LOGIC;
  signal \p_0_in__0\ : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal p_1_in : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal p_1_in30_in : STD_LOGIC;
  signal \p_1_in__0\ : STD_LOGIC_VECTOR ( 5 downto 2 );
  signal \p_1_in__1\ : STD_LOGIC_VECTOR ( 5 downto 2 );
  signal p_22_out : STD_LOGIC;
  signal p_8_out : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal pi_dqs_found_all_bank : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal pi_dqs_found_all_bank_r : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal pi_dqs_found_any_bank : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal \pi_dqs_found_any_bank[0]_i_1_n_0\ : STD_LOGIC;
  signal \pi_dqs_found_any_bank[2]_i_1_n_0\ : STD_LOGIC;
  signal \pi_dqs_found_any_bank_r_reg_n_0_[0]\ : STD_LOGIC;
  signal pi_dqs_found_lanes_r1 : STD_LOGIC_VECTOR ( 11 downto 0 );
  attribute async_reg : string;
  attribute async_reg of pi_dqs_found_lanes_r1 : signal is "true";
  signal pi_dqs_found_lanes_r2 : STD_LOGIC_VECTOR ( 11 downto 0 );
  attribute async_reg of pi_dqs_found_lanes_r2 : signal is "true";
  signal pi_dqs_found_lanes_r3 : STD_LOGIC_VECTOR ( 11 downto 0 );
  attribute async_reg of pi_dqs_found_lanes_r3 : signal is "true";
  signal \^pi_dqs_found_rank_done\ : STD_LOGIC;
  signal \pi_rst_stg1_cal[0]_i_1_n_0\ : STD_LOGIC;
  signal \pi_rst_stg1_cal[1]_i_1_n_0\ : STD_LOGIC;
  signal \pi_rst_stg1_cal[2]_i_1_n_0\ : STD_LOGIC;
  signal \pi_rst_stg1_cal_r1[0]_i_1_n_0\ : STD_LOGIC;
  signal \pi_rst_stg1_cal_r1[1]_i_1_n_0\ : STD_LOGIC;
  signal \pi_rst_stg1_cal_r1[2]_i_1_n_0\ : STD_LOGIC;
  signal \pi_rst_stg1_cal_r1_reg_n_0_[0]\ : STD_LOGIC;
  signal \pi_rst_stg1_cal_r[0]_i_1_n_0\ : STD_LOGIC;
  signal \pi_rst_stg1_cal_r[0]_i_2_n_0\ : STD_LOGIC;
  signal \pi_rst_stg1_cal_r[1]_i_1_n_0\ : STD_LOGIC;
  signal \pi_rst_stg1_cal_r[2]_i_1_n_0\ : STD_LOGIC;
  signal \pi_rst_stg1_cal_r[2]_i_2_n_0\ : STD_LOGIC;
  signal \pi_rst_stg1_cal_r_reg_n_0_[0]\ : STD_LOGIC;
  signal \pi_rst_stg1_cal_r_reg_n_0_[1]\ : STD_LOGIC;
  signal \pi_rst_stg1_cal_r_reg_n_0_[2]\ : STD_LOGIC;
  signal \^pi_rst_stg1_cal_reg[0]_0\ : STD_LOGIC;
  signal \^pi_rst_stg1_cal_reg[2]_0\ : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal rank_done_r1 : STD_LOGIC;
  signal rank_done_r_i_1_n_0 : STD_LOGIC;
  signal rank_done_r_i_2_n_0 : STD_LOGIC;
  signal \rank_final_loop[0].bank_final_loop[0].final_data_offset_mc[0][0]_i_1_n_0\ : STD_LOGIC;
  signal \rank_final_loop[0].bank_final_loop[0].final_data_offset_mc[0][1]_i_1_n_0\ : STD_LOGIC;
  signal \rank_final_loop[0].bank_final_loop[0].final_data_offset_mc[0][2]_i_1_n_0\ : STD_LOGIC;
  signal \rank_final_loop[0].bank_final_loop[0].final_data_offset_mc[0][3]_i_1_n_0\ : STD_LOGIC;
  signal \rank_final_loop[0].bank_final_loop[0].final_data_offset_mc[0][4]_i_1_n_0\ : STD_LOGIC;
  signal \rank_final_loop[0].bank_final_loop[0].final_data_offset_mc[0][5]_i_2_n_0\ : STD_LOGIC;
  signal \^rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][5]_0\ : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal \^rank_final_loop[0].bank_final_loop[0].final_data_offset_reg[0][3]_0\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \rank_final_loop[0].bank_final_loop[1].final_data_offset_mc[0][11]_i_1_n_0\ : STD_LOGIC;
  signal \^rank_final_loop[0].bank_final_loop[1].final_data_offset_mc_reg[0][11]_0\ : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal \^rank_final_loop[0].bank_final_loop[1].final_data_offset_reg[0][9]_0\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \rank_final_loop[0].bank_final_loop[2].final_data_offset_mc[0][12]_i_1_n_0\ : STD_LOGIC;
  signal \rank_final_loop[0].bank_final_loop[2].final_data_offset_mc[0][13]_i_1_n_0\ : STD_LOGIC;
  signal \rank_final_loop[0].bank_final_loop[2].final_data_offset_mc[0][14]_i_1_n_0\ : STD_LOGIC;
  signal \rank_final_loop[0].bank_final_loop[2].final_data_offset_mc[0][15]_i_1_n_0\ : STD_LOGIC;
  signal \rank_final_loop[0].bank_final_loop[2].final_data_offset_mc[0][16]_i_1_n_0\ : STD_LOGIC;
  signal \rank_final_loop[0].bank_final_loop[2].final_data_offset_mc[0][17]_i_1_n_0\ : STD_LOGIC;
  signal \^rank_final_loop[0].bank_final_loop[2].final_data_offset_mc_reg[0][17]_0\ : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal \^rank_final_loop[0].bank_final_loop[2].final_data_offset_reg[0][15]_0\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \rank_final_loop[0].final_do_index[0][0]_i_1_n_0\ : STD_LOGIC;
  signal \rank_final_loop[0].final_do_index[0][1]_i_1_n_0\ : STD_LOGIC;
  signal \rank_final_loop[0].final_do_index[0][2]_i_1_n_0\ : STD_LOGIC;
  signal \rank_final_loop[0].final_do_index_reg_n_0_[0][0]\ : STD_LOGIC;
  signal \rank_final_loop[0].final_do_index_reg_n_0_[0][1]\ : STD_LOGIC;
  signal \rank_final_loop[0].final_do_index_reg_n_0_[0][2]\ : STD_LOGIC;
  signal \rank_final_loop[0].final_do_max[0][0]_i_1_n_0\ : STD_LOGIC;
  signal \rank_final_loop[0].final_do_max[0][1]_i_1_n_0\ : STD_LOGIC;
  signal \rank_final_loop[0].final_do_max[0][2]_i_1_n_0\ : STD_LOGIC;
  signal \rank_final_loop[0].final_do_max[0][3]_i_1_n_0\ : STD_LOGIC;
  signal \rank_final_loop[0].final_do_max[0][4]_i_1_n_0\ : STD_LOGIC;
  signal \rank_final_loop[0].final_do_max[0][5]_i_10_n_0\ : STD_LOGIC;
  signal \rank_final_loop[0].final_do_max[0][5]_i_11_n_0\ : STD_LOGIC;
  signal \rank_final_loop[0].final_do_max[0][5]_i_1_n_0\ : STD_LOGIC;
  signal \rank_final_loop[0].final_do_max[0][5]_i_2_n_0\ : STD_LOGIC;
  signal \rank_final_loop[0].final_do_max[0][5]_i_3_n_0\ : STD_LOGIC;
  signal \rank_final_loop[0].final_do_max[0][5]_i_4_n_0\ : STD_LOGIC;
  signal \rank_final_loop[0].final_do_max[0][5]_i_5_n_0\ : STD_LOGIC;
  signal \rank_final_loop[0].final_do_max[0][5]_i_6_n_0\ : STD_LOGIC;
  signal \rank_final_loop[0].final_do_max[0][5]_i_7_n_0\ : STD_LOGIC;
  signal \rank_final_loop[0].final_do_max[0][5]_i_8_n_0\ : STD_LOGIC;
  signal \rank_final_loop[0].final_do_max[0][5]_i_9_n_0\ : STD_LOGIC;
  signal \rank_final_loop[0].final_do_max_reg[0]_45\ : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal rd_byte_data_offset : STD_LOGIC;
  signal \rd_byte_data_offset[0][11]_i_1_n_0\ : STD_LOGIC;
  signal \rd_byte_data_offset[0][11]_i_2_n_0\ : STD_LOGIC;
  signal \rd_byte_data_offset[0][11]_i_4_n_0\ : STD_LOGIC;
  signal \rd_byte_data_offset[0][11]_i_5_n_0\ : STD_LOGIC;
  signal \rd_byte_data_offset[0][13]_i_1_n_0\ : STD_LOGIC;
  signal \rd_byte_data_offset[0][17]_i_1_n_0\ : STD_LOGIC;
  signal \rd_byte_data_offset[0][17]_i_2_n_0\ : STD_LOGIC;
  signal \rd_byte_data_offset[0][17]_i_4_n_0\ : STD_LOGIC;
  signal \rd_byte_data_offset[0][1]_i_1_n_0\ : STD_LOGIC;
  signal \rd_byte_data_offset[0][5]_i_1_n_0\ : STD_LOGIC;
  signal \rd_byte_data_offset[0][5]_i_4_n_0\ : STD_LOGIC;
  signal \^rd_byte_data_offset_reg[0][15]_0\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \^rd_byte_data_offset_reg[0][9]_0\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \rd_byte_data_offset_reg[0]_46\ : STD_LOGIC;
  signal \rd_byte_data_offset_reg_n_0_[0][0]\ : STD_LOGIC;
  signal \rd_byte_data_offset_reg_n_0_[0][10]\ : STD_LOGIC;
  signal \rd_byte_data_offset_reg_n_0_[0][11]\ : STD_LOGIC;
  signal \rd_byte_data_offset_reg_n_0_[0][12]\ : STD_LOGIC;
  signal \rd_byte_data_offset_reg_n_0_[0][13]\ : STD_LOGIC;
  signal \rd_byte_data_offset_reg_n_0_[0][14]\ : STD_LOGIC;
  signal \rd_byte_data_offset_reg_n_0_[0][16]\ : STD_LOGIC;
  signal \rd_byte_data_offset_reg_n_0_[0][17]\ : STD_LOGIC;
  signal \rd_byte_data_offset_reg_n_0_[0][1]\ : STD_LOGIC;
  signal \rd_byte_data_offset_reg_n_0_[0][2]\ : STD_LOGIC;
  signal \rd_byte_data_offset_reg_n_0_[0][4]\ : STD_LOGIC;
  signal \rd_byte_data_offset_reg_n_0_[0][5]\ : STD_LOGIC;
  signal \rd_byte_data_offset_reg_n_0_[0][6]\ : STD_LOGIC;
  signal \rd_byte_data_offset_reg_n_0_[0][7]\ : STD_LOGIC;
  signal \rd_byte_data_offset_reg_n_0_[0][8]\ : STD_LOGIC;
  signal rd_data_offset_cal_done : STD_LOGIC;
  signal rd_data_offset_ranks_0 : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal rd_data_offset_ranks_1 : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal rd_data_offset_ranks_2 : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal \rnk_cnt_r[0]_i_1_n_0\ : STD_LOGIC;
  signal \rnk_cnt_r[1]_i_1_n_0\ : STD_LOGIC;
  signal \rnk_cnt_r_reg_n_0_[0]\ : STD_LOGIC;
  signal \rnk_cnt_r_reg_n_0_[1]\ : STD_LOGIC;
  signal rst_dqs_find : STD_LOGIC;
  signal rst_dqs_find_i_1_n_0 : STD_LOGIC;
  signal rst_dqs_find_i_2_n_0 : STD_LOGIC;
  signal rst_dqs_find_i_3_n_0 : STD_LOGIC;
  signal rst_dqs_find_i_4_n_0 : STD_LOGIC;
  signal rst_dqs_find_i_5_n_0 : STD_LOGIC;
  signal rst_dqs_find_i_6_n_0 : STD_LOGIC;
  signal rst_dqs_find_i_7_n_0 : STD_LOGIC;
  signal rst_dqs_find_r1 : STD_LOGIC;
  signal rst_dqs_find_r2 : STD_LOGIC;
  signal stable_pass_cnt : STD_LOGIC;
  signal \stable_pass_cnt[5]_i_3_n_0\ : STD_LOGIC;
  signal stable_pass_cnt_reg : STD_LOGIC_VECTOR ( 5 downto 1 );
  signal \stable_pass_cnt_reg_n_0_[0]\ : STD_LOGIC;
  signal \NLW_dec_cnt_reg[2]_i_2_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \NLW_dec_cnt_reg[4]_i_4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
  signal \NLW_dec_cnt_reg[4]_i_4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \FSM_sequential_fine_adj_state_r[0]_i_4\ : label is "soft_lutpair294";
  attribute SOFT_HLUTNM of \FSM_sequential_fine_adj_state_r[0]_i_6\ : label is "soft_lutpair246";
  attribute SOFT_HLUTNM of \FSM_sequential_fine_adj_state_r[1]_i_13\ : label is "soft_lutpair288";
  attribute SOFT_HLUTNM of \FSM_sequential_fine_adj_state_r[1]_i_3\ : label is "soft_lutpair252";
  attribute SOFT_HLUTNM of \FSM_sequential_fine_adj_state_r[1]_i_4\ : label is "soft_lutpair267";
  attribute SOFT_HLUTNM of \FSM_sequential_fine_adj_state_r[1]_i_5\ : label is "soft_lutpair248";
  attribute SOFT_HLUTNM of \FSM_sequential_fine_adj_state_r[1]_i_7\ : label is "soft_lutpair247";
  attribute SOFT_HLUTNM of \FSM_sequential_fine_adj_state_r[1]_i_9\ : label is "soft_lutpair250";
  attribute SOFT_HLUTNM of \FSM_sequential_fine_adj_state_r[2]_i_5\ : label is "soft_lutpair280";
  attribute SOFT_HLUTNM of \FSM_sequential_fine_adj_state_r[3]_i_7\ : label is "soft_lutpair249";
  attribute SOFT_HLUTNM of \FSM_sequential_fine_adj_state_r[3]_i_8\ : label is "soft_lutpair247";
  attribute FSM_ENCODED_STATES : string;
  attribute FSM_ENCODED_STATES of \FSM_sequential_fine_adj_state_r_reg[0]\ : label is "FINE_ADJ_INIT:0101,RST_WAIT:0001,RST_POSTWAIT1:0100,FINE_DEC_PREWAIT:1101,FINE_DEC_WAIT:1100,FINE_DEC:1011,PRECH_WAIT:1111,RST_POSTWAIT:0011,FINE_ADJ_IDLE:0000,FINE_INC_PREWAIT:1000,DETECT_DQSFOUND:1010,FINE_INC_WAIT:0111,DETECT_PREWAIT:1001,FINE_ADJ_DONE:0010,FINAL_WAIT:1110,FINE_INC:0110";
  attribute FSM_ENCODED_STATES of \FSM_sequential_fine_adj_state_r_reg[1]\ : label is "FINE_ADJ_INIT:0101,RST_WAIT:0001,RST_POSTWAIT1:0100,FINE_DEC_PREWAIT:1101,FINE_DEC_WAIT:1100,FINE_DEC:1011,PRECH_WAIT:1111,RST_POSTWAIT:0011,FINE_ADJ_IDLE:0000,FINE_INC_PREWAIT:1000,DETECT_DQSFOUND:1010,FINE_INC_WAIT:0111,DETECT_PREWAIT:1001,FINE_ADJ_DONE:0010,FINAL_WAIT:1110,FINE_INC:0110";
  attribute FSM_ENCODED_STATES of \FSM_sequential_fine_adj_state_r_reg[2]\ : label is "FINE_ADJ_INIT:0101,RST_WAIT:0001,RST_POSTWAIT1:0100,FINE_DEC_PREWAIT:1101,FINE_DEC_WAIT:1100,FINE_DEC:1011,PRECH_WAIT:1111,RST_POSTWAIT:0011,FINE_ADJ_IDLE:0000,FINE_INC_PREWAIT:1000,DETECT_DQSFOUND:1010,FINE_INC_WAIT:0111,DETECT_PREWAIT:1001,FINE_ADJ_DONE:0010,FINAL_WAIT:1110,FINE_INC:0110";
  attribute FSM_ENCODED_STATES of \FSM_sequential_fine_adj_state_r_reg[3]\ : label is "FINE_ADJ_INIT:0101,RST_WAIT:0001,RST_POSTWAIT1:0100,FINE_DEC_PREWAIT:1101,FINE_DEC_WAIT:1100,FINE_DEC:1011,PRECH_WAIT:1111,RST_POSTWAIT:0011,FINE_ADJ_IDLE:0000,FINE_INC_PREWAIT:1000,DETECT_DQSFOUND:1010,FINE_INC_WAIT:0111,DETECT_PREWAIT:1001,FINE_ADJ_DONE:0010,FINAL_WAIT:1110,FINE_INC:0110";
  attribute SOFT_HLUTNM of \calib_data_offset_0[0]_i_1\ : label is "soft_lutpair273";
  attribute SOFT_HLUTNM of \calib_data_offset_0[1]_i_1\ : label is "soft_lutpair278";
  attribute SOFT_HLUTNM of \calib_data_offset_1[0]_i_1\ : label is "soft_lutpair272";
  attribute SOFT_HLUTNM of \calib_data_offset_2[0]_i_1\ : label is "soft_lutpair274";
  attribute SOFT_HLUTNM of \calib_data_offset_2[1]_i_1\ : label is "soft_lutpair275";
  attribute SOFT_HLUTNM of \calib_sel[1]_i_2\ : label is "soft_lutpair268";
  attribute SOFT_HLUTNM of \calib_sel[3]_i_1\ : label is "soft_lutpair268";
  attribute SOFT_HLUTNM of ck_po_stg2_f_en_i_1 : label is "soft_lutpair267";
  attribute SOFT_HLUTNM of ck_po_stg2_f_indec_i_1 : label is "soft_lutpair261";
  attribute SOFT_HLUTNM of \ctl_lane_cnt[1]_i_1__0\ : label is "soft_lutpair279";
  attribute SOFT_HLUTNM of \ctl_lane_cnt[2]_i_1__0\ : label is "soft_lutpair279";
  attribute SOFT_HLUTNM of \ctl_lane_cnt[2]_i_2__0\ : label is "soft_lutpair261";
  attribute SOFT_HLUTNM of \dec_cnt[3]_i_2\ : label is "soft_lutpair269";
  attribute SOFT_HLUTNM of \dec_cnt[3]_i_4\ : label is "soft_lutpair271";
  attribute SOFT_HLUTNM of \dec_cnt[4]_i_2\ : label is "soft_lutpair269";
  attribute SOFT_HLUTNM of \dec_cnt[4]_i_3\ : label is "soft_lutpair262";
  attribute SOFT_HLUTNM of \dec_cnt[4]_i_8\ : label is "soft_lutpair277";
  attribute SOFT_HLUTNM of \dec_cnt[4]_i_9\ : label is "soft_lutpair257";
  attribute SOFT_HLUTNM of \dec_cnt[5]_i_10\ : label is "soft_lutpair276";
  attribute SOFT_HLUTNM of \dec_cnt[5]_i_12\ : label is "soft_lutpair257";
  attribute SOFT_HLUTNM of \dec_cnt[5]_i_3\ : label is "soft_lutpair249";
  attribute SOFT_HLUTNM of \dec_cnt[5]_i_5\ : label is "soft_lutpair277";
  attribute SOFT_HLUTNM of \dec_cnt[5]_i_6\ : label is "soft_lutpair280";
  attribute SOFT_HLUTNM of \dec_cnt[5]_i_7\ : label is "soft_lutpair248";
  attribute SOFT_HLUTNM of \detect_rd_cnt[1]_i_1\ : label is "soft_lutpair289";
  attribute SOFT_HLUTNM of \detect_rd_cnt[2]_i_1\ : label is "soft_lutpair289";
  attribute SOFT_HLUTNM of \detect_rd_cnt[3]_i_3\ : label is "soft_lutpair246";
  attribute SOFT_HLUTNM of dqs_found_done_r_i_3 : label is "soft_lutpair258";
  attribute SOFT_HLUTNM of dqs_found_prech_req_i_1 : label is "soft_lutpair253";
  attribute SOFT_HLUTNM of dqs_found_prech_req_i_4 : label is "soft_lutpair262";
  attribute SOFT_HLUTNM of final_dec_done_i_1 : label is "soft_lutpair251";
  attribute SOFT_HLUTNM of \first_fail_taps[0]_i_1\ : label is "soft_lutpair284";
  attribute SOFT_HLUTNM of \first_fail_taps[1]_i_1\ : label is "soft_lutpair287";
  attribute SOFT_HLUTNM of \first_fail_taps[2]_i_1\ : label is "soft_lutpair288";
  attribute SOFT_HLUTNM of \first_fail_taps[4]_i_1\ : label is "soft_lutpair284";
  attribute SOFT_HLUTNM of \first_fail_taps[5]_i_2\ : label is "soft_lutpair287";
  attribute SOFT_HLUTNM of \first_fail_taps[5]_i_4\ : label is "soft_lutpair253";
  attribute SOFT_HLUTNM of \first_fail_taps[5]_i_5\ : label is "soft_lutpair252";
  attribute SOFT_HLUTNM of \gen_no_mirror.div_clk_loop[0].phy_address[10]_i_4\ : label is "soft_lutpair286";
  attribute SOFT_HLUTNM of \inc_cnt[1]_i_1\ : label is "soft_lutpair290";
  attribute SOFT_HLUTNM of \inc_cnt[2]_i_1\ : label is "soft_lutpair290";
  attribute SOFT_HLUTNM of \inc_cnt[3]_i_1\ : label is "soft_lutpair271";
  attribute SOFT_HLUTNM of \inc_cnt[4]_i_1\ : label is "soft_lutpair250";
  attribute SOFT_HLUTNM of \inc_cnt[5]_i_3\ : label is "soft_lutpair294";
  attribute SOFT_HLUTNM of \init_dec_cnt[1]_i_1\ : label is "soft_lutpair285";
  attribute SOFT_HLUTNM of \init_dec_cnt[2]_i_1\ : label is "soft_lutpair285";
  attribute SOFT_HLUTNM of \init_dec_cnt[3]_i_1\ : label is "soft_lutpair265";
  attribute SOFT_HLUTNM of \init_dec_cnt[4]_i_1\ : label is "soft_lutpair265";
  attribute SOFT_HLUTNM of \init_dec_cnt[5]_i_3\ : label is "soft_lutpair276";
  attribute SOFT_HLUTNM of init_dec_done_i_1 : label is "soft_lutpair251";
  attribute srl_name : string;
  attribute srl_name of init_dqsfound_done_r4_reg_srl2 : label is "\u_mig_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr/init_dqsfound_done_r4_reg_srl2 ";
  attribute SOFT_HLUTNM of \init_state_r[2]_i_28\ : label is "soft_lutpair286";
  attribute ASYNC_REG_boolean : boolean;
  attribute ASYNC_REG_boolean of \pi_dqs_found_lanes_r1_reg[0]\ : label is std.standard.true;
  attribute KEEP : string;
  attribute KEEP of \pi_dqs_found_lanes_r1_reg[0]\ : label is "yes";
  attribute ASYNC_REG_boolean of \pi_dqs_found_lanes_r1_reg[10]\ : label is std.standard.true;
  attribute KEEP of \pi_dqs_found_lanes_r1_reg[10]\ : label is "yes";
  attribute ASYNC_REG_boolean of \pi_dqs_found_lanes_r1_reg[11]\ : label is std.standard.true;
  attribute KEEP of \pi_dqs_found_lanes_r1_reg[11]\ : label is "yes";
  attribute ASYNC_REG_boolean of \pi_dqs_found_lanes_r1_reg[1]\ : label is std.standard.true;
  attribute KEEP of \pi_dqs_found_lanes_r1_reg[1]\ : label is "yes";
  attribute ASYNC_REG_boolean of \pi_dqs_found_lanes_r1_reg[2]\ : label is std.standard.true;
  attribute KEEP of \pi_dqs_found_lanes_r1_reg[2]\ : label is "yes";
  attribute ASYNC_REG_boolean of \pi_dqs_found_lanes_r1_reg[3]\ : label is std.standard.true;
  attribute KEEP of \pi_dqs_found_lanes_r1_reg[3]\ : label is "yes";
  attribute ASYNC_REG_boolean of \pi_dqs_found_lanes_r1_reg[4]\ : label is std.standard.true;
  attribute KEEP of \pi_dqs_found_lanes_r1_reg[4]\ : label is "yes";
  attribute ASYNC_REG_boolean of \pi_dqs_found_lanes_r1_reg[5]\ : label is std.standard.true;
  attribute KEEP of \pi_dqs_found_lanes_r1_reg[5]\ : label is "yes";
  attribute ASYNC_REG_boolean of \pi_dqs_found_lanes_r1_reg[6]\ : label is std.standard.true;
  attribute KEEP of \pi_dqs_found_lanes_r1_reg[6]\ : label is "yes";
  attribute ASYNC_REG_boolean of \pi_dqs_found_lanes_r1_reg[7]\ : label is std.standard.true;
  attribute KEEP of \pi_dqs_found_lanes_r1_reg[7]\ : label is "yes";
  attribute ASYNC_REG_boolean of \pi_dqs_found_lanes_r1_reg[8]\ : label is std.standard.true;
  attribute KEEP of \pi_dqs_found_lanes_r1_reg[8]\ : label is "yes";
  attribute ASYNC_REG_boolean of \pi_dqs_found_lanes_r1_reg[9]\ : label is std.standard.true;
  attribute KEEP of \pi_dqs_found_lanes_r1_reg[9]\ : label is "yes";
  attribute ASYNC_REG_boolean of \pi_dqs_found_lanes_r2_reg[0]\ : label is std.standard.true;
  attribute KEEP of \pi_dqs_found_lanes_r2_reg[0]\ : label is "yes";
  attribute ASYNC_REG_boolean of \pi_dqs_found_lanes_r2_reg[10]\ : label is std.standard.true;
  attribute KEEP of \pi_dqs_found_lanes_r2_reg[10]\ : label is "yes";
  attribute ASYNC_REG_boolean of \pi_dqs_found_lanes_r2_reg[11]\ : label is std.standard.true;
  attribute KEEP of \pi_dqs_found_lanes_r2_reg[11]\ : label is "yes";
  attribute ASYNC_REG_boolean of \pi_dqs_found_lanes_r2_reg[1]\ : label is std.standard.true;
  attribute KEEP of \pi_dqs_found_lanes_r2_reg[1]\ : label is "yes";
  attribute ASYNC_REG_boolean of \pi_dqs_found_lanes_r2_reg[2]\ : label is std.standard.true;
  attribute KEEP of \pi_dqs_found_lanes_r2_reg[2]\ : label is "yes";
  attribute ASYNC_REG_boolean of \pi_dqs_found_lanes_r2_reg[3]\ : label is std.standard.true;
  attribute KEEP of \pi_dqs_found_lanes_r2_reg[3]\ : label is "yes";
  attribute ASYNC_REG_boolean of \pi_dqs_found_lanes_r2_reg[4]\ : label is std.standard.true;
  attribute KEEP of \pi_dqs_found_lanes_r2_reg[4]\ : label is "yes";
  attribute ASYNC_REG_boolean of \pi_dqs_found_lanes_r2_reg[5]\ : label is std.standard.true;
  attribute KEEP of \pi_dqs_found_lanes_r2_reg[5]\ : label is "yes";
  attribute ASYNC_REG_boolean of \pi_dqs_found_lanes_r2_reg[6]\ : label is std.standard.true;
  attribute KEEP of \pi_dqs_found_lanes_r2_reg[6]\ : label is "yes";
  attribute ASYNC_REG_boolean of \pi_dqs_found_lanes_r2_reg[7]\ : label is std.standard.true;
  attribute KEEP of \pi_dqs_found_lanes_r2_reg[7]\ : label is "yes";
  attribute ASYNC_REG_boolean of \pi_dqs_found_lanes_r2_reg[8]\ : label is std.standard.true;
  attribute KEEP of \pi_dqs_found_lanes_r2_reg[8]\ : label is "yes";
  attribute ASYNC_REG_boolean of \pi_dqs_found_lanes_r2_reg[9]\ : label is std.standard.true;
  attribute KEEP of \pi_dqs_found_lanes_r2_reg[9]\ : label is "yes";
  attribute ASYNC_REG_boolean of \pi_dqs_found_lanes_r3_reg[0]\ : label is std.standard.true;
  attribute KEEP of \pi_dqs_found_lanes_r3_reg[0]\ : label is "yes";
  attribute ASYNC_REG_boolean of \pi_dqs_found_lanes_r3_reg[10]\ : label is std.standard.true;
  attribute KEEP of \pi_dqs_found_lanes_r3_reg[10]\ : label is "yes";
  attribute ASYNC_REG_boolean of \pi_dqs_found_lanes_r3_reg[11]\ : label is std.standard.true;
  attribute KEEP of \pi_dqs_found_lanes_r3_reg[11]\ : label is "yes";
  attribute ASYNC_REG_boolean of \pi_dqs_found_lanes_r3_reg[1]\ : label is std.standard.true;
  attribute KEEP of \pi_dqs_found_lanes_r3_reg[1]\ : label is "yes";
  attribute ASYNC_REG_boolean of \pi_dqs_found_lanes_r3_reg[2]\ : label is std.standard.true;
  attribute KEEP of \pi_dqs_found_lanes_r3_reg[2]\ : label is "yes";
  attribute ASYNC_REG_boolean of \pi_dqs_found_lanes_r3_reg[3]\ : label is std.standard.true;
  attribute KEEP of \pi_dqs_found_lanes_r3_reg[3]\ : label is "yes";
  attribute ASYNC_REG_boolean of \pi_dqs_found_lanes_r3_reg[4]\ : label is std.standard.true;
  attribute KEEP of \pi_dqs_found_lanes_r3_reg[4]\ : label is "yes";
  attribute ASYNC_REG_boolean of \pi_dqs_found_lanes_r3_reg[5]\ : label is std.standard.true;
  attribute KEEP of \pi_dqs_found_lanes_r3_reg[5]\ : label is "yes";
  attribute ASYNC_REG_boolean of \pi_dqs_found_lanes_r3_reg[6]\ : label is std.standard.true;
  attribute KEEP of \pi_dqs_found_lanes_r3_reg[6]\ : label is "yes";
  attribute ASYNC_REG_boolean of \pi_dqs_found_lanes_r3_reg[7]\ : label is std.standard.true;
  attribute KEEP of \pi_dqs_found_lanes_r3_reg[7]\ : label is "yes";
  attribute ASYNC_REG_boolean of \pi_dqs_found_lanes_r3_reg[8]\ : label is std.standard.true;
  attribute KEEP of \pi_dqs_found_lanes_r3_reg[8]\ : label is "yes";
  attribute ASYNC_REG_boolean of \pi_dqs_found_lanes_r3_reg[9]\ : label is std.standard.true;
  attribute KEEP of \pi_dqs_found_lanes_r3_reg[9]\ : label is "yes";
  attribute SOFT_HLUTNM of \pi_rst_stg1_cal[1]_i_1\ : label is "soft_lutpair293";
  attribute SOFT_HLUTNM of \pi_rst_stg1_cal[2]_i_1\ : label is "soft_lutpair293";
  attribute SOFT_HLUTNM of rank_done_r_i_1 : label is "soft_lutpair258";
  attribute SOFT_HLUTNM of \rank_final_loop[0].bank_final_loop[0].final_data_offset_mc[0][0]_i_1\ : label is "soft_lutpair282";
  attribute SOFT_HLUTNM of \rank_final_loop[0].bank_final_loop[0].final_data_offset_mc[0][1]_i_1\ : label is "soft_lutpair273";
  attribute SOFT_HLUTNM of \rank_final_loop[0].bank_final_loop[0].final_data_offset_mc[0][3]_i_1\ : label is "soft_lutpair263";
  attribute SOFT_HLUTNM of \rank_final_loop[0].bank_final_loop[0].final_data_offset_mc[0][4]_i_1\ : label is "soft_lutpair263";
  attribute SOFT_HLUTNM of \rank_final_loop[0].bank_final_loop[2].final_data_offset_mc[0][12]_i_1\ : label is "soft_lutpair283";
  attribute SOFT_HLUTNM of \rank_final_loop[0].bank_final_loop[2].final_data_offset_mc[0][13]_i_1\ : label is "soft_lutpair274";
  attribute SOFT_HLUTNM of \rank_final_loop[0].bank_final_loop[2].final_data_offset_mc[0][15]_i_1\ : label is "soft_lutpair264";
  attribute SOFT_HLUTNM of \rank_final_loop[0].bank_final_loop[2].final_data_offset_mc[0][16]_i_1\ : label is "soft_lutpair264";
  attribute SOFT_HLUTNM of \rank_final_loop[0].final_do_index[0][0]_i_1\ : label is "soft_lutpair292";
  attribute SOFT_HLUTNM of \rank_final_loop[0].final_do_index[0][1]_i_1\ : label is "soft_lutpair292";
  attribute SOFT_HLUTNM of \rank_final_loop[0].final_do_index[0][2]_i_1\ : label is "soft_lutpair291";
  attribute SOFT_HLUTNM of \rank_final_loop[0].final_do_max[0][1]_i_1\ : label is "soft_lutpair281";
  attribute SOFT_HLUTNM of \rank_final_loop[0].final_do_max[0][3]_i_1\ : label is "soft_lutpair260";
  attribute SOFT_HLUTNM of \rank_final_loop[0].final_do_max[0][4]_i_1\ : label is "soft_lutpair260";
  attribute SOFT_HLUTNM of \rank_final_loop[0].final_do_max[0][5]_i_10\ : label is "soft_lutpair281";
  attribute SOFT_HLUTNM of \rank_final_loop[0].final_do_max[0][5]_i_6\ : label is "soft_lutpair291";
  attribute SOFT_HLUTNM of \rd_byte_data_offset[0][10]_i_1\ : label is "soft_lutpair254";
  attribute SOFT_HLUTNM of \rd_byte_data_offset[0][13]_i_1\ : label is "soft_lutpair275";
  attribute SOFT_HLUTNM of \rd_byte_data_offset[0][14]_i_1\ : label is "soft_lutpair283";
  attribute SOFT_HLUTNM of \rd_byte_data_offset[0][15]_i_1\ : label is "soft_lutpair266";
  attribute SOFT_HLUTNM of \rd_byte_data_offset[0][16]_i_1\ : label is "soft_lutpair266";
  attribute SOFT_HLUTNM of \rd_byte_data_offset[0][1]_i_1\ : label is "soft_lutpair278";
  attribute SOFT_HLUTNM of \rd_byte_data_offset[0][2]_i_1\ : label is "soft_lutpair282";
  attribute SOFT_HLUTNM of \rd_byte_data_offset[0][3]_i_1\ : label is "soft_lutpair259";
  attribute SOFT_HLUTNM of \rd_byte_data_offset[0][4]_i_1\ : label is "soft_lutpair259";
  attribute SOFT_HLUTNM of \rd_byte_data_offset[0][7]_i_1\ : label is "soft_lutpair272";
  attribute SOFT_HLUTNM of \rd_byte_data_offset[0][9]_i_1\ : label is "soft_lutpair254";
  attribute SOFT_HLUTNM of \rnk_cnt_r[0]_i_1\ : label is "soft_lutpair270";
  attribute SOFT_HLUTNM of \rnk_cnt_r[1]_i_1\ : label is "soft_lutpair270";
  attribute SOFT_HLUTNM of \stable_pass_cnt[0]_i_1\ : label is "soft_lutpair255";
  attribute SOFT_HLUTNM of \stable_pass_cnt[1]_i_1\ : label is "soft_lutpair255";
  attribute SOFT_HLUTNM of \stable_pass_cnt[2]_i_1\ : label is "soft_lutpair256";
  attribute SOFT_HLUTNM of \stable_pass_cnt[3]_i_1\ : label is "soft_lutpair256";
begin
  Q(0) <= \^q\(0);
  \calib_sel1__1\ <= \^calib_sel1__1\;
  ck_po_stg2_f_en <= \^ck_po_stg2_f_en\;
  ck_po_stg2_f_indec <= \^ck_po_stg2_f_indec\;
  ctl_lane_sel <= \^ctl_lane_sel\;
  dqs_found_done_r_reg_0 <= \^dqs_found_done_r_reg_0\;
  dqs_found_prech_req <= \^dqs_found_prech_req\;
  fine_adjust_reg_0 <= \^fine_adjust_reg_0\;
  init_dqsfound_done_r2 <= \^init_dqsfound_done_r2\;
  pi_dqs_found_rank_done <= \^pi_dqs_found_rank_done\;
  \pi_rst_stg1_cal_reg[0]_0\ <= \^pi_rst_stg1_cal_reg[0]_0\;
  \pi_rst_stg1_cal_reg[2]_0\(2 downto 0) <= \^pi_rst_stg1_cal_reg[2]_0\(2 downto 0);
  \rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][5]_0\(5 downto 0) <= \^rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][5]_0\(5 downto 0);
  \rank_final_loop[0].bank_final_loop[0].final_data_offset_reg[0][3]_0\(0) <= \^rank_final_loop[0].bank_final_loop[0].final_data_offset_reg[0][3]_0\(0);
  \rank_final_loop[0].bank_final_loop[1].final_data_offset_mc_reg[0][11]_0\(5 downto 0) <= \^rank_final_loop[0].bank_final_loop[1].final_data_offset_mc_reg[0][11]_0\(5 downto 0);
  \rank_final_loop[0].bank_final_loop[1].final_data_offset_reg[0][9]_0\(0) <= \^rank_final_loop[0].bank_final_loop[1].final_data_offset_reg[0][9]_0\(0);
  \rank_final_loop[0].bank_final_loop[2].final_data_offset_mc_reg[0][17]_0\(5 downto 0) <= \^rank_final_loop[0].bank_final_loop[2].final_data_offset_mc_reg[0][17]_0\(5 downto 0);
  \rank_final_loop[0].bank_final_loop[2].final_data_offset_reg[0][15]_0\(0) <= \^rank_final_loop[0].bank_final_loop[2].final_data_offset_reg[0][15]_0\(0);
  \rd_byte_data_offset_reg[0][15]_0\(0) <= \^rd_byte_data_offset_reg[0][15]_0\(0);
  \rd_byte_data_offset_reg[0][9]_0\(0) <= \^rd_byte_data_offset_reg[0][9]_0\(0);
\FSM_sequential_fine_adj_state_r[0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"2220222222222222"
    )
        port map (
      I0 => \FSM_sequential_fine_adj_state_r[0]_i_2_n_0\,
      I1 => \FSM_sequential_fine_adj_state_r[0]_i_3_n_0\,
      I2 => \FSM_sequential_fine_adj_state_r[3]_i_4_n_0\,
      I3 => fine_adj_state_r(1),
      I4 => \FSM_sequential_fine_adj_state_r[0]_i_4_n_0\,
      I5 => final_dec_done_reg_n_0,
      O => \FSM_sequential_fine_adj_state_r[0]_i_1_n_0\
    );
\FSM_sequential_fine_adj_state_r[0]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFEFF"
    )
        port map (
      I0 => \FSM_sequential_fine_adj_state_r[0]_i_5_n_0\,
      I1 => fine_adj_state_r(1),
      I2 => fine_adj_state_r(0),
      I3 => fine_adj_state_r(3),
      I4 => \init_dec_cnt[5]_i_3_n_0\,
      I5 => \FSM_sequential_fine_adj_state_r[3]_i_4_n_0\,
      O => \FSM_sequential_fine_adj_state_r[0]_i_2_n_0\
    );
\FSM_sequential_fine_adj_state_r[0]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"3203FC3032033C30"
    )
        port map (
      I0 => \FSM_sequential_fine_adj_state_r[0]_i_6_n_0\,
      I1 => fine_adj_state_r(2),
      I2 => fine_adj_state_r(1),
      I3 => fine_adj_state_r(0),
      I4 => fine_adj_state_r(3),
      I5 => \init_dec_cnt[5]_i_3_n_0\,
      O => \FSM_sequential_fine_adj_state_r[0]_i_3_n_0\
    );
\FSM_sequential_fine_adj_state_r[0]_i_4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => fine_adj_state_r(0),
      I1 => fine_adj_state_r(3),
      O => \FSM_sequential_fine_adj_state_r[0]_i_4_n_0\
    );
\FSM_sequential_fine_adj_state_r[0]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFFFE"
    )
        port map (
      I0 => \dec_cnt_reg_n_0_[5]\,
      I1 => \dec_cnt_reg_n_0_[3]\,
      I2 => \dec_cnt_reg_n_0_[0]\,
      I3 => \dec_cnt_reg_n_0_[1]\,
      I4 => \dec_cnt_reg_n_0_[2]\,
      I5 => \dec_cnt_reg_n_0_[4]\,
      O => \FSM_sequential_fine_adj_state_r[0]_i_5_n_0\
    );
\FSM_sequential_fine_adj_state_r[0]_i_6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000400"
    )
        port map (
      I0 => detect_rd_cnt_reg(3),
      I1 => detect_pi_found_dqs,
      I2 => detect_rd_cnt_reg(2),
      I3 => detect_rd_cnt_reg(0),
      I4 => detect_rd_cnt_reg(1),
      O => \FSM_sequential_fine_adj_state_r[0]_i_6_n_0\
    );
\FSM_sequential_fine_adj_state_r[1]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"A0A2AAA2A0A0AAA0"
    )
        port map (
      I0 => \FSM_sequential_fine_adj_state_r[1]_i_2_n_0\,
      I1 => \FSM_sequential_fine_adj_state_r[1]_i_3_n_0\,
      I2 => \FSM_sequential_fine_adj_state_r[1]_i_4_n_0\,
      I3 => \FSM_sequential_fine_adj_state_r[1]_i_5_n_0\,
      I4 => \FSM_sequential_fine_adj_state_r[1]_i_6_n_0\,
      I5 => \FSM_sequential_fine_adj_state_r[1]_i_7_n_0\,
      O => \FSM_sequential_fine_adj_state_r[1]_i_1_n_0\
    );
\FSM_sequential_fine_adj_state_r[1]_i_10\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0200000200020000"
    )
        port map (
      I0 => \inc_cnt_reg_n_0_[5]\,
      I1 => \inc_cnt_reg_n_0_[0]\,
      I2 => \inc_cnt_reg_n_0_[1]\,
      I3 => \inc_cnt_reg_n_0_[3]\,
      I4 => \inc_cnt_reg_n_0_[4]\,
      I5 => \inc_cnt_reg_n_0_[2]\,
      O => \FSM_sequential_fine_adj_state_r[1]_i_10_n_0\
    );
\FSM_sequential_fine_adj_state_r[1]_i_11\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAAAAAAAAAA8"
    )
        port map (
      I0 => \inc_cnt_reg_n_0_[5]\,
      I1 => \inc_cnt_reg_n_0_[2]\,
      I2 => \inc_cnt_reg_n_0_[4]\,
      I3 => \inc_cnt_reg_n_0_[3]\,
      I4 => \inc_cnt_reg_n_0_[1]\,
      I5 => \inc_cnt_reg_n_0_[0]\,
      O => \FSM_sequential_fine_adj_state_r[1]_i_11_n_0\
    );
\FSM_sequential_fine_adj_state_r[1]_i_12\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000060000"
    )
        port map (
      I0 => \inc_cnt_reg_n_0_[4]\,
      I1 => \inc_cnt_reg_n_0_[2]\,
      I2 => \inc_cnt_reg_n_0_[1]\,
      I3 => \inc_cnt_reg_n_0_[0]\,
      I4 => \inc_cnt_reg_n_0_[3]\,
      I5 => \inc_cnt_reg_n_0_[5]\,
      O => \FSM_sequential_fine_adj_state_r[1]_i_12_n_0\
    );
\FSM_sequential_fine_adj_state_r[1]_i_13\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"4F"
    )
        port map (
      I0 => \FSM_sequential_fine_adj_state_r[1]_i_11_n_0\,
      I1 => \first_fail_taps[5]_i_3_n_0\,
      I2 => first_fail_detect_reg_n_0,
      O => \FSM_sequential_fine_adj_state_r[1]_i_13_n_0\
    );
\FSM_sequential_fine_adj_state_r[1]_i_14\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"7FFFFFFFFFFFFFFF"
    )
        port map (
      I0 => \inc_cnt_reg_n_0_[5]\,
      I1 => \inc_cnt_reg_n_0_[3]\,
      I2 => \inc_cnt_reg_n_0_[1]\,
      I3 => \inc_cnt_reg_n_0_[4]\,
      I4 => \inc_cnt_reg_n_0_[2]\,
      I5 => \inc_cnt_reg_n_0_[0]\,
      O => \FSM_sequential_fine_adj_state_r[1]_i_14_n_0\
    );
\FSM_sequential_fine_adj_state_r[1]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"ABBBABBAFFFFFFFF"
    )
        port map (
      I0 => \FSM_sequential_fine_adj_state_r[1]_i_8_n_0\,
      I1 => \inc_cnt[5]_i_3_n_0\,
      I2 => fine_adj_state_r(3),
      I3 => fine_adj_state_r(2),
      I4 => p_1_in30_in,
      I5 => \FSM_sequential_fine_adj_state_r[0]_i_2_n_0\,
      O => \FSM_sequential_fine_adj_state_r[1]_i_2_n_0\
    );
\FSM_sequential_fine_adj_state_r[1]_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"10000000"
    )
        port map (
      I0 => \FSM_sequential_fine_adj_state_r[1]_i_9_n_0\,
      I1 => \FSM_sequential_fine_adj_state_r[1]_i_10_n_0\,
      I2 => \FSM_sequential_fine_adj_state_r[1]_i_11_n_0\,
      I3 => \first_fail_taps[5]_i_3_n_0\,
      I4 => first_fail_detect_reg_n_0,
      O => \FSM_sequential_fine_adj_state_r[1]_i_3_n_0\
    );
\FSM_sequential_fine_adj_state_r[1]_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"BF"
    )
        port map (
      I0 => fine_adj_state_r(0),
      I1 => fine_adj_state_r(1),
      I2 => fine_adj_state_r(3),
      O => \FSM_sequential_fine_adj_state_r[1]_i_4_n_0\
    );
\FSM_sequential_fine_adj_state_r[1]_i_5\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"80FF"
    )
        port map (
      I0 => pi_dqs_found_all_bank(0),
      I1 => pi_dqs_found_all_bank(1),
      I2 => pi_dqs_found_all_bank(2),
      I3 => detect_pi_found_dqs,
      O => \FSM_sequential_fine_adj_state_r[1]_i_5_n_0\
    );
\FSM_sequential_fine_adj_state_r[1]_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"7FBFFFEBFFEBFFFF"
    )
        port map (
      I0 => \inc_cnt_reg_n_0_[0]\,
      I1 => \inc_cnt_reg_n_0_[2]\,
      I2 => \inc_cnt_reg_n_0_[4]\,
      I3 => \inc_cnt_reg_n_0_[1]\,
      I4 => \inc_cnt_reg_n_0_[3]\,
      I5 => \inc_cnt_reg_n_0_[5]\,
      O => \FSM_sequential_fine_adj_state_r[1]_i_6_n_0\
    );
\FSM_sequential_fine_adj_state_r[1]_i_7\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"EFEFEFFF"
    )
        port map (
      I0 => \FSM_sequential_fine_adj_state_r[1]_i_12_n_0\,
      I1 => \dec_cnt[5]_i_6_n_0\,
      I2 => \FSM_sequential_fine_adj_state_r[1]_i_13_n_0\,
      I3 => first_fail_detect_reg_n_0,
      I4 => \FSM_sequential_fine_adj_state_r[1]_i_14_n_0\,
      O => \FSM_sequential_fine_adj_state_r[1]_i_7_n_0\
    );
\FSM_sequential_fine_adj_state_r[1]_i_8\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"5050450050504550"
    )
        port map (
      I0 => fine_adj_state_r(1),
      I1 => \FSM_sequential_fine_adj_state_r[0]_i_6_n_0\,
      I2 => fine_adj_state_r(0),
      I3 => fine_adj_state_r(3),
      I4 => fine_adj_state_r(2),
      I5 => \FSM_sequential_fine_adj_state_r[3]_i_4_n_0\,
      O => \FSM_sequential_fine_adj_state_r[1]_i_8_n_0\
    );
\FSM_sequential_fine_adj_state_r[1]_i_9\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"80000000"
    )
        port map (
      I0 => \inc_cnt_reg_n_0_[0]\,
      I1 => \inc_cnt_reg_n_0_[2]\,
      I2 => \inc_cnt_reg_n_0_[4]\,
      I3 => \inc_cnt_reg_n_0_[1]\,
      I4 => \inc_cnt_reg_n_0_[3]\,
      O => \FSM_sequential_fine_adj_state_r[1]_i_9_n_0\
    );
\FSM_sequential_fine_adj_state_r[2]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"03C73FF003C73FC0"
    )
        port map (
      I0 => \FSM_sequential_fine_adj_state_r[2]_i_2_n_0\,
      I1 => fine_adj_state_r(1),
      I2 => fine_adj_state_r(0),
      I3 => fine_adj_state_r(2),
      I4 => fine_adj_state_r(3),
      I5 => \FSM_sequential_fine_adj_state_r[3]_i_4_n_0\,
      O => \FSM_sequential_fine_adj_state_r[2]_i_1_n_0\
    );
\FSM_sequential_fine_adj_state_r[2]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000FFFF7F00"
    )
        port map (
      I0 => pi_dqs_found_all_bank(0),
      I1 => pi_dqs_found_all_bank(1),
      I2 => pi_dqs_found_all_bank(2),
      I3 => detect_pi_found_dqs,
      I4 => \FSM_sequential_fine_adj_state_r[2]_i_3_n_0\,
      I5 => \FSM_sequential_fine_adj_state_r[2]_i_4_n_0\,
      O => \FSM_sequential_fine_adj_state_r[2]_i_2_n_0\
    );
\FSM_sequential_fine_adj_state_r[2]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFF79FFFFFF9F"
    )
        port map (
      I0 => \inc_cnt_reg_n_0_[2]\,
      I1 => \inc_cnt_reg_n_0_[4]\,
      I2 => \inc_cnt_reg_n_0_[3]\,
      I3 => \inc_cnt_reg_n_0_[1]\,
      I4 => \inc_cnt_reg_n_0_[0]\,
      I5 => \inc_cnt_reg_n_0_[5]\,
      O => \FSM_sequential_fine_adj_state_r[2]_i_3_n_0\
    );
\FSM_sequential_fine_adj_state_r[2]_i_4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000F808"
    )
        port map (
      I0 => \FSM_sequential_fine_adj_state_r[1]_i_10_n_0\,
      I1 => \FSM_sequential_fine_adj_state_r[2]_i_5_n_0\,
      I2 => \FSM_sequential_fine_adj_state_r[1]_i_13_n_0\,
      I3 => \FSM_sequential_fine_adj_state_r[1]_i_12_n_0\,
      I4 => \FSM_sequential_fine_adj_state_r[1]_i_5_n_0\,
      O => \FSM_sequential_fine_adj_state_r[2]_i_4_n_0\
    );
\FSM_sequential_fine_adj_state_r[2]_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"08"
    )
        port map (
      I0 => \FSM_sequential_fine_adj_state_r[1]_i_11_n_0\,
      I1 => \first_fail_taps[5]_i_3_n_0\,
      I2 => \FSM_sequential_fine_adj_state_r[1]_i_9_n_0\,
      O => \FSM_sequential_fine_adj_state_r[2]_i_5_n_0\
    );
\FSM_sequential_fine_adj_state_r[3]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFF00008000"
    )
        port map (
      I0 => fine_adj_state_r(1),
      I1 => pi_dqs_found_all_bank(0),
      I2 => pi_dqs_found_all_bank(1),
      I3 => pi_dqs_found_all_bank(2),
      I4 => fine_adj_state_r(3),
      I5 => \FSM_sequential_fine_adj_state_r[3]_i_3_n_0\,
      O => \FSM_sequential_fine_adj_state_r[3]_i_1_n_0\
    );
\FSM_sequential_fine_adj_state_r[3]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000030CCCCE0"
    )
        port map (
      I0 => \FSM_sequential_fine_adj_state_r[3]_i_4_n_0\,
      I1 => fine_adj_state_r(3),
      I2 => fine_adj_state_r(0),
      I3 => fine_adj_state_r(2),
      I4 => fine_adj_state_r(1),
      I5 => \FSM_sequential_fine_adj_state_r[3]_i_5_n_0\,
      O => \FSM_sequential_fine_adj_state_r[3]_i_2_n_0\
    );
\FSM_sequential_fine_adj_state_r[3]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFF0FF20FC2"
    )
        port map (
      I0 => init_dqsfound_done_r5,
      I1 => fine_adj_state_r(1),
      I2 => fine_adj_state_r(0),
      I3 => fine_adj_state_r(2),
      I4 => \FSM_sequential_fine_adj_state_r[3]_i_6_n_0\,
      I5 => \FSM_sequential_fine_adj_state_r[3]_i_7_n_0\,
      O => \FSM_sequential_fine_adj_state_r[3]_i_3_n_0\
    );
\FSM_sequential_fine_adj_state_r[3]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFFFE"
    )
        port map (
      I0 => init_dec_cnt_reg(5),
      I1 => init_dec_cnt_reg(3),
      I2 => init_dec_cnt_reg(0),
      I3 => init_dec_cnt_reg(1),
      I4 => init_dec_cnt_reg(2),
      I5 => init_dec_cnt_reg(4),
      O => \FSM_sequential_fine_adj_state_r[3]_i_4_n_0\
    );
\FSM_sequential_fine_adj_state_r[3]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"32FF323232323232"
    )
        port map (
      I0 => \FSM_sequential_fine_adj_state_r[3]_i_8_n_0\,
      I1 => \FSM_sequential_fine_adj_state_r[3]_i_9_n_0\,
      I2 => \FSM_sequential_fine_adj_state_r[1]_i_3_n_0\,
      I3 => \inc_cnt[5]_i_3_n_0\,
      I4 => \FSM_sequential_fine_adj_state_r[1]_i_5_n_0\,
      I5 => \FSM_sequential_fine_adj_state_r[1]_i_6_n_0\,
      O => \FSM_sequential_fine_adj_state_r[3]_i_5_n_0\
    );
\FSM_sequential_fine_adj_state_r[3]_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"04"
    )
        port map (
      I0 => pi_dqs_found_any_bank(2),
      I1 => rst_dqs_find_r2,
      I2 => pi_dqs_found_any_bank(0),
      O => \FSM_sequential_fine_adj_state_r[3]_i_6_n_0\
    );
\FSM_sequential_fine_adj_state_r[3]_i_7\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"EFCC2FCC"
    )
        port map (
      I0 => detect_pi_found_dqs,
      I1 => fine_adj_state_r(2),
      I2 => fine_adj_state_r(1),
      I3 => fine_adj_state_r(3),
      I4 => prech_done,
      O => \FSM_sequential_fine_adj_state_r[3]_i_7_n_0\
    );
\FSM_sequential_fine_adj_state_r[3]_i_8\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \FSM_sequential_fine_adj_state_r[1]_i_13_n_0\,
      I1 => \FSM_sequential_fine_adj_state_r[1]_i_12_n_0\,
      O => \FSM_sequential_fine_adj_state_r[3]_i_8_n_0\
    );
\FSM_sequential_fine_adj_state_r[3]_i_9\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFBBBF"
    )
        port map (
      I0 => fine_adj_state_r(0),
      I1 => fine_adj_state_r(1),
      I2 => first_fail_detect_reg_n_0,
      I3 => \FSM_sequential_fine_adj_state_r[1]_i_14_n_0\,
      I4 => \dec_cnt[5]_i_6_n_0\,
      I5 => \FSM_sequential_fine_adj_state_r[1]_i_5_n_0\,
      O => \FSM_sequential_fine_adj_state_r[3]_i_9_n_0\
    );
\FSM_sequential_fine_adj_state_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => init_dqsfound_done_r5_reg_0,
      CE => \FSM_sequential_fine_adj_state_r[3]_i_1_n_0\,
      D => \FSM_sequential_fine_adj_state_r[0]_i_1_n_0\,
      Q => fine_adj_state_r(0),
      R => \pi_dqs_found_any_bank_reg[0]_0\(1)
    );
\FSM_sequential_fine_adj_state_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => init_dqsfound_done_r5_reg_0,
      CE => \FSM_sequential_fine_adj_state_r[3]_i_1_n_0\,
      D => \FSM_sequential_fine_adj_state_r[1]_i_1_n_0\,
      Q => fine_adj_state_r(1),
      R => \pi_dqs_found_any_bank_reg[0]_0\(1)
    );
\FSM_sequential_fine_adj_state_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => init_dqsfound_done_r5_reg_0,
      CE => \FSM_sequential_fine_adj_state_r[3]_i_1_n_0\,
      D => \FSM_sequential_fine_adj_state_r[2]_i_1_n_0\,
      Q => fine_adj_state_r(2),
      R => \pi_dqs_found_any_bank_reg[0]_0\(1)
    );
\FSM_sequential_fine_adj_state_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => init_dqsfound_done_r5_reg_0,
      CE => \FSM_sequential_fine_adj_state_r[3]_i_1_n_0\,
      D => \FSM_sequential_fine_adj_state_r[3]_i_2_n_0\,
      Q => fine_adj_state_r(3),
      R => \pi_dqs_found_any_bank_reg[0]_0\(1)
    );
\calib_data_offset_0[0]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"CDC8"
    )
        port map (
      I0 => pi_dqs_found_done_r1,
      I1 => rd_data_offset_ranks_0(0),
      I2 => \^init_dqsfound_done_r2\,
      I3 => \rd_byte_data_offset_reg_n_0_[0][0]\,
      O => pi_dqs_found_done_r1_reg_3
    );
\calib_data_offset_0[1]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"CDC8"
    )
        port map (
      I0 => pi_dqs_found_done_r1,
      I1 => rd_data_offset_ranks_0(1),
      I2 => \^init_dqsfound_done_r2\,
      I3 => \rd_byte_data_offset_reg_n_0_[0][1]\,
      O => pi_dqs_found_done_r1_reg_2
    );
\calib_data_offset_0[2]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"CDC8"
    )
        port map (
      I0 => pi_dqs_found_done_r1,
      I1 => rd_data_offset_ranks_0(2),
      I2 => \^init_dqsfound_done_r2\,
      I3 => \rd_byte_data_offset_reg_n_0_[0][2]\,
      O => pi_dqs_found_done_r1_reg_1
    );
\calib_data_offset_0[4]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"CDC8"
    )
        port map (
      I0 => pi_dqs_found_done_r1,
      I1 => rd_data_offset_ranks_0(4),
      I2 => \^init_dqsfound_done_r2\,
      I3 => \rd_byte_data_offset_reg_n_0_[0][4]\,
      O => pi_dqs_found_done_r1_reg_0
    );
\calib_data_offset_0[5]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"CDC8"
    )
        port map (
      I0 => pi_dqs_found_done_r1,
      I1 => rd_data_offset_ranks_0(5),
      I2 => \^init_dqsfound_done_r2\,
      I3 => \rd_byte_data_offset_reg_n_0_[0][5]\,
      O => pi_dqs_found_done_r1_reg
    );
\calib_data_offset_1[0]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"CDC8"
    )
        port map (
      I0 => pi_dqs_found_done_r1,
      I1 => rd_data_offset_ranks_1(0),
      I2 => \^init_dqsfound_done_r2\,
      I3 => \rd_byte_data_offset_reg_n_0_[0][6]\,
      O => pi_dqs_found_done_r1_reg_8
    );
\calib_data_offset_1[1]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"CDC8"
    )
        port map (
      I0 => pi_dqs_found_done_r1,
      I1 => rd_data_offset_ranks_1(1),
      I2 => \^init_dqsfound_done_r2\,
      I3 => \rd_byte_data_offset_reg_n_0_[0][7]\,
      O => pi_dqs_found_done_r1_reg_7
    );
\calib_data_offset_1[2]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"CDC8"
    )
        port map (
      I0 => pi_dqs_found_done_r1,
      I1 => rd_data_offset_ranks_1(2),
      I2 => \^init_dqsfound_done_r2\,
      I3 => \rd_byte_data_offset_reg_n_0_[0][8]\,
      O => pi_dqs_found_done_r1_reg_6
    );
\calib_data_offset_1[4]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"CDC8"
    )
        port map (
      I0 => pi_dqs_found_done_r1,
      I1 => rd_data_offset_ranks_1(4),
      I2 => \^init_dqsfound_done_r2\,
      I3 => \rd_byte_data_offset_reg_n_0_[0][10]\,
      O => pi_dqs_found_done_r1_reg_5
    );
\calib_data_offset_1[5]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"CDC8"
    )
        port map (
      I0 => pi_dqs_found_done_r1,
      I1 => rd_data_offset_ranks_1(5),
      I2 => \^init_dqsfound_done_r2\,
      I3 => \rd_byte_data_offset_reg_n_0_[0][11]\,
      O => pi_dqs_found_done_r1_reg_4
    );
\calib_data_offset_2[0]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"CDC8"
    )
        port map (
      I0 => pi_dqs_found_done_r1,
      I1 => rd_data_offset_ranks_2(0),
      I2 => \^init_dqsfound_done_r2\,
      I3 => \rd_byte_data_offset_reg_n_0_[0][12]\,
      O => pi_dqs_found_done_r1_reg_13
    );
\calib_data_offset_2[1]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"CDC8"
    )
        port map (
      I0 => pi_dqs_found_done_r1,
      I1 => rd_data_offset_ranks_2(1),
      I2 => \^init_dqsfound_done_r2\,
      I3 => \rd_byte_data_offset_reg_n_0_[0][13]\,
      O => pi_dqs_found_done_r1_reg_12
    );
\calib_data_offset_2[2]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"CDC8"
    )
        port map (
      I0 => pi_dqs_found_done_r1,
      I1 => rd_data_offset_ranks_2(2),
      I2 => \^init_dqsfound_done_r2\,
      I3 => \rd_byte_data_offset_reg_n_0_[0][14]\,
      O => pi_dqs_found_done_r1_reg_11
    );
\calib_data_offset_2[4]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"CDC8"
    )
        port map (
      I0 => pi_dqs_found_done_r1,
      I1 => rd_data_offset_ranks_2(4),
      I2 => \^init_dqsfound_done_r2\,
      I3 => \rd_byte_data_offset_reg_n_0_[0][16]\,
      O => pi_dqs_found_done_r1_reg_10
    );
\calib_data_offset_2[5]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"CDC8"
    )
        port map (
      I0 => pi_dqs_found_done_r1,
      I1 => rd_data_offset_ranks_2(5),
      I2 => \^init_dqsfound_done_r2\,
      I3 => \rd_byte_data_offset_reg_n_0_[0][17]\,
      O => pi_dqs_found_done_r1_reg_9
    );
\calib_sel[0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"100010001FFF1000"
    )
        port map (
      I0 => \gen_byte_sel_div2.ctl_lane_sel_reg[2]_1\,
      I1 => \gen_byte_sel_div2.ctl_lane_sel_reg[0]\,
      I2 => \^calib_sel1__1\,
      I3 => cmd_delay_start0,
      I4 => \calib_sel_reg[0]\(0),
      I5 => \calib_sel_reg[0]\(2),
      O => \gen_byte_sel_div2.ctl_lane_sel_reg[2]\
    );
\calib_sel[1]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"14FFFFFF14000000"
    )
        port map (
      I0 => \gen_byte_sel_div2.ctl_lane_sel_reg[2]_1\,
      I1 => \gen_byte_sel_div2.ctl_lane_sel_reg[1]\,
      I2 => \gen_byte_sel_div2.ctl_lane_sel_reg[0]\,
      I3 => \^calib_sel1__1\,
      I4 => cmd_delay_start0,
      I5 => \calib_sel_reg[1]\,
      O => \gen_byte_sel_div2.ctl_lane_sel_reg[2]_0\
    );
\calib_sel[1]_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"4F"
    )
        port map (
      I0 => fine_adjust_done_r_reg_n_0,
      I1 => rd_data_offset_cal_done,
      I2 => ck_addr_cmd_delay_done,
      O => \^calib_sel1__1\
    );
\calib_sel[3]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"08088808"
    )
        port map (
      I0 => pi_fine_dly_dec_done,
      I1 => dqs_po_dec_done,
      I2 => ck_addr_cmd_delay_done,
      I3 => rd_data_offset_cal_done,
      I4 => fine_adjust_done_r_reg_n_0,
      O => \^ctl_lane_sel\
    );
\calib_sel[4]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"000000000000A2FF"
    )
        port map (
      I0 => ck_addr_cmd_delay_done,
      I1 => rd_data_offset_cal_done,
      I2 => fine_adjust_done_r_reg_n_0,
      I3 => cmd_delay_start0,
      I4 => \calib_sel_reg[0]\(2),
      I5 => \calib_sel_reg[0]\(1),
      O => delay_done_r4_reg_0
    );
ck_po_stg2_f_en_i_1: unisim.vcomponents.LUT5
    generic map(
      INIT => X"E7FF0280"
    )
        port map (
      I0 => fine_adj_state_r(1),
      I1 => fine_adj_state_r(0),
      I2 => fine_adj_state_r(3),
      I3 => fine_adj_state_r(2),
      I4 => \^ck_po_stg2_f_en\,
      O => ck_po_stg2_f_en_i_1_n_0
    );
ck_po_stg2_f_en_reg: unisim.vcomponents.FDRE
     port map (
      C => init_dqsfound_done_r5_reg_0,
      CE => '1',
      D => ck_po_stg2_f_en_i_1_n_0,
      Q => \^ck_po_stg2_f_en\,
      R => \pi_dqs_found_any_bank_reg[0]_0\(0)
    );
ck_po_stg2_f_indec_i_1: unisim.vcomponents.LUT5
    generic map(
      INIT => X"E77F0200"
    )
        port map (
      I0 => fine_adj_state_r(1),
      I1 => fine_adj_state_r(0),
      I2 => fine_adj_state_r(3),
      I3 => fine_adj_state_r(2),
      I4 => \^ck_po_stg2_f_indec\,
      O => ck_po_stg2_f_indec_i_1_n_0
    );
ck_po_stg2_f_indec_reg: unisim.vcomponents.FDRE
     port map (
      C => init_dqsfound_done_r5_reg_0,
      CE => '1',
      D => ck_po_stg2_f_indec_i_1_n_0,
      Q => \^ck_po_stg2_f_indec\,
      R => \pi_dqs_found_any_bank_reg[0]_0\(1)
    );
\cmd_pipe_plus.mc_data_offset[0]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \^rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][5]_0\(0),
      O => \rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][0]_0\
    );
\cmd_pipe_plus.mc_data_offset_1[0]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \^rank_final_loop[0].bank_final_loop[1].final_data_offset_mc_reg[0][11]_0\(0),
      O => \rank_final_loop[0].bank_final_loop[1].final_data_offset_mc_reg[0][6]_0\
    );
\cmd_pipe_plus.mc_data_offset_2[0]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \^rank_final_loop[0].bank_final_loop[2].final_data_offset_mc_reg[0][17]_0\(0),
      O => \rank_final_loop[0].bank_final_loop[2].final_data_offset_mc_reg[0][12]_0\
    );
\ctl_lane_cnt[0]_i_1__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0FD0"
    )
        port map (
      I0 => fine_adjust_lane_cnt(1),
      I1 => fine_adjust_lane_cnt(2),
      I2 => ctl_lane_cnt_0,
      I3 => fine_adjust_lane_cnt(0),
      O => \ctl_lane_cnt[0]_i_1__0_n_0\
    );
\ctl_lane_cnt[1]_i_1__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2FC0"
    )
        port map (
      I0 => fine_adjust_lane_cnt(2),
      I1 => fine_adjust_lane_cnt(0),
      I2 => ctl_lane_cnt_0,
      I3 => fine_adjust_lane_cnt(1),
      O => \ctl_lane_cnt[1]_i_1__0_n_0\
    );
\ctl_lane_cnt[2]_i_1__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7F80"
    )
        port map (
      I0 => fine_adjust_lane_cnt(1),
      I1 => fine_adjust_lane_cnt(0),
      I2 => ctl_lane_cnt_0,
      I3 => fine_adjust_lane_cnt(2),
      O => \ctl_lane_cnt[2]_i_1__0_n_0\
    );
\ctl_lane_cnt[2]_i_2__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0280"
    )
        port map (
      I0 => fine_adj_state_r(2),
      I1 => fine_adj_state_r(0),
      I2 => fine_adj_state_r(1),
      I3 => fine_adj_state_r(3),
      O => ctl_lane_cnt_0
    );
\ctl_lane_cnt_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => init_dqsfound_done_r5_reg_0,
      CE => '1',
      D => \ctl_lane_cnt[0]_i_1__0_n_0\,
      Q => fine_adjust_lane_cnt(0),
      R => \pi_dqs_found_any_bank_reg[0]_0\(1)
    );
\ctl_lane_cnt_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => init_dqsfound_done_r5_reg_0,
      CE => '1',
      D => \ctl_lane_cnt[1]_i_1__0_n_0\,
      Q => fine_adjust_lane_cnt(1),
      R => \pi_dqs_found_any_bank_reg[0]_0\(1)
    );
\ctl_lane_cnt_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => init_dqsfound_done_r5_reg_0,
      CE => '1',
      D => \ctl_lane_cnt[2]_i_1__0_n_0\,
      Q => fine_adjust_lane_cnt(2),
      R => \pi_dqs_found_any_bank_reg[0]_0\(1)
    );
\dec_cnt[0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"4744474447447777"
    )
        port map (
      I0 => \dec_cnt_reg_n_0_[0]\,
      I1 => fine_adj_state_r(0),
      I2 => \dec_cnt[4]_i_3_n_0\,
      I3 => \dec_cnt_reg[2]_i_2_n_6\,
      I4 => \FSM_sequential_fine_adj_state_r[1]_i_5_n_0\,
      I5 => \dec_cnt[0]_i_2_n_0\,
      O => dec_cnt(0)
    );
\dec_cnt[0]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8888BBB8BBBBBBB8"
    )
        port map (
      I0 => \inc_cnt_reg_n_0_[1]\,
      I1 => \dec_cnt[5]_i_6_n_0\,
      I2 => \first_fail_taps_reg_n_0_[1]\,
      I3 => \first_fail_taps[5]_i_3_n_0\,
      I4 => \FSM_sequential_fine_adj_state_r[1]_i_14_n_0\,
      I5 => \dec_cnt_reg[2]_i_2_n_6\,
      O => \dec_cnt[0]_i_2_n_0\
    );
\dec_cnt[1]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"909F90909F9F9F9F"
    )
        port map (
      I0 => \dec_cnt_reg_n_0_[0]\,
      I1 => \dec_cnt_reg_n_0_[1]\,
      I2 => fine_adj_state_r(0),
      I3 => \dec_cnt[4]_i_3_n_0\,
      I4 => \dec_cnt_reg[2]_i_2_n_5\,
      I5 => \dec_cnt[1]_i_2_n_0\,
      O => dec_cnt(1)
    );
\dec_cnt[1]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FEAEAEFE"
    )
        port map (
      I0 => \FSM_sequential_fine_adj_state_r[1]_i_5_n_0\,
      I1 => \dec_cnt[1]_i_3_n_0\,
      I2 => \dec_cnt[5]_i_6_n_0\,
      I3 => \inc_cnt_reg_n_0_[2]\,
      I4 => \inc_cnt_reg_n_0_[1]\,
      O => \dec_cnt[1]_i_2_n_0\
    );
\dec_cnt[1]_i_3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0EFE"
    )
        port map (
      I0 => \first_fail_taps_reg_n_0_[2]\,
      I1 => \first_fail_taps[5]_i_3_n_0\,
      I2 => \FSM_sequential_fine_adj_state_r[1]_i_14_n_0\,
      I3 => \dec_cnt_reg[2]_i_2_n_5\,
      O => \dec_cnt[1]_i_3_n_0\
    );
\dec_cnt[2]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFF400F400F4FFF4"
    )
        port map (
      I0 => \dec_cnt[4]_i_3_n_0\,
      I1 => \dec_cnt_reg[2]_i_2_n_4\,
      I2 => \dec_cnt[2]_i_3_n_0\,
      I3 => fine_adj_state_r(0),
      I4 => \dec_cnt_reg_n_0_[2]\,
      I5 => \dec_cnt[2]_i_4_n_0\,
      O => dec_cnt(2)
    );
\dec_cnt[2]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0151515151010101"
    )
        port map (
      I0 => \FSM_sequential_fine_adj_state_r[1]_i_5_n_0\,
      I1 => \dec_cnt[2]_i_9_n_0\,
      I2 => \dec_cnt[5]_i_6_n_0\,
      I3 => \inc_cnt_reg_n_0_[1]\,
      I4 => \inc_cnt_reg_n_0_[2]\,
      I5 => \inc_cnt_reg_n_0_[3]\,
      O => \dec_cnt[2]_i_3_n_0\
    );
\dec_cnt[2]_i_4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => \dec_cnt_reg_n_0_[0]\,
      I1 => \dec_cnt_reg_n_0_[1]\,
      O => \dec_cnt[2]_i_4_n_0\
    );
\dec_cnt[2]_i_5\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => \inc_cnt_reg_n_0_[3]\,
      I1 => \first_fail_taps_reg_n_0_[3]\,
      O => \dec_cnt[2]_i_5_n_0\
    );
\dec_cnt[2]_i_6\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => \inc_cnt_reg_n_0_[2]\,
      I1 => \first_fail_taps_reg_n_0_[2]\,
      O => \dec_cnt[2]_i_6_n_0\
    );
\dec_cnt[2]_i_7\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => \inc_cnt_reg_n_0_[1]\,
      I1 => \first_fail_taps_reg_n_0_[1]\,
      O => \dec_cnt[2]_i_7_n_0\
    );
\dec_cnt[2]_i_8\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => \inc_cnt_reg_n_0_[0]\,
      I1 => \first_fail_taps_reg_n_0_[0]\,
      O => \dec_cnt[2]_i_8_n_0\
    );
\dec_cnt[2]_i_9\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0EFE"
    )
        port map (
      I0 => \first_fail_taps_reg_n_0_[3]\,
      I1 => \first_fail_taps[5]_i_3_n_0\,
      I2 => \FSM_sequential_fine_adj_state_r[1]_i_14_n_0\,
      I3 => \dec_cnt_reg[2]_i_2_n_4\,
      O => \dec_cnt[2]_i_9_n_0\
    );
\dec_cnt[3]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8A888A888A88AAAA"
    )
        port map (
      I0 => \dec_cnt[3]_i_2_n_0\,
      I1 => fine_adj_state_r(0),
      I2 => \dec_cnt[4]_i_3_n_0\,
      I3 => \dec_cnt_reg[4]_i_4_n_7\,
      I4 => \FSM_sequential_fine_adj_state_r[1]_i_5_n_0\,
      I5 => \dec_cnt[3]_i_3_n_0\,
      O => dec_cnt(3)
    );
\dec_cnt[3]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFD5557"
    )
        port map (
      I0 => fine_adj_state_r(0),
      I1 => \dec_cnt_reg_n_0_[2]\,
      I2 => \dec_cnt_reg_n_0_[1]\,
      I3 => \dec_cnt_reg_n_0_[0]\,
      I4 => \dec_cnt_reg_n_0_[3]\,
      O => \dec_cnt[3]_i_2_n_0\
    );
\dec_cnt[3]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8888BBB8BBBBBBB8"
    )
        port map (
      I0 => \dec_cnt[3]_i_4_n_0\,
      I1 => \dec_cnt[5]_i_6_n_0\,
      I2 => \first_fail_taps_reg_n_0_[4]\,
      I3 => \first_fail_taps[5]_i_3_n_0\,
      I4 => \FSM_sequential_fine_adj_state_r[1]_i_14_n_0\,
      I5 => \dec_cnt_reg[4]_i_4_n_7\,
      O => \dec_cnt[3]_i_3_n_0\
    );
\dec_cnt[3]_i_4\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9555"
    )
        port map (
      I0 => \inc_cnt_reg_n_0_[4]\,
      I1 => \inc_cnt_reg_n_0_[3]\,
      I2 => \inc_cnt_reg_n_0_[1]\,
      I3 => \inc_cnt_reg_n_0_[2]\,
      O => \dec_cnt[3]_i_4_n_0\
    );
\dec_cnt[4]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"909F90909F9F9F9F"
    )
        port map (
      I0 => \dec_cnt_reg_n_0_[4]\,
      I1 => \dec_cnt[4]_i_2_n_0\,
      I2 => fine_adj_state_r(0),
      I3 => \dec_cnt[4]_i_3_n_0\,
      I4 => \dec_cnt_reg[4]_i_4_n_6\,
      I5 => \dec_cnt[4]_i_5_n_0\,
      O => dec_cnt(4)
    );
\dec_cnt[4]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFFE"
    )
        port map (
      I0 => \dec_cnt_reg_n_0_[3]\,
      I1 => \dec_cnt_reg_n_0_[0]\,
      I2 => \dec_cnt_reg_n_0_[1]\,
      I3 => \dec_cnt_reg_n_0_[2]\,
      O => \dec_cnt[4]_i_2_n_0\
    );
\dec_cnt[4]_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AEEEEEEE"
    )
        port map (
      I0 => \dec_cnt[5]_i_11_n_0\,
      I1 => detect_pi_found_dqs,
      I2 => pi_dqs_found_all_bank(2),
      I3 => pi_dqs_found_all_bank(1),
      I4 => pi_dqs_found_all_bank(0),
      O => \dec_cnt[4]_i_3_n_0\
    );
\dec_cnt[4]_i_5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AEFEFEAE"
    )
        port map (
      I0 => \FSM_sequential_fine_adj_state_r[1]_i_5_n_0\,
      I1 => \dec_cnt[4]_i_8_n_0\,
      I2 => \dec_cnt[5]_i_6_n_0\,
      I3 => \dec_cnt[4]_i_9_n_0\,
      I4 => \inc_cnt_reg_n_0_[5]\,
      O => \dec_cnt[4]_i_5_n_0\
    );
\dec_cnt[4]_i_6\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => \inc_cnt_reg_n_0_[5]\,
      I1 => \first_fail_taps_reg_n_0_[5]\,
      O => \dec_cnt[4]_i_6_n_0\
    );
\dec_cnt[4]_i_7\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => \inc_cnt_reg_n_0_[4]\,
      I1 => \first_fail_taps_reg_n_0_[4]\,
      O => \dec_cnt[4]_i_7_n_0\
    );
\dec_cnt[4]_i_8\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0EFE"
    )
        port map (
      I0 => \first_fail_taps_reg_n_0_[5]\,
      I1 => \first_fail_taps[5]_i_3_n_0\,
      I2 => \FSM_sequential_fine_adj_state_r[1]_i_14_n_0\,
      I3 => \dec_cnt_reg[4]_i_4_n_6\,
      O => \dec_cnt[4]_i_8_n_0\
    );
\dec_cnt[4]_i_9\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7FFF"
    )
        port map (
      I0 => \inc_cnt_reg_n_0_[3]\,
      I1 => \inc_cnt_reg_n_0_[1]\,
      I2 => \inc_cnt_reg_n_0_[4]\,
      I3 => \inc_cnt_reg_n_0_[2]\,
      O => \dec_cnt[4]_i_9_n_0\
    );
\dec_cnt[5]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"4444444455555554"
    )
        port map (
      I0 => \dec_cnt[5]_i_3_n_0\,
      I1 => \dec_cnt[5]_i_4_n_0\,
      I2 => \first_fail_taps[5]_i_5_n_0\,
      I3 => \dec_cnt[5]_i_5_n_0\,
      I4 => \dec_cnt[5]_i_6_n_0\,
      I5 => \dec_cnt[5]_i_7_n_0\,
      O => \dec_cnt[5]_i_1_n_0\
    );
\dec_cnt[5]_i_10\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0010"
    )
        port map (
      I0 => \FSM_sequential_fine_adj_state_r[3]_i_4_n_0\,
      I1 => fine_adjust_lane_cnt(2),
      I2 => fine_adjust_lane_cnt(1),
      I3 => fine_adjust_lane_cnt(0),
      O => \dec_cnt[5]_i_10_n_0\
    );
\dec_cnt[5]_i_11\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFE0000FFFFFFFF"
    )
        port map (
      I0 => \first_fail_taps_reg_n_0_[2]\,
      I1 => \first_fail_taps_reg_n_0_[3]\,
      I2 => \first_fail_taps_reg_n_0_[1]\,
      I3 => \first_fail_taps_reg_n_0_[4]\,
      I4 => \first_fail_taps_reg_n_0_[5]\,
      I5 => first_fail_detect_reg_n_0,
      O => \dec_cnt[5]_i_11_n_0\
    );
\dec_cnt[5]_i_12\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"7FFFFFFF"
    )
        port map (
      I0 => \inc_cnt_reg_n_0_[2]\,
      I1 => \inc_cnt_reg_n_0_[4]\,
      I2 => \inc_cnt_reg_n_0_[1]\,
      I3 => \inc_cnt_reg_n_0_[3]\,
      I4 => \inc_cnt_reg_n_0_[5]\,
      O => \dec_cnt[5]_i_12_n_0\
    );
\dec_cnt[5]_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"BF"
    )
        port map (
      I0 => fine_adj_state_r(2),
      I1 => fine_adj_state_r(1),
      I2 => fine_adj_state_r(3),
      O => \dec_cnt[5]_i_3_n_0\
    );
\dec_cnt[5]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"880F880088008800"
    )
        port map (
      I0 => \FSM_sequential_fine_adj_state_r[0]_i_5_n_0\,
      I1 => \dec_cnt[5]_i_10_n_0\,
      I2 => \FSM_sequential_fine_adj_state_r[1]_i_14_n_0\,
      I3 => fine_adj_state_r(0),
      I4 => p_1_in30_in,
      I5 => detect_pi_found_dqs,
      O => \dec_cnt[5]_i_4_n_0\
    );
\dec_cnt[5]_i_5\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => first_fail_detect_reg_n_0,
      I1 => \FSM_sequential_fine_adj_state_r[1]_i_14_n_0\,
      O => \dec_cnt[5]_i_5_n_0\
    );
\dec_cnt[5]_i_6\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"000E"
    )
        port map (
      I0 => \FSM_sequential_fine_adj_state_r[1]_i_9_n_0\,
      I1 => \inc_cnt_reg_n_0_[5]\,
      I2 => \first_fail_taps[5]_i_3_n_0\,
      I3 => first_fail_detect_reg_n_0,
      O => \dec_cnt[5]_i_6_n_0\
    );
\dec_cnt[5]_i_7\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FBBBBBBB"
    )
        port map (
      I0 => fine_adj_state_r(0),
      I1 => detect_pi_found_dqs,
      I2 => pi_dqs_found_all_bank(2),
      I3 => pi_dqs_found_all_bank(1),
      I4 => pi_dqs_found_all_bank(0),
      O => \dec_cnt[5]_i_7_n_0\
    );
\dec_cnt[5]_i_8\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"88888888B8B888BB"
    )
        port map (
      I0 => \dec_cnt[5]_i_11_n_0\,
      I1 => \FSM_sequential_fine_adj_state_r[1]_i_5_n_0\,
      I2 => \inc_cnt_reg_n_0_[0]\,
      I3 => first_fail_detect_reg_n_0,
      I4 => \first_fail_taps[5]_i_3_n_0\,
      I5 => \dec_cnt[5]_i_12_n_0\,
      O => \dec_cnt[5]_i_8_n_0\
    );
\dec_cnt[5]_i_9\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAAAAAAAAAA9"
    )
        port map (
      I0 => \dec_cnt_reg_n_0_[5]\,
      I1 => \dec_cnt_reg_n_0_[3]\,
      I2 => \dec_cnt_reg_n_0_[0]\,
      I3 => \dec_cnt_reg_n_0_[1]\,
      I4 => \dec_cnt_reg_n_0_[2]\,
      I5 => \dec_cnt_reg_n_0_[4]\,
      O => \dec_cnt[5]_i_9_n_0\
    );
\dec_cnt_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => init_dqsfound_done_r5_reg_0,
      CE => \dec_cnt[5]_i_1_n_0\,
      D => dec_cnt(0),
      Q => \dec_cnt_reg_n_0_[0]\,
      R => \pi_dqs_found_any_bank_reg[0]_0\(1)
    );
\dec_cnt_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => init_dqsfound_done_r5_reg_0,
      CE => \dec_cnt[5]_i_1_n_0\,
      D => dec_cnt(1),
      Q => \dec_cnt_reg_n_0_[1]\,
      R => \pi_dqs_found_any_bank_reg[0]_0\(1)
    );
\dec_cnt_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => init_dqsfound_done_r5_reg_0,
      CE => \dec_cnt[5]_i_1_n_0\,
      D => dec_cnt(2),
      Q => \dec_cnt_reg_n_0_[2]\,
      R => \pi_dqs_found_any_bank_reg[0]_0\(1)
    );
\dec_cnt_reg[2]_i_2\: unisim.vcomponents.CARRY4
     port map (
      CI => '0',
      CO(3) => \dec_cnt_reg[2]_i_2_n_0\,
      CO(2) => \dec_cnt_reg[2]_i_2_n_1\,
      CO(1) => \dec_cnt_reg[2]_i_2_n_2\,
      CO(0) => \dec_cnt_reg[2]_i_2_n_3\,
      CYINIT => '1',
      DI(3) => \inc_cnt_reg_n_0_[3]\,
      DI(2) => \inc_cnt_reg_n_0_[2]\,
      DI(1) => \inc_cnt_reg_n_0_[1]\,
      DI(0) => \inc_cnt_reg_n_0_[0]\,
      O(3) => \dec_cnt_reg[2]_i_2_n_4\,
      O(2) => \dec_cnt_reg[2]_i_2_n_5\,
      O(1) => \dec_cnt_reg[2]_i_2_n_6\,
      O(0) => \NLW_dec_cnt_reg[2]_i_2_O_UNCONNECTED\(0),
      S(3) => \dec_cnt[2]_i_5_n_0\,
      S(2) => \dec_cnt[2]_i_6_n_0\,
      S(1) => \dec_cnt[2]_i_7_n_0\,
      S(0) => \dec_cnt[2]_i_8_n_0\
    );
\dec_cnt_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => init_dqsfound_done_r5_reg_0,
      CE => \dec_cnt[5]_i_1_n_0\,
      D => dec_cnt(3),
      Q => \dec_cnt_reg_n_0_[3]\,
      R => \pi_dqs_found_any_bank_reg[0]_0\(1)
    );
\dec_cnt_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => init_dqsfound_done_r5_reg_0,
      CE => \dec_cnt[5]_i_1_n_0\,
      D => dec_cnt(4),
      Q => \dec_cnt_reg_n_0_[4]\,
      R => \pi_dqs_found_any_bank_reg[0]_0\(1)
    );
\dec_cnt_reg[4]_i_4\: unisim.vcomponents.CARRY4
     port map (
      CI => \dec_cnt_reg[2]_i_2_n_0\,
      CO(3 downto 1) => \NLW_dec_cnt_reg[4]_i_4_CO_UNCONNECTED\(3 downto 1),
      CO(0) => \dec_cnt_reg[4]_i_4_n_3\,
      CYINIT => '0',
      DI(3 downto 1) => B"000",
      DI(0) => \inc_cnt_reg_n_0_[4]\,
      O(3 downto 2) => \NLW_dec_cnt_reg[4]_i_4_O_UNCONNECTED\(3 downto 2),
      O(1) => \dec_cnt_reg[4]_i_4_n_6\,
      O(0) => \dec_cnt_reg[4]_i_4_n_7\,
      S(3 downto 2) => B"00",
      S(1) => \dec_cnt[4]_i_6_n_0\,
      S(0) => \dec_cnt[4]_i_7_n_0\
    );
\dec_cnt_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => init_dqsfound_done_r5_reg_0,
      CE => \dec_cnt[5]_i_1_n_0\,
      D => dec_cnt(5),
      Q => \dec_cnt_reg_n_0_[5]\,
      R => \pi_dqs_found_any_bank_reg[0]_0\(1)
    );
\dec_cnt_reg[5]_i_2\: unisim.vcomponents.MUXF7
     port map (
      I0 => \dec_cnt[5]_i_8_n_0\,
      I1 => \dec_cnt[5]_i_9_n_0\,
      O => dec_cnt(5),
      S => fine_adj_state_r(0)
    );
\detect_rd_cnt[0]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => detect_rd_cnt_reg(0),
      O => \detect_rd_cnt0__0\(0)
    );
\detect_rd_cnt[1]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => detect_rd_cnt_reg(0),
      I1 => detect_rd_cnt_reg(1),
      O => \detect_rd_cnt[1]_i_1_n_0\
    );
\detect_rd_cnt[2]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"A9"
    )
        port map (
      I0 => detect_rd_cnt_reg(2),
      I1 => detect_rd_cnt_reg(1),
      I2 => detect_rd_cnt_reg(0),
      O => \detect_rd_cnt0__0\(2)
    );
\detect_rd_cnt[3]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AAAAAAAB"
    )
        port map (
      I0 => init_dqsfound_done_r_reg_0,
      I1 => detect_rd_cnt_reg(3),
      I2 => detect_rd_cnt_reg(1),
      I3 => detect_rd_cnt_reg(0),
      I4 => detect_rd_cnt_reg(2),
      O => \detect_rd_cnt[3]_i_1_n_0\
    );
\detect_rd_cnt[3]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AAAAAAA8"
    )
        port map (
      I0 => detect_pi_found_dqs,
      I1 => detect_rd_cnt_reg(3),
      I2 => detect_rd_cnt_reg(1),
      I3 => detect_rd_cnt_reg(0),
      I4 => detect_rd_cnt_reg(2),
      O => detect_rd_cnt0
    );
\detect_rd_cnt[3]_i_3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"AAA9"
    )
        port map (
      I0 => detect_rd_cnt_reg(3),
      I1 => detect_rd_cnt_reg(2),
      I2 => detect_rd_cnt_reg(0),
      I3 => detect_rd_cnt_reg(1),
      O => \detect_rd_cnt0__0\(3)
    );
\detect_rd_cnt_reg[0]\: unisim.vcomponents.FDSE
     port map (
      C => init_dqsfound_done_r5_reg_0,
      CE => detect_rd_cnt0,
      D => \detect_rd_cnt0__0\(0),
      Q => detect_rd_cnt_reg(0),
      S => \detect_rd_cnt[3]_i_1_n_0\
    );
\detect_rd_cnt_reg[1]\: unisim.vcomponents.FDSE
     port map (
      C => init_dqsfound_done_r5_reg_0,
      CE => detect_rd_cnt0,
      D => \detect_rd_cnt[1]_i_1_n_0\,
      Q => detect_rd_cnt_reg(1),
      S => \detect_rd_cnt[3]_i_1_n_0\
    );
\detect_rd_cnt_reg[2]\: unisim.vcomponents.FDSE
     port map (
      C => init_dqsfound_done_r5_reg_0,
      CE => detect_rd_cnt0,
      D => \detect_rd_cnt0__0\(2),
      Q => detect_rd_cnt_reg(2),
      S => \detect_rd_cnt[3]_i_1_n_0\
    );
\detect_rd_cnt_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => init_dqsfound_done_r5_reg_0,
      CE => detect_rd_cnt0,
      D => \detect_rd_cnt0__0\(3),
      Q => detect_rd_cnt_reg(3),
      R => \detect_rd_cnt[3]_i_1_n_0\
    );
dqs_found_done_r_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000800000000000"
    )
        port map (
      I0 => p_1_in30_in,
      I1 => \rd_byte_data_offset_reg[0]_46\,
      I2 => dqs_found_done_r_i_4_n_0,
      I3 => fine_adj_state_r(1),
      I4 => fine_adj_state_r(0),
      I5 => init_dqsfound_done_r1_reg_n_0,
      O => dqs_found_done_r0
    );
dqs_found_done_r_i_2: unisim.vcomponents.LUT3
    generic map(
      INIT => X"80"
    )
        port map (
      I0 => pi_dqs_found_all_bank(2),
      I1 => pi_dqs_found_all_bank(1),
      I2 => pi_dqs_found_all_bank(0),
      O => p_1_in30_in
    );
dqs_found_done_r_i_3: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \rnk_cnt_r_reg_n_0_[0]\,
      I1 => \rnk_cnt_r_reg_n_0_[1]\,
      O => \rd_byte_data_offset_reg[0]_46\
    );
dqs_found_done_r_i_4: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => fine_adj_state_r(3),
      I1 => fine_adj_state_r(2),
      O => dqs_found_done_r_i_4_n_0
    );
dqs_found_done_r_reg: unisim.vcomponents.FDRE
     port map (
      C => init_dqsfound_done_r5_reg_0,
      CE => '1',
      D => dqs_found_done_r0,
      Q => \^dqs_found_done_r_reg_0\,
      R => \pi_dqs_found_any_bank_reg[0]_0\(0)
    );
dqs_found_prech_req_i_1: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFBF0080"
    )
        port map (
      I0 => dqs_found_prech_req_i_2_n_0,
      I1 => fine_adj_state_r(1),
      I2 => fine_adj_state_r(3),
      I3 => dqs_found_prech_req_i_3_n_0,
      I4 => \^dqs_found_prech_req\,
      O => dqs_found_prech_req_i_1_n_0
    );
dqs_found_prech_req_i_2: unisim.vcomponents.LUT5
    generic map(
      INIT => X"54545044"
    )
        port map (
      I0 => fine_adj_state_r(2),
      I1 => \FSM_sequential_fine_adj_state_r[1]_i_10_n_0\,
      I2 => \FSM_sequential_fine_adj_state_r[1]_i_12_n_0\,
      I3 => \FSM_sequential_fine_adj_state_r[1]_i_13_n_0\,
      I4 => \FSM_sequential_fine_adj_state_r[1]_i_5_n_0\,
      O => dqs_found_prech_req_i_2_n_0
    );
dqs_found_prech_req_i_3: unisim.vcomponents.LUT6
    generic map(
      INIT => X"5555FFFFFFFF00FC"
    )
        port map (
      I0 => prech_done,
      I1 => dqs_found_prech_req_i_4_n_0,
      I2 => \FSM_sequential_fine_adj_state_r[2]_i_3_n_0\,
      I3 => \FSM_sequential_fine_adj_state_r[2]_i_4_n_0\,
      I4 => fine_adj_state_r(0),
      I5 => fine_adj_state_r(2),
      O => dqs_found_prech_req_i_3_n_0
    );
dqs_found_prech_req_i_4: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7FFF"
    )
        port map (
      I0 => detect_pi_found_dqs,
      I1 => pi_dqs_found_all_bank(0),
      I2 => pi_dqs_found_all_bank(1),
      I3 => pi_dqs_found_all_bank(2),
      O => dqs_found_prech_req_i_4_n_0
    );
dqs_found_prech_req_reg: unisim.vcomponents.FDRE
     port map (
      C => init_dqsfound_done_r5_reg_0,
      CE => '1',
      D => dqs_found_prech_req_i_1_n_0,
      Q => \^dqs_found_prech_req\,
      R => \pi_dqs_found_any_bank_reg[0]_0\(0)
    );
dqs_found_start_r_reg: unisim.vcomponents.FDRE
     port map (
      C => init_dqsfound_done_r5_reg_0,
      CE => '1',
      D => dqs_found_start_r_reg_0,
      Q => dqs_found_start_r,
      R => '0'
    );
final_dec_done_i_1: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFF4440"
    )
        port map (
      I0 => \FSM_sequential_fine_adj_state_r[0]_i_2_n_0\,
      I1 => fine_adj_state_r(2),
      I2 => init_dec_done_reg_n_0,
      I3 => \FSM_sequential_fine_adj_state_r[3]_i_4_n_0\,
      I4 => final_dec_done_reg_n_0,
      O => final_dec_done_i_1_n_0
    );
final_dec_done_reg: unisim.vcomponents.FDRE
     port map (
      C => init_dqsfound_done_r5_reg_0,
      CE => '1',
      D => final_dec_done_i_1_n_0,
      Q => final_dec_done_reg_n_0,
      R => \pi_dqs_found_any_bank_reg[0]_0\(1)
    );
fine_adjust_done_r_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFF01000000"
    )
        port map (
      I0 => fine_adj_state_r(2),
      I1 => fine_adj_state_r(3),
      I2 => fine_adj_state_r(0),
      I3 => p_1_in30_in,
      I4 => fine_adj_state_r(1),
      I5 => fine_adjust_done_r_reg_n_0,
      O => fine_adjust_done_r_i_1_n_0
    );
fine_adjust_done_r_reg: unisim.vcomponents.FDRE
     port map (
      C => init_dqsfound_done_r5_reg_0,
      CE => '1',
      D => fine_adjust_done_r_i_1_n_0,
      Q => fine_adjust_done_r_reg_n_0,
      R => \pi_dqs_found_any_bank_reg[0]_0\(1)
    );
fine_adjust_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFF00000004"
    )
        port map (
      I0 => fine_adj_state_r(1),
      I1 => init_dqsfound_done_r5,
      I2 => fine_adj_state_r(2),
      I3 => fine_adj_state_r(3),
      I4 => fine_adj_state_r(0),
      I5 => \^fine_adjust_reg_0\,
      O => fine_adjust_i_1_n_0
    );
fine_adjust_reg: unisim.vcomponents.FDRE
     port map (
      C => init_dqsfound_done_r5_reg_0,
      CE => '1',
      D => fine_adjust_i_1_n_0,
      Q => \^fine_adjust_reg_0\,
      R => \pi_dqs_found_any_bank_reg[0]_0\(1)
    );
first_fail_detect_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00007FFFFFFFFFFF"
    )
        port map (
      I0 => stable_pass_cnt_reg(3),
      I1 => stable_pass_cnt_reg(2),
      I2 => stable_pass_cnt_reg(4),
      I3 => stable_pass_cnt_reg(1),
      I4 => stable_pass_cnt_reg(5),
      I5 => first_fail_detect_reg_n_0,
      O => first_fail_detect_i_1_n_0
    );
first_fail_detect_reg: unisim.vcomponents.FDRE
     port map (
      C => init_dqsfound_done_r5_reg_0,
      CE => first_fail_detect,
      D => first_fail_detect_i_1_n_0,
      Q => first_fail_detect_reg_n_0,
      R => first_fail_detect_reg_0
    );
\first_fail_taps[0]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \first_fail_taps[5]_i_3_n_0\,
      I1 => \first_fail_taps[5]_i_5_n_0\,
      I2 => \inc_cnt_reg_n_0_[0]\,
      O => \first_fail_taps[0]_i_1_n_0\
    );
\first_fail_taps[1]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \first_fail_taps[5]_i_3_n_0\,
      I1 => \first_fail_taps[5]_i_5_n_0\,
      I2 => \inc_cnt_reg_n_0_[1]\,
      O => \first_fail_taps[1]_i_1_n_0\
    );
\first_fail_taps[2]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \first_fail_taps[5]_i_3_n_0\,
      I1 => \first_fail_taps[5]_i_5_n_0\,
      I2 => \inc_cnt_reg_n_0_[2]\,
      O => \first_fail_taps[2]_i_1_n_0\
    );
\first_fail_taps[3]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \first_fail_taps[5]_i_3_n_0\,
      I1 => \first_fail_taps[5]_i_5_n_0\,
      I2 => \inc_cnt_reg_n_0_[3]\,
      O => \first_fail_taps[3]_i_1_n_0\
    );
\first_fail_taps[4]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \first_fail_taps[5]_i_3_n_0\,
      I1 => \first_fail_taps[5]_i_5_n_0\,
      I2 => \inc_cnt_reg_n_0_[4]\,
      O => \first_fail_taps[4]_i_1_n_0\
    );
\first_fail_taps[5]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000D00000000"
    )
        port map (
      I0 => first_fail_detect_reg_n_0,
      I1 => \first_fail_taps[5]_i_3_n_0\,
      I2 => fine_adj_state_r(0),
      I3 => \FSM_sequential_fine_adj_state_r[1]_i_5_n_0\,
      I4 => fine_adj_state_r(2),
      I5 => \first_fail_taps[5]_i_4_n_0\,
      O => first_fail_detect
    );
\first_fail_taps[5]_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \first_fail_taps[5]_i_3_n_0\,
      I1 => \first_fail_taps[5]_i_5_n_0\,
      I2 => \inc_cnt_reg_n_0_[5]\,
      O => \first_fail_taps[5]_i_2_n_0\
    );
\first_fail_taps[5]_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"15555555"
    )
        port map (
      I0 => stable_pass_cnt_reg(5),
      I1 => stable_pass_cnt_reg(1),
      I2 => stable_pass_cnt_reg(4),
      I3 => stable_pass_cnt_reg(2),
      I4 => stable_pass_cnt_reg(3),
      O => \first_fail_taps[5]_i_3_n_0\
    );
\first_fail_taps[5]_i_4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => fine_adj_state_r(3),
      I1 => fine_adj_state_r(1),
      O => \first_fail_taps[5]_i_4_n_0\
    );
\first_fail_taps[5]_i_5\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8A0A"
    )
        port map (
      I0 => first_fail_detect_reg_n_0,
      I1 => \FSM_sequential_fine_adj_state_r[1]_i_9_n_0\,
      I2 => \first_fail_taps[5]_i_3_n_0\,
      I3 => \FSM_sequential_fine_adj_state_r[1]_i_11_n_0\,
      O => \first_fail_taps[5]_i_5_n_0\
    );
\first_fail_taps_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => init_dqsfound_done_r5_reg_0,
      CE => first_fail_detect,
      D => \first_fail_taps[0]_i_1_n_0\,
      Q => \first_fail_taps_reg_n_0_[0]\,
      R => \pi_dqs_found_any_bank_reg[0]_0\(0)
    );
\first_fail_taps_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => init_dqsfound_done_r5_reg_0,
      CE => first_fail_detect,
      D => \first_fail_taps[1]_i_1_n_0\,
      Q => \first_fail_taps_reg_n_0_[1]\,
      R => \pi_dqs_found_any_bank_reg[0]_0\(0)
    );
\first_fail_taps_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => init_dqsfound_done_r5_reg_0,
      CE => first_fail_detect,
      D => \first_fail_taps[2]_i_1_n_0\,
      Q => \first_fail_taps_reg_n_0_[2]\,
      R => \pi_dqs_found_any_bank_reg[0]_0\(0)
    );
\first_fail_taps_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => init_dqsfound_done_r5_reg_0,
      CE => first_fail_detect,
      D => \first_fail_taps[3]_i_1_n_0\,
      Q => \first_fail_taps_reg_n_0_[3]\,
      R => \pi_dqs_found_any_bank_reg[0]_0\(0)
    );
\first_fail_taps_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => init_dqsfound_done_r5_reg_0,
      CE => first_fail_detect,
      D => \first_fail_taps[4]_i_1_n_0\,
      Q => \first_fail_taps_reg_n_0_[4]\,
      R => \pi_dqs_found_any_bank_reg[0]_0\(0)
    );
\first_fail_taps_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => init_dqsfound_done_r5_reg_0,
      CE => first_fail_detect,
      D => \first_fail_taps[5]_i_2_n_0\,
      Q => \first_fail_taps_reg_n_0_[5]\,
      R => \pi_dqs_found_any_bank_reg[0]_0\(0)
    );
\gen_byte_sel_div2.byte_sel_cnt[3]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FBFBFBFBBBFBFBFB"
    )
        port map (
      I0 => \gen_byte_sel_div2.byte_sel_cnt_reg[0]\,
      I1 => cmd_delay_start0,
      I2 => ck_addr_cmd_delay_done,
      I3 => pi_calib_done,
      I4 => \^dqs_found_done_r_reg_0\,
      I5 => byte_sel_cnt1,
      O => SR(0)
    );
\gen_byte_sel_div2.byte_sel_cnt[3]_i_4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => rd_data_offset_cal_done,
      I1 => fine_adjust_done_r_reg_n_0,
      O => byte_sel_cnt1
    );
\gen_byte_sel_div2.calib_in_common_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8FFFFFFF80FFFFFF"
    )
        port map (
      I0 => \gen_byte_sel_div2.calib_in_common_i_2_n_0\,
      I1 => ck_addr_cmd_delay_done,
      I2 => \gen_byte_sel_div2.calib_in_common_i_3_n_0\,
      I3 => pi_fine_dly_dec_done,
      I4 => dqs_po_dec_done,
      I5 => calib_in_common,
      O => delay_done_r4_reg
    );
\gen_byte_sel_div2.calib_in_common_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FBFB08FBFBFBFBFB"
    )
        port map (
      I0 => \^pi_rst_stg1_cal_reg[0]_0\,
      I1 => rd_data_offset_cal_done,
      I2 => fine_adjust_done_r_reg_n_0,
      I3 => \^dqs_found_done_r_reg_0\,
      I4 => calib_in_common4_out,
      I5 => pi_calib_done,
      O => \gen_byte_sel_div2.calib_in_common_i_2_n_0\
    );
\gen_byte_sel_div2.calib_in_common_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"DFDFFFDFFFFFFFFF"
    )
        port map (
      I0 => \^dqs_found_done_r_reg_0\,
      I1 => \gen_byte_sel_div2.calib_in_common_reg\,
      I2 => pi_calib_done,
      I3 => rd_data_offset_cal_done,
      I4 => fine_adjust_done_r_reg_n_0,
      I5 => ck_addr_cmd_delay_done,
      O => \gen_byte_sel_div2.calib_in_common_i_3_n_0\
    );
\gen_byte_sel_div2.ctl_lane_sel[0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"2F20FFFF2F200000"
    )
        port map (
      I0 => fine_adjust_lane_cnt(0),
      I1 => \^pi_rst_stg1_cal_reg[0]_0\,
      I2 => ck_addr_cmd_delay_done,
      I3 => ctl_lane_cnt(0),
      I4 => \^ctl_lane_sel\,
      I5 => \gen_byte_sel_div2.ctl_lane_sel_reg[0]\,
      O => \ctl_lane_cnt_reg[0]_0\
    );
\gen_byte_sel_div2.ctl_lane_sel[1]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"2F20FFFF2F200000"
    )
        port map (
      I0 => fine_adjust_lane_cnt(1),
      I1 => \^pi_rst_stg1_cal_reg[0]_0\,
      I2 => ck_addr_cmd_delay_done,
      I3 => ctl_lane_cnt(1),
      I4 => \^ctl_lane_sel\,
      I5 => \gen_byte_sel_div2.ctl_lane_sel_reg[1]\,
      O => \ctl_lane_cnt_reg[1]_0\
    );
\gen_byte_sel_div2.ctl_lane_sel[2]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"2F20FFFF2F200000"
    )
        port map (
      I0 => fine_adjust_lane_cnt(2),
      I1 => \^pi_rst_stg1_cal_reg[0]_0\,
      I2 => ck_addr_cmd_delay_done,
      I3 => ctl_lane_cnt(2),
      I4 => \^ctl_lane_sel\,
      I5 => \gen_byte_sel_div2.ctl_lane_sel_reg[2]_1\,
      O => \ctl_lane_cnt_reg[2]_0\
    );
\gen_byte_sel_div2.ctl_lane_sel[2]_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"FE"
    )
        port map (
      I0 => \^pi_rst_stg1_cal_reg[2]_0\(0),
      I1 => \^pi_rst_stg1_cal_reg[2]_0\(2),
      I2 => \^pi_rst_stg1_cal_reg[2]_0\(1),
      O => \^pi_rst_stg1_cal_reg[0]_0\
    );
\gen_no_mirror.div_clk_loop[0].phy_address[10]_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"80"
    )
        port map (
      I0 => \^dqs_found_done_r_reg_0\,
      I1 => \gen_no_mirror.div_clk_loop[0].phy_address_reg[10]\,
      I2 => \gen_no_mirror.div_clk_loop[0].phy_address_reg[10]_0\,
      O => dqs_found_done_r_reg_1
    );
i_0: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '1',
      O => n_0_0
    );
i_1: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '1',
      O => n_0_1
    );
i_2: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '1',
      O => n_0_2
    );
i_3: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '1',
      O => n_0_3
    );
\inc_cnt[0]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \inc_cnt_reg_n_0_[0]\,
      O => p_0_in(0)
    );
\inc_cnt[1]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \inc_cnt_reg_n_0_[0]\,
      I1 => \inc_cnt_reg_n_0_[1]\,
      O => p_0_in(1)
    );
\inc_cnt[2]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"6A"
    )
        port map (
      I0 => \inc_cnt_reg_n_0_[2]\,
      I1 => \inc_cnt_reg_n_0_[1]\,
      I2 => \inc_cnt_reg_n_0_[0]\,
      O => p_0_in(2)
    );
\inc_cnt[3]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6AAA"
    )
        port map (
      I0 => \inc_cnt_reg_n_0_[3]\,
      I1 => \inc_cnt_reg_n_0_[2]\,
      I2 => \inc_cnt_reg_n_0_[0]\,
      I3 => \inc_cnt_reg_n_0_[1]\,
      O => p_0_in(3)
    );
\inc_cnt[4]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"6AAAAAAA"
    )
        port map (
      I0 => \inc_cnt_reg_n_0_[4]\,
      I1 => \inc_cnt_reg_n_0_[3]\,
      I2 => \inc_cnt_reg_n_0_[1]\,
      I3 => \inc_cnt_reg_n_0_[0]\,
      I4 => \inc_cnt_reg_n_0_[2]\,
      O => p_0_in(4)
    );
\inc_cnt[5]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000000400"
    )
        port map (
      I0 => fine_adjust_lane_cnt(0),
      I1 => fine_adjust_lane_cnt(1),
      I2 => fine_adjust_lane_cnt(2),
      I3 => fine_adj_state_r(2),
      I4 => \inc_cnt[5]_i_3_n_0\,
      I5 => fine_adj_state_r(3),
      O => inc_cnt
    );
\inc_cnt[5]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"6AAAAAAAAAAAAAAA"
    )
        port map (
      I0 => \inc_cnt_reg_n_0_[5]\,
      I1 => \inc_cnt_reg_n_0_[3]\,
      I2 => \inc_cnt_reg_n_0_[1]\,
      I3 => \inc_cnt_reg_n_0_[4]\,
      I4 => \inc_cnt_reg_n_0_[2]\,
      I5 => \inc_cnt_reg_n_0_[0]\,
      O => p_0_in(5)
    );
\inc_cnt[5]_i_3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => fine_adj_state_r(0),
      I1 => fine_adj_state_r(1),
      O => \inc_cnt[5]_i_3_n_0\
    );
\inc_cnt_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => init_dqsfound_done_r5_reg_0,
      CE => inc_cnt,
      D => p_0_in(0),
      Q => \inc_cnt_reg_n_0_[0]\,
      R => \stable_pass_cnt_reg[0]_0\
    );
\inc_cnt_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => init_dqsfound_done_r5_reg_0,
      CE => inc_cnt,
      D => p_0_in(1),
      Q => \inc_cnt_reg_n_0_[1]\,
      R => \stable_pass_cnt_reg[0]_0\
    );
\inc_cnt_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => init_dqsfound_done_r5_reg_0,
      CE => inc_cnt,
      D => p_0_in(2),
      Q => \inc_cnt_reg_n_0_[2]\,
      R => \stable_pass_cnt_reg[0]_0\
    );
\inc_cnt_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => init_dqsfound_done_r5_reg_0,
      CE => inc_cnt,
      D => p_0_in(3),
      Q => \inc_cnt_reg_n_0_[3]\,
      R => \stable_pass_cnt_reg[0]_0\
    );
\inc_cnt_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => init_dqsfound_done_r5_reg_0,
      CE => inc_cnt,
      D => p_0_in(4),
      Q => \inc_cnt_reg_n_0_[4]\,
      R => \stable_pass_cnt_reg[0]_0\
    );
\inc_cnt_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => init_dqsfound_done_r5_reg_0,
      CE => inc_cnt,
      D => p_0_in(5),
      Q => \inc_cnt_reg_n_0_[5]\,
      R => \stable_pass_cnt_reg[0]_0\
    );
\init_dec_cnt[0]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => init_dec_cnt_reg(0),
      O => init_dec_cnt0(0)
    );
\init_dec_cnt[1]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => init_dec_cnt_reg(0),
      I1 => init_dec_cnt_reg(1),
      O => \init_dec_cnt[1]_i_1_n_0\
    );
\init_dec_cnt[2]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"E1"
    )
        port map (
      I0 => init_dec_cnt_reg(0),
      I1 => init_dec_cnt_reg(1),
      I2 => init_dec_cnt_reg(2),
      O => init_dec_cnt0(2)
    );
\init_dec_cnt[3]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FE01"
    )
        port map (
      I0 => init_dec_cnt_reg(2),
      I1 => init_dec_cnt_reg(1),
      I2 => init_dec_cnt_reg(0),
      I3 => init_dec_cnt_reg(3),
      O => init_dec_cnt0(3)
    );
\init_dec_cnt[4]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFE0001"
    )
        port map (
      I0 => init_dec_cnt_reg(3),
      I1 => init_dec_cnt_reg(0),
      I2 => init_dec_cnt_reg(1),
      I3 => init_dec_cnt_reg(2),
      I4 => init_dec_cnt_reg(4),
      O => init_dec_cnt0(4)
    );
\init_dec_cnt[5]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000008000"
    )
        port map (
      I0 => \FSM_sequential_fine_adj_state_r[3]_i_4_n_0\,
      I1 => fine_adj_state_r(0),
      I2 => fine_adj_state_r(3),
      I3 => fine_adj_state_r(1),
      I4 => fine_adj_state_r(2),
      I5 => \init_dec_cnt[5]_i_3_n_0\,
      O => init_dec_cnt
    );
\init_dec_cnt[5]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFE00000001"
    )
        port map (
      I0 => init_dec_cnt_reg(4),
      I1 => init_dec_cnt_reg(2),
      I2 => init_dec_cnt_reg(1),
      I3 => init_dec_cnt_reg(0),
      I4 => init_dec_cnt_reg(3),
      I5 => init_dec_cnt_reg(5),
      O => init_dec_cnt0(5)
    );
\init_dec_cnt[5]_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"FB"
    )
        port map (
      I0 => fine_adjust_lane_cnt(0),
      I1 => fine_adjust_lane_cnt(1),
      I2 => fine_adjust_lane_cnt(2),
      O => \init_dec_cnt[5]_i_3_n_0\
    );
\init_dec_cnt_reg[0]\: unisim.vcomponents.FDSE
     port map (
      C => init_dqsfound_done_r5_reg_0,
      CE => init_dec_cnt,
      D => init_dec_cnt0(0),
      Q => init_dec_cnt_reg(0),
      S => \init_dec_cnt_reg[4]_0\(0)
    );
\init_dec_cnt_reg[1]\: unisim.vcomponents.FDSE
     port map (
      C => init_dqsfound_done_r5_reg_0,
      CE => init_dec_cnt,
      D => \init_dec_cnt[1]_i_1_n_0\,
      Q => init_dec_cnt_reg(1),
      S => \init_dec_cnt_reg[4]_0\(0)
    );
\init_dec_cnt_reg[2]\: unisim.vcomponents.FDSE
     port map (
      C => init_dqsfound_done_r5_reg_0,
      CE => init_dec_cnt,
      D => init_dec_cnt0(2),
      Q => init_dec_cnt_reg(2),
      S => \init_dec_cnt_reg[4]_0\(0)
    );
\init_dec_cnt_reg[3]\: unisim.vcomponents.FDSE
     port map (
      C => init_dqsfound_done_r5_reg_0,
      CE => init_dec_cnt,
      D => init_dec_cnt0(3),
      Q => init_dec_cnt_reg(3),
      S => \init_dec_cnt_reg[4]_0\(0)
    );
\init_dec_cnt_reg[4]\: unisim.vcomponents.FDSE
     port map (
      C => init_dqsfound_done_r5_reg_0,
      CE => init_dec_cnt,
      D => init_dec_cnt0(4),
      Q => init_dec_cnt_reg(4),
      S => \init_dec_cnt_reg[4]_0\(0)
    );
\init_dec_cnt_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => init_dqsfound_done_r5_reg_0,
      CE => init_dec_cnt,
      D => init_dec_cnt0(5),
      Q => init_dec_cnt_reg(5),
      R => \init_dec_cnt_reg[4]_0\(0)
    );
init_dec_done_i_1: unisim.vcomponents.LUT4
    generic map(
      INIT => X"CCDC"
    )
        port map (
      I0 => \FSM_sequential_fine_adj_state_r[3]_i_4_n_0\,
      I1 => init_dec_done_reg_n_0,
      I2 => fine_adj_state_r(2),
      I3 => \FSM_sequential_fine_adj_state_r[0]_i_2_n_0\,
      O => init_dec_done_i_1_n_0
    );
init_dec_done_reg: unisim.vcomponents.FDRE
     port map (
      C => init_dqsfound_done_r5_reg_0,
      CE => '1',
      D => init_dec_done_i_1_n_0,
      Q => init_dec_done_reg_n_0,
      R => \pi_dqs_found_any_bank_reg[0]_0\(1)
    );
init_dqsfound_done_r1_reg: unisim.vcomponents.FDRE
     port map (
      C => init_dqsfound_done_r5_reg_0,
      CE => '1',
      D => rd_data_offset_cal_done,
      Q => init_dqsfound_done_r1_reg_n_0,
      R => '0'
    );
init_dqsfound_done_r2_reg: unisim.vcomponents.FDRE
     port map (
      C => init_dqsfound_done_r5_reg_0,
      CE => '1',
      D => init_dqsfound_done_r1_reg_n_0,
      Q => \^init_dqsfound_done_r2\,
      R => '0'
    );
init_dqsfound_done_r4_reg_srl2: unisim.vcomponents.SRL16E
     port map (
      A0 => '1',
      A1 => '0',
      A2 => '0',
      A3 => '0',
      CE => '1',
      CLK => init_dqsfound_done_r5_reg_0,
      D => \^init_dqsfound_done_r2\,
      Q => init_dqsfound_done_r4_reg_srl2_n_0
    );
init_dqsfound_done_r5_reg: unisim.vcomponents.FDRE
     port map (
      C => init_dqsfound_done_r5_reg_0,
      CE => '1',
      D => init_dqsfound_done_r4_reg_srl2_n_0,
      Q => init_dqsfound_done_r5,
      R => '0'
    );
init_dqsfound_done_r_i_1: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000100"
    )
        port map (
      I0 => \pi_rst_stg1_cal_r_reg_n_0_[0]\,
      I1 => init_dqsfound_done_r_reg_0,
      I2 => \pi_rst_stg1_cal_r_reg_n_0_[1]\,
      I3 => init_dqsfound_done_r_i_2_n_0,
      I4 => \pi_rst_stg1_cal_r_reg_n_0_[2]\,
      O => init_dqsfound_done_r_i_1_n_0
    );
init_dqsfound_done_r_i_2: unisim.vcomponents.LUT6
    generic map(
      INIT => X"1FFFFFFF10000000"
    )
        port map (
      I0 => \rnk_cnt_r_reg_n_0_[0]\,
      I1 => \rnk_cnt_r_reg_n_0_[1]\,
      I2 => pi_dqs_found_all_bank(2),
      I3 => pi_dqs_found_all_bank(1),
      I4 => pi_dqs_found_all_bank(0),
      I5 => rd_data_offset_cal_done,
      O => init_dqsfound_done_r_i_2_n_0
    );
init_dqsfound_done_r_reg: unisim.vcomponents.FDRE
     port map (
      C => init_dqsfound_done_r5_reg_0,
      CE => '1',
      D => init_dqsfound_done_r_i_1_n_0,
      Q => rd_data_offset_cal_done,
      R => '0'
    );
\init_state_r[0]_i_24\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"FE"
    )
        port map (
      I0 => \^pi_dqs_found_rank_done\,
      I1 => \init_state_r[0]_i_10\,
      I2 => \^dqs_found_done_r_reg_0\,
      O => rank_done_r_reg_0
    );
\init_state_r[2]_i_28\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"7"
    )
        port map (
      I0 => \^dqs_found_done_r_reg_0\,
      I1 => \init_state_r[2]_i_10\,
      O => dqs_found_done_r_reg_2
    );
\pi_dqs_found_all_bank[0]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8000"
    )
        port map (
      I0 => pi_dqs_found_lanes_r3(0),
      I1 => pi_dqs_found_lanes_r3(1),
      I2 => pi_dqs_found_lanes_r3(2),
      I3 => pi_dqs_found_lanes_r3(3),
      O => p_8_out(0)
    );
\pi_dqs_found_all_bank[2]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8000"
    )
        port map (
      I0 => pi_dqs_found_lanes_r3(8),
      I1 => pi_dqs_found_lanes_r3(9),
      I2 => pi_dqs_found_lanes_r3(10),
      I3 => pi_dqs_found_lanes_r3(11),
      O => p_8_out(2)
    );
\pi_dqs_found_all_bank_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => init_dqsfound_done_r5_reg_0,
      CE => '1',
      D => pi_dqs_found_all_bank(0),
      Q => pi_dqs_found_all_bank_r(0),
      R => '0'
    );
\pi_dqs_found_all_bank_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => init_dqsfound_done_r5_reg_0,
      CE => '1',
      D => pi_dqs_found_all_bank(1),
      Q => pi_dqs_found_all_bank_r(1),
      R => '0'
    );
\pi_dqs_found_all_bank_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => init_dqsfound_done_r5_reg_0,
      CE => '1',
      D => pi_dqs_found_all_bank(2),
      Q => pi_dqs_found_all_bank_r(2),
      R => '0'
    );
\pi_dqs_found_all_bank_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => init_dqsfound_done_r5_reg_0,
      CE => dqs_found_start_r_reg_0,
      D => p_8_out(0),
      Q => pi_dqs_found_all_bank(0),
      R => \pi_dqs_found_any_bank_reg[0]_0\(1)
    );
\pi_dqs_found_all_bank_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => init_dqsfound_done_r5_reg_0,
      CE => dqs_found_start_r_reg_0,
      D => dqs_found_start_r_reg_0,
      Q => pi_dqs_found_all_bank(1),
      R => \pi_dqs_found_any_bank_reg[0]_0\(1)
    );
\pi_dqs_found_all_bank_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => init_dqsfound_done_r5_reg_0,
      CE => dqs_found_start_r_reg_0,
      D => p_8_out(2),
      Q => pi_dqs_found_all_bank(2),
      R => \pi_dqs_found_any_bank_reg[0]_0\(1)
    );
\pi_dqs_found_any_bank[0]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFFE"
    )
        port map (
      I0 => pi_dqs_found_lanes_r3(0),
      I1 => pi_dqs_found_lanes_r3(1),
      I2 => pi_dqs_found_lanes_r3(3),
      I3 => pi_dqs_found_lanes_r3(2),
      O => \pi_dqs_found_any_bank[0]_i_1_n_0\
    );
\pi_dqs_found_any_bank[2]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFFE"
    )
        port map (
      I0 => pi_dqs_found_lanes_r3(8),
      I1 => pi_dqs_found_lanes_r3(11),
      I2 => pi_dqs_found_lanes_r3(9),
      I3 => pi_dqs_found_lanes_r3(10),
      O => \pi_dqs_found_any_bank[2]_i_1_n_0\
    );
\pi_dqs_found_any_bank_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => init_dqsfound_done_r5_reg_0,
      CE => '1',
      D => pi_dqs_found_any_bank(0),
      Q => \pi_dqs_found_any_bank_r_reg_n_0_[0]\,
      R => '0'
    );
\pi_dqs_found_any_bank_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => init_dqsfound_done_r5_reg_0,
      CE => '1',
      D => pi_dqs_found_any_bank(2),
      Q => p_0_in62_in,
      R => '0'
    );
\pi_dqs_found_any_bank_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => init_dqsfound_done_r5_reg_0,
      CE => dqs_found_start_r_reg_0,
      D => \pi_dqs_found_any_bank[0]_i_1_n_0\,
      Q => pi_dqs_found_any_bank(0),
      R => \pi_dqs_found_any_bank_reg[0]_0\(1)
    );
\pi_dqs_found_any_bank_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => init_dqsfound_done_r5_reg_0,
      CE => dqs_found_start_r_reg_0,
      D => \pi_dqs_found_any_bank[2]_i_1_n_0\,
      Q => pi_dqs_found_any_bank(2),
      R => \pi_dqs_found_any_bank_reg[0]_0\(1)
    );
\pi_dqs_found_lanes_r1_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => init_dqsfound_done_r5_reg_0,
      CE => '1',
      D => in0(0),
      Q => pi_dqs_found_lanes_r1(0),
      R => '0'
    );
\pi_dqs_found_lanes_r1_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => init_dqsfound_done_r5_reg_0,
      CE => '1',
      D => in0(6),
      Q => pi_dqs_found_lanes_r1(10),
      R => '0'
    );
\pi_dqs_found_lanes_r1_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => init_dqsfound_done_r5_reg_0,
      CE => '1',
      D => in0(7),
      Q => pi_dqs_found_lanes_r1(11),
      R => '0'
    );
\pi_dqs_found_lanes_r1_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => init_dqsfound_done_r5_reg_0,
      CE => '1',
      D => in0(1),
      Q => pi_dqs_found_lanes_r1(1),
      R => '0'
    );
\pi_dqs_found_lanes_r1_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => init_dqsfound_done_r5_reg_0,
      CE => '1',
      D => in0(2),
      Q => pi_dqs_found_lanes_r1(2),
      R => '0'
    );
\pi_dqs_found_lanes_r1_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => init_dqsfound_done_r5_reg_0,
      CE => '1',
      D => in0(3),
      Q => pi_dqs_found_lanes_r1(3),
      R => '0'
    );
\pi_dqs_found_lanes_r1_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => init_dqsfound_done_r5_reg_0,
      CE => '1',
      D => n_0_3,
      Q => pi_dqs_found_lanes_r1(4),
      R => '0'
    );
\pi_dqs_found_lanes_r1_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => init_dqsfound_done_r5_reg_0,
      CE => '1',
      D => n_0_2,
      Q => pi_dqs_found_lanes_r1(5),
      R => '0'
    );
\pi_dqs_found_lanes_r1_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => init_dqsfound_done_r5_reg_0,
      CE => '1',
      D => n_0_1,
      Q => pi_dqs_found_lanes_r1(6),
      R => '0'
    );
\pi_dqs_found_lanes_r1_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => init_dqsfound_done_r5_reg_0,
      CE => '1',
      D => n_0_0,
      Q => pi_dqs_found_lanes_r1(7),
      R => '0'
    );
\pi_dqs_found_lanes_r1_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => init_dqsfound_done_r5_reg_0,
      CE => '1',
      D => in0(4),
      Q => pi_dqs_found_lanes_r1(8),
      R => '0'
    );
\pi_dqs_found_lanes_r1_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => init_dqsfound_done_r5_reg_0,
      CE => '1',
      D => in0(5),
      Q => pi_dqs_found_lanes_r1(9),
      R => '0'
    );
\pi_dqs_found_lanes_r2_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => init_dqsfound_done_r5_reg_0,
      CE => '1',
      D => pi_dqs_found_lanes_r1(0),
      Q => pi_dqs_found_lanes_r2(0),
      R => '0'
    );
\pi_dqs_found_lanes_r2_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => init_dqsfound_done_r5_reg_0,
      CE => '1',
      D => pi_dqs_found_lanes_r1(10),
      Q => pi_dqs_found_lanes_r2(10),
      R => '0'
    );
\pi_dqs_found_lanes_r2_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => init_dqsfound_done_r5_reg_0,
      CE => '1',
      D => pi_dqs_found_lanes_r1(11),
      Q => pi_dqs_found_lanes_r2(11),
      R => '0'
    );
\pi_dqs_found_lanes_r2_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => init_dqsfound_done_r5_reg_0,
      CE => '1',
      D => pi_dqs_found_lanes_r1(1),
      Q => pi_dqs_found_lanes_r2(1),
      R => '0'
    );
\pi_dqs_found_lanes_r2_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => init_dqsfound_done_r5_reg_0,
      CE => '1',
      D => pi_dqs_found_lanes_r1(2),
      Q => pi_dqs_found_lanes_r2(2),
      R => '0'
    );
\pi_dqs_found_lanes_r2_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => init_dqsfound_done_r5_reg_0,
      CE => '1',
      D => pi_dqs_found_lanes_r1(3),
      Q => pi_dqs_found_lanes_r2(3),
      R => '0'
    );
\pi_dqs_found_lanes_r2_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => init_dqsfound_done_r5_reg_0,
      CE => '1',
      D => pi_dqs_found_lanes_r1(4),
      Q => pi_dqs_found_lanes_r2(4),
      R => '0'
    );
\pi_dqs_found_lanes_r2_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => init_dqsfound_done_r5_reg_0,
      CE => '1',
      D => pi_dqs_found_lanes_r1(5),
      Q => pi_dqs_found_lanes_r2(5),
      R => '0'
    );
\pi_dqs_found_lanes_r2_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => init_dqsfound_done_r5_reg_0,
      CE => '1',
      D => pi_dqs_found_lanes_r1(6),
      Q => pi_dqs_found_lanes_r2(6),
      R => '0'
    );
\pi_dqs_found_lanes_r2_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => init_dqsfound_done_r5_reg_0,
      CE => '1',
      D => pi_dqs_found_lanes_r1(7),
      Q => pi_dqs_found_lanes_r2(7),
      R => '0'
    );
\pi_dqs_found_lanes_r2_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => init_dqsfound_done_r5_reg_0,
      CE => '1',
      D => pi_dqs_found_lanes_r1(8),
      Q => pi_dqs_found_lanes_r2(8),
      R => '0'
    );
\pi_dqs_found_lanes_r2_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => init_dqsfound_done_r5_reg_0,
      CE => '1',
      D => pi_dqs_found_lanes_r1(9),
      Q => pi_dqs_found_lanes_r2(9),
      R => '0'
    );
\pi_dqs_found_lanes_r3_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => init_dqsfound_done_r5_reg_0,
      CE => '1',
      D => pi_dqs_found_lanes_r2(0),
      Q => pi_dqs_found_lanes_r3(0),
      R => '0'
    );
\pi_dqs_found_lanes_r3_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => init_dqsfound_done_r5_reg_0,
      CE => '1',
      D => pi_dqs_found_lanes_r2(10),
      Q => pi_dqs_found_lanes_r3(10),
      R => '0'
    );
\pi_dqs_found_lanes_r3_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => init_dqsfound_done_r5_reg_0,
      CE => '1',
      D => pi_dqs_found_lanes_r2(11),
      Q => pi_dqs_found_lanes_r3(11),
      R => '0'
    );
\pi_dqs_found_lanes_r3_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => init_dqsfound_done_r5_reg_0,
      CE => '1',
      D => pi_dqs_found_lanes_r2(1),
      Q => pi_dqs_found_lanes_r3(1),
      R => '0'
    );
\pi_dqs_found_lanes_r3_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => init_dqsfound_done_r5_reg_0,
      CE => '1',
      D => pi_dqs_found_lanes_r2(2),
      Q => pi_dqs_found_lanes_r3(2),
      R => '0'
    );
\pi_dqs_found_lanes_r3_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => init_dqsfound_done_r5_reg_0,
      CE => '1',
      D => pi_dqs_found_lanes_r2(3),
      Q => pi_dqs_found_lanes_r3(3),
      R => '0'
    );
\pi_dqs_found_lanes_r3_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => init_dqsfound_done_r5_reg_0,
      CE => '1',
      D => pi_dqs_found_lanes_r2(4),
      Q => pi_dqs_found_lanes_r3(4),
      R => '0'
    );
\pi_dqs_found_lanes_r3_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => init_dqsfound_done_r5_reg_0,
      CE => '1',
      D => pi_dqs_found_lanes_r2(5),
      Q => pi_dqs_found_lanes_r3(5),
      R => '0'
    );
\pi_dqs_found_lanes_r3_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => init_dqsfound_done_r5_reg_0,
      CE => '1',
      D => pi_dqs_found_lanes_r2(6),
      Q => pi_dqs_found_lanes_r3(6),
      R => '0'
    );
\pi_dqs_found_lanes_r3_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => init_dqsfound_done_r5_reg_0,
      CE => '1',
      D => pi_dqs_found_lanes_r2(7),
      Q => pi_dqs_found_lanes_r3(7),
      R => '0'
    );
\pi_dqs_found_lanes_r3_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => init_dqsfound_done_r5_reg_0,
      CE => '1',
      D => pi_dqs_found_lanes_r2(8),
      Q => pi_dqs_found_lanes_r3(8),
      R => '0'
    );
\pi_dqs_found_lanes_r3_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => init_dqsfound_done_r5_reg_0,
      CE => '1',
      D => pi_dqs_found_lanes_r2(9),
      Q => pi_dqs_found_lanes_r3(9),
      R => '0'
    );
\pi_rst_stg1_cal[0]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => \pi_rst_stg1_cal_r_reg_n_0_[0]\,
      I1 => rst_dqs_find,
      O => \pi_rst_stg1_cal[0]_i_1_n_0\
    );
\pi_rst_stg1_cal[1]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => \pi_rst_stg1_cal_r_reg_n_0_[1]\,
      I1 => rst_dqs_find,
      O => \pi_rst_stg1_cal[1]_i_1_n_0\
    );
\pi_rst_stg1_cal[2]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => \pi_rst_stg1_cal_r_reg_n_0_[2]\,
      I1 => rst_dqs_find,
      O => \pi_rst_stg1_cal[2]_i_1_n_0\
    );
\pi_rst_stg1_cal_r1[0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"000000000000FFA8"
    )
        port map (
      I0 => \pi_rst_stg1_cal_r1_reg_n_0_[0]\,
      I1 => \pi_dqs_found_any_bank_r_reg_n_0_[0]\,
      I2 => pi_dqs_found_all_bank(0),
      I3 => \pi_rst_stg1_cal_r_reg_n_0_[0]\,
      I4 => init_dqsfound_done_r_reg_0,
      I5 => \^fine_adjust_reg_0\,
      O => \pi_rst_stg1_cal_r1[0]_i_1_n_0\
    );
\pi_rst_stg1_cal_r1[1]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"000000F8"
    )
        port map (
      I0 => p_0_in22_in,
      I1 => pi_dqs_found_all_bank(1),
      I2 => \pi_rst_stg1_cal_r_reg_n_0_[1]\,
      I3 => init_dqsfound_done_r_reg_0,
      I4 => \^fine_adjust_reg_0\,
      O => \pi_rst_stg1_cal_r1[1]_i_1_n_0\
    );
\pi_rst_stg1_cal_r1[2]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"000000000000FFA8"
    )
        port map (
      I0 => p_0_in17_in,
      I1 => p_0_in62_in,
      I2 => pi_dqs_found_all_bank(2),
      I3 => \pi_rst_stg1_cal_r_reg_n_0_[2]\,
      I4 => init_dqsfound_done_r_reg_0,
      I5 => \^fine_adjust_reg_0\,
      O => \pi_rst_stg1_cal_r1[2]_i_1_n_0\
    );
\pi_rst_stg1_cal_r1_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => init_dqsfound_done_r5_reg_0,
      CE => '1',
      D => \pi_rst_stg1_cal_r1[0]_i_1_n_0\,
      Q => \pi_rst_stg1_cal_r1_reg_n_0_[0]\,
      R => '0'
    );
\pi_rst_stg1_cal_r1_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => init_dqsfound_done_r5_reg_0,
      CE => '1',
      D => \pi_rst_stg1_cal_r1[1]_i_1_n_0\,
      Q => p_0_in22_in,
      R => '0'
    );
\pi_rst_stg1_cal_r1_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => init_dqsfound_done_r5_reg_0,
      CE => '1',
      D => \pi_rst_stg1_cal_r1[2]_i_1_n_0\,
      Q => p_0_in17_in,
      R => '0'
    );
\pi_rst_stg1_cal_r[0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000011111110"
    )
        port map (
      I0 => \^fine_adjust_reg_0\,
      I1 => init_dqsfound_done_r_reg_0,
      I2 => \pi_rst_stg1_cal_r[0]_i_2_n_0\,
      I3 => \rd_byte_data_offset[0][5]_i_4_n_0\,
      I4 => \pi_rst_stg1_cal_r_reg_n_0_[0]\,
      I5 => \pi_rst_stg1_cal_r1_reg_n_0_[0]\,
      O => \pi_rst_stg1_cal_r[0]_i_1_n_0\
    );
\pi_rst_stg1_cal_r[0]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4F44"
    )
        port map (
      I0 => dqs_found_start_r,
      I1 => dqs_found_start_r_reg_0,
      I2 => pi_dqs_found_all_bank(0),
      I3 => \pi_dqs_found_any_bank_r_reg_n_0_[0]\,
      O => \pi_rst_stg1_cal_r[0]_i_2_n_0\
    );
\pi_rst_stg1_cal_r[1]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000AAAAAA08"
    )
        port map (
      I0 => \pi_rst_stg1_cal_r_reg[1]_0\,
      I1 => dqs_found_start_r_reg_0,
      I2 => dqs_found_start_r,
      I3 => \rd_byte_data_offset[0][11]_i_4_n_0\,
      I4 => \pi_rst_stg1_cal_r_reg_n_0_[1]\,
      I5 => p_0_in22_in,
      O => \pi_rst_stg1_cal_r[1]_i_1_n_0\
    );
\pi_rst_stg1_cal_r[2]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000011111110"
    )
        port map (
      I0 => \^fine_adjust_reg_0\,
      I1 => init_dqsfound_done_r_reg_0,
      I2 => \pi_rst_stg1_cal_r[2]_i_2_n_0\,
      I3 => \rd_byte_data_offset[0][17]_i_4_n_0\,
      I4 => \pi_rst_stg1_cal_r_reg_n_0_[2]\,
      I5 => p_0_in17_in,
      O => \pi_rst_stg1_cal_r[2]_i_1_n_0\
    );
\pi_rst_stg1_cal_r[2]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4F44"
    )
        port map (
      I0 => dqs_found_start_r,
      I1 => dqs_found_start_r_reg_0,
      I2 => pi_dqs_found_all_bank(2),
      I3 => p_0_in62_in,
      O => \pi_rst_stg1_cal_r[2]_i_2_n_0\
    );
\pi_rst_stg1_cal_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => init_dqsfound_done_r5_reg_0,
      CE => '1',
      D => \pi_rst_stg1_cal_r[0]_i_1_n_0\,
      Q => \pi_rst_stg1_cal_r_reg_n_0_[0]\,
      R => '0'
    );
\pi_rst_stg1_cal_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => init_dqsfound_done_r5_reg_0,
      CE => '1',
      D => \pi_rst_stg1_cal_r[1]_i_1_n_0\,
      Q => \pi_rst_stg1_cal_r_reg_n_0_[1]\,
      R => '0'
    );
\pi_rst_stg1_cal_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => init_dqsfound_done_r5_reg_0,
      CE => '1',
      D => \pi_rst_stg1_cal_r[2]_i_1_n_0\,
      Q => \pi_rst_stg1_cal_r_reg_n_0_[2]\,
      R => '0'
    );
\pi_rst_stg1_cal_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => init_dqsfound_done_r5_reg_0,
      CE => '1',
      D => \pi_rst_stg1_cal[0]_i_1_n_0\,
      Q => \^pi_rst_stg1_cal_reg[2]_0\(0),
      R => \pi_dqs_found_any_bank_reg[0]_0\(0)
    );
\pi_rst_stg1_cal_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => init_dqsfound_done_r5_reg_0,
      CE => '1',
      D => \pi_rst_stg1_cal[1]_i_1_n_0\,
      Q => \^pi_rst_stg1_cal_reg[2]_0\(1),
      R => \pi_dqs_found_any_bank_reg[0]_0\(0)
    );
\pi_rst_stg1_cal_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => init_dqsfound_done_r5_reg_0,
      CE => '1',
      D => \pi_rst_stg1_cal[2]_i_1_n_0\,
      Q => \^pi_rst_stg1_cal_reg[2]_0\(2),
      R => \pi_dqs_found_any_bank_reg[0]_0\(0)
    );
rank_done_r1_reg: unisim.vcomponents.FDRE
     port map (
      C => init_dqsfound_done_r5_reg_0,
      CE => '1',
      D => \^pi_dqs_found_rank_done\,
      Q => rank_done_r1,
      R => '0'
    );
rank_done_r_i_1: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00005551"
    )
        port map (
      I0 => init_dqsfound_done_r_reg_0,
      I1 => rd_data_offset_cal_done,
      I2 => \rnk_cnt_r_reg_n_0_[1]\,
      I3 => \rnk_cnt_r_reg_n_0_[0]\,
      I4 => rank_done_r_i_2_n_0,
      O => rank_done_r_i_1_n_0
    );
rank_done_r_i_2: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FF7F7F7F7F7F7F7F"
    )
        port map (
      I0 => pi_dqs_found_all_bank(0),
      I1 => pi_dqs_found_all_bank(1),
      I2 => pi_dqs_found_all_bank(2),
      I3 => pi_dqs_found_all_bank_r(2),
      I4 => pi_dqs_found_all_bank_r(1),
      I5 => pi_dqs_found_all_bank_r(0),
      O => rank_done_r_i_2_n_0
    );
rank_done_r_reg: unisim.vcomponents.FDRE
     port map (
      C => init_dqsfound_done_r5_reg_0,
      CE => '1',
      D => rank_done_r_i_1_n_0,
      Q => \^pi_dqs_found_rank_done\,
      R => '0'
    );
\rank_final_loop[0].bank_final_loop[0].final_data_offset[0][5]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => rd_data_offset_cal_done,
      I1 => init_dqsfound_done_r1_reg_n_0,
      O => p_22_out
    );
\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc[0][0]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \rd_byte_data_offset_reg_n_0_[0][0]\,
      O => \rank_final_loop[0].bank_final_loop[0].final_data_offset_mc[0][0]_i_1_n_0\
    );
\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc[0][1]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => \rd_byte_data_offset_reg_n_0_[0][0]\,
      I1 => \rd_byte_data_offset_reg_n_0_[0][1]\,
      O => \rank_final_loop[0].bank_final_loop[0].final_data_offset_mc[0][1]_i_1_n_0\
    );
\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc[0][2]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"A9"
    )
        port map (
      I0 => \rd_byte_data_offset_reg_n_0_[0][2]\,
      I1 => \rd_byte_data_offset_reg_n_0_[0][0]\,
      I2 => \rd_byte_data_offset_reg_n_0_[0][1]\,
      O => \rank_final_loop[0].bank_final_loop[0].final_data_offset_mc[0][2]_i_1_n_0\
    );
\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc[0][3]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"AAA9"
    )
        port map (
      I0 => \^q\(0),
      I1 => \rd_byte_data_offset_reg_n_0_[0][2]\,
      I2 => \rd_byte_data_offset_reg_n_0_[0][1]\,
      I3 => \rd_byte_data_offset_reg_n_0_[0][0]\,
      O => \rank_final_loop[0].bank_final_loop[0].final_data_offset_mc[0][3]_i_1_n_0\
    );
\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc[0][4]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AAAAAAA9"
    )
        port map (
      I0 => \rd_byte_data_offset_reg_n_0_[0][4]\,
      I1 => \^q\(0),
      I2 => \rd_byte_data_offset_reg_n_0_[0][0]\,
      I3 => \rd_byte_data_offset_reg_n_0_[0][1]\,
      I4 => \rd_byte_data_offset_reg_n_0_[0][2]\,
      O => \rank_final_loop[0].bank_final_loop[0].final_data_offset_mc[0][4]_i_1_n_0\
    );
\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc[0][5]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"04"
    )
        port map (
      I0 => init_dqsfound_done_r1_reg_n_0,
      I1 => rd_data_offset_cal_done,
      I2 => init_dqsfound_done_r_reg_0,
      O => final_data_offset_mc
    );
\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc[0][5]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAAAAAAAAAA9"
    )
        port map (
      I0 => \rd_byte_data_offset_reg_n_0_[0][5]\,
      I1 => \rd_byte_data_offset_reg_n_0_[0][4]\,
      I2 => \rd_byte_data_offset_reg_n_0_[0][2]\,
      I3 => \rd_byte_data_offset_reg_n_0_[0][1]\,
      I4 => \rd_byte_data_offset_reg_n_0_[0][0]\,
      I5 => \^q\(0),
      O => \rank_final_loop[0].bank_final_loop[0].final_data_offset_mc[0][5]_i_2_n_0\
    );
\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][0]\: unisim.vcomponents.FDRE
     port map (
      C => init_dqsfound_done_r5_reg_0,
      CE => final_data_offset_mc,
      D => \rank_final_loop[0].bank_final_loop[0].final_data_offset_mc[0][0]_i_1_n_0\,
      Q => \^rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][5]_0\(0),
      R => '0'
    );
\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][1]\: unisim.vcomponents.FDRE
     port map (
      C => init_dqsfound_done_r5_reg_0,
      CE => final_data_offset_mc,
      D => \rank_final_loop[0].bank_final_loop[0].final_data_offset_mc[0][1]_i_1_n_0\,
      Q => \^rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][5]_0\(1),
      R => '0'
    );
\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][2]\: unisim.vcomponents.FDRE
     port map (
      C => init_dqsfound_done_r5_reg_0,
      CE => final_data_offset_mc,
      D => \rank_final_loop[0].bank_final_loop[0].final_data_offset_mc[0][2]_i_1_n_0\,
      Q => \^rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][5]_0\(2),
      R => '0'
    );
\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][3]\: unisim.vcomponents.FDRE
     port map (
      C => init_dqsfound_done_r5_reg_0,
      CE => final_data_offset_mc,
      D => \rank_final_loop[0].bank_final_loop[0].final_data_offset_mc[0][3]_i_1_n_0\,
      Q => \^rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][5]_0\(3),
      R => '0'
    );
\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][4]\: unisim.vcomponents.FDRE
     port map (
      C => init_dqsfound_done_r5_reg_0,
      CE => final_data_offset_mc,
      D => \rank_final_loop[0].bank_final_loop[0].final_data_offset_mc[0][4]_i_1_n_0\,
      Q => \^rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][5]_0\(4),
      R => '0'
    );
\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][5]\: unisim.vcomponents.FDRE
     port map (
      C => init_dqsfound_done_r5_reg_0,
      CE => final_data_offset_mc,
      D => \rank_final_loop[0].bank_final_loop[0].final_data_offset_mc[0][5]_i_2_n_0\,
      Q => \^rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][5]_0\(5),
      R => '0'
    );
\rank_final_loop[0].bank_final_loop[0].final_data_offset_reg[0][0]\: unisim.vcomponents.FDRE
     port map (
      C => init_dqsfound_done_r5_reg_0,
      CE => p_22_out,
      D => \rd_byte_data_offset_reg_n_0_[0][0]\,
      Q => rd_data_offset_ranks_0(0),
      R => \pi_dqs_found_any_bank_reg[0]_0\(1)
    );
\rank_final_loop[0].bank_final_loop[0].final_data_offset_reg[0][1]\: unisim.vcomponents.FDRE
     port map (
      C => init_dqsfound_done_r5_reg_0,
      CE => p_22_out,
      D => \rd_byte_data_offset_reg_n_0_[0][1]\,
      Q => rd_data_offset_ranks_0(1),
      R => \pi_dqs_found_any_bank_reg[0]_0\(1)
    );
\rank_final_loop[0].bank_final_loop[0].final_data_offset_reg[0][2]\: unisim.vcomponents.FDRE
     port map (
      C => init_dqsfound_done_r5_reg_0,
      CE => p_22_out,
      D => \rd_byte_data_offset_reg_n_0_[0][2]\,
      Q => rd_data_offset_ranks_0(2),
      R => \pi_dqs_found_any_bank_reg[0]_0\(1)
    );
\rank_final_loop[0].bank_final_loop[0].final_data_offset_reg[0][3]\: unisim.vcomponents.FDRE
     port map (
      C => init_dqsfound_done_r5_reg_0,
      CE => p_22_out,
      D => \^q\(0),
      Q => \^rank_final_loop[0].bank_final_loop[0].final_data_offset_reg[0][3]_0\(0),
      R => \pi_dqs_found_any_bank_reg[0]_0\(1)
    );
\rank_final_loop[0].bank_final_loop[0].final_data_offset_reg[0][4]\: unisim.vcomponents.FDRE
     port map (
      C => init_dqsfound_done_r5_reg_0,
      CE => p_22_out,
      D => \rd_byte_data_offset_reg_n_0_[0][4]\,
      Q => rd_data_offset_ranks_0(4),
      R => \pi_dqs_found_any_bank_reg[0]_0\(1)
    );
\rank_final_loop[0].bank_final_loop[0].final_data_offset_reg[0][5]\: unisim.vcomponents.FDRE
     port map (
      C => init_dqsfound_done_r5_reg_0,
      CE => p_22_out,
      D => \rd_byte_data_offset_reg_n_0_[0][5]\,
      Q => rd_data_offset_ranks_0(5),
      R => \pi_dqs_found_any_bank_reg[0]_0\(1)
    );
\rank_final_loop[0].bank_final_loop[1].final_data_offset[0][11]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"8A"
    )
        port map (
      I0 => init_dqsfound_done_r5,
      I1 => init_dqsfound_done_r1_reg_n_0,
      I2 => rd_data_offset_cal_done,
      O => final_data_offset
    );
\rank_final_loop[0].bank_final_loop[1].final_data_offset_mc[0][11]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"00D0"
    )
        port map (
      I0 => rd_data_offset_cal_done,
      I1 => init_dqsfound_done_r1_reg_n_0,
      I2 => init_dqsfound_done_r5,
      I3 => init_dqsfound_done_r_reg_0,
      O => \rank_final_loop[0].bank_final_loop[1].final_data_offset_mc[0][11]_i_1_n_0\
    );
\rank_final_loop[0].bank_final_loop[1].final_data_offset_mc_reg[0][10]\: unisim.vcomponents.FDRE
     port map (
      C => init_dqsfound_done_r5_reg_0,
      CE => \rank_final_loop[0].bank_final_loop[1].final_data_offset_mc[0][11]_i_1_n_0\,
      D => \rank_final_loop[0].final_do_max_reg[0]_45\(4),
      Q => \^rank_final_loop[0].bank_final_loop[1].final_data_offset_mc_reg[0][11]_0\(4),
      R => '0'
    );
\rank_final_loop[0].bank_final_loop[1].final_data_offset_mc_reg[0][11]\: unisim.vcomponents.FDRE
     port map (
      C => init_dqsfound_done_r5_reg_0,
      CE => \rank_final_loop[0].bank_final_loop[1].final_data_offset_mc[0][11]_i_1_n_0\,
      D => \rank_final_loop[0].final_do_max_reg[0]_45\(5),
      Q => \^rank_final_loop[0].bank_final_loop[1].final_data_offset_mc_reg[0][11]_0\(5),
      R => '0'
    );
\rank_final_loop[0].bank_final_loop[1].final_data_offset_mc_reg[0][6]\: unisim.vcomponents.FDRE
     port map (
      C => init_dqsfound_done_r5_reg_0,
      CE => \rank_final_loop[0].bank_final_loop[1].final_data_offset_mc[0][11]_i_1_n_0\,
      D => \rank_final_loop[0].final_do_max_reg[0]_45\(0),
      Q => \^rank_final_loop[0].bank_final_loop[1].final_data_offset_mc_reg[0][11]_0\(0),
      R => '0'
    );
\rank_final_loop[0].bank_final_loop[1].final_data_offset_mc_reg[0][7]\: unisim.vcomponents.FDRE
     port map (
      C => init_dqsfound_done_r5_reg_0,
      CE => \rank_final_loop[0].bank_final_loop[1].final_data_offset_mc[0][11]_i_1_n_0\,
      D => \rank_final_loop[0].final_do_max_reg[0]_45\(1),
      Q => \^rank_final_loop[0].bank_final_loop[1].final_data_offset_mc_reg[0][11]_0\(1),
      R => '0'
    );
\rank_final_loop[0].bank_final_loop[1].final_data_offset_mc_reg[0][8]\: unisim.vcomponents.FDRE
     port map (
      C => init_dqsfound_done_r5_reg_0,
      CE => \rank_final_loop[0].bank_final_loop[1].final_data_offset_mc[0][11]_i_1_n_0\,
      D => \rank_final_loop[0].final_do_max_reg[0]_45\(2),
      Q => \^rank_final_loop[0].bank_final_loop[1].final_data_offset_mc_reg[0][11]_0\(2),
      R => '0'
    );
\rank_final_loop[0].bank_final_loop[1].final_data_offset_mc_reg[0][9]\: unisim.vcomponents.FDRE
     port map (
      C => init_dqsfound_done_r5_reg_0,
      CE => \rank_final_loop[0].bank_final_loop[1].final_data_offset_mc[0][11]_i_1_n_0\,
      D => \rank_final_loop[0].final_do_max_reg[0]_45\(3),
      Q => \^rank_final_loop[0].bank_final_loop[1].final_data_offset_mc_reg[0][11]_0\(3),
      R => '0'
    );
\rank_final_loop[0].bank_final_loop[1].final_data_offset_reg[0][10]\: unisim.vcomponents.FDRE
     port map (
      C => init_dqsfound_done_r5_reg_0,
      CE => final_data_offset,
      D => \rank_final_loop[0].final_do_max_reg[0]_45\(4),
      Q => rd_data_offset_ranks_1(4),
      R => \pi_dqs_found_any_bank_reg[0]_0\(1)
    );
\rank_final_loop[0].bank_final_loop[1].final_data_offset_reg[0][11]\: unisim.vcomponents.FDRE
     port map (
      C => init_dqsfound_done_r5_reg_0,
      CE => final_data_offset,
      D => \rank_final_loop[0].final_do_max_reg[0]_45\(5),
      Q => rd_data_offset_ranks_1(5),
      R => \pi_dqs_found_any_bank_reg[0]_0\(1)
    );
\rank_final_loop[0].bank_final_loop[1].final_data_offset_reg[0][6]\: unisim.vcomponents.FDRE
     port map (
      C => init_dqsfound_done_r5_reg_0,
      CE => final_data_offset,
      D => \rank_final_loop[0].final_do_max_reg[0]_45\(0),
      Q => rd_data_offset_ranks_1(0),
      R => \pi_dqs_found_any_bank_reg[0]_0\(1)
    );
\rank_final_loop[0].bank_final_loop[1].final_data_offset_reg[0][7]\: unisim.vcomponents.FDRE
     port map (
      C => init_dqsfound_done_r5_reg_0,
      CE => final_data_offset,
      D => \rank_final_loop[0].final_do_max_reg[0]_45\(1),
      Q => rd_data_offset_ranks_1(1),
      R => \pi_dqs_found_any_bank_reg[0]_0\(1)
    );
\rank_final_loop[0].bank_final_loop[1].final_data_offset_reg[0][8]\: unisim.vcomponents.FDRE
     port map (
      C => init_dqsfound_done_r5_reg_0,
      CE => final_data_offset,
      D => \rank_final_loop[0].final_do_max_reg[0]_45\(2),
      Q => rd_data_offset_ranks_1(2),
      R => \pi_dqs_found_any_bank_reg[0]_0\(1)
    );
\rank_final_loop[0].bank_final_loop[1].final_data_offset_reg[0][9]\: unisim.vcomponents.FDRE
     port map (
      C => init_dqsfound_done_r5_reg_0,
      CE => final_data_offset,
      D => \rank_final_loop[0].final_do_max_reg[0]_45\(3),
      Q => \^rank_final_loop[0].bank_final_loop[1].final_data_offset_reg[0][9]_0\(0),
      R => \pi_dqs_found_any_bank_reg[0]_0\(1)
    );
\rank_final_loop[0].bank_final_loop[2].final_data_offset_mc[0][12]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \rd_byte_data_offset_reg_n_0_[0][12]\,
      O => \rank_final_loop[0].bank_final_loop[2].final_data_offset_mc[0][12]_i_1_n_0\
    );
\rank_final_loop[0].bank_final_loop[2].final_data_offset_mc[0][13]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => \rd_byte_data_offset_reg_n_0_[0][12]\,
      I1 => \rd_byte_data_offset_reg_n_0_[0][13]\,
      O => \rank_final_loop[0].bank_final_loop[2].final_data_offset_mc[0][13]_i_1_n_0\
    );
\rank_final_loop[0].bank_final_loop[2].final_data_offset_mc[0][14]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"A9"
    )
        port map (
      I0 => \rd_byte_data_offset_reg_n_0_[0][14]\,
      I1 => \rd_byte_data_offset_reg_n_0_[0][12]\,
      I2 => \rd_byte_data_offset_reg_n_0_[0][13]\,
      O => \rank_final_loop[0].bank_final_loop[2].final_data_offset_mc[0][14]_i_1_n_0\
    );
\rank_final_loop[0].bank_final_loop[2].final_data_offset_mc[0][15]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"AAA9"
    )
        port map (
      I0 => \^rd_byte_data_offset_reg[0][15]_0\(0),
      I1 => \rd_byte_data_offset_reg_n_0_[0][14]\,
      I2 => \rd_byte_data_offset_reg_n_0_[0][13]\,
      I3 => \rd_byte_data_offset_reg_n_0_[0][12]\,
      O => \rank_final_loop[0].bank_final_loop[2].final_data_offset_mc[0][15]_i_1_n_0\
    );
\rank_final_loop[0].bank_final_loop[2].final_data_offset_mc[0][16]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AAAAAAA9"
    )
        port map (
      I0 => \rd_byte_data_offset_reg_n_0_[0][16]\,
      I1 => \^rd_byte_data_offset_reg[0][15]_0\(0),
      I2 => \rd_byte_data_offset_reg_n_0_[0][12]\,
      I3 => \rd_byte_data_offset_reg_n_0_[0][13]\,
      I4 => \rd_byte_data_offset_reg_n_0_[0][14]\,
      O => \rank_final_loop[0].bank_final_loop[2].final_data_offset_mc[0][16]_i_1_n_0\
    );
\rank_final_loop[0].bank_final_loop[2].final_data_offset_mc[0][17]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAAAAAAAAAA9"
    )
        port map (
      I0 => \rd_byte_data_offset_reg_n_0_[0][17]\,
      I1 => \rd_byte_data_offset_reg_n_0_[0][16]\,
      I2 => \rd_byte_data_offset_reg_n_0_[0][14]\,
      I3 => \rd_byte_data_offset_reg_n_0_[0][13]\,
      I4 => \rd_byte_data_offset_reg_n_0_[0][12]\,
      I5 => \^rd_byte_data_offset_reg[0][15]_0\(0),
      O => \rank_final_loop[0].bank_final_loop[2].final_data_offset_mc[0][17]_i_1_n_0\
    );
\rank_final_loop[0].bank_final_loop[2].final_data_offset_mc_reg[0][12]\: unisim.vcomponents.FDRE
     port map (
      C => init_dqsfound_done_r5_reg_0,
      CE => final_data_offset_mc,
      D => \rank_final_loop[0].bank_final_loop[2].final_data_offset_mc[0][12]_i_1_n_0\,
      Q => \^rank_final_loop[0].bank_final_loop[2].final_data_offset_mc_reg[0][17]_0\(0),
      R => '0'
    );
\rank_final_loop[0].bank_final_loop[2].final_data_offset_mc_reg[0][13]\: unisim.vcomponents.FDRE
     port map (
      C => init_dqsfound_done_r5_reg_0,
      CE => final_data_offset_mc,
      D => \rank_final_loop[0].bank_final_loop[2].final_data_offset_mc[0][13]_i_1_n_0\,
      Q => \^rank_final_loop[0].bank_final_loop[2].final_data_offset_mc_reg[0][17]_0\(1),
      R => '0'
    );
\rank_final_loop[0].bank_final_loop[2].final_data_offset_mc_reg[0][14]\: unisim.vcomponents.FDRE
     port map (
      C => init_dqsfound_done_r5_reg_0,
      CE => final_data_offset_mc,
      D => \rank_final_loop[0].bank_final_loop[2].final_data_offset_mc[0][14]_i_1_n_0\,
      Q => \^rank_final_loop[0].bank_final_loop[2].final_data_offset_mc_reg[0][17]_0\(2),
      R => '0'
    );
\rank_final_loop[0].bank_final_loop[2].final_data_offset_mc_reg[0][15]\: unisim.vcomponents.FDRE
     port map (
      C => init_dqsfound_done_r5_reg_0,
      CE => final_data_offset_mc,
      D => \rank_final_loop[0].bank_final_loop[2].final_data_offset_mc[0][15]_i_1_n_0\,
      Q => \^rank_final_loop[0].bank_final_loop[2].final_data_offset_mc_reg[0][17]_0\(3),
      R => '0'
    );
\rank_final_loop[0].bank_final_loop[2].final_data_offset_mc_reg[0][16]\: unisim.vcomponents.FDRE
     port map (
      C => init_dqsfound_done_r5_reg_0,
      CE => final_data_offset_mc,
      D => \rank_final_loop[0].bank_final_loop[2].final_data_offset_mc[0][16]_i_1_n_0\,
      Q => \^rank_final_loop[0].bank_final_loop[2].final_data_offset_mc_reg[0][17]_0\(4),
      R => '0'
    );
\rank_final_loop[0].bank_final_loop[2].final_data_offset_mc_reg[0][17]\: unisim.vcomponents.FDRE
     port map (
      C => init_dqsfound_done_r5_reg_0,
      CE => final_data_offset_mc,
      D => \rank_final_loop[0].bank_final_loop[2].final_data_offset_mc[0][17]_i_1_n_0\,
      Q => \^rank_final_loop[0].bank_final_loop[2].final_data_offset_mc_reg[0][17]_0\(5),
      R => '0'
    );
\rank_final_loop[0].bank_final_loop[2].final_data_offset_reg[0][12]\: unisim.vcomponents.FDRE
     port map (
      C => init_dqsfound_done_r5_reg_0,
      CE => p_22_out,
      D => \rd_byte_data_offset_reg_n_0_[0][12]\,
      Q => rd_data_offset_ranks_2(0),
      R => \pi_dqs_found_any_bank_reg[0]_0\(0)
    );
\rank_final_loop[0].bank_final_loop[2].final_data_offset_reg[0][13]\: unisim.vcomponents.FDRE
     port map (
      C => init_dqsfound_done_r5_reg_0,
      CE => p_22_out,
      D => \rd_byte_data_offset_reg_n_0_[0][13]\,
      Q => rd_data_offset_ranks_2(1),
      R => \pi_dqs_found_any_bank_reg[0]_0\(0)
    );
\rank_final_loop[0].bank_final_loop[2].final_data_offset_reg[0][14]\: unisim.vcomponents.FDRE
     port map (
      C => init_dqsfound_done_r5_reg_0,
      CE => p_22_out,
      D => \rd_byte_data_offset_reg_n_0_[0][14]\,
      Q => rd_data_offset_ranks_2(2),
      R => \pi_dqs_found_any_bank_reg[0]_0\(0)
    );
\rank_final_loop[0].bank_final_loop[2].final_data_offset_reg[0][15]\: unisim.vcomponents.FDRE
     port map (
      C => init_dqsfound_done_r5_reg_0,
      CE => p_22_out,
      D => \^rd_byte_data_offset_reg[0][15]_0\(0),
      Q => \^rank_final_loop[0].bank_final_loop[2].final_data_offset_reg[0][15]_0\(0),
      R => \pi_dqs_found_any_bank_reg[0]_0\(0)
    );
\rank_final_loop[0].bank_final_loop[2].final_data_offset_reg[0][16]\: unisim.vcomponents.FDRE
     port map (
      C => init_dqsfound_done_r5_reg_0,
      CE => p_22_out,
      D => \rd_byte_data_offset_reg_n_0_[0][16]\,
      Q => rd_data_offset_ranks_2(4),
      R => \pi_dqs_found_any_bank_reg[0]_0\(0)
    );
\rank_final_loop[0].bank_final_loop[2].final_data_offset_reg[0][17]\: unisim.vcomponents.FDRE
     port map (
      C => init_dqsfound_done_r5_reg_0,
      CE => p_22_out,
      D => \rd_byte_data_offset_reg_n_0_[0][17]\,
      Q => rd_data_offset_ranks_2(5),
      R => \pi_dqs_found_any_bank_reg[0]_0\(1)
    );
\rank_final_loop[0].final_do_index[0][0]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \rank_final_loop[0].final_do_index_reg_n_0_[0][0]\,
      O => \rank_final_loop[0].final_do_index[0][0]_i_1_n_0\
    );
\rank_final_loop[0].final_do_index[0][1]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \rank_final_loop[0].final_do_index_reg_n_0_[0][0]\,
      I1 => \rank_final_loop[0].final_do_index_reg_n_0_[0][1]\,
      O => \rank_final_loop[0].final_do_index[0][1]_i_1_n_0\
    );
\rank_final_loop[0].final_do_index[0][2]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"6A"
    )
        port map (
      I0 => \rank_final_loop[0].final_do_index_reg_n_0_[0][2]\,
      I1 => \rank_final_loop[0].final_do_index_reg_n_0_[0][1]\,
      I2 => \rank_final_loop[0].final_do_index_reg_n_0_[0][0]\,
      O => \rank_final_loop[0].final_do_index[0][2]_i_1_n_0\
    );
\rank_final_loop[0].final_do_index_reg[0][0]\: unisim.vcomponents.FDRE
     port map (
      C => init_dqsfound_done_r5_reg_0,
      CE => '1',
      D => \rank_final_loop[0].final_do_index[0][0]_i_1_n_0\,
      Q => \rank_final_loop[0].final_do_index_reg_n_0_[0][0]\,
      R => \pi_dqs_found_any_bank_reg[0]_0\(1)
    );
\rank_final_loop[0].final_do_index_reg[0][1]\: unisim.vcomponents.FDRE
     port map (
      C => init_dqsfound_done_r5_reg_0,
      CE => '1',
      D => \rank_final_loop[0].final_do_index[0][1]_i_1_n_0\,
      Q => \rank_final_loop[0].final_do_index_reg_n_0_[0][1]\,
      R => \pi_dqs_found_any_bank_reg[0]_0\(1)
    );
\rank_final_loop[0].final_do_index_reg[0][2]\: unisim.vcomponents.FDRE
     port map (
      C => init_dqsfound_done_r5_reg_0,
      CE => '1',
      D => \rank_final_loop[0].final_do_index[0][2]_i_1_n_0\,
      Q => \rank_final_loop[0].final_do_index_reg_n_0_[0][2]\,
      R => \pi_dqs_found_any_bank_reg[0]_0\(1)
    );
\rank_final_loop[0].final_do_max[0][0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FCFFF4F4FCFFF7F7"
    )
        port map (
      I0 => rd_data_offset_ranks_1(0),
      I1 => \rank_final_loop[0].final_do_index_reg_n_0_[0][0]\,
      I2 => \rank_final_loop[0].final_do_index_reg_n_0_[0][2]\,
      I3 => rd_data_offset_ranks_2(0),
      I4 => \rank_final_loop[0].final_do_index_reg_n_0_[0][1]\,
      I5 => rd_data_offset_ranks_0(0),
      O => \rank_final_loop[0].final_do_max[0][0]_i_1_n_0\
    );
\rank_final_loop[0].final_do_max[0][1]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => \rank_final_loop[0].final_do_max[0][0]_i_1_n_0\,
      I1 => \rank_final_loop[0].final_do_max[0][5]_i_8_n_0\,
      O => \rank_final_loop[0].final_do_max[0][1]_i_1_n_0\
    );
\rank_final_loop[0].final_do_max[0][2]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"95"
    )
        port map (
      I0 => \rank_final_loop[0].final_do_max[0][5]_i_9_n_0\,
      I1 => \rank_final_loop[0].final_do_max[0][0]_i_1_n_0\,
      I2 => \rank_final_loop[0].final_do_max[0][5]_i_8_n_0\,
      O => \rank_final_loop[0].final_do_max[0][2]_i_1_n_0\
    );
\rank_final_loop[0].final_do_max[0][3]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9555"
    )
        port map (
      I0 => \rank_final_loop[0].final_do_max[0][5]_i_7_n_0\,
      I1 => \rank_final_loop[0].final_do_max[0][5]_i_9_n_0\,
      I2 => \rank_final_loop[0].final_do_max[0][5]_i_8_n_0\,
      I3 => \rank_final_loop[0].final_do_max[0][0]_i_1_n_0\,
      O => \rank_final_loop[0].final_do_max[0][3]_i_1_n_0\
    );
\rank_final_loop[0].final_do_max[0][4]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"7FFF8000"
    )
        port map (
      I0 => \rank_final_loop[0].final_do_max[0][5]_i_9_n_0\,
      I1 => \rank_final_loop[0].final_do_max[0][5]_i_8_n_0\,
      I2 => \rank_final_loop[0].final_do_max[0][0]_i_1_n_0\,
      I3 => \rank_final_loop[0].final_do_max[0][5]_i_7_n_0\,
      I4 => \rank_final_loop[0].final_do_max[0][5]_i_3_n_0\,
      O => \rank_final_loop[0].final_do_max[0][4]_i_1_n_0\
    );
\rank_final_loop[0].final_do_max[0][5]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000F4F4FF"
    )
        port map (
      I0 => \rank_final_loop[0].final_do_max_reg[0]_45\(4),
      I1 => \rank_final_loop[0].final_do_max[0][5]_i_3_n_0\,
      I2 => \rank_final_loop[0].final_do_max[0][5]_i_4_n_0\,
      I3 => \rank_final_loop[0].final_do_max_reg[0]_45\(5),
      I4 => \rank_final_loop[0].final_do_max[0][5]_i_5_n_0\,
      I5 => \rank_final_loop[0].final_do_max[0][5]_i_6_n_0\,
      O => \rank_final_loop[0].final_do_max[0][5]_i_1_n_0\
    );
\rank_final_loop[0].final_do_max[0][5]_i_10\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"011F"
    )
        port map (
      I0 => \rank_final_loop[0].final_do_max_reg[0]_45\(0),
      I1 => \rank_final_loop[0].final_do_max[0][0]_i_1_n_0\,
      I2 => \rank_final_loop[0].final_do_max[0][5]_i_8_n_0\,
      I3 => \rank_final_loop[0].final_do_max_reg[0]_45\(1),
      O => \rank_final_loop[0].final_do_max[0][5]_i_10_n_0\
    );
\rank_final_loop[0].final_do_max[0][5]_i_11\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \rank_final_loop[0].final_do_max_reg[0]_45\(4),
      I1 => \rank_final_loop[0].final_do_max[0][5]_i_3_n_0\,
      O => \rank_final_loop[0].final_do_max[0][5]_i_11_n_0\
    );
\rank_final_loop[0].final_do_max[0][5]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"40000000BFFFFFFF"
    )
        port map (
      I0 => \rank_final_loop[0].final_do_max[0][5]_i_3_n_0\,
      I1 => \rank_final_loop[0].final_do_max[0][5]_i_7_n_0\,
      I2 => \rank_final_loop[0].final_do_max[0][0]_i_1_n_0\,
      I3 => \rank_final_loop[0].final_do_max[0][5]_i_8_n_0\,
      I4 => \rank_final_loop[0].final_do_max[0][5]_i_9_n_0\,
      I5 => \rank_final_loop[0].final_do_max[0][5]_i_5_n_0\,
      O => \rank_final_loop[0].final_do_max[0][5]_i_2_n_0\
    );
\rank_final_loop[0].final_do_max[0][5]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"03000B0B03000808"
    )
        port map (
      I0 => rd_data_offset_ranks_1(4),
      I1 => \rank_final_loop[0].final_do_index_reg_n_0_[0][0]\,
      I2 => \rank_final_loop[0].final_do_index_reg_n_0_[0][2]\,
      I3 => rd_data_offset_ranks_2(4),
      I4 => \rank_final_loop[0].final_do_index_reg_n_0_[0][1]\,
      I5 => rd_data_offset_ranks_0(4),
      O => \rank_final_loop[0].final_do_max[0][5]_i_3_n_0\
    );
\rank_final_loop[0].final_do_max[0][5]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000071007100FF"
    )
        port map (
      I0 => \rank_final_loop[0].final_do_max[0][5]_i_9_n_0\,
      I1 => \rank_final_loop[0].final_do_max_reg[0]_45\(2),
      I2 => \rank_final_loop[0].final_do_max[0][5]_i_10_n_0\,
      I3 => \rank_final_loop[0].final_do_max[0][5]_i_11_n_0\,
      I4 => \rank_final_loop[0].final_do_max_reg[0]_45\(3),
      I5 => \rank_final_loop[0].final_do_max[0][5]_i_7_n_0\,
      O => \rank_final_loop[0].final_do_max[0][5]_i_4_n_0\
    );
\rank_final_loop[0].final_do_max[0][5]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FCFFF4F4FCFFF7F7"
    )
        port map (
      I0 => rd_data_offset_ranks_1(5),
      I1 => \rank_final_loop[0].final_do_index_reg_n_0_[0][0]\,
      I2 => \rank_final_loop[0].final_do_index_reg_n_0_[0][2]\,
      I3 => rd_data_offset_ranks_2(5),
      I4 => \rank_final_loop[0].final_do_index_reg_n_0_[0][1]\,
      I5 => rd_data_offset_ranks_0(5),
      O => \rank_final_loop[0].final_do_max[0][5]_i_5_n_0\
    );
\rank_final_loop[0].final_do_max[0][5]_i_6\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => \rank_final_loop[0].final_do_index_reg_n_0_[0][0]\,
      I1 => \rank_final_loop[0].final_do_index_reg_n_0_[0][2]\,
      O => \rank_final_loop[0].final_do_max[0][5]_i_6_n_0\
    );
\rank_final_loop[0].final_do_max[0][5]_i_7\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FCFCDCDFFFFFDCDF"
    )
        port map (
      I0 => \^rank_final_loop[0].bank_final_loop[1].final_data_offset_reg[0][9]_0\(0),
      I1 => \rank_final_loop[0].final_do_index_reg_n_0_[0][2]\,
      I2 => \rank_final_loop[0].final_do_index_reg_n_0_[0][0]\,
      I3 => \^rank_final_loop[0].bank_final_loop[0].final_data_offset_reg[0][3]_0\(0),
      I4 => \rank_final_loop[0].final_do_index_reg_n_0_[0][1]\,
      I5 => \^rank_final_loop[0].bank_final_loop[2].final_data_offset_reg[0][15]_0\(0),
      O => \rank_final_loop[0].final_do_max[0][5]_i_7_n_0\
    );
\rank_final_loop[0].final_do_max[0][5]_i_8\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FCFFF4F4FCFFF7F7"
    )
        port map (
      I0 => rd_data_offset_ranks_1(1),
      I1 => \rank_final_loop[0].final_do_index_reg_n_0_[0][0]\,
      I2 => \rank_final_loop[0].final_do_index_reg_n_0_[0][2]\,
      I3 => rd_data_offset_ranks_2(1),
      I4 => \rank_final_loop[0].final_do_index_reg_n_0_[0][1]\,
      I5 => rd_data_offset_ranks_0(1),
      O => \rank_final_loop[0].final_do_max[0][5]_i_8_n_0\
    );
\rank_final_loop[0].final_do_max[0][5]_i_9\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FCFFF4F4FCFFF7F7"
    )
        port map (
      I0 => rd_data_offset_ranks_1(2),
      I1 => \rank_final_loop[0].final_do_index_reg_n_0_[0][0]\,
      I2 => \rank_final_loop[0].final_do_index_reg_n_0_[0][2]\,
      I3 => rd_data_offset_ranks_2(2),
      I4 => \rank_final_loop[0].final_do_index_reg_n_0_[0][1]\,
      I5 => rd_data_offset_ranks_0(2),
      O => \rank_final_loop[0].final_do_max[0][5]_i_9_n_0\
    );
\rank_final_loop[0].final_do_max_reg[0][0]\: unisim.vcomponents.FDRE
     port map (
      C => init_dqsfound_done_r5_reg_0,
      CE => \rank_final_loop[0].final_do_max[0][5]_i_1_n_0\,
      D => \rank_final_loop[0].final_do_max[0][0]_i_1_n_0\,
      Q => \rank_final_loop[0].final_do_max_reg[0]_45\(0),
      R => \pi_dqs_found_any_bank_reg[0]_0\(0)
    );
\rank_final_loop[0].final_do_max_reg[0][1]\: unisim.vcomponents.FDRE
     port map (
      C => init_dqsfound_done_r5_reg_0,
      CE => \rank_final_loop[0].final_do_max[0][5]_i_1_n_0\,
      D => \rank_final_loop[0].final_do_max[0][1]_i_1_n_0\,
      Q => \rank_final_loop[0].final_do_max_reg[0]_45\(1),
      R => \pi_dqs_found_any_bank_reg[0]_0\(0)
    );
\rank_final_loop[0].final_do_max_reg[0][2]\: unisim.vcomponents.FDRE
     port map (
      C => init_dqsfound_done_r5_reg_0,
      CE => \rank_final_loop[0].final_do_max[0][5]_i_1_n_0\,
      D => \rank_final_loop[0].final_do_max[0][2]_i_1_n_0\,
      Q => \rank_final_loop[0].final_do_max_reg[0]_45\(2),
      R => \pi_dqs_found_any_bank_reg[0]_0\(0)
    );
\rank_final_loop[0].final_do_max_reg[0][3]\: unisim.vcomponents.FDRE
     port map (
      C => init_dqsfound_done_r5_reg_0,
      CE => \rank_final_loop[0].final_do_max[0][5]_i_1_n_0\,
      D => \rank_final_loop[0].final_do_max[0][3]_i_1_n_0\,
      Q => \rank_final_loop[0].final_do_max_reg[0]_45\(3),
      R => \pi_dqs_found_any_bank_reg[0]_0\(0)
    );
\rank_final_loop[0].final_do_max_reg[0][4]\: unisim.vcomponents.FDRE
     port map (
      C => init_dqsfound_done_r5_reg_0,
      CE => \rank_final_loop[0].final_do_max[0][5]_i_1_n_0\,
      D => \rank_final_loop[0].final_do_max[0][4]_i_1_n_0\,
      Q => \rank_final_loop[0].final_do_max_reg[0]_45\(4),
      R => \pi_dqs_found_any_bank_reg[0]_0\(0)
    );
\rank_final_loop[0].final_do_max_reg[0][5]\: unisim.vcomponents.FDRE
     port map (
      C => init_dqsfound_done_r5_reg_0,
      CE => \rank_final_loop[0].final_do_max[0][5]_i_1_n_0\,
      D => \rank_final_loop[0].final_do_max[0][5]_i_2_n_0\,
      Q => \rank_final_loop[0].final_do_max_reg[0]_45\(5),
      R => \pi_dqs_found_any_bank_reg[0]_0\(0)
    );
\rd_byte_data_offset[0][10]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"6AAAAAAA"
    )
        port map (
      I0 => \rd_byte_data_offset_reg_n_0_[0][10]\,
      I1 => \^rd_byte_data_offset_reg[0][9]_0\(0),
      I2 => \rd_byte_data_offset_reg_n_0_[0][8]\,
      I3 => \rd_byte_data_offset_reg_n_0_[0][7]\,
      I4 => \rd_byte_data_offset_reg_n_0_[0][6]\,
      O => p_1_in(4)
    );
\rd_byte_data_offset[0][11]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAAAAAAAFFAE"
    )
        port map (
      I0 => init_dqsfound_done_r_reg_0,
      I1 => rank_done_r1,
      I2 => rd_data_offset_cal_done,
      I3 => \rd_byte_data_offset[0][11]_i_4_n_0\,
      I4 => \rnk_cnt_r_reg_n_0_[0]\,
      I5 => \rnk_cnt_r_reg_n_0_[1]\,
      O => \rd_byte_data_offset[0][11]_i_1_n_0\
    );
\rd_byte_data_offset[0][11]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000000001"
    )
        port map (
      I0 => \rd_byte_data_offset[0][11]_i_4_n_0\,
      I1 => rank_done_r1,
      I2 => pi_dqs_found_all_bank(1),
      I3 => rd_data_offset_cal_done,
      I4 => \^fine_adjust_reg_0\,
      I5 => \rd_byte_data_offset[0][11]_i_5_n_0\,
      O => \rd_byte_data_offset[0][11]_i_2_n_0\
    );
\rd_byte_data_offset[0][11]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"6AAAAAAAAAAAAAAA"
    )
        port map (
      I0 => \rd_byte_data_offset_reg_n_0_[0][11]\,
      I1 => \rd_byte_data_offset_reg_n_0_[0][6]\,
      I2 => \rd_byte_data_offset_reg_n_0_[0][7]\,
      I3 => \rd_byte_data_offset_reg_n_0_[0][8]\,
      I4 => \^rd_byte_data_offset_reg[0][9]_0\(0),
      I5 => \rd_byte_data_offset_reg_n_0_[0][10]\,
      O => p_1_in(5)
    );
\rd_byte_data_offset[0][11]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFEEEAAAAAAAA"
    )
        port map (
      I0 => \rd_byte_data_offset_reg_n_0_[0][11]\,
      I1 => \^rd_byte_data_offset_reg[0][9]_0\(0),
      I2 => \rd_byte_data_offset_reg_n_0_[0][6]\,
      I3 => \rd_byte_data_offset_reg_n_0_[0][7]\,
      I4 => \rd_byte_data_offset_reg_n_0_[0][8]\,
      I5 => \rd_byte_data_offset_reg_n_0_[0][10]\,
      O => \rd_byte_data_offset[0][11]_i_4_n_0\
    );
\rd_byte_data_offset[0][11]_i_5\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FDFF"
    )
        port map (
      I0 => \FSM_sequential_fine_adj_state_r[0]_i_6_n_0\,
      I1 => \rnk_cnt_r_reg_n_0_[0]\,
      I2 => \rnk_cnt_r_reg_n_0_[1]\,
      I3 => dqs_found_start_r,
      O => \rd_byte_data_offset[0][11]_i_5_n_0\
    );
\rd_byte_data_offset[0][13]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \rd_byte_data_offset_reg_n_0_[0][13]\,
      I1 => \rd_byte_data_offset_reg_n_0_[0][12]\,
      O => \rd_byte_data_offset[0][13]_i_1_n_0\
    );
\rd_byte_data_offset[0][14]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"6A"
    )
        port map (
      I0 => \rd_byte_data_offset_reg_n_0_[0][14]\,
      I1 => \rd_byte_data_offset_reg_n_0_[0][12]\,
      I2 => \rd_byte_data_offset_reg_n_0_[0][13]\,
      O => \p_1_in__0\(2)
    );
\rd_byte_data_offset[0][15]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6AAA"
    )
        port map (
      I0 => \^rd_byte_data_offset_reg[0][15]_0\(0),
      I1 => \rd_byte_data_offset_reg_n_0_[0][13]\,
      I2 => \rd_byte_data_offset_reg_n_0_[0][12]\,
      I3 => \rd_byte_data_offset_reg_n_0_[0][14]\,
      O => \p_1_in__0\(3)
    );
\rd_byte_data_offset[0][16]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"6AAAAAAA"
    )
        port map (
      I0 => \rd_byte_data_offset_reg_n_0_[0][16]\,
      I1 => \^rd_byte_data_offset_reg[0][15]_0\(0),
      I2 => \rd_byte_data_offset_reg_n_0_[0][14]\,
      I3 => \rd_byte_data_offset_reg_n_0_[0][12]\,
      I4 => \rd_byte_data_offset_reg_n_0_[0][13]\,
      O => \p_1_in__0\(4)
    );
\rd_byte_data_offset[0][17]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAAAAAAAFFAE"
    )
        port map (
      I0 => init_dqsfound_done_r_reg_0,
      I1 => rank_done_r1,
      I2 => rd_data_offset_cal_done,
      I3 => \rd_byte_data_offset[0][17]_i_4_n_0\,
      I4 => \rnk_cnt_r_reg_n_0_[0]\,
      I5 => \rnk_cnt_r_reg_n_0_[1]\,
      O => \rd_byte_data_offset[0][17]_i_1_n_0\
    );
\rd_byte_data_offset[0][17]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000000001"
    )
        port map (
      I0 => \rd_byte_data_offset[0][17]_i_4_n_0\,
      I1 => rank_done_r1,
      I2 => pi_dqs_found_all_bank(2),
      I3 => rd_data_offset_cal_done,
      I4 => \^fine_adjust_reg_0\,
      I5 => \rd_byte_data_offset[0][11]_i_5_n_0\,
      O => \rd_byte_data_offset[0][17]_i_2_n_0\
    );
\rd_byte_data_offset[0][17]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"6AAAAAAAAAAAAAAA"
    )
        port map (
      I0 => \rd_byte_data_offset_reg_n_0_[0][17]\,
      I1 => \rd_byte_data_offset_reg_n_0_[0][13]\,
      I2 => \rd_byte_data_offset_reg_n_0_[0][12]\,
      I3 => \rd_byte_data_offset_reg_n_0_[0][14]\,
      I4 => \^rd_byte_data_offset_reg[0][15]_0\(0),
      I5 => \rd_byte_data_offset_reg_n_0_[0][16]\,
      O => \p_1_in__0\(5)
    );
\rd_byte_data_offset[0][17]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFEEEAAAAAAAA"
    )
        port map (
      I0 => \rd_byte_data_offset_reg_n_0_[0][17]\,
      I1 => \^rd_byte_data_offset_reg[0][15]_0\(0),
      I2 => \rd_byte_data_offset_reg_n_0_[0][13]\,
      I3 => \rd_byte_data_offset_reg_n_0_[0][12]\,
      I4 => \rd_byte_data_offset_reg_n_0_[0][14]\,
      I5 => \rd_byte_data_offset_reg_n_0_[0][16]\,
      O => \rd_byte_data_offset[0][17]_i_4_n_0\
    );
\rd_byte_data_offset[0][1]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \rd_byte_data_offset_reg_n_0_[0][1]\,
      I1 => \rd_byte_data_offset_reg_n_0_[0][0]\,
      O => \rd_byte_data_offset[0][1]_i_1_n_0\
    );
\rd_byte_data_offset[0][2]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"6A"
    )
        port map (
      I0 => \rd_byte_data_offset_reg_n_0_[0][2]\,
      I1 => \rd_byte_data_offset_reg_n_0_[0][0]\,
      I2 => \rd_byte_data_offset_reg_n_0_[0][1]\,
      O => \p_1_in__1\(2)
    );
\rd_byte_data_offset[0][3]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6AAA"
    )
        port map (
      I0 => \^q\(0),
      I1 => \rd_byte_data_offset_reg_n_0_[0][1]\,
      I2 => \rd_byte_data_offset_reg_n_0_[0][0]\,
      I3 => \rd_byte_data_offset_reg_n_0_[0][2]\,
      O => \p_1_in__1\(3)
    );
\rd_byte_data_offset[0][4]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"6AAAAAAA"
    )
        port map (
      I0 => \rd_byte_data_offset_reg_n_0_[0][4]\,
      I1 => \^q\(0),
      I2 => \rd_byte_data_offset_reg_n_0_[0][2]\,
      I3 => \rd_byte_data_offset_reg_n_0_[0][0]\,
      I4 => \rd_byte_data_offset_reg_n_0_[0][1]\,
      O => \p_1_in__1\(4)
    );
\rd_byte_data_offset[0][5]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAAAAAAAFFAE"
    )
        port map (
      I0 => init_dqsfound_done_r_reg_0,
      I1 => rank_done_r1,
      I2 => rd_data_offset_cal_done,
      I3 => \rd_byte_data_offset[0][5]_i_4_n_0\,
      I4 => \rnk_cnt_r_reg_n_0_[0]\,
      I5 => \rnk_cnt_r_reg_n_0_[1]\,
      O => \rd_byte_data_offset[0][5]_i_1_n_0\
    );
\rd_byte_data_offset[0][5]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000000001"
    )
        port map (
      I0 => \rd_byte_data_offset[0][5]_i_4_n_0\,
      I1 => rank_done_r1,
      I2 => pi_dqs_found_all_bank(0),
      I3 => rd_data_offset_cal_done,
      I4 => \^fine_adjust_reg_0\,
      I5 => \rd_byte_data_offset[0][11]_i_5_n_0\,
      O => rd_byte_data_offset
    );
\rd_byte_data_offset[0][5]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"6AAAAAAAAAAAAAAA"
    )
        port map (
      I0 => \rd_byte_data_offset_reg_n_0_[0][5]\,
      I1 => \rd_byte_data_offset_reg_n_0_[0][1]\,
      I2 => \rd_byte_data_offset_reg_n_0_[0][0]\,
      I3 => \rd_byte_data_offset_reg_n_0_[0][2]\,
      I4 => \^q\(0),
      I5 => \rd_byte_data_offset_reg_n_0_[0][4]\,
      O => \p_1_in__1\(5)
    );
\rd_byte_data_offset[0][5]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFEEEAAAAAAAA"
    )
        port map (
      I0 => \rd_byte_data_offset_reg_n_0_[0][5]\,
      I1 => \^q\(0),
      I2 => \rd_byte_data_offset_reg_n_0_[0][1]\,
      I3 => \rd_byte_data_offset_reg_n_0_[0][0]\,
      I4 => \rd_byte_data_offset_reg_n_0_[0][2]\,
      I5 => \rd_byte_data_offset_reg_n_0_[0][4]\,
      O => \rd_byte_data_offset[0][5]_i_4_n_0\
    );
\rd_byte_data_offset[0][6]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \rd_byte_data_offset_reg_n_0_[0][6]\,
      O => p_1_in(0)
    );
\rd_byte_data_offset[0][7]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \rd_byte_data_offset_reg_n_0_[0][6]\,
      I1 => \rd_byte_data_offset_reg_n_0_[0][7]\,
      O => p_1_in(1)
    );
\rd_byte_data_offset[0][8]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"6A"
    )
        port map (
      I0 => \rd_byte_data_offset_reg_n_0_[0][8]\,
      I1 => \rd_byte_data_offset_reg_n_0_[0][7]\,
      I2 => \rd_byte_data_offset_reg_n_0_[0][6]\,
      O => p_1_in(2)
    );
\rd_byte_data_offset[0][9]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6AAA"
    )
        port map (
      I0 => \^rd_byte_data_offset_reg[0][9]_0\(0),
      I1 => \rd_byte_data_offset_reg_n_0_[0][6]\,
      I2 => \rd_byte_data_offset_reg_n_0_[0][7]\,
      I3 => \rd_byte_data_offset_reg_n_0_[0][8]\,
      O => p_1_in(3)
    );
\rd_byte_data_offset_reg[0][0]\: unisim.vcomponents.FDRE
     port map (
      C => init_dqsfound_done_r5_reg_0,
      CE => rd_byte_data_offset,
      D => \rank_final_loop[0].bank_final_loop[0].final_data_offset_mc[0][0]_i_1_n_0\,
      Q => \rd_byte_data_offset_reg_n_0_[0][0]\,
      R => \rd_byte_data_offset[0][5]_i_1_n_0\
    );
\rd_byte_data_offset_reg[0][10]\: unisim.vcomponents.FDRE
     port map (
      C => init_dqsfound_done_r5_reg_0,
      CE => \rd_byte_data_offset[0][11]_i_2_n_0\,
      D => p_1_in(4),
      Q => \rd_byte_data_offset_reg_n_0_[0][10]\,
      R => \rd_byte_data_offset[0][11]_i_1_n_0\
    );
\rd_byte_data_offset_reg[0][11]\: unisim.vcomponents.FDRE
     port map (
      C => init_dqsfound_done_r5_reg_0,
      CE => \rd_byte_data_offset[0][11]_i_2_n_0\,
      D => p_1_in(5),
      Q => \rd_byte_data_offset_reg_n_0_[0][11]\,
      R => \rd_byte_data_offset[0][11]_i_1_n_0\
    );
\rd_byte_data_offset_reg[0][12]\: unisim.vcomponents.FDRE
     port map (
      C => init_dqsfound_done_r5_reg_0,
      CE => \rd_byte_data_offset[0][17]_i_2_n_0\,
      D => \rank_final_loop[0].bank_final_loop[2].final_data_offset_mc[0][12]_i_1_n_0\,
      Q => \rd_byte_data_offset_reg_n_0_[0][12]\,
      R => \rd_byte_data_offset[0][17]_i_1_n_0\
    );
\rd_byte_data_offset_reg[0][13]\: unisim.vcomponents.FDRE
     port map (
      C => init_dqsfound_done_r5_reg_0,
      CE => \rd_byte_data_offset[0][17]_i_2_n_0\,
      D => \rd_byte_data_offset[0][13]_i_1_n_0\,
      Q => \rd_byte_data_offset_reg_n_0_[0][13]\,
      R => \rd_byte_data_offset[0][17]_i_1_n_0\
    );
\rd_byte_data_offset_reg[0][14]\: unisim.vcomponents.FDSE
     port map (
      C => init_dqsfound_done_r5_reg_0,
      CE => \rd_byte_data_offset[0][17]_i_2_n_0\,
      D => \p_1_in__0\(2),
      Q => \rd_byte_data_offset_reg_n_0_[0][14]\,
      S => \rd_byte_data_offset[0][17]_i_1_n_0\
    );
\rd_byte_data_offset_reg[0][15]\: unisim.vcomponents.FDRE
     port map (
      C => init_dqsfound_done_r5_reg_0,
      CE => \rd_byte_data_offset[0][17]_i_2_n_0\,
      D => \p_1_in__0\(3),
      Q => \^rd_byte_data_offset_reg[0][15]_0\(0),
      R => \rd_byte_data_offset[0][17]_i_1_n_0\
    );
\rd_byte_data_offset_reg[0][16]\: unisim.vcomponents.FDRE
     port map (
      C => init_dqsfound_done_r5_reg_0,
      CE => \rd_byte_data_offset[0][17]_i_2_n_0\,
      D => \p_1_in__0\(4),
      Q => \rd_byte_data_offset_reg_n_0_[0][16]\,
      R => \rd_byte_data_offset[0][17]_i_1_n_0\
    );
\rd_byte_data_offset_reg[0][17]\: unisim.vcomponents.FDRE
     port map (
      C => init_dqsfound_done_r5_reg_0,
      CE => \rd_byte_data_offset[0][17]_i_2_n_0\,
      D => \p_1_in__0\(5),
      Q => \rd_byte_data_offset_reg_n_0_[0][17]\,
      R => \rd_byte_data_offset[0][17]_i_1_n_0\
    );
\rd_byte_data_offset_reg[0][1]\: unisim.vcomponents.FDRE
     port map (
      C => init_dqsfound_done_r5_reg_0,
      CE => rd_byte_data_offset,
      D => \rd_byte_data_offset[0][1]_i_1_n_0\,
      Q => \rd_byte_data_offset_reg_n_0_[0][1]\,
      R => \rd_byte_data_offset[0][5]_i_1_n_0\
    );
\rd_byte_data_offset_reg[0][2]\: unisim.vcomponents.FDSE
     port map (
      C => init_dqsfound_done_r5_reg_0,
      CE => rd_byte_data_offset,
      D => \p_1_in__1\(2),
      Q => \rd_byte_data_offset_reg_n_0_[0][2]\,
      S => \rd_byte_data_offset[0][5]_i_1_n_0\
    );
\rd_byte_data_offset_reg[0][3]\: unisim.vcomponents.FDRE
     port map (
      C => init_dqsfound_done_r5_reg_0,
      CE => rd_byte_data_offset,
      D => \p_1_in__1\(3),
      Q => \^q\(0),
      R => \rd_byte_data_offset[0][5]_i_1_n_0\
    );
\rd_byte_data_offset_reg[0][4]\: unisim.vcomponents.FDRE
     port map (
      C => init_dqsfound_done_r5_reg_0,
      CE => rd_byte_data_offset,
      D => \p_1_in__1\(4),
      Q => \rd_byte_data_offset_reg_n_0_[0][4]\,
      R => \rd_byte_data_offset[0][5]_i_1_n_0\
    );
\rd_byte_data_offset_reg[0][5]\: unisim.vcomponents.FDRE
     port map (
      C => init_dqsfound_done_r5_reg_0,
      CE => rd_byte_data_offset,
      D => \p_1_in__1\(5),
      Q => \rd_byte_data_offset_reg_n_0_[0][5]\,
      R => \rd_byte_data_offset[0][5]_i_1_n_0\
    );
\rd_byte_data_offset_reg[0][6]\: unisim.vcomponents.FDRE
     port map (
      C => init_dqsfound_done_r5_reg_0,
      CE => \rd_byte_data_offset[0][11]_i_2_n_0\,
      D => p_1_in(0),
      Q => \rd_byte_data_offset_reg_n_0_[0][6]\,
      R => \rd_byte_data_offset[0][11]_i_1_n_0\
    );
\rd_byte_data_offset_reg[0][7]\: unisim.vcomponents.FDRE
     port map (
      C => init_dqsfound_done_r5_reg_0,
      CE => \rd_byte_data_offset[0][11]_i_2_n_0\,
      D => p_1_in(1),
      Q => \rd_byte_data_offset_reg_n_0_[0][7]\,
      R => \rd_byte_data_offset[0][11]_i_1_n_0\
    );
\rd_byte_data_offset_reg[0][8]\: unisim.vcomponents.FDSE
     port map (
      C => init_dqsfound_done_r5_reg_0,
      CE => \rd_byte_data_offset[0][11]_i_2_n_0\,
      D => p_1_in(2),
      Q => \rd_byte_data_offset_reg_n_0_[0][8]\,
      S => \rd_byte_data_offset[0][11]_i_1_n_0\
    );
\rd_byte_data_offset_reg[0][9]\: unisim.vcomponents.FDRE
     port map (
      C => init_dqsfound_done_r5_reg_0,
      CE => \rd_byte_data_offset[0][11]_i_2_n_0\,
      D => p_1_in(3),
      Q => \^rd_byte_data_offset_reg[0][9]_0\(0),
      R => \rd_byte_data_offset[0][11]_i_1_n_0\
    );
\rnk_cnt_r[0]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"D2"
    )
        port map (
      I0 => \^pi_dqs_found_rank_done\,
      I1 => rd_data_offset_cal_done,
      I2 => \rnk_cnt_r_reg_n_0_[0]\,
      O => \rnk_cnt_r[0]_i_1_n_0\
    );
\rnk_cnt_r[1]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F708"
    )
        port map (
      I0 => \rnk_cnt_r_reg_n_0_[0]\,
      I1 => \^pi_dqs_found_rank_done\,
      I2 => rd_data_offset_cal_done,
      I3 => \rnk_cnt_r_reg_n_0_[1]\,
      O => \rnk_cnt_r[1]_i_1_n_0\
    );
\rnk_cnt_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => init_dqsfound_done_r5_reg_0,
      CE => '1',
      D => \rnk_cnt_r[0]_i_1_n_0\,
      Q => \rnk_cnt_r_reg_n_0_[0]\,
      R => \pi_dqs_found_any_bank_reg[0]_0\(1)
    );
\rnk_cnt_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => init_dqsfound_done_r5_reg_0,
      CE => '1',
      D => \rnk_cnt_r[1]_i_1_n_0\,
      Q => \rnk_cnt_r_reg_n_0_[1]\,
      R => \pi_dqs_found_any_bank_reg[0]_0\(1)
    );
rst_dqs_find_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"80AAFFFF80AA0000"
    )
        port map (
      I0 => rst_dqs_find_i_2_n_0,
      I1 => fine_adj_state_r(1),
      I2 => prech_done,
      I3 => fine_adj_state_r(0),
      I4 => rst_dqs_find_i_3_n_0,
      I5 => rst_dqs_find,
      O => rst_dqs_find_i_1_n_0
    );
rst_dqs_find_i_2: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FEEEFEFFEEEEEEEE"
    )
        port map (
      I0 => rst_dqs_find_i_4_n_0,
      I1 => fine_adj_state_r(2),
      I2 => \FSM_sequential_fine_adj_state_r[1]_i_14_n_0\,
      I3 => \FSM_sequential_fine_adj_state_r[1]_i_5_n_0\,
      I4 => \first_fail_taps[5]_i_5_n_0\,
      I5 => fine_adj_state_r(3),
      O => rst_dqs_find_i_2_n_0
    );
rst_dqs_find_i_3: unisim.vcomponents.LUT6
    generic map(
      INIT => X"008000800A8A0282"
    )
        port map (
      I0 => rst_dqs_find_i_5_n_0,
      I1 => fine_adj_state_r(1),
      I2 => fine_adj_state_r(3),
      I3 => rst_dqs_find_i_6_n_0,
      I4 => p_1_in30_in,
      I5 => fine_adj_state_r(2),
      O => rst_dqs_find_i_3_n_0
    );
rst_dqs_find_i_4: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => init_dqsfound_done_r5,
      I1 => fine_adj_state_r(1),
      O => rst_dqs_find_i_4_n_0
    );
rst_dqs_find_i_5: unisim.vcomponents.LUT6
    generic map(
      INIT => X"88FFFFF88888FFF8"
    )
        port map (
      I0 => prech_done,
      I1 => fine_adj_state_r(2),
      I2 => init_dqsfound_done_r5,
      I3 => fine_adj_state_r(1),
      I4 => fine_adj_state_r(0),
      I5 => \FSM_sequential_fine_adj_state_r[3]_i_6_n_0\,
      O => rst_dqs_find_i_5_n_0
    );
rst_dqs_find_i_6: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000FFFFFFAB"
    )
        port map (
      I0 => \dec_cnt[5]_i_6_n_0\,
      I1 => first_fail_detect_reg_n_0,
      I2 => \FSM_sequential_fine_adj_state_r[1]_i_14_n_0\,
      I3 => \FSM_sequential_fine_adj_state_r[1]_i_5_n_0\,
      I4 => \first_fail_taps[5]_i_5_n_0\,
      I5 => rst_dqs_find_i_7_n_0,
      O => rst_dqs_find_i_6_n_0
    );
rst_dqs_find_i_7: unisim.vcomponents.LUT5
    generic map(
      INIT => X"EAAAAAAA"
    )
        port map (
      I0 => fine_adj_state_r(2),
      I1 => p_1_in30_in,
      I2 => detect_pi_found_dqs,
      I3 => \FSM_sequential_fine_adj_state_r[1]_i_14_n_0\,
      I4 => \FSM_sequential_fine_adj_state_r[2]_i_3_n_0\,
      O => rst_dqs_find_i_7_n_0
    );
rst_dqs_find_r1_reg: unisim.vcomponents.FDRE
     port map (
      C => init_dqsfound_done_r5_reg_0,
      CE => '1',
      D => rst_dqs_find,
      Q => rst_dqs_find_r1,
      R => '0'
    );
rst_dqs_find_r2_reg: unisim.vcomponents.FDRE
     port map (
      C => init_dqsfound_done_r5_reg_0,
      CE => '1',
      D => rst_dqs_find_r1,
      Q => rst_dqs_find_r2,
      R => '0'
    );
rst_dqs_find_reg: unisim.vcomponents.FDRE
     port map (
      C => init_dqsfound_done_r5_reg_0,
      CE => '1',
      D => rst_dqs_find_i_1_n_0,
      Q => rst_dqs_find,
      R => \pi_dqs_found_any_bank_reg[0]_0\(1)
    );
\stable_pass_cnt[0]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0080"
    )
        port map (
      I0 => pi_dqs_found_all_bank(2),
      I1 => pi_dqs_found_all_bank(1),
      I2 => pi_dqs_found_all_bank(0),
      I3 => \stable_pass_cnt_reg_n_0_[0]\,
      O => \p_0_in__0\(0)
    );
\stable_pass_cnt[1]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00808000"
    )
        port map (
      I0 => pi_dqs_found_all_bank(2),
      I1 => pi_dqs_found_all_bank(1),
      I2 => pi_dqs_found_all_bank(0),
      I3 => stable_pass_cnt_reg(1),
      I4 => \stable_pass_cnt_reg_n_0_[0]\,
      O => \p_0_in__0\(1)
    );
\stable_pass_cnt[2]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2A80"
    )
        port map (
      I0 => \FSM_sequential_fine_adj_state_r[1]_i_5_n_0\,
      I1 => \stable_pass_cnt_reg_n_0_[0]\,
      I2 => stable_pass_cnt_reg(1),
      I3 => stable_pass_cnt_reg(2),
      O => \p_0_in__0\(2)
    );
\stable_pass_cnt[3]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"2AAA8000"
    )
        port map (
      I0 => \FSM_sequential_fine_adj_state_r[1]_i_5_n_0\,
      I1 => stable_pass_cnt_reg(1),
      I2 => \stable_pass_cnt_reg_n_0_[0]\,
      I3 => stable_pass_cnt_reg(2),
      I4 => stable_pass_cnt_reg(3),
      O => \p_0_in__0\(3)
    );
\stable_pass_cnt[4]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"2AAAAAAA80000000"
    )
        port map (
      I0 => \FSM_sequential_fine_adj_state_r[1]_i_5_n_0\,
      I1 => stable_pass_cnt_reg(1),
      I2 => \stable_pass_cnt_reg_n_0_[0]\,
      I3 => stable_pass_cnt_reg(3),
      I4 => stable_pass_cnt_reg(2),
      I5 => stable_pass_cnt_reg(4),
      O => \p_0_in__0\(4)
    );
\stable_pass_cnt[5]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000800"
    )
        port map (
      I0 => detect_pi_found_dqs,
      I1 => fine_adj_state_r(3),
      I2 => fine_adj_state_r(2),
      I3 => fine_adj_state_r(1),
      I4 => fine_adj_state_r(0),
      O => stable_pass_cnt
    );
\stable_pass_cnt[5]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"2AAAAAAA80000000"
    )
        port map (
      I0 => \FSM_sequential_fine_adj_state_r[1]_i_5_n_0\,
      I1 => stable_pass_cnt_reg(2),
      I2 => stable_pass_cnt_reg(3),
      I3 => \stable_pass_cnt[5]_i_3_n_0\,
      I4 => stable_pass_cnt_reg(4),
      I5 => stable_pass_cnt_reg(5),
      O => \p_0_in__0\(5)
    );
\stable_pass_cnt[5]_i_3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stable_pass_cnt_reg_n_0_[0]\,
      I1 => stable_pass_cnt_reg(1),
      O => \stable_pass_cnt[5]_i_3_n_0\
    );
\stable_pass_cnt_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => init_dqsfound_done_r5_reg_0,
      CE => stable_pass_cnt,
      D => \p_0_in__0\(0),
      Q => \stable_pass_cnt_reg_n_0_[0]\,
      R => \stable_pass_cnt_reg[0]_0\
    );
\stable_pass_cnt_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => init_dqsfound_done_r5_reg_0,
      CE => stable_pass_cnt,
      D => \p_0_in__0\(1),
      Q => stable_pass_cnt_reg(1),
      R => \stable_pass_cnt_reg[0]_0\
    );
\stable_pass_cnt_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => init_dqsfound_done_r5_reg_0,
      CE => stable_pass_cnt,
      D => \p_0_in__0\(2),
      Q => stable_pass_cnt_reg(2),
      R => \stable_pass_cnt_reg[0]_0\
    );
\stable_pass_cnt_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => init_dqsfound_done_r5_reg_0,
      CE => stable_pass_cnt,
      D => \p_0_in__0\(3),
      Q => stable_pass_cnt_reg(3),
      R => \stable_pass_cnt_reg[0]_0\
    );
\stable_pass_cnt_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => init_dqsfound_done_r5_reg_0,
      CE => stable_pass_cnt,
      D => \p_0_in__0\(4),
      Q => stable_pass_cnt_reg(4),
      R => \stable_pass_cnt_reg[0]_0\
    );
\stable_pass_cnt_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => init_dqsfound_done_r5_reg_0,
      CE => stable_pass_cnt,
      D => \p_0_in__0\(5),
      Q => stable_pass_cnt_reg(5),
      R => \stable_pass_cnt_reg[0]_0\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mig_mig_7series_v4_2_ddr_phy_init is
  port (
    prech_done : out STD_LOGIC;
    wrlvl_done_r1 : out STD_LOGIC;
    prbs_rdlvl_done_pulse_reg_0 : out STD_LOGIC;
    prech_req_posedge_r_reg_0 : out STD_LOGIC;
    pi_calib_done : out STD_LOGIC;
    complex_ocal_reset_rd_addr : out STD_LOGIC;
    wl_sm_start : out STD_LOGIC;
    wrcal_rd_wait : out STD_LOGIC;
    wrcal_sanity_chk : out STD_LOGIC;
    detect_pi_found_dqs : out STD_LOGIC;
    calib_complete : out STD_LOGIC;
    pi_dqs_found_done_r1 : out STD_LOGIC;
    complex_act_start : out STD_LOGIC;
    \one_rank.stg1_wr_done_reg_0\ : out STD_LOGIC;
    wrlvl_final_if_rst : out STD_LOGIC;
    wr_lvl_start_reg_0 : out STD_LOGIC;
    rdlvl_stg1_start_reg_0 : out STD_LOGIC;
    phy_write_calib : out STD_LOGIC;
    phy_read_calib : out STD_LOGIC;
    first_rdlvl_pat_r : out STD_LOGIC;
    first_wrcal_pat_r : out STD_LOGIC;
    D : out STD_LOGIC_VECTOR ( 7 downto 0 );
    Q : out STD_LOGIC_VECTOR ( 0 to 0 );
    d_in : out STD_LOGIC_VECTOR ( 35 downto 0 );
    phy_dout : out STD_LOGIC_VECTOR ( 23 downto 0 );
    init_complete_r1_timing_reg_0 : out STD_LOGIC;
    D6 : out STD_LOGIC_VECTOR ( 7 downto 0 );
    D8 : out STD_LOGIC_VECTOR ( 3 downto 0 );
    \gen_no_mirror.div_clk_loop[0].phy_address_reg[2]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
    D5 : out STD_LOGIC_VECTOR ( 3 downto 0 );
    D4 : out STD_LOGIC_VECTOR ( 3 downto 0 );
    D7 : out STD_LOGIC_VECTOR ( 3 downto 0 );
    D9 : out STD_LOGIC_VECTOR ( 3 downto 0 );
    D1 : out STD_LOGIC_VECTOR ( 3 downto 0 );
    \gen_no_mirror.div_clk_loop[0].phy_address_reg[8]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
    \gen_no_mirror.div_clk_loop[0].phy_address_reg[9]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
    D3 : out STD_LOGIC_VECTOR ( 3 downto 0 );
    \gen_no_mirror.div_clk_loop[0].phy_bank_reg[0]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
    \gen_no_mirror.div_clk_loop[0].phy_bank_reg[1]_0\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
    \write_buffer.wr_buf_out_data_reg[448]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
    D2 : out STD_LOGIC_VECTOR ( 7 downto 0 );
    \write_buffer.wr_buf_out_data_reg[450]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
    \write_buffer.wr_buf_out_data_reg[451]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
    \write_buffer.wr_buf_out_data_reg[452]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
    \write_buffer.wr_buf_out_data_reg[453]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
    \write_buffer.wr_buf_out_data_reg[454]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
    \write_buffer.wr_buf_out_data_reg[455]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
    \write_buffer.wr_buf_out_data_reg[456]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
    \write_buffer.wr_buf_out_data_reg[457]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
    \write_buffer.wr_buf_out_data_reg[458]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
    \write_buffer.wr_buf_out_data_reg[459]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
    \write_buffer.wr_buf_out_data_reg[460]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
    \write_buffer.wr_buf_out_data_reg[461]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
    \write_buffer.wr_buf_out_data_reg[462]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
    \write_buffer.wr_buf_out_data_reg[463]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
    \write_buffer.wr_buf_out_data_reg[464]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
    \write_buffer.wr_buf_out_data_reg[465]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
    \write_buffer.wr_buf_out_data_reg[466]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
    \write_buffer.wr_buf_out_data_reg[467]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
    \write_buffer.wr_buf_out_data_reg[468]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
    \write_buffer.wr_buf_out_data_reg[469]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
    \write_buffer.wr_buf_out_data_reg[470]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
    \write_buffer.wr_buf_out_data_reg[471]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
    \write_buffer.wr_buf_out_data_reg[472]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
    \write_buffer.wr_buf_out_data_reg[473]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
    \write_buffer.wr_buf_out_data_reg[474]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
    \write_buffer.wr_buf_out_data_reg[475]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
    \write_buffer.wr_buf_out_data_reg[476]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
    \write_buffer.wr_buf_out_data_reg[477]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
    \write_buffer.wr_buf_out_data_reg[478]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
    \write_buffer.wr_buf_out_data_reg[479]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
    \write_buffer.wr_buf_out_data_reg[480]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
    \write_buffer.wr_buf_out_data_reg[481]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
    \write_buffer.wr_buf_out_data_reg[482]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
    \write_buffer.wr_buf_out_data_reg[483]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
    \write_buffer.wr_buf_out_data_reg[484]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
    \write_buffer.wr_buf_out_data_reg[485]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
    \write_buffer.wr_buf_out_data_reg[486]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
    \write_buffer.wr_buf_out_data_reg[487]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
    \write_buffer.wr_buf_out_data_reg[488]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
    \write_buffer.wr_buf_out_data_reg[489]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
    \write_buffer.wr_buf_out_data_reg[490]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
    \write_buffer.wr_buf_out_data_reg[491]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
    \write_buffer.wr_buf_out_data_reg[492]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
    \write_buffer.wr_buf_out_data_reg[493]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
    \write_buffer.wr_buf_out_data_reg[494]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
    \write_buffer.wr_buf_out_data_reg[495]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
    \write_buffer.wr_buf_out_data_reg[496]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
    \write_buffer.wr_buf_out_data_reg[497]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
    \write_buffer.wr_buf_out_data_reg[498]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
    \write_buffer.wr_buf_out_data_reg[499]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
    \write_buffer.wr_buf_out_data_reg[500]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
    \write_buffer.wr_buf_out_data_reg[501]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
    \write_buffer.wr_buf_out_data_reg[502]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
    \write_buffer.wr_buf_out_data_reg[503]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
    \write_buffer.wr_buf_out_data_reg[504]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
    \write_buffer.wr_buf_out_data_reg[505]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
    \write_buffer.wr_buf_out_data_reg[506]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
    \write_buffer.wr_buf_out_data_reg[507]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
    \write_buffer.wr_buf_out_data_reg[508]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
    \write_buffer.wr_buf_out_data_reg[509]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
    \write_buffer.wr_buf_out_data_reg[510]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
    \write_buffer.wr_buf_out_data_reg[511]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
    \cmd_pipe_plus.mc_ras_n_reg[1]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \cmd_pipe_plus.mc_cas_n_reg[1]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    \cmd_pipe_plus.mc_odt_reg[0]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
    \cmd_pipe_plus.mc_cke_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
    \cmd_pipe_plus.mc_we_n_reg[1]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    app_rd_data_valid : out STD_LOGIC;
    \read_fifo.tail_r_reg[0]\ : out STD_LOGIC;
    wl_sm_start_reg_0 : out STD_LOGIC;
    mux_rd_valid_r0 : out STD_LOGIC;
    prbs_rdlvl_start_reg_0 : out STD_LOGIC;
    prbs_rdlvl_start_reg_1 : out STD_LOGIC;
    stg1_wr_done : out STD_LOGIC;
    \init_state_r_reg[4]_0\ : out STD_LOGIC;
    \init_state_r_reg[4]_1\ : out STD_LOGIC;
    rdlvl_stg1_start_int_reg_0 : out STD_LOGIC;
    E : out STD_LOGIC_VECTOR ( 0 to 0 );
    prbs_rdlvl_done_reg : out STD_LOGIC_VECTOR ( 0 to 0 );
    \rd_addr_reg[1]\ : out STD_LOGIC;
    prbs_rdlvl_done_reg_0 : out STD_LOGIC;
    SR : out STD_LOGIC_VECTOR ( 0 to 0 );
    phy_data_wr_en : out STD_LOGIC;
    phy_cmd_wr_en : out STD_LOGIC;
    mux_reset_n : out STD_LOGIC;
    \cmd_pipe_plus.mc_cke_reg[3]_0\ : out STD_LOGIC_VECTOR ( 5 downto 0 );
    wrcal_start_reg_0 : out STD_LOGIC;
    pi_dqs_found_start_reg_0 : out STD_LOGIC;
    mpr_rdlvl_start_reg_0 : out STD_LOGIC;
    \calib_seq_reg[1]_0\ : out STD_LOGIC_VECTOR ( 10 downto 0 );
    \cmd_pipe_plus.mc_data_offset_1_reg[5]\ : out STD_LOGIC_VECTOR ( 5 downto 0 );
    \cmd_pipe_plus.mc_data_offset_2_reg[5]\ : out STD_LOGIC_VECTOR ( 5 downto 0 );
    \write_buffer.wr_buf_out_data_reg[455]_0\ : out STD_LOGIC_VECTOR ( 63 downto 0 );
    \write_buffer.wr_buf_out_data_reg[463]_0\ : out STD_LOGIC_VECTOR ( 63 downto 0 );
    \write_buffer.wr_buf_out_data_reg[471]_0\ : out STD_LOGIC_VECTOR ( 63 downto 0 );
    \write_buffer.wr_buf_out_data_reg[479]_0\ : out STD_LOGIC_VECTOR ( 63 downto 0 );
    \write_buffer.wr_buf_out_data_reg[487]_0\ : out STD_LOGIC_VECTOR ( 63 downto 0 );
    \write_buffer.wr_buf_out_data_reg[495]_0\ : out STD_LOGIC_VECTOR ( 63 downto 0 );
    \write_buffer.wr_buf_out_data_reg[503]_0\ : out STD_LOGIC_VECTOR ( 63 downto 0 );
    \write_buffer.wr_buf_out_data_reg[511]_0\ : out STD_LOGIC_VECTOR ( 63 downto 0 );
    \rdlvl_start_dly0_r_reg[14]_0\ : in STD_LOGIC;
    pi_phase_locked_all_r1_reg_0 : in STD_LOGIC;
    \victim_sel_reg[0]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    wrlvl_done_r_reg_0 : in STD_LOGIC;
    prbs_last_byte_done : in STD_LOGIC;
    wrlvl_rank_done : in STD_LOGIC;
    prbs_rdlvl_done_pulse0 : in STD_LOGIC;
    \en_cnt_div4.enable_wrlvl_cnt_reg[2]_0\ : in STD_LOGIC;
    reset_rd_addr0 : in STD_LOGIC;
    prech_req : in STD_LOGIC;
    wrcal_resume_w : in STD_LOGIC;
    complex_oclkdelay_calib_done_r1_reg_0 : in STD_LOGIC;
    rdlvl_last_byte_done : in STD_LOGIC;
    pi_dqs_found_done_r1_reg_0 : in STD_LOGIC;
    \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[56]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[510]_0\ : in STD_LOGIC;
    \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[506]_0\ : in STD_LOGIC;
    \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[125]_0\ : in STD_LOGIC;
    \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[121]_0\ : in STD_LOGIC;
    \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[61]_0\ : in STD_LOGIC;
    \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[57]_0\ : in STD_LOGIC;
    \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[508]_0\ : in STD_LOGIC;
    prbs_out : in STD_LOGIC_VECTOR ( 19 downto 0 );
    \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[187]_0\ : in STD_LOGIC;
    \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[445]_0\ : in STD_LOGIC;
    \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[441]_0\ : in STD_LOGIC;
    \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[380]_0\ : in STD_LOGIC;
    \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[376]_0\ : in STD_LOGIC;
    \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[319]_0\ : in STD_LOGIC;
    \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[315]_0\ : in STD_LOGIC;
    \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[255]_0\ : in STD_LOGIC;
    \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[253]_0\ : in STD_LOGIC;
    \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[251]_0\ : in STD_LOGIC;
    \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[249]_0\ : in STD_LOGIC;
    \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[188]_0\ : in STD_LOGIC;
    \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[184]_0\ : in STD_LOGIC;
    \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[190]_0\ : in STD_LOGIC;
    \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[186]_0\ : in STD_LOGIC;
    \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[124]_0\ : in STD_LOGIC;
    \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[120]_0\ : in STD_LOGIC;
    \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[511]_0\ : in STD_LOGIC;
    \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[507]_0\ : in STD_LOGIC;
    \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[446]_0\ : in STD_LOGIC;
    \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[442]_0\ : in STD_LOGIC;
    \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[382]_0\ : in STD_LOGIC;
    \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[378]_0\ : in STD_LOGIC;
    \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[509]_0\ : in STD_LOGIC;
    \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[505]_0\ : in STD_LOGIC;
    \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[316]_0\ : in STD_LOGIC;
    \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[312]_0\ : in STD_LOGIC;
    \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[252]_0\ : in STD_LOGIC;
    \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[248]_0\ : in STD_LOGIC;
    \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[62]_0\ : in STD_LOGIC;
    \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[58]_0\ : in STD_LOGIC;
    \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[447]_0\ : in STD_LOGIC;
    \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[444]_0\ : in STD_LOGIC;
    \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[443]_0\ : in STD_LOGIC;
    \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[440]_0\ : in STD_LOGIC;
    \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[381]_0\ : in STD_LOGIC;
    \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[377]_0\ : in STD_LOGIC;
    \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[191]_0\ : in STD_LOGIC;
    \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[187]_1\ : in STD_LOGIC;
    \rd_addr_reg[7]\ : in STD_LOGIC;
    prbs_rdlvl_done_r1 : in STD_LOGIC;
    \init_state_r[0]_i_4_0\ : in STD_LOGIC;
    \complex_num_writes_reg[1]_0\ : in STD_LOGIC;
    pi_dqs_found_rank_done : in STD_LOGIC;
    complex_pi_incdec_done : in STD_LOGIC;
    rdlvl_stg1_done_r1 : in STD_LOGIC;
    write_calib_reg_0 : in STD_LOGIC;
    wrlvl_byte_redo : in STD_LOGIC;
    \phy_ctl_wd_i1_reg[0]\ : in STD_LOGIC;
    mem_reg_0_15_36_41 : in STD_LOGIC;
    if_empty : in STD_LOGIC;
    mc_address : in STD_LOGIC_VECTOR ( 34 downto 0 );
    phy_ctl_wr_i1_reg : in STD_LOGIC;
    mem_out : in STD_LOGIC_VECTOR ( 35 downto 0 );
    out_fifo : in STD_LOGIC;
    out_fifo_0 : in STD_LOGIC_VECTOR ( 23 downto 0 );
    out_fifo_1 : in STD_LOGIC;
    mc_ras_n : in STD_LOGIC_VECTOR ( 0 to 0 );
    out_fifo_2 : in STD_LOGIC;
    mc_bank : in STD_LOGIC_VECTOR ( 8 downto 0 );
    mem_reg_0_15_78_79 : in STD_LOGIC_VECTOR ( 511 downto 0 );
    out_fifo_3 : in STD_LOGIC_VECTOR ( 63 downto 0 );
    out_fifo_4 : in STD_LOGIC;
    out_fifo_5 : in STD_LOGIC_VECTOR ( 63 downto 0 );
    out_fifo_6 : in STD_LOGIC;
    out_fifo_7 : in STD_LOGIC_VECTOR ( 63 downto 0 );
    out_fifo_8 : in STD_LOGIC;
    out_fifo_9 : in STD_LOGIC_VECTOR ( 63 downto 0 );
    out_fifo_10 : in STD_LOGIC;
    out_fifo_11 : in STD_LOGIC;
    out_fifo_12 : in STD_LOGIC_VECTOR ( 63 downto 0 );
    out_fifo_13 : in STD_LOGIC;
    out_fifo_14 : in STD_LOGIC_VECTOR ( 63 downto 0 );
    out_fifo_15 : in STD_LOGIC;
    out_fifo_16 : in STD_LOGIC_VECTOR ( 63 downto 0 );
    out_fifo_17 : in STD_LOGIC;
    out_fifo_18 : in STD_LOGIC_VECTOR ( 63 downto 0 );
    out_fifo_19 : in STD_LOGIC;
    out_fifo_20 : in STD_LOGIC;
    out_fifo_21 : in STD_LOGIC;
    out_fifo_22 : in STD_LOGIC;
    out_fifo_23 : in STD_LOGIC;
    out_fifo_24 : in STD_LOGIC;
    out_fifo_25 : in STD_LOGIC;
    out_fifo_26 : in STD_LOGIC;
    out_fifo_27 : in STD_LOGIC;
    out_fifo_28 : in STD_LOGIC;
    mc_cas_n : in STD_LOGIC_VECTOR ( 0 to 0 );
    out_fifo_29 : in STD_LOGIC_VECTOR ( 11 downto 0 );
    out_fifo_30 : in STD_LOGIC;
    mc_odt : in STD_LOGIC_VECTOR ( 0 to 0 );
    out_fifo_31 : in STD_LOGIC;
    mc_cke : in STD_LOGIC_VECTOR ( 0 to 0 );
    mc_we_n : in STD_LOGIC_VECTOR ( 0 to 0 );
    app_rd_data_valid_0 : in STD_LOGIC_VECTOR ( 0 to 0 );
    \read_fifo.tail_r\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    wr_level_done_r5 : in STD_LOGIC;
    prbs_rdlvl_start_r : in STD_LOGIC;
    \calib_data_offset_0_reg[3]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    init_dqsfound_done_r2 : in STD_LOGIC;
    \calib_data_offset_0_reg[3]_1\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \calib_data_offset_1_reg[3]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \calib_data_offset_1_reg[3]_1\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \calib_data_offset_2_reg[3]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \calib_data_offset_2_reg[3]_1\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    ddr3_lm_done_r_reg_0 : in STD_LOGIC;
    ck_addr_cmd_delay_done : in STD_LOGIC;
    \calib_seq_reg[0]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \gen_no_mirror.div_clk_loop[0].phy_address_reg[10]_0\ : in STD_LOGIC;
    rdlvl_pi_incdec : in STD_LOGIC;
    prbs_rdlvl_start_reg_2 : in STD_LOGIC;
    \rd_addr_reg[7]_0\ : in STD_LOGIC;
    done_dqs_tap_inc : in STD_LOGIC;
    \stg1_wr_rd_cnt_reg[3]_0\ : in STD_LOGIC;
    prech_req_posedge_r_reg_1 : in STD_LOGIC;
    dqs_found_prech_req : in STD_LOGIC;
    rdlvl_stg1_rank_done : in STD_LOGIC;
    rdlvl_prech_req : in STD_LOGIC;
    wrcal_prech_req : in STD_LOGIC;
    \init_state_r[2]_i_4_0\ : in STD_LOGIC;
    \init_state_r[0]_i_14_0\ : in STD_LOGIC;
    num_samples_done_r : in STD_LOGIC;
    \init_state_r[4]_i_17_0\ : in STD_LOGIC;
    \row_cnt_victim_rotate.complex_row_cnt_reg[6]_0\ : in STD_LOGIC;
    \init_state_r[1]_i_6_0\ : in STD_LOGIC;
    \init_state_r[2]_i_3_0\ : in STD_LOGIC;
    reset_rd_addr : in STD_LOGIC;
    \row_cnt_victim_rotate.complex_row_cnt_reg[1]_0\ : in STD_LOGIC;
    \row_cnt_victim_rotate.complex_row_cnt_reg[2]_0\ : in STD_LOGIC;
    \row_cnt_victim_rotate.complex_row_cnt_reg[3]_0\ : in STD_LOGIC;
    \init_state_r[4]_i_10_0\ : in STD_LOGIC;
    \init_state_r[3]_i_4_0\ : in STD_LOGIC;
    \init_state_r[0]_i_4_1\ : in STD_LOGIC;
    \samples_cnt_r_reg[11]\ : in STD_LOGIC;
    \rd_addr_reg[3]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    mc_wrdata_en : in STD_LOGIC;
    \en_cnt_div4.enable_wrlvl_cnt_reg[4]_0\ : in STD_LOGIC;
    \calib_data_offset_0_reg[5]_0\ : in STD_LOGIC;
    \calib_data_offset_0_reg[4]_0\ : in STD_LOGIC;
    \calib_data_offset_0_reg[2]_0\ : in STD_LOGIC;
    \calib_data_offset_0_reg[1]_0\ : in STD_LOGIC;
    \calib_data_offset_0_reg[0]_0\ : in STD_LOGIC;
    \calib_data_offset_1_reg[5]_0\ : in STD_LOGIC;
    \calib_data_offset_1_reg[4]_0\ : in STD_LOGIC;
    \calib_data_offset_1_reg[2]_0\ : in STD_LOGIC;
    \calib_data_offset_1_reg[1]_0\ : in STD_LOGIC;
    \calib_data_offset_1_reg[0]_0\ : in STD_LOGIC;
    \calib_data_offset_2_reg[5]_0\ : in STD_LOGIC;
    \calib_data_offset_2_reg[4]_0\ : in STD_LOGIC;
    \calib_data_offset_2_reg[2]_0\ : in STD_LOGIC;
    \calib_data_offset_2_reg[1]_0\ : in STD_LOGIC;
    \calib_data_offset_2_reg[0]_0\ : in STD_LOGIC;
    \cnt_pwron_ce_r_reg[0]_0\ : in STD_LOGIC;
    \data_offset_1_i1_reg[0]\ : in STD_LOGIC;
    \data_offset_1_i1_reg[1]\ : in STD_LOGIC;
    \data_offset_1_i1_reg[2]\ : in STD_LOGIC;
    mc_data_offset_1 : in STD_LOGIC_VECTOR ( 0 to 0 );
    \data_offset_1_i1_reg[4]\ : in STD_LOGIC;
    \data_offset_1_i1_reg[5]\ : in STD_LOGIC;
    \data_offset_2_i1_reg[0]\ : in STD_LOGIC;
    \data_offset_2_i1_reg[1]\ : in STD_LOGIC;
    \data_offset_2_i1_reg[2]\ : in STD_LOGIC;
    mc_data_offset_2 : in STD_LOGIC_VECTOR ( 0 to 0 );
    \data_offset_2_i1_reg[4]\ : in STD_LOGIC;
    \data_offset_2_i1_reg[5]\ : in STD_LOGIC;
    mc_cmd : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \phy_ctl_wd_i1_reg[17]\ : in STD_LOGIC;
    \phy_ctl_wd_i1_reg[18]\ : in STD_LOGIC;
    \phy_ctl_wd_i1_reg[19]\ : in STD_LOGIC;
    mc_data_offset : in STD_LOGIC_VECTOR ( 0 to 0 );
    \phy_ctl_wd_i1_reg[21]\ : in STD_LOGIC;
    \phy_ctl_wd_i1_reg[22]\ : in STD_LOGIC;
    mem_reg_0_15_48_53 : in STD_LOGIC;
    mem_reg_0_15_54_59 : in STD_LOGIC;
    mem_reg_0_15_66_71 : in STD_LOGIC;
    mem_reg_0_15_72_77 : in STD_LOGIC;
    mem_reg_0_15_18_23 : in STD_LOGIC;
    mem_reg_0_15_18_23_0 : in STD_LOGIC;
    mem_reg_0_15_36_41_0 : in STD_LOGIC;
    mem_reg_0_15_36_41_1 : in STD_LOGIC;
    mem_reg_0_15_54_59_0 : in STD_LOGIC;
    mem_reg_0_15_78_79_0 : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of mig_mig_7series_v4_2_ddr_phy_init : entity is "mig_7series_v4_2_ddr_phy_init";
end mig_mig_7series_v4_2_ddr_phy_init;

architecture STRUCTURE of mig_mig_7series_v4_2_ddr_phy_init is
  signal \DDR3_1rank.phy_int_cs_n[1]_i_10_n_0\ : STD_LOGIC;
  signal \DDR3_1rank.phy_int_cs_n[1]_i_1_n_0\ : STD_LOGIC;
  signal \DDR3_1rank.phy_int_cs_n[1]_i_2_n_0\ : STD_LOGIC;
  signal \DDR3_1rank.phy_int_cs_n[1]_i_3_n_0\ : STD_LOGIC;
  signal \DDR3_1rank.phy_int_cs_n[1]_i_4_n_0\ : STD_LOGIC;
  signal \DDR3_1rank.phy_int_cs_n[1]_i_5_n_0\ : STD_LOGIC;
  signal \DDR3_1rank.phy_int_cs_n[1]_i_6_n_0\ : STD_LOGIC;
  signal \DDR3_1rank.phy_int_cs_n[1]_i_7_n_0\ : STD_LOGIC;
  signal \DDR3_1rank.phy_int_cs_n[1]_i_8_n_0\ : STD_LOGIC;
  signal \DDR3_1rank.phy_int_cs_n[1]_i_9_n_0\ : STD_LOGIC;
  signal \^q\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal address_w : STD_LOGIC_VECTOR ( 12 downto 0 );
  signal \back_to_back_reads_4_1.num_reads[0]_i_1_n_0\ : STD_LOGIC;
  signal \back_to_back_reads_4_1.num_reads[1]_i_1_n_0\ : STD_LOGIC;
  signal bank_w : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal burst_addr_r_i_1_n_0 : STD_LOGIC;
  signal burst_addr_r_i_2_n_0 : STD_LOGIC;
  signal burst_addr_r_i_3_n_0 : STD_LOGIC;
  signal calib_cke : STD_LOGIC_VECTOR ( 3 to 3 );
  signal calib_cmd : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal \calib_cmd[0]_i_1_n_0\ : STD_LOGIC;
  signal \calib_cmd[1]_i_1_n_0\ : STD_LOGIC;
  signal \calib_cmd[2]_i_1_n_0\ : STD_LOGIC;
  signal \calib_cmd[2]_i_2_n_0\ : STD_LOGIC;
  signal \calib_cmd[2]_i_3_n_0\ : STD_LOGIC;
  signal \calib_cmd[2]_i_4_n_0\ : STD_LOGIC;
  signal \calib_cmd[2]_i_5_n_0\ : STD_LOGIC;
  signal calib_cmd_wren : STD_LOGIC;
  signal calib_data_offset_0 : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal \calib_data_offset_0[3]_i_1_n_0\ : STD_LOGIC;
  signal \calib_data_offset_0[3]_i_2_n_0\ : STD_LOGIC;
  signal \calib_data_offset_0[5]_i_1_n_0\ : STD_LOGIC;
  signal calib_data_offset_1 : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal \calib_data_offset_1[3]_i_1_n_0\ : STD_LOGIC;
  signal \calib_data_offset_1[3]_i_2_n_0\ : STD_LOGIC;
  signal calib_data_offset_2 : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal \calib_data_offset_2[3]_i_1_n_0\ : STD_LOGIC;
  signal \calib_data_offset_2[3]_i_2_n_0\ : STD_LOGIC;
  signal calib_odt : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \calib_odt[0]_i_1_n_0\ : STD_LOGIC;
  signal \calib_odt[0]_i_2_n_0\ : STD_LOGIC;
  signal \calib_odt[0]_i_3_n_0\ : STD_LOGIC;
  signal \calib_seq[0]_i_1_n_0\ : STD_LOGIC;
  signal \calib_seq[1]_i_1_n_0\ : STD_LOGIC;
  signal \^calib_seq_reg[1]_0\ : STD_LOGIC_VECTOR ( 10 downto 0 );
  signal calib_wrdata_en : STD_LOGIC;
  signal calib_wrdata_en_i_2_n_0 : STD_LOGIC;
  signal clear : STD_LOGIC;
  signal cnt_cmd_done_m7_r : STD_LOGIC;
  signal cnt_cmd_done_m7_r_i_1_n_0 : STD_LOGIC;
  signal cnt_cmd_done_m7_r_i_2_n_0 : STD_LOGIC;
  signal cnt_cmd_done_r : STD_LOGIC;
  signal cnt_cmd_done_r_i_1_n_0 : STD_LOGIC;
  signal \cnt_cmd_r[0]_i_1_n_0\ : STD_LOGIC;
  signal \cnt_cmd_r[1]_i_1_n_0\ : STD_LOGIC;
  signal \cnt_cmd_r[2]_i_1_n_0\ : STD_LOGIC;
  signal \cnt_cmd_r[3]_i_1_n_0\ : STD_LOGIC;
  signal \cnt_cmd_r[4]_i_1_n_0\ : STD_LOGIC;
  signal \cnt_cmd_r[5]_i_1_n_0\ : STD_LOGIC;
  signal \cnt_cmd_r[6]_i_1_n_0\ : STD_LOGIC;
  signal \cnt_cmd_r[6]_i_2_n_0\ : STD_LOGIC;
  signal \cnt_cmd_r[6]_i_3_n_0\ : STD_LOGIC;
  signal \cnt_cmd_r[6]_i_4_n_0\ : STD_LOGIC;
  signal \cnt_cmd_r_reg_n_0_[0]\ : STD_LOGIC;
  signal \cnt_cmd_r_reg_n_0_[1]\ : STD_LOGIC;
  signal \cnt_cmd_r_reg_n_0_[2]\ : STD_LOGIC;
  signal \cnt_cmd_r_reg_n_0_[3]\ : STD_LOGIC;
  signal \cnt_cmd_r_reg_n_0_[4]\ : STD_LOGIC;
  signal \cnt_cmd_r_reg_n_0_[5]\ : STD_LOGIC;
  signal \cnt_cmd_r_reg_n_0_[6]\ : STD_LOGIC;
  signal cnt_dllk_zqinit_done_r : STD_LOGIC;
  signal cnt_dllk_zqinit_done_r_i_1_n_0 : STD_LOGIC;
  signal \cnt_dllk_zqinit_r[7]_i_1_n_0\ : STD_LOGIC;
  signal cnt_dllk_zqinit_r_reg : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal cnt_init_af_done_r : STD_LOGIC;
  signal cnt_init_af_done_r_i_1_n_0 : STD_LOGIC;
  signal cnt_init_af_r : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \cnt_init_af_r[0]_i_1_n_0\ : STD_LOGIC;
  signal \cnt_init_af_r[1]_i_1_n_0\ : STD_LOGIC;
  signal cnt_init_mr_done_r : STD_LOGIC;
  signal cnt_init_mr_done_r_i_1_n_0 : STD_LOGIC;
  signal cnt_init_mr_r : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal cnt_init_mr_r1 : STD_LOGIC;
  signal \cnt_init_mr_r[0]_i_1_n_0\ : STD_LOGIC;
  signal \cnt_init_mr_r[0]_i_2_n_0\ : STD_LOGIC;
  signal \cnt_init_mr_r[0]_i_3_n_0\ : STD_LOGIC;
  signal \cnt_init_mr_r[1]_i_1_n_0\ : STD_LOGIC;
  signal \cnt_init_mr_r[1]_i_2_n_0\ : STD_LOGIC;
  signal cnt_pwron_ce_r_reg : STD_LOGIC_VECTOR ( 9 downto 0 );
  signal cnt_pwron_cke_done_r : STD_LOGIC;
  signal cnt_pwron_cke_done_r_i_1_n_0 : STD_LOGIC;
  signal cnt_pwron_cke_done_r_i_2_n_0 : STD_LOGIC;
  signal cnt_pwron_cke_done_r_i_3_n_0 : STD_LOGIC;
  signal \cnt_pwron_r[8]_i_2_n_0\ : STD_LOGIC;
  signal cnt_pwron_r_reg : STD_LOGIC_VECTOR ( 8 downto 0 );
  signal cnt_pwron_reset_done_r : STD_LOGIC;
  signal cnt_pwron_reset_done_r_i_1_n_0 : STD_LOGIC;
  signal cnt_pwron_reset_done_r_i_2_n_0 : STD_LOGIC;
  signal cnt_txpr_done_r : STD_LOGIC;
  signal cnt_txpr_done_r_i_1_n_0 : STD_LOGIC;
  signal cnt_txpr_done_r_i_2_n_0 : STD_LOGIC;
  signal \cnt_txpr_r[7]_i_3_n_0\ : STD_LOGIC;
  signal cnt_txpr_r_reg : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal complex_act_start0 : STD_LOGIC;
  signal complex_act_start_i_2_n_0 : STD_LOGIC;
  signal complex_address0 : STD_LOGIC;
  signal \complex_address[9]_i_2_n_0\ : STD_LOGIC;
  signal \complex_address[9]_i_3_n_0\ : STD_LOGIC;
  signal \complex_address_reg_n_0_[0]\ : STD_LOGIC;
  signal \complex_address_reg_n_0_[1]\ : STD_LOGIC;
  signal \complex_address_reg_n_0_[2]\ : STD_LOGIC;
  signal \complex_address_reg_n_0_[3]\ : STD_LOGIC;
  signal \complex_address_reg_n_0_[4]\ : STD_LOGIC;
  signal \complex_address_reg_n_0_[5]\ : STD_LOGIC;
  signal \complex_address_reg_n_0_[6]\ : STD_LOGIC;
  signal \complex_address_reg_n_0_[7]\ : STD_LOGIC;
  signal \complex_address_reg_n_0_[8]\ : STD_LOGIC;
  signal \complex_address_reg_n_0_[9]\ : STD_LOGIC;
  signal complex_byte_rd_done : STD_LOGIC;
  signal complex_byte_rd_done_i_1_n_0 : STD_LOGIC;
  signal complex_byte_rd_done_i_2_n_0 : STD_LOGIC;
  signal \complex_num_reads[0]_i_1_n_0\ : STD_LOGIC;
  signal \complex_num_reads[1]_i_1_n_0\ : STD_LOGIC;
  signal \complex_num_reads[1]_i_2_n_0\ : STD_LOGIC;
  signal \complex_num_reads[2]_i_1_n_0\ : STD_LOGIC;
  signal \complex_num_reads[2]_i_2_n_0\ : STD_LOGIC;
  signal \complex_num_reads[2]_i_3_n_0\ : STD_LOGIC;
  signal \complex_num_reads[2]_i_4_n_0\ : STD_LOGIC;
  signal \complex_num_reads[2]_i_5_n_0\ : STD_LOGIC;
  signal \complex_num_reads[2]_i_6_n_0\ : STD_LOGIC;
  signal \complex_num_reads[3]_i_1_n_0\ : STD_LOGIC;
  signal \complex_num_reads[3]_i_2_n_0\ : STD_LOGIC;
  signal \complex_num_reads[3]_i_3_n_0\ : STD_LOGIC;
  signal \complex_num_reads[3]_i_4_n_0\ : STD_LOGIC;
  signal \complex_num_reads[3]_i_5_n_0\ : STD_LOGIC;
  signal \complex_num_reads[3]_i_6_n_0\ : STD_LOGIC;
  signal \complex_num_reads[3]_i_7_n_0\ : STD_LOGIC;
  signal complex_num_reads_dec : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \complex_num_reads_dec[0]_i_1_n_0\ : STD_LOGIC;
  signal \complex_num_reads_dec[1]_i_1_n_0\ : STD_LOGIC;
  signal \complex_num_reads_dec[2]_i_1_n_0\ : STD_LOGIC;
  signal \complex_num_reads_dec[3]_i_1_n_0\ : STD_LOGIC;
  signal \complex_num_reads_dec[3]_i_2_n_0\ : STD_LOGIC;
  signal \complex_num_reads_dec[3]_i_3_n_0\ : STD_LOGIC;
  signal \complex_num_reads_dec[3]_i_4_n_0\ : STD_LOGIC;
  signal \complex_num_reads_reg_n_0_[0]\ : STD_LOGIC;
  signal \complex_num_reads_reg_n_0_[1]\ : STD_LOGIC;
  signal \complex_num_reads_reg_n_0_[2]\ : STD_LOGIC;
  signal \complex_num_reads_reg_n_0_[3]\ : STD_LOGIC;
  signal \complex_num_writes[0]_i_1_n_0\ : STD_LOGIC;
  signal \complex_num_writes[0]_i_2_n_0\ : STD_LOGIC;
  signal \complex_num_writes[1]_i_1_n_0\ : STD_LOGIC;
  signal \complex_num_writes[1]_i_2_n_0\ : STD_LOGIC;
  signal \complex_num_writes[2]_i_1_n_0\ : STD_LOGIC;
  signal \complex_num_writes[2]_i_2_n_0\ : STD_LOGIC;
  signal \complex_num_writes[2]_i_3_n_0\ : STD_LOGIC;
  signal \complex_num_writes[2]_i_4_n_0\ : STD_LOGIC;
  signal \complex_num_writes[2]_i_5_n_0\ : STD_LOGIC;
  signal \complex_num_writes[2]_i_7_n_0\ : STD_LOGIC;
  signal \complex_num_writes[2]_i_8_n_0\ : STD_LOGIC;
  signal \complex_num_writes[2]_i_9_n_0\ : STD_LOGIC;
  signal \complex_num_writes[3]_i_1_n_0\ : STD_LOGIC;
  signal \complex_num_writes[3]_i_2_n_0\ : STD_LOGIC;
  signal \complex_num_writes[3]_i_3_n_0\ : STD_LOGIC;
  signal \complex_num_writes[3]_i_4_n_0\ : STD_LOGIC;
  signal \complex_num_writes[4]_i_10_n_0\ : STD_LOGIC;
  signal \complex_num_writes[4]_i_11_n_0\ : STD_LOGIC;
  signal \complex_num_writes[4]_i_12_n_0\ : STD_LOGIC;
  signal \complex_num_writes[4]_i_13_n_0\ : STD_LOGIC;
  signal \complex_num_writes[4]_i_14_n_0\ : STD_LOGIC;
  signal \complex_num_writes[4]_i_15_n_0\ : STD_LOGIC;
  signal \complex_num_writes[4]_i_16_n_0\ : STD_LOGIC;
  signal \complex_num_writes[4]_i_1_n_0\ : STD_LOGIC;
  signal \complex_num_writes[4]_i_2_n_0\ : STD_LOGIC;
  signal \complex_num_writes[4]_i_3_n_0\ : STD_LOGIC;
  signal \complex_num_writes[4]_i_4_n_0\ : STD_LOGIC;
  signal \complex_num_writes[4]_i_5_n_0\ : STD_LOGIC;
  signal \complex_num_writes[4]_i_6_n_0\ : STD_LOGIC;
  signal \complex_num_writes[4]_i_7_n_0\ : STD_LOGIC;
  signal \complex_num_writes[4]_i_8_n_0\ : STD_LOGIC;
  signal \complex_num_writes[4]_i_9_n_0\ : STD_LOGIC;
  signal complex_num_writes_dec : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal \complex_num_writes_dec[0]_i_1_n_0\ : STD_LOGIC;
  signal \complex_num_writes_dec[1]_i_1_n_0\ : STD_LOGIC;
  signal \complex_num_writes_dec[2]_i_1_n_0\ : STD_LOGIC;
  signal \complex_num_writes_dec[3]_i_1_n_0\ : STD_LOGIC;
  signal \complex_num_writes_dec[4]_i_2_n_0\ : STD_LOGIC;
  signal \complex_num_writes_dec[4]_i_3_n_0\ : STD_LOGIC;
  signal \complex_num_writes_dec[4]_i_4_n_0\ : STD_LOGIC;
  signal \complex_num_writes_dec[4]_i_5_n_0\ : STD_LOGIC;
  signal \complex_num_writes_reg_n_0_[0]\ : STD_LOGIC;
  signal \complex_num_writes_reg_n_0_[1]\ : STD_LOGIC;
  signal \complex_num_writes_reg_n_0_[2]\ : STD_LOGIC;
  signal \complex_num_writes_reg_n_0_[3]\ : STD_LOGIC;
  signal \complex_num_writes_reg_n_0_[4]\ : STD_LOGIC;
  signal complex_ocal_odt_ext : STD_LOGIC;
  signal complex_ocal_odt_ext_i_1_n_0 : STD_LOGIC;
  signal complex_ocal_odt_ext_i_2_n_0 : STD_LOGIC;
  signal complex_ocal_odt_ext_i_3_n_0 : STD_LOGIC;
  signal \^complex_ocal_reset_rd_addr\ : STD_LOGIC;
  signal complex_ocal_reset_rd_addr0 : STD_LOGIC;
  signal complex_ocal_reset_rd_addr_i_2_n_0 : STD_LOGIC;
  signal complex_ocal_reset_rd_addr_i_3_n_0 : STD_LOGIC;
  signal complex_ocal_wr_start : STD_LOGIC;
  signal complex_ocal_wr_start_i_1_n_0 : STD_LOGIC;
  signal complex_oclkdelay_calib_done_r1 : STD_LOGIC;
  signal complex_oclkdelay_calib_start_int : STD_LOGIC;
  signal complex_oclkdelay_calib_start_int_i_1_n_0 : STD_LOGIC;
  signal complex_oclkdelay_calib_start_int_i_2_n_0 : STD_LOGIC;
  signal complex_oclkdelay_calib_start_r1 : STD_LOGIC;
  signal complex_odt_ext : STD_LOGIC;
  signal complex_odt_ext_i_1_n_0 : STD_LOGIC;
  signal complex_row0_rd_done : STD_LOGIC;
  signal complex_row0_rd_done1 : STD_LOGIC;
  signal complex_row0_rd_done_i_1_n_0 : STD_LOGIC;
  signal complex_row0_rd_done_i_2_n_0 : STD_LOGIC;
  signal complex_row0_wr_done : STD_LOGIC;
  signal complex_row0_wr_done0 : STD_LOGIC;
  signal complex_row1_rd_cnt : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal \complex_row1_rd_cnt[0]_i_1_n_0\ : STD_LOGIC;
  signal \complex_row1_rd_cnt[1]_i_1_n_0\ : STD_LOGIC;
  signal \complex_row1_rd_cnt[2]_i_1_n_0\ : STD_LOGIC;
  signal complex_row1_rd_done : STD_LOGIC;
  signal complex_row1_rd_done_i_1_n_0 : STD_LOGIC;
  signal complex_row1_rd_done_i_2_n_0 : STD_LOGIC;
  signal complex_row1_rd_done_r1 : STD_LOGIC;
  signal complex_row1_wr_done : STD_LOGIC;
  signal complex_row_cnt : STD_LOGIC;
  signal complex_row_cnt_ocal : STD_LOGIC;
  signal complex_row_cnt_ocal0 : STD_LOGIC;
  signal \complex_row_cnt_ocal[3]_i_4_n_0\ : STD_LOGIC;
  signal \complex_row_cnt_ocal[3]_i_5_n_0\ : STD_LOGIC;
  signal \complex_row_cnt_ocal[3]_i_6_n_0\ : STD_LOGIC;
  signal complex_row_cnt_ocal_reg : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal complex_sample_cnt_inc : STD_LOGIC;
  signal complex_sample_cnt_inc0 : STD_LOGIC;
  signal complex_sample_cnt_inc_i_2_n_0 : STD_LOGIC;
  signal complex_sample_cnt_inc_i_3_n_0 : STD_LOGIC;
  signal complex_sample_cnt_inc_r1 : STD_LOGIC;
  signal complex_sample_cnt_inc_r2 : STD_LOGIC;
  signal \complex_wait_cnt[3]_i_1_n_0\ : STD_LOGIC;
  signal \complex_wait_cnt[3]_i_3_n_0\ : STD_LOGIC;
  signal complex_wait_cnt_reg : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal complex_wr_done : STD_LOGIC;
  signal ddr2_pre_flag_r_i_1_n_0 : STD_LOGIC;
  signal ddr2_pre_flag_r_i_2_n_0 : STD_LOGIC;
  signal ddr2_pre_flag_r_reg_n_0 : STD_LOGIC;
  signal ddr2_refresh_flag_r : STD_LOGIC;
  signal ddr2_refresh_flag_r_i_1_n_0 : STD_LOGIC;
  signal ddr2_refresh_flag_r_i_2_n_0 : STD_LOGIC;
  signal ddr2_refresh_flag_r_i_3_n_0 : STD_LOGIC;
  signal ddr3_lm_done_r : STD_LOGIC;
  signal ddr3_lm_done_r_i_1_n_0 : STD_LOGIC;
  signal detect_pi_found_dqs0 : STD_LOGIC;
  signal detect_pi_found_dqs_i_2_n_0 : STD_LOGIC;
  signal dqs_asrt_cnt : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \dqs_asrt_cnt[0]_i_1_n_0\ : STD_LOGIC;
  signal \dqs_asrt_cnt[1]_i_1_n_0\ : STD_LOGIC;
  signal \en_cnt_div4.enable_wrlvl_cnt[0]_i_1_n_0\ : STD_LOGIC;
  signal \en_cnt_div4.enable_wrlvl_cnt[1]_i_1_n_0\ : STD_LOGIC;
  signal \en_cnt_div4.enable_wrlvl_cnt[2]_i_1_n_0\ : STD_LOGIC;
  signal \en_cnt_div4.enable_wrlvl_cnt[3]_i_1_n_0\ : STD_LOGIC;
  signal \en_cnt_div4.enable_wrlvl_cnt[4]_i_1_n_0\ : STD_LOGIC;
  signal \en_cnt_div4.wrlvl_odt_i_1_n_0\ : STD_LOGIC;
  signal \en_cnt_div4.wrlvl_odt_i_2_n_0\ : STD_LOGIC;
  signal enable_wrlvl_cnt : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal enable_wrlvl_cnt0 : STD_LOGIC;
  signal \^first_rdlvl_pat_r\ : STD_LOGIC;
  signal first_rdlvl_pat_r_i_1_n_0 : STD_LOGIC;
  signal \^first_wrcal_pat_r\ : STD_LOGIC;
  signal first_wrcal_pat_r_i_1_n_0 : STD_LOGIC;
  signal \gen_no_mirror.div_clk_loop[0].phy_address[0]_i_2_n_0\ : STD_LOGIC;
  signal \gen_no_mirror.div_clk_loop[0].phy_address[0]_i_3_n_0\ : STD_LOGIC;
  signal \gen_no_mirror.div_clk_loop[0].phy_address[0]_i_4_n_0\ : STD_LOGIC;
  signal \gen_no_mirror.div_clk_loop[0].phy_address[10]_i_2_n_0\ : STD_LOGIC;
  signal \gen_no_mirror.div_clk_loop[0].phy_address[10]_i_3_n_0\ : STD_LOGIC;
  signal \gen_no_mirror.div_clk_loop[0].phy_address[10]_i_5_n_0\ : STD_LOGIC;
  signal \gen_no_mirror.div_clk_loop[0].phy_address[10]_i_6_n_0\ : STD_LOGIC;
  signal \gen_no_mirror.div_clk_loop[0].phy_address[12]_i_2_n_0\ : STD_LOGIC;
  signal \gen_no_mirror.div_clk_loop[0].phy_address[1]_i_2_n_0\ : STD_LOGIC;
  signal \gen_no_mirror.div_clk_loop[0].phy_address[1]_i_3_n_0\ : STD_LOGIC;
  signal \gen_no_mirror.div_clk_loop[0].phy_address[1]_i_4_n_0\ : STD_LOGIC;
  signal \gen_no_mirror.div_clk_loop[0].phy_address[1]_i_5_n_0\ : STD_LOGIC;
  signal \gen_no_mirror.div_clk_loop[0].phy_address[2]_i_2_n_0\ : STD_LOGIC;
  signal \gen_no_mirror.div_clk_loop[0].phy_address[2]_i_3_n_0\ : STD_LOGIC;
  signal \gen_no_mirror.div_clk_loop[0].phy_address[2]_i_4_n_0\ : STD_LOGIC;
  signal \gen_no_mirror.div_clk_loop[0].phy_address[2]_i_5_n_0\ : STD_LOGIC;
  signal \gen_no_mirror.div_clk_loop[0].phy_address[2]_i_6_n_0\ : STD_LOGIC;
  signal \gen_no_mirror.div_clk_loop[0].phy_address[3]_i_2_n_0\ : STD_LOGIC;
  signal \gen_no_mirror.div_clk_loop[0].phy_address[3]_i_3_n_0\ : STD_LOGIC;
  signal \gen_no_mirror.div_clk_loop[0].phy_address[4]_i_2_n_0\ : STD_LOGIC;
  signal \gen_no_mirror.div_clk_loop[0].phy_address[4]_i_3_n_0\ : STD_LOGIC;
  signal \gen_no_mirror.div_clk_loop[0].phy_address[4]_i_4_n_0\ : STD_LOGIC;
  signal \gen_no_mirror.div_clk_loop[0].phy_address[5]_i_2_n_0\ : STD_LOGIC;
  signal \gen_no_mirror.div_clk_loop[0].phy_address[5]_i_3_n_0\ : STD_LOGIC;
  signal \gen_no_mirror.div_clk_loop[0].phy_address[5]_i_4_n_0\ : STD_LOGIC;
  signal \gen_no_mirror.div_clk_loop[0].phy_address[5]_i_5_n_0\ : STD_LOGIC;
  signal \gen_no_mirror.div_clk_loop[0].phy_address[5]_i_6_n_0\ : STD_LOGIC;
  signal \gen_no_mirror.div_clk_loop[0].phy_address[6]_i_10_n_0\ : STD_LOGIC;
  signal \gen_no_mirror.div_clk_loop[0].phy_address[6]_i_2_n_0\ : STD_LOGIC;
  signal \gen_no_mirror.div_clk_loop[0].phy_address[6]_i_3_n_0\ : STD_LOGIC;
  signal \gen_no_mirror.div_clk_loop[0].phy_address[6]_i_4_n_0\ : STD_LOGIC;
  signal \gen_no_mirror.div_clk_loop[0].phy_address[6]_i_5_n_0\ : STD_LOGIC;
  signal \gen_no_mirror.div_clk_loop[0].phy_address[6]_i_6_n_0\ : STD_LOGIC;
  signal \gen_no_mirror.div_clk_loop[0].phy_address[6]_i_7_n_0\ : STD_LOGIC;
  signal \gen_no_mirror.div_clk_loop[0].phy_address[6]_i_8_n_0\ : STD_LOGIC;
  signal \gen_no_mirror.div_clk_loop[0].phy_address[6]_i_9_n_0\ : STD_LOGIC;
  signal \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_10_n_0\ : STD_LOGIC;
  signal \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_11_n_0\ : STD_LOGIC;
  signal \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_12_n_0\ : STD_LOGIC;
  signal \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_13_n_0\ : STD_LOGIC;
  signal \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_2_n_0\ : STD_LOGIC;
  signal \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_3_n_0\ : STD_LOGIC;
  signal \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_4_n_0\ : STD_LOGIC;
  signal \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_5_n_0\ : STD_LOGIC;
  signal \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_6_n_0\ : STD_LOGIC;
  signal \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_7_n_0\ : STD_LOGIC;
  signal \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_8_n_0\ : STD_LOGIC;
  signal \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_9_n_0\ : STD_LOGIC;
  signal \gen_no_mirror.div_clk_loop[0].phy_address[8]_i_2_n_0\ : STD_LOGIC;
  signal \gen_no_mirror.div_clk_loop[0].phy_address[8]_i_3_n_0\ : STD_LOGIC;
  signal \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_10_n_0\ : STD_LOGIC;
  signal \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_11_n_0\ : STD_LOGIC;
  signal \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_12_n_0\ : STD_LOGIC;
  signal \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_13_n_0\ : STD_LOGIC;
  signal \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_14_n_0\ : STD_LOGIC;
  signal \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_15_n_0\ : STD_LOGIC;
  signal \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_16_n_0\ : STD_LOGIC;
  signal \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_17_n_0\ : STD_LOGIC;
  signal \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_2_n_0\ : STD_LOGIC;
  signal \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_3_n_0\ : STD_LOGIC;
  signal \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_4_n_0\ : STD_LOGIC;
  signal \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_5_n_0\ : STD_LOGIC;
  signal \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_6_n_0\ : STD_LOGIC;
  signal \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_7_n_0\ : STD_LOGIC;
  signal \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_8_n_0\ : STD_LOGIC;
  signal \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_9_n_0\ : STD_LOGIC;
  signal \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[0]\ : STD_LOGIC;
  signal \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[10]\ : STD_LOGIC;
  signal \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[12]\ : STD_LOGIC;
  signal \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[1]\ : STD_LOGIC;
  signal \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[2]\ : STD_LOGIC;
  signal \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[3]\ : STD_LOGIC;
  signal \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[4]\ : STD_LOGIC;
  signal \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[5]\ : STD_LOGIC;
  signal \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[6]\ : STD_LOGIC;
  signal \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[7]\ : STD_LOGIC;
  signal \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[8]\ : STD_LOGIC;
  signal \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[9]\ : STD_LOGIC;
  signal \gen_no_mirror.div_clk_loop[0].phy_bank[0]_i_2_n_0\ : STD_LOGIC;
  signal \gen_no_mirror.div_clk_loop[0].phy_bank[0]_i_3_n_0\ : STD_LOGIC;
  signal \gen_no_mirror.div_clk_loop[0].phy_bank[1]_i_2_n_0\ : STD_LOGIC;
  signal \gen_rnk[0].mr1_r_reg_n_0_[0][1]\ : STD_LOGIC;
  signal init_complete_r1 : STD_LOGIC;
  signal init_complete_r1_timing : STD_LOGIC;
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of init_complete_r1_timing : signal is "true";
  signal \^init_complete_r1_timing_reg_0\ : STD_LOGIC;
  signal init_complete_r2 : STD_LOGIC;
  signal init_complete_r_i_1_n_0 : STD_LOGIC;
  signal init_complete_r_reg_n_0 : STD_LOGIC;
  signal init_complete_r_timing : STD_LOGIC;
  attribute RTL_KEEP of init_complete_r_timing : signal is "true";
  signal init_complete_r_timing_i_1_n_0 : STD_LOGIC;
  signal init_next_state1100_out : STD_LOGIC;
  signal init_state_r : STD_LOGIC_VECTOR ( 6 to 6 );
  signal init_state_r1 : STD_LOGIC_VECTOR ( 6 downto 0 );
  signal \init_state_r[0]_i_10_n_0\ : STD_LOGIC;
  signal \init_state_r[0]_i_11_n_0\ : STD_LOGIC;
  signal \init_state_r[0]_i_12_n_0\ : STD_LOGIC;
  signal \init_state_r[0]_i_13_n_0\ : STD_LOGIC;
  signal \init_state_r[0]_i_14_n_0\ : STD_LOGIC;
  signal \init_state_r[0]_i_15_n_0\ : STD_LOGIC;
  signal \init_state_r[0]_i_16_n_0\ : STD_LOGIC;
  signal \init_state_r[0]_i_17_n_0\ : STD_LOGIC;
  signal \init_state_r[0]_i_18_n_0\ : STD_LOGIC;
  signal \init_state_r[0]_i_19_n_0\ : STD_LOGIC;
  signal \init_state_r[0]_i_1_n_0\ : STD_LOGIC;
  signal \init_state_r[0]_i_20_n_0\ : STD_LOGIC;
  signal \init_state_r[0]_i_21_n_0\ : STD_LOGIC;
  signal \init_state_r[0]_i_22_n_0\ : STD_LOGIC;
  signal \init_state_r[0]_i_23_n_0\ : STD_LOGIC;
  signal \init_state_r[0]_i_25_n_0\ : STD_LOGIC;
  signal \init_state_r[0]_i_26_n_0\ : STD_LOGIC;
  signal \init_state_r[0]_i_27_n_0\ : STD_LOGIC;
  signal \init_state_r[0]_i_28_n_0\ : STD_LOGIC;
  signal \init_state_r[0]_i_29_n_0\ : STD_LOGIC;
  signal \init_state_r[0]_i_2_n_0\ : STD_LOGIC;
  signal \init_state_r[0]_i_30_n_0\ : STD_LOGIC;
  signal \init_state_r[0]_i_31_n_0\ : STD_LOGIC;
  signal \init_state_r[0]_i_32_n_0\ : STD_LOGIC;
  signal \init_state_r[0]_i_3_n_0\ : STD_LOGIC;
  signal \init_state_r[0]_i_4_n_0\ : STD_LOGIC;
  signal \init_state_r[0]_i_5_n_0\ : STD_LOGIC;
  signal \init_state_r[0]_i_6_n_0\ : STD_LOGIC;
  signal \init_state_r[0]_i_7_n_0\ : STD_LOGIC;
  signal \init_state_r[0]_i_8_n_0\ : STD_LOGIC;
  signal \init_state_r[0]_i_9_n_0\ : STD_LOGIC;
  signal \init_state_r[1]_i_10_n_0\ : STD_LOGIC;
  signal \init_state_r[1]_i_11_n_0\ : STD_LOGIC;
  signal \init_state_r[1]_i_12_n_0\ : STD_LOGIC;
  signal \init_state_r[1]_i_13_n_0\ : STD_LOGIC;
  signal \init_state_r[1]_i_14_n_0\ : STD_LOGIC;
  signal \init_state_r[1]_i_15_n_0\ : STD_LOGIC;
  signal \init_state_r[1]_i_16_n_0\ : STD_LOGIC;
  signal \init_state_r[1]_i_17_n_0\ : STD_LOGIC;
  signal \init_state_r[1]_i_18_n_0\ : STD_LOGIC;
  signal \init_state_r[1]_i_19_n_0\ : STD_LOGIC;
  signal \init_state_r[1]_i_1_n_0\ : STD_LOGIC;
  signal \init_state_r[1]_i_20_n_0\ : STD_LOGIC;
  signal \init_state_r[1]_i_21_n_0\ : STD_LOGIC;
  signal \init_state_r[1]_i_22_n_0\ : STD_LOGIC;
  signal \init_state_r[1]_i_23_n_0\ : STD_LOGIC;
  signal \init_state_r[1]_i_24_n_0\ : STD_LOGIC;
  signal \init_state_r[1]_i_25_n_0\ : STD_LOGIC;
  signal \init_state_r[1]_i_26_n_0\ : STD_LOGIC;
  signal \init_state_r[1]_i_27_n_0\ : STD_LOGIC;
  signal \init_state_r[1]_i_29_n_0\ : STD_LOGIC;
  signal \init_state_r[1]_i_2_n_0\ : STD_LOGIC;
  signal \init_state_r[1]_i_30_n_0\ : STD_LOGIC;
  signal \init_state_r[1]_i_31_n_0\ : STD_LOGIC;
  signal \init_state_r[1]_i_32_n_0\ : STD_LOGIC;
  signal \init_state_r[1]_i_34_n_0\ : STD_LOGIC;
  signal \init_state_r[1]_i_3_n_0\ : STD_LOGIC;
  signal \init_state_r[1]_i_4_n_0\ : STD_LOGIC;
  signal \init_state_r[1]_i_5_n_0\ : STD_LOGIC;
  signal \init_state_r[1]_i_6_n_0\ : STD_LOGIC;
  signal \init_state_r[1]_i_7_n_0\ : STD_LOGIC;
  signal \init_state_r[1]_i_8_n_0\ : STD_LOGIC;
  signal \init_state_r[1]_i_9_n_0\ : STD_LOGIC;
  signal \init_state_r[2]_i_10_n_0\ : STD_LOGIC;
  signal \init_state_r[2]_i_11_n_0\ : STD_LOGIC;
  signal \init_state_r[2]_i_12_n_0\ : STD_LOGIC;
  signal \init_state_r[2]_i_13_n_0\ : STD_LOGIC;
  signal \init_state_r[2]_i_14_n_0\ : STD_LOGIC;
  signal \init_state_r[2]_i_15_n_0\ : STD_LOGIC;
  signal \init_state_r[2]_i_16_n_0\ : STD_LOGIC;
  signal \init_state_r[2]_i_17_n_0\ : STD_LOGIC;
  signal \init_state_r[2]_i_18_n_0\ : STD_LOGIC;
  signal \init_state_r[2]_i_19_n_0\ : STD_LOGIC;
  signal \init_state_r[2]_i_1_n_0\ : STD_LOGIC;
  signal \init_state_r[2]_i_20_n_0\ : STD_LOGIC;
  signal \init_state_r[2]_i_21_n_0\ : STD_LOGIC;
  signal \init_state_r[2]_i_22_n_0\ : STD_LOGIC;
  signal \init_state_r[2]_i_23_n_0\ : STD_LOGIC;
  signal \init_state_r[2]_i_24_n_0\ : STD_LOGIC;
  signal \init_state_r[2]_i_25_n_0\ : STD_LOGIC;
  signal \init_state_r[2]_i_26_n_0\ : STD_LOGIC;
  signal \init_state_r[2]_i_29_n_0\ : STD_LOGIC;
  signal \init_state_r[2]_i_2_n_0\ : STD_LOGIC;
  signal \init_state_r[2]_i_30_n_0\ : STD_LOGIC;
  signal \init_state_r[2]_i_31_n_0\ : STD_LOGIC;
  signal \init_state_r[2]_i_32_n_0\ : STD_LOGIC;
  signal \init_state_r[2]_i_33_n_0\ : STD_LOGIC;
  signal \init_state_r[2]_i_34_n_0\ : STD_LOGIC;
  signal \init_state_r[2]_i_36_n_0\ : STD_LOGIC;
  signal \init_state_r[2]_i_38_n_0\ : STD_LOGIC;
  signal \init_state_r[2]_i_39_n_0\ : STD_LOGIC;
  signal \init_state_r[2]_i_3_n_0\ : STD_LOGIC;
  signal \init_state_r[2]_i_40_n_0\ : STD_LOGIC;
  signal \init_state_r[2]_i_41_n_0\ : STD_LOGIC;
  signal \init_state_r[2]_i_42_n_0\ : STD_LOGIC;
  signal \init_state_r[2]_i_43_n_0\ : STD_LOGIC;
  signal \init_state_r[2]_i_44_n_0\ : STD_LOGIC;
  signal \init_state_r[2]_i_45_n_0\ : STD_LOGIC;
  signal \init_state_r[2]_i_4_n_0\ : STD_LOGIC;
  signal \init_state_r[2]_i_5_n_0\ : STD_LOGIC;
  signal \init_state_r[2]_i_6_n_0\ : STD_LOGIC;
  signal \init_state_r[2]_i_7_n_0\ : STD_LOGIC;
  signal \init_state_r[2]_i_8_n_0\ : STD_LOGIC;
  signal \init_state_r[2]_i_9_n_0\ : STD_LOGIC;
  signal \init_state_r[3]_i_10_n_0\ : STD_LOGIC;
  signal \init_state_r[3]_i_11_n_0\ : STD_LOGIC;
  signal \init_state_r[3]_i_12_n_0\ : STD_LOGIC;
  signal \init_state_r[3]_i_13_n_0\ : STD_LOGIC;
  signal \init_state_r[3]_i_14_n_0\ : STD_LOGIC;
  signal \init_state_r[3]_i_15_n_0\ : STD_LOGIC;
  signal \init_state_r[3]_i_16_n_0\ : STD_LOGIC;
  signal \init_state_r[3]_i_17_n_0\ : STD_LOGIC;
  signal \init_state_r[3]_i_18_n_0\ : STD_LOGIC;
  signal \init_state_r[3]_i_19_n_0\ : STD_LOGIC;
  signal \init_state_r[3]_i_1_n_0\ : STD_LOGIC;
  signal \init_state_r[3]_i_20_n_0\ : STD_LOGIC;
  signal \init_state_r[3]_i_21_n_0\ : STD_LOGIC;
  signal \init_state_r[3]_i_22_n_0\ : STD_LOGIC;
  signal \init_state_r[3]_i_24_n_0\ : STD_LOGIC;
  signal \init_state_r[3]_i_2_n_0\ : STD_LOGIC;
  signal \init_state_r[3]_i_3_n_0\ : STD_LOGIC;
  signal \init_state_r[3]_i_4_n_0\ : STD_LOGIC;
  signal \init_state_r[3]_i_5_n_0\ : STD_LOGIC;
  signal \init_state_r[3]_i_6_n_0\ : STD_LOGIC;
  signal \init_state_r[3]_i_7_n_0\ : STD_LOGIC;
  signal \init_state_r[3]_i_8_n_0\ : STD_LOGIC;
  signal \init_state_r[3]_i_9_n_0\ : STD_LOGIC;
  signal \init_state_r[4]_i_10_n_0\ : STD_LOGIC;
  signal \init_state_r[4]_i_11_n_0\ : STD_LOGIC;
  signal \init_state_r[4]_i_12_n_0\ : STD_LOGIC;
  signal \init_state_r[4]_i_13_n_0\ : STD_LOGIC;
  signal \init_state_r[4]_i_14_n_0\ : STD_LOGIC;
  signal \init_state_r[4]_i_15_n_0\ : STD_LOGIC;
  signal \init_state_r[4]_i_16_n_0\ : STD_LOGIC;
  signal \init_state_r[4]_i_17_n_0\ : STD_LOGIC;
  signal \init_state_r[4]_i_18_n_0\ : STD_LOGIC;
  signal \init_state_r[4]_i_19_n_0\ : STD_LOGIC;
  signal \init_state_r[4]_i_1_n_0\ : STD_LOGIC;
  signal \init_state_r[4]_i_20_n_0\ : STD_LOGIC;
  signal \init_state_r[4]_i_21_n_0\ : STD_LOGIC;
  signal \init_state_r[4]_i_22_n_0\ : STD_LOGIC;
  signal \init_state_r[4]_i_23_n_0\ : STD_LOGIC;
  signal \init_state_r[4]_i_24_n_0\ : STD_LOGIC;
  signal \init_state_r[4]_i_25_n_0\ : STD_LOGIC;
  signal \init_state_r[4]_i_26_n_0\ : STD_LOGIC;
  signal \init_state_r[4]_i_27_n_0\ : STD_LOGIC;
  signal \init_state_r[4]_i_2_n_0\ : STD_LOGIC;
  signal \init_state_r[4]_i_3_n_0\ : STD_LOGIC;
  signal \init_state_r[4]_i_4_n_0\ : STD_LOGIC;
  signal \init_state_r[4]_i_5_n_0\ : STD_LOGIC;
  signal \init_state_r[4]_i_6_n_0\ : STD_LOGIC;
  signal \init_state_r[4]_i_7_n_0\ : STD_LOGIC;
  signal \init_state_r[4]_i_8_n_0\ : STD_LOGIC;
  signal \init_state_r[4]_i_9_n_0\ : STD_LOGIC;
  signal \init_state_r[5]_i_10_n_0\ : STD_LOGIC;
  signal \init_state_r[5]_i_11_n_0\ : STD_LOGIC;
  signal \init_state_r[5]_i_12_n_0\ : STD_LOGIC;
  signal \init_state_r[5]_i_13_n_0\ : STD_LOGIC;
  signal \init_state_r[5]_i_14_n_0\ : STD_LOGIC;
  signal \init_state_r[5]_i_15_n_0\ : STD_LOGIC;
  signal \init_state_r[5]_i_16_n_0\ : STD_LOGIC;
  signal \init_state_r[5]_i_17_n_0\ : STD_LOGIC;
  signal \init_state_r[5]_i_18_n_0\ : STD_LOGIC;
  signal \init_state_r[5]_i_19_n_0\ : STD_LOGIC;
  signal \init_state_r[5]_i_1_n_0\ : STD_LOGIC;
  signal \init_state_r[5]_i_20_n_0\ : STD_LOGIC;
  signal \init_state_r[5]_i_21_n_0\ : STD_LOGIC;
  signal \init_state_r[5]_i_22_n_0\ : STD_LOGIC;
  signal \init_state_r[5]_i_23_n_0\ : STD_LOGIC;
  signal \init_state_r[5]_i_24_n_0\ : STD_LOGIC;
  signal \init_state_r[5]_i_25_n_0\ : STD_LOGIC;
  signal \init_state_r[5]_i_26_n_0\ : STD_LOGIC;
  signal \init_state_r[5]_i_27_n_0\ : STD_LOGIC;
  signal \init_state_r[5]_i_28_n_0\ : STD_LOGIC;
  signal \init_state_r[5]_i_29_n_0\ : STD_LOGIC;
  signal \init_state_r[5]_i_2_n_0\ : STD_LOGIC;
  signal \init_state_r[5]_i_30_n_0\ : STD_LOGIC;
  signal \init_state_r[5]_i_31_n_0\ : STD_LOGIC;
  signal \init_state_r[5]_i_32_n_0\ : STD_LOGIC;
  signal \init_state_r[5]_i_33_n_0\ : STD_LOGIC;
  signal \init_state_r[5]_i_34_n_0\ : STD_LOGIC;
  signal \init_state_r[5]_i_35_n_0\ : STD_LOGIC;
  signal \init_state_r[5]_i_36_n_0\ : STD_LOGIC;
  signal \init_state_r[5]_i_37_n_0\ : STD_LOGIC;
  signal \init_state_r[5]_i_38_n_0\ : STD_LOGIC;
  signal \init_state_r[5]_i_39_n_0\ : STD_LOGIC;
  signal \init_state_r[5]_i_3_n_0\ : STD_LOGIC;
  signal \init_state_r[5]_i_40_n_0\ : STD_LOGIC;
  signal \init_state_r[5]_i_41_n_0\ : STD_LOGIC;
  signal \init_state_r[5]_i_42_n_0\ : STD_LOGIC;
  signal \init_state_r[5]_i_43_n_0\ : STD_LOGIC;
  signal \init_state_r[5]_i_44_n_0\ : STD_LOGIC;
  signal \init_state_r[5]_i_45_n_0\ : STD_LOGIC;
  signal \init_state_r[5]_i_46_n_0\ : STD_LOGIC;
  signal \init_state_r[5]_i_47_n_0\ : STD_LOGIC;
  signal \init_state_r[5]_i_48_n_0\ : STD_LOGIC;
  signal \init_state_r[5]_i_49_n_0\ : STD_LOGIC;
  signal \init_state_r[5]_i_4_n_0\ : STD_LOGIC;
  signal \init_state_r[5]_i_50_n_0\ : STD_LOGIC;
  signal \init_state_r[5]_i_5_n_0\ : STD_LOGIC;
  signal \init_state_r[5]_i_6_n_0\ : STD_LOGIC;
  signal \init_state_r[5]_i_7_n_0\ : STD_LOGIC;
  signal \init_state_r[5]_i_8_n_0\ : STD_LOGIC;
  signal \init_state_r[5]_i_9_n_0\ : STD_LOGIC;
  signal \init_state_r[6]_i_10_n_0\ : STD_LOGIC;
  signal \init_state_r[6]_i_11_n_0\ : STD_LOGIC;
  signal \init_state_r[6]_i_12_n_0\ : STD_LOGIC;
  signal \init_state_r[6]_i_13_n_0\ : STD_LOGIC;
  signal \init_state_r[6]_i_14_n_0\ : STD_LOGIC;
  signal \init_state_r[6]_i_15_n_0\ : STD_LOGIC;
  signal \init_state_r[6]_i_16_n_0\ : STD_LOGIC;
  signal \init_state_r[6]_i_17_n_0\ : STD_LOGIC;
  signal \init_state_r[6]_i_18_n_0\ : STD_LOGIC;
  signal \init_state_r[6]_i_19_n_0\ : STD_LOGIC;
  signal \init_state_r[6]_i_1_n_0\ : STD_LOGIC;
  signal \init_state_r[6]_i_20_n_0\ : STD_LOGIC;
  signal \init_state_r[6]_i_21_n_0\ : STD_LOGIC;
  signal \init_state_r[6]_i_22_n_0\ : STD_LOGIC;
  signal \init_state_r[6]_i_23_n_0\ : STD_LOGIC;
  signal \init_state_r[6]_i_24_n_0\ : STD_LOGIC;
  signal \init_state_r[6]_i_25_n_0\ : STD_LOGIC;
  signal \init_state_r[6]_i_26_n_0\ : STD_LOGIC;
  signal \init_state_r[6]_i_2_n_0\ : STD_LOGIC;
  signal \init_state_r[6]_i_3_n_0\ : STD_LOGIC;
  signal \init_state_r[6]_i_4_n_0\ : STD_LOGIC;
  signal \init_state_r[6]_i_5_n_0\ : STD_LOGIC;
  signal \init_state_r[6]_i_6_n_0\ : STD_LOGIC;
  signal \init_state_r[6]_i_7_n_0\ : STD_LOGIC;
  signal \init_state_r[6]_i_8_n_0\ : STD_LOGIC;
  signal \init_state_r[6]_i_9_n_0\ : STD_LOGIC;
  signal \^init_state_r_reg[4]_0\ : STD_LOGIC;
  signal \^init_state_r_reg[4]_1\ : STD_LOGIC;
  signal \init_state_r_reg_n_0_[1]\ : STD_LOGIC;
  signal \init_state_r_reg_n_0_[2]\ : STD_LOGIC;
  signal \init_state_r_reg_n_0_[3]\ : STD_LOGIC;
  signal \init_state_r_reg_n_0_[4]\ : STD_LOGIC;
  signal \init_state_r_reg_n_0_[5]\ : STD_LOGIC;
  signal mem_init_done_r : STD_LOGIC;
  signal mem_init_done_r_i_1_n_0 : STD_LOGIC;
  signal mem_init_done_r_i_2_n_0 : STD_LOGIC;
  signal mpr_rdlvl_start_i_1_n_0 : STD_LOGIC;
  signal mpr_rdlvl_start_i_2_n_0 : STD_LOGIC;
  signal \^mpr_rdlvl_start_reg_0\ : STD_LOGIC;
  signal num_reads : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal num_refresh0 : STD_LOGIC;
  signal \num_refresh[3]_i_1_n_0\ : STD_LOGIC;
  signal \num_refresh[3]_i_4_n_0\ : STD_LOGIC;
  signal \num_refresh[3]_i_5_n_0\ : STD_LOGIC;
  signal \num_refresh[3]_i_6_n_0\ : STD_LOGIC;
  signal num_refresh_reg : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \ocal_act_wait_cnt[3]_i_1_n_0\ : STD_LOGIC;
  signal \ocal_act_wait_cnt[3]_i_3_n_0\ : STD_LOGIC;
  signal ocal_act_wait_cnt_reg : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal oclk_wr_cnt0 : STD_LOGIC_VECTOR ( 3 downto 2 );
  signal \oclk_wr_cnt[0]_i_1_n_0\ : STD_LOGIC;
  signal \oclk_wr_cnt[1]_i_1_n_0\ : STD_LOGIC;
  signal \oclk_wr_cnt[3]_i_1_n_0\ : STD_LOGIC;
  signal \oclk_wr_cnt[3]_i_4_n_0\ : STD_LOGIC;
  signal oclk_wr_cnt_reg : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \odd_cwl.phy_cas_n[1]_i_1_n_0\ : STD_LOGIC;
  signal \odd_cwl.phy_cas_n[1]_i_2_n_0\ : STD_LOGIC;
  signal \odd_cwl.phy_cas_n[1]_i_3_n_0\ : STD_LOGIC;
  signal \odd_cwl.phy_cas_n[1]_i_4_n_0\ : STD_LOGIC;
  signal \odd_cwl.phy_ras_n[1]_i_1_n_0\ : STD_LOGIC;
  signal \odd_cwl.phy_we_n[1]_i_1_n_0\ : STD_LOGIC;
  signal \one_rank.stg1_wr_done_i_1_n_0\ : STD_LOGIC;
  signal \^one_rank.stg1_wr_done_reg_0\ : STD_LOGIC;
  signal \one_rank_complex.complex_wr_done_i_1_n_0\ : STD_LOGIC;
  signal \one_rank_complex.complex_wr_done_i_2_n_0\ : STD_LOGIC;
  signal \one_rank_complex.complex_wr_done_i_3_n_0\ : STD_LOGIC;
  signal \one_rank_complex.complex_wr_done_i_4_n_0\ : STD_LOGIC;
  signal p_0_in0_in : STD_LOGIC;
  signal \p_0_in__0\ : STD_LOGIC_VECTOR ( 9 downto 0 );
  signal \p_0_in__1\ : STD_LOGIC_VECTOR ( 8 downto 0 );
  signal \p_0_in__2\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \p_0_in__3\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \p_0_in__4\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \p_0_in__5\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \p_0_in__6\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \p_0_in__7\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \p_0_in__8\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal p_115_in : STD_LOGIC;
  signal p_17_in : STD_LOGIC_VECTOR ( 3 to 3 );
  signal p_81_in : STD_LOGIC;
  signal phy_bank : STD_LOGIC_VECTOR ( 11 downto 9 );
  signal phy_cas_n : STD_LOGIC_VECTOR ( 1 to 1 );
  signal phy_cs_n : STD_LOGIC_VECTOR ( 1 to 1 );
  signal phy_ras_n : STD_LOGIC_VECTOR ( 1 to 1 );
  signal \^phy_read_calib\ : STD_LOGIC;
  signal phy_reset_n : STD_LOGIC;
  signal phy_we_n : STD_LOGIC_VECTOR ( 1 to 1 );
  signal phy_wrdata : STD_LOGIC_VECTOR ( 511 downto 56 );
  signal phy_wrdata_en : STD_LOGIC;
  signal \^phy_write_calib\ : STD_LOGIC;
  signal \^pi_calib_done\ : STD_LOGIC;
  signal pi_calib_done_r : STD_LOGIC;
  signal pi_calib_done_r_i_1_n_0 : STD_LOGIC;
  signal pi_calib_rank_done_r : STD_LOGIC;
  signal \^pi_dqs_found_done_r1\ : STD_LOGIC;
  signal pi_dqs_found_start_i_1_n_0 : STD_LOGIC;
  signal pi_dqs_found_start_i_2_n_0 : STD_LOGIC;
  signal \^pi_dqs_found_start_reg_0\ : STD_LOGIC;
  signal pi_phase_locked_all_r1 : STD_LOGIC;
  attribute async_reg : string;
  attribute async_reg of pi_phase_locked_all_r1 : signal is "true";
  signal pi_phase_locked_all_r2 : STD_LOGIC;
  attribute async_reg of pi_phase_locked_all_r2 : signal is "true";
  signal pi_phase_locked_all_r3 : STD_LOGIC;
  attribute async_reg of pi_phase_locked_all_r3 : signal is "true";
  signal pi_phase_locked_all_r4 : STD_LOGIC;
  attribute async_reg of pi_phase_locked_all_r4 : signal is "true";
  signal prbs_gen_clk_en : STD_LOGIC;
  signal prbs_gen_clk_en0 : STD_LOGIC;
  signal prbs_gen_clk_en_i_1_n_0 : STD_LOGIC;
  signal prbs_gen_clk_en_i_3_n_0 : STD_LOGIC;
  signal prbs_gen_clk_en_i_4_n_0 : STD_LOGIC;
  signal prbs_gen_clk_en_i_5_n_0 : STD_LOGIC;
  signal prbs_gen_oclk_clk_en : STD_LOGIC;
  signal prbs_gen_oclk_clk_en_i_10_n_0 : STD_LOGIC;
  signal prbs_gen_oclk_clk_en_i_11_n_0 : STD_LOGIC;
  signal prbs_gen_oclk_clk_en_i_12_n_0 : STD_LOGIC;
  signal prbs_gen_oclk_clk_en_i_1_n_0 : STD_LOGIC;
  signal prbs_gen_oclk_clk_en_i_2_n_0 : STD_LOGIC;
  signal prbs_gen_oclk_clk_en_i_3_n_0 : STD_LOGIC;
  signal prbs_gen_oclk_clk_en_i_4_n_0 : STD_LOGIC;
  signal prbs_gen_oclk_clk_en_i_5_n_0 : STD_LOGIC;
  signal prbs_gen_oclk_clk_en_i_6_n_0 : STD_LOGIC;
  signal prbs_gen_oclk_clk_en_i_7_n_0 : STD_LOGIC;
  signal prbs_gen_oclk_clk_en_i_8_n_0 : STD_LOGIC;
  signal prbs_gen_oclk_clk_en_i_9_n_0 : STD_LOGIC;
  signal prbs_last_byte_done_r : STD_LOGIC;
  signal \^prbs_rdlvl_done_pulse_reg_0\ : STD_LOGIC;
  signal prbs_rdlvl_start_i_1_n_0 : STD_LOGIC;
  signal prbs_rdlvl_start_i_2_n_0 : STD_LOGIC;
  signal prbs_rdlvl_start_i_3_n_0 : STD_LOGIC;
  signal \^prbs_rdlvl_start_reg_0\ : STD_LOGIC;
  signal \prech_done_dly_r_reg[15]_srl16_n_0\ : STD_LOGIC;
  signal prech_done_pre : STD_LOGIC;
  signal prech_pending_r : STD_LOGIC;
  signal prech_pending_r_i_1_n_0 : STD_LOGIC;
  signal prech_pending_r_i_2_n_0 : STD_LOGIC;
  signal prech_pending_r_i_3_n_0 : STD_LOGIC;
  signal prech_pending_r_i_4_n_0 : STD_LOGIC;
  signal prech_pending_r_i_5_n_0 : STD_LOGIC;
  signal prech_pending_r_i_6_n_0 : STD_LOGIC;
  signal prech_req_posedge_r0 : STD_LOGIC;
  signal \^prech_req_posedge_r_reg_0\ : STD_LOGIC;
  signal prech_req_r : STD_LOGIC;
  signal pwron_ce_r : STD_LOGIC;
  signal pwron_ce_r_i_1_n_0 : STD_LOGIC;
  signal pwron_ce_r_i_2_n_0 : STD_LOGIC;
  signal rdlvl_last_byte_done_r : STD_LOGIC;
  signal rdlvl_start_dly0_r : STD_LOGIC_VECTOR ( 14 to 14 );
  signal \rdlvl_start_dly0_r_reg[13]_srl14_n_0\ : STD_LOGIC;
  signal rdlvl_start_pre : STD_LOGIC;
  signal rdlvl_start_pre_i_1_n_0 : STD_LOGIC;
  signal rdlvl_stg1_start_i_1_n_0 : STD_LOGIC;
  signal rdlvl_stg1_start_i_2_n_0 : STD_LOGIC;
  signal rdlvl_stg1_start_int : STD_LOGIC;
  signal rdlvl_stg1_start_int_i_1_n_0 : STD_LOGIC;
  signal rdlvl_stg1_start_int_i_2_n_0 : STD_LOGIC;
  signal \^rdlvl_stg1_start_int_reg_0\ : STD_LOGIC;
  signal \^rdlvl_stg1_start_reg_0\ : STD_LOGIC;
  signal read_calib_i_1_n_0 : STD_LOGIC;
  signal reg_ctrl_cnt_r : STD_LOGIC;
  signal \reg_ctrl_cnt_r[3]_i_1_n_0\ : STD_LOGIC;
  signal reg_ctrl_cnt_r_reg : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal reset_rd_addr_r1 : STD_LOGIC;
  signal \row_cnt_victim_rotate.complex_row_cnt[0]_i_1_n_0\ : STD_LOGIC;
  signal \row_cnt_victim_rotate.complex_row_cnt[1]_i_1_n_0\ : STD_LOGIC;
  signal \row_cnt_victim_rotate.complex_row_cnt[2]_i_1_n_0\ : STD_LOGIC;
  signal \row_cnt_victim_rotate.complex_row_cnt[3]_i_1_n_0\ : STD_LOGIC;
  signal \row_cnt_victim_rotate.complex_row_cnt[3]_i_2_n_0\ : STD_LOGIC;
  signal \row_cnt_victim_rotate.complex_row_cnt[4]_i_1_n_0\ : STD_LOGIC;
  signal \row_cnt_victim_rotate.complex_row_cnt[4]_i_3_n_0\ : STD_LOGIC;
  signal \row_cnt_victim_rotate.complex_row_cnt[4]_i_4_n_0\ : STD_LOGIC;
  signal \row_cnt_victim_rotate.complex_row_cnt[4]_i_5_n_0\ : STD_LOGIC;
  signal \row_cnt_victim_rotate.complex_row_cnt[4]_i_6_n_0\ : STD_LOGIC;
  signal \row_cnt_victim_rotate.complex_row_cnt[4]_i_7_n_0\ : STD_LOGIC;
  signal \row_cnt_victim_rotate.complex_row_cnt[4]_i_8_n_0\ : STD_LOGIC;
  signal \row_cnt_victim_rotate.complex_row_cnt[4]_i_9_n_0\ : STD_LOGIC;
  signal \row_cnt_victim_rotate.complex_row_cnt[5]_i_1_n_0\ : STD_LOGIC;
  signal \row_cnt_victim_rotate.complex_row_cnt[5]_i_2_n_0\ : STD_LOGIC;
  signal \row_cnt_victim_rotate.complex_row_cnt[6]_i_1_n_0\ : STD_LOGIC;
  signal \row_cnt_victim_rotate.complex_row_cnt[7]_i_1_n_0\ : STD_LOGIC;
  signal \row_cnt_victim_rotate.complex_row_cnt[7]_i_2_n_0\ : STD_LOGIC;
  signal \row_cnt_victim_rotate.complex_row_cnt[7]_i_3_n_0\ : STD_LOGIC;
  signal \row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[0]\ : STD_LOGIC;
  signal \row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[1]\ : STD_LOGIC;
  signal \row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[2]\ : STD_LOGIC;
  signal \row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[3]\ : STD_LOGIC;
  signal \row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[4]\ : STD_LOGIC;
  signal \row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[5]\ : STD_LOGIC;
  signal \row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[6]\ : STD_LOGIC;
  signal \row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[7]\ : STD_LOGIC;
  signal \^stg1_wr_done\ : STD_LOGIC;
  signal \stg1_wr_rd_cnt[0]_i_1_n_0\ : STD_LOGIC;
  signal \stg1_wr_rd_cnt[1]_i_1_n_0\ : STD_LOGIC;
  signal \stg1_wr_rd_cnt[2]_i_1_n_0\ : STD_LOGIC;
  signal \stg1_wr_rd_cnt[3]_i_1_n_0\ : STD_LOGIC;
  signal \stg1_wr_rd_cnt[3]_i_2_n_0\ : STD_LOGIC;
  signal \stg1_wr_rd_cnt[4]_i_1_n_0\ : STD_LOGIC;
  signal \stg1_wr_rd_cnt[4]_i_3_n_0\ : STD_LOGIC;
  signal \stg1_wr_rd_cnt[4]_i_4_n_0\ : STD_LOGIC;
  signal \stg1_wr_rd_cnt[5]_i_1_n_0\ : STD_LOGIC;
  signal \stg1_wr_rd_cnt[5]_i_2_n_0\ : STD_LOGIC;
  signal \stg1_wr_rd_cnt[6]_i_1_n_0\ : STD_LOGIC;
  signal \stg1_wr_rd_cnt[6]_i_2_n_0\ : STD_LOGIC;
  signal \stg1_wr_rd_cnt[7]_i_1_n_0\ : STD_LOGIC;
  signal \stg1_wr_rd_cnt[8]_i_1_n_0\ : STD_LOGIC;
  signal \stg1_wr_rd_cnt[8]_i_2_n_0\ : STD_LOGIC;
  signal \stg1_wr_rd_cnt[8]_i_3_n_0\ : STD_LOGIC;
  signal \stg1_wr_rd_cnt[8]_i_4_n_0\ : STD_LOGIC;
  signal \stg1_wr_rd_cnt[8]_i_5_n_0\ : STD_LOGIC;
  signal \stg1_wr_rd_cnt[8]_i_6_n_0\ : STD_LOGIC;
  signal \stg1_wr_rd_cnt_reg_n_0_[0]\ : STD_LOGIC;
  signal \stg1_wr_rd_cnt_reg_n_0_[1]\ : STD_LOGIC;
  signal \stg1_wr_rd_cnt_reg_n_0_[2]\ : STD_LOGIC;
  signal \stg1_wr_rd_cnt_reg_n_0_[3]\ : STD_LOGIC;
  signal \stg1_wr_rd_cnt_reg_n_0_[4]\ : STD_LOGIC;
  signal \stg1_wr_rd_cnt_reg_n_0_[5]\ : STD_LOGIC;
  signal \stg1_wr_rd_cnt_reg_n_0_[6]\ : STD_LOGIC;
  signal \stg1_wr_rd_cnt_reg_n_0_[7]\ : STD_LOGIC;
  signal \stg1_wr_rd_cnt_reg_n_0_[8]\ : STD_LOGIC;
  signal \victim_sel[0]_i_1_n_0\ : STD_LOGIC;
  signal \victim_sel[0]_i_2_n_0\ : STD_LOGIC;
  signal \victim_sel[1]_i_1_n_0\ : STD_LOGIC;
  signal \victim_sel[1]_i_2_n_0\ : STD_LOGIC;
  signal \victim_sel[2]_i_1_n_0\ : STD_LOGIC;
  signal \victim_sel[2]_i_2_n_0\ : STD_LOGIC;
  signal \victim_sel[2]_i_3_n_0\ : STD_LOGIC;
  signal \victim_sel[2]_i_4_n_0\ : STD_LOGIC;
  signal \victim_sel_reg_n_0_[0]\ : STD_LOGIC;
  signal \victim_sel_reg_n_0_[1]\ : STD_LOGIC;
  signal \victim_sel_reg_n_0_[2]\ : STD_LOGIC;
  signal \^wl_sm_start\ : STD_LOGIC;
  signal \wr_done_victim_rotate.complex_row0_wr_done_i_1_n_0\ : STD_LOGIC;
  signal \wr_done_victim_rotate.complex_row0_wr_done_i_3_n_0\ : STD_LOGIC;
  signal \wr_done_victim_rotate.complex_row1_wr_done_i_1_n_0\ : STD_LOGIC;
  signal wr_level_dqs_asrt : STD_LOGIC;
  signal wr_level_dqs_asrt_i_1_n_0 : STD_LOGIC;
  signal wr_level_dqs_asrt_r1 : STD_LOGIC;
  signal wr_lvl_start_i_1_n_0 : STD_LOGIC;
  signal \^wr_lvl_start_reg_0\ : STD_LOGIC;
  signal wr_victim_inc : STD_LOGIC;
  signal wr_victim_inc0 : STD_LOGIC;
  signal wr_victim_inc_i_2_n_0 : STD_LOGIC;
  signal wr_victim_inc_i_3_n_0 : STD_LOGIC;
  signal wr_victim_sel : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal \wr_victim_sel[0]_i_1_n_0\ : STD_LOGIC;
  signal \wr_victim_sel[1]_i_1_n_0\ : STD_LOGIC;
  signal \wr_victim_sel[2]_i_1_n_0\ : STD_LOGIC;
  signal \wr_victim_sel[2]_i_3_n_0\ : STD_LOGIC;
  signal wr_victim_sel_ocal : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal \wr_victim_sel_ocal[0]_i_1_n_0\ : STD_LOGIC;
  signal \wr_victim_sel_ocal[1]_i_1_n_0\ : STD_LOGIC;
  signal \wr_victim_sel_ocal[2]_i_1_n_0\ : STD_LOGIC;
  signal \wr_victim_sel_ocal[2]_i_2_n_0\ : STD_LOGIC;
  signal wrcal_final_chk : STD_LOGIC;
  signal wrcal_final_chk_i_1_n_0 : STD_LOGIC;
  signal wrcal_final_chk_i_2_n_0 : STD_LOGIC;
  signal wrcal_rd_wait_i_1_n_0 : STD_LOGIC;
  signal wrcal_reads : STD_LOGIC;
  signal wrcal_reads05_out : STD_LOGIC;
  signal \wrcal_reads[0]_i_1_n_0\ : STD_LOGIC;
  signal \wrcal_reads[1]_i_1_n_0\ : STD_LOGIC;
  signal \wrcal_reads[2]_i_1_n_0\ : STD_LOGIC;
  signal \wrcal_reads[3]_i_1_n_0\ : STD_LOGIC;
  signal \wrcal_reads[4]_i_1_n_0\ : STD_LOGIC;
  signal \wrcal_reads[5]_i_1_n_0\ : STD_LOGIC;
  signal \wrcal_reads[6]_i_1_n_0\ : STD_LOGIC;
  signal \wrcal_reads[7]_i_10_n_0\ : STD_LOGIC;
  signal \wrcal_reads[7]_i_2_n_0\ : STD_LOGIC;
  signal \wrcal_reads[7]_i_3_n_0\ : STD_LOGIC;
  signal \wrcal_reads[7]_i_4_n_0\ : STD_LOGIC;
  signal \wrcal_reads[7]_i_5_n_0\ : STD_LOGIC;
  signal \wrcal_reads[7]_i_6_n_0\ : STD_LOGIC;
  signal \wrcal_reads[7]_i_7_n_0\ : STD_LOGIC;
  signal \wrcal_reads[7]_i_8_n_0\ : STD_LOGIC;
  signal \wrcal_reads_reg_n_0_[0]\ : STD_LOGIC;
  signal \wrcal_reads_reg_n_0_[1]\ : STD_LOGIC;
  signal \wrcal_reads_reg_n_0_[2]\ : STD_LOGIC;
  signal \wrcal_reads_reg_n_0_[3]\ : STD_LOGIC;
  signal \wrcal_reads_reg_n_0_[4]\ : STD_LOGIC;
  signal \wrcal_reads_reg_n_0_[5]\ : STD_LOGIC;
  signal \wrcal_reads_reg_n_0_[6]\ : STD_LOGIC;
  signal \wrcal_reads_reg_n_0_[7]\ : STD_LOGIC;
  signal wrcal_resume_r : STD_LOGIC;
  signal wrcal_start_dly_r : STD_LOGIC_VECTOR ( 5 to 5 );
  signal \wrcal_start_dly_r_reg[4]_srl5_n_0\ : STD_LOGIC;
  signal wrcal_start_i_1_n_0 : STD_LOGIC;
  signal wrcal_start_pre : STD_LOGIC;
  signal \^wrcal_start_reg_0\ : STD_LOGIC;
  signal wrcal_wr_cnt0 : STD_LOGIC_VECTOR ( 3 downto 2 );
  signal \wrcal_wr_cnt[0]_i_1_n_0\ : STD_LOGIC;
  signal \wrcal_wr_cnt[1]_i_1_n_0\ : STD_LOGIC;
  signal \wrcal_wr_cnt[3]_i_1_n_0\ : STD_LOGIC;
  signal \wrcal_wr_cnt[3]_i_2_n_0\ : STD_LOGIC;
  signal \wrcal_wr_cnt[3]_i_4_n_0\ : STD_LOGIC;
  signal wrcal_wr_cnt_reg : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \wrdq_div1_4to1_wrcal_first.phy_wrdata[190]_i_1_n_0\ : STD_LOGIC;
  signal \wrdq_div1_4to1_wrcal_first.phy_wrdata[511]_i_1_n_0\ : STD_LOGIC;
  signal write_calib_i_1_n_0 : STD_LOGIC;
  signal write_calib_i_2_n_0 : STD_LOGIC;
  signal wrlvl_active : STD_LOGIC;
  signal wrlvl_active_i_1_n_0 : STD_LOGIC;
  signal wrlvl_active_r1 : STD_LOGIC;
  signal wrlvl_done_r : STD_LOGIC;
  signal \^wrlvl_done_r1\ : STD_LOGIC;
  signal \^wrlvl_final_if_rst\ : STD_LOGIC;
  signal wrlvl_final_if_rst_i_1_n_0 : STD_LOGIC;
  signal wrlvl_final_if_rst_i_2_n_0 : STD_LOGIC;
  signal wrlvl_final_if_rst_i_3_n_0 : STD_LOGIC;
  signal wrlvl_odt : STD_LOGIC;
  signal wrlvl_odt_ctl : STD_LOGIC;
  signal wrlvl_odt_ctl_i_1_n_0 : STD_LOGIC;
  signal wrlvl_odt_ctl_i_2_n_0 : STD_LOGIC;
  signal wrlvl_rank_done_r1 : STD_LOGIC;
  signal wrlvl_rank_done_r6_reg_srl5_n_0 : STD_LOGIC;
  signal wrlvl_rank_done_r7 : STD_LOGIC;
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \DDR3_1rank.phy_int_cs_n[1]_i_10\ : label is "soft_lutpair425";
  attribute SOFT_HLUTNM of \DDR3_1rank.phy_int_cs_n[1]_i_2\ : label is "soft_lutpair486";
  attribute SOFT_HLUTNM of \DDR3_1rank.phy_int_cs_n[1]_i_9\ : label is "soft_lutpair423";
  attribute SOFT_HLUTNM of app_rd_data_valid_INST_0 : label is "soft_lutpair532";
  attribute SOFT_HLUTNM of \calib_cmd[0]_i_1\ : label is "soft_lutpair510";
  attribute SOFT_HLUTNM of \calib_cmd[1]_i_1\ : label is "soft_lutpair531";
  attribute SOFT_HLUTNM of \calib_cmd[2]_i_1\ : label is "soft_lutpair531";
  attribute SOFT_HLUTNM of \calib_cmd[2]_i_2\ : label is "soft_lutpair455";
  attribute SOFT_HLUTNM of \calib_data_offset_0[3]_i_1\ : label is "soft_lutpair506";
  attribute SOFT_HLUTNM of \calib_data_offset_1[3]_i_1\ : label is "soft_lutpair510";
  attribute SOFT_HLUTNM of \calib_data_offset_2[3]_i_1\ : label is "soft_lutpair506";
  attribute SOFT_HLUTNM of \calib_odt[0]_i_1\ : label is "soft_lutpair455";
  attribute SOFT_HLUTNM of \calib_seq[0]_i_1\ : label is "soft_lutpair450";
  attribute SOFT_HLUTNM of \calib_seq[1]_i_1\ : label is "soft_lutpair450";
  attribute SOFT_HLUTNM of calib_wrdata_en_i_2 : label is "soft_lutpair388";
  attribute SOFT_HLUTNM of cnt_cmd_done_m7_r_i_2 : label is "soft_lutpair518";
  attribute SOFT_HLUTNM of \cnt_cmd_r[0]_i_1\ : label is "soft_lutpair520";
  attribute SOFT_HLUTNM of \cnt_cmd_r[1]_i_1\ : label is "soft_lutpair520";
  attribute SOFT_HLUTNM of \cnt_cmd_r[2]_i_1\ : label is "soft_lutpair518";
  attribute SOFT_HLUTNM of \cnt_cmd_r[3]_i_1\ : label is "soft_lutpair424";
  attribute SOFT_HLUTNM of \cnt_cmd_r[4]_i_1\ : label is "soft_lutpair424";
  attribute SOFT_HLUTNM of cnt_dllk_zqinit_done_r_i_1 : label is "soft_lutpair471";
  attribute SOFT_HLUTNM of \cnt_dllk_zqinit_r[1]_i_1\ : label is "soft_lutpair519";
  attribute SOFT_HLUTNM of \cnt_dllk_zqinit_r[2]_i_1\ : label is "soft_lutpair519";
  attribute SOFT_HLUTNM of \cnt_dllk_zqinit_r[3]_i_1\ : label is "soft_lutpair419";
  attribute SOFT_HLUTNM of \cnt_dllk_zqinit_r[4]_i_1\ : label is "soft_lutpair419";
  attribute SOFT_HLUTNM of \cnt_dllk_zqinit_r[7]_i_2\ : label is "soft_lutpair471";
  attribute SOFT_HLUTNM of cnt_init_af_done_r_i_1 : label is "soft_lutpair392";
  attribute SOFT_HLUTNM of \cnt_init_af_r[1]_i_1\ : label is "soft_lutpair392";
  attribute SOFT_HLUTNM of \cnt_init_mr_r[0]_i_2\ : label is "soft_lutpair522";
  attribute SOFT_HLUTNM of \cnt_init_mr_r[0]_i_3\ : label is "soft_lutpair488";
  attribute SOFT_HLUTNM of \cnt_pwron_ce_r[1]_i_1\ : label is "soft_lutpair502";
  attribute SOFT_HLUTNM of \cnt_pwron_ce_r[2]_i_1\ : label is "soft_lutpair502";
  attribute SOFT_HLUTNM of \cnt_pwron_ce_r[3]_i_1\ : label is "soft_lutpair435";
  attribute SOFT_HLUTNM of \cnt_pwron_ce_r[4]_i_1\ : label is "soft_lutpair435";
  attribute SOFT_HLUTNM of \cnt_pwron_ce_r[6]_i_1\ : label is "soft_lutpair507";
  attribute SOFT_HLUTNM of \cnt_pwron_ce_r[7]_i_1\ : label is "soft_lutpair507";
  attribute SOFT_HLUTNM of \cnt_pwron_ce_r[8]_i_1\ : label is "soft_lutpair433";
  attribute SOFT_HLUTNM of \cnt_pwron_ce_r[9]_i_1\ : label is "soft_lutpair433";
  attribute SOFT_HLUTNM of cnt_pwron_cke_done_r_i_3 : label is "soft_lutpair498";
  attribute SOFT_HLUTNM of \cnt_pwron_r[0]_i_1\ : label is "soft_lutpair526";
  attribute SOFT_HLUTNM of \cnt_pwron_r[1]_i_1\ : label is "soft_lutpair526";
  attribute SOFT_HLUTNM of \cnt_pwron_r[2]_i_1\ : label is "soft_lutpair498";
  attribute SOFT_HLUTNM of \cnt_pwron_r[3]_i_1\ : label is "soft_lutpair428";
  attribute SOFT_HLUTNM of \cnt_pwron_r[4]_i_1\ : label is "soft_lutpair428";
  attribute SOFT_HLUTNM of \cnt_pwron_r[7]_i_1\ : label is "soft_lutpair464";
  attribute SOFT_HLUTNM of \cnt_pwron_r[8]_i_1\ : label is "soft_lutpair464";
  attribute SOFT_HLUTNM of cnt_txpr_done_r_i_2 : label is "soft_lutpair472";
  attribute SOFT_HLUTNM of \cnt_txpr_r[0]_i_1\ : label is "soft_lutpair527";
  attribute SOFT_HLUTNM of \cnt_txpr_r[1]_i_1\ : label is "soft_lutpair527";
  attribute SOFT_HLUTNM of \cnt_txpr_r[2]_i_1\ : label is "soft_lutpair472";
  attribute SOFT_HLUTNM of \cnt_txpr_r[3]_i_1\ : label is "soft_lutpair420";
  attribute SOFT_HLUTNM of \cnt_txpr_r[4]_i_1\ : label is "soft_lutpair420";
  attribute SOFT_HLUTNM of \cnt_txpr_r[6]_i_1\ : label is "soft_lutpair512";
  attribute SOFT_HLUTNM of \cnt_txpr_r[7]_i_2\ : label is "soft_lutpair512";
  attribute SOFT_HLUTNM of complex_act_start_i_2 : label is "soft_lutpair476";
  attribute SOFT_HLUTNM of complex_byte_rd_done_i_1 : label is "soft_lutpair391";
  attribute SOFT_HLUTNM of \complex_num_reads[1]_i_2\ : label is "soft_lutpair458";
  attribute SOFT_HLUTNM of \complex_num_reads[2]_i_5\ : label is "soft_lutpair477";
  attribute SOFT_HLUTNM of \complex_num_reads[3]_i_4\ : label is "soft_lutpair477";
  attribute SOFT_HLUTNM of \complex_num_writes[2]_i_4\ : label is "soft_lutpair487";
  attribute SOFT_HLUTNM of \complex_num_writes[2]_i_7\ : label is "soft_lutpair415";
  attribute SOFT_HLUTNM of \complex_num_writes[2]_i_8\ : label is "soft_lutpair458";
  attribute SOFT_HLUTNM of \complex_num_writes[2]_i_9\ : label is "soft_lutpair453";
  attribute SOFT_HLUTNM of \complex_num_writes[4]_i_11\ : label is "soft_lutpair439";
  attribute SOFT_HLUTNM of \complex_num_writes[4]_i_14\ : label is "soft_lutpair481";
  attribute SOFT_HLUTNM of \complex_num_writes[4]_i_15\ : label is "soft_lutpair386";
  attribute SOFT_HLUTNM of \complex_num_writes[4]_i_2\ : label is "soft_lutpair487";
  attribute SOFT_HLUTNM of \complex_num_writes[4]_i_6\ : label is "soft_lutpair385";
  attribute SOFT_HLUTNM of \complex_num_writes[4]_i_8\ : label is "soft_lutpair439";
  attribute SOFT_HLUTNM of \complex_num_writes[4]_i_9\ : label is "soft_lutpair415";
  attribute SOFT_HLUTNM of \complex_num_writes_dec[2]_i_1\ : label is "soft_lutpair390";
  attribute SOFT_HLUTNM of \complex_num_writes_dec[4]_i_5\ : label is "soft_lutpair390";
  attribute SOFT_HLUTNM of complex_ocal_odt_ext_i_3 : label is "soft_lutpair423";
  attribute SOFT_HLUTNM of complex_ocal_reset_rd_addr_i_2 : label is "soft_lutpair530";
  attribute SOFT_HLUTNM of complex_ocal_wr_start_i_1 : label is "soft_lutpair490";
  attribute SOFT_HLUTNM of complex_oclkdelay_calib_start_int_i_1 : label is "soft_lutpair440";
  attribute SOFT_HLUTNM of complex_oclkdelay_calib_start_int_i_2 : label is "soft_lutpair408";
  attribute SOFT_HLUTNM of complex_row0_rd_done_i_1 : label is "soft_lutpair461";
  attribute SOFT_HLUTNM of \complex_row_cnt_ocal[1]_i_1\ : label is "soft_lutpair500";
  attribute SOFT_HLUTNM of \complex_row_cnt_ocal[2]_i_1\ : label is "soft_lutpair500";
  attribute SOFT_HLUTNM of \complex_row_cnt_ocal[3]_i_3\ : label is "soft_lutpair451";
  attribute SOFT_HLUTNM of \complex_row_cnt_ocal[3]_i_4\ : label is "soft_lutpair451";
  attribute SOFT_HLUTNM of complex_sample_cnt_inc_i_2 : label is "soft_lutpair385";
  attribute SOFT_HLUTNM of complex_sample_cnt_inc_i_3 : label is "soft_lutpair386";
  attribute SOFT_HLUTNM of \complex_wait_cnt[1]_i_1\ : label is "soft_lutpair530";
  attribute SOFT_HLUTNM of \complex_wait_cnt[2]_i_1\ : label is "soft_lutpair437";
  attribute SOFT_HLUTNM of \complex_wait_cnt[3]_i_2\ : label is "soft_lutpair422";
  attribute SOFT_HLUTNM of \data_offset_1_i1[0]_i_1\ : label is "soft_lutpair496";
  attribute SOFT_HLUTNM of \data_offset_1_i1[1]_i_1\ : label is "soft_lutpair497";
  attribute SOFT_HLUTNM of \data_offset_1_i1[2]_i_1\ : label is "soft_lutpair499";
  attribute SOFT_HLUTNM of \data_offset_1_i1[3]_i_1\ : label is "soft_lutpair501";
  attribute SOFT_HLUTNM of \data_offset_1_i1[4]_i_1\ : label is "soft_lutpair501";
  attribute SOFT_HLUTNM of \data_offset_1_i1[5]_i_1\ : label is "soft_lutpair497";
  attribute SOFT_HLUTNM of \data_offset_2_i1[0]_i_1\ : label is "soft_lutpair496";
  attribute SOFT_HLUTNM of \data_offset_2_i1[1]_i_1\ : label is "soft_lutpair499";
  attribute SOFT_HLUTNM of \data_offset_2_i1[2]_i_1\ : label is "soft_lutpair508";
  attribute SOFT_HLUTNM of \data_offset_2_i1[3]_i_1\ : label is "soft_lutpair508";
  attribute SOFT_HLUTNM of \data_offset_2_i1[4]_i_1\ : label is "soft_lutpair516";
  attribute SOFT_HLUTNM of \data_offset_2_i1[5]_i_1\ : label is "soft_lutpair516";
  attribute SOFT_HLUTNM of ddr2_refresh_flag_r_i_2 : label is "soft_lutpair463";
  attribute SOFT_HLUTNM of ddr2_refresh_flag_r_i_3 : label is "soft_lutpair427";
  attribute SOFT_HLUTNM of detect_pi_found_dqs_i_2 : label is "soft_lutpair440";
  attribute SOFT_HLUTNM of \en_cnt_div4.enable_wrlvl_cnt[3]_i_3\ : label is "soft_lutpair434";
  attribute SOFT_HLUTNM of \en_cnt_div4.wrlvl_odt_i_2\ : label is "soft_lutpair434";
  attribute SOFT_HLUTNM of \gen_no_mirror.div_clk_loop[0].phy_address[0]_i_2\ : label is "soft_lutpair476";
  attribute SOFT_HLUTNM of \gen_no_mirror.div_clk_loop[0].phy_address[0]_i_4\ : label is "soft_lutpair467";
  attribute SOFT_HLUTNM of \gen_no_mirror.div_clk_loop[0].phy_address[10]_i_3\ : label is "soft_lutpair489";
  attribute SOFT_HLUTNM of \gen_no_mirror.div_clk_loop[0].phy_address[12]_i_2\ : label is "soft_lutpair456";
  attribute SOFT_HLUTNM of \gen_no_mirror.div_clk_loop[0].phy_address[1]_i_2\ : label is "soft_lutpair416";
  attribute SOFT_HLUTNM of \gen_no_mirror.div_clk_loop[0].phy_address[1]_i_4\ : label is "soft_lutpair465";
  attribute SOFT_HLUTNM of \gen_no_mirror.div_clk_loop[0].phy_address[2]_i_3\ : label is "soft_lutpair474";
  attribute SOFT_HLUTNM of \gen_no_mirror.div_clk_loop[0].phy_address[2]_i_6\ : label is "soft_lutpair416";
  attribute SOFT_HLUTNM of \gen_no_mirror.div_clk_loop[0].phy_address[4]_i_3\ : label is "soft_lutpair462";
  attribute SOFT_HLUTNM of \gen_no_mirror.div_clk_loop[0].phy_address[4]_i_4\ : label is "soft_lutpair465";
  attribute SOFT_HLUTNM of \gen_no_mirror.div_clk_loop[0].phy_address[5]_i_3\ : label is "soft_lutpair468";
  attribute SOFT_HLUTNM of \gen_no_mirror.div_clk_loop[0].phy_address[5]_i_5\ : label is "soft_lutpair467";
  attribute SOFT_HLUTNM of \gen_no_mirror.div_clk_loop[0].phy_address[5]_i_6\ : label is "soft_lutpair484";
  attribute SOFT_HLUTNM of \gen_no_mirror.div_clk_loop[0].phy_address[6]_i_10\ : label is "soft_lutpair413";
  attribute SOFT_HLUTNM of \gen_no_mirror.div_clk_loop[0].phy_address[6]_i_3\ : label is "soft_lutpair468";
  attribute SOFT_HLUTNM of \gen_no_mirror.div_clk_loop[0].phy_address[6]_i_4\ : label is "soft_lutpair474";
  attribute SOFT_HLUTNM of \gen_no_mirror.div_clk_loop[0].phy_address[6]_i_5\ : label is "soft_lutpair489";
  attribute SOFT_HLUTNM of \gen_no_mirror.div_clk_loop[0].phy_address[6]_i_6\ : label is "soft_lutpair485";
  attribute SOFT_HLUTNM of \gen_no_mirror.div_clk_loop[0].phy_address[6]_i_7\ : label is "soft_lutpair484";
  attribute SOFT_HLUTNM of \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_12\ : label is "soft_lutpair414";
  attribute SOFT_HLUTNM of \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_2\ : label is "soft_lutpair452";
  attribute SOFT_HLUTNM of \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_4\ : label is "soft_lutpair432";
  attribute SOFT_HLUTNM of \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_9\ : label is "soft_lutpair413";
  attribute SOFT_HLUTNM of \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_10\ : label is "soft_lutpair473";
  attribute SOFT_HLUTNM of \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_12\ : label is "soft_lutpair414";
  attribute SOFT_HLUTNM of \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_13\ : label is "soft_lutpair473";
  attribute SOFT_HLUTNM of \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_17\ : label is "soft_lutpair481";
  attribute SOFT_HLUTNM of \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_2\ : label is "soft_lutpair432";
  attribute SOFT_HLUTNM of \gen_no_mirror.div_clk_loop[0].phy_bank[1]_i_1\ : label is "soft_lutpair466";
  attribute KEEP : string;
  attribute KEEP of init_complete_r1_timing_reg : label is "yes";
  attribute KEEP of init_complete_r_timing_reg : label is "yes";
  attribute SOFT_HLUTNM of \init_state_r[0]_i_2\ : label is "soft_lutpair429";
  attribute SOFT_HLUTNM of \init_state_r[0]_i_23\ : label is "soft_lutpair417";
  attribute SOFT_HLUTNM of \init_state_r[0]_i_26\ : label is "soft_lutpair399";
  attribute SOFT_HLUTNM of \init_state_r[0]_i_29\ : label is "soft_lutpair521";
  attribute SOFT_HLUTNM of \init_state_r[0]_i_30\ : label is "soft_lutpair442";
  attribute SOFT_HLUTNM of \init_state_r[1]_i_11\ : label is "soft_lutpair401";
  attribute SOFT_HLUTNM of \init_state_r[1]_i_19\ : label is "soft_lutpair403";
  attribute SOFT_HLUTNM of \init_state_r[1]_i_23\ : label is "soft_lutpair396";
  attribute SOFT_HLUTNM of \init_state_r[1]_i_24\ : label is "soft_lutpair480";
  attribute SOFT_HLUTNM of \init_state_r[1]_i_27\ : label is "soft_lutpair444";
  attribute SOFT_HLUTNM of \init_state_r[1]_i_29\ : label is "soft_lutpair480";
  attribute SOFT_HLUTNM of \init_state_r[1]_i_31\ : label is "soft_lutpair403";
  attribute SOFT_HLUTNM of \init_state_r[2]_i_13\ : label is "soft_lutpair405";
  attribute SOFT_HLUTNM of \init_state_r[2]_i_16\ : label is "soft_lutpair443";
  attribute SOFT_HLUTNM of \init_state_r[2]_i_2\ : label is "soft_lutpair430";
  attribute SOFT_HLUTNM of \init_state_r[2]_i_21\ : label is "soft_lutpair448";
  attribute SOFT_HLUTNM of \init_state_r[2]_i_24\ : label is "soft_lutpair404";
  attribute SOFT_HLUTNM of \init_state_r[2]_i_25\ : label is "soft_lutpair431";
  attribute SOFT_HLUTNM of \init_state_r[2]_i_30\ : label is "soft_lutpair444";
  attribute SOFT_HLUTNM of \init_state_r[2]_i_32\ : label is "soft_lutpair396";
  attribute SOFT_HLUTNM of \init_state_r[2]_i_38\ : label is "soft_lutpair460";
  attribute SOFT_HLUTNM of \init_state_r[2]_i_40\ : label is "soft_lutpair436";
  attribute SOFT_HLUTNM of \init_state_r[2]_i_41\ : label is "soft_lutpair404";
  attribute SOFT_HLUTNM of \init_state_r[2]_i_42\ : label is "soft_lutpair395";
  attribute SOFT_HLUTNM of \init_state_r[2]_i_43\ : label is "soft_lutpair397";
  attribute SOFT_HLUTNM of \init_state_r[2]_i_6\ : label is "soft_lutpair412";
  attribute SOFT_HLUTNM of \init_state_r[3]_i_16\ : label is "soft_lutpair488";
  attribute SOFT_HLUTNM of \init_state_r[3]_i_17\ : label is "soft_lutpair522";
  attribute SOFT_HLUTNM of \init_state_r[3]_i_18\ : label is "soft_lutpair521";
  attribute SOFT_HLUTNM of \init_state_r[3]_i_20\ : label is "soft_lutpair406";
  attribute SOFT_HLUTNM of \init_state_r[3]_i_21\ : label is "soft_lutpair398";
  attribute SOFT_HLUTNM of \init_state_r[3]_i_22\ : label is "soft_lutpair395";
  attribute SOFT_HLUTNM of \init_state_r[3]_i_24\ : label is "soft_lutpair436";
  attribute SOFT_HLUTNM of \init_state_r[3]_i_6\ : label is "soft_lutpair452";
  attribute SOFT_HLUTNM of \init_state_r[4]_i_12\ : label is "soft_lutpair443";
  attribute SOFT_HLUTNM of \init_state_r[4]_i_13\ : label is "soft_lutpair417";
  attribute SOFT_HLUTNM of \init_state_r[4]_i_14\ : label is "soft_lutpair482";
  attribute SOFT_HLUTNM of \init_state_r[4]_i_16\ : label is "soft_lutpair387";
  attribute SOFT_HLUTNM of \init_state_r[4]_i_18\ : label is "soft_lutpair421";
  attribute SOFT_HLUTNM of \init_state_r[4]_i_19\ : label is "soft_lutpair438";
  attribute SOFT_HLUTNM of \init_state_r[4]_i_25\ : label is "soft_lutpair447";
  attribute SOFT_HLUTNM of \init_state_r[4]_i_4\ : label is "soft_lutpair529";
  attribute SOFT_HLUTNM of \init_state_r[5]_i_12\ : label is "soft_lutpair398";
  attribute SOFT_HLUTNM of \init_state_r[5]_i_13\ : label is "soft_lutpair397";
  attribute SOFT_HLUTNM of \init_state_r[5]_i_15\ : label is "soft_lutpair448";
  attribute SOFT_HLUTNM of \init_state_r[5]_i_18\ : label is "soft_lutpair438";
  attribute SOFT_HLUTNM of \init_state_r[5]_i_19\ : label is "soft_lutpair469";
  attribute SOFT_HLUTNM of \init_state_r[5]_i_27\ : label is "soft_lutpair411";
  attribute SOFT_HLUTNM of \init_state_r[5]_i_29\ : label is "soft_lutpair421";
  attribute SOFT_HLUTNM of \init_state_r[5]_i_30\ : label is "soft_lutpair407";
  attribute SOFT_HLUTNM of \init_state_r[5]_i_31\ : label is "soft_lutpair463";
  attribute SOFT_HLUTNM of \init_state_r[5]_i_32\ : label is "soft_lutpair411";
  attribute SOFT_HLUTNM of \init_state_r[5]_i_33\ : label is "soft_lutpair410";
  attribute SOFT_HLUTNM of \init_state_r[5]_i_34\ : label is "soft_lutpair410";
  attribute SOFT_HLUTNM of \init_state_r[5]_i_35\ : label is "soft_lutpair406";
  attribute SOFT_HLUTNM of \init_state_r[5]_i_37\ : label is "soft_lutpair449";
  attribute SOFT_HLUTNM of \init_state_r[5]_i_39\ : label is "soft_lutpair483";
  attribute SOFT_HLUTNM of \init_state_r[5]_i_41\ : label is "soft_lutpair447";
  attribute SOFT_HLUTNM of \init_state_r[5]_i_42\ : label is "soft_lutpair400";
  attribute SOFT_HLUTNM of \init_state_r[5]_i_43\ : label is "soft_lutpair483";
  attribute SOFT_HLUTNM of \init_state_r[5]_i_44\ : label is "soft_lutpair412";
  attribute SOFT_HLUTNM of \init_state_r[5]_i_46\ : label is "soft_lutpair442";
  attribute SOFT_HLUTNM of \init_state_r[5]_i_49\ : label is "soft_lutpair475";
  attribute SOFT_HLUTNM of \init_state_r[5]_i_50\ : label is "soft_lutpair445";
  attribute SOFT_HLUTNM of \init_state_r[6]_i_12\ : label is "soft_lutpair429";
  attribute SOFT_HLUTNM of \init_state_r[6]_i_14\ : label is "soft_lutpair437";
  attribute SOFT_HLUTNM of \init_state_r[6]_i_15\ : label is "soft_lutpair387";
  attribute SOFT_HLUTNM of \init_state_r[6]_i_2\ : label is "soft_lutpair485";
  attribute SOFT_HLUTNM of \init_state_r[6]_i_21\ : label is "soft_lutpair400";
  attribute SOFT_HLUTNM of \init_state_r[6]_i_22\ : label is "soft_lutpair456";
  attribute SOFT_HLUTNM of \init_state_r[6]_i_23\ : label is "soft_lutpair405";
  attribute SOFT_HLUTNM of \init_state_r[6]_i_24\ : label is "soft_lutpair401";
  attribute SOFT_HLUTNM of \init_state_r[6]_i_25\ : label is "soft_lutpair399";
  attribute SOFT_HLUTNM of \init_state_r[6]_i_9\ : label is "soft_lutpair446";
  attribute SOFT_HLUTNM of mpr_rdlvl_start_i_1 : label is "soft_lutpair469";
  attribute SOFT_HLUTNM of mux_rd_valid_r_i_1 : label is "soft_lutpair525";
  attribute SOFT_HLUTNM of new_cnt_dqs_r_i_2 : label is "soft_lutpair525";
  attribute SOFT_HLUTNM of \num_refresh[1]_i_1\ : label is "soft_lutpair513";
  attribute SOFT_HLUTNM of \num_refresh[2]_i_1\ : label is "soft_lutpair513";
  attribute SOFT_HLUTNM of \num_refresh[3]_i_3\ : label is "soft_lutpair460";
  attribute SOFT_HLUTNM of \ocal_act_wait_cnt[1]_i_1\ : label is "soft_lutpair495";
  attribute SOFT_HLUTNM of \ocal_act_wait_cnt[2]_i_1\ : label is "soft_lutpair495";
  attribute SOFT_HLUTNM of \ocal_act_wait_cnt[3]_i_2\ : label is "soft_lutpair457";
  attribute SOFT_HLUTNM of \ocal_act_wait_cnt[3]_i_3\ : label is "soft_lutpair457";
  attribute SOFT_HLUTNM of \oclk_wr_cnt[0]_i_1\ : label is "soft_lutpair523";
  attribute SOFT_HLUTNM of \oclk_wr_cnt[1]_i_1\ : label is "soft_lutpair523";
  attribute SOFT_HLUTNM of \oclk_wr_cnt[3]_i_3\ : label is "soft_lutpair431";
  attribute SOFT_HLUTNM of \odd_cwl.phy_cas_n[1]_i_3\ : label is "soft_lutpair446";
  attribute SOFT_HLUTNM of \odd_cwl.phy_cas_n[1]_i_4\ : label is "soft_lutpair408";
  attribute SOFT_HLUTNM of \odd_cwl.phy_we_n[1]_i_1\ : label is "soft_lutpair486";
  attribute SOFT_HLUTNM of \one_rank_complex.complex_wr_done_i_4\ : label is "soft_lutpair422";
  attribute SOFT_HLUTNM of \out_fifo_i_38__9\ : label is "soft_lutpair462";
  attribute SOFT_HLUTNM of \phy_ctl_wd_i1[0]_i_1\ : label is "soft_lutpair509";
  attribute SOFT_HLUTNM of \phy_ctl_wd_i1[17]_i_1\ : label is "soft_lutpair511";
  attribute SOFT_HLUTNM of \phy_ctl_wd_i1[18]_i_1\ : label is "soft_lutpair515";
  attribute SOFT_HLUTNM of \phy_ctl_wd_i1[19]_i_1\ : label is "soft_lutpair517";
  attribute SOFT_HLUTNM of \phy_ctl_wd_i1[1]_i_1\ : label is "soft_lutpair509";
  attribute SOFT_HLUTNM of \phy_ctl_wd_i1[21]_i_1\ : label is "soft_lutpair517";
  attribute SOFT_HLUTNM of \phy_ctl_wd_i1[22]_i_1\ : label is "soft_lutpair515";
  attribute SOFT_HLUTNM of \phy_ctl_wd_i1[2]_i_1\ : label is "soft_lutpair511";
  attribute ASYNC_REG_boolean : boolean;
  attribute ASYNC_REG_boolean of pi_phase_locked_all_r1_reg : label is std.standard.true;
  attribute KEEP of pi_phase_locked_all_r1_reg : label is "yes";
  attribute ASYNC_REG_boolean of pi_phase_locked_all_r2_reg : label is std.standard.true;
  attribute KEEP of pi_phase_locked_all_r2_reg : label is "yes";
  attribute ASYNC_REG_boolean of pi_phase_locked_all_r3_reg : label is std.standard.true;
  attribute KEEP of pi_phase_locked_all_r3_reg : label is "yes";
  attribute ASYNC_REG_boolean of pi_phase_locked_all_r4_reg : label is std.standard.true;
  attribute KEEP of pi_phase_locked_all_r4_reg : label is "yes";
  attribute SOFT_HLUTNM of prbs_gen_clk_en_i_4 : label is "soft_lutpair425";
  attribute SOFT_HLUTNM of prbs_gen_clk_en_i_5 : label is "soft_lutpair402";
  attribute SOFT_HLUTNM of prbs_gen_oclk_clk_en_i_12 : label is "soft_lutpair427";
  attribute SOFT_HLUTNM of prbs_gen_oclk_clk_en_i_2 : label is "soft_lutpair494";
  attribute SOFT_HLUTNM of prbs_gen_oclk_clk_en_i_8 : label is "soft_lutpair402";
  attribute SOFT_HLUTNM of prbs_rdlvl_start_i_2 : label is "soft_lutpair445";
  attribute SOFT_HLUTNM of prbs_rdlvl_start_i_3 : label is "soft_lutpair388";
  attribute srl_bus_name : string;
  attribute srl_bus_name of \prech_done_dly_r_reg[15]_srl16\ : label is "\u_mig_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/prech_done_dly_r_reg ";
  attribute srl_name : string;
  attribute srl_name of \prech_done_dly_r_reg[15]_srl16\ : label is "\u_mig_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/prech_done_dly_r_reg[15]_srl16 ";
  attribute SOFT_HLUTNM of \prech_done_dly_r_reg[15]_srl16_i_1\ : label is "soft_lutpair478";
  attribute SOFT_HLUTNM of prech_pending_r_i_1 : label is "soft_lutpair478";
  attribute SOFT_HLUTNM of \rd_addr[7]_i_1\ : label is "soft_lutpair490";
  attribute srl_bus_name of \rdlvl_start_dly0_r_reg[13]_srl14\ : label is "\u_mig_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/rdlvl_start_dly0_r_reg ";
  attribute srl_name of \rdlvl_start_dly0_r_reg[13]_srl14\ : label is "\u_mig_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/rdlvl_start_dly0_r_reg[13]_srl14 ";
  attribute SOFT_HLUTNM of rdlvl_stg1_start_int_i_2 : label is "soft_lutpair482";
  attribute SOFT_HLUTNM of \read_fifo.tail_r[0]_i_1\ : label is "soft_lutpair532";
  attribute SOFT_HLUTNM of \reg_ctrl_cnt_r[0]_i_1\ : label is "soft_lutpair528";
  attribute SOFT_HLUTNM of \reg_ctrl_cnt_r[1]_i_1\ : label is "soft_lutpair528";
  attribute SOFT_HLUTNM of \reg_ctrl_cnt_r[2]_i_1\ : label is "soft_lutpair459";
  attribute SOFT_HLUTNM of \reg_ctrl_cnt_r[3]_i_3\ : label is "soft_lutpair459";
  attribute SOFT_HLUTNM of \row_cnt_victim_rotate.complex_row_cnt[0]_i_1\ : label is "soft_lutpair426";
  attribute SOFT_HLUTNM of \row_cnt_victim_rotate.complex_row_cnt[3]_i_2\ : label is "soft_lutpair426";
  attribute SOFT_HLUTNM of \samples_cnt_r[11]_i_1\ : label is "soft_lutpair461";
  attribute SOFT_HLUTNM of \stg1_wr_rd_cnt[0]_i_1\ : label is "soft_lutpair470";
  attribute SOFT_HLUTNM of \stg1_wr_rd_cnt[2]_i_1\ : label is "soft_lutpair475";
  attribute SOFT_HLUTNM of \stg1_wr_rd_cnt[6]_i_1\ : label is "soft_lutpair470";
  attribute SOFT_HLUTNM of \stg1_wr_rd_cnt[6]_i_2\ : label is "soft_lutpair389";
  attribute SOFT_HLUTNM of \stg1_wr_rd_cnt[7]_i_1\ : label is "soft_lutpair409";
  attribute SOFT_HLUTNM of \stg1_wr_rd_cnt[8]_i_2\ : label is "soft_lutpair409";
  attribute SOFT_HLUTNM of \stg1_wr_rd_cnt[8]_i_3\ : label is "soft_lutpair389";
  attribute SOFT_HLUTNM of \victim_sel[0]_i_1\ : label is "soft_lutpair491";
  attribute SOFT_HLUTNM of \victim_sel[1]_i_1\ : label is "soft_lutpair492";
  attribute SOFT_HLUTNM of \victim_sel[2]_i_1\ : label is "soft_lutpair491";
  attribute SOFT_HLUTNM of \victim_sel_rotate.sel[56]_i_1\ : label is "soft_lutpair492";
  attribute SOFT_HLUTNM of \victim_sel_rotate.sel[57]_i_1\ : label is "soft_lutpair504";
  attribute SOFT_HLUTNM of \victim_sel_rotate.sel[58]_i_1\ : label is "soft_lutpair505";
  attribute SOFT_HLUTNM of \victim_sel_rotate.sel[60]_i_1\ : label is "soft_lutpair505";
  attribute SOFT_HLUTNM of \victim_sel_rotate.sel[61]_i_1\ : label is "soft_lutpair503";
  attribute SOFT_HLUTNM of \victim_sel_rotate.sel[62]_i_1\ : label is "soft_lutpair504";
  attribute SOFT_HLUTNM of \victim_sel_rotate.sel[63]_i_1\ : label is "soft_lutpair503";
  attribute SOFT_HLUTNM of \wr_done_victim_rotate.complex_row0_wr_done_i_1\ : label is "soft_lutpair454";
  attribute SOFT_HLUTNM of \wr_done_victim_rotate.complex_row0_wr_done_i_3\ : label is "soft_lutpair391";
  attribute SOFT_HLUTNM of \wr_done_victim_rotate.complex_row1_wr_done_i_1\ : label is "soft_lutpair454";
  attribute SOFT_HLUTNM of wr_ptr0_i_1 : label is "soft_lutpair493";
  attribute SOFT_HLUTNM of \wr_ptr[3]_i_3\ : label is "soft_lutpair493";
  attribute SOFT_HLUTNM of wr_victim_inc_i_1 : label is "soft_lutpair494";
  attribute SOFT_HLUTNM of wr_victim_inc_i_3 : label is "soft_lutpair453";
  attribute SOFT_HLUTNM of \wr_victim_sel[0]_i_1\ : label is "soft_lutpair418";
  attribute SOFT_HLUTNM of \wr_victim_sel[1]_i_1\ : label is "soft_lutpair418";
  attribute SOFT_HLUTNM of \wr_victim_sel_ocal[0]_i_1\ : label is "soft_lutpair441";
  attribute SOFT_HLUTNM of \wr_victim_sel_ocal[1]_i_1\ : label is "soft_lutpair441";
  attribute SOFT_HLUTNM of \wrcal_reads[0]_i_1\ : label is "soft_lutpair479";
  attribute SOFT_HLUTNM of \wrcal_reads[1]_i_1\ : label is "soft_lutpair479";
  attribute SOFT_HLUTNM of \wrcal_reads[2]_i_1\ : label is "soft_lutpair394";
  attribute SOFT_HLUTNM of \wrcal_reads[3]_i_1\ : label is "soft_lutpair394";
  attribute SOFT_HLUTNM of \wrcal_reads[6]_i_1\ : label is "soft_lutpair393";
  attribute SOFT_HLUTNM of \wrcal_reads[7]_i_10\ : label is "soft_lutpair449";
  attribute SOFT_HLUTNM of \wrcal_reads[7]_i_3\ : label is "soft_lutpair393";
  attribute SOFT_HLUTNM of \wrcal_reads[7]_i_4\ : label is "soft_lutpair529";
  attribute SOFT_HLUTNM of \wrcal_reads[7]_i_5\ : label is "soft_lutpair430";
  attribute SOFT_HLUTNM of \wrcal_reads[7]_i_7\ : label is "soft_lutpair466";
  attribute srl_bus_name of \wrcal_start_dly_r_reg[4]_srl5\ : label is "\u_mig_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/wrcal_start_dly_r_reg ";
  attribute srl_name of \wrcal_start_dly_r_reg[4]_srl5\ : label is "\u_mig_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/wrcal_start_dly_r_reg[4]_srl5 ";
  attribute SOFT_HLUTNM of \wrcal_wr_cnt[0]_i_1\ : label is "soft_lutpair524";
  attribute SOFT_HLUTNM of \wrcal_wr_cnt[1]_i_1\ : label is "soft_lutpair524";
  attribute SOFT_HLUTNM of \wrcal_wr_cnt[2]_i_1\ : label is "soft_lutpair514";
  attribute SOFT_HLUTNM of \wrcal_wr_cnt[3]_i_3\ : label is "soft_lutpair407";
  attribute SOFT_HLUTNM of \wrcal_wr_cnt[3]_i_4\ : label is "soft_lutpair514";
  attribute srl_name of wrlvl_rank_done_r6_reg_srl5 : label is "\u_mig_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/wrlvl_rank_done_r6_reg_srl5 ";
begin
  Q(0) <= \^q\(0);
  \calib_seq_reg[1]_0\(10 downto 0) <= \^calib_seq_reg[1]_0\(10 downto 0);
  complex_ocal_reset_rd_addr <= \^complex_ocal_reset_rd_addr\;
  first_rdlvl_pat_r <= \^first_rdlvl_pat_r\;
  first_wrcal_pat_r <= \^first_wrcal_pat_r\;
  init_complete_r1_timing_reg_0 <= \^init_complete_r1_timing_reg_0\;
  \init_state_r_reg[4]_0\ <= \^init_state_r_reg[4]_0\;
  \init_state_r_reg[4]_1\ <= \^init_state_r_reg[4]_1\;
  mpr_rdlvl_start_reg_0 <= \^mpr_rdlvl_start_reg_0\;
  \one_rank.stg1_wr_done_reg_0\ <= \^one_rank.stg1_wr_done_reg_0\;
  phy_read_calib <= \^phy_read_calib\;
  phy_write_calib <= \^phy_write_calib\;
  pi_calib_done <= \^pi_calib_done\;
  pi_dqs_found_done_r1 <= \^pi_dqs_found_done_r1\;
  pi_dqs_found_start_reg_0 <= \^pi_dqs_found_start_reg_0\;
  prbs_rdlvl_done_pulse_reg_0 <= \^prbs_rdlvl_done_pulse_reg_0\;
  prbs_rdlvl_start_reg_0 <= \^prbs_rdlvl_start_reg_0\;
  prech_req_posedge_r_reg_0 <= \^prech_req_posedge_r_reg_0\;
  rdlvl_stg1_start_int_reg_0 <= \^rdlvl_stg1_start_int_reg_0\;
  rdlvl_stg1_start_reg_0 <= \^rdlvl_stg1_start_reg_0\;
  stg1_wr_done <= \^stg1_wr_done\;
  wl_sm_start <= \^wl_sm_start\;
  wr_lvl_start_reg_0 <= \^wr_lvl_start_reg_0\;
  wrcal_start_reg_0 <= \^wrcal_start_reg_0\;
  wrlvl_done_r1 <= \^wrlvl_done_r1\;
  wrlvl_final_if_rst <= \^wrlvl_final_if_rst\;
\DDR3_1rank.phy_int_cs_n[1]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000AAAB0000"
    )
        port map (
      I0 => \DDR3_1rank.phy_int_cs_n[1]_i_2_n_0\,
      I1 => \^q\(0),
      I2 => \init_state_r_reg_n_0_[1]\,
      I3 => prbs_rdlvl_start_i_3_n_0,
      I4 => \DDR3_1rank.phy_int_cs_n[1]_i_3_n_0\,
      I5 => \cnt_dllk_zqinit_r[7]_i_1_n_0\,
      O => \DDR3_1rank.phy_int_cs_n[1]_i_1_n_0\
    );
\DDR3_1rank.phy_int_cs_n[1]_i_10\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFDFFF"
    )
        port map (
      I0 => \init_state_r_reg_n_0_[4]\,
      I1 => init_state_r(6),
      I2 => \init_state_r_reg_n_0_[5]\,
      I3 => \init_state_r_reg_n_0_[2]\,
      I4 => \init_state_r_reg_n_0_[3]\,
      O => \DDR3_1rank.phy_int_cs_n[1]_i_10_n_0\
    );
\DDR3_1rank.phy_int_cs_n[1]_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => phy_wrdata_en,
      I1 => \calib_cmd[2]_i_3_n_0\,
      O => \DDR3_1rank.phy_int_cs_n[1]_i_2_n_0\
    );
\DDR3_1rank.phy_int_cs_n[1]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000400000000"
    )
        port map (
      I0 => \DDR3_1rank.phy_int_cs_n[1]_i_4_n_0\,
      I1 => \num_refresh[3]_i_4_n_0\,
      I2 => \DDR3_1rank.phy_int_cs_n[1]_i_5_n_0\,
      I3 => complex_row1_rd_done_i_2_n_0,
      I4 => \DDR3_1rank.phy_int_cs_n[1]_i_6_n_0\,
      I5 => \DDR3_1rank.phy_int_cs_n[1]_i_7_n_0\,
      O => \DDR3_1rank.phy_int_cs_n[1]_i_3_n_0\
    );
\DDR3_1rank.phy_int_cs_n[1]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"BAAAFAAABFAAFFAA"
    )
        port map (
      I0 => \DDR3_1rank.phy_int_cs_n[1]_i_8_n_0\,
      I1 => complex_oclkdelay_calib_start_int_i_2_n_0,
      I2 => \^q\(0),
      I3 => \init_state_r_reg_n_0_[1]\,
      I4 => \DDR3_1rank.phy_int_cs_n[1]_i_9_n_0\,
      I5 => \DDR3_1rank.phy_int_cs_n[1]_i_10_n_0\,
      O => \DDR3_1rank.phy_int_cs_n[1]_i_4_n_0\
    );
\DDR3_1rank.phy_int_cs_n[1]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000300020000"
    )
        port map (
      I0 => \init_state_r_reg_n_0_[1]\,
      I1 => \^q\(0),
      I2 => \init_state_r[3]_i_6_n_0\,
      I3 => \init_state_r_reg_n_0_[4]\,
      I4 => \init_state_r_reg_n_0_[2]\,
      I5 => \init_state_r_reg_n_0_[3]\,
      O => \DDR3_1rank.phy_int_cs_n[1]_i_5_n_0\
    );
\DDR3_1rank.phy_int_cs_n[1]_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000040000000"
    )
        port map (
      I0 => init_state_r(6),
      I1 => \init_state_r_reg_n_0_[5]\,
      I2 => \init_state_r_reg_n_0_[2]\,
      I3 => \init_state_r_reg_n_0_[4]\,
      I4 => \init_state_r_reg_n_0_[3]\,
      I5 => prbs_rdlvl_start_i_2_n_0,
      O => \DDR3_1rank.phy_int_cs_n[1]_i_6_n_0\
    );
\DDR3_1rank.phy_int_cs_n[1]_i_7\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"5151515151511151"
    )
        port map (
      I0 => \cnt_init_mr_r[1]_i_2_n_0\,
      I1 => \init_state_r_reg_n_0_[1]\,
      I2 => mpr_rdlvl_start_i_2_n_0,
      I3 => \^q\(0),
      I4 => \wrcal_reads[7]_i_7_n_0\,
      I5 => \wrcal_reads[7]_i_4_n_0\,
      O => \DDR3_1rank.phy_int_cs_n[1]_i_7_n_0\
    );
\DDR3_1rank.phy_int_cs_n[1]_i_8\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"4004000000000000"
    )
        port map (
      I0 => \init_state_r[3]_i_6_n_0\,
      I1 => \init_state_r_reg_n_0_[3]\,
      I2 => \init_state_r_reg_n_0_[1]\,
      I3 => \init_state_r_reg_n_0_[2]\,
      I4 => \init_state_r_reg_n_0_[4]\,
      I5 => \^q\(0),
      O => \DDR3_1rank.phy_int_cs_n[1]_i_8_n_0\
    );
\DDR3_1rank.phy_int_cs_n[1]_i_9\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFEFFFFF"
    )
        port map (
      I0 => \init_state_r_reg_n_0_[5]\,
      I1 => init_state_r(6),
      I2 => \init_state_r_reg_n_0_[4]\,
      I3 => \init_state_r_reg_n_0_[3]\,
      I4 => \init_state_r_reg_n_0_[2]\,
      O => \DDR3_1rank.phy_int_cs_n[1]_i_9_n_0\
    );
\DDR3_1rank.phy_int_cs_n_reg[1]\: unisim.vcomponents.FDSE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => '1',
      D => \DDR3_1rank.phy_int_cs_n[1]_i_1_n_0\,
      Q => phy_cs_n(1),
      S => \victim_sel_reg[0]_0\(0)
    );
\FSM_sequential_wl_state_r[0]_i_13\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \^wl_sm_start\,
      I1 => wr_level_done_r5,
      O => wl_sm_start_reg_0
    );
app_rd_data_valid_INST_0: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \^init_complete_r1_timing_reg_0\,
      I1 => app_rd_data_valid_0(0),
      O => app_rd_data_valid
    );
app_rd_data_valid_INST_0_i_1: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => init_complete_r1_timing,
      I1 => if_empty,
      O => \^init_complete_r1_timing_reg_0\
    );
\back_to_back_reads_4_1.num_reads[0]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000023"
    )
        port map (
      I0 => num_reads(1),
      I1 => num_reads(0),
      I2 => pi_dqs_found_start_i_2_n_0,
      I3 => \^init_state_r_reg[4]_1\,
      I4 => write_calib_reg_0,
      O => \back_to_back_reads_4_1.num_reads[0]_i_1_n_0\
    );
\back_to_back_reads_4_1.num_reads[1]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000089"
    )
        port map (
      I0 => num_reads(1),
      I1 => num_reads(0),
      I2 => pi_dqs_found_start_i_2_n_0,
      I3 => \^init_state_r_reg[4]_1\,
      I4 => \rd_addr_reg[7]\,
      O => \back_to_back_reads_4_1.num_reads[1]_i_1_n_0\
    );
\back_to_back_reads_4_1.num_reads_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => '1',
      D => \back_to_back_reads_4_1.num_reads[0]_i_1_n_0\,
      Q => num_reads(0),
      R => '0'
    );
\back_to_back_reads_4_1.num_reads_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => '1',
      D => \back_to_back_reads_4_1.num_reads[1]_i_1_n_0\,
      Q => num_reads(1),
      R => '0'
    );
burst_addr_r_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"000000000000EEEF"
    )
        port map (
      I0 => burst_addr_r_i_2_n_0,
      I1 => burst_addr_r_i_3_n_0,
      I2 => p_17_in(3),
      I3 => \DDR3_1rank.phy_int_cs_n[1]_i_2_n_0\,
      I4 => ddr3_lm_done_r_reg_0,
      I5 => \rd_addr_reg[7]\,
      O => burst_addr_r_i_1_n_0
    );
burst_addr_r_i_2: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0100000004000000"
    )
        port map (
      I0 => \cnt_init_mr_r[0]_i_2_n_0\,
      I1 => \init_state_r_reg_n_0_[4]\,
      I2 => init_state_r(6),
      I3 => \init_state_r_reg_n_0_[5]\,
      I4 => \^q\(0),
      I5 => \init_state_r_reg_n_0_[1]\,
      O => burst_addr_r_i_2_n_0
    );
burst_addr_r_i_3: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFF10000313"
    )
        port map (
      I0 => \^q\(0),
      I1 => \wrcal_reads[7]_i_7_n_0\,
      I2 => \init_state_r_reg_n_0_[1]\,
      I3 => \init_state_r_reg_n_0_[2]\,
      I4 => \init_state_r_reg_n_0_[3]\,
      I5 => p_0_in0_in,
      O => burst_addr_r_i_3_n_0
    );
burst_addr_r_reg: unisim.vcomponents.FDRE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => '1',
      D => burst_addr_r_i_1_n_0,
      Q => p_17_in(3),
      R => '0'
    );
\calib_cke_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => '1',
      D => cnt_pwron_cke_done_r,
      Q => calib_cke(3),
      R => \victim_sel_reg[0]_0\(0)
    );
\calib_cmd[0]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"D"
    )
        port map (
      I0 => \calib_cmd[2]_i_2_n_0\,
      I1 => \calib_cmd[2]_i_3_n_0\,
      O => \calib_cmd[0]_i_1_n_0\
    );
\calib_cmd[1]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \calib_cmd[2]_i_3_n_0\,
      I1 => \calib_cmd[2]_i_2_n_0\,
      O => \calib_cmd[1]_i_1_n_0\
    );
\calib_cmd[2]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \calib_cmd[2]_i_2_n_0\,
      I1 => \calib_cmd[2]_i_3_n_0\,
      O => \calib_cmd[2]_i_1_n_0\
    );
\calib_cmd[2]_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => wr_level_dqs_asrt,
      I1 => phy_wrdata_en,
      O => \calib_cmd[2]_i_2_n_0\
    );
\calib_cmd[2]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFF45FFFF"
    )
        port map (
      I0 => rdlvl_pi_incdec,
      I1 => \calib_cmd[2]_i_4_n_0\,
      I2 => rdlvl_stg1_start_i_2_n_0,
      I3 => \calib_cmd[2]_i_5_n_0\,
      I4 => \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_8_n_0\,
      I5 => burst_addr_r_i_2_n_0,
      O => \calib_cmd[2]_i_3_n_0\
    );
\calib_cmd[2]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000001000000"
    )
        port map (
      I0 => \init_state_r_reg_n_0_[1]\,
      I1 => init_state_r(6),
      I2 => \init_state_r_reg_n_0_[4]\,
      I3 => \init_state_r_reg_n_0_[5]\,
      I4 => \^q\(0),
      I5 => \init_state_r[4]_i_4_n_0\,
      O => \calib_cmd[2]_i_4_n_0\
    );
\calib_cmd[2]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000020400"
    )
        port map (
      I0 => \init_state_r_reg_n_0_[2]\,
      I1 => \init_state_r_reg_n_0_[3]\,
      I2 => complex_act_start_i_2_n_0,
      I3 => \init_state_r_reg_n_0_[4]\,
      I4 => \init_state_r_reg_n_0_[1]\,
      I5 => \^q\(0),
      O => \calib_cmd[2]_i_5_n_0\
    );
\calib_cmd_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => '1',
      D => \calib_cmd[0]_i_1_n_0\,
      Q => calib_cmd(0),
      R => '0'
    );
\calib_cmd_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => '1',
      D => \calib_cmd[1]_i_1_n_0\,
      Q => calib_cmd(1),
      R => '0'
    );
\calib_cmd_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => '1',
      D => \calib_cmd[2]_i_1_n_0\,
      Q => calib_cmd(2),
      R => '0'
    );
calib_ctl_wren_i_1: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => cnt_pwron_cke_done_r,
      I1 => \calib_seq_reg[0]_0\(0),
      O => p_115_in
    );
calib_ctl_wren_reg: unisim.vcomponents.FDRE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => '1',
      D => p_115_in,
      Q => calib_cmd_wren,
      R => \en_cnt_div4.enable_wrlvl_cnt_reg[2]_0\
    );
\calib_data_offset_0[3]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"D0"
    )
        port map (
      I0 => \calib_cmd[2]_i_2_n_0\,
      I1 => \calib_cmd[2]_i_3_n_0\,
      I2 => \calib_data_offset_0[3]_i_2_n_0\,
      O => \calib_data_offset_0[3]_i_1_n_0\
    );
\calib_data_offset_0[3]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"A0A2A080FFFFFFFF"
    )
        port map (
      I0 => \^pi_calib_done\,
      I1 => \^pi_dqs_found_done_r1\,
      I2 => \calib_data_offset_0_reg[3]_0\(0),
      I3 => init_dqsfound_done_r2,
      I4 => \calib_data_offset_0_reg[3]_1\(0),
      I5 => \calib_cmd[2]_i_2_n_0\,
      O => \calib_data_offset_0[3]_i_2_n_0\
    );
\calib_data_offset_0[5]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"7F"
    )
        port map (
      I0 => \calib_cmd[2]_i_3_n_0\,
      I1 => \calib_cmd[2]_i_2_n_0\,
      I2 => \^pi_calib_done\,
      O => \calib_data_offset_0[5]_i_1_n_0\
    );
\calib_data_offset_0_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => '1',
      D => \calib_data_offset_0_reg[0]_0\,
      Q => calib_data_offset_0(0),
      R => \calib_data_offset_0[5]_i_1_n_0\
    );
\calib_data_offset_0_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => '1',
      D => \calib_data_offset_0_reg[1]_0\,
      Q => calib_data_offset_0(1),
      R => \calib_data_offset_0[5]_i_1_n_0\
    );
\calib_data_offset_0_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => '1',
      D => \calib_data_offset_0_reg[2]_0\,
      Q => calib_data_offset_0(2),
      R => \calib_data_offset_0[5]_i_1_n_0\
    );
\calib_data_offset_0_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => '1',
      D => \calib_data_offset_0[3]_i_1_n_0\,
      Q => calib_data_offset_0(3),
      R => '0'
    );
\calib_data_offset_0_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => '1',
      D => \calib_data_offset_0_reg[4]_0\,
      Q => calib_data_offset_0(4),
      R => \calib_data_offset_0[5]_i_1_n_0\
    );
\calib_data_offset_0_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => '1',
      D => \calib_data_offset_0_reg[5]_0\,
      Q => calib_data_offset_0(5),
      R => \calib_data_offset_0[5]_i_1_n_0\
    );
\calib_data_offset_1[3]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"D0"
    )
        port map (
      I0 => \calib_cmd[2]_i_2_n_0\,
      I1 => \calib_cmd[2]_i_3_n_0\,
      I2 => \calib_data_offset_1[3]_i_2_n_0\,
      O => \calib_data_offset_1[3]_i_1_n_0\
    );
\calib_data_offset_1[3]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"A0A2A080FFFFFFFF"
    )
        port map (
      I0 => \^pi_calib_done\,
      I1 => \^pi_dqs_found_done_r1\,
      I2 => \calib_data_offset_1_reg[3]_0\(0),
      I3 => init_dqsfound_done_r2,
      I4 => \calib_data_offset_1_reg[3]_1\(0),
      I5 => \calib_cmd[2]_i_2_n_0\,
      O => \calib_data_offset_1[3]_i_2_n_0\
    );
\calib_data_offset_1_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => '1',
      D => \calib_data_offset_1_reg[0]_0\,
      Q => calib_data_offset_1(0),
      R => \calib_data_offset_0[5]_i_1_n_0\
    );
\calib_data_offset_1_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => '1',
      D => \calib_data_offset_1_reg[1]_0\,
      Q => calib_data_offset_1(1),
      R => \calib_data_offset_0[5]_i_1_n_0\
    );
\calib_data_offset_1_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => '1',
      D => \calib_data_offset_1_reg[2]_0\,
      Q => calib_data_offset_1(2),
      R => \calib_data_offset_0[5]_i_1_n_0\
    );
\calib_data_offset_1_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => '1',
      D => \calib_data_offset_1[3]_i_1_n_0\,
      Q => calib_data_offset_1(3),
      R => '0'
    );
\calib_data_offset_1_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => '1',
      D => \calib_data_offset_1_reg[4]_0\,
      Q => calib_data_offset_1(4),
      R => \calib_data_offset_0[5]_i_1_n_0\
    );
\calib_data_offset_1_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => '1',
      D => \calib_data_offset_1_reg[5]_0\,
      Q => calib_data_offset_1(5),
      R => \calib_data_offset_0[5]_i_1_n_0\
    );
\calib_data_offset_2[3]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"D0"
    )
        port map (
      I0 => \calib_cmd[2]_i_2_n_0\,
      I1 => \calib_cmd[2]_i_3_n_0\,
      I2 => \calib_data_offset_2[3]_i_2_n_0\,
      O => \calib_data_offset_2[3]_i_1_n_0\
    );
\calib_data_offset_2[3]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"A0A2A080FFFFFFFF"
    )
        port map (
      I0 => \^pi_calib_done\,
      I1 => \^pi_dqs_found_done_r1\,
      I2 => \calib_data_offset_2_reg[3]_0\(0),
      I3 => init_dqsfound_done_r2,
      I4 => \calib_data_offset_2_reg[3]_1\(0),
      I5 => \calib_cmd[2]_i_2_n_0\,
      O => \calib_data_offset_2[3]_i_2_n_0\
    );
\calib_data_offset_2_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => '1',
      D => \calib_data_offset_2_reg[0]_0\,
      Q => calib_data_offset_2(0),
      R => \calib_data_offset_0[5]_i_1_n_0\
    );
\calib_data_offset_2_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => '1',
      D => \calib_data_offset_2_reg[1]_0\,
      Q => calib_data_offset_2(1),
      R => \calib_data_offset_0[5]_i_1_n_0\
    );
\calib_data_offset_2_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => '1',
      D => \calib_data_offset_2_reg[2]_0\,
      Q => calib_data_offset_2(2),
      R => \calib_data_offset_0[5]_i_1_n_0\
    );
\calib_data_offset_2_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => '1',
      D => \calib_data_offset_2[3]_i_1_n_0\,
      Q => calib_data_offset_2(3),
      R => '0'
    );
\calib_data_offset_2_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => '1',
      D => \calib_data_offset_2_reg[4]_0\,
      Q => calib_data_offset_2(4),
      R => \calib_data_offset_0[5]_i_1_n_0\
    );
\calib_data_offset_2_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => '1',
      D => \calib_data_offset_2_reg[5]_0\,
      Q => calib_data_offset_2(5),
      R => \calib_data_offset_0[5]_i_1_n_0\
    );
\calib_odt[0]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"00E0"
    )
        port map (
      I0 => \calib_odt[0]_i_2_n_0\,
      I1 => phy_wrdata_en,
      I2 => \gen_rnk[0].mr1_r_reg_n_0_[0][1]\,
      I3 => write_calib_reg_0,
      O => \calib_odt[0]_i_1_n_0\
    );
\calib_odt[0]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFFFFE"
    )
        port map (
      I0 => \^stg1_wr_done\,
      I1 => complex_ocal_odt_ext,
      I2 => complex_odt_ext,
      I3 => \complex_address[9]_i_3_n_0\,
      I4 => \calib_odt[0]_i_3_n_0\,
      O => \calib_odt[0]_i_2_n_0\
    );
\calib_odt[0]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"C0005500C00055FF"
    )
        port map (
      I0 => calib_wrdata_en_i_2_n_0,
      I1 => \odd_cwl.phy_cas_n[1]_i_4_n_0\,
      I2 => wrlvl_odt,
      I3 => \init_state_r_reg_n_0_[1]\,
      I4 => \^q\(0),
      I5 => complex_ocal_odt_ext_i_3_n_0,
      O => \calib_odt[0]_i_3_n_0\
    );
\calib_odt_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => '1',
      D => \calib_odt[0]_i_1_n_0\,
      Q => calib_odt(0),
      R => '0'
    );
\calib_seq[0]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"78"
    )
        port map (
      I0 => cnt_pwron_cke_done_r,
      I1 => \calib_seq_reg[0]_0\(0),
      I2 => \^calib_seq_reg[1]_0\(9),
      O => \calib_seq[0]_i_1_n_0\
    );
\calib_seq[1]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7F80"
    )
        port map (
      I0 => \^calib_seq_reg[1]_0\(9),
      I1 => cnt_pwron_cke_done_r,
      I2 => \calib_seq_reg[0]_0\(0),
      I3 => \^calib_seq_reg[1]_0\(10),
      O => \calib_seq[1]_i_1_n_0\
    );
\calib_seq_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => '1',
      D => \calib_seq[0]_i_1_n_0\,
      Q => \^calib_seq_reg[1]_0\(9),
      R => \victim_sel_reg[0]_0\(0)
    );
\calib_seq_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => '1',
      D => \calib_seq[1]_i_1_n_0\,
      Q => \^calib_seq_reg[1]_0\(10),
      R => \victim_sel_reg[0]_0\(0)
    );
calib_wrdata_en_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFCCCFCCDD"
    )
        port map (
      I0 => prbs_rdlvl_start_i_3_n_0,
      I1 => p_0_in0_in,
      I2 => calib_wrdata_en_i_2_n_0,
      I3 => \init_state_r_reg_n_0_[1]\,
      I4 => \^q\(0),
      I5 => \stg1_wr_rd_cnt[8]_i_5_n_0\,
      O => phy_wrdata_en
    );
calib_wrdata_en_i_2: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFFEFF"
    )
        port map (
      I0 => \init_state_r_reg_n_0_[2]\,
      I1 => \init_state_r_reg_n_0_[3]\,
      I2 => init_state_r(6),
      I3 => \init_state_r_reg_n_0_[5]\,
      I4 => \init_state_r_reg_n_0_[4]\,
      O => calib_wrdata_en_i_2_n_0
    );
calib_wrdata_en_reg: unisim.vcomponents.FDRE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => '1',
      D => phy_wrdata_en,
      Q => calib_wrdata_en,
      R => '0'
    );
cnt_cmd_done_m7_r_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000800000"
    )
        port map (
      I0 => \cnt_cmd_r_reg_n_0_[5]\,
      I1 => \cnt_cmd_r_reg_n_0_[4]\,
      I2 => \cnt_cmd_r_reg_n_0_[3]\,
      I3 => \cnt_cmd_r_reg_n_0_[2]\,
      I4 => \cnt_cmd_r_reg_n_0_[6]\,
      I5 => cnt_cmd_done_m7_r_i_2_n_0,
      O => cnt_cmd_done_m7_r_i_1_n_0
    );
cnt_cmd_done_m7_r_i_2: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => \cnt_cmd_r_reg_n_0_[1]\,
      I1 => \cnt_cmd_r_reg_n_0_[0]\,
      O => cnt_cmd_done_m7_r_i_2_n_0
    );
cnt_cmd_done_m7_r_reg: unisim.vcomponents.FDRE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => '1',
      D => cnt_cmd_done_m7_r_i_1_n_0,
      Q => cnt_cmd_done_m7_r,
      R => '0'
    );
cnt_cmd_done_r_i_1: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \cnt_cmd_r[6]_i_4_n_0\,
      I1 => \cnt_cmd_r_reg_n_0_[6]\,
      O => cnt_cmd_done_r_i_1_n_0
    );
cnt_cmd_done_r_reg: unisim.vcomponents.FDRE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => '1',
      D => cnt_cmd_done_r_i_1_n_0,
      Q => cnt_cmd_done_r,
      R => '0'
    );
\cnt_cmd_r[0]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \cnt_cmd_r_reg_n_0_[0]\,
      O => \cnt_cmd_r[0]_i_1_n_0\
    );
\cnt_cmd_r[1]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \cnt_cmd_r_reg_n_0_[0]\,
      I1 => \cnt_cmd_r_reg_n_0_[1]\,
      O => \cnt_cmd_r[1]_i_1_n_0\
    );
\cnt_cmd_r[2]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"6A"
    )
        port map (
      I0 => \cnt_cmd_r_reg_n_0_[2]\,
      I1 => \cnt_cmd_r_reg_n_0_[0]\,
      I2 => \cnt_cmd_r_reg_n_0_[1]\,
      O => \cnt_cmd_r[2]_i_1_n_0\
    );
\cnt_cmd_r[3]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6AAA"
    )
        port map (
      I0 => \cnt_cmd_r_reg_n_0_[3]\,
      I1 => \cnt_cmd_r_reg_n_0_[2]\,
      I2 => \cnt_cmd_r_reg_n_0_[1]\,
      I3 => \cnt_cmd_r_reg_n_0_[0]\,
      O => \cnt_cmd_r[3]_i_1_n_0\
    );
\cnt_cmd_r[4]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"6AAAAAAA"
    )
        port map (
      I0 => \cnt_cmd_r_reg_n_0_[4]\,
      I1 => \cnt_cmd_r_reg_n_0_[3]\,
      I2 => \cnt_cmd_r_reg_n_0_[0]\,
      I3 => \cnt_cmd_r_reg_n_0_[1]\,
      I4 => \cnt_cmd_r_reg_n_0_[2]\,
      O => \cnt_cmd_r[4]_i_1_n_0\
    );
\cnt_cmd_r[5]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"6AAAAAAAAAAAAAAA"
    )
        port map (
      I0 => \cnt_cmd_r_reg_n_0_[5]\,
      I1 => \cnt_cmd_r_reg_n_0_[2]\,
      I2 => \cnt_cmd_r_reg_n_0_[1]\,
      I3 => \cnt_cmd_r_reg_n_0_[0]\,
      I4 => \cnt_cmd_r_reg_n_0_[3]\,
      I5 => \cnt_cmd_r_reg_n_0_[4]\,
      O => \cnt_cmd_r[5]_i_1_n_0\
    );
\cnt_cmd_r[6]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => init_state_r(6),
      I1 => \cnt_cmd_r[6]_i_3_n_0\,
      O => \cnt_cmd_r[6]_i_1_n_0\
    );
\cnt_cmd_r[6]_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \cnt_cmd_r_reg_n_0_[6]\,
      I1 => \cnt_cmd_r[6]_i_4_n_0\,
      O => \cnt_cmd_r[6]_i_2_n_0\
    );
\cnt_cmd_r[6]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFD7B8C3F9C7EDC7"
    )
        port map (
      I0 => \init_state_r_reg_n_0_[3]\,
      I1 => \^q\(0),
      I2 => \init_state_r_reg_n_0_[5]\,
      I3 => \init_state_r_reg_n_0_[4]\,
      I4 => \init_state_r_reg_n_0_[2]\,
      I5 => \init_state_r_reg_n_0_[1]\,
      O => \cnt_cmd_r[6]_i_3_n_0\
    );
\cnt_cmd_r[6]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8000000000000000"
    )
        port map (
      I0 => \cnt_cmd_r_reg_n_0_[3]\,
      I1 => \cnt_cmd_r_reg_n_0_[0]\,
      I2 => \cnt_cmd_r_reg_n_0_[1]\,
      I3 => \cnt_cmd_r_reg_n_0_[2]\,
      I4 => \cnt_cmd_r_reg_n_0_[4]\,
      I5 => \cnt_cmd_r_reg_n_0_[5]\,
      O => \cnt_cmd_r[6]_i_4_n_0\
    );
\cnt_cmd_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => '1',
      D => \cnt_cmd_r[0]_i_1_n_0\,
      Q => \cnt_cmd_r_reg_n_0_[0]\,
      R => \cnt_cmd_r[6]_i_1_n_0\
    );
\cnt_cmd_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => '1',
      D => \cnt_cmd_r[1]_i_1_n_0\,
      Q => \cnt_cmd_r_reg_n_0_[1]\,
      R => \cnt_cmd_r[6]_i_1_n_0\
    );
\cnt_cmd_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => '1',
      D => \cnt_cmd_r[2]_i_1_n_0\,
      Q => \cnt_cmd_r_reg_n_0_[2]\,
      R => \cnt_cmd_r[6]_i_1_n_0\
    );
\cnt_cmd_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => '1',
      D => \cnt_cmd_r[3]_i_1_n_0\,
      Q => \cnt_cmd_r_reg_n_0_[3]\,
      R => \cnt_cmd_r[6]_i_1_n_0\
    );
\cnt_cmd_r_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => '1',
      D => \cnt_cmd_r[4]_i_1_n_0\,
      Q => \cnt_cmd_r_reg_n_0_[4]\,
      R => \cnt_cmd_r[6]_i_1_n_0\
    );
\cnt_cmd_r_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => '1',
      D => \cnt_cmd_r[5]_i_1_n_0\,
      Q => \cnt_cmd_r_reg_n_0_[5]\,
      R => \cnt_cmd_r[6]_i_1_n_0\
    );
\cnt_cmd_r_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => '1',
      D => \cnt_cmd_r[6]_i_2_n_0\,
      Q => \cnt_cmd_r_reg_n_0_[6]\,
      R => \cnt_cmd_r[6]_i_1_n_0\
    );
cnt_dllk_zqinit_done_r_i_1: unisim.vcomponents.LUT4
    generic map(
      INIT => X"EAAA"
    )
        port map (
      I0 => cnt_dllk_zqinit_done_r,
      I1 => cnt_dllk_zqinit_r_reg(6),
      I2 => mem_init_done_r_i_2_n_0,
      I3 => cnt_dllk_zqinit_r_reg(7),
      O => cnt_dllk_zqinit_done_r_i_1_n_0
    );
cnt_dllk_zqinit_done_r_reg: unisim.vcomponents.FDRE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => '1',
      D => cnt_dllk_zqinit_done_r_i_1_n_0,
      Q => cnt_dllk_zqinit_done_r,
      R => \cnt_dllk_zqinit_r[7]_i_1_n_0\
    );
\cnt_dllk_zqinit_r[0]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => cnt_dllk_zqinit_r_reg(0),
      O => \p_0_in__4\(0)
    );
\cnt_dllk_zqinit_r[1]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => cnt_dllk_zqinit_r_reg(1),
      I1 => cnt_dllk_zqinit_r_reg(0),
      O => \p_0_in__4\(1)
    );
\cnt_dllk_zqinit_r[2]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"6A"
    )
        port map (
      I0 => cnt_dllk_zqinit_r_reg(2),
      I1 => cnt_dllk_zqinit_r_reg(0),
      I2 => cnt_dllk_zqinit_r_reg(1),
      O => \p_0_in__4\(2)
    );
\cnt_dllk_zqinit_r[3]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6AAA"
    )
        port map (
      I0 => cnt_dllk_zqinit_r_reg(3),
      I1 => cnt_dllk_zqinit_r_reg(1),
      I2 => cnt_dllk_zqinit_r_reg(0),
      I3 => cnt_dllk_zqinit_r_reg(2),
      O => \p_0_in__4\(3)
    );
\cnt_dllk_zqinit_r[4]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"6AAAAAAA"
    )
        port map (
      I0 => cnt_dllk_zqinit_r_reg(4),
      I1 => cnt_dllk_zqinit_r_reg(2),
      I2 => cnt_dllk_zqinit_r_reg(0),
      I3 => cnt_dllk_zqinit_r_reg(1),
      I4 => cnt_dllk_zqinit_r_reg(3),
      O => \p_0_in__4\(4)
    );
\cnt_dllk_zqinit_r[5]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"6AAAAAAAAAAAAAAA"
    )
        port map (
      I0 => cnt_dllk_zqinit_r_reg(5),
      I1 => cnt_dllk_zqinit_r_reg(3),
      I2 => cnt_dllk_zqinit_r_reg(1),
      I3 => cnt_dllk_zqinit_r_reg(0),
      I4 => cnt_dllk_zqinit_r_reg(2),
      I5 => cnt_dllk_zqinit_r_reg(4),
      O => \p_0_in__4\(5)
    );
\cnt_dllk_zqinit_r[6]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => cnt_dllk_zqinit_r_reg(6),
      I1 => mem_init_done_r_i_2_n_0,
      O => \p_0_in__4\(6)
    );
\cnt_dllk_zqinit_r[7]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000000001"
    )
        port map (
      I0 => \wrcal_reads[7]_i_4_n_0\,
      I1 => \init_state_r_reg_n_0_[4]\,
      I2 => \init_state_r_reg_n_0_[5]\,
      I3 => init_state_r(6),
      I4 => \^q\(0),
      I5 => \init_state_r_reg_n_0_[1]\,
      O => \cnt_dllk_zqinit_r[7]_i_1_n_0\
    );
\cnt_dllk_zqinit_r[7]_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"6A"
    )
        port map (
      I0 => cnt_dllk_zqinit_r_reg(7),
      I1 => mem_init_done_r_i_2_n_0,
      I2 => cnt_dllk_zqinit_r_reg(6),
      O => \p_0_in__4\(7)
    );
\cnt_dllk_zqinit_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => '1',
      D => \p_0_in__4\(0),
      Q => cnt_dllk_zqinit_r_reg(0),
      R => \cnt_dllk_zqinit_r[7]_i_1_n_0\
    );
\cnt_dllk_zqinit_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => '1',
      D => \p_0_in__4\(1),
      Q => cnt_dllk_zqinit_r_reg(1),
      R => \cnt_dllk_zqinit_r[7]_i_1_n_0\
    );
\cnt_dllk_zqinit_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => '1',
      D => \p_0_in__4\(2),
      Q => cnt_dllk_zqinit_r_reg(2),
      R => \cnt_dllk_zqinit_r[7]_i_1_n_0\
    );
\cnt_dllk_zqinit_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => '1',
      D => \p_0_in__4\(3),
      Q => cnt_dllk_zqinit_r_reg(3),
      R => \cnt_dllk_zqinit_r[7]_i_1_n_0\
    );
\cnt_dllk_zqinit_r_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => '1',
      D => \p_0_in__4\(4),
      Q => cnt_dllk_zqinit_r_reg(4),
      R => \cnt_dllk_zqinit_r[7]_i_1_n_0\
    );
\cnt_dllk_zqinit_r_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => '1',
      D => \p_0_in__4\(5),
      Q => cnt_dllk_zqinit_r_reg(5),
      R => \cnt_dllk_zqinit_r[7]_i_1_n_0\
    );
\cnt_dllk_zqinit_r_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => '1',
      D => \p_0_in__4\(6),
      Q => cnt_dllk_zqinit_r_reg(6),
      R => \cnt_dllk_zqinit_r[7]_i_1_n_0\
    );
\cnt_dllk_zqinit_r_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => '1',
      D => \p_0_in__4\(7),
      Q => cnt_dllk_zqinit_r_reg(7),
      R => \cnt_dllk_zqinit_r[7]_i_1_n_0\
    );
cnt_init_af_done_r_i_1: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000E222"
    )
        port map (
      I0 => cnt_init_af_done_r,
      I1 => cnt_init_mr_r1,
      I2 => cnt_init_af_r(1),
      I3 => cnt_init_af_r(0),
      I4 => \reg_ctrl_cnt_r[3]_i_1_n_0\,
      O => cnt_init_af_done_r_i_1_n_0
    );
cnt_init_af_done_r_reg: unisim.vcomponents.FDRE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => '1',
      D => cnt_init_af_done_r_i_1_n_0,
      Q => cnt_init_af_done_r,
      R => '0'
    );
\cnt_init_af_r[0]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"06"
    )
        port map (
      I0 => cnt_init_af_r(0),
      I1 => cnt_init_mr_r1,
      I2 => \reg_ctrl_cnt_r[3]_i_1_n_0\,
      O => \cnt_init_af_r[0]_i_1_n_0\
    );
\cnt_init_af_r[1]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"006A"
    )
        port map (
      I0 => cnt_init_af_r(1),
      I1 => cnt_init_mr_r1,
      I2 => cnt_init_af_r(0),
      I3 => \reg_ctrl_cnt_r[3]_i_1_n_0\,
      O => \cnt_init_af_r[1]_i_1_n_0\
    );
\cnt_init_af_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => '1',
      D => \cnt_init_af_r[0]_i_1_n_0\,
      Q => cnt_init_af_r(0),
      R => '0'
    );
\cnt_init_af_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => '1',
      D => \cnt_init_af_r[1]_i_1_n_0\,
      Q => cnt_init_af_r(1),
      R => '0'
    );
cnt_init_mr_done_r_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"000000000000E222"
    )
        port map (
      I0 => cnt_init_mr_done_r,
      I1 => \cnt_init_mr_r[1]_i_2_n_0\,
      I2 => cnt_init_mr_r(1),
      I3 => cnt_init_mr_r(0),
      I4 => \reg_ctrl_cnt_r[3]_i_1_n_0\,
      I5 => cnt_init_mr_r1,
      O => cnt_init_mr_done_r_i_1_n_0
    );
cnt_init_mr_done_r_reg: unisim.vcomponents.FDRE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => '1',
      D => cnt_init_mr_done_r_i_1_n_0,
      Q => cnt_init_mr_done_r,
      R => '0'
    );
\cnt_init_mr_r[0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000AA9AAA8A"
    )
        port map (
      I0 => cnt_init_mr_r(0),
      I1 => \cnt_init_mr_r[0]_i_2_n_0\,
      I2 => \cnt_init_mr_r[0]_i_3_n_0\,
      I3 => \^q\(0),
      I4 => \init_state_r_reg_n_0_[1]\,
      I5 => cnt_init_mr_r1,
      O => \cnt_init_mr_r[0]_i_1_n_0\
    );
\cnt_init_mr_r[0]_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => \init_state_r_reg_n_0_[3]\,
      I1 => \init_state_r_reg_n_0_[2]\,
      O => \cnt_init_mr_r[0]_i_2_n_0\
    );
\cnt_init_mr_r[0]_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"01"
    )
        port map (
      I0 => \init_state_r_reg_n_0_[4]\,
      I1 => \init_state_r_reg_n_0_[5]\,
      I2 => init_state_r(6),
      O => \cnt_init_mr_r[0]_i_3_n_0\
    );
\cnt_init_mr_r[1]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000006A"
    )
        port map (
      I0 => cnt_init_mr_r(1),
      I1 => \cnt_init_mr_r[1]_i_2_n_0\,
      I2 => cnt_init_mr_r(0),
      I3 => \reg_ctrl_cnt_r[3]_i_1_n_0\,
      I4 => cnt_init_mr_r1,
      O => \cnt_init_mr_r[1]_i_1_n_0\
    );
\cnt_init_mr_r[1]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000100000000"
    )
        port map (
      I0 => \init_state_r_reg_n_0_[3]\,
      I1 => \init_state_r_reg_n_0_[2]\,
      I2 => \init_state_r_reg_n_0_[4]\,
      I3 => \init_state_r_reg_n_0_[5]\,
      I4 => init_state_r(6),
      I5 => detect_pi_found_dqs_i_2_n_0,
      O => \cnt_init_mr_r[1]_i_2_n_0\
    );
\cnt_init_mr_r[1]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000001000000"
    )
        port map (
      I0 => \init_state_r_reg_n_0_[5]\,
      I1 => init_state_r(6),
      I2 => \init_state_r[4]_i_4_n_0\,
      I3 => \gen_no_mirror.div_clk_loop[0].phy_address[12]_i_2_n_0\,
      I4 => \init_state_r_reg_n_0_[4]\,
      I5 => mem_init_done_r,
      O => cnt_init_mr_r1
    );
\cnt_init_mr_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => '1',
      D => \cnt_init_mr_r[0]_i_1_n_0\,
      Q => cnt_init_mr_r(0),
      R => '0'
    );
\cnt_init_mr_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => '1',
      D => \cnt_init_mr_r[1]_i_1_n_0\,
      Q => cnt_init_mr_r(1),
      R => '0'
    );
\cnt_pwron_ce_r[0]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => cnt_pwron_ce_r_reg(0),
      O => \p_0_in__0\(0)
    );
\cnt_pwron_ce_r[1]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => cnt_pwron_ce_r_reg(1),
      I1 => cnt_pwron_ce_r_reg(0),
      O => \p_0_in__0\(1)
    );
\cnt_pwron_ce_r[2]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"6A"
    )
        port map (
      I0 => cnt_pwron_ce_r_reg(2),
      I1 => cnt_pwron_ce_r_reg(0),
      I2 => cnt_pwron_ce_r_reg(1),
      O => \p_0_in__0\(2)
    );
\cnt_pwron_ce_r[3]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6AAA"
    )
        port map (
      I0 => cnt_pwron_ce_r_reg(3),
      I1 => cnt_pwron_ce_r_reg(1),
      I2 => cnt_pwron_ce_r_reg(0),
      I3 => cnt_pwron_ce_r_reg(2),
      O => \p_0_in__0\(3)
    );
\cnt_pwron_ce_r[4]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"6AAAAAAA"
    )
        port map (
      I0 => cnt_pwron_ce_r_reg(4),
      I1 => cnt_pwron_ce_r_reg(2),
      I2 => cnt_pwron_ce_r_reg(0),
      I3 => cnt_pwron_ce_r_reg(1),
      I4 => cnt_pwron_ce_r_reg(3),
      O => \p_0_in__0\(4)
    );
\cnt_pwron_ce_r[5]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"6AAAAAAAAAAAAAAA"
    )
        port map (
      I0 => cnt_pwron_ce_r_reg(5),
      I1 => cnt_pwron_ce_r_reg(3),
      I2 => cnt_pwron_ce_r_reg(1),
      I3 => cnt_pwron_ce_r_reg(0),
      I4 => cnt_pwron_ce_r_reg(2),
      I5 => cnt_pwron_ce_r_reg(4),
      O => \p_0_in__0\(5)
    );
\cnt_pwron_ce_r[6]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => cnt_pwron_ce_r_reg(6),
      I1 => pwron_ce_r_i_2_n_0,
      O => \p_0_in__0\(6)
    );
\cnt_pwron_ce_r[7]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"6A"
    )
        port map (
      I0 => cnt_pwron_ce_r_reg(7),
      I1 => pwron_ce_r_i_2_n_0,
      I2 => cnt_pwron_ce_r_reg(6),
      O => \p_0_in__0\(7)
    );
\cnt_pwron_ce_r[8]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6AAA"
    )
        port map (
      I0 => cnt_pwron_ce_r_reg(8),
      I1 => cnt_pwron_ce_r_reg(6),
      I2 => pwron_ce_r_i_2_n_0,
      I3 => cnt_pwron_ce_r_reg(7),
      O => \p_0_in__0\(8)
    );
\cnt_pwron_ce_r[9]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"6AAAAAAA"
    )
        port map (
      I0 => cnt_pwron_ce_r_reg(9),
      I1 => cnt_pwron_ce_r_reg(7),
      I2 => pwron_ce_r_i_2_n_0,
      I3 => cnt_pwron_ce_r_reg(6),
      I4 => cnt_pwron_ce_r_reg(8),
      O => \p_0_in__0\(9)
    );
\cnt_pwron_ce_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => '1',
      D => \p_0_in__0\(0),
      Q => cnt_pwron_ce_r_reg(0),
      R => \cnt_pwron_ce_r_reg[0]_0\
    );
\cnt_pwron_ce_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => '1',
      D => \p_0_in__0\(1),
      Q => cnt_pwron_ce_r_reg(1),
      R => \cnt_pwron_ce_r_reg[0]_0\
    );
\cnt_pwron_ce_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => '1',
      D => \p_0_in__0\(2),
      Q => cnt_pwron_ce_r_reg(2),
      R => \cnt_pwron_ce_r_reg[0]_0\
    );
\cnt_pwron_ce_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => '1',
      D => \p_0_in__0\(3),
      Q => cnt_pwron_ce_r_reg(3),
      R => \cnt_pwron_ce_r_reg[0]_0\
    );
\cnt_pwron_ce_r_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => '1',
      D => \p_0_in__0\(4),
      Q => cnt_pwron_ce_r_reg(4),
      R => \cnt_pwron_ce_r_reg[0]_0\
    );
\cnt_pwron_ce_r_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => '1',
      D => \p_0_in__0\(5),
      Q => cnt_pwron_ce_r_reg(5),
      R => \cnt_pwron_ce_r_reg[0]_0\
    );
\cnt_pwron_ce_r_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => '1',
      D => \p_0_in__0\(6),
      Q => cnt_pwron_ce_r_reg(6),
      R => \cnt_pwron_ce_r_reg[0]_0\
    );
\cnt_pwron_ce_r_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => '1',
      D => \p_0_in__0\(7),
      Q => cnt_pwron_ce_r_reg(7),
      R => \cnt_pwron_ce_r_reg[0]_0\
    );
\cnt_pwron_ce_r_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => '1',
      D => \p_0_in__0\(8),
      Q => cnt_pwron_ce_r_reg(8),
      R => \cnt_pwron_ce_r_reg[0]_0\
    );
\cnt_pwron_ce_r_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => '1',
      D => \p_0_in__0\(9),
      Q => cnt_pwron_ce_r_reg(9),
      R => \cnt_pwron_ce_r_reg[0]_0\
    );
cnt_pwron_cke_done_r_i_1: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000BA00"
    )
        port map (
      I0 => cnt_pwron_cke_done_r,
      I1 => cnt_pwron_cke_done_r_i_2_n_0,
      I2 => cnt_pwron_cke_done_r_i_3_n_0,
      I3 => \calib_seq_reg[0]_0\(0),
      I4 => \rd_addr_reg[7]\,
      O => cnt_pwron_cke_done_r_i_1_n_0
    );
cnt_pwron_cke_done_r_i_2: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFEFFFFFFFFFFF"
    )
        port map (
      I0 => cnt_pwron_r_reg(8),
      I1 => cnt_pwron_r_reg(7),
      I2 => cnt_pwron_r_reg(2),
      I3 => cnt_pwron_r_reg(6),
      I4 => cnt_pwron_r_reg(4),
      I5 => cnt_pwron_r_reg(1),
      O => cnt_pwron_cke_done_r_i_2_n_0
    );
cnt_pwron_cke_done_r_i_3: unisim.vcomponents.LUT3
    generic map(
      INIT => X"01"
    )
        port map (
      I0 => cnt_pwron_r_reg(5),
      I1 => cnt_pwron_r_reg(0),
      I2 => cnt_pwron_r_reg(3),
      O => cnt_pwron_cke_done_r_i_3_n_0
    );
cnt_pwron_cke_done_r_reg: unisim.vcomponents.FDRE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => '1',
      D => cnt_pwron_cke_done_r_i_1_n_0,
      Q => cnt_pwron_cke_done_r,
      R => '0'
    );
\cnt_pwron_r[0]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => cnt_pwron_r_reg(0),
      O => \p_0_in__1\(0)
    );
\cnt_pwron_r[1]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => cnt_pwron_r_reg(1),
      I1 => cnt_pwron_r_reg(0),
      O => \p_0_in__1\(1)
    );
\cnt_pwron_r[2]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"6A"
    )
        port map (
      I0 => cnt_pwron_r_reg(2),
      I1 => cnt_pwron_r_reg(0),
      I2 => cnt_pwron_r_reg(1),
      O => \p_0_in__1\(2)
    );
\cnt_pwron_r[3]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6AAA"
    )
        port map (
      I0 => cnt_pwron_r_reg(3),
      I1 => cnt_pwron_r_reg(1),
      I2 => cnt_pwron_r_reg(0),
      I3 => cnt_pwron_r_reg(2),
      O => \p_0_in__1\(3)
    );
\cnt_pwron_r[4]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"6AAAAAAA"
    )
        port map (
      I0 => cnt_pwron_r_reg(4),
      I1 => cnt_pwron_r_reg(2),
      I2 => cnt_pwron_r_reg(0),
      I3 => cnt_pwron_r_reg(1),
      I4 => cnt_pwron_r_reg(3),
      O => \p_0_in__1\(4)
    );
\cnt_pwron_r[5]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"6AAAAAAAAAAAAAAA"
    )
        port map (
      I0 => cnt_pwron_r_reg(5),
      I1 => cnt_pwron_r_reg(3),
      I2 => cnt_pwron_r_reg(1),
      I3 => cnt_pwron_r_reg(0),
      I4 => cnt_pwron_r_reg(2),
      I5 => cnt_pwron_r_reg(4),
      O => \p_0_in__1\(5)
    );
\cnt_pwron_r[6]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => cnt_pwron_r_reg(6),
      I1 => \cnt_pwron_r[8]_i_2_n_0\,
      O => \p_0_in__1\(6)
    );
\cnt_pwron_r[7]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"6A"
    )
        port map (
      I0 => cnt_pwron_r_reg(7),
      I1 => \cnt_pwron_r[8]_i_2_n_0\,
      I2 => cnt_pwron_r_reg(6),
      O => \p_0_in__1\(7)
    );
\cnt_pwron_r[8]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6AAA"
    )
        port map (
      I0 => cnt_pwron_r_reg(8),
      I1 => cnt_pwron_r_reg(6),
      I2 => \cnt_pwron_r[8]_i_2_n_0\,
      I3 => cnt_pwron_r_reg(7),
      O => \p_0_in__1\(8)
    );
\cnt_pwron_r[8]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8000000000000000"
    )
        port map (
      I0 => cnt_pwron_r_reg(3),
      I1 => cnt_pwron_r_reg(1),
      I2 => cnt_pwron_r_reg(0),
      I3 => cnt_pwron_r_reg(2),
      I4 => cnt_pwron_r_reg(4),
      I5 => cnt_pwron_r_reg(5),
      O => \cnt_pwron_r[8]_i_2_n_0\
    );
\cnt_pwron_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => pwron_ce_r,
      D => \p_0_in__1\(0),
      Q => cnt_pwron_r_reg(0),
      R => \cnt_pwron_ce_r_reg[0]_0\
    );
\cnt_pwron_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => pwron_ce_r,
      D => \p_0_in__1\(1),
      Q => cnt_pwron_r_reg(1),
      R => \cnt_pwron_ce_r_reg[0]_0\
    );
\cnt_pwron_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => pwron_ce_r,
      D => \p_0_in__1\(2),
      Q => cnt_pwron_r_reg(2),
      R => \cnt_pwron_ce_r_reg[0]_0\
    );
\cnt_pwron_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => pwron_ce_r,
      D => \p_0_in__1\(3),
      Q => cnt_pwron_r_reg(3),
      R => \cnt_pwron_ce_r_reg[0]_0\
    );
\cnt_pwron_r_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => pwron_ce_r,
      D => \p_0_in__1\(4),
      Q => cnt_pwron_r_reg(4),
      R => \cnt_pwron_ce_r_reg[0]_0\
    );
\cnt_pwron_r_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => pwron_ce_r,
      D => \p_0_in__1\(5),
      Q => cnt_pwron_r_reg(5),
      R => \cnt_pwron_ce_r_reg[0]_0\
    );
\cnt_pwron_r_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => pwron_ce_r,
      D => \p_0_in__1\(6),
      Q => cnt_pwron_r_reg(6),
      R => \cnt_pwron_ce_r_reg[0]_0\
    );
\cnt_pwron_r_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => pwron_ce_r,
      D => \p_0_in__1\(7),
      Q => cnt_pwron_r_reg(7),
      R => \cnt_pwron_ce_r_reg[0]_0\
    );
\cnt_pwron_r_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => pwron_ce_r,
      D => \p_0_in__1\(8),
      Q => cnt_pwron_r_reg(8),
      R => \cnt_pwron_ce_r_reg[0]_0\
    );
cnt_pwron_reset_done_r_i_1: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000F200"
    )
        port map (
      I0 => cnt_pwron_cke_done_r_i_3_n_0,
      I1 => cnt_pwron_reset_done_r_i_2_n_0,
      I2 => cnt_pwron_reset_done_r,
      I3 => \calib_seq_reg[0]_0\(0),
      I4 => \rd_addr_reg[7]\,
      O => cnt_pwron_reset_done_r_i_1_n_0
    );
cnt_pwron_reset_done_r_i_2: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFEFFFFFFFFFF"
    )
        port map (
      I0 => cnt_pwron_r_reg(8),
      I1 => cnt_pwron_r_reg(7),
      I2 => cnt_pwron_r_reg(1),
      I3 => cnt_pwron_r_reg(2),
      I4 => cnt_pwron_r_reg(6),
      I5 => cnt_pwron_r_reg(4),
      O => cnt_pwron_reset_done_r_i_2_n_0
    );
cnt_pwron_reset_done_r_reg: unisim.vcomponents.FDRE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => '1',
      D => cnt_pwron_reset_done_r_i_1_n_0,
      Q => cnt_pwron_reset_done_r,
      R => '0'
    );
cnt_txpr_done_r_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAAAAAAAABAA"
    )
        port map (
      I0 => cnt_txpr_done_r,
      I1 => cnt_txpr_done_r_i_2_n_0,
      I2 => cnt_txpr_r_reg(7),
      I3 => cnt_txpr_r_reg(4),
      I4 => cnt_txpr_r_reg(6),
      I5 => cnt_txpr_r_reg(3),
      O => cnt_txpr_done_r_i_1_n_0
    );
cnt_txpr_done_r_i_2: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFDF"
    )
        port map (
      I0 => cnt_txpr_r_reg(1),
      I1 => cnt_txpr_r_reg(0),
      I2 => cnt_txpr_r_reg(2),
      I3 => cnt_txpr_r_reg(5),
      O => cnt_txpr_done_r_i_2_n_0
    );
cnt_txpr_done_r_reg: unisim.vcomponents.FDRE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => '1',
      D => cnt_txpr_done_r_i_1_n_0,
      Q => cnt_txpr_done_r,
      R => clear
    );
\cnt_txpr_r[0]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => cnt_txpr_r_reg(0),
      O => \p_0_in__2\(0)
    );
\cnt_txpr_r[1]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => cnt_txpr_r_reg(1),
      I1 => cnt_txpr_r_reg(0),
      O => \p_0_in__2\(1)
    );
\cnt_txpr_r[2]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"6A"
    )
        port map (
      I0 => cnt_txpr_r_reg(2),
      I1 => cnt_txpr_r_reg(0),
      I2 => cnt_txpr_r_reg(1),
      O => \p_0_in__2\(2)
    );
\cnt_txpr_r[3]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6AAA"
    )
        port map (
      I0 => cnt_txpr_r_reg(3),
      I1 => cnt_txpr_r_reg(1),
      I2 => cnt_txpr_r_reg(0),
      I3 => cnt_txpr_r_reg(2),
      O => \p_0_in__2\(3)
    );
\cnt_txpr_r[4]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"6AAAAAAA"
    )
        port map (
      I0 => cnt_txpr_r_reg(4),
      I1 => cnt_txpr_r_reg(2),
      I2 => cnt_txpr_r_reg(0),
      I3 => cnt_txpr_r_reg(1),
      I4 => cnt_txpr_r_reg(3),
      O => \p_0_in__2\(4)
    );
\cnt_txpr_r[5]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"6AAAAAAAAAAAAAAA"
    )
        port map (
      I0 => cnt_txpr_r_reg(5),
      I1 => cnt_txpr_r_reg(3),
      I2 => cnt_txpr_r_reg(1),
      I3 => cnt_txpr_r_reg(0),
      I4 => cnt_txpr_r_reg(2),
      I5 => cnt_txpr_r_reg(4),
      O => \p_0_in__2\(5)
    );
\cnt_txpr_r[6]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => cnt_txpr_r_reg(6),
      I1 => \cnt_txpr_r[7]_i_3_n_0\,
      O => \p_0_in__2\(6)
    );
\cnt_txpr_r[7]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => cnt_pwron_cke_done_r,
      O => clear
    );
\cnt_txpr_r[7]_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"6A"
    )
        port map (
      I0 => cnt_txpr_r_reg(7),
      I1 => \cnt_txpr_r[7]_i_3_n_0\,
      I2 => cnt_txpr_r_reg(6),
      O => \p_0_in__2\(7)
    );
\cnt_txpr_r[7]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8000000000000000"
    )
        port map (
      I0 => cnt_txpr_r_reg(5),
      I1 => cnt_txpr_r_reg(3),
      I2 => cnt_txpr_r_reg(1),
      I3 => cnt_txpr_r_reg(0),
      I4 => cnt_txpr_r_reg(2),
      I5 => cnt_txpr_r_reg(4),
      O => \cnt_txpr_r[7]_i_3_n_0\
    );
\cnt_txpr_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => '1',
      D => \p_0_in__2\(0),
      Q => cnt_txpr_r_reg(0),
      R => clear
    );
\cnt_txpr_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => '1',
      D => \p_0_in__2\(1),
      Q => cnt_txpr_r_reg(1),
      R => clear
    );
\cnt_txpr_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => '1',
      D => \p_0_in__2\(2),
      Q => cnt_txpr_r_reg(2),
      R => clear
    );
\cnt_txpr_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => '1',
      D => \p_0_in__2\(3),
      Q => cnt_txpr_r_reg(3),
      R => clear
    );
\cnt_txpr_r_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => '1',
      D => \p_0_in__2\(4),
      Q => cnt_txpr_r_reg(4),
      R => clear
    );
\cnt_txpr_r_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => '1',
      D => \p_0_in__2\(5),
      Q => cnt_txpr_r_reg(5),
      R => clear
    );
\cnt_txpr_r_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => '1',
      D => \p_0_in__2\(6),
      Q => cnt_txpr_r_reg(6),
      R => clear
    );
\cnt_txpr_r_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => '1',
      D => \p_0_in__2\(7),
      Q => cnt_txpr_r_reg(7),
      R => clear
    );
complex_act_start_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00FF000002020000"
    )
        port map (
      I0 => \init_state_r_reg_n_0_[4]\,
      I1 => complex_act_start_i_2_n_0,
      I2 => \wrcal_reads[7]_i_4_n_0\,
      I3 => prbs_rdlvl_start_i_3_n_0,
      I4 => \init_state_r_reg_n_0_[1]\,
      I5 => \^q\(0),
      O => complex_act_start0
    );
complex_act_start_i_2: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => init_state_r(6),
      I1 => \init_state_r_reg_n_0_[5]\,
      O => complex_act_start_i_2_n_0
    );
complex_act_start_reg: unisim.vcomponents.FDRE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => '1',
      D => complex_act_start0,
      Q => complex_act_start,
      R => '0'
    );
\complex_address[9]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFF10FF10101000"
    )
        port map (
      I0 => complex_oclkdelay_calib_start_int_i_2_n_0,
      I1 => \init_state_r_reg_n_0_[1]\,
      I2 => \^q\(0),
      I3 => init_state_r1(2),
      I4 => \complex_address[9]_i_2_n_0\,
      I5 => \complex_address[9]_i_3_n_0\,
      O => complex_address0
    );
\complex_address[9]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFBFFFFFFF"
    )
        port map (
      I0 => init_state_r1(6),
      I1 => init_state_r1(5),
      I2 => init_state_r1(4),
      I3 => init_state_r1(3),
      I4 => init_state_r1(0),
      I5 => init_state_r1(1),
      O => \complex_address[9]_i_2_n_0\
    );
\complex_address[9]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0080000000000000"
    )
        port map (
      I0 => \gen_no_mirror.div_clk_loop[0].phy_address[12]_i_2_n_0\,
      I1 => \init_state_r_reg_n_0_[2]\,
      I2 => \init_state_r_reg_n_0_[5]\,
      I3 => init_state_r(6),
      I4 => \init_state_r_reg_n_0_[4]\,
      I5 => \init_state_r_reg_n_0_[3]\,
      O => \complex_address[9]_i_3_n_0\
    );
\complex_address_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => complex_address0,
      D => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[0]\,
      Q => \complex_address_reg_n_0_[0]\,
      R => \en_cnt_div4.enable_wrlvl_cnt_reg[2]_0\
    );
\complex_address_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => complex_address0,
      D => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[1]\,
      Q => \complex_address_reg_n_0_[1]\,
      R => \en_cnt_div4.enable_wrlvl_cnt_reg[2]_0\
    );
\complex_address_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => complex_address0,
      D => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[2]\,
      Q => \complex_address_reg_n_0_[2]\,
      R => \en_cnt_div4.enable_wrlvl_cnt_reg[2]_0\
    );
\complex_address_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => complex_address0,
      D => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[3]\,
      Q => \complex_address_reg_n_0_[3]\,
      R => \en_cnt_div4.enable_wrlvl_cnt_reg[2]_0\
    );
\complex_address_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => complex_address0,
      D => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[4]\,
      Q => \complex_address_reg_n_0_[4]\,
      R => \en_cnt_div4.enable_wrlvl_cnt_reg[2]_0\
    );
\complex_address_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => complex_address0,
      D => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[5]\,
      Q => \complex_address_reg_n_0_[5]\,
      R => \en_cnt_div4.enable_wrlvl_cnt_reg[2]_0\
    );
\complex_address_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => complex_address0,
      D => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[6]\,
      Q => \complex_address_reg_n_0_[6]\,
      R => \en_cnt_div4.enable_wrlvl_cnt_reg[2]_0\
    );
\complex_address_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => complex_address0,
      D => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[7]\,
      Q => \complex_address_reg_n_0_[7]\,
      R => \en_cnt_div4.enable_wrlvl_cnt_reg[2]_0\
    );
\complex_address_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => complex_address0,
      D => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[8]\,
      Q => \complex_address_reg_n_0_[8]\,
      R => \en_cnt_div4.enable_wrlvl_cnt_reg[2]_0\
    );
\complex_address_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => complex_address0,
      D => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[9]\,
      Q => \complex_address_reg_n_0_[9]\,
      R => \en_cnt_div4.enable_wrlvl_cnt_reg[2]_0\
    );
complex_byte_rd_done_i_1: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00001110"
    )
        port map (
      I0 => write_calib_reg_0,
      I1 => \^prbs_rdlvl_done_pulse_reg_0\,
      I2 => complex_byte_rd_done_i_2_n_0,
      I3 => complex_byte_rd_done,
      I4 => \stg1_wr_rd_cnt[8]_i_5_n_0\,
      O => complex_byte_rd_done_i_1_n_0
    );
complex_byte_rd_done_i_2: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000800000000000"
    )
        port map (
      I0 => complex_row1_rd_cnt(1),
      I1 => complex_row1_rd_cnt(0),
      I2 => complex_row1_rd_cnt(2),
      I3 => complex_row1_rd_done,
      I4 => complex_row1_rd_done_r1,
      I5 => complex_oclkdelay_calib_done_r1_reg_0,
      O => complex_byte_rd_done_i_2_n_0
    );
complex_byte_rd_done_reg: unisim.vcomponents.FDRE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => '1',
      D => complex_byte_rd_done_i_1_n_0,
      Q => complex_byte_rd_done,
      R => '0'
    );
\complex_num_reads[0]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFF26EE"
    )
        port map (
      I0 => \complex_num_reads_reg_n_0_[0]\,
      I1 => \complex_num_reads[3]_i_2_n_0\,
      I2 => \complex_num_writes[4]_i_6_n_0\,
      I3 => \complex_num_reads[2]_i_3_n_0\,
      I4 => \complex_num_reads[3]_i_4_n_0\,
      O => \complex_num_reads[0]_i_1_n_0\
    );
\complex_num_reads[1]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0222FE2200000000"
    )
        port map (
      I0 => \complex_num_reads_reg_n_0_[1]\,
      I1 => \complex_num_reads[2]_i_5_n_0\,
      I2 => \complex_num_writes[2]_i_5_n_0\,
      I3 => \complex_num_reads[2]_i_3_n_0\,
      I4 => \complex_num_reads[1]_i_2_n_0\,
      I5 => \complex_num_reads[2]_i_2_n_0\,
      O => \complex_num_reads[1]_i_1_n_0\
    );
\complex_num_reads[1]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"A88A"
    )
        port map (
      I0 => \complex_num_writes[4]_i_7_n_0\,
      I1 => \complex_num_writes[4]_i_6_n_0\,
      I2 => \complex_num_reads_reg_n_0_[1]\,
      I3 => \complex_num_reads_reg_n_0_[0]\,
      O => \complex_num_reads[1]_i_2_n_0\
    );
\complex_num_reads[2]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0022000008AA0800"
    )
        port map (
      I0 => \complex_num_reads[2]_i_2_n_0\,
      I1 => \complex_num_reads[2]_i_3_n_0\,
      I2 => \complex_num_reads[2]_i_4_n_0\,
      I3 => \complex_num_reads[2]_i_5_n_0\,
      I4 => \complex_num_reads_reg_n_0_[2]\,
      I5 => \complex_num_writes[2]_i_5_n_0\,
      O => \complex_num_reads[2]_i_1_n_0\
    );
\complex_num_reads[2]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0015555555555555"
    )
        port map (
      I0 => \rd_addr_reg[7]\,
      I1 => \complex_num_reads_reg_n_0_[2]\,
      I2 => \complex_num_reads_reg_n_0_[1]\,
      I3 => \complex_num_reads_reg_n_0_[3]\,
      I4 => \complex_num_writes[4]_i_12_n_0\,
      I5 => \complex_num_reads[2]_i_3_n_0\,
      O => \complex_num_reads[2]_i_2_n_0\
    );
\complex_num_reads[2]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000004000"
    )
        port map (
      I0 => \complex_num_reads[2]_i_6_n_0\,
      I1 => complex_wait_cnt_reg(2),
      I2 => complex_wait_cnt_reg(3),
      I3 => complex_wait_cnt_reg(1),
      I4 => complex_wait_cnt_reg(0),
      I5 => complex_row0_rd_done,
      O => \complex_num_reads[2]_i_3_n_0\
    );
\complex_num_reads[2]_i_4\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"802A"
    )
        port map (
      I0 => \complex_num_writes[2]_i_8_n_0\,
      I1 => \complex_num_reads_reg_n_0_[1]\,
      I2 => \complex_num_reads_reg_n_0_[0]\,
      I3 => \complex_num_reads_reg_n_0_[2]\,
      O => \complex_num_reads[2]_i_4_n_0\
    );
\complex_num_reads[2]_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"F8"
    )
        port map (
      I0 => \complex_num_reads[2]_i_3_n_0\,
      I1 => \complex_num_reads[3]_i_7_n_0\,
      I2 => \complex_num_reads[3]_i_2_n_0\,
      O => \complex_num_reads[2]_i_5_n_0\
    );
\complex_num_reads[2]_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFDFFFFFFFFFFFFF"
    )
        port map (
      I0 => \init_state_r_reg_n_0_[5]\,
      I1 => init_state_r(6),
      I2 => \init_state_r_reg_n_0_[4]\,
      I3 => \init_state_r_reg_n_0_[2]\,
      I4 => \init_state_r_reg_n_0_[3]\,
      I5 => \gen_no_mirror.div_clk_loop[0].phy_address[12]_i_2_n_0\,
      O => \complex_num_reads[2]_i_6_n_0\
    );
\complex_num_reads[3]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"00E2"
    )
        port map (
      I0 => \complex_num_reads_reg_n_0_[3]\,
      I1 => \complex_num_reads[3]_i_2_n_0\,
      I2 => \complex_num_reads[3]_i_3_n_0\,
      I3 => \complex_num_reads[3]_i_4_n_0\,
      O => \complex_num_reads[3]_i_1_n_0\
    );
\complex_num_reads[3]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0EFEFEFE"
    )
        port map (
      I0 => \complex_num_writes[3]_i_4_n_0\,
      I1 => \^stg1_wr_done\,
      I2 => \complex_num_reads[2]_i_3_n_0\,
      I3 => \complex_num_reads[3]_i_5_n_0\,
      I4 => \complex_num_reads[3]_i_6_n_0\,
      O => \complex_num_reads[3]_i_2_n_0\
    );
\complex_num_reads[3]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8AA8A8A8A8A8A8A8"
    )
        port map (
      I0 => \complex_num_reads[2]_i_3_n_0\,
      I1 => \complex_num_writes[4]_i_6_n_0\,
      I2 => \complex_num_reads_reg_n_0_[3]\,
      I3 => \complex_num_reads_reg_n_0_[2]\,
      I4 => \complex_num_reads_reg_n_0_[1]\,
      I5 => \complex_num_reads_reg_n_0_[0]\,
      O => \complex_num_reads[3]_i_3_n_0\
    );
\complex_num_reads[3]_i_4\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F5D5"
    )
        port map (
      I0 => \complex_num_reads[2]_i_2_n_0\,
      I1 => \complex_num_reads[3]_i_7_n_0\,
      I2 => \complex_num_reads[2]_i_3_n_0\,
      I3 => \complex_num_writes[2]_i_5_n_0\,
      O => \complex_num_reads[3]_i_4_n_0\
    );
\complex_num_reads[3]_i_5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"55554440"
    )
        port map (
      I0 => \complex_num_writes[4]_i_12_n_0\,
      I1 => \complex_num_reads_reg_n_0_[2]\,
      I2 => \complex_num_reads_reg_n_0_[0]\,
      I3 => \complex_num_reads_reg_n_0_[1]\,
      I4 => \complex_num_reads_reg_n_0_[3]\,
      O => \complex_num_reads[3]_i_5_n_0\
    );
\complex_num_reads[3]_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"BABABAAABAAAAAAA"
    )
        port map (
      I0 => \complex_num_writes[4]_i_10_n_0\,
      I1 => \complex_num_writes[4]_i_6_n_0\,
      I2 => \complex_num_reads_reg_n_0_[3]\,
      I3 => \complex_num_reads_reg_n_0_[2]\,
      I4 => \complex_num_reads_reg_n_0_[1]\,
      I5 => \complex_num_writes[4]_i_13_n_0\,
      O => \complex_num_reads[3]_i_6_n_0\
    );
\complex_num_reads[3]_i_7\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000000080"
    )
        port map (
      I0 => \complex_num_writes[2]_i_9_n_0\,
      I1 => \stg1_wr_rd_cnt_reg_n_0_[3]\,
      I2 => \stg1_wr_rd_cnt_reg_n_0_[0]\,
      I3 => \stg1_wr_rd_cnt_reg_n_0_[2]\,
      I4 => \stg1_wr_rd_cnt_reg_n_0_[5]\,
      I5 => \stg1_wr_rd_cnt_reg_n_0_[4]\,
      O => \complex_num_reads[3]_i_7_n_0\
    );
\complex_num_reads_dec[0]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"74"
    )
        port map (
      I0 => complex_num_reads_dec(0),
      I1 => \complex_num_reads_dec[3]_i_3_n_0\,
      I2 => \complex_num_reads_reg_n_0_[0]\,
      O => \complex_num_reads_dec[0]_i_1_n_0\
    );
\complex_num_reads_dec[1]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9F90"
    )
        port map (
      I0 => complex_num_reads_dec(1),
      I1 => complex_num_reads_dec(0),
      I2 => \complex_num_reads_dec[3]_i_3_n_0\,
      I3 => \complex_num_reads_reg_n_0_[1]\,
      O => \complex_num_reads_dec[1]_i_1_n_0\
    );
\complex_num_reads_dec[2]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"A9FFA900"
    )
        port map (
      I0 => complex_num_reads_dec(2),
      I1 => complex_num_reads_dec(0),
      I2 => complex_num_reads_dec(1),
      I3 => \complex_num_reads_dec[3]_i_3_n_0\,
      I4 => \complex_num_reads_reg_n_0_[2]\,
      O => \complex_num_reads_dec[2]_i_1_n_0\
    );
\complex_num_reads_dec[3]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"DDDDDDDDDDDDDDD5"
    )
        port map (
      I0 => \complex_num_reads_dec[3]_i_3_n_0\,
      I1 => \stg1_wr_rd_cnt[8]_i_4_n_0\,
      I2 => complex_num_reads_dec(2),
      I3 => complex_num_reads_dec(1),
      I4 => complex_num_reads_dec(0),
      I5 => complex_num_reads_dec(3),
      O => \complex_num_reads_dec[3]_i_1_n_0\
    );
\complex_num_reads_dec[3]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAA9FFFFAAA90000"
    )
        port map (
      I0 => complex_num_reads_dec(3),
      I1 => complex_num_reads_dec(2),
      I2 => complex_num_reads_dec(1),
      I3 => complex_num_reads_dec(0),
      I4 => \complex_num_reads_dec[3]_i_3_n_0\,
      I5 => \complex_num_reads_reg_n_0_[3]\,
      O => \complex_num_reads_dec[3]_i_2_n_0\
    );
\complex_num_reads_dec[3]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"5555555554555555"
    )
        port map (
      I0 => \complex_num_reads_dec[3]_i_4_n_0\,
      I1 => complex_oclkdelay_calib_start_int_i_2_n_0,
      I2 => \init_state_r_reg_n_0_[1]\,
      I3 => \^q\(0),
      I4 => \init_state_r[5]_i_13_n_0\,
      I5 => complex_row0_rd_done,
      O => \complex_num_reads_dec[3]_i_3_n_0\
    );
\complex_num_reads_dec[3]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFF00000020"
    )
        port map (
      I0 => \init_state_r_reg_n_0_[4]\,
      I1 => init_state_r(6),
      I2 => \init_state_r_reg_n_0_[5]\,
      I3 => \wrcal_reads[7]_i_4_n_0\,
      I4 => prbs_rdlvl_start_i_2_n_0,
      I5 => \^stg1_wr_done\,
      O => \complex_num_reads_dec[3]_i_4_n_0\
    );
\complex_num_reads_dec_reg[0]\: unisim.vcomponents.FDSE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => \complex_num_reads_dec[3]_i_1_n_0\,
      D => \complex_num_reads_dec[0]_i_1_n_0\,
      Q => complex_num_reads_dec(0),
      S => \en_cnt_div4.enable_wrlvl_cnt_reg[2]_0\
    );
\complex_num_reads_dec_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => \complex_num_reads_dec[3]_i_1_n_0\,
      D => \complex_num_reads_dec[1]_i_1_n_0\,
      Q => complex_num_reads_dec(1),
      R => \en_cnt_div4.enable_wrlvl_cnt_reg[2]_0\
    );
\complex_num_reads_dec_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => \complex_num_reads_dec[3]_i_1_n_0\,
      D => \complex_num_reads_dec[2]_i_1_n_0\,
      Q => complex_num_reads_dec(2),
      R => \en_cnt_div4.enable_wrlvl_cnt_reg[2]_0\
    );
\complex_num_reads_dec_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => \complex_num_reads_dec[3]_i_1_n_0\,
      D => \complex_num_reads_dec[3]_i_2_n_0\,
      Q => complex_num_reads_dec(3),
      R => \en_cnt_div4.enable_wrlvl_cnt_reg[2]_0\
    );
\complex_num_reads_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => '1',
      D => \complex_num_reads[0]_i_1_n_0\,
      Q => \complex_num_reads_reg_n_0_[0]\,
      R => '0'
    );
\complex_num_reads_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => '1',
      D => \complex_num_reads[1]_i_1_n_0\,
      Q => \complex_num_reads_reg_n_0_[1]\,
      R => '0'
    );
\complex_num_reads_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => '1',
      D => \complex_num_reads[2]_i_1_n_0\,
      Q => \complex_num_reads_reg_n_0_[2]\,
      R => '0'
    );
\complex_num_reads_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => '1',
      D => \complex_num_reads[3]_i_1_n_0\,
      Q => \complex_num_reads_reg_n_0_[3]\,
      R => '0'
    );
\complex_num_writes[0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"22622E6EFFFFFFFF"
    )
        port map (
      I0 => \complex_num_writes_reg_n_0_[0]\,
      I1 => \complex_num_writes[3]_i_2_n_0\,
      I2 => \complex_num_writes[4]_i_5_n_0\,
      I3 => \complex_num_writes[4]_i_6_n_0\,
      I4 => \complex_num_writes[0]_i_2_n_0\,
      I5 => \complex_num_writes[4]_i_2_n_0\,
      O => \complex_num_writes[0]_i_1_n_0\
    );
\complex_num_writes[0]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000000800"
    )
        port map (
      I0 => complex_row0_wr_done,
      I1 => \init_state_r_reg_n_0_[4]\,
      I2 => init_state_r(6),
      I3 => \init_state_r_reg_n_0_[5]\,
      I4 => \wrcal_reads[7]_i_4_n_0\,
      I5 => prbs_rdlvl_start_i_2_n_0,
      O => \complex_num_writes[0]_i_2_n_0\
    );
\complex_num_writes[1]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FEEE022200000000"
    )
        port map (
      I0 => \complex_num_writes_reg_n_0_[1]\,
      I1 => \complex_num_writes[2]_i_4_n_0\,
      I2 => \complex_num_writes[4]_i_5_n_0\,
      I3 => \complex_num_writes[2]_i_5_n_0\,
      I4 => \complex_num_writes[1]_i_2_n_0\,
      I5 => \complex_num_writes[2]_i_2_n_0\,
      O => \complex_num_writes[1]_i_1_n_0\
    );
\complex_num_writes[1]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"CECECEEECEEECECE"
    )
        port map (
      I0 => \complex_num_writes[4]_i_5_n_0\,
      I1 => \complex_num_writes[0]_i_2_n_0\,
      I2 => \complex_num_writes[4]_i_7_n_0\,
      I3 => \complex_num_writes[4]_i_6_n_0\,
      I4 => \complex_num_writes_reg_n_0_[0]\,
      I5 => \complex_num_writes_reg_n_0_[1]\,
      O => \complex_num_writes[1]_i_2_n_0\
    );
\complex_num_writes[2]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00008A808A808A80"
    )
        port map (
      I0 => \complex_num_writes[2]_i_2_n_0\,
      I1 => \complex_num_writes[2]_i_3_n_0\,
      I2 => \complex_num_writes[2]_i_4_n_0\,
      I3 => \complex_num_writes_reg_n_0_[2]\,
      I4 => \complex_num_writes[4]_i_5_n_0\,
      I5 => \complex_num_writes[2]_i_5_n_0\,
      O => \complex_num_writes[2]_i_1_n_0\
    );
\complex_num_writes[2]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0222AAAAAAAAAAAA"
    )
        port map (
      I0 => \complex_num_writes_reg[1]_0\,
      I1 => \complex_num_writes[2]_i_7_n_0\,
      I2 => \complex_num_writes_reg_n_0_[2]\,
      I3 => \complex_num_writes_reg_n_0_[1]\,
      I4 => \complex_num_writes[4]_i_12_n_0\,
      I5 => \complex_num_writes[4]_i_5_n_0\,
      O => \complex_num_writes[2]_i_2_n_0\
    );
\complex_num_writes[2]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"BFFFFBBBAAAAAAAA"
    )
        port map (
      I0 => \complex_num_writes[0]_i_2_n_0\,
      I1 => \complex_num_writes[2]_i_8_n_0\,
      I2 => \complex_num_writes_reg_n_0_[1]\,
      I3 => \complex_num_writes_reg_n_0_[0]\,
      I4 => \complex_num_writes_reg_n_0_[2]\,
      I5 => \complex_num_writes[4]_i_5_n_0\,
      O => \complex_num_writes[2]_i_3_n_0\
    );
\complex_num_writes[2]_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"BA"
    )
        port map (
      I0 => \complex_num_writes[4]_i_4_n_0\,
      I1 => \complex_num_writes[2]_i_8_n_0\,
      I2 => \complex_num_writes[4]_i_5_n_0\,
      O => \complex_num_writes[2]_i_4_n_0\
    );
\complex_num_writes[2]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000008000"
    )
        port map (
      I0 => \complex_num_writes[2]_i_9_n_0\,
      I1 => \stg1_wr_rd_cnt_reg_n_0_[4]\,
      I2 => \stg1_wr_rd_cnt_reg_n_0_[2]\,
      I3 => \stg1_wr_rd_cnt_reg_n_0_[0]\,
      I4 => \stg1_wr_rd_cnt_reg_n_0_[5]\,
      I5 => \stg1_wr_rd_cnt_reg_n_0_[3]\,
      O => \complex_num_writes[2]_i_5_n_0\
    );
\complex_num_writes[2]_i_7\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => \complex_num_writes_reg_n_0_[3]\,
      I1 => \complex_num_writes_reg_n_0_[4]\,
      O => \complex_num_writes[2]_i_7_n_0\
    );
\complex_num_writes[2]_i_8\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \complex_num_reads[3]_i_7_n_0\,
      I1 => \complex_num_writes[4]_i_6_n_0\,
      O => \complex_num_writes[2]_i_8_n_0\
    );
\complex_num_writes[2]_i_9\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0004"
    )
        port map (
      I0 => \stg1_wr_rd_cnt_reg_n_0_[1]\,
      I1 => \stg1_wr_rd_cnt_reg_n_0_[6]\,
      I2 => \stg1_wr_rd_cnt_reg_n_0_[7]\,
      I3 => \stg1_wr_rd_cnt_reg_n_0_[8]\,
      O => \complex_num_writes[2]_i_9_n_0\
    );
\complex_num_writes[3]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"EEE2E2E200000000"
    )
        port map (
      I0 => \complex_num_writes_reg_n_0_[3]\,
      I1 => \complex_num_writes[3]_i_2_n_0\,
      I2 => \complex_num_writes[3]_i_3_n_0\,
      I3 => complex_row0_wr_done,
      I4 => \complex_num_writes[3]_i_4_n_0\,
      I5 => \complex_num_writes[4]_i_2_n_0\,
      O => \complex_num_writes[3]_i_1_n_0\
    );
\complex_num_writes[3]_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"F8"
    )
        port map (
      I0 => \complex_num_writes[4]_i_6_n_0\,
      I1 => \complex_num_writes[4]_i_5_n_0\,
      I2 => \complex_num_writes[4]_i_4_n_0\,
      O => \complex_num_writes[3]_i_2_n_0\
    );
\complex_num_writes[3]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8AA8A8A8A8A8A8A8"
    )
        port map (
      I0 => \complex_num_writes[4]_i_5_n_0\,
      I1 => \complex_num_writes[4]_i_6_n_0\,
      I2 => \complex_num_writes_reg_n_0_[3]\,
      I3 => \complex_num_writes_reg_n_0_[1]\,
      I4 => \complex_num_writes_reg_n_0_[0]\,
      I5 => \complex_num_writes_reg_n_0_[2]\,
      O => \complex_num_writes[3]_i_3_n_0\
    );
\complex_num_writes[3]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000100000000000"
    )
        port map (
      I0 => prbs_rdlvl_start_i_2_n_0,
      I1 => \init_state_r_reg_n_0_[3]\,
      I2 => \init_state_r_reg_n_0_[2]\,
      I3 => \init_state_r_reg_n_0_[5]\,
      I4 => init_state_r(6),
      I5 => \init_state_r_reg_n_0_[4]\,
      O => \complex_num_writes[3]_i_4_n_0\
    );
\complex_num_writes[4]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00008A808A808A80"
    )
        port map (
      I0 => \complex_num_writes[4]_i_2_n_0\,
      I1 => \complex_num_writes[4]_i_3_n_0\,
      I2 => \complex_num_writes[4]_i_4_n_0\,
      I3 => \complex_num_writes_reg_n_0_[4]\,
      I4 => \complex_num_writes[4]_i_5_n_0\,
      I5 => \complex_num_writes[4]_i_6_n_0\,
      O => \complex_num_writes[4]_i_1_n_0\
    );
\complex_num_writes[4]_i_10\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFF8880AAAA"
    )
        port map (
      I0 => \stg1_wr_rd_cnt_reg_n_0_[6]\,
      I1 => \stg1_wr_rd_cnt_reg_n_0_[3]\,
      I2 => \stg1_wr_rd_cnt_reg_n_0_[2]\,
      I3 => \stg1_wr_rd_cnt_reg_n_0_[1]\,
      I4 => \complex_num_writes[4]_i_14_n_0\,
      I5 => \complex_num_writes[4]_i_15_n_0\,
      O => \complex_num_writes[4]_i_10_n_0\
    );
\complex_num_writes[4]_i_11\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFEEEEE"
    )
        port map (
      I0 => \complex_num_writes_reg_n_0_[4]\,
      I1 => \complex_num_writes_reg_n_0_[3]\,
      I2 => \complex_num_writes_reg_n_0_[1]\,
      I3 => \complex_num_writes_reg_n_0_[0]\,
      I4 => \complex_num_writes_reg_n_0_[2]\,
      O => \complex_num_writes[4]_i_11_n_0\
    );
\complex_num_writes[4]_i_12\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"FE"
    )
        port map (
      I0 => \stg1_wr_rd_cnt_reg_n_0_[8]\,
      I1 => \stg1_wr_rd_cnt_reg_n_0_[7]\,
      I2 => \complex_num_writes[4]_i_16_n_0\,
      O => \complex_num_writes[4]_i_12_n_0\
    );
\complex_num_writes[4]_i_13\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFFA8"
    )
        port map (
      I0 => \stg1_wr_rd_cnt_reg_n_0_[5]\,
      I1 => \stg1_wr_rd_cnt_reg_n_0_[3]\,
      I2 => \stg1_wr_rd_cnt_reg_n_0_[4]\,
      I3 => \stg1_wr_rd_cnt_reg_n_0_[6]\,
      I4 => \stg1_wr_rd_cnt_reg_n_0_[8]\,
      I5 => \stg1_wr_rd_cnt_reg_n_0_[7]\,
      O => \complex_num_writes[4]_i_13_n_0\
    );
\complex_num_writes[4]_i_14\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \stg1_wr_rd_cnt_reg_n_0_[5]\,
      I1 => \stg1_wr_rd_cnt_reg_n_0_[4]\,
      O => \complex_num_writes[4]_i_14_n_0\
    );
\complex_num_writes[4]_i_15\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => \stg1_wr_rd_cnt_reg_n_0_[7]\,
      I1 => \stg1_wr_rd_cnt_reg_n_0_[8]\,
      O => \complex_num_writes[4]_i_15_n_0\
    );
\complex_num_writes[4]_i_16\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"C8C8C8C0C8C0C8C0"
    )
        port map (
      I0 => \stg1_wr_rd_cnt_reg_n_0_[4]\,
      I1 => \stg1_wr_rd_cnt_reg_n_0_[6]\,
      I2 => \stg1_wr_rd_cnt_reg_n_0_[5]\,
      I3 => \stg1_wr_rd_cnt_reg_n_0_[3]\,
      I4 => \stg1_wr_rd_cnt_reg_n_0_[1]\,
      I5 => \stg1_wr_rd_cnt_reg_n_0_[2]\,
      O => \complex_num_writes[4]_i_16_n_0\
    );
\complex_num_writes[4]_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"8A"
    )
        port map (
      I0 => \complex_num_writes[2]_i_2_n_0\,
      I1 => \complex_num_writes[4]_i_7_n_0\,
      I2 => \complex_num_writes[4]_i_5_n_0\,
      O => \complex_num_writes[4]_i_2_n_0\
    );
\complex_num_writes[4]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"C0EAEAC0EAC0EAC0"
    )
        port map (
      I0 => \complex_num_writes[4]_i_5_n_0\,
      I1 => complex_row0_wr_done,
      I2 => \complex_num_writes[3]_i_4_n_0\,
      I3 => \complex_num_writes_reg_n_0_[4]\,
      I4 => \complex_num_writes[4]_i_8_n_0\,
      I5 => \complex_num_writes_reg_n_0_[3]\,
      O => \complex_num_writes[4]_i_3_n_0\
    );
\complex_num_writes[4]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFABFBAAAAAAAA"
    )
        port map (
      I0 => \complex_num_writes[3]_i_4_n_0\,
      I1 => \complex_num_writes[4]_i_9_n_0\,
      I2 => \complex_num_writes[4]_i_10_n_0\,
      I3 => \complex_num_writes[4]_i_11_n_0\,
      I4 => \complex_num_writes[4]_i_12_n_0\,
      I5 => \complex_num_writes[4]_i_5_n_0\,
      O => \complex_num_writes[4]_i_4_n_0\
    );
\complex_num_writes[4]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000800000"
    )
        port map (
      I0 => complex_wait_cnt_reg(2),
      I1 => complex_wait_cnt_reg(3),
      I2 => complex_wait_cnt_reg(1),
      I3 => complex_wait_cnt_reg(0),
      I4 => \complex_address[9]_i_3_n_0\,
      I5 => complex_row0_wr_done,
      O => \complex_num_writes[4]_i_5_n_0\
    );
\complex_num_writes[4]_i_6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"40000000"
    )
        port map (
      I0 => complex_sample_cnt_inc_i_3_n_0,
      I1 => \stg1_wr_rd_cnt_reg_n_0_[5]\,
      I2 => \stg1_wr_rd_cnt_reg_n_0_[0]\,
      I3 => \stg1_wr_rd_cnt_reg_n_0_[1]\,
      I4 => \stg1_wr_rd_cnt_reg_n_0_[2]\,
      O => \complex_num_writes[4]_i_6_n_0\
    );
\complex_num_writes[4]_i_7\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"EFFFFFDFFFFFFFFF"
    )
        port map (
      I0 => \stg1_wr_rd_cnt_reg_n_0_[3]\,
      I1 => \stg1_wr_rd_cnt_reg_n_0_[5]\,
      I2 => \stg1_wr_rd_cnt_reg_n_0_[0]\,
      I3 => \stg1_wr_rd_cnt_reg_n_0_[2]\,
      I4 => \stg1_wr_rd_cnt_reg_n_0_[4]\,
      I5 => \complex_num_writes[2]_i_9_n_0\,
      O => \complex_num_writes[4]_i_7_n_0\
    );
\complex_num_writes[4]_i_8\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"80"
    )
        port map (
      I0 => \complex_num_writes_reg_n_0_[2]\,
      I1 => \complex_num_writes_reg_n_0_[0]\,
      I2 => \complex_num_writes_reg_n_0_[1]\,
      O => \complex_num_writes[4]_i_8_n_0\
    );
\complex_num_writes[4]_i_9\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FEAAEAAA"
    )
        port map (
      I0 => \complex_num_writes_reg_n_0_[4]\,
      I1 => \complex_num_writes_reg_n_0_[1]\,
      I2 => \complex_num_writes_reg_n_0_[2]\,
      I3 => \complex_num_writes_reg_n_0_[3]\,
      I4 => \complex_num_writes[4]_i_13_n_0\,
      O => \complex_num_writes[4]_i_9_n_0\
    );
\complex_num_writes_dec[0]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"74"
    )
        port map (
      I0 => complex_num_writes_dec(0),
      I1 => \complex_num_writes_dec[4]_i_4_n_0\,
      I2 => \complex_num_writes_reg_n_0_[0]\,
      O => \complex_num_writes_dec[0]_i_1_n_0\
    );
\complex_num_writes_dec[1]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9F90"
    )
        port map (
      I0 => complex_num_writes_dec(1),
      I1 => complex_num_writes_dec(0),
      I2 => \complex_num_writes_dec[4]_i_4_n_0\,
      I3 => \complex_num_writes_reg_n_0_[1]\,
      O => \complex_num_writes_dec[1]_i_1_n_0\
    );
\complex_num_writes_dec[2]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"A9FFA900"
    )
        port map (
      I0 => complex_num_writes_dec(2),
      I1 => complex_num_writes_dec(0),
      I2 => complex_num_writes_dec(1),
      I3 => \complex_num_writes_dec[4]_i_4_n_0\,
      I4 => \complex_num_writes_reg_n_0_[2]\,
      O => \complex_num_writes_dec[2]_i_1_n_0\
    );
\complex_num_writes_dec[3]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAA9FFFFAAA90000"
    )
        port map (
      I0 => complex_num_writes_dec(3),
      I1 => complex_num_writes_dec(2),
      I2 => complex_num_writes_dec(1),
      I3 => complex_num_writes_dec(0),
      I4 => \complex_num_writes_dec[4]_i_4_n_0\,
      I5 => \complex_num_writes_reg_n_0_[3]\,
      O => \complex_num_writes_dec[3]_i_1_n_0\
    );
\complex_num_writes_dec[4]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => \^prbs_rdlvl_done_pulse_reg_0\,
      I1 => write_calib_reg_0,
      O => complex_row0_rd_done1
    );
\complex_num_writes_dec[4]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FDFF5555"
    )
        port map (
      I0 => \complex_num_writes_dec[4]_i_4_n_0\,
      I1 => complex_num_writes_dec(4),
      I2 => complex_num_writes_dec(3),
      I3 => \complex_num_writes_dec[4]_i_5_n_0\,
      I4 => \stg1_wr_rd_cnt[8]_i_5_n_0\,
      O => \complex_num_writes_dec[4]_i_2_n_0\
    );
\complex_num_writes_dec[4]_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"9AFF9A00"
    )
        port map (
      I0 => complex_num_writes_dec(4),
      I1 => complex_num_writes_dec(3),
      I2 => \complex_num_writes_dec[4]_i_5_n_0\,
      I3 => \complex_num_writes_dec[4]_i_4_n_0\,
      I4 => \complex_num_writes_reg_n_0_[4]\,
      O => \complex_num_writes_dec[4]_i_3_n_0\
    );
\complex_num_writes_dec[4]_i_4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"000000DF"
    )
        port map (
      I0 => \init_state_r[5]_i_13_n_0\,
      I1 => complex_row0_rd_done,
      I2 => \complex_address[9]_i_3_n_0\,
      I3 => \^stg1_wr_done\,
      I4 => \complex_num_writes[3]_i_4_n_0\,
      O => \complex_num_writes_dec[4]_i_4_n_0\
    );
\complex_num_writes_dec[4]_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"01"
    )
        port map (
      I0 => complex_num_writes_dec(0),
      I1 => complex_num_writes_dec(1),
      I2 => complex_num_writes_dec(2),
      O => \complex_num_writes_dec[4]_i_5_n_0\
    );
\complex_num_writes_dec_reg[0]\: unisim.vcomponents.FDSE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => \complex_num_writes_dec[4]_i_2_n_0\,
      D => \complex_num_writes_dec[0]_i_1_n_0\,
      Q => complex_num_writes_dec(0),
      S => complex_row0_rd_done1
    );
\complex_num_writes_dec_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => \complex_num_writes_dec[4]_i_2_n_0\,
      D => \complex_num_writes_dec[1]_i_1_n_0\,
      Q => complex_num_writes_dec(1),
      R => complex_row0_rd_done1
    );
\complex_num_writes_dec_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => \complex_num_writes_dec[4]_i_2_n_0\,
      D => \complex_num_writes_dec[2]_i_1_n_0\,
      Q => complex_num_writes_dec(2),
      R => complex_row0_rd_done1
    );
\complex_num_writes_dec_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => \complex_num_writes_dec[4]_i_2_n_0\,
      D => \complex_num_writes_dec[3]_i_1_n_0\,
      Q => complex_num_writes_dec(3),
      R => complex_row0_rd_done1
    );
\complex_num_writes_dec_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => \complex_num_writes_dec[4]_i_2_n_0\,
      D => \complex_num_writes_dec[4]_i_3_n_0\,
      Q => complex_num_writes_dec(4),
      R => complex_row0_rd_done1
    );
\complex_num_writes_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => '1',
      D => \complex_num_writes[0]_i_1_n_0\,
      Q => \complex_num_writes_reg_n_0_[0]\,
      R => '0'
    );
\complex_num_writes_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => '1',
      D => \complex_num_writes[1]_i_1_n_0\,
      Q => \complex_num_writes_reg_n_0_[1]\,
      R => '0'
    );
\complex_num_writes_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => '1',
      D => \complex_num_writes[2]_i_1_n_0\,
      Q => \complex_num_writes_reg_n_0_[2]\,
      R => '0'
    );
\complex_num_writes_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => '1',
      D => \complex_num_writes[3]_i_1_n_0\,
      Q => \complex_num_writes_reg_n_0_[3]\,
      R => '0'
    );
\complex_num_writes_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => '1',
      D => \complex_num_writes[4]_i_1_n_0\,
      Q => \complex_num_writes_reg_n_0_[4]\,
      R => '0'
    );
complex_ocal_odt_ext_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000FFFFFFDF"
    )
        port map (
      I0 => cnt_cmd_done_m7_r,
      I1 => prbs_rdlvl_start_i_2_n_0,
      I2 => \init_state_r_reg_n_0_[4]\,
      I3 => \init_state_r[3]_i_6_n_0\,
      I4 => \cnt_init_mr_r[0]_i_2_n_0\,
      I5 => complex_ocal_odt_ext_i_2_n_0,
      O => complex_ocal_odt_ext_i_1_n_0
    );
complex_ocal_odt_ext_i_2: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFF1100FFF0"
    )
        port map (
      I0 => complex_ocal_odt_ext_i_3_n_0,
      I1 => \^q\(0),
      I2 => prbs_rdlvl_start_i_3_n_0,
      I3 => \init_state_r_reg_n_0_[1]\,
      I4 => complex_ocal_odt_ext,
      I5 => write_calib_reg_0,
      O => complex_ocal_odt_ext_i_2_n_0
    );
complex_ocal_odt_ext_i_3: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFEFFFFF"
    )
        port map (
      I0 => \init_state_r_reg_n_0_[2]\,
      I1 => \init_state_r_reg_n_0_[3]\,
      I2 => \init_state_r_reg_n_0_[4]\,
      I3 => init_state_r(6),
      I4 => \init_state_r_reg_n_0_[5]\,
      O => complex_ocal_odt_ext_i_3_n_0
    );
complex_ocal_odt_ext_reg: unisim.vcomponents.FDRE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => '1',
      D => complex_ocal_odt_ext_i_1_n_0,
      Q => complex_ocal_odt_ext,
      R => '0'
    );
complex_ocal_reset_rd_addr_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"44444F4444444444"
    )
        port map (
      I0 => prbs_last_byte_done_r,
      I1 => prbs_last_byte_done,
      I2 => complex_ocal_reset_rd_addr_i_2_n_0,
      I3 => complex_wait_cnt_reg(3),
      I4 => complex_wait_cnt_reg(2),
      I5 => complex_ocal_reset_rd_addr_i_3_n_0,
      O => complex_ocal_reset_rd_addr0
    );
complex_ocal_reset_rd_addr_i_2: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => complex_wait_cnt_reg(1),
      I1 => complex_wait_cnt_reg(0),
      O => complex_ocal_reset_rd_addr_i_2_n_0
    );
complex_ocal_reset_rd_addr_i_3: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0080000000000000"
    )
        port map (
      I0 => \wrcal_reads[7]_i_5_n_0\,
      I1 => \init_state_r_reg_n_0_[2]\,
      I2 => \init_state_r_reg_n_0_[5]\,
      I3 => init_state_r(6),
      I4 => \init_state_r_reg_n_0_[4]\,
      I5 => \init_state_r_reg_n_0_[3]\,
      O => complex_ocal_reset_rd_addr_i_3_n_0
    );
complex_ocal_reset_rd_addr_reg: unisim.vcomponents.FDRE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => '1',
      D => complex_ocal_reset_rd_addr0,
      Q => \^complex_ocal_reset_rd_addr\,
      R => '0'
    );
complex_ocal_wr_start_i_1: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => \^complex_ocal_reset_rd_addr\,
      I1 => complex_ocal_wr_start,
      O => complex_ocal_wr_start_i_1_n_0
    );
complex_ocal_wr_start_reg: unisim.vcomponents.FDRE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => '1',
      D => complex_ocal_wr_start_i_1_n_0,
      Q => complex_ocal_wr_start,
      R => \victim_sel_reg[0]_0\(0)
    );
complex_oclkdelay_calib_done_r1_reg: unisim.vcomponents.FDRE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => '1',
      D => complex_oclkdelay_calib_done_r1_reg_0,
      Q => complex_oclkdelay_calib_done_r1,
      R => \victim_sel_reg[0]_0\(0)
    );
complex_oclkdelay_calib_start_int_i_1: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFF1000"
    )
        port map (
      I0 => complex_oclkdelay_calib_start_int_i_2_n_0,
      I1 => \^q\(0),
      I2 => \init_state_r_reg_n_0_[1]\,
      I3 => prbs_last_byte_done_r,
      I4 => complex_oclkdelay_calib_start_int,
      O => complex_oclkdelay_calib_start_int_i_1_n_0
    );
complex_oclkdelay_calib_start_int_i_2: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFDFFFFF"
    )
        port map (
      I0 => \init_state_r_reg_n_0_[3]\,
      I1 => \init_state_r_reg_n_0_[2]\,
      I2 => \init_state_r_reg_n_0_[4]\,
      I3 => init_state_r(6),
      I4 => \init_state_r_reg_n_0_[5]\,
      O => complex_oclkdelay_calib_start_int_i_2_n_0
    );
complex_oclkdelay_calib_start_int_reg: unisim.vcomponents.FDRE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => '1',
      D => complex_oclkdelay_calib_start_int_i_1_n_0,
      Q => complex_oclkdelay_calib_start_int,
      R => \victim_sel_reg[0]_0\(0)
    );
complex_oclkdelay_calib_start_r1_reg: unisim.vcomponents.FDRE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => '1',
      D => complex_oclkdelay_calib_start_int,
      Q => complex_oclkdelay_calib_start_r1,
      R => '0'
    );
complex_odt_ext_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000055551000"
    )
        port map (
      I0 => write_calib_reg_0,
      I1 => complex_sample_cnt_inc_i_2_n_0,
      I2 => rdlvl_stg1_done_r1,
      I3 => \stg1_wr_rd_cnt[8]_i_5_n_0\,
      I4 => complex_odt_ext,
      I5 => complex_row1_rd_done_i_2_n_0,
      O => complex_odt_ext_i_1_n_0
    );
complex_odt_ext_reg: unisim.vcomponents.FDRE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => '1',
      D => complex_odt_ext_i_1_n_0,
      Q => complex_odt_ext,
      R => '0'
    );
complex_row0_rd_done_i_1: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0010"
    )
        port map (
      I0 => \^prbs_rdlvl_done_pulse_reg_0\,
      I1 => write_calib_reg_0,
      I2 => complex_row0_rd_done_i_2_n_0,
      I3 => complex_sample_cnt_inc,
      O => complex_row0_rd_done_i_1_n_0
    );
complex_row0_rd_done_i_2: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFF0000E000"
    )
        port map (
      I0 => \^prbs_rdlvl_start_reg_0\,
      I1 => complex_oclkdelay_calib_start_int,
      I2 => complex_row1_wr_done,
      I3 => complex_row0_wr_done,
      I4 => wr_victim_inc_i_2_n_0,
      I5 => complex_row0_rd_done,
      O => complex_row0_rd_done_i_2_n_0
    );
complex_row0_rd_done_reg: unisim.vcomponents.FDRE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => '1',
      D => complex_row0_rd_done_i_1_n_0,
      Q => complex_row0_rd_done,
      R => '0'
    );
\complex_row1_rd_cnt[0]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000009A"
    )
        port map (
      I0 => complex_row1_rd_cnt(0),
      I1 => complex_row1_rd_done_r1,
      I2 => complex_row1_rd_done,
      I3 => \rd_addr_reg[7]\,
      I4 => \^prbs_rdlvl_done_pulse_reg_0\,
      O => \complex_row1_rd_cnt[0]_i_1_n_0\
    );
\complex_row1_rd_cnt[1]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000009AAA"
    )
        port map (
      I0 => complex_row1_rd_cnt(1),
      I1 => complex_row1_rd_done_r1,
      I2 => complex_row1_rd_done,
      I3 => complex_row1_rd_cnt(0),
      I4 => \rd_addr_reg[7]\,
      I5 => \^prbs_rdlvl_done_pulse_reg_0\,
      O => \complex_row1_rd_cnt[1]_i_1_n_0\
    );
\complex_row1_rd_cnt[2]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"000000009AAAAAAA"
    )
        port map (
      I0 => complex_row1_rd_cnt(2),
      I1 => complex_row1_rd_done_r1,
      I2 => complex_row1_rd_done,
      I3 => complex_row1_rd_cnt(1),
      I4 => complex_row1_rd_cnt(0),
      I5 => complex_row0_rd_done1,
      O => \complex_row1_rd_cnt[2]_i_1_n_0\
    );
\complex_row1_rd_cnt_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => '1',
      D => \complex_row1_rd_cnt[0]_i_1_n_0\,
      Q => complex_row1_rd_cnt(0),
      R => '0'
    );
\complex_row1_rd_cnt_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => '1',
      D => \complex_row1_rd_cnt[1]_i_1_n_0\,
      Q => complex_row1_rd_cnt(1),
      R => '0'
    );
\complex_row1_rd_cnt_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => '1',
      D => \complex_row1_rd_cnt[2]_i_1_n_0\,
      Q => complex_row1_rd_cnt(2),
      R => '0'
    );
complex_row1_rd_done_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000011110100"
    )
        port map (
      I0 => write_calib_reg_0,
      I1 => \^prbs_rdlvl_done_pulse_reg_0\,
      I2 => wr_victim_inc_i_2_n_0,
      I3 => complex_row0_rd_done,
      I4 => complex_row1_rd_done,
      I5 => complex_row1_rd_done_i_2_n_0,
      O => complex_row1_rd_done_i_1_n_0
    );
complex_row1_rd_done_i_2: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000000020"
    )
        port map (
      I0 => \init_state_r_reg_n_0_[4]\,
      I1 => \init_state_r_reg_n_0_[3]\,
      I2 => \init_state_r_reg_n_0_[2]\,
      I3 => \init_state_r_reg_n_0_[1]\,
      I4 => \^q\(0),
      I5 => init_state_r(6),
      O => complex_row1_rd_done_i_2_n_0
    );
complex_row1_rd_done_r1_reg: unisim.vcomponents.FDRE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => '1',
      D => complex_row1_rd_done,
      Q => complex_row1_rd_done_r1,
      R => '0'
    );
complex_row1_rd_done_reg: unisim.vcomponents.FDRE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => '1',
      D => complex_row1_rd_done_i_1_n_0,
      Q => complex_row1_rd_done,
      R => '0'
    );
\complex_row_cnt_ocal[0]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => complex_row_cnt_ocal_reg(0),
      O => \p_0_in__6\(0)
    );
\complex_row_cnt_ocal[1]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => complex_row_cnt_ocal_reg(1),
      I1 => complex_row_cnt_ocal_reg(0),
      O => \p_0_in__6\(1)
    );
\complex_row_cnt_ocal[2]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"6A"
    )
        port map (
      I0 => complex_row_cnt_ocal_reg(2),
      I1 => complex_row_cnt_ocal_reg(0),
      I2 => complex_row_cnt_ocal_reg(1),
      O => \p_0_in__6\(2)
    );
\complex_row_cnt_ocal[3]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFF8F"
    )
        port map (
      I0 => wr_victim_inc,
      I1 => \complex_row_cnt_ocal[3]_i_4_n_0\,
      I2 => rdlvl_stg1_done_r1,
      I3 => complex_byte_rd_done,
      I4 => \^prbs_rdlvl_done_pulse_reg_0\,
      I5 => write_calib_reg_0,
      O => complex_row_cnt_ocal0
    );
\complex_row_cnt_ocal[3]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000FFF80000"
    )
        port map (
      I0 => \complex_row_cnt_ocal[3]_i_5_n_0\,
      I1 => \complex_row_cnt_ocal[3]_i_6_n_0\,
      I2 => wr_victim_inc,
      I3 => complex_sample_cnt_inc_r2,
      I4 => complex_oclkdelay_calib_done_r1_reg_0,
      I5 => \complex_row_cnt_ocal[3]_i_4_n_0\,
      O => complex_row_cnt_ocal
    );
\complex_row_cnt_ocal[3]_i_3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6AAA"
    )
        port map (
      I0 => complex_row_cnt_ocal_reg(3),
      I1 => complex_row_cnt_ocal_reg(1),
      I2 => complex_row_cnt_ocal_reg(0),
      I3 => complex_row_cnt_ocal_reg(2),
      O => \p_0_in__6\(3)
    );
\complex_row_cnt_ocal[3]_i_4\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8000"
    )
        port map (
      I0 => complex_row_cnt_ocal_reg(3),
      I1 => complex_row_cnt_ocal_reg(1),
      I2 => complex_row_cnt_ocal_reg(0),
      I3 => complex_row_cnt_ocal_reg(2),
      O => \complex_row_cnt_ocal[3]_i_4_n_0\
    );
\complex_row_cnt_ocal[3]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"1000000000000000"
    )
        port map (
      I0 => wr_victim_inc_i_3_n_0,
      I1 => \stg1_wr_rd_cnt_reg_n_0_[0]\,
      I2 => \stg1_wr_rd_cnt_reg_n_0_[1]\,
      I3 => \stg1_wr_rd_cnt_reg_n_0_[3]\,
      I4 => \stg1_wr_rd_cnt_reg_n_0_[2]\,
      I5 => \stg1_wr_rd_cnt_reg_n_0_[4]\,
      O => \complex_row_cnt_ocal[3]_i_5_n_0\
    );
\complex_row_cnt_ocal[3]_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000010000000000"
    )
        port map (
      I0 => \^q\(0),
      I1 => \init_state_r_reg_n_0_[1]\,
      I2 => \wrcal_reads[7]_i_4_n_0\,
      I3 => \init_state_r_reg_n_0_[5]\,
      I4 => init_state_r(6),
      I5 => \init_state_r_reg_n_0_[4]\,
      O => \complex_row_cnt_ocal[3]_i_6_n_0\
    );
\complex_row_cnt_ocal_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => complex_row_cnt_ocal,
      D => \p_0_in__6\(0),
      Q => complex_row_cnt_ocal_reg(0),
      R => complex_row_cnt_ocal0
    );
\complex_row_cnt_ocal_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => complex_row_cnt_ocal,
      D => \p_0_in__6\(1),
      Q => complex_row_cnt_ocal_reg(1),
      R => complex_row_cnt_ocal0
    );
\complex_row_cnt_ocal_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => complex_row_cnt_ocal,
      D => \p_0_in__6\(2),
      Q => complex_row_cnt_ocal_reg(2),
      R => complex_row_cnt_ocal0
    );
\complex_row_cnt_ocal_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => complex_row_cnt_ocal,
      D => \p_0_in__6\(3),
      Q => complex_row_cnt_ocal_reg(3),
      R => complex_row_cnt_ocal0
    );
complex_sample_cnt_inc_i_1: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => complex_row1_rd_done,
      I1 => complex_sample_cnt_inc_i_2_n_0,
      O => complex_sample_cnt_inc0
    );
complex_sample_cnt_inc_i_2: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFFFFB"
    )
        port map (
      I0 => \stg1_wr_rd_cnt_reg_n_0_[2]\,
      I1 => \stg1_wr_rd_cnt_reg_n_0_[0]\,
      I2 => \stg1_wr_rd_cnt_reg_n_0_[1]\,
      I3 => complex_sample_cnt_inc_i_3_n_0,
      I4 => \stg1_wr_rd_cnt_reg_n_0_[5]\,
      O => complex_sample_cnt_inc_i_2_n_0
    );
complex_sample_cnt_inc_i_3: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFFFFE"
    )
        port map (
      I0 => \stg1_wr_rd_cnt_reg_n_0_[7]\,
      I1 => \stg1_wr_rd_cnt_reg_n_0_[8]\,
      I2 => \stg1_wr_rd_cnt_reg_n_0_[6]\,
      I3 => \stg1_wr_rd_cnt_reg_n_0_[4]\,
      I4 => \stg1_wr_rd_cnt_reg_n_0_[3]\,
      O => complex_sample_cnt_inc_i_3_n_0
    );
complex_sample_cnt_inc_r1_reg: unisim.vcomponents.FDRE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => '1',
      D => complex_sample_cnt_inc,
      Q => complex_sample_cnt_inc_r1,
      R => '0'
    );
complex_sample_cnt_inc_r2_reg: unisim.vcomponents.FDRE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => '1',
      D => complex_sample_cnt_inc_r1,
      Q => complex_sample_cnt_inc_r2,
      R => '0'
    );
complex_sample_cnt_inc_reg: unisim.vcomponents.FDRE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => '1',
      D => complex_sample_cnt_inc0,
      Q => complex_sample_cnt_inc,
      R => \victim_sel_reg[0]_0\(0)
    );
\complex_wait_cnt[0]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => complex_wait_cnt_reg(0),
      O => \p_0_in__7\(0)
    );
\complex_wait_cnt[1]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => complex_wait_cnt_reg(1),
      I1 => complex_wait_cnt_reg(0),
      O => \p_0_in__7\(1)
    );
\complex_wait_cnt[2]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"78"
    )
        port map (
      I0 => complex_wait_cnt_reg(1),
      I1 => complex_wait_cnt_reg(0),
      I2 => complex_wait_cnt_reg(2),
      O => \p_0_in__7\(2)
    );
\complex_wait_cnt[3]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFEAAAAAAA"
    )
        port map (
      I0 => \complex_wait_cnt[3]_i_3_n_0\,
      I1 => complex_wait_cnt_reg(0),
      I2 => complex_wait_cnt_reg(1),
      I3 => complex_wait_cnt_reg(2),
      I4 => complex_wait_cnt_reg(3),
      I5 => \rd_addr_reg[7]\,
      O => \complex_wait_cnt[3]_i_1_n_0\
    );
\complex_wait_cnt[3]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6AAA"
    )
        port map (
      I0 => complex_wait_cnt_reg(3),
      I1 => complex_wait_cnt_reg(1),
      I2 => complex_wait_cnt_reg(0),
      I3 => complex_wait_cnt_reg(2),
      O => \p_0_in__7\(3)
    );
\complex_wait_cnt[3]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFDFDDDFFDFFDFFF"
    )
        port map (
      I0 => \init_state_r_reg_n_0_[4]\,
      I1 => complex_act_start_i_2_n_0,
      I2 => \init_state_r_reg_n_0_[2]\,
      I3 => \init_state_r_reg_n_0_[3]\,
      I4 => \init_state_r_reg_n_0_[1]\,
      I5 => \^q\(0),
      O => \complex_wait_cnt[3]_i_3_n_0\
    );
\complex_wait_cnt_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => '1',
      D => \p_0_in__7\(0),
      Q => complex_wait_cnt_reg(0),
      R => \complex_wait_cnt[3]_i_1_n_0\
    );
\complex_wait_cnt_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => '1',
      D => \p_0_in__7\(1),
      Q => complex_wait_cnt_reg(1),
      R => \complex_wait_cnt[3]_i_1_n_0\
    );
\complex_wait_cnt_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => '1',
      D => \p_0_in__7\(2),
      Q => complex_wait_cnt_reg(2),
      R => \complex_wait_cnt[3]_i_1_n_0\
    );
\complex_wait_cnt_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => '1',
      D => \p_0_in__7\(3),
      Q => complex_wait_cnt_reg(3),
      R => \complex_wait_cnt[3]_i_1_n_0\
    );
\data_offset_1_i1[0]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \data_offset_1_i1_reg[0]\,
      I1 => phy_ctl_wr_i1_reg,
      I2 => calib_data_offset_1(0),
      O => \cmd_pipe_plus.mc_data_offset_1_reg[5]\(0)
    );
\data_offset_1_i1[1]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \data_offset_1_i1_reg[1]\,
      I1 => phy_ctl_wr_i1_reg,
      I2 => calib_data_offset_1(1),
      O => \cmd_pipe_plus.mc_data_offset_1_reg[5]\(1)
    );
\data_offset_1_i1[2]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \data_offset_1_i1_reg[2]\,
      I1 => phy_ctl_wr_i1_reg,
      I2 => calib_data_offset_1(2),
      O => \cmd_pipe_plus.mc_data_offset_1_reg[5]\(2)
    );
\data_offset_1_i1[3]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => mc_data_offset_1(0),
      I1 => phy_ctl_wr_i1_reg,
      I2 => calib_data_offset_1(3),
      O => \cmd_pipe_plus.mc_data_offset_1_reg[5]\(3)
    );
\data_offset_1_i1[4]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \data_offset_1_i1_reg[4]\,
      I1 => phy_ctl_wr_i1_reg,
      I2 => calib_data_offset_1(4),
      O => \cmd_pipe_plus.mc_data_offset_1_reg[5]\(4)
    );
\data_offset_1_i1[5]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \data_offset_1_i1_reg[5]\,
      I1 => phy_ctl_wr_i1_reg,
      I2 => calib_data_offset_1(5),
      O => \cmd_pipe_plus.mc_data_offset_1_reg[5]\(5)
    );
\data_offset_2_i1[0]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \data_offset_2_i1_reg[0]\,
      I1 => phy_ctl_wr_i1_reg,
      I2 => calib_data_offset_2(0),
      O => \cmd_pipe_plus.mc_data_offset_2_reg[5]\(0)
    );
\data_offset_2_i1[1]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \data_offset_2_i1_reg[1]\,
      I1 => phy_ctl_wr_i1_reg,
      I2 => calib_data_offset_2(1),
      O => \cmd_pipe_plus.mc_data_offset_2_reg[5]\(1)
    );
\data_offset_2_i1[2]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \data_offset_2_i1_reg[2]\,
      I1 => phy_ctl_wr_i1_reg,
      I2 => calib_data_offset_2(2),
      O => \cmd_pipe_plus.mc_data_offset_2_reg[5]\(2)
    );
\data_offset_2_i1[3]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => mc_data_offset_2(0),
      I1 => phy_ctl_wr_i1_reg,
      I2 => calib_data_offset_2(3),
      O => \cmd_pipe_plus.mc_data_offset_2_reg[5]\(3)
    );
\data_offset_2_i1[4]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \data_offset_2_i1_reg[4]\,
      I1 => phy_ctl_wr_i1_reg,
      I2 => calib_data_offset_2(4),
      O => \cmd_pipe_plus.mc_data_offset_2_reg[5]\(4)
    );
\data_offset_2_i1[5]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \data_offset_2_i1_reg[5]\,
      I1 => phy_ctl_wr_i1_reg,
      I2 => calib_data_offset_2(5),
      O => \cmd_pipe_plus.mc_data_offset_2_reg[5]\(5)
    );
ddr2_pre_flag_r_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"2222222222F02222"
    )
        port map (
      I0 => ddr2_pre_flag_r_reg_n_0,
      I1 => ddr2_pre_flag_r_i_2_n_0,
      I2 => \init_state_r_reg_n_0_[1]\,
      I3 => \^q\(0),
      I4 => \cnt_init_mr_r[0]_i_3_n_0\,
      I5 => \cnt_init_mr_r[0]_i_2_n_0\,
      O => ddr2_pre_flag_r_i_1_n_0
    );
ddr2_pre_flag_r_i_2: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8000000000000000"
    )
        port map (
      I0 => ddr2_refresh_flag_r_i_3_n_0,
      I1 => \^q\(0),
      I2 => \init_state_r_reg_n_0_[1]\,
      I3 => cnt_cmd_done_r,
      I4 => ddr2_refresh_flag_r,
      I5 => cnt_init_mr_done_r,
      O => ddr2_pre_flag_r_i_2_n_0
    );
ddr2_pre_flag_r_reg: unisim.vcomponents.FDRE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => '1',
      D => ddr2_pre_flag_r_i_1_n_0,
      Q => ddr2_pre_flag_r_reg_n_0,
      R => '0'
    );
ddr2_refresh_flag_r_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000FF8CFFCCFFCC"
    )
        port map (
      I0 => ddr2_refresh_flag_r_i_2_n_0,
      I1 => ddr2_refresh_flag_r,
      I2 => cnt_init_mr_done_r,
      I3 => cnt_init_mr_r1,
      I4 => \wrcal_reads[7]_i_5_n_0\,
      I5 => ddr2_refresh_flag_r_i_3_n_0,
      O => ddr2_refresh_flag_r_i_1_n_0
    );
ddr2_refresh_flag_r_i_2: unisim.vcomponents.LUT3
    generic map(
      INIT => X"7F"
    )
        port map (
      I0 => \^q\(0),
      I1 => \init_state_r_reg_n_0_[1]\,
      I2 => cnt_cmd_done_r,
      O => ddr2_refresh_flag_r_i_2_n_0
    );
ddr2_refresh_flag_r_i_3: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000001"
    )
        port map (
      I0 => init_state_r(6),
      I1 => \init_state_r_reg_n_0_[5]\,
      I2 => \init_state_r_reg_n_0_[4]\,
      I3 => \init_state_r_reg_n_0_[2]\,
      I4 => \init_state_r_reg_n_0_[3]\,
      O => ddr2_refresh_flag_r_i_3_n_0
    );
ddr2_refresh_flag_r_reg: unisim.vcomponents.FDRE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => '1',
      D => ddr2_refresh_flag_r_i_1_n_0,
      Q => ddr2_refresh_flag_r,
      R => '0'
    );
ddr3_lm_done_r_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFF00000004"
    )
        port map (
      I0 => prbs_rdlvl_start_i_2_n_0,
      I1 => ddr3_lm_done_r_reg_0,
      I2 => \init_state_r[3]_i_6_n_0\,
      I3 => \init_state_r_reg_n_0_[4]\,
      I4 => \cnt_init_mr_r[0]_i_2_n_0\,
      I5 => ddr3_lm_done_r,
      O => ddr3_lm_done_r_i_1_n_0
    );
ddr3_lm_done_r_reg: unisim.vcomponents.FDRE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => '1',
      D => ddr3_lm_done_r_i_1_n_0,
      Q => ddr3_lm_done_r,
      R => \en_cnt_div4.enable_wrlvl_cnt_reg[2]_0\
    );
detect_pi_found_dqs_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000010000000"
    )
        port map (
      I0 => \cnt_init_mr_r[0]_i_2_n_0\,
      I1 => \init_state_r[3]_i_6_n_0\,
      I2 => \init_state_r_reg_n_0_[4]\,
      I3 => detect_pi_found_dqs_i_2_n_0,
      I4 => \cnt_cmd_r[6]_i_4_n_0\,
      I5 => \cnt_cmd_r_reg_n_0_[6]\,
      O => detect_pi_found_dqs0
    );
detect_pi_found_dqs_i_2: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \init_state_r_reg_n_0_[1]\,
      I1 => \^q\(0),
      O => detect_pi_found_dqs_i_2_n_0
    );
detect_pi_found_dqs_reg: unisim.vcomponents.FDRE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => '1',
      D => detect_pi_found_dqs0,
      Q => detect_pi_found_dqs,
      R => \en_cnt_div4.enable_wrlvl_cnt_reg[2]_0\
    );
\dqs_asrt_cnt[0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000DADA00DA"
    )
        port map (
      I0 => dqs_asrt_cnt(0),
      I1 => dqs_asrt_cnt(1),
      I2 => wr_level_dqs_asrt,
      I3 => wrlvl_done_r,
      I4 => \^wrlvl_done_r1\,
      I5 => \rd_addr_reg[7]\,
      O => \dqs_asrt_cnt[0]_i_1_n_0\
    );
\dqs_asrt_cnt[1]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000ECEC00EC"
    )
        port map (
      I0 => dqs_asrt_cnt(0),
      I1 => dqs_asrt_cnt(1),
      I2 => wr_level_dqs_asrt,
      I3 => wrlvl_done_r,
      I4 => \^wrlvl_done_r1\,
      I5 => \rd_addr_reg[7]\,
      O => \dqs_asrt_cnt[1]_i_1_n_0\
    );
\dqs_asrt_cnt_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => '1',
      D => \dqs_asrt_cnt[0]_i_1_n_0\,
      Q => dqs_asrt_cnt(0),
      R => '0'
    );
\dqs_asrt_cnt_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => '1',
      D => \dqs_asrt_cnt[1]_i_1_n_0\,
      Q => dqs_asrt_cnt(1),
      R => '0'
    );
\en_cnt_div4.enable_wrlvl_cnt[0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000033333332"
    )
        port map (
      I0 => enable_wrlvl_cnt(1),
      I1 => enable_wrlvl_cnt(0),
      I2 => enable_wrlvl_cnt(3),
      I3 => enable_wrlvl_cnt(2),
      I4 => enable_wrlvl_cnt(4),
      I5 => \en_cnt_div4.enable_wrlvl_cnt_reg[4]_0\,
      O => \en_cnt_div4.enable_wrlvl_cnt[0]_i_1_n_0\
    );
\en_cnt_div4.enable_wrlvl_cnt[1]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000099999998"
    )
        port map (
      I0 => enable_wrlvl_cnt(1),
      I1 => enable_wrlvl_cnt(0),
      I2 => enable_wrlvl_cnt(3),
      I3 => enable_wrlvl_cnt(2),
      I4 => enable_wrlvl_cnt(4),
      I5 => \en_cnt_div4.enable_wrlvl_cnt_reg[4]_0\,
      O => \en_cnt_div4.enable_wrlvl_cnt[1]_i_1_n_0\
    );
\en_cnt_div4.enable_wrlvl_cnt[2]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFEE11EE10"
    )
        port map (
      I0 => enable_wrlvl_cnt(1),
      I1 => enable_wrlvl_cnt(0),
      I2 => enable_wrlvl_cnt(3),
      I3 => enable_wrlvl_cnt(2),
      I4 => enable_wrlvl_cnt(4),
      I5 => \^init_state_r_reg[4]_0\,
      O => \en_cnt_div4.enable_wrlvl_cnt[2]_i_1_n_0\
    );
\en_cnt_div4.enable_wrlvl_cnt[3]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFF0E1F0E0"
    )
        port map (
      I0 => enable_wrlvl_cnt(1),
      I1 => enable_wrlvl_cnt(0),
      I2 => enable_wrlvl_cnt(3),
      I3 => enable_wrlvl_cnt(2),
      I4 => enable_wrlvl_cnt(4),
      I5 => \^init_state_r_reg[4]_0\,
      O => \en_cnt_div4.enable_wrlvl_cnt[3]_i_1_n_0\
    );
\en_cnt_div4.enable_wrlvl_cnt[3]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0002FFFF00020002"
    )
        port map (
      I0 => detect_pi_found_dqs_i_2_n_0,
      I1 => \init_state_r[3]_i_6_n_0\,
      I2 => \init_state_r_reg_n_0_[4]\,
      I3 => \wrcal_reads[7]_i_4_n_0\,
      I4 => enable_wrlvl_cnt0,
      I5 => wrlvl_odt,
      O => \^init_state_r_reg[4]_0\
    );
\en_cnt_div4.enable_wrlvl_cnt[3]_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFFFFE"
    )
        port map (
      I0 => enable_wrlvl_cnt(4),
      I1 => enable_wrlvl_cnt(2),
      I2 => enable_wrlvl_cnt(3),
      I3 => enable_wrlvl_cnt(0),
      I4 => enable_wrlvl_cnt(1),
      O => enable_wrlvl_cnt0
    );
\en_cnt_div4.enable_wrlvl_cnt[4]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000FFFE0000"
    )
        port map (
      I0 => enable_wrlvl_cnt(1),
      I1 => enable_wrlvl_cnt(0),
      I2 => enable_wrlvl_cnt(3),
      I3 => enable_wrlvl_cnt(2),
      I4 => enable_wrlvl_cnt(4),
      I5 => \en_cnt_div4.enable_wrlvl_cnt_reg[4]_0\,
      O => \en_cnt_div4.enable_wrlvl_cnt[4]_i_1_n_0\
    );
\en_cnt_div4.enable_wrlvl_cnt_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => '1',
      D => \en_cnt_div4.enable_wrlvl_cnt[0]_i_1_n_0\,
      Q => enable_wrlvl_cnt(0),
      R => '0'
    );
\en_cnt_div4.enable_wrlvl_cnt_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => '1',
      D => \en_cnt_div4.enable_wrlvl_cnt[1]_i_1_n_0\,
      Q => enable_wrlvl_cnt(1),
      R => '0'
    );
\en_cnt_div4.enable_wrlvl_cnt_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => '1',
      D => \en_cnt_div4.enable_wrlvl_cnt[2]_i_1_n_0\,
      Q => enable_wrlvl_cnt(2),
      R => \en_cnt_div4.enable_wrlvl_cnt_reg[2]_0\
    );
\en_cnt_div4.enable_wrlvl_cnt_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => '1',
      D => \en_cnt_div4.enable_wrlvl_cnt[3]_i_1_n_0\,
      Q => enable_wrlvl_cnt(3),
      R => \en_cnt_div4.enable_wrlvl_cnt_reg[2]_0\
    );
\en_cnt_div4.enable_wrlvl_cnt_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => '1',
      D => \en_cnt_div4.enable_wrlvl_cnt[4]_i_1_n_0\,
      Q => enable_wrlvl_cnt(4),
      R => '0'
    );
\en_cnt_div4.wrlvl_odt_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0054"
    )
        port map (
      I0 => write_calib_reg_0,
      I1 => \en_cnt_div4.wrlvl_odt_i_2_n_0\,
      I2 => wrlvl_odt,
      I3 => wrlvl_odt_ctl,
      O => \en_cnt_div4.wrlvl_odt_i_1_n_0\
    );
\en_cnt_div4.wrlvl_odt_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000100"
    )
        port map (
      I0 => enable_wrlvl_cnt(2),
      I1 => enable_wrlvl_cnt(3),
      I2 => enable_wrlvl_cnt(4),
      I3 => enable_wrlvl_cnt(0),
      I4 => enable_wrlvl_cnt(1),
      O => \en_cnt_div4.wrlvl_odt_i_2_n_0\
    );
\en_cnt_div4.wrlvl_odt_reg\: unisim.vcomponents.FDRE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => '1',
      D => \en_cnt_div4.wrlvl_odt_i_1_n_0\,
      Q => wrlvl_odt,
      R => '0'
    );
first_rdlvl_pat_r_i_1: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFF4"
    )
        port map (
      I0 => \stg1_wr_rd_cnt[8]_i_5_n_0\,
      I1 => \^first_rdlvl_pat_r\,
      I2 => rdlvl_stg1_rank_done,
      I3 => write_calib_reg_0,
      O => first_rdlvl_pat_r_i_1_n_0
    );
first_rdlvl_pat_r_reg: unisim.vcomponents.FDRE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => '1',
      D => first_rdlvl_pat_r_i_1_n_0,
      Q => \^first_rdlvl_pat_r\,
      R => '0'
    );
first_wrcal_pat_r_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFEFAAAB"
    )
        port map (
      I0 => write_calib_reg_0,
      I1 => calib_wrdata_en_i_2_n_0,
      I2 => \^q\(0),
      I3 => \init_state_r_reg_n_0_[1]\,
      I4 => \^first_wrcal_pat_r\,
      I5 => wrcal_resume_w,
      O => first_wrcal_pat_r_i_1_n_0
    );
first_wrcal_pat_r_reg: unisim.vcomponents.FDRE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => '1',
      D => first_wrcal_pat_r_i_1_n_0,
      Q => \^first_wrcal_pat_r\,
      R => '0'
    );
\gen_no_mirror.div_clk_loop[0].phy_address[0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFEAAAAAAAAA"
    )
        port map (
      I0 => \gen_no_mirror.div_clk_loop[0].phy_address[0]_i_2_n_0\,
      I1 => \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_3_n_0\,
      I2 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[0]\,
      I3 => \gen_no_mirror.div_clk_loop[0].phy_address[0]_i_3_n_0\,
      I4 => \gen_no_mirror.div_clk_loop[0].phy_address[0]_i_4_n_0\,
      I5 => \gen_no_mirror.div_clk_loop[0].phy_address[6]_i_5_n_0\,
      O => address_w(0)
    );
\gen_no_mirror.div_clk_loop[0].phy_address[0]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0200"
    )
        port map (
      I0 => \gen_no_mirror.div_clk_loop[0].phy_address[1]_i_5_n_0\,
      I1 => init_state_r(6),
      I2 => reg_ctrl_cnt_r_reg(3),
      I3 => reg_ctrl_cnt_r_reg(0),
      O => \gen_no_mirror.div_clk_loop[0].phy_address[0]_i_2_n_0\
    );
\gen_no_mirror.div_clk_loop[0].phy_address[0]_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"080808AA"
    )
        port map (
      I0 => \complex_address_reg_n_0_[0]\,
      I1 => \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_7_n_0\,
      I2 => \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_6_n_0\,
      I3 => \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_10_n_0\,
      I4 => \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_9_n_0\,
      O => \gen_no_mirror.div_clk_loop[0].phy_address[0]_i_3_n_0\
    );
\gen_no_mirror.div_clk_loop[0].phy_address[0]_i_4\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"00E2"
    )
        port map (
      I0 => \row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[0]\,
      I1 => complex_oclkdelay_calib_done_r1_reg_0,
      I2 => complex_row_cnt_ocal_reg(0),
      I3 => \gen_no_mirror.div_clk_loop[0].phy_address[6]_i_8_n_0\,
      O => \gen_no_mirror.div_clk_loop[0].phy_address[0]_i_4_n_0\
    );
\gen_no_mirror.div_clk_loop[0].phy_address[10]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"44444000FFFFFFFF"
    )
        port map (
      I0 => \gen_no_mirror.div_clk_loop[0].phy_address[10]_i_2_n_0\,
      I1 => \gen_no_mirror.div_clk_loop[0].phy_address[10]_i_3_n_0\,
      I2 => cnt_init_mr_r(0),
      I3 => cnt_init_mr_r(1),
      I4 => \gen_no_mirror.div_clk_loop[0].phy_address_reg[10]_0\,
      I5 => \gen_no_mirror.div_clk_loop[0].phy_address[10]_i_5_n_0\,
      O => address_w(10)
    );
\gen_no_mirror.div_clk_loop[0].phy_address[10]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFF7FEF"
    )
        port map (
      I0 => \init_state_r_reg_n_0_[4]\,
      I1 => \^q\(0),
      I2 => \init_state_r_reg_n_0_[1]\,
      I3 => \init_state_r_reg_n_0_[3]\,
      I4 => \init_state_r_reg_n_0_[2]\,
      I5 => \init_state_r_reg_n_0_[5]\,
      O => \gen_no_mirror.div_clk_loop[0].phy_address[10]_i_2_n_0\
    );
\gen_no_mirror.div_clk_loop[0].phy_address[10]_i_3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \gen_no_mirror.div_clk_loop[0].phy_address[10]_i_6_n_0\,
      I1 => init_state_r(6),
      O => \gen_no_mirror.div_clk_loop[0].phy_address[10]_i_3_n_0\
    );
\gen_no_mirror.div_clk_loop[0].phy_address[10]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFEFFFFFFF6FE"
    )
        port map (
      I0 => \^q\(0),
      I1 => \init_state_r_reg_n_0_[1]\,
      I2 => \wrcal_reads[7]_i_4_n_0\,
      I3 => \init_state_r_reg_n_0_[4]\,
      I4 => init_state_r(6),
      I5 => \init_state_r_reg_n_0_[5]\,
      O => \gen_no_mirror.div_clk_loop[0].phy_address[10]_i_5_n_0\
    );
\gen_no_mirror.div_clk_loop[0].phy_address[10]_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000040070000"
    )
        port map (
      I0 => \init_state_r_reg_n_0_[3]\,
      I1 => \init_state_r_reg_n_0_[2]\,
      I2 => \init_state_r_reg_n_0_[5]\,
      I3 => \^q\(0),
      I4 => \init_state_r_reg_n_0_[1]\,
      I5 => \init_state_r_reg_n_0_[4]\,
      O => \gen_no_mirror.div_clk_loop[0].phy_address[10]_i_6_n_0\
    );
\gen_no_mirror.div_clk_loop[0].phy_address[12]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000001000400000"
    )
        port map (
      I0 => \init_state_r_reg_n_0_[3]\,
      I1 => \init_state_r_reg_n_0_[2]\,
      I2 => \gen_no_mirror.div_clk_loop[0].phy_address[12]_i_2_n_0\,
      I3 => init_state_r(6),
      I4 => \init_state_r_reg_n_0_[5]\,
      I5 => \init_state_r_reg_n_0_[4]\,
      O => address_w(12)
    );
\gen_no_mirror.div_clk_loop[0].phy_address[12]_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \^q\(0),
      I1 => \init_state_r_reg_n_0_[1]\,
      O => \gen_no_mirror.div_clk_loop[0].phy_address[12]_i_2_n_0\
    );
\gen_no_mirror.div_clk_loop[0].phy_address[1]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"EAFFFFFFAAAAAAAA"
    )
        port map (
      I0 => \gen_no_mirror.div_clk_loop[0].phy_address[1]_i_2_n_0\,
      I1 => \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_3_n_0\,
      I2 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[1]\,
      I3 => \gen_no_mirror.div_clk_loop[0].phy_address[1]_i_3_n_0\,
      I4 => \gen_no_mirror.div_clk_loop[0].phy_address[1]_i_4_n_0\,
      I5 => \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_2_n_0\,
      O => address_w(1)
    );
\gen_no_mirror.div_clk_loop[0].phy_address[1]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00405555"
    )
        port map (
      I0 => init_state_r(6),
      I1 => \gen_no_mirror.div_clk_loop[0].phy_address[1]_i_5_n_0\,
      I2 => reg_ctrl_cnt_r_reg(1),
      I3 => reg_ctrl_cnt_r_reg(3),
      I4 => \gen_no_mirror.div_clk_loop[0].phy_address[6]_i_9_n_0\,
      O => \gen_no_mirror.div_clk_loop[0].phy_address[1]_i_2_n_0\
    );
\gen_no_mirror.div_clk_loop[0].phy_address[1]_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"DDD0FFFF"
    )
        port map (
      I0 => \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_7_n_0\,
      I1 => \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_6_n_0\,
      I2 => \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_10_n_0\,
      I3 => \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_9_n_0\,
      I4 => \complex_address_reg_n_0_[1]\,
      O => \gen_no_mirror.div_clk_loop[0].phy_address[1]_i_3_n_0\
    );
\gen_no_mirror.div_clk_loop[0].phy_address[1]_i_4\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"ABFB"
    )
        port map (
      I0 => \gen_no_mirror.div_clk_loop[0].phy_address[6]_i_8_n_0\,
      I1 => \row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[1]\,
      I2 => complex_oclkdelay_calib_done_r1_reg_0,
      I3 => complex_row_cnt_ocal_reg(1),
      O => \gen_no_mirror.div_clk_loop[0].phy_address[1]_i_4_n_0\
    );
\gen_no_mirror.div_clk_loop[0].phy_address[1]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"1000000000000000"
    )
        port map (
      I0 => \init_state_r_reg_n_0_[5]\,
      I1 => \init_state_r_reg_n_0_[2]\,
      I2 => \init_state_r_reg_n_0_[3]\,
      I3 => \init_state_r_reg_n_0_[1]\,
      I4 => \^q\(0),
      I5 => \init_state_r_reg_n_0_[4]\,
      O => \gen_no_mirror.div_clk_loop[0].phy_address[1]_i_5_n_0\
    );
\gen_no_mirror.div_clk_loop[0].phy_address[2]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFF8FFF0000"
    )
        port map (
      I0 => \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_3_n_0\,
      I1 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[2]\,
      I2 => \gen_no_mirror.div_clk_loop[0].phy_address[2]_i_2_n_0\,
      I3 => \gen_no_mirror.div_clk_loop[0].phy_address[2]_i_3_n_0\,
      I4 => \gen_no_mirror.div_clk_loop[0].phy_address[6]_i_5_n_0\,
      I5 => \gen_no_mirror.div_clk_loop[0].phy_address[2]_i_4_n_0\,
      O => address_w(2)
    );
\gen_no_mirror.div_clk_loop[0].phy_address[2]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"DDD0FFFF"
    )
        port map (
      I0 => \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_7_n_0\,
      I1 => \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_6_n_0\,
      I2 => \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_10_n_0\,
      I3 => \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_9_n_0\,
      I4 => \complex_address_reg_n_0_[2]\,
      O => \gen_no_mirror.div_clk_loop[0].phy_address[2]_i_2_n_0\
    );
\gen_no_mirror.div_clk_loop[0].phy_address[2]_i_3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"ABFB"
    )
        port map (
      I0 => \gen_no_mirror.div_clk_loop[0].phy_address[6]_i_8_n_0\,
      I1 => \row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[2]\,
      I2 => complex_oclkdelay_calib_done_r1_reg_0,
      I3 => complex_row_cnt_ocal_reg(2),
      O => \gen_no_mirror.div_clk_loop[0].phy_address[2]_i_3_n_0\
    );
\gen_no_mirror.div_clk_loop[0].phy_address[2]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"BABBBABABABABABA"
    )
        port map (
      I0 => \gen_no_mirror.div_clk_loop[0].phy_address[6]_i_6_n_0\,
      I1 => \gen_no_mirror.div_clk_loop[0].phy_address[2]_i_5_n_0\,
      I2 => \gen_no_mirror.div_clk_loop[0].phy_address[10]_i_3_n_0\,
      I3 => reg_ctrl_cnt_r_reg(1),
      I4 => reg_ctrl_cnt_r_reg(2),
      I5 => \gen_no_mirror.div_clk_loop[0].phy_address[2]_i_6_n_0\,
      O => \gen_no_mirror.div_clk_loop[0].phy_address[2]_i_4_n_0\
    );
\gen_no_mirror.div_clk_loop[0].phy_address[2]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FDFFFFFFBFFFFFFF"
    )
        port map (
      I0 => \init_state_r_reg_n_0_[3]\,
      I1 => \init_state_r_reg_n_0_[2]\,
      I2 => \init_state_r_reg_n_0_[5]\,
      I3 => \^q\(0),
      I4 => \init_state_r_reg_n_0_[1]\,
      I5 => \init_state_r_reg_n_0_[4]\,
      O => \gen_no_mirror.div_clk_loop[0].phy_address[2]_i_5_n_0\
    );
\gen_no_mirror.div_clk_loop[0].phy_address[2]_i_6\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => init_state_r(6),
      I1 => reg_ctrl_cnt_r_reg(3),
      O => \gen_no_mirror.div_clk_loop[0].phy_address[2]_i_6_n_0\
    );
\gen_no_mirror.div_clk_loop[0].phy_address[3]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8A888A888A88AAAA"
    )
        port map (
      I0 => \gen_no_mirror.div_clk_loop[0].phy_address[6]_i_5_n_0\,
      I1 => \gen_no_mirror.div_clk_loop[0].phy_address[3]_i_2_n_0\,
      I2 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[3]\,
      I3 => \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_3_n_0\,
      I4 => \complex_address_reg_n_0_[3]\,
      I5 => \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_4_n_0\,
      O => address_w(3)
    );
\gen_no_mirror.div_clk_loop[0].phy_address[3]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000EEE222E2"
    )
        port map (
      I0 => p_17_in(3),
      I1 => \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_8_n_0\,
      I2 => \row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[3]\,
      I3 => complex_oclkdelay_calib_done_r1_reg_0,
      I4 => complex_row_cnt_ocal_reg(3),
      I5 => \gen_no_mirror.div_clk_loop[0].phy_address[3]_i_3_n_0\,
      O => \gen_no_mirror.div_clk_loop[0].phy_address[3]_i_2_n_0\
    );
\gen_no_mirror.div_clk_loop[0].phy_address[3]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFEAA"
    )
        port map (
      I0 => \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_9_n_0\,
      I1 => \stg1_wr_rd_cnt[8]_i_5_n_0\,
      I2 => \stg1_wr_rd_cnt[8]_i_4_n_0\,
      I3 => complex_oclkdelay_calib_done_r1_reg_0,
      I4 => \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_10_n_0\,
      I5 => \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_11_n_0\,
      O => \gen_no_mirror.div_clk_loop[0].phy_address[3]_i_3_n_0\
    );
\gen_no_mirror.div_clk_loop[0].phy_address[4]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"20AA2020AAAAAAAA"
    )
        port map (
      I0 => \gen_no_mirror.div_clk_loop[0].phy_address[6]_i_5_n_0\,
      I1 => \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_4_n_0\,
      I2 => \gen_no_mirror.div_clk_loop[0].phy_address[4]_i_2_n_0\,
      I3 => \gen_no_mirror.div_clk_loop[0].phy_address[4]_i_3_n_0\,
      I4 => \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_3_n_0\,
      I5 => \gen_no_mirror.div_clk_loop[0].phy_address[4]_i_4_n_0\,
      O => address_w(4)
    );
\gen_no_mirror.div_clk_loop[0].phy_address[4]_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \complex_address_reg_n_0_[4]\,
      I1 => \complex_address_reg_n_0_[3]\,
      O => \gen_no_mirror.div_clk_loop[0].phy_address[4]_i_2_n_0\
    );
\gen_no_mirror.div_clk_loop[0].phy_address[4]_i_3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[4]\,
      I1 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[3]\,
      O => \gen_no_mirror.div_clk_loop[0].phy_address[4]_i_3_n_0\
    );
\gen_no_mirror.div_clk_loop[0].phy_address[4]_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"EF"
    )
        port map (
      I0 => \gen_no_mirror.div_clk_loop[0].phy_address[6]_i_8_n_0\,
      I1 => complex_oclkdelay_calib_done_r1_reg_0,
      I2 => \row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[4]\,
      O => \gen_no_mirror.div_clk_loop[0].phy_address[4]_i_4_n_0\
    );
\gen_no_mirror.div_clk_loop[0].phy_address[5]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFEAAAAAAAAA"
    )
        port map (
      I0 => \gen_no_mirror.div_clk_loop[0].phy_address[5]_i_2_n_0\,
      I1 => \gen_no_mirror.div_clk_loop[0].phy_address[5]_i_3_n_0\,
      I2 => \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_3_n_0\,
      I3 => \gen_no_mirror.div_clk_loop[0].phy_address[5]_i_4_n_0\,
      I4 => \gen_no_mirror.div_clk_loop[0].phy_address[5]_i_5_n_0\,
      I5 => \gen_no_mirror.div_clk_loop[0].phy_address[6]_i_5_n_0\,
      O => address_w(5)
    );
\gen_no_mirror.div_clk_loop[0].phy_address[5]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"000000000000EA00"
    )
        port map (
      I0 => \gen_no_mirror.div_clk_loop[0].phy_address_reg[10]_0\,
      I1 => cnt_init_mr_r(1),
      I2 => cnt_init_mr_r(0),
      I3 => \gen_no_mirror.div_clk_loop[0].phy_address[10]_i_6_n_0\,
      I4 => init_state_r(6),
      I5 => \gen_no_mirror.div_clk_loop[0].phy_address[10]_i_2_n_0\,
      O => \gen_no_mirror.div_clk_loop[0].phy_address[5]_i_2_n_0\
    );
\gen_no_mirror.div_clk_loop[0].phy_address[5]_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"6A"
    )
        port map (
      I0 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[5]\,
      I1 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[3]\,
      I2 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[4]\,
      O => \gen_no_mirror.div_clk_loop[0].phy_address[5]_i_3_n_0\
    );
\gen_no_mirror.div_clk_loop[0].phy_address[5]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000222F222F0000"
    )
        port map (
      I0 => \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_7_n_0\,
      I1 => \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_6_n_0\,
      I2 => \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_10_n_0\,
      I3 => \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_9_n_0\,
      I4 => \gen_no_mirror.div_clk_loop[0].phy_address[5]_i_6_n_0\,
      I5 => \complex_address_reg_n_0_[5]\,
      O => \gen_no_mirror.div_clk_loop[0].phy_address[5]_i_4_n_0\
    );
\gen_no_mirror.div_clk_loop[0].phy_address[5]_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"02"
    )
        port map (
      I0 => \row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[5]\,
      I1 => \gen_no_mirror.div_clk_loop[0].phy_address[6]_i_8_n_0\,
      I2 => complex_oclkdelay_calib_done_r1_reg_0,
      O => \gen_no_mirror.div_clk_loop[0].phy_address[5]_i_5_n_0\
    );
\gen_no_mirror.div_clk_loop[0].phy_address[5]_i_6\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \complex_address_reg_n_0_[4]\,
      I1 => \complex_address_reg_n_0_[3]\,
      O => \gen_no_mirror.div_clk_loop[0].phy_address[5]_i_6_n_0\
    );
\gen_no_mirror.div_clk_loop[0].phy_address[6]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFF5D0000"
    )
        port map (
      I0 => \gen_no_mirror.div_clk_loop[0].phy_address[6]_i_2_n_0\,
      I1 => \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_3_n_0\,
      I2 => \gen_no_mirror.div_clk_loop[0].phy_address[6]_i_3_n_0\,
      I3 => \gen_no_mirror.div_clk_loop[0].phy_address[6]_i_4_n_0\,
      I4 => \gen_no_mirror.div_clk_loop[0].phy_address[6]_i_5_n_0\,
      I5 => \gen_no_mirror.div_clk_loop[0].phy_address[6]_i_6_n_0\,
      O => address_w(6)
    );
\gen_no_mirror.div_clk_loop[0].phy_address[6]_i_10\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"A8"
    )
        port map (
      I0 => complex_oclkdelay_calib_done_r1_reg_0,
      I1 => \stg1_wr_rd_cnt[8]_i_4_n_0\,
      I2 => \stg1_wr_rd_cnt[8]_i_5_n_0\,
      O => \gen_no_mirror.div_clk_loop[0].phy_address[6]_i_10_n_0\
    );
\gen_no_mirror.div_clk_loop[0].phy_address[6]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFDDD0DDD0FFFF"
    )
        port map (
      I0 => \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_7_n_0\,
      I1 => \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_6_n_0\,
      I2 => \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_10_n_0\,
      I3 => \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_9_n_0\,
      I4 => \gen_no_mirror.div_clk_loop[0].phy_address[6]_i_7_n_0\,
      I5 => \complex_address_reg_n_0_[6]\,
      O => \gen_no_mirror.div_clk_loop[0].phy_address[6]_i_2_n_0\
    );
\gen_no_mirror.div_clk_loop[0].phy_address[6]_i_3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9555"
    )
        port map (
      I0 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[6]\,
      I1 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[5]\,
      I2 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[4]\,
      I3 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[3]\,
      O => \gen_no_mirror.div_clk_loop[0].phy_address[6]_i_3_n_0\
    );
\gen_no_mirror.div_clk_loop[0].phy_address[6]_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"02"
    )
        port map (
      I0 => \row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[6]\,
      I1 => \gen_no_mirror.div_clk_loop[0].phy_address[6]_i_8_n_0\,
      I2 => complex_oclkdelay_calib_done_r1_reg_0,
      O => \gen_no_mirror.div_clk_loop[0].phy_address[6]_i_4_n_0\
    );
\gen_no_mirror.div_clk_loop[0].phy_address[6]_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"8A"
    )
        port map (
      I0 => \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_2_n_0\,
      I1 => init_state_r(6),
      I2 => \gen_no_mirror.div_clk_loop[0].phy_address[10]_i_6_n_0\,
      O => \gen_no_mirror.div_clk_loop[0].phy_address[6]_i_5_n_0\
    );
\gen_no_mirror.div_clk_loop[0].phy_address[6]_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"04"
    )
        port map (
      I0 => init_state_r(6),
      I1 => \gen_rnk[0].mr1_r_reg_n_0_[0][1]\,
      I2 => \gen_no_mirror.div_clk_loop[0].phy_address[6]_i_9_n_0\,
      O => \gen_no_mirror.div_clk_loop[0].phy_address[6]_i_6_n_0\
    );
\gen_no_mirror.div_clk_loop[0].phy_address[6]_i_7\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"80"
    )
        port map (
      I0 => \complex_address_reg_n_0_[3]\,
      I1 => \complex_address_reg_n_0_[4]\,
      I2 => \complex_address_reg_n_0_[5]\,
      O => \gen_no_mirror.div_clk_loop[0].phy_address[6]_i_7_n_0\
    );
\gen_no_mirror.div_clk_loop[0].phy_address[6]_i_8\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFF4FFFFFFFF"
    )
        port map (
      I0 => calib_wrdata_en_i_2_n_0,
      I1 => \^q\(0),
      I2 => \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_10_n_0\,
      I3 => \gen_no_mirror.div_clk_loop[0].phy_address[6]_i_10_n_0\,
      I4 => \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_9_n_0\,
      I5 => \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_8_n_0\,
      O => \gen_no_mirror.div_clk_loop[0].phy_address[6]_i_8_n_0\
    );
\gen_no_mirror.div_clk_loop[0].phy_address[6]_i_9\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"DDDDD9DD77777777"
    )
        port map (
      I0 => \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_6_n_0\,
      I1 => \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_7_n_0\,
      I2 => \gen_no_mirror.div_clk_loop[0].phy_address_reg[10]_0\,
      I3 => cnt_init_mr_r(1),
      I4 => cnt_init_mr_r(0),
      I5 => \gen_no_mirror.div_clk_loop[0].phy_address[10]_i_6_n_0\,
      O => \gen_no_mirror.div_clk_loop[0].phy_address[6]_i_9_n_0\
    );
\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"20AA2020AAAAAAAA"
    )
        port map (
      I0 => \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_2_n_0\,
      I1 => \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_3_n_0\,
      I2 => \row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[7]\,
      I3 => \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_4_n_0\,
      I4 => \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_3_n_0\,
      I5 => \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_5_n_0\,
      O => address_w(7)
    );
\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_10\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"CCCCCCCCCCCFDDDD"
    )
        port map (
      I0 => prbs_rdlvl_start_i_3_n_0,
      I1 => p_0_in0_in,
      I2 => \cnt_init_mr_r[0]_i_2_n_0\,
      I3 => \init_state_r[6]_i_2_n_0\,
      I4 => \^q\(0),
      I5 => \init_state_r_reg_n_0_[1]\,
      O => \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_10_n_0\
    );
\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_11\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000000020"
    )
        port map (
      I0 => \^q\(0),
      I1 => \init_state_r_reg_n_0_[4]\,
      I2 => \init_state_r_reg_n_0_[5]\,
      I3 => init_state_r(6),
      I4 => \init_state_r_reg_n_0_[3]\,
      I5 => \init_state_r_reg_n_0_[2]\,
      O => \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_11_n_0\
    );
\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_12\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"95555555"
    )
        port map (
      I0 => \complex_address_reg_n_0_[7]\,
      I1 => \complex_address_reg_n_0_[6]\,
      I2 => \complex_address_reg_n_0_[3]\,
      I3 => \complex_address_reg_n_0_[4]\,
      I4 => \complex_address_reg_n_0_[5]\,
      O => \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_12_n_0\
    );
\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_13\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000002000000000"
    )
        port map (
      I0 => detect_pi_found_dqs_i_2_n_0,
      I1 => \init_state_r_reg_n_0_[4]\,
      I2 => \init_state_r_reg_n_0_[5]\,
      I3 => init_state_r(6),
      I4 => \init_state_r_reg_n_0_[3]\,
      I5 => \init_state_r_reg_n_0_[2]\,
      O => \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_13_n_0\
    );
\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"AA08"
    )
        port map (
      I0 => \gen_no_mirror.div_clk_loop[0].phy_address[10]_i_5_n_0\,
      I1 => \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_6_n_0\,
      I2 => \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_7_n_0\,
      I3 => init_state_r(6),
      O => \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_2_n_0\
    );
\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFFFFD"
    )
        port map (
      I0 => \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_8_n_0\,
      I1 => \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_9_n_0\,
      I2 => complex_oclkdelay_calib_done_r1_reg_0,
      I3 => \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_10_n_0\,
      I4 => \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_11_n_0\,
      O => \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_3_n_0\
    );
\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"95555555"
    )
        port map (
      I0 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[7]\,
      I1 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[6]\,
      I2 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[3]\,
      I3 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[4]\,
      I4 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[5]\,
      O => \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_4_n_0\
    );
\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000FEAAFEFE"
    )
        port map (
      I0 => \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_12_n_0\,
      I1 => \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_9_n_0\,
      I2 => \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_10_n_0\,
      I3 => \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_6_n_0\,
      I4 => \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_7_n_0\,
      I5 => \gen_no_mirror.div_clk_loop[0].phy_address[10]_i_3_n_0\,
      O => \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_5_n_0\
    );
\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F9FDFFFFDFFFFEFF"
    )
        port map (
      I0 => \init_state_r_reg_n_0_[5]\,
      I1 => \init_state_r_reg_n_0_[4]\,
      I2 => \init_state_r_reg_n_0_[2]\,
      I3 => \init_state_r_reg_n_0_[1]\,
      I4 => \^q\(0),
      I5 => \init_state_r_reg_n_0_[3]\,
      O => \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_6_n_0\
    );
\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_7\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"1000000000001110"
    )
        port map (
      I0 => \init_state_r_reg_n_0_[5]\,
      I1 => \init_state_r_reg_n_0_[2]\,
      I2 => \init_state_r_reg_n_0_[3]\,
      I3 => \init_state_r_reg_n_0_[1]\,
      I4 => \^q\(0),
      I5 => \init_state_r_reg_n_0_[4]\,
      O => \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_7_n_0\
    );
\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_8\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFBFFFDFF"
    )
        port map (
      I0 => \init_state_r_reg_n_0_[4]\,
      I1 => \init_state_r_reg_n_0_[5]\,
      I2 => init_state_r(6),
      I3 => \gen_no_mirror.div_clk_loop[0].phy_address[12]_i_2_n_0\,
      I4 => \init_state_r_reg_n_0_[2]\,
      I5 => \init_state_r_reg_n_0_[3]\,
      O => \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_8_n_0\
    );
\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_9\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"55555545"
    )
        port map (
      I0 => complex_oclkdelay_calib_done_r1_reg_0,
      I1 => \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_13_n_0\,
      I2 => rdlvl_stg1_start_i_2_n_0,
      I3 => \stg1_wr_rd_cnt[8]_i_5_n_0\,
      I4 => \stg1_wr_rd_cnt[8]_i_4_n_0\,
      O => \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_9_n_0\
    );
\gen_no_mirror.div_clk_loop[0].phy_address[8]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FF60FF60FF60FFFF"
    )
        port map (
      I0 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[8]\,
      I1 => \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_2_n_0\,
      I2 => \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_3_n_0\,
      I3 => \gen_no_mirror.div_clk_loop[0].phy_address[8]_i_2_n_0\,
      I4 => \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_4_n_0\,
      I5 => \gen_no_mirror.div_clk_loop[0].phy_address[8]_i_3_n_0\,
      O => address_w(8)
    );
\gen_no_mirror.div_clk_loop[0].phy_address[8]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0080808080808080"
    )
        port map (
      I0 => \cnt_init_mr_r[1]_i_2_n_0\,
      I1 => cnt_init_mr_r(0),
      I2 => cnt_init_mr_r(1),
      I3 => pi_dqs_found_done_r1_reg_0,
      I4 => prbs_rdlvl_start_reg_2,
      I5 => complex_oclkdelay_calib_done_r1_reg_0,
      O => \gen_no_mirror.div_clk_loop[0].phy_address[8]_i_2_n_0\
    );
\gen_no_mirror.div_clk_loop[0].phy_address[8]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"9555555555555555"
    )
        port map (
      I0 => \complex_address_reg_n_0_[8]\,
      I1 => \complex_address_reg_n_0_[7]\,
      I2 => \complex_address_reg_n_0_[5]\,
      I3 => \complex_address_reg_n_0_[4]\,
      I4 => \complex_address_reg_n_0_[3]\,
      I5 => \complex_address_reg_n_0_[6]\,
      O => \gen_no_mirror.div_clk_loop[0].phy_address[8]_i_3_n_0\
    );
\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"6A00FFFF6A006A00"
    )
        port map (
      I0 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[9]\,
      I1 => \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_2_n_0\,
      I2 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[8]\,
      I3 => \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_3_n_0\,
      I4 => \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_4_n_0\,
      I5 => \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_5_n_0\,
      O => address_w(9)
    );
\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_10\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"4F"
    )
        port map (
      I0 => \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_11_n_0\,
      I1 => init_state_r1(3),
      I2 => \stg1_wr_rd_cnt[8]_i_5_n_0\,
      O => \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_10_n_0\
    );
\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_11\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFFF7"
    )
        port map (
      I0 => init_state_r1(2),
      I1 => init_state_r1(1),
      I2 => init_state_r1(5),
      I3 => init_state_r1(0),
      I4 => init_state_r1(4),
      I5 => init_state_r1(6),
      O => \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_11_n_0\
    );
\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_12\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"80000000"
    )
        port map (
      I0 => \complex_address_reg_n_0_[6]\,
      I1 => \complex_address_reg_n_0_[3]\,
      I2 => \complex_address_reg_n_0_[4]\,
      I3 => \complex_address_reg_n_0_[5]\,
      I4 => \complex_address_reg_n_0_[7]\,
      O => \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_12_n_0\
    );
\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_13\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"5504"
    )
        port map (
      I0 => complex_row0_rd_done,
      I1 => init_state_r1(3),
      I2 => \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_11_n_0\,
      I3 => \^one_rank.stg1_wr_done_reg_0\,
      O => \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_13_n_0\
    );
\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_14\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000008000000000"
    )
        port map (
      I0 => \stg1_wr_rd_cnt_reg_n_0_[1]\,
      I1 => \stg1_wr_rd_cnt_reg_n_0_[0]\,
      I2 => \stg1_wr_rd_cnt_reg_n_0_[5]\,
      I3 => \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_17_n_0\,
      I4 => \complex_num_writes[4]_i_15_n_0\,
      I5 => \stg1_wr_rd_cnt_reg_n_0_[6]\,
      O => \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_14_n_0\
    );
\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_15\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000000100"
    )
        port map (
      I0 => complex_sample_cnt_inc_i_3_n_0,
      I1 => \stg1_wr_rd_cnt_reg_n_0_[5]\,
      I2 => prbs_rdlvl_start_reg_2,
      I3 => \stg1_wr_rd_cnt_reg_n_0_[2]\,
      I4 => \stg1_wr_rd_cnt_reg_n_0_[1]\,
      I5 => \stg1_wr_rd_cnt_reg_n_0_[0]\,
      O => \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_15_n_0\
    );
\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_16\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"4444444444444044"
    )
        port map (
      I0 => calib_wrdata_en_i_2_n_0,
      I1 => \^q\(0),
      I2 => wrcal_wr_cnt_reg(3),
      I3 => wrcal_wr_cnt_reg(2),
      I4 => wrcal_wr_cnt_reg(0),
      I5 => wrcal_wr_cnt_reg(1),
      O => \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_16_n_0\
    );
\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_17\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"7F"
    )
        port map (
      I0 => \stg1_wr_rd_cnt_reg_n_0_[4]\,
      I1 => \stg1_wr_rd_cnt_reg_n_0_[2]\,
      I2 => \stg1_wr_rd_cnt_reg_n_0_[3]\,
      O => \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_17_n_0\
    );
\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"80000000"
    )
        port map (
      I0 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[6]\,
      I1 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[3]\,
      I2 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[4]\,
      I3 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[5]\,
      I4 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[7]\,
      O => \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_2_n_0\
    );
\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"F1FFF1F1"
    )
        port map (
      I0 => \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_6_n_0\,
      I1 => \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_7_n_0\,
      I2 => \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_8_n_0\,
      I3 => \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_9_n_0\,
      I4 => \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_10_n_0\,
      O => \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_3_n_0\
    );
\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"BAFF0000BAFFBAFF"
    )
        port map (
      I0 => \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_9_n_0\,
      I1 => \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_11_n_0\,
      I2 => init_state_r1(3),
      I3 => \stg1_wr_rd_cnt[8]_i_5_n_0\,
      I4 => \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_6_n_0\,
      I5 => \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_7_n_0\,
      O => \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_4_n_0\
    );
\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"6A"
    )
        port map (
      I0 => \complex_address_reg_n_0_[9]\,
      I1 => \complex_address_reg_n_0_[8]\,
      I2 => \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_12_n_0\,
      O => \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_5_n_0\
    );
\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFFF5D"
    )
        port map (
      I0 => \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_9_n_0\,
      I1 => \row_cnt_victim_rotate.complex_row_cnt[4]_i_9_n_0\,
      I2 => \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_13_n_0\,
      I3 => \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_14_n_0\,
      I4 => \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_15_n_0\,
      O => \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_6_n_0\
    );
\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_7\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"A8AA"
    )
        port map (
      I0 => \stg1_wr_rd_cnt[8]_i_4_n_0\,
      I1 => init_state_r1(1),
      I2 => init_state_r1(2),
      I3 => prbs_gen_oclk_clk_en_i_11_n_0,
      O => \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_7_n_0\
    );
\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_8\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFEF0000"
    )
        port map (
      I0 => oclk_wr_cnt_reg(1),
      I1 => oclk_wr_cnt_reg(0),
      I2 => oclk_wr_cnt_reg(2),
      I3 => oclk_wr_cnt_reg(3),
      I4 => \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_10_n_0\,
      I5 => \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_16_n_0\,
      O => \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_8_n_0\
    );
\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_9\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FF57FFFFFF57FF57"
    )
        port map (
      I0 => complex_oclkdelay_calib_done_r1_reg_0,
      I1 => \stg1_wr_rd_cnt[8]_i_4_n_0\,
      I2 => \stg1_wr_rd_cnt[8]_i_5_n_0\,
      I3 => \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_14_n_0\,
      I4 => \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_13_n_0\,
      I5 => \complex_row_cnt_ocal[3]_i_5_n_0\,
      O => \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_9_n_0\
    );
\gen_no_mirror.div_clk_loop[0].phy_address_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => '1',
      D => address_w(0),
      Q => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[0]\,
      R => '0'
    );
\gen_no_mirror.div_clk_loop[0].phy_address_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => '1',
      D => address_w(10),
      Q => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[10]\,
      R => '0'
    );
\gen_no_mirror.div_clk_loop[0].phy_address_reg[12]\: unisim.vcomponents.FDRE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => '1',
      D => address_w(12),
      Q => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[12]\,
      R => '0'
    );
\gen_no_mirror.div_clk_loop[0].phy_address_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => '1',
      D => address_w(1),
      Q => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[1]\,
      R => '0'
    );
\gen_no_mirror.div_clk_loop[0].phy_address_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => '1',
      D => address_w(2),
      Q => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[2]\,
      R => '0'
    );
\gen_no_mirror.div_clk_loop[0].phy_address_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => '1',
      D => address_w(3),
      Q => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[3]\,
      R => '0'
    );
\gen_no_mirror.div_clk_loop[0].phy_address_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => '1',
      D => address_w(4),
      Q => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[4]\,
      R => '0'
    );
\gen_no_mirror.div_clk_loop[0].phy_address_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => '1',
      D => address_w(5),
      Q => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[5]\,
      R => '0'
    );
\gen_no_mirror.div_clk_loop[0].phy_address_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => '1',
      D => address_w(6),
      Q => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[6]\,
      R => '0'
    );
\gen_no_mirror.div_clk_loop[0].phy_address_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => '1',
      D => address_w(7),
      Q => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[7]\,
      R => '0'
    );
\gen_no_mirror.div_clk_loop[0].phy_address_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => '1',
      D => address_w(8),
      Q => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[8]\,
      R => '0'
    );
\gen_no_mirror.div_clk_loop[0].phy_address_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => '1',
      D => address_w(9),
      Q => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[9]\,
      R => '0'
    );
\gen_no_mirror.div_clk_loop[0].phy_bank[0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"000000000000AA08"
    )
        port map (
      I0 => \gen_no_mirror.div_clk_loop[0].phy_bank[0]_i_2_n_0\,
      I1 => \init_state_r_reg_n_0_[3]\,
      I2 => \init_state_r_reg_n_0_[2]\,
      I3 => \init_state_r_reg_n_0_[1]\,
      I4 => \init_state_r_reg_n_0_[4]\,
      I5 => init_state_r(6),
      O => bank_w(0)
    );
\gen_no_mirror.div_clk_loop[0].phy_bank[0]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"4007800740078003"
    )
        port map (
      I0 => \init_state_r_reg_n_0_[3]\,
      I1 => \init_state_r_reg_n_0_[1]\,
      I2 => \init_state_r_reg_n_0_[5]\,
      I3 => \^q\(0),
      I4 => \init_state_r_reg_n_0_[2]\,
      I5 => \gen_no_mirror.div_clk_loop[0].phy_bank[0]_i_3_n_0\,
      O => \gen_no_mirror.div_clk_loop[0].phy_bank[0]_i_2_n_0\
    );
\gen_no_mirror.div_clk_loop[0].phy_bank[0]_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"06666666"
    )
        port map (
      I0 => cnt_init_mr_r(1),
      I1 => cnt_init_mr_r(0),
      I2 => complex_oclkdelay_calib_done_r1_reg_0,
      I3 => prbs_rdlvl_start_reg_2,
      I4 => pi_dqs_found_done_r1_reg_0,
      O => \gen_no_mirror.div_clk_loop[0].phy_bank[0]_i_3_n_0\
    );
\gen_no_mirror.div_clk_loop[0].phy_bank[1]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0020"
    )
        port map (
      I0 => \gen_no_mirror.div_clk_loop[0].phy_bank[1]_i_2_n_0\,
      I1 => \init_state_r_reg_n_0_[4]\,
      I2 => \init_state_r_reg_n_0_[1]\,
      I3 => init_state_r(6),
      O => bank_w(1)
    );
\gen_no_mirror.div_clk_loop[0].phy_bank[1]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0980098009800981"
    )
        port map (
      I0 => \^q\(0),
      I1 => \init_state_r_reg_n_0_[5]\,
      I2 => \init_state_r_reg_n_0_[2]\,
      I3 => \init_state_r_reg_n_0_[3]\,
      I4 => \gen_no_mirror.div_clk_loop[0].phy_address_reg[10]_0\,
      I5 => cnt_init_mr_r(1),
      O => \gen_no_mirror.div_clk_loop[0].phy_bank[1]_i_2_n_0\
    );
\gen_no_mirror.div_clk_loop[0].phy_bank[2]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0800"
    )
        port map (
      I0 => reg_ctrl_cnt_r,
      I1 => reg_ctrl_cnt_r_reg(2),
      I2 => reg_ctrl_cnt_r_reg(3),
      I3 => reg_ctrl_cnt_r_reg(1),
      O => bank_w(2)
    );
\gen_no_mirror.div_clk_loop[0].phy_bank_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => '1',
      D => bank_w(0),
      Q => phy_bank(9),
      R => '0'
    );
\gen_no_mirror.div_clk_loop[0].phy_bank_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => '1',
      D => bank_w(1),
      Q => phy_bank(10),
      R => '0'
    );
\gen_no_mirror.div_clk_loop[0].phy_bank_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => '1',
      D => bank_w(2),
      Q => phy_bank(11),
      R => '0'
    );
\gen_reset_obuf.u_reset_obuf_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => phy_ctl_wr_i1_reg,
      I1 => phy_reset_n,
      O => mux_reset_n
    );
\gen_rnk[0].mr1_r_reg[0][1]\: unisim.vcomponents.FDRE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => '1',
      D => '1',
      Q => \gen_rnk[0].mr1_r_reg_n_0_[0][1]\,
      R => \en_cnt_div4.enable_wrlvl_cnt_reg[2]_0\
    );
init_calib_complete_reg: unisim.vcomponents.FDRE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => '1',
      D => init_complete_r2,
      Q => calib_complete,
      R => \en_cnt_div4.enable_wrlvl_cnt_reg[2]_0\
    );
init_complete_r1_reg: unisim.vcomponents.FDRE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => '1',
      D => init_complete_r_reg_n_0,
      Q => init_complete_r1,
      R => \en_cnt_div4.enable_wrlvl_cnt_reg[2]_0\
    );
init_complete_r1_timing_reg: unisim.vcomponents.FDRE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => '1',
      D => init_complete_r_timing,
      Q => init_complete_r1_timing,
      R => \en_cnt_div4.enable_wrlvl_cnt_reg[2]_0\
    );
init_complete_r2_reg: unisim.vcomponents.FDRE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => '1',
      D => init_complete_r1,
      Q => init_complete_r2,
      R => \victim_sel_reg[0]_0\(0)
    );
init_complete_r_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFF00000020"
    )
        port map (
      I0 => detect_pi_found_dqs_i_2_n_0,
      I1 => \wrcal_reads[7]_i_4_n_0\,
      I2 => \init_state_r_reg_n_0_[4]\,
      I3 => init_state_r(6),
      I4 => \init_state_r_reg_n_0_[5]\,
      I5 => init_complete_r_reg_n_0,
      O => init_complete_r_i_1_n_0
    );
init_complete_r_reg: unisim.vcomponents.FDRE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => '1',
      D => init_complete_r_i_1_n_0,
      Q => init_complete_r_reg_n_0,
      R => \victim_sel_reg[0]_0\(0)
    );
init_complete_r_timing_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFF00000020"
    )
        port map (
      I0 => detect_pi_found_dqs_i_2_n_0,
      I1 => \wrcal_reads[7]_i_4_n_0\,
      I2 => \init_state_r_reg_n_0_[4]\,
      I3 => init_state_r(6),
      I4 => \init_state_r_reg_n_0_[5]\,
      I5 => init_complete_r_timing,
      O => init_complete_r_timing_i_1_n_0
    );
init_complete_r_timing_reg: unisim.vcomponents.FDRE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => '1',
      D => init_complete_r_timing_i_1_n_0,
      Q => init_complete_r_timing,
      R => \victim_sel_reg[0]_0\(0)
    );
\init_state_r1_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => '1',
      D => \^q\(0),
      Q => init_state_r1(0),
      R => \victim_sel_reg[0]_0\(0)
    );
\init_state_r1_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => '1',
      D => \init_state_r_reg_n_0_[1]\,
      Q => init_state_r1(1),
      R => \victim_sel_reg[0]_0\(0)
    );
\init_state_r1_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => '1',
      D => \init_state_r_reg_n_0_[2]\,
      Q => init_state_r1(2),
      R => \victim_sel_reg[0]_0\(0)
    );
\init_state_r1_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => '1',
      D => \init_state_r_reg_n_0_[3]\,
      Q => init_state_r1(3),
      R => \victim_sel_reg[0]_0\(0)
    );
\init_state_r1_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => '1',
      D => \init_state_r_reg_n_0_[4]\,
      Q => init_state_r1(4),
      R => \victim_sel_reg[0]_0\(0)
    );
\init_state_r1_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => '1',
      D => \init_state_r_reg_n_0_[5]\,
      Q => init_state_r1(5),
      R => \victim_sel_reg[0]_0\(0)
    );
\init_state_r1_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => '1',
      D => init_state_r(6),
      Q => init_state_r1(6),
      R => \victim_sel_reg[0]_0\(0)
    );
\init_state_r[0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAFEAAFEFFFFAAFE"
    )
        port map (
      I0 => \init_state_r[0]_i_2_n_0\,
      I1 => \init_state_r[0]_i_3_n_0\,
      I2 => \init_state_r[0]_i_4_n_0\,
      I3 => \init_state_r[0]_i_5_n_0\,
      I4 => \init_state_r[0]_i_6_n_0\,
      I5 => \init_state_r[0]_i_7_n_0\,
      O => \init_state_r[0]_i_1_n_0\
    );
\init_state_r[0]_i_10\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0FFF0FF0BB00BB00"
    )
        port map (
      I0 => num_reads(1),
      I1 => num_reads(0),
      I2 => cnt_cmd_done_r,
      I3 => \^q\(0),
      I4 => \init_state_r[0]_i_4_1\,
      I5 => \init_state_r_reg_n_0_[1]\,
      O => \init_state_r[0]_i_10_n_0\
    );
\init_state_r[0]_i_11\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000001101"
    )
        port map (
      I0 => \^q\(0),
      I1 => rdlvl_stg1_rank_done,
      I2 => prbs_rdlvl_start_reg_2,
      I3 => rdlvl_stg1_done_r1,
      I4 => prbs_rdlvl_done_pulse0,
      I5 => \^prech_req_posedge_r_reg_0\,
      O => \init_state_r[0]_i_11_n_0\
    );
\init_state_r[0]_i_12\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFF55151515"
    )
        port map (
      I0 => \init_state_r[4]_i_4_n_0\,
      I1 => \^q\(0),
      I2 => cnt_cmd_done_r,
      I3 => \^wrlvl_done_r1\,
      I4 => \init_state_r_reg_n_0_[1]\,
      I5 => \init_state_r[0]_i_25_n_0\,
      O => \init_state_r[0]_i_12_n_0\
    );
\init_state_r[0]_i_13\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0455155504440444"
    )
        port map (
      I0 => \cnt_init_mr_r[0]_i_2_n_0\,
      I1 => \init_state_r_reg_n_0_[1]\,
      I2 => cnt_cmd_done_r,
      I3 => \^q\(0),
      I4 => cnt_txpr_done_r,
      I5 => \init_state_r[0]_i_26_n_0\,
      O => \init_state_r[0]_i_13_n_0\
    );
\init_state_r[0]_i_14\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8A8AA000AA8AA000"
    )
        port map (
      I0 => \init_state_r[0]_i_27_n_0\,
      I1 => reset_rd_addr_r1,
      I2 => \^q\(0),
      I3 => cnt_cmd_done_r,
      I4 => \init_state_r_reg_n_0_[1]\,
      I5 => rdlvl_stg1_done_r1,
      O => \init_state_r[0]_i_14_n_0\
    );
\init_state_r[0]_i_15\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FF7FFF7FFF7F7F7F"
    )
        port map (
      I0 => \init_state_r_reg_n_0_[3]\,
      I1 => \init_state_r_reg_n_0_[2]\,
      I2 => detect_pi_found_dqs_i_2_n_0,
      I3 => \init_state_r[2]_i_8_n_0\,
      I4 => rdlvl_stg1_done_r1,
      I5 => complex_sample_cnt_inc_i_2_n_0,
      O => \init_state_r[0]_i_15_n_0\
    );
\init_state_r[0]_i_16\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FF450055FF45FF55"
    )
        port map (
      I0 => \init_state_r[6]_i_11_n_0\,
      I1 => \init_state_r[5]_i_13_n_0\,
      I2 => complex_sample_cnt_inc_i_2_n_0,
      I3 => \init_state_r_reg_n_0_[1]\,
      I4 => \^q\(0),
      I5 => prbs_rdlvl_done_pulse0,
      O => \init_state_r[0]_i_16_n_0\
    );
\init_state_r[0]_i_17\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000F355FF55FF55"
    )
        port map (
      I0 => \^q\(0),
      I1 => complex_row1_wr_done,
      I2 => \^one_rank.stg1_wr_done_reg_0\,
      I3 => \init_state_r[5]_i_13_n_0\,
      I4 => \init_state_r[3]_i_21_n_0\,
      I5 => \init_state_r[0]_i_28_n_0\,
      O => \init_state_r[0]_i_17_n_0\
    );
\init_state_r[0]_i_18\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFF04FF04FF04FF"
    )
        port map (
      I0 => \cnt_init_mr_r[0]_i_2_n_0\,
      I1 => \init_state_r[0]_i_29_n_0\,
      I2 => \init_state_r[2]_i_29_n_0\,
      I3 => \init_state_r_reg_n_0_[4]\,
      I4 => \init_state_r[0]_i_30_n_0\,
      I5 => complex_oclkdelay_calib_done_r1_reg_0,
      O => \init_state_r[0]_i_18_n_0\
    );
\init_state_r[0]_i_19\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFF00F7"
    )
        port map (
      I0 => complex_sample_cnt_inc_i_2_n_0,
      I1 => \^q\(0),
      I2 => \init_state_r[5]_i_13_n_0\,
      I3 => \init_state_r[6]_i_15_n_0\,
      I4 => rdlvl_stg1_start_int_i_2_n_0,
      I5 => \init_state_r_reg_n_0_[1]\,
      O => \init_state_r[0]_i_19_n_0\
    );
\init_state_r[0]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"F0F000D0"
    )
        port map (
      I0 => \init_state_r_reg_n_0_[1]\,
      I1 => \ocal_act_wait_cnt[3]_i_3_n_0\,
      I2 => init_state_r(6),
      I3 => \init_state_r_reg_n_0_[2]\,
      I4 => \^q\(0),
      O => \init_state_r[0]_i_2_n_0\
    );
\init_state_r[0]_i_20\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFBB30FFFF0000"
    )
        port map (
      I0 => \init_state_r[5]_i_35_n_0\,
      I1 => \^q\(0),
      I2 => cnt_cmd_done_r,
      I3 => \init_state_r_reg_n_0_[2]\,
      I4 => \init_state_r_reg_n_0_[4]\,
      I5 => \init_state_r_reg_n_0_[3]\,
      O => \init_state_r[0]_i_20_n_0\
    );
\init_state_r[0]_i_21\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000747400FF"
    )
        port map (
      I0 => p_17_in(3),
      I1 => \^q\(0),
      I2 => cnt_cmd_done_r,
      I3 => \init_state_r[0]_i_31_n_0\,
      I4 => \init_state_r_reg_n_0_[1]\,
      I5 => \cnt_init_mr_r[0]_i_2_n_0\,
      O => \init_state_r[0]_i_21_n_0\
    );
\init_state_r[0]_i_22\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0F00020F0F0F020F"
    )
        port map (
      I0 => \wrcal_reads_reg_n_0_[0]\,
      I1 => \wrcal_reads[7]_i_6_n_0\,
      I2 => \init_state_r[2]_i_45_n_0\,
      I3 => \^q\(0),
      I4 => \init_state_r_reg_n_0_[1]\,
      I5 => init_next_state1100_out,
      O => \init_state_r[0]_i_22_n_0\
    );
\init_state_r[0]_i_23\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFEF"
    )
        port map (
      I0 => reg_ctrl_cnt_r_reg(0),
      I1 => reg_ctrl_cnt_r_reg(1),
      I2 => reg_ctrl_cnt_r_reg(3),
      I3 => reg_ctrl_cnt_r_reg(2),
      O => \init_state_r[0]_i_23_n_0\
    );
\init_state_r[0]_i_25\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAAABBFFAFFF"
    )
        port map (
      I0 => \init_state_r_reg_n_0_[4]\,
      I1 => wrlvl_rank_done_r7,
      I2 => cnt_dllk_zqinit_done_r,
      I3 => \^q\(0),
      I4 => \init_state_r_reg_n_0_[1]\,
      I5 => \wrcal_reads[7]_i_4_n_0\,
      O => \init_state_r[0]_i_25_n_0\
    );
\init_state_r[0]_i_26\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"EAAA"
    )
        port map (
      I0 => \^q\(0),
      I1 => \calib_seq_reg[0]_0\(0),
      I2 => cnt_pwron_cke_done_r,
      I3 => ck_addr_cmd_delay_done,
      O => \init_state_r[0]_i_26_n_0\
    );
\init_state_r[0]_i_27\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"BBFBFFFFBBFBBBFB"
    )
        port map (
      I0 => \init_state_r_reg_n_0_[1]\,
      I1 => \^pi_calib_done\,
      I2 => pi_dqs_found_done_r1_reg_0,
      I3 => ddr3_lm_done_r_reg_0,
      I4 => \init_state_r[0]_i_32_n_0\,
      I5 => \init_state_r[0]_i_14_0\,
      O => \init_state_r[0]_i_27_n_0\
    );
\init_state_r[0]_i_28\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFC8F8FFFF"
    )
        port map (
      I0 => prbs_last_byte_done_r,
      I1 => \init_state_r[5]_i_13_n_0\,
      I2 => complex_oclkdelay_calib_done_r1_reg_0,
      I3 => prbs_rdlvl_done_r1,
      I4 => \^q\(0),
      I5 => \init_state_r_reg_n_0_[1]\,
      O => \init_state_r[0]_i_28_n_0\
    );
\init_state_r[0]_i_29\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => \init_state_r_reg_n_0_[1]\,
      I1 => cnt_cmd_done_r,
      O => \init_state_r[0]_i_29_n_0\
    );
\init_state_r[0]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0100000011101010"
    )
        port map (
      I0 => \init_state_r[4]_i_4_n_0\,
      I1 => \^q\(0),
      I2 => \init_state_r_reg_n_0_[1]\,
      I3 => ddr2_pre_flag_r_reg_n_0,
      I4 => cnt_cmd_done_r,
      I5 => \init_state_r[4]_i_10_n_0\,
      O => \init_state_r[0]_i_3_n_0\
    );
\init_state_r[0]_i_30\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4000"
    )
        port map (
      I0 => \^q\(0),
      I1 => \init_state_r_reg_n_0_[1]\,
      I2 => \init_state_r_reg_n_0_[2]\,
      I3 => \init_state_r_reg_n_0_[3]\,
      O => \init_state_r[0]_i_30_n_0\
    );
\init_state_r[0]_i_31\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAAAAAAABABB"
    )
        port map (
      I0 => \init_state_r[5]_i_30_n_0\,
      I1 => \^q\(0),
      I2 => wrcal_prech_req,
      I3 => cnt_cmd_done_r,
      I4 => ddr3_lm_done_r_reg_0,
      I5 => \^prech_req_posedge_r_reg_0\,
      O => \init_state_r[0]_i_31_n_0\
    );
\init_state_r[0]_i_32\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFEEFFEEFFEEAA08"
    )
        port map (
      I0 => \^one_rank.stg1_wr_done_reg_0\,
      I1 => complex_oclkdelay_calib_done_r1_reg_0,
      I2 => rdlvl_stg1_start_int,
      I3 => prbs_last_byte_done,
      I4 => prbs_rdlvl_start_reg_2,
      I5 => rdlvl_last_byte_done,
      O => \init_state_r[0]_i_32_n_0\
    );
\init_state_r[0]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"EFEEEFEFEFEEEFEE"
    )
        port map (
      I0 => \init_state_r[0]_i_8_n_0\,
      I1 => \init_state_r[0]_i_9_n_0\,
      I2 => \cnt_init_mr_r[0]_i_2_n_0\,
      I3 => \init_state_r[0]_i_10_n_0\,
      I4 => \init_state_r[0]_i_11_n_0\,
      I5 => \wrcal_reads[7]_i_5_n_0\,
      O => \init_state_r[0]_i_4_n_0\
    );
\init_state_r[0]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"ABABABAAAAAAAAAA"
    )
        port map (
      I0 => \init_state_r[3]_i_6_n_0\,
      I1 => \init_state_r[0]_i_12_n_0\,
      I2 => \init_state_r[0]_i_13_n_0\,
      I3 => \init_state_r[0]_i_14_n_0\,
      I4 => rdlvl_stg1_start_int_i_2_n_0,
      I5 => \init_state_r[0]_i_15_n_0\,
      O => \init_state_r[0]_i_5_n_0\
    );
\init_state_r[0]_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFF0350FFFFFFFF"
    )
        port map (
      I0 => \init_state_r[0]_i_16_n_0\,
      I1 => \init_state_r[0]_i_17_n_0\,
      I2 => \init_state_r_reg_n_0_[3]\,
      I3 => \init_state_r_reg_n_0_[2]\,
      I4 => \init_state_r[0]_i_18_n_0\,
      I5 => \init_state_r[0]_i_19_n_0\,
      O => \init_state_r[0]_i_6_n_0\
    );
\init_state_r[0]_i_7\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"DDDFDDDFDDDFDDDD"
    )
        port map (
      I0 => \init_state_r_reg_n_0_[5]\,
      I1 => init_state_r(6),
      I2 => \init_state_r[0]_i_20_n_0\,
      I3 => \init_state_r[0]_i_21_n_0\,
      I4 => \wrcal_reads[7]_i_4_n_0\,
      I5 => \init_state_r[0]_i_22_n_0\,
      O => \init_state_r[0]_i_7_n_0\
    );
\init_state_r[0]_i_8\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0001111111111111"
    )
        port map (
      I0 => \wrcal_reads[7]_i_4_n_0\,
      I1 => \init_state_r_reg_n_0_[1]\,
      I2 => \init_state_r[0]_i_4_0\,
      I3 => \init_state_r[4]_i_24_n_0\,
      I4 => \^q\(0),
      I5 => cnt_cmd_done_r,
      O => \init_state_r[0]_i_8_n_0\
    );
\init_state_r[0]_i_9\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"555F555D555D555D"
    )
        port map (
      I0 => \init_state_r_reg_n_0_[4]\,
      I1 => \init_state_r_reg_n_0_[1]\,
      I2 => rdlvl_stg1_start_int_i_2_n_0,
      I3 => \^q\(0),
      I4 => cnt_cmd_done_r,
      I5 => \init_state_r[0]_i_23_n_0\,
      O => \init_state_r[0]_i_9_n_0\
    );
\init_state_r[1]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAFEAAFEAAFEFFFF"
    )
        port map (
      I0 => \init_state_r[1]_i_2_n_0\,
      I1 => \init_state_r[1]_i_3_n_0\,
      I2 => \init_state_r[1]_i_4_n_0\,
      I3 => \init_state_r[1]_i_5_n_0\,
      I4 => \init_state_r[1]_i_6_n_0\,
      I5 => \init_state_r[1]_i_7_n_0\,
      O => \init_state_r[1]_i_1_n_0\
    );
\init_state_r[1]_i_10\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000EEFEFEFE"
    )
        port map (
      I0 => \init_state_r[2]_i_42_n_0\,
      I1 => \init_state_r[1]_i_22_n_0\,
      I2 => \init_state_r_reg_n_0_[1]\,
      I3 => \init_state_r[2]_i_43_n_0\,
      I4 => \init_state_r[5]_i_27_n_0\,
      I5 => \init_state_r[1]_i_23_n_0\,
      O => \init_state_r[1]_i_10_n_0\
    );
\init_state_r[1]_i_11\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AAAAAAAB"
    )
        port map (
      I0 => \init_state_r_reg_n_0_[4]\,
      I1 => \init_state_r[5]_i_32_n_0\,
      I2 => \init_state_r_reg_n_0_[1]\,
      I3 => \init_state_r_reg_n_0_[2]\,
      I4 => \init_state_r_reg_n_0_[3]\,
      O => \init_state_r[1]_i_11_n_0\
    );
\init_state_r[1]_i_12\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAA8AAAAAAAAAA"
    )
        port map (
      I0 => \init_state_r[1]_i_24_n_0\,
      I1 => wrcal_wr_cnt_reg(3),
      I2 => wrcal_wr_cnt_reg(2),
      I3 => wrcal_wr_cnt_reg(0),
      I4 => wrcal_wr_cnt_reg(1),
      I5 => \gen_no_mirror.div_clk_loop[0].phy_address[12]_i_2_n_0\,
      O => \init_state_r[1]_i_12_n_0\
    );
\init_state_r[1]_i_13\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"C0C3FAFF00C3FAFF"
    )
        port map (
      I0 => \init_state_r[1]_i_25_n_0\,
      I1 => \init_state_r_reg_n_0_[1]\,
      I2 => \^q\(0),
      I3 => \init_state_r_reg_n_0_[2]\,
      I4 => \init_state_r_reg_n_0_[3]\,
      I5 => \init_state_r[3]_i_20_n_0\,
      O => \init_state_r[1]_i_13_n_0\
    );
\init_state_r[1]_i_14\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000055555DDD"
    )
        port map (
      I0 => detect_pi_found_dqs_i_2_n_0,
      I1 => \init_state_r[1]_i_26_n_0\,
      I2 => \init_state_r[2]_i_38_n_0\,
      I3 => \init_state_r[2]_i_39_n_0\,
      I4 => \init_state_r[4]_i_22_n_0\,
      I5 => \init_state_r[1]_i_27_n_0\,
      O => \init_state_r[1]_i_14_n_0\
    );
\init_state_r[1]_i_15\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FABFFAFFFABFFABF"
    )
        port map (
      I0 => \wrcal_reads[7]_i_4_n_0\,
      I1 => cnt_cmd_done_r,
      I2 => \^q\(0),
      I3 => \init_state_r_reg_n_0_[1]\,
      I4 => \init_state_r[0]_i_4_0\,
      I5 => \init_state_r[2]_i_4_0\,
      O => \init_state_r[1]_i_15_n_0\
    );
\init_state_r[1]_i_16\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFEF000000"
    )
        port map (
      I0 => \^prech_req_posedge_r_reg_0\,
      I1 => prbs_rdlvl_done_pulse0,
      I2 => \init_state_r[1]_i_6_0\,
      I3 => \init_state_r[6]_i_24_n_0\,
      I4 => \init_state_r[1]_i_29_n_0\,
      I5 => \init_state_r[1]_i_30_n_0\,
      O => \init_state_r[1]_i_16_n_0\
    );
\init_state_r[1]_i_17\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"5554000055555555"
    )
        port map (
      I0 => \cnt_init_mr_r[0]_i_2_n_0\,
      I1 => pi_dqs_found_done_r1_reg_0,
      I2 => \^prech_req_posedge_r_reg_0\,
      I3 => pi_dqs_found_rank_done,
      I4 => detect_pi_found_dqs_i_2_n_0,
      I5 => \init_state_r[1]_i_31_n_0\,
      O => \init_state_r[1]_i_17_n_0\
    );
\init_state_r[1]_i_18\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8000000088888888"
    )
        port map (
      I0 => cnt_cmd_done_r,
      I1 => \gen_no_mirror.div_clk_loop[0].phy_address[12]_i_2_n_0\,
      I2 => \init_state_r[1]_i_32_n_0\,
      I3 => \init_state_r[0]_i_14_0\,
      I4 => ddr3_lm_done_r_reg_0,
      I5 => \^pi_calib_done\,
      O => \init_state_r[1]_i_18_n_0\
    );
\init_state_r[1]_i_19\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AAAA88A0"
    )
        port map (
      I0 => \init_state_r[5]_i_46_n_0\,
      I1 => rdlvl_stg1_done_r1,
      I2 => \init_state_r_reg_n_0_[1]\,
      I3 => cnt_cmd_done_r,
      I4 => reset_rd_addr_r1,
      O => \init_state_r[1]_i_19_n_0\
    );
\init_state_r[1]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"88882000AAAAAAAA"
    )
        port map (
      I0 => init_state_r(6),
      I1 => \init_state_r_reg_n_0_[2]\,
      I2 => \^prech_req_posedge_r_reg_0\,
      I3 => \^q\(0),
      I4 => \init_state_r_reg_n_0_[1]\,
      I5 => \init_state_r[5]_i_28_n_0\,
      O => \init_state_r[1]_i_2_n_0\
    );
\init_state_r[1]_i_20\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFF0040"
    )
        port map (
      I0 => \wrcal_reads[7]_i_4_n_0\,
      I1 => \gen_no_mirror.div_clk_loop[0].phy_address[12]_i_2_n_0\,
      I2 => cnt_dllk_zqinit_done_r,
      I3 => mem_init_done_r,
      I4 => \init_state_r_reg_n_0_[4]\,
      I5 => \init_state_r[1]_i_34_n_0\,
      O => \init_state_r[1]_i_20_n_0\
    );
\init_state_r[1]_i_21\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0555404055554040"
    )
        port map (
      I0 => \cnt_init_mr_r[0]_i_2_n_0\,
      I1 => cnt_txpr_done_r,
      I2 => \^q\(0),
      I3 => cnt_cmd_done_r,
      I4 => \init_state_r_reg_n_0_[1]\,
      I5 => \init_state_r[2]_i_31_n_0\,
      O => \init_state_r[1]_i_21_n_0\
    );
\init_state_r[1]_i_22\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000800000000000"
    )
        port map (
      I0 => complex_wait_cnt_reg(3),
      I1 => complex_wait_cnt_reg(2),
      I2 => complex_wait_cnt_reg(1),
      I3 => complex_wait_cnt_reg(0),
      I4 => \init_state_r_reg_n_0_[1]\,
      I5 => \^q\(0),
      O => \init_state_r[1]_i_22_n_0\
    );
\init_state_r[1]_i_23\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"BAABAAAB"
    )
        port map (
      I0 => \init_state_r_reg_n_0_[3]\,
      I1 => \init_state_r_reg_n_0_[2]\,
      I2 => \^q\(0),
      I3 => \init_state_r_reg_n_0_[1]\,
      I4 => cnt_cmd_done_r,
      O => \init_state_r[1]_i_23_n_0\
    );
\init_state_r[1]_i_24\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"8F"
    )
        port map (
      I0 => p_17_in(3),
      I1 => \^q\(0),
      I2 => \init_state_r_reg_n_0_[1]\,
      O => \init_state_r[1]_i_24_n_0\
    );
\init_state_r[1]_i_25\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"000000000001FF01"
    )
        port map (
      I0 => wrlvl_byte_redo,
      I1 => \^prech_req_posedge_r_reg_0\,
      I2 => ddr3_lm_done_r_reg_0,
      I3 => wrcal_resume_r,
      I4 => wrcal_final_chk,
      I5 => \init_state_r_reg_n_0_[1]\,
      O => \init_state_r[1]_i_25_n_0\
    );
\init_state_r[1]_i_26\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0FFF0FFFFFFF8FF"
    )
        port map (
      I0 => prbs_last_byte_done_r,
      I1 => mem_init_done_r,
      I2 => ddr3_lm_done_r_reg_0,
      I3 => pi_dqs_found_done_r1_reg_0,
      I4 => prbs_rdlvl_start_reg_2,
      I5 => complex_oclkdelay_calib_done_r1_reg_0,
      O => \init_state_r[1]_i_26_n_0\
    );
\init_state_r[1]_i_27\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2232"
    )
        port map (
      I0 => \^q\(0),
      I1 => \init_state_r_reg_n_0_[1]\,
      I2 => cnt_cmd_done_r,
      I3 => ddr2_pre_flag_r_reg_n_0,
      O => \init_state_r[1]_i_27_n_0\
    );
\init_state_r[1]_i_29\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"4F"
    )
        port map (
      I0 => num_reads(1),
      I1 => num_reads(0),
      I2 => \^q\(0),
      O => \init_state_r[1]_i_29_n_0\
    );
\init_state_r[1]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFF00F1FFFF"
    )
        port map (
      I0 => \init_state_r[1]_i_8_n_0\,
      I1 => complex_sample_cnt_inc_i_2_n_0,
      I2 => \init_state_r[1]_i_9_n_0\,
      I3 => \init_state_r[4]_i_4_n_0\,
      I4 => \init_state_r_reg_n_0_[4]\,
      I5 => \init_state_r[1]_i_10_n_0\,
      O => \init_state_r[1]_i_3_n_0\
    );
\init_state_r[1]_i_30\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"3E000000FFFFFFFF"
    )
        port map (
      I0 => cnt_cmd_done_r,
      I1 => \^q\(0),
      I2 => \init_state_r_reg_n_0_[1]\,
      I3 => \init_state_r_reg_n_0_[2]\,
      I4 => \init_state_r_reg_n_0_[3]\,
      I5 => \init_state_r_reg_n_0_[4]\,
      O => \init_state_r[1]_i_30_n_0\
    );
\init_state_r[1]_i_31\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => cnt_cmd_done_r,
      I1 => \init_state_r_reg_n_0_[1]\,
      O => \init_state_r[1]_i_31_n_0\
    );
\init_state_r[1]_i_32\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"CCDDFFFF051D051D"
    )
        port map (
      I0 => \^one_rank.stg1_wr_done_reg_0\,
      I1 => prbs_rdlvl_start_reg_2,
      I2 => prbs_last_byte_done,
      I3 => rdlvl_last_byte_done,
      I4 => rdlvl_stg1_start_int,
      I5 => complex_oclkdelay_calib_done_r1_reg_0,
      O => \init_state_r[1]_i_32_n_0\
    );
\init_state_r[1]_i_34\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000FCCC44CC0000"
    )
        port map (
      I0 => wrlvl_rank_done_r7,
      I1 => \init_state_r_reg_n_0_[1]\,
      I2 => cnt_cmd_done_r,
      I3 => \^q\(0),
      I4 => \init_state_r_reg_n_0_[2]\,
      I5 => \init_state_r_reg_n_0_[3]\,
      O => \init_state_r[1]_i_34_n_0\
    );
\init_state_r[1]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8080888088888888"
    )
        port map (
      I0 => \init_state_r_reg_n_0_[2]\,
      I1 => \init_state_r_reg_n_0_[3]\,
      I2 => \init_state_r[5]_i_13_n_0\,
      I3 => \^q\(0),
      I4 => complex_sample_cnt_inc_i_2_n_0,
      I5 => \init_state_r[5]_i_12_n_0\,
      O => \init_state_r[1]_i_4_n_0\
    );
\init_state_r[1]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"DFDFDFDDDDDDDDDD"
    )
        port map (
      I0 => \init_state_r_reg_n_0_[5]\,
      I1 => init_state_r(6),
      I2 => \init_state_r[1]_i_11_n_0\,
      I3 => \init_state_r[1]_i_12_n_0\,
      I4 => \cnt_init_mr_r[0]_i_2_n_0\,
      I5 => \init_state_r[1]_i_13_n_0\,
      O => \init_state_r[1]_i_5_n_0\
    );
\init_state_r[1]_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAAAAAAAFEAA"
    )
        port map (
      I0 => \init_state_r[3]_i_6_n_0\,
      I1 => \init_state_r[4]_i_4_n_0\,
      I2 => \init_state_r[1]_i_14_n_0\,
      I3 => \init_state_r[1]_i_15_n_0\,
      I4 => \init_state_r[1]_i_16_n_0\,
      I5 => \init_state_r[1]_i_17_n_0\,
      O => \init_state_r[1]_i_6_n_0\
    );
\init_state_r[1]_i_7\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000000000F2"
    )
        port map (
      I0 => \init_state_r[6]_i_20_n_0\,
      I1 => \init_state_r[1]_i_18_n_0\,
      I2 => rdlvl_stg1_start_int_i_2_n_0,
      I3 => \init_state_r[1]_i_19_n_0\,
      I4 => \init_state_r[1]_i_20_n_0\,
      I5 => \init_state_r[1]_i_21_n_0\,
      O => \init_state_r[1]_i_7_n_0\
    );
\init_state_r[1]_i_8\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AAAAAAAB"
    )
        port map (
      I0 => \init_state_r_reg_n_0_[1]\,
      I1 => \init_state_r[6]_i_22_n_0\,
      I2 => complex_row0_rd_done,
      I3 => complex_num_reads_dec(3),
      I4 => complex_num_reads_dec(2),
      O => \init_state_r[1]_i_8_n_0\
    );
\init_state_r[1]_i_9\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0030BABA00FFBABA"
    )
        port map (
      I0 => \^prech_req_posedge_r_reg_0\,
      I1 => prbs_rdlvl_done_r1,
      I2 => complex_oclkdelay_calib_done_r1_reg_0,
      I3 => \^q\(0),
      I4 => \init_state_r_reg_n_0_[1]\,
      I5 => \init_state_r[5]_i_13_n_0\,
      O => \init_state_r[1]_i_9_n_0\
    );
\init_state_r[2]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AEAEAEAEFFAEFFFF"
    )
        port map (
      I0 => \init_state_r[2]_i_2_n_0\,
      I1 => \init_state_r[2]_i_3_n_0\,
      I2 => \init_state_r[2]_i_4_n_0\,
      I3 => \init_state_r[2]_i_5_n_0\,
      I4 => \init_state_r[2]_i_6_n_0\,
      I5 => \init_state_r[2]_i_7_n_0\,
      O => \init_state_r[2]_i_1_n_0\
    );
\init_state_r[2]_i_10\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFF00001FFF"
    )
        port map (
      I0 => \^rdlvl_stg1_start_int_reg_0\,
      I1 => \init_state_r[2]_i_3_0\,
      I2 => \init_state_r[2]_i_29_n_0\,
      I3 => \^pi_calib_done\,
      I4 => \init_state_r_reg_n_0_[1]\,
      I5 => \init_state_r[2]_i_30_n_0\,
      O => \init_state_r[2]_i_10_n_0\
    );
\init_state_r[2]_i_11\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFF8FFF8FFF8FFFF"
    )
        port map (
      I0 => \init_state_r[2]_i_31_n_0\,
      I1 => \init_state_r[2]_i_32_n_0\,
      I2 => \init_state_r_reg_n_0_[4]\,
      I3 => \init_state_r[2]_i_33_n_0\,
      I4 => \wrcal_reads[7]_i_4_n_0\,
      I5 => \init_state_r[2]_i_34_n_0\,
      O => \init_state_r[2]_i_11_n_0\
    );
\init_state_r[2]_i_12\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"67000000FFFFFFFF"
    )
        port map (
      I0 => \^q\(0),
      I1 => \init_state_r_reg_n_0_[1]\,
      I2 => cnt_cmd_done_r,
      I3 => \init_state_r_reg_n_0_[2]\,
      I4 => \init_state_r_reg_n_0_[3]\,
      I5 => \init_state_r_reg_n_0_[4]\,
      O => \init_state_r[2]_i_12_n_0\
    );
\init_state_r[2]_i_13\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"BAAAAAAA"
    )
        port map (
      I0 => \init_state_r_reg_n_0_[3]\,
      I1 => \init_state_r_reg_n_0_[2]\,
      I2 => \init_state_r_reg_n_0_[1]\,
      I3 => \^q\(0),
      I4 => cnt_cmd_done_r,
      O => \init_state_r[2]_i_13_n_0\
    );
\init_state_r[2]_i_14\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"77777777FF7F7777"
    )
        port map (
      I0 => prbs_rdlvl_start_i_2_n_0,
      I1 => \init_state_r_reg_n_0_[2]\,
      I2 => ddr3_lm_done_r,
      I3 => \init_state_r[2]_i_4_0\,
      I4 => \init_state_r[2]_i_29_n_0\,
      I5 => \init_state_r[0]_i_4_0\,
      O => \init_state_r[2]_i_14_n_0\
    );
\init_state_r[2]_i_15\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000FFFFF474"
    )
        port map (
      I0 => \init_state_r[2]_i_36_n_0\,
      I1 => \init_state_r[4]_i_10_0\,
      I2 => \init_state_r[2]_i_38_n_0\,
      I3 => \init_state_r[2]_i_39_n_0\,
      I4 => \init_state_r[2]_i_40_n_0\,
      I5 => \init_state_r[2]_i_41_n_0\,
      O => \init_state_r[2]_i_15_n_0\
    );
\init_state_r[2]_i_16\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"AA2A"
    )
        port map (
      I0 => \init_state_r_reg_n_0_[3]\,
      I1 => \init_state_r_reg_n_0_[1]\,
      I2 => \^q\(0),
      I3 => \init_state_r_reg_n_0_[2]\,
      O => \init_state_r[2]_i_16_n_0\
    );
\init_state_r[2]_i_17\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFF7500FFFFFFFF"
    )
        port map (
      I0 => \init_state_r[5]_i_13_n_0\,
      I1 => prbs_rdlvl_done_r1,
      I2 => complex_oclkdelay_calib_done_r1_reg_0,
      I3 => detect_pi_found_dqs_i_2_n_0,
      I4 => \init_state_r_reg_n_0_[2]\,
      I5 => \init_state_r_reg_n_0_[3]\,
      O => \init_state_r[2]_i_17_n_0\
    );
\init_state_r[2]_i_18\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000FFDFFFDFFFDF"
    )
        port map (
      I0 => \init_state_r[5]_i_48_n_0\,
      I1 => \stg1_wr_rd_cnt_reg_n_0_[1]\,
      I2 => \stg1_wr_rd_cnt_reg_n_0_[0]\,
      I3 => \stg1_wr_rd_cnt_reg_n_0_[2]\,
      I4 => \^q\(0),
      I5 => \init_state_r[5]_i_13_n_0\,
      O => \init_state_r[2]_i_18_n_0\
    );
\init_state_r[2]_i_19\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFF10111010"
    )
        port map (
      I0 => \init_state_r_reg_n_0_[3]\,
      I1 => \init_state_r[2]_i_42_n_0\,
      I2 => \init_state_r[5]_i_41_n_0\,
      I3 => \init_state_r[2]_i_43_n_0\,
      I4 => \init_state_r[5]_i_27_n_0\,
      I5 => \init_state_r[2]_i_44_n_0\,
      O => \init_state_r[2]_i_19_n_0\
    );
\init_state_r[2]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AAAA8000"
    )
        port map (
      I0 => init_state_r(6),
      I1 => complex_pi_incdec_done,
      I2 => \^q\(0),
      I3 => \init_state_r_reg_n_0_[1]\,
      I4 => \init_state_r_reg_n_0_[2]\,
      O => \init_state_r[2]_i_2_n_0\
    );
\init_state_r[2]_i_20\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFDFFFFF00000000"
    )
        port map (
      I0 => \^q\(0),
      I1 => \stg1_wr_rd_cnt_reg_n_0_[2]\,
      I2 => \stg1_wr_rd_cnt_reg_n_0_[0]\,
      I3 => \stg1_wr_rd_cnt_reg_n_0_[1]\,
      I4 => \init_state_r[5]_i_48_n_0\,
      I5 => \init_state_r[5]_i_12_n_0\,
      O => \init_state_r[2]_i_20_n_0\
    );
\init_state_r[2]_i_21\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => \^q\(0),
      I1 => complex_oclkdelay_calib_done_r1_reg_0,
      O => \init_state_r[2]_i_21_n_0\
    );
\init_state_r[2]_i_22\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"EFEEEEEEEEEEEEEE"
    )
        port map (
      I0 => \init_state_r_reg_n_0_[3]\,
      I1 => \init_state_r_reg_n_0_[4]\,
      I2 => \init_state_r_reg_n_0_[2]\,
      I3 => \^q\(0),
      I4 => \init_state_r_reg_n_0_[1]\,
      I5 => p_17_in(3),
      O => \init_state_r[2]_i_22_n_0\
    );
\init_state_r[2]_i_23\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFAAFFFFBAAAFFFF"
    )
        port map (
      I0 => \init_state_r[2]_i_45_n_0\,
      I1 => pi_phase_locked_all_r4,
      I2 => pi_phase_locked_all_r3,
      I3 => \init_state_r_reg_n_0_[1]\,
      I4 => \init_state_r_reg_n_0_[2]\,
      I5 => \^q\(0),
      O => \init_state_r[2]_i_23_n_0\
    );
\init_state_r[2]_i_24\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \init_state_r_reg_n_0_[1]\,
      I1 => \init_state_r_reg_n_0_[2]\,
      O => \init_state_r[2]_i_24_n_0\
    );
\init_state_r[2]_i_25\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0004FFFF"
    )
        port map (
      I0 => oclk_wr_cnt_reg(1),
      I1 => oclk_wr_cnt_reg(0),
      I2 => oclk_wr_cnt_reg(2),
      I3 => oclk_wr_cnt_reg(3),
      I4 => \^q\(0),
      O => \init_state_r[2]_i_25_n_0\
    );
\init_state_r[2]_i_26\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFF5FD5F555"
    )
        port map (
      I0 => \init_state_r_reg_n_0_[3]\,
      I1 => cnt_cmd_done_r,
      I2 => \init_state_r_reg_n_0_[1]\,
      I3 => \^q\(0),
      I4 => \init_state_r_reg_n_0_[2]\,
      I5 => \init_state_r_reg_n_0_[4]\,
      O => \init_state_r[2]_i_26_n_0\
    );
\init_state_r[2]_i_27\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"DDDF0003DCDC0000"
    )
        port map (
      I0 => rdlvl_stg1_start_int,
      I1 => prbs_rdlvl_start_reg_2,
      I2 => rdlvl_last_byte_done,
      I3 => prbs_last_byte_done,
      I4 => complex_oclkdelay_calib_done_r1_reg_0,
      I5 => \^one_rank.stg1_wr_done_reg_0\,
      O => \^rdlvl_stg1_start_int_reg_0\
    );
\init_state_r[2]_i_29\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^q\(0),
      I1 => cnt_cmd_done_r,
      O => \init_state_r[2]_i_29_n_0\
    );
\init_state_r[2]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFF0000FF0D"
    )
        port map (
      I0 => \init_state_r[2]_i_8_n_0\,
      I1 => \init_state_r[2]_i_9_n_0\,
      I2 => \^q\(0),
      I3 => \init_state_r[2]_i_10_n_0\,
      I4 => rdlvl_stg1_start_int_i_2_n_0,
      I5 => \init_state_r[2]_i_11_n_0\,
      O => \init_state_r[2]_i_3_n_0\
    );
\init_state_r[2]_i_30\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0040"
    )
        port map (
      I0 => cnt_cmd_done_r,
      I1 => \init_state_r_reg_n_0_[1]\,
      I2 => \^q\(0),
      I3 => reset_rd_addr_r1,
      O => \init_state_r[2]_i_30_n_0\
    );
\init_state_r[2]_i_31\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FBBBBBBB"
    )
        port map (
      I0 => cnt_init_mr_done_r,
      I1 => cnt_cmd_done_r,
      I2 => pi_dqs_found_done_r1_reg_0,
      I3 => prbs_rdlvl_start_reg_2,
      I4 => complex_oclkdelay_calib_done_r1_reg_0,
      O => \init_state_r[2]_i_31_n_0\
    );
\init_state_r[2]_i_32\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"10000000"
    )
        port map (
      I0 => \init_state_r_reg_n_0_[2]\,
      I1 => \init_state_r_reg_n_0_[3]\,
      I2 => cnt_cmd_done_r,
      I3 => \init_state_r_reg_n_0_[1]\,
      I4 => \^q\(0),
      O => \init_state_r[2]_i_32_n_0\
    );
\init_state_r[2]_i_33\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000400000000000"
    )
        port map (
      I0 => \^wrlvl_done_r1\,
      I1 => cnt_cmd_done_r,
      I2 => \init_state_r_reg_n_0_[1]\,
      I3 => \^q\(0),
      I4 => \init_state_r_reg_n_0_[2]\,
      I5 => \init_state_r_reg_n_0_[3]\,
      O => \init_state_r[2]_i_33_n_0\
    );
\init_state_r[2]_i_34\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"808A8080808A8A8A"
    )
        port map (
      I0 => \^q\(0),
      I1 => wrlvl_rank_done_r7,
      I2 => \init_state_r_reg_n_0_[1]\,
      I3 => mem_init_done_r,
      I4 => cnt_dllk_zqinit_done_r,
      I5 => \init_state_r_reg_n_0_[2]\,
      O => \init_state_r[2]_i_34_n_0\
    );
\init_state_r[2]_i_36\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"20FFFFFF2020FF00"
    )
        port map (
      I0 => prbs_last_byte_done_r,
      I1 => complex_oclkdelay_calib_done_r1_reg_0,
      I2 => pi_dqs_found_done_r1_reg_0,
      I3 => ddr3_lm_done_r_reg_0,
      I4 => mem_init_done_r,
      I5 => wrlvl_byte_redo,
      O => \init_state_r[2]_i_36_n_0\
    );
\init_state_r[2]_i_38\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0010"
    )
        port map (
      I0 => num_refresh_reg(0),
      I1 => num_refresh_reg(1),
      I2 => num_refresh_reg(3),
      I3 => num_refresh_reg(2),
      O => \init_state_r[2]_i_38_n_0\
    );
\init_state_r[2]_i_39\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2000"
    )
        port map (
      I0 => pi_dqs_found_done_r1_reg_0,
      I1 => complex_oclkdelay_calib_done_r1_reg_0,
      I2 => prbs_last_byte_done_r,
      I3 => mem_init_done_r,
      O => \init_state_r[2]_i_39_n_0\
    );
\init_state_r[2]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"ABAABBBBABAAABAA"
    )
        port map (
      I0 => \init_state_r[3]_i_6_n_0\,
      I1 => \init_state_r[2]_i_12_n_0\,
      I2 => \init_state_r[2]_i_13_n_0\,
      I3 => \init_state_r[2]_i_14_n_0\,
      I4 => \init_state_r[2]_i_15_n_0\,
      I5 => \init_state_r[2]_i_16_n_0\,
      O => \init_state_r[2]_i_4_n_0\
    );
\init_state_r[2]_i_40\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"04"
    )
        port map (
      I0 => \^wrlvl_done_r1\,
      I1 => pi_dqs_found_done_r1_reg_0,
      I2 => wrlvl_byte_redo,
      O => \init_state_r[2]_i_40_n_0\
    );
\init_state_r[2]_i_41\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"DFDFFFDF"
    )
        port map (
      I0 => \init_state_r_reg_n_0_[1]\,
      I1 => \init_state_r_reg_n_0_[2]\,
      I2 => cnt_cmd_done_r,
      I3 => cnt_init_af_done_r,
      I4 => mem_init_done_r,
      O => \init_state_r[2]_i_41_n_0\
    );
\init_state_r[2]_i_42\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0020FFFF"
    )
        port map (
      I0 => complex_oclkdelay_calib_done_r1_reg_0,
      I1 => prbs_rdlvl_done_r1,
      I2 => \^q\(0),
      I3 => \init_state_r_reg_n_0_[1]\,
      I4 => \init_state_r_reg_n_0_[2]\,
      O => \init_state_r[2]_i_42_n_0\
    );
\init_state_r[2]_i_43\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"80000000"
    )
        port map (
      I0 => complex_wait_cnt_reg(3),
      I1 => complex_wait_cnt_reg(2),
      I2 => complex_wait_cnt_reg(1),
      I3 => complex_wait_cnt_reg(0),
      I4 => \^one_rank.stg1_wr_done_reg_0\,
      O => \init_state_r[2]_i_43_n_0\
    );
\init_state_r[2]_i_44\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000080FFFFFFFF"
    )
        port map (
      I0 => \^q\(0),
      I1 => \init_state_r_reg_n_0_[1]\,
      I2 => cnt_cmd_done_r,
      I3 => \init_state_r_reg_n_0_[3]\,
      I4 => \init_state_r_reg_n_0_[2]\,
      I5 => \init_state_r_reg_n_0_[4]\,
      O => \init_state_r[2]_i_44_n_0\
    );
\init_state_r[2]_i_45\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"1111111111111110"
    )
        port map (
      I0 => \^q\(0),
      I1 => \init_state_r_reg_n_0_[1]\,
      I2 => wrlvl_byte_redo,
      I3 => \^prech_req_posedge_r_reg_0\,
      I4 => ddr3_lm_done_r_reg_0,
      I5 => wrcal_resume_r,
      O => \init_state_r[2]_i_45_n_0\
    );
\init_state_r[2]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFF45444444"
    )
        port map (
      I0 => \init_state_r[2]_i_17_n_0\,
      I1 => \init_state_r_reg_n_0_[1]\,
      I2 => \init_state_r[6]_i_11_n_0\,
      I3 => \init_state_r_reg_n_0_[2]\,
      I4 => \init_state_r[2]_i_18_n_0\,
      I5 => \init_state_r[2]_i_19_n_0\,
      O => \init_state_r[2]_i_5_n_0\
    );
\init_state_r[2]_i_6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"7F5F7F7F"
    )
        port map (
      I0 => \init_state_r_reg_n_0_[3]\,
      I1 => \init_state_r[2]_i_20_n_0\,
      I2 => \init_state_r_reg_n_0_[2]\,
      I3 => \init_state_r[2]_i_21_n_0\,
      I4 => \init_state_r_reg_n_0_[1]\,
      O => \init_state_r[2]_i_6_n_0\
    );
\init_state_r[2]_i_7\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFF4444FF4F"
    )
        port map (
      I0 => \init_state_r[2]_i_22_n_0\,
      I1 => \init_state_r[2]_i_23_n_0\,
      I2 => \init_state_r[2]_i_24_n_0\,
      I3 => \init_state_r[2]_i_25_n_0\,
      I4 => \init_state_r[2]_i_26_n_0\,
      I5 => complex_act_start_i_2_n_0,
      O => \init_state_r[2]_i_7_n_0\
    );
\init_state_r[2]_i_8\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFBFFFFFFFFFF"
    )
        port map (
      I0 => prbs_gen_oclk_clk_en_i_9_n_0,
      I1 => rdlvl_stg1_done_r1,
      I2 => complex_row0_wr_done,
      I3 => complex_oclkdelay_calib_done_r1_reg_0,
      I4 => complex_num_writes_dec(1),
      I5 => complex_num_writes_dec(0),
      O => \init_state_r[2]_i_8_n_0\
    );
\init_state_r[2]_i_9\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFEFFFFFFFFFF"
    )
        port map (
      I0 => \stg1_wr_rd_cnt_reg_n_0_[5]\,
      I1 => complex_sample_cnt_inc_i_3_n_0,
      I2 => \stg1_wr_rd_cnt_reg_n_0_[1]\,
      I3 => \stg1_wr_rd_cnt_reg_n_0_[0]\,
      I4 => \stg1_wr_rd_cnt_reg_n_0_[2]\,
      I5 => rdlvl_stg1_done_r1,
      O => \init_state_r[2]_i_9_n_0\
    );
\init_state_r[3]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"EEEEEEEEFFFFEEEF"
    )
        port map (
      I0 => \init_state_r[3]_i_2_n_0\,
      I1 => \init_state_r[3]_i_3_n_0\,
      I2 => \init_state_r[3]_i_4_n_0\,
      I3 => \init_state_r_reg_n_0_[4]\,
      I4 => \init_state_r[3]_i_5_n_0\,
      I5 => \init_state_r[3]_i_6_n_0\,
      O => \init_state_r[3]_i_1_n_0\
    );
\init_state_r[3]_i_10\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"000A3333AAAABBBB"
    )
        port map (
      I0 => \init_state_r[3]_i_21_n_0\,
      I1 => \init_state_r_reg_n_0_[3]\,
      I2 => complex_oclkdelay_calib_done_r1_reg_0,
      I3 => prbs_last_byte_done_r,
      I4 => \init_state_r[5]_i_13_n_0\,
      I5 => \init_state_r[3]_i_22_n_0\,
      O => \init_state_r[3]_i_10_n_0\
    );
\init_state_r[3]_i_11\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000000C040C"
    )
        port map (
      I0 => \init_state_r[5]_i_13_n_0\,
      I1 => \init_state_r_reg_n_0_[3]\,
      I2 => \init_state_r_reg_n_0_[2]\,
      I3 => detect_pi_found_dqs_i_2_n_0,
      I4 => prbs_rdlvl_done_pulse0,
      I5 => \init_state_r[5]_i_42_n_0\,
      O => \init_state_r[3]_i_11_n_0\
    );
\init_state_r[3]_i_12\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"000000F0DDDDFFFF"
    )
        port map (
      I0 => \init_state_r_reg_n_0_[1]\,
      I1 => \init_state_r[2]_i_21_n_0\,
      I2 => \init_state_r[5]_i_14_n_0\,
      I3 => \init_state_r[5]_i_13_n_0\,
      I4 => \init_state_r_reg_n_0_[3]\,
      I5 => \init_state_r[5]_i_12_n_0\,
      O => \init_state_r[3]_i_12_n_0\
    );
\init_state_r[3]_i_13\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0BFB000000000000"
    )
        port map (
      I0 => \init_state_r[3]_i_4_0\,
      I1 => \^pi_calib_done\,
      I2 => \init_state_r_reg_n_0_[1]\,
      I3 => reset_rd_addr_r1,
      I4 => \^q\(0),
      I5 => cnt_cmd_done_r,
      O => \init_state_r[3]_i_13_n_0\
    );
\init_state_r[3]_i_14\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0F0F3F0F4F7F7F7F"
    )
        port map (
      I0 => wrlvl_rank_done_r7,
      I1 => \init_state_r_reg_n_0_[1]\,
      I2 => \^q\(0),
      I3 => cnt_dllk_zqinit_done_r,
      I4 => mem_init_done_r,
      I5 => \init_state_r_reg_n_0_[3]\,
      O => \init_state_r[3]_i_14_n_0\
    );
\init_state_r[3]_i_15\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AA88AA8CAA88EE8C"
    )
        port map (
      I0 => \init_state_r_reg_n_0_[2]\,
      I1 => cnt_cmd_done_r,
      I2 => ddr2_pre_flag_r_reg_n_0,
      I3 => \init_state_r_reg_n_0_[1]\,
      I4 => \^q\(0),
      I5 => \init_state_r[3]_i_24_n_0\,
      O => \init_state_r[3]_i_15_n_0\
    );
\init_state_r[3]_i_16\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \init_state_r_reg_n_0_[4]\,
      I1 => \init_state_r_reg_n_0_[3]\,
      O => \init_state_r[3]_i_16_n_0\
    );
\init_state_r[3]_i_17\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \init_state_r_reg_n_0_[4]\,
      I1 => \init_state_r_reg_n_0_[2]\,
      O => \init_state_r[3]_i_17_n_0\
    );
\init_state_r[3]_i_18\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \init_state_r_reg_n_0_[1]\,
      I1 => \init_state_r_reg_n_0_[3]\,
      O => \init_state_r[3]_i_18_n_0\
    );
\init_state_r[3]_i_19\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFF04FF00FF00"
    )
        port map (
      I0 => \init_state_r[4]_i_24_n_0\,
      I1 => cnt_cmd_done_r,
      I2 => \init_state_r[0]_i_4_0\,
      I3 => \init_state_r_reg_n_0_[3]\,
      I4 => \init_state_r_reg_n_0_[1]\,
      I5 => \^q\(0),
      O => \init_state_r[3]_i_19_n_0\
    );
\init_state_r[3]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"F4444444"
    )
        port map (
      I0 => \init_state_r[3]_i_7_n_0\,
      I1 => \init_state_r[3]_i_8_n_0\,
      I2 => \init_state_r_reg_n_0_[3]\,
      I3 => init_state_r(6),
      I4 => \init_state_r[3]_i_9_n_0\,
      O => \init_state_r[3]_i_2_n_0\
    );
\init_state_r[3]_i_20\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0010"
    )
        port map (
      I0 => oclk_wr_cnt_reg(3),
      I1 => oclk_wr_cnt_reg(2),
      I2 => oclk_wr_cnt_reg(0),
      I3 => oclk_wr_cnt_reg(1),
      O => \init_state_r[3]_i_20_n_0\
    );
\init_state_r[3]_i_21\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"BF"
    )
        port map (
      I0 => \^prech_req_posedge_r_reg_0\,
      I1 => \^q\(0),
      I2 => \init_state_r_reg_n_0_[1]\,
      O => \init_state_r[3]_i_21_n_0\
    );
\init_state_r[3]_i_22\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4044"
    )
        port map (
      I0 => \init_state_r_reg_n_0_[1]\,
      I1 => \^q\(0),
      I2 => prbs_rdlvl_done_r1,
      I3 => complex_oclkdelay_calib_done_r1_reg_0,
      O => \init_state_r[3]_i_22_n_0\
    );
\init_state_r[3]_i_24\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FB00FBFB"
    )
        port map (
      I0 => wrlvl_byte_redo,
      I1 => pi_dqs_found_done_r1_reg_0,
      I2 => \^wrlvl_done_r1\,
      I3 => mem_init_done_r,
      I4 => cnt_init_af_done_r,
      O => \init_state_r[3]_i_24_n_0\
    );
\init_state_r[3]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"5555010055555100"
    )
        port map (
      I0 => \init_state_r[6]_i_2_n_0\,
      I1 => \init_state_r[3]_i_10_n_0\,
      I2 => \init_state_r_reg_n_0_[3]\,
      I3 => \init_state_r_reg_n_0_[2]\,
      I4 => \init_state_r[3]_i_11_n_0\,
      I5 => \init_state_r[3]_i_12_n_0\,
      O => \init_state_r[3]_i_3_n_0\
    );
\init_state_r[3]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8F838F83BFB38F83"
    )
        port map (
      I0 => \init_state_r[3]_i_13_n_0\,
      I1 => \init_state_r_reg_n_0_[2]\,
      I2 => \init_state_r_reg_n_0_[3]\,
      I3 => \init_state_r[3]_i_14_n_0\,
      I4 => cnt_cmd_done_r,
      I5 => prbs_rdlvl_start_i_2_n_0,
      O => \init_state_r[3]_i_4_n_0\
    );
\init_state_r[3]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"44444F4444444444"
    )
        port map (
      I0 => \init_state_r[3]_i_15_n_0\,
      I1 => \init_state_r[3]_i_16_n_0\,
      I2 => \init_state_r[4]_i_13_n_0\,
      I3 => \init_state_r[3]_i_17_n_0\,
      I4 => \init_state_r[3]_i_18_n_0\,
      I5 => \init_state_r[3]_i_19_n_0\,
      O => \init_state_r[3]_i_5_n_0\
    );
\init_state_r[3]_i_6\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => init_state_r(6),
      I1 => \init_state_r_reg_n_0_[5]\,
      O => \init_state_r[3]_i_6_n_0\
    );
\init_state_r[3]_i_7\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"883F000000000000"
    )
        port map (
      I0 => \init_state_r[3]_i_20_n_0\,
      I1 => \init_state_r_reg_n_0_[1]\,
      I2 => cnt_cmd_done_r,
      I3 => \^q\(0),
      I4 => \init_state_r_reg_n_0_[3]\,
      I5 => \init_state_r_reg_n_0_[2]\,
      O => \init_state_r[3]_i_7_n_0\
    );
\init_state_r[3]_i_8\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"000000000000EF80"
    )
        port map (
      I0 => \^q\(0),
      I1 => \init_state_r_reg_n_0_[1]\,
      I2 => \init_state_r_reg_n_0_[2]\,
      I3 => \init_state_r_reg_n_0_[3]\,
      I4 => \init_state_r_reg_n_0_[4]\,
      I5 => complex_act_start_i_2_n_0,
      O => \init_state_r[3]_i_8_n_0\
    );
\init_state_r[3]_i_9\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F1F1F5F5F1FFF5F5"
    )
        port map (
      I0 => \init_state_r[5]_i_28_n_0\,
      I1 => complex_pi_incdec_done,
      I2 => \init_state_r_reg_n_0_[2]\,
      I3 => \^prech_req_posedge_r_reg_0\,
      I4 => \^q\(0),
      I5 => \init_state_r_reg_n_0_[1]\,
      O => \init_state_r[3]_i_9_n_0\
    );
\init_state_r[4]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFF5501"
    )
        port map (
      I0 => \init_state_r[4]_i_2_n_0\,
      I1 => \init_state_r[4]_i_3_n_0\,
      I2 => \init_state_r[4]_i_4_n_0\,
      I3 => \init_state_r[4]_i_5_n_0\,
      I4 => \init_state_r[4]_i_6_n_0\,
      I5 => \init_state_r[4]_i_7_n_0\,
      O => \init_state_r[4]_i_1_n_0\
    );
\init_state_r[4]_i_10\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"EEAEEEEEEEEEEEEE"
    )
        port map (
      I0 => \init_state_r[4]_i_22_n_0\,
      I1 => \init_state_r[4]_i_23_n_0\,
      I2 => pi_dqs_found_done_r1_reg_0,
      I3 => complex_oclkdelay_calib_done_r1_reg_0,
      I4 => prbs_last_byte_done_r,
      I5 => mem_init_done_r,
      O => \init_state_r[4]_i_10_n_0\
    );
\init_state_r[4]_i_11\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"5455105554555455"
    )
        port map (
      I0 => \wrcal_reads[7]_i_4_n_0\,
      I1 => cnt_cmd_done_r,
      I2 => \init_state_r_reg_n_0_[4]\,
      I3 => \gen_no_mirror.div_clk_loop[0].phy_address[12]_i_2_n_0\,
      I4 => \init_state_r[0]_i_4_0\,
      I5 => \init_state_r[4]_i_24_n_0\,
      O => \init_state_r[4]_i_11_n_0\
    );
\init_state_r[4]_i_12\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7000"
    )
        port map (
      I0 => \^q\(0),
      I1 => \init_state_r_reg_n_0_[1]\,
      I2 => \init_state_r_reg_n_0_[2]\,
      I3 => \init_state_r_reg_n_0_[3]\,
      O => \init_state_r[4]_i_12_n_0\
    );
\init_state_r[4]_i_13\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000010"
    )
        port map (
      I0 => \^q\(0),
      I1 => reg_ctrl_cnt_r_reg(2),
      I2 => reg_ctrl_cnt_r_reg(3),
      I3 => reg_ctrl_cnt_r_reg(1),
      I4 => reg_ctrl_cnt_r_reg(0),
      O => \init_state_r[4]_i_13_n_0\
    );
\init_state_r[4]_i_14\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"1F"
    )
        port map (
      I0 => \init_state_r_reg_n_0_[2]\,
      I1 => \init_state_r_reg_n_0_[3]\,
      I2 => \init_state_r_reg_n_0_[4]\,
      O => \init_state_r[4]_i_14_n_0\
    );
\init_state_r[4]_i_15\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFF0FFF4FFF4FFF"
    )
        port map (
      I0 => \init_state_r[4]_i_25_n_0\,
      I1 => \init_state_r[4]_i_26_n_0\,
      I2 => \init_state_r_reg_n_0_[4]\,
      I3 => \init_state_r_reg_n_0_[2]\,
      I4 => detect_pi_found_dqs_i_2_n_0,
      I5 => \init_state_r_reg_n_0_[3]\,
      O => \init_state_r[4]_i_15_n_0\
    );
\init_state_r[4]_i_16\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"BA00FF00"
    )
        port map (
      I0 => \^prech_req_posedge_r_reg_0\,
      I1 => complex_oclkdelay_calib_done_r1,
      I2 => complex_oclkdelay_calib_done_r1_reg_0,
      I3 => \^q\(0),
      I4 => complex_sample_cnt_inc_i_2_n_0,
      O => \init_state_r[4]_i_16_n_0\
    );
\init_state_r[4]_i_17\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"DDDFDDDFDDDFDDDD"
    )
        port map (
      I0 => \init_state_r_reg_n_0_[5]\,
      I1 => init_state_r(6),
      I2 => \init_state_r[3]_i_7_n_0\,
      I3 => \init_state_r[1]_i_11_n_0\,
      I4 => \wrcal_reads[7]_i_4_n_0\,
      I5 => \init_state_r[4]_i_27_n_0\,
      O => \init_state_r[4]_i_17_n_0\
    );
\init_state_r[4]_i_18\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000C0A0"
    )
        port map (
      I0 => \^prech_req_posedge_r_reg_0\,
      I1 => complex_pi_incdec_done,
      I2 => \^q\(0),
      I3 => \init_state_r_reg_n_0_[1]\,
      I4 => \init_state_r_reg_n_0_[2]\,
      O => \init_state_r[4]_i_18_n_0\
    );
\init_state_r[4]_i_19\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"3F7F"
    )
        port map (
      I0 => cnt_cmd_done_r,
      I1 => \init_state_r_reg_n_0_[1]\,
      I2 => \^q\(0),
      I3 => \init_state_r_reg_n_0_[4]\,
      O => \init_state_r[4]_i_19_n_0\
    );
\init_state_r[4]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"EEEFEEEFEEEFEEEE"
    )
        port map (
      I0 => \init_state_r_reg_n_0_[5]\,
      I1 => init_state_r(6),
      I2 => \init_state_r_reg_n_0_[4]\,
      I3 => \init_state_r[4]_i_8_n_0\,
      I4 => rdlvl_stg1_start_int_i_2_n_0,
      I5 => \init_state_r[4]_i_9_n_0\,
      O => \init_state_r[4]_i_2_n_0\
    );
\init_state_r[4]_i_20\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"B000A000F000E000"
    )
        port map (
      I0 => reset_rd_addr_r1,
      I1 => cnt_cmd_done_r,
      I2 => \init_state_r_reg_n_0_[1]\,
      I3 => \^q\(0),
      I4 => \init_state_r_reg_n_0_[4]\,
      I5 => rdlvl_stg1_done_r1,
      O => \init_state_r[4]_i_20_n_0\
    );
\init_state_r[4]_i_21\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000080CC0000"
    )
        port map (
      I0 => \^rdlvl_stg1_start_int_reg_0\,
      I1 => \init_state_r[2]_i_29_n_0\,
      I2 => ddr3_lm_done_r_reg_0,
      I3 => pi_dqs_found_done_r1_reg_0,
      I4 => \^pi_calib_done\,
      I5 => \init_state_r_reg_n_0_[1]\,
      O => \init_state_r[4]_i_21_n_0\
    );
\init_state_r[4]_i_22\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"04FF04FFFFFF04FF"
    )
        port map (
      I0 => wrlvl_byte_redo,
      I1 => pi_dqs_found_done_r1_reg_0,
      I2 => \^wrlvl_done_r1\,
      I3 => cnt_cmd_done_r,
      I4 => cnt_init_af_done_r,
      I5 => mem_init_done_r,
      O => \init_state_r[4]_i_22_n_0\
    );
\init_state_r[4]_i_23\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8FFB800"
    )
        port map (
      I0 => mem_init_done_r,
      I1 => ddr3_lm_done_r_reg_0,
      I2 => wrlvl_byte_redo,
      I3 => \init_state_r[4]_i_10_0\,
      I4 => \init_state_r[2]_i_38_n_0\,
      O => \init_state_r[4]_i_23_n_0\
    );
\init_state_r[4]_i_24\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"4000000000000000"
    )
        port map (
      I0 => ddr3_lm_done_r,
      I1 => prbs_rdlvl_start_reg_2,
      I2 => complex_oclkdelay_calib_done_r1_reg_0,
      I3 => \^wrlvl_done_r1\,
      I4 => pi_dqs_found_done_r1_reg_0,
      I5 => ddr3_lm_done_r_reg_0,
      O => \init_state_r[4]_i_24_n_0\
    );
\init_state_r[4]_i_25\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4000"
    )
        port map (
      I0 => \^q\(0),
      I1 => \init_state_r_reg_n_0_[1]\,
      I2 => num_samples_done_r,
      I3 => \^prbs_rdlvl_start_reg_0\,
      O => \init_state_r[4]_i_25_n_0\
    );
\init_state_r[4]_i_26\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FDFDFDFCFDFDFD0C"
    )
        port map (
      I0 => \init_state_r[3]_i_22_n_0\,
      I1 => \init_state_r_reg_n_0_[4]\,
      I2 => \init_state_r[5]_i_13_n_0\,
      I3 => prbs_rdlvl_start_i_2_n_0,
      I4 => \^prech_req_posedge_r_reg_0\,
      I5 => \^one_rank.stg1_wr_done_reg_0\,
      O => \init_state_r[4]_i_26_n_0\
    );
\init_state_r[4]_i_27\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFF0FBBBB"
    )
        port map (
      I0 => wrcal_resume_r,
      I1 => \init_state_r[4]_i_17_0\,
      I2 => pi_phase_locked_all_r3,
      I3 => pi_phase_locked_all_r4,
      I4 => \init_state_r_reg_n_0_[1]\,
      I5 => \^q\(0),
      O => \init_state_r[4]_i_27_n_0\
    );
\init_state_r[4]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"4051000040515151"
    )
        port map (
      I0 => \^q\(0),
      I1 => \init_state_r_reg_n_0_[1]\,
      I2 => \init_state_r[4]_i_10_n_0\,
      I3 => ddr2_pre_flag_r_reg_n_0,
      I4 => cnt_cmd_done_r,
      I5 => \init_state_r_reg_n_0_[4]\,
      O => \init_state_r[4]_i_3_n_0\
    );
\init_state_r[4]_i_4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => \init_state_r_reg_n_0_[2]\,
      I1 => \init_state_r_reg_n_0_[3]\,
      O => \init_state_r[4]_i_4_n_0\
    );
\init_state_r[4]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFEAEEEEEE"
    )
        port map (
      I0 => \init_state_r[4]_i_11_n_0\,
      I1 => \init_state_r[4]_i_12_n_0\,
      I2 => \init_state_r_reg_n_0_[1]\,
      I3 => cnt_cmd_done_r,
      I4 => \init_state_r[4]_i_13_n_0\,
      I5 => \init_state_r[4]_i_14_n_0\,
      O => \init_state_r[4]_i_5_n_0\
    );
\init_state_r[4]_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000ABAAABAB"
    )
        port map (
      I0 => \init_state_r[4]_i_15_n_0\,
      I1 => rdlvl_stg1_start_int_i_2_n_0,
      I2 => \init_state_r_reg_n_0_[1]\,
      I3 => \init_state_r[4]_i_16_n_0\,
      I4 => \init_state_r[5]_i_13_n_0\,
      I5 => \init_state_r[4]_i_17_n_0\,
      O => \init_state_r[4]_i_6_n_0\
    );
\init_state_r[4]_i_7\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"A8A8A888A8A8A8A8"
    )
        port map (
      I0 => init_state_r(6),
      I1 => \init_state_r[4]_i_18_n_0\,
      I2 => \init_state_r_reg_n_0_[4]\,
      I3 => \init_state_r_reg_n_0_[2]\,
      I4 => \gen_no_mirror.div_clk_loop[0].phy_address[12]_i_2_n_0\,
      I5 => \init_state_r[5]_i_28_n_0\,
      O => \init_state_r[4]_i_7_n_0\
    );
\init_state_r[4]_i_8\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000031332033"
    )
        port map (
      I0 => \init_state_r_reg_n_0_[3]\,
      I1 => \init_state_r_reg_n_0_[2]\,
      I2 => \^wrlvl_done_r1\,
      I3 => cnt_cmd_done_r,
      I4 => \gen_no_mirror.div_clk_loop[0].phy_address_reg[10]_0\,
      I5 => \init_state_r[4]_i_19_n_0\,
      O => \init_state_r[4]_i_8_n_0\
    );
\init_state_r[4]_i_9\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"000000000000DD5D"
    )
        port map (
      I0 => detect_pi_found_dqs_i_2_n_0,
      I1 => \init_state_r[2]_i_8_n_0\,
      I2 => rdlvl_stg1_done_r1,
      I3 => complex_sample_cnt_inc_i_2_n_0,
      I4 => \init_state_r[4]_i_20_n_0\,
      I5 => \init_state_r[4]_i_21_n_0\,
      O => \init_state_r[4]_i_9_n_0\
    );
\init_state_r[5]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFF5554"
    )
        port map (
      I0 => \init_state_r[5]_i_2_n_0\,
      I1 => \init_state_r[5]_i_3_n_0\,
      I2 => \init_state_r[5]_i_4_n_0\,
      I3 => \init_state_r[5]_i_5_n_0\,
      I4 => \init_state_r[5]_i_6_n_0\,
      I5 => \init_state_r[5]_i_7_n_0\,
      O => \init_state_r[5]_i_1_n_0\
    );
\init_state_r[5]_i_10\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFA20000"
    )
        port map (
      I0 => \init_state_r_reg_n_0_[5]\,
      I1 => pi_phase_locked_all_r3,
      I2 => pi_phase_locked_all_r4,
      I3 => \^q\(0),
      I4 => \init_state_r_reg_n_0_[1]\,
      O => \init_state_r[5]_i_10_n_0\
    );
\init_state_r[5]_i_11\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFD00"
    )
        port map (
      I0 => \wrcal_reads_reg_n_0_[0]\,
      I1 => \init_state_r[5]_i_37_n_0\,
      I2 => \init_state_r[5]_i_38_n_0\,
      I3 => \init_state_r[5]_i_39_n_0\,
      I4 => \init_state_r[5]_i_40_n_0\,
      I5 => \init_state_r_reg_n_0_[1]\,
      O => \init_state_r[5]_i_11_n_0\
    );
\init_state_r[5]_i_12\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"10115555"
    )
        port map (
      I0 => \init_state_r_reg_n_0_[1]\,
      I1 => \^prech_req_posedge_r_reg_0\,
      I2 => complex_oclkdelay_calib_done_r1,
      I3 => complex_oclkdelay_calib_done_r1_reg_0,
      I4 => \^q\(0),
      O => \init_state_r[5]_i_12_n_0\
    );
\init_state_r[5]_i_13\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8000"
    )
        port map (
      I0 => complex_wait_cnt_reg(0),
      I1 => complex_wait_cnt_reg(1),
      I2 => complex_wait_cnt_reg(2),
      I3 => complex_wait_cnt_reg(3),
      O => \init_state_r[5]_i_13_n_0\
    );
\init_state_r[5]_i_14\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFEFFFFFFFFFF"
    )
        port map (
      I0 => \stg1_wr_rd_cnt_reg_n_0_[5]\,
      I1 => complex_sample_cnt_inc_i_3_n_0,
      I2 => \stg1_wr_rd_cnt_reg_n_0_[1]\,
      I3 => \stg1_wr_rd_cnt_reg_n_0_[0]\,
      I4 => \stg1_wr_rd_cnt_reg_n_0_[2]\,
      I5 => \^q\(0),
      O => \init_state_r[5]_i_14_n_0\
    );
\init_state_r[5]_i_15\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"EFFF"
    )
        port map (
      I0 => complex_oclkdelay_calib_done_r1_reg_0,
      I1 => \^q\(0),
      I2 => \init_state_r_reg_n_0_[5]\,
      I3 => \init_state_r_reg_n_0_[1]\,
      O => \init_state_r[5]_i_15_n_0\
    );
\init_state_r[5]_i_16\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0004000444440004"
    )
        port map (
      I0 => \init_state_r_reg_n_0_[1]\,
      I1 => \^q\(0),
      I2 => \init_state_r_reg_n_0_[5]\,
      I3 => \init_state_r[5]_i_13_n_0\,
      I4 => complex_oclkdelay_calib_done_r1_reg_0,
      I5 => prbs_rdlvl_done_r1,
      O => \init_state_r[5]_i_16_n_0\
    );
\init_state_r[5]_i_17\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"CFCCCCCCCECCCECC"
    )
        port map (
      I0 => \init_state_r_reg_n_0_[5]\,
      I1 => \init_state_r[5]_i_41_n_0\,
      I2 => \^prech_req_posedge_r_reg_0\,
      I3 => \^q\(0),
      I4 => \^one_rank.stg1_wr_done_reg_0\,
      I5 => \init_state_r[5]_i_13_n_0\,
      O => \init_state_r[5]_i_17_n_0\
    );
\init_state_r[5]_i_18\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AA002A02"
    )
        port map (
      I0 => \init_state_r_reg_n_0_[4]\,
      I1 => \init_state_r_reg_n_0_[5]\,
      I2 => \^q\(0),
      I3 => \init_state_r_reg_n_0_[1]\,
      I4 => cnt_cmd_done_r,
      O => \init_state_r[5]_i_18_n_0\
    );
\init_state_r[5]_i_19\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => \init_state_r_reg_n_0_[1]\,
      I1 => \init_state_r_reg_n_0_[5]\,
      O => \init_state_r[5]_i_19_n_0\
    );
\init_state_r[5]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"ABAAABABABAAABAA"
    )
        port map (
      I0 => complex_act_start_i_2_n_0,
      I1 => \init_state_r[5]_i_8_n_0\,
      I2 => \init_state_r[5]_i_9_n_0\,
      I3 => \wrcal_reads[7]_i_4_n_0\,
      I4 => \init_state_r[5]_i_10_n_0\,
      I5 => \init_state_r[5]_i_11_n_0\,
      O => \init_state_r[5]_i_2_n_0\
    );
\init_state_r[5]_i_20\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000100000000"
    )
        port map (
      I0 => complex_num_reads_dec(2),
      I1 => complex_num_reads_dec(3),
      I2 => complex_row0_rd_done,
      I3 => \init_state_r[2]_i_21_n_0\,
      I4 => complex_num_reads_dec(1),
      I5 => complex_num_reads_dec(0),
      O => \init_state_r[5]_i_20_n_0\
    );
\init_state_r[5]_i_21\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFAB00"
    )
        port map (
      I0 => prbs_rdlvl_done_pulse0,
      I1 => \init_state_r[5]_i_13_n_0\,
      I2 => \init_state_r_reg_n_0_[5]\,
      I3 => detect_pi_found_dqs_i_2_n_0,
      I4 => \init_state_r[5]_i_42_n_0\,
      I5 => \init_state_r[4]_i_4_n_0\,
      O => \init_state_r[5]_i_21_n_0\
    );
\init_state_r[5]_i_22\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000FFFFF4FF"
    )
        port map (
      I0 => \init_state_r[5]_i_43_n_0\,
      I1 => \init_state_r[5]_i_44_n_0\,
      I2 => \init_state_r[5]_i_45_n_0\,
      I3 => \init_state_r_reg_n_0_[4]\,
      I4 => \init_state_r[5]_i_46_n_0\,
      I5 => \init_state_r[3]_i_6_n_0\,
      O => \init_state_r[5]_i_22_n_0\
    );
\init_state_r[5]_i_23\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFBAAAAABABAAAAA"
    )
        port map (
      I0 => \init_state_r[5]_i_47_n_0\,
      I1 => cnt_cmd_done_r,
      I2 => \init_state_r_reg_n_0_[5]\,
      I3 => \init_state_r_reg_n_0_[1]\,
      I4 => \^q\(0),
      I5 => reset_rd_addr_r1,
      O => \init_state_r[5]_i_23_n_0\
    );
\init_state_r[5]_i_24\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"DFDFDF00FFFFFFFF"
    )
        port map (
      I0 => \init_state_r[5]_i_48_n_0\,
      I1 => \init_state_r[5]_i_49_n_0\,
      I2 => rdlvl_stg1_done_r1,
      I3 => prbs_gen_oclk_clk_en_i_9_n_0,
      I4 => \init_state_r[6]_i_26_n_0\,
      I5 => detect_pi_found_dqs_i_2_n_0,
      O => \init_state_r[5]_i_24_n_0\
    );
\init_state_r[5]_i_25\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFBBBFBBFFFFBFFF"
    )
        port map (
      I0 => \cnt_init_mr_r[0]_i_2_n_0\,
      I1 => \init_state_r_reg_n_0_[5]\,
      I2 => \^q\(0),
      I3 => \init_state_r_reg_n_0_[1]\,
      I4 => cnt_cmd_done_r,
      I5 => \init_state_r[6]_i_25_n_0\,
      O => \init_state_r[5]_i_25_n_0\
    );
\init_state_r[5]_i_26\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFF040004F0"
    )
        port map (
      I0 => \init_state_r[5]_i_50_n_0\,
      I1 => \init_state_r_reg_n_0_[5]\,
      I2 => \init_state_r_reg_n_0_[3]\,
      I3 => \init_state_r_reg_n_0_[2]\,
      I4 => \init_state_r[5]_i_43_n_0\,
      I5 => \init_state_r_reg_n_0_[4]\,
      O => \init_state_r[5]_i_26_n_0\
    );
\init_state_r[5]_i_27\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \^q\(0),
      I1 => \^prech_req_posedge_r_reg_0\,
      O => \init_state_r[5]_i_27_n_0\
    );
\init_state_r[5]_i_28\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"40000000FFFFFFFF"
    )
        port map (
      I0 => \^q\(0),
      I1 => ocal_act_wait_cnt_reg(3),
      I2 => ocal_act_wait_cnt_reg(2),
      I3 => ocal_act_wait_cnt_reg(1),
      I4 => ocal_act_wait_cnt_reg(0),
      I5 => \init_state_r_reg_n_0_[1]\,
      O => \init_state_r[5]_i_28_n_0\
    );
\init_state_r[5]_i_29\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"BFFF"
    )
        port map (
      I0 => \init_state_r_reg_n_0_[2]\,
      I1 => \init_state_r_reg_n_0_[1]\,
      I2 => \^q\(0),
      I3 => complex_pi_incdec_done,
      O => \init_state_r[5]_i_29_n_0\
    );
\init_state_r[5]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0400444455555555"
    )
        port map (
      I0 => rdlvl_stg1_start_int_i_2_n_0,
      I1 => \init_state_r[5]_i_12_n_0\,
      I2 => \init_state_r[5]_i_13_n_0\,
      I3 => \init_state_r_reg_n_0_[5]\,
      I4 => \init_state_r[5]_i_14_n_0\,
      I5 => \init_state_r[5]_i_15_n_0\,
      O => \init_state_r[5]_i_3_n_0\
    );
\init_state_r[5]_i_30\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000020"
    )
        port map (
      I0 => \^q\(0),
      I1 => wrcal_wr_cnt_reg(1),
      I2 => wrcal_wr_cnt_reg(0),
      I3 => wrcal_wr_cnt_reg(2),
      I4 => wrcal_wr_cnt_reg(3),
      O => \init_state_r[5]_i_30_n_0\
    );
\init_state_r[5]_i_31\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"AABA"
    )
        port map (
      I0 => \init_state_r_reg_n_0_[1]\,
      I1 => wrcal_prech_req,
      I2 => cnt_cmd_done_r,
      I3 => \^q\(0),
      O => \init_state_r[5]_i_31_n_0\
    );
\init_state_r[5]_i_32\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFF11F1"
    )
        port map (
      I0 => \^prech_req_posedge_r_reg_0\,
      I1 => ddr3_lm_done_r_reg_0,
      I2 => cnt_cmd_done_r,
      I3 => wrcal_prech_req,
      I4 => \^q\(0),
      O => \init_state_r[5]_i_32_n_0\
    );
\init_state_r[5]_i_33\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00103010"
    )
        port map (
      I0 => cnt_cmd_done_r,
      I1 => \init_state_r_reg_n_0_[5]\,
      I2 => \init_state_r_reg_n_0_[1]\,
      I3 => \^q\(0),
      I4 => p_17_in(3),
      O => \init_state_r[5]_i_33_n_0\
    );
\init_state_r[5]_i_34\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"F8"
    )
        port map (
      I0 => \init_state_r_reg_n_0_[1]\,
      I1 => cnt_cmd_done_r,
      I2 => \^q\(0),
      O => \init_state_r[5]_i_34_n_0\
    );
\init_state_r[5]_i_35\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AAAAAA8A"
    )
        port map (
      I0 => \init_state_r_reg_n_0_[1]\,
      I1 => oclk_wr_cnt_reg(1),
      I2 => oclk_wr_cnt_reg(0),
      I3 => oclk_wr_cnt_reg(2),
      I4 => oclk_wr_cnt_reg(3),
      O => \init_state_r[5]_i_35_n_0\
    );
\init_state_r[5]_i_36\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAFFFEAAAAAAAA"
    )
        port map (
      I0 => \init_state_r_reg_n_0_[4]\,
      I1 => cnt_cmd_done_r,
      I2 => \^q\(0),
      I3 => \init_state_r_reg_n_0_[5]\,
      I4 => \init_state_r_reg_n_0_[2]\,
      I5 => \init_state_r_reg_n_0_[3]\,
      O => \init_state_r[5]_i_36_n_0\
    );
\init_state_r[5]_i_37\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFFE"
    )
        port map (
      I0 => \wrcal_reads_reg_n_0_[5]\,
      I1 => \wrcal_reads_reg_n_0_[6]\,
      I2 => \wrcal_reads_reg_n_0_[1]\,
      I3 => \wrcal_reads_reg_n_0_[3]\,
      O => \init_state_r[5]_i_37_n_0\
    );
\init_state_r[5]_i_38\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"FE"
    )
        port map (
      I0 => \wrcal_reads_reg_n_0_[4]\,
      I1 => \wrcal_reads_reg_n_0_[2]\,
      I2 => \wrcal_reads_reg_n_0_[7]\,
      O => \init_state_r[5]_i_38_n_0\
    );
\init_state_r[5]_i_39\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \^q\(0),
      I1 => \init_state_r_reg_n_0_[5]\,
      O => \init_state_r[5]_i_39_n_0\
    );
\init_state_r[5]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000440F0F0F4F0F"
    )
        port map (
      I0 => \init_state_r[5]_i_16_n_0\,
      I1 => \init_state_r[5]_i_17_n_0\,
      I2 => \init_state_r[5]_i_18_n_0\,
      I3 => \init_state_r_reg_n_0_[2]\,
      I4 => \init_state_r_reg_n_0_[3]\,
      I5 => \init_state_r_reg_n_0_[4]\,
      O => \init_state_r[5]_i_4_n_0\
    );
\init_state_r[5]_i_40\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"000000000000FFFD"
    )
        port map (
      I0 => \init_state_r_reg_n_0_[5]\,
      I1 => wrlvl_byte_redo,
      I2 => \^prech_req_posedge_r_reg_0\,
      I3 => ddr3_lm_done_r_reg_0,
      I4 => wrcal_resume_r,
      I5 => \^q\(0),
      O => \init_state_r[5]_i_40_n_0\
    );
\init_state_r[5]_i_41\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"15FF"
    )
        port map (
      I0 => \^q\(0),
      I1 => \^prbs_rdlvl_start_reg_0\,
      I2 => num_samples_done_r,
      I3 => \init_state_r_reg_n_0_[1]\,
      O => \init_state_r[5]_i_41_n_0\
    );
\init_state_r[5]_i_42\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"00F2"
    )
        port map (
      I0 => complex_oclkdelay_calib_done_r1_reg_0,
      I1 => prbs_rdlvl_done_r1,
      I2 => \^prech_req_posedge_r_reg_0\,
      I3 => \init_state_r_reg_n_0_[1]\,
      O => \init_state_r[5]_i_42_n_0\
    );
\init_state_r[5]_i_43\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"BF"
    )
        port map (
      I0 => cnt_cmd_done_r,
      I1 => \init_state_r_reg_n_0_[5]\,
      I2 => \^q\(0),
      O => \init_state_r[5]_i_43_n_0\
    );
\init_state_r[5]_i_44\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"04"
    )
        port map (
      I0 => \init_state_r_reg_n_0_[1]\,
      I1 => \init_state_r_reg_n_0_[2]\,
      I2 => \init_state_r_reg_n_0_[3]\,
      O => \init_state_r[5]_i_44_n_0\
    );
\init_state_r[5]_i_45\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000020002000200"
    )
        port map (
      I0 => \init_state_r_reg_n_0_[5]\,
      I1 => \^q\(0),
      I2 => cnt_cmd_done_r,
      I3 => \init_state_r_reg_n_0_[3]\,
      I4 => \init_state_r_reg_n_0_[1]\,
      I5 => \init_state_r_reg_n_0_[2]\,
      O => \init_state_r[5]_i_45_n_0\
    );
\init_state_r[5]_i_46\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8000"
    )
        port map (
      I0 => \init_state_r_reg_n_0_[2]\,
      I1 => \^q\(0),
      I2 => \init_state_r_reg_n_0_[3]\,
      I3 => \init_state_r_reg_n_0_[1]\,
      O => \init_state_r[5]_i_46_n_0\
    );
\init_state_r[5]_i_47\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0008000808080008"
    )
        port map (
      I0 => cnt_cmd_done_r,
      I1 => \^q\(0),
      I2 => \init_state_r_reg_n_0_[1]\,
      I3 => \^pi_calib_done\,
      I4 => pi_dqs_found_done_r1_reg_0,
      I5 => ddr3_lm_done_r_reg_0,
      O => \init_state_r[5]_i_47_n_0\
    );
\init_state_r[5]_i_48\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000000001"
    )
        port map (
      I0 => \stg1_wr_rd_cnt_reg_n_0_[5]\,
      I1 => \stg1_wr_rd_cnt_reg_n_0_[3]\,
      I2 => \stg1_wr_rd_cnt_reg_n_0_[4]\,
      I3 => \stg1_wr_rd_cnt_reg_n_0_[6]\,
      I4 => \stg1_wr_rd_cnt_reg_n_0_[8]\,
      I5 => \stg1_wr_rd_cnt_reg_n_0_[7]\,
      O => \init_state_r[5]_i_48_n_0\
    );
\init_state_r[5]_i_49\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"FB"
    )
        port map (
      I0 => \stg1_wr_rd_cnt_reg_n_0_[1]\,
      I1 => \stg1_wr_rd_cnt_reg_n_0_[0]\,
      I2 => \stg1_wr_rd_cnt_reg_n_0_[2]\,
      O => \init_state_r[5]_i_49_n_0\
    );
\init_state_r[5]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000FFEFEFEF"
    )
        port map (
      I0 => \init_state_r[5]_i_19_n_0\,
      I1 => \init_state_r[5]_i_20_n_0\,
      I2 => complex_sample_cnt_inc_i_2_n_0,
      I3 => \^q\(0),
      I4 => \init_state_r[5]_i_13_n_0\,
      I5 => \init_state_r[5]_i_21_n_0\,
      O => \init_state_r[5]_i_5_n_0\
    );
\init_state_r[5]_i_50\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"AFCF"
    )
        port map (
      I0 => wrlvl_rank_done_r7,
      I1 => cnt_dllk_zqinit_done_r,
      I2 => \^q\(0),
      I3 => \init_state_r_reg_n_0_[1]\,
      O => \init_state_r[5]_i_50_n_0\
    );
\init_state_r[5]_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAAA2022AAAA"
    )
        port map (
      I0 => \init_state_r[5]_i_22_n_0\,
      I1 => rdlvl_stg1_start_int_i_2_n_0,
      I2 => \init_state_r[5]_i_23_n_0\,
      I3 => \init_state_r[5]_i_24_n_0\,
      I4 => \init_state_r[5]_i_25_n_0\,
      I5 => \init_state_r[5]_i_26_n_0\,
      O => \init_state_r[5]_i_6_n_0\
    );
\init_state_r[5]_i_7\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"88808888AAAAAAAA"
    )
        port map (
      I0 => init_state_r(6),
      I1 => \init_state_r_reg_n_0_[5]\,
      I2 => \init_state_r_reg_n_0_[2]\,
      I3 => \init_state_r[5]_i_27_n_0\,
      I4 => \init_state_r[5]_i_28_n_0\,
      I5 => \init_state_r[5]_i_29_n_0\,
      O => \init_state_r[5]_i_7_n_0\
    );
\init_state_r[5]_i_8\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"000000000000FEEE"
    )
        port map (
      I0 => \init_state_r[5]_i_30_n_0\,
      I1 => \init_state_r[5]_i_31_n_0\,
      I2 => \init_state_r[5]_i_32_n_0\,
      I3 => \init_state_r_reg_n_0_[5]\,
      I4 => \init_state_r[5]_i_33_n_0\,
      I5 => \cnt_init_mr_r[0]_i_2_n_0\,
      O => \init_state_r[5]_i_8_n_0\
    );
\init_state_r[5]_i_9\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFF40444444"
    )
        port map (
      I0 => rdlvl_stg1_start_int_i_2_n_0,
      I1 => \init_state_r[5]_i_34_n_0\,
      I2 => \init_state_r_reg_n_0_[5]\,
      I3 => \^q\(0),
      I4 => \init_state_r[5]_i_35_n_0\,
      I5 => \init_state_r[5]_i_36_n_0\,
      O => \init_state_r[5]_i_9_n_0\
    );
\init_state_r[6]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFF5455"
    )
        port map (
      I0 => \init_state_r[6]_i_2_n_0\,
      I1 => \init_state_r[6]_i_3_n_0\,
      I2 => \init_state_r[6]_i_4_n_0\,
      I3 => \init_state_r[6]_i_5_n_0\,
      I4 => \init_state_r[6]_i_6_n_0\,
      I5 => \init_state_r[6]_i_7_n_0\,
      O => \init_state_r[6]_i_1_n_0\
    );
\init_state_r[6]_i_10\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0040004000000040"
    )
        port map (
      I0 => \init_state_r[5]_i_13_n_0\,
      I1 => init_state_r(6),
      I2 => \init_state_r_reg_n_0_[1]\,
      I3 => \^q\(0),
      I4 => complex_oclkdelay_calib_done_r1_reg_0,
      I5 => prbs_rdlvl_done_r1,
      O => \init_state_r[6]_i_10_n_0\
    );
\init_state_r[6]_i_11\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFF0001"
    )
        port map (
      I0 => \init_state_r[6]_i_22_n_0\,
      I1 => complex_row0_rd_done,
      I2 => complex_num_reads_dec(3),
      I3 => complex_num_reads_dec(2),
      I4 => prbs_rdlvl_done_pulse0,
      I5 => \^prech_req_posedge_r_reg_0\,
      O => \init_state_r[6]_i_11_n_0\
    );
\init_state_r[6]_i_12\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AB"
    )
        port map (
      I0 => \init_state_r_reg_n_0_[1]\,
      I1 => init_state_r(6),
      I2 => \^q\(0),
      O => \init_state_r[6]_i_12_n_0\
    );
\init_state_r[6]_i_13\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"80000000AAAAAAAA"
    )
        port map (
      I0 => \^q\(0),
      I1 => complex_wait_cnt_reg(0),
      I2 => complex_wait_cnt_reg(1),
      I3 => complex_wait_cnt_reg(2),
      I4 => complex_wait_cnt_reg(3),
      I5 => init_state_r(6),
      O => \init_state_r[6]_i_13_n_0\
    );
\init_state_r[6]_i_14\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"2AAAAAAA"
    )
        port map (
      I0 => init_state_r(6),
      I1 => complex_wait_cnt_reg(3),
      I2 => complex_wait_cnt_reg(2),
      I3 => complex_wait_cnt_reg(1),
      I4 => complex_wait_cnt_reg(0),
      O => \init_state_r[6]_i_14_n_0\
    );
\init_state_r[6]_i_15\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"AA08"
    )
        port map (
      I0 => \^q\(0),
      I1 => complex_oclkdelay_calib_done_r1_reg_0,
      I2 => complex_oclkdelay_calib_done_r1,
      I3 => \^prech_req_posedge_r_reg_0\,
      O => \init_state_r[6]_i_15_n_0\
    );
\init_state_r[6]_i_16\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"77777777FF7F7777"
    )
        port map (
      I0 => \init_state_r_reg_n_0_[2]\,
      I1 => \init_state_r_reg_n_0_[3]\,
      I2 => init_state_r(6),
      I3 => complex_oclkdelay_calib_done_r1_reg_0,
      I4 => \init_state_r_reg_n_0_[1]\,
      I5 => \^q\(0),
      O => \init_state_r[6]_i_16_n_0\
    );
\init_state_r[6]_i_17\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FF1F1F1F11111111"
    )
        port map (
      I0 => \init_state_r[6]_i_9_n_0\,
      I1 => prbs_rdlvl_start_i_2_n_0,
      I2 => \init_state_r[6]_i_23_n_0\,
      I3 => \init_state_r[6]_i_24_n_0\,
      I4 => \init_state_r[6]_i_25_n_0\,
      I5 => init_state_r(6),
      O => \init_state_r[6]_i_17_n_0\
    );
\init_state_r[6]_i_18\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000D8000000"
    )
        port map (
      I0 => cnt_cmd_done_r,
      I1 => rdlvl_stg1_done_r1,
      I2 => init_state_r(6),
      I3 => \init_state_r_reg_n_0_[1]\,
      I4 => \^q\(0),
      I5 => reset_rd_addr_r1,
      O => \init_state_r[6]_i_18_n_0\
    );
\init_state_r[6]_i_19\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"5555555555575555"
    )
        port map (
      I0 => init_state_r(6),
      I1 => \stg1_wr_rd_cnt_reg_n_0_[5]\,
      I2 => complex_sample_cnt_inc_i_3_n_0,
      I3 => \stg1_wr_rd_cnt_reg_n_0_[1]\,
      I4 => \stg1_wr_rd_cnt_reg_n_0_[0]\,
      I5 => \stg1_wr_rd_cnt_reg_n_0_[2]\,
      O => \init_state_r[6]_i_19_n_0\
    );
\init_state_r[6]_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"DF"
    )
        port map (
      I0 => \init_state_r_reg_n_0_[5]\,
      I1 => init_state_r(6),
      I2 => \init_state_r_reg_n_0_[4]\,
      O => \init_state_r[6]_i_2_n_0\
    );
\init_state_r[6]_i_20\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"BBBBBBBBBBBBBBBF"
    )
        port map (
      I0 => \^q\(0),
      I1 => \init_state_r_reg_n_0_[1]\,
      I2 => \init_state_r[6]_i_26_n_0\,
      I3 => complex_num_writes_dec(2),
      I4 => complex_num_writes_dec(4),
      I5 => complex_num_writes_dec(3),
      O => \init_state_r[6]_i_20_n_0\
    );
\init_state_r[6]_i_21\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AAFF0CFF"
    )
        port map (
      I0 => \^prech_req_posedge_r_reg_0\,
      I1 => complex_oclkdelay_calib_done_r1_reg_0,
      I2 => prbs_rdlvl_done_r1,
      I3 => \^q\(0),
      I4 => \init_state_r_reg_n_0_[1]\,
      O => \init_state_r[6]_i_21_n_0\
    );
\init_state_r[6]_i_22\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFFD"
    )
        port map (
      I0 => complex_num_reads_dec(0),
      I1 => complex_num_reads_dec(1),
      I2 => complex_oclkdelay_calib_done_r1_reg_0,
      I3 => \^q\(0),
      O => \init_state_r[6]_i_22_n_0\
    );
\init_state_r[6]_i_23\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFD5FF"
    )
        port map (
      I0 => \init_state_r_reg_n_0_[3]\,
      I1 => \init_state_r_reg_n_0_[1]\,
      I2 => \init_state_r_reg_n_0_[2]\,
      I3 => \^q\(0),
      I4 => cnt_cmd_done_r,
      O => \init_state_r[6]_i_23_n_0\
    );
\init_state_r[6]_i_24\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"01"
    )
        port map (
      I0 => \init_state_r_reg_n_0_[1]\,
      I1 => \init_state_r_reg_n_0_[2]\,
      I2 => \init_state_r_reg_n_0_[3]\,
      O => \init_state_r[6]_i_24_n_0\
    );
\init_state_r[6]_i_25\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"007FFF7F"
    )
        port map (
      I0 => ck_addr_cmd_delay_done,
      I1 => cnt_pwron_cke_done_r,
      I2 => \calib_seq_reg[0]_0\(0),
      I3 => \^q\(0),
      I4 => cnt_txpr_done_r,
      O => \init_state_r[6]_i_25_n_0\
    );
\init_state_r[6]_i_26\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFDFFFFF"
    )
        port map (
      I0 => complex_num_writes_dec(0),
      I1 => complex_num_writes_dec(1),
      I2 => complex_oclkdelay_calib_done_r1_reg_0,
      I3 => complex_row0_wr_done,
      I4 => rdlvl_stg1_done_r1,
      O => \init_state_r[6]_i_26_n_0\
    );
\init_state_r[6]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"1F1F1F1FFF1F1FFF"
    )
        port map (
      I0 => \init_state_r[6]_i_8_n_0\,
      I1 => \wrcal_reads[7]_i_4_n_0\,
      I2 => \init_state_r_reg_n_0_[4]\,
      I3 => \^q\(0),
      I4 => \init_state_r_reg_n_0_[1]\,
      I5 => \init_state_r[6]_i_9_n_0\,
      O => \init_state_r[6]_i_3_n_0\
    );
\init_state_r[6]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"4444444544444444"
    )
        port map (
      I0 => \init_state_r[4]_i_4_n_0\,
      I1 => \init_state_r[6]_i_10_n_0\,
      I2 => \init_state_r[6]_i_11_n_0\,
      I3 => \init_state_r[6]_i_12_n_0\,
      I4 => \init_state_r[6]_i_13_n_0\,
      I5 => complex_sample_cnt_inc_i_2_n_0,
      O => \init_state_r[6]_i_4_n_0\
    );
\init_state_r[6]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFF0000FF75"
    )
        port map (
      I0 => \init_state_r[6]_i_14_n_0\,
      I1 => complex_sample_cnt_inc_i_2_n_0,
      I2 => \^q\(0),
      I3 => \init_state_r[6]_i_15_n_0\,
      I4 => \init_state_r_reg_n_0_[1]\,
      I5 => \init_state_r[6]_i_16_n_0\,
      O => \init_state_r[6]_i_5_n_0\
    );
\init_state_r[6]_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8A888A888A888A8A"
    )
        port map (
      I0 => \cnt_init_mr_r[0]_i_3_n_0\,
      I1 => \init_state_r[6]_i_17_n_0\,
      I2 => rdlvl_stg1_start_int_i_2_n_0,
      I3 => \init_state_r[6]_i_18_n_0\,
      I4 => \init_state_r[6]_i_19_n_0\,
      I5 => \init_state_r[6]_i_20_n_0\,
      O => \init_state_r[6]_i_6_n_0\
    );
\init_state_r[6]_i_7\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"88AAA8AA8AAAAAAA"
    )
        port map (
      I0 => init_state_r(6),
      I1 => \init_state_r_reg_n_0_[2]\,
      I2 => \init_state_r_reg_n_0_[1]\,
      I3 => \^q\(0),
      I4 => complex_pi_incdec_done,
      I5 => \^prech_req_posedge_r_reg_0\,
      O => \init_state_r[6]_i_7_n_0\
    );
\init_state_r[6]_i_8\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00FDFDFDFDFDFDFD"
    )
        port map (
      I0 => init_state_r(6),
      I1 => \init_state_r[5]_i_13_n_0\,
      I2 => \init_state_r[6]_i_21_n_0\,
      I3 => \^prbs_rdlvl_start_reg_0\,
      I4 => num_samples_done_r,
      I5 => detect_pi_found_dqs_i_2_n_0,
      O => \init_state_r[6]_i_8_n_0\
    );
\init_state_r[6]_i_9\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FEFF"
    )
        port map (
      I0 => \init_state_r_reg_n_0_[2]\,
      I1 => \init_state_r_reg_n_0_[3]\,
      I2 => cnt_cmd_done_r,
      I3 => init_state_r(6),
      O => \init_state_r[6]_i_9_n_0\
    );
\init_state_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => '1',
      D => \init_state_r[0]_i_1_n_0\,
      Q => \^q\(0),
      R => \victim_sel_reg[0]_0\(0)
    );
\init_state_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => '1',
      D => \init_state_r[1]_i_1_n_0\,
      Q => \init_state_r_reg_n_0_[1]\,
      R => \victim_sel_reg[0]_0\(0)
    );
\init_state_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => '1',
      D => \init_state_r[2]_i_1_n_0\,
      Q => \init_state_r_reg_n_0_[2]\,
      R => \victim_sel_reg[0]_0\(0)
    );
\init_state_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => '1',
      D => \init_state_r[3]_i_1_n_0\,
      Q => \init_state_r_reg_n_0_[3]\,
      R => \victim_sel_reg[0]_0\(0)
    );
\init_state_r_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => '1',
      D => \init_state_r[4]_i_1_n_0\,
      Q => \init_state_r_reg_n_0_[4]\,
      R => \victim_sel_reg[0]_0\(0)
    );
\init_state_r_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => '1',
      D => \init_state_r[5]_i_1_n_0\,
      Q => \init_state_r_reg_n_0_[5]\,
      R => \victim_sel_reg[0]_0\(0)
    );
\init_state_r_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => '1',
      D => \init_state_r[6]_i_1_n_0\,
      Q => init_state_r(6),
      R => \victim_sel_reg[0]_0\(0)
    );
mem_init_done_r_i_1: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFF4000"
    )
        port map (
      I0 => cnt_dllk_zqinit_done_r,
      I1 => cnt_dllk_zqinit_r_reg(7),
      I2 => mem_init_done_r_i_2_n_0,
      I3 => cnt_dllk_zqinit_r_reg(6),
      I4 => mem_init_done_r,
      O => mem_init_done_r_i_1_n_0
    );
mem_init_done_r_i_2: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8000000000000000"
    )
        port map (
      I0 => cnt_dllk_zqinit_r_reg(5),
      I1 => cnt_dllk_zqinit_r_reg(3),
      I2 => cnt_dllk_zqinit_r_reg(1),
      I3 => cnt_dllk_zqinit_r_reg(0),
      I4 => cnt_dllk_zqinit_r_reg(2),
      I5 => cnt_dllk_zqinit_r_reg(4),
      O => mem_init_done_r_i_2_n_0
    );
mem_init_done_r_reg: unisim.vcomponents.FDRE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => '1',
      D => mem_init_done_r_i_1_n_0,
      Q => mem_init_done_r,
      R => \victim_sel_reg[0]_0\(0)
    );
\mem_reg_0_15_12_17_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(320),
      I1 => phy_wrdata(376),
      I2 => mem_reg_0_15_18_23_0,
      O => \write_buffer.wr_buf_out_data_reg[455]_0\(5)
    );
\mem_reg_0_15_12_17_i_1__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(352),
      I1 => phy_wrdata(376),
      I2 => mem_reg_0_15_36_41_0,
      O => \write_buffer.wr_buf_out_data_reg[487]_0\(5)
    );
\mem_reg_0_15_12_17_i_1__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => mc_odt(0),
      I1 => phy_ctl_wr_i1_reg,
      I2 => calib_odt(0),
      O => \cmd_pipe_plus.mc_cke_reg[3]_0\(0)
    );
mem_reg_0_15_12_17_i_2: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(256),
      I1 => phy_wrdata(312),
      I2 => mem_reg_0_15_18_23,
      O => \write_buffer.wr_buf_out_data_reg[455]_0\(4)
    );
\mem_reg_0_15_12_17_i_2__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(288),
      I1 => phy_wrdata(312),
      I2 => mem_reg_0_15_18_23_0,
      O => \write_buffer.wr_buf_out_data_reg[487]_0\(4)
    );
mem_reg_0_15_12_17_i_3: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(448),
      I1 => phy_wrdata(504),
      I2 => mem_reg_0_15_54_59_0,
      O => \write_buffer.wr_buf_out_data_reg[455]_0\(7)
    );
\mem_reg_0_15_12_17_i_3__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(480),
      I1 => phy_wrdata(504),
      I2 => mem_reg_0_15_78_79_0,
      O => \write_buffer.wr_buf_out_data_reg[487]_0\(7)
    );
mem_reg_0_15_12_17_i_4: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(384),
      I1 => phy_wrdata(440),
      I2 => mem_reg_0_15_36_41_1,
      O => \write_buffer.wr_buf_out_data_reg[455]_0\(6)
    );
\mem_reg_0_15_12_17_i_4__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(416),
      I1 => phy_wrdata(440),
      I2 => mem_reg_0_15_36_41_1,
      O => \write_buffer.wr_buf_out_data_reg[487]_0\(6)
    );
mem_reg_0_15_12_17_i_5: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(65),
      I1 => phy_wrdata(121),
      I2 => mem_reg_0_15_48_53,
      O => \write_buffer.wr_buf_out_data_reg[455]_0\(9)
    );
\mem_reg_0_15_12_17_i_5__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(72),
      I1 => phy_wrdata(120),
      I2 => mem_reg_0_15_48_53,
      O => \write_buffer.wr_buf_out_data_reg[463]_0\(1)
    );
\mem_reg_0_15_12_17_i_5__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(80),
      I1 => phy_wrdata(120),
      I2 => mem_reg_0_15_54_59,
      O => \write_buffer.wr_buf_out_data_reg[471]_0\(1)
    );
\mem_reg_0_15_12_17_i_5__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(88),
      I1 => phy_wrdata(120),
      I2 => mem_reg_0_15_54_59,
      O => \write_buffer.wr_buf_out_data_reg[479]_0\(1)
    );
\mem_reg_0_15_12_17_i_5__3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(97),
      I1 => phy_wrdata(121),
      I2 => mem_reg_0_15_54_59,
      O => \write_buffer.wr_buf_out_data_reg[487]_0\(9)
    );
\mem_reg_0_15_12_17_i_5__4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(104),
      I1 => phy_wrdata(120),
      I2 => mem_reg_0_15_54_59,
      O => \write_buffer.wr_buf_out_data_reg[495]_0\(1)
    );
\mem_reg_0_15_12_17_i_5__5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(112),
      I1 => phy_wrdata(120),
      I2 => mem_reg_0_15_54_59,
      O => \write_buffer.wr_buf_out_data_reg[503]_0\(1)
    );
\mem_reg_0_15_12_17_i_5__6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(120),
      I1 => phy_wrdata(120),
      I2 => mem_reg_0_15_54_59,
      O => \write_buffer.wr_buf_out_data_reg[511]_0\(1)
    );
mem_reg_0_15_12_17_i_6: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(1),
      I1 => phy_wrdata(57),
      I2 => mem_reg_0_15_36_41,
      O => \write_buffer.wr_buf_out_data_reg[455]_0\(8)
    );
\mem_reg_0_15_12_17_i_6__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(8),
      I1 => phy_wrdata(56),
      I2 => mem_reg_0_15_36_41,
      O => \write_buffer.wr_buf_out_data_reg[463]_0\(0)
    );
\mem_reg_0_15_12_17_i_6__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(16),
      I1 => phy_wrdata(56),
      I2 => mem_reg_0_15_36_41,
      O => \write_buffer.wr_buf_out_data_reg[471]_0\(0)
    );
\mem_reg_0_15_12_17_i_6__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(24),
      I1 => phy_wrdata(56),
      I2 => mem_reg_0_15_36_41,
      O => \write_buffer.wr_buf_out_data_reg[479]_0\(0)
    );
\mem_reg_0_15_12_17_i_6__3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(33),
      I1 => phy_wrdata(57),
      I2 => mem_reg_0_15_48_53,
      O => \write_buffer.wr_buf_out_data_reg[487]_0\(8)
    );
\mem_reg_0_15_12_17_i_6__4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(40),
      I1 => phy_wrdata(56),
      I2 => mem_reg_0_15_48_53,
      O => \write_buffer.wr_buf_out_data_reg[495]_0\(0)
    );
\mem_reg_0_15_12_17_i_6__5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(48),
      I1 => phy_wrdata(56),
      I2 => mem_reg_0_15_48_53,
      O => \write_buffer.wr_buf_out_data_reg[503]_0\(0)
    );
\mem_reg_0_15_12_17_i_6__6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(56),
      I1 => phy_wrdata(56),
      I2 => mem_reg_0_15_48_53,
      O => \write_buffer.wr_buf_out_data_reg[511]_0\(0)
    );
mem_reg_0_15_18_23_i_1: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(193),
      I1 => phy_wrdata(249),
      I2 => mem_reg_0_15_72_77,
      O => \write_buffer.wr_buf_out_data_reg[455]_0\(11)
    );
\mem_reg_0_15_18_23_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(200),
      I1 => phy_wrdata(248),
      I2 => mem_reg_0_15_72_77,
      O => \write_buffer.wr_buf_out_data_reg[463]_0\(3)
    );
\mem_reg_0_15_18_23_i_1__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(208),
      I1 => phy_wrdata(248),
      I2 => mem_reg_0_15_72_77,
      O => \write_buffer.wr_buf_out_data_reg[471]_0\(3)
    );
\mem_reg_0_15_18_23_i_1__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(216),
      I1 => phy_wrdata(248),
      I2 => mem_reg_0_15_72_77,
      O => \write_buffer.wr_buf_out_data_reg[479]_0\(3)
    );
\mem_reg_0_15_18_23_i_1__3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(225),
      I1 => phy_wrdata(249),
      I2 => mem_reg_0_15_18_23,
      O => \write_buffer.wr_buf_out_data_reg[487]_0\(11)
    );
\mem_reg_0_15_18_23_i_1__4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(232),
      I1 => phy_wrdata(248),
      I2 => mem_reg_0_15_18_23,
      O => \write_buffer.wr_buf_out_data_reg[495]_0\(3)
    );
\mem_reg_0_15_18_23_i_1__5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(240),
      I1 => phy_wrdata(248),
      I2 => mem_reg_0_15_18_23,
      O => \write_buffer.wr_buf_out_data_reg[503]_0\(3)
    );
\mem_reg_0_15_18_23_i_1__6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(248),
      I1 => phy_wrdata(248),
      I2 => mem_reg_0_15_18_23,
      O => \write_buffer.wr_buf_out_data_reg[511]_0\(3)
    );
mem_reg_0_15_18_23_i_2: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(129),
      I1 => phy_wrdata(185),
      I2 => mem_reg_0_15_66_71,
      O => \write_buffer.wr_buf_out_data_reg[455]_0\(10)
    );
\mem_reg_0_15_18_23_i_2__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(136),
      I1 => phy_wrdata(184),
      I2 => mem_reg_0_15_66_71,
      O => \write_buffer.wr_buf_out_data_reg[463]_0\(2)
    );
\mem_reg_0_15_18_23_i_2__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(144),
      I1 => phy_wrdata(184),
      I2 => mem_reg_0_15_66_71,
      O => \write_buffer.wr_buf_out_data_reg[471]_0\(2)
    );
\mem_reg_0_15_18_23_i_2__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(152),
      I1 => phy_wrdata(184),
      I2 => mem_reg_0_15_66_71,
      O => \write_buffer.wr_buf_out_data_reg[479]_0\(2)
    );
\mem_reg_0_15_18_23_i_2__3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(161),
      I1 => phy_wrdata(185),
      I2 => mem_reg_0_15_66_71,
      O => \write_buffer.wr_buf_out_data_reg[487]_0\(10)
    );
\mem_reg_0_15_18_23_i_2__4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(168),
      I1 => phy_wrdata(184),
      I2 => mem_reg_0_15_66_71,
      O => \write_buffer.wr_buf_out_data_reg[495]_0\(2)
    );
\mem_reg_0_15_18_23_i_2__5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(176),
      I1 => phy_wrdata(184),
      I2 => mem_reg_0_15_72_77,
      O => \write_buffer.wr_buf_out_data_reg[503]_0\(2)
    );
\mem_reg_0_15_18_23_i_2__6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(184),
      I1 => phy_wrdata(184),
      I2 => mem_reg_0_15_72_77,
      O => \write_buffer.wr_buf_out_data_reg[511]_0\(2)
    );
mem_reg_0_15_18_23_i_3: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(321),
      I1 => phy_wrdata(377),
      I2 => mem_reg_0_15_18_23_0,
      O => \write_buffer.wr_buf_out_data_reg[455]_0\(13)
    );
\mem_reg_0_15_18_23_i_3__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(328),
      I1 => phy_wrdata(376),
      I2 => mem_reg_0_15_36_41_0,
      O => \write_buffer.wr_buf_out_data_reg[463]_0\(5)
    );
\mem_reg_0_15_18_23_i_3__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(336),
      I1 => phy_wrdata(376),
      I2 => mem_reg_0_15_36_41_0,
      O => \write_buffer.wr_buf_out_data_reg[471]_0\(5)
    );
\mem_reg_0_15_18_23_i_3__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(344),
      I1 => phy_wrdata(376),
      I2 => mem_reg_0_15_36_41_0,
      O => \write_buffer.wr_buf_out_data_reg[479]_0\(5)
    );
\mem_reg_0_15_18_23_i_3__3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(353),
      I1 => phy_wrdata(377),
      I2 => mem_reg_0_15_36_41_0,
      O => \write_buffer.wr_buf_out_data_reg[487]_0\(13)
    );
\mem_reg_0_15_18_23_i_3__4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(360),
      I1 => phy_wrdata(376),
      I2 => mem_reg_0_15_36_41_0,
      O => \write_buffer.wr_buf_out_data_reg[495]_0\(5)
    );
\mem_reg_0_15_18_23_i_3__5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(368),
      I1 => phy_wrdata(376),
      I2 => mem_reg_0_15_36_41_0,
      O => \write_buffer.wr_buf_out_data_reg[503]_0\(5)
    );
\mem_reg_0_15_18_23_i_3__6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(376),
      I1 => phy_wrdata(376),
      I2 => mem_reg_0_15_36_41_1,
      O => \write_buffer.wr_buf_out_data_reg[511]_0\(5)
    );
mem_reg_0_15_18_23_i_4: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(257),
      I1 => phy_wrdata(313),
      I2 => mem_reg_0_15_18_23,
      O => \write_buffer.wr_buf_out_data_reg[455]_0\(12)
    );
\mem_reg_0_15_18_23_i_4__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(264),
      I1 => phy_wrdata(312),
      I2 => mem_reg_0_15_18_23,
      O => \write_buffer.wr_buf_out_data_reg[463]_0\(4)
    );
\mem_reg_0_15_18_23_i_4__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(272),
      I1 => phy_wrdata(312),
      I2 => mem_reg_0_15_18_23,
      O => \write_buffer.wr_buf_out_data_reg[471]_0\(4)
    );
\mem_reg_0_15_18_23_i_4__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(280),
      I1 => phy_wrdata(312),
      I2 => mem_reg_0_15_18_23_0,
      O => \write_buffer.wr_buf_out_data_reg[479]_0\(4)
    );
\mem_reg_0_15_18_23_i_4__3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(289),
      I1 => phy_wrdata(313),
      I2 => mem_reg_0_15_18_23_0,
      O => \write_buffer.wr_buf_out_data_reg[487]_0\(12)
    );
\mem_reg_0_15_18_23_i_4__4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(296),
      I1 => phy_wrdata(312),
      I2 => mem_reg_0_15_18_23_0,
      O => \write_buffer.wr_buf_out_data_reg[495]_0\(4)
    );
\mem_reg_0_15_18_23_i_4__5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(304),
      I1 => phy_wrdata(312),
      I2 => mem_reg_0_15_18_23_0,
      O => \write_buffer.wr_buf_out_data_reg[503]_0\(4)
    );
\mem_reg_0_15_18_23_i_4__6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(312),
      I1 => phy_wrdata(312),
      I2 => mem_reg_0_15_18_23_0,
      O => \write_buffer.wr_buf_out_data_reg[511]_0\(4)
    );
mem_reg_0_15_18_23_i_5: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(449),
      I1 => phy_wrdata(505),
      I2 => mem_reg_0_15_54_59_0,
      O => \write_buffer.wr_buf_out_data_reg[455]_0\(15)
    );
\mem_reg_0_15_18_23_i_5__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(456),
      I1 => phy_wrdata(504),
      I2 => mem_reg_0_15_54_59_0,
      O => \write_buffer.wr_buf_out_data_reg[463]_0\(7)
    );
\mem_reg_0_15_18_23_i_5__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(464),
      I1 => phy_wrdata(504),
      I2 => mem_reg_0_15_54_59_0,
      O => \write_buffer.wr_buf_out_data_reg[471]_0\(7)
    );
\mem_reg_0_15_18_23_i_5__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(472),
      I1 => phy_wrdata(504),
      I2 => mem_reg_0_15_78_79_0,
      O => \write_buffer.wr_buf_out_data_reg[479]_0\(7)
    );
\mem_reg_0_15_18_23_i_5__3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(481),
      I1 => phy_wrdata(505),
      I2 => mem_reg_0_15_78_79_0,
      O => \write_buffer.wr_buf_out_data_reg[487]_0\(15)
    );
\mem_reg_0_15_18_23_i_5__4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(488),
      I1 => phy_wrdata(504),
      I2 => mem_reg_0_15_78_79_0,
      O => \write_buffer.wr_buf_out_data_reg[495]_0\(7)
    );
\mem_reg_0_15_18_23_i_5__5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(496),
      I1 => phy_wrdata(504),
      I2 => mem_reg_0_15_78_79_0,
      O => \write_buffer.wr_buf_out_data_reg[503]_0\(7)
    );
\mem_reg_0_15_18_23_i_5__6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(504),
      I1 => phy_wrdata(504),
      I2 => mem_reg_0_15_78_79_0,
      O => \write_buffer.wr_buf_out_data_reg[511]_0\(7)
    );
mem_reg_0_15_18_23_i_6: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(385),
      I1 => phy_wrdata(441),
      I2 => mem_reg_0_15_36_41_1,
      O => \write_buffer.wr_buf_out_data_reg[455]_0\(14)
    );
\mem_reg_0_15_18_23_i_6__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(392),
      I1 => phy_wrdata(440),
      I2 => mem_reg_0_15_36_41_1,
      O => \write_buffer.wr_buf_out_data_reg[463]_0\(6)
    );
\mem_reg_0_15_18_23_i_6__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(400),
      I1 => phy_wrdata(440),
      I2 => mem_reg_0_15_36_41_1,
      O => \write_buffer.wr_buf_out_data_reg[471]_0\(6)
    );
\mem_reg_0_15_18_23_i_6__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(408),
      I1 => phy_wrdata(440),
      I2 => mem_reg_0_15_36_41_1,
      O => \write_buffer.wr_buf_out_data_reg[479]_0\(6)
    );
\mem_reg_0_15_18_23_i_6__3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(417),
      I1 => phy_wrdata(441),
      I2 => mem_reg_0_15_36_41_1,
      O => \write_buffer.wr_buf_out_data_reg[487]_0\(14)
    );
\mem_reg_0_15_18_23_i_6__4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(424),
      I1 => phy_wrdata(440),
      I2 => mem_reg_0_15_54_59_0,
      O => \write_buffer.wr_buf_out_data_reg[495]_0\(6)
    );
\mem_reg_0_15_18_23_i_6__5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(432),
      I1 => phy_wrdata(440),
      I2 => mem_reg_0_15_54_59_0,
      O => \write_buffer.wr_buf_out_data_reg[503]_0\(6)
    );
\mem_reg_0_15_18_23_i_6__6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(440),
      I1 => phy_wrdata(440),
      I2 => mem_reg_0_15_54_59_0,
      O => \write_buffer.wr_buf_out_data_reg[511]_0\(6)
    );
mem_reg_0_15_24_29_i_1: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mc_address(22),
      I1 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[10]\,
      I2 => \phy_ctl_wd_i1_reg[0]\,
      O => d_in(5)
    );
\mem_reg_0_15_24_29_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(66),
      I1 => phy_wrdata(122),
      I2 => mem_reg_0_15_48_53,
      O => \write_buffer.wr_buf_out_data_reg[455]_0\(17)
    );
\mem_reg_0_15_24_29_i_1__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(73),
      I1 => phy_wrdata(121),
      I2 => mem_reg_0_15_48_53,
      O => \write_buffer.wr_buf_out_data_reg[463]_0\(9)
    );
\mem_reg_0_15_24_29_i_1__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(81),
      I1 => phy_wrdata(121),
      I2 => mem_reg_0_15_54_59,
      O => \write_buffer.wr_buf_out_data_reg[471]_0\(9)
    );
\mem_reg_0_15_24_29_i_1__3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(89),
      I1 => phy_wrdata(121),
      I2 => mem_reg_0_15_54_59,
      O => \write_buffer.wr_buf_out_data_reg[479]_0\(9)
    );
\mem_reg_0_15_24_29_i_1__4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(98),
      I1 => phy_wrdata(122),
      I2 => mem_reg_0_15_54_59,
      O => \write_buffer.wr_buf_out_data_reg[487]_0\(17)
    );
\mem_reg_0_15_24_29_i_1__5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(105),
      I1 => phy_wrdata(121),
      I2 => mem_reg_0_15_54_59,
      O => \write_buffer.wr_buf_out_data_reg[495]_0\(9)
    );
\mem_reg_0_15_24_29_i_1__6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(113),
      I1 => phy_wrdata(121),
      I2 => mem_reg_0_15_54_59,
      O => \write_buffer.wr_buf_out_data_reg[503]_0\(9)
    );
\mem_reg_0_15_24_29_i_1__7\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(121),
      I1 => phy_wrdata(121),
      I2 => mem_reg_0_15_54_59,
      O => \write_buffer.wr_buf_out_data_reg[511]_0\(9)
    );
mem_reg_0_15_24_29_i_2: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mc_address(10),
      I1 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[10]\,
      I2 => \phy_ctl_wd_i1_reg[0]\,
      O => d_in(4)
    );
\mem_reg_0_15_24_29_i_2__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(2),
      I1 => phy_wrdata(58),
      I2 => mem_reg_0_15_36_41,
      O => \write_buffer.wr_buf_out_data_reg[455]_0\(16)
    );
\mem_reg_0_15_24_29_i_2__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(9),
      I1 => phy_wrdata(57),
      I2 => mem_reg_0_15_36_41,
      O => \write_buffer.wr_buf_out_data_reg[463]_0\(8)
    );
\mem_reg_0_15_24_29_i_2__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(17),
      I1 => phy_wrdata(57),
      I2 => mem_reg_0_15_36_41,
      O => \write_buffer.wr_buf_out_data_reg[471]_0\(8)
    );
\mem_reg_0_15_24_29_i_2__3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(25),
      I1 => phy_wrdata(57),
      I2 => mem_reg_0_15_36_41,
      O => \write_buffer.wr_buf_out_data_reg[479]_0\(8)
    );
\mem_reg_0_15_24_29_i_2__4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(34),
      I1 => phy_wrdata(58),
      I2 => mem_reg_0_15_48_53,
      O => \write_buffer.wr_buf_out_data_reg[487]_0\(16)
    );
\mem_reg_0_15_24_29_i_2__5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(41),
      I1 => phy_wrdata(57),
      I2 => mem_reg_0_15_48_53,
      O => \write_buffer.wr_buf_out_data_reg[495]_0\(8)
    );
\mem_reg_0_15_24_29_i_2__6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(49),
      I1 => phy_wrdata(57),
      I2 => mem_reg_0_15_48_53,
      O => \write_buffer.wr_buf_out_data_reg[503]_0\(8)
    );
\mem_reg_0_15_24_29_i_2__7\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(57),
      I1 => phy_wrdata(57),
      I2 => mem_reg_0_15_48_53,
      O => \write_buffer.wr_buf_out_data_reg[511]_0\(8)
    );
mem_reg_0_15_24_29_i_3: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(194),
      I1 => phy_wrdata(250),
      I2 => mem_reg_0_15_72_77,
      O => \write_buffer.wr_buf_out_data_reg[455]_0\(19)
    );
\mem_reg_0_15_24_29_i_3__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(201),
      I1 => phy_wrdata(249),
      I2 => mem_reg_0_15_72_77,
      O => \write_buffer.wr_buf_out_data_reg[463]_0\(11)
    );
\mem_reg_0_15_24_29_i_3__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(209),
      I1 => phy_wrdata(249),
      I2 => mem_reg_0_15_72_77,
      O => \write_buffer.wr_buf_out_data_reg[471]_0\(11)
    );
\mem_reg_0_15_24_29_i_3__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(217),
      I1 => phy_wrdata(249),
      I2 => mem_reg_0_15_72_77,
      O => \write_buffer.wr_buf_out_data_reg[479]_0\(11)
    );
\mem_reg_0_15_24_29_i_3__3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(226),
      I1 => phy_wrdata(250),
      I2 => mem_reg_0_15_18_23,
      O => \write_buffer.wr_buf_out_data_reg[487]_0\(19)
    );
\mem_reg_0_15_24_29_i_3__4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(233),
      I1 => phy_wrdata(249),
      I2 => mem_reg_0_15_18_23,
      O => \write_buffer.wr_buf_out_data_reg[495]_0\(11)
    );
\mem_reg_0_15_24_29_i_3__5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(241),
      I1 => phy_wrdata(249),
      I2 => mem_reg_0_15_18_23,
      O => \write_buffer.wr_buf_out_data_reg[503]_0\(11)
    );
\mem_reg_0_15_24_29_i_3__6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(249),
      I1 => phy_wrdata(249),
      I2 => mem_reg_0_15_18_23,
      O => \write_buffer.wr_buf_out_data_reg[511]_0\(11)
    );
\mem_reg_0_15_24_29_i_3__7\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[10]\,
      I1 => mem_reg_0_15_36_41,
      O => d_in(7)
    );
mem_reg_0_15_24_29_i_4: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mc_address(33),
      I1 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[10]\,
      I2 => \phy_ctl_wd_i1_reg[0]\,
      O => d_in(6)
    );
\mem_reg_0_15_24_29_i_4__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(130),
      I1 => phy_wrdata(186),
      I2 => mem_reg_0_15_66_71,
      O => \write_buffer.wr_buf_out_data_reg[455]_0\(18)
    );
\mem_reg_0_15_24_29_i_4__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(137),
      I1 => phy_wrdata(185),
      I2 => mem_reg_0_15_66_71,
      O => \write_buffer.wr_buf_out_data_reg[463]_0\(10)
    );
\mem_reg_0_15_24_29_i_4__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(145),
      I1 => phy_wrdata(185),
      I2 => mem_reg_0_15_66_71,
      O => \write_buffer.wr_buf_out_data_reg[471]_0\(10)
    );
\mem_reg_0_15_24_29_i_4__3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(153),
      I1 => phy_wrdata(185),
      I2 => mem_reg_0_15_66_71,
      O => \write_buffer.wr_buf_out_data_reg[479]_0\(10)
    );
\mem_reg_0_15_24_29_i_4__4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(162),
      I1 => phy_wrdata(186),
      I2 => mem_reg_0_15_66_71,
      O => \write_buffer.wr_buf_out_data_reg[487]_0\(18)
    );
\mem_reg_0_15_24_29_i_4__5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(169),
      I1 => phy_wrdata(185),
      I2 => mem_reg_0_15_66_71,
      O => \write_buffer.wr_buf_out_data_reg[495]_0\(10)
    );
\mem_reg_0_15_24_29_i_4__6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(177),
      I1 => phy_wrdata(185),
      I2 => mem_reg_0_15_72_77,
      O => \write_buffer.wr_buf_out_data_reg[503]_0\(10)
    );
\mem_reg_0_15_24_29_i_4__7\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(185),
      I1 => phy_wrdata(185),
      I2 => mem_reg_0_15_72_77,
      O => \write_buffer.wr_buf_out_data_reg[511]_0\(10)
    );
mem_reg_0_15_24_29_i_5: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(322),
      I1 => phy_wrdata(378),
      I2 => mem_reg_0_15_36_41_0,
      O => \write_buffer.wr_buf_out_data_reg[455]_0\(21)
    );
\mem_reg_0_15_24_29_i_5__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(329),
      I1 => phy_wrdata(377),
      I2 => mem_reg_0_15_36_41_0,
      O => \write_buffer.wr_buf_out_data_reg[463]_0\(13)
    );
\mem_reg_0_15_24_29_i_5__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(337),
      I1 => phy_wrdata(377),
      I2 => mem_reg_0_15_36_41_0,
      O => \write_buffer.wr_buf_out_data_reg[471]_0\(13)
    );
\mem_reg_0_15_24_29_i_5__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(345),
      I1 => phy_wrdata(377),
      I2 => mem_reg_0_15_36_41_0,
      O => \write_buffer.wr_buf_out_data_reg[479]_0\(13)
    );
\mem_reg_0_15_24_29_i_5__3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(354),
      I1 => phy_wrdata(378),
      I2 => mem_reg_0_15_36_41_0,
      O => \write_buffer.wr_buf_out_data_reg[487]_0\(21)
    );
\mem_reg_0_15_24_29_i_5__4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(361),
      I1 => phy_wrdata(377),
      I2 => mem_reg_0_15_36_41_0,
      O => \write_buffer.wr_buf_out_data_reg[495]_0\(13)
    );
\mem_reg_0_15_24_29_i_5__5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(369),
      I1 => phy_wrdata(377),
      I2 => mem_reg_0_15_36_41_0,
      O => \write_buffer.wr_buf_out_data_reg[503]_0\(13)
    );
\mem_reg_0_15_24_29_i_5__6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(377),
      I1 => phy_wrdata(377),
      I2 => mem_reg_0_15_36_41_1,
      O => \write_buffer.wr_buf_out_data_reg[511]_0\(13)
    );
mem_reg_0_15_24_29_i_6: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(258),
      I1 => phy_wrdata(314),
      I2 => mem_reg_0_15_18_23,
      O => \write_buffer.wr_buf_out_data_reg[455]_0\(20)
    );
\mem_reg_0_15_24_29_i_6__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(265),
      I1 => phy_wrdata(313),
      I2 => mem_reg_0_15_18_23,
      O => \write_buffer.wr_buf_out_data_reg[463]_0\(12)
    );
\mem_reg_0_15_24_29_i_6__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(273),
      I1 => phy_wrdata(313),
      I2 => mem_reg_0_15_18_23_0,
      O => \write_buffer.wr_buf_out_data_reg[471]_0\(12)
    );
\mem_reg_0_15_24_29_i_6__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(281),
      I1 => phy_wrdata(313),
      I2 => mem_reg_0_15_18_23_0,
      O => \write_buffer.wr_buf_out_data_reg[479]_0\(12)
    );
\mem_reg_0_15_24_29_i_6__3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(290),
      I1 => phy_wrdata(314),
      I2 => mem_reg_0_15_18_23_0,
      O => \write_buffer.wr_buf_out_data_reg[487]_0\(20)
    );
\mem_reg_0_15_24_29_i_6__4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(297),
      I1 => phy_wrdata(313),
      I2 => mem_reg_0_15_18_23_0,
      O => \write_buffer.wr_buf_out_data_reg[495]_0\(12)
    );
\mem_reg_0_15_24_29_i_6__5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(305),
      I1 => phy_wrdata(313),
      I2 => mem_reg_0_15_18_23_0,
      O => \write_buffer.wr_buf_out_data_reg[503]_0\(12)
    );
\mem_reg_0_15_24_29_i_6__6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(313),
      I1 => phy_wrdata(313),
      I2 => mem_reg_0_15_18_23_0,
      O => \write_buffer.wr_buf_out_data_reg[511]_0\(12)
    );
mem_reg_0_15_30_35_i_1: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mc_address(16),
      I1 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[4]\,
      I2 => \phy_ctl_wd_i1_reg[0]\,
      O => d_in(9)
    );
\mem_reg_0_15_30_35_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mc_address(20),
      I1 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[8]\,
      I2 => \phy_ctl_wd_i1_reg[0]\,
      O => phy_dout(1)
    );
\mem_reg_0_15_30_35_i_1__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(450),
      I1 => phy_wrdata(506),
      I2 => mem_reg_0_15_54_59_0,
      O => \write_buffer.wr_buf_out_data_reg[455]_0\(23)
    );
\mem_reg_0_15_30_35_i_1__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(457),
      I1 => phy_wrdata(505),
      I2 => mem_reg_0_15_54_59_0,
      O => \write_buffer.wr_buf_out_data_reg[463]_0\(15)
    );
\mem_reg_0_15_30_35_i_1__3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(465),
      I1 => phy_wrdata(505),
      I2 => mem_reg_0_15_54_59_0,
      O => \write_buffer.wr_buf_out_data_reg[471]_0\(15)
    );
\mem_reg_0_15_30_35_i_1__4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(473),
      I1 => phy_wrdata(505),
      I2 => mem_reg_0_15_78_79_0,
      O => \write_buffer.wr_buf_out_data_reg[479]_0\(15)
    );
\mem_reg_0_15_30_35_i_1__5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(482),
      I1 => phy_wrdata(506),
      I2 => mem_reg_0_15_78_79_0,
      O => \write_buffer.wr_buf_out_data_reg[487]_0\(23)
    );
\mem_reg_0_15_30_35_i_1__6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(489),
      I1 => phy_wrdata(505),
      I2 => mem_reg_0_15_78_79_0,
      O => \write_buffer.wr_buf_out_data_reg[495]_0\(15)
    );
\mem_reg_0_15_30_35_i_1__7\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(497),
      I1 => phy_wrdata(505),
      I2 => mem_reg_0_15_78_79_0,
      O => \write_buffer.wr_buf_out_data_reg[503]_0\(15)
    );
\mem_reg_0_15_30_35_i_1__8\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(505),
      I1 => phy_wrdata(505),
      I2 => mem_reg_0_15_78_79_0,
      O => \write_buffer.wr_buf_out_data_reg[511]_0\(15)
    );
\mem_reg_0_15_30_35_i_1__9\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => mc_cas_n(0),
      I1 => phy_ctl_wr_i1_reg,
      I2 => phy_cs_n(1),
      O => \cmd_pipe_plus.mc_cke_reg[3]_0\(1)
    );
mem_reg_0_15_30_35_i_2: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mc_address(4),
      I1 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[4]\,
      I2 => \phy_ctl_wd_i1_reg[0]\,
      O => d_in(8)
    );
\mem_reg_0_15_30_35_i_2__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mc_address(8),
      I1 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[8]\,
      I2 => \phy_ctl_wd_i1_reg[0]\,
      O => phy_dout(0)
    );
\mem_reg_0_15_30_35_i_2__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(386),
      I1 => phy_wrdata(442),
      I2 => mem_reg_0_15_36_41_1,
      O => \write_buffer.wr_buf_out_data_reg[455]_0\(22)
    );
\mem_reg_0_15_30_35_i_2__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(393),
      I1 => phy_wrdata(441),
      I2 => mem_reg_0_15_36_41_1,
      O => \write_buffer.wr_buf_out_data_reg[463]_0\(14)
    );
\mem_reg_0_15_30_35_i_2__3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(401),
      I1 => phy_wrdata(441),
      I2 => mem_reg_0_15_36_41_1,
      O => \write_buffer.wr_buf_out_data_reg[471]_0\(14)
    );
\mem_reg_0_15_30_35_i_2__4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(409),
      I1 => phy_wrdata(441),
      I2 => mem_reg_0_15_36_41_1,
      O => \write_buffer.wr_buf_out_data_reg[479]_0\(14)
    );
\mem_reg_0_15_30_35_i_2__5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(418),
      I1 => phy_wrdata(442),
      I2 => mem_reg_0_15_36_41_1,
      O => \write_buffer.wr_buf_out_data_reg[487]_0\(22)
    );
\mem_reg_0_15_30_35_i_2__6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(425),
      I1 => phy_wrdata(441),
      I2 => mem_reg_0_15_54_59_0,
      O => \write_buffer.wr_buf_out_data_reg[495]_0\(14)
    );
\mem_reg_0_15_30_35_i_2__7\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(433),
      I1 => phy_wrdata(441),
      I2 => mem_reg_0_15_54_59_0,
      O => \write_buffer.wr_buf_out_data_reg[503]_0\(14)
    );
\mem_reg_0_15_30_35_i_2__8\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(441),
      I1 => phy_wrdata(441),
      I2 => mem_reg_0_15_54_59_0,
      O => \write_buffer.wr_buf_out_data_reg[511]_0\(14)
    );
mem_reg_0_15_30_35_i_3: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(67),
      I1 => phy_wrdata(123),
      I2 => mem_reg_0_15_48_53,
      O => \write_buffer.wr_buf_out_data_reg[455]_0\(25)
    );
\mem_reg_0_15_30_35_i_3__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(74),
      I1 => phy_wrdata(122),
      I2 => mem_reg_0_15_48_53,
      O => \write_buffer.wr_buf_out_data_reg[463]_0\(17)
    );
\mem_reg_0_15_30_35_i_3__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(82),
      I1 => phy_wrdata(122),
      I2 => mem_reg_0_15_54_59,
      O => \write_buffer.wr_buf_out_data_reg[471]_0\(17)
    );
\mem_reg_0_15_30_35_i_3__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(90),
      I1 => phy_wrdata(122),
      I2 => mem_reg_0_15_54_59,
      O => \write_buffer.wr_buf_out_data_reg[479]_0\(17)
    );
\mem_reg_0_15_30_35_i_3__3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(99),
      I1 => phy_wrdata(123),
      I2 => mem_reg_0_15_54_59,
      O => \write_buffer.wr_buf_out_data_reg[487]_0\(25)
    );
\mem_reg_0_15_30_35_i_3__4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(106),
      I1 => phy_wrdata(122),
      I2 => mem_reg_0_15_54_59,
      O => \write_buffer.wr_buf_out_data_reg[495]_0\(17)
    );
\mem_reg_0_15_30_35_i_3__5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(114),
      I1 => phy_wrdata(122),
      I2 => mem_reg_0_15_54_59,
      O => \write_buffer.wr_buf_out_data_reg[503]_0\(17)
    );
\mem_reg_0_15_30_35_i_3__6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(122),
      I1 => phy_wrdata(122),
      I2 => mem_reg_0_15_54_59,
      O => \write_buffer.wr_buf_out_data_reg[511]_0\(17)
    );
\mem_reg_0_15_30_35_i_3__7\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[4]\,
      I1 => mem_reg_0_15_36_41,
      O => d_in(11)
    );
\mem_reg_0_15_30_35_i_3__8\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[8]\,
      I1 => mem_reg_0_15_36_41,
      O => phy_dout(3)
    );
mem_reg_0_15_30_35_i_4: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mc_address(27),
      I1 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[4]\,
      I2 => \phy_ctl_wd_i1_reg[0]\,
      O => d_in(10)
    );
\mem_reg_0_15_30_35_i_4__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mc_address(31),
      I1 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[8]\,
      I2 => \phy_ctl_wd_i1_reg[0]\,
      O => phy_dout(2)
    );
\mem_reg_0_15_30_35_i_4__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(3),
      I1 => phy_wrdata(59),
      I2 => mem_reg_0_15_36_41,
      O => \write_buffer.wr_buf_out_data_reg[455]_0\(24)
    );
\mem_reg_0_15_30_35_i_4__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(10),
      I1 => phy_wrdata(58),
      I2 => mem_reg_0_15_36_41,
      O => \write_buffer.wr_buf_out_data_reg[463]_0\(16)
    );
\mem_reg_0_15_30_35_i_4__3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(18),
      I1 => phy_wrdata(58),
      I2 => mem_reg_0_15_36_41,
      O => \write_buffer.wr_buf_out_data_reg[471]_0\(16)
    );
\mem_reg_0_15_30_35_i_4__4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(26),
      I1 => phy_wrdata(58),
      I2 => mem_reg_0_15_36_41,
      O => \write_buffer.wr_buf_out_data_reg[479]_0\(16)
    );
\mem_reg_0_15_30_35_i_4__5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(35),
      I1 => phy_wrdata(59),
      I2 => mem_reg_0_15_48_53,
      O => \write_buffer.wr_buf_out_data_reg[487]_0\(24)
    );
\mem_reg_0_15_30_35_i_4__6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(42),
      I1 => phy_wrdata(58),
      I2 => mem_reg_0_15_48_53,
      O => \write_buffer.wr_buf_out_data_reg[495]_0\(16)
    );
\mem_reg_0_15_30_35_i_4__7\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(50),
      I1 => phy_wrdata(58),
      I2 => mem_reg_0_15_48_53,
      O => \write_buffer.wr_buf_out_data_reg[503]_0\(16)
    );
\mem_reg_0_15_30_35_i_4__8\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(58),
      I1 => phy_wrdata(58),
      I2 => mem_reg_0_15_48_53,
      O => \write_buffer.wr_buf_out_data_reg[511]_0\(16)
    );
mem_reg_0_15_30_35_i_5: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(195),
      I1 => phy_wrdata(251),
      I2 => mem_reg_0_15_72_77,
      O => \write_buffer.wr_buf_out_data_reg[455]_0\(27)
    );
\mem_reg_0_15_30_35_i_5__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(202),
      I1 => phy_wrdata(250),
      I2 => mem_reg_0_15_72_77,
      O => \write_buffer.wr_buf_out_data_reg[463]_0\(19)
    );
\mem_reg_0_15_30_35_i_5__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(210),
      I1 => phy_wrdata(250),
      I2 => mem_reg_0_15_72_77,
      O => \write_buffer.wr_buf_out_data_reg[471]_0\(19)
    );
\mem_reg_0_15_30_35_i_5__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(218),
      I1 => phy_wrdata(250),
      I2 => mem_reg_0_15_72_77,
      O => \write_buffer.wr_buf_out_data_reg[479]_0\(19)
    );
\mem_reg_0_15_30_35_i_5__3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(227),
      I1 => phy_wrdata(251),
      I2 => mem_reg_0_15_18_23,
      O => \write_buffer.wr_buf_out_data_reg[487]_0\(27)
    );
\mem_reg_0_15_30_35_i_5__4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(234),
      I1 => phy_wrdata(250),
      I2 => mem_reg_0_15_18_23,
      O => \write_buffer.wr_buf_out_data_reg[495]_0\(19)
    );
\mem_reg_0_15_30_35_i_5__5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(242),
      I1 => phy_wrdata(250),
      I2 => mem_reg_0_15_18_23,
      O => \write_buffer.wr_buf_out_data_reg[503]_0\(19)
    );
\mem_reg_0_15_30_35_i_5__6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(250),
      I1 => phy_wrdata(250),
      I2 => mem_reg_0_15_18_23,
      O => \write_buffer.wr_buf_out_data_reg[511]_0\(19)
    );
mem_reg_0_15_30_35_i_6: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(131),
      I1 => phy_wrdata(187),
      I2 => mem_reg_0_15_66_71,
      O => \write_buffer.wr_buf_out_data_reg[455]_0\(26)
    );
\mem_reg_0_15_30_35_i_6__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(138),
      I1 => phy_wrdata(186),
      I2 => mem_reg_0_15_66_71,
      O => \write_buffer.wr_buf_out_data_reg[463]_0\(18)
    );
\mem_reg_0_15_30_35_i_6__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(146),
      I1 => phy_wrdata(186),
      I2 => mem_reg_0_15_66_71,
      O => \write_buffer.wr_buf_out_data_reg[471]_0\(18)
    );
\mem_reg_0_15_30_35_i_6__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(154),
      I1 => phy_wrdata(186),
      I2 => mem_reg_0_15_66_71,
      O => \write_buffer.wr_buf_out_data_reg[479]_0\(18)
    );
\mem_reg_0_15_30_35_i_6__3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(163),
      I1 => phy_wrdata(187),
      I2 => mem_reg_0_15_66_71,
      O => \write_buffer.wr_buf_out_data_reg[487]_0\(26)
    );
\mem_reg_0_15_30_35_i_6__4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(170),
      I1 => phy_wrdata(186),
      I2 => mem_reg_0_15_66_71,
      O => \write_buffer.wr_buf_out_data_reg[495]_0\(18)
    );
\mem_reg_0_15_30_35_i_6__5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(178),
      I1 => phy_wrdata(186),
      I2 => mem_reg_0_15_72_77,
      O => \write_buffer.wr_buf_out_data_reg[503]_0\(18)
    );
\mem_reg_0_15_30_35_i_6__6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(186),
      I1 => phy_wrdata(186),
      I2 => mem_reg_0_15_72_77,
      O => \write_buffer.wr_buf_out_data_reg[511]_0\(18)
    );
mem_reg_0_15_36_41_i_1: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mc_bank(5),
      I1 => phy_bank(11),
      I2 => mem_reg_0_15_36_41,
      O => phy_dout(5)
    );
\mem_reg_0_15_36_41_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(323),
      I1 => phy_wrdata(379),
      I2 => mem_reg_0_15_36_41_0,
      O => \write_buffer.wr_buf_out_data_reg[455]_0\(29)
    );
\mem_reg_0_15_36_41_i_1__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(330),
      I1 => phy_wrdata(378),
      I2 => mem_reg_0_15_36_41_0,
      O => \write_buffer.wr_buf_out_data_reg[463]_0\(21)
    );
\mem_reg_0_15_36_41_i_1__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(338),
      I1 => phy_wrdata(378),
      I2 => mem_reg_0_15_36_41_0,
      O => \write_buffer.wr_buf_out_data_reg[471]_0\(21)
    );
\mem_reg_0_15_36_41_i_1__3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(346),
      I1 => phy_wrdata(378),
      I2 => mem_reg_0_15_36_41_0,
      O => \write_buffer.wr_buf_out_data_reg[479]_0\(21)
    );
\mem_reg_0_15_36_41_i_1__4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(355),
      I1 => phy_wrdata(379),
      I2 => mem_reg_0_15_36_41_0,
      O => \write_buffer.wr_buf_out_data_reg[487]_0\(29)
    );
\mem_reg_0_15_36_41_i_1__5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(362),
      I1 => phy_wrdata(378),
      I2 => mem_reg_0_15_36_41_0,
      O => \write_buffer.wr_buf_out_data_reg[495]_0\(21)
    );
\mem_reg_0_15_36_41_i_1__6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(370),
      I1 => phy_wrdata(378),
      I2 => mem_reg_0_15_36_41_0,
      O => \write_buffer.wr_buf_out_data_reg[503]_0\(21)
    );
\mem_reg_0_15_36_41_i_1__7\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(378),
      I1 => phy_wrdata(378),
      I2 => mem_reg_0_15_36_41_1,
      O => \write_buffer.wr_buf_out_data_reg[511]_0\(21)
    );
\mem_reg_0_15_36_41_i_1__8\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => mc_cas_n(0),
      I1 => phy_ctl_wr_i1_reg,
      I2 => phy_cas_n(1),
      O => \cmd_pipe_plus.mc_cke_reg[3]_0\(2)
    );
mem_reg_0_15_36_41_i_2: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mc_bank(2),
      I1 => phy_bank(11),
      I2 => mem_reg_0_15_36_41,
      O => phy_dout(4)
    );
\mem_reg_0_15_36_41_i_2__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(259),
      I1 => phy_wrdata(315),
      I2 => mem_reg_0_15_18_23,
      O => \write_buffer.wr_buf_out_data_reg[455]_0\(28)
    );
\mem_reg_0_15_36_41_i_2__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(266),
      I1 => phy_wrdata(314),
      I2 => mem_reg_0_15_18_23,
      O => \write_buffer.wr_buf_out_data_reg[463]_0\(20)
    );
\mem_reg_0_15_36_41_i_2__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(274),
      I1 => phy_wrdata(314),
      I2 => mem_reg_0_15_18_23_0,
      O => \write_buffer.wr_buf_out_data_reg[471]_0\(20)
    );
\mem_reg_0_15_36_41_i_2__3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(282),
      I1 => phy_wrdata(314),
      I2 => mem_reg_0_15_18_23_0,
      O => \write_buffer.wr_buf_out_data_reg[479]_0\(20)
    );
\mem_reg_0_15_36_41_i_2__4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(291),
      I1 => phy_wrdata(315),
      I2 => mem_reg_0_15_18_23_0,
      O => \write_buffer.wr_buf_out_data_reg[487]_0\(28)
    );
\mem_reg_0_15_36_41_i_2__5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(298),
      I1 => phy_wrdata(314),
      I2 => mem_reg_0_15_18_23_0,
      O => \write_buffer.wr_buf_out_data_reg[495]_0\(20)
    );
\mem_reg_0_15_36_41_i_2__6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(306),
      I1 => phy_wrdata(314),
      I2 => mem_reg_0_15_18_23_0,
      O => \write_buffer.wr_buf_out_data_reg[503]_0\(20)
    );
\mem_reg_0_15_36_41_i_2__7\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(314),
      I1 => phy_wrdata(314),
      I2 => mem_reg_0_15_18_23_0,
      O => \write_buffer.wr_buf_out_data_reg[511]_0\(20)
    );
mem_reg_0_15_36_41_i_3: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(451),
      I1 => phy_wrdata(507),
      I2 => mem_reg_0_15_54_59_0,
      O => \write_buffer.wr_buf_out_data_reg[455]_0\(31)
    );
\mem_reg_0_15_36_41_i_3__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(458),
      I1 => phy_wrdata(506),
      I2 => mem_reg_0_15_54_59_0,
      O => \write_buffer.wr_buf_out_data_reg[463]_0\(23)
    );
\mem_reg_0_15_36_41_i_3__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(466),
      I1 => phy_wrdata(506),
      I2 => mem_reg_0_15_54_59_0,
      O => \write_buffer.wr_buf_out_data_reg[471]_0\(23)
    );
\mem_reg_0_15_36_41_i_3__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(474),
      I1 => phy_wrdata(506),
      I2 => mem_reg_0_15_78_79_0,
      O => \write_buffer.wr_buf_out_data_reg[479]_0\(23)
    );
\mem_reg_0_15_36_41_i_3__3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(483),
      I1 => phy_wrdata(507),
      I2 => mem_reg_0_15_78_79_0,
      O => \write_buffer.wr_buf_out_data_reg[487]_0\(31)
    );
\mem_reg_0_15_36_41_i_3__4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(490),
      I1 => phy_wrdata(506),
      I2 => mem_reg_0_15_78_79_0,
      O => \write_buffer.wr_buf_out_data_reg[495]_0\(23)
    );
\mem_reg_0_15_36_41_i_3__5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(498),
      I1 => phy_wrdata(506),
      I2 => mem_reg_0_15_78_79_0,
      O => \write_buffer.wr_buf_out_data_reg[503]_0\(23)
    );
\mem_reg_0_15_36_41_i_3__6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(506),
      I1 => phy_wrdata(506),
      I2 => mem_reg_0_15_78_79_0,
      O => \write_buffer.wr_buf_out_data_reg[511]_0\(23)
    );
mem_reg_0_15_36_41_i_4: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(387),
      I1 => phy_wrdata(443),
      I2 => mem_reg_0_15_36_41_1,
      O => \write_buffer.wr_buf_out_data_reg[455]_0\(30)
    );
\mem_reg_0_15_36_41_i_4__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(394),
      I1 => phy_wrdata(442),
      I2 => mem_reg_0_15_36_41_1,
      O => \write_buffer.wr_buf_out_data_reg[463]_0\(22)
    );
\mem_reg_0_15_36_41_i_4__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(402),
      I1 => phy_wrdata(442),
      I2 => mem_reg_0_15_36_41_1,
      O => \write_buffer.wr_buf_out_data_reg[471]_0\(22)
    );
\mem_reg_0_15_36_41_i_4__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(410),
      I1 => phy_wrdata(442),
      I2 => mem_reg_0_15_36_41_1,
      O => \write_buffer.wr_buf_out_data_reg[479]_0\(22)
    );
\mem_reg_0_15_36_41_i_4__3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(419),
      I1 => phy_wrdata(443),
      I2 => mem_reg_0_15_36_41_1,
      O => \write_buffer.wr_buf_out_data_reg[487]_0\(30)
    );
\mem_reg_0_15_36_41_i_4__4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(426),
      I1 => phy_wrdata(442),
      I2 => mem_reg_0_15_54_59_0,
      O => \write_buffer.wr_buf_out_data_reg[495]_0\(22)
    );
\mem_reg_0_15_36_41_i_4__5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(434),
      I1 => phy_wrdata(442),
      I2 => mem_reg_0_15_54_59_0,
      O => \write_buffer.wr_buf_out_data_reg[503]_0\(22)
    );
\mem_reg_0_15_36_41_i_4__6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(442),
      I1 => phy_wrdata(442),
      I2 => mem_reg_0_15_54_59_0,
      O => \write_buffer.wr_buf_out_data_reg[511]_0\(22)
    );
mem_reg_0_15_36_41_i_5: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(68),
      I1 => phy_wrdata(124),
      I2 => mem_reg_0_15_48_53,
      O => \write_buffer.wr_buf_out_data_reg[455]_0\(33)
    );
\mem_reg_0_15_36_41_i_5__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(75),
      I1 => phy_wrdata(123),
      I2 => mem_reg_0_15_48_53,
      O => \write_buffer.wr_buf_out_data_reg[463]_0\(25)
    );
\mem_reg_0_15_36_41_i_5__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(83),
      I1 => phy_wrdata(123),
      I2 => mem_reg_0_15_54_59,
      O => \write_buffer.wr_buf_out_data_reg[471]_0\(25)
    );
\mem_reg_0_15_36_41_i_5__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(91),
      I1 => phy_wrdata(123),
      I2 => mem_reg_0_15_54_59,
      O => \write_buffer.wr_buf_out_data_reg[479]_0\(25)
    );
\mem_reg_0_15_36_41_i_5__3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(100),
      I1 => phy_wrdata(124),
      I2 => mem_reg_0_15_54_59,
      O => \write_buffer.wr_buf_out_data_reg[487]_0\(33)
    );
\mem_reg_0_15_36_41_i_5__4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(107),
      I1 => phy_wrdata(123),
      I2 => mem_reg_0_15_54_59,
      O => \write_buffer.wr_buf_out_data_reg[495]_0\(25)
    );
\mem_reg_0_15_36_41_i_5__5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(115),
      I1 => phy_wrdata(123),
      I2 => mem_reg_0_15_54_59,
      O => \write_buffer.wr_buf_out_data_reg[503]_0\(25)
    );
\mem_reg_0_15_36_41_i_5__6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(123),
      I1 => phy_wrdata(123),
      I2 => mem_reg_0_15_54_59,
      O => \write_buffer.wr_buf_out_data_reg[511]_0\(25)
    );
mem_reg_0_15_36_41_i_6: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(4),
      I1 => phy_wrdata(60),
      I2 => mem_reg_0_15_36_41,
      O => \write_buffer.wr_buf_out_data_reg[455]_0\(32)
    );
\mem_reg_0_15_36_41_i_6__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(11),
      I1 => phy_wrdata(59),
      I2 => mem_reg_0_15_36_41,
      O => \write_buffer.wr_buf_out_data_reg[463]_0\(24)
    );
\mem_reg_0_15_36_41_i_6__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(19),
      I1 => phy_wrdata(59),
      I2 => mem_reg_0_15_36_41,
      O => \write_buffer.wr_buf_out_data_reg[471]_0\(24)
    );
\mem_reg_0_15_36_41_i_6__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(27),
      I1 => phy_wrdata(59),
      I2 => mem_reg_0_15_36_41,
      O => \write_buffer.wr_buf_out_data_reg[479]_0\(24)
    );
\mem_reg_0_15_36_41_i_6__3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(36),
      I1 => phy_wrdata(60),
      I2 => mem_reg_0_15_48_53,
      O => \write_buffer.wr_buf_out_data_reg[487]_0\(32)
    );
\mem_reg_0_15_36_41_i_6__4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(43),
      I1 => phy_wrdata(59),
      I2 => mem_reg_0_15_48_53,
      O => \write_buffer.wr_buf_out_data_reg[495]_0\(24)
    );
\mem_reg_0_15_36_41_i_6__5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(51),
      I1 => phy_wrdata(59),
      I2 => mem_reg_0_15_48_53,
      O => \write_buffer.wr_buf_out_data_reg[503]_0\(24)
    );
\mem_reg_0_15_36_41_i_6__6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(59),
      I1 => phy_wrdata(59),
      I2 => mem_reg_0_15_48_53,
      O => \write_buffer.wr_buf_out_data_reg[511]_0\(24)
    );
mem_reg_0_15_42_47_i_1: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(196),
      I1 => phy_wrdata(252),
      I2 => mem_reg_0_15_72_77,
      O => \write_buffer.wr_buf_out_data_reg[455]_0\(35)
    );
\mem_reg_0_15_42_47_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(203),
      I1 => phy_wrdata(251),
      I2 => mem_reg_0_15_72_77,
      O => \write_buffer.wr_buf_out_data_reg[463]_0\(27)
    );
\mem_reg_0_15_42_47_i_1__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(211),
      I1 => phy_wrdata(251),
      I2 => mem_reg_0_15_72_77,
      O => \write_buffer.wr_buf_out_data_reg[471]_0\(27)
    );
\mem_reg_0_15_42_47_i_1__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(219),
      I1 => phy_wrdata(251),
      I2 => mem_reg_0_15_72_77,
      O => \write_buffer.wr_buf_out_data_reg[479]_0\(27)
    );
\mem_reg_0_15_42_47_i_1__3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(228),
      I1 => phy_wrdata(252),
      I2 => mem_reg_0_15_18_23,
      O => \write_buffer.wr_buf_out_data_reg[487]_0\(35)
    );
\mem_reg_0_15_42_47_i_1__4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(235),
      I1 => phy_wrdata(251),
      I2 => mem_reg_0_15_18_23,
      O => \write_buffer.wr_buf_out_data_reg[495]_0\(27)
    );
\mem_reg_0_15_42_47_i_1__5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(243),
      I1 => phy_wrdata(251),
      I2 => mem_reg_0_15_18_23,
      O => \write_buffer.wr_buf_out_data_reg[503]_0\(27)
    );
\mem_reg_0_15_42_47_i_1__6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(251),
      I1 => phy_wrdata(251),
      I2 => mem_reg_0_15_18_23,
      O => \write_buffer.wr_buf_out_data_reg[511]_0\(27)
    );
\mem_reg_0_15_42_47_i_1__7\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => phy_bank(11),
      I1 => mem_reg_0_15_36_41,
      O => phy_dout(7)
    );
mem_reg_0_15_42_47_i_2: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mc_address(15),
      I1 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[3]\,
      I2 => \phy_ctl_wd_i1_reg[0]\,
      O => d_in(13)
    );
\mem_reg_0_15_42_47_i_2__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mc_bank(8),
      I1 => phy_bank(11),
      I2 => mem_reg_0_15_36_41,
      O => phy_dout(6)
    );
\mem_reg_0_15_42_47_i_2__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(132),
      I1 => phy_wrdata(188),
      I2 => mem_reg_0_15_66_71,
      O => \write_buffer.wr_buf_out_data_reg[455]_0\(34)
    );
\mem_reg_0_15_42_47_i_2__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(139),
      I1 => phy_wrdata(187),
      I2 => mem_reg_0_15_66_71,
      O => \write_buffer.wr_buf_out_data_reg[463]_0\(26)
    );
\mem_reg_0_15_42_47_i_2__3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(147),
      I1 => phy_wrdata(187),
      I2 => mem_reg_0_15_66_71,
      O => \write_buffer.wr_buf_out_data_reg[471]_0\(26)
    );
\mem_reg_0_15_42_47_i_2__4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(155),
      I1 => phy_wrdata(187),
      I2 => mem_reg_0_15_66_71,
      O => \write_buffer.wr_buf_out_data_reg[479]_0\(26)
    );
\mem_reg_0_15_42_47_i_2__5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(164),
      I1 => phy_wrdata(188),
      I2 => mem_reg_0_15_66_71,
      O => \write_buffer.wr_buf_out_data_reg[487]_0\(34)
    );
\mem_reg_0_15_42_47_i_2__6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(171),
      I1 => phy_wrdata(187),
      I2 => mem_reg_0_15_66_71,
      O => \write_buffer.wr_buf_out_data_reg[495]_0\(26)
    );
\mem_reg_0_15_42_47_i_2__7\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(179),
      I1 => phy_wrdata(187),
      I2 => mem_reg_0_15_72_77,
      O => \write_buffer.wr_buf_out_data_reg[503]_0\(26)
    );
\mem_reg_0_15_42_47_i_2__8\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(187),
      I1 => phy_wrdata(187),
      I2 => mem_reg_0_15_72_77,
      O => \write_buffer.wr_buf_out_data_reg[511]_0\(26)
    );
\mem_reg_0_15_42_47_i_2__9\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => mc_ras_n(0),
      I1 => phy_ctl_wr_i1_reg,
      I2 => phy_ras_n(1),
      O => \cmd_pipe_plus.mc_cke_reg[3]_0\(3)
    );
mem_reg_0_15_42_47_i_3: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mc_address(3),
      I1 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[3]\,
      I2 => \phy_ctl_wd_i1_reg[0]\,
      O => d_in(12)
    );
\mem_reg_0_15_42_47_i_3__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mc_bank(4),
      I1 => phy_bank(10),
      I2 => mem_reg_0_15_36_41,
      O => phy_dout(9)
    );
\mem_reg_0_15_42_47_i_3__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(324),
      I1 => phy_wrdata(380),
      I2 => mem_reg_0_15_36_41_0,
      O => \write_buffer.wr_buf_out_data_reg[455]_0\(37)
    );
\mem_reg_0_15_42_47_i_3__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(331),
      I1 => phy_wrdata(379),
      I2 => mem_reg_0_15_36_41_0,
      O => \write_buffer.wr_buf_out_data_reg[463]_0\(29)
    );
\mem_reg_0_15_42_47_i_3__3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(339),
      I1 => phy_wrdata(379),
      I2 => mem_reg_0_15_36_41_0,
      O => \write_buffer.wr_buf_out_data_reg[471]_0\(29)
    );
\mem_reg_0_15_42_47_i_3__4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(347),
      I1 => phy_wrdata(379),
      I2 => mem_reg_0_15_36_41_0,
      O => \write_buffer.wr_buf_out_data_reg[479]_0\(29)
    );
\mem_reg_0_15_42_47_i_3__5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(356),
      I1 => phy_wrdata(380),
      I2 => mem_reg_0_15_36_41_0,
      O => \write_buffer.wr_buf_out_data_reg[487]_0\(37)
    );
\mem_reg_0_15_42_47_i_3__6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(363),
      I1 => phy_wrdata(379),
      I2 => mem_reg_0_15_36_41_0,
      O => \write_buffer.wr_buf_out_data_reg[495]_0\(29)
    );
\mem_reg_0_15_42_47_i_3__7\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(371),
      I1 => phy_wrdata(379),
      I2 => mem_reg_0_15_36_41_1,
      O => \write_buffer.wr_buf_out_data_reg[503]_0\(29)
    );
\mem_reg_0_15_42_47_i_3__8\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(379),
      I1 => phy_wrdata(379),
      I2 => mem_reg_0_15_36_41_1,
      O => \write_buffer.wr_buf_out_data_reg[511]_0\(29)
    );
mem_reg_0_15_42_47_i_4: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mc_bank(1),
      I1 => phy_bank(10),
      I2 => mem_reg_0_15_36_41,
      O => phy_dout(8)
    );
\mem_reg_0_15_42_47_i_4__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(260),
      I1 => phy_wrdata(316),
      I2 => mem_reg_0_15_18_23,
      O => \write_buffer.wr_buf_out_data_reg[455]_0\(36)
    );
\mem_reg_0_15_42_47_i_4__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(267),
      I1 => phy_wrdata(315),
      I2 => mem_reg_0_15_18_23,
      O => \write_buffer.wr_buf_out_data_reg[463]_0\(28)
    );
\mem_reg_0_15_42_47_i_4__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(275),
      I1 => phy_wrdata(315),
      I2 => mem_reg_0_15_18_23_0,
      O => \write_buffer.wr_buf_out_data_reg[471]_0\(28)
    );
\mem_reg_0_15_42_47_i_4__3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(283),
      I1 => phy_wrdata(315),
      I2 => mem_reg_0_15_18_23_0,
      O => \write_buffer.wr_buf_out_data_reg[479]_0\(28)
    );
\mem_reg_0_15_42_47_i_4__4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(292),
      I1 => phy_wrdata(316),
      I2 => mem_reg_0_15_18_23_0,
      O => \write_buffer.wr_buf_out_data_reg[487]_0\(36)
    );
\mem_reg_0_15_42_47_i_4__5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(299),
      I1 => phy_wrdata(315),
      I2 => mem_reg_0_15_18_23_0,
      O => \write_buffer.wr_buf_out_data_reg[495]_0\(28)
    );
\mem_reg_0_15_42_47_i_4__6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(307),
      I1 => phy_wrdata(315),
      I2 => mem_reg_0_15_18_23_0,
      O => \write_buffer.wr_buf_out_data_reg[503]_0\(28)
    );
\mem_reg_0_15_42_47_i_4__7\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(315),
      I1 => phy_wrdata(315),
      I2 => mem_reg_0_15_18_23_0,
      O => \write_buffer.wr_buf_out_data_reg[511]_0\(28)
    );
\mem_reg_0_15_42_47_i_4__8\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[3]\,
      I1 => \phy_ctl_wd_i1_reg[0]\,
      O => d_in(15)
    );
mem_reg_0_15_42_47_i_5: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mc_address(26),
      I1 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[3]\,
      I2 => \phy_ctl_wd_i1_reg[0]\,
      O => d_in(14)
    );
\mem_reg_0_15_42_47_i_5__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(452),
      I1 => phy_wrdata(508),
      I2 => mem_reg_0_15_54_59_0,
      O => \write_buffer.wr_buf_out_data_reg[455]_0\(39)
    );
\mem_reg_0_15_42_47_i_5__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(459),
      I1 => phy_wrdata(507),
      I2 => mem_reg_0_15_54_59_0,
      O => \write_buffer.wr_buf_out_data_reg[463]_0\(31)
    );
\mem_reg_0_15_42_47_i_5__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(467),
      I1 => phy_wrdata(507),
      I2 => mem_reg_0_15_54_59_0,
      O => \write_buffer.wr_buf_out_data_reg[471]_0\(31)
    );
\mem_reg_0_15_42_47_i_5__3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(475),
      I1 => phy_wrdata(507),
      I2 => mem_reg_0_15_78_79_0,
      O => \write_buffer.wr_buf_out_data_reg[479]_0\(31)
    );
\mem_reg_0_15_42_47_i_5__4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(484),
      I1 => phy_wrdata(508),
      I2 => mem_reg_0_15_78_79_0,
      O => \write_buffer.wr_buf_out_data_reg[487]_0\(39)
    );
\mem_reg_0_15_42_47_i_5__5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(491),
      I1 => phy_wrdata(507),
      I2 => mem_reg_0_15_78_79_0,
      O => \write_buffer.wr_buf_out_data_reg[495]_0\(31)
    );
\mem_reg_0_15_42_47_i_5__6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(499),
      I1 => phy_wrdata(507),
      I2 => mem_reg_0_15_78_79_0,
      O => \write_buffer.wr_buf_out_data_reg[503]_0\(31)
    );
\mem_reg_0_15_42_47_i_5__7\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(507),
      I1 => phy_wrdata(507),
      I2 => mem_reg_0_15_78_79_0,
      O => \write_buffer.wr_buf_out_data_reg[511]_0\(31)
    );
\mem_reg_0_15_42_47_i_5__8\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => phy_bank(10),
      I1 => mem_reg_0_15_36_41,
      O => phy_dout(11)
    );
mem_reg_0_15_42_47_i_6: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mc_bank(7),
      I1 => phy_bank(10),
      I2 => mem_reg_0_15_36_41,
      O => phy_dout(10)
    );
\mem_reg_0_15_42_47_i_6__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(388),
      I1 => phy_wrdata(444),
      I2 => mem_reg_0_15_36_41_1,
      O => \write_buffer.wr_buf_out_data_reg[455]_0\(38)
    );
\mem_reg_0_15_42_47_i_6__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(395),
      I1 => phy_wrdata(443),
      I2 => mem_reg_0_15_36_41_1,
      O => \write_buffer.wr_buf_out_data_reg[463]_0\(30)
    );
\mem_reg_0_15_42_47_i_6__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(403),
      I1 => phy_wrdata(443),
      I2 => mem_reg_0_15_36_41_1,
      O => \write_buffer.wr_buf_out_data_reg[471]_0\(30)
    );
\mem_reg_0_15_42_47_i_6__3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(411),
      I1 => phy_wrdata(443),
      I2 => mem_reg_0_15_36_41_1,
      O => \write_buffer.wr_buf_out_data_reg[479]_0\(30)
    );
\mem_reg_0_15_42_47_i_6__4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(420),
      I1 => phy_wrdata(444),
      I2 => mem_reg_0_15_54_59_0,
      O => \write_buffer.wr_buf_out_data_reg[487]_0\(38)
    );
\mem_reg_0_15_42_47_i_6__5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(427),
      I1 => phy_wrdata(443),
      I2 => mem_reg_0_15_54_59_0,
      O => \write_buffer.wr_buf_out_data_reg[495]_0\(30)
    );
\mem_reg_0_15_42_47_i_6__6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(435),
      I1 => phy_wrdata(443),
      I2 => mem_reg_0_15_54_59_0,
      O => \write_buffer.wr_buf_out_data_reg[503]_0\(30)
    );
\mem_reg_0_15_42_47_i_6__7\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(443),
      I1 => phy_wrdata(443),
      I2 => mem_reg_0_15_54_59_0,
      O => \write_buffer.wr_buf_out_data_reg[511]_0\(30)
    );
mem_reg_0_15_48_53_i_1: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mc_ras_n(0),
      I1 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[12]\,
      I2 => \phy_ctl_wd_i1_reg[0]\,
      O => d_in(17)
    );
\mem_reg_0_15_48_53_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mc_bank(3),
      I1 => phy_bank(9),
      I2 => mem_reg_0_15_36_41,
      O => phy_dout(13)
    );
\mem_reg_0_15_48_53_i_1__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(69),
      I1 => phy_wrdata(125),
      I2 => mem_reg_0_15_48_53,
      O => \write_buffer.wr_buf_out_data_reg[455]_0\(41)
    );
\mem_reg_0_15_48_53_i_1__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(76),
      I1 => phy_wrdata(124),
      I2 => mem_reg_0_15_48_53,
      O => \write_buffer.wr_buf_out_data_reg[463]_0\(33)
    );
\mem_reg_0_15_48_53_i_1__3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(84),
      I1 => phy_wrdata(124),
      I2 => mem_reg_0_15_54_59,
      O => \write_buffer.wr_buf_out_data_reg[471]_0\(33)
    );
\mem_reg_0_15_48_53_i_1__4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(92),
      I1 => phy_wrdata(124),
      I2 => mem_reg_0_15_54_59,
      O => \write_buffer.wr_buf_out_data_reg[479]_0\(33)
    );
\mem_reg_0_15_48_53_i_1__5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(101),
      I1 => phy_wrdata(125),
      I2 => mem_reg_0_15_54_59,
      O => \write_buffer.wr_buf_out_data_reg[487]_0\(41)
    );
\mem_reg_0_15_48_53_i_1__6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(108),
      I1 => phy_wrdata(124),
      I2 => mem_reg_0_15_54_59,
      O => \write_buffer.wr_buf_out_data_reg[495]_0\(33)
    );
\mem_reg_0_15_48_53_i_1__7\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(116),
      I1 => phy_wrdata(124),
      I2 => mem_reg_0_15_54_59,
      O => \write_buffer.wr_buf_out_data_reg[503]_0\(33)
    );
\mem_reg_0_15_48_53_i_1__8\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(124),
      I1 => phy_wrdata(124),
      I2 => mem_reg_0_15_54_59,
      O => \write_buffer.wr_buf_out_data_reg[511]_0\(33)
    );
\mem_reg_0_15_48_53_i_1__9\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => mc_we_n(0),
      I1 => phy_ctl_wr_i1_reg,
      I2 => phy_we_n(1),
      O => \cmd_pipe_plus.mc_cke_reg[3]_0\(4)
    );
mem_reg_0_15_48_53_i_2: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mc_address(11),
      I1 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[12]\,
      I2 => \phy_ctl_wd_i1_reg[0]\,
      O => d_in(16)
    );
\mem_reg_0_15_48_53_i_2__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mc_bank(0),
      I1 => phy_bank(9),
      I2 => mem_reg_0_15_36_41,
      O => phy_dout(12)
    );
\mem_reg_0_15_48_53_i_2__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(5),
      I1 => phy_wrdata(61),
      I2 => mem_reg_0_15_36_41,
      O => \write_buffer.wr_buf_out_data_reg[455]_0\(40)
    );
\mem_reg_0_15_48_53_i_2__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(12),
      I1 => phy_wrdata(60),
      I2 => mem_reg_0_15_36_41,
      O => \write_buffer.wr_buf_out_data_reg[463]_0\(32)
    );
\mem_reg_0_15_48_53_i_2__3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(20),
      I1 => phy_wrdata(60),
      I2 => mem_reg_0_15_36_41,
      O => \write_buffer.wr_buf_out_data_reg[471]_0\(32)
    );
\mem_reg_0_15_48_53_i_2__4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(28),
      I1 => phy_wrdata(60),
      I2 => mem_reg_0_15_48_53,
      O => \write_buffer.wr_buf_out_data_reg[479]_0\(32)
    );
\mem_reg_0_15_48_53_i_2__5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(37),
      I1 => phy_wrdata(61),
      I2 => mem_reg_0_15_48_53,
      O => \write_buffer.wr_buf_out_data_reg[487]_0\(40)
    );
\mem_reg_0_15_48_53_i_2__6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(44),
      I1 => phy_wrdata(60),
      I2 => mem_reg_0_15_48_53,
      O => \write_buffer.wr_buf_out_data_reg[495]_0\(32)
    );
\mem_reg_0_15_48_53_i_2__7\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(52),
      I1 => phy_wrdata(60),
      I2 => mem_reg_0_15_48_53,
      O => \write_buffer.wr_buf_out_data_reg[503]_0\(32)
    );
\mem_reg_0_15_48_53_i_2__8\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(60),
      I1 => phy_wrdata(60),
      I2 => mem_reg_0_15_48_53,
      O => \write_buffer.wr_buf_out_data_reg[511]_0\(32)
    );
mem_reg_0_15_48_53_i_3: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(197),
      I1 => phy_wrdata(253),
      I2 => mem_reg_0_15_72_77,
      O => \write_buffer.wr_buf_out_data_reg[455]_0\(43)
    );
\mem_reg_0_15_48_53_i_3__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(204),
      I1 => phy_wrdata(252),
      I2 => mem_reg_0_15_72_77,
      O => \write_buffer.wr_buf_out_data_reg[463]_0\(35)
    );
\mem_reg_0_15_48_53_i_3__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(212),
      I1 => phy_wrdata(252),
      I2 => mem_reg_0_15_72_77,
      O => \write_buffer.wr_buf_out_data_reg[471]_0\(35)
    );
\mem_reg_0_15_48_53_i_3__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(220),
      I1 => phy_wrdata(252),
      I2 => mem_reg_0_15_72_77,
      O => \write_buffer.wr_buf_out_data_reg[479]_0\(35)
    );
\mem_reg_0_15_48_53_i_3__3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(229),
      I1 => phy_wrdata(253),
      I2 => mem_reg_0_15_18_23,
      O => \write_buffer.wr_buf_out_data_reg[487]_0\(43)
    );
\mem_reg_0_15_48_53_i_3__4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(236),
      I1 => phy_wrdata(252),
      I2 => mem_reg_0_15_18_23,
      O => \write_buffer.wr_buf_out_data_reg[495]_0\(35)
    );
\mem_reg_0_15_48_53_i_3__5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(244),
      I1 => phy_wrdata(252),
      I2 => mem_reg_0_15_18_23,
      O => \write_buffer.wr_buf_out_data_reg[503]_0\(35)
    );
\mem_reg_0_15_48_53_i_3__6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(252),
      I1 => phy_wrdata(252),
      I2 => mem_reg_0_15_18_23,
      O => \write_buffer.wr_buf_out_data_reg[511]_0\(35)
    );
\mem_reg_0_15_48_53_i_3__7\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[12]\,
      I1 => mem_reg_0_15_36_41,
      O => d_in(19)
    );
mem_reg_0_15_48_53_i_4: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mc_address(34),
      I1 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[12]\,
      I2 => \phy_ctl_wd_i1_reg[0]\,
      O => d_in(18)
    );
\mem_reg_0_15_48_53_i_4__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(133),
      I1 => phy_wrdata(189),
      I2 => mem_reg_0_15_66_71,
      O => \write_buffer.wr_buf_out_data_reg[455]_0\(42)
    );
\mem_reg_0_15_48_53_i_4__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(140),
      I1 => phy_wrdata(188),
      I2 => mem_reg_0_15_66_71,
      O => \write_buffer.wr_buf_out_data_reg[463]_0\(34)
    );
\mem_reg_0_15_48_53_i_4__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(148),
      I1 => phy_wrdata(188),
      I2 => mem_reg_0_15_66_71,
      O => \write_buffer.wr_buf_out_data_reg[471]_0\(34)
    );
\mem_reg_0_15_48_53_i_4__3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(156),
      I1 => phy_wrdata(188),
      I2 => mem_reg_0_15_66_71,
      O => \write_buffer.wr_buf_out_data_reg[479]_0\(34)
    );
\mem_reg_0_15_48_53_i_4__4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(165),
      I1 => phy_wrdata(189),
      I2 => mem_reg_0_15_66_71,
      O => \write_buffer.wr_buf_out_data_reg[487]_0\(42)
    );
\mem_reg_0_15_48_53_i_4__5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(172),
      I1 => phy_wrdata(188),
      I2 => mem_reg_0_15_66_71,
      O => \write_buffer.wr_buf_out_data_reg[495]_0\(34)
    );
\mem_reg_0_15_48_53_i_4__6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(180),
      I1 => phy_wrdata(188),
      I2 => mem_reg_0_15_72_77,
      O => \write_buffer.wr_buf_out_data_reg[503]_0\(34)
    );
\mem_reg_0_15_48_53_i_4__7\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(188),
      I1 => phy_wrdata(188),
      I2 => mem_reg_0_15_72_77,
      O => \write_buffer.wr_buf_out_data_reg[511]_0\(34)
    );
mem_reg_0_15_48_53_i_5: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mc_address(12),
      I1 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[0]\,
      I2 => \phy_ctl_wd_i1_reg[0]\,
      O => d_in(21)
    );
\mem_reg_0_15_48_53_i_5__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(325),
      I1 => phy_wrdata(381),
      I2 => mem_reg_0_15_36_41_0,
      O => \write_buffer.wr_buf_out_data_reg[455]_0\(45)
    );
\mem_reg_0_15_48_53_i_5__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(332),
      I1 => phy_wrdata(380),
      I2 => mem_reg_0_15_36_41_0,
      O => \write_buffer.wr_buf_out_data_reg[463]_0\(37)
    );
\mem_reg_0_15_48_53_i_5__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(340),
      I1 => phy_wrdata(380),
      I2 => mem_reg_0_15_36_41_0,
      O => \write_buffer.wr_buf_out_data_reg[471]_0\(37)
    );
\mem_reg_0_15_48_53_i_5__3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(348),
      I1 => phy_wrdata(380),
      I2 => mem_reg_0_15_36_41_0,
      O => \write_buffer.wr_buf_out_data_reg[479]_0\(37)
    );
\mem_reg_0_15_48_53_i_5__4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(357),
      I1 => phy_wrdata(381),
      I2 => mem_reg_0_15_36_41_0,
      O => \write_buffer.wr_buf_out_data_reg[487]_0\(45)
    );
\mem_reg_0_15_48_53_i_5__5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(364),
      I1 => phy_wrdata(380),
      I2 => mem_reg_0_15_36_41_0,
      O => \write_buffer.wr_buf_out_data_reg[495]_0\(37)
    );
\mem_reg_0_15_48_53_i_5__6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(372),
      I1 => phy_wrdata(380),
      I2 => mem_reg_0_15_36_41_1,
      O => \write_buffer.wr_buf_out_data_reg[503]_0\(37)
    );
\mem_reg_0_15_48_53_i_5__7\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(380),
      I1 => phy_wrdata(380),
      I2 => mem_reg_0_15_36_41_1,
      O => \write_buffer.wr_buf_out_data_reg[511]_0\(37)
    );
mem_reg_0_15_48_53_i_6: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mc_address(0),
      I1 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[0]\,
      I2 => \phy_ctl_wd_i1_reg[0]\,
      O => d_in(20)
    );
\mem_reg_0_15_48_53_i_6__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(261),
      I1 => phy_wrdata(317),
      I2 => mem_reg_0_15_18_23,
      O => \write_buffer.wr_buf_out_data_reg[455]_0\(44)
    );
\mem_reg_0_15_48_53_i_6__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(268),
      I1 => phy_wrdata(316),
      I2 => mem_reg_0_15_18_23,
      O => \write_buffer.wr_buf_out_data_reg[463]_0\(36)
    );
\mem_reg_0_15_48_53_i_6__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(276),
      I1 => phy_wrdata(316),
      I2 => mem_reg_0_15_18_23_0,
      O => \write_buffer.wr_buf_out_data_reg[471]_0\(36)
    );
\mem_reg_0_15_48_53_i_6__3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(284),
      I1 => phy_wrdata(316),
      I2 => mem_reg_0_15_18_23_0,
      O => \write_buffer.wr_buf_out_data_reg[479]_0\(36)
    );
\mem_reg_0_15_48_53_i_6__4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(293),
      I1 => phy_wrdata(317),
      I2 => mem_reg_0_15_18_23_0,
      O => \write_buffer.wr_buf_out_data_reg[487]_0\(44)
    );
\mem_reg_0_15_48_53_i_6__5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(300),
      I1 => phy_wrdata(316),
      I2 => mem_reg_0_15_18_23_0,
      O => \write_buffer.wr_buf_out_data_reg[495]_0\(36)
    );
\mem_reg_0_15_48_53_i_6__6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(308),
      I1 => phy_wrdata(316),
      I2 => mem_reg_0_15_18_23_0,
      O => \write_buffer.wr_buf_out_data_reg[503]_0\(36)
    );
\mem_reg_0_15_48_53_i_6__7\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(316),
      I1 => phy_wrdata(316),
      I2 => mem_reg_0_15_18_23_0,
      O => \write_buffer.wr_buf_out_data_reg[511]_0\(36)
    );
mem_reg_0_15_54_59_i_1: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(453),
      I1 => phy_wrdata(509),
      I2 => mem_reg_0_15_54_59_0,
      O => \write_buffer.wr_buf_out_data_reg[455]_0\(47)
    );
\mem_reg_0_15_54_59_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(460),
      I1 => phy_wrdata(508),
      I2 => mem_reg_0_15_54_59_0,
      O => \write_buffer.wr_buf_out_data_reg[463]_0\(39)
    );
\mem_reg_0_15_54_59_i_1__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(468),
      I1 => phy_wrdata(508),
      I2 => mem_reg_0_15_54_59_0,
      O => \write_buffer.wr_buf_out_data_reg[471]_0\(39)
    );
\mem_reg_0_15_54_59_i_1__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(476),
      I1 => phy_wrdata(508),
      I2 => mem_reg_0_15_78_79_0,
      O => \write_buffer.wr_buf_out_data_reg[479]_0\(39)
    );
\mem_reg_0_15_54_59_i_1__3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(485),
      I1 => phy_wrdata(509),
      I2 => mem_reg_0_15_78_79_0,
      O => \write_buffer.wr_buf_out_data_reg[487]_0\(47)
    );
\mem_reg_0_15_54_59_i_1__4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(492),
      I1 => phy_wrdata(508),
      I2 => mem_reg_0_15_78_79_0,
      O => \write_buffer.wr_buf_out_data_reg[495]_0\(39)
    );
\mem_reg_0_15_54_59_i_1__5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(500),
      I1 => phy_wrdata(508),
      I2 => mem_reg_0_15_78_79_0,
      O => \write_buffer.wr_buf_out_data_reg[503]_0\(39)
    );
\mem_reg_0_15_54_59_i_1__6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(508),
      I1 => phy_wrdata(508),
      I2 => mem_reg_0_15_78_79_0,
      O => \write_buffer.wr_buf_out_data_reg[511]_0\(39)
    );
\mem_reg_0_15_54_59_i_1__7\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[0]\,
      I1 => \phy_ctl_wd_i1_reg[0]\,
      O => d_in(23)
    );
\mem_reg_0_15_54_59_i_1__8\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => phy_bank(9),
      I1 => mem_reg_0_15_36_41,
      O => phy_dout(15)
    );
mem_reg_0_15_54_59_i_2: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mc_address(23),
      I1 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[0]\,
      I2 => \phy_ctl_wd_i1_reg[0]\,
      O => d_in(22)
    );
\mem_reg_0_15_54_59_i_2__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mc_bank(6),
      I1 => phy_bank(9),
      I2 => mem_reg_0_15_36_41,
      O => phy_dout(14)
    );
\mem_reg_0_15_54_59_i_2__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(389),
      I1 => phy_wrdata(445),
      I2 => mem_reg_0_15_36_41_1,
      O => \write_buffer.wr_buf_out_data_reg[455]_0\(46)
    );
\mem_reg_0_15_54_59_i_2__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(396),
      I1 => phy_wrdata(444),
      I2 => mem_reg_0_15_36_41_1,
      O => \write_buffer.wr_buf_out_data_reg[463]_0\(38)
    );
\mem_reg_0_15_54_59_i_2__3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(404),
      I1 => phy_wrdata(444),
      I2 => mem_reg_0_15_36_41_1,
      O => \write_buffer.wr_buf_out_data_reg[471]_0\(38)
    );
\mem_reg_0_15_54_59_i_2__4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(412),
      I1 => phy_wrdata(444),
      I2 => mem_reg_0_15_36_41_1,
      O => \write_buffer.wr_buf_out_data_reg[479]_0\(38)
    );
\mem_reg_0_15_54_59_i_2__5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(421),
      I1 => phy_wrdata(445),
      I2 => mem_reg_0_15_54_59_0,
      O => \write_buffer.wr_buf_out_data_reg[487]_0\(46)
    );
\mem_reg_0_15_54_59_i_2__6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(428),
      I1 => phy_wrdata(444),
      I2 => mem_reg_0_15_54_59_0,
      O => \write_buffer.wr_buf_out_data_reg[495]_0\(38)
    );
\mem_reg_0_15_54_59_i_2__7\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(436),
      I1 => phy_wrdata(444),
      I2 => mem_reg_0_15_54_59_0,
      O => \write_buffer.wr_buf_out_data_reg[503]_0\(38)
    );
\mem_reg_0_15_54_59_i_2__8\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(444),
      I1 => phy_wrdata(444),
      I2 => mem_reg_0_15_54_59_0,
      O => \write_buffer.wr_buf_out_data_reg[511]_0\(38)
    );
\mem_reg_0_15_54_59_i_2__9\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => mc_cke(0),
      I1 => phy_ctl_wr_i1_reg,
      I2 => calib_cke(3),
      O => \cmd_pipe_plus.mc_cke_reg[3]_0\(5)
    );
mem_reg_0_15_54_59_i_3: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mc_address(17),
      I1 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[5]\,
      I2 => \phy_ctl_wd_i1_reg[0]\,
      O => d_in(25)
    );
\mem_reg_0_15_54_59_i_3__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(70),
      I1 => phy_wrdata(126),
      I2 => mem_reg_0_15_48_53,
      O => \write_buffer.wr_buf_out_data_reg[455]_0\(49)
    );
\mem_reg_0_15_54_59_i_3__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(77),
      I1 => phy_wrdata(125),
      I2 => mem_reg_0_15_54_59,
      O => \write_buffer.wr_buf_out_data_reg[463]_0\(41)
    );
\mem_reg_0_15_54_59_i_3__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(85),
      I1 => phy_wrdata(125),
      I2 => mem_reg_0_15_54_59,
      O => \write_buffer.wr_buf_out_data_reg[471]_0\(41)
    );
\mem_reg_0_15_54_59_i_3__3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(93),
      I1 => phy_wrdata(125),
      I2 => mem_reg_0_15_54_59,
      O => \write_buffer.wr_buf_out_data_reg[479]_0\(41)
    );
\mem_reg_0_15_54_59_i_3__4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(102),
      I1 => phy_wrdata(126),
      I2 => mem_reg_0_15_54_59,
      O => \write_buffer.wr_buf_out_data_reg[487]_0\(49)
    );
\mem_reg_0_15_54_59_i_3__5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(109),
      I1 => phy_wrdata(125),
      I2 => mem_reg_0_15_54_59,
      O => \write_buffer.wr_buf_out_data_reg[495]_0\(41)
    );
\mem_reg_0_15_54_59_i_3__6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(117),
      I1 => phy_wrdata(125),
      I2 => mem_reg_0_15_54_59,
      O => \write_buffer.wr_buf_out_data_reg[503]_0\(41)
    );
\mem_reg_0_15_54_59_i_3__7\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(125),
      I1 => phy_wrdata(125),
      I2 => mem_reg_0_15_54_59,
      O => \write_buffer.wr_buf_out_data_reg[511]_0\(41)
    );
mem_reg_0_15_54_59_i_4: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mc_address(5),
      I1 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[5]\,
      I2 => \phy_ctl_wd_i1_reg[0]\,
      O => d_in(24)
    );
\mem_reg_0_15_54_59_i_4__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(6),
      I1 => phy_wrdata(62),
      I2 => mem_reg_0_15_36_41,
      O => \write_buffer.wr_buf_out_data_reg[455]_0\(48)
    );
\mem_reg_0_15_54_59_i_4__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(13),
      I1 => phy_wrdata(61),
      I2 => mem_reg_0_15_36_41,
      O => \write_buffer.wr_buf_out_data_reg[463]_0\(40)
    );
\mem_reg_0_15_54_59_i_4__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(21),
      I1 => phy_wrdata(61),
      I2 => mem_reg_0_15_36_41,
      O => \write_buffer.wr_buf_out_data_reg[471]_0\(40)
    );
\mem_reg_0_15_54_59_i_4__3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(29),
      I1 => phy_wrdata(61),
      I2 => mem_reg_0_15_48_53,
      O => \write_buffer.wr_buf_out_data_reg[479]_0\(40)
    );
\mem_reg_0_15_54_59_i_4__4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(38),
      I1 => phy_wrdata(62),
      I2 => mem_reg_0_15_48_53,
      O => \write_buffer.wr_buf_out_data_reg[487]_0\(48)
    );
\mem_reg_0_15_54_59_i_4__5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(45),
      I1 => phy_wrdata(61),
      I2 => mem_reg_0_15_48_53,
      O => \write_buffer.wr_buf_out_data_reg[495]_0\(40)
    );
\mem_reg_0_15_54_59_i_4__6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(53),
      I1 => phy_wrdata(61),
      I2 => mem_reg_0_15_48_53,
      O => \write_buffer.wr_buf_out_data_reg[503]_0\(40)
    );
\mem_reg_0_15_54_59_i_4__7\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(61),
      I1 => phy_wrdata(61),
      I2 => mem_reg_0_15_48_53,
      O => \write_buffer.wr_buf_out_data_reg[511]_0\(40)
    );
mem_reg_0_15_54_59_i_5: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(198),
      I1 => phy_wrdata(254),
      I2 => mem_reg_0_15_72_77,
      O => \write_buffer.wr_buf_out_data_reg[455]_0\(51)
    );
\mem_reg_0_15_54_59_i_5__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(205),
      I1 => phy_wrdata(253),
      I2 => mem_reg_0_15_72_77,
      O => \write_buffer.wr_buf_out_data_reg[463]_0\(43)
    );
\mem_reg_0_15_54_59_i_5__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(213),
      I1 => phy_wrdata(253),
      I2 => mem_reg_0_15_72_77,
      O => \write_buffer.wr_buf_out_data_reg[471]_0\(43)
    );
\mem_reg_0_15_54_59_i_5__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(221),
      I1 => phy_wrdata(253),
      I2 => mem_reg_0_15_72_77,
      O => \write_buffer.wr_buf_out_data_reg[479]_0\(43)
    );
\mem_reg_0_15_54_59_i_5__3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(230),
      I1 => phy_wrdata(254),
      I2 => mem_reg_0_15_18_23,
      O => \write_buffer.wr_buf_out_data_reg[487]_0\(51)
    );
\mem_reg_0_15_54_59_i_5__4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(237),
      I1 => phy_wrdata(253),
      I2 => mem_reg_0_15_18_23,
      O => \write_buffer.wr_buf_out_data_reg[495]_0\(43)
    );
\mem_reg_0_15_54_59_i_5__5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(245),
      I1 => phy_wrdata(253),
      I2 => mem_reg_0_15_18_23,
      O => \write_buffer.wr_buf_out_data_reg[503]_0\(43)
    );
\mem_reg_0_15_54_59_i_5__6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(253),
      I1 => phy_wrdata(253),
      I2 => mem_reg_0_15_18_23,
      O => \write_buffer.wr_buf_out_data_reg[511]_0\(43)
    );
\mem_reg_0_15_54_59_i_5__7\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[5]\,
      I1 => mem_reg_0_15_36_41,
      O => d_in(27)
    );
mem_reg_0_15_54_59_i_6: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mc_address(28),
      I1 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[5]\,
      I2 => \phy_ctl_wd_i1_reg[0]\,
      O => d_in(26)
    );
\mem_reg_0_15_54_59_i_6__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(134),
      I1 => phy_wrdata(190),
      I2 => mem_reg_0_15_66_71,
      O => \write_buffer.wr_buf_out_data_reg[455]_0\(50)
    );
\mem_reg_0_15_54_59_i_6__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(141),
      I1 => phy_wrdata(189),
      I2 => mem_reg_0_15_66_71,
      O => \write_buffer.wr_buf_out_data_reg[463]_0\(42)
    );
\mem_reg_0_15_54_59_i_6__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(149),
      I1 => phy_wrdata(189),
      I2 => mem_reg_0_15_66_71,
      O => \write_buffer.wr_buf_out_data_reg[471]_0\(42)
    );
\mem_reg_0_15_54_59_i_6__3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(157),
      I1 => phy_wrdata(189),
      I2 => mem_reg_0_15_66_71,
      O => \write_buffer.wr_buf_out_data_reg[479]_0\(42)
    );
\mem_reg_0_15_54_59_i_6__4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(166),
      I1 => phy_wrdata(190),
      I2 => mem_reg_0_15_66_71,
      O => \write_buffer.wr_buf_out_data_reg[487]_0\(50)
    );
\mem_reg_0_15_54_59_i_6__5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(173),
      I1 => phy_wrdata(189),
      I2 => mem_reg_0_15_66_71,
      O => \write_buffer.wr_buf_out_data_reg[495]_0\(42)
    );
\mem_reg_0_15_54_59_i_6__6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(181),
      I1 => phy_wrdata(189),
      I2 => mem_reg_0_15_72_77,
      O => \write_buffer.wr_buf_out_data_reg[503]_0\(42)
    );
\mem_reg_0_15_54_59_i_6__7\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(189),
      I1 => phy_wrdata(189),
      I2 => mem_reg_0_15_72_77,
      O => \write_buffer.wr_buf_out_data_reg[511]_0\(42)
    );
mem_reg_0_15_60_65_i_1: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mc_address(13),
      I1 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[1]\,
      I2 => \phy_ctl_wd_i1_reg[0]\,
      O => d_in(29)
    );
\mem_reg_0_15_60_65_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mc_address(14),
      I1 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[2]\,
      I2 => \phy_ctl_wd_i1_reg[0]\,
      O => phy_dout(17)
    );
\mem_reg_0_15_60_65_i_1__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(326),
      I1 => phy_wrdata(382),
      I2 => mem_reg_0_15_36_41_0,
      O => \write_buffer.wr_buf_out_data_reg[455]_0\(53)
    );
\mem_reg_0_15_60_65_i_1__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(333),
      I1 => phy_wrdata(381),
      I2 => mem_reg_0_15_36_41_0,
      O => \write_buffer.wr_buf_out_data_reg[463]_0\(45)
    );
\mem_reg_0_15_60_65_i_1__3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(341),
      I1 => phy_wrdata(381),
      I2 => mem_reg_0_15_36_41_0,
      O => \write_buffer.wr_buf_out_data_reg[471]_0\(45)
    );
\mem_reg_0_15_60_65_i_1__4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(349),
      I1 => phy_wrdata(381),
      I2 => mem_reg_0_15_36_41_0,
      O => \write_buffer.wr_buf_out_data_reg[479]_0\(45)
    );
\mem_reg_0_15_60_65_i_1__5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(358),
      I1 => phy_wrdata(382),
      I2 => mem_reg_0_15_36_41_0,
      O => \write_buffer.wr_buf_out_data_reg[487]_0\(53)
    );
\mem_reg_0_15_60_65_i_1__6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(365),
      I1 => phy_wrdata(381),
      I2 => mem_reg_0_15_36_41_0,
      O => \write_buffer.wr_buf_out_data_reg[495]_0\(45)
    );
\mem_reg_0_15_60_65_i_1__7\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(373),
      I1 => phy_wrdata(381),
      I2 => mem_reg_0_15_36_41_1,
      O => \write_buffer.wr_buf_out_data_reg[503]_0\(45)
    );
\mem_reg_0_15_60_65_i_1__8\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(381),
      I1 => phy_wrdata(381),
      I2 => mem_reg_0_15_36_41_1,
      O => \write_buffer.wr_buf_out_data_reg[511]_0\(45)
    );
mem_reg_0_15_60_65_i_2: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mc_address(1),
      I1 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[1]\,
      I2 => \phy_ctl_wd_i1_reg[0]\,
      O => d_in(28)
    );
\mem_reg_0_15_60_65_i_2__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mc_address(2),
      I1 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[2]\,
      I2 => \phy_ctl_wd_i1_reg[0]\,
      O => phy_dout(16)
    );
\mem_reg_0_15_60_65_i_2__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(262),
      I1 => phy_wrdata(318),
      I2 => mem_reg_0_15_18_23,
      O => \write_buffer.wr_buf_out_data_reg[455]_0\(52)
    );
\mem_reg_0_15_60_65_i_2__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(269),
      I1 => phy_wrdata(317),
      I2 => mem_reg_0_15_18_23,
      O => \write_buffer.wr_buf_out_data_reg[463]_0\(44)
    );
\mem_reg_0_15_60_65_i_2__3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(277),
      I1 => phy_wrdata(317),
      I2 => mem_reg_0_15_18_23_0,
      O => \write_buffer.wr_buf_out_data_reg[471]_0\(44)
    );
\mem_reg_0_15_60_65_i_2__4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(285),
      I1 => phy_wrdata(317),
      I2 => mem_reg_0_15_18_23_0,
      O => \write_buffer.wr_buf_out_data_reg[479]_0\(44)
    );
\mem_reg_0_15_60_65_i_2__5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(294),
      I1 => phy_wrdata(318),
      I2 => mem_reg_0_15_18_23_0,
      O => \write_buffer.wr_buf_out_data_reg[487]_0\(52)
    );
\mem_reg_0_15_60_65_i_2__6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(301),
      I1 => phy_wrdata(317),
      I2 => mem_reg_0_15_18_23_0,
      O => \write_buffer.wr_buf_out_data_reg[495]_0\(44)
    );
\mem_reg_0_15_60_65_i_2__7\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(309),
      I1 => phy_wrdata(317),
      I2 => mem_reg_0_15_18_23_0,
      O => \write_buffer.wr_buf_out_data_reg[503]_0\(44)
    );
\mem_reg_0_15_60_65_i_2__8\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(317),
      I1 => phy_wrdata(317),
      I2 => mem_reg_0_15_18_23_0,
      O => \write_buffer.wr_buf_out_data_reg[511]_0\(44)
    );
mem_reg_0_15_60_65_i_3: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(454),
      I1 => phy_wrdata(510),
      I2 => mem_reg_0_15_54_59_0,
      O => \write_buffer.wr_buf_out_data_reg[455]_0\(55)
    );
\mem_reg_0_15_60_65_i_3__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(461),
      I1 => phy_wrdata(509),
      I2 => mem_reg_0_15_54_59_0,
      O => \write_buffer.wr_buf_out_data_reg[463]_0\(47)
    );
\mem_reg_0_15_60_65_i_3__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(469),
      I1 => phy_wrdata(509),
      I2 => mem_reg_0_15_78_79_0,
      O => \write_buffer.wr_buf_out_data_reg[471]_0\(47)
    );
\mem_reg_0_15_60_65_i_3__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(477),
      I1 => phy_wrdata(509),
      I2 => mem_reg_0_15_78_79_0,
      O => \write_buffer.wr_buf_out_data_reg[479]_0\(47)
    );
\mem_reg_0_15_60_65_i_3__3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(486),
      I1 => phy_wrdata(510),
      I2 => mem_reg_0_15_78_79_0,
      O => \write_buffer.wr_buf_out_data_reg[487]_0\(55)
    );
\mem_reg_0_15_60_65_i_3__4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(493),
      I1 => phy_wrdata(509),
      I2 => mem_reg_0_15_78_79_0,
      O => \write_buffer.wr_buf_out_data_reg[495]_0\(47)
    );
\mem_reg_0_15_60_65_i_3__5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(501),
      I1 => phy_wrdata(509),
      I2 => mem_reg_0_15_78_79_0,
      O => \write_buffer.wr_buf_out_data_reg[503]_0\(47)
    );
\mem_reg_0_15_60_65_i_3__6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(509),
      I1 => phy_wrdata(509),
      I2 => mem_reg_0_15_78_79_0,
      O => \write_buffer.wr_buf_out_data_reg[511]_0\(47)
    );
mem_reg_0_15_60_65_i_4: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(390),
      I1 => phy_wrdata(446),
      I2 => mem_reg_0_15_36_41_1,
      O => \write_buffer.wr_buf_out_data_reg[455]_0\(54)
    );
\mem_reg_0_15_60_65_i_4__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(397),
      I1 => phy_wrdata(445),
      I2 => mem_reg_0_15_36_41_1,
      O => \write_buffer.wr_buf_out_data_reg[463]_0\(46)
    );
\mem_reg_0_15_60_65_i_4__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(405),
      I1 => phy_wrdata(445),
      I2 => mem_reg_0_15_36_41_1,
      O => \write_buffer.wr_buf_out_data_reg[471]_0\(46)
    );
\mem_reg_0_15_60_65_i_4__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(413),
      I1 => phy_wrdata(445),
      I2 => mem_reg_0_15_36_41_1,
      O => \write_buffer.wr_buf_out_data_reg[479]_0\(46)
    );
\mem_reg_0_15_60_65_i_4__3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(422),
      I1 => phy_wrdata(446),
      I2 => mem_reg_0_15_54_59_0,
      O => \write_buffer.wr_buf_out_data_reg[487]_0\(54)
    );
\mem_reg_0_15_60_65_i_4__4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(429),
      I1 => phy_wrdata(445),
      I2 => mem_reg_0_15_54_59_0,
      O => \write_buffer.wr_buf_out_data_reg[495]_0\(46)
    );
\mem_reg_0_15_60_65_i_4__5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(437),
      I1 => phy_wrdata(445),
      I2 => mem_reg_0_15_54_59_0,
      O => \write_buffer.wr_buf_out_data_reg[503]_0\(46)
    );
\mem_reg_0_15_60_65_i_4__6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(445),
      I1 => phy_wrdata(445),
      I2 => mem_reg_0_15_54_59_0,
      O => \write_buffer.wr_buf_out_data_reg[511]_0\(46)
    );
mem_reg_0_15_60_65_i_5: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(78),
      I1 => phy_wrdata(126),
      I2 => mem_reg_0_15_54_59,
      O => \write_buffer.wr_buf_out_data_reg[463]_0\(49)
    );
\mem_reg_0_15_60_65_i_5__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(86),
      I1 => phy_wrdata(126),
      I2 => mem_reg_0_15_54_59,
      O => \write_buffer.wr_buf_out_data_reg[471]_0\(49)
    );
\mem_reg_0_15_60_65_i_5__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(94),
      I1 => phy_wrdata(126),
      I2 => mem_reg_0_15_54_59,
      O => \write_buffer.wr_buf_out_data_reg[479]_0\(49)
    );
\mem_reg_0_15_60_65_i_5__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(110),
      I1 => phy_wrdata(126),
      I2 => mem_reg_0_15_54_59,
      O => \write_buffer.wr_buf_out_data_reg[495]_0\(49)
    );
\mem_reg_0_15_60_65_i_5__3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(118),
      I1 => phy_wrdata(126),
      I2 => mem_reg_0_15_54_59,
      O => \write_buffer.wr_buf_out_data_reg[503]_0\(49)
    );
\mem_reg_0_15_60_65_i_5__4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(126),
      I1 => phy_wrdata(126),
      I2 => mem_reg_0_15_66_71,
      O => \write_buffer.wr_buf_out_data_reg[511]_0\(49)
    );
mem_reg_0_15_60_65_i_6: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(14),
      I1 => phy_wrdata(62),
      I2 => mem_reg_0_15_36_41,
      O => \write_buffer.wr_buf_out_data_reg[463]_0\(48)
    );
\mem_reg_0_15_60_65_i_6__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(22),
      I1 => phy_wrdata(62),
      I2 => mem_reg_0_15_36_41,
      O => \write_buffer.wr_buf_out_data_reg[471]_0\(48)
    );
\mem_reg_0_15_60_65_i_6__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(30),
      I1 => phy_wrdata(62),
      I2 => mem_reg_0_15_48_53,
      O => \write_buffer.wr_buf_out_data_reg[479]_0\(48)
    );
\mem_reg_0_15_60_65_i_6__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(46),
      I1 => phy_wrdata(62),
      I2 => mem_reg_0_15_48_53,
      O => \write_buffer.wr_buf_out_data_reg[495]_0\(48)
    );
\mem_reg_0_15_60_65_i_6__3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(54),
      I1 => phy_wrdata(62),
      I2 => mem_reg_0_15_48_53,
      O => \write_buffer.wr_buf_out_data_reg[503]_0\(48)
    );
\mem_reg_0_15_60_65_i_6__4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(62),
      I1 => phy_wrdata(62),
      I2 => mem_reg_0_15_48_53,
      O => \write_buffer.wr_buf_out_data_reg[511]_0\(48)
    );
mem_reg_0_15_66_71_i_1: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(206),
      I1 => phy_wrdata(254),
      I2 => mem_reg_0_15_72_77,
      O => \write_buffer.wr_buf_out_data_reg[463]_0\(51)
    );
\mem_reg_0_15_66_71_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(214),
      I1 => phy_wrdata(254),
      I2 => mem_reg_0_15_72_77,
      O => \write_buffer.wr_buf_out_data_reg[471]_0\(51)
    );
\mem_reg_0_15_66_71_i_1__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(222),
      I1 => phy_wrdata(254),
      I2 => mem_reg_0_15_72_77,
      O => \write_buffer.wr_buf_out_data_reg[479]_0\(51)
    );
\mem_reg_0_15_66_71_i_1__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(238),
      I1 => phy_wrdata(254),
      I2 => mem_reg_0_15_18_23,
      O => \write_buffer.wr_buf_out_data_reg[495]_0\(51)
    );
\mem_reg_0_15_66_71_i_1__3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(246),
      I1 => phy_wrdata(254),
      I2 => mem_reg_0_15_18_23,
      O => \write_buffer.wr_buf_out_data_reg[503]_0\(51)
    );
\mem_reg_0_15_66_71_i_1__4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(254),
      I1 => phy_wrdata(254),
      I2 => mem_reg_0_15_18_23,
      O => \write_buffer.wr_buf_out_data_reg[511]_0\(51)
    );
\mem_reg_0_15_66_71_i_1__5\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[1]\,
      I1 => \phy_ctl_wd_i1_reg[0]\,
      O => d_in(31)
    );
\mem_reg_0_15_66_71_i_1__6\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[2]\,
      I1 => \phy_ctl_wd_i1_reg[0]\,
      O => phy_dout(19)
    );
mem_reg_0_15_66_71_i_2: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mc_address(24),
      I1 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[1]\,
      I2 => \phy_ctl_wd_i1_reg[0]\,
      O => d_in(30)
    );
\mem_reg_0_15_66_71_i_2__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mc_address(25),
      I1 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[2]\,
      I2 => \phy_ctl_wd_i1_reg[0]\,
      O => phy_dout(18)
    );
\mem_reg_0_15_66_71_i_2__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(142),
      I1 => phy_wrdata(190),
      I2 => mem_reg_0_15_66_71,
      O => \write_buffer.wr_buf_out_data_reg[463]_0\(50)
    );
\mem_reg_0_15_66_71_i_2__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(150),
      I1 => phy_wrdata(190),
      I2 => mem_reg_0_15_66_71,
      O => \write_buffer.wr_buf_out_data_reg[471]_0\(50)
    );
\mem_reg_0_15_66_71_i_2__3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(158),
      I1 => phy_wrdata(190),
      I2 => mem_reg_0_15_66_71,
      O => \write_buffer.wr_buf_out_data_reg[479]_0\(50)
    );
\mem_reg_0_15_66_71_i_2__4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(174),
      I1 => phy_wrdata(190),
      I2 => mem_reg_0_15_66_71,
      O => \write_buffer.wr_buf_out_data_reg[495]_0\(50)
    );
\mem_reg_0_15_66_71_i_2__5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(182),
      I1 => phy_wrdata(190),
      I2 => mem_reg_0_15_72_77,
      O => \write_buffer.wr_buf_out_data_reg[503]_0\(50)
    );
\mem_reg_0_15_66_71_i_2__6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(190),
      I1 => phy_wrdata(190),
      I2 => mem_reg_0_15_72_77,
      O => \write_buffer.wr_buf_out_data_reg[511]_0\(50)
    );
mem_reg_0_15_66_71_i_3: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(334),
      I1 => phy_wrdata(382),
      I2 => mem_reg_0_15_36_41_0,
      O => \write_buffer.wr_buf_out_data_reg[463]_0\(53)
    );
\mem_reg_0_15_66_71_i_3__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(342),
      I1 => phy_wrdata(382),
      I2 => mem_reg_0_15_36_41_0,
      O => \write_buffer.wr_buf_out_data_reg[471]_0\(53)
    );
\mem_reg_0_15_66_71_i_3__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(350),
      I1 => phy_wrdata(382),
      I2 => mem_reg_0_15_36_41_0,
      O => \write_buffer.wr_buf_out_data_reg[479]_0\(53)
    );
\mem_reg_0_15_66_71_i_3__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(366),
      I1 => phy_wrdata(382),
      I2 => mem_reg_0_15_36_41_0,
      O => \write_buffer.wr_buf_out_data_reg[495]_0\(53)
    );
\mem_reg_0_15_66_71_i_3__3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(374),
      I1 => phy_wrdata(382),
      I2 => mem_reg_0_15_36_41_1,
      O => \write_buffer.wr_buf_out_data_reg[503]_0\(53)
    );
\mem_reg_0_15_66_71_i_3__4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(382),
      I1 => phy_wrdata(382),
      I2 => mem_reg_0_15_36_41_1,
      O => \write_buffer.wr_buf_out_data_reg[511]_0\(53)
    );
mem_reg_0_15_66_71_i_4: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(270),
      I1 => phy_wrdata(318),
      I2 => mem_reg_0_15_18_23,
      O => \write_buffer.wr_buf_out_data_reg[463]_0\(52)
    );
\mem_reg_0_15_66_71_i_4__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(278),
      I1 => phy_wrdata(318),
      I2 => mem_reg_0_15_18_23_0,
      O => \write_buffer.wr_buf_out_data_reg[471]_0\(52)
    );
\mem_reg_0_15_66_71_i_4__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(286),
      I1 => phy_wrdata(318),
      I2 => mem_reg_0_15_18_23_0,
      O => \write_buffer.wr_buf_out_data_reg[479]_0\(52)
    );
\mem_reg_0_15_66_71_i_4__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(302),
      I1 => phy_wrdata(318),
      I2 => mem_reg_0_15_18_23_0,
      O => \write_buffer.wr_buf_out_data_reg[495]_0\(52)
    );
\mem_reg_0_15_66_71_i_4__3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(310),
      I1 => phy_wrdata(318),
      I2 => mem_reg_0_15_18_23_0,
      O => \write_buffer.wr_buf_out_data_reg[503]_0\(52)
    );
\mem_reg_0_15_66_71_i_4__4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(318),
      I1 => phy_wrdata(318),
      I2 => mem_reg_0_15_18_23_0,
      O => \write_buffer.wr_buf_out_data_reg[511]_0\(52)
    );
mem_reg_0_15_66_71_i_5: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(462),
      I1 => phy_wrdata(510),
      I2 => mem_reg_0_15_54_59_0,
      O => \write_buffer.wr_buf_out_data_reg[463]_0\(55)
    );
\mem_reg_0_15_66_71_i_5__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(470),
      I1 => phy_wrdata(510),
      I2 => mem_reg_0_15_78_79_0,
      O => \write_buffer.wr_buf_out_data_reg[471]_0\(55)
    );
\mem_reg_0_15_66_71_i_5__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(478),
      I1 => phy_wrdata(510),
      I2 => mem_reg_0_15_78_79_0,
      O => \write_buffer.wr_buf_out_data_reg[479]_0\(55)
    );
\mem_reg_0_15_66_71_i_5__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(494),
      I1 => phy_wrdata(510),
      I2 => mem_reg_0_15_78_79_0,
      O => \write_buffer.wr_buf_out_data_reg[495]_0\(55)
    );
\mem_reg_0_15_66_71_i_5__3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(502),
      I1 => phy_wrdata(510),
      I2 => mem_reg_0_15_78_79_0,
      O => \write_buffer.wr_buf_out_data_reg[503]_0\(55)
    );
\mem_reg_0_15_66_71_i_5__4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(510),
      I1 => phy_wrdata(510),
      I2 => mem_reg_0_15_78_79_0,
      O => \write_buffer.wr_buf_out_data_reg[511]_0\(55)
    );
mem_reg_0_15_66_71_i_6: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(398),
      I1 => phy_wrdata(446),
      I2 => mem_reg_0_15_36_41_1,
      O => \write_buffer.wr_buf_out_data_reg[463]_0\(54)
    );
\mem_reg_0_15_66_71_i_6__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(406),
      I1 => phy_wrdata(446),
      I2 => mem_reg_0_15_36_41_1,
      O => \write_buffer.wr_buf_out_data_reg[471]_0\(54)
    );
\mem_reg_0_15_66_71_i_6__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(414),
      I1 => phy_wrdata(446),
      I2 => mem_reg_0_15_36_41_1,
      O => \write_buffer.wr_buf_out_data_reg[479]_0\(54)
    );
\mem_reg_0_15_66_71_i_6__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(430),
      I1 => phy_wrdata(446),
      I2 => mem_reg_0_15_54_59_0,
      O => \write_buffer.wr_buf_out_data_reg[495]_0\(54)
    );
\mem_reg_0_15_66_71_i_6__3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(438),
      I1 => phy_wrdata(446),
      I2 => mem_reg_0_15_54_59_0,
      O => \write_buffer.wr_buf_out_data_reg[503]_0\(54)
    );
\mem_reg_0_15_66_71_i_6__4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(446),
      I1 => phy_wrdata(446),
      I2 => mem_reg_0_15_54_59_0,
      O => \write_buffer.wr_buf_out_data_reg[511]_0\(54)
    );
mem_reg_0_15_6_11_i_1: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mc_address(19),
      I1 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[7]\,
      I2 => \phy_ctl_wd_i1_reg[0]\,
      O => d_in(1)
    );
mem_reg_0_15_6_11_i_2: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mc_address(7),
      I1 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[7]\,
      I2 => \phy_ctl_wd_i1_reg[0]\,
      O => d_in(0)
    );
mem_reg_0_15_6_11_i_3: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(64),
      I1 => phy_wrdata(120),
      I2 => mem_reg_0_15_48_53,
      O => \write_buffer.wr_buf_out_data_reg[455]_0\(1)
    );
\mem_reg_0_15_6_11_i_3__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(96),
      I1 => phy_wrdata(120),
      I2 => mem_reg_0_15_54_59,
      O => \write_buffer.wr_buf_out_data_reg[487]_0\(1)
    );
\mem_reg_0_15_6_11_i_3__1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[7]\,
      I1 => mem_reg_0_15_36_41,
      O => d_in(3)
    );
mem_reg_0_15_6_11_i_4: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mc_address(30),
      I1 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[7]\,
      I2 => \phy_ctl_wd_i1_reg[0]\,
      O => d_in(2)
    );
\mem_reg_0_15_6_11_i_4__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(0),
      I1 => phy_wrdata(56),
      I2 => mem_reg_0_15_36_41,
      O => \write_buffer.wr_buf_out_data_reg[455]_0\(0)
    );
\mem_reg_0_15_6_11_i_4__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(32),
      I1 => phy_wrdata(56),
      I2 => mem_reg_0_15_48_53,
      O => \write_buffer.wr_buf_out_data_reg[487]_0\(0)
    );
mem_reg_0_15_6_11_i_5: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(192),
      I1 => phy_wrdata(248),
      I2 => mem_reg_0_15_72_77,
      O => \write_buffer.wr_buf_out_data_reg[455]_0\(3)
    );
\mem_reg_0_15_6_11_i_5__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(224),
      I1 => phy_wrdata(248),
      I2 => mem_reg_0_15_18_23,
      O => \write_buffer.wr_buf_out_data_reg[487]_0\(3)
    );
mem_reg_0_15_6_11_i_6: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(128),
      I1 => phy_wrdata(184),
      I2 => mem_reg_0_15_66_71,
      O => \write_buffer.wr_buf_out_data_reg[455]_0\(2)
    );
\mem_reg_0_15_6_11_i_6__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(160),
      I1 => phy_wrdata(184),
      I2 => mem_reg_0_15_66_71,
      O => \write_buffer.wr_buf_out_data_reg[487]_0\(2)
    );
mem_reg_0_15_72_77_i_1: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mc_address(18),
      I1 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[6]\,
      I2 => \phy_ctl_wd_i1_reg[0]\,
      O => phy_dout(21)
    );
\mem_reg_0_15_72_77_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mc_address(21),
      I1 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[9]\,
      I2 => \phy_ctl_wd_i1_reg[0]\,
      O => d_in(33)
    );
\mem_reg_0_15_72_77_i_1__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(71),
      I1 => phy_wrdata(127),
      I2 => mem_reg_0_15_48_53,
      O => \write_buffer.wr_buf_out_data_reg[455]_0\(57)
    );
\mem_reg_0_15_72_77_i_1__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(79),
      I1 => phy_wrdata(127),
      I2 => mem_reg_0_15_54_59,
      O => \write_buffer.wr_buf_out_data_reg[463]_0\(57)
    );
\mem_reg_0_15_72_77_i_1__3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(87),
      I1 => phy_wrdata(127),
      I2 => mem_reg_0_15_54_59,
      O => \write_buffer.wr_buf_out_data_reg[471]_0\(57)
    );
\mem_reg_0_15_72_77_i_1__4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(95),
      I1 => phy_wrdata(127),
      I2 => mem_reg_0_15_54_59,
      O => \write_buffer.wr_buf_out_data_reg[479]_0\(57)
    );
\mem_reg_0_15_72_77_i_1__5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(103),
      I1 => phy_wrdata(127),
      I2 => mem_reg_0_15_54_59,
      O => \write_buffer.wr_buf_out_data_reg[487]_0\(57)
    );
\mem_reg_0_15_72_77_i_1__6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(111),
      I1 => phy_wrdata(127),
      I2 => mem_reg_0_15_54_59,
      O => \write_buffer.wr_buf_out_data_reg[495]_0\(57)
    );
\mem_reg_0_15_72_77_i_1__7\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(119),
      I1 => phy_wrdata(127),
      I2 => mem_reg_0_15_54_59,
      O => \write_buffer.wr_buf_out_data_reg[503]_0\(57)
    );
\mem_reg_0_15_72_77_i_1__8\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(127),
      I1 => phy_wrdata(127),
      I2 => mem_reg_0_15_66_71,
      O => \write_buffer.wr_buf_out_data_reg[511]_0\(57)
    );
mem_reg_0_15_72_77_i_2: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mc_address(6),
      I1 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[6]\,
      I2 => \phy_ctl_wd_i1_reg[0]\,
      O => phy_dout(20)
    );
\mem_reg_0_15_72_77_i_2__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mc_address(9),
      I1 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[9]\,
      I2 => \phy_ctl_wd_i1_reg[0]\,
      O => d_in(32)
    );
\mem_reg_0_15_72_77_i_2__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(7),
      I1 => phy_wrdata(63),
      I2 => mem_reg_0_15_36_41,
      O => \write_buffer.wr_buf_out_data_reg[455]_0\(56)
    );
\mem_reg_0_15_72_77_i_2__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(15),
      I1 => phy_wrdata(63),
      I2 => mem_reg_0_15_36_41,
      O => \write_buffer.wr_buf_out_data_reg[463]_0\(56)
    );
\mem_reg_0_15_72_77_i_2__3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(23),
      I1 => phy_wrdata(63),
      I2 => mem_reg_0_15_36_41,
      O => \write_buffer.wr_buf_out_data_reg[471]_0\(56)
    );
\mem_reg_0_15_72_77_i_2__4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(31),
      I1 => phy_wrdata(63),
      I2 => mem_reg_0_15_48_53,
      O => \write_buffer.wr_buf_out_data_reg[479]_0\(56)
    );
\mem_reg_0_15_72_77_i_2__5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(39),
      I1 => phy_wrdata(63),
      I2 => mem_reg_0_15_48_53,
      O => \write_buffer.wr_buf_out_data_reg[487]_0\(56)
    );
\mem_reg_0_15_72_77_i_2__6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(47),
      I1 => phy_wrdata(63),
      I2 => mem_reg_0_15_48_53,
      O => \write_buffer.wr_buf_out_data_reg[495]_0\(56)
    );
\mem_reg_0_15_72_77_i_2__7\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(55),
      I1 => phy_wrdata(63),
      I2 => mem_reg_0_15_48_53,
      O => \write_buffer.wr_buf_out_data_reg[503]_0\(56)
    );
\mem_reg_0_15_72_77_i_2__8\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(63),
      I1 => phy_wrdata(63),
      I2 => mem_reg_0_15_48_53,
      O => \write_buffer.wr_buf_out_data_reg[511]_0\(56)
    );
mem_reg_0_15_72_77_i_3: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(199),
      I1 => phy_wrdata(255),
      I2 => mem_reg_0_15_72_77,
      O => \write_buffer.wr_buf_out_data_reg[455]_0\(59)
    );
\mem_reg_0_15_72_77_i_3__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(207),
      I1 => phy_wrdata(255),
      I2 => mem_reg_0_15_72_77,
      O => \write_buffer.wr_buf_out_data_reg[463]_0\(59)
    );
\mem_reg_0_15_72_77_i_3__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(215),
      I1 => phy_wrdata(255),
      I2 => mem_reg_0_15_72_77,
      O => \write_buffer.wr_buf_out_data_reg[471]_0\(59)
    );
\mem_reg_0_15_72_77_i_3__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(223),
      I1 => phy_wrdata(255),
      I2 => mem_reg_0_15_72_77,
      O => \write_buffer.wr_buf_out_data_reg[479]_0\(59)
    );
\mem_reg_0_15_72_77_i_3__3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(231),
      I1 => phy_wrdata(255),
      I2 => mem_reg_0_15_18_23,
      O => \write_buffer.wr_buf_out_data_reg[487]_0\(59)
    );
\mem_reg_0_15_72_77_i_3__4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(239),
      I1 => phy_wrdata(255),
      I2 => mem_reg_0_15_18_23,
      O => \write_buffer.wr_buf_out_data_reg[495]_0\(59)
    );
\mem_reg_0_15_72_77_i_3__5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(247),
      I1 => phy_wrdata(255),
      I2 => mem_reg_0_15_18_23,
      O => \write_buffer.wr_buf_out_data_reg[503]_0\(59)
    );
\mem_reg_0_15_72_77_i_3__6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(255),
      I1 => phy_wrdata(255),
      I2 => mem_reg_0_15_18_23,
      O => \write_buffer.wr_buf_out_data_reg[511]_0\(59)
    );
\mem_reg_0_15_72_77_i_3__7\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[6]\,
      I1 => mem_reg_0_15_36_41,
      O => phy_dout(23)
    );
\mem_reg_0_15_72_77_i_3__8\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[9]\,
      I1 => mem_reg_0_15_36_41,
      O => d_in(35)
    );
mem_reg_0_15_72_77_i_4: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mc_address(29),
      I1 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[6]\,
      I2 => \phy_ctl_wd_i1_reg[0]\,
      O => phy_dout(22)
    );
\mem_reg_0_15_72_77_i_4__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mc_address(32),
      I1 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[9]\,
      I2 => \phy_ctl_wd_i1_reg[0]\,
      O => d_in(34)
    );
\mem_reg_0_15_72_77_i_4__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(135),
      I1 => phy_wrdata(191),
      I2 => mem_reg_0_15_66_71,
      O => \write_buffer.wr_buf_out_data_reg[455]_0\(58)
    );
\mem_reg_0_15_72_77_i_4__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(143),
      I1 => phy_wrdata(191),
      I2 => mem_reg_0_15_66_71,
      O => \write_buffer.wr_buf_out_data_reg[463]_0\(58)
    );
\mem_reg_0_15_72_77_i_4__3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(151),
      I1 => phy_wrdata(191),
      I2 => mem_reg_0_15_66_71,
      O => \write_buffer.wr_buf_out_data_reg[471]_0\(58)
    );
\mem_reg_0_15_72_77_i_4__4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(159),
      I1 => phy_wrdata(191),
      I2 => mem_reg_0_15_66_71,
      O => \write_buffer.wr_buf_out_data_reg[479]_0\(58)
    );
\mem_reg_0_15_72_77_i_4__5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(167),
      I1 => phy_wrdata(191),
      I2 => mem_reg_0_15_66_71,
      O => \write_buffer.wr_buf_out_data_reg[487]_0\(58)
    );
\mem_reg_0_15_72_77_i_4__6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(175),
      I1 => phy_wrdata(191),
      I2 => mem_reg_0_15_72_77,
      O => \write_buffer.wr_buf_out_data_reg[495]_0\(58)
    );
\mem_reg_0_15_72_77_i_4__7\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(183),
      I1 => phy_wrdata(191),
      I2 => mem_reg_0_15_72_77,
      O => \write_buffer.wr_buf_out_data_reg[503]_0\(58)
    );
\mem_reg_0_15_72_77_i_4__8\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(191),
      I1 => phy_wrdata(191),
      I2 => mem_reg_0_15_72_77,
      O => \write_buffer.wr_buf_out_data_reg[511]_0\(58)
    );
mem_reg_0_15_72_77_i_5: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(327),
      I1 => phy_wrdata(383),
      I2 => mem_reg_0_15_36_41_0,
      O => \write_buffer.wr_buf_out_data_reg[455]_0\(61)
    );
\mem_reg_0_15_72_77_i_5__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(335),
      I1 => phy_wrdata(383),
      I2 => mem_reg_0_15_36_41_0,
      O => \write_buffer.wr_buf_out_data_reg[463]_0\(61)
    );
\mem_reg_0_15_72_77_i_5__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(343),
      I1 => phy_wrdata(383),
      I2 => mem_reg_0_15_36_41_0,
      O => \write_buffer.wr_buf_out_data_reg[471]_0\(61)
    );
\mem_reg_0_15_72_77_i_5__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(351),
      I1 => phy_wrdata(383),
      I2 => mem_reg_0_15_36_41_0,
      O => \write_buffer.wr_buf_out_data_reg[479]_0\(61)
    );
\mem_reg_0_15_72_77_i_5__3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(359),
      I1 => phy_wrdata(383),
      I2 => mem_reg_0_15_36_41_0,
      O => \write_buffer.wr_buf_out_data_reg[487]_0\(61)
    );
\mem_reg_0_15_72_77_i_5__4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(367),
      I1 => phy_wrdata(383),
      I2 => mem_reg_0_15_36_41_0,
      O => \write_buffer.wr_buf_out_data_reg[495]_0\(61)
    );
\mem_reg_0_15_72_77_i_5__5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(375),
      I1 => phy_wrdata(383),
      I2 => mem_reg_0_15_36_41_1,
      O => \write_buffer.wr_buf_out_data_reg[503]_0\(61)
    );
\mem_reg_0_15_72_77_i_5__6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(383),
      I1 => phy_wrdata(383),
      I2 => mem_reg_0_15_36_41_1,
      O => \write_buffer.wr_buf_out_data_reg[511]_0\(61)
    );
mem_reg_0_15_72_77_i_6: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(263),
      I1 => phy_wrdata(319),
      I2 => mem_reg_0_15_18_23,
      O => \write_buffer.wr_buf_out_data_reg[455]_0\(60)
    );
\mem_reg_0_15_72_77_i_6__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(271),
      I1 => phy_wrdata(319),
      I2 => mem_reg_0_15_18_23,
      O => \write_buffer.wr_buf_out_data_reg[463]_0\(60)
    );
\mem_reg_0_15_72_77_i_6__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(279),
      I1 => phy_wrdata(319),
      I2 => mem_reg_0_15_18_23_0,
      O => \write_buffer.wr_buf_out_data_reg[471]_0\(60)
    );
\mem_reg_0_15_72_77_i_6__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(287),
      I1 => phy_wrdata(319),
      I2 => mem_reg_0_15_18_23_0,
      O => \write_buffer.wr_buf_out_data_reg[479]_0\(60)
    );
\mem_reg_0_15_72_77_i_6__3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(295),
      I1 => phy_wrdata(319),
      I2 => mem_reg_0_15_18_23_0,
      O => \write_buffer.wr_buf_out_data_reg[487]_0\(60)
    );
\mem_reg_0_15_72_77_i_6__4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(303),
      I1 => phy_wrdata(319),
      I2 => mem_reg_0_15_18_23_0,
      O => \write_buffer.wr_buf_out_data_reg[495]_0\(60)
    );
\mem_reg_0_15_72_77_i_6__5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(311),
      I1 => phy_wrdata(319),
      I2 => mem_reg_0_15_18_23_0,
      O => \write_buffer.wr_buf_out_data_reg[503]_0\(60)
    );
\mem_reg_0_15_72_77_i_6__6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(319),
      I1 => phy_wrdata(319),
      I2 => mem_reg_0_15_18_23_0,
      O => \write_buffer.wr_buf_out_data_reg[511]_0\(60)
    );
mem_reg_0_15_78_79_i_1: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(455),
      I1 => phy_wrdata(511),
      I2 => mem_reg_0_15_54_59_0,
      O => \write_buffer.wr_buf_out_data_reg[455]_0\(63)
    );
\mem_reg_0_15_78_79_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(463),
      I1 => phy_wrdata(511),
      I2 => mem_reg_0_15_54_59_0,
      O => \write_buffer.wr_buf_out_data_reg[463]_0\(63)
    );
\mem_reg_0_15_78_79_i_1__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(471),
      I1 => phy_wrdata(511),
      I2 => mem_reg_0_15_78_79_0,
      O => \write_buffer.wr_buf_out_data_reg[471]_0\(63)
    );
\mem_reg_0_15_78_79_i_1__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(479),
      I1 => phy_wrdata(511),
      I2 => mem_reg_0_15_78_79_0,
      O => \write_buffer.wr_buf_out_data_reg[479]_0\(63)
    );
\mem_reg_0_15_78_79_i_1__3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(487),
      I1 => phy_wrdata(511),
      I2 => mem_reg_0_15_78_79_0,
      O => \write_buffer.wr_buf_out_data_reg[487]_0\(63)
    );
\mem_reg_0_15_78_79_i_1__4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(495),
      I1 => phy_wrdata(511),
      I2 => mem_reg_0_15_78_79_0,
      O => \write_buffer.wr_buf_out_data_reg[495]_0\(63)
    );
\mem_reg_0_15_78_79_i_1__5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(503),
      I1 => phy_wrdata(511),
      I2 => mem_reg_0_15_78_79_0,
      O => \write_buffer.wr_buf_out_data_reg[503]_0\(63)
    );
\mem_reg_0_15_78_79_i_1__6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(511),
      I1 => phy_wrdata(511),
      I2 => mem_reg_0_15_78_79_0,
      O => \write_buffer.wr_buf_out_data_reg[511]_0\(63)
    );
mem_reg_0_15_78_79_i_2: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(391),
      I1 => phy_wrdata(447),
      I2 => mem_reg_0_15_36_41_1,
      O => \write_buffer.wr_buf_out_data_reg[455]_0\(62)
    );
\mem_reg_0_15_78_79_i_2__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(399),
      I1 => phy_wrdata(447),
      I2 => mem_reg_0_15_36_41_1,
      O => \write_buffer.wr_buf_out_data_reg[463]_0\(62)
    );
\mem_reg_0_15_78_79_i_2__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(407),
      I1 => phy_wrdata(447),
      I2 => mem_reg_0_15_36_41_1,
      O => \write_buffer.wr_buf_out_data_reg[471]_0\(62)
    );
\mem_reg_0_15_78_79_i_2__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(415),
      I1 => phy_wrdata(447),
      I2 => mem_reg_0_15_36_41_1,
      O => \write_buffer.wr_buf_out_data_reg[479]_0\(62)
    );
\mem_reg_0_15_78_79_i_2__3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(423),
      I1 => phy_wrdata(447),
      I2 => mem_reg_0_15_54_59_0,
      O => \write_buffer.wr_buf_out_data_reg[487]_0\(62)
    );
\mem_reg_0_15_78_79_i_2__4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(431),
      I1 => phy_wrdata(447),
      I2 => mem_reg_0_15_54_59_0,
      O => \write_buffer.wr_buf_out_data_reg[495]_0\(62)
    );
\mem_reg_0_15_78_79_i_2__5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(439),
      I1 => phy_wrdata(447),
      I2 => mem_reg_0_15_54_59_0,
      O => \write_buffer.wr_buf_out_data_reg[503]_0\(62)
    );
\mem_reg_0_15_78_79_i_2__6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mem_reg_0_15_78_79(447),
      I1 => phy_wrdata(447),
      I2 => mem_reg_0_15_54_59_0,
      O => \write_buffer.wr_buf_out_data_reg[511]_0\(62)
    );
mpr_rdlvl_start_i_1: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FF02"
    )
        port map (
      I0 => pi_dqs_found_done_r1_reg_0,
      I1 => \init_state_r_reg_n_0_[1]\,
      I2 => mpr_rdlvl_start_i_2_n_0,
      I3 => \^mpr_rdlvl_start_reg_0\,
      O => mpr_rdlvl_start_i_1_n_0
    );
mpr_rdlvl_start_i_2: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFDFFF"
    )
        port map (
      I0 => \init_state_r_reg_n_0_[3]\,
      I1 => \init_state_r_reg_n_0_[2]\,
      I2 => \^q\(0),
      I3 => \init_state_r_reg_n_0_[5]\,
      I4 => \init_state_r_reg_n_0_[4]\,
      I5 => init_state_r(6),
      O => mpr_rdlvl_start_i_2_n_0
    );
mpr_rdlvl_start_reg: unisim.vcomponents.FDRE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => '1',
      D => mpr_rdlvl_start_i_1_n_0,
      Q => \^mpr_rdlvl_start_reg_0\,
      R => \victim_sel_reg[0]_0\(0)
    );
mux_rd_valid_r_i_1: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \^prbs_rdlvl_start_reg_0\,
      I1 => if_empty,
      O => mux_rd_valid_r0
    );
new_cnt_dqs_r_i_2: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \^prbs_rdlvl_start_reg_0\,
      I1 => prbs_rdlvl_start_r,
      O => prbs_rdlvl_start_reg_1
    );
\num_refresh[0]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => num_refresh_reg(0),
      O => \p_0_in__5\(0)
    );
\num_refresh[1]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => num_refresh_reg(1),
      I1 => num_refresh_reg(0),
      O => \p_0_in__5\(1)
    );
\num_refresh[2]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"6A"
    )
        port map (
      I0 => num_refresh_reg(2),
      I1 => num_refresh_reg(0),
      I2 => num_refresh_reg(1),
      O => \p_0_in__5\(2)
    );
\num_refresh[3]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFDFDD"
    )
        port map (
      I0 => \num_refresh[3]_i_4_n_0\,
      I1 => \rd_addr_reg[7]\,
      I2 => complex_oclkdelay_calib_start_int_i_2_n_0,
      I3 => \init_state_r_reg_n_0_[1]\,
      I4 => \num_refresh[3]_i_5_n_0\,
      O => \num_refresh[3]_i_1_n_0\
    );
\num_refresh[3]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0A8AAA8A"
    )
        port map (
      I0 => \num_refresh[3]_i_6_n_0\,
      I1 => ddr3_lm_done_r_reg_0,
      I2 => pi_dqs_found_done_r1_reg_0,
      I3 => prbs_rdlvl_start_reg_2,
      I4 => complex_oclkdelay_calib_done_r1_reg_0,
      O => num_refresh0
    );
\num_refresh[3]_i_3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6AAA"
    )
        port map (
      I0 => num_refresh_reg(3),
      I1 => num_refresh_reg(1),
      I2 => num_refresh_reg(0),
      I3 => num_refresh_reg(2),
      O => \p_0_in__5\(3)
    );
\num_refresh[3]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFEFFFFFFFFE"
    )
        port map (
      I0 => rdlvl_stg1_start_int_i_2_n_0,
      I1 => init_state_r(6),
      I2 => \init_state_r_reg_n_0_[5]\,
      I3 => \init_state_r_reg_n_0_[4]\,
      I4 => \init_state_r_reg_n_0_[1]\,
      I5 => \^q\(0),
      O => \num_refresh[3]_i_4_n_0\
    );
\num_refresh[3]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000041000000"
    )
        port map (
      I0 => prbs_rdlvl_start_i_2_n_0,
      I1 => \init_state_r_reg_n_0_[3]\,
      I2 => \init_state_r_reg_n_0_[4]\,
      I3 => \init_state_r_reg_n_0_[2]\,
      I4 => \init_state_r_reg_n_0_[5]\,
      I5 => init_state_r(6),
      O => \num_refresh[3]_i_5_n_0\
    );
\num_refresh[3]_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000000800"
    )
        port map (
      I0 => \init_state_r_reg_n_0_[4]\,
      I1 => \gen_no_mirror.div_clk_loop[0].phy_address[12]_i_2_n_0\,
      I2 => \init_state_r_reg_n_0_[2]\,
      I3 => \init_state_r_reg_n_0_[3]\,
      I4 => init_state_r(6),
      I5 => \init_state_r_reg_n_0_[5]\,
      O => \num_refresh[3]_i_6_n_0\
    );
\num_refresh_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => num_refresh0,
      D => \p_0_in__5\(0),
      Q => num_refresh_reg(0),
      R => \num_refresh[3]_i_1_n_0\
    );
\num_refresh_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => num_refresh0,
      D => \p_0_in__5\(1),
      Q => num_refresh_reg(1),
      R => \num_refresh[3]_i_1_n_0\
    );
\num_refresh_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => num_refresh0,
      D => \p_0_in__5\(2),
      Q => num_refresh_reg(2),
      R => \num_refresh[3]_i_1_n_0\
    );
\num_refresh_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => num_refresh0,
      D => \p_0_in__5\(3),
      Q => num_refresh_reg(3),
      R => \num_refresh[3]_i_1_n_0\
    );
\ocal_act_wait_cnt[0]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => ocal_act_wait_cnt_reg(0),
      O => \p_0_in__8\(0)
    );
\ocal_act_wait_cnt[1]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => ocal_act_wait_cnt_reg(1),
      I1 => ocal_act_wait_cnt_reg(0),
      O => \p_0_in__8\(1)
    );
\ocal_act_wait_cnt[2]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"6A"
    )
        port map (
      I0 => ocal_act_wait_cnt_reg(2),
      I1 => ocal_act_wait_cnt_reg(1),
      I2 => ocal_act_wait_cnt_reg(0),
      O => \p_0_in__8\(2)
    );
\ocal_act_wait_cnt[3]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFFFFD"
    )
        port map (
      I0 => \init_state_r_reg_n_0_[1]\,
      I1 => \^q\(0),
      I2 => \ocal_act_wait_cnt[3]_i_3_n_0\,
      I3 => prbs_rdlvl_start_i_3_n_0,
      I4 => write_calib_reg_0,
      O => \ocal_act_wait_cnt[3]_i_1_n_0\
    );
\ocal_act_wait_cnt[3]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7F80"
    )
        port map (
      I0 => ocal_act_wait_cnt_reg(0),
      I1 => ocal_act_wait_cnt_reg(1),
      I2 => ocal_act_wait_cnt_reg(2),
      I3 => ocal_act_wait_cnt_reg(3),
      O => \p_0_in__8\(3)
    );
\ocal_act_wait_cnt[3]_i_3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8000"
    )
        port map (
      I0 => ocal_act_wait_cnt_reg(3),
      I1 => ocal_act_wait_cnt_reg(2),
      I2 => ocal_act_wait_cnt_reg(1),
      I3 => ocal_act_wait_cnt_reg(0),
      O => \ocal_act_wait_cnt[3]_i_3_n_0\
    );
\ocal_act_wait_cnt_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => '1',
      D => \p_0_in__8\(0),
      Q => ocal_act_wait_cnt_reg(0),
      R => \ocal_act_wait_cnt[3]_i_1_n_0\
    );
\ocal_act_wait_cnt_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => '1',
      D => \p_0_in__8\(1),
      Q => ocal_act_wait_cnt_reg(1),
      R => \ocal_act_wait_cnt[3]_i_1_n_0\
    );
\ocal_act_wait_cnt_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => '1',
      D => \p_0_in__8\(2),
      Q => ocal_act_wait_cnt_reg(2),
      R => \ocal_act_wait_cnt[3]_i_1_n_0\
    );
\ocal_act_wait_cnt_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => '1',
      D => \p_0_in__8\(3),
      Q => ocal_act_wait_cnt_reg(3),
      R => \ocal_act_wait_cnt[3]_i_1_n_0\
    );
\oclk_wr_cnt[0]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => oclk_wr_cnt_reg(0),
      O => \oclk_wr_cnt[0]_i_1_n_0\
    );
\oclk_wr_cnt[1]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => oclk_wr_cnt_reg(0),
      I1 => oclk_wr_cnt_reg(1),
      O => \oclk_wr_cnt[1]_i_1_n_0\
    );
\oclk_wr_cnt[2]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"A9"
    )
        port map (
      I0 => oclk_wr_cnt_reg(2),
      I1 => oclk_wr_cnt_reg(1),
      I2 => oclk_wr_cnt_reg(0),
      O => oclk_wr_cnt0(2)
    );
\oclk_wr_cnt[3]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFAAAAAAAB"
    )
        port map (
      I0 => \oclk_wr_cnt[3]_i_4_n_0\,
      I1 => oclk_wr_cnt_reg(1),
      I2 => oclk_wr_cnt_reg(0),
      I3 => oclk_wr_cnt_reg(3),
      I4 => oclk_wr_cnt_reg(2),
      I5 => write_calib_reg_0,
      O => \oclk_wr_cnt[3]_i_1_n_0\
    );
\oclk_wr_cnt[3]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000002000000"
    )
        port map (
      I0 => \init_state_r_reg_n_0_[1]\,
      I1 => init_state_r(6),
      I2 => \init_state_r_reg_n_0_[4]\,
      I3 => \init_state_r_reg_n_0_[5]\,
      I4 => \^q\(0),
      I5 => rdlvl_stg1_start_int_i_2_n_0,
      O => p_0_in0_in
    );
\oclk_wr_cnt[3]_i_3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"AAA9"
    )
        port map (
      I0 => oclk_wr_cnt_reg(3),
      I1 => oclk_wr_cnt_reg(2),
      I2 => oclk_wr_cnt_reg(0),
      I3 => oclk_wr_cnt_reg(1),
      O => oclk_wr_cnt0(3)
    );
\oclk_wr_cnt[3]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000000800"
    )
        port map (
      I0 => \wrcal_reads[7]_i_5_n_0\,
      I1 => \init_state_r_reg_n_0_[5]\,
      I2 => init_state_r(6),
      I3 => \init_state_r_reg_n_0_[4]\,
      I4 => \init_state_r_reg_n_0_[3]\,
      I5 => \init_state_r_reg_n_0_[2]\,
      O => \oclk_wr_cnt[3]_i_4_n_0\
    );
\oclk_wr_cnt_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => p_0_in0_in,
      D => \oclk_wr_cnt[0]_i_1_n_0\,
      Q => oclk_wr_cnt_reg(0),
      R => \oclk_wr_cnt[3]_i_1_n_0\
    );
\oclk_wr_cnt_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => p_0_in0_in,
      D => \oclk_wr_cnt[1]_i_1_n_0\,
      Q => oclk_wr_cnt_reg(1),
      R => \oclk_wr_cnt[3]_i_1_n_0\
    );
\oclk_wr_cnt_reg[2]\: unisim.vcomponents.FDSE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => p_0_in0_in,
      D => oclk_wr_cnt0(2),
      Q => oclk_wr_cnt_reg(2),
      S => \oclk_wr_cnt[3]_i_1_n_0\
    );
\oclk_wr_cnt_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => p_0_in0_in,
      D => oclk_wr_cnt0(3),
      Q => oclk_wr_cnt_reg(3),
      R => \oclk_wr_cnt[3]_i_1_n_0\
    );
\odd_cwl.phy_cas_n[1]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8888888888880888"
    )
        port map (
      I0 => \DDR3_1rank.phy_int_cs_n[1]_i_2_n_0\,
      I1 => \odd_cwl.phy_cas_n[1]_i_2_n_0\,
      I2 => \init_state_r_reg_n_0_[4]\,
      I3 => \gen_no_mirror.div_clk_loop[0].phy_address[12]_i_2_n_0\,
      I4 => \init_state_r[4]_i_4_n_0\,
      I5 => \init_state_r[3]_i_6_n_0\,
      O => \odd_cwl.phy_cas_n[1]_i_1_n_0\
    );
\odd_cwl.phy_cas_n[1]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"2A0AAA022AAAAA22"
    )
        port map (
      I0 => \DDR3_1rank.phy_int_cs_n[1]_i_7_n_0\,
      I1 => \odd_cwl.phy_cas_n[1]_i_3_n_0\,
      I2 => \init_state_r_reg_n_0_[1]\,
      I3 => \^q\(0),
      I4 => \init_state_r_reg_n_0_[4]\,
      I5 => \odd_cwl.phy_cas_n[1]_i_4_n_0\,
      O => \odd_cwl.phy_cas_n[1]_i_2_n_0\
    );
\odd_cwl.phy_cas_n[1]_i_3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0010"
    )
        port map (
      I0 => \init_state_r_reg_n_0_[5]\,
      I1 => init_state_r(6),
      I2 => \init_state_r_reg_n_0_[3]\,
      I3 => \init_state_r_reg_n_0_[2]\,
      O => \odd_cwl.phy_cas_n[1]_i_3_n_0\
    );
\odd_cwl.phy_cas_n[1]_i_4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000100"
    )
        port map (
      I0 => init_state_r(6),
      I1 => \init_state_r_reg_n_0_[5]\,
      I2 => \init_state_r_reg_n_0_[4]\,
      I3 => \init_state_r_reg_n_0_[2]\,
      I4 => \init_state_r_reg_n_0_[3]\,
      O => \odd_cwl.phy_cas_n[1]_i_4_n_0\
    );
\odd_cwl.phy_cas_n_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => '1',
      D => \odd_cwl.phy_cas_n[1]_i_1_n_0\,
      Q => phy_cas_n(1),
      R => '0'
    );
\odd_cwl.phy_ras_n[1]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAAAAAAAAAA2"
    )
        port map (
      I0 => \DDR3_1rank.phy_int_cs_n[1]_i_3_n_0\,
      I1 => \init_state_r_reg_n_0_[4]\,
      I2 => prbs_rdlvl_start_i_2_n_0,
      I3 => \init_state_r_reg_n_0_[5]\,
      I4 => init_state_r(6),
      I5 => \init_state_r[4]_i_4_n_0\,
      O => \odd_cwl.phy_ras_n[1]_i_1_n_0\
    );
\odd_cwl.phy_ras_n_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => '1',
      D => \odd_cwl.phy_ras_n[1]_i_1_n_0\,
      Q => phy_ras_n(1),
      R => '0'
    );
\odd_cwl.phy_we_n[1]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"08"
    )
        port map (
      I0 => \odd_cwl.phy_cas_n[1]_i_2_n_0\,
      I1 => \gen_no_mirror.div_clk_loop[0].phy_address[10]_i_5_n_0\,
      I2 => phy_wrdata_en,
      O => \odd_cwl.phy_we_n[1]_i_1_n_0\
    );
\odd_cwl.phy_we_n_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => '1',
      D => \odd_cwl.phy_we_n[1]_i_1_n_0\,
      Q => phy_we_n(1),
      R => '0'
    );
\one_rank.stg1_wr_done_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0001000100010000"
    )
        port map (
      I0 => \reg_ctrl_cnt_r[3]_i_1_n_0\,
      I1 => rdlvl_last_byte_done,
      I2 => \^prbs_rdlvl_done_pulse_reg_0\,
      I3 => complex_byte_rd_done,
      I4 => \^stg1_wr_done\,
      I5 => \^one_rank.stg1_wr_done_reg_0\,
      O => \one_rank.stg1_wr_done_i_1_n_0\
    );
\one_rank.stg1_wr_done_reg\: unisim.vcomponents.FDRE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => '1',
      D => \one_rank.stg1_wr_done_i_1_n_0\,
      Q => \^one_rank.stg1_wr_done_reg_0\,
      R => '0'
    );
\one_rank_complex.complex_wr_done_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000002A"
    )
        port map (
      I0 => \one_rank_complex.complex_wr_done_i_2_n_0\,
      I1 => complex_oclkdelay_calib_done_r1_reg_0,
      I2 => \stg1_wr_rd_cnt[8]_i_5_n_0\,
      I3 => rdlvl_last_byte_done,
      I4 => \reg_ctrl_cnt_r[3]_i_1_n_0\,
      O => \one_rank_complex.complex_wr_done_i_1_n_0\
    );
\one_rank_complex.complex_wr_done_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000551055105510"
    )
        port map (
      I0 => \^prbs_rdlvl_done_pulse_reg_0\,
      I1 => \one_rank_complex.complex_wr_done_i_3_n_0\,
      I2 => \one_rank_complex.complex_wr_done_i_4_n_0\,
      I3 => complex_wr_done,
      I4 => \victim_sel[2]_i_4_n_0\,
      I5 => complex_byte_rd_done,
      O => \one_rank_complex.complex_wr_done_i_2_n_0\
    );
\one_rank_complex.complex_wr_done_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFDFFFFFFFFFDFFF"
    )
        port map (
      I0 => \init_state_r_reg_n_0_[4]\,
      I1 => complex_act_start_i_2_n_0,
      I2 => \init_state_r_reg_n_0_[2]\,
      I3 => \init_state_r_reg_n_0_[3]\,
      I4 => \init_state_r_reg_n_0_[1]\,
      I5 => \^q\(0),
      O => \one_rank_complex.complex_wr_done_i_3_n_0\
    );
\one_rank_complex.complex_wr_done_i_4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00800000"
    )
        port map (
      I0 => complex_wait_cnt_reg(2),
      I1 => complex_wait_cnt_reg(3),
      I2 => complex_row1_wr_done,
      I3 => complex_wait_cnt_reg(1),
      I4 => complex_wait_cnt_reg(0),
      O => \one_rank_complex.complex_wr_done_i_4_n_0\
    );
\one_rank_complex.complex_wr_done_reg\: unisim.vcomponents.FDRE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => '1',
      D => \one_rank_complex.complex_wr_done_i_1_n_0\,
      Q => complex_wr_done,
      R => '0'
    );
\out_fifo_i_10__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(448),
      I1 => phy_wrdata(504),
      I2 => out_fifo_27,
      I3 => out_fifo_3(7),
      I4 => out_fifo_4,
      O => \write_buffer.wr_buf_out_data_reg[448]\(7)
    );
\out_fifo_i_10__3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(480),
      I1 => phy_wrdata(504),
      I2 => out_fifo_28,
      I3 => out_fifo_12(7),
      I4 => out_fifo_13,
      O => \write_buffer.wr_buf_out_data_reg[480]\(7)
    );
\out_fifo_i_11__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(384),
      I1 => phy_wrdata(440),
      I2 => out_fifo_26,
      I3 => out_fifo_3(6),
      I4 => out_fifo_4,
      O => \write_buffer.wr_buf_out_data_reg[448]\(6)
    );
\out_fifo_i_11__3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(416),
      I1 => phy_wrdata(440),
      I2 => out_fifo_26,
      I3 => out_fifo_12(6),
      I4 => out_fifo_13,
      O => \write_buffer.wr_buf_out_data_reg[480]\(6)
    );
\out_fifo_i_12__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(320),
      I1 => phy_wrdata(376),
      I2 => out_fifo_24,
      I3 => out_fifo_3(5),
      I4 => out_fifo_4,
      O => \write_buffer.wr_buf_out_data_reg[448]\(5)
    );
\out_fifo_i_12__3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(352),
      I1 => phy_wrdata(376),
      I2 => out_fifo_25,
      I3 => out_fifo_12(5),
      I4 => out_fifo_13,
      O => \write_buffer.wr_buf_out_data_reg[480]\(5)
    );
\out_fifo_i_13__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(256),
      I1 => phy_wrdata(312),
      I2 => out_fifo_23,
      I3 => out_fifo_3(4),
      I4 => out_fifo_4,
      O => \write_buffer.wr_buf_out_data_reg[448]\(4)
    );
\out_fifo_i_13__3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(288),
      I1 => phy_wrdata(312),
      I2 => out_fifo_24,
      I3 => out_fifo_12(4),
      I4 => out_fifo_13,
      O => \write_buffer.wr_buf_out_data_reg[480]\(4)
    );
\out_fifo_i_14__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(192),
      I1 => phy_wrdata(248),
      I2 => out_fifo_22,
      I3 => out_fifo_3(3),
      I4 => out_fifo_4,
      O => \write_buffer.wr_buf_out_data_reg[448]\(3)
    );
\out_fifo_i_14__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(224),
      I1 => phy_wrdata(248),
      I2 => out_fifo_23,
      I3 => out_fifo_12(3),
      I4 => out_fifo_13,
      O => \write_buffer.wr_buf_out_data_reg[480]\(3)
    );
\out_fifo_i_14__2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"EEF0"
    )
        port map (
      I0 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[7]\,
      I1 => out_fifo_31,
      I2 => mem_out(3),
      I3 => out_fifo,
      O => D1(3)
    );
\out_fifo_i_14__3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"EEF0"
    )
        port map (
      I0 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[8]\,
      I1 => out_fifo_31,
      I2 => out_fifo_0(3),
      I3 => out_fifo_1,
      O => \gen_no_mirror.div_clk_loop[0].phy_address_reg[8]_0\(3)
    );
\out_fifo_i_15__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mc_address(30),
      I1 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[7]\,
      I2 => out_fifo_2,
      I3 => mem_out(2),
      I4 => out_fifo,
      O => D1(2)
    );
\out_fifo_i_15__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mc_address(31),
      I1 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[8]\,
      I2 => out_fifo_2,
      I3 => out_fifo_0(2),
      I4 => out_fifo_1,
      O => \gen_no_mirror.div_clk_loop[0].phy_address_reg[8]_0\(2)
    );
\out_fifo_i_15__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(128),
      I1 => phy_wrdata(184),
      I2 => out_fifo_21,
      I3 => out_fifo_3(2),
      I4 => out_fifo_4,
      O => \write_buffer.wr_buf_out_data_reg[448]\(2)
    );
\out_fifo_i_15__3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(160),
      I1 => phy_wrdata(184),
      I2 => out_fifo_21,
      I3 => out_fifo_12(2),
      I4 => out_fifo_13,
      O => \write_buffer.wr_buf_out_data_reg[480]\(2)
    );
out_fifo_i_16: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mc_address(19),
      I1 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[7]\,
      I2 => phy_ctl_wr_i1_reg,
      I3 => mem_out(1),
      I4 => out_fifo,
      O => D1(1)
    );
\out_fifo_i_16__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mc_address(20),
      I1 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[8]\,
      I2 => phy_ctl_wr_i1_reg,
      I3 => out_fifo_0(1),
      I4 => out_fifo_1,
      O => \gen_no_mirror.div_clk_loop[0].phy_address_reg[8]_0\(1)
    );
\out_fifo_i_16__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(64),
      I1 => phy_wrdata(120),
      I2 => out_fifo_11,
      I3 => out_fifo_3(1),
      I4 => out_fifo_4,
      O => \write_buffer.wr_buf_out_data_reg[448]\(1)
    );
\out_fifo_i_16__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(96),
      I1 => phy_wrdata(120),
      I2 => out_fifo_20,
      I3 => out_fifo_12(1),
      I4 => out_fifo_13,
      O => \write_buffer.wr_buf_out_data_reg[480]\(1)
    );
\out_fifo_i_16__3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => mc_odt(0),
      I1 => out_fifo_31,
      I2 => calib_odt(0),
      I3 => out_fifo_29(3),
      I4 => out_fifo_30,
      O => \cmd_pipe_plus.mc_odt_reg[0]\(3)
    );
out_fifo_i_17: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mc_address(7),
      I1 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[7]\,
      I2 => phy_ctl_wr_i1_reg,
      I3 => mem_out(0),
      I4 => out_fifo,
      O => D1(0)
    );
\out_fifo_i_17__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mc_address(8),
      I1 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[8]\,
      I2 => phy_ctl_wr_i1_reg,
      I3 => out_fifo_0(0),
      I4 => out_fifo_1,
      O => \gen_no_mirror.div_clk_loop[0].phy_address_reg[8]_0\(0)
    );
\out_fifo_i_17__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(0),
      I1 => phy_wrdata(56),
      I2 => out_fifo_2,
      I3 => out_fifo_3(0),
      I4 => out_fifo_4,
      O => \write_buffer.wr_buf_out_data_reg[448]\(0)
    );
\out_fifo_i_17__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(32),
      I1 => phy_wrdata(56),
      I2 => out_fifo_11,
      I3 => out_fifo_12(0),
      I4 => out_fifo_13,
      O => \write_buffer.wr_buf_out_data_reg[480]\(0)
    );
\out_fifo_i_17__3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => mc_odt(0),
      I1 => out_fifo_31,
      I2 => calib_odt(0),
      I3 => out_fifo_29(2),
      I4 => out_fifo_30,
      O => \cmd_pipe_plus.mc_odt_reg[0]\(2)
    );
\out_fifo_i_18__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(449),
      I1 => phy_wrdata(505),
      I2 => out_fifo_27,
      I3 => out_fifo_3(15),
      I4 => out_fifo_4,
      O => D2(7)
    );
\out_fifo_i_18__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(456),
      I1 => phy_wrdata(504),
      I2 => out_fifo_27,
      I3 => out_fifo_5(7),
      I4 => out_fifo_6,
      O => \write_buffer.wr_buf_out_data_reg[456]\(7)
    );
\out_fifo_i_18__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(464),
      I1 => phy_wrdata(504),
      I2 => out_fifo_27,
      I3 => out_fifo_7(7),
      I4 => out_fifo_8,
      O => \write_buffer.wr_buf_out_data_reg[464]\(7)
    );
\out_fifo_i_18__3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(472),
      I1 => phy_wrdata(504),
      I2 => out_fifo_28,
      I3 => out_fifo_9(7),
      I4 => out_fifo_10,
      O => \write_buffer.wr_buf_out_data_reg[472]\(7)
    );
\out_fifo_i_18__4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(481),
      I1 => phy_wrdata(505),
      I2 => out_fifo_28,
      I3 => out_fifo_12(15),
      I4 => out_fifo_13,
      O => \write_buffer.wr_buf_out_data_reg[481]\(7)
    );
\out_fifo_i_18__5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(488),
      I1 => phy_wrdata(504),
      I2 => out_fifo_28,
      I3 => out_fifo_14(7),
      I4 => out_fifo_15,
      O => \write_buffer.wr_buf_out_data_reg[488]\(7)
    );
\out_fifo_i_18__6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(496),
      I1 => phy_wrdata(504),
      I2 => out_fifo_28,
      I3 => out_fifo_16(7),
      I4 => out_fifo_17,
      O => \write_buffer.wr_buf_out_data_reg[496]\(7)
    );
\out_fifo_i_18__7\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(504),
      I1 => phy_wrdata(504),
      I2 => out_fifo_28,
      I3 => out_fifo_18(7),
      I4 => out_fifo_19,
      O => \write_buffer.wr_buf_out_data_reg[504]\(7)
    );
\out_fifo_i_18__8\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => mc_odt(0),
      I1 => out_fifo_28,
      I2 => calib_odt(0),
      I3 => out_fifo_29(1),
      I4 => out_fifo_30,
      O => \cmd_pipe_plus.mc_odt_reg[0]\(1)
    );
\out_fifo_i_18__9\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"EEF0"
    )
        port map (
      I0 => phy_bank(10),
      I1 => out_fifo_31,
      I2 => out_fifo_0(11),
      I3 => out_fifo_1,
      O => \gen_no_mirror.div_clk_loop[0].phy_bank_reg[1]_0\(7)
    );
\out_fifo_i_19__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mc_bank(7),
      I1 => phy_bank(10),
      I2 => out_fifo_2,
      I3 => out_fifo_0(10),
      I4 => out_fifo_1,
      O => \gen_no_mirror.div_clk_loop[0].phy_bank_reg[1]_0\(6)
    );
\out_fifo_i_19__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(385),
      I1 => phy_wrdata(441),
      I2 => out_fifo_26,
      I3 => out_fifo_3(14),
      I4 => out_fifo_4,
      O => D2(6)
    );
\out_fifo_i_19__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(392),
      I1 => phy_wrdata(440),
      I2 => out_fifo_26,
      I3 => out_fifo_5(6),
      I4 => out_fifo_6,
      O => \write_buffer.wr_buf_out_data_reg[456]\(6)
    );
\out_fifo_i_19__3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(400),
      I1 => phy_wrdata(440),
      I2 => out_fifo_26,
      I3 => out_fifo_7(6),
      I4 => out_fifo_8,
      O => \write_buffer.wr_buf_out_data_reg[464]\(6)
    );
\out_fifo_i_19__4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(408),
      I1 => phy_wrdata(440),
      I2 => out_fifo_26,
      I3 => out_fifo_9(6),
      I4 => out_fifo_10,
      O => \write_buffer.wr_buf_out_data_reg[472]\(6)
    );
\out_fifo_i_19__5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(417),
      I1 => phy_wrdata(441),
      I2 => out_fifo_26,
      I3 => out_fifo_12(14),
      I4 => out_fifo_13,
      O => \write_buffer.wr_buf_out_data_reg[481]\(6)
    );
\out_fifo_i_19__6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(424),
      I1 => phy_wrdata(440),
      I2 => out_fifo_27,
      I3 => out_fifo_14(6),
      I4 => out_fifo_15,
      O => \write_buffer.wr_buf_out_data_reg[488]\(6)
    );
\out_fifo_i_19__7\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(432),
      I1 => phy_wrdata(440),
      I2 => out_fifo_27,
      I3 => out_fifo_16(6),
      I4 => out_fifo_17,
      O => \write_buffer.wr_buf_out_data_reg[496]\(6)
    );
\out_fifo_i_19__8\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(440),
      I1 => phy_wrdata(440),
      I2 => out_fifo_27,
      I3 => out_fifo_18(6),
      I4 => out_fifo_19,
      O => \write_buffer.wr_buf_out_data_reg[504]\(6)
    );
\out_fifo_i_19__9\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => mc_odt(0),
      I1 => out_fifo_28,
      I2 => calib_odt(0),
      I3 => out_fifo_29(0),
      I4 => out_fifo_30,
      O => \cmd_pipe_plus.mc_odt_reg[0]\(0)
    );
\out_fifo_i_20__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mc_bank(4),
      I1 => phy_bank(10),
      I2 => out_fifo_2,
      I3 => out_fifo_0(9),
      I4 => out_fifo_1,
      O => \gen_no_mirror.div_clk_loop[0].phy_bank_reg[1]_0\(5)
    );
\out_fifo_i_20__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(321),
      I1 => phy_wrdata(377),
      I2 => out_fifo_25,
      I3 => out_fifo_3(13),
      I4 => out_fifo_4,
      O => D2(5)
    );
\out_fifo_i_20__3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(328),
      I1 => phy_wrdata(376),
      I2 => out_fifo_25,
      I3 => out_fifo_5(5),
      I4 => out_fifo_6,
      O => \write_buffer.wr_buf_out_data_reg[456]\(5)
    );
\out_fifo_i_20__4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(336),
      I1 => phy_wrdata(376),
      I2 => out_fifo_25,
      I3 => out_fifo_7(5),
      I4 => out_fifo_8,
      O => \write_buffer.wr_buf_out_data_reg[464]\(5)
    );
\out_fifo_i_20__5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(344),
      I1 => phy_wrdata(376),
      I2 => out_fifo_25,
      I3 => out_fifo_9(5),
      I4 => out_fifo_10,
      O => \write_buffer.wr_buf_out_data_reg[472]\(5)
    );
\out_fifo_i_20__6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(353),
      I1 => phy_wrdata(377),
      I2 => out_fifo_25,
      I3 => out_fifo_12(13),
      I4 => out_fifo_13,
      O => \write_buffer.wr_buf_out_data_reg[481]\(5)
    );
\out_fifo_i_20__7\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(360),
      I1 => phy_wrdata(376),
      I2 => out_fifo_25,
      I3 => out_fifo_14(5),
      I4 => out_fifo_15,
      O => \write_buffer.wr_buf_out_data_reg[488]\(5)
    );
\out_fifo_i_20__8\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(368),
      I1 => phy_wrdata(376),
      I2 => out_fifo_25,
      I3 => out_fifo_16(5),
      I4 => out_fifo_17,
      O => \write_buffer.wr_buf_out_data_reg[496]\(5)
    );
\out_fifo_i_20__9\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(376),
      I1 => phy_wrdata(376),
      I2 => out_fifo_26,
      I3 => out_fifo_18(5),
      I4 => out_fifo_19,
      O => \write_buffer.wr_buf_out_data_reg[504]\(5)
    );
\out_fifo_i_21__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mc_bank(1),
      I1 => phy_bank(10),
      I2 => out_fifo_2,
      I3 => out_fifo_0(8),
      I4 => out_fifo_1,
      O => \gen_no_mirror.div_clk_loop[0].phy_bank_reg[1]_0\(4)
    );
\out_fifo_i_21__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(257),
      I1 => phy_wrdata(313),
      I2 => out_fifo_23,
      I3 => out_fifo_3(12),
      I4 => out_fifo_4,
      O => D2(4)
    );
\out_fifo_i_21__3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(264),
      I1 => phy_wrdata(312),
      I2 => out_fifo_23,
      I3 => out_fifo_5(4),
      I4 => out_fifo_6,
      O => \write_buffer.wr_buf_out_data_reg[456]\(4)
    );
\out_fifo_i_21__4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(272),
      I1 => phy_wrdata(312),
      I2 => out_fifo_24,
      I3 => out_fifo_7(4),
      I4 => out_fifo_8,
      O => \write_buffer.wr_buf_out_data_reg[464]\(4)
    );
\out_fifo_i_21__5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(280),
      I1 => phy_wrdata(312),
      I2 => out_fifo_24,
      I3 => out_fifo_9(4),
      I4 => out_fifo_10,
      O => \write_buffer.wr_buf_out_data_reg[472]\(4)
    );
\out_fifo_i_21__6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(289),
      I1 => phy_wrdata(313),
      I2 => out_fifo_24,
      I3 => out_fifo_12(12),
      I4 => out_fifo_13,
      O => \write_buffer.wr_buf_out_data_reg[481]\(4)
    );
\out_fifo_i_21__7\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(296),
      I1 => phy_wrdata(312),
      I2 => out_fifo_24,
      I3 => out_fifo_14(4),
      I4 => out_fifo_15,
      O => \write_buffer.wr_buf_out_data_reg[488]\(4)
    );
\out_fifo_i_21__8\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(304),
      I1 => phy_wrdata(312),
      I2 => out_fifo_24,
      I3 => out_fifo_16(4),
      I4 => out_fifo_17,
      O => \write_buffer.wr_buf_out_data_reg[496]\(4)
    );
\out_fifo_i_21__9\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(312),
      I1 => phy_wrdata(312),
      I2 => out_fifo_24,
      I3 => out_fifo_18(4),
      I4 => out_fifo_19,
      O => \write_buffer.wr_buf_out_data_reg[504]\(4)
    );
\out_fifo_i_22__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(193),
      I1 => phy_wrdata(249),
      I2 => out_fifo_22,
      I3 => out_fifo_3(11),
      I4 => out_fifo_4,
      O => D2(3)
    );
\out_fifo_i_22__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(200),
      I1 => phy_wrdata(248),
      I2 => out_fifo_22,
      I3 => out_fifo_5(3),
      I4 => out_fifo_6,
      O => \write_buffer.wr_buf_out_data_reg[456]\(3)
    );
\out_fifo_i_22__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(208),
      I1 => phy_wrdata(248),
      I2 => out_fifo_22,
      I3 => out_fifo_7(3),
      I4 => out_fifo_8,
      O => \write_buffer.wr_buf_out_data_reg[464]\(3)
    );
\out_fifo_i_22__3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(216),
      I1 => phy_wrdata(248),
      I2 => out_fifo_22,
      I3 => out_fifo_9(3),
      I4 => out_fifo_10,
      O => \write_buffer.wr_buf_out_data_reg[472]\(3)
    );
\out_fifo_i_22__4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(225),
      I1 => phy_wrdata(249),
      I2 => out_fifo_23,
      I3 => out_fifo_12(11),
      I4 => out_fifo_13,
      O => \write_buffer.wr_buf_out_data_reg[481]\(3)
    );
\out_fifo_i_22__5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(232),
      I1 => phy_wrdata(248),
      I2 => out_fifo_23,
      I3 => out_fifo_14(3),
      I4 => out_fifo_15,
      O => \write_buffer.wr_buf_out_data_reg[488]\(3)
    );
\out_fifo_i_22__6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(240),
      I1 => phy_wrdata(248),
      I2 => out_fifo_23,
      I3 => out_fifo_16(3),
      I4 => out_fifo_17,
      O => \write_buffer.wr_buf_out_data_reg[496]\(3)
    );
\out_fifo_i_22__7\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(248),
      I1 => phy_wrdata(248),
      I2 => out_fifo_23,
      I3 => out_fifo_18(3),
      I4 => out_fifo_19,
      O => \write_buffer.wr_buf_out_data_reg[504]\(3)
    );
\out_fifo_i_22__8\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"EEF0"
    )
        port map (
      I0 => phy_bank(11),
      I1 => out_fifo_31,
      I2 => out_fifo_0(7),
      I3 => out_fifo_1,
      O => \gen_no_mirror.div_clk_loop[0].phy_bank_reg[1]_0\(3)
    );
\out_fifo_i_23__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mc_bank(8),
      I1 => phy_bank(11),
      I2 => out_fifo_2,
      I3 => out_fifo_0(6),
      I4 => out_fifo_1,
      O => \gen_no_mirror.div_clk_loop[0].phy_bank_reg[1]_0\(2)
    );
\out_fifo_i_23__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(129),
      I1 => phy_wrdata(185),
      I2 => out_fifo_21,
      I3 => out_fifo_3(10),
      I4 => out_fifo_4,
      O => D2(2)
    );
\out_fifo_i_23__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(136),
      I1 => phy_wrdata(184),
      I2 => out_fifo_21,
      I3 => out_fifo_5(2),
      I4 => out_fifo_6,
      O => \write_buffer.wr_buf_out_data_reg[456]\(2)
    );
\out_fifo_i_23__3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(144),
      I1 => phy_wrdata(184),
      I2 => out_fifo_21,
      I3 => out_fifo_7(2),
      I4 => out_fifo_8,
      O => \write_buffer.wr_buf_out_data_reg[464]\(2)
    );
\out_fifo_i_23__4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(152),
      I1 => phy_wrdata(184),
      I2 => out_fifo_21,
      I3 => out_fifo_9(2),
      I4 => out_fifo_10,
      O => \write_buffer.wr_buf_out_data_reg[472]\(2)
    );
\out_fifo_i_23__5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(161),
      I1 => phy_wrdata(185),
      I2 => out_fifo_21,
      I3 => out_fifo_12(10),
      I4 => out_fifo_13,
      O => \write_buffer.wr_buf_out_data_reg[481]\(2)
    );
\out_fifo_i_23__6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(168),
      I1 => phy_wrdata(184),
      I2 => out_fifo_21,
      I3 => out_fifo_14(2),
      I4 => out_fifo_15,
      O => \write_buffer.wr_buf_out_data_reg[488]\(2)
    );
\out_fifo_i_23__7\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(176),
      I1 => phy_wrdata(184),
      I2 => out_fifo_22,
      I3 => out_fifo_16(2),
      I4 => out_fifo_17,
      O => \write_buffer.wr_buf_out_data_reg[496]\(2)
    );
\out_fifo_i_23__8\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(184),
      I1 => phy_wrdata(184),
      I2 => out_fifo_22,
      I3 => out_fifo_18(2),
      I4 => out_fifo_19,
      O => \write_buffer.wr_buf_out_data_reg[504]\(2)
    );
\out_fifo_i_24__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mc_bank(5),
      I1 => phy_bank(11),
      I2 => out_fifo_2,
      I3 => out_fifo_0(5),
      I4 => out_fifo_1,
      O => \gen_no_mirror.div_clk_loop[0].phy_bank_reg[1]_0\(1)
    );
\out_fifo_i_24__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(65),
      I1 => phy_wrdata(121),
      I2 => out_fifo_11,
      I3 => out_fifo_3(9),
      I4 => out_fifo_4,
      O => D2(1)
    );
\out_fifo_i_24__3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(72),
      I1 => phy_wrdata(120),
      I2 => out_fifo_11,
      I3 => out_fifo_5(1),
      I4 => out_fifo_6,
      O => \write_buffer.wr_buf_out_data_reg[456]\(1)
    );
\out_fifo_i_24__4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(80),
      I1 => phy_wrdata(120),
      I2 => out_fifo_20,
      I3 => out_fifo_7(1),
      I4 => out_fifo_8,
      O => \write_buffer.wr_buf_out_data_reg[464]\(1)
    );
\out_fifo_i_24__5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(88),
      I1 => phy_wrdata(120),
      I2 => out_fifo_20,
      I3 => out_fifo_9(1),
      I4 => out_fifo_10,
      O => \write_buffer.wr_buf_out_data_reg[472]\(1)
    );
\out_fifo_i_24__6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(97),
      I1 => phy_wrdata(121),
      I2 => out_fifo_20,
      I3 => out_fifo_12(9),
      I4 => out_fifo_13,
      O => \write_buffer.wr_buf_out_data_reg[481]\(1)
    );
\out_fifo_i_24__7\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(104),
      I1 => phy_wrdata(120),
      I2 => out_fifo_20,
      I3 => out_fifo_14(1),
      I4 => out_fifo_15,
      O => \write_buffer.wr_buf_out_data_reg[488]\(1)
    );
\out_fifo_i_24__8\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(112),
      I1 => phy_wrdata(120),
      I2 => out_fifo_20,
      I3 => out_fifo_16(1),
      I4 => out_fifo_17,
      O => \write_buffer.wr_buf_out_data_reg[496]\(1)
    );
\out_fifo_i_24__9\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(120),
      I1 => phy_wrdata(120),
      I2 => out_fifo_20,
      I3 => out_fifo_18(1),
      I4 => out_fifo_19,
      O => \write_buffer.wr_buf_out_data_reg[504]\(1)
    );
\out_fifo_i_25__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mc_bank(2),
      I1 => phy_bank(11),
      I2 => out_fifo_2,
      I3 => out_fifo_0(4),
      I4 => out_fifo_1,
      O => \gen_no_mirror.div_clk_loop[0].phy_bank_reg[1]_0\(0)
    );
\out_fifo_i_25__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(1),
      I1 => phy_wrdata(57),
      I2 => out_fifo_2,
      I3 => out_fifo_3(8),
      I4 => out_fifo_4,
      O => D2(0)
    );
\out_fifo_i_25__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(8),
      I1 => phy_wrdata(56),
      I2 => out_fifo_2,
      I3 => out_fifo_5(0),
      I4 => out_fifo_6,
      O => \write_buffer.wr_buf_out_data_reg[456]\(0)
    );
\out_fifo_i_25__3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(16),
      I1 => phy_wrdata(56),
      I2 => out_fifo_2,
      I3 => out_fifo_7(0),
      I4 => out_fifo_8,
      O => \write_buffer.wr_buf_out_data_reg[464]\(0)
    );
\out_fifo_i_25__4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(24),
      I1 => phy_wrdata(56),
      I2 => out_fifo_2,
      I3 => out_fifo_9(0),
      I4 => out_fifo_10,
      O => \write_buffer.wr_buf_out_data_reg[472]\(0)
    );
\out_fifo_i_25__5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(33),
      I1 => phy_wrdata(57),
      I2 => out_fifo_11,
      I3 => out_fifo_12(8),
      I4 => out_fifo_13,
      O => \write_buffer.wr_buf_out_data_reg[481]\(0)
    );
\out_fifo_i_25__6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(40),
      I1 => phy_wrdata(56),
      I2 => out_fifo_11,
      I3 => out_fifo_14(0),
      I4 => out_fifo_15,
      O => \write_buffer.wr_buf_out_data_reg[488]\(0)
    );
\out_fifo_i_25__7\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(48),
      I1 => phy_wrdata(56),
      I2 => out_fifo_11,
      I3 => out_fifo_16(0),
      I4 => out_fifo_17,
      O => \write_buffer.wr_buf_out_data_reg[496]\(0)
    );
\out_fifo_i_25__8\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(56),
      I1 => phy_wrdata(56),
      I2 => out_fifo_11,
      I3 => out_fifo_18(0),
      I4 => out_fifo_19,
      O => \write_buffer.wr_buf_out_data_reg[504]\(0)
    );
\out_fifo_i_26__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(450),
      I1 => phy_wrdata(506),
      I2 => out_fifo_27,
      I3 => out_fifo_3(23),
      I4 => out_fifo_4,
      O => \write_buffer.wr_buf_out_data_reg[450]\(7)
    );
\out_fifo_i_26__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(457),
      I1 => phy_wrdata(505),
      I2 => out_fifo_27,
      I3 => out_fifo_5(15),
      I4 => out_fifo_6,
      O => \write_buffer.wr_buf_out_data_reg[457]\(7)
    );
\out_fifo_i_26__3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(465),
      I1 => phy_wrdata(505),
      I2 => out_fifo_27,
      I3 => out_fifo_7(15),
      I4 => out_fifo_8,
      O => \write_buffer.wr_buf_out_data_reg[465]\(7)
    );
\out_fifo_i_26__4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(473),
      I1 => phy_wrdata(505),
      I2 => out_fifo_28,
      I3 => out_fifo_9(15),
      I4 => out_fifo_10,
      O => \write_buffer.wr_buf_out_data_reg[473]\(7)
    );
\out_fifo_i_26__5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(482),
      I1 => phy_wrdata(506),
      I2 => out_fifo_28,
      I3 => out_fifo_12(23),
      I4 => out_fifo_13,
      O => \write_buffer.wr_buf_out_data_reg[482]\(7)
    );
\out_fifo_i_26__6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(489),
      I1 => phy_wrdata(505),
      I2 => out_fifo_28,
      I3 => out_fifo_14(15),
      I4 => out_fifo_15,
      O => \write_buffer.wr_buf_out_data_reg[489]\(7)
    );
\out_fifo_i_26__7\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(497),
      I1 => phy_wrdata(505),
      I2 => out_fifo_28,
      I3 => out_fifo_16(15),
      I4 => out_fifo_17,
      O => \write_buffer.wr_buf_out_data_reg[497]\(7)
    );
\out_fifo_i_26__8\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(505),
      I1 => phy_wrdata(505),
      I2 => out_fifo_28,
      I3 => out_fifo_18(15),
      I4 => out_fifo_19,
      O => \write_buffer.wr_buf_out_data_reg[505]\(7)
    );
\out_fifo_i_26__9\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"EEF0"
    )
        port map (
      I0 => phy_bank(9),
      I1 => out_fifo_31,
      I2 => out_fifo_0(15),
      I3 => out_fifo_1,
      O => \gen_no_mirror.div_clk_loop[0].phy_bank_reg[0]_0\(3)
    );
\out_fifo_i_27__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mc_bank(6),
      I1 => phy_bank(9),
      I2 => out_fifo_2,
      I3 => out_fifo_0(14),
      I4 => out_fifo_1,
      O => \gen_no_mirror.div_clk_loop[0].phy_bank_reg[0]_0\(2)
    );
\out_fifo_i_27__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(386),
      I1 => phy_wrdata(442),
      I2 => out_fifo_26,
      I3 => out_fifo_3(22),
      I4 => out_fifo_4,
      O => \write_buffer.wr_buf_out_data_reg[450]\(6)
    );
\out_fifo_i_27__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(393),
      I1 => phy_wrdata(441),
      I2 => out_fifo_26,
      I3 => out_fifo_5(14),
      I4 => out_fifo_6,
      O => \write_buffer.wr_buf_out_data_reg[457]\(6)
    );
\out_fifo_i_27__3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(401),
      I1 => phy_wrdata(441),
      I2 => out_fifo_26,
      I3 => out_fifo_7(14),
      I4 => out_fifo_8,
      O => \write_buffer.wr_buf_out_data_reg[465]\(6)
    );
\out_fifo_i_27__4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(409),
      I1 => phy_wrdata(441),
      I2 => out_fifo_26,
      I3 => out_fifo_9(14),
      I4 => out_fifo_10,
      O => \write_buffer.wr_buf_out_data_reg[473]\(6)
    );
\out_fifo_i_27__5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(418),
      I1 => phy_wrdata(442),
      I2 => out_fifo_26,
      I3 => out_fifo_12(22),
      I4 => out_fifo_13,
      O => \write_buffer.wr_buf_out_data_reg[482]\(6)
    );
\out_fifo_i_27__6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(425),
      I1 => phy_wrdata(441),
      I2 => out_fifo_27,
      I3 => out_fifo_14(14),
      I4 => out_fifo_15,
      O => \write_buffer.wr_buf_out_data_reg[489]\(6)
    );
\out_fifo_i_27__7\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(433),
      I1 => phy_wrdata(441),
      I2 => out_fifo_27,
      I3 => out_fifo_16(14),
      I4 => out_fifo_17,
      O => \write_buffer.wr_buf_out_data_reg[497]\(6)
    );
\out_fifo_i_27__8\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(441),
      I1 => phy_wrdata(441),
      I2 => out_fifo_27,
      I3 => out_fifo_18(14),
      I4 => out_fifo_19,
      O => \write_buffer.wr_buf_out_data_reg[505]\(6)
    );
\out_fifo_i_28__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mc_bank(3),
      I1 => phy_bank(9),
      I2 => out_fifo_2,
      I3 => out_fifo_0(13),
      I4 => out_fifo_1,
      O => \gen_no_mirror.div_clk_loop[0].phy_bank_reg[0]_0\(1)
    );
\out_fifo_i_28__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(322),
      I1 => phy_wrdata(378),
      I2 => out_fifo_25,
      I3 => out_fifo_3(21),
      I4 => out_fifo_4,
      O => \write_buffer.wr_buf_out_data_reg[450]\(5)
    );
\out_fifo_i_28__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(329),
      I1 => phy_wrdata(377),
      I2 => out_fifo_25,
      I3 => out_fifo_5(13),
      I4 => out_fifo_6,
      O => \write_buffer.wr_buf_out_data_reg[457]\(5)
    );
\out_fifo_i_28__3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(337),
      I1 => phy_wrdata(377),
      I2 => out_fifo_25,
      I3 => out_fifo_7(13),
      I4 => out_fifo_8,
      O => \write_buffer.wr_buf_out_data_reg[465]\(5)
    );
\out_fifo_i_28__4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(345),
      I1 => phy_wrdata(377),
      I2 => out_fifo_25,
      I3 => out_fifo_9(13),
      I4 => out_fifo_10,
      O => \write_buffer.wr_buf_out_data_reg[473]\(5)
    );
\out_fifo_i_28__5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(354),
      I1 => phy_wrdata(378),
      I2 => out_fifo_25,
      I3 => out_fifo_12(21),
      I4 => out_fifo_13,
      O => \write_buffer.wr_buf_out_data_reg[482]\(5)
    );
\out_fifo_i_28__6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(361),
      I1 => phy_wrdata(377),
      I2 => out_fifo_25,
      I3 => out_fifo_14(13),
      I4 => out_fifo_15,
      O => \write_buffer.wr_buf_out_data_reg[489]\(5)
    );
\out_fifo_i_28__7\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(369),
      I1 => phy_wrdata(377),
      I2 => out_fifo_25,
      I3 => out_fifo_16(13),
      I4 => out_fifo_17,
      O => \write_buffer.wr_buf_out_data_reg[497]\(5)
    );
\out_fifo_i_28__8\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(377),
      I1 => phy_wrdata(377),
      I2 => out_fifo_26,
      I3 => out_fifo_18(13),
      I4 => out_fifo_19,
      O => \write_buffer.wr_buf_out_data_reg[505]\(5)
    );
\out_fifo_i_28__9\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => mc_cas_n(0),
      I1 => out_fifo_28,
      I2 => phy_cs_n(1),
      I3 => out_fifo_29(4),
      I4 => out_fifo_30,
      O => \cmd_pipe_plus.mc_cas_n_reg[1]\(0)
    );
\out_fifo_i_29__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mc_bank(0),
      I1 => phy_bank(9),
      I2 => out_fifo_2,
      I3 => out_fifo_0(12),
      I4 => out_fifo_1,
      O => \gen_no_mirror.div_clk_loop[0].phy_bank_reg[0]_0\(0)
    );
\out_fifo_i_29__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(258),
      I1 => phy_wrdata(314),
      I2 => out_fifo_23,
      I3 => out_fifo_3(20),
      I4 => out_fifo_4,
      O => \write_buffer.wr_buf_out_data_reg[450]\(4)
    );
\out_fifo_i_29__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(265),
      I1 => phy_wrdata(313),
      I2 => out_fifo_23,
      I3 => out_fifo_5(12),
      I4 => out_fifo_6,
      O => \write_buffer.wr_buf_out_data_reg[457]\(4)
    );
\out_fifo_i_29__3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(273),
      I1 => phy_wrdata(313),
      I2 => out_fifo_24,
      I3 => out_fifo_7(12),
      I4 => out_fifo_8,
      O => \write_buffer.wr_buf_out_data_reg[465]\(4)
    );
\out_fifo_i_29__4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(281),
      I1 => phy_wrdata(313),
      I2 => out_fifo_24,
      I3 => out_fifo_9(12),
      I4 => out_fifo_10,
      O => \write_buffer.wr_buf_out_data_reg[473]\(4)
    );
\out_fifo_i_29__5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(290),
      I1 => phy_wrdata(314),
      I2 => out_fifo_24,
      I3 => out_fifo_12(20),
      I4 => out_fifo_13,
      O => \write_buffer.wr_buf_out_data_reg[482]\(4)
    );
\out_fifo_i_29__6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(297),
      I1 => phy_wrdata(313),
      I2 => out_fifo_24,
      I3 => out_fifo_14(12),
      I4 => out_fifo_15,
      O => \write_buffer.wr_buf_out_data_reg[489]\(4)
    );
\out_fifo_i_29__7\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(305),
      I1 => phy_wrdata(313),
      I2 => out_fifo_24,
      I3 => out_fifo_16(12),
      I4 => out_fifo_17,
      O => \write_buffer.wr_buf_out_data_reg[497]\(4)
    );
\out_fifo_i_29__8\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(313),
      I1 => phy_wrdata(313),
      I2 => out_fifo_24,
      I3 => out_fifo_18(12),
      I4 => out_fifo_19,
      O => \write_buffer.wr_buf_out_data_reg[505]\(4)
    );
\out_fifo_i_30__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(194),
      I1 => phy_wrdata(250),
      I2 => out_fifo_22,
      I3 => out_fifo_3(19),
      I4 => out_fifo_4,
      O => \write_buffer.wr_buf_out_data_reg[450]\(3)
    );
\out_fifo_i_30__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(201),
      I1 => phy_wrdata(249),
      I2 => out_fifo_22,
      I3 => out_fifo_5(11),
      I4 => out_fifo_6,
      O => \write_buffer.wr_buf_out_data_reg[457]\(3)
    );
\out_fifo_i_30__3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(209),
      I1 => phy_wrdata(249),
      I2 => out_fifo_22,
      I3 => out_fifo_7(11),
      I4 => out_fifo_8,
      O => \write_buffer.wr_buf_out_data_reg[465]\(3)
    );
\out_fifo_i_30__4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(217),
      I1 => phy_wrdata(249),
      I2 => out_fifo_22,
      I3 => out_fifo_9(11),
      I4 => out_fifo_10,
      O => \write_buffer.wr_buf_out_data_reg[473]\(3)
    );
\out_fifo_i_30__5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(226),
      I1 => phy_wrdata(250),
      I2 => out_fifo_23,
      I3 => out_fifo_12(19),
      I4 => out_fifo_13,
      O => \write_buffer.wr_buf_out_data_reg[482]\(3)
    );
\out_fifo_i_30__6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(233),
      I1 => phy_wrdata(249),
      I2 => out_fifo_23,
      I3 => out_fifo_14(11),
      I4 => out_fifo_15,
      O => \write_buffer.wr_buf_out_data_reg[489]\(3)
    );
\out_fifo_i_30__7\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(241),
      I1 => phy_wrdata(249),
      I2 => out_fifo_23,
      I3 => out_fifo_16(11),
      I4 => out_fifo_17,
      O => \write_buffer.wr_buf_out_data_reg[497]\(3)
    );
\out_fifo_i_30__8\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(249),
      I1 => phy_wrdata(249),
      I2 => out_fifo_23,
      I3 => out_fifo_18(11),
      I4 => out_fifo_19,
      O => \write_buffer.wr_buf_out_data_reg[505]\(3)
    );
\out_fifo_i_30__9\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"EEF0"
    )
        port map (
      I0 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[10]\,
      I1 => out_fifo_31,
      I2 => mem_out(7),
      I3 => out_fifo,
      O => D3(3)
    );
\out_fifo_i_31__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mc_address(33),
      I1 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[10]\,
      I2 => out_fifo_2,
      I3 => mem_out(6),
      I4 => out_fifo,
      O => D3(2)
    );
\out_fifo_i_31__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(130),
      I1 => phy_wrdata(186),
      I2 => out_fifo_21,
      I3 => out_fifo_3(18),
      I4 => out_fifo_4,
      O => \write_buffer.wr_buf_out_data_reg[450]\(2)
    );
\out_fifo_i_31__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(137),
      I1 => phy_wrdata(185),
      I2 => out_fifo_21,
      I3 => out_fifo_5(10),
      I4 => out_fifo_6,
      O => \write_buffer.wr_buf_out_data_reg[457]\(2)
    );
\out_fifo_i_31__3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(145),
      I1 => phy_wrdata(185),
      I2 => out_fifo_21,
      I3 => out_fifo_7(10),
      I4 => out_fifo_8,
      O => \write_buffer.wr_buf_out_data_reg[465]\(2)
    );
\out_fifo_i_31__4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(153),
      I1 => phy_wrdata(185),
      I2 => out_fifo_21,
      I3 => out_fifo_9(10),
      I4 => out_fifo_10,
      O => \write_buffer.wr_buf_out_data_reg[473]\(2)
    );
\out_fifo_i_31__5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(162),
      I1 => phy_wrdata(186),
      I2 => out_fifo_21,
      I3 => out_fifo_12(18),
      I4 => out_fifo_13,
      O => \write_buffer.wr_buf_out_data_reg[482]\(2)
    );
\out_fifo_i_31__6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(169),
      I1 => phy_wrdata(185),
      I2 => out_fifo_21,
      I3 => out_fifo_14(10),
      I4 => out_fifo_15,
      O => \write_buffer.wr_buf_out_data_reg[489]\(2)
    );
\out_fifo_i_31__7\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(177),
      I1 => phy_wrdata(185),
      I2 => out_fifo_22,
      I3 => out_fifo_16(10),
      I4 => out_fifo_17,
      O => \write_buffer.wr_buf_out_data_reg[497]\(2)
    );
\out_fifo_i_31__8\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(185),
      I1 => phy_wrdata(185),
      I2 => out_fifo_22,
      I3 => out_fifo_18(10),
      I4 => out_fifo_19,
      O => \write_buffer.wr_buf_out_data_reg[505]\(2)
    );
\out_fifo_i_32__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mc_address(22),
      I1 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[10]\,
      I2 => phy_ctl_wr_i1_reg,
      I3 => mem_out(5),
      I4 => out_fifo,
      O => D3(1)
    );
\out_fifo_i_32__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(66),
      I1 => phy_wrdata(122),
      I2 => out_fifo_11,
      I3 => out_fifo_3(17),
      I4 => out_fifo_4,
      O => \write_buffer.wr_buf_out_data_reg[450]\(1)
    );
\out_fifo_i_32__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(73),
      I1 => phy_wrdata(121),
      I2 => out_fifo_11,
      I3 => out_fifo_5(9),
      I4 => out_fifo_6,
      O => \write_buffer.wr_buf_out_data_reg[457]\(1)
    );
\out_fifo_i_32__3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(81),
      I1 => phy_wrdata(121),
      I2 => out_fifo_20,
      I3 => out_fifo_7(9),
      I4 => out_fifo_8,
      O => \write_buffer.wr_buf_out_data_reg[465]\(1)
    );
\out_fifo_i_32__4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(89),
      I1 => phy_wrdata(121),
      I2 => out_fifo_20,
      I3 => out_fifo_9(9),
      I4 => out_fifo_10,
      O => \write_buffer.wr_buf_out_data_reg[473]\(1)
    );
\out_fifo_i_32__5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(98),
      I1 => phy_wrdata(122),
      I2 => out_fifo_20,
      I3 => out_fifo_12(17),
      I4 => out_fifo_13,
      O => \write_buffer.wr_buf_out_data_reg[482]\(1)
    );
\out_fifo_i_32__6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(105),
      I1 => phy_wrdata(121),
      I2 => out_fifo_20,
      I3 => out_fifo_14(9),
      I4 => out_fifo_15,
      O => \write_buffer.wr_buf_out_data_reg[489]\(1)
    );
\out_fifo_i_32__7\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(113),
      I1 => phy_wrdata(121),
      I2 => out_fifo_20,
      I3 => out_fifo_16(9),
      I4 => out_fifo_17,
      O => \write_buffer.wr_buf_out_data_reg[497]\(1)
    );
\out_fifo_i_32__8\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(121),
      I1 => phy_wrdata(121),
      I2 => out_fifo_20,
      I3 => out_fifo_18(9),
      I4 => out_fifo_19,
      O => \write_buffer.wr_buf_out_data_reg[505]\(1)
    );
\out_fifo_i_32__9\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => mc_ras_n(0),
      I1 => out_fifo_28,
      I2 => phy_ras_n(1),
      I3 => out_fifo_29(6),
      I4 => out_fifo_30,
      O => \cmd_pipe_plus.mc_ras_n_reg[1]\(1)
    );
\out_fifo_i_33__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mc_address(10),
      I1 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[10]\,
      I2 => phy_ctl_wr_i1_reg,
      I3 => mem_out(4),
      I4 => out_fifo,
      O => D3(0)
    );
\out_fifo_i_33__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(2),
      I1 => phy_wrdata(58),
      I2 => out_fifo_2,
      I3 => out_fifo_3(16),
      I4 => out_fifo_4,
      O => \write_buffer.wr_buf_out_data_reg[450]\(0)
    );
\out_fifo_i_33__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(9),
      I1 => phy_wrdata(57),
      I2 => out_fifo_2,
      I3 => out_fifo_5(8),
      I4 => out_fifo_6,
      O => \write_buffer.wr_buf_out_data_reg[457]\(0)
    );
\out_fifo_i_33__3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(17),
      I1 => phy_wrdata(57),
      I2 => out_fifo_2,
      I3 => out_fifo_7(8),
      I4 => out_fifo_8,
      O => \write_buffer.wr_buf_out_data_reg[465]\(0)
    );
\out_fifo_i_33__4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(25),
      I1 => phy_wrdata(57),
      I2 => out_fifo_2,
      I3 => out_fifo_9(8),
      I4 => out_fifo_10,
      O => \write_buffer.wr_buf_out_data_reg[473]\(0)
    );
\out_fifo_i_33__5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(34),
      I1 => phy_wrdata(58),
      I2 => out_fifo_11,
      I3 => out_fifo_12(16),
      I4 => out_fifo_13,
      O => \write_buffer.wr_buf_out_data_reg[482]\(0)
    );
\out_fifo_i_33__6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(41),
      I1 => phy_wrdata(57),
      I2 => out_fifo_11,
      I3 => out_fifo_14(8),
      I4 => out_fifo_15,
      O => \write_buffer.wr_buf_out_data_reg[489]\(0)
    );
\out_fifo_i_33__7\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(49),
      I1 => phy_wrdata(57),
      I2 => out_fifo_11,
      I3 => out_fifo_16(8),
      I4 => out_fifo_17,
      O => \write_buffer.wr_buf_out_data_reg[497]\(0)
    );
\out_fifo_i_33__8\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(57),
      I1 => phy_wrdata(57),
      I2 => out_fifo_11,
      I3 => out_fifo_18(8),
      I4 => out_fifo_19,
      O => \write_buffer.wr_buf_out_data_reg[505]\(0)
    );
\out_fifo_i_34__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(451),
      I1 => phy_wrdata(507),
      I2 => out_fifo_27,
      I3 => out_fifo_3(31),
      I4 => out_fifo_4,
      O => \write_buffer.wr_buf_out_data_reg[451]\(7)
    );
\out_fifo_i_34__3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(458),
      I1 => phy_wrdata(506),
      I2 => out_fifo_27,
      I3 => out_fifo_5(23),
      I4 => out_fifo_6,
      O => \write_buffer.wr_buf_out_data_reg[458]\(7)
    );
\out_fifo_i_34__4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(466),
      I1 => phy_wrdata(506),
      I2 => out_fifo_27,
      I3 => out_fifo_7(23),
      I4 => out_fifo_8,
      O => \write_buffer.wr_buf_out_data_reg[466]\(7)
    );
\out_fifo_i_34__5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(474),
      I1 => phy_wrdata(506),
      I2 => out_fifo_28,
      I3 => out_fifo_9(23),
      I4 => out_fifo_10,
      O => \write_buffer.wr_buf_out_data_reg[474]\(7)
    );
\out_fifo_i_34__6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(483),
      I1 => phy_wrdata(507),
      I2 => out_fifo_28,
      I3 => out_fifo_12(31),
      I4 => out_fifo_13,
      O => \write_buffer.wr_buf_out_data_reg[483]\(7)
    );
\out_fifo_i_34__7\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(490),
      I1 => phy_wrdata(506),
      I2 => out_fifo_28,
      I3 => out_fifo_14(23),
      I4 => out_fifo_15,
      O => \write_buffer.wr_buf_out_data_reg[490]\(7)
    );
\out_fifo_i_34__8\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(498),
      I1 => phy_wrdata(506),
      I2 => out_fifo_28,
      I3 => out_fifo_16(23),
      I4 => out_fifo_17,
      O => \write_buffer.wr_buf_out_data_reg[498]\(7)
    );
\out_fifo_i_34__9\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(506),
      I1 => phy_wrdata(506),
      I2 => out_fifo_28,
      I3 => out_fifo_18(23),
      I4 => out_fifo_19,
      O => \write_buffer.wr_buf_out_data_reg[506]\(7)
    );
\out_fifo_i_35__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(387),
      I1 => phy_wrdata(443),
      I2 => out_fifo_26,
      I3 => out_fifo_3(30),
      I4 => out_fifo_4,
      O => \write_buffer.wr_buf_out_data_reg[451]\(6)
    );
\out_fifo_i_35__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(394),
      I1 => phy_wrdata(442),
      I2 => out_fifo_26,
      I3 => out_fifo_5(22),
      I4 => out_fifo_6,
      O => \write_buffer.wr_buf_out_data_reg[458]\(6)
    );
\out_fifo_i_35__3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(402),
      I1 => phy_wrdata(442),
      I2 => out_fifo_26,
      I3 => out_fifo_7(22),
      I4 => out_fifo_8,
      O => \write_buffer.wr_buf_out_data_reg[466]\(6)
    );
\out_fifo_i_35__4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(410),
      I1 => phy_wrdata(442),
      I2 => out_fifo_26,
      I3 => out_fifo_9(22),
      I4 => out_fifo_10,
      O => \write_buffer.wr_buf_out_data_reg[474]\(6)
    );
\out_fifo_i_35__5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(419),
      I1 => phy_wrdata(443),
      I2 => out_fifo_27,
      I3 => out_fifo_12(30),
      I4 => out_fifo_13,
      O => \write_buffer.wr_buf_out_data_reg[483]\(6)
    );
\out_fifo_i_35__6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(426),
      I1 => phy_wrdata(442),
      I2 => out_fifo_27,
      I3 => out_fifo_14(22),
      I4 => out_fifo_15,
      O => \write_buffer.wr_buf_out_data_reg[490]\(6)
    );
\out_fifo_i_35__7\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(434),
      I1 => phy_wrdata(442),
      I2 => out_fifo_27,
      I3 => out_fifo_16(22),
      I4 => out_fifo_17,
      O => \write_buffer.wr_buf_out_data_reg[498]\(6)
    );
\out_fifo_i_35__8\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(442),
      I1 => phy_wrdata(442),
      I2 => out_fifo_27,
      I3 => out_fifo_18(22),
      I4 => out_fifo_19,
      O => \write_buffer.wr_buf_out_data_reg[506]\(6)
    );
\out_fifo_i_36__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(323),
      I1 => phy_wrdata(379),
      I2 => out_fifo_25,
      I3 => out_fifo_3(29),
      I4 => out_fifo_4,
      O => \write_buffer.wr_buf_out_data_reg[451]\(5)
    );
\out_fifo_i_36__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(330),
      I1 => phy_wrdata(378),
      I2 => out_fifo_25,
      I3 => out_fifo_5(21),
      I4 => out_fifo_6,
      O => \write_buffer.wr_buf_out_data_reg[458]\(5)
    );
\out_fifo_i_36__3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(338),
      I1 => phy_wrdata(378),
      I2 => out_fifo_25,
      I3 => out_fifo_7(21),
      I4 => out_fifo_8,
      O => \write_buffer.wr_buf_out_data_reg[466]\(5)
    );
\out_fifo_i_36__4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(346),
      I1 => phy_wrdata(378),
      I2 => out_fifo_25,
      I3 => out_fifo_9(21),
      I4 => out_fifo_10,
      O => \write_buffer.wr_buf_out_data_reg[474]\(5)
    );
\out_fifo_i_36__5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(355),
      I1 => phy_wrdata(379),
      I2 => out_fifo_25,
      I3 => out_fifo_12(29),
      I4 => out_fifo_13,
      O => \write_buffer.wr_buf_out_data_reg[483]\(5)
    );
\out_fifo_i_36__6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(362),
      I1 => phy_wrdata(378),
      I2 => out_fifo_25,
      I3 => out_fifo_14(21),
      I4 => out_fifo_15,
      O => \write_buffer.wr_buf_out_data_reg[490]\(5)
    );
\out_fifo_i_36__7\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(370),
      I1 => phy_wrdata(378),
      I2 => out_fifo_26,
      I3 => out_fifo_16(21),
      I4 => out_fifo_17,
      O => \write_buffer.wr_buf_out_data_reg[498]\(5)
    );
\out_fifo_i_36__8\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(378),
      I1 => phy_wrdata(378),
      I2 => out_fifo_26,
      I3 => out_fifo_18(21),
      I4 => out_fifo_19,
      O => \write_buffer.wr_buf_out_data_reg[506]\(5)
    );
\out_fifo_i_36__9\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => mc_cas_n(0),
      I1 => out_fifo_28,
      I2 => phy_cas_n(1),
      I3 => out_fifo_29(5),
      I4 => out_fifo_30,
      O => \cmd_pipe_plus.mc_ras_n_reg[1]\(0)
    );
\out_fifo_i_37__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(259),
      I1 => phy_wrdata(315),
      I2 => out_fifo_23,
      I3 => out_fifo_3(28),
      I4 => out_fifo_4,
      O => \write_buffer.wr_buf_out_data_reg[451]\(4)
    );
\out_fifo_i_37__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(266),
      I1 => phy_wrdata(314),
      I2 => out_fifo_23,
      I3 => out_fifo_5(20),
      I4 => out_fifo_6,
      O => \write_buffer.wr_buf_out_data_reg[458]\(4)
    );
\out_fifo_i_37__3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(274),
      I1 => phy_wrdata(314),
      I2 => out_fifo_24,
      I3 => out_fifo_7(20),
      I4 => out_fifo_8,
      O => \write_buffer.wr_buf_out_data_reg[466]\(4)
    );
\out_fifo_i_37__4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(282),
      I1 => phy_wrdata(314),
      I2 => out_fifo_24,
      I3 => out_fifo_9(20),
      I4 => out_fifo_10,
      O => \write_buffer.wr_buf_out_data_reg[474]\(4)
    );
\out_fifo_i_37__5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(291),
      I1 => phy_wrdata(315),
      I2 => out_fifo_24,
      I3 => out_fifo_12(28),
      I4 => out_fifo_13,
      O => \write_buffer.wr_buf_out_data_reg[483]\(4)
    );
\out_fifo_i_37__6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(298),
      I1 => phy_wrdata(314),
      I2 => out_fifo_24,
      I3 => out_fifo_14(20),
      I4 => out_fifo_15,
      O => \write_buffer.wr_buf_out_data_reg[490]\(4)
    );
\out_fifo_i_37__7\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(306),
      I1 => phy_wrdata(314),
      I2 => out_fifo_24,
      I3 => out_fifo_16(20),
      I4 => out_fifo_17,
      O => \write_buffer.wr_buf_out_data_reg[498]\(4)
    );
\out_fifo_i_37__8\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(314),
      I1 => phy_wrdata(314),
      I2 => out_fifo_24,
      I3 => out_fifo_18(20),
      I4 => out_fifo_19,
      O => \write_buffer.wr_buf_out_data_reg[506]\(4)
    );
\out_fifo_i_38__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(195),
      I1 => phy_wrdata(251),
      I2 => out_fifo_22,
      I3 => out_fifo_3(27),
      I4 => out_fifo_4,
      O => \write_buffer.wr_buf_out_data_reg[451]\(3)
    );
\out_fifo_i_38__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(202),
      I1 => phy_wrdata(250),
      I2 => out_fifo_22,
      I3 => out_fifo_5(19),
      I4 => out_fifo_6,
      O => \write_buffer.wr_buf_out_data_reg[458]\(3)
    );
\out_fifo_i_38__3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(210),
      I1 => phy_wrdata(250),
      I2 => out_fifo_22,
      I3 => out_fifo_7(19),
      I4 => out_fifo_8,
      O => \write_buffer.wr_buf_out_data_reg[466]\(3)
    );
\out_fifo_i_38__4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(218),
      I1 => phy_wrdata(250),
      I2 => out_fifo_22,
      I3 => out_fifo_9(19),
      I4 => out_fifo_10,
      O => \write_buffer.wr_buf_out_data_reg[474]\(3)
    );
\out_fifo_i_38__5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(227),
      I1 => phy_wrdata(251),
      I2 => out_fifo_23,
      I3 => out_fifo_12(27),
      I4 => out_fifo_13,
      O => \write_buffer.wr_buf_out_data_reg[483]\(3)
    );
\out_fifo_i_38__6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(234),
      I1 => phy_wrdata(250),
      I2 => out_fifo_23,
      I3 => out_fifo_14(19),
      I4 => out_fifo_15,
      O => \write_buffer.wr_buf_out_data_reg[490]\(3)
    );
\out_fifo_i_38__7\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(242),
      I1 => phy_wrdata(250),
      I2 => out_fifo_23,
      I3 => out_fifo_16(19),
      I4 => out_fifo_17,
      O => \write_buffer.wr_buf_out_data_reg[498]\(3)
    );
\out_fifo_i_38__8\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(250),
      I1 => phy_wrdata(250),
      I2 => out_fifo_23,
      I3 => out_fifo_18(19),
      I4 => out_fifo_19,
      O => \write_buffer.wr_buf_out_data_reg[506]\(3)
    );
\out_fifo_i_38__9\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"EEF0"
    )
        port map (
      I0 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[4]\,
      I1 => out_fifo_31,
      I2 => mem_out(11),
      I3 => out_fifo,
      O => D4(3)
    );
\out_fifo_i_39__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mc_address(27),
      I1 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[4]\,
      I2 => out_fifo_2,
      I3 => mem_out(10),
      I4 => out_fifo,
      O => D4(2)
    );
\out_fifo_i_39__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(131),
      I1 => phy_wrdata(187),
      I2 => out_fifo_21,
      I3 => out_fifo_3(26),
      I4 => out_fifo_4,
      O => \write_buffer.wr_buf_out_data_reg[451]\(2)
    );
\out_fifo_i_39__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(138),
      I1 => phy_wrdata(186),
      I2 => out_fifo_21,
      I3 => out_fifo_5(18),
      I4 => out_fifo_6,
      O => \write_buffer.wr_buf_out_data_reg[458]\(2)
    );
\out_fifo_i_39__3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(146),
      I1 => phy_wrdata(186),
      I2 => out_fifo_21,
      I3 => out_fifo_7(18),
      I4 => out_fifo_8,
      O => \write_buffer.wr_buf_out_data_reg[466]\(2)
    );
\out_fifo_i_39__4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(154),
      I1 => phy_wrdata(186),
      I2 => out_fifo_21,
      I3 => out_fifo_9(18),
      I4 => out_fifo_10,
      O => \write_buffer.wr_buf_out_data_reg[474]\(2)
    );
\out_fifo_i_39__5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(163),
      I1 => phy_wrdata(187),
      I2 => out_fifo_21,
      I3 => out_fifo_12(26),
      I4 => out_fifo_13,
      O => \write_buffer.wr_buf_out_data_reg[483]\(2)
    );
\out_fifo_i_39__6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(170),
      I1 => phy_wrdata(186),
      I2 => out_fifo_21,
      I3 => out_fifo_14(18),
      I4 => out_fifo_15,
      O => \write_buffer.wr_buf_out_data_reg[490]\(2)
    );
\out_fifo_i_39__7\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(178),
      I1 => phy_wrdata(186),
      I2 => out_fifo_22,
      I3 => out_fifo_16(18),
      I4 => out_fifo_17,
      O => \write_buffer.wr_buf_out_data_reg[498]\(2)
    );
\out_fifo_i_39__8\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(186),
      I1 => phy_wrdata(186),
      I2 => out_fifo_22,
      I3 => out_fifo_18(18),
      I4 => out_fifo_19,
      O => \write_buffer.wr_buf_out_data_reg[506]\(2)
    );
\out_fifo_i_40__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mc_address(16),
      I1 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[4]\,
      I2 => phy_ctl_wr_i1_reg,
      I3 => mem_out(9),
      I4 => out_fifo,
      O => D4(1)
    );
\out_fifo_i_40__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(67),
      I1 => phy_wrdata(123),
      I2 => out_fifo_11,
      I3 => out_fifo_3(25),
      I4 => out_fifo_4,
      O => \write_buffer.wr_buf_out_data_reg[451]\(1)
    );
\out_fifo_i_40__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(74),
      I1 => phy_wrdata(122),
      I2 => out_fifo_11,
      I3 => out_fifo_5(17),
      I4 => out_fifo_6,
      O => \write_buffer.wr_buf_out_data_reg[458]\(1)
    );
\out_fifo_i_40__3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(82),
      I1 => phy_wrdata(122),
      I2 => out_fifo_20,
      I3 => out_fifo_7(17),
      I4 => out_fifo_8,
      O => \write_buffer.wr_buf_out_data_reg[466]\(1)
    );
\out_fifo_i_40__4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(90),
      I1 => phy_wrdata(122),
      I2 => out_fifo_20,
      I3 => out_fifo_9(17),
      I4 => out_fifo_10,
      O => \write_buffer.wr_buf_out_data_reg[474]\(1)
    );
\out_fifo_i_40__5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(99),
      I1 => phy_wrdata(123),
      I2 => out_fifo_20,
      I3 => out_fifo_12(25),
      I4 => out_fifo_13,
      O => \write_buffer.wr_buf_out_data_reg[483]\(1)
    );
\out_fifo_i_40__6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(106),
      I1 => phy_wrdata(122),
      I2 => out_fifo_20,
      I3 => out_fifo_14(17),
      I4 => out_fifo_15,
      O => \write_buffer.wr_buf_out_data_reg[490]\(1)
    );
\out_fifo_i_40__7\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(114),
      I1 => phy_wrdata(122),
      I2 => out_fifo_20,
      I3 => out_fifo_16(17),
      I4 => out_fifo_17,
      O => \write_buffer.wr_buf_out_data_reg[498]\(1)
    );
\out_fifo_i_40__8\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(122),
      I1 => phy_wrdata(122),
      I2 => out_fifo_20,
      I3 => out_fifo_18(17),
      I4 => out_fifo_19,
      O => \write_buffer.wr_buf_out_data_reg[506]\(1)
    );
\out_fifo_i_40__9\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => mc_we_n(0),
      I1 => out_fifo_31,
      I2 => phy_we_n(1),
      I3 => out_fifo_29(7),
      I4 => out_fifo_30,
      O => \cmd_pipe_plus.mc_we_n_reg[1]\(0)
    );
\out_fifo_i_41__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mc_address(4),
      I1 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[4]\,
      I2 => phy_ctl_wr_i1_reg,
      I3 => mem_out(8),
      I4 => out_fifo,
      O => D4(0)
    );
\out_fifo_i_41__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(3),
      I1 => phy_wrdata(59),
      I2 => out_fifo_2,
      I3 => out_fifo_3(24),
      I4 => out_fifo_4,
      O => \write_buffer.wr_buf_out_data_reg[451]\(0)
    );
\out_fifo_i_41__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(10),
      I1 => phy_wrdata(58),
      I2 => out_fifo_2,
      I3 => out_fifo_5(16),
      I4 => out_fifo_6,
      O => \write_buffer.wr_buf_out_data_reg[458]\(0)
    );
\out_fifo_i_41__3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(18),
      I1 => phy_wrdata(58),
      I2 => out_fifo_2,
      I3 => out_fifo_7(16),
      I4 => out_fifo_8,
      O => \write_buffer.wr_buf_out_data_reg[466]\(0)
    );
\out_fifo_i_41__4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(26),
      I1 => phy_wrdata(58),
      I2 => out_fifo_2,
      I3 => out_fifo_9(16),
      I4 => out_fifo_10,
      O => \write_buffer.wr_buf_out_data_reg[474]\(0)
    );
\out_fifo_i_41__5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(35),
      I1 => phy_wrdata(59),
      I2 => out_fifo_11,
      I3 => out_fifo_12(24),
      I4 => out_fifo_13,
      O => \write_buffer.wr_buf_out_data_reg[483]\(0)
    );
\out_fifo_i_41__6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(42),
      I1 => phy_wrdata(58),
      I2 => out_fifo_11,
      I3 => out_fifo_14(16),
      I4 => out_fifo_15,
      O => \write_buffer.wr_buf_out_data_reg[490]\(0)
    );
\out_fifo_i_41__7\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(50),
      I1 => phy_wrdata(58),
      I2 => out_fifo_11,
      I3 => out_fifo_16(16),
      I4 => out_fifo_17,
      O => \write_buffer.wr_buf_out_data_reg[498]\(0)
    );
\out_fifo_i_41__8\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(58),
      I1 => phy_wrdata(58),
      I2 => out_fifo_11,
      I3 => out_fifo_18(16),
      I4 => out_fifo_19,
      O => \write_buffer.wr_buf_out_data_reg[506]\(0)
    );
\out_fifo_i_42__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(452),
      I1 => phy_wrdata(508),
      I2 => out_fifo_27,
      I3 => out_fifo_3(39),
      I4 => out_fifo_4,
      O => \write_buffer.wr_buf_out_data_reg[452]\(7)
    );
\out_fifo_i_42__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(459),
      I1 => phy_wrdata(507),
      I2 => out_fifo_27,
      I3 => out_fifo_5(31),
      I4 => out_fifo_6,
      O => \write_buffer.wr_buf_out_data_reg[459]\(7)
    );
\out_fifo_i_42__3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(467),
      I1 => phy_wrdata(507),
      I2 => out_fifo_27,
      I3 => out_fifo_7(31),
      I4 => out_fifo_8,
      O => \write_buffer.wr_buf_out_data_reg[467]\(7)
    );
\out_fifo_i_42__4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(475),
      I1 => phy_wrdata(507),
      I2 => out_fifo_28,
      I3 => out_fifo_9(31),
      I4 => out_fifo_10,
      O => \write_buffer.wr_buf_out_data_reg[475]\(7)
    );
\out_fifo_i_42__5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(484),
      I1 => phy_wrdata(508),
      I2 => out_fifo_28,
      I3 => out_fifo_12(39),
      I4 => out_fifo_13,
      O => \write_buffer.wr_buf_out_data_reg[484]\(7)
    );
\out_fifo_i_42__6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(491),
      I1 => phy_wrdata(507),
      I2 => out_fifo_28,
      I3 => out_fifo_14(31),
      I4 => out_fifo_15,
      O => \write_buffer.wr_buf_out_data_reg[491]\(7)
    );
\out_fifo_i_42__7\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(499),
      I1 => phy_wrdata(507),
      I2 => out_fifo_28,
      I3 => out_fifo_16(31),
      I4 => out_fifo_17,
      O => \write_buffer.wr_buf_out_data_reg[499]\(7)
    );
\out_fifo_i_42__8\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(507),
      I1 => phy_wrdata(507),
      I2 => out_fifo_28,
      I3 => out_fifo_18(31),
      I4 => out_fifo_19,
      O => \write_buffer.wr_buf_out_data_reg[507]\(7)
    );
\out_fifo_i_42__9\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"EEF0"
    )
        port map (
      I0 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[3]\,
      I1 => out_fifo_31,
      I2 => mem_out(15),
      I3 => out_fifo,
      O => D5(3)
    );
\out_fifo_i_43__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mc_address(26),
      I1 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[3]\,
      I2 => out_fifo_2,
      I3 => mem_out(14),
      I4 => out_fifo,
      O => D5(2)
    );
\out_fifo_i_43__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(388),
      I1 => phy_wrdata(444),
      I2 => out_fifo_26,
      I3 => out_fifo_3(38),
      I4 => out_fifo_4,
      O => \write_buffer.wr_buf_out_data_reg[452]\(6)
    );
\out_fifo_i_43__3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(395),
      I1 => phy_wrdata(443),
      I2 => out_fifo_26,
      I3 => out_fifo_5(30),
      I4 => out_fifo_6,
      O => \write_buffer.wr_buf_out_data_reg[459]\(6)
    );
\out_fifo_i_43__4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(403),
      I1 => phy_wrdata(443),
      I2 => out_fifo_26,
      I3 => out_fifo_7(30),
      I4 => out_fifo_8,
      O => \write_buffer.wr_buf_out_data_reg[467]\(6)
    );
\out_fifo_i_43__5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(411),
      I1 => phy_wrdata(443),
      I2 => out_fifo_26,
      I3 => out_fifo_9(30),
      I4 => out_fifo_10,
      O => \write_buffer.wr_buf_out_data_reg[475]\(6)
    );
\out_fifo_i_43__6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(420),
      I1 => phy_wrdata(444),
      I2 => out_fifo_27,
      I3 => out_fifo_12(38),
      I4 => out_fifo_13,
      O => \write_buffer.wr_buf_out_data_reg[484]\(6)
    );
\out_fifo_i_43__7\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(427),
      I1 => phy_wrdata(443),
      I2 => out_fifo_27,
      I3 => out_fifo_14(30),
      I4 => out_fifo_15,
      O => \write_buffer.wr_buf_out_data_reg[491]\(6)
    );
\out_fifo_i_43__8\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(435),
      I1 => phy_wrdata(443),
      I2 => out_fifo_27,
      I3 => out_fifo_16(30),
      I4 => out_fifo_17,
      O => \write_buffer.wr_buf_out_data_reg[499]\(6)
    );
\out_fifo_i_43__9\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(443),
      I1 => phy_wrdata(443),
      I2 => out_fifo_27,
      I3 => out_fifo_18(30),
      I4 => out_fifo_19,
      O => \write_buffer.wr_buf_out_data_reg[507]\(6)
    );
\out_fifo_i_44__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mc_address(15),
      I1 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[3]\,
      I2 => phy_ctl_wr_i1_reg,
      I3 => mem_out(13),
      I4 => out_fifo,
      O => D5(1)
    );
\out_fifo_i_44__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(324),
      I1 => phy_wrdata(380),
      I2 => out_fifo_25,
      I3 => out_fifo_3(37),
      I4 => out_fifo_4,
      O => \write_buffer.wr_buf_out_data_reg[452]\(5)
    );
\out_fifo_i_44__3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(331),
      I1 => phy_wrdata(379),
      I2 => out_fifo_25,
      I3 => out_fifo_5(29),
      I4 => out_fifo_6,
      O => \write_buffer.wr_buf_out_data_reg[459]\(5)
    );
\out_fifo_i_44__4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(339),
      I1 => phy_wrdata(379),
      I2 => out_fifo_25,
      I3 => out_fifo_7(29),
      I4 => out_fifo_8,
      O => \write_buffer.wr_buf_out_data_reg[467]\(5)
    );
\out_fifo_i_44__5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(347),
      I1 => phy_wrdata(379),
      I2 => out_fifo_25,
      I3 => out_fifo_9(29),
      I4 => out_fifo_10,
      O => \write_buffer.wr_buf_out_data_reg[475]\(5)
    );
\out_fifo_i_44__6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(356),
      I1 => phy_wrdata(380),
      I2 => out_fifo_25,
      I3 => out_fifo_12(37),
      I4 => out_fifo_13,
      O => \write_buffer.wr_buf_out_data_reg[484]\(5)
    );
\out_fifo_i_44__7\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(363),
      I1 => phy_wrdata(379),
      I2 => out_fifo_25,
      I3 => out_fifo_14(29),
      I4 => out_fifo_15,
      O => \write_buffer.wr_buf_out_data_reg[491]\(5)
    );
\out_fifo_i_44__8\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(371),
      I1 => phy_wrdata(379),
      I2 => out_fifo_26,
      I3 => out_fifo_16(29),
      I4 => out_fifo_17,
      O => \write_buffer.wr_buf_out_data_reg[499]\(5)
    );
\out_fifo_i_44__9\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(379),
      I1 => phy_wrdata(379),
      I2 => out_fifo_26,
      I3 => out_fifo_18(29),
      I4 => out_fifo_19,
      O => \write_buffer.wr_buf_out_data_reg[507]\(5)
    );
\out_fifo_i_45__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mc_address(3),
      I1 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[3]\,
      I2 => phy_ctl_wr_i1_reg,
      I3 => mem_out(12),
      I4 => out_fifo,
      O => D5(0)
    );
\out_fifo_i_45__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(260),
      I1 => phy_wrdata(316),
      I2 => out_fifo_23,
      I3 => out_fifo_3(36),
      I4 => out_fifo_4,
      O => \write_buffer.wr_buf_out_data_reg[452]\(4)
    );
\out_fifo_i_45__3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(267),
      I1 => phy_wrdata(315),
      I2 => out_fifo_23,
      I3 => out_fifo_5(28),
      I4 => out_fifo_6,
      O => \write_buffer.wr_buf_out_data_reg[459]\(4)
    );
\out_fifo_i_45__4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(275),
      I1 => phy_wrdata(315),
      I2 => out_fifo_24,
      I3 => out_fifo_7(28),
      I4 => out_fifo_8,
      O => \write_buffer.wr_buf_out_data_reg[467]\(4)
    );
\out_fifo_i_45__5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(283),
      I1 => phy_wrdata(315),
      I2 => out_fifo_24,
      I3 => out_fifo_9(28),
      I4 => out_fifo_10,
      O => \write_buffer.wr_buf_out_data_reg[475]\(4)
    );
\out_fifo_i_45__6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(292),
      I1 => phy_wrdata(316),
      I2 => out_fifo_24,
      I3 => out_fifo_12(36),
      I4 => out_fifo_13,
      O => \write_buffer.wr_buf_out_data_reg[484]\(4)
    );
\out_fifo_i_45__7\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(299),
      I1 => phy_wrdata(315),
      I2 => out_fifo_24,
      I3 => out_fifo_14(28),
      I4 => out_fifo_15,
      O => \write_buffer.wr_buf_out_data_reg[491]\(4)
    );
\out_fifo_i_45__8\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(307),
      I1 => phy_wrdata(315),
      I2 => out_fifo_24,
      I3 => out_fifo_16(28),
      I4 => out_fifo_17,
      O => \write_buffer.wr_buf_out_data_reg[499]\(4)
    );
\out_fifo_i_45__9\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(315),
      I1 => phy_wrdata(315),
      I2 => out_fifo_24,
      I3 => out_fifo_18(28),
      I4 => out_fifo_19,
      O => \write_buffer.wr_buf_out_data_reg[507]\(4)
    );
out_fifo_i_46: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(196),
      I1 => phy_wrdata(252),
      I2 => out_fifo_22,
      I3 => out_fifo_3(35),
      I4 => out_fifo_4,
      O => \write_buffer.wr_buf_out_data_reg[452]\(3)
    );
\out_fifo_i_46__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(203),
      I1 => phy_wrdata(251),
      I2 => out_fifo_22,
      I3 => out_fifo_5(27),
      I4 => out_fifo_6,
      O => \write_buffer.wr_buf_out_data_reg[459]\(3)
    );
\out_fifo_i_46__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(211),
      I1 => phy_wrdata(251),
      I2 => out_fifo_22,
      I3 => out_fifo_7(27),
      I4 => out_fifo_8,
      O => \write_buffer.wr_buf_out_data_reg[467]\(3)
    );
\out_fifo_i_46__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(219),
      I1 => phy_wrdata(251),
      I2 => out_fifo_22,
      I3 => out_fifo_9(27),
      I4 => out_fifo_10,
      O => \write_buffer.wr_buf_out_data_reg[475]\(3)
    );
\out_fifo_i_46__3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(228),
      I1 => phy_wrdata(252),
      I2 => out_fifo_23,
      I3 => out_fifo_12(35),
      I4 => out_fifo_13,
      O => \write_buffer.wr_buf_out_data_reg[484]\(3)
    );
\out_fifo_i_46__4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(235),
      I1 => phy_wrdata(251),
      I2 => out_fifo_23,
      I3 => out_fifo_14(27),
      I4 => out_fifo_15,
      O => \write_buffer.wr_buf_out_data_reg[491]\(3)
    );
\out_fifo_i_46__5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(243),
      I1 => phy_wrdata(251),
      I2 => out_fifo_23,
      I3 => out_fifo_16(27),
      I4 => out_fifo_17,
      O => \write_buffer.wr_buf_out_data_reg[499]\(3)
    );
\out_fifo_i_46__6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(251),
      I1 => phy_wrdata(251),
      I2 => out_fifo_23,
      I3 => out_fifo_18(27),
      I4 => out_fifo_19,
      O => \write_buffer.wr_buf_out_data_reg[507]\(3)
    );
\out_fifo_i_46__7\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => mc_cke(0),
      I1 => out_fifo_31,
      I2 => calib_cke(3),
      I3 => out_fifo_29(11),
      I4 => out_fifo_30,
      O => \cmd_pipe_plus.mc_cke_reg[3]\(3)
    );
\out_fifo_i_46__8\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"EEF0"
    )
        port map (
      I0 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[2]\,
      I1 => out_fifo_31,
      I2 => out_fifo_0(19),
      I3 => out_fifo_1,
      O => \gen_no_mirror.div_clk_loop[0].phy_address_reg[2]_0\(3)
    );
out_fifo_i_47: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mc_address(25),
      I1 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[2]\,
      I2 => out_fifo_2,
      I3 => out_fifo_0(18),
      I4 => out_fifo_1,
      O => \gen_no_mirror.div_clk_loop[0].phy_address_reg[2]_0\(2)
    );
\out_fifo_i_47__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(132),
      I1 => phy_wrdata(188),
      I2 => out_fifo_21,
      I3 => out_fifo_3(34),
      I4 => out_fifo_4,
      O => \write_buffer.wr_buf_out_data_reg[452]\(2)
    );
\out_fifo_i_47__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(139),
      I1 => phy_wrdata(187),
      I2 => out_fifo_21,
      I3 => out_fifo_5(26),
      I4 => out_fifo_6,
      O => \write_buffer.wr_buf_out_data_reg[459]\(2)
    );
\out_fifo_i_47__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(147),
      I1 => phy_wrdata(187),
      I2 => out_fifo_21,
      I3 => out_fifo_7(26),
      I4 => out_fifo_8,
      O => \write_buffer.wr_buf_out_data_reg[467]\(2)
    );
\out_fifo_i_47__3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(155),
      I1 => phy_wrdata(187),
      I2 => out_fifo_21,
      I3 => out_fifo_9(26),
      I4 => out_fifo_10,
      O => \write_buffer.wr_buf_out_data_reg[475]\(2)
    );
\out_fifo_i_47__4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(164),
      I1 => phy_wrdata(188),
      I2 => out_fifo_21,
      I3 => out_fifo_12(34),
      I4 => out_fifo_13,
      O => \write_buffer.wr_buf_out_data_reg[484]\(2)
    );
\out_fifo_i_47__5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(171),
      I1 => phy_wrdata(187),
      I2 => out_fifo_21,
      I3 => out_fifo_14(26),
      I4 => out_fifo_15,
      O => \write_buffer.wr_buf_out_data_reg[491]\(2)
    );
\out_fifo_i_47__6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(179),
      I1 => phy_wrdata(187),
      I2 => out_fifo_22,
      I3 => out_fifo_16(26),
      I4 => out_fifo_17,
      O => \write_buffer.wr_buf_out_data_reg[499]\(2)
    );
\out_fifo_i_47__7\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(187),
      I1 => phy_wrdata(187),
      I2 => out_fifo_22,
      I3 => out_fifo_18(26),
      I4 => out_fifo_19,
      O => \write_buffer.wr_buf_out_data_reg[507]\(2)
    );
\out_fifo_i_47__8\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => mc_cke(0),
      I1 => out_fifo_31,
      I2 => calib_cke(3),
      I3 => out_fifo_29(10),
      I4 => out_fifo_30,
      O => \cmd_pipe_plus.mc_cke_reg[3]\(2)
    );
out_fifo_i_48: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mc_address(14),
      I1 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[2]\,
      I2 => phy_ctl_wr_i1_reg,
      I3 => out_fifo_0(17),
      I4 => out_fifo_1,
      O => \gen_no_mirror.div_clk_loop[0].phy_address_reg[2]_0\(1)
    );
\out_fifo_i_48__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(68),
      I1 => phy_wrdata(124),
      I2 => out_fifo_11,
      I3 => out_fifo_3(33),
      I4 => out_fifo_4,
      O => \write_buffer.wr_buf_out_data_reg[452]\(1)
    );
\out_fifo_i_48__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(75),
      I1 => phy_wrdata(123),
      I2 => out_fifo_11,
      I3 => out_fifo_5(25),
      I4 => out_fifo_6,
      O => \write_buffer.wr_buf_out_data_reg[459]\(1)
    );
\out_fifo_i_48__3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(83),
      I1 => phy_wrdata(123),
      I2 => out_fifo_20,
      I3 => out_fifo_7(25),
      I4 => out_fifo_8,
      O => \write_buffer.wr_buf_out_data_reg[467]\(1)
    );
\out_fifo_i_48__4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(91),
      I1 => phy_wrdata(123),
      I2 => out_fifo_20,
      I3 => out_fifo_9(25),
      I4 => out_fifo_10,
      O => \write_buffer.wr_buf_out_data_reg[475]\(1)
    );
\out_fifo_i_48__5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(100),
      I1 => phy_wrdata(124),
      I2 => out_fifo_20,
      I3 => out_fifo_12(33),
      I4 => out_fifo_13,
      O => \write_buffer.wr_buf_out_data_reg[484]\(1)
    );
\out_fifo_i_48__6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(107),
      I1 => phy_wrdata(123),
      I2 => out_fifo_20,
      I3 => out_fifo_14(25),
      I4 => out_fifo_15,
      O => \write_buffer.wr_buf_out_data_reg[491]\(1)
    );
\out_fifo_i_48__7\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(115),
      I1 => phy_wrdata(123),
      I2 => out_fifo_20,
      I3 => out_fifo_16(25),
      I4 => out_fifo_17,
      O => \write_buffer.wr_buf_out_data_reg[499]\(1)
    );
\out_fifo_i_48__8\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(123),
      I1 => phy_wrdata(123),
      I2 => out_fifo_20,
      I3 => out_fifo_18(25),
      I4 => out_fifo_19,
      O => \write_buffer.wr_buf_out_data_reg[507]\(1)
    );
\out_fifo_i_48__9\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => mc_cke(0),
      I1 => out_fifo_31,
      I2 => calib_cke(3),
      I3 => out_fifo_29(9),
      I4 => out_fifo_30,
      O => \cmd_pipe_plus.mc_cke_reg[3]\(1)
    );
out_fifo_i_49: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mc_address(2),
      I1 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[2]\,
      I2 => phy_ctl_wr_i1_reg,
      I3 => out_fifo_0(16),
      I4 => out_fifo_1,
      O => \gen_no_mirror.div_clk_loop[0].phy_address_reg[2]_0\(0)
    );
\out_fifo_i_49__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(4),
      I1 => phy_wrdata(60),
      I2 => out_fifo_2,
      I3 => out_fifo_3(32),
      I4 => out_fifo_4,
      O => \write_buffer.wr_buf_out_data_reg[452]\(0)
    );
\out_fifo_i_49__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(11),
      I1 => phy_wrdata(59),
      I2 => out_fifo_2,
      I3 => out_fifo_5(24),
      I4 => out_fifo_6,
      O => \write_buffer.wr_buf_out_data_reg[459]\(0)
    );
\out_fifo_i_49__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(19),
      I1 => phy_wrdata(59),
      I2 => out_fifo_2,
      I3 => out_fifo_7(24),
      I4 => out_fifo_8,
      O => \write_buffer.wr_buf_out_data_reg[467]\(0)
    );
\out_fifo_i_49__3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(27),
      I1 => phy_wrdata(59),
      I2 => out_fifo_11,
      I3 => out_fifo_9(24),
      I4 => out_fifo_10,
      O => \write_buffer.wr_buf_out_data_reg[475]\(0)
    );
\out_fifo_i_49__4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(36),
      I1 => phy_wrdata(60),
      I2 => out_fifo_11,
      I3 => out_fifo_12(32),
      I4 => out_fifo_13,
      O => \write_buffer.wr_buf_out_data_reg[484]\(0)
    );
\out_fifo_i_49__5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(43),
      I1 => phy_wrdata(59),
      I2 => out_fifo_11,
      I3 => out_fifo_14(24),
      I4 => out_fifo_15,
      O => \write_buffer.wr_buf_out_data_reg[491]\(0)
    );
\out_fifo_i_49__6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(51),
      I1 => phy_wrdata(59),
      I2 => out_fifo_11,
      I3 => out_fifo_16(24),
      I4 => out_fifo_17,
      O => \write_buffer.wr_buf_out_data_reg[499]\(0)
    );
\out_fifo_i_49__7\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(59),
      I1 => phy_wrdata(59),
      I2 => out_fifo_11,
      I3 => out_fifo_18(24),
      I4 => out_fifo_19,
      O => \write_buffer.wr_buf_out_data_reg[507]\(0)
    );
\out_fifo_i_49__8\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => mc_cke(0),
      I1 => out_fifo_31,
      I2 => calib_cke(3),
      I3 => out_fifo_29(8),
      I4 => out_fifo_30,
      O => \cmd_pipe_plus.mc_cke_reg[3]\(0)
    );
\out_fifo_i_50__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(453),
      I1 => phy_wrdata(509),
      I2 => out_fifo_27,
      I3 => out_fifo_3(47),
      I4 => out_fifo_4,
      O => \write_buffer.wr_buf_out_data_reg[453]\(7)
    );
\out_fifo_i_50__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(460),
      I1 => phy_wrdata(508),
      I2 => out_fifo_27,
      I3 => out_fifo_5(39),
      I4 => out_fifo_6,
      O => \write_buffer.wr_buf_out_data_reg[460]\(7)
    );
\out_fifo_i_50__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(468),
      I1 => phy_wrdata(508),
      I2 => out_fifo_28,
      I3 => out_fifo_7(39),
      I4 => out_fifo_8,
      O => \write_buffer.wr_buf_out_data_reg[468]\(7)
    );
\out_fifo_i_50__3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(476),
      I1 => phy_wrdata(508),
      I2 => out_fifo_28,
      I3 => out_fifo_9(39),
      I4 => out_fifo_10,
      O => \write_buffer.wr_buf_out_data_reg[476]\(7)
    );
\out_fifo_i_50__4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(485),
      I1 => phy_wrdata(509),
      I2 => out_fifo_28,
      I3 => out_fifo_12(47),
      I4 => out_fifo_13,
      O => \write_buffer.wr_buf_out_data_reg[485]\(7)
    );
\out_fifo_i_50__5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(492),
      I1 => phy_wrdata(508),
      I2 => out_fifo_28,
      I3 => out_fifo_14(39),
      I4 => out_fifo_15,
      O => \write_buffer.wr_buf_out_data_reg[492]\(7)
    );
\out_fifo_i_50__6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(500),
      I1 => phy_wrdata(508),
      I2 => out_fifo_28,
      I3 => out_fifo_16(39),
      I4 => out_fifo_17,
      O => \write_buffer.wr_buf_out_data_reg[500]\(7)
    );
\out_fifo_i_50__7\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(508),
      I1 => phy_wrdata(508),
      I2 => out_fifo_28,
      I3 => out_fifo_18(39),
      I4 => out_fifo_19,
      O => \write_buffer.wr_buf_out_data_reg[508]\(7)
    );
\out_fifo_i_50__8\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"EEF0"
    )
        port map (
      I0 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[0]\,
      I1 => out_fifo_31,
      I2 => mem_out(23),
      I3 => out_fifo,
      O => D6(7)
    );
\out_fifo_i_51__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mc_address(23),
      I1 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[0]\,
      I2 => phy_ctl_wr_i1_reg,
      I3 => mem_out(22),
      I4 => out_fifo,
      O => D6(6)
    );
\out_fifo_i_51__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(389),
      I1 => phy_wrdata(445),
      I2 => out_fifo_26,
      I3 => out_fifo_3(46),
      I4 => out_fifo_4,
      O => \write_buffer.wr_buf_out_data_reg[453]\(6)
    );
\out_fifo_i_51__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(396),
      I1 => phy_wrdata(444),
      I2 => out_fifo_26,
      I3 => out_fifo_5(38),
      I4 => out_fifo_6,
      O => \write_buffer.wr_buf_out_data_reg[460]\(6)
    );
\out_fifo_i_51__3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(404),
      I1 => phy_wrdata(444),
      I2 => out_fifo_26,
      I3 => out_fifo_7(38),
      I4 => out_fifo_8,
      O => \write_buffer.wr_buf_out_data_reg[468]\(6)
    );
\out_fifo_i_51__4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(412),
      I1 => phy_wrdata(444),
      I2 => out_fifo_26,
      I3 => out_fifo_9(38),
      I4 => out_fifo_10,
      O => \write_buffer.wr_buf_out_data_reg[476]\(6)
    );
\out_fifo_i_51__5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(421),
      I1 => phy_wrdata(445),
      I2 => out_fifo_27,
      I3 => out_fifo_12(46),
      I4 => out_fifo_13,
      O => \write_buffer.wr_buf_out_data_reg[485]\(6)
    );
\out_fifo_i_51__6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(428),
      I1 => phy_wrdata(444),
      I2 => out_fifo_27,
      I3 => out_fifo_14(38),
      I4 => out_fifo_15,
      O => \write_buffer.wr_buf_out_data_reg[492]\(6)
    );
\out_fifo_i_51__7\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(436),
      I1 => phy_wrdata(444),
      I2 => out_fifo_27,
      I3 => out_fifo_16(38),
      I4 => out_fifo_17,
      O => \write_buffer.wr_buf_out_data_reg[500]\(6)
    );
\out_fifo_i_51__8\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(444),
      I1 => phy_wrdata(444),
      I2 => out_fifo_27,
      I3 => out_fifo_18(38),
      I4 => out_fifo_19,
      O => \write_buffer.wr_buf_out_data_reg[508]\(6)
    );
out_fifo_i_52: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mc_address(12),
      I1 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[0]\,
      I2 => phy_ctl_wr_i1_reg,
      I3 => mem_out(21),
      I4 => out_fifo,
      O => D6(5)
    );
\out_fifo_i_52__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(325),
      I1 => phy_wrdata(381),
      I2 => out_fifo_25,
      I3 => out_fifo_3(45),
      I4 => out_fifo_4,
      O => \write_buffer.wr_buf_out_data_reg[453]\(5)
    );
\out_fifo_i_52__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(332),
      I1 => phy_wrdata(380),
      I2 => out_fifo_25,
      I3 => out_fifo_5(37),
      I4 => out_fifo_6,
      O => \write_buffer.wr_buf_out_data_reg[460]\(5)
    );
\out_fifo_i_52__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(340),
      I1 => phy_wrdata(380),
      I2 => out_fifo_25,
      I3 => out_fifo_7(37),
      I4 => out_fifo_8,
      O => \write_buffer.wr_buf_out_data_reg[468]\(5)
    );
\out_fifo_i_52__3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(348),
      I1 => phy_wrdata(380),
      I2 => out_fifo_25,
      I3 => out_fifo_9(37),
      I4 => out_fifo_10,
      O => \write_buffer.wr_buf_out_data_reg[476]\(5)
    );
\out_fifo_i_52__4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(357),
      I1 => phy_wrdata(381),
      I2 => out_fifo_25,
      I3 => out_fifo_12(45),
      I4 => out_fifo_13,
      O => \write_buffer.wr_buf_out_data_reg[485]\(5)
    );
\out_fifo_i_52__5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(364),
      I1 => phy_wrdata(380),
      I2 => out_fifo_25,
      I3 => out_fifo_14(37),
      I4 => out_fifo_15,
      O => \write_buffer.wr_buf_out_data_reg[492]\(5)
    );
\out_fifo_i_52__6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(372),
      I1 => phy_wrdata(380),
      I2 => out_fifo_26,
      I3 => out_fifo_16(37),
      I4 => out_fifo_17,
      O => \write_buffer.wr_buf_out_data_reg[500]\(5)
    );
\out_fifo_i_52__7\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(380),
      I1 => phy_wrdata(380),
      I2 => out_fifo_26,
      I3 => out_fifo_18(37),
      I4 => out_fifo_19,
      O => \write_buffer.wr_buf_out_data_reg[508]\(5)
    );
\out_fifo_i_52__8\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"EEF0"
    )
        port map (
      I0 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[6]\,
      I1 => out_fifo_31,
      I2 => out_fifo_0(23),
      I3 => out_fifo_1,
      O => D9(3)
    );
out_fifo_i_53: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mc_address(0),
      I1 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[0]\,
      I2 => phy_ctl_wr_i1_reg,
      I3 => mem_out(20),
      I4 => out_fifo,
      O => D6(4)
    );
\out_fifo_i_53__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mc_address(29),
      I1 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[6]\,
      I2 => out_fifo_2,
      I3 => out_fifo_0(22),
      I4 => out_fifo_1,
      O => D9(2)
    );
\out_fifo_i_53__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(261),
      I1 => phy_wrdata(317),
      I2 => out_fifo_23,
      I3 => out_fifo_3(44),
      I4 => out_fifo_4,
      O => \write_buffer.wr_buf_out_data_reg[453]\(4)
    );
\out_fifo_i_53__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(268),
      I1 => phy_wrdata(316),
      I2 => out_fifo_23,
      I3 => out_fifo_5(36),
      I4 => out_fifo_6,
      O => \write_buffer.wr_buf_out_data_reg[460]\(4)
    );
\out_fifo_i_53__3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(276),
      I1 => phy_wrdata(316),
      I2 => out_fifo_24,
      I3 => out_fifo_7(36),
      I4 => out_fifo_8,
      O => \write_buffer.wr_buf_out_data_reg[468]\(4)
    );
\out_fifo_i_53__4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(284),
      I1 => phy_wrdata(316),
      I2 => out_fifo_24,
      I3 => out_fifo_9(36),
      I4 => out_fifo_10,
      O => \write_buffer.wr_buf_out_data_reg[476]\(4)
    );
\out_fifo_i_53__5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(293),
      I1 => phy_wrdata(317),
      I2 => out_fifo_24,
      I3 => out_fifo_12(44),
      I4 => out_fifo_13,
      O => \write_buffer.wr_buf_out_data_reg[485]\(4)
    );
\out_fifo_i_53__6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(300),
      I1 => phy_wrdata(316),
      I2 => out_fifo_24,
      I3 => out_fifo_14(36),
      I4 => out_fifo_15,
      O => \write_buffer.wr_buf_out_data_reg[492]\(4)
    );
\out_fifo_i_53__7\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(308),
      I1 => phy_wrdata(316),
      I2 => out_fifo_24,
      I3 => out_fifo_16(36),
      I4 => out_fifo_17,
      O => \write_buffer.wr_buf_out_data_reg[500]\(4)
    );
\out_fifo_i_53__8\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(316),
      I1 => phy_wrdata(316),
      I2 => out_fifo_24,
      I3 => out_fifo_18(36),
      I4 => out_fifo_19,
      O => \write_buffer.wr_buf_out_data_reg[508]\(4)
    );
out_fifo_i_54: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mc_address(18),
      I1 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[6]\,
      I2 => phy_ctl_wr_i1_reg,
      I3 => out_fifo_0(21),
      I4 => out_fifo_1,
      O => D9(1)
    );
\out_fifo_i_54__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(197),
      I1 => phy_wrdata(253),
      I2 => out_fifo_22,
      I3 => out_fifo_3(43),
      I4 => out_fifo_4,
      O => \write_buffer.wr_buf_out_data_reg[453]\(3)
    );
\out_fifo_i_54__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(204),
      I1 => phy_wrdata(252),
      I2 => out_fifo_22,
      I3 => out_fifo_5(35),
      I4 => out_fifo_6,
      O => \write_buffer.wr_buf_out_data_reg[460]\(3)
    );
\out_fifo_i_54__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(212),
      I1 => phy_wrdata(252),
      I2 => out_fifo_22,
      I3 => out_fifo_7(35),
      I4 => out_fifo_8,
      O => \write_buffer.wr_buf_out_data_reg[468]\(3)
    );
\out_fifo_i_54__3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(220),
      I1 => phy_wrdata(252),
      I2 => out_fifo_22,
      I3 => out_fifo_9(35),
      I4 => out_fifo_10,
      O => \write_buffer.wr_buf_out_data_reg[476]\(3)
    );
\out_fifo_i_54__4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(229),
      I1 => phy_wrdata(253),
      I2 => out_fifo_23,
      I3 => out_fifo_12(43),
      I4 => out_fifo_13,
      O => \write_buffer.wr_buf_out_data_reg[485]\(3)
    );
\out_fifo_i_54__5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(236),
      I1 => phy_wrdata(252),
      I2 => out_fifo_23,
      I3 => out_fifo_14(35),
      I4 => out_fifo_15,
      O => \write_buffer.wr_buf_out_data_reg[492]\(3)
    );
\out_fifo_i_54__6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(244),
      I1 => phy_wrdata(252),
      I2 => out_fifo_23,
      I3 => out_fifo_16(35),
      I4 => out_fifo_17,
      O => \write_buffer.wr_buf_out_data_reg[500]\(3)
    );
\out_fifo_i_54__7\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(252),
      I1 => phy_wrdata(252),
      I2 => out_fifo_23,
      I3 => out_fifo_18(35),
      I4 => out_fifo_19,
      O => \write_buffer.wr_buf_out_data_reg[508]\(3)
    );
\out_fifo_i_54__8\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"EEF0"
    )
        port map (
      I0 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[12]\,
      I1 => out_fifo_31,
      I2 => mem_out(19),
      I3 => out_fifo,
      O => D6(3)
    );
out_fifo_i_55: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mc_address(6),
      I1 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[6]\,
      I2 => phy_ctl_wr_i1_reg,
      I3 => out_fifo_0(20),
      I4 => out_fifo_1,
      O => D9(0)
    );
\out_fifo_i_55__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mc_address(34),
      I1 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[12]\,
      I2 => out_fifo_2,
      I3 => mem_out(18),
      I4 => out_fifo,
      O => D6(2)
    );
\out_fifo_i_55__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(133),
      I1 => phy_wrdata(189),
      I2 => out_fifo_21,
      I3 => out_fifo_3(42),
      I4 => out_fifo_4,
      O => \write_buffer.wr_buf_out_data_reg[453]\(2)
    );
\out_fifo_i_55__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(140),
      I1 => phy_wrdata(188),
      I2 => out_fifo_21,
      I3 => out_fifo_5(34),
      I4 => out_fifo_6,
      O => \write_buffer.wr_buf_out_data_reg[460]\(2)
    );
\out_fifo_i_55__3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(148),
      I1 => phy_wrdata(188),
      I2 => out_fifo_21,
      I3 => out_fifo_7(34),
      I4 => out_fifo_8,
      O => \write_buffer.wr_buf_out_data_reg[468]\(2)
    );
\out_fifo_i_55__4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(156),
      I1 => phy_wrdata(188),
      I2 => out_fifo_21,
      I3 => out_fifo_9(34),
      I4 => out_fifo_10,
      O => \write_buffer.wr_buf_out_data_reg[476]\(2)
    );
\out_fifo_i_55__5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(165),
      I1 => phy_wrdata(189),
      I2 => out_fifo_21,
      I3 => out_fifo_12(42),
      I4 => out_fifo_13,
      O => \write_buffer.wr_buf_out_data_reg[485]\(2)
    );
\out_fifo_i_55__6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(172),
      I1 => phy_wrdata(188),
      I2 => out_fifo_21,
      I3 => out_fifo_14(34),
      I4 => out_fifo_15,
      O => \write_buffer.wr_buf_out_data_reg[492]\(2)
    );
\out_fifo_i_55__7\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(180),
      I1 => phy_wrdata(188),
      I2 => out_fifo_22,
      I3 => out_fifo_16(34),
      I4 => out_fifo_17,
      O => \write_buffer.wr_buf_out_data_reg[500]\(2)
    );
\out_fifo_i_55__8\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(188),
      I1 => phy_wrdata(188),
      I2 => out_fifo_22,
      I3 => out_fifo_18(34),
      I4 => out_fifo_19,
      O => \write_buffer.wr_buf_out_data_reg[508]\(2)
    );
out_fifo_i_56: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mc_ras_n(0),
      I1 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[12]\,
      I2 => phy_ctl_wr_i1_reg,
      I3 => mem_out(17),
      I4 => out_fifo,
      O => D6(1)
    );
\out_fifo_i_56__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(69),
      I1 => phy_wrdata(125),
      I2 => out_fifo_11,
      I3 => out_fifo_3(41),
      I4 => out_fifo_4,
      O => \write_buffer.wr_buf_out_data_reg[453]\(1)
    );
\out_fifo_i_56__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(76),
      I1 => phy_wrdata(124),
      I2 => out_fifo_20,
      I3 => out_fifo_5(33),
      I4 => out_fifo_6,
      O => \write_buffer.wr_buf_out_data_reg[460]\(1)
    );
\out_fifo_i_56__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(84),
      I1 => phy_wrdata(124),
      I2 => out_fifo_20,
      I3 => out_fifo_7(33),
      I4 => out_fifo_8,
      O => \write_buffer.wr_buf_out_data_reg[468]\(1)
    );
\out_fifo_i_56__3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(92),
      I1 => phy_wrdata(124),
      I2 => out_fifo_20,
      I3 => out_fifo_9(33),
      I4 => out_fifo_10,
      O => \write_buffer.wr_buf_out_data_reg[476]\(1)
    );
\out_fifo_i_56__4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(101),
      I1 => phy_wrdata(125),
      I2 => out_fifo_20,
      I3 => out_fifo_12(41),
      I4 => out_fifo_13,
      O => \write_buffer.wr_buf_out_data_reg[485]\(1)
    );
\out_fifo_i_56__5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(108),
      I1 => phy_wrdata(124),
      I2 => out_fifo_20,
      I3 => out_fifo_14(33),
      I4 => out_fifo_15,
      O => \write_buffer.wr_buf_out_data_reg[492]\(1)
    );
\out_fifo_i_56__6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(116),
      I1 => phy_wrdata(124),
      I2 => out_fifo_20,
      I3 => out_fifo_16(33),
      I4 => out_fifo_17,
      O => \write_buffer.wr_buf_out_data_reg[500]\(1)
    );
\out_fifo_i_56__7\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(124),
      I1 => phy_wrdata(124),
      I2 => out_fifo_20,
      I3 => out_fifo_18(33),
      I4 => out_fifo_19,
      O => \write_buffer.wr_buf_out_data_reg[508]\(1)
    );
out_fifo_i_57: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mc_address(11),
      I1 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[12]\,
      I2 => phy_ctl_wr_i1_reg,
      I3 => mem_out(16),
      I4 => out_fifo,
      O => D6(0)
    );
\out_fifo_i_57__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(5),
      I1 => phy_wrdata(61),
      I2 => out_fifo_2,
      I3 => out_fifo_3(40),
      I4 => out_fifo_4,
      O => \write_buffer.wr_buf_out_data_reg[453]\(0)
    );
\out_fifo_i_57__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(12),
      I1 => phy_wrdata(60),
      I2 => out_fifo_2,
      I3 => out_fifo_5(32),
      I4 => out_fifo_6,
      O => \write_buffer.wr_buf_out_data_reg[460]\(0)
    );
\out_fifo_i_57__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(20),
      I1 => phy_wrdata(60),
      I2 => out_fifo_2,
      I3 => out_fifo_7(32),
      I4 => out_fifo_8,
      O => \write_buffer.wr_buf_out_data_reg[468]\(0)
    );
\out_fifo_i_57__3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(28),
      I1 => phy_wrdata(60),
      I2 => out_fifo_11,
      I3 => out_fifo_9(32),
      I4 => out_fifo_10,
      O => \write_buffer.wr_buf_out_data_reg[476]\(0)
    );
\out_fifo_i_57__4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(37),
      I1 => phy_wrdata(61),
      I2 => out_fifo_11,
      I3 => out_fifo_12(40),
      I4 => out_fifo_13,
      O => \write_buffer.wr_buf_out_data_reg[485]\(0)
    );
\out_fifo_i_57__5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(44),
      I1 => phy_wrdata(60),
      I2 => out_fifo_11,
      I3 => out_fifo_14(32),
      I4 => out_fifo_15,
      O => \write_buffer.wr_buf_out_data_reg[492]\(0)
    );
\out_fifo_i_57__6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(52),
      I1 => phy_wrdata(60),
      I2 => out_fifo_11,
      I3 => out_fifo_16(32),
      I4 => out_fifo_17,
      O => \write_buffer.wr_buf_out_data_reg[500]\(0)
    );
\out_fifo_i_57__7\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(60),
      I1 => phy_wrdata(60),
      I2 => out_fifo_11,
      I3 => out_fifo_18(32),
      I4 => out_fifo_19,
      O => \write_buffer.wr_buf_out_data_reg[508]\(0)
    );
\out_fifo_i_58__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(454),
      I1 => phy_wrdata(510),
      I2 => out_fifo_27,
      I3 => out_fifo_3(55),
      I4 => out_fifo_4,
      O => \write_buffer.wr_buf_out_data_reg[454]\(7)
    );
\out_fifo_i_58__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(461),
      I1 => phy_wrdata(509),
      I2 => out_fifo_27,
      I3 => out_fifo_5(47),
      I4 => out_fifo_6,
      O => \write_buffer.wr_buf_out_data_reg[461]\(7)
    );
\out_fifo_i_58__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(469),
      I1 => phy_wrdata(509),
      I2 => out_fifo_28,
      I3 => out_fifo_7(47),
      I4 => out_fifo_8,
      O => \write_buffer.wr_buf_out_data_reg[469]\(7)
    );
\out_fifo_i_58__3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(477),
      I1 => phy_wrdata(509),
      I2 => out_fifo_28,
      I3 => out_fifo_9(47),
      I4 => out_fifo_10,
      O => \write_buffer.wr_buf_out_data_reg[477]\(7)
    );
\out_fifo_i_58__4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(486),
      I1 => phy_wrdata(510),
      I2 => out_fifo_28,
      I3 => out_fifo_12(55),
      I4 => out_fifo_13,
      O => \write_buffer.wr_buf_out_data_reg[486]\(7)
    );
\out_fifo_i_58__5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(493),
      I1 => phy_wrdata(509),
      I2 => out_fifo_28,
      I3 => out_fifo_14(47),
      I4 => out_fifo_15,
      O => \write_buffer.wr_buf_out_data_reg[493]\(7)
    );
\out_fifo_i_58__6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(501),
      I1 => phy_wrdata(509),
      I2 => out_fifo_28,
      I3 => out_fifo_16(47),
      I4 => out_fifo_17,
      O => \write_buffer.wr_buf_out_data_reg[501]\(7)
    );
\out_fifo_i_58__7\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(509),
      I1 => phy_wrdata(509),
      I2 => out_fifo_28,
      I3 => out_fifo_18(47),
      I4 => out_fifo_19,
      O => \write_buffer.wr_buf_out_data_reg[509]\(7)
    );
\out_fifo_i_59__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(390),
      I1 => phy_wrdata(446),
      I2 => out_fifo_26,
      I3 => out_fifo_3(54),
      I4 => out_fifo_4,
      O => \write_buffer.wr_buf_out_data_reg[454]\(6)
    );
\out_fifo_i_59__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(397),
      I1 => phy_wrdata(445),
      I2 => out_fifo_26,
      I3 => out_fifo_5(46),
      I4 => out_fifo_6,
      O => \write_buffer.wr_buf_out_data_reg[461]\(6)
    );
\out_fifo_i_59__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(405),
      I1 => phy_wrdata(445),
      I2 => out_fifo_26,
      I3 => out_fifo_7(46),
      I4 => out_fifo_8,
      O => \write_buffer.wr_buf_out_data_reg[469]\(6)
    );
\out_fifo_i_59__3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(413),
      I1 => phy_wrdata(445),
      I2 => out_fifo_26,
      I3 => out_fifo_9(46),
      I4 => out_fifo_10,
      O => \write_buffer.wr_buf_out_data_reg[477]\(6)
    );
\out_fifo_i_59__4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(422),
      I1 => phy_wrdata(446),
      I2 => out_fifo_27,
      I3 => out_fifo_12(54),
      I4 => out_fifo_13,
      O => \write_buffer.wr_buf_out_data_reg[486]\(6)
    );
\out_fifo_i_59__5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(429),
      I1 => phy_wrdata(445),
      I2 => out_fifo_27,
      I3 => out_fifo_14(46),
      I4 => out_fifo_15,
      O => \write_buffer.wr_buf_out_data_reg[493]\(6)
    );
\out_fifo_i_59__6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(437),
      I1 => phy_wrdata(445),
      I2 => out_fifo_27,
      I3 => out_fifo_16(46),
      I4 => out_fifo_17,
      O => \write_buffer.wr_buf_out_data_reg[501]\(6)
    );
\out_fifo_i_59__7\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(445),
      I1 => phy_wrdata(445),
      I2 => out_fifo_27,
      I3 => out_fifo_18(46),
      I4 => out_fifo_19,
      O => \write_buffer.wr_buf_out_data_reg[509]\(6)
    );
\out_fifo_i_60__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(326),
      I1 => phy_wrdata(382),
      I2 => out_fifo_25,
      I3 => out_fifo_3(53),
      I4 => out_fifo_4,
      O => \write_buffer.wr_buf_out_data_reg[454]\(5)
    );
\out_fifo_i_60__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(333),
      I1 => phy_wrdata(381),
      I2 => out_fifo_25,
      I3 => out_fifo_5(45),
      I4 => out_fifo_6,
      O => \write_buffer.wr_buf_out_data_reg[461]\(5)
    );
\out_fifo_i_60__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(341),
      I1 => phy_wrdata(381),
      I2 => out_fifo_25,
      I3 => out_fifo_7(45),
      I4 => out_fifo_8,
      O => \write_buffer.wr_buf_out_data_reg[469]\(5)
    );
\out_fifo_i_60__3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(349),
      I1 => phy_wrdata(381),
      I2 => out_fifo_25,
      I3 => out_fifo_9(45),
      I4 => out_fifo_10,
      O => \write_buffer.wr_buf_out_data_reg[477]\(5)
    );
\out_fifo_i_60__4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(358),
      I1 => phy_wrdata(382),
      I2 => out_fifo_25,
      I3 => out_fifo_12(53),
      I4 => out_fifo_13,
      O => \write_buffer.wr_buf_out_data_reg[486]\(5)
    );
\out_fifo_i_60__5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(365),
      I1 => phy_wrdata(381),
      I2 => out_fifo_25,
      I3 => out_fifo_14(45),
      I4 => out_fifo_15,
      O => \write_buffer.wr_buf_out_data_reg[493]\(5)
    );
\out_fifo_i_60__6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(373),
      I1 => phy_wrdata(381),
      I2 => out_fifo_26,
      I3 => out_fifo_16(45),
      I4 => out_fifo_17,
      O => \write_buffer.wr_buf_out_data_reg[501]\(5)
    );
\out_fifo_i_60__7\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(381),
      I1 => phy_wrdata(381),
      I2 => out_fifo_26,
      I3 => out_fifo_18(45),
      I4 => out_fifo_19,
      O => \write_buffer.wr_buf_out_data_reg[509]\(5)
    );
\out_fifo_i_61__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(262),
      I1 => phy_wrdata(318),
      I2 => out_fifo_23,
      I3 => out_fifo_3(52),
      I4 => out_fifo_4,
      O => \write_buffer.wr_buf_out_data_reg[454]\(4)
    );
\out_fifo_i_61__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(269),
      I1 => phy_wrdata(317),
      I2 => out_fifo_23,
      I3 => out_fifo_5(44),
      I4 => out_fifo_6,
      O => \write_buffer.wr_buf_out_data_reg[461]\(4)
    );
\out_fifo_i_61__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(277),
      I1 => phy_wrdata(317),
      I2 => out_fifo_24,
      I3 => out_fifo_7(44),
      I4 => out_fifo_8,
      O => \write_buffer.wr_buf_out_data_reg[469]\(4)
    );
\out_fifo_i_61__3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(285),
      I1 => phy_wrdata(317),
      I2 => out_fifo_24,
      I3 => out_fifo_9(44),
      I4 => out_fifo_10,
      O => \write_buffer.wr_buf_out_data_reg[477]\(4)
    );
\out_fifo_i_61__4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(294),
      I1 => phy_wrdata(318),
      I2 => out_fifo_24,
      I3 => out_fifo_12(52),
      I4 => out_fifo_13,
      O => \write_buffer.wr_buf_out_data_reg[486]\(4)
    );
\out_fifo_i_61__5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(301),
      I1 => phy_wrdata(317),
      I2 => out_fifo_24,
      I3 => out_fifo_14(44),
      I4 => out_fifo_15,
      O => \write_buffer.wr_buf_out_data_reg[493]\(4)
    );
\out_fifo_i_61__6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(309),
      I1 => phy_wrdata(317),
      I2 => out_fifo_24,
      I3 => out_fifo_16(44),
      I4 => out_fifo_17,
      O => \write_buffer.wr_buf_out_data_reg[501]\(4)
    );
\out_fifo_i_61__7\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(317),
      I1 => phy_wrdata(317),
      I2 => out_fifo_24,
      I3 => out_fifo_18(44),
      I4 => out_fifo_19,
      O => \write_buffer.wr_buf_out_data_reg[509]\(4)
    );
out_fifo_i_62: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(198),
      I1 => phy_wrdata(254),
      I2 => out_fifo_22,
      I3 => out_fifo_3(51),
      I4 => out_fifo_4,
      O => \write_buffer.wr_buf_out_data_reg[454]\(3)
    );
\out_fifo_i_62__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(205),
      I1 => phy_wrdata(253),
      I2 => out_fifo_22,
      I3 => out_fifo_5(43),
      I4 => out_fifo_6,
      O => \write_buffer.wr_buf_out_data_reg[461]\(3)
    );
\out_fifo_i_62__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(213),
      I1 => phy_wrdata(253),
      I2 => out_fifo_22,
      I3 => out_fifo_7(43),
      I4 => out_fifo_8,
      O => \write_buffer.wr_buf_out_data_reg[469]\(3)
    );
\out_fifo_i_62__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(221),
      I1 => phy_wrdata(253),
      I2 => out_fifo_22,
      I3 => out_fifo_9(43),
      I4 => out_fifo_10,
      O => \write_buffer.wr_buf_out_data_reg[477]\(3)
    );
\out_fifo_i_62__3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(230),
      I1 => phy_wrdata(254),
      I2 => out_fifo_23,
      I3 => out_fifo_12(51),
      I4 => out_fifo_13,
      O => \write_buffer.wr_buf_out_data_reg[486]\(3)
    );
\out_fifo_i_62__4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(237),
      I1 => phy_wrdata(253),
      I2 => out_fifo_23,
      I3 => out_fifo_14(43),
      I4 => out_fifo_15,
      O => \write_buffer.wr_buf_out_data_reg[493]\(3)
    );
\out_fifo_i_62__5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(245),
      I1 => phy_wrdata(253),
      I2 => out_fifo_23,
      I3 => out_fifo_16(43),
      I4 => out_fifo_17,
      O => \write_buffer.wr_buf_out_data_reg[501]\(3)
    );
\out_fifo_i_62__6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(253),
      I1 => phy_wrdata(253),
      I2 => out_fifo_23,
      I3 => out_fifo_18(43),
      I4 => out_fifo_19,
      O => \write_buffer.wr_buf_out_data_reg[509]\(3)
    );
\out_fifo_i_62__7\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"EEF0"
    )
        port map (
      I0 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[5]\,
      I1 => out_fifo_31,
      I2 => mem_out(27),
      I3 => out_fifo,
      O => D7(3)
    );
out_fifo_i_63: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mc_address(28),
      I1 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[5]\,
      I2 => out_fifo_2,
      I3 => mem_out(26),
      I4 => out_fifo,
      O => D7(2)
    );
\out_fifo_i_63__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(134),
      I1 => phy_wrdata(190),
      I2 => out_fifo_21,
      I3 => out_fifo_3(50),
      I4 => out_fifo_4,
      O => \write_buffer.wr_buf_out_data_reg[454]\(2)
    );
\out_fifo_i_63__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(141),
      I1 => phy_wrdata(189),
      I2 => out_fifo_21,
      I3 => out_fifo_5(42),
      I4 => out_fifo_6,
      O => \write_buffer.wr_buf_out_data_reg[461]\(2)
    );
\out_fifo_i_63__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(149),
      I1 => phy_wrdata(189),
      I2 => out_fifo_21,
      I3 => out_fifo_7(42),
      I4 => out_fifo_8,
      O => \write_buffer.wr_buf_out_data_reg[469]\(2)
    );
\out_fifo_i_63__3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(157),
      I1 => phy_wrdata(189),
      I2 => out_fifo_21,
      I3 => out_fifo_9(42),
      I4 => out_fifo_10,
      O => \write_buffer.wr_buf_out_data_reg[477]\(2)
    );
\out_fifo_i_63__4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(166),
      I1 => phy_wrdata(190),
      I2 => out_fifo_21,
      I3 => out_fifo_12(50),
      I4 => out_fifo_13,
      O => \write_buffer.wr_buf_out_data_reg[486]\(2)
    );
\out_fifo_i_63__5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(173),
      I1 => phy_wrdata(189),
      I2 => out_fifo_21,
      I3 => out_fifo_14(42),
      I4 => out_fifo_15,
      O => \write_buffer.wr_buf_out_data_reg[493]\(2)
    );
\out_fifo_i_63__6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(181),
      I1 => phy_wrdata(189),
      I2 => out_fifo_22,
      I3 => out_fifo_16(42),
      I4 => out_fifo_17,
      O => \write_buffer.wr_buf_out_data_reg[501]\(2)
    );
\out_fifo_i_63__7\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(189),
      I1 => phy_wrdata(189),
      I2 => out_fifo_22,
      I3 => out_fifo_18(42),
      I4 => out_fifo_19,
      O => \write_buffer.wr_buf_out_data_reg[509]\(2)
    );
out_fifo_i_64: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mc_address(17),
      I1 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[5]\,
      I2 => phy_ctl_wr_i1_reg,
      I3 => mem_out(25),
      I4 => out_fifo,
      O => D7(1)
    );
\out_fifo_i_64__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(70),
      I1 => phy_wrdata(126),
      I2 => out_fifo_11,
      I3 => out_fifo_3(49),
      I4 => out_fifo_4,
      O => \write_buffer.wr_buf_out_data_reg[454]\(1)
    );
\out_fifo_i_64__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(77),
      I1 => phy_wrdata(125),
      I2 => out_fifo_20,
      I3 => out_fifo_5(41),
      I4 => out_fifo_6,
      O => \write_buffer.wr_buf_out_data_reg[461]\(1)
    );
\out_fifo_i_64__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(85),
      I1 => phy_wrdata(125),
      I2 => out_fifo_20,
      I3 => out_fifo_7(41),
      I4 => out_fifo_8,
      O => \write_buffer.wr_buf_out_data_reg[469]\(1)
    );
\out_fifo_i_64__3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(93),
      I1 => phy_wrdata(125),
      I2 => out_fifo_20,
      I3 => out_fifo_9(41),
      I4 => out_fifo_10,
      O => \write_buffer.wr_buf_out_data_reg[477]\(1)
    );
\out_fifo_i_64__4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(102),
      I1 => phy_wrdata(126),
      I2 => out_fifo_20,
      I3 => out_fifo_12(49),
      I4 => out_fifo_13,
      O => \write_buffer.wr_buf_out_data_reg[486]\(1)
    );
\out_fifo_i_64__5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(109),
      I1 => phy_wrdata(125),
      I2 => out_fifo_20,
      I3 => out_fifo_14(41),
      I4 => out_fifo_15,
      O => \write_buffer.wr_buf_out_data_reg[493]\(1)
    );
\out_fifo_i_64__6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(117),
      I1 => phy_wrdata(125),
      I2 => out_fifo_20,
      I3 => out_fifo_16(41),
      I4 => out_fifo_17,
      O => \write_buffer.wr_buf_out_data_reg[501]\(1)
    );
\out_fifo_i_64__7\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(125),
      I1 => phy_wrdata(125),
      I2 => out_fifo_21,
      I3 => out_fifo_18(41),
      I4 => out_fifo_19,
      O => \write_buffer.wr_buf_out_data_reg[509]\(1)
    );
out_fifo_i_65: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mc_address(5),
      I1 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[5]\,
      I2 => phy_ctl_wr_i1_reg,
      I3 => mem_out(24),
      I4 => out_fifo,
      O => D7(0)
    );
\out_fifo_i_65__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(6),
      I1 => phy_wrdata(62),
      I2 => out_fifo_2,
      I3 => out_fifo_3(48),
      I4 => out_fifo_4,
      O => \write_buffer.wr_buf_out_data_reg[454]\(0)
    );
\out_fifo_i_65__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(13),
      I1 => phy_wrdata(61),
      I2 => out_fifo_2,
      I3 => out_fifo_5(40),
      I4 => out_fifo_6,
      O => \write_buffer.wr_buf_out_data_reg[461]\(0)
    );
\out_fifo_i_65__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(21),
      I1 => phy_wrdata(61),
      I2 => out_fifo_2,
      I3 => out_fifo_7(40),
      I4 => out_fifo_8,
      O => \write_buffer.wr_buf_out_data_reg[469]\(0)
    );
\out_fifo_i_65__3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(29),
      I1 => phy_wrdata(61),
      I2 => out_fifo_11,
      I3 => out_fifo_9(40),
      I4 => out_fifo_10,
      O => \write_buffer.wr_buf_out_data_reg[477]\(0)
    );
\out_fifo_i_65__4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(38),
      I1 => phy_wrdata(62),
      I2 => out_fifo_11,
      I3 => out_fifo_12(48),
      I4 => out_fifo_13,
      O => \write_buffer.wr_buf_out_data_reg[486]\(0)
    );
\out_fifo_i_65__5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(45),
      I1 => phy_wrdata(61),
      I2 => out_fifo_11,
      I3 => out_fifo_14(40),
      I4 => out_fifo_15,
      O => \write_buffer.wr_buf_out_data_reg[493]\(0)
    );
\out_fifo_i_65__6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(53),
      I1 => phy_wrdata(61),
      I2 => out_fifo_11,
      I3 => out_fifo_16(40),
      I4 => out_fifo_17,
      O => \write_buffer.wr_buf_out_data_reg[501]\(0)
    );
\out_fifo_i_65__7\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(61),
      I1 => phy_wrdata(61),
      I2 => out_fifo_11,
      I3 => out_fifo_18(40),
      I4 => out_fifo_19,
      O => \write_buffer.wr_buf_out_data_reg[509]\(0)
    );
\out_fifo_i_66__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(462),
      I1 => phy_wrdata(510),
      I2 => out_fifo_27,
      I3 => out_fifo_5(55),
      I4 => out_fifo_6,
      O => \write_buffer.wr_buf_out_data_reg[462]\(7)
    );
\out_fifo_i_66__3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(470),
      I1 => phy_wrdata(510),
      I2 => out_fifo_28,
      I3 => out_fifo_7(55),
      I4 => out_fifo_8,
      O => \write_buffer.wr_buf_out_data_reg[470]\(7)
    );
\out_fifo_i_66__4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(478),
      I1 => phy_wrdata(510),
      I2 => out_fifo_28,
      I3 => out_fifo_9(55),
      I4 => out_fifo_10,
      O => \write_buffer.wr_buf_out_data_reg[478]\(7)
    );
\out_fifo_i_66__5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(494),
      I1 => phy_wrdata(510),
      I2 => out_fifo_28,
      I3 => out_fifo_14(55),
      I4 => out_fifo_15,
      O => \write_buffer.wr_buf_out_data_reg[494]\(7)
    );
\out_fifo_i_66__6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(502),
      I1 => phy_wrdata(510),
      I2 => out_fifo_28,
      I3 => out_fifo_16(55),
      I4 => out_fifo_17,
      O => \write_buffer.wr_buf_out_data_reg[502]\(7)
    );
\out_fifo_i_66__7\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(510),
      I1 => phy_wrdata(510),
      I2 => out_fifo_28,
      I3 => out_fifo_18(55),
      I4 => out_fifo_19,
      O => \write_buffer.wr_buf_out_data_reg[510]\(7)
    );
\out_fifo_i_67__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(398),
      I1 => phy_wrdata(446),
      I2 => out_fifo_26,
      I3 => out_fifo_5(54),
      I4 => out_fifo_6,
      O => \write_buffer.wr_buf_out_data_reg[462]\(6)
    );
\out_fifo_i_67__3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(406),
      I1 => phy_wrdata(446),
      I2 => out_fifo_26,
      I3 => out_fifo_7(54),
      I4 => out_fifo_8,
      O => \write_buffer.wr_buf_out_data_reg[470]\(6)
    );
\out_fifo_i_67__4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(414),
      I1 => phy_wrdata(446),
      I2 => out_fifo_26,
      I3 => out_fifo_9(54),
      I4 => out_fifo_10,
      O => \write_buffer.wr_buf_out_data_reg[478]\(6)
    );
\out_fifo_i_67__5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(430),
      I1 => phy_wrdata(446),
      I2 => out_fifo_27,
      I3 => out_fifo_14(54),
      I4 => out_fifo_15,
      O => \write_buffer.wr_buf_out_data_reg[494]\(6)
    );
\out_fifo_i_67__6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(438),
      I1 => phy_wrdata(446),
      I2 => out_fifo_27,
      I3 => out_fifo_16(54),
      I4 => out_fifo_17,
      O => \write_buffer.wr_buf_out_data_reg[502]\(6)
    );
\out_fifo_i_67__7\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(446),
      I1 => phy_wrdata(446),
      I2 => out_fifo_27,
      I3 => out_fifo_18(54),
      I4 => out_fifo_19,
      O => \write_buffer.wr_buf_out_data_reg[510]\(6)
    );
\out_fifo_i_68__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(334),
      I1 => phy_wrdata(382),
      I2 => out_fifo_25,
      I3 => out_fifo_5(53),
      I4 => out_fifo_6,
      O => \write_buffer.wr_buf_out_data_reg[462]\(5)
    );
\out_fifo_i_68__3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(342),
      I1 => phy_wrdata(382),
      I2 => out_fifo_25,
      I3 => out_fifo_7(53),
      I4 => out_fifo_8,
      O => \write_buffer.wr_buf_out_data_reg[470]\(5)
    );
\out_fifo_i_68__4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(350),
      I1 => phy_wrdata(382),
      I2 => out_fifo_25,
      I3 => out_fifo_9(53),
      I4 => out_fifo_10,
      O => \write_buffer.wr_buf_out_data_reg[478]\(5)
    );
\out_fifo_i_68__5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(366),
      I1 => phy_wrdata(382),
      I2 => out_fifo_25,
      I3 => out_fifo_14(53),
      I4 => out_fifo_15,
      O => \write_buffer.wr_buf_out_data_reg[494]\(5)
    );
\out_fifo_i_68__6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(374),
      I1 => phy_wrdata(382),
      I2 => out_fifo_26,
      I3 => out_fifo_16(53),
      I4 => out_fifo_17,
      O => \write_buffer.wr_buf_out_data_reg[502]\(5)
    );
\out_fifo_i_68__7\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(382),
      I1 => phy_wrdata(382),
      I2 => out_fifo_26,
      I3 => out_fifo_18(53),
      I4 => out_fifo_19,
      O => \write_buffer.wr_buf_out_data_reg[510]\(5)
    );
\out_fifo_i_69__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(270),
      I1 => phy_wrdata(318),
      I2 => out_fifo_23,
      I3 => out_fifo_5(52),
      I4 => out_fifo_6,
      O => \write_buffer.wr_buf_out_data_reg[462]\(4)
    );
\out_fifo_i_69__3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(278),
      I1 => phy_wrdata(318),
      I2 => out_fifo_24,
      I3 => out_fifo_7(52),
      I4 => out_fifo_8,
      O => \write_buffer.wr_buf_out_data_reg[470]\(4)
    );
\out_fifo_i_69__4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(286),
      I1 => phy_wrdata(318),
      I2 => out_fifo_24,
      I3 => out_fifo_9(52),
      I4 => out_fifo_10,
      O => \write_buffer.wr_buf_out_data_reg[478]\(4)
    );
\out_fifo_i_69__5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(302),
      I1 => phy_wrdata(318),
      I2 => out_fifo_24,
      I3 => out_fifo_14(52),
      I4 => out_fifo_15,
      O => \write_buffer.wr_buf_out_data_reg[494]\(4)
    );
\out_fifo_i_69__6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(310),
      I1 => phy_wrdata(318),
      I2 => out_fifo_24,
      I3 => out_fifo_16(52),
      I4 => out_fifo_17,
      O => \write_buffer.wr_buf_out_data_reg[502]\(4)
    );
\out_fifo_i_69__7\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(318),
      I1 => phy_wrdata(318),
      I2 => out_fifo_24,
      I3 => out_fifo_18(52),
      I4 => out_fifo_19,
      O => \write_buffer.wr_buf_out_data_reg[510]\(4)
    );
\out_fifo_i_70__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(206),
      I1 => phy_wrdata(254),
      I2 => out_fifo_22,
      I3 => out_fifo_5(51),
      I4 => out_fifo_6,
      O => \write_buffer.wr_buf_out_data_reg[462]\(3)
    );
\out_fifo_i_70__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(214),
      I1 => phy_wrdata(254),
      I2 => out_fifo_22,
      I3 => out_fifo_7(51),
      I4 => out_fifo_8,
      O => \write_buffer.wr_buf_out_data_reg[470]\(3)
    );
\out_fifo_i_70__3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(222),
      I1 => phy_wrdata(254),
      I2 => out_fifo_22,
      I3 => out_fifo_9(51),
      I4 => out_fifo_10,
      O => \write_buffer.wr_buf_out_data_reg[478]\(3)
    );
\out_fifo_i_70__4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(238),
      I1 => phy_wrdata(254),
      I2 => out_fifo_23,
      I3 => out_fifo_14(51),
      I4 => out_fifo_15,
      O => \write_buffer.wr_buf_out_data_reg[494]\(3)
    );
\out_fifo_i_70__5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(246),
      I1 => phy_wrdata(254),
      I2 => out_fifo_23,
      I3 => out_fifo_16(51),
      I4 => out_fifo_17,
      O => \write_buffer.wr_buf_out_data_reg[502]\(3)
    );
\out_fifo_i_70__6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(254),
      I1 => phy_wrdata(254),
      I2 => out_fifo_23,
      I3 => out_fifo_18(51),
      I4 => out_fifo_19,
      O => \write_buffer.wr_buf_out_data_reg[510]\(3)
    );
\out_fifo_i_70__7\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"EEF0"
    )
        port map (
      I0 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[1]\,
      I1 => out_fifo_31,
      I2 => mem_out(31),
      I3 => out_fifo,
      O => D8(3)
    );
\out_fifo_i_71__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mc_address(24),
      I1 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[1]\,
      I2 => out_fifo_2,
      I3 => mem_out(30),
      I4 => out_fifo,
      O => D8(2)
    );
\out_fifo_i_71__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(142),
      I1 => phy_wrdata(190),
      I2 => out_fifo_21,
      I3 => out_fifo_5(50),
      I4 => out_fifo_6,
      O => \write_buffer.wr_buf_out_data_reg[462]\(2)
    );
\out_fifo_i_71__3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(150),
      I1 => phy_wrdata(190),
      I2 => out_fifo_21,
      I3 => out_fifo_7(50),
      I4 => out_fifo_8,
      O => \write_buffer.wr_buf_out_data_reg[470]\(2)
    );
\out_fifo_i_71__4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(158),
      I1 => phy_wrdata(190),
      I2 => out_fifo_21,
      I3 => out_fifo_9(50),
      I4 => out_fifo_10,
      O => \write_buffer.wr_buf_out_data_reg[478]\(2)
    );
\out_fifo_i_71__5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(174),
      I1 => phy_wrdata(190),
      I2 => out_fifo_22,
      I3 => out_fifo_14(50),
      I4 => out_fifo_15,
      O => \write_buffer.wr_buf_out_data_reg[494]\(2)
    );
\out_fifo_i_71__6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(182),
      I1 => phy_wrdata(190),
      I2 => out_fifo_22,
      I3 => out_fifo_16(50),
      I4 => out_fifo_17,
      O => \write_buffer.wr_buf_out_data_reg[502]\(2)
    );
\out_fifo_i_71__7\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(190),
      I1 => phy_wrdata(190),
      I2 => out_fifo_22,
      I3 => out_fifo_18(50),
      I4 => out_fifo_19,
      O => \write_buffer.wr_buf_out_data_reg[510]\(2)
    );
\out_fifo_i_72__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mc_address(13),
      I1 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[1]\,
      I2 => phy_ctl_wr_i1_reg,
      I3 => mem_out(29),
      I4 => out_fifo,
      O => D8(1)
    );
\out_fifo_i_72__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(78),
      I1 => phy_wrdata(126),
      I2 => out_fifo_20,
      I3 => out_fifo_5(49),
      I4 => out_fifo_6,
      O => \write_buffer.wr_buf_out_data_reg[462]\(1)
    );
\out_fifo_i_72__3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(86),
      I1 => phy_wrdata(126),
      I2 => out_fifo_20,
      I3 => out_fifo_7(49),
      I4 => out_fifo_8,
      O => \write_buffer.wr_buf_out_data_reg[470]\(1)
    );
\out_fifo_i_72__4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(94),
      I1 => phy_wrdata(126),
      I2 => out_fifo_20,
      I3 => out_fifo_9(49),
      I4 => out_fifo_10,
      O => \write_buffer.wr_buf_out_data_reg[478]\(1)
    );
\out_fifo_i_72__5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(110),
      I1 => phy_wrdata(126),
      I2 => out_fifo_20,
      I3 => out_fifo_14(49),
      I4 => out_fifo_15,
      O => \write_buffer.wr_buf_out_data_reg[494]\(1)
    );
\out_fifo_i_72__6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(118),
      I1 => phy_wrdata(126),
      I2 => out_fifo_20,
      I3 => out_fifo_16(49),
      I4 => out_fifo_17,
      O => \write_buffer.wr_buf_out_data_reg[502]\(1)
    );
\out_fifo_i_72__7\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(126),
      I1 => phy_wrdata(126),
      I2 => out_fifo_21,
      I3 => out_fifo_18(49),
      I4 => out_fifo_19,
      O => \write_buffer.wr_buf_out_data_reg[510]\(1)
    );
\out_fifo_i_73__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mc_address(1),
      I1 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[1]\,
      I2 => phy_ctl_wr_i1_reg,
      I3 => mem_out(28),
      I4 => out_fifo,
      O => D8(0)
    );
\out_fifo_i_73__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(14),
      I1 => phy_wrdata(62),
      I2 => out_fifo_2,
      I3 => out_fifo_5(48),
      I4 => out_fifo_6,
      O => \write_buffer.wr_buf_out_data_reg[462]\(0)
    );
\out_fifo_i_73__3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(22),
      I1 => phy_wrdata(62),
      I2 => out_fifo_2,
      I3 => out_fifo_7(48),
      I4 => out_fifo_8,
      O => \write_buffer.wr_buf_out_data_reg[470]\(0)
    );
\out_fifo_i_73__4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(30),
      I1 => phy_wrdata(62),
      I2 => out_fifo_11,
      I3 => out_fifo_9(48),
      I4 => out_fifo_10,
      O => \write_buffer.wr_buf_out_data_reg[478]\(0)
    );
\out_fifo_i_73__5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(46),
      I1 => phy_wrdata(62),
      I2 => out_fifo_11,
      I3 => out_fifo_14(48),
      I4 => out_fifo_15,
      O => \write_buffer.wr_buf_out_data_reg[494]\(0)
    );
\out_fifo_i_73__6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(54),
      I1 => phy_wrdata(62),
      I2 => out_fifo_11,
      I3 => out_fifo_16(48),
      I4 => out_fifo_17,
      O => \write_buffer.wr_buf_out_data_reg[502]\(0)
    );
\out_fifo_i_73__7\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(62),
      I1 => phy_wrdata(62),
      I2 => out_fifo_11,
      I3 => out_fifo_18(48),
      I4 => out_fifo_19,
      O => \write_buffer.wr_buf_out_data_reg[510]\(0)
    );
\out_fifo_i_74__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(455),
      I1 => phy_wrdata(511),
      I2 => out_fifo_27,
      I3 => out_fifo_3(63),
      I4 => out_fifo_4,
      O => \write_buffer.wr_buf_out_data_reg[455]\(7)
    );
\out_fifo_i_74__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(463),
      I1 => phy_wrdata(511),
      I2 => out_fifo_27,
      I3 => out_fifo_5(63),
      I4 => out_fifo_6,
      O => \write_buffer.wr_buf_out_data_reg[463]\(7)
    );
\out_fifo_i_74__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(471),
      I1 => phy_wrdata(511),
      I2 => out_fifo_28,
      I3 => out_fifo_7(63),
      I4 => out_fifo_8,
      O => \write_buffer.wr_buf_out_data_reg[471]\(7)
    );
\out_fifo_i_74__3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(479),
      I1 => phy_wrdata(511),
      I2 => out_fifo_28,
      I3 => out_fifo_9(63),
      I4 => out_fifo_10,
      O => \write_buffer.wr_buf_out_data_reg[479]\(7)
    );
\out_fifo_i_74__4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(487),
      I1 => phy_wrdata(511),
      I2 => out_fifo_28,
      I3 => out_fifo_12(63),
      I4 => out_fifo_13,
      O => \write_buffer.wr_buf_out_data_reg[487]\(7)
    );
\out_fifo_i_74__5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(495),
      I1 => phy_wrdata(511),
      I2 => out_fifo_28,
      I3 => out_fifo_14(63),
      I4 => out_fifo_15,
      O => \write_buffer.wr_buf_out_data_reg[495]\(7)
    );
\out_fifo_i_74__6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(503),
      I1 => phy_wrdata(511),
      I2 => out_fifo_28,
      I3 => out_fifo_16(63),
      I4 => out_fifo_17,
      O => \write_buffer.wr_buf_out_data_reg[503]\(7)
    );
\out_fifo_i_74__7\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(511),
      I1 => phy_wrdata(511),
      I2 => out_fifo_28,
      I3 => out_fifo_18(63),
      I4 => out_fifo_19,
      O => \write_buffer.wr_buf_out_data_reg[511]\(7)
    );
\out_fifo_i_75__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(391),
      I1 => phy_wrdata(447),
      I2 => out_fifo_26,
      I3 => out_fifo_3(62),
      I4 => out_fifo_4,
      O => \write_buffer.wr_buf_out_data_reg[455]\(6)
    );
\out_fifo_i_75__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(399),
      I1 => phy_wrdata(447),
      I2 => out_fifo_26,
      I3 => out_fifo_5(62),
      I4 => out_fifo_6,
      O => \write_buffer.wr_buf_out_data_reg[463]\(6)
    );
\out_fifo_i_75__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(407),
      I1 => phy_wrdata(447),
      I2 => out_fifo_26,
      I3 => out_fifo_7(62),
      I4 => out_fifo_8,
      O => \write_buffer.wr_buf_out_data_reg[471]\(6)
    );
\out_fifo_i_75__3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(415),
      I1 => phy_wrdata(447),
      I2 => out_fifo_26,
      I3 => out_fifo_9(62),
      I4 => out_fifo_10,
      O => \write_buffer.wr_buf_out_data_reg[479]\(6)
    );
\out_fifo_i_75__4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(423),
      I1 => phy_wrdata(447),
      I2 => out_fifo_27,
      I3 => out_fifo_12(62),
      I4 => out_fifo_13,
      O => \write_buffer.wr_buf_out_data_reg[487]\(6)
    );
\out_fifo_i_75__5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(431),
      I1 => phy_wrdata(447),
      I2 => out_fifo_27,
      I3 => out_fifo_14(62),
      I4 => out_fifo_15,
      O => \write_buffer.wr_buf_out_data_reg[495]\(6)
    );
\out_fifo_i_75__6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(439),
      I1 => phy_wrdata(447),
      I2 => out_fifo_27,
      I3 => out_fifo_16(62),
      I4 => out_fifo_17,
      O => \write_buffer.wr_buf_out_data_reg[503]\(6)
    );
\out_fifo_i_75__7\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(447),
      I1 => phy_wrdata(447),
      I2 => out_fifo_27,
      I3 => out_fifo_18(62),
      I4 => out_fifo_19,
      O => \write_buffer.wr_buf_out_data_reg[511]\(6)
    );
out_fifo_i_76: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(327),
      I1 => phy_wrdata(383),
      I2 => out_fifo_25,
      I3 => out_fifo_3(61),
      I4 => out_fifo_4,
      O => \write_buffer.wr_buf_out_data_reg[455]\(5)
    );
\out_fifo_i_76__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(335),
      I1 => phy_wrdata(383),
      I2 => out_fifo_25,
      I3 => out_fifo_5(61),
      I4 => out_fifo_6,
      O => \write_buffer.wr_buf_out_data_reg[463]\(5)
    );
\out_fifo_i_76__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(343),
      I1 => phy_wrdata(383),
      I2 => out_fifo_25,
      I3 => out_fifo_7(61),
      I4 => out_fifo_8,
      O => \write_buffer.wr_buf_out_data_reg[471]\(5)
    );
\out_fifo_i_76__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(351),
      I1 => phy_wrdata(383),
      I2 => out_fifo_25,
      I3 => out_fifo_9(61),
      I4 => out_fifo_10,
      O => \write_buffer.wr_buf_out_data_reg[479]\(5)
    );
\out_fifo_i_76__3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(359),
      I1 => phy_wrdata(383),
      I2 => out_fifo_25,
      I3 => out_fifo_12(61),
      I4 => out_fifo_13,
      O => \write_buffer.wr_buf_out_data_reg[487]\(5)
    );
\out_fifo_i_76__4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(367),
      I1 => phy_wrdata(383),
      I2 => out_fifo_25,
      I3 => out_fifo_14(61),
      I4 => out_fifo_15,
      O => \write_buffer.wr_buf_out_data_reg[495]\(5)
    );
\out_fifo_i_76__5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(375),
      I1 => phy_wrdata(383),
      I2 => out_fifo_26,
      I3 => out_fifo_16(61),
      I4 => out_fifo_17,
      O => \write_buffer.wr_buf_out_data_reg[503]\(5)
    );
\out_fifo_i_76__6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(383),
      I1 => phy_wrdata(383),
      I2 => out_fifo_26,
      I3 => out_fifo_18(61),
      I4 => out_fifo_19,
      O => \write_buffer.wr_buf_out_data_reg[511]\(5)
    );
\out_fifo_i_76__7\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"EEF0"
    )
        port map (
      I0 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[9]\,
      I1 => out_fifo_31,
      I2 => mem_out(35),
      I3 => out_fifo,
      O => \gen_no_mirror.div_clk_loop[0].phy_address_reg[9]_0\(3)
    );
out_fifo_i_77: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mc_address(32),
      I1 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[9]\,
      I2 => out_fifo_2,
      I3 => mem_out(34),
      I4 => out_fifo,
      O => \gen_no_mirror.div_clk_loop[0].phy_address_reg[9]_0\(2)
    );
\out_fifo_i_77__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(263),
      I1 => phy_wrdata(319),
      I2 => out_fifo_23,
      I3 => out_fifo_3(60),
      I4 => out_fifo_4,
      O => \write_buffer.wr_buf_out_data_reg[455]\(4)
    );
\out_fifo_i_77__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(271),
      I1 => phy_wrdata(319),
      I2 => out_fifo_23,
      I3 => out_fifo_5(60),
      I4 => out_fifo_6,
      O => \write_buffer.wr_buf_out_data_reg[463]\(4)
    );
\out_fifo_i_77__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(279),
      I1 => phy_wrdata(319),
      I2 => out_fifo_24,
      I3 => out_fifo_7(60),
      I4 => out_fifo_8,
      O => \write_buffer.wr_buf_out_data_reg[471]\(4)
    );
\out_fifo_i_77__3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(287),
      I1 => phy_wrdata(319),
      I2 => out_fifo_24,
      I3 => out_fifo_9(60),
      I4 => out_fifo_10,
      O => \write_buffer.wr_buf_out_data_reg[479]\(4)
    );
\out_fifo_i_77__4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(295),
      I1 => phy_wrdata(319),
      I2 => out_fifo_24,
      I3 => out_fifo_12(60),
      I4 => out_fifo_13,
      O => \write_buffer.wr_buf_out_data_reg[487]\(4)
    );
\out_fifo_i_77__5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(303),
      I1 => phy_wrdata(319),
      I2 => out_fifo_24,
      I3 => out_fifo_14(60),
      I4 => out_fifo_15,
      O => \write_buffer.wr_buf_out_data_reg[495]\(4)
    );
\out_fifo_i_77__6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(311),
      I1 => phy_wrdata(319),
      I2 => out_fifo_24,
      I3 => out_fifo_16(60),
      I4 => out_fifo_17,
      O => \write_buffer.wr_buf_out_data_reg[503]\(4)
    );
\out_fifo_i_77__7\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(319),
      I1 => phy_wrdata(319),
      I2 => out_fifo_24,
      I3 => out_fifo_18(60),
      I4 => out_fifo_19,
      O => \write_buffer.wr_buf_out_data_reg[511]\(4)
    );
out_fifo_i_78: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mc_address(21),
      I1 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[9]\,
      I2 => phy_ctl_wr_i1_reg,
      I3 => mem_out(33),
      I4 => out_fifo,
      O => \gen_no_mirror.div_clk_loop[0].phy_address_reg[9]_0\(1)
    );
\out_fifo_i_78__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(199),
      I1 => phy_wrdata(255),
      I2 => out_fifo_22,
      I3 => out_fifo_3(59),
      I4 => out_fifo_4,
      O => \write_buffer.wr_buf_out_data_reg[455]\(3)
    );
\out_fifo_i_78__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(207),
      I1 => phy_wrdata(255),
      I2 => out_fifo_22,
      I3 => out_fifo_5(59),
      I4 => out_fifo_6,
      O => \write_buffer.wr_buf_out_data_reg[463]\(3)
    );
\out_fifo_i_78__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(215),
      I1 => phy_wrdata(255),
      I2 => out_fifo_22,
      I3 => out_fifo_7(59),
      I4 => out_fifo_8,
      O => \write_buffer.wr_buf_out_data_reg[471]\(3)
    );
\out_fifo_i_78__3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(223),
      I1 => phy_wrdata(255),
      I2 => out_fifo_23,
      I3 => out_fifo_9(59),
      I4 => out_fifo_10,
      O => \write_buffer.wr_buf_out_data_reg[479]\(3)
    );
\out_fifo_i_78__4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(231),
      I1 => phy_wrdata(255),
      I2 => out_fifo_23,
      I3 => out_fifo_12(59),
      I4 => out_fifo_13,
      O => \write_buffer.wr_buf_out_data_reg[487]\(3)
    );
\out_fifo_i_78__5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(239),
      I1 => phy_wrdata(255),
      I2 => out_fifo_23,
      I3 => out_fifo_14(59),
      I4 => out_fifo_15,
      O => \write_buffer.wr_buf_out_data_reg[495]\(3)
    );
\out_fifo_i_78__6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(247),
      I1 => phy_wrdata(255),
      I2 => out_fifo_23,
      I3 => out_fifo_16(59),
      I4 => out_fifo_17,
      O => \write_buffer.wr_buf_out_data_reg[503]\(3)
    );
\out_fifo_i_78__7\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(255),
      I1 => phy_wrdata(255),
      I2 => out_fifo_23,
      I3 => out_fifo_18(59),
      I4 => out_fifo_19,
      O => \write_buffer.wr_buf_out_data_reg[511]\(3)
    );
out_fifo_i_79: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mc_address(9),
      I1 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[9]\,
      I2 => phy_ctl_wr_i1_reg,
      I3 => mem_out(32),
      I4 => out_fifo,
      O => \gen_no_mirror.div_clk_loop[0].phy_address_reg[9]_0\(0)
    );
\out_fifo_i_79__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(135),
      I1 => phy_wrdata(191),
      I2 => out_fifo_21,
      I3 => out_fifo_3(58),
      I4 => out_fifo_4,
      O => \write_buffer.wr_buf_out_data_reg[455]\(2)
    );
\out_fifo_i_79__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(143),
      I1 => phy_wrdata(191),
      I2 => out_fifo_21,
      I3 => out_fifo_5(58),
      I4 => out_fifo_6,
      O => \write_buffer.wr_buf_out_data_reg[463]\(2)
    );
\out_fifo_i_79__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(151),
      I1 => phy_wrdata(191),
      I2 => out_fifo_21,
      I3 => out_fifo_7(58),
      I4 => out_fifo_8,
      O => \write_buffer.wr_buf_out_data_reg[471]\(2)
    );
\out_fifo_i_79__3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(159),
      I1 => phy_wrdata(191),
      I2 => out_fifo_21,
      I3 => out_fifo_9(58),
      I4 => out_fifo_10,
      O => \write_buffer.wr_buf_out_data_reg[479]\(2)
    );
\out_fifo_i_79__4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(167),
      I1 => phy_wrdata(191),
      I2 => out_fifo_21,
      I3 => out_fifo_12(58),
      I4 => out_fifo_13,
      O => \write_buffer.wr_buf_out_data_reg[487]\(2)
    );
\out_fifo_i_79__5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(175),
      I1 => phy_wrdata(191),
      I2 => out_fifo_22,
      I3 => out_fifo_14(58),
      I4 => out_fifo_15,
      O => \write_buffer.wr_buf_out_data_reg[495]\(2)
    );
\out_fifo_i_79__6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(183),
      I1 => phy_wrdata(191),
      I2 => out_fifo_22,
      I3 => out_fifo_16(58),
      I4 => out_fifo_17,
      O => \write_buffer.wr_buf_out_data_reg[503]\(2)
    );
\out_fifo_i_79__7\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(191),
      I1 => phy_wrdata(191),
      I2 => out_fifo_22,
      I3 => out_fifo_18(58),
      I4 => out_fifo_19,
      O => \write_buffer.wr_buf_out_data_reg[511]\(2)
    );
out_fifo_i_80: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(71),
      I1 => phy_wrdata(127),
      I2 => out_fifo_11,
      I3 => out_fifo_3(57),
      I4 => out_fifo_4,
      O => \write_buffer.wr_buf_out_data_reg[455]\(1)
    );
\out_fifo_i_80__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(79),
      I1 => phy_wrdata(127),
      I2 => out_fifo_20,
      I3 => out_fifo_5(57),
      I4 => out_fifo_6,
      O => \write_buffer.wr_buf_out_data_reg[463]\(1)
    );
\out_fifo_i_80__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(87),
      I1 => phy_wrdata(127),
      I2 => out_fifo_20,
      I3 => out_fifo_7(57),
      I4 => out_fifo_8,
      O => \write_buffer.wr_buf_out_data_reg[471]\(1)
    );
\out_fifo_i_80__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(95),
      I1 => phy_wrdata(127),
      I2 => out_fifo_20,
      I3 => out_fifo_9(57),
      I4 => out_fifo_10,
      O => \write_buffer.wr_buf_out_data_reg[479]\(1)
    );
\out_fifo_i_80__3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(103),
      I1 => phy_wrdata(127),
      I2 => out_fifo_20,
      I3 => out_fifo_12(57),
      I4 => out_fifo_13,
      O => \write_buffer.wr_buf_out_data_reg[487]\(1)
    );
\out_fifo_i_80__4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(111),
      I1 => phy_wrdata(127),
      I2 => out_fifo_20,
      I3 => out_fifo_14(57),
      I4 => out_fifo_15,
      O => \write_buffer.wr_buf_out_data_reg[495]\(1)
    );
\out_fifo_i_80__5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(119),
      I1 => phy_wrdata(127),
      I2 => out_fifo_20,
      I3 => out_fifo_16(57),
      I4 => out_fifo_17,
      O => \write_buffer.wr_buf_out_data_reg[503]\(1)
    );
\out_fifo_i_80__6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(127),
      I1 => phy_wrdata(127),
      I2 => out_fifo_21,
      I3 => out_fifo_18(57),
      I4 => out_fifo_19,
      O => \write_buffer.wr_buf_out_data_reg[511]\(1)
    );
out_fifo_i_81: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(7),
      I1 => phy_wrdata(63),
      I2 => out_fifo_2,
      I3 => out_fifo_3(56),
      I4 => out_fifo_4,
      O => \write_buffer.wr_buf_out_data_reg[455]\(0)
    );
\out_fifo_i_81__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(15),
      I1 => phy_wrdata(63),
      I2 => out_fifo_2,
      I3 => out_fifo_5(56),
      I4 => out_fifo_6,
      O => \write_buffer.wr_buf_out_data_reg[463]\(0)
    );
\out_fifo_i_81__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(23),
      I1 => phy_wrdata(63),
      I2 => out_fifo_2,
      I3 => out_fifo_7(56),
      I4 => out_fifo_8,
      O => \write_buffer.wr_buf_out_data_reg[471]\(0)
    );
\out_fifo_i_81__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(31),
      I1 => phy_wrdata(63),
      I2 => out_fifo_11,
      I3 => out_fifo_9(56),
      I4 => out_fifo_10,
      O => \write_buffer.wr_buf_out_data_reg[479]\(0)
    );
\out_fifo_i_81__3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(39),
      I1 => phy_wrdata(63),
      I2 => out_fifo_11,
      I3 => out_fifo_12(56),
      I4 => out_fifo_13,
      O => \write_buffer.wr_buf_out_data_reg[487]\(0)
    );
\out_fifo_i_81__4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(47),
      I1 => phy_wrdata(63),
      I2 => out_fifo_11,
      I3 => out_fifo_14(56),
      I4 => out_fifo_15,
      O => \write_buffer.wr_buf_out_data_reg[495]\(0)
    );
\out_fifo_i_81__5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(55),
      I1 => phy_wrdata(63),
      I2 => out_fifo_11,
      I3 => out_fifo_16(56),
      I4 => out_fifo_17,
      O => \write_buffer.wr_buf_out_data_reg[503]\(0)
    );
\out_fifo_i_81__6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mem_reg_0_15_78_79(63),
      I1 => phy_wrdata(63),
      I2 => out_fifo_11,
      I3 => out_fifo_18(56),
      I4 => out_fifo_19,
      O => \write_buffer.wr_buf_out_data_reg[511]\(0)
    );
\phy_ctl_wd_i1[0]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mc_cmd(0),
      I1 => calib_cmd(0),
      I2 => \phy_ctl_wd_i1_reg[0]\,
      O => \^calib_seq_reg[1]_0\(0)
    );
\phy_ctl_wd_i1[17]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => \phy_ctl_wd_i1_reg[17]\,
      I1 => calib_data_offset_0(0),
      I2 => \phy_ctl_wd_i1_reg[0]\,
      O => \^calib_seq_reg[1]_0\(3)
    );
\phy_ctl_wd_i1[18]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => \phy_ctl_wd_i1_reg[18]\,
      I1 => calib_data_offset_0(1),
      I2 => \phy_ctl_wd_i1_reg[0]\,
      O => \^calib_seq_reg[1]_0\(4)
    );
\phy_ctl_wd_i1[19]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => \phy_ctl_wd_i1_reg[19]\,
      I1 => calib_data_offset_0(2),
      I2 => \phy_ctl_wd_i1_reg[0]\,
      O => \^calib_seq_reg[1]_0\(5)
    );
\phy_ctl_wd_i1[1]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mc_cmd(1),
      I1 => calib_cmd(1),
      I2 => \phy_ctl_wd_i1_reg[0]\,
      O => \^calib_seq_reg[1]_0\(1)
    );
\phy_ctl_wd_i1[20]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mc_data_offset(0),
      I1 => calib_data_offset_0(3),
      I2 => \phy_ctl_wd_i1_reg[0]\,
      O => \^calib_seq_reg[1]_0\(6)
    );
\phy_ctl_wd_i1[21]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => \phy_ctl_wd_i1_reg[21]\,
      I1 => calib_data_offset_0(4),
      I2 => \phy_ctl_wd_i1_reg[0]\,
      O => \^calib_seq_reg[1]_0\(7)
    );
\phy_ctl_wd_i1[22]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => \phy_ctl_wd_i1_reg[22]\,
      I1 => calib_data_offset_0(5),
      I2 => \phy_ctl_wd_i1_reg[0]\,
      O => \^calib_seq_reg[1]_0\(8)
    );
\phy_ctl_wd_i1[2]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mc_cas_n(0),
      I1 => calib_cmd(2),
      I2 => \phy_ctl_wd_i1_reg[0]\,
      O => \^calib_seq_reg[1]_0\(2)
    );
phy_reset_n_reg: unisim.vcomponents.FDCE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => '1',
      CLR => \en_cnt_div4.enable_wrlvl_cnt_reg[2]_0\,
      D => cnt_pwron_reset_done_r,
      Q => phy_reset_n
    );
pi_calib_done_r1_reg: unisim.vcomponents.FDRE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => '1',
      D => pi_calib_done_r,
      Q => \^pi_calib_done\,
      R => '0'
    );
pi_calib_done_r_i_1: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => pi_calib_rank_done_r,
      I1 => pi_calib_done_r,
      O => pi_calib_done_r_i_1_n_0
    );
pi_calib_done_r_reg: unisim.vcomponents.FDRE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => '1',
      D => pi_calib_done_r_i_1_n_0,
      Q => pi_calib_done_r,
      R => \en_cnt_div4.enable_wrlvl_cnt_reg[2]_0\
    );
pi_calib_rank_done_r_i_1: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => pi_phase_locked_all_r3,
      I1 => pi_phase_locked_all_r4,
      O => init_next_state1100_out
    );
pi_calib_rank_done_r_reg: unisim.vcomponents.FDRE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => '1',
      D => init_next_state1100_out,
      Q => pi_calib_rank_done_r,
      R => \victim_sel_reg[0]_0\(0)
    );
pi_dqs_found_done_r1_reg: unisim.vcomponents.FDRE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => '1',
      D => pi_dqs_found_done_r1_reg_0,
      Q => \^pi_dqs_found_done_r1\,
      R => \en_cnt_div4.enable_wrlvl_cnt_reg[2]_0\
    );
pi_dqs_found_start_i_1: unisim.vcomponents.LUT5
    generic map(
      INIT => X"000000AB"
    )
        port map (
      I0 => \^pi_dqs_found_start_reg_0\,
      I1 => pi_dqs_found_done_r1_reg_0,
      I2 => pi_dqs_found_start_i_2_n_0,
      I3 => wrlvl_byte_redo,
      I4 => \rd_addr_reg[7]\,
      O => pi_dqs_found_start_i_1_n_0
    );
pi_dqs_found_start_i_2: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFEFFFFFFFFFFFF"
    )
        port map (
      I0 => \init_state_r_reg_n_0_[3]\,
      I1 => \init_state_r_reg_n_0_[2]\,
      I2 => init_state_r(6),
      I3 => \init_state_r_reg_n_0_[5]\,
      I4 => \init_state_r_reg_n_0_[4]\,
      I5 => \gen_no_mirror.div_clk_loop[0].phy_address[12]_i_2_n_0\,
      O => pi_dqs_found_start_i_2_n_0
    );
pi_dqs_found_start_reg: unisim.vcomponents.FDRE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => '1',
      D => pi_dqs_found_start_i_1_n_0,
      Q => \^pi_dqs_found_start_reg_0\,
      R => '0'
    );
pi_phase_locked_all_r1_reg: unisim.vcomponents.FDRE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => '1',
      D => pi_phase_locked_all_r1_reg_0,
      Q => pi_phase_locked_all_r1,
      R => '0'
    );
pi_phase_locked_all_r2_reg: unisim.vcomponents.FDRE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => '1',
      D => pi_phase_locked_all_r1,
      Q => pi_phase_locked_all_r2,
      R => '0'
    );
pi_phase_locked_all_r3_reg: unisim.vcomponents.FDRE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => '1',
      D => pi_phase_locked_all_r2,
      Q => pi_phase_locked_all_r3,
      R => '0'
    );
pi_phase_locked_all_r4_reg: unisim.vcomponents.FDRE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => '1',
      D => pi_phase_locked_all_r3,
      Q => pi_phase_locked_all_r4,
      R => '0'
    );
prbs_gen_clk_en_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"000000000E0E0E00"
    )
        port map (
      I0 => \^one_rank.stg1_wr_done_reg_0\,
      I1 => wr_victim_inc_i_2_n_0,
      I2 => \rd_addr_reg[7]\,
      I3 => prbs_gen_clk_en0,
      I4 => prbs_gen_clk_en,
      I5 => complex_oclkdelay_calib_done_r1_reg_0,
      O => prbs_gen_clk_en_i_1_n_0
    );
prbs_gen_clk_en_i_2: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFF444444F4"
    )
        port map (
      I0 => prbs_gen_clk_en_i_3_n_0,
      I1 => rdlvl_stg1_done_r1,
      I2 => \^prbs_rdlvl_start_reg_0\,
      I3 => prbs_gen_clk_en_i_4_n_0,
      I4 => prbs_rdlvl_start_i_2_n_0,
      I5 => \stg1_wr_rd_cnt[8]_i_4_n_0\,
      O => prbs_gen_clk_en0
    );
prbs_gen_clk_en_i_3: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00D0D0D0D0D0D0D0"
    )
        port map (
      I0 => \complex_num_writes[3]_i_4_n_0\,
      I1 => prbs_gen_clk_en_i_5_n_0,
      I2 => \rd_addr_reg[7]_0\,
      I3 => \cnt_cmd_r[6]_i_4_n_0\,
      I4 => \cnt_cmd_r_reg_n_0_[6]\,
      I5 => \stg1_wr_rd_cnt[4]_i_4_n_0\,
      O => prbs_gen_clk_en_i_3_n_0
    );
prbs_gen_clk_en_i_4: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFEFFFF"
    )
        port map (
      I0 => \init_state_r_reg_n_0_[3]\,
      I1 => \init_state_r_reg_n_0_[2]\,
      I2 => init_state_r(6),
      I3 => \init_state_r_reg_n_0_[5]\,
      I4 => \init_state_r_reg_n_0_[4]\,
      O => prbs_gen_clk_en_i_4_n_0
    );
prbs_gen_clk_en_i_5: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FF7F"
    )
        port map (
      I0 => complex_wait_cnt_reg(2),
      I1 => complex_wait_cnt_reg(3),
      I2 => complex_wait_cnt_reg(1),
      I3 => complex_wait_cnt_reg(0),
      O => prbs_gen_clk_en_i_5_n_0
    );
prbs_gen_clk_en_reg: unisim.vcomponents.FDRE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => '1',
      D => prbs_gen_clk_en_i_1_n_0,
      Q => prbs_gen_clk_en,
      R => '0'
    );
prbs_gen_oclk_clk_en_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000000080"
    )
        port map (
      I0 => prbs_gen_oclk_clk_en_i_2_n_0,
      I1 => complex_ocal_wr_start,
      I2 => prbs_gen_oclk_clk_en_i_3_n_0,
      I3 => prbs_gen_oclk_clk_en_i_4_n_0,
      I4 => prbs_gen_oclk_clk_en_i_5_n_0,
      I5 => prbs_gen_oclk_clk_en_i_6_n_0,
      O => prbs_gen_oclk_clk_en_i_1_n_0
    );
prbs_gen_oclk_clk_en_i_10: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000080000000000"
    )
        port map (
      I0 => complex_byte_rd_done,
      I1 => \init_state_r_reg_n_0_[4]\,
      I2 => init_state_r(6),
      I3 => \init_state_r_reg_n_0_[5]\,
      I4 => \wrcal_reads[7]_i_4_n_0\,
      I5 => detect_pi_found_dqs_i_2_n_0,
      O => prbs_gen_oclk_clk_en_i_10_n_0
    );
prbs_gen_oclk_clk_en_i_11: unisim.vcomponents.LUT5
    generic map(
      INIT => X"10000000"
    )
        port map (
      I0 => init_state_r1(0),
      I1 => init_state_r1(6),
      I2 => init_state_r1(5),
      I3 => init_state_r1(4),
      I4 => init_state_r1(3),
      O => prbs_gen_oclk_clk_en_i_11_n_0
    );
prbs_gen_oclk_clk_en_i_12: unisim.vcomponents.LUT5
    generic map(
      INIT => X"F7FFFFFF"
    )
        port map (
      I0 => \init_state_r_reg_n_0_[3]\,
      I1 => \init_state_r_reg_n_0_[4]\,
      I2 => init_state_r(6),
      I3 => \init_state_r_reg_n_0_[5]\,
      I4 => \init_state_r_reg_n_0_[2]\,
      O => prbs_gen_oclk_clk_en_i_12_n_0
    );
prbs_gen_oclk_clk_en_i_2: unisim.vcomponents.LUT3
    generic map(
      INIT => X"54"
    )
        port map (
      I0 => write_calib_reg_0,
      I1 => wr_victim_inc_i_2_n_0,
      I2 => \^one_rank.stg1_wr_done_reg_0\,
      O => prbs_gen_oclk_clk_en_i_2_n_0
    );
prbs_gen_oclk_clk_en_i_3: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000EEEFEEEE"
    )
        port map (
      I0 => prbs_gen_oclk_clk_en,
      I1 => prbs_gen_oclk_clk_en_i_7_n_0,
      I2 => \^one_rank.stg1_wr_done_reg_0\,
      I3 => complex_row1_wr_done,
      I4 => prbs_gen_oclk_clk_en_i_8_n_0,
      I5 => complex_oclkdelay_calib_done_r1_reg_0,
      O => prbs_gen_oclk_clk_en_i_3_n_0
    );
prbs_gen_oclk_clk_en_i_4: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000000008"
    )
        port map (
      I0 => \init_state_r[5]_i_13_n_0\,
      I1 => \complex_num_writes_reg_n_0_[0]\,
      I2 => \complex_num_writes_reg_n_0_[1]\,
      I3 => \complex_num_writes_reg_n_0_[2]\,
      I4 => \complex_num_writes_reg_n_0_[3]\,
      I5 => \complex_num_writes_reg_n_0_[4]\,
      O => prbs_gen_oclk_clk_en_i_4_n_0
    );
prbs_gen_oclk_clk_en_i_5: unisim.vcomponents.LUT6
    generic map(
      INIT => X"11111F1111111111"
    )
        port map (
      I0 => complex_oclkdelay_calib_start_int_i_2_n_0,
      I1 => prbs_rdlvl_start_i_2_n_0,
      I2 => prbs_gen_oclk_clk_en_i_9_n_0,
      I3 => complex_num_writes_dec(1),
      I4 => complex_num_writes_dec(0),
      I5 => \stg1_wr_rd_cnt[8]_i_5_n_0\,
      O => prbs_gen_oclk_clk_en_i_5_n_0
    );
prbs_gen_oclk_clk_en_i_6: unisim.vcomponents.LUT6
    generic map(
      INIT => X"EAAAAAAAEAAAEAAA"
    )
        port map (
      I0 => prbs_gen_oclk_clk_en_i_10_n_0,
      I1 => init_state_r1(2),
      I2 => init_state_r1(1),
      I3 => prbs_gen_oclk_clk_en_i_11_n_0,
      I4 => prbs_gen_oclk_clk_en_i_12_n_0,
      I5 => detect_pi_found_dqs_i_2_n_0,
      O => prbs_gen_oclk_clk_en_i_6_n_0
    );
prbs_gen_oclk_clk_en_i_7: unisim.vcomponents.LUT6
    generic map(
      INIT => X"CFCCCFCCFFFFEFEE"
    )
        port map (
      I0 => \complex_address[9]_i_3_n_0\,
      I1 => \stg1_wr_rd_cnt[8]_i_4_n_0\,
      I2 => \rd_addr_reg[7]_0\,
      I3 => prbs_rdlvl_done_r1,
      I4 => complex_ocal_reset_rd_addr_i_3_n_0,
      I5 => prbs_gen_clk_en_i_5_n_0,
      O => prbs_gen_oclk_clk_en_i_7_n_0
    );
prbs_gen_oclk_clk_en_i_8: unisim.vcomponents.LUT5
    generic map(
      INIT => X"20000000"
    )
        port map (
      I0 => \complex_num_writes[3]_i_4_n_0\,
      I1 => complex_wait_cnt_reg(0),
      I2 => complex_wait_cnt_reg(1),
      I3 => complex_wait_cnt_reg(3),
      I4 => complex_wait_cnt_reg(2),
      O => prbs_gen_oclk_clk_en_i_8_n_0
    );
prbs_gen_oclk_clk_en_i_9: unisim.vcomponents.LUT3
    generic map(
      INIT => X"FE"
    )
        port map (
      I0 => complex_num_writes_dec(2),
      I1 => complex_num_writes_dec(4),
      I2 => complex_num_writes_dec(3),
      O => prbs_gen_oclk_clk_en_i_9_n_0
    );
prbs_gen_oclk_clk_en_reg: unisim.vcomponents.FDRE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => '1',
      D => prbs_gen_oclk_clk_en_i_1_n_0,
      Q => prbs_gen_oclk_clk_en,
      R => '0'
    );
prbs_last_byte_done_r_reg: unisim.vcomponents.FDRE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => '1',
      D => prbs_last_byte_done,
      Q => prbs_last_byte_done_r,
      R => '0'
    );
prbs_rdlvl_done_pulse_reg: unisim.vcomponents.FDRE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => '1',
      D => prbs_rdlvl_done_pulse0,
      Q => \^prbs_rdlvl_done_pulse_reg_0\,
      R => '0'
    );
prbs_rdlvl_start_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFF00000020"
    )
        port map (
      I0 => pi_dqs_found_done_r1_reg_0,
      I1 => complex_oclkdelay_calib_done_r1_reg_0,
      I2 => prbs_rdlvl_start_reg_2,
      I3 => prbs_rdlvl_start_i_2_n_0,
      I4 => prbs_rdlvl_start_i_3_n_0,
      I5 => \^prbs_rdlvl_start_reg_0\,
      O => prbs_rdlvl_start_i_1_n_0
    );
prbs_rdlvl_start_i_2: unisim.vcomponents.LUT2
    generic map(
      INIT => X"7"
    )
        port map (
      I0 => \init_state_r_reg_n_0_[1]\,
      I1 => \^q\(0),
      O => prbs_rdlvl_start_i_2_n_0
    );
prbs_rdlvl_start_i_3: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFEFFFF"
    )
        port map (
      I0 => \init_state_r_reg_n_0_[4]\,
      I1 => \init_state_r_reg_n_0_[3]\,
      I2 => \init_state_r_reg_n_0_[2]\,
      I3 => \init_state_r_reg_n_0_[5]\,
      I4 => init_state_r(6),
      O => prbs_rdlvl_start_i_3_n_0
    );
prbs_rdlvl_start_reg: unisim.vcomponents.FDRE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => '1',
      D => prbs_rdlvl_start_i_1_n_0,
      Q => \^prbs_rdlvl_start_reg_0\,
      R => \victim_sel_reg[0]_0\(0)
    );
\prech_done_dly_r_reg[15]_srl16\: unisim.vcomponents.SRL16E
     port map (
      A0 => '1',
      A1 => '1',
      A2 => '1',
      A3 => '1',
      CE => '1',
      CLK => \rdlvl_start_dly0_r_reg[14]_0\,
      D => prech_done_pre,
      Q => \prech_done_dly_r_reg[15]_srl16_n_0\
    );
\prech_done_dly_r_reg[15]_srl16_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => prech_pending_r_i_2_n_0,
      I1 => \^prech_req_posedge_r_reg_0\,
      O => prech_done_pre
    );
prech_done_reg: unisim.vcomponents.FDRE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => '1',
      D => \prech_done_dly_r_reg[15]_srl16_n_0\,
      Q => prech_done,
      R => '0'
    );
prech_pending_r_i_1: unisim.vcomponents.LUT3
    generic map(
      INIT => X"BA"
    )
        port map (
      I0 => \^prech_req_posedge_r_reg_0\,
      I1 => prech_pending_r_i_2_n_0,
      I2 => prech_pending_r,
      O => prech_pending_r_i_1_n_0
    );
prech_pending_r_i_2: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAA800AAAAAAAA"
    )
        port map (
      I0 => prech_pending_r,
      I1 => \complex_row_cnt_ocal[3]_i_6_n_0\,
      I2 => prech_pending_r_i_3_n_0,
      I3 => prbs_last_byte_done_r,
      I4 => prech_pending_r_i_4_n_0,
      I5 => prech_pending_r_i_5_n_0,
      O => prech_pending_r_i_2_n_0
    );
prech_pending_r_i_3: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000000008"
    )
        port map (
      I0 => cnt_cmd_done_r,
      I1 => \gen_no_mirror.div_clk_loop[0].phy_address[12]_i_2_n_0\,
      I2 => \init_state_r_reg_n_0_[4]\,
      I3 => \init_state_r_reg_n_0_[5]\,
      I4 => init_state_r(6),
      I5 => rdlvl_stg1_start_int_i_2_n_0,
      O => prech_pending_r_i_3_n_0
    );
prech_pending_r_i_4: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFF8FF"
    )
        port map (
      I0 => \stg1_wr_rd_cnt[4]_i_4_n_0\,
      I1 => dqs_found_prech_req,
      I2 => \^stg1_wr_done\,
      I3 => rdlvl_stg1_start_i_2_n_0,
      I4 => \num_refresh[3]_i_5_n_0\,
      O => prech_pending_r_i_4_n_0
    );
prech_pending_r_i_5: unisim.vcomponents.LUT6
    generic map(
      INIT => X"DDD0DDDDDDDDDDDD"
    )
        port map (
      I0 => cnt_cmd_done_r,
      I1 => prech_pending_r_i_6_n_0,
      I2 => complex_oclkdelay_calib_start_int_i_2_n_0,
      I3 => \^q\(0),
      I4 => \init_state_r_reg_n_0_[1]\,
      I5 => complex_oclkdelay_calib_start_r1,
      O => prech_pending_r_i_5_n_0
    );
prech_pending_r_i_6: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000CCFDCCFDCCFD"
    )
        port map (
      I0 => \wrcal_reads[7]_i_5_n_0\,
      I1 => \wrcal_reads[7]_i_7_n_0\,
      I2 => \cnt_init_mr_r[0]_i_2_n_0\,
      I3 => \init_state_r[0]_i_30_n_0\,
      I4 => \stg1_wr_rd_cnt[4]_i_4_n_0\,
      I5 => rdlvl_last_byte_done_r,
      O => prech_pending_r_i_6_n_0
    );
prech_pending_r_reg: unisim.vcomponents.FDRE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => '1',
      D => prech_pending_r_i_1_n_0,
      Q => prech_pending_r,
      R => \en_cnt_div4.enable_wrlvl_cnt_reg[2]_0\
    );
prech_req_posedge_r_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"5555555455545554"
    )
        port map (
      I0 => prech_req_r,
      I1 => rdlvl_prech_req,
      I2 => wrcal_prech_req,
      I3 => prech_req_posedge_r_reg_1,
      I4 => dqs_found_prech_req,
      I5 => \^init_state_r_reg[4]_1\,
      O => prech_req_posedge_r0
    );
prech_req_posedge_r_i_2: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000000008"
    )
        port map (
      I0 => detect_pi_found_dqs_i_2_n_0,
      I1 => \init_state_r_reg_n_0_[4]\,
      I2 => \init_state_r_reg_n_0_[5]\,
      I3 => init_state_r(6),
      I4 => \init_state_r_reg_n_0_[2]\,
      I5 => \init_state_r_reg_n_0_[3]\,
      O => \^init_state_r_reg[4]_1\
    );
prech_req_posedge_r_reg: unisim.vcomponents.FDRE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => '1',
      D => prech_req_posedge_r0,
      Q => \^prech_req_posedge_r_reg_0\,
      R => \victim_sel_reg[0]_0\(0)
    );
prech_req_r_reg: unisim.vcomponents.FDRE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => '1',
      D => prech_req,
      Q => prech_req_r,
      R => \victim_sel_reg[0]_0\(0)
    );
pwron_ce_r_i_1: unisim.vcomponents.LUT5
    generic map(
      INIT => X"80000000"
    )
        port map (
      I0 => cnt_pwron_ce_r_reg(9),
      I1 => cnt_pwron_ce_r_reg(7),
      I2 => pwron_ce_r_i_2_n_0,
      I3 => cnt_pwron_ce_r_reg(6),
      I4 => cnt_pwron_ce_r_reg(8),
      O => pwron_ce_r_i_1_n_0
    );
pwron_ce_r_i_2: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8000000000000000"
    )
        port map (
      I0 => cnt_pwron_ce_r_reg(5),
      I1 => cnt_pwron_ce_r_reg(3),
      I2 => cnt_pwron_ce_r_reg(1),
      I3 => cnt_pwron_ce_r_reg(0),
      I4 => cnt_pwron_ce_r_reg(2),
      I5 => cnt_pwron_ce_r_reg(4),
      O => pwron_ce_r_i_2_n_0
    );
pwron_ce_r_reg: unisim.vcomponents.FDRE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => '1',
      D => pwron_ce_r_i_1_n_0,
      Q => pwron_ce_r,
      R => \victim_sel_reg[0]_0\(0)
    );
\rd_addr[2]_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FF575757"
    )
        port map (
      I0 => complex_oclkdelay_calib_done_r1_reg_0,
      I1 => prbs_gen_clk_en,
      I2 => prbs_gen_oclk_clk_en,
      I3 => complex_wr_done,
      I4 => \rd_addr_reg[7]_0\,
      O => prbs_rdlvl_done_reg_0
    );
\rd_addr[3]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"BFBFBFAAAAAAAAAA"
    )
        port map (
      I0 => \rd_addr_reg[3]\(0),
      I1 => \rd_addr_reg[7]_0\,
      I2 => complex_wr_done,
      I3 => prbs_gen_oclk_clk_en,
      I4 => prbs_gen_clk_en,
      I5 => complex_oclkdelay_calib_done_r1_reg_0,
      O => \rd_addr_reg[1]\
    );
\rd_addr[7]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"FE"
    )
        port map (
      I0 => \rd_addr_reg[7]\,
      I1 => \^complex_ocal_reset_rd_addr\,
      I2 => reset_rd_addr,
      O => SR(0)
    );
\rd_addr[7]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0BFF0BFF0BFF0000"
    )
        port map (
      I0 => complex_oclkdelay_calib_done_r1_reg_0,
      I1 => \^prbs_rdlvl_start_reg_0\,
      I2 => complex_wr_done,
      I3 => \rd_addr_reg[7]_0\,
      I4 => prbs_gen_clk_en,
      I5 => prbs_gen_oclk_clk_en,
      O => prbs_rdlvl_done_reg(0)
    );
rdlvl_last_byte_done_r_reg: unisim.vcomponents.FDRE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => '1',
      D => rdlvl_last_byte_done,
      Q => rdlvl_last_byte_done_r,
      R => '0'
    );
\rdlvl_start_dly0_r_reg[13]_srl14\: unisim.vcomponents.SRL16E
     port map (
      A0 => '1',
      A1 => '0',
      A2 => '1',
      A3 => '1',
      CE => '1',
      CLK => \rdlvl_start_dly0_r_reg[14]_0\,
      D => rdlvl_start_pre,
      Q => \rdlvl_start_dly0_r_reg[13]_srl14_n_0\
    );
\rdlvl_start_dly0_r_reg[14]\: unisim.vcomponents.FDRE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => '1',
      D => \rdlvl_start_dly0_r_reg[13]_srl14_n_0\,
      Q => rdlvl_start_dly0_r(14),
      R => '0'
    );
rdlvl_start_pre_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFF00080000"
    )
        port map (
      I0 => pi_dqs_found_done_r1_reg_0,
      I1 => \wrcal_reads[7]_i_5_n_0\,
      I2 => \cnt_init_mr_r[0]_i_2_n_0\,
      I3 => \init_state_r[3]_i_6_n_0\,
      I4 => \init_state_r_reg_n_0_[4]\,
      I5 => rdlvl_start_pre,
      O => rdlvl_start_pre_i_1_n_0
    );
rdlvl_start_pre_reg: unisim.vcomponents.FDRE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => '1',
      D => rdlvl_start_pre_i_1_n_0,
      Q => rdlvl_start_pre,
      R => \en_cnt_div4.enable_wrlvl_cnt_reg[2]_0\
    );
rdlvl_stg1_start_i_1: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FB08"
    )
        port map (
      I0 => rdlvl_start_dly0_r(14),
      I1 => pi_dqs_found_done_r1_reg_0,
      I2 => rdlvl_stg1_start_i_2_n_0,
      I3 => \^rdlvl_stg1_start_reg_0\,
      O => rdlvl_stg1_start_i_1_n_0
    );
rdlvl_stg1_start_i_2: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFDFFFFFFFF"
    )
        port map (
      I0 => \init_state_r_reg_n_0_[4]\,
      I1 => \init_state_r_reg_n_0_[5]\,
      I2 => init_state_r(6),
      I3 => \init_state_r_reg_n_0_[2]\,
      I4 => \init_state_r_reg_n_0_[3]\,
      I5 => \wrcal_reads[7]_i_5_n_0\,
      O => rdlvl_stg1_start_i_2_n_0
    );
rdlvl_stg1_start_int_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFF00008000"
    )
        port map (
      I0 => pi_dqs_found_done_r1_reg_0,
      I1 => cnt_cmd_done_r,
      I2 => \gen_no_mirror.div_clk_loop[0].phy_address[12]_i_2_n_0\,
      I3 => \cnt_init_mr_r[0]_i_3_n_0\,
      I4 => rdlvl_stg1_start_int_i_2_n_0,
      I5 => rdlvl_stg1_start_int,
      O => rdlvl_stg1_start_int_i_1_n_0
    );
rdlvl_stg1_start_int_i_2: unisim.vcomponents.LUT2
    generic map(
      INIT => X"7"
    )
        port map (
      I0 => \init_state_r_reg_n_0_[3]\,
      I1 => \init_state_r_reg_n_0_[2]\,
      O => rdlvl_stg1_start_int_i_2_n_0
    );
rdlvl_stg1_start_int_reg: unisim.vcomponents.FDRE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => '1',
      D => rdlvl_stg1_start_int_i_1_n_0,
      Q => rdlvl_stg1_start_int,
      R => \en_cnt_div4.enable_wrlvl_cnt_reg[2]_0\
    );
rdlvl_stg1_start_reg: unisim.vcomponents.FDRE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => '1',
      D => rdlvl_stg1_start_i_1_n_0,
      Q => \^rdlvl_stg1_start_reg_0\,
      R => \victim_sel_reg[0]_0\(0)
    );
read_calib_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000055550100"
    )
        port map (
      I0 => write_calib_reg_0,
      I1 => \wrcal_reads[7]_i_4_n_0\,
      I2 => \wrcal_reads[7]_i_7_n_0\,
      I3 => detect_pi_found_dqs_i_2_n_0,
      I4 => \^phy_read_calib\,
      I5 => \^pi_calib_done\,
      O => read_calib_i_1_n_0
    );
read_calib_reg: unisim.vcomponents.FDRE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => '1',
      D => read_calib_i_1_n_0,
      Q => \^phy_read_calib\,
      R => '0'
    );
\read_fifo.tail_r[0]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \^init_complete_r1_timing_reg_0\,
      I1 => \read_fifo.tail_r\(0),
      O => \read_fifo.tail_r_reg[0]\
    );
\reg_ctrl_cnt_r[0]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => reg_ctrl_cnt_r_reg(0),
      O => \p_0_in__3\(0)
    );
\reg_ctrl_cnt_r[1]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => reg_ctrl_cnt_r_reg(1),
      I1 => reg_ctrl_cnt_r_reg(0),
      O => \p_0_in__3\(1)
    );
\reg_ctrl_cnt_r[2]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"6A"
    )
        port map (
      I0 => reg_ctrl_cnt_r_reg(2),
      I1 => reg_ctrl_cnt_r_reg(0),
      I2 => reg_ctrl_cnt_r_reg(1),
      O => \p_0_in__3\(2)
    );
\reg_ctrl_cnt_r[3]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000100000000"
    )
        port map (
      I0 => \init_state_r_reg_n_0_[3]\,
      I1 => \init_state_r_reg_n_0_[2]\,
      I2 => \init_state_r_reg_n_0_[4]\,
      I3 => \init_state_r_reg_n_0_[5]\,
      I4 => init_state_r(6),
      I5 => \wrcal_reads[7]_i_5_n_0\,
      O => \reg_ctrl_cnt_r[3]_i_1_n_0\
    );
\reg_ctrl_cnt_r[3]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000400000000"
    )
        port map (
      I0 => \init_state_r_reg_n_0_[2]\,
      I1 => \init_state_r_reg_n_0_[3]\,
      I2 => init_state_r(6),
      I3 => \init_state_r_reg_n_0_[5]\,
      I4 => prbs_rdlvl_start_i_2_n_0,
      I5 => \init_state_r_reg_n_0_[4]\,
      O => reg_ctrl_cnt_r
    );
\reg_ctrl_cnt_r[3]_i_3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6AAA"
    )
        port map (
      I0 => reg_ctrl_cnt_r_reg(3),
      I1 => reg_ctrl_cnt_r_reg(1),
      I2 => reg_ctrl_cnt_r_reg(0),
      I3 => reg_ctrl_cnt_r_reg(2),
      O => \p_0_in__3\(3)
    );
\reg_ctrl_cnt_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => reg_ctrl_cnt_r,
      D => \p_0_in__3\(0),
      Q => reg_ctrl_cnt_r_reg(0),
      R => \reg_ctrl_cnt_r[3]_i_1_n_0\
    );
\reg_ctrl_cnt_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => reg_ctrl_cnt_r,
      D => \p_0_in__3\(1),
      Q => reg_ctrl_cnt_r_reg(1),
      R => \reg_ctrl_cnt_r[3]_i_1_n_0\
    );
\reg_ctrl_cnt_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => reg_ctrl_cnt_r,
      D => \p_0_in__3\(2),
      Q => reg_ctrl_cnt_r_reg(2),
      R => \reg_ctrl_cnt_r[3]_i_1_n_0\
    );
\reg_ctrl_cnt_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => reg_ctrl_cnt_r,
      D => \p_0_in__3\(3),
      Q => reg_ctrl_cnt_r_reg(3),
      R => \reg_ctrl_cnt_r[3]_i_1_n_0\
    );
reset_rd_addr_r1_reg: unisim.vcomponents.FDRE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => '1',
      D => reset_rd_addr0,
      Q => reset_rd_addr_r1,
      R => '0'
    );
\row_cnt_victim_rotate.complex_row_cnt[0]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"55550455"
    )
        port map (
      I0 => \row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[0]\,
      I1 => \row_cnt_victim_rotate.complex_row_cnt[4]_i_5_n_0\,
      I2 => \^one_rank.stg1_wr_done_reg_0\,
      I3 => complex_sample_cnt_inc_r2,
      I4 => \row_cnt_victim_rotate.complex_row_cnt_reg[6]_0\,
      O => \row_cnt_victim_rotate.complex_row_cnt[0]_i_1_n_0\
    );
\row_cnt_victim_rotate.complex_row_cnt[1]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8BB8"
    )
        port map (
      I0 => \row_cnt_victim_rotate.complex_row_cnt_reg[1]_0\,
      I1 => \row_cnt_victim_rotate.complex_row_cnt[3]_i_2_n_0\,
      I2 => \row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[1]\,
      I3 => \row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[0]\,
      O => \row_cnt_victim_rotate.complex_row_cnt[1]_i_1_n_0\
    );
\row_cnt_victim_rotate.complex_row_cnt[2]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"8BB8B8B8"
    )
        port map (
      I0 => \row_cnt_victim_rotate.complex_row_cnt_reg[2]_0\,
      I1 => \row_cnt_victim_rotate.complex_row_cnt[3]_i_2_n_0\,
      I2 => \row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[2]\,
      I3 => \row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[0]\,
      I4 => \row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[1]\,
      O => \row_cnt_victim_rotate.complex_row_cnt[2]_i_1_n_0\
    );
\row_cnt_victim_rotate.complex_row_cnt[3]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8BB8B8B8B8B8B8B8"
    )
        port map (
      I0 => \row_cnt_victim_rotate.complex_row_cnt_reg[3]_0\,
      I1 => \row_cnt_victim_rotate.complex_row_cnt[3]_i_2_n_0\,
      I2 => \row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[3]\,
      I3 => \row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[1]\,
      I4 => \row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[0]\,
      I5 => \row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[2]\,
      O => \row_cnt_victim_rotate.complex_row_cnt[3]_i_1_n_0\
    );
\row_cnt_victim_rotate.complex_row_cnt[3]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4044"
    )
        port map (
      I0 => \row_cnt_victim_rotate.complex_row_cnt_reg[6]_0\,
      I1 => complex_sample_cnt_inc_r2,
      I2 => \^one_rank.stg1_wr_done_reg_0\,
      I3 => \row_cnt_victim_rotate.complex_row_cnt[4]_i_5_n_0\,
      O => \row_cnt_victim_rotate.complex_row_cnt[3]_i_2_n_0\
    );
\row_cnt_victim_rotate.complex_row_cnt[4]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"EFEFEEEFAAAAAAAA"
    )
        port map (
      I0 => \row_cnt_victim_rotate.complex_row_cnt[4]_i_4_n_0\,
      I1 => reset_rd_addr_r1,
      I2 => \row_cnt_victim_rotate.complex_row_cnt[4]_i_5_n_0\,
      I3 => complex_sample_cnt_inc_r2,
      I4 => \row_cnt_victim_rotate.complex_row_cnt_reg[6]_0\,
      I5 => \row_cnt_victim_rotate.complex_row_cnt[4]_i_6_n_0\,
      O => \row_cnt_victim_rotate.complex_row_cnt[4]_i_1_n_0\
    );
\row_cnt_victim_rotate.complex_row_cnt[4]_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"0E"
    )
        port map (
      I0 => \row_cnt_victim_rotate.complex_row_cnt[4]_i_5_n_0\,
      I1 => \^one_rank.stg1_wr_done_reg_0\,
      I2 => \row_cnt_victim_rotate.complex_row_cnt[4]_i_7_n_0\,
      O => complex_row_cnt
    );
\row_cnt_victim_rotate.complex_row_cnt[4]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"1555555540000000"
    )
        port map (
      I0 => \row_cnt_victim_rotate.complex_row_cnt[4]_i_8_n_0\,
      I1 => \row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[3]\,
      I2 => \row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[1]\,
      I3 => \row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[0]\,
      I4 => \row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[2]\,
      I5 => \row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[4]\,
      O => \row_cnt_victim_rotate.complex_row_cnt[4]_i_3_n_0\
    );
\row_cnt_victim_rotate.complex_row_cnt[4]_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"FB"
    )
        port map (
      I0 => p_81_in,
      I1 => rdlvl_stg1_done_r1,
      I2 => complex_oclkdelay_calib_done_r1_reg_0,
      O => \row_cnt_victim_rotate.complex_row_cnt[4]_i_4_n_0\
    );
\row_cnt_victim_rotate.complex_row_cnt[4]_i_5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000001"
    )
        port map (
      I0 => \row_cnt_victim_rotate.complex_row_cnt[5]_i_2_n_0\,
      I1 => \row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[6]\,
      I2 => \row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[5]\,
      I3 => \row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[4]\,
      I4 => \row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[7]\,
      O => \row_cnt_victim_rotate.complex_row_cnt[4]_i_5_n_0\
    );
\row_cnt_victim_rotate.complex_row_cnt[4]_i_6\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \^one_rank.stg1_wr_done_reg_0\,
      I1 => \row_cnt_victim_rotate.complex_row_cnt[4]_i_7_n_0\,
      O => \row_cnt_victim_rotate.complex_row_cnt[4]_i_6_n_0\
    );
\row_cnt_victim_rotate.complex_row_cnt[4]_i_7\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000100010001"
    )
        port map (
      I0 => reset_rd_addr_r1,
      I1 => \row_cnt_victim_rotate.complex_row_cnt_reg[6]_0\,
      I2 => wr_victim_inc,
      I3 => complex_sample_cnt_inc_r2,
      I4 => \complex_row_cnt_ocal[3]_i_6_n_0\,
      I5 => \row_cnt_victim_rotate.complex_row_cnt[4]_i_9_n_0\,
      O => \row_cnt_victim_rotate.complex_row_cnt[4]_i_7_n_0\
    );
\row_cnt_victim_rotate.complex_row_cnt[4]_i_8\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => complex_sample_cnt_inc_r2,
      I1 => \row_cnt_victim_rotate.complex_row_cnt_reg[6]_0\,
      O => \row_cnt_victim_rotate.complex_row_cnt[4]_i_8_n_0\
    );
\row_cnt_victim_rotate.complex_row_cnt[4]_i_9\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000004000000"
    )
        port map (
      I0 => \stg1_wr_rd_cnt_reg_n_0_[3]\,
      I1 => \stg1_wr_rd_cnt_reg_n_0_[1]\,
      I2 => \stg1_wr_rd_cnt_reg_n_0_[0]\,
      I3 => \stg1_wr_rd_cnt_reg_n_0_[4]\,
      I4 => \stg1_wr_rd_cnt_reg_n_0_[2]\,
      I5 => wr_victim_inc_i_3_n_0,
      O => \row_cnt_victim_rotate.complex_row_cnt[4]_i_9_n_0\
    );
\row_cnt_victim_rotate.complex_row_cnt[5]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000022226AAA"
    )
        port map (
      I0 => \row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[5]\,
      I1 => complex_row_cnt,
      I2 => \row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[4]\,
      I3 => \row_cnt_victim_rotate.complex_row_cnt[5]_i_2_n_0\,
      I4 => \row_cnt_victim_rotate.complex_row_cnt[4]_i_8_n_0\,
      I5 => \row_cnt_victim_rotate.complex_row_cnt[7]_i_3_n_0\,
      O => \row_cnt_victim_rotate.complex_row_cnt[5]_i_1_n_0\
    );
\row_cnt_victim_rotate.complex_row_cnt[5]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8000"
    )
        port map (
      I0 => \row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[3]\,
      I1 => \row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[1]\,
      I2 => \row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[0]\,
      I3 => \row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[2]\,
      O => \row_cnt_victim_rotate.complex_row_cnt[5]_i_2_n_0\
    );
\row_cnt_victim_rotate.complex_row_cnt[6]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"000000006626AA2A"
    )
        port map (
      I0 => \row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[6]\,
      I1 => complex_row_cnt,
      I2 => complex_sample_cnt_inc_r2,
      I3 => \row_cnt_victim_rotate.complex_row_cnt_reg[6]_0\,
      I4 => \row_cnt_victim_rotate.complex_row_cnt[7]_i_2_n_0\,
      I5 => \row_cnt_victim_rotate.complex_row_cnt[7]_i_3_n_0\,
      O => \row_cnt_victim_rotate.complex_row_cnt[6]_i_1_n_0\
    );
\row_cnt_victim_rotate.complex_row_cnt[7]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000022226AAA"
    )
        port map (
      I0 => \row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[7]\,
      I1 => complex_row_cnt,
      I2 => \row_cnt_victim_rotate.complex_row_cnt[7]_i_2_n_0\,
      I3 => \row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[6]\,
      I4 => \row_cnt_victim_rotate.complex_row_cnt[4]_i_8_n_0\,
      I5 => \row_cnt_victim_rotate.complex_row_cnt[7]_i_3_n_0\,
      O => \row_cnt_victim_rotate.complex_row_cnt[7]_i_1_n_0\
    );
\row_cnt_victim_rotate.complex_row_cnt[7]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8000000000000000"
    )
        port map (
      I0 => \row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[4]\,
      I1 => \row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[3]\,
      I2 => \row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[1]\,
      I3 => \row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[0]\,
      I4 => \row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[2]\,
      I5 => \row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[5]\,
      O => \row_cnt_victim_rotate.complex_row_cnt[7]_i_2_n_0\
    );
\row_cnt_victim_rotate.complex_row_cnt[7]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFF5D0000"
    )
        port map (
      I0 => \row_cnt_victim_rotate.complex_row_cnt[4]_i_5_n_0\,
      I1 => complex_sample_cnt_inc_r2,
      I2 => \row_cnt_victim_rotate.complex_row_cnt_reg[6]_0\,
      I3 => reset_rd_addr_r1,
      I4 => \row_cnt_victim_rotate.complex_row_cnt[4]_i_6_n_0\,
      I5 => \row_cnt_victim_rotate.complex_row_cnt[4]_i_4_n_0\,
      O => \row_cnt_victim_rotate.complex_row_cnt[7]_i_3_n_0\
    );
\row_cnt_victim_rotate.complex_row_cnt_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => complex_row_cnt,
      D => \row_cnt_victim_rotate.complex_row_cnt[0]_i_1_n_0\,
      Q => \row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[0]\,
      R => \row_cnt_victim_rotate.complex_row_cnt[4]_i_1_n_0\
    );
\row_cnt_victim_rotate.complex_row_cnt_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => complex_row_cnt,
      D => \row_cnt_victim_rotate.complex_row_cnt[1]_i_1_n_0\,
      Q => \row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[1]\,
      R => \row_cnt_victim_rotate.complex_row_cnt[4]_i_1_n_0\
    );
\row_cnt_victim_rotate.complex_row_cnt_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => complex_row_cnt,
      D => \row_cnt_victim_rotate.complex_row_cnt[2]_i_1_n_0\,
      Q => \row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[2]\,
      R => \row_cnt_victim_rotate.complex_row_cnt[4]_i_1_n_0\
    );
\row_cnt_victim_rotate.complex_row_cnt_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => complex_row_cnt,
      D => \row_cnt_victim_rotate.complex_row_cnt[3]_i_1_n_0\,
      Q => \row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[3]\,
      R => \row_cnt_victim_rotate.complex_row_cnt[4]_i_1_n_0\
    );
\row_cnt_victim_rotate.complex_row_cnt_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => complex_row_cnt,
      D => \row_cnt_victim_rotate.complex_row_cnt[4]_i_3_n_0\,
      Q => \row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[4]\,
      R => \row_cnt_victim_rotate.complex_row_cnt[4]_i_1_n_0\
    );
\row_cnt_victim_rotate.complex_row_cnt_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => '1',
      D => \row_cnt_victim_rotate.complex_row_cnt[5]_i_1_n_0\,
      Q => \row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[5]\,
      R => '0'
    );
\row_cnt_victim_rotate.complex_row_cnt_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => '1',
      D => \row_cnt_victim_rotate.complex_row_cnt[6]_i_1_n_0\,
      Q => \row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[6]\,
      R => '0'
    );
\row_cnt_victim_rotate.complex_row_cnt_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => '1',
      D => \row_cnt_victim_rotate.complex_row_cnt[7]_i_1_n_0\,
      Q => \row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[7]\,
      R => '0'
    );
\samples_cnt_r[11]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => complex_sample_cnt_inc,
      I1 => \samples_cnt_r_reg[11]\,
      O => E(0)
    );
\stg1_wr_rd_cnt[0]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"BA"
    )
        port map (
      I0 => \stg1_wr_rd_cnt[6]_i_2_n_0\,
      I1 => \stg1_wr_rd_cnt_reg_n_0_[0]\,
      I2 => \stg1_wr_rd_cnt[8]_i_3_n_0\,
      O => \stg1_wr_rd_cnt[0]_i_1_n_0\
    );
\stg1_wr_rd_cnt[1]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0D00000D0D0D0D0D"
    )
        port map (
      I0 => \^stg1_wr_done\,
      I1 => prbs_rdlvl_start_reg_2,
      I2 => write_calib_reg_0,
      I3 => \stg1_wr_rd_cnt_reg_n_0_[1]\,
      I4 => \stg1_wr_rd_cnt_reg_n_0_[0]\,
      I5 => \stg1_wr_rd_cnt[4]_i_3_n_0\,
      O => \stg1_wr_rd_cnt[1]_i_1_n_0\
    );
\stg1_wr_rd_cnt[1]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"1000000000000000"
    )
        port map (
      I0 => \init_state_r[3]_i_6_n_0\,
      I1 => \init_state_r_reg_n_0_[4]\,
      I2 => \init_state_r_reg_n_0_[1]\,
      I3 => \init_state_r_reg_n_0_[3]\,
      I4 => \^q\(0),
      I5 => \init_state_r_reg_n_0_[2]\,
      O => \^stg1_wr_done\
    );
\stg1_wr_rd_cnt[2]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FD57"
    )
        port map (
      I0 => \stg1_wr_rd_cnt[8]_i_3_n_0\,
      I1 => \stg1_wr_rd_cnt_reg_n_0_[1]\,
      I2 => \stg1_wr_rd_cnt_reg_n_0_[0]\,
      I3 => \stg1_wr_rd_cnt_reg_n_0_[2]\,
      O => \stg1_wr_rd_cnt[2]_i_1_n_0\
    );
\stg1_wr_rd_cnt[3]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"008AAA8AAA8A008A"
    )
        port map (
      I0 => \stg1_wr_rd_cnt_reg[3]_0\,
      I1 => complex_oclkdelay_calib_done_r1_reg_0,
      I2 => \stg1_wr_rd_cnt[3]_i_2_n_0\,
      I3 => \stg1_wr_rd_cnt[4]_i_3_n_0\,
      I4 => \stg1_wr_rd_cnt[5]_i_2_n_0\,
      I5 => \stg1_wr_rd_cnt_reg_n_0_[3]\,
      O => \stg1_wr_rd_cnt[3]_i_1_n_0\
    );
\stg1_wr_rd_cnt[3]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00002F00"
    )
        port map (
      I0 => complex_row0_rd_done,
      I1 => complex_row1_rd_done,
      I2 => complex_row1_wr_done,
      I3 => complex_row0_wr_done,
      I4 => wr_victim_inc,
      O => \stg1_wr_rd_cnt[3]_i_2_n_0\
    );
\stg1_wr_rd_cnt[4]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"8288AAAA"
    )
        port map (
      I0 => \stg1_wr_rd_cnt_reg[3]_0\,
      I1 => \stg1_wr_rd_cnt_reg_n_0_[4]\,
      I2 => \stg1_wr_rd_cnt_reg_n_0_[3]\,
      I3 => \stg1_wr_rd_cnt[5]_i_2_n_0\,
      I4 => \stg1_wr_rd_cnt[4]_i_3_n_0\,
      O => \stg1_wr_rd_cnt[4]_i_1_n_0\
    );
\stg1_wr_rd_cnt[4]_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00020202"
    )
        port map (
      I0 => complex_sample_cnt_inc_i_2_n_0,
      I1 => rdlvl_last_byte_done,
      I2 => complex_ocal_reset_rd_addr_i_3_n_0,
      I3 => prech_req_posedge_r_reg_1,
      I4 => \stg1_wr_rd_cnt[4]_i_4_n_0\,
      O => \stg1_wr_rd_cnt[4]_i_3_n_0\
    );
\stg1_wr_rd_cnt[4]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000000004"
    )
        port map (
      I0 => \init_state_r_reg_n_0_[1]\,
      I1 => \^q\(0),
      I2 => \init_state_r_reg_n_0_[4]\,
      I3 => \init_state_r_reg_n_0_[5]\,
      I4 => init_state_r(6),
      I5 => rdlvl_stg1_start_int_i_2_n_0,
      O => \stg1_wr_rd_cnt[4]_i_4_n_0\
    );
\stg1_wr_rd_cnt[5]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"EEEBEEEEAAAAAAAA"
    )
        port map (
      I0 => \stg1_wr_rd_cnt[6]_i_2_n_0\,
      I1 => \stg1_wr_rd_cnt_reg_n_0_[5]\,
      I2 => \stg1_wr_rd_cnt_reg_n_0_[3]\,
      I3 => \stg1_wr_rd_cnt_reg_n_0_[4]\,
      I4 => \stg1_wr_rd_cnt[5]_i_2_n_0\,
      I5 => \stg1_wr_rd_cnt[8]_i_3_n_0\,
      O => \stg1_wr_rd_cnt[5]_i_1_n_0\
    );
\stg1_wr_rd_cnt[5]_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"01"
    )
        port map (
      I0 => \stg1_wr_rd_cnt_reg_n_0_[2]\,
      I1 => \stg1_wr_rd_cnt_reg_n_0_[0]\,
      I2 => \stg1_wr_rd_cnt_reg_n_0_[1]\,
      O => \stg1_wr_rd_cnt[5]_i_2_n_0\
    );
\stg1_wr_rd_cnt[6]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FF60"
    )
        port map (
      I0 => \stg1_wr_rd_cnt_reg_n_0_[6]\,
      I1 => \stg1_wr_rd_cnt[8]_i_6_n_0\,
      I2 => \stg1_wr_rd_cnt[8]_i_3_n_0\,
      I3 => \stg1_wr_rd_cnt[6]_i_2_n_0\,
      O => \stg1_wr_rd_cnt[6]_i_1_n_0\
    );
\stg1_wr_rd_cnt[6]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00001011"
    )
        port map (
      I0 => \stg1_wr_rd_cnt[3]_i_2_n_0\,
      I1 => write_calib_reg_0,
      I2 => prbs_rdlvl_start_reg_2,
      I3 => \^stg1_wr_done\,
      I4 => \stg1_wr_rd_cnt[4]_i_3_n_0\,
      O => \stg1_wr_rd_cnt[6]_i_2_n_0\
    );
\stg1_wr_rd_cnt[7]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"A208"
    )
        port map (
      I0 => \stg1_wr_rd_cnt[8]_i_3_n_0\,
      I1 => \stg1_wr_rd_cnt[8]_i_6_n_0\,
      I2 => \stg1_wr_rd_cnt_reg_n_0_[6]\,
      I3 => \stg1_wr_rd_cnt_reg_n_0_[7]\,
      O => \stg1_wr_rd_cnt[7]_i_1_n_0\
    );
\stg1_wr_rd_cnt[8]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFD5"
    )
        port map (
      I0 => \stg1_wr_rd_cnt[8]_i_3_n_0\,
      I1 => \stg1_wr_rd_cnt[8]_i_4_n_0\,
      I2 => prbs_rdlvl_start_reg_2,
      I3 => \stg1_wr_rd_cnt[8]_i_5_n_0\,
      O => \stg1_wr_rd_cnt[8]_i_1_n_0\
    );
\stg1_wr_rd_cnt[8]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"A8AA0200"
    )
        port map (
      I0 => \stg1_wr_rd_cnt[8]_i_3_n_0\,
      I1 => \stg1_wr_rd_cnt_reg_n_0_[7]\,
      I2 => \stg1_wr_rd_cnt_reg_n_0_[6]\,
      I3 => \stg1_wr_rd_cnt[8]_i_6_n_0\,
      I4 => \stg1_wr_rd_cnt_reg_n_0_[8]\,
      O => \stg1_wr_rd_cnt[8]_i_2_n_0\
    );
\stg1_wr_rd_cnt[8]_i_3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"00A2"
    )
        port map (
      I0 => \stg1_wr_rd_cnt[4]_i_3_n_0\,
      I1 => \^stg1_wr_done\,
      I2 => prbs_rdlvl_start_reg_2,
      I3 => write_calib_reg_0,
      O => \stg1_wr_rd_cnt[8]_i_3_n_0\
    );
\stg1_wr_rd_cnt[8]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000080000000000"
    )
        port map (
      I0 => \wrcal_reads[7]_i_5_n_0\,
      I1 => \init_state_r_reg_n_0_[5]\,
      I2 => init_state_r(6),
      I3 => \init_state_r_reg_n_0_[4]\,
      I4 => \init_state_r_reg_n_0_[2]\,
      I5 => \init_state_r_reg_n_0_[3]\,
      O => \stg1_wr_rd_cnt[8]_i_4_n_0\
    );
\stg1_wr_rd_cnt[8]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0100000000000000"
    )
        port map (
      I0 => init_state_r(6),
      I1 => \init_state_r_reg_n_0_[5]\,
      I2 => \init_state_r_reg_n_0_[4]\,
      I3 => \init_state_r_reg_n_0_[3]\,
      I4 => \init_state_r_reg_n_0_[2]\,
      I5 => detect_pi_found_dqs_i_2_n_0,
      O => \stg1_wr_rd_cnt[8]_i_5_n_0\
    );
\stg1_wr_rd_cnt[8]_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000000001"
    )
        port map (
      I0 => \stg1_wr_rd_cnt_reg_n_0_[4]\,
      I1 => \stg1_wr_rd_cnt_reg_n_0_[5]\,
      I2 => \stg1_wr_rd_cnt_reg_n_0_[3]\,
      I3 => \stg1_wr_rd_cnt_reg_n_0_[2]\,
      I4 => \stg1_wr_rd_cnt_reg_n_0_[0]\,
      I5 => \stg1_wr_rd_cnt_reg_n_0_[1]\,
      O => \stg1_wr_rd_cnt[8]_i_6_n_0\
    );
\stg1_wr_rd_cnt_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => \stg1_wr_rd_cnt[8]_i_1_n_0\,
      D => \stg1_wr_rd_cnt[0]_i_1_n_0\,
      Q => \stg1_wr_rd_cnt_reg_n_0_[0]\,
      R => '0'
    );
\stg1_wr_rd_cnt_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => \stg1_wr_rd_cnt[8]_i_1_n_0\,
      D => \stg1_wr_rd_cnt[1]_i_1_n_0\,
      Q => \stg1_wr_rd_cnt_reg_n_0_[1]\,
      R => '0'
    );
\stg1_wr_rd_cnt_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => \stg1_wr_rd_cnt[8]_i_1_n_0\,
      D => \stg1_wr_rd_cnt[2]_i_1_n_0\,
      Q => \stg1_wr_rd_cnt_reg_n_0_[2]\,
      R => '0'
    );
\stg1_wr_rd_cnt_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => \stg1_wr_rd_cnt[8]_i_1_n_0\,
      D => \stg1_wr_rd_cnt[3]_i_1_n_0\,
      Q => \stg1_wr_rd_cnt_reg_n_0_[3]\,
      R => '0'
    );
\stg1_wr_rd_cnt_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => \stg1_wr_rd_cnt[8]_i_1_n_0\,
      D => \stg1_wr_rd_cnt[4]_i_1_n_0\,
      Q => \stg1_wr_rd_cnt_reg_n_0_[4]\,
      R => '0'
    );
\stg1_wr_rd_cnt_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => \stg1_wr_rd_cnt[8]_i_1_n_0\,
      D => \stg1_wr_rd_cnt[5]_i_1_n_0\,
      Q => \stg1_wr_rd_cnt_reg_n_0_[5]\,
      R => '0'
    );
\stg1_wr_rd_cnt_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => \stg1_wr_rd_cnt[8]_i_1_n_0\,
      D => \stg1_wr_rd_cnt[6]_i_1_n_0\,
      Q => \stg1_wr_rd_cnt_reg_n_0_[6]\,
      R => '0'
    );
\stg1_wr_rd_cnt_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => \stg1_wr_rd_cnt[8]_i_1_n_0\,
      D => \stg1_wr_rd_cnt[7]_i_1_n_0\,
      Q => \stg1_wr_rd_cnt_reg_n_0_[7]\,
      R => '0'
    );
\stg1_wr_rd_cnt_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => \stg1_wr_rd_cnt[8]_i_1_n_0\,
      D => \stg1_wr_rd_cnt[8]_i_2_n_0\,
      Q => \stg1_wr_rd_cnt_reg_n_0_[8]\,
      R => '0'
    );
\victim_sel[0]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \victim_sel[0]_i_2_n_0\,
      I1 => \victim_sel[2]_i_3_n_0\,
      I2 => \victim_sel_reg_n_0_[0]\,
      O => \victim_sel[0]_i_1_n_0\
    );
\victim_sel[0]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"3A3F0A0F3A300A00"
    )
        port map (
      I0 => \row_cnt_victim_rotate.complex_row_cnt_reg[1]_0\,
      I1 => complex_wr_done,
      I2 => complex_oclkdelay_calib_done_r1_reg_0,
      I3 => \^one_rank.stg1_wr_done_reg_0\,
      I4 => wr_victim_sel_ocal(0),
      I5 => wr_victim_sel(0),
      O => \victim_sel[0]_i_2_n_0\
    );
\victim_sel[1]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \victim_sel[1]_i_2_n_0\,
      I1 => \victim_sel[2]_i_3_n_0\,
      I2 => \victim_sel_reg_n_0_[1]\,
      O => \victim_sel[1]_i_1_n_0\
    );
\victim_sel[1]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"3A3F0A0F3A300A00"
    )
        port map (
      I0 => \row_cnt_victim_rotate.complex_row_cnt_reg[2]_0\,
      I1 => complex_wr_done,
      I2 => complex_oclkdelay_calib_done_r1_reg_0,
      I3 => \^one_rank.stg1_wr_done_reg_0\,
      I4 => wr_victim_sel_ocal(1),
      I5 => wr_victim_sel(1),
      O => \victim_sel[1]_i_2_n_0\
    );
\victim_sel[2]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \victim_sel[2]_i_2_n_0\,
      I1 => \victim_sel[2]_i_3_n_0\,
      I2 => \victim_sel_reg_n_0_[2]\,
      O => \victim_sel[2]_i_1_n_0\
    );
\victim_sel[2]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"3A3F0A0F3A300A00"
    )
        port map (
      I0 => \row_cnt_victim_rotate.complex_row_cnt_reg[3]_0\,
      I1 => complex_wr_done,
      I2 => complex_oclkdelay_calib_done_r1_reg_0,
      I3 => \^one_rank.stg1_wr_done_reg_0\,
      I4 => wr_victim_sel_ocal(2),
      I5 => wr_victim_sel(2),
      O => \victim_sel[2]_i_2_n_0\
    );
\victim_sel[2]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFBABF"
    )
        port map (
      I0 => \victim_sel[2]_i_4_n_0\,
      I1 => complex_wr_done,
      I2 => complex_oclkdelay_calib_done_r1_reg_0,
      I3 => \^one_rank.stg1_wr_done_reg_0\,
      I4 => reset_rd_addr,
      I5 => \^complex_ocal_reset_rd_addr\,
      O => \victim_sel[2]_i_3_n_0\
    );
\victim_sel[2]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000200000000000"
    )
        port map (
      I0 => detect_pi_found_dqs_i_2_n_0,
      I1 => \init_state_r_reg_n_0_[3]\,
      I2 => \init_state_r_reg_n_0_[2]\,
      I3 => \init_state_r_reg_n_0_[5]\,
      I4 => init_state_r(6),
      I5 => \init_state_r_reg_n_0_[4]\,
      O => \victim_sel[2]_i_4_n_0\
    );
\victim_sel_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => '1',
      D => \victim_sel[0]_i_1_n_0\,
      Q => \victim_sel_reg_n_0_[0]\,
      R => \victim_sel_reg[0]_0\(0)
    );
\victim_sel_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => '1',
      D => \victim_sel[1]_i_1_n_0\,
      Q => \victim_sel_reg_n_0_[1]\,
      R => \victim_sel_reg[0]_0\(0)
    );
\victim_sel_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => '1',
      D => \victim_sel[2]_i_1_n_0\,
      Q => \victim_sel_reg_n_0_[2]\,
      R => \victim_sel_reg[0]_0\(0)
    );
\victim_sel_rotate.sel[56]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"01"
    )
        port map (
      I0 => \victim_sel_reg_n_0_[2]\,
      I1 => \victim_sel_reg_n_0_[0]\,
      I2 => \victim_sel_reg_n_0_[1]\,
      O => D(0)
    );
\victim_sel_rotate.sel[57]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"02"
    )
        port map (
      I0 => \victim_sel_reg_n_0_[0]\,
      I1 => \victim_sel_reg_n_0_[2]\,
      I2 => \victim_sel_reg_n_0_[1]\,
      O => D(1)
    );
\victim_sel_rotate.sel[58]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"02"
    )
        port map (
      I0 => \victim_sel_reg_n_0_[1]\,
      I1 => \victim_sel_reg_n_0_[2]\,
      I2 => \victim_sel_reg_n_0_[0]\,
      O => D(2)
    );
\victim_sel_rotate.sel[59]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \victim_sel_reg_n_0_[2]\,
      I1 => \victim_sel_reg_n_0_[0]\,
      I2 => \victim_sel_reg_n_0_[1]\,
      O => D(3)
    );
\victim_sel_rotate.sel[60]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"02"
    )
        port map (
      I0 => \victim_sel_reg_n_0_[2]\,
      I1 => \victim_sel_reg_n_0_[0]\,
      I2 => \victim_sel_reg_n_0_[1]\,
      O => D(4)
    );
\victim_sel_rotate.sel[61]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"08"
    )
        port map (
      I0 => \victim_sel_reg_n_0_[0]\,
      I1 => \victim_sel_reg_n_0_[2]\,
      I2 => \victim_sel_reg_n_0_[1]\,
      O => D(5)
    );
\victim_sel_rotate.sel[62]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \victim_sel_reg_n_0_[0]\,
      I1 => \victim_sel_reg_n_0_[2]\,
      I2 => \victim_sel_reg_n_0_[1]\,
      O => D(6)
    );
\victim_sel_rotate.sel[63]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"80"
    )
        port map (
      I0 => \victim_sel_reg_n_0_[1]\,
      I1 => \victim_sel_reg_n_0_[0]\,
      I2 => \victim_sel_reg_n_0_[2]\,
      O => D(7)
    );
wl_sm_start_reg: unisim.vcomponents.FDRE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => '1',
      D => wr_level_dqs_asrt_r1,
      Q => \^wl_sm_start\,
      R => \en_cnt_div4.enable_wrlvl_cnt_reg[2]_0\
    );
\wr_done_victim_rotate.complex_row0_wr_done_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"00AE"
    )
        port map (
      I0 => complex_row0_wr_done,
      I1 => rdlvl_stg1_done_r1,
      I2 => wr_victim_inc_i_2_n_0,
      I3 => complex_row0_wr_done0,
      O => \wr_done_victim_rotate.complex_row0_wr_done_i_1_n_0\
    );
\wr_done_victim_rotate.complex_row0_wr_done_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFF0011F011"
    )
        port map (
      I0 => \row_cnt_victim_rotate.complex_row_cnt[5]_i_2_n_0\,
      I1 => \wr_victim_sel[2]_i_3_n_0\,
      I2 => wr_victim_inc,
      I3 => complex_oclkdelay_calib_done_r1_reg_0,
      I4 => \complex_row_cnt_ocal[3]_i_4_n_0\,
      I5 => \wr_done_victim_rotate.complex_row0_wr_done_i_3_n_0\,
      O => complex_row0_wr_done0
    );
\wr_done_victim_rotate.complex_row0_wr_done_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"FE"
    )
        port map (
      I0 => complex_byte_rd_done,
      I1 => \^prbs_rdlvl_done_pulse_reg_0\,
      I2 => write_calib_reg_0,
      O => \wr_done_victim_rotate.complex_row0_wr_done_i_3_n_0\
    );
\wr_done_victim_rotate.complex_row0_wr_done_reg\: unisim.vcomponents.FDRE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => '1',
      D => \wr_done_victim_rotate.complex_row0_wr_done_i_1_n_0\,
      Q => complex_row0_wr_done,
      R => '0'
    );
\wr_done_victim_rotate.complex_row1_wr_done_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"00AE"
    )
        port map (
      I0 => complex_row1_wr_done,
      I1 => complex_row0_wr_done,
      I2 => wr_victim_inc_i_2_n_0,
      I3 => complex_row0_wr_done0,
      O => \wr_done_victim_rotate.complex_row1_wr_done_i_1_n_0\
    );
\wr_done_victim_rotate.complex_row1_wr_done_reg\: unisim.vcomponents.FDRE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => '1',
      D => \wr_done_victim_rotate.complex_row1_wr_done_i_1_n_0\,
      Q => complex_row1_wr_done,
      R => '0'
    );
wr_level_dqs_asrt_i_1: unisim.vcomponents.LUT4
    generic map(
      INIT => X"00A8"
    )
        port map (
      I0 => \en_cnt_div4.wrlvl_odt_i_2_n_0\,
      I1 => wrlvl_active_r1,
      I2 => wr_level_dqs_asrt,
      I3 => write_calib_reg_0,
      O => wr_level_dqs_asrt_i_1_n_0
    );
wr_level_dqs_asrt_r1_reg: unisim.vcomponents.FDRE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => '1',
      D => wr_level_dqs_asrt,
      Q => wr_level_dqs_asrt_r1,
      R => '0'
    );
wr_level_dqs_asrt_reg: unisim.vcomponents.FDRE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => '1',
      D => wr_level_dqs_asrt_i_1_n_0,
      Q => wr_level_dqs_asrt,
      R => '0'
    );
wr_lvl_start_i_1: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000EA00"
    )
        port map (
      I0 => \^wr_lvl_start_reg_0\,
      I1 => dqs_asrt_cnt(0),
      I2 => dqs_asrt_cnt(1),
      I3 => wrlvl_active,
      I4 => write_calib_reg_0,
      O => wr_lvl_start_i_1_n_0
    );
wr_lvl_start_reg: unisim.vcomponents.FDRE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => '1',
      D => wr_lvl_start_i_1_n_0,
      Q => \^wr_lvl_start_reg_0\,
      R => '0'
    );
wr_ptr0_i_1: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => phy_ctl_wr_i1_reg,
      I1 => calib_cmd_wren,
      O => phy_cmd_wr_en
    );
\wr_ptr[3]_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => mc_wrdata_en,
      I1 => phy_ctl_wr_i1_reg,
      I2 => calib_wrdata_en,
      O => phy_data_wr_en
    );
wr_victim_inc_i_1: unisim.vcomponents.LUT3
    generic map(
      INIT => X"04"
    )
        port map (
      I0 => wr_victim_inc_i_2_n_0,
      I1 => complex_row0_wr_done,
      I2 => \^one_rank.stg1_wr_done_reg_0\,
      O => wr_victim_inc0
    );
wr_victim_inc_i_2: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFFEF"
    )
        port map (
      I0 => wr_victim_inc_i_3_n_0,
      I1 => \stg1_wr_rd_cnt_reg_n_0_[0]\,
      I2 => \stg1_wr_rd_cnt_reg_n_0_[1]\,
      I3 => \stg1_wr_rd_cnt_reg_n_0_[3]\,
      I4 => \stg1_wr_rd_cnt_reg_n_0_[4]\,
      I5 => \stg1_wr_rd_cnt_reg_n_0_[2]\,
      O => wr_victim_inc_i_2_n_0
    );
wr_victim_inc_i_3: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFFE"
    )
        port map (
      I0 => \stg1_wr_rd_cnt_reg_n_0_[5]\,
      I1 => \stg1_wr_rd_cnt_reg_n_0_[7]\,
      I2 => \stg1_wr_rd_cnt_reg_n_0_[8]\,
      I3 => \stg1_wr_rd_cnt_reg_n_0_[6]\,
      O => wr_victim_inc_i_3_n_0
    );
wr_victim_inc_reg: unisim.vcomponents.FDRE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => '1',
      D => wr_victim_inc0,
      Q => wr_victim_inc,
      R => \en_cnt_div4.enable_wrlvl_cnt_reg[2]_0\
    );
\wr_victim_sel[0]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"006A"
    )
        port map (
      I0 => wr_victim_sel(0),
      I1 => wr_victim_inc,
      I2 => rdlvl_stg1_done_r1,
      I3 => p_81_in,
      O => \wr_victim_sel[0]_i_1_n_0\
    );
\wr_victim_sel[1]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00006AAA"
    )
        port map (
      I0 => wr_victim_sel(1),
      I1 => wr_victim_inc,
      I2 => rdlvl_stg1_done_r1,
      I3 => wr_victim_sel(0),
      I4 => p_81_in,
      O => \wr_victim_sel[1]_i_1_n_0\
    );
\wr_victim_sel[2]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"000000006AAAAAAA"
    )
        port map (
      I0 => wr_victim_sel(2),
      I1 => wr_victim_inc,
      I2 => rdlvl_stg1_done_r1,
      I3 => wr_victim_sel(1),
      I4 => wr_victim_sel(0),
      I5 => p_81_in,
      O => \wr_victim_sel[2]_i_1_n_0\
    );
\wr_victim_sel[2]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"BAAAAAAAAAAAAAAA"
    )
        port map (
      I0 => write_calib_reg_0,
      I1 => \wr_victim_sel[2]_i_3_n_0\,
      I2 => \row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[3]\,
      I3 => \row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[1]\,
      I4 => \row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[0]\,
      I5 => \row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[2]\,
      O => p_81_in
    );
\wr_victim_sel[2]_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFEFFFF"
    )
        port map (
      I0 => \row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[6]\,
      I1 => \row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[5]\,
      I2 => \row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[4]\,
      I3 => \row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[7]\,
      I4 => wr_victim_inc,
      O => \wr_victim_sel[2]_i_3_n_0\
    );
\wr_victim_sel_ocal[0]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"006A"
    )
        port map (
      I0 => wr_victim_sel_ocal(0),
      I1 => wr_victim_inc,
      I2 => complex_oclkdelay_calib_done_r1_reg_0,
      I3 => \wr_victim_sel_ocal[2]_i_2_n_0\,
      O => \wr_victim_sel_ocal[0]_i_1_n_0\
    );
\wr_victim_sel_ocal[1]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00006AAA"
    )
        port map (
      I0 => wr_victim_sel_ocal(1),
      I1 => wr_victim_inc,
      I2 => complex_oclkdelay_calib_done_r1_reg_0,
      I3 => wr_victim_sel_ocal(0),
      I4 => \wr_victim_sel_ocal[2]_i_2_n_0\,
      O => \wr_victim_sel_ocal[1]_i_1_n_0\
    );
\wr_victim_sel_ocal[2]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"000000006AAAAAAA"
    )
        port map (
      I0 => wr_victim_sel_ocal(2),
      I1 => wr_victim_inc,
      I2 => complex_oclkdelay_calib_done_r1_reg_0,
      I3 => wr_victim_sel_ocal(1),
      I4 => wr_victim_sel_ocal(0),
      I5 => \wr_victim_sel_ocal[2]_i_2_n_0\,
      O => \wr_victim_sel_ocal[2]_i_1_n_0\
    );
\wr_victim_sel_ocal[2]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"EAAAAAAAAAAAAAAA"
    )
        port map (
      I0 => write_calib_reg_0,
      I1 => wr_victim_inc,
      I2 => complex_row_cnt_ocal_reg(3),
      I3 => complex_row_cnt_ocal_reg(1),
      I4 => complex_row_cnt_ocal_reg(0),
      I5 => complex_row_cnt_ocal_reg(2),
      O => \wr_victim_sel_ocal[2]_i_2_n_0\
    );
\wr_victim_sel_ocal_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => '1',
      D => \wr_victim_sel_ocal[0]_i_1_n_0\,
      Q => wr_victim_sel_ocal(0),
      R => '0'
    );
\wr_victim_sel_ocal_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => '1',
      D => \wr_victim_sel_ocal[1]_i_1_n_0\,
      Q => wr_victim_sel_ocal(1),
      R => '0'
    );
\wr_victim_sel_ocal_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => '1',
      D => \wr_victim_sel_ocal[2]_i_1_n_0\,
      Q => wr_victim_sel_ocal(2),
      R => '0'
    );
\wr_victim_sel_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => '1',
      D => \wr_victim_sel[0]_i_1_n_0\,
      Q => wr_victim_sel(0),
      R => '0'
    );
\wr_victim_sel_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => '1',
      D => \wr_victim_sel[1]_i_1_n_0\,
      Q => wr_victim_sel(1),
      R => '0'
    );
\wr_victim_sel_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => '1',
      D => \wr_victim_sel[2]_i_1_n_0\,
      Q => wr_victim_sel(2),
      R => '0'
    );
wrcal_final_chk_i_1: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFF4000"
    )
        port map (
      I0 => wrcal_final_chk_i_2_n_0,
      I1 => \init_state_r[4]_i_1_n_0\,
      I2 => \init_state_r[0]_i_1_n_0\,
      I3 => \init_state_r[3]_i_1_n_0\,
      I4 => wrcal_final_chk,
      O => wrcal_final_chk_i_1_n_0
    );
wrcal_final_chk_i_2: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFDFFF"
    )
        port map (
      I0 => ddr3_lm_done_r_reg_0,
      I1 => \init_state_r[6]_i_1_n_0\,
      I2 => \init_state_r[1]_i_1_n_0\,
      I3 => \init_state_r[2]_i_1_n_0\,
      I4 => \init_state_r[5]_i_1_n_0\,
      O => wrcal_final_chk_i_2_n_0
    );
wrcal_final_chk_reg: unisim.vcomponents.FDRE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => '1',
      D => wrcal_final_chk_i_1_n_0,
      Q => wrcal_final_chk,
      R => \victim_sel_reg[0]_0\(0)
    );
wrcal_rd_wait_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000000100"
    )
        port map (
      I0 => \^q\(0),
      I1 => \init_state_r_reg_n_0_[1]\,
      I2 => \init_state_r_reg_n_0_[4]\,
      I3 => \init_state_r_reg_n_0_[5]\,
      I4 => init_state_r(6),
      I5 => \wrcal_reads[7]_i_4_n_0\,
      O => wrcal_rd_wait_i_1_n_0
    );
wrcal_rd_wait_reg: unisim.vcomponents.FDRE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => '1',
      D => wrcal_rd_wait_i_1_n_0,
      Q => wrcal_rd_wait,
      R => \victim_sel_reg[0]_0\(0)
    );
\wrcal_reads[0]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => wrcal_reads,
      I1 => \wrcal_reads_reg_n_0_[0]\,
      O => \wrcal_reads[0]_i_1_n_0\
    );
\wrcal_reads[1]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"F9"
    )
        port map (
      I0 => \wrcal_reads_reg_n_0_[0]\,
      I1 => \wrcal_reads_reg_n_0_[1]\,
      I2 => wrcal_reads,
      O => \wrcal_reads[1]_i_1_n_0\
    );
\wrcal_reads[2]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFE1"
    )
        port map (
      I0 => \wrcal_reads_reg_n_0_[1]\,
      I1 => \wrcal_reads_reg_n_0_[0]\,
      I2 => \wrcal_reads_reg_n_0_[2]\,
      I3 => wrcal_reads,
      O => \wrcal_reads[2]_i_1_n_0\
    );
\wrcal_reads[3]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFFE01"
    )
        port map (
      I0 => \wrcal_reads_reg_n_0_[0]\,
      I1 => \wrcal_reads_reg_n_0_[1]\,
      I2 => \wrcal_reads_reg_n_0_[2]\,
      I3 => \wrcal_reads_reg_n_0_[3]\,
      I4 => wrcal_reads,
      O => \wrcal_reads[3]_i_1_n_0\
    );
\wrcal_reads[4]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFE0001"
    )
        port map (
      I0 => \wrcal_reads_reg_n_0_[2]\,
      I1 => \wrcal_reads_reg_n_0_[1]\,
      I2 => \wrcal_reads_reg_n_0_[0]\,
      I3 => \wrcal_reads_reg_n_0_[3]\,
      I4 => \wrcal_reads_reg_n_0_[4]\,
      I5 => wrcal_reads,
      O => \wrcal_reads[4]_i_1_n_0\
    );
\wrcal_reads[5]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"F6"
    )
        port map (
      I0 => \wrcal_reads[7]_i_8_n_0\,
      I1 => \wrcal_reads_reg_n_0_[5]\,
      I2 => wrcal_reads,
      O => \wrcal_reads[5]_i_1_n_0\
    );
\wrcal_reads[6]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFD2"
    )
        port map (
      I0 => \wrcal_reads[7]_i_8_n_0\,
      I1 => \wrcal_reads_reg_n_0_[5]\,
      I2 => \wrcal_reads_reg_n_0_[6]\,
      I3 => wrcal_reads,
      O => \wrcal_reads[6]_i_1_n_0\
    );
\wrcal_reads[7]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAABAAAAAAAAAA"
    )
        port map (
      I0 => write_calib_reg_0,
      I1 => \wrcal_reads[7]_i_4_n_0\,
      I2 => init_state_r(6),
      I3 => \init_state_r_reg_n_0_[5]\,
      I4 => \init_state_r_reg_n_0_[4]\,
      I5 => \wrcal_reads[7]_i_5_n_0\,
      O => wrcal_reads05_out
    );
\wrcal_reads[7]_i_10\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => \wrcal_reads_reg_n_0_[6]\,
      I1 => \wrcal_reads_reg_n_0_[5]\,
      O => \wrcal_reads[7]_i_10_n_0\
    );
\wrcal_reads[7]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"EEEEEEEEEEEEEFEE"
    )
        port map (
      I0 => \wrcal_reads_reg_n_0_[0]\,
      I1 => \wrcal_reads[7]_i_6_n_0\,
      I2 => \wrcal_reads[7]_i_4_n_0\,
      I3 => \^q\(0),
      I4 => \init_state_r_reg_n_0_[1]\,
      I5 => \wrcal_reads[7]_i_7_n_0\,
      O => \wrcal_reads[7]_i_2_n_0\
    );
\wrcal_reads[7]_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFFD02"
    )
        port map (
      I0 => \wrcal_reads[7]_i_8_n_0\,
      I1 => \wrcal_reads_reg_n_0_[5]\,
      I2 => \wrcal_reads_reg_n_0_[6]\,
      I3 => \wrcal_reads_reg_n_0_[7]\,
      I4 => wrcal_reads,
      O => \wrcal_reads[7]_i_3_n_0\
    );
\wrcal_reads[7]_i_4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => \init_state_r_reg_n_0_[3]\,
      I1 => \init_state_r_reg_n_0_[2]\,
      O => \wrcal_reads[7]_i_4_n_0\
    );
\wrcal_reads[7]_i_5\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \init_state_r_reg_n_0_[1]\,
      I1 => \^q\(0),
      O => \wrcal_reads[7]_i_5_n_0\
    );
\wrcal_reads[7]_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFFFE"
    )
        port map (
      I0 => \wrcal_reads_reg_n_0_[7]\,
      I1 => \wrcal_reads_reg_n_0_[2]\,
      I2 => \wrcal_reads_reg_n_0_[4]\,
      I3 => \wrcal_reads_reg_n_0_[3]\,
      I4 => \wrcal_reads_reg_n_0_[1]\,
      I5 => \wrcal_reads[7]_i_10_n_0\,
      O => \wrcal_reads[7]_i_6_n_0\
    );
\wrcal_reads[7]_i_7\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"FB"
    )
        port map (
      I0 => \init_state_r_reg_n_0_[4]\,
      I1 => \init_state_r_reg_n_0_[5]\,
      I2 => init_state_r(6),
      O => \wrcal_reads[7]_i_7_n_0\
    );
\wrcal_reads[7]_i_8\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000001"
    )
        port map (
      I0 => \wrcal_reads_reg_n_0_[3]\,
      I1 => \wrcal_reads_reg_n_0_[0]\,
      I2 => \wrcal_reads_reg_n_0_[1]\,
      I3 => \wrcal_reads_reg_n_0_[2]\,
      I4 => \wrcal_reads_reg_n_0_[4]\,
      O => \wrcal_reads[7]_i_8_n_0\
    );
\wrcal_reads[7]_i_9\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000000010"
    )
        port map (
      I0 => \wrcal_reads[7]_i_7_n_0\,
      I1 => \init_state_r_reg_n_0_[1]\,
      I2 => \^q\(0),
      I3 => \wrcal_reads[7]_i_4_n_0\,
      I4 => \wrcal_reads[7]_i_6_n_0\,
      I5 => \wrcal_reads_reg_n_0_[0]\,
      O => wrcal_reads
    );
\wrcal_reads_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => \wrcal_reads[7]_i_2_n_0\,
      D => \wrcal_reads[0]_i_1_n_0\,
      Q => \wrcal_reads_reg_n_0_[0]\,
      R => wrcal_reads05_out
    );
\wrcal_reads_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => \wrcal_reads[7]_i_2_n_0\,
      D => \wrcal_reads[1]_i_1_n_0\,
      Q => \wrcal_reads_reg_n_0_[1]\,
      R => wrcal_reads05_out
    );
\wrcal_reads_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => \wrcal_reads[7]_i_2_n_0\,
      D => \wrcal_reads[2]_i_1_n_0\,
      Q => \wrcal_reads_reg_n_0_[2]\,
      R => wrcal_reads05_out
    );
\wrcal_reads_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => \wrcal_reads[7]_i_2_n_0\,
      D => \wrcal_reads[3]_i_1_n_0\,
      Q => \wrcal_reads_reg_n_0_[3]\,
      R => wrcal_reads05_out
    );
\wrcal_reads_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => \wrcal_reads[7]_i_2_n_0\,
      D => \wrcal_reads[4]_i_1_n_0\,
      Q => \wrcal_reads_reg_n_0_[4]\,
      R => wrcal_reads05_out
    );
\wrcal_reads_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => \wrcal_reads[7]_i_2_n_0\,
      D => \wrcal_reads[5]_i_1_n_0\,
      Q => \wrcal_reads_reg_n_0_[5]\,
      R => wrcal_reads05_out
    );
\wrcal_reads_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => \wrcal_reads[7]_i_2_n_0\,
      D => \wrcal_reads[6]_i_1_n_0\,
      Q => \wrcal_reads_reg_n_0_[6]\,
      R => wrcal_reads05_out
    );
\wrcal_reads_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => \wrcal_reads[7]_i_2_n_0\,
      D => \wrcal_reads[7]_i_3_n_0\,
      Q => \wrcal_reads_reg_n_0_[7]\,
      R => wrcal_reads05_out
    );
wrcal_resume_r_reg: unisim.vcomponents.FDRE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => '1',
      D => wrcal_resume_w,
      Q => wrcal_resume_r,
      R => '0'
    );
wrcal_sanity_chk_reg: unisim.vcomponents.FDRE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => '1',
      D => wrcal_final_chk,
      Q => wrcal_sanity_chk,
      R => '0'
    );
\wrcal_start_dly_r_reg[4]_srl5\: unisim.vcomponents.SRL16E
     port map (
      A0 => '0',
      A1 => '0',
      A2 => '1',
      A3 => '0',
      CE => '1',
      CLK => \rdlvl_start_dly0_r_reg[14]_0\,
      D => wrcal_start_pre,
      Q => \wrcal_start_dly_r_reg[4]_srl5_n_0\
    );
\wrcal_start_dly_r_reg[4]_srl5_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000001001000"
    )
        port map (
      I0 => \init_state_r_reg_n_0_[4]\,
      I1 => complex_act_start_i_2_n_0,
      I2 => \init_state_r_reg_n_0_[1]\,
      I3 => \^q\(0),
      I4 => \init_state_r_reg_n_0_[2]\,
      I5 => \init_state_r_reg_n_0_[3]\,
      O => wrcal_start_pre
    );
\wrcal_start_dly_r_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => '1',
      D => \wrcal_start_dly_r_reg[4]_srl5_n_0\,
      Q => wrcal_start_dly_r(5),
      R => '0'
    );
wrcal_start_i_1: unisim.vcomponents.LUT4
    generic map(
      INIT => X"000E"
    )
        port map (
      I0 => \^wrcal_start_reg_0\,
      I1 => wrcal_start_dly_r(5),
      I2 => wrlvl_byte_redo,
      I3 => \rd_addr_reg[7]\,
      O => wrcal_start_i_1_n_0
    );
wrcal_start_reg: unisim.vcomponents.FDRE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => '1',
      D => wrcal_start_i_1_n_0,
      Q => \^wrcal_start_reg_0\,
      R => '0'
    );
\wrcal_wr_cnt[0]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => wrcal_wr_cnt_reg(0),
      O => \wrcal_wr_cnt[0]_i_1_n_0\
    );
\wrcal_wr_cnt[1]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => wrcal_wr_cnt_reg(0),
      I1 => wrcal_wr_cnt_reg(1),
      O => \wrcal_wr_cnt[1]_i_1_n_0\
    );
\wrcal_wr_cnt[2]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"A9"
    )
        port map (
      I0 => wrcal_wr_cnt_reg(2),
      I1 => wrcal_wr_cnt_reg(1),
      I2 => wrcal_wr_cnt_reg(0),
      O => wrcal_wr_cnt0(2)
    );
\wrcal_wr_cnt[3]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFF444444F4"
    )
        port map (
      I0 => calib_wrdata_en_i_2_n_0,
      I1 => detect_pi_found_dqs_i_2_n_0,
      I2 => \wrcal_wr_cnt[3]_i_4_n_0\,
      I3 => wrcal_wr_cnt_reg(3),
      I4 => wrcal_wr_cnt_reg(2),
      I5 => write_calib_reg_0,
      O => \wrcal_wr_cnt[3]_i_1_n_0\
    );
\wrcal_wr_cnt[3]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000100000"
    )
        port map (
      I0 => \cnt_init_mr_r[0]_i_2_n_0\,
      I1 => init_state_r(6),
      I2 => \init_state_r_reg_n_0_[5]\,
      I3 => \init_state_r_reg_n_0_[4]\,
      I4 => \^q\(0),
      I5 => \init_state_r_reg_n_0_[1]\,
      O => \wrcal_wr_cnt[3]_i_2_n_0\
    );
\wrcal_wr_cnt[3]_i_3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"AAA9"
    )
        port map (
      I0 => wrcal_wr_cnt_reg(3),
      I1 => wrcal_wr_cnt_reg(2),
      I2 => wrcal_wr_cnt_reg(0),
      I3 => wrcal_wr_cnt_reg(1),
      O => wrcal_wr_cnt0(3)
    );
\wrcal_wr_cnt[3]_i_4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => wrcal_wr_cnt_reg(0),
      I1 => wrcal_wr_cnt_reg(1),
      O => \wrcal_wr_cnt[3]_i_4_n_0\
    );
\wrcal_wr_cnt_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => \wrcal_wr_cnt[3]_i_2_n_0\,
      D => \wrcal_wr_cnt[0]_i_1_n_0\,
      Q => wrcal_wr_cnt_reg(0),
      R => \wrcal_wr_cnt[3]_i_1_n_0\
    );
\wrcal_wr_cnt_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => \wrcal_wr_cnt[3]_i_2_n_0\,
      D => \wrcal_wr_cnt[1]_i_1_n_0\,
      Q => wrcal_wr_cnt_reg(1),
      R => \wrcal_wr_cnt[3]_i_1_n_0\
    );
\wrcal_wr_cnt_reg[2]\: unisim.vcomponents.FDSE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => \wrcal_wr_cnt[3]_i_2_n_0\,
      D => wrcal_wr_cnt0(2),
      Q => wrcal_wr_cnt_reg(2),
      S => \wrcal_wr_cnt[3]_i_1_n_0\
    );
\wrcal_wr_cnt_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => \wrcal_wr_cnt[3]_i_2_n_0\,
      D => wrcal_wr_cnt0(3),
      Q => wrcal_wr_cnt_reg(3),
      R => \wrcal_wr_cnt[3]_i_1_n_0\
    );
\wrdq_div1_4to1_wrcal_first.phy_wrdata[190]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \^first_wrcal_pat_r\,
      I1 => ddr3_lm_done_r_reg_0,
      O => \wrdq_div1_4to1_wrcal_first.phy_wrdata[190]_i_1_n_0\
    );
\wrdq_div1_4to1_wrcal_first.phy_wrdata[511]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \^first_wrcal_pat_r\,
      I1 => ddr3_lm_done_r_reg_0,
      O => \wrdq_div1_4to1_wrcal_first.phy_wrdata[511]_i_1_n_0\
    );
\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[120]\: unisim.vcomponents.FDRE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[56]_0\(0),
      D => \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[120]_0\,
      Q => phy_wrdata(120),
      R => \wrdq_div1_4to1_wrcal_first.phy_wrdata[190]_i_1_n_0\
    );
\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[121]\: unisim.vcomponents.FDRE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[56]_0\(0),
      D => \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[121]_0\,
      Q => phy_wrdata(121),
      R => '0'
    );
\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[122]\: unisim.vcomponents.FDRE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[56]_0\(0),
      D => prbs_out(4),
      Q => phy_wrdata(122),
      R => \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[508]_0\
    );
\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[123]\: unisim.vcomponents.FDRE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[56]_0\(0),
      D => prbs_out(5),
      Q => phy_wrdata(123),
      R => \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[508]_0\
    );
\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[124]\: unisim.vcomponents.FDRE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[56]_0\(0),
      D => \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[124]_0\,
      Q => phy_wrdata(124),
      R => \wrdq_div1_4to1_wrcal_first.phy_wrdata[190]_i_1_n_0\
    );
\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[125]\: unisim.vcomponents.FDRE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[56]_0\(0),
      D => \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[125]_0\,
      Q => phy_wrdata(125),
      R => '0'
    );
\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[126]\: unisim.vcomponents.FDRE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[56]_0\(0),
      D => prbs_out(6),
      Q => phy_wrdata(126),
      R => \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[508]_0\
    );
\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[127]\: unisim.vcomponents.FDRE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[56]_0\(0),
      D => prbs_out(7),
      Q => phy_wrdata(127),
      R => \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[508]_0\
    );
\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[184]\: unisim.vcomponents.FDRE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[56]_0\(0),
      D => \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[184]_0\,
      Q => phy_wrdata(184),
      R => \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[187]_0\
    );
\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[185]\: unisim.vcomponents.FDSE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[56]_0\(0),
      D => prbs_out(8),
      Q => phy_wrdata(185),
      S => \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[508]_0\
    );
\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[186]\: unisim.vcomponents.FDRE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[56]_0\(0),
      D => \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[186]_0\,
      Q => phy_wrdata(186),
      R => \wrdq_div1_4to1_wrcal_first.phy_wrdata[190]_i_1_n_0\
    );
\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[187]\: unisim.vcomponents.FDSE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[56]_0\(0),
      D => \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[187]_1\,
      Q => phy_wrdata(187),
      S => \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[187]_0\
    );
\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[188]\: unisim.vcomponents.FDRE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[56]_0\(0),
      D => \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[188]_0\,
      Q => phy_wrdata(188),
      R => \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[187]_0\
    );
\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[189]\: unisim.vcomponents.FDSE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[56]_0\(0),
      D => prbs_out(9),
      Q => phy_wrdata(189),
      S => \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[508]_0\
    );
\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[190]\: unisim.vcomponents.FDRE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[56]_0\(0),
      D => \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[190]_0\,
      Q => phy_wrdata(190),
      R => \wrdq_div1_4to1_wrcal_first.phy_wrdata[190]_i_1_n_0\
    );
\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[191]\: unisim.vcomponents.FDSE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[56]_0\(0),
      D => \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[191]_0\,
      Q => phy_wrdata(191),
      S => \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[187]_0\
    );
\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[248]\: unisim.vcomponents.FDSE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[56]_0\(0),
      D => \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[248]_0\,
      Q => phy_wrdata(248),
      S => \wrdq_div1_4to1_wrcal_first.phy_wrdata[190]_i_1_n_0\
    );
\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[249]\: unisim.vcomponents.FDRE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[56]_0\(0),
      D => \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[249]_0\,
      Q => phy_wrdata(249),
      R => \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[187]_0\
    );
\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[250]\: unisim.vcomponents.FDSE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[56]_0\(0),
      D => prbs_out(10),
      Q => phy_wrdata(250),
      S => \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[508]_0\
    );
\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[251]\: unisim.vcomponents.FDRE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[56]_0\(0),
      D => \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[251]_0\,
      Q => phy_wrdata(251),
      R => \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[187]_0\
    );
\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[252]\: unisim.vcomponents.FDSE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[56]_0\(0),
      D => \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[252]_0\,
      Q => phy_wrdata(252),
      S => \wrdq_div1_4to1_wrcal_first.phy_wrdata[190]_i_1_n_0\
    );
\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[253]\: unisim.vcomponents.FDRE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[56]_0\(0),
      D => \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[253]_0\,
      Q => phy_wrdata(253),
      R => \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[187]_0\
    );
\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[254]\: unisim.vcomponents.FDSE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[56]_0\(0),
      D => prbs_out(11),
      Q => phy_wrdata(254),
      S => \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[508]_0\
    );
\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[255]\: unisim.vcomponents.FDRE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[56]_0\(0),
      D => \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[255]_0\,
      Q => phy_wrdata(255),
      R => \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[187]_0\
    );
\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[312]\: unisim.vcomponents.FDSE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[56]_0\(0),
      D => \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[312]_0\,
      Q => phy_wrdata(312),
      S => \wrdq_div1_4to1_wrcal_first.phy_wrdata[190]_i_1_n_0\
    );
\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[313]\: unisim.vcomponents.FDRE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[56]_0\(0),
      D => prbs_out(12),
      Q => phy_wrdata(313),
      R => \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[508]_0\
    );
\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[314]\: unisim.vcomponents.FDSE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[56]_0\(0),
      D => prbs_out(13),
      Q => phy_wrdata(314),
      S => \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[508]_0\
    );
\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[315]\: unisim.vcomponents.FDRE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[56]_0\(0),
      D => \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[315]_0\,
      Q => phy_wrdata(315),
      R => \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[187]_0\
    );
\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[316]\: unisim.vcomponents.FDSE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[56]_0\(0),
      D => \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[316]_0\,
      Q => phy_wrdata(316),
      S => \wrdq_div1_4to1_wrcal_first.phy_wrdata[190]_i_1_n_0\
    );
\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[317]\: unisim.vcomponents.FDRE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[56]_0\(0),
      D => prbs_out(14),
      Q => phy_wrdata(317),
      R => \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[508]_0\
    );
\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[318]\: unisim.vcomponents.FDSE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[56]_0\(0),
      D => prbs_out(15),
      Q => phy_wrdata(318),
      S => \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[508]_0\
    );
\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[319]\: unisim.vcomponents.FDRE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[56]_0\(0),
      D => \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[319]_0\,
      Q => phy_wrdata(319),
      R => \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[187]_0\
    );
\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[376]\: unisim.vcomponents.FDRE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[56]_0\(0),
      D => \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[376]_0\,
      Q => phy_wrdata(376),
      R => \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[187]_0\
    );
\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[377]\: unisim.vcomponents.FDSE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[56]_0\(0),
      D => \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[377]_0\,
      Q => phy_wrdata(377),
      S => \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[187]_0\
    );
\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[378]\: unisim.vcomponents.FDSE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[56]_0\(0),
      D => \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[378]_0\,
      Q => phy_wrdata(378),
      S => \wrdq_div1_4to1_wrcal_first.phy_wrdata[511]_i_1_n_0\
    );
\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[379]\: unisim.vcomponents.FDSE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[56]_0\(0),
      D => prbs_out(16),
      Q => phy_wrdata(379),
      S => \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[508]_0\
    );
\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[380]\: unisim.vcomponents.FDRE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[56]_0\(0),
      D => \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[380]_0\,
      Q => phy_wrdata(380),
      R => \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[187]_0\
    );
\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[381]\: unisim.vcomponents.FDSE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[56]_0\(0),
      D => \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[381]_0\,
      Q => phy_wrdata(381),
      S => \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[187]_0\
    );
\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[382]\: unisim.vcomponents.FDSE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[56]_0\(0),
      D => \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[382]_0\,
      Q => phy_wrdata(382),
      S => \wrdq_div1_4to1_wrcal_first.phy_wrdata[511]_i_1_n_0\
    );
\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[383]\: unisim.vcomponents.FDSE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[56]_0\(0),
      D => prbs_out(17),
      Q => phy_wrdata(383),
      S => \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[508]_0\
    );
\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[440]\: unisim.vcomponents.FDSE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[56]_0\(0),
      D => \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[440]_0\,
      Q => phy_wrdata(440),
      S => \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[187]_0\
    );
\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[441]\: unisim.vcomponents.FDRE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[56]_0\(0),
      D => \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[441]_0\,
      Q => phy_wrdata(441),
      R => \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[187]_0\
    );
\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[442]\: unisim.vcomponents.FDSE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[56]_0\(0),
      D => \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[442]_0\,
      Q => phy_wrdata(442),
      S => \wrdq_div1_4to1_wrcal_first.phy_wrdata[511]_i_1_n_0\
    );
\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[443]\: unisim.vcomponents.FDSE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[56]_0\(0),
      D => \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[443]_0\,
      Q => phy_wrdata(443),
      S => \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[187]_0\
    );
\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[444]\: unisim.vcomponents.FDSE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[56]_0\(0),
      D => \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[444]_0\,
      Q => phy_wrdata(444),
      S => \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[187]_0\
    );
\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[445]\: unisim.vcomponents.FDRE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[56]_0\(0),
      D => \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[445]_0\,
      Q => phy_wrdata(445),
      R => \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[187]_0\
    );
\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[446]\: unisim.vcomponents.FDSE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[56]_0\(0),
      D => \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[446]_0\,
      Q => phy_wrdata(446),
      S => \wrdq_div1_4to1_wrcal_first.phy_wrdata[511]_i_1_n_0\
    );
\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[447]\: unisim.vcomponents.FDSE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[56]_0\(0),
      D => \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[447]_0\,
      Q => phy_wrdata(447),
      S => \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[187]_0\
    );
\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[504]\: unisim.vcomponents.FDRE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[56]_0\(0),
      D => prbs_out(18),
      Q => phy_wrdata(504),
      R => \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[508]_0\
    );
\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[505]\: unisim.vcomponents.FDSE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[56]_0\(0),
      D => \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[505]_0\,
      Q => phy_wrdata(505),
      S => \wrdq_div1_4to1_wrcal_first.phy_wrdata[190]_i_1_n_0\
    );
\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[506]\: unisim.vcomponents.FDRE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[56]_0\(0),
      D => \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[506]_0\,
      Q => phy_wrdata(506),
      R => '0'
    );
\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[507]\: unisim.vcomponents.FDSE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[56]_0\(0),
      D => \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[507]_0\,
      Q => phy_wrdata(507),
      S => \wrdq_div1_4to1_wrcal_first.phy_wrdata[511]_i_1_n_0\
    );
\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[508]\: unisim.vcomponents.FDRE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[56]_0\(0),
      D => prbs_out(19),
      Q => phy_wrdata(508),
      R => \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[508]_0\
    );
\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[509]\: unisim.vcomponents.FDSE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[56]_0\(0),
      D => \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[509]_0\,
      Q => phy_wrdata(509),
      S => \wrdq_div1_4to1_wrcal_first.phy_wrdata[190]_i_1_n_0\
    );
\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[510]\: unisim.vcomponents.FDRE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[56]_0\(0),
      D => \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[510]_0\,
      Q => phy_wrdata(510),
      R => '0'
    );
\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[511]\: unisim.vcomponents.FDSE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[56]_0\(0),
      D => \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[511]_0\,
      Q => phy_wrdata(511),
      S => \wrdq_div1_4to1_wrcal_first.phy_wrdata[511]_i_1_n_0\
    );
\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[56]\: unisim.vcomponents.FDSE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[56]_0\(0),
      D => prbs_out(0),
      Q => phy_wrdata(56),
      S => \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[508]_0\
    );
\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[57]\: unisim.vcomponents.FDRE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[56]_0\(0),
      D => \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[57]_0\,
      Q => phy_wrdata(57),
      R => '0'
    );
\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[58]\: unisim.vcomponents.FDSE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[56]_0\(0),
      D => \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[58]_0\,
      Q => phy_wrdata(58),
      S => \wrdq_div1_4to1_wrcal_first.phy_wrdata[190]_i_1_n_0\
    );
\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[59]\: unisim.vcomponents.FDSE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[56]_0\(0),
      D => prbs_out(1),
      Q => phy_wrdata(59),
      S => \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[508]_0\
    );
\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[60]\: unisim.vcomponents.FDSE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[56]_0\(0),
      D => prbs_out(2),
      Q => phy_wrdata(60),
      S => \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[508]_0\
    );
\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[61]\: unisim.vcomponents.FDRE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[56]_0\(0),
      D => \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[61]_0\,
      Q => phy_wrdata(61),
      R => '0'
    );
\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[62]\: unisim.vcomponents.FDSE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[56]_0\(0),
      D => \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[62]_0\,
      Q => phy_wrdata(62),
      S => \wrdq_div1_4to1_wrcal_first.phy_wrdata[190]_i_1_n_0\
    );
\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[63]\: unisim.vcomponents.FDSE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[56]_0\(0),
      D => prbs_out(3),
      Q => phy_wrdata(63),
      S => \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[508]_0\
    );
write_calib_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"000000007F7F7F00"
    )
        port map (
      I0 => done_dqs_tap_inc,
      I1 => \init_state_r_reg_n_0_[1]\,
      I2 => write_calib_i_2_n_0,
      I3 => wrlvl_active_r1,
      I4 => \^phy_write_calib\,
      I5 => write_calib_reg_0,
      O => write_calib_i_1_n_0
    );
write_calib_i_2: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000000004"
    )
        port map (
      I0 => \init_state_r_reg_n_0_[2]\,
      I1 => \init_state_r_reg_n_0_[3]\,
      I2 => init_state_r(6),
      I3 => \init_state_r_reg_n_0_[5]\,
      I4 => \^q\(0),
      I5 => \init_state_r_reg_n_0_[4]\,
      O => write_calib_i_2_n_0
    );
write_calib_reg: unisim.vcomponents.FDRE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => '1',
      D => write_calib_i_1_n_0,
      Q => \^phy_write_calib\,
      R => '0'
    );
wrlvl_active_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000005540"
    )
        port map (
      I0 => done_dqs_tap_inc,
      I1 => wrlvl_odt,
      I2 => \en_cnt_div4.wrlvl_odt_i_2_n_0\,
      I3 => wrlvl_active,
      I4 => wrlvl_rank_done,
      I5 => write_calib_reg_0,
      O => wrlvl_active_i_1_n_0
    );
wrlvl_active_r1_reg: unisim.vcomponents.FDRE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => '1',
      D => wrlvl_active,
      Q => wrlvl_active_r1,
      R => '0'
    );
wrlvl_active_reg: unisim.vcomponents.FDRE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => '1',
      D => wrlvl_active_i_1_n_0,
      Q => wrlvl_active,
      R => '0'
    );
wrlvl_done_r1_reg: unisim.vcomponents.FDRE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => '1',
      D => wrlvl_done_r,
      Q => \^wrlvl_done_r1\,
      R => '0'
    );
wrlvl_done_r_reg: unisim.vcomponents.FDRE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => '1',
      D => wrlvl_done_r_reg_0,
      Q => wrlvl_done_r,
      R => '0'
    );
wrlvl_final_if_rst_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000020202220"
    )
        port map (
      I0 => wrlvl_final_if_rst_i_2_n_0,
      I1 => write_calib_reg_0,
      I2 => \^wrlvl_final_if_rst\,
      I3 => wrlvl_done_r,
      I4 => wrlvl_final_if_rst_i_3_n_0,
      I5 => \num_refresh[3]_i_6_n_0\,
      O => wrlvl_final_if_rst_i_1_n_0
    );
wrlvl_final_if_rst_i_2: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFBFFFFFFFF"
    )
        port map (
      I0 => \init_state_r_reg_n_0_[4]\,
      I1 => \init_state_r_reg_n_0_[5]\,
      I2 => init_state_r(6),
      I3 => \init_state_r_reg_n_0_[3]\,
      I4 => \init_state_r_reg_n_0_[2]\,
      I5 => \gen_no_mirror.div_clk_loop[0].phy_address[12]_i_2_n_0\,
      O => wrlvl_final_if_rst_i_2_n_0
    );
wrlvl_final_if_rst_i_3: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFFFD"
    )
        port map (
      I0 => \init_state_r_reg_n_0_[1]\,
      I1 => \init_state_r_reg_n_0_[4]\,
      I2 => \^q\(0),
      I3 => \init_state_r_reg_n_0_[5]\,
      I4 => init_state_r(6),
      I5 => \init_state_r[4]_i_4_n_0\,
      O => wrlvl_final_if_rst_i_3_n_0
    );
wrlvl_final_if_rst_reg: unisim.vcomponents.FDRE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => '1',
      D => wrlvl_final_if_rst_i_1_n_0,
      Q => \^wrlvl_final_if_rst\,
      R => '0'
    );
wrlvl_odt_ctl_i_1: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000AA20"
    )
        port map (
      I0 => wrlvl_odt_ctl_i_2_n_0,
      I1 => wrlvl_rank_done_r1,
      I2 => wrlvl_rank_done,
      I3 => wrlvl_odt_ctl,
      I4 => write_calib_reg_0,
      O => wrlvl_odt_ctl_i_1_n_0
    );
wrlvl_odt_ctl_i_2: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFDFFFDFFFDFFFF"
    )
        port map (
      I0 => detect_pi_found_dqs_i_2_n_0,
      I1 => \init_state_r[3]_i_6_n_0\,
      I2 => \init_state_r_reg_n_0_[4]\,
      I3 => \wrcal_reads[7]_i_4_n_0\,
      I4 => \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_11_n_0\,
      I5 => init_state_r1(3),
      O => wrlvl_odt_ctl_i_2_n_0
    );
wrlvl_odt_ctl_reg: unisim.vcomponents.FDRE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => '1',
      D => wrlvl_odt_ctl_i_1_n_0,
      Q => wrlvl_odt_ctl,
      R => '0'
    );
wrlvl_rank_done_r1_reg: unisim.vcomponents.FDRE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => '1',
      D => wrlvl_rank_done,
      Q => wrlvl_rank_done_r1,
      R => '0'
    );
wrlvl_rank_done_r6_reg_srl5: unisim.vcomponents.SRL16E
     port map (
      A0 => '0',
      A1 => '0',
      A2 => '1',
      A3 => '0',
      CE => '1',
      CLK => \rdlvl_start_dly0_r_reg[14]_0\,
      D => wrlvl_rank_done_r1,
      Q => wrlvl_rank_done_r6_reg_srl5_n_0
    );
wrlvl_rank_done_r7_reg: unisim.vcomponents.FDRE
     port map (
      C => \rdlvl_start_dly0_r_reg[14]_0\,
      CE => '1',
      D => wrlvl_rank_done_r6_reg_srl5_n_0,
      Q => wrlvl_rank_done_r7,
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mig_mig_7series_v4_2_ddr_phy_prbs_rdlvl is
  port (
    prbs_rdlvl_start_r : out STD_LOGIC;
    complex_victim_inc_reg_0 : out STD_LOGIC;
    prbs_rdlvl_prech_req_reg_0 : out STD_LOGIC;
    prbs_pi_stg2_f_en : out STD_LOGIC;
    prbs_pi_stg2_f_incdec : out STD_LOGIC;
    new_cnt_dqs_r_reg_0 : out STD_LOGIC;
    num_samples_done_r : out STD_LOGIC;
    prbs_rdlvl_done_reg_0 : out STD_LOGIC;
    prbs_last_byte_done : out STD_LOGIC;
    reset_rd_addr : out STD_LOGIC;
    complex_pi_incdec_done : out STD_LOGIC;
    \samples_cnt_r_reg[11]_0\ : out STD_LOGIC;
    D : out STD_LOGIC_VECTOR ( 5 downto 0 );
    \rd_victim_sel_reg[2]_0\ : out STD_LOGIC;
    \rd_victim_sel_reg[0]_0\ : out STD_LOGIC;
    \rd_victim_sel_reg[1]_0\ : out STD_LOGIC;
    prbs_rdlvl_done_pulse0 : out STD_LOGIC;
    prbs_rdlvl_done_reg_1 : out STD_LOGIC;
    dqs_found_done_r_reg : out STD_LOGIC;
    reset_rd_addr0 : out STD_LOGIC;
    \prbs_dqs_cnt_r_reg[0]_0\ : out STD_LOGIC;
    \prbs_dqs_cnt_r_reg[1]_0\ : out STD_LOGIC;
    \prbs_dqs_cnt_r_reg[2]_0\ : out STD_LOGIC;
    \prbs_dqs_cnt_r_reg[3]_0\ : out STD_LOGIC;
    reset_if_r9_reg : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_0\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
    prbs_rdlvl_start_r_reg_0 : in STD_LOGIC;
    \bit_cnt_reg[7]_0\ : in STD_LOGIC;
    mux_rd_valid_r0 : in STD_LOGIC;
    \samples_cnt_r_reg[0]_0\ : in STD_LOGIC;
    prbs_out : in STD_LOGIC_VECTOR ( 63 downto 0 );
    \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]_0\ : in STD_LOGIC;
    \gen_mux_rd[1].mux_rd_rise0_r1_reg[1]_0\ : in STD_LOGIC;
    \gen_mux_rd[2].mux_rd_rise0_r1_reg[2]_0\ : in STD_LOGIC;
    \gen_mux_rd[3].mux_rd_rise0_r1_reg[3]_0\ : in STD_LOGIC;
    \gen_mux_rd[4].mux_rd_rise0_r1_reg[4]_0\ : in STD_LOGIC;
    \gen_mux_rd[5].mux_rd_rise0_r1_reg[5]_0\ : in STD_LOGIC;
    \gen_mux_rd[6].mux_rd_rise0_r1_reg[6]_0\ : in STD_LOGIC;
    \gen_mux_rd[7].mux_rd_rise0_r1_reg[7]_0\ : in STD_LOGIC;
    \gen_mux_rd[0].mux_rd_fall0_r1_reg[0]_0\ : in STD_LOGIC;
    \gen_mux_rd[1].mux_rd_fall0_r1_reg[1]_0\ : in STD_LOGIC;
    \gen_mux_rd[2].mux_rd_fall0_r1_reg[2]_0\ : in STD_LOGIC;
    \gen_mux_rd[3].mux_rd_fall0_r1_reg[3]_0\ : in STD_LOGIC;
    \gen_mux_rd[4].mux_rd_fall0_r1_reg[4]_0\ : in STD_LOGIC;
    \gen_mux_rd[5].mux_rd_fall0_r1_reg[5]_0\ : in STD_LOGIC;
    \gen_mux_rd[6].mux_rd_fall0_r1_reg[6]_0\ : in STD_LOGIC;
    \gen_mux_rd[7].mux_rd_fall0_r1_reg[7]_0\ : in STD_LOGIC;
    \gen_mux_rd[0].mux_rd_rise1_r1_reg[0]_0\ : in STD_LOGIC;
    \gen_mux_rd[1].mux_rd_rise1_r1_reg[1]_0\ : in STD_LOGIC;
    \gen_mux_rd[2].mux_rd_rise1_r1_reg[2]_0\ : in STD_LOGIC;
    \gen_mux_rd[3].mux_rd_rise1_r1_reg[3]_0\ : in STD_LOGIC;
    \gen_mux_rd[4].mux_rd_rise1_r1_reg[4]_0\ : in STD_LOGIC;
    \gen_mux_rd[5].mux_rd_rise1_r1_reg[5]_0\ : in STD_LOGIC;
    \gen_mux_rd[6].mux_rd_rise1_r1_reg[6]_0\ : in STD_LOGIC;
    \gen_mux_rd[7].mux_rd_rise1_r1_reg[7]_0\ : in STD_LOGIC;
    \gen_mux_rd[0].mux_rd_fall1_r1_reg[0]_0\ : in STD_LOGIC;
    \gen_mux_rd[1].mux_rd_fall1_r1_reg[1]_0\ : in STD_LOGIC;
    \gen_mux_rd[2].mux_rd_fall1_r1_reg[2]_0\ : in STD_LOGIC;
    \gen_mux_rd[3].mux_rd_fall1_r1_reg[3]_0\ : in STD_LOGIC;
    \gen_mux_rd[4].mux_rd_fall1_r1_reg[4]_0\ : in STD_LOGIC;
    \gen_mux_rd[5].mux_rd_fall1_r1_reg[5]_0\ : in STD_LOGIC;
    \gen_mux_rd[6].mux_rd_fall1_r1_reg[6]_0\ : in STD_LOGIC;
    \gen_mux_rd[7].mux_rd_fall1_r1_reg[7]_0\ : in STD_LOGIC;
    \gen_mux_rd[0].mux_rd_rise2_r1_reg[0]_0\ : in STD_LOGIC;
    \gen_mux_rd[1].mux_rd_rise2_r1_reg[1]_0\ : in STD_LOGIC;
    \gen_mux_rd[2].mux_rd_rise2_r1_reg[2]_0\ : in STD_LOGIC;
    \gen_mux_rd[3].mux_rd_rise2_r1_reg[3]_0\ : in STD_LOGIC;
    \gen_mux_rd[4].mux_rd_rise2_r1_reg[4]_0\ : in STD_LOGIC;
    \gen_mux_rd[5].mux_rd_rise2_r1_reg[5]_0\ : in STD_LOGIC;
    \gen_mux_rd[6].mux_rd_rise2_r1_reg[6]_0\ : in STD_LOGIC;
    \gen_mux_rd[7].mux_rd_rise2_r1_reg[7]_0\ : in STD_LOGIC;
    \gen_mux_rd[0].mux_rd_fall2_r1_reg[0]_0\ : in STD_LOGIC;
    \gen_mux_rd[1].mux_rd_fall2_r1_reg[1]_0\ : in STD_LOGIC;
    \gen_mux_rd[2].mux_rd_fall2_r1_reg[2]_0\ : in STD_LOGIC;
    \gen_mux_rd[3].mux_rd_fall2_r1_reg[3]_0\ : in STD_LOGIC;
    \gen_mux_rd[4].mux_rd_fall2_r1_reg[4]_0\ : in STD_LOGIC;
    \gen_mux_rd[5].mux_rd_fall2_r1_reg[5]_0\ : in STD_LOGIC;
    \gen_mux_rd[6].mux_rd_fall2_r1_reg[6]_0\ : in STD_LOGIC;
    \gen_mux_rd[7].mux_rd_fall2_r1_reg[7]_0\ : in STD_LOGIC;
    \gen_mux_rd[0].mux_rd_rise3_r1_reg[0]_0\ : in STD_LOGIC;
    \gen_mux_rd[1].mux_rd_rise3_r1_reg[1]_0\ : in STD_LOGIC;
    \gen_mux_rd[2].mux_rd_rise3_r1_reg[2]_0\ : in STD_LOGIC;
    \gen_mux_rd[3].mux_rd_rise3_r1_reg[3]_0\ : in STD_LOGIC;
    \gen_mux_rd[4].mux_rd_rise3_r1_reg[4]_0\ : in STD_LOGIC;
    \gen_mux_rd[5].mux_rd_rise3_r1_reg[5]_0\ : in STD_LOGIC;
    \gen_mux_rd[6].mux_rd_rise3_r1_reg[6]_0\ : in STD_LOGIC;
    \gen_mux_rd[7].mux_rd_rise3_r1_reg[7]_0\ : in STD_LOGIC;
    \gen_mux_rd[0].mux_rd_fall3_r1_reg[0]_0\ : in STD_LOGIC;
    \gen_mux_rd[1].mux_rd_fall3_r1_reg[1]_0\ : in STD_LOGIC;
    \gen_mux_rd[2].mux_rd_fall3_r1_reg[2]_0\ : in STD_LOGIC;
    \gen_mux_rd[3].mux_rd_fall3_r1_reg[3]_0\ : in STD_LOGIC;
    \gen_mux_rd[4].mux_rd_fall3_r1_reg[4]_0\ : in STD_LOGIC;
    \gen_mux_rd[5].mux_rd_fall3_r1_reg[5]_0\ : in STD_LOGIC;
    \gen_mux_rd[6].mux_rd_fall3_r1_reg[6]_0\ : in STD_LOGIC;
    \gen_mux_rd[7].mux_rd_fall3_r1_reg[7]_0\ : in STD_LOGIC;
    \prbs_dec_tap_cnt_reg[0]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \match_flag_and_reg[7]_0\ : in STD_LOGIC;
    no_err_win_detected_reg_0 : in STD_LOGIC;
    prbs_found_2nd_edge_r_reg_0 : in STD_LOGIC;
    new_cnt_dqs_r_reg_1 : in STD_LOGIC;
    \rd_victim_sel_reg[2]_1\ : in STD_LOGIC;
    prech_done : in STD_LOGIC;
    \cmp_err_4to1.compare_err_f3_reg_0\ : in STD_LOGIC;
    complex_act_start : in STD_LOGIC;
    prbs_rdlvl_done_r1 : in STD_LOGIC;
    \gen_byte_sel_div2.byte_sel_cnt_reg[0]\ : in STD_LOGIC;
    \init_state_r[0]_i_27\ : in STD_LOGIC;
    \gen_byte_sel_div2.byte_sel_cnt_reg[0]_0\ : in STD_LOGIC;
    rdlvl_last_byte_done : in STD_LOGIC;
    \init_state_r[0]_i_27_0\ : in STD_LOGIC;
    complex_ocal_reset_rd_addr : in STD_LOGIC;
    rdlvl_stg1_done_r1 : in STD_LOGIC;
    reset_if : in STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 3 downto 0 );
    reset_if_r9 : in STD_LOGIC;
    reset_if_reg : in STD_LOGIC;
    E : in STD_LOGIC_VECTOR ( 0 to 0 );
    \prbs_dqs_cnt_r_reg[0]_1\ : in STD_LOGIC;
    \rdlvl_cpt_tap_cnt_reg[5]_0\ : in STD_LOGIC;
    \rdlvl_cpt_tap_cnt_reg[5]_1\ : in STD_LOGIC_VECTOR ( 5 downto 0 );
    \rdlvl_cpt_tap_cnt_reg[5]_2\ : in STD_LOGIC;
    \rdlvl_cpt_tap_cnt_reg[5]_3\ : in STD_LOGIC_VECTOR ( 5 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of mig_mig_7series_v4_2_ddr_phy_prbs_rdlvl : entity is "mig_7series_v4_2_ddr_phy_prbs_rdlvl";
end mig_mig_7series_v4_2_ddr_phy_prbs_rdlvl;

architecture STRUCTURE of mig_mig_7series_v4_2_ddr_phy_prbs_rdlvl is
  signal \^d\ : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal bit_cnt0 : STD_LOGIC;
  signal \bit_cnt[7]_i_1_n_0\ : STD_LOGIC;
  signal \bit_cnt[7]_i_3_n_0\ : STD_LOGIC;
  signal \bit_cnt_reg_n_0_[0]\ : STD_LOGIC;
  signal \bit_cnt_reg_n_0_[1]\ : STD_LOGIC;
  signal \bit_cnt_reg_n_0_[2]\ : STD_LOGIC;
  signal \bit_cnt_reg_n_0_[3]\ : STD_LOGIC;
  signal \cmp_err_4to1.compare_err_f0_i_2_n_0\ : STD_LOGIC;
  signal \cmp_err_4to1.compare_err_f0_i_3_n_0\ : STD_LOGIC;
  signal \cmp_err_4to1.compare_err_f0_reg_n_0\ : STD_LOGIC;
  signal \cmp_err_4to1.compare_err_f1_i_2_n_0\ : STD_LOGIC;
  signal \cmp_err_4to1.compare_err_f1_i_3_n_0\ : STD_LOGIC;
  signal \cmp_err_4to1.compare_err_f1_reg_n_0\ : STD_LOGIC;
  signal \cmp_err_4to1.compare_err_f2_i_2_n_0\ : STD_LOGIC;
  signal \cmp_err_4to1.compare_err_f2_i_3_n_0\ : STD_LOGIC;
  signal \cmp_err_4to1.compare_err_f2_reg_n_0\ : STD_LOGIC;
  signal \cmp_err_4to1.compare_err_f3_i_2_n_0\ : STD_LOGIC;
  signal \cmp_err_4to1.compare_err_f3_i_3_n_0\ : STD_LOGIC;
  signal \cmp_err_4to1.compare_err_f3_reg_n_0\ : STD_LOGIC;
  signal \cmp_err_4to1.compare_err_i_4_n_0\ : STD_LOGIC;
  signal \cmp_err_4to1.compare_err_r0_i_2_n_0\ : STD_LOGIC;
  signal \cmp_err_4to1.compare_err_r0_i_3_n_0\ : STD_LOGIC;
  signal \cmp_err_4to1.compare_err_r0_reg_n_0\ : STD_LOGIC;
  signal \cmp_err_4to1.compare_err_r1_i_2_n_0\ : STD_LOGIC;
  signal \cmp_err_4to1.compare_err_r1_i_3_n_0\ : STD_LOGIC;
  signal \cmp_err_4to1.compare_err_r1_reg_n_0\ : STD_LOGIC;
  signal \cmp_err_4to1.compare_err_r2_i_2_n_0\ : STD_LOGIC;
  signal \cmp_err_4to1.compare_err_r2_i_3_n_0\ : STD_LOGIC;
  signal \cmp_err_4to1.compare_err_r2_reg_n_0\ : STD_LOGIC;
  signal \cmp_err_4to1.compare_err_r3_i_2_n_0\ : STD_LOGIC;
  signal \cmp_err_4to1.compare_err_r3_i_3_n_0\ : STD_LOGIC;
  signal \cmp_err_4to1.compare_err_r3_reg_n_0\ : STD_LOGIC;
  signal \cmp_err_4to1.compare_err_reg_n_0\ : STD_LOGIC;
  signal \cmp_err_pb_4to1.(null)[0].compare_err_pb[0]_i_3_n_0\ : STD_LOGIC;
  signal \cmp_err_pb_4to1.(null)[0].compare_err_pb[0]_i_4_n_0\ : STD_LOGIC;
  signal \cmp_err_pb_4to1.(null)[0].compare_err_pb[0]_i_5_n_0\ : STD_LOGIC;
  signal \cmp_err_pb_4to1.(null)[0].compare_err_pb[0]_i_6_n_0\ : STD_LOGIC;
  signal \cmp_err_pb_4to1.(null)[0].compare_err_pb[0]_i_7_n_0\ : STD_LOGIC;
  signal \cmp_err_pb_4to1.(null)[1].compare_err_pb[1]_i_2_n_0\ : STD_LOGIC;
  signal \cmp_err_pb_4to1.(null)[1].compare_err_pb[1]_i_3_n_0\ : STD_LOGIC;
  signal \cmp_err_pb_4to1.(null)[1].compare_err_pb[1]_i_4_n_0\ : STD_LOGIC;
  signal \cmp_err_pb_4to1.(null)[2].compare_err_pb[2]_i_2_n_0\ : STD_LOGIC;
  signal \cmp_err_pb_4to1.(null)[2].compare_err_pb[2]_i_3_n_0\ : STD_LOGIC;
  signal \cmp_err_pb_4to1.(null)[2].compare_err_pb[2]_i_4_n_0\ : STD_LOGIC;
  signal \cmp_err_pb_4to1.(null)[3].compare_err_pb[3]_i_2_n_0\ : STD_LOGIC;
  signal \cmp_err_pb_4to1.(null)[3].compare_err_pb[3]_i_3_n_0\ : STD_LOGIC;
  signal \cmp_err_pb_4to1.(null)[3].compare_err_pb[3]_i_4_n_0\ : STD_LOGIC;
  signal \cmp_err_pb_4to1.(null)[4].compare_err_pb[4]_i_2_n_0\ : STD_LOGIC;
  signal \cmp_err_pb_4to1.(null)[4].compare_err_pb[4]_i_3_n_0\ : STD_LOGIC;
  signal \cmp_err_pb_4to1.(null)[4].compare_err_pb[4]_i_4_n_0\ : STD_LOGIC;
  signal \cmp_err_pb_4to1.(null)[5].compare_err_pb[5]_i_2_n_0\ : STD_LOGIC;
  signal \cmp_err_pb_4to1.(null)[5].compare_err_pb[5]_i_3_n_0\ : STD_LOGIC;
  signal \cmp_err_pb_4to1.(null)[5].compare_err_pb[5]_i_4_n_0\ : STD_LOGIC;
  signal \cmp_err_pb_4to1.(null)[6].compare_err_pb[6]_i_2_n_0\ : STD_LOGIC;
  signal \cmp_err_pb_4to1.(null)[6].compare_err_pb[6]_i_3_n_0\ : STD_LOGIC;
  signal \cmp_err_pb_4to1.(null)[6].compare_err_pb[6]_i_4_n_0\ : STD_LOGIC;
  signal \cmp_err_pb_4to1.(null)[7].compare_err_pb[7]_i_2_n_0\ : STD_LOGIC;
  signal \cmp_err_pb_4to1.(null)[7].compare_err_pb[7]_i_3_n_0\ : STD_LOGIC;
  signal \cmp_err_pb_4to1.(null)[7].compare_err_pb[7]_i_4_n_0\ : STD_LOGIC;
  signal cnt_wait_state : STD_LOGIC;
  signal cnt_wait_state_i_1_n_0 : STD_LOGIC;
  signal compare_err0 : STD_LOGIC;
  signal compare_err086_out : STD_LOGIC;
  signal compare_err_f00 : STD_LOGIC;
  signal compare_err_f10 : STD_LOGIC;
  signal compare_err_f20 : STD_LOGIC;
  signal compare_err_f30 : STD_LOGIC;
  signal compare_err_latch_i_1_n_0 : STD_LOGIC;
  signal compare_err_latch_reg_n_0 : STD_LOGIC;
  signal compare_err_pb : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal compare_err_pb_and_i_1_n_0 : STD_LOGIC;
  signal compare_err_pb_and_i_2_n_0 : STD_LOGIC;
  signal compare_err_pb_and_i_3_n_0 : STD_LOGIC;
  signal compare_err_pb_and_reg_n_0 : STD_LOGIC;
  signal compare_err_pb_or_i_1_n_0 : STD_LOGIC;
  signal compare_err_pb_or_i_2_n_0 : STD_LOGIC;
  signal compare_err_pb_or_i_3_n_0 : STD_LOGIC;
  signal compare_err_r00 : STD_LOGIC;
  signal compare_err_r10 : STD_LOGIC;
  signal compare_err_r20 : STD_LOGIC;
  signal compare_err_r30 : STD_LOGIC;
  signal \^complex_pi_incdec_done\ : STD_LOGIC;
  signal complex_pi_incdec_done_i_1_n_0 : STD_LOGIC;
  signal complex_pi_incdec_done_i_2_n_0 : STD_LOGIC;
  signal complex_pi_incdec_done_i_3_n_0 : STD_LOGIC;
  signal complex_pi_incdec_done_i_4_n_0 : STD_LOGIC;
  signal complex_pi_incdec_done_i_5_n_0 : STD_LOGIC;
  signal complex_pi_incdec_done_i_6_n_0 : STD_LOGIC;
  signal complex_pi_incdec_done_i_7_n_0 : STD_LOGIC;
  signal complex_pi_incdec_done_i_8_n_0 : STD_LOGIC;
  signal complex_victim_inc : STD_LOGIC;
  signal data0 : STD_LOGIC_VECTOR ( 11 downto 1 );
  signal edge_det_error_i_1_n_0 : STD_LOGIC;
  signal edge_det_error_i_2_n_0 : STD_LOGIC;
  signal edge_det_error_i_3_n_0 : STD_LOGIC;
  signal edge_det_error_i_4_n_0 : STD_LOGIC;
  signal edge_det_error_i_5_n_0 : STD_LOGIC;
  signal edge_det_error_i_6_n_0 : STD_LOGIC;
  signal edge_det_error_i_7_n_0 : STD_LOGIC;
  signal edge_det_error_reg_n_0 : STD_LOGIC;
  signal err_chk_invalid : STD_LOGIC;
  signal err_chk_invalid_i_1_n_0 : STD_LOGIC;
  signal fine_inc_stage_i_1_n_0 : STD_LOGIC;
  signal fine_inc_stage_reg_n_0 : STD_LOGIC;
  signal fine_pi_dec_cnt : STD_LOGIC;
  signal \fine_pi_dec_cnt[0]_i_1_n_0\ : STD_LOGIC;
  signal \fine_pi_dec_cnt[0]_i_2_n_0\ : STD_LOGIC;
  signal \fine_pi_dec_cnt[0]_i_3_n_0\ : STD_LOGIC;
  signal \fine_pi_dec_cnt[1]_i_1_n_0\ : STD_LOGIC;
  signal \fine_pi_dec_cnt[1]_i_2_n_0\ : STD_LOGIC;
  signal \fine_pi_dec_cnt[1]_i_3_n_0\ : STD_LOGIC;
  signal \fine_pi_dec_cnt[2]_i_1_n_0\ : STD_LOGIC;
  signal \fine_pi_dec_cnt[2]_i_2_n_0\ : STD_LOGIC;
  signal \fine_pi_dec_cnt[3]_i_10_n_0\ : STD_LOGIC;
  signal \fine_pi_dec_cnt[3]_i_11_n_0\ : STD_LOGIC;
  signal \fine_pi_dec_cnt[3]_i_12_n_0\ : STD_LOGIC;
  signal \fine_pi_dec_cnt[3]_i_1_n_0\ : STD_LOGIC;
  signal \fine_pi_dec_cnt[3]_i_2_n_0\ : STD_LOGIC;
  signal \fine_pi_dec_cnt[3]_i_3_n_0\ : STD_LOGIC;
  signal \fine_pi_dec_cnt[3]_i_4_n_0\ : STD_LOGIC;
  signal \fine_pi_dec_cnt[3]_i_5_n_0\ : STD_LOGIC;
  signal \fine_pi_dec_cnt[3]_i_6_n_0\ : STD_LOGIC;
  signal \fine_pi_dec_cnt[3]_i_8_n_0\ : STD_LOGIC;
  signal \fine_pi_dec_cnt[3]_i_9_n_0\ : STD_LOGIC;
  signal \fine_pi_dec_cnt[4]_i_1_n_0\ : STD_LOGIC;
  signal \fine_pi_dec_cnt[4]_i_2_n_0\ : STD_LOGIC;
  signal \fine_pi_dec_cnt[4]_i_3_n_0\ : STD_LOGIC;
  signal \fine_pi_dec_cnt[4]_i_4_n_0\ : STD_LOGIC;
  signal \fine_pi_dec_cnt[5]_i_11_n_0\ : STD_LOGIC;
  signal \fine_pi_dec_cnt[5]_i_12_n_0\ : STD_LOGIC;
  signal \fine_pi_dec_cnt[5]_i_13_n_0\ : STD_LOGIC;
  signal \fine_pi_dec_cnt[5]_i_14_n_0\ : STD_LOGIC;
  signal \fine_pi_dec_cnt[5]_i_2_n_0\ : STD_LOGIC;
  signal \fine_pi_dec_cnt[5]_i_3_n_0\ : STD_LOGIC;
  signal \fine_pi_dec_cnt[5]_i_4_n_0\ : STD_LOGIC;
  signal \fine_pi_dec_cnt[5]_i_5_n_0\ : STD_LOGIC;
  signal \fine_pi_dec_cnt[5]_i_6_n_0\ : STD_LOGIC;
  signal \fine_pi_dec_cnt[5]_i_7_n_0\ : STD_LOGIC;
  signal \fine_pi_dec_cnt[5]_i_8_n_0\ : STD_LOGIC;
  signal \fine_pi_dec_cnt[5]_i_9_n_0\ : STD_LOGIC;
  signal \fine_pi_dec_cnt_reg[3]_i_7_n_0\ : STD_LOGIC;
  signal \fine_pi_dec_cnt_reg[3]_i_7_n_1\ : STD_LOGIC;
  signal \fine_pi_dec_cnt_reg[3]_i_7_n_2\ : STD_LOGIC;
  signal \fine_pi_dec_cnt_reg[3]_i_7_n_3\ : STD_LOGIC;
  signal \fine_pi_dec_cnt_reg[3]_i_7_n_4\ : STD_LOGIC;
  signal \fine_pi_dec_cnt_reg[3]_i_7_n_5\ : STD_LOGIC;
  signal \fine_pi_dec_cnt_reg[3]_i_7_n_6\ : STD_LOGIC;
  signal \fine_pi_dec_cnt_reg[3]_i_7_n_7\ : STD_LOGIC;
  signal \fine_pi_dec_cnt_reg[5]_i_10_n_1\ : STD_LOGIC;
  signal \fine_pi_dec_cnt_reg[5]_i_10_n_3\ : STD_LOGIC;
  signal \fine_pi_dec_cnt_reg[5]_i_10_n_6\ : STD_LOGIC;
  signal \fine_pi_dec_cnt_reg[5]_i_10_n_7\ : STD_LOGIC;
  signal \fine_pi_dec_cnt_reg_n_0_[0]\ : STD_LOGIC;
  signal \fine_pi_dec_cnt_reg_n_0_[1]\ : STD_LOGIC;
  signal \fine_pi_dec_cnt_reg_n_0_[2]\ : STD_LOGIC;
  signal \fine_pi_dec_cnt_reg_n_0_[3]\ : STD_LOGIC;
  signal \fine_pi_dec_cnt_reg_n_0_[4]\ : STD_LOGIC;
  signal \fine_pi_dec_cnt_reg_n_0_[5]\ : STD_LOGIC;
  signal \gen_mux_div4.gen_rd_4[1].mux_rd_fall0_r2_reg\ : STD_LOGIC;
  signal \gen_mux_div4.gen_rd_4[1].mux_rd_fall1_r2_reg\ : STD_LOGIC;
  signal \gen_mux_div4.gen_rd_4[1].mux_rd_fall2_r2_reg\ : STD_LOGIC;
  signal \gen_mux_div4.gen_rd_4[1].mux_rd_fall3_r2_reg\ : STD_LOGIC;
  signal \gen_mux_div4.gen_rd_4[1].mux_rd_rise0_r2_reg\ : STD_LOGIC;
  signal \gen_mux_div4.gen_rd_4[1].mux_rd_rise1_r2_reg\ : STD_LOGIC;
  signal \gen_mux_div4.gen_rd_4[1].mux_rd_rise2_r2_reg\ : STD_LOGIC;
  signal \gen_mux_div4.gen_rd_4[1].mux_rd_rise3_r2_reg\ : STD_LOGIC;
  signal \gen_mux_div4.gen_rd_4[2].mux_rd_fall0_r2_reg\ : STD_LOGIC;
  signal \gen_mux_div4.gen_rd_4[2].mux_rd_fall1_r2_reg\ : STD_LOGIC;
  signal \gen_mux_div4.gen_rd_4[2].mux_rd_fall2_r2_reg\ : STD_LOGIC;
  signal \gen_mux_div4.gen_rd_4[2].mux_rd_fall3_r2_reg\ : STD_LOGIC;
  signal \gen_mux_div4.gen_rd_4[2].mux_rd_rise0_r2_reg\ : STD_LOGIC;
  signal \gen_mux_div4.gen_rd_4[2].mux_rd_rise1_r2_reg\ : STD_LOGIC;
  signal \gen_mux_div4.gen_rd_4[2].mux_rd_rise2_r2_reg\ : STD_LOGIC;
  signal \gen_mux_div4.gen_rd_4[2].mux_rd_rise3_r2_reg\ : STD_LOGIC;
  signal \gen_mux_div4.gen_rd_4[3].mux_rd_fall0_r2_reg\ : STD_LOGIC;
  signal \gen_mux_div4.gen_rd_4[3].mux_rd_fall1_r2_reg\ : STD_LOGIC;
  signal \gen_mux_div4.gen_rd_4[3].mux_rd_fall2_r2_reg\ : STD_LOGIC;
  signal \gen_mux_div4.gen_rd_4[3].mux_rd_fall3_r2_reg\ : STD_LOGIC;
  signal \gen_mux_div4.gen_rd_4[3].mux_rd_rise0_r2_reg\ : STD_LOGIC;
  signal \gen_mux_div4.gen_rd_4[3].mux_rd_rise1_r2_reg\ : STD_LOGIC;
  signal \gen_mux_div4.gen_rd_4[3].mux_rd_rise2_r2_reg\ : STD_LOGIC;
  signal \gen_mux_div4.gen_rd_4[3].mux_rd_rise3_r2_reg\ : STD_LOGIC;
  signal \gen_mux_div4.gen_rd_4[4].mux_rd_fall0_r2_reg\ : STD_LOGIC;
  signal \gen_mux_div4.gen_rd_4[4].mux_rd_fall1_r2_reg\ : STD_LOGIC;
  signal \gen_mux_div4.gen_rd_4[4].mux_rd_fall2_r2_reg\ : STD_LOGIC;
  signal \gen_mux_div4.gen_rd_4[4].mux_rd_fall3_r2_reg\ : STD_LOGIC;
  signal \gen_mux_div4.gen_rd_4[4].mux_rd_rise0_r2_reg\ : STD_LOGIC;
  signal \gen_mux_div4.gen_rd_4[4].mux_rd_rise1_r2_reg\ : STD_LOGIC;
  signal \gen_mux_div4.gen_rd_4[4].mux_rd_rise2_r2_reg\ : STD_LOGIC;
  signal \gen_mux_div4.gen_rd_4[4].mux_rd_rise3_r2_reg\ : STD_LOGIC;
  signal \gen_mux_div4.gen_rd_4[5].mux_rd_fall0_r2_reg\ : STD_LOGIC;
  signal \gen_mux_div4.gen_rd_4[5].mux_rd_fall1_r2_reg\ : STD_LOGIC;
  signal \gen_mux_div4.gen_rd_4[5].mux_rd_fall2_r2_reg\ : STD_LOGIC;
  signal \gen_mux_div4.gen_rd_4[5].mux_rd_fall3_r2_reg\ : STD_LOGIC;
  signal \gen_mux_div4.gen_rd_4[5].mux_rd_rise0_r2_reg\ : STD_LOGIC;
  signal \gen_mux_div4.gen_rd_4[5].mux_rd_rise1_r2_reg\ : STD_LOGIC;
  signal \gen_mux_div4.gen_rd_4[5].mux_rd_rise2_r2_reg\ : STD_LOGIC;
  signal \gen_mux_div4.gen_rd_4[5].mux_rd_rise3_r2_reg\ : STD_LOGIC;
  signal \gen_mux_div4.gen_rd_4[6].mux_rd_fall0_r2_reg\ : STD_LOGIC;
  signal \gen_mux_div4.gen_rd_4[6].mux_rd_fall1_r2_reg\ : STD_LOGIC;
  signal \gen_mux_div4.gen_rd_4[6].mux_rd_fall2_r2_reg\ : STD_LOGIC;
  signal \gen_mux_div4.gen_rd_4[6].mux_rd_fall3_r2_reg\ : STD_LOGIC;
  signal \gen_mux_div4.gen_rd_4[6].mux_rd_rise0_r2_reg\ : STD_LOGIC;
  signal \gen_mux_div4.gen_rd_4[6].mux_rd_rise1_r2_reg\ : STD_LOGIC;
  signal \gen_mux_div4.gen_rd_4[6].mux_rd_rise2_r2_reg\ : STD_LOGIC;
  signal \gen_mux_div4.gen_rd_4[6].mux_rd_rise3_r2_reg\ : STD_LOGIC;
  signal \gen_mux_div4.gen_rd_4[7].mux_rd_fall0_r2_reg\ : STD_LOGIC;
  signal \gen_mux_div4.gen_rd_4[7].mux_rd_fall1_r2_reg\ : STD_LOGIC;
  signal \gen_mux_div4.gen_rd_4[7].mux_rd_fall2_r2_reg\ : STD_LOGIC;
  signal \gen_mux_div4.gen_rd_4[7].mux_rd_fall3_r2_reg\ : STD_LOGIC;
  signal \gen_mux_div4.gen_rd_4[7].mux_rd_rise0_r2_reg\ : STD_LOGIC;
  signal \gen_mux_div4.gen_rd_4[7].mux_rd_rise1_r2_reg\ : STD_LOGIC;
  signal \gen_mux_div4.gen_rd_4[7].mux_rd_rise2_r2_reg\ : STD_LOGIC;
  signal \gen_mux_div4.gen_rd_4[7].mux_rd_rise3_r2_reg\ : STD_LOGIC;
  signal \gen_mux_rd[1].mux_rd_fall0_r1_reg\ : STD_LOGIC;
  signal \gen_mux_rd[1].mux_rd_fall1_r1_reg\ : STD_LOGIC;
  signal \gen_mux_rd[1].mux_rd_fall2_r1_reg\ : STD_LOGIC;
  signal \gen_mux_rd[1].mux_rd_fall3_r1_reg\ : STD_LOGIC;
  signal \gen_mux_rd[1].mux_rd_rise0_r1_reg\ : STD_LOGIC;
  signal \gen_mux_rd[1].mux_rd_rise1_r1_reg\ : STD_LOGIC;
  signal \gen_mux_rd[1].mux_rd_rise2_r1_reg\ : STD_LOGIC;
  signal \gen_mux_rd[1].mux_rd_rise3_r1_reg\ : STD_LOGIC;
  signal \gen_mux_rd[2].mux_rd_fall0_r1_reg\ : STD_LOGIC;
  signal \gen_mux_rd[2].mux_rd_fall1_r1_reg\ : STD_LOGIC;
  signal \gen_mux_rd[2].mux_rd_fall2_r1_reg\ : STD_LOGIC;
  signal \gen_mux_rd[2].mux_rd_fall3_r1_reg\ : STD_LOGIC;
  signal \gen_mux_rd[2].mux_rd_rise0_r1_reg\ : STD_LOGIC;
  signal \gen_mux_rd[2].mux_rd_rise1_r1_reg\ : STD_LOGIC;
  signal \gen_mux_rd[2].mux_rd_rise2_r1_reg\ : STD_LOGIC;
  signal \gen_mux_rd[2].mux_rd_rise3_r1_reg\ : STD_LOGIC;
  signal \gen_mux_rd[3].mux_rd_fall0_r1_reg\ : STD_LOGIC;
  signal \gen_mux_rd[3].mux_rd_fall1_r1_reg\ : STD_LOGIC;
  signal \gen_mux_rd[3].mux_rd_fall2_r1_reg\ : STD_LOGIC;
  signal \gen_mux_rd[3].mux_rd_fall3_r1_reg\ : STD_LOGIC;
  signal \gen_mux_rd[3].mux_rd_rise0_r1_reg\ : STD_LOGIC;
  signal \gen_mux_rd[3].mux_rd_rise1_r1_reg\ : STD_LOGIC;
  signal \gen_mux_rd[3].mux_rd_rise2_r1_reg\ : STD_LOGIC;
  signal \gen_mux_rd[3].mux_rd_rise3_r1_reg\ : STD_LOGIC;
  signal \gen_mux_rd[4].mux_rd_fall0_r1_reg\ : STD_LOGIC;
  signal \gen_mux_rd[4].mux_rd_fall1_r1_reg\ : STD_LOGIC;
  signal \gen_mux_rd[4].mux_rd_fall2_r1_reg\ : STD_LOGIC;
  signal \gen_mux_rd[4].mux_rd_fall3_r1_reg\ : STD_LOGIC;
  signal \gen_mux_rd[4].mux_rd_rise0_r1_reg\ : STD_LOGIC;
  signal \gen_mux_rd[4].mux_rd_rise1_r1_reg\ : STD_LOGIC;
  signal \gen_mux_rd[4].mux_rd_rise2_r1_reg\ : STD_LOGIC;
  signal \gen_mux_rd[4].mux_rd_rise3_r1_reg\ : STD_LOGIC;
  signal \gen_mux_rd[5].mux_rd_fall0_r1_reg\ : STD_LOGIC;
  signal \gen_mux_rd[5].mux_rd_fall1_r1_reg\ : STD_LOGIC;
  signal \gen_mux_rd[5].mux_rd_fall2_r1_reg\ : STD_LOGIC;
  signal \gen_mux_rd[5].mux_rd_fall3_r1_reg\ : STD_LOGIC;
  signal \gen_mux_rd[5].mux_rd_rise0_r1_reg\ : STD_LOGIC;
  signal \gen_mux_rd[5].mux_rd_rise1_r1_reg\ : STD_LOGIC;
  signal \gen_mux_rd[5].mux_rd_rise2_r1_reg\ : STD_LOGIC;
  signal \gen_mux_rd[5].mux_rd_rise3_r1_reg\ : STD_LOGIC;
  signal \gen_mux_rd[6].mux_rd_fall0_r1_reg\ : STD_LOGIC;
  signal \gen_mux_rd[6].mux_rd_fall1_r1_reg\ : STD_LOGIC;
  signal \gen_mux_rd[6].mux_rd_fall2_r1_reg\ : STD_LOGIC;
  signal \gen_mux_rd[6].mux_rd_fall3_r1_reg\ : STD_LOGIC;
  signal \gen_mux_rd[6].mux_rd_rise0_r1_reg\ : STD_LOGIC;
  signal \gen_mux_rd[6].mux_rd_rise1_r1_reg\ : STD_LOGIC;
  signal \gen_mux_rd[6].mux_rd_rise2_r1_reg\ : STD_LOGIC;
  signal \gen_mux_rd[6].mux_rd_rise3_r1_reg\ : STD_LOGIC;
  signal \gen_mux_rd[7].mux_rd_fall0_r1_reg\ : STD_LOGIC;
  signal \gen_mux_rd[7].mux_rd_fall1_r1_reg\ : STD_LOGIC;
  signal \gen_mux_rd[7].mux_rd_fall2_r1_reg\ : STD_LOGIC;
  signal \gen_mux_rd[7].mux_rd_fall3_r1_reg\ : STD_LOGIC;
  signal \gen_mux_rd[7].mux_rd_rise0_r1_reg\ : STD_LOGIC;
  signal \gen_mux_rd[7].mux_rd_rise1_r1_reg\ : STD_LOGIC;
  signal \gen_mux_rd[7].mux_rd_rise2_r1_reg\ : STD_LOGIC;
  signal \gen_mux_rd[7].mux_rd_rise3_r1_reg\ : STD_LOGIC;
  signal \genblk7[0].compare_err_pb_latch_r[0]_i_1_n_0\ : STD_LOGIC;
  signal \genblk7[0].compare_err_pb_latch_r[0]_i_2_n_0\ : STD_LOGIC;
  signal \genblk7[0].compare_err_pb_latch_r_reg_n_0_[0]\ : STD_LOGIC;
  signal \genblk7[1].compare_err_pb_latch_r[1]_i_1_n_0\ : STD_LOGIC;
  signal \genblk7[1].compare_err_pb_latch_r_reg_n_0_[1]\ : STD_LOGIC;
  signal \genblk7[2].compare_err_pb_latch_r[2]_i_1_n_0\ : STD_LOGIC;
  signal \genblk7[2].compare_err_pb_latch_r_reg_n_0_[2]\ : STD_LOGIC;
  signal \genblk7[3].compare_err_pb_latch_r[3]_i_1_n_0\ : STD_LOGIC;
  signal \genblk7[3].compare_err_pb_latch_r_reg_n_0_[3]\ : STD_LOGIC;
  signal \genblk7[4].compare_err_pb_latch_r[4]_i_1_n_0\ : STD_LOGIC;
  signal \genblk7[4].compare_err_pb_latch_r_reg_n_0_[4]\ : STD_LOGIC;
  signal \genblk7[5].compare_err_pb_latch_r[5]_i_1_n_0\ : STD_LOGIC;
  signal \genblk7[5].compare_err_pb_latch_r_reg_n_0_[5]\ : STD_LOGIC;
  signal \genblk7[6].compare_err_pb_latch_r[6]_i_1_n_0\ : STD_LOGIC;
  signal \genblk7[6].compare_err_pb_latch_r_reg_n_0_[6]\ : STD_LOGIC;
  signal \genblk7[7].compare_err_pb_latch_r[7]_i_1_n_0\ : STD_LOGIC;
  signal \genblk7[7].compare_err_pb_latch_r_reg_n_0_[7]\ : STD_LOGIC;
  signal \genblk8[0].left_edge_updated[0]_i_1_n_0\ : STD_LOGIC;
  signal \genblk8[0].left_edge_updated[0]_i_2_n_0\ : STD_LOGIC;
  signal \genblk8[0].match_flag_pb[7]_i_1_n_0\ : STD_LOGIC;
  signal \genblk8[0].right_edge_found_pb[0]_i_1_n_0\ : STD_LOGIC;
  signal \genblk8[0].right_edge_found_pb[0]_i_2_n_0\ : STD_LOGIC;
  signal \genblk8[0].right_edge_found_pb[0]_i_3_n_0\ : STD_LOGIC;
  signal \genblk8[0].right_edge_found_pb[0]_i_4_n_0\ : STD_LOGIC;
  signal \genblk8[0].right_edge_found_pb[0]_i_5_n_0\ : STD_LOGIC;
  signal \genblk8[0].right_edge_found_pb[0]_i_6_n_0\ : STD_LOGIC;
  signal \genblk8[0].right_edge_found_pb_reg_n_0_[0]\ : STD_LOGIC;
  signal \genblk8[1].left_edge_updated[1]_i_1_n_0\ : STD_LOGIC;
  signal \genblk8[1].right_edge_found_pb[1]_i_1_n_0\ : STD_LOGIC;
  signal \genblk8[1].right_edge_found_pb[1]_i_2_n_0\ : STD_LOGIC;
  signal \genblk8[1].right_edge_found_pb[1]_i_3_n_0\ : STD_LOGIC;
  signal \genblk8[1].right_edge_found_pb[1]_i_4_n_0\ : STD_LOGIC;
  signal \genblk8[1].right_edge_found_pb_reg_n_0_[1]\ : STD_LOGIC;
  signal \genblk8[2].left_edge_updated[2]_i_1_n_0\ : STD_LOGIC;
  signal \genblk8[2].right_edge_found_pb[2]_i_1_n_0\ : STD_LOGIC;
  signal \genblk8[2].right_edge_found_pb[2]_i_2_n_0\ : STD_LOGIC;
  signal \genblk8[2].right_edge_found_pb[2]_i_3_n_0\ : STD_LOGIC;
  signal \genblk8[2].right_edge_found_pb[2]_i_4_n_0\ : STD_LOGIC;
  signal \genblk8[2].right_edge_found_pb_reg_n_0_[2]\ : STD_LOGIC;
  signal \genblk8[3].left_edge_updated[3]_i_1_n_0\ : STD_LOGIC;
  signal \genblk8[3].left_edge_updated[3]_i_2_n_0\ : STD_LOGIC;
  signal \genblk8[3].right_edge_found_pb[3]_i_1_n_0\ : STD_LOGIC;
  signal \genblk8[3].right_edge_found_pb[3]_i_2_n_0\ : STD_LOGIC;
  signal \genblk8[3].right_edge_found_pb[3]_i_3_n_0\ : STD_LOGIC;
  signal \genblk8[3].right_edge_found_pb[3]_i_4_n_0\ : STD_LOGIC;
  signal \genblk8[3].right_edge_found_pb[3]_i_5_n_0\ : STD_LOGIC;
  signal \genblk8[3].right_edge_found_pb_reg_n_0_[3]\ : STD_LOGIC;
  signal \genblk8[4].left_edge_updated[4]_i_1_n_0\ : STD_LOGIC;
  signal \genblk8[4].left_edge_updated[4]_i_2_n_0\ : STD_LOGIC;
  signal \genblk8[4].right_edge_found_pb[4]_i_1_n_0\ : STD_LOGIC;
  signal \genblk8[4].right_edge_found_pb[4]_i_2_n_0\ : STD_LOGIC;
  signal \genblk8[4].right_edge_found_pb[4]_i_3_n_0\ : STD_LOGIC;
  signal \genblk8[4].right_edge_found_pb[4]_i_4_n_0\ : STD_LOGIC;
  signal \genblk8[4].right_edge_found_pb[4]_i_5_n_0\ : STD_LOGIC;
  signal \genblk8[4].right_edge_found_pb_reg_n_0_[4]\ : STD_LOGIC;
  signal \genblk8[5].left_edge_updated[5]_i_1_n_0\ : STD_LOGIC;
  signal \genblk8[5].left_edge_updated[5]_i_2_n_0\ : STD_LOGIC;
  signal \genblk8[5].right_edge_found_pb[5]_i_1_n_0\ : STD_LOGIC;
  signal \genblk8[5].right_edge_found_pb[5]_i_2_n_0\ : STD_LOGIC;
  signal \genblk8[5].right_edge_found_pb[5]_i_3_n_0\ : STD_LOGIC;
  signal \genblk8[5].right_edge_found_pb[5]_i_4_n_0\ : STD_LOGIC;
  signal \genblk8[5].right_edge_found_pb[5]_i_5_n_0\ : STD_LOGIC;
  signal \genblk8[5].right_edge_found_pb_reg_n_0_[5]\ : STD_LOGIC;
  signal \genblk8[6].left_edge_updated[6]_i_1_n_0\ : STD_LOGIC;
  signal \genblk8[6].left_edge_updated[6]_i_2_n_0\ : STD_LOGIC;
  signal \genblk8[6].right_edge_found_pb[6]_i_1_n_0\ : STD_LOGIC;
  signal \genblk8[6].right_edge_found_pb[6]_i_2_n_0\ : STD_LOGIC;
  signal \genblk8[6].right_edge_found_pb[6]_i_3_n_0\ : STD_LOGIC;
  signal \genblk8[6].right_edge_found_pb[6]_i_4_n_0\ : STD_LOGIC;
  signal \genblk8[6].right_edge_found_pb[6]_i_5_n_0\ : STD_LOGIC;
  signal \genblk8[6].right_edge_found_pb_reg_n_0_[6]\ : STD_LOGIC;
  signal \genblk8[7].left_edge_updated[7]_i_1_n_0\ : STD_LOGIC;
  signal \genblk8[7].right_edge_found_pb[7]_i_1_n_0\ : STD_LOGIC;
  signal \genblk8[7].right_edge_found_pb[7]_i_2_n_0\ : STD_LOGIC;
  signal \genblk8[7].right_edge_found_pb[7]_i_3_n_0\ : STD_LOGIC;
  signal \genblk8[7].right_edge_found_pb[7]_i_4_n_0\ : STD_LOGIC;
  signal \genblk8[7].right_edge_found_pb_reg_n_0_[7]\ : STD_LOGIC;
  signal \largest_left_edge[0]_i_1_n_0\ : STD_LOGIC;
  signal \largest_left_edge[1]_i_1_n_0\ : STD_LOGIC;
  signal \largest_left_edge[2]_i_1_n_0\ : STD_LOGIC;
  signal \largest_left_edge[3]_i_1_n_0\ : STD_LOGIC;
  signal \largest_left_edge[4]_i_1_n_0\ : STD_LOGIC;
  signal \largest_left_edge[5]_i_1_n_0\ : STD_LOGIC;
  signal \largest_left_edge[5]_i_2_n_0\ : STD_LOGIC;
  signal \largest_left_edge[5]_i_3_n_0\ : STD_LOGIC;
  signal \largest_left_edge[5]_i_4_n_0\ : STD_LOGIC;
  signal \largest_left_edge[5]_i_5_n_0\ : STD_LOGIC;
  signal \largest_left_edge_reg_n_0_[0]\ : STD_LOGIC;
  signal \largest_left_edge_reg_n_0_[1]\ : STD_LOGIC;
  signal \largest_left_edge_reg_n_0_[2]\ : STD_LOGIC;
  signal \largest_left_edge_reg_n_0_[3]\ : STD_LOGIC;
  signal \largest_left_edge_reg_n_0_[4]\ : STD_LOGIC;
  signal \largest_left_edge_reg_n_0_[5]\ : STD_LOGIC;
  signal left_edge_found_pb85_out : STD_LOGIC;
  signal left_edge_updated : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal match_flag_and : STD_LOGIC;
  signal \match_flag_and[0]_i_1_n_0\ : STD_LOGIC;
  signal \match_flag_and[1]_i_1_n_0\ : STD_LOGIC;
  signal \match_flag_and[2]_i_1_n_0\ : STD_LOGIC;
  signal \match_flag_and[3]_i_1_n_0\ : STD_LOGIC;
  signal \match_flag_and[4]_i_1_n_0\ : STD_LOGIC;
  signal \match_flag_and[5]_i_1_n_0\ : STD_LOGIC;
  signal \match_flag_and[6]_i_1_n_0\ : STD_LOGIC;
  signal \match_flag_and[7]_i_2_n_0\ : STD_LOGIC;
  signal \match_flag_and_reg_n_0_[0]\ : STD_LOGIC;
  signal \match_flag_and_reg_n_0_[1]\ : STD_LOGIC;
  signal \match_flag_and_reg_n_0_[2]\ : STD_LOGIC;
  signal \match_flag_and_reg_n_0_[3]\ : STD_LOGIC;
  signal \match_flag_and_reg_n_0_[4]\ : STD_LOGIC;
  signal \match_flag_and_reg_n_0_[5]\ : STD_LOGIC;
  signal \match_flag_and_reg_n_0_[6]\ : STD_LOGIC;
  signal \match_flag_and_reg_n_0_[7]\ : STD_LOGIC;
  signal \match_flag_or[0]_i_1_n_0\ : STD_LOGIC;
  signal \match_flag_or[1]_i_1_n_0\ : STD_LOGIC;
  signal \match_flag_or[2]_i_1_n_0\ : STD_LOGIC;
  signal \match_flag_or[3]_i_1_n_0\ : STD_LOGIC;
  signal \match_flag_or[4]_i_1_n_0\ : STD_LOGIC;
  signal \match_flag_or[5]_i_1_n_0\ : STD_LOGIC;
  signal \match_flag_or[6]_i_1_n_0\ : STD_LOGIC;
  signal match_flag_pb : STD_LOGIC_VECTOR ( 63 downto 0 );
  signal mux_rd_fall0_r1 : STD_LOGIC;
  signal mux_rd_fall0_r2 : STD_LOGIC;
  signal mux_rd_fall1_r1 : STD_LOGIC;
  signal mux_rd_fall1_r2 : STD_LOGIC;
  signal mux_rd_fall2_r1 : STD_LOGIC;
  signal mux_rd_fall2_r2 : STD_LOGIC;
  signal mux_rd_fall3_r1 : STD_LOGIC;
  signal mux_rd_fall3_r2 : STD_LOGIC;
  signal mux_rd_rise0_r1 : STD_LOGIC;
  signal mux_rd_rise0_r2 : STD_LOGIC;
  signal mux_rd_rise1_r1 : STD_LOGIC;
  signal mux_rd_rise1_r2 : STD_LOGIC;
  signal mux_rd_rise2_r1 : STD_LOGIC;
  signal mux_rd_rise2_r2 : STD_LOGIC;
  signal mux_rd_rise3_r1 : STD_LOGIC;
  signal mux_rd_rise3_r2 : STD_LOGIC;
  signal mux_rd_valid_r : STD_LOGIC;
  signal new_cnt_dqs_r_i_1_n_0 : STD_LOGIC;
  signal new_cnt_dqs_r_i_3_n_0 : STD_LOGIC;
  signal new_cnt_dqs_r_i_4_n_0 : STD_LOGIC;
  signal \^new_cnt_dqs_r_reg_0\ : STD_LOGIC;
  signal no_err_win_detected_i_1_n_0 : STD_LOGIC;
  signal no_err_win_detected_i_2_n_0 : STD_LOGIC;
  signal no_err_win_detected_latch_i_1_n_0 : STD_LOGIC;
  signal no_err_win_detected_latch_i_2_n_0 : STD_LOGIC;
  signal no_err_win_detected_latch_i_3_n_0 : STD_LOGIC;
  signal no_err_win_detected_latch_reg_n_0 : STD_LOGIC;
  signal no_err_win_detected_reg_n_0 : STD_LOGIC;
  signal num_samples_done_ind_i_1_n_0 : STD_LOGIC;
  signal num_samples_done_ind_reg_n_0 : STD_LOGIC;
  signal \^num_samples_done_r\ : STD_LOGIC;
  signal p_0_in : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal p_0_in166_in : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal p_0_in169_in : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal p_0_in172_in : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal p_0_in175_in : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal p_0_in178_in : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal p_0_in181_in : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal p_0_in184_in : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal p_0_in187_in : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \p_0_in__0\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal p_10_out : STD_LOGIC;
  signal p_154_out : STD_LOGIC;
  signal p_19_out : STD_LOGIC;
  signal p_1_in167_in : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal p_1_in170_in : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal p_1_in173_in : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal p_1_in176_in : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal p_1_in179_in : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal p_1_in182_in : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal p_1_in185_in : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal p_1_in188_in : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal p_28_out : STD_LOGIC;
  signal p_37_out : STD_LOGIC;
  signal p_46_out : STD_LOGIC;
  signal p_55_out : STD_LOGIC;
  signal p_64_out : STD_LOGIC;
  signal p_66_out : STD_LOGIC;
  signal p_75_out : STD_LOGIC;
  signal pi_en_stg2_f_timing : STD_LOGIC;
  signal pi_stg2_f_incdec_timing : STD_LOGIC;
  signal \pi_stg2_f_incdec_timing_i_1__0_n_0\ : STD_LOGIC;
  signal \prbs_1st_edge_taps_r[1]_i_1_n_0\ : STD_LOGIC;
  signal \prbs_1st_edge_taps_r[2]_i_1_n_0\ : STD_LOGIC;
  signal \prbs_1st_edge_taps_r[3]_i_1_n_0\ : STD_LOGIC;
  signal \prbs_1st_edge_taps_r[4]_i_1_n_0\ : STD_LOGIC;
  signal \prbs_1st_edge_taps_r[5]_i_1_n_0\ : STD_LOGIC;
  signal \prbs_1st_edge_taps_r[5]_i_2_n_0\ : STD_LOGIC;
  signal \prbs_1st_edge_taps_r[5]_i_3_n_0\ : STD_LOGIC;
  signal \prbs_1st_edge_taps_r_reg_n_0_[0]\ : STD_LOGIC;
  signal \prbs_1st_edge_taps_r_reg_n_0_[1]\ : STD_LOGIC;
  signal \prbs_1st_edge_taps_r_reg_n_0_[2]\ : STD_LOGIC;
  signal \prbs_1st_edge_taps_r_reg_n_0_[3]\ : STD_LOGIC;
  signal \prbs_1st_edge_taps_r_reg_n_0_[4]\ : STD_LOGIC;
  signal \prbs_1st_edge_taps_r_reg_n_0_[5]\ : STD_LOGIC;
  signal prbs_2nd_edge_taps_r : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal \prbs_2nd_edge_taps_r[0]_i_1_n_0\ : STD_LOGIC;
  signal \prbs_2nd_edge_taps_r[1]_i_1_n_0\ : STD_LOGIC;
  signal \prbs_2nd_edge_taps_r[2]_i_1_n_0\ : STD_LOGIC;
  signal \prbs_2nd_edge_taps_r[3]_i_1_n_0\ : STD_LOGIC;
  signal \prbs_2nd_edge_taps_r[4]_i_1_n_0\ : STD_LOGIC;
  signal \prbs_2nd_edge_taps_r[5]_i_1_n_0\ : STD_LOGIC;
  signal \prbs_2nd_edge_taps_r[5]_i_2_n_0\ : STD_LOGIC;
  signal \prbs_2nd_edge_taps_r[5]_i_3_n_0\ : STD_LOGIC;
  signal \prbs_2nd_edge_taps_r[5]_i_4_n_0\ : STD_LOGIC;
  signal \prbs_2nd_edge_taps_r[5]_i_5_n_0\ : STD_LOGIC;
  signal prbs_dec_tap_cnt : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal prbs_dec_tap_cnt10_out : STD_LOGIC_VECTOR ( 5 downto 1 );
  signal prbs_dec_tap_cnt2 : STD_LOGIC_VECTOR ( 5 downto 1 );
  signal \prbs_dec_tap_cnt[0]_i_1_n_0\ : STD_LOGIC;
  signal \prbs_dec_tap_cnt[0]_i_2_n_0\ : STD_LOGIC;
  signal \prbs_dec_tap_cnt[1]_i_1_n_0\ : STD_LOGIC;
  signal \prbs_dec_tap_cnt[1]_i_2_n_0\ : STD_LOGIC;
  signal \prbs_dec_tap_cnt[2]_i_1_n_0\ : STD_LOGIC;
  signal \prbs_dec_tap_cnt[2]_i_2_n_0\ : STD_LOGIC;
  signal \prbs_dec_tap_cnt[2]_i_3_n_0\ : STD_LOGIC;
  signal \prbs_dec_tap_cnt[2]_i_5_n_0\ : STD_LOGIC;
  signal \prbs_dec_tap_cnt[2]_i_6_n_0\ : STD_LOGIC;
  signal \prbs_dec_tap_cnt[2]_i_7_n_0\ : STD_LOGIC;
  signal \prbs_dec_tap_cnt[2]_i_8_n_0\ : STD_LOGIC;
  signal \prbs_dec_tap_cnt[3]_i_1_n_0\ : STD_LOGIC;
  signal \prbs_dec_tap_cnt[3]_i_2_n_0\ : STD_LOGIC;
  signal \prbs_dec_tap_cnt[3]_i_3_n_0\ : STD_LOGIC;
  signal \prbs_dec_tap_cnt[3]_i_4_n_0\ : STD_LOGIC;
  signal \prbs_dec_tap_cnt[4]_i_1_n_0\ : STD_LOGIC;
  signal \prbs_dec_tap_cnt[4]_i_2_n_0\ : STD_LOGIC;
  signal \prbs_dec_tap_cnt[4]_i_3_n_0\ : STD_LOGIC;
  signal \prbs_dec_tap_cnt[4]_i_4_n_0\ : STD_LOGIC;
  signal \prbs_dec_tap_cnt[4]_i_6_n_0\ : STD_LOGIC;
  signal \prbs_dec_tap_cnt[4]_i_7_n_0\ : STD_LOGIC;
  signal \prbs_dec_tap_cnt[5]_i_10_n_0\ : STD_LOGIC;
  signal \prbs_dec_tap_cnt[5]_i_11_n_0\ : STD_LOGIC;
  signal \prbs_dec_tap_cnt[5]_i_12_n_0\ : STD_LOGIC;
  signal \prbs_dec_tap_cnt[5]_i_13_n_0\ : STD_LOGIC;
  signal \prbs_dec_tap_cnt[5]_i_1_n_0\ : STD_LOGIC;
  signal \prbs_dec_tap_cnt[5]_i_2_n_0\ : STD_LOGIC;
  signal \prbs_dec_tap_cnt[5]_i_3_n_0\ : STD_LOGIC;
  signal \prbs_dec_tap_cnt[5]_i_4_n_0\ : STD_LOGIC;
  signal \prbs_dec_tap_cnt[5]_i_5_n_0\ : STD_LOGIC;
  signal \prbs_dec_tap_cnt[5]_i_8_n_0\ : STD_LOGIC;
  signal \prbs_dec_tap_cnt[5]_i_9_n_0\ : STD_LOGIC;
  signal \prbs_dec_tap_cnt_reg[2]_i_4_n_0\ : STD_LOGIC;
  signal \prbs_dec_tap_cnt_reg[2]_i_4_n_1\ : STD_LOGIC;
  signal \prbs_dec_tap_cnt_reg[2]_i_4_n_2\ : STD_LOGIC;
  signal \prbs_dec_tap_cnt_reg[2]_i_4_n_3\ : STD_LOGIC;
  signal \prbs_dec_tap_cnt_reg[4]_i_5_n_3\ : STD_LOGIC;
  signal \prbs_dec_tap_cnt_reg[5]_i_6_n_1\ : STD_LOGIC;
  signal \prbs_dec_tap_cnt_reg[5]_i_6_n_3\ : STD_LOGIC;
  signal \prbs_dec_tap_cnt_reg[5]_i_7_n_0\ : STD_LOGIC;
  signal \prbs_dec_tap_cnt_reg[5]_i_7_n_1\ : STD_LOGIC;
  signal \prbs_dec_tap_cnt_reg[5]_i_7_n_2\ : STD_LOGIC;
  signal \prbs_dec_tap_cnt_reg[5]_i_7_n_3\ : STD_LOGIC;
  signal \prbs_dqs_cnt_r[0]_i_1_n_0\ : STD_LOGIC;
  signal \prbs_dqs_cnt_r[1]_i_1_n_0\ : STD_LOGIC;
  signal \prbs_dqs_cnt_r[2]_i_1_n_0\ : STD_LOGIC;
  signal \prbs_dqs_cnt_r[3]_i_1_n_0\ : STD_LOGIC;
  signal \prbs_dqs_cnt_r[3]_i_2_n_0\ : STD_LOGIC;
  signal \prbs_dqs_cnt_r[3]_i_3_n_0\ : STD_LOGIC;
  signal \prbs_dqs_cnt_r[3]_i_4_n_0\ : STD_LOGIC;
  signal \prbs_dqs_cnt_r_reg_n_0_[0]\ : STD_LOGIC;
  signal \prbs_dqs_cnt_r_reg_n_0_[1]\ : STD_LOGIC;
  signal \prbs_dqs_cnt_r_reg_n_0_[2]\ : STD_LOGIC;
  signal \prbs_dqs_cnt_r_reg_n_0_[3]\ : STD_LOGIC;
  signal \prbs_dqs_tap_cnt_r[0]_i_1_n_0\ : STD_LOGIC;
  signal \prbs_dqs_tap_cnt_r[1]_i_1_n_0\ : STD_LOGIC;
  signal \prbs_dqs_tap_cnt_r[2]_i_1_n_0\ : STD_LOGIC;
  signal \prbs_dqs_tap_cnt_r[3]_i_1_n_0\ : STD_LOGIC;
  signal \prbs_dqs_tap_cnt_r[3]_i_2_n_0\ : STD_LOGIC;
  signal \prbs_dqs_tap_cnt_r[4]_i_1_n_0\ : STD_LOGIC;
  signal \prbs_dqs_tap_cnt_r[4]_i_2_n_0\ : STD_LOGIC;
  signal \prbs_dqs_tap_cnt_r[5]_i_1_n_0\ : STD_LOGIC;
  signal \prbs_dqs_tap_cnt_r[5]_i_2_n_0\ : STD_LOGIC;
  signal \prbs_dqs_tap_cnt_r[5]_i_3_n_0\ : STD_LOGIC;
  signal \prbs_dqs_tap_cnt_r[5]_i_4_n_0\ : STD_LOGIC;
  signal \prbs_dqs_tap_cnt_r_reg_n_0_[0]\ : STD_LOGIC;
  signal \prbs_dqs_tap_cnt_r_reg_n_0_[1]\ : STD_LOGIC;
  signal \prbs_dqs_tap_cnt_r_reg_n_0_[2]\ : STD_LOGIC;
  signal \prbs_dqs_tap_cnt_r_reg_n_0_[3]\ : STD_LOGIC;
  signal \prbs_dqs_tap_cnt_r_reg_n_0_[4]\ : STD_LOGIC;
  signal \prbs_dqs_tap_cnt_r_reg_n_0_[5]\ : STD_LOGIC;
  signal prbs_dqs_tap_limit_r : STD_LOGIC;
  signal prbs_dqs_tap_limit_r_i_1_n_0 : STD_LOGIC;
  signal prbs_dqs_tap_limit_r_i_2_n_0 : STD_LOGIC;
  signal prbs_found_1st_edge_r_i_1_n_0 : STD_LOGIC;
  signal prbs_found_1st_edge_r_reg_n_0 : STD_LOGIC;
  signal prbs_found_2nd_edge_r_i_1_n_0 : STD_LOGIC;
  signal prbs_found_2nd_edge_r_reg_n_0 : STD_LOGIC;
  signal prbs_inc_tap_cnt : STD_LOGIC;
  signal \prbs_inc_tap_cnt[0]_i_1_n_0\ : STD_LOGIC;
  signal \prbs_inc_tap_cnt[1]_i_1_n_0\ : STD_LOGIC;
  signal \prbs_inc_tap_cnt[1]_i_2_n_0\ : STD_LOGIC;
  signal \prbs_inc_tap_cnt[2]_i_1_n_0\ : STD_LOGIC;
  signal \prbs_inc_tap_cnt[2]_i_2_n_0\ : STD_LOGIC;
  signal \prbs_inc_tap_cnt[2]_i_3_n_0\ : STD_LOGIC;
  signal \prbs_inc_tap_cnt[3]_i_1_n_0\ : STD_LOGIC;
  signal \prbs_inc_tap_cnt[3]_i_2_n_0\ : STD_LOGIC;
  signal \prbs_inc_tap_cnt[3]_i_3_n_0\ : STD_LOGIC;
  signal \prbs_inc_tap_cnt[4]_i_1_n_0\ : STD_LOGIC;
  signal \prbs_inc_tap_cnt[5]_i_10_n_0\ : STD_LOGIC;
  signal \prbs_inc_tap_cnt[5]_i_11_n_0\ : STD_LOGIC;
  signal \prbs_inc_tap_cnt[5]_i_12_n_0\ : STD_LOGIC;
  signal \prbs_inc_tap_cnt[5]_i_2_n_0\ : STD_LOGIC;
  signal \prbs_inc_tap_cnt[5]_i_3_n_0\ : STD_LOGIC;
  signal \prbs_inc_tap_cnt[5]_i_4_n_0\ : STD_LOGIC;
  signal \prbs_inc_tap_cnt[5]_i_5_n_0\ : STD_LOGIC;
  signal \prbs_inc_tap_cnt[5]_i_6_n_0\ : STD_LOGIC;
  signal \prbs_inc_tap_cnt[5]_i_7_n_0\ : STD_LOGIC;
  signal \prbs_inc_tap_cnt[5]_i_8_n_0\ : STD_LOGIC;
  signal \prbs_inc_tap_cnt[5]_i_9_n_0\ : STD_LOGIC;
  signal \prbs_inc_tap_cnt_reg_n_0_[0]\ : STD_LOGIC;
  signal \prbs_inc_tap_cnt_reg_n_0_[1]\ : STD_LOGIC;
  signal \prbs_inc_tap_cnt_reg_n_0_[2]\ : STD_LOGIC;
  signal \prbs_inc_tap_cnt_reg_n_0_[3]\ : STD_LOGIC;
  signal \prbs_inc_tap_cnt_reg_n_0_[4]\ : STD_LOGIC;
  signal \prbs_inc_tap_cnt_reg_n_0_[5]\ : STD_LOGIC;
  signal \^prbs_last_byte_done\ : STD_LOGIC;
  signal prbs_last_byte_done_i_1_n_0 : STD_LOGIC;
  signal prbs_last_byte_done_i_2_n_0 : STD_LOGIC;
  signal prbs_prech_req_r : STD_LOGIC;
  signal prbs_prech_req_r_i_1_n_0 : STD_LOGIC;
  signal prbs_rdlvl_done_i_1_n_0 : STD_LOGIC;
  signal \^prbs_rdlvl_done_reg_0\ : STD_LOGIC;
  signal \^prbs_rdlvl_start_r\ : STD_LOGIC;
  signal prbs_state_r : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal \prbs_state_r[0]_i_1_n_0\ : STD_LOGIC;
  signal \prbs_state_r[0]_i_2_n_0\ : STD_LOGIC;
  signal \prbs_state_r[0]_i_3_n_0\ : STD_LOGIC;
  signal \prbs_state_r[0]_i_4_n_0\ : STD_LOGIC;
  signal \prbs_state_r[0]_i_5_n_0\ : STD_LOGIC;
  signal \prbs_state_r[1]_i_1_n_0\ : STD_LOGIC;
  signal \prbs_state_r[1]_i_2_n_0\ : STD_LOGIC;
  signal \prbs_state_r[1]_i_3_n_0\ : STD_LOGIC;
  signal \prbs_state_r[1]_i_4_n_0\ : STD_LOGIC;
  signal \prbs_state_r[1]_i_5_n_0\ : STD_LOGIC;
  signal \prbs_state_r[1]_i_6_n_0\ : STD_LOGIC;
  signal \prbs_state_r[2]_i_1_n_0\ : STD_LOGIC;
  signal \prbs_state_r[2]_i_2_n_0\ : STD_LOGIC;
  signal \prbs_state_r[2]_i_3_n_0\ : STD_LOGIC;
  signal \prbs_state_r[2]_i_4_n_0\ : STD_LOGIC;
  signal \prbs_state_r[2]_i_5_n_0\ : STD_LOGIC;
  signal \prbs_state_r[3]_i_1_n_0\ : STD_LOGIC;
  signal \prbs_state_r[3]_i_2_n_0\ : STD_LOGIC;
  signal \prbs_state_r[3]_i_3_n_0\ : STD_LOGIC;
  signal \prbs_state_r[3]_i_4_n_0\ : STD_LOGIC;
  signal \prbs_state_r[3]_i_5_n_0\ : STD_LOGIC;
  signal \prbs_state_r[3]_i_6_n_0\ : STD_LOGIC;
  signal \prbs_state_r[4]_i_10_n_0\ : STD_LOGIC;
  signal \prbs_state_r[4]_i_11_n_0\ : STD_LOGIC;
  signal \prbs_state_r[4]_i_12_n_0\ : STD_LOGIC;
  signal \prbs_state_r[4]_i_1_n_0\ : STD_LOGIC;
  signal \prbs_state_r[4]_i_2_n_0\ : STD_LOGIC;
  signal \prbs_state_r[4]_i_3_n_0\ : STD_LOGIC;
  signal \prbs_state_r[4]_i_4_n_0\ : STD_LOGIC;
  signal \prbs_state_r[4]_i_5_n_0\ : STD_LOGIC;
  signal \prbs_state_r[4]_i_6_n_0\ : STD_LOGIC;
  signal \prbs_state_r[4]_i_7_n_0\ : STD_LOGIC;
  signal \prbs_state_r[4]_i_8_n_0\ : STD_LOGIC;
  signal \prbs_state_r[4]_i_9_n_0\ : STD_LOGIC;
  signal prbs_tap_en_r : STD_LOGIC;
  signal prbs_tap_en_r_i_1_n_0 : STD_LOGIC;
  signal prbs_tap_en_r_reg_n_0 : STD_LOGIC;
  signal prbs_tap_inc_r : STD_LOGIC;
  signal prbs_tap_inc_r_i_1_n_0 : STD_LOGIC;
  signal prbs_tap_inc_r_i_3_n_0 : STD_LOGIC;
  signal prbs_tap_inc_r_i_4_n_0 : STD_LOGIC;
  signal rd_valid_r1 : STD_LOGIC;
  signal rd_valid_r2_reg_n_0 : STD_LOGIC;
  signal \rd_victim_sel[0]_i_1_n_0\ : STD_LOGIC;
  signal \rd_victim_sel[1]_i_1_n_0\ : STD_LOGIC;
  signal \rd_victim_sel[2]_i_1_n_0\ : STD_LOGIC;
  signal \^rd_victim_sel_reg[0]_0\ : STD_LOGIC;
  signal \^rd_victim_sel_reg[1]_0\ : STD_LOGIC;
  signal \^rd_victim_sel_reg[2]_0\ : STD_LOGIC;
  signal rdlvl_cpt_tap_cnt : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal reset_if_i_2_n_0 : STD_LOGIC;
  signal \^reset_rd_addr\ : STD_LOGIC;
  signal reset_rd_addr_i_1_n_0 : STD_LOGIC;
  signal right_edge_found_i_1_n_0 : STD_LOGIC;
  signal right_edge_found_i_2_n_0 : STD_LOGIC;
  signal right_edge_found_i_3_n_0 : STD_LOGIC;
  signal right_edge_found_i_4_n_0 : STD_LOGIC;
  signal right_edge_found_i_5_n_0 : STD_LOGIC;
  signal right_edge_found_reg_n_0 : STD_LOGIC;
  signal \samples_cnt_r[0]_i_1_n_0\ : STD_LOGIC;
  signal \samples_cnt_r[0]_i_2_n_0\ : STD_LOGIC;
  signal \samples_cnt_r[0]_i_3_n_0\ : STD_LOGIC;
  signal \samples_cnt_r[10]_i_1_n_0\ : STD_LOGIC;
  signal \samples_cnt_r[11]_i_2_n_0\ : STD_LOGIC;
  signal \samples_cnt_r[1]_i_1_n_0\ : STD_LOGIC;
  signal \samples_cnt_r[2]_i_1_n_0\ : STD_LOGIC;
  signal \samples_cnt_r[3]_i_1_n_0\ : STD_LOGIC;
  signal \samples_cnt_r[4]_i_1_n_0\ : STD_LOGIC;
  signal \samples_cnt_r[5]_i_1_n_0\ : STD_LOGIC;
  signal \samples_cnt_r[6]_i_1_n_0\ : STD_LOGIC;
  signal \samples_cnt_r[7]_i_1_n_0\ : STD_LOGIC;
  signal \samples_cnt_r[8]_i_1_n_0\ : STD_LOGIC;
  signal \samples_cnt_r[9]_i_1_n_0\ : STD_LOGIC;
  signal \^samples_cnt_r_reg[11]_0\ : STD_LOGIC;
  signal \samples_cnt_r_reg[11]_i_4_n_2\ : STD_LOGIC;
  signal \samples_cnt_r_reg[11]_i_4_n_3\ : STD_LOGIC;
  signal \samples_cnt_r_reg[4]_i_2_n_0\ : STD_LOGIC;
  signal \samples_cnt_r_reg[4]_i_2_n_1\ : STD_LOGIC;
  signal \samples_cnt_r_reg[4]_i_2_n_2\ : STD_LOGIC;
  signal \samples_cnt_r_reg[4]_i_2_n_3\ : STD_LOGIC;
  signal \samples_cnt_r_reg[8]_i_2_n_0\ : STD_LOGIC;
  signal \samples_cnt_r_reg[8]_i_2_n_1\ : STD_LOGIC;
  signal \samples_cnt_r_reg[8]_i_2_n_2\ : STD_LOGIC;
  signal \samples_cnt_r_reg[8]_i_2_n_3\ : STD_LOGIC;
  signal \samples_cnt_r_reg_n_0_[0]\ : STD_LOGIC;
  signal \samples_cnt_r_reg_n_0_[10]\ : STD_LOGIC;
  signal \samples_cnt_r_reg_n_0_[11]\ : STD_LOGIC;
  signal \samples_cnt_r_reg_n_0_[1]\ : STD_LOGIC;
  signal \samples_cnt_r_reg_n_0_[2]\ : STD_LOGIC;
  signal \samples_cnt_r_reg_n_0_[3]\ : STD_LOGIC;
  signal \samples_cnt_r_reg_n_0_[4]\ : STD_LOGIC;
  signal \samples_cnt_r_reg_n_0_[5]\ : STD_LOGIC;
  signal \samples_cnt_r_reg_n_0_[6]\ : STD_LOGIC;
  signal \samples_cnt_r_reg_n_0_[7]\ : STD_LOGIC;
  signal \samples_cnt_r_reg_n_0_[8]\ : STD_LOGIC;
  signal \samples_cnt_r_reg_n_0_[9]\ : STD_LOGIC;
  signal sel0 : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal smallest_right_edge : STD_LOGIC;
  signal \smallest_right_edge[0]_i_1_n_0\ : STD_LOGIC;
  signal \smallest_right_edge[1]_i_1_n_0\ : STD_LOGIC;
  signal \smallest_right_edge[2]_i_1_n_0\ : STD_LOGIC;
  signal \smallest_right_edge[3]_i_1_n_0\ : STD_LOGIC;
  signal \smallest_right_edge[4]_i_1_n_0\ : STD_LOGIC;
  signal \smallest_right_edge[5]_i_10_n_0\ : STD_LOGIC;
  signal \smallest_right_edge[5]_i_2_n_0\ : STD_LOGIC;
  signal \smallest_right_edge[5]_i_3_n_0\ : STD_LOGIC;
  signal \smallest_right_edge[5]_i_4_n_0\ : STD_LOGIC;
  signal \smallest_right_edge[5]_i_5_n_0\ : STD_LOGIC;
  signal \smallest_right_edge[5]_i_6_n_0\ : STD_LOGIC;
  signal \smallest_right_edge[5]_i_7_n_0\ : STD_LOGIC;
  signal \smallest_right_edge[5]_i_8_n_0\ : STD_LOGIC;
  signal \smallest_right_edge[5]_i_9_n_0\ : STD_LOGIC;
  signal \smallest_right_edge_reg_n_0_[0]\ : STD_LOGIC;
  signal \smallest_right_edge_reg_n_0_[1]\ : STD_LOGIC;
  signal \smallest_right_edge_reg_n_0_[2]\ : STD_LOGIC;
  signal \smallest_right_edge_reg_n_0_[3]\ : STD_LOGIC;
  signal \smallest_right_edge_reg_n_0_[4]\ : STD_LOGIC;
  signal \smallest_right_edge_reg_n_0_[5]\ : STD_LOGIC;
  signal \stage_cnt[0]_i_1_n_0\ : STD_LOGIC;
  signal \stage_cnt[0]_i_2_n_0\ : STD_LOGIC;
  signal \stage_cnt[1]_i_1_n_0\ : STD_LOGIC;
  signal \stage_cnt[1]_i_2_n_0\ : STD_LOGIC;
  signal \stage_cnt_reg_n_0_[0]\ : STD_LOGIC;
  signal \stage_cnt_reg_n_0_[1]\ : STD_LOGIC;
  signal \victim_not_fixed.num_samples_done_r_i_1_n_0\ : STD_LOGIC;
  signal \victim_not_fixed.num_samples_done_r_i_2_n_0\ : STD_LOGIC;
  signal wait_state_cnt_en_r : STD_LOGIC;
  signal wait_state_cnt_en_r0 : STD_LOGIC;
  signal \wait_state_cnt_r[3]_i_1_n_0\ : STD_LOGIC;
  signal wait_state_cnt_r_reg : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \NLW_fine_pi_dec_cnt_reg[5]_i_10_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
  signal \NLW_fine_pi_dec_cnt_reg[5]_i_10_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
  signal \NLW_prbs_dec_tap_cnt_reg[2]_i_4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \NLW_prbs_dec_tap_cnt_reg[4]_i_5_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
  signal \NLW_prbs_dec_tap_cnt_reg[4]_i_5_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
  signal \NLW_prbs_dec_tap_cnt_reg[5]_i_6_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
  signal \NLW_prbs_dec_tap_cnt_reg[5]_i_6_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
  signal \NLW_prbs_dec_tap_cnt_reg[5]_i_7_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \NLW_samples_cnt_r_reg[11]_i_4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
  signal \NLW_samples_cnt_r_reg[11]_i_4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \bit_cnt[0]_i_1\ : label is "soft_lutpair78";
  attribute SOFT_HLUTNM of \bit_cnt[1]_i_1\ : label is "soft_lutpair78";
  attribute SOFT_HLUTNM of \bit_cnt[2]_i_1\ : label is "soft_lutpair71";
  attribute SOFT_HLUTNM of \bit_cnt[3]_i_1\ : label is "soft_lutpair71";
  attribute SOFT_HLUTNM of \bit_cnt[7]_i_3\ : label is "soft_lutpair14";
  attribute SOFT_HLUTNM of \cmp_err_pb_4to1.(null)[0].compare_err_pb[0]_i_3\ : label is "soft_lutpair41";
  attribute SOFT_HLUTNM of \cmp_err_pb_4to1.(null)[0].compare_err_pb[0]_i_4\ : label is "soft_lutpair54";
  attribute SOFT_HLUTNM of cnt_wait_state_i_1 : label is "soft_lutpair22";
  attribute SOFT_HLUTNM of compare_err_pb_and_i_2 : label is "soft_lutpair66";
  attribute SOFT_HLUTNM of compare_err_pb_and_i_3 : label is "soft_lutpair63";
  attribute SOFT_HLUTNM of compare_err_pb_or_i_2 : label is "soft_lutpair66";
  attribute SOFT_HLUTNM of compare_err_pb_or_i_3 : label is "soft_lutpair63";
  attribute SOFT_HLUTNM of complex_pi_incdec_done_i_3 : label is "soft_lutpair18";
  attribute SOFT_HLUTNM of complex_pi_incdec_done_i_7 : label is "soft_lutpair21";
  attribute SOFT_HLUTNM of edge_det_error_i_4 : label is "soft_lutpair28";
  attribute SOFT_HLUTNM of err_chk_invalid_i_1 : label is "soft_lutpair22";
  attribute SOFT_HLUTNM of \fine_pi_dec_cnt[0]_i_2\ : label is "soft_lutpair40";
  attribute SOFT_HLUTNM of \fine_pi_dec_cnt[0]_i_3\ : label is "soft_lutpair27";
  attribute SOFT_HLUTNM of \fine_pi_dec_cnt[1]_i_1\ : label is "soft_lutpair60";
  attribute SOFT_HLUTNM of \fine_pi_dec_cnt[1]_i_3\ : label is "soft_lutpair27";
  attribute SOFT_HLUTNM of \fine_pi_dec_cnt[2]_i_1\ : label is "soft_lutpair19";
  attribute SOFT_HLUTNM of \fine_pi_dec_cnt[3]_i_2\ : label is "soft_lutpair16";
  attribute SOFT_HLUTNM of \fine_pi_dec_cnt[3]_i_4\ : label is "soft_lutpair33";
  attribute SOFT_HLUTNM of \fine_pi_dec_cnt[3]_i_5\ : label is "soft_lutpair37";
  attribute SOFT_HLUTNM of \fine_pi_dec_cnt[3]_i_6\ : label is "soft_lutpair19";
  attribute SOFT_HLUTNM of \fine_pi_dec_cnt[4]_i_2\ : label is "soft_lutpair52";
  attribute SOFT_HLUTNM of \fine_pi_dec_cnt[4]_i_3\ : label is "soft_lutpair37";
  attribute SOFT_HLUTNM of \fine_pi_dec_cnt[5]_i_11\ : label is "soft_lutpair33";
  attribute SOFT_HLUTNM of \fine_pi_dec_cnt[5]_i_12\ : label is "soft_lutpair40";
  attribute SOFT_HLUTNM of \fine_pi_dec_cnt[5]_i_5\ : label is "soft_lutpair43";
  attribute SOFT_HLUTNM of \gen_byte_sel_div2.byte_sel_cnt[0]_i_2\ : label is "soft_lutpair34";
  attribute SOFT_HLUTNM of \genblk7[0].compare_err_pb_latch_r[0]_i_2\ : label is "soft_lutpair39";
  attribute SOFT_HLUTNM of \genblk7[3].compare_err_pb_latch_r[3]_i_1\ : label is "soft_lutpair47";
  attribute SOFT_HLUTNM of \genblk7[4].compare_err_pb_latch_r[4]_i_1\ : label is "soft_lutpair53";
  attribute SOFT_HLUTNM of \genblk7[5].compare_err_pb_latch_r[5]_i_1\ : label is "soft_lutpair61";
  attribute SOFT_HLUTNM of \genblk7[6].compare_err_pb_latch_r[6]_i_1\ : label is "soft_lutpair62";
  attribute SOFT_HLUTNM of \genblk8[0].right_edge_found_pb[0]_i_3\ : label is "soft_lutpair39";
  attribute SOFT_HLUTNM of \genblk8[0].right_edge_found_pb[0]_i_4\ : label is "soft_lutpair14";
  attribute SOFT_HLUTNM of \genblk8[2].right_edge_found_pb[2]_i_2\ : label is "soft_lutpair24";
  attribute SOFT_HLUTNM of \genblk8[2].right_edge_found_pb[2]_i_3\ : label is "soft_lutpair24";
  attribute SOFT_HLUTNM of \genblk8[3].right_edge_found_pb[3]_i_3\ : label is "soft_lutpair47";
  attribute SOFT_HLUTNM of \genblk8[4].right_edge_found_pb[4]_i_3\ : label is "soft_lutpair53";
  attribute SOFT_HLUTNM of \genblk8[5].right_edge_found_pb[5]_i_3\ : label is "soft_lutpair61";
  attribute SOFT_HLUTNM of \genblk8[6].right_edge_found_pb[6]_i_3\ : label is "soft_lutpair62";
  attribute SOFT_HLUTNM of \largest_left_edge[0]_i_1\ : label is "soft_lutpair70";
  attribute SOFT_HLUTNM of \largest_left_edge[1]_i_1\ : label is "soft_lutpair70";
  attribute SOFT_HLUTNM of \largest_left_edge[2]_i_1\ : label is "soft_lutpair65";
  attribute SOFT_HLUTNM of \largest_left_edge[3]_i_1\ : label is "soft_lutpair31";
  attribute SOFT_HLUTNM of \largest_left_edge[5]_i_2\ : label is "soft_lutpair46";
  attribute SOFT_HLUTNM of \largest_left_edge[5]_i_4\ : label is "soft_lutpair38";
  attribute SOFT_HLUTNM of \match_flag_and[6]_i_1\ : label is "soft_lutpair18";
  attribute SOFT_HLUTNM of new_cnt_dqs_r_i_4 : label is "soft_lutpair52";
  attribute SOFT_HLUTNM of \pi_stg2_f_incdec_timing_i_1__0\ : label is "soft_lutpair67";
  attribute SOFT_HLUTNM of \prbs_1st_edge_taps_r[1]_i_1\ : label is "soft_lutpair69";
  attribute SOFT_HLUTNM of \prbs_1st_edge_taps_r[2]_i_1\ : label is "soft_lutpair69";
  attribute SOFT_HLUTNM of \prbs_1st_edge_taps_r[3]_i_1\ : label is "soft_lutpair31";
  attribute SOFT_HLUTNM of \prbs_1st_edge_taps_r[4]_i_1\ : label is "soft_lutpair17";
  attribute SOFT_HLUTNM of \prbs_2nd_edge_taps_r[0]_i_1\ : label is "soft_lutpair36";
  attribute SOFT_HLUTNM of \prbs_2nd_edge_taps_r[1]_i_1\ : label is "soft_lutpair73";
  attribute SOFT_HLUTNM of \prbs_2nd_edge_taps_r[2]_i_1\ : label is "soft_lutpair73";
  attribute SOFT_HLUTNM of \prbs_2nd_edge_taps_r[3]_i_1\ : label is "soft_lutpair49";
  attribute SOFT_HLUTNM of \prbs_2nd_edge_taps_r[4]_i_1\ : label is "soft_lutpair17";
  attribute SOFT_HLUTNM of \prbs_2nd_edge_taps_r[5]_i_5\ : label is "soft_lutpair68";
  attribute SOFT_HLUTNM of \prbs_dec_tap_cnt[0]_i_1\ : label is "soft_lutpair59";
  attribute SOFT_HLUTNM of \prbs_dec_tap_cnt[1]_i_1\ : label is "soft_lutpair59";
  attribute SOFT_HLUTNM of \prbs_dec_tap_cnt[2]_i_1\ : label is "soft_lutpair29";
  attribute SOFT_HLUTNM of \prbs_dec_tap_cnt[3]_i_3\ : label is "soft_lutpair46";
  attribute SOFT_HLUTNM of \prbs_dec_tap_cnt[3]_i_4\ : label is "soft_lutpair45";
  attribute SOFT_HLUTNM of \prbs_dec_tap_cnt[4]_i_2\ : label is "soft_lutpair29";
  attribute SOFT_HLUTNM of \prbs_dec_tap_cnt[4]_i_4\ : label is "soft_lutpair45";
  attribute SOFT_HLUTNM of \prbs_dqs_cnt_r[0]_i_1\ : label is "soft_lutpair34";
  attribute SOFT_HLUTNM of \prbs_dqs_cnt_r[1]_i_1\ : label is "soft_lutpair74";
  attribute SOFT_HLUTNM of \prbs_dqs_cnt_r[2]_i_1\ : label is "soft_lutpair74";
  attribute SOFT_HLUTNM of \prbs_dqs_cnt_r[3]_i_2\ : label is "soft_lutpair48";
  attribute SOFT_HLUTNM of \prbs_dqs_cnt_r[3]_i_3\ : label is "soft_lutpair16";
  attribute SOFT_HLUTNM of \prbs_dqs_cnt_r[3]_i_4\ : label is "soft_lutpair48";
  attribute SOFT_HLUTNM of \prbs_dqs_tap_cnt_r[1]_i_1\ : label is "soft_lutpair36";
  attribute SOFT_HLUTNM of \prbs_dqs_tap_cnt_r[3]_i_2\ : label is "soft_lutpair49";
  attribute SOFT_HLUTNM of \prbs_dqs_tap_cnt_r[4]_i_2\ : label is "soft_lutpair38";
  attribute SOFT_HLUTNM of prbs_dqs_tap_limit_r_i_1 : label is "soft_lutpair67";
  attribute SOFT_HLUTNM of prbs_found_1st_edge_r_i_1 : label is "soft_lutpair50";
  attribute SOFT_HLUTNM of prbs_found_2nd_edge_r_i_1 : label is "soft_lutpair21";
  attribute SOFT_HLUTNM of \prbs_inc_tap_cnt[1]_i_1\ : label is "soft_lutpair23";
  attribute SOFT_HLUTNM of \prbs_inc_tap_cnt[1]_i_2\ : label is "soft_lutpair42";
  attribute SOFT_HLUTNM of \prbs_inc_tap_cnt[2]_i_2\ : label is "soft_lutpair23";
  attribute SOFT_HLUTNM of \prbs_inc_tap_cnt[2]_i_3\ : label is "soft_lutpair42";
  attribute SOFT_HLUTNM of \prbs_inc_tap_cnt[3]_i_3\ : label is "soft_lutpair57";
  attribute SOFT_HLUTNM of \prbs_inc_tap_cnt[5]_i_10\ : label is "soft_lutpair65";
  attribute SOFT_HLUTNM of \prbs_inc_tap_cnt[5]_i_11\ : label is "soft_lutpair56";
  attribute SOFT_HLUTNM of \prbs_inc_tap_cnt[5]_i_12\ : label is "soft_lutpair57";
  attribute SOFT_HLUTNM of \prbs_inc_tap_cnt[5]_i_5\ : label is "soft_lutpair20";
  attribute SOFT_HLUTNM of \prbs_inc_tap_cnt[5]_i_7\ : label is "soft_lutpair56";
  attribute SOFT_HLUTNM of \prbs_inc_tap_cnt[5]_i_8\ : label is "soft_lutpair55";
  attribute SOFT_HLUTNM of \prbs_inc_tap_cnt[5]_i_9\ : label is "soft_lutpair68";
  attribute SOFT_HLUTNM of prbs_last_byte_done_i_2 : label is "soft_lutpair60";
  attribute SOFT_HLUTNM of prbs_rdlvl_done_pulse_i_1 : label is "soft_lutpair35";
  attribute MAX_FANOUT : string;
  attribute MAX_FANOUT of prbs_rdlvl_done_reg : label is "100";
  attribute SOFT_HLUTNM of \prbs_state_r[0]_i_2\ : label is "soft_lutpair44";
  attribute SOFT_HLUTNM of \prbs_state_r[1]_i_4\ : label is "soft_lutpair26";
  attribute SOFT_HLUTNM of \prbs_state_r[1]_i_6\ : label is "soft_lutpair15";
  attribute SOFT_HLUTNM of \prbs_state_r[2]_i_1\ : label is "soft_lutpair25";
  attribute SOFT_HLUTNM of \prbs_state_r[2]_i_4\ : label is "soft_lutpair15";
  attribute SOFT_HLUTNM of \prbs_state_r[3]_i_2\ : label is "soft_lutpair51";
  attribute SOFT_HLUTNM of \prbs_state_r[3]_i_3\ : label is "soft_lutpair51";
  attribute SOFT_HLUTNM of \prbs_state_r[3]_i_4\ : label is "soft_lutpair54";
  attribute SOFT_HLUTNM of \prbs_state_r[4]_i_11\ : label is "soft_lutpair25";
  attribute SOFT_HLUTNM of \prbs_state_r[4]_i_12\ : label is "soft_lutpair50";
  attribute SOFT_HLUTNM of \prbs_state_r[4]_i_2\ : label is "soft_lutpair26";
  attribute SOFT_HLUTNM of \prbs_state_r[4]_i_3\ : label is "soft_lutpair44";
  attribute SOFT_HLUTNM of \prbs_state_r[4]_i_5\ : label is "soft_lutpair55";
  attribute SOFT_HLUTNM of \prbs_state_r[4]_i_9\ : label is "soft_lutpair28";
  attribute SOFT_HLUTNM of reset_if_i_2 : label is "soft_lutpair35";
  attribute SOFT_HLUTNM of right_edge_found_i_3 : label is "soft_lutpair41";
  attribute SOFT_HLUTNM of right_edge_found_i_5 : label is "soft_lutpair58";
  attribute SOFT_HLUTNM of \samples_cnt_r[10]_i_1\ : label is "soft_lutpair75";
  attribute SOFT_HLUTNM of \samples_cnt_r[11]_i_2\ : label is "soft_lutpair76";
  attribute SOFT_HLUTNM of \samples_cnt_r[1]_i_1\ : label is "soft_lutpair75";
  attribute SOFT_HLUTNM of \samples_cnt_r[2]_i_1\ : label is "soft_lutpair77";
  attribute SOFT_HLUTNM of \samples_cnt_r[3]_i_1\ : label is "soft_lutpair76";
  attribute SOFT_HLUTNM of \samples_cnt_r[4]_i_1\ : label is "soft_lutpair79";
  attribute SOFT_HLUTNM of \samples_cnt_r[5]_i_1\ : label is "soft_lutpair81";
  attribute SOFT_HLUTNM of \samples_cnt_r[6]_i_1\ : label is "soft_lutpair79";
  attribute SOFT_HLUTNM of \samples_cnt_r[8]_i_1\ : label is "soft_lutpair81";
  attribute SOFT_HLUTNM of \samples_cnt_r[9]_i_1\ : label is "soft_lutpair77";
  attribute SOFT_HLUTNM of \smallest_right_edge[0]_i_1\ : label is "soft_lutpair72";
  attribute SOFT_HLUTNM of \smallest_right_edge[1]_i_1\ : label is "soft_lutpair72";
  attribute SOFT_HLUTNM of \smallest_right_edge[2]_i_1\ : label is "soft_lutpair32";
  attribute SOFT_HLUTNM of \smallest_right_edge[3]_i_1\ : label is "soft_lutpair32";
  attribute SOFT_HLUTNM of \smallest_right_edge[5]_i_10\ : label is "soft_lutpair58";
  attribute SOFT_HLUTNM of \smallest_right_edge[5]_i_5\ : label is "soft_lutpair20";
  attribute SOFT_HLUTNM of \smallest_right_edge[5]_i_6\ : label is "soft_lutpair30";
  attribute SOFT_HLUTNM of \stage_cnt[1]_i_1\ : label is "soft_lutpair43";
  attribute SOFT_HLUTNM of wait_state_cnt_en_r_i_1 : label is "soft_lutpair30";
  attribute SOFT_HLUTNM of \wait_state_cnt_r[0]_i_1\ : label is "soft_lutpair80";
  attribute SOFT_HLUTNM of \wait_state_cnt_r[1]_i_1\ : label is "soft_lutpair80";
  attribute SOFT_HLUTNM of \wait_state_cnt_r[2]_i_1\ : label is "soft_lutpair64";
  attribute SOFT_HLUTNM of \wait_state_cnt_r[3]_i_2\ : label is "soft_lutpair64";
begin
  D(5 downto 0) <= \^d\(5 downto 0);
  complex_pi_incdec_done <= \^complex_pi_incdec_done\;
  new_cnt_dqs_r_reg_0 <= \^new_cnt_dqs_r_reg_0\;
  num_samples_done_r <= \^num_samples_done_r\;
  prbs_last_byte_done <= \^prbs_last_byte_done\;
  prbs_rdlvl_done_reg_0 <= \^prbs_rdlvl_done_reg_0\;
  prbs_rdlvl_start_r <= \^prbs_rdlvl_start_r\;
  \rd_victim_sel_reg[0]_0\ <= \^rd_victim_sel_reg[0]_0\;
  \rd_victim_sel_reg[1]_0\ <= \^rd_victim_sel_reg[1]_0\;
  \rd_victim_sel_reg[2]_0\ <= \^rd_victim_sel_reg[2]_0\;
  reset_rd_addr <= \^reset_rd_addr\;
  \samples_cnt_r_reg[11]_0\ <= \^samples_cnt_r_reg[11]_0\;
\bit_cnt[0]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \bit_cnt_reg_n_0_[0]\,
      O => \p_0_in__0\(0)
    );
\bit_cnt[1]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \bit_cnt_reg_n_0_[0]\,
      I1 => \bit_cnt_reg_n_0_[1]\,
      O => \p_0_in__0\(1)
    );
\bit_cnt[2]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"6A"
    )
        port map (
      I0 => \bit_cnt_reg_n_0_[2]\,
      I1 => \bit_cnt_reg_n_0_[1]\,
      I2 => \bit_cnt_reg_n_0_[0]\,
      O => \p_0_in__0\(2)
    );
\bit_cnt[3]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"80"
    )
        port map (
      I0 => \bit_cnt_reg_n_0_[2]\,
      I1 => \bit_cnt_reg_n_0_[0]\,
      I2 => \bit_cnt_reg_n_0_[1]\,
      O => \p_0_in__0\(3)
    );
\bit_cnt[7]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFF00000002"
    )
        port map (
      I0 => prbs_state_r(0),
      I1 => prbs_state_r(3),
      I2 => prbs_state_r(2),
      I3 => prbs_state_r(1),
      I4 => prbs_state_r(4),
      I5 => \rd_victim_sel_reg[2]_1\,
      O => \bit_cnt[7]_i_1_n_0\
    );
\bit_cnt[7]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000100000000"
    )
        port map (
      I0 => \p_0_in__0\(6),
      I1 => \p_0_in__0\(7),
      I2 => \stage_cnt_reg_n_0_[1]\,
      I3 => \stage_cnt_reg_n_0_[0]\,
      I4 => \bit_cnt_reg_n_0_[3]\,
      I5 => \bit_cnt[7]_i_3_n_0\,
      O => bit_cnt0
    );
\bit_cnt[7]_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00080000"
    )
        port map (
      I0 => prbs_state_r(4),
      I1 => prbs_state_r(0),
      I2 => prbs_state_r(3),
      I3 => prbs_state_r(2),
      I4 => prbs_state_r(1),
      O => \bit_cnt[7]_i_3_n_0\
    );
\bit_cnt_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => bit_cnt0,
      D => \p_0_in__0\(0),
      Q => \bit_cnt_reg_n_0_[0]\,
      R => \bit_cnt[7]_i_1_n_0\
    );
\bit_cnt_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => bit_cnt0,
      D => \p_0_in__0\(1),
      Q => \bit_cnt_reg_n_0_[1]\,
      R => \bit_cnt[7]_i_1_n_0\
    );
\bit_cnt_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => bit_cnt0,
      D => \p_0_in__0\(2),
      Q => \bit_cnt_reg_n_0_[2]\,
      R => \bit_cnt[7]_i_1_n_0\
    );
\bit_cnt_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => bit_cnt0,
      D => \p_0_in__0\(3),
      Q => \bit_cnt_reg_n_0_[3]\,
      R => \bit_cnt[7]_i_1_n_0\
    );
\bit_cnt_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => bit_cnt0,
      D => \p_0_in__0\(6),
      Q => \p_0_in__0\(6),
      R => \bit_cnt[7]_i_1_n_0\
    );
\bit_cnt_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => bit_cnt0,
      D => \p_0_in__0\(7),
      Q => \p_0_in__0\(7),
      R => \bit_cnt[7]_i_1_n_0\
    );
\cmp_err_4to1.compare_err_f0_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFF6FF6"
    )
        port map (
      I0 => p_0_in184_in(7),
      I1 => p_1_in185_in(7),
      I2 => p_0_in184_in(6),
      I3 => p_1_in185_in(6),
      I4 => \cmp_err_4to1.compare_err_f0_i_2_n_0\,
      I5 => \cmp_err_4to1.compare_err_f0_i_3_n_0\,
      O => compare_err_f00
    );
\cmp_err_4to1.compare_err_f0_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"6FF6FFFFFFFF6FF6"
    )
        port map (
      I0 => p_1_in185_in(3),
      I1 => p_0_in184_in(3),
      I2 => p_0_in184_in(5),
      I3 => p_1_in185_in(5),
      I4 => p_0_in184_in(4),
      I5 => p_1_in185_in(4),
      O => \cmp_err_4to1.compare_err_f0_i_2_n_0\
    );
\cmp_err_4to1.compare_err_f0_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"6FF6FFFFFFFF6FF6"
    )
        port map (
      I0 => p_1_in185_in(0),
      I1 => p_0_in184_in(0),
      I2 => p_0_in184_in(2),
      I3 => p_1_in185_in(2),
      I4 => p_0_in184_in(1),
      I5 => p_1_in185_in(1),
      O => \cmp_err_4to1.compare_err_f0_i_3_n_0\
    );
\cmp_err_4to1.compare_err_f0_reg\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => rd_valid_r2_reg_n_0,
      D => compare_err_f00,
      Q => \cmp_err_4to1.compare_err_f0_reg_n_0\,
      R => compare_err0
    );
\cmp_err_4to1.compare_err_f1_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFF6FF6"
    )
        port map (
      I0 => p_0_in178_in(7),
      I1 => p_1_in179_in(7),
      I2 => p_0_in178_in(6),
      I3 => p_1_in179_in(6),
      I4 => \cmp_err_4to1.compare_err_f1_i_2_n_0\,
      I5 => \cmp_err_4to1.compare_err_f1_i_3_n_0\,
      O => compare_err_f10
    );
\cmp_err_4to1.compare_err_f1_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"6FF6FFFFFFFF6FF6"
    )
        port map (
      I0 => p_1_in179_in(3),
      I1 => p_0_in178_in(3),
      I2 => p_0_in178_in(5),
      I3 => p_1_in179_in(5),
      I4 => p_0_in178_in(4),
      I5 => p_1_in179_in(4),
      O => \cmp_err_4to1.compare_err_f1_i_2_n_0\
    );
\cmp_err_4to1.compare_err_f1_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"6FF6FFFFFFFF6FF6"
    )
        port map (
      I0 => p_1_in179_in(0),
      I1 => p_0_in178_in(0),
      I2 => p_0_in178_in(2),
      I3 => p_1_in179_in(2),
      I4 => p_0_in178_in(1),
      I5 => p_1_in179_in(1),
      O => \cmp_err_4to1.compare_err_f1_i_3_n_0\
    );
\cmp_err_4to1.compare_err_f1_reg\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => rd_valid_r2_reg_n_0,
      D => compare_err_f10,
      Q => \cmp_err_4to1.compare_err_f1_reg_n_0\,
      R => compare_err0
    );
\cmp_err_4to1.compare_err_f2_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFF6FF6"
    )
        port map (
      I0 => p_0_in172_in(7),
      I1 => p_1_in173_in(7),
      I2 => p_0_in172_in(6),
      I3 => p_1_in173_in(6),
      I4 => \cmp_err_4to1.compare_err_f2_i_2_n_0\,
      I5 => \cmp_err_4to1.compare_err_f2_i_3_n_0\,
      O => compare_err_f20
    );
\cmp_err_4to1.compare_err_f2_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"6FF6FFFFFFFF6FF6"
    )
        port map (
      I0 => p_1_in173_in(3),
      I1 => p_0_in172_in(3),
      I2 => p_0_in172_in(5),
      I3 => p_1_in173_in(5),
      I4 => p_0_in172_in(4),
      I5 => p_1_in173_in(4),
      O => \cmp_err_4to1.compare_err_f2_i_2_n_0\
    );
\cmp_err_4to1.compare_err_f2_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"6FF6FFFFFFFF6FF6"
    )
        port map (
      I0 => p_1_in173_in(0),
      I1 => p_0_in172_in(0),
      I2 => p_0_in172_in(2),
      I3 => p_1_in173_in(2),
      I4 => p_0_in172_in(1),
      I5 => p_1_in173_in(1),
      O => \cmp_err_4to1.compare_err_f2_i_3_n_0\
    );
\cmp_err_4to1.compare_err_f2_reg\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => rd_valid_r2_reg_n_0,
      D => compare_err_f20,
      Q => \cmp_err_4to1.compare_err_f2_reg_n_0\,
      R => compare_err0
    );
\cmp_err_4to1.compare_err_f3_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFF6FF6"
    )
        port map (
      I0 => p_0_in166_in(7),
      I1 => p_1_in167_in(7),
      I2 => p_0_in166_in(6),
      I3 => p_1_in167_in(6),
      I4 => \cmp_err_4to1.compare_err_f3_i_2_n_0\,
      I5 => \cmp_err_4to1.compare_err_f3_i_3_n_0\,
      O => compare_err_f30
    );
\cmp_err_4to1.compare_err_f3_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"6FF6FFFFFFFF6FF6"
    )
        port map (
      I0 => p_1_in167_in(3),
      I1 => p_0_in166_in(3),
      I2 => p_0_in166_in(5),
      I3 => p_1_in167_in(5),
      I4 => p_0_in166_in(4),
      I5 => p_1_in167_in(4),
      O => \cmp_err_4to1.compare_err_f3_i_2_n_0\
    );
\cmp_err_4to1.compare_err_f3_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"6FF6FFFFFFFF6FF6"
    )
        port map (
      I0 => p_1_in167_in(0),
      I1 => p_0_in166_in(0),
      I2 => p_0_in166_in(2),
      I3 => p_1_in167_in(2),
      I4 => p_0_in166_in(1),
      I5 => p_1_in167_in(1),
      O => \cmp_err_4to1.compare_err_f3_i_3_n_0\
    );
\cmp_err_4to1.compare_err_f3_reg\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => rd_valid_r2_reg_n_0,
      D => compare_err_f30,
      Q => \cmp_err_4to1.compare_err_f3_reg_n_0\,
      R => compare_err0
    );
\cmp_err_4to1.compare_err_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAAAAABABAAA"
    )
        port map (
      I0 => \cmp_err_4to1.compare_err_f3_reg_0\,
      I1 => prbs_state_r(4),
      I2 => prbs_state_r(0),
      I3 => prbs_state_r(2),
      I4 => prbs_state_r(1),
      I5 => prbs_state_r(3),
      O => compare_err0
    );
\cmp_err_4to1.compare_err_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFFFFE"
    )
        port map (
      I0 => \cmp_err_4to1.compare_err_r1_reg_n_0\,
      I1 => \cmp_err_4to1.compare_err_f1_reg_n_0\,
      I2 => \cmp_err_4to1.compare_err_f3_reg_n_0\,
      I3 => \cmp_err_4to1.compare_err_f0_reg_n_0\,
      I4 => \cmp_err_4to1.compare_err_i_4_n_0\,
      O => compare_err086_out
    );
\cmp_err_4to1.compare_err_i_4\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFFE"
    )
        port map (
      I0 => \cmp_err_4to1.compare_err_r0_reg_n_0\,
      I1 => \cmp_err_4to1.compare_err_f2_reg_n_0\,
      I2 => \cmp_err_4to1.compare_err_r3_reg_n_0\,
      I3 => \cmp_err_4to1.compare_err_r2_reg_n_0\,
      O => \cmp_err_4to1.compare_err_i_4_n_0\
    );
\cmp_err_4to1.compare_err_r0_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFF6FF6"
    )
        port map (
      I0 => p_0_in187_in(7),
      I1 => p_1_in188_in(7),
      I2 => p_0_in187_in(6),
      I3 => p_1_in188_in(6),
      I4 => \cmp_err_4to1.compare_err_r0_i_2_n_0\,
      I5 => \cmp_err_4to1.compare_err_r0_i_3_n_0\,
      O => compare_err_r00
    );
\cmp_err_4to1.compare_err_r0_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"6FF6FFFFFFFF6FF6"
    )
        port map (
      I0 => p_1_in188_in(3),
      I1 => p_0_in187_in(3),
      I2 => p_0_in187_in(5),
      I3 => p_1_in188_in(5),
      I4 => p_0_in187_in(4),
      I5 => p_1_in188_in(4),
      O => \cmp_err_4to1.compare_err_r0_i_2_n_0\
    );
\cmp_err_4to1.compare_err_r0_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"6FF6FFFFFFFF6FF6"
    )
        port map (
      I0 => p_1_in188_in(0),
      I1 => p_0_in187_in(0),
      I2 => p_0_in187_in(2),
      I3 => p_1_in188_in(2),
      I4 => p_0_in187_in(1),
      I5 => p_1_in188_in(1),
      O => \cmp_err_4to1.compare_err_r0_i_3_n_0\
    );
\cmp_err_4to1.compare_err_r0_reg\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => rd_valid_r2_reg_n_0,
      D => compare_err_r00,
      Q => \cmp_err_4to1.compare_err_r0_reg_n_0\,
      R => compare_err0
    );
\cmp_err_4to1.compare_err_r1_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFF6FF6"
    )
        port map (
      I0 => p_0_in181_in(7),
      I1 => p_1_in182_in(7),
      I2 => p_0_in181_in(6),
      I3 => p_1_in182_in(6),
      I4 => \cmp_err_4to1.compare_err_r1_i_2_n_0\,
      I5 => \cmp_err_4to1.compare_err_r1_i_3_n_0\,
      O => compare_err_r10
    );
\cmp_err_4to1.compare_err_r1_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"6FF6FFFFFFFF6FF6"
    )
        port map (
      I0 => p_1_in182_in(3),
      I1 => p_0_in181_in(3),
      I2 => p_0_in181_in(5),
      I3 => p_1_in182_in(5),
      I4 => p_0_in181_in(4),
      I5 => p_1_in182_in(4),
      O => \cmp_err_4to1.compare_err_r1_i_2_n_0\
    );
\cmp_err_4to1.compare_err_r1_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"6FF6FFFFFFFF6FF6"
    )
        port map (
      I0 => p_1_in182_in(0),
      I1 => p_0_in181_in(0),
      I2 => p_0_in181_in(2),
      I3 => p_1_in182_in(2),
      I4 => p_0_in181_in(1),
      I5 => p_1_in182_in(1),
      O => \cmp_err_4to1.compare_err_r1_i_3_n_0\
    );
\cmp_err_4to1.compare_err_r1_reg\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => rd_valid_r2_reg_n_0,
      D => compare_err_r10,
      Q => \cmp_err_4to1.compare_err_r1_reg_n_0\,
      R => compare_err0
    );
\cmp_err_4to1.compare_err_r2_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFF6FF6"
    )
        port map (
      I0 => p_0_in175_in(7),
      I1 => p_1_in176_in(7),
      I2 => p_0_in175_in(6),
      I3 => p_1_in176_in(6),
      I4 => \cmp_err_4to1.compare_err_r2_i_2_n_0\,
      I5 => \cmp_err_4to1.compare_err_r2_i_3_n_0\,
      O => compare_err_r20
    );
\cmp_err_4to1.compare_err_r2_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"6FF6FFFFFFFF6FF6"
    )
        port map (
      I0 => p_1_in176_in(3),
      I1 => p_0_in175_in(3),
      I2 => p_0_in175_in(5),
      I3 => p_1_in176_in(5),
      I4 => p_0_in175_in(4),
      I5 => p_1_in176_in(4),
      O => \cmp_err_4to1.compare_err_r2_i_2_n_0\
    );
\cmp_err_4to1.compare_err_r2_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"6FF6FFFFFFFF6FF6"
    )
        port map (
      I0 => p_1_in176_in(0),
      I1 => p_0_in175_in(0),
      I2 => p_0_in175_in(2),
      I3 => p_1_in176_in(2),
      I4 => p_0_in175_in(1),
      I5 => p_1_in176_in(1),
      O => \cmp_err_4to1.compare_err_r2_i_3_n_0\
    );
\cmp_err_4to1.compare_err_r2_reg\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => rd_valid_r2_reg_n_0,
      D => compare_err_r20,
      Q => \cmp_err_4to1.compare_err_r2_reg_n_0\,
      R => compare_err0
    );
\cmp_err_4to1.compare_err_r3_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFF6FF6"
    )
        port map (
      I0 => p_0_in169_in(7),
      I1 => p_1_in170_in(7),
      I2 => p_0_in169_in(6),
      I3 => p_1_in170_in(6),
      I4 => \cmp_err_4to1.compare_err_r3_i_2_n_0\,
      I5 => \cmp_err_4to1.compare_err_r3_i_3_n_0\,
      O => compare_err_r30
    );
\cmp_err_4to1.compare_err_r3_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"6FF6FFFFFFFF6FF6"
    )
        port map (
      I0 => p_1_in170_in(3),
      I1 => p_0_in169_in(3),
      I2 => p_0_in169_in(5),
      I3 => p_1_in170_in(5),
      I4 => p_0_in169_in(4),
      I5 => p_1_in170_in(4),
      O => \cmp_err_4to1.compare_err_r3_i_2_n_0\
    );
\cmp_err_4to1.compare_err_r3_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"6FF6FFFFFFFF6FF6"
    )
        port map (
      I0 => p_1_in170_in(0),
      I1 => p_0_in169_in(0),
      I2 => p_0_in169_in(2),
      I3 => p_1_in170_in(2),
      I4 => p_0_in169_in(1),
      I5 => p_1_in170_in(1),
      O => \cmp_err_4to1.compare_err_r3_i_3_n_0\
    );
\cmp_err_4to1.compare_err_r3_reg\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => rd_valid_r2_reg_n_0,
      D => compare_err_r30,
      Q => \cmp_err_4to1.compare_err_r3_reg_n_0\,
      R => compare_err0
    );
\cmp_err_4to1.compare_err_reg\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => rd_valid_r2_reg_n_0,
      D => compare_err086_out,
      Q => \cmp_err_4to1.compare_err_reg_n_0\,
      R => compare_err0
    );
\cmp_err_pb_4to1.(null)[0].compare_err_pb[0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FEFEFEFEFEFFFEFE"
    )
        port map (
      I0 => \rd_victim_sel_reg[2]_1\,
      I1 => \^new_cnt_dqs_r_reg_0\,
      I2 => \cmp_err_pb_4to1.(null)[0].compare_err_pb[0]_i_3_n_0\,
      I3 => \cmp_err_pb_4to1.(null)[0].compare_err_pb[0]_i_4_n_0\,
      I4 => err_chk_invalid,
      I5 => prbs_state_r(0),
      O => p_66_out
    );
\cmp_err_pb_4to1.(null)[0].compare_err_pb[0]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFBEFFFFBE"
    )
        port map (
      I0 => \cmp_err_pb_4to1.(null)[0].compare_err_pb[0]_i_5_n_0\,
      I1 => p_1_in188_in(0),
      I2 => p_0_in187_in(0),
      I3 => p_1_in167_in(0),
      I4 => p_0_in166_in(0),
      I5 => \cmp_err_pb_4to1.(null)[0].compare_err_pb[0]_i_6_n_0\,
      O => p_75_out
    );
\cmp_err_pb_4to1.(null)[0].compare_err_pb[0]_i_3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0800"
    )
        port map (
      I0 => prbs_state_r(2),
      I1 => prbs_state_r(0),
      I2 => prbs_state_r(4),
      I3 => prbs_state_r(3),
      O => \cmp_err_pb_4to1.(null)[0].compare_err_pb[0]_i_3_n_0\
    );
\cmp_err_pb_4to1.(null)[0].compare_err_pb[0]_i_4\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F7EF"
    )
        port map (
      I0 => prbs_state_r(1),
      I1 => prbs_state_r(2),
      I2 => prbs_state_r(4),
      I3 => prbs_state_r(3),
      O => \cmp_err_pb_4to1.(null)[0].compare_err_pb[0]_i_4_n_0\
    );
\cmp_err_pb_4to1.(null)[0].compare_err_pb[0]_i_5\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6FF6"
    )
        port map (
      I0 => p_1_in176_in(0),
      I1 => p_0_in175_in(0),
      I2 => p_1_in179_in(0),
      I3 => p_0_in178_in(0),
      O => \cmp_err_pb_4to1.(null)[0].compare_err_pb[0]_i_5_n_0\
    );
\cmp_err_pb_4to1.(null)[0].compare_err_pb[0]_i_6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFF6FF6"
    )
        port map (
      I0 => p_0_in184_in(0),
      I1 => p_1_in185_in(0),
      I2 => p_0_in181_in(0),
      I3 => p_1_in182_in(0),
      I4 => \cmp_err_pb_4to1.(null)[0].compare_err_pb[0]_i_7_n_0\,
      O => \cmp_err_pb_4to1.(null)[0].compare_err_pb[0]_i_6_n_0\
    );
\cmp_err_pb_4to1.(null)[0].compare_err_pb[0]_i_7\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6FF6"
    )
        port map (
      I0 => p_1_in173_in(0),
      I1 => p_0_in172_in(0),
      I2 => p_1_in170_in(0),
      I3 => p_0_in169_in(0),
      O => \cmp_err_pb_4to1.(null)[0].compare_err_pb[0]_i_7_n_0\
    );
\cmp_err_pb_4to1.(null)[0].compare_err_pb_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => rd_valid_r2_reg_n_0,
      D => p_75_out,
      Q => compare_err_pb(0),
      R => p_66_out
    );
\cmp_err_pb_4to1.(null)[1].compare_err_pb[1]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFBEFFFFBE"
    )
        port map (
      I0 => \cmp_err_pb_4to1.(null)[1].compare_err_pb[1]_i_2_n_0\,
      I1 => p_1_in188_in(1),
      I2 => p_0_in187_in(1),
      I3 => p_1_in167_in(1),
      I4 => p_0_in166_in(1),
      I5 => \cmp_err_pb_4to1.(null)[1].compare_err_pb[1]_i_3_n_0\,
      O => p_64_out
    );
\cmp_err_pb_4to1.(null)[1].compare_err_pb[1]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6FF6"
    )
        port map (
      I0 => p_1_in170_in(1),
      I1 => p_0_in169_in(1),
      I2 => p_1_in173_in(1),
      I3 => p_0_in172_in(1),
      O => \cmp_err_pb_4to1.(null)[1].compare_err_pb[1]_i_2_n_0\
    );
\cmp_err_pb_4to1.(null)[1].compare_err_pb[1]_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFF6FF6"
    )
        port map (
      I0 => p_0_in178_in(1),
      I1 => p_1_in179_in(1),
      I2 => p_0_in175_in(1),
      I3 => p_1_in176_in(1),
      I4 => \cmp_err_pb_4to1.(null)[1].compare_err_pb[1]_i_4_n_0\,
      O => \cmp_err_pb_4to1.(null)[1].compare_err_pb[1]_i_3_n_0\
    );
\cmp_err_pb_4to1.(null)[1].compare_err_pb[1]_i_4\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6FF6"
    )
        port map (
      I0 => p_1_in182_in(1),
      I1 => p_0_in181_in(1),
      I2 => p_1_in185_in(1),
      I3 => p_0_in184_in(1),
      O => \cmp_err_pb_4to1.(null)[1].compare_err_pb[1]_i_4_n_0\
    );
\cmp_err_pb_4to1.(null)[1].compare_err_pb_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => rd_valid_r2_reg_n_0,
      D => p_64_out,
      Q => compare_err_pb(1),
      R => p_66_out
    );
\cmp_err_pb_4to1.(null)[2].compare_err_pb[2]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFBEFFFFBE"
    )
        port map (
      I0 => \cmp_err_pb_4to1.(null)[2].compare_err_pb[2]_i_2_n_0\,
      I1 => p_1_in170_in(2),
      I2 => p_0_in169_in(2),
      I3 => p_1_in188_in(2),
      I4 => p_0_in187_in(2),
      I5 => \cmp_err_pb_4to1.(null)[2].compare_err_pb[2]_i_3_n_0\,
      O => p_55_out
    );
\cmp_err_pb_4to1.(null)[2].compare_err_pb[2]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6FF6"
    )
        port map (
      I0 => p_1_in167_in(2),
      I1 => p_0_in166_in(2),
      I2 => p_1_in173_in(2),
      I3 => p_0_in172_in(2),
      O => \cmp_err_pb_4to1.(null)[2].compare_err_pb[2]_i_2_n_0\
    );
\cmp_err_pb_4to1.(null)[2].compare_err_pb[2]_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFF6FF6"
    )
        port map (
      I0 => p_0_in178_in(2),
      I1 => p_1_in179_in(2),
      I2 => p_0_in175_in(2),
      I3 => p_1_in176_in(2),
      I4 => \cmp_err_pb_4to1.(null)[2].compare_err_pb[2]_i_4_n_0\,
      O => \cmp_err_pb_4to1.(null)[2].compare_err_pb[2]_i_3_n_0\
    );
\cmp_err_pb_4to1.(null)[2].compare_err_pb[2]_i_4\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6FF6"
    )
        port map (
      I0 => p_1_in182_in(2),
      I1 => p_0_in181_in(2),
      I2 => p_1_in185_in(2),
      I3 => p_0_in184_in(2),
      O => \cmp_err_pb_4to1.(null)[2].compare_err_pb[2]_i_4_n_0\
    );
\cmp_err_pb_4to1.(null)[2].compare_err_pb_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => rd_valid_r2_reg_n_0,
      D => p_55_out,
      Q => compare_err_pb(2),
      R => p_66_out
    );
\cmp_err_pb_4to1.(null)[3].compare_err_pb[3]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFBEFFFFBE"
    )
        port map (
      I0 => \cmp_err_pb_4to1.(null)[3].compare_err_pb[3]_i_2_n_0\,
      I1 => p_1_in188_in(3),
      I2 => p_0_in187_in(3),
      I3 => p_1_in167_in(3),
      I4 => p_0_in166_in(3),
      I5 => \cmp_err_pb_4to1.(null)[3].compare_err_pb[3]_i_3_n_0\,
      O => p_46_out
    );
\cmp_err_pb_4to1.(null)[3].compare_err_pb[3]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6FF6"
    )
        port map (
      I0 => p_1_in170_in(3),
      I1 => p_0_in169_in(3),
      I2 => p_1_in173_in(3),
      I3 => p_0_in172_in(3),
      O => \cmp_err_pb_4to1.(null)[3].compare_err_pb[3]_i_2_n_0\
    );
\cmp_err_pb_4to1.(null)[3].compare_err_pb[3]_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFF6FF6"
    )
        port map (
      I0 => p_0_in178_in(3),
      I1 => p_1_in179_in(3),
      I2 => p_0_in175_in(3),
      I3 => p_1_in176_in(3),
      I4 => \cmp_err_pb_4to1.(null)[3].compare_err_pb[3]_i_4_n_0\,
      O => \cmp_err_pb_4to1.(null)[3].compare_err_pb[3]_i_3_n_0\
    );
\cmp_err_pb_4to1.(null)[3].compare_err_pb[3]_i_4\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6FF6"
    )
        port map (
      I0 => p_1_in182_in(3),
      I1 => p_0_in181_in(3),
      I2 => p_1_in185_in(3),
      I3 => p_0_in184_in(3),
      O => \cmp_err_pb_4to1.(null)[3].compare_err_pb[3]_i_4_n_0\
    );
\cmp_err_pb_4to1.(null)[3].compare_err_pb_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => rd_valid_r2_reg_n_0,
      D => p_46_out,
      Q => compare_err_pb(3),
      R => p_66_out
    );
\cmp_err_pb_4to1.(null)[4].compare_err_pb[4]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFBEFFFFBE"
    )
        port map (
      I0 => \cmp_err_pb_4to1.(null)[4].compare_err_pb[4]_i_2_n_0\,
      I1 => p_1_in188_in(4),
      I2 => p_0_in187_in(4),
      I3 => p_1_in167_in(4),
      I4 => p_0_in166_in(4),
      I5 => \cmp_err_pb_4to1.(null)[4].compare_err_pb[4]_i_3_n_0\,
      O => p_37_out
    );
\cmp_err_pb_4to1.(null)[4].compare_err_pb[4]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6FF6"
    )
        port map (
      I0 => p_1_in170_in(4),
      I1 => p_0_in169_in(4),
      I2 => p_1_in173_in(4),
      I3 => p_0_in172_in(4),
      O => \cmp_err_pb_4to1.(null)[4].compare_err_pb[4]_i_2_n_0\
    );
\cmp_err_pb_4to1.(null)[4].compare_err_pb[4]_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFF6FF6"
    )
        port map (
      I0 => p_0_in178_in(4),
      I1 => p_1_in179_in(4),
      I2 => p_0_in175_in(4),
      I3 => p_1_in176_in(4),
      I4 => \cmp_err_pb_4to1.(null)[4].compare_err_pb[4]_i_4_n_0\,
      O => \cmp_err_pb_4to1.(null)[4].compare_err_pb[4]_i_3_n_0\
    );
\cmp_err_pb_4to1.(null)[4].compare_err_pb[4]_i_4\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6FF6"
    )
        port map (
      I0 => p_1_in182_in(4),
      I1 => p_0_in181_in(4),
      I2 => p_1_in185_in(4),
      I3 => p_0_in184_in(4),
      O => \cmp_err_pb_4to1.(null)[4].compare_err_pb[4]_i_4_n_0\
    );
\cmp_err_pb_4to1.(null)[4].compare_err_pb_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => rd_valid_r2_reg_n_0,
      D => p_37_out,
      Q => compare_err_pb(4),
      R => p_66_out
    );
\cmp_err_pb_4to1.(null)[5].compare_err_pb[5]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFBEFFFFBE"
    )
        port map (
      I0 => \cmp_err_pb_4to1.(null)[5].compare_err_pb[5]_i_2_n_0\,
      I1 => p_1_in173_in(5),
      I2 => p_0_in172_in(5),
      I3 => p_1_in188_in(5),
      I4 => p_0_in187_in(5),
      I5 => \cmp_err_pb_4to1.(null)[5].compare_err_pb[5]_i_3_n_0\,
      O => p_28_out
    );
\cmp_err_pb_4to1.(null)[5].compare_err_pb[5]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6FF6"
    )
        port map (
      I0 => p_1_in167_in(5),
      I1 => p_0_in166_in(5),
      I2 => p_1_in170_in(5),
      I3 => p_0_in169_in(5),
      O => \cmp_err_pb_4to1.(null)[5].compare_err_pb[5]_i_2_n_0\
    );
\cmp_err_pb_4to1.(null)[5].compare_err_pb[5]_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFF6FF6"
    )
        port map (
      I0 => p_0_in178_in(5),
      I1 => p_1_in179_in(5),
      I2 => p_0_in175_in(5),
      I3 => p_1_in176_in(5),
      I4 => \cmp_err_pb_4to1.(null)[5].compare_err_pb[5]_i_4_n_0\,
      O => \cmp_err_pb_4to1.(null)[5].compare_err_pb[5]_i_3_n_0\
    );
\cmp_err_pb_4to1.(null)[5].compare_err_pb[5]_i_4\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6FF6"
    )
        port map (
      I0 => p_1_in182_in(5),
      I1 => p_0_in181_in(5),
      I2 => p_1_in185_in(5),
      I3 => p_0_in184_in(5),
      O => \cmp_err_pb_4to1.(null)[5].compare_err_pb[5]_i_4_n_0\
    );
\cmp_err_pb_4to1.(null)[5].compare_err_pb_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => rd_valid_r2_reg_n_0,
      D => p_28_out,
      Q => compare_err_pb(5),
      R => p_66_out
    );
\cmp_err_pb_4to1.(null)[6].compare_err_pb[6]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFBEFFFFBE"
    )
        port map (
      I0 => \cmp_err_pb_4to1.(null)[6].compare_err_pb[6]_i_2_n_0\,
      I1 => p_1_in188_in(6),
      I2 => p_0_in187_in(6),
      I3 => p_1_in176_in(6),
      I4 => p_0_in175_in(6),
      I5 => \cmp_err_pb_4to1.(null)[6].compare_err_pb[6]_i_3_n_0\,
      O => p_19_out
    );
\cmp_err_pb_4to1.(null)[6].compare_err_pb[6]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6FF6"
    )
        port map (
      I0 => p_1_in185_in(6),
      I1 => p_0_in184_in(6),
      I2 => p_1_in182_in(6),
      I3 => p_0_in181_in(6),
      O => \cmp_err_pb_4to1.(null)[6].compare_err_pb[6]_i_2_n_0\
    );
\cmp_err_pb_4to1.(null)[6].compare_err_pb[6]_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFF6FF6"
    )
        port map (
      I0 => p_0_in169_in(6),
      I1 => p_1_in170_in(6),
      I2 => p_0_in166_in(6),
      I3 => p_1_in167_in(6),
      I4 => \cmp_err_pb_4to1.(null)[6].compare_err_pb[6]_i_4_n_0\,
      O => \cmp_err_pb_4to1.(null)[6].compare_err_pb[6]_i_3_n_0\
    );
\cmp_err_pb_4to1.(null)[6].compare_err_pb[6]_i_4\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6FF6"
    )
        port map (
      I0 => p_1_in173_in(6),
      I1 => p_0_in172_in(6),
      I2 => p_1_in179_in(6),
      I3 => p_0_in178_in(6),
      O => \cmp_err_pb_4to1.(null)[6].compare_err_pb[6]_i_4_n_0\
    );
\cmp_err_pb_4to1.(null)[6].compare_err_pb_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => rd_valid_r2_reg_n_0,
      D => p_19_out,
      Q => compare_err_pb(6),
      R => p_66_out
    );
\cmp_err_pb_4to1.(null)[7].compare_err_pb[7]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFBEFFFFBE"
    )
        port map (
      I0 => \cmp_err_pb_4to1.(null)[7].compare_err_pb[7]_i_2_n_0\,
      I1 => p_1_in188_in(7),
      I2 => p_0_in187_in(7),
      I3 => p_1_in167_in(7),
      I4 => p_0_in166_in(7),
      I5 => \cmp_err_pb_4to1.(null)[7].compare_err_pb[7]_i_3_n_0\,
      O => p_10_out
    );
\cmp_err_pb_4to1.(null)[7].compare_err_pb[7]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6FF6"
    )
        port map (
      I0 => p_1_in173_in(7),
      I1 => p_0_in172_in(7),
      I2 => p_1_in176_in(7),
      I3 => p_0_in175_in(7),
      O => \cmp_err_pb_4to1.(null)[7].compare_err_pb[7]_i_2_n_0\
    );
\cmp_err_pb_4to1.(null)[7].compare_err_pb[7]_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFF6FF6"
    )
        port map (
      I0 => p_0_in169_in(7),
      I1 => p_1_in170_in(7),
      I2 => p_0_in184_in(7),
      I3 => p_1_in185_in(7),
      I4 => \cmp_err_pb_4to1.(null)[7].compare_err_pb[7]_i_4_n_0\,
      O => \cmp_err_pb_4to1.(null)[7].compare_err_pb[7]_i_3_n_0\
    );
\cmp_err_pb_4to1.(null)[7].compare_err_pb[7]_i_4\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6FF6"
    )
        port map (
      I0 => p_1_in182_in(7),
      I1 => p_0_in181_in(7),
      I2 => p_1_in179_in(7),
      I3 => p_0_in178_in(7),
      O => \cmp_err_pb_4to1.(null)[7].compare_err_pb[7]_i_4_n_0\
    );
\cmp_err_pb_4to1.(null)[7].compare_err_pb_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => rd_valid_r2_reg_n_0,
      D => p_10_out,
      Q => compare_err_pb(7),
      R => p_66_out
    );
cnt_wait_state_i_1: unisim.vcomponents.LUT5
    generic map(
      INIT => X"80000000"
    )
        port map (
      I0 => wait_state_cnt_r_reg(3),
      I1 => wait_state_cnt_en_r,
      I2 => wait_state_cnt_r_reg(0),
      I3 => wait_state_cnt_r_reg(1),
      I4 => wait_state_cnt_r_reg(2),
      O => cnt_wait_state_i_1_n_0
    );
cnt_wait_state_reg: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => '1',
      D => cnt_wait_state_i_1_n_0,
      Q => cnt_wait_state,
      R => '0'
    );
compare_err_latch_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000003000000020"
    )
        port map (
      I0 => \cmp_err_4to1.compare_err_reg_n_0\,
      I1 => prbs_state_r(0),
      I2 => \prbs_state_r[3]_i_4_n_0\,
      I3 => prbs_state_r(4),
      I4 => prbs_state_r(3),
      I5 => compare_err_latch_reg_n_0,
      O => compare_err_latch_i_1_n_0
    );
compare_err_latch_reg: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => '1',
      D => compare_err_latch_i_1_n_0,
      Q => compare_err_latch_reg_n_0,
      R => '0'
    );
compare_err_pb_and_i_1: unisim.vcomponents.LUT5
    generic map(
      INIT => X"000000AB"
    )
        port map (
      I0 => compare_err_pb_and_reg_n_0,
      I1 => compare_err_pb_and_i_2_n_0,
      I2 => compare_err_pb_and_i_3_n_0,
      I3 => \rd_victim_sel_reg[2]_1\,
      I4 => \genblk7[0].compare_err_pb_latch_r[0]_i_1_n_0\,
      O => compare_err_pb_and_i_1_n_0
    );
compare_err_pb_and_i_2: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7FFF"
    )
        port map (
      I0 => compare_err_pb(1),
      I1 => compare_err_pb(0),
      I2 => compare_err_pb(3),
      I3 => compare_err_pb(2),
      O => compare_err_pb_and_i_2_n_0
    );
compare_err_pb_and_i_3: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7FFF"
    )
        port map (
      I0 => compare_err_pb(5),
      I1 => compare_err_pb(4),
      I2 => compare_err_pb(7),
      I3 => compare_err_pb(6),
      O => compare_err_pb_and_i_3_n_0
    );
compare_err_pb_and_reg: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => '1',
      D => compare_err_pb_and_i_1_n_0,
      Q => compare_err_pb_and_reg_n_0,
      R => '0'
    );
compare_err_pb_or_i_1: unisim.vcomponents.LUT5
    generic map(
      INIT => X"000000FE"
    )
        port map (
      I0 => sel0(0),
      I1 => compare_err_pb_or_i_2_n_0,
      I2 => compare_err_pb_or_i_3_n_0,
      I3 => \rd_victim_sel_reg[2]_1\,
      I4 => \genblk7[0].compare_err_pb_latch_r[0]_i_1_n_0\,
      O => compare_err_pb_or_i_1_n_0
    );
compare_err_pb_or_i_2: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFFE"
    )
        port map (
      I0 => compare_err_pb(1),
      I1 => compare_err_pb(0),
      I2 => compare_err_pb(3),
      I3 => compare_err_pb(2),
      O => compare_err_pb_or_i_2_n_0
    );
compare_err_pb_or_i_3: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFFE"
    )
        port map (
      I0 => compare_err_pb(5),
      I1 => compare_err_pb(4),
      I2 => compare_err_pb(7),
      I3 => compare_err_pb(6),
      O => compare_err_pb_or_i_3_n_0
    );
compare_err_pb_or_reg: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => '1',
      D => compare_err_pb_or_i_1_n_0,
      Q => sel0(0),
      R => '0'
    );
complex_pi_incdec_done_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAABFAAAAAA80"
    )
        port map (
      I0 => complex_pi_incdec_done_i_2_n_0,
      I1 => complex_pi_incdec_done_i_3_n_0,
      I2 => complex_pi_incdec_done_i_4_n_0,
      I3 => complex_pi_incdec_done_i_5_n_0,
      I4 => complex_pi_incdec_done_i_6_n_0,
      I5 => \^complex_pi_incdec_done\,
      O => complex_pi_incdec_done_i_1_n_0
    );
complex_pi_incdec_done_i_2: unisim.vcomponents.LUT6
    generic map(
      INIT => X"A0A2A2A2A0AEA2A2"
    )
        port map (
      I0 => cnt_wait_state,
      I1 => prbs_state_r(1),
      I2 => prbs_state_r(2),
      I3 => prbs_state_r(4),
      I4 => prbs_state_r(0),
      I5 => prbs_state_r(3),
      O => complex_pi_incdec_done_i_2_n_0
    );
complex_pi_incdec_done_i_3: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => prbs_state_r(1),
      I1 => prbs_state_r(4),
      O => complex_pi_incdec_done_i_3_n_0
    );
complex_pi_incdec_done_i_4: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0A5A0A0A15150505"
    )
        port map (
      I0 => prbs_state_r(0),
      I1 => \prbs_state_r[2]_i_5_n_0\,
      I2 => prbs_state_r(2),
      I3 => \fine_pi_dec_cnt[5]_i_4_n_0\,
      I4 => cnt_wait_state,
      I5 => prbs_state_r(3),
      O => complex_pi_incdec_done_i_4_n_0
    );
complex_pi_incdec_done_i_5: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000080000000000"
    )
        port map (
      I0 => \prbs_dec_tap_cnt[5]_i_3_n_0\,
      I1 => prbs_state_r(2),
      I2 => prbs_state_r(0),
      I3 => cnt_wait_state,
      I4 => prbs_state_r(4),
      I5 => complex_pi_incdec_done_i_7_n_0,
      O => complex_pi_incdec_done_i_5_n_0
    );
complex_pi_incdec_done_i_6: unisim.vcomponents.LUT6
    generic map(
      INIT => X"000001000000FFFF"
    )
        port map (
      I0 => \prbs_state_r[3]_i_6_n_0\,
      I1 => prbs_state_r(4),
      I2 => prbs_state_r(3),
      I3 => prbs_state_r(1),
      I4 => prbs_state_r(2),
      I5 => complex_pi_incdec_done_i_8_n_0,
      O => complex_pi_incdec_done_i_6_n_0
    );
complex_pi_incdec_done_i_7: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => prbs_state_r(3),
      I1 => prbs_state_r(1),
      O => complex_pi_incdec_done_i_7_n_0
    );
complex_pi_incdec_done_i_8: unisim.vcomponents.LUT6
    generic map(
      INIT => X"EEEEEEEEEEEFEFFF"
    )
        port map (
      I0 => prbs_state_r(3),
      I1 => prbs_state_r(1),
      I2 => prbs_state_r(4),
      I3 => cnt_wait_state,
      I4 => prbs_state_r(0),
      I5 => prbs_state_r(2),
      O => complex_pi_incdec_done_i_8_n_0
    );
complex_pi_incdec_done_reg: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => '1',
      D => complex_pi_incdec_done_i_1_n_0,
      Q => \^complex_pi_incdec_done\,
      R => \match_flag_and_reg[7]_0\
    );
complex_victim_inc_i_1: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \^samples_cnt_r_reg[11]_0\,
      O => complex_victim_inc
    );
complex_victim_inc_reg: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => '1',
      D => complex_victim_inc,
      Q => complex_victim_inc_reg_0,
      R => \samples_cnt_r_reg[0]_0\
    );
edge_det_error_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFB3000000"
    )
        port map (
      I0 => edge_det_error_i_2_n_0,
      I1 => prbs_found_1st_edge_r_reg_n_0,
      I2 => prbs_found_2nd_edge_r_reg_n_0,
      I3 => edge_det_error_i_3_n_0,
      I4 => edge_det_error_i_4_n_0,
      I5 => edge_det_error_reg_n_0,
      O => edge_det_error_i_1_n_0
    );
edge_det_error_i_2: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B2BB2222"
    )
        port map (
      I0 => \prbs_1st_edge_taps_r_reg_n_0_[5]\,
      I1 => prbs_2nd_edge_taps_r(5),
      I2 => \prbs_1st_edge_taps_r_reg_n_0_[4]\,
      I3 => prbs_2nd_edge_taps_r(4),
      I4 => edge_det_error_i_5_n_0,
      O => edge_det_error_i_2_n_0
    );
edge_det_error_i_3: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => prbs_state_r(3),
      I1 => prbs_state_r(4),
      O => edge_det_error_i_3_n_0
    );
edge_det_error_i_4: unisim.vcomponents.LUT3
    generic map(
      INIT => X"80"
    )
        port map (
      I0 => prbs_state_r(2),
      I1 => prbs_state_r(1),
      I2 => prbs_state_r(0),
      O => edge_det_error_i_4_n_0
    );
edge_det_error_i_5: unisim.vcomponents.LUT6
    generic map(
      INIT => X"22F2FFFF22F222F2"
    )
        port map (
      I0 => edge_det_error_i_6_n_0,
      I1 => edge_det_error_i_7_n_0,
      I2 => \prbs_1st_edge_taps_r_reg_n_0_[4]\,
      I3 => prbs_2nd_edge_taps_r(4),
      I4 => prbs_2nd_edge_taps_r(3),
      I5 => \prbs_1st_edge_taps_r_reg_n_0_[3]\,
      O => edge_det_error_i_5_n_0
    );
edge_det_error_i_6: unisim.vcomponents.LUT6
    generic map(
      INIT => X"D0FDD0FDFFFFD0FD"
    )
        port map (
      I0 => prbs_2nd_edge_taps_r(0),
      I1 => \prbs_1st_edge_taps_r_reg_n_0_[0]\,
      I2 => \prbs_1st_edge_taps_r_reg_n_0_[1]\,
      I3 => prbs_2nd_edge_taps_r(1),
      I4 => \prbs_1st_edge_taps_r_reg_n_0_[2]\,
      I5 => prbs_2nd_edge_taps_r(2),
      O => edge_det_error_i_6_n_0
    );
edge_det_error_i_7: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4F44"
    )
        port map (
      I0 => \prbs_1st_edge_taps_r_reg_n_0_[3]\,
      I1 => prbs_2nd_edge_taps_r(3),
      I2 => \prbs_1st_edge_taps_r_reg_n_0_[2]\,
      I3 => prbs_2nd_edge_taps_r(2),
      O => edge_det_error_i_7_n_0
    );
edge_det_error_reg: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => '1',
      D => edge_det_error_i_1_n_0,
      Q => edge_det_error_reg_n_0,
      R => \samples_cnt_r_reg[0]_0\
    );
err_chk_invalid_i_1: unisim.vcomponents.LUT3
    generic map(
      INIT => X"7F"
    )
        port map (
      I0 => wait_state_cnt_r_reg(3),
      I1 => wait_state_cnt_r_reg(2),
      I2 => wait_state_cnt_r_reg(1),
      O => err_chk_invalid_i_1_n_0
    );
err_chk_invalid_reg: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => '1',
      D => err_chk_invalid_i_1_n_0,
      Q => err_chk_invalid,
      R => '0'
    );
fine_inc_stage_i_1: unisim.vcomponents.LUT2
    generic map(
      INIT => X"7"
    )
        port map (
      I0 => \stage_cnt_reg_n_0_[0]\,
      I1 => \stage_cnt_reg_n_0_[1]\,
      O => fine_inc_stage_i_1_n_0
    );
fine_inc_stage_reg: unisim.vcomponents.FDSE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => '1',
      D => fine_inc_stage_i_1_n_0,
      Q => fine_inc_stage_reg_n_0,
      S => \prbs_dec_tap_cnt_reg[0]_0\(0)
    );
\fine_pi_dec_cnt[0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00CA003AFFCAFF3A"
    )
        port map (
      I0 => \^d\(0),
      I1 => \fine_pi_dec_cnt[0]_i_2_n_0\,
      I2 => prbs_state_r(1),
      I3 => prbs_state_r(2),
      I4 => \fine_pi_dec_cnt[0]_i_3_n_0\,
      I5 => \fine_pi_dec_cnt_reg_n_0_[0]\,
      O => \fine_pi_dec_cnt[0]_i_1_n_0\
    );
\fine_pi_dec_cnt[0]_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"FB"
    )
        port map (
      I0 => \fine_pi_dec_cnt_reg[3]_i_7_n_6\,
      I1 => \stage_cnt_reg_n_0_[1]\,
      I2 => \stage_cnt_reg_n_0_[0]\,
      O => \fine_pi_dec_cnt[0]_i_2_n_0\
    );
\fine_pi_dec_cnt[0]_i_3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FB04"
    )
        port map (
      I0 => \stage_cnt_reg_n_0_[0]\,
      I1 => \stage_cnt_reg_n_0_[1]\,
      I2 => \fine_pi_dec_cnt_reg[3]_i_7_n_7\,
      I3 => \prbs_dqs_tap_cnt_r_reg_n_0_[0]\,
      O => \fine_pi_dec_cnt[0]_i_3_n_0\
    );
\fine_pi_dec_cnt[1]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E22E"
    )
        port map (
      I0 => \fine_pi_dec_cnt[1]_i_2_n_0\,
      I1 => prbs_state_r(2),
      I2 => \fine_pi_dec_cnt_reg_n_0_[0]\,
      I3 => \fine_pi_dec_cnt_reg_n_0_[1]\,
      O => \fine_pi_dec_cnt[1]_i_1_n_0\
    );
\fine_pi_dec_cnt[1]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"CCC3333CAAAAAAAA"
    )
        port map (
      I0 => \^d\(1),
      I1 => \fine_pi_dec_cnt[1]_i_3_n_0\,
      I2 => \fine_pi_dec_cnt[5]_i_11_n_0\,
      I3 => \fine_pi_dec_cnt_reg[3]_i_7_n_5\,
      I4 => \prbs_dqs_tap_cnt_r_reg_n_0_[1]\,
      I5 => prbs_state_r(1),
      O => \fine_pi_dec_cnt[1]_i_2_n_0\
    );
\fine_pi_dec_cnt[1]_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FBF3FFFB"
    )
        port map (
      I0 => \fine_pi_dec_cnt_reg[3]_i_7_n_6\,
      I1 => \stage_cnt_reg_n_0_[1]\,
      I2 => \stage_cnt_reg_n_0_[0]\,
      I3 => \fine_pi_dec_cnt_reg[3]_i_7_n_7\,
      I4 => \prbs_dqs_tap_cnt_r_reg_n_0_[0]\,
      O => \fine_pi_dec_cnt[1]_i_3_n_0\
    );
\fine_pi_dec_cnt[2]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FCAA03AA"
    )
        port map (
      I0 => \fine_pi_dec_cnt[2]_i_2_n_0\,
      I1 => \fine_pi_dec_cnt_reg_n_0_[0]\,
      I2 => \fine_pi_dec_cnt_reg_n_0_[1]\,
      I3 => prbs_state_r(2),
      I4 => \fine_pi_dec_cnt_reg_n_0_[2]\,
      O => \fine_pi_dec_cnt[2]_i_1_n_0\
    );
\fine_pi_dec_cnt[2]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"CCC3333CAAAAAAAA"
    )
        port map (
      I0 => \^d\(2),
      I1 => \fine_pi_dec_cnt[3]_i_8_n_0\,
      I2 => \fine_pi_dec_cnt[5]_i_11_n_0\,
      I3 => \fine_pi_dec_cnt_reg[3]_i_7_n_4\,
      I4 => \prbs_dqs_tap_cnt_r_reg_n_0_[2]\,
      I5 => prbs_state_r(1),
      O => \fine_pi_dec_cnt[2]_i_2_n_0\
    );
\fine_pi_dec_cnt[3]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFAAEAAABA"
    )
        port map (
      I0 => \fine_pi_dec_cnt[3]_i_2_n_0\,
      I1 => \fine_pi_dec_cnt[3]_i_3_n_0\,
      I2 => prbs_state_r(1),
      I3 => prbs_state_r(2),
      I4 => \fine_pi_dec_cnt[3]_i_4_n_0\,
      I5 => \fine_pi_dec_cnt[3]_i_5_n_0\,
      O => \fine_pi_dec_cnt[3]_i_1_n_0\
    );
\fine_pi_dec_cnt[3]_i_10\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \smallest_right_edge_reg_n_0_[2]\,
      I1 => \largest_left_edge_reg_n_0_[2]\,
      O => \fine_pi_dec_cnt[3]_i_10_n_0\
    );
\fine_pi_dec_cnt[3]_i_11\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \smallest_right_edge_reg_n_0_[1]\,
      I1 => \largest_left_edge_reg_n_0_[1]\,
      O => \fine_pi_dec_cnt[3]_i_11_n_0\
    );
\fine_pi_dec_cnt[3]_i_12\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \smallest_right_edge_reg_n_0_[0]\,
      I1 => \largest_left_edge_reg_n_0_[0]\,
      O => \fine_pi_dec_cnt[3]_i_12_n_0\
    );
\fine_pi_dec_cnt[3]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"880F8800"
    )
        port map (
      I0 => \fine_pi_dec_cnt[3]_i_6_n_0\,
      I1 => \fine_pi_dec_cnt_reg_n_0_[3]\,
      I2 => prbs_state_r(1),
      I3 => prbs_state_r(2),
      I4 => \^d\(3),
      O => \fine_pi_dec_cnt[3]_i_2_n_0\
    );
\fine_pi_dec_cnt[3]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"04FB40BF04FB04FB"
    )
        port map (
      I0 => \stage_cnt_reg_n_0_[0]\,
      I1 => \stage_cnt_reg_n_0_[1]\,
      I2 => \fine_pi_dec_cnt_reg[5]_i_10_n_7\,
      I3 => \prbs_dqs_tap_cnt_r_reg_n_0_[3]\,
      I4 => \fine_pi_dec_cnt_reg[3]_i_7_n_4\,
      I5 => \prbs_dqs_tap_cnt_r_reg_n_0_[2]\,
      O => \fine_pi_dec_cnt[3]_i_3_n_0\
    );
\fine_pi_dec_cnt[3]_i_4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"55450010"
    )
        port map (
      I0 => \fine_pi_dec_cnt[3]_i_8_n_0\,
      I1 => \stage_cnt_reg_n_0_[0]\,
      I2 => \stage_cnt_reg_n_0_[1]\,
      I3 => \fine_pi_dec_cnt_reg[3]_i_7_n_4\,
      I4 => \prbs_dqs_tap_cnt_r_reg_n_0_[2]\,
      O => \fine_pi_dec_cnt[3]_i_4_n_0\
    );
\fine_pi_dec_cnt[3]_i_5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000004"
    )
        port map (
      I0 => \fine_pi_dec_cnt_reg_n_0_[3]\,
      I1 => prbs_state_r(2),
      I2 => \fine_pi_dec_cnt_reg_n_0_[0]\,
      I3 => \fine_pi_dec_cnt_reg_n_0_[1]\,
      I4 => \fine_pi_dec_cnt_reg_n_0_[2]\,
      O => \fine_pi_dec_cnt[3]_i_5_n_0\
    );
\fine_pi_dec_cnt[3]_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"FE"
    )
        port map (
      I0 => \fine_pi_dec_cnt_reg_n_0_[2]\,
      I1 => \fine_pi_dec_cnt_reg_n_0_[1]\,
      I2 => \fine_pi_dec_cnt_reg_n_0_[0]\,
      O => \fine_pi_dec_cnt[3]_i_6_n_0\
    );
\fine_pi_dec_cnt[3]_i_8\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"ECFECCCCFFFFECFE"
    )
        port map (
      I0 => \fine_pi_dec_cnt_reg[3]_i_7_n_6\,
      I1 => \fine_pi_dec_cnt[5]_i_11_n_0\,
      I2 => \fine_pi_dec_cnt_reg[3]_i_7_n_7\,
      I3 => \prbs_dqs_tap_cnt_r_reg_n_0_[0]\,
      I4 => \fine_pi_dec_cnt_reg[3]_i_7_n_5\,
      I5 => \prbs_dqs_tap_cnt_r_reg_n_0_[1]\,
      O => \fine_pi_dec_cnt[3]_i_8_n_0\
    );
\fine_pi_dec_cnt[3]_i_9\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \smallest_right_edge_reg_n_0_[3]\,
      I1 => \largest_left_edge_reg_n_0_[3]\,
      O => \fine_pi_dec_cnt[3]_i_9_n_0\
    );
\fine_pi_dec_cnt[4]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"EAAEEAAEFBBFEAAE"
    )
        port map (
      I0 => \fine_pi_dec_cnt[4]_i_2_n_0\,
      I1 => prbs_state_r(2),
      I2 => \fine_pi_dec_cnt[4]_i_3_n_0\,
      I3 => \fine_pi_dec_cnt_reg_n_0_[4]\,
      I4 => \^d\(4),
      I5 => prbs_state_r(1),
      O => \fine_pi_dec_cnt[4]_i_1_n_0\
    );
\fine_pi_dec_cnt[4]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2002"
    )
        port map (
      I0 => prbs_state_r(1),
      I1 => prbs_state_r(2),
      I2 => \fine_pi_dec_cnt[4]_i_4_n_0\,
      I3 => \fine_pi_dec_cnt[5]_i_9_n_0\,
      O => \fine_pi_dec_cnt[4]_i_2_n_0\
    );
\fine_pi_dec_cnt[4]_i_3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFFE"
    )
        port map (
      I0 => \fine_pi_dec_cnt_reg_n_0_[3]\,
      I1 => \fine_pi_dec_cnt_reg_n_0_[0]\,
      I2 => \fine_pi_dec_cnt_reg_n_0_[1]\,
      I3 => \fine_pi_dec_cnt_reg_n_0_[2]\,
      O => \fine_pi_dec_cnt[4]_i_3_n_0\
    );
\fine_pi_dec_cnt[4]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"5565556555955565"
    )
        port map (
      I0 => \prbs_dqs_tap_cnt_r_reg_n_0_[4]\,
      I1 => \fine_pi_dec_cnt_reg[5]_i_10_n_6\,
      I2 => \stage_cnt_reg_n_0_[1]\,
      I3 => \stage_cnt_reg_n_0_[0]\,
      I4 => \fine_pi_dec_cnt_reg[5]_i_10_n_7\,
      I5 => \prbs_dqs_tap_cnt_r_reg_n_0_[3]\,
      O => \fine_pi_dec_cnt[4]_i_4_n_0\
    );
\fine_pi_dec_cnt[5]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FBAAAAAAEAAAAAAA"
    )
        port map (
      I0 => \fine_pi_dec_cnt[5]_i_3_n_0\,
      I1 => prbs_state_r(2),
      I2 => \fine_pi_dec_cnt[5]_i_4_n_0\,
      I3 => \fine_pi_dec_cnt[5]_i_5_n_0\,
      I4 => \prbs_state_r[0]_i_2_n_0\,
      I5 => cnt_wait_state,
      O => fine_pi_dec_cnt
    );
\fine_pi_dec_cnt[5]_i_11\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => \stage_cnt_reg_n_0_[0]\,
      I1 => \stage_cnt_reg_n_0_[1]\,
      O => \fine_pi_dec_cnt[5]_i_11_n_0\
    );
\fine_pi_dec_cnt[5]_i_12\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0B00"
    )
        port map (
      I0 => \prbs_dqs_tap_cnt_r_reg_n_0_[3]\,
      I1 => \fine_pi_dec_cnt_reg[5]_i_10_n_7\,
      I2 => \stage_cnt_reg_n_0_[0]\,
      I3 => \stage_cnt_reg_n_0_[1]\,
      O => \fine_pi_dec_cnt[5]_i_12_n_0\
    );
\fine_pi_dec_cnt[5]_i_13\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \smallest_right_edge_reg_n_0_[5]\,
      I1 => \largest_left_edge_reg_n_0_[5]\,
      O => \fine_pi_dec_cnt[5]_i_13_n_0\
    );
\fine_pi_dec_cnt[5]_i_14\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \smallest_right_edge_reg_n_0_[4]\,
      I1 => \largest_left_edge_reg_n_0_[4]\,
      O => \fine_pi_dec_cnt[5]_i_14_n_0\
    );
\fine_pi_dec_cnt[5]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"88BBBB88B8B8B8B8"
    )
        port map (
      I0 => \fine_pi_dec_cnt[5]_i_6_n_0\,
      I1 => prbs_state_r(2),
      I2 => \^d\(5),
      I3 => \fine_pi_dec_cnt[5]_i_7_n_0\,
      I4 => \fine_pi_dec_cnt[5]_i_8_n_0\,
      I5 => prbs_state_r(1),
      O => \fine_pi_dec_cnt[5]_i_2_n_0\
    );
\fine_pi_dec_cnt[5]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"000C000000000002"
    )
        port map (
      I0 => new_cnt_dqs_r_reg_1,
      I1 => prbs_state_r(1),
      I2 => prbs_state_r(2),
      I3 => prbs_state_r(3),
      I4 => prbs_state_r(0),
      I5 => prbs_state_r(4),
      O => \fine_pi_dec_cnt[5]_i_3_n_0\
    );
\fine_pi_dec_cnt[5]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFFFE"
    )
        port map (
      I0 => \fine_pi_dec_cnt_reg_n_0_[3]\,
      I1 => \fine_pi_dec_cnt_reg_n_0_[0]\,
      I2 => \fine_pi_dec_cnt_reg_n_0_[1]\,
      I3 => \fine_pi_dec_cnt_reg_n_0_[2]\,
      I4 => \fine_pi_dec_cnt_reg_n_0_[4]\,
      I5 => \fine_pi_dec_cnt_reg_n_0_[5]\,
      O => \fine_pi_dec_cnt[5]_i_4_n_0\
    );
\fine_pi_dec_cnt[5]_i_5\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => prbs_state_r(3),
      I1 => prbs_state_r(4),
      O => \fine_pi_dec_cnt[5]_i_5_n_0\
    );
\fine_pi_dec_cnt[5]_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAAAAAAAAAA9"
    )
        port map (
      I0 => \fine_pi_dec_cnt_reg_n_0_[5]\,
      I1 => \fine_pi_dec_cnt_reg_n_0_[4]\,
      I2 => \fine_pi_dec_cnt_reg_n_0_[2]\,
      I3 => \fine_pi_dec_cnt_reg_n_0_[1]\,
      I4 => \fine_pi_dec_cnt_reg_n_0_[0]\,
      I5 => \fine_pi_dec_cnt_reg_n_0_[3]\,
      O => \fine_pi_dec_cnt[5]_i_6_n_0\
    );
\fine_pi_dec_cnt[5]_i_7\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AA8AAA200020008A"
    )
        port map (
      I0 => \fine_pi_dec_cnt[5]_i_9_n_0\,
      I1 => \prbs_dqs_tap_cnt_r_reg_n_0_[3]\,
      I2 => \fine_pi_dec_cnt_reg[5]_i_10_n_7\,
      I3 => \fine_pi_dec_cnt[5]_i_11_n_0\,
      I4 => \fine_pi_dec_cnt_reg[5]_i_10_n_6\,
      I5 => \prbs_dqs_tap_cnt_r_reg_n_0_[4]\,
      O => \fine_pi_dec_cnt[5]_i_7_n_0\
    );
\fine_pi_dec_cnt[5]_i_8\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"3936C9C9C9C9C6C9"
    )
        port map (
      I0 => \fine_pi_dec_cnt_reg[5]_i_10_n_1\,
      I1 => \prbs_dqs_tap_cnt_r_reg_n_0_[5]\,
      I2 => \fine_pi_dec_cnt[5]_i_11_n_0\,
      I3 => \fine_pi_dec_cnt_reg[5]_i_10_n_6\,
      I4 => \prbs_dqs_tap_cnt_r_reg_n_0_[4]\,
      I5 => \fine_pi_dec_cnt[5]_i_12_n_0\,
      O => \fine_pi_dec_cnt[5]_i_8_n_0\
    );
\fine_pi_dec_cnt[5]_i_9\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"006600F6A0F6A0FF"
    )
        port map (
      I0 => \prbs_dqs_tap_cnt_r_reg_n_0_[3]\,
      I1 => \fine_pi_dec_cnt_reg[5]_i_10_n_7\,
      I2 => \prbs_dqs_tap_cnt_r_reg_n_0_[2]\,
      I3 => \fine_pi_dec_cnt[5]_i_11_n_0\,
      I4 => \fine_pi_dec_cnt_reg[3]_i_7_n_4\,
      I5 => \fine_pi_dec_cnt[3]_i_8_n_0\,
      O => \fine_pi_dec_cnt[5]_i_9_n_0\
    );
\fine_pi_dec_cnt_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => fine_pi_dec_cnt,
      D => \fine_pi_dec_cnt[0]_i_1_n_0\,
      Q => \fine_pi_dec_cnt_reg_n_0_[0]\,
      R => \samples_cnt_r_reg[0]_0\
    );
\fine_pi_dec_cnt_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => fine_pi_dec_cnt,
      D => \fine_pi_dec_cnt[1]_i_1_n_0\,
      Q => \fine_pi_dec_cnt_reg_n_0_[1]\,
      R => \samples_cnt_r_reg[0]_0\
    );
\fine_pi_dec_cnt_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => fine_pi_dec_cnt,
      D => \fine_pi_dec_cnt[2]_i_1_n_0\,
      Q => \fine_pi_dec_cnt_reg_n_0_[2]\,
      R => \samples_cnt_r_reg[0]_0\
    );
\fine_pi_dec_cnt_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => fine_pi_dec_cnt,
      D => \fine_pi_dec_cnt[3]_i_1_n_0\,
      Q => \fine_pi_dec_cnt_reg_n_0_[3]\,
      R => \samples_cnt_r_reg[0]_0\
    );
\fine_pi_dec_cnt_reg[3]_i_7\: unisim.vcomponents.CARRY4
     port map (
      CI => '0',
      CO(3) => \fine_pi_dec_cnt_reg[3]_i_7_n_0\,
      CO(2) => \fine_pi_dec_cnt_reg[3]_i_7_n_1\,
      CO(1) => \fine_pi_dec_cnt_reg[3]_i_7_n_2\,
      CO(0) => \fine_pi_dec_cnt_reg[3]_i_7_n_3\,
      CYINIT => '0',
      DI(3) => \smallest_right_edge_reg_n_0_[3]\,
      DI(2) => \smallest_right_edge_reg_n_0_[2]\,
      DI(1) => \smallest_right_edge_reg_n_0_[1]\,
      DI(0) => \smallest_right_edge_reg_n_0_[0]\,
      O(3) => \fine_pi_dec_cnt_reg[3]_i_7_n_4\,
      O(2) => \fine_pi_dec_cnt_reg[3]_i_7_n_5\,
      O(1) => \fine_pi_dec_cnt_reg[3]_i_7_n_6\,
      O(0) => \fine_pi_dec_cnt_reg[3]_i_7_n_7\,
      S(3) => \fine_pi_dec_cnt[3]_i_9_n_0\,
      S(2) => \fine_pi_dec_cnt[3]_i_10_n_0\,
      S(1) => \fine_pi_dec_cnt[3]_i_11_n_0\,
      S(0) => \fine_pi_dec_cnt[3]_i_12_n_0\
    );
\fine_pi_dec_cnt_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => fine_pi_dec_cnt,
      D => \fine_pi_dec_cnt[4]_i_1_n_0\,
      Q => \fine_pi_dec_cnt_reg_n_0_[4]\,
      R => \samples_cnt_r_reg[0]_0\
    );
\fine_pi_dec_cnt_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => fine_pi_dec_cnt,
      D => \fine_pi_dec_cnt[5]_i_2_n_0\,
      Q => \fine_pi_dec_cnt_reg_n_0_[5]\,
      R => \samples_cnt_r_reg[0]_0\
    );
\fine_pi_dec_cnt_reg[5]_i_10\: unisim.vcomponents.CARRY4
     port map (
      CI => \fine_pi_dec_cnt_reg[3]_i_7_n_0\,
      CO(3) => \NLW_fine_pi_dec_cnt_reg[5]_i_10_CO_UNCONNECTED\(3),
      CO(2) => \fine_pi_dec_cnt_reg[5]_i_10_n_1\,
      CO(1) => \NLW_fine_pi_dec_cnt_reg[5]_i_10_CO_UNCONNECTED\(1),
      CO(0) => \fine_pi_dec_cnt_reg[5]_i_10_n_3\,
      CYINIT => '0',
      DI(3 downto 2) => B"00",
      DI(1) => \smallest_right_edge_reg_n_0_[5]\,
      DI(0) => \smallest_right_edge_reg_n_0_[4]\,
      O(3 downto 2) => \NLW_fine_pi_dec_cnt_reg[5]_i_10_O_UNCONNECTED\(3 downto 2),
      O(1) => \fine_pi_dec_cnt_reg[5]_i_10_n_6\,
      O(0) => \fine_pi_dec_cnt_reg[5]_i_10_n_7\,
      S(3 downto 2) => B"01",
      S(1) => \fine_pi_dec_cnt[5]_i_13_n_0\,
      S(0) => \fine_pi_dec_cnt[5]_i_14_n_0\
    );
\gen_byte_sel_div2.byte_sel_cnt[0]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0808FB08"
    )
        port map (
      I0 => \prbs_dqs_cnt_r_reg_n_0_[0]\,
      I1 => \gen_byte_sel_div2.byte_sel_cnt_reg[0]\,
      I2 => \^prbs_rdlvl_done_reg_0\,
      I3 => Q(0),
      I4 => \gen_byte_sel_div2.byte_sel_cnt_reg[0]_0\,
      O => \prbs_dqs_cnt_r_reg[0]_0\
    );
\gen_byte_sel_div2.byte_sel_cnt[1]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0808FB08"
    )
        port map (
      I0 => \prbs_dqs_cnt_r_reg_n_0_[1]\,
      I1 => \gen_byte_sel_div2.byte_sel_cnt_reg[0]\,
      I2 => \^prbs_rdlvl_done_reg_0\,
      I3 => Q(1),
      I4 => \gen_byte_sel_div2.byte_sel_cnt_reg[0]_0\,
      O => \prbs_dqs_cnt_r_reg[1]_0\
    );
\gen_byte_sel_div2.byte_sel_cnt[2]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0808FB08"
    )
        port map (
      I0 => \prbs_dqs_cnt_r_reg_n_0_[2]\,
      I1 => \gen_byte_sel_div2.byte_sel_cnt_reg[0]\,
      I2 => \^prbs_rdlvl_done_reg_0\,
      I3 => Q(2),
      I4 => \gen_byte_sel_div2.byte_sel_cnt_reg[0]_0\,
      O => \prbs_dqs_cnt_r_reg[2]_0\
    );
\gen_byte_sel_div2.byte_sel_cnt[3]_i_5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0808FB08"
    )
        port map (
      I0 => \prbs_dqs_cnt_r_reg_n_0_[3]\,
      I1 => \gen_byte_sel_div2.byte_sel_cnt_reg[0]\,
      I2 => \^prbs_rdlvl_done_reg_0\,
      I3 => Q(3),
      I4 => \gen_byte_sel_div2.byte_sel_cnt_reg[0]_0\,
      O => \prbs_dqs_cnt_r_reg[3]_0\
    );
\gen_mux_div4.gen_rd_4[0].mux_rd_fall0_r2_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => mux_rd_valid_r,
      D => mux_rd_fall0_r1,
      Q => mux_rd_fall0_r2,
      R => '0'
    );
\gen_mux_div4.gen_rd_4[0].mux_rd_fall0_r3_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => '1',
      D => mux_rd_fall0_r2,
      Q => p_1_in185_in(0),
      R => '0'
    );
\gen_mux_div4.gen_rd_4[0].mux_rd_fall1_r2_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => mux_rd_valid_r,
      D => mux_rd_fall1_r1,
      Q => mux_rd_fall1_r2,
      R => '0'
    );
\gen_mux_div4.gen_rd_4[0].mux_rd_fall1_r3_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => '1',
      D => mux_rd_fall1_r2,
      Q => p_1_in179_in(0),
      R => '0'
    );
\gen_mux_div4.gen_rd_4[0].mux_rd_fall2_r2_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => mux_rd_valid_r,
      D => mux_rd_fall2_r1,
      Q => mux_rd_fall2_r2,
      R => '0'
    );
\gen_mux_div4.gen_rd_4[0].mux_rd_fall2_r3_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => '1',
      D => mux_rd_fall2_r2,
      Q => p_1_in173_in(0),
      R => '0'
    );
\gen_mux_div4.gen_rd_4[0].mux_rd_fall3_r2_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => mux_rd_valid_r,
      D => mux_rd_fall3_r1,
      Q => mux_rd_fall3_r2,
      R => '0'
    );
\gen_mux_div4.gen_rd_4[0].mux_rd_fall3_r3_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => '1',
      D => mux_rd_fall3_r2,
      Q => p_1_in167_in(0),
      R => '0'
    );
\gen_mux_div4.gen_rd_4[0].mux_rd_rise0_r2_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => mux_rd_valid_r,
      D => mux_rd_rise0_r1,
      Q => mux_rd_rise0_r2,
      R => '0'
    );
\gen_mux_div4.gen_rd_4[0].mux_rd_rise0_r3_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => '1',
      D => mux_rd_rise0_r2,
      Q => p_1_in188_in(0),
      R => '0'
    );
\gen_mux_div4.gen_rd_4[0].mux_rd_rise1_r2_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => mux_rd_valid_r,
      D => mux_rd_rise1_r1,
      Q => mux_rd_rise1_r2,
      R => '0'
    );
\gen_mux_div4.gen_rd_4[0].mux_rd_rise1_r3_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => '1',
      D => mux_rd_rise1_r2,
      Q => p_1_in182_in(0),
      R => '0'
    );
\gen_mux_div4.gen_rd_4[0].mux_rd_rise2_r2_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => mux_rd_valid_r,
      D => mux_rd_rise2_r1,
      Q => mux_rd_rise2_r2,
      R => '0'
    );
\gen_mux_div4.gen_rd_4[0].mux_rd_rise2_r3_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => '1',
      D => mux_rd_rise2_r2,
      Q => p_1_in176_in(0),
      R => '0'
    );
\gen_mux_div4.gen_rd_4[0].mux_rd_rise3_r2_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => mux_rd_valid_r,
      D => mux_rd_rise3_r1,
      Q => mux_rd_rise3_r2,
      R => '0'
    );
\gen_mux_div4.gen_rd_4[0].mux_rd_rise3_r3_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => '1',
      D => mux_rd_rise3_r2,
      Q => p_1_in170_in(0),
      R => '0'
    );
\gen_mux_div4.gen_rd_4[1].mux_rd_fall0_r2_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => mux_rd_valid_r,
      D => \gen_mux_rd[1].mux_rd_fall0_r1_reg\,
      Q => \gen_mux_div4.gen_rd_4[1].mux_rd_fall0_r2_reg\,
      R => '0'
    );
\gen_mux_div4.gen_rd_4[1].mux_rd_fall0_r3_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => '1',
      D => \gen_mux_div4.gen_rd_4[1].mux_rd_fall0_r2_reg\,
      Q => p_1_in185_in(1),
      R => '0'
    );
\gen_mux_div4.gen_rd_4[1].mux_rd_fall1_r2_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => mux_rd_valid_r,
      D => \gen_mux_rd[1].mux_rd_fall1_r1_reg\,
      Q => \gen_mux_div4.gen_rd_4[1].mux_rd_fall1_r2_reg\,
      R => '0'
    );
\gen_mux_div4.gen_rd_4[1].mux_rd_fall1_r3_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => '1',
      D => \gen_mux_div4.gen_rd_4[1].mux_rd_fall1_r2_reg\,
      Q => p_1_in179_in(1),
      R => '0'
    );
\gen_mux_div4.gen_rd_4[1].mux_rd_fall2_r2_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => mux_rd_valid_r,
      D => \gen_mux_rd[1].mux_rd_fall2_r1_reg\,
      Q => \gen_mux_div4.gen_rd_4[1].mux_rd_fall2_r2_reg\,
      R => '0'
    );
\gen_mux_div4.gen_rd_4[1].mux_rd_fall2_r3_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => '1',
      D => \gen_mux_div4.gen_rd_4[1].mux_rd_fall2_r2_reg\,
      Q => p_1_in173_in(1),
      R => '0'
    );
\gen_mux_div4.gen_rd_4[1].mux_rd_fall3_r2_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => mux_rd_valid_r,
      D => \gen_mux_rd[1].mux_rd_fall3_r1_reg\,
      Q => \gen_mux_div4.gen_rd_4[1].mux_rd_fall3_r2_reg\,
      R => '0'
    );
\gen_mux_div4.gen_rd_4[1].mux_rd_fall3_r3_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => '1',
      D => \gen_mux_div4.gen_rd_4[1].mux_rd_fall3_r2_reg\,
      Q => p_1_in167_in(1),
      R => '0'
    );
\gen_mux_div4.gen_rd_4[1].mux_rd_rise0_r2_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => mux_rd_valid_r,
      D => \gen_mux_rd[1].mux_rd_rise0_r1_reg\,
      Q => \gen_mux_div4.gen_rd_4[1].mux_rd_rise0_r2_reg\,
      R => '0'
    );
\gen_mux_div4.gen_rd_4[1].mux_rd_rise0_r3_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => '1',
      D => \gen_mux_div4.gen_rd_4[1].mux_rd_rise0_r2_reg\,
      Q => p_1_in188_in(1),
      R => '0'
    );
\gen_mux_div4.gen_rd_4[1].mux_rd_rise1_r2_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => mux_rd_valid_r,
      D => \gen_mux_rd[1].mux_rd_rise1_r1_reg\,
      Q => \gen_mux_div4.gen_rd_4[1].mux_rd_rise1_r2_reg\,
      R => '0'
    );
\gen_mux_div4.gen_rd_4[1].mux_rd_rise1_r3_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => '1',
      D => \gen_mux_div4.gen_rd_4[1].mux_rd_rise1_r2_reg\,
      Q => p_1_in182_in(1),
      R => '0'
    );
\gen_mux_div4.gen_rd_4[1].mux_rd_rise2_r2_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => mux_rd_valid_r,
      D => \gen_mux_rd[1].mux_rd_rise2_r1_reg\,
      Q => \gen_mux_div4.gen_rd_4[1].mux_rd_rise2_r2_reg\,
      R => '0'
    );
\gen_mux_div4.gen_rd_4[1].mux_rd_rise2_r3_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => '1',
      D => \gen_mux_div4.gen_rd_4[1].mux_rd_rise2_r2_reg\,
      Q => p_1_in176_in(1),
      R => '0'
    );
\gen_mux_div4.gen_rd_4[1].mux_rd_rise3_r2_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => mux_rd_valid_r,
      D => \gen_mux_rd[1].mux_rd_rise3_r1_reg\,
      Q => \gen_mux_div4.gen_rd_4[1].mux_rd_rise3_r2_reg\,
      R => '0'
    );
\gen_mux_div4.gen_rd_4[1].mux_rd_rise3_r3_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => '1',
      D => \gen_mux_div4.gen_rd_4[1].mux_rd_rise3_r2_reg\,
      Q => p_1_in170_in(1),
      R => '0'
    );
\gen_mux_div4.gen_rd_4[2].mux_rd_fall0_r2_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => mux_rd_valid_r,
      D => \gen_mux_rd[2].mux_rd_fall0_r1_reg\,
      Q => \gen_mux_div4.gen_rd_4[2].mux_rd_fall0_r2_reg\,
      R => '0'
    );
\gen_mux_div4.gen_rd_4[2].mux_rd_fall0_r3_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => '1',
      D => \gen_mux_div4.gen_rd_4[2].mux_rd_fall0_r2_reg\,
      Q => p_1_in185_in(2),
      R => '0'
    );
\gen_mux_div4.gen_rd_4[2].mux_rd_fall1_r2_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => mux_rd_valid_r,
      D => \gen_mux_rd[2].mux_rd_fall1_r1_reg\,
      Q => \gen_mux_div4.gen_rd_4[2].mux_rd_fall1_r2_reg\,
      R => '0'
    );
\gen_mux_div4.gen_rd_4[2].mux_rd_fall1_r3_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => '1',
      D => \gen_mux_div4.gen_rd_4[2].mux_rd_fall1_r2_reg\,
      Q => p_1_in179_in(2),
      R => '0'
    );
\gen_mux_div4.gen_rd_4[2].mux_rd_fall2_r2_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => mux_rd_valid_r,
      D => \gen_mux_rd[2].mux_rd_fall2_r1_reg\,
      Q => \gen_mux_div4.gen_rd_4[2].mux_rd_fall2_r2_reg\,
      R => '0'
    );
\gen_mux_div4.gen_rd_4[2].mux_rd_fall2_r3_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => '1',
      D => \gen_mux_div4.gen_rd_4[2].mux_rd_fall2_r2_reg\,
      Q => p_1_in173_in(2),
      R => '0'
    );
\gen_mux_div4.gen_rd_4[2].mux_rd_fall3_r2_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => mux_rd_valid_r,
      D => \gen_mux_rd[2].mux_rd_fall3_r1_reg\,
      Q => \gen_mux_div4.gen_rd_4[2].mux_rd_fall3_r2_reg\,
      R => '0'
    );
\gen_mux_div4.gen_rd_4[2].mux_rd_fall3_r3_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => '1',
      D => \gen_mux_div4.gen_rd_4[2].mux_rd_fall3_r2_reg\,
      Q => p_1_in167_in(2),
      R => '0'
    );
\gen_mux_div4.gen_rd_4[2].mux_rd_rise0_r2_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => mux_rd_valid_r,
      D => \gen_mux_rd[2].mux_rd_rise0_r1_reg\,
      Q => \gen_mux_div4.gen_rd_4[2].mux_rd_rise0_r2_reg\,
      R => '0'
    );
\gen_mux_div4.gen_rd_4[2].mux_rd_rise0_r3_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => '1',
      D => \gen_mux_div4.gen_rd_4[2].mux_rd_rise0_r2_reg\,
      Q => p_1_in188_in(2),
      R => '0'
    );
\gen_mux_div4.gen_rd_4[2].mux_rd_rise1_r2_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => mux_rd_valid_r,
      D => \gen_mux_rd[2].mux_rd_rise1_r1_reg\,
      Q => \gen_mux_div4.gen_rd_4[2].mux_rd_rise1_r2_reg\,
      R => '0'
    );
\gen_mux_div4.gen_rd_4[2].mux_rd_rise1_r3_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => '1',
      D => \gen_mux_div4.gen_rd_4[2].mux_rd_rise1_r2_reg\,
      Q => p_1_in182_in(2),
      R => '0'
    );
\gen_mux_div4.gen_rd_4[2].mux_rd_rise2_r2_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => mux_rd_valid_r,
      D => \gen_mux_rd[2].mux_rd_rise2_r1_reg\,
      Q => \gen_mux_div4.gen_rd_4[2].mux_rd_rise2_r2_reg\,
      R => '0'
    );
\gen_mux_div4.gen_rd_4[2].mux_rd_rise2_r3_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => '1',
      D => \gen_mux_div4.gen_rd_4[2].mux_rd_rise2_r2_reg\,
      Q => p_1_in176_in(2),
      R => '0'
    );
\gen_mux_div4.gen_rd_4[2].mux_rd_rise3_r2_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => mux_rd_valid_r,
      D => \gen_mux_rd[2].mux_rd_rise3_r1_reg\,
      Q => \gen_mux_div4.gen_rd_4[2].mux_rd_rise3_r2_reg\,
      R => '0'
    );
\gen_mux_div4.gen_rd_4[2].mux_rd_rise3_r3_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => '1',
      D => \gen_mux_div4.gen_rd_4[2].mux_rd_rise3_r2_reg\,
      Q => p_1_in170_in(2),
      R => '0'
    );
\gen_mux_div4.gen_rd_4[3].mux_rd_fall0_r2_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => mux_rd_valid_r,
      D => \gen_mux_rd[3].mux_rd_fall0_r1_reg\,
      Q => \gen_mux_div4.gen_rd_4[3].mux_rd_fall0_r2_reg\,
      R => '0'
    );
\gen_mux_div4.gen_rd_4[3].mux_rd_fall0_r3_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => '1',
      D => \gen_mux_div4.gen_rd_4[3].mux_rd_fall0_r2_reg\,
      Q => p_1_in185_in(3),
      R => '0'
    );
\gen_mux_div4.gen_rd_4[3].mux_rd_fall1_r2_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => mux_rd_valid_r,
      D => \gen_mux_rd[3].mux_rd_fall1_r1_reg\,
      Q => \gen_mux_div4.gen_rd_4[3].mux_rd_fall1_r2_reg\,
      R => '0'
    );
\gen_mux_div4.gen_rd_4[3].mux_rd_fall1_r3_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => '1',
      D => \gen_mux_div4.gen_rd_4[3].mux_rd_fall1_r2_reg\,
      Q => p_1_in179_in(3),
      R => '0'
    );
\gen_mux_div4.gen_rd_4[3].mux_rd_fall2_r2_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => mux_rd_valid_r,
      D => \gen_mux_rd[3].mux_rd_fall2_r1_reg\,
      Q => \gen_mux_div4.gen_rd_4[3].mux_rd_fall2_r2_reg\,
      R => '0'
    );
\gen_mux_div4.gen_rd_4[3].mux_rd_fall2_r3_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => '1',
      D => \gen_mux_div4.gen_rd_4[3].mux_rd_fall2_r2_reg\,
      Q => p_1_in173_in(3),
      R => '0'
    );
\gen_mux_div4.gen_rd_4[3].mux_rd_fall3_r2_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => mux_rd_valid_r,
      D => \gen_mux_rd[3].mux_rd_fall3_r1_reg\,
      Q => \gen_mux_div4.gen_rd_4[3].mux_rd_fall3_r2_reg\,
      R => '0'
    );
\gen_mux_div4.gen_rd_4[3].mux_rd_fall3_r3_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => '1',
      D => \gen_mux_div4.gen_rd_4[3].mux_rd_fall3_r2_reg\,
      Q => p_1_in167_in(3),
      R => '0'
    );
\gen_mux_div4.gen_rd_4[3].mux_rd_rise0_r2_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => mux_rd_valid_r,
      D => \gen_mux_rd[3].mux_rd_rise0_r1_reg\,
      Q => \gen_mux_div4.gen_rd_4[3].mux_rd_rise0_r2_reg\,
      R => '0'
    );
\gen_mux_div4.gen_rd_4[3].mux_rd_rise0_r3_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => '1',
      D => \gen_mux_div4.gen_rd_4[3].mux_rd_rise0_r2_reg\,
      Q => p_1_in188_in(3),
      R => '0'
    );
\gen_mux_div4.gen_rd_4[3].mux_rd_rise1_r2_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => mux_rd_valid_r,
      D => \gen_mux_rd[3].mux_rd_rise1_r1_reg\,
      Q => \gen_mux_div4.gen_rd_4[3].mux_rd_rise1_r2_reg\,
      R => '0'
    );
\gen_mux_div4.gen_rd_4[3].mux_rd_rise1_r3_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => '1',
      D => \gen_mux_div4.gen_rd_4[3].mux_rd_rise1_r2_reg\,
      Q => p_1_in182_in(3),
      R => '0'
    );
\gen_mux_div4.gen_rd_4[3].mux_rd_rise2_r2_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => mux_rd_valid_r,
      D => \gen_mux_rd[3].mux_rd_rise2_r1_reg\,
      Q => \gen_mux_div4.gen_rd_4[3].mux_rd_rise2_r2_reg\,
      R => '0'
    );
\gen_mux_div4.gen_rd_4[3].mux_rd_rise2_r3_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => '1',
      D => \gen_mux_div4.gen_rd_4[3].mux_rd_rise2_r2_reg\,
      Q => p_1_in176_in(3),
      R => '0'
    );
\gen_mux_div4.gen_rd_4[3].mux_rd_rise3_r2_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => mux_rd_valid_r,
      D => \gen_mux_rd[3].mux_rd_rise3_r1_reg\,
      Q => \gen_mux_div4.gen_rd_4[3].mux_rd_rise3_r2_reg\,
      R => '0'
    );
\gen_mux_div4.gen_rd_4[3].mux_rd_rise3_r3_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => '1',
      D => \gen_mux_div4.gen_rd_4[3].mux_rd_rise3_r2_reg\,
      Q => p_1_in170_in(3),
      R => '0'
    );
\gen_mux_div4.gen_rd_4[4].mux_rd_fall0_r2_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => mux_rd_valid_r,
      D => \gen_mux_rd[4].mux_rd_fall0_r1_reg\,
      Q => \gen_mux_div4.gen_rd_4[4].mux_rd_fall0_r2_reg\,
      R => '0'
    );
\gen_mux_div4.gen_rd_4[4].mux_rd_fall0_r3_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => '1',
      D => \gen_mux_div4.gen_rd_4[4].mux_rd_fall0_r2_reg\,
      Q => p_1_in185_in(4),
      R => '0'
    );
\gen_mux_div4.gen_rd_4[4].mux_rd_fall1_r2_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => mux_rd_valid_r,
      D => \gen_mux_rd[4].mux_rd_fall1_r1_reg\,
      Q => \gen_mux_div4.gen_rd_4[4].mux_rd_fall1_r2_reg\,
      R => '0'
    );
\gen_mux_div4.gen_rd_4[4].mux_rd_fall1_r3_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => '1',
      D => \gen_mux_div4.gen_rd_4[4].mux_rd_fall1_r2_reg\,
      Q => p_1_in179_in(4),
      R => '0'
    );
\gen_mux_div4.gen_rd_4[4].mux_rd_fall2_r2_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => mux_rd_valid_r,
      D => \gen_mux_rd[4].mux_rd_fall2_r1_reg\,
      Q => \gen_mux_div4.gen_rd_4[4].mux_rd_fall2_r2_reg\,
      R => '0'
    );
\gen_mux_div4.gen_rd_4[4].mux_rd_fall2_r3_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => '1',
      D => \gen_mux_div4.gen_rd_4[4].mux_rd_fall2_r2_reg\,
      Q => p_1_in173_in(4),
      R => '0'
    );
\gen_mux_div4.gen_rd_4[4].mux_rd_fall3_r2_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => mux_rd_valid_r,
      D => \gen_mux_rd[4].mux_rd_fall3_r1_reg\,
      Q => \gen_mux_div4.gen_rd_4[4].mux_rd_fall3_r2_reg\,
      R => '0'
    );
\gen_mux_div4.gen_rd_4[4].mux_rd_fall3_r3_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => '1',
      D => \gen_mux_div4.gen_rd_4[4].mux_rd_fall3_r2_reg\,
      Q => p_1_in167_in(4),
      R => '0'
    );
\gen_mux_div4.gen_rd_4[4].mux_rd_rise0_r2_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => mux_rd_valid_r,
      D => \gen_mux_rd[4].mux_rd_rise0_r1_reg\,
      Q => \gen_mux_div4.gen_rd_4[4].mux_rd_rise0_r2_reg\,
      R => '0'
    );
\gen_mux_div4.gen_rd_4[4].mux_rd_rise0_r3_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => '1',
      D => \gen_mux_div4.gen_rd_4[4].mux_rd_rise0_r2_reg\,
      Q => p_1_in188_in(4),
      R => '0'
    );
\gen_mux_div4.gen_rd_4[4].mux_rd_rise1_r2_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => mux_rd_valid_r,
      D => \gen_mux_rd[4].mux_rd_rise1_r1_reg\,
      Q => \gen_mux_div4.gen_rd_4[4].mux_rd_rise1_r2_reg\,
      R => '0'
    );
\gen_mux_div4.gen_rd_4[4].mux_rd_rise1_r3_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => '1',
      D => \gen_mux_div4.gen_rd_4[4].mux_rd_rise1_r2_reg\,
      Q => p_1_in182_in(4),
      R => '0'
    );
\gen_mux_div4.gen_rd_4[4].mux_rd_rise2_r2_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => mux_rd_valid_r,
      D => \gen_mux_rd[4].mux_rd_rise2_r1_reg\,
      Q => \gen_mux_div4.gen_rd_4[4].mux_rd_rise2_r2_reg\,
      R => '0'
    );
\gen_mux_div4.gen_rd_4[4].mux_rd_rise2_r3_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => '1',
      D => \gen_mux_div4.gen_rd_4[4].mux_rd_rise2_r2_reg\,
      Q => p_1_in176_in(4),
      R => '0'
    );
\gen_mux_div4.gen_rd_4[4].mux_rd_rise3_r2_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => mux_rd_valid_r,
      D => \gen_mux_rd[4].mux_rd_rise3_r1_reg\,
      Q => \gen_mux_div4.gen_rd_4[4].mux_rd_rise3_r2_reg\,
      R => '0'
    );
\gen_mux_div4.gen_rd_4[4].mux_rd_rise3_r3_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => '1',
      D => \gen_mux_div4.gen_rd_4[4].mux_rd_rise3_r2_reg\,
      Q => p_1_in170_in(4),
      R => '0'
    );
\gen_mux_div4.gen_rd_4[5].mux_rd_fall0_r2_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => mux_rd_valid_r,
      D => \gen_mux_rd[5].mux_rd_fall0_r1_reg\,
      Q => \gen_mux_div4.gen_rd_4[5].mux_rd_fall0_r2_reg\,
      R => '0'
    );
\gen_mux_div4.gen_rd_4[5].mux_rd_fall0_r3_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => '1',
      D => \gen_mux_div4.gen_rd_4[5].mux_rd_fall0_r2_reg\,
      Q => p_1_in185_in(5),
      R => '0'
    );
\gen_mux_div4.gen_rd_4[5].mux_rd_fall1_r2_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => mux_rd_valid_r,
      D => \gen_mux_rd[5].mux_rd_fall1_r1_reg\,
      Q => \gen_mux_div4.gen_rd_4[5].mux_rd_fall1_r2_reg\,
      R => '0'
    );
\gen_mux_div4.gen_rd_4[5].mux_rd_fall1_r3_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => '1',
      D => \gen_mux_div4.gen_rd_4[5].mux_rd_fall1_r2_reg\,
      Q => p_1_in179_in(5),
      R => '0'
    );
\gen_mux_div4.gen_rd_4[5].mux_rd_fall2_r2_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => mux_rd_valid_r,
      D => \gen_mux_rd[5].mux_rd_fall2_r1_reg\,
      Q => \gen_mux_div4.gen_rd_4[5].mux_rd_fall2_r2_reg\,
      R => '0'
    );
\gen_mux_div4.gen_rd_4[5].mux_rd_fall2_r3_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => '1',
      D => \gen_mux_div4.gen_rd_4[5].mux_rd_fall2_r2_reg\,
      Q => p_1_in173_in(5),
      R => '0'
    );
\gen_mux_div4.gen_rd_4[5].mux_rd_fall3_r2_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => mux_rd_valid_r,
      D => \gen_mux_rd[5].mux_rd_fall3_r1_reg\,
      Q => \gen_mux_div4.gen_rd_4[5].mux_rd_fall3_r2_reg\,
      R => '0'
    );
\gen_mux_div4.gen_rd_4[5].mux_rd_fall3_r3_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => '1',
      D => \gen_mux_div4.gen_rd_4[5].mux_rd_fall3_r2_reg\,
      Q => p_1_in167_in(5),
      R => '0'
    );
\gen_mux_div4.gen_rd_4[5].mux_rd_rise0_r2_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => mux_rd_valid_r,
      D => \gen_mux_rd[5].mux_rd_rise0_r1_reg\,
      Q => \gen_mux_div4.gen_rd_4[5].mux_rd_rise0_r2_reg\,
      R => '0'
    );
\gen_mux_div4.gen_rd_4[5].mux_rd_rise0_r3_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => '1',
      D => \gen_mux_div4.gen_rd_4[5].mux_rd_rise0_r2_reg\,
      Q => p_1_in188_in(5),
      R => '0'
    );
\gen_mux_div4.gen_rd_4[5].mux_rd_rise1_r2_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => mux_rd_valid_r,
      D => \gen_mux_rd[5].mux_rd_rise1_r1_reg\,
      Q => \gen_mux_div4.gen_rd_4[5].mux_rd_rise1_r2_reg\,
      R => '0'
    );
\gen_mux_div4.gen_rd_4[5].mux_rd_rise1_r3_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => '1',
      D => \gen_mux_div4.gen_rd_4[5].mux_rd_rise1_r2_reg\,
      Q => p_1_in182_in(5),
      R => '0'
    );
\gen_mux_div4.gen_rd_4[5].mux_rd_rise2_r2_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => mux_rd_valid_r,
      D => \gen_mux_rd[5].mux_rd_rise2_r1_reg\,
      Q => \gen_mux_div4.gen_rd_4[5].mux_rd_rise2_r2_reg\,
      R => '0'
    );
\gen_mux_div4.gen_rd_4[5].mux_rd_rise2_r3_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => '1',
      D => \gen_mux_div4.gen_rd_4[5].mux_rd_rise2_r2_reg\,
      Q => p_1_in176_in(5),
      R => '0'
    );
\gen_mux_div4.gen_rd_4[5].mux_rd_rise3_r2_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => mux_rd_valid_r,
      D => \gen_mux_rd[5].mux_rd_rise3_r1_reg\,
      Q => \gen_mux_div4.gen_rd_4[5].mux_rd_rise3_r2_reg\,
      R => '0'
    );
\gen_mux_div4.gen_rd_4[5].mux_rd_rise3_r3_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => '1',
      D => \gen_mux_div4.gen_rd_4[5].mux_rd_rise3_r2_reg\,
      Q => p_1_in170_in(5),
      R => '0'
    );
\gen_mux_div4.gen_rd_4[6].mux_rd_fall0_r2_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => mux_rd_valid_r,
      D => \gen_mux_rd[6].mux_rd_fall0_r1_reg\,
      Q => \gen_mux_div4.gen_rd_4[6].mux_rd_fall0_r2_reg\,
      R => '0'
    );
\gen_mux_div4.gen_rd_4[6].mux_rd_fall0_r3_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => '1',
      D => \gen_mux_div4.gen_rd_4[6].mux_rd_fall0_r2_reg\,
      Q => p_1_in185_in(6),
      R => '0'
    );
\gen_mux_div4.gen_rd_4[6].mux_rd_fall1_r2_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => mux_rd_valid_r,
      D => \gen_mux_rd[6].mux_rd_fall1_r1_reg\,
      Q => \gen_mux_div4.gen_rd_4[6].mux_rd_fall1_r2_reg\,
      R => '0'
    );
\gen_mux_div4.gen_rd_4[6].mux_rd_fall1_r3_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => '1',
      D => \gen_mux_div4.gen_rd_4[6].mux_rd_fall1_r2_reg\,
      Q => p_1_in179_in(6),
      R => '0'
    );
\gen_mux_div4.gen_rd_4[6].mux_rd_fall2_r2_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => mux_rd_valid_r,
      D => \gen_mux_rd[6].mux_rd_fall2_r1_reg\,
      Q => \gen_mux_div4.gen_rd_4[6].mux_rd_fall2_r2_reg\,
      R => '0'
    );
\gen_mux_div4.gen_rd_4[6].mux_rd_fall2_r3_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => '1',
      D => \gen_mux_div4.gen_rd_4[6].mux_rd_fall2_r2_reg\,
      Q => p_1_in173_in(6),
      R => '0'
    );
\gen_mux_div4.gen_rd_4[6].mux_rd_fall3_r2_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => mux_rd_valid_r,
      D => \gen_mux_rd[6].mux_rd_fall3_r1_reg\,
      Q => \gen_mux_div4.gen_rd_4[6].mux_rd_fall3_r2_reg\,
      R => '0'
    );
\gen_mux_div4.gen_rd_4[6].mux_rd_fall3_r3_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => '1',
      D => \gen_mux_div4.gen_rd_4[6].mux_rd_fall3_r2_reg\,
      Q => p_1_in167_in(6),
      R => '0'
    );
\gen_mux_div4.gen_rd_4[6].mux_rd_rise0_r2_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => mux_rd_valid_r,
      D => \gen_mux_rd[6].mux_rd_rise0_r1_reg\,
      Q => \gen_mux_div4.gen_rd_4[6].mux_rd_rise0_r2_reg\,
      R => '0'
    );
\gen_mux_div4.gen_rd_4[6].mux_rd_rise0_r3_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => '1',
      D => \gen_mux_div4.gen_rd_4[6].mux_rd_rise0_r2_reg\,
      Q => p_1_in188_in(6),
      R => '0'
    );
\gen_mux_div4.gen_rd_4[6].mux_rd_rise1_r2_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => mux_rd_valid_r,
      D => \gen_mux_rd[6].mux_rd_rise1_r1_reg\,
      Q => \gen_mux_div4.gen_rd_4[6].mux_rd_rise1_r2_reg\,
      R => '0'
    );
\gen_mux_div4.gen_rd_4[6].mux_rd_rise1_r3_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => '1',
      D => \gen_mux_div4.gen_rd_4[6].mux_rd_rise1_r2_reg\,
      Q => p_1_in182_in(6),
      R => '0'
    );
\gen_mux_div4.gen_rd_4[6].mux_rd_rise2_r2_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => mux_rd_valid_r,
      D => \gen_mux_rd[6].mux_rd_rise2_r1_reg\,
      Q => \gen_mux_div4.gen_rd_4[6].mux_rd_rise2_r2_reg\,
      R => '0'
    );
\gen_mux_div4.gen_rd_4[6].mux_rd_rise2_r3_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => '1',
      D => \gen_mux_div4.gen_rd_4[6].mux_rd_rise2_r2_reg\,
      Q => p_1_in176_in(6),
      R => '0'
    );
\gen_mux_div4.gen_rd_4[6].mux_rd_rise3_r2_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => mux_rd_valid_r,
      D => \gen_mux_rd[6].mux_rd_rise3_r1_reg\,
      Q => \gen_mux_div4.gen_rd_4[6].mux_rd_rise3_r2_reg\,
      R => '0'
    );
\gen_mux_div4.gen_rd_4[6].mux_rd_rise3_r3_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => '1',
      D => \gen_mux_div4.gen_rd_4[6].mux_rd_rise3_r2_reg\,
      Q => p_1_in170_in(6),
      R => '0'
    );
\gen_mux_div4.gen_rd_4[7].mux_rd_fall0_r2_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => mux_rd_valid_r,
      D => \gen_mux_rd[7].mux_rd_fall0_r1_reg\,
      Q => \gen_mux_div4.gen_rd_4[7].mux_rd_fall0_r2_reg\,
      R => '0'
    );
\gen_mux_div4.gen_rd_4[7].mux_rd_fall0_r3_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => '1',
      D => \gen_mux_div4.gen_rd_4[7].mux_rd_fall0_r2_reg\,
      Q => p_1_in185_in(7),
      R => '0'
    );
\gen_mux_div4.gen_rd_4[7].mux_rd_fall1_r2_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => mux_rd_valid_r,
      D => \gen_mux_rd[7].mux_rd_fall1_r1_reg\,
      Q => \gen_mux_div4.gen_rd_4[7].mux_rd_fall1_r2_reg\,
      R => '0'
    );
\gen_mux_div4.gen_rd_4[7].mux_rd_fall1_r3_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => '1',
      D => \gen_mux_div4.gen_rd_4[7].mux_rd_fall1_r2_reg\,
      Q => p_1_in179_in(7),
      R => '0'
    );
\gen_mux_div4.gen_rd_4[7].mux_rd_fall2_r2_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => mux_rd_valid_r,
      D => \gen_mux_rd[7].mux_rd_fall2_r1_reg\,
      Q => \gen_mux_div4.gen_rd_4[7].mux_rd_fall2_r2_reg\,
      R => '0'
    );
\gen_mux_div4.gen_rd_4[7].mux_rd_fall2_r3_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => '1',
      D => \gen_mux_div4.gen_rd_4[7].mux_rd_fall2_r2_reg\,
      Q => p_1_in173_in(7),
      R => '0'
    );
\gen_mux_div4.gen_rd_4[7].mux_rd_fall3_r2_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => mux_rd_valid_r,
      D => \gen_mux_rd[7].mux_rd_fall3_r1_reg\,
      Q => \gen_mux_div4.gen_rd_4[7].mux_rd_fall3_r2_reg\,
      R => '0'
    );
\gen_mux_div4.gen_rd_4[7].mux_rd_fall3_r3_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => '1',
      D => \gen_mux_div4.gen_rd_4[7].mux_rd_fall3_r2_reg\,
      Q => p_1_in167_in(7),
      R => '0'
    );
\gen_mux_div4.gen_rd_4[7].mux_rd_rise0_r2_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => mux_rd_valid_r,
      D => \gen_mux_rd[7].mux_rd_rise0_r1_reg\,
      Q => \gen_mux_div4.gen_rd_4[7].mux_rd_rise0_r2_reg\,
      R => '0'
    );
\gen_mux_div4.gen_rd_4[7].mux_rd_rise0_r3_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => '1',
      D => \gen_mux_div4.gen_rd_4[7].mux_rd_rise0_r2_reg\,
      Q => p_1_in188_in(7),
      R => '0'
    );
\gen_mux_div4.gen_rd_4[7].mux_rd_rise1_r2_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => mux_rd_valid_r,
      D => \gen_mux_rd[7].mux_rd_rise1_r1_reg\,
      Q => \gen_mux_div4.gen_rd_4[7].mux_rd_rise1_r2_reg\,
      R => '0'
    );
\gen_mux_div4.gen_rd_4[7].mux_rd_rise1_r3_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => '1',
      D => \gen_mux_div4.gen_rd_4[7].mux_rd_rise1_r2_reg\,
      Q => p_1_in182_in(7),
      R => '0'
    );
\gen_mux_div4.gen_rd_4[7].mux_rd_rise2_r2_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => mux_rd_valid_r,
      D => \gen_mux_rd[7].mux_rd_rise2_r1_reg\,
      Q => \gen_mux_div4.gen_rd_4[7].mux_rd_rise2_r2_reg\,
      R => '0'
    );
\gen_mux_div4.gen_rd_4[7].mux_rd_rise2_r3_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => '1',
      D => \gen_mux_div4.gen_rd_4[7].mux_rd_rise2_r2_reg\,
      Q => p_1_in176_in(7),
      R => '0'
    );
\gen_mux_div4.gen_rd_4[7].mux_rd_rise3_r2_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => mux_rd_valid_r,
      D => \gen_mux_rd[7].mux_rd_rise3_r1_reg\,
      Q => \gen_mux_div4.gen_rd_4[7].mux_rd_rise3_r2_reg\,
      R => '0'
    );
\gen_mux_div4.gen_rd_4[7].mux_rd_rise3_r3_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => '1',
      D => \gen_mux_div4.gen_rd_4[7].mux_rd_rise3_r2_reg\,
      Q => p_1_in170_in(7),
      R => '0'
    );
\gen_mux_rd[0].compare_data_fall0_r1_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => '1',
      D => prbs_out(8),
      Q => p_0_in184_in(0),
      R => '0'
    );
\gen_mux_rd[0].compare_data_fall1_r1_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => '1',
      D => prbs_out(24),
      Q => p_0_in178_in(0),
      R => '0'
    );
\gen_mux_rd[0].compare_data_fall2_r1_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => '1',
      D => prbs_out(40),
      Q => p_0_in172_in(0),
      R => '0'
    );
\gen_mux_rd[0].compare_data_fall3_r1_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => '1',
      D => prbs_out(56),
      Q => p_0_in166_in(0),
      R => '0'
    );
\gen_mux_rd[0].compare_data_rise0_r1_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => '1',
      D => prbs_out(0),
      Q => p_0_in187_in(0),
      R => '0'
    );
\gen_mux_rd[0].compare_data_rise1_r1_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => '1',
      D => prbs_out(16),
      Q => p_0_in181_in(0),
      R => '0'
    );
\gen_mux_rd[0].compare_data_rise2_r1_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => '1',
      D => prbs_out(32),
      Q => p_0_in175_in(0),
      R => '0'
    );
\gen_mux_rd[0].compare_data_rise3_r1_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => '1',
      D => prbs_out(48),
      Q => p_0_in169_in(0),
      R => '0'
    );
\gen_mux_rd[0].mux_rd_fall0_r1_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => '1',
      D => \gen_mux_rd[0].mux_rd_fall0_r1_reg[0]_0\,
      Q => mux_rd_fall0_r1,
      R => '0'
    );
\gen_mux_rd[0].mux_rd_fall1_r1_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => '1',
      D => \gen_mux_rd[0].mux_rd_fall1_r1_reg[0]_0\,
      Q => mux_rd_fall1_r1,
      R => '0'
    );
\gen_mux_rd[0].mux_rd_fall2_r1_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => '1',
      D => \gen_mux_rd[0].mux_rd_fall2_r1_reg[0]_0\,
      Q => mux_rd_fall2_r1,
      R => '0'
    );
\gen_mux_rd[0].mux_rd_fall3_r1_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => '1',
      D => \gen_mux_rd[0].mux_rd_fall3_r1_reg[0]_0\,
      Q => mux_rd_fall3_r1,
      R => '0'
    );
\gen_mux_rd[0].mux_rd_rise0_r1_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => '1',
      D => \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]_0\,
      Q => mux_rd_rise0_r1,
      R => '0'
    );
\gen_mux_rd[0].mux_rd_rise1_r1_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => '1',
      D => \gen_mux_rd[0].mux_rd_rise1_r1_reg[0]_0\,
      Q => mux_rd_rise1_r1,
      R => '0'
    );
\gen_mux_rd[0].mux_rd_rise2_r1_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => '1',
      D => \gen_mux_rd[0].mux_rd_rise2_r1_reg[0]_0\,
      Q => mux_rd_rise2_r1,
      R => '0'
    );
\gen_mux_rd[0].mux_rd_rise3_r1_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => '1',
      D => \gen_mux_rd[0].mux_rd_rise3_r1_reg[0]_0\,
      Q => mux_rd_rise3_r1,
      R => '0'
    );
\gen_mux_rd[1].compare_data_fall0_r1_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => '1',
      D => prbs_out(9),
      Q => p_0_in184_in(1),
      R => '0'
    );
\gen_mux_rd[1].compare_data_fall1_r1_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => '1',
      D => prbs_out(25),
      Q => p_0_in178_in(1),
      R => '0'
    );
\gen_mux_rd[1].compare_data_fall2_r1_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => '1',
      D => prbs_out(41),
      Q => p_0_in172_in(1),
      R => '0'
    );
\gen_mux_rd[1].compare_data_fall3_r1_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => '1',
      D => prbs_out(57),
      Q => p_0_in166_in(1),
      R => '0'
    );
\gen_mux_rd[1].compare_data_rise0_r1_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => '1',
      D => prbs_out(1),
      Q => p_0_in187_in(1),
      R => '0'
    );
\gen_mux_rd[1].compare_data_rise1_r1_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => '1',
      D => prbs_out(17),
      Q => p_0_in181_in(1),
      R => '0'
    );
\gen_mux_rd[1].compare_data_rise2_r1_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => '1',
      D => prbs_out(33),
      Q => p_0_in175_in(1),
      R => '0'
    );
\gen_mux_rd[1].compare_data_rise3_r1_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => '1',
      D => prbs_out(49),
      Q => p_0_in169_in(1),
      R => '0'
    );
\gen_mux_rd[1].mux_rd_fall0_r1_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => '1',
      D => \gen_mux_rd[1].mux_rd_fall0_r1_reg[1]_0\,
      Q => \gen_mux_rd[1].mux_rd_fall0_r1_reg\,
      R => '0'
    );
\gen_mux_rd[1].mux_rd_fall1_r1_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => '1',
      D => \gen_mux_rd[1].mux_rd_fall1_r1_reg[1]_0\,
      Q => \gen_mux_rd[1].mux_rd_fall1_r1_reg\,
      R => '0'
    );
\gen_mux_rd[1].mux_rd_fall2_r1_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => '1',
      D => \gen_mux_rd[1].mux_rd_fall2_r1_reg[1]_0\,
      Q => \gen_mux_rd[1].mux_rd_fall2_r1_reg\,
      R => '0'
    );
\gen_mux_rd[1].mux_rd_fall3_r1_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => '1',
      D => \gen_mux_rd[1].mux_rd_fall3_r1_reg[1]_0\,
      Q => \gen_mux_rd[1].mux_rd_fall3_r1_reg\,
      R => '0'
    );
\gen_mux_rd[1].mux_rd_rise0_r1_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => '1',
      D => \gen_mux_rd[1].mux_rd_rise0_r1_reg[1]_0\,
      Q => \gen_mux_rd[1].mux_rd_rise0_r1_reg\,
      R => '0'
    );
\gen_mux_rd[1].mux_rd_rise1_r1_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => '1',
      D => \gen_mux_rd[1].mux_rd_rise1_r1_reg[1]_0\,
      Q => \gen_mux_rd[1].mux_rd_rise1_r1_reg\,
      R => '0'
    );
\gen_mux_rd[1].mux_rd_rise2_r1_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => '1',
      D => \gen_mux_rd[1].mux_rd_rise2_r1_reg[1]_0\,
      Q => \gen_mux_rd[1].mux_rd_rise2_r1_reg\,
      R => '0'
    );
\gen_mux_rd[1].mux_rd_rise3_r1_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => '1',
      D => \gen_mux_rd[1].mux_rd_rise3_r1_reg[1]_0\,
      Q => \gen_mux_rd[1].mux_rd_rise3_r1_reg\,
      R => '0'
    );
\gen_mux_rd[2].compare_data_fall0_r1_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => '1',
      D => prbs_out(10),
      Q => p_0_in184_in(2),
      R => '0'
    );
\gen_mux_rd[2].compare_data_fall1_r1_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => '1',
      D => prbs_out(26),
      Q => p_0_in178_in(2),
      R => '0'
    );
\gen_mux_rd[2].compare_data_fall2_r1_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => '1',
      D => prbs_out(42),
      Q => p_0_in172_in(2),
      R => '0'
    );
\gen_mux_rd[2].compare_data_fall3_r1_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => '1',
      D => prbs_out(58),
      Q => p_0_in166_in(2),
      R => '0'
    );
\gen_mux_rd[2].compare_data_rise0_r1_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => '1',
      D => prbs_out(2),
      Q => p_0_in187_in(2),
      R => '0'
    );
\gen_mux_rd[2].compare_data_rise1_r1_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => '1',
      D => prbs_out(18),
      Q => p_0_in181_in(2),
      R => '0'
    );
\gen_mux_rd[2].compare_data_rise2_r1_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => '1',
      D => prbs_out(34),
      Q => p_0_in175_in(2),
      R => '0'
    );
\gen_mux_rd[2].compare_data_rise3_r1_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => '1',
      D => prbs_out(50),
      Q => p_0_in169_in(2),
      R => '0'
    );
\gen_mux_rd[2].mux_rd_fall0_r1_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => '1',
      D => \gen_mux_rd[2].mux_rd_fall0_r1_reg[2]_0\,
      Q => \gen_mux_rd[2].mux_rd_fall0_r1_reg\,
      R => '0'
    );
\gen_mux_rd[2].mux_rd_fall1_r1_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => '1',
      D => \gen_mux_rd[2].mux_rd_fall1_r1_reg[2]_0\,
      Q => \gen_mux_rd[2].mux_rd_fall1_r1_reg\,
      R => '0'
    );
\gen_mux_rd[2].mux_rd_fall2_r1_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => '1',
      D => \gen_mux_rd[2].mux_rd_fall2_r1_reg[2]_0\,
      Q => \gen_mux_rd[2].mux_rd_fall2_r1_reg\,
      R => '0'
    );
\gen_mux_rd[2].mux_rd_fall3_r1_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => '1',
      D => \gen_mux_rd[2].mux_rd_fall3_r1_reg[2]_0\,
      Q => \gen_mux_rd[2].mux_rd_fall3_r1_reg\,
      R => '0'
    );
\gen_mux_rd[2].mux_rd_rise0_r1_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => '1',
      D => \gen_mux_rd[2].mux_rd_rise0_r1_reg[2]_0\,
      Q => \gen_mux_rd[2].mux_rd_rise0_r1_reg\,
      R => '0'
    );
\gen_mux_rd[2].mux_rd_rise1_r1_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => '1',
      D => \gen_mux_rd[2].mux_rd_rise1_r1_reg[2]_0\,
      Q => \gen_mux_rd[2].mux_rd_rise1_r1_reg\,
      R => '0'
    );
\gen_mux_rd[2].mux_rd_rise2_r1_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => '1',
      D => \gen_mux_rd[2].mux_rd_rise2_r1_reg[2]_0\,
      Q => \gen_mux_rd[2].mux_rd_rise2_r1_reg\,
      R => '0'
    );
\gen_mux_rd[2].mux_rd_rise3_r1_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => '1',
      D => \gen_mux_rd[2].mux_rd_rise3_r1_reg[2]_0\,
      Q => \gen_mux_rd[2].mux_rd_rise3_r1_reg\,
      R => '0'
    );
\gen_mux_rd[3].compare_data_fall0_r1_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => '1',
      D => prbs_out(11),
      Q => p_0_in184_in(3),
      R => '0'
    );
\gen_mux_rd[3].compare_data_fall1_r1_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => '1',
      D => prbs_out(27),
      Q => p_0_in178_in(3),
      R => '0'
    );
\gen_mux_rd[3].compare_data_fall2_r1_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => '1',
      D => prbs_out(43),
      Q => p_0_in172_in(3),
      R => '0'
    );
\gen_mux_rd[3].compare_data_fall3_r1_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => '1',
      D => prbs_out(59),
      Q => p_0_in166_in(3),
      R => '0'
    );
\gen_mux_rd[3].compare_data_rise0_r1_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => '1',
      D => prbs_out(3),
      Q => p_0_in187_in(3),
      R => '0'
    );
\gen_mux_rd[3].compare_data_rise1_r1_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => '1',
      D => prbs_out(19),
      Q => p_0_in181_in(3),
      R => '0'
    );
\gen_mux_rd[3].compare_data_rise2_r1_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => '1',
      D => prbs_out(35),
      Q => p_0_in175_in(3),
      R => '0'
    );
\gen_mux_rd[3].compare_data_rise3_r1_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => '1',
      D => prbs_out(51),
      Q => p_0_in169_in(3),
      R => '0'
    );
\gen_mux_rd[3].mux_rd_fall0_r1_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => '1',
      D => \gen_mux_rd[3].mux_rd_fall0_r1_reg[3]_0\,
      Q => \gen_mux_rd[3].mux_rd_fall0_r1_reg\,
      R => '0'
    );
\gen_mux_rd[3].mux_rd_fall1_r1_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => '1',
      D => \gen_mux_rd[3].mux_rd_fall1_r1_reg[3]_0\,
      Q => \gen_mux_rd[3].mux_rd_fall1_r1_reg\,
      R => '0'
    );
\gen_mux_rd[3].mux_rd_fall2_r1_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => '1',
      D => \gen_mux_rd[3].mux_rd_fall2_r1_reg[3]_0\,
      Q => \gen_mux_rd[3].mux_rd_fall2_r1_reg\,
      R => '0'
    );
\gen_mux_rd[3].mux_rd_fall3_r1_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => '1',
      D => \gen_mux_rd[3].mux_rd_fall3_r1_reg[3]_0\,
      Q => \gen_mux_rd[3].mux_rd_fall3_r1_reg\,
      R => '0'
    );
\gen_mux_rd[3].mux_rd_rise0_r1_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => '1',
      D => \gen_mux_rd[3].mux_rd_rise0_r1_reg[3]_0\,
      Q => \gen_mux_rd[3].mux_rd_rise0_r1_reg\,
      R => '0'
    );
\gen_mux_rd[3].mux_rd_rise1_r1_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => '1',
      D => \gen_mux_rd[3].mux_rd_rise1_r1_reg[3]_0\,
      Q => \gen_mux_rd[3].mux_rd_rise1_r1_reg\,
      R => '0'
    );
\gen_mux_rd[3].mux_rd_rise2_r1_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => '1',
      D => \gen_mux_rd[3].mux_rd_rise2_r1_reg[3]_0\,
      Q => \gen_mux_rd[3].mux_rd_rise2_r1_reg\,
      R => '0'
    );
\gen_mux_rd[3].mux_rd_rise3_r1_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => '1',
      D => \gen_mux_rd[3].mux_rd_rise3_r1_reg[3]_0\,
      Q => \gen_mux_rd[3].mux_rd_rise3_r1_reg\,
      R => '0'
    );
\gen_mux_rd[4].compare_data_fall0_r1_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => '1',
      D => prbs_out(12),
      Q => p_0_in184_in(4),
      R => '0'
    );
\gen_mux_rd[4].compare_data_fall1_r1_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => '1',
      D => prbs_out(28),
      Q => p_0_in178_in(4),
      R => '0'
    );
\gen_mux_rd[4].compare_data_fall2_r1_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => '1',
      D => prbs_out(44),
      Q => p_0_in172_in(4),
      R => '0'
    );
\gen_mux_rd[4].compare_data_fall3_r1_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => '1',
      D => prbs_out(60),
      Q => p_0_in166_in(4),
      R => '0'
    );
\gen_mux_rd[4].compare_data_rise0_r1_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => '1',
      D => prbs_out(4),
      Q => p_0_in187_in(4),
      R => '0'
    );
\gen_mux_rd[4].compare_data_rise1_r1_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => '1',
      D => prbs_out(20),
      Q => p_0_in181_in(4),
      R => '0'
    );
\gen_mux_rd[4].compare_data_rise2_r1_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => '1',
      D => prbs_out(36),
      Q => p_0_in175_in(4),
      R => '0'
    );
\gen_mux_rd[4].compare_data_rise3_r1_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => '1',
      D => prbs_out(52),
      Q => p_0_in169_in(4),
      R => '0'
    );
\gen_mux_rd[4].mux_rd_fall0_r1_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => '1',
      D => \gen_mux_rd[4].mux_rd_fall0_r1_reg[4]_0\,
      Q => \gen_mux_rd[4].mux_rd_fall0_r1_reg\,
      R => '0'
    );
\gen_mux_rd[4].mux_rd_fall1_r1_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => '1',
      D => \gen_mux_rd[4].mux_rd_fall1_r1_reg[4]_0\,
      Q => \gen_mux_rd[4].mux_rd_fall1_r1_reg\,
      R => '0'
    );
\gen_mux_rd[4].mux_rd_fall2_r1_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => '1',
      D => \gen_mux_rd[4].mux_rd_fall2_r1_reg[4]_0\,
      Q => \gen_mux_rd[4].mux_rd_fall2_r1_reg\,
      R => '0'
    );
\gen_mux_rd[4].mux_rd_fall3_r1_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => '1',
      D => \gen_mux_rd[4].mux_rd_fall3_r1_reg[4]_0\,
      Q => \gen_mux_rd[4].mux_rd_fall3_r1_reg\,
      R => '0'
    );
\gen_mux_rd[4].mux_rd_rise0_r1_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => '1',
      D => \gen_mux_rd[4].mux_rd_rise0_r1_reg[4]_0\,
      Q => \gen_mux_rd[4].mux_rd_rise0_r1_reg\,
      R => '0'
    );
\gen_mux_rd[4].mux_rd_rise1_r1_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => '1',
      D => \gen_mux_rd[4].mux_rd_rise1_r1_reg[4]_0\,
      Q => \gen_mux_rd[4].mux_rd_rise1_r1_reg\,
      R => '0'
    );
\gen_mux_rd[4].mux_rd_rise2_r1_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => '1',
      D => \gen_mux_rd[4].mux_rd_rise2_r1_reg[4]_0\,
      Q => \gen_mux_rd[4].mux_rd_rise2_r1_reg\,
      R => '0'
    );
\gen_mux_rd[4].mux_rd_rise3_r1_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => '1',
      D => \gen_mux_rd[4].mux_rd_rise3_r1_reg[4]_0\,
      Q => \gen_mux_rd[4].mux_rd_rise3_r1_reg\,
      R => '0'
    );
\gen_mux_rd[5].compare_data_fall0_r1_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => '1',
      D => prbs_out(13),
      Q => p_0_in184_in(5),
      R => '0'
    );
\gen_mux_rd[5].compare_data_fall1_r1_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => '1',
      D => prbs_out(29),
      Q => p_0_in178_in(5),
      R => '0'
    );
\gen_mux_rd[5].compare_data_fall2_r1_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => '1',
      D => prbs_out(45),
      Q => p_0_in172_in(5),
      R => '0'
    );
\gen_mux_rd[5].compare_data_fall3_r1_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => '1',
      D => prbs_out(61),
      Q => p_0_in166_in(5),
      R => '0'
    );
\gen_mux_rd[5].compare_data_rise0_r1_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => '1',
      D => prbs_out(5),
      Q => p_0_in187_in(5),
      R => '0'
    );
\gen_mux_rd[5].compare_data_rise1_r1_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => '1',
      D => prbs_out(21),
      Q => p_0_in181_in(5),
      R => '0'
    );
\gen_mux_rd[5].compare_data_rise2_r1_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => '1',
      D => prbs_out(37),
      Q => p_0_in175_in(5),
      R => '0'
    );
\gen_mux_rd[5].compare_data_rise3_r1_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => '1',
      D => prbs_out(53),
      Q => p_0_in169_in(5),
      R => '0'
    );
\gen_mux_rd[5].mux_rd_fall0_r1_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => '1',
      D => \gen_mux_rd[5].mux_rd_fall0_r1_reg[5]_0\,
      Q => \gen_mux_rd[5].mux_rd_fall0_r1_reg\,
      R => '0'
    );
\gen_mux_rd[5].mux_rd_fall1_r1_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => '1',
      D => \gen_mux_rd[5].mux_rd_fall1_r1_reg[5]_0\,
      Q => \gen_mux_rd[5].mux_rd_fall1_r1_reg\,
      R => '0'
    );
\gen_mux_rd[5].mux_rd_fall2_r1_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => '1',
      D => \gen_mux_rd[5].mux_rd_fall2_r1_reg[5]_0\,
      Q => \gen_mux_rd[5].mux_rd_fall2_r1_reg\,
      R => '0'
    );
\gen_mux_rd[5].mux_rd_fall3_r1_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => '1',
      D => \gen_mux_rd[5].mux_rd_fall3_r1_reg[5]_0\,
      Q => \gen_mux_rd[5].mux_rd_fall3_r1_reg\,
      R => '0'
    );
\gen_mux_rd[5].mux_rd_rise0_r1_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => '1',
      D => \gen_mux_rd[5].mux_rd_rise0_r1_reg[5]_0\,
      Q => \gen_mux_rd[5].mux_rd_rise0_r1_reg\,
      R => '0'
    );
\gen_mux_rd[5].mux_rd_rise1_r1_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => '1',
      D => \gen_mux_rd[5].mux_rd_rise1_r1_reg[5]_0\,
      Q => \gen_mux_rd[5].mux_rd_rise1_r1_reg\,
      R => '0'
    );
\gen_mux_rd[5].mux_rd_rise2_r1_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => '1',
      D => \gen_mux_rd[5].mux_rd_rise2_r1_reg[5]_0\,
      Q => \gen_mux_rd[5].mux_rd_rise2_r1_reg\,
      R => '0'
    );
\gen_mux_rd[5].mux_rd_rise3_r1_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => '1',
      D => \gen_mux_rd[5].mux_rd_rise3_r1_reg[5]_0\,
      Q => \gen_mux_rd[5].mux_rd_rise3_r1_reg\,
      R => '0'
    );
\gen_mux_rd[6].compare_data_fall0_r1_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => '1',
      D => prbs_out(14),
      Q => p_0_in184_in(6),
      R => '0'
    );
\gen_mux_rd[6].compare_data_fall1_r1_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => '1',
      D => prbs_out(30),
      Q => p_0_in178_in(6),
      R => '0'
    );
\gen_mux_rd[6].compare_data_fall2_r1_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => '1',
      D => prbs_out(46),
      Q => p_0_in172_in(6),
      R => '0'
    );
\gen_mux_rd[6].compare_data_fall3_r1_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => '1',
      D => prbs_out(62),
      Q => p_0_in166_in(6),
      R => '0'
    );
\gen_mux_rd[6].compare_data_rise0_r1_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => '1',
      D => prbs_out(6),
      Q => p_0_in187_in(6),
      R => '0'
    );
\gen_mux_rd[6].compare_data_rise1_r1_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => '1',
      D => prbs_out(22),
      Q => p_0_in181_in(6),
      R => '0'
    );
\gen_mux_rd[6].compare_data_rise2_r1_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => '1',
      D => prbs_out(38),
      Q => p_0_in175_in(6),
      R => '0'
    );
\gen_mux_rd[6].compare_data_rise3_r1_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => '1',
      D => prbs_out(54),
      Q => p_0_in169_in(6),
      R => '0'
    );
\gen_mux_rd[6].mux_rd_fall0_r1_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => '1',
      D => \gen_mux_rd[6].mux_rd_fall0_r1_reg[6]_0\,
      Q => \gen_mux_rd[6].mux_rd_fall0_r1_reg\,
      R => '0'
    );
\gen_mux_rd[6].mux_rd_fall1_r1_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => '1',
      D => \gen_mux_rd[6].mux_rd_fall1_r1_reg[6]_0\,
      Q => \gen_mux_rd[6].mux_rd_fall1_r1_reg\,
      R => '0'
    );
\gen_mux_rd[6].mux_rd_fall2_r1_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => '1',
      D => \gen_mux_rd[6].mux_rd_fall2_r1_reg[6]_0\,
      Q => \gen_mux_rd[6].mux_rd_fall2_r1_reg\,
      R => '0'
    );
\gen_mux_rd[6].mux_rd_fall3_r1_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => '1',
      D => \gen_mux_rd[6].mux_rd_fall3_r1_reg[6]_0\,
      Q => \gen_mux_rd[6].mux_rd_fall3_r1_reg\,
      R => '0'
    );
\gen_mux_rd[6].mux_rd_rise0_r1_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => '1',
      D => \gen_mux_rd[6].mux_rd_rise0_r1_reg[6]_0\,
      Q => \gen_mux_rd[6].mux_rd_rise0_r1_reg\,
      R => '0'
    );
\gen_mux_rd[6].mux_rd_rise1_r1_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => '1',
      D => \gen_mux_rd[6].mux_rd_rise1_r1_reg[6]_0\,
      Q => \gen_mux_rd[6].mux_rd_rise1_r1_reg\,
      R => '0'
    );
\gen_mux_rd[6].mux_rd_rise2_r1_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => '1',
      D => \gen_mux_rd[6].mux_rd_rise2_r1_reg[6]_0\,
      Q => \gen_mux_rd[6].mux_rd_rise2_r1_reg\,
      R => '0'
    );
\gen_mux_rd[6].mux_rd_rise3_r1_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => '1',
      D => \gen_mux_rd[6].mux_rd_rise3_r1_reg[6]_0\,
      Q => \gen_mux_rd[6].mux_rd_rise3_r1_reg\,
      R => '0'
    );
\gen_mux_rd[7].compare_data_fall0_r1_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => '1',
      D => prbs_out(15),
      Q => p_0_in184_in(7),
      R => '0'
    );
\gen_mux_rd[7].compare_data_fall1_r1_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => '1',
      D => prbs_out(31),
      Q => p_0_in178_in(7),
      R => '0'
    );
\gen_mux_rd[7].compare_data_fall2_r1_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => '1',
      D => prbs_out(47),
      Q => p_0_in172_in(7),
      R => '0'
    );
\gen_mux_rd[7].compare_data_fall3_r1_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => '1',
      D => prbs_out(63),
      Q => p_0_in166_in(7),
      R => '0'
    );
\gen_mux_rd[7].compare_data_rise0_r1_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => '1',
      D => prbs_out(7),
      Q => p_0_in187_in(7),
      R => '0'
    );
\gen_mux_rd[7].compare_data_rise1_r1_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => '1',
      D => prbs_out(23),
      Q => p_0_in181_in(7),
      R => '0'
    );
\gen_mux_rd[7].compare_data_rise2_r1_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => '1',
      D => prbs_out(39),
      Q => p_0_in175_in(7),
      R => '0'
    );
\gen_mux_rd[7].compare_data_rise3_r1_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => '1',
      D => prbs_out(55),
      Q => p_0_in169_in(7),
      R => '0'
    );
\gen_mux_rd[7].mux_rd_fall0_r1_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => '1',
      D => \gen_mux_rd[7].mux_rd_fall0_r1_reg[7]_0\,
      Q => \gen_mux_rd[7].mux_rd_fall0_r1_reg\,
      R => '0'
    );
\gen_mux_rd[7].mux_rd_fall1_r1_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => '1',
      D => \gen_mux_rd[7].mux_rd_fall1_r1_reg[7]_0\,
      Q => \gen_mux_rd[7].mux_rd_fall1_r1_reg\,
      R => '0'
    );
\gen_mux_rd[7].mux_rd_fall2_r1_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => '1',
      D => \gen_mux_rd[7].mux_rd_fall2_r1_reg[7]_0\,
      Q => \gen_mux_rd[7].mux_rd_fall2_r1_reg\,
      R => '0'
    );
\gen_mux_rd[7].mux_rd_fall3_r1_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => '1',
      D => \gen_mux_rd[7].mux_rd_fall3_r1_reg[7]_0\,
      Q => \gen_mux_rd[7].mux_rd_fall3_r1_reg\,
      R => '0'
    );
\gen_mux_rd[7].mux_rd_rise0_r1_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => '1',
      D => \gen_mux_rd[7].mux_rd_rise0_r1_reg[7]_0\,
      Q => \gen_mux_rd[7].mux_rd_rise0_r1_reg\,
      R => '0'
    );
\gen_mux_rd[7].mux_rd_rise1_r1_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => '1',
      D => \gen_mux_rd[7].mux_rd_rise1_r1_reg[7]_0\,
      Q => \gen_mux_rd[7].mux_rd_rise1_r1_reg\,
      R => '0'
    );
\gen_mux_rd[7].mux_rd_rise2_r1_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => '1',
      D => \gen_mux_rd[7].mux_rd_rise2_r1_reg[7]_0\,
      Q => \gen_mux_rd[7].mux_rd_rise2_r1_reg\,
      R => '0'
    );
\gen_mux_rd[7].mux_rd_rise3_r1_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => '1',
      D => \gen_mux_rd[7].mux_rd_rise3_r1_reg[7]_0\,
      Q => \gen_mux_rd[7].mux_rd_rise3_r1_reg\,
      R => '0'
    );
\genblk7[0].compare_err_pb_latch_r[0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00F0002000000100"
    )
        port map (
      I0 => prbs_state_r(1),
      I1 => cnt_wait_state,
      I2 => prbs_state_r(3),
      I3 => prbs_state_r(4),
      I4 => prbs_state_r(0),
      I5 => prbs_state_r(2),
      O => \genblk7[0].compare_err_pb_latch_r[0]_i_1_n_0\
    );
\genblk7[0].compare_err_pb_latch_r[0]_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => compare_err_pb(0),
      I1 => \genblk7[0].compare_err_pb_latch_r_reg_n_0_[0]\,
      O => \genblk7[0].compare_err_pb_latch_r[0]_i_2_n_0\
    );
\genblk7[0].compare_err_pb_latch_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => '1',
      D => \genblk7[0].compare_err_pb_latch_r[0]_i_2_n_0\,
      Q => \genblk7[0].compare_err_pb_latch_r_reg_n_0_[0]\,
      R => \genblk7[0].compare_err_pb_latch_r[0]_i_1_n_0\
    );
\genblk7[1].compare_err_pb_latch_r[1]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => compare_err_pb(1),
      I1 => \genblk7[1].compare_err_pb_latch_r_reg_n_0_[1]\,
      O => \genblk7[1].compare_err_pb_latch_r[1]_i_1_n_0\
    );
\genblk7[1].compare_err_pb_latch_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => '1',
      D => \genblk7[1].compare_err_pb_latch_r[1]_i_1_n_0\,
      Q => \genblk7[1].compare_err_pb_latch_r_reg_n_0_[1]\,
      R => \genblk7[0].compare_err_pb_latch_r[0]_i_1_n_0\
    );
\genblk7[2].compare_err_pb_latch_r[2]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => compare_err_pb(2),
      I1 => \genblk7[2].compare_err_pb_latch_r_reg_n_0_[2]\,
      O => \genblk7[2].compare_err_pb_latch_r[2]_i_1_n_0\
    );
\genblk7[2].compare_err_pb_latch_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => '1',
      D => \genblk7[2].compare_err_pb_latch_r[2]_i_1_n_0\,
      Q => \genblk7[2].compare_err_pb_latch_r_reg_n_0_[2]\,
      R => \genblk7[0].compare_err_pb_latch_r[0]_i_1_n_0\
    );
\genblk7[3].compare_err_pb_latch_r[3]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => compare_err_pb(3),
      I1 => \genblk7[3].compare_err_pb_latch_r_reg_n_0_[3]\,
      O => \genblk7[3].compare_err_pb_latch_r[3]_i_1_n_0\
    );
\genblk7[3].compare_err_pb_latch_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => '1',
      D => \genblk7[3].compare_err_pb_latch_r[3]_i_1_n_0\,
      Q => \genblk7[3].compare_err_pb_latch_r_reg_n_0_[3]\,
      R => \genblk7[0].compare_err_pb_latch_r[0]_i_1_n_0\
    );
\genblk7[4].compare_err_pb_latch_r[4]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => compare_err_pb(4),
      I1 => \genblk7[4].compare_err_pb_latch_r_reg_n_0_[4]\,
      O => \genblk7[4].compare_err_pb_latch_r[4]_i_1_n_0\
    );
\genblk7[4].compare_err_pb_latch_r_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => '1',
      D => \genblk7[4].compare_err_pb_latch_r[4]_i_1_n_0\,
      Q => \genblk7[4].compare_err_pb_latch_r_reg_n_0_[4]\,
      R => \genblk7[0].compare_err_pb_latch_r[0]_i_1_n_0\
    );
\genblk7[5].compare_err_pb_latch_r[5]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => compare_err_pb(5),
      I1 => \genblk7[5].compare_err_pb_latch_r_reg_n_0_[5]\,
      O => \genblk7[5].compare_err_pb_latch_r[5]_i_1_n_0\
    );
\genblk7[5].compare_err_pb_latch_r_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => '1',
      D => \genblk7[5].compare_err_pb_latch_r[5]_i_1_n_0\,
      Q => \genblk7[5].compare_err_pb_latch_r_reg_n_0_[5]\,
      R => \genblk7[0].compare_err_pb_latch_r[0]_i_1_n_0\
    );
\genblk7[6].compare_err_pb_latch_r[6]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => compare_err_pb(6),
      I1 => \genblk7[6].compare_err_pb_latch_r_reg_n_0_[6]\,
      O => \genblk7[6].compare_err_pb_latch_r[6]_i_1_n_0\
    );
\genblk7[6].compare_err_pb_latch_r_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => '1',
      D => \genblk7[6].compare_err_pb_latch_r[6]_i_1_n_0\,
      Q => \genblk7[6].compare_err_pb_latch_r_reg_n_0_[6]\,
      R => \genblk7[0].compare_err_pb_latch_r[0]_i_1_n_0\
    );
\genblk7[7].compare_err_pb_latch_r[7]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => compare_err_pb(7),
      I1 => \genblk7[7].compare_err_pb_latch_r_reg_n_0_[7]\,
      O => \genblk7[7].compare_err_pb_latch_r[7]_i_1_n_0\
    );
\genblk7[7].compare_err_pb_latch_r_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => '1',
      D => \genblk7[7].compare_err_pb_latch_r[7]_i_1_n_0\,
      Q => \genblk7[7].compare_err_pb_latch_r_reg_n_0_[7]\,
      R => \genblk7[0].compare_err_pb_latch_r[0]_i_1_n_0\
    );
\genblk8[0].left_edge_updated[0]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88BF8880"
    )
        port map (
      I0 => \genblk8[0].left_edge_updated[0]_i_2_n_0\,
      I1 => p_154_out,
      I2 => \genblk8[0].right_edge_found_pb[0]_i_3_n_0\,
      I3 => \cmp_err_pb_4to1.(null)[0].compare_err_pb[0]_i_3_n_0\,
      I4 => left_edge_updated(0),
      O => \genblk8[0].left_edge_updated[0]_i_1_n_0\
    );
\genblk8[0].left_edge_updated[0]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000000100"
    )
        port map (
      I0 => match_flag_pb(3),
      I1 => match_flag_pb(2),
      I2 => match_flag_pb(0),
      I3 => match_flag_pb(7),
      I4 => \genblk7[0].compare_err_pb_latch_r_reg_n_0_[0]\,
      I5 => \genblk8[0].right_edge_found_pb[0]_i_5_n_0\,
      O => \genblk8[0].left_edge_updated[0]_i_2_n_0\
    );
\genblk8[0].left_edge_updated_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => '1',
      D => \genblk8[0].left_edge_updated[0]_i_1_n_0\,
      Q => left_edge_updated(0),
      R => \bit_cnt[7]_i_1_n_0\
    );
\genblk8[0].match_flag_pb[7]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAAAAEABAAAA"
    )
        port map (
      I0 => \rd_victim_sel_reg[2]_1\,
      I1 => prbs_state_r(3),
      I2 => prbs_state_r(1),
      I3 => prbs_state_r(2),
      I4 => prbs_state_r(0),
      I5 => prbs_state_r(4),
      O => \genblk8[0].match_flag_pb[7]_i_1_n_0\
    );
\genblk8[0].match_flag_pb[7]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000800000000"
    )
        port map (
      I0 => prbs_state_r(0),
      I1 => \^num_samples_done_r\,
      I2 => prbs_state_r(1),
      I3 => prbs_state_r(3),
      I4 => prbs_state_r(2),
      I5 => prbs_state_r(4),
      O => p_154_out
    );
\genblk8[0].match_flag_pb_reg[0]\: unisim.vcomponents.FDSE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => p_154_out,
      D => \genblk7[0].compare_err_pb_latch_r_reg_n_0_[0]\,
      Q => match_flag_pb(0),
      S => \genblk8[0].match_flag_pb[7]_i_1_n_0\
    );
\genblk8[0].match_flag_pb_reg[1]\: unisim.vcomponents.FDSE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => p_154_out,
      D => match_flag_pb(0),
      Q => match_flag_pb(1),
      S => \genblk8[0].match_flag_pb[7]_i_1_n_0\
    );
\genblk8[0].match_flag_pb_reg[2]\: unisim.vcomponents.FDSE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => p_154_out,
      D => match_flag_pb(1),
      Q => match_flag_pb(2),
      S => \genblk8[0].match_flag_pb[7]_i_1_n_0\
    );
\genblk8[0].match_flag_pb_reg[3]\: unisim.vcomponents.FDSE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => p_154_out,
      D => match_flag_pb(2),
      Q => match_flag_pb(3),
      S => \genblk8[0].match_flag_pb[7]_i_1_n_0\
    );
\genblk8[0].match_flag_pb_reg[4]\: unisim.vcomponents.FDSE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => p_154_out,
      D => match_flag_pb(3),
      Q => match_flag_pb(4),
      S => \genblk8[0].match_flag_pb[7]_i_1_n_0\
    );
\genblk8[0].match_flag_pb_reg[5]\: unisim.vcomponents.FDSE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => p_154_out,
      D => match_flag_pb(4),
      Q => match_flag_pb(5),
      S => \genblk8[0].match_flag_pb[7]_i_1_n_0\
    );
\genblk8[0].match_flag_pb_reg[6]\: unisim.vcomponents.FDSE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => p_154_out,
      D => match_flag_pb(5),
      Q => match_flag_pb(6),
      S => \genblk8[0].match_flag_pb[7]_i_1_n_0\
    );
\genblk8[0].match_flag_pb_reg[7]\: unisim.vcomponents.FDSE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => p_154_out,
      D => match_flag_pb(6),
      Q => match_flag_pb(7),
      S => \genblk8[0].match_flag_pb[7]_i_1_n_0\
    );
\genblk8[0].right_edge_found_pb[0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"1F001F00AAAABFAA"
    )
        port map (
      I0 => \genblk8[0].right_edge_found_pb_reg_n_0_[0]\,
      I1 => prbs_dqs_tap_limit_r_i_2_n_0,
      I2 => \genblk8[0].right_edge_found_pb[0]_i_2_n_0\,
      I3 => p_154_out,
      I4 => \genblk8[0].right_edge_found_pb[0]_i_3_n_0\,
      I5 => \genblk8[0].right_edge_found_pb[0]_i_4_n_0\,
      O => \genblk8[0].right_edge_found_pb[0]_i_1_n_0\
    );
\genblk8[0].right_edge_found_pb[0]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFEFFFF"
    )
        port map (
      I0 => \genblk8[0].right_edge_found_pb[0]_i_5_n_0\,
      I1 => match_flag_pb(3),
      I2 => match_flag_pb(2),
      I3 => match_flag_pb(0),
      I4 => \genblk7[0].compare_err_pb_latch_r_reg_n_0_[0]\,
      I5 => match_flag_pb(7),
      O => \genblk8[0].right_edge_found_pb[0]_i_2_n_0\
    );
\genblk8[0].right_edge_found_pb[0]_i_3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0002"
    )
        port map (
      I0 => \genblk8[0].right_edge_found_pb[0]_i_6_n_0\,
      I1 => \genblk7[0].compare_err_pb_latch_r_reg_n_0_[0]\,
      I2 => match_flag_pb(0),
      I3 => match_flag_pb(1),
      O => \genblk8[0].right_edge_found_pb[0]_i_3_n_0\
    );
\genblk8[0].right_edge_found_pb[0]_i_4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00400000"
    )
        port map (
      I0 => prbs_state_r(4),
      I1 => prbs_state_r(0),
      I2 => prbs_state_r(2),
      I3 => prbs_state_r(1),
      I4 => prbs_state_r(3),
      O => \genblk8[0].right_edge_found_pb[0]_i_4_n_0\
    );
\genblk8[0].right_edge_found_pb[0]_i_5\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFFE"
    )
        port map (
      I0 => match_flag_pb(6),
      I1 => match_flag_pb(4),
      I2 => match_flag_pb(1),
      I3 => match_flag_pb(5),
      O => \genblk8[0].right_edge_found_pb[0]_i_5_n_0\
    );
\genblk8[0].right_edge_found_pb[0]_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000100000000"
    )
        port map (
      I0 => match_flag_pb(2),
      I1 => match_flag_pb(3),
      I2 => match_flag_pb(4),
      I3 => match_flag_pb(5),
      I4 => match_flag_pb(6),
      I5 => match_flag_pb(7),
      O => \genblk8[0].right_edge_found_pb[0]_i_6_n_0\
    );
\genblk8[0].right_edge_found_pb_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => '1',
      D => \genblk8[0].right_edge_found_pb[0]_i_1_n_0\,
      Q => \genblk8[0].right_edge_found_pb_reg_n_0_[0]\,
      R => \bit_cnt[7]_i_1_n_0\
    );
\genblk8[1].left_edge_updated[1]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8F88"
    )
        port map (
      I0 => p_154_out,
      I1 => \genblk8[1].right_edge_found_pb[1]_i_3_n_0\,
      I2 => \cmp_err_pb_4to1.(null)[0].compare_err_pb[0]_i_3_n_0\,
      I3 => left_edge_updated(1),
      O => \genblk8[1].left_edge_updated[1]_i_1_n_0\
    );
\genblk8[1].left_edge_updated_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => '1',
      D => \genblk8[1].left_edge_updated[1]_i_1_n_0\,
      Q => left_edge_updated(1),
      R => \bit_cnt[7]_i_1_n_0\
    );
\genblk8[1].match_flag_pb_reg[10]\: unisim.vcomponents.FDSE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => p_154_out,
      D => match_flag_pb(9),
      Q => match_flag_pb(10),
      S => \genblk8[0].match_flag_pb[7]_i_1_n_0\
    );
\genblk8[1].match_flag_pb_reg[11]\: unisim.vcomponents.FDSE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => p_154_out,
      D => match_flag_pb(10),
      Q => match_flag_pb(11),
      S => \genblk8[0].match_flag_pb[7]_i_1_n_0\
    );
\genblk8[1].match_flag_pb_reg[12]\: unisim.vcomponents.FDSE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => p_154_out,
      D => match_flag_pb(11),
      Q => match_flag_pb(12),
      S => \genblk8[0].match_flag_pb[7]_i_1_n_0\
    );
\genblk8[1].match_flag_pb_reg[13]\: unisim.vcomponents.FDSE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => p_154_out,
      D => match_flag_pb(12),
      Q => match_flag_pb(13),
      S => \genblk8[0].match_flag_pb[7]_i_1_n_0\
    );
\genblk8[1].match_flag_pb_reg[14]\: unisim.vcomponents.FDSE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => p_154_out,
      D => match_flag_pb(13),
      Q => match_flag_pb(14),
      S => \genblk8[0].match_flag_pb[7]_i_1_n_0\
    );
\genblk8[1].match_flag_pb_reg[15]\: unisim.vcomponents.FDSE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => p_154_out,
      D => match_flag_pb(14),
      Q => match_flag_pb(15),
      S => \genblk8[0].match_flag_pb[7]_i_1_n_0\
    );
\genblk8[1].match_flag_pb_reg[8]\: unisim.vcomponents.FDSE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => p_154_out,
      D => \genblk7[1].compare_err_pb_latch_r_reg_n_0_[1]\,
      Q => match_flag_pb(8),
      S => \genblk8[0].match_flag_pb[7]_i_1_n_0\
    );
\genblk8[1].match_flag_pb_reg[9]\: unisim.vcomponents.FDSE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => p_154_out,
      D => match_flag_pb(8),
      Q => match_flag_pb(9),
      S => \genblk8[0].match_flag_pb[7]_i_1_n_0\
    );
\genblk8[1].right_edge_found_pb[1]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"1F001F00AAAABFAA"
    )
        port map (
      I0 => \genblk8[1].right_edge_found_pb_reg_n_0_[1]\,
      I1 => prbs_dqs_tap_limit_r_i_2_n_0,
      I2 => \genblk8[1].right_edge_found_pb[1]_i_2_n_0\,
      I3 => p_154_out,
      I4 => \genblk8[1].right_edge_found_pb[1]_i_3_n_0\,
      I5 => \genblk8[0].right_edge_found_pb[0]_i_4_n_0\,
      O => \genblk8[1].right_edge_found_pb[1]_i_1_n_0\
    );
\genblk8[1].right_edge_found_pb[1]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFEFFFF"
    )
        port map (
      I0 => \genblk8[1].right_edge_found_pb[1]_i_4_n_0\,
      I1 => match_flag_pb(11),
      I2 => match_flag_pb(10),
      I3 => match_flag_pb(8),
      I4 => \genblk7[1].compare_err_pb_latch_r_reg_n_0_[1]\,
      I5 => match_flag_pb(15),
      O => \genblk8[1].right_edge_found_pb[1]_i_2_n_0\
    );
\genblk8[1].right_edge_found_pb[1]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000000100"
    )
        port map (
      I0 => match_flag_pb(11),
      I1 => match_flag_pb(10),
      I2 => match_flag_pb(8),
      I3 => match_flag_pb(15),
      I4 => \genblk7[1].compare_err_pb_latch_r_reg_n_0_[1]\,
      I5 => \genblk8[1].right_edge_found_pb[1]_i_4_n_0\,
      O => \genblk8[1].right_edge_found_pb[1]_i_3_n_0\
    );
\genblk8[1].right_edge_found_pb[1]_i_4\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFFE"
    )
        port map (
      I0 => match_flag_pb(14),
      I1 => match_flag_pb(12),
      I2 => match_flag_pb(9),
      I3 => match_flag_pb(13),
      O => \genblk8[1].right_edge_found_pb[1]_i_4_n_0\
    );
\genblk8[1].right_edge_found_pb_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => '1',
      D => \genblk8[1].right_edge_found_pb[1]_i_1_n_0\,
      Q => \genblk8[1].right_edge_found_pb_reg_n_0_[1]\,
      R => \bit_cnt[7]_i_1_n_0\
    );
\genblk8[2].left_edge_updated[2]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FBFFFFFFAAAAAAAA"
    )
        port map (
      I0 => left_edge_found_pb85_out,
      I1 => prbs_state_r(3),
      I2 => prbs_state_r(4),
      I3 => prbs_state_r(0),
      I4 => prbs_state_r(2),
      I5 => left_edge_updated(2),
      O => \genblk8[2].left_edge_updated[2]_i_1_n_0\
    );
\genblk8[2].left_edge_updated[2]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000000200"
    )
        port map (
      I0 => p_154_out,
      I1 => match_flag_pb(16),
      I2 => match_flag_pb(17),
      I3 => match_flag_pb(23),
      I4 => \genblk7[2].compare_err_pb_latch_r_reg_n_0_[2]\,
      I5 => \genblk8[2].right_edge_found_pb[2]_i_4_n_0\,
      O => left_edge_found_pb85_out
    );
\genblk8[2].left_edge_updated_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => '1',
      D => \genblk8[2].left_edge_updated[2]_i_1_n_0\,
      Q => left_edge_updated(2),
      R => \bit_cnt[7]_i_1_n_0\
    );
\genblk8[2].match_flag_pb_reg[16]\: unisim.vcomponents.FDSE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => p_154_out,
      D => \genblk7[2].compare_err_pb_latch_r_reg_n_0_[2]\,
      Q => match_flag_pb(16),
      S => \genblk8[0].match_flag_pb[7]_i_1_n_0\
    );
\genblk8[2].match_flag_pb_reg[17]\: unisim.vcomponents.FDSE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => p_154_out,
      D => match_flag_pb(16),
      Q => match_flag_pb(17),
      S => \genblk8[0].match_flag_pb[7]_i_1_n_0\
    );
\genblk8[2].match_flag_pb_reg[18]\: unisim.vcomponents.FDSE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => p_154_out,
      D => match_flag_pb(17),
      Q => match_flag_pb(18),
      S => \genblk8[0].match_flag_pb[7]_i_1_n_0\
    );
\genblk8[2].match_flag_pb_reg[19]\: unisim.vcomponents.FDSE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => p_154_out,
      D => match_flag_pb(18),
      Q => match_flag_pb(19),
      S => \genblk8[0].match_flag_pb[7]_i_1_n_0\
    );
\genblk8[2].match_flag_pb_reg[20]\: unisim.vcomponents.FDSE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => p_154_out,
      D => match_flag_pb(19),
      Q => match_flag_pb(20),
      S => \genblk8[0].match_flag_pb[7]_i_1_n_0\
    );
\genblk8[2].match_flag_pb_reg[21]\: unisim.vcomponents.FDSE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => p_154_out,
      D => match_flag_pb(20),
      Q => match_flag_pb(21),
      S => \genblk8[0].match_flag_pb[7]_i_1_n_0\
    );
\genblk8[2].match_flag_pb_reg[22]\: unisim.vcomponents.FDSE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => p_154_out,
      D => match_flag_pb(21),
      Q => match_flag_pb(22),
      S => \genblk8[0].match_flag_pb[7]_i_1_n_0\
    );
\genblk8[2].match_flag_pb_reg[23]\: unisim.vcomponents.FDSE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => p_154_out,
      D => match_flag_pb(22),
      Q => match_flag_pb(23),
      S => \genblk8[0].match_flag_pb[7]_i_1_n_0\
    );
\genblk8[2].right_edge_found_pb[2]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"1F1F0000BFAAAAAA"
    )
        port map (
      I0 => \genblk8[2].right_edge_found_pb_reg_n_0_[2]\,
      I1 => prbs_dqs_tap_limit_r_i_2_n_0,
      I2 => \genblk8[2].right_edge_found_pb[2]_i_2_n_0\,
      I3 => \genblk8[2].right_edge_found_pb[2]_i_3_n_0\,
      I4 => p_154_out,
      I5 => \genblk8[0].right_edge_found_pb[0]_i_4_n_0\,
      O => \genblk8[2].right_edge_found_pb[2]_i_1_n_0\
    );
\genblk8[2].right_edge_found_pb[2]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFFFEF"
    )
        port map (
      I0 => \genblk8[2].right_edge_found_pb[2]_i_4_n_0\,
      I1 => match_flag_pb(23),
      I2 => \genblk7[2].compare_err_pb_latch_r_reg_n_0_[2]\,
      I3 => match_flag_pb(17),
      I4 => match_flag_pb(16),
      O => \genblk8[2].right_edge_found_pb[2]_i_2_n_0\
    );
\genblk8[2].right_edge_found_pb[2]_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFFFEF"
    )
        port map (
      I0 => \genblk8[2].right_edge_found_pb[2]_i_4_n_0\,
      I1 => \genblk7[2].compare_err_pb_latch_r_reg_n_0_[2]\,
      I2 => match_flag_pb(23),
      I3 => match_flag_pb(17),
      I4 => match_flag_pb(16),
      O => \genblk8[2].right_edge_found_pb[2]_i_3_n_0\
    );
\genblk8[2].right_edge_found_pb[2]_i_4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFFFFE"
    )
        port map (
      I0 => match_flag_pb(22),
      I1 => match_flag_pb(18),
      I2 => match_flag_pb(19),
      I3 => match_flag_pb(21),
      I4 => match_flag_pb(20),
      O => \genblk8[2].right_edge_found_pb[2]_i_4_n_0\
    );
\genblk8[2].right_edge_found_pb_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => '1',
      D => \genblk8[2].right_edge_found_pb[2]_i_1_n_0\,
      Q => \genblk8[2].right_edge_found_pb_reg_n_0_[2]\,
      R => \bit_cnt[7]_i_1_n_0\
    );
\genblk8[3].left_edge_updated[3]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88BF8880"
    )
        port map (
      I0 => \genblk8[3].left_edge_updated[3]_i_2_n_0\,
      I1 => p_154_out,
      I2 => \genblk8[3].right_edge_found_pb[3]_i_3_n_0\,
      I3 => \cmp_err_pb_4to1.(null)[0].compare_err_pb[0]_i_3_n_0\,
      I4 => left_edge_updated(3),
      O => \genblk8[3].left_edge_updated[3]_i_1_n_0\
    );
\genblk8[3].left_edge_updated[3]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000000100"
    )
        port map (
      I0 => match_flag_pb(27),
      I1 => match_flag_pb(26),
      I2 => match_flag_pb(24),
      I3 => match_flag_pb(31),
      I4 => \genblk7[3].compare_err_pb_latch_r_reg_n_0_[3]\,
      I5 => \genblk8[3].right_edge_found_pb[3]_i_4_n_0\,
      O => \genblk8[3].left_edge_updated[3]_i_2_n_0\
    );
\genblk8[3].left_edge_updated_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => '1',
      D => \genblk8[3].left_edge_updated[3]_i_1_n_0\,
      Q => left_edge_updated(3),
      R => \bit_cnt[7]_i_1_n_0\
    );
\genblk8[3].match_flag_pb_reg[24]\: unisim.vcomponents.FDSE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => p_154_out,
      D => \genblk7[3].compare_err_pb_latch_r_reg_n_0_[3]\,
      Q => match_flag_pb(24),
      S => \genblk8[0].match_flag_pb[7]_i_1_n_0\
    );
\genblk8[3].match_flag_pb_reg[25]\: unisim.vcomponents.FDSE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => p_154_out,
      D => match_flag_pb(24),
      Q => match_flag_pb(25),
      S => \genblk8[0].match_flag_pb[7]_i_1_n_0\
    );
\genblk8[3].match_flag_pb_reg[26]\: unisim.vcomponents.FDSE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => p_154_out,
      D => match_flag_pb(25),
      Q => match_flag_pb(26),
      S => \genblk8[0].match_flag_pb[7]_i_1_n_0\
    );
\genblk8[3].match_flag_pb_reg[27]\: unisim.vcomponents.FDSE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => p_154_out,
      D => match_flag_pb(26),
      Q => match_flag_pb(27),
      S => \genblk8[0].match_flag_pb[7]_i_1_n_0\
    );
\genblk8[3].match_flag_pb_reg[28]\: unisim.vcomponents.FDSE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => p_154_out,
      D => match_flag_pb(27),
      Q => match_flag_pb(28),
      S => \genblk8[0].match_flag_pb[7]_i_1_n_0\
    );
\genblk8[3].match_flag_pb_reg[29]\: unisim.vcomponents.FDSE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => p_154_out,
      D => match_flag_pb(28),
      Q => match_flag_pb(29),
      S => \genblk8[0].match_flag_pb[7]_i_1_n_0\
    );
\genblk8[3].match_flag_pb_reg[30]\: unisim.vcomponents.FDSE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => p_154_out,
      D => match_flag_pb(29),
      Q => match_flag_pb(30),
      S => \genblk8[0].match_flag_pb[7]_i_1_n_0\
    );
\genblk8[3].match_flag_pb_reg[31]\: unisim.vcomponents.FDSE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => p_154_out,
      D => match_flag_pb(30),
      Q => match_flag_pb(31),
      S => \genblk8[0].match_flag_pb[7]_i_1_n_0\
    );
\genblk8[3].right_edge_found_pb[3]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"1F001F00AAAABFAA"
    )
        port map (
      I0 => \genblk8[3].right_edge_found_pb_reg_n_0_[3]\,
      I1 => prbs_dqs_tap_limit_r_i_2_n_0,
      I2 => \genblk8[3].right_edge_found_pb[3]_i_2_n_0\,
      I3 => p_154_out,
      I4 => \genblk8[3].right_edge_found_pb[3]_i_3_n_0\,
      I5 => \genblk8[0].right_edge_found_pb[0]_i_4_n_0\,
      O => \genblk8[3].right_edge_found_pb[3]_i_1_n_0\
    );
\genblk8[3].right_edge_found_pb[3]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFEFFFF"
    )
        port map (
      I0 => \genblk8[3].right_edge_found_pb[3]_i_4_n_0\,
      I1 => match_flag_pb(27),
      I2 => match_flag_pb(26),
      I3 => match_flag_pb(24),
      I4 => \genblk7[3].compare_err_pb_latch_r_reg_n_0_[3]\,
      I5 => match_flag_pb(31),
      O => \genblk8[3].right_edge_found_pb[3]_i_2_n_0\
    );
\genblk8[3].right_edge_found_pb[3]_i_3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0002"
    )
        port map (
      I0 => \genblk8[3].right_edge_found_pb[3]_i_5_n_0\,
      I1 => \genblk7[3].compare_err_pb_latch_r_reg_n_0_[3]\,
      I2 => match_flag_pb(24),
      I3 => match_flag_pb(25),
      O => \genblk8[3].right_edge_found_pb[3]_i_3_n_0\
    );
\genblk8[3].right_edge_found_pb[3]_i_4\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFFE"
    )
        port map (
      I0 => match_flag_pb(30),
      I1 => match_flag_pb(28),
      I2 => match_flag_pb(25),
      I3 => match_flag_pb(29),
      O => \genblk8[3].right_edge_found_pb[3]_i_4_n_0\
    );
\genblk8[3].right_edge_found_pb[3]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000100000000"
    )
        port map (
      I0 => match_flag_pb(26),
      I1 => match_flag_pb(27),
      I2 => match_flag_pb(28),
      I3 => match_flag_pb(29),
      I4 => match_flag_pb(30),
      I5 => match_flag_pb(31),
      O => \genblk8[3].right_edge_found_pb[3]_i_5_n_0\
    );
\genblk8[3].right_edge_found_pb_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => '1',
      D => \genblk8[3].right_edge_found_pb[3]_i_1_n_0\,
      Q => \genblk8[3].right_edge_found_pb_reg_n_0_[3]\,
      R => \bit_cnt[7]_i_1_n_0\
    );
\genblk8[4].left_edge_updated[4]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88BF8880"
    )
        port map (
      I0 => \genblk8[4].left_edge_updated[4]_i_2_n_0\,
      I1 => p_154_out,
      I2 => \genblk8[4].right_edge_found_pb[4]_i_3_n_0\,
      I3 => \cmp_err_pb_4to1.(null)[0].compare_err_pb[0]_i_3_n_0\,
      I4 => left_edge_updated(4),
      O => \genblk8[4].left_edge_updated[4]_i_1_n_0\
    );
\genblk8[4].left_edge_updated[4]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000000100"
    )
        port map (
      I0 => match_flag_pb(35),
      I1 => match_flag_pb(34),
      I2 => match_flag_pb(32),
      I3 => match_flag_pb(39),
      I4 => \genblk7[4].compare_err_pb_latch_r_reg_n_0_[4]\,
      I5 => \genblk8[4].right_edge_found_pb[4]_i_4_n_0\,
      O => \genblk8[4].left_edge_updated[4]_i_2_n_0\
    );
\genblk8[4].left_edge_updated_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => '1',
      D => \genblk8[4].left_edge_updated[4]_i_1_n_0\,
      Q => left_edge_updated(4),
      R => \bit_cnt[7]_i_1_n_0\
    );
\genblk8[4].match_flag_pb_reg[32]\: unisim.vcomponents.FDSE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => p_154_out,
      D => \genblk7[4].compare_err_pb_latch_r_reg_n_0_[4]\,
      Q => match_flag_pb(32),
      S => \genblk8[0].match_flag_pb[7]_i_1_n_0\
    );
\genblk8[4].match_flag_pb_reg[33]\: unisim.vcomponents.FDSE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => p_154_out,
      D => match_flag_pb(32),
      Q => match_flag_pb(33),
      S => \genblk8[0].match_flag_pb[7]_i_1_n_0\
    );
\genblk8[4].match_flag_pb_reg[34]\: unisim.vcomponents.FDSE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => p_154_out,
      D => match_flag_pb(33),
      Q => match_flag_pb(34),
      S => \genblk8[0].match_flag_pb[7]_i_1_n_0\
    );
\genblk8[4].match_flag_pb_reg[35]\: unisim.vcomponents.FDSE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => p_154_out,
      D => match_flag_pb(34),
      Q => match_flag_pb(35),
      S => \genblk8[0].match_flag_pb[7]_i_1_n_0\
    );
\genblk8[4].match_flag_pb_reg[36]\: unisim.vcomponents.FDSE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => p_154_out,
      D => match_flag_pb(35),
      Q => match_flag_pb(36),
      S => \genblk8[0].match_flag_pb[7]_i_1_n_0\
    );
\genblk8[4].match_flag_pb_reg[37]\: unisim.vcomponents.FDSE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => p_154_out,
      D => match_flag_pb(36),
      Q => match_flag_pb(37),
      S => \genblk8[0].match_flag_pb[7]_i_1_n_0\
    );
\genblk8[4].match_flag_pb_reg[38]\: unisim.vcomponents.FDSE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => p_154_out,
      D => match_flag_pb(37),
      Q => match_flag_pb(38),
      S => \genblk8[0].match_flag_pb[7]_i_1_n_0\
    );
\genblk8[4].match_flag_pb_reg[39]\: unisim.vcomponents.FDSE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => p_154_out,
      D => match_flag_pb(38),
      Q => match_flag_pb(39),
      S => \genblk8[0].match_flag_pb[7]_i_1_n_0\
    );
\genblk8[4].right_edge_found_pb[4]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"1F001F00AAAABFAA"
    )
        port map (
      I0 => \genblk8[4].right_edge_found_pb_reg_n_0_[4]\,
      I1 => prbs_dqs_tap_limit_r_i_2_n_0,
      I2 => \genblk8[4].right_edge_found_pb[4]_i_2_n_0\,
      I3 => p_154_out,
      I4 => \genblk8[4].right_edge_found_pb[4]_i_3_n_0\,
      I5 => \genblk8[0].right_edge_found_pb[0]_i_4_n_0\,
      O => \genblk8[4].right_edge_found_pb[4]_i_1_n_0\
    );
\genblk8[4].right_edge_found_pb[4]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFEFFFF"
    )
        port map (
      I0 => \genblk8[4].right_edge_found_pb[4]_i_4_n_0\,
      I1 => match_flag_pb(35),
      I2 => match_flag_pb(34),
      I3 => match_flag_pb(32),
      I4 => \genblk7[4].compare_err_pb_latch_r_reg_n_0_[4]\,
      I5 => match_flag_pb(39),
      O => \genblk8[4].right_edge_found_pb[4]_i_2_n_0\
    );
\genblk8[4].right_edge_found_pb[4]_i_3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0002"
    )
        port map (
      I0 => \genblk8[4].right_edge_found_pb[4]_i_5_n_0\,
      I1 => \genblk7[4].compare_err_pb_latch_r_reg_n_0_[4]\,
      I2 => match_flag_pb(32),
      I3 => match_flag_pb(33),
      O => \genblk8[4].right_edge_found_pb[4]_i_3_n_0\
    );
\genblk8[4].right_edge_found_pb[4]_i_4\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFFE"
    )
        port map (
      I0 => match_flag_pb(38),
      I1 => match_flag_pb(36),
      I2 => match_flag_pb(33),
      I3 => match_flag_pb(37),
      O => \genblk8[4].right_edge_found_pb[4]_i_4_n_0\
    );
\genblk8[4].right_edge_found_pb[4]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000100000000"
    )
        port map (
      I0 => match_flag_pb(34),
      I1 => match_flag_pb(35),
      I2 => match_flag_pb(36),
      I3 => match_flag_pb(37),
      I4 => match_flag_pb(38),
      I5 => match_flag_pb(39),
      O => \genblk8[4].right_edge_found_pb[4]_i_5_n_0\
    );
\genblk8[4].right_edge_found_pb_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => '1',
      D => \genblk8[4].right_edge_found_pb[4]_i_1_n_0\,
      Q => \genblk8[4].right_edge_found_pb_reg_n_0_[4]\,
      R => \bit_cnt[7]_i_1_n_0\
    );
\genblk8[5].left_edge_updated[5]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88BF8880"
    )
        port map (
      I0 => \genblk8[5].left_edge_updated[5]_i_2_n_0\,
      I1 => p_154_out,
      I2 => \genblk8[5].right_edge_found_pb[5]_i_3_n_0\,
      I3 => \cmp_err_pb_4to1.(null)[0].compare_err_pb[0]_i_3_n_0\,
      I4 => left_edge_updated(5),
      O => \genblk8[5].left_edge_updated[5]_i_1_n_0\
    );
\genblk8[5].left_edge_updated[5]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000000100"
    )
        port map (
      I0 => match_flag_pb(43),
      I1 => match_flag_pb(42),
      I2 => match_flag_pb(40),
      I3 => match_flag_pb(47),
      I4 => \genblk7[5].compare_err_pb_latch_r_reg_n_0_[5]\,
      I5 => \genblk8[5].right_edge_found_pb[5]_i_4_n_0\,
      O => \genblk8[5].left_edge_updated[5]_i_2_n_0\
    );
\genblk8[5].left_edge_updated_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => '1',
      D => \genblk8[5].left_edge_updated[5]_i_1_n_0\,
      Q => left_edge_updated(5),
      R => \bit_cnt[7]_i_1_n_0\
    );
\genblk8[5].match_flag_pb_reg[40]\: unisim.vcomponents.FDSE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => p_154_out,
      D => \genblk7[5].compare_err_pb_latch_r_reg_n_0_[5]\,
      Q => match_flag_pb(40),
      S => \genblk8[0].match_flag_pb[7]_i_1_n_0\
    );
\genblk8[5].match_flag_pb_reg[41]\: unisim.vcomponents.FDSE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => p_154_out,
      D => match_flag_pb(40),
      Q => match_flag_pb(41),
      S => \genblk8[0].match_flag_pb[7]_i_1_n_0\
    );
\genblk8[5].match_flag_pb_reg[42]\: unisim.vcomponents.FDSE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => p_154_out,
      D => match_flag_pb(41),
      Q => match_flag_pb(42),
      S => \genblk8[0].match_flag_pb[7]_i_1_n_0\
    );
\genblk8[5].match_flag_pb_reg[43]\: unisim.vcomponents.FDSE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => p_154_out,
      D => match_flag_pb(42),
      Q => match_flag_pb(43),
      S => \genblk8[0].match_flag_pb[7]_i_1_n_0\
    );
\genblk8[5].match_flag_pb_reg[44]\: unisim.vcomponents.FDSE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => p_154_out,
      D => match_flag_pb(43),
      Q => match_flag_pb(44),
      S => \genblk8[0].match_flag_pb[7]_i_1_n_0\
    );
\genblk8[5].match_flag_pb_reg[45]\: unisim.vcomponents.FDSE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => p_154_out,
      D => match_flag_pb(44),
      Q => match_flag_pb(45),
      S => \genblk8[0].match_flag_pb[7]_i_1_n_0\
    );
\genblk8[5].match_flag_pb_reg[46]\: unisim.vcomponents.FDSE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => p_154_out,
      D => match_flag_pb(45),
      Q => match_flag_pb(46),
      S => \genblk8[0].match_flag_pb[7]_i_1_n_0\
    );
\genblk8[5].match_flag_pb_reg[47]\: unisim.vcomponents.FDSE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => p_154_out,
      D => match_flag_pb(46),
      Q => match_flag_pb(47),
      S => \genblk8[0].match_flag_pb[7]_i_1_n_0\
    );
\genblk8[5].right_edge_found_pb[5]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"1F001F00AAAABFAA"
    )
        port map (
      I0 => \genblk8[5].right_edge_found_pb_reg_n_0_[5]\,
      I1 => prbs_dqs_tap_limit_r_i_2_n_0,
      I2 => \genblk8[5].right_edge_found_pb[5]_i_2_n_0\,
      I3 => p_154_out,
      I4 => \genblk8[5].right_edge_found_pb[5]_i_3_n_0\,
      I5 => \genblk8[0].right_edge_found_pb[0]_i_4_n_0\,
      O => \genblk8[5].right_edge_found_pb[5]_i_1_n_0\
    );
\genblk8[5].right_edge_found_pb[5]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFEFFFF"
    )
        port map (
      I0 => \genblk8[5].right_edge_found_pb[5]_i_4_n_0\,
      I1 => match_flag_pb(43),
      I2 => match_flag_pb(42),
      I3 => match_flag_pb(40),
      I4 => \genblk7[5].compare_err_pb_latch_r_reg_n_0_[5]\,
      I5 => match_flag_pb(47),
      O => \genblk8[5].right_edge_found_pb[5]_i_2_n_0\
    );
\genblk8[5].right_edge_found_pb[5]_i_3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0002"
    )
        port map (
      I0 => \genblk8[5].right_edge_found_pb[5]_i_5_n_0\,
      I1 => \genblk7[5].compare_err_pb_latch_r_reg_n_0_[5]\,
      I2 => match_flag_pb(40),
      I3 => match_flag_pb(41),
      O => \genblk8[5].right_edge_found_pb[5]_i_3_n_0\
    );
\genblk8[5].right_edge_found_pb[5]_i_4\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFFE"
    )
        port map (
      I0 => match_flag_pb(46),
      I1 => match_flag_pb(44),
      I2 => match_flag_pb(41),
      I3 => match_flag_pb(45),
      O => \genblk8[5].right_edge_found_pb[5]_i_4_n_0\
    );
\genblk8[5].right_edge_found_pb[5]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000100000000"
    )
        port map (
      I0 => match_flag_pb(42),
      I1 => match_flag_pb(43),
      I2 => match_flag_pb(44),
      I3 => match_flag_pb(45),
      I4 => match_flag_pb(46),
      I5 => match_flag_pb(47),
      O => \genblk8[5].right_edge_found_pb[5]_i_5_n_0\
    );
\genblk8[5].right_edge_found_pb_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => '1',
      D => \genblk8[5].right_edge_found_pb[5]_i_1_n_0\,
      Q => \genblk8[5].right_edge_found_pb_reg_n_0_[5]\,
      R => \bit_cnt[7]_i_1_n_0\
    );
\genblk8[6].left_edge_updated[6]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88BF8880"
    )
        port map (
      I0 => \genblk8[6].left_edge_updated[6]_i_2_n_0\,
      I1 => p_154_out,
      I2 => \genblk8[6].right_edge_found_pb[6]_i_3_n_0\,
      I3 => \cmp_err_pb_4to1.(null)[0].compare_err_pb[0]_i_3_n_0\,
      I4 => left_edge_updated(6),
      O => \genblk8[6].left_edge_updated[6]_i_1_n_0\
    );
\genblk8[6].left_edge_updated[6]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000000100"
    )
        port map (
      I0 => match_flag_pb(51),
      I1 => match_flag_pb(50),
      I2 => match_flag_pb(48),
      I3 => match_flag_pb(55),
      I4 => \genblk7[6].compare_err_pb_latch_r_reg_n_0_[6]\,
      I5 => \genblk8[6].right_edge_found_pb[6]_i_4_n_0\,
      O => \genblk8[6].left_edge_updated[6]_i_2_n_0\
    );
\genblk8[6].left_edge_updated_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => '1',
      D => \genblk8[6].left_edge_updated[6]_i_1_n_0\,
      Q => left_edge_updated(6),
      R => \bit_cnt[7]_i_1_n_0\
    );
\genblk8[6].match_flag_pb_reg[48]\: unisim.vcomponents.FDSE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => p_154_out,
      D => \genblk7[6].compare_err_pb_latch_r_reg_n_0_[6]\,
      Q => match_flag_pb(48),
      S => \genblk8[0].match_flag_pb[7]_i_1_n_0\
    );
\genblk8[6].match_flag_pb_reg[49]\: unisim.vcomponents.FDSE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => p_154_out,
      D => match_flag_pb(48),
      Q => match_flag_pb(49),
      S => \genblk8[0].match_flag_pb[7]_i_1_n_0\
    );
\genblk8[6].match_flag_pb_reg[50]\: unisim.vcomponents.FDSE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => p_154_out,
      D => match_flag_pb(49),
      Q => match_flag_pb(50),
      S => \genblk8[0].match_flag_pb[7]_i_1_n_0\
    );
\genblk8[6].match_flag_pb_reg[51]\: unisim.vcomponents.FDSE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => p_154_out,
      D => match_flag_pb(50),
      Q => match_flag_pb(51),
      S => \genblk8[0].match_flag_pb[7]_i_1_n_0\
    );
\genblk8[6].match_flag_pb_reg[52]\: unisim.vcomponents.FDSE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => p_154_out,
      D => match_flag_pb(51),
      Q => match_flag_pb(52),
      S => \genblk8[0].match_flag_pb[7]_i_1_n_0\
    );
\genblk8[6].match_flag_pb_reg[53]\: unisim.vcomponents.FDSE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => p_154_out,
      D => match_flag_pb(52),
      Q => match_flag_pb(53),
      S => \genblk8[0].match_flag_pb[7]_i_1_n_0\
    );
\genblk8[6].match_flag_pb_reg[54]\: unisim.vcomponents.FDSE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => p_154_out,
      D => match_flag_pb(53),
      Q => match_flag_pb(54),
      S => \genblk8[0].match_flag_pb[7]_i_1_n_0\
    );
\genblk8[6].match_flag_pb_reg[55]\: unisim.vcomponents.FDSE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => p_154_out,
      D => match_flag_pb(54),
      Q => match_flag_pb(55),
      S => \genblk8[0].match_flag_pb[7]_i_1_n_0\
    );
\genblk8[6].right_edge_found_pb[6]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"1F001F00AAAABFAA"
    )
        port map (
      I0 => \genblk8[6].right_edge_found_pb_reg_n_0_[6]\,
      I1 => prbs_dqs_tap_limit_r_i_2_n_0,
      I2 => \genblk8[6].right_edge_found_pb[6]_i_2_n_0\,
      I3 => p_154_out,
      I4 => \genblk8[6].right_edge_found_pb[6]_i_3_n_0\,
      I5 => \genblk8[0].right_edge_found_pb[0]_i_4_n_0\,
      O => \genblk8[6].right_edge_found_pb[6]_i_1_n_0\
    );
\genblk8[6].right_edge_found_pb[6]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFEFFFF"
    )
        port map (
      I0 => \genblk8[6].right_edge_found_pb[6]_i_4_n_0\,
      I1 => match_flag_pb(51),
      I2 => match_flag_pb(50),
      I3 => match_flag_pb(48),
      I4 => \genblk7[6].compare_err_pb_latch_r_reg_n_0_[6]\,
      I5 => match_flag_pb(55),
      O => \genblk8[6].right_edge_found_pb[6]_i_2_n_0\
    );
\genblk8[6].right_edge_found_pb[6]_i_3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0002"
    )
        port map (
      I0 => \genblk8[6].right_edge_found_pb[6]_i_5_n_0\,
      I1 => \genblk7[6].compare_err_pb_latch_r_reg_n_0_[6]\,
      I2 => match_flag_pb(48),
      I3 => match_flag_pb(49),
      O => \genblk8[6].right_edge_found_pb[6]_i_3_n_0\
    );
\genblk8[6].right_edge_found_pb[6]_i_4\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFFE"
    )
        port map (
      I0 => match_flag_pb(54),
      I1 => match_flag_pb(52),
      I2 => match_flag_pb(49),
      I3 => match_flag_pb(53),
      O => \genblk8[6].right_edge_found_pb[6]_i_4_n_0\
    );
\genblk8[6].right_edge_found_pb[6]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000100000000"
    )
        port map (
      I0 => match_flag_pb(50),
      I1 => match_flag_pb(51),
      I2 => match_flag_pb(52),
      I3 => match_flag_pb(53),
      I4 => match_flag_pb(54),
      I5 => match_flag_pb(55),
      O => \genblk8[6].right_edge_found_pb[6]_i_5_n_0\
    );
\genblk8[6].right_edge_found_pb_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => '1',
      D => \genblk8[6].right_edge_found_pb[6]_i_1_n_0\,
      Q => \genblk8[6].right_edge_found_pb_reg_n_0_[6]\,
      R => \bit_cnt[7]_i_1_n_0\
    );
\genblk8[7].left_edge_updated[7]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8F88"
    )
        port map (
      I0 => p_154_out,
      I1 => \genblk8[7].right_edge_found_pb[7]_i_3_n_0\,
      I2 => \cmp_err_pb_4to1.(null)[0].compare_err_pb[0]_i_3_n_0\,
      I3 => left_edge_updated(7),
      O => \genblk8[7].left_edge_updated[7]_i_1_n_0\
    );
\genblk8[7].left_edge_updated_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => '1',
      D => \genblk8[7].left_edge_updated[7]_i_1_n_0\,
      Q => left_edge_updated(7),
      R => \bit_cnt[7]_i_1_n_0\
    );
\genblk8[7].match_flag_pb_reg[56]\: unisim.vcomponents.FDSE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => p_154_out,
      D => \genblk7[7].compare_err_pb_latch_r_reg_n_0_[7]\,
      Q => match_flag_pb(56),
      S => \genblk8[0].match_flag_pb[7]_i_1_n_0\
    );
\genblk8[7].match_flag_pb_reg[57]\: unisim.vcomponents.FDSE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => p_154_out,
      D => match_flag_pb(56),
      Q => match_flag_pb(57),
      S => \genblk8[0].match_flag_pb[7]_i_1_n_0\
    );
\genblk8[7].match_flag_pb_reg[58]\: unisim.vcomponents.FDSE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => p_154_out,
      D => match_flag_pb(57),
      Q => match_flag_pb(58),
      S => \genblk8[0].match_flag_pb[7]_i_1_n_0\
    );
\genblk8[7].match_flag_pb_reg[59]\: unisim.vcomponents.FDSE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => p_154_out,
      D => match_flag_pb(58),
      Q => match_flag_pb(59),
      S => \genblk8[0].match_flag_pb[7]_i_1_n_0\
    );
\genblk8[7].match_flag_pb_reg[60]\: unisim.vcomponents.FDSE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => p_154_out,
      D => match_flag_pb(59),
      Q => match_flag_pb(60),
      S => \genblk8[0].match_flag_pb[7]_i_1_n_0\
    );
\genblk8[7].match_flag_pb_reg[61]\: unisim.vcomponents.FDSE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => p_154_out,
      D => match_flag_pb(60),
      Q => match_flag_pb(61),
      S => \genblk8[0].match_flag_pb[7]_i_1_n_0\
    );
\genblk8[7].match_flag_pb_reg[62]\: unisim.vcomponents.FDSE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => p_154_out,
      D => match_flag_pb(61),
      Q => match_flag_pb(62),
      S => \genblk8[0].match_flag_pb[7]_i_1_n_0\
    );
\genblk8[7].match_flag_pb_reg[63]\: unisim.vcomponents.FDSE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => p_154_out,
      D => match_flag_pb(62),
      Q => match_flag_pb(63),
      S => \genblk8[0].match_flag_pb[7]_i_1_n_0\
    );
\genblk8[7].right_edge_found_pb[7]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"CD00CD00AAAAEFAA"
    )
        port map (
      I0 => \genblk8[7].right_edge_found_pb_reg_n_0_[7]\,
      I1 => \genblk8[7].right_edge_found_pb[7]_i_2_n_0\,
      I2 => prbs_dqs_tap_limit_r_i_2_n_0,
      I3 => p_154_out,
      I4 => \genblk8[7].right_edge_found_pb[7]_i_3_n_0\,
      I5 => \genblk8[0].right_edge_found_pb[0]_i_4_n_0\,
      O => \genblk8[7].right_edge_found_pb[7]_i_1_n_0\
    );
\genblk8[7].right_edge_found_pb[7]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000000100"
    )
        port map (
      I0 => match_flag_pb(59),
      I1 => match_flag_pb(58),
      I2 => match_flag_pb(56),
      I3 => \genblk7[7].compare_err_pb_latch_r_reg_n_0_[7]\,
      I4 => match_flag_pb(63),
      I5 => \genblk8[7].right_edge_found_pb[7]_i_4_n_0\,
      O => \genblk8[7].right_edge_found_pb[7]_i_2_n_0\
    );
\genblk8[7].right_edge_found_pb[7]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000000100"
    )
        port map (
      I0 => match_flag_pb(59),
      I1 => match_flag_pb(58),
      I2 => match_flag_pb(56),
      I3 => match_flag_pb(63),
      I4 => \genblk7[7].compare_err_pb_latch_r_reg_n_0_[7]\,
      I5 => \genblk8[7].right_edge_found_pb[7]_i_4_n_0\,
      O => \genblk8[7].right_edge_found_pb[7]_i_3_n_0\
    );
\genblk8[7].right_edge_found_pb[7]_i_4\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFFE"
    )
        port map (
      I0 => match_flag_pb(62),
      I1 => match_flag_pb(60),
      I2 => match_flag_pb(57),
      I3 => match_flag_pb(61),
      O => \genblk8[7].right_edge_found_pb[7]_i_4_n_0\
    );
\genblk8[7].right_edge_found_pb_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => '1',
      D => \genblk8[7].right_edge_found_pb[7]_i_1_n_0\,
      Q => \genblk8[7].right_edge_found_pb_reg_n_0_[7]\,
      R => \bit_cnt[7]_i_1_n_0\
    );
\init_state_r[1]_i_33\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AAAAAA8A"
    )
        port map (
      I0 => \init_state_r[0]_i_27\,
      I1 => \^prbs_last_byte_done\,
      I2 => rdlvl_last_byte_done,
      I3 => \^prbs_rdlvl_done_reg_0\,
      I4 => \init_state_r[0]_i_27_0\,
      O => dqs_found_done_r_reg
    );
\init_state_r[2]_i_37\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"80B0"
    )
        port map (
      I0 => \^prbs_rdlvl_done_reg_0\,
      I1 => \gen_byte_sel_div2.byte_sel_cnt_reg[0]\,
      I2 => \init_state_r[0]_i_27\,
      I3 => \gen_byte_sel_div2.byte_sel_cnt_reg[0]_0\,
      O => prbs_rdlvl_done_reg_1
    );
\largest_left_edge[0]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => prbs_state_r(2),
      I1 => \prbs_dqs_tap_cnt_r_reg_n_0_[0]\,
      O => \largest_left_edge[0]_i_1_n_0\
    );
\largest_left_edge[1]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"60"
    )
        port map (
      I0 => \prbs_dqs_tap_cnt_r_reg_n_0_[1]\,
      I1 => \prbs_dqs_tap_cnt_r_reg_n_0_[0]\,
      I2 => prbs_state_r(2),
      O => \largest_left_edge[1]_i_1_n_0\
    );
\largest_left_edge[2]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6A00"
    )
        port map (
      I0 => \prbs_dqs_tap_cnt_r_reg_n_0_[2]\,
      I1 => \prbs_dqs_tap_cnt_r_reg_n_0_[0]\,
      I2 => \prbs_dqs_tap_cnt_r_reg_n_0_[1]\,
      I3 => prbs_state_r(2),
      O => \largest_left_edge[2]_i_1_n_0\
    );
\largest_left_edge[3]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"82222222"
    )
        port map (
      I0 => prbs_state_r(2),
      I1 => \prbs_dqs_tap_cnt_r_reg_n_0_[3]\,
      I2 => \prbs_dqs_tap_cnt_r_reg_n_0_[1]\,
      I3 => \prbs_dqs_tap_cnt_r_reg_n_0_[0]\,
      I4 => \prbs_dqs_tap_cnt_r_reg_n_0_[2]\,
      O => \largest_left_edge[3]_i_1_n_0\
    );
\largest_left_edge[4]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FF800000007F0000"
    )
        port map (
      I0 => \prbs_dqs_tap_cnt_r_reg_n_0_[2]\,
      I1 => \prbs_dqs_tap_cnt_r_reg_n_0_[0]\,
      I2 => \prbs_dqs_tap_cnt_r_reg_n_0_[1]\,
      I3 => \prbs_dqs_tap_cnt_r_reg_n_0_[3]\,
      I4 => prbs_state_r(2),
      I5 => \prbs_dqs_tap_cnt_r_reg_n_0_[4]\,
      O => \largest_left_edge[4]_i_1_n_0\
    );
\largest_left_edge[5]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0080001000000010"
    )
        port map (
      I0 => prbs_state_r(0),
      I1 => prbs_state_r(1),
      I2 => prbs_state_r(3),
      I3 => prbs_state_r(4),
      I4 => prbs_state_r(2),
      I5 => \largest_left_edge[5]_i_3_n_0\,
      O => \largest_left_edge[5]_i_1_n_0\
    );
\largest_left_edge[5]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"D020"
    )
        port map (
      I0 => \largest_left_edge[5]_i_4_n_0\,
      I1 => \prbs_dqs_tap_cnt_r_reg_n_0_[4]\,
      I2 => prbs_state_r(2),
      I3 => \prbs_dqs_tap_cnt_r_reg_n_0_[5]\,
      O => \largest_left_edge[5]_i_2_n_0\
    );
\largest_left_edge[5]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"5555555555555551"
    )
        port map (
      I0 => no_err_win_detected_latch_reg_n_0,
      I1 => \largest_left_edge[5]_i_5_n_0\,
      I2 => left_edge_updated(7),
      I3 => left_edge_updated(6),
      I4 => left_edge_updated(5),
      I5 => left_edge_updated(4),
      O => \largest_left_edge[5]_i_3_n_0\
    );
\largest_left_edge[5]_i_4\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"007F"
    )
        port map (
      I0 => \prbs_dqs_tap_cnt_r_reg_n_0_[2]\,
      I1 => \prbs_dqs_tap_cnt_r_reg_n_0_[0]\,
      I2 => \prbs_dqs_tap_cnt_r_reg_n_0_[1]\,
      I3 => \prbs_dqs_tap_cnt_r_reg_n_0_[3]\,
      O => \largest_left_edge[5]_i_4_n_0\
    );
\largest_left_edge[5]_i_5\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0001"
    )
        port map (
      I0 => left_edge_updated(1),
      I1 => left_edge_updated(0),
      I2 => left_edge_updated(3),
      I3 => left_edge_updated(2),
      O => \largest_left_edge[5]_i_5_n_0\
    );
\largest_left_edge_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => \largest_left_edge[5]_i_1_n_0\,
      D => \largest_left_edge[0]_i_1_n_0\,
      Q => \largest_left_edge_reg_n_0_[0]\,
      R => \samples_cnt_r_reg[0]_0\
    );
\largest_left_edge_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => \largest_left_edge[5]_i_1_n_0\,
      D => \largest_left_edge[1]_i_1_n_0\,
      Q => \largest_left_edge_reg_n_0_[1]\,
      R => \samples_cnt_r_reg[0]_0\
    );
\largest_left_edge_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => \largest_left_edge[5]_i_1_n_0\,
      D => \largest_left_edge[2]_i_1_n_0\,
      Q => \largest_left_edge_reg_n_0_[2]\,
      R => \samples_cnt_r_reg[0]_0\
    );
\largest_left_edge_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => \largest_left_edge[5]_i_1_n_0\,
      D => \largest_left_edge[3]_i_1_n_0\,
      Q => \largest_left_edge_reg_n_0_[3]\,
      R => \samples_cnt_r_reg[0]_0\
    );
\largest_left_edge_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => \largest_left_edge[5]_i_1_n_0\,
      D => \largest_left_edge[4]_i_1_n_0\,
      Q => \largest_left_edge_reg_n_0_[4]\,
      R => \samples_cnt_r_reg[0]_0\
    );
\largest_left_edge_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => \largest_left_edge[5]_i_1_n_0\,
      D => \largest_left_edge[5]_i_2_n_0\,
      Q => \largest_left_edge_reg_n_0_[5]\,
      R => \samples_cnt_r_reg[0]_0\
    );
\match_flag_and[0]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFF3BBBB"
    )
        port map (
      I0 => compare_err_pb_and_reg_n_0,
      I1 => prbs_state_r(4),
      I2 => num_samples_done_ind_reg_n_0,
      I3 => \^num_samples_done_r\,
      I4 => prbs_state_r(1),
      O => \match_flag_and[0]_i_1_n_0\
    );
\match_flag_and[1]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFF3BBBB"
    )
        port map (
      I0 => \match_flag_and_reg_n_0_[0]\,
      I1 => prbs_state_r(4),
      I2 => num_samples_done_ind_reg_n_0,
      I3 => \^num_samples_done_r\,
      I4 => prbs_state_r(1),
      O => \match_flag_and[1]_i_1_n_0\
    );
\match_flag_and[2]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFF3BBBB"
    )
        port map (
      I0 => \match_flag_and_reg_n_0_[1]\,
      I1 => prbs_state_r(4),
      I2 => num_samples_done_ind_reg_n_0,
      I3 => \^num_samples_done_r\,
      I4 => prbs_state_r(1),
      O => \match_flag_and[2]_i_1_n_0\
    );
\match_flag_and[3]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFF3BBBB"
    )
        port map (
      I0 => \match_flag_and_reg_n_0_[2]\,
      I1 => prbs_state_r(4),
      I2 => num_samples_done_ind_reg_n_0,
      I3 => \^num_samples_done_r\,
      I4 => prbs_state_r(1),
      O => \match_flag_and[3]_i_1_n_0\
    );
\match_flag_and[4]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFF3BBBB"
    )
        port map (
      I0 => \match_flag_and_reg_n_0_[3]\,
      I1 => prbs_state_r(4),
      I2 => num_samples_done_ind_reg_n_0,
      I3 => \^num_samples_done_r\,
      I4 => prbs_state_r(1),
      O => \match_flag_and[4]_i_1_n_0\
    );
\match_flag_and[5]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFF3BBBB"
    )
        port map (
      I0 => \match_flag_and_reg_n_0_[4]\,
      I1 => prbs_state_r(4),
      I2 => num_samples_done_ind_reg_n_0,
      I3 => \^num_samples_done_r\,
      I4 => prbs_state_r(1),
      O => \match_flag_and[5]_i_1_n_0\
    );
\match_flag_and[6]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFF3BBBB"
    )
        port map (
      I0 => \match_flag_and_reg_n_0_[5]\,
      I1 => prbs_state_r(4),
      I2 => num_samples_done_ind_reg_n_0,
      I3 => \^num_samples_done_r\,
      I4 => prbs_state_r(1),
      O => \match_flag_and[6]_i_1_n_0\
    );
\match_flag_and[7]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"020C020C02040004"
    )
        port map (
      I0 => prbs_state_r(4),
      I1 => prbs_state_r(0),
      I2 => \prbs_state_r[4]_i_5_n_0\,
      I3 => prbs_state_r(1),
      I4 => num_samples_done_ind_reg_n_0,
      I5 => \^num_samples_done_r\,
      O => match_flag_and
    );
\match_flag_and[7]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFF3BBBB"
    )
        port map (
      I0 => \match_flag_and_reg_n_0_[6]\,
      I1 => prbs_state_r(4),
      I2 => num_samples_done_ind_reg_n_0,
      I3 => \^num_samples_done_r\,
      I4 => prbs_state_r(1),
      O => \match_flag_and[7]_i_2_n_0\
    );
\match_flag_and_reg[0]\: unisim.vcomponents.FDSE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => match_flag_and,
      D => \match_flag_and[0]_i_1_n_0\,
      Q => \match_flag_and_reg_n_0_[0]\,
      S => \match_flag_and_reg[7]_0\
    );
\match_flag_and_reg[1]\: unisim.vcomponents.FDSE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => match_flag_and,
      D => \match_flag_and[1]_i_1_n_0\,
      Q => \match_flag_and_reg_n_0_[1]\,
      S => \match_flag_and_reg[7]_0\
    );
\match_flag_and_reg[2]\: unisim.vcomponents.FDSE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => match_flag_and,
      D => \match_flag_and[2]_i_1_n_0\,
      Q => \match_flag_and_reg_n_0_[2]\,
      S => \match_flag_and_reg[7]_0\
    );
\match_flag_and_reg[3]\: unisim.vcomponents.FDSE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => match_flag_and,
      D => \match_flag_and[3]_i_1_n_0\,
      Q => \match_flag_and_reg_n_0_[3]\,
      S => \match_flag_and_reg[7]_0\
    );
\match_flag_and_reg[4]\: unisim.vcomponents.FDSE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => match_flag_and,
      D => \match_flag_and[4]_i_1_n_0\,
      Q => \match_flag_and_reg_n_0_[4]\,
      S => \match_flag_and_reg[7]_0\
    );
\match_flag_and_reg[5]\: unisim.vcomponents.FDSE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => match_flag_and,
      D => \match_flag_and[5]_i_1_n_0\,
      Q => \match_flag_and_reg_n_0_[5]\,
      S => \match_flag_and_reg[7]_0\
    );
\match_flag_and_reg[6]\: unisim.vcomponents.FDSE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => match_flag_and,
      D => \match_flag_and[6]_i_1_n_0\,
      Q => \match_flag_and_reg_n_0_[6]\,
      S => \match_flag_and_reg[7]_0\
    );
\match_flag_and_reg[7]\: unisim.vcomponents.FDSE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => match_flag_and,
      D => \match_flag_and[7]_i_2_n_0\,
      Q => \match_flag_and_reg_n_0_[7]\,
      S => \match_flag_and_reg[7]_0\
    );
\match_flag_or[0]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFF3BBBB"
    )
        port map (
      I0 => sel0(0),
      I1 => prbs_state_r(4),
      I2 => num_samples_done_ind_reg_n_0,
      I3 => \^num_samples_done_r\,
      I4 => prbs_state_r(1),
      O => \match_flag_or[0]_i_1_n_0\
    );
\match_flag_or[1]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFF3BBBB"
    )
        port map (
      I0 => sel0(1),
      I1 => prbs_state_r(4),
      I2 => num_samples_done_ind_reg_n_0,
      I3 => \^num_samples_done_r\,
      I4 => prbs_state_r(1),
      O => \match_flag_or[1]_i_1_n_0\
    );
\match_flag_or[2]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFF3BBBB"
    )
        port map (
      I0 => sel0(2),
      I1 => prbs_state_r(4),
      I2 => num_samples_done_ind_reg_n_0,
      I3 => \^num_samples_done_r\,
      I4 => prbs_state_r(1),
      O => \match_flag_or[2]_i_1_n_0\
    );
\match_flag_or[3]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFF3BBBB"
    )
        port map (
      I0 => sel0(3),
      I1 => prbs_state_r(4),
      I2 => num_samples_done_ind_reg_n_0,
      I3 => \^num_samples_done_r\,
      I4 => prbs_state_r(1),
      O => \match_flag_or[3]_i_1_n_0\
    );
\match_flag_or[4]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFF3BBBB"
    )
        port map (
      I0 => sel0(4),
      I1 => prbs_state_r(4),
      I2 => num_samples_done_ind_reg_n_0,
      I3 => \^num_samples_done_r\,
      I4 => prbs_state_r(1),
      O => \match_flag_or[4]_i_1_n_0\
    );
\match_flag_or[5]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFF3BBBB"
    )
        port map (
      I0 => sel0(5),
      I1 => prbs_state_r(4),
      I2 => num_samples_done_ind_reg_n_0,
      I3 => \^num_samples_done_r\,
      I4 => prbs_state_r(1),
      O => \match_flag_or[5]_i_1_n_0\
    );
\match_flag_or[6]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFF3BBBB"
    )
        port map (
      I0 => sel0(6),
      I1 => prbs_state_r(4),
      I2 => num_samples_done_ind_reg_n_0,
      I3 => \^num_samples_done_r\,
      I4 => prbs_state_r(1),
      O => \match_flag_or[6]_i_1_n_0\
    );
\match_flag_or_reg[0]\: unisim.vcomponents.FDSE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => match_flag_and,
      D => \match_flag_or[0]_i_1_n_0\,
      Q => sel0(1),
      S => \prbs_dec_tap_cnt_reg[0]_0\(0)
    );
\match_flag_or_reg[1]\: unisim.vcomponents.FDSE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => match_flag_and,
      D => \match_flag_or[1]_i_1_n_0\,
      Q => sel0(2),
      S => \prbs_dec_tap_cnt_reg[0]_0\(0)
    );
\match_flag_or_reg[2]\: unisim.vcomponents.FDSE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => match_flag_and,
      D => \match_flag_or[2]_i_1_n_0\,
      Q => sel0(3),
      S => \prbs_dec_tap_cnt_reg[0]_0\(0)
    );
\match_flag_or_reg[3]\: unisim.vcomponents.FDSE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => match_flag_and,
      D => \match_flag_or[3]_i_1_n_0\,
      Q => sel0(4),
      S => \prbs_dec_tap_cnt_reg[0]_0\(0)
    );
\match_flag_or_reg[4]\: unisim.vcomponents.FDSE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => match_flag_and,
      D => \match_flag_or[4]_i_1_n_0\,
      Q => sel0(5),
      S => \prbs_dec_tap_cnt_reg[0]_0\(0)
    );
\match_flag_or_reg[5]\: unisim.vcomponents.FDSE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => match_flag_and,
      D => \match_flag_or[5]_i_1_n_0\,
      Q => sel0(6),
      S => \prbs_dec_tap_cnt_reg[0]_0\(0)
    );
\match_flag_or_reg[6]\: unisim.vcomponents.FDSE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => match_flag_and,
      D => \match_flag_or[6]_i_1_n_0\,
      Q => sel0(7),
      S => \prbs_dec_tap_cnt_reg[0]_0\(0)
    );
mux_rd_valid_r_reg: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => '1',
      D => mux_rd_valid_r0,
      Q => mux_rd_valid_r,
      R => '0'
    );
new_cnt_dqs_r_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AA0CFFFFAA0C0000"
    )
        port map (
      I0 => prech_done,
      I1 => new_cnt_dqs_r_reg_1,
      I2 => prbs_state_r(0),
      I3 => prbs_state_r(3),
      I4 => new_cnt_dqs_r_i_3_n_0,
      I5 => \^new_cnt_dqs_r_reg_0\,
      O => new_cnt_dqs_r_i_1_n_0
    );
new_cnt_dqs_r_i_3: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAAAFAEAAAEA"
    )
        port map (
      I0 => \prbs_dqs_cnt_r[3]_i_1_n_0\,
      I1 => new_cnt_dqs_r_reg_1,
      I2 => new_cnt_dqs_r_i_4_n_0,
      I3 => prbs_state_r(0),
      I4 => cnt_wait_state,
      I5 => prbs_state_r(3),
      O => new_cnt_dqs_r_i_3_n_0
    );
new_cnt_dqs_r_i_4: unisim.vcomponents.LUT3
    generic map(
      INIT => X"01"
    )
        port map (
      I0 => prbs_state_r(2),
      I1 => prbs_state_r(1),
      I2 => prbs_state_r(4),
      O => new_cnt_dqs_r_i_4_n_0
    );
new_cnt_dqs_r_reg: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => '1',
      D => new_cnt_dqs_r_i_1_n_0,
      Q => \^new_cnt_dqs_r_reg_0\,
      R => \prbs_dec_tap_cnt_reg[0]_0\(0)
    );
no_err_win_detected_i_1: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000002"
    )
        port map (
      I0 => no_err_win_detected_i_2_n_0,
      I1 => sel0(2),
      I2 => sel0(3),
      I3 => sel0(0),
      I4 => sel0(1),
      O => no_err_win_detected_i_1_n_0
    );
no_err_win_detected_i_2: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000100000000"
    )
        port map (
      I0 => sel0(4),
      I1 => sel0(5),
      I2 => sel0(6),
      I3 => sel0(7),
      I4 => prbs_state_r(1),
      I5 => prbs_state_r(4),
      O => no_err_win_detected_i_2_n_0
    );
no_err_win_detected_latch_i_1: unisim.vcomponents.LUT5
    generic map(
      INIT => X"888F8880"
    )
        port map (
      I0 => no_err_win_detected_reg_n_0,
      I1 => prbs_state_r(3),
      I2 => no_err_win_detected_latch_i_2_n_0,
      I3 => no_err_win_detected_latch_i_3_n_0,
      I4 => no_err_win_detected_latch_reg_n_0,
      O => no_err_win_detected_latch_i_1_n_0
    );
no_err_win_detected_latch_i_2: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000800200000000"
    )
        port map (
      I0 => no_err_win_detected_reg_n_0,
      I1 => prbs_state_r(3),
      I2 => prbs_state_r(1),
      I3 => prbs_state_r(2),
      I4 => prbs_state_r(4),
      I5 => prbs_state_r(0),
      O => no_err_win_detected_latch_i_2_n_0
    );
no_err_win_detected_latch_i_3: unisim.vcomponents.LUT6
    generic map(
      INIT => X"000000E0000F0000"
    )
        port map (
      I0 => \^num_samples_done_r\,
      I1 => num_samples_done_ind_reg_n_0,
      I2 => prbs_state_r(1),
      I3 => \prbs_state_r[4]_i_5_n_0\,
      I4 => prbs_state_r(0),
      I5 => prbs_state_r(4),
      O => no_err_win_detected_latch_i_3_n_0
    );
no_err_win_detected_latch_reg: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => '1',
      D => no_err_win_detected_latch_i_1_n_0,
      Q => no_err_win_detected_latch_reg_n_0,
      R => \prbs_dec_tap_cnt_reg[0]_0\(0)
    );
no_err_win_detected_reg: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => match_flag_and,
      D => no_err_win_detected_i_1_n_0,
      Q => no_err_win_detected_reg_n_0,
      R => no_err_win_detected_reg_0
    );
num_samples_done_ind_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0F0F0F0B2B0F0F0"
    )
        port map (
      I0 => prbs_state_r(0),
      I1 => prbs_state_r(1),
      I2 => num_samples_done_ind_reg_n_0,
      I3 => \^num_samples_done_r\,
      I4 => prbs_state_r(4),
      I5 => \prbs_state_r[4]_i_5_n_0\,
      O => num_samples_done_ind_i_1_n_0
    );
num_samples_done_ind_reg: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => '1',
      D => num_samples_done_ind_i_1_n_0,
      Q => num_samples_done_ind_reg_n_0,
      R => \samples_cnt_r_reg[0]_0\
    );
pi_en_stg2_f_reg: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => '1',
      D => pi_en_stg2_f_timing,
      Q => prbs_pi_stg2_f_en,
      R => '0'
    );
pi_en_stg2_f_timing_reg: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => '1',
      D => prbs_tap_en_r_reg_n_0,
      Q => pi_en_stg2_f_timing,
      R => \match_flag_and_reg[7]_0\
    );
pi_stg2_f_incdec_reg: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => '1',
      D => pi_stg2_f_incdec_timing,
      Q => prbs_pi_stg2_f_incdec,
      R => '0'
    );
\pi_stg2_f_incdec_timing_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \rd_victim_sel_reg[2]_1\,
      I1 => prbs_tap_inc_r,
      I2 => prbs_tap_en_r_reg_n_0,
      O => \pi_stg2_f_incdec_timing_i_1__0_n_0\
    );
pi_stg2_f_incdec_timing_reg: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => '1',
      D => \pi_stg2_f_incdec_timing_i_1__0_n_0\,
      Q => pi_stg2_f_incdec_timing,
      R => '0'
    );
\prbs_1st_edge_taps_r[1]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \prbs_dqs_tap_cnt_r_reg_n_0_[0]\,
      I1 => \prbs_dqs_tap_cnt_r_reg_n_0_[1]\,
      O => \prbs_1st_edge_taps_r[1]_i_1_n_0\
    );
\prbs_1st_edge_taps_r[2]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"78"
    )
        port map (
      I0 => \prbs_dqs_tap_cnt_r_reg_n_0_[1]\,
      I1 => \prbs_dqs_tap_cnt_r_reg_n_0_[0]\,
      I2 => \prbs_dqs_tap_cnt_r_reg_n_0_[2]\,
      O => \prbs_1st_edge_taps_r[2]_i_1_n_0\
    );
\prbs_1st_edge_taps_r[3]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7F80"
    )
        port map (
      I0 => \prbs_dqs_tap_cnt_r_reg_n_0_[2]\,
      I1 => \prbs_dqs_tap_cnt_r_reg_n_0_[0]\,
      I2 => \prbs_dqs_tap_cnt_r_reg_n_0_[1]\,
      I3 => \prbs_dqs_tap_cnt_r_reg_n_0_[3]\,
      O => \prbs_1st_edge_taps_r[3]_i_1_n_0\
    );
\prbs_1st_edge_taps_r[4]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"7FFF8000"
    )
        port map (
      I0 => \prbs_dqs_tap_cnt_r_reg_n_0_[3]\,
      I1 => \prbs_dqs_tap_cnt_r_reg_n_0_[1]\,
      I2 => \prbs_dqs_tap_cnt_r_reg_n_0_[0]\,
      I3 => \prbs_dqs_tap_cnt_r_reg_n_0_[2]\,
      I4 => \prbs_dqs_tap_cnt_r_reg_n_0_[4]\,
      O => \prbs_1st_edge_taps_r[4]_i_1_n_0\
    );
\prbs_1st_edge_taps_r[5]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"4C005D00"
    )
        port map (
      I0 => prbs_found_1st_edge_r_reg_n_0,
      I1 => prbs_state_r(3),
      I2 => prbs_state_r(1),
      I3 => \prbs_2nd_edge_taps_r[5]_i_4_n_0\,
      I4 => compare_err_latch_reg_n_0,
      O => \prbs_1st_edge_taps_r[5]_i_1_n_0\
    );
\prbs_1st_edge_taps_r[5]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"5D00"
    )
        port map (
      I0 => prbs_found_1st_edge_r_reg_n_0,
      I1 => prbs_state_r(3),
      I2 => prbs_state_r(1),
      I3 => \prbs_2nd_edge_taps_r[5]_i_4_n_0\,
      O => \prbs_1st_edge_taps_r[5]_i_2_n_0\
    );
\prbs_1st_edge_taps_r[5]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"7FFFFFFF80000000"
    )
        port map (
      I0 => \prbs_dqs_tap_cnt_r_reg_n_0_[4]\,
      I1 => \prbs_dqs_tap_cnt_r_reg_n_0_[2]\,
      I2 => \prbs_dqs_tap_cnt_r_reg_n_0_[0]\,
      I3 => \prbs_dqs_tap_cnt_r_reg_n_0_[1]\,
      I4 => \prbs_dqs_tap_cnt_r_reg_n_0_[3]\,
      I5 => \prbs_dqs_tap_cnt_r_reg_n_0_[5]\,
      O => \prbs_1st_edge_taps_r[5]_i_3_n_0\
    );
\prbs_1st_edge_taps_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => \prbs_1st_edge_taps_r[5]_i_2_n_0\,
      D => \prbs_2nd_edge_taps_r[0]_i_1_n_0\,
      Q => \prbs_1st_edge_taps_r_reg_n_0_[0]\,
      R => \prbs_1st_edge_taps_r[5]_i_1_n_0\
    );
\prbs_1st_edge_taps_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => \prbs_1st_edge_taps_r[5]_i_2_n_0\,
      D => \prbs_1st_edge_taps_r[1]_i_1_n_0\,
      Q => \prbs_1st_edge_taps_r_reg_n_0_[1]\,
      R => \prbs_1st_edge_taps_r[5]_i_1_n_0\
    );
\prbs_1st_edge_taps_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => \prbs_1st_edge_taps_r[5]_i_2_n_0\,
      D => \prbs_1st_edge_taps_r[2]_i_1_n_0\,
      Q => \prbs_1st_edge_taps_r_reg_n_0_[2]\,
      R => \prbs_1st_edge_taps_r[5]_i_1_n_0\
    );
\prbs_1st_edge_taps_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => \prbs_1st_edge_taps_r[5]_i_2_n_0\,
      D => \prbs_1st_edge_taps_r[3]_i_1_n_0\,
      Q => \prbs_1st_edge_taps_r_reg_n_0_[3]\,
      R => \prbs_1st_edge_taps_r[5]_i_1_n_0\
    );
\prbs_1st_edge_taps_r_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => \prbs_1st_edge_taps_r[5]_i_2_n_0\,
      D => \prbs_1st_edge_taps_r[4]_i_1_n_0\,
      Q => \prbs_1st_edge_taps_r_reg_n_0_[4]\,
      R => \prbs_1st_edge_taps_r[5]_i_1_n_0\
    );
\prbs_1st_edge_taps_r_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => \prbs_1st_edge_taps_r[5]_i_2_n_0\,
      D => \prbs_1st_edge_taps_r[5]_i_3_n_0\,
      Q => \prbs_1st_edge_taps_r_reg_n_0_[5]\,
      R => \prbs_1st_edge_taps_r[5]_i_1_n_0\
    );
\prbs_2nd_edge_taps_r[0]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \prbs_dqs_tap_cnt_r_reg_n_0_[0]\,
      O => \prbs_2nd_edge_taps_r[0]_i_1_n_0\
    );
\prbs_2nd_edge_taps_r[1]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => \prbs_dqs_tap_cnt_r_reg_n_0_[1]\,
      I1 => \prbs_dqs_tap_cnt_r_reg_n_0_[0]\,
      O => \prbs_2nd_edge_taps_r[1]_i_1_n_0\
    );
\prbs_2nd_edge_taps_r[2]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"E1"
    )
        port map (
      I0 => \prbs_dqs_tap_cnt_r_reg_n_0_[0]\,
      I1 => \prbs_dqs_tap_cnt_r_reg_n_0_[1]\,
      I2 => \prbs_dqs_tap_cnt_r_reg_n_0_[2]\,
      O => \prbs_2nd_edge_taps_r[2]_i_1_n_0\
    );
\prbs_2nd_edge_taps_r[3]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FE01"
    )
        port map (
      I0 => \prbs_dqs_tap_cnt_r_reg_n_0_[2]\,
      I1 => \prbs_dqs_tap_cnt_r_reg_n_0_[1]\,
      I2 => \prbs_dqs_tap_cnt_r_reg_n_0_[0]\,
      I3 => \prbs_dqs_tap_cnt_r_reg_n_0_[3]\,
      O => \prbs_2nd_edge_taps_r[3]_i_1_n_0\
    );
\prbs_2nd_edge_taps_r[4]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFE0001"
    )
        port map (
      I0 => \prbs_dqs_tap_cnt_r_reg_n_0_[3]\,
      I1 => \prbs_dqs_tap_cnt_r_reg_n_0_[0]\,
      I2 => \prbs_dqs_tap_cnt_r_reg_n_0_[1]\,
      I3 => \prbs_dqs_tap_cnt_r_reg_n_0_[2]\,
      I4 => \prbs_dqs_tap_cnt_r_reg_n_0_[4]\,
      O => \prbs_2nd_edge_taps_r[4]_i_1_n_0\
    );
\prbs_2nd_edge_taps_r[5]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8C00"
    )
        port map (
      I0 => prbs_found_1st_edge_r_reg_n_0,
      I1 => prbs_state_r(3),
      I2 => prbs_state_r(1),
      I3 => \prbs_2nd_edge_taps_r[5]_i_4_n_0\,
      O => \prbs_2nd_edge_taps_r[5]_i_1_n_0\
    );
\prbs_2nd_edge_taps_r[5]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"AE00"
    )
        port map (
      I0 => prbs_found_1st_edge_r_reg_n_0,
      I1 => prbs_state_r(3),
      I2 => prbs_state_r(1),
      I3 => \prbs_2nd_edge_taps_r[5]_i_4_n_0\,
      O => \prbs_2nd_edge_taps_r[5]_i_2_n_0\
    );
\prbs_2nd_edge_taps_r[5]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFE00000001"
    )
        port map (
      I0 => \prbs_dqs_tap_cnt_r_reg_n_0_[4]\,
      I1 => \prbs_dqs_tap_cnt_r_reg_n_0_[2]\,
      I2 => \prbs_dqs_tap_cnt_r_reg_n_0_[1]\,
      I3 => \prbs_dqs_tap_cnt_r_reg_n_0_[0]\,
      I4 => \prbs_dqs_tap_cnt_r_reg_n_0_[3]\,
      I5 => \prbs_dqs_tap_cnt_r_reg_n_0_[5]\,
      O => \prbs_2nd_edge_taps_r[5]_i_3_n_0\
    );
\prbs_2nd_edge_taps_r[5]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0002FF0000000000"
    )
        port map (
      I0 => \^num_samples_done_r\,
      I1 => prbs_dqs_tap_limit_r,
      I2 => \prbs_inc_tap_cnt[5]_i_4_n_0\,
      I3 => prbs_state_r(3),
      I4 => prbs_state_r(1),
      I5 => \prbs_2nd_edge_taps_r[5]_i_5_n_0\,
      O => \prbs_2nd_edge_taps_r[5]_i_4_n_0\
    );
\prbs_2nd_edge_taps_r[5]_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"01"
    )
        port map (
      I0 => prbs_state_r(2),
      I1 => prbs_state_r(4),
      I2 => prbs_state_r(0),
      O => \prbs_2nd_edge_taps_r[5]_i_5_n_0\
    );
\prbs_2nd_edge_taps_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => \prbs_2nd_edge_taps_r[5]_i_2_n_0\,
      D => \prbs_2nd_edge_taps_r[0]_i_1_n_0\,
      Q => prbs_2nd_edge_taps_r(0),
      R => \prbs_2nd_edge_taps_r[5]_i_1_n_0\
    );
\prbs_2nd_edge_taps_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => \prbs_2nd_edge_taps_r[5]_i_2_n_0\,
      D => \prbs_2nd_edge_taps_r[1]_i_1_n_0\,
      Q => prbs_2nd_edge_taps_r(1),
      R => \prbs_2nd_edge_taps_r[5]_i_1_n_0\
    );
\prbs_2nd_edge_taps_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => \prbs_2nd_edge_taps_r[5]_i_2_n_0\,
      D => \prbs_2nd_edge_taps_r[2]_i_1_n_0\,
      Q => prbs_2nd_edge_taps_r(2),
      R => \prbs_2nd_edge_taps_r[5]_i_1_n_0\
    );
\prbs_2nd_edge_taps_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => \prbs_2nd_edge_taps_r[5]_i_2_n_0\,
      D => \prbs_2nd_edge_taps_r[3]_i_1_n_0\,
      Q => prbs_2nd_edge_taps_r(3),
      R => \prbs_2nd_edge_taps_r[5]_i_1_n_0\
    );
\prbs_2nd_edge_taps_r_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => \prbs_2nd_edge_taps_r[5]_i_2_n_0\,
      D => \prbs_2nd_edge_taps_r[4]_i_1_n_0\,
      Q => prbs_2nd_edge_taps_r(4),
      R => \prbs_2nd_edge_taps_r[5]_i_1_n_0\
    );
\prbs_2nd_edge_taps_r_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => \prbs_2nd_edge_taps_r[5]_i_2_n_0\,
      D => \prbs_2nd_edge_taps_r[5]_i_3_n_0\,
      Q => prbs_2nd_edge_taps_r(5),
      R => \prbs_2nd_edge_taps_r[5]_i_1_n_0\
    );
\prbs_dec_tap_cnt[0]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"8B"
    )
        port map (
      I0 => \prbs_dec_tap_cnt[0]_i_2_n_0\,
      I1 => prbs_state_r(2),
      I2 => prbs_dec_tap_cnt(0),
      O => \prbs_dec_tap_cnt[0]_i_1_n_0\
    );
\prbs_dec_tap_cnt[0]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"72FF7200"
    )
        port map (
      I0 => prbs_found_2nd_edge_r_reg_n_0,
      I1 => prbs_dec_tap_cnt2(1),
      I2 => prbs_dec_tap_cnt10_out(1),
      I3 => prbs_found_1st_edge_r_reg_n_0,
      I4 => \prbs_dqs_tap_cnt_r_reg_n_0_[1]\,
      O => \prbs_dec_tap_cnt[0]_i_2_n_0\
    );
\prbs_dec_tap_cnt[1]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F909"
    )
        port map (
      I0 => prbs_dec_tap_cnt(1),
      I1 => prbs_dec_tap_cnt(0),
      I2 => prbs_state_r(2),
      I3 => \prbs_dec_tap_cnt[1]_i_2_n_0\,
      O => \prbs_dec_tap_cnt[1]_i_1_n_0\
    );
\prbs_dec_tap_cnt[1]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"66FFF0F06600F0F0"
    )
        port map (
      I0 => prbs_dec_tap_cnt2(2),
      I1 => prbs_dec_tap_cnt2(1),
      I2 => \prbs_dqs_tap_cnt_r_reg_n_0_[2]\,
      I3 => prbs_found_2nd_edge_r_reg_n_0,
      I4 => prbs_found_1st_edge_r_reg_n_0,
      I5 => prbs_dec_tap_cnt10_out(2),
      O => \prbs_dec_tap_cnt[1]_i_2_n_0\
    );
\prbs_dec_tap_cnt[2]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFE100E1"
    )
        port map (
      I0 => prbs_dec_tap_cnt(0),
      I1 => prbs_dec_tap_cnt(1),
      I2 => prbs_dec_tap_cnt(2),
      I3 => prbs_state_r(2),
      I4 => \prbs_dec_tap_cnt[2]_i_2_n_0\,
      O => \prbs_dec_tap_cnt[2]_i_1_n_0\
    );
\prbs_dec_tap_cnt[2]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"66FFF0F06600F0F0"
    )
        port map (
      I0 => \prbs_dec_tap_cnt[2]_i_3_n_0\,
      I1 => prbs_dec_tap_cnt2(3),
      I2 => \prbs_dqs_tap_cnt_r_reg_n_0_[3]\,
      I3 => prbs_found_2nd_edge_r_reg_n_0,
      I4 => prbs_found_1st_edge_r_reg_n_0,
      I5 => prbs_dec_tap_cnt10_out(3),
      O => \prbs_dec_tap_cnt[2]_i_2_n_0\
    );
\prbs_dec_tap_cnt[2]_i_3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => prbs_dec_tap_cnt2(1),
      I1 => prbs_dec_tap_cnt2(2),
      O => \prbs_dec_tap_cnt[2]_i_3_n_0\
    );
\prbs_dec_tap_cnt[2]_i_5\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => \prbs_dqs_tap_cnt_r_reg_n_0_[3]\,
      I1 => \prbs_1st_edge_taps_r_reg_n_0_[3]\,
      O => \prbs_dec_tap_cnt[2]_i_5_n_0\
    );
\prbs_dec_tap_cnt[2]_i_6\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => \prbs_dqs_tap_cnt_r_reg_n_0_[2]\,
      I1 => \prbs_1st_edge_taps_r_reg_n_0_[2]\,
      O => \prbs_dec_tap_cnt[2]_i_6_n_0\
    );
\prbs_dec_tap_cnt[2]_i_7\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => \prbs_dqs_tap_cnt_r_reg_n_0_[1]\,
      I1 => \prbs_1st_edge_taps_r_reg_n_0_[1]\,
      O => \prbs_dec_tap_cnt[2]_i_7_n_0\
    );
\prbs_dec_tap_cnt[2]_i_8\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => \prbs_dqs_tap_cnt_r_reg_n_0_[0]\,
      I1 => \prbs_1st_edge_taps_r_reg_n_0_[0]\,
      O => \prbs_dec_tap_cnt[2]_i_8_n_0\
    );
\prbs_dec_tap_cnt[3]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"CCCCCCC88888888C"
    )
        port map (
      I0 => prbs_state_r(2),
      I1 => \prbs_dec_tap_cnt[3]_i_2_n_0\,
      I2 => prbs_dec_tap_cnt(0),
      I3 => prbs_dec_tap_cnt(1),
      I4 => prbs_dec_tap_cnt(2),
      I5 => prbs_dec_tap_cnt(3),
      O => \prbs_dec_tap_cnt[3]_i_1_n_0\
    );
\prbs_dec_tap_cnt[3]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"BAFAEAFABAAAEAAA"
    )
        port map (
      I0 => \prbs_dec_tap_cnt[3]_i_3_n_0\,
      I1 => prbs_dec_tap_cnt2(4),
      I2 => prbs_found_1st_edge_r_reg_n_0,
      I3 => prbs_found_2nd_edge_r_reg_n_0,
      I4 => \prbs_dec_tap_cnt[3]_i_4_n_0\,
      I5 => prbs_dec_tap_cnt10_out(4),
      O => \prbs_dec_tap_cnt[3]_i_2_n_0\
    );
\prbs_dec_tap_cnt[3]_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"4F"
    )
        port map (
      I0 => prbs_found_1st_edge_r_reg_n_0,
      I1 => \prbs_dqs_tap_cnt_r_reg_n_0_[4]\,
      I2 => prbs_state_r(2),
      O => \prbs_dec_tap_cnt[3]_i_3_n_0\
    );
\prbs_dec_tap_cnt[3]_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"80"
    )
        port map (
      I0 => prbs_dec_tap_cnt2(3),
      I1 => prbs_dec_tap_cnt2(2),
      I2 => prbs_dec_tap_cnt2(1),
      O => \prbs_dec_tap_cnt[3]_i_4_n_0\
    );
\prbs_dec_tap_cnt[4]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFAAA90000AAA9"
    )
        port map (
      I0 => prbs_dec_tap_cnt(4),
      I1 => \prbs_dec_tap_cnt[4]_i_2_n_0\,
      I2 => prbs_dec_tap_cnt(2),
      I3 => prbs_dec_tap_cnt(3),
      I4 => prbs_state_r(2),
      I5 => \prbs_dec_tap_cnt[4]_i_3_n_0\,
      O => \prbs_dec_tap_cnt[4]_i_1_n_0\
    );
\prbs_dec_tap_cnt[4]_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => prbs_dec_tap_cnt(0),
      I1 => prbs_dec_tap_cnt(1),
      O => \prbs_dec_tap_cnt[4]_i_2_n_0\
    );
\prbs_dec_tap_cnt[4]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"66FFF0F06600F0F0"
    )
        port map (
      I0 => prbs_dec_tap_cnt2(5),
      I1 => \prbs_dec_tap_cnt[4]_i_4_n_0\,
      I2 => \prbs_dqs_tap_cnt_r_reg_n_0_[5]\,
      I3 => prbs_found_2nd_edge_r_reg_n_0,
      I4 => prbs_found_1st_edge_r_reg_n_0,
      I5 => prbs_dec_tap_cnt10_out(5),
      O => \prbs_dec_tap_cnt[4]_i_3_n_0\
    );
\prbs_dec_tap_cnt[4]_i_4\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8000"
    )
        port map (
      I0 => prbs_dec_tap_cnt2(1),
      I1 => prbs_dec_tap_cnt2(2),
      I2 => prbs_dec_tap_cnt2(3),
      I3 => prbs_dec_tap_cnt2(4),
      O => \prbs_dec_tap_cnt[4]_i_4_n_0\
    );
\prbs_dec_tap_cnt[4]_i_6\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => \prbs_1st_edge_taps_r_reg_n_0_[5]\,
      I1 => \prbs_dqs_tap_cnt_r_reg_n_0_[5]\,
      O => \prbs_dec_tap_cnt[4]_i_6_n_0\
    );
\prbs_dec_tap_cnt[4]_i_7\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => \prbs_dqs_tap_cnt_r_reg_n_0_[4]\,
      I1 => \prbs_1st_edge_taps_r_reg_n_0_[4]\,
      O => \prbs_dec_tap_cnt[4]_i_7_n_0\
    );
\prbs_dec_tap_cnt[5]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"000000C000000040"
    )
        port map (
      I0 => \prbs_dec_tap_cnt[5]_i_3_n_0\,
      I1 => prbs_state_r(0),
      I2 => prbs_state_r(1),
      I3 => prbs_state_r(4),
      I4 => prbs_state_r(3),
      I5 => prbs_state_r(2),
      O => \prbs_dec_tap_cnt[5]_i_1_n_0\
    );
\prbs_dec_tap_cnt[5]_i_10\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => prbs_2nd_edge_taps_r(3),
      I1 => \prbs_1st_edge_taps_r_reg_n_0_[3]\,
      O => \prbs_dec_tap_cnt[5]_i_10_n_0\
    );
\prbs_dec_tap_cnt[5]_i_11\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => prbs_2nd_edge_taps_r(2),
      I1 => \prbs_1st_edge_taps_r_reg_n_0_[2]\,
      O => \prbs_dec_tap_cnt[5]_i_11_n_0\
    );
\prbs_dec_tap_cnt[5]_i_12\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => prbs_2nd_edge_taps_r(1),
      I1 => \prbs_1st_edge_taps_r_reg_n_0_[1]\,
      O => \prbs_dec_tap_cnt[5]_i_12_n_0\
    );
\prbs_dec_tap_cnt[5]_i_13\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => prbs_2nd_edge_taps_r(0),
      I1 => \prbs_1st_edge_taps_r_reg_n_0_[0]\,
      O => \prbs_dec_tap_cnt[5]_i_13_n_0\
    );
\prbs_dec_tap_cnt[5]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F000000066666666"
    )
        port map (
      I0 => prbs_dec_tap_cnt(5),
      I1 => \prbs_dec_tap_cnt[5]_i_4_n_0\,
      I2 => \prbs_dec_tap_cnt[5]_i_5_n_0\,
      I3 => prbs_found_2nd_edge_r_reg_n_0,
      I4 => prbs_found_1st_edge_r_reg_n_0,
      I5 => prbs_state_r(2),
      O => \prbs_dec_tap_cnt[5]_i_2_n_0\
    );
\prbs_dec_tap_cnt[5]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000000001"
    )
        port map (
      I0 => prbs_dec_tap_cnt(4),
      I1 => prbs_dec_tap_cnt(3),
      I2 => prbs_dec_tap_cnt(2),
      I3 => prbs_dec_tap_cnt(1),
      I4 => prbs_dec_tap_cnt(0),
      I5 => prbs_dec_tap_cnt(5),
      O => \prbs_dec_tap_cnt[5]_i_3_n_0\
    );
\prbs_dec_tap_cnt[5]_i_4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000001"
    )
        port map (
      I0 => prbs_dec_tap_cnt(0),
      I1 => prbs_dec_tap_cnt(1),
      I2 => prbs_dec_tap_cnt(2),
      I3 => prbs_dec_tap_cnt(3),
      I4 => prbs_dec_tap_cnt(4),
      O => \prbs_dec_tap_cnt[5]_i_4_n_0\
    );
\prbs_dec_tap_cnt[5]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"9555555555555555"
    )
        port map (
      I0 => \prbs_dec_tap_cnt_reg[5]_i_6_n_1\,
      I1 => prbs_dec_tap_cnt2(5),
      I2 => prbs_dec_tap_cnt2(1),
      I3 => prbs_dec_tap_cnt2(2),
      I4 => prbs_dec_tap_cnt2(3),
      I5 => prbs_dec_tap_cnt2(4),
      O => \prbs_dec_tap_cnt[5]_i_5_n_0\
    );
\prbs_dec_tap_cnt[5]_i_8\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => prbs_2nd_edge_taps_r(5),
      I1 => \prbs_1st_edge_taps_r_reg_n_0_[5]\,
      O => \prbs_dec_tap_cnt[5]_i_8_n_0\
    );
\prbs_dec_tap_cnt[5]_i_9\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => prbs_2nd_edge_taps_r(4),
      I1 => \prbs_1st_edge_taps_r_reg_n_0_[4]\,
      O => \prbs_dec_tap_cnt[5]_i_9_n_0\
    );
\prbs_dec_tap_cnt_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => \prbs_dec_tap_cnt[5]_i_1_n_0\,
      D => \prbs_dec_tap_cnt[0]_i_1_n_0\,
      Q => prbs_dec_tap_cnt(0),
      R => \prbs_dec_tap_cnt_reg[0]_0\(0)
    );
\prbs_dec_tap_cnt_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => \prbs_dec_tap_cnt[5]_i_1_n_0\,
      D => \prbs_dec_tap_cnt[1]_i_1_n_0\,
      Q => prbs_dec_tap_cnt(1),
      R => \prbs_dec_tap_cnt_reg[0]_0\(0)
    );
\prbs_dec_tap_cnt_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => \prbs_dec_tap_cnt[5]_i_1_n_0\,
      D => \prbs_dec_tap_cnt[2]_i_1_n_0\,
      Q => prbs_dec_tap_cnt(2),
      R => \prbs_dec_tap_cnt_reg[0]_0\(0)
    );
\prbs_dec_tap_cnt_reg[2]_i_4\: unisim.vcomponents.CARRY4
     port map (
      CI => '0',
      CO(3) => \prbs_dec_tap_cnt_reg[2]_i_4_n_0\,
      CO(2) => \prbs_dec_tap_cnt_reg[2]_i_4_n_1\,
      CO(1) => \prbs_dec_tap_cnt_reg[2]_i_4_n_2\,
      CO(0) => \prbs_dec_tap_cnt_reg[2]_i_4_n_3\,
      CYINIT => '1',
      DI(3) => \prbs_dqs_tap_cnt_r_reg_n_0_[3]\,
      DI(2) => \prbs_dqs_tap_cnt_r_reg_n_0_[2]\,
      DI(1) => \prbs_dqs_tap_cnt_r_reg_n_0_[1]\,
      DI(0) => \prbs_dqs_tap_cnt_r_reg_n_0_[0]\,
      O(3 downto 1) => prbs_dec_tap_cnt10_out(3 downto 1),
      O(0) => \NLW_prbs_dec_tap_cnt_reg[2]_i_4_O_UNCONNECTED\(0),
      S(3) => \prbs_dec_tap_cnt[2]_i_5_n_0\,
      S(2) => \prbs_dec_tap_cnt[2]_i_6_n_0\,
      S(1) => \prbs_dec_tap_cnt[2]_i_7_n_0\,
      S(0) => \prbs_dec_tap_cnt[2]_i_8_n_0\
    );
\prbs_dec_tap_cnt_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => \prbs_dec_tap_cnt[5]_i_1_n_0\,
      D => \prbs_dec_tap_cnt[3]_i_1_n_0\,
      Q => prbs_dec_tap_cnt(3),
      R => \prbs_dec_tap_cnt_reg[0]_0\(0)
    );
\prbs_dec_tap_cnt_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => \prbs_dec_tap_cnt[5]_i_1_n_0\,
      D => \prbs_dec_tap_cnt[4]_i_1_n_0\,
      Q => prbs_dec_tap_cnt(4),
      R => \prbs_dec_tap_cnt_reg[0]_0\(0)
    );
\prbs_dec_tap_cnt_reg[4]_i_5\: unisim.vcomponents.CARRY4
     port map (
      CI => \prbs_dec_tap_cnt_reg[2]_i_4_n_0\,
      CO(3 downto 1) => \NLW_prbs_dec_tap_cnt_reg[4]_i_5_CO_UNCONNECTED\(3 downto 1),
      CO(0) => \prbs_dec_tap_cnt_reg[4]_i_5_n_3\,
      CYINIT => '0',
      DI(3 downto 1) => B"000",
      DI(0) => \prbs_dqs_tap_cnt_r_reg_n_0_[4]\,
      O(3 downto 2) => \NLW_prbs_dec_tap_cnt_reg[4]_i_5_O_UNCONNECTED\(3 downto 2),
      O(1 downto 0) => prbs_dec_tap_cnt10_out(5 downto 4),
      S(3 downto 2) => B"00",
      S(1) => \prbs_dec_tap_cnt[4]_i_6_n_0\,
      S(0) => \prbs_dec_tap_cnt[4]_i_7_n_0\
    );
\prbs_dec_tap_cnt_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => \prbs_dec_tap_cnt[5]_i_1_n_0\,
      D => \prbs_dec_tap_cnt[5]_i_2_n_0\,
      Q => prbs_dec_tap_cnt(5),
      R => \prbs_dec_tap_cnt_reg[0]_0\(0)
    );
\prbs_dec_tap_cnt_reg[5]_i_6\: unisim.vcomponents.CARRY4
     port map (
      CI => \prbs_dec_tap_cnt_reg[5]_i_7_n_0\,
      CO(3) => \NLW_prbs_dec_tap_cnt_reg[5]_i_6_CO_UNCONNECTED\(3),
      CO(2) => \prbs_dec_tap_cnt_reg[5]_i_6_n_1\,
      CO(1) => \NLW_prbs_dec_tap_cnt_reg[5]_i_6_CO_UNCONNECTED\(1),
      CO(0) => \prbs_dec_tap_cnt_reg[5]_i_6_n_3\,
      CYINIT => '0',
      DI(3 downto 2) => B"00",
      DI(1 downto 0) => prbs_2nd_edge_taps_r(5 downto 4),
      O(3 downto 2) => \NLW_prbs_dec_tap_cnt_reg[5]_i_6_O_UNCONNECTED\(3 downto 2),
      O(1 downto 0) => prbs_dec_tap_cnt2(5 downto 4),
      S(3 downto 2) => B"01",
      S(1) => \prbs_dec_tap_cnt[5]_i_8_n_0\,
      S(0) => \prbs_dec_tap_cnt[5]_i_9_n_0\
    );
\prbs_dec_tap_cnt_reg[5]_i_7\: unisim.vcomponents.CARRY4
     port map (
      CI => '0',
      CO(3) => \prbs_dec_tap_cnt_reg[5]_i_7_n_0\,
      CO(2) => \prbs_dec_tap_cnt_reg[5]_i_7_n_1\,
      CO(1) => \prbs_dec_tap_cnt_reg[5]_i_7_n_2\,
      CO(0) => \prbs_dec_tap_cnt_reg[5]_i_7_n_3\,
      CYINIT => '1',
      DI(3 downto 0) => prbs_2nd_edge_taps_r(3 downto 0),
      O(3 downto 1) => prbs_dec_tap_cnt2(3 downto 1),
      O(0) => \NLW_prbs_dec_tap_cnt_reg[5]_i_7_O_UNCONNECTED\(0),
      S(3) => \prbs_dec_tap_cnt[5]_i_10_n_0\,
      S(2) => \prbs_dec_tap_cnt[5]_i_11_n_0\,
      S(1) => \prbs_dec_tap_cnt[5]_i_12_n_0\,
      S(0) => \prbs_dec_tap_cnt[5]_i_13_n_0\
    );
\prbs_dqs_cnt_r[0]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \prbs_dqs_cnt_r_reg_n_0_[0]\,
      O => \prbs_dqs_cnt_r[0]_i_1_n_0\
    );
\prbs_dqs_cnt_r[1]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \prbs_dqs_cnt_r_reg_n_0_[0]\,
      I1 => \prbs_dqs_cnt_r_reg_n_0_[1]\,
      O => \prbs_dqs_cnt_r[1]_i_1_n_0\
    );
\prbs_dqs_cnt_r[2]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"6A"
    )
        port map (
      I0 => \prbs_dqs_cnt_r_reg_n_0_[2]\,
      I1 => \prbs_dqs_cnt_r_reg_n_0_[1]\,
      I2 => \prbs_dqs_cnt_r_reg_n_0_[0]\,
      O => \prbs_dqs_cnt_r[2]_i_1_n_0\
    );
\prbs_dqs_cnt_r[3]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0200000000000000"
    )
        port map (
      I0 => \prbs_dqs_cnt_r[3]_i_3_n_0\,
      I1 => prbs_state_r(4),
      I2 => prbs_state_r(0),
      I3 => prbs_state_r(3),
      I4 => prech_done,
      I5 => \prbs_dqs_cnt_r[3]_i_4_n_0\,
      O => \prbs_dqs_cnt_r[3]_i_1_n_0\
    );
\prbs_dqs_cnt_r[3]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6AAA"
    )
        port map (
      I0 => \prbs_dqs_cnt_r_reg_n_0_[3]\,
      I1 => \prbs_dqs_cnt_r_reg_n_0_[0]\,
      I2 => \prbs_dqs_cnt_r_reg_n_0_[1]\,
      I3 => \prbs_dqs_cnt_r_reg_n_0_[2]\,
      O => \prbs_dqs_cnt_r[3]_i_2_n_0\
    );
\prbs_dqs_cnt_r[3]_i_3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => prbs_state_r(1),
      I1 => prbs_state_r(2),
      O => \prbs_dqs_cnt_r[3]_i_3_n_0\
    );
\prbs_dqs_cnt_r[3]_i_4\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"1555"
    )
        port map (
      I0 => \prbs_dqs_cnt_r_reg_n_0_[3]\,
      I1 => \prbs_dqs_cnt_r_reg_n_0_[0]\,
      I2 => \prbs_dqs_cnt_r_reg_n_0_[1]\,
      I3 => \prbs_dqs_cnt_r_reg_n_0_[2]\,
      O => \prbs_dqs_cnt_r[3]_i_4_n_0\
    );
\prbs_dqs_cnt_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => \prbs_dqs_cnt_r[3]_i_1_n_0\,
      D => \prbs_dqs_cnt_r[0]_i_1_n_0\,
      Q => \prbs_dqs_cnt_r_reg_n_0_[0]\,
      R => \prbs_dqs_cnt_r_reg[0]_1\
    );
\prbs_dqs_cnt_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => \prbs_dqs_cnt_r[3]_i_1_n_0\,
      D => \prbs_dqs_cnt_r[1]_i_1_n_0\,
      Q => \prbs_dqs_cnt_r_reg_n_0_[1]\,
      R => \prbs_dqs_cnt_r_reg[0]_1\
    );
\prbs_dqs_cnt_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => \prbs_dqs_cnt_r[3]_i_1_n_0\,
      D => \prbs_dqs_cnt_r[2]_i_1_n_0\,
      Q => \prbs_dqs_cnt_r_reg_n_0_[2]\,
      R => \prbs_dqs_cnt_r_reg[0]_1\
    );
\prbs_dqs_cnt_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => \prbs_dqs_cnt_r[3]_i_1_n_0\,
      D => \prbs_dqs_cnt_r[3]_i_2_n_0\,
      Q => \prbs_dqs_cnt_r_reg_n_0_[3]\,
      R => \prbs_dqs_cnt_r_reg[0]_1\
    );
\prbs_dqs_tap_cnt_r[0]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"8B"
    )
        port map (
      I0 => \^d\(0),
      I1 => \^new_cnt_dqs_r_reg_0\,
      I2 => \prbs_dqs_tap_cnt_r_reg_n_0_[0]\,
      O => \prbs_dqs_tap_cnt_r[0]_i_1_n_0\
    );
\prbs_dqs_tap_cnt_r[1]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FF690069"
    )
        port map (
      I0 => prbs_tap_inc_r,
      I1 => \prbs_dqs_tap_cnt_r_reg_n_0_[1]\,
      I2 => \prbs_dqs_tap_cnt_r_reg_n_0_[0]\,
      I3 => \^new_cnt_dqs_r_reg_0\,
      I4 => \^d\(1),
      O => \prbs_dqs_tap_cnt_r[1]_i_1_n_0\
    );
\prbs_dqs_tap_cnt_r[2]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFF7E8100007E81"
    )
        port map (
      I0 => prbs_tap_inc_r,
      I1 => \prbs_dqs_tap_cnt_r_reg_n_0_[0]\,
      I2 => \prbs_dqs_tap_cnt_r_reg_n_0_[1]\,
      I3 => \prbs_dqs_tap_cnt_r_reg_n_0_[2]\,
      I4 => \^new_cnt_dqs_r_reg_0\,
      I5 => \^d\(2),
      O => \prbs_dqs_tap_cnt_r[2]_i_1_n_0\
    );
\prbs_dqs_tap_cnt_r[3]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFB100B1"
    )
        port map (
      I0 => prbs_tap_inc_r,
      I1 => \prbs_dqs_tap_cnt_r[3]_i_2_n_0\,
      I2 => \prbs_1st_edge_taps_r[3]_i_1_n_0\,
      I3 => \^new_cnt_dqs_r_reg_0\,
      I4 => \^d\(3),
      O => \prbs_dqs_tap_cnt_r[3]_i_1_n_0\
    );
\prbs_dqs_tap_cnt_r[3]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"5556"
    )
        port map (
      I0 => \prbs_dqs_tap_cnt_r_reg_n_0_[3]\,
      I1 => \prbs_dqs_tap_cnt_r_reg_n_0_[0]\,
      I2 => \prbs_dqs_tap_cnt_r_reg_n_0_[1]\,
      I3 => \prbs_dqs_tap_cnt_r_reg_n_0_[2]\,
      O => \prbs_dqs_tap_cnt_r[3]_i_2_n_0\
    );
\prbs_dqs_tap_cnt_r[4]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFB100B1"
    )
        port map (
      I0 => prbs_tap_inc_r,
      I1 => \prbs_dqs_tap_cnt_r[4]_i_2_n_0\,
      I2 => \prbs_1st_edge_taps_r[4]_i_1_n_0\,
      I3 => \^new_cnt_dqs_r_reg_0\,
      I4 => \^d\(4),
      O => \prbs_dqs_tap_cnt_r[4]_i_1_n_0\
    );
\prbs_dqs_tap_cnt_r[4]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"55555556"
    )
        port map (
      I0 => \prbs_dqs_tap_cnt_r_reg_n_0_[4]\,
      I1 => \prbs_dqs_tap_cnt_r_reg_n_0_[2]\,
      I2 => \prbs_dqs_tap_cnt_r_reg_n_0_[1]\,
      I3 => \prbs_dqs_tap_cnt_r_reg_n_0_[0]\,
      I4 => \prbs_dqs_tap_cnt_r_reg_n_0_[3]\,
      O => \prbs_dqs_tap_cnt_r[4]_i_2_n_0\
    );
\prbs_dqs_tap_cnt_r[5]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FEAA"
    )
        port map (
      I0 => \^new_cnt_dqs_r_reg_0\,
      I1 => prbs_tap_inc_r,
      I2 => \prbs_dqs_tap_cnt_r[5]_i_3_n_0\,
      I3 => prbs_tap_en_r_reg_n_0,
      O => \prbs_dqs_tap_cnt_r[5]_i_1_n_0\
    );
\prbs_dqs_tap_cnt_r[5]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFB100B1"
    )
        port map (
      I0 => prbs_tap_inc_r,
      I1 => \prbs_dqs_tap_cnt_r[5]_i_4_n_0\,
      I2 => \prbs_1st_edge_taps_r[5]_i_3_n_0\,
      I3 => \^new_cnt_dqs_r_reg_0\,
      I4 => \^d\(5),
      O => \prbs_dqs_tap_cnt_r[5]_i_2_n_0\
    );
\prbs_dqs_tap_cnt_r[5]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFFFE"
    )
        port map (
      I0 => \prbs_dqs_tap_cnt_r_reg_n_0_[5]\,
      I1 => \prbs_dqs_tap_cnt_r_reg_n_0_[3]\,
      I2 => \prbs_dqs_tap_cnt_r_reg_n_0_[0]\,
      I3 => \prbs_dqs_tap_cnt_r_reg_n_0_[1]\,
      I4 => \prbs_dqs_tap_cnt_r_reg_n_0_[2]\,
      I5 => \prbs_dqs_tap_cnt_r_reg_n_0_[4]\,
      O => \prbs_dqs_tap_cnt_r[5]_i_3_n_0\
    );
\prbs_dqs_tap_cnt_r[5]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"5555555555555556"
    )
        port map (
      I0 => \prbs_dqs_tap_cnt_r_reg_n_0_[5]\,
      I1 => \prbs_dqs_tap_cnt_r_reg_n_0_[3]\,
      I2 => \prbs_dqs_tap_cnt_r_reg_n_0_[0]\,
      I3 => \prbs_dqs_tap_cnt_r_reg_n_0_[1]\,
      I4 => \prbs_dqs_tap_cnt_r_reg_n_0_[2]\,
      I5 => \prbs_dqs_tap_cnt_r_reg_n_0_[4]\,
      O => \prbs_dqs_tap_cnt_r[5]_i_4_n_0\
    );
\prbs_dqs_tap_cnt_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => \prbs_dqs_tap_cnt_r[5]_i_1_n_0\,
      D => \prbs_dqs_tap_cnt_r[0]_i_1_n_0\,
      Q => \prbs_dqs_tap_cnt_r_reg_n_0_[0]\,
      R => \samples_cnt_r_reg[0]_0\
    );
\prbs_dqs_tap_cnt_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => \prbs_dqs_tap_cnt_r[5]_i_1_n_0\,
      D => \prbs_dqs_tap_cnt_r[1]_i_1_n_0\,
      Q => \prbs_dqs_tap_cnt_r_reg_n_0_[1]\,
      R => \samples_cnt_r_reg[0]_0\
    );
\prbs_dqs_tap_cnt_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => \prbs_dqs_tap_cnt_r[5]_i_1_n_0\,
      D => \prbs_dqs_tap_cnt_r[2]_i_1_n_0\,
      Q => \prbs_dqs_tap_cnt_r_reg_n_0_[2]\,
      R => \samples_cnt_r_reg[0]_0\
    );
\prbs_dqs_tap_cnt_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => \prbs_dqs_tap_cnt_r[5]_i_1_n_0\,
      D => \prbs_dqs_tap_cnt_r[3]_i_1_n_0\,
      Q => \prbs_dqs_tap_cnt_r_reg_n_0_[3]\,
      R => \samples_cnt_r_reg[0]_0\
    );
\prbs_dqs_tap_cnt_r_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => \prbs_dqs_tap_cnt_r[5]_i_1_n_0\,
      D => \prbs_dqs_tap_cnt_r[4]_i_1_n_0\,
      Q => \prbs_dqs_tap_cnt_r_reg_n_0_[4]\,
      R => \samples_cnt_r_reg[0]_0\
    );
\prbs_dqs_tap_cnt_r_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => \prbs_dqs_tap_cnt_r[5]_i_1_n_0\,
      D => \prbs_dqs_tap_cnt_r[5]_i_2_n_0\,
      Q => \prbs_dqs_tap_cnt_r_reg_n_0_[5]\,
      R => \samples_cnt_r_reg[0]_0\
    );
prbs_dqs_tap_limit_r_i_1: unisim.vcomponents.LUT3
    generic map(
      INIT => X"01"
    )
        port map (
      I0 => prbs_dqs_tap_limit_r_i_2_n_0,
      I1 => \^new_cnt_dqs_r_reg_0\,
      I2 => \rd_victim_sel_reg[2]_1\,
      O => prbs_dqs_tap_limit_r_i_1_n_0
    );
prbs_dqs_tap_limit_r_i_2: unisim.vcomponents.LUT6
    generic map(
      INIT => X"7FFFFFFFFFFFFFFF"
    )
        port map (
      I0 => \prbs_dqs_tap_cnt_r_reg_n_0_[4]\,
      I1 => \prbs_dqs_tap_cnt_r_reg_n_0_[2]\,
      I2 => \prbs_dqs_tap_cnt_r_reg_n_0_[0]\,
      I3 => \prbs_dqs_tap_cnt_r_reg_n_0_[1]\,
      I4 => \prbs_dqs_tap_cnt_r_reg_n_0_[3]\,
      I5 => \prbs_dqs_tap_cnt_r_reg_n_0_[5]\,
      O => prbs_dqs_tap_limit_r_i_2_n_0
    );
prbs_dqs_tap_limit_r_reg: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => '1',
      D => prbs_dqs_tap_limit_r_i_1_n_0,
      Q => prbs_dqs_tap_limit_r,
      R => '0'
    );
prbs_found_1st_edge_r_i_1: unisim.vcomponents.LUT4
    generic map(
      INIT => X"1F10"
    )
        port map (
      I0 => \prbs_inc_tap_cnt[5]_i_4_n_0\,
      I1 => prbs_state_r(3),
      I2 => \prbs_2nd_edge_taps_r[5]_i_4_n_0\,
      I3 => prbs_found_1st_edge_r_reg_n_0,
      O => prbs_found_1st_edge_r_i_1_n_0
    );
prbs_found_1st_edge_r_reg: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => '1',
      D => prbs_found_1st_edge_r_i_1_n_0,
      Q => prbs_found_1st_edge_r_reg_n_0,
      R => \prbs_dec_tap_cnt_reg[0]_0\(0)
    );
prbs_found_2nd_edge_r_i_1: unisim.vcomponents.LUT5
    generic map(
      INIT => X"73FF2200"
    )
        port map (
      I0 => prbs_found_1st_edge_r_reg_n_0,
      I1 => prbs_state_r(3),
      I2 => prbs_state_r(1),
      I3 => \prbs_2nd_edge_taps_r[5]_i_4_n_0\,
      I4 => prbs_found_2nd_edge_r_reg_n_0,
      O => prbs_found_2nd_edge_r_i_1_n_0
    );
prbs_found_2nd_edge_r_reg: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => '1',
      D => prbs_found_2nd_edge_r_i_1_n_0,
      Q => prbs_found_2nd_edge_r_reg_n_0,
      R => prbs_found_2nd_edge_r_reg_0
    );
\prbs_inc_tap_cnt[0]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"06F6"
    )
        port map (
      I0 => \prbs_dqs_tap_cnt_r_reg_n_0_[0]\,
      I1 => rdlvl_cpt_tap_cnt(0),
      I2 => prbs_state_r(2),
      I3 => \prbs_inc_tap_cnt_reg_n_0_[0]\,
      O => \prbs_inc_tap_cnt[0]_i_1_n_0\
    );
\prbs_inc_tap_cnt[1]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8BB4744"
    )
        port map (
      I0 => \prbs_inc_tap_cnt_reg_n_0_[0]\,
      I1 => prbs_state_r(2),
      I2 => rdlvl_cpt_tap_cnt(0),
      I3 => \prbs_dqs_tap_cnt_r_reg_n_0_[0]\,
      I4 => \prbs_inc_tap_cnt[1]_i_2_n_0\,
      O => \prbs_inc_tap_cnt[1]_i_1_n_0\
    );
\prbs_inc_tap_cnt[1]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F606"
    )
        port map (
      I0 => \prbs_dqs_tap_cnt_r_reg_n_0_[1]\,
      I1 => rdlvl_cpt_tap_cnt(1),
      I2 => prbs_state_r(2),
      I3 => \prbs_inc_tap_cnt_reg_n_0_[1]\,
      O => \prbs_inc_tap_cnt[1]_i_2_n_0\
    );
\prbs_inc_tap_cnt[2]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"656A6A659A95959A"
    )
        port map (
      I0 => \prbs_inc_tap_cnt[2]_i_2_n_0\,
      I1 => \prbs_inc_tap_cnt_reg_n_0_[2]\,
      I2 => prbs_state_r(2),
      I3 => rdlvl_cpt_tap_cnt(2),
      I4 => \prbs_dqs_tap_cnt_r_reg_n_0_[2]\,
      I5 => \prbs_inc_tap_cnt[2]_i_3_n_0\,
      O => \prbs_inc_tap_cnt[2]_i_1_n_0\
    );
\prbs_inc_tap_cnt[2]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00004744"
    )
        port map (
      I0 => \prbs_inc_tap_cnt_reg_n_0_[0]\,
      I1 => prbs_state_r(2),
      I2 => rdlvl_cpt_tap_cnt(0),
      I3 => \prbs_dqs_tap_cnt_r_reg_n_0_[0]\,
      I4 => \prbs_inc_tap_cnt[1]_i_2_n_0\,
      O => \prbs_inc_tap_cnt[2]_i_2_n_0\
    );
\prbs_inc_tap_cnt[2]_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"F4"
    )
        port map (
      I0 => rdlvl_cpt_tap_cnt(1),
      I1 => \prbs_dqs_tap_cnt_r_reg_n_0_[1]\,
      I2 => prbs_state_r(2),
      O => \prbs_inc_tap_cnt[2]_i_3_n_0\
    );
\prbs_inc_tap_cnt[3]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AA9655965569AA69"
    )
        port map (
      I0 => \prbs_inc_tap_cnt[3]_i_2_n_0\,
      I1 => \prbs_dqs_tap_cnt_r_reg_n_0_[3]\,
      I2 => rdlvl_cpt_tap_cnt(3),
      I3 => prbs_state_r(2),
      I4 => \prbs_inc_tap_cnt_reg_n_0_[3]\,
      I5 => \prbs_inc_tap_cnt[3]_i_3_n_0\,
      O => \prbs_inc_tap_cnt[3]_i_1_n_0\
    );
\prbs_inc_tap_cnt[3]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"EFEAEAEF8A80808A"
    )
        port map (
      I0 => \prbs_inc_tap_cnt[2]_i_2_n_0\,
      I1 => \prbs_inc_tap_cnt_reg_n_0_[2]\,
      I2 => prbs_state_r(2),
      I3 => rdlvl_cpt_tap_cnt(2),
      I4 => \prbs_dqs_tap_cnt_r_reg_n_0_[2]\,
      I5 => \prbs_inc_tap_cnt[2]_i_3_n_0\,
      O => \prbs_inc_tap_cnt[3]_i_2_n_0\
    );
\prbs_inc_tap_cnt[3]_i_3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FD0D"
    )
        port map (
      I0 => \prbs_dqs_tap_cnt_r_reg_n_0_[2]\,
      I1 => rdlvl_cpt_tap_cnt(2),
      I2 => prbs_state_r(2),
      I3 => \prbs_inc_tap_cnt_reg_n_0_[2]\,
      O => \prbs_inc_tap_cnt[3]_i_3_n_0\
    );
\prbs_inc_tap_cnt[4]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AA9655965569AA69"
    )
        port map (
      I0 => \prbs_inc_tap_cnt[5]_i_6_n_0\,
      I1 => \prbs_dqs_tap_cnt_r_reg_n_0_[4]\,
      I2 => rdlvl_cpt_tap_cnt(4),
      I3 => prbs_state_r(2),
      I4 => \prbs_inc_tap_cnt_reg_n_0_[4]\,
      I5 => \prbs_inc_tap_cnt[5]_i_7_n_0\,
      O => \prbs_inc_tap_cnt[4]_i_1_n_0\
    );
\prbs_inc_tap_cnt[5]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAAAAAAAAAAE"
    )
        port map (
      I0 => \prbs_inc_tap_cnt[5]_i_3_n_0\,
      I1 => \^num_samples_done_r\,
      I2 => prbs_dqs_tap_limit_r,
      I3 => \prbs_inc_tap_cnt[5]_i_4_n_0\,
      I4 => \prbs_inc_tap_cnt[5]_i_5_n_0\,
      I5 => prbs_found_1st_edge_r_reg_n_0,
      O => prbs_inc_tap_cnt
    );
\prbs_inc_tap_cnt[5]_i_10\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"FE"
    )
        port map (
      I0 => \prbs_dqs_tap_cnt_r_reg_n_0_[2]\,
      I1 => \prbs_dqs_tap_cnt_r_reg_n_0_[1]\,
      I2 => \prbs_dqs_tap_cnt_r_reg_n_0_[0]\,
      O => \prbs_inc_tap_cnt[5]_i_10_n_0\
    );
\prbs_inc_tap_cnt[5]_i_11\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F909"
    )
        port map (
      I0 => \prbs_dqs_tap_cnt_r_reg_n_0_[3]\,
      I1 => rdlvl_cpt_tap_cnt(3),
      I2 => prbs_state_r(2),
      I3 => \prbs_inc_tap_cnt_reg_n_0_[3]\,
      O => \prbs_inc_tap_cnt[5]_i_11_n_0\
    );
\prbs_inc_tap_cnt[5]_i_12\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \prbs_inc_tap_cnt_reg_n_0_[2]\,
      I1 => prbs_state_r(2),
      I2 => rdlvl_cpt_tap_cnt(2),
      O => \prbs_inc_tap_cnt[5]_i_12_n_0\
    );
\prbs_inc_tap_cnt[5]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"B4B4B42DD2D2D2B4"
    )
        port map (
      I0 => \prbs_inc_tap_cnt[5]_i_6_n_0\,
      I1 => \prbs_inc_tap_cnt[5]_i_7_n_0\,
      I2 => \prbs_inc_tap_cnt[5]_i_8_n_0\,
      I3 => prbs_state_r(2),
      I4 => \prbs_dqs_tap_cnt_r_reg_n_0_[4]\,
      I5 => \prbs_inc_tap_cnt[5]_i_9_n_0\,
      O => \prbs_inc_tap_cnt[5]_i_2_n_0\
    );
\prbs_inc_tap_cnt[5]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0002000000000000"
    )
        port map (
      I0 => prbs_state_r(0),
      I1 => prbs_state_r(1),
      I2 => prbs_state_r(4),
      I3 => prbs_state_r(3),
      I4 => prbs_state_r(2),
      I5 => \prbs_state_r[2]_i_5_n_0\,
      O => \prbs_inc_tap_cnt[5]_i_3_n_0\
    );
\prbs_inc_tap_cnt[5]_i_4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000FFFE"
    )
        port map (
      I0 => \prbs_dqs_tap_cnt_r_reg_n_0_[4]\,
      I1 => \prbs_inc_tap_cnt[5]_i_10_n_0\,
      I2 => \prbs_dqs_tap_cnt_r_reg_n_0_[3]\,
      I3 => \prbs_dqs_tap_cnt_r_reg_n_0_[5]\,
      I4 => compare_err_latch_reg_n_0,
      O => \prbs_inc_tap_cnt[5]_i_4_n_0\
    );
\prbs_inc_tap_cnt[5]_i_5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFFFFB"
    )
        port map (
      I0 => prbs_state_r(0),
      I1 => prbs_state_r(1),
      I2 => prbs_state_r(2),
      I3 => prbs_state_r(4),
      I4 => prbs_state_r(3),
      O => \prbs_inc_tap_cnt[5]_i_5_n_0\
    );
\prbs_inc_tap_cnt[5]_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"A8EAA8EAA8EA80A8"
    )
        port map (
      I0 => \prbs_inc_tap_cnt[5]_i_11_n_0\,
      I1 => \prbs_inc_tap_cnt[2]_i_3_n_0\,
      I2 => \prbs_inc_tap_cnt[2]_i_2_n_0\,
      I3 => \prbs_inc_tap_cnt[5]_i_12_n_0\,
      I4 => \prbs_dqs_tap_cnt_r_reg_n_0_[2]\,
      I5 => prbs_state_r(2),
      O => \prbs_inc_tap_cnt[5]_i_6_n_0\
    );
\prbs_inc_tap_cnt[5]_i_7\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FD0D"
    )
        port map (
      I0 => \prbs_dqs_tap_cnt_r_reg_n_0_[3]\,
      I1 => rdlvl_cpt_tap_cnt(3),
      I2 => prbs_state_r(2),
      I3 => \prbs_inc_tap_cnt_reg_n_0_[3]\,
      O => \prbs_inc_tap_cnt[5]_i_7_n_0\
    );
\prbs_inc_tap_cnt[5]_i_8\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F909"
    )
        port map (
      I0 => \prbs_dqs_tap_cnt_r_reg_n_0_[5]\,
      I1 => rdlvl_cpt_tap_cnt(5),
      I2 => prbs_state_r(2),
      I3 => \prbs_inc_tap_cnt_reg_n_0_[5]\,
      O => \prbs_inc_tap_cnt[5]_i_8_n_0\
    );
\prbs_inc_tap_cnt[5]_i_9\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \prbs_inc_tap_cnt_reg_n_0_[4]\,
      I1 => prbs_state_r(2),
      I2 => rdlvl_cpt_tap_cnt(4),
      O => \prbs_inc_tap_cnt[5]_i_9_n_0\
    );
\prbs_inc_tap_cnt_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => prbs_inc_tap_cnt,
      D => \prbs_inc_tap_cnt[0]_i_1_n_0\,
      Q => \prbs_inc_tap_cnt_reg_n_0_[0]\,
      R => \match_flag_and_reg[7]_0\
    );
\prbs_inc_tap_cnt_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => prbs_inc_tap_cnt,
      D => \prbs_inc_tap_cnt[1]_i_1_n_0\,
      Q => \prbs_inc_tap_cnt_reg_n_0_[1]\,
      R => \match_flag_and_reg[7]_0\
    );
\prbs_inc_tap_cnt_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => prbs_inc_tap_cnt,
      D => \prbs_inc_tap_cnt[2]_i_1_n_0\,
      Q => \prbs_inc_tap_cnt_reg_n_0_[2]\,
      R => \match_flag_and_reg[7]_0\
    );
\prbs_inc_tap_cnt_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => prbs_inc_tap_cnt,
      D => \prbs_inc_tap_cnt[3]_i_1_n_0\,
      Q => \prbs_inc_tap_cnt_reg_n_0_[3]\,
      R => \match_flag_and_reg[7]_0\
    );
\prbs_inc_tap_cnt_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => prbs_inc_tap_cnt,
      D => \prbs_inc_tap_cnt[4]_i_1_n_0\,
      Q => \prbs_inc_tap_cnt_reg_n_0_[4]\,
      R => \match_flag_and_reg[7]_0\
    );
\prbs_inc_tap_cnt_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => prbs_inc_tap_cnt,
      D => \prbs_inc_tap_cnt[5]_i_2_n_0\,
      Q => \prbs_inc_tap_cnt_reg_n_0_[5]\,
      R => \match_flag_and_reg[7]_0\
    );
prbs_last_byte_done_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FC3CFFFF00040000"
    )
        port map (
      I0 => \prbs_dqs_cnt_r[3]_i_4_n_0\,
      I1 => prbs_state_r(3),
      I2 => prbs_state_r(1),
      I3 => prbs_state_r(0),
      I4 => prbs_last_byte_done_i_2_n_0,
      I5 => \^prbs_last_byte_done\,
      O => prbs_last_byte_done_i_1_n_0
    );
prbs_last_byte_done_i_2: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => prbs_state_r(4),
      I1 => prbs_state_r(2),
      O => prbs_last_byte_done_i_2_n_0
    );
prbs_last_byte_done_reg: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => '1',
      D => prbs_last_byte_done_i_1_n_0,
      Q => \^prbs_last_byte_done\,
      R => \prbs_dec_tap_cnt_reg[0]_0\(0)
    );
prbs_prech_req_r_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"CFFFDF0F00001000"
    )
        port map (
      I0 => prech_done,
      I1 => prbs_state_r(0),
      I2 => prbs_last_byte_done_i_2_n_0,
      I3 => prbs_state_r(3),
      I4 => prbs_state_r(1),
      I5 => prbs_prech_req_r,
      O => prbs_prech_req_r_i_1_n_0
    );
prbs_prech_req_r_reg: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => '1',
      D => prbs_prech_req_r_i_1_n_0,
      Q => prbs_prech_req_r,
      R => \match_flag_and_reg[7]_0\
    );
prbs_rdlvl_done_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFDFFFFF00100000"
    )
        port map (
      I0 => edge_det_error_reg_n_0,
      I1 => prbs_state_r(4),
      I2 => prbs_state_r(3),
      I3 => prbs_state_r(0),
      I4 => \prbs_state_r[3]_i_4_n_0\,
      I5 => \^prbs_rdlvl_done_reg_0\,
      O => prbs_rdlvl_done_i_1_n_0
    );
prbs_rdlvl_done_pulse_i_1: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \^prbs_rdlvl_done_reg_0\,
      I1 => prbs_rdlvl_done_r1,
      O => prbs_rdlvl_done_pulse0
    );
prbs_rdlvl_done_reg: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => '1',
      D => prbs_rdlvl_done_i_1_n_0,
      Q => \^prbs_rdlvl_done_reg_0\,
      R => \samples_cnt_r_reg[0]_0\
    );
prbs_rdlvl_prech_req_reg: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => '1',
      D => prbs_prech_req_r,
      Q => prbs_rdlvl_prech_req_reg_0,
      R => \prbs_dec_tap_cnt_reg[0]_0\(0)
    );
prbs_rdlvl_start_r_reg: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => '1',
      D => prbs_rdlvl_start_r_reg_0,
      Q => \^prbs_rdlvl_start_r\,
      R => '0'
    );
\prbs_state_r[0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8AFF8AFF8AFF8A8A"
    )
        port map (
      I0 => prbs_state_r(4),
      I1 => prbs_state_r(2),
      I2 => \prbs_state_r[0]_i_2_n_0\,
      I3 => \prbs_state_r[0]_i_3_n_0\,
      I4 => \prbs_state_r[0]_i_4_n_0\,
      I5 => \prbs_state_r[0]_i_5_n_0\,
      O => \prbs_state_r[0]_i_1_n_0\
    );
\prbs_state_r[0]_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => prbs_state_r(0),
      I1 => prbs_state_r(1),
      O => \prbs_state_r[0]_i_2_n_0\
    );
\prbs_state_r[0]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFAFA10000"
    )
        port map (
      I0 => prbs_state_r(0),
      I1 => \prbs_dqs_cnt_r[3]_i_4_n_0\,
      I2 => prbs_state_r(2),
      I3 => prbs_state_r(1),
      I4 => prbs_state_r(3),
      I5 => prbs_state_r(4),
      O => \prbs_state_r[0]_i_3_n_0\
    );
\prbs_state_r[0]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000DE0000"
    )
        port map (
      I0 => prbs_found_1st_edge_r_reg_n_0,
      I1 => prbs_dqs_tap_limit_r,
      I2 => \prbs_inc_tap_cnt[5]_i_4_n_0\,
      I3 => prbs_state_r(2),
      I4 => prbs_state_r(1),
      I5 => prbs_state_r(0),
      O => \prbs_state_r[0]_i_4_n_0\
    );
\prbs_state_r[0]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFC0C0FFFFC707"
    )
        port map (
      I0 => \prbs_dec_tap_cnt[5]_i_3_n_0\,
      I1 => prbs_state_r(2),
      I2 => prbs_state_r(1),
      I3 => \prbs_state_r[2]_i_5_n_0\,
      I4 => \prbs_state_r[1]_i_4_n_0\,
      I5 => prbs_state_r(0),
      O => \prbs_state_r[0]_i_5_n_0\
    );
\prbs_state_r[1]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFF55101010"
    )
        port map (
      I0 => prbs_state_r(4),
      I1 => \prbs_state_r[1]_i_2_n_0\,
      I2 => \prbs_state_r[1]_i_3_n_0\,
      I3 => \prbs_state_r[1]_i_4_n_0\,
      I4 => \prbs_state_r[1]_i_5_n_0\,
      I5 => \prbs_state_r[1]_i_6_n_0\,
      O => \prbs_state_r[1]_i_1_n_0\
    );
\prbs_state_r[1]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFEFCFC30307575"
    )
        port map (
      I0 => prbs_state_r(0),
      I1 => prbs_state_r(4),
      I2 => prbs_state_r(3),
      I3 => \prbs_state_r[2]_i_5_n_0\,
      I4 => prbs_state_r(1),
      I5 => prbs_state_r(2),
      O => \prbs_state_r[1]_i_2_n_0\
    );
\prbs_state_r[1]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFF5054FFFFFFFF"
    )
        port map (
      I0 => prbs_state_r(0),
      I1 => prbs_found_1st_edge_r_reg_n_0,
      I2 => prbs_dqs_tap_limit_r,
      I3 => \prbs_inc_tap_cnt[5]_i_4_n_0\,
      I4 => prbs_state_r(2),
      I5 => prbs_state_r(1),
      O => \prbs_state_r[1]_i_3_n_0\
    );
\prbs_state_r[1]_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => prbs_state_r(2),
      I1 => prbs_state_r(4),
      I2 => prbs_state_r(3),
      O => \prbs_state_r[1]_i_4_n_0\
    );
\prbs_state_r[1]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"5500551155005F11"
    )
        port map (
      I0 => prbs_state_r(1),
      I1 => \prbs_dqs_cnt_r[3]_i_4_n_0\,
      I2 => \fine_pi_dec_cnt[5]_i_4_n_0\,
      I3 => prbs_state_r(2),
      I4 => prbs_state_r(0),
      I5 => fine_inc_stage_reg_n_0,
      O => \prbs_state_r[1]_i_5_n_0\
    );
\prbs_state_r[1]_i_6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"CC620000"
    )
        port map (
      I0 => prbs_state_r(1),
      I1 => prbs_state_r(0),
      I2 => \smallest_right_edge[5]_i_3_n_0\,
      I3 => prbs_state_r(2),
      I4 => prbs_state_r(4),
      O => \prbs_state_r[1]_i_6_n_0\
    );
\prbs_state_r[2]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFFF10"
    )
        port map (
      I0 => prbs_state_r(4),
      I1 => prbs_state_r(3),
      I2 => \prbs_state_r[2]_i_2_n_0\,
      I3 => \prbs_state_r[2]_i_3_n_0\,
      I4 => \prbs_state_r[2]_i_4_n_0\,
      O => \prbs_state_r[2]_i_1_n_0\
    );
\prbs_state_r[2]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"EEFCCC00EE30CC00"
    )
        port map (
      I0 => \prbs_state_r[2]_i_5_n_0\,
      I1 => prbs_state_r(0),
      I2 => \prbs_state_r[4]_i_12_n_0\,
      I3 => prbs_state_r(2),
      I4 => prbs_state_r(1),
      I5 => \prbs_state_r[3]_i_6_n_0\,
      O => \prbs_state_r[2]_i_2_n_0\
    );
\prbs_state_r[2]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0040444444440000"
    )
        port map (
      I0 => prbs_state_r(4),
      I1 => prbs_state_r(3),
      I2 => \fine_pi_dec_cnt[5]_i_4_n_0\,
      I3 => prbs_state_r(0),
      I4 => prbs_state_r(2),
      I5 => prbs_state_r(1),
      O => \prbs_state_r[2]_i_3_n_0\
    );
\prbs_state_r[2]_i_4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"62660000"
    )
        port map (
      I0 => prbs_state_r(2),
      I1 => prbs_state_r(0),
      I2 => prbs_state_r(1),
      I3 => \smallest_right_edge[5]_i_3_n_0\,
      I4 => prbs_state_r(4),
      O => \prbs_state_r[2]_i_4_n_0\
    );
\prbs_state_r[2]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFFFE"
    )
        port map (
      I0 => \prbs_inc_tap_cnt_reg_n_0_[1]\,
      I1 => \prbs_inc_tap_cnt_reg_n_0_[2]\,
      I2 => \prbs_inc_tap_cnt_reg_n_0_[0]\,
      I3 => \prbs_inc_tap_cnt_reg_n_0_[5]\,
      I4 => \prbs_inc_tap_cnt_reg_n_0_[4]\,
      I5 => \prbs_inc_tap_cnt_reg_n_0_[3]\,
      O => \prbs_state_r[2]_i_5_n_0\
    );
\prbs_state_r[3]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"000000000E00FFFF"
    )
        port map (
      I0 => \prbs_state_r[3]_i_2_n_0\,
      I1 => \prbs_state_r[3]_i_3_n_0\,
      I2 => prbs_state_r(3),
      I3 => \prbs_state_r[3]_i_4_n_0\,
      I4 => \prbs_state_r[3]_i_5_n_0\,
      I5 => prbs_state_r(4),
      O => \prbs_state_r[3]_i_1_n_0\
    );
\prbs_state_r[3]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"00DC"
    )
        port map (
      I0 => \prbs_inc_tap_cnt[5]_i_4_n_0\,
      I1 => prbs_dqs_tap_limit_r,
      I2 => prbs_found_1st_edge_r_reg_n_0,
      I3 => prbs_state_r(0),
      O => \prbs_state_r[3]_i_2_n_0\
    );
\prbs_state_r[3]_i_3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => prbs_state_r(0),
      I1 => \prbs_state_r[3]_i_6_n_0\,
      O => \prbs_state_r[3]_i_3_n_0\
    );
\prbs_state_r[3]_i_4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => prbs_state_r(1),
      I1 => prbs_state_r(2),
      O => \prbs_state_r[3]_i_4_n_0\
    );
\prbs_state_r[3]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FF0F4FFF0FFF0F0F"
    )
        port map (
      I0 => \fine_pi_dec_cnt[5]_i_4_n_0\,
      I1 => fine_inc_stage_reg_n_0,
      I2 => \prbs_state_r[1]_i_4_n_0\,
      I3 => prbs_state_r(1),
      I4 => prbs_state_r(0),
      I5 => prbs_state_r(2),
      O => \prbs_state_r[3]_i_5_n_0\
    );
\prbs_state_r[3]_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFEFF"
    )
        port map (
      I0 => prbs_dec_tap_cnt(4),
      I1 => prbs_dec_tap_cnt(5),
      I2 => prbs_dec_tap_cnt(1),
      I3 => prbs_dec_tap_cnt(0),
      I4 => prbs_dec_tap_cnt(3),
      I5 => prbs_dec_tap_cnt(2),
      O => \prbs_state_r[3]_i_6_n_0\
    );
\prbs_state_r[4]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFCCCECFCE"
    )
        port map (
      I0 => \prbs_state_r[4]_i_3_n_0\,
      I1 => \prbs_state_r[4]_i_4_n_0\,
      I2 => \prbs_state_r[4]_i_5_n_0\,
      I3 => prbs_state_r(4),
      I4 => \prbs_state_r[4]_i_6_n_0\,
      I5 => \prbs_state_r[4]_i_7_n_0\,
      O => \prbs_state_r[4]_i_1_n_0\
    );
\prbs_state_r[4]_i_10\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFAFFFAA0FCA0A0"
    )
        port map (
      I0 => cnt_wait_state,
      I1 => prech_done,
      I2 => prbs_state_r(2),
      I3 => prbs_state_r(1),
      I4 => prbs_state_r(3),
      I5 => prbs_state_r(0),
      O => \prbs_state_r[4]_i_10_n_0\
    );
\prbs_state_r[4]_i_11\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => prbs_state_r(3),
      I1 => prbs_state_r(4),
      O => \prbs_state_r[4]_i_11_n_0\
    );
\prbs_state_r[4]_i_12\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"31"
    )
        port map (
      I0 => prbs_found_1st_edge_r_reg_n_0,
      I1 => prbs_dqs_tap_limit_r,
      I2 => \prbs_inc_tap_cnt[5]_i_4_n_0\,
      O => \prbs_state_r[4]_i_12_n_0\
    );
\prbs_state_r[4]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"2A2A082A"
    )
        port map (
      I0 => \prbs_state_r[4]_i_8_n_0\,
      I1 => prbs_state_r(4),
      I2 => prbs_state_r(2),
      I3 => prbs_state_r(3),
      I4 => \prbs_state_r[4]_i_9_n_0\,
      O => \prbs_state_r[4]_i_2_n_0\
    );
\prbs_state_r[4]_i_3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0004"
    )
        port map (
      I0 => \^prbs_rdlvl_start_r\,
      I1 => prbs_rdlvl_start_r_reg_0,
      I2 => prbs_state_r(0),
      I3 => prbs_state_r(1),
      O => \prbs_state_r[4]_i_3_n_0\
    );
\prbs_state_r[4]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000FFFF00000008"
    )
        port map (
      I0 => \^num_samples_done_r\,
      I1 => prbs_state_r(1),
      I2 => prbs_state_r(2),
      I3 => prbs_state_r(3),
      I4 => prbs_state_r(4),
      I5 => \prbs_state_r[4]_i_10_n_0\,
      O => \prbs_state_r[4]_i_4_n_0\
    );
\prbs_state_r[4]_i_5\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => prbs_state_r(3),
      I1 => prbs_state_r(2),
      O => \prbs_state_r[4]_i_5_n_0\
    );
\prbs_state_r[4]_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"3300000F3355FF0F"
    )
        port map (
      I0 => num_samples_done_ind_reg_n_0,
      I1 => \stage_cnt[0]_i_2_n_0\,
      I2 => cnt_wait_state,
      I3 => prbs_state_r(0),
      I4 => prbs_state_r(1),
      I5 => \^num_samples_done_r\,
      O => \prbs_state_r[4]_i_6_n_0\
    );
\prbs_state_r[4]_i_7\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000800080008"
    )
        port map (
      I0 => complex_act_start,
      I1 => prbs_state_r(2),
      I2 => prbs_state_r(1),
      I3 => \prbs_state_r[4]_i_11_n_0\,
      I4 => prbs_state_r(0),
      I5 => edge_det_error_reg_n_0,
      O => \prbs_state_r[4]_i_7_n_0\
    );
\prbs_state_r[4]_i_8\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFEEEEEEEEFEEEEE"
    )
        port map (
      I0 => prbs_state_r(3),
      I1 => prbs_state_r(4),
      I2 => \prbs_state_r[4]_i_12_n_0\,
      I3 => prbs_state_r(2),
      I4 => prbs_state_r(1),
      I5 => prbs_state_r(0),
      O => \prbs_state_r[4]_i_8_n_0\
    );
\prbs_state_r[4]_i_9\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"F4000000"
    )
        port map (
      I0 => \fine_pi_dec_cnt[5]_i_4_n_0\,
      I1 => fine_inc_stage_reg_n_0,
      I2 => prbs_state_r(0),
      I3 => prbs_state_r(1),
      I4 => prbs_state_r(2),
      O => \prbs_state_r[4]_i_9_n_0\
    );
\prbs_state_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => \prbs_state_r[4]_i_1_n_0\,
      D => \prbs_state_r[0]_i_1_n_0\,
      Q => prbs_state_r(0),
      R => \samples_cnt_r_reg[0]_0\
    );
\prbs_state_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => \prbs_state_r[4]_i_1_n_0\,
      D => \prbs_state_r[1]_i_1_n_0\,
      Q => prbs_state_r(1),
      R => \samples_cnt_r_reg[0]_0\
    );
\prbs_state_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => \prbs_state_r[4]_i_1_n_0\,
      D => \prbs_state_r[2]_i_1_n_0\,
      Q => prbs_state_r(2),
      R => \samples_cnt_r_reg[0]_0\
    );
\prbs_state_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => \prbs_state_r[4]_i_1_n_0\,
      D => \prbs_state_r[3]_i_1_n_0\,
      Q => prbs_state_r(3),
      R => \samples_cnt_r_reg[0]_0\
    );
\prbs_state_r_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => \prbs_state_r[4]_i_1_n_0\,
      D => \prbs_state_r[4]_i_2_n_0\,
      Q => prbs_state_r(4),
      R => \samples_cnt_r_reg[0]_0\
    );
prbs_tap_en_r_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FD00FFFFFD000000"
    )
        port map (
      I0 => prbs_state_r(3),
      I1 => prbs_state_r(1),
      I2 => \fine_pi_dec_cnt[5]_i_4_n_0\,
      I3 => prbs_state_r(0),
      I4 => prbs_tap_en_r,
      I5 => prbs_tap_en_r_reg_n_0,
      O => prbs_tap_en_r_i_1_n_0
    );
prbs_tap_en_r_reg: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => '1',
      D => prbs_tap_en_r_i_1_n_0,
      Q => prbs_tap_en_r_reg_n_0,
      R => \prbs_dec_tap_cnt_reg[0]_0\(0)
    );
prbs_tap_inc_r_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8088FFFF80880000"
    )
        port map (
      I0 => prbs_state_r(2),
      I1 => prbs_state_r(0),
      I2 => prbs_state_r(1),
      I3 => prbs_state_r(3),
      I4 => prbs_tap_en_r,
      I5 => prbs_tap_inc_r,
      O => prbs_tap_inc_r_i_1_n_0
    );
prbs_tap_inc_r_i_2: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFF00001006"
    )
        port map (
      I0 => prbs_state_r(3),
      I1 => prbs_state_r(4),
      I2 => prbs_state_r(1),
      I3 => prbs_state_r(0),
      I4 => prbs_state_r(2),
      I5 => prbs_tap_inc_r_i_3_n_0,
      O => prbs_tap_en_r
    );
prbs_tap_inc_r_i_3: unisim.vcomponents.LUT6
    generic map(
      INIT => X"000000005BFB0BBB"
    )
        port map (
      I0 => prbs_state_r(1),
      I1 => prbs_state_r(3),
      I2 => prbs_state_r(0),
      I3 => prbs_dqs_tap_limit_r,
      I4 => \fine_pi_dec_cnt[5]_i_4_n_0\,
      I5 => prbs_tap_inc_r_i_4_n_0,
      O => prbs_tap_inc_r_i_3_n_0
    );
prbs_tap_inc_r_i_4: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFF4440FFFF"
    )
        port map (
      I0 => prbs_state_r(3),
      I1 => prbs_state_r(0),
      I2 => prbs_dqs_tap_limit_r,
      I3 => prbs_state_r(1),
      I4 => prbs_state_r(2),
      I5 => prbs_state_r(4),
      O => prbs_tap_inc_r_i_4_n_0
    );
prbs_tap_inc_r_reg: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => '1',
      D => prbs_tap_inc_r_i_1_n_0,
      Q => prbs_tap_inc_r,
      R => \samples_cnt_r_reg[0]_0\
    );
\rd_mux_sel_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => '1',
      D => \prbs_dqs_cnt_r_reg_n_0_[0]\,
      Q => \rd_mux_sel_r_reg[2]_0\(0),
      R => '0'
    );
\rd_mux_sel_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => '1',
      D => \prbs_dqs_cnt_r_reg_n_0_[1]\,
      Q => \rd_mux_sel_r_reg[2]_0\(1),
      R => '0'
    );
\rd_mux_sel_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => '1',
      D => \prbs_dqs_cnt_r_reg_n_0_[2]\,
      Q => \rd_mux_sel_r_reg[2]_0\(2),
      R => '0'
    );
rd_valid_r1_reg: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => '1',
      D => mux_rd_valid_r,
      Q => rd_valid_r1,
      R => '0'
    );
rd_valid_r2_reg: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => '1',
      D => rd_valid_r1,
      Q => rd_valid_r2_reg_n_0,
      R => '0'
    );
\rd_victim_sel[0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"000000000000E5A5"
    )
        port map (
      I0 => \^samples_cnt_r_reg[11]_0\,
      I1 => \^rd_victim_sel_reg[1]_0\,
      I2 => \^rd_victim_sel_reg[0]_0\,
      I3 => \^rd_victim_sel_reg[2]_0\,
      I4 => \^num_samples_done_r\,
      I5 => \rd_victim_sel_reg[2]_1\,
      O => \rd_victim_sel[0]_i_1_n_0\
    );
\rd_victim_sel[1]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"000000000000DC9C"
    )
        port map (
      I0 => \^samples_cnt_r_reg[11]_0\,
      I1 => \^rd_victim_sel_reg[1]_0\,
      I2 => \^rd_victim_sel_reg[0]_0\,
      I3 => \^rd_victim_sel_reg[2]_0\,
      I4 => \^num_samples_done_r\,
      I5 => \rd_victim_sel_reg[2]_1\,
      O => \rd_victim_sel[1]_i_1_n_0\
    );
\rd_victim_sel[2]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"000000000000FF40"
    )
        port map (
      I0 => \^samples_cnt_r_reg[11]_0\,
      I1 => \^rd_victim_sel_reg[1]_0\,
      I2 => \^rd_victim_sel_reg[0]_0\,
      I3 => \^rd_victim_sel_reg[2]_0\,
      I4 => \^num_samples_done_r\,
      I5 => \rd_victim_sel_reg[2]_1\,
      O => \rd_victim_sel[2]_i_1_n_0\
    );
\rd_victim_sel_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => '1',
      D => \rd_victim_sel[0]_i_1_n_0\,
      Q => \^rd_victim_sel_reg[0]_0\,
      R => '0'
    );
\rd_victim_sel_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => '1',
      D => \rd_victim_sel[1]_i_1_n_0\,
      Q => \^rd_victim_sel_reg[1]_0\,
      R => '0'
    );
\rd_victim_sel_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => '1',
      D => \rd_victim_sel[2]_i_1_n_0\,
      Q => \^rd_victim_sel_reg[2]_0\,
      R => '0'
    );
\rdlvl_cpt_tap_cnt[0]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4540"
    )
        port map (
      I0 => \rdlvl_cpt_tap_cnt_reg[5]_0\,
      I1 => \rdlvl_cpt_tap_cnt_reg[5]_1\(0),
      I2 => \rdlvl_cpt_tap_cnt_reg[5]_2\,
      I3 => \rdlvl_cpt_tap_cnt_reg[5]_3\(0),
      O => \^d\(0)
    );
\rdlvl_cpt_tap_cnt[1]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4540"
    )
        port map (
      I0 => \rdlvl_cpt_tap_cnt_reg[5]_0\,
      I1 => \rdlvl_cpt_tap_cnt_reg[5]_1\(1),
      I2 => \rdlvl_cpt_tap_cnt_reg[5]_2\,
      I3 => \rdlvl_cpt_tap_cnt_reg[5]_3\(1),
      O => \^d\(1)
    );
\rdlvl_cpt_tap_cnt[2]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4540"
    )
        port map (
      I0 => \rdlvl_cpt_tap_cnt_reg[5]_0\,
      I1 => \rdlvl_cpt_tap_cnt_reg[5]_1\(2),
      I2 => \rdlvl_cpt_tap_cnt_reg[5]_2\,
      I3 => \rdlvl_cpt_tap_cnt_reg[5]_3\(2),
      O => \^d\(2)
    );
\rdlvl_cpt_tap_cnt[3]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4540"
    )
        port map (
      I0 => \rdlvl_cpt_tap_cnt_reg[5]_0\,
      I1 => \rdlvl_cpt_tap_cnt_reg[5]_1\(3),
      I2 => \rdlvl_cpt_tap_cnt_reg[5]_2\,
      I3 => \rdlvl_cpt_tap_cnt_reg[5]_3\(3),
      O => \^d\(3)
    );
\rdlvl_cpt_tap_cnt[4]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4540"
    )
        port map (
      I0 => \rdlvl_cpt_tap_cnt_reg[5]_0\,
      I1 => \rdlvl_cpt_tap_cnt_reg[5]_1\(4),
      I2 => \rdlvl_cpt_tap_cnt_reg[5]_2\,
      I3 => \rdlvl_cpt_tap_cnt_reg[5]_3\(4),
      O => \^d\(4)
    );
\rdlvl_cpt_tap_cnt[5]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4540"
    )
        port map (
      I0 => \rdlvl_cpt_tap_cnt_reg[5]_0\,
      I1 => \rdlvl_cpt_tap_cnt_reg[5]_1\(5),
      I2 => \rdlvl_cpt_tap_cnt_reg[5]_2\,
      I3 => \rdlvl_cpt_tap_cnt_reg[5]_3\(5),
      O => \^d\(5)
    );
\rdlvl_cpt_tap_cnt_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => \^new_cnt_dqs_r_reg_0\,
      D => \^d\(0),
      Q => rdlvl_cpt_tap_cnt(0),
      R => \prbs_dec_tap_cnt_reg[0]_0\(0)
    );
\rdlvl_cpt_tap_cnt_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => \^new_cnt_dqs_r_reg_0\,
      D => \^d\(1),
      Q => rdlvl_cpt_tap_cnt(1),
      R => \prbs_dec_tap_cnt_reg[0]_0\(0)
    );
\rdlvl_cpt_tap_cnt_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => \^new_cnt_dqs_r_reg_0\,
      D => \^d\(2),
      Q => rdlvl_cpt_tap_cnt(2),
      R => \prbs_dec_tap_cnt_reg[0]_0\(0)
    );
\rdlvl_cpt_tap_cnt_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => \^new_cnt_dqs_r_reg_0\,
      D => \^d\(3),
      Q => rdlvl_cpt_tap_cnt(3),
      R => \prbs_dec_tap_cnt_reg[0]_0\(0)
    );
\rdlvl_cpt_tap_cnt_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => \^new_cnt_dqs_r_reg_0\,
      D => \^d\(4),
      Q => rdlvl_cpt_tap_cnt(4),
      R => \prbs_dec_tap_cnt_reg[0]_0\(0)
    );
\rdlvl_cpt_tap_cnt_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => \^new_cnt_dqs_r_reg_0\,
      D => \^d\(5),
      Q => rdlvl_cpt_tap_cnt(5),
      R => \prbs_dec_tap_cnt_reg[0]_0\(0)
    );
reset_if_i_1: unisim.vcomponents.LUT3
    generic map(
      INIT => X"02"
    )
        port map (
      I0 => reset_if_i_2_n_0,
      I1 => reset_if_r9,
      I2 => reset_if_reg,
      O => reset_if_r9_reg
    );
reset_if_i_2: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFF22F2"
    )
        port map (
      I0 => \^prbs_rdlvl_done_reg_0\,
      I1 => prbs_rdlvl_done_r1,
      I2 => \gen_byte_sel_div2.byte_sel_cnt_reg[0]\,
      I3 => rdlvl_stg1_done_r1,
      I4 => reset_if,
      O => reset_if_i_2_n_0
    );
reset_rd_addr_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFDFEFF00010000"
    )
        port map (
      I0 => prbs_state_r(1),
      I1 => prbs_state_r(4),
      I2 => prbs_state_r(2),
      I3 => prbs_state_r(0),
      I4 => prbs_state_r(3),
      I5 => \^reset_rd_addr\,
      O => reset_rd_addr_i_1_n_0
    );
reset_rd_addr_r1_i_1: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => \^reset_rd_addr\,
      I1 => complex_ocal_reset_rd_addr,
      O => reset_rd_addr0
    );
reset_rd_addr_reg: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => '1',
      D => reset_rd_addr_i_1_n_0,
      Q => \^reset_rd_addr\,
      R => \match_flag_and_reg[7]_0\
    );
right_edge_found_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"10FFFFFF10000000"
    )
        port map (
      I0 => prbs_state_r(4),
      I1 => no_err_win_detected_reg_n_0,
      I2 => right_edge_found_i_2_n_0,
      I3 => right_edge_found_i_3_n_0,
      I4 => right_edge_found_i_4_n_0,
      I5 => right_edge_found_reg_n_0,
      O => right_edge_found_i_1_n_0
    );
right_edge_found_i_2: unisim.vcomponents.LUT6
    generic map(
      INIT => X"5555555555555551"
    )
        port map (
      I0 => right_edge_found_reg_n_0,
      I1 => right_edge_found_i_5_n_0,
      I2 => \genblk8[7].right_edge_found_pb_reg_n_0_[7]\,
      I3 => \genblk8[6].right_edge_found_pb_reg_n_0_[6]\,
      I4 => \genblk8[5].right_edge_found_pb_reg_n_0_[5]\,
      I5 => \genblk8[4].right_edge_found_pb_reg_n_0_[4]\,
      O => right_edge_found_i_2_n_0
    );
right_edge_found_i_3: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8100"
    )
        port map (
      I0 => prbs_state_r(2),
      I1 => prbs_state_r(3),
      I2 => prbs_state_r(0),
      I3 => prbs_state_r(1),
      O => right_edge_found_i_3_n_0
    );
right_edge_found_i_4: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000EEEEFFF00000"
    )
        port map (
      I0 => num_samples_done_ind_reg_n_0,
      I1 => \^num_samples_done_r\,
      I2 => no_err_win_detected_reg_n_0,
      I3 => right_edge_found_i_2_n_0,
      I4 => prbs_state_r(3),
      I5 => prbs_state_r(4),
      O => right_edge_found_i_4_n_0
    );
right_edge_found_i_5: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0001"
    )
        port map (
      I0 => \genblk8[1].right_edge_found_pb_reg_n_0_[1]\,
      I1 => \genblk8[0].right_edge_found_pb_reg_n_0_[0]\,
      I2 => \genblk8[3].right_edge_found_pb_reg_n_0_[3]\,
      I3 => \genblk8[2].right_edge_found_pb_reg_n_0_[2]\,
      O => right_edge_found_i_5_n_0
    );
right_edge_found_reg: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => '1',
      D => right_edge_found_i_1_n_0,
      Q => right_edge_found_reg_n_0,
      R => \samples_cnt_r_reg[0]_0\
    );
\samples_cnt_r[0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000FFFFFFFE"
    )
        port map (
      I0 => \samples_cnt_r_reg_n_0_[11]\,
      I1 => \samples_cnt_r_reg_n_0_[10]\,
      I2 => \samples_cnt_r_reg_n_0_[1]\,
      I3 => \samples_cnt_r[0]_i_2_n_0\,
      I4 => \samples_cnt_r[0]_i_3_n_0\,
      I5 => \samples_cnt_r_reg_n_0_[0]\,
      O => \samples_cnt_r[0]_i_1_n_0\
    );
\samples_cnt_r[0]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFFE"
    )
        port map (
      I0 => \samples_cnt_r_reg_n_0_[7]\,
      I1 => \samples_cnt_r_reg_n_0_[6]\,
      I2 => \samples_cnt_r_reg_n_0_[9]\,
      I3 => \samples_cnt_r_reg_n_0_[8]\,
      O => \samples_cnt_r[0]_i_2_n_0\
    );
\samples_cnt_r[0]_i_3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFF7"
    )
        port map (
      I0 => \samples_cnt_r_reg_n_0_[3]\,
      I1 => \samples_cnt_r_reg_n_0_[2]\,
      I2 => \samples_cnt_r_reg_n_0_[5]\,
      I3 => \samples_cnt_r_reg_n_0_[4]\,
      O => \samples_cnt_r[0]_i_3_n_0\
    );
\samples_cnt_r[10]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^samples_cnt_r_reg[11]_0\,
      I1 => data0(10),
      O => \samples_cnt_r[10]_i_1_n_0\
    );
\samples_cnt_r[11]_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^samples_cnt_r_reg[11]_0\,
      I1 => data0(11),
      O => \samples_cnt_r[11]_i_2_n_0\
    );
\samples_cnt_r[11]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFFFE"
    )
        port map (
      I0 => \samples_cnt_r_reg_n_0_[11]\,
      I1 => \samples_cnt_r_reg_n_0_[10]\,
      I2 => \samples_cnt_r_reg_n_0_[1]\,
      I3 => \samples_cnt_r[0]_i_2_n_0\,
      I4 => \samples_cnt_r[0]_i_3_n_0\,
      I5 => \samples_cnt_r_reg_n_0_[0]\,
      O => \^samples_cnt_r_reg[11]_0\
    );
\samples_cnt_r[1]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^samples_cnt_r_reg[11]_0\,
      I1 => data0(1),
      O => \samples_cnt_r[1]_i_1_n_0\
    );
\samples_cnt_r[2]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^samples_cnt_r_reg[11]_0\,
      I1 => data0(2),
      O => \samples_cnt_r[2]_i_1_n_0\
    );
\samples_cnt_r[3]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^samples_cnt_r_reg[11]_0\,
      I1 => data0(3),
      O => \samples_cnt_r[3]_i_1_n_0\
    );
\samples_cnt_r[4]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^samples_cnt_r_reg[11]_0\,
      I1 => data0(4),
      O => \samples_cnt_r[4]_i_1_n_0\
    );
\samples_cnt_r[5]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^samples_cnt_r_reg[11]_0\,
      I1 => data0(5),
      O => \samples_cnt_r[5]_i_1_n_0\
    );
\samples_cnt_r[6]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^samples_cnt_r_reg[11]_0\,
      I1 => data0(6),
      O => \samples_cnt_r[6]_i_1_n_0\
    );
\samples_cnt_r[7]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^samples_cnt_r_reg[11]_0\,
      I1 => data0(7),
      O => \samples_cnt_r[7]_i_1_n_0\
    );
\samples_cnt_r[8]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^samples_cnt_r_reg[11]_0\,
      I1 => data0(8),
      O => \samples_cnt_r[8]_i_1_n_0\
    );
\samples_cnt_r[9]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^samples_cnt_r_reg[11]_0\,
      I1 => data0(9),
      O => \samples_cnt_r[9]_i_1_n_0\
    );
\samples_cnt_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => E(0),
      D => \samples_cnt_r[0]_i_1_n_0\,
      Q => \samples_cnt_r_reg_n_0_[0]\,
      R => \samples_cnt_r_reg[0]_0\
    );
\samples_cnt_r_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => E(0),
      D => \samples_cnt_r[10]_i_1_n_0\,
      Q => \samples_cnt_r_reg_n_0_[10]\,
      R => \samples_cnt_r_reg[0]_0\
    );
\samples_cnt_r_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => E(0),
      D => \samples_cnt_r[11]_i_2_n_0\,
      Q => \samples_cnt_r_reg_n_0_[11]\,
      R => \samples_cnt_r_reg[0]_0\
    );
\samples_cnt_r_reg[11]_i_4\: unisim.vcomponents.CARRY4
     port map (
      CI => \samples_cnt_r_reg[8]_i_2_n_0\,
      CO(3 downto 2) => \NLW_samples_cnt_r_reg[11]_i_4_CO_UNCONNECTED\(3 downto 2),
      CO(1) => \samples_cnt_r_reg[11]_i_4_n_2\,
      CO(0) => \samples_cnt_r_reg[11]_i_4_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3) => \NLW_samples_cnt_r_reg[11]_i_4_O_UNCONNECTED\(3),
      O(2 downto 0) => data0(11 downto 9),
      S(3) => '0',
      S(2) => \samples_cnt_r_reg_n_0_[11]\,
      S(1) => \samples_cnt_r_reg_n_0_[10]\,
      S(0) => \samples_cnt_r_reg_n_0_[9]\
    );
\samples_cnt_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => E(0),
      D => \samples_cnt_r[1]_i_1_n_0\,
      Q => \samples_cnt_r_reg_n_0_[1]\,
      R => \samples_cnt_r_reg[0]_0\
    );
\samples_cnt_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => E(0),
      D => \samples_cnt_r[2]_i_1_n_0\,
      Q => \samples_cnt_r_reg_n_0_[2]\,
      R => \samples_cnt_r_reg[0]_0\
    );
\samples_cnt_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => E(0),
      D => \samples_cnt_r[3]_i_1_n_0\,
      Q => \samples_cnt_r_reg_n_0_[3]\,
      R => \samples_cnt_r_reg[0]_0\
    );
\samples_cnt_r_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => E(0),
      D => \samples_cnt_r[4]_i_1_n_0\,
      Q => \samples_cnt_r_reg_n_0_[4]\,
      R => \samples_cnt_r_reg[0]_0\
    );
\samples_cnt_r_reg[4]_i_2\: unisim.vcomponents.CARRY4
     port map (
      CI => '0',
      CO(3) => \samples_cnt_r_reg[4]_i_2_n_0\,
      CO(2) => \samples_cnt_r_reg[4]_i_2_n_1\,
      CO(1) => \samples_cnt_r_reg[4]_i_2_n_2\,
      CO(0) => \samples_cnt_r_reg[4]_i_2_n_3\,
      CYINIT => \samples_cnt_r_reg_n_0_[0]\,
      DI(3 downto 0) => B"0000",
      O(3 downto 0) => data0(4 downto 1),
      S(3) => \samples_cnt_r_reg_n_0_[4]\,
      S(2) => \samples_cnt_r_reg_n_0_[3]\,
      S(1) => \samples_cnt_r_reg_n_0_[2]\,
      S(0) => \samples_cnt_r_reg_n_0_[1]\
    );
\samples_cnt_r_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => E(0),
      D => \samples_cnt_r[5]_i_1_n_0\,
      Q => \samples_cnt_r_reg_n_0_[5]\,
      R => \samples_cnt_r_reg[0]_0\
    );
\samples_cnt_r_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => E(0),
      D => \samples_cnt_r[6]_i_1_n_0\,
      Q => \samples_cnt_r_reg_n_0_[6]\,
      R => \samples_cnt_r_reg[0]_0\
    );
\samples_cnt_r_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => E(0),
      D => \samples_cnt_r[7]_i_1_n_0\,
      Q => \samples_cnt_r_reg_n_0_[7]\,
      R => \samples_cnt_r_reg[0]_0\
    );
\samples_cnt_r_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => E(0),
      D => \samples_cnt_r[8]_i_1_n_0\,
      Q => \samples_cnt_r_reg_n_0_[8]\,
      R => \samples_cnt_r_reg[0]_0\
    );
\samples_cnt_r_reg[8]_i_2\: unisim.vcomponents.CARRY4
     port map (
      CI => \samples_cnt_r_reg[4]_i_2_n_0\,
      CO(3) => \samples_cnt_r_reg[8]_i_2_n_0\,
      CO(2) => \samples_cnt_r_reg[8]_i_2_n_1\,
      CO(1) => \samples_cnt_r_reg[8]_i_2_n_2\,
      CO(0) => \samples_cnt_r_reg[8]_i_2_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3 downto 0) => data0(8 downto 5),
      S(3) => \samples_cnt_r_reg_n_0_[8]\,
      S(2) => \samples_cnt_r_reg_n_0_[7]\,
      S(1) => \samples_cnt_r_reg_n_0_[6]\,
      S(0) => \samples_cnt_r_reg_n_0_[5]\
    );
\samples_cnt_r_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => E(0),
      D => \samples_cnt_r[9]_i_1_n_0\,
      Q => \samples_cnt_r_reg_n_0_[9]\,
      R => \samples_cnt_r_reg[0]_0\
    );
\smallest_right_edge[0]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"7"
    )
        port map (
      I0 => prbs_state_r(0),
      I1 => \prbs_dqs_tap_cnt_r_reg_n_0_[0]\,
      O => \smallest_right_edge[0]_i_1_n_0\
    );
\smallest_right_edge[1]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"D7"
    )
        port map (
      I0 => prbs_state_r(0),
      I1 => \prbs_dqs_tap_cnt_r_reg_n_0_[1]\,
      I2 => \prbs_dqs_tap_cnt_r_reg_n_0_[0]\,
      O => \smallest_right_edge[1]_i_1_n_0\
    );
\smallest_right_edge[2]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FD57"
    )
        port map (
      I0 => prbs_state_r(0),
      I1 => \prbs_dqs_tap_cnt_r_reg_n_0_[0]\,
      I2 => \prbs_dqs_tap_cnt_r_reg_n_0_[1]\,
      I3 => \prbs_dqs_tap_cnt_r_reg_n_0_[2]\,
      O => \smallest_right_edge[2]_i_1_n_0\
    );
\smallest_right_edge[3]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFD5557"
    )
        port map (
      I0 => prbs_state_r(0),
      I1 => \prbs_dqs_tap_cnt_r_reg_n_0_[2]\,
      I2 => \prbs_dqs_tap_cnt_r_reg_n_0_[1]\,
      I3 => \prbs_dqs_tap_cnt_r_reg_n_0_[0]\,
      I4 => \prbs_dqs_tap_cnt_r_reg_n_0_[3]\,
      O => \smallest_right_edge[3]_i_1_n_0\
    );
\smallest_right_edge[4]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFD55555557"
    )
        port map (
      I0 => prbs_state_r(0),
      I1 => \prbs_dqs_tap_cnt_r_reg_n_0_[3]\,
      I2 => \prbs_dqs_tap_cnt_r_reg_n_0_[0]\,
      I3 => \prbs_dqs_tap_cnt_r_reg_n_0_[1]\,
      I4 => \prbs_dqs_tap_cnt_r_reg_n_0_[2]\,
      I5 => \prbs_dqs_tap_cnt_r_reg_n_0_[4]\,
      O => \smallest_right_edge[4]_i_1_n_0\
    );
\smallest_right_edge[5]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFF0020200000"
    )
        port map (
      I0 => \smallest_right_edge[5]_i_3_n_0\,
      I1 => right_edge_found_reg_n_0,
      I2 => \^num_samples_done_r\,
      I3 => \smallest_right_edge[5]_i_4_n_0\,
      I4 => \smallest_right_edge[5]_i_5_n_0\,
      I5 => \smallest_right_edge[5]_i_6_n_0\,
      O => smallest_right_edge
    );
\smallest_right_edge[5]_i_10\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8000"
    )
        port map (
      I0 => \genblk8[1].right_edge_found_pb_reg_n_0_[1]\,
      I1 => \genblk8[0].right_edge_found_pb_reg_n_0_[0]\,
      I2 => \genblk8[3].right_edge_found_pb_reg_n_0_[3]\,
      I3 => \genblk8[2].right_edge_found_pb_reg_n_0_[2]\,
      O => \smallest_right_edge[5]_i_10_n_0\
    );
\smallest_right_edge[5]_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"7"
    )
        port map (
      I0 => prbs_state_r(0),
      I1 => \prbs_dqs_tap_cnt_r[5]_i_4_n_0\,
      O => \smallest_right_edge[5]_i_2_n_0\
    );
\smallest_right_edge[5]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAAAAAAAAAEA"
    )
        port map (
      I0 => \smallest_right_edge[5]_i_7_n_0\,
      I1 => \smallest_right_edge[5]_i_8_n_0\,
      I2 => \smallest_right_edge[5]_i_9_n_0\,
      I3 => \match_flag_and_reg_n_0_[0]\,
      I4 => \match_flag_and_reg_n_0_[1]\,
      I5 => \match_flag_and_reg_n_0_[2]\,
      O => \smallest_right_edge[5]_i_3_n_0\
    );
\smallest_right_edge[5]_i_4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => right_edge_found_i_2_n_0,
      I1 => no_err_win_detected_reg_n_0,
      O => \smallest_right_edge[5]_i_4_n_0\
    );
\smallest_right_edge[5]_i_5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00011000"
    )
        port map (
      I0 => prbs_state_r(1),
      I1 => prbs_state_r(2),
      I2 => prbs_state_r(0),
      I3 => prbs_state_r(4),
      I4 => prbs_state_r(3),
      O => \smallest_right_edge[5]_i_5_n_0\
    );
\smallest_right_edge[5]_i_6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"40000004"
    )
        port map (
      I0 => prbs_state_r(4),
      I1 => prbs_state_r(3),
      I2 => prbs_state_r(2),
      I3 => prbs_state_r(1),
      I4 => prbs_state_r(0),
      O => \smallest_right_edge[5]_i_6_n_0\
    );
\smallest_right_edge[5]_i_7\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFF80000000"
    )
        port map (
      I0 => \smallest_right_edge[5]_i_10_n_0\,
      I1 => \genblk8[7].right_edge_found_pb_reg_n_0_[7]\,
      I2 => \genblk8[6].right_edge_found_pb_reg_n_0_[6]\,
      I3 => \genblk8[5].right_edge_found_pb_reg_n_0_[5]\,
      I4 => \genblk8[4].right_edge_found_pb_reg_n_0_[4]\,
      I5 => prbs_dqs_tap_limit_r,
      O => \smallest_right_edge[5]_i_7_n_0\
    );
\smallest_right_edge[5]_i_8\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FEFEFEFEFEFEFEEE"
    )
        port map (
      I0 => \prbs_dqs_tap_cnt_r_reg_n_0_[5]\,
      I1 => \prbs_dqs_tap_cnt_r_reg_n_0_[4]\,
      I2 => \prbs_dqs_tap_cnt_r_reg_n_0_[3]\,
      I3 => \prbs_dqs_tap_cnt_r_reg_n_0_[2]\,
      I4 => \prbs_dqs_tap_cnt_r_reg_n_0_[1]\,
      I5 => \prbs_dqs_tap_cnt_r_reg_n_0_[0]\,
      O => \smallest_right_edge[5]_i_8_n_0\
    );
\smallest_right_edge[5]_i_9\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000100000000"
    )
        port map (
      I0 => \match_flag_and_reg_n_0_[3]\,
      I1 => \match_flag_and_reg_n_0_[4]\,
      I2 => \match_flag_and_reg_n_0_[5]\,
      I3 => \match_flag_and_reg_n_0_[6]\,
      I4 => \match_flag_and_reg_n_0_[7]\,
      I5 => compare_err_pb_and_reg_n_0,
      O => \smallest_right_edge[5]_i_9_n_0\
    );
\smallest_right_edge_reg[0]\: unisim.vcomponents.FDSE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => smallest_right_edge,
      D => \smallest_right_edge[0]_i_1_n_0\,
      Q => \smallest_right_edge_reg_n_0_[0]\,
      S => \samples_cnt_r_reg[0]_0\
    );
\smallest_right_edge_reg[1]\: unisim.vcomponents.FDSE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => smallest_right_edge,
      D => \smallest_right_edge[1]_i_1_n_0\,
      Q => \smallest_right_edge_reg_n_0_[1]\,
      S => \samples_cnt_r_reg[0]_0\
    );
\smallest_right_edge_reg[2]\: unisim.vcomponents.FDSE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => smallest_right_edge,
      D => \smallest_right_edge[2]_i_1_n_0\,
      Q => \smallest_right_edge_reg_n_0_[2]\,
      S => \samples_cnt_r_reg[0]_0\
    );
\smallest_right_edge_reg[3]\: unisim.vcomponents.FDSE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => smallest_right_edge,
      D => \smallest_right_edge[3]_i_1_n_0\,
      Q => \smallest_right_edge_reg_n_0_[3]\,
      S => \samples_cnt_r_reg[0]_0\
    );
\smallest_right_edge_reg[4]\: unisim.vcomponents.FDSE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => smallest_right_edge,
      D => \smallest_right_edge[4]_i_1_n_0\,
      Q => \smallest_right_edge_reg_n_0_[4]\,
      S => \samples_cnt_r_reg[0]_0\
    );
\smallest_right_edge_reg[5]\: unisim.vcomponents.FDSE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => smallest_right_edge,
      D => \smallest_right_edge[5]_i_2_n_0\,
      Q => \smallest_right_edge_reg_n_0_[5]\,
      S => \samples_cnt_r_reg[0]_0\
    );
\stage_cnt[0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"DFFFFCFF20000000"
    )
        port map (
      I0 => \stage_cnt[0]_i_2_n_0\,
      I1 => \prbs_state_r[4]_i_5_n_0\,
      I2 => prbs_state_r(4),
      I3 => prbs_state_r(0),
      I4 => prbs_state_r(1),
      I5 => \stage_cnt_reg_n_0_[0]\,
      O => \stage_cnt[0]_i_1_n_0\
    );
\stage_cnt[0]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000000010"
    )
        port map (
      I0 => \p_0_in__0\(6),
      I1 => \p_0_in__0\(7),
      I2 => \bit_cnt_reg_n_0_[3]\,
      I3 => \bit_cnt_reg_n_0_[2]\,
      I4 => \bit_cnt_reg_n_0_[0]\,
      I5 => \bit_cnt_reg_n_0_[1]\,
      O => \stage_cnt[0]_i_2_n_0\
    );
\stage_cnt[1]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F80"
    )
        port map (
      I0 => prbs_state_r(4),
      I1 => \stage_cnt_reg_n_0_[0]\,
      I2 => \stage_cnt[1]_i_2_n_0\,
      I3 => \stage_cnt_reg_n_0_[1]\,
      O => \stage_cnt[1]_i_1_n_0\
    );
\stage_cnt[1]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0200000000030000"
    )
        port map (
      I0 => \stage_cnt[0]_i_2_n_0\,
      I1 => prbs_state_r(2),
      I2 => prbs_state_r(3),
      I3 => prbs_state_r(4),
      I4 => prbs_state_r(0),
      I5 => prbs_state_r(1),
      O => \stage_cnt[1]_i_2_n_0\
    );
\stage_cnt_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => '1',
      D => \stage_cnt[0]_i_1_n_0\,
      Q => \stage_cnt_reg_n_0_[0]\,
      R => \samples_cnt_r_reg[0]_0\
    );
\stage_cnt_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => '1',
      D => \stage_cnt[1]_i_1_n_0\,
      Q => \stage_cnt_reg_n_0_[1]\,
      R => \samples_cnt_r_reg[0]_0\
    );
\victim_not_fixed.num_samples_done_r_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8AAA8AAAAA8A8AAA"
    )
        port map (
      I0 => \victim_not_fixed.num_samples_done_r_i_2_n_0\,
      I1 => prbs_state_r(4),
      I2 => prbs_state_r(0),
      I3 => prbs_state_r(2),
      I4 => prbs_state_r(1),
      I5 => prbs_state_r(3),
      O => \victim_not_fixed.num_samples_done_r_i_1_n_0\
    );
\victim_not_fixed.num_samples_done_r_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000AAAAEAAA"
    )
        port map (
      I0 => \^num_samples_done_r\,
      I1 => \^rd_victim_sel_reg[2]_0\,
      I2 => \^rd_victim_sel_reg[0]_0\,
      I3 => \^rd_victim_sel_reg[1]_0\,
      I4 => \^samples_cnt_r_reg[11]_0\,
      I5 => \rd_victim_sel_reg[2]_1\,
      O => \victim_not_fixed.num_samples_done_r_i_2_n_0\
    );
\victim_not_fixed.num_samples_done_r_reg\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => '1',
      D => \victim_not_fixed.num_samples_done_r_i_1_n_0\,
      Q => \^num_samples_done_r\,
      R => '0'
    );
wait_state_cnt_en_r_i_1: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0101081C"
    )
        port map (
      I0 => prbs_state_r(1),
      I1 => prbs_state_r(2),
      I2 => prbs_state_r(4),
      I3 => prbs_state_r(3),
      I4 => prbs_state_r(0),
      O => wait_state_cnt_en_r0
    );
wait_state_cnt_en_r_reg: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => '1',
      D => wait_state_cnt_en_r0,
      Q => wait_state_cnt_en_r,
      R => '0'
    );
\wait_state_cnt_r[0]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => wait_state_cnt_r_reg(0),
      O => p_0_in(0)
    );
\wait_state_cnt_r[1]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => wait_state_cnt_r_reg(0),
      I1 => wait_state_cnt_r_reg(1),
      O => p_0_in(1)
    );
\wait_state_cnt_r[2]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"6A"
    )
        port map (
      I0 => wait_state_cnt_r_reg(2),
      I1 => wait_state_cnt_r_reg(1),
      I2 => wait_state_cnt_r_reg(0),
      O => p_0_in(2)
    );
\wait_state_cnt_r[3]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"8000FFFF"
    )
        port map (
      I0 => wait_state_cnt_r_reg(3),
      I1 => wait_state_cnt_r_reg(2),
      I2 => wait_state_cnt_r_reg(1),
      I3 => wait_state_cnt_r_reg(0),
      I4 => wait_state_cnt_en_r,
      O => \wait_state_cnt_r[3]_i_1_n_0\
    );
\wait_state_cnt_r[3]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6AAA"
    )
        port map (
      I0 => wait_state_cnt_r_reg(3),
      I1 => wait_state_cnt_r_reg(0),
      I2 => wait_state_cnt_r_reg(1),
      I3 => wait_state_cnt_r_reg(2),
      O => p_0_in(3)
    );
\wait_state_cnt_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => '1',
      D => p_0_in(0),
      Q => wait_state_cnt_r_reg(0),
      R => \wait_state_cnt_r[3]_i_1_n_0\
    );
\wait_state_cnt_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => '1',
      D => p_0_in(1),
      Q => wait_state_cnt_r_reg(1),
      R => \wait_state_cnt_r[3]_i_1_n_0\
    );
\wait_state_cnt_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => '1',
      D => p_0_in(2),
      Q => wait_state_cnt_r_reg(2),
      R => \wait_state_cnt_r[3]_i_1_n_0\
    );
\wait_state_cnt_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => \bit_cnt_reg[7]_0\,
      CE => '1',
      D => p_0_in(3),
      Q => wait_state_cnt_r_reg(3),
      R => \wait_state_cnt_r[3]_i_1_n_0\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mig_mig_7series_v4_2_ddr_phy_rdlvl is
  port (
    new_cnt_cpt_r_reg_0 : out STD_LOGIC;
    samp_edge_cnt0_en_r : out STD_LOGIC;
    idelay_ce_int : out STD_LOGIC;
    idelay_inc_int : out STD_LOGIC;
    rdlvl_prech_req : out STD_LOGIC;
    pi_fine_dly_dec_done : out STD_LOGIC;
    rdlvl_pi_stg2_f_en : out STD_LOGIC;
    rdlvl_pi_stg2_f_incdec : out STD_LOGIC;
    pi_stg2_load_reg_0 : out STD_LOGIC;
    pi_cnt_dec_reg_0 : out STD_LOGIC;
    rdlvl_stg1_done_int_reg_0 : out STD_LOGIC;
    rdlvl_stg1_rank_done : out STD_LOGIC;
    rdlvl_last_byte_done : out STD_LOGIC;
    rdlvl_pi_incdec : out STD_LOGIC;
    \rnk_cnt_r_reg[1]_0\ : out STD_LOGIC;
    \cal1_cnt_cpt_r_reg[2]_0\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_0\ : out STD_LOGIC;
    Q : out STD_LOGIC_VECTOR ( 1 downto 0 );
    rdlvl_stg1_done_int_reg_1 : out STD_LOGIC;
    rdlvl_stg1_done_int_reg_2 : out STD_LOGIC_VECTOR ( 0 to 0 );
    p_1_in : out STD_LOGIC;
    \cal1_cnt_cpt_r_reg[2]_1\ : out STD_LOGIC;
    \cal1_cnt_cpt_r_reg[0]_0\ : out STD_LOGIC;
    \cal1_cnt_cpt_r_reg[0]_1\ : out STD_LOGIC;
    cal1_dq_idel_ce_reg_0 : out STD_LOGIC;
    \rnk_cnt_r_reg[0]_0\ : out STD_LOGIC;
    cal1_dq_idel_ce_reg_1 : out STD_LOGIC;
    cal1_dq_idel_ce_reg_2 : out STD_LOGIC;
    prech_req : out STD_LOGIC;
    rdlvl_stg1_done_r1_reg : out STD_LOGIC;
    rdlvl_stg1_done_int_reg_3 : out STD_LOGIC_VECTOR ( 3 downto 0 );
    \pi_stg2_reg_l_reg[5]_0\ : out STD_LOGIC_VECTOR ( 5 downto 0 );
    \rdlvl_dqs_tap_cnt_r_reg[0][0][2]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    rdlvl_pi_incdec_reg_0 : in STD_LOGIC;
    \gen_mux_rd[0].mux_rd_rise0_r_reg[0]_0\ : in STD_LOGIC;
    \gen_mux_rd[1].mux_rd_rise0_r_reg[1]_0\ : in STD_LOGIC;
    \gen_mux_rd[2].mux_rd_rise0_r_reg[2]_0\ : in STD_LOGIC;
    \gen_mux_rd[3].mux_rd_rise0_r_reg[3]_0\ : in STD_LOGIC;
    \gen_mux_rd[4].mux_rd_rise0_r_reg[4]_0\ : in STD_LOGIC;
    \gen_mux_rd[5].mux_rd_rise0_r_reg[5]_0\ : in STD_LOGIC;
    \gen_mux_rd[6].mux_rd_rise0_r_reg[6]_0\ : in STD_LOGIC;
    \gen_mux_rd[7].mux_rd_rise0_r_reg[7]_0\ : in STD_LOGIC;
    \gen_mux_rd[0].mux_rd_fall0_r_reg[0]_0\ : in STD_LOGIC;
    \gen_mux_rd[1].mux_rd_fall0_r_reg[1]_0\ : in STD_LOGIC;
    \gen_mux_rd[2].mux_rd_fall0_r_reg[2]_0\ : in STD_LOGIC;
    \gen_mux_rd[3].mux_rd_fall0_r_reg[3]_0\ : in STD_LOGIC;
    \gen_mux_rd[4].mux_rd_fall0_r_reg[4]_0\ : in STD_LOGIC;
    \gen_mux_rd[5].mux_rd_fall0_r_reg[5]_0\ : in STD_LOGIC;
    \gen_mux_rd[6].mux_rd_fall0_r_reg[6]_0\ : in STD_LOGIC;
    \gen_mux_rd[7].mux_rd_fall0_r_reg[7]_0\ : in STD_LOGIC;
    \gen_mux_rd[0].mux_rd_rise1_r_reg[0]_0\ : in STD_LOGIC;
    \gen_mux_rd[1].mux_rd_rise1_r_reg[1]_0\ : in STD_LOGIC;
    \gen_mux_rd[2].mux_rd_rise1_r_reg[2]_0\ : in STD_LOGIC;
    \gen_mux_rd[3].mux_rd_rise1_r_reg[3]_0\ : in STD_LOGIC;
    \gen_mux_rd[4].mux_rd_rise1_r_reg[4]_0\ : in STD_LOGIC;
    \gen_mux_rd[5].mux_rd_rise1_r_reg[5]_0\ : in STD_LOGIC;
    \gen_mux_rd[6].mux_rd_rise1_r_reg[6]_0\ : in STD_LOGIC;
    \gen_mux_rd[7].mux_rd_rise1_r_reg[7]_0\ : in STD_LOGIC;
    \gen_mux_rd[0].mux_rd_fall1_r_reg[0]_0\ : in STD_LOGIC;
    \gen_mux_rd[1].mux_rd_fall1_r_reg[1]_0\ : in STD_LOGIC;
    \gen_mux_rd[2].mux_rd_fall1_r_reg[2]_0\ : in STD_LOGIC;
    \gen_mux_rd[3].mux_rd_fall1_r_reg[3]_0\ : in STD_LOGIC;
    \gen_mux_rd[4].mux_rd_fall1_r_reg[4]_0\ : in STD_LOGIC;
    \gen_mux_rd[5].mux_rd_fall1_r_reg[5]_0\ : in STD_LOGIC;
    \gen_mux_rd[6].mux_rd_fall1_r_reg[6]_0\ : in STD_LOGIC;
    \gen_mux_rd[7].mux_rd_fall1_r_reg[7]_0\ : in STD_LOGIC;
    \gen_mux_rd[0].mux_rd_rise2_r_reg[0]_0\ : in STD_LOGIC;
    \gen_mux_rd[1].mux_rd_rise2_r_reg[1]_0\ : in STD_LOGIC;
    \gen_mux_rd[2].mux_rd_rise2_r_reg[2]_0\ : in STD_LOGIC;
    \gen_mux_rd[3].mux_rd_rise2_r_reg[3]_0\ : in STD_LOGIC;
    \gen_mux_rd[4].mux_rd_rise2_r_reg[4]_0\ : in STD_LOGIC;
    \gen_mux_rd[5].mux_rd_rise2_r_reg[5]_0\ : in STD_LOGIC;
    \gen_mux_rd[6].mux_rd_rise2_r_reg[6]_0\ : in STD_LOGIC;
    \gen_mux_rd[7].mux_rd_rise2_r_reg[7]_0\ : in STD_LOGIC;
    \gen_mux_rd[0].mux_rd_fall2_r_reg[0]_0\ : in STD_LOGIC;
    \gen_mux_rd[1].mux_rd_fall2_r_reg[1]_0\ : in STD_LOGIC;
    \gen_mux_rd[2].mux_rd_fall2_r_reg[2]_0\ : in STD_LOGIC;
    \gen_mux_rd[3].mux_rd_fall2_r_reg[3]_0\ : in STD_LOGIC;
    \gen_mux_rd[4].mux_rd_fall2_r_reg[4]_0\ : in STD_LOGIC;
    \gen_mux_rd[5].mux_rd_fall2_r_reg[5]_0\ : in STD_LOGIC;
    \gen_mux_rd[6].mux_rd_fall2_r_reg[6]_0\ : in STD_LOGIC;
    \gen_mux_rd[7].mux_rd_fall2_r_reg[7]_0\ : in STD_LOGIC;
    \gen_mux_rd[0].mux_rd_rise3_r_reg[0]_0\ : in STD_LOGIC;
    \gen_mux_rd[1].mux_rd_rise3_r_reg[1]_0\ : in STD_LOGIC;
    \gen_mux_rd[2].mux_rd_rise3_r_reg[2]_0\ : in STD_LOGIC;
    \gen_mux_rd[3].mux_rd_rise3_r_reg[3]_0\ : in STD_LOGIC;
    \gen_mux_rd[4].mux_rd_rise3_r_reg[4]_0\ : in STD_LOGIC;
    \gen_mux_rd[5].mux_rd_rise3_r_reg[5]_0\ : in STD_LOGIC;
    \gen_mux_rd[6].mux_rd_rise3_r_reg[6]_0\ : in STD_LOGIC;
    \gen_mux_rd[7].mux_rd_rise3_r_reg[7]_0\ : in STD_LOGIC;
    \gen_mux_rd[0].mux_rd_fall3_r_reg[0]_0\ : in STD_LOGIC;
    \gen_mux_rd[1].mux_rd_fall3_r_reg[1]_0\ : in STD_LOGIC;
    \gen_mux_rd[2].mux_rd_fall3_r_reg[2]_0\ : in STD_LOGIC;
    \gen_mux_rd[3].mux_rd_fall3_r_reg[3]_0\ : in STD_LOGIC;
    \gen_mux_rd[4].mux_rd_fall3_r_reg[4]_0\ : in STD_LOGIC;
    \gen_mux_rd[5].mux_rd_fall3_r_reg[5]_0\ : in STD_LOGIC;
    \gen_mux_rd[6].mux_rd_fall3_r_reg[6]_0\ : in STD_LOGIC;
    \gen_mux_rd[7].mux_rd_fall3_r_reg[7]_0\ : in STD_LOGIC;
    mpr_rdlvl_start_r_reg_0 : in STD_LOGIC;
    rdlvl_stg1_start_r_reg_0 : in STD_LOGIC;
    E : in STD_LOGIC_VECTOR ( 0 to 0 );
    dqs_po_dec_done : in STD_LOGIC;
    \samp_edge_cnt1_r_reg[0]_0\ : in STD_LOGIC;
    sr_valid_r_reg_0 : in STD_LOGIC;
    SR : in STD_LOGIC_VECTOR ( 1 downto 0 );
    found_second_edge_r_reg_0 : in STD_LOGIC;
    pi_stg2_f_incdec_timing_reg_0 : in STD_LOGIC;
    \stg1_wr_rd_cnt_reg[3]\ : in STD_LOGIC;
    stg1_wr_done : in STD_LOGIC;
    \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[56]\ : in STD_LOGIC;
    \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[56]_0\ : in STD_LOGIC;
    \done_cnt_reg[2]_0\ : in STD_LOGIC;
    prech_done : in STD_LOGIC;
    D : in STD_LOGIC_VECTOR ( 5 downto 0 );
    wrcal_prech_req : in STD_LOGIC;
    prech_req_r_reg : in STD_LOGIC;
    dqs_found_prech_req : in STD_LOGIC;
    prech_req_r_reg_0 : in STD_LOGIC;
    rdlvl_stg1_done_r1 : in STD_LOGIC;
    \init_state_r[1]_i_16\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \gen_byte_sel_div2.byte_sel_cnt_reg[3]\ : in STD_LOGIC;
    \gen_byte_sel_div2.byte_sel_cnt_reg[3]_0\ : in STD_LOGIC;
    \gen_byte_sel_div2.byte_sel_cnt_reg[3]_1\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \gen_byte_sel_div2.byte_sel_cnt_reg[2]\ : in STD_LOGIC;
    \gen_byte_sel_div2.byte_sel_cnt_reg[2]_0\ : in STD_LOGIC;
    \gen_byte_sel_div2.byte_sel_cnt_reg[1]\ : in STD_LOGIC;
    \gen_byte_sel_div2.byte_sel_cnt_reg[1]_0\ : in STD_LOGIC;
    \gen_byte_sel_div2.byte_sel_cnt_reg[0]\ : in STD_LOGIC;
    \gen_byte_sel_div2.byte_sel_cnt_reg[0]_0\ : in STD_LOGIC;
    \idelay_tap_cnt_r_reg[0][0][4]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \idelay_tap_cnt_r_reg[0][1][4]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \idelay_tap_cnt_r_reg[0][2][4]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \idelay_tap_cnt_r_reg[0][3][4]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \idelay_tap_cnt_r_reg[0][4][4]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \idelay_tap_cnt_r_reg[0][5][4]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \idelay_tap_cnt_r_reg[0][6][4]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \idelay_tap_cnt_r_reg[0][7][4]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \tap_cnt_cpt_r_reg[5]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \cnt_shift_r_reg[0]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \wait_cnt_r_reg[0]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of mig_mig_7series_v4_2_ddr_phy_rdlvl : entity is "mig_7series_v4_2_ddr_phy_rdlvl";
end mig_mig_7series_v4_2_ddr_phy_rdlvl;

architecture STRUCTURE of mig_mig_7series_v4_2_ddr_phy_rdlvl is
  signal \FSM_onehot_cal1_state_r[10]_i_1_n_0\ : STD_LOGIC;
  signal \FSM_onehot_cal1_state_r[11]_i_1_n_0\ : STD_LOGIC;
  signal \FSM_onehot_cal1_state_r[13]_i_1_n_0\ : STD_LOGIC;
  signal \FSM_onehot_cal1_state_r[14]_i_1_n_0\ : STD_LOGIC;
  signal \FSM_onehot_cal1_state_r[15]_i_1_n_0\ : STD_LOGIC;
  signal \FSM_onehot_cal1_state_r[15]_i_2_n_0\ : STD_LOGIC;
  signal \FSM_onehot_cal1_state_r[15]_i_3_n_0\ : STD_LOGIC;
  signal \FSM_onehot_cal1_state_r[16]_i_1_n_0\ : STD_LOGIC;
  signal \FSM_onehot_cal1_state_r[16]_i_2_n_0\ : STD_LOGIC;
  signal \FSM_onehot_cal1_state_r[16]_i_3_n_0\ : STD_LOGIC;
  signal \FSM_onehot_cal1_state_r[16]_i_4_n_0\ : STD_LOGIC;
  signal \FSM_onehot_cal1_state_r[1]_i_1_n_0\ : STD_LOGIC;
  signal \FSM_onehot_cal1_state_r[20]_i_1_n_0\ : STD_LOGIC;
  signal \FSM_onehot_cal1_state_r[21]_i_1_n_0\ : STD_LOGIC;
  signal \FSM_onehot_cal1_state_r[21]_i_2_n_0\ : STD_LOGIC;
  signal \FSM_onehot_cal1_state_r[21]_i_3_n_0\ : STD_LOGIC;
  signal \FSM_onehot_cal1_state_r[22]_i_1_n_0\ : STD_LOGIC;
  signal \FSM_onehot_cal1_state_r[22]_i_2_n_0\ : STD_LOGIC;
  signal \FSM_onehot_cal1_state_r[29]_i_1_n_0\ : STD_LOGIC;
  signal \FSM_onehot_cal1_state_r[2]_i_1_n_0\ : STD_LOGIC;
  signal \FSM_onehot_cal1_state_r[34]_i_10_n_0\ : STD_LOGIC;
  signal \FSM_onehot_cal1_state_r[34]_i_11_n_0\ : STD_LOGIC;
  signal \FSM_onehot_cal1_state_r[34]_i_12_n_0\ : STD_LOGIC;
  signal \FSM_onehot_cal1_state_r[34]_i_13_n_0\ : STD_LOGIC;
  signal \FSM_onehot_cal1_state_r[34]_i_1_n_0\ : STD_LOGIC;
  signal \FSM_onehot_cal1_state_r[34]_i_2_n_0\ : STD_LOGIC;
  signal \FSM_onehot_cal1_state_r[34]_i_3_n_0\ : STD_LOGIC;
  signal \FSM_onehot_cal1_state_r[34]_i_4_n_0\ : STD_LOGIC;
  signal \FSM_onehot_cal1_state_r[34]_i_5_n_0\ : STD_LOGIC;
  signal \FSM_onehot_cal1_state_r[34]_i_6_n_0\ : STD_LOGIC;
  signal \FSM_onehot_cal1_state_r[34]_i_8_n_0\ : STD_LOGIC;
  signal \FSM_onehot_cal1_state_r[34]_i_9_n_0\ : STD_LOGIC;
  signal \FSM_onehot_cal1_state_r[4]_i_1_n_0\ : STD_LOGIC;
  signal \FSM_onehot_cal1_state_r[5]_i_1_n_0\ : STD_LOGIC;
  signal \FSM_onehot_cal1_state_r[5]_i_2_n_0\ : STD_LOGIC;
  signal \FSM_onehot_cal1_state_r[5]_i_3_n_0\ : STD_LOGIC;
  signal \FSM_onehot_cal1_state_r[6]_i_1_n_0\ : STD_LOGIC;
  signal \FSM_onehot_cal1_state_r[6]_i_2_n_0\ : STD_LOGIC;
  signal \FSM_onehot_cal1_state_r[7]_i_1_n_0\ : STD_LOGIC;
  signal \FSM_onehot_cal1_state_r[8]_i_1_n_0\ : STD_LOGIC;
  signal \FSM_onehot_cal1_state_r[9]_i_1_n_0\ : STD_LOGIC;
  signal \FSM_onehot_cal1_state_r_reg_n_0_[12]\ : STD_LOGIC;
  signal \FSM_onehot_cal1_state_r_reg_n_0_[15]\ : STD_LOGIC;
  signal \FSM_onehot_cal1_state_r_reg_n_0_[16]\ : STD_LOGIC;
  signal \FSM_onehot_cal1_state_r_reg_n_0_[1]\ : STD_LOGIC;
  signal \FSM_onehot_cal1_state_r_reg_n_0_[22]\ : STD_LOGIC;
  signal \FSM_onehot_cal1_state_r_reg_n_0_[29]\ : STD_LOGIC;
  signal \FSM_onehot_cal1_state_r_reg_n_0_[3]\ : STD_LOGIC;
  signal \FSM_onehot_cal1_state_r_reg_n_0_[7]\ : STD_LOGIC;
  signal \FSM_onehot_cal1_state_r_reg_n_0_[8]\ : STD_LOGIC;
  signal \^q\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \cal1_cnt_cpt_r[0]_i_1_n_0\ : STD_LOGIC;
  signal \cal1_cnt_cpt_r[1]_i_1_n_0\ : STD_LOGIC;
  signal \cal1_cnt_cpt_r[2]_i_1_n_0\ : STD_LOGIC;
  signal \cal1_cnt_cpt_r[2]_i_2_n_0\ : STD_LOGIC;
  signal \cal1_cnt_cpt_r[2]_i_3_n_0\ : STD_LOGIC;
  signal \^cal1_cnt_cpt_r_reg[2]_1\ : STD_LOGIC;
  signal \cal1_cnt_cpt_r_reg_n_0_[0]\ : STD_LOGIC;
  signal \cal1_cnt_cpt_r_reg_n_0_[1]\ : STD_LOGIC;
  signal \cal1_cnt_cpt_r_reg_n_0_[2]\ : STD_LOGIC;
  signal cal1_dlyce_cpt_r : STD_LOGIC;
  signal cal1_dlyce_cpt_r_reg_n_0 : STD_LOGIC;
  signal cal1_dlyinc_cpt_r : STD_LOGIC;
  signal cal1_dlyinc_cpt_r_reg_n_0 : STD_LOGIC;
  signal cal1_dq_idel_ce : STD_LOGIC;
  signal cal1_dq_idel_inc : STD_LOGIC;
  signal cal1_prech_req_r : STD_LOGIC;
  signal \cal1_prech_req_r__0\ : STD_LOGIC;
  signal \cal1_state_r1[0]_i_1_n_0\ : STD_LOGIC;
  signal \cal1_state_r1[0]_i_2_n_0\ : STD_LOGIC;
  signal \cal1_state_r1[0]_i_3_n_0\ : STD_LOGIC;
  signal \cal1_state_r1[1]_i_1_n_0\ : STD_LOGIC;
  signal \cal1_state_r1[1]_i_2_n_0\ : STD_LOGIC;
  signal \cal1_state_r1[2]_i_1_n_0\ : STD_LOGIC;
  signal \cal1_state_r1[2]_i_2_n_0\ : STD_LOGIC;
  signal \cal1_state_r1[3]_i_1_n_0\ : STD_LOGIC;
  signal \cal1_state_r1[3]_i_2_n_0\ : STD_LOGIC;
  signal \cal1_state_r1[3]_i_3_n_0\ : STD_LOGIC;
  signal \cal1_state_r1[4]_i_1_n_0\ : STD_LOGIC;
  signal \cal1_state_r1[5]_i_1_n_0\ : STD_LOGIC;
  signal \cal1_state_r1_reg_n_0_[0]\ : STD_LOGIC;
  signal \cal1_state_r1_reg_n_0_[1]\ : STD_LOGIC;
  signal \cal1_state_r1_reg_n_0_[2]\ : STD_LOGIC;
  signal \cal1_state_r1_reg_n_0_[3]\ : STD_LOGIC;
  signal \cal1_state_r1_reg_n_0_[4]\ : STD_LOGIC;
  signal \cal1_state_r1_reg_n_0_[5]\ : STD_LOGIC;
  signal cal1_wait_cnt_en_r : STD_LOGIC;
  signal cal1_wait_cnt_en_r0 : STD_LOGIC;
  signal cal1_wait_cnt_en_r_i_2_n_0 : STD_LOGIC;
  signal cal1_wait_cnt_en_r_i_3_n_0 : STD_LOGIC;
  signal \cal1_wait_cnt_r[4]_i_1_n_0\ : STD_LOGIC;
  signal cal1_wait_cnt_r_reg : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal cal1_wait_r : STD_LOGIC;
  signal cal1_wait_r_i_1_n_0 : STD_LOGIC;
  signal cnt_idel_dec_cpt_r : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal cnt_idel_dec_cpt_r1 : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal \cnt_idel_dec_cpt_r[0]_i_2_n_0\ : STD_LOGIC;
  signal \cnt_idel_dec_cpt_r[0]_i_3_n_0\ : STD_LOGIC;
  signal \cnt_idel_dec_cpt_r[1]_i_2_n_0\ : STD_LOGIC;
  signal \cnt_idel_dec_cpt_r[1]_i_3_n_0\ : STD_LOGIC;
  signal \cnt_idel_dec_cpt_r[1]_i_4_n_0\ : STD_LOGIC;
  signal \cnt_idel_dec_cpt_r[2]_i_11_n_0\ : STD_LOGIC;
  signal \cnt_idel_dec_cpt_r[2]_i_12_n_0\ : STD_LOGIC;
  signal \cnt_idel_dec_cpt_r[2]_i_13_n_0\ : STD_LOGIC;
  signal \cnt_idel_dec_cpt_r[2]_i_14_n_0\ : STD_LOGIC;
  signal \cnt_idel_dec_cpt_r[2]_i_15_n_0\ : STD_LOGIC;
  signal \cnt_idel_dec_cpt_r[2]_i_3_n_0\ : STD_LOGIC;
  signal \cnt_idel_dec_cpt_r[2]_i_4_n_0\ : STD_LOGIC;
  signal \cnt_idel_dec_cpt_r[2]_i_5_n_0\ : STD_LOGIC;
  signal \cnt_idel_dec_cpt_r[2]_i_6_n_0\ : STD_LOGIC;
  signal \cnt_idel_dec_cpt_r[2]_i_7_n_0\ : STD_LOGIC;
  signal \cnt_idel_dec_cpt_r[2]_i_8_n_0\ : STD_LOGIC;
  signal \cnt_idel_dec_cpt_r[2]_i_9_n_0\ : STD_LOGIC;
  signal \cnt_idel_dec_cpt_r[3]_i_2_n_0\ : STD_LOGIC;
  signal \cnt_idel_dec_cpt_r[3]_i_3_n_0\ : STD_LOGIC;
  signal \cnt_idel_dec_cpt_r[3]_i_4_n_0\ : STD_LOGIC;
  signal \cnt_idel_dec_cpt_r[3]_i_5_n_0\ : STD_LOGIC;
  signal \cnt_idel_dec_cpt_r[4]_i_10_n_0\ : STD_LOGIC;
  signal \cnt_idel_dec_cpt_r[4]_i_11_n_0\ : STD_LOGIC;
  signal \cnt_idel_dec_cpt_r[4]_i_12_n_0\ : STD_LOGIC;
  signal \cnt_idel_dec_cpt_r[4]_i_13_n_0\ : STD_LOGIC;
  signal \cnt_idel_dec_cpt_r[4]_i_14_n_0\ : STD_LOGIC;
  signal \cnt_idel_dec_cpt_r[4]_i_3_n_0\ : STD_LOGIC;
  signal \cnt_idel_dec_cpt_r[4]_i_4_n_0\ : STD_LOGIC;
  signal \cnt_idel_dec_cpt_r[4]_i_5_n_0\ : STD_LOGIC;
  signal \cnt_idel_dec_cpt_r[4]_i_6_n_0\ : STD_LOGIC;
  signal \cnt_idel_dec_cpt_r[4]_i_7_n_0\ : STD_LOGIC;
  signal \cnt_idel_dec_cpt_r[4]_i_9_n_0\ : STD_LOGIC;
  signal \cnt_idel_dec_cpt_r[5]_i_1_n_0\ : STD_LOGIC;
  signal \cnt_idel_dec_cpt_r[5]_i_3_n_0\ : STD_LOGIC;
  signal \cnt_idel_dec_cpt_r[5]_i_4_n_0\ : STD_LOGIC;
  signal \cnt_idel_dec_cpt_r[5]_i_5_n_0\ : STD_LOGIC;
  signal \cnt_idel_dec_cpt_r[5]_i_6_n_0\ : STD_LOGIC;
  signal \cnt_idel_dec_cpt_r_reg[2]_i_10_n_0\ : STD_LOGIC;
  signal \cnt_idel_dec_cpt_r_reg[2]_i_10_n_1\ : STD_LOGIC;
  signal \cnt_idel_dec_cpt_r_reg[2]_i_10_n_2\ : STD_LOGIC;
  signal \cnt_idel_dec_cpt_r_reg[2]_i_10_n_3\ : STD_LOGIC;
  signal \cnt_idel_dec_cpt_r_reg[2]_i_10_n_4\ : STD_LOGIC;
  signal \cnt_idel_dec_cpt_r_reg[2]_i_10_n_5\ : STD_LOGIC;
  signal \cnt_idel_dec_cpt_r_reg[2]_i_10_n_6\ : STD_LOGIC;
  signal \cnt_idel_dec_cpt_r_reg[2]_i_2_n_0\ : STD_LOGIC;
  signal \cnt_idel_dec_cpt_r_reg[2]_i_2_n_1\ : STD_LOGIC;
  signal \cnt_idel_dec_cpt_r_reg[2]_i_2_n_2\ : STD_LOGIC;
  signal \cnt_idel_dec_cpt_r_reg[2]_i_2_n_3\ : STD_LOGIC;
  signal \cnt_idel_dec_cpt_r_reg[4]_i_2_n_1\ : STD_LOGIC;
  signal \cnt_idel_dec_cpt_r_reg[4]_i_2_n_3\ : STD_LOGIC;
  signal \cnt_idel_dec_cpt_r_reg[4]_i_8_n_3\ : STD_LOGIC;
  signal \cnt_idel_dec_cpt_r_reg[4]_i_8_n_6\ : STD_LOGIC;
  signal \cnt_idel_dec_cpt_r_reg[4]_i_8_n_7\ : STD_LOGIC;
  signal \cnt_idel_dec_cpt_r_reg_n_0_[0]\ : STD_LOGIC;
  signal \cnt_idel_dec_cpt_r_reg_n_0_[1]\ : STD_LOGIC;
  signal \cnt_idel_dec_cpt_r_reg_n_0_[2]\ : STD_LOGIC;
  signal \cnt_idel_dec_cpt_r_reg_n_0_[3]\ : STD_LOGIC;
  signal \cnt_idel_dec_cpt_r_reg_n_0_[4]\ : STD_LOGIC;
  signal \cnt_idel_dec_cpt_r_reg_n_0_[5]\ : STD_LOGIC;
  signal cnt_shift_r_reg : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal detect_edge_done_r : STD_LOGIC;
  signal detect_edge_done_r_i_1_n_0 : STD_LOGIC;
  signal detect_edge_done_r_i_2_n_0 : STD_LOGIC;
  signal done_cnt : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal done_cnt1 : STD_LOGIC;
  signal \done_cnt[0]_i_1_n_0\ : STD_LOGIC;
  signal \done_cnt[1]_i_1_n_0\ : STD_LOGIC;
  signal \done_cnt[2]_i_1_n_0\ : STD_LOGIC;
  signal \done_cnt[3]_i_1_n_0\ : STD_LOGIC;
  signal dqs_po_dec_done_r1 : STD_LOGIC;
  signal dqs_po_dec_done_r2 : STD_LOGIC;
  signal fine_dly_dec_done_r1 : STD_LOGIC;
  signal fine_dly_dec_done_r1_i_1_n_0 : STD_LOGIC;
  signal fine_dly_dec_done_r1_i_2_n_0 : STD_LOGIC;
  signal fine_dly_dec_done_r2 : STD_LOGIC;
  signal \first_edge_taps_r[5]_i_1_n_0\ : STD_LOGIC;
  signal \first_edge_taps_r[5]_i_2_n_0\ : STD_LOGIC;
  signal \first_edge_taps_r[5]_i_3_n_0\ : STD_LOGIC;
  signal \first_edge_taps_r_reg_n_0_[0]\ : STD_LOGIC;
  signal \first_edge_taps_r_reg_n_0_[1]\ : STD_LOGIC;
  signal \first_edge_taps_r_reg_n_0_[2]\ : STD_LOGIC;
  signal \first_edge_taps_r_reg_n_0_[3]\ : STD_LOGIC;
  signal \first_edge_taps_r_reg_n_0_[4]\ : STD_LOGIC;
  signal \first_edge_taps_r_reg_n_0_[5]\ : STD_LOGIC;
  signal found_edge_r_i_1_n_0 : STD_LOGIC;
  signal found_edge_r_i_2_n_0 : STD_LOGIC;
  signal found_edge_r_reg_n_0 : STD_LOGIC;
  signal found_first_edge_r_i_1_n_0 : STD_LOGIC;
  signal found_first_edge_r_reg_n_0 : STD_LOGIC;
  signal found_second_edge_r_i_1_n_0 : STD_LOGIC;
  signal found_second_edge_r_reg_n_0 : STD_LOGIC;
  signal found_stable_eye_last_r : STD_LOGIC;
  signal found_stable_eye_last_r_i_1_n_0 : STD_LOGIC;
  signal found_stable_eye_r_i_1_n_0 : STD_LOGIC;
  signal found_stable_eye_r_i_2_n_0 : STD_LOGIC;
  signal found_stable_eye_r_reg_n_0 : STD_LOGIC;
  signal \gen_mux_rd[0].mux_rd_fall0_r_reg_n_0_[0]\ : STD_LOGIC;
  signal \gen_mux_rd[0].mux_rd_fall1_r_reg_n_0_[0]\ : STD_LOGIC;
  signal \gen_mux_rd[0].mux_rd_fall2_r_reg_n_0_[0]\ : STD_LOGIC;
  signal \gen_mux_rd[0].mux_rd_fall3_r_reg_n_0_[0]\ : STD_LOGIC;
  signal \gen_mux_rd[0].mux_rd_rise0_r_reg_n_0_[0]\ : STD_LOGIC;
  signal \gen_mux_rd[0].mux_rd_rise1_r_reg_n_0_[0]\ : STD_LOGIC;
  signal \gen_mux_rd[0].mux_rd_rise2_r_reg_n_0_[0]\ : STD_LOGIC;
  signal \gen_mux_rd[0].mux_rd_rise3_r_reg_n_0_[0]\ : STD_LOGIC;
  signal \gen_mux_rd[1].mux_rd_fall0_r_reg_n_0_[1]\ : STD_LOGIC;
  signal \gen_mux_rd[1].mux_rd_fall1_r_reg_n_0_[1]\ : STD_LOGIC;
  signal \gen_mux_rd[1].mux_rd_fall2_r_reg_n_0_[1]\ : STD_LOGIC;
  signal \gen_mux_rd[1].mux_rd_fall3_r_reg_n_0_[1]\ : STD_LOGIC;
  signal \gen_mux_rd[1].mux_rd_rise0_r_reg_n_0_[1]\ : STD_LOGIC;
  signal \gen_mux_rd[1].mux_rd_rise1_r_reg_n_0_[1]\ : STD_LOGIC;
  signal \gen_mux_rd[1].mux_rd_rise2_r_reg_n_0_[1]\ : STD_LOGIC;
  signal \gen_mux_rd[1].mux_rd_rise3_r_reg_n_0_[1]\ : STD_LOGIC;
  signal \gen_mux_rd[2].mux_rd_fall0_r_reg_n_0_[2]\ : STD_LOGIC;
  signal \gen_mux_rd[2].mux_rd_fall1_r_reg_n_0_[2]\ : STD_LOGIC;
  signal \gen_mux_rd[2].mux_rd_fall2_r_reg_n_0_[2]\ : STD_LOGIC;
  signal \gen_mux_rd[2].mux_rd_fall3_r_reg_n_0_[2]\ : STD_LOGIC;
  signal \gen_mux_rd[2].mux_rd_rise0_r_reg_n_0_[2]\ : STD_LOGIC;
  signal \gen_mux_rd[2].mux_rd_rise1_r_reg_n_0_[2]\ : STD_LOGIC;
  signal \gen_mux_rd[2].mux_rd_rise2_r_reg_n_0_[2]\ : STD_LOGIC;
  signal \gen_mux_rd[2].mux_rd_rise3_r_reg_n_0_[2]\ : STD_LOGIC;
  signal \gen_mux_rd[3].mux_rd_fall0_r_reg_n_0_[3]\ : STD_LOGIC;
  signal \gen_mux_rd[3].mux_rd_fall1_r_reg_n_0_[3]\ : STD_LOGIC;
  signal \gen_mux_rd[3].mux_rd_fall2_r_reg_n_0_[3]\ : STD_LOGIC;
  signal \gen_mux_rd[3].mux_rd_fall3_r_reg_n_0_[3]\ : STD_LOGIC;
  signal \gen_mux_rd[3].mux_rd_rise0_r_reg_n_0_[3]\ : STD_LOGIC;
  signal \gen_mux_rd[3].mux_rd_rise1_r_reg_n_0_[3]\ : STD_LOGIC;
  signal \gen_mux_rd[3].mux_rd_rise2_r_reg_n_0_[3]\ : STD_LOGIC;
  signal \gen_mux_rd[3].mux_rd_rise3_r_reg_n_0_[3]\ : STD_LOGIC;
  signal \gen_mux_rd[4].mux_rd_fall0_r_reg_n_0_[4]\ : STD_LOGIC;
  signal \gen_mux_rd[4].mux_rd_fall1_r_reg_n_0_[4]\ : STD_LOGIC;
  signal \gen_mux_rd[4].mux_rd_fall2_r_reg_n_0_[4]\ : STD_LOGIC;
  signal \gen_mux_rd[4].mux_rd_fall3_r_reg_n_0_[4]\ : STD_LOGIC;
  signal \gen_mux_rd[4].mux_rd_rise0_r_reg_n_0_[4]\ : STD_LOGIC;
  signal \gen_mux_rd[4].mux_rd_rise1_r_reg_n_0_[4]\ : STD_LOGIC;
  signal \gen_mux_rd[4].mux_rd_rise2_r_reg_n_0_[4]\ : STD_LOGIC;
  signal \gen_mux_rd[4].mux_rd_rise3_r_reg_n_0_[4]\ : STD_LOGIC;
  signal \gen_mux_rd[5].mux_rd_fall0_r_reg_n_0_[5]\ : STD_LOGIC;
  signal \gen_mux_rd[5].mux_rd_fall1_r_reg_n_0_[5]\ : STD_LOGIC;
  signal \gen_mux_rd[5].mux_rd_fall2_r_reg_n_0_[5]\ : STD_LOGIC;
  signal \gen_mux_rd[5].mux_rd_fall3_r_reg_n_0_[5]\ : STD_LOGIC;
  signal \gen_mux_rd[5].mux_rd_rise0_r_reg_n_0_[5]\ : STD_LOGIC;
  signal \gen_mux_rd[5].mux_rd_rise1_r_reg_n_0_[5]\ : STD_LOGIC;
  signal \gen_mux_rd[5].mux_rd_rise2_r_reg_n_0_[5]\ : STD_LOGIC;
  signal \gen_mux_rd[5].mux_rd_rise3_r_reg_n_0_[5]\ : STD_LOGIC;
  signal \gen_mux_rd[6].mux_rd_fall0_r_reg_n_0_[6]\ : STD_LOGIC;
  signal \gen_mux_rd[6].mux_rd_fall1_r_reg_n_0_[6]\ : STD_LOGIC;
  signal \gen_mux_rd[6].mux_rd_fall2_r_reg_n_0_[6]\ : STD_LOGIC;
  signal \gen_mux_rd[6].mux_rd_fall3_r_reg_n_0_[6]\ : STD_LOGIC;
  signal \gen_mux_rd[6].mux_rd_rise0_r_reg_n_0_[6]\ : STD_LOGIC;
  signal \gen_mux_rd[6].mux_rd_rise1_r_reg_n_0_[6]\ : STD_LOGIC;
  signal \gen_mux_rd[6].mux_rd_rise2_r_reg_n_0_[6]\ : STD_LOGIC;
  signal \gen_mux_rd[6].mux_rd_rise3_r_reg_n_0_[6]\ : STD_LOGIC;
  signal \gen_mux_rd[7].mux_rd_fall0_r_reg_n_0_[7]\ : STD_LOGIC;
  signal \gen_mux_rd[7].mux_rd_fall1_r_reg_n_0_[7]\ : STD_LOGIC;
  signal \gen_mux_rd[7].mux_rd_fall2_r_reg_n_0_[7]\ : STD_LOGIC;
  signal \gen_mux_rd[7].mux_rd_fall3_r_reg_n_0_[7]\ : STD_LOGIC;
  signal \gen_mux_rd[7].mux_rd_rise0_r_reg_n_0_[7]\ : STD_LOGIC;
  signal \gen_mux_rd[7].mux_rd_rise1_r_reg_n_0_[7]\ : STD_LOGIC;
  signal \gen_mux_rd[7].mux_rd_rise2_r_reg_n_0_[7]\ : STD_LOGIC;
  signal \gen_mux_rd[7].mux_rd_rise3_r_reg_n_0_[7]\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[0].old_sr_fall0_r_reg[0]_191\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[0].old_sr_fall1_r_reg[0]_207\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[0].old_sr_fall2_r_reg[0]_175\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[0].old_sr_fall3_r_reg[0]_183\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[0].old_sr_rise0_r_reg[0]_223\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[0].old_sr_rise1_r_reg[0]_199\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[0].old_sr_rise2_r_reg[0]_215\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[0].old_sr_rise3_r_reg[0]_231\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[0].prev_sr_fall0_r_reg[0]_143\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[0].prev_sr_fall1_r_reg[0]_119\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[0].prev_sr_fall2_r_reg[0]_127\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[0].prev_sr_fall3_r_reg[0]_151\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[0].prev_sr_rise0_r_reg[0]_159\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[0].prev_sr_rise1_r_reg[0]_111\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[0].prev_sr_rise2_r_reg[0]_135\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[0].prev_sr_rise3_r_reg[0]_167\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[1].old_sr_fall0_r_reg[1]_192\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[1].old_sr_fall1_r_reg[1]_208\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[1].old_sr_fall2_r_reg[1]_176\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[1].old_sr_fall3_r_reg[1]_184\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[1].old_sr_rise0_r_reg[1]_224\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[1].old_sr_rise1_r_reg[1]_200\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[1].old_sr_rise2_r_reg[1]_216\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[1].old_sr_rise3_r_reg[1]_232\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[1].prev_sr_fall0_r_reg[1]_144\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[1].prev_sr_fall1_r_reg[1]_120\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[1].prev_sr_fall2_r_reg[1]_128\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[1].prev_sr_fall3_r_reg[1]_152\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[1].prev_sr_rise0_r_reg[1]_160\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[1].prev_sr_rise1_r_reg[1]_112\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[1].prev_sr_rise2_r_reg[1]_136\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[1].prev_sr_rise3_r_reg[1]_168\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[2].old_sr_fall0_r_reg[2]_193\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[2].old_sr_fall1_r_reg[2]_209\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[2].old_sr_fall2_r_reg[2]_177\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[2].old_sr_fall3_r_reg[2]_185\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[2].old_sr_rise0_r_reg[2]_225\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[2].old_sr_rise1_r_reg[2]_201\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[2].old_sr_rise2_r_reg[2]_217\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[2].old_sr_rise3_r_reg[2]_233\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[2].prev_sr_fall0_r_reg[2]_145\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[2].prev_sr_fall1_r_reg[2]_121\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[2].prev_sr_fall2_r_reg[2]_129\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[2].prev_sr_fall3_r_reg[2]_153\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[2].prev_sr_rise0_r_reg[2]_161\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[2].prev_sr_rise1_r_reg[2]_113\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[2].prev_sr_rise2_r_reg[2]_137\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[2].prev_sr_rise3_r_reg[2]_169\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[3].old_sr_fall0_r_reg[3]_194\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[3].old_sr_fall1_r_reg[3]_210\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[3].old_sr_fall2_r_reg[3]_178\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[3].old_sr_fall3_r_reg[3]_186\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[3].old_sr_rise0_r_reg[3]_226\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[3].old_sr_rise1_r_reg[3]_202\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[3].old_sr_rise2_r_reg[3]_218\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[3].old_sr_rise3_r_reg[3]_234\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[3].prev_sr_fall0_r_reg[3]_146\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[3].prev_sr_fall1_r_reg[3]_122\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[3].prev_sr_fall2_r_reg[3]_130\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[3].prev_sr_fall3_r_reg[3]_154\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[3].prev_sr_rise0_r_reg[3]_162\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[3].prev_sr_rise1_r_reg[3]_114\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[3].prev_sr_rise2_r_reg[3]_138\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[3].prev_sr_rise3_r_reg[3]_170\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[4].old_sr_fall0_r_reg[4]_195\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[4].old_sr_fall1_r_reg[4]_211\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[4].old_sr_fall2_r_reg[4]_179\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[4].old_sr_fall3_r_reg[4]_187\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[4].old_sr_rise0_r_reg[4]_227\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[4].old_sr_rise1_r_reg[4]_203\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[4].old_sr_rise2_r_reg[4]_219\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[4].old_sr_rise3_r_reg[4]_235\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[4].prev_sr_fall0_r_reg[4]_147\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[4].prev_sr_fall1_r_reg[4]_123\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[4].prev_sr_fall2_r_reg[4]_131\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[4].prev_sr_fall3_r_reg[4]_155\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[4].prev_sr_rise0_r_reg[4]_163\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[4].prev_sr_rise1_r_reg[4]_115\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[4].prev_sr_rise2_r_reg[4]_139\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[4].prev_sr_rise3_r_reg[4]_171\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[5].old_sr_fall0_r_reg[5]_196\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[5].old_sr_fall1_r_reg[5]_212\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[5].old_sr_fall2_r_reg[5]_180\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[5].old_sr_fall3_r_reg[5]_188\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[5].old_sr_rise0_r_reg[5]_228\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[5].old_sr_rise1_r_reg[5]_204\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[5].old_sr_rise2_r_reg[5]_220\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[5].old_sr_rise3_r_reg[5]_236\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[5].prev_sr_fall0_r_reg[5]_148\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[5].prev_sr_fall1_r_reg[5]_124\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[5].prev_sr_fall2_r_reg[5]_132\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[5].prev_sr_fall3_r_reg[5]_156\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[5].prev_sr_rise0_r_reg[5]_164\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[5].prev_sr_rise1_r_reg[5]_116\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[5].prev_sr_rise2_r_reg[5]_140\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[5].prev_sr_rise3_r_reg[5]_172\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[6].old_sr_fall0_r_reg[6]_197\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[6].old_sr_fall1_r_reg[6]_213\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[6].old_sr_fall2_r_reg[6]_181\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[6].old_sr_fall3_r_reg[6]_189\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[6].old_sr_rise0_r_reg[6]_229\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[6].old_sr_rise1_r_reg[6]_205\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[6].old_sr_rise2_r_reg[6]_221\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[6].old_sr_rise3_r_reg[6]_237\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[6].prev_sr_fall0_r_reg[6]_149\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[6].prev_sr_fall1_r_reg[6]_125\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[6].prev_sr_fall2_r_reg[6]_133\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[6].prev_sr_fall3_r_reg[6]_157\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[6].prev_sr_rise0_r_reg[6]_165\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[6].prev_sr_rise1_r_reg[6]_117\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[6].prev_sr_rise2_r_reg[6]_141\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[6].prev_sr_rise3_r_reg[6]_173\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[7].old_sr_fall0_r_reg[7]_198\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[7].old_sr_fall1_r_reg[7]_214\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[7].old_sr_fall2_r_reg[7]_182\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[7].old_sr_fall3_r_reg[7]_190\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[7].old_sr_rise0_r_reg[7]_230\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[7].old_sr_rise1_r_reg[7]_206\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[7].old_sr_rise2_r_reg[7]_222\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[7].old_sr_rise3_r_reg[7]_238\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[7].prev_sr_fall0_r_reg[7]_150\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[7].prev_sr_fall1_r_reg[7]_126\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[7].prev_sr_fall2_r_reg[7]_134\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[7].prev_sr_fall3_r_reg[7]_158\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[7].prev_sr_rise0_r_reg[7]_166\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[7].prev_sr_rise1_r_reg[7]_118\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[7].prev_sr_rise2_r_reg[7]_142\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[7].prev_sr_rise3_r_reg[7]_174\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_fall0_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_fall1_r[0]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_fall1_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_fall2_r[0]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_rise1_r[0]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_rise2_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_rise3_r[0]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[0].idel_pat1_match_fall3_r[0]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[0].idel_pat1_match_fall3_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[0].idel_pat1_match_rise0_r[0]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[0].idel_pat1_match_rise0_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[0].idel_pat1_match_rise2_r[0]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[0].pat0_match_fall0_r[0]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[0].pat1_match_fall2_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_fall1_r[1]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_fall2_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_fall3_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_rise0_r[1]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_rise0_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_rise2_r[1]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_rise2_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_rise3_r[1]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[1].idel_pat1_match_fall0_r[1]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[1].idel_pat1_match_fall0_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[1].idel_pat1_match_fall1_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[1].idel_pat1_match_fall2_r[1]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[1].pat0_match_fall3_r[1]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[1].pat0_match_rise1_r[1]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_fall1_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_fall2_r[2]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_fall2_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_fall3_r[2]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_rise0_r[2]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_rise0_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_rise2_r[2]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[2].idel_pat1_match_fall0_r[2]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[2].idel_pat1_match_fall0_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[2].idel_pat1_match_rise1_r[2]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[2].idel_pat1_match_rise2_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[2].idel_pat1_match_rise3_r[2]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[2].pat0_match_fall1_r[2]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[2].pat1_match_fall3_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_fall0_r[3]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_fall0_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_fall2_r[3]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_fall3_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_rise0_r[3]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_rise2_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_rise3_r[3]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[3].idel_pat1_match_fall1_r[3]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[3].idel_pat1_match_fall1_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[3].idel_pat1_match_fall2_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[3].idel_pat1_match_fall3_r[3]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[3].idel_pat1_match_rise1_r[3]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[3].pat0_match_rise2_r[3]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[3].pat1_match_rise0_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_fall0_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_fall1_r[4]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_fall1_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_fall2_r[4]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_rise1_r[4]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_rise2_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_rise3_r[4]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[4].idel_pat1_match_fall3_r[4]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[4].idel_pat1_match_fall3_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[4].idel_pat1_match_rise0_r[4]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[4].idel_pat1_match_rise0_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[4].idel_pat1_match_rise2_r[4]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[4].pat0_match_fall0_r[4]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[4].pat1_match_fall2_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_fall1_r[5]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_fall2_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_fall3_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_rise0_r[5]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_rise0_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_rise2_r[5]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_rise2_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_rise3_r[5]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[5].idel_pat1_match_fall0_r[5]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[5].idel_pat1_match_fall0_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[5].idel_pat1_match_fall1_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[5].idel_pat1_match_fall2_r[5]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[5].pat0_match_fall3_r[5]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[5].pat0_match_rise1_r[5]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_fall1_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_fall2_r[6]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_fall2_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_fall3_r[6]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_rise0_r[6]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_rise0_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_rise2_r[6]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[6].idel_pat1_match_fall0_r[6]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[6].idel_pat1_match_fall0_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[6].idel_pat1_match_rise1_r[6]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[6].idel_pat1_match_rise2_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[6].idel_pat1_match_rise3_r[6]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[6].pat0_match_fall1_r[6]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[6].pat1_match_fall3_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_fall0_r[7]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_fall0_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_fall2_r[7]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_fall3_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_rise0_r[7]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_rise2_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_rise3_r[7]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[7].idel_pat1_match_fall1_r[7]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[7].idel_pat1_match_fall1_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[7].idel_pat1_match_fall2_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[7].idel_pat1_match_fall3_r[7]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[7].idel_pat1_match_rise1_r[7]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[7].pat0_match_rise2_r[7]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[7].pat1_match_rise0_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.idel_pat0_data_match_r_i_2_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.idel_pat0_data_match_r_reg_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.idel_pat0_match_fall0_and_r_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.idel_pat0_match_fall1_and_r_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.idel_pat0_match_fall2_and_r_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.idel_pat0_match_fall2_and_r_i_2_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.idel_pat0_match_fall3_and_r_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.idel_pat0_match_fall3_and_r_i_2_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.idel_pat0_match_rise0_and_r_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.idel_pat0_match_rise1_and_r_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.idel_pat0_match_rise2_and_r_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.idel_pat0_match_rise2_and_r_i_2_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.idel_pat0_match_rise3_and_r_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.idel_pat1_data_match_r_i_2_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.idel_pat1_data_match_r_reg_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.idel_pat1_match_fall0_and_r_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.idel_pat1_match_fall0_and_r_i_2_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.idel_pat1_match_fall1_and_r_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.idel_pat1_match_fall1_and_r_i_2_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.idel_pat1_match_fall2_and_r_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.idel_pat1_match_fall3_and_r_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.idel_pat1_match_rise0_and_r_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.idel_pat1_match_rise1_and_r_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.idel_pat1_match_rise2_and_r_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.idel_pat1_match_rise3_and_r_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.pat0_data_match_r_i_2_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.pat0_data_match_r_reg_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.pat0_match_fall0_and_r_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.pat0_match_fall0_and_r_i_2_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.pat0_match_fall1_and_r_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.pat0_match_fall1_and_r_i_2_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.pat0_match_fall2_and_r_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.pat0_match_fall2_and_r_i_2_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.pat0_match_fall3_and_r_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.pat0_match_fall3_and_r_i_2_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.pat0_match_rise0_and_r_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.pat0_match_rise0_and_r_i_2_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.pat0_match_rise1_and_r_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.pat0_match_rise1_and_r_i_2_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.pat0_match_rise2_and_r_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.pat0_match_rise2_and_r_i_2_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.pat0_match_rise3_and_r_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.pat0_match_rise3_and_r_i_2_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.pat1_data_match_r_i_2_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.pat1_data_match_r_reg_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.pat1_match_fall0_and_r_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.pat1_match_fall0_and_r_i_2_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.pat1_match_fall1_and_r_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.pat1_match_fall1_and_r_i_2_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.pat1_match_fall2_and_r_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.pat1_match_fall2_and_r_i_2_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.pat1_match_fall3_and_r_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.pat1_match_fall3_and_r_i_2_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.pat1_match_rise0_and_r_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.pat1_match_rise0_and_r_i_2_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.pat1_match_rise1_and_r_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.pat1_match_rise1_and_r_i_2_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.pat1_match_rise2_and_r_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.pat1_match_rise2_and_r_i_2_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.pat1_match_rise3_and_r_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.pat1_match_rise3_and_r_i_2_n_0\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall0_r_reg[0]_95\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall1_r_reg[0]_71\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall2_r_reg[0]_79\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall3_r_reg[0]_55\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise0_r_reg[0]_47\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise1_r_reg[0]_87\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise2_r_reg[0]_63\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise3_r_reg[0]_103\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall0_r_reg[1]_96\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall1_r_reg[1]_72\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall2_r_reg[1]_80\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall3_r_reg[1]_56\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise0_r_reg[1]_48\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise1_r_reg[1]_88\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise2_r_reg[1]_64\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise3_r_reg[1]_104\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall0_r_reg[2]_97\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall1_r_reg[2]_73\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall2_r_reg[2]_81\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall3_r_reg[2]_57\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise0_r_reg[2]_49\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise1_r_reg[2]_89\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise2_r_reg[2]_65\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise3_r_reg[2]_105\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall0_r_reg[3]_98\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall1_r_reg[3]_74\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall2_r_reg[3]_82\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall3_r_reg[3]_58\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise0_r_reg[3]_50\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise1_r_reg[3]_90\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise2_r_reg[3]_66\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise3_r_reg[3]_106\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall0_r_reg[4]_99\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall1_r_reg[4]_75\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall2_r_reg[4]_83\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall3_r_reg[4]_59\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise0_r_reg[4]_51\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise1_r_reg[4]_91\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise2_r_reg[4]_67\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise3_r_reg[4]_107\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall0_r_reg[5]_100\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall1_r_reg[5]_76\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall2_r_reg[5]_84\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall3_r_reg[5]_60\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise0_r_reg[5]_52\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise1_r_reg[5]_92\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise2_r_reg[5]_68\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise3_r_reg[5]_108\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall0_r_reg[6]_101\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall1_r_reg[6]_77\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall2_r_reg[6]_85\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall3_r_reg[6]_61\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise0_r_reg[6]_53\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise1_r_reg[6]_93\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise2_r_reg[6]_69\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise3_r_reg[6]_109\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall0_r_reg[7]_102\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall1_r_reg[7]_78\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall2_r_reg[7]_86\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall3_r_reg[7]_62\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise0_r_reg[7]_54\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise1_r_reg[7]_94\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise2_r_reg[7]_70\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise3_r_reg[7]_110\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[0].old_sr_diff_r_reg_n_0_[0]\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[0].old_sr_match_cyc2_r[0]_inv_i_2_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[0].old_sr_match_cyc2_r_reg[0]_inv_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall0_r[0]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall0_r_reg_n_0_[0]\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall1_r[0]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall1_r_reg_n_0_[0]\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall2_r[0]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall2_r_reg_n_0_[0]\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall3_r[0]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall3_r_reg_n_0_[0]\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise0_r[0]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise0_r_reg_n_0_[0]\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise1_r[0]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise1_r_reg_n_0_[0]\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise2_r[0]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise2_r_reg_n_0_[0]\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise3_r[0]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise3_r_reg_n_0_[0]\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[0].prev_sr_diff_r[0]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[0].prev_sr_diff_r_reg_n_0_[0]\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_cyc2_r[0]_inv_i_2_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_cyc2_r_reg[0]_inv_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r_reg_n_0_[0]\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall1_r[0]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall1_r_reg_n_0_[0]\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall2_r[0]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall2_r_reg_n_0_[0]\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall3_r[0]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall3_r_reg_n_0_[0]\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise0_r[0]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise0_r_reg_n_0_[0]\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise1_r[0]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise1_r_reg_n_0_[0]\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise2_r[0]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise2_r_reg_n_0_[0]\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise3_r[0]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise3_r_reg_n_0_[0]\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[1].old_sr_match_cyc2_r[1]_inv_i_2_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[1].old_sr_match_cyc2_r_reg[1]_inv_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[1].old_sr_match_fall0_r[1]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[1].old_sr_match_fall1_r[1]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[1].old_sr_match_fall2_r[1]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[1].old_sr_match_fall3_r[1]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[1].old_sr_match_rise0_r[1]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[1].old_sr_match_rise1_r[1]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[1].old_sr_match_rise2_r[1]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[1].old_sr_match_rise3_r[1]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[1].prev_sr_match_cyc2_r[1]_inv_i_2_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[1].prev_sr_match_cyc2_r_reg[1]_inv_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[1].prev_sr_match_fall0_r[1]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[1].prev_sr_match_fall1_r[1]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[1].prev_sr_match_fall2_r[1]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[1].prev_sr_match_fall3_r[1]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[1].prev_sr_match_rise0_r[1]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[1].prev_sr_match_rise1_r[1]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[1].prev_sr_match_rise2_r[1]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[1].prev_sr_match_rise3_r[1]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[2].old_sr_match_cyc2_r[2]_inv_i_2_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[2].old_sr_match_cyc2_r_reg[2]_inv_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[2].old_sr_match_fall0_r[2]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[2].old_sr_match_fall1_r[2]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[2].old_sr_match_fall2_r[2]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[2].old_sr_match_fall3_r[2]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[2].old_sr_match_rise0_r[2]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[2].old_sr_match_rise1_r[2]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[2].old_sr_match_rise2_r[2]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[2].old_sr_match_rise3_r[2]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[2].prev_sr_match_cyc2_r[2]_inv_i_2_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[2].prev_sr_match_cyc2_r_reg[2]_inv_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[2].prev_sr_match_fall0_r[2]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[2].prev_sr_match_fall1_r[2]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[2].prev_sr_match_fall2_r[2]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[2].prev_sr_match_fall3_r[2]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[2].prev_sr_match_rise0_r[2]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[2].prev_sr_match_rise1_r[2]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[2].prev_sr_match_rise2_r[2]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[2].prev_sr_match_rise3_r[2]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[3].old_sr_match_cyc2_r[3]_inv_i_2_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[3].old_sr_match_cyc2_r_reg[3]_inv_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[3].old_sr_match_fall0_r[3]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[3].old_sr_match_fall1_r[3]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[3].old_sr_match_fall2_r[3]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[3].old_sr_match_fall3_r[3]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[3].old_sr_match_rise0_r[3]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[3].old_sr_match_rise1_r[3]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[3].old_sr_match_rise2_r[3]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[3].old_sr_match_rise3_r[3]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[3].prev_sr_match_cyc2_r[3]_inv_i_2_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[3].prev_sr_match_cyc2_r_reg[3]_inv_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[3].prev_sr_match_fall0_r[3]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[3].prev_sr_match_fall1_r[3]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[3].prev_sr_match_fall2_r[3]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[3].prev_sr_match_fall3_r[3]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[3].prev_sr_match_rise0_r[3]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[3].prev_sr_match_rise1_r[3]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[3].prev_sr_match_rise2_r[3]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[3].prev_sr_match_rise3_r[3]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[4].old_sr_match_cyc2_r[4]_inv_i_2_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[4].old_sr_match_cyc2_r_reg[4]_inv_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[4].old_sr_match_fall0_r[4]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[4].old_sr_match_fall1_r[4]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[4].old_sr_match_fall2_r[4]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[4].old_sr_match_fall3_r[4]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[4].old_sr_match_rise0_r[4]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[4].old_sr_match_rise1_r[4]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[4].old_sr_match_rise2_r[4]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[4].old_sr_match_rise3_r[4]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[4].prev_sr_match_cyc2_r[4]_inv_i_2_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[4].prev_sr_match_cyc2_r_reg[4]_inv_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[4].prev_sr_match_fall0_r[4]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[4].prev_sr_match_fall1_r[4]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[4].prev_sr_match_fall2_r[4]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[4].prev_sr_match_fall3_r[4]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[4].prev_sr_match_rise0_r[4]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[4].prev_sr_match_rise1_r[4]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[4].prev_sr_match_rise2_r[4]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[4].prev_sr_match_rise3_r[4]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[5].old_sr_match_cyc2_r[5]_inv_i_2_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[5].old_sr_match_cyc2_r_reg[5]_inv_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[5].old_sr_match_fall0_r[5]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[5].old_sr_match_fall1_r[5]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[5].old_sr_match_fall2_r[5]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[5].old_sr_match_fall3_r[5]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[5].old_sr_match_rise0_r[5]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[5].old_sr_match_rise1_r[5]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[5].old_sr_match_rise2_r[5]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[5].old_sr_match_rise3_r[5]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[5].prev_sr_match_cyc2_r[5]_inv_i_2_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[5].prev_sr_match_cyc2_r_reg[5]_inv_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[5].prev_sr_match_fall0_r[5]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[5].prev_sr_match_fall1_r[5]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[5].prev_sr_match_fall2_r[5]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[5].prev_sr_match_fall3_r[5]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[5].prev_sr_match_rise0_r[5]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[5].prev_sr_match_rise1_r[5]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[5].prev_sr_match_rise2_r[5]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[5].prev_sr_match_rise3_r[5]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[6].old_sr_match_cyc2_r[6]_inv_i_2_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[6].old_sr_match_cyc2_r_reg[6]_inv_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[6].old_sr_match_fall0_r[6]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[6].old_sr_match_fall1_r[6]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[6].old_sr_match_fall2_r[6]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[6].old_sr_match_fall3_r[6]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[6].old_sr_match_rise0_r[6]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[6].old_sr_match_rise1_r[6]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[6].old_sr_match_rise2_r[6]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[6].old_sr_match_rise3_r[6]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[6].prev_sr_match_cyc2_r[6]_inv_i_2_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[6].prev_sr_match_cyc2_r_reg[6]_inv_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[6].prev_sr_match_fall0_r[6]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[6].prev_sr_match_fall1_r[6]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[6].prev_sr_match_fall2_r[6]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[6].prev_sr_match_fall3_r[6]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[6].prev_sr_match_rise0_r[6]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[6].prev_sr_match_rise1_r[6]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[6].prev_sr_match_rise2_r[6]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[6].prev_sr_match_rise3_r[6]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[7].old_sr_diff_r_reg_n_0_[7]\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[7].old_sr_match_cyc2_r[7]_inv_i_2_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[7].old_sr_match_cyc2_r_reg[7]_inv_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[7].old_sr_match_fall0_r[7]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[7].old_sr_match_fall1_r[7]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[7].old_sr_match_fall2_r[7]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[7].old_sr_match_fall2_r_reg_n_0_[7]\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[7].old_sr_match_fall3_r[7]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[7].old_sr_match_rise0_r[7]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[7].old_sr_match_rise1_r[7]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[7].old_sr_match_rise1_r_reg_n_0_[7]\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[7].old_sr_match_rise2_r[7]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[7].old_sr_match_rise2_r_reg_n_0_[7]\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[7].old_sr_match_rise3_r[7]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[7].prev_sr_diff_r_reg_n_0_[7]\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[7].prev_sr_match_cyc2_r[7]_inv_i_2_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[7].prev_sr_match_cyc2_r_reg[7]_inv_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[7].prev_sr_match_fall0_r[7]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[7].prev_sr_match_fall1_r[7]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[7].prev_sr_match_fall2_r[7]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[7].prev_sr_match_fall3_r[7]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[7].prev_sr_match_rise0_r[7]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[7].prev_sr_match_rise1_r[7]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[7].prev_sr_match_rise2_r[7]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[7].prev_sr_match_rise3_r[7]_i_1_n_0\ : STD_LOGIC;
  signal \gen_track_left_edge[0].pb_cnt_eye_size_r[0][4]_i_1_n_0\ : STD_LOGIC;
  signal \gen_track_left_edge[0].pb_cnt_eye_size_r[0][4]_i_4_n_0\ : STD_LOGIC;
  signal \gen_track_left_edge[0].pb_cnt_eye_size_r[0][4]_i_5_n_0\ : STD_LOGIC;
  signal \gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0]_239\ : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal \gen_track_left_edge[0].pb_detect_edge_done_r[0]_i_1_n_0\ : STD_LOGIC;
  signal \gen_track_left_edge[0].pb_found_edge_r[0]_i_1_n_0\ : STD_LOGIC;
  signal \gen_track_left_edge[0].pb_found_edge_r[0]_i_2_n_0\ : STD_LOGIC;
  signal \gen_track_left_edge[0].pb_found_edge_r_reg_n_0_[0]\ : STD_LOGIC;
  signal \gen_track_left_edge[0].pb_found_stable_eye_r[0]_i_1_n_0\ : STD_LOGIC;
  signal \gen_track_left_edge[0].pb_last_tap_jitter_r[0]_i_1_n_0\ : STD_LOGIC;
  signal \gen_track_left_edge[0].pb_last_tap_jitter_r_reg_n_0_[0]\ : STD_LOGIC;
  signal \gen_track_left_edge[1].pb_cnt_eye_size_r[1][4]_i_1_n_0\ : STD_LOGIC;
  signal \gen_track_left_edge[1].pb_cnt_eye_size_r[1][4]_i_2_n_0\ : STD_LOGIC;
  signal \gen_track_left_edge[1].pb_cnt_eye_size_r[1][4]_i_4_n_0\ : STD_LOGIC;
  signal \gen_track_left_edge[1].pb_cnt_eye_size_r[1][4]_i_5_n_0\ : STD_LOGIC;
  signal \gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1]_240\ : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal \gen_track_left_edge[1].pb_detect_edge_done_r[1]_i_1_n_0\ : STD_LOGIC;
  signal \gen_track_left_edge[1].pb_found_edge_r[1]_i_1_n_0\ : STD_LOGIC;
  signal \gen_track_left_edge[1].pb_found_edge_r[1]_i_2_n_0\ : STD_LOGIC;
  signal \gen_track_left_edge[1].pb_found_edge_r_reg_n_0_[1]\ : STD_LOGIC;
  signal \gen_track_left_edge[1].pb_found_stable_eye_r[1]_i_1_n_0\ : STD_LOGIC;
  signal \gen_track_left_edge[1].pb_last_tap_jitter_r[1]_i_1_n_0\ : STD_LOGIC;
  signal \gen_track_left_edge[2].pb_cnt_eye_size_r[2][4]_i_1_n_0\ : STD_LOGIC;
  signal \gen_track_left_edge[2].pb_cnt_eye_size_r[2][4]_i_2_n_0\ : STD_LOGIC;
  signal \gen_track_left_edge[2].pb_cnt_eye_size_r[2][4]_i_4_n_0\ : STD_LOGIC;
  signal \gen_track_left_edge[2].pb_cnt_eye_size_r[2][4]_i_5_n_0\ : STD_LOGIC;
  signal \gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2]_241\ : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal \gen_track_left_edge[2].pb_detect_edge_done_r[2]_i_1_n_0\ : STD_LOGIC;
  signal \gen_track_left_edge[2].pb_found_edge_r[2]_i_1_n_0\ : STD_LOGIC;
  signal \gen_track_left_edge[2].pb_found_edge_r[2]_i_2_n_0\ : STD_LOGIC;
  signal \gen_track_left_edge[2].pb_found_edge_r_reg_n_0_[2]\ : STD_LOGIC;
  signal \gen_track_left_edge[2].pb_found_stable_eye_r[2]_i_1_n_0\ : STD_LOGIC;
  signal \gen_track_left_edge[2].pb_last_tap_jitter_r[2]_i_1_n_0\ : STD_LOGIC;
  signal \gen_track_left_edge[3].pb_cnt_eye_size_r[3][4]_i_1_n_0\ : STD_LOGIC;
  signal \gen_track_left_edge[3].pb_cnt_eye_size_r[3][4]_i_2_n_0\ : STD_LOGIC;
  signal \gen_track_left_edge[3].pb_cnt_eye_size_r[3][4]_i_4_n_0\ : STD_LOGIC;
  signal \gen_track_left_edge[3].pb_cnt_eye_size_r[3][4]_i_5_n_0\ : STD_LOGIC;
  signal \gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3]_242\ : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal \gen_track_left_edge[3].pb_detect_edge_done_r[3]_i_1_n_0\ : STD_LOGIC;
  signal \gen_track_left_edge[3].pb_found_edge_r[3]_i_1_n_0\ : STD_LOGIC;
  signal \gen_track_left_edge[3].pb_found_edge_r[3]_i_2_n_0\ : STD_LOGIC;
  signal \gen_track_left_edge[3].pb_found_edge_r_reg_n_0_[3]\ : STD_LOGIC;
  signal \gen_track_left_edge[3].pb_found_stable_eye_r[3]_i_1_n_0\ : STD_LOGIC;
  signal \gen_track_left_edge[3].pb_last_tap_jitter_r[3]_i_1_n_0\ : STD_LOGIC;
  signal \gen_track_left_edge[4].pb_cnt_eye_size_r[4][4]_i_1_n_0\ : STD_LOGIC;
  signal \gen_track_left_edge[4].pb_cnt_eye_size_r[4][4]_i_2_n_0\ : STD_LOGIC;
  signal \gen_track_left_edge[4].pb_cnt_eye_size_r[4][4]_i_4_n_0\ : STD_LOGIC;
  signal \gen_track_left_edge[4].pb_cnt_eye_size_r[4][4]_i_5_n_0\ : STD_LOGIC;
  signal \gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4]_243\ : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal \gen_track_left_edge[4].pb_detect_edge_done_r[4]_i_1_n_0\ : STD_LOGIC;
  signal \gen_track_left_edge[4].pb_found_edge_r[4]_i_1_n_0\ : STD_LOGIC;
  signal \gen_track_left_edge[4].pb_found_edge_r[4]_i_2_n_0\ : STD_LOGIC;
  signal \gen_track_left_edge[4].pb_found_edge_r_reg_n_0_[4]\ : STD_LOGIC;
  signal \gen_track_left_edge[4].pb_found_stable_eye_r[4]_i_1_n_0\ : STD_LOGIC;
  signal \gen_track_left_edge[4].pb_last_tap_jitter_r[4]_i_1_n_0\ : STD_LOGIC;
  signal \gen_track_left_edge[5].pb_cnt_eye_size_r[5][4]_i_1_n_0\ : STD_LOGIC;
  signal \gen_track_left_edge[5].pb_cnt_eye_size_r[5][4]_i_2_n_0\ : STD_LOGIC;
  signal \gen_track_left_edge[5].pb_cnt_eye_size_r[5][4]_i_4_n_0\ : STD_LOGIC;
  signal \gen_track_left_edge[5].pb_cnt_eye_size_r[5][4]_i_5_n_0\ : STD_LOGIC;
  signal \gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5]_244\ : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal \gen_track_left_edge[5].pb_detect_edge_done_r[5]_i_1_n_0\ : STD_LOGIC;
  signal \gen_track_left_edge[5].pb_found_edge_r[5]_i_1_n_0\ : STD_LOGIC;
  signal \gen_track_left_edge[5].pb_found_edge_r[5]_i_2_n_0\ : STD_LOGIC;
  signal \gen_track_left_edge[5].pb_found_edge_r_reg_n_0_[5]\ : STD_LOGIC;
  signal \gen_track_left_edge[5].pb_found_stable_eye_r[5]_i_1_n_0\ : STD_LOGIC;
  signal \gen_track_left_edge[5].pb_last_tap_jitter_r[5]_i_1_n_0\ : STD_LOGIC;
  signal \gen_track_left_edge[6].pb_cnt_eye_size_r[6][4]_i_1_n_0\ : STD_LOGIC;
  signal \gen_track_left_edge[6].pb_cnt_eye_size_r[6][4]_i_2_n_0\ : STD_LOGIC;
  signal \gen_track_left_edge[6].pb_cnt_eye_size_r[6][4]_i_4_n_0\ : STD_LOGIC;
  signal \gen_track_left_edge[6].pb_cnt_eye_size_r[6][4]_i_5_n_0\ : STD_LOGIC;
  signal \gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6]_245\ : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal \gen_track_left_edge[6].pb_detect_edge_done_r[6]_i_1_n_0\ : STD_LOGIC;
  signal \gen_track_left_edge[6].pb_found_edge_r[6]_i_1_n_0\ : STD_LOGIC;
  signal \gen_track_left_edge[6].pb_found_edge_r[6]_i_2_n_0\ : STD_LOGIC;
  signal \gen_track_left_edge[6].pb_found_edge_r_reg_n_0_[6]\ : STD_LOGIC;
  signal \gen_track_left_edge[6].pb_found_stable_eye_r[6]_i_1_n_0\ : STD_LOGIC;
  signal \gen_track_left_edge[6].pb_last_tap_jitter_r[6]_i_1_n_0\ : STD_LOGIC;
  signal \gen_track_left_edge[7].pb_cnt_eye_size_r[7][4]_i_1_n_0\ : STD_LOGIC;
  signal \gen_track_left_edge[7].pb_cnt_eye_size_r[7][4]_i_2_n_0\ : STD_LOGIC;
  signal \gen_track_left_edge[7].pb_cnt_eye_size_r[7][4]_i_4_n_0\ : STD_LOGIC;
  signal \gen_track_left_edge[7].pb_cnt_eye_size_r[7][4]_i_5_n_0\ : STD_LOGIC;
  signal \gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7]_246\ : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal \gen_track_left_edge[7].pb_detect_edge_done_r[7]_i_1_n_0\ : STD_LOGIC;
  signal \gen_track_left_edge[7].pb_found_edge_r[7]_i_1_n_0\ : STD_LOGIC;
  signal \gen_track_left_edge[7].pb_found_edge_r[7]_i_2_n_0\ : STD_LOGIC;
  signal \gen_track_left_edge[7].pb_found_edge_r_reg_n_0_[7]\ : STD_LOGIC;
  signal \gen_track_left_edge[7].pb_found_stable_eye_r[7]_i_1_n_0\ : STD_LOGIC;
  signal \gen_track_left_edge[7].pb_last_tap_jitter_r[7]_i_1_n_0\ : STD_LOGIC;
  signal idel_adj_inc_i_1_n_0 : STD_LOGIC;
  signal idel_adj_inc_reg_n_0 : STD_LOGIC;
  signal idel_dec_cnt : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal \idel_dec_cnt[3]_i_2_n_0\ : STD_LOGIC;
  signal \idel_dec_cnt[4]_i_1_n_0\ : STD_LOGIC;
  signal \idel_dec_cnt[4]_i_3_n_0\ : STD_LOGIC;
  signal \idel_dec_cnt[4]_i_4_n_0\ : STD_LOGIC;
  signal \idel_dec_cnt[4]_i_5_n_0\ : STD_LOGIC;
  signal \idel_dec_cnt_reg_n_0_[0]\ : STD_LOGIC;
  signal \idel_dec_cnt_reg_n_0_[1]\ : STD_LOGIC;
  signal \idel_dec_cnt_reg_n_0_[2]\ : STD_LOGIC;
  signal \idel_dec_cnt_reg_n_0_[3]\ : STD_LOGIC;
  signal \idel_dec_cnt_reg_n_0_[4]\ : STD_LOGIC;
  signal idel_mpr_pat_detect_r : STD_LOGIC;
  signal idel_pat0_data_match_r0 : STD_LOGIC;
  signal idel_pat0_match_fall0_and_r : STD_LOGIC;
  signal idel_pat0_match_fall1_and_r : STD_LOGIC;
  signal idel_pat0_match_fall2_and_r : STD_LOGIC;
  signal idel_pat0_match_fall3_and_r : STD_LOGIC;
  signal idel_pat0_match_rise0_and_r : STD_LOGIC;
  signal idel_pat0_match_rise1_and_r : STD_LOGIC;
  signal idel_pat0_match_rise2_and_r : STD_LOGIC;
  signal idel_pat0_match_rise3_and_r : STD_LOGIC;
  signal idel_pat0_match_rise3_r : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal idel_pat1_data_match_r0 : STD_LOGIC;
  signal idel_pat1_match_fall0_and_r : STD_LOGIC;
  signal idel_pat1_match_fall1_and_r : STD_LOGIC;
  signal idel_pat1_match_fall2_and_r : STD_LOGIC;
  signal idel_pat1_match_fall3_and_r : STD_LOGIC;
  signal idel_pat1_match_rise0_and_r : STD_LOGIC;
  signal idel_pat1_match_rise1_and_r : STD_LOGIC;
  signal idel_pat1_match_rise1_r : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal idel_pat1_match_rise2_and_r : STD_LOGIC;
  signal idel_pat1_match_rise3_and_r : STD_LOGIC;
  signal idel_pat_detect_valid_r_i_1_n_0 : STD_LOGIC;
  signal idel_pat_detect_valid_r_reg_n_0 : STD_LOGIC;
  signal \^idelay_ce_int\ : STD_LOGIC;
  signal \^idelay_inc_int\ : STD_LOGIC;
  signal idelay_tap_cnt_r : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal \idelay_tap_cnt_r[0][0][0]_i_1_n_0\ : STD_LOGIC;
  signal \idelay_tap_cnt_r[0][0][1]_i_1_n_0\ : STD_LOGIC;
  signal \idelay_tap_cnt_r[0][0][2]_i_1_n_0\ : STD_LOGIC;
  signal \idelay_tap_cnt_r[0][0][3]_i_1_n_0\ : STD_LOGIC;
  signal \idelay_tap_cnt_r[0][0][3]_i_2_n_0\ : STD_LOGIC;
  signal \idelay_tap_cnt_r[0][0][4]_i_2_n_0\ : STD_LOGIC;
  signal \idelay_tap_cnt_r[0][0][4]_i_6_n_0\ : STD_LOGIC;
  signal \idelay_tap_cnt_r_reg_n_0_[0][0][0]\ : STD_LOGIC;
  signal \idelay_tap_cnt_r_reg_n_0_[0][0][1]\ : STD_LOGIC;
  signal \idelay_tap_cnt_r_reg_n_0_[0][0][2]\ : STD_LOGIC;
  signal \idelay_tap_cnt_r_reg_n_0_[0][0][3]\ : STD_LOGIC;
  signal \idelay_tap_cnt_r_reg_n_0_[0][0][4]\ : STD_LOGIC;
  signal \idelay_tap_cnt_r_reg_n_0_[0][1][0]\ : STD_LOGIC;
  signal \idelay_tap_cnt_r_reg_n_0_[0][1][1]\ : STD_LOGIC;
  signal \idelay_tap_cnt_r_reg_n_0_[0][1][2]\ : STD_LOGIC;
  signal \idelay_tap_cnt_r_reg_n_0_[0][1][3]\ : STD_LOGIC;
  signal \idelay_tap_cnt_r_reg_n_0_[0][1][4]\ : STD_LOGIC;
  signal \idelay_tap_cnt_r_reg_n_0_[0][2][0]\ : STD_LOGIC;
  signal \idelay_tap_cnt_r_reg_n_0_[0][2][1]\ : STD_LOGIC;
  signal \idelay_tap_cnt_r_reg_n_0_[0][2][2]\ : STD_LOGIC;
  signal \idelay_tap_cnt_r_reg_n_0_[0][2][3]\ : STD_LOGIC;
  signal \idelay_tap_cnt_r_reg_n_0_[0][2][4]\ : STD_LOGIC;
  signal \idelay_tap_cnt_r_reg_n_0_[0][3][0]\ : STD_LOGIC;
  signal \idelay_tap_cnt_r_reg_n_0_[0][3][1]\ : STD_LOGIC;
  signal \idelay_tap_cnt_r_reg_n_0_[0][3][2]\ : STD_LOGIC;
  signal \idelay_tap_cnt_r_reg_n_0_[0][3][3]\ : STD_LOGIC;
  signal \idelay_tap_cnt_r_reg_n_0_[0][3][4]\ : STD_LOGIC;
  signal \idelay_tap_cnt_r_reg_n_0_[0][4][0]\ : STD_LOGIC;
  signal \idelay_tap_cnt_r_reg_n_0_[0][4][1]\ : STD_LOGIC;
  signal \idelay_tap_cnt_r_reg_n_0_[0][4][2]\ : STD_LOGIC;
  signal \idelay_tap_cnt_r_reg_n_0_[0][4][3]\ : STD_LOGIC;
  signal \idelay_tap_cnt_r_reg_n_0_[0][4][4]\ : STD_LOGIC;
  signal \idelay_tap_cnt_r_reg_n_0_[0][5][0]\ : STD_LOGIC;
  signal \idelay_tap_cnt_r_reg_n_0_[0][5][1]\ : STD_LOGIC;
  signal \idelay_tap_cnt_r_reg_n_0_[0][5][2]\ : STD_LOGIC;
  signal \idelay_tap_cnt_r_reg_n_0_[0][5][3]\ : STD_LOGIC;
  signal \idelay_tap_cnt_r_reg_n_0_[0][5][4]\ : STD_LOGIC;
  signal \idelay_tap_cnt_r_reg_n_0_[0][6][0]\ : STD_LOGIC;
  signal \idelay_tap_cnt_r_reg_n_0_[0][6][1]\ : STD_LOGIC;
  signal \idelay_tap_cnt_r_reg_n_0_[0][6][2]\ : STD_LOGIC;
  signal \idelay_tap_cnt_r_reg_n_0_[0][6][3]\ : STD_LOGIC;
  signal \idelay_tap_cnt_r_reg_n_0_[0][6][4]\ : STD_LOGIC;
  signal \idelay_tap_cnt_r_reg_n_0_[0][7][0]\ : STD_LOGIC;
  signal \idelay_tap_cnt_r_reg_n_0_[0][7][1]\ : STD_LOGIC;
  signal \idelay_tap_cnt_r_reg_n_0_[0][7][2]\ : STD_LOGIC;
  signal \idelay_tap_cnt_r_reg_n_0_[0][7][3]\ : STD_LOGIC;
  signal \idelay_tap_cnt_r_reg_n_0_[0][7][4]\ : STD_LOGIC;
  signal idelay_tap_cnt_slice_r : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal \idelay_tap_cnt_slice_r[0]_i_2_n_0\ : STD_LOGIC;
  signal \idelay_tap_cnt_slice_r[0]_i_3_n_0\ : STD_LOGIC;
  signal \idelay_tap_cnt_slice_r[1]_i_2_n_0\ : STD_LOGIC;
  signal \idelay_tap_cnt_slice_r[1]_i_3_n_0\ : STD_LOGIC;
  signal \idelay_tap_cnt_slice_r[2]_i_2_n_0\ : STD_LOGIC;
  signal \idelay_tap_cnt_slice_r[2]_i_3_n_0\ : STD_LOGIC;
  signal \idelay_tap_cnt_slice_r[3]_i_2_n_0\ : STD_LOGIC;
  signal \idelay_tap_cnt_slice_r[3]_i_3_n_0\ : STD_LOGIC;
  signal \idelay_tap_cnt_slice_r[4]_i_2_n_0\ : STD_LOGIC;
  signal \idelay_tap_cnt_slice_r[4]_i_3_n_0\ : STD_LOGIC;
  signal idelay_tap_limit_r_i_1_n_0 : STD_LOGIC;
  signal idelay_tap_limit_r_i_2_n_0 : STD_LOGIC;
  signal idelay_tap_limit_r_reg_n_0 : STD_LOGIC;
  signal inhibit_edge_detect_r : STD_LOGIC;
  signal \mpr_4to1.idel_mpr_pat_detect_r_i_1_n_0\ : STD_LOGIC;
  signal \mpr_4to1.idel_mpr_pat_detect_r_i_2_n_0\ : STD_LOGIC;
  signal \mpr_4to1.idel_mpr_pat_detect_r_i_3_n_0\ : STD_LOGIC;
  signal \mpr_4to1.inhibit_edge_detect_r_i_1_n_0\ : STD_LOGIC;
  signal \mpr_4to1.inhibit_edge_detect_r_i_2_n_0\ : STD_LOGIC;
  signal \mpr_4to1.inhibit_edge_detect_r_i_3_n_0\ : STD_LOGIC;
  signal \mpr_4to1.inhibit_edge_detect_r_i_4_n_0\ : STD_LOGIC;
  signal \mpr_4to1.inhibit_edge_detect_r_i_5_n_0\ : STD_LOGIC;
  signal \mpr_4to1.inhibit_edge_detect_r_i_6_n_0\ : STD_LOGIC;
  signal \mpr_4to1.stable_idel_cnt[0]_i_1_n_0\ : STD_LOGIC;
  signal \mpr_4to1.stable_idel_cnt[1]_i_1_n_0\ : STD_LOGIC;
  signal \mpr_4to1.stable_idel_cnt[2]_i_1_n_0\ : STD_LOGIC;
  signal \mpr_4to1.stable_idel_cnt[2]_i_4_n_0\ : STD_LOGIC;
  signal \mpr_4to1.stable_idel_cnt[2]_i_5_n_0\ : STD_LOGIC;
  signal \mpr_4to1.stable_idel_cnt[2]_i_6_n_0\ : STD_LOGIC;
  signal \mpr_4to1.stable_idel_cnt[2]_i_7_n_0\ : STD_LOGIC;
  signal \mpr_4to1.stable_idel_cnt_reg_n_0_[0]\ : STD_LOGIC;
  signal \mpr_4to1.stable_idel_cnt_reg_n_0_[1]\ : STD_LOGIC;
  signal \mpr_4to1.stable_idel_cnt_reg_n_0_[2]\ : STD_LOGIC;
  signal mpr_dec_cpt_r : STD_LOGIC;
  signal mpr_dec_cpt_r_i_1_n_0 : STD_LOGIC;
  signal mpr_dec_cpt_r_reg_n_0 : STD_LOGIC;
  signal mpr_rd_fall0_prev_r : STD_LOGIC;
  signal mpr_rd_fall1_prev_r : STD_LOGIC;
  signal mpr_rd_fall2_prev_r : STD_LOGIC;
  signal mpr_rd_fall3_prev_r : STD_LOGIC;
  signal mpr_rd_rise0_prev_r : STD_LOGIC;
  signal mpr_rd_rise0_prev_r0 : STD_LOGIC;
  signal mpr_rd_rise1_prev_r : STD_LOGIC;
  signal mpr_rd_rise2_prev_r : STD_LOGIC;
  signal mpr_rd_rise3_prev_r : STD_LOGIC;
  signal mpr_rdlvl_start_r : STD_LOGIC;
  signal new_cnt_cpt_r : STD_LOGIC;
  signal new_cnt_cpt_r_i_2_n_0 : STD_LOGIC;
  signal \^new_cnt_cpt_r_reg_0\ : STD_LOGIC;
  signal p_0_in : STD_LOGIC;
  signal p_0_in100_in : STD_LOGIC;
  signal p_0_in103_in : STD_LOGIC;
  signal p_0_in10_in : STD_LOGIC;
  signal p_0_in135_in : STD_LOGIC;
  signal p_0_in13_in : STD_LOGIC;
  signal p_0_in157_in : STD_LOGIC;
  signal p_0_in16_in : STD_LOGIC;
  signal p_0_in182_in : STD_LOGIC;
  signal p_0_in1_in : STD_LOGIC;
  signal p_0_in207_in : STD_LOGIC;
  signal p_0_in232_in : STD_LOGIC;
  signal p_0_in257_in : STD_LOGIC;
  signal p_0_in282_in : STD_LOGIC;
  signal p_0_in307_in : STD_LOGIC;
  signal p_0_in332_in : STD_LOGIC;
  signal p_0_in357_in : STD_LOGIC;
  signal p_0_in382_in : STD_LOGIC;
  signal p_0_in407_in : STD_LOGIC;
  signal p_0_in432_in : STD_LOGIC;
  signal p_0_in457_in : STD_LOGIC;
  signal p_0_in4_in : STD_LOGIC;
  signal p_0_in541_in : STD_LOGIC;
  signal p_0_in549_in : STD_LOGIC;
  signal p_0_in7_in : STD_LOGIC;
  signal p_0_in88_in : STD_LOGIC;
  signal p_0_in91_in : STD_LOGIC;
  signal p_0_in94_in : STD_LOGIC;
  signal p_0_in97_in : STD_LOGIC;
  signal \p_0_in__0\ : STD_LOGIC_VECTOR ( 5 downto 2 );
  signal \p_0_in__1\ : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal \p_0_in__10\ : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal \p_0_in__2\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \p_0_in__3\ : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal \p_0_in__4\ : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal \p_0_in__5\ : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal \p_0_in__6\ : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal \p_0_in__7\ : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal \p_0_in__8\ : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal \p_0_in__9\ : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal p_12_in : STD_LOGIC;
  signal p_139_out : STD_LOGIC;
  signal p_13_in : STD_LOGIC;
  signal p_14_in : STD_LOGIC;
  signal p_165_out : STD_LOGIC;
  signal p_190_out : STD_LOGIC;
  signal p_1_in11_in : STD_LOGIC;
  signal p_1_in138_in : STD_LOGIC;
  signal p_1_in14_in : STD_LOGIC;
  signal p_1_in164_in : STD_LOGIC;
  signal p_1_in17_in : STD_LOGIC;
  signal p_1_in189_in : STD_LOGIC;
  signal p_1_in214_in : STD_LOGIC;
  signal p_1_in239_in : STD_LOGIC;
  signal p_1_in264_in : STD_LOGIC;
  signal p_1_in26_in : STD_LOGIC;
  signal p_1_in289_in : STD_LOGIC;
  signal p_1_in2_in : STD_LOGIC;
  signal p_1_in314_in : STD_LOGIC;
  signal p_1_in339_in : STD_LOGIC;
  signal p_1_in364_in : STD_LOGIC;
  signal p_1_in389_in : STD_LOGIC;
  signal p_1_in414_in : STD_LOGIC;
  signal p_1_in439_in : STD_LOGIC;
  signal p_1_in464_in : STD_LOGIC;
  signal p_1_in5_in : STD_LOGIC;
  signal p_1_in8_in : STD_LOGIC;
  signal p_215_out : STD_LOGIC;
  signal p_240_out : STD_LOGIC;
  signal p_265_out : STD_LOGIC;
  signal p_27_in : STD_LOGIC;
  signal p_290_out : STD_LOGIC;
  signal p_2_in : STD_LOGIC;
  signal p_2_in158_in : STD_LOGIC;
  signal p_2_in183_in : STD_LOGIC;
  signal p_2_in208_in : STD_LOGIC;
  signal p_2_in233_in : STD_LOGIC;
  signal p_2_in258_in : STD_LOGIC;
  signal p_2_in283_in : STD_LOGIC;
  signal p_2_in308_in : STD_LOGIC;
  signal p_2_in333_in : STD_LOGIC;
  signal p_2_in358_in : STD_LOGIC;
  signal p_2_in383_in : STD_LOGIC;
  signal p_2_in408_in : STD_LOGIC;
  signal p_2_in433_in : STD_LOGIC;
  signal p_2_in458_in : STD_LOGIC;
  signal p_315_out : STD_LOGIC;
  signal p_340_out : STD_LOGIC;
  signal p_34_in : STD_LOGIC;
  signal p_365_out : STD_LOGIC;
  signal p_390_out : STD_LOGIC;
  signal p_3_in136_in : STD_LOGIC;
  signal p_3_in159_in : STD_LOGIC;
  signal p_3_in184_in : STD_LOGIC;
  signal p_3_in209_in : STD_LOGIC;
  signal p_3_in234_in : STD_LOGIC;
  signal p_3_in259_in : STD_LOGIC;
  signal p_3_in284_in : STD_LOGIC;
  signal p_3_in309_in : STD_LOGIC;
  signal p_3_in334_in : STD_LOGIC;
  signal p_3_in359_in : STD_LOGIC;
  signal p_3_in384_in : STD_LOGIC;
  signal p_3_in409_in : STD_LOGIC;
  signal p_3_in434_in : STD_LOGIC;
  signal p_3_in459_in : STD_LOGIC;
  signal p_415_out : STD_LOGIC;
  signal p_440_out : STD_LOGIC;
  signal p_465_out : STD_LOGIC;
  signal p_490_out : STD_LOGIC;
  signal p_4_in160_in : STD_LOGIC;
  signal p_4_in185_in : STD_LOGIC;
  signal p_4_in210_in : STD_LOGIC;
  signal p_4_in235_in : STD_LOGIC;
  signal p_4_in260_in : STD_LOGIC;
  signal p_4_in285_in : STD_LOGIC;
  signal p_4_in310_in : STD_LOGIC;
  signal p_4_in335_in : STD_LOGIC;
  signal p_4_in360_in : STD_LOGIC;
  signal p_4_in385_in : STD_LOGIC;
  signal p_4_in410_in : STD_LOGIC;
  signal p_4_in435_in : STD_LOGIC;
  signal p_4_in460_in : STD_LOGIC;
  signal p_515_out : STD_LOGIC;
  signal p_5_in161_in : STD_LOGIC;
  signal p_5_in186_in : STD_LOGIC;
  signal p_5_in211_in : STD_LOGIC;
  signal p_5_in236_in : STD_LOGIC;
  signal p_5_in261_in : STD_LOGIC;
  signal p_5_in286_in : STD_LOGIC;
  signal p_5_in311_in : STD_LOGIC;
  signal p_5_in336_in : STD_LOGIC;
  signal p_5_in361_in : STD_LOGIC;
  signal p_5_in386_in : STD_LOGIC;
  signal p_5_in411_in : STD_LOGIC;
  signal p_5_in436_in : STD_LOGIC;
  signal p_5_in461_in : STD_LOGIC;
  signal p_6_in137_in : STD_LOGIC;
  signal p_6_in162_in : STD_LOGIC;
  signal p_6_in187_in : STD_LOGIC;
  signal p_6_in212_in : STD_LOGIC;
  signal p_6_in237_in : STD_LOGIC;
  signal p_6_in262_in : STD_LOGIC;
  signal p_6_in287_in : STD_LOGIC;
  signal p_6_in312_in : STD_LOGIC;
  signal p_6_in337_in : STD_LOGIC;
  signal p_6_in362_in : STD_LOGIC;
  signal p_6_in387_in : STD_LOGIC;
  signal p_6_in412_in : STD_LOGIC;
  signal p_6_in437_in : STD_LOGIC;
  signal p_6_in462_in : STD_LOGIC;
  signal p_7_in : STD_LOGIC;
  signal p_7_in163_in : STD_LOGIC;
  signal p_7_in188_in : STD_LOGIC;
  signal p_7_in213_in : STD_LOGIC;
  signal p_7_in238_in : STD_LOGIC;
  signal p_7_in263_in : STD_LOGIC;
  signal p_7_in288_in : STD_LOGIC;
  signal p_7_in313_in : STD_LOGIC;
  signal p_7_in338_in : STD_LOGIC;
  signal p_7_in363_in : STD_LOGIC;
  signal p_7_in388_in : STD_LOGIC;
  signal p_7_in413_in : STD_LOGIC;
  signal p_7_in438_in : STD_LOGIC;
  signal p_7_in463_in : STD_LOGIC;
  signal p_8_in : STD_LOGIC;
  signal p_9_in : STD_LOGIC;
  signal pat0_data_match_r0 : STD_LOGIC;
  signal pat0_match_fall0_and_r : STD_LOGIC;
  signal pat0_match_fall0_r : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal pat0_match_fall1_and_r : STD_LOGIC;
  signal pat0_match_fall1_r : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal pat0_match_fall2_and_r : STD_LOGIC;
  signal pat0_match_fall2_r : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal pat0_match_fall3_and_r : STD_LOGIC;
  signal pat0_match_fall3_r : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal pat0_match_rise0_and_r : STD_LOGIC;
  signal pat0_match_rise0_r : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal pat0_match_rise1_and_r : STD_LOGIC;
  signal pat0_match_rise1_r : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal pat0_match_rise2_and_r : STD_LOGIC;
  signal pat0_match_rise2_r : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal pat0_match_rise3_and_r : STD_LOGIC;
  signal pat0_match_rise3_r : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal pat1_data_match_r0 : STD_LOGIC;
  signal pat1_match_fall0_and_r : STD_LOGIC;
  signal pat1_match_fall1_and_r : STD_LOGIC;
  signal pat1_match_fall2_and_r : STD_LOGIC;
  signal pat1_match_fall3_and_r : STD_LOGIC;
  signal pat1_match_rise0_and_r : STD_LOGIC;
  signal pat1_match_rise1_and_r : STD_LOGIC;
  signal pat1_match_rise2_and_r : STD_LOGIC;
  signal pat1_match_rise3_and_r : STD_LOGIC;
  signal pb_cnt_eye_size_r : STD_LOGIC;
  signal pb_detect_edge : STD_LOGIC;
  signal pb_detect_edge_done_r : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal pb_found_stable_eye_r : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal pi_cnt_dec_i_1_n_0 : STD_LOGIC;
  signal pi_cnt_dec_i_2_n_0 : STD_LOGIC;
  signal \^pi_cnt_dec_reg_0\ : STD_LOGIC;
  signal pi_en_stg2_f_timing : STD_LOGIC;
  signal pi_en_stg2_f_timing_i_1_n_0 : STD_LOGIC;
  signal \^pi_fine_dly_dec_done\ : STD_LOGIC;
  signal pi_rdval_cnt : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal \pi_rdval_cnt[0]_i_1_n_0\ : STD_LOGIC;
  signal \pi_rdval_cnt[1]_i_1_n_0\ : STD_LOGIC;
  signal \pi_rdval_cnt[2]_i_1_n_0\ : STD_LOGIC;
  signal \pi_rdval_cnt[3]_i_1_n_0\ : STD_LOGIC;
  signal \pi_rdval_cnt[3]_i_2_n_0\ : STD_LOGIC;
  signal \pi_rdval_cnt[3]_i_3_n_0\ : STD_LOGIC;
  signal \pi_rdval_cnt[4]_i_1_n_0\ : STD_LOGIC;
  signal \pi_rdval_cnt[5]_i_1_n_0\ : STD_LOGIC;
  signal \pi_rdval_cnt[5]_i_2_n_0\ : STD_LOGIC;
  signal \pi_rdval_cnt[5]_i_3_n_0\ : STD_LOGIC;
  signal \pi_rdval_cnt[5]_i_4_n_0\ : STD_LOGIC;
  signal pi_stg2_f_incdec_timing : STD_LOGIC;
  signal pi_stg2_f_incdec_timing_i_1_n_0 : STD_LOGIC;
  signal pi_stg2_load_timing : STD_LOGIC;
  signal pi_stg2_load_timing_i_1_n_0 : STD_LOGIC;
  signal pi_stg2_rdlvl_cnt : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal pi_stg2_reg_l_timing : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal \pi_stg2_reg_l_timing[0]_i_2_n_0\ : STD_LOGIC;
  signal \pi_stg2_reg_l_timing[0]_i_3_n_0\ : STD_LOGIC;
  signal \pi_stg2_reg_l_timing[1]_i_2_n_0\ : STD_LOGIC;
  signal \pi_stg2_reg_l_timing[1]_i_3_n_0\ : STD_LOGIC;
  signal \pi_stg2_reg_l_timing[2]_i_2_n_0\ : STD_LOGIC;
  signal \pi_stg2_reg_l_timing[2]_i_3_n_0\ : STD_LOGIC;
  signal \pi_stg2_reg_l_timing[3]_i_2_n_0\ : STD_LOGIC;
  signal \pi_stg2_reg_l_timing[3]_i_3_n_0\ : STD_LOGIC;
  signal \pi_stg2_reg_l_timing[4]_i_2_n_0\ : STD_LOGIC;
  signal \pi_stg2_reg_l_timing[4]_i_3_n_0\ : STD_LOGIC;
  signal \pi_stg2_reg_l_timing[5]_i_1_n_0\ : STD_LOGIC;
  signal \pi_stg2_reg_l_timing[5]_i_3_n_0\ : STD_LOGIC;
  signal \pi_stg2_reg_l_timing[5]_i_4_n_0\ : STD_LOGIC;
  signal \pi_stg2_reg_l_timing[5]_i_5_n_0\ : STD_LOGIC;
  signal \rd_mux_sel_r_reg_n_0_[2]\ : STD_LOGIC;
  signal rdlvl_dqs_tap_cnt_r : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal \rdlvl_dqs_tap_cnt_r[0][0][5]_i_1_n_0\ : STD_LOGIC;
  signal \rdlvl_dqs_tap_cnt_r[0][0][5]_i_2_n_0\ : STD_LOGIC;
  signal \rdlvl_dqs_tap_cnt_r[0][1][5]_i_1_n_0\ : STD_LOGIC;
  signal \rdlvl_dqs_tap_cnt_r[0][2][5]_i_1_n_0\ : STD_LOGIC;
  signal \rdlvl_dqs_tap_cnt_r[0][3][5]_i_1_n_0\ : STD_LOGIC;
  signal \rdlvl_dqs_tap_cnt_r[0][4][5]_i_1_n_0\ : STD_LOGIC;
  signal \rdlvl_dqs_tap_cnt_r[0][5][5]_i_1_n_0\ : STD_LOGIC;
  signal \rdlvl_dqs_tap_cnt_r[0][6][5]_i_1_n_0\ : STD_LOGIC;
  signal \rdlvl_dqs_tap_cnt_r[0][7][5]_i_1_n_0\ : STD_LOGIC;
  signal \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][0][0]\ : STD_LOGIC;
  signal \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][0][1]\ : STD_LOGIC;
  signal \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][0][2]\ : STD_LOGIC;
  signal \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][0][3]\ : STD_LOGIC;
  signal \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][0][4]\ : STD_LOGIC;
  signal \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][0][5]\ : STD_LOGIC;
  signal \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][1][0]\ : STD_LOGIC;
  signal \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][1][1]\ : STD_LOGIC;
  signal \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][1][2]\ : STD_LOGIC;
  signal \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][1][3]\ : STD_LOGIC;
  signal \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][1][4]\ : STD_LOGIC;
  signal \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][1][5]\ : STD_LOGIC;
  signal \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][2][0]\ : STD_LOGIC;
  signal \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][2][1]\ : STD_LOGIC;
  signal \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][2][2]\ : STD_LOGIC;
  signal \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][2][3]\ : STD_LOGIC;
  signal \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][2][4]\ : STD_LOGIC;
  signal \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][2][5]\ : STD_LOGIC;
  signal \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][3][0]\ : STD_LOGIC;
  signal \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][3][1]\ : STD_LOGIC;
  signal \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][3][2]\ : STD_LOGIC;
  signal \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][3][3]\ : STD_LOGIC;
  signal \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][3][4]\ : STD_LOGIC;
  signal \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][3][5]\ : STD_LOGIC;
  signal \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][4][0]\ : STD_LOGIC;
  signal \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][4][1]\ : STD_LOGIC;
  signal \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][4][2]\ : STD_LOGIC;
  signal \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][4][3]\ : STD_LOGIC;
  signal \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][4][4]\ : STD_LOGIC;
  signal \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][4][5]\ : STD_LOGIC;
  signal \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][5][0]\ : STD_LOGIC;
  signal \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][5][1]\ : STD_LOGIC;
  signal \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][5][2]\ : STD_LOGIC;
  signal \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][5][3]\ : STD_LOGIC;
  signal \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][5][4]\ : STD_LOGIC;
  signal \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][5][5]\ : STD_LOGIC;
  signal \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][6][0]\ : STD_LOGIC;
  signal \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][6][1]\ : STD_LOGIC;
  signal \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][6][2]\ : STD_LOGIC;
  signal \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][6][3]\ : STD_LOGIC;
  signal \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][6][4]\ : STD_LOGIC;
  signal \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][6][5]\ : STD_LOGIC;
  signal \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][7][0]\ : STD_LOGIC;
  signal \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][7][1]\ : STD_LOGIC;
  signal \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][7][2]\ : STD_LOGIC;
  signal \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][7][3]\ : STD_LOGIC;
  signal \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][7][4]\ : STD_LOGIC;
  signal \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][7][5]\ : STD_LOGIC;
  signal \^rdlvl_last_byte_done\ : STD_LOGIC;
  signal rdlvl_last_byte_done_int_i_1_n_0 : STD_LOGIC;
  signal \^rdlvl_pi_incdec\ : STD_LOGIC;
  signal rdlvl_pi_incdec_i_1_n_0 : STD_LOGIC;
  signal rdlvl_pi_incdec_i_2_n_0 : STD_LOGIC;
  signal rdlvl_pi_incdec_i_3_n_0 : STD_LOGIC;
  signal rdlvl_pi_incdec_i_4_n_0 : STD_LOGIC;
  signal rdlvl_pi_incdec_i_5_n_0 : STD_LOGIC;
  signal \^rdlvl_prech_req\ : STD_LOGIC;
  signal rdlvl_rank_done_r_i_1_n_0 : STD_LOGIC;
  signal rdlvl_rank_done_r_i_2_n_0 : STD_LOGIC;
  signal rdlvl_rank_done_r_i_3_n_0 : STD_LOGIC;
  signal rdlvl_stg1_done_int : STD_LOGIC;
  signal rdlvl_stg1_done_int_i_1_n_0 : STD_LOGIC;
  signal \^rdlvl_stg1_done_int_reg_0\ : STD_LOGIC;
  signal \^rdlvl_stg1_rank_done\ : STD_LOGIC;
  signal rdlvl_stg1_start_r : STD_LOGIC;
  signal regl_dqs_cnt : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \regl_dqs_cnt[0]_i_1_n_0\ : STD_LOGIC;
  signal \regl_dqs_cnt[1]_i_1_n_0\ : STD_LOGIC;
  signal \regl_dqs_cnt[2]_i_1_n_0\ : STD_LOGIC;
  signal \regl_dqs_cnt[3]_i_1_n_0\ : STD_LOGIC;
  signal regl_dqs_cnt_r : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal regl_rank_cnt : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal regl_rank_cnt0 : STD_LOGIC;
  signal \regl_rank_cnt[0]_i_1_n_0\ : STD_LOGIC;
  signal \regl_rank_cnt[1]_i_1_n_0\ : STD_LOGIC;
  signal \regl_rank_cnt[1]_i_3_n_0\ : STD_LOGIC;
  signal right_edge_taps_r : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal \right_edge_taps_r[5]_i_1_n_0\ : STD_LOGIC;
  signal \right_edge_taps_r_reg_n_0_[0]\ : STD_LOGIC;
  signal \right_edge_taps_r_reg_n_0_[1]\ : STD_LOGIC;
  signal \right_edge_taps_r_reg_n_0_[2]\ : STD_LOGIC;
  signal \right_edge_taps_r_reg_n_0_[3]\ : STD_LOGIC;
  signal \right_edge_taps_r_reg_n_0_[4]\ : STD_LOGIC;
  signal \right_edge_taps_r_reg_n_0_[5]\ : STD_LOGIC;
  signal \rnk_cnt_r[0]_i_1__0_n_0\ : STD_LOGIC;
  signal \rnk_cnt_r[1]_i_1__0_n_0\ : STD_LOGIC;
  signal \rnk_cnt_r[1]_i_2_n_0\ : STD_LOGIC;
  signal \rnk_cnt_r_reg_n_0_[0]\ : STD_LOGIC;
  signal \rnk_cnt_r_reg_n_0_[1]\ : STD_LOGIC;
  signal samp_cnt_done_r_i_1_n_0 : STD_LOGIC;
  signal samp_cnt_done_r_i_2_n_0 : STD_LOGIC;
  signal samp_cnt_done_r_i_3_n_0 : STD_LOGIC;
  signal samp_cnt_done_r_i_4_n_0 : STD_LOGIC;
  signal samp_cnt_done_r_reg_n_0 : STD_LOGIC;
  signal \^samp_edge_cnt0_en_r\ : STD_LOGIC;
  signal \samp_edge_cnt0_r[0]_i_3_n_0\ : STD_LOGIC;
  signal samp_edge_cnt0_r_reg : STD_LOGIC_VECTOR ( 11 downto 0 );
  signal \samp_edge_cnt0_r_reg[0]_i_2_n_0\ : STD_LOGIC;
  signal \samp_edge_cnt0_r_reg[0]_i_2_n_1\ : STD_LOGIC;
  signal \samp_edge_cnt0_r_reg[0]_i_2_n_2\ : STD_LOGIC;
  signal \samp_edge_cnt0_r_reg[0]_i_2_n_3\ : STD_LOGIC;
  signal \samp_edge_cnt0_r_reg[0]_i_2_n_4\ : STD_LOGIC;
  signal \samp_edge_cnt0_r_reg[0]_i_2_n_5\ : STD_LOGIC;
  signal \samp_edge_cnt0_r_reg[0]_i_2_n_6\ : STD_LOGIC;
  signal \samp_edge_cnt0_r_reg[0]_i_2_n_7\ : STD_LOGIC;
  signal \samp_edge_cnt0_r_reg[4]_i_1_n_0\ : STD_LOGIC;
  signal \samp_edge_cnt0_r_reg[4]_i_1_n_1\ : STD_LOGIC;
  signal \samp_edge_cnt0_r_reg[4]_i_1_n_2\ : STD_LOGIC;
  signal \samp_edge_cnt0_r_reg[4]_i_1_n_3\ : STD_LOGIC;
  signal \samp_edge_cnt0_r_reg[4]_i_1_n_4\ : STD_LOGIC;
  signal \samp_edge_cnt0_r_reg[4]_i_1_n_5\ : STD_LOGIC;
  signal \samp_edge_cnt0_r_reg[4]_i_1_n_6\ : STD_LOGIC;
  signal \samp_edge_cnt0_r_reg[4]_i_1_n_7\ : STD_LOGIC;
  signal \samp_edge_cnt0_r_reg[8]_i_1_n_1\ : STD_LOGIC;
  signal \samp_edge_cnt0_r_reg[8]_i_1_n_2\ : STD_LOGIC;
  signal \samp_edge_cnt0_r_reg[8]_i_1_n_3\ : STD_LOGIC;
  signal \samp_edge_cnt0_r_reg[8]_i_1_n_4\ : STD_LOGIC;
  signal \samp_edge_cnt0_r_reg[8]_i_1_n_5\ : STD_LOGIC;
  signal \samp_edge_cnt0_r_reg[8]_i_1_n_6\ : STD_LOGIC;
  signal \samp_edge_cnt0_r_reg[8]_i_1_n_7\ : STD_LOGIC;
  signal samp_edge_cnt1_en_r : STD_LOGIC;
  signal samp_edge_cnt1_en_r0 : STD_LOGIC;
  signal samp_edge_cnt1_en_r_i_2_n_0 : STD_LOGIC;
  signal samp_edge_cnt1_en_r_i_3_n_0 : STD_LOGIC;
  signal \samp_edge_cnt1_r[0]_i_2_n_0\ : STD_LOGIC;
  signal samp_edge_cnt1_r_reg : STD_LOGIC_VECTOR ( 11 downto 0 );
  signal \samp_edge_cnt1_r_reg[0]_i_1_n_0\ : STD_LOGIC;
  signal \samp_edge_cnt1_r_reg[0]_i_1_n_1\ : STD_LOGIC;
  signal \samp_edge_cnt1_r_reg[0]_i_1_n_2\ : STD_LOGIC;
  signal \samp_edge_cnt1_r_reg[0]_i_1_n_3\ : STD_LOGIC;
  signal \samp_edge_cnt1_r_reg[0]_i_1_n_4\ : STD_LOGIC;
  signal \samp_edge_cnt1_r_reg[0]_i_1_n_5\ : STD_LOGIC;
  signal \samp_edge_cnt1_r_reg[0]_i_1_n_6\ : STD_LOGIC;
  signal \samp_edge_cnt1_r_reg[0]_i_1_n_7\ : STD_LOGIC;
  signal \samp_edge_cnt1_r_reg[4]_i_1_n_0\ : STD_LOGIC;
  signal \samp_edge_cnt1_r_reg[4]_i_1_n_1\ : STD_LOGIC;
  signal \samp_edge_cnt1_r_reg[4]_i_1_n_2\ : STD_LOGIC;
  signal \samp_edge_cnt1_r_reg[4]_i_1_n_3\ : STD_LOGIC;
  signal \samp_edge_cnt1_r_reg[4]_i_1_n_4\ : STD_LOGIC;
  signal \samp_edge_cnt1_r_reg[4]_i_1_n_5\ : STD_LOGIC;
  signal \samp_edge_cnt1_r_reg[4]_i_1_n_6\ : STD_LOGIC;
  signal \samp_edge_cnt1_r_reg[4]_i_1_n_7\ : STD_LOGIC;
  signal \samp_edge_cnt1_r_reg[8]_i_1_n_1\ : STD_LOGIC;
  signal \samp_edge_cnt1_r_reg[8]_i_1_n_2\ : STD_LOGIC;
  signal \samp_edge_cnt1_r_reg[8]_i_1_n_3\ : STD_LOGIC;
  signal \samp_edge_cnt1_r_reg[8]_i_1_n_4\ : STD_LOGIC;
  signal \samp_edge_cnt1_r_reg[8]_i_1_n_5\ : STD_LOGIC;
  signal \samp_edge_cnt1_r_reg[8]_i_1_n_6\ : STD_LOGIC;
  signal \samp_edge_cnt1_r_reg[8]_i_1_n_7\ : STD_LOGIC;
  signal \second_edge_taps_r[1]_i_1_n_0\ : STD_LOGIC;
  signal \second_edge_taps_r[2]_i_1_n_0\ : STD_LOGIC;
  signal \second_edge_taps_r[3]_i_1_n_0\ : STD_LOGIC;
  signal \second_edge_taps_r[4]_i_1_n_0\ : STD_LOGIC;
  signal \second_edge_taps_r[5]_i_1_n_0\ : STD_LOGIC;
  signal \second_edge_taps_r[5]_i_2_n_0\ : STD_LOGIC;
  signal \second_edge_taps_r[5]_i_3_n_0\ : STD_LOGIC;
  signal \second_edge_taps_r_reg_n_0_[0]\ : STD_LOGIC;
  signal \second_edge_taps_r_reg_n_0_[1]\ : STD_LOGIC;
  signal \second_edge_taps_r_reg_n_0_[2]\ : STD_LOGIC;
  signal \second_edge_taps_r_reg_n_0_[3]\ : STD_LOGIC;
  signal \second_edge_taps_r_reg_n_0_[4]\ : STD_LOGIC;
  signal \second_edge_taps_r_reg_n_0_[5]\ : STD_LOGIC;
  signal sr_valid_r1 : STD_LOGIC;
  signal sr_valid_r2 : STD_LOGIC;
  signal sr_valid_r_i_1_n_0 : STD_LOGIC;
  signal sr_valid_r_reg_n_0 : STD_LOGIC;
  signal stable_idel_cnt : STD_LOGIC;
  signal stable_idel_cnt0 : STD_LOGIC;
  signal store_sr_r0 : STD_LOGIC;
  signal store_sr_r_i_1_n_0 : STD_LOGIC;
  signal store_sr_r_reg_n_0 : STD_LOGIC;
  signal store_sr_req_pulsed_r : STD_LOGIC;
  signal \store_sr_req_pulsed_r__0\ : STD_LOGIC;
  signal store_sr_req_r : STD_LOGIC;
  signal store_sr_req_r_i_2_n_0 : STD_LOGIC;
  signal store_sr_req_r_reg_n_0 : STD_LOGIC;
  signal tap_cnt_cpt_r : STD_LOGIC;
  signal tap_cnt_cpt_r0 : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \tap_cnt_cpt_r[1]_i_1_n_0\ : STD_LOGIC;
  signal \tap_cnt_cpt_r[5]_i_4_n_0\ : STD_LOGIC;
  signal \tap_cnt_cpt_r[5]_i_5_n_0\ : STD_LOGIC;
  signal \tap_cnt_cpt_r[5]_i_6_n_0\ : STD_LOGIC;
  signal \tap_cnt_cpt_r_reg_n_0_[0]\ : STD_LOGIC;
  signal \tap_cnt_cpt_r_reg_n_0_[1]\ : STD_LOGIC;
  signal \tap_cnt_cpt_r_reg_n_0_[2]\ : STD_LOGIC;
  signal \tap_cnt_cpt_r_reg_n_0_[3]\ : STD_LOGIC;
  signal \tap_cnt_cpt_r_reg_n_0_[4]\ : STD_LOGIC;
  signal \tap_cnt_cpt_r_reg_n_0_[5]\ : STD_LOGIC;
  signal tap_limit_cpt_r : STD_LOGIC;
  signal tap_limit_cpt_r_i_1_n_0 : STD_LOGIC;
  signal tap_limit_cpt_r_i_2_n_0 : STD_LOGIC;
  signal wait_cnt_r0 : STD_LOGIC;
  signal \wait_cnt_r0__0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \wait_cnt_r[1]_i_1__0_n_0\ : STD_LOGIC;
  signal wait_cnt_r_reg : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \NLW_cnt_idel_dec_cpt_r_reg[2]_i_10_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \NLW_cnt_idel_dec_cpt_r_reg[2]_i_2_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \NLW_cnt_idel_dec_cpt_r_reg[4]_i_2_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
  signal \NLW_cnt_idel_dec_cpt_r_reg[4]_i_2_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
  signal \NLW_cnt_idel_dec_cpt_r_reg[4]_i_8_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
  signal \NLW_cnt_idel_dec_cpt_r_reg[4]_i_8_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
  signal \NLW_samp_edge_cnt0_r_reg[8]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
  signal \NLW_samp_edge_cnt1_r_reg[8]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \FSM_onehot_cal1_state_r[10]_i_1\ : label is "soft_lutpair104";
  attribute SOFT_HLUTNM of \FSM_onehot_cal1_state_r[11]_i_1\ : label is "soft_lutpair107";
  attribute SOFT_HLUTNM of \FSM_onehot_cal1_state_r[13]_i_1\ : label is "soft_lutpair117";
  attribute SOFT_HLUTNM of \FSM_onehot_cal1_state_r[14]_i_1\ : label is "soft_lutpair128";
  attribute SOFT_HLUTNM of \FSM_onehot_cal1_state_r[15]_i_2\ : label is "soft_lutpair132";
  attribute SOFT_HLUTNM of \FSM_onehot_cal1_state_r[16]_i_3\ : label is "soft_lutpair109";
  attribute SOFT_HLUTNM of \FSM_onehot_cal1_state_r[16]_i_4\ : label is "soft_lutpair119";
  attribute SOFT_HLUTNM of \FSM_onehot_cal1_state_r[21]_i_2\ : label is "soft_lutpair130";
  attribute SOFT_HLUTNM of \FSM_onehot_cal1_state_r[22]_i_2\ : label is "soft_lutpair110";
  attribute SOFT_HLUTNM of \FSM_onehot_cal1_state_r[29]_i_1\ : label is "soft_lutpair107";
  attribute SOFT_HLUTNM of \FSM_onehot_cal1_state_r[34]_i_11\ : label is "soft_lutpair128";
  attribute SOFT_HLUTNM of \FSM_onehot_cal1_state_r[34]_i_13\ : label is "soft_lutpair112";
  attribute SOFT_HLUTNM of \FSM_onehot_cal1_state_r[34]_i_2\ : label is "soft_lutpair123";
  attribute SOFT_HLUTNM of \FSM_onehot_cal1_state_r[34]_i_4\ : label is "soft_lutpair82";
  attribute SOFT_HLUTNM of \FSM_onehot_cal1_state_r[34]_i_7\ : label is "soft_lutpair102";
  attribute SOFT_HLUTNM of \FSM_onehot_cal1_state_r[34]_i_8\ : label is "soft_lutpair108";
  attribute SOFT_HLUTNM of \FSM_onehot_cal1_state_r[4]_i_1\ : label is "soft_lutpair132";
  attribute SOFT_HLUTNM of \FSM_onehot_cal1_state_r[5]_i_1\ : label is "soft_lutpair100";
  attribute SOFT_HLUTNM of \FSM_onehot_cal1_state_r[5]_i_2\ : label is "soft_lutpair97";
  attribute SOFT_HLUTNM of \FSM_onehot_cal1_state_r[5]_i_3\ : label is "soft_lutpair88";
  attribute SOFT_HLUTNM of \FSM_onehot_cal1_state_r[6]_i_2\ : label is "soft_lutpair100";
  attribute SOFT_HLUTNM of \FSM_onehot_cal1_state_r[6]_i_3\ : label is "soft_lutpair218";
  attribute SOFT_HLUTNM of \FSM_onehot_cal1_state_r[8]_i_1\ : label is "soft_lutpair121";
  attribute SOFT_HLUTNM of \FSM_onehot_cal1_state_r[9]_i_1\ : label is "soft_lutpair210";
  attribute FSM_ENCODED_STATES : string;
  attribute FSM_ENCODED_STATES of \FSM_onehot_cal1_state_r_reg[0]\ : label is "CAL1_STORE_FIRST_WAIT:00000000000000000010000000000000000,CAL1_NEW_DQS_WAIT:00000000000000000000010000000000000,CAL1_IDLE:00000000000000000000000000010000000,CAL1_REGL_LOAD:00000000000000000000000000001000000,CAL1_PB_INC_DQ:00000001000000000000000000000000000,CAL1_PB_DEC_CPT_WAIT:00000000100000000000000000000000000,CAL1_CENTER_WAIT:00000000000000000000000000000000001,CAL1_PB_DETECT_EDGE_DQ:00001000000000000000000000000000000,CAL1_PB_DEC_CPT:00000000001000000000000000000000000,CAL1_PB_DEC_CPT_LEFT_WAIT:01000000000000000000000000000000000,CAL1_PB_INC_DQ_WAIT:00000010000000000000000000000000000,CAL1_RD_STOP_FOR_PI_INC:00000000000000000000000100000000000,CAL1_DONE:00000000000000000000000000000100000,CAL1_PB_DEC_CPT_LEFT:00000000000100000000000000000000000,CAL1_NEW_DQS_PREWAIT:00000000000000000000000000100000000,CAL1_NEXT_DQS:00000000000000000000000000000010000,CAL1_IDEL_DEC_CPT_WAIT:00000000000000000000100000000000000,CAL1_IDEL_DEC_CPT:00000000000000000000000000000000010,CAL1_PB_INC_CPT_WAIT:00000000000000000100000000000000000,CAL1_PB_INC_CPT:00000000000000010000000000000000000,CAL1_CALC_IDEL:00000100000000000000000000000000000,CAL1_PB_DETECT_EDGE:00000000000000001000000000000000000,CAL1_DQ_IDEL_TAP_DEC_WAIT:00100000000000000000000000000000000,CAL1_IDEL_INC_CPT_WAIT:00010000000000000000000000000000000,CAL1_PB_STORE_FIRST_WAIT:00000000010000000000000000000000000,CAL1_DQ_IDEL_TAP_DEC:00000000000000000001000000000000000,CAL1_IDEL_INC_CPT:00000000000000000000001000000000000,CAL1_DQ_IDEL_TAP_INC_WAIT:00000000000000000000000000000001000,CAL1_DETECT_EDGE:00000000000001000000000000000000000,CAL1_DQ_IDEL_TAP_INC:00000000000000000000000000000000100,CAL1_MPR_PAT_DETECT:00000000000000000000000010000000000,CAL1_VALID_WAIT:10000000000000000000000000000000000,CAL1_MPR_NEW_DQS_WAIT:00000000000000000000000001000000000,CAL1_RDLVL_ERR:00000000000010000000000000000000000,CAL1_PAT_DETECT:00000000000000100000000000000000000";
  attribute FSM_ENCODED_STATES of \FSM_onehot_cal1_state_r_reg[10]\ : label is "CAL1_STORE_FIRST_WAIT:00000000000000000010000000000000000,CAL1_NEW_DQS_WAIT:00000000000000000000010000000000000,CAL1_IDLE:00000000000000000000000000010000000,CAL1_REGL_LOAD:00000000000000000000000000001000000,CAL1_PB_INC_DQ:00000001000000000000000000000000000,CAL1_PB_DEC_CPT_WAIT:00000000100000000000000000000000000,CAL1_CENTER_WAIT:00000000000000000000000000000000001,CAL1_PB_DETECT_EDGE_DQ:00001000000000000000000000000000000,CAL1_PB_DEC_CPT:00000000001000000000000000000000000,CAL1_PB_DEC_CPT_LEFT_WAIT:01000000000000000000000000000000000,CAL1_PB_INC_DQ_WAIT:00000010000000000000000000000000000,CAL1_RD_STOP_FOR_PI_INC:00000000000000000000000100000000000,CAL1_DONE:00000000000000000000000000000100000,CAL1_PB_DEC_CPT_LEFT:00000000000100000000000000000000000,CAL1_NEW_DQS_PREWAIT:00000000000000000000000000100000000,CAL1_NEXT_DQS:00000000000000000000000000000010000,CAL1_IDEL_DEC_CPT_WAIT:00000000000000000000100000000000000,CAL1_IDEL_DEC_CPT:00000000000000000000000000000000010,CAL1_PB_INC_CPT_WAIT:00000000000000000100000000000000000,CAL1_PB_INC_CPT:00000000000000010000000000000000000,CAL1_CALC_IDEL:00000100000000000000000000000000000,CAL1_PB_DETECT_EDGE:00000000000000001000000000000000000,CAL1_DQ_IDEL_TAP_DEC_WAIT:00100000000000000000000000000000000,CAL1_IDEL_INC_CPT_WAIT:00010000000000000000000000000000000,CAL1_PB_STORE_FIRST_WAIT:00000000010000000000000000000000000,CAL1_DQ_IDEL_TAP_DEC:00000000000000000001000000000000000,CAL1_IDEL_INC_CPT:00000000000000000000001000000000000,CAL1_DQ_IDEL_TAP_INC_WAIT:00000000000000000000000000000001000,CAL1_DETECT_EDGE:00000000000001000000000000000000000,CAL1_DQ_IDEL_TAP_INC:00000000000000000000000000000000100,CAL1_MPR_PAT_DETECT:00000000000000000000000010000000000,CAL1_VALID_WAIT:10000000000000000000000000000000000,CAL1_MPR_NEW_DQS_WAIT:00000000000000000000000001000000000,CAL1_RDLVL_ERR:00000000000010000000000000000000000,CAL1_PAT_DETECT:00000000000000100000000000000000000";
  attribute FSM_ENCODED_STATES of \FSM_onehot_cal1_state_r_reg[11]\ : label is "CAL1_STORE_FIRST_WAIT:00000000000000000010000000000000000,CAL1_NEW_DQS_WAIT:00000000000000000000010000000000000,CAL1_IDLE:00000000000000000000000000010000000,CAL1_REGL_LOAD:00000000000000000000000000001000000,CAL1_PB_INC_DQ:00000001000000000000000000000000000,CAL1_PB_DEC_CPT_WAIT:00000000100000000000000000000000000,CAL1_CENTER_WAIT:00000000000000000000000000000000001,CAL1_PB_DETECT_EDGE_DQ:00001000000000000000000000000000000,CAL1_PB_DEC_CPT:00000000001000000000000000000000000,CAL1_PB_DEC_CPT_LEFT_WAIT:01000000000000000000000000000000000,CAL1_PB_INC_DQ_WAIT:00000010000000000000000000000000000,CAL1_RD_STOP_FOR_PI_INC:00000000000000000000000100000000000,CAL1_DONE:00000000000000000000000000000100000,CAL1_PB_DEC_CPT_LEFT:00000000000100000000000000000000000,CAL1_NEW_DQS_PREWAIT:00000000000000000000000000100000000,CAL1_NEXT_DQS:00000000000000000000000000000010000,CAL1_IDEL_DEC_CPT_WAIT:00000000000000000000100000000000000,CAL1_IDEL_DEC_CPT:00000000000000000000000000000000010,CAL1_PB_INC_CPT_WAIT:00000000000000000100000000000000000,CAL1_PB_INC_CPT:00000000000000010000000000000000000,CAL1_CALC_IDEL:00000100000000000000000000000000000,CAL1_PB_DETECT_EDGE:00000000000000001000000000000000000,CAL1_DQ_IDEL_TAP_DEC_WAIT:00100000000000000000000000000000000,CAL1_IDEL_INC_CPT_WAIT:00010000000000000000000000000000000,CAL1_PB_STORE_FIRST_WAIT:00000000010000000000000000000000000,CAL1_DQ_IDEL_TAP_DEC:00000000000000000001000000000000000,CAL1_IDEL_INC_CPT:00000000000000000000001000000000000,CAL1_DQ_IDEL_TAP_INC_WAIT:00000000000000000000000000000001000,CAL1_DETECT_EDGE:00000000000001000000000000000000000,CAL1_DQ_IDEL_TAP_INC:00000000000000000000000000000000100,CAL1_MPR_PAT_DETECT:00000000000000000000000010000000000,CAL1_VALID_WAIT:10000000000000000000000000000000000,CAL1_MPR_NEW_DQS_WAIT:00000000000000000000000001000000000,CAL1_RDLVL_ERR:00000000000010000000000000000000000,CAL1_PAT_DETECT:00000000000000100000000000000000000";
  attribute FSM_ENCODED_STATES of \FSM_onehot_cal1_state_r_reg[12]\ : label is "CAL1_STORE_FIRST_WAIT:00000000000000000010000000000000000,CAL1_NEW_DQS_WAIT:00000000000000000000010000000000000,CAL1_IDLE:00000000000000000000000000010000000,CAL1_REGL_LOAD:00000000000000000000000000001000000,CAL1_PB_INC_DQ:00000001000000000000000000000000000,CAL1_PB_DEC_CPT_WAIT:00000000100000000000000000000000000,CAL1_CENTER_WAIT:00000000000000000000000000000000001,CAL1_PB_DETECT_EDGE_DQ:00001000000000000000000000000000000,CAL1_PB_DEC_CPT:00000000001000000000000000000000000,CAL1_PB_DEC_CPT_LEFT_WAIT:01000000000000000000000000000000000,CAL1_PB_INC_DQ_WAIT:00000010000000000000000000000000000,CAL1_RD_STOP_FOR_PI_INC:00000000000000000000000100000000000,CAL1_DONE:00000000000000000000000000000100000,CAL1_PB_DEC_CPT_LEFT:00000000000100000000000000000000000,CAL1_NEW_DQS_PREWAIT:00000000000000000000000000100000000,CAL1_NEXT_DQS:00000000000000000000000000000010000,CAL1_IDEL_DEC_CPT_WAIT:00000000000000000000100000000000000,CAL1_IDEL_DEC_CPT:00000000000000000000000000000000010,CAL1_PB_INC_CPT_WAIT:00000000000000000100000000000000000,CAL1_PB_INC_CPT:00000000000000010000000000000000000,CAL1_CALC_IDEL:00000100000000000000000000000000000,CAL1_PB_DETECT_EDGE:00000000000000001000000000000000000,CAL1_DQ_IDEL_TAP_DEC_WAIT:00100000000000000000000000000000000,CAL1_IDEL_INC_CPT_WAIT:00010000000000000000000000000000000,CAL1_PB_STORE_FIRST_WAIT:00000000010000000000000000000000000,CAL1_DQ_IDEL_TAP_DEC:00000000000000000001000000000000000,CAL1_IDEL_INC_CPT:00000000000000000000001000000000000,CAL1_DQ_IDEL_TAP_INC_WAIT:00000000000000000000000000000001000,CAL1_DETECT_EDGE:00000000000001000000000000000000000,CAL1_DQ_IDEL_TAP_INC:00000000000000000000000000000000100,CAL1_MPR_PAT_DETECT:00000000000000000000000010000000000,CAL1_VALID_WAIT:10000000000000000000000000000000000,CAL1_MPR_NEW_DQS_WAIT:00000000000000000000000001000000000,CAL1_RDLVL_ERR:00000000000010000000000000000000000,CAL1_PAT_DETECT:00000000000000100000000000000000000";
  attribute FSM_ENCODED_STATES of \FSM_onehot_cal1_state_r_reg[13]\ : label is "CAL1_STORE_FIRST_WAIT:00000000000000000010000000000000000,CAL1_NEW_DQS_WAIT:00000000000000000000010000000000000,CAL1_IDLE:00000000000000000000000000010000000,CAL1_REGL_LOAD:00000000000000000000000000001000000,CAL1_PB_INC_DQ:00000001000000000000000000000000000,CAL1_PB_DEC_CPT_WAIT:00000000100000000000000000000000000,CAL1_CENTER_WAIT:00000000000000000000000000000000001,CAL1_PB_DETECT_EDGE_DQ:00001000000000000000000000000000000,CAL1_PB_DEC_CPT:00000000001000000000000000000000000,CAL1_PB_DEC_CPT_LEFT_WAIT:01000000000000000000000000000000000,CAL1_PB_INC_DQ_WAIT:00000010000000000000000000000000000,CAL1_RD_STOP_FOR_PI_INC:00000000000000000000000100000000000,CAL1_DONE:00000000000000000000000000000100000,CAL1_PB_DEC_CPT_LEFT:00000000000100000000000000000000000,CAL1_NEW_DQS_PREWAIT:00000000000000000000000000100000000,CAL1_NEXT_DQS:00000000000000000000000000000010000,CAL1_IDEL_DEC_CPT_WAIT:00000000000000000000100000000000000,CAL1_IDEL_DEC_CPT:00000000000000000000000000000000010,CAL1_PB_INC_CPT_WAIT:00000000000000000100000000000000000,CAL1_PB_INC_CPT:00000000000000010000000000000000000,CAL1_CALC_IDEL:00000100000000000000000000000000000,CAL1_PB_DETECT_EDGE:00000000000000001000000000000000000,CAL1_DQ_IDEL_TAP_DEC_WAIT:00100000000000000000000000000000000,CAL1_IDEL_INC_CPT_WAIT:00010000000000000000000000000000000,CAL1_PB_STORE_FIRST_WAIT:00000000010000000000000000000000000,CAL1_DQ_IDEL_TAP_DEC:00000000000000000001000000000000000,CAL1_IDEL_INC_CPT:00000000000000000000001000000000000,CAL1_DQ_IDEL_TAP_INC_WAIT:00000000000000000000000000000001000,CAL1_DETECT_EDGE:00000000000001000000000000000000000,CAL1_DQ_IDEL_TAP_INC:00000000000000000000000000000000100,CAL1_MPR_PAT_DETECT:00000000000000000000000010000000000,CAL1_VALID_WAIT:10000000000000000000000000000000000,CAL1_MPR_NEW_DQS_WAIT:00000000000000000000000001000000000,CAL1_RDLVL_ERR:00000000000010000000000000000000000,CAL1_PAT_DETECT:00000000000000100000000000000000000";
  attribute FSM_ENCODED_STATES of \FSM_onehot_cal1_state_r_reg[14]\ : label is "CAL1_STORE_FIRST_WAIT:00000000000000000010000000000000000,CAL1_NEW_DQS_WAIT:00000000000000000000010000000000000,CAL1_IDLE:00000000000000000000000000010000000,CAL1_REGL_LOAD:00000000000000000000000000001000000,CAL1_PB_INC_DQ:00000001000000000000000000000000000,CAL1_PB_DEC_CPT_WAIT:00000000100000000000000000000000000,CAL1_CENTER_WAIT:00000000000000000000000000000000001,CAL1_PB_DETECT_EDGE_DQ:00001000000000000000000000000000000,CAL1_PB_DEC_CPT:00000000001000000000000000000000000,CAL1_PB_DEC_CPT_LEFT_WAIT:01000000000000000000000000000000000,CAL1_PB_INC_DQ_WAIT:00000010000000000000000000000000000,CAL1_RD_STOP_FOR_PI_INC:00000000000000000000000100000000000,CAL1_DONE:00000000000000000000000000000100000,CAL1_PB_DEC_CPT_LEFT:00000000000100000000000000000000000,CAL1_NEW_DQS_PREWAIT:00000000000000000000000000100000000,CAL1_NEXT_DQS:00000000000000000000000000000010000,CAL1_IDEL_DEC_CPT_WAIT:00000000000000000000100000000000000,CAL1_IDEL_DEC_CPT:00000000000000000000000000000000010,CAL1_PB_INC_CPT_WAIT:00000000000000000100000000000000000,CAL1_PB_INC_CPT:00000000000000010000000000000000000,CAL1_CALC_IDEL:00000100000000000000000000000000000,CAL1_PB_DETECT_EDGE:00000000000000001000000000000000000,CAL1_DQ_IDEL_TAP_DEC_WAIT:00100000000000000000000000000000000,CAL1_IDEL_INC_CPT_WAIT:00010000000000000000000000000000000,CAL1_PB_STORE_FIRST_WAIT:00000000010000000000000000000000000,CAL1_DQ_IDEL_TAP_DEC:00000000000000000001000000000000000,CAL1_IDEL_INC_CPT:00000000000000000000001000000000000,CAL1_DQ_IDEL_TAP_INC_WAIT:00000000000000000000000000000001000,CAL1_DETECT_EDGE:00000000000001000000000000000000000,CAL1_DQ_IDEL_TAP_INC:00000000000000000000000000000000100,CAL1_MPR_PAT_DETECT:00000000000000000000000010000000000,CAL1_VALID_WAIT:10000000000000000000000000000000000,CAL1_MPR_NEW_DQS_WAIT:00000000000000000000000001000000000,CAL1_RDLVL_ERR:00000000000010000000000000000000000,CAL1_PAT_DETECT:00000000000000100000000000000000000";
  attribute FSM_ENCODED_STATES of \FSM_onehot_cal1_state_r_reg[15]\ : label is "CAL1_STORE_FIRST_WAIT:00000000000000000010000000000000000,CAL1_NEW_DQS_WAIT:00000000000000000000010000000000000,CAL1_IDLE:00000000000000000000000000010000000,CAL1_REGL_LOAD:00000000000000000000000000001000000,CAL1_PB_INC_DQ:00000001000000000000000000000000000,CAL1_PB_DEC_CPT_WAIT:00000000100000000000000000000000000,CAL1_CENTER_WAIT:00000000000000000000000000000000001,CAL1_PB_DETECT_EDGE_DQ:00001000000000000000000000000000000,CAL1_PB_DEC_CPT:00000000001000000000000000000000000,CAL1_PB_DEC_CPT_LEFT_WAIT:01000000000000000000000000000000000,CAL1_PB_INC_DQ_WAIT:00000010000000000000000000000000000,CAL1_RD_STOP_FOR_PI_INC:00000000000000000000000100000000000,CAL1_DONE:00000000000000000000000000000100000,CAL1_PB_DEC_CPT_LEFT:00000000000100000000000000000000000,CAL1_NEW_DQS_PREWAIT:00000000000000000000000000100000000,CAL1_NEXT_DQS:00000000000000000000000000000010000,CAL1_IDEL_DEC_CPT_WAIT:00000000000000000000100000000000000,CAL1_IDEL_DEC_CPT:00000000000000000000000000000000010,CAL1_PB_INC_CPT_WAIT:00000000000000000100000000000000000,CAL1_PB_INC_CPT:00000000000000010000000000000000000,CAL1_CALC_IDEL:00000100000000000000000000000000000,CAL1_PB_DETECT_EDGE:00000000000000001000000000000000000,CAL1_DQ_IDEL_TAP_DEC_WAIT:00100000000000000000000000000000000,CAL1_IDEL_INC_CPT_WAIT:00010000000000000000000000000000000,CAL1_PB_STORE_FIRST_WAIT:00000000010000000000000000000000000,CAL1_DQ_IDEL_TAP_DEC:00000000000000000001000000000000000,CAL1_IDEL_INC_CPT:00000000000000000000001000000000000,CAL1_DQ_IDEL_TAP_INC_WAIT:00000000000000000000000000000001000,CAL1_DETECT_EDGE:00000000000001000000000000000000000,CAL1_DQ_IDEL_TAP_INC:00000000000000000000000000000000100,CAL1_MPR_PAT_DETECT:00000000000000000000000010000000000,CAL1_VALID_WAIT:10000000000000000000000000000000000,CAL1_MPR_NEW_DQS_WAIT:00000000000000000000000001000000000,CAL1_RDLVL_ERR:00000000000010000000000000000000000,CAL1_PAT_DETECT:00000000000000100000000000000000000";
  attribute FSM_ENCODED_STATES of \FSM_onehot_cal1_state_r_reg[16]\ : label is "CAL1_STORE_FIRST_WAIT:00000000000000000010000000000000000,CAL1_NEW_DQS_WAIT:00000000000000000000010000000000000,CAL1_IDLE:00000000000000000000000000010000000,CAL1_REGL_LOAD:00000000000000000000000000001000000,CAL1_PB_INC_DQ:00000001000000000000000000000000000,CAL1_PB_DEC_CPT_WAIT:00000000100000000000000000000000000,CAL1_CENTER_WAIT:00000000000000000000000000000000001,CAL1_PB_DETECT_EDGE_DQ:00001000000000000000000000000000000,CAL1_PB_DEC_CPT:00000000001000000000000000000000000,CAL1_PB_DEC_CPT_LEFT_WAIT:01000000000000000000000000000000000,CAL1_PB_INC_DQ_WAIT:00000010000000000000000000000000000,CAL1_RD_STOP_FOR_PI_INC:00000000000000000000000100000000000,CAL1_DONE:00000000000000000000000000000100000,CAL1_PB_DEC_CPT_LEFT:00000000000100000000000000000000000,CAL1_NEW_DQS_PREWAIT:00000000000000000000000000100000000,CAL1_NEXT_DQS:00000000000000000000000000000010000,CAL1_IDEL_DEC_CPT_WAIT:00000000000000000000100000000000000,CAL1_IDEL_DEC_CPT:00000000000000000000000000000000010,CAL1_PB_INC_CPT_WAIT:00000000000000000100000000000000000,CAL1_PB_INC_CPT:00000000000000010000000000000000000,CAL1_CALC_IDEL:00000100000000000000000000000000000,CAL1_PB_DETECT_EDGE:00000000000000001000000000000000000,CAL1_DQ_IDEL_TAP_DEC_WAIT:00100000000000000000000000000000000,CAL1_IDEL_INC_CPT_WAIT:00010000000000000000000000000000000,CAL1_PB_STORE_FIRST_WAIT:00000000010000000000000000000000000,CAL1_DQ_IDEL_TAP_DEC:00000000000000000001000000000000000,CAL1_IDEL_INC_CPT:00000000000000000000001000000000000,CAL1_DQ_IDEL_TAP_INC_WAIT:00000000000000000000000000000001000,CAL1_DETECT_EDGE:00000000000001000000000000000000000,CAL1_DQ_IDEL_TAP_INC:00000000000000000000000000000000100,CAL1_MPR_PAT_DETECT:00000000000000000000000010000000000,CAL1_VALID_WAIT:10000000000000000000000000000000000,CAL1_MPR_NEW_DQS_WAIT:00000000000000000000000001000000000,CAL1_RDLVL_ERR:00000000000010000000000000000000000,CAL1_PAT_DETECT:00000000000000100000000000000000000";
  attribute FSM_ENCODED_STATES of \FSM_onehot_cal1_state_r_reg[1]\ : label is "CAL1_STORE_FIRST_WAIT:00000000000000000010000000000000000,CAL1_NEW_DQS_WAIT:00000000000000000000010000000000000,CAL1_IDLE:00000000000000000000000000010000000,CAL1_REGL_LOAD:00000000000000000000000000001000000,CAL1_PB_INC_DQ:00000001000000000000000000000000000,CAL1_PB_DEC_CPT_WAIT:00000000100000000000000000000000000,CAL1_CENTER_WAIT:00000000000000000000000000000000001,CAL1_PB_DETECT_EDGE_DQ:00001000000000000000000000000000000,CAL1_PB_DEC_CPT:00000000001000000000000000000000000,CAL1_PB_DEC_CPT_LEFT_WAIT:01000000000000000000000000000000000,CAL1_PB_INC_DQ_WAIT:00000010000000000000000000000000000,CAL1_RD_STOP_FOR_PI_INC:00000000000000000000000100000000000,CAL1_DONE:00000000000000000000000000000100000,CAL1_PB_DEC_CPT_LEFT:00000000000100000000000000000000000,CAL1_NEW_DQS_PREWAIT:00000000000000000000000000100000000,CAL1_NEXT_DQS:00000000000000000000000000000010000,CAL1_IDEL_DEC_CPT_WAIT:00000000000000000000100000000000000,CAL1_IDEL_DEC_CPT:00000000000000000000000000000000010,CAL1_PB_INC_CPT_WAIT:00000000000000000100000000000000000,CAL1_PB_INC_CPT:00000000000000010000000000000000000,CAL1_CALC_IDEL:00000100000000000000000000000000000,CAL1_PB_DETECT_EDGE:00000000000000001000000000000000000,CAL1_DQ_IDEL_TAP_DEC_WAIT:00100000000000000000000000000000000,CAL1_IDEL_INC_CPT_WAIT:00010000000000000000000000000000000,CAL1_PB_STORE_FIRST_WAIT:00000000010000000000000000000000000,CAL1_DQ_IDEL_TAP_DEC:00000000000000000001000000000000000,CAL1_IDEL_INC_CPT:00000000000000000000001000000000000,CAL1_DQ_IDEL_TAP_INC_WAIT:00000000000000000000000000000001000,CAL1_DETECT_EDGE:00000000000001000000000000000000000,CAL1_DQ_IDEL_TAP_INC:00000000000000000000000000000000100,CAL1_MPR_PAT_DETECT:00000000000000000000000010000000000,CAL1_VALID_WAIT:10000000000000000000000000000000000,CAL1_MPR_NEW_DQS_WAIT:00000000000000000000000001000000000,CAL1_RDLVL_ERR:00000000000010000000000000000000000,CAL1_PAT_DETECT:00000000000000100000000000000000000";
  attribute FSM_ENCODED_STATES of \FSM_onehot_cal1_state_r_reg[20]\ : label is "CAL1_STORE_FIRST_WAIT:00000000000000000010000000000000000,CAL1_NEW_DQS_WAIT:00000000000000000000010000000000000,CAL1_IDLE:00000000000000000000000000010000000,CAL1_REGL_LOAD:00000000000000000000000000001000000,CAL1_PB_INC_DQ:00000001000000000000000000000000000,CAL1_PB_DEC_CPT_WAIT:00000000100000000000000000000000000,CAL1_CENTER_WAIT:00000000000000000000000000000000001,CAL1_PB_DETECT_EDGE_DQ:00001000000000000000000000000000000,CAL1_PB_DEC_CPT:00000000001000000000000000000000000,CAL1_PB_DEC_CPT_LEFT_WAIT:01000000000000000000000000000000000,CAL1_PB_INC_DQ_WAIT:00000010000000000000000000000000000,CAL1_RD_STOP_FOR_PI_INC:00000000000000000000000100000000000,CAL1_DONE:00000000000000000000000000000100000,CAL1_PB_DEC_CPT_LEFT:00000000000100000000000000000000000,CAL1_NEW_DQS_PREWAIT:00000000000000000000000000100000000,CAL1_NEXT_DQS:00000000000000000000000000000010000,CAL1_IDEL_DEC_CPT_WAIT:00000000000000000000100000000000000,CAL1_IDEL_DEC_CPT:00000000000000000000000000000000010,CAL1_PB_INC_CPT_WAIT:00000000000000000100000000000000000,CAL1_PB_INC_CPT:00000000000000010000000000000000000,CAL1_CALC_IDEL:00000100000000000000000000000000000,CAL1_PB_DETECT_EDGE:00000000000000001000000000000000000,CAL1_DQ_IDEL_TAP_DEC_WAIT:00100000000000000000000000000000000,CAL1_IDEL_INC_CPT_WAIT:00010000000000000000000000000000000,CAL1_PB_STORE_FIRST_WAIT:00000000010000000000000000000000000,CAL1_DQ_IDEL_TAP_DEC:00000000000000000001000000000000000,CAL1_IDEL_INC_CPT:00000000000000000000001000000000000,CAL1_DQ_IDEL_TAP_INC_WAIT:00000000000000000000000000000001000,CAL1_DETECT_EDGE:00000000000001000000000000000000000,CAL1_DQ_IDEL_TAP_INC:00000000000000000000000000000000100,CAL1_MPR_PAT_DETECT:00000000000000000000000010000000000,CAL1_VALID_WAIT:10000000000000000000000000000000000,CAL1_MPR_NEW_DQS_WAIT:00000000000000000000000001000000000,CAL1_RDLVL_ERR:00000000000010000000000000000000000,CAL1_PAT_DETECT:00000000000000100000000000000000000";
  attribute FSM_ENCODED_STATES of \FSM_onehot_cal1_state_r_reg[21]\ : label is "CAL1_STORE_FIRST_WAIT:00000000000000000010000000000000000,CAL1_NEW_DQS_WAIT:00000000000000000000010000000000000,CAL1_IDLE:00000000000000000000000000010000000,CAL1_REGL_LOAD:00000000000000000000000000001000000,CAL1_PB_INC_DQ:00000001000000000000000000000000000,CAL1_PB_DEC_CPT_WAIT:00000000100000000000000000000000000,CAL1_CENTER_WAIT:00000000000000000000000000000000001,CAL1_PB_DETECT_EDGE_DQ:00001000000000000000000000000000000,CAL1_PB_DEC_CPT:00000000001000000000000000000000000,CAL1_PB_DEC_CPT_LEFT_WAIT:01000000000000000000000000000000000,CAL1_PB_INC_DQ_WAIT:00000010000000000000000000000000000,CAL1_RD_STOP_FOR_PI_INC:00000000000000000000000100000000000,CAL1_DONE:00000000000000000000000000000100000,CAL1_PB_DEC_CPT_LEFT:00000000000100000000000000000000000,CAL1_NEW_DQS_PREWAIT:00000000000000000000000000100000000,CAL1_NEXT_DQS:00000000000000000000000000000010000,CAL1_IDEL_DEC_CPT_WAIT:00000000000000000000100000000000000,CAL1_IDEL_DEC_CPT:00000000000000000000000000000000010,CAL1_PB_INC_CPT_WAIT:00000000000000000100000000000000000,CAL1_PB_INC_CPT:00000000000000010000000000000000000,CAL1_CALC_IDEL:00000100000000000000000000000000000,CAL1_PB_DETECT_EDGE:00000000000000001000000000000000000,CAL1_DQ_IDEL_TAP_DEC_WAIT:00100000000000000000000000000000000,CAL1_IDEL_INC_CPT_WAIT:00010000000000000000000000000000000,CAL1_PB_STORE_FIRST_WAIT:00000000010000000000000000000000000,CAL1_DQ_IDEL_TAP_DEC:00000000000000000001000000000000000,CAL1_IDEL_INC_CPT:00000000000000000000001000000000000,CAL1_DQ_IDEL_TAP_INC_WAIT:00000000000000000000000000000001000,CAL1_DETECT_EDGE:00000000000001000000000000000000000,CAL1_DQ_IDEL_TAP_INC:00000000000000000000000000000000100,CAL1_MPR_PAT_DETECT:00000000000000000000000010000000000,CAL1_VALID_WAIT:10000000000000000000000000000000000,CAL1_MPR_NEW_DQS_WAIT:00000000000000000000000001000000000,CAL1_RDLVL_ERR:00000000000010000000000000000000000,CAL1_PAT_DETECT:00000000000000100000000000000000000";
  attribute FSM_ENCODED_STATES of \FSM_onehot_cal1_state_r_reg[22]\ : label is "CAL1_STORE_FIRST_WAIT:00000000000000000010000000000000000,CAL1_NEW_DQS_WAIT:00000000000000000000010000000000000,CAL1_IDLE:00000000000000000000000000010000000,CAL1_REGL_LOAD:00000000000000000000000000001000000,CAL1_PB_INC_DQ:00000001000000000000000000000000000,CAL1_PB_DEC_CPT_WAIT:00000000100000000000000000000000000,CAL1_CENTER_WAIT:00000000000000000000000000000000001,CAL1_PB_DETECT_EDGE_DQ:00001000000000000000000000000000000,CAL1_PB_DEC_CPT:00000000001000000000000000000000000,CAL1_PB_DEC_CPT_LEFT_WAIT:01000000000000000000000000000000000,CAL1_PB_INC_DQ_WAIT:00000010000000000000000000000000000,CAL1_RD_STOP_FOR_PI_INC:00000000000000000000000100000000000,CAL1_DONE:00000000000000000000000000000100000,CAL1_PB_DEC_CPT_LEFT:00000000000100000000000000000000000,CAL1_NEW_DQS_PREWAIT:00000000000000000000000000100000000,CAL1_NEXT_DQS:00000000000000000000000000000010000,CAL1_IDEL_DEC_CPT_WAIT:00000000000000000000100000000000000,CAL1_IDEL_DEC_CPT:00000000000000000000000000000000010,CAL1_PB_INC_CPT_WAIT:00000000000000000100000000000000000,CAL1_PB_INC_CPT:00000000000000010000000000000000000,CAL1_CALC_IDEL:00000100000000000000000000000000000,CAL1_PB_DETECT_EDGE:00000000000000001000000000000000000,CAL1_DQ_IDEL_TAP_DEC_WAIT:00100000000000000000000000000000000,CAL1_IDEL_INC_CPT_WAIT:00010000000000000000000000000000000,CAL1_PB_STORE_FIRST_WAIT:00000000010000000000000000000000000,CAL1_DQ_IDEL_TAP_DEC:00000000000000000001000000000000000,CAL1_IDEL_INC_CPT:00000000000000000000001000000000000,CAL1_DQ_IDEL_TAP_INC_WAIT:00000000000000000000000000000001000,CAL1_DETECT_EDGE:00000000000001000000000000000000000,CAL1_DQ_IDEL_TAP_INC:00000000000000000000000000000000100,CAL1_MPR_PAT_DETECT:00000000000000000000000010000000000,CAL1_VALID_WAIT:10000000000000000000000000000000000,CAL1_MPR_NEW_DQS_WAIT:00000000000000000000000001000000000,CAL1_RDLVL_ERR:00000000000010000000000000000000000,CAL1_PAT_DETECT:00000000000000100000000000000000000";
  attribute FSM_ENCODED_STATES of \FSM_onehot_cal1_state_r_reg[29]\ : label is "CAL1_STORE_FIRST_WAIT:00000000000000000010000000000000000,CAL1_NEW_DQS_WAIT:00000000000000000000010000000000000,CAL1_IDLE:00000000000000000000000000010000000,CAL1_REGL_LOAD:00000000000000000000000000001000000,CAL1_PB_INC_DQ:00000001000000000000000000000000000,CAL1_PB_DEC_CPT_WAIT:00000000100000000000000000000000000,CAL1_CENTER_WAIT:00000000000000000000000000000000001,CAL1_PB_DETECT_EDGE_DQ:00001000000000000000000000000000000,CAL1_PB_DEC_CPT:00000000001000000000000000000000000,CAL1_PB_DEC_CPT_LEFT_WAIT:01000000000000000000000000000000000,CAL1_PB_INC_DQ_WAIT:00000010000000000000000000000000000,CAL1_RD_STOP_FOR_PI_INC:00000000000000000000000100000000000,CAL1_DONE:00000000000000000000000000000100000,CAL1_PB_DEC_CPT_LEFT:00000000000100000000000000000000000,CAL1_NEW_DQS_PREWAIT:00000000000000000000000000100000000,CAL1_NEXT_DQS:00000000000000000000000000000010000,CAL1_IDEL_DEC_CPT_WAIT:00000000000000000000100000000000000,CAL1_IDEL_DEC_CPT:00000000000000000000000000000000010,CAL1_PB_INC_CPT_WAIT:00000000000000000100000000000000000,CAL1_PB_INC_CPT:00000000000000010000000000000000000,CAL1_CALC_IDEL:00000100000000000000000000000000000,CAL1_PB_DETECT_EDGE:00000000000000001000000000000000000,CAL1_DQ_IDEL_TAP_DEC_WAIT:00100000000000000000000000000000000,CAL1_IDEL_INC_CPT_WAIT:00010000000000000000000000000000000,CAL1_PB_STORE_FIRST_WAIT:00000000010000000000000000000000000,CAL1_DQ_IDEL_TAP_DEC:00000000000000000001000000000000000,CAL1_IDEL_INC_CPT:00000000000000000000001000000000000,CAL1_DQ_IDEL_TAP_INC_WAIT:00000000000000000000000000000001000,CAL1_DETECT_EDGE:00000000000001000000000000000000000,CAL1_DQ_IDEL_TAP_INC:00000000000000000000000000000000100,CAL1_MPR_PAT_DETECT:00000000000000000000000010000000000,CAL1_VALID_WAIT:10000000000000000000000000000000000,CAL1_MPR_NEW_DQS_WAIT:00000000000000000000000001000000000,CAL1_RDLVL_ERR:00000000000010000000000000000000000,CAL1_PAT_DETECT:00000000000000100000000000000000000";
  attribute FSM_ENCODED_STATES of \FSM_onehot_cal1_state_r_reg[2]\ : label is "CAL1_STORE_FIRST_WAIT:00000000000000000010000000000000000,CAL1_NEW_DQS_WAIT:00000000000000000000010000000000000,CAL1_IDLE:00000000000000000000000000010000000,CAL1_REGL_LOAD:00000000000000000000000000001000000,CAL1_PB_INC_DQ:00000001000000000000000000000000000,CAL1_PB_DEC_CPT_WAIT:00000000100000000000000000000000000,CAL1_CENTER_WAIT:00000000000000000000000000000000001,CAL1_PB_DETECT_EDGE_DQ:00001000000000000000000000000000000,CAL1_PB_DEC_CPT:00000000001000000000000000000000000,CAL1_PB_DEC_CPT_LEFT_WAIT:01000000000000000000000000000000000,CAL1_PB_INC_DQ_WAIT:00000010000000000000000000000000000,CAL1_RD_STOP_FOR_PI_INC:00000000000000000000000100000000000,CAL1_DONE:00000000000000000000000000000100000,CAL1_PB_DEC_CPT_LEFT:00000000000100000000000000000000000,CAL1_NEW_DQS_PREWAIT:00000000000000000000000000100000000,CAL1_NEXT_DQS:00000000000000000000000000000010000,CAL1_IDEL_DEC_CPT_WAIT:00000000000000000000100000000000000,CAL1_IDEL_DEC_CPT:00000000000000000000000000000000010,CAL1_PB_INC_CPT_WAIT:00000000000000000100000000000000000,CAL1_PB_INC_CPT:00000000000000010000000000000000000,CAL1_CALC_IDEL:00000100000000000000000000000000000,CAL1_PB_DETECT_EDGE:00000000000000001000000000000000000,CAL1_DQ_IDEL_TAP_DEC_WAIT:00100000000000000000000000000000000,CAL1_IDEL_INC_CPT_WAIT:00010000000000000000000000000000000,CAL1_PB_STORE_FIRST_WAIT:00000000010000000000000000000000000,CAL1_DQ_IDEL_TAP_DEC:00000000000000000001000000000000000,CAL1_IDEL_INC_CPT:00000000000000000000001000000000000,CAL1_DQ_IDEL_TAP_INC_WAIT:00000000000000000000000000000001000,CAL1_DETECT_EDGE:00000000000001000000000000000000000,CAL1_DQ_IDEL_TAP_INC:00000000000000000000000000000000100,CAL1_MPR_PAT_DETECT:00000000000000000000000010000000000,CAL1_VALID_WAIT:10000000000000000000000000000000000,CAL1_MPR_NEW_DQS_WAIT:00000000000000000000000001000000000,CAL1_RDLVL_ERR:00000000000010000000000000000000000,CAL1_PAT_DETECT:00000000000000100000000000000000000";
  attribute FSM_ENCODED_STATES of \FSM_onehot_cal1_state_r_reg[31]\ : label is "CAL1_STORE_FIRST_WAIT:00000000000000000010000000000000000,CAL1_NEW_DQS_WAIT:00000000000000000000010000000000000,CAL1_IDLE:00000000000000000000000000010000000,CAL1_REGL_LOAD:00000000000000000000000000001000000,CAL1_PB_INC_DQ:00000001000000000000000000000000000,CAL1_PB_DEC_CPT_WAIT:00000000100000000000000000000000000,CAL1_CENTER_WAIT:00000000000000000000000000000000001,CAL1_PB_DETECT_EDGE_DQ:00001000000000000000000000000000000,CAL1_PB_DEC_CPT:00000000001000000000000000000000000,CAL1_PB_DEC_CPT_LEFT_WAIT:01000000000000000000000000000000000,CAL1_PB_INC_DQ_WAIT:00000010000000000000000000000000000,CAL1_RD_STOP_FOR_PI_INC:00000000000000000000000100000000000,CAL1_DONE:00000000000000000000000000000100000,CAL1_PB_DEC_CPT_LEFT:00000000000100000000000000000000000,CAL1_NEW_DQS_PREWAIT:00000000000000000000000000100000000,CAL1_NEXT_DQS:00000000000000000000000000000010000,CAL1_IDEL_DEC_CPT_WAIT:00000000000000000000100000000000000,CAL1_IDEL_DEC_CPT:00000000000000000000000000000000010,CAL1_PB_INC_CPT_WAIT:00000000000000000100000000000000000,CAL1_PB_INC_CPT:00000000000000010000000000000000000,CAL1_CALC_IDEL:00000100000000000000000000000000000,CAL1_PB_DETECT_EDGE:00000000000000001000000000000000000,CAL1_DQ_IDEL_TAP_DEC_WAIT:00100000000000000000000000000000000,CAL1_IDEL_INC_CPT_WAIT:00010000000000000000000000000000000,CAL1_PB_STORE_FIRST_WAIT:00000000010000000000000000000000000,CAL1_DQ_IDEL_TAP_DEC:00000000000000000001000000000000000,CAL1_IDEL_INC_CPT:00000000000000000000001000000000000,CAL1_DQ_IDEL_TAP_INC_WAIT:00000000000000000000000000000001000,CAL1_DETECT_EDGE:00000000000001000000000000000000000,CAL1_DQ_IDEL_TAP_INC:00000000000000000000000000000000100,CAL1_MPR_PAT_DETECT:00000000000000000000000010000000000,CAL1_VALID_WAIT:10000000000000000000000000000000000,CAL1_MPR_NEW_DQS_WAIT:00000000000000000000000001000000000,CAL1_RDLVL_ERR:00000000000010000000000000000000000,CAL1_PAT_DETECT:00000000000000100000000000000000000";
  attribute FSM_ENCODED_STATES of \FSM_onehot_cal1_state_r_reg[32]\ : label is "CAL1_STORE_FIRST_WAIT:00000000000000000010000000000000000,CAL1_NEW_DQS_WAIT:00000000000000000000010000000000000,CAL1_IDLE:00000000000000000000000000010000000,CAL1_REGL_LOAD:00000000000000000000000000001000000,CAL1_PB_INC_DQ:00000001000000000000000000000000000,CAL1_PB_DEC_CPT_WAIT:00000000100000000000000000000000000,CAL1_CENTER_WAIT:00000000000000000000000000000000001,CAL1_PB_DETECT_EDGE_DQ:00001000000000000000000000000000000,CAL1_PB_DEC_CPT:00000000001000000000000000000000000,CAL1_PB_DEC_CPT_LEFT_WAIT:01000000000000000000000000000000000,CAL1_PB_INC_DQ_WAIT:00000010000000000000000000000000000,CAL1_RD_STOP_FOR_PI_INC:00000000000000000000000100000000000,CAL1_DONE:00000000000000000000000000000100000,CAL1_PB_DEC_CPT_LEFT:00000000000100000000000000000000000,CAL1_NEW_DQS_PREWAIT:00000000000000000000000000100000000,CAL1_NEXT_DQS:00000000000000000000000000000010000,CAL1_IDEL_DEC_CPT_WAIT:00000000000000000000100000000000000,CAL1_IDEL_DEC_CPT:00000000000000000000000000000000010,CAL1_PB_INC_CPT_WAIT:00000000000000000100000000000000000,CAL1_PB_INC_CPT:00000000000000010000000000000000000,CAL1_CALC_IDEL:00000100000000000000000000000000000,CAL1_PB_DETECT_EDGE:00000000000000001000000000000000000,CAL1_DQ_IDEL_TAP_DEC_WAIT:00100000000000000000000000000000000,CAL1_IDEL_INC_CPT_WAIT:00010000000000000000000000000000000,CAL1_PB_STORE_FIRST_WAIT:00000000010000000000000000000000000,CAL1_DQ_IDEL_TAP_DEC:00000000000000000001000000000000000,CAL1_IDEL_INC_CPT:00000000000000000000001000000000000,CAL1_DQ_IDEL_TAP_INC_WAIT:00000000000000000000000000000001000,CAL1_DETECT_EDGE:00000000000001000000000000000000000,CAL1_DQ_IDEL_TAP_INC:00000000000000000000000000000000100,CAL1_MPR_PAT_DETECT:00000000000000000000000010000000000,CAL1_VALID_WAIT:10000000000000000000000000000000000,CAL1_MPR_NEW_DQS_WAIT:00000000000000000000000001000000000,CAL1_RDLVL_ERR:00000000000010000000000000000000000,CAL1_PAT_DETECT:00000000000000100000000000000000000";
  attribute FSM_ENCODED_STATES of \FSM_onehot_cal1_state_r_reg[34]\ : label is "CAL1_STORE_FIRST_WAIT:00000000000000000010000000000000000,CAL1_NEW_DQS_WAIT:00000000000000000000010000000000000,CAL1_IDLE:00000000000000000000000000010000000,CAL1_REGL_LOAD:00000000000000000000000000001000000,CAL1_PB_INC_DQ:00000001000000000000000000000000000,CAL1_PB_DEC_CPT_WAIT:00000000100000000000000000000000000,CAL1_CENTER_WAIT:00000000000000000000000000000000001,CAL1_PB_DETECT_EDGE_DQ:00001000000000000000000000000000000,CAL1_PB_DEC_CPT:00000000001000000000000000000000000,CAL1_PB_DEC_CPT_LEFT_WAIT:01000000000000000000000000000000000,CAL1_PB_INC_DQ_WAIT:00000010000000000000000000000000000,CAL1_RD_STOP_FOR_PI_INC:00000000000000000000000100000000000,CAL1_DONE:00000000000000000000000000000100000,CAL1_PB_DEC_CPT_LEFT:00000000000100000000000000000000000,CAL1_NEW_DQS_PREWAIT:00000000000000000000000000100000000,CAL1_NEXT_DQS:00000000000000000000000000000010000,CAL1_IDEL_DEC_CPT_WAIT:00000000000000000000100000000000000,CAL1_IDEL_DEC_CPT:00000000000000000000000000000000010,CAL1_PB_INC_CPT_WAIT:00000000000000000100000000000000000,CAL1_PB_INC_CPT:00000000000000010000000000000000000,CAL1_CALC_IDEL:00000100000000000000000000000000000,CAL1_PB_DETECT_EDGE:00000000000000001000000000000000000,CAL1_DQ_IDEL_TAP_DEC_WAIT:00100000000000000000000000000000000,CAL1_IDEL_INC_CPT_WAIT:00010000000000000000000000000000000,CAL1_PB_STORE_FIRST_WAIT:00000000010000000000000000000000000,CAL1_DQ_IDEL_TAP_DEC:00000000000000000001000000000000000,CAL1_IDEL_INC_CPT:00000000000000000000001000000000000,CAL1_DQ_IDEL_TAP_INC_WAIT:00000000000000000000000000000001000,CAL1_DETECT_EDGE:00000000000001000000000000000000000,CAL1_DQ_IDEL_TAP_INC:00000000000000000000000000000000100,CAL1_MPR_PAT_DETECT:00000000000000000000000010000000000,CAL1_VALID_WAIT:10000000000000000000000000000000000,CAL1_MPR_NEW_DQS_WAIT:00000000000000000000000001000000000,CAL1_RDLVL_ERR:00000000000010000000000000000000000,CAL1_PAT_DETECT:00000000000000100000000000000000000";
  attribute FSM_ENCODED_STATES of \FSM_onehot_cal1_state_r_reg[3]\ : label is "CAL1_STORE_FIRST_WAIT:00000000000000000010000000000000000,CAL1_NEW_DQS_WAIT:00000000000000000000010000000000000,CAL1_IDLE:00000000000000000000000000010000000,CAL1_REGL_LOAD:00000000000000000000000000001000000,CAL1_PB_INC_DQ:00000001000000000000000000000000000,CAL1_PB_DEC_CPT_WAIT:00000000100000000000000000000000000,CAL1_CENTER_WAIT:00000000000000000000000000000000001,CAL1_PB_DETECT_EDGE_DQ:00001000000000000000000000000000000,CAL1_PB_DEC_CPT:00000000001000000000000000000000000,CAL1_PB_DEC_CPT_LEFT_WAIT:01000000000000000000000000000000000,CAL1_PB_INC_DQ_WAIT:00000010000000000000000000000000000,CAL1_RD_STOP_FOR_PI_INC:00000000000000000000000100000000000,CAL1_DONE:00000000000000000000000000000100000,CAL1_PB_DEC_CPT_LEFT:00000000000100000000000000000000000,CAL1_NEW_DQS_PREWAIT:00000000000000000000000000100000000,CAL1_NEXT_DQS:00000000000000000000000000000010000,CAL1_IDEL_DEC_CPT_WAIT:00000000000000000000100000000000000,CAL1_IDEL_DEC_CPT:00000000000000000000000000000000010,CAL1_PB_INC_CPT_WAIT:00000000000000000100000000000000000,CAL1_PB_INC_CPT:00000000000000010000000000000000000,CAL1_CALC_IDEL:00000100000000000000000000000000000,CAL1_PB_DETECT_EDGE:00000000000000001000000000000000000,CAL1_DQ_IDEL_TAP_DEC_WAIT:00100000000000000000000000000000000,CAL1_IDEL_INC_CPT_WAIT:00010000000000000000000000000000000,CAL1_PB_STORE_FIRST_WAIT:00000000010000000000000000000000000,CAL1_DQ_IDEL_TAP_DEC:00000000000000000001000000000000000,CAL1_IDEL_INC_CPT:00000000000000000000001000000000000,CAL1_DQ_IDEL_TAP_INC_WAIT:00000000000000000000000000000001000,CAL1_DETECT_EDGE:00000000000001000000000000000000000,CAL1_DQ_IDEL_TAP_INC:00000000000000000000000000000000100,CAL1_MPR_PAT_DETECT:00000000000000000000000010000000000,CAL1_VALID_WAIT:10000000000000000000000000000000000,CAL1_MPR_NEW_DQS_WAIT:00000000000000000000000001000000000,CAL1_RDLVL_ERR:00000000000010000000000000000000000,CAL1_PAT_DETECT:00000000000000100000000000000000000";
  attribute FSM_ENCODED_STATES of \FSM_onehot_cal1_state_r_reg[4]\ : label is "CAL1_STORE_FIRST_WAIT:00000000000000000010000000000000000,CAL1_NEW_DQS_WAIT:00000000000000000000010000000000000,CAL1_IDLE:00000000000000000000000000010000000,CAL1_REGL_LOAD:00000000000000000000000000001000000,CAL1_PB_INC_DQ:00000001000000000000000000000000000,CAL1_PB_DEC_CPT_WAIT:00000000100000000000000000000000000,CAL1_CENTER_WAIT:00000000000000000000000000000000001,CAL1_PB_DETECT_EDGE_DQ:00001000000000000000000000000000000,CAL1_PB_DEC_CPT:00000000001000000000000000000000000,CAL1_PB_DEC_CPT_LEFT_WAIT:01000000000000000000000000000000000,CAL1_PB_INC_DQ_WAIT:00000010000000000000000000000000000,CAL1_RD_STOP_FOR_PI_INC:00000000000000000000000100000000000,CAL1_DONE:00000000000000000000000000000100000,CAL1_PB_DEC_CPT_LEFT:00000000000100000000000000000000000,CAL1_NEW_DQS_PREWAIT:00000000000000000000000000100000000,CAL1_NEXT_DQS:00000000000000000000000000000010000,CAL1_IDEL_DEC_CPT_WAIT:00000000000000000000100000000000000,CAL1_IDEL_DEC_CPT:00000000000000000000000000000000010,CAL1_PB_INC_CPT_WAIT:00000000000000000100000000000000000,CAL1_PB_INC_CPT:00000000000000010000000000000000000,CAL1_CALC_IDEL:00000100000000000000000000000000000,CAL1_PB_DETECT_EDGE:00000000000000001000000000000000000,CAL1_DQ_IDEL_TAP_DEC_WAIT:00100000000000000000000000000000000,CAL1_IDEL_INC_CPT_WAIT:00010000000000000000000000000000000,CAL1_PB_STORE_FIRST_WAIT:00000000010000000000000000000000000,CAL1_DQ_IDEL_TAP_DEC:00000000000000000001000000000000000,CAL1_IDEL_INC_CPT:00000000000000000000001000000000000,CAL1_DQ_IDEL_TAP_INC_WAIT:00000000000000000000000000000001000,CAL1_DETECT_EDGE:00000000000001000000000000000000000,CAL1_DQ_IDEL_TAP_INC:00000000000000000000000000000000100,CAL1_MPR_PAT_DETECT:00000000000000000000000010000000000,CAL1_VALID_WAIT:10000000000000000000000000000000000,CAL1_MPR_NEW_DQS_WAIT:00000000000000000000000001000000000,CAL1_RDLVL_ERR:00000000000010000000000000000000000,CAL1_PAT_DETECT:00000000000000100000000000000000000";
  attribute FSM_ENCODED_STATES of \FSM_onehot_cal1_state_r_reg[5]\ : label is "CAL1_STORE_FIRST_WAIT:00000000000000000010000000000000000,CAL1_NEW_DQS_WAIT:00000000000000000000010000000000000,CAL1_IDLE:00000000000000000000000000010000000,CAL1_REGL_LOAD:00000000000000000000000000001000000,CAL1_PB_INC_DQ:00000001000000000000000000000000000,CAL1_PB_DEC_CPT_WAIT:00000000100000000000000000000000000,CAL1_CENTER_WAIT:00000000000000000000000000000000001,CAL1_PB_DETECT_EDGE_DQ:00001000000000000000000000000000000,CAL1_PB_DEC_CPT:00000000001000000000000000000000000,CAL1_PB_DEC_CPT_LEFT_WAIT:01000000000000000000000000000000000,CAL1_PB_INC_DQ_WAIT:00000010000000000000000000000000000,CAL1_RD_STOP_FOR_PI_INC:00000000000000000000000100000000000,CAL1_DONE:00000000000000000000000000000100000,CAL1_PB_DEC_CPT_LEFT:00000000000100000000000000000000000,CAL1_NEW_DQS_PREWAIT:00000000000000000000000000100000000,CAL1_NEXT_DQS:00000000000000000000000000000010000,CAL1_IDEL_DEC_CPT_WAIT:00000000000000000000100000000000000,CAL1_IDEL_DEC_CPT:00000000000000000000000000000000010,CAL1_PB_INC_CPT_WAIT:00000000000000000100000000000000000,CAL1_PB_INC_CPT:00000000000000010000000000000000000,CAL1_CALC_IDEL:00000100000000000000000000000000000,CAL1_PB_DETECT_EDGE:00000000000000001000000000000000000,CAL1_DQ_IDEL_TAP_DEC_WAIT:00100000000000000000000000000000000,CAL1_IDEL_INC_CPT_WAIT:00010000000000000000000000000000000,CAL1_PB_STORE_FIRST_WAIT:00000000010000000000000000000000000,CAL1_DQ_IDEL_TAP_DEC:00000000000000000001000000000000000,CAL1_IDEL_INC_CPT:00000000000000000000001000000000000,CAL1_DQ_IDEL_TAP_INC_WAIT:00000000000000000000000000000001000,CAL1_DETECT_EDGE:00000000000001000000000000000000000,CAL1_DQ_IDEL_TAP_INC:00000000000000000000000000000000100,CAL1_MPR_PAT_DETECT:00000000000000000000000010000000000,CAL1_VALID_WAIT:10000000000000000000000000000000000,CAL1_MPR_NEW_DQS_WAIT:00000000000000000000000001000000000,CAL1_RDLVL_ERR:00000000000010000000000000000000000,CAL1_PAT_DETECT:00000000000000100000000000000000000";
  attribute FSM_ENCODED_STATES of \FSM_onehot_cal1_state_r_reg[6]\ : label is "CAL1_STORE_FIRST_WAIT:00000000000000000010000000000000000,CAL1_NEW_DQS_WAIT:00000000000000000000010000000000000,CAL1_IDLE:00000000000000000000000000010000000,CAL1_REGL_LOAD:00000000000000000000000000001000000,CAL1_PB_INC_DQ:00000001000000000000000000000000000,CAL1_PB_DEC_CPT_WAIT:00000000100000000000000000000000000,CAL1_CENTER_WAIT:00000000000000000000000000000000001,CAL1_PB_DETECT_EDGE_DQ:00001000000000000000000000000000000,CAL1_PB_DEC_CPT:00000000001000000000000000000000000,CAL1_PB_DEC_CPT_LEFT_WAIT:01000000000000000000000000000000000,CAL1_PB_INC_DQ_WAIT:00000010000000000000000000000000000,CAL1_RD_STOP_FOR_PI_INC:00000000000000000000000100000000000,CAL1_DONE:00000000000000000000000000000100000,CAL1_PB_DEC_CPT_LEFT:00000000000100000000000000000000000,CAL1_NEW_DQS_PREWAIT:00000000000000000000000000100000000,CAL1_NEXT_DQS:00000000000000000000000000000010000,CAL1_IDEL_DEC_CPT_WAIT:00000000000000000000100000000000000,CAL1_IDEL_DEC_CPT:00000000000000000000000000000000010,CAL1_PB_INC_CPT_WAIT:00000000000000000100000000000000000,CAL1_PB_INC_CPT:00000000000000010000000000000000000,CAL1_CALC_IDEL:00000100000000000000000000000000000,CAL1_PB_DETECT_EDGE:00000000000000001000000000000000000,CAL1_DQ_IDEL_TAP_DEC_WAIT:00100000000000000000000000000000000,CAL1_IDEL_INC_CPT_WAIT:00010000000000000000000000000000000,CAL1_PB_STORE_FIRST_WAIT:00000000010000000000000000000000000,CAL1_DQ_IDEL_TAP_DEC:00000000000000000001000000000000000,CAL1_IDEL_INC_CPT:00000000000000000000001000000000000,CAL1_DQ_IDEL_TAP_INC_WAIT:00000000000000000000000000000001000,CAL1_DETECT_EDGE:00000000000001000000000000000000000,CAL1_DQ_IDEL_TAP_INC:00000000000000000000000000000000100,CAL1_MPR_PAT_DETECT:00000000000000000000000010000000000,CAL1_VALID_WAIT:10000000000000000000000000000000000,CAL1_MPR_NEW_DQS_WAIT:00000000000000000000000001000000000,CAL1_RDLVL_ERR:00000000000010000000000000000000000,CAL1_PAT_DETECT:00000000000000100000000000000000000";
  attribute FSM_ENCODED_STATES of \FSM_onehot_cal1_state_r_reg[7]\ : label is "CAL1_STORE_FIRST_WAIT:00000000000000000010000000000000000,CAL1_NEW_DQS_WAIT:00000000000000000000010000000000000,CAL1_IDLE:00000000000000000000000000010000000,CAL1_REGL_LOAD:00000000000000000000000000001000000,CAL1_PB_INC_DQ:00000001000000000000000000000000000,CAL1_PB_DEC_CPT_WAIT:00000000100000000000000000000000000,CAL1_CENTER_WAIT:00000000000000000000000000000000001,CAL1_PB_DETECT_EDGE_DQ:00001000000000000000000000000000000,CAL1_PB_DEC_CPT:00000000001000000000000000000000000,CAL1_PB_DEC_CPT_LEFT_WAIT:01000000000000000000000000000000000,CAL1_PB_INC_DQ_WAIT:00000010000000000000000000000000000,CAL1_RD_STOP_FOR_PI_INC:00000000000000000000000100000000000,CAL1_DONE:00000000000000000000000000000100000,CAL1_PB_DEC_CPT_LEFT:00000000000100000000000000000000000,CAL1_NEW_DQS_PREWAIT:00000000000000000000000000100000000,CAL1_NEXT_DQS:00000000000000000000000000000010000,CAL1_IDEL_DEC_CPT_WAIT:00000000000000000000100000000000000,CAL1_IDEL_DEC_CPT:00000000000000000000000000000000010,CAL1_PB_INC_CPT_WAIT:00000000000000000100000000000000000,CAL1_PB_INC_CPT:00000000000000010000000000000000000,CAL1_CALC_IDEL:00000100000000000000000000000000000,CAL1_PB_DETECT_EDGE:00000000000000001000000000000000000,CAL1_DQ_IDEL_TAP_DEC_WAIT:00100000000000000000000000000000000,CAL1_IDEL_INC_CPT_WAIT:00010000000000000000000000000000000,CAL1_PB_STORE_FIRST_WAIT:00000000010000000000000000000000000,CAL1_DQ_IDEL_TAP_DEC:00000000000000000001000000000000000,CAL1_IDEL_INC_CPT:00000000000000000000001000000000000,CAL1_DQ_IDEL_TAP_INC_WAIT:00000000000000000000000000000001000,CAL1_DETECT_EDGE:00000000000001000000000000000000000,CAL1_DQ_IDEL_TAP_INC:00000000000000000000000000000000100,CAL1_MPR_PAT_DETECT:00000000000000000000000010000000000,CAL1_VALID_WAIT:10000000000000000000000000000000000,CAL1_MPR_NEW_DQS_WAIT:00000000000000000000000001000000000,CAL1_RDLVL_ERR:00000000000010000000000000000000000,CAL1_PAT_DETECT:00000000000000100000000000000000000";
  attribute FSM_ENCODED_STATES of \FSM_onehot_cal1_state_r_reg[8]\ : label is "CAL1_STORE_FIRST_WAIT:00000000000000000010000000000000000,CAL1_NEW_DQS_WAIT:00000000000000000000010000000000000,CAL1_IDLE:00000000000000000000000000010000000,CAL1_REGL_LOAD:00000000000000000000000000001000000,CAL1_PB_INC_DQ:00000001000000000000000000000000000,CAL1_PB_DEC_CPT_WAIT:00000000100000000000000000000000000,CAL1_CENTER_WAIT:00000000000000000000000000000000001,CAL1_PB_DETECT_EDGE_DQ:00001000000000000000000000000000000,CAL1_PB_DEC_CPT:00000000001000000000000000000000000,CAL1_PB_DEC_CPT_LEFT_WAIT:01000000000000000000000000000000000,CAL1_PB_INC_DQ_WAIT:00000010000000000000000000000000000,CAL1_RD_STOP_FOR_PI_INC:00000000000000000000000100000000000,CAL1_DONE:00000000000000000000000000000100000,CAL1_PB_DEC_CPT_LEFT:00000000000100000000000000000000000,CAL1_NEW_DQS_PREWAIT:00000000000000000000000000100000000,CAL1_NEXT_DQS:00000000000000000000000000000010000,CAL1_IDEL_DEC_CPT_WAIT:00000000000000000000100000000000000,CAL1_IDEL_DEC_CPT:00000000000000000000000000000000010,CAL1_PB_INC_CPT_WAIT:00000000000000000100000000000000000,CAL1_PB_INC_CPT:00000000000000010000000000000000000,CAL1_CALC_IDEL:00000100000000000000000000000000000,CAL1_PB_DETECT_EDGE:00000000000000001000000000000000000,CAL1_DQ_IDEL_TAP_DEC_WAIT:00100000000000000000000000000000000,CAL1_IDEL_INC_CPT_WAIT:00010000000000000000000000000000000,CAL1_PB_STORE_FIRST_WAIT:00000000010000000000000000000000000,CAL1_DQ_IDEL_TAP_DEC:00000000000000000001000000000000000,CAL1_IDEL_INC_CPT:00000000000000000000001000000000000,CAL1_DQ_IDEL_TAP_INC_WAIT:00000000000000000000000000000001000,CAL1_DETECT_EDGE:00000000000001000000000000000000000,CAL1_DQ_IDEL_TAP_INC:00000000000000000000000000000000100,CAL1_MPR_PAT_DETECT:00000000000000000000000010000000000,CAL1_VALID_WAIT:10000000000000000000000000000000000,CAL1_MPR_NEW_DQS_WAIT:00000000000000000000000001000000000,CAL1_RDLVL_ERR:00000000000010000000000000000000000,CAL1_PAT_DETECT:00000000000000100000000000000000000";
  attribute FSM_ENCODED_STATES of \FSM_onehot_cal1_state_r_reg[9]\ : label is "CAL1_STORE_FIRST_WAIT:00000000000000000010000000000000000,CAL1_NEW_DQS_WAIT:00000000000000000000010000000000000,CAL1_IDLE:00000000000000000000000000010000000,CAL1_REGL_LOAD:00000000000000000000000000001000000,CAL1_PB_INC_DQ:00000001000000000000000000000000000,CAL1_PB_DEC_CPT_WAIT:00000000100000000000000000000000000,CAL1_CENTER_WAIT:00000000000000000000000000000000001,CAL1_PB_DETECT_EDGE_DQ:00001000000000000000000000000000000,CAL1_PB_DEC_CPT:00000000001000000000000000000000000,CAL1_PB_DEC_CPT_LEFT_WAIT:01000000000000000000000000000000000,CAL1_PB_INC_DQ_WAIT:00000010000000000000000000000000000,CAL1_RD_STOP_FOR_PI_INC:00000000000000000000000100000000000,CAL1_DONE:00000000000000000000000000000100000,CAL1_PB_DEC_CPT_LEFT:00000000000100000000000000000000000,CAL1_NEW_DQS_PREWAIT:00000000000000000000000000100000000,CAL1_NEXT_DQS:00000000000000000000000000000010000,CAL1_IDEL_DEC_CPT_WAIT:00000000000000000000100000000000000,CAL1_IDEL_DEC_CPT:00000000000000000000000000000000010,CAL1_PB_INC_CPT_WAIT:00000000000000000100000000000000000,CAL1_PB_INC_CPT:00000000000000010000000000000000000,CAL1_CALC_IDEL:00000100000000000000000000000000000,CAL1_PB_DETECT_EDGE:00000000000000001000000000000000000,CAL1_DQ_IDEL_TAP_DEC_WAIT:00100000000000000000000000000000000,CAL1_IDEL_INC_CPT_WAIT:00010000000000000000000000000000000,CAL1_PB_STORE_FIRST_WAIT:00000000010000000000000000000000000,CAL1_DQ_IDEL_TAP_DEC:00000000000000000001000000000000000,CAL1_IDEL_INC_CPT:00000000000000000000001000000000000,CAL1_DQ_IDEL_TAP_INC_WAIT:00000000000000000000000000000001000,CAL1_DETECT_EDGE:00000000000001000000000000000000000,CAL1_DQ_IDEL_TAP_INC:00000000000000000000000000000000100,CAL1_MPR_PAT_DETECT:00000000000000000000000010000000000,CAL1_VALID_WAIT:10000000000000000000000000000000000,CAL1_MPR_NEW_DQS_WAIT:00000000000000000000000001000000000,CAL1_RDLVL_ERR:00000000000010000000000000000000000,CAL1_PAT_DETECT:00000000000000100000000000000000000";
  attribute SOFT_HLUTNM of \cal1_cnt_cpt_r[2]_i_2\ : label is "soft_lutpair219";
  attribute SOFT_HLUTNM of cal1_dlyce_cpt_r_i_1 : label is "soft_lutpair222";
  attribute SOFT_HLUTNM of cal1_dlyinc_cpt_r_i_1 : label is "soft_lutpair222";
  attribute SOFT_HLUTNM of \cal1_state_r1[0]_i_2\ : label is "soft_lutpair111";
  attribute SOFT_HLUTNM of \cal1_state_r1[1]_i_2\ : label is "soft_lutpair111";
  attribute SOFT_HLUTNM of \cal1_state_r1[2]_i_2\ : label is "soft_lutpair130";
  attribute SOFT_HLUTNM of \cal1_state_r1[3]_i_2\ : label is "soft_lutpair108";
  attribute SOFT_HLUTNM of \cal1_state_r1[3]_i_3\ : label is "soft_lutpair112";
  attribute SOFT_HLUTNM of \cal1_state_r1[4]_i_1\ : label is "soft_lutpair104";
  attribute SOFT_HLUTNM of \cal1_state_r1[5]_i_1\ : label is "soft_lutpair206";
  attribute SOFT_HLUTNM of cal1_wait_cnt_en_r_i_2 : label is "soft_lutpair129";
  attribute SOFT_HLUTNM of cal1_wait_cnt_en_r_i_3 : label is "soft_lutpair206";
  attribute SOFT_HLUTNM of \cal1_wait_cnt_r[1]_i_1\ : label is "soft_lutpair220";
  attribute SOFT_HLUTNM of \cal1_wait_cnt_r[2]_i_1\ : label is "soft_lutpair220";
  attribute SOFT_HLUTNM of \cal1_wait_cnt_r[3]_i_1\ : label is "soft_lutpair106";
  attribute SOFT_HLUTNM of \cal1_wait_cnt_r[4]_i_2\ : label is "soft_lutpair106";
  attribute SOFT_HLUTNM of \cnt_idel_dec_cpt_r[0]_i_3\ : label is "soft_lutpair119";
  attribute SOFT_HLUTNM of \cnt_idel_dec_cpt_r[1]_i_4\ : label is "soft_lutpair120";
  attribute SOFT_HLUTNM of \cnt_idel_dec_cpt_r[3]_i_2\ : label is "soft_lutpair131";
  attribute SOFT_HLUTNM of \cnt_idel_dec_cpt_r[3]_i_5\ : label is "soft_lutpair208";
  attribute SOFT_HLUTNM of \cnt_idel_dec_cpt_r[4]_i_10\ : label is "soft_lutpair103";
  attribute SOFT_HLUTNM of \cnt_idel_dec_cpt_r[4]_i_3\ : label is "soft_lutpair131";
  attribute SOFT_HLUTNM of \cnt_idel_dec_cpt_r[5]_i_6\ : label is "soft_lutpair103";
  attribute SOFT_HLUTNM of \cnt_shift_r[2]_i_1\ : label is "soft_lutpair126";
  attribute SOFT_HLUTNM of \cnt_shift_r[3]_i_2\ : label is "soft_lutpair126";
  attribute SOFT_HLUTNM of \ctl_lane_cnt[2]_i_3\ : label is "soft_lutpair209";
  attribute SOFT_HLUTNM of \done_cnt[1]_i_1\ : label is "soft_lutpair87";
  attribute SOFT_HLUTNM of \done_cnt[3]_i_1\ : label is "soft_lutpair87";
  attribute SOFT_HLUTNM of \first_edge_taps_r[5]_i_3\ : label is "soft_lutpair125";
  attribute SOFT_HLUTNM of \gen_byte_sel_div2.byte_sel_cnt[0]_i_3\ : label is "soft_lutpair219";
  attribute SOFT_HLUTNM of \gen_byte_sel_div2.byte_sel_cnt[1]_i_3\ : label is "soft_lutpair207";
  attribute SOFT_HLUTNM of \gen_byte_sel_div2.byte_sel_cnt[2]_i_3\ : label is "soft_lutpair207";
  attribute SOFT_HLUTNM of \gen_pat_match_div4.idel_pat0_match_fall2_and_r_i_1\ : label is "soft_lutpair216";
  attribute SOFT_HLUTNM of \gen_pat_match_div4.idel_pat0_match_rise2_and_r_i_1\ : label is "soft_lutpair205";
  attribute SOFT_HLUTNM of \gen_pat_match_div4.idel_pat1_match_fall0_and_r_i_1\ : label is "soft_lutpair213";
  attribute SOFT_HLUTNM of \gen_pat_match_div4.pat0_match_fall0_and_r_i_1\ : label is "soft_lutpair213";
  attribute SOFT_HLUTNM of \gen_pat_match_div4.pat0_match_rise2_and_r_i_1\ : label is "soft_lutpair205";
  attribute SOFT_HLUTNM of \gen_pat_match_div4.pat1_match_fall2_and_r_i_1\ : label is "soft_lutpair216";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall0_r[0]_i_1\ : label is "soft_lutpair199";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall1_r[0]_i_1\ : label is "soft_lutpair186";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall2_r[0]_i_1\ : label is "soft_lutpair195";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall3_r[0]_i_1\ : label is "soft_lutpair203";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise0_r[0]_i_1\ : label is "soft_lutpair153";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise1_r[0]_i_1\ : label is "soft_lutpair191";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise2_r[0]_i_1\ : label is "soft_lutpair158";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise3_r[0]_i_1\ : label is "soft_lutpair149";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_1\ : label is "soft_lutpair199";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall1_r[0]_i_1\ : label is "soft_lutpair186";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall2_r[0]_i_1\ : label is "soft_lutpair195";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall3_r[0]_i_1\ : label is "soft_lutpair203";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise0_r[0]_i_1\ : label is "soft_lutpair153";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise1_r[0]_i_1\ : label is "soft_lutpair191";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise2_r[0]_i_1\ : label is "soft_lutpair158";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise3_r[0]_i_1\ : label is "soft_lutpair149";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[1].old_sr_match_fall0_r[1]_i_1\ : label is "soft_lutpair176";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[1].old_sr_match_fall1_r[1]_i_1\ : label is "soft_lutpair139";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[1].old_sr_match_fall2_r[1]_i_1\ : label is "soft_lutpair145";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[1].old_sr_match_fall3_r[1]_i_1\ : label is "soft_lutpair180";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[1].old_sr_match_rise0_r[1]_i_1\ : label is "soft_lutpair167";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[1].old_sr_match_rise1_r[1]_i_1\ : label is "soft_lutpair133";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[1].old_sr_match_rise2_r[1]_i_1\ : label is "soft_lutpair171";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[1].old_sr_match_rise3_r[1]_i_1\ : label is "soft_lutpair163";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[1].prev_sr_match_fall0_r[1]_i_1\ : label is "soft_lutpair176";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[1].prev_sr_match_fall1_r[1]_i_1\ : label is "soft_lutpair139";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[1].prev_sr_match_fall2_r[1]_i_1\ : label is "soft_lutpair145";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[1].prev_sr_match_fall3_r[1]_i_1\ : label is "soft_lutpair180";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[1].prev_sr_match_rise0_r[1]_i_1\ : label is "soft_lutpair167";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[1].prev_sr_match_rise1_r[1]_i_1\ : label is "soft_lutpair133";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[1].prev_sr_match_rise2_r[1]_i_1\ : label is "soft_lutpair171";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[1].prev_sr_match_rise3_r[1]_i_1\ : label is "soft_lutpair163";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[2].old_sr_match_fall0_r[2]_i_1\ : label is "soft_lutpair200";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[2].old_sr_match_fall1_r[2]_i_1\ : label is "soft_lutpair185";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[2].old_sr_match_fall2_r[2]_i_1\ : label is "soft_lutpair196";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[2].old_sr_match_fall3_r[2]_i_1\ : label is "soft_lutpair183";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[2].old_sr_match_rise0_r[2]_i_1\ : label is "soft_lutpair152";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[2].old_sr_match_rise1_r[2]_i_1\ : label is "soft_lutpair192";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[2].old_sr_match_rise2_r[2]_i_1\ : label is "soft_lutpair157";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[2].old_sr_match_rise3_r[2]_i_1\ : label is "soft_lutpair148";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[2].prev_sr_match_fall0_r[2]_i_1\ : label is "soft_lutpair200";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[2].prev_sr_match_fall1_r[2]_i_1\ : label is "soft_lutpair185";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[2].prev_sr_match_fall2_r[2]_i_1\ : label is "soft_lutpair196";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[2].prev_sr_match_fall3_r[2]_i_1\ : label is "soft_lutpair183";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[2].prev_sr_match_rise0_r[2]_i_1\ : label is "soft_lutpair152";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[2].prev_sr_match_rise1_r[2]_i_1\ : label is "soft_lutpair192";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[2].prev_sr_match_rise2_r[2]_i_1\ : label is "soft_lutpair157";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[2].prev_sr_match_rise3_r[2]_i_1\ : label is "soft_lutpair148";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[3].old_sr_match_fall0_r[3]_i_1\ : label is "soft_lutpair175";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[3].old_sr_match_fall1_r[3]_i_1\ : label is "soft_lutpair141";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[3].old_sr_match_fall2_r[3]_i_1\ : label is "soft_lutpair144";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[3].old_sr_match_fall3_r[3]_i_1\ : label is "soft_lutpair179";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[3].old_sr_match_rise0_r[3]_i_1\ : label is "soft_lutpair166";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[3].old_sr_match_rise1_r[3]_i_1\ : label is "soft_lutpair172";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[3].old_sr_match_rise2_r[3]_i_1\ : label is "soft_lutpair170";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[3].old_sr_match_rise3_r[3]_i_1\ : label is "soft_lutpair162";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[3].prev_sr_match_fall0_r[3]_i_1\ : label is "soft_lutpair175";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[3].prev_sr_match_fall1_r[3]_i_1\ : label is "soft_lutpair141";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[3].prev_sr_match_fall2_r[3]_i_1\ : label is "soft_lutpair144";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[3].prev_sr_match_fall3_r[3]_i_1\ : label is "soft_lutpair179";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[3].prev_sr_match_rise0_r[3]_i_1\ : label is "soft_lutpair166";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[3].prev_sr_match_rise1_r[3]_i_1\ : label is "soft_lutpair172";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[3].prev_sr_match_rise2_r[3]_i_1\ : label is "soft_lutpair170";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[3].prev_sr_match_rise3_r[3]_i_1\ : label is "soft_lutpair162";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[4].old_sr_match_fall0_r[4]_i_1\ : label is "soft_lutpair201";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[4].old_sr_match_fall1_r[4]_i_1\ : label is "soft_lutpair184";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[4].old_sr_match_fall2_r[4]_i_1\ : label is "soft_lutpair197";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[4].old_sr_match_fall3_r[4]_i_1\ : label is "soft_lutpair188";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[4].old_sr_match_rise0_r[4]_i_1\ : label is "soft_lutpair151";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[4].old_sr_match_rise1_r[4]_i_1\ : label is "soft_lutpair193";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[4].old_sr_match_rise2_r[4]_i_1\ : label is "soft_lutpair155";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[4].old_sr_match_rise3_r[4]_i_1\ : label is "soft_lutpair147";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[4].prev_sr_match_fall0_r[4]_i_1\ : label is "soft_lutpair201";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[4].prev_sr_match_fall1_r[4]_i_1\ : label is "soft_lutpair184";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[4].prev_sr_match_fall2_r[4]_i_1\ : label is "soft_lutpair197";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[4].prev_sr_match_fall3_r[4]_i_1\ : label is "soft_lutpair188";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[4].prev_sr_match_rise0_r[4]_i_1\ : label is "soft_lutpair151";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[4].prev_sr_match_rise1_r[4]_i_1\ : label is "soft_lutpair193";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[4].prev_sr_match_rise2_r[4]_i_1\ : label is "soft_lutpair155";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[4].prev_sr_match_rise3_r[4]_i_1\ : label is "soft_lutpair147";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[5].old_sr_match_fall0_r[5]_i_1\ : label is "soft_lutpair174";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[5].old_sr_match_fall1_r[5]_i_1\ : label is "soft_lutpair143";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[5].old_sr_match_fall2_r[5]_i_1\ : label is "soft_lutpair182";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[5].old_sr_match_fall3_r[5]_i_1\ : label is "soft_lutpair178";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[5].old_sr_match_rise0_r[5]_i_1\ : label is "soft_lutpair165";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[5].old_sr_match_rise1_r[5]_i_1\ : label is "soft_lutpair135";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[5].old_sr_match_rise2_r[5]_i_1\ : label is "soft_lutpair169";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[5].old_sr_match_rise3_r[5]_i_1\ : label is "soft_lutpair161";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[5].prev_sr_match_fall0_r[5]_i_1\ : label is "soft_lutpair174";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[5].prev_sr_match_fall1_r[5]_i_1\ : label is "soft_lutpair143";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[5].prev_sr_match_fall2_r[5]_i_1\ : label is "soft_lutpair182";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[5].prev_sr_match_fall3_r[5]_i_1\ : label is "soft_lutpair178";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[5].prev_sr_match_rise0_r[5]_i_1\ : label is "soft_lutpair165";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[5].prev_sr_match_rise1_r[5]_i_1\ : label is "soft_lutpair135";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[5].prev_sr_match_rise2_r[5]_i_1\ : label is "soft_lutpair169";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[5].prev_sr_match_rise3_r[5]_i_1\ : label is "soft_lutpair161";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[6].old_sr_match_fall0_r[6]_i_1\ : label is "soft_lutpair202";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[6].old_sr_match_fall1_r[6]_i_1\ : label is "soft_lutpair159";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[6].old_sr_match_fall2_r[6]_i_1\ : label is "soft_lutpair198";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[6].old_sr_match_fall3_r[6]_i_1\ : label is "soft_lutpair204";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[6].old_sr_match_rise0_r[6]_i_1\ : label is "soft_lutpair150";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[6].old_sr_match_rise1_r[6]_i_1\ : label is "soft_lutpair194";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[6].old_sr_match_rise2_r[6]_i_1\ : label is "soft_lutpair154";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[6].old_sr_match_rise3_r[6]_i_1\ : label is "soft_lutpair156";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[6].prev_sr_match_fall0_r[6]_i_1\ : label is "soft_lutpair202";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[6].prev_sr_match_fall1_r[6]_i_1\ : label is "soft_lutpair159";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[6].prev_sr_match_fall2_r[6]_i_1\ : label is "soft_lutpair198";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[6].prev_sr_match_fall3_r[6]_i_1\ : label is "soft_lutpair204";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[6].prev_sr_match_rise0_r[6]_i_1\ : label is "soft_lutpair150";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[6].prev_sr_match_rise1_r[6]_i_1\ : label is "soft_lutpair194";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[6].prev_sr_match_rise2_r[6]_i_1\ : label is "soft_lutpair154";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[6].prev_sr_match_rise3_r[6]_i_1\ : label is "soft_lutpair156";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[7].old_sr_match_fall0_r[7]_i_1\ : label is "soft_lutpair173";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[7].old_sr_match_fall1_r[7]_i_1\ : label is "soft_lutpair146";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[7].old_sr_match_fall2_r[7]_i_1\ : label is "soft_lutpair181";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[7].old_sr_match_fall3_r[7]_i_1\ : label is "soft_lutpair177";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[7].old_sr_match_rise0_r[7]_i_1\ : label is "soft_lutpair164";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[7].old_sr_match_rise1_r[7]_i_1\ : label is "soft_lutpair137";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[7].old_sr_match_rise2_r[7]_i_1\ : label is "soft_lutpair168";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[7].old_sr_match_rise3_r[7]_i_1\ : label is "soft_lutpair160";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[7].prev_sr_match_fall0_r[7]_i_1\ : label is "soft_lutpair173";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[7].prev_sr_match_fall1_r[7]_i_1\ : label is "soft_lutpair146";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[7].prev_sr_match_fall2_r[7]_i_1\ : label is "soft_lutpair181";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[7].prev_sr_match_fall3_r[7]_i_1\ : label is "soft_lutpair177";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[7].prev_sr_match_rise0_r[7]_i_1\ : label is "soft_lutpair164";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[7].prev_sr_match_rise1_r[7]_i_1\ : label is "soft_lutpair137";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[7].prev_sr_match_rise2_r[7]_i_1\ : label is "soft_lutpair168";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[7].prev_sr_match_rise3_r[7]_i_1\ : label is "soft_lutpair160";
  attribute SOFT_HLUTNM of \gen_track_left_edge[0].pb_cnt_eye_size_r[0][0]_i_1\ : label is "soft_lutpair223";
  attribute SOFT_HLUTNM of \gen_track_left_edge[0].pb_cnt_eye_size_r[0][1]_i_1\ : label is "soft_lutpair223";
  attribute SOFT_HLUTNM of \gen_track_left_edge[0].pb_cnt_eye_size_r[0][2]_i_1\ : label is "soft_lutpair187";
  attribute SOFT_HLUTNM of \gen_track_left_edge[0].pb_cnt_eye_size_r[0][3]_i_1\ : label is "soft_lutpair187";
  attribute SOFT_HLUTNM of \gen_track_left_edge[0].pb_cnt_eye_size_r[0][4]_i_3\ : label is "soft_lutpair105";
  attribute SOFT_HLUTNM of \gen_track_left_edge[0].pb_cnt_eye_size_r[0][4]_i_5\ : label is "soft_lutpair105";
  attribute SOFT_HLUTNM of \gen_track_left_edge[1].pb_cnt_eye_size_r[1][0]_i_1\ : label is "soft_lutpair224";
  attribute SOFT_HLUTNM of \gen_track_left_edge[1].pb_cnt_eye_size_r[1][1]_i_1\ : label is "soft_lutpair224";
  attribute SOFT_HLUTNM of \gen_track_left_edge[1].pb_cnt_eye_size_r[1][2]_i_1\ : label is "soft_lutpair142";
  attribute SOFT_HLUTNM of \gen_track_left_edge[1].pb_cnt_eye_size_r[1][3]_i_1\ : label is "soft_lutpair142";
  attribute SOFT_HLUTNM of \gen_track_left_edge[1].pb_cnt_eye_size_r[1][4]_i_3\ : label is "soft_lutpair83";
  attribute SOFT_HLUTNM of \gen_track_left_edge[1].pb_cnt_eye_size_r[1][4]_i_5\ : label is "soft_lutpair83";
  attribute SOFT_HLUTNM of \gen_track_left_edge[1].pb_detect_edge_done_r[1]_i_1\ : label is "soft_lutpair82";
  attribute SOFT_HLUTNM of \gen_track_left_edge[2].pb_cnt_eye_size_r[2][0]_i_1\ : label is "soft_lutpair225";
  attribute SOFT_HLUTNM of \gen_track_left_edge[2].pb_cnt_eye_size_r[2][1]_i_1\ : label is "soft_lutpair225";
  attribute SOFT_HLUTNM of \gen_track_left_edge[2].pb_cnt_eye_size_r[2][2]_i_1\ : label is "soft_lutpair189";
  attribute SOFT_HLUTNM of \gen_track_left_edge[2].pb_cnt_eye_size_r[2][3]_i_1\ : label is "soft_lutpair189";
  attribute SOFT_HLUTNM of \gen_track_left_edge[2].pb_cnt_eye_size_r[2][4]_i_3\ : label is "soft_lutpair91";
  attribute SOFT_HLUTNM of \gen_track_left_edge[2].pb_cnt_eye_size_r[2][4]_i_5\ : label is "soft_lutpair91";
  attribute SOFT_HLUTNM of \gen_track_left_edge[3].pb_cnt_eye_size_r[3][0]_i_1\ : label is "soft_lutpair226";
  attribute SOFT_HLUTNM of \gen_track_left_edge[3].pb_cnt_eye_size_r[3][1]_i_1\ : label is "soft_lutpair226";
  attribute SOFT_HLUTNM of \gen_track_left_edge[3].pb_cnt_eye_size_r[3][2]_i_1\ : label is "soft_lutpair140";
  attribute SOFT_HLUTNM of \gen_track_left_edge[3].pb_cnt_eye_size_r[3][3]_i_1\ : label is "soft_lutpair140";
  attribute SOFT_HLUTNM of \gen_track_left_edge[3].pb_cnt_eye_size_r[3][4]_i_3\ : label is "soft_lutpair92";
  attribute SOFT_HLUTNM of \gen_track_left_edge[3].pb_cnt_eye_size_r[3][4]_i_5\ : label is "soft_lutpair92";
  attribute SOFT_HLUTNM of \gen_track_left_edge[4].pb_cnt_eye_size_r[4][0]_i_1\ : label is "soft_lutpair227";
  attribute SOFT_HLUTNM of \gen_track_left_edge[4].pb_cnt_eye_size_r[4][1]_i_1\ : label is "soft_lutpair227";
  attribute SOFT_HLUTNM of \gen_track_left_edge[4].pb_cnt_eye_size_r[4][2]_i_1\ : label is "soft_lutpair138";
  attribute SOFT_HLUTNM of \gen_track_left_edge[4].pb_cnt_eye_size_r[4][3]_i_1\ : label is "soft_lutpair138";
  attribute SOFT_HLUTNM of \gen_track_left_edge[4].pb_cnt_eye_size_r[4][4]_i_3\ : label is "soft_lutpair93";
  attribute SOFT_HLUTNM of \gen_track_left_edge[4].pb_cnt_eye_size_r[4][4]_i_5\ : label is "soft_lutpair93";
  attribute SOFT_HLUTNM of \gen_track_left_edge[5].pb_cnt_eye_size_r[5][0]_i_1\ : label is "soft_lutpair228";
  attribute SOFT_HLUTNM of \gen_track_left_edge[5].pb_cnt_eye_size_r[5][1]_i_1\ : label is "soft_lutpair228";
  attribute SOFT_HLUTNM of \gen_track_left_edge[5].pb_cnt_eye_size_r[5][2]_i_1\ : label is "soft_lutpair190";
  attribute SOFT_HLUTNM of \gen_track_left_edge[5].pb_cnt_eye_size_r[5][3]_i_1\ : label is "soft_lutpair190";
  attribute SOFT_HLUTNM of \gen_track_left_edge[5].pb_cnt_eye_size_r[5][4]_i_3\ : label is "soft_lutpair95";
  attribute SOFT_HLUTNM of \gen_track_left_edge[5].pb_cnt_eye_size_r[5][4]_i_5\ : label is "soft_lutpair95";
  attribute SOFT_HLUTNM of \gen_track_left_edge[6].pb_cnt_eye_size_r[6][0]_i_1\ : label is "soft_lutpair229";
  attribute SOFT_HLUTNM of \gen_track_left_edge[6].pb_cnt_eye_size_r[6][1]_i_1\ : label is "soft_lutpair229";
  attribute SOFT_HLUTNM of \gen_track_left_edge[6].pb_cnt_eye_size_r[6][2]_i_1\ : label is "soft_lutpair136";
  attribute SOFT_HLUTNM of \gen_track_left_edge[6].pb_cnt_eye_size_r[6][3]_i_1\ : label is "soft_lutpair136";
  attribute SOFT_HLUTNM of \gen_track_left_edge[6].pb_cnt_eye_size_r[6][4]_i_3\ : label is "soft_lutpair96";
  attribute SOFT_HLUTNM of \gen_track_left_edge[6].pb_cnt_eye_size_r[6][4]_i_5\ : label is "soft_lutpair96";
  attribute SOFT_HLUTNM of \gen_track_left_edge[7].pb_cnt_eye_size_r[7][0]_i_1\ : label is "soft_lutpair230";
  attribute SOFT_HLUTNM of \gen_track_left_edge[7].pb_cnt_eye_size_r[7][1]_i_1\ : label is "soft_lutpair230";
  attribute SOFT_HLUTNM of \gen_track_left_edge[7].pb_cnt_eye_size_r[7][2]_i_1\ : label is "soft_lutpair134";
  attribute SOFT_HLUTNM of \gen_track_left_edge[7].pb_cnt_eye_size_r[7][3]_i_1\ : label is "soft_lutpair134";
  attribute SOFT_HLUTNM of \gen_track_left_edge[7].pb_cnt_eye_size_r[7][4]_i_3\ : label is "soft_lutpair101";
  attribute SOFT_HLUTNM of \gen_track_left_edge[7].pb_cnt_eye_size_r[7][4]_i_5\ : label is "soft_lutpair101";
  attribute SOFT_HLUTNM of \idel_dec_cnt[0]_i_1\ : label is "soft_lutpair109";
  attribute SOFT_HLUTNM of \idel_dec_cnt[4]_i_3\ : label is "soft_lutpair124";
  attribute SOFT_HLUTNM of \idel_dec_cnt[4]_i_4\ : label is "soft_lutpair84";
  attribute SOFT_HLUTNM of \idel_dec_cnt[4]_i_5\ : label is "soft_lutpair84";
  attribute SOFT_HLUTNM of idel_pat_detect_valid_r_i_1 : label is "soft_lutpair110";
  attribute SOFT_HLUTNM of \idelay_tap_cnt_r[0][0][0]_i_1\ : label is "soft_lutpair85";
  attribute SOFT_HLUTNM of \idelay_tap_cnt_r[0][0][1]_i_1\ : label is "soft_lutpair85";
  attribute SOFT_HLUTNM of \idelay_tap_cnt_r[0][0][3]_i_2\ : label is "soft_lutpair114";
  attribute SOFT_HLUTNM of \idelay_tap_cnt_r[0][0][4]_i_2\ : label is "soft_lutpair212";
  attribute SOFT_HLUTNM of \idelay_tap_cnt_r[0][0][4]_i_3\ : label is "soft_lutpair214";
  attribute SOFT_HLUTNM of \idelay_tap_cnt_r[0][0][4]_i_4\ : label is "soft_lutpair127";
  attribute SOFT_HLUTNM of \idelay_tap_cnt_r[0][1][4]_i_2\ : label is "soft_lutpair218";
  attribute SOFT_HLUTNM of \idelay_tap_cnt_r[0][1][4]_i_3\ : label is "soft_lutpair217";
  attribute SOFT_HLUTNM of \idelay_tap_cnt_r[0][3][4]_i_2\ : label is "soft_lutpair217";
  attribute SOFT_HLUTNM of \idelay_tap_cnt_r[0][4][4]_i_2\ : label is "soft_lutpair127";
  attribute SOFT_HLUTNM of idelay_tap_limit_r_i_1 : label is "soft_lutpair209";
  attribute SOFT_HLUTNM of \init_state_r[1]_i_28\ : label is "soft_lutpair115";
  attribute SOFT_HLUTNM of \mpr_4to1.idel_mpr_pat_detect_r_i_2\ : label is "soft_lutpair123";
  attribute SOFT_HLUTNM of \mpr_4to1.inhibit_edge_detect_r_i_5\ : label is "soft_lutpair113";
  attribute SOFT_HLUTNM of \mpr_4to1.inhibit_edge_detect_r_i_6\ : label is "soft_lutpair113";
  attribute SOFT_HLUTNM of \mpr_4to1.stable_idel_cnt[1]_i_1\ : label is "soft_lutpair94";
  attribute SOFT_HLUTNM of \mpr_4to1.stable_idel_cnt[2]_i_1\ : label is "soft_lutpair94";
  attribute SOFT_HLUTNM of \mpr_4to1.stable_idel_cnt[2]_i_3\ : label is "soft_lutpair212";
  attribute SOFT_HLUTNM of pi_cnt_dec_i_2 : label is "soft_lutpair122";
  attribute SOFT_HLUTNM of \pi_rdval_cnt[0]_i_1\ : label is "soft_lutpair89";
  attribute SOFT_HLUTNM of \pi_rdval_cnt[3]_i_2\ : label is "soft_lutpair89";
  attribute SOFT_HLUTNM of \pi_rdval_cnt[3]_i_3\ : label is "soft_lutpair118";
  attribute SOFT_HLUTNM of \pi_rdval_cnt[5]_i_4\ : label is "soft_lutpair118";
  attribute SOFT_HLUTNM of pi_stg2_f_incdec_timing_i_1 : label is "soft_lutpair114";
  attribute SOFT_HLUTNM of rdlvl_pi_incdec_i_3 : label is "soft_lutpair117";
  attribute SOFT_HLUTNM of rdlvl_pi_incdec_i_5 : label is "soft_lutpair129";
  attribute SOFT_HLUTNM of rdlvl_rank_done_r_i_2 : label is "soft_lutpair214";
  attribute SOFT_HLUTNM of rdlvl_rank_done_r_i_3 : label is "soft_lutpair210";
  attribute SOFT_HLUTNM of rdlvl_stg1_done_int_i_1 : label is "soft_lutpair115";
  attribute syn_maxfan : string;
  attribute syn_maxfan of rdlvl_stg1_done_int_reg : label is "30";
  attribute SOFT_HLUTNM of \regl_dqs_cnt[0]_i_1\ : label is "soft_lutpair90";
  attribute SOFT_HLUTNM of \regl_dqs_cnt[1]_i_1\ : label is "soft_lutpair90";
  attribute SOFT_HLUTNM of \regl_rank_cnt[0]_i_1\ : label is "soft_lutpair116";
  attribute SOFT_HLUTNM of \regl_rank_cnt[1]_i_1\ : label is "soft_lutpair116";
  attribute SOFT_HLUTNM of \regl_rank_cnt[1]_i_2\ : label is "soft_lutpair88";
  attribute SOFT_HLUTNM of \regl_rank_cnt[1]_i_3\ : label is "soft_lutpair97";
  attribute SOFT_HLUTNM of \right_edge_taps_r[0]_i_1\ : label is "soft_lutpair232";
  attribute SOFT_HLUTNM of \right_edge_taps_r[1]_i_1\ : label is "soft_lutpair232";
  attribute SOFT_HLUTNM of \right_edge_taps_r[2]_i_1\ : label is "soft_lutpair231";
  attribute SOFT_HLUTNM of \right_edge_taps_r[3]_i_1\ : label is "soft_lutpair208";
  attribute SOFT_HLUTNM of \right_edge_taps_r[4]_i_1\ : label is "soft_lutpair231";
  attribute SOFT_HLUTNM of \right_edge_taps_r[5]_i_2\ : label is "soft_lutpair125";
  attribute SOFT_HLUTNM of \rnk_cnt_r[1]_i_2\ : label is "soft_lutpair121";
  attribute SOFT_HLUTNM of samp_edge_cnt0_en_r_i_1 : label is "soft_lutpair124";
  attribute SOFT_HLUTNM of \second_edge_taps_r[1]_i_1\ : label is "soft_lutpair215";
  attribute SOFT_HLUTNM of \second_edge_taps_r[2]_i_1\ : label is "soft_lutpair215";
  attribute SOFT_HLUTNM of \second_edge_taps_r[3]_i_1\ : label is "soft_lutpair98";
  attribute SOFT_HLUTNM of \second_edge_taps_r[4]_i_1\ : label is "soft_lutpair98";
  attribute SOFT_HLUTNM of \stg1_wr_rd_cnt[4]_i_2\ : label is "soft_lutpair211";
  attribute SOFT_HLUTNM of store_sr_req_r_i_1 : label is "soft_lutpair102";
  attribute SOFT_HLUTNM of \tap_cnt_cpt_r[1]_i_1\ : label is "soft_lutpair120";
  attribute SOFT_HLUTNM of \tap_cnt_cpt_r[2]_i_1\ : label is "soft_lutpair99";
  attribute SOFT_HLUTNM of \tap_cnt_cpt_r[3]_i_1\ : label is "soft_lutpair99";
  attribute SOFT_HLUTNM of \tap_cnt_cpt_r[5]_i_4\ : label is "soft_lutpair86";
  attribute SOFT_HLUTNM of \tap_cnt_cpt_r[5]_i_6\ : label is "soft_lutpair86";
  attribute SOFT_HLUTNM of \wait_cnt_r[1]_i_1__0\ : label is "soft_lutpair221";
  attribute SOFT_HLUTNM of \wait_cnt_r[2]_i_1\ : label is "soft_lutpair221";
  attribute SOFT_HLUTNM of \wait_cnt_r[3]_i_3\ : label is "soft_lutpair122";
  attribute SOFT_HLUTNM of \wrdq_div1_4to1_wrcal_first.phy_wrdata[510]_i_1\ : label is "soft_lutpair211";
begin
  Q(1 downto 0) <= \^q\(1 downto 0);
  \cal1_cnt_cpt_r_reg[2]_1\ <= \^cal1_cnt_cpt_r_reg[2]_1\;
  idelay_ce_int <= \^idelay_ce_int\;
  idelay_inc_int <= \^idelay_inc_int\;
  new_cnt_cpt_r_reg_0 <= \^new_cnt_cpt_r_reg_0\;
  pi_cnt_dec_reg_0 <= \^pi_cnt_dec_reg_0\;
  pi_fine_dly_dec_done <= \^pi_fine_dly_dec_done\;
  rdlvl_last_byte_done <= \^rdlvl_last_byte_done\;
  rdlvl_pi_incdec <= \^rdlvl_pi_incdec\;
  rdlvl_prech_req <= \^rdlvl_prech_req\;
  rdlvl_stg1_done_int_reg_0 <= \^rdlvl_stg1_done_int_reg_0\;
  rdlvl_stg1_rank_done <= \^rdlvl_stg1_rank_done\;
  samp_edge_cnt0_en_r <= \^samp_edge_cnt0_en_r\;
\FSM_onehot_cal1_state_r[10]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => p_1_in26_in,
      I1 => p_2_in,
      O => \FSM_onehot_cal1_state_r[10]_i_1_n_0\
    );
\FSM_onehot_cal1_state_r[11]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00002AAA"
    )
        port map (
      I0 => store_sr_req_pulsed_r,
      I1 => found_edge_r_reg_n_0,
      I2 => found_stable_eye_last_r,
      I3 => found_first_edge_r_reg_n_0,
      I4 => tap_limit_cpt_r,
      O => \FSM_onehot_cal1_state_r[11]_i_1_n_0\
    );
\FSM_onehot_cal1_state_r[13]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FBAA"
    )
        port map (
      I0 => \FSM_onehot_cal1_state_r_reg_n_0_[8]\,
      I1 => mpr_rdlvl_start_r_reg_0,
      I2 => mpr_rdlvl_start_r,
      I3 => \FSM_onehot_cal1_state_r_reg_n_0_[7]\,
      O => \FSM_onehot_cal1_state_r[13]_i_1_n_0\
    );
\FSM_onehot_cal1_state_r[14]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \FSM_onehot_cal1_state_r_reg_n_0_[1]\,
      I1 => \FSM_onehot_cal1_state_r[16]_i_2_n_0\,
      O => \FSM_onehot_cal1_state_r[14]_i_1_n_0\
    );
\FSM_onehot_cal1_state_r[15]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"BA"
    )
        port map (
      I0 => \FSM_onehot_cal1_state_r[15]_i_2_n_0\,
      I1 => \FSM_onehot_cal1_state_r[15]_i_3_n_0\,
      I2 => p_12_in,
      O => \FSM_onehot_cal1_state_r[15]_i_1_n_0\
    );
\FSM_onehot_cal1_state_r[15]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4000"
    )
        port map (
      I0 => \FSM_onehot_cal1_state_r[16]_i_3_n_0\,
      I1 => mpr_dec_cpt_r_reg_n_0,
      I2 => \FSM_onehot_cal1_state_r_reg_n_0_[1]\,
      I3 => \FSM_onehot_cal1_state_r[16]_i_2_n_0\,
      O => \FSM_onehot_cal1_state_r[15]_i_2_n_0\
    );
\FSM_onehot_cal1_state_r[15]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000000002"
    )
        port map (
      I0 => \pi_rdval_cnt[5]_i_3_n_0\,
      I1 => \idel_dec_cnt_reg_n_0_[4]\,
      I2 => \idel_dec_cnt_reg_n_0_[2]\,
      I3 => \idel_dec_cnt_reg_n_0_[1]\,
      I4 => \idel_dec_cnt_reg_n_0_[0]\,
      I5 => \idel_dec_cnt_reg_n_0_[3]\,
      O => \FSM_onehot_cal1_state_r[15]_i_3_n_0\
    );
\FSM_onehot_cal1_state_r[16]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFF8000FF00"
    )
        port map (
      I0 => \FSM_onehot_cal1_state_r[16]_i_2_n_0\,
      I1 => \FSM_onehot_cal1_state_r_reg_n_0_[1]\,
      I2 => \FSM_onehot_cal1_state_r[16]_i_3_n_0\,
      I3 => mpr_dec_cpt_r_reg_n_0,
      I4 => \FSM_onehot_cal1_state_r[21]_i_2_n_0\,
      I5 => \FSM_onehot_cal1_state_r[16]_i_4_n_0\,
      O => \FSM_onehot_cal1_state_r[16]_i_1_n_0\
    );
\FSM_onehot_cal1_state_r[16]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000000100"
    )
        port map (
      I0 => \cnt_idel_dec_cpt_r_reg_n_0_[4]\,
      I1 => \cnt_idel_dec_cpt_r_reg_n_0_[3]\,
      I2 => \cnt_idel_dec_cpt_r_reg_n_0_[5]\,
      I3 => \cnt_idel_dec_cpt_r_reg_n_0_[0]\,
      I4 => \cnt_idel_dec_cpt_r_reg_n_0_[2]\,
      I5 => \cnt_idel_dec_cpt_r_reg_n_0_[1]\,
      O => \FSM_onehot_cal1_state_r[16]_i_2_n_0\
    );
\FSM_onehot_cal1_state_r[16]_i_3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => idelay_tap_cnt_r(0),
      I1 => \mpr_4to1.inhibit_edge_detect_r_i_2_n_0\,
      O => \FSM_onehot_cal1_state_r[16]_i_3_n_0\
    );
\FSM_onehot_cal1_state_r[16]_i_4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => p_27_in,
      I1 => store_sr_req_r_i_2_n_0,
      O => \FSM_onehot_cal1_state_r[16]_i_4_n_0\
    );
\FSM_onehot_cal1_state_r[1]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"FE"
    )
        port map (
      I0 => mpr_dec_cpt_r,
      I1 => p_9_in,
      I2 => p_13_in,
      O => \FSM_onehot_cal1_state_r[1]_i_1_n_0\
    );
\FSM_onehot_cal1_state_r[20]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"BA"
    )
        port map (
      I0 => \FSM_onehot_cal1_state_r_reg_n_0_[16]\,
      I1 => idel_adj_inc_reg_n_0,
      I2 => \FSM_onehot_cal1_state_r_reg_n_0_[3]\,
      O => \FSM_onehot_cal1_state_r[20]_i_1_n_0\
    );
\FSM_onehot_cal1_state_r[21]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFF1F1F1F1F1F1F1"
    )
        port map (
      I0 => \FSM_onehot_cal1_state_r[21]_i_2_n_0\,
      I1 => mpr_dec_cpt_r_reg_n_0,
      I2 => \FSM_onehot_cal1_state_r[21]_i_3_n_0\,
      I3 => idel_mpr_pat_detect_r,
      I4 => p_0_in549_in,
      I5 => idel_pat_detect_valid_r_reg_n_0,
      O => \FSM_onehot_cal1_state_r[21]_i_1_n_0\
    );
\FSM_onehot_cal1_state_r[21]_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"7"
    )
        port map (
      I0 => p_12_in,
      I1 => \FSM_onehot_cal1_state_r[15]_i_3_n_0\,
      O => \FSM_onehot_cal1_state_r[21]_i_2_n_0\
    );
\FSM_onehot_cal1_state_r[21]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFE0E0E0"
    )
        port map (
      I0 => \gen_pat_match_div4.idel_pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.idel_pat0_data_match_r_reg_n_0\,
      I2 => p_34_in,
      I3 => \FSM_onehot_cal1_state_r_reg_n_0_[3]\,
      I4 => idel_adj_inc_reg_n_0,
      I5 => p_8_in,
      O => \FSM_onehot_cal1_state_r[21]_i_3_n_0\
    );
\FSM_onehot_cal1_state_r[22]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"080808080808AA08"
    )
        port map (
      I0 => idelay_tap_limit_r_reg_n_0,
      I1 => \FSM_onehot_cal1_state_r[22]_i_2_n_0\,
      I2 => idel_mpr_pat_detect_r,
      I3 => p_34_in,
      I4 => \gen_pat_match_div4.idel_pat0_data_match_r_reg_n_0\,
      I5 => \gen_pat_match_div4.idel_pat1_data_match_r_reg_n_0\,
      O => \FSM_onehot_cal1_state_r[22]_i_1_n_0\
    );
\FSM_onehot_cal1_state_r[22]_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => idel_pat_detect_valid_r_reg_n_0,
      I1 => p_0_in549_in,
      O => \FSM_onehot_cal1_state_r[22]_i_2_n_0\
    );
\FSM_onehot_cal1_state_r[29]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AAAA8000"
    )
        port map (
      I0 => store_sr_req_pulsed_r,
      I1 => found_edge_r_reg_n_0,
      I2 => found_stable_eye_last_r,
      I3 => found_first_edge_r_reg_n_0,
      I4 => tap_limit_cpt_r,
      O => \FSM_onehot_cal1_state_r[29]_i_1_n_0\
    );
\FSM_onehot_cal1_state_r[2]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0404040404045504"
    )
        port map (
      I0 => idelay_tap_limit_r_reg_n_0,
      I1 => \FSM_onehot_cal1_state_r[22]_i_2_n_0\,
      I2 => idel_mpr_pat_detect_r,
      I3 => p_34_in,
      I4 => \gen_pat_match_div4.idel_pat0_data_match_r_reg_n_0\,
      I5 => \gen_pat_match_div4.idel_pat1_data_match_r_reg_n_0\,
      O => \FSM_onehot_cal1_state_r[2]_i_1_n_0\
    );
\FSM_onehot_cal1_state_r[34]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFF7500"
    )
        port map (
      I0 => \FSM_onehot_cal1_state_r[34]_i_3_n_0\,
      I1 => \FSM_onehot_cal1_state_r[34]_i_4_n_0\,
      I2 => detect_edge_done_r,
      I3 => \FSM_onehot_cal1_state_r[34]_i_5_n_0\,
      I4 => \FSM_onehot_cal1_state_r[34]_i_6_n_0\,
      I5 => mpr_dec_cpt_r,
      O => \FSM_onehot_cal1_state_r[34]_i_1_n_0\
    );
\FSM_onehot_cal1_state_r[34]_i_10\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFF88F8"
    )
        port map (
      I0 => prech_done,
      I1 => cal1_prech_req_r,
      I2 => p_27_in,
      I3 => cal1_wait_r,
      I4 => \FSM_onehot_cal1_state_r_reg_n_0_[12]\,
      O => \FSM_onehot_cal1_state_r[34]_i_10_n_0\
    );
\FSM_onehot_cal1_state_r[34]_i_11\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFFE"
    )
        port map (
      I0 => p_0_in549_in,
      I1 => p_0_in541_in,
      I2 => \FSM_onehot_cal1_state_r_reg_n_0_[1]\,
      I3 => cal1_dq_idel_inc,
      O => \FSM_onehot_cal1_state_r[34]_i_11_n_0\
    );
\FSM_onehot_cal1_state_r[34]_i_12\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000000002"
    )
        port map (
      I0 => \FSM_onehot_cal1_state_r[34]_i_4_n_0\,
      I1 => p_9_in,
      I2 => p_0_in549_in,
      I3 => p_0_in541_in,
      I4 => \FSM_onehot_cal1_state_r[34]_i_13_n_0\,
      I5 => \cal1_state_r1[2]_i_2_n_0\,
      O => \FSM_onehot_cal1_state_r[34]_i_12_n_0\
    );
\FSM_onehot_cal1_state_r[34]_i_13\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"FE"
    )
        port map (
      I0 => \FSM_onehot_cal1_state_r_reg_n_0_[29]\,
      I1 => \FSM_onehot_cal1_state_r_reg_n_0_[8]\,
      I2 => p_8_in,
      O => \FSM_onehot_cal1_state_r[34]_i_13_n_0\
    );
\FSM_onehot_cal1_state_r[34]_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => p_0_in549_in,
      I1 => idel_pat_detect_valid_r_reg_n_0,
      O => \FSM_onehot_cal1_state_r[34]_i_2_n_0\
    );
\FSM_onehot_cal1_state_r[34]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000000100"
    )
        port map (
      I0 => cal1_dq_idel_inc,
      I1 => \FSM_onehot_cal1_state_r_reg_n_0_[1]\,
      I2 => \FSM_onehot_cal1_state_r[34]_i_8_n_0\,
      I3 => cal1_wait_r,
      I4 => \FSM_onehot_cal1_state_r_reg_n_0_[29]\,
      I5 => \FSM_onehot_cal1_state_r_reg_n_0_[15]\,
      O => \FSM_onehot_cal1_state_r[34]_i_3_n_0\
    );
\FSM_onehot_cal1_state_r[34]_i_4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => p_34_in,
      I1 => store_sr_req_pulsed_r,
      O => \FSM_onehot_cal1_state_r[34]_i_4_n_0\
    );
\FSM_onehot_cal1_state_r[34]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFFFE"
    )
        port map (
      I0 => \FSM_onehot_cal1_state_r[34]_i_9_n_0\,
      I1 => p_14_in,
      I2 => \FSM_onehot_cal1_state_r_reg_n_0_[3]\,
      I3 => \FSM_onehot_cal1_state_r_reg_n_0_[15]\,
      I4 => \FSM_onehot_cal1_state_r_reg_n_0_[16]\,
      I5 => p_13_in,
      O => \FSM_onehot_cal1_state_r[34]_i_5_n_0\
    );
\FSM_onehot_cal1_state_r[34]_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFF40F04040"
    )
        port map (
      I0 => mpr_rdlvl_start_r,
      I1 => mpr_rdlvl_start_r_reg_0,
      I2 => \FSM_onehot_cal1_state_r_reg_n_0_[7]\,
      I3 => rdlvl_stg1_start_r,
      I4 => rdlvl_stg1_start_r_reg_0,
      I5 => \FSM_onehot_cal1_state_r[34]_i_10_n_0\,
      O => \FSM_onehot_cal1_state_r[34]_i_6_n_0\
    );
\FSM_onehot_cal1_state_r[34]_i_7\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => p_27_in,
      I1 => store_sr_req_r_i_2_n_0,
      O => mpr_dec_cpt_r
    );
\FSM_onehot_cal1_state_r[34]_i_8\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => p_0_in541_in,
      I1 => p_0_in549_in,
      O => \FSM_onehot_cal1_state_r[34]_i_8_n_0\
    );
\FSM_onehot_cal1_state_r[34]_i_9\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000FFFFFFFE"
    )
        port map (
      I0 => cal1_wait_cnt_en_r_i_2_n_0,
      I1 => p_9_in,
      I2 => \FSM_onehot_cal1_state_r_reg_n_0_[29]\,
      I3 => detect_edge_done_r,
      I4 => \FSM_onehot_cal1_state_r[34]_i_11_n_0\,
      I5 => \FSM_onehot_cal1_state_r[34]_i_12_n_0\,
      O => \FSM_onehot_cal1_state_r[34]_i_9_n_0\
    );
\FSM_onehot_cal1_state_r[4]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => mpr_dec_cpt_r_reg_n_0,
      I1 => \FSM_onehot_cal1_state_r[16]_i_2_n_0\,
      I2 => \FSM_onehot_cal1_state_r_reg_n_0_[1]\,
      O => \FSM_onehot_cal1_state_r[4]_i_1_n_0\
    );
\FSM_onehot_cal1_state_r[5]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000002"
    )
        port map (
      I0 => p_0_in541_in,
      I1 => \FSM_onehot_cal1_state_r[5]_i_2_n_0\,
      I2 => regl_rank_cnt(1),
      I3 => regl_rank_cnt(0),
      I4 => \FSM_onehot_cal1_state_r[5]_i_3_n_0\,
      O => \FSM_onehot_cal1_state_r[5]_i_1_n_0\
    );
\FSM_onehot_cal1_state_r[5]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFFD"
    )
        port map (
      I0 => done_cnt(0),
      I1 => done_cnt(1),
      I2 => done_cnt(3),
      I3 => done_cnt(2),
      O => \FSM_onehot_cal1_state_r[5]_i_2_n_0\
    );
\FSM_onehot_cal1_state_r[5]_i_3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"BFFF"
    )
        port map (
      I0 => regl_dqs_cnt(3),
      I1 => regl_dqs_cnt(1),
      I2 => regl_dqs_cnt(0),
      I3 => regl_dqs_cnt(2),
      O => \FSM_onehot_cal1_state_r[5]_i_3_n_0\
    );
\FSM_onehot_cal1_state_r[6]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"44444444F4444444"
    )
        port map (
      I0 => \FSM_onehot_cal1_state_r[6]_i_2_n_0\,
      I1 => p_0_in541_in,
      I2 => cal1_prech_req_r,
      I3 => \cal1_cnt_cpt_r_reg_n_0_[1]\,
      I4 => \cal1_cnt_cpt_r_reg_n_0_[0]\,
      I5 => \^cal1_cnt_cpt_r_reg[2]_1\,
      O => \FSM_onehot_cal1_state_r[6]_i_1_n_0\
    );
\FSM_onehot_cal1_state_r[6]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0001"
    )
        port map (
      I0 => \FSM_onehot_cal1_state_r[5]_i_3_n_0\,
      I1 => regl_rank_cnt(0),
      I2 => regl_rank_cnt(1),
      I3 => \FSM_onehot_cal1_state_r[5]_i_2_n_0\,
      O => \FSM_onehot_cal1_state_r[6]_i_2_n_0\
    );
\FSM_onehot_cal1_state_r[6]_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"FD"
    )
        port map (
      I0 => \cal1_cnt_cpt_r_reg_n_0_[2]\,
      I1 => \rnk_cnt_r_reg_n_0_[0]\,
      I2 => \rnk_cnt_r_reg_n_0_[1]\,
      O => \^cal1_cnt_cpt_r_reg[2]_1\
    );
\FSM_onehot_cal1_state_r[7]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8000800080000000"
    )
        port map (
      I0 => cal1_prech_req_r,
      I1 => \cal1_cnt_cpt_r_reg_n_0_[1]\,
      I2 => \cal1_cnt_cpt_r_reg_n_0_[0]\,
      I3 => \cal1_cnt_cpt_r_reg_n_0_[2]\,
      I4 => \rnk_cnt_r_reg_n_0_[0]\,
      I5 => \rnk_cnt_r_reg_n_0_[1]\,
      O => \FSM_onehot_cal1_state_r[7]_i_1_n_0\
    );
\FSM_onehot_cal1_state_r[8]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2AAA"
    )
        port map (
      I0 => cal1_prech_req_r,
      I1 => \cal1_cnt_cpt_r_reg_n_0_[2]\,
      I2 => \cal1_cnt_cpt_r_reg_n_0_[0]\,
      I3 => \cal1_cnt_cpt_r_reg_n_0_[1]\,
      O => \FSM_onehot_cal1_state_r[8]_i_1_n_0\
    );
\FSM_onehot_cal1_state_r[9]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => mpr_rdlvl_start_r,
      I1 => mpr_rdlvl_start_r_reg_0,
      I2 => \FSM_onehot_cal1_state_r_reg_n_0_[7]\,
      O => \FSM_onehot_cal1_state_r[9]_i_1_n_0\
    );
\FSM_onehot_cal1_state_r_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => \FSM_onehot_cal1_state_r[34]_i_1_n_0\,
      D => \FSM_onehot_cal1_state_r_reg_n_0_[29]\,
      Q => p_13_in,
      R => SR(1)
    );
\FSM_onehot_cal1_state_r_reg[10]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => \FSM_onehot_cal1_state_r[34]_i_1_n_0\,
      D => \FSM_onehot_cal1_state_r[10]_i_1_n_0\,
      Q => p_0_in549_in,
      R => SR(1)
    );
\FSM_onehot_cal1_state_r_reg[11]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => \FSM_onehot_cal1_state_r[34]_i_1_n_0\,
      D => \FSM_onehot_cal1_state_r[11]_i_1_n_0\,
      Q => p_14_in,
      R => SR(1)
    );
\FSM_onehot_cal1_state_r_reg[12]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => \FSM_onehot_cal1_state_r[34]_i_1_n_0\,
      D => p_14_in,
      Q => \FSM_onehot_cal1_state_r_reg_n_0_[12]\,
      R => SR(1)
    );
\FSM_onehot_cal1_state_r_reg[13]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => \FSM_onehot_cal1_state_r[34]_i_1_n_0\,
      D => \FSM_onehot_cal1_state_r[13]_i_1_n_0\,
      Q => p_27_in,
      R => SR(1)
    );
\FSM_onehot_cal1_state_r_reg[14]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => \FSM_onehot_cal1_state_r[34]_i_1_n_0\,
      D => \FSM_onehot_cal1_state_r[14]_i_1_n_0\,
      Q => p_9_in,
      R => SR(1)
    );
\FSM_onehot_cal1_state_r_reg[15]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => \FSM_onehot_cal1_state_r[34]_i_1_n_0\,
      D => \FSM_onehot_cal1_state_r[15]_i_1_n_0\,
      Q => \FSM_onehot_cal1_state_r_reg_n_0_[15]\,
      R => SR(1)
    );
\FSM_onehot_cal1_state_r_reg[16]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => \FSM_onehot_cal1_state_r[34]_i_1_n_0\,
      D => \FSM_onehot_cal1_state_r[16]_i_1_n_0\,
      Q => \FSM_onehot_cal1_state_r_reg_n_0_[16]\,
      R => SR(1)
    );
\FSM_onehot_cal1_state_r_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => \FSM_onehot_cal1_state_r[34]_i_1_n_0\,
      D => \FSM_onehot_cal1_state_r[1]_i_1_n_0\,
      Q => \FSM_onehot_cal1_state_r_reg_n_0_[1]\,
      R => SR(1)
    );
\FSM_onehot_cal1_state_r_reg[20]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => \FSM_onehot_cal1_state_r[34]_i_1_n_0\,
      D => \FSM_onehot_cal1_state_r[20]_i_1_n_0\,
      Q => p_34_in,
      R => SR(1)
    );
\FSM_onehot_cal1_state_r_reg[21]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => \FSM_onehot_cal1_state_r[34]_i_1_n_0\,
      D => \FSM_onehot_cal1_state_r[21]_i_1_n_0\,
      Q => store_sr_req_pulsed_r,
      R => SR(1)
    );
\FSM_onehot_cal1_state_r_reg[22]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => \FSM_onehot_cal1_state_r[34]_i_1_n_0\,
      D => \FSM_onehot_cal1_state_r[22]_i_1_n_0\,
      Q => \FSM_onehot_cal1_state_r_reg_n_0_[22]\,
      R => SR(1)
    );
\FSM_onehot_cal1_state_r_reg[29]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => \FSM_onehot_cal1_state_r[34]_i_1_n_0\,
      D => \FSM_onehot_cal1_state_r[29]_i_1_n_0\,
      Q => \FSM_onehot_cal1_state_r_reg_n_0_[29]\,
      R => SR(1)
    );
\FSM_onehot_cal1_state_r_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => \FSM_onehot_cal1_state_r[34]_i_1_n_0\,
      D => \FSM_onehot_cal1_state_r[2]_i_1_n_0\,
      Q => cal1_dq_idel_inc,
      R => SR(1)
    );
\FSM_onehot_cal1_state_r_reg[31]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => \FSM_onehot_cal1_state_r[34]_i_1_n_0\,
      D => \FSM_onehot_cal1_state_r_reg_n_0_[12]\,
      Q => p_8_in,
      R => SR(1)
    );
\FSM_onehot_cal1_state_r_reg[32]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => \FSM_onehot_cal1_state_r[34]_i_1_n_0\,
      D => \FSM_onehot_cal1_state_r_reg_n_0_[15]\,
      Q => p_12_in,
      R => SR(1)
    );
\FSM_onehot_cal1_state_r_reg[34]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => \FSM_onehot_cal1_state_r[34]_i_1_n_0\,
      D => \FSM_onehot_cal1_state_r[34]_i_2_n_0\,
      Q => p_2_in,
      R => SR(1)
    );
\FSM_onehot_cal1_state_r_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => \FSM_onehot_cal1_state_r[34]_i_1_n_0\,
      D => cal1_dq_idel_inc,
      Q => \FSM_onehot_cal1_state_r_reg_n_0_[3]\,
      R => SR(1)
    );
\FSM_onehot_cal1_state_r_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => \FSM_onehot_cal1_state_r[34]_i_1_n_0\,
      D => \FSM_onehot_cal1_state_r[4]_i_1_n_0\,
      Q => cal1_prech_req_r,
      R => SR(1)
    );
\FSM_onehot_cal1_state_r_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => \FSM_onehot_cal1_state_r[34]_i_1_n_0\,
      D => \FSM_onehot_cal1_state_r[5]_i_1_n_0\,
      Q => rdlvl_stg1_done_int,
      R => SR(1)
    );
\FSM_onehot_cal1_state_r_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => \FSM_onehot_cal1_state_r[34]_i_1_n_0\,
      D => \FSM_onehot_cal1_state_r[6]_i_1_n_0\,
      Q => p_0_in541_in,
      R => SR(1)
    );
\FSM_onehot_cal1_state_r_reg[7]\: unisim.vcomponents.FDSE
    generic map(
      INIT => '1'
    )
        port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => \FSM_onehot_cal1_state_r[34]_i_1_n_0\,
      D => \FSM_onehot_cal1_state_r[7]_i_1_n_0\,
      Q => \FSM_onehot_cal1_state_r_reg_n_0_[7]\,
      S => SR(1)
    );
\FSM_onehot_cal1_state_r_reg[8]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => \FSM_onehot_cal1_state_r[34]_i_1_n_0\,
      D => \FSM_onehot_cal1_state_r[8]_i_1_n_0\,
      Q => \FSM_onehot_cal1_state_r_reg_n_0_[8]\,
      R => SR(1)
    );
\FSM_onehot_cal1_state_r_reg[9]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => \FSM_onehot_cal1_state_r[34]_i_1_n_0\,
      D => \FSM_onehot_cal1_state_r[9]_i_1_n_0\,
      Q => p_1_in26_in,
      R => SR(1)
    );
\cal1_cnt_cpt_r[0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0F4F50505A5A5050"
    )
        port map (
      I0 => p_0_in541_in,
      I1 => \cal1_cnt_cpt_r_reg_n_0_[1]\,
      I2 => \cal1_cnt_cpt_r_reg_n_0_[0]\,
      I3 => \^cal1_cnt_cpt_r_reg[2]_1\,
      I4 => cal1_prech_req_r,
      I5 => prech_done,
      O => \cal1_cnt_cpt_r[0]_i_1_n_0\
    );
\cal1_cnt_cpt_r[1]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"3C7C44446C6C4444"
    )
        port map (
      I0 => p_0_in541_in,
      I1 => \cal1_cnt_cpt_r_reg_n_0_[1]\,
      I2 => \cal1_cnt_cpt_r_reg_n_0_[0]\,
      I3 => \^cal1_cnt_cpt_r_reg[2]_1\,
      I4 => cal1_prech_req_r,
      I5 => prech_done,
      O => \cal1_cnt_cpt_r[1]_i_1_n_0\
    );
\cal1_cnt_cpt_r[2]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"73CC550077885500"
    )
        port map (
      I0 => p_0_in541_in,
      I1 => \cal1_cnt_cpt_r[2]_i_2_n_0\,
      I2 => \cal1_cnt_cpt_r[2]_i_3_n_0\,
      I3 => \cal1_cnt_cpt_r_reg_n_0_[2]\,
      I4 => cal1_prech_req_r,
      I5 => prech_done,
      O => \cal1_cnt_cpt_r[2]_i_1_n_0\
    );
\cal1_cnt_cpt_r[2]_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \cal1_cnt_cpt_r_reg_n_0_[0]\,
      I1 => \cal1_cnt_cpt_r_reg_n_0_[1]\,
      O => \cal1_cnt_cpt_r[2]_i_2_n_0\
    );
\cal1_cnt_cpt_r[2]_i_3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \rnk_cnt_r_reg_n_0_[1]\,
      I1 => \rnk_cnt_r_reg_n_0_[0]\,
      O => \cal1_cnt_cpt_r[2]_i_3_n_0\
    );
\cal1_cnt_cpt_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \cal1_cnt_cpt_r[0]_i_1_n_0\,
      Q => \cal1_cnt_cpt_r_reg_n_0_[0]\,
      R => \rdlvl_dqs_tap_cnt_r_reg[0][0][2]_0\(1)
    );
\cal1_cnt_cpt_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \cal1_cnt_cpt_r[1]_i_1_n_0\,
      Q => \cal1_cnt_cpt_r_reg_n_0_[1]\,
      R => \rdlvl_dqs_tap_cnt_r_reg[0][0][2]_0\(1)
    );
\cal1_cnt_cpt_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \cal1_cnt_cpt_r[2]_i_1_n_0\,
      Q => \cal1_cnt_cpt_r_reg_n_0_[2]\,
      R => \rdlvl_dqs_tap_cnt_r_reg[0][0][2]_0\(1)
    );
cal1_dlyce_cpt_r_i_1: unisim.vcomponents.LUT3
    generic map(
      INIT => X"BA"
    )
        port map (
      I0 => \FSM_onehot_cal1_state_r_reg_n_0_[1]\,
      I1 => tap_limit_cpt_r,
      I2 => \FSM_onehot_cal1_state_r_reg_n_0_[12]\,
      O => cal1_dlyce_cpt_r
    );
cal1_dlyce_cpt_r_reg: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => cal1_dlyce_cpt_r,
      Q => cal1_dlyce_cpt_r_reg_n_0,
      R => \rdlvl_dqs_tap_cnt_r_reg[0][0][2]_0\(1)
    );
cal1_dlyinc_cpt_r_i_1: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \FSM_onehot_cal1_state_r_reg_n_0_[12]\,
      I1 => tap_limit_cpt_r,
      O => cal1_dlyinc_cpt_r
    );
cal1_dlyinc_cpt_r_reg: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => cal1_dlyinc_cpt_r,
      Q => cal1_dlyinc_cpt_r_reg_n_0,
      R => \rdlvl_dqs_tap_cnt_r_reg[0][0][2]_0\(1)
    );
cal1_dq_idel_ce_i_1: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => cal1_dq_idel_inc,
      I1 => \FSM_onehot_cal1_state_r_reg_n_0_[15]\,
      O => cal1_dq_idel_ce
    );
cal1_dq_idel_ce_reg: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => cal1_dq_idel_ce,
      Q => \^idelay_ce_int\,
      R => \rdlvl_dqs_tap_cnt_r_reg[0][0][2]_0\(1)
    );
cal1_dq_idel_inc_reg: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => cal1_dq_idel_inc,
      Q => \^idelay_inc_int\,
      R => \rdlvl_dqs_tap_cnt_r_reg[0][0][2]_0\(1)
    );
cal1_prech_req_r_reg: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => cal1_prech_req_r,
      Q => \cal1_prech_req_r__0\,
      R => \rdlvl_dqs_tap_cnt_r_reg[0][0][2]_0\(1)
    );
\cal1_state_r1[0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFFFE"
    )
        port map (
      I0 => p_0_in541_in,
      I1 => rdlvl_stg1_done_int,
      I2 => \cal1_state_r1[0]_i_2_n_0\,
      I3 => p_9_in,
      I4 => \FSM_onehot_cal1_state_r_reg_n_0_[29]\,
      I5 => \cal1_state_r1[0]_i_3_n_0\,
      O => \cal1_state_r1[0]_i_1_n_0\
    );
\cal1_state_r1[0]_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => p_34_in,
      I1 => p_0_in549_in,
      O => \cal1_state_r1[0]_i_2_n_0\
    );
\cal1_state_r1[0]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFFFE"
    )
        port map (
      I0 => p_27_in,
      I1 => p_14_in,
      I2 => p_1_in26_in,
      I3 => \FSM_onehot_cal1_state_r_reg_n_0_[3]\,
      I4 => p_12_in,
      I5 => \FSM_onehot_cal1_state_r_reg_n_0_[12]\,
      O => \cal1_state_r1[0]_i_3_n_0\
    );
\cal1_state_r1[1]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFFFE"
    )
        port map (
      I0 => \cal1_state_r1[3]_i_3_n_0\,
      I1 => \cal1_state_r1[1]_i_2_n_0\,
      I2 => p_12_in,
      I3 => p_2_in,
      I4 => cal1_prech_req_r,
      I5 => \FSM_onehot_cal1_state_r_reg_n_0_[15]\,
      O => \cal1_state_r1[1]_i_1_n_0\
    );
\cal1_state_r1[1]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFFE"
    )
        port map (
      I0 => p_13_in,
      I1 => \FSM_onehot_cal1_state_r_reg_n_0_[16]\,
      I2 => p_0_in549_in,
      I3 => p_34_in,
      O => \cal1_state_r1[1]_i_2_n_0\
    );
\cal1_state_r1[2]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFFFE"
    )
        port map (
      I0 => \cal1_state_r1[3]_i_2_n_0\,
      I1 => \FSM_onehot_cal1_state_r_reg_n_0_[3]\,
      I2 => \FSM_onehot_cal1_state_r_reg_n_0_[15]\,
      I3 => p_1_in26_in,
      I4 => rdlvl_stg1_done_int,
      I5 => \cal1_state_r1[2]_i_2_n_0\,
      O => \cal1_state_r1[2]_i_1_n_0\
    );
\cal1_state_r1[2]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFFE"
    )
        port map (
      I0 => p_12_in,
      I1 => p_2_in,
      I2 => \FSM_onehot_cal1_state_r_reg_n_0_[1]\,
      I3 => cal1_dq_idel_inc,
      O => \cal1_state_r1[2]_i_2_n_0\
    );
\cal1_state_r1[3]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFFFE"
    )
        port map (
      I0 => \FSM_onehot_cal1_state_r_reg_n_0_[12]\,
      I1 => \FSM_onehot_cal1_state_r_reg_n_0_[1]\,
      I2 => store_sr_req_pulsed_r,
      I3 => \FSM_onehot_cal1_state_r[10]_i_1_n_0\,
      I4 => \cal1_state_r1[3]_i_2_n_0\,
      I5 => \cal1_state_r1[3]_i_3_n_0\,
      O => \cal1_state_r1[3]_i_1_n_0\
    );
\cal1_state_r1[3]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFFE"
    )
        port map (
      I0 => cal1_prech_req_r,
      I1 => p_0_in549_in,
      I2 => \FSM_onehot_cal1_state_r_reg_n_0_[22]\,
      I3 => p_9_in,
      O => \cal1_state_r1[3]_i_2_n_0\
    );
\cal1_state_r1[3]_i_3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFFE"
    )
        port map (
      I0 => p_0_in541_in,
      I1 => rdlvl_stg1_done_int,
      I2 => \FSM_onehot_cal1_state_r_reg_n_0_[29]\,
      I3 => p_8_in,
      O => \cal1_state_r1[3]_i_3_n_0\
    );
\cal1_state_r1[4]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFFFFE"
    )
        port map (
      I0 => p_2_in,
      I1 => p_1_in26_in,
      I2 => p_0_in541_in,
      I3 => p_0_in549_in,
      I4 => \FSM_onehot_cal1_state_r_reg_n_0_[22]\,
      O => \cal1_state_r1[4]_i_1_n_0\
    );
\cal1_state_r1[5]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"FE"
    )
        port map (
      I0 => \FSM_onehot_cal1_state_r_reg_n_0_[8]\,
      I1 => p_14_in,
      I2 => p_13_in,
      O => \cal1_state_r1[5]_i_1_n_0\
    );
\cal1_state_r1_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \cal1_state_r1[0]_i_1_n_0\,
      Q => \cal1_state_r1_reg_n_0_[0]\,
      R => '0'
    );
\cal1_state_r1_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \cal1_state_r1[1]_i_1_n_0\,
      Q => \cal1_state_r1_reg_n_0_[1]\,
      R => '0'
    );
\cal1_state_r1_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \cal1_state_r1[2]_i_1_n_0\,
      Q => \cal1_state_r1_reg_n_0_[2]\,
      R => '0'
    );
\cal1_state_r1_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \cal1_state_r1[3]_i_1_n_0\,
      Q => \cal1_state_r1_reg_n_0_[3]\,
      R => '0'
    );
\cal1_state_r1_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \cal1_state_r1[4]_i_1_n_0\,
      Q => \cal1_state_r1_reg_n_0_[4]\,
      R => '0'
    );
\cal1_state_r1_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \cal1_state_r1[5]_i_1_n_0\,
      Q => \cal1_state_r1_reg_n_0_[5]\,
      R => '0'
    );
cal1_wait_cnt_en_r_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFFFE"
    )
        port map (
      I0 => cal1_wait_cnt_en_r_i_2_n_0,
      I1 => p_9_in,
      I2 => p_13_in,
      I3 => \FSM_onehot_cal1_state_r_reg_n_0_[3]\,
      I4 => \FSM_onehot_cal1_state_r_reg_n_0_[16]\,
      I5 => cal1_wait_cnt_en_r_i_3_n_0,
      O => cal1_wait_cnt_en_r0
    );
cal1_wait_cnt_en_r_i_2: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFFE"
    )
        port map (
      I0 => p_12_in,
      I1 => p_2_in,
      I2 => \FSM_onehot_cal1_state_r_reg_n_0_[8]\,
      I3 => p_8_in,
      O => cal1_wait_cnt_en_r_i_2_n_0
    );
cal1_wait_cnt_en_r_i_3: unisim.vcomponents.LUT3
    generic map(
      INIT => X"FE"
    )
        port map (
      I0 => p_1_in26_in,
      I1 => p_14_in,
      I2 => p_27_in,
      O => cal1_wait_cnt_en_r_i_3_n_0
    );
cal1_wait_cnt_en_r_reg: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => cal1_wait_cnt_en_r0,
      Q => cal1_wait_cnt_en_r,
      R => '0'
    );
\cal1_wait_cnt_r[0]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => cal1_wait_cnt_r_reg(0),
      O => \p_0_in__1\(0)
    );
\cal1_wait_cnt_r[1]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => cal1_wait_cnt_r_reg(1),
      I1 => cal1_wait_cnt_r_reg(0),
      O => \p_0_in__1\(1)
    );
\cal1_wait_cnt_r[2]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"6A"
    )
        port map (
      I0 => cal1_wait_cnt_r_reg(2),
      I1 => cal1_wait_cnt_r_reg(0),
      I2 => cal1_wait_cnt_r_reg(1),
      O => \p_0_in__1\(2)
    );
\cal1_wait_cnt_r[3]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6AAA"
    )
        port map (
      I0 => cal1_wait_cnt_r_reg(3),
      I1 => cal1_wait_cnt_r_reg(1),
      I2 => cal1_wait_cnt_r_reg(0),
      I3 => cal1_wait_cnt_r_reg(2),
      O => \p_0_in__1\(3)
    );
\cal1_wait_cnt_r[4]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"40000000FFFFFFFF"
    )
        port map (
      I0 => cal1_wait_cnt_r_reg(4),
      I1 => cal1_wait_cnt_r_reg(3),
      I2 => cal1_wait_cnt_r_reg(1),
      I3 => cal1_wait_cnt_r_reg(0),
      I4 => cal1_wait_cnt_r_reg(2),
      I5 => cal1_wait_cnt_en_r,
      O => \cal1_wait_cnt_r[4]_i_1_n_0\
    );
\cal1_wait_cnt_r[4]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"6AAAAAAA"
    )
        port map (
      I0 => cal1_wait_cnt_r_reg(4),
      I1 => cal1_wait_cnt_r_reg(2),
      I2 => cal1_wait_cnt_r_reg(0),
      I3 => cal1_wait_cnt_r_reg(1),
      I4 => cal1_wait_cnt_r_reg(3),
      O => \p_0_in__1\(4)
    );
\cal1_wait_cnt_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \p_0_in__1\(0),
      Q => cal1_wait_cnt_r_reg(0),
      R => \cal1_wait_cnt_r[4]_i_1_n_0\
    );
\cal1_wait_cnt_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \p_0_in__1\(1),
      Q => cal1_wait_cnt_r_reg(1),
      R => \cal1_wait_cnt_r[4]_i_1_n_0\
    );
\cal1_wait_cnt_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \p_0_in__1\(2),
      Q => cal1_wait_cnt_r_reg(2),
      R => \cal1_wait_cnt_r[4]_i_1_n_0\
    );
\cal1_wait_cnt_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \p_0_in__1\(3),
      Q => cal1_wait_cnt_r_reg(3),
      R => \cal1_wait_cnt_r[4]_i_1_n_0\
    );
\cal1_wait_cnt_r_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \p_0_in__1\(4),
      Q => cal1_wait_cnt_r_reg(4),
      R => \cal1_wait_cnt_r[4]_i_1_n_0\
    );
cal1_wait_r_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"DFFFFFFFFFFFFFFF"
    )
        port map (
      I0 => cal1_wait_cnt_en_r,
      I1 => cal1_wait_cnt_r_reg(4),
      I2 => cal1_wait_cnt_r_reg(3),
      I3 => cal1_wait_cnt_r_reg(1),
      I4 => cal1_wait_cnt_r_reg(0),
      I5 => cal1_wait_cnt_r_reg(2),
      O => cal1_wait_r_i_1_n_0
    );
cal1_wait_r_reg: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => cal1_wait_r_i_1_n_0,
      Q => cal1_wait_r,
      R => '0'
    );
\cnt_idel_dec_cpt_r[0]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFF7020"
    )
        port map (
      I0 => found_second_edge_r_reg_n_0,
      I1 => cnt_idel_dec_cpt_r1(0),
      I2 => \FSM_onehot_cal1_state_r_reg_n_0_[29]\,
      I3 => \cnt_idel_dec_cpt_r[0]_i_2_n_0\,
      I4 => \cnt_idel_dec_cpt_r[0]_i_3_n_0\,
      O => cnt_idel_dec_cpt_r(0)
    );
\cnt_idel_dec_cpt_r[0]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"B800B8FFB8FFB800"
    )
        port map (
      I0 => \cnt_idel_dec_cpt_r_reg[2]_i_10_n_6\,
      I1 => found_first_edge_r_reg_n_0,
      I2 => \tap_cnt_cpt_r_reg_n_0_[1]\,
      I3 => \cnt_idel_dec_cpt_r[4]_i_9_n_0\,
      I4 => \tap_cnt_cpt_r_reg_n_0_[0]\,
      I5 => \right_edge_taps_r_reg_n_0_[1]\,
      O => \cnt_idel_dec_cpt_r[0]_i_2_n_0\
    );
\cnt_idel_dec_cpt_r[0]_i_3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8F88"
    )
        port map (
      I0 => D(0),
      I1 => p_27_in,
      I2 => \cnt_idel_dec_cpt_r_reg_n_0_[0]\,
      I3 => \FSM_onehot_cal1_state_r_reg_n_0_[1]\,
      O => \cnt_idel_dec_cpt_r[0]_i_3_n_0\
    );
\cnt_idel_dec_cpt_r[1]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFF28AA2800"
    )
        port map (
      I0 => \FSM_onehot_cal1_state_r_reg_n_0_[29]\,
      I1 => cnt_idel_dec_cpt_r1(1),
      I2 => cnt_idel_dec_cpt_r1(0),
      I3 => found_second_edge_r_reg_n_0,
      I4 => \cnt_idel_dec_cpt_r[1]_i_2_n_0\,
      I5 => \cnt_idel_dec_cpt_r[1]_i_3_n_0\,
      O => cnt_idel_dec_cpt_r(1)
    );
\cnt_idel_dec_cpt_r[1]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8FFB800"
    )
        port map (
      I0 => \cnt_idel_dec_cpt_r_reg[2]_i_10_n_5\,
      I1 => found_first_edge_r_reg_n_0,
      I2 => \tap_cnt_cpt_r_reg_n_0_[2]\,
      I3 => \cnt_idel_dec_cpt_r[4]_i_9_n_0\,
      I4 => \cnt_idel_dec_cpt_r[1]_i_4_n_0\,
      O => \cnt_idel_dec_cpt_r[1]_i_2_n_0\
    );
\cnt_idel_dec_cpt_r[1]_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"F88F8888"
    )
        port map (
      I0 => D(1),
      I1 => p_27_in,
      I2 => \cnt_idel_dec_cpt_r_reg_n_0_[1]\,
      I3 => \cnt_idel_dec_cpt_r_reg_n_0_[0]\,
      I4 => \FSM_onehot_cal1_state_r_reg_n_0_[1]\,
      O => \cnt_idel_dec_cpt_r[1]_i_3_n_0\
    );
\cnt_idel_dec_cpt_r[1]_i_4\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4BB4"
    )
        port map (
      I0 => \tap_cnt_cpt_r_reg_n_0_[0]\,
      I1 => \right_edge_taps_r_reg_n_0_[1]\,
      I2 => \right_edge_taps_r_reg_n_0_[2]\,
      I3 => \tap_cnt_cpt_r_reg_n_0_[1]\,
      O => \cnt_idel_dec_cpt_r[1]_i_4_n_0\
    );
\cnt_idel_dec_cpt_r[2]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFF28AA2800"
    )
        port map (
      I0 => \FSM_onehot_cal1_state_r_reg_n_0_[29]\,
      I1 => cnt_idel_dec_cpt_r1(2),
      I2 => \cnt_idel_dec_cpt_r[2]_i_3_n_0\,
      I3 => found_second_edge_r_reg_n_0,
      I4 => \cnt_idel_dec_cpt_r[2]_i_4_n_0\,
      I5 => \cnt_idel_dec_cpt_r[2]_i_5_n_0\,
      O => cnt_idel_dec_cpt_r(2)
    );
\cnt_idel_dec_cpt_r[2]_i_11\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"2B22D4DDD4DD2B22"
    )
        port map (
      I0 => \right_edge_taps_r_reg_n_0_[2]\,
      I1 => \tap_cnt_cpt_r_reg_n_0_[1]\,
      I2 => \tap_cnt_cpt_r_reg_n_0_[0]\,
      I3 => \right_edge_taps_r_reg_n_0_[1]\,
      I4 => \right_edge_taps_r_reg_n_0_[3]\,
      I5 => \tap_cnt_cpt_r_reg_n_0_[2]\,
      O => \cnt_idel_dec_cpt_r[2]_i_11_n_0\
    );
\cnt_idel_dec_cpt_r[2]_i_12\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => \tap_cnt_cpt_r_reg_n_0_[3]\,
      I1 => \first_edge_taps_r_reg_n_0_[3]\,
      O => \cnt_idel_dec_cpt_r[2]_i_12_n_0\
    );
\cnt_idel_dec_cpt_r[2]_i_13\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => \tap_cnt_cpt_r_reg_n_0_[2]\,
      I1 => \first_edge_taps_r_reg_n_0_[2]\,
      O => \cnt_idel_dec_cpt_r[2]_i_13_n_0\
    );
\cnt_idel_dec_cpt_r[2]_i_14\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => \tap_cnt_cpt_r_reg_n_0_[1]\,
      I1 => \first_edge_taps_r_reg_n_0_[1]\,
      O => \cnt_idel_dec_cpt_r[2]_i_14_n_0\
    );
\cnt_idel_dec_cpt_r[2]_i_15\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => \tap_cnt_cpt_r_reg_n_0_[0]\,
      I1 => \first_edge_taps_r_reg_n_0_[0]\,
      O => \cnt_idel_dec_cpt_r[2]_i_15_n_0\
    );
\cnt_idel_dec_cpt_r[2]_i_3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => cnt_idel_dec_cpt_r1(1),
      I1 => cnt_idel_dec_cpt_r1(0),
      O => \cnt_idel_dec_cpt_r[2]_i_3_n_0\
    );
\cnt_idel_dec_cpt_r[2]_i_4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8FFB800"
    )
        port map (
      I0 => \cnt_idel_dec_cpt_r_reg[2]_i_10_n_4\,
      I1 => found_first_edge_r_reg_n_0,
      I2 => \tap_cnt_cpt_r_reg_n_0_[3]\,
      I3 => \cnt_idel_dec_cpt_r[4]_i_9_n_0\,
      I4 => \cnt_idel_dec_cpt_r[2]_i_11_n_0\,
      O => \cnt_idel_dec_cpt_r[2]_i_4_n_0\
    );
\cnt_idel_dec_cpt_r[2]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F888F888F88888F8"
    )
        port map (
      I0 => D(2),
      I1 => p_27_in,
      I2 => \FSM_onehot_cal1_state_r_reg_n_0_[1]\,
      I3 => \cnt_idel_dec_cpt_r_reg_n_0_[2]\,
      I4 => \cnt_idel_dec_cpt_r_reg_n_0_[0]\,
      I5 => \cnt_idel_dec_cpt_r_reg_n_0_[1]\,
      O => \cnt_idel_dec_cpt_r[2]_i_5_n_0\
    );
\cnt_idel_dec_cpt_r[2]_i_6\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => \second_edge_taps_r_reg_n_0_[3]\,
      I1 => \first_edge_taps_r_reg_n_0_[3]\,
      O => \cnt_idel_dec_cpt_r[2]_i_6_n_0\
    );
\cnt_idel_dec_cpt_r[2]_i_7\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => \second_edge_taps_r_reg_n_0_[2]\,
      I1 => \first_edge_taps_r_reg_n_0_[2]\,
      O => \cnt_idel_dec_cpt_r[2]_i_7_n_0\
    );
\cnt_idel_dec_cpt_r[2]_i_8\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => \second_edge_taps_r_reg_n_0_[1]\,
      I1 => \first_edge_taps_r_reg_n_0_[1]\,
      O => \cnt_idel_dec_cpt_r[2]_i_8_n_0\
    );
\cnt_idel_dec_cpt_r[2]_i_9\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => \second_edge_taps_r_reg_n_0_[0]\,
      I1 => \first_edge_taps_r_reg_n_0_[0]\,
      O => \cnt_idel_dec_cpt_r[2]_i_9_n_0\
    );
\cnt_idel_dec_cpt_r[3]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFF28AA2800"
    )
        port map (
      I0 => \FSM_onehot_cal1_state_r_reg_n_0_[29]\,
      I1 => cnt_idel_dec_cpt_r1(3),
      I2 => \cnt_idel_dec_cpt_r[3]_i_2_n_0\,
      I3 => found_second_edge_r_reg_n_0,
      I4 => \cnt_idel_dec_cpt_r[3]_i_3_n_0\,
      I5 => \cnt_idel_dec_cpt_r[3]_i_4_n_0\,
      O => cnt_idel_dec_cpt_r(3)
    );
\cnt_idel_dec_cpt_r[3]_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"80"
    )
        port map (
      I0 => cnt_idel_dec_cpt_r1(2),
      I1 => cnt_idel_dec_cpt_r1(0),
      I2 => cnt_idel_dec_cpt_r1(1),
      O => \cnt_idel_dec_cpt_r[3]_i_2_n_0\
    );
\cnt_idel_dec_cpt_r[3]_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8FFB800"
    )
        port map (
      I0 => \cnt_idel_dec_cpt_r_reg[4]_i_8_n_7\,
      I1 => found_first_edge_r_reg_n_0,
      I2 => \tap_cnt_cpt_r_reg_n_0_[4]\,
      I3 => \cnt_idel_dec_cpt_r[4]_i_9_n_0\,
      I4 => \cnt_idel_dec_cpt_r[3]_i_5_n_0\,
      O => \cnt_idel_dec_cpt_r[3]_i_3_n_0\
    );
\cnt_idel_dec_cpt_r[3]_i_4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"8FF88888"
    )
        port map (
      I0 => D(3),
      I1 => p_27_in,
      I2 => \cnt_idel_dec_cpt_r_reg_n_0_[3]\,
      I3 => \cnt_idel_dec_cpt_r[4]_i_11_n_0\,
      I4 => \FSM_onehot_cal1_state_r_reg_n_0_[1]\,
      O => \cnt_idel_dec_cpt_r[3]_i_4_n_0\
    );
\cnt_idel_dec_cpt_r[3]_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"96"
    )
        port map (
      I0 => \cnt_idel_dec_cpt_r[4]_i_14_n_0\,
      I1 => \right_edge_taps_r_reg_n_0_[4]\,
      I2 => \tap_cnt_cpt_r_reg_n_0_[3]\,
      O => \cnt_idel_dec_cpt_r[3]_i_5_n_0\
    );
\cnt_idel_dec_cpt_r[4]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFF28AA2800"
    )
        port map (
      I0 => \FSM_onehot_cal1_state_r_reg_n_0_[29]\,
      I1 => cnt_idel_dec_cpt_r1(4),
      I2 => \cnt_idel_dec_cpt_r[4]_i_3_n_0\,
      I3 => found_second_edge_r_reg_n_0,
      I4 => \cnt_idel_dec_cpt_r[4]_i_4_n_0\,
      I5 => \cnt_idel_dec_cpt_r[4]_i_5_n_0\,
      O => cnt_idel_dec_cpt_r(4)
    );
\cnt_idel_dec_cpt_r[4]_i_10\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B24D4DB2"
    )
        port map (
      I0 => \right_edge_taps_r_reg_n_0_[4]\,
      I1 => \tap_cnt_cpt_r_reg_n_0_[3]\,
      I2 => \cnt_idel_dec_cpt_r[4]_i_14_n_0\,
      I3 => \right_edge_taps_r_reg_n_0_[5]\,
      I4 => \tap_cnt_cpt_r_reg_n_0_[4]\,
      O => \cnt_idel_dec_cpt_r[4]_i_10_n_0\
    );
\cnt_idel_dec_cpt_r[4]_i_11\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"01"
    )
        port map (
      I0 => \cnt_idel_dec_cpt_r_reg_n_0_[0]\,
      I1 => \cnt_idel_dec_cpt_r_reg_n_0_[1]\,
      I2 => \cnt_idel_dec_cpt_r_reg_n_0_[2]\,
      O => \cnt_idel_dec_cpt_r[4]_i_11_n_0\
    );
\cnt_idel_dec_cpt_r[4]_i_12\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => \tap_cnt_cpt_r_reg_n_0_[5]\,
      I1 => \first_edge_taps_r_reg_n_0_[5]\,
      O => \cnt_idel_dec_cpt_r[4]_i_12_n_0\
    );
\cnt_idel_dec_cpt_r[4]_i_13\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => \tap_cnt_cpt_r_reg_n_0_[4]\,
      I1 => \first_edge_taps_r_reg_n_0_[4]\,
      O => \cnt_idel_dec_cpt_r[4]_i_13_n_0\
    );
\cnt_idel_dec_cpt_r[4]_i_14\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"2B22FFFF00002B22"
    )
        port map (
      I0 => \right_edge_taps_r_reg_n_0_[2]\,
      I1 => \tap_cnt_cpt_r_reg_n_0_[1]\,
      I2 => \tap_cnt_cpt_r_reg_n_0_[0]\,
      I3 => \right_edge_taps_r_reg_n_0_[1]\,
      I4 => \tap_cnt_cpt_r_reg_n_0_[2]\,
      I5 => \right_edge_taps_r_reg_n_0_[3]\,
      O => \cnt_idel_dec_cpt_r[4]_i_14_n_0\
    );
\cnt_idel_dec_cpt_r[4]_i_3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8000"
    )
        port map (
      I0 => cnt_idel_dec_cpt_r1(3),
      I1 => cnt_idel_dec_cpt_r1(1),
      I2 => cnt_idel_dec_cpt_r1(0),
      I3 => cnt_idel_dec_cpt_r1(2),
      O => \cnt_idel_dec_cpt_r[4]_i_3_n_0\
    );
\cnt_idel_dec_cpt_r[4]_i_4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8FFB800"
    )
        port map (
      I0 => \cnt_idel_dec_cpt_r_reg[4]_i_8_n_6\,
      I1 => found_first_edge_r_reg_n_0,
      I2 => \tap_cnt_cpt_r_reg_n_0_[5]\,
      I3 => \cnt_idel_dec_cpt_r[4]_i_9_n_0\,
      I4 => \cnt_idel_dec_cpt_r[4]_i_10_n_0\,
      O => \cnt_idel_dec_cpt_r[4]_i_4_n_0\
    );
\cnt_idel_dec_cpt_r[4]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F8F88FF888888888"
    )
        port map (
      I0 => D(4),
      I1 => p_27_in,
      I2 => \cnt_idel_dec_cpt_r_reg_n_0_[4]\,
      I3 => \cnt_idel_dec_cpt_r[4]_i_11_n_0\,
      I4 => \cnt_idel_dec_cpt_r_reg_n_0_[3]\,
      I5 => \FSM_onehot_cal1_state_r_reg_n_0_[1]\,
      O => \cnt_idel_dec_cpt_r[4]_i_5_n_0\
    );
\cnt_idel_dec_cpt_r[4]_i_6\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => \second_edge_taps_r_reg_n_0_[5]\,
      I1 => \first_edge_taps_r_reg_n_0_[5]\,
      O => \cnt_idel_dec_cpt_r[4]_i_6_n_0\
    );
\cnt_idel_dec_cpt_r[4]_i_7\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => \second_edge_taps_r_reg_n_0_[4]\,
      I1 => \first_edge_taps_r_reg_n_0_[4]\,
      O => \cnt_idel_dec_cpt_r[4]_i_7_n_0\
    );
\cnt_idel_dec_cpt_r[4]_i_9\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000000001"
    )
        port map (
      I0 => \right_edge_taps_r_reg_n_0_[5]\,
      I1 => \right_edge_taps_r_reg_n_0_[4]\,
      I2 => \right_edge_taps_r_reg_n_0_[1]\,
      I3 => \right_edge_taps_r_reg_n_0_[0]\,
      I4 => \right_edge_taps_r_reg_n_0_[2]\,
      I5 => \right_edge_taps_r_reg_n_0_[3]\,
      O => \cnt_idel_dec_cpt_r[4]_i_9_n_0\
    );
\cnt_idel_dec_cpt_r[5]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"FE"
    )
        port map (
      I0 => mpr_dec_cpt_r,
      I1 => \FSM_onehot_cal1_state_r_reg_n_0_[1]\,
      I2 => \FSM_onehot_cal1_state_r_reg_n_0_[29]\,
      O => \cnt_idel_dec_cpt_r[5]_i_1_n_0\
    );
\cnt_idel_dec_cpt_r[5]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFAEAEAE"
    )
        port map (
      I0 => \cnt_idel_dec_cpt_r[5]_i_3_n_0\,
      I1 => \FSM_onehot_cal1_state_r_reg_n_0_[1]\,
      I2 => \cnt_idel_dec_cpt_r[5]_i_4_n_0\,
      I3 => p_27_in,
      I4 => D(5),
      O => cnt_idel_dec_cpt_r(5)
    );
\cnt_idel_dec_cpt_r[5]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8808080808888888"
    )
        port map (
      I0 => \cnt_idel_dec_cpt_r[5]_i_5_n_0\,
      I1 => \FSM_onehot_cal1_state_r_reg_n_0_[29]\,
      I2 => found_second_edge_r_reg_n_0,
      I3 => cnt_idel_dec_cpt_r1(4),
      I4 => \cnt_idel_dec_cpt_r[4]_i_3_n_0\,
      I5 => \cnt_idel_dec_cpt_r_reg[4]_i_2_n_1\,
      O => \cnt_idel_dec_cpt_r[5]_i_3_n_0\
    );
\cnt_idel_dec_cpt_r[5]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"5555555555555556"
    )
        port map (
      I0 => \cnt_idel_dec_cpt_r_reg_n_0_[5]\,
      I1 => \cnt_idel_dec_cpt_r_reg_n_0_[0]\,
      I2 => \cnt_idel_dec_cpt_r_reg_n_0_[1]\,
      I3 => \cnt_idel_dec_cpt_r_reg_n_0_[2]\,
      I4 => \cnt_idel_dec_cpt_r_reg_n_0_[3]\,
      I5 => \cnt_idel_dec_cpt_r_reg_n_0_[4]\,
      O => \cnt_idel_dec_cpt_r[5]_i_4_n_0\
    );
\cnt_idel_dec_cpt_r[5]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAAABEBBEEBE"
    )
        port map (
      I0 => found_second_edge_r_reg_n_0,
      I1 => \tap_cnt_cpt_r_reg_n_0_[5]\,
      I2 => \right_edge_taps_r_reg_n_0_[5]\,
      I3 => \tap_cnt_cpt_r_reg_n_0_[4]\,
      I4 => \cnt_idel_dec_cpt_r[5]_i_6_n_0\,
      I5 => \cnt_idel_dec_cpt_r[4]_i_9_n_0\,
      O => \cnt_idel_dec_cpt_r[5]_i_5_n_0\
    );
\cnt_idel_dec_cpt_r[5]_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B2"
    )
        port map (
      I0 => \cnt_idel_dec_cpt_r[4]_i_14_n_0\,
      I1 => \tap_cnt_cpt_r_reg_n_0_[3]\,
      I2 => \right_edge_taps_r_reg_n_0_[4]\,
      O => \cnt_idel_dec_cpt_r[5]_i_6_n_0\
    );
\cnt_idel_dec_cpt_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => \cnt_idel_dec_cpt_r[5]_i_1_n_0\,
      D => cnt_idel_dec_cpt_r(0),
      Q => \cnt_idel_dec_cpt_r_reg_n_0_[0]\,
      R => '0'
    );
\cnt_idel_dec_cpt_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => \cnt_idel_dec_cpt_r[5]_i_1_n_0\,
      D => cnt_idel_dec_cpt_r(1),
      Q => \cnt_idel_dec_cpt_r_reg_n_0_[1]\,
      R => '0'
    );
\cnt_idel_dec_cpt_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => \cnt_idel_dec_cpt_r[5]_i_1_n_0\,
      D => cnt_idel_dec_cpt_r(2),
      Q => \cnt_idel_dec_cpt_r_reg_n_0_[2]\,
      R => '0'
    );
\cnt_idel_dec_cpt_r_reg[2]_i_10\: unisim.vcomponents.CARRY4
     port map (
      CI => '0',
      CO(3) => \cnt_idel_dec_cpt_r_reg[2]_i_10_n_0\,
      CO(2) => \cnt_idel_dec_cpt_r_reg[2]_i_10_n_1\,
      CO(1) => \cnt_idel_dec_cpt_r_reg[2]_i_10_n_2\,
      CO(0) => \cnt_idel_dec_cpt_r_reg[2]_i_10_n_3\,
      CYINIT => '1',
      DI(3) => \tap_cnt_cpt_r_reg_n_0_[3]\,
      DI(2) => \tap_cnt_cpt_r_reg_n_0_[2]\,
      DI(1) => \tap_cnt_cpt_r_reg_n_0_[1]\,
      DI(0) => \tap_cnt_cpt_r_reg_n_0_[0]\,
      O(3) => \cnt_idel_dec_cpt_r_reg[2]_i_10_n_4\,
      O(2) => \cnt_idel_dec_cpt_r_reg[2]_i_10_n_5\,
      O(1) => \cnt_idel_dec_cpt_r_reg[2]_i_10_n_6\,
      O(0) => \NLW_cnt_idel_dec_cpt_r_reg[2]_i_10_O_UNCONNECTED\(0),
      S(3) => \cnt_idel_dec_cpt_r[2]_i_12_n_0\,
      S(2) => \cnt_idel_dec_cpt_r[2]_i_13_n_0\,
      S(1) => \cnt_idel_dec_cpt_r[2]_i_14_n_0\,
      S(0) => \cnt_idel_dec_cpt_r[2]_i_15_n_0\
    );
\cnt_idel_dec_cpt_r_reg[2]_i_2\: unisim.vcomponents.CARRY4
     port map (
      CI => '0',
      CO(3) => \cnt_idel_dec_cpt_r_reg[2]_i_2_n_0\,
      CO(2) => \cnt_idel_dec_cpt_r_reg[2]_i_2_n_1\,
      CO(1) => \cnt_idel_dec_cpt_r_reg[2]_i_2_n_2\,
      CO(0) => \cnt_idel_dec_cpt_r_reg[2]_i_2_n_3\,
      CYINIT => '1',
      DI(3) => \second_edge_taps_r_reg_n_0_[3]\,
      DI(2) => \second_edge_taps_r_reg_n_0_[2]\,
      DI(1) => \second_edge_taps_r_reg_n_0_[1]\,
      DI(0) => \second_edge_taps_r_reg_n_0_[0]\,
      O(3 downto 1) => cnt_idel_dec_cpt_r1(2 downto 0),
      O(0) => \NLW_cnt_idel_dec_cpt_r_reg[2]_i_2_O_UNCONNECTED\(0),
      S(3) => \cnt_idel_dec_cpt_r[2]_i_6_n_0\,
      S(2) => \cnt_idel_dec_cpt_r[2]_i_7_n_0\,
      S(1) => \cnt_idel_dec_cpt_r[2]_i_8_n_0\,
      S(0) => \cnt_idel_dec_cpt_r[2]_i_9_n_0\
    );
\cnt_idel_dec_cpt_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => \cnt_idel_dec_cpt_r[5]_i_1_n_0\,
      D => cnt_idel_dec_cpt_r(3),
      Q => \cnt_idel_dec_cpt_r_reg_n_0_[3]\,
      R => '0'
    );
\cnt_idel_dec_cpt_r_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => \cnt_idel_dec_cpt_r[5]_i_1_n_0\,
      D => cnt_idel_dec_cpt_r(4),
      Q => \cnt_idel_dec_cpt_r_reg_n_0_[4]\,
      R => '0'
    );
\cnt_idel_dec_cpt_r_reg[4]_i_2\: unisim.vcomponents.CARRY4
     port map (
      CI => \cnt_idel_dec_cpt_r_reg[2]_i_2_n_0\,
      CO(3) => \NLW_cnt_idel_dec_cpt_r_reg[4]_i_2_CO_UNCONNECTED\(3),
      CO(2) => \cnt_idel_dec_cpt_r_reg[4]_i_2_n_1\,
      CO(1) => \NLW_cnt_idel_dec_cpt_r_reg[4]_i_2_CO_UNCONNECTED\(1),
      CO(0) => \cnt_idel_dec_cpt_r_reg[4]_i_2_n_3\,
      CYINIT => '0',
      DI(3 downto 2) => B"00",
      DI(1) => \second_edge_taps_r_reg_n_0_[5]\,
      DI(0) => \second_edge_taps_r_reg_n_0_[4]\,
      O(3 downto 2) => \NLW_cnt_idel_dec_cpt_r_reg[4]_i_2_O_UNCONNECTED\(3 downto 2),
      O(1 downto 0) => cnt_idel_dec_cpt_r1(4 downto 3),
      S(3 downto 2) => B"01",
      S(1) => \cnt_idel_dec_cpt_r[4]_i_6_n_0\,
      S(0) => \cnt_idel_dec_cpt_r[4]_i_7_n_0\
    );
\cnt_idel_dec_cpt_r_reg[4]_i_8\: unisim.vcomponents.CARRY4
     port map (
      CI => \cnt_idel_dec_cpt_r_reg[2]_i_10_n_0\,
      CO(3 downto 1) => \NLW_cnt_idel_dec_cpt_r_reg[4]_i_8_CO_UNCONNECTED\(3 downto 1),
      CO(0) => \cnt_idel_dec_cpt_r_reg[4]_i_8_n_3\,
      CYINIT => '0',
      DI(3 downto 1) => B"000",
      DI(0) => \tap_cnt_cpt_r_reg_n_0_[4]\,
      O(3 downto 2) => \NLW_cnt_idel_dec_cpt_r_reg[4]_i_8_O_UNCONNECTED\(3 downto 2),
      O(1) => \cnt_idel_dec_cpt_r_reg[4]_i_8_n_6\,
      O(0) => \cnt_idel_dec_cpt_r_reg[4]_i_8_n_7\,
      S(3 downto 2) => B"00",
      S(1) => \cnt_idel_dec_cpt_r[4]_i_12_n_0\,
      S(0) => \cnt_idel_dec_cpt_r[4]_i_13_n_0\
    );
\cnt_idel_dec_cpt_r_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => \cnt_idel_dec_cpt_r[5]_i_1_n_0\,
      D => cnt_idel_dec_cpt_r(5),
      Q => \cnt_idel_dec_cpt_r_reg_n_0_[5]\,
      R => '0'
    );
\cnt_shift_r[0]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"3332"
    )
        port map (
      I0 => cnt_shift_r_reg(1),
      I1 => cnt_shift_r_reg(0),
      I2 => cnt_shift_r_reg(2),
      I3 => cnt_shift_r_reg(3),
      O => \p_0_in__2\(0)
    );
\cnt_shift_r[1]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => cnt_shift_r_reg(0),
      I1 => cnt_shift_r_reg(1),
      O => \p_0_in__2\(1)
    );
\cnt_shift_r[2]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"6A"
    )
        port map (
      I0 => cnt_shift_r_reg(2),
      I1 => cnt_shift_r_reg(1),
      I2 => cnt_shift_r_reg(0),
      O => \p_0_in__2\(2)
    );
\cnt_shift_r[3]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6AAA"
    )
        port map (
      I0 => cnt_shift_r_reg(3),
      I1 => cnt_shift_r_reg(0),
      I2 => cnt_shift_r_reg(1),
      I3 => cnt_shift_r_reg(2),
      O => \p_0_in__2\(3)
    );
\cnt_shift_r_reg[0]\: unisim.vcomponents.FDSE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => E(0),
      D => \p_0_in__2\(0),
      Q => cnt_shift_r_reg(0),
      S => \cnt_shift_r_reg[0]_0\(0)
    );
\cnt_shift_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => E(0),
      D => \p_0_in__2\(1),
      Q => cnt_shift_r_reg(1),
      R => \cnt_shift_r_reg[0]_0\(0)
    );
\cnt_shift_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => E(0),
      D => \p_0_in__2\(2),
      Q => cnt_shift_r_reg(2),
      R => \cnt_shift_r_reg[0]_0\(0)
    );
\cnt_shift_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => E(0),
      D => \p_0_in__2\(3),
      Q => cnt_shift_r_reg(3),
      R => \cnt_shift_r_reg[0]_0\(0)
    );
\ctl_lane_cnt[2]_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"BF"
    )
        port map (
      I0 => \done_cnt_reg[2]_0\,
      I1 => \^pi_fine_dly_dec_done\,
      I2 => dqs_po_dec_done,
      O => p_1_in
    );
detect_edge_done_r_i_1: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00008000"
    )
        port map (
      I0 => pb_detect_edge_done_r(4),
      I1 => pb_detect_edge_done_r(6),
      I2 => pb_detect_edge_done_r(0),
      I3 => pb_detect_edge_done_r(2),
      I4 => detect_edge_done_r_i_2_n_0,
      O => detect_edge_done_r_i_1_n_0
    );
detect_edge_done_r_i_2: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7FFF"
    )
        port map (
      I0 => pb_detect_edge_done_r(3),
      I1 => pb_detect_edge_done_r(1),
      I2 => pb_detect_edge_done_r(7),
      I3 => pb_detect_edge_done_r(5),
      O => detect_edge_done_r_i_2_n_0
    );
detect_edge_done_r_reg: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => detect_edge_done_r_i_1_n_0,
      Q => detect_edge_done_r,
      R => '0'
    );
\done_cnt[0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000003332"
    )
        port map (
      I0 => done_cnt(2),
      I1 => done_cnt(0),
      I2 => done_cnt(1),
      I3 => done_cnt(3),
      I4 => done_cnt1,
      I5 => \done_cnt_reg[2]_0\,
      O => \done_cnt[0]_i_1_n_0\
    );
\done_cnt[1]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FAAFFAAE"
    )
        port map (
      I0 => done_cnt1,
      I1 => done_cnt(3),
      I2 => done_cnt(1),
      I3 => done_cnt(0),
      I4 => done_cnt(2),
      O => \done_cnt[1]_i_1_n_0\
    );
\done_cnt[2]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"000000000000A9A8"
    )
        port map (
      I0 => done_cnt(2),
      I1 => done_cnt(0),
      I2 => done_cnt(1),
      I3 => done_cnt(3),
      I4 => done_cnt1,
      I5 => \done_cnt_reg[2]_0\,
      O => \done_cnt[2]_i_1_n_0\
    );
\done_cnt[3]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"EEEEEEEA"
    )
        port map (
      I0 => done_cnt1,
      I1 => done_cnt(3),
      I2 => done_cnt(1),
      I3 => done_cnt(0),
      I4 => done_cnt(2),
      O => \done_cnt[3]_i_1_n_0\
    );
\done_cnt[3]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"1F11"
    )
        port map (
      I0 => \FSM_onehot_cal1_state_r[5]_i_2_n_0\,
      I1 => rdlvl_stg1_done_int,
      I2 => \rdlvl_dqs_tap_cnt_r[0][0][5]_i_2_n_0\,
      I3 => p_0_in541_in,
      O => done_cnt1
    );
\done_cnt_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \done_cnt[0]_i_1_n_0\,
      Q => done_cnt(0),
      R => '0'
    );
\done_cnt_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \done_cnt[1]_i_1_n_0\,
      Q => done_cnt(1),
      R => SR(0)
    );
\done_cnt_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \done_cnt[2]_i_1_n_0\,
      Q => done_cnt(2),
      R => '0'
    );
\done_cnt_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \done_cnt[3]_i_1_n_0\,
      Q => done_cnt(3),
      R => SR(0)
    );
dqs_po_dec_done_r1_reg: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => dqs_po_dec_done,
      Q => dqs_po_dec_done_r1,
      R => '0'
    );
dqs_po_dec_done_r2_reg: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => dqs_po_dec_done_r1,
      Q => dqs_po_dec_done_r2,
      R => '0'
    );
fine_dly_dec_done_r1_i_1: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFF222"
    )
        port map (
      I0 => \^pi_cnt_dec_reg_0\,
      I1 => fine_dly_dec_done_r1_i_2_n_0,
      I2 => dqs_po_dec_done_r2,
      I3 => \pi_rdval_cnt[5]_i_3_n_0\,
      I4 => fine_dly_dec_done_r1,
      O => fine_dly_dec_done_r1_i_1_n_0
    );
fine_dly_dec_done_r1_i_2: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFEFF"
    )
        port map (
      I0 => pi_rdval_cnt(2),
      I1 => pi_rdval_cnt(3),
      I2 => pi_rdval_cnt(1),
      I3 => pi_rdval_cnt(0),
      I4 => pi_rdval_cnt(4),
      I5 => pi_rdval_cnt(5),
      O => fine_dly_dec_done_r1_i_2_n_0
    );
fine_dly_dec_done_r1_reg: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => fine_dly_dec_done_r1_i_1_n_0,
      Q => fine_dly_dec_done_r1,
      R => \rdlvl_dqs_tap_cnt_r_reg[0][0][2]_0\(1)
    );
fine_dly_dec_done_r2_reg: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => fine_dly_dec_done_r1,
      Q => fine_dly_dec_done_r2,
      R => '0'
    );
\first_edge_taps_r[5]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000BFAA"
    )
        port map (
      I0 => cal1_prech_req_r,
      I1 => found_first_edge_r_reg_n_0,
      I2 => found_stable_eye_last_r,
      I3 => \first_edge_taps_r[5]_i_3_n_0\,
      I4 => store_sr_req_pulsed_r,
      O => \first_edge_taps_r[5]_i_1_n_0\
    );
\first_edge_taps_r[5]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"BFAA"
    )
        port map (
      I0 => cal1_prech_req_r,
      I1 => found_first_edge_r_reg_n_0,
      I2 => found_stable_eye_last_r,
      I3 => \first_edge_taps_r[5]_i_3_n_0\,
      O => \first_edge_taps_r[5]_i_2_n_0\
    );
\first_edge_taps_r[5]_i_3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0080"
    )
        port map (
      I0 => found_edge_r_reg_n_0,
      I1 => store_sr_req_pulsed_r,
      I2 => detect_edge_done_r,
      I3 => tap_limit_cpt_r,
      O => \first_edge_taps_r[5]_i_3_n_0\
    );
\first_edge_taps_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => \first_edge_taps_r[5]_i_2_n_0\,
      D => \tap_cnt_cpt_r_reg_n_0_[0]\,
      Q => \first_edge_taps_r_reg_n_0_[0]\,
      R => \first_edge_taps_r[5]_i_1_n_0\
    );
\first_edge_taps_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => \first_edge_taps_r[5]_i_2_n_0\,
      D => \tap_cnt_cpt_r_reg_n_0_[1]\,
      Q => \first_edge_taps_r_reg_n_0_[1]\,
      R => \first_edge_taps_r[5]_i_1_n_0\
    );
\first_edge_taps_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => \first_edge_taps_r[5]_i_2_n_0\,
      D => \tap_cnt_cpt_r_reg_n_0_[2]\,
      Q => \first_edge_taps_r_reg_n_0_[2]\,
      R => \first_edge_taps_r[5]_i_1_n_0\
    );
\first_edge_taps_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => \first_edge_taps_r[5]_i_2_n_0\,
      D => \tap_cnt_cpt_r_reg_n_0_[3]\,
      Q => \first_edge_taps_r_reg_n_0_[3]\,
      R => \first_edge_taps_r[5]_i_1_n_0\
    );
\first_edge_taps_r_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => \first_edge_taps_r[5]_i_2_n_0\,
      D => \tap_cnt_cpt_r_reg_n_0_[4]\,
      Q => \first_edge_taps_r_reg_n_0_[4]\,
      R => \first_edge_taps_r[5]_i_1_n_0\
    );
\first_edge_taps_r_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => \first_edge_taps_r[5]_i_2_n_0\,
      D => \tap_cnt_cpt_r_reg_n_0_[5]\,
      Q => \first_edge_taps_r_reg_n_0_[5]\,
      R => \first_edge_taps_r[5]_i_1_n_0\
    );
found_edge_r_i_1: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFFFFE"
    )
        port map (
      I0 => \gen_track_left_edge[3].pb_found_edge_r_reg_n_0_[3]\,
      I1 => \gen_track_left_edge[6].pb_found_edge_r_reg_n_0_[6]\,
      I2 => \gen_track_left_edge[5].pb_found_edge_r_reg_n_0_[5]\,
      I3 => \gen_track_left_edge[7].pb_found_edge_r_reg_n_0_[7]\,
      I4 => found_edge_r_i_2_n_0,
      O => found_edge_r_i_1_n_0
    );
found_edge_r_i_2: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFFE"
    )
        port map (
      I0 => \gen_track_left_edge[4].pb_found_edge_r_reg_n_0_[4]\,
      I1 => \gen_track_left_edge[0].pb_found_edge_r_reg_n_0_[0]\,
      I2 => \gen_track_left_edge[2].pb_found_edge_r_reg_n_0_[2]\,
      I3 => \gen_track_left_edge[1].pb_found_edge_r_reg_n_0_[1]\,
      O => found_edge_r_i_2_n_0
    );
found_edge_r_reg: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => found_edge_r_i_1_n_0,
      Q => found_edge_r_reg_n_0,
      R => '0'
    );
found_first_edge_r_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FF555555BA000000"
    )
        port map (
      I0 => cal1_prech_req_r,
      I1 => tap_limit_cpt_r,
      I2 => detect_edge_done_r,
      I3 => store_sr_req_pulsed_r,
      I4 => found_edge_r_reg_n_0,
      I5 => found_first_edge_r_reg_n_0,
      O => found_first_edge_r_i_1_n_0
    );
found_first_edge_r_reg: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => found_first_edge_r_i_1_n_0,
      Q => found_first_edge_r_reg_n_0,
      R => \rdlvl_dqs_tap_cnt_r_reg[0][0][2]_0\(1)
    );
found_second_edge_r_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F5551555E0000000"
    )
        port map (
      I0 => cal1_prech_req_r,
      I1 => \first_edge_taps_r[5]_i_3_n_0\,
      I2 => found_first_edge_r_reg_n_0,
      I3 => found_stable_eye_last_r,
      I4 => store_sr_req_pulsed_r,
      I5 => found_second_edge_r_reg_n_0,
      O => found_second_edge_r_i_1_n_0
    );
found_second_edge_r_reg: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => found_second_edge_r_i_1_n_0,
      Q => found_second_edge_r_reg_n_0,
      R => found_second_edge_r_reg_0
    );
found_stable_eye_last_r_i_1: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => found_stable_eye_r_reg_n_0,
      I1 => detect_edge_done_r,
      I2 => found_stable_eye_last_r,
      O => found_stable_eye_last_r_i_1_n_0
    );
found_stable_eye_last_r_reg: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => found_stable_eye_last_r_i_1_n_0,
      Q => found_stable_eye_last_r,
      R => \FSM_onehot_cal1_state_r_reg_n_0_[16]\
    );
found_stable_eye_r_i_1: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00008000"
    )
        port map (
      I0 => pb_found_stable_eye_r(2),
      I1 => pb_found_stable_eye_r(3),
      I2 => pb_found_stable_eye_r(0),
      I3 => pb_found_stable_eye_r(1),
      I4 => found_stable_eye_r_i_2_n_0,
      O => found_stable_eye_r_i_1_n_0
    );
found_stable_eye_r_i_2: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7FFF"
    )
        port map (
      I0 => pb_found_stable_eye_r(5),
      I1 => pb_found_stable_eye_r(4),
      I2 => pb_found_stable_eye_r(7),
      I3 => pb_found_stable_eye_r(6),
      O => found_stable_eye_r_i_2_n_0
    );
found_stable_eye_r_reg: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => found_stable_eye_r_i_1_n_0,
      Q => found_stable_eye_r_reg_n_0,
      R => '0'
    );
\gen_byte_sel_div2.byte_sel_cnt[0]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8FFB800"
    )
        port map (
      I0 => \gen_byte_sel_div2.byte_sel_cnt_reg[0]\,
      I1 => \^rdlvl_stg1_done_int_reg_0\,
      I2 => pi_stg2_rdlvl_cnt(0),
      I3 => \gen_byte_sel_div2.byte_sel_cnt_reg[3]_0\,
      I4 => \gen_byte_sel_div2.byte_sel_cnt_reg[0]_0\,
      O => rdlvl_stg1_done_int_reg_3(0)
    );
\gen_byte_sel_div2.byte_sel_cnt[0]_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => regl_dqs_cnt_r(0),
      I1 => p_0_in541_in,
      I2 => \cal1_cnt_cpt_r_reg_n_0_[0]\,
      O => pi_stg2_rdlvl_cnt(0)
    );
\gen_byte_sel_div2.byte_sel_cnt[1]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8FFB800"
    )
        port map (
      I0 => \gen_byte_sel_div2.byte_sel_cnt_reg[1]\,
      I1 => \^rdlvl_stg1_done_int_reg_0\,
      I2 => pi_stg2_rdlvl_cnt(1),
      I3 => \gen_byte_sel_div2.byte_sel_cnt_reg[3]_0\,
      I4 => \gen_byte_sel_div2.byte_sel_cnt_reg[1]_0\,
      O => rdlvl_stg1_done_int_reg_3(1)
    );
\gen_byte_sel_div2.byte_sel_cnt[1]_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => regl_dqs_cnt_r(1),
      I1 => p_0_in541_in,
      I2 => \cal1_cnt_cpt_r_reg_n_0_[1]\,
      O => pi_stg2_rdlvl_cnt(1)
    );
\gen_byte_sel_div2.byte_sel_cnt[2]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8FFB800"
    )
        port map (
      I0 => \gen_byte_sel_div2.byte_sel_cnt_reg[2]\,
      I1 => \^rdlvl_stg1_done_int_reg_0\,
      I2 => pi_stg2_rdlvl_cnt(2),
      I3 => \gen_byte_sel_div2.byte_sel_cnt_reg[3]_0\,
      I4 => \gen_byte_sel_div2.byte_sel_cnt_reg[2]_0\,
      O => rdlvl_stg1_done_int_reg_3(2)
    );
\gen_byte_sel_div2.byte_sel_cnt[2]_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => regl_dqs_cnt_r(2),
      I1 => p_0_in541_in,
      I2 => \cal1_cnt_cpt_r_reg_n_0_[2]\,
      O => pi_stg2_rdlvl_cnt(2)
    );
\gen_byte_sel_div2.byte_sel_cnt[3]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"B888FFFFB8880000"
    )
        port map (
      I0 => \gen_byte_sel_div2.byte_sel_cnt_reg[3]\,
      I1 => \^rdlvl_stg1_done_int_reg_0\,
      I2 => p_0_in541_in,
      I3 => regl_dqs_cnt_r(3),
      I4 => \gen_byte_sel_div2.byte_sel_cnt_reg[3]_0\,
      I5 => \gen_byte_sel_div2.byte_sel_cnt_reg[3]_1\(0),
      O => rdlvl_stg1_done_int_reg_3(3)
    );
\gen_mux_rd[0].mux_rd_fall0_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_mux_rd[0].mux_rd_fall0_r_reg[0]_0\,
      Q => \gen_mux_rd[0].mux_rd_fall0_r_reg_n_0_[0]\,
      R => '0'
    );
\gen_mux_rd[0].mux_rd_fall1_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_mux_rd[0].mux_rd_fall1_r_reg[0]_0\,
      Q => \gen_mux_rd[0].mux_rd_fall1_r_reg_n_0_[0]\,
      R => '0'
    );
\gen_mux_rd[0].mux_rd_fall2_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_mux_rd[0].mux_rd_fall2_r_reg[0]_0\,
      Q => \gen_mux_rd[0].mux_rd_fall2_r_reg_n_0_[0]\,
      R => '0'
    );
\gen_mux_rd[0].mux_rd_fall3_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_mux_rd[0].mux_rd_fall3_r_reg[0]_0\,
      Q => \gen_mux_rd[0].mux_rd_fall3_r_reg_n_0_[0]\,
      R => '0'
    );
\gen_mux_rd[0].mux_rd_rise0_r[0]_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"95"
    )
        port map (
      I0 => \rd_mux_sel_r_reg_n_0_[2]\,
      I1 => \^q\(1),
      I2 => \^q\(0),
      O => \rd_mux_sel_r_reg[2]_0\
    );
\gen_mux_rd[0].mux_rd_rise0_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_mux_rd[0].mux_rd_rise0_r_reg[0]_0\,
      Q => \gen_mux_rd[0].mux_rd_rise0_r_reg_n_0_[0]\,
      R => '0'
    );
\gen_mux_rd[0].mux_rd_rise1_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_mux_rd[0].mux_rd_rise1_r_reg[0]_0\,
      Q => \gen_mux_rd[0].mux_rd_rise1_r_reg_n_0_[0]\,
      R => '0'
    );
\gen_mux_rd[0].mux_rd_rise2_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_mux_rd[0].mux_rd_rise2_r_reg[0]_0\,
      Q => \gen_mux_rd[0].mux_rd_rise2_r_reg_n_0_[0]\,
      R => '0'
    );
\gen_mux_rd[0].mux_rd_rise3_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_mux_rd[0].mux_rd_rise3_r_reg[0]_0\,
      Q => \gen_mux_rd[0].mux_rd_rise3_r_reg_n_0_[0]\,
      R => '0'
    );
\gen_mux_rd[1].mux_rd_fall0_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_mux_rd[1].mux_rd_fall0_r_reg[1]_0\,
      Q => \gen_mux_rd[1].mux_rd_fall0_r_reg_n_0_[1]\,
      R => '0'
    );
\gen_mux_rd[1].mux_rd_fall1_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_mux_rd[1].mux_rd_fall1_r_reg[1]_0\,
      Q => \gen_mux_rd[1].mux_rd_fall1_r_reg_n_0_[1]\,
      R => '0'
    );
\gen_mux_rd[1].mux_rd_fall2_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_mux_rd[1].mux_rd_fall2_r_reg[1]_0\,
      Q => \gen_mux_rd[1].mux_rd_fall2_r_reg_n_0_[1]\,
      R => '0'
    );
\gen_mux_rd[1].mux_rd_fall3_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_mux_rd[1].mux_rd_fall3_r_reg[1]_0\,
      Q => \gen_mux_rd[1].mux_rd_fall3_r_reg_n_0_[1]\,
      R => '0'
    );
\gen_mux_rd[1].mux_rd_rise0_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_mux_rd[1].mux_rd_rise0_r_reg[1]_0\,
      Q => \gen_mux_rd[1].mux_rd_rise0_r_reg_n_0_[1]\,
      R => '0'
    );
\gen_mux_rd[1].mux_rd_rise1_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_mux_rd[1].mux_rd_rise1_r_reg[1]_0\,
      Q => \gen_mux_rd[1].mux_rd_rise1_r_reg_n_0_[1]\,
      R => '0'
    );
\gen_mux_rd[1].mux_rd_rise2_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_mux_rd[1].mux_rd_rise2_r_reg[1]_0\,
      Q => \gen_mux_rd[1].mux_rd_rise2_r_reg_n_0_[1]\,
      R => '0'
    );
\gen_mux_rd[1].mux_rd_rise3_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_mux_rd[1].mux_rd_rise3_r_reg[1]_0\,
      Q => \gen_mux_rd[1].mux_rd_rise3_r_reg_n_0_[1]\,
      R => '0'
    );
\gen_mux_rd[2].mux_rd_fall0_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_mux_rd[2].mux_rd_fall0_r_reg[2]_0\,
      Q => \gen_mux_rd[2].mux_rd_fall0_r_reg_n_0_[2]\,
      R => '0'
    );
\gen_mux_rd[2].mux_rd_fall1_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_mux_rd[2].mux_rd_fall1_r_reg[2]_0\,
      Q => \gen_mux_rd[2].mux_rd_fall1_r_reg_n_0_[2]\,
      R => '0'
    );
\gen_mux_rd[2].mux_rd_fall2_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_mux_rd[2].mux_rd_fall2_r_reg[2]_0\,
      Q => \gen_mux_rd[2].mux_rd_fall2_r_reg_n_0_[2]\,
      R => '0'
    );
\gen_mux_rd[2].mux_rd_fall3_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_mux_rd[2].mux_rd_fall3_r_reg[2]_0\,
      Q => \gen_mux_rd[2].mux_rd_fall3_r_reg_n_0_[2]\,
      R => '0'
    );
\gen_mux_rd[2].mux_rd_rise0_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_mux_rd[2].mux_rd_rise0_r_reg[2]_0\,
      Q => \gen_mux_rd[2].mux_rd_rise0_r_reg_n_0_[2]\,
      R => '0'
    );
\gen_mux_rd[2].mux_rd_rise1_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_mux_rd[2].mux_rd_rise1_r_reg[2]_0\,
      Q => \gen_mux_rd[2].mux_rd_rise1_r_reg_n_0_[2]\,
      R => '0'
    );
\gen_mux_rd[2].mux_rd_rise2_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_mux_rd[2].mux_rd_rise2_r_reg[2]_0\,
      Q => \gen_mux_rd[2].mux_rd_rise2_r_reg_n_0_[2]\,
      R => '0'
    );
\gen_mux_rd[2].mux_rd_rise3_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_mux_rd[2].mux_rd_rise3_r_reg[2]_0\,
      Q => \gen_mux_rd[2].mux_rd_rise3_r_reg_n_0_[2]\,
      R => '0'
    );
\gen_mux_rd[3].mux_rd_fall0_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_mux_rd[3].mux_rd_fall0_r_reg[3]_0\,
      Q => \gen_mux_rd[3].mux_rd_fall0_r_reg_n_0_[3]\,
      R => '0'
    );
\gen_mux_rd[3].mux_rd_fall1_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_mux_rd[3].mux_rd_fall1_r_reg[3]_0\,
      Q => \gen_mux_rd[3].mux_rd_fall1_r_reg_n_0_[3]\,
      R => '0'
    );
\gen_mux_rd[3].mux_rd_fall2_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_mux_rd[3].mux_rd_fall2_r_reg[3]_0\,
      Q => \gen_mux_rd[3].mux_rd_fall2_r_reg_n_0_[3]\,
      R => '0'
    );
\gen_mux_rd[3].mux_rd_fall3_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_mux_rd[3].mux_rd_fall3_r_reg[3]_0\,
      Q => \gen_mux_rd[3].mux_rd_fall3_r_reg_n_0_[3]\,
      R => '0'
    );
\gen_mux_rd[3].mux_rd_rise0_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_mux_rd[3].mux_rd_rise0_r_reg[3]_0\,
      Q => \gen_mux_rd[3].mux_rd_rise0_r_reg_n_0_[3]\,
      R => '0'
    );
\gen_mux_rd[3].mux_rd_rise1_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_mux_rd[3].mux_rd_rise1_r_reg[3]_0\,
      Q => \gen_mux_rd[3].mux_rd_rise1_r_reg_n_0_[3]\,
      R => '0'
    );
\gen_mux_rd[3].mux_rd_rise2_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_mux_rd[3].mux_rd_rise2_r_reg[3]_0\,
      Q => \gen_mux_rd[3].mux_rd_rise2_r_reg_n_0_[3]\,
      R => '0'
    );
\gen_mux_rd[3].mux_rd_rise3_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_mux_rd[3].mux_rd_rise3_r_reg[3]_0\,
      Q => \gen_mux_rd[3].mux_rd_rise3_r_reg_n_0_[3]\,
      R => '0'
    );
\gen_mux_rd[4].mux_rd_fall0_r_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_mux_rd[4].mux_rd_fall0_r_reg[4]_0\,
      Q => \gen_mux_rd[4].mux_rd_fall0_r_reg_n_0_[4]\,
      R => '0'
    );
\gen_mux_rd[4].mux_rd_fall1_r_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_mux_rd[4].mux_rd_fall1_r_reg[4]_0\,
      Q => \gen_mux_rd[4].mux_rd_fall1_r_reg_n_0_[4]\,
      R => '0'
    );
\gen_mux_rd[4].mux_rd_fall2_r_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_mux_rd[4].mux_rd_fall2_r_reg[4]_0\,
      Q => \gen_mux_rd[4].mux_rd_fall2_r_reg_n_0_[4]\,
      R => '0'
    );
\gen_mux_rd[4].mux_rd_fall3_r_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_mux_rd[4].mux_rd_fall3_r_reg[4]_0\,
      Q => \gen_mux_rd[4].mux_rd_fall3_r_reg_n_0_[4]\,
      R => '0'
    );
\gen_mux_rd[4].mux_rd_rise0_r_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_mux_rd[4].mux_rd_rise0_r_reg[4]_0\,
      Q => \gen_mux_rd[4].mux_rd_rise0_r_reg_n_0_[4]\,
      R => '0'
    );
\gen_mux_rd[4].mux_rd_rise1_r_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_mux_rd[4].mux_rd_rise1_r_reg[4]_0\,
      Q => \gen_mux_rd[4].mux_rd_rise1_r_reg_n_0_[4]\,
      R => '0'
    );
\gen_mux_rd[4].mux_rd_rise2_r_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_mux_rd[4].mux_rd_rise2_r_reg[4]_0\,
      Q => \gen_mux_rd[4].mux_rd_rise2_r_reg_n_0_[4]\,
      R => '0'
    );
\gen_mux_rd[4].mux_rd_rise3_r_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_mux_rd[4].mux_rd_rise3_r_reg[4]_0\,
      Q => \gen_mux_rd[4].mux_rd_rise3_r_reg_n_0_[4]\,
      R => '0'
    );
\gen_mux_rd[5].mux_rd_fall0_r_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_mux_rd[5].mux_rd_fall0_r_reg[5]_0\,
      Q => \gen_mux_rd[5].mux_rd_fall0_r_reg_n_0_[5]\,
      R => '0'
    );
\gen_mux_rd[5].mux_rd_fall1_r_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_mux_rd[5].mux_rd_fall1_r_reg[5]_0\,
      Q => \gen_mux_rd[5].mux_rd_fall1_r_reg_n_0_[5]\,
      R => '0'
    );
\gen_mux_rd[5].mux_rd_fall2_r_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_mux_rd[5].mux_rd_fall2_r_reg[5]_0\,
      Q => \gen_mux_rd[5].mux_rd_fall2_r_reg_n_0_[5]\,
      R => '0'
    );
\gen_mux_rd[5].mux_rd_fall3_r_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_mux_rd[5].mux_rd_fall3_r_reg[5]_0\,
      Q => \gen_mux_rd[5].mux_rd_fall3_r_reg_n_0_[5]\,
      R => '0'
    );
\gen_mux_rd[5].mux_rd_rise0_r_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_mux_rd[5].mux_rd_rise0_r_reg[5]_0\,
      Q => \gen_mux_rd[5].mux_rd_rise0_r_reg_n_0_[5]\,
      R => '0'
    );
\gen_mux_rd[5].mux_rd_rise1_r_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_mux_rd[5].mux_rd_rise1_r_reg[5]_0\,
      Q => \gen_mux_rd[5].mux_rd_rise1_r_reg_n_0_[5]\,
      R => '0'
    );
\gen_mux_rd[5].mux_rd_rise2_r_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_mux_rd[5].mux_rd_rise2_r_reg[5]_0\,
      Q => \gen_mux_rd[5].mux_rd_rise2_r_reg_n_0_[5]\,
      R => '0'
    );
\gen_mux_rd[5].mux_rd_rise3_r_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_mux_rd[5].mux_rd_rise3_r_reg[5]_0\,
      Q => \gen_mux_rd[5].mux_rd_rise3_r_reg_n_0_[5]\,
      R => '0'
    );
\gen_mux_rd[6].mux_rd_fall0_r_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_mux_rd[6].mux_rd_fall0_r_reg[6]_0\,
      Q => \gen_mux_rd[6].mux_rd_fall0_r_reg_n_0_[6]\,
      R => '0'
    );
\gen_mux_rd[6].mux_rd_fall1_r_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_mux_rd[6].mux_rd_fall1_r_reg[6]_0\,
      Q => \gen_mux_rd[6].mux_rd_fall1_r_reg_n_0_[6]\,
      R => '0'
    );
\gen_mux_rd[6].mux_rd_fall2_r_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_mux_rd[6].mux_rd_fall2_r_reg[6]_0\,
      Q => \gen_mux_rd[6].mux_rd_fall2_r_reg_n_0_[6]\,
      R => '0'
    );
\gen_mux_rd[6].mux_rd_fall3_r_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_mux_rd[6].mux_rd_fall3_r_reg[6]_0\,
      Q => \gen_mux_rd[6].mux_rd_fall3_r_reg_n_0_[6]\,
      R => '0'
    );
\gen_mux_rd[6].mux_rd_rise0_r_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_mux_rd[6].mux_rd_rise0_r_reg[6]_0\,
      Q => \gen_mux_rd[6].mux_rd_rise0_r_reg_n_0_[6]\,
      R => '0'
    );
\gen_mux_rd[6].mux_rd_rise1_r_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_mux_rd[6].mux_rd_rise1_r_reg[6]_0\,
      Q => \gen_mux_rd[6].mux_rd_rise1_r_reg_n_0_[6]\,
      R => '0'
    );
\gen_mux_rd[6].mux_rd_rise2_r_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_mux_rd[6].mux_rd_rise2_r_reg[6]_0\,
      Q => \gen_mux_rd[6].mux_rd_rise2_r_reg_n_0_[6]\,
      R => '0'
    );
\gen_mux_rd[6].mux_rd_rise3_r_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_mux_rd[6].mux_rd_rise3_r_reg[6]_0\,
      Q => \gen_mux_rd[6].mux_rd_rise3_r_reg_n_0_[6]\,
      R => '0'
    );
\gen_mux_rd[7].mux_rd_fall0_r_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_mux_rd[7].mux_rd_fall0_r_reg[7]_0\,
      Q => \gen_mux_rd[7].mux_rd_fall0_r_reg_n_0_[7]\,
      R => '0'
    );
\gen_mux_rd[7].mux_rd_fall1_r_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_mux_rd[7].mux_rd_fall1_r_reg[7]_0\,
      Q => \gen_mux_rd[7].mux_rd_fall1_r_reg_n_0_[7]\,
      R => '0'
    );
\gen_mux_rd[7].mux_rd_fall2_r_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_mux_rd[7].mux_rd_fall2_r_reg[7]_0\,
      Q => \gen_mux_rd[7].mux_rd_fall2_r_reg_n_0_[7]\,
      R => '0'
    );
\gen_mux_rd[7].mux_rd_fall3_r_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_mux_rd[7].mux_rd_fall3_r_reg[7]_0\,
      Q => \gen_mux_rd[7].mux_rd_fall3_r_reg_n_0_[7]\,
      R => '0'
    );
\gen_mux_rd[7].mux_rd_rise0_r_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_mux_rd[7].mux_rd_rise0_r_reg[7]_0\,
      Q => \gen_mux_rd[7].mux_rd_rise0_r_reg_n_0_[7]\,
      R => '0'
    );
\gen_mux_rd[7].mux_rd_rise1_r_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_mux_rd[7].mux_rd_rise1_r_reg[7]_0\,
      Q => \gen_mux_rd[7].mux_rd_rise1_r_reg_n_0_[7]\,
      R => '0'
    );
\gen_mux_rd[7].mux_rd_rise2_r_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_mux_rd[7].mux_rd_rise2_r_reg[7]_0\,
      Q => \gen_mux_rd[7].mux_rd_rise2_r_reg_n_0_[7]\,
      R => '0'
    );
\gen_mux_rd[7].mux_rd_rise3_r_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_mux_rd[7].mux_rd_rise3_r_reg[7]_0\,
      Q => \gen_mux_rd[7].mux_rd_rise3_r_reg_n_0_[7]\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[0].old_sr_fall0_r_reg[0][0]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => store_sr_r0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall0_r_reg[0]_95\,
      Q => \gen_old_sr_div4.gen_old_sr[0].old_sr_fall0_r_reg[0]_191\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[0].old_sr_fall1_r_reg[0][0]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => store_sr_r0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall1_r_reg[0]_71\,
      Q => \gen_old_sr_div4.gen_old_sr[0].old_sr_fall1_r_reg[0]_207\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[0].old_sr_fall2_r[0][0]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => store_sr_r_reg_n_0,
      I1 => sr_valid_r_reg_n_0,
      O => store_sr_r0
    );
\gen_old_sr_div4.gen_old_sr[0].old_sr_fall2_r_reg[0][0]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => store_sr_r0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall2_r_reg[0]_79\,
      Q => \gen_old_sr_div4.gen_old_sr[0].old_sr_fall2_r_reg[0]_175\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[0].old_sr_fall3_r_reg[0][0]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => store_sr_r0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall3_r_reg[0]_55\,
      Q => \gen_old_sr_div4.gen_old_sr[0].old_sr_fall3_r_reg[0]_183\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[0].old_sr_rise0_r_reg[0][0]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => store_sr_r0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise0_r_reg[0]_47\,
      Q => \gen_old_sr_div4.gen_old_sr[0].old_sr_rise0_r_reg[0]_223\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[0].old_sr_rise1_r_reg[0][0]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => store_sr_r0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise1_r_reg[0]_87\,
      Q => \gen_old_sr_div4.gen_old_sr[0].old_sr_rise1_r_reg[0]_199\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[0].old_sr_rise2_r_reg[0][0]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => store_sr_r0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise2_r_reg[0]_63\,
      Q => \gen_old_sr_div4.gen_old_sr[0].old_sr_rise2_r_reg[0]_215\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[0].old_sr_rise3_r_reg[0][0]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => store_sr_r0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise3_r_reg[0]_103\,
      Q => \gen_old_sr_div4.gen_old_sr[0].old_sr_rise3_r_reg[0]_231\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[0].prev_sr_fall0_r_reg[0][0]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => sr_valid_r_reg_n_0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall0_r_reg[0]_95\,
      Q => \gen_old_sr_div4.gen_old_sr[0].prev_sr_fall0_r_reg[0]_143\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[0].prev_sr_fall1_r_reg[0][0]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => sr_valid_r_reg_n_0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall1_r_reg[0]_71\,
      Q => \gen_old_sr_div4.gen_old_sr[0].prev_sr_fall1_r_reg[0]_119\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[0].prev_sr_fall2_r_reg[0][0]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => sr_valid_r_reg_n_0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall2_r_reg[0]_79\,
      Q => \gen_old_sr_div4.gen_old_sr[0].prev_sr_fall2_r_reg[0]_127\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[0].prev_sr_fall3_r_reg[0][0]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => sr_valid_r_reg_n_0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall3_r_reg[0]_55\,
      Q => \gen_old_sr_div4.gen_old_sr[0].prev_sr_fall3_r_reg[0]_151\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[0].prev_sr_rise0_r_reg[0][0]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => sr_valid_r_reg_n_0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise0_r_reg[0]_47\,
      Q => \gen_old_sr_div4.gen_old_sr[0].prev_sr_rise0_r_reg[0]_159\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[0].prev_sr_rise1_r_reg[0][0]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => sr_valid_r_reg_n_0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise1_r_reg[0]_87\,
      Q => \gen_old_sr_div4.gen_old_sr[0].prev_sr_rise1_r_reg[0]_111\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[0].prev_sr_rise2_r_reg[0][0]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => sr_valid_r_reg_n_0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise2_r_reg[0]_63\,
      Q => \gen_old_sr_div4.gen_old_sr[0].prev_sr_rise2_r_reg[0]_135\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[0].prev_sr_rise3_r_reg[0][0]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => sr_valid_r_reg_n_0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise3_r_reg[0]_103\,
      Q => \gen_old_sr_div4.gen_old_sr[0].prev_sr_rise3_r_reg[0]_167\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[1].old_sr_fall0_r_reg[1][0]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => store_sr_r0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall0_r_reg[1]_96\,
      Q => \gen_old_sr_div4.gen_old_sr[1].old_sr_fall0_r_reg[1]_192\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[1].old_sr_fall1_r_reg[1][0]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => store_sr_r0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall1_r_reg[1]_72\,
      Q => \gen_old_sr_div4.gen_old_sr[1].old_sr_fall1_r_reg[1]_208\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[1].old_sr_fall2_r_reg[1][0]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => store_sr_r0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall2_r_reg[1]_80\,
      Q => \gen_old_sr_div4.gen_old_sr[1].old_sr_fall2_r_reg[1]_176\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[1].old_sr_fall3_r_reg[1][0]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => store_sr_r0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall3_r_reg[1]_56\,
      Q => \gen_old_sr_div4.gen_old_sr[1].old_sr_fall3_r_reg[1]_184\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[1].old_sr_rise0_r_reg[1][0]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => store_sr_r0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise0_r_reg[1]_48\,
      Q => \gen_old_sr_div4.gen_old_sr[1].old_sr_rise0_r_reg[1]_224\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[1].old_sr_rise1_r_reg[1][0]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => store_sr_r0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise1_r_reg[1]_88\,
      Q => \gen_old_sr_div4.gen_old_sr[1].old_sr_rise1_r_reg[1]_200\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[1].old_sr_rise2_r_reg[1][0]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => store_sr_r0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise2_r_reg[1]_64\,
      Q => \gen_old_sr_div4.gen_old_sr[1].old_sr_rise2_r_reg[1]_216\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[1].old_sr_rise3_r_reg[1][0]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => store_sr_r0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise3_r_reg[1]_104\,
      Q => \gen_old_sr_div4.gen_old_sr[1].old_sr_rise3_r_reg[1]_232\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[1].prev_sr_fall0_r_reg[1][0]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => sr_valid_r_reg_n_0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall0_r_reg[1]_96\,
      Q => \gen_old_sr_div4.gen_old_sr[1].prev_sr_fall0_r_reg[1]_144\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[1].prev_sr_fall1_r_reg[1][0]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => sr_valid_r_reg_n_0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall1_r_reg[1]_72\,
      Q => \gen_old_sr_div4.gen_old_sr[1].prev_sr_fall1_r_reg[1]_120\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[1].prev_sr_fall2_r_reg[1][0]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => sr_valid_r_reg_n_0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall2_r_reg[1]_80\,
      Q => \gen_old_sr_div4.gen_old_sr[1].prev_sr_fall2_r_reg[1]_128\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[1].prev_sr_fall3_r_reg[1][0]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => sr_valid_r_reg_n_0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall3_r_reg[1]_56\,
      Q => \gen_old_sr_div4.gen_old_sr[1].prev_sr_fall3_r_reg[1]_152\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[1].prev_sr_rise0_r_reg[1][0]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => sr_valid_r_reg_n_0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise0_r_reg[1]_48\,
      Q => \gen_old_sr_div4.gen_old_sr[1].prev_sr_rise0_r_reg[1]_160\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[1].prev_sr_rise1_r_reg[1][0]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => sr_valid_r_reg_n_0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise1_r_reg[1]_88\,
      Q => \gen_old_sr_div4.gen_old_sr[1].prev_sr_rise1_r_reg[1]_112\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[1].prev_sr_rise2_r_reg[1][0]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => sr_valid_r_reg_n_0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise2_r_reg[1]_64\,
      Q => \gen_old_sr_div4.gen_old_sr[1].prev_sr_rise2_r_reg[1]_136\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[1].prev_sr_rise3_r_reg[1][0]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => sr_valid_r_reg_n_0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise3_r_reg[1]_104\,
      Q => \gen_old_sr_div4.gen_old_sr[1].prev_sr_rise3_r_reg[1]_168\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[2].old_sr_fall0_r_reg[2][0]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => store_sr_r0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall0_r_reg[2]_97\,
      Q => \gen_old_sr_div4.gen_old_sr[2].old_sr_fall0_r_reg[2]_193\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[2].old_sr_fall1_r_reg[2][0]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => store_sr_r0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall1_r_reg[2]_73\,
      Q => \gen_old_sr_div4.gen_old_sr[2].old_sr_fall1_r_reg[2]_209\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[2].old_sr_fall2_r_reg[2][0]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => store_sr_r0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall2_r_reg[2]_81\,
      Q => \gen_old_sr_div4.gen_old_sr[2].old_sr_fall2_r_reg[2]_177\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[2].old_sr_fall3_r_reg[2][0]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => store_sr_r0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall3_r_reg[2]_57\,
      Q => \gen_old_sr_div4.gen_old_sr[2].old_sr_fall3_r_reg[2]_185\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[2].old_sr_rise0_r_reg[2][0]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => store_sr_r0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise0_r_reg[2]_49\,
      Q => \gen_old_sr_div4.gen_old_sr[2].old_sr_rise0_r_reg[2]_225\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[2].old_sr_rise1_r_reg[2][0]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => store_sr_r0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise1_r_reg[2]_89\,
      Q => \gen_old_sr_div4.gen_old_sr[2].old_sr_rise1_r_reg[2]_201\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[2].old_sr_rise2_r_reg[2][0]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => store_sr_r0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise2_r_reg[2]_65\,
      Q => \gen_old_sr_div4.gen_old_sr[2].old_sr_rise2_r_reg[2]_217\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[2].old_sr_rise3_r_reg[2][0]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => store_sr_r0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise3_r_reg[2]_105\,
      Q => \gen_old_sr_div4.gen_old_sr[2].old_sr_rise3_r_reg[2]_233\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[2].prev_sr_fall0_r_reg[2][0]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => sr_valid_r_reg_n_0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall0_r_reg[2]_97\,
      Q => \gen_old_sr_div4.gen_old_sr[2].prev_sr_fall0_r_reg[2]_145\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[2].prev_sr_fall1_r_reg[2][0]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => sr_valid_r_reg_n_0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall1_r_reg[2]_73\,
      Q => \gen_old_sr_div4.gen_old_sr[2].prev_sr_fall1_r_reg[2]_121\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[2].prev_sr_fall2_r_reg[2][0]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => sr_valid_r_reg_n_0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall2_r_reg[2]_81\,
      Q => \gen_old_sr_div4.gen_old_sr[2].prev_sr_fall2_r_reg[2]_129\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[2].prev_sr_fall3_r_reg[2][0]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => sr_valid_r_reg_n_0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall3_r_reg[2]_57\,
      Q => \gen_old_sr_div4.gen_old_sr[2].prev_sr_fall3_r_reg[2]_153\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[2].prev_sr_rise0_r_reg[2][0]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => sr_valid_r_reg_n_0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise0_r_reg[2]_49\,
      Q => \gen_old_sr_div4.gen_old_sr[2].prev_sr_rise0_r_reg[2]_161\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[2].prev_sr_rise1_r_reg[2][0]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => sr_valid_r_reg_n_0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise1_r_reg[2]_89\,
      Q => \gen_old_sr_div4.gen_old_sr[2].prev_sr_rise1_r_reg[2]_113\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[2].prev_sr_rise2_r_reg[2][0]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => sr_valid_r_reg_n_0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise2_r_reg[2]_65\,
      Q => \gen_old_sr_div4.gen_old_sr[2].prev_sr_rise2_r_reg[2]_137\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[2].prev_sr_rise3_r_reg[2][0]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => sr_valid_r_reg_n_0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise3_r_reg[2]_105\,
      Q => \gen_old_sr_div4.gen_old_sr[2].prev_sr_rise3_r_reg[2]_169\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[3].old_sr_fall0_r_reg[3][0]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => store_sr_r0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall0_r_reg[3]_98\,
      Q => \gen_old_sr_div4.gen_old_sr[3].old_sr_fall0_r_reg[3]_194\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[3].old_sr_fall1_r_reg[3][0]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => store_sr_r0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall1_r_reg[3]_74\,
      Q => \gen_old_sr_div4.gen_old_sr[3].old_sr_fall1_r_reg[3]_210\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[3].old_sr_fall2_r_reg[3][0]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => store_sr_r0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall2_r_reg[3]_82\,
      Q => \gen_old_sr_div4.gen_old_sr[3].old_sr_fall2_r_reg[3]_178\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[3].old_sr_fall3_r_reg[3][0]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => store_sr_r0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall3_r_reg[3]_58\,
      Q => \gen_old_sr_div4.gen_old_sr[3].old_sr_fall3_r_reg[3]_186\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[3].old_sr_rise0_r_reg[3][0]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => store_sr_r0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise0_r_reg[3]_50\,
      Q => \gen_old_sr_div4.gen_old_sr[3].old_sr_rise0_r_reg[3]_226\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[3].old_sr_rise1_r_reg[3][0]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => store_sr_r0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise1_r_reg[3]_90\,
      Q => \gen_old_sr_div4.gen_old_sr[3].old_sr_rise1_r_reg[3]_202\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[3].old_sr_rise2_r_reg[3][0]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => store_sr_r0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise2_r_reg[3]_66\,
      Q => \gen_old_sr_div4.gen_old_sr[3].old_sr_rise2_r_reg[3]_218\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[3].old_sr_rise3_r_reg[3][0]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => store_sr_r0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise3_r_reg[3]_106\,
      Q => \gen_old_sr_div4.gen_old_sr[3].old_sr_rise3_r_reg[3]_234\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[3].prev_sr_fall0_r_reg[3][0]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => sr_valid_r_reg_n_0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall0_r_reg[3]_98\,
      Q => \gen_old_sr_div4.gen_old_sr[3].prev_sr_fall0_r_reg[3]_146\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[3].prev_sr_fall1_r_reg[3][0]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => sr_valid_r_reg_n_0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall1_r_reg[3]_74\,
      Q => \gen_old_sr_div4.gen_old_sr[3].prev_sr_fall1_r_reg[3]_122\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[3].prev_sr_fall2_r_reg[3][0]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => sr_valid_r_reg_n_0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall2_r_reg[3]_82\,
      Q => \gen_old_sr_div4.gen_old_sr[3].prev_sr_fall2_r_reg[3]_130\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[3].prev_sr_fall3_r_reg[3][0]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => sr_valid_r_reg_n_0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall3_r_reg[3]_58\,
      Q => \gen_old_sr_div4.gen_old_sr[3].prev_sr_fall3_r_reg[3]_154\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[3].prev_sr_rise0_r_reg[3][0]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => sr_valid_r_reg_n_0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise0_r_reg[3]_50\,
      Q => \gen_old_sr_div4.gen_old_sr[3].prev_sr_rise0_r_reg[3]_162\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[3].prev_sr_rise1_r_reg[3][0]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => sr_valid_r_reg_n_0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise1_r_reg[3]_90\,
      Q => \gen_old_sr_div4.gen_old_sr[3].prev_sr_rise1_r_reg[3]_114\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[3].prev_sr_rise2_r_reg[3][0]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => sr_valid_r_reg_n_0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise2_r_reg[3]_66\,
      Q => \gen_old_sr_div4.gen_old_sr[3].prev_sr_rise2_r_reg[3]_138\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[3].prev_sr_rise3_r_reg[3][0]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => sr_valid_r_reg_n_0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise3_r_reg[3]_106\,
      Q => \gen_old_sr_div4.gen_old_sr[3].prev_sr_rise3_r_reg[3]_170\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[4].old_sr_fall0_r_reg[4][0]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => store_sr_r0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall0_r_reg[4]_99\,
      Q => \gen_old_sr_div4.gen_old_sr[4].old_sr_fall0_r_reg[4]_195\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[4].old_sr_fall1_r_reg[4][0]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => store_sr_r0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall1_r_reg[4]_75\,
      Q => \gen_old_sr_div4.gen_old_sr[4].old_sr_fall1_r_reg[4]_211\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[4].old_sr_fall2_r_reg[4][0]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => store_sr_r0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall2_r_reg[4]_83\,
      Q => \gen_old_sr_div4.gen_old_sr[4].old_sr_fall2_r_reg[4]_179\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[4].old_sr_fall3_r_reg[4][0]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => store_sr_r0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall3_r_reg[4]_59\,
      Q => \gen_old_sr_div4.gen_old_sr[4].old_sr_fall3_r_reg[4]_187\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[4].old_sr_rise0_r_reg[4][0]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => store_sr_r0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise0_r_reg[4]_51\,
      Q => \gen_old_sr_div4.gen_old_sr[4].old_sr_rise0_r_reg[4]_227\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[4].old_sr_rise1_r_reg[4][0]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => store_sr_r0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise1_r_reg[4]_91\,
      Q => \gen_old_sr_div4.gen_old_sr[4].old_sr_rise1_r_reg[4]_203\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[4].old_sr_rise2_r_reg[4][0]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => store_sr_r0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise2_r_reg[4]_67\,
      Q => \gen_old_sr_div4.gen_old_sr[4].old_sr_rise2_r_reg[4]_219\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[4].old_sr_rise3_r_reg[4][0]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => store_sr_r0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise3_r_reg[4]_107\,
      Q => \gen_old_sr_div4.gen_old_sr[4].old_sr_rise3_r_reg[4]_235\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[4].prev_sr_fall0_r_reg[4][0]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => sr_valid_r_reg_n_0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall0_r_reg[4]_99\,
      Q => \gen_old_sr_div4.gen_old_sr[4].prev_sr_fall0_r_reg[4]_147\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[4].prev_sr_fall1_r_reg[4][0]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => sr_valid_r_reg_n_0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall1_r_reg[4]_75\,
      Q => \gen_old_sr_div4.gen_old_sr[4].prev_sr_fall1_r_reg[4]_123\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[4].prev_sr_fall2_r_reg[4][0]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => sr_valid_r_reg_n_0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall2_r_reg[4]_83\,
      Q => \gen_old_sr_div4.gen_old_sr[4].prev_sr_fall2_r_reg[4]_131\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[4].prev_sr_fall3_r_reg[4][0]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => sr_valid_r_reg_n_0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall3_r_reg[4]_59\,
      Q => \gen_old_sr_div4.gen_old_sr[4].prev_sr_fall3_r_reg[4]_155\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[4].prev_sr_rise0_r_reg[4][0]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => sr_valid_r_reg_n_0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise0_r_reg[4]_51\,
      Q => \gen_old_sr_div4.gen_old_sr[4].prev_sr_rise0_r_reg[4]_163\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[4].prev_sr_rise1_r_reg[4][0]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => sr_valid_r_reg_n_0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise1_r_reg[4]_91\,
      Q => \gen_old_sr_div4.gen_old_sr[4].prev_sr_rise1_r_reg[4]_115\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[4].prev_sr_rise2_r_reg[4][0]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => sr_valid_r_reg_n_0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise2_r_reg[4]_67\,
      Q => \gen_old_sr_div4.gen_old_sr[4].prev_sr_rise2_r_reg[4]_139\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[4].prev_sr_rise3_r_reg[4][0]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => sr_valid_r_reg_n_0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise3_r_reg[4]_107\,
      Q => \gen_old_sr_div4.gen_old_sr[4].prev_sr_rise3_r_reg[4]_171\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[5].old_sr_fall0_r_reg[5][0]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => store_sr_r0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall0_r_reg[5]_100\,
      Q => \gen_old_sr_div4.gen_old_sr[5].old_sr_fall0_r_reg[5]_196\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[5].old_sr_fall1_r_reg[5][0]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => store_sr_r0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall1_r_reg[5]_76\,
      Q => \gen_old_sr_div4.gen_old_sr[5].old_sr_fall1_r_reg[5]_212\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[5].old_sr_fall2_r_reg[5][0]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => store_sr_r0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall2_r_reg[5]_84\,
      Q => \gen_old_sr_div4.gen_old_sr[5].old_sr_fall2_r_reg[5]_180\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[5].old_sr_fall3_r_reg[5][0]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => store_sr_r0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall3_r_reg[5]_60\,
      Q => \gen_old_sr_div4.gen_old_sr[5].old_sr_fall3_r_reg[5]_188\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[5].old_sr_rise0_r_reg[5][0]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => store_sr_r0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise0_r_reg[5]_52\,
      Q => \gen_old_sr_div4.gen_old_sr[5].old_sr_rise0_r_reg[5]_228\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[5].old_sr_rise1_r_reg[5][0]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => store_sr_r0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise1_r_reg[5]_92\,
      Q => \gen_old_sr_div4.gen_old_sr[5].old_sr_rise1_r_reg[5]_204\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[5].old_sr_rise2_r_reg[5][0]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => store_sr_r0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise2_r_reg[5]_68\,
      Q => \gen_old_sr_div4.gen_old_sr[5].old_sr_rise2_r_reg[5]_220\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[5].old_sr_rise3_r_reg[5][0]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => store_sr_r0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise3_r_reg[5]_108\,
      Q => \gen_old_sr_div4.gen_old_sr[5].old_sr_rise3_r_reg[5]_236\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[5].prev_sr_fall0_r_reg[5][0]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => sr_valid_r_reg_n_0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall0_r_reg[5]_100\,
      Q => \gen_old_sr_div4.gen_old_sr[5].prev_sr_fall0_r_reg[5]_148\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[5].prev_sr_fall1_r_reg[5][0]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => sr_valid_r_reg_n_0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall1_r_reg[5]_76\,
      Q => \gen_old_sr_div4.gen_old_sr[5].prev_sr_fall1_r_reg[5]_124\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[5].prev_sr_fall2_r_reg[5][0]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => sr_valid_r_reg_n_0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall2_r_reg[5]_84\,
      Q => \gen_old_sr_div4.gen_old_sr[5].prev_sr_fall2_r_reg[5]_132\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[5].prev_sr_fall3_r_reg[5][0]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => sr_valid_r_reg_n_0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall3_r_reg[5]_60\,
      Q => \gen_old_sr_div4.gen_old_sr[5].prev_sr_fall3_r_reg[5]_156\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[5].prev_sr_rise0_r_reg[5][0]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => sr_valid_r_reg_n_0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise0_r_reg[5]_52\,
      Q => \gen_old_sr_div4.gen_old_sr[5].prev_sr_rise0_r_reg[5]_164\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[5].prev_sr_rise1_r_reg[5][0]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => sr_valid_r_reg_n_0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise1_r_reg[5]_92\,
      Q => \gen_old_sr_div4.gen_old_sr[5].prev_sr_rise1_r_reg[5]_116\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[5].prev_sr_rise2_r_reg[5][0]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => sr_valid_r_reg_n_0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise2_r_reg[5]_68\,
      Q => \gen_old_sr_div4.gen_old_sr[5].prev_sr_rise2_r_reg[5]_140\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[5].prev_sr_rise3_r_reg[5][0]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => sr_valid_r_reg_n_0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise3_r_reg[5]_108\,
      Q => \gen_old_sr_div4.gen_old_sr[5].prev_sr_rise3_r_reg[5]_172\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[6].old_sr_fall0_r_reg[6][0]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => store_sr_r0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall0_r_reg[6]_101\,
      Q => \gen_old_sr_div4.gen_old_sr[6].old_sr_fall0_r_reg[6]_197\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[6].old_sr_fall1_r_reg[6][0]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => store_sr_r0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall1_r_reg[6]_77\,
      Q => \gen_old_sr_div4.gen_old_sr[6].old_sr_fall1_r_reg[6]_213\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[6].old_sr_fall2_r_reg[6][0]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => store_sr_r0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall2_r_reg[6]_85\,
      Q => \gen_old_sr_div4.gen_old_sr[6].old_sr_fall2_r_reg[6]_181\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[6].old_sr_fall3_r_reg[6][0]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => store_sr_r0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall3_r_reg[6]_61\,
      Q => \gen_old_sr_div4.gen_old_sr[6].old_sr_fall3_r_reg[6]_189\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[6].old_sr_rise0_r_reg[6][0]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => store_sr_r0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise0_r_reg[6]_53\,
      Q => \gen_old_sr_div4.gen_old_sr[6].old_sr_rise0_r_reg[6]_229\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[6].old_sr_rise1_r_reg[6][0]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => store_sr_r0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise1_r_reg[6]_93\,
      Q => \gen_old_sr_div4.gen_old_sr[6].old_sr_rise1_r_reg[6]_205\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[6].old_sr_rise2_r_reg[6][0]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => store_sr_r0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise2_r_reg[6]_69\,
      Q => \gen_old_sr_div4.gen_old_sr[6].old_sr_rise2_r_reg[6]_221\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[6].old_sr_rise3_r_reg[6][0]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => store_sr_r0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise3_r_reg[6]_109\,
      Q => \gen_old_sr_div4.gen_old_sr[6].old_sr_rise3_r_reg[6]_237\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[6].prev_sr_fall0_r_reg[6][0]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => sr_valid_r_reg_n_0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall0_r_reg[6]_101\,
      Q => \gen_old_sr_div4.gen_old_sr[6].prev_sr_fall0_r_reg[6]_149\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[6].prev_sr_fall1_r_reg[6][0]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => sr_valid_r_reg_n_0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall1_r_reg[6]_77\,
      Q => \gen_old_sr_div4.gen_old_sr[6].prev_sr_fall1_r_reg[6]_125\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[6].prev_sr_fall2_r_reg[6][0]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => sr_valid_r_reg_n_0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall2_r_reg[6]_85\,
      Q => \gen_old_sr_div4.gen_old_sr[6].prev_sr_fall2_r_reg[6]_133\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[6].prev_sr_fall3_r_reg[6][0]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => sr_valid_r_reg_n_0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall3_r_reg[6]_61\,
      Q => \gen_old_sr_div4.gen_old_sr[6].prev_sr_fall3_r_reg[6]_157\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[6].prev_sr_rise0_r_reg[6][0]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => sr_valid_r_reg_n_0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise0_r_reg[6]_53\,
      Q => \gen_old_sr_div4.gen_old_sr[6].prev_sr_rise0_r_reg[6]_165\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[6].prev_sr_rise1_r_reg[6][0]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => sr_valid_r_reg_n_0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise1_r_reg[6]_93\,
      Q => \gen_old_sr_div4.gen_old_sr[6].prev_sr_rise1_r_reg[6]_117\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[6].prev_sr_rise2_r_reg[6][0]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => sr_valid_r_reg_n_0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise2_r_reg[6]_69\,
      Q => \gen_old_sr_div4.gen_old_sr[6].prev_sr_rise2_r_reg[6]_141\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[6].prev_sr_rise3_r_reg[6][0]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => sr_valid_r_reg_n_0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise3_r_reg[6]_109\,
      Q => \gen_old_sr_div4.gen_old_sr[6].prev_sr_rise3_r_reg[6]_173\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[7].old_sr_fall0_r_reg[7][0]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => store_sr_r0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall0_r_reg[7]_102\,
      Q => \gen_old_sr_div4.gen_old_sr[7].old_sr_fall0_r_reg[7]_198\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[7].old_sr_fall1_r_reg[7][0]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => store_sr_r0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall1_r_reg[7]_78\,
      Q => \gen_old_sr_div4.gen_old_sr[7].old_sr_fall1_r_reg[7]_214\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[7].old_sr_fall2_r_reg[7][0]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => store_sr_r0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall2_r_reg[7]_86\,
      Q => \gen_old_sr_div4.gen_old_sr[7].old_sr_fall2_r_reg[7]_182\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[7].old_sr_fall3_r_reg[7][0]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => store_sr_r0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall3_r_reg[7]_62\,
      Q => \gen_old_sr_div4.gen_old_sr[7].old_sr_fall3_r_reg[7]_190\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[7].old_sr_rise0_r_reg[7][0]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => store_sr_r0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise0_r_reg[7]_54\,
      Q => \gen_old_sr_div4.gen_old_sr[7].old_sr_rise0_r_reg[7]_230\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[7].old_sr_rise1_r_reg[7][0]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => store_sr_r0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise1_r_reg[7]_94\,
      Q => \gen_old_sr_div4.gen_old_sr[7].old_sr_rise1_r_reg[7]_206\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[7].old_sr_rise2_r_reg[7][0]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => store_sr_r0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise2_r_reg[7]_70\,
      Q => \gen_old_sr_div4.gen_old_sr[7].old_sr_rise2_r_reg[7]_222\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[7].old_sr_rise3_r_reg[7][0]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => store_sr_r0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise3_r_reg[7]_110\,
      Q => \gen_old_sr_div4.gen_old_sr[7].old_sr_rise3_r_reg[7]_238\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[7].prev_sr_fall0_r_reg[7][0]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => sr_valid_r_reg_n_0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall0_r_reg[7]_102\,
      Q => \gen_old_sr_div4.gen_old_sr[7].prev_sr_fall0_r_reg[7]_150\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[7].prev_sr_fall1_r_reg[7][0]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => sr_valid_r_reg_n_0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall1_r_reg[7]_78\,
      Q => \gen_old_sr_div4.gen_old_sr[7].prev_sr_fall1_r_reg[7]_126\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[7].prev_sr_fall2_r_reg[7][0]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => sr_valid_r_reg_n_0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall2_r_reg[7]_86\,
      Q => \gen_old_sr_div4.gen_old_sr[7].prev_sr_fall2_r_reg[7]_134\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[7].prev_sr_fall3_r_reg[7][0]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => sr_valid_r_reg_n_0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall3_r_reg[7]_62\,
      Q => \gen_old_sr_div4.gen_old_sr[7].prev_sr_fall3_r_reg[7]_158\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[7].prev_sr_rise0_r_reg[7][0]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => sr_valid_r_reg_n_0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise0_r_reg[7]_54\,
      Q => \gen_old_sr_div4.gen_old_sr[7].prev_sr_rise0_r_reg[7]_166\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[7].prev_sr_rise1_r_reg[7][0]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => sr_valid_r_reg_n_0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise1_r_reg[7]_94\,
      Q => \gen_old_sr_div4.gen_old_sr[7].prev_sr_rise1_r_reg[7]_118\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[7].prev_sr_rise2_r_reg[7][0]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => sr_valid_r_reg_n_0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise2_r_reg[7]_70\,
      Q => \gen_old_sr_div4.gen_old_sr[7].prev_sr_rise2_r_reg[7]_142\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[7].prev_sr_rise3_r_reg[7][0]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => sr_valid_r_reg_n_0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise3_r_reg[7]_110\,
      Q => \gen_old_sr_div4.gen_old_sr[7].prev_sr_rise3_r_reg[7]_174\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_fall0_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall0_r_reg[0]_95\,
      Q => \gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_fall0_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_fall1_r[0]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall1_r_reg[0]_71\,
      O => \gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_fall1_r[0]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_fall1_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_fall1_r[0]_i_1_n_0\,
      Q => \gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_fall1_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_fall2_r[0]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall2_r_reg[0]_79\,
      O => \gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_fall2_r[0]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_fall2_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_fall2_r[0]_i_1_n_0\,
      Q => pat0_match_fall2_r(0),
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_fall3_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall3_r_reg[0]_55\,
      Q => pat0_match_fall3_r(0),
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_rise0_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise0_r_reg[0]_47\,
      Q => pat0_match_rise0_r(0),
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_rise1_r[0]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise1_r_reg[0]_87\,
      O => \gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_rise1_r[0]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_rise1_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_rise1_r[0]_i_1_n_0\,
      Q => pat0_match_rise1_r(0),
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_rise2_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise2_r_reg[0]_63\,
      Q => \gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_rise2_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_rise3_r[0]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise3_r_reg[0]_103\,
      O => \gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_rise3_r[0]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_rise3_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_rise3_r[0]_i_1_n_0\,
      Q => idel_pat0_match_rise3_r(0),
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[0].idel_pat1_match_fall1_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall1_r_reg[0]_71\,
      Q => pat0_match_fall1_r(0),
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[0].idel_pat1_match_fall3_r[0]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall3_r_reg[0]_55\,
      O => \gen_pat_match_div4.gen_pat_match[0].idel_pat1_match_fall3_r[0]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[0].idel_pat1_match_fall3_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[0].idel_pat1_match_fall3_r[0]_i_1_n_0\,
      Q => \gen_pat_match_div4.gen_pat_match[0].idel_pat1_match_fall3_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[0].idel_pat1_match_rise0_r[0]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise0_r_reg[0]_47\,
      O => \gen_pat_match_div4.gen_pat_match[0].idel_pat1_match_rise0_r[0]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[0].idel_pat1_match_rise0_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[0].idel_pat1_match_rise0_r[0]_i_1_n_0\,
      Q => \gen_pat_match_div4.gen_pat_match[0].idel_pat1_match_rise0_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[0].idel_pat1_match_rise1_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise1_r_reg[0]_87\,
      Q => idel_pat1_match_rise1_r(0),
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[0].idel_pat1_match_rise2_r[0]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise2_r_reg[0]_63\,
      O => \gen_pat_match_div4.gen_pat_match[0].idel_pat1_match_rise2_r[0]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[0].idel_pat1_match_rise2_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[0].idel_pat1_match_rise2_r[0]_i_1_n_0\,
      Q => pat0_match_rise2_r(0),
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[0].idel_pat1_match_rise3_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise3_r_reg[0]_103\,
      Q => pat0_match_rise3_r(0),
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[0].pat0_match_fall0_r[0]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall0_r_reg[0]_95\,
      O => \gen_pat_match_div4.gen_pat_match[0].pat0_match_fall0_r[0]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[0].pat0_match_fall0_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[0].pat0_match_fall0_r[0]_i_1_n_0\,
      Q => pat0_match_fall0_r(0),
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[0].pat1_match_fall2_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall2_r_reg[0]_79\,
      Q => \gen_pat_match_div4.gen_pat_match[0].pat1_match_fall2_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_fall0_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall0_r_reg[1]_96\,
      Q => pat0_match_fall0_r(1),
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_fall1_r[1]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall1_r_reg[1]_72\,
      O => \gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_fall1_r[1]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_fall1_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_fall1_r[1]_i_1_n_0\,
      Q => pat0_match_fall1_r(1),
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_fall2_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall2_r_reg[1]_80\,
      Q => \gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_fall2_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_fall3_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall3_r_reg[1]_56\,
      Q => \gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_fall3_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_rise0_r[1]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise0_r_reg[1]_48\,
      O => \gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_rise0_r[1]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_rise0_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_rise0_r[1]_i_1_n_0\,
      Q => \gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_rise0_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_rise1_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise1_r_reg[1]_88\,
      Q => idel_pat1_match_rise1_r(1),
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_rise2_r[1]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise2_r_reg[1]_64\,
      O => \gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_rise2_r[1]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_rise2_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_rise2_r[1]_i_1_n_0\,
      Q => \gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_rise2_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_rise3_r[1]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise3_r_reg[1]_104\,
      O => \gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_rise3_r[1]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_rise3_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_rise3_r[1]_i_1_n_0\,
      Q => idel_pat0_match_rise3_r(1),
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[1].idel_pat1_match_fall0_r[1]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall0_r_reg[1]_96\,
      O => \gen_pat_match_div4.gen_pat_match[1].idel_pat1_match_fall0_r[1]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[1].idel_pat1_match_fall0_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[1].idel_pat1_match_fall0_r[1]_i_1_n_0\,
      Q => \gen_pat_match_div4.gen_pat_match[1].idel_pat1_match_fall0_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[1].idel_pat1_match_fall1_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall1_r_reg[1]_72\,
      Q => \gen_pat_match_div4.gen_pat_match[1].idel_pat1_match_fall1_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[1].idel_pat1_match_fall2_r[1]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall2_r_reg[1]_80\,
      O => \gen_pat_match_div4.gen_pat_match[1].idel_pat1_match_fall2_r[1]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[1].idel_pat1_match_fall2_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[1].idel_pat1_match_fall2_r[1]_i_1_n_0\,
      Q => pat0_match_fall2_r(1),
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[1].idel_pat1_match_rise2_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise2_r_reg[1]_64\,
      Q => pat0_match_rise2_r(1),
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[1].pat0_match_fall3_r[1]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall3_r_reg[1]_56\,
      O => \gen_pat_match_div4.gen_pat_match[1].pat0_match_fall3_r[1]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[1].pat0_match_fall3_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[1].pat0_match_fall3_r[1]_i_1_n_0\,
      Q => pat0_match_fall3_r(1),
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[1].pat0_match_rise0_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise0_r_reg[1]_48\,
      Q => pat0_match_rise0_r(1),
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[1].pat0_match_rise1_r[1]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise1_r_reg[1]_88\,
      O => \gen_pat_match_div4.gen_pat_match[1].pat0_match_rise1_r[1]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[1].pat0_match_rise1_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[1].pat0_match_rise1_r[1]_i_1_n_0\,
      Q => pat0_match_rise1_r(1),
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[1].pat0_match_rise3_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise3_r_reg[1]_104\,
      Q => pat0_match_rise3_r(1),
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_fall0_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall0_r_reg[2]_97\,
      Q => pat0_match_fall0_r(2),
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_fall1_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall1_r_reg[2]_73\,
      Q => \gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_fall1_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_fall2_r[2]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall2_r_reg[2]_81\,
      O => \gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_fall2_r[2]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_fall2_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_fall2_r[2]_i_1_n_0\,
      Q => \gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_fall2_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_fall3_r[2]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall3_r_reg[2]_57\,
      O => \gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_fall3_r[2]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_fall3_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_fall3_r[2]_i_1_n_0\,
      Q => pat0_match_fall3_r(2),
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_rise0_r[2]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise0_r_reg[2]_49\,
      O => \gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_rise0_r[2]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_rise0_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_rise0_r[2]_i_1_n_0\,
      Q => \gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_rise0_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_rise1_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise1_r_reg[2]_89\,
      Q => pat0_match_rise1_r(2),
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_rise2_r[2]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise2_r_reg[2]_65\,
      O => \gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_rise2_r[2]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_rise2_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_rise2_r[2]_i_1_n_0\,
      Q => pat0_match_rise2_r(2),
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_rise3_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise3_r_reg[2]_105\,
      Q => idel_pat0_match_rise3_r(2),
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[2].idel_pat1_match_fall0_r[2]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall0_r_reg[2]_97\,
      O => \gen_pat_match_div4.gen_pat_match[2].idel_pat1_match_fall0_r[2]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[2].idel_pat1_match_fall0_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[2].idel_pat1_match_fall0_r[2]_i_1_n_0\,
      Q => \gen_pat_match_div4.gen_pat_match[2].idel_pat1_match_fall0_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[2].idel_pat1_match_fall2_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall2_r_reg[2]_81\,
      Q => pat0_match_fall2_r(2),
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[2].idel_pat1_match_rise0_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise0_r_reg[2]_49\,
      Q => pat0_match_rise0_r(2),
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[2].idel_pat1_match_rise1_r[2]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise1_r_reg[2]_89\,
      O => \gen_pat_match_div4.gen_pat_match[2].idel_pat1_match_rise1_r[2]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[2].idel_pat1_match_rise1_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[2].idel_pat1_match_rise1_r[2]_i_1_n_0\,
      Q => idel_pat1_match_rise1_r(2),
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[2].idel_pat1_match_rise2_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise2_r_reg[2]_65\,
      Q => \gen_pat_match_div4.gen_pat_match[2].idel_pat1_match_rise2_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[2].idel_pat1_match_rise3_r[2]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise3_r_reg[2]_105\,
      O => \gen_pat_match_div4.gen_pat_match[2].idel_pat1_match_rise3_r[2]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[2].idel_pat1_match_rise3_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[2].idel_pat1_match_rise3_r[2]_i_1_n_0\,
      Q => pat0_match_rise3_r(2),
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[2].pat0_match_fall1_r[2]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall1_r_reg[2]_73\,
      O => \gen_pat_match_div4.gen_pat_match[2].pat0_match_fall1_r[2]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[2].pat0_match_fall1_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[2].pat0_match_fall1_r[2]_i_1_n_0\,
      Q => pat0_match_fall1_r(2),
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[2].pat1_match_fall3_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall3_r_reg[2]_57\,
      Q => \gen_pat_match_div4.gen_pat_match[2].pat1_match_fall3_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_fall0_r[3]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall0_r_reg[3]_98\,
      O => \gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_fall0_r[3]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_fall0_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_fall0_r[3]_i_1_n_0\,
      Q => \gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_fall0_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_fall1_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall1_r_reg[3]_74\,
      Q => pat0_match_fall1_r(3),
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_fall2_r[3]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall2_r_reg[3]_82\,
      O => \gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_fall2_r[3]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_fall2_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_fall2_r[3]_i_1_n_0\,
      Q => pat0_match_fall2_r(3),
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_fall3_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall3_r_reg[3]_58\,
      Q => \gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_fall3_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_rise0_r[3]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise0_r_reg[3]_50\,
      O => \gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_rise0_r[3]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_rise0_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_rise0_r[3]_i_1_n_0\,
      Q => pat0_match_rise0_r(3),
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_rise1_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise1_r_reg[3]_90\,
      Q => pat0_match_rise1_r(3),
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_rise2_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise2_r_reg[3]_66\,
      Q => \gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_rise2_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_rise3_r[3]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise3_r_reg[3]_106\,
      O => \gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_rise3_r[3]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_rise3_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_rise3_r[3]_i_1_n_0\,
      Q => idel_pat0_match_rise3_r(3),
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[3].idel_pat1_match_fall0_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall0_r_reg[3]_98\,
      Q => pat0_match_fall0_r(3),
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[3].idel_pat1_match_fall1_r[3]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall1_r_reg[3]_74\,
      O => \gen_pat_match_div4.gen_pat_match[3].idel_pat1_match_fall1_r[3]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[3].idel_pat1_match_fall1_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[3].idel_pat1_match_fall1_r[3]_i_1_n_0\,
      Q => \gen_pat_match_div4.gen_pat_match[3].idel_pat1_match_fall1_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[3].idel_pat1_match_fall2_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall2_r_reg[3]_82\,
      Q => \gen_pat_match_div4.gen_pat_match[3].idel_pat1_match_fall2_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[3].idel_pat1_match_fall3_r[3]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall3_r_reg[3]_58\,
      O => \gen_pat_match_div4.gen_pat_match[3].idel_pat1_match_fall3_r[3]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[3].idel_pat1_match_fall3_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[3].idel_pat1_match_fall3_r[3]_i_1_n_0\,
      Q => pat0_match_fall3_r(3),
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[3].idel_pat1_match_rise1_r[3]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise1_r_reg[3]_90\,
      O => \gen_pat_match_div4.gen_pat_match[3].idel_pat1_match_rise1_r[3]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[3].idel_pat1_match_rise1_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[3].idel_pat1_match_rise1_r[3]_i_1_n_0\,
      Q => idel_pat1_match_rise1_r(3),
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[3].idel_pat1_match_rise3_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise3_r_reg[3]_106\,
      Q => pat0_match_rise3_r(3),
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[3].pat0_match_rise2_r[3]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise2_r_reg[3]_66\,
      O => \gen_pat_match_div4.gen_pat_match[3].pat0_match_rise2_r[3]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[3].pat0_match_rise2_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[3].pat0_match_rise2_r[3]_i_1_n_0\,
      Q => pat0_match_rise2_r(3),
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[3].pat1_match_rise0_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise0_r_reg[3]_50\,
      Q => \gen_pat_match_div4.gen_pat_match[3].pat1_match_rise0_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_fall0_r_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall0_r_reg[4]_99\,
      Q => \gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_fall0_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_fall1_r[4]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall1_r_reg[4]_75\,
      O => \gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_fall1_r[4]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_fall1_r_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_fall1_r[4]_i_1_n_0\,
      Q => \gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_fall1_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_fall2_r[4]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall2_r_reg[4]_83\,
      O => \gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_fall2_r[4]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_fall2_r_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_fall2_r[4]_i_1_n_0\,
      Q => pat0_match_fall2_r(4),
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_fall3_r_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall3_r_reg[4]_59\,
      Q => pat0_match_fall3_r(4),
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_rise0_r_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise0_r_reg[4]_51\,
      Q => pat0_match_rise0_r(4),
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_rise1_r[4]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise1_r_reg[4]_91\,
      O => \gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_rise1_r[4]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_rise1_r_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_rise1_r[4]_i_1_n_0\,
      Q => pat0_match_rise1_r(4),
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_rise2_r_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise2_r_reg[4]_67\,
      Q => \gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_rise2_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_rise3_r[4]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise3_r_reg[4]_107\,
      O => \gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_rise3_r[4]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_rise3_r_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_rise3_r[4]_i_1_n_0\,
      Q => idel_pat0_match_rise3_r(4),
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[4].idel_pat1_match_fall1_r_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall1_r_reg[4]_75\,
      Q => pat0_match_fall1_r(4),
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[4].idel_pat1_match_fall3_r[4]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall3_r_reg[4]_59\,
      O => \gen_pat_match_div4.gen_pat_match[4].idel_pat1_match_fall3_r[4]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[4].idel_pat1_match_fall3_r_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[4].idel_pat1_match_fall3_r[4]_i_1_n_0\,
      Q => \gen_pat_match_div4.gen_pat_match[4].idel_pat1_match_fall3_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[4].idel_pat1_match_rise0_r[4]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise0_r_reg[4]_51\,
      O => \gen_pat_match_div4.gen_pat_match[4].idel_pat1_match_rise0_r[4]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[4].idel_pat1_match_rise0_r_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[4].idel_pat1_match_rise0_r[4]_i_1_n_0\,
      Q => \gen_pat_match_div4.gen_pat_match[4].idel_pat1_match_rise0_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[4].idel_pat1_match_rise1_r_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise1_r_reg[4]_91\,
      Q => idel_pat1_match_rise1_r(4),
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[4].idel_pat1_match_rise2_r[4]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise2_r_reg[4]_67\,
      O => \gen_pat_match_div4.gen_pat_match[4].idel_pat1_match_rise2_r[4]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[4].idel_pat1_match_rise2_r_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[4].idel_pat1_match_rise2_r[4]_i_1_n_0\,
      Q => pat0_match_rise2_r(4),
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[4].idel_pat1_match_rise3_r_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise3_r_reg[4]_107\,
      Q => pat0_match_rise3_r(4),
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[4].pat0_match_fall0_r[4]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall0_r_reg[4]_99\,
      O => \gen_pat_match_div4.gen_pat_match[4].pat0_match_fall0_r[4]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[4].pat0_match_fall0_r_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[4].pat0_match_fall0_r[4]_i_1_n_0\,
      Q => pat0_match_fall0_r(4),
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[4].pat1_match_fall2_r_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall2_r_reg[4]_83\,
      Q => \gen_pat_match_div4.gen_pat_match[4].pat1_match_fall2_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_fall0_r_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall0_r_reg[5]_100\,
      Q => pat0_match_fall0_r(5),
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_fall1_r[5]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall1_r_reg[5]_76\,
      O => \gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_fall1_r[5]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_fall1_r_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_fall1_r[5]_i_1_n_0\,
      Q => pat0_match_fall1_r(5),
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_fall2_r_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall2_r_reg[5]_84\,
      Q => \gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_fall2_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_fall3_r_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall3_r_reg[5]_60\,
      Q => \gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_fall3_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_rise0_r[5]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise0_r_reg[5]_52\,
      O => \gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_rise0_r[5]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_rise0_r_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_rise0_r[5]_i_1_n_0\,
      Q => \gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_rise0_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_rise1_r_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise1_r_reg[5]_92\,
      Q => idel_pat1_match_rise1_r(5),
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_rise2_r[5]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise2_r_reg[5]_68\,
      O => \gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_rise2_r[5]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_rise2_r_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_rise2_r[5]_i_1_n_0\,
      Q => \gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_rise2_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_rise3_r[5]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise3_r_reg[5]_108\,
      O => \gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_rise3_r[5]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_rise3_r_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_rise3_r[5]_i_1_n_0\,
      Q => idel_pat0_match_rise3_r(5),
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[5].idel_pat1_match_fall0_r[5]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall0_r_reg[5]_100\,
      O => \gen_pat_match_div4.gen_pat_match[5].idel_pat1_match_fall0_r[5]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[5].idel_pat1_match_fall0_r_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[5].idel_pat1_match_fall0_r[5]_i_1_n_0\,
      Q => \gen_pat_match_div4.gen_pat_match[5].idel_pat1_match_fall0_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[5].idel_pat1_match_fall1_r_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall1_r_reg[5]_76\,
      Q => \gen_pat_match_div4.gen_pat_match[5].idel_pat1_match_fall1_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[5].idel_pat1_match_fall2_r[5]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall2_r_reg[5]_84\,
      O => \gen_pat_match_div4.gen_pat_match[5].idel_pat1_match_fall2_r[5]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[5].idel_pat1_match_fall2_r_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[5].idel_pat1_match_fall2_r[5]_i_1_n_0\,
      Q => pat0_match_fall2_r(5),
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[5].idel_pat1_match_rise2_r_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise2_r_reg[5]_68\,
      Q => pat0_match_rise2_r(5),
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[5].pat0_match_fall3_r[5]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall3_r_reg[5]_60\,
      O => \gen_pat_match_div4.gen_pat_match[5].pat0_match_fall3_r[5]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[5].pat0_match_fall3_r_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[5].pat0_match_fall3_r[5]_i_1_n_0\,
      Q => pat0_match_fall3_r(5),
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[5].pat0_match_rise0_r_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise0_r_reg[5]_52\,
      Q => pat0_match_rise0_r(5),
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[5].pat0_match_rise1_r[5]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise1_r_reg[5]_92\,
      O => \gen_pat_match_div4.gen_pat_match[5].pat0_match_rise1_r[5]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[5].pat0_match_rise1_r_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[5].pat0_match_rise1_r[5]_i_1_n_0\,
      Q => pat0_match_rise1_r(5),
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[5].pat0_match_rise3_r_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise3_r_reg[5]_108\,
      Q => pat0_match_rise3_r(5),
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_fall0_r_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall0_r_reg[6]_101\,
      Q => pat0_match_fall0_r(6),
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_fall1_r_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall1_r_reg[6]_77\,
      Q => \gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_fall1_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_fall2_r[6]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall2_r_reg[6]_85\,
      O => \gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_fall2_r[6]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_fall2_r_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_fall2_r[6]_i_1_n_0\,
      Q => \gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_fall2_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_fall3_r[6]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall3_r_reg[6]_61\,
      O => \gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_fall3_r[6]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_fall3_r_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_fall3_r[6]_i_1_n_0\,
      Q => pat0_match_fall3_r(6),
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_rise0_r[6]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise0_r_reg[6]_53\,
      O => \gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_rise0_r[6]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_rise0_r_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_rise0_r[6]_i_1_n_0\,
      Q => \gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_rise0_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_rise1_r_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise1_r_reg[6]_93\,
      Q => pat0_match_rise1_r(6),
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_rise2_r[6]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise2_r_reg[6]_69\,
      O => \gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_rise2_r[6]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_rise2_r_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_rise2_r[6]_i_1_n_0\,
      Q => pat0_match_rise2_r(6),
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_rise3_r_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise3_r_reg[6]_109\,
      Q => idel_pat0_match_rise3_r(6),
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[6].idel_pat1_match_fall0_r[6]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall0_r_reg[6]_101\,
      O => \gen_pat_match_div4.gen_pat_match[6].idel_pat1_match_fall0_r[6]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[6].idel_pat1_match_fall0_r_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[6].idel_pat1_match_fall0_r[6]_i_1_n_0\,
      Q => \gen_pat_match_div4.gen_pat_match[6].idel_pat1_match_fall0_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[6].idel_pat1_match_fall2_r_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall2_r_reg[6]_85\,
      Q => pat0_match_fall2_r(6),
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[6].idel_pat1_match_rise0_r_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise0_r_reg[6]_53\,
      Q => pat0_match_rise0_r(6),
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[6].idel_pat1_match_rise1_r[6]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise1_r_reg[6]_93\,
      O => \gen_pat_match_div4.gen_pat_match[6].idel_pat1_match_rise1_r[6]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[6].idel_pat1_match_rise1_r_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[6].idel_pat1_match_rise1_r[6]_i_1_n_0\,
      Q => idel_pat1_match_rise1_r(6),
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[6].idel_pat1_match_rise2_r_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise2_r_reg[6]_69\,
      Q => \gen_pat_match_div4.gen_pat_match[6].idel_pat1_match_rise2_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[6].idel_pat1_match_rise3_r[6]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise3_r_reg[6]_109\,
      O => \gen_pat_match_div4.gen_pat_match[6].idel_pat1_match_rise3_r[6]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[6].idel_pat1_match_rise3_r_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[6].idel_pat1_match_rise3_r[6]_i_1_n_0\,
      Q => pat0_match_rise3_r(6),
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[6].pat0_match_fall1_r[6]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall1_r_reg[6]_77\,
      O => \gen_pat_match_div4.gen_pat_match[6].pat0_match_fall1_r[6]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[6].pat0_match_fall1_r_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[6].pat0_match_fall1_r[6]_i_1_n_0\,
      Q => pat0_match_fall1_r(6),
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[6].pat1_match_fall3_r_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall3_r_reg[6]_61\,
      Q => \gen_pat_match_div4.gen_pat_match[6].pat1_match_fall3_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_fall0_r[7]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall0_r_reg[7]_102\,
      O => \gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_fall0_r[7]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_fall0_r_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_fall0_r[7]_i_1_n_0\,
      Q => \gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_fall0_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_fall1_r_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall1_r_reg[7]_78\,
      Q => pat0_match_fall1_r(7),
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_fall2_r[7]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall2_r_reg[7]_86\,
      O => \gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_fall2_r[7]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_fall2_r_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_fall2_r[7]_i_1_n_0\,
      Q => pat0_match_fall2_r(7),
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_fall3_r_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall3_r_reg[7]_62\,
      Q => \gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_fall3_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_rise0_r[7]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise0_r_reg[7]_54\,
      O => \gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_rise0_r[7]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_rise0_r_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_rise0_r[7]_i_1_n_0\,
      Q => pat0_match_rise0_r(7),
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_rise1_r_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise1_r_reg[7]_94\,
      Q => pat0_match_rise1_r(7),
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_rise2_r_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise2_r_reg[7]_70\,
      Q => \gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_rise2_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_rise3_r[7]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise3_r_reg[7]_110\,
      O => \gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_rise3_r[7]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_rise3_r_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_rise3_r[7]_i_1_n_0\,
      Q => idel_pat0_match_rise3_r(7),
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[7].idel_pat1_match_fall0_r_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall0_r_reg[7]_102\,
      Q => pat0_match_fall0_r(7),
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[7].idel_pat1_match_fall1_r[7]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall1_r_reg[7]_78\,
      O => \gen_pat_match_div4.gen_pat_match[7].idel_pat1_match_fall1_r[7]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[7].idel_pat1_match_fall1_r_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[7].idel_pat1_match_fall1_r[7]_i_1_n_0\,
      Q => \gen_pat_match_div4.gen_pat_match[7].idel_pat1_match_fall1_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[7].idel_pat1_match_fall2_r_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall2_r_reg[7]_86\,
      Q => \gen_pat_match_div4.gen_pat_match[7].idel_pat1_match_fall2_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[7].idel_pat1_match_fall3_r[7]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall3_r_reg[7]_62\,
      O => \gen_pat_match_div4.gen_pat_match[7].idel_pat1_match_fall3_r[7]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[7].idel_pat1_match_fall3_r_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[7].idel_pat1_match_fall3_r[7]_i_1_n_0\,
      Q => pat0_match_fall3_r(7),
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[7].idel_pat1_match_rise1_r[7]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise1_r_reg[7]_94\,
      O => \gen_pat_match_div4.gen_pat_match[7].idel_pat1_match_rise1_r[7]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[7].idel_pat1_match_rise1_r_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[7].idel_pat1_match_rise1_r[7]_i_1_n_0\,
      Q => idel_pat1_match_rise1_r(7),
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[7].idel_pat1_match_rise3_r_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise3_r_reg[7]_110\,
      Q => pat0_match_rise3_r(7),
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[7].pat0_match_rise2_r[7]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise2_r_reg[7]_70\,
      O => \gen_pat_match_div4.gen_pat_match[7].pat0_match_rise2_r[7]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[7].pat0_match_rise2_r_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[7].pat0_match_rise2_r[7]_i_1_n_0\,
      Q => pat0_match_rise2_r(7),
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[7].pat1_match_rise0_r_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise0_r_reg[7]_54\,
      Q => \gen_pat_match_div4.gen_pat_match[7].pat1_match_rise0_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.idel_pat0_data_match_r_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00008000"
    )
        port map (
      I0 => idel_pat0_match_fall0_and_r,
      I1 => idel_pat0_match_rise1_and_r,
      I2 => idel_pat0_match_rise3_and_r,
      I3 => idel_pat0_match_fall3_and_r,
      I4 => \gen_pat_match_div4.idel_pat0_data_match_r_i_2_n_0\,
      O => idel_pat0_data_match_r0
    );
\gen_pat_match_div4.idel_pat0_data_match_r_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7FFF"
    )
        port map (
      I0 => idel_pat0_match_fall1_and_r,
      I1 => idel_pat0_match_fall2_and_r,
      I2 => idel_pat0_match_rise0_and_r,
      I3 => idel_pat0_match_rise2_and_r,
      O => \gen_pat_match_div4.idel_pat0_data_match_r_i_2_n_0\
    );
\gen_pat_match_div4.idel_pat0_data_match_r_reg\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => idel_pat0_data_match_r0,
      Q => \gen_pat_match_div4.idel_pat0_data_match_r_reg_n_0\,
      R => '0'
    );
\gen_pat_match_div4.idel_pat0_match_fall0_and_r_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8000000000000000"
    )
        port map (
      I0 => \gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_fall0_r_reg\,
      I1 => \gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_fall0_r_reg\,
      I2 => \gen_pat_match_div4.pat1_match_fall0_and_r_i_2_n_0\,
      I3 => pat0_match_fall0_r(2),
      I4 => pat0_match_fall0_r(5),
      I5 => pat0_match_fall0_r(6),
      O => \gen_pat_match_div4.idel_pat0_match_fall0_and_r_i_1_n_0\
    );
\gen_pat_match_div4.idel_pat0_match_fall0_and_r_reg\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_pat_match_div4.idel_pat0_match_fall0_and_r_i_1_n_0\,
      Q => idel_pat0_match_fall0_and_r,
      R => '0'
    );
\gen_pat_match_div4.idel_pat0_match_fall1_and_r_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8000000000000000"
    )
        port map (
      I0 => \gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_fall1_r_reg\,
      I1 => \gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_fall1_r_reg\,
      I2 => \gen_pat_match_div4.pat1_match_fall1_and_r_i_2_n_0\,
      I3 => pat0_match_fall1_r(1),
      I4 => pat0_match_fall1_r(5),
      I5 => pat0_match_fall1_r(7),
      O => \gen_pat_match_div4.idel_pat0_match_fall1_and_r_i_1_n_0\
    );
\gen_pat_match_div4.idel_pat0_match_fall1_and_r_reg\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_pat_match_div4.idel_pat0_match_fall1_and_r_i_1_n_0\,
      Q => idel_pat0_match_fall1_and_r,
      R => '0'
    );
\gen_pat_match_div4.idel_pat0_match_fall2_and_r_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"80"
    )
        port map (
      I0 => \gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_fall2_r_reg\,
      I1 => \gen_pat_match_div4.idel_pat0_match_fall2_and_r_i_2_n_0\,
      I2 => pat0_match_fall2_r(3),
      O => \gen_pat_match_div4.idel_pat0_match_fall2_and_r_i_1_n_0\
    );
\gen_pat_match_div4.idel_pat0_match_fall2_and_r_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8000000000000000"
    )
        port map (
      I0 => \gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_fall2_r_reg\,
      I1 => \gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_fall2_r_reg\,
      I2 => pat0_match_fall2_r(0),
      I3 => \gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_fall2_r_reg\,
      I4 => pat0_match_fall2_r(4),
      I5 => pat0_match_fall2_r(7),
      O => \gen_pat_match_div4.idel_pat0_match_fall2_and_r_i_2_n_0\
    );
\gen_pat_match_div4.idel_pat0_match_fall2_and_r_reg\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_pat_match_div4.idel_pat0_match_fall2_and_r_i_1_n_0\,
      Q => idel_pat0_match_fall2_and_r,
      R => '0'
    );
\gen_pat_match_div4.idel_pat0_match_fall3_and_r_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00008000"
    )
        port map (
      I0 => \gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_fall3_r_reg\,
      I1 => \gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_fall3_r_reg\,
      I2 => pat0_match_fall3_r(6),
      I3 => pat0_match_fall3_r(4),
      I4 => \gen_pat_match_div4.idel_pat0_match_fall3_and_r_i_2_n_0\,
      O => \gen_pat_match_div4.idel_pat0_match_fall3_and_r_i_1_n_0\
    );
\gen_pat_match_div4.idel_pat0_match_fall3_and_r_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7FFF"
    )
        port map (
      I0 => pat0_match_fall3_r(0),
      I1 => pat0_match_fall3_r(2),
      I2 => \gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_fall3_r_reg\,
      I3 => \gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_fall3_r_reg\,
      O => \gen_pat_match_div4.idel_pat0_match_fall3_and_r_i_2_n_0\
    );
\gen_pat_match_div4.idel_pat0_match_fall3_and_r_reg\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_pat_match_div4.idel_pat0_match_fall3_and_r_i_1_n_0\,
      Q => idel_pat0_match_fall3_and_r,
      R => '0'
    );
\gen_pat_match_div4.idel_pat0_match_rise0_and_r_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"80000000"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_match_rise0_and_r_i_2_n_0\,
      I1 => \gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_rise0_r_reg\,
      I2 => \gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_rise0_r_reg\,
      I3 => pat0_match_rise0_r(7),
      I4 => pat0_match_rise0_r(3),
      O => \gen_pat_match_div4.idel_pat0_match_rise0_and_r_i_1_n_0\
    );
\gen_pat_match_div4.idel_pat0_match_rise0_and_r_reg\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_pat_match_div4.idel_pat0_match_rise0_and_r_i_1_n_0\,
      Q => idel_pat0_match_rise0_and_r,
      R => '0'
    );
\gen_pat_match_div4.idel_pat0_match_rise1_and_r_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"80000000"
    )
        port map (
      I0 => \gen_pat_match_div4.pat0_match_rise1_and_r_i_2_n_0\,
      I1 => idel_pat1_match_rise1_r(5),
      I2 => idel_pat1_match_rise1_r(1),
      I3 => pat0_match_rise1_r(4),
      I4 => pat0_match_rise1_r(0),
      O => \gen_pat_match_div4.idel_pat0_match_rise1_and_r_i_1_n_0\
    );
\gen_pat_match_div4.idel_pat0_match_rise1_and_r_reg\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_pat_match_div4.idel_pat0_match_rise1_and_r_i_1_n_0\,
      Q => idel_pat0_match_rise1_and_r,
      R => '0'
    );
\gen_pat_match_div4.idel_pat0_match_rise2_and_r_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"80"
    )
        port map (
      I0 => pat0_match_rise2_r(6),
      I1 => \gen_pat_match_div4.idel_pat0_match_rise2_and_r_i_2_n_0\,
      I2 => \gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_rise2_r_reg\,
      O => \gen_pat_match_div4.idel_pat0_match_rise2_and_r_i_1_n_0\
    );
\gen_pat_match_div4.idel_pat0_match_rise2_and_r_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8000000000000000"
    )
        port map (
      I0 => \gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_rise2_r_reg\,
      I1 => \gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_rise2_r_reg\,
      I2 => \gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_rise2_r_reg\,
      I3 => pat0_match_rise2_r(2),
      I4 => \gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_rise2_r_reg\,
      I5 => \gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_rise2_r_reg\,
      O => \gen_pat_match_div4.idel_pat0_match_rise2_and_r_i_2_n_0\
    );
\gen_pat_match_div4.idel_pat0_match_rise2_and_r_reg\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_pat_match_div4.idel_pat0_match_rise2_and_r_i_1_n_0\,
      Q => idel_pat0_match_rise2_and_r,
      R => '0'
    );
\gen_pat_match_div4.idel_pat0_match_rise3_and_r_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"80000000"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_match_rise3_and_r_i_2_n_0\,
      I1 => idel_pat0_match_rise3_r(6),
      I2 => idel_pat0_match_rise3_r(2),
      I3 => idel_pat0_match_rise3_r(5),
      I4 => idel_pat0_match_rise3_r(1),
      O => \gen_pat_match_div4.idel_pat0_match_rise3_and_r_i_1_n_0\
    );
\gen_pat_match_div4.idel_pat0_match_rise3_and_r_reg\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_pat_match_div4.idel_pat0_match_rise3_and_r_i_1_n_0\,
      Q => idel_pat0_match_rise3_and_r,
      R => '0'
    );
\gen_pat_match_div4.idel_pat1_data_match_r_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00008000"
    )
        port map (
      I0 => idel_pat1_match_rise1_and_r,
      I1 => idel_pat1_match_fall1_and_r,
      I2 => idel_pat1_match_rise3_and_r,
      I3 => idel_pat1_match_fall0_and_r,
      I4 => \gen_pat_match_div4.idel_pat1_data_match_r_i_2_n_0\,
      O => idel_pat1_data_match_r0
    );
\gen_pat_match_div4.idel_pat1_data_match_r_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7FFF"
    )
        port map (
      I0 => idel_pat1_match_fall2_and_r,
      I1 => idel_pat1_match_rise2_and_r,
      I2 => idel_pat1_match_rise0_and_r,
      I3 => idel_pat1_match_fall3_and_r,
      O => \gen_pat_match_div4.idel_pat1_data_match_r_i_2_n_0\
    );
\gen_pat_match_div4.idel_pat1_data_match_r_reg\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => idel_pat1_data_match_r0,
      Q => \gen_pat_match_div4.idel_pat1_data_match_r_reg_n_0\,
      R => '0'
    );
\gen_pat_match_div4.idel_pat1_match_fall0_and_r_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"80"
    )
        port map (
      I0 => \gen_pat_match_div4.gen_pat_match[6].idel_pat1_match_fall0_r_reg\,
      I1 => \gen_pat_match_div4.idel_pat1_match_fall0_and_r_i_2_n_0\,
      I2 => pat0_match_fall0_r(7),
      O => \gen_pat_match_div4.idel_pat1_match_fall0_and_r_i_1_n_0\
    );
\gen_pat_match_div4.idel_pat1_match_fall0_and_r_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8000000000000000"
    )
        port map (
      I0 => \gen_pat_match_div4.gen_pat_match[5].idel_pat1_match_fall0_r_reg\,
      I1 => pat0_match_fall0_r(3),
      I2 => \gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_fall0_r_reg\,
      I3 => \gen_pat_match_div4.gen_pat_match[1].idel_pat1_match_fall0_r_reg\,
      I4 => \gen_pat_match_div4.gen_pat_match[2].idel_pat1_match_fall0_r_reg\,
      I5 => \gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_fall0_r_reg\,
      O => \gen_pat_match_div4.idel_pat1_match_fall0_and_r_i_2_n_0\
    );
\gen_pat_match_div4.idel_pat1_match_fall0_and_r_reg\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_pat_match_div4.idel_pat1_match_fall0_and_r_i_1_n_0\,
      Q => idel_pat1_match_fall0_and_r,
      R => '0'
    );
\gen_pat_match_div4.idel_pat1_match_fall1_and_r_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"80"
    )
        port map (
      I0 => \gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_fall1_r_reg\,
      I1 => \gen_pat_match_div4.idel_pat1_match_fall1_and_r_i_2_n_0\,
      I2 => \gen_pat_match_div4.gen_pat_match[7].idel_pat1_match_fall1_r_reg\,
      O => \gen_pat_match_div4.idel_pat1_match_fall1_and_r_i_1_n_0\
    );
\gen_pat_match_div4.idel_pat1_match_fall1_and_r_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8000000000000000"
    )
        port map (
      I0 => pat0_match_fall1_r(4),
      I1 => pat0_match_fall1_r(0),
      I2 => \gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_fall1_r_reg\,
      I3 => \gen_pat_match_div4.gen_pat_match[3].idel_pat1_match_fall1_r_reg\,
      I4 => \gen_pat_match_div4.gen_pat_match[1].idel_pat1_match_fall1_r_reg\,
      I5 => \gen_pat_match_div4.gen_pat_match[5].idel_pat1_match_fall1_r_reg\,
      O => \gen_pat_match_div4.idel_pat1_match_fall1_and_r_i_2_n_0\
    );
\gen_pat_match_div4.idel_pat1_match_fall1_and_r_reg\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_pat_match_div4.idel_pat1_match_fall1_and_r_i_1_n_0\,
      Q => idel_pat1_match_fall1_and_r,
      R => '0'
    );
\gen_pat_match_div4.idel_pat1_match_fall2_and_r_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"80000000"
    )
        port map (
      I0 => pat0_match_fall2_r(6),
      I1 => \gen_pat_match_div4.gen_pat_match[3].idel_pat1_match_fall2_r_reg\,
      I2 => \gen_pat_match_div4.pat0_match_fall2_and_r_i_2_n_0\,
      I3 => pat0_match_fall2_r(5),
      I4 => \gen_pat_match_div4.gen_pat_match[7].idel_pat1_match_fall2_r_reg\,
      O => \gen_pat_match_div4.idel_pat1_match_fall2_and_r_i_1_n_0\
    );
\gen_pat_match_div4.idel_pat1_match_fall2_and_r_reg\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_pat_match_div4.idel_pat1_match_fall2_and_r_i_1_n_0\,
      Q => idel_pat1_match_fall2_and_r,
      R => '0'
    );
\gen_pat_match_div4.idel_pat1_match_fall3_and_r_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"80000000"
    )
        port map (
      I0 => \gen_pat_match_div4.pat0_match_fall3_and_r_i_2_n_0\,
      I1 => \gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_fall3_r_reg\,
      I2 => \gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_fall3_r_reg\,
      I3 => \gen_pat_match_div4.gen_pat_match[4].idel_pat1_match_fall3_r_reg\,
      I4 => \gen_pat_match_div4.gen_pat_match[0].idel_pat1_match_fall3_r_reg\,
      O => \gen_pat_match_div4.idel_pat1_match_fall3_and_r_i_1_n_0\
    );
\gen_pat_match_div4.idel_pat1_match_fall3_and_r_reg\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_pat_match_div4.idel_pat1_match_fall3_and_r_i_1_n_0\,
      Q => idel_pat1_match_fall3_and_r,
      R => '0'
    );
\gen_pat_match_div4.idel_pat1_match_rise0_and_r_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"80000000"
    )
        port map (
      I0 => \gen_pat_match_div4.pat0_match_rise0_and_r_i_2_n_0\,
      I1 => \gen_pat_match_div4.gen_pat_match[4].idel_pat1_match_rise0_r_reg\,
      I2 => \gen_pat_match_div4.gen_pat_match[0].idel_pat1_match_rise0_r_reg\,
      I3 => \gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_rise0_r_reg\,
      I4 => \gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_rise0_r_reg\,
      O => \gen_pat_match_div4.idel_pat1_match_rise0_and_r_i_1_n_0\
    );
\gen_pat_match_div4.idel_pat1_match_rise0_and_r_reg\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_pat_match_div4.idel_pat1_match_rise0_and_r_i_1_n_0\,
      Q => idel_pat1_match_rise0_and_r,
      R => '0'
    );
\gen_pat_match_div4.idel_pat1_match_rise1_and_r_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"80000000"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_match_rise1_and_r_i_2_n_0\,
      I1 => idel_pat1_match_rise1_r(6),
      I2 => idel_pat1_match_rise1_r(2),
      I3 => idel_pat1_match_rise1_r(7),
      I4 => idel_pat1_match_rise1_r(3),
      O => \gen_pat_match_div4.idel_pat1_match_rise1_and_r_i_1_n_0\
    );
\gen_pat_match_div4.idel_pat1_match_rise1_and_r_reg\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_pat_match_div4.idel_pat1_match_rise1_and_r_i_1_n_0\,
      Q => idel_pat1_match_rise1_and_r,
      R => '0'
    );
\gen_pat_match_div4.idel_pat1_match_rise2_and_r_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8000000000000000"
    )
        port map (
      I0 => \gen_pat_match_div4.gen_pat_match[6].idel_pat1_match_rise2_r_reg\,
      I1 => pat0_match_rise2_r(4),
      I2 => \gen_pat_match_div4.pat1_match_rise2_and_r_i_2_n_0\,
      I3 => pat0_match_rise2_r(1),
      I4 => pat0_match_rise2_r(5),
      I5 => \gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_rise2_r_reg\,
      O => \gen_pat_match_div4.idel_pat1_match_rise2_and_r_i_1_n_0\
    );
\gen_pat_match_div4.idel_pat1_match_rise2_and_r_reg\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_pat_match_div4.idel_pat1_match_rise2_and_r_i_1_n_0\,
      Q => idel_pat1_match_rise2_and_r,
      R => '0'
    );
\gen_pat_match_div4.idel_pat1_match_rise3_and_r_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"80000000"
    )
        port map (
      I0 => \gen_pat_match_div4.pat0_match_rise3_and_r_i_2_n_0\,
      I1 => idel_pat0_match_rise3_r(5),
      I2 => idel_pat0_match_rise3_r(1),
      I3 => pat0_match_rise3_r(6),
      I4 => pat0_match_rise3_r(2),
      O => \gen_pat_match_div4.idel_pat1_match_rise3_and_r_i_1_n_0\
    );
\gen_pat_match_div4.idel_pat1_match_rise3_and_r_reg\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_pat_match_div4.idel_pat1_match_rise3_and_r_i_1_n_0\,
      Q => idel_pat1_match_rise3_and_r,
      R => '0'
    );
\gen_pat_match_div4.pat0_data_match_r_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00008000"
    )
        port map (
      I0 => pat0_match_rise1_and_r,
      I1 => pat0_match_fall2_and_r,
      I2 => pat0_match_rise3_and_r,
      I3 => pat0_match_fall0_and_r,
      I4 => \gen_pat_match_div4.pat0_data_match_r_i_2_n_0\,
      O => pat0_data_match_r0
    );
\gen_pat_match_div4.pat0_data_match_r_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7FFF"
    )
        port map (
      I0 => pat0_match_rise2_and_r,
      I1 => pat0_match_fall1_and_r,
      I2 => pat0_match_rise0_and_r,
      I3 => pat0_match_fall3_and_r,
      O => \gen_pat_match_div4.pat0_data_match_r_i_2_n_0\
    );
\gen_pat_match_div4.pat0_data_match_r_reg\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => pat0_data_match_r0,
      Q => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      R => '0'
    );
\gen_pat_match_div4.pat0_match_fall0_and_r_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"80"
    )
        port map (
      I0 => pat0_match_fall0_r(6),
      I1 => \gen_pat_match_div4.pat0_match_fall0_and_r_i_2_n_0\,
      I2 => pat0_match_fall0_r(7),
      O => \gen_pat_match_div4.pat0_match_fall0_and_r_i_1_n_0\
    );
\gen_pat_match_div4.pat0_match_fall0_and_r_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8000000000000000"
    )
        port map (
      I0 => pat0_match_fall0_r(4),
      I1 => pat0_match_fall0_r(2),
      I2 => pat0_match_fall0_r(0),
      I3 => pat0_match_fall0_r(1),
      I4 => pat0_match_fall0_r(3),
      I5 => pat0_match_fall0_r(5),
      O => \gen_pat_match_div4.pat0_match_fall0_and_r_i_2_n_0\
    );
\gen_pat_match_div4.pat0_match_fall0_and_r_reg\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_pat_match_div4.pat0_match_fall0_and_r_i_1_n_0\,
      Q => pat0_match_fall0_and_r,
      R => '0'
    );
\gen_pat_match_div4.pat0_match_fall1_and_r_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"80"
    )
        port map (
      I0 => pat0_match_fall1_r(6),
      I1 => \gen_pat_match_div4.pat0_match_fall1_and_r_i_2_n_0\,
      I2 => pat0_match_fall1_r(7),
      O => \gen_pat_match_div4.pat0_match_fall1_and_r_i_1_n_0\
    );
\gen_pat_match_div4.pat0_match_fall1_and_r_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8000000000000000"
    )
        port map (
      I0 => pat0_match_fall1_r(4),
      I1 => pat0_match_fall1_r(1),
      I2 => pat0_match_fall1_r(3),
      I3 => pat0_match_fall1_r(2),
      I4 => pat0_match_fall1_r(0),
      I5 => pat0_match_fall1_r(5),
      O => \gen_pat_match_div4.pat0_match_fall1_and_r_i_2_n_0\
    );
\gen_pat_match_div4.pat0_match_fall1_and_r_reg\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_pat_match_div4.pat0_match_fall1_and_r_i_1_n_0\,
      Q => pat0_match_fall1_and_r,
      R => '0'
    );
\gen_pat_match_div4.pat0_match_fall2_and_r_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"80000000"
    )
        port map (
      I0 => pat0_match_fall2_r(7),
      I1 => pat0_match_fall2_r(5),
      I2 => \gen_pat_match_div4.pat0_match_fall2_and_r_i_2_n_0\,
      I3 => pat0_match_fall2_r(6),
      I4 => pat0_match_fall2_r(3),
      O => \gen_pat_match_div4.pat0_match_fall2_and_r_i_1_n_0\
    );
\gen_pat_match_div4.pat0_match_fall2_and_r_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8000"
    )
        port map (
      I0 => pat0_match_fall2_r(2),
      I1 => pat0_match_fall2_r(1),
      I2 => pat0_match_fall2_r(0),
      I3 => pat0_match_fall2_r(4),
      O => \gen_pat_match_div4.pat0_match_fall2_and_r_i_2_n_0\
    );
\gen_pat_match_div4.pat0_match_fall2_and_r_reg\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_pat_match_div4.pat0_match_fall2_and_r_i_1_n_0\,
      Q => pat0_match_fall2_and_r,
      R => '0'
    );
\gen_pat_match_div4.pat0_match_fall3_and_r_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"80000000"
    )
        port map (
      I0 => \gen_pat_match_div4.pat0_match_fall3_and_r_i_2_n_0\,
      I1 => pat0_match_fall3_r(4),
      I2 => pat0_match_fall3_r(1),
      I3 => pat0_match_fall3_r(5),
      I4 => pat0_match_fall3_r(0),
      O => \gen_pat_match_div4.pat0_match_fall3_and_r_i_1_n_0\
    );
\gen_pat_match_div4.pat0_match_fall3_and_r_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8000"
    )
        port map (
      I0 => pat0_match_fall3_r(2),
      I1 => pat0_match_fall3_r(7),
      I2 => pat0_match_fall3_r(3),
      I3 => pat0_match_fall3_r(6),
      O => \gen_pat_match_div4.pat0_match_fall3_and_r_i_2_n_0\
    );
\gen_pat_match_div4.pat0_match_fall3_and_r_reg\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_pat_match_div4.pat0_match_fall3_and_r_i_1_n_0\,
      Q => pat0_match_fall3_and_r,
      R => '0'
    );
\gen_pat_match_div4.pat0_match_rise0_and_r_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"80000000"
    )
        port map (
      I0 => \gen_pat_match_div4.pat0_match_rise0_and_r_i_2_n_0\,
      I1 => pat0_match_rise0_r(5),
      I2 => pat0_match_rise0_r(1),
      I3 => pat0_match_rise0_r(4),
      I4 => pat0_match_rise0_r(0),
      O => \gen_pat_match_div4.pat0_match_rise0_and_r_i_1_n_0\
    );
\gen_pat_match_div4.pat0_match_rise0_and_r_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8000"
    )
        port map (
      I0 => pat0_match_rise0_r(2),
      I1 => pat0_match_rise0_r(6),
      I2 => pat0_match_rise0_r(3),
      I3 => pat0_match_rise0_r(7),
      O => \gen_pat_match_div4.pat0_match_rise0_and_r_i_2_n_0\
    );
\gen_pat_match_div4.pat0_match_rise0_and_r_reg\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_pat_match_div4.pat0_match_rise0_and_r_i_1_n_0\,
      Q => pat0_match_rise0_and_r,
      R => '0'
    );
\gen_pat_match_div4.pat0_match_rise1_and_r_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"80000000"
    )
        port map (
      I0 => \gen_pat_match_div4.pat0_match_rise1_and_r_i_2_n_0\,
      I1 => pat0_match_rise1_r(5),
      I2 => pat0_match_rise1_r(1),
      I3 => pat0_match_rise1_r(4),
      I4 => pat0_match_rise1_r(0),
      O => \gen_pat_match_div4.pat0_match_rise1_and_r_i_1_n_0\
    );
\gen_pat_match_div4.pat0_match_rise1_and_r_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8000"
    )
        port map (
      I0 => pat0_match_rise1_r(3),
      I1 => pat0_match_rise1_r(7),
      I2 => pat0_match_rise1_r(2),
      I3 => pat0_match_rise1_r(6),
      O => \gen_pat_match_div4.pat0_match_rise1_and_r_i_2_n_0\
    );
\gen_pat_match_div4.pat0_match_rise1_and_r_reg\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_pat_match_div4.pat0_match_rise1_and_r_i_1_n_0\,
      Q => pat0_match_rise1_and_r,
      R => '0'
    );
\gen_pat_match_div4.pat0_match_rise2_and_r_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"80"
    )
        port map (
      I0 => pat0_match_rise2_r(7),
      I1 => \gen_pat_match_div4.pat0_match_rise2_and_r_i_2_n_0\,
      I2 => pat0_match_rise2_r(6),
      O => \gen_pat_match_div4.pat0_match_rise2_and_r_i_1_n_0\
    );
\gen_pat_match_div4.pat0_match_rise2_and_r_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8000000000000000"
    )
        port map (
      I0 => pat0_match_rise2_r(4),
      I1 => pat0_match_rise2_r(2),
      I2 => pat0_match_rise2_r(0),
      I3 => pat0_match_rise2_r(1),
      I4 => pat0_match_rise2_r(3),
      I5 => pat0_match_rise2_r(5),
      O => \gen_pat_match_div4.pat0_match_rise2_and_r_i_2_n_0\
    );
\gen_pat_match_div4.pat0_match_rise2_and_r_reg\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_pat_match_div4.pat0_match_rise2_and_r_i_1_n_0\,
      Q => pat0_match_rise2_and_r,
      R => '0'
    );
\gen_pat_match_div4.pat0_match_rise3_and_r_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"80000000"
    )
        port map (
      I0 => pat0_match_rise3_r(6),
      I1 => pat0_match_rise3_r(2),
      I2 => pat0_match_rise3_r(5),
      I3 => pat0_match_rise3_r(1),
      I4 => \gen_pat_match_div4.pat0_match_rise3_and_r_i_2_n_0\,
      O => \gen_pat_match_div4.pat0_match_rise3_and_r_i_1_n_0\
    );
\gen_pat_match_div4.pat0_match_rise3_and_r_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8000"
    )
        port map (
      I0 => pat0_match_rise3_r(3),
      I1 => pat0_match_rise3_r(7),
      I2 => pat0_match_rise3_r(0),
      I3 => pat0_match_rise3_r(4),
      O => \gen_pat_match_div4.pat0_match_rise3_and_r_i_2_n_0\
    );
\gen_pat_match_div4.pat0_match_rise3_and_r_reg\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_pat_match_div4.pat0_match_rise3_and_r_i_1_n_0\,
      Q => pat0_match_rise3_and_r,
      R => '0'
    );
\gen_pat_match_div4.pat1_data_match_r_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00008000"
    )
        port map (
      I0 => pat1_match_fall0_and_r,
      I1 => pat1_match_rise1_and_r,
      I2 => pat1_match_rise3_and_r,
      I3 => pat1_match_fall2_and_r,
      I4 => \gen_pat_match_div4.pat1_data_match_r_i_2_n_0\,
      O => pat1_data_match_r0
    );
\gen_pat_match_div4.pat1_data_match_r_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7FFF"
    )
        port map (
      I0 => pat1_match_rise2_and_r,
      I1 => pat1_match_fall1_and_r,
      I2 => pat1_match_rise0_and_r,
      I3 => pat1_match_fall3_and_r,
      O => \gen_pat_match_div4.pat1_data_match_r_i_2_n_0\
    );
\gen_pat_match_div4.pat1_data_match_r_reg\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => pat1_data_match_r0,
      Q => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      R => '0'
    );
\gen_pat_match_div4.pat1_match_fall0_and_r_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8000000000000000"
    )
        port map (
      I0 => \gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_fall0_r_reg\,
      I1 => \gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_fall0_r_reg\,
      I2 => \gen_pat_match_div4.pat1_match_fall0_and_r_i_2_n_0\,
      I3 => \gen_pat_match_div4.gen_pat_match[2].idel_pat1_match_fall0_r_reg\,
      I4 => pat0_match_fall0_r(5),
      I5 => \gen_pat_match_div4.gen_pat_match[6].idel_pat1_match_fall0_r_reg\,
      O => \gen_pat_match_div4.pat1_match_fall0_and_r_i_1_n_0\
    );
\gen_pat_match_div4.pat1_match_fall0_and_r_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"80"
    )
        port map (
      I0 => \gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_fall0_r_reg\,
      I1 => pat0_match_fall0_r(1),
      I2 => \gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_fall0_r_reg\,
      O => \gen_pat_match_div4.pat1_match_fall0_and_r_i_2_n_0\
    );
\gen_pat_match_div4.pat1_match_fall0_and_r_reg\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_pat_match_div4.pat1_match_fall0_and_r_i_1_n_0\,
      Q => pat1_match_fall0_and_r,
      R => '0'
    );
\gen_pat_match_div4.pat1_match_fall1_and_r_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8000000000000000"
    )
        port map (
      I0 => \gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_fall1_r_reg\,
      I1 => \gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_fall1_r_reg\,
      I2 => \gen_pat_match_div4.pat1_match_fall1_and_r_i_2_n_0\,
      I3 => \gen_pat_match_div4.gen_pat_match[1].idel_pat1_match_fall1_r_reg\,
      I4 => \gen_pat_match_div4.gen_pat_match[5].idel_pat1_match_fall1_r_reg\,
      I5 => pat0_match_fall1_r(7),
      O => \gen_pat_match_div4.pat1_match_fall1_and_r_i_1_n_0\
    );
\gen_pat_match_div4.pat1_match_fall1_and_r_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"80"
    )
        port map (
      I0 => pat0_match_fall1_r(3),
      I1 => \gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_fall1_r_reg\,
      I2 => \gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_fall1_r_reg\,
      O => \gen_pat_match_div4.pat1_match_fall1_and_r_i_2_n_0\
    );
\gen_pat_match_div4.pat1_match_fall1_and_r_reg\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_pat_match_div4.pat1_match_fall1_and_r_i_1_n_0\,
      Q => pat1_match_fall1_and_r,
      R => '0'
    );
\gen_pat_match_div4.pat1_match_fall2_and_r_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"80"
    )
        port map (
      I0 => \gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_fall2_r_reg\,
      I1 => \gen_pat_match_div4.pat1_match_fall2_and_r_i_2_n_0\,
      I2 => \gen_pat_match_div4.gen_pat_match[7].idel_pat1_match_fall2_r_reg\,
      O => \gen_pat_match_div4.pat1_match_fall2_and_r_i_1_n_0\
    );
\gen_pat_match_div4.pat1_match_fall2_and_r_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8000000000000000"
    )
        port map (
      I0 => \gen_pat_match_div4.gen_pat_match[4].pat1_match_fall2_r_reg\,
      I1 => \gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_fall2_r_reg\,
      I2 => pat0_match_fall2_r(1),
      I3 => \gen_pat_match_div4.gen_pat_match[0].pat1_match_fall2_r_reg\,
      I4 => \gen_pat_match_div4.gen_pat_match[3].idel_pat1_match_fall2_r_reg\,
      I5 => pat0_match_fall2_r(5),
      O => \gen_pat_match_div4.pat1_match_fall2_and_r_i_2_n_0\
    );
\gen_pat_match_div4.pat1_match_fall2_and_r_reg\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_pat_match_div4.pat1_match_fall2_and_r_i_1_n_0\,
      Q => pat1_match_fall2_and_r,
      R => '0'
    );
\gen_pat_match_div4.pat1_match_fall3_and_r_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00008000"
    )
        port map (
      I0 => \gen_pat_match_div4.gen_pat_match[6].pat1_match_fall3_r_reg\,
      I1 => \gen_pat_match_div4.gen_pat_match[4].idel_pat1_match_fall3_r_reg\,
      I2 => pat0_match_fall3_r(7),
      I3 => pat0_match_fall3_r(5),
      I4 => \gen_pat_match_div4.pat1_match_fall3_and_r_i_2_n_0\,
      O => \gen_pat_match_div4.pat1_match_fall3_and_r_i_1_n_0\
    );
\gen_pat_match_div4.pat1_match_fall3_and_r_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7FFF"
    )
        port map (
      I0 => pat0_match_fall3_r(1),
      I1 => pat0_match_fall3_r(3),
      I2 => \gen_pat_match_div4.gen_pat_match[0].idel_pat1_match_fall3_r_reg\,
      I3 => \gen_pat_match_div4.gen_pat_match[2].pat1_match_fall3_r_reg\,
      O => \gen_pat_match_div4.pat1_match_fall3_and_r_i_2_n_0\
    );
\gen_pat_match_div4.pat1_match_fall3_and_r_reg\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_pat_match_div4.pat1_match_fall3_and_r_i_1_n_0\,
      Q => pat1_match_fall3_and_r,
      R => '0'
    );
\gen_pat_match_div4.pat1_match_rise0_and_r_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"80000000"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_match_rise0_and_r_i_2_n_0\,
      I1 => \gen_pat_match_div4.gen_pat_match[7].pat1_match_rise0_r_reg\,
      I2 => \gen_pat_match_div4.gen_pat_match[3].pat1_match_rise0_r_reg\,
      I3 => \gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_rise0_r_reg\,
      I4 => \gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_rise0_r_reg\,
      O => \gen_pat_match_div4.pat1_match_rise0_and_r_i_1_n_0\
    );
\gen_pat_match_div4.pat1_match_rise0_and_r_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8000"
    )
        port map (
      I0 => pat0_match_rise0_r(0),
      I1 => pat0_match_rise0_r(4),
      I2 => \gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_rise0_r_reg\,
      I3 => \gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_rise0_r_reg\,
      O => \gen_pat_match_div4.pat1_match_rise0_and_r_i_2_n_0\
    );
\gen_pat_match_div4.pat1_match_rise0_and_r_reg\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_pat_match_div4.pat1_match_rise0_and_r_i_1_n_0\,
      Q => pat1_match_rise0_and_r,
      R => '0'
    );
\gen_pat_match_div4.pat1_match_rise1_and_r_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"80000000"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_match_rise1_and_r_i_2_n_0\,
      I1 => idel_pat1_match_rise1_r(7),
      I2 => idel_pat1_match_rise1_r(3),
      I3 => pat0_match_rise1_r(6),
      I4 => pat0_match_rise1_r(2),
      O => \gen_pat_match_div4.pat1_match_rise1_and_r_i_1_n_0\
    );
\gen_pat_match_div4.pat1_match_rise1_and_r_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8000"
    )
        port map (
      I0 => idel_pat1_match_rise1_r(0),
      I1 => idel_pat1_match_rise1_r(4),
      I2 => idel_pat1_match_rise1_r(1),
      I3 => idel_pat1_match_rise1_r(5),
      O => \gen_pat_match_div4.pat1_match_rise1_and_r_i_2_n_0\
    );
\gen_pat_match_div4.pat1_match_rise1_and_r_reg\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_pat_match_div4.pat1_match_rise1_and_r_i_1_n_0\,
      Q => pat1_match_rise1_and_r,
      R => '0'
    );
\gen_pat_match_div4.pat1_match_rise2_and_r_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8000000000000000"
    )
        port map (
      I0 => \gen_pat_match_div4.gen_pat_match[6].idel_pat1_match_rise2_r_reg\,
      I1 => pat0_match_rise2_r(4),
      I2 => \gen_pat_match_div4.pat1_match_rise2_and_r_i_2_n_0\,
      I3 => \gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_rise2_r_reg\,
      I4 => \gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_rise2_r_reg\,
      I5 => \gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_rise2_r_reg\,
      O => \gen_pat_match_div4.pat1_match_rise2_and_r_i_1_n_0\
    );
\gen_pat_match_div4.pat1_match_rise2_and_r_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"80"
    )
        port map (
      I0 => \gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_rise2_r_reg\,
      I1 => \gen_pat_match_div4.gen_pat_match[2].idel_pat1_match_rise2_r_reg\,
      I2 => pat0_match_rise2_r(0),
      O => \gen_pat_match_div4.pat1_match_rise2_and_r_i_2_n_0\
    );
\gen_pat_match_div4.pat1_match_rise2_and_r_reg\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_pat_match_div4.pat1_match_rise2_and_r_i_1_n_0\,
      Q => pat1_match_rise2_and_r,
      R => '0'
    );
\gen_pat_match_div4.pat1_match_rise3_and_r_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"80000000"
    )
        port map (
      I0 => pat0_match_rise3_r(6),
      I1 => pat0_match_rise3_r(2),
      I2 => pat0_match_rise3_r(5),
      I3 => pat0_match_rise3_r(1),
      I4 => \gen_pat_match_div4.pat1_match_rise3_and_r_i_2_n_0\,
      O => \gen_pat_match_div4.pat1_match_rise3_and_r_i_1_n_0\
    );
\gen_pat_match_div4.pat1_match_rise3_and_r_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8000"
    )
        port map (
      I0 => idel_pat0_match_rise3_r(4),
      I1 => idel_pat0_match_rise3_r(7),
      I2 => idel_pat0_match_rise3_r(0),
      I3 => idel_pat0_match_rise3_r(3),
      O => \gen_pat_match_div4.pat1_match_rise3_and_r_i_2_n_0\
    );
\gen_pat_match_div4.pat1_match_rise3_and_r_reg\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_pat_match_div4.pat1_match_rise3_and_r_i_1_n_0\,
      Q => pat1_match_rise3_and_r,
      R => '0'
    );
\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall0_r_reg[0][0]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => E(0),
      D => \gen_mux_rd[0].mux_rd_fall0_r_reg_n_0_[0]\,
      Q => \gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall0_r_reg[0]_95\,
      R => '0'
    );
\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall1_r_reg[0][0]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => E(0),
      D => \gen_mux_rd[0].mux_rd_fall1_r_reg_n_0_[0]\,
      Q => \gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall1_r_reg[0]_71\,
      R => '0'
    );
\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall2_r_reg[0][0]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => E(0),
      D => \gen_mux_rd[0].mux_rd_fall2_r_reg_n_0_[0]\,
      Q => \gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall2_r_reg[0]_79\,
      R => '0'
    );
\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall3_r_reg[0][0]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => E(0),
      D => \gen_mux_rd[0].mux_rd_fall3_r_reg_n_0_[0]\,
      Q => \gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall3_r_reg[0]_55\,
      R => '0'
    );
\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise0_r_reg[0][0]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => E(0),
      D => \gen_mux_rd[0].mux_rd_rise0_r_reg_n_0_[0]\,
      Q => \gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise0_r_reg[0]_47\,
      R => '0'
    );
\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise1_r_reg[0][0]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => E(0),
      D => \gen_mux_rd[0].mux_rd_rise1_r_reg_n_0_[0]\,
      Q => \gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise1_r_reg[0]_87\,
      R => '0'
    );
\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise2_r_reg[0][0]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => E(0),
      D => \gen_mux_rd[0].mux_rd_rise2_r_reg_n_0_[0]\,
      Q => \gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise2_r_reg[0]_63\,
      R => '0'
    );
\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise3_r_reg[0][0]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => E(0),
      D => \gen_mux_rd[0].mux_rd_rise3_r_reg_n_0_[0]\,
      Q => \gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise3_r_reg[0]_103\,
      R => '0'
    );
\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall0_r_reg[1][0]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => E(0),
      D => \gen_mux_rd[1].mux_rd_fall0_r_reg_n_0_[1]\,
      Q => \gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall0_r_reg[1]_96\,
      R => '0'
    );
\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall1_r_reg[1][0]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => E(0),
      D => \gen_mux_rd[1].mux_rd_fall1_r_reg_n_0_[1]\,
      Q => \gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall1_r_reg[1]_72\,
      R => '0'
    );
\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall2_r_reg[1][0]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => E(0),
      D => \gen_mux_rd[1].mux_rd_fall2_r_reg_n_0_[1]\,
      Q => \gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall2_r_reg[1]_80\,
      R => '0'
    );
\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall3_r_reg[1][0]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => E(0),
      D => \gen_mux_rd[1].mux_rd_fall3_r_reg_n_0_[1]\,
      Q => \gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall3_r_reg[1]_56\,
      R => '0'
    );
\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise0_r_reg[1][0]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => E(0),
      D => \gen_mux_rd[1].mux_rd_rise0_r_reg_n_0_[1]\,
      Q => \gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise0_r_reg[1]_48\,
      R => '0'
    );
\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise1_r_reg[1][0]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => E(0),
      D => \gen_mux_rd[1].mux_rd_rise1_r_reg_n_0_[1]\,
      Q => \gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise1_r_reg[1]_88\,
      R => '0'
    );
\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise2_r_reg[1][0]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => E(0),
      D => \gen_mux_rd[1].mux_rd_rise2_r_reg_n_0_[1]\,
      Q => \gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise2_r_reg[1]_64\,
      R => '0'
    );
\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise3_r_reg[1][0]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => E(0),
      D => \gen_mux_rd[1].mux_rd_rise3_r_reg_n_0_[1]\,
      Q => \gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise3_r_reg[1]_104\,
      R => '0'
    );
\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall0_r_reg[2][0]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => E(0),
      D => \gen_mux_rd[2].mux_rd_fall0_r_reg_n_0_[2]\,
      Q => \gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall0_r_reg[2]_97\,
      R => '0'
    );
\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall1_r_reg[2][0]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => E(0),
      D => \gen_mux_rd[2].mux_rd_fall1_r_reg_n_0_[2]\,
      Q => \gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall1_r_reg[2]_73\,
      R => '0'
    );
\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall2_r_reg[2][0]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => E(0),
      D => \gen_mux_rd[2].mux_rd_fall2_r_reg_n_0_[2]\,
      Q => \gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall2_r_reg[2]_81\,
      R => '0'
    );
\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall3_r_reg[2][0]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => E(0),
      D => \gen_mux_rd[2].mux_rd_fall3_r_reg_n_0_[2]\,
      Q => \gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall3_r_reg[2]_57\,
      R => '0'
    );
\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise0_r_reg[2][0]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => E(0),
      D => \gen_mux_rd[2].mux_rd_rise0_r_reg_n_0_[2]\,
      Q => \gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise0_r_reg[2]_49\,
      R => '0'
    );
\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise1_r_reg[2][0]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => E(0),
      D => \gen_mux_rd[2].mux_rd_rise1_r_reg_n_0_[2]\,
      Q => \gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise1_r_reg[2]_89\,
      R => '0'
    );
\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise2_r_reg[2][0]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => E(0),
      D => \gen_mux_rd[2].mux_rd_rise2_r_reg_n_0_[2]\,
      Q => \gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise2_r_reg[2]_65\,
      R => '0'
    );
\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise3_r_reg[2][0]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => E(0),
      D => \gen_mux_rd[2].mux_rd_rise3_r_reg_n_0_[2]\,
      Q => \gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise3_r_reg[2]_105\,
      R => '0'
    );
\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall0_r_reg[3][0]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => E(0),
      D => \gen_mux_rd[3].mux_rd_fall0_r_reg_n_0_[3]\,
      Q => \gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall0_r_reg[3]_98\,
      R => '0'
    );
\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall1_r_reg[3][0]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => E(0),
      D => \gen_mux_rd[3].mux_rd_fall1_r_reg_n_0_[3]\,
      Q => \gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall1_r_reg[3]_74\,
      R => '0'
    );
\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall2_r_reg[3][0]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => E(0),
      D => \gen_mux_rd[3].mux_rd_fall2_r_reg_n_0_[3]\,
      Q => \gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall2_r_reg[3]_82\,
      R => '0'
    );
\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall3_r_reg[3][0]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => E(0),
      D => \gen_mux_rd[3].mux_rd_fall3_r_reg_n_0_[3]\,
      Q => \gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall3_r_reg[3]_58\,
      R => '0'
    );
\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise0_r_reg[3][0]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => E(0),
      D => \gen_mux_rd[3].mux_rd_rise0_r_reg_n_0_[3]\,
      Q => \gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise0_r_reg[3]_50\,
      R => '0'
    );
\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise1_r_reg[3][0]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => E(0),
      D => \gen_mux_rd[3].mux_rd_rise1_r_reg_n_0_[3]\,
      Q => \gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise1_r_reg[3]_90\,
      R => '0'
    );
\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise2_r_reg[3][0]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => E(0),
      D => \gen_mux_rd[3].mux_rd_rise2_r_reg_n_0_[3]\,
      Q => \gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise2_r_reg[3]_66\,
      R => '0'
    );
\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise3_r_reg[3][0]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => E(0),
      D => \gen_mux_rd[3].mux_rd_rise3_r_reg_n_0_[3]\,
      Q => \gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise3_r_reg[3]_106\,
      R => '0'
    );
\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall0_r_reg[4][0]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => E(0),
      D => \gen_mux_rd[4].mux_rd_fall0_r_reg_n_0_[4]\,
      Q => \gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall0_r_reg[4]_99\,
      R => '0'
    );
\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall1_r_reg[4][0]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => E(0),
      D => \gen_mux_rd[4].mux_rd_fall1_r_reg_n_0_[4]\,
      Q => \gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall1_r_reg[4]_75\,
      R => '0'
    );
\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall2_r_reg[4][0]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => E(0),
      D => \gen_mux_rd[4].mux_rd_fall2_r_reg_n_0_[4]\,
      Q => \gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall2_r_reg[4]_83\,
      R => '0'
    );
\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall3_r_reg[4][0]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => E(0),
      D => \gen_mux_rd[4].mux_rd_fall3_r_reg_n_0_[4]\,
      Q => \gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall3_r_reg[4]_59\,
      R => '0'
    );
\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise0_r_reg[4][0]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => E(0),
      D => \gen_mux_rd[4].mux_rd_rise0_r_reg_n_0_[4]\,
      Q => \gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise0_r_reg[4]_51\,
      R => '0'
    );
\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise1_r_reg[4][0]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => E(0),
      D => \gen_mux_rd[4].mux_rd_rise1_r_reg_n_0_[4]\,
      Q => \gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise1_r_reg[4]_91\,
      R => '0'
    );
\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise2_r_reg[4][0]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => E(0),
      D => \gen_mux_rd[4].mux_rd_rise2_r_reg_n_0_[4]\,
      Q => \gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise2_r_reg[4]_67\,
      R => '0'
    );
\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise3_r_reg[4][0]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => E(0),
      D => \gen_mux_rd[4].mux_rd_rise3_r_reg_n_0_[4]\,
      Q => \gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise3_r_reg[4]_107\,
      R => '0'
    );
\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall0_r_reg[5][0]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => E(0),
      D => \gen_mux_rd[5].mux_rd_fall0_r_reg_n_0_[5]\,
      Q => \gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall0_r_reg[5]_100\,
      R => '0'
    );
\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall1_r_reg[5][0]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => E(0),
      D => \gen_mux_rd[5].mux_rd_fall1_r_reg_n_0_[5]\,
      Q => \gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall1_r_reg[5]_76\,
      R => '0'
    );
\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall2_r_reg[5][0]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => E(0),
      D => \gen_mux_rd[5].mux_rd_fall2_r_reg_n_0_[5]\,
      Q => \gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall2_r_reg[5]_84\,
      R => '0'
    );
\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall3_r_reg[5][0]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => E(0),
      D => \gen_mux_rd[5].mux_rd_fall3_r_reg_n_0_[5]\,
      Q => \gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall3_r_reg[5]_60\,
      R => '0'
    );
\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise0_r_reg[5][0]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => E(0),
      D => \gen_mux_rd[5].mux_rd_rise0_r_reg_n_0_[5]\,
      Q => \gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise0_r_reg[5]_52\,
      R => '0'
    );
\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise1_r_reg[5][0]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => E(0),
      D => \gen_mux_rd[5].mux_rd_rise1_r_reg_n_0_[5]\,
      Q => \gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise1_r_reg[5]_92\,
      R => '0'
    );
\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise2_r_reg[5][0]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => E(0),
      D => \gen_mux_rd[5].mux_rd_rise2_r_reg_n_0_[5]\,
      Q => \gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise2_r_reg[5]_68\,
      R => '0'
    );
\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise3_r_reg[5][0]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => E(0),
      D => \gen_mux_rd[5].mux_rd_rise3_r_reg_n_0_[5]\,
      Q => \gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise3_r_reg[5]_108\,
      R => '0'
    );
\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall0_r_reg[6][0]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => E(0),
      D => \gen_mux_rd[6].mux_rd_fall0_r_reg_n_0_[6]\,
      Q => \gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall0_r_reg[6]_101\,
      R => '0'
    );
\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall1_r_reg[6][0]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => E(0),
      D => \gen_mux_rd[6].mux_rd_fall1_r_reg_n_0_[6]\,
      Q => \gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall1_r_reg[6]_77\,
      R => '0'
    );
\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall2_r_reg[6][0]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => E(0),
      D => \gen_mux_rd[6].mux_rd_fall2_r_reg_n_0_[6]\,
      Q => \gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall2_r_reg[6]_85\,
      R => '0'
    );
\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall3_r_reg[6][0]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => E(0),
      D => \gen_mux_rd[6].mux_rd_fall3_r_reg_n_0_[6]\,
      Q => \gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall3_r_reg[6]_61\,
      R => '0'
    );
\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise0_r_reg[6][0]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => E(0),
      D => \gen_mux_rd[6].mux_rd_rise0_r_reg_n_0_[6]\,
      Q => \gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise0_r_reg[6]_53\,
      R => '0'
    );
\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise1_r_reg[6][0]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => E(0),
      D => \gen_mux_rd[6].mux_rd_rise1_r_reg_n_0_[6]\,
      Q => \gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise1_r_reg[6]_93\,
      R => '0'
    );
\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise2_r_reg[6][0]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => E(0),
      D => \gen_mux_rd[6].mux_rd_rise2_r_reg_n_0_[6]\,
      Q => \gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise2_r_reg[6]_69\,
      R => '0'
    );
\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise3_r_reg[6][0]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => E(0),
      D => \gen_mux_rd[6].mux_rd_rise3_r_reg_n_0_[6]\,
      Q => \gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise3_r_reg[6]_109\,
      R => '0'
    );
\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall0_r_reg[7][0]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => E(0),
      D => \gen_mux_rd[7].mux_rd_fall0_r_reg_n_0_[7]\,
      Q => \gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall0_r_reg[7]_102\,
      R => '0'
    );
\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall1_r_reg[7][0]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => E(0),
      D => \gen_mux_rd[7].mux_rd_fall1_r_reg_n_0_[7]\,
      Q => \gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall1_r_reg[7]_78\,
      R => '0'
    );
\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall2_r_reg[7][0]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => E(0),
      D => \gen_mux_rd[7].mux_rd_fall2_r_reg_n_0_[7]\,
      Q => \gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall2_r_reg[7]_86\,
      R => '0'
    );
\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall3_r_reg[7][0]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => E(0),
      D => \gen_mux_rd[7].mux_rd_fall3_r_reg_n_0_[7]\,
      Q => \gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall3_r_reg[7]_62\,
      R => '0'
    );
\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise0_r_reg[7][0]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => E(0),
      D => \gen_mux_rd[7].mux_rd_rise0_r_reg_n_0_[7]\,
      Q => \gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise0_r_reg[7]_54\,
      R => '0'
    );
\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise1_r_reg[7][0]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => E(0),
      D => \gen_mux_rd[7].mux_rd_rise1_r_reg_n_0_[7]\,
      Q => \gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise1_r_reg[7]_94\,
      R => '0'
    );
\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise2_r_reg[7][0]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => E(0),
      D => \gen_mux_rd[7].mux_rd_rise2_r_reg_n_0_[7]\,
      Q => \gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise2_r_reg[7]_70\,
      R => '0'
    );
\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise3_r_reg[7][0]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => E(0),
      D => \gen_mux_rd[7].mux_rd_rise3_r_reg_n_0_[7]\,
      Q => \gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise3_r_reg[7]_110\,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[0].old_sr_diff_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[0].old_sr_match_cyc2_r_reg[0]_inv_n_0\,
      Q => \gen_sr_match_div4.gen_sr_match[0].old_sr_diff_r_reg_n_0_[0]\,
      R => \gen_sr_match_div4.gen_sr_match[0].prev_sr_diff_r[0]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[0].old_sr_match_cyc2_r[0]_inv_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFF7FFF"
    )
        port map (
      I0 => \gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise2_r_reg_n_0_[0]\,
      I1 => \gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall1_r_reg_n_0_[0]\,
      I2 => \gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise3_r_reg_n_0_[0]\,
      I3 => \gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise0_r_reg_n_0_[0]\,
      I4 => \gen_sr_match_div4.gen_sr_match[0].old_sr_match_cyc2_r[0]_inv_i_2_n_0\,
      O => p_490_out
    );
\gen_sr_match_div4.gen_sr_match[0].old_sr_match_cyc2_r[0]_inv_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7FFF"
    )
        port map (
      I0 => \gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall0_r_reg_n_0_[0]\,
      I1 => \gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise1_r_reg_n_0_[0]\,
      I2 => \gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall2_r_reg_n_0_[0]\,
      I3 => \gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall3_r_reg_n_0_[0]\,
      O => \gen_sr_match_div4.gen_sr_match[0].old_sr_match_cyc2_r[0]_inv_i_2_n_0\
    );
\gen_sr_match_div4.gen_sr_match[0].old_sr_match_cyc2_r_reg[0]_inv\: unisim.vcomponents.FDRE
    generic map(
      INIT => '1'
    )
        port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => p_490_out,
      Q => \gen_sr_match_div4.gen_sr_match[0].old_sr_match_cyc2_r_reg[0]_inv_n_0\,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall0_r[0]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall0_r_reg[0]_95\,
      I3 => \gen_old_sr_div4.gen_old_sr[0].old_sr_fall0_r_reg[0]_191\,
      O => \gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall0_r[0]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall0_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall0_r[0]_i_1_n_0\,
      Q => \gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall0_r_reg_n_0_[0]\,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall1_r[0]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall1_r_reg[0]_71\,
      I3 => \gen_old_sr_div4.gen_old_sr[0].old_sr_fall1_r_reg[0]_207\,
      O => \gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall1_r[0]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall1_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall1_r[0]_i_1_n_0\,
      Q => \gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall1_r_reg_n_0_[0]\,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall2_r[0]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall2_r_reg[0]_79\,
      I3 => \gen_old_sr_div4.gen_old_sr[0].old_sr_fall2_r_reg[0]_175\,
      O => \gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall2_r[0]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall2_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall2_r[0]_i_1_n_0\,
      Q => \gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall2_r_reg_n_0_[0]\,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall3_r[0]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall3_r_reg[0]_55\,
      I3 => \gen_old_sr_div4.gen_old_sr[0].old_sr_fall3_r_reg[0]_183\,
      O => \gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall3_r[0]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall3_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall3_r[0]_i_1_n_0\,
      Q => \gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall3_r_reg_n_0_[0]\,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise0_r[0]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise0_r_reg[0]_47\,
      I3 => \gen_old_sr_div4.gen_old_sr[0].old_sr_rise0_r_reg[0]_223\,
      O => \gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise0_r[0]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise0_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise0_r[0]_i_1_n_0\,
      Q => \gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise0_r_reg_n_0_[0]\,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise1_r[0]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise1_r_reg[0]_87\,
      I3 => \gen_old_sr_div4.gen_old_sr[0].old_sr_rise1_r_reg[0]_199\,
      O => \gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise1_r[0]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise1_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise1_r[0]_i_1_n_0\,
      Q => \gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise1_r_reg_n_0_[0]\,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise2_r[0]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise2_r_reg[0]_63\,
      I3 => \gen_old_sr_div4.gen_old_sr[0].old_sr_rise2_r_reg[0]_215\,
      O => \gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise2_r[0]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise2_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise2_r[0]_i_1_n_0\,
      Q => \gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise2_r_reg_n_0_[0]\,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise3_r[0]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise3_r_reg[0]_103\,
      I3 => \gen_old_sr_div4.gen_old_sr[0].old_sr_rise3_r_reg[0]_231\,
      O => \gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise3_r[0]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise3_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise3_r[0]_i_1_n_0\,
      Q => \gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise3_r_reg_n_0_[0]\,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[0].prev_sr_diff_r[0]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => sr_valid_r2,
      O => \gen_sr_match_div4.gen_sr_match[0].prev_sr_diff_r[0]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[0].prev_sr_diff_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_cyc2_r_reg[0]_inv_n_0\,
      Q => \gen_sr_match_div4.gen_sr_match[0].prev_sr_diff_r_reg_n_0_[0]\,
      R => \gen_sr_match_div4.gen_sr_match[0].prev_sr_diff_r[0]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_cyc2_r[0]_inv_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFF7FFF"
    )
        port map (
      I0 => \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall3_r_reg_n_0_[0]\,
      I1 => \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r_reg_n_0_[0]\,
      I2 => \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise3_r_reg_n_0_[0]\,
      I3 => \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise0_r_reg_n_0_[0]\,
      I4 => \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_cyc2_r[0]_inv_i_2_n_0\,
      O => p_515_out
    );
\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_cyc2_r[0]_inv_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7FFF"
    )
        port map (
      I0 => \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall2_r_reg_n_0_[0]\,
      I1 => \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise2_r_reg_n_0_[0]\,
      I2 => \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise1_r_reg_n_0_[0]\,
      I3 => \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall1_r_reg_n_0_[0]\,
      O => \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_cyc2_r[0]_inv_i_2_n_0\
    );
\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_cyc2_r_reg[0]_inv\: unisim.vcomponents.FDRE
    generic map(
      INIT => '1'
    )
        port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => p_515_out,
      Q => \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_cyc2_r_reg[0]_inv_n_0\,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall0_r_reg[0]_95\,
      I3 => \gen_old_sr_div4.gen_old_sr[0].prev_sr_fall0_r_reg[0]_143\,
      O => \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_1_n_0\,
      Q => \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r_reg_n_0_[0]\,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall1_r[0]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall1_r_reg[0]_71\,
      I3 => \gen_old_sr_div4.gen_old_sr[0].prev_sr_fall1_r_reg[0]_119\,
      O => \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall1_r[0]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall1_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall1_r[0]_i_1_n_0\,
      Q => \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall1_r_reg_n_0_[0]\,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall2_r[0]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall2_r_reg[0]_79\,
      I3 => \gen_old_sr_div4.gen_old_sr[0].prev_sr_fall2_r_reg[0]_127\,
      O => \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall2_r[0]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall2_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall2_r[0]_i_1_n_0\,
      Q => \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall2_r_reg_n_0_[0]\,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall3_r[0]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall3_r_reg[0]_55\,
      I3 => \gen_old_sr_div4.gen_old_sr[0].prev_sr_fall3_r_reg[0]_151\,
      O => \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall3_r[0]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall3_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall3_r[0]_i_1_n_0\,
      Q => \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall3_r_reg_n_0_[0]\,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise0_r[0]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise0_r_reg[0]_47\,
      I3 => \gen_old_sr_div4.gen_old_sr[0].prev_sr_rise0_r_reg[0]_159\,
      O => \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise0_r[0]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise0_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise0_r[0]_i_1_n_0\,
      Q => \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise0_r_reg_n_0_[0]\,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise1_r[0]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise1_r_reg[0]_87\,
      I3 => \gen_old_sr_div4.gen_old_sr[0].prev_sr_rise1_r_reg[0]_111\,
      O => \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise1_r[0]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise1_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise1_r[0]_i_1_n_0\,
      Q => \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise1_r_reg_n_0_[0]\,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise2_r[0]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise2_r_reg[0]_63\,
      I3 => \gen_old_sr_div4.gen_old_sr[0].prev_sr_rise2_r_reg[0]_135\,
      O => \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise2_r[0]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise2_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise2_r[0]_i_1_n_0\,
      Q => \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise2_r_reg_n_0_[0]\,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise3_r[0]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise3_r_reg[0]_103\,
      I3 => \gen_old_sr_div4.gen_old_sr[0].prev_sr_rise3_r_reg[0]_167\,
      O => \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise3_r[0]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise3_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise3_r[0]_i_1_n_0\,
      Q => \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise3_r_reg_n_0_[0]\,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[1].old_sr_diff_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[1].old_sr_match_cyc2_r_reg[1]_inv_n_0\,
      Q => p_1_in17_in,
      R => \gen_sr_match_div4.gen_sr_match[0].prev_sr_diff_r[0]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[1].old_sr_match_cyc2_r[1]_inv_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFF7FFF"
    )
        port map (
      I0 => p_7_in438_in,
      I1 => p_5_in436_in,
      I2 => p_6_in437_in,
      I3 => p_1_in439_in,
      I4 => \gen_sr_match_div4.gen_sr_match[1].old_sr_match_cyc2_r[1]_inv_i_2_n_0\,
      O => p_440_out
    );
\gen_sr_match_div4.gen_sr_match[1].old_sr_match_cyc2_r[1]_inv_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7FFF"
    )
        port map (
      I0 => p_3_in434_in,
      I1 => p_4_in435_in,
      I2 => p_2_in433_in,
      I3 => p_0_in432_in,
      O => \gen_sr_match_div4.gen_sr_match[1].old_sr_match_cyc2_r[1]_inv_i_2_n_0\
    );
\gen_sr_match_div4.gen_sr_match[1].old_sr_match_cyc2_r_reg[1]_inv\: unisim.vcomponents.FDRE
    generic map(
      INIT => '1'
    )
        port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => p_440_out,
      Q => \gen_sr_match_div4.gen_sr_match[1].old_sr_match_cyc2_r_reg[1]_inv_n_0\,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[1].old_sr_match_fall0_r[1]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall0_r_reg[1]_96\,
      I3 => \gen_old_sr_div4.gen_old_sr[1].old_sr_fall0_r_reg[1]_192\,
      O => \gen_sr_match_div4.gen_sr_match[1].old_sr_match_fall0_r[1]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[1].old_sr_match_fall0_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[1].old_sr_match_fall0_r[1]_i_1_n_0\,
      Q => p_0_in432_in,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[1].old_sr_match_fall1_r[1]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall1_r_reg[1]_72\,
      I3 => \gen_old_sr_div4.gen_old_sr[1].old_sr_fall1_r_reg[1]_208\,
      O => \gen_sr_match_div4.gen_sr_match[1].old_sr_match_fall1_r[1]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[1].old_sr_match_fall1_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[1].old_sr_match_fall1_r[1]_i_1_n_0\,
      Q => p_3_in434_in,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[1].old_sr_match_fall2_r[1]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall2_r_reg[1]_80\,
      I3 => \gen_old_sr_div4.gen_old_sr[1].old_sr_fall2_r_reg[1]_176\,
      O => \gen_sr_match_div4.gen_sr_match[1].old_sr_match_fall2_r[1]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[1].old_sr_match_fall2_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[1].old_sr_match_fall2_r[1]_i_1_n_0\,
      Q => p_5_in436_in,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[1].old_sr_match_fall3_r[1]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall3_r_reg[1]_56\,
      I3 => \gen_old_sr_div4.gen_old_sr[1].old_sr_fall3_r_reg[1]_184\,
      O => \gen_sr_match_div4.gen_sr_match[1].old_sr_match_fall3_r[1]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[1].old_sr_match_fall3_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[1].old_sr_match_fall3_r[1]_i_1_n_0\,
      Q => p_7_in438_in,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[1].old_sr_match_rise0_r[1]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise0_r_reg[1]_48\,
      I3 => \gen_old_sr_div4.gen_old_sr[1].old_sr_rise0_r_reg[1]_224\,
      O => \gen_sr_match_div4.gen_sr_match[1].old_sr_match_rise0_r[1]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[1].old_sr_match_rise0_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[1].old_sr_match_rise0_r[1]_i_1_n_0\,
      Q => p_1_in439_in,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[1].old_sr_match_rise1_r[1]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise1_r_reg[1]_88\,
      I3 => \gen_old_sr_div4.gen_old_sr[1].old_sr_rise1_r_reg[1]_200\,
      O => \gen_sr_match_div4.gen_sr_match[1].old_sr_match_rise1_r[1]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[1].old_sr_match_rise1_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[1].old_sr_match_rise1_r[1]_i_1_n_0\,
      Q => p_2_in433_in,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[1].old_sr_match_rise2_r[1]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise2_r_reg[1]_64\,
      I3 => \gen_old_sr_div4.gen_old_sr[1].old_sr_rise2_r_reg[1]_216\,
      O => \gen_sr_match_div4.gen_sr_match[1].old_sr_match_rise2_r[1]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[1].old_sr_match_rise2_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[1].old_sr_match_rise2_r[1]_i_1_n_0\,
      Q => p_4_in435_in,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[1].old_sr_match_rise3_r[1]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise3_r_reg[1]_104\,
      I3 => \gen_old_sr_div4.gen_old_sr[1].old_sr_rise3_r_reg[1]_232\,
      O => \gen_sr_match_div4.gen_sr_match[1].old_sr_match_rise3_r[1]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[1].old_sr_match_rise3_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[1].old_sr_match_rise3_r[1]_i_1_n_0\,
      Q => p_6_in437_in,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[1].prev_sr_diff_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[1].prev_sr_match_cyc2_r_reg[1]_inv_n_0\,
      Q => p_0_in103_in,
      R => \gen_sr_match_div4.gen_sr_match[0].prev_sr_diff_r[0]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[1].prev_sr_match_cyc2_r[1]_inv_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFF7FFF"
    )
        port map (
      I0 => p_6_in462_in,
      I1 => p_5_in461_in,
      I2 => p_7_in463_in,
      I3 => p_1_in464_in,
      I4 => \gen_sr_match_div4.gen_sr_match[1].prev_sr_match_cyc2_r[1]_inv_i_2_n_0\,
      O => p_465_out
    );
\gen_sr_match_div4.gen_sr_match[1].prev_sr_match_cyc2_r[1]_inv_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7FFF"
    )
        port map (
      I0 => p_3_in459_in,
      I1 => p_4_in460_in,
      I2 => p_2_in458_in,
      I3 => p_0_in457_in,
      O => \gen_sr_match_div4.gen_sr_match[1].prev_sr_match_cyc2_r[1]_inv_i_2_n_0\
    );
\gen_sr_match_div4.gen_sr_match[1].prev_sr_match_cyc2_r_reg[1]_inv\: unisim.vcomponents.FDRE
    generic map(
      INIT => '1'
    )
        port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => p_465_out,
      Q => \gen_sr_match_div4.gen_sr_match[1].prev_sr_match_cyc2_r_reg[1]_inv_n_0\,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[1].prev_sr_match_fall0_r[1]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall0_r_reg[1]_96\,
      I3 => \gen_old_sr_div4.gen_old_sr[1].prev_sr_fall0_r_reg[1]_144\,
      O => \gen_sr_match_div4.gen_sr_match[1].prev_sr_match_fall0_r[1]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[1].prev_sr_match_fall0_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[1].prev_sr_match_fall0_r[1]_i_1_n_0\,
      Q => p_0_in457_in,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[1].prev_sr_match_fall1_r[1]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall1_r_reg[1]_72\,
      I3 => \gen_old_sr_div4.gen_old_sr[1].prev_sr_fall1_r_reg[1]_120\,
      O => \gen_sr_match_div4.gen_sr_match[1].prev_sr_match_fall1_r[1]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[1].prev_sr_match_fall1_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[1].prev_sr_match_fall1_r[1]_i_1_n_0\,
      Q => p_3_in459_in,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[1].prev_sr_match_fall2_r[1]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall2_r_reg[1]_80\,
      I3 => \gen_old_sr_div4.gen_old_sr[1].prev_sr_fall2_r_reg[1]_128\,
      O => \gen_sr_match_div4.gen_sr_match[1].prev_sr_match_fall2_r[1]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[1].prev_sr_match_fall2_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[1].prev_sr_match_fall2_r[1]_i_1_n_0\,
      Q => p_5_in461_in,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[1].prev_sr_match_fall3_r[1]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall3_r_reg[1]_56\,
      I3 => \gen_old_sr_div4.gen_old_sr[1].prev_sr_fall3_r_reg[1]_152\,
      O => \gen_sr_match_div4.gen_sr_match[1].prev_sr_match_fall3_r[1]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[1].prev_sr_match_fall3_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[1].prev_sr_match_fall3_r[1]_i_1_n_0\,
      Q => p_7_in463_in,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[1].prev_sr_match_rise0_r[1]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise0_r_reg[1]_48\,
      I3 => \gen_old_sr_div4.gen_old_sr[1].prev_sr_rise0_r_reg[1]_160\,
      O => \gen_sr_match_div4.gen_sr_match[1].prev_sr_match_rise0_r[1]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[1].prev_sr_match_rise0_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[1].prev_sr_match_rise0_r[1]_i_1_n_0\,
      Q => p_1_in464_in,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[1].prev_sr_match_rise1_r[1]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise1_r_reg[1]_88\,
      I3 => \gen_old_sr_div4.gen_old_sr[1].prev_sr_rise1_r_reg[1]_112\,
      O => \gen_sr_match_div4.gen_sr_match[1].prev_sr_match_rise1_r[1]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[1].prev_sr_match_rise1_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[1].prev_sr_match_rise1_r[1]_i_1_n_0\,
      Q => p_2_in458_in,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[1].prev_sr_match_rise2_r[1]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise2_r_reg[1]_64\,
      I3 => \gen_old_sr_div4.gen_old_sr[1].prev_sr_rise2_r_reg[1]_136\,
      O => \gen_sr_match_div4.gen_sr_match[1].prev_sr_match_rise2_r[1]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[1].prev_sr_match_rise2_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[1].prev_sr_match_rise2_r[1]_i_1_n_0\,
      Q => p_4_in460_in,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[1].prev_sr_match_rise3_r[1]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise3_r_reg[1]_104\,
      I3 => \gen_old_sr_div4.gen_old_sr[1].prev_sr_rise3_r_reg[1]_168\,
      O => \gen_sr_match_div4.gen_sr_match[1].prev_sr_match_rise3_r[1]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[1].prev_sr_match_rise3_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[1].prev_sr_match_rise3_r[1]_i_1_n_0\,
      Q => p_6_in462_in,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[2].old_sr_diff_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[2].old_sr_match_cyc2_r_reg[2]_inv_n_0\,
      Q => p_1_in14_in,
      R => \gen_sr_match_div4.gen_sr_match[0].prev_sr_diff_r[0]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[2].old_sr_match_cyc2_r[2]_inv_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFF7FFF"
    )
        port map (
      I0 => p_7_in388_in,
      I1 => p_6_in387_in,
      I2 => p_5_in386_in,
      I3 => p_1_in389_in,
      I4 => \gen_sr_match_div4.gen_sr_match[2].old_sr_match_cyc2_r[2]_inv_i_2_n_0\,
      O => p_390_out
    );
\gen_sr_match_div4.gen_sr_match[2].old_sr_match_cyc2_r[2]_inv_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7FFF"
    )
        port map (
      I0 => p_3_in384_in,
      I1 => p_4_in385_in,
      I2 => p_0_in382_in,
      I3 => p_2_in383_in,
      O => \gen_sr_match_div4.gen_sr_match[2].old_sr_match_cyc2_r[2]_inv_i_2_n_0\
    );
\gen_sr_match_div4.gen_sr_match[2].old_sr_match_cyc2_r_reg[2]_inv\: unisim.vcomponents.FDRE
    generic map(
      INIT => '1'
    )
        port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => p_390_out,
      Q => \gen_sr_match_div4.gen_sr_match[2].old_sr_match_cyc2_r_reg[2]_inv_n_0\,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[2].old_sr_match_fall0_r[2]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall0_r_reg[2]_97\,
      I3 => \gen_old_sr_div4.gen_old_sr[2].old_sr_fall0_r_reg[2]_193\,
      O => \gen_sr_match_div4.gen_sr_match[2].old_sr_match_fall0_r[2]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[2].old_sr_match_fall0_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[2].old_sr_match_fall0_r[2]_i_1_n_0\,
      Q => p_0_in382_in,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[2].old_sr_match_fall1_r[2]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall1_r_reg[2]_73\,
      I3 => \gen_old_sr_div4.gen_old_sr[2].old_sr_fall1_r_reg[2]_209\,
      O => \gen_sr_match_div4.gen_sr_match[2].old_sr_match_fall1_r[2]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[2].old_sr_match_fall1_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[2].old_sr_match_fall1_r[2]_i_1_n_0\,
      Q => p_3_in384_in,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[2].old_sr_match_fall2_r[2]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall2_r_reg[2]_81\,
      I3 => \gen_old_sr_div4.gen_old_sr[2].old_sr_fall2_r_reg[2]_177\,
      O => \gen_sr_match_div4.gen_sr_match[2].old_sr_match_fall2_r[2]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[2].old_sr_match_fall2_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[2].old_sr_match_fall2_r[2]_i_1_n_0\,
      Q => p_5_in386_in,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[2].old_sr_match_fall3_r[2]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall3_r_reg[2]_57\,
      I3 => \gen_old_sr_div4.gen_old_sr[2].old_sr_fall3_r_reg[2]_185\,
      O => \gen_sr_match_div4.gen_sr_match[2].old_sr_match_fall3_r[2]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[2].old_sr_match_fall3_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[2].old_sr_match_fall3_r[2]_i_1_n_0\,
      Q => p_7_in388_in,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[2].old_sr_match_rise0_r[2]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise0_r_reg[2]_49\,
      I3 => \gen_old_sr_div4.gen_old_sr[2].old_sr_rise0_r_reg[2]_225\,
      O => \gen_sr_match_div4.gen_sr_match[2].old_sr_match_rise0_r[2]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[2].old_sr_match_rise0_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[2].old_sr_match_rise0_r[2]_i_1_n_0\,
      Q => p_1_in389_in,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[2].old_sr_match_rise1_r[2]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise1_r_reg[2]_89\,
      I3 => \gen_old_sr_div4.gen_old_sr[2].old_sr_rise1_r_reg[2]_201\,
      O => \gen_sr_match_div4.gen_sr_match[2].old_sr_match_rise1_r[2]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[2].old_sr_match_rise1_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[2].old_sr_match_rise1_r[2]_i_1_n_0\,
      Q => p_2_in383_in,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[2].old_sr_match_rise2_r[2]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise2_r_reg[2]_65\,
      I3 => \gen_old_sr_div4.gen_old_sr[2].old_sr_rise2_r_reg[2]_217\,
      O => \gen_sr_match_div4.gen_sr_match[2].old_sr_match_rise2_r[2]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[2].old_sr_match_rise2_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[2].old_sr_match_rise2_r[2]_i_1_n_0\,
      Q => p_4_in385_in,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[2].old_sr_match_rise3_r[2]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise3_r_reg[2]_105\,
      I3 => \gen_old_sr_div4.gen_old_sr[2].old_sr_rise3_r_reg[2]_233\,
      O => \gen_sr_match_div4.gen_sr_match[2].old_sr_match_rise3_r[2]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[2].old_sr_match_rise3_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[2].old_sr_match_rise3_r[2]_i_1_n_0\,
      Q => p_6_in387_in,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[2].prev_sr_diff_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[2].prev_sr_match_cyc2_r_reg[2]_inv_n_0\,
      Q => p_0_in100_in,
      R => \gen_sr_match_div4.gen_sr_match[0].prev_sr_diff_r[0]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[2].prev_sr_match_cyc2_r[2]_inv_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFF7FFF"
    )
        port map (
      I0 => p_7_in413_in,
      I1 => p_5_in411_in,
      I2 => p_6_in412_in,
      I3 => p_1_in414_in,
      I4 => \gen_sr_match_div4.gen_sr_match[2].prev_sr_match_cyc2_r[2]_inv_i_2_n_0\,
      O => p_415_out
    );
\gen_sr_match_div4.gen_sr_match[2].prev_sr_match_cyc2_r[2]_inv_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7FFF"
    )
        port map (
      I0 => p_3_in409_in,
      I1 => p_4_in410_in,
      I2 => p_2_in408_in,
      I3 => p_0_in407_in,
      O => \gen_sr_match_div4.gen_sr_match[2].prev_sr_match_cyc2_r[2]_inv_i_2_n_0\
    );
\gen_sr_match_div4.gen_sr_match[2].prev_sr_match_cyc2_r_reg[2]_inv\: unisim.vcomponents.FDRE
    generic map(
      INIT => '1'
    )
        port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => p_415_out,
      Q => \gen_sr_match_div4.gen_sr_match[2].prev_sr_match_cyc2_r_reg[2]_inv_n_0\,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[2].prev_sr_match_fall0_r[2]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall0_r_reg[2]_97\,
      I3 => \gen_old_sr_div4.gen_old_sr[2].prev_sr_fall0_r_reg[2]_145\,
      O => \gen_sr_match_div4.gen_sr_match[2].prev_sr_match_fall0_r[2]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[2].prev_sr_match_fall0_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[2].prev_sr_match_fall0_r[2]_i_1_n_0\,
      Q => p_0_in407_in,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[2].prev_sr_match_fall1_r[2]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall1_r_reg[2]_73\,
      I3 => \gen_old_sr_div4.gen_old_sr[2].prev_sr_fall1_r_reg[2]_121\,
      O => \gen_sr_match_div4.gen_sr_match[2].prev_sr_match_fall1_r[2]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[2].prev_sr_match_fall1_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[2].prev_sr_match_fall1_r[2]_i_1_n_0\,
      Q => p_3_in409_in,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[2].prev_sr_match_fall2_r[2]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall2_r_reg[2]_81\,
      I3 => \gen_old_sr_div4.gen_old_sr[2].prev_sr_fall2_r_reg[2]_129\,
      O => \gen_sr_match_div4.gen_sr_match[2].prev_sr_match_fall2_r[2]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[2].prev_sr_match_fall2_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[2].prev_sr_match_fall2_r[2]_i_1_n_0\,
      Q => p_5_in411_in,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[2].prev_sr_match_fall3_r[2]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall3_r_reg[2]_57\,
      I3 => \gen_old_sr_div4.gen_old_sr[2].prev_sr_fall3_r_reg[2]_153\,
      O => \gen_sr_match_div4.gen_sr_match[2].prev_sr_match_fall3_r[2]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[2].prev_sr_match_fall3_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[2].prev_sr_match_fall3_r[2]_i_1_n_0\,
      Q => p_7_in413_in,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[2].prev_sr_match_rise0_r[2]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise0_r_reg[2]_49\,
      I3 => \gen_old_sr_div4.gen_old_sr[2].prev_sr_rise0_r_reg[2]_161\,
      O => \gen_sr_match_div4.gen_sr_match[2].prev_sr_match_rise0_r[2]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[2].prev_sr_match_rise0_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[2].prev_sr_match_rise0_r[2]_i_1_n_0\,
      Q => p_1_in414_in,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[2].prev_sr_match_rise1_r[2]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise1_r_reg[2]_89\,
      I3 => \gen_old_sr_div4.gen_old_sr[2].prev_sr_rise1_r_reg[2]_113\,
      O => \gen_sr_match_div4.gen_sr_match[2].prev_sr_match_rise1_r[2]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[2].prev_sr_match_rise1_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[2].prev_sr_match_rise1_r[2]_i_1_n_0\,
      Q => p_2_in408_in,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[2].prev_sr_match_rise2_r[2]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise2_r_reg[2]_65\,
      I3 => \gen_old_sr_div4.gen_old_sr[2].prev_sr_rise2_r_reg[2]_137\,
      O => \gen_sr_match_div4.gen_sr_match[2].prev_sr_match_rise2_r[2]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[2].prev_sr_match_rise2_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[2].prev_sr_match_rise2_r[2]_i_1_n_0\,
      Q => p_4_in410_in,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[2].prev_sr_match_rise3_r[2]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise3_r_reg[2]_105\,
      I3 => \gen_old_sr_div4.gen_old_sr[2].prev_sr_rise3_r_reg[2]_169\,
      O => \gen_sr_match_div4.gen_sr_match[2].prev_sr_match_rise3_r[2]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[2].prev_sr_match_rise3_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[2].prev_sr_match_rise3_r[2]_i_1_n_0\,
      Q => p_6_in412_in,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[3].old_sr_diff_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[3].old_sr_match_cyc2_r_reg[3]_inv_n_0\,
      Q => p_1_in11_in,
      R => \gen_sr_match_div4.gen_sr_match[0].prev_sr_diff_r[0]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[3].old_sr_match_cyc2_r[3]_inv_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFF7FFF"
    )
        port map (
      I0 => p_7_in338_in,
      I1 => p_6_in337_in,
      I2 => p_3_in334_in,
      I3 => p_1_in339_in,
      I4 => \gen_sr_match_div4.gen_sr_match[3].old_sr_match_cyc2_r[3]_inv_i_2_n_0\,
      O => p_340_out
    );
\gen_sr_match_div4.gen_sr_match[3].old_sr_match_cyc2_r[3]_inv_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7FFF"
    )
        port map (
      I0 => p_4_in335_in,
      I1 => p_5_in336_in,
      I2 => p_0_in332_in,
      I3 => p_2_in333_in,
      O => \gen_sr_match_div4.gen_sr_match[3].old_sr_match_cyc2_r[3]_inv_i_2_n_0\
    );
\gen_sr_match_div4.gen_sr_match[3].old_sr_match_cyc2_r_reg[3]_inv\: unisim.vcomponents.FDRE
    generic map(
      INIT => '1'
    )
        port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => p_340_out,
      Q => \gen_sr_match_div4.gen_sr_match[3].old_sr_match_cyc2_r_reg[3]_inv_n_0\,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[3].old_sr_match_fall0_r[3]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall0_r_reg[3]_98\,
      I3 => \gen_old_sr_div4.gen_old_sr[3].old_sr_fall0_r_reg[3]_194\,
      O => \gen_sr_match_div4.gen_sr_match[3].old_sr_match_fall0_r[3]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[3].old_sr_match_fall0_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[3].old_sr_match_fall0_r[3]_i_1_n_0\,
      Q => p_0_in332_in,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[3].old_sr_match_fall1_r[3]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall1_r_reg[3]_74\,
      I3 => \gen_old_sr_div4.gen_old_sr[3].old_sr_fall1_r_reg[3]_210\,
      O => \gen_sr_match_div4.gen_sr_match[3].old_sr_match_fall1_r[3]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[3].old_sr_match_fall1_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[3].old_sr_match_fall1_r[3]_i_1_n_0\,
      Q => p_3_in334_in,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[3].old_sr_match_fall2_r[3]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall2_r_reg[3]_82\,
      I3 => \gen_old_sr_div4.gen_old_sr[3].old_sr_fall2_r_reg[3]_178\,
      O => \gen_sr_match_div4.gen_sr_match[3].old_sr_match_fall2_r[3]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[3].old_sr_match_fall2_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[3].old_sr_match_fall2_r[3]_i_1_n_0\,
      Q => p_5_in336_in,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[3].old_sr_match_fall3_r[3]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall3_r_reg[3]_58\,
      I3 => \gen_old_sr_div4.gen_old_sr[3].old_sr_fall3_r_reg[3]_186\,
      O => \gen_sr_match_div4.gen_sr_match[3].old_sr_match_fall3_r[3]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[3].old_sr_match_fall3_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[3].old_sr_match_fall3_r[3]_i_1_n_0\,
      Q => p_7_in338_in,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[3].old_sr_match_rise0_r[3]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise0_r_reg[3]_50\,
      I3 => \gen_old_sr_div4.gen_old_sr[3].old_sr_rise0_r_reg[3]_226\,
      O => \gen_sr_match_div4.gen_sr_match[3].old_sr_match_rise0_r[3]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[3].old_sr_match_rise0_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[3].old_sr_match_rise0_r[3]_i_1_n_0\,
      Q => p_1_in339_in,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[3].old_sr_match_rise1_r[3]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise1_r_reg[3]_90\,
      I3 => \gen_old_sr_div4.gen_old_sr[3].old_sr_rise1_r_reg[3]_202\,
      O => \gen_sr_match_div4.gen_sr_match[3].old_sr_match_rise1_r[3]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[3].old_sr_match_rise1_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[3].old_sr_match_rise1_r[3]_i_1_n_0\,
      Q => p_2_in333_in,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[3].old_sr_match_rise2_r[3]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise2_r_reg[3]_66\,
      I3 => \gen_old_sr_div4.gen_old_sr[3].old_sr_rise2_r_reg[3]_218\,
      O => \gen_sr_match_div4.gen_sr_match[3].old_sr_match_rise2_r[3]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[3].old_sr_match_rise2_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[3].old_sr_match_rise2_r[3]_i_1_n_0\,
      Q => p_4_in335_in,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[3].old_sr_match_rise3_r[3]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise3_r_reg[3]_106\,
      I3 => \gen_old_sr_div4.gen_old_sr[3].old_sr_rise3_r_reg[3]_234\,
      O => \gen_sr_match_div4.gen_sr_match[3].old_sr_match_rise3_r[3]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[3].old_sr_match_rise3_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[3].old_sr_match_rise3_r[3]_i_1_n_0\,
      Q => p_6_in337_in,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[3].prev_sr_diff_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[3].prev_sr_match_cyc2_r_reg[3]_inv_n_0\,
      Q => p_0_in97_in,
      R => \gen_sr_match_div4.gen_sr_match[0].prev_sr_diff_r[0]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[3].prev_sr_match_cyc2_r[3]_inv_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFF7FFF"
    )
        port map (
      I0 => p_5_in361_in,
      I1 => p_4_in360_in,
      I2 => p_7_in363_in,
      I3 => p_6_in362_in,
      I4 => \gen_sr_match_div4.gen_sr_match[3].prev_sr_match_cyc2_r[3]_inv_i_2_n_0\,
      O => p_365_out
    );
\gen_sr_match_div4.gen_sr_match[3].prev_sr_match_cyc2_r[3]_inv_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7FFF"
    )
        port map (
      I0 => p_0_in357_in,
      I1 => p_3_in359_in,
      I2 => p_2_in358_in,
      I3 => p_1_in364_in,
      O => \gen_sr_match_div4.gen_sr_match[3].prev_sr_match_cyc2_r[3]_inv_i_2_n_0\
    );
\gen_sr_match_div4.gen_sr_match[3].prev_sr_match_cyc2_r_reg[3]_inv\: unisim.vcomponents.FDRE
    generic map(
      INIT => '1'
    )
        port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => p_365_out,
      Q => \gen_sr_match_div4.gen_sr_match[3].prev_sr_match_cyc2_r_reg[3]_inv_n_0\,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[3].prev_sr_match_fall0_r[3]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall0_r_reg[3]_98\,
      I3 => \gen_old_sr_div4.gen_old_sr[3].prev_sr_fall0_r_reg[3]_146\,
      O => \gen_sr_match_div4.gen_sr_match[3].prev_sr_match_fall0_r[3]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[3].prev_sr_match_fall0_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[3].prev_sr_match_fall0_r[3]_i_1_n_0\,
      Q => p_0_in357_in,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[3].prev_sr_match_fall1_r[3]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall1_r_reg[3]_74\,
      I3 => \gen_old_sr_div4.gen_old_sr[3].prev_sr_fall1_r_reg[3]_122\,
      O => \gen_sr_match_div4.gen_sr_match[3].prev_sr_match_fall1_r[3]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[3].prev_sr_match_fall1_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[3].prev_sr_match_fall1_r[3]_i_1_n_0\,
      Q => p_3_in359_in,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[3].prev_sr_match_fall2_r[3]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall2_r_reg[3]_82\,
      I3 => \gen_old_sr_div4.gen_old_sr[3].prev_sr_fall2_r_reg[3]_130\,
      O => \gen_sr_match_div4.gen_sr_match[3].prev_sr_match_fall2_r[3]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[3].prev_sr_match_fall2_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[3].prev_sr_match_fall2_r[3]_i_1_n_0\,
      Q => p_5_in361_in,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[3].prev_sr_match_fall3_r[3]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall3_r_reg[3]_58\,
      I3 => \gen_old_sr_div4.gen_old_sr[3].prev_sr_fall3_r_reg[3]_154\,
      O => \gen_sr_match_div4.gen_sr_match[3].prev_sr_match_fall3_r[3]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[3].prev_sr_match_fall3_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[3].prev_sr_match_fall3_r[3]_i_1_n_0\,
      Q => p_7_in363_in,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[3].prev_sr_match_rise0_r[3]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise0_r_reg[3]_50\,
      I3 => \gen_old_sr_div4.gen_old_sr[3].prev_sr_rise0_r_reg[3]_162\,
      O => \gen_sr_match_div4.gen_sr_match[3].prev_sr_match_rise0_r[3]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[3].prev_sr_match_rise0_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[3].prev_sr_match_rise0_r[3]_i_1_n_0\,
      Q => p_1_in364_in,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[3].prev_sr_match_rise1_r[3]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise1_r_reg[3]_90\,
      I3 => \gen_old_sr_div4.gen_old_sr[3].prev_sr_rise1_r_reg[3]_114\,
      O => \gen_sr_match_div4.gen_sr_match[3].prev_sr_match_rise1_r[3]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[3].prev_sr_match_rise1_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[3].prev_sr_match_rise1_r[3]_i_1_n_0\,
      Q => p_2_in358_in,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[3].prev_sr_match_rise2_r[3]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise2_r_reg[3]_66\,
      I3 => \gen_old_sr_div4.gen_old_sr[3].prev_sr_rise2_r_reg[3]_138\,
      O => \gen_sr_match_div4.gen_sr_match[3].prev_sr_match_rise2_r[3]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[3].prev_sr_match_rise2_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[3].prev_sr_match_rise2_r[3]_i_1_n_0\,
      Q => p_4_in360_in,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[3].prev_sr_match_rise3_r[3]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise3_r_reg[3]_106\,
      I3 => \gen_old_sr_div4.gen_old_sr[3].prev_sr_rise3_r_reg[3]_170\,
      O => \gen_sr_match_div4.gen_sr_match[3].prev_sr_match_rise3_r[3]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[3].prev_sr_match_rise3_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[3].prev_sr_match_rise3_r[3]_i_1_n_0\,
      Q => p_6_in362_in,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[4].old_sr_diff_r_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[4].old_sr_match_cyc2_r_reg[4]_inv_n_0\,
      Q => p_1_in8_in,
      R => \gen_sr_match_div4.gen_sr_match[0].prev_sr_diff_r[0]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[4].old_sr_match_cyc2_r[4]_inv_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFF7FFF"
    )
        port map (
      I0 => p_7_in288_in,
      I1 => p_6_in287_in,
      I2 => p_0_in282_in,
      I3 => p_1_in289_in,
      I4 => \gen_sr_match_div4.gen_sr_match[4].old_sr_match_cyc2_r[4]_inv_i_2_n_0\,
      O => p_290_out
    );
\gen_sr_match_div4.gen_sr_match[4].old_sr_match_cyc2_r[4]_inv_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7FFF"
    )
        port map (
      I0 => p_4_in285_in,
      I1 => p_5_in286_in,
      I2 => p_2_in283_in,
      I3 => p_3_in284_in,
      O => \gen_sr_match_div4.gen_sr_match[4].old_sr_match_cyc2_r[4]_inv_i_2_n_0\
    );
\gen_sr_match_div4.gen_sr_match[4].old_sr_match_cyc2_r_reg[4]_inv\: unisim.vcomponents.FDRE
    generic map(
      INIT => '1'
    )
        port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => p_290_out,
      Q => \gen_sr_match_div4.gen_sr_match[4].old_sr_match_cyc2_r_reg[4]_inv_n_0\,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[4].old_sr_match_fall0_r[4]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall0_r_reg[4]_99\,
      I3 => \gen_old_sr_div4.gen_old_sr[4].old_sr_fall0_r_reg[4]_195\,
      O => \gen_sr_match_div4.gen_sr_match[4].old_sr_match_fall0_r[4]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[4].old_sr_match_fall0_r_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[4].old_sr_match_fall0_r[4]_i_1_n_0\,
      Q => p_0_in282_in,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[4].old_sr_match_fall1_r[4]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall1_r_reg[4]_75\,
      I3 => \gen_old_sr_div4.gen_old_sr[4].old_sr_fall1_r_reg[4]_211\,
      O => \gen_sr_match_div4.gen_sr_match[4].old_sr_match_fall1_r[4]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[4].old_sr_match_fall1_r_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[4].old_sr_match_fall1_r[4]_i_1_n_0\,
      Q => p_3_in284_in,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[4].old_sr_match_fall2_r[4]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall2_r_reg[4]_83\,
      I3 => \gen_old_sr_div4.gen_old_sr[4].old_sr_fall2_r_reg[4]_179\,
      O => \gen_sr_match_div4.gen_sr_match[4].old_sr_match_fall2_r[4]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[4].old_sr_match_fall2_r_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[4].old_sr_match_fall2_r[4]_i_1_n_0\,
      Q => p_5_in286_in,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[4].old_sr_match_fall3_r[4]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall3_r_reg[4]_59\,
      I3 => \gen_old_sr_div4.gen_old_sr[4].old_sr_fall3_r_reg[4]_187\,
      O => \gen_sr_match_div4.gen_sr_match[4].old_sr_match_fall3_r[4]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[4].old_sr_match_fall3_r_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[4].old_sr_match_fall3_r[4]_i_1_n_0\,
      Q => p_7_in288_in,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[4].old_sr_match_rise0_r[4]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise0_r_reg[4]_51\,
      I3 => \gen_old_sr_div4.gen_old_sr[4].old_sr_rise0_r_reg[4]_227\,
      O => \gen_sr_match_div4.gen_sr_match[4].old_sr_match_rise0_r[4]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[4].old_sr_match_rise0_r_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[4].old_sr_match_rise0_r[4]_i_1_n_0\,
      Q => p_1_in289_in,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[4].old_sr_match_rise1_r[4]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise1_r_reg[4]_91\,
      I3 => \gen_old_sr_div4.gen_old_sr[4].old_sr_rise1_r_reg[4]_203\,
      O => \gen_sr_match_div4.gen_sr_match[4].old_sr_match_rise1_r[4]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[4].old_sr_match_rise1_r_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[4].old_sr_match_rise1_r[4]_i_1_n_0\,
      Q => p_2_in283_in,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[4].old_sr_match_rise2_r[4]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise2_r_reg[4]_67\,
      I3 => \gen_old_sr_div4.gen_old_sr[4].old_sr_rise2_r_reg[4]_219\,
      O => \gen_sr_match_div4.gen_sr_match[4].old_sr_match_rise2_r[4]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[4].old_sr_match_rise2_r_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[4].old_sr_match_rise2_r[4]_i_1_n_0\,
      Q => p_4_in285_in,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[4].old_sr_match_rise3_r[4]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise3_r_reg[4]_107\,
      I3 => \gen_old_sr_div4.gen_old_sr[4].old_sr_rise3_r_reg[4]_235\,
      O => \gen_sr_match_div4.gen_sr_match[4].old_sr_match_rise3_r[4]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[4].old_sr_match_rise3_r_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[4].old_sr_match_rise3_r[4]_i_1_n_0\,
      Q => p_6_in287_in,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[4].prev_sr_diff_r_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[4].prev_sr_match_cyc2_r_reg[4]_inv_n_0\,
      Q => p_0_in94_in,
      R => \gen_sr_match_div4.gen_sr_match[0].prev_sr_diff_r[0]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[4].prev_sr_match_cyc2_r[4]_inv_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFF7FFF"
    )
        port map (
      I0 => p_6_in312_in,
      I1 => p_5_in311_in,
      I2 => p_7_in313_in,
      I3 => p_1_in314_in,
      I4 => \gen_sr_match_div4.gen_sr_match[4].prev_sr_match_cyc2_r[4]_inv_i_2_n_0\,
      O => p_315_out
    );
\gen_sr_match_div4.gen_sr_match[4].prev_sr_match_cyc2_r[4]_inv_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7FFF"
    )
        port map (
      I0 => p_3_in309_in,
      I1 => p_4_in310_in,
      I2 => p_0_in307_in,
      I3 => p_2_in308_in,
      O => \gen_sr_match_div4.gen_sr_match[4].prev_sr_match_cyc2_r[4]_inv_i_2_n_0\
    );
\gen_sr_match_div4.gen_sr_match[4].prev_sr_match_cyc2_r_reg[4]_inv\: unisim.vcomponents.FDRE
    generic map(
      INIT => '1'
    )
        port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => p_315_out,
      Q => \gen_sr_match_div4.gen_sr_match[4].prev_sr_match_cyc2_r_reg[4]_inv_n_0\,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[4].prev_sr_match_fall0_r[4]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall0_r_reg[4]_99\,
      I3 => \gen_old_sr_div4.gen_old_sr[4].prev_sr_fall0_r_reg[4]_147\,
      O => \gen_sr_match_div4.gen_sr_match[4].prev_sr_match_fall0_r[4]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[4].prev_sr_match_fall0_r_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[4].prev_sr_match_fall0_r[4]_i_1_n_0\,
      Q => p_0_in307_in,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[4].prev_sr_match_fall1_r[4]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall1_r_reg[4]_75\,
      I3 => \gen_old_sr_div4.gen_old_sr[4].prev_sr_fall1_r_reg[4]_123\,
      O => \gen_sr_match_div4.gen_sr_match[4].prev_sr_match_fall1_r[4]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[4].prev_sr_match_fall1_r_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[4].prev_sr_match_fall1_r[4]_i_1_n_0\,
      Q => p_3_in309_in,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[4].prev_sr_match_fall2_r[4]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall2_r_reg[4]_83\,
      I3 => \gen_old_sr_div4.gen_old_sr[4].prev_sr_fall2_r_reg[4]_131\,
      O => \gen_sr_match_div4.gen_sr_match[4].prev_sr_match_fall2_r[4]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[4].prev_sr_match_fall2_r_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[4].prev_sr_match_fall2_r[4]_i_1_n_0\,
      Q => p_5_in311_in,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[4].prev_sr_match_fall3_r[4]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall3_r_reg[4]_59\,
      I3 => \gen_old_sr_div4.gen_old_sr[4].prev_sr_fall3_r_reg[4]_155\,
      O => \gen_sr_match_div4.gen_sr_match[4].prev_sr_match_fall3_r[4]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[4].prev_sr_match_fall3_r_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[4].prev_sr_match_fall3_r[4]_i_1_n_0\,
      Q => p_7_in313_in,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[4].prev_sr_match_rise0_r[4]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise0_r_reg[4]_51\,
      I3 => \gen_old_sr_div4.gen_old_sr[4].prev_sr_rise0_r_reg[4]_163\,
      O => \gen_sr_match_div4.gen_sr_match[4].prev_sr_match_rise0_r[4]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[4].prev_sr_match_rise0_r_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[4].prev_sr_match_rise0_r[4]_i_1_n_0\,
      Q => p_1_in314_in,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[4].prev_sr_match_rise1_r[4]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise1_r_reg[4]_91\,
      I3 => \gen_old_sr_div4.gen_old_sr[4].prev_sr_rise1_r_reg[4]_115\,
      O => \gen_sr_match_div4.gen_sr_match[4].prev_sr_match_rise1_r[4]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[4].prev_sr_match_rise1_r_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[4].prev_sr_match_rise1_r[4]_i_1_n_0\,
      Q => p_2_in308_in,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[4].prev_sr_match_rise2_r[4]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise2_r_reg[4]_67\,
      I3 => \gen_old_sr_div4.gen_old_sr[4].prev_sr_rise2_r_reg[4]_139\,
      O => \gen_sr_match_div4.gen_sr_match[4].prev_sr_match_rise2_r[4]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[4].prev_sr_match_rise2_r_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[4].prev_sr_match_rise2_r[4]_i_1_n_0\,
      Q => p_4_in310_in,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[4].prev_sr_match_rise3_r[4]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise3_r_reg[4]_107\,
      I3 => \gen_old_sr_div4.gen_old_sr[4].prev_sr_rise3_r_reg[4]_171\,
      O => \gen_sr_match_div4.gen_sr_match[4].prev_sr_match_rise3_r[4]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[4].prev_sr_match_rise3_r_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[4].prev_sr_match_rise3_r[4]_i_1_n_0\,
      Q => p_6_in312_in,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[5].old_sr_diff_r_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[5].old_sr_match_cyc2_r_reg[5]_inv_n_0\,
      Q => p_1_in5_in,
      R => \gen_sr_match_div4.gen_sr_match[0].prev_sr_diff_r[0]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[5].old_sr_match_cyc2_r[5]_inv_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFF7FFF"
    )
        port map (
      I0 => p_7_in238_in,
      I1 => p_6_in237_in,
      I2 => p_0_in232_in,
      I3 => p_1_in239_in,
      I4 => \gen_sr_match_div4.gen_sr_match[5].old_sr_match_cyc2_r[5]_inv_i_2_n_0\,
      O => p_240_out
    );
\gen_sr_match_div4.gen_sr_match[5].old_sr_match_cyc2_r[5]_inv_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7FFF"
    )
        port map (
      I0 => p_4_in235_in,
      I1 => p_5_in236_in,
      I2 => p_2_in233_in,
      I3 => p_3_in234_in,
      O => \gen_sr_match_div4.gen_sr_match[5].old_sr_match_cyc2_r[5]_inv_i_2_n_0\
    );
\gen_sr_match_div4.gen_sr_match[5].old_sr_match_cyc2_r_reg[5]_inv\: unisim.vcomponents.FDRE
    generic map(
      INIT => '1'
    )
        port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => p_240_out,
      Q => \gen_sr_match_div4.gen_sr_match[5].old_sr_match_cyc2_r_reg[5]_inv_n_0\,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[5].old_sr_match_fall0_r[5]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall0_r_reg[5]_100\,
      I3 => \gen_old_sr_div4.gen_old_sr[5].old_sr_fall0_r_reg[5]_196\,
      O => \gen_sr_match_div4.gen_sr_match[5].old_sr_match_fall0_r[5]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[5].old_sr_match_fall0_r_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[5].old_sr_match_fall0_r[5]_i_1_n_0\,
      Q => p_0_in232_in,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[5].old_sr_match_fall1_r[5]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall1_r_reg[5]_76\,
      I3 => \gen_old_sr_div4.gen_old_sr[5].old_sr_fall1_r_reg[5]_212\,
      O => \gen_sr_match_div4.gen_sr_match[5].old_sr_match_fall1_r[5]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[5].old_sr_match_fall1_r_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[5].old_sr_match_fall1_r[5]_i_1_n_0\,
      Q => p_3_in234_in,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[5].old_sr_match_fall2_r[5]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall2_r_reg[5]_84\,
      I3 => \gen_old_sr_div4.gen_old_sr[5].old_sr_fall2_r_reg[5]_180\,
      O => \gen_sr_match_div4.gen_sr_match[5].old_sr_match_fall2_r[5]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[5].old_sr_match_fall2_r_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[5].old_sr_match_fall2_r[5]_i_1_n_0\,
      Q => p_5_in236_in,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[5].old_sr_match_fall3_r[5]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall3_r_reg[5]_60\,
      I3 => \gen_old_sr_div4.gen_old_sr[5].old_sr_fall3_r_reg[5]_188\,
      O => \gen_sr_match_div4.gen_sr_match[5].old_sr_match_fall3_r[5]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[5].old_sr_match_fall3_r_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[5].old_sr_match_fall3_r[5]_i_1_n_0\,
      Q => p_7_in238_in,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[5].old_sr_match_rise0_r[5]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise0_r_reg[5]_52\,
      I3 => \gen_old_sr_div4.gen_old_sr[5].old_sr_rise0_r_reg[5]_228\,
      O => \gen_sr_match_div4.gen_sr_match[5].old_sr_match_rise0_r[5]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[5].old_sr_match_rise0_r_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[5].old_sr_match_rise0_r[5]_i_1_n_0\,
      Q => p_1_in239_in,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[5].old_sr_match_rise1_r[5]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise1_r_reg[5]_92\,
      I3 => \gen_old_sr_div4.gen_old_sr[5].old_sr_rise1_r_reg[5]_204\,
      O => \gen_sr_match_div4.gen_sr_match[5].old_sr_match_rise1_r[5]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[5].old_sr_match_rise1_r_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[5].old_sr_match_rise1_r[5]_i_1_n_0\,
      Q => p_2_in233_in,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[5].old_sr_match_rise2_r[5]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise2_r_reg[5]_68\,
      I3 => \gen_old_sr_div4.gen_old_sr[5].old_sr_rise2_r_reg[5]_220\,
      O => \gen_sr_match_div4.gen_sr_match[5].old_sr_match_rise2_r[5]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[5].old_sr_match_rise2_r_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[5].old_sr_match_rise2_r[5]_i_1_n_0\,
      Q => p_4_in235_in,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[5].old_sr_match_rise3_r[5]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise3_r_reg[5]_108\,
      I3 => \gen_old_sr_div4.gen_old_sr[5].old_sr_rise3_r_reg[5]_236\,
      O => \gen_sr_match_div4.gen_sr_match[5].old_sr_match_rise3_r[5]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[5].old_sr_match_rise3_r_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[5].old_sr_match_rise3_r[5]_i_1_n_0\,
      Q => p_6_in237_in,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[5].prev_sr_diff_r_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[5].prev_sr_match_cyc2_r_reg[5]_inv_n_0\,
      Q => p_0_in91_in,
      R => \gen_sr_match_div4.gen_sr_match[0].prev_sr_diff_r[0]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[5].prev_sr_match_cyc2_r[5]_inv_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFF7FFF"
    )
        port map (
      I0 => p_7_in263_in,
      I1 => p_6_in262_in,
      I2 => p_0_in257_in,
      I3 => p_1_in264_in,
      I4 => \gen_sr_match_div4.gen_sr_match[5].prev_sr_match_cyc2_r[5]_inv_i_2_n_0\,
      O => p_265_out
    );
\gen_sr_match_div4.gen_sr_match[5].prev_sr_match_cyc2_r[5]_inv_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7FFF"
    )
        port map (
      I0 => p_4_in260_in,
      I1 => p_5_in261_in,
      I2 => p_2_in258_in,
      I3 => p_3_in259_in,
      O => \gen_sr_match_div4.gen_sr_match[5].prev_sr_match_cyc2_r[5]_inv_i_2_n_0\
    );
\gen_sr_match_div4.gen_sr_match[5].prev_sr_match_cyc2_r_reg[5]_inv\: unisim.vcomponents.FDRE
    generic map(
      INIT => '1'
    )
        port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => p_265_out,
      Q => \gen_sr_match_div4.gen_sr_match[5].prev_sr_match_cyc2_r_reg[5]_inv_n_0\,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[5].prev_sr_match_fall0_r[5]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall0_r_reg[5]_100\,
      I3 => \gen_old_sr_div4.gen_old_sr[5].prev_sr_fall0_r_reg[5]_148\,
      O => \gen_sr_match_div4.gen_sr_match[5].prev_sr_match_fall0_r[5]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[5].prev_sr_match_fall0_r_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[5].prev_sr_match_fall0_r[5]_i_1_n_0\,
      Q => p_0_in257_in,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[5].prev_sr_match_fall1_r[5]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall1_r_reg[5]_76\,
      I3 => \gen_old_sr_div4.gen_old_sr[5].prev_sr_fall1_r_reg[5]_124\,
      O => \gen_sr_match_div4.gen_sr_match[5].prev_sr_match_fall1_r[5]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[5].prev_sr_match_fall1_r_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[5].prev_sr_match_fall1_r[5]_i_1_n_0\,
      Q => p_3_in259_in,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[5].prev_sr_match_fall2_r[5]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall2_r_reg[5]_84\,
      I3 => \gen_old_sr_div4.gen_old_sr[5].prev_sr_fall2_r_reg[5]_132\,
      O => \gen_sr_match_div4.gen_sr_match[5].prev_sr_match_fall2_r[5]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[5].prev_sr_match_fall2_r_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[5].prev_sr_match_fall2_r[5]_i_1_n_0\,
      Q => p_5_in261_in,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[5].prev_sr_match_fall3_r[5]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall3_r_reg[5]_60\,
      I3 => \gen_old_sr_div4.gen_old_sr[5].prev_sr_fall3_r_reg[5]_156\,
      O => \gen_sr_match_div4.gen_sr_match[5].prev_sr_match_fall3_r[5]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[5].prev_sr_match_fall3_r_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[5].prev_sr_match_fall3_r[5]_i_1_n_0\,
      Q => p_7_in263_in,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[5].prev_sr_match_rise0_r[5]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise0_r_reg[5]_52\,
      I3 => \gen_old_sr_div4.gen_old_sr[5].prev_sr_rise0_r_reg[5]_164\,
      O => \gen_sr_match_div4.gen_sr_match[5].prev_sr_match_rise0_r[5]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[5].prev_sr_match_rise0_r_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[5].prev_sr_match_rise0_r[5]_i_1_n_0\,
      Q => p_1_in264_in,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[5].prev_sr_match_rise1_r[5]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise1_r_reg[5]_92\,
      I3 => \gen_old_sr_div4.gen_old_sr[5].prev_sr_rise1_r_reg[5]_116\,
      O => \gen_sr_match_div4.gen_sr_match[5].prev_sr_match_rise1_r[5]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[5].prev_sr_match_rise1_r_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[5].prev_sr_match_rise1_r[5]_i_1_n_0\,
      Q => p_2_in258_in,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[5].prev_sr_match_rise2_r[5]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise2_r_reg[5]_68\,
      I3 => \gen_old_sr_div4.gen_old_sr[5].prev_sr_rise2_r_reg[5]_140\,
      O => \gen_sr_match_div4.gen_sr_match[5].prev_sr_match_rise2_r[5]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[5].prev_sr_match_rise2_r_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[5].prev_sr_match_rise2_r[5]_i_1_n_0\,
      Q => p_4_in260_in,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[5].prev_sr_match_rise3_r[5]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise3_r_reg[5]_108\,
      I3 => \gen_old_sr_div4.gen_old_sr[5].prev_sr_rise3_r_reg[5]_172\,
      O => \gen_sr_match_div4.gen_sr_match[5].prev_sr_match_rise3_r[5]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[5].prev_sr_match_rise3_r_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[5].prev_sr_match_rise3_r[5]_i_1_n_0\,
      Q => p_6_in262_in,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[6].old_sr_diff_r_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[6].old_sr_match_cyc2_r_reg[6]_inv_n_0\,
      Q => p_1_in2_in,
      R => \gen_sr_match_div4.gen_sr_match[0].prev_sr_diff_r[0]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[6].old_sr_match_cyc2_r[6]_inv_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFF7FFF"
    )
        port map (
      I0 => p_7_in188_in,
      I1 => p_6_in187_in,
      I2 => p_0_in182_in,
      I3 => p_1_in189_in,
      I4 => \gen_sr_match_div4.gen_sr_match[6].old_sr_match_cyc2_r[6]_inv_i_2_n_0\,
      O => p_190_out
    );
\gen_sr_match_div4.gen_sr_match[6].old_sr_match_cyc2_r[6]_inv_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7FFF"
    )
        port map (
      I0 => p_4_in185_in,
      I1 => p_5_in186_in,
      I2 => p_2_in183_in,
      I3 => p_3_in184_in,
      O => \gen_sr_match_div4.gen_sr_match[6].old_sr_match_cyc2_r[6]_inv_i_2_n_0\
    );
\gen_sr_match_div4.gen_sr_match[6].old_sr_match_cyc2_r_reg[6]_inv\: unisim.vcomponents.FDRE
    generic map(
      INIT => '1'
    )
        port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => p_190_out,
      Q => \gen_sr_match_div4.gen_sr_match[6].old_sr_match_cyc2_r_reg[6]_inv_n_0\,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[6].old_sr_match_fall0_r[6]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall0_r_reg[6]_101\,
      I3 => \gen_old_sr_div4.gen_old_sr[6].old_sr_fall0_r_reg[6]_197\,
      O => \gen_sr_match_div4.gen_sr_match[6].old_sr_match_fall0_r[6]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[6].old_sr_match_fall0_r_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[6].old_sr_match_fall0_r[6]_i_1_n_0\,
      Q => p_0_in182_in,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[6].old_sr_match_fall1_r[6]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall1_r_reg[6]_77\,
      I3 => \gen_old_sr_div4.gen_old_sr[6].old_sr_fall1_r_reg[6]_213\,
      O => \gen_sr_match_div4.gen_sr_match[6].old_sr_match_fall1_r[6]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[6].old_sr_match_fall1_r_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[6].old_sr_match_fall1_r[6]_i_1_n_0\,
      Q => p_3_in184_in,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[6].old_sr_match_fall2_r[6]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall2_r_reg[6]_85\,
      I3 => \gen_old_sr_div4.gen_old_sr[6].old_sr_fall2_r_reg[6]_181\,
      O => \gen_sr_match_div4.gen_sr_match[6].old_sr_match_fall2_r[6]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[6].old_sr_match_fall2_r_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[6].old_sr_match_fall2_r[6]_i_1_n_0\,
      Q => p_5_in186_in,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[6].old_sr_match_fall3_r[6]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall3_r_reg[6]_61\,
      I3 => \gen_old_sr_div4.gen_old_sr[6].old_sr_fall3_r_reg[6]_189\,
      O => \gen_sr_match_div4.gen_sr_match[6].old_sr_match_fall3_r[6]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[6].old_sr_match_fall3_r_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[6].old_sr_match_fall3_r[6]_i_1_n_0\,
      Q => p_7_in188_in,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[6].old_sr_match_rise0_r[6]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise0_r_reg[6]_53\,
      I3 => \gen_old_sr_div4.gen_old_sr[6].old_sr_rise0_r_reg[6]_229\,
      O => \gen_sr_match_div4.gen_sr_match[6].old_sr_match_rise0_r[6]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[6].old_sr_match_rise0_r_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[6].old_sr_match_rise0_r[6]_i_1_n_0\,
      Q => p_1_in189_in,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[6].old_sr_match_rise1_r[6]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise1_r_reg[6]_93\,
      I3 => \gen_old_sr_div4.gen_old_sr[6].old_sr_rise1_r_reg[6]_205\,
      O => \gen_sr_match_div4.gen_sr_match[6].old_sr_match_rise1_r[6]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[6].old_sr_match_rise1_r_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[6].old_sr_match_rise1_r[6]_i_1_n_0\,
      Q => p_2_in183_in,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[6].old_sr_match_rise2_r[6]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise2_r_reg[6]_69\,
      I3 => \gen_old_sr_div4.gen_old_sr[6].old_sr_rise2_r_reg[6]_221\,
      O => \gen_sr_match_div4.gen_sr_match[6].old_sr_match_rise2_r[6]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[6].old_sr_match_rise2_r_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[6].old_sr_match_rise2_r[6]_i_1_n_0\,
      Q => p_4_in185_in,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[6].old_sr_match_rise3_r[6]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise3_r_reg[6]_109\,
      I3 => \gen_old_sr_div4.gen_old_sr[6].old_sr_rise3_r_reg[6]_237\,
      O => \gen_sr_match_div4.gen_sr_match[6].old_sr_match_rise3_r[6]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[6].old_sr_match_rise3_r_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[6].old_sr_match_rise3_r[6]_i_1_n_0\,
      Q => p_6_in187_in,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[6].prev_sr_diff_r_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[6].prev_sr_match_cyc2_r_reg[6]_inv_n_0\,
      Q => p_0_in88_in,
      R => \gen_sr_match_div4.gen_sr_match[0].prev_sr_diff_r[0]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[6].prev_sr_match_cyc2_r[6]_inv_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFF7FFF"
    )
        port map (
      I0 => p_7_in213_in,
      I1 => p_6_in212_in,
      I2 => p_0_in207_in,
      I3 => p_1_in214_in,
      I4 => \gen_sr_match_div4.gen_sr_match[6].prev_sr_match_cyc2_r[6]_inv_i_2_n_0\,
      O => p_215_out
    );
\gen_sr_match_div4.gen_sr_match[6].prev_sr_match_cyc2_r[6]_inv_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7FFF"
    )
        port map (
      I0 => p_4_in210_in,
      I1 => p_5_in211_in,
      I2 => p_2_in208_in,
      I3 => p_3_in209_in,
      O => \gen_sr_match_div4.gen_sr_match[6].prev_sr_match_cyc2_r[6]_inv_i_2_n_0\
    );
\gen_sr_match_div4.gen_sr_match[6].prev_sr_match_cyc2_r_reg[6]_inv\: unisim.vcomponents.FDRE
    generic map(
      INIT => '1'
    )
        port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => p_215_out,
      Q => \gen_sr_match_div4.gen_sr_match[6].prev_sr_match_cyc2_r_reg[6]_inv_n_0\,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[6].prev_sr_match_fall0_r[6]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall0_r_reg[6]_101\,
      I3 => \gen_old_sr_div4.gen_old_sr[6].prev_sr_fall0_r_reg[6]_149\,
      O => \gen_sr_match_div4.gen_sr_match[6].prev_sr_match_fall0_r[6]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[6].prev_sr_match_fall0_r_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[6].prev_sr_match_fall0_r[6]_i_1_n_0\,
      Q => p_0_in207_in,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[6].prev_sr_match_fall1_r[6]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall1_r_reg[6]_77\,
      I3 => \gen_old_sr_div4.gen_old_sr[6].prev_sr_fall1_r_reg[6]_125\,
      O => \gen_sr_match_div4.gen_sr_match[6].prev_sr_match_fall1_r[6]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[6].prev_sr_match_fall1_r_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[6].prev_sr_match_fall1_r[6]_i_1_n_0\,
      Q => p_3_in209_in,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[6].prev_sr_match_fall2_r[6]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall2_r_reg[6]_85\,
      I3 => \gen_old_sr_div4.gen_old_sr[6].prev_sr_fall2_r_reg[6]_133\,
      O => \gen_sr_match_div4.gen_sr_match[6].prev_sr_match_fall2_r[6]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[6].prev_sr_match_fall2_r_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[6].prev_sr_match_fall2_r[6]_i_1_n_0\,
      Q => p_5_in211_in,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[6].prev_sr_match_fall3_r[6]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall3_r_reg[6]_61\,
      I3 => \gen_old_sr_div4.gen_old_sr[6].prev_sr_fall3_r_reg[6]_157\,
      O => \gen_sr_match_div4.gen_sr_match[6].prev_sr_match_fall3_r[6]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[6].prev_sr_match_fall3_r_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[6].prev_sr_match_fall3_r[6]_i_1_n_0\,
      Q => p_7_in213_in,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[6].prev_sr_match_rise0_r[6]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise0_r_reg[6]_53\,
      I3 => \gen_old_sr_div4.gen_old_sr[6].prev_sr_rise0_r_reg[6]_165\,
      O => \gen_sr_match_div4.gen_sr_match[6].prev_sr_match_rise0_r[6]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[6].prev_sr_match_rise0_r_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[6].prev_sr_match_rise0_r[6]_i_1_n_0\,
      Q => p_1_in214_in,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[6].prev_sr_match_rise1_r[6]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise1_r_reg[6]_93\,
      I3 => \gen_old_sr_div4.gen_old_sr[6].prev_sr_rise1_r_reg[6]_117\,
      O => \gen_sr_match_div4.gen_sr_match[6].prev_sr_match_rise1_r[6]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[6].prev_sr_match_rise1_r_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[6].prev_sr_match_rise1_r[6]_i_1_n_0\,
      Q => p_2_in208_in,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[6].prev_sr_match_rise2_r[6]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise2_r_reg[6]_69\,
      I3 => \gen_old_sr_div4.gen_old_sr[6].prev_sr_rise2_r_reg[6]_141\,
      O => \gen_sr_match_div4.gen_sr_match[6].prev_sr_match_rise2_r[6]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[6].prev_sr_match_rise2_r_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[6].prev_sr_match_rise2_r[6]_i_1_n_0\,
      Q => p_4_in210_in,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[6].prev_sr_match_rise3_r[6]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise3_r_reg[6]_109\,
      I3 => \gen_old_sr_div4.gen_old_sr[6].prev_sr_rise3_r_reg[6]_173\,
      O => \gen_sr_match_div4.gen_sr_match[6].prev_sr_match_rise3_r[6]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[6].prev_sr_match_rise3_r_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[6].prev_sr_match_rise3_r[6]_i_1_n_0\,
      Q => p_6_in212_in,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[7].old_sr_diff_r_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[7].old_sr_match_cyc2_r_reg[7]_inv_n_0\,
      Q => \gen_sr_match_div4.gen_sr_match[7].old_sr_diff_r_reg_n_0_[7]\,
      R => \gen_sr_match_div4.gen_sr_match[0].prev_sr_diff_r[0]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[7].old_sr_match_cyc2_r[7]_inv_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFF7FFF"
    )
        port map (
      I0 => p_7_in,
      I1 => p_6_in137_in,
      I2 => p_0_in135_in,
      I3 => p_1_in138_in,
      I4 => \gen_sr_match_div4.gen_sr_match[7].old_sr_match_cyc2_r[7]_inv_i_2_n_0\,
      O => p_139_out
    );
\gen_sr_match_div4.gen_sr_match[7].old_sr_match_cyc2_r[7]_inv_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7FFF"
    )
        port map (
      I0 => \gen_sr_match_div4.gen_sr_match[7].old_sr_match_rise2_r_reg_n_0_[7]\,
      I1 => \gen_sr_match_div4.gen_sr_match[7].old_sr_match_fall2_r_reg_n_0_[7]\,
      I2 => \gen_sr_match_div4.gen_sr_match[7].old_sr_match_rise1_r_reg_n_0_[7]\,
      I3 => p_3_in136_in,
      O => \gen_sr_match_div4.gen_sr_match[7].old_sr_match_cyc2_r[7]_inv_i_2_n_0\
    );
\gen_sr_match_div4.gen_sr_match[7].old_sr_match_cyc2_r_reg[7]_inv\: unisim.vcomponents.FDRE
    generic map(
      INIT => '1'
    )
        port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => p_139_out,
      Q => \gen_sr_match_div4.gen_sr_match[7].old_sr_match_cyc2_r_reg[7]_inv_n_0\,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[7].old_sr_match_fall0_r[7]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall0_r_reg[7]_102\,
      I3 => \gen_old_sr_div4.gen_old_sr[7].old_sr_fall0_r_reg[7]_198\,
      O => \gen_sr_match_div4.gen_sr_match[7].old_sr_match_fall0_r[7]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[7].old_sr_match_fall0_r_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[7].old_sr_match_fall0_r[7]_i_1_n_0\,
      Q => p_0_in135_in,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[7].old_sr_match_fall1_r[7]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall1_r_reg[7]_78\,
      I3 => \gen_old_sr_div4.gen_old_sr[7].old_sr_fall1_r_reg[7]_214\,
      O => \gen_sr_match_div4.gen_sr_match[7].old_sr_match_fall1_r[7]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[7].old_sr_match_fall1_r_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[7].old_sr_match_fall1_r[7]_i_1_n_0\,
      Q => p_3_in136_in,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[7].old_sr_match_fall2_r[7]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall2_r_reg[7]_86\,
      I3 => \gen_old_sr_div4.gen_old_sr[7].old_sr_fall2_r_reg[7]_182\,
      O => \gen_sr_match_div4.gen_sr_match[7].old_sr_match_fall2_r[7]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[7].old_sr_match_fall2_r_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[7].old_sr_match_fall2_r[7]_i_1_n_0\,
      Q => \gen_sr_match_div4.gen_sr_match[7].old_sr_match_fall2_r_reg_n_0_[7]\,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[7].old_sr_match_fall3_r[7]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall3_r_reg[7]_62\,
      I3 => \gen_old_sr_div4.gen_old_sr[7].old_sr_fall3_r_reg[7]_190\,
      O => \gen_sr_match_div4.gen_sr_match[7].old_sr_match_fall3_r[7]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[7].old_sr_match_fall3_r_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[7].old_sr_match_fall3_r[7]_i_1_n_0\,
      Q => p_7_in,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[7].old_sr_match_rise0_r[7]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise0_r_reg[7]_54\,
      I3 => \gen_old_sr_div4.gen_old_sr[7].old_sr_rise0_r_reg[7]_230\,
      O => \gen_sr_match_div4.gen_sr_match[7].old_sr_match_rise0_r[7]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[7].old_sr_match_rise0_r_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[7].old_sr_match_rise0_r[7]_i_1_n_0\,
      Q => p_1_in138_in,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[7].old_sr_match_rise1_r[7]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise1_r_reg[7]_94\,
      I3 => \gen_old_sr_div4.gen_old_sr[7].old_sr_rise1_r_reg[7]_206\,
      O => \gen_sr_match_div4.gen_sr_match[7].old_sr_match_rise1_r[7]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[7].old_sr_match_rise1_r_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[7].old_sr_match_rise1_r[7]_i_1_n_0\,
      Q => \gen_sr_match_div4.gen_sr_match[7].old_sr_match_rise1_r_reg_n_0_[7]\,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[7].old_sr_match_rise2_r[7]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise2_r_reg[7]_70\,
      I3 => \gen_old_sr_div4.gen_old_sr[7].old_sr_rise2_r_reg[7]_222\,
      O => \gen_sr_match_div4.gen_sr_match[7].old_sr_match_rise2_r[7]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[7].old_sr_match_rise2_r_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[7].old_sr_match_rise2_r[7]_i_1_n_0\,
      Q => \gen_sr_match_div4.gen_sr_match[7].old_sr_match_rise2_r_reg_n_0_[7]\,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[7].old_sr_match_rise3_r[7]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise3_r_reg[7]_110\,
      I3 => \gen_old_sr_div4.gen_old_sr[7].old_sr_rise3_r_reg[7]_238\,
      O => \gen_sr_match_div4.gen_sr_match[7].old_sr_match_rise3_r[7]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[7].old_sr_match_rise3_r_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[7].old_sr_match_rise3_r[7]_i_1_n_0\,
      Q => p_6_in137_in,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[7].prev_sr_diff_r_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[7].prev_sr_match_cyc2_r_reg[7]_inv_n_0\,
      Q => \gen_sr_match_div4.gen_sr_match[7].prev_sr_diff_r_reg_n_0_[7]\,
      R => \gen_sr_match_div4.gen_sr_match[0].prev_sr_diff_r[0]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[7].prev_sr_match_cyc2_r[7]_inv_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFF7FFF"
    )
        port map (
      I0 => p_7_in163_in,
      I1 => p_6_in162_in,
      I2 => p_0_in157_in,
      I3 => p_1_in164_in,
      I4 => \gen_sr_match_div4.gen_sr_match[7].prev_sr_match_cyc2_r[7]_inv_i_2_n_0\,
      O => p_165_out
    );
\gen_sr_match_div4.gen_sr_match[7].prev_sr_match_cyc2_r[7]_inv_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7FFF"
    )
        port map (
      I0 => p_4_in160_in,
      I1 => p_5_in161_in,
      I2 => p_2_in158_in,
      I3 => p_3_in159_in,
      O => \gen_sr_match_div4.gen_sr_match[7].prev_sr_match_cyc2_r[7]_inv_i_2_n_0\
    );
\gen_sr_match_div4.gen_sr_match[7].prev_sr_match_cyc2_r_reg[7]_inv\: unisim.vcomponents.FDRE
    generic map(
      INIT => '1'
    )
        port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => p_165_out,
      Q => \gen_sr_match_div4.gen_sr_match[7].prev_sr_match_cyc2_r_reg[7]_inv_n_0\,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[7].prev_sr_match_fall0_r[7]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall0_r_reg[7]_102\,
      I3 => \gen_old_sr_div4.gen_old_sr[7].prev_sr_fall0_r_reg[7]_150\,
      O => \gen_sr_match_div4.gen_sr_match[7].prev_sr_match_fall0_r[7]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[7].prev_sr_match_fall0_r_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[7].prev_sr_match_fall0_r[7]_i_1_n_0\,
      Q => p_0_in157_in,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[7].prev_sr_match_fall1_r[7]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall1_r_reg[7]_78\,
      I3 => \gen_old_sr_div4.gen_old_sr[7].prev_sr_fall1_r_reg[7]_126\,
      O => \gen_sr_match_div4.gen_sr_match[7].prev_sr_match_fall1_r[7]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[7].prev_sr_match_fall1_r_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[7].prev_sr_match_fall1_r[7]_i_1_n_0\,
      Q => p_3_in159_in,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[7].prev_sr_match_fall2_r[7]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall2_r_reg[7]_86\,
      I3 => \gen_old_sr_div4.gen_old_sr[7].prev_sr_fall2_r_reg[7]_134\,
      O => \gen_sr_match_div4.gen_sr_match[7].prev_sr_match_fall2_r[7]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[7].prev_sr_match_fall2_r_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[7].prev_sr_match_fall2_r[7]_i_1_n_0\,
      Q => p_5_in161_in,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[7].prev_sr_match_fall3_r[7]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall3_r_reg[7]_62\,
      I3 => \gen_old_sr_div4.gen_old_sr[7].prev_sr_fall3_r_reg[7]_158\,
      O => \gen_sr_match_div4.gen_sr_match[7].prev_sr_match_fall3_r[7]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[7].prev_sr_match_fall3_r_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[7].prev_sr_match_fall3_r[7]_i_1_n_0\,
      Q => p_7_in163_in,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[7].prev_sr_match_rise0_r[7]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise0_r_reg[7]_54\,
      I3 => \gen_old_sr_div4.gen_old_sr[7].prev_sr_rise0_r_reg[7]_166\,
      O => \gen_sr_match_div4.gen_sr_match[7].prev_sr_match_rise0_r[7]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[7].prev_sr_match_rise0_r_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[7].prev_sr_match_rise0_r[7]_i_1_n_0\,
      Q => p_1_in164_in,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[7].prev_sr_match_rise1_r[7]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise1_r_reg[7]_94\,
      I3 => \gen_old_sr_div4.gen_old_sr[7].prev_sr_rise1_r_reg[7]_118\,
      O => \gen_sr_match_div4.gen_sr_match[7].prev_sr_match_rise1_r[7]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[7].prev_sr_match_rise1_r_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[7].prev_sr_match_rise1_r[7]_i_1_n_0\,
      Q => p_2_in158_in,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[7].prev_sr_match_rise2_r[7]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise2_r_reg[7]_70\,
      I3 => \gen_old_sr_div4.gen_old_sr[7].prev_sr_rise2_r_reg[7]_142\,
      O => \gen_sr_match_div4.gen_sr_match[7].prev_sr_match_rise2_r[7]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[7].prev_sr_match_rise2_r_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[7].prev_sr_match_rise2_r[7]_i_1_n_0\,
      Q => p_4_in160_in,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[7].prev_sr_match_rise3_r[7]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise3_r_reg[7]_110\,
      I3 => \gen_old_sr_div4.gen_old_sr[7].prev_sr_rise3_r_reg[7]_174\,
      O => \gen_sr_match_div4.gen_sr_match[7].prev_sr_match_rise3_r[7]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[7].prev_sr_match_rise3_r_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[7].prev_sr_match_rise3_r[7]_i_1_n_0\,
      Q => p_6_in162_in,
      R => '0'
    );
\gen_track_left_edge[0].pb_cnt_eye_size_r[0][0]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0]_239\(0),
      O => \p_0_in__3\(0)
    );
\gen_track_left_edge[0].pb_cnt_eye_size_r[0][1]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0]_239\(1),
      I1 => \gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0]_239\(0),
      O => \p_0_in__3\(1)
    );
\gen_track_left_edge[0].pb_cnt_eye_size_r[0][2]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"6A"
    )
        port map (
      I0 => \gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0]_239\(2),
      I1 => \gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0]_239\(0),
      I2 => \gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0]_239\(1),
      O => \p_0_in__3\(2)
    );
\gen_track_left_edge[0].pb_cnt_eye_size_r[0][3]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6AAA"
    )
        port map (
      I0 => \gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0]_239\(3),
      I1 => \gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0]_239\(1),
      I2 => \gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0]_239\(0),
      I3 => \gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0]_239\(2),
      O => \p_0_in__3\(3)
    );
\gen_track_left_edge[0].pb_cnt_eye_size_r[0][4]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFEFAAAA"
    )
        port map (
      I0 => \FSM_onehot_cal1_state_r_reg_n_0_[16]\,
      I1 => \gen_track_left_edge[0].pb_last_tap_jitter_r_reg_n_0_[0]\,
      I2 => samp_cnt_done_r_reg_n_0,
      I3 => \gen_track_left_edge[0].pb_found_edge_r_reg_n_0_[0]\,
      I4 => \gen_track_left_edge[0].pb_cnt_eye_size_r[0][4]_i_4_n_0\,
      O => \gen_track_left_edge[0].pb_cnt_eye_size_r[0][4]_i_1_n_0\
    );
\gen_track_left_edge[0].pb_cnt_eye_size_r[0][4]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"11100000"
    )
        port map (
      I0 => \gen_track_left_edge[0].pb_cnt_eye_size_r[0][4]_i_5_n_0\,
      I1 => pb_detect_edge_done_r(0),
      I2 => store_sr_req_pulsed_r,
      I3 => p_34_in,
      I4 => samp_cnt_done_r_reg_n_0,
      O => pb_cnt_eye_size_r
    );
\gen_track_left_edge[0].pb_cnt_eye_size_r[0][4]_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"6AAAAAAA"
    )
        port map (
      I0 => \gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0]_239\(4),
      I1 => \gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0]_239\(2),
      I2 => \gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0]_239\(0),
      I3 => \gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0]_239\(1),
      I4 => \gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0]_239\(3),
      O => \p_0_in__3\(4)
    );
\gen_track_left_edge[0].pb_cnt_eye_size_r[0][4]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"1111111111111110"
    )
        port map (
      I0 => \FSM_onehot_cal1_state_r[34]_i_4_n_0\,
      I1 => pb_detect_edge_done_r(0),
      I2 => \gen_track_left_edge[0].pb_last_tap_jitter_r_reg_n_0_[0]\,
      I3 => \gen_sr_match_div4.gen_sr_match[0].old_sr_diff_r_reg_n_0_[0]\,
      I4 => \gen_sr_match_div4.gen_sr_match[0].prev_sr_diff_r_reg_n_0_[0]\,
      I5 => samp_cnt_done_r_reg_n_0,
      O => \gen_track_left_edge[0].pb_cnt_eye_size_r[0][4]_i_4_n_0\
    );
\gen_track_left_edge[0].pb_cnt_eye_size_r[0][4]_i_5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00008000"
    )
        port map (
      I0 => \gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0]_239\(2),
      I1 => \gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0]_239\(0),
      I2 => \gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0]_239\(1),
      I3 => \gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0]_239\(3),
      I4 => \gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0]_239\(4),
      O => \gen_track_left_edge[0].pb_cnt_eye_size_r[0][4]_i_5_n_0\
    );
\gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0][0]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => pb_cnt_eye_size_r,
      D => \p_0_in__3\(0),
      Q => \gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0]_239\(0),
      R => \gen_track_left_edge[0].pb_cnt_eye_size_r[0][4]_i_1_n_0\
    );
\gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0][1]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => pb_cnt_eye_size_r,
      D => \p_0_in__3\(1),
      Q => \gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0]_239\(1),
      R => \gen_track_left_edge[0].pb_cnt_eye_size_r[0][4]_i_1_n_0\
    );
\gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0][2]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => pb_cnt_eye_size_r,
      D => \p_0_in__3\(2),
      Q => \gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0]_239\(2),
      R => \gen_track_left_edge[0].pb_cnt_eye_size_r[0][4]_i_1_n_0\
    );
\gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0][3]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => pb_cnt_eye_size_r,
      D => \p_0_in__3\(3),
      Q => \gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0]_239\(3),
      R => \gen_track_left_edge[0].pb_cnt_eye_size_r[0][4]_i_1_n_0\
    );
\gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0][4]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => pb_cnt_eye_size_r,
      D => \p_0_in__3\(4),
      Q => \gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0]_239\(4),
      R => \gen_track_left_edge[0].pb_cnt_eye_size_r[0][4]_i_1_n_0\
    );
\gen_track_left_edge[0].pb_detect_edge_done_r[0]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"EEEEEEE0"
    )
        port map (
      I0 => store_sr_req_pulsed_r,
      I1 => p_34_in,
      I2 => \gen_sr_match_div4.gen_sr_match[0].prev_sr_diff_r_reg_n_0_[0]\,
      I3 => samp_cnt_done_r_reg_n_0,
      I4 => pb_detect_edge_done_r(0),
      O => \gen_track_left_edge[0].pb_detect_edge_done_r[0]_i_1_n_0\
    );
\gen_track_left_edge[0].pb_detect_edge_done_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_track_left_edge[0].pb_detect_edge_done_r[0]_i_1_n_0\,
      Q => pb_detect_edge_done_r(0),
      R => \FSM_onehot_cal1_state_r_reg_n_0_[16]\
    );
\gen_track_left_edge[0].pb_found_edge_r[0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"5555555501000101"
    )
        port map (
      I0 => \FSM_onehot_cal1_state_r[34]_i_4_n_0\,
      I1 => pb_detect_edge_done_r(0),
      I2 => \gen_track_left_edge[0].pb_found_edge_r[0]_i_2_n_0\,
      I3 => \gen_track_left_edge[0].pb_last_tap_jitter_r_reg_n_0_[0]\,
      I4 => samp_cnt_done_r_reg_n_0,
      I5 => \gen_track_left_edge[0].pb_found_edge_r_reg_n_0_[0]\,
      O => \gen_track_left_edge[0].pb_found_edge_r[0]_i_1_n_0\
    );
\gen_track_left_edge[0].pb_found_edge_r[0]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0001"
    )
        port map (
      I0 => samp_cnt_done_r_reg_n_0,
      I1 => \gen_sr_match_div4.gen_sr_match[0].prev_sr_diff_r_reg_n_0_[0]\,
      I2 => \gen_sr_match_div4.gen_sr_match[0].old_sr_diff_r_reg_n_0_[0]\,
      I3 => \gen_track_left_edge[0].pb_last_tap_jitter_r_reg_n_0_[0]\,
      O => \gen_track_left_edge[0].pb_found_edge_r[0]_i_2_n_0\
    );
\gen_track_left_edge[0].pb_found_edge_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_track_left_edge[0].pb_found_edge_r[0]_i_1_n_0\,
      Q => \gen_track_left_edge[0].pb_found_edge_r_reg_n_0_[0]\,
      R => \FSM_onehot_cal1_state_r_reg_n_0_[16]\
    );
\gen_track_left_edge[0].pb_found_stable_eye_r[0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"55555F5500000800"
    )
        port map (
      I0 => \gen_track_left_edge[0].pb_cnt_eye_size_r[0][4]_i_4_n_0\,
      I1 => \gen_track_left_edge[0].pb_cnt_eye_size_r[0][4]_i_5_n_0\,
      I2 => \gen_track_left_edge[0].pb_last_tap_jitter_r_reg_n_0_[0]\,
      I3 => samp_cnt_done_r_reg_n_0,
      I4 => \gen_track_left_edge[0].pb_found_edge_r_reg_n_0_[0]\,
      I5 => pb_found_stable_eye_r(0),
      O => \gen_track_left_edge[0].pb_found_stable_eye_r[0]_i_1_n_0\
    );
\gen_track_left_edge[0].pb_found_stable_eye_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_track_left_edge[0].pb_found_stable_eye_r[0]_i_1_n_0\,
      Q => pb_found_stable_eye_r(0),
      R => \FSM_onehot_cal1_state_r_reg_n_0_[16]\
    );
\gen_track_left_edge[0].pb_last_tap_jitter_r[0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000FDFD0100"
    )
        port map (
      I0 => samp_cnt_done_r_reg_n_0,
      I1 => pb_detect_edge_done_r(0),
      I2 => \FSM_onehot_cal1_state_r[34]_i_4_n_0\,
      I3 => \gen_sr_match_div4.gen_sr_match[0].prev_sr_diff_r_reg_n_0_[0]\,
      I4 => \gen_track_left_edge[0].pb_last_tap_jitter_r_reg_n_0_[0]\,
      I5 => \FSM_onehot_cal1_state_r_reg_n_0_[16]\,
      O => \gen_track_left_edge[0].pb_last_tap_jitter_r[0]_i_1_n_0\
    );
\gen_track_left_edge[0].pb_last_tap_jitter_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_track_left_edge[0].pb_last_tap_jitter_r[0]_i_1_n_0\,
      Q => \gen_track_left_edge[0].pb_last_tap_jitter_r_reg_n_0_[0]\,
      R => '0'
    );
\gen_track_left_edge[1].pb_cnt_eye_size_r[1][0]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1]_240\(0),
      O => \p_0_in__4\(0)
    );
\gen_track_left_edge[1].pb_cnt_eye_size_r[1][1]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1]_240\(1),
      I1 => \gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1]_240\(0),
      O => \p_0_in__4\(1)
    );
\gen_track_left_edge[1].pb_cnt_eye_size_r[1][2]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"6A"
    )
        port map (
      I0 => \gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1]_240\(2),
      I1 => \gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1]_240\(0),
      I2 => \gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1]_240\(1),
      O => \p_0_in__4\(2)
    );
\gen_track_left_edge[1].pb_cnt_eye_size_r[1][3]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6AAA"
    )
        port map (
      I0 => \gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1]_240\(3),
      I1 => \gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1]_240\(1),
      I2 => \gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1]_240\(0),
      I3 => \gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1]_240\(2),
      O => \p_0_in__4\(3)
    );
\gen_track_left_edge[1].pb_cnt_eye_size_r[1][4]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFEFAAAA"
    )
        port map (
      I0 => \FSM_onehot_cal1_state_r_reg_n_0_[16]\,
      I1 => \gen_track_left_edge[1].pb_found_edge_r_reg_n_0_[1]\,
      I2 => samp_cnt_done_r_reg_n_0,
      I3 => p_0_in16_in,
      I4 => \gen_track_left_edge[1].pb_cnt_eye_size_r[1][4]_i_4_n_0\,
      O => \gen_track_left_edge[1].pb_cnt_eye_size_r[1][4]_i_1_n_0\
    );
\gen_track_left_edge[1].pb_cnt_eye_size_r[1][4]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"11100000"
    )
        port map (
      I0 => \gen_track_left_edge[1].pb_cnt_eye_size_r[1][4]_i_5_n_0\,
      I1 => pb_detect_edge_done_r(1),
      I2 => store_sr_req_pulsed_r,
      I3 => p_34_in,
      I4 => samp_cnt_done_r_reg_n_0,
      O => \gen_track_left_edge[1].pb_cnt_eye_size_r[1][4]_i_2_n_0\
    );
\gen_track_left_edge[1].pb_cnt_eye_size_r[1][4]_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"6AAAAAAA"
    )
        port map (
      I0 => \gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1]_240\(4),
      I1 => \gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1]_240\(2),
      I2 => \gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1]_240\(0),
      I3 => \gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1]_240\(1),
      I4 => \gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1]_240\(3),
      O => \p_0_in__4\(4)
    );
\gen_track_left_edge[1].pb_cnt_eye_size_r[1][4]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"1111111111111110"
    )
        port map (
      I0 => \FSM_onehot_cal1_state_r[34]_i_4_n_0\,
      I1 => pb_detect_edge_done_r(1),
      I2 => p_0_in16_in,
      I3 => p_1_in17_in,
      I4 => p_0_in103_in,
      I5 => samp_cnt_done_r_reg_n_0,
      O => \gen_track_left_edge[1].pb_cnt_eye_size_r[1][4]_i_4_n_0\
    );
\gen_track_left_edge[1].pb_cnt_eye_size_r[1][4]_i_5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00008000"
    )
        port map (
      I0 => \gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1]_240\(2),
      I1 => \gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1]_240\(0),
      I2 => \gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1]_240\(1),
      I3 => \gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1]_240\(3),
      I4 => \gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1]_240\(4),
      O => \gen_track_left_edge[1].pb_cnt_eye_size_r[1][4]_i_5_n_0\
    );
\gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1][0]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => \gen_track_left_edge[1].pb_cnt_eye_size_r[1][4]_i_2_n_0\,
      D => \p_0_in__4\(0),
      Q => \gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1]_240\(0),
      R => \gen_track_left_edge[1].pb_cnt_eye_size_r[1][4]_i_1_n_0\
    );
\gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1][1]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => \gen_track_left_edge[1].pb_cnt_eye_size_r[1][4]_i_2_n_0\,
      D => \p_0_in__4\(1),
      Q => \gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1]_240\(1),
      R => \gen_track_left_edge[1].pb_cnt_eye_size_r[1][4]_i_1_n_0\
    );
\gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1][2]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => \gen_track_left_edge[1].pb_cnt_eye_size_r[1][4]_i_2_n_0\,
      D => \p_0_in__4\(2),
      Q => \gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1]_240\(2),
      R => \gen_track_left_edge[1].pb_cnt_eye_size_r[1][4]_i_1_n_0\
    );
\gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1][3]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => \gen_track_left_edge[1].pb_cnt_eye_size_r[1][4]_i_2_n_0\,
      D => \p_0_in__4\(3),
      Q => \gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1]_240\(3),
      R => \gen_track_left_edge[1].pb_cnt_eye_size_r[1][4]_i_1_n_0\
    );
\gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1][4]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => \gen_track_left_edge[1].pb_cnt_eye_size_r[1][4]_i_2_n_0\,
      D => \p_0_in__4\(4),
      Q => \gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1]_240\(4),
      R => \gen_track_left_edge[1].pb_cnt_eye_size_r[1][4]_i_1_n_0\
    );
\gen_track_left_edge[1].pb_detect_edge_done_r[1]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"EEEEEEE0"
    )
        port map (
      I0 => store_sr_req_pulsed_r,
      I1 => p_34_in,
      I2 => p_0_in103_in,
      I3 => samp_cnt_done_r_reg_n_0,
      I4 => pb_detect_edge_done_r(1),
      O => \gen_track_left_edge[1].pb_detect_edge_done_r[1]_i_1_n_0\
    );
\gen_track_left_edge[1].pb_detect_edge_done_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_track_left_edge[1].pb_detect_edge_done_r[1]_i_1_n_0\,
      Q => pb_detect_edge_done_r(1),
      R => \FSM_onehot_cal1_state_r_reg_n_0_[16]\
    );
\gen_track_left_edge[1].pb_found_edge_r[1]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"5501550155005501"
    )
        port map (
      I0 => \FSM_onehot_cal1_state_r[34]_i_4_n_0\,
      I1 => pb_detect_edge_done_r(1),
      I2 => \gen_track_left_edge[1].pb_found_edge_r[1]_i_2_n_0\,
      I3 => \gen_track_left_edge[1].pb_found_edge_r_reg_n_0_[1]\,
      I4 => samp_cnt_done_r_reg_n_0,
      I5 => p_0_in16_in,
      O => \gen_track_left_edge[1].pb_found_edge_r[1]_i_1_n_0\
    );
\gen_track_left_edge[1].pb_found_edge_r[1]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0001"
    )
        port map (
      I0 => samp_cnt_done_r_reg_n_0,
      I1 => p_0_in103_in,
      I2 => p_1_in17_in,
      I3 => p_0_in16_in,
      O => \gen_track_left_edge[1].pb_found_edge_r[1]_i_2_n_0\
    );
\gen_track_left_edge[1].pb_found_edge_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_track_left_edge[1].pb_found_edge_r[1]_i_1_n_0\,
      Q => \gen_track_left_edge[1].pb_found_edge_r_reg_n_0_[1]\,
      R => \FSM_onehot_cal1_state_r_reg_n_0_[16]\
    );
\gen_track_left_edge[1].pb_found_stable_eye_r[1]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"55555F5500000800"
    )
        port map (
      I0 => \gen_track_left_edge[1].pb_cnt_eye_size_r[1][4]_i_4_n_0\,
      I1 => \gen_track_left_edge[1].pb_cnt_eye_size_r[1][4]_i_5_n_0\,
      I2 => \gen_track_left_edge[1].pb_found_edge_r_reg_n_0_[1]\,
      I3 => samp_cnt_done_r_reg_n_0,
      I4 => p_0_in16_in,
      I5 => pb_found_stable_eye_r(1),
      O => \gen_track_left_edge[1].pb_found_stable_eye_r[1]_i_1_n_0\
    );
\gen_track_left_edge[1].pb_found_stable_eye_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_track_left_edge[1].pb_found_stable_eye_r[1]_i_1_n_0\,
      Q => pb_found_stable_eye_r(1),
      R => \FSM_onehot_cal1_state_r_reg_n_0_[16]\
    );
\gen_track_left_edge[1].pb_last_tap_jitter_r[1]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000FDFD0100"
    )
        port map (
      I0 => samp_cnt_done_r_reg_n_0,
      I1 => pb_detect_edge_done_r(1),
      I2 => \FSM_onehot_cal1_state_r[34]_i_4_n_0\,
      I3 => p_0_in103_in,
      I4 => p_0_in16_in,
      I5 => \FSM_onehot_cal1_state_r_reg_n_0_[16]\,
      O => \gen_track_left_edge[1].pb_last_tap_jitter_r[1]_i_1_n_0\
    );
\gen_track_left_edge[1].pb_last_tap_jitter_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_track_left_edge[1].pb_last_tap_jitter_r[1]_i_1_n_0\,
      Q => p_0_in16_in,
      R => '0'
    );
\gen_track_left_edge[2].pb_cnt_eye_size_r[2][0]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2]_241\(0),
      O => \p_0_in__5\(0)
    );
\gen_track_left_edge[2].pb_cnt_eye_size_r[2][1]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2]_241\(1),
      I1 => \gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2]_241\(0),
      O => \p_0_in__5\(1)
    );
\gen_track_left_edge[2].pb_cnt_eye_size_r[2][2]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"6A"
    )
        port map (
      I0 => \gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2]_241\(2),
      I1 => \gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2]_241\(0),
      I2 => \gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2]_241\(1),
      O => \p_0_in__5\(2)
    );
\gen_track_left_edge[2].pb_cnt_eye_size_r[2][3]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6AAA"
    )
        port map (
      I0 => \gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2]_241\(3),
      I1 => \gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2]_241\(1),
      I2 => \gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2]_241\(0),
      I3 => \gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2]_241\(2),
      O => \p_0_in__5\(3)
    );
\gen_track_left_edge[2].pb_cnt_eye_size_r[2][4]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFEFAAAA"
    )
        port map (
      I0 => \FSM_onehot_cal1_state_r_reg_n_0_[16]\,
      I1 => \gen_track_left_edge[2].pb_found_edge_r_reg_n_0_[2]\,
      I2 => samp_cnt_done_r_reg_n_0,
      I3 => p_0_in13_in,
      I4 => \gen_track_left_edge[2].pb_cnt_eye_size_r[2][4]_i_4_n_0\,
      O => \gen_track_left_edge[2].pb_cnt_eye_size_r[2][4]_i_1_n_0\
    );
\gen_track_left_edge[2].pb_cnt_eye_size_r[2][4]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"11100000"
    )
        port map (
      I0 => \gen_track_left_edge[2].pb_cnt_eye_size_r[2][4]_i_5_n_0\,
      I1 => pb_detect_edge_done_r(2),
      I2 => store_sr_req_pulsed_r,
      I3 => p_34_in,
      I4 => samp_cnt_done_r_reg_n_0,
      O => \gen_track_left_edge[2].pb_cnt_eye_size_r[2][4]_i_2_n_0\
    );
\gen_track_left_edge[2].pb_cnt_eye_size_r[2][4]_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"6AAAAAAA"
    )
        port map (
      I0 => \gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2]_241\(4),
      I1 => \gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2]_241\(2),
      I2 => \gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2]_241\(0),
      I3 => \gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2]_241\(1),
      I4 => \gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2]_241\(3),
      O => \p_0_in__5\(4)
    );
\gen_track_left_edge[2].pb_cnt_eye_size_r[2][4]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"1111111111111110"
    )
        port map (
      I0 => \FSM_onehot_cal1_state_r[34]_i_4_n_0\,
      I1 => pb_detect_edge_done_r(2),
      I2 => p_0_in13_in,
      I3 => p_1_in14_in,
      I4 => p_0_in100_in,
      I5 => samp_cnt_done_r_reg_n_0,
      O => \gen_track_left_edge[2].pb_cnt_eye_size_r[2][4]_i_4_n_0\
    );
\gen_track_left_edge[2].pb_cnt_eye_size_r[2][4]_i_5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00008000"
    )
        port map (
      I0 => \gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2]_241\(2),
      I1 => \gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2]_241\(0),
      I2 => \gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2]_241\(1),
      I3 => \gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2]_241\(3),
      I4 => \gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2]_241\(4),
      O => \gen_track_left_edge[2].pb_cnt_eye_size_r[2][4]_i_5_n_0\
    );
\gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2][0]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => \gen_track_left_edge[2].pb_cnt_eye_size_r[2][4]_i_2_n_0\,
      D => \p_0_in__5\(0),
      Q => \gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2]_241\(0),
      R => \gen_track_left_edge[2].pb_cnt_eye_size_r[2][4]_i_1_n_0\
    );
\gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2][1]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => \gen_track_left_edge[2].pb_cnt_eye_size_r[2][4]_i_2_n_0\,
      D => \p_0_in__5\(1),
      Q => \gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2]_241\(1),
      R => \gen_track_left_edge[2].pb_cnt_eye_size_r[2][4]_i_1_n_0\
    );
\gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2][2]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => \gen_track_left_edge[2].pb_cnt_eye_size_r[2][4]_i_2_n_0\,
      D => \p_0_in__5\(2),
      Q => \gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2]_241\(2),
      R => \gen_track_left_edge[2].pb_cnt_eye_size_r[2][4]_i_1_n_0\
    );
\gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2][3]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => \gen_track_left_edge[2].pb_cnt_eye_size_r[2][4]_i_2_n_0\,
      D => \p_0_in__5\(3),
      Q => \gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2]_241\(3),
      R => \gen_track_left_edge[2].pb_cnt_eye_size_r[2][4]_i_1_n_0\
    );
\gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2][4]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => \gen_track_left_edge[2].pb_cnt_eye_size_r[2][4]_i_2_n_0\,
      D => \p_0_in__5\(4),
      Q => \gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2]_241\(4),
      R => \gen_track_left_edge[2].pb_cnt_eye_size_r[2][4]_i_1_n_0\
    );
\gen_track_left_edge[2].pb_detect_edge_done_r[2]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"EEEEEEE0"
    )
        port map (
      I0 => store_sr_req_pulsed_r,
      I1 => p_34_in,
      I2 => p_0_in100_in,
      I3 => samp_cnt_done_r_reg_n_0,
      I4 => pb_detect_edge_done_r(2),
      O => \gen_track_left_edge[2].pb_detect_edge_done_r[2]_i_1_n_0\
    );
\gen_track_left_edge[2].pb_detect_edge_done_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_track_left_edge[2].pb_detect_edge_done_r[2]_i_1_n_0\,
      Q => pb_detect_edge_done_r(2),
      R => \FSM_onehot_cal1_state_r_reg_n_0_[16]\
    );
\gen_track_left_edge[2].pb_found_edge_r[2]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"5501550155005501"
    )
        port map (
      I0 => \FSM_onehot_cal1_state_r[34]_i_4_n_0\,
      I1 => pb_detect_edge_done_r(2),
      I2 => \gen_track_left_edge[2].pb_found_edge_r[2]_i_2_n_0\,
      I3 => \gen_track_left_edge[2].pb_found_edge_r_reg_n_0_[2]\,
      I4 => samp_cnt_done_r_reg_n_0,
      I5 => p_0_in13_in,
      O => \gen_track_left_edge[2].pb_found_edge_r[2]_i_1_n_0\
    );
\gen_track_left_edge[2].pb_found_edge_r[2]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0001"
    )
        port map (
      I0 => samp_cnt_done_r_reg_n_0,
      I1 => p_0_in100_in,
      I2 => p_1_in14_in,
      I3 => p_0_in13_in,
      O => \gen_track_left_edge[2].pb_found_edge_r[2]_i_2_n_0\
    );
\gen_track_left_edge[2].pb_found_edge_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_track_left_edge[2].pb_found_edge_r[2]_i_1_n_0\,
      Q => \gen_track_left_edge[2].pb_found_edge_r_reg_n_0_[2]\,
      R => \FSM_onehot_cal1_state_r_reg_n_0_[16]\
    );
\gen_track_left_edge[2].pb_found_stable_eye_r[2]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"55555F5500000800"
    )
        port map (
      I0 => \gen_track_left_edge[2].pb_cnt_eye_size_r[2][4]_i_4_n_0\,
      I1 => \gen_track_left_edge[2].pb_cnt_eye_size_r[2][4]_i_5_n_0\,
      I2 => \gen_track_left_edge[2].pb_found_edge_r_reg_n_0_[2]\,
      I3 => samp_cnt_done_r_reg_n_0,
      I4 => p_0_in13_in,
      I5 => pb_found_stable_eye_r(2),
      O => \gen_track_left_edge[2].pb_found_stable_eye_r[2]_i_1_n_0\
    );
\gen_track_left_edge[2].pb_found_stable_eye_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_track_left_edge[2].pb_found_stable_eye_r[2]_i_1_n_0\,
      Q => pb_found_stable_eye_r(2),
      R => \FSM_onehot_cal1_state_r_reg_n_0_[16]\
    );
\gen_track_left_edge[2].pb_last_tap_jitter_r[2]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000FDFD0100"
    )
        port map (
      I0 => samp_cnt_done_r_reg_n_0,
      I1 => pb_detect_edge_done_r(2),
      I2 => \FSM_onehot_cal1_state_r[34]_i_4_n_0\,
      I3 => p_0_in100_in,
      I4 => p_0_in13_in,
      I5 => \FSM_onehot_cal1_state_r_reg_n_0_[16]\,
      O => \gen_track_left_edge[2].pb_last_tap_jitter_r[2]_i_1_n_0\
    );
\gen_track_left_edge[2].pb_last_tap_jitter_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_track_left_edge[2].pb_last_tap_jitter_r[2]_i_1_n_0\,
      Q => p_0_in13_in,
      R => '0'
    );
\gen_track_left_edge[3].pb_cnt_eye_size_r[3][0]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3]_242\(0),
      O => \p_0_in__6\(0)
    );
\gen_track_left_edge[3].pb_cnt_eye_size_r[3][1]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3]_242\(1),
      I1 => \gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3]_242\(0),
      O => \p_0_in__6\(1)
    );
\gen_track_left_edge[3].pb_cnt_eye_size_r[3][2]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"6A"
    )
        port map (
      I0 => \gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3]_242\(2),
      I1 => \gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3]_242\(0),
      I2 => \gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3]_242\(1),
      O => \p_0_in__6\(2)
    );
\gen_track_left_edge[3].pb_cnt_eye_size_r[3][3]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6AAA"
    )
        port map (
      I0 => \gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3]_242\(3),
      I1 => \gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3]_242\(1),
      I2 => \gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3]_242\(0),
      I3 => \gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3]_242\(2),
      O => \p_0_in__6\(3)
    );
\gen_track_left_edge[3].pb_cnt_eye_size_r[3][4]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFEFAAAA"
    )
        port map (
      I0 => \FSM_onehot_cal1_state_r_reg_n_0_[16]\,
      I1 => \gen_track_left_edge[3].pb_found_edge_r_reg_n_0_[3]\,
      I2 => samp_cnt_done_r_reg_n_0,
      I3 => p_0_in10_in,
      I4 => \gen_track_left_edge[3].pb_cnt_eye_size_r[3][4]_i_4_n_0\,
      O => \gen_track_left_edge[3].pb_cnt_eye_size_r[3][4]_i_1_n_0\
    );
\gen_track_left_edge[3].pb_cnt_eye_size_r[3][4]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"11100000"
    )
        port map (
      I0 => \gen_track_left_edge[3].pb_cnt_eye_size_r[3][4]_i_5_n_0\,
      I1 => pb_detect_edge_done_r(3),
      I2 => store_sr_req_pulsed_r,
      I3 => p_34_in,
      I4 => samp_cnt_done_r_reg_n_0,
      O => \gen_track_left_edge[3].pb_cnt_eye_size_r[3][4]_i_2_n_0\
    );
\gen_track_left_edge[3].pb_cnt_eye_size_r[3][4]_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"6AAAAAAA"
    )
        port map (
      I0 => \gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3]_242\(4),
      I1 => \gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3]_242\(2),
      I2 => \gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3]_242\(0),
      I3 => \gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3]_242\(1),
      I4 => \gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3]_242\(3),
      O => \p_0_in__6\(4)
    );
\gen_track_left_edge[3].pb_cnt_eye_size_r[3][4]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"1111111111111110"
    )
        port map (
      I0 => \FSM_onehot_cal1_state_r[34]_i_4_n_0\,
      I1 => pb_detect_edge_done_r(3),
      I2 => p_0_in10_in,
      I3 => p_1_in11_in,
      I4 => p_0_in97_in,
      I5 => samp_cnt_done_r_reg_n_0,
      O => \gen_track_left_edge[3].pb_cnt_eye_size_r[3][4]_i_4_n_0\
    );
\gen_track_left_edge[3].pb_cnt_eye_size_r[3][4]_i_5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00008000"
    )
        port map (
      I0 => \gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3]_242\(2),
      I1 => \gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3]_242\(0),
      I2 => \gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3]_242\(1),
      I3 => \gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3]_242\(3),
      I4 => \gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3]_242\(4),
      O => \gen_track_left_edge[3].pb_cnt_eye_size_r[3][4]_i_5_n_0\
    );
\gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3][0]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => \gen_track_left_edge[3].pb_cnt_eye_size_r[3][4]_i_2_n_0\,
      D => \p_0_in__6\(0),
      Q => \gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3]_242\(0),
      R => \gen_track_left_edge[3].pb_cnt_eye_size_r[3][4]_i_1_n_0\
    );
\gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3][1]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => \gen_track_left_edge[3].pb_cnt_eye_size_r[3][4]_i_2_n_0\,
      D => \p_0_in__6\(1),
      Q => \gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3]_242\(1),
      R => \gen_track_left_edge[3].pb_cnt_eye_size_r[3][4]_i_1_n_0\
    );
\gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3][2]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => \gen_track_left_edge[3].pb_cnt_eye_size_r[3][4]_i_2_n_0\,
      D => \p_0_in__6\(2),
      Q => \gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3]_242\(2),
      R => \gen_track_left_edge[3].pb_cnt_eye_size_r[3][4]_i_1_n_0\
    );
\gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3][3]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => \gen_track_left_edge[3].pb_cnt_eye_size_r[3][4]_i_2_n_0\,
      D => \p_0_in__6\(3),
      Q => \gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3]_242\(3),
      R => \gen_track_left_edge[3].pb_cnt_eye_size_r[3][4]_i_1_n_0\
    );
\gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3][4]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => \gen_track_left_edge[3].pb_cnt_eye_size_r[3][4]_i_2_n_0\,
      D => \p_0_in__6\(4),
      Q => \gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3]_242\(4),
      R => \gen_track_left_edge[3].pb_cnt_eye_size_r[3][4]_i_1_n_0\
    );
\gen_track_left_edge[3].pb_detect_edge_done_r[3]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"EEEEEEE0"
    )
        port map (
      I0 => store_sr_req_pulsed_r,
      I1 => p_34_in,
      I2 => p_0_in97_in,
      I3 => samp_cnt_done_r_reg_n_0,
      I4 => pb_detect_edge_done_r(3),
      O => \gen_track_left_edge[3].pb_detect_edge_done_r[3]_i_1_n_0\
    );
\gen_track_left_edge[3].pb_detect_edge_done_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_track_left_edge[3].pb_detect_edge_done_r[3]_i_1_n_0\,
      Q => pb_detect_edge_done_r(3),
      R => \FSM_onehot_cal1_state_r_reg_n_0_[16]\
    );
\gen_track_left_edge[3].pb_found_edge_r[3]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"5501550155005501"
    )
        port map (
      I0 => \FSM_onehot_cal1_state_r[34]_i_4_n_0\,
      I1 => pb_detect_edge_done_r(3),
      I2 => \gen_track_left_edge[3].pb_found_edge_r[3]_i_2_n_0\,
      I3 => \gen_track_left_edge[3].pb_found_edge_r_reg_n_0_[3]\,
      I4 => samp_cnt_done_r_reg_n_0,
      I5 => p_0_in10_in,
      O => \gen_track_left_edge[3].pb_found_edge_r[3]_i_1_n_0\
    );
\gen_track_left_edge[3].pb_found_edge_r[3]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0001"
    )
        port map (
      I0 => samp_cnt_done_r_reg_n_0,
      I1 => p_0_in97_in,
      I2 => p_1_in11_in,
      I3 => p_0_in10_in,
      O => \gen_track_left_edge[3].pb_found_edge_r[3]_i_2_n_0\
    );
\gen_track_left_edge[3].pb_found_edge_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_track_left_edge[3].pb_found_edge_r[3]_i_1_n_0\,
      Q => \gen_track_left_edge[3].pb_found_edge_r_reg_n_0_[3]\,
      R => \FSM_onehot_cal1_state_r_reg_n_0_[16]\
    );
\gen_track_left_edge[3].pb_found_stable_eye_r[3]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"55555F5500000800"
    )
        port map (
      I0 => \gen_track_left_edge[3].pb_cnt_eye_size_r[3][4]_i_4_n_0\,
      I1 => \gen_track_left_edge[3].pb_cnt_eye_size_r[3][4]_i_5_n_0\,
      I2 => \gen_track_left_edge[3].pb_found_edge_r_reg_n_0_[3]\,
      I3 => samp_cnt_done_r_reg_n_0,
      I4 => p_0_in10_in,
      I5 => pb_found_stable_eye_r(3),
      O => \gen_track_left_edge[3].pb_found_stable_eye_r[3]_i_1_n_0\
    );
\gen_track_left_edge[3].pb_found_stable_eye_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_track_left_edge[3].pb_found_stable_eye_r[3]_i_1_n_0\,
      Q => pb_found_stable_eye_r(3),
      R => \FSM_onehot_cal1_state_r_reg_n_0_[16]\
    );
\gen_track_left_edge[3].pb_last_tap_jitter_r[3]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000FDFD0100"
    )
        port map (
      I0 => samp_cnt_done_r_reg_n_0,
      I1 => pb_detect_edge_done_r(3),
      I2 => \FSM_onehot_cal1_state_r[34]_i_4_n_0\,
      I3 => p_0_in97_in,
      I4 => p_0_in10_in,
      I5 => \FSM_onehot_cal1_state_r_reg_n_0_[16]\,
      O => \gen_track_left_edge[3].pb_last_tap_jitter_r[3]_i_1_n_0\
    );
\gen_track_left_edge[3].pb_last_tap_jitter_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_track_left_edge[3].pb_last_tap_jitter_r[3]_i_1_n_0\,
      Q => p_0_in10_in,
      R => '0'
    );
\gen_track_left_edge[4].pb_cnt_eye_size_r[4][0]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4]_243\(0),
      O => \p_0_in__7\(0)
    );
\gen_track_left_edge[4].pb_cnt_eye_size_r[4][1]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4]_243\(1),
      I1 => \gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4]_243\(0),
      O => \p_0_in__7\(1)
    );
\gen_track_left_edge[4].pb_cnt_eye_size_r[4][2]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"6A"
    )
        port map (
      I0 => \gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4]_243\(2),
      I1 => \gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4]_243\(0),
      I2 => \gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4]_243\(1),
      O => \p_0_in__7\(2)
    );
\gen_track_left_edge[4].pb_cnt_eye_size_r[4][3]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6AAA"
    )
        port map (
      I0 => \gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4]_243\(3),
      I1 => \gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4]_243\(1),
      I2 => \gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4]_243\(0),
      I3 => \gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4]_243\(2),
      O => \p_0_in__7\(3)
    );
\gen_track_left_edge[4].pb_cnt_eye_size_r[4][4]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFEFAAAA"
    )
        port map (
      I0 => \FSM_onehot_cal1_state_r_reg_n_0_[16]\,
      I1 => \gen_track_left_edge[4].pb_found_edge_r_reg_n_0_[4]\,
      I2 => samp_cnt_done_r_reg_n_0,
      I3 => p_0_in7_in,
      I4 => \gen_track_left_edge[4].pb_cnt_eye_size_r[4][4]_i_4_n_0\,
      O => \gen_track_left_edge[4].pb_cnt_eye_size_r[4][4]_i_1_n_0\
    );
\gen_track_left_edge[4].pb_cnt_eye_size_r[4][4]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"11100000"
    )
        port map (
      I0 => \gen_track_left_edge[4].pb_cnt_eye_size_r[4][4]_i_5_n_0\,
      I1 => pb_detect_edge_done_r(4),
      I2 => store_sr_req_pulsed_r,
      I3 => p_34_in,
      I4 => samp_cnt_done_r_reg_n_0,
      O => \gen_track_left_edge[4].pb_cnt_eye_size_r[4][4]_i_2_n_0\
    );
\gen_track_left_edge[4].pb_cnt_eye_size_r[4][4]_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"6AAAAAAA"
    )
        port map (
      I0 => \gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4]_243\(4),
      I1 => \gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4]_243\(2),
      I2 => \gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4]_243\(0),
      I3 => \gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4]_243\(1),
      I4 => \gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4]_243\(3),
      O => \p_0_in__7\(4)
    );
\gen_track_left_edge[4].pb_cnt_eye_size_r[4][4]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"1111111111111110"
    )
        port map (
      I0 => \FSM_onehot_cal1_state_r[34]_i_4_n_0\,
      I1 => pb_detect_edge_done_r(4),
      I2 => p_0_in7_in,
      I3 => p_1_in8_in,
      I4 => p_0_in94_in,
      I5 => samp_cnt_done_r_reg_n_0,
      O => \gen_track_left_edge[4].pb_cnt_eye_size_r[4][4]_i_4_n_0\
    );
\gen_track_left_edge[4].pb_cnt_eye_size_r[4][4]_i_5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00008000"
    )
        port map (
      I0 => \gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4]_243\(2),
      I1 => \gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4]_243\(0),
      I2 => \gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4]_243\(1),
      I3 => \gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4]_243\(3),
      I4 => \gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4]_243\(4),
      O => \gen_track_left_edge[4].pb_cnt_eye_size_r[4][4]_i_5_n_0\
    );
\gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4][0]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => \gen_track_left_edge[4].pb_cnt_eye_size_r[4][4]_i_2_n_0\,
      D => \p_0_in__7\(0),
      Q => \gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4]_243\(0),
      R => \gen_track_left_edge[4].pb_cnt_eye_size_r[4][4]_i_1_n_0\
    );
\gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4][1]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => \gen_track_left_edge[4].pb_cnt_eye_size_r[4][4]_i_2_n_0\,
      D => \p_0_in__7\(1),
      Q => \gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4]_243\(1),
      R => \gen_track_left_edge[4].pb_cnt_eye_size_r[4][4]_i_1_n_0\
    );
\gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4][2]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => \gen_track_left_edge[4].pb_cnt_eye_size_r[4][4]_i_2_n_0\,
      D => \p_0_in__7\(2),
      Q => \gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4]_243\(2),
      R => \gen_track_left_edge[4].pb_cnt_eye_size_r[4][4]_i_1_n_0\
    );
\gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4][3]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => \gen_track_left_edge[4].pb_cnt_eye_size_r[4][4]_i_2_n_0\,
      D => \p_0_in__7\(3),
      Q => \gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4]_243\(3),
      R => \gen_track_left_edge[4].pb_cnt_eye_size_r[4][4]_i_1_n_0\
    );
\gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4][4]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => \gen_track_left_edge[4].pb_cnt_eye_size_r[4][4]_i_2_n_0\,
      D => \p_0_in__7\(4),
      Q => \gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4]_243\(4),
      R => \gen_track_left_edge[4].pb_cnt_eye_size_r[4][4]_i_1_n_0\
    );
\gen_track_left_edge[4].pb_detect_edge_done_r[4]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"EEEEEEE0"
    )
        port map (
      I0 => store_sr_req_pulsed_r,
      I1 => p_34_in,
      I2 => p_0_in94_in,
      I3 => samp_cnt_done_r_reg_n_0,
      I4 => pb_detect_edge_done_r(4),
      O => \gen_track_left_edge[4].pb_detect_edge_done_r[4]_i_1_n_0\
    );
\gen_track_left_edge[4].pb_detect_edge_done_r_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_track_left_edge[4].pb_detect_edge_done_r[4]_i_1_n_0\,
      Q => pb_detect_edge_done_r(4),
      R => \FSM_onehot_cal1_state_r_reg_n_0_[16]\
    );
\gen_track_left_edge[4].pb_found_edge_r[4]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"5501550155005501"
    )
        port map (
      I0 => \FSM_onehot_cal1_state_r[34]_i_4_n_0\,
      I1 => pb_detect_edge_done_r(4),
      I2 => \gen_track_left_edge[4].pb_found_edge_r[4]_i_2_n_0\,
      I3 => \gen_track_left_edge[4].pb_found_edge_r_reg_n_0_[4]\,
      I4 => samp_cnt_done_r_reg_n_0,
      I5 => p_0_in7_in,
      O => \gen_track_left_edge[4].pb_found_edge_r[4]_i_1_n_0\
    );
\gen_track_left_edge[4].pb_found_edge_r[4]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0001"
    )
        port map (
      I0 => samp_cnt_done_r_reg_n_0,
      I1 => p_0_in94_in,
      I2 => p_1_in8_in,
      I3 => p_0_in7_in,
      O => \gen_track_left_edge[4].pb_found_edge_r[4]_i_2_n_0\
    );
\gen_track_left_edge[4].pb_found_edge_r_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_track_left_edge[4].pb_found_edge_r[4]_i_1_n_0\,
      Q => \gen_track_left_edge[4].pb_found_edge_r_reg_n_0_[4]\,
      R => \FSM_onehot_cal1_state_r_reg_n_0_[16]\
    );
\gen_track_left_edge[4].pb_found_stable_eye_r[4]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"55555F5500000800"
    )
        port map (
      I0 => \gen_track_left_edge[4].pb_cnt_eye_size_r[4][4]_i_4_n_0\,
      I1 => \gen_track_left_edge[4].pb_cnt_eye_size_r[4][4]_i_5_n_0\,
      I2 => \gen_track_left_edge[4].pb_found_edge_r_reg_n_0_[4]\,
      I3 => samp_cnt_done_r_reg_n_0,
      I4 => p_0_in7_in,
      I5 => pb_found_stable_eye_r(4),
      O => \gen_track_left_edge[4].pb_found_stable_eye_r[4]_i_1_n_0\
    );
\gen_track_left_edge[4].pb_found_stable_eye_r_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_track_left_edge[4].pb_found_stable_eye_r[4]_i_1_n_0\,
      Q => pb_found_stable_eye_r(4),
      R => \FSM_onehot_cal1_state_r_reg_n_0_[16]\
    );
\gen_track_left_edge[4].pb_last_tap_jitter_r[4]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000FDFD0100"
    )
        port map (
      I0 => samp_cnt_done_r_reg_n_0,
      I1 => pb_detect_edge_done_r(4),
      I2 => \FSM_onehot_cal1_state_r[34]_i_4_n_0\,
      I3 => p_0_in94_in,
      I4 => p_0_in7_in,
      I5 => \FSM_onehot_cal1_state_r_reg_n_0_[16]\,
      O => \gen_track_left_edge[4].pb_last_tap_jitter_r[4]_i_1_n_0\
    );
\gen_track_left_edge[4].pb_last_tap_jitter_r_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_track_left_edge[4].pb_last_tap_jitter_r[4]_i_1_n_0\,
      Q => p_0_in7_in,
      R => '0'
    );
\gen_track_left_edge[5].pb_cnt_eye_size_r[5][0]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5]_244\(0),
      O => \p_0_in__8\(0)
    );
\gen_track_left_edge[5].pb_cnt_eye_size_r[5][1]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5]_244\(1),
      I1 => \gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5]_244\(0),
      O => \p_0_in__8\(1)
    );
\gen_track_left_edge[5].pb_cnt_eye_size_r[5][2]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"6A"
    )
        port map (
      I0 => \gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5]_244\(2),
      I1 => \gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5]_244\(0),
      I2 => \gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5]_244\(1),
      O => \p_0_in__8\(2)
    );
\gen_track_left_edge[5].pb_cnt_eye_size_r[5][3]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6AAA"
    )
        port map (
      I0 => \gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5]_244\(3),
      I1 => \gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5]_244\(1),
      I2 => \gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5]_244\(0),
      I3 => \gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5]_244\(2),
      O => \p_0_in__8\(3)
    );
\gen_track_left_edge[5].pb_cnt_eye_size_r[5][4]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFEFAAAA"
    )
        port map (
      I0 => \FSM_onehot_cal1_state_r_reg_n_0_[16]\,
      I1 => \gen_track_left_edge[5].pb_found_edge_r_reg_n_0_[5]\,
      I2 => samp_cnt_done_r_reg_n_0,
      I3 => p_0_in4_in,
      I4 => \gen_track_left_edge[5].pb_cnt_eye_size_r[5][4]_i_4_n_0\,
      O => \gen_track_left_edge[5].pb_cnt_eye_size_r[5][4]_i_1_n_0\
    );
\gen_track_left_edge[5].pb_cnt_eye_size_r[5][4]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"11100000"
    )
        port map (
      I0 => \gen_track_left_edge[5].pb_cnt_eye_size_r[5][4]_i_5_n_0\,
      I1 => pb_detect_edge_done_r(5),
      I2 => store_sr_req_pulsed_r,
      I3 => p_34_in,
      I4 => samp_cnt_done_r_reg_n_0,
      O => \gen_track_left_edge[5].pb_cnt_eye_size_r[5][4]_i_2_n_0\
    );
\gen_track_left_edge[5].pb_cnt_eye_size_r[5][4]_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"6AAAAAAA"
    )
        port map (
      I0 => \gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5]_244\(4),
      I1 => \gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5]_244\(2),
      I2 => \gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5]_244\(0),
      I3 => \gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5]_244\(1),
      I4 => \gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5]_244\(3),
      O => \p_0_in__8\(4)
    );
\gen_track_left_edge[5].pb_cnt_eye_size_r[5][4]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"1111111111111110"
    )
        port map (
      I0 => \FSM_onehot_cal1_state_r[34]_i_4_n_0\,
      I1 => pb_detect_edge_done_r(5),
      I2 => p_0_in4_in,
      I3 => p_1_in5_in,
      I4 => p_0_in91_in,
      I5 => samp_cnt_done_r_reg_n_0,
      O => \gen_track_left_edge[5].pb_cnt_eye_size_r[5][4]_i_4_n_0\
    );
\gen_track_left_edge[5].pb_cnt_eye_size_r[5][4]_i_5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00008000"
    )
        port map (
      I0 => \gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5]_244\(2),
      I1 => \gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5]_244\(0),
      I2 => \gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5]_244\(1),
      I3 => \gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5]_244\(3),
      I4 => \gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5]_244\(4),
      O => \gen_track_left_edge[5].pb_cnt_eye_size_r[5][4]_i_5_n_0\
    );
\gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5][0]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => \gen_track_left_edge[5].pb_cnt_eye_size_r[5][4]_i_2_n_0\,
      D => \p_0_in__8\(0),
      Q => \gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5]_244\(0),
      R => \gen_track_left_edge[5].pb_cnt_eye_size_r[5][4]_i_1_n_0\
    );
\gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5][1]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => \gen_track_left_edge[5].pb_cnt_eye_size_r[5][4]_i_2_n_0\,
      D => \p_0_in__8\(1),
      Q => \gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5]_244\(1),
      R => \gen_track_left_edge[5].pb_cnt_eye_size_r[5][4]_i_1_n_0\
    );
\gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5][2]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => \gen_track_left_edge[5].pb_cnt_eye_size_r[5][4]_i_2_n_0\,
      D => \p_0_in__8\(2),
      Q => \gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5]_244\(2),
      R => \gen_track_left_edge[5].pb_cnt_eye_size_r[5][4]_i_1_n_0\
    );
\gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5][3]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => \gen_track_left_edge[5].pb_cnt_eye_size_r[5][4]_i_2_n_0\,
      D => \p_0_in__8\(3),
      Q => \gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5]_244\(3),
      R => \gen_track_left_edge[5].pb_cnt_eye_size_r[5][4]_i_1_n_0\
    );
\gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5][4]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => \gen_track_left_edge[5].pb_cnt_eye_size_r[5][4]_i_2_n_0\,
      D => \p_0_in__8\(4),
      Q => \gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5]_244\(4),
      R => \gen_track_left_edge[5].pb_cnt_eye_size_r[5][4]_i_1_n_0\
    );
\gen_track_left_edge[5].pb_detect_edge_done_r[5]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"EEEEEEE0"
    )
        port map (
      I0 => store_sr_req_pulsed_r,
      I1 => p_34_in,
      I2 => p_0_in91_in,
      I3 => samp_cnt_done_r_reg_n_0,
      I4 => pb_detect_edge_done_r(5),
      O => \gen_track_left_edge[5].pb_detect_edge_done_r[5]_i_1_n_0\
    );
\gen_track_left_edge[5].pb_detect_edge_done_r_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_track_left_edge[5].pb_detect_edge_done_r[5]_i_1_n_0\,
      Q => pb_detect_edge_done_r(5),
      R => \FSM_onehot_cal1_state_r_reg_n_0_[16]\
    );
\gen_track_left_edge[5].pb_found_edge_r[5]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"5501550155005501"
    )
        port map (
      I0 => \FSM_onehot_cal1_state_r[34]_i_4_n_0\,
      I1 => pb_detect_edge_done_r(5),
      I2 => \gen_track_left_edge[5].pb_found_edge_r[5]_i_2_n_0\,
      I3 => \gen_track_left_edge[5].pb_found_edge_r_reg_n_0_[5]\,
      I4 => samp_cnt_done_r_reg_n_0,
      I5 => p_0_in4_in,
      O => \gen_track_left_edge[5].pb_found_edge_r[5]_i_1_n_0\
    );
\gen_track_left_edge[5].pb_found_edge_r[5]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0001"
    )
        port map (
      I0 => samp_cnt_done_r_reg_n_0,
      I1 => p_0_in91_in,
      I2 => p_1_in5_in,
      I3 => p_0_in4_in,
      O => \gen_track_left_edge[5].pb_found_edge_r[5]_i_2_n_0\
    );
\gen_track_left_edge[5].pb_found_edge_r_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_track_left_edge[5].pb_found_edge_r[5]_i_1_n_0\,
      Q => \gen_track_left_edge[5].pb_found_edge_r_reg_n_0_[5]\,
      R => \FSM_onehot_cal1_state_r_reg_n_0_[16]\
    );
\gen_track_left_edge[5].pb_found_stable_eye_r[5]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"55555F5500000800"
    )
        port map (
      I0 => \gen_track_left_edge[5].pb_cnt_eye_size_r[5][4]_i_4_n_0\,
      I1 => \gen_track_left_edge[5].pb_cnt_eye_size_r[5][4]_i_5_n_0\,
      I2 => \gen_track_left_edge[5].pb_found_edge_r_reg_n_0_[5]\,
      I3 => samp_cnt_done_r_reg_n_0,
      I4 => p_0_in4_in,
      I5 => pb_found_stable_eye_r(5),
      O => \gen_track_left_edge[5].pb_found_stable_eye_r[5]_i_1_n_0\
    );
\gen_track_left_edge[5].pb_found_stable_eye_r_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_track_left_edge[5].pb_found_stable_eye_r[5]_i_1_n_0\,
      Q => pb_found_stable_eye_r(5),
      R => \FSM_onehot_cal1_state_r_reg_n_0_[16]\
    );
\gen_track_left_edge[5].pb_last_tap_jitter_r[5]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000FDFD0100"
    )
        port map (
      I0 => samp_cnt_done_r_reg_n_0,
      I1 => pb_detect_edge_done_r(5),
      I2 => \FSM_onehot_cal1_state_r[34]_i_4_n_0\,
      I3 => p_0_in91_in,
      I4 => p_0_in4_in,
      I5 => \FSM_onehot_cal1_state_r_reg_n_0_[16]\,
      O => \gen_track_left_edge[5].pb_last_tap_jitter_r[5]_i_1_n_0\
    );
\gen_track_left_edge[5].pb_last_tap_jitter_r_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_track_left_edge[5].pb_last_tap_jitter_r[5]_i_1_n_0\,
      Q => p_0_in4_in,
      R => '0'
    );
\gen_track_left_edge[6].pb_cnt_eye_size_r[6][0]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6]_245\(0),
      O => \p_0_in__9\(0)
    );
\gen_track_left_edge[6].pb_cnt_eye_size_r[6][1]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6]_245\(1),
      I1 => \gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6]_245\(0),
      O => \p_0_in__9\(1)
    );
\gen_track_left_edge[6].pb_cnt_eye_size_r[6][2]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"6A"
    )
        port map (
      I0 => \gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6]_245\(2),
      I1 => \gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6]_245\(0),
      I2 => \gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6]_245\(1),
      O => \p_0_in__9\(2)
    );
\gen_track_left_edge[6].pb_cnt_eye_size_r[6][3]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6AAA"
    )
        port map (
      I0 => \gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6]_245\(3),
      I1 => \gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6]_245\(1),
      I2 => \gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6]_245\(0),
      I3 => \gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6]_245\(2),
      O => \p_0_in__9\(3)
    );
\gen_track_left_edge[6].pb_cnt_eye_size_r[6][4]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFEFAAAA"
    )
        port map (
      I0 => \FSM_onehot_cal1_state_r_reg_n_0_[16]\,
      I1 => \gen_track_left_edge[6].pb_found_edge_r_reg_n_0_[6]\,
      I2 => samp_cnt_done_r_reg_n_0,
      I3 => p_0_in1_in,
      I4 => \gen_track_left_edge[6].pb_cnt_eye_size_r[6][4]_i_4_n_0\,
      O => \gen_track_left_edge[6].pb_cnt_eye_size_r[6][4]_i_1_n_0\
    );
\gen_track_left_edge[6].pb_cnt_eye_size_r[6][4]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"11100000"
    )
        port map (
      I0 => \gen_track_left_edge[6].pb_cnt_eye_size_r[6][4]_i_5_n_0\,
      I1 => pb_detect_edge_done_r(6),
      I2 => store_sr_req_pulsed_r,
      I3 => p_34_in,
      I4 => samp_cnt_done_r_reg_n_0,
      O => \gen_track_left_edge[6].pb_cnt_eye_size_r[6][4]_i_2_n_0\
    );
\gen_track_left_edge[6].pb_cnt_eye_size_r[6][4]_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"6AAAAAAA"
    )
        port map (
      I0 => \gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6]_245\(4),
      I1 => \gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6]_245\(2),
      I2 => \gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6]_245\(0),
      I3 => \gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6]_245\(1),
      I4 => \gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6]_245\(3),
      O => \p_0_in__9\(4)
    );
\gen_track_left_edge[6].pb_cnt_eye_size_r[6][4]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"1111111111111110"
    )
        port map (
      I0 => \FSM_onehot_cal1_state_r[34]_i_4_n_0\,
      I1 => pb_detect_edge_done_r(6),
      I2 => p_0_in1_in,
      I3 => p_1_in2_in,
      I4 => p_0_in88_in,
      I5 => samp_cnt_done_r_reg_n_0,
      O => \gen_track_left_edge[6].pb_cnt_eye_size_r[6][4]_i_4_n_0\
    );
\gen_track_left_edge[6].pb_cnt_eye_size_r[6][4]_i_5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00008000"
    )
        port map (
      I0 => \gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6]_245\(2),
      I1 => \gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6]_245\(0),
      I2 => \gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6]_245\(1),
      I3 => \gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6]_245\(3),
      I4 => \gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6]_245\(4),
      O => \gen_track_left_edge[6].pb_cnt_eye_size_r[6][4]_i_5_n_0\
    );
\gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6][0]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => \gen_track_left_edge[6].pb_cnt_eye_size_r[6][4]_i_2_n_0\,
      D => \p_0_in__9\(0),
      Q => \gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6]_245\(0),
      R => \gen_track_left_edge[6].pb_cnt_eye_size_r[6][4]_i_1_n_0\
    );
\gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6][1]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => \gen_track_left_edge[6].pb_cnt_eye_size_r[6][4]_i_2_n_0\,
      D => \p_0_in__9\(1),
      Q => \gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6]_245\(1),
      R => \gen_track_left_edge[6].pb_cnt_eye_size_r[6][4]_i_1_n_0\
    );
\gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6][2]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => \gen_track_left_edge[6].pb_cnt_eye_size_r[6][4]_i_2_n_0\,
      D => \p_0_in__9\(2),
      Q => \gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6]_245\(2),
      R => \gen_track_left_edge[6].pb_cnt_eye_size_r[6][4]_i_1_n_0\
    );
\gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6][3]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => \gen_track_left_edge[6].pb_cnt_eye_size_r[6][4]_i_2_n_0\,
      D => \p_0_in__9\(3),
      Q => \gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6]_245\(3),
      R => \gen_track_left_edge[6].pb_cnt_eye_size_r[6][4]_i_1_n_0\
    );
\gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6][4]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => \gen_track_left_edge[6].pb_cnt_eye_size_r[6][4]_i_2_n_0\,
      D => \p_0_in__9\(4),
      Q => \gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6]_245\(4),
      R => \gen_track_left_edge[6].pb_cnt_eye_size_r[6][4]_i_1_n_0\
    );
\gen_track_left_edge[6].pb_detect_edge_done_r[6]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"EEEEEEE0"
    )
        port map (
      I0 => store_sr_req_pulsed_r,
      I1 => p_34_in,
      I2 => p_0_in88_in,
      I3 => samp_cnt_done_r_reg_n_0,
      I4 => pb_detect_edge_done_r(6),
      O => \gen_track_left_edge[6].pb_detect_edge_done_r[6]_i_1_n_0\
    );
\gen_track_left_edge[6].pb_detect_edge_done_r_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_track_left_edge[6].pb_detect_edge_done_r[6]_i_1_n_0\,
      Q => pb_detect_edge_done_r(6),
      R => \FSM_onehot_cal1_state_r_reg_n_0_[16]\
    );
\gen_track_left_edge[6].pb_found_edge_r[6]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"5501550155005501"
    )
        port map (
      I0 => \FSM_onehot_cal1_state_r[34]_i_4_n_0\,
      I1 => pb_detect_edge_done_r(6),
      I2 => \gen_track_left_edge[6].pb_found_edge_r[6]_i_2_n_0\,
      I3 => \gen_track_left_edge[6].pb_found_edge_r_reg_n_0_[6]\,
      I4 => samp_cnt_done_r_reg_n_0,
      I5 => p_0_in1_in,
      O => \gen_track_left_edge[6].pb_found_edge_r[6]_i_1_n_0\
    );
\gen_track_left_edge[6].pb_found_edge_r[6]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0001"
    )
        port map (
      I0 => samp_cnt_done_r_reg_n_0,
      I1 => p_0_in88_in,
      I2 => p_1_in2_in,
      I3 => p_0_in1_in,
      O => \gen_track_left_edge[6].pb_found_edge_r[6]_i_2_n_0\
    );
\gen_track_left_edge[6].pb_found_edge_r_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_track_left_edge[6].pb_found_edge_r[6]_i_1_n_0\,
      Q => \gen_track_left_edge[6].pb_found_edge_r_reg_n_0_[6]\,
      R => \FSM_onehot_cal1_state_r_reg_n_0_[16]\
    );
\gen_track_left_edge[6].pb_found_stable_eye_r[6]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"55555F5500000800"
    )
        port map (
      I0 => \gen_track_left_edge[6].pb_cnt_eye_size_r[6][4]_i_4_n_0\,
      I1 => \gen_track_left_edge[6].pb_cnt_eye_size_r[6][4]_i_5_n_0\,
      I2 => \gen_track_left_edge[6].pb_found_edge_r_reg_n_0_[6]\,
      I3 => samp_cnt_done_r_reg_n_0,
      I4 => p_0_in1_in,
      I5 => pb_found_stable_eye_r(6),
      O => \gen_track_left_edge[6].pb_found_stable_eye_r[6]_i_1_n_0\
    );
\gen_track_left_edge[6].pb_found_stable_eye_r_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_track_left_edge[6].pb_found_stable_eye_r[6]_i_1_n_0\,
      Q => pb_found_stable_eye_r(6),
      R => \FSM_onehot_cal1_state_r_reg_n_0_[16]\
    );
\gen_track_left_edge[6].pb_last_tap_jitter_r[6]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000FDFD0100"
    )
        port map (
      I0 => samp_cnt_done_r_reg_n_0,
      I1 => pb_detect_edge_done_r(6),
      I2 => \FSM_onehot_cal1_state_r[34]_i_4_n_0\,
      I3 => p_0_in88_in,
      I4 => p_0_in1_in,
      I5 => \FSM_onehot_cal1_state_r_reg_n_0_[16]\,
      O => \gen_track_left_edge[6].pb_last_tap_jitter_r[6]_i_1_n_0\
    );
\gen_track_left_edge[6].pb_last_tap_jitter_r_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_track_left_edge[6].pb_last_tap_jitter_r[6]_i_1_n_0\,
      Q => p_0_in1_in,
      R => '0'
    );
\gen_track_left_edge[7].pb_cnt_eye_size_r[7][0]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7]_246\(0),
      O => \p_0_in__10\(0)
    );
\gen_track_left_edge[7].pb_cnt_eye_size_r[7][1]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7]_246\(1),
      I1 => \gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7]_246\(0),
      O => \p_0_in__10\(1)
    );
\gen_track_left_edge[7].pb_cnt_eye_size_r[7][2]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"6A"
    )
        port map (
      I0 => \gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7]_246\(2),
      I1 => \gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7]_246\(0),
      I2 => \gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7]_246\(1),
      O => \p_0_in__10\(2)
    );
\gen_track_left_edge[7].pb_cnt_eye_size_r[7][3]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6AAA"
    )
        port map (
      I0 => \gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7]_246\(3),
      I1 => \gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7]_246\(1),
      I2 => \gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7]_246\(0),
      I3 => \gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7]_246\(2),
      O => \p_0_in__10\(3)
    );
\gen_track_left_edge[7].pb_cnt_eye_size_r[7][4]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFEFAAAA"
    )
        port map (
      I0 => \FSM_onehot_cal1_state_r_reg_n_0_[16]\,
      I1 => \gen_track_left_edge[7].pb_found_edge_r_reg_n_0_[7]\,
      I2 => samp_cnt_done_r_reg_n_0,
      I3 => p_0_in,
      I4 => \gen_track_left_edge[7].pb_cnt_eye_size_r[7][4]_i_4_n_0\,
      O => \gen_track_left_edge[7].pb_cnt_eye_size_r[7][4]_i_1_n_0\
    );
\gen_track_left_edge[7].pb_cnt_eye_size_r[7][4]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"11100000"
    )
        port map (
      I0 => \gen_track_left_edge[7].pb_cnt_eye_size_r[7][4]_i_5_n_0\,
      I1 => pb_detect_edge_done_r(7),
      I2 => store_sr_req_pulsed_r,
      I3 => p_34_in,
      I4 => samp_cnt_done_r_reg_n_0,
      O => \gen_track_left_edge[7].pb_cnt_eye_size_r[7][4]_i_2_n_0\
    );
\gen_track_left_edge[7].pb_cnt_eye_size_r[7][4]_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"6AAAAAAA"
    )
        port map (
      I0 => \gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7]_246\(4),
      I1 => \gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7]_246\(2),
      I2 => \gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7]_246\(0),
      I3 => \gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7]_246\(1),
      I4 => \gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7]_246\(3),
      O => \p_0_in__10\(4)
    );
\gen_track_left_edge[7].pb_cnt_eye_size_r[7][4]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"1111111111111110"
    )
        port map (
      I0 => \FSM_onehot_cal1_state_r[34]_i_4_n_0\,
      I1 => pb_detect_edge_done_r(7),
      I2 => p_0_in,
      I3 => \gen_sr_match_div4.gen_sr_match[7].old_sr_diff_r_reg_n_0_[7]\,
      I4 => \gen_sr_match_div4.gen_sr_match[7].prev_sr_diff_r_reg_n_0_[7]\,
      I5 => samp_cnt_done_r_reg_n_0,
      O => \gen_track_left_edge[7].pb_cnt_eye_size_r[7][4]_i_4_n_0\
    );
\gen_track_left_edge[7].pb_cnt_eye_size_r[7][4]_i_5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00008000"
    )
        port map (
      I0 => \gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7]_246\(2),
      I1 => \gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7]_246\(0),
      I2 => \gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7]_246\(1),
      I3 => \gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7]_246\(3),
      I4 => \gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7]_246\(4),
      O => \gen_track_left_edge[7].pb_cnt_eye_size_r[7][4]_i_5_n_0\
    );
\gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7][0]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => \gen_track_left_edge[7].pb_cnt_eye_size_r[7][4]_i_2_n_0\,
      D => \p_0_in__10\(0),
      Q => \gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7]_246\(0),
      R => \gen_track_left_edge[7].pb_cnt_eye_size_r[7][4]_i_1_n_0\
    );
\gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7][1]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => \gen_track_left_edge[7].pb_cnt_eye_size_r[7][4]_i_2_n_0\,
      D => \p_0_in__10\(1),
      Q => \gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7]_246\(1),
      R => \gen_track_left_edge[7].pb_cnt_eye_size_r[7][4]_i_1_n_0\
    );
\gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7][2]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => \gen_track_left_edge[7].pb_cnt_eye_size_r[7][4]_i_2_n_0\,
      D => \p_0_in__10\(2),
      Q => \gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7]_246\(2),
      R => \gen_track_left_edge[7].pb_cnt_eye_size_r[7][4]_i_1_n_0\
    );
\gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7][3]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => \gen_track_left_edge[7].pb_cnt_eye_size_r[7][4]_i_2_n_0\,
      D => \p_0_in__10\(3),
      Q => \gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7]_246\(3),
      R => \gen_track_left_edge[7].pb_cnt_eye_size_r[7][4]_i_1_n_0\
    );
\gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7][4]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => \gen_track_left_edge[7].pb_cnt_eye_size_r[7][4]_i_2_n_0\,
      D => \p_0_in__10\(4),
      Q => \gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7]_246\(4),
      R => \gen_track_left_edge[7].pb_cnt_eye_size_r[7][4]_i_1_n_0\
    );
\gen_track_left_edge[7].pb_detect_edge_done_r[7]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"EEEEEEE0"
    )
        port map (
      I0 => store_sr_req_pulsed_r,
      I1 => p_34_in,
      I2 => \gen_sr_match_div4.gen_sr_match[7].prev_sr_diff_r_reg_n_0_[7]\,
      I3 => samp_cnt_done_r_reg_n_0,
      I4 => pb_detect_edge_done_r(7),
      O => \gen_track_left_edge[7].pb_detect_edge_done_r[7]_i_1_n_0\
    );
\gen_track_left_edge[7].pb_detect_edge_done_r_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_track_left_edge[7].pb_detect_edge_done_r[7]_i_1_n_0\,
      Q => pb_detect_edge_done_r(7),
      R => \FSM_onehot_cal1_state_r_reg_n_0_[16]\
    );
\gen_track_left_edge[7].pb_found_edge_r[7]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"5501550155005501"
    )
        port map (
      I0 => \FSM_onehot_cal1_state_r[34]_i_4_n_0\,
      I1 => pb_detect_edge_done_r(7),
      I2 => \gen_track_left_edge[7].pb_found_edge_r[7]_i_2_n_0\,
      I3 => \gen_track_left_edge[7].pb_found_edge_r_reg_n_0_[7]\,
      I4 => samp_cnt_done_r_reg_n_0,
      I5 => p_0_in,
      O => \gen_track_left_edge[7].pb_found_edge_r[7]_i_1_n_0\
    );
\gen_track_left_edge[7].pb_found_edge_r[7]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0001"
    )
        port map (
      I0 => samp_cnt_done_r_reg_n_0,
      I1 => \gen_sr_match_div4.gen_sr_match[7].prev_sr_diff_r_reg_n_0_[7]\,
      I2 => \gen_sr_match_div4.gen_sr_match[7].old_sr_diff_r_reg_n_0_[7]\,
      I3 => p_0_in,
      O => \gen_track_left_edge[7].pb_found_edge_r[7]_i_2_n_0\
    );
\gen_track_left_edge[7].pb_found_edge_r_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_track_left_edge[7].pb_found_edge_r[7]_i_1_n_0\,
      Q => \gen_track_left_edge[7].pb_found_edge_r_reg_n_0_[7]\,
      R => \FSM_onehot_cal1_state_r_reg_n_0_[16]\
    );
\gen_track_left_edge[7].pb_found_stable_eye_r[7]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"55555F5500000800"
    )
        port map (
      I0 => \gen_track_left_edge[7].pb_cnt_eye_size_r[7][4]_i_4_n_0\,
      I1 => \gen_track_left_edge[7].pb_cnt_eye_size_r[7][4]_i_5_n_0\,
      I2 => \gen_track_left_edge[7].pb_found_edge_r_reg_n_0_[7]\,
      I3 => samp_cnt_done_r_reg_n_0,
      I4 => p_0_in,
      I5 => pb_found_stable_eye_r(7),
      O => \gen_track_left_edge[7].pb_found_stable_eye_r[7]_i_1_n_0\
    );
\gen_track_left_edge[7].pb_found_stable_eye_r_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_track_left_edge[7].pb_found_stable_eye_r[7]_i_1_n_0\,
      Q => pb_found_stable_eye_r(7),
      R => \FSM_onehot_cal1_state_r_reg_n_0_[16]\
    );
\gen_track_left_edge[7].pb_last_tap_jitter_r[7]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000FDFD0100"
    )
        port map (
      I0 => samp_cnt_done_r_reg_n_0,
      I1 => pb_detect_edge_done_r(7),
      I2 => \FSM_onehot_cal1_state_r[34]_i_4_n_0\,
      I3 => \gen_sr_match_div4.gen_sr_match[7].prev_sr_diff_r_reg_n_0_[7]\,
      I4 => p_0_in,
      I5 => \FSM_onehot_cal1_state_r_reg_n_0_[16]\,
      O => \gen_track_left_edge[7].pb_last_tap_jitter_r[7]_i_1_n_0\
    );
\gen_track_left_edge[7].pb_last_tap_jitter_r_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \gen_track_left_edge[7].pb_last_tap_jitter_r[7]_i_1_n_0\,
      Q => p_0_in,
      R => '0'
    );
idel_adj_inc_i_1: unisim.vcomponents.LUT4
    generic map(
      INIT => X"C580"
    )
        port map (
      I0 => \idel_dec_cnt[4]_i_3_n_0\,
      I1 => cal1_wait_r,
      I2 => \FSM_onehot_cal1_state_r_reg_n_0_[3]\,
      I3 => idel_adj_inc_reg_n_0,
      O => idel_adj_inc_i_1_n_0
    );
idel_adj_inc_reg: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => idel_adj_inc_i_1_n_0,
      Q => idel_adj_inc_reg_n_0,
      R => \rdlvl_dqs_tap_cnt_r_reg[0][0][2]_0\(1)
    );
\idel_dec_cnt[0]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8F88"
    )
        port map (
      I0 => \FSM_onehot_cal1_state_r_reg_n_0_[1]\,
      I1 => idelay_tap_cnt_r(0),
      I2 => \idel_dec_cnt_reg_n_0_[0]\,
      I3 => \FSM_onehot_cal1_state_r_reg_n_0_[15]\,
      O => idel_dec_cnt(0)
    );
\idel_dec_cnt[1]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"F88F8888"
    )
        port map (
      I0 => \FSM_onehot_cal1_state_r_reg_n_0_[1]\,
      I1 => idelay_tap_cnt_r(1),
      I2 => \idel_dec_cnt_reg_n_0_[1]\,
      I3 => \idel_dec_cnt_reg_n_0_[0]\,
      I4 => \FSM_onehot_cal1_state_r_reg_n_0_[15]\,
      O => idel_dec_cnt(1)
    );
\idel_dec_cnt[2]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F8F8F88F88888888"
    )
        port map (
      I0 => \FSM_onehot_cal1_state_r_reg_n_0_[1]\,
      I1 => idelay_tap_cnt_r(2),
      I2 => \idel_dec_cnt_reg_n_0_[2]\,
      I3 => \idel_dec_cnt_reg_n_0_[0]\,
      I4 => \idel_dec_cnt_reg_n_0_[1]\,
      I5 => \FSM_onehot_cal1_state_r_reg_n_0_[15]\,
      O => idel_dec_cnt(2)
    );
\idel_dec_cnt[3]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"8FF88888"
    )
        port map (
      I0 => \FSM_onehot_cal1_state_r_reg_n_0_[1]\,
      I1 => idelay_tap_cnt_r(3),
      I2 => \idel_dec_cnt_reg_n_0_[3]\,
      I3 => \idel_dec_cnt[3]_i_2_n_0\,
      I4 => \FSM_onehot_cal1_state_r_reg_n_0_[15]\,
      O => idel_dec_cnt(3)
    );
\idel_dec_cnt[3]_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"01"
    )
        port map (
      I0 => \idel_dec_cnt_reg_n_0_[0]\,
      I1 => \idel_dec_cnt_reg_n_0_[1]\,
      I2 => \idel_dec_cnt_reg_n_0_[2]\,
      O => \idel_dec_cnt[3]_i_2_n_0\
    );
\idel_dec_cnt[4]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFF8F8FFF8"
    )
        port map (
      I0 => \FSM_onehot_cal1_state_r[22]_i_2_n_0\,
      I1 => idel_mpr_pat_detect_r,
      I2 => \idel_dec_cnt[4]_i_3_n_0\,
      I3 => \FSM_onehot_cal1_state_r_reg_n_0_[15]\,
      I4 => \idel_dec_cnt[4]_i_4_n_0\,
      I5 => \FSM_onehot_cal1_state_r[15]_i_2_n_0\,
      O => \idel_dec_cnt[4]_i_1_n_0\
    );
\idel_dec_cnt[4]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"8FF88888"
    )
        port map (
      I0 => \FSM_onehot_cal1_state_r_reg_n_0_[1]\,
      I1 => idelay_tap_cnt_r(4),
      I2 => \idel_dec_cnt_reg_n_0_[4]\,
      I3 => \idel_dec_cnt[4]_i_5_n_0\,
      I4 => \FSM_onehot_cal1_state_r_reg_n_0_[15]\,
      O => idel_dec_cnt(4)
    );
\idel_dec_cnt[4]_i_3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"A800"
    )
        port map (
      I0 => detect_edge_done_r,
      I1 => \gen_pat_match_div4.idel_pat1_data_match_r_reg_n_0\,
      I2 => \gen_pat_match_div4.idel_pat0_data_match_r_reg_n_0\,
      I3 => p_34_in,
      O => \idel_dec_cnt[4]_i_3_n_0\
    );
\idel_dec_cnt[4]_i_4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000001"
    )
        port map (
      I0 => \idel_dec_cnt_reg_n_0_[3]\,
      I1 => \idel_dec_cnt_reg_n_0_[0]\,
      I2 => \idel_dec_cnt_reg_n_0_[1]\,
      I3 => \idel_dec_cnt_reg_n_0_[2]\,
      I4 => \idel_dec_cnt_reg_n_0_[4]\,
      O => \idel_dec_cnt[4]_i_4_n_0\
    );
\idel_dec_cnt[4]_i_5\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0001"
    )
        port map (
      I0 => \idel_dec_cnt_reg_n_0_[2]\,
      I1 => \idel_dec_cnt_reg_n_0_[1]\,
      I2 => \idel_dec_cnt_reg_n_0_[0]\,
      I3 => \idel_dec_cnt_reg_n_0_[3]\,
      O => \idel_dec_cnt[4]_i_5_n_0\
    );
\idel_dec_cnt_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => \idel_dec_cnt[4]_i_1_n_0\,
      D => idel_dec_cnt(0),
      Q => \idel_dec_cnt_reg_n_0_[0]\,
      R => \rdlvl_dqs_tap_cnt_r_reg[0][0][2]_0\(1)
    );
\idel_dec_cnt_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => \idel_dec_cnt[4]_i_1_n_0\,
      D => idel_dec_cnt(1),
      Q => \idel_dec_cnt_reg_n_0_[1]\,
      R => \rdlvl_dqs_tap_cnt_r_reg[0][0][2]_0\(1)
    );
\idel_dec_cnt_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => \idel_dec_cnt[4]_i_1_n_0\,
      D => idel_dec_cnt(2),
      Q => \idel_dec_cnt_reg_n_0_[2]\,
      R => \rdlvl_dqs_tap_cnt_r_reg[0][0][2]_0\(1)
    );
\idel_dec_cnt_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => \idel_dec_cnt[4]_i_1_n_0\,
      D => idel_dec_cnt(3),
      Q => \idel_dec_cnt_reg_n_0_[3]\,
      R => \rdlvl_dqs_tap_cnt_r_reg[0][0][2]_0\(1)
    );
\idel_dec_cnt_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => \idel_dec_cnt[4]_i_1_n_0\,
      D => idel_dec_cnt(4),
      Q => \idel_dec_cnt_reg_n_0_[4]\,
      R => \rdlvl_dqs_tap_cnt_r_reg[0][0][2]_0\(1)
    );
idel_pat_detect_valid_r_i_1: unisim.vcomponents.LUT4
    generic map(
      INIT => X"CCCE"
    )
        port map (
      I0 => idel_pat_detect_valid_r_reg_n_0,
      I1 => p_0_in549_in,
      I2 => cal1_dq_idel_inc,
      I3 => store_sr_req_pulsed_r,
      O => idel_pat_detect_valid_r_i_1_n_0
    );
idel_pat_detect_valid_r_reg: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => idel_pat_detect_valid_r_i_1_n_0,
      Q => idel_pat_detect_valid_r_reg_n_0,
      R => \rdlvl_dqs_tap_cnt_r_reg[0][0][2]_0\(1)
    );
\idelay_tap_cnt_r[0][0][0]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"04"
    )
        port map (
      I0 => pi_stg2_f_incdec_timing_reg_0,
      I1 => \^idelay_ce_int\,
      I2 => idelay_tap_cnt_slice_r(0),
      O => \idelay_tap_cnt_r[0][0][0]_i_1_n_0\
    );
\idelay_tap_cnt_r[0][0][1]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"04404004"
    )
        port map (
      I0 => pi_stg2_f_incdec_timing_reg_0,
      I1 => \^idelay_ce_int\,
      I2 => idelay_tap_cnt_slice_r(0),
      I3 => idelay_tap_cnt_slice_r(1),
      I4 => \^idelay_inc_int\,
      O => \idelay_tap_cnt_r[0][0][1]_i_1_n_0\
    );
\idelay_tap_cnt_r[0][0][2]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0444400044400004"
    )
        port map (
      I0 => pi_stg2_f_incdec_timing_reg_0,
      I1 => \^idelay_ce_int\,
      I2 => \^idelay_inc_int\,
      I3 => idelay_tap_cnt_slice_r(0),
      I4 => idelay_tap_cnt_slice_r(2),
      I5 => idelay_tap_cnt_slice_r(1),
      O => \idelay_tap_cnt_r[0][0][2]_i_1_n_0\
    );
\idelay_tap_cnt_r[0][0][3]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"28A0A0A0A0A0A082"
    )
        port map (
      I0 => \idelay_tap_cnt_r[0][0][3]_i_2_n_0\,
      I1 => idelay_tap_cnt_slice_r(2),
      I2 => idelay_tap_cnt_slice_r(3),
      I3 => idelay_tap_cnt_slice_r(0),
      I4 => \^idelay_inc_int\,
      I5 => idelay_tap_cnt_slice_r(1),
      O => \idelay_tap_cnt_r[0][0][3]_i_1_n_0\
    );
\idelay_tap_cnt_r[0][0][3]_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \^idelay_ce_int\,
      I1 => pi_stg2_f_incdec_timing_reg_0,
      O => \idelay_tap_cnt_r[0][0][3]_i_2_n_0\
    );
\idelay_tap_cnt_r[0][0][4]_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"04"
    )
        port map (
      I0 => pi_stg2_f_incdec_timing_reg_0,
      I1 => \^idelay_ce_int\,
      I2 => \idelay_tap_cnt_r[0][0][4]_i_6_n_0\,
      O => \idelay_tap_cnt_r[0][0][4]_i_2_n_0\
    );
\idelay_tap_cnt_r[0][0][4]_i_3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \cal1_cnt_cpt_r_reg_n_0_[0]\,
      I1 => \cal1_cnt_cpt_r_reg_n_0_[1]\,
      O => \cal1_cnt_cpt_r_reg[0]_0\
    );
\idelay_tap_cnt_r[0][0][4]_i_4\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0100"
    )
        port map (
      I0 => \cal1_cnt_cpt_r_reg_n_0_[2]\,
      I1 => \rnk_cnt_r_reg_n_0_[1]\,
      I2 => \rnk_cnt_r_reg_n_0_[0]\,
      I3 => \^idelay_ce_int\,
      O => \cal1_cnt_cpt_r_reg[2]_0\
    );
\idelay_tap_cnt_r[0][0][4]_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"9555555555555556"
    )
        port map (
      I0 => idelay_tap_cnt_slice_r(4),
      I1 => idelay_tap_cnt_slice_r(0),
      I2 => \^idelay_inc_int\,
      I3 => idelay_tap_cnt_slice_r(1),
      I4 => idelay_tap_cnt_slice_r(3),
      I5 => idelay_tap_cnt_slice_r(2),
      O => \idelay_tap_cnt_r[0][0][4]_i_6_n_0\
    );
\idelay_tap_cnt_r[0][1][4]_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"01"
    )
        port map (
      I0 => \rnk_cnt_r_reg_n_0_[0]\,
      I1 => \rnk_cnt_r_reg_n_0_[1]\,
      I2 => \cal1_cnt_cpt_r_reg_n_0_[2]\,
      O => \rnk_cnt_r_reg[0]_0\
    );
\idelay_tap_cnt_r[0][1][4]_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"08"
    )
        port map (
      I0 => \^idelay_ce_int\,
      I1 => \cal1_cnt_cpt_r_reg_n_0_[0]\,
      I2 => \cal1_cnt_cpt_r_reg_n_0_[1]\,
      O => cal1_dq_idel_ce_reg_1
    );
\idelay_tap_cnt_r[0][2][4]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000200000000"
    )
        port map (
      I0 => \^idelay_ce_int\,
      I1 => \rnk_cnt_r_reg_n_0_[0]\,
      I2 => \rnk_cnt_r_reg_n_0_[1]\,
      I3 => \cal1_cnt_cpt_r_reg_n_0_[2]\,
      I4 => \cal1_cnt_cpt_r_reg_n_0_[0]\,
      I5 => \cal1_cnt_cpt_r_reg_n_0_[1]\,
      O => cal1_dq_idel_ce_reg_0
    );
\idelay_tap_cnt_r[0][3][4]_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"7F"
    )
        port map (
      I0 => \^idelay_ce_int\,
      I1 => \cal1_cnt_cpt_r_reg_n_0_[1]\,
      I2 => \cal1_cnt_cpt_r_reg_n_0_[0]\,
      O => cal1_dq_idel_ce_reg_2
    );
\idelay_tap_cnt_r[0][4][4]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"EFFF"
    )
        port map (
      I0 => \rnk_cnt_r_reg_n_0_[1]\,
      I1 => \rnk_cnt_r_reg_n_0_[0]\,
      I2 => \cal1_cnt_cpt_r_reg_n_0_[2]\,
      I3 => \^idelay_ce_int\,
      O => \rnk_cnt_r_reg[1]_0\
    );
\idelay_tap_cnt_r[0][6][4]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000004000"
    )
        port map (
      I0 => \cal1_cnt_cpt_r_reg_n_0_[0]\,
      I1 => \cal1_cnt_cpt_r_reg_n_0_[1]\,
      I2 => \^idelay_ce_int\,
      I3 => \cal1_cnt_cpt_r_reg_n_0_[2]\,
      I4 => \rnk_cnt_r_reg_n_0_[0]\,
      I5 => \rnk_cnt_r_reg_n_0_[1]\,
      O => \cal1_cnt_cpt_r_reg[0]_1\
    );
\idelay_tap_cnt_r_reg[0][0][0]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => \idelay_tap_cnt_r_reg[0][0][4]_0\(0),
      D => \idelay_tap_cnt_r[0][0][0]_i_1_n_0\,
      Q => \idelay_tap_cnt_r_reg_n_0_[0][0][0]\,
      R => '0'
    );
\idelay_tap_cnt_r_reg[0][0][1]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => \idelay_tap_cnt_r_reg[0][0][4]_0\(0),
      D => \idelay_tap_cnt_r[0][0][1]_i_1_n_0\,
      Q => \idelay_tap_cnt_r_reg_n_0_[0][0][1]\,
      R => '0'
    );
\idelay_tap_cnt_r_reg[0][0][2]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => \idelay_tap_cnt_r_reg[0][0][4]_0\(0),
      D => \idelay_tap_cnt_r[0][0][2]_i_1_n_0\,
      Q => \idelay_tap_cnt_r_reg_n_0_[0][0][2]\,
      R => '0'
    );
\idelay_tap_cnt_r_reg[0][0][3]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => \idelay_tap_cnt_r_reg[0][0][4]_0\(0),
      D => \idelay_tap_cnt_r[0][0][3]_i_1_n_0\,
      Q => \idelay_tap_cnt_r_reg_n_0_[0][0][3]\,
      R => '0'
    );
\idelay_tap_cnt_r_reg[0][0][4]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => \idelay_tap_cnt_r_reg[0][0][4]_0\(0),
      D => \idelay_tap_cnt_r[0][0][4]_i_2_n_0\,
      Q => \idelay_tap_cnt_r_reg_n_0_[0][0][4]\,
      R => '0'
    );
\idelay_tap_cnt_r_reg[0][1][0]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => \idelay_tap_cnt_r_reg[0][1][4]_0\(0),
      D => \idelay_tap_cnt_r[0][0][0]_i_1_n_0\,
      Q => \idelay_tap_cnt_r_reg_n_0_[0][1][0]\,
      R => '0'
    );
\idelay_tap_cnt_r_reg[0][1][1]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => \idelay_tap_cnt_r_reg[0][1][4]_0\(0),
      D => \idelay_tap_cnt_r[0][0][1]_i_1_n_0\,
      Q => \idelay_tap_cnt_r_reg_n_0_[0][1][1]\,
      R => '0'
    );
\idelay_tap_cnt_r_reg[0][1][2]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => \idelay_tap_cnt_r_reg[0][1][4]_0\(0),
      D => \idelay_tap_cnt_r[0][0][2]_i_1_n_0\,
      Q => \idelay_tap_cnt_r_reg_n_0_[0][1][2]\,
      R => '0'
    );
\idelay_tap_cnt_r_reg[0][1][3]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => \idelay_tap_cnt_r_reg[0][1][4]_0\(0),
      D => \idelay_tap_cnt_r[0][0][3]_i_1_n_0\,
      Q => \idelay_tap_cnt_r_reg_n_0_[0][1][3]\,
      R => '0'
    );
\idelay_tap_cnt_r_reg[0][1][4]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => \idelay_tap_cnt_r_reg[0][1][4]_0\(0),
      D => \idelay_tap_cnt_r[0][0][4]_i_2_n_0\,
      Q => \idelay_tap_cnt_r_reg_n_0_[0][1][4]\,
      R => '0'
    );
\idelay_tap_cnt_r_reg[0][2][0]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => \idelay_tap_cnt_r_reg[0][2][4]_0\(0),
      D => \idelay_tap_cnt_r[0][0][0]_i_1_n_0\,
      Q => \idelay_tap_cnt_r_reg_n_0_[0][2][0]\,
      R => '0'
    );
\idelay_tap_cnt_r_reg[0][2][1]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => \idelay_tap_cnt_r_reg[0][2][4]_0\(0),
      D => \idelay_tap_cnt_r[0][0][1]_i_1_n_0\,
      Q => \idelay_tap_cnt_r_reg_n_0_[0][2][1]\,
      R => '0'
    );
\idelay_tap_cnt_r_reg[0][2][2]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => \idelay_tap_cnt_r_reg[0][2][4]_0\(0),
      D => \idelay_tap_cnt_r[0][0][2]_i_1_n_0\,
      Q => \idelay_tap_cnt_r_reg_n_0_[0][2][2]\,
      R => '0'
    );
\idelay_tap_cnt_r_reg[0][2][3]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => \idelay_tap_cnt_r_reg[0][2][4]_0\(0),
      D => \idelay_tap_cnt_r[0][0][3]_i_1_n_0\,
      Q => \idelay_tap_cnt_r_reg_n_0_[0][2][3]\,
      R => '0'
    );
\idelay_tap_cnt_r_reg[0][2][4]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => \idelay_tap_cnt_r_reg[0][2][4]_0\(0),
      D => \idelay_tap_cnt_r[0][0][4]_i_2_n_0\,
      Q => \idelay_tap_cnt_r_reg_n_0_[0][2][4]\,
      R => '0'
    );
\idelay_tap_cnt_r_reg[0][3][0]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => \idelay_tap_cnt_r_reg[0][3][4]_0\(0),
      D => \idelay_tap_cnt_r[0][0][0]_i_1_n_0\,
      Q => \idelay_tap_cnt_r_reg_n_0_[0][3][0]\,
      R => '0'
    );
\idelay_tap_cnt_r_reg[0][3][1]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => \idelay_tap_cnt_r_reg[0][3][4]_0\(0),
      D => \idelay_tap_cnt_r[0][0][1]_i_1_n_0\,
      Q => \idelay_tap_cnt_r_reg_n_0_[0][3][1]\,
      R => '0'
    );
\idelay_tap_cnt_r_reg[0][3][2]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => \idelay_tap_cnt_r_reg[0][3][4]_0\(0),
      D => \idelay_tap_cnt_r[0][0][2]_i_1_n_0\,
      Q => \idelay_tap_cnt_r_reg_n_0_[0][3][2]\,
      R => '0'
    );
\idelay_tap_cnt_r_reg[0][3][3]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => \idelay_tap_cnt_r_reg[0][3][4]_0\(0),
      D => \idelay_tap_cnt_r[0][0][3]_i_1_n_0\,
      Q => \idelay_tap_cnt_r_reg_n_0_[0][3][3]\,
      R => '0'
    );
\idelay_tap_cnt_r_reg[0][3][4]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => \idelay_tap_cnt_r_reg[0][3][4]_0\(0),
      D => \idelay_tap_cnt_r[0][0][4]_i_2_n_0\,
      Q => \idelay_tap_cnt_r_reg_n_0_[0][3][4]\,
      R => '0'
    );
\idelay_tap_cnt_r_reg[0][4][0]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => \idelay_tap_cnt_r_reg[0][4][4]_0\(0),
      D => \idelay_tap_cnt_r[0][0][0]_i_1_n_0\,
      Q => \idelay_tap_cnt_r_reg_n_0_[0][4][0]\,
      R => '0'
    );
\idelay_tap_cnt_r_reg[0][4][1]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => \idelay_tap_cnt_r_reg[0][4][4]_0\(0),
      D => \idelay_tap_cnt_r[0][0][1]_i_1_n_0\,
      Q => \idelay_tap_cnt_r_reg_n_0_[0][4][1]\,
      R => '0'
    );
\idelay_tap_cnt_r_reg[0][4][2]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => \idelay_tap_cnt_r_reg[0][4][4]_0\(0),
      D => \idelay_tap_cnt_r[0][0][2]_i_1_n_0\,
      Q => \idelay_tap_cnt_r_reg_n_0_[0][4][2]\,
      R => '0'
    );
\idelay_tap_cnt_r_reg[0][4][3]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => \idelay_tap_cnt_r_reg[0][4][4]_0\(0),
      D => \idelay_tap_cnt_r[0][0][3]_i_1_n_0\,
      Q => \idelay_tap_cnt_r_reg_n_0_[0][4][3]\,
      R => '0'
    );
\idelay_tap_cnt_r_reg[0][4][4]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => \idelay_tap_cnt_r_reg[0][4][4]_0\(0),
      D => \idelay_tap_cnt_r[0][0][4]_i_2_n_0\,
      Q => \idelay_tap_cnt_r_reg_n_0_[0][4][4]\,
      R => '0'
    );
\idelay_tap_cnt_r_reg[0][5][0]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => \idelay_tap_cnt_r_reg[0][5][4]_0\(0),
      D => \idelay_tap_cnt_r[0][0][0]_i_1_n_0\,
      Q => \idelay_tap_cnt_r_reg_n_0_[0][5][0]\,
      R => '0'
    );
\idelay_tap_cnt_r_reg[0][5][1]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => \idelay_tap_cnt_r_reg[0][5][4]_0\(0),
      D => \idelay_tap_cnt_r[0][0][1]_i_1_n_0\,
      Q => \idelay_tap_cnt_r_reg_n_0_[0][5][1]\,
      R => '0'
    );
\idelay_tap_cnt_r_reg[0][5][2]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => \idelay_tap_cnt_r_reg[0][5][4]_0\(0),
      D => \idelay_tap_cnt_r[0][0][2]_i_1_n_0\,
      Q => \idelay_tap_cnt_r_reg_n_0_[0][5][2]\,
      R => '0'
    );
\idelay_tap_cnt_r_reg[0][5][3]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => \idelay_tap_cnt_r_reg[0][5][4]_0\(0),
      D => \idelay_tap_cnt_r[0][0][3]_i_1_n_0\,
      Q => \idelay_tap_cnt_r_reg_n_0_[0][5][3]\,
      R => '0'
    );
\idelay_tap_cnt_r_reg[0][5][4]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => \idelay_tap_cnt_r_reg[0][5][4]_0\(0),
      D => \idelay_tap_cnt_r[0][0][4]_i_2_n_0\,
      Q => \idelay_tap_cnt_r_reg_n_0_[0][5][4]\,
      R => '0'
    );
\idelay_tap_cnt_r_reg[0][6][0]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => \idelay_tap_cnt_r_reg[0][6][4]_0\(0),
      D => \idelay_tap_cnt_r[0][0][0]_i_1_n_0\,
      Q => \idelay_tap_cnt_r_reg_n_0_[0][6][0]\,
      R => '0'
    );
\idelay_tap_cnt_r_reg[0][6][1]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => \idelay_tap_cnt_r_reg[0][6][4]_0\(0),
      D => \idelay_tap_cnt_r[0][0][1]_i_1_n_0\,
      Q => \idelay_tap_cnt_r_reg_n_0_[0][6][1]\,
      R => '0'
    );
\idelay_tap_cnt_r_reg[0][6][2]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => \idelay_tap_cnt_r_reg[0][6][4]_0\(0),
      D => \idelay_tap_cnt_r[0][0][2]_i_1_n_0\,
      Q => \idelay_tap_cnt_r_reg_n_0_[0][6][2]\,
      R => '0'
    );
\idelay_tap_cnt_r_reg[0][6][3]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => \idelay_tap_cnt_r_reg[0][6][4]_0\(0),
      D => \idelay_tap_cnt_r[0][0][3]_i_1_n_0\,
      Q => \idelay_tap_cnt_r_reg_n_0_[0][6][3]\,
      R => '0'
    );
\idelay_tap_cnt_r_reg[0][6][4]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => \idelay_tap_cnt_r_reg[0][6][4]_0\(0),
      D => \idelay_tap_cnt_r[0][0][4]_i_2_n_0\,
      Q => \idelay_tap_cnt_r_reg_n_0_[0][6][4]\,
      R => '0'
    );
\idelay_tap_cnt_r_reg[0][7][0]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => \idelay_tap_cnt_r_reg[0][7][4]_0\(0),
      D => \idelay_tap_cnt_r[0][0][0]_i_1_n_0\,
      Q => \idelay_tap_cnt_r_reg_n_0_[0][7][0]\,
      R => '0'
    );
\idelay_tap_cnt_r_reg[0][7][1]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => \idelay_tap_cnt_r_reg[0][7][4]_0\(0),
      D => \idelay_tap_cnt_r[0][0][1]_i_1_n_0\,
      Q => \idelay_tap_cnt_r_reg_n_0_[0][7][1]\,
      R => '0'
    );
\idelay_tap_cnt_r_reg[0][7][2]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => \idelay_tap_cnt_r_reg[0][7][4]_0\(0),
      D => \idelay_tap_cnt_r[0][0][2]_i_1_n_0\,
      Q => \idelay_tap_cnt_r_reg_n_0_[0][7][2]\,
      R => '0'
    );
\idelay_tap_cnt_r_reg[0][7][3]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => \idelay_tap_cnt_r_reg[0][7][4]_0\(0),
      D => \idelay_tap_cnt_r[0][0][3]_i_1_n_0\,
      Q => \idelay_tap_cnt_r_reg_n_0_[0][7][3]\,
      R => '0'
    );
\idelay_tap_cnt_r_reg[0][7][4]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => \idelay_tap_cnt_r_reg[0][7][4]_0\(0),
      D => \idelay_tap_cnt_r[0][0][4]_i_2_n_0\,
      Q => \idelay_tap_cnt_r_reg_n_0_[0][7][4]\,
      R => '0'
    );
\idelay_tap_cnt_slice_r[0]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \idelay_tap_cnt_r_reg_n_0_[0][3][0]\,
      I1 => \idelay_tap_cnt_r_reg_n_0_[0][2][0]\,
      I2 => \cal1_cnt_cpt_r_reg_n_0_[1]\,
      I3 => \idelay_tap_cnt_r_reg_n_0_[0][1][0]\,
      I4 => \cal1_cnt_cpt_r_reg_n_0_[0]\,
      I5 => \idelay_tap_cnt_r_reg_n_0_[0][0][0]\,
      O => \idelay_tap_cnt_slice_r[0]_i_2_n_0\
    );
\idelay_tap_cnt_slice_r[0]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \idelay_tap_cnt_r_reg_n_0_[0][7][0]\,
      I1 => \idelay_tap_cnt_r_reg_n_0_[0][6][0]\,
      I2 => \cal1_cnt_cpt_r_reg_n_0_[1]\,
      I3 => \idelay_tap_cnt_r_reg_n_0_[0][5][0]\,
      I4 => \cal1_cnt_cpt_r_reg_n_0_[0]\,
      I5 => \idelay_tap_cnt_r_reg_n_0_[0][4][0]\,
      O => \idelay_tap_cnt_slice_r[0]_i_3_n_0\
    );
\idelay_tap_cnt_slice_r[1]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \idelay_tap_cnt_r_reg_n_0_[0][3][1]\,
      I1 => \idelay_tap_cnt_r_reg_n_0_[0][2][1]\,
      I2 => \cal1_cnt_cpt_r_reg_n_0_[1]\,
      I3 => \idelay_tap_cnt_r_reg_n_0_[0][1][1]\,
      I4 => \cal1_cnt_cpt_r_reg_n_0_[0]\,
      I5 => \idelay_tap_cnt_r_reg_n_0_[0][0][1]\,
      O => \idelay_tap_cnt_slice_r[1]_i_2_n_0\
    );
\idelay_tap_cnt_slice_r[1]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \idelay_tap_cnt_r_reg_n_0_[0][7][1]\,
      I1 => \idelay_tap_cnt_r_reg_n_0_[0][6][1]\,
      I2 => \cal1_cnt_cpt_r_reg_n_0_[1]\,
      I3 => \idelay_tap_cnt_r_reg_n_0_[0][5][1]\,
      I4 => \cal1_cnt_cpt_r_reg_n_0_[0]\,
      I5 => \idelay_tap_cnt_r_reg_n_0_[0][4][1]\,
      O => \idelay_tap_cnt_slice_r[1]_i_3_n_0\
    );
\idelay_tap_cnt_slice_r[2]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \idelay_tap_cnt_r_reg_n_0_[0][3][2]\,
      I1 => \idelay_tap_cnt_r_reg_n_0_[0][2][2]\,
      I2 => \cal1_cnt_cpt_r_reg_n_0_[1]\,
      I3 => \idelay_tap_cnt_r_reg_n_0_[0][1][2]\,
      I4 => \cal1_cnt_cpt_r_reg_n_0_[0]\,
      I5 => \idelay_tap_cnt_r_reg_n_0_[0][0][2]\,
      O => \idelay_tap_cnt_slice_r[2]_i_2_n_0\
    );
\idelay_tap_cnt_slice_r[2]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \idelay_tap_cnt_r_reg_n_0_[0][7][2]\,
      I1 => \idelay_tap_cnt_r_reg_n_0_[0][6][2]\,
      I2 => \cal1_cnt_cpt_r_reg_n_0_[1]\,
      I3 => \idelay_tap_cnt_r_reg_n_0_[0][5][2]\,
      I4 => \cal1_cnt_cpt_r_reg_n_0_[0]\,
      I5 => \idelay_tap_cnt_r_reg_n_0_[0][4][2]\,
      O => \idelay_tap_cnt_slice_r[2]_i_3_n_0\
    );
\idelay_tap_cnt_slice_r[3]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \idelay_tap_cnt_r_reg_n_0_[0][3][3]\,
      I1 => \idelay_tap_cnt_r_reg_n_0_[0][2][3]\,
      I2 => \cal1_cnt_cpt_r_reg_n_0_[1]\,
      I3 => \idelay_tap_cnt_r_reg_n_0_[0][1][3]\,
      I4 => \cal1_cnt_cpt_r_reg_n_0_[0]\,
      I5 => \idelay_tap_cnt_r_reg_n_0_[0][0][3]\,
      O => \idelay_tap_cnt_slice_r[3]_i_2_n_0\
    );
\idelay_tap_cnt_slice_r[3]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \idelay_tap_cnt_r_reg_n_0_[0][7][3]\,
      I1 => \idelay_tap_cnt_r_reg_n_0_[0][6][3]\,
      I2 => \cal1_cnt_cpt_r_reg_n_0_[1]\,
      I3 => \idelay_tap_cnt_r_reg_n_0_[0][5][3]\,
      I4 => \cal1_cnt_cpt_r_reg_n_0_[0]\,
      I5 => \idelay_tap_cnt_r_reg_n_0_[0][4][3]\,
      O => \idelay_tap_cnt_slice_r[3]_i_3_n_0\
    );
\idelay_tap_cnt_slice_r[4]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \idelay_tap_cnt_r_reg_n_0_[0][3][4]\,
      I1 => \idelay_tap_cnt_r_reg_n_0_[0][2][4]\,
      I2 => \cal1_cnt_cpt_r_reg_n_0_[1]\,
      I3 => \idelay_tap_cnt_r_reg_n_0_[0][1][4]\,
      I4 => \cal1_cnt_cpt_r_reg_n_0_[0]\,
      I5 => \idelay_tap_cnt_r_reg_n_0_[0][0][4]\,
      O => \idelay_tap_cnt_slice_r[4]_i_2_n_0\
    );
\idelay_tap_cnt_slice_r[4]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \idelay_tap_cnt_r_reg_n_0_[0][7][4]\,
      I1 => \idelay_tap_cnt_r_reg_n_0_[0][6][4]\,
      I2 => \cal1_cnt_cpt_r_reg_n_0_[1]\,
      I3 => \idelay_tap_cnt_r_reg_n_0_[0][5][4]\,
      I4 => \cal1_cnt_cpt_r_reg_n_0_[0]\,
      I5 => \idelay_tap_cnt_r_reg_n_0_[0][4][4]\,
      O => \idelay_tap_cnt_slice_r[4]_i_3_n_0\
    );
\idelay_tap_cnt_slice_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => idelay_tap_cnt_r(0),
      Q => idelay_tap_cnt_slice_r(0),
      R => \rdlvl_dqs_tap_cnt_r_reg[0][0][2]_0\(1)
    );
\idelay_tap_cnt_slice_r_reg[0]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \idelay_tap_cnt_slice_r[0]_i_2_n_0\,
      I1 => \idelay_tap_cnt_slice_r[0]_i_3_n_0\,
      O => idelay_tap_cnt_r(0),
      S => \cal1_cnt_cpt_r_reg_n_0_[2]\
    );
\idelay_tap_cnt_slice_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => idelay_tap_cnt_r(1),
      Q => idelay_tap_cnt_slice_r(1),
      R => \rdlvl_dqs_tap_cnt_r_reg[0][0][2]_0\(1)
    );
\idelay_tap_cnt_slice_r_reg[1]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \idelay_tap_cnt_slice_r[1]_i_2_n_0\,
      I1 => \idelay_tap_cnt_slice_r[1]_i_3_n_0\,
      O => idelay_tap_cnt_r(1),
      S => \cal1_cnt_cpt_r_reg_n_0_[2]\
    );
\idelay_tap_cnt_slice_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => idelay_tap_cnt_r(2),
      Q => idelay_tap_cnt_slice_r(2),
      R => \rdlvl_dqs_tap_cnt_r_reg[0][0][2]_0\(1)
    );
\idelay_tap_cnt_slice_r_reg[2]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \idelay_tap_cnt_slice_r[2]_i_2_n_0\,
      I1 => \idelay_tap_cnt_slice_r[2]_i_3_n_0\,
      O => idelay_tap_cnt_r(2),
      S => \cal1_cnt_cpt_r_reg_n_0_[2]\
    );
\idelay_tap_cnt_slice_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => idelay_tap_cnt_r(3),
      Q => idelay_tap_cnt_slice_r(3),
      R => \rdlvl_dqs_tap_cnt_r_reg[0][0][2]_0\(1)
    );
\idelay_tap_cnt_slice_r_reg[3]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \idelay_tap_cnt_slice_r[3]_i_2_n_0\,
      I1 => \idelay_tap_cnt_slice_r[3]_i_3_n_0\,
      O => idelay_tap_cnt_r(3),
      S => \cal1_cnt_cpt_r_reg_n_0_[2]\
    );
\idelay_tap_cnt_slice_r_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => idelay_tap_cnt_r(4),
      Q => idelay_tap_cnt_slice_r(4),
      R => \rdlvl_dqs_tap_cnt_r_reg[0][0][2]_0\(1)
    );
\idelay_tap_cnt_slice_r_reg[4]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \idelay_tap_cnt_slice_r[4]_i_2_n_0\,
      I1 => \idelay_tap_cnt_slice_r[4]_i_3_n_0\,
      O => idelay_tap_cnt_r(4),
      S => \cal1_cnt_cpt_r_reg_n_0_[2]\
    );
idelay_tap_limit_r_i_1: unisim.vcomponents.LUT3
    generic map(
      INIT => X"02"
    )
        port map (
      I0 => idelay_tap_limit_r_i_2_n_0,
      I1 => \^new_cnt_cpt_r_reg_0\,
      I2 => \done_cnt_reg[2]_0\,
      O => idelay_tap_limit_r_i_1_n_0
    );
idelay_tap_limit_r_i_2: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFF80000000"
    )
        port map (
      I0 => idelay_tap_cnt_r(3),
      I1 => idelay_tap_cnt_r(0),
      I2 => idelay_tap_cnt_r(2),
      I3 => idelay_tap_cnt_r(4),
      I4 => idelay_tap_cnt_r(1),
      I5 => idelay_tap_limit_r_reg_n_0,
      O => idelay_tap_limit_r_i_2_n_0
    );
idelay_tap_limit_r_reg: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => idelay_tap_limit_r_i_1_n_0,
      Q => idelay_tap_limit_r_reg_n_0,
      R => '0'
    );
\init_state_r[1]_i_28\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"000B"
    )
        port map (
      I0 => rdlvl_stg1_done_r1,
      I1 => \^rdlvl_stg1_done_int_reg_0\,
      I2 => \^rdlvl_stg1_rank_done\,
      I3 => \init_state_r[1]_i_16\(0),
      O => rdlvl_stg1_done_r1_reg
    );
\mpr_4to1.idel_mpr_pat_detect_r_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000200"
    )
        port map (
      I0 => \mpr_4to1.inhibit_edge_detect_r_i_4_n_0\,
      I1 => \mpr_4to1.idel_mpr_pat_detect_r_i_2_n_0\,
      I2 => p_1_in26_in,
      I3 => \mpr_4to1.idel_mpr_pat_detect_r_i_3_n_0\,
      I4 => inhibit_edge_detect_r,
      O => \mpr_4to1.idel_mpr_pat_detect_r_i_1_n_0\
    );
\mpr_4to1.idel_mpr_pat_detect_r_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0008"
    )
        port map (
      I0 => p_0_in549_in,
      I1 => idel_pat_detect_valid_r_reg_n_0,
      I2 => \mpr_4to1.stable_idel_cnt_reg_n_0_[1]\,
      I3 => \mpr_4to1.stable_idel_cnt_reg_n_0_[2]\,
      O => \mpr_4to1.idel_mpr_pat_detect_r_i_2_n_0\
    );
\mpr_4to1.idel_mpr_pat_detect_r_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFF00100000"
    )
        port map (
      I0 => \mpr_4to1.inhibit_edge_detect_r_i_3_n_0\,
      I1 => \mpr_4to1.stable_idel_cnt_reg_n_0_[0]\,
      I2 => \mpr_4to1.stable_idel_cnt_reg_n_0_[1]\,
      I3 => \mpr_4to1.stable_idel_cnt_reg_n_0_[2]\,
      I4 => \mpr_4to1.stable_idel_cnt[2]_i_4_n_0\,
      I5 => idel_mpr_pat_detect_r,
      O => \mpr_4to1.idel_mpr_pat_detect_r_i_3_n_0\
    );
\mpr_4to1.idel_mpr_pat_detect_r_reg\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \mpr_4to1.idel_mpr_pat_detect_r_i_1_n_0\,
      Q => idel_mpr_pat_detect_r,
      R => '0'
    );
\mpr_4to1.inhibit_edge_detect_r_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"F700FFFF"
    )
        port map (
      I0 => \mpr_4to1.inhibit_edge_detect_r_i_2_n_0\,
      I1 => p_0_in549_in,
      I2 => \mpr_4to1.inhibit_edge_detect_r_i_3_n_0\,
      I3 => inhibit_edge_detect_r,
      I4 => \mpr_4to1.inhibit_edge_detect_r_i_4_n_0\,
      O => \mpr_4to1.inhibit_edge_detect_r_i_1_n_0\
    );
\mpr_4to1.inhibit_edge_detect_r_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFFE"
    )
        port map (
      I0 => idelay_tap_cnt_r(3),
      I1 => idelay_tap_cnt_r(4),
      I2 => idelay_tap_cnt_r(1),
      I3 => idelay_tap_cnt_r(2),
      O => \mpr_4to1.inhibit_edge_detect_r_i_2_n_0\
    );
\mpr_4to1.inhibit_edge_detect_r_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFFBFF"
    )
        port map (
      I0 => mpr_rd_rise2_prev_r,
      I1 => mpr_rd_fall2_prev_r,
      I2 => mpr_rd_rise1_prev_r,
      I3 => mpr_rd_fall0_prev_r,
      I4 => \mpr_4to1.inhibit_edge_detect_r_i_5_n_0\,
      O => \mpr_4to1.inhibit_edge_detect_r_i_3_n_0\
    );
\mpr_4to1.inhibit_edge_detect_r_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"5555555555554555"
    )
        port map (
      I0 => pi_stg2_f_incdec_timing_reg_0,
      I1 => \mpr_4to1.inhibit_edge_detect_r_i_6_n_0\,
      I2 => mpr_rd_rise2_prev_r,
      I3 => mpr_rd_rise1_prev_r,
      I4 => mpr_rd_fall1_prev_r,
      I5 => mpr_rd_fall0_prev_r,
      O => \mpr_4to1.inhibit_edge_detect_r_i_4_n_0\
    );
\mpr_4to1.inhibit_edge_detect_r_i_5\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFDF"
    )
        port map (
      I0 => mpr_rd_fall1_prev_r,
      I1 => mpr_rd_rise3_prev_r,
      I2 => mpr_rd_fall3_prev_r,
      I3 => mpr_rd_rise0_prev_r,
      O => \mpr_4to1.inhibit_edge_detect_r_i_5_n_0\
    );
\mpr_4to1.inhibit_edge_detect_r_i_6\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFF7"
    )
        port map (
      I0 => mpr_rd_rise3_prev_r,
      I1 => mpr_rd_rise0_prev_r,
      I2 => mpr_rd_fall2_prev_r,
      I3 => mpr_rd_fall3_prev_r,
      O => \mpr_4to1.inhibit_edge_detect_r_i_6_n_0\
    );
\mpr_4to1.inhibit_edge_detect_r_reg\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \mpr_4to1.inhibit_edge_detect_r_i_1_n_0\,
      Q => inhibit_edge_detect_r,
      R => '0'
    );
\mpr_4to1.stable_idel_cnt[0]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"06"
    )
        port map (
      I0 => \mpr_4to1.stable_idel_cnt_reg_n_0_[0]\,
      I1 => stable_idel_cnt,
      I2 => stable_idel_cnt0,
      O => \mpr_4to1.stable_idel_cnt[0]_i_1_n_0\
    );
\mpr_4to1.stable_idel_cnt[1]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"006A"
    )
        port map (
      I0 => \mpr_4to1.stable_idel_cnt_reg_n_0_[1]\,
      I1 => stable_idel_cnt,
      I2 => \mpr_4to1.stable_idel_cnt_reg_n_0_[0]\,
      I3 => stable_idel_cnt0,
      O => \mpr_4to1.stable_idel_cnt[1]_i_1_n_0\
    );
\mpr_4to1.stable_idel_cnt[2]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00006AAA"
    )
        port map (
      I0 => \mpr_4to1.stable_idel_cnt_reg_n_0_[2]\,
      I1 => stable_idel_cnt,
      I2 => \mpr_4to1.stable_idel_cnt_reg_n_0_[1]\,
      I3 => \mpr_4to1.stable_idel_cnt_reg_n_0_[0]\,
      I4 => stable_idel_cnt0,
      O => \mpr_4to1.stable_idel_cnt[2]_i_1_n_0\
    );
\mpr_4to1.stable_idel_cnt[2]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000000040"
    )
        port map (
      I0 => \mpr_4to1.stable_idel_cnt[2]_i_4_n_0\,
      I1 => p_0_in549_in,
      I2 => idel_pat_detect_valid_r_reg_n_0,
      I3 => \mpr_4to1.stable_idel_cnt_reg_n_0_[1]\,
      I4 => \mpr_4to1.stable_idel_cnt_reg_n_0_[2]\,
      I5 => \FSM_onehot_cal1_state_r[16]_i_3_n_0\,
      O => stable_idel_cnt
    );
\mpr_4to1.stable_idel_cnt[2]_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"FE"
    )
        port map (
      I0 => \mpr_4to1.stable_idel_cnt[2]_i_4_n_0\,
      I1 => \FSM_onehot_cal1_state_r_reg_n_0_[8]\,
      I2 => pi_stg2_f_incdec_timing_reg_0,
      O => stable_idel_cnt0
    );
\mpr_4to1.stable_idel_cnt[2]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFBEFFFFBE"
    )
        port map (
      I0 => \mpr_4to1.stable_idel_cnt[2]_i_5_n_0\,
      I1 => \gen_mux_rd[0].mux_rd_rise3_r_reg_n_0_[0]\,
      I2 => mpr_rd_rise3_prev_r,
      I3 => \gen_mux_rd[0].mux_rd_fall1_r_reg_n_0_[0]\,
      I4 => mpr_rd_fall1_prev_r,
      I5 => \mpr_4to1.stable_idel_cnt[2]_i_6_n_0\,
      O => \mpr_4to1.stable_idel_cnt[2]_i_4_n_0\
    );
\mpr_4to1.stable_idel_cnt[2]_i_5\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6FF6"
    )
        port map (
      I0 => \gen_mux_rd[0].mux_rd_fall3_r_reg_n_0_[0]\,
      I1 => mpr_rd_fall3_prev_r,
      I2 => \gen_mux_rd[0].mux_rd_rise0_r_reg_n_0_[0]\,
      I3 => mpr_rd_rise0_prev_r,
      O => \mpr_4to1.stable_idel_cnt[2]_i_5_n_0\
    );
\mpr_4to1.stable_idel_cnt[2]_i_6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFF6FF6"
    )
        port map (
      I0 => mpr_rd_rise2_prev_r,
      I1 => \gen_mux_rd[0].mux_rd_rise2_r_reg_n_0_[0]\,
      I2 => mpr_rd_fall0_prev_r,
      I3 => \gen_mux_rd[0].mux_rd_fall0_r_reg_n_0_[0]\,
      I4 => \mpr_4to1.stable_idel_cnt[2]_i_7_n_0\,
      O => \mpr_4to1.stable_idel_cnt[2]_i_6_n_0\
    );
\mpr_4to1.stable_idel_cnt[2]_i_7\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6FF6"
    )
        port map (
      I0 => \gen_mux_rd[0].mux_rd_fall2_r_reg_n_0_[0]\,
      I1 => mpr_rd_fall2_prev_r,
      I2 => \gen_mux_rd[0].mux_rd_rise1_r_reg_n_0_[0]\,
      I3 => mpr_rd_rise1_prev_r,
      O => \mpr_4to1.stable_idel_cnt[2]_i_7_n_0\
    );
\mpr_4to1.stable_idel_cnt_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \mpr_4to1.stable_idel_cnt[0]_i_1_n_0\,
      Q => \mpr_4to1.stable_idel_cnt_reg_n_0_[0]\,
      R => '0'
    );
\mpr_4to1.stable_idel_cnt_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \mpr_4to1.stable_idel_cnt[1]_i_1_n_0\,
      Q => \mpr_4to1.stable_idel_cnt_reg_n_0_[1]\,
      R => '0'
    );
\mpr_4to1.stable_idel_cnt_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \mpr_4to1.stable_idel_cnt[2]_i_1_n_0\,
      Q => \mpr_4to1.stable_idel_cnt_reg_n_0_[2]\,
      R => '0'
    );
mpr_dec_cpt_r_i_1: unisim.vcomponents.LUT3
    generic map(
      INIT => X"DC"
    )
        port map (
      I0 => \FSM_onehot_cal1_state_r_reg_n_0_[16]\,
      I1 => mpr_dec_cpt_r,
      I2 => mpr_dec_cpt_r_reg_n_0,
      O => mpr_dec_cpt_r_i_1_n_0
    );
mpr_dec_cpt_r_reg: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => mpr_dec_cpt_r_i_1_n_0,
      Q => mpr_dec_cpt_r_reg_n_0,
      R => \rdlvl_dqs_tap_cnt_r_reg[0][0][2]_0\(1)
    );
mpr_rd_fall0_prev_r_reg: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => mpr_rd_rise0_prev_r0,
      D => \gen_mux_rd[0].mux_rd_fall0_r_reg_n_0_[0]\,
      Q => mpr_rd_fall0_prev_r,
      R => '0'
    );
mpr_rd_fall1_prev_r_reg: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => mpr_rd_rise0_prev_r0,
      D => \gen_mux_rd[0].mux_rd_fall1_r_reg_n_0_[0]\,
      Q => mpr_rd_fall1_prev_r,
      R => '0'
    );
mpr_rd_fall2_prev_r_reg: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => mpr_rd_rise0_prev_r0,
      D => \gen_mux_rd[0].mux_rd_fall2_r_reg_n_0_[0]\,
      Q => mpr_rd_fall2_prev_r,
      R => '0'
    );
mpr_rd_fall3_prev_r_reg: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => mpr_rd_rise0_prev_r0,
      D => \gen_mux_rd[0].mux_rd_fall3_r_reg_n_0_[0]\,
      Q => mpr_rd_fall3_prev_r,
      R => '0'
    );
mpr_rd_rise0_prev_r_reg: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => mpr_rd_rise0_prev_r0,
      D => \gen_mux_rd[0].mux_rd_rise0_r_reg_n_0_[0]\,
      Q => mpr_rd_rise0_prev_r,
      R => '0'
    );
mpr_rd_rise1_prev_r_i_1: unisim.vcomponents.LUT3
    generic map(
      INIT => X"EA"
    )
        port map (
      I0 => p_1_in26_in,
      I1 => p_0_in549_in,
      I2 => idel_pat_detect_valid_r_reg_n_0,
      O => mpr_rd_rise0_prev_r0
    );
mpr_rd_rise1_prev_r_reg: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => mpr_rd_rise0_prev_r0,
      D => \gen_mux_rd[0].mux_rd_rise1_r_reg_n_0_[0]\,
      Q => mpr_rd_rise1_prev_r,
      R => '0'
    );
mpr_rd_rise2_prev_r_reg: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => mpr_rd_rise0_prev_r0,
      D => \gen_mux_rd[0].mux_rd_rise2_r_reg_n_0_[0]\,
      Q => mpr_rd_rise2_prev_r,
      R => '0'
    );
mpr_rd_rise3_prev_r_reg: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => mpr_rd_rise0_prev_r0,
      D => \gen_mux_rd[0].mux_rd_rise3_r_reg_n_0_[0]\,
      Q => mpr_rd_rise3_prev_r,
      R => '0'
    );
mpr_rdlvl_start_r_reg: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => mpr_rdlvl_start_r_reg_0,
      Q => mpr_rdlvl_start_r,
      R => '0'
    );
new_cnt_cpt_r_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAAAEAEEAAAA"
    )
        port map (
      I0 => new_cnt_cpt_r_i_2_n_0,
      I1 => \FSM_onehot_cal1_state_r_reg_n_0_[7]\,
      I2 => mpr_rdlvl_start_r,
      I3 => mpr_rdlvl_start_r_reg_0,
      I4 => rdlvl_stg1_start_r_reg_0,
      I5 => rdlvl_stg1_start_r,
      O => new_cnt_cpt_r
    );
new_cnt_cpt_r_i_2: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0888888888888888"
    )
        port map (
      I0 => prech_done,
      I1 => cal1_prech_req_r,
      I2 => \cal1_cnt_cpt_r_reg_n_0_[2]\,
      I3 => \cal1_cnt_cpt_r[2]_i_3_n_0\,
      I4 => \cal1_cnt_cpt_r_reg_n_0_[0]\,
      I5 => \cal1_cnt_cpt_r_reg_n_0_[1]\,
      O => new_cnt_cpt_r_i_2_n_0
    );
new_cnt_cpt_r_reg: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => new_cnt_cpt_r,
      Q => \^new_cnt_cpt_r_reg_0\,
      R => \rdlvl_dqs_tap_cnt_r_reg[0][0][2]_0\(1)
    );
pi_cnt_dec_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000040000"
    )
        port map (
      I0 => pi_cnt_dec_i_2_n_0,
      I1 => dqs_po_dec_done_r2,
      I2 => pi_stg2_f_incdec_timing_reg_0,
      I3 => wait_cnt_r_reg(1),
      I4 => wait_cnt_r_reg(0),
      I5 => \pi_rdval_cnt[5]_i_3_n_0\,
      O => pi_cnt_dec_i_1_n_0
    );
pi_cnt_dec_i_2: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => wait_cnt_r_reg(2),
      I1 => wait_cnt_r_reg(3),
      O => pi_cnt_dec_i_2_n_0
    );
pi_cnt_dec_reg: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => pi_cnt_dec_i_1_n_0,
      Q => \^pi_cnt_dec_reg_0\,
      R => '0'
    );
pi_en_stg2_f_reg: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => pi_en_stg2_f_timing,
      Q => rdlvl_pi_stg2_f_en,
      R => '0'
    );
pi_en_stg2_f_timing_i_1: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => cal1_dlyce_cpt_r_reg_n_0,
      I1 => \^pi_cnt_dec_reg_0\,
      O => pi_en_stg2_f_timing_i_1_n_0
    );
pi_en_stg2_f_timing_reg: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => pi_en_stg2_f_timing_i_1_n_0,
      Q => pi_en_stg2_f_timing,
      R => SR(1)
    );
pi_fine_dly_dec_done_reg: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => fine_dly_dec_done_r2,
      Q => \^pi_fine_dly_dec_done\,
      R => '0'
    );
\pi_rdval_cnt[0]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"080808FB"
    )
        port map (
      I0 => D(0),
      I1 => dqs_po_dec_done_r1,
      I2 => dqs_po_dec_done_r2,
      I3 => pi_rdval_cnt(0),
      I4 => \pi_rdval_cnt[5]_i_3_n_0\,
      O => \pi_rdval_cnt[0]_i_1_n_0\
    );
\pi_rdval_cnt[1]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"08FB0808080808FB"
    )
        port map (
      I0 => D(1),
      I1 => dqs_po_dec_done_r1,
      I2 => dqs_po_dec_done_r2,
      I3 => \pi_rdval_cnt[5]_i_3_n_0\,
      I4 => pi_rdval_cnt(0),
      I5 => pi_rdval_cnt(1),
      O => \pi_rdval_cnt[1]_i_1_n_0\
    );
\pi_rdval_cnt[2]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"88888888BBB8888B"
    )
        port map (
      I0 => D(2),
      I1 => \pi_rdval_cnt[3]_i_2_n_0\,
      I2 => pi_rdval_cnt(1),
      I3 => pi_rdval_cnt(0),
      I4 => pi_rdval_cnt(2),
      I5 => \pi_rdval_cnt[5]_i_3_n_0\,
      O => \pi_rdval_cnt[2]_i_1_n_0\
    );
\pi_rdval_cnt[3]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"88888888BB8B88B8"
    )
        port map (
      I0 => D(3),
      I1 => \pi_rdval_cnt[3]_i_2_n_0\,
      I2 => \pi_rdval_cnt[3]_i_3_n_0\,
      I3 => pi_rdval_cnt(2),
      I4 => pi_rdval_cnt(3),
      I5 => \pi_rdval_cnt[5]_i_3_n_0\,
      O => \pi_rdval_cnt[3]_i_1_n_0\
    );
\pi_rdval_cnt[3]_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => dqs_po_dec_done_r1,
      I1 => dqs_po_dec_done_r2,
      O => \pi_rdval_cnt[3]_i_2_n_0\
    );
\pi_rdval_cnt[3]_i_3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => pi_rdval_cnt(1),
      I1 => pi_rdval_cnt(0),
      O => \pi_rdval_cnt[3]_i_3_n_0\
    );
\pi_rdval_cnt[4]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"08FB0808FB08FB08"
    )
        port map (
      I0 => D(4),
      I1 => dqs_po_dec_done_r1,
      I2 => dqs_po_dec_done_r2,
      I3 => pi_rdval_cnt(4),
      I4 => pi_rdval_cnt(5),
      I5 => \pi_rdval_cnt[5]_i_4_n_0\,
      O => \pi_rdval_cnt[4]_i_1_n_0\
    );
\pi_rdval_cnt[5]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFAE"
    )
        port map (
      I0 => \^pi_cnt_dec_reg_0\,
      I1 => dqs_po_dec_done_r1,
      I2 => dqs_po_dec_done_r2,
      I3 => \pi_rdval_cnt[5]_i_3_n_0\,
      O => \pi_rdval_cnt[5]_i_1_n_0\
    );
\pi_rdval_cnt[5]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FB080808FB08FB08"
    )
        port map (
      I0 => D(5),
      I1 => dqs_po_dec_done_r1,
      I2 => dqs_po_dec_done_r2,
      I3 => pi_rdval_cnt(5),
      I4 => pi_rdval_cnt(4),
      I5 => \pi_rdval_cnt[5]_i_4_n_0\,
      O => \pi_rdval_cnt[5]_i_2_n_0\
    );
\pi_rdval_cnt[5]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000000001"
    )
        port map (
      I0 => pi_rdval_cnt(3),
      I1 => pi_rdval_cnt(2),
      I2 => pi_rdval_cnt(1),
      I3 => pi_rdval_cnt(0),
      I4 => pi_rdval_cnt(5),
      I5 => pi_rdval_cnt(4),
      O => \pi_rdval_cnt[5]_i_3_n_0\
    );
\pi_rdval_cnt[5]_i_4\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0001"
    )
        port map (
      I0 => pi_rdval_cnt(0),
      I1 => pi_rdval_cnt(1),
      I2 => pi_rdval_cnt(2),
      I3 => pi_rdval_cnt(3),
      O => \pi_rdval_cnt[5]_i_4_n_0\
    );
\pi_rdval_cnt_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => \pi_rdval_cnt[5]_i_1_n_0\,
      D => \pi_rdval_cnt[0]_i_1_n_0\,
      Q => pi_rdval_cnt(0),
      R => \rdlvl_dqs_tap_cnt_r_reg[0][0][2]_0\(1)
    );
\pi_rdval_cnt_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => \pi_rdval_cnt[5]_i_1_n_0\,
      D => \pi_rdval_cnt[1]_i_1_n_0\,
      Q => pi_rdval_cnt(1),
      R => \rdlvl_dqs_tap_cnt_r_reg[0][0][2]_0\(1)
    );
\pi_rdval_cnt_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => \pi_rdval_cnt[5]_i_1_n_0\,
      D => \pi_rdval_cnt[2]_i_1_n_0\,
      Q => pi_rdval_cnt(2),
      R => \rdlvl_dqs_tap_cnt_r_reg[0][0][2]_0\(1)
    );
\pi_rdval_cnt_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => \pi_rdval_cnt[5]_i_1_n_0\,
      D => \pi_rdval_cnt[3]_i_1_n_0\,
      Q => pi_rdval_cnt(3),
      R => \rdlvl_dqs_tap_cnt_r_reg[0][0][2]_0\(1)
    );
\pi_rdval_cnt_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => \pi_rdval_cnt[5]_i_1_n_0\,
      D => \pi_rdval_cnt[4]_i_1_n_0\,
      Q => pi_rdval_cnt(4),
      R => \rdlvl_dqs_tap_cnt_r_reg[0][0][2]_0\(1)
    );
\pi_rdval_cnt_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => \pi_rdval_cnt[5]_i_1_n_0\,
      D => \pi_rdval_cnt[5]_i_2_n_0\,
      Q => pi_rdval_cnt(5),
      R => \rdlvl_dqs_tap_cnt_r_reg[0][0][2]_0\(1)
    );
pi_stg2_f_incdec_reg: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => pi_stg2_f_incdec_timing,
      Q => rdlvl_pi_stg2_f_incdec,
      R => '0'
    );
pi_stg2_f_incdec_timing_i_1: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0008"
    )
        port map (
      I0 => cal1_dlyce_cpt_r_reg_n_0,
      I1 => cal1_dlyinc_cpt_r_reg_n_0,
      I2 => \^pi_cnt_dec_reg_0\,
      I3 => pi_stg2_f_incdec_timing_reg_0,
      O => pi_stg2_f_incdec_timing_i_1_n_0
    );
pi_stg2_f_incdec_timing_reg: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => pi_stg2_f_incdec_timing_i_1_n_0,
      Q => pi_stg2_f_incdec_timing,
      R => '0'
    );
pi_stg2_load_reg: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => pi_stg2_load_timing,
      Q => pi_stg2_load_reg_0,
      R => '0'
    );
pi_stg2_load_timing_i_1: unisim.vcomponents.LUT3
    generic map(
      INIT => X"04"
    )
        port map (
      I0 => regl_dqs_cnt(3),
      I1 => \pi_stg2_reg_l_timing[5]_i_3_n_0\,
      I2 => \regl_rank_cnt[1]_i_3_n_0\,
      O => pi_stg2_load_timing_i_1_n_0
    );
pi_stg2_load_timing_reg: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => pi_stg2_load_timing_i_1_n_0,
      Q => pi_stg2_load_timing,
      R => '0'
    );
\pi_stg2_reg_l_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => pi_stg2_reg_l_timing(0),
      Q => \pi_stg2_reg_l_reg[5]_0\(0),
      R => '0'
    );
\pi_stg2_reg_l_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => pi_stg2_reg_l_timing(1),
      Q => \pi_stg2_reg_l_reg[5]_0\(1),
      R => '0'
    );
\pi_stg2_reg_l_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => pi_stg2_reg_l_timing(2),
      Q => \pi_stg2_reg_l_reg[5]_0\(2),
      R => '0'
    );
\pi_stg2_reg_l_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => pi_stg2_reg_l_timing(3),
      Q => \pi_stg2_reg_l_reg[5]_0\(3),
      R => '0'
    );
\pi_stg2_reg_l_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => pi_stg2_reg_l_timing(4),
      Q => \pi_stg2_reg_l_reg[5]_0\(4),
      R => '0'
    );
\pi_stg2_reg_l_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => pi_stg2_reg_l_timing(5),
      Q => \pi_stg2_reg_l_reg[5]_0\(5),
      R => '0'
    );
\pi_stg2_reg_l_timing[0]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][3][0]\,
      I1 => \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][2][0]\,
      I2 => regl_dqs_cnt(1),
      I3 => \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][1][0]\,
      I4 => regl_dqs_cnt(0),
      I5 => \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][0][0]\,
      O => \pi_stg2_reg_l_timing[0]_i_2_n_0\
    );
\pi_stg2_reg_l_timing[0]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][7][0]\,
      I1 => \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][6][0]\,
      I2 => regl_dqs_cnt(1),
      I3 => \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][5][0]\,
      I4 => regl_dqs_cnt(0),
      I5 => \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][4][0]\,
      O => \pi_stg2_reg_l_timing[0]_i_3_n_0\
    );
\pi_stg2_reg_l_timing[1]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][3][1]\,
      I1 => \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][2][1]\,
      I2 => regl_dqs_cnt(1),
      I3 => \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][1][1]\,
      I4 => regl_dqs_cnt(0),
      I5 => \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][0][1]\,
      O => \pi_stg2_reg_l_timing[1]_i_2_n_0\
    );
\pi_stg2_reg_l_timing[1]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][7][1]\,
      I1 => \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][6][1]\,
      I2 => regl_dqs_cnt(1),
      I3 => \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][5][1]\,
      I4 => regl_dqs_cnt(0),
      I5 => \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][4][1]\,
      O => \pi_stg2_reg_l_timing[1]_i_3_n_0\
    );
\pi_stg2_reg_l_timing[2]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][3][2]\,
      I1 => \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][2][2]\,
      I2 => regl_dqs_cnt(1),
      I3 => \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][1][2]\,
      I4 => regl_dqs_cnt(0),
      I5 => \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][0][2]\,
      O => \pi_stg2_reg_l_timing[2]_i_2_n_0\
    );
\pi_stg2_reg_l_timing[2]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][7][2]\,
      I1 => \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][6][2]\,
      I2 => regl_dqs_cnt(1),
      I3 => \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][5][2]\,
      I4 => regl_dqs_cnt(0),
      I5 => \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][4][2]\,
      O => \pi_stg2_reg_l_timing[2]_i_3_n_0\
    );
\pi_stg2_reg_l_timing[3]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][3][3]\,
      I1 => \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][2][3]\,
      I2 => regl_dqs_cnt(1),
      I3 => \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][1][3]\,
      I4 => regl_dqs_cnt(0),
      I5 => \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][0][3]\,
      O => \pi_stg2_reg_l_timing[3]_i_2_n_0\
    );
\pi_stg2_reg_l_timing[3]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][7][3]\,
      I1 => \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][6][3]\,
      I2 => regl_dqs_cnt(1),
      I3 => \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][5][3]\,
      I4 => regl_dqs_cnt(0),
      I5 => \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][4][3]\,
      O => \pi_stg2_reg_l_timing[3]_i_3_n_0\
    );
\pi_stg2_reg_l_timing[4]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][3][4]\,
      I1 => \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][2][4]\,
      I2 => regl_dqs_cnt(1),
      I3 => \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][1][4]\,
      I4 => regl_dqs_cnt(0),
      I5 => \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][0][4]\,
      O => \pi_stg2_reg_l_timing[4]_i_2_n_0\
    );
\pi_stg2_reg_l_timing[4]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][7][4]\,
      I1 => \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][6][4]\,
      I2 => regl_dqs_cnt(1),
      I3 => \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][5][4]\,
      I4 => regl_dqs_cnt(0),
      I5 => \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][4][4]\,
      O => \pi_stg2_reg_l_timing[4]_i_3_n_0\
    );
\pi_stg2_reg_l_timing[5]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"EF"
    )
        port map (
      I0 => \regl_rank_cnt[1]_i_3_n_0\,
      I1 => regl_dqs_cnt(3),
      I2 => \pi_stg2_reg_l_timing[5]_i_3_n_0\,
      O => \pi_stg2_reg_l_timing[5]_i_1_n_0\
    );
\pi_stg2_reg_l_timing[5]_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00020000"
    )
        port map (
      I0 => p_0_in541_in,
      I1 => done_cnt(2),
      I2 => done_cnt(3),
      I3 => done_cnt(1),
      I4 => done_cnt(0),
      O => \pi_stg2_reg_l_timing[5]_i_3_n_0\
    );
\pi_stg2_reg_l_timing[5]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][3][5]\,
      I1 => \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][2][5]\,
      I2 => regl_dqs_cnt(1),
      I3 => \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][1][5]\,
      I4 => regl_dqs_cnt(0),
      I5 => \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][0][5]\,
      O => \pi_stg2_reg_l_timing[5]_i_4_n_0\
    );
\pi_stg2_reg_l_timing[5]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][7][5]\,
      I1 => \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][6][5]\,
      I2 => regl_dqs_cnt(1),
      I3 => \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][5][5]\,
      I4 => regl_dqs_cnt(0),
      I5 => \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][4][5]\,
      O => \pi_stg2_reg_l_timing[5]_i_5_n_0\
    );
\pi_stg2_reg_l_timing_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => rdlvl_dqs_tap_cnt_r(0),
      Q => pi_stg2_reg_l_timing(0),
      R => \pi_stg2_reg_l_timing[5]_i_1_n_0\
    );
\pi_stg2_reg_l_timing_reg[0]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \pi_stg2_reg_l_timing[0]_i_2_n_0\,
      I1 => \pi_stg2_reg_l_timing[0]_i_3_n_0\,
      O => rdlvl_dqs_tap_cnt_r(0),
      S => regl_dqs_cnt(2)
    );
\pi_stg2_reg_l_timing_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => rdlvl_dqs_tap_cnt_r(1),
      Q => pi_stg2_reg_l_timing(1),
      R => \pi_stg2_reg_l_timing[5]_i_1_n_0\
    );
\pi_stg2_reg_l_timing_reg[1]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \pi_stg2_reg_l_timing[1]_i_2_n_0\,
      I1 => \pi_stg2_reg_l_timing[1]_i_3_n_0\,
      O => rdlvl_dqs_tap_cnt_r(1),
      S => regl_dqs_cnt(2)
    );
\pi_stg2_reg_l_timing_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => rdlvl_dqs_tap_cnt_r(2),
      Q => pi_stg2_reg_l_timing(2),
      R => \pi_stg2_reg_l_timing[5]_i_1_n_0\
    );
\pi_stg2_reg_l_timing_reg[2]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \pi_stg2_reg_l_timing[2]_i_2_n_0\,
      I1 => \pi_stg2_reg_l_timing[2]_i_3_n_0\,
      O => rdlvl_dqs_tap_cnt_r(2),
      S => regl_dqs_cnt(2)
    );
\pi_stg2_reg_l_timing_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => rdlvl_dqs_tap_cnt_r(3),
      Q => pi_stg2_reg_l_timing(3),
      R => \pi_stg2_reg_l_timing[5]_i_1_n_0\
    );
\pi_stg2_reg_l_timing_reg[3]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \pi_stg2_reg_l_timing[3]_i_2_n_0\,
      I1 => \pi_stg2_reg_l_timing[3]_i_3_n_0\,
      O => rdlvl_dqs_tap_cnt_r(3),
      S => regl_dqs_cnt(2)
    );
\pi_stg2_reg_l_timing_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => rdlvl_dqs_tap_cnt_r(4),
      Q => pi_stg2_reg_l_timing(4),
      R => \pi_stg2_reg_l_timing[5]_i_1_n_0\
    );
\pi_stg2_reg_l_timing_reg[4]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \pi_stg2_reg_l_timing[4]_i_2_n_0\,
      I1 => \pi_stg2_reg_l_timing[4]_i_3_n_0\,
      O => rdlvl_dqs_tap_cnt_r(4),
      S => regl_dqs_cnt(2)
    );
\pi_stg2_reg_l_timing_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => rdlvl_dqs_tap_cnt_r(5),
      Q => pi_stg2_reg_l_timing(5),
      R => \pi_stg2_reg_l_timing[5]_i_1_n_0\
    );
\pi_stg2_reg_l_timing_reg[5]_i_2\: unisim.vcomponents.MUXF7
     port map (
      I0 => \pi_stg2_reg_l_timing[5]_i_4_n_0\,
      I1 => \pi_stg2_reg_l_timing[5]_i_5_n_0\,
      O => rdlvl_dqs_tap_cnt_r(5),
      S => regl_dqs_cnt(2)
    );
prech_req_r_i_1: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFEFEFE"
    )
        port map (
      I0 => \^rdlvl_prech_req\,
      I1 => wrcal_prech_req,
      I2 => prech_req_r_reg,
      I3 => dqs_found_prech_req,
      I4 => prech_req_r_reg_0,
      O => prech_req
    );
\rd_mux_sel_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \cal1_cnt_cpt_r_reg_n_0_[0]\,
      Q => \^q\(0),
      R => '0'
    );
\rd_mux_sel_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \cal1_cnt_cpt_r_reg_n_0_[1]\,
      Q => \^q\(1),
      R => '0'
    );
\rd_mux_sel_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \cal1_cnt_cpt_r_reg_n_0_[2]\,
      Q => \rd_mux_sel_r_reg_n_0_[2]\,
      R => '0'
    );
\rdlvl_dqs_tap_cnt_r[0][0][5]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000000001"
    )
        port map (
      I0 => \^q\(1),
      I1 => \^q\(0),
      I2 => \rd_mux_sel_r_reg_n_0_[2]\,
      I3 => \rnk_cnt_r_reg_n_0_[0]\,
      I4 => \rnk_cnt_r_reg_n_0_[1]\,
      I5 => \rdlvl_dqs_tap_cnt_r[0][0][5]_i_2_n_0\,
      O => \rdlvl_dqs_tap_cnt_r[0][0][5]_i_1_n_0\
    );
\rdlvl_dqs_tap_cnt_r[0][0][5]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FEFFFFFFFFFFFFFF"
    )
        port map (
      I0 => \cal1_state_r1_reg_n_0_[4]\,
      I1 => \cal1_state_r1_reg_n_0_[5]\,
      I2 => \cal1_state_r1_reg_n_0_[0]\,
      I3 => \cal1_state_r1_reg_n_0_[2]\,
      I4 => \cal1_state_r1_reg_n_0_[1]\,
      I5 => \cal1_state_r1_reg_n_0_[3]\,
      O => \rdlvl_dqs_tap_cnt_r[0][0][5]_i_2_n_0\
    );
\rdlvl_dqs_tap_cnt_r[0][1][5]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000100000000"
    )
        port map (
      I0 => \rd_mux_sel_r_reg_n_0_[2]\,
      I1 => \rnk_cnt_r_reg_n_0_[0]\,
      I2 => \rnk_cnt_r_reg_n_0_[1]\,
      I3 => \rdlvl_dqs_tap_cnt_r[0][0][5]_i_2_n_0\,
      I4 => \^q\(1),
      I5 => \^q\(0),
      O => \rdlvl_dqs_tap_cnt_r[0][1][5]_i_1_n_0\
    );
\rdlvl_dqs_tap_cnt_r[0][2][5]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000100000000"
    )
        port map (
      I0 => \rd_mux_sel_r_reg_n_0_[2]\,
      I1 => \rnk_cnt_r_reg_n_0_[0]\,
      I2 => \rnk_cnt_r_reg_n_0_[1]\,
      I3 => \rdlvl_dqs_tap_cnt_r[0][0][5]_i_2_n_0\,
      I4 => \^q\(0),
      I5 => \^q\(1),
      O => \rdlvl_dqs_tap_cnt_r[0][2][5]_i_1_n_0\
    );
\rdlvl_dqs_tap_cnt_r[0][3][5]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0001000000000000"
    )
        port map (
      I0 => \rd_mux_sel_r_reg_n_0_[2]\,
      I1 => \rnk_cnt_r_reg_n_0_[0]\,
      I2 => \rnk_cnt_r_reg_n_0_[1]\,
      I3 => \rdlvl_dqs_tap_cnt_r[0][0][5]_i_2_n_0\,
      I4 => \^q\(1),
      I5 => \^q\(0),
      O => \rdlvl_dqs_tap_cnt_r[0][3][5]_i_1_n_0\
    );
\rdlvl_dqs_tap_cnt_r[0][4][5]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000000010"
    )
        port map (
      I0 => \^q\(1),
      I1 => \^q\(0),
      I2 => \rd_mux_sel_r_reg_n_0_[2]\,
      I3 => \rnk_cnt_r_reg_n_0_[0]\,
      I4 => \rnk_cnt_r_reg_n_0_[1]\,
      I5 => \rdlvl_dqs_tap_cnt_r[0][0][5]_i_2_n_0\,
      O => \rdlvl_dqs_tap_cnt_r[0][4][5]_i_1_n_0\
    );
\rdlvl_dqs_tap_cnt_r[0][5][5]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000000040"
    )
        port map (
      I0 => \^q\(1),
      I1 => \^q\(0),
      I2 => \rd_mux_sel_r_reg_n_0_[2]\,
      I3 => \rnk_cnt_r_reg_n_0_[0]\,
      I4 => \rnk_cnt_r_reg_n_0_[1]\,
      I5 => \rdlvl_dqs_tap_cnt_r[0][0][5]_i_2_n_0\,
      O => \rdlvl_dqs_tap_cnt_r[0][5][5]_i_1_n_0\
    );
\rdlvl_dqs_tap_cnt_r[0][6][5]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000000040"
    )
        port map (
      I0 => \^q\(0),
      I1 => \^q\(1),
      I2 => \rd_mux_sel_r_reg_n_0_[2]\,
      I3 => \rnk_cnt_r_reg_n_0_[0]\,
      I4 => \rnk_cnt_r_reg_n_0_[1]\,
      I5 => \rdlvl_dqs_tap_cnt_r[0][0][5]_i_2_n_0\,
      O => \rdlvl_dqs_tap_cnt_r[0][6][5]_i_1_n_0\
    );
\rdlvl_dqs_tap_cnt_r[0][7][5]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000000080"
    )
        port map (
      I0 => \^q\(1),
      I1 => \^q\(0),
      I2 => \rd_mux_sel_r_reg_n_0_[2]\,
      I3 => \rnk_cnt_r_reg_n_0_[0]\,
      I4 => \rnk_cnt_r_reg_n_0_[1]\,
      I5 => \rdlvl_dqs_tap_cnt_r[0][0][5]_i_2_n_0\,
      O => \rdlvl_dqs_tap_cnt_r[0][7][5]_i_1_n_0\
    );
\rdlvl_dqs_tap_cnt_r_reg[0][0][0]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => \rdlvl_dqs_tap_cnt_r[0][0][5]_i_1_n_0\,
      D => \tap_cnt_cpt_r_reg_n_0_[0]\,
      Q => \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][0][0]\,
      R => \rdlvl_dqs_tap_cnt_r_reg[0][0][2]_0\(0)
    );
\rdlvl_dqs_tap_cnt_r_reg[0][0][1]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => \rdlvl_dqs_tap_cnt_r[0][0][5]_i_1_n_0\,
      D => \tap_cnt_cpt_r_reg_n_0_[1]\,
      Q => \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][0][1]\,
      R => \rdlvl_dqs_tap_cnt_r_reg[0][0][2]_0\(0)
    );
\rdlvl_dqs_tap_cnt_r_reg[0][0][2]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => \rdlvl_dqs_tap_cnt_r[0][0][5]_i_1_n_0\,
      D => \tap_cnt_cpt_r_reg_n_0_[2]\,
      Q => \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][0][2]\,
      R => \rdlvl_dqs_tap_cnt_r_reg[0][0][2]_0\(1)
    );
\rdlvl_dqs_tap_cnt_r_reg[0][0][3]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => \rdlvl_dqs_tap_cnt_r[0][0][5]_i_1_n_0\,
      D => \tap_cnt_cpt_r_reg_n_0_[3]\,
      Q => \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][0][3]\,
      R => \rdlvl_dqs_tap_cnt_r_reg[0][0][2]_0\(1)
    );
\rdlvl_dqs_tap_cnt_r_reg[0][0][4]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => \rdlvl_dqs_tap_cnt_r[0][0][5]_i_1_n_0\,
      D => \tap_cnt_cpt_r_reg_n_0_[4]\,
      Q => \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][0][4]\,
      R => \rdlvl_dqs_tap_cnt_r_reg[0][0][2]_0\(1)
    );
\rdlvl_dqs_tap_cnt_r_reg[0][0][5]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => \rdlvl_dqs_tap_cnt_r[0][0][5]_i_1_n_0\,
      D => \tap_cnt_cpt_r_reg_n_0_[5]\,
      Q => \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][0][5]\,
      R => \rdlvl_dqs_tap_cnt_r_reg[0][0][2]_0\(1)
    );
\rdlvl_dqs_tap_cnt_r_reg[0][1][0]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => \rdlvl_dqs_tap_cnt_r[0][1][5]_i_1_n_0\,
      D => \tap_cnt_cpt_r_reg_n_0_[0]\,
      Q => \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][1][0]\,
      R => SR(1)
    );
\rdlvl_dqs_tap_cnt_r_reg[0][1][1]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => \rdlvl_dqs_tap_cnt_r[0][1][5]_i_1_n_0\,
      D => \tap_cnt_cpt_r_reg_n_0_[1]\,
      Q => \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][1][1]\,
      R => SR(1)
    );
\rdlvl_dqs_tap_cnt_r_reg[0][1][2]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => \rdlvl_dqs_tap_cnt_r[0][1][5]_i_1_n_0\,
      D => \tap_cnt_cpt_r_reg_n_0_[2]\,
      Q => \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][1][2]\,
      R => SR(1)
    );
\rdlvl_dqs_tap_cnt_r_reg[0][1][3]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => \rdlvl_dqs_tap_cnt_r[0][1][5]_i_1_n_0\,
      D => \tap_cnt_cpt_r_reg_n_0_[3]\,
      Q => \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][1][3]\,
      R => SR(1)
    );
\rdlvl_dqs_tap_cnt_r_reg[0][1][4]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => \rdlvl_dqs_tap_cnt_r[0][1][5]_i_1_n_0\,
      D => \tap_cnt_cpt_r_reg_n_0_[4]\,
      Q => \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][1][4]\,
      R => SR(1)
    );
\rdlvl_dqs_tap_cnt_r_reg[0][1][5]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => \rdlvl_dqs_tap_cnt_r[0][1][5]_i_1_n_0\,
      D => \tap_cnt_cpt_r_reg_n_0_[5]\,
      Q => \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][1][5]\,
      R => SR(1)
    );
\rdlvl_dqs_tap_cnt_r_reg[0][2][0]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => \rdlvl_dqs_tap_cnt_r[0][2][5]_i_1_n_0\,
      D => \tap_cnt_cpt_r_reg_n_0_[0]\,
      Q => \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][2][0]\,
      R => \rdlvl_dqs_tap_cnt_r_reg[0][0][2]_0\(0)
    );
\rdlvl_dqs_tap_cnt_r_reg[0][2][1]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => \rdlvl_dqs_tap_cnt_r[0][2][5]_i_1_n_0\,
      D => \tap_cnt_cpt_r_reg_n_0_[1]\,
      Q => \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][2][1]\,
      R => \rdlvl_dqs_tap_cnt_r_reg[0][0][2]_0\(0)
    );
\rdlvl_dqs_tap_cnt_r_reg[0][2][2]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => \rdlvl_dqs_tap_cnt_r[0][2][5]_i_1_n_0\,
      D => \tap_cnt_cpt_r_reg_n_0_[2]\,
      Q => \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][2][2]\,
      R => \rdlvl_dqs_tap_cnt_r_reg[0][0][2]_0\(0)
    );
\rdlvl_dqs_tap_cnt_r_reg[0][2][3]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => \rdlvl_dqs_tap_cnt_r[0][2][5]_i_1_n_0\,
      D => \tap_cnt_cpt_r_reg_n_0_[3]\,
      Q => \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][2][3]\,
      R => \rdlvl_dqs_tap_cnt_r_reg[0][0][2]_0\(0)
    );
\rdlvl_dqs_tap_cnt_r_reg[0][2][4]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => \rdlvl_dqs_tap_cnt_r[0][2][5]_i_1_n_0\,
      D => \tap_cnt_cpt_r_reg_n_0_[4]\,
      Q => \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][2][4]\,
      R => \rdlvl_dqs_tap_cnt_r_reg[0][0][2]_0\(0)
    );
\rdlvl_dqs_tap_cnt_r_reg[0][2][5]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => \rdlvl_dqs_tap_cnt_r[0][2][5]_i_1_n_0\,
      D => \tap_cnt_cpt_r_reg_n_0_[5]\,
      Q => \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][2][5]\,
      R => \rdlvl_dqs_tap_cnt_r_reg[0][0][2]_0\(0)
    );
\rdlvl_dqs_tap_cnt_r_reg[0][3][0]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => \rdlvl_dqs_tap_cnt_r[0][3][5]_i_1_n_0\,
      D => \tap_cnt_cpt_r_reg_n_0_[0]\,
      Q => \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][3][0]\,
      R => SR(1)
    );
\rdlvl_dqs_tap_cnt_r_reg[0][3][1]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => \rdlvl_dqs_tap_cnt_r[0][3][5]_i_1_n_0\,
      D => \tap_cnt_cpt_r_reg_n_0_[1]\,
      Q => \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][3][1]\,
      R => SR(1)
    );
\rdlvl_dqs_tap_cnt_r_reg[0][3][2]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => \rdlvl_dqs_tap_cnt_r[0][3][5]_i_1_n_0\,
      D => \tap_cnt_cpt_r_reg_n_0_[2]\,
      Q => \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][3][2]\,
      R => SR(1)
    );
\rdlvl_dqs_tap_cnt_r_reg[0][3][3]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => \rdlvl_dqs_tap_cnt_r[0][3][5]_i_1_n_0\,
      D => \tap_cnt_cpt_r_reg_n_0_[3]\,
      Q => \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][3][3]\,
      R => SR(1)
    );
\rdlvl_dqs_tap_cnt_r_reg[0][3][4]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => \rdlvl_dqs_tap_cnt_r[0][3][5]_i_1_n_0\,
      D => \tap_cnt_cpt_r_reg_n_0_[4]\,
      Q => \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][3][4]\,
      R => SR(1)
    );
\rdlvl_dqs_tap_cnt_r_reg[0][3][5]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => \rdlvl_dqs_tap_cnt_r[0][3][5]_i_1_n_0\,
      D => \tap_cnt_cpt_r_reg_n_0_[5]\,
      Q => \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][3][5]\,
      R => SR(1)
    );
\rdlvl_dqs_tap_cnt_r_reg[0][4][0]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => \rdlvl_dqs_tap_cnt_r[0][4][5]_i_1_n_0\,
      D => \tap_cnt_cpt_r_reg_n_0_[0]\,
      Q => \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][4][0]\,
      R => \rdlvl_dqs_tap_cnt_r_reg[0][0][2]_0\(0)
    );
\rdlvl_dqs_tap_cnt_r_reg[0][4][1]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => \rdlvl_dqs_tap_cnt_r[0][4][5]_i_1_n_0\,
      D => \tap_cnt_cpt_r_reg_n_0_[1]\,
      Q => \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][4][1]\,
      R => \rdlvl_dqs_tap_cnt_r_reg[0][0][2]_0\(0)
    );
\rdlvl_dqs_tap_cnt_r_reg[0][4][2]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => \rdlvl_dqs_tap_cnt_r[0][4][5]_i_1_n_0\,
      D => \tap_cnt_cpt_r_reg_n_0_[2]\,
      Q => \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][4][2]\,
      R => \rdlvl_dqs_tap_cnt_r_reg[0][0][2]_0\(0)
    );
\rdlvl_dqs_tap_cnt_r_reg[0][4][3]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => \rdlvl_dqs_tap_cnt_r[0][4][5]_i_1_n_0\,
      D => \tap_cnt_cpt_r_reg_n_0_[3]\,
      Q => \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][4][3]\,
      R => \rdlvl_dqs_tap_cnt_r_reg[0][0][2]_0\(0)
    );
\rdlvl_dqs_tap_cnt_r_reg[0][4][4]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => \rdlvl_dqs_tap_cnt_r[0][4][5]_i_1_n_0\,
      D => \tap_cnt_cpt_r_reg_n_0_[4]\,
      Q => \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][4][4]\,
      R => \rdlvl_dqs_tap_cnt_r_reg[0][0][2]_0\(0)
    );
\rdlvl_dqs_tap_cnt_r_reg[0][4][5]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => \rdlvl_dqs_tap_cnt_r[0][4][5]_i_1_n_0\,
      D => \tap_cnt_cpt_r_reg_n_0_[5]\,
      Q => \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][4][5]\,
      R => \rdlvl_dqs_tap_cnt_r_reg[0][0][2]_0\(0)
    );
\rdlvl_dqs_tap_cnt_r_reg[0][5][0]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => \rdlvl_dqs_tap_cnt_r[0][5][5]_i_1_n_0\,
      D => \tap_cnt_cpt_r_reg_n_0_[0]\,
      Q => \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][5][0]\,
      R => SR(1)
    );
\rdlvl_dqs_tap_cnt_r_reg[0][5][1]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => \rdlvl_dqs_tap_cnt_r[0][5][5]_i_1_n_0\,
      D => \tap_cnt_cpt_r_reg_n_0_[1]\,
      Q => \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][5][1]\,
      R => SR(1)
    );
\rdlvl_dqs_tap_cnt_r_reg[0][5][2]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => \rdlvl_dqs_tap_cnt_r[0][5][5]_i_1_n_0\,
      D => \tap_cnt_cpt_r_reg_n_0_[2]\,
      Q => \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][5][2]\,
      R => SR(1)
    );
\rdlvl_dqs_tap_cnt_r_reg[0][5][3]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => \rdlvl_dqs_tap_cnt_r[0][5][5]_i_1_n_0\,
      D => \tap_cnt_cpt_r_reg_n_0_[3]\,
      Q => \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][5][3]\,
      R => SR(1)
    );
\rdlvl_dqs_tap_cnt_r_reg[0][5][4]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => \rdlvl_dqs_tap_cnt_r[0][5][5]_i_1_n_0\,
      D => \tap_cnt_cpt_r_reg_n_0_[4]\,
      Q => \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][5][4]\,
      R => SR(1)
    );
\rdlvl_dqs_tap_cnt_r_reg[0][5][5]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => \rdlvl_dqs_tap_cnt_r[0][5][5]_i_1_n_0\,
      D => \tap_cnt_cpt_r_reg_n_0_[5]\,
      Q => \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][5][5]\,
      R => SR(1)
    );
\rdlvl_dqs_tap_cnt_r_reg[0][6][0]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => \rdlvl_dqs_tap_cnt_r[0][6][5]_i_1_n_0\,
      D => \tap_cnt_cpt_r_reg_n_0_[0]\,
      Q => \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][6][0]\,
      R => \rdlvl_dqs_tap_cnt_r_reg[0][0][2]_0\(0)
    );
\rdlvl_dqs_tap_cnt_r_reg[0][6][1]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => \rdlvl_dqs_tap_cnt_r[0][6][5]_i_1_n_0\,
      D => \tap_cnt_cpt_r_reg_n_0_[1]\,
      Q => \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][6][1]\,
      R => \rdlvl_dqs_tap_cnt_r_reg[0][0][2]_0\(0)
    );
\rdlvl_dqs_tap_cnt_r_reg[0][6][2]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => \rdlvl_dqs_tap_cnt_r[0][6][5]_i_1_n_0\,
      D => \tap_cnt_cpt_r_reg_n_0_[2]\,
      Q => \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][6][2]\,
      R => \rdlvl_dqs_tap_cnt_r_reg[0][0][2]_0\(0)
    );
\rdlvl_dqs_tap_cnt_r_reg[0][6][3]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => \rdlvl_dqs_tap_cnt_r[0][6][5]_i_1_n_0\,
      D => \tap_cnt_cpt_r_reg_n_0_[3]\,
      Q => \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][6][3]\,
      R => \rdlvl_dqs_tap_cnt_r_reg[0][0][2]_0\(0)
    );
\rdlvl_dqs_tap_cnt_r_reg[0][6][4]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => \rdlvl_dqs_tap_cnt_r[0][6][5]_i_1_n_0\,
      D => \tap_cnt_cpt_r_reg_n_0_[4]\,
      Q => \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][6][4]\,
      R => \rdlvl_dqs_tap_cnt_r_reg[0][0][2]_0\(0)
    );
\rdlvl_dqs_tap_cnt_r_reg[0][6][5]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => \rdlvl_dqs_tap_cnt_r[0][6][5]_i_1_n_0\,
      D => \tap_cnt_cpt_r_reg_n_0_[5]\,
      Q => \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][6][5]\,
      R => \rdlvl_dqs_tap_cnt_r_reg[0][0][2]_0\(0)
    );
\rdlvl_dqs_tap_cnt_r_reg[0][7][0]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => \rdlvl_dqs_tap_cnt_r[0][7][5]_i_1_n_0\,
      D => \tap_cnt_cpt_r_reg_n_0_[0]\,
      Q => \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][7][0]\,
      R => SR(0)
    );
\rdlvl_dqs_tap_cnt_r_reg[0][7][1]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => \rdlvl_dqs_tap_cnt_r[0][7][5]_i_1_n_0\,
      D => \tap_cnt_cpt_r_reg_n_0_[1]\,
      Q => \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][7][1]\,
      R => SR(1)
    );
\rdlvl_dqs_tap_cnt_r_reg[0][7][2]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => \rdlvl_dqs_tap_cnt_r[0][7][5]_i_1_n_0\,
      D => \tap_cnt_cpt_r_reg_n_0_[2]\,
      Q => \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][7][2]\,
      R => SR(1)
    );
\rdlvl_dqs_tap_cnt_r_reg[0][7][3]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => \rdlvl_dqs_tap_cnt_r[0][7][5]_i_1_n_0\,
      D => \tap_cnt_cpt_r_reg_n_0_[3]\,
      Q => \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][7][3]\,
      R => SR(1)
    );
\rdlvl_dqs_tap_cnt_r_reg[0][7][4]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => \rdlvl_dqs_tap_cnt_r[0][7][5]_i_1_n_0\,
      D => \tap_cnt_cpt_r_reg_n_0_[4]\,
      Q => \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][7][4]\,
      R => SR(1)
    );
\rdlvl_dqs_tap_cnt_r_reg[0][7][5]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => \rdlvl_dqs_tap_cnt_r[0][7][5]_i_1_n_0\,
      D => \tap_cnt_cpt_r_reg_n_0_[5]\,
      Q => \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][7][5]\,
      R => SR(1)
    );
rdlvl_last_byte_done_int_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAABAAAAAAA8"
    )
        port map (
      I0 => cal1_prech_req_r,
      I1 => \FSM_onehot_cal1_state_r[5]_i_1_n_0\,
      I2 => p_27_in,
      I3 => \FSM_onehot_cal1_state_r_reg_n_0_[7]\,
      I4 => \rnk_cnt_r[1]_i_2_n_0\,
      I5 => \^rdlvl_last_byte_done\,
      O => rdlvl_last_byte_done_int_i_1_n_0
    );
rdlvl_last_byte_done_int_reg: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => rdlvl_last_byte_done_int_i_1_n_0,
      Q => \^rdlvl_last_byte_done\,
      R => SR(1)
    );
rdlvl_pi_incdec_i_1: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FEFFFE00"
    )
        port map (
      I0 => mpr_dec_cpt_r,
      I1 => rdlvl_pi_incdec_i_2_n_0,
      I2 => rdlvl_pi_incdec_i_3_n_0,
      I3 => rdlvl_pi_incdec_i_4_n_0,
      I4 => \^rdlvl_pi_incdec\,
      O => rdlvl_pi_incdec_i_1_n_0
    );
rdlvl_pi_incdec_i_2: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFF0FFFEFFF0"
    )
        port map (
      I0 => p_8_in,
      I1 => \FSM_onehot_cal1_state_r_reg_n_0_[8]\,
      I2 => p_14_in,
      I3 => \FSM_onehot_cal1_state_r_reg_n_0_[29]\,
      I4 => cal1_wait_r,
      I5 => p_27_in,
      O => rdlvl_pi_incdec_i_2_n_0
    );
rdlvl_pi_incdec_i_3: unisim.vcomponents.LUT3
    generic map(
      INIT => X"8A"
    )
        port map (
      I0 => \FSM_onehot_cal1_state_r_reg_n_0_[7]\,
      I1 => mpr_rdlvl_start_r,
      I2 => mpr_rdlvl_start_r_reg_0,
      O => rdlvl_pi_incdec_i_3_n_0
    );
rdlvl_pi_incdec_i_4: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFFCD"
    )
        port map (
      I0 => cal1_wait_r,
      I1 => \FSM_onehot_cal1_state_r_reg_n_0_[29]\,
      I2 => rdlvl_pi_incdec_i_5_n_0,
      I3 => p_14_in,
      I4 => \cal1_state_r1[0]_i_2_n_0\,
      I5 => rdlvl_rank_done_r_i_3_n_0,
      O => rdlvl_pi_incdec_i_4_n_0
    );
rdlvl_pi_incdec_i_5: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => p_8_in,
      I1 => \FSM_onehot_cal1_state_r_reg_n_0_[8]\,
      O => rdlvl_pi_incdec_i_5_n_0
    );
rdlvl_pi_incdec_reg: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => rdlvl_pi_incdec_i_1_n_0,
      Q => \^rdlvl_pi_incdec\,
      R => \rdlvl_dqs_tap_cnt_r_reg[0][0][2]_0\(0)
    );
rdlvl_prech_req_reg: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \cal1_prech_req_r__0\,
      Q => \^rdlvl_prech_req\,
      R => \rdlvl_dqs_tap_cnt_r_reg[0][0][2]_0\(1)
    );
rdlvl_rank_done_r_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"A0A0A0FFA0A0A080"
    )
        port map (
      I0 => cal1_prech_req_r,
      I1 => prech_done,
      I2 => rdlvl_rank_done_r_i_2_n_0,
      I3 => rdlvl_rank_done_r_i_3_n_0,
      I4 => p_0_in541_in,
      I5 => \^rdlvl_stg1_rank_done\,
      O => rdlvl_rank_done_r_i_1_n_0
    );
rdlvl_rank_done_r_i_2: unisim.vcomponents.LUT3
    generic map(
      INIT => X"80"
    )
        port map (
      I0 => \cal1_cnt_cpt_r_reg_n_0_[1]\,
      I1 => \cal1_cnt_cpt_r_reg_n_0_[0]\,
      I2 => \cal1_cnt_cpt_r_reg_n_0_[2]\,
      O => rdlvl_rank_done_r_i_2_n_0
    );
rdlvl_rank_done_r_i_3: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => p_27_in,
      I1 => \FSM_onehot_cal1_state_r_reg_n_0_[7]\,
      O => rdlvl_rank_done_r_i_3_n_0
    );
rdlvl_rank_done_r_reg: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => rdlvl_rank_done_r_i_1_n_0,
      Q => \^rdlvl_stg1_rank_done\,
      R => \rdlvl_dqs_tap_cnt_r_reg[0][0][2]_0\(1)
    );
rdlvl_stg1_done_int_i_1: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => rdlvl_stg1_done_int,
      I1 => \^rdlvl_stg1_done_int_reg_0\,
      O => rdlvl_stg1_done_int_i_1_n_0
    );
rdlvl_stg1_done_int_reg: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => rdlvl_stg1_done_int_i_1_n_0,
      Q => \^rdlvl_stg1_done_int_reg_0\,
      R => \rdlvl_dqs_tap_cnt_r_reg[0][0][2]_0\(1)
    );
rdlvl_stg1_start_r_reg: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => rdlvl_stg1_start_r_reg_0,
      Q => rdlvl_stg1_start_r,
      R => '0'
    );
\regl_dqs_cnt[0]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"00E6"
    )
        port map (
      I0 => regl_dqs_cnt(0),
      I1 => \pi_stg2_reg_l_timing[5]_i_3_n_0\,
      I2 => \FSM_onehot_cal1_state_r[5]_i_1_n_0\,
      I3 => \regl_rank_cnt[1]_i_3_n_0\,
      O => \regl_dqs_cnt[0]_i_1_n_0\
    );
\regl_dqs_cnt[1]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000EE6A"
    )
        port map (
      I0 => regl_dqs_cnt(1),
      I1 => \pi_stg2_reg_l_timing[5]_i_3_n_0\,
      I2 => regl_dqs_cnt(0),
      I3 => \FSM_onehot_cal1_state_r[5]_i_1_n_0\,
      I4 => \regl_rank_cnt[1]_i_3_n_0\,
      O => \regl_dqs_cnt[1]_i_1_n_0\
    );
\regl_dqs_cnt[2]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000EEEE6AAA"
    )
        port map (
      I0 => regl_dqs_cnt(2),
      I1 => \pi_stg2_reg_l_timing[5]_i_3_n_0\,
      I2 => regl_dqs_cnt(0),
      I3 => regl_dqs_cnt(1),
      I4 => \FSM_onehot_cal1_state_r[5]_i_1_n_0\,
      I5 => \regl_rank_cnt[1]_i_3_n_0\,
      O => \regl_dqs_cnt[2]_i_1_n_0\
    );
\regl_dqs_cnt[3]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0444444444444444"
    )
        port map (
      I0 => \regl_rank_cnt[1]_i_3_n_0\,
      I1 => regl_dqs_cnt(3),
      I2 => regl_dqs_cnt(1),
      I3 => regl_dqs_cnt(0),
      I4 => regl_dqs_cnt(2),
      I5 => \pi_stg2_reg_l_timing[5]_i_3_n_0\,
      O => \regl_dqs_cnt[3]_i_1_n_0\
    );
\regl_dqs_cnt_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => regl_dqs_cnt(0),
      Q => regl_dqs_cnt_r(0),
      R => '0'
    );
\regl_dqs_cnt_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => regl_dqs_cnt(1),
      Q => regl_dqs_cnt_r(1),
      R => '0'
    );
\regl_dqs_cnt_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => regl_dqs_cnt(2),
      Q => regl_dqs_cnt_r(2),
      R => '0'
    );
\regl_dqs_cnt_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => regl_dqs_cnt(3),
      Q => regl_dqs_cnt_r(3),
      R => '0'
    );
\regl_dqs_cnt_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \regl_dqs_cnt[0]_i_1_n_0\,
      Q => regl_dqs_cnt(0),
      R => '0'
    );
\regl_dqs_cnt_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \regl_dqs_cnt[1]_i_1_n_0\,
      Q => regl_dqs_cnt(1),
      R => '0'
    );
\regl_dqs_cnt_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \regl_dqs_cnt[2]_i_1_n_0\,
      Q => regl_dqs_cnt(2),
      R => '0'
    );
\regl_dqs_cnt_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \regl_dqs_cnt[3]_i_1_n_0\,
      Q => regl_dqs_cnt(3),
      R => '0'
    );
\regl_rank_cnt[0]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0062"
    )
        port map (
      I0 => regl_rank_cnt(0),
      I1 => regl_rank_cnt0,
      I2 => regl_rank_cnt(1),
      I3 => \regl_rank_cnt[1]_i_3_n_0\,
      O => \regl_rank_cnt[0]_i_1_n_0\
    );
\regl_rank_cnt[1]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"006A"
    )
        port map (
      I0 => regl_rank_cnt(1),
      I1 => regl_rank_cnt0,
      I2 => regl_rank_cnt(0),
      I3 => \regl_rank_cnt[1]_i_3_n_0\,
      O => \regl_rank_cnt[1]_i_1_n_0\
    );
\regl_rank_cnt[1]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00008000"
    )
        port map (
      I0 => \pi_stg2_reg_l_timing[5]_i_3_n_0\,
      I1 => regl_dqs_cnt(2),
      I2 => regl_dqs_cnt(0),
      I3 => regl_dqs_cnt(1),
      I4 => regl_dqs_cnt(3),
      O => regl_rank_cnt0
    );
\regl_rank_cnt[1]_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AAAAAAAB"
    )
        port map (
      I0 => \done_cnt_reg[2]_0\,
      I1 => done_cnt(3),
      I2 => done_cnt(1),
      I3 => done_cnt(0),
      I4 => done_cnt(2),
      O => \regl_rank_cnt[1]_i_3_n_0\
    );
\regl_rank_cnt_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \regl_rank_cnt[0]_i_1_n_0\,
      Q => regl_rank_cnt(0),
      R => '0'
    );
\regl_rank_cnt_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \regl_rank_cnt[1]_i_1_n_0\,
      Q => regl_rank_cnt(1),
      R => '0'
    );
\right_edge_taps_r[0]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \tap_cnt_cpt_r_reg_n_0_[0]\,
      I1 => store_sr_req_pulsed_r,
      O => right_edge_taps_r(0)
    );
\right_edge_taps_r[1]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \tap_cnt_cpt_r_reg_n_0_[1]\,
      I1 => store_sr_req_pulsed_r,
      O => right_edge_taps_r(1)
    );
\right_edge_taps_r[2]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \tap_cnt_cpt_r_reg_n_0_[2]\,
      I1 => store_sr_req_pulsed_r,
      O => right_edge_taps_r(2)
    );
\right_edge_taps_r[3]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \tap_cnt_cpt_r_reg_n_0_[3]\,
      I1 => store_sr_req_pulsed_r,
      O => right_edge_taps_r(3)
    );
\right_edge_taps_r[4]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \tap_cnt_cpt_r_reg_n_0_[4]\,
      I1 => store_sr_req_pulsed_r,
      O => right_edge_taps_r(4)
    );
\right_edge_taps_r[5]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"BAAA"
    )
        port map (
      I0 => cal1_prech_req_r,
      I1 => found_first_edge_r_reg_n_0,
      I2 => found_stable_eye_last_r,
      I3 => \first_edge_taps_r[5]_i_3_n_0\,
      O => \right_edge_taps_r[5]_i_1_n_0\
    );
\right_edge_taps_r[5]_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \tap_cnt_cpt_r_reg_n_0_[5]\,
      I1 => store_sr_req_pulsed_r,
      O => right_edge_taps_r(5)
    );
\right_edge_taps_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => \right_edge_taps_r[5]_i_1_n_0\,
      D => right_edge_taps_r(0),
      Q => \right_edge_taps_r_reg_n_0_[0]\,
      R => \rdlvl_dqs_tap_cnt_r_reg[0][0][2]_0\(1)
    );
\right_edge_taps_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => \right_edge_taps_r[5]_i_1_n_0\,
      D => right_edge_taps_r(1),
      Q => \right_edge_taps_r_reg_n_0_[1]\,
      R => \rdlvl_dqs_tap_cnt_r_reg[0][0][2]_0\(1)
    );
\right_edge_taps_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => \right_edge_taps_r[5]_i_1_n_0\,
      D => right_edge_taps_r(2),
      Q => \right_edge_taps_r_reg_n_0_[2]\,
      R => \rdlvl_dqs_tap_cnt_r_reg[0][0][2]_0\(1)
    );
\right_edge_taps_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => \right_edge_taps_r[5]_i_1_n_0\,
      D => right_edge_taps_r(3),
      Q => \right_edge_taps_r_reg_n_0_[3]\,
      R => \rdlvl_dqs_tap_cnt_r_reg[0][0][2]_0\(1)
    );
\right_edge_taps_r_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => \right_edge_taps_r[5]_i_1_n_0\,
      D => right_edge_taps_r(4),
      Q => \right_edge_taps_r_reg_n_0_[4]\,
      R => \rdlvl_dqs_tap_cnt_r_reg[0][0][2]_0\(1)
    );
\right_edge_taps_r_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => \right_edge_taps_r[5]_i_1_n_0\,
      D => right_edge_taps_r(5),
      Q => \right_edge_taps_r_reg_n_0_[5]\,
      R => \rdlvl_dqs_tap_cnt_r_reg[0][0][2]_0\(1)
    );
\rnk_cnt_r[0]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"03A8038833883388"
    )
        port map (
      I0 => cal1_prech_req_r,
      I1 => p_0_in541_in,
      I2 => \rnk_cnt_r[1]_i_2_n_0\,
      I3 => \rnk_cnt_r_reg_n_0_[0]\,
      I4 => \rnk_cnt_r_reg_n_0_[1]\,
      I5 => prech_done,
      O => \rnk_cnt_r[0]_i_1__0_n_0\
    );
\rnk_cnt_r[1]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"03ABA80033BB8800"
    )
        port map (
      I0 => cal1_prech_req_r,
      I1 => p_0_in541_in,
      I2 => \rnk_cnt_r[1]_i_2_n_0\,
      I3 => \rnk_cnt_r_reg_n_0_[0]\,
      I4 => \rnk_cnt_r_reg_n_0_[1]\,
      I5 => prech_done,
      O => \rnk_cnt_r[1]_i_1__0_n_0\
    );
\rnk_cnt_r[1]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8000"
    )
        port map (
      I0 => \cal1_cnt_cpt_r_reg_n_0_[2]\,
      I1 => \cal1_cnt_cpt_r_reg_n_0_[0]\,
      I2 => \cal1_cnt_cpt_r_reg_n_0_[1]\,
      I3 => cal1_prech_req_r,
      O => \rnk_cnt_r[1]_i_2_n_0\
    );
\rnk_cnt_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \rnk_cnt_r[0]_i_1__0_n_0\,
      Q => \rnk_cnt_r_reg_n_0_[0]\,
      R => \rdlvl_dqs_tap_cnt_r_reg[0][0][2]_0\(1)
    );
\rnk_cnt_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => \rnk_cnt_r[1]_i_1__0_n_0\,
      Q => \rnk_cnt_r_reg_n_0_[1]\,
      R => \rdlvl_dqs_tap_cnt_r_reg[0][0][2]_0\(1)
    );
samp_cnt_done_r_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000AAAE0000"
    )
        port map (
      I0 => samp_cnt_done_r_reg_n_0,
      I1 => samp_cnt_done_r_i_2_n_0,
      I2 => samp_cnt_done_r_i_3_n_0,
      I3 => samp_cnt_done_r_i_4_n_0,
      I4 => \^samp_edge_cnt0_en_r\,
      I5 => \done_cnt_reg[2]_0\,
      O => samp_cnt_done_r_i_1_n_0
    );
samp_cnt_done_r_i_2: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0010"
    )
        port map (
      I0 => samp_edge_cnt1_r_reg(11),
      I1 => samp_edge_cnt1_r_reg(7),
      I2 => samp_edge_cnt1_r_reg(0),
      I3 => samp_edge_cnt1_r_reg(6),
      O => samp_cnt_done_r_i_2_n_0
    );
samp_cnt_done_r_i_3: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFFE"
    )
        port map (
      I0 => samp_edge_cnt1_r_reg(1),
      I1 => samp_edge_cnt1_r_reg(10),
      I2 => samp_edge_cnt1_r_reg(8),
      I3 => samp_edge_cnt1_r_reg(3),
      O => samp_cnt_done_r_i_3_n_0
    );
samp_cnt_done_r_i_4: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFFE"
    )
        port map (
      I0 => samp_edge_cnt1_r_reg(4),
      I1 => samp_edge_cnt1_r_reg(9),
      I2 => samp_edge_cnt1_r_reg(2),
      I3 => samp_edge_cnt1_r_reg(5),
      O => samp_cnt_done_r_i_4_n_0
    );
samp_cnt_done_r_reg: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => samp_cnt_done_r_i_1_n_0,
      Q => samp_cnt_done_r_reg_n_0,
      R => '0'
    );
samp_edge_cnt0_en_r_i_1: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => store_sr_req_pulsed_r,
      I1 => p_34_in,
      O => pb_detect_edge
    );
samp_edge_cnt0_en_r_reg: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => pb_detect_edge,
      Q => \^samp_edge_cnt0_en_r\,
      R => '0'
    );
\samp_edge_cnt0_r[0]_i_3\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => samp_edge_cnt0_r_reg(0),
      O => \samp_edge_cnt0_r[0]_i_3_n_0\
    );
\samp_edge_cnt0_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => sr_valid_r2,
      D => \samp_edge_cnt0_r_reg[0]_i_2_n_7\,
      Q => samp_edge_cnt0_r_reg(0),
      R => \samp_edge_cnt1_r_reg[0]_0\
    );
\samp_edge_cnt0_r_reg[0]_i_2\: unisim.vcomponents.CARRY4
     port map (
      CI => '0',
      CO(3) => \samp_edge_cnt0_r_reg[0]_i_2_n_0\,
      CO(2) => \samp_edge_cnt0_r_reg[0]_i_2_n_1\,
      CO(1) => \samp_edge_cnt0_r_reg[0]_i_2_n_2\,
      CO(0) => \samp_edge_cnt0_r_reg[0]_i_2_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0001",
      O(3) => \samp_edge_cnt0_r_reg[0]_i_2_n_4\,
      O(2) => \samp_edge_cnt0_r_reg[0]_i_2_n_5\,
      O(1) => \samp_edge_cnt0_r_reg[0]_i_2_n_6\,
      O(0) => \samp_edge_cnt0_r_reg[0]_i_2_n_7\,
      S(3 downto 1) => samp_edge_cnt0_r_reg(3 downto 1),
      S(0) => \samp_edge_cnt0_r[0]_i_3_n_0\
    );
\samp_edge_cnt0_r_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => sr_valid_r2,
      D => \samp_edge_cnt0_r_reg[8]_i_1_n_5\,
      Q => samp_edge_cnt0_r_reg(10),
      R => \samp_edge_cnt1_r_reg[0]_0\
    );
\samp_edge_cnt0_r_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => sr_valid_r2,
      D => \samp_edge_cnt0_r_reg[8]_i_1_n_4\,
      Q => samp_edge_cnt0_r_reg(11),
      R => \samp_edge_cnt1_r_reg[0]_0\
    );
\samp_edge_cnt0_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => sr_valid_r2,
      D => \samp_edge_cnt0_r_reg[0]_i_2_n_6\,
      Q => samp_edge_cnt0_r_reg(1),
      R => \samp_edge_cnt1_r_reg[0]_0\
    );
\samp_edge_cnt0_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => sr_valid_r2,
      D => \samp_edge_cnt0_r_reg[0]_i_2_n_5\,
      Q => samp_edge_cnt0_r_reg(2),
      R => \samp_edge_cnt1_r_reg[0]_0\
    );
\samp_edge_cnt0_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => sr_valid_r2,
      D => \samp_edge_cnt0_r_reg[0]_i_2_n_4\,
      Q => samp_edge_cnt0_r_reg(3),
      R => \samp_edge_cnt1_r_reg[0]_0\
    );
\samp_edge_cnt0_r_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => sr_valid_r2,
      D => \samp_edge_cnt0_r_reg[4]_i_1_n_7\,
      Q => samp_edge_cnt0_r_reg(4),
      R => \samp_edge_cnt1_r_reg[0]_0\
    );
\samp_edge_cnt0_r_reg[4]_i_1\: unisim.vcomponents.CARRY4
     port map (
      CI => \samp_edge_cnt0_r_reg[0]_i_2_n_0\,
      CO(3) => \samp_edge_cnt0_r_reg[4]_i_1_n_0\,
      CO(2) => \samp_edge_cnt0_r_reg[4]_i_1_n_1\,
      CO(1) => \samp_edge_cnt0_r_reg[4]_i_1_n_2\,
      CO(0) => \samp_edge_cnt0_r_reg[4]_i_1_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3) => \samp_edge_cnt0_r_reg[4]_i_1_n_4\,
      O(2) => \samp_edge_cnt0_r_reg[4]_i_1_n_5\,
      O(1) => \samp_edge_cnt0_r_reg[4]_i_1_n_6\,
      O(0) => \samp_edge_cnt0_r_reg[4]_i_1_n_7\,
      S(3 downto 0) => samp_edge_cnt0_r_reg(7 downto 4)
    );
\samp_edge_cnt0_r_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => sr_valid_r2,
      D => \samp_edge_cnt0_r_reg[4]_i_1_n_6\,
      Q => samp_edge_cnt0_r_reg(5),
      R => \samp_edge_cnt1_r_reg[0]_0\
    );
\samp_edge_cnt0_r_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => sr_valid_r2,
      D => \samp_edge_cnt0_r_reg[4]_i_1_n_5\,
      Q => samp_edge_cnt0_r_reg(6),
      R => \samp_edge_cnt1_r_reg[0]_0\
    );
\samp_edge_cnt0_r_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => sr_valid_r2,
      D => \samp_edge_cnt0_r_reg[4]_i_1_n_4\,
      Q => samp_edge_cnt0_r_reg(7),
      R => \samp_edge_cnt1_r_reg[0]_0\
    );
\samp_edge_cnt0_r_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => sr_valid_r2,
      D => \samp_edge_cnt0_r_reg[8]_i_1_n_7\,
      Q => samp_edge_cnt0_r_reg(8),
      R => \samp_edge_cnt1_r_reg[0]_0\
    );
\samp_edge_cnt0_r_reg[8]_i_1\: unisim.vcomponents.CARRY4
     port map (
      CI => \samp_edge_cnt0_r_reg[4]_i_1_n_0\,
      CO(3) => \NLW_samp_edge_cnt0_r_reg[8]_i_1_CO_UNCONNECTED\(3),
      CO(2) => \samp_edge_cnt0_r_reg[8]_i_1_n_1\,
      CO(1) => \samp_edge_cnt0_r_reg[8]_i_1_n_2\,
      CO(0) => \samp_edge_cnt0_r_reg[8]_i_1_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3) => \samp_edge_cnt0_r_reg[8]_i_1_n_4\,
      O(2) => \samp_edge_cnt0_r_reg[8]_i_1_n_5\,
      O(1) => \samp_edge_cnt0_r_reg[8]_i_1_n_6\,
      O(0) => \samp_edge_cnt0_r_reg[8]_i_1_n_7\,
      S(3 downto 0) => samp_edge_cnt0_r_reg(11 downto 8)
    );
\samp_edge_cnt0_r_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => sr_valid_r2,
      D => \samp_edge_cnt0_r_reg[8]_i_1_n_6\,
      Q => samp_edge_cnt0_r_reg(9),
      R => \samp_edge_cnt1_r_reg[0]_0\
    );
samp_edge_cnt1_en_r_i_1: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000200"
    )
        port map (
      I0 => samp_edge_cnt1_en_r_i_2_n_0,
      I1 => samp_edge_cnt1_en_r_i_3_n_0,
      I2 => samp_edge_cnt0_r_reg(2),
      I3 => samp_edge_cnt0_r_reg(0),
      I4 => samp_edge_cnt0_r_reg(5),
      O => samp_edge_cnt1_en_r0
    );
samp_edge_cnt1_en_r_i_2: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000000001"
    )
        port map (
      I0 => samp_edge_cnt0_r_reg(10),
      I1 => samp_edge_cnt0_r_reg(4),
      I2 => samp_edge_cnt0_r_reg(9),
      I3 => samp_edge_cnt0_r_reg(7),
      I4 => samp_edge_cnt0_r_reg(11),
      I5 => samp_edge_cnt0_r_reg(6),
      O => samp_edge_cnt1_en_r_i_2_n_0
    );
samp_edge_cnt1_en_r_i_3: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFEF"
    )
        port map (
      I0 => samp_edge_cnt0_r_reg(8),
      I1 => samp_edge_cnt0_r_reg(3),
      I2 => sr_valid_r2,
      I3 => samp_edge_cnt0_r_reg(1),
      O => samp_edge_cnt1_en_r_i_3_n_0
    );
samp_edge_cnt1_en_r_reg: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => samp_edge_cnt1_en_r0,
      Q => samp_edge_cnt1_en_r,
      R => \rdlvl_dqs_tap_cnt_r_reg[0][0][2]_0\(1)
    );
\samp_edge_cnt1_r[0]_i_2\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => samp_edge_cnt1_r_reg(0),
      O => \samp_edge_cnt1_r[0]_i_2_n_0\
    );
\samp_edge_cnt1_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => samp_edge_cnt1_en_r,
      D => \samp_edge_cnt1_r_reg[0]_i_1_n_7\,
      Q => samp_edge_cnt1_r_reg(0),
      R => \samp_edge_cnt1_r_reg[0]_0\
    );
\samp_edge_cnt1_r_reg[0]_i_1\: unisim.vcomponents.CARRY4
     port map (
      CI => '0',
      CO(3) => \samp_edge_cnt1_r_reg[0]_i_1_n_0\,
      CO(2) => \samp_edge_cnt1_r_reg[0]_i_1_n_1\,
      CO(1) => \samp_edge_cnt1_r_reg[0]_i_1_n_2\,
      CO(0) => \samp_edge_cnt1_r_reg[0]_i_1_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0001",
      O(3) => \samp_edge_cnt1_r_reg[0]_i_1_n_4\,
      O(2) => \samp_edge_cnt1_r_reg[0]_i_1_n_5\,
      O(1) => \samp_edge_cnt1_r_reg[0]_i_1_n_6\,
      O(0) => \samp_edge_cnt1_r_reg[0]_i_1_n_7\,
      S(3 downto 1) => samp_edge_cnt1_r_reg(3 downto 1),
      S(0) => \samp_edge_cnt1_r[0]_i_2_n_0\
    );
\samp_edge_cnt1_r_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => samp_edge_cnt1_en_r,
      D => \samp_edge_cnt1_r_reg[8]_i_1_n_5\,
      Q => samp_edge_cnt1_r_reg(10),
      R => \samp_edge_cnt1_r_reg[0]_0\
    );
\samp_edge_cnt1_r_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => samp_edge_cnt1_en_r,
      D => \samp_edge_cnt1_r_reg[8]_i_1_n_4\,
      Q => samp_edge_cnt1_r_reg(11),
      R => \samp_edge_cnt1_r_reg[0]_0\
    );
\samp_edge_cnt1_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => samp_edge_cnt1_en_r,
      D => \samp_edge_cnt1_r_reg[0]_i_1_n_6\,
      Q => samp_edge_cnt1_r_reg(1),
      R => \samp_edge_cnt1_r_reg[0]_0\
    );
\samp_edge_cnt1_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => samp_edge_cnt1_en_r,
      D => \samp_edge_cnt1_r_reg[0]_i_1_n_5\,
      Q => samp_edge_cnt1_r_reg(2),
      R => \samp_edge_cnt1_r_reg[0]_0\
    );
\samp_edge_cnt1_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => samp_edge_cnt1_en_r,
      D => \samp_edge_cnt1_r_reg[0]_i_1_n_4\,
      Q => samp_edge_cnt1_r_reg(3),
      R => \samp_edge_cnt1_r_reg[0]_0\
    );
\samp_edge_cnt1_r_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => samp_edge_cnt1_en_r,
      D => \samp_edge_cnt1_r_reg[4]_i_1_n_7\,
      Q => samp_edge_cnt1_r_reg(4),
      R => \samp_edge_cnt1_r_reg[0]_0\
    );
\samp_edge_cnt1_r_reg[4]_i_1\: unisim.vcomponents.CARRY4
     port map (
      CI => \samp_edge_cnt1_r_reg[0]_i_1_n_0\,
      CO(3) => \samp_edge_cnt1_r_reg[4]_i_1_n_0\,
      CO(2) => \samp_edge_cnt1_r_reg[4]_i_1_n_1\,
      CO(1) => \samp_edge_cnt1_r_reg[4]_i_1_n_2\,
      CO(0) => \samp_edge_cnt1_r_reg[4]_i_1_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3) => \samp_edge_cnt1_r_reg[4]_i_1_n_4\,
      O(2) => \samp_edge_cnt1_r_reg[4]_i_1_n_5\,
      O(1) => \samp_edge_cnt1_r_reg[4]_i_1_n_6\,
      O(0) => \samp_edge_cnt1_r_reg[4]_i_1_n_7\,
      S(3 downto 0) => samp_edge_cnt1_r_reg(7 downto 4)
    );
\samp_edge_cnt1_r_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => samp_edge_cnt1_en_r,
      D => \samp_edge_cnt1_r_reg[4]_i_1_n_6\,
      Q => samp_edge_cnt1_r_reg(5),
      R => \samp_edge_cnt1_r_reg[0]_0\
    );
\samp_edge_cnt1_r_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => samp_edge_cnt1_en_r,
      D => \samp_edge_cnt1_r_reg[4]_i_1_n_5\,
      Q => samp_edge_cnt1_r_reg(6),
      R => \samp_edge_cnt1_r_reg[0]_0\
    );
\samp_edge_cnt1_r_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => samp_edge_cnt1_en_r,
      D => \samp_edge_cnt1_r_reg[4]_i_1_n_4\,
      Q => samp_edge_cnt1_r_reg(7),
      R => \samp_edge_cnt1_r_reg[0]_0\
    );
\samp_edge_cnt1_r_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => samp_edge_cnt1_en_r,
      D => \samp_edge_cnt1_r_reg[8]_i_1_n_7\,
      Q => samp_edge_cnt1_r_reg(8),
      R => \samp_edge_cnt1_r_reg[0]_0\
    );
\samp_edge_cnt1_r_reg[8]_i_1\: unisim.vcomponents.CARRY4
     port map (
      CI => \samp_edge_cnt1_r_reg[4]_i_1_n_0\,
      CO(3) => \NLW_samp_edge_cnt1_r_reg[8]_i_1_CO_UNCONNECTED\(3),
      CO(2) => \samp_edge_cnt1_r_reg[8]_i_1_n_1\,
      CO(1) => \samp_edge_cnt1_r_reg[8]_i_1_n_2\,
      CO(0) => \samp_edge_cnt1_r_reg[8]_i_1_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3) => \samp_edge_cnt1_r_reg[8]_i_1_n_4\,
      O(2) => \samp_edge_cnt1_r_reg[8]_i_1_n_5\,
      O(1) => \samp_edge_cnt1_r_reg[8]_i_1_n_6\,
      O(0) => \samp_edge_cnt1_r_reg[8]_i_1_n_7\,
      S(3 downto 0) => samp_edge_cnt1_r_reg(11 downto 8)
    );
\samp_edge_cnt1_r_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => samp_edge_cnt1_en_r,
      D => \samp_edge_cnt1_r_reg[8]_i_1_n_6\,
      Q => samp_edge_cnt1_r_reg(9),
      R => \samp_edge_cnt1_r_reg[0]_0\
    );
\second_edge_taps_r[0]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \tap_cnt_cpt_r_reg_n_0_[0]\,
      O => tap_cnt_cpt_r0(0)
    );
\second_edge_taps_r[1]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => \tap_cnt_cpt_r_reg_n_0_[0]\,
      I1 => \tap_cnt_cpt_r_reg_n_0_[1]\,
      O => \second_edge_taps_r[1]_i_1_n_0\
    );
\second_edge_taps_r[2]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"E1"
    )
        port map (
      I0 => \tap_cnt_cpt_r_reg_n_0_[1]\,
      I1 => \tap_cnt_cpt_r_reg_n_0_[0]\,
      I2 => \tap_cnt_cpt_r_reg_n_0_[2]\,
      O => \second_edge_taps_r[2]_i_1_n_0\
    );
\second_edge_taps_r[3]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FE01"
    )
        port map (
      I0 => \tap_cnt_cpt_r_reg_n_0_[0]\,
      I1 => \tap_cnt_cpt_r_reg_n_0_[1]\,
      I2 => \tap_cnt_cpt_r_reg_n_0_[2]\,
      I3 => \tap_cnt_cpt_r_reg_n_0_[3]\,
      O => \second_edge_taps_r[3]_i_1_n_0\
    );
\second_edge_taps_r[4]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFE0001"
    )
        port map (
      I0 => \tap_cnt_cpt_r_reg_n_0_[2]\,
      I1 => \tap_cnt_cpt_r_reg_n_0_[1]\,
      I2 => \tap_cnt_cpt_r_reg_n_0_[0]\,
      I3 => \tap_cnt_cpt_r_reg_n_0_[3]\,
      I4 => \tap_cnt_cpt_r_reg_n_0_[4]\,
      O => \second_edge_taps_r[4]_i_1_n_0\
    );
\second_edge_taps_r[5]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000EAAA"
    )
        port map (
      I0 => cal1_prech_req_r,
      I1 => \first_edge_taps_r[5]_i_3_n_0\,
      I2 => found_first_edge_r_reg_n_0,
      I3 => found_stable_eye_last_r,
      I4 => store_sr_req_pulsed_r,
      O => \second_edge_taps_r[5]_i_1_n_0\
    );
\second_edge_taps_r[5]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"EAAA"
    )
        port map (
      I0 => cal1_prech_req_r,
      I1 => \first_edge_taps_r[5]_i_3_n_0\,
      I2 => found_first_edge_r_reg_n_0,
      I3 => found_stable_eye_last_r,
      O => \second_edge_taps_r[5]_i_2_n_0\
    );
\second_edge_taps_r[5]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFE00000001"
    )
        port map (
      I0 => \tap_cnt_cpt_r_reg_n_0_[3]\,
      I1 => \tap_cnt_cpt_r_reg_n_0_[0]\,
      I2 => \tap_cnt_cpt_r_reg_n_0_[1]\,
      I3 => \tap_cnt_cpt_r_reg_n_0_[2]\,
      I4 => \tap_cnt_cpt_r_reg_n_0_[4]\,
      I5 => \tap_cnt_cpt_r_reg_n_0_[5]\,
      O => \second_edge_taps_r[5]_i_3_n_0\
    );
\second_edge_taps_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => \second_edge_taps_r[5]_i_2_n_0\,
      D => tap_cnt_cpt_r0(0),
      Q => \second_edge_taps_r_reg_n_0_[0]\,
      R => \second_edge_taps_r[5]_i_1_n_0\
    );
\second_edge_taps_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => \second_edge_taps_r[5]_i_2_n_0\,
      D => \second_edge_taps_r[1]_i_1_n_0\,
      Q => \second_edge_taps_r_reg_n_0_[1]\,
      R => \second_edge_taps_r[5]_i_1_n_0\
    );
\second_edge_taps_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => \second_edge_taps_r[5]_i_2_n_0\,
      D => \second_edge_taps_r[2]_i_1_n_0\,
      Q => \second_edge_taps_r_reg_n_0_[2]\,
      R => \second_edge_taps_r[5]_i_1_n_0\
    );
\second_edge_taps_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => \second_edge_taps_r[5]_i_2_n_0\,
      D => \second_edge_taps_r[3]_i_1_n_0\,
      Q => \second_edge_taps_r_reg_n_0_[3]\,
      R => \second_edge_taps_r[5]_i_1_n_0\
    );
\second_edge_taps_r_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => \second_edge_taps_r[5]_i_2_n_0\,
      D => \second_edge_taps_r[4]_i_1_n_0\,
      Q => \second_edge_taps_r_reg_n_0_[4]\,
      R => \second_edge_taps_r[5]_i_1_n_0\
    );
\second_edge_taps_r_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => \second_edge_taps_r[5]_i_2_n_0\,
      D => \second_edge_taps_r[5]_i_3_n_0\,
      Q => \second_edge_taps_r_reg_n_0_[5]\,
      R => \second_edge_taps_r[5]_i_1_n_0\
    );
sr_valid_r1_reg: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => sr_valid_r_reg_n_0,
      Q => sr_valid_r1,
      R => '0'
    );
sr_valid_r2_reg: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => sr_valid_r1,
      Q => sr_valid_r2,
      R => '0'
    );
sr_valid_r_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000000008"
    )
        port map (
      I0 => rdlvl_stg1_start_r_reg_0,
      I1 => E(0),
      I2 => cnt_shift_r_reg(3),
      I3 => cnt_shift_r_reg(2),
      I4 => cnt_shift_r_reg(0),
      I5 => cnt_shift_r_reg(1),
      O => sr_valid_r_i_1_n_0
    );
sr_valid_r_reg: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => sr_valid_r_i_1_n_0,
      Q => sr_valid_r_reg_n_0,
      R => sr_valid_r_reg_0
    );
\stg1_wr_rd_cnt[4]_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"45"
    )
        port map (
      I0 => \stg1_wr_rd_cnt_reg[3]\,
      I1 => \^rdlvl_stg1_done_int_reg_0\,
      I2 => stg1_wr_done,
      O => rdlvl_stg1_done_int_reg_1
    );
store_sr_r_i_1: unisim.vcomponents.LUT3
    generic map(
      INIT => X"BA"
    )
        port map (
      I0 => store_sr_req_r_reg_n_0,
      I1 => sr_valid_r_reg_n_0,
      I2 => store_sr_r_reg_n_0,
      O => store_sr_r_i_1_n_0
    );
store_sr_r_reg: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => store_sr_r_i_1_n_0,
      Q => store_sr_r_reg_n_0,
      R => \rdlvl_dqs_tap_cnt_r_reg[0][0][2]_0\(1)
    );
store_sr_req_pulsed_r_reg: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => store_sr_req_pulsed_r,
      Q => \store_sr_req_pulsed_r__0\,
      R => \rdlvl_dqs_tap_cnt_r_reg[0][0][2]_0\(1)
    );
store_sr_req_r_i_1: unisim.vcomponents.LUT5
    generic map(
      INIT => X"44444F44"
    )
        port map (
      I0 => \store_sr_req_pulsed_r__0\,
      I1 => store_sr_req_pulsed_r,
      I2 => cal1_wait_r,
      I3 => p_27_in,
      I4 => store_sr_req_r_i_2_n_0,
      O => store_sr_req_r
    );
store_sr_req_r_i_2: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFFFE"
    )
        port map (
      I0 => D(5),
      I1 => D(1),
      I2 => D(2),
      I3 => D(3),
      I4 => D(0),
      I5 => D(4),
      O => store_sr_req_r_i_2_n_0
    );
store_sr_req_r_reg: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => store_sr_req_r,
      Q => store_sr_req_r_reg_n_0,
      R => \rdlvl_dqs_tap_cnt_r_reg[0][0][2]_0\(1)
    );
\tap_cnt_cpt_r[1]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"69"
    )
        port map (
      I0 => cal1_dlyinc_cpt_r_reg_n_0,
      I1 => \tap_cnt_cpt_r_reg_n_0_[0]\,
      I2 => \tap_cnt_cpt_r_reg_n_0_[1]\,
      O => \tap_cnt_cpt_r[1]_i_1_n_0\
    );
\tap_cnt_cpt_r[2]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6AA9"
    )
        port map (
      I0 => \tap_cnt_cpt_r_reg_n_0_[2]\,
      I1 => \tap_cnt_cpt_r_reg_n_0_[0]\,
      I2 => \tap_cnt_cpt_r_reg_n_0_[1]\,
      I3 => cal1_dlyinc_cpt_r_reg_n_0,
      O => \p_0_in__0\(2)
    );
\tap_cnt_cpt_r[3]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"6CCCCCC9"
    )
        port map (
      I0 => cal1_dlyinc_cpt_r_reg_n_0,
      I1 => \tap_cnt_cpt_r_reg_n_0_[3]\,
      I2 => \tap_cnt_cpt_r_reg_n_0_[2]\,
      I3 => \tap_cnt_cpt_r_reg_n_0_[1]\,
      I4 => \tap_cnt_cpt_r_reg_n_0_[0]\,
      O => \p_0_in__0\(3)
    );
\tap_cnt_cpt_r[4]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"6CCCCCCCCCCCCCC9"
    )
        port map (
      I0 => cal1_dlyinc_cpt_r_reg_n_0,
      I1 => \tap_cnt_cpt_r_reg_n_0_[4]\,
      I2 => \tap_cnt_cpt_r_reg_n_0_[3]\,
      I3 => \tap_cnt_cpt_r_reg_n_0_[0]\,
      I4 => \tap_cnt_cpt_r_reg_n_0_[1]\,
      I5 => \tap_cnt_cpt_r_reg_n_0_[2]\,
      O => \p_0_in__0\(4)
    );
\tap_cnt_cpt_r[5]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"AA8A"
    )
        port map (
      I0 => cal1_dlyce_cpt_r_reg_n_0,
      I1 => \tap_cnt_cpt_r_reg_n_0_[5]\,
      I2 => \tap_cnt_cpt_r[5]_i_4_n_0\,
      I3 => cal1_dlyinc_cpt_r_reg_n_0,
      O => tap_cnt_cpt_r
    );
\tap_cnt_cpt_r[5]_i_3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"1DD1"
    )
        port map (
      I0 => \tap_cnt_cpt_r[5]_i_5_n_0\,
      I1 => cal1_dlyinc_cpt_r_reg_n_0,
      I2 => \tap_cnt_cpt_r_reg_n_0_[5]\,
      I3 => \tap_cnt_cpt_r[5]_i_6_n_0\,
      O => \p_0_in__0\(5)
    );
\tap_cnt_cpt_r[5]_i_4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000001"
    )
        port map (
      I0 => \tap_cnt_cpt_r_reg_n_0_[3]\,
      I1 => \tap_cnt_cpt_r_reg_n_0_[0]\,
      I2 => \tap_cnt_cpt_r_reg_n_0_[1]\,
      I3 => \tap_cnt_cpt_r_reg_n_0_[2]\,
      I4 => \tap_cnt_cpt_r_reg_n_0_[4]\,
      O => \tap_cnt_cpt_r[5]_i_4_n_0\
    );
\tap_cnt_cpt_r[5]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"5555555555555556"
    )
        port map (
      I0 => \tap_cnt_cpt_r_reg_n_0_[5]\,
      I1 => \tap_cnt_cpt_r_reg_n_0_[4]\,
      I2 => \tap_cnt_cpt_r_reg_n_0_[2]\,
      I3 => \tap_cnt_cpt_r_reg_n_0_[1]\,
      I4 => \tap_cnt_cpt_r_reg_n_0_[0]\,
      I5 => \tap_cnt_cpt_r_reg_n_0_[3]\,
      O => \tap_cnt_cpt_r[5]_i_5_n_0\
    );
\tap_cnt_cpt_r[5]_i_6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"80000000"
    )
        port map (
      I0 => \tap_cnt_cpt_r_reg_n_0_[3]\,
      I1 => \tap_cnt_cpt_r_reg_n_0_[0]\,
      I2 => \tap_cnt_cpt_r_reg_n_0_[1]\,
      I3 => \tap_cnt_cpt_r_reg_n_0_[2]\,
      I4 => \tap_cnt_cpt_r_reg_n_0_[4]\,
      O => \tap_cnt_cpt_r[5]_i_6_n_0\
    );
\tap_cnt_cpt_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => tap_cnt_cpt_r,
      D => tap_cnt_cpt_r0(0),
      Q => \tap_cnt_cpt_r_reg_n_0_[0]\,
      R => \tap_cnt_cpt_r_reg[5]_0\(0)
    );
\tap_cnt_cpt_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => tap_cnt_cpt_r,
      D => \tap_cnt_cpt_r[1]_i_1_n_0\,
      Q => \tap_cnt_cpt_r_reg_n_0_[1]\,
      R => \tap_cnt_cpt_r_reg[5]_0\(0)
    );
\tap_cnt_cpt_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => tap_cnt_cpt_r,
      D => \p_0_in__0\(2),
      Q => \tap_cnt_cpt_r_reg_n_0_[2]\,
      R => \tap_cnt_cpt_r_reg[5]_0\(0)
    );
\tap_cnt_cpt_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => tap_cnt_cpt_r,
      D => \p_0_in__0\(3),
      Q => \tap_cnt_cpt_r_reg_n_0_[3]\,
      R => \tap_cnt_cpt_r_reg[5]_0\(0)
    );
\tap_cnt_cpt_r_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => tap_cnt_cpt_r,
      D => \p_0_in__0\(4),
      Q => \tap_cnt_cpt_r_reg_n_0_[4]\,
      R => \tap_cnt_cpt_r_reg[5]_0\(0)
    );
\tap_cnt_cpt_r_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => tap_cnt_cpt_r,
      D => \p_0_in__0\(5),
      Q => \tap_cnt_cpt_r_reg_n_0_[5]\,
      R => \tap_cnt_cpt_r_reg[5]_0\(0)
    );
tap_limit_cpt_r_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"000000000000AA80"
    )
        port map (
      I0 => tap_limit_cpt_r_i_2_n_0,
      I1 => \tap_cnt_cpt_r_reg_n_0_[5]\,
      I2 => \tap_cnt_cpt_r[5]_i_6_n_0\,
      I3 => tap_limit_cpt_r,
      I4 => \done_cnt_reg[2]_0\,
      I5 => \^new_cnt_cpt_r_reg_0\,
      O => tap_limit_cpt_r_i_1_n_0
    );
tap_limit_cpt_r_i_2: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFEFF"
    )
        port map (
      I0 => \cal1_state_r1_reg_n_0_[4]\,
      I1 => \cal1_state_r1_reg_n_0_[5]\,
      I2 => \cal1_state_r1_reg_n_0_[0]\,
      I3 => \cal1_state_r1_reg_n_0_[2]\,
      I4 => \cal1_state_r1_reg_n_0_[1]\,
      I5 => \cal1_state_r1_reg_n_0_[3]\,
      O => tap_limit_cpt_r_i_2_n_0
    );
tap_limit_cpt_r_reg: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => '1',
      D => tap_limit_cpt_r_i_1_n_0,
      Q => tap_limit_cpt_r,
      R => '0'
    );
\wait_cnt_r[0]_i_1__0\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => wait_cnt_r_reg(0),
      O => \wait_cnt_r0__0\(0)
    );
\wait_cnt_r[1]_i_1__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => wait_cnt_r_reg(1),
      I1 => wait_cnt_r_reg(0),
      O => \wait_cnt_r[1]_i_1__0_n_0\
    );
\wait_cnt_r[2]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"A9"
    )
        port map (
      I0 => wait_cnt_r_reg(2),
      I1 => wait_cnt_r_reg(0),
      I2 => wait_cnt_r_reg(1),
      O => \wait_cnt_r0__0\(2)
    );
\wait_cnt_r[3]_i_2__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AAAAAAA8"
    )
        port map (
      I0 => dqs_po_dec_done_r2,
      I1 => wait_cnt_r_reg(2),
      I2 => wait_cnt_r_reg(3),
      I3 => wait_cnt_r_reg(1),
      I4 => wait_cnt_r_reg(0),
      O => wait_cnt_r0
    );
\wait_cnt_r[3]_i_3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"AAA9"
    )
        port map (
      I0 => wait_cnt_r_reg(3),
      I1 => wait_cnt_r_reg(2),
      I2 => wait_cnt_r_reg(1),
      I3 => wait_cnt_r_reg(0),
      O => \wait_cnt_r0__0\(3)
    );
\wait_cnt_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => wait_cnt_r0,
      D => \wait_cnt_r0__0\(0),
      Q => wait_cnt_r_reg(0),
      R => \wait_cnt_r_reg[0]_0\(0)
    );
\wait_cnt_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => wait_cnt_r0,
      D => \wait_cnt_r[1]_i_1__0_n_0\,
      Q => wait_cnt_r_reg(1),
      R => \wait_cnt_r_reg[0]_0\(0)
    );
\wait_cnt_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => wait_cnt_r0,
      D => \wait_cnt_r0__0\(2),
      Q => wait_cnt_r_reg(2),
      R => \wait_cnt_r_reg[0]_0\(0)
    );
\wait_cnt_r_reg[3]\: unisim.vcomponents.FDSE
     port map (
      C => rdlvl_pi_incdec_reg_0,
      CE => wait_cnt_r0,
      D => \wait_cnt_r0__0\(3),
      Q => wait_cnt_r_reg(3),
      S => \wait_cnt_r_reg[0]_0\(0)
    );
\wrdq_div1_4to1_wrcal_first.phy_wrdata[510]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"7F"
    )
        port map (
      I0 => \^rdlvl_stg1_done_int_reg_0\,
      I1 => \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[56]\,
      I2 => \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[56]_0\,
      O => rdlvl_stg1_done_int_reg_2(0)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mig_mig_7series_v4_2_ddr_phy_tempmon is
  port (
    tempmon_pi_f_inc : out STD_LOGIC;
    tempmon_sel_pi_incdec : out STD_LOGIC;
    D : out STD_LOGIC_VECTOR ( 2 downto 0 );
    pi_f_inc_reg_0 : out STD_LOGIC;
    rdlvl_stg1_done_int_reg : out STD_LOGIC;
    calib_in_common4_out : out STD_LOGIC;
    pi_f_dec_reg_0 : in STD_LOGIC;
    \four_dec_min_limit_reg[0]_0\ : in STD_LOGIC;
    mc_ref_zq_wip : in STD_LOGIC;
    pi_f_dec_reg_1 : in STD_LOGIC_VECTOR ( 0 to 0 );
    \neutral_max_limit_reg[11]_0\ : in STD_LOGIC;
    \one_dec_min_limit_reg[11]_0\ : in STD_LOGIC;
    \device_temp_101_reg[0]_0\ : in STD_LOGIC;
    \one_dec_max_limit_reg[2]_0\ : in STD_LOGIC;
    calib_in_common : in STD_LOGIC;
    \calib_sel1__1\ : in STD_LOGIC;
    cmd_delay_start0 : in STD_LOGIC;
    \calib_zero_inputs_reg[2]\ : in STD_LOGIC;
    dqs_po_dec_done : in STD_LOGIC;
    pi_fine_dly_dec_done : in STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \gen_byte_sel_div2.calib_in_common_i_2\ : in STD_LOGIC;
    \gen_byte_sel_div2.calib_in_common_i_3\ : in STD_LOGIC;
    \gen_byte_sel_div2.calib_in_common_i_2_0\ : in STD_LOGIC;
    \gen_byte_sel_div2.calib_in_common_i_2_1\ : in STD_LOGIC;
    \calib_sel_reg[0]\ : in STD_LOGIC;
    calib_complete : in STD_LOGIC;
    \device_temp_101_reg[11]_0\ : in STD_LOGIC_VECTOR ( 11 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of mig_mig_7series_v4_2_ddr_phy_tempmon : entity is "mig_7series_v4_2_ddr_phy_tempmon";
end mig_mig_7series_v4_2_ddr_phy_tempmon;

architecture STRUCTURE of mig_mig_7series_v4_2_ddr_phy_tempmon is
  signal \calib_zero_inputs[0]_i_2_n_0\ : STD_LOGIC;
  signal \calib_zero_inputs[2]_i_2_n_0\ : STD_LOGIC;
  signal device_temp_101 : STD_LOGIC_VECTOR ( 11 downto 0 );
  signal device_temp_init : STD_LOGIC_VECTOR ( 11 downto 0 );
  signal \device_temp_init[11]_i_2_n_0\ : STD_LOGIC;
  signal \device_temp_init[11]_i_3_n_0\ : STD_LOGIC;
  signal four_dec_min_limit : STD_LOGIC_VECTOR ( 11 downto 0 );
  signal \four_dec_min_limit[11]_i_2_n_0\ : STD_LOGIC;
  signal \four_dec_min_limit[11]_i_3_n_0\ : STD_LOGIC;
  signal \four_dec_min_limit[5]_i_2_n_0\ : STD_LOGIC;
  signal \four_dec_min_limit[5]_i_3_n_0\ : STD_LOGIC;
  signal \four_dec_min_limit[5]_i_4_n_0\ : STD_LOGIC;
  signal \four_dec_min_limit[9]_i_2_n_0\ : STD_LOGIC;
  signal \four_dec_min_limit[9]_i_3_n_0\ : STD_LOGIC;
  signal \four_dec_min_limit[9]_i_4_n_0\ : STD_LOGIC;
  signal \four_dec_min_limit[9]_i_5_n_0\ : STD_LOGIC;
  signal four_dec_min_limit_nxt : STD_LOGIC_VECTOR ( 11 downto 2 );
  signal \four_dec_min_limit_reg[11]_i_1_n_3\ : STD_LOGIC;
  signal \four_dec_min_limit_reg[5]_i_1_n_0\ : STD_LOGIC;
  signal \four_dec_min_limit_reg[5]_i_1_n_1\ : STD_LOGIC;
  signal \four_dec_min_limit_reg[5]_i_1_n_2\ : STD_LOGIC;
  signal \four_dec_min_limit_reg[5]_i_1_n_3\ : STD_LOGIC;
  signal \four_dec_min_limit_reg[9]_i_1_n_0\ : STD_LOGIC;
  signal \four_dec_min_limit_reg[9]_i_1_n_1\ : STD_LOGIC;
  signal \four_dec_min_limit_reg[9]_i_1_n_2\ : STD_LOGIC;
  signal \four_dec_min_limit_reg[9]_i_1_n_3\ : STD_LOGIC;
  signal four_inc_max_limit : STD_LOGIC_VECTOR ( 11 downto 2 );
  signal \four_inc_max_limit[11]_i_2_n_0\ : STD_LOGIC;
  signal \four_inc_max_limit[11]_i_3_n_0\ : STD_LOGIC;
  signal \four_inc_max_limit[4]_i_2_n_0\ : STD_LOGIC;
  signal \four_inc_max_limit[4]_i_3_n_0\ : STD_LOGIC;
  signal \four_inc_max_limit[4]_i_4_n_0\ : STD_LOGIC;
  signal \four_inc_max_limit[4]_i_5_n_0\ : STD_LOGIC;
  signal \four_inc_max_limit[8]_i_2_n_0\ : STD_LOGIC;
  signal \four_inc_max_limit[8]_i_3_n_0\ : STD_LOGIC;
  signal four_inc_max_limit_nxt : STD_LOGIC_VECTOR ( 11 downto 2 );
  signal \four_inc_max_limit_reg[11]_i_1_n_2\ : STD_LOGIC;
  signal \four_inc_max_limit_reg[11]_i_1_n_3\ : STD_LOGIC;
  signal \four_inc_max_limit_reg[4]_i_1_n_0\ : STD_LOGIC;
  signal \four_inc_max_limit_reg[4]_i_1_n_1\ : STD_LOGIC;
  signal \four_inc_max_limit_reg[4]_i_1_n_2\ : STD_LOGIC;
  signal \four_inc_max_limit_reg[4]_i_1_n_3\ : STD_LOGIC;
  signal \four_inc_max_limit_reg[8]_i_1_n_0\ : STD_LOGIC;
  signal \four_inc_max_limit_reg[8]_i_1_n_1\ : STD_LOGIC;
  signal \four_inc_max_limit_reg[8]_i_1_n_2\ : STD_LOGIC;
  signal \four_inc_max_limit_reg[8]_i_1_n_3\ : STD_LOGIC;
  signal neutral_max_limit : STD_LOGIC_VECTOR ( 11 downto 2 );
  signal \neutral_max_limit[4]_i_2_n_0\ : STD_LOGIC;
  signal \neutral_max_limit[4]_i_3_n_0\ : STD_LOGIC;
  signal \neutral_max_limit[4]_i_4_n_0\ : STD_LOGIC;
  signal \neutral_max_limit[8]_i_2_n_0\ : STD_LOGIC;
  signal \neutral_max_limit[8]_i_3_n_0\ : STD_LOGIC;
  signal neutral_max_limit_nxt : STD_LOGIC_VECTOR ( 11 downto 2 );
  signal \neutral_max_limit_reg[11]_i_1_n_2\ : STD_LOGIC;
  signal \neutral_max_limit_reg[11]_i_1_n_3\ : STD_LOGIC;
  signal \neutral_max_limit_reg[4]_i_1_n_0\ : STD_LOGIC;
  signal \neutral_max_limit_reg[4]_i_1_n_1\ : STD_LOGIC;
  signal \neutral_max_limit_reg[4]_i_1_n_2\ : STD_LOGIC;
  signal \neutral_max_limit_reg[4]_i_1_n_3\ : STD_LOGIC;
  signal \neutral_max_limit_reg[8]_i_1_n_0\ : STD_LOGIC;
  signal \neutral_max_limit_reg[8]_i_1_n_1\ : STD_LOGIC;
  signal \neutral_max_limit_reg[8]_i_1_n_2\ : STD_LOGIC;
  signal \neutral_max_limit_reg[8]_i_1_n_3\ : STD_LOGIC;
  signal neutral_min_limit : STD_LOGIC_VECTOR ( 11 downto 2 );
  signal \neutral_min_limit[11]_i_2_n_0\ : STD_LOGIC;
  signal \neutral_min_limit[11]_i_3_n_0\ : STD_LOGIC;
  signal \neutral_min_limit[5]_i_2_n_0\ : STD_LOGIC;
  signal \neutral_min_limit[5]_i_3_n_0\ : STD_LOGIC;
  signal \neutral_min_limit[5]_i_4_n_0\ : STD_LOGIC;
  signal \neutral_min_limit[9]_i_2_n_0\ : STD_LOGIC;
  signal \neutral_min_limit[9]_i_3_n_0\ : STD_LOGIC;
  signal \neutral_min_limit[9]_i_4_n_0\ : STD_LOGIC;
  signal \neutral_min_limit[9]_i_5_n_0\ : STD_LOGIC;
  signal neutral_min_limit_nxt : STD_LOGIC_VECTOR ( 11 downto 2 );
  signal \neutral_min_limit_reg[11]_i_1_n_3\ : STD_LOGIC;
  signal \neutral_min_limit_reg[5]_i_1_n_0\ : STD_LOGIC;
  signal \neutral_min_limit_reg[5]_i_1_n_1\ : STD_LOGIC;
  signal \neutral_min_limit_reg[5]_i_1_n_2\ : STD_LOGIC;
  signal \neutral_min_limit_reg[5]_i_1_n_3\ : STD_LOGIC;
  signal \neutral_min_limit_reg[9]_i_1_n_0\ : STD_LOGIC;
  signal \neutral_min_limit_reg[9]_i_1_n_1\ : STD_LOGIC;
  signal \neutral_min_limit_reg[9]_i_1_n_2\ : STD_LOGIC;
  signal \neutral_min_limit_reg[9]_i_1_n_3\ : STD_LOGIC;
  signal one_dec_max_limit : STD_LOGIC_VECTOR ( 11 downto 2 );
  signal \one_dec_max_limit[4]_i_2_n_0\ : STD_LOGIC;
  signal \one_dec_max_limit[8]_i_2_n_0\ : STD_LOGIC;
  signal \one_dec_max_limit[8]_i_3_n_0\ : STD_LOGIC;
  signal \one_dec_max_limit[8]_i_4_n_0\ : STD_LOGIC;
  signal one_dec_max_limit_nxt : STD_LOGIC_VECTOR ( 11 downto 2 );
  signal \one_dec_max_limit_reg[11]_i_1_n_2\ : STD_LOGIC;
  signal \one_dec_max_limit_reg[11]_i_1_n_3\ : STD_LOGIC;
  signal \one_dec_max_limit_reg[4]_i_1_n_0\ : STD_LOGIC;
  signal \one_dec_max_limit_reg[4]_i_1_n_1\ : STD_LOGIC;
  signal \one_dec_max_limit_reg[4]_i_1_n_2\ : STD_LOGIC;
  signal \one_dec_max_limit_reg[4]_i_1_n_3\ : STD_LOGIC;
  signal \one_dec_max_limit_reg[8]_i_1_n_0\ : STD_LOGIC;
  signal \one_dec_max_limit_reg[8]_i_1_n_1\ : STD_LOGIC;
  signal \one_dec_max_limit_reg[8]_i_1_n_2\ : STD_LOGIC;
  signal \one_dec_max_limit_reg[8]_i_1_n_3\ : STD_LOGIC;
  signal one_dec_min_limit : STD_LOGIC_VECTOR ( 11 downto 2 );
  signal \one_dec_min_limit[11]_i_2_n_0\ : STD_LOGIC;
  signal \one_dec_min_limit[11]_i_3_n_0\ : STD_LOGIC;
  signal \one_dec_min_limit[5]_i_2_n_0\ : STD_LOGIC;
  signal \one_dec_min_limit[5]_i_3_n_0\ : STD_LOGIC;
  signal \one_dec_min_limit[5]_i_4_n_0\ : STD_LOGIC;
  signal \one_dec_min_limit[9]_i_2_n_0\ : STD_LOGIC;
  signal \one_dec_min_limit[9]_i_3_n_0\ : STD_LOGIC;
  signal \one_dec_min_limit[9]_i_4_n_0\ : STD_LOGIC;
  signal \one_dec_min_limit[9]_i_5_n_0\ : STD_LOGIC;
  signal one_dec_min_limit_nxt : STD_LOGIC_VECTOR ( 11 downto 2 );
  signal \one_dec_min_limit_reg[11]_i_1_n_3\ : STD_LOGIC;
  signal \one_dec_min_limit_reg[5]_i_1_n_0\ : STD_LOGIC;
  signal \one_dec_min_limit_reg[5]_i_1_n_1\ : STD_LOGIC;
  signal \one_dec_min_limit_reg[5]_i_1_n_2\ : STD_LOGIC;
  signal \one_dec_min_limit_reg[5]_i_1_n_3\ : STD_LOGIC;
  signal \one_dec_min_limit_reg[9]_i_1_n_0\ : STD_LOGIC;
  signal \one_dec_min_limit_reg[9]_i_1_n_1\ : STD_LOGIC;
  signal \one_dec_min_limit_reg[9]_i_1_n_2\ : STD_LOGIC;
  signal \one_dec_min_limit_reg[9]_i_1_n_3\ : STD_LOGIC;
  signal one_inc_max_limit : STD_LOGIC_VECTOR ( 11 downto 1 );
  signal \one_inc_max_limit[11]_i_2_n_0\ : STD_LOGIC;
  signal \one_inc_max_limit[11]_i_3_n_0\ : STD_LOGIC;
  signal \one_inc_max_limit[11]_i_4_n_0\ : STD_LOGIC;
  signal \one_inc_max_limit[4]_i_2_n_0\ : STD_LOGIC;
  signal \one_inc_max_limit[8]_i_2_n_0\ : STD_LOGIC;
  signal \one_inc_max_limit[8]_i_3_n_0\ : STD_LOGIC;
  signal one_inc_max_limit_nxt : STD_LOGIC_VECTOR ( 11 downto 1 );
  signal \one_inc_max_limit_reg[11]_i_1_n_2\ : STD_LOGIC;
  signal \one_inc_max_limit_reg[11]_i_1_n_3\ : STD_LOGIC;
  signal \one_inc_max_limit_reg[4]_i_1_n_0\ : STD_LOGIC;
  signal \one_inc_max_limit_reg[4]_i_1_n_1\ : STD_LOGIC;
  signal \one_inc_max_limit_reg[4]_i_1_n_2\ : STD_LOGIC;
  signal \one_inc_max_limit_reg[4]_i_1_n_3\ : STD_LOGIC;
  signal \one_inc_max_limit_reg[8]_i_1_n_0\ : STD_LOGIC;
  signal \one_inc_max_limit_reg[8]_i_1_n_1\ : STD_LOGIC;
  signal \one_inc_max_limit_reg[8]_i_1_n_2\ : STD_LOGIC;
  signal \one_inc_max_limit_reg[8]_i_1_n_3\ : STD_LOGIC;
  signal one_inc_min_limit : STD_LOGIC_VECTOR ( 11 downto 1 );
  signal \one_inc_min_limit[11]_i_2_n_0\ : STD_LOGIC;
  signal \one_inc_min_limit[11]_i_3_n_0\ : STD_LOGIC;
  signal \one_inc_min_limit[5]_i_2_n_0\ : STD_LOGIC;
  signal \one_inc_min_limit[5]_i_3_n_0\ : STD_LOGIC;
  signal \one_inc_min_limit[5]_i_4_n_0\ : STD_LOGIC;
  signal \one_inc_min_limit[9]_i_2_n_0\ : STD_LOGIC;
  signal \one_inc_min_limit[9]_i_3_n_0\ : STD_LOGIC;
  signal \one_inc_min_limit[9]_i_4_n_0\ : STD_LOGIC;
  signal \one_inc_min_limit[9]_i_5_n_0\ : STD_LOGIC;
  signal one_inc_min_limit_nxt : STD_LOGIC_VECTOR ( 11 downto 2 );
  signal \one_inc_min_limit_reg[11]_i_1_n_3\ : STD_LOGIC;
  signal \one_inc_min_limit_reg[5]_i_1_n_0\ : STD_LOGIC;
  signal \one_inc_min_limit_reg[5]_i_1_n_1\ : STD_LOGIC;
  signal \one_inc_min_limit_reg[5]_i_1_n_2\ : STD_LOGIC;
  signal \one_inc_min_limit_reg[5]_i_1_n_3\ : STD_LOGIC;
  signal \one_inc_min_limit_reg[9]_i_1_n_0\ : STD_LOGIC;
  signal \one_inc_min_limit_reg[9]_i_1_n_1\ : STD_LOGIC;
  signal \one_inc_min_limit_reg[9]_i_1_n_2\ : STD_LOGIC;
  signal \one_inc_min_limit_reg[9]_i_1_n_3\ : STD_LOGIC;
  signal p_0_in : STD_LOGIC;
  signal pi_f_dec_i_2_n_0 : STD_LOGIC;
  signal pi_f_dec_nxt : STD_LOGIC;
  signal pi_f_inc_i_2_n_0 : STD_LOGIC;
  signal pi_f_inc_i_3_n_0 : STD_LOGIC;
  signal pi_f_inc_i_4_n_0 : STD_LOGIC;
  signal pi_f_inc_i_5_n_0 : STD_LOGIC;
  signal pi_f_inc_i_6_n_0 : STD_LOGIC;
  signal pi_f_inc_i_7_n_0 : STD_LOGIC;
  signal pi_f_inc_nxt : STD_LOGIC;
  signal \^pi_f_inc_reg_0\ : STD_LOGIC;
  signal temp_cmp_four_dec_min_101 : STD_LOGIC;
  signal temp_cmp_four_dec_min_102 : STD_LOGIC;
  signal temp_cmp_four_dec_min_102_i_10_n_0 : STD_LOGIC;
  signal temp_cmp_four_dec_min_102_i_11_n_0 : STD_LOGIC;
  signal temp_cmp_four_dec_min_102_i_12_n_0 : STD_LOGIC;
  signal temp_cmp_four_dec_min_102_i_13_n_0 : STD_LOGIC;
  signal temp_cmp_four_dec_min_102_i_14_n_0 : STD_LOGIC;
  signal temp_cmp_four_dec_min_102_i_3_n_0 : STD_LOGIC;
  signal temp_cmp_four_dec_min_102_i_4_n_0 : STD_LOGIC;
  signal temp_cmp_four_dec_min_102_i_5_n_0 : STD_LOGIC;
  signal temp_cmp_four_dec_min_102_i_6_n_0 : STD_LOGIC;
  signal temp_cmp_four_dec_min_102_i_7_n_0 : STD_LOGIC;
  signal temp_cmp_four_dec_min_102_i_8_n_0 : STD_LOGIC;
  signal temp_cmp_four_dec_min_102_i_9_n_0 : STD_LOGIC;
  signal temp_cmp_four_dec_min_102_reg_i_1_n_3 : STD_LOGIC;
  signal temp_cmp_four_dec_min_102_reg_i_2_n_0 : STD_LOGIC;
  signal temp_cmp_four_dec_min_102_reg_i_2_n_1 : STD_LOGIC;
  signal temp_cmp_four_dec_min_102_reg_i_2_n_2 : STD_LOGIC;
  signal temp_cmp_four_dec_min_102_reg_i_2_n_3 : STD_LOGIC;
  signal temp_cmp_four_inc_max_101 : STD_LOGIC;
  signal temp_cmp_four_inc_max_102 : STD_LOGIC;
  signal temp_cmp_four_inc_max_102_i_10_n_0 : STD_LOGIC;
  signal temp_cmp_four_inc_max_102_i_11_n_0 : STD_LOGIC;
  signal temp_cmp_four_inc_max_102_i_12_n_0 : STD_LOGIC;
  signal temp_cmp_four_inc_max_102_i_13_n_0 : STD_LOGIC;
  signal temp_cmp_four_inc_max_102_i_14_n_0 : STD_LOGIC;
  signal temp_cmp_four_inc_max_102_i_3_n_0 : STD_LOGIC;
  signal temp_cmp_four_inc_max_102_i_4_n_0 : STD_LOGIC;
  signal temp_cmp_four_inc_max_102_i_5_n_0 : STD_LOGIC;
  signal temp_cmp_four_inc_max_102_i_6_n_0 : STD_LOGIC;
  signal temp_cmp_four_inc_max_102_i_7_n_0 : STD_LOGIC;
  signal temp_cmp_four_inc_max_102_i_8_n_0 : STD_LOGIC;
  signal temp_cmp_four_inc_max_102_i_9_n_0 : STD_LOGIC;
  signal temp_cmp_four_inc_max_102_reg_i_1_n_3 : STD_LOGIC;
  signal temp_cmp_four_inc_max_102_reg_i_2_n_0 : STD_LOGIC;
  signal temp_cmp_four_inc_max_102_reg_i_2_n_1 : STD_LOGIC;
  signal temp_cmp_four_inc_max_102_reg_i_2_n_2 : STD_LOGIC;
  signal temp_cmp_four_inc_max_102_reg_i_2_n_3 : STD_LOGIC;
  signal temp_cmp_neutral_max_101 : STD_LOGIC;
  signal temp_cmp_neutral_max_102 : STD_LOGIC;
  signal temp_cmp_neutral_max_102_i_10_n_0 : STD_LOGIC;
  signal temp_cmp_neutral_max_102_i_11_n_0 : STD_LOGIC;
  signal temp_cmp_neutral_max_102_i_12_n_0 : STD_LOGIC;
  signal temp_cmp_neutral_max_102_i_13_n_0 : STD_LOGIC;
  signal temp_cmp_neutral_max_102_i_14_n_0 : STD_LOGIC;
  signal temp_cmp_neutral_max_102_i_3_n_0 : STD_LOGIC;
  signal temp_cmp_neutral_max_102_i_4_n_0 : STD_LOGIC;
  signal temp_cmp_neutral_max_102_i_5_n_0 : STD_LOGIC;
  signal temp_cmp_neutral_max_102_i_6_n_0 : STD_LOGIC;
  signal temp_cmp_neutral_max_102_i_7_n_0 : STD_LOGIC;
  signal temp_cmp_neutral_max_102_i_8_n_0 : STD_LOGIC;
  signal temp_cmp_neutral_max_102_i_9_n_0 : STD_LOGIC;
  signal temp_cmp_neutral_max_102_reg_i_1_n_3 : STD_LOGIC;
  signal temp_cmp_neutral_max_102_reg_i_2_n_0 : STD_LOGIC;
  signal temp_cmp_neutral_max_102_reg_i_2_n_1 : STD_LOGIC;
  signal temp_cmp_neutral_max_102_reg_i_2_n_2 : STD_LOGIC;
  signal temp_cmp_neutral_max_102_reg_i_2_n_3 : STD_LOGIC;
  signal temp_cmp_neutral_min_101 : STD_LOGIC;
  signal temp_cmp_neutral_min_102 : STD_LOGIC;
  signal temp_cmp_neutral_min_102_i_10_n_0 : STD_LOGIC;
  signal temp_cmp_neutral_min_102_i_11_n_0 : STD_LOGIC;
  signal temp_cmp_neutral_min_102_i_12_n_0 : STD_LOGIC;
  signal temp_cmp_neutral_min_102_i_13_n_0 : STD_LOGIC;
  signal temp_cmp_neutral_min_102_i_14_n_0 : STD_LOGIC;
  signal temp_cmp_neutral_min_102_i_3_n_0 : STD_LOGIC;
  signal temp_cmp_neutral_min_102_i_4_n_0 : STD_LOGIC;
  signal temp_cmp_neutral_min_102_i_5_n_0 : STD_LOGIC;
  signal temp_cmp_neutral_min_102_i_6_n_0 : STD_LOGIC;
  signal temp_cmp_neutral_min_102_i_7_n_0 : STD_LOGIC;
  signal temp_cmp_neutral_min_102_i_8_n_0 : STD_LOGIC;
  signal temp_cmp_neutral_min_102_i_9_n_0 : STD_LOGIC;
  signal temp_cmp_neutral_min_102_reg_i_1_n_3 : STD_LOGIC;
  signal temp_cmp_neutral_min_102_reg_i_2_n_0 : STD_LOGIC;
  signal temp_cmp_neutral_min_102_reg_i_2_n_1 : STD_LOGIC;
  signal temp_cmp_neutral_min_102_reg_i_2_n_2 : STD_LOGIC;
  signal temp_cmp_neutral_min_102_reg_i_2_n_3 : STD_LOGIC;
  signal temp_cmp_one_dec_max_101 : STD_LOGIC;
  signal temp_cmp_one_dec_max_102 : STD_LOGIC;
  signal temp_cmp_one_dec_max_102_i_10_n_0 : STD_LOGIC;
  signal temp_cmp_one_dec_max_102_i_11_n_0 : STD_LOGIC;
  signal temp_cmp_one_dec_max_102_i_12_n_0 : STD_LOGIC;
  signal temp_cmp_one_dec_max_102_i_13_n_0 : STD_LOGIC;
  signal temp_cmp_one_dec_max_102_i_14_n_0 : STD_LOGIC;
  signal temp_cmp_one_dec_max_102_i_3_n_0 : STD_LOGIC;
  signal temp_cmp_one_dec_max_102_i_4_n_0 : STD_LOGIC;
  signal temp_cmp_one_dec_max_102_i_5_n_0 : STD_LOGIC;
  signal temp_cmp_one_dec_max_102_i_6_n_0 : STD_LOGIC;
  signal temp_cmp_one_dec_max_102_i_7_n_0 : STD_LOGIC;
  signal temp_cmp_one_dec_max_102_i_8_n_0 : STD_LOGIC;
  signal temp_cmp_one_dec_max_102_i_9_n_0 : STD_LOGIC;
  signal temp_cmp_one_dec_max_102_reg_i_1_n_3 : STD_LOGIC;
  signal temp_cmp_one_dec_max_102_reg_i_2_n_0 : STD_LOGIC;
  signal temp_cmp_one_dec_max_102_reg_i_2_n_1 : STD_LOGIC;
  signal temp_cmp_one_dec_max_102_reg_i_2_n_2 : STD_LOGIC;
  signal temp_cmp_one_dec_max_102_reg_i_2_n_3 : STD_LOGIC;
  signal temp_cmp_one_dec_min_101 : STD_LOGIC;
  signal temp_cmp_one_dec_min_102 : STD_LOGIC;
  signal temp_cmp_one_dec_min_102_i_10_n_0 : STD_LOGIC;
  signal temp_cmp_one_dec_min_102_i_11_n_0 : STD_LOGIC;
  signal temp_cmp_one_dec_min_102_i_12_n_0 : STD_LOGIC;
  signal temp_cmp_one_dec_min_102_i_13_n_0 : STD_LOGIC;
  signal temp_cmp_one_dec_min_102_i_14_n_0 : STD_LOGIC;
  signal temp_cmp_one_dec_min_102_i_3_n_0 : STD_LOGIC;
  signal temp_cmp_one_dec_min_102_i_4_n_0 : STD_LOGIC;
  signal temp_cmp_one_dec_min_102_i_5_n_0 : STD_LOGIC;
  signal temp_cmp_one_dec_min_102_i_6_n_0 : STD_LOGIC;
  signal temp_cmp_one_dec_min_102_i_7_n_0 : STD_LOGIC;
  signal temp_cmp_one_dec_min_102_i_8_n_0 : STD_LOGIC;
  signal temp_cmp_one_dec_min_102_i_9_n_0 : STD_LOGIC;
  signal temp_cmp_one_dec_min_102_reg_i_1_n_3 : STD_LOGIC;
  signal temp_cmp_one_dec_min_102_reg_i_2_n_0 : STD_LOGIC;
  signal temp_cmp_one_dec_min_102_reg_i_2_n_1 : STD_LOGIC;
  signal temp_cmp_one_dec_min_102_reg_i_2_n_2 : STD_LOGIC;
  signal temp_cmp_one_dec_min_102_reg_i_2_n_3 : STD_LOGIC;
  signal temp_cmp_one_inc_max_101 : STD_LOGIC;
  signal temp_cmp_one_inc_max_102 : STD_LOGIC;
  signal temp_cmp_one_inc_max_102_i_10_n_0 : STD_LOGIC;
  signal temp_cmp_one_inc_max_102_i_11_n_0 : STD_LOGIC;
  signal temp_cmp_one_inc_max_102_i_12_n_0 : STD_LOGIC;
  signal temp_cmp_one_inc_max_102_i_13_n_0 : STD_LOGIC;
  signal temp_cmp_one_inc_max_102_i_14_n_0 : STD_LOGIC;
  signal temp_cmp_one_inc_max_102_i_3_n_0 : STD_LOGIC;
  signal temp_cmp_one_inc_max_102_i_4_n_0 : STD_LOGIC;
  signal temp_cmp_one_inc_max_102_i_5_n_0 : STD_LOGIC;
  signal temp_cmp_one_inc_max_102_i_6_n_0 : STD_LOGIC;
  signal temp_cmp_one_inc_max_102_i_7_n_0 : STD_LOGIC;
  signal temp_cmp_one_inc_max_102_i_8_n_0 : STD_LOGIC;
  signal temp_cmp_one_inc_max_102_i_9_n_0 : STD_LOGIC;
  signal temp_cmp_one_inc_max_102_reg_i_1_n_3 : STD_LOGIC;
  signal temp_cmp_one_inc_max_102_reg_i_2_n_0 : STD_LOGIC;
  signal temp_cmp_one_inc_max_102_reg_i_2_n_1 : STD_LOGIC;
  signal temp_cmp_one_inc_max_102_reg_i_2_n_2 : STD_LOGIC;
  signal temp_cmp_one_inc_max_102_reg_i_2_n_3 : STD_LOGIC;
  signal temp_cmp_one_inc_min_101 : STD_LOGIC;
  signal temp_cmp_one_inc_min_102 : STD_LOGIC;
  signal temp_cmp_one_inc_min_102_i_10_n_0 : STD_LOGIC;
  signal temp_cmp_one_inc_min_102_i_11_n_0 : STD_LOGIC;
  signal temp_cmp_one_inc_min_102_i_12_n_0 : STD_LOGIC;
  signal temp_cmp_one_inc_min_102_i_13_n_0 : STD_LOGIC;
  signal temp_cmp_one_inc_min_102_i_14_n_0 : STD_LOGIC;
  signal temp_cmp_one_inc_min_102_i_3_n_0 : STD_LOGIC;
  signal temp_cmp_one_inc_min_102_i_4_n_0 : STD_LOGIC;
  signal temp_cmp_one_inc_min_102_i_5_n_0 : STD_LOGIC;
  signal temp_cmp_one_inc_min_102_i_6_n_0 : STD_LOGIC;
  signal temp_cmp_one_inc_min_102_i_7_n_0 : STD_LOGIC;
  signal temp_cmp_one_inc_min_102_i_8_n_0 : STD_LOGIC;
  signal temp_cmp_one_inc_min_102_i_9_n_0 : STD_LOGIC;
  signal temp_cmp_one_inc_min_102_reg_i_1_n_3 : STD_LOGIC;
  signal temp_cmp_one_inc_min_102_reg_i_2_n_0 : STD_LOGIC;
  signal temp_cmp_one_inc_min_102_reg_i_2_n_1 : STD_LOGIC;
  signal temp_cmp_one_inc_min_102_reg_i_2_n_2 : STD_LOGIC;
  signal temp_cmp_one_inc_min_102_reg_i_2_n_3 : STD_LOGIC;
  signal temp_cmp_three_dec_max_101 : STD_LOGIC;
  signal temp_cmp_three_dec_max_102 : STD_LOGIC;
  signal temp_cmp_three_dec_max_102_i_10_n_0 : STD_LOGIC;
  signal temp_cmp_three_dec_max_102_i_11_n_0 : STD_LOGIC;
  signal temp_cmp_three_dec_max_102_i_12_n_0 : STD_LOGIC;
  signal temp_cmp_three_dec_max_102_i_13_n_0 : STD_LOGIC;
  signal temp_cmp_three_dec_max_102_i_14_n_0 : STD_LOGIC;
  signal temp_cmp_three_dec_max_102_i_3_n_0 : STD_LOGIC;
  signal temp_cmp_three_dec_max_102_i_4_n_0 : STD_LOGIC;
  signal temp_cmp_three_dec_max_102_i_5_n_0 : STD_LOGIC;
  signal temp_cmp_three_dec_max_102_i_6_n_0 : STD_LOGIC;
  signal temp_cmp_three_dec_max_102_i_7_n_0 : STD_LOGIC;
  signal temp_cmp_three_dec_max_102_i_8_n_0 : STD_LOGIC;
  signal temp_cmp_three_dec_max_102_i_9_n_0 : STD_LOGIC;
  signal temp_cmp_three_dec_max_102_reg_i_1_n_3 : STD_LOGIC;
  signal temp_cmp_three_dec_max_102_reg_i_2_n_0 : STD_LOGIC;
  signal temp_cmp_three_dec_max_102_reg_i_2_n_1 : STD_LOGIC;
  signal temp_cmp_three_dec_max_102_reg_i_2_n_2 : STD_LOGIC;
  signal temp_cmp_three_dec_max_102_reg_i_2_n_3 : STD_LOGIC;
  signal temp_cmp_three_dec_min_101 : STD_LOGIC;
  signal temp_cmp_three_dec_min_102 : STD_LOGIC;
  signal temp_cmp_three_dec_min_102_i_10_n_0 : STD_LOGIC;
  signal temp_cmp_three_dec_min_102_i_11_n_0 : STD_LOGIC;
  signal temp_cmp_three_dec_min_102_i_12_n_0 : STD_LOGIC;
  signal temp_cmp_three_dec_min_102_i_13_n_0 : STD_LOGIC;
  signal temp_cmp_three_dec_min_102_i_14_n_0 : STD_LOGIC;
  signal temp_cmp_three_dec_min_102_i_3_n_0 : STD_LOGIC;
  signal temp_cmp_three_dec_min_102_i_4_n_0 : STD_LOGIC;
  signal temp_cmp_three_dec_min_102_i_5_n_0 : STD_LOGIC;
  signal temp_cmp_three_dec_min_102_i_6_n_0 : STD_LOGIC;
  signal temp_cmp_three_dec_min_102_i_7_n_0 : STD_LOGIC;
  signal temp_cmp_three_dec_min_102_i_8_n_0 : STD_LOGIC;
  signal temp_cmp_three_dec_min_102_i_9_n_0 : STD_LOGIC;
  signal temp_cmp_three_dec_min_102_reg_i_1_n_3 : STD_LOGIC;
  signal temp_cmp_three_dec_min_102_reg_i_2_n_0 : STD_LOGIC;
  signal temp_cmp_three_dec_min_102_reg_i_2_n_1 : STD_LOGIC;
  signal temp_cmp_three_dec_min_102_reg_i_2_n_2 : STD_LOGIC;
  signal temp_cmp_three_dec_min_102_reg_i_2_n_3 : STD_LOGIC;
  signal temp_cmp_three_inc_max_101 : STD_LOGIC;
  signal temp_cmp_three_inc_max_102 : STD_LOGIC;
  signal temp_cmp_three_inc_max_102_i_10_n_0 : STD_LOGIC;
  signal temp_cmp_three_inc_max_102_i_11_n_0 : STD_LOGIC;
  signal temp_cmp_three_inc_max_102_i_12_n_0 : STD_LOGIC;
  signal temp_cmp_three_inc_max_102_i_13_n_0 : STD_LOGIC;
  signal temp_cmp_three_inc_max_102_i_14_n_0 : STD_LOGIC;
  signal temp_cmp_three_inc_max_102_i_3_n_0 : STD_LOGIC;
  signal temp_cmp_three_inc_max_102_i_4_n_0 : STD_LOGIC;
  signal temp_cmp_three_inc_max_102_i_5_n_0 : STD_LOGIC;
  signal temp_cmp_three_inc_max_102_i_6_n_0 : STD_LOGIC;
  signal temp_cmp_three_inc_max_102_i_7_n_0 : STD_LOGIC;
  signal temp_cmp_three_inc_max_102_i_8_n_0 : STD_LOGIC;
  signal temp_cmp_three_inc_max_102_i_9_n_0 : STD_LOGIC;
  signal temp_cmp_three_inc_max_102_reg_i_1_n_3 : STD_LOGIC;
  signal temp_cmp_three_inc_max_102_reg_i_2_n_0 : STD_LOGIC;
  signal temp_cmp_three_inc_max_102_reg_i_2_n_1 : STD_LOGIC;
  signal temp_cmp_three_inc_max_102_reg_i_2_n_2 : STD_LOGIC;
  signal temp_cmp_three_inc_max_102_reg_i_2_n_3 : STD_LOGIC;
  signal temp_cmp_three_inc_min_101 : STD_LOGIC;
  signal temp_cmp_three_inc_min_102 : STD_LOGIC;
  signal temp_cmp_three_inc_min_102_i_10_n_0 : STD_LOGIC;
  signal temp_cmp_three_inc_min_102_i_11_n_0 : STD_LOGIC;
  signal temp_cmp_three_inc_min_102_i_12_n_0 : STD_LOGIC;
  signal temp_cmp_three_inc_min_102_i_13_n_0 : STD_LOGIC;
  signal temp_cmp_three_inc_min_102_i_14_n_0 : STD_LOGIC;
  signal temp_cmp_three_inc_min_102_i_3_n_0 : STD_LOGIC;
  signal temp_cmp_three_inc_min_102_i_4_n_0 : STD_LOGIC;
  signal temp_cmp_three_inc_min_102_i_5_n_0 : STD_LOGIC;
  signal temp_cmp_three_inc_min_102_i_6_n_0 : STD_LOGIC;
  signal temp_cmp_three_inc_min_102_i_7_n_0 : STD_LOGIC;
  signal temp_cmp_three_inc_min_102_i_8_n_0 : STD_LOGIC;
  signal temp_cmp_three_inc_min_102_i_9_n_0 : STD_LOGIC;
  signal temp_cmp_three_inc_min_102_reg_i_1_n_3 : STD_LOGIC;
  signal temp_cmp_three_inc_min_102_reg_i_2_n_0 : STD_LOGIC;
  signal temp_cmp_three_inc_min_102_reg_i_2_n_1 : STD_LOGIC;
  signal temp_cmp_three_inc_min_102_reg_i_2_n_2 : STD_LOGIC;
  signal temp_cmp_three_inc_min_102_reg_i_2_n_3 : STD_LOGIC;
  signal temp_cmp_two_dec_max_101 : STD_LOGIC;
  signal temp_cmp_two_dec_max_102 : STD_LOGIC;
  signal temp_cmp_two_dec_max_102_i_10_n_0 : STD_LOGIC;
  signal temp_cmp_two_dec_max_102_i_11_n_0 : STD_LOGIC;
  signal temp_cmp_two_dec_max_102_i_12_n_0 : STD_LOGIC;
  signal temp_cmp_two_dec_max_102_i_13_n_0 : STD_LOGIC;
  signal temp_cmp_two_dec_max_102_i_14_n_0 : STD_LOGIC;
  signal temp_cmp_two_dec_max_102_i_3_n_0 : STD_LOGIC;
  signal temp_cmp_two_dec_max_102_i_4_n_0 : STD_LOGIC;
  signal temp_cmp_two_dec_max_102_i_5_n_0 : STD_LOGIC;
  signal temp_cmp_two_dec_max_102_i_6_n_0 : STD_LOGIC;
  signal temp_cmp_two_dec_max_102_i_7_n_0 : STD_LOGIC;
  signal temp_cmp_two_dec_max_102_i_8_n_0 : STD_LOGIC;
  signal temp_cmp_two_dec_max_102_i_9_n_0 : STD_LOGIC;
  signal temp_cmp_two_dec_max_102_reg_i_1_n_3 : STD_LOGIC;
  signal temp_cmp_two_dec_max_102_reg_i_2_n_0 : STD_LOGIC;
  signal temp_cmp_two_dec_max_102_reg_i_2_n_1 : STD_LOGIC;
  signal temp_cmp_two_dec_max_102_reg_i_2_n_2 : STD_LOGIC;
  signal temp_cmp_two_dec_max_102_reg_i_2_n_3 : STD_LOGIC;
  signal temp_cmp_two_dec_min_101 : STD_LOGIC;
  signal temp_cmp_two_dec_min_102 : STD_LOGIC;
  signal temp_cmp_two_dec_min_102_i_10_n_0 : STD_LOGIC;
  signal temp_cmp_two_dec_min_102_i_11_n_0 : STD_LOGIC;
  signal temp_cmp_two_dec_min_102_i_12_n_0 : STD_LOGIC;
  signal temp_cmp_two_dec_min_102_i_13_n_0 : STD_LOGIC;
  signal temp_cmp_two_dec_min_102_i_14_n_0 : STD_LOGIC;
  signal temp_cmp_two_dec_min_102_i_3_n_0 : STD_LOGIC;
  signal temp_cmp_two_dec_min_102_i_4_n_0 : STD_LOGIC;
  signal temp_cmp_two_dec_min_102_i_5_n_0 : STD_LOGIC;
  signal temp_cmp_two_dec_min_102_i_6_n_0 : STD_LOGIC;
  signal temp_cmp_two_dec_min_102_i_7_n_0 : STD_LOGIC;
  signal temp_cmp_two_dec_min_102_i_8_n_0 : STD_LOGIC;
  signal temp_cmp_two_dec_min_102_i_9_n_0 : STD_LOGIC;
  signal temp_cmp_two_dec_min_102_reg_i_1_n_3 : STD_LOGIC;
  signal temp_cmp_two_dec_min_102_reg_i_2_n_0 : STD_LOGIC;
  signal temp_cmp_two_dec_min_102_reg_i_2_n_1 : STD_LOGIC;
  signal temp_cmp_two_dec_min_102_reg_i_2_n_2 : STD_LOGIC;
  signal temp_cmp_two_dec_min_102_reg_i_2_n_3 : STD_LOGIC;
  signal temp_cmp_two_inc_max_101 : STD_LOGIC;
  signal temp_cmp_two_inc_max_102 : STD_LOGIC;
  signal temp_cmp_two_inc_max_102_i_10_n_0 : STD_LOGIC;
  signal temp_cmp_two_inc_max_102_i_11_n_0 : STD_LOGIC;
  signal temp_cmp_two_inc_max_102_i_12_n_0 : STD_LOGIC;
  signal temp_cmp_two_inc_max_102_i_13_n_0 : STD_LOGIC;
  signal temp_cmp_two_inc_max_102_i_14_n_0 : STD_LOGIC;
  signal temp_cmp_two_inc_max_102_i_3_n_0 : STD_LOGIC;
  signal temp_cmp_two_inc_max_102_i_4_n_0 : STD_LOGIC;
  signal temp_cmp_two_inc_max_102_i_5_n_0 : STD_LOGIC;
  signal temp_cmp_two_inc_max_102_i_6_n_0 : STD_LOGIC;
  signal temp_cmp_two_inc_max_102_i_7_n_0 : STD_LOGIC;
  signal temp_cmp_two_inc_max_102_i_8_n_0 : STD_LOGIC;
  signal temp_cmp_two_inc_max_102_i_9_n_0 : STD_LOGIC;
  signal temp_cmp_two_inc_max_102_reg_i_1_n_3 : STD_LOGIC;
  signal temp_cmp_two_inc_max_102_reg_i_2_n_0 : STD_LOGIC;
  signal temp_cmp_two_inc_max_102_reg_i_2_n_1 : STD_LOGIC;
  signal temp_cmp_two_inc_max_102_reg_i_2_n_2 : STD_LOGIC;
  signal temp_cmp_two_inc_max_102_reg_i_2_n_3 : STD_LOGIC;
  signal temp_cmp_two_inc_min_101 : STD_LOGIC;
  signal temp_cmp_two_inc_min_102 : STD_LOGIC;
  signal temp_cmp_two_inc_min_102_i_10_n_0 : STD_LOGIC;
  signal temp_cmp_two_inc_min_102_i_11_n_0 : STD_LOGIC;
  signal temp_cmp_two_inc_min_102_i_12_n_0 : STD_LOGIC;
  signal temp_cmp_two_inc_min_102_i_13_n_0 : STD_LOGIC;
  signal temp_cmp_two_inc_min_102_i_14_n_0 : STD_LOGIC;
  signal temp_cmp_two_inc_min_102_i_3_n_0 : STD_LOGIC;
  signal temp_cmp_two_inc_min_102_i_4_n_0 : STD_LOGIC;
  signal temp_cmp_two_inc_min_102_i_5_n_0 : STD_LOGIC;
  signal temp_cmp_two_inc_min_102_i_6_n_0 : STD_LOGIC;
  signal temp_cmp_two_inc_min_102_i_7_n_0 : STD_LOGIC;
  signal temp_cmp_two_inc_min_102_i_8_n_0 : STD_LOGIC;
  signal temp_cmp_two_inc_min_102_i_9_n_0 : STD_LOGIC;
  signal temp_cmp_two_inc_min_102_reg_i_1_n_3 : STD_LOGIC;
  signal temp_cmp_two_inc_min_102_reg_i_2_n_0 : STD_LOGIC;
  signal temp_cmp_two_inc_min_102_reg_i_2_n_1 : STD_LOGIC;
  signal temp_cmp_two_inc_min_102_reg_i_2_n_2 : STD_LOGIC;
  signal temp_cmp_two_inc_min_102_reg_i_2_n_3 : STD_LOGIC;
  signal tempmon_init_complete : STD_LOGIC;
  signal tempmon_pi_f_dec : STD_LOGIC;
  signal \^tempmon_pi_f_inc\ : STD_LOGIC;
  signal tempmon_sample_en_101 : STD_LOGIC;
  signal tempmon_sample_en_102 : STD_LOGIC;
  signal tempmon_state : STD_LOGIC_VECTOR ( 10 downto 0 );
  signal \tempmon_state[10]_i_10_n_0\ : STD_LOGIC;
  signal \tempmon_state[10]_i_11_n_0\ : STD_LOGIC;
  signal \tempmon_state[10]_i_12_n_0\ : STD_LOGIC;
  signal \tempmon_state[10]_i_13_n_0\ : STD_LOGIC;
  signal \tempmon_state[10]_i_14_n_0\ : STD_LOGIC;
  signal \tempmon_state[10]_i_15_n_0\ : STD_LOGIC;
  signal \tempmon_state[10]_i_1_n_0\ : STD_LOGIC;
  signal \tempmon_state[10]_i_3_n_0\ : STD_LOGIC;
  signal \tempmon_state[10]_i_4_n_0\ : STD_LOGIC;
  signal \tempmon_state[10]_i_5_n_0\ : STD_LOGIC;
  signal \tempmon_state[10]_i_6_n_0\ : STD_LOGIC;
  signal \tempmon_state[10]_i_7_n_0\ : STD_LOGIC;
  signal \tempmon_state[10]_i_8_n_0\ : STD_LOGIC;
  signal \tempmon_state[10]_i_9_n_0\ : STD_LOGIC;
  signal \tempmon_state[6]_i_2_n_0\ : STD_LOGIC;
  signal tempmon_state_init : STD_LOGIC;
  signal tempmon_state_nxt : STD_LOGIC_VECTOR ( 10 downto 0 );
  signal three_dec_max_limit : STD_LOGIC_VECTOR ( 11 downto 0 );
  signal \three_dec_max_limit[0]_i_1_n_0\ : STD_LOGIC;
  signal \three_dec_max_limit[10]_i_1_n_0\ : STD_LOGIC;
  signal \three_dec_max_limit[11]_i_1_n_0\ : STD_LOGIC;
  signal \three_dec_max_limit[11]_i_3_n_0\ : STD_LOGIC;
  signal \three_dec_max_limit[1]_i_1_n_0\ : STD_LOGIC;
  signal \three_dec_max_limit[2]_i_1_n_0\ : STD_LOGIC;
  signal \three_dec_max_limit[3]_i_1_n_0\ : STD_LOGIC;
  signal \three_dec_max_limit[4]_i_1_n_0\ : STD_LOGIC;
  signal \three_dec_max_limit[5]_i_1_n_0\ : STD_LOGIC;
  signal \three_dec_max_limit[6]_i_1_n_0\ : STD_LOGIC;
  signal \three_dec_max_limit[7]_i_1_n_0\ : STD_LOGIC;
  signal \three_dec_max_limit[8]_i_1_n_0\ : STD_LOGIC;
  signal \three_dec_max_limit[8]_i_3_n_0\ : STD_LOGIC;
  signal \three_dec_max_limit[8]_i_4_n_0\ : STD_LOGIC;
  signal \three_dec_max_limit[9]_i_1_n_0\ : STD_LOGIC;
  signal \three_dec_max_limit_reg[11]_i_2_n_2\ : STD_LOGIC;
  signal \three_dec_max_limit_reg[11]_i_2_n_3\ : STD_LOGIC;
  signal \three_dec_max_limit_reg[11]_i_2_n_5\ : STD_LOGIC;
  signal \three_dec_max_limit_reg[11]_i_2_n_6\ : STD_LOGIC;
  signal \three_dec_max_limit_reg[11]_i_2_n_7\ : STD_LOGIC;
  signal \three_dec_max_limit_reg[4]_i_2_n_0\ : STD_LOGIC;
  signal \three_dec_max_limit_reg[4]_i_2_n_1\ : STD_LOGIC;
  signal \three_dec_max_limit_reg[4]_i_2_n_2\ : STD_LOGIC;
  signal \three_dec_max_limit_reg[4]_i_2_n_3\ : STD_LOGIC;
  signal \three_dec_max_limit_reg[4]_i_2_n_4\ : STD_LOGIC;
  signal \three_dec_max_limit_reg[4]_i_2_n_5\ : STD_LOGIC;
  signal \three_dec_max_limit_reg[4]_i_2_n_6\ : STD_LOGIC;
  signal \three_dec_max_limit_reg[8]_i_2_n_0\ : STD_LOGIC;
  signal \three_dec_max_limit_reg[8]_i_2_n_1\ : STD_LOGIC;
  signal \three_dec_max_limit_reg[8]_i_2_n_2\ : STD_LOGIC;
  signal \three_dec_max_limit_reg[8]_i_2_n_3\ : STD_LOGIC;
  signal \three_dec_max_limit_reg[8]_i_2_n_4\ : STD_LOGIC;
  signal \three_dec_max_limit_reg[8]_i_2_n_5\ : STD_LOGIC;
  signal \three_dec_max_limit_reg[8]_i_2_n_6\ : STD_LOGIC;
  signal \three_dec_max_limit_reg[8]_i_2_n_7\ : STD_LOGIC;
  signal three_dec_min_limit : STD_LOGIC_VECTOR ( 11 downto 0 );
  signal \three_dec_min_limit[11]_i_2_n_0\ : STD_LOGIC;
  signal \three_dec_min_limit[11]_i_3_n_0\ : STD_LOGIC;
  signal \three_dec_min_limit[5]_i_2_n_0\ : STD_LOGIC;
  signal \three_dec_min_limit[5]_i_3_n_0\ : STD_LOGIC;
  signal \three_dec_min_limit[5]_i_4_n_0\ : STD_LOGIC;
  signal \three_dec_min_limit[9]_i_2_n_0\ : STD_LOGIC;
  signal \three_dec_min_limit[9]_i_3_n_0\ : STD_LOGIC;
  signal \three_dec_min_limit[9]_i_4_n_0\ : STD_LOGIC;
  signal \three_dec_min_limit[9]_i_5_n_0\ : STD_LOGIC;
  signal three_dec_min_limit_nxt : STD_LOGIC_VECTOR ( 11 downto 2 );
  signal \three_dec_min_limit_reg[11]_i_1_n_3\ : STD_LOGIC;
  signal \three_dec_min_limit_reg[5]_i_1_n_0\ : STD_LOGIC;
  signal \three_dec_min_limit_reg[5]_i_1_n_1\ : STD_LOGIC;
  signal \three_dec_min_limit_reg[5]_i_1_n_2\ : STD_LOGIC;
  signal \three_dec_min_limit_reg[5]_i_1_n_3\ : STD_LOGIC;
  signal \three_dec_min_limit_reg[9]_i_1_n_0\ : STD_LOGIC;
  signal \three_dec_min_limit_reg[9]_i_1_n_1\ : STD_LOGIC;
  signal \three_dec_min_limit_reg[9]_i_1_n_2\ : STD_LOGIC;
  signal \three_dec_min_limit_reg[9]_i_1_n_3\ : STD_LOGIC;
  signal three_inc_max_limit : STD_LOGIC_VECTOR ( 11 downto 2 );
  signal \three_inc_max_limit[11]_i_2_n_0\ : STD_LOGIC;
  signal \three_inc_max_limit[11]_i_3_n_0\ : STD_LOGIC;
  signal \three_inc_max_limit[4]_i_2_n_0\ : STD_LOGIC;
  signal \three_inc_max_limit[4]_i_3_n_0\ : STD_LOGIC;
  signal \three_inc_max_limit[8]_i_2_n_0\ : STD_LOGIC;
  signal \three_inc_max_limit[8]_i_3_n_0\ : STD_LOGIC;
  signal \three_inc_max_limit[8]_i_4_n_0\ : STD_LOGIC;
  signal three_inc_max_limit_nxt : STD_LOGIC_VECTOR ( 11 downto 2 );
  signal \three_inc_max_limit_reg[11]_i_1_n_2\ : STD_LOGIC;
  signal \three_inc_max_limit_reg[11]_i_1_n_3\ : STD_LOGIC;
  signal \three_inc_max_limit_reg[4]_i_1_n_0\ : STD_LOGIC;
  signal \three_inc_max_limit_reg[4]_i_1_n_1\ : STD_LOGIC;
  signal \three_inc_max_limit_reg[4]_i_1_n_2\ : STD_LOGIC;
  signal \three_inc_max_limit_reg[4]_i_1_n_3\ : STD_LOGIC;
  signal \three_inc_max_limit_reg[4]_i_1_n_7\ : STD_LOGIC;
  signal \three_inc_max_limit_reg[8]_i_1_n_0\ : STD_LOGIC;
  signal \three_inc_max_limit_reg[8]_i_1_n_1\ : STD_LOGIC;
  signal \three_inc_max_limit_reg[8]_i_1_n_2\ : STD_LOGIC;
  signal \three_inc_max_limit_reg[8]_i_1_n_3\ : STD_LOGIC;
  signal three_inc_min_limit : STD_LOGIC_VECTOR ( 11 downto 2 );
  signal \three_inc_min_limit[11]_i_2_n_0\ : STD_LOGIC;
  signal \three_inc_min_limit[11]_i_3_n_0\ : STD_LOGIC;
  signal \three_inc_min_limit[5]_i_2_n_0\ : STD_LOGIC;
  signal \three_inc_min_limit[5]_i_3_n_0\ : STD_LOGIC;
  signal \three_inc_min_limit[5]_i_4_n_0\ : STD_LOGIC;
  signal \three_inc_min_limit[9]_i_2_n_0\ : STD_LOGIC;
  signal \three_inc_min_limit[9]_i_3_n_0\ : STD_LOGIC;
  signal \three_inc_min_limit[9]_i_4_n_0\ : STD_LOGIC;
  signal \three_inc_min_limit[9]_i_5_n_0\ : STD_LOGIC;
  signal three_inc_min_limit_nxt : STD_LOGIC_VECTOR ( 11 downto 2 );
  signal \three_inc_min_limit_reg[11]_i_1_n_3\ : STD_LOGIC;
  signal \three_inc_min_limit_reg[5]_i_1_n_0\ : STD_LOGIC;
  signal \three_inc_min_limit_reg[5]_i_1_n_1\ : STD_LOGIC;
  signal \three_inc_min_limit_reg[5]_i_1_n_2\ : STD_LOGIC;
  signal \three_inc_min_limit_reg[5]_i_1_n_3\ : STD_LOGIC;
  signal \three_inc_min_limit_reg[9]_i_1_n_0\ : STD_LOGIC;
  signal \three_inc_min_limit_reg[9]_i_1_n_1\ : STD_LOGIC;
  signal \three_inc_min_limit_reg[9]_i_1_n_2\ : STD_LOGIC;
  signal \three_inc_min_limit_reg[9]_i_1_n_3\ : STD_LOGIC;
  signal two_dec_max_limit : STD_LOGIC_VECTOR ( 11 downto 0 );
  signal \two_dec_max_limit[0]_i_1_n_0\ : STD_LOGIC;
  signal \two_dec_max_limit[11]_i_2_n_0\ : STD_LOGIC;
  signal \two_dec_max_limit[4]_i_2_n_0\ : STD_LOGIC;
  signal \two_dec_max_limit[4]_i_3_n_0\ : STD_LOGIC;
  signal \two_dec_max_limit[8]_i_2_n_0\ : STD_LOGIC;
  signal two_dec_max_limit_nxt : STD_LOGIC_VECTOR ( 11 downto 1 );
  signal \two_dec_max_limit_reg[11]_i_1_n_2\ : STD_LOGIC;
  signal \two_dec_max_limit_reg[11]_i_1_n_3\ : STD_LOGIC;
  signal \two_dec_max_limit_reg[4]_i_1_n_0\ : STD_LOGIC;
  signal \two_dec_max_limit_reg[4]_i_1_n_1\ : STD_LOGIC;
  signal \two_dec_max_limit_reg[4]_i_1_n_2\ : STD_LOGIC;
  signal \two_dec_max_limit_reg[4]_i_1_n_3\ : STD_LOGIC;
  signal \two_dec_max_limit_reg[8]_i_1_n_0\ : STD_LOGIC;
  signal \two_dec_max_limit_reg[8]_i_1_n_1\ : STD_LOGIC;
  signal \two_dec_max_limit_reg[8]_i_1_n_2\ : STD_LOGIC;
  signal \two_dec_max_limit_reg[8]_i_1_n_3\ : STD_LOGIC;
  signal two_dec_min_limit : STD_LOGIC_VECTOR ( 11 downto 2 );
  signal \two_dec_min_limit[11]_i_2_n_0\ : STD_LOGIC;
  signal \two_dec_min_limit[11]_i_3_n_0\ : STD_LOGIC;
  signal \two_dec_min_limit[5]_i_2_n_0\ : STD_LOGIC;
  signal \two_dec_min_limit[5]_i_3_n_0\ : STD_LOGIC;
  signal \two_dec_min_limit[5]_i_4_n_0\ : STD_LOGIC;
  signal \two_dec_min_limit[9]_i_2_n_0\ : STD_LOGIC;
  signal \two_dec_min_limit[9]_i_3_n_0\ : STD_LOGIC;
  signal \two_dec_min_limit[9]_i_4_n_0\ : STD_LOGIC;
  signal \two_dec_min_limit[9]_i_5_n_0\ : STD_LOGIC;
  signal two_dec_min_limit_nxt : STD_LOGIC_VECTOR ( 11 downto 2 );
  signal \two_dec_min_limit_reg[11]_i_1_n_3\ : STD_LOGIC;
  signal \two_dec_min_limit_reg[5]_i_1_n_0\ : STD_LOGIC;
  signal \two_dec_min_limit_reg[5]_i_1_n_1\ : STD_LOGIC;
  signal \two_dec_min_limit_reg[5]_i_1_n_2\ : STD_LOGIC;
  signal \two_dec_min_limit_reg[5]_i_1_n_3\ : STD_LOGIC;
  signal \two_dec_min_limit_reg[9]_i_1_n_0\ : STD_LOGIC;
  signal \two_dec_min_limit_reg[9]_i_1_n_1\ : STD_LOGIC;
  signal \two_dec_min_limit_reg[9]_i_1_n_2\ : STD_LOGIC;
  signal \two_dec_min_limit_reg[9]_i_1_n_3\ : STD_LOGIC;
  signal two_inc_max_limit : STD_LOGIC_VECTOR ( 11 downto 1 );
  signal \two_inc_max_limit[11]_i_2_n_0\ : STD_LOGIC;
  signal \two_inc_max_limit[11]_i_3_n_0\ : STD_LOGIC;
  signal \two_inc_max_limit[11]_i_4_n_0\ : STD_LOGIC;
  signal \two_inc_max_limit[1]_i_1_n_0\ : STD_LOGIC;
  signal \two_inc_max_limit[4]_i_2_n_0\ : STD_LOGIC;
  signal \two_inc_max_limit[4]_i_3_n_0\ : STD_LOGIC;
  signal \two_inc_max_limit[4]_i_4_n_0\ : STD_LOGIC;
  signal \two_inc_max_limit[8]_i_2_n_0\ : STD_LOGIC;
  signal two_inc_max_limit_nxt : STD_LOGIC_VECTOR ( 11 downto 2 );
  signal \two_inc_max_limit_reg[11]_i_1_n_2\ : STD_LOGIC;
  signal \two_inc_max_limit_reg[11]_i_1_n_3\ : STD_LOGIC;
  signal \two_inc_max_limit_reg[4]_i_1_n_0\ : STD_LOGIC;
  signal \two_inc_max_limit_reg[4]_i_1_n_1\ : STD_LOGIC;
  signal \two_inc_max_limit_reg[4]_i_1_n_2\ : STD_LOGIC;
  signal \two_inc_max_limit_reg[4]_i_1_n_3\ : STD_LOGIC;
  signal \two_inc_max_limit_reg[8]_i_1_n_0\ : STD_LOGIC;
  signal \two_inc_max_limit_reg[8]_i_1_n_1\ : STD_LOGIC;
  signal \two_inc_max_limit_reg[8]_i_1_n_2\ : STD_LOGIC;
  signal \two_inc_max_limit_reg[8]_i_1_n_3\ : STD_LOGIC;
  signal two_inc_min_limit : STD_LOGIC_VECTOR ( 11 downto 1 );
  signal \two_inc_min_limit[11]_i_2_n_0\ : STD_LOGIC;
  signal \two_inc_min_limit[11]_i_3_n_0\ : STD_LOGIC;
  signal \two_inc_min_limit[5]_i_2_n_0\ : STD_LOGIC;
  signal \two_inc_min_limit[5]_i_3_n_0\ : STD_LOGIC;
  signal \two_inc_min_limit[5]_i_4_n_0\ : STD_LOGIC;
  signal \two_inc_min_limit[9]_i_2_n_0\ : STD_LOGIC;
  signal \two_inc_min_limit[9]_i_3_n_0\ : STD_LOGIC;
  signal \two_inc_min_limit[9]_i_4_n_0\ : STD_LOGIC;
  signal \two_inc_min_limit[9]_i_5_n_0\ : STD_LOGIC;
  signal two_inc_min_limit_nxt : STD_LOGIC_VECTOR ( 11 downto 2 );
  signal \two_inc_min_limit_reg[11]_i_1_n_3\ : STD_LOGIC;
  signal \two_inc_min_limit_reg[5]_i_1_n_0\ : STD_LOGIC;
  signal \two_inc_min_limit_reg[5]_i_1_n_1\ : STD_LOGIC;
  signal \two_inc_min_limit_reg[5]_i_1_n_2\ : STD_LOGIC;
  signal \two_inc_min_limit_reg[5]_i_1_n_3\ : STD_LOGIC;
  signal \two_inc_min_limit_reg[9]_i_1_n_0\ : STD_LOGIC;
  signal \two_inc_min_limit_reg[9]_i_1_n_1\ : STD_LOGIC;
  signal \two_inc_min_limit_reg[9]_i_1_n_2\ : STD_LOGIC;
  signal \two_inc_min_limit_reg[9]_i_1_n_3\ : STD_LOGIC;
  signal \update_temp_101__0\ : STD_LOGIC;
  signal update_temp_102 : STD_LOGIC;
  signal \NLW_four_dec_min_limit_reg[11]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
  signal \NLW_four_dec_min_limit_reg[11]_i_1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
  signal \NLW_four_inc_max_limit_reg[11]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
  signal \NLW_four_inc_max_limit_reg[11]_i_1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
  signal \NLW_neutral_max_limit_reg[11]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
  signal \NLW_neutral_max_limit_reg[11]_i_1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
  signal \NLW_neutral_max_limit_reg[4]_i_1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \NLW_neutral_min_limit_reg[11]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
  signal \NLW_neutral_min_limit_reg[11]_i_1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
  signal \NLW_one_dec_max_limit_reg[11]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
  signal \NLW_one_dec_max_limit_reg[11]_i_1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
  signal \NLW_one_dec_max_limit_reg[4]_i_1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \NLW_one_dec_min_limit_reg[11]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
  signal \NLW_one_dec_min_limit_reg[11]_i_1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
  signal \NLW_one_inc_max_limit_reg[11]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
  signal \NLW_one_inc_max_limit_reg[11]_i_1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
  signal \NLW_one_inc_max_limit_reg[4]_i_1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \NLW_one_inc_min_limit_reg[11]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
  signal \NLW_one_inc_min_limit_reg[11]_i_1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
  signal NLW_temp_cmp_four_dec_min_102_reg_i_1_CO_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 2 );
  signal NLW_temp_cmp_four_dec_min_102_reg_i_1_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal NLW_temp_cmp_four_dec_min_102_reg_i_2_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal NLW_temp_cmp_four_inc_max_102_reg_i_1_CO_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 2 );
  signal NLW_temp_cmp_four_inc_max_102_reg_i_1_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal NLW_temp_cmp_four_inc_max_102_reg_i_2_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal NLW_temp_cmp_neutral_max_102_reg_i_1_CO_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 2 );
  signal NLW_temp_cmp_neutral_max_102_reg_i_1_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal NLW_temp_cmp_neutral_max_102_reg_i_2_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal NLW_temp_cmp_neutral_min_102_reg_i_1_CO_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 2 );
  signal NLW_temp_cmp_neutral_min_102_reg_i_1_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal NLW_temp_cmp_neutral_min_102_reg_i_2_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal NLW_temp_cmp_one_dec_max_102_reg_i_1_CO_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 2 );
  signal NLW_temp_cmp_one_dec_max_102_reg_i_1_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal NLW_temp_cmp_one_dec_max_102_reg_i_2_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal NLW_temp_cmp_one_dec_min_102_reg_i_1_CO_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 2 );
  signal NLW_temp_cmp_one_dec_min_102_reg_i_1_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal NLW_temp_cmp_one_dec_min_102_reg_i_2_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal NLW_temp_cmp_one_inc_max_102_reg_i_1_CO_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 2 );
  signal NLW_temp_cmp_one_inc_max_102_reg_i_1_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal NLW_temp_cmp_one_inc_max_102_reg_i_2_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal NLW_temp_cmp_one_inc_min_102_reg_i_1_CO_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 2 );
  signal NLW_temp_cmp_one_inc_min_102_reg_i_1_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal NLW_temp_cmp_one_inc_min_102_reg_i_2_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal NLW_temp_cmp_three_dec_max_102_reg_i_1_CO_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 2 );
  signal NLW_temp_cmp_three_dec_max_102_reg_i_1_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal NLW_temp_cmp_three_dec_max_102_reg_i_2_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal NLW_temp_cmp_three_dec_min_102_reg_i_1_CO_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 2 );
  signal NLW_temp_cmp_three_dec_min_102_reg_i_1_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal NLW_temp_cmp_three_dec_min_102_reg_i_2_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal NLW_temp_cmp_three_inc_max_102_reg_i_1_CO_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 2 );
  signal NLW_temp_cmp_three_inc_max_102_reg_i_1_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal NLW_temp_cmp_three_inc_max_102_reg_i_2_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal NLW_temp_cmp_three_inc_min_102_reg_i_1_CO_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 2 );
  signal NLW_temp_cmp_three_inc_min_102_reg_i_1_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal NLW_temp_cmp_three_inc_min_102_reg_i_2_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal NLW_temp_cmp_two_dec_max_102_reg_i_1_CO_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 2 );
  signal NLW_temp_cmp_two_dec_max_102_reg_i_1_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal NLW_temp_cmp_two_dec_max_102_reg_i_2_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal NLW_temp_cmp_two_dec_min_102_reg_i_1_CO_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 2 );
  signal NLW_temp_cmp_two_dec_min_102_reg_i_1_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal NLW_temp_cmp_two_dec_min_102_reg_i_2_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal NLW_temp_cmp_two_inc_max_102_reg_i_1_CO_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 2 );
  signal NLW_temp_cmp_two_inc_max_102_reg_i_1_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal NLW_temp_cmp_two_inc_max_102_reg_i_2_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal NLW_temp_cmp_two_inc_min_102_reg_i_1_CO_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 2 );
  signal NLW_temp_cmp_two_inc_min_102_reg_i_1_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal NLW_temp_cmp_two_inc_min_102_reg_i_2_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \NLW_three_dec_max_limit_reg[11]_i_2_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 to 2 );
  signal \NLW_three_dec_max_limit_reg[11]_i_2_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
  signal \NLW_three_dec_max_limit_reg[4]_i_2_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \NLW_three_dec_min_limit_reg[11]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
  signal \NLW_three_dec_min_limit_reg[11]_i_1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
  signal \NLW_three_inc_max_limit_reg[11]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
  signal \NLW_three_inc_max_limit_reg[11]_i_1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
  signal \NLW_three_inc_min_limit_reg[11]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
  signal \NLW_three_inc_min_limit_reg[11]_i_1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
  signal \NLW_two_dec_max_limit_reg[11]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
  signal \NLW_two_dec_max_limit_reg[11]_i_1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
  signal \NLW_two_dec_max_limit_reg[4]_i_1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \NLW_two_dec_min_limit_reg[11]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
  signal \NLW_two_dec_min_limit_reg[11]_i_1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
  signal \NLW_two_inc_max_limit_reg[11]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
  signal \NLW_two_inc_max_limit_reg[11]_i_1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
  signal \NLW_two_inc_max_limit_reg[4]_i_1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \NLW_two_inc_min_limit_reg[11]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
  signal \NLW_two_inc_min_limit_reg[11]_i_1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \calib_sel[4]_i_1\ : label is "soft_lutpair238";
  attribute SOFT_HLUTNM of \calib_zero_inputs[0]_i_2\ : label is "soft_lutpair236";
  attribute SOFT_HLUTNM of \calib_zero_inputs[2]_i_2\ : label is "soft_lutpair236";
  attribute SOFT_HLUTNM of \device_temp_init[11]_i_3\ : label is "soft_lutpair239";
  attribute SOFT_HLUTNM of pi_f_inc_i_7 : label is "soft_lutpair234";
  attribute SOFT_HLUTNM of tempmon_pi_f_en_r_i_1 : label is "soft_lutpair238";
  attribute SOFT_HLUTNM of \tempmon_state[10]_i_10\ : label is "soft_lutpair233";
  attribute SOFT_HLUTNM of \tempmon_state[10]_i_11\ : label is "soft_lutpair233";
  attribute SOFT_HLUTNM of \tempmon_state[10]_i_15\ : label is "soft_lutpair237";
  attribute SOFT_HLUTNM of \tempmon_state[10]_i_4\ : label is "soft_lutpair235";
  attribute SOFT_HLUTNM of \tempmon_state[10]_i_7\ : label is "soft_lutpair234";
  attribute SOFT_HLUTNM of \tempmon_state[1]_i_1\ : label is "soft_lutpair235";
  attribute SOFT_HLUTNM of \tempmon_state[6]_i_2\ : label is "soft_lutpair239";
  attribute SOFT_HLUTNM of \tempmon_state[9]_i_1\ : label is "soft_lutpair237";
  attribute FSM_ENCODED_STATES : string;
  attribute FSM_ENCODED_STATES of \tempmon_state_reg[0]\ : label is "IDLE:00000000001,ONE_INC:00000100000,FOUR_DEC:10000000000,THREE_INC:00000001000,TWO_DEC:00100000000,FOUR_INC:00000000100,ONE_DEC:00010000000,INIT:00000000010,NEUTRAL:00001000000,TWO_INC:00000010000,THREE_DEC:01000000000";
  attribute FSM_ENCODED_STATES of \tempmon_state_reg[10]\ : label is "IDLE:00000000001,ONE_INC:00000100000,FOUR_DEC:10000000000,THREE_INC:00000001000,TWO_DEC:00100000000,FOUR_INC:00000000100,ONE_DEC:00010000000,INIT:00000000010,NEUTRAL:00001000000,TWO_INC:00000010000,THREE_DEC:01000000000";
  attribute FSM_ENCODED_STATES of \tempmon_state_reg[1]\ : label is "IDLE:00000000001,ONE_INC:00000100000,FOUR_DEC:10000000000,THREE_INC:00000001000,TWO_DEC:00100000000,FOUR_INC:00000000100,ONE_DEC:00010000000,INIT:00000000010,NEUTRAL:00001000000,TWO_INC:00000010000,THREE_DEC:01000000000";
  attribute FSM_ENCODED_STATES of \tempmon_state_reg[2]\ : label is "IDLE:00000000001,ONE_INC:00000100000,FOUR_DEC:10000000000,THREE_INC:00000001000,TWO_DEC:00100000000,FOUR_INC:00000000100,ONE_DEC:00010000000,INIT:00000000010,NEUTRAL:00001000000,TWO_INC:00000010000,THREE_DEC:01000000000";
  attribute FSM_ENCODED_STATES of \tempmon_state_reg[3]\ : label is "IDLE:00000000001,ONE_INC:00000100000,FOUR_DEC:10000000000,THREE_INC:00000001000,TWO_DEC:00100000000,FOUR_INC:00000000100,ONE_DEC:00010000000,INIT:00000000010,NEUTRAL:00001000000,TWO_INC:00000010000,THREE_DEC:01000000000";
  attribute FSM_ENCODED_STATES of \tempmon_state_reg[4]\ : label is "IDLE:00000000001,ONE_INC:00000100000,FOUR_DEC:10000000000,THREE_INC:00000001000,TWO_DEC:00100000000,FOUR_INC:00000000100,ONE_DEC:00010000000,INIT:00000000010,NEUTRAL:00001000000,TWO_INC:00000010000,THREE_DEC:01000000000";
  attribute FSM_ENCODED_STATES of \tempmon_state_reg[5]\ : label is "IDLE:00000000001,ONE_INC:00000100000,FOUR_DEC:10000000000,THREE_INC:00000001000,TWO_DEC:00100000000,FOUR_INC:00000000100,ONE_DEC:00010000000,INIT:00000000010,NEUTRAL:00001000000,TWO_INC:00000010000,THREE_DEC:01000000000";
  attribute FSM_ENCODED_STATES of \tempmon_state_reg[6]\ : label is "IDLE:00000000001,ONE_INC:00000100000,FOUR_DEC:10000000000,THREE_INC:00000001000,TWO_DEC:00100000000,FOUR_INC:00000000100,ONE_DEC:00010000000,INIT:00000000010,NEUTRAL:00001000000,TWO_INC:00000010000,THREE_DEC:01000000000";
  attribute FSM_ENCODED_STATES of \tempmon_state_reg[7]\ : label is "IDLE:00000000001,ONE_INC:00000100000,FOUR_DEC:10000000000,THREE_INC:00000001000,TWO_DEC:00100000000,FOUR_INC:00000000100,ONE_DEC:00010000000,INIT:00000000010,NEUTRAL:00001000000,TWO_INC:00000010000,THREE_DEC:01000000000";
  attribute FSM_ENCODED_STATES of \tempmon_state_reg[8]\ : label is "IDLE:00000000001,ONE_INC:00000100000,FOUR_DEC:10000000000,THREE_INC:00000001000,TWO_DEC:00100000000,FOUR_INC:00000000100,ONE_DEC:00010000000,INIT:00000000010,NEUTRAL:00001000000,TWO_INC:00000010000,THREE_DEC:01000000000";
  attribute FSM_ENCODED_STATES of \tempmon_state_reg[9]\ : label is "IDLE:00000000001,ONE_INC:00000100000,FOUR_DEC:10000000000,THREE_INC:00000001000,TWO_DEC:00100000000,FOUR_INC:00000000100,ONE_DEC:00010000000,INIT:00000000010,NEUTRAL:00001000000,TWO_INC:00000010000,THREE_DEC:01000000000";
  attribute SOFT_HLUTNM of \three_dec_max_limit[0]_i_1\ : label is "soft_lutpair243";
  attribute SOFT_HLUTNM of \three_dec_max_limit[10]_i_1\ : label is "soft_lutpair240";
  attribute SOFT_HLUTNM of \three_dec_max_limit[11]_i_1\ : label is "soft_lutpair241";
  attribute SOFT_HLUTNM of \three_dec_max_limit[1]_i_1\ : label is "soft_lutpair245";
  attribute SOFT_HLUTNM of \three_dec_max_limit[2]_i_1\ : label is "soft_lutpair245";
  attribute SOFT_HLUTNM of \three_dec_max_limit[3]_i_1\ : label is "soft_lutpair244";
  attribute SOFT_HLUTNM of \three_dec_max_limit[4]_i_1\ : label is "soft_lutpair242";
  attribute SOFT_HLUTNM of \three_dec_max_limit[5]_i_1\ : label is "soft_lutpair241";
  attribute SOFT_HLUTNM of \three_dec_max_limit[6]_i_1\ : label is "soft_lutpair243";
  attribute SOFT_HLUTNM of \three_dec_max_limit[7]_i_1\ : label is "soft_lutpair240";
  attribute SOFT_HLUTNM of \three_dec_max_limit[8]_i_1\ : label is "soft_lutpair244";
  attribute SOFT_HLUTNM of \three_dec_max_limit[9]_i_1\ : label is "soft_lutpair242";
begin
  pi_f_inc_reg_0 <= \^pi_f_inc_reg_0\;
  tempmon_pi_f_inc <= \^tempmon_pi_f_inc\;
\calib_sel[4]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"ABAA"
    )
        port map (
      I0 => \calib_sel_reg[0]\,
      I1 => \^tempmon_pi_f_inc\,
      I2 => tempmon_pi_f_dec,
      I3 => calib_complete,
      O => \^pi_f_inc_reg_0\
    );
\calib_zero_inputs[0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"BFBAAAAAAAAAAAAA"
    )
        port map (
      I0 => \^pi_f_inc_reg_0\,
      I1 => \calib_zero_inputs_reg[2]\,
      I2 => \calib_sel1__1\,
      I3 => \calib_zero_inputs[0]_i_2_n_0\,
      I4 => dqs_po_dec_done,
      I5 => pi_fine_dly_dec_done,
      O => D(0)
    );
\calib_zero_inputs[0]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000001"
    )
        port map (
      I0 => calib_in_common,
      I1 => Q(1),
      I2 => Q(0),
      I3 => tempmon_pi_f_dec,
      I4 => \^tempmon_pi_f_inc\,
      O => \calib_zero_inputs[0]_i_2_n_0\
    );
\calib_zero_inputs[1]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAABAAAAAAAA"
    )
        port map (
      I0 => \^pi_f_inc_reg_0\,
      I1 => calib_in_common,
      I2 => \^tempmon_pi_f_inc\,
      I3 => tempmon_pi_f_dec,
      I4 => \calib_sel1__1\,
      I5 => cmd_delay_start0,
      O => D(1)
    );
\calib_zero_inputs[2]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"BFBAAAAAAAAAAAAA"
    )
        port map (
      I0 => \^pi_f_inc_reg_0\,
      I1 => \calib_zero_inputs_reg[2]\,
      I2 => \calib_sel1__1\,
      I3 => \calib_zero_inputs[2]_i_2_n_0\,
      I4 => dqs_po_dec_done,
      I5 => pi_fine_dly_dec_done,
      O => D(2)
    );
\calib_zero_inputs[2]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000000E"
    )
        port map (
      I0 => Q(1),
      I1 => Q(0),
      I2 => calib_in_common,
      I3 => tempmon_pi_f_dec,
      I4 => \^tempmon_pi_f_inc\,
      O => \calib_zero_inputs[2]_i_2_n_0\
    );
\device_temp_101_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => pi_f_dec_reg_0,
      CE => '1',
      D => \device_temp_101_reg[11]_0\(0),
      Q => device_temp_101(0),
      R => \device_temp_101_reg[0]_0\
    );
\device_temp_101_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => pi_f_dec_reg_0,
      CE => '1',
      D => \device_temp_101_reg[11]_0\(10),
      Q => device_temp_101(10),
      R => \device_temp_101_reg[0]_0\
    );
\device_temp_101_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => pi_f_dec_reg_0,
      CE => '1',
      D => \device_temp_101_reg[11]_0\(11),
      Q => device_temp_101(11),
      R => \device_temp_101_reg[0]_0\
    );
\device_temp_101_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => pi_f_dec_reg_0,
      CE => '1',
      D => \device_temp_101_reg[11]_0\(1),
      Q => device_temp_101(1),
      R => \device_temp_101_reg[0]_0\
    );
\device_temp_101_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => pi_f_dec_reg_0,
      CE => '1',
      D => \device_temp_101_reg[11]_0\(2),
      Q => device_temp_101(2),
      R => \device_temp_101_reg[0]_0\
    );
\device_temp_101_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => pi_f_dec_reg_0,
      CE => '1',
      D => \device_temp_101_reg[11]_0\(3),
      Q => device_temp_101(3),
      R => \device_temp_101_reg[0]_0\
    );
\device_temp_101_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => pi_f_dec_reg_0,
      CE => '1',
      D => \device_temp_101_reg[11]_0\(4),
      Q => device_temp_101(4),
      R => \device_temp_101_reg[0]_0\
    );
\device_temp_101_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => pi_f_dec_reg_0,
      CE => '1',
      D => \device_temp_101_reg[11]_0\(5),
      Q => device_temp_101(5),
      R => \device_temp_101_reg[0]_0\
    );
\device_temp_101_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => pi_f_dec_reg_0,
      CE => '1',
      D => \device_temp_101_reg[11]_0\(6),
      Q => device_temp_101(6),
      R => \device_temp_101_reg[0]_0\
    );
\device_temp_101_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => pi_f_dec_reg_0,
      CE => '1',
      D => \device_temp_101_reg[11]_0\(7),
      Q => device_temp_101(7),
      R => \device_temp_101_reg[0]_0\
    );
\device_temp_101_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => pi_f_dec_reg_0,
      CE => '1',
      D => \device_temp_101_reg[11]_0\(8),
      Q => device_temp_101(8),
      R => \device_temp_101_reg[0]_0\
    );
\device_temp_101_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => pi_f_dec_reg_0,
      CE => '1',
      D => \device_temp_101_reg[11]_0\(9),
      Q => device_temp_101(9),
      R => \device_temp_101_reg[0]_0\
    );
\device_temp_init[11]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000001"
    )
        port map (
      I0 => tempmon_state(9),
      I1 => tempmon_state(7),
      I2 => tempmon_state(8),
      I3 => \device_temp_init[11]_i_2_n_0\,
      I4 => \device_temp_init[11]_i_3_n_0\,
      O => tempmon_state_init
    );
\device_temp_init[11]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFFD"
    )
        port map (
      I0 => tempmon_state(1),
      I1 => tempmon_state(2),
      I2 => tempmon_state(3),
      I3 => tempmon_state(10),
      O => \device_temp_init[11]_i_2_n_0\
    );
\device_temp_init[11]_i_3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFFE"
    )
        port map (
      I0 => tempmon_state(0),
      I1 => tempmon_state(4),
      I2 => tempmon_state(5),
      I3 => tempmon_state(6),
      O => \device_temp_init[11]_i_3_n_0\
    );
\device_temp_init_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => pi_f_dec_reg_0,
      CE => tempmon_state_init,
      D => device_temp_101(0),
      Q => device_temp_init(0),
      R => \device_temp_101_reg[0]_0\
    );
\device_temp_init_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => pi_f_dec_reg_0,
      CE => tempmon_state_init,
      D => device_temp_101(10),
      Q => device_temp_init(10),
      R => \device_temp_101_reg[0]_0\
    );
\device_temp_init_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => pi_f_dec_reg_0,
      CE => tempmon_state_init,
      D => device_temp_101(11),
      Q => device_temp_init(11),
      R => \device_temp_101_reg[0]_0\
    );
\device_temp_init_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => pi_f_dec_reg_0,
      CE => tempmon_state_init,
      D => device_temp_101(1),
      Q => device_temp_init(1),
      R => \device_temp_101_reg[0]_0\
    );
\device_temp_init_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => pi_f_dec_reg_0,
      CE => tempmon_state_init,
      D => device_temp_101(2),
      Q => device_temp_init(2),
      R => \device_temp_101_reg[0]_0\
    );
\device_temp_init_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => pi_f_dec_reg_0,
      CE => tempmon_state_init,
      D => device_temp_101(3),
      Q => device_temp_init(3),
      R => \device_temp_101_reg[0]_0\
    );
\device_temp_init_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => pi_f_dec_reg_0,
      CE => tempmon_state_init,
      D => device_temp_101(4),
      Q => device_temp_init(4),
      R => \device_temp_101_reg[0]_0\
    );
\device_temp_init_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => pi_f_dec_reg_0,
      CE => tempmon_state_init,
      D => device_temp_101(5),
      Q => device_temp_init(5),
      R => \device_temp_101_reg[0]_0\
    );
\device_temp_init_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => pi_f_dec_reg_0,
      CE => tempmon_state_init,
      D => device_temp_101(6),
      Q => device_temp_init(6),
      R => \device_temp_101_reg[0]_0\
    );
\device_temp_init_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => pi_f_dec_reg_0,
      CE => tempmon_state_init,
      D => device_temp_101(7),
      Q => device_temp_init(7),
      R => \device_temp_101_reg[0]_0\
    );
\device_temp_init_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => pi_f_dec_reg_0,
      CE => tempmon_state_init,
      D => device_temp_101(8),
      Q => device_temp_init(8),
      R => \device_temp_101_reg[0]_0\
    );
\device_temp_init_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => pi_f_dec_reg_0,
      CE => tempmon_state_init,
      D => device_temp_101(9),
      Q => device_temp_init(9),
      R => \device_temp_101_reg[0]_0\
    );
\four_dec_min_limit[11]_i_2\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => three_dec_max_limit(11),
      O => \four_dec_min_limit[11]_i_2_n_0\
    );
\four_dec_min_limit[11]_i_3\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => three_dec_max_limit(10),
      O => \four_dec_min_limit[11]_i_3_n_0\
    );
\four_dec_min_limit[5]_i_2\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => three_dec_max_limit(5),
      O => \four_dec_min_limit[5]_i_2_n_0\
    );
\four_dec_min_limit[5]_i_3\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => three_dec_max_limit(4),
      O => \four_dec_min_limit[5]_i_3_n_0\
    );
\four_dec_min_limit[5]_i_4\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => three_dec_max_limit(3),
      O => \four_dec_min_limit[5]_i_4_n_0\
    );
\four_dec_min_limit[9]_i_2\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => three_dec_max_limit(9),
      O => \four_dec_min_limit[9]_i_2_n_0\
    );
\four_dec_min_limit[9]_i_3\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => three_dec_max_limit(8),
      O => \four_dec_min_limit[9]_i_3_n_0\
    );
\four_dec_min_limit[9]_i_4\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => three_dec_max_limit(7),
      O => \four_dec_min_limit[9]_i_4_n_0\
    );
\four_dec_min_limit[9]_i_5\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => three_dec_max_limit(6),
      O => \four_dec_min_limit[9]_i_5_n_0\
    );
\four_dec_min_limit_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => pi_f_dec_reg_0,
      CE => '1',
      D => three_dec_max_limit(0),
      Q => four_dec_min_limit(0),
      R => \four_dec_min_limit_reg[0]_0\
    );
\four_dec_min_limit_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => pi_f_dec_reg_0,
      CE => '1',
      D => four_dec_min_limit_nxt(10),
      Q => four_dec_min_limit(10),
      R => \four_dec_min_limit_reg[0]_0\
    );
\four_dec_min_limit_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => pi_f_dec_reg_0,
      CE => '1',
      D => four_dec_min_limit_nxt(11),
      Q => four_dec_min_limit(11),
      R => \four_dec_min_limit_reg[0]_0\
    );
\four_dec_min_limit_reg[11]_i_1\: unisim.vcomponents.CARRY4
     port map (
      CI => \four_dec_min_limit_reg[9]_i_1_n_0\,
      CO(3 downto 1) => \NLW_four_dec_min_limit_reg[11]_i_1_CO_UNCONNECTED\(3 downto 1),
      CO(0) => \four_dec_min_limit_reg[11]_i_1_n_3\,
      CYINIT => '0',
      DI(3 downto 1) => B"000",
      DI(0) => three_dec_max_limit(10),
      O(3 downto 2) => \NLW_four_dec_min_limit_reg[11]_i_1_O_UNCONNECTED\(3 downto 2),
      O(1 downto 0) => four_dec_min_limit_nxt(11 downto 10),
      S(3 downto 2) => B"00",
      S(1) => \four_dec_min_limit[11]_i_2_n_0\,
      S(0) => \four_dec_min_limit[11]_i_3_n_0\
    );
\four_dec_min_limit_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => pi_f_dec_reg_0,
      CE => '1',
      D => three_dec_max_limit(1),
      Q => four_dec_min_limit(1),
      R => \four_dec_min_limit_reg[0]_0\
    );
\four_dec_min_limit_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => pi_f_dec_reg_0,
      CE => '1',
      D => four_dec_min_limit_nxt(2),
      Q => four_dec_min_limit(2),
      R => \four_dec_min_limit_reg[0]_0\
    );
\four_dec_min_limit_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => pi_f_dec_reg_0,
      CE => '1',
      D => four_dec_min_limit_nxt(3),
      Q => four_dec_min_limit(3),
      R => \four_dec_min_limit_reg[0]_0\
    );
\four_dec_min_limit_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => pi_f_dec_reg_0,
      CE => '1',
      D => four_dec_min_limit_nxt(4),
      Q => four_dec_min_limit(4),
      R => \four_dec_min_limit_reg[0]_0\
    );
\four_dec_min_limit_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => pi_f_dec_reg_0,
      CE => '1',
      D => four_dec_min_limit_nxt(5),
      Q => four_dec_min_limit(5),
      R => \four_dec_min_limit_reg[0]_0\
    );
\four_dec_min_limit_reg[5]_i_1\: unisim.vcomponents.CARRY4
     port map (
      CI => '0',
      CO(3) => \four_dec_min_limit_reg[5]_i_1_n_0\,
      CO(2) => \four_dec_min_limit_reg[5]_i_1_n_1\,
      CO(1) => \four_dec_min_limit_reg[5]_i_1_n_2\,
      CO(0) => \four_dec_min_limit_reg[5]_i_1_n_3\,
      CYINIT => '0',
      DI(3 downto 1) => three_dec_max_limit(5 downto 3),
      DI(0) => '0',
      O(3 downto 0) => four_dec_min_limit_nxt(5 downto 2),
      S(3) => \four_dec_min_limit[5]_i_2_n_0\,
      S(2) => \four_dec_min_limit[5]_i_3_n_0\,
      S(1) => \four_dec_min_limit[5]_i_4_n_0\,
      S(0) => three_dec_max_limit(2)
    );
\four_dec_min_limit_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => pi_f_dec_reg_0,
      CE => '1',
      D => four_dec_min_limit_nxt(6),
      Q => four_dec_min_limit(6),
      R => \four_dec_min_limit_reg[0]_0\
    );
\four_dec_min_limit_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => pi_f_dec_reg_0,
      CE => '1',
      D => four_dec_min_limit_nxt(7),
      Q => four_dec_min_limit(7),
      R => \four_dec_min_limit_reg[0]_0\
    );
\four_dec_min_limit_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => pi_f_dec_reg_0,
      CE => '1',
      D => four_dec_min_limit_nxt(8),
      Q => four_dec_min_limit(8),
      R => \four_dec_min_limit_reg[0]_0\
    );
\four_dec_min_limit_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => pi_f_dec_reg_0,
      CE => '1',
      D => four_dec_min_limit_nxt(9),
      Q => four_dec_min_limit(9),
      R => \four_dec_min_limit_reg[0]_0\
    );
\four_dec_min_limit_reg[9]_i_1\: unisim.vcomponents.CARRY4
     port map (
      CI => \four_dec_min_limit_reg[5]_i_1_n_0\,
      CO(3) => \four_dec_min_limit_reg[9]_i_1_n_0\,
      CO(2) => \four_dec_min_limit_reg[9]_i_1_n_1\,
      CO(1) => \four_dec_min_limit_reg[9]_i_1_n_2\,
      CO(0) => \four_dec_min_limit_reg[9]_i_1_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => three_dec_max_limit(9 downto 6),
      O(3 downto 0) => four_dec_min_limit_nxt(9 downto 6),
      S(3) => \four_dec_min_limit[9]_i_2_n_0\,
      S(2) => \four_dec_min_limit[9]_i_3_n_0\,
      S(1) => \four_dec_min_limit[9]_i_4_n_0\,
      S(0) => \four_dec_min_limit[9]_i_5_n_0\
    );
\four_inc_max_limit[11]_i_2\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => device_temp_init(11),
      O => \four_inc_max_limit[11]_i_2_n_0\
    );
\four_inc_max_limit[11]_i_3\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => device_temp_init(10),
      O => \four_inc_max_limit[11]_i_3_n_0\
    );
\four_inc_max_limit[4]_i_2\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => device_temp_init(4),
      O => \four_inc_max_limit[4]_i_2_n_0\
    );
\four_inc_max_limit[4]_i_3\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => device_temp_init(3),
      O => \four_inc_max_limit[4]_i_3_n_0\
    );
\four_inc_max_limit[4]_i_4\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => device_temp_init(2),
      O => \four_inc_max_limit[4]_i_4_n_0\
    );
\four_inc_max_limit[4]_i_5\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => device_temp_init(1),
      O => \four_inc_max_limit[4]_i_5_n_0\
    );
\four_inc_max_limit[8]_i_2\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => device_temp_init(7),
      O => \four_inc_max_limit[8]_i_2_n_0\
    );
\four_inc_max_limit[8]_i_3\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => device_temp_init(5),
      O => \four_inc_max_limit[8]_i_3_n_0\
    );
\four_inc_max_limit_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => pi_f_dec_reg_0,
      CE => '1',
      D => four_inc_max_limit_nxt(10),
      Q => four_inc_max_limit(10),
      R => \one_dec_max_limit_reg[2]_0\
    );
\four_inc_max_limit_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => pi_f_dec_reg_0,
      CE => '1',
      D => four_inc_max_limit_nxt(11),
      Q => four_inc_max_limit(11),
      R => \one_dec_max_limit_reg[2]_0\
    );
\four_inc_max_limit_reg[11]_i_1\: unisim.vcomponents.CARRY4
     port map (
      CI => \four_inc_max_limit_reg[8]_i_1_n_0\,
      CO(3 downto 2) => \NLW_four_inc_max_limit_reg[11]_i_1_CO_UNCONNECTED\(3 downto 2),
      CO(1) => \four_inc_max_limit_reg[11]_i_1_n_2\,
      CO(0) => \four_inc_max_limit_reg[11]_i_1_n_3\,
      CYINIT => '0',
      DI(3 downto 2) => B"00",
      DI(1) => device_temp_init(10),
      DI(0) => '0',
      O(3) => \NLW_four_inc_max_limit_reg[11]_i_1_O_UNCONNECTED\(3),
      O(2 downto 0) => four_inc_max_limit_nxt(11 downto 9),
      S(3) => '0',
      S(2) => \four_inc_max_limit[11]_i_2_n_0\,
      S(1) => \four_inc_max_limit[11]_i_3_n_0\,
      S(0) => device_temp_init(9)
    );
\four_inc_max_limit_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => pi_f_dec_reg_0,
      CE => '1',
      D => four_inc_max_limit_nxt(2),
      Q => four_inc_max_limit(2),
      R => \one_dec_max_limit_reg[2]_0\
    );
\four_inc_max_limit_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => pi_f_dec_reg_0,
      CE => '1',
      D => four_inc_max_limit_nxt(3),
      Q => four_inc_max_limit(3),
      R => \one_dec_max_limit_reg[2]_0\
    );
\four_inc_max_limit_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => pi_f_dec_reg_0,
      CE => '1',
      D => four_inc_max_limit_nxt(4),
      Q => four_inc_max_limit(4),
      R => \one_dec_max_limit_reg[2]_0\
    );
\four_inc_max_limit_reg[4]_i_1\: unisim.vcomponents.CARRY4
     port map (
      CI => '0',
      CO(3) => \four_inc_max_limit_reg[4]_i_1_n_0\,
      CO(2) => \four_inc_max_limit_reg[4]_i_1_n_1\,
      CO(1) => \four_inc_max_limit_reg[4]_i_1_n_2\,
      CO(0) => \four_inc_max_limit_reg[4]_i_1_n_3\,
      CYINIT => device_temp_init(0),
      DI(3 downto 0) => device_temp_init(4 downto 1),
      O(3 downto 1) => four_inc_max_limit_nxt(4 downto 2),
      O(0) => two_dec_max_limit_nxt(1),
      S(3) => \four_inc_max_limit[4]_i_2_n_0\,
      S(2) => \four_inc_max_limit[4]_i_3_n_0\,
      S(1) => \four_inc_max_limit[4]_i_4_n_0\,
      S(0) => \four_inc_max_limit[4]_i_5_n_0\
    );
\four_inc_max_limit_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => pi_f_dec_reg_0,
      CE => '1',
      D => four_inc_max_limit_nxt(5),
      Q => four_inc_max_limit(5),
      R => \one_dec_max_limit_reg[2]_0\
    );
\four_inc_max_limit_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => pi_f_dec_reg_0,
      CE => '1',
      D => four_inc_max_limit_nxt(6),
      Q => four_inc_max_limit(6),
      R => \one_dec_max_limit_reg[2]_0\
    );
\four_inc_max_limit_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => pi_f_dec_reg_0,
      CE => '1',
      D => four_inc_max_limit_nxt(7),
      Q => four_inc_max_limit(7),
      R => \one_dec_max_limit_reg[2]_0\
    );
\four_inc_max_limit_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => pi_f_dec_reg_0,
      CE => '1',
      D => four_inc_max_limit_nxt(8),
      Q => four_inc_max_limit(8),
      R => \one_dec_max_limit_reg[2]_0\
    );
\four_inc_max_limit_reg[8]_i_1\: unisim.vcomponents.CARRY4
     port map (
      CI => \four_inc_max_limit_reg[4]_i_1_n_0\,
      CO(3) => \four_inc_max_limit_reg[8]_i_1_n_0\,
      CO(2) => \four_inc_max_limit_reg[8]_i_1_n_1\,
      CO(1) => \four_inc_max_limit_reg[8]_i_1_n_2\,
      CO(0) => \four_inc_max_limit_reg[8]_i_1_n_3\,
      CYINIT => '0',
      DI(3) => '0',
      DI(2) => device_temp_init(7),
      DI(1) => '0',
      DI(0) => device_temp_init(5),
      O(3 downto 0) => four_inc_max_limit_nxt(8 downto 5),
      S(3) => device_temp_init(8),
      S(2) => \four_inc_max_limit[8]_i_2_n_0\,
      S(1) => device_temp_init(6),
      S(0) => \four_inc_max_limit[8]_i_3_n_0\
    );
\four_inc_max_limit_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => pi_f_dec_reg_0,
      CE => '1',
      D => four_inc_max_limit_nxt(9),
      Q => four_inc_max_limit(9),
      R => \one_dec_max_limit_reg[2]_0\
    );
\gen_byte_sel_div2.calib_in_common_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"A800000000000000"
    )
        port map (
      I0 => \gen_byte_sel_div2.calib_in_common_i_2_1\,
      I1 => \^tempmon_pi_f_inc\,
      I2 => tempmon_pi_f_dec,
      I3 => \gen_byte_sel_div2.calib_in_common_i_2_0\,
      I4 => \gen_byte_sel_div2.calib_in_common_i_3\,
      I5 => \gen_byte_sel_div2.calib_in_common_i_2\,
      O => calib_in_common4_out
    );
\gen_byte_sel_div2.calib_in_common_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFF7FFFFFFFFF"
    )
        port map (
      I0 => \gen_byte_sel_div2.calib_in_common_i_2\,
      I1 => \gen_byte_sel_div2.calib_in_common_i_3\,
      I2 => \gen_byte_sel_div2.calib_in_common_i_2_0\,
      I3 => \^tempmon_pi_f_inc\,
      I4 => tempmon_pi_f_dec,
      I5 => \gen_byte_sel_div2.calib_in_common_i_2_1\,
      O => rdlvl_stg1_done_int_reg
    );
\neutral_max_limit[4]_i_2\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => device_temp_init(4),
      O => \neutral_max_limit[4]_i_2_n_0\
    );
\neutral_max_limit[4]_i_3\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => device_temp_init(2),
      O => \neutral_max_limit[4]_i_3_n_0\
    );
\neutral_max_limit[4]_i_4\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => device_temp_init(1),
      O => \neutral_max_limit[4]_i_4_n_0\
    );
\neutral_max_limit[8]_i_2\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => device_temp_init(6),
      O => \neutral_max_limit[8]_i_2_n_0\
    );
\neutral_max_limit[8]_i_3\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => device_temp_init(5),
      O => \neutral_max_limit[8]_i_3_n_0\
    );
\neutral_max_limit_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => pi_f_dec_reg_0,
      CE => '1',
      D => neutral_max_limit_nxt(10),
      Q => neutral_max_limit(10),
      R => \neutral_max_limit_reg[11]_0\
    );
\neutral_max_limit_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => pi_f_dec_reg_0,
      CE => '1',
      D => neutral_max_limit_nxt(11),
      Q => neutral_max_limit(11),
      R => \neutral_max_limit_reg[11]_0\
    );
\neutral_max_limit_reg[11]_i_1\: unisim.vcomponents.CARRY4
     port map (
      CI => \neutral_max_limit_reg[8]_i_1_n_0\,
      CO(3 downto 2) => \NLW_neutral_max_limit_reg[11]_i_1_CO_UNCONNECTED\(3 downto 2),
      CO(1) => \neutral_max_limit_reg[11]_i_1_n_2\,
      CO(0) => \neutral_max_limit_reg[11]_i_1_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3) => \NLW_neutral_max_limit_reg[11]_i_1_O_UNCONNECTED\(3),
      O(2 downto 0) => neutral_max_limit_nxt(11 downto 9),
      S(3) => '0',
      S(2 downto 0) => device_temp_init(11 downto 9)
    );
\neutral_max_limit_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => pi_f_dec_reg_0,
      CE => '1',
      D => neutral_max_limit_nxt(2),
      Q => neutral_max_limit(2),
      R => \neutral_max_limit_reg[11]_0\
    );
\neutral_max_limit_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => pi_f_dec_reg_0,
      CE => '1',
      D => neutral_max_limit_nxt(3),
      Q => neutral_max_limit(3),
      R => \neutral_max_limit_reg[11]_0\
    );
\neutral_max_limit_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => pi_f_dec_reg_0,
      CE => '1',
      D => neutral_max_limit_nxt(4),
      Q => neutral_max_limit(4),
      R => \neutral_max_limit_reg[11]_0\
    );
\neutral_max_limit_reg[4]_i_1\: unisim.vcomponents.CARRY4
     port map (
      CI => '0',
      CO(3) => \neutral_max_limit_reg[4]_i_1_n_0\,
      CO(2) => \neutral_max_limit_reg[4]_i_1_n_1\,
      CO(1) => \neutral_max_limit_reg[4]_i_1_n_2\,
      CO(0) => \neutral_max_limit_reg[4]_i_1_n_3\,
      CYINIT => device_temp_init(0),
      DI(3) => device_temp_init(4),
      DI(2) => '0',
      DI(1 downto 0) => device_temp_init(2 downto 1),
      O(3 downto 1) => neutral_max_limit_nxt(4 downto 2),
      O(0) => \NLW_neutral_max_limit_reg[4]_i_1_O_UNCONNECTED\(0),
      S(3) => \neutral_max_limit[4]_i_2_n_0\,
      S(2) => device_temp_init(3),
      S(1) => \neutral_max_limit[4]_i_3_n_0\,
      S(0) => \neutral_max_limit[4]_i_4_n_0\
    );
\neutral_max_limit_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => pi_f_dec_reg_0,
      CE => '1',
      D => neutral_max_limit_nxt(5),
      Q => neutral_max_limit(5),
      R => \neutral_max_limit_reg[11]_0\
    );
\neutral_max_limit_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => pi_f_dec_reg_0,
      CE => '1',
      D => neutral_max_limit_nxt(6),
      Q => neutral_max_limit(6),
      R => \neutral_max_limit_reg[11]_0\
    );
\neutral_max_limit_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => pi_f_dec_reg_0,
      CE => '1',
      D => neutral_max_limit_nxt(7),
      Q => neutral_max_limit(7),
      R => \neutral_max_limit_reg[11]_0\
    );
\neutral_max_limit_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => pi_f_dec_reg_0,
      CE => '1',
      D => neutral_max_limit_nxt(8),
      Q => neutral_max_limit(8),
      R => \neutral_max_limit_reg[11]_0\
    );
\neutral_max_limit_reg[8]_i_1\: unisim.vcomponents.CARRY4
     port map (
      CI => \neutral_max_limit_reg[4]_i_1_n_0\,
      CO(3) => \neutral_max_limit_reg[8]_i_1_n_0\,
      CO(2) => \neutral_max_limit_reg[8]_i_1_n_1\,
      CO(1) => \neutral_max_limit_reg[8]_i_1_n_2\,
      CO(0) => \neutral_max_limit_reg[8]_i_1_n_3\,
      CYINIT => '0',
      DI(3 downto 2) => B"00",
      DI(1 downto 0) => device_temp_init(6 downto 5),
      O(3 downto 0) => neutral_max_limit_nxt(8 downto 5),
      S(3 downto 2) => device_temp_init(8 downto 7),
      S(1) => \neutral_max_limit[8]_i_2_n_0\,
      S(0) => \neutral_max_limit[8]_i_3_n_0\
    );
\neutral_max_limit_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => pi_f_dec_reg_0,
      CE => '1',
      D => neutral_max_limit_nxt(9),
      Q => neutral_max_limit(9),
      R => \neutral_max_limit_reg[11]_0\
    );
\neutral_min_limit[11]_i_2\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => one_inc_max_limit(11),
      O => \neutral_min_limit[11]_i_2_n_0\
    );
\neutral_min_limit[11]_i_3\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => one_inc_max_limit(10),
      O => \neutral_min_limit[11]_i_3_n_0\
    );
\neutral_min_limit[5]_i_2\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => one_inc_max_limit(5),
      O => \neutral_min_limit[5]_i_2_n_0\
    );
\neutral_min_limit[5]_i_3\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => one_inc_max_limit(4),
      O => \neutral_min_limit[5]_i_3_n_0\
    );
\neutral_min_limit[5]_i_4\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => one_inc_max_limit(3),
      O => \neutral_min_limit[5]_i_4_n_0\
    );
\neutral_min_limit[9]_i_2\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => one_inc_max_limit(9),
      O => \neutral_min_limit[9]_i_2_n_0\
    );
\neutral_min_limit[9]_i_3\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => one_inc_max_limit(8),
      O => \neutral_min_limit[9]_i_3_n_0\
    );
\neutral_min_limit[9]_i_4\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => one_inc_max_limit(7),
      O => \neutral_min_limit[9]_i_4_n_0\
    );
\neutral_min_limit[9]_i_5\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => one_inc_max_limit(6),
      O => \neutral_min_limit[9]_i_5_n_0\
    );
\neutral_min_limit_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => pi_f_dec_reg_0,
      CE => '1',
      D => neutral_min_limit_nxt(10),
      Q => neutral_min_limit(10),
      R => \four_dec_min_limit_reg[0]_0\
    );
\neutral_min_limit_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => pi_f_dec_reg_0,
      CE => '1',
      D => neutral_min_limit_nxt(11),
      Q => neutral_min_limit(11),
      R => \four_dec_min_limit_reg[0]_0\
    );
\neutral_min_limit_reg[11]_i_1\: unisim.vcomponents.CARRY4
     port map (
      CI => \neutral_min_limit_reg[9]_i_1_n_0\,
      CO(3 downto 1) => \NLW_neutral_min_limit_reg[11]_i_1_CO_UNCONNECTED\(3 downto 1),
      CO(0) => \neutral_min_limit_reg[11]_i_1_n_3\,
      CYINIT => '0',
      DI(3 downto 1) => B"000",
      DI(0) => one_inc_max_limit(10),
      O(3 downto 2) => \NLW_neutral_min_limit_reg[11]_i_1_O_UNCONNECTED\(3 downto 2),
      O(1 downto 0) => neutral_min_limit_nxt(11 downto 10),
      S(3 downto 2) => B"00",
      S(1) => \neutral_min_limit[11]_i_2_n_0\,
      S(0) => \neutral_min_limit[11]_i_3_n_0\
    );
\neutral_min_limit_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => pi_f_dec_reg_0,
      CE => '1',
      D => neutral_min_limit_nxt(2),
      Q => neutral_min_limit(2),
      R => \four_dec_min_limit_reg[0]_0\
    );
\neutral_min_limit_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => pi_f_dec_reg_0,
      CE => '1',
      D => neutral_min_limit_nxt(3),
      Q => neutral_min_limit(3),
      R => \four_dec_min_limit_reg[0]_0\
    );
\neutral_min_limit_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => pi_f_dec_reg_0,
      CE => '1',
      D => neutral_min_limit_nxt(4),
      Q => neutral_min_limit(4),
      R => \four_dec_min_limit_reg[0]_0\
    );
\neutral_min_limit_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => pi_f_dec_reg_0,
      CE => '1',
      D => neutral_min_limit_nxt(5),
      Q => neutral_min_limit(5),
      R => \four_dec_min_limit_reg[0]_0\
    );
\neutral_min_limit_reg[5]_i_1\: unisim.vcomponents.CARRY4
     port map (
      CI => '0',
      CO(3) => \neutral_min_limit_reg[5]_i_1_n_0\,
      CO(2) => \neutral_min_limit_reg[5]_i_1_n_1\,
      CO(1) => \neutral_min_limit_reg[5]_i_1_n_2\,
      CO(0) => \neutral_min_limit_reg[5]_i_1_n_3\,
      CYINIT => '0',
      DI(3 downto 1) => one_inc_max_limit(5 downto 3),
      DI(0) => '0',
      O(3 downto 0) => neutral_min_limit_nxt(5 downto 2),
      S(3) => \neutral_min_limit[5]_i_2_n_0\,
      S(2) => \neutral_min_limit[5]_i_3_n_0\,
      S(1) => \neutral_min_limit[5]_i_4_n_0\,
      S(0) => one_inc_max_limit(2)
    );
\neutral_min_limit_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => pi_f_dec_reg_0,
      CE => '1',
      D => neutral_min_limit_nxt(6),
      Q => neutral_min_limit(6),
      R => \four_dec_min_limit_reg[0]_0\
    );
\neutral_min_limit_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => pi_f_dec_reg_0,
      CE => '1',
      D => neutral_min_limit_nxt(7),
      Q => neutral_min_limit(7),
      R => \four_dec_min_limit_reg[0]_0\
    );
\neutral_min_limit_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => pi_f_dec_reg_0,
      CE => '1',
      D => neutral_min_limit_nxt(8),
      Q => neutral_min_limit(8),
      R => \four_dec_min_limit_reg[0]_0\
    );
\neutral_min_limit_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => pi_f_dec_reg_0,
      CE => '1',
      D => neutral_min_limit_nxt(9),
      Q => neutral_min_limit(9),
      R => \four_dec_min_limit_reg[0]_0\
    );
\neutral_min_limit_reg[9]_i_1\: unisim.vcomponents.CARRY4
     port map (
      CI => \neutral_min_limit_reg[5]_i_1_n_0\,
      CO(3) => \neutral_min_limit_reg[9]_i_1_n_0\,
      CO(2) => \neutral_min_limit_reg[9]_i_1_n_1\,
      CO(1) => \neutral_min_limit_reg[9]_i_1_n_2\,
      CO(0) => \neutral_min_limit_reg[9]_i_1_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => one_inc_max_limit(9 downto 6),
      O(3 downto 0) => neutral_min_limit_nxt(9 downto 6),
      S(3) => \neutral_min_limit[9]_i_2_n_0\,
      S(2) => \neutral_min_limit[9]_i_3_n_0\,
      S(1) => \neutral_min_limit[9]_i_4_n_0\,
      S(0) => \neutral_min_limit[9]_i_5_n_0\
    );
\one_dec_max_limit[4]_i_2\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => device_temp_init(2),
      O => \one_dec_max_limit[4]_i_2_n_0\
    );
\one_dec_max_limit[8]_i_2\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => device_temp_init(8),
      O => \one_dec_max_limit[8]_i_2_n_0\
    );
\one_dec_max_limit[8]_i_3\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => device_temp_init(6),
      O => \one_dec_max_limit[8]_i_3_n_0\
    );
\one_dec_max_limit[8]_i_4\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => device_temp_init(5),
      O => \one_dec_max_limit[8]_i_4_n_0\
    );
\one_dec_max_limit_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => pi_f_dec_reg_0,
      CE => '1',
      D => one_dec_max_limit_nxt(10),
      Q => one_dec_max_limit(10),
      R => \one_dec_max_limit_reg[2]_0\
    );
\one_dec_max_limit_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => pi_f_dec_reg_0,
      CE => '1',
      D => one_dec_max_limit_nxt(11),
      Q => one_dec_max_limit(11),
      R => \one_dec_max_limit_reg[2]_0\
    );
\one_dec_max_limit_reg[11]_i_1\: unisim.vcomponents.CARRY4
     port map (
      CI => \one_dec_max_limit_reg[8]_i_1_n_0\,
      CO(3 downto 2) => \NLW_one_dec_max_limit_reg[11]_i_1_CO_UNCONNECTED\(3 downto 2),
      CO(1) => \one_dec_max_limit_reg[11]_i_1_n_2\,
      CO(0) => \one_dec_max_limit_reg[11]_i_1_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3) => \NLW_one_dec_max_limit_reg[11]_i_1_O_UNCONNECTED\(3),
      O(2 downto 0) => one_dec_max_limit_nxt(11 downto 9),
      S(3) => '0',
      S(2 downto 0) => device_temp_init(11 downto 9)
    );
\one_dec_max_limit_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => pi_f_dec_reg_0,
      CE => '1',
      D => one_dec_max_limit_nxt(2),
      Q => one_dec_max_limit(2),
      R => \one_dec_max_limit_reg[2]_0\
    );
\one_dec_max_limit_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => pi_f_dec_reg_0,
      CE => '1',
      D => one_dec_max_limit_nxt(3),
      Q => one_dec_max_limit(3),
      R => \one_dec_max_limit_reg[2]_0\
    );
\one_dec_max_limit_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => pi_f_dec_reg_0,
      CE => '1',
      D => one_dec_max_limit_nxt(4),
      Q => one_dec_max_limit(4),
      R => \one_dec_max_limit_reg[2]_0\
    );
\one_dec_max_limit_reg[4]_i_1\: unisim.vcomponents.CARRY4
     port map (
      CI => '0',
      CO(3) => \one_dec_max_limit_reg[4]_i_1_n_0\,
      CO(2) => \one_dec_max_limit_reg[4]_i_1_n_1\,
      CO(1) => \one_dec_max_limit_reg[4]_i_1_n_2\,
      CO(0) => \one_dec_max_limit_reg[4]_i_1_n_3\,
      CYINIT => device_temp_init(0),
      DI(3 downto 2) => B"00",
      DI(1) => device_temp_init(2),
      DI(0) => '0',
      O(3 downto 1) => one_dec_max_limit_nxt(4 downto 2),
      O(0) => \NLW_one_dec_max_limit_reg[4]_i_1_O_UNCONNECTED\(0),
      S(3 downto 2) => device_temp_init(4 downto 3),
      S(1) => \one_dec_max_limit[4]_i_2_n_0\,
      S(0) => device_temp_init(1)
    );
\one_dec_max_limit_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => pi_f_dec_reg_0,
      CE => '1',
      D => one_dec_max_limit_nxt(5),
      Q => one_dec_max_limit(5),
      R => \one_dec_max_limit_reg[2]_0\
    );
\one_dec_max_limit_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => pi_f_dec_reg_0,
      CE => '1',
      D => one_dec_max_limit_nxt(6),
      Q => one_dec_max_limit(6),
      R => \one_dec_max_limit_reg[2]_0\
    );
\one_dec_max_limit_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => pi_f_dec_reg_0,
      CE => '1',
      D => one_dec_max_limit_nxt(7),
      Q => one_dec_max_limit(7),
      R => \one_dec_max_limit_reg[2]_0\
    );
\one_dec_max_limit_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => pi_f_dec_reg_0,
      CE => '1',
      D => one_dec_max_limit_nxt(8),
      Q => one_dec_max_limit(8),
      R => \one_dec_max_limit_reg[2]_0\
    );
\one_dec_max_limit_reg[8]_i_1\: unisim.vcomponents.CARRY4
     port map (
      CI => \one_dec_max_limit_reg[4]_i_1_n_0\,
      CO(3) => \one_dec_max_limit_reg[8]_i_1_n_0\,
      CO(2) => \one_dec_max_limit_reg[8]_i_1_n_1\,
      CO(1) => \one_dec_max_limit_reg[8]_i_1_n_2\,
      CO(0) => \one_dec_max_limit_reg[8]_i_1_n_3\,
      CYINIT => '0',
      DI(3) => device_temp_init(8),
      DI(2) => '0',
      DI(1 downto 0) => device_temp_init(6 downto 5),
      O(3 downto 0) => one_dec_max_limit_nxt(8 downto 5),
      S(3) => \one_dec_max_limit[8]_i_2_n_0\,
      S(2) => device_temp_init(7),
      S(1) => \one_dec_max_limit[8]_i_3_n_0\,
      S(0) => \one_dec_max_limit[8]_i_4_n_0\
    );
\one_dec_max_limit_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => pi_f_dec_reg_0,
      CE => '1',
      D => one_dec_max_limit_nxt(9),
      Q => one_dec_max_limit(9),
      R => \one_dec_max_limit_reg[2]_0\
    );
\one_dec_min_limit[11]_i_2\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => neutral_max_limit(11),
      O => \one_dec_min_limit[11]_i_2_n_0\
    );
\one_dec_min_limit[11]_i_3\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => neutral_max_limit(10),
      O => \one_dec_min_limit[11]_i_3_n_0\
    );
\one_dec_min_limit[5]_i_2\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => neutral_max_limit(5),
      O => \one_dec_min_limit[5]_i_2_n_0\
    );
\one_dec_min_limit[5]_i_3\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => neutral_max_limit(4),
      O => \one_dec_min_limit[5]_i_3_n_0\
    );
\one_dec_min_limit[5]_i_4\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => neutral_max_limit(3),
      O => \one_dec_min_limit[5]_i_4_n_0\
    );
\one_dec_min_limit[9]_i_2\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => neutral_max_limit(9),
      O => \one_dec_min_limit[9]_i_2_n_0\
    );
\one_dec_min_limit[9]_i_3\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => neutral_max_limit(8),
      O => \one_dec_min_limit[9]_i_3_n_0\
    );
\one_dec_min_limit[9]_i_4\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => neutral_max_limit(7),
      O => \one_dec_min_limit[9]_i_4_n_0\
    );
\one_dec_min_limit[9]_i_5\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => neutral_max_limit(6),
      O => \one_dec_min_limit[9]_i_5_n_0\
    );
\one_dec_min_limit_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => pi_f_dec_reg_0,
      CE => '1',
      D => one_dec_min_limit_nxt(10),
      Q => one_dec_min_limit(10),
      R => \one_dec_min_limit_reg[11]_0\
    );
\one_dec_min_limit_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => pi_f_dec_reg_0,
      CE => '1',
      D => one_dec_min_limit_nxt(11),
      Q => one_dec_min_limit(11),
      R => \one_dec_min_limit_reg[11]_0\
    );
\one_dec_min_limit_reg[11]_i_1\: unisim.vcomponents.CARRY4
     port map (
      CI => \one_dec_min_limit_reg[9]_i_1_n_0\,
      CO(3 downto 1) => \NLW_one_dec_min_limit_reg[11]_i_1_CO_UNCONNECTED\(3 downto 1),
      CO(0) => \one_dec_min_limit_reg[11]_i_1_n_3\,
      CYINIT => '0',
      DI(3 downto 1) => B"000",
      DI(0) => neutral_max_limit(10),
      O(3 downto 2) => \NLW_one_dec_min_limit_reg[11]_i_1_O_UNCONNECTED\(3 downto 2),
      O(1 downto 0) => one_dec_min_limit_nxt(11 downto 10),
      S(3 downto 2) => B"00",
      S(1) => \one_dec_min_limit[11]_i_2_n_0\,
      S(0) => \one_dec_min_limit[11]_i_3_n_0\
    );
\one_dec_min_limit_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => pi_f_dec_reg_0,
      CE => '1',
      D => one_dec_min_limit_nxt(2),
      Q => one_dec_min_limit(2),
      R => \one_dec_min_limit_reg[11]_0\
    );
\one_dec_min_limit_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => pi_f_dec_reg_0,
      CE => '1',
      D => one_dec_min_limit_nxt(3),
      Q => one_dec_min_limit(3),
      R => \one_dec_min_limit_reg[11]_0\
    );
\one_dec_min_limit_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => pi_f_dec_reg_0,
      CE => '1',
      D => one_dec_min_limit_nxt(4),
      Q => one_dec_min_limit(4),
      R => \one_dec_min_limit_reg[11]_0\
    );
\one_dec_min_limit_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => pi_f_dec_reg_0,
      CE => '1',
      D => one_dec_min_limit_nxt(5),
      Q => one_dec_min_limit(5),
      R => \one_dec_min_limit_reg[11]_0\
    );
\one_dec_min_limit_reg[5]_i_1\: unisim.vcomponents.CARRY4
     port map (
      CI => '0',
      CO(3) => \one_dec_min_limit_reg[5]_i_1_n_0\,
      CO(2) => \one_dec_min_limit_reg[5]_i_1_n_1\,
      CO(1) => \one_dec_min_limit_reg[5]_i_1_n_2\,
      CO(0) => \one_dec_min_limit_reg[5]_i_1_n_3\,
      CYINIT => '0',
      DI(3 downto 1) => neutral_max_limit(5 downto 3),
      DI(0) => '0',
      O(3 downto 0) => one_dec_min_limit_nxt(5 downto 2),
      S(3) => \one_dec_min_limit[5]_i_2_n_0\,
      S(2) => \one_dec_min_limit[5]_i_3_n_0\,
      S(1) => \one_dec_min_limit[5]_i_4_n_0\,
      S(0) => neutral_max_limit(2)
    );
\one_dec_min_limit_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => pi_f_dec_reg_0,
      CE => '1',
      D => one_dec_min_limit_nxt(6),
      Q => one_dec_min_limit(6),
      R => \one_dec_min_limit_reg[11]_0\
    );
\one_dec_min_limit_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => pi_f_dec_reg_0,
      CE => '1',
      D => one_dec_min_limit_nxt(7),
      Q => one_dec_min_limit(7),
      R => \one_dec_min_limit_reg[11]_0\
    );
\one_dec_min_limit_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => pi_f_dec_reg_0,
      CE => '1',
      D => one_dec_min_limit_nxt(8),
      Q => one_dec_min_limit(8),
      R => \one_dec_min_limit_reg[11]_0\
    );
\one_dec_min_limit_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => pi_f_dec_reg_0,
      CE => '1',
      D => one_dec_min_limit_nxt(9),
      Q => one_dec_min_limit(9),
      R => \one_dec_min_limit_reg[11]_0\
    );
\one_dec_min_limit_reg[9]_i_1\: unisim.vcomponents.CARRY4
     port map (
      CI => \one_dec_min_limit_reg[5]_i_1_n_0\,
      CO(3) => \one_dec_min_limit_reg[9]_i_1_n_0\,
      CO(2) => \one_dec_min_limit_reg[9]_i_1_n_1\,
      CO(1) => \one_dec_min_limit_reg[9]_i_1_n_2\,
      CO(0) => \one_dec_min_limit_reg[9]_i_1_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => neutral_max_limit(9 downto 6),
      O(3 downto 0) => one_dec_min_limit_nxt(9 downto 6),
      S(3) => \one_dec_min_limit[9]_i_2_n_0\,
      S(2) => \one_dec_min_limit[9]_i_3_n_0\,
      S(1) => \one_dec_min_limit[9]_i_4_n_0\,
      S(0) => \one_dec_min_limit[9]_i_5_n_0\
    );
\one_inc_max_limit[11]_i_2\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => device_temp_init(11),
      O => \one_inc_max_limit[11]_i_2_n_0\
    );
\one_inc_max_limit[11]_i_3\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => device_temp_init(10),
      O => \one_inc_max_limit[11]_i_3_n_0\
    );
\one_inc_max_limit[11]_i_4\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => device_temp_init(9),
      O => \one_inc_max_limit[11]_i_4_n_0\
    );
\one_inc_max_limit[1]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => device_temp_init(0),
      I1 => device_temp_init(1),
      O => one_inc_max_limit_nxt(1)
    );
\one_inc_max_limit[4]_i_2\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => device_temp_init(3),
      O => \one_inc_max_limit[4]_i_2_n_0\
    );
\one_inc_max_limit[8]_i_2\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => device_temp_init(8),
      O => \one_inc_max_limit[8]_i_2_n_0\
    );
\one_inc_max_limit[8]_i_3\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => device_temp_init(7),
      O => \one_inc_max_limit[8]_i_3_n_0\
    );
\one_inc_max_limit_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => pi_f_dec_reg_0,
      CE => '1',
      D => one_inc_max_limit_nxt(10),
      Q => one_inc_max_limit(10),
      R => \one_dec_max_limit_reg[2]_0\
    );
\one_inc_max_limit_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => pi_f_dec_reg_0,
      CE => '1',
      D => one_inc_max_limit_nxt(11),
      Q => one_inc_max_limit(11),
      R => \one_dec_max_limit_reg[2]_0\
    );
\one_inc_max_limit_reg[11]_i_1\: unisim.vcomponents.CARRY4
     port map (
      CI => \one_inc_max_limit_reg[8]_i_1_n_0\,
      CO(3 downto 2) => \NLW_one_inc_max_limit_reg[11]_i_1_CO_UNCONNECTED\(3 downto 2),
      CO(1) => \one_inc_max_limit_reg[11]_i_1_n_2\,
      CO(0) => \one_inc_max_limit_reg[11]_i_1_n_3\,
      CYINIT => '0',
      DI(3 downto 2) => B"00",
      DI(1 downto 0) => device_temp_init(10 downto 9),
      O(3) => \NLW_one_inc_max_limit_reg[11]_i_1_O_UNCONNECTED\(3),
      O(2 downto 0) => one_inc_max_limit_nxt(11 downto 9),
      S(3) => '0',
      S(2) => \one_inc_max_limit[11]_i_2_n_0\,
      S(1) => \one_inc_max_limit[11]_i_3_n_0\,
      S(0) => \one_inc_max_limit[11]_i_4_n_0\
    );
\one_inc_max_limit_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => pi_f_dec_reg_0,
      CE => '1',
      D => one_inc_max_limit_nxt(1),
      Q => one_inc_max_limit(1),
      R => \one_dec_max_limit_reg[2]_0\
    );
\one_inc_max_limit_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => pi_f_dec_reg_0,
      CE => '1',
      D => one_inc_max_limit_nxt(2),
      Q => one_inc_max_limit(2),
      R => \one_dec_max_limit_reg[2]_0\
    );
\one_inc_max_limit_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => pi_f_dec_reg_0,
      CE => '1',
      D => one_inc_max_limit_nxt(3),
      Q => one_inc_max_limit(3),
      R => \one_dec_max_limit_reg[2]_0\
    );
\one_inc_max_limit_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => pi_f_dec_reg_0,
      CE => '1',
      D => one_inc_max_limit_nxt(4),
      Q => one_inc_max_limit(4),
      R => \one_dec_max_limit_reg[2]_0\
    );
\one_inc_max_limit_reg[4]_i_1\: unisim.vcomponents.CARRY4
     port map (
      CI => '0',
      CO(3) => \one_inc_max_limit_reg[4]_i_1_n_0\,
      CO(2) => \one_inc_max_limit_reg[4]_i_1_n_1\,
      CO(1) => \one_inc_max_limit_reg[4]_i_1_n_2\,
      CO(0) => \one_inc_max_limit_reg[4]_i_1_n_3\,
      CYINIT => device_temp_init(0),
      DI(3) => '0',
      DI(2) => device_temp_init(3),
      DI(1 downto 0) => B"00",
      O(3 downto 1) => one_inc_max_limit_nxt(4 downto 2),
      O(0) => \NLW_one_inc_max_limit_reg[4]_i_1_O_UNCONNECTED\(0),
      S(3) => device_temp_init(4),
      S(2) => \one_inc_max_limit[4]_i_2_n_0\,
      S(1 downto 0) => device_temp_init(2 downto 1)
    );
\one_inc_max_limit_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => pi_f_dec_reg_0,
      CE => '1',
      D => one_inc_max_limit_nxt(5),
      Q => one_inc_max_limit(5),
      R => \one_dec_max_limit_reg[2]_0\
    );
\one_inc_max_limit_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => pi_f_dec_reg_0,
      CE => '1',
      D => one_inc_max_limit_nxt(6),
      Q => one_inc_max_limit(6),
      R => \one_dec_max_limit_reg[2]_0\
    );
\one_inc_max_limit_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => pi_f_dec_reg_0,
      CE => '1',
      D => one_inc_max_limit_nxt(7),
      Q => one_inc_max_limit(7),
      R => \one_dec_max_limit_reg[2]_0\
    );
\one_inc_max_limit_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => pi_f_dec_reg_0,
      CE => '1',
      D => one_inc_max_limit_nxt(8),
      Q => one_inc_max_limit(8),
      R => \one_dec_max_limit_reg[2]_0\
    );
\one_inc_max_limit_reg[8]_i_1\: unisim.vcomponents.CARRY4
     port map (
      CI => \one_inc_max_limit_reg[4]_i_1_n_0\,
      CO(3) => \one_inc_max_limit_reg[8]_i_1_n_0\,
      CO(2) => \one_inc_max_limit_reg[8]_i_1_n_1\,
      CO(1) => \one_inc_max_limit_reg[8]_i_1_n_2\,
      CO(0) => \one_inc_max_limit_reg[8]_i_1_n_3\,
      CYINIT => '0',
      DI(3 downto 2) => device_temp_init(8 downto 7),
      DI(1 downto 0) => B"00",
      O(3 downto 0) => one_inc_max_limit_nxt(8 downto 5),
      S(3) => \one_inc_max_limit[8]_i_2_n_0\,
      S(2) => \one_inc_max_limit[8]_i_3_n_0\,
      S(1 downto 0) => device_temp_init(6 downto 5)
    );
\one_inc_max_limit_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => pi_f_dec_reg_0,
      CE => '1',
      D => one_inc_max_limit_nxt(9),
      Q => one_inc_max_limit(9),
      R => \one_dec_max_limit_reg[2]_0\
    );
\one_inc_min_limit[11]_i_2\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => two_inc_max_limit(11),
      O => \one_inc_min_limit[11]_i_2_n_0\
    );
\one_inc_min_limit[11]_i_3\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => two_inc_max_limit(10),
      O => \one_inc_min_limit[11]_i_3_n_0\
    );
\one_inc_min_limit[5]_i_2\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => two_inc_max_limit(5),
      O => \one_inc_min_limit[5]_i_2_n_0\
    );
\one_inc_min_limit[5]_i_3\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => two_inc_max_limit(4),
      O => \one_inc_min_limit[5]_i_3_n_0\
    );
\one_inc_min_limit[5]_i_4\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => two_inc_max_limit(3),
      O => \one_inc_min_limit[5]_i_4_n_0\
    );
\one_inc_min_limit[9]_i_2\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => two_inc_max_limit(9),
      O => \one_inc_min_limit[9]_i_2_n_0\
    );
\one_inc_min_limit[9]_i_3\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => two_inc_max_limit(8),
      O => \one_inc_min_limit[9]_i_3_n_0\
    );
\one_inc_min_limit[9]_i_4\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => two_inc_max_limit(7),
      O => \one_inc_min_limit[9]_i_4_n_0\
    );
\one_inc_min_limit[9]_i_5\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => two_inc_max_limit(6),
      O => \one_inc_min_limit[9]_i_5_n_0\
    );
\one_inc_min_limit_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => pi_f_dec_reg_0,
      CE => '1',
      D => one_inc_min_limit_nxt(10),
      Q => one_inc_min_limit(10),
      R => \neutral_max_limit_reg[11]_0\
    );
\one_inc_min_limit_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => pi_f_dec_reg_0,
      CE => '1',
      D => one_inc_min_limit_nxt(11),
      Q => one_inc_min_limit(11),
      R => \neutral_max_limit_reg[11]_0\
    );
\one_inc_min_limit_reg[11]_i_1\: unisim.vcomponents.CARRY4
     port map (
      CI => \one_inc_min_limit_reg[9]_i_1_n_0\,
      CO(3 downto 1) => \NLW_one_inc_min_limit_reg[11]_i_1_CO_UNCONNECTED\(3 downto 1),
      CO(0) => \one_inc_min_limit_reg[11]_i_1_n_3\,
      CYINIT => '0',
      DI(3 downto 1) => B"000",
      DI(0) => two_inc_max_limit(10),
      O(3 downto 2) => \NLW_one_inc_min_limit_reg[11]_i_1_O_UNCONNECTED\(3 downto 2),
      O(1 downto 0) => one_inc_min_limit_nxt(11 downto 10),
      S(3 downto 2) => B"00",
      S(1) => \one_inc_min_limit[11]_i_2_n_0\,
      S(0) => \one_inc_min_limit[11]_i_3_n_0\
    );
\one_inc_min_limit_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => pi_f_dec_reg_0,
      CE => '1',
      D => two_inc_max_limit(1),
      Q => one_inc_min_limit(1),
      R => \neutral_max_limit_reg[11]_0\
    );
\one_inc_min_limit_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => pi_f_dec_reg_0,
      CE => '1',
      D => one_inc_min_limit_nxt(2),
      Q => one_inc_min_limit(2),
      R => \neutral_max_limit_reg[11]_0\
    );
\one_inc_min_limit_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => pi_f_dec_reg_0,
      CE => '1',
      D => one_inc_min_limit_nxt(3),
      Q => one_inc_min_limit(3),
      R => \neutral_max_limit_reg[11]_0\
    );
\one_inc_min_limit_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => pi_f_dec_reg_0,
      CE => '1',
      D => one_inc_min_limit_nxt(4),
      Q => one_inc_min_limit(4),
      R => \neutral_max_limit_reg[11]_0\
    );
\one_inc_min_limit_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => pi_f_dec_reg_0,
      CE => '1',
      D => one_inc_min_limit_nxt(5),
      Q => one_inc_min_limit(5),
      R => \neutral_max_limit_reg[11]_0\
    );
\one_inc_min_limit_reg[5]_i_1\: unisim.vcomponents.CARRY4
     port map (
      CI => '0',
      CO(3) => \one_inc_min_limit_reg[5]_i_1_n_0\,
      CO(2) => \one_inc_min_limit_reg[5]_i_1_n_1\,
      CO(1) => \one_inc_min_limit_reg[5]_i_1_n_2\,
      CO(0) => \one_inc_min_limit_reg[5]_i_1_n_3\,
      CYINIT => '0',
      DI(3 downto 1) => two_inc_max_limit(5 downto 3),
      DI(0) => '0',
      O(3 downto 0) => one_inc_min_limit_nxt(5 downto 2),
      S(3) => \one_inc_min_limit[5]_i_2_n_0\,
      S(2) => \one_inc_min_limit[5]_i_3_n_0\,
      S(1) => \one_inc_min_limit[5]_i_4_n_0\,
      S(0) => two_inc_max_limit(2)
    );
\one_inc_min_limit_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => pi_f_dec_reg_0,
      CE => '1',
      D => one_inc_min_limit_nxt(6),
      Q => one_inc_min_limit(6),
      R => \neutral_max_limit_reg[11]_0\
    );
\one_inc_min_limit_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => pi_f_dec_reg_0,
      CE => '1',
      D => one_inc_min_limit_nxt(7),
      Q => one_inc_min_limit(7),
      R => \neutral_max_limit_reg[11]_0\
    );
\one_inc_min_limit_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => pi_f_dec_reg_0,
      CE => '1',
      D => one_inc_min_limit_nxt(8),
      Q => one_inc_min_limit(8),
      R => \neutral_max_limit_reg[11]_0\
    );
\one_inc_min_limit_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => pi_f_dec_reg_0,
      CE => '1',
      D => one_inc_min_limit_nxt(9),
      Q => one_inc_min_limit(9),
      R => \neutral_max_limit_reg[11]_0\
    );
\one_inc_min_limit_reg[9]_i_1\: unisim.vcomponents.CARRY4
     port map (
      CI => \one_inc_min_limit_reg[5]_i_1_n_0\,
      CO(3) => \one_inc_min_limit_reg[9]_i_1_n_0\,
      CO(2) => \one_inc_min_limit_reg[9]_i_1_n_1\,
      CO(1) => \one_inc_min_limit_reg[9]_i_1_n_2\,
      CO(0) => \one_inc_min_limit_reg[9]_i_1_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => two_inc_max_limit(9 downto 6),
      O(3 downto 0) => one_inc_min_limit_nxt(9 downto 6),
      S(3) => \one_inc_min_limit[9]_i_2_n_0\,
      S(2) => \one_inc_min_limit[9]_i_3_n_0\,
      S(1) => \one_inc_min_limit[9]_i_4_n_0\,
      S(0) => \one_inc_min_limit[9]_i_5_n_0\
    );
pi_f_dec_i_1: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8A88"
    )
        port map (
      I0 => \tempmon_state[10]_i_6_n_0\,
      I1 => \tempmon_state[10]_i_5_n_0\,
      I2 => pi_f_dec_i_2_n_0,
      I3 => update_temp_102,
      O => pi_f_dec_nxt
    );
pi_f_dec_i_2: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000077707770777"
    )
        port map (
      I0 => tempmon_state(3),
      I1 => temp_cmp_three_inc_max_102,
      I2 => temp_cmp_two_inc_max_102,
      I3 => tempmon_state(4),
      I4 => temp_cmp_one_inc_max_102,
      I5 => tempmon_state(5),
      O => pi_f_dec_i_2_n_0
    );
pi_f_dec_reg: unisim.vcomponents.FDRE
     port map (
      C => pi_f_dec_reg_0,
      CE => '1',
      D => pi_f_dec_nxt,
      Q => tempmon_pi_f_dec,
      R => pi_f_dec_reg_1(0)
    );
pi_f_inc_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFF7555500000000"
    )
        port map (
      I0 => pi_f_inc_i_2_n_0,
      I1 => pi_f_inc_i_3_n_0,
      I2 => pi_f_inc_i_4_n_0,
      I3 => pi_f_inc_i_5_n_0,
      I4 => update_temp_102,
      I5 => \tempmon_state[10]_i_6_n_0\,
      O => pi_f_inc_nxt
    );
pi_f_inc_i_2: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00FFF7FFF7FFF7FF"
    )
        port map (
      I0 => temp_cmp_one_inc_min_102,
      I1 => tempmon_state(5),
      I2 => temp_cmp_one_inc_max_102,
      I3 => update_temp_102,
      I4 => temp_cmp_four_dec_min_102,
      I5 => tempmon_state(10),
      O => pi_f_inc_i_2_n_0
    );
pi_f_inc_i_3: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F7000000F777F777"
    )
        port map (
      I0 => tempmon_state(8),
      I1 => temp_cmp_two_dec_min_102,
      I2 => temp_cmp_two_dec_max_102,
      I3 => update_temp_102,
      I4 => temp_cmp_one_dec_max_102,
      I5 => pi_f_inc_i_6_n_0,
      O => pi_f_inc_i_3_n_0
    );
pi_f_inc_i_4: unisim.vcomponents.LUT6
    generic map(
      INIT => X"40FF404040404040"
    )
        port map (
      I0 => temp_cmp_three_inc_max_102,
      I1 => tempmon_state(3),
      I2 => temp_cmp_three_inc_min_102,
      I3 => temp_cmp_two_inc_max_102,
      I4 => tempmon_state(4),
      I5 => temp_cmp_two_inc_min_102,
      O => pi_f_inc_i_4_n_0
    );
pi_f_inc_i_5: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0808FF88FF08FF88"
    )
        port map (
      I0 => tempmon_state(9),
      I1 => temp_cmp_three_dec_min_102,
      I2 => temp_cmp_three_dec_max_102,
      I3 => pi_f_inc_i_7_n_0,
      I4 => update_temp_102,
      I5 => temp_cmp_neutral_max_102,
      O => pi_f_inc_i_5_n_0
    );
pi_f_inc_i_6: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => tempmon_state(7),
      I1 => temp_cmp_one_dec_min_102,
      O => pi_f_inc_i_6_n_0
    );
pi_f_inc_i_7: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => tempmon_state(6),
      I1 => temp_cmp_neutral_min_102,
      O => pi_f_inc_i_7_n_0
    );
pi_f_inc_reg: unisim.vcomponents.FDRE
     port map (
      C => pi_f_dec_reg_0,
      CE => '1',
      D => pi_f_inc_nxt,
      Q => \^tempmon_pi_f_inc\,
      R => \four_dec_min_limit_reg[0]_0\
    );
temp_cmp_four_dec_min_102_i_10: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F02"
    )
        port map (
      I0 => four_dec_min_limit(0),
      I1 => device_temp_101(0),
      I2 => device_temp_101(1),
      I3 => four_dec_min_limit(1),
      O => temp_cmp_four_dec_min_102_i_10_n_0
    );
temp_cmp_four_dec_min_102_i_11: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => four_dec_min_limit(6),
      I1 => device_temp_101(6),
      I2 => four_dec_min_limit(7),
      I3 => device_temp_101(7),
      O => temp_cmp_four_dec_min_102_i_11_n_0
    );
temp_cmp_four_dec_min_102_i_12: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => four_dec_min_limit(4),
      I1 => device_temp_101(4),
      I2 => four_dec_min_limit(5),
      I3 => device_temp_101(5),
      O => temp_cmp_four_dec_min_102_i_12_n_0
    );
temp_cmp_four_dec_min_102_i_13: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => four_dec_min_limit(2),
      I1 => device_temp_101(2),
      I2 => four_dec_min_limit(3),
      I3 => device_temp_101(3),
      O => temp_cmp_four_dec_min_102_i_13_n_0
    );
temp_cmp_four_dec_min_102_i_14: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => four_dec_min_limit(0),
      I1 => device_temp_101(0),
      I2 => four_dec_min_limit(1),
      I3 => device_temp_101(1),
      O => temp_cmp_four_dec_min_102_i_14_n_0
    );
temp_cmp_four_dec_min_102_i_3: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F02"
    )
        port map (
      I0 => four_dec_min_limit(10),
      I1 => device_temp_101(10),
      I2 => device_temp_101(11),
      I3 => four_dec_min_limit(11),
      O => temp_cmp_four_dec_min_102_i_3_n_0
    );
temp_cmp_four_dec_min_102_i_4: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F02"
    )
        port map (
      I0 => four_dec_min_limit(8),
      I1 => device_temp_101(8),
      I2 => device_temp_101(9),
      I3 => four_dec_min_limit(9),
      O => temp_cmp_four_dec_min_102_i_4_n_0
    );
temp_cmp_four_dec_min_102_i_5: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => four_dec_min_limit(10),
      I1 => device_temp_101(10),
      I2 => four_dec_min_limit(11),
      I3 => device_temp_101(11),
      O => temp_cmp_four_dec_min_102_i_5_n_0
    );
temp_cmp_four_dec_min_102_i_6: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => four_dec_min_limit(8),
      I1 => device_temp_101(8),
      I2 => four_dec_min_limit(9),
      I3 => device_temp_101(9),
      O => temp_cmp_four_dec_min_102_i_6_n_0
    );
temp_cmp_four_dec_min_102_i_7: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F02"
    )
        port map (
      I0 => four_dec_min_limit(6),
      I1 => device_temp_101(6),
      I2 => device_temp_101(7),
      I3 => four_dec_min_limit(7),
      O => temp_cmp_four_dec_min_102_i_7_n_0
    );
temp_cmp_four_dec_min_102_i_8: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F02"
    )
        port map (
      I0 => four_dec_min_limit(4),
      I1 => device_temp_101(4),
      I2 => device_temp_101(5),
      I3 => four_dec_min_limit(5),
      O => temp_cmp_four_dec_min_102_i_8_n_0
    );
temp_cmp_four_dec_min_102_i_9: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F02"
    )
        port map (
      I0 => four_dec_min_limit(2),
      I1 => device_temp_101(2),
      I2 => device_temp_101(3),
      I3 => four_dec_min_limit(3),
      O => temp_cmp_four_dec_min_102_i_9_n_0
    );
temp_cmp_four_dec_min_102_reg: unisim.vcomponents.FDRE
     port map (
      C => pi_f_dec_reg_0,
      CE => '1',
      D => temp_cmp_four_dec_min_101,
      Q => temp_cmp_four_dec_min_102,
      R => '0'
    );
temp_cmp_four_dec_min_102_reg_i_1: unisim.vcomponents.CARRY4
     port map (
      CI => temp_cmp_four_dec_min_102_reg_i_2_n_0,
      CO(3 downto 2) => NLW_temp_cmp_four_dec_min_102_reg_i_1_CO_UNCONNECTED(3 downto 2),
      CO(1) => temp_cmp_four_dec_min_101,
      CO(0) => temp_cmp_four_dec_min_102_reg_i_1_n_3,
      CYINIT => '0',
      DI(3 downto 2) => B"00",
      DI(1) => temp_cmp_four_dec_min_102_i_3_n_0,
      DI(0) => temp_cmp_four_dec_min_102_i_4_n_0,
      O(3 downto 0) => NLW_temp_cmp_four_dec_min_102_reg_i_1_O_UNCONNECTED(3 downto 0),
      S(3 downto 2) => B"00",
      S(1) => temp_cmp_four_dec_min_102_i_5_n_0,
      S(0) => temp_cmp_four_dec_min_102_i_6_n_0
    );
temp_cmp_four_dec_min_102_reg_i_2: unisim.vcomponents.CARRY4
     port map (
      CI => '0',
      CO(3) => temp_cmp_four_dec_min_102_reg_i_2_n_0,
      CO(2) => temp_cmp_four_dec_min_102_reg_i_2_n_1,
      CO(1) => temp_cmp_four_dec_min_102_reg_i_2_n_2,
      CO(0) => temp_cmp_four_dec_min_102_reg_i_2_n_3,
      CYINIT => '0',
      DI(3) => temp_cmp_four_dec_min_102_i_7_n_0,
      DI(2) => temp_cmp_four_dec_min_102_i_8_n_0,
      DI(1) => temp_cmp_four_dec_min_102_i_9_n_0,
      DI(0) => temp_cmp_four_dec_min_102_i_10_n_0,
      O(3 downto 0) => NLW_temp_cmp_four_dec_min_102_reg_i_2_O_UNCONNECTED(3 downto 0),
      S(3) => temp_cmp_four_dec_min_102_i_11_n_0,
      S(2) => temp_cmp_four_dec_min_102_i_12_n_0,
      S(1) => temp_cmp_four_dec_min_102_i_13_n_0,
      S(0) => temp_cmp_four_dec_min_102_i_14_n_0
    );
temp_cmp_four_inc_max_102_i_10: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F02"
    )
        port map (
      I0 => device_temp_101(0),
      I1 => two_dec_max_limit(0),
      I2 => two_inc_max_limit(1),
      I3 => device_temp_101(1),
      O => temp_cmp_four_inc_max_102_i_10_n_0
    );
temp_cmp_four_inc_max_102_i_11: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => device_temp_101(6),
      I1 => four_inc_max_limit(6),
      I2 => device_temp_101(7),
      I3 => four_inc_max_limit(7),
      O => temp_cmp_four_inc_max_102_i_11_n_0
    );
temp_cmp_four_inc_max_102_i_12: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => device_temp_101(4),
      I1 => four_inc_max_limit(4),
      I2 => device_temp_101(5),
      I3 => four_inc_max_limit(5),
      O => temp_cmp_four_inc_max_102_i_12_n_0
    );
temp_cmp_four_inc_max_102_i_13: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => device_temp_101(2),
      I1 => four_inc_max_limit(2),
      I2 => device_temp_101(3),
      I3 => four_inc_max_limit(3),
      O => temp_cmp_four_inc_max_102_i_13_n_0
    );
temp_cmp_four_inc_max_102_i_14: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => device_temp_101(0),
      I1 => two_dec_max_limit(0),
      I2 => device_temp_101(1),
      I3 => two_inc_max_limit(1),
      O => temp_cmp_four_inc_max_102_i_14_n_0
    );
temp_cmp_four_inc_max_102_i_3: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F02"
    )
        port map (
      I0 => device_temp_101(10),
      I1 => four_inc_max_limit(10),
      I2 => four_inc_max_limit(11),
      I3 => device_temp_101(11),
      O => temp_cmp_four_inc_max_102_i_3_n_0
    );
temp_cmp_four_inc_max_102_i_4: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F02"
    )
        port map (
      I0 => device_temp_101(8),
      I1 => four_inc_max_limit(8),
      I2 => four_inc_max_limit(9),
      I3 => device_temp_101(9),
      O => temp_cmp_four_inc_max_102_i_4_n_0
    );
temp_cmp_four_inc_max_102_i_5: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => device_temp_101(10),
      I1 => four_inc_max_limit(10),
      I2 => device_temp_101(11),
      I3 => four_inc_max_limit(11),
      O => temp_cmp_four_inc_max_102_i_5_n_0
    );
temp_cmp_four_inc_max_102_i_6: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => device_temp_101(8),
      I1 => four_inc_max_limit(8),
      I2 => device_temp_101(9),
      I3 => four_inc_max_limit(9),
      O => temp_cmp_four_inc_max_102_i_6_n_0
    );
temp_cmp_four_inc_max_102_i_7: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F02"
    )
        port map (
      I0 => device_temp_101(6),
      I1 => four_inc_max_limit(6),
      I2 => four_inc_max_limit(7),
      I3 => device_temp_101(7),
      O => temp_cmp_four_inc_max_102_i_7_n_0
    );
temp_cmp_four_inc_max_102_i_8: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F02"
    )
        port map (
      I0 => device_temp_101(4),
      I1 => four_inc_max_limit(4),
      I2 => four_inc_max_limit(5),
      I3 => device_temp_101(5),
      O => temp_cmp_four_inc_max_102_i_8_n_0
    );
temp_cmp_four_inc_max_102_i_9: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F02"
    )
        port map (
      I0 => device_temp_101(2),
      I1 => four_inc_max_limit(2),
      I2 => four_inc_max_limit(3),
      I3 => device_temp_101(3),
      O => temp_cmp_four_inc_max_102_i_9_n_0
    );
temp_cmp_four_inc_max_102_reg: unisim.vcomponents.FDRE
     port map (
      C => pi_f_dec_reg_0,
      CE => '1',
      D => temp_cmp_four_inc_max_101,
      Q => temp_cmp_four_inc_max_102,
      R => '0'
    );
temp_cmp_four_inc_max_102_reg_i_1: unisim.vcomponents.CARRY4
     port map (
      CI => temp_cmp_four_inc_max_102_reg_i_2_n_0,
      CO(3 downto 2) => NLW_temp_cmp_four_inc_max_102_reg_i_1_CO_UNCONNECTED(3 downto 2),
      CO(1) => temp_cmp_four_inc_max_101,
      CO(0) => temp_cmp_four_inc_max_102_reg_i_1_n_3,
      CYINIT => '0',
      DI(3 downto 2) => B"00",
      DI(1) => temp_cmp_four_inc_max_102_i_3_n_0,
      DI(0) => temp_cmp_four_inc_max_102_i_4_n_0,
      O(3 downto 0) => NLW_temp_cmp_four_inc_max_102_reg_i_1_O_UNCONNECTED(3 downto 0),
      S(3 downto 2) => B"00",
      S(1) => temp_cmp_four_inc_max_102_i_5_n_0,
      S(0) => temp_cmp_four_inc_max_102_i_6_n_0
    );
temp_cmp_four_inc_max_102_reg_i_2: unisim.vcomponents.CARRY4
     port map (
      CI => '0',
      CO(3) => temp_cmp_four_inc_max_102_reg_i_2_n_0,
      CO(2) => temp_cmp_four_inc_max_102_reg_i_2_n_1,
      CO(1) => temp_cmp_four_inc_max_102_reg_i_2_n_2,
      CO(0) => temp_cmp_four_inc_max_102_reg_i_2_n_3,
      CYINIT => '1',
      DI(3) => temp_cmp_four_inc_max_102_i_7_n_0,
      DI(2) => temp_cmp_four_inc_max_102_i_8_n_0,
      DI(1) => temp_cmp_four_inc_max_102_i_9_n_0,
      DI(0) => temp_cmp_four_inc_max_102_i_10_n_0,
      O(3 downto 0) => NLW_temp_cmp_four_inc_max_102_reg_i_2_O_UNCONNECTED(3 downto 0),
      S(3) => temp_cmp_four_inc_max_102_i_11_n_0,
      S(2) => temp_cmp_four_inc_max_102_i_12_n_0,
      S(1) => temp_cmp_four_inc_max_102_i_13_n_0,
      S(0) => temp_cmp_four_inc_max_102_i_14_n_0
    );
temp_cmp_neutral_max_102_i_10: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F02"
    )
        port map (
      I0 => device_temp_101(0),
      I1 => two_dec_max_limit(0),
      I2 => two_inc_max_limit(1),
      I3 => device_temp_101(1),
      O => temp_cmp_neutral_max_102_i_10_n_0
    );
temp_cmp_neutral_max_102_i_11: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => device_temp_101(6),
      I1 => neutral_max_limit(6),
      I2 => device_temp_101(7),
      I3 => neutral_max_limit(7),
      O => temp_cmp_neutral_max_102_i_11_n_0
    );
temp_cmp_neutral_max_102_i_12: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => device_temp_101(4),
      I1 => neutral_max_limit(4),
      I2 => device_temp_101(5),
      I3 => neutral_max_limit(5),
      O => temp_cmp_neutral_max_102_i_12_n_0
    );
temp_cmp_neutral_max_102_i_13: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => device_temp_101(2),
      I1 => neutral_max_limit(2),
      I2 => device_temp_101(3),
      I3 => neutral_max_limit(3),
      O => temp_cmp_neutral_max_102_i_13_n_0
    );
temp_cmp_neutral_max_102_i_14: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => device_temp_101(0),
      I1 => two_dec_max_limit(0),
      I2 => device_temp_101(1),
      I3 => two_inc_max_limit(1),
      O => temp_cmp_neutral_max_102_i_14_n_0
    );
temp_cmp_neutral_max_102_i_3: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F02"
    )
        port map (
      I0 => device_temp_101(10),
      I1 => neutral_max_limit(10),
      I2 => neutral_max_limit(11),
      I3 => device_temp_101(11),
      O => temp_cmp_neutral_max_102_i_3_n_0
    );
temp_cmp_neutral_max_102_i_4: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F02"
    )
        port map (
      I0 => device_temp_101(8),
      I1 => neutral_max_limit(8),
      I2 => neutral_max_limit(9),
      I3 => device_temp_101(9),
      O => temp_cmp_neutral_max_102_i_4_n_0
    );
temp_cmp_neutral_max_102_i_5: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => device_temp_101(10),
      I1 => neutral_max_limit(10),
      I2 => device_temp_101(11),
      I3 => neutral_max_limit(11),
      O => temp_cmp_neutral_max_102_i_5_n_0
    );
temp_cmp_neutral_max_102_i_6: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => device_temp_101(8),
      I1 => neutral_max_limit(8),
      I2 => device_temp_101(9),
      I3 => neutral_max_limit(9),
      O => temp_cmp_neutral_max_102_i_6_n_0
    );
temp_cmp_neutral_max_102_i_7: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F02"
    )
        port map (
      I0 => device_temp_101(6),
      I1 => neutral_max_limit(6),
      I2 => neutral_max_limit(7),
      I3 => device_temp_101(7),
      O => temp_cmp_neutral_max_102_i_7_n_0
    );
temp_cmp_neutral_max_102_i_8: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F02"
    )
        port map (
      I0 => device_temp_101(4),
      I1 => neutral_max_limit(4),
      I2 => neutral_max_limit(5),
      I3 => device_temp_101(5),
      O => temp_cmp_neutral_max_102_i_8_n_0
    );
temp_cmp_neutral_max_102_i_9: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F02"
    )
        port map (
      I0 => device_temp_101(2),
      I1 => neutral_max_limit(2),
      I2 => neutral_max_limit(3),
      I3 => device_temp_101(3),
      O => temp_cmp_neutral_max_102_i_9_n_0
    );
temp_cmp_neutral_max_102_reg: unisim.vcomponents.FDRE
     port map (
      C => pi_f_dec_reg_0,
      CE => '1',
      D => temp_cmp_neutral_max_101,
      Q => temp_cmp_neutral_max_102,
      R => '0'
    );
temp_cmp_neutral_max_102_reg_i_1: unisim.vcomponents.CARRY4
     port map (
      CI => temp_cmp_neutral_max_102_reg_i_2_n_0,
      CO(3 downto 2) => NLW_temp_cmp_neutral_max_102_reg_i_1_CO_UNCONNECTED(3 downto 2),
      CO(1) => temp_cmp_neutral_max_101,
      CO(0) => temp_cmp_neutral_max_102_reg_i_1_n_3,
      CYINIT => '0',
      DI(3 downto 2) => B"00",
      DI(1) => temp_cmp_neutral_max_102_i_3_n_0,
      DI(0) => temp_cmp_neutral_max_102_i_4_n_0,
      O(3 downto 0) => NLW_temp_cmp_neutral_max_102_reg_i_1_O_UNCONNECTED(3 downto 0),
      S(3 downto 2) => B"00",
      S(1) => temp_cmp_neutral_max_102_i_5_n_0,
      S(0) => temp_cmp_neutral_max_102_i_6_n_0
    );
temp_cmp_neutral_max_102_reg_i_2: unisim.vcomponents.CARRY4
     port map (
      CI => '0',
      CO(3) => temp_cmp_neutral_max_102_reg_i_2_n_0,
      CO(2) => temp_cmp_neutral_max_102_reg_i_2_n_1,
      CO(1) => temp_cmp_neutral_max_102_reg_i_2_n_2,
      CO(0) => temp_cmp_neutral_max_102_reg_i_2_n_3,
      CYINIT => '1',
      DI(3) => temp_cmp_neutral_max_102_i_7_n_0,
      DI(2) => temp_cmp_neutral_max_102_i_8_n_0,
      DI(1) => temp_cmp_neutral_max_102_i_9_n_0,
      DI(0) => temp_cmp_neutral_max_102_i_10_n_0,
      O(3 downto 0) => NLW_temp_cmp_neutral_max_102_reg_i_2_O_UNCONNECTED(3 downto 0),
      S(3) => temp_cmp_neutral_max_102_i_11_n_0,
      S(2) => temp_cmp_neutral_max_102_i_12_n_0,
      S(1) => temp_cmp_neutral_max_102_i_13_n_0,
      S(0) => temp_cmp_neutral_max_102_i_14_n_0
    );
temp_cmp_neutral_min_102_i_10: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F02"
    )
        port map (
      I0 => three_dec_min_limit(0),
      I1 => device_temp_101(0),
      I2 => device_temp_101(1),
      I3 => two_inc_min_limit(1),
      O => temp_cmp_neutral_min_102_i_10_n_0
    );
temp_cmp_neutral_min_102_i_11: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => neutral_min_limit(6),
      I1 => device_temp_101(6),
      I2 => neutral_min_limit(7),
      I3 => device_temp_101(7),
      O => temp_cmp_neutral_min_102_i_11_n_0
    );
temp_cmp_neutral_min_102_i_12: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => neutral_min_limit(4),
      I1 => device_temp_101(4),
      I2 => neutral_min_limit(5),
      I3 => device_temp_101(5),
      O => temp_cmp_neutral_min_102_i_12_n_0
    );
temp_cmp_neutral_min_102_i_13: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => neutral_min_limit(2),
      I1 => device_temp_101(2),
      I2 => neutral_min_limit(3),
      I3 => device_temp_101(3),
      O => temp_cmp_neutral_min_102_i_13_n_0
    );
temp_cmp_neutral_min_102_i_14: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => three_dec_min_limit(0),
      I1 => device_temp_101(0),
      I2 => two_inc_min_limit(1),
      I3 => device_temp_101(1),
      O => temp_cmp_neutral_min_102_i_14_n_0
    );
temp_cmp_neutral_min_102_i_3: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F02"
    )
        port map (
      I0 => neutral_min_limit(10),
      I1 => device_temp_101(10),
      I2 => device_temp_101(11),
      I3 => neutral_min_limit(11),
      O => temp_cmp_neutral_min_102_i_3_n_0
    );
temp_cmp_neutral_min_102_i_4: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F02"
    )
        port map (
      I0 => neutral_min_limit(8),
      I1 => device_temp_101(8),
      I2 => device_temp_101(9),
      I3 => neutral_min_limit(9),
      O => temp_cmp_neutral_min_102_i_4_n_0
    );
temp_cmp_neutral_min_102_i_5: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => neutral_min_limit(10),
      I1 => device_temp_101(10),
      I2 => neutral_min_limit(11),
      I3 => device_temp_101(11),
      O => temp_cmp_neutral_min_102_i_5_n_0
    );
temp_cmp_neutral_min_102_i_6: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => neutral_min_limit(8),
      I1 => device_temp_101(8),
      I2 => neutral_min_limit(9),
      I3 => device_temp_101(9),
      O => temp_cmp_neutral_min_102_i_6_n_0
    );
temp_cmp_neutral_min_102_i_7: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F02"
    )
        port map (
      I0 => neutral_min_limit(6),
      I1 => device_temp_101(6),
      I2 => device_temp_101(7),
      I3 => neutral_min_limit(7),
      O => temp_cmp_neutral_min_102_i_7_n_0
    );
temp_cmp_neutral_min_102_i_8: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F02"
    )
        port map (
      I0 => neutral_min_limit(4),
      I1 => device_temp_101(4),
      I2 => device_temp_101(5),
      I3 => neutral_min_limit(5),
      O => temp_cmp_neutral_min_102_i_8_n_0
    );
temp_cmp_neutral_min_102_i_9: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F02"
    )
        port map (
      I0 => neutral_min_limit(2),
      I1 => device_temp_101(2),
      I2 => device_temp_101(3),
      I3 => neutral_min_limit(3),
      O => temp_cmp_neutral_min_102_i_9_n_0
    );
temp_cmp_neutral_min_102_reg: unisim.vcomponents.FDRE
     port map (
      C => pi_f_dec_reg_0,
      CE => '1',
      D => temp_cmp_neutral_min_101,
      Q => temp_cmp_neutral_min_102,
      R => '0'
    );
temp_cmp_neutral_min_102_reg_i_1: unisim.vcomponents.CARRY4
     port map (
      CI => temp_cmp_neutral_min_102_reg_i_2_n_0,
      CO(3 downto 2) => NLW_temp_cmp_neutral_min_102_reg_i_1_CO_UNCONNECTED(3 downto 2),
      CO(1) => temp_cmp_neutral_min_101,
      CO(0) => temp_cmp_neutral_min_102_reg_i_1_n_3,
      CYINIT => '0',
      DI(3 downto 2) => B"00",
      DI(1) => temp_cmp_neutral_min_102_i_3_n_0,
      DI(0) => temp_cmp_neutral_min_102_i_4_n_0,
      O(3 downto 0) => NLW_temp_cmp_neutral_min_102_reg_i_1_O_UNCONNECTED(3 downto 0),
      S(3 downto 2) => B"00",
      S(1) => temp_cmp_neutral_min_102_i_5_n_0,
      S(0) => temp_cmp_neutral_min_102_i_6_n_0
    );
temp_cmp_neutral_min_102_reg_i_2: unisim.vcomponents.CARRY4
     port map (
      CI => '0',
      CO(3) => temp_cmp_neutral_min_102_reg_i_2_n_0,
      CO(2) => temp_cmp_neutral_min_102_reg_i_2_n_1,
      CO(1) => temp_cmp_neutral_min_102_reg_i_2_n_2,
      CO(0) => temp_cmp_neutral_min_102_reg_i_2_n_3,
      CYINIT => '0',
      DI(3) => temp_cmp_neutral_min_102_i_7_n_0,
      DI(2) => temp_cmp_neutral_min_102_i_8_n_0,
      DI(1) => temp_cmp_neutral_min_102_i_9_n_0,
      DI(0) => temp_cmp_neutral_min_102_i_10_n_0,
      O(3 downto 0) => NLW_temp_cmp_neutral_min_102_reg_i_2_O_UNCONNECTED(3 downto 0),
      S(3) => temp_cmp_neutral_min_102_i_11_n_0,
      S(2) => temp_cmp_neutral_min_102_i_12_n_0,
      S(1) => temp_cmp_neutral_min_102_i_13_n_0,
      S(0) => temp_cmp_neutral_min_102_i_14_n_0
    );
temp_cmp_one_dec_max_102_i_10: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F02"
    )
        port map (
      I0 => device_temp_101(0),
      I1 => two_dec_max_limit(0),
      I2 => one_inc_max_limit(1),
      I3 => device_temp_101(1),
      O => temp_cmp_one_dec_max_102_i_10_n_0
    );
temp_cmp_one_dec_max_102_i_11: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => device_temp_101(6),
      I1 => one_dec_max_limit(6),
      I2 => device_temp_101(7),
      I3 => one_dec_max_limit(7),
      O => temp_cmp_one_dec_max_102_i_11_n_0
    );
temp_cmp_one_dec_max_102_i_12: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => device_temp_101(4),
      I1 => one_dec_max_limit(4),
      I2 => device_temp_101(5),
      I3 => one_dec_max_limit(5),
      O => temp_cmp_one_dec_max_102_i_12_n_0
    );
temp_cmp_one_dec_max_102_i_13: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => device_temp_101(2),
      I1 => one_dec_max_limit(2),
      I2 => device_temp_101(3),
      I3 => one_dec_max_limit(3),
      O => temp_cmp_one_dec_max_102_i_13_n_0
    );
temp_cmp_one_dec_max_102_i_14: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => device_temp_101(0),
      I1 => two_dec_max_limit(0),
      I2 => device_temp_101(1),
      I3 => one_inc_max_limit(1),
      O => temp_cmp_one_dec_max_102_i_14_n_0
    );
temp_cmp_one_dec_max_102_i_3: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F02"
    )
        port map (
      I0 => device_temp_101(10),
      I1 => one_dec_max_limit(10),
      I2 => one_dec_max_limit(11),
      I3 => device_temp_101(11),
      O => temp_cmp_one_dec_max_102_i_3_n_0
    );
temp_cmp_one_dec_max_102_i_4: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F02"
    )
        port map (
      I0 => device_temp_101(8),
      I1 => one_dec_max_limit(8),
      I2 => one_dec_max_limit(9),
      I3 => device_temp_101(9),
      O => temp_cmp_one_dec_max_102_i_4_n_0
    );
temp_cmp_one_dec_max_102_i_5: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => device_temp_101(10),
      I1 => one_dec_max_limit(10),
      I2 => device_temp_101(11),
      I3 => one_dec_max_limit(11),
      O => temp_cmp_one_dec_max_102_i_5_n_0
    );
temp_cmp_one_dec_max_102_i_6: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => device_temp_101(8),
      I1 => one_dec_max_limit(8),
      I2 => device_temp_101(9),
      I3 => one_dec_max_limit(9),
      O => temp_cmp_one_dec_max_102_i_6_n_0
    );
temp_cmp_one_dec_max_102_i_7: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F02"
    )
        port map (
      I0 => device_temp_101(6),
      I1 => one_dec_max_limit(6),
      I2 => one_dec_max_limit(7),
      I3 => device_temp_101(7),
      O => temp_cmp_one_dec_max_102_i_7_n_0
    );
temp_cmp_one_dec_max_102_i_8: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F02"
    )
        port map (
      I0 => device_temp_101(4),
      I1 => one_dec_max_limit(4),
      I2 => one_dec_max_limit(5),
      I3 => device_temp_101(5),
      O => temp_cmp_one_dec_max_102_i_8_n_0
    );
temp_cmp_one_dec_max_102_i_9: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F02"
    )
        port map (
      I0 => device_temp_101(2),
      I1 => one_dec_max_limit(2),
      I2 => one_dec_max_limit(3),
      I3 => device_temp_101(3),
      O => temp_cmp_one_dec_max_102_i_9_n_0
    );
temp_cmp_one_dec_max_102_reg: unisim.vcomponents.FDRE
     port map (
      C => pi_f_dec_reg_0,
      CE => '1',
      D => temp_cmp_one_dec_max_101,
      Q => temp_cmp_one_dec_max_102,
      R => '0'
    );
temp_cmp_one_dec_max_102_reg_i_1: unisim.vcomponents.CARRY4
     port map (
      CI => temp_cmp_one_dec_max_102_reg_i_2_n_0,
      CO(3 downto 2) => NLW_temp_cmp_one_dec_max_102_reg_i_1_CO_UNCONNECTED(3 downto 2),
      CO(1) => temp_cmp_one_dec_max_101,
      CO(0) => temp_cmp_one_dec_max_102_reg_i_1_n_3,
      CYINIT => '0',
      DI(3 downto 2) => B"00",
      DI(1) => temp_cmp_one_dec_max_102_i_3_n_0,
      DI(0) => temp_cmp_one_dec_max_102_i_4_n_0,
      O(3 downto 0) => NLW_temp_cmp_one_dec_max_102_reg_i_1_O_UNCONNECTED(3 downto 0),
      S(3 downto 2) => B"00",
      S(1) => temp_cmp_one_dec_max_102_i_5_n_0,
      S(0) => temp_cmp_one_dec_max_102_i_6_n_0
    );
temp_cmp_one_dec_max_102_reg_i_2: unisim.vcomponents.CARRY4
     port map (
      CI => '0',
      CO(3) => temp_cmp_one_dec_max_102_reg_i_2_n_0,
      CO(2) => temp_cmp_one_dec_max_102_reg_i_2_n_1,
      CO(1) => temp_cmp_one_dec_max_102_reg_i_2_n_2,
      CO(0) => temp_cmp_one_dec_max_102_reg_i_2_n_3,
      CYINIT => '1',
      DI(3) => temp_cmp_one_dec_max_102_i_7_n_0,
      DI(2) => temp_cmp_one_dec_max_102_i_8_n_0,
      DI(1) => temp_cmp_one_dec_max_102_i_9_n_0,
      DI(0) => temp_cmp_one_dec_max_102_i_10_n_0,
      O(3 downto 0) => NLW_temp_cmp_one_dec_max_102_reg_i_2_O_UNCONNECTED(3 downto 0),
      S(3) => temp_cmp_one_dec_max_102_i_11_n_0,
      S(2) => temp_cmp_one_dec_max_102_i_12_n_0,
      S(1) => temp_cmp_one_dec_max_102_i_13_n_0,
      S(0) => temp_cmp_one_dec_max_102_i_14_n_0
    );
temp_cmp_one_dec_min_102_i_10: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F02"
    )
        port map (
      I0 => three_dec_min_limit(0),
      I1 => device_temp_101(0),
      I2 => device_temp_101(1),
      I3 => one_inc_min_limit(1),
      O => temp_cmp_one_dec_min_102_i_10_n_0
    );
temp_cmp_one_dec_min_102_i_11: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => one_dec_min_limit(6),
      I1 => device_temp_101(6),
      I2 => one_dec_min_limit(7),
      I3 => device_temp_101(7),
      O => temp_cmp_one_dec_min_102_i_11_n_0
    );
temp_cmp_one_dec_min_102_i_12: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => one_dec_min_limit(4),
      I1 => device_temp_101(4),
      I2 => one_dec_min_limit(5),
      I3 => device_temp_101(5),
      O => temp_cmp_one_dec_min_102_i_12_n_0
    );
temp_cmp_one_dec_min_102_i_13: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => one_dec_min_limit(2),
      I1 => device_temp_101(2),
      I2 => one_dec_min_limit(3),
      I3 => device_temp_101(3),
      O => temp_cmp_one_dec_min_102_i_13_n_0
    );
temp_cmp_one_dec_min_102_i_14: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => three_dec_min_limit(0),
      I1 => device_temp_101(0),
      I2 => one_inc_min_limit(1),
      I3 => device_temp_101(1),
      O => temp_cmp_one_dec_min_102_i_14_n_0
    );
temp_cmp_one_dec_min_102_i_3: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F02"
    )
        port map (
      I0 => one_dec_min_limit(10),
      I1 => device_temp_101(10),
      I2 => device_temp_101(11),
      I3 => one_dec_min_limit(11),
      O => temp_cmp_one_dec_min_102_i_3_n_0
    );
temp_cmp_one_dec_min_102_i_4: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F02"
    )
        port map (
      I0 => one_dec_min_limit(8),
      I1 => device_temp_101(8),
      I2 => device_temp_101(9),
      I3 => one_dec_min_limit(9),
      O => temp_cmp_one_dec_min_102_i_4_n_0
    );
temp_cmp_one_dec_min_102_i_5: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => one_dec_min_limit(10),
      I1 => device_temp_101(10),
      I2 => one_dec_min_limit(11),
      I3 => device_temp_101(11),
      O => temp_cmp_one_dec_min_102_i_5_n_0
    );
temp_cmp_one_dec_min_102_i_6: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => one_dec_min_limit(8),
      I1 => device_temp_101(8),
      I2 => one_dec_min_limit(9),
      I3 => device_temp_101(9),
      O => temp_cmp_one_dec_min_102_i_6_n_0
    );
temp_cmp_one_dec_min_102_i_7: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F02"
    )
        port map (
      I0 => one_dec_min_limit(6),
      I1 => device_temp_101(6),
      I2 => device_temp_101(7),
      I3 => one_dec_min_limit(7),
      O => temp_cmp_one_dec_min_102_i_7_n_0
    );
temp_cmp_one_dec_min_102_i_8: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F02"
    )
        port map (
      I0 => one_dec_min_limit(4),
      I1 => device_temp_101(4),
      I2 => device_temp_101(5),
      I3 => one_dec_min_limit(5),
      O => temp_cmp_one_dec_min_102_i_8_n_0
    );
temp_cmp_one_dec_min_102_i_9: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F02"
    )
        port map (
      I0 => one_dec_min_limit(2),
      I1 => device_temp_101(2),
      I2 => device_temp_101(3),
      I3 => one_dec_min_limit(3),
      O => temp_cmp_one_dec_min_102_i_9_n_0
    );
temp_cmp_one_dec_min_102_reg: unisim.vcomponents.FDRE
     port map (
      C => pi_f_dec_reg_0,
      CE => '1',
      D => temp_cmp_one_dec_min_101,
      Q => temp_cmp_one_dec_min_102,
      R => '0'
    );
temp_cmp_one_dec_min_102_reg_i_1: unisim.vcomponents.CARRY4
     port map (
      CI => temp_cmp_one_dec_min_102_reg_i_2_n_0,
      CO(3 downto 2) => NLW_temp_cmp_one_dec_min_102_reg_i_1_CO_UNCONNECTED(3 downto 2),
      CO(1) => temp_cmp_one_dec_min_101,
      CO(0) => temp_cmp_one_dec_min_102_reg_i_1_n_3,
      CYINIT => '0',
      DI(3 downto 2) => B"00",
      DI(1) => temp_cmp_one_dec_min_102_i_3_n_0,
      DI(0) => temp_cmp_one_dec_min_102_i_4_n_0,
      O(3 downto 0) => NLW_temp_cmp_one_dec_min_102_reg_i_1_O_UNCONNECTED(3 downto 0),
      S(3 downto 2) => B"00",
      S(1) => temp_cmp_one_dec_min_102_i_5_n_0,
      S(0) => temp_cmp_one_dec_min_102_i_6_n_0
    );
temp_cmp_one_dec_min_102_reg_i_2: unisim.vcomponents.CARRY4
     port map (
      CI => '0',
      CO(3) => temp_cmp_one_dec_min_102_reg_i_2_n_0,
      CO(2) => temp_cmp_one_dec_min_102_reg_i_2_n_1,
      CO(1) => temp_cmp_one_dec_min_102_reg_i_2_n_2,
      CO(0) => temp_cmp_one_dec_min_102_reg_i_2_n_3,
      CYINIT => '0',
      DI(3) => temp_cmp_one_dec_min_102_i_7_n_0,
      DI(2) => temp_cmp_one_dec_min_102_i_8_n_0,
      DI(1) => temp_cmp_one_dec_min_102_i_9_n_0,
      DI(0) => temp_cmp_one_dec_min_102_i_10_n_0,
      O(3 downto 0) => NLW_temp_cmp_one_dec_min_102_reg_i_2_O_UNCONNECTED(3 downto 0),
      S(3) => temp_cmp_one_dec_min_102_i_11_n_0,
      S(2) => temp_cmp_one_dec_min_102_i_12_n_0,
      S(1) => temp_cmp_one_dec_min_102_i_13_n_0,
      S(0) => temp_cmp_one_dec_min_102_i_14_n_0
    );
temp_cmp_one_inc_max_102_i_10: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F02"
    )
        port map (
      I0 => device_temp_101(0),
      I1 => two_dec_max_limit(0),
      I2 => one_inc_max_limit(1),
      I3 => device_temp_101(1),
      O => temp_cmp_one_inc_max_102_i_10_n_0
    );
temp_cmp_one_inc_max_102_i_11: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => device_temp_101(6),
      I1 => one_inc_max_limit(6),
      I2 => device_temp_101(7),
      I3 => one_inc_max_limit(7),
      O => temp_cmp_one_inc_max_102_i_11_n_0
    );
temp_cmp_one_inc_max_102_i_12: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => device_temp_101(4),
      I1 => one_inc_max_limit(4),
      I2 => device_temp_101(5),
      I3 => one_inc_max_limit(5),
      O => temp_cmp_one_inc_max_102_i_12_n_0
    );
temp_cmp_one_inc_max_102_i_13: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => device_temp_101(2),
      I1 => one_inc_max_limit(2),
      I2 => device_temp_101(3),
      I3 => one_inc_max_limit(3),
      O => temp_cmp_one_inc_max_102_i_13_n_0
    );
temp_cmp_one_inc_max_102_i_14: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => device_temp_101(0),
      I1 => two_dec_max_limit(0),
      I2 => device_temp_101(1),
      I3 => one_inc_max_limit(1),
      O => temp_cmp_one_inc_max_102_i_14_n_0
    );
temp_cmp_one_inc_max_102_i_3: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F02"
    )
        port map (
      I0 => device_temp_101(10),
      I1 => one_inc_max_limit(10),
      I2 => one_inc_max_limit(11),
      I3 => device_temp_101(11),
      O => temp_cmp_one_inc_max_102_i_3_n_0
    );
temp_cmp_one_inc_max_102_i_4: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F02"
    )
        port map (
      I0 => device_temp_101(8),
      I1 => one_inc_max_limit(8),
      I2 => one_inc_max_limit(9),
      I3 => device_temp_101(9),
      O => temp_cmp_one_inc_max_102_i_4_n_0
    );
temp_cmp_one_inc_max_102_i_5: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => device_temp_101(10),
      I1 => one_inc_max_limit(10),
      I2 => device_temp_101(11),
      I3 => one_inc_max_limit(11),
      O => temp_cmp_one_inc_max_102_i_5_n_0
    );
temp_cmp_one_inc_max_102_i_6: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => device_temp_101(8),
      I1 => one_inc_max_limit(8),
      I2 => device_temp_101(9),
      I3 => one_inc_max_limit(9),
      O => temp_cmp_one_inc_max_102_i_6_n_0
    );
temp_cmp_one_inc_max_102_i_7: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F02"
    )
        port map (
      I0 => device_temp_101(6),
      I1 => one_inc_max_limit(6),
      I2 => one_inc_max_limit(7),
      I3 => device_temp_101(7),
      O => temp_cmp_one_inc_max_102_i_7_n_0
    );
temp_cmp_one_inc_max_102_i_8: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F02"
    )
        port map (
      I0 => device_temp_101(4),
      I1 => one_inc_max_limit(4),
      I2 => one_inc_max_limit(5),
      I3 => device_temp_101(5),
      O => temp_cmp_one_inc_max_102_i_8_n_0
    );
temp_cmp_one_inc_max_102_i_9: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F02"
    )
        port map (
      I0 => device_temp_101(2),
      I1 => one_inc_max_limit(2),
      I2 => one_inc_max_limit(3),
      I3 => device_temp_101(3),
      O => temp_cmp_one_inc_max_102_i_9_n_0
    );
temp_cmp_one_inc_max_102_reg: unisim.vcomponents.FDRE
     port map (
      C => pi_f_dec_reg_0,
      CE => '1',
      D => temp_cmp_one_inc_max_101,
      Q => temp_cmp_one_inc_max_102,
      R => '0'
    );
temp_cmp_one_inc_max_102_reg_i_1: unisim.vcomponents.CARRY4
     port map (
      CI => temp_cmp_one_inc_max_102_reg_i_2_n_0,
      CO(3 downto 2) => NLW_temp_cmp_one_inc_max_102_reg_i_1_CO_UNCONNECTED(3 downto 2),
      CO(1) => temp_cmp_one_inc_max_101,
      CO(0) => temp_cmp_one_inc_max_102_reg_i_1_n_3,
      CYINIT => '0',
      DI(3 downto 2) => B"00",
      DI(1) => temp_cmp_one_inc_max_102_i_3_n_0,
      DI(0) => temp_cmp_one_inc_max_102_i_4_n_0,
      O(3 downto 0) => NLW_temp_cmp_one_inc_max_102_reg_i_1_O_UNCONNECTED(3 downto 0),
      S(3 downto 2) => B"00",
      S(1) => temp_cmp_one_inc_max_102_i_5_n_0,
      S(0) => temp_cmp_one_inc_max_102_i_6_n_0
    );
temp_cmp_one_inc_max_102_reg_i_2: unisim.vcomponents.CARRY4
     port map (
      CI => '0',
      CO(3) => temp_cmp_one_inc_max_102_reg_i_2_n_0,
      CO(2) => temp_cmp_one_inc_max_102_reg_i_2_n_1,
      CO(1) => temp_cmp_one_inc_max_102_reg_i_2_n_2,
      CO(0) => temp_cmp_one_inc_max_102_reg_i_2_n_3,
      CYINIT => '1',
      DI(3) => temp_cmp_one_inc_max_102_i_7_n_0,
      DI(2) => temp_cmp_one_inc_max_102_i_8_n_0,
      DI(1) => temp_cmp_one_inc_max_102_i_9_n_0,
      DI(0) => temp_cmp_one_inc_max_102_i_10_n_0,
      O(3 downto 0) => NLW_temp_cmp_one_inc_max_102_reg_i_2_O_UNCONNECTED(3 downto 0),
      S(3) => temp_cmp_one_inc_max_102_i_11_n_0,
      S(2) => temp_cmp_one_inc_max_102_i_12_n_0,
      S(1) => temp_cmp_one_inc_max_102_i_13_n_0,
      S(0) => temp_cmp_one_inc_max_102_i_14_n_0
    );
temp_cmp_one_inc_min_102_i_10: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F02"
    )
        port map (
      I0 => three_dec_min_limit(0),
      I1 => device_temp_101(0),
      I2 => device_temp_101(1),
      I3 => one_inc_min_limit(1),
      O => temp_cmp_one_inc_min_102_i_10_n_0
    );
temp_cmp_one_inc_min_102_i_11: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => one_inc_min_limit(6),
      I1 => device_temp_101(6),
      I2 => one_inc_min_limit(7),
      I3 => device_temp_101(7),
      O => temp_cmp_one_inc_min_102_i_11_n_0
    );
temp_cmp_one_inc_min_102_i_12: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => one_inc_min_limit(4),
      I1 => device_temp_101(4),
      I2 => one_inc_min_limit(5),
      I3 => device_temp_101(5),
      O => temp_cmp_one_inc_min_102_i_12_n_0
    );
temp_cmp_one_inc_min_102_i_13: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => one_inc_min_limit(2),
      I1 => device_temp_101(2),
      I2 => one_inc_min_limit(3),
      I3 => device_temp_101(3),
      O => temp_cmp_one_inc_min_102_i_13_n_0
    );
temp_cmp_one_inc_min_102_i_14: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => three_dec_min_limit(0),
      I1 => device_temp_101(0),
      I2 => one_inc_min_limit(1),
      I3 => device_temp_101(1),
      O => temp_cmp_one_inc_min_102_i_14_n_0
    );
temp_cmp_one_inc_min_102_i_3: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F02"
    )
        port map (
      I0 => one_inc_min_limit(10),
      I1 => device_temp_101(10),
      I2 => device_temp_101(11),
      I3 => one_inc_min_limit(11),
      O => temp_cmp_one_inc_min_102_i_3_n_0
    );
temp_cmp_one_inc_min_102_i_4: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F02"
    )
        port map (
      I0 => one_inc_min_limit(8),
      I1 => device_temp_101(8),
      I2 => device_temp_101(9),
      I3 => one_inc_min_limit(9),
      O => temp_cmp_one_inc_min_102_i_4_n_0
    );
temp_cmp_one_inc_min_102_i_5: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => one_inc_min_limit(10),
      I1 => device_temp_101(10),
      I2 => one_inc_min_limit(11),
      I3 => device_temp_101(11),
      O => temp_cmp_one_inc_min_102_i_5_n_0
    );
temp_cmp_one_inc_min_102_i_6: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => one_inc_min_limit(8),
      I1 => device_temp_101(8),
      I2 => one_inc_min_limit(9),
      I3 => device_temp_101(9),
      O => temp_cmp_one_inc_min_102_i_6_n_0
    );
temp_cmp_one_inc_min_102_i_7: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F02"
    )
        port map (
      I0 => one_inc_min_limit(6),
      I1 => device_temp_101(6),
      I2 => device_temp_101(7),
      I3 => one_inc_min_limit(7),
      O => temp_cmp_one_inc_min_102_i_7_n_0
    );
temp_cmp_one_inc_min_102_i_8: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F02"
    )
        port map (
      I0 => one_inc_min_limit(4),
      I1 => device_temp_101(4),
      I2 => device_temp_101(5),
      I3 => one_inc_min_limit(5),
      O => temp_cmp_one_inc_min_102_i_8_n_0
    );
temp_cmp_one_inc_min_102_i_9: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F02"
    )
        port map (
      I0 => one_inc_min_limit(2),
      I1 => device_temp_101(2),
      I2 => device_temp_101(3),
      I3 => one_inc_min_limit(3),
      O => temp_cmp_one_inc_min_102_i_9_n_0
    );
temp_cmp_one_inc_min_102_reg: unisim.vcomponents.FDRE
     port map (
      C => pi_f_dec_reg_0,
      CE => '1',
      D => temp_cmp_one_inc_min_101,
      Q => temp_cmp_one_inc_min_102,
      R => '0'
    );
temp_cmp_one_inc_min_102_reg_i_1: unisim.vcomponents.CARRY4
     port map (
      CI => temp_cmp_one_inc_min_102_reg_i_2_n_0,
      CO(3 downto 2) => NLW_temp_cmp_one_inc_min_102_reg_i_1_CO_UNCONNECTED(3 downto 2),
      CO(1) => temp_cmp_one_inc_min_101,
      CO(0) => temp_cmp_one_inc_min_102_reg_i_1_n_3,
      CYINIT => '0',
      DI(3 downto 2) => B"00",
      DI(1) => temp_cmp_one_inc_min_102_i_3_n_0,
      DI(0) => temp_cmp_one_inc_min_102_i_4_n_0,
      O(3 downto 0) => NLW_temp_cmp_one_inc_min_102_reg_i_1_O_UNCONNECTED(3 downto 0),
      S(3 downto 2) => B"00",
      S(1) => temp_cmp_one_inc_min_102_i_5_n_0,
      S(0) => temp_cmp_one_inc_min_102_i_6_n_0
    );
temp_cmp_one_inc_min_102_reg_i_2: unisim.vcomponents.CARRY4
     port map (
      CI => '0',
      CO(3) => temp_cmp_one_inc_min_102_reg_i_2_n_0,
      CO(2) => temp_cmp_one_inc_min_102_reg_i_2_n_1,
      CO(1) => temp_cmp_one_inc_min_102_reg_i_2_n_2,
      CO(0) => temp_cmp_one_inc_min_102_reg_i_2_n_3,
      CYINIT => '0',
      DI(3) => temp_cmp_one_inc_min_102_i_7_n_0,
      DI(2) => temp_cmp_one_inc_min_102_i_8_n_0,
      DI(1) => temp_cmp_one_inc_min_102_i_9_n_0,
      DI(0) => temp_cmp_one_inc_min_102_i_10_n_0,
      O(3 downto 0) => NLW_temp_cmp_one_inc_min_102_reg_i_2_O_UNCONNECTED(3 downto 0),
      S(3) => temp_cmp_one_inc_min_102_i_11_n_0,
      S(2) => temp_cmp_one_inc_min_102_i_12_n_0,
      S(1) => temp_cmp_one_inc_min_102_i_13_n_0,
      S(0) => temp_cmp_one_inc_min_102_i_14_n_0
    );
temp_cmp_three_dec_max_102_i_10: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F02"
    )
        port map (
      I0 => device_temp_101(0),
      I1 => three_dec_max_limit(0),
      I2 => three_dec_max_limit(1),
      I3 => device_temp_101(1),
      O => temp_cmp_three_dec_max_102_i_10_n_0
    );
temp_cmp_three_dec_max_102_i_11: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => device_temp_101(6),
      I1 => three_dec_max_limit(6),
      I2 => device_temp_101(7),
      I3 => three_dec_max_limit(7),
      O => temp_cmp_three_dec_max_102_i_11_n_0
    );
temp_cmp_three_dec_max_102_i_12: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => device_temp_101(4),
      I1 => three_dec_max_limit(4),
      I2 => device_temp_101(5),
      I3 => three_dec_max_limit(5),
      O => temp_cmp_three_dec_max_102_i_12_n_0
    );
temp_cmp_three_dec_max_102_i_13: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => device_temp_101(2),
      I1 => three_dec_max_limit(2),
      I2 => device_temp_101(3),
      I3 => three_dec_max_limit(3),
      O => temp_cmp_three_dec_max_102_i_13_n_0
    );
temp_cmp_three_dec_max_102_i_14: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => device_temp_101(0),
      I1 => three_dec_max_limit(0),
      I2 => device_temp_101(1),
      I3 => three_dec_max_limit(1),
      O => temp_cmp_three_dec_max_102_i_14_n_0
    );
temp_cmp_three_dec_max_102_i_3: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F02"
    )
        port map (
      I0 => device_temp_101(10),
      I1 => three_dec_max_limit(10),
      I2 => three_dec_max_limit(11),
      I3 => device_temp_101(11),
      O => temp_cmp_three_dec_max_102_i_3_n_0
    );
temp_cmp_three_dec_max_102_i_4: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F02"
    )
        port map (
      I0 => device_temp_101(8),
      I1 => three_dec_max_limit(8),
      I2 => three_dec_max_limit(9),
      I3 => device_temp_101(9),
      O => temp_cmp_three_dec_max_102_i_4_n_0
    );
temp_cmp_three_dec_max_102_i_5: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => device_temp_101(10),
      I1 => three_dec_max_limit(10),
      I2 => device_temp_101(11),
      I3 => three_dec_max_limit(11),
      O => temp_cmp_three_dec_max_102_i_5_n_0
    );
temp_cmp_three_dec_max_102_i_6: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => device_temp_101(8),
      I1 => three_dec_max_limit(8),
      I2 => device_temp_101(9),
      I3 => three_dec_max_limit(9),
      O => temp_cmp_three_dec_max_102_i_6_n_0
    );
temp_cmp_three_dec_max_102_i_7: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F02"
    )
        port map (
      I0 => device_temp_101(6),
      I1 => three_dec_max_limit(6),
      I2 => three_dec_max_limit(7),
      I3 => device_temp_101(7),
      O => temp_cmp_three_dec_max_102_i_7_n_0
    );
temp_cmp_three_dec_max_102_i_8: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F02"
    )
        port map (
      I0 => device_temp_101(4),
      I1 => three_dec_max_limit(4),
      I2 => three_dec_max_limit(5),
      I3 => device_temp_101(5),
      O => temp_cmp_three_dec_max_102_i_8_n_0
    );
temp_cmp_three_dec_max_102_i_9: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F02"
    )
        port map (
      I0 => device_temp_101(2),
      I1 => three_dec_max_limit(2),
      I2 => three_dec_max_limit(3),
      I3 => device_temp_101(3),
      O => temp_cmp_three_dec_max_102_i_9_n_0
    );
temp_cmp_three_dec_max_102_reg: unisim.vcomponents.FDRE
     port map (
      C => pi_f_dec_reg_0,
      CE => '1',
      D => temp_cmp_three_dec_max_101,
      Q => temp_cmp_three_dec_max_102,
      R => '0'
    );
temp_cmp_three_dec_max_102_reg_i_1: unisim.vcomponents.CARRY4
     port map (
      CI => temp_cmp_three_dec_max_102_reg_i_2_n_0,
      CO(3 downto 2) => NLW_temp_cmp_three_dec_max_102_reg_i_1_CO_UNCONNECTED(3 downto 2),
      CO(1) => temp_cmp_three_dec_max_101,
      CO(0) => temp_cmp_three_dec_max_102_reg_i_1_n_3,
      CYINIT => '0',
      DI(3 downto 2) => B"00",
      DI(1) => temp_cmp_three_dec_max_102_i_3_n_0,
      DI(0) => temp_cmp_three_dec_max_102_i_4_n_0,
      O(3 downto 0) => NLW_temp_cmp_three_dec_max_102_reg_i_1_O_UNCONNECTED(3 downto 0),
      S(3 downto 2) => B"00",
      S(1) => temp_cmp_three_dec_max_102_i_5_n_0,
      S(0) => temp_cmp_three_dec_max_102_i_6_n_0
    );
temp_cmp_three_dec_max_102_reg_i_2: unisim.vcomponents.CARRY4
     port map (
      CI => '0',
      CO(3) => temp_cmp_three_dec_max_102_reg_i_2_n_0,
      CO(2) => temp_cmp_three_dec_max_102_reg_i_2_n_1,
      CO(1) => temp_cmp_three_dec_max_102_reg_i_2_n_2,
      CO(0) => temp_cmp_three_dec_max_102_reg_i_2_n_3,
      CYINIT => '1',
      DI(3) => temp_cmp_three_dec_max_102_i_7_n_0,
      DI(2) => temp_cmp_three_dec_max_102_i_8_n_0,
      DI(1) => temp_cmp_three_dec_max_102_i_9_n_0,
      DI(0) => temp_cmp_three_dec_max_102_i_10_n_0,
      O(3 downto 0) => NLW_temp_cmp_three_dec_max_102_reg_i_2_O_UNCONNECTED(3 downto 0),
      S(3) => temp_cmp_three_dec_max_102_i_11_n_0,
      S(2) => temp_cmp_three_dec_max_102_i_12_n_0,
      S(1) => temp_cmp_three_dec_max_102_i_13_n_0,
      S(0) => temp_cmp_three_dec_max_102_i_14_n_0
    );
temp_cmp_three_dec_min_102_i_10: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F02"
    )
        port map (
      I0 => three_dec_min_limit(0),
      I1 => device_temp_101(0),
      I2 => device_temp_101(1),
      I3 => three_dec_min_limit(1),
      O => temp_cmp_three_dec_min_102_i_10_n_0
    );
temp_cmp_three_dec_min_102_i_11: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => three_dec_min_limit(6),
      I1 => device_temp_101(6),
      I2 => three_dec_min_limit(7),
      I3 => device_temp_101(7),
      O => temp_cmp_three_dec_min_102_i_11_n_0
    );
temp_cmp_three_dec_min_102_i_12: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => three_dec_min_limit(4),
      I1 => device_temp_101(4),
      I2 => three_dec_min_limit(5),
      I3 => device_temp_101(5),
      O => temp_cmp_three_dec_min_102_i_12_n_0
    );
temp_cmp_three_dec_min_102_i_13: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => three_dec_min_limit(2),
      I1 => device_temp_101(2),
      I2 => three_dec_min_limit(3),
      I3 => device_temp_101(3),
      O => temp_cmp_three_dec_min_102_i_13_n_0
    );
temp_cmp_three_dec_min_102_i_14: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => three_dec_min_limit(0),
      I1 => device_temp_101(0),
      I2 => three_dec_min_limit(1),
      I3 => device_temp_101(1),
      O => temp_cmp_three_dec_min_102_i_14_n_0
    );
temp_cmp_three_dec_min_102_i_3: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F02"
    )
        port map (
      I0 => three_dec_min_limit(10),
      I1 => device_temp_101(10),
      I2 => device_temp_101(11),
      I3 => three_dec_min_limit(11),
      O => temp_cmp_three_dec_min_102_i_3_n_0
    );
temp_cmp_three_dec_min_102_i_4: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F02"
    )
        port map (
      I0 => three_dec_min_limit(8),
      I1 => device_temp_101(8),
      I2 => device_temp_101(9),
      I3 => three_dec_min_limit(9),
      O => temp_cmp_three_dec_min_102_i_4_n_0
    );
temp_cmp_three_dec_min_102_i_5: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => three_dec_min_limit(10),
      I1 => device_temp_101(10),
      I2 => three_dec_min_limit(11),
      I3 => device_temp_101(11),
      O => temp_cmp_three_dec_min_102_i_5_n_0
    );
temp_cmp_three_dec_min_102_i_6: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => three_dec_min_limit(8),
      I1 => device_temp_101(8),
      I2 => three_dec_min_limit(9),
      I3 => device_temp_101(9),
      O => temp_cmp_three_dec_min_102_i_6_n_0
    );
temp_cmp_three_dec_min_102_i_7: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F02"
    )
        port map (
      I0 => three_dec_min_limit(6),
      I1 => device_temp_101(6),
      I2 => device_temp_101(7),
      I3 => three_dec_min_limit(7),
      O => temp_cmp_three_dec_min_102_i_7_n_0
    );
temp_cmp_three_dec_min_102_i_8: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F02"
    )
        port map (
      I0 => three_dec_min_limit(4),
      I1 => device_temp_101(4),
      I2 => device_temp_101(5),
      I3 => three_dec_min_limit(5),
      O => temp_cmp_three_dec_min_102_i_8_n_0
    );
temp_cmp_three_dec_min_102_i_9: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F02"
    )
        port map (
      I0 => three_dec_min_limit(2),
      I1 => device_temp_101(2),
      I2 => device_temp_101(3),
      I3 => three_dec_min_limit(3),
      O => temp_cmp_three_dec_min_102_i_9_n_0
    );
temp_cmp_three_dec_min_102_reg: unisim.vcomponents.FDRE
     port map (
      C => pi_f_dec_reg_0,
      CE => '1',
      D => temp_cmp_three_dec_min_101,
      Q => temp_cmp_three_dec_min_102,
      R => '0'
    );
temp_cmp_three_dec_min_102_reg_i_1: unisim.vcomponents.CARRY4
     port map (
      CI => temp_cmp_three_dec_min_102_reg_i_2_n_0,
      CO(3 downto 2) => NLW_temp_cmp_three_dec_min_102_reg_i_1_CO_UNCONNECTED(3 downto 2),
      CO(1) => temp_cmp_three_dec_min_101,
      CO(0) => temp_cmp_three_dec_min_102_reg_i_1_n_3,
      CYINIT => '0',
      DI(3 downto 2) => B"00",
      DI(1) => temp_cmp_three_dec_min_102_i_3_n_0,
      DI(0) => temp_cmp_three_dec_min_102_i_4_n_0,
      O(3 downto 0) => NLW_temp_cmp_three_dec_min_102_reg_i_1_O_UNCONNECTED(3 downto 0),
      S(3 downto 2) => B"00",
      S(1) => temp_cmp_three_dec_min_102_i_5_n_0,
      S(0) => temp_cmp_three_dec_min_102_i_6_n_0
    );
temp_cmp_three_dec_min_102_reg_i_2: unisim.vcomponents.CARRY4
     port map (
      CI => '0',
      CO(3) => temp_cmp_three_dec_min_102_reg_i_2_n_0,
      CO(2) => temp_cmp_three_dec_min_102_reg_i_2_n_1,
      CO(1) => temp_cmp_three_dec_min_102_reg_i_2_n_2,
      CO(0) => temp_cmp_three_dec_min_102_reg_i_2_n_3,
      CYINIT => '0',
      DI(3) => temp_cmp_three_dec_min_102_i_7_n_0,
      DI(2) => temp_cmp_three_dec_min_102_i_8_n_0,
      DI(1) => temp_cmp_three_dec_min_102_i_9_n_0,
      DI(0) => temp_cmp_three_dec_min_102_i_10_n_0,
      O(3 downto 0) => NLW_temp_cmp_three_dec_min_102_reg_i_2_O_UNCONNECTED(3 downto 0),
      S(3) => temp_cmp_three_dec_min_102_i_11_n_0,
      S(2) => temp_cmp_three_dec_min_102_i_12_n_0,
      S(1) => temp_cmp_three_dec_min_102_i_13_n_0,
      S(0) => temp_cmp_three_dec_min_102_i_14_n_0
    );
temp_cmp_three_inc_max_102_i_10: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F02"
    )
        port map (
      I0 => device_temp_101(0),
      I1 => two_dec_max_limit(0),
      I2 => one_inc_max_limit(1),
      I3 => device_temp_101(1),
      O => temp_cmp_three_inc_max_102_i_10_n_0
    );
temp_cmp_three_inc_max_102_i_11: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => device_temp_101(6),
      I1 => three_inc_max_limit(6),
      I2 => device_temp_101(7),
      I3 => three_inc_max_limit(7),
      O => temp_cmp_three_inc_max_102_i_11_n_0
    );
temp_cmp_three_inc_max_102_i_12: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => device_temp_101(4),
      I1 => three_inc_max_limit(4),
      I2 => device_temp_101(5),
      I3 => three_inc_max_limit(5),
      O => temp_cmp_three_inc_max_102_i_12_n_0
    );
temp_cmp_three_inc_max_102_i_13: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => device_temp_101(2),
      I1 => three_inc_max_limit(2),
      I2 => device_temp_101(3),
      I3 => three_inc_max_limit(3),
      O => temp_cmp_three_inc_max_102_i_13_n_0
    );
temp_cmp_three_inc_max_102_i_14: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => device_temp_101(0),
      I1 => two_dec_max_limit(0),
      I2 => device_temp_101(1),
      I3 => one_inc_max_limit(1),
      O => temp_cmp_three_inc_max_102_i_14_n_0
    );
temp_cmp_three_inc_max_102_i_3: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F02"
    )
        port map (
      I0 => device_temp_101(10),
      I1 => three_inc_max_limit(10),
      I2 => three_inc_max_limit(11),
      I3 => device_temp_101(11),
      O => temp_cmp_three_inc_max_102_i_3_n_0
    );
temp_cmp_three_inc_max_102_i_4: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F02"
    )
        port map (
      I0 => device_temp_101(8),
      I1 => three_inc_max_limit(8),
      I2 => three_inc_max_limit(9),
      I3 => device_temp_101(9),
      O => temp_cmp_three_inc_max_102_i_4_n_0
    );
temp_cmp_three_inc_max_102_i_5: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => device_temp_101(10),
      I1 => three_inc_max_limit(10),
      I2 => device_temp_101(11),
      I3 => three_inc_max_limit(11),
      O => temp_cmp_three_inc_max_102_i_5_n_0
    );
temp_cmp_three_inc_max_102_i_6: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => device_temp_101(8),
      I1 => three_inc_max_limit(8),
      I2 => device_temp_101(9),
      I3 => three_inc_max_limit(9),
      O => temp_cmp_three_inc_max_102_i_6_n_0
    );
temp_cmp_three_inc_max_102_i_7: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F02"
    )
        port map (
      I0 => device_temp_101(6),
      I1 => three_inc_max_limit(6),
      I2 => three_inc_max_limit(7),
      I3 => device_temp_101(7),
      O => temp_cmp_three_inc_max_102_i_7_n_0
    );
temp_cmp_three_inc_max_102_i_8: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F02"
    )
        port map (
      I0 => device_temp_101(4),
      I1 => three_inc_max_limit(4),
      I2 => three_inc_max_limit(5),
      I3 => device_temp_101(5),
      O => temp_cmp_three_inc_max_102_i_8_n_0
    );
temp_cmp_three_inc_max_102_i_9: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F02"
    )
        port map (
      I0 => device_temp_101(2),
      I1 => three_inc_max_limit(2),
      I2 => three_inc_max_limit(3),
      I3 => device_temp_101(3),
      O => temp_cmp_three_inc_max_102_i_9_n_0
    );
temp_cmp_three_inc_max_102_reg: unisim.vcomponents.FDRE
     port map (
      C => pi_f_dec_reg_0,
      CE => '1',
      D => temp_cmp_three_inc_max_101,
      Q => temp_cmp_three_inc_max_102,
      R => '0'
    );
temp_cmp_three_inc_max_102_reg_i_1: unisim.vcomponents.CARRY4
     port map (
      CI => temp_cmp_three_inc_max_102_reg_i_2_n_0,
      CO(3 downto 2) => NLW_temp_cmp_three_inc_max_102_reg_i_1_CO_UNCONNECTED(3 downto 2),
      CO(1) => temp_cmp_three_inc_max_101,
      CO(0) => temp_cmp_three_inc_max_102_reg_i_1_n_3,
      CYINIT => '0',
      DI(3 downto 2) => B"00",
      DI(1) => temp_cmp_three_inc_max_102_i_3_n_0,
      DI(0) => temp_cmp_three_inc_max_102_i_4_n_0,
      O(3 downto 0) => NLW_temp_cmp_three_inc_max_102_reg_i_1_O_UNCONNECTED(3 downto 0),
      S(3 downto 2) => B"00",
      S(1) => temp_cmp_three_inc_max_102_i_5_n_0,
      S(0) => temp_cmp_three_inc_max_102_i_6_n_0
    );
temp_cmp_three_inc_max_102_reg_i_2: unisim.vcomponents.CARRY4
     port map (
      CI => '0',
      CO(3) => temp_cmp_three_inc_max_102_reg_i_2_n_0,
      CO(2) => temp_cmp_three_inc_max_102_reg_i_2_n_1,
      CO(1) => temp_cmp_three_inc_max_102_reg_i_2_n_2,
      CO(0) => temp_cmp_three_inc_max_102_reg_i_2_n_3,
      CYINIT => '1',
      DI(3) => temp_cmp_three_inc_max_102_i_7_n_0,
      DI(2) => temp_cmp_three_inc_max_102_i_8_n_0,
      DI(1) => temp_cmp_three_inc_max_102_i_9_n_0,
      DI(0) => temp_cmp_three_inc_max_102_i_10_n_0,
      O(3 downto 0) => NLW_temp_cmp_three_inc_max_102_reg_i_2_O_UNCONNECTED(3 downto 0),
      S(3) => temp_cmp_three_inc_max_102_i_11_n_0,
      S(2) => temp_cmp_three_inc_max_102_i_12_n_0,
      S(1) => temp_cmp_three_inc_max_102_i_13_n_0,
      S(0) => temp_cmp_three_inc_max_102_i_14_n_0
    );
temp_cmp_three_inc_min_102_i_10: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F02"
    )
        port map (
      I0 => three_dec_min_limit(0),
      I1 => device_temp_101(0),
      I2 => device_temp_101(1),
      I3 => one_inc_min_limit(1),
      O => temp_cmp_three_inc_min_102_i_10_n_0
    );
temp_cmp_three_inc_min_102_i_11: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => three_inc_min_limit(6),
      I1 => device_temp_101(6),
      I2 => three_inc_min_limit(7),
      I3 => device_temp_101(7),
      O => temp_cmp_three_inc_min_102_i_11_n_0
    );
temp_cmp_three_inc_min_102_i_12: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => three_inc_min_limit(4),
      I1 => device_temp_101(4),
      I2 => three_inc_min_limit(5),
      I3 => device_temp_101(5),
      O => temp_cmp_three_inc_min_102_i_12_n_0
    );
temp_cmp_three_inc_min_102_i_13: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => three_inc_min_limit(2),
      I1 => device_temp_101(2),
      I2 => three_inc_min_limit(3),
      I3 => device_temp_101(3),
      O => temp_cmp_three_inc_min_102_i_13_n_0
    );
temp_cmp_three_inc_min_102_i_14: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => three_dec_min_limit(0),
      I1 => device_temp_101(0),
      I2 => one_inc_min_limit(1),
      I3 => device_temp_101(1),
      O => temp_cmp_three_inc_min_102_i_14_n_0
    );
temp_cmp_three_inc_min_102_i_3: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F02"
    )
        port map (
      I0 => three_inc_min_limit(10),
      I1 => device_temp_101(10),
      I2 => device_temp_101(11),
      I3 => three_inc_min_limit(11),
      O => temp_cmp_three_inc_min_102_i_3_n_0
    );
temp_cmp_three_inc_min_102_i_4: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F02"
    )
        port map (
      I0 => three_inc_min_limit(8),
      I1 => device_temp_101(8),
      I2 => device_temp_101(9),
      I3 => three_inc_min_limit(9),
      O => temp_cmp_three_inc_min_102_i_4_n_0
    );
temp_cmp_three_inc_min_102_i_5: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => three_inc_min_limit(10),
      I1 => device_temp_101(10),
      I2 => three_inc_min_limit(11),
      I3 => device_temp_101(11),
      O => temp_cmp_three_inc_min_102_i_5_n_0
    );
temp_cmp_three_inc_min_102_i_6: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => three_inc_min_limit(8),
      I1 => device_temp_101(8),
      I2 => three_inc_min_limit(9),
      I3 => device_temp_101(9),
      O => temp_cmp_three_inc_min_102_i_6_n_0
    );
temp_cmp_three_inc_min_102_i_7: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F02"
    )
        port map (
      I0 => three_inc_min_limit(6),
      I1 => device_temp_101(6),
      I2 => device_temp_101(7),
      I3 => three_inc_min_limit(7),
      O => temp_cmp_three_inc_min_102_i_7_n_0
    );
temp_cmp_three_inc_min_102_i_8: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F02"
    )
        port map (
      I0 => three_inc_min_limit(4),
      I1 => device_temp_101(4),
      I2 => device_temp_101(5),
      I3 => three_inc_min_limit(5),
      O => temp_cmp_three_inc_min_102_i_8_n_0
    );
temp_cmp_three_inc_min_102_i_9: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F02"
    )
        port map (
      I0 => three_inc_min_limit(2),
      I1 => device_temp_101(2),
      I2 => device_temp_101(3),
      I3 => three_inc_min_limit(3),
      O => temp_cmp_three_inc_min_102_i_9_n_0
    );
temp_cmp_three_inc_min_102_reg: unisim.vcomponents.FDRE
     port map (
      C => pi_f_dec_reg_0,
      CE => '1',
      D => temp_cmp_three_inc_min_101,
      Q => temp_cmp_three_inc_min_102,
      R => '0'
    );
temp_cmp_three_inc_min_102_reg_i_1: unisim.vcomponents.CARRY4
     port map (
      CI => temp_cmp_three_inc_min_102_reg_i_2_n_0,
      CO(3 downto 2) => NLW_temp_cmp_three_inc_min_102_reg_i_1_CO_UNCONNECTED(3 downto 2),
      CO(1) => temp_cmp_three_inc_min_101,
      CO(0) => temp_cmp_three_inc_min_102_reg_i_1_n_3,
      CYINIT => '0',
      DI(3 downto 2) => B"00",
      DI(1) => temp_cmp_three_inc_min_102_i_3_n_0,
      DI(0) => temp_cmp_three_inc_min_102_i_4_n_0,
      O(3 downto 0) => NLW_temp_cmp_three_inc_min_102_reg_i_1_O_UNCONNECTED(3 downto 0),
      S(3 downto 2) => B"00",
      S(1) => temp_cmp_three_inc_min_102_i_5_n_0,
      S(0) => temp_cmp_three_inc_min_102_i_6_n_0
    );
temp_cmp_three_inc_min_102_reg_i_2: unisim.vcomponents.CARRY4
     port map (
      CI => '0',
      CO(3) => temp_cmp_three_inc_min_102_reg_i_2_n_0,
      CO(2) => temp_cmp_three_inc_min_102_reg_i_2_n_1,
      CO(1) => temp_cmp_three_inc_min_102_reg_i_2_n_2,
      CO(0) => temp_cmp_three_inc_min_102_reg_i_2_n_3,
      CYINIT => '0',
      DI(3) => temp_cmp_three_inc_min_102_i_7_n_0,
      DI(2) => temp_cmp_three_inc_min_102_i_8_n_0,
      DI(1) => temp_cmp_three_inc_min_102_i_9_n_0,
      DI(0) => temp_cmp_three_inc_min_102_i_10_n_0,
      O(3 downto 0) => NLW_temp_cmp_three_inc_min_102_reg_i_2_O_UNCONNECTED(3 downto 0),
      S(3) => temp_cmp_three_inc_min_102_i_11_n_0,
      S(2) => temp_cmp_three_inc_min_102_i_12_n_0,
      S(1) => temp_cmp_three_inc_min_102_i_13_n_0,
      S(0) => temp_cmp_three_inc_min_102_i_14_n_0
    );
temp_cmp_two_dec_max_102_i_10: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F02"
    )
        port map (
      I0 => device_temp_101(0),
      I1 => two_dec_max_limit(0),
      I2 => two_dec_max_limit(1),
      I3 => device_temp_101(1),
      O => temp_cmp_two_dec_max_102_i_10_n_0
    );
temp_cmp_two_dec_max_102_i_11: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => device_temp_101(6),
      I1 => two_dec_max_limit(6),
      I2 => device_temp_101(7),
      I3 => two_dec_max_limit(7),
      O => temp_cmp_two_dec_max_102_i_11_n_0
    );
temp_cmp_two_dec_max_102_i_12: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => device_temp_101(4),
      I1 => two_dec_max_limit(4),
      I2 => device_temp_101(5),
      I3 => two_dec_max_limit(5),
      O => temp_cmp_two_dec_max_102_i_12_n_0
    );
temp_cmp_two_dec_max_102_i_13: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => device_temp_101(2),
      I1 => two_dec_max_limit(2),
      I2 => device_temp_101(3),
      I3 => two_dec_max_limit(3),
      O => temp_cmp_two_dec_max_102_i_13_n_0
    );
temp_cmp_two_dec_max_102_i_14: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => device_temp_101(0),
      I1 => two_dec_max_limit(0),
      I2 => device_temp_101(1),
      I3 => two_dec_max_limit(1),
      O => temp_cmp_two_dec_max_102_i_14_n_0
    );
temp_cmp_two_dec_max_102_i_3: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F02"
    )
        port map (
      I0 => device_temp_101(10),
      I1 => two_dec_max_limit(10),
      I2 => two_dec_max_limit(11),
      I3 => device_temp_101(11),
      O => temp_cmp_two_dec_max_102_i_3_n_0
    );
temp_cmp_two_dec_max_102_i_4: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F02"
    )
        port map (
      I0 => device_temp_101(8),
      I1 => two_dec_max_limit(8),
      I2 => two_dec_max_limit(9),
      I3 => device_temp_101(9),
      O => temp_cmp_two_dec_max_102_i_4_n_0
    );
temp_cmp_two_dec_max_102_i_5: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => device_temp_101(10),
      I1 => two_dec_max_limit(10),
      I2 => device_temp_101(11),
      I3 => two_dec_max_limit(11),
      O => temp_cmp_two_dec_max_102_i_5_n_0
    );
temp_cmp_two_dec_max_102_i_6: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => device_temp_101(8),
      I1 => two_dec_max_limit(8),
      I2 => device_temp_101(9),
      I3 => two_dec_max_limit(9),
      O => temp_cmp_two_dec_max_102_i_6_n_0
    );
temp_cmp_two_dec_max_102_i_7: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F02"
    )
        port map (
      I0 => device_temp_101(6),
      I1 => two_dec_max_limit(6),
      I2 => two_dec_max_limit(7),
      I3 => device_temp_101(7),
      O => temp_cmp_two_dec_max_102_i_7_n_0
    );
temp_cmp_two_dec_max_102_i_8: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F02"
    )
        port map (
      I0 => device_temp_101(4),
      I1 => two_dec_max_limit(4),
      I2 => two_dec_max_limit(5),
      I3 => device_temp_101(5),
      O => temp_cmp_two_dec_max_102_i_8_n_0
    );
temp_cmp_two_dec_max_102_i_9: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F02"
    )
        port map (
      I0 => device_temp_101(2),
      I1 => two_dec_max_limit(2),
      I2 => two_dec_max_limit(3),
      I3 => device_temp_101(3),
      O => temp_cmp_two_dec_max_102_i_9_n_0
    );
temp_cmp_two_dec_max_102_reg: unisim.vcomponents.FDRE
     port map (
      C => pi_f_dec_reg_0,
      CE => '1',
      D => temp_cmp_two_dec_max_101,
      Q => temp_cmp_two_dec_max_102,
      R => '0'
    );
temp_cmp_two_dec_max_102_reg_i_1: unisim.vcomponents.CARRY4
     port map (
      CI => temp_cmp_two_dec_max_102_reg_i_2_n_0,
      CO(3 downto 2) => NLW_temp_cmp_two_dec_max_102_reg_i_1_CO_UNCONNECTED(3 downto 2),
      CO(1) => temp_cmp_two_dec_max_101,
      CO(0) => temp_cmp_two_dec_max_102_reg_i_1_n_3,
      CYINIT => '0',
      DI(3 downto 2) => B"00",
      DI(1) => temp_cmp_two_dec_max_102_i_3_n_0,
      DI(0) => temp_cmp_two_dec_max_102_i_4_n_0,
      O(3 downto 0) => NLW_temp_cmp_two_dec_max_102_reg_i_1_O_UNCONNECTED(3 downto 0),
      S(3 downto 2) => B"00",
      S(1) => temp_cmp_two_dec_max_102_i_5_n_0,
      S(0) => temp_cmp_two_dec_max_102_i_6_n_0
    );
temp_cmp_two_dec_max_102_reg_i_2: unisim.vcomponents.CARRY4
     port map (
      CI => '0',
      CO(3) => temp_cmp_two_dec_max_102_reg_i_2_n_0,
      CO(2) => temp_cmp_two_dec_max_102_reg_i_2_n_1,
      CO(1) => temp_cmp_two_dec_max_102_reg_i_2_n_2,
      CO(0) => temp_cmp_two_dec_max_102_reg_i_2_n_3,
      CYINIT => '1',
      DI(3) => temp_cmp_two_dec_max_102_i_7_n_0,
      DI(2) => temp_cmp_two_dec_max_102_i_8_n_0,
      DI(1) => temp_cmp_two_dec_max_102_i_9_n_0,
      DI(0) => temp_cmp_two_dec_max_102_i_10_n_0,
      O(3 downto 0) => NLW_temp_cmp_two_dec_max_102_reg_i_2_O_UNCONNECTED(3 downto 0),
      S(3) => temp_cmp_two_dec_max_102_i_11_n_0,
      S(2) => temp_cmp_two_dec_max_102_i_12_n_0,
      S(1) => temp_cmp_two_dec_max_102_i_13_n_0,
      S(0) => temp_cmp_two_dec_max_102_i_14_n_0
    );
temp_cmp_two_dec_min_102_i_10: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F02"
    )
        port map (
      I0 => three_dec_min_limit(0),
      I1 => device_temp_101(0),
      I2 => device_temp_101(1),
      I3 => two_inc_min_limit(1),
      O => temp_cmp_two_dec_min_102_i_10_n_0
    );
temp_cmp_two_dec_min_102_i_11: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => two_dec_min_limit(6),
      I1 => device_temp_101(6),
      I2 => two_dec_min_limit(7),
      I3 => device_temp_101(7),
      O => temp_cmp_two_dec_min_102_i_11_n_0
    );
temp_cmp_two_dec_min_102_i_12: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => two_dec_min_limit(4),
      I1 => device_temp_101(4),
      I2 => two_dec_min_limit(5),
      I3 => device_temp_101(5),
      O => temp_cmp_two_dec_min_102_i_12_n_0
    );
temp_cmp_two_dec_min_102_i_13: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => two_dec_min_limit(2),
      I1 => device_temp_101(2),
      I2 => two_dec_min_limit(3),
      I3 => device_temp_101(3),
      O => temp_cmp_two_dec_min_102_i_13_n_0
    );
temp_cmp_two_dec_min_102_i_14: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => three_dec_min_limit(0),
      I1 => device_temp_101(0),
      I2 => two_inc_min_limit(1),
      I3 => device_temp_101(1),
      O => temp_cmp_two_dec_min_102_i_14_n_0
    );
temp_cmp_two_dec_min_102_i_3: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F02"
    )
        port map (
      I0 => two_dec_min_limit(10),
      I1 => device_temp_101(10),
      I2 => device_temp_101(11),
      I3 => two_dec_min_limit(11),
      O => temp_cmp_two_dec_min_102_i_3_n_0
    );
temp_cmp_two_dec_min_102_i_4: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F02"
    )
        port map (
      I0 => two_dec_min_limit(8),
      I1 => device_temp_101(8),
      I2 => device_temp_101(9),
      I3 => two_dec_min_limit(9),
      O => temp_cmp_two_dec_min_102_i_4_n_0
    );
temp_cmp_two_dec_min_102_i_5: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => two_dec_min_limit(10),
      I1 => device_temp_101(10),
      I2 => two_dec_min_limit(11),
      I3 => device_temp_101(11),
      O => temp_cmp_two_dec_min_102_i_5_n_0
    );
temp_cmp_two_dec_min_102_i_6: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => two_dec_min_limit(8),
      I1 => device_temp_101(8),
      I2 => two_dec_min_limit(9),
      I3 => device_temp_101(9),
      O => temp_cmp_two_dec_min_102_i_6_n_0
    );
temp_cmp_two_dec_min_102_i_7: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F02"
    )
        port map (
      I0 => two_dec_min_limit(6),
      I1 => device_temp_101(6),
      I2 => device_temp_101(7),
      I3 => two_dec_min_limit(7),
      O => temp_cmp_two_dec_min_102_i_7_n_0
    );
temp_cmp_two_dec_min_102_i_8: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F02"
    )
        port map (
      I0 => two_dec_min_limit(4),
      I1 => device_temp_101(4),
      I2 => device_temp_101(5),
      I3 => two_dec_min_limit(5),
      O => temp_cmp_two_dec_min_102_i_8_n_0
    );
temp_cmp_two_dec_min_102_i_9: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F02"
    )
        port map (
      I0 => two_dec_min_limit(2),
      I1 => device_temp_101(2),
      I2 => device_temp_101(3),
      I3 => two_dec_min_limit(3),
      O => temp_cmp_two_dec_min_102_i_9_n_0
    );
temp_cmp_two_dec_min_102_reg: unisim.vcomponents.FDRE
     port map (
      C => pi_f_dec_reg_0,
      CE => '1',
      D => temp_cmp_two_dec_min_101,
      Q => temp_cmp_two_dec_min_102,
      R => '0'
    );
temp_cmp_two_dec_min_102_reg_i_1: unisim.vcomponents.CARRY4
     port map (
      CI => temp_cmp_two_dec_min_102_reg_i_2_n_0,
      CO(3 downto 2) => NLW_temp_cmp_two_dec_min_102_reg_i_1_CO_UNCONNECTED(3 downto 2),
      CO(1) => temp_cmp_two_dec_min_101,
      CO(0) => temp_cmp_two_dec_min_102_reg_i_1_n_3,
      CYINIT => '0',
      DI(3 downto 2) => B"00",
      DI(1) => temp_cmp_two_dec_min_102_i_3_n_0,
      DI(0) => temp_cmp_two_dec_min_102_i_4_n_0,
      O(3 downto 0) => NLW_temp_cmp_two_dec_min_102_reg_i_1_O_UNCONNECTED(3 downto 0),
      S(3 downto 2) => B"00",
      S(1) => temp_cmp_two_dec_min_102_i_5_n_0,
      S(0) => temp_cmp_two_dec_min_102_i_6_n_0
    );
temp_cmp_two_dec_min_102_reg_i_2: unisim.vcomponents.CARRY4
     port map (
      CI => '0',
      CO(3) => temp_cmp_two_dec_min_102_reg_i_2_n_0,
      CO(2) => temp_cmp_two_dec_min_102_reg_i_2_n_1,
      CO(1) => temp_cmp_two_dec_min_102_reg_i_2_n_2,
      CO(0) => temp_cmp_two_dec_min_102_reg_i_2_n_3,
      CYINIT => '0',
      DI(3) => temp_cmp_two_dec_min_102_i_7_n_0,
      DI(2) => temp_cmp_two_dec_min_102_i_8_n_0,
      DI(1) => temp_cmp_two_dec_min_102_i_9_n_0,
      DI(0) => temp_cmp_two_dec_min_102_i_10_n_0,
      O(3 downto 0) => NLW_temp_cmp_two_dec_min_102_reg_i_2_O_UNCONNECTED(3 downto 0),
      S(3) => temp_cmp_two_dec_min_102_i_11_n_0,
      S(2) => temp_cmp_two_dec_min_102_i_12_n_0,
      S(1) => temp_cmp_two_dec_min_102_i_13_n_0,
      S(0) => temp_cmp_two_dec_min_102_i_14_n_0
    );
temp_cmp_two_inc_max_102_i_10: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F02"
    )
        port map (
      I0 => device_temp_101(0),
      I1 => two_dec_max_limit(0),
      I2 => two_inc_max_limit(1),
      I3 => device_temp_101(1),
      O => temp_cmp_two_inc_max_102_i_10_n_0
    );
temp_cmp_two_inc_max_102_i_11: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => device_temp_101(6),
      I1 => two_inc_max_limit(6),
      I2 => device_temp_101(7),
      I3 => two_inc_max_limit(7),
      O => temp_cmp_two_inc_max_102_i_11_n_0
    );
temp_cmp_two_inc_max_102_i_12: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => device_temp_101(4),
      I1 => two_inc_max_limit(4),
      I2 => device_temp_101(5),
      I3 => two_inc_max_limit(5),
      O => temp_cmp_two_inc_max_102_i_12_n_0
    );
temp_cmp_two_inc_max_102_i_13: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => device_temp_101(2),
      I1 => two_inc_max_limit(2),
      I2 => device_temp_101(3),
      I3 => two_inc_max_limit(3),
      O => temp_cmp_two_inc_max_102_i_13_n_0
    );
temp_cmp_two_inc_max_102_i_14: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => device_temp_101(0),
      I1 => two_dec_max_limit(0),
      I2 => device_temp_101(1),
      I3 => two_inc_max_limit(1),
      O => temp_cmp_two_inc_max_102_i_14_n_0
    );
temp_cmp_two_inc_max_102_i_3: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F02"
    )
        port map (
      I0 => device_temp_101(10),
      I1 => two_inc_max_limit(10),
      I2 => two_inc_max_limit(11),
      I3 => device_temp_101(11),
      O => temp_cmp_two_inc_max_102_i_3_n_0
    );
temp_cmp_two_inc_max_102_i_4: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F02"
    )
        port map (
      I0 => device_temp_101(8),
      I1 => two_inc_max_limit(8),
      I2 => two_inc_max_limit(9),
      I3 => device_temp_101(9),
      O => temp_cmp_two_inc_max_102_i_4_n_0
    );
temp_cmp_two_inc_max_102_i_5: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => device_temp_101(10),
      I1 => two_inc_max_limit(10),
      I2 => device_temp_101(11),
      I3 => two_inc_max_limit(11),
      O => temp_cmp_two_inc_max_102_i_5_n_0
    );
temp_cmp_two_inc_max_102_i_6: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => device_temp_101(8),
      I1 => two_inc_max_limit(8),
      I2 => device_temp_101(9),
      I3 => two_inc_max_limit(9),
      O => temp_cmp_two_inc_max_102_i_6_n_0
    );
temp_cmp_two_inc_max_102_i_7: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F02"
    )
        port map (
      I0 => device_temp_101(6),
      I1 => two_inc_max_limit(6),
      I2 => two_inc_max_limit(7),
      I3 => device_temp_101(7),
      O => temp_cmp_two_inc_max_102_i_7_n_0
    );
temp_cmp_two_inc_max_102_i_8: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F02"
    )
        port map (
      I0 => device_temp_101(4),
      I1 => two_inc_max_limit(4),
      I2 => two_inc_max_limit(5),
      I3 => device_temp_101(5),
      O => temp_cmp_two_inc_max_102_i_8_n_0
    );
temp_cmp_two_inc_max_102_i_9: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F02"
    )
        port map (
      I0 => device_temp_101(2),
      I1 => two_inc_max_limit(2),
      I2 => two_inc_max_limit(3),
      I3 => device_temp_101(3),
      O => temp_cmp_two_inc_max_102_i_9_n_0
    );
temp_cmp_two_inc_max_102_reg: unisim.vcomponents.FDRE
     port map (
      C => pi_f_dec_reg_0,
      CE => '1',
      D => temp_cmp_two_inc_max_101,
      Q => temp_cmp_two_inc_max_102,
      R => '0'
    );
temp_cmp_two_inc_max_102_reg_i_1: unisim.vcomponents.CARRY4
     port map (
      CI => temp_cmp_two_inc_max_102_reg_i_2_n_0,
      CO(3 downto 2) => NLW_temp_cmp_two_inc_max_102_reg_i_1_CO_UNCONNECTED(3 downto 2),
      CO(1) => temp_cmp_two_inc_max_101,
      CO(0) => temp_cmp_two_inc_max_102_reg_i_1_n_3,
      CYINIT => '0',
      DI(3 downto 2) => B"00",
      DI(1) => temp_cmp_two_inc_max_102_i_3_n_0,
      DI(0) => temp_cmp_two_inc_max_102_i_4_n_0,
      O(3 downto 0) => NLW_temp_cmp_two_inc_max_102_reg_i_1_O_UNCONNECTED(3 downto 0),
      S(3 downto 2) => B"00",
      S(1) => temp_cmp_two_inc_max_102_i_5_n_0,
      S(0) => temp_cmp_two_inc_max_102_i_6_n_0
    );
temp_cmp_two_inc_max_102_reg_i_2: unisim.vcomponents.CARRY4
     port map (
      CI => '0',
      CO(3) => temp_cmp_two_inc_max_102_reg_i_2_n_0,
      CO(2) => temp_cmp_two_inc_max_102_reg_i_2_n_1,
      CO(1) => temp_cmp_two_inc_max_102_reg_i_2_n_2,
      CO(0) => temp_cmp_two_inc_max_102_reg_i_2_n_3,
      CYINIT => '1',
      DI(3) => temp_cmp_two_inc_max_102_i_7_n_0,
      DI(2) => temp_cmp_two_inc_max_102_i_8_n_0,
      DI(1) => temp_cmp_two_inc_max_102_i_9_n_0,
      DI(0) => temp_cmp_two_inc_max_102_i_10_n_0,
      O(3 downto 0) => NLW_temp_cmp_two_inc_max_102_reg_i_2_O_UNCONNECTED(3 downto 0),
      S(3) => temp_cmp_two_inc_max_102_i_11_n_0,
      S(2) => temp_cmp_two_inc_max_102_i_12_n_0,
      S(1) => temp_cmp_two_inc_max_102_i_13_n_0,
      S(0) => temp_cmp_two_inc_max_102_i_14_n_0
    );
temp_cmp_two_inc_min_102_i_10: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F02"
    )
        port map (
      I0 => three_dec_min_limit(0),
      I1 => device_temp_101(0),
      I2 => device_temp_101(1),
      I3 => two_inc_min_limit(1),
      O => temp_cmp_two_inc_min_102_i_10_n_0
    );
temp_cmp_two_inc_min_102_i_11: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => two_inc_min_limit(6),
      I1 => device_temp_101(6),
      I2 => two_inc_min_limit(7),
      I3 => device_temp_101(7),
      O => temp_cmp_two_inc_min_102_i_11_n_0
    );
temp_cmp_two_inc_min_102_i_12: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => two_inc_min_limit(4),
      I1 => device_temp_101(4),
      I2 => two_inc_min_limit(5),
      I3 => device_temp_101(5),
      O => temp_cmp_two_inc_min_102_i_12_n_0
    );
temp_cmp_two_inc_min_102_i_13: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => two_inc_min_limit(2),
      I1 => device_temp_101(2),
      I2 => two_inc_min_limit(3),
      I3 => device_temp_101(3),
      O => temp_cmp_two_inc_min_102_i_13_n_0
    );
temp_cmp_two_inc_min_102_i_14: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => three_dec_min_limit(0),
      I1 => device_temp_101(0),
      I2 => two_inc_min_limit(1),
      I3 => device_temp_101(1),
      O => temp_cmp_two_inc_min_102_i_14_n_0
    );
temp_cmp_two_inc_min_102_i_3: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F02"
    )
        port map (
      I0 => two_inc_min_limit(10),
      I1 => device_temp_101(10),
      I2 => device_temp_101(11),
      I3 => two_inc_min_limit(11),
      O => temp_cmp_two_inc_min_102_i_3_n_0
    );
temp_cmp_two_inc_min_102_i_4: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F02"
    )
        port map (
      I0 => two_inc_min_limit(8),
      I1 => device_temp_101(8),
      I2 => device_temp_101(9),
      I3 => two_inc_min_limit(9),
      O => temp_cmp_two_inc_min_102_i_4_n_0
    );
temp_cmp_two_inc_min_102_i_5: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => two_inc_min_limit(10),
      I1 => device_temp_101(10),
      I2 => two_inc_min_limit(11),
      I3 => device_temp_101(11),
      O => temp_cmp_two_inc_min_102_i_5_n_0
    );
temp_cmp_two_inc_min_102_i_6: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => two_inc_min_limit(8),
      I1 => device_temp_101(8),
      I2 => two_inc_min_limit(9),
      I3 => device_temp_101(9),
      O => temp_cmp_two_inc_min_102_i_6_n_0
    );
temp_cmp_two_inc_min_102_i_7: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F02"
    )
        port map (
      I0 => two_inc_min_limit(6),
      I1 => device_temp_101(6),
      I2 => device_temp_101(7),
      I3 => two_inc_min_limit(7),
      O => temp_cmp_two_inc_min_102_i_7_n_0
    );
temp_cmp_two_inc_min_102_i_8: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F02"
    )
        port map (
      I0 => two_inc_min_limit(4),
      I1 => device_temp_101(4),
      I2 => device_temp_101(5),
      I3 => two_inc_min_limit(5),
      O => temp_cmp_two_inc_min_102_i_8_n_0
    );
temp_cmp_two_inc_min_102_i_9: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F02"
    )
        port map (
      I0 => two_inc_min_limit(2),
      I1 => device_temp_101(2),
      I2 => device_temp_101(3),
      I3 => two_inc_min_limit(3),
      O => temp_cmp_two_inc_min_102_i_9_n_0
    );
temp_cmp_two_inc_min_102_reg: unisim.vcomponents.FDRE
     port map (
      C => pi_f_dec_reg_0,
      CE => '1',
      D => temp_cmp_two_inc_min_101,
      Q => temp_cmp_two_inc_min_102,
      R => '0'
    );
temp_cmp_two_inc_min_102_reg_i_1: unisim.vcomponents.CARRY4
     port map (
      CI => temp_cmp_two_inc_min_102_reg_i_2_n_0,
      CO(3 downto 2) => NLW_temp_cmp_two_inc_min_102_reg_i_1_CO_UNCONNECTED(3 downto 2),
      CO(1) => temp_cmp_two_inc_min_101,
      CO(0) => temp_cmp_two_inc_min_102_reg_i_1_n_3,
      CYINIT => '0',
      DI(3 downto 2) => B"00",
      DI(1) => temp_cmp_two_inc_min_102_i_3_n_0,
      DI(0) => temp_cmp_two_inc_min_102_i_4_n_0,
      O(3 downto 0) => NLW_temp_cmp_two_inc_min_102_reg_i_1_O_UNCONNECTED(3 downto 0),
      S(3 downto 2) => B"00",
      S(1) => temp_cmp_two_inc_min_102_i_5_n_0,
      S(0) => temp_cmp_two_inc_min_102_i_6_n_0
    );
temp_cmp_two_inc_min_102_reg_i_2: unisim.vcomponents.CARRY4
     port map (
      CI => '0',
      CO(3) => temp_cmp_two_inc_min_102_reg_i_2_n_0,
      CO(2) => temp_cmp_two_inc_min_102_reg_i_2_n_1,
      CO(1) => temp_cmp_two_inc_min_102_reg_i_2_n_2,
      CO(0) => temp_cmp_two_inc_min_102_reg_i_2_n_3,
      CYINIT => '0',
      DI(3) => temp_cmp_two_inc_min_102_i_7_n_0,
      DI(2) => temp_cmp_two_inc_min_102_i_8_n_0,
      DI(1) => temp_cmp_two_inc_min_102_i_9_n_0,
      DI(0) => temp_cmp_two_inc_min_102_i_10_n_0,
      O(3 downto 0) => NLW_temp_cmp_two_inc_min_102_reg_i_2_O_UNCONNECTED(3 downto 0),
      S(3) => temp_cmp_two_inc_min_102_i_11_n_0,
      S(2) => temp_cmp_two_inc_min_102_i_12_n_0,
      S(1) => temp_cmp_two_inc_min_102_i_13_n_0,
      S(0) => temp_cmp_two_inc_min_102_i_14_n_0
    );
tempmon_init_complete_reg: unisim.vcomponents.FDRE
     port map (
      C => pi_f_dec_reg_0,
      CE => tempmon_state_init,
      D => tempmon_state_init,
      Q => tempmon_init_complete,
      R => \four_dec_min_limit_reg[0]_0\
    );
tempmon_pi_f_en_r_i_1: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => \^tempmon_pi_f_inc\,
      I1 => tempmon_pi_f_dec,
      O => tempmon_sel_pi_incdec
    );
tempmon_sample_en_101_reg: unisim.vcomponents.FDRE
     port map (
      C => pi_f_dec_reg_0,
      CE => '1',
      D => mc_ref_zq_wip,
      Q => tempmon_sample_en_101,
      R => \four_dec_min_limit_reg[0]_0\
    );
tempmon_sample_en_102_reg: unisim.vcomponents.FDRE
     port map (
      C => pi_f_dec_reg_0,
      CE => '1',
      D => tempmon_sample_en_101,
      Q => tempmon_sample_en_102,
      R => \four_dec_min_limit_reg[0]_0\
    );
\tempmon_state[0]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \tempmon_state[10]_i_6_n_0\,
      O => tempmon_state_nxt(0)
    );
\tempmon_state[10]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFC444"
    )
        port map (
      I0 => \tempmon_state[10]_i_3_n_0\,
      I1 => update_temp_102,
      I2 => temp_cmp_four_dec_min_102,
      I3 => tempmon_state(10),
      I4 => \tempmon_state[10]_i_4_n_0\,
      I5 => \tempmon_state[10]_i_5_n_0\,
      O => \tempmon_state[10]_i_1_n_0\
    );
\tempmon_state[10]_i_10\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00010116"
    )
        port map (
      I0 => tempmon_state(0),
      I1 => tempmon_state(1),
      I2 => tempmon_state(2),
      I3 => tempmon_state(3),
      I4 => tempmon_state(4),
      O => \tempmon_state[10]_i_10_n_0\
    );
\tempmon_state[10]_i_11\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFEFEE8"
    )
        port map (
      I0 => tempmon_state(0),
      I1 => tempmon_state(1),
      I2 => tempmon_state(2),
      I3 => tempmon_state(3),
      I4 => tempmon_state(4),
      O => \tempmon_state[10]_i_11_n_0\
    );
\tempmon_state[10]_i_12\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000100010116"
    )
        port map (
      I0 => tempmon_state(5),
      I1 => tempmon_state(6),
      I2 => tempmon_state(7),
      I3 => tempmon_state(8),
      I4 => tempmon_state(9),
      I5 => tempmon_state(10),
      O => \tempmon_state[10]_i_12_n_0\
    );
\tempmon_state[10]_i_13\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFEFFFEFEE8"
    )
        port map (
      I0 => tempmon_state(5),
      I1 => tempmon_state(6),
      I2 => tempmon_state(7),
      I3 => tempmon_state(8),
      I4 => tempmon_state(9),
      I5 => tempmon_state(10),
      O => \tempmon_state[10]_i_13_n_0\
    );
\tempmon_state[10]_i_14\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F888"
    )
        port map (
      I0 => temp_cmp_two_dec_min_102,
      I1 => tempmon_state(8),
      I2 => temp_cmp_three_inc_min_102,
      I3 => tempmon_state(3),
      O => \tempmon_state[10]_i_14_n_0\
    );
\tempmon_state[10]_i_15\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"80"
    )
        port map (
      I0 => temp_cmp_two_dec_max_102,
      I1 => update_temp_102,
      I2 => tempmon_state(8),
      O => \tempmon_state[10]_i_15_n_0\
    );
\tempmon_state[10]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8000"
    )
        port map (
      I0 => update_temp_102,
      I1 => temp_cmp_three_dec_max_102,
      I2 => tempmon_state(9),
      I3 => \tempmon_state[10]_i_6_n_0\,
      O => tempmon_state_nxt(10)
    );
\tempmon_state[10]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000022202220222"
    )
        port map (
      I0 => pi_f_dec_i_2_n_0,
      I1 => \tempmon_state[10]_i_7_n_0\,
      I2 => temp_cmp_one_dec_min_102,
      I3 => tempmon_state(7),
      I4 => temp_cmp_three_dec_min_102,
      I5 => tempmon_state(9),
      O => \tempmon_state[10]_i_3_n_0\
    );
\tempmon_state[10]_i_4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFEFEFEF"
    )
        port map (
      I0 => \tempmon_state[10]_i_8_n_0\,
      I1 => tempmon_state(1),
      I2 => \tempmon_state[10]_i_6_n_0\,
      I3 => tempmon_state(0),
      I4 => calib_complete,
      O => \tempmon_state[10]_i_4_n_0\
    );
\tempmon_state[10]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFAAEAAAEAAAEAAA"
    )
        port map (
      I0 => \tempmon_state[10]_i_9_n_0\,
      I1 => tempmon_state(6),
      I2 => temp_cmp_neutral_max_102,
      I3 => update_temp_102,
      I4 => tempmon_state(7),
      I5 => temp_cmp_one_dec_max_102,
      O => \tempmon_state[10]_i_5_n_0\
    );
\tempmon_state[10]_i_6\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0012"
    )
        port map (
      I0 => \tempmon_state[10]_i_10_n_0\,
      I1 => \tempmon_state[10]_i_11_n_0\,
      I2 => \tempmon_state[10]_i_12_n_0\,
      I3 => \tempmon_state[10]_i_13_n_0\,
      O => \tempmon_state[10]_i_6_n_0\
    );
\tempmon_state[10]_i_7\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFF888"
    )
        port map (
      I0 => tempmon_state(4),
      I1 => temp_cmp_two_inc_min_102,
      I2 => tempmon_state(6),
      I3 => temp_cmp_neutral_min_102,
      I4 => \tempmon_state[10]_i_14_n_0\,
      O => \tempmon_state[10]_i_7_n_0\
    );
\tempmon_state[10]_i_8\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"80"
    )
        port map (
      I0 => temp_cmp_one_inc_min_102,
      I1 => tempmon_state(5),
      I2 => update_temp_102,
      O => \tempmon_state[10]_i_8_n_0\
    );
\tempmon_state[10]_i_9\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFF8F0F0F8F8F0F0"
    )
        port map (
      I0 => tempmon_state(2),
      I1 => temp_cmp_four_inc_max_102,
      I2 => \tempmon_state[10]_i_15_n_0\,
      I3 => tempmon_state(9),
      I4 => update_temp_102,
      I5 => temp_cmp_three_dec_max_102,
      O => \tempmon_state[10]_i_9_n_0\
    );
\tempmon_state[1]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \tempmon_state[10]_i_6_n_0\,
      I1 => tempmon_state(0),
      O => tempmon_state_nxt(1)
    );
\tempmon_state[2]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7000"
    )
        port map (
      I0 => temp_cmp_three_inc_max_102,
      I1 => update_temp_102,
      I2 => tempmon_state(3),
      I3 => \tempmon_state[10]_i_6_n_0\,
      O => tempmon_state_nxt(2)
    );
\tempmon_state[3]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"8AAA8888"
    )
        port map (
      I0 => \tempmon_state[10]_i_6_n_0\,
      I1 => tempmon_state(2),
      I2 => temp_cmp_two_inc_max_102,
      I3 => update_temp_102,
      I4 => tempmon_state(4),
      O => tempmon_state_nxt(3)
    );
\tempmon_state[4]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8080F000F080F000"
    )
        port map (
      I0 => temp_cmp_three_inc_max_102,
      I1 => tempmon_state(3),
      I2 => \tempmon_state[10]_i_6_n_0\,
      I3 => tempmon_state(5),
      I4 => update_temp_102,
      I5 => temp_cmp_one_inc_max_102,
      O => tempmon_state_nxt(4)
    );
\tempmon_state[5]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8080F000F080F000"
    )
        port map (
      I0 => temp_cmp_two_inc_max_102,
      I1 => tempmon_state(4),
      I2 => \tempmon_state[10]_i_6_n_0\,
      I3 => tempmon_state(6),
      I4 => update_temp_102,
      I5 => temp_cmp_neutral_max_102,
      O => tempmon_state_nxt(5)
    );
\tempmon_state[6]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFF0000BFA00000"
    )
        port map (
      I0 => \tempmon_state[6]_i_2_n_0\,
      I1 => temp_cmp_one_dec_max_102,
      I2 => update_temp_102,
      I3 => tempmon_state(7),
      I4 => \tempmon_state[10]_i_6_n_0\,
      I5 => tempmon_state(1),
      O => tempmon_state_nxt(6)
    );
\tempmon_state[6]_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => temp_cmp_one_inc_max_102,
      I1 => tempmon_state(5),
      O => \tempmon_state[6]_i_2_n_0\
    );
\tempmon_state[7]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"80AAAAAA80008000"
    )
        port map (
      I0 => \tempmon_state[10]_i_6_n_0\,
      I1 => tempmon_state(6),
      I2 => temp_cmp_neutral_max_102,
      I3 => update_temp_102,
      I4 => temp_cmp_two_dec_max_102,
      I5 => tempmon_state(8),
      O => tempmon_state_nxt(7)
    );
\tempmon_state[8]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8080F080F000F000"
    )
        port map (
      I0 => tempmon_state(7),
      I1 => temp_cmp_one_dec_max_102,
      I2 => \tempmon_state[10]_i_6_n_0\,
      I3 => tempmon_state(9),
      I4 => temp_cmp_three_dec_max_102,
      I5 => update_temp_102,
      O => tempmon_state_nxt(8)
    );
\tempmon_state[9]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AAAA8000"
    )
        port map (
      I0 => \tempmon_state[10]_i_6_n_0\,
      I1 => temp_cmp_two_dec_max_102,
      I2 => update_temp_102,
      I3 => tempmon_state(8),
      I4 => tempmon_state(10),
      O => tempmon_state_nxt(9)
    );
\tempmon_state_reg[0]\: unisim.vcomponents.FDSE
     port map (
      C => pi_f_dec_reg_0,
      CE => \tempmon_state[10]_i_1_n_0\,
      D => tempmon_state_nxt(0),
      Q => tempmon_state(0),
      S => \device_temp_101_reg[0]_0\
    );
\tempmon_state_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => pi_f_dec_reg_0,
      CE => \tempmon_state[10]_i_1_n_0\,
      D => tempmon_state_nxt(10),
      Q => tempmon_state(10),
      R => \device_temp_101_reg[0]_0\
    );
\tempmon_state_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => pi_f_dec_reg_0,
      CE => \tempmon_state[10]_i_1_n_0\,
      D => tempmon_state_nxt(1),
      Q => tempmon_state(1),
      R => \device_temp_101_reg[0]_0\
    );
\tempmon_state_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => pi_f_dec_reg_0,
      CE => \tempmon_state[10]_i_1_n_0\,
      D => tempmon_state_nxt(2),
      Q => tempmon_state(2),
      R => \device_temp_101_reg[0]_0\
    );
\tempmon_state_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => pi_f_dec_reg_0,
      CE => \tempmon_state[10]_i_1_n_0\,
      D => tempmon_state_nxt(3),
      Q => tempmon_state(3),
      R => \device_temp_101_reg[0]_0\
    );
\tempmon_state_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => pi_f_dec_reg_0,
      CE => \tempmon_state[10]_i_1_n_0\,
      D => tempmon_state_nxt(4),
      Q => tempmon_state(4),
      R => \device_temp_101_reg[0]_0\
    );
\tempmon_state_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => pi_f_dec_reg_0,
      CE => \tempmon_state[10]_i_1_n_0\,
      D => tempmon_state_nxt(5),
      Q => tempmon_state(5),
      R => \device_temp_101_reg[0]_0\
    );
\tempmon_state_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => pi_f_dec_reg_0,
      CE => \tempmon_state[10]_i_1_n_0\,
      D => tempmon_state_nxt(6),
      Q => tempmon_state(6),
      R => \device_temp_101_reg[0]_0\
    );
\tempmon_state_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => pi_f_dec_reg_0,
      CE => \tempmon_state[10]_i_1_n_0\,
      D => tempmon_state_nxt(7),
      Q => tempmon_state(7),
      R => \device_temp_101_reg[0]_0\
    );
\tempmon_state_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => pi_f_dec_reg_0,
      CE => \tempmon_state[10]_i_1_n_0\,
      D => tempmon_state_nxt(8),
      Q => tempmon_state(8),
      R => \device_temp_101_reg[0]_0\
    );
\tempmon_state_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => pi_f_dec_reg_0,
      CE => \tempmon_state[10]_i_1_n_0\,
      D => tempmon_state_nxt(9),
      Q => tempmon_state(9),
      R => \device_temp_101_reg[0]_0\
    );
\three_dec_max_limit[0]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => p_0_in,
      I1 => device_temp_init(0),
      O => \three_dec_max_limit[0]_i_1_n_0\
    );
\three_dec_max_limit[10]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => \three_dec_max_limit_reg[11]_i_2_n_6\,
      I1 => p_0_in,
      O => \three_dec_max_limit[10]_i_1_n_0\
    );
\three_dec_max_limit[11]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => \three_dec_max_limit_reg[11]_i_2_n_5\,
      I1 => p_0_in,
      O => \three_dec_max_limit[11]_i_1_n_0\
    );
\three_dec_max_limit[11]_i_3\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => device_temp_init(9),
      O => \three_dec_max_limit[11]_i_3_n_0\
    );
\three_dec_max_limit[1]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => \three_inc_max_limit_reg[4]_i_1_n_7\,
      I1 => p_0_in,
      O => \three_dec_max_limit[1]_i_1_n_0\
    );
\three_dec_max_limit[2]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => \three_dec_max_limit_reg[4]_i_2_n_6\,
      I1 => p_0_in,
      O => \three_dec_max_limit[2]_i_1_n_0\
    );
\three_dec_max_limit[3]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => \three_dec_max_limit_reg[4]_i_2_n_5\,
      I1 => p_0_in,
      O => \three_dec_max_limit[3]_i_1_n_0\
    );
\three_dec_max_limit[4]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => \three_dec_max_limit_reg[4]_i_2_n_4\,
      I1 => p_0_in,
      O => \three_dec_max_limit[4]_i_1_n_0\
    );
\three_dec_max_limit[5]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => \three_dec_max_limit_reg[8]_i_2_n_7\,
      I1 => p_0_in,
      O => \three_dec_max_limit[5]_i_1_n_0\
    );
\three_dec_max_limit[6]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => \three_dec_max_limit_reg[8]_i_2_n_6\,
      I1 => p_0_in,
      O => \three_dec_max_limit[6]_i_1_n_0\
    );
\three_dec_max_limit[7]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => \three_dec_max_limit_reg[8]_i_2_n_5\,
      I1 => p_0_in,
      O => \three_dec_max_limit[7]_i_1_n_0\
    );
\three_dec_max_limit[8]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => \three_dec_max_limit_reg[8]_i_2_n_4\,
      I1 => p_0_in,
      O => \three_dec_max_limit[8]_i_1_n_0\
    );
\three_dec_max_limit[8]_i_3\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => device_temp_init(8),
      O => \three_dec_max_limit[8]_i_3_n_0\
    );
\three_dec_max_limit[8]_i_4\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => device_temp_init(6),
      O => \three_dec_max_limit[8]_i_4_n_0\
    );
\three_dec_max_limit[9]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => \three_dec_max_limit_reg[11]_i_2_n_7\,
      I1 => p_0_in,
      O => \three_dec_max_limit[9]_i_1_n_0\
    );
\three_dec_max_limit_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => pi_f_dec_reg_0,
      CE => '1',
      D => \three_dec_max_limit[0]_i_1_n_0\,
      Q => three_dec_max_limit(0),
      R => \four_dec_min_limit_reg[0]_0\
    );
\three_dec_max_limit_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => pi_f_dec_reg_0,
      CE => '1',
      D => \three_dec_max_limit[10]_i_1_n_0\,
      Q => three_dec_max_limit(10),
      R => \four_dec_min_limit_reg[0]_0\
    );
\three_dec_max_limit_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => pi_f_dec_reg_0,
      CE => '1',
      D => \three_dec_max_limit[11]_i_1_n_0\,
      Q => three_dec_max_limit(11),
      R => \four_dec_min_limit_reg[0]_0\
    );
\three_dec_max_limit_reg[11]_i_2\: unisim.vcomponents.CARRY4
     port map (
      CI => \three_dec_max_limit_reg[8]_i_2_n_0\,
      CO(3) => p_0_in,
      CO(2) => \NLW_three_dec_max_limit_reg[11]_i_2_CO_UNCONNECTED\(2),
      CO(1) => \three_dec_max_limit_reg[11]_i_2_n_2\,
      CO(0) => \three_dec_max_limit_reg[11]_i_2_n_3\,
      CYINIT => '0',
      DI(3 downto 1) => B"000",
      DI(0) => device_temp_init(9),
      O(3) => \NLW_three_dec_max_limit_reg[11]_i_2_O_UNCONNECTED\(3),
      O(2) => \three_dec_max_limit_reg[11]_i_2_n_5\,
      O(1) => \three_dec_max_limit_reg[11]_i_2_n_6\,
      O(0) => \three_dec_max_limit_reg[11]_i_2_n_7\,
      S(3) => '1',
      S(2 downto 1) => device_temp_init(11 downto 10),
      S(0) => \three_dec_max_limit[11]_i_3_n_0\
    );
\three_dec_max_limit_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => pi_f_dec_reg_0,
      CE => '1',
      D => \three_dec_max_limit[1]_i_1_n_0\,
      Q => three_dec_max_limit(1),
      R => \four_dec_min_limit_reg[0]_0\
    );
\three_dec_max_limit_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => pi_f_dec_reg_0,
      CE => '1',
      D => \three_dec_max_limit[2]_i_1_n_0\,
      Q => three_dec_max_limit(2),
      R => \four_dec_min_limit_reg[0]_0\
    );
\three_dec_max_limit_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => pi_f_dec_reg_0,
      CE => '1',
      D => \three_dec_max_limit[3]_i_1_n_0\,
      Q => three_dec_max_limit(3),
      R => \four_dec_min_limit_reg[0]_0\
    );
\three_dec_max_limit_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => pi_f_dec_reg_0,
      CE => '1',
      D => \three_dec_max_limit[4]_i_1_n_0\,
      Q => three_dec_max_limit(4),
      R => \four_dec_min_limit_reg[0]_0\
    );
\three_dec_max_limit_reg[4]_i_2\: unisim.vcomponents.CARRY4
     port map (
      CI => '0',
      CO(3) => \three_dec_max_limit_reg[4]_i_2_n_0\,
      CO(2) => \three_dec_max_limit_reg[4]_i_2_n_1\,
      CO(1) => \three_dec_max_limit_reg[4]_i_2_n_2\,
      CO(0) => \three_dec_max_limit_reg[4]_i_2_n_3\,
      CYINIT => device_temp_init(0),
      DI(3 downto 0) => B"0000",
      O(3) => \three_dec_max_limit_reg[4]_i_2_n_4\,
      O(2) => \three_dec_max_limit_reg[4]_i_2_n_5\,
      O(1) => \three_dec_max_limit_reg[4]_i_2_n_6\,
      O(0) => \NLW_three_dec_max_limit_reg[4]_i_2_O_UNCONNECTED\(0),
      S(3 downto 0) => device_temp_init(4 downto 1)
    );
\three_dec_max_limit_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => pi_f_dec_reg_0,
      CE => '1',
      D => \three_dec_max_limit[5]_i_1_n_0\,
      Q => three_dec_max_limit(5),
      R => \four_dec_min_limit_reg[0]_0\
    );
\three_dec_max_limit_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => pi_f_dec_reg_0,
      CE => '1',
      D => \three_dec_max_limit[6]_i_1_n_0\,
      Q => three_dec_max_limit(6),
      R => \four_dec_min_limit_reg[0]_0\
    );
\three_dec_max_limit_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => pi_f_dec_reg_0,
      CE => '1',
      D => \three_dec_max_limit[7]_i_1_n_0\,
      Q => three_dec_max_limit(7),
      R => \four_dec_min_limit_reg[0]_0\
    );
\three_dec_max_limit_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => pi_f_dec_reg_0,
      CE => '1',
      D => \three_dec_max_limit[8]_i_1_n_0\,
      Q => three_dec_max_limit(8),
      R => \four_dec_min_limit_reg[0]_0\
    );
\three_dec_max_limit_reg[8]_i_2\: unisim.vcomponents.CARRY4
     port map (
      CI => \three_dec_max_limit_reg[4]_i_2_n_0\,
      CO(3) => \three_dec_max_limit_reg[8]_i_2_n_0\,
      CO(2) => \three_dec_max_limit_reg[8]_i_2_n_1\,
      CO(1) => \three_dec_max_limit_reg[8]_i_2_n_2\,
      CO(0) => \three_dec_max_limit_reg[8]_i_2_n_3\,
      CYINIT => '0',
      DI(3) => device_temp_init(8),
      DI(2) => '0',
      DI(1) => device_temp_init(6),
      DI(0) => '0',
      O(3) => \three_dec_max_limit_reg[8]_i_2_n_4\,
      O(2) => \three_dec_max_limit_reg[8]_i_2_n_5\,
      O(1) => \three_dec_max_limit_reg[8]_i_2_n_6\,
      O(0) => \three_dec_max_limit_reg[8]_i_2_n_7\,
      S(3) => \three_dec_max_limit[8]_i_3_n_0\,
      S(2) => device_temp_init(7),
      S(1) => \three_dec_max_limit[8]_i_4_n_0\,
      S(0) => device_temp_init(5)
    );
\three_dec_max_limit_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => pi_f_dec_reg_0,
      CE => '1',
      D => \three_dec_max_limit[9]_i_1_n_0\,
      Q => three_dec_max_limit(9),
      R => \four_dec_min_limit_reg[0]_0\
    );
\three_dec_min_limit[11]_i_2\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => two_dec_max_limit(11),
      O => \three_dec_min_limit[11]_i_2_n_0\
    );
\three_dec_min_limit[11]_i_3\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => two_dec_max_limit(10),
      O => \three_dec_min_limit[11]_i_3_n_0\
    );
\three_dec_min_limit[5]_i_2\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => two_dec_max_limit(5),
      O => \three_dec_min_limit[5]_i_2_n_0\
    );
\three_dec_min_limit[5]_i_3\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => two_dec_max_limit(4),
      O => \three_dec_min_limit[5]_i_3_n_0\
    );
\three_dec_min_limit[5]_i_4\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => two_dec_max_limit(3),
      O => \three_dec_min_limit[5]_i_4_n_0\
    );
\three_dec_min_limit[9]_i_2\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => two_dec_max_limit(9),
      O => \three_dec_min_limit[9]_i_2_n_0\
    );
\three_dec_min_limit[9]_i_3\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => two_dec_max_limit(8),
      O => \three_dec_min_limit[9]_i_3_n_0\
    );
\three_dec_min_limit[9]_i_4\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => two_dec_max_limit(7),
      O => \three_dec_min_limit[9]_i_4_n_0\
    );
\three_dec_min_limit[9]_i_5\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => two_dec_max_limit(6),
      O => \three_dec_min_limit[9]_i_5_n_0\
    );
\three_dec_min_limit_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => pi_f_dec_reg_0,
      CE => '1',
      D => two_dec_max_limit(0),
      Q => three_dec_min_limit(0),
      R => \one_dec_min_limit_reg[11]_0\
    );
\three_dec_min_limit_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => pi_f_dec_reg_0,
      CE => '1',
      D => three_dec_min_limit_nxt(10),
      Q => three_dec_min_limit(10),
      R => \one_dec_min_limit_reg[11]_0\
    );
\three_dec_min_limit_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => pi_f_dec_reg_0,
      CE => '1',
      D => three_dec_min_limit_nxt(11),
      Q => three_dec_min_limit(11),
      R => \one_dec_min_limit_reg[11]_0\
    );
\three_dec_min_limit_reg[11]_i_1\: unisim.vcomponents.CARRY4
     port map (
      CI => \three_dec_min_limit_reg[9]_i_1_n_0\,
      CO(3 downto 1) => \NLW_three_dec_min_limit_reg[11]_i_1_CO_UNCONNECTED\(3 downto 1),
      CO(0) => \three_dec_min_limit_reg[11]_i_1_n_3\,
      CYINIT => '0',
      DI(3 downto 1) => B"000",
      DI(0) => two_dec_max_limit(10),
      O(3 downto 2) => \NLW_three_dec_min_limit_reg[11]_i_1_O_UNCONNECTED\(3 downto 2),
      O(1 downto 0) => three_dec_min_limit_nxt(11 downto 10),
      S(3 downto 2) => B"00",
      S(1) => \three_dec_min_limit[11]_i_2_n_0\,
      S(0) => \three_dec_min_limit[11]_i_3_n_0\
    );
\three_dec_min_limit_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => pi_f_dec_reg_0,
      CE => '1',
      D => two_dec_max_limit(1),
      Q => three_dec_min_limit(1),
      R => \one_dec_min_limit_reg[11]_0\
    );
\three_dec_min_limit_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => pi_f_dec_reg_0,
      CE => '1',
      D => three_dec_min_limit_nxt(2),
      Q => three_dec_min_limit(2),
      R => \one_dec_min_limit_reg[11]_0\
    );
\three_dec_min_limit_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => pi_f_dec_reg_0,
      CE => '1',
      D => three_dec_min_limit_nxt(3),
      Q => three_dec_min_limit(3),
      R => \one_dec_min_limit_reg[11]_0\
    );
\three_dec_min_limit_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => pi_f_dec_reg_0,
      CE => '1',
      D => three_dec_min_limit_nxt(4),
      Q => three_dec_min_limit(4),
      R => \one_dec_min_limit_reg[11]_0\
    );
\three_dec_min_limit_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => pi_f_dec_reg_0,
      CE => '1',
      D => three_dec_min_limit_nxt(5),
      Q => three_dec_min_limit(5),
      R => \one_dec_min_limit_reg[11]_0\
    );
\three_dec_min_limit_reg[5]_i_1\: unisim.vcomponents.CARRY4
     port map (
      CI => '0',
      CO(3) => \three_dec_min_limit_reg[5]_i_1_n_0\,
      CO(2) => \three_dec_min_limit_reg[5]_i_1_n_1\,
      CO(1) => \three_dec_min_limit_reg[5]_i_1_n_2\,
      CO(0) => \three_dec_min_limit_reg[5]_i_1_n_3\,
      CYINIT => '0',
      DI(3 downto 1) => two_dec_max_limit(5 downto 3),
      DI(0) => '0',
      O(3 downto 0) => three_dec_min_limit_nxt(5 downto 2),
      S(3) => \three_dec_min_limit[5]_i_2_n_0\,
      S(2) => \three_dec_min_limit[5]_i_3_n_0\,
      S(1) => \three_dec_min_limit[5]_i_4_n_0\,
      S(0) => two_dec_max_limit(2)
    );
\three_dec_min_limit_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => pi_f_dec_reg_0,
      CE => '1',
      D => three_dec_min_limit_nxt(6),
      Q => three_dec_min_limit(6),
      R => \one_dec_min_limit_reg[11]_0\
    );
\three_dec_min_limit_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => pi_f_dec_reg_0,
      CE => '1',
      D => three_dec_min_limit_nxt(7),
      Q => three_dec_min_limit(7),
      R => \one_dec_min_limit_reg[11]_0\
    );
\three_dec_min_limit_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => pi_f_dec_reg_0,
      CE => '1',
      D => three_dec_min_limit_nxt(8),
      Q => three_dec_min_limit(8),
      R => \one_dec_min_limit_reg[11]_0\
    );
\three_dec_min_limit_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => pi_f_dec_reg_0,
      CE => '1',
      D => three_dec_min_limit_nxt(9),
      Q => three_dec_min_limit(9),
      R => \one_dec_min_limit_reg[11]_0\
    );
\three_dec_min_limit_reg[9]_i_1\: unisim.vcomponents.CARRY4
     port map (
      CI => \three_dec_min_limit_reg[5]_i_1_n_0\,
      CO(3) => \three_dec_min_limit_reg[9]_i_1_n_0\,
      CO(2) => \three_dec_min_limit_reg[9]_i_1_n_1\,
      CO(1) => \three_dec_min_limit_reg[9]_i_1_n_2\,
      CO(0) => \three_dec_min_limit_reg[9]_i_1_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => two_dec_max_limit(9 downto 6),
      O(3 downto 0) => three_dec_min_limit_nxt(9 downto 6),
      S(3) => \three_dec_min_limit[9]_i_2_n_0\,
      S(2) => \three_dec_min_limit[9]_i_3_n_0\,
      S(1) => \three_dec_min_limit[9]_i_4_n_0\,
      S(0) => \three_dec_min_limit[9]_i_5_n_0\
    );
\three_inc_max_limit[11]_i_2\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => device_temp_init(11),
      O => \three_inc_max_limit[11]_i_2_n_0\
    );
\three_inc_max_limit[11]_i_3\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => device_temp_init(10),
      O => \three_inc_max_limit[11]_i_3_n_0\
    );
\three_inc_max_limit[4]_i_2\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => device_temp_init(3),
      O => \three_inc_max_limit[4]_i_2_n_0\
    );
\three_inc_max_limit[4]_i_3\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => device_temp_init(2),
      O => \three_inc_max_limit[4]_i_3_n_0\
    );
\three_inc_max_limit[8]_i_2\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => device_temp_init(8),
      O => \three_inc_max_limit[8]_i_2_n_0\
    );
\three_inc_max_limit[8]_i_3\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => device_temp_init(7),
      O => \three_inc_max_limit[8]_i_3_n_0\
    );
\three_inc_max_limit[8]_i_4\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => device_temp_init(5),
      O => \three_inc_max_limit[8]_i_4_n_0\
    );
\three_inc_max_limit_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => pi_f_dec_reg_0,
      CE => '1',
      D => three_inc_max_limit_nxt(10),
      Q => three_inc_max_limit(10),
      R => \one_dec_max_limit_reg[2]_0\
    );
\three_inc_max_limit_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => pi_f_dec_reg_0,
      CE => '1',
      D => three_inc_max_limit_nxt(11),
      Q => three_inc_max_limit(11),
      R => \one_dec_max_limit_reg[2]_0\
    );
\three_inc_max_limit_reg[11]_i_1\: unisim.vcomponents.CARRY4
     port map (
      CI => \three_inc_max_limit_reg[8]_i_1_n_0\,
      CO(3 downto 2) => \NLW_three_inc_max_limit_reg[11]_i_1_CO_UNCONNECTED\(3 downto 2),
      CO(1) => \three_inc_max_limit_reg[11]_i_1_n_2\,
      CO(0) => \three_inc_max_limit_reg[11]_i_1_n_3\,
      CYINIT => '0',
      DI(3 downto 2) => B"00",
      DI(1) => device_temp_init(10),
      DI(0) => '0',
      O(3) => \NLW_three_inc_max_limit_reg[11]_i_1_O_UNCONNECTED\(3),
      O(2 downto 0) => three_inc_max_limit_nxt(11 downto 9),
      S(3) => '0',
      S(2) => \three_inc_max_limit[11]_i_2_n_0\,
      S(1) => \three_inc_max_limit[11]_i_3_n_0\,
      S(0) => device_temp_init(9)
    );
\three_inc_max_limit_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => pi_f_dec_reg_0,
      CE => '1',
      D => three_inc_max_limit_nxt(2),
      Q => three_inc_max_limit(2),
      R => \one_dec_max_limit_reg[2]_0\
    );
\three_inc_max_limit_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => pi_f_dec_reg_0,
      CE => '1',
      D => three_inc_max_limit_nxt(3),
      Q => three_inc_max_limit(3),
      R => \one_dec_max_limit_reg[2]_0\
    );
\three_inc_max_limit_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => pi_f_dec_reg_0,
      CE => '1',
      D => three_inc_max_limit_nxt(4),
      Q => three_inc_max_limit(4),
      R => \one_dec_max_limit_reg[2]_0\
    );
\three_inc_max_limit_reg[4]_i_1\: unisim.vcomponents.CARRY4
     port map (
      CI => '0',
      CO(3) => \three_inc_max_limit_reg[4]_i_1_n_0\,
      CO(2) => \three_inc_max_limit_reg[4]_i_1_n_1\,
      CO(1) => \three_inc_max_limit_reg[4]_i_1_n_2\,
      CO(0) => \three_inc_max_limit_reg[4]_i_1_n_3\,
      CYINIT => device_temp_init(0),
      DI(3) => '0',
      DI(2 downto 1) => device_temp_init(3 downto 2),
      DI(0) => '0',
      O(3 downto 1) => three_inc_max_limit_nxt(4 downto 2),
      O(0) => \three_inc_max_limit_reg[4]_i_1_n_7\,
      S(3) => device_temp_init(4),
      S(2) => \three_inc_max_limit[4]_i_2_n_0\,
      S(1) => \three_inc_max_limit[4]_i_3_n_0\,
      S(0) => device_temp_init(1)
    );
\three_inc_max_limit_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => pi_f_dec_reg_0,
      CE => '1',
      D => three_inc_max_limit_nxt(5),
      Q => three_inc_max_limit(5),
      R => \one_dec_max_limit_reg[2]_0\
    );
\three_inc_max_limit_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => pi_f_dec_reg_0,
      CE => '1',
      D => three_inc_max_limit_nxt(6),
      Q => three_inc_max_limit(6),
      R => \one_dec_max_limit_reg[2]_0\
    );
\three_inc_max_limit_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => pi_f_dec_reg_0,
      CE => '1',
      D => three_inc_max_limit_nxt(7),
      Q => three_inc_max_limit(7),
      R => \one_dec_max_limit_reg[2]_0\
    );
\three_inc_max_limit_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => pi_f_dec_reg_0,
      CE => '1',
      D => three_inc_max_limit_nxt(8),
      Q => three_inc_max_limit(8),
      R => \one_dec_max_limit_reg[2]_0\
    );
\three_inc_max_limit_reg[8]_i_1\: unisim.vcomponents.CARRY4
     port map (
      CI => \three_inc_max_limit_reg[4]_i_1_n_0\,
      CO(3) => \three_inc_max_limit_reg[8]_i_1_n_0\,
      CO(2) => \three_inc_max_limit_reg[8]_i_1_n_1\,
      CO(1) => \three_inc_max_limit_reg[8]_i_1_n_2\,
      CO(0) => \three_inc_max_limit_reg[8]_i_1_n_3\,
      CYINIT => '0',
      DI(3 downto 2) => device_temp_init(8 downto 7),
      DI(1) => '0',
      DI(0) => device_temp_init(5),
      O(3 downto 0) => three_inc_max_limit_nxt(8 downto 5),
      S(3) => \three_inc_max_limit[8]_i_2_n_0\,
      S(2) => \three_inc_max_limit[8]_i_3_n_0\,
      S(1) => device_temp_init(6),
      S(0) => \three_inc_max_limit[8]_i_4_n_0\
    );
\three_inc_max_limit_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => pi_f_dec_reg_0,
      CE => '1',
      D => three_inc_max_limit_nxt(9),
      Q => three_inc_max_limit(9),
      R => \one_dec_max_limit_reg[2]_0\
    );
\three_inc_min_limit[11]_i_2\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => four_inc_max_limit(11),
      O => \three_inc_min_limit[11]_i_2_n_0\
    );
\three_inc_min_limit[11]_i_3\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => four_inc_max_limit(10),
      O => \three_inc_min_limit[11]_i_3_n_0\
    );
\three_inc_min_limit[5]_i_2\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => four_inc_max_limit(5),
      O => \three_inc_min_limit[5]_i_2_n_0\
    );
\three_inc_min_limit[5]_i_3\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => four_inc_max_limit(4),
      O => \three_inc_min_limit[5]_i_3_n_0\
    );
\three_inc_min_limit[5]_i_4\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => four_inc_max_limit(3),
      O => \three_inc_min_limit[5]_i_4_n_0\
    );
\three_inc_min_limit[9]_i_2\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => four_inc_max_limit(9),
      O => \three_inc_min_limit[9]_i_2_n_0\
    );
\three_inc_min_limit[9]_i_3\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => four_inc_max_limit(8),
      O => \three_inc_min_limit[9]_i_3_n_0\
    );
\three_inc_min_limit[9]_i_4\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => four_inc_max_limit(7),
      O => \three_inc_min_limit[9]_i_4_n_0\
    );
\three_inc_min_limit[9]_i_5\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => four_inc_max_limit(6),
      O => \three_inc_min_limit[9]_i_5_n_0\
    );
\three_inc_min_limit_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => pi_f_dec_reg_0,
      CE => '1',
      D => three_inc_min_limit_nxt(10),
      Q => three_inc_min_limit(10),
      R => \neutral_max_limit_reg[11]_0\
    );
\three_inc_min_limit_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => pi_f_dec_reg_0,
      CE => '1',
      D => three_inc_min_limit_nxt(11),
      Q => three_inc_min_limit(11),
      R => \neutral_max_limit_reg[11]_0\
    );
\three_inc_min_limit_reg[11]_i_1\: unisim.vcomponents.CARRY4
     port map (
      CI => \three_inc_min_limit_reg[9]_i_1_n_0\,
      CO(3 downto 1) => \NLW_three_inc_min_limit_reg[11]_i_1_CO_UNCONNECTED\(3 downto 1),
      CO(0) => \three_inc_min_limit_reg[11]_i_1_n_3\,
      CYINIT => '0',
      DI(3 downto 1) => B"000",
      DI(0) => four_inc_max_limit(10),
      O(3 downto 2) => \NLW_three_inc_min_limit_reg[11]_i_1_O_UNCONNECTED\(3 downto 2),
      O(1 downto 0) => three_inc_min_limit_nxt(11 downto 10),
      S(3 downto 2) => B"00",
      S(1) => \three_inc_min_limit[11]_i_2_n_0\,
      S(0) => \three_inc_min_limit[11]_i_3_n_0\
    );
\three_inc_min_limit_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => pi_f_dec_reg_0,
      CE => '1',
      D => three_inc_min_limit_nxt(2),
      Q => three_inc_min_limit(2),
      R => \neutral_max_limit_reg[11]_0\
    );
\three_inc_min_limit_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => pi_f_dec_reg_0,
      CE => '1',
      D => three_inc_min_limit_nxt(3),
      Q => three_inc_min_limit(3),
      R => \neutral_max_limit_reg[11]_0\
    );
\three_inc_min_limit_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => pi_f_dec_reg_0,
      CE => '1',
      D => three_inc_min_limit_nxt(4),
      Q => three_inc_min_limit(4),
      R => \neutral_max_limit_reg[11]_0\
    );
\three_inc_min_limit_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => pi_f_dec_reg_0,
      CE => '1',
      D => three_inc_min_limit_nxt(5),
      Q => three_inc_min_limit(5),
      R => \neutral_max_limit_reg[11]_0\
    );
\three_inc_min_limit_reg[5]_i_1\: unisim.vcomponents.CARRY4
     port map (
      CI => '0',
      CO(3) => \three_inc_min_limit_reg[5]_i_1_n_0\,
      CO(2) => \three_inc_min_limit_reg[5]_i_1_n_1\,
      CO(1) => \three_inc_min_limit_reg[5]_i_1_n_2\,
      CO(0) => \three_inc_min_limit_reg[5]_i_1_n_3\,
      CYINIT => '0',
      DI(3 downto 1) => four_inc_max_limit(5 downto 3),
      DI(0) => '0',
      O(3 downto 0) => three_inc_min_limit_nxt(5 downto 2),
      S(3) => \three_inc_min_limit[5]_i_2_n_0\,
      S(2) => \three_inc_min_limit[5]_i_3_n_0\,
      S(1) => \three_inc_min_limit[5]_i_4_n_0\,
      S(0) => four_inc_max_limit(2)
    );
\three_inc_min_limit_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => pi_f_dec_reg_0,
      CE => '1',
      D => three_inc_min_limit_nxt(6),
      Q => three_inc_min_limit(6),
      R => \neutral_max_limit_reg[11]_0\
    );
\three_inc_min_limit_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => pi_f_dec_reg_0,
      CE => '1',
      D => three_inc_min_limit_nxt(7),
      Q => three_inc_min_limit(7),
      R => \neutral_max_limit_reg[11]_0\
    );
\three_inc_min_limit_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => pi_f_dec_reg_0,
      CE => '1',
      D => three_inc_min_limit_nxt(8),
      Q => three_inc_min_limit(8),
      R => \neutral_max_limit_reg[11]_0\
    );
\three_inc_min_limit_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => pi_f_dec_reg_0,
      CE => '1',
      D => three_inc_min_limit_nxt(9),
      Q => three_inc_min_limit(9),
      R => \neutral_max_limit_reg[11]_0\
    );
\three_inc_min_limit_reg[9]_i_1\: unisim.vcomponents.CARRY4
     port map (
      CI => \three_inc_min_limit_reg[5]_i_1_n_0\,
      CO(3) => \three_inc_min_limit_reg[9]_i_1_n_0\,
      CO(2) => \three_inc_min_limit_reg[9]_i_1_n_1\,
      CO(1) => \three_inc_min_limit_reg[9]_i_1_n_2\,
      CO(0) => \three_inc_min_limit_reg[9]_i_1_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => four_inc_max_limit(9 downto 6),
      O(3 downto 0) => three_inc_min_limit_nxt(9 downto 6),
      S(3) => \three_inc_min_limit[9]_i_2_n_0\,
      S(2) => \three_inc_min_limit[9]_i_3_n_0\,
      S(1) => \three_inc_min_limit[9]_i_4_n_0\,
      S(0) => \three_inc_min_limit[9]_i_5_n_0\
    );
\two_dec_max_limit[0]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => device_temp_init(0),
      O => \two_dec_max_limit[0]_i_1_n_0\
    );
\two_dec_max_limit[11]_i_2\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => device_temp_init(9),
      O => \two_dec_max_limit[11]_i_2_n_0\
    );
\two_dec_max_limit[4]_i_2\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => device_temp_init(4),
      O => \two_dec_max_limit[4]_i_2_n_0\
    );
\two_dec_max_limit[4]_i_3\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => device_temp_init(1),
      O => \two_dec_max_limit[4]_i_3_n_0\
    );
\two_dec_max_limit[8]_i_2\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => device_temp_init(6),
      O => \two_dec_max_limit[8]_i_2_n_0\
    );
\two_dec_max_limit_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => pi_f_dec_reg_0,
      CE => '1',
      D => \two_dec_max_limit[0]_i_1_n_0\,
      Q => two_dec_max_limit(0),
      R => \neutral_max_limit_reg[11]_0\
    );
\two_dec_max_limit_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => pi_f_dec_reg_0,
      CE => '1',
      D => two_dec_max_limit_nxt(10),
      Q => two_dec_max_limit(10),
      R => \neutral_max_limit_reg[11]_0\
    );
\two_dec_max_limit_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => pi_f_dec_reg_0,
      CE => '1',
      D => two_dec_max_limit_nxt(11),
      Q => two_dec_max_limit(11),
      R => \neutral_max_limit_reg[11]_0\
    );
\two_dec_max_limit_reg[11]_i_1\: unisim.vcomponents.CARRY4
     port map (
      CI => \two_dec_max_limit_reg[8]_i_1_n_0\,
      CO(3 downto 2) => \NLW_two_dec_max_limit_reg[11]_i_1_CO_UNCONNECTED\(3 downto 2),
      CO(1) => \two_dec_max_limit_reg[11]_i_1_n_2\,
      CO(0) => \two_dec_max_limit_reg[11]_i_1_n_3\,
      CYINIT => '0',
      DI(3 downto 1) => B"000",
      DI(0) => device_temp_init(9),
      O(3) => \NLW_two_dec_max_limit_reg[11]_i_1_O_UNCONNECTED\(3),
      O(2 downto 0) => two_dec_max_limit_nxt(11 downto 9),
      S(3) => '0',
      S(2 downto 1) => device_temp_init(11 downto 10),
      S(0) => \two_dec_max_limit[11]_i_2_n_0\
    );
\two_dec_max_limit_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => pi_f_dec_reg_0,
      CE => '1',
      D => two_dec_max_limit_nxt(1),
      Q => two_dec_max_limit(1),
      R => \neutral_max_limit_reg[11]_0\
    );
\two_dec_max_limit_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => pi_f_dec_reg_0,
      CE => '1',
      D => two_dec_max_limit_nxt(2),
      Q => two_dec_max_limit(2),
      R => \neutral_max_limit_reg[11]_0\
    );
\two_dec_max_limit_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => pi_f_dec_reg_0,
      CE => '1',
      D => two_dec_max_limit_nxt(3),
      Q => two_dec_max_limit(3),
      R => \neutral_max_limit_reg[11]_0\
    );
\two_dec_max_limit_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => pi_f_dec_reg_0,
      CE => '1',
      D => two_dec_max_limit_nxt(4),
      Q => two_dec_max_limit(4),
      R => \neutral_max_limit_reg[11]_0\
    );
\two_dec_max_limit_reg[4]_i_1\: unisim.vcomponents.CARRY4
     port map (
      CI => '0',
      CO(3) => \two_dec_max_limit_reg[4]_i_1_n_0\,
      CO(2) => \two_dec_max_limit_reg[4]_i_1_n_1\,
      CO(1) => \two_dec_max_limit_reg[4]_i_1_n_2\,
      CO(0) => \two_dec_max_limit_reg[4]_i_1_n_3\,
      CYINIT => device_temp_init(0),
      DI(3) => device_temp_init(4),
      DI(2 downto 1) => B"00",
      DI(0) => device_temp_init(1),
      O(3 downto 1) => two_dec_max_limit_nxt(4 downto 2),
      O(0) => \NLW_two_dec_max_limit_reg[4]_i_1_O_UNCONNECTED\(0),
      S(3) => \two_dec_max_limit[4]_i_2_n_0\,
      S(2 downto 1) => device_temp_init(3 downto 2),
      S(0) => \two_dec_max_limit[4]_i_3_n_0\
    );
\two_dec_max_limit_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => pi_f_dec_reg_0,
      CE => '1',
      D => two_dec_max_limit_nxt(5),
      Q => two_dec_max_limit(5),
      R => \neutral_max_limit_reg[11]_0\
    );
\two_dec_max_limit_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => pi_f_dec_reg_0,
      CE => '1',
      D => two_dec_max_limit_nxt(6),
      Q => two_dec_max_limit(6),
      R => \neutral_max_limit_reg[11]_0\
    );
\two_dec_max_limit_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => pi_f_dec_reg_0,
      CE => '1',
      D => two_dec_max_limit_nxt(7),
      Q => two_dec_max_limit(7),
      R => \neutral_max_limit_reg[11]_0\
    );
\two_dec_max_limit_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => pi_f_dec_reg_0,
      CE => '1',
      D => two_dec_max_limit_nxt(8),
      Q => two_dec_max_limit(8),
      R => \neutral_max_limit_reg[11]_0\
    );
\two_dec_max_limit_reg[8]_i_1\: unisim.vcomponents.CARRY4
     port map (
      CI => \two_dec_max_limit_reg[4]_i_1_n_0\,
      CO(3) => \two_dec_max_limit_reg[8]_i_1_n_0\,
      CO(2) => \two_dec_max_limit_reg[8]_i_1_n_1\,
      CO(1) => \two_dec_max_limit_reg[8]_i_1_n_2\,
      CO(0) => \two_dec_max_limit_reg[8]_i_1_n_3\,
      CYINIT => '0',
      DI(3 downto 2) => B"00",
      DI(1) => device_temp_init(6),
      DI(0) => '0',
      O(3 downto 0) => two_dec_max_limit_nxt(8 downto 5),
      S(3 downto 2) => device_temp_init(8 downto 7),
      S(1) => \two_dec_max_limit[8]_i_2_n_0\,
      S(0) => device_temp_init(5)
    );
\two_dec_max_limit_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => pi_f_dec_reg_0,
      CE => '1',
      D => two_dec_max_limit_nxt(9),
      Q => two_dec_max_limit(9),
      R => \neutral_max_limit_reg[11]_0\
    );
\two_dec_min_limit[11]_i_2\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => one_dec_max_limit(11),
      O => \two_dec_min_limit[11]_i_2_n_0\
    );
\two_dec_min_limit[11]_i_3\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => one_dec_max_limit(10),
      O => \two_dec_min_limit[11]_i_3_n_0\
    );
\two_dec_min_limit[5]_i_2\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => one_dec_max_limit(5),
      O => \two_dec_min_limit[5]_i_2_n_0\
    );
\two_dec_min_limit[5]_i_3\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => one_dec_max_limit(4),
      O => \two_dec_min_limit[5]_i_3_n_0\
    );
\two_dec_min_limit[5]_i_4\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => one_dec_max_limit(3),
      O => \two_dec_min_limit[5]_i_4_n_0\
    );
\two_dec_min_limit[9]_i_2\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => one_dec_max_limit(9),
      O => \two_dec_min_limit[9]_i_2_n_0\
    );
\two_dec_min_limit[9]_i_3\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => one_dec_max_limit(8),
      O => \two_dec_min_limit[9]_i_3_n_0\
    );
\two_dec_min_limit[9]_i_4\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => one_dec_max_limit(7),
      O => \two_dec_min_limit[9]_i_4_n_0\
    );
\two_dec_min_limit[9]_i_5\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => one_dec_max_limit(6),
      O => \two_dec_min_limit[9]_i_5_n_0\
    );
\two_dec_min_limit_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => pi_f_dec_reg_0,
      CE => '1',
      D => two_dec_min_limit_nxt(10),
      Q => two_dec_min_limit(10),
      R => pi_f_dec_reg_1(0)
    );
\two_dec_min_limit_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => pi_f_dec_reg_0,
      CE => '1',
      D => two_dec_min_limit_nxt(11),
      Q => two_dec_min_limit(11),
      R => pi_f_dec_reg_1(0)
    );
\two_dec_min_limit_reg[11]_i_1\: unisim.vcomponents.CARRY4
     port map (
      CI => \two_dec_min_limit_reg[9]_i_1_n_0\,
      CO(3 downto 1) => \NLW_two_dec_min_limit_reg[11]_i_1_CO_UNCONNECTED\(3 downto 1),
      CO(0) => \two_dec_min_limit_reg[11]_i_1_n_3\,
      CYINIT => '0',
      DI(3 downto 1) => B"000",
      DI(0) => one_dec_max_limit(10),
      O(3 downto 2) => \NLW_two_dec_min_limit_reg[11]_i_1_O_UNCONNECTED\(3 downto 2),
      O(1 downto 0) => two_dec_min_limit_nxt(11 downto 10),
      S(3 downto 2) => B"00",
      S(1) => \two_dec_min_limit[11]_i_2_n_0\,
      S(0) => \two_dec_min_limit[11]_i_3_n_0\
    );
\two_dec_min_limit_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => pi_f_dec_reg_0,
      CE => '1',
      D => two_dec_min_limit_nxt(2),
      Q => two_dec_min_limit(2),
      R => pi_f_dec_reg_1(0)
    );
\two_dec_min_limit_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => pi_f_dec_reg_0,
      CE => '1',
      D => two_dec_min_limit_nxt(3),
      Q => two_dec_min_limit(3),
      R => pi_f_dec_reg_1(0)
    );
\two_dec_min_limit_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => pi_f_dec_reg_0,
      CE => '1',
      D => two_dec_min_limit_nxt(4),
      Q => two_dec_min_limit(4),
      R => pi_f_dec_reg_1(0)
    );
\two_dec_min_limit_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => pi_f_dec_reg_0,
      CE => '1',
      D => two_dec_min_limit_nxt(5),
      Q => two_dec_min_limit(5),
      R => pi_f_dec_reg_1(0)
    );
\two_dec_min_limit_reg[5]_i_1\: unisim.vcomponents.CARRY4
     port map (
      CI => '0',
      CO(3) => \two_dec_min_limit_reg[5]_i_1_n_0\,
      CO(2) => \two_dec_min_limit_reg[5]_i_1_n_1\,
      CO(1) => \two_dec_min_limit_reg[5]_i_1_n_2\,
      CO(0) => \two_dec_min_limit_reg[5]_i_1_n_3\,
      CYINIT => '0',
      DI(3 downto 1) => one_dec_max_limit(5 downto 3),
      DI(0) => '0',
      O(3 downto 0) => two_dec_min_limit_nxt(5 downto 2),
      S(3) => \two_dec_min_limit[5]_i_2_n_0\,
      S(2) => \two_dec_min_limit[5]_i_3_n_0\,
      S(1) => \two_dec_min_limit[5]_i_4_n_0\,
      S(0) => one_dec_max_limit(2)
    );
\two_dec_min_limit_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => pi_f_dec_reg_0,
      CE => '1',
      D => two_dec_min_limit_nxt(6),
      Q => two_dec_min_limit(6),
      R => pi_f_dec_reg_1(0)
    );
\two_dec_min_limit_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => pi_f_dec_reg_0,
      CE => '1',
      D => two_dec_min_limit_nxt(7),
      Q => two_dec_min_limit(7),
      R => pi_f_dec_reg_1(0)
    );
\two_dec_min_limit_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => pi_f_dec_reg_0,
      CE => '1',
      D => two_dec_min_limit_nxt(8),
      Q => two_dec_min_limit(8),
      R => pi_f_dec_reg_1(0)
    );
\two_dec_min_limit_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => pi_f_dec_reg_0,
      CE => '1',
      D => two_dec_min_limit_nxt(9),
      Q => two_dec_min_limit(9),
      R => pi_f_dec_reg_1(0)
    );
\two_dec_min_limit_reg[9]_i_1\: unisim.vcomponents.CARRY4
     port map (
      CI => \two_dec_min_limit_reg[5]_i_1_n_0\,
      CO(3) => \two_dec_min_limit_reg[9]_i_1_n_0\,
      CO(2) => \two_dec_min_limit_reg[9]_i_1_n_1\,
      CO(1) => \two_dec_min_limit_reg[9]_i_1_n_2\,
      CO(0) => \two_dec_min_limit_reg[9]_i_1_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => one_dec_max_limit(9 downto 6),
      O(3 downto 0) => two_dec_min_limit_nxt(9 downto 6),
      S(3) => \two_dec_min_limit[9]_i_2_n_0\,
      S(2) => \two_dec_min_limit[9]_i_3_n_0\,
      S(1) => \two_dec_min_limit[9]_i_4_n_0\,
      S(0) => \two_dec_min_limit[9]_i_5_n_0\
    );
\two_inc_max_limit[11]_i_2\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => device_temp_init(11),
      O => \two_inc_max_limit[11]_i_2_n_0\
    );
\two_inc_max_limit[11]_i_3\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => device_temp_init(10),
      O => \two_inc_max_limit[11]_i_3_n_0\
    );
\two_inc_max_limit[11]_i_4\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => device_temp_init(9),
      O => \two_inc_max_limit[11]_i_4_n_0\
    );
\two_inc_max_limit[1]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => device_temp_init(0),
      I1 => device_temp_init(1),
      O => \two_inc_max_limit[1]_i_1_n_0\
    );
\two_inc_max_limit[4]_i_2\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => device_temp_init(4),
      O => \two_inc_max_limit[4]_i_2_n_0\
    );
\two_inc_max_limit[4]_i_3\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => device_temp_init(3),
      O => \two_inc_max_limit[4]_i_3_n_0\
    );
\two_inc_max_limit[4]_i_4\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => device_temp_init(1),
      O => \two_inc_max_limit[4]_i_4_n_0\
    );
\two_inc_max_limit[8]_i_2\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => device_temp_init(7),
      O => \two_inc_max_limit[8]_i_2_n_0\
    );
\two_inc_max_limit_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => pi_f_dec_reg_0,
      CE => '1',
      D => two_inc_max_limit_nxt(10),
      Q => two_inc_max_limit(10),
      R => \device_temp_101_reg[0]_0\
    );
\two_inc_max_limit_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => pi_f_dec_reg_0,
      CE => '1',
      D => two_inc_max_limit_nxt(11),
      Q => two_inc_max_limit(11),
      R => \device_temp_101_reg[0]_0\
    );
\two_inc_max_limit_reg[11]_i_1\: unisim.vcomponents.CARRY4
     port map (
      CI => \two_inc_max_limit_reg[8]_i_1_n_0\,
      CO(3 downto 2) => \NLW_two_inc_max_limit_reg[11]_i_1_CO_UNCONNECTED\(3 downto 2),
      CO(1) => \two_inc_max_limit_reg[11]_i_1_n_2\,
      CO(0) => \two_inc_max_limit_reg[11]_i_1_n_3\,
      CYINIT => '0',
      DI(3 downto 2) => B"00",
      DI(1 downto 0) => device_temp_init(10 downto 9),
      O(3) => \NLW_two_inc_max_limit_reg[11]_i_1_O_UNCONNECTED\(3),
      O(2 downto 0) => two_inc_max_limit_nxt(11 downto 9),
      S(3) => '0',
      S(2) => \two_inc_max_limit[11]_i_2_n_0\,
      S(1) => \two_inc_max_limit[11]_i_3_n_0\,
      S(0) => \two_inc_max_limit[11]_i_4_n_0\
    );
\two_inc_max_limit_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => pi_f_dec_reg_0,
      CE => '1',
      D => \two_inc_max_limit[1]_i_1_n_0\,
      Q => two_inc_max_limit(1),
      R => \device_temp_101_reg[0]_0\
    );
\two_inc_max_limit_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => pi_f_dec_reg_0,
      CE => '1',
      D => two_inc_max_limit_nxt(2),
      Q => two_inc_max_limit(2),
      R => \device_temp_101_reg[0]_0\
    );
\two_inc_max_limit_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => pi_f_dec_reg_0,
      CE => '1',
      D => two_inc_max_limit_nxt(3),
      Q => two_inc_max_limit(3),
      R => \device_temp_101_reg[0]_0\
    );
\two_inc_max_limit_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => pi_f_dec_reg_0,
      CE => '1',
      D => two_inc_max_limit_nxt(4),
      Q => two_inc_max_limit(4),
      R => \device_temp_101_reg[0]_0\
    );
\two_inc_max_limit_reg[4]_i_1\: unisim.vcomponents.CARRY4
     port map (
      CI => '0',
      CO(3) => \two_inc_max_limit_reg[4]_i_1_n_0\,
      CO(2) => \two_inc_max_limit_reg[4]_i_1_n_1\,
      CO(1) => \two_inc_max_limit_reg[4]_i_1_n_2\,
      CO(0) => \two_inc_max_limit_reg[4]_i_1_n_3\,
      CYINIT => device_temp_init(0),
      DI(3 downto 2) => device_temp_init(4 downto 3),
      DI(1) => '0',
      DI(0) => device_temp_init(1),
      O(3 downto 1) => two_inc_max_limit_nxt(4 downto 2),
      O(0) => \NLW_two_inc_max_limit_reg[4]_i_1_O_UNCONNECTED\(0),
      S(3) => \two_inc_max_limit[4]_i_2_n_0\,
      S(2) => \two_inc_max_limit[4]_i_3_n_0\,
      S(1) => device_temp_init(2),
      S(0) => \two_inc_max_limit[4]_i_4_n_0\
    );
\two_inc_max_limit_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => pi_f_dec_reg_0,
      CE => '1',
      D => two_inc_max_limit_nxt(5),
      Q => two_inc_max_limit(5),
      R => \device_temp_101_reg[0]_0\
    );
\two_inc_max_limit_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => pi_f_dec_reg_0,
      CE => '1',
      D => two_inc_max_limit_nxt(6),
      Q => two_inc_max_limit(6),
      R => \device_temp_101_reg[0]_0\
    );
\two_inc_max_limit_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => pi_f_dec_reg_0,
      CE => '1',
      D => two_inc_max_limit_nxt(7),
      Q => two_inc_max_limit(7),
      R => \device_temp_101_reg[0]_0\
    );
\two_inc_max_limit_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => pi_f_dec_reg_0,
      CE => '1',
      D => two_inc_max_limit_nxt(8),
      Q => two_inc_max_limit(8),
      R => \device_temp_101_reg[0]_0\
    );
\two_inc_max_limit_reg[8]_i_1\: unisim.vcomponents.CARRY4
     port map (
      CI => \two_inc_max_limit_reg[4]_i_1_n_0\,
      CO(3) => \two_inc_max_limit_reg[8]_i_1_n_0\,
      CO(2) => \two_inc_max_limit_reg[8]_i_1_n_1\,
      CO(1) => \two_inc_max_limit_reg[8]_i_1_n_2\,
      CO(0) => \two_inc_max_limit_reg[8]_i_1_n_3\,
      CYINIT => '0',
      DI(3) => '0',
      DI(2) => device_temp_init(7),
      DI(1 downto 0) => B"00",
      O(3 downto 0) => two_inc_max_limit_nxt(8 downto 5),
      S(3) => device_temp_init(8),
      S(2) => \two_inc_max_limit[8]_i_2_n_0\,
      S(1 downto 0) => device_temp_init(6 downto 5)
    );
\two_inc_max_limit_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => pi_f_dec_reg_0,
      CE => '1',
      D => two_inc_max_limit_nxt(9),
      Q => two_inc_max_limit(9),
      R => \device_temp_101_reg[0]_0\
    );
\two_inc_min_limit[11]_i_2\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => three_inc_max_limit(11),
      O => \two_inc_min_limit[11]_i_2_n_0\
    );
\two_inc_min_limit[11]_i_3\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => three_inc_max_limit(10),
      O => \two_inc_min_limit[11]_i_3_n_0\
    );
\two_inc_min_limit[5]_i_2\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => three_inc_max_limit(5),
      O => \two_inc_min_limit[5]_i_2_n_0\
    );
\two_inc_min_limit[5]_i_3\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => three_inc_max_limit(4),
      O => \two_inc_min_limit[5]_i_3_n_0\
    );
\two_inc_min_limit[5]_i_4\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => three_inc_max_limit(3),
      O => \two_inc_min_limit[5]_i_4_n_0\
    );
\two_inc_min_limit[9]_i_2\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => three_inc_max_limit(9),
      O => \two_inc_min_limit[9]_i_2_n_0\
    );
\two_inc_min_limit[9]_i_3\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => three_inc_max_limit(8),
      O => \two_inc_min_limit[9]_i_3_n_0\
    );
\two_inc_min_limit[9]_i_4\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => three_inc_max_limit(7),
      O => \two_inc_min_limit[9]_i_4_n_0\
    );
\two_inc_min_limit[9]_i_5\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => three_inc_max_limit(6),
      O => \two_inc_min_limit[9]_i_5_n_0\
    );
\two_inc_min_limit_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => pi_f_dec_reg_0,
      CE => '1',
      D => two_inc_min_limit_nxt(10),
      Q => two_inc_min_limit(10),
      R => \four_dec_min_limit_reg[0]_0\
    );
\two_inc_min_limit_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => pi_f_dec_reg_0,
      CE => '1',
      D => two_inc_min_limit_nxt(11),
      Q => two_inc_min_limit(11),
      R => \four_dec_min_limit_reg[0]_0\
    );
\two_inc_min_limit_reg[11]_i_1\: unisim.vcomponents.CARRY4
     port map (
      CI => \two_inc_min_limit_reg[9]_i_1_n_0\,
      CO(3 downto 1) => \NLW_two_inc_min_limit_reg[11]_i_1_CO_UNCONNECTED\(3 downto 1),
      CO(0) => \two_inc_min_limit_reg[11]_i_1_n_3\,
      CYINIT => '0',
      DI(3 downto 1) => B"000",
      DI(0) => three_inc_max_limit(10),
      O(3 downto 2) => \NLW_two_inc_min_limit_reg[11]_i_1_O_UNCONNECTED\(3 downto 2),
      O(1 downto 0) => two_inc_min_limit_nxt(11 downto 10),
      S(3 downto 2) => B"00",
      S(1) => \two_inc_min_limit[11]_i_2_n_0\,
      S(0) => \two_inc_min_limit[11]_i_3_n_0\
    );
\two_inc_min_limit_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => pi_f_dec_reg_0,
      CE => '1',
      D => one_inc_max_limit(1),
      Q => two_inc_min_limit(1),
      R => \four_dec_min_limit_reg[0]_0\
    );
\two_inc_min_limit_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => pi_f_dec_reg_0,
      CE => '1',
      D => two_inc_min_limit_nxt(2),
      Q => two_inc_min_limit(2),
      R => \four_dec_min_limit_reg[0]_0\
    );
\two_inc_min_limit_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => pi_f_dec_reg_0,
      CE => '1',
      D => two_inc_min_limit_nxt(3),
      Q => two_inc_min_limit(3),
      R => \four_dec_min_limit_reg[0]_0\
    );
\two_inc_min_limit_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => pi_f_dec_reg_0,
      CE => '1',
      D => two_inc_min_limit_nxt(4),
      Q => two_inc_min_limit(4),
      R => \four_dec_min_limit_reg[0]_0\
    );
\two_inc_min_limit_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => pi_f_dec_reg_0,
      CE => '1',
      D => two_inc_min_limit_nxt(5),
      Q => two_inc_min_limit(5),
      R => \four_dec_min_limit_reg[0]_0\
    );
\two_inc_min_limit_reg[5]_i_1\: unisim.vcomponents.CARRY4
     port map (
      CI => '0',
      CO(3) => \two_inc_min_limit_reg[5]_i_1_n_0\,
      CO(2) => \two_inc_min_limit_reg[5]_i_1_n_1\,
      CO(1) => \two_inc_min_limit_reg[5]_i_1_n_2\,
      CO(0) => \two_inc_min_limit_reg[5]_i_1_n_3\,
      CYINIT => '0',
      DI(3 downto 1) => three_inc_max_limit(5 downto 3),
      DI(0) => '0',
      O(3 downto 0) => two_inc_min_limit_nxt(5 downto 2),
      S(3) => \two_inc_min_limit[5]_i_2_n_0\,
      S(2) => \two_inc_min_limit[5]_i_3_n_0\,
      S(1) => \two_inc_min_limit[5]_i_4_n_0\,
      S(0) => three_inc_max_limit(2)
    );
\two_inc_min_limit_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => pi_f_dec_reg_0,
      CE => '1',
      D => two_inc_min_limit_nxt(6),
      Q => two_inc_min_limit(6),
      R => \four_dec_min_limit_reg[0]_0\
    );
\two_inc_min_limit_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => pi_f_dec_reg_0,
      CE => '1',
      D => two_inc_min_limit_nxt(7),
      Q => two_inc_min_limit(7),
      R => \four_dec_min_limit_reg[0]_0\
    );
\two_inc_min_limit_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => pi_f_dec_reg_0,
      CE => '1',
      D => two_inc_min_limit_nxt(8),
      Q => two_inc_min_limit(8),
      R => \four_dec_min_limit_reg[0]_0\
    );
\two_inc_min_limit_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => pi_f_dec_reg_0,
      CE => '1',
      D => two_inc_min_limit_nxt(9),
      Q => two_inc_min_limit(9),
      R => \four_dec_min_limit_reg[0]_0\
    );
\two_inc_min_limit_reg[9]_i_1\: unisim.vcomponents.CARRY4
     port map (
      CI => \two_inc_min_limit_reg[5]_i_1_n_0\,
      CO(3) => \two_inc_min_limit_reg[9]_i_1_n_0\,
      CO(2) => \two_inc_min_limit_reg[9]_i_1_n_1\,
      CO(1) => \two_inc_min_limit_reg[9]_i_1_n_2\,
      CO(0) => \two_inc_min_limit_reg[9]_i_1_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => three_inc_max_limit(9 downto 6),
      O(3 downto 0) => two_inc_min_limit_nxt(9 downto 6),
      S(3) => \two_inc_min_limit[9]_i_2_n_0\,
      S(2) => \two_inc_min_limit[9]_i_3_n_0\,
      S(1) => \two_inc_min_limit[9]_i_4_n_0\,
      S(0) => \two_inc_min_limit[9]_i_5_n_0\
    );
update_temp_101: unisim.vcomponents.LUT3
    generic map(
      INIT => X"20"
    )
        port map (
      I0 => tempmon_init_complete,
      I1 => tempmon_sample_en_102,
      I2 => tempmon_sample_en_101,
      O => \update_temp_101__0\
    );
update_temp_102_reg: unisim.vcomponents.FDRE
     port map (
      C => pi_f_dec_reg_0,
      CE => '1',
      D => \update_temp_101__0\,
      Q => update_temp_102,
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mig_mig_7series_v4_2_ddr_phy_wrcal is
  port (
    wrcal_resume_w : out STD_LOGIC;
    E : out STD_LOGIC_VECTOR ( 0 to 0 );
    wrcal_prech_req : out STD_LOGIC;
    wrcal_done_reg_0 : out STD_LOGIC;
    wrcal_sanity_chk_done_reg_0 : out STD_LOGIC;
    wrlvl_byte_redo : out STD_LOGIC;
    early1_data_reg_0 : out STD_LOGIC;
    phy_if_reset_w : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[3]_0\ : out STD_LOGIC;
    done_dqs_dec238_out : out STD_LOGIC;
    Q : out STD_LOGIC_VECTOR ( 3 downto 0 );
    LD0 : out STD_LOGIC;
    LD0_0 : out STD_LOGIC;
    LD0_1 : out STD_LOGIC;
    LD0_2 : out STD_LOGIC;
    LD0_3 : out STD_LOGIC;
    LD0_4 : out STD_LOGIC;
    LD0_5 : out STD_LOGIC;
    LD0_6 : out STD_LOGIC;
    wrcal_done_reg_1 : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_0\ : out STD_LOGIC;
    early1_data_reg_1 : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[0]_0\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_0\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[0]_1\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[0]_2\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[0]_3\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    \po_stg2_wrcal_cnt_reg[0]_4\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    \po_stg2_wrcal_cnt_reg[0]_5\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    \po_stg2_wrcal_cnt_reg[0]_6\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    \po_stg2_wrcal_cnt_reg[1]_1\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    \po_stg2_wrcal_cnt_reg[0]_7\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    \po_stg2_wrcal_cnt_reg[0]_8\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    \po_stg2_wrcal_cnt_reg[1]_2\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    wrcal_done_reg_2 : out STD_LOGIC;
    wrcal_done_reg_3 : out STD_LOGIC;
    wrlvl_byte_redo_reg_0 : out STD_LOGIC;
    wrcal_done_reg_4 : out STD_LOGIC;
    wrcal_pat_resume_reg_0 : in STD_LOGIC;
    phy_rddata_en : in STD_LOGIC;
    wrcal_sanity_chk : in STD_LOGIC;
    p_0_out : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg[1]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg[2]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg[3]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg[4]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg[5]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg[6]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg[7]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg[0]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg[1]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg[2]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg[3]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg[4]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg[5]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg[6]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg[0]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg[1]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg[2]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg[3]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg[4]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg[5]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg[6]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg[7]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise2_r_reg[0]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg[1]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg[2]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg[3]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise2_r_reg[4]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg[5]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg[6]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg[7]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg[0]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg[1]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg[2]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg[3]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg[4]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg[5]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg[6]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg[7]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg[0]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg[1]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg[2]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise3_r_reg[3]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg[4]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg[5]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg[6]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise3_r_reg[7]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg[0]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg[1]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg[2]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg[3]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg[4]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg[5]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg[6]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg[7]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg[0]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg[1]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg[2]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg[3]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg[4]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg[5]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg[6]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg[7]_0\ : in STD_LOGIC;
    cal2_if_reset_reg_0 : in STD_LOGIC;
    cal2_done_r_reg_0 : in STD_LOGIC_VECTOR ( 0 to 0 );
    wrlvl_byte_done : in STD_LOGIC;
    \corse_cnt[0][2]_i_3\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \corse_cnt[0][2]_i_3_0\ : in STD_LOGIC;
    idelay_ce_int : in STD_LOGIC;
    \input_[9].iserdes_dq_.idelay_dq.idelaye2\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    calib_in_common : in STD_LOGIC;
    \input_[9].iserdes_dq_.idelay_dq.idelaye2_0\ : in STD_LOGIC;
    \input_[9].iserdes_dq_.idelay_dq.idelaye2_1\ : in STD_LOGIC;
    idelay_ld_rst : in STD_LOGIC;
    idelay_ld_rst_7 : in STD_LOGIC;
    idelay_ld_rst_8 : in STD_LOGIC;
    idelay_ld_rst_9 : in STD_LOGIC;
    idelay_ld_rst_10 : in STD_LOGIC;
    idelay_ld_rst_11 : in STD_LOGIC;
    idelay_ld_rst_12 : in STD_LOGIC;
    idelay_ld_rst_13 : in STD_LOGIC;
    wrlvl_byte_redo_r : in STD_LOGIC;
    \wrlvl_redo_corse_inc[2]_i_7\ : in STD_LOGIC;
    \wrlvl_redo_corse_inc[2]_i_7_0\ : in STD_LOGIC;
    \idelay_tap_cnt_r_reg[0][4][4]\ : in STD_LOGIC;
    \idelay_tap_cnt_r_reg[0][4][4]_0\ : in STD_LOGIC;
    \idelay_tap_cnt_r_reg[0][4][4]_1\ : in STD_LOGIC;
    \idelay_tap_cnt_r_reg[0][0][4]\ : in STD_LOGIC;
    \idelay_tap_cnt_r_reg[0][0][4]_0\ : in STD_LOGIC;
    \idelay_tap_cnt_r_reg[0][5][4]\ : in STD_LOGIC;
    \idelay_tap_cnt_r_reg[0][5][4]_0\ : in STD_LOGIC;
    \idelay_tap_cnt_r_reg[0][6][4]\ : in STD_LOGIC;
    \idelay_tap_cnt_r_reg[0][7][4]\ : in STD_LOGIC;
    \idelay_tap_cnt_r_reg[0][1][4]\ : in STD_LOGIC;
    \idelay_tap_cnt_r_reg[0][2][4]\ : in STD_LOGIC;
    \init_state_r[3]_i_13\ : in STD_LOGIC;
    wrlvl_done_r1 : in STD_LOGIC;
    \init_state_r[2]_i_14\ : in STD_LOGIC;
    \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[508]\ : in STD_LOGIC;
    \init_state_r[3]_i_13_0\ : in STD_LOGIC;
    \init_state_r[4]_i_27\ : in STD_LOGIC;
    \not_empty_wait_cnt_reg[4]_0\ : in STD_LOGIC;
    wrcal_rd_wait : in STD_LOGIC;
    prech_done : in STD_LOGIC;
    \cal2_state_r_reg[0]_0\ : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of mig_mig_7series_v4_2_ddr_phy_wrcal : entity is "mig_7series_v4_2_ddr_phy_wrcal";
end mig_mig_7series_v4_2_ddr_phy_wrcal;

architecture STRUCTURE of mig_mig_7series_v4_2_ddr_phy_wrcal is
  signal \^e\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \^q\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal cal2_done_r : STD_LOGIC;
  signal cal2_done_r_i_1_n_0 : STD_LOGIC;
  signal cal2_if_reset_i_1_n_0 : STD_LOGIC;
  signal cal2_if_reset_i_2_n_0 : STD_LOGIC;
  signal cal2_if_reset_i_3_n_0 : STD_LOGIC;
  signal cal2_if_reset_i_4_n_0 : STD_LOGIC;
  signal cal2_if_reset_i_5_n_0 : STD_LOGIC;
  signal cal2_prech_req_r : STD_LOGIC;
  signal cal2_prech_req_r_i_1_n_0 : STD_LOGIC;
  signal cal2_prech_req_r_i_2_n_0 : STD_LOGIC;
  signal cal2_state_r : STD_LOGIC;
  signal \cal2_state_r[0]_i_2_n_0\ : STD_LOGIC;
  signal \cal2_state_r[0]_i_3_n_0\ : STD_LOGIC;
  signal \cal2_state_r[0]_i_4_n_0\ : STD_LOGIC;
  signal \cal2_state_r[0]_i_5_n_0\ : STD_LOGIC;
  signal \cal2_state_r[1]_i_2_n_0\ : STD_LOGIC;
  signal \cal2_state_r[1]_i_3_n_0\ : STD_LOGIC;
  signal \cal2_state_r[1]_i_4_n_0\ : STD_LOGIC;
  signal \cal2_state_r[2]_i_1_n_0\ : STD_LOGIC;
  signal \cal2_state_r[2]_i_2_n_0\ : STD_LOGIC;
  signal \cal2_state_r[2]_i_3_n_0\ : STD_LOGIC;
  signal \cal2_state_r[3]_i_2_n_0\ : STD_LOGIC;
  signal \cal2_state_r[3]_i_3_n_0\ : STD_LOGIC;
  signal \cal2_state_r[3]_i_4_n_0\ : STD_LOGIC;
  signal \cal2_state_r[3]_i_5_n_0\ : STD_LOGIC;
  signal \cal2_state_r[3]_i_6_n_0\ : STD_LOGIC;
  signal \cal2_state_r[3]_i_7_n_0\ : STD_LOGIC;
  signal \cal2_state_r[3]_i_8_n_0\ : STD_LOGIC;
  signal \cal2_state_r[3]_i_9_n_0\ : STD_LOGIC;
  signal \cal2_state_r_reg[0]_i_1_n_0\ : STD_LOGIC;
  signal \cal2_state_r_reg[1]_i_1_n_0\ : STD_LOGIC;
  signal \cal2_state_r_reg_n_0_[0]\ : STD_LOGIC;
  signal \cal2_state_r_reg_n_0_[1]\ : STD_LOGIC;
  signal \cal2_state_r_reg_n_0_[2]\ : STD_LOGIC;
  signal \cal2_state_r_reg_n_0_[3]\ : STD_LOGIC;
  signal \^done_dqs_dec238_out\ : STD_LOGIC;
  signal early1_data_i_1_n_0 : STD_LOGIC;
  signal early1_data_i_2_n_0 : STD_LOGIC;
  signal early1_data_i_3_n_0 : STD_LOGIC;
  signal early1_data_match_r0 : STD_LOGIC;
  signal \^early1_data_reg_0\ : STD_LOGIC;
  signal early1_match_fall0_and_r : STD_LOGIC;
  signal early1_match_fall0_r : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal early1_match_fall1_and_r : STD_LOGIC;
  signal early1_match_fall2_and_r : STD_LOGIC;
  signal early1_match_fall3_and_r : STD_LOGIC;
  signal early1_match_rise0_and_r : STD_LOGIC;
  signal early1_match_rise0_r : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal early1_match_rise1_and_r : STD_LOGIC;
  signal early1_match_rise2_and_r : STD_LOGIC;
  signal early1_match_rise3_and_r : STD_LOGIC;
  signal early2_data_i_1_n_0 : STD_LOGIC;
  signal early2_data_match_r0 : STD_LOGIC;
  signal early2_data_reg_n_0 : STD_LOGIC;
  signal early2_match_fall0_and_r : STD_LOGIC;
  signal early2_match_fall0_r : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal early2_match_fall1_and_r : STD_LOGIC;
  signal early2_match_fall1_r : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal early2_match_fall2_and_r : STD_LOGIC;
  signal early2_match_fall2_r : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal early2_match_fall3_and_r : STD_LOGIC;
  signal early2_match_fall3_r : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal early2_match_rise0_and_r : STD_LOGIC;
  signal early2_match_rise0_r : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal early2_match_rise1_and_r : STD_LOGIC;
  signal early2_match_rise1_r : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal early2_match_rise2_and_r : STD_LOGIC;
  signal early2_match_rise2_r : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal early2_match_rise3_and_r : STD_LOGIC;
  signal early2_match_rise3_r : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg_n_0_[0]\ : STD_LOGIC;
  signal \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg_n_0_[0]\ : STD_LOGIC;
  signal \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg_n_0_[0]\ : STD_LOGIC;
  signal \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg_n_0_[0]\ : STD_LOGIC;
  signal \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg_n_0_[0]\ : STD_LOGIC;
  signal \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg_n_0_[0]\ : STD_LOGIC;
  signal \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise2_r_reg_n_0_[0]\ : STD_LOGIC;
  signal \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg_n_0_[0]\ : STD_LOGIC;
  signal \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg_n_0_[1]\ : STD_LOGIC;
  signal \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg_n_0_[1]\ : STD_LOGIC;
  signal \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg_n_0_[1]\ : STD_LOGIC;
  signal \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg_n_0_[1]\ : STD_LOGIC;
  signal \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg_n_0_[1]\ : STD_LOGIC;
  signal \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg_n_0_[1]\ : STD_LOGIC;
  signal \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg_n_0_[1]\ : STD_LOGIC;
  signal \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg_n_0_[1]\ : STD_LOGIC;
  signal \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg_n_0_[2]\ : STD_LOGIC;
  signal \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg_n_0_[2]\ : STD_LOGIC;
  signal \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg_n_0_[2]\ : STD_LOGIC;
  signal \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg_n_0_[2]\ : STD_LOGIC;
  signal \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg_n_0_[2]\ : STD_LOGIC;
  signal \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg_n_0_[2]\ : STD_LOGIC;
  signal \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg_n_0_[2]\ : STD_LOGIC;
  signal \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg_n_0_[2]\ : STD_LOGIC;
  signal \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg_n_0_[3]\ : STD_LOGIC;
  signal \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg_n_0_[3]\ : STD_LOGIC;
  signal \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg_n_0_[3]\ : STD_LOGIC;
  signal \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg_n_0_[3]\ : STD_LOGIC;
  signal \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg_n_0_[3]\ : STD_LOGIC;
  signal \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg_n_0_[3]\ : STD_LOGIC;
  signal \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg_n_0_[3]\ : STD_LOGIC;
  signal \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise3_r_reg_n_0_[3]\ : STD_LOGIC;
  signal \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg_n_0_[4]\ : STD_LOGIC;
  signal \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg_n_0_[4]\ : STD_LOGIC;
  signal \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg_n_0_[4]\ : STD_LOGIC;
  signal \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg_n_0_[4]\ : STD_LOGIC;
  signal \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg_n_0_[4]\ : STD_LOGIC;
  signal \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg_n_0_[4]\ : STD_LOGIC;
  signal \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise2_r_reg_n_0_[4]\ : STD_LOGIC;
  signal \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg_n_0_[4]\ : STD_LOGIC;
  signal \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg_n_0_[5]\ : STD_LOGIC;
  signal \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg_n_0_[5]\ : STD_LOGIC;
  signal \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg_n_0_[5]\ : STD_LOGIC;
  signal \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg_n_0_[5]\ : STD_LOGIC;
  signal \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg_n_0_[5]\ : STD_LOGIC;
  signal \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg_n_0_[5]\ : STD_LOGIC;
  signal \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg_n_0_[5]\ : STD_LOGIC;
  signal \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg_n_0_[5]\ : STD_LOGIC;
  signal \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg_n_0_[6]\ : STD_LOGIC;
  signal \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg_n_0_[6]\ : STD_LOGIC;
  signal \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg_n_0_[6]\ : STD_LOGIC;
  signal \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg_n_0_[6]\ : STD_LOGIC;
  signal \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg_n_0_[6]\ : STD_LOGIC;
  signal \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg_n_0_[6]\ : STD_LOGIC;
  signal \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg_n_0_[6]\ : STD_LOGIC;
  signal \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg_n_0_[6]\ : STD_LOGIC;
  signal \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg_n_0_[7]\ : STD_LOGIC;
  signal \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg_n_0_[7]\ : STD_LOGIC;
  signal \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg_n_0_[7]\ : STD_LOGIC;
  signal \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg_n_0_[7]\ : STD_LOGIC;
  signal \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg_n_0_[7]\ : STD_LOGIC;
  signal \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg_n_0_[7]\ : STD_LOGIC;
  signal \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg_n_0_[7]\ : STD_LOGIC;
  signal \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise3_r_reg_n_0_[7]\ : STD_LOGIC;
  signal \gen_pat_match_div4.early1_data_match_r_i_2_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.early1_data_match_r_reg_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.early1_match_fall0_and_r_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.early1_match_fall0_and_r_i_2_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.early1_match_fall1_and_r_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.early1_match_fall1_and_r_i_2_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.early1_match_fall2_and_r_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.early1_match_fall2_and_r_i_2_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.early1_match_fall3_and_r_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.early1_match_fall3_and_r_i_2_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.early1_match_rise0_and_r_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.early1_match_rise0_and_r_i_2_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.early1_match_rise1_and_r_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.early1_match_rise1_and_r_i_2_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.early1_match_rise2_and_r_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.early1_match_rise2_and_r_i_2_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.early1_match_rise3_and_r_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.early1_match_rise3_and_r_i_2_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.early2_data_match_r_i_2_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.early2_data_match_r_reg_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.early2_match_fall0_and_r_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.early2_match_fall0_and_r_i_2_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.early2_match_fall1_and_r_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.early2_match_fall1_and_r_i_2_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.early2_match_fall2_and_r_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.early2_match_fall2_and_r_i_2_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.early2_match_fall3_and_r_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.early2_match_fall3_and_r_i_2_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.early2_match_rise0_and_r_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.early2_match_rise0_and_r_i_2_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.early2_match_rise1_and_r_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.early2_match_rise1_and_r_i_2_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.early2_match_rise2_and_r_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.early2_match_rise2_and_r_i_2_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.early2_match_rise3_and_r_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.early2_match_rise3_and_r_i_2_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[0].early1_match_fall1_r[0]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[0].early1_match_fall3_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[0].early1_match_rise0_r[0]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[0].early2_match_rise3_r[0]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[0].pat_match_fall0_r[0]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[0].pat_match_fall1_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[0].pat_match_fall2_r[0]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[0].pat_match_fall2_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[0].pat_match_fall3_r[0]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[0].pat_match_rise1_r[0]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[0].pat_match_rise1_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[0].pat_match_rise3_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[1].early1_match_fall3_r[1]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[1].early1_match_rise1_r[1]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[1].early2_match_fall2_r[1]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[1].early2_match_rise0_r[1]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[1].pat_match_fall0_r[1]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[1].pat_match_fall1_r[1]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[1].pat_match_fall1_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[1].pat_match_fall2_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[1].pat_match_fall3_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[1].pat_match_rise1_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[1].pat_match_rise2_r[1]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[1].pat_match_rise2_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[1].pat_match_rise3_r[1]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[1].pat_match_rise3_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[2].early1_match_fall1_r[2]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[2].early1_match_fall1_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[2].early1_match_fall2_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[2].early1_match_fall3_r[2]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[2].early1_match_fall3_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[2].early1_match_rise0_r[2]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[2].early1_match_rise1_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[2].early1_match_rise2_r[2]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[2].pat_match_fall0_r[2]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[2].pat_match_fall2_r[2]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[2].pat_match_rise1_r[2]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[2].pat_match_rise2_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[2].pat_match_rise3_r[2]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[2].pat_match_rise3_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[3].early1_match_fall1_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[3].early1_match_fall2_r[3]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[3].early1_match_rise1_r[3]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[3].early1_match_rise1_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[3].early2_match_rise0_r[3]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[3].pat_match_fall0_r[3]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[3].pat_match_fall1_r[3]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[3].pat_match_fall2_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[3].pat_match_fall3_r[3]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[3].pat_match_rise2_r[3]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[3].pat_match_rise2_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[4].early1_match_fall1_r[4]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[4].early1_match_fall3_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[4].early1_match_rise0_r[4]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[4].early2_match_rise3_r[4]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[4].pat_match_fall0_r[4]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[4].pat_match_fall1_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[4].pat_match_fall2_r[4]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[4].pat_match_fall2_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[4].pat_match_fall3_r[4]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[4].pat_match_rise1_r[4]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[4].pat_match_rise1_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[4].pat_match_rise3_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[5].early1_match_fall3_r[5]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[5].early1_match_rise1_r[5]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[5].early2_match_fall2_r[5]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[5].early2_match_rise0_r[5]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[5].pat_match_fall0_r[5]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[5].pat_match_fall1_r[5]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[5].pat_match_fall1_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[5].pat_match_fall2_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[5].pat_match_fall3_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[5].pat_match_rise1_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[5].pat_match_rise2_r[5]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[5].pat_match_rise2_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[5].pat_match_rise3_r[5]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[5].pat_match_rise3_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[6].early1_match_fall1_r[6]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[6].early1_match_fall1_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[6].early1_match_fall2_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[6].early1_match_fall3_r[6]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[6].early1_match_fall3_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[6].early1_match_rise0_r[6]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[6].early1_match_rise1_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[6].early1_match_rise2_r[6]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[6].pat_match_fall0_r[6]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[6].pat_match_fall2_r[6]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[6].pat_match_rise1_r[6]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[6].pat_match_rise2_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[6].pat_match_rise3_r[6]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[6].pat_match_rise3_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[7].early1_match_fall1_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[7].early1_match_fall2_r[7]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[7].early1_match_rise1_r[7]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[7].early1_match_rise1_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[7].early2_match_rise0_r[7]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[7].pat_match_fall0_r[7]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[7].pat_match_fall1_r[7]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[7].pat_match_fall2_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[7].pat_match_fall3_r[7]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[7].pat_match_rise2_r[7]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[7].pat_match_rise2_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.pat_data_match_r_i_2_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.pat_data_match_r_reg_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.pat_data_match_valid_r_reg_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.pat_match_fall0_and_r_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.pat_match_fall1_and_r_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.pat_match_fall2_and_r_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.pat_match_fall3_and_r_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.pat_match_rise0_and_r_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.pat_match_rise1_and_r_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.pat_match_rise2_and_r_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.pat_match_rise3_and_r_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr[0].sr_fall0_r_reg[0]_263\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr[0].sr_fall1_r_reg[0]_303\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr[0].sr_fall2_r_reg[0]_279\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr[0].sr_fall3_r_reg[0]_255\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr[0].sr_rise0_r_reg[0]_295\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr[0].sr_rise1_r_reg[0]_247\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr[0].sr_rise2_r_reg[0]_271\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr[0].sr_rise3_r_reg[0]_287\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr[1].sr_fall0_r_reg[1]_264\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr[1].sr_fall1_r_reg[1]_304\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr[1].sr_fall2_r_reg[1]_280\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr[1].sr_fall3_r_reg[1]_256\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr[1].sr_rise0_r_reg[1]_296\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr[1].sr_rise1_r_reg[1]_248\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr[1].sr_rise2_r_reg[1]_272\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr[1].sr_rise3_r_reg[1]_288\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr[2].sr_fall0_r_reg[2]_265\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr[2].sr_fall1_r_reg[2]_305\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr[2].sr_fall2_r_reg[2]_281\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr[2].sr_fall3_r_reg[2]_257\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr[2].sr_rise0_r_reg[2]_297\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr[2].sr_rise1_r_reg[2]_249\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr[2].sr_rise2_r_reg[2]_273\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr[2].sr_rise3_r_reg[2]_289\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr[3].sr_fall0_r_reg[3]_266\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr[3].sr_fall1_r_reg[3]_306\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr[3].sr_fall2_r_reg[3]_282\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr[3].sr_fall3_r_reg[3]_258\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr[3].sr_rise0_r_reg[3]_298\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr[3].sr_rise1_r_reg[3]_250\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr[3].sr_rise2_r_reg[3]_274\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr[3].sr_rise3_r_reg[3]_290\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr[4].sr_fall0_r_reg[4]_267\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr[4].sr_fall1_r_reg[4]_307\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr[4].sr_fall2_r_reg[4]_283\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr[4].sr_fall3_r_reg[4]_259\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr[4].sr_rise0_r_reg[4]_299\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr[4].sr_rise1_r_reg[4]_251\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr[4].sr_rise2_r_reg[4]_275\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr[4].sr_rise3_r_reg[4]_291\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr[5].sr_fall0_r_reg[5]_268\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr[5].sr_fall1_r_reg[5]_308\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr[5].sr_fall2_r_reg[5]_284\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr[5].sr_fall3_r_reg[5]_260\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr[5].sr_rise0_r_reg[5]_300\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr[5].sr_rise1_r_reg[5]_252\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr[5].sr_rise2_r_reg[5]_276\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr[5].sr_rise3_r_reg[5]_292\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr[6].sr_fall0_r_reg[6]_269\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr[6].sr_fall1_r_reg[6]_309\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr[6].sr_fall2_r_reg[6]_285\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr[6].sr_fall3_r_reg[6]_261\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr[6].sr_rise0_r_reg[6]_301\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr[6].sr_rise1_r_reg[6]_253\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr[6].sr_rise2_r_reg[6]_277\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr[6].sr_rise3_r_reg[6]_293\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr[7].sr_fall0_r_reg[7]_270\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr[7].sr_fall1_r_reg[7]_310\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr[7].sr_fall2_r_reg[7]_286\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr[7].sr_fall3_r_reg[7]_262\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr[7].sr_rise0_r_reg[7]_302\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr[7].sr_rise1_r_reg[7]_254\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr[7].sr_rise2_r_reg[7]_278\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr[7].sr_rise3_r_reg[7]_294\ : STD_LOGIC;
  signal idelay_ld : STD_LOGIC;
  signal idelay_ld_done_i_1_n_0 : STD_LOGIC;
  signal idelay_ld_done_i_2_n_0 : STD_LOGIC;
  signal idelay_ld_done_reg_n_0 : STD_LOGIC;
  signal idelay_ld_i_1_n_0 : STD_LOGIC;
  signal idelay_ld_i_2_n_0 : STD_LOGIC;
  signal \idelay_tap_cnt_r[0][0][4]_i_5_n_0\ : STD_LOGIC;
  signal \idelay_tap_cnt_r[0][4][4]_i_3_n_0\ : STD_LOGIC;
  signal \not_empty_wait_cnt[4]_i_1_n_0\ : STD_LOGIC;
  signal \not_empty_wait_cnt_reg_n_0_[0]\ : STD_LOGIC;
  signal \not_empty_wait_cnt_reg_n_0_[1]\ : STD_LOGIC;
  signal \not_empty_wait_cnt_reg_n_0_[2]\ : STD_LOGIC;
  signal \not_empty_wait_cnt_reg_n_0_[3]\ : STD_LOGIC;
  signal \not_empty_wait_cnt_reg_n_0_[4]\ : STD_LOGIC;
  signal p_0_in : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal \p_0_in__0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal p_1_in : STD_LOGIC;
  signal pat_data_match_r0 : STD_LOGIC;
  signal pat_match_fall0_and_r : STD_LOGIC;
  signal pat_match_fall1_and_r : STD_LOGIC;
  signal pat_match_fall2_and_r : STD_LOGIC;
  signal pat_match_fall3_and_r : STD_LOGIC;
  signal pat_match_rise0_and_r : STD_LOGIC;
  signal pat_match_rise1_and_r : STD_LOGIC;
  signal pat_match_rise2_and_r : STD_LOGIC;
  signal pat_match_rise3_and_r : STD_LOGIC;
  signal \^phy_if_reset_w\ : STD_LOGIC;
  signal rd_active_r1 : STD_LOGIC;
  signal rd_active_r3_reg_srl2_n_0 : STD_LOGIC;
  signal \tap_inc_wait_cnt[3]_i_1_n_0\ : STD_LOGIC;
  signal tap_inc_wait_cnt_reg : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal wrcal_done_i_1_n_0 : STD_LOGIC;
  signal \^wrcal_done_reg_0\ : STD_LOGIC;
  signal wrcal_dqs_cnt_r : STD_LOGIC_VECTOR ( 3 to 3 );
  signal \wrcal_dqs_cnt_r[0]_i_1_n_0\ : STD_LOGIC;
  signal \wrcal_dqs_cnt_r[1]_i_1_n_0\ : STD_LOGIC;
  signal \wrcal_dqs_cnt_r[2]_i_1_n_0\ : STD_LOGIC;
  signal \wrcal_dqs_cnt_r[3]_i_1_n_0\ : STD_LOGIC;
  signal \wrcal_dqs_cnt_r[3]_i_2_n_0\ : STD_LOGIC;
  signal \wrcal_dqs_cnt_r[3]_i_3_n_0\ : STD_LOGIC;
  signal \wrcal_dqs_cnt_r[3]_i_4_n_0\ : STD_LOGIC;
  signal \wrcal_dqs_cnt_r_reg_n_0_[0]\ : STD_LOGIC;
  signal \wrcal_dqs_cnt_r_reg_n_0_[1]\ : STD_LOGIC;
  signal \wrcal_dqs_cnt_r_reg_n_0_[2]\ : STD_LOGIC;
  signal wrcal_pat_resume_r : STD_LOGIC;
  signal wrcal_pat_resume_r2_reg_srl2_n_0 : STD_LOGIC;
  signal wrcal_pat_resume_r_i_1_n_0 : STD_LOGIC;
  signal wrcal_pat_resume_r_i_2_n_0 : STD_LOGIC;
  signal wrcal_pat_resume_r_i_3_n_0 : STD_LOGIC;
  signal wrcal_sanity_chk_done_i_1_n_0 : STD_LOGIC;
  signal \^wrcal_sanity_chk_done_reg_0\ : STD_LOGIC;
  signal wrcal_sanity_chk_r_reg_n_0 : STD_LOGIC;
  signal wrlvl_byte_done_r : STD_LOGIC;
  signal \^wrlvl_byte_redo\ : STD_LOGIC;
  signal wrlvl_byte_redo_i_1_n_0 : STD_LOGIC;
  signal wrlvl_byte_redo_i_2_n_0 : STD_LOGIC;
  signal wrlvl_byte_redo_i_3_n_0 : STD_LOGIC;
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of cal2_done_r_i_2 : label is "soft_lutpair533";
  attribute SOFT_HLUTNM of cal2_prech_req_r_i_2 : label is "soft_lutpair549";
  attribute SOFT_HLUTNM of \cal2_state_r[3]_i_6\ : label is "soft_lutpair533";
  attribute SOFT_HLUTNM of \cal2_state_r[3]_i_7\ : label is "soft_lutpair547";
  attribute SOFT_HLUTNM of \cal2_state_r[3]_i_9\ : label is "soft_lutpair537";
  attribute SOFT_HLUTNM of \corse_cnt[0][2]_i_10\ : label is "soft_lutpair534";
  attribute SOFT_HLUTNM of \corse_cnt[1][2]_i_3\ : label is "soft_lutpair536";
  attribute SOFT_HLUTNM of \corse_cnt[2][2]_i_3\ : label is "soft_lutpair554";
  attribute SOFT_HLUTNM of \corse_cnt[3][2]_i_3\ : label is "soft_lutpair554";
  attribute SOFT_HLUTNM of early1_data_i_3 : label is "soft_lutpair537";
  attribute SOFT_HLUTNM of \gen_pat_match_div4.early1_match_fall1_and_r_i_2\ : label is "soft_lutpair543";
  attribute SOFT_HLUTNM of \gen_pat_match_div4.early1_match_fall3_and_r_i_2\ : label is "soft_lutpair540";
  attribute SOFT_HLUTNM of \gen_pat_match_div4.early1_match_rise1_and_r_i_2\ : label is "soft_lutpair545";
  attribute SOFT_HLUTNM of \gen_pat_match_div4.early1_match_rise2_and_r_i_1\ : label is "soft_lutpair544";
  attribute SOFT_HLUTNM of \gen_pat_match_div4.early2_match_fall0_and_r_i_2\ : label is "soft_lutpair546";
  attribute SOFT_HLUTNM of \gen_pat_match_div4.early2_match_fall1_and_r_i_1\ : label is "soft_lutpair543";
  attribute SOFT_HLUTNM of \gen_pat_match_div4.early2_match_fall3_and_r_i_1\ : label is "soft_lutpair540";
  attribute SOFT_HLUTNM of \gen_pat_match_div4.early2_match_rise0_and_r_i_2\ : label is "soft_lutpair542";
  attribute SOFT_HLUTNM of \gen_pat_match_div4.early2_match_rise1_and_r_i_1\ : label is "soft_lutpair545";
  attribute SOFT_HLUTNM of \gen_pat_match_div4.early2_match_rise2_and_r_i_2\ : label is "soft_lutpair544";
  attribute SOFT_HLUTNM of \gen_pat_match_div4.pat_match_fall0_and_r_i_1\ : label is "soft_lutpair546";
  attribute SOFT_HLUTNM of \gen_pat_match_div4.pat_match_rise0_and_r_i_1\ : label is "soft_lutpair542";
  attribute SOFT_HLUTNM of idelay_ld_done_i_2 : label is "soft_lutpair547";
  attribute SOFT_HLUTNM of \idelay_tap_cnt_r[0][0][4]_i_5\ : label is "soft_lutpair548";
  attribute SOFT_HLUTNM of \idelay_tap_cnt_r[0][2][4]_i_1\ : label is "soft_lutpair534";
  attribute SOFT_HLUTNM of \idelay_tap_cnt_r[0][4][4]_i_3\ : label is "soft_lutpair548";
  attribute SOFT_HLUTNM of \idelay_tap_cnt_r[0][6][4]_i_1\ : label is "soft_lutpair536";
  attribute SOFT_HLUTNM of \init_state_r[2]_i_35\ : label is "soft_lutpair535";
  attribute SOFT_HLUTNM of \init_state_r[4]_i_28\ : label is "soft_lutpair552";
  attribute SOFT_HLUTNM of \not_empty_wait_cnt[1]_i_1\ : label is "soft_lutpair553";
  attribute SOFT_HLUTNM of \not_empty_wait_cnt[2]_i_1\ : label is "soft_lutpair553";
  attribute SOFT_HLUTNM of \not_empty_wait_cnt[3]_i_1\ : label is "soft_lutpair538";
  attribute SOFT_HLUTNM of \not_empty_wait_cnt[4]_i_2\ : label is "soft_lutpair538";
  attribute srl_name : string;
  attribute srl_name of rd_active_r3_reg_srl2 : label is "\u_mig_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_wrcal/rd_active_r3_reg_srl2 ";
  attribute SOFT_HLUTNM of \tap_inc_wait_cnt[0]_i_1\ : label is "soft_lutpair555";
  attribute SOFT_HLUTNM of \tap_inc_wait_cnt[1]_i_1\ : label is "soft_lutpair555";
  attribute SOFT_HLUTNM of \tap_inc_wait_cnt[2]_i_1\ : label is "soft_lutpair550";
  attribute SOFT_HLUTNM of \tap_inc_wait_cnt[3]_i_2\ : label is "soft_lutpair550";
  attribute SOFT_HLUTNM of \wl_tap_count_r[5]_i_3\ : label is "soft_lutpair552";
  attribute SOFT_HLUTNM of wrcal_done_i_1 : label is "soft_lutpair539";
  attribute SOFT_HLUTNM of \wrcal_dqs_cnt_r[0]_i_1\ : label is "soft_lutpair551";
  attribute SOFT_HLUTNM of \wrcal_dqs_cnt_r[1]_i_1\ : label is "soft_lutpair551";
  attribute SOFT_HLUTNM of \wrcal_dqs_cnt_r[2]_i_1\ : label is "soft_lutpair549";
  attribute SOFT_HLUTNM of \wrcal_dqs_cnt_r[3]_i_2\ : label is "soft_lutpair541";
  attribute SOFT_HLUTNM of \wrcal_dqs_cnt_r[3]_i_4\ : label is "soft_lutpair541";
  attribute syn_maxfan : string;
  attribute syn_maxfan of \wrcal_dqs_cnt_r_reg[0]\ : label is "10";
  attribute syn_maxfan of \wrcal_dqs_cnt_r_reg[1]\ : label is "10";
  attribute syn_maxfan of \wrcal_dqs_cnt_r_reg[2]\ : label is "10";
  attribute syn_maxfan of \wrcal_dqs_cnt_r_reg[3]\ : label is "10";
  attribute srl_name of wrcal_pat_resume_r2_reg_srl2 : label is "\u_mig_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_wrcal/wrcal_pat_resume_r2_reg_srl2 ";
  attribute SOFT_HLUTNM of \wrdq_div1_4to1_wrcal_first.phy_wrdata[445]_i_1\ : label is "soft_lutpair539";
  attribute SOFT_HLUTNM of \wrdq_div1_4to1_wrcal_first.phy_wrdata[508]_i_1\ : label is "soft_lutpair535";
begin
  E(0) <= \^e\(0);
  Q(3 downto 0) <= \^q\(3 downto 0);
  done_dqs_dec238_out <= \^done_dqs_dec238_out\;
  early1_data_reg_0 <= \^early1_data_reg_0\;
  phy_if_reset_w <= \^phy_if_reset_w\;
  wrcal_done_reg_0 <= \^wrcal_done_reg_0\;
  wrcal_sanity_chk_done_reg_0 <= \^wrcal_sanity_chk_done_reg_0\;
  wrlvl_byte_redo <= \^wrlvl_byte_redo\;
\FSM_sequential_wl_state_r[4]_i_21\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"DD45"
    )
        port map (
      I0 => \^early1_data_reg_0\,
      I1 => \wrlvl_redo_corse_inc[2]_i_7\,
      I2 => early2_data_reg_n_0,
      I3 => \wrlvl_redo_corse_inc[2]_i_7_0\,
      O => early1_data_reg_1
    );
cal2_done_r_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFEFFF00002000"
    )
        port map (
      I0 => p_1_in,
      I1 => \cal2_state_r_reg_n_0_[3]\,
      I2 => \cal2_state_r_reg_n_0_[2]\,
      I3 => \cal2_state_r_reg_n_0_[1]\,
      I4 => \cal2_state_r_reg_n_0_[0]\,
      I5 => cal2_done_r,
      O => cal2_done_r_i_1_n_0
    );
cal2_done_r_i_2: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => wrcal_sanity_chk_r_reg_n_0,
      I1 => wrcal_sanity_chk,
      O => p_1_in
    );
cal2_done_r_reg: unisim.vcomponents.FDRE
     port map (
      C => wrcal_pat_resume_reg_0,
      CE => '1',
      D => cal2_done_r_i_1_n_0,
      Q => cal2_done_r,
      R => cal2_done_r_reg_0(0)
    );
cal2_if_reset_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFBABF00008A80"
    )
        port map (
      I0 => cal2_if_reset_i_2_n_0,
      I1 => cal2_if_reset_i_3_n_0,
      I2 => \cal2_state_r_reg_n_0_[0]\,
      I3 => cal2_if_reset_i_4_n_0,
      I4 => \cal2_state_r_reg_n_0_[3]\,
      I5 => \^phy_if_reset_w\,
      O => cal2_if_reset_i_1_n_0
    );
cal2_if_reset_i_2: unisim.vcomponents.LUT6
    generic map(
      INIT => X"004F0040F000F000"
    )
        port map (
      I0 => \^e\(0),
      I1 => rd_active_r1,
      I2 => \cal2_state_r_reg_n_0_[0]\,
      I3 => \cal2_state_r_reg_n_0_[2]\,
      I4 => wrcal_sanity_chk_r_reg_n_0,
      I5 => \cal2_state_r_reg_n_0_[1]\,
      O => cal2_if_reset_i_2_n_0
    );
cal2_if_reset_i_3: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00FF000040FF40FF"
    )
        port map (
      I0 => \^e\(0),
      I1 => wrlvl_byte_done,
      I2 => rd_active_r1,
      I3 => \cal2_state_r_reg_n_0_[1]\,
      I4 => idelay_ld_done_i_2_n_0,
      I5 => \cal2_state_r_reg_n_0_[2]\,
      O => cal2_if_reset_i_3_n_0
    );
cal2_if_reset_i_4: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FF80FFFFFF800000"
    )
        port map (
      I0 => prech_done,
      I1 => cal2_prech_req_r_i_2_n_0,
      I2 => wrcal_sanity_chk_r_reg_n_0,
      I3 => \cal2_state_r_reg_n_0_[2]\,
      I4 => \cal2_state_r_reg_n_0_[1]\,
      I5 => cal2_if_reset_i_5_n_0,
      O => cal2_if_reset_i_4_n_0
    );
cal2_if_reset_i_5: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8000FFFF80000000"
    )
        port map (
      I0 => tap_inc_wait_cnt_reg(2),
      I1 => tap_inc_wait_cnt_reg(0),
      I2 => tap_inc_wait_cnt_reg(1),
      I3 => tap_inc_wait_cnt_reg(3),
      I4 => \cal2_state_r_reg_n_0_[2]\,
      I5 => \cal2_state_r_reg[0]_0\,
      O => cal2_if_reset_i_5_n_0
    );
cal2_if_reset_reg: unisim.vcomponents.FDRE
     port map (
      C => wrcal_pat_resume_reg_0,
      CE => '1',
      D => cal2_if_reset_i_1_n_0,
      Q => \^phy_if_reset_w\,
      R => cal2_if_reset_reg_0
    );
cal2_prech_req_r_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000010110000"
    )
        port map (
      I0 => \cal2_state_r_reg_n_0_[3]\,
      I1 => \cal2_state_r_reg_n_0_[2]\,
      I2 => cal2_prech_req_r_i_2_n_0,
      I3 => wrcal_sanity_chk_r_reg_n_0,
      I4 => \cal2_state_r_reg_n_0_[1]\,
      I5 => \cal2_state_r_reg_n_0_[0]\,
      O => cal2_prech_req_r_i_1_n_0
    );
cal2_prech_req_r_i_2: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0080"
    )
        port map (
      I0 => \wrcal_dqs_cnt_r_reg_n_0_[1]\,
      I1 => \wrcal_dqs_cnt_r_reg_n_0_[0]\,
      I2 => \wrcal_dqs_cnt_r_reg_n_0_[2]\,
      I3 => wrcal_dqs_cnt_r(3),
      O => cal2_prech_req_r_i_2_n_0
    );
cal2_prech_req_r_reg: unisim.vcomponents.FDRE
     port map (
      C => wrcal_pat_resume_reg_0,
      CE => '1',
      D => cal2_prech_req_r_i_1_n_0,
      Q => cal2_prech_req_r,
      R => cal2_if_reset_reg_0
    );
\cal2_state_r[0]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000FF5D005D"
    )
        port map (
      I0 => \cal2_state_r_reg_n_0_[2]\,
      I1 => idelay_ld_done_reg_n_0,
      I2 => wrcal_sanity_chk_r_reg_n_0,
      I3 => \cal2_state_r_reg_n_0_[1]\,
      I4 => \cal2_state_r[0]_i_4_n_0\,
      I5 => \cal2_state_r_reg_n_0_[3]\,
      O => \cal2_state_r[0]_i_2_n_0\
    );
\cal2_state_r[0]_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000CCE2"
    )
        port map (
      I0 => \cal2_state_r[0]_i_5_n_0\,
      I1 => \cal2_state_r_reg_n_0_[2]\,
      I2 => tap_inc_wait_cnt_reg(0),
      I3 => \cal2_state_r_reg_n_0_[1]\,
      I4 => \cal2_state_r_reg_n_0_[3]\,
      O => \cal2_state_r[0]_i_3_n_0\
    );
\cal2_state_r[0]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000FFFF7FFF"
    )
        port map (
      I0 => prech_done,
      I1 => \wrcal_dqs_cnt_r_reg_n_0_[1]\,
      I2 => \wrcal_dqs_cnt_r_reg_n_0_[0]\,
      I3 => \wrcal_dqs_cnt_r_reg_n_0_[2]\,
      I4 => wrcal_dqs_cnt_r(3),
      I5 => \cal2_state_r_reg_n_0_[2]\,
      O => \cal2_state_r[0]_i_4_n_0\
    );
\cal2_state_r[0]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000054550000"
    )
        port map (
      I0 => wrcal_sanity_chk_r_reg_n_0,
      I1 => \gen_pat_match_div4.early2_data_match_r_reg_n_0\,
      I2 => \gen_pat_match_div4.early1_data_match_r_reg_n_0\,
      I3 => idelay_ld_done_reg_n_0,
      I4 => \gen_pat_match_div4.pat_data_match_valid_r_reg_n_0\,
      I5 => \gen_pat_match_div4.pat_data_match_r_reg_n_0\,
      O => \cal2_state_r[0]_i_5_n_0\
    );
\cal2_state_r[1]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0F0050D0"
    )
        port map (
      I0 => prech_done,
      I1 => cal2_prech_req_r_i_2_n_0,
      I2 => \cal2_state_r_reg_n_0_[1]\,
      I3 => wrcal_sanity_chk_r_reg_n_0,
      I4 => \cal2_state_r_reg_n_0_[2]\,
      O => \cal2_state_r[1]_i_2_n_0\
    );
\cal2_state_r[1]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000FFE200E2"
    )
        port map (
      I0 => \cal2_state_r[1]_i_4_n_0\,
      I1 => \gen_pat_match_div4.pat_data_match_r_reg_n_0\,
      I2 => \gen_pat_match_div4.pat_data_match_valid_r_reg_n_0\,
      I3 => \cal2_state_r_reg_n_0_[2]\,
      I4 => tap_inc_wait_cnt_reg(1),
      I5 => \cal2_state_r_reg_n_0_[1]\,
      O => \cal2_state_r[1]_i_3_n_0\
    );
\cal2_state_r[1]_i_4\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"00C8"
    )
        port map (
      I0 => \gen_pat_match_div4.early1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat_data_match_valid_r_reg_n_0\,
      I2 => \gen_pat_match_div4.early2_data_match_r_reg_n_0\,
      I3 => wrcal_sanity_chk_r_reg_n_0,
      O => \cal2_state_r[1]_i_4_n_0\
    );
\cal2_state_r[2]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"4F4AFFFF4F4A0000"
    )
        port map (
      I0 => \cal2_state_r_reg_n_0_[1]\,
      I1 => tap_inc_wait_cnt_reg(2),
      I2 => \cal2_state_r_reg_n_0_[2]\,
      I3 => \cal2_state_r[2]_i_2_n_0\,
      I4 => \cal2_state_r_reg_n_0_[0]\,
      I5 => \cal2_state_r[2]_i_3_n_0\,
      O => \cal2_state_r[2]_i_1_n_0\
    );
\cal2_state_r[2]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000000010"
    )
        port map (
      I0 => wrcal_sanity_chk_r_reg_n_0,
      I1 => \gen_pat_match_div4.early2_data_match_r_reg_n_0\,
      I2 => \gen_pat_match_div4.pat_data_match_valid_r_reg_n_0\,
      I3 => \gen_pat_match_div4.early1_data_match_r_reg_n_0\,
      I4 => idelay_ld_done_reg_n_0,
      I5 => \gen_pat_match_div4.pat_data_match_r_reg_n_0\,
      O => \cal2_state_r[2]_i_2_n_0\
    );
\cal2_state_r[2]_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0F00D0D0"
    )
        port map (
      I0 => prech_done,
      I1 => cal2_prech_req_r_i_2_n_0,
      I2 => \cal2_state_r_reg_n_0_[1]\,
      I3 => wrcal_sanity_chk_r_reg_n_0,
      I4 => \cal2_state_r_reg_n_0_[2]\,
      O => \cal2_state_r[2]_i_3_n_0\
    );
\cal2_state_r[3]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00E2FFFF00E20000"
    )
        port map (
      I0 => \cal2_state_r[3]_i_5_n_0\,
      I1 => \cal2_state_r_reg_n_0_[2]\,
      I2 => tap_inc_wait_cnt_reg(3),
      I3 => \cal2_state_r_reg_n_0_[1]\,
      I4 => \cal2_state_r_reg_n_0_[0]\,
      I5 => \cal2_state_r_reg_n_0_[3]\,
      O => \cal2_state_r[3]_i_2_n_0\
    );
\cal2_state_r[3]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"45404F4F45404A4A"
    )
        port map (
      I0 => \cal2_state_r_reg_n_0_[3]\,
      I1 => \cal2_state_r[3]_i_6_n_0\,
      I2 => \cal2_state_r_reg_n_0_[1]\,
      I3 => \cal2_state_r[3]_i_7_n_0\,
      I4 => \cal2_state_r_reg_n_0_[2]\,
      I5 => \cal2_state_r_reg[0]_0\,
      O => \cal2_state_r[3]_i_3_n_0\
    );
\cal2_state_r[3]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000FFE200E2"
    )
        port map (
      I0 => \cal2_state_r[3]_i_8_n_0\,
      I1 => \cal2_state_r_reg_n_0_[2]\,
      I2 => idelay_ld_done_i_2_n_0,
      I3 => \cal2_state_r_reg_n_0_[1]\,
      I4 => \cal2_state_r[3]_i_9_n_0\,
      I5 => \cal2_state_r_reg_n_0_[3]\,
      O => \cal2_state_r[3]_i_4_n_0\
    );
\cal2_state_r[3]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"7777777733333373"
    )
        port map (
      I0 => \gen_pat_match_div4.pat_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat_data_match_valid_r_reg_n_0\,
      I2 => idelay_ld_done_reg_n_0,
      I3 => \gen_pat_match_div4.early1_data_match_r_reg_n_0\,
      I4 => \gen_pat_match_div4.early2_data_match_r_reg_n_0\,
      I5 => wrcal_sanity_chk_r_reg_n_0,
      O => \cal2_state_r[3]_i_5_n_0\
    );
\cal2_state_r[3]_i_6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"3B3B3808"
    )
        port map (
      I0 => wrcal_sanity_chk,
      I1 => \cal2_state_r_reg_n_0_[2]\,
      I2 => wrcal_sanity_chk_r_reg_n_0,
      I3 => \wrcal_dqs_cnt_r[3]_i_4_n_0\,
      I4 => prech_done,
      O => \cal2_state_r[3]_i_6_n_0\
    );
\cal2_state_r[3]_i_7\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8000"
    )
        port map (
      I0 => tap_inc_wait_cnt_reg(2),
      I1 => tap_inc_wait_cnt_reg(0),
      I2 => tap_inc_wait_cnt_reg(1),
      I3 => tap_inc_wait_cnt_reg(3),
      O => \cal2_state_r[3]_i_7_n_0\
    );
\cal2_state_r[3]_i_8\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFF80000000"
    )
        port map (
      I0 => \not_empty_wait_cnt_reg_n_0_[2]\,
      I1 => \not_empty_wait_cnt_reg_n_0_[1]\,
      I2 => \not_empty_wait_cnt_reg_n_0_[0]\,
      I3 => \not_empty_wait_cnt_reg_n_0_[3]\,
      I4 => \not_empty_wait_cnt_reg_n_0_[4]\,
      I5 => \gen_pat_match_div4.pat_data_match_valid_r_reg_n_0\,
      O => \cal2_state_r[3]_i_8_n_0\
    );
\cal2_state_r[3]_i_9\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"8888B888"
    )
        port map (
      I0 => \cal2_state_r[3]_i_7_n_0\,
      I1 => \cal2_state_r_reg_n_0_[2]\,
      I2 => rd_active_r1,
      I3 => wrlvl_byte_done,
      I4 => \^e\(0),
      O => \cal2_state_r[3]_i_9_n_0\
    );
\cal2_state_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => wrcal_pat_resume_reg_0,
      CE => cal2_state_r,
      D => \cal2_state_r_reg[0]_i_1_n_0\,
      Q => \cal2_state_r_reg_n_0_[0]\,
      R => cal2_done_r_reg_0(0)
    );
\cal2_state_r_reg[0]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \cal2_state_r[0]_i_2_n_0\,
      I1 => \cal2_state_r[0]_i_3_n_0\,
      O => \cal2_state_r_reg[0]_i_1_n_0\,
      S => \cal2_state_r_reg_n_0_[0]\
    );
\cal2_state_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => wrcal_pat_resume_reg_0,
      CE => cal2_state_r,
      D => \cal2_state_r_reg[1]_i_1_n_0\,
      Q => \cal2_state_r_reg_n_0_[1]\,
      R => cal2_done_r_reg_0(0)
    );
\cal2_state_r_reg[1]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \cal2_state_r[1]_i_2_n_0\,
      I1 => \cal2_state_r[1]_i_3_n_0\,
      O => \cal2_state_r_reg[1]_i_1_n_0\,
      S => \cal2_state_r_reg_n_0_[0]\
    );
\cal2_state_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => wrcal_pat_resume_reg_0,
      CE => cal2_state_r,
      D => \cal2_state_r[2]_i_1_n_0\,
      Q => \cal2_state_r_reg_n_0_[2]\,
      R => cal2_done_r_reg_0(0)
    );
\cal2_state_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => wrcal_pat_resume_reg_0,
      CE => cal2_state_r,
      D => \cal2_state_r[3]_i_2_n_0\,
      Q => \cal2_state_r_reg_n_0_[3]\,
      R => cal2_done_r_reg_0(0)
    );
\cal2_state_r_reg[3]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \cal2_state_r[3]_i_3_n_0\,
      I1 => \cal2_state_r[3]_i_4_n_0\,
      O => cal2_state_r,
      S => \cal2_state_r_reg_n_0_[0]\
    );
\corse_cnt[0][2]_i_10\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => \^q\(0),
      I1 => \^q\(1),
      O => \po_stg2_wrcal_cnt_reg[0]_0\
    );
\corse_cnt[0][2]_i_9\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFBFFFFFFFFFF"
    )
        port map (
      I0 => \^q\(2),
      I1 => \^done_dqs_dec238_out\,
      I2 => \^q\(3),
      I3 => \corse_cnt[0][2]_i_3\(0),
      I4 => \corse_cnt[0][2]_i_3\(1),
      I5 => \corse_cnt[0][2]_i_3_0\,
      O => \po_stg2_wrcal_cnt_reg[2]_0\
    );
\corse_cnt[1][2]_i_3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => \^q\(1),
      I1 => \^q\(0),
      O => \po_stg2_wrcal_cnt_reg[1]_0\
    );
\corse_cnt[2][2]_i_3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => \^q\(0),
      I1 => \^q\(1),
      O => \po_stg2_wrcal_cnt_reg[0]_1\
    );
\corse_cnt[3][2]_i_3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"7"
    )
        port map (
      I0 => \^q\(0),
      I1 => \^q\(1),
      O => \po_stg2_wrcal_cnt_reg[0]_2\
    );
\corse_cnt[4][2]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFDFFFFFFFFFFFFF"
    )
        port map (
      I0 => \^done_dqs_dec238_out\,
      I1 => \^q\(3),
      I2 => \corse_cnt[0][2]_i_3\(0),
      I3 => \corse_cnt[0][2]_i_3\(1),
      I4 => \corse_cnt[0][2]_i_3_0\,
      I5 => \^q\(2),
      O => \po_stg2_wrcal_cnt_reg[3]_0\
    );
early1_data_i_1: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F20"
    )
        port map (
      I0 => \gen_pat_match_div4.early1_data_match_r_reg_n_0\,
      I1 => \cal2_state_r_reg_n_0_[1]\,
      I2 => early1_data_i_2_n_0,
      I3 => \^early1_data_reg_0\,
      O => early1_data_i_1_n_0
    );
early1_data_i_2: unisim.vcomponents.LUT5
    generic map(
      INIT => X"45400000"
    )
        port map (
      I0 => \cal2_state_r_reg_n_0_[3]\,
      I1 => early1_data_i_3_n_0,
      I2 => \cal2_state_r_reg_n_0_[1]\,
      I3 => wrlvl_byte_redo_i_3_n_0,
      I4 => \cal2_state_r_reg_n_0_[0]\,
      O => early1_data_i_2_n_0
    );
early1_data_i_3: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0040"
    )
        port map (
      I0 => \^e\(0),
      I1 => wrlvl_byte_done,
      I2 => rd_active_r1,
      I3 => \cal2_state_r_reg_n_0_[2]\,
      O => early1_data_i_3_n_0
    );
early1_data_reg: unisim.vcomponents.FDRE
     port map (
      C => wrcal_pat_resume_reg_0,
      CE => '1',
      D => early1_data_i_1_n_0,
      Q => \^early1_data_reg_0\,
      R => cal2_if_reset_reg_0
    );
early2_data_i_1: unisim.vcomponents.LUT5
    generic map(
      INIT => X"04FF0400"
    )
        port map (
      I0 => \gen_pat_match_div4.early1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.early2_data_match_r_reg_n_0\,
      I2 => \cal2_state_r_reg_n_0_[1]\,
      I3 => early1_data_i_2_n_0,
      I4 => early2_data_reg_n_0,
      O => early2_data_i_1_n_0
    );
early2_data_reg: unisim.vcomponents.FDRE
     port map (
      C => wrcal_pat_resume_reg_0,
      CE => '1',
      D => early2_data_i_1_n_0,
      Q => early2_data_reg_n_0,
      R => cal2_done_r_reg_0(0)
    );
\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => wrcal_pat_resume_reg_0,
      CE => '1',
      D => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg[0]_0\,
      Q => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg_n_0_[0]\,
      R => '0'
    );
\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => wrcal_pat_resume_reg_0,
      CE => '1',
      D => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg[0]_0\,
      Q => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg_n_0_[0]\,
      R => '0'
    );
\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => wrcal_pat_resume_reg_0,
      CE => '1',
      D => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg[0]_0\,
      Q => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg_n_0_[0]\,
      R => '0'
    );
\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => wrcal_pat_resume_reg_0,
      CE => '1',
      D => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg[0]_0\,
      Q => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg_n_0_[0]\,
      R => '0'
    );
\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => wrcal_pat_resume_reg_0,
      CE => '1',
      D => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg[0]_0\,
      Q => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg_n_0_[0]\,
      R => '0'
    );
\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => wrcal_pat_resume_reg_0,
      CE => '1',
      D => p_0_out,
      Q => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg_n_0_[0]\,
      R => '0'
    );
\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise2_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => wrcal_pat_resume_reg_0,
      CE => '1',
      D => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise2_r_reg[0]_0\,
      Q => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise2_r_reg_n_0_[0]\,
      R => '0'
    );
\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => wrcal_pat_resume_reg_0,
      CE => '1',
      D => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg[0]_0\,
      Q => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg_n_0_[0]\,
      R => '0'
    );
\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => wrcal_pat_resume_reg_0,
      CE => '1',
      D => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg[1]_0\,
      Q => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg_n_0_[1]\,
      R => '0'
    );
\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => wrcal_pat_resume_reg_0,
      CE => '1',
      D => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg[1]_0\,
      Q => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg_n_0_[1]\,
      R => '0'
    );
\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => wrcal_pat_resume_reg_0,
      CE => '1',
      D => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg[1]_0\,
      Q => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg_n_0_[1]\,
      R => '0'
    );
\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => wrcal_pat_resume_reg_0,
      CE => '1',
      D => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg[1]_0\,
      Q => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg_n_0_[1]\,
      R => '0'
    );
\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => wrcal_pat_resume_reg_0,
      CE => '1',
      D => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg[1]_0\,
      Q => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg_n_0_[1]\,
      R => '0'
    );
\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => wrcal_pat_resume_reg_0,
      CE => '1',
      D => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg[1]_0\,
      Q => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg_n_0_[1]\,
      R => '0'
    );
\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => wrcal_pat_resume_reg_0,
      CE => '1',
      D => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg[1]_0\,
      Q => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg_n_0_[1]\,
      R => '0'
    );
\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => wrcal_pat_resume_reg_0,
      CE => '1',
      D => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg[1]_0\,
      Q => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg_n_0_[1]\,
      R => '0'
    );
\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => wrcal_pat_resume_reg_0,
      CE => '1',
      D => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg[2]_0\,
      Q => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg_n_0_[2]\,
      R => '0'
    );
\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => wrcal_pat_resume_reg_0,
      CE => '1',
      D => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg[2]_0\,
      Q => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg_n_0_[2]\,
      R => '0'
    );
\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => wrcal_pat_resume_reg_0,
      CE => '1',
      D => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg[2]_0\,
      Q => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg_n_0_[2]\,
      R => '0'
    );
\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => wrcal_pat_resume_reg_0,
      CE => '1',
      D => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg[2]_0\,
      Q => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg_n_0_[2]\,
      R => '0'
    );
\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => wrcal_pat_resume_reg_0,
      CE => '1',
      D => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg[2]_0\,
      Q => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg_n_0_[2]\,
      R => '0'
    );
\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => wrcal_pat_resume_reg_0,
      CE => '1',
      D => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg[2]_0\,
      Q => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg_n_0_[2]\,
      R => '0'
    );
\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => wrcal_pat_resume_reg_0,
      CE => '1',
      D => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg[2]_0\,
      Q => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg_n_0_[2]\,
      R => '0'
    );
\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => wrcal_pat_resume_reg_0,
      CE => '1',
      D => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg[2]_0\,
      Q => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg_n_0_[2]\,
      R => '0'
    );
\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => wrcal_pat_resume_reg_0,
      CE => '1',
      D => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg[3]_0\,
      Q => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg_n_0_[3]\,
      R => '0'
    );
\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => wrcal_pat_resume_reg_0,
      CE => '1',
      D => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg[3]_0\,
      Q => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg_n_0_[3]\,
      R => '0'
    );
\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => wrcal_pat_resume_reg_0,
      CE => '1',
      D => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg[3]_0\,
      Q => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg_n_0_[3]\,
      R => '0'
    );
\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => wrcal_pat_resume_reg_0,
      CE => '1',
      D => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg[3]_0\,
      Q => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg_n_0_[3]\,
      R => '0'
    );
\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => wrcal_pat_resume_reg_0,
      CE => '1',
      D => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg[3]_0\,
      Q => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg_n_0_[3]\,
      R => '0'
    );
\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => wrcal_pat_resume_reg_0,
      CE => '1',
      D => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg[3]_0\,
      Q => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg_n_0_[3]\,
      R => '0'
    );
\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => wrcal_pat_resume_reg_0,
      CE => '1',
      D => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg[3]_0\,
      Q => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg_n_0_[3]\,
      R => '0'
    );
\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise3_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => wrcal_pat_resume_reg_0,
      CE => '1',
      D => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise3_r_reg[3]_0\,
      Q => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise3_r_reg_n_0_[3]\,
      R => '0'
    );
\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => wrcal_pat_resume_reg_0,
      CE => '1',
      D => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg[4]_0\,
      Q => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg_n_0_[4]\,
      R => '0'
    );
\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => wrcal_pat_resume_reg_0,
      CE => '1',
      D => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg[4]_0\,
      Q => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg_n_0_[4]\,
      R => '0'
    );
\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => wrcal_pat_resume_reg_0,
      CE => '1',
      D => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg[4]_0\,
      Q => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg_n_0_[4]\,
      R => '0'
    );
\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => wrcal_pat_resume_reg_0,
      CE => '1',
      D => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg[4]_0\,
      Q => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg_n_0_[4]\,
      R => '0'
    );
\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => wrcal_pat_resume_reg_0,
      CE => '1',
      D => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg[4]_0\,
      Q => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg_n_0_[4]\,
      R => '0'
    );
\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => wrcal_pat_resume_reg_0,
      CE => '1',
      D => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg[4]_0\,
      Q => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg_n_0_[4]\,
      R => '0'
    );
\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise2_r_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => wrcal_pat_resume_reg_0,
      CE => '1',
      D => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise2_r_reg[4]_0\,
      Q => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise2_r_reg_n_0_[4]\,
      R => '0'
    );
\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => wrcal_pat_resume_reg_0,
      CE => '1',
      D => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg[4]_0\,
      Q => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg_n_0_[4]\,
      R => '0'
    );
\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => wrcal_pat_resume_reg_0,
      CE => '1',
      D => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg[5]_0\,
      Q => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg_n_0_[5]\,
      R => '0'
    );
\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => wrcal_pat_resume_reg_0,
      CE => '1',
      D => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg[5]_0\,
      Q => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg_n_0_[5]\,
      R => '0'
    );
\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => wrcal_pat_resume_reg_0,
      CE => '1',
      D => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg[5]_0\,
      Q => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg_n_0_[5]\,
      R => '0'
    );
\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => wrcal_pat_resume_reg_0,
      CE => '1',
      D => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg[5]_0\,
      Q => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg_n_0_[5]\,
      R => '0'
    );
\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => wrcal_pat_resume_reg_0,
      CE => '1',
      D => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg[5]_0\,
      Q => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg_n_0_[5]\,
      R => '0'
    );
\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => wrcal_pat_resume_reg_0,
      CE => '1',
      D => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg[5]_0\,
      Q => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg_n_0_[5]\,
      R => '0'
    );
\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => wrcal_pat_resume_reg_0,
      CE => '1',
      D => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg[5]_0\,
      Q => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg_n_0_[5]\,
      R => '0'
    );
\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => wrcal_pat_resume_reg_0,
      CE => '1',
      D => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg[5]_0\,
      Q => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg_n_0_[5]\,
      R => '0'
    );
\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => wrcal_pat_resume_reg_0,
      CE => '1',
      D => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg[6]_0\,
      Q => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg_n_0_[6]\,
      R => '0'
    );
\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => wrcal_pat_resume_reg_0,
      CE => '1',
      D => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg[6]_0\,
      Q => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg_n_0_[6]\,
      R => '0'
    );
\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => wrcal_pat_resume_reg_0,
      CE => '1',
      D => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg[6]_0\,
      Q => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg_n_0_[6]\,
      R => '0'
    );
\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => wrcal_pat_resume_reg_0,
      CE => '1',
      D => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg[6]_0\,
      Q => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg_n_0_[6]\,
      R => '0'
    );
\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => wrcal_pat_resume_reg_0,
      CE => '1',
      D => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg[6]_0\,
      Q => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg_n_0_[6]\,
      R => '0'
    );
\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => wrcal_pat_resume_reg_0,
      CE => '1',
      D => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg[6]_0\,
      Q => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg_n_0_[6]\,
      R => '0'
    );
\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => wrcal_pat_resume_reg_0,
      CE => '1',
      D => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg[6]_0\,
      Q => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg_n_0_[6]\,
      R => '0'
    );
\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => wrcal_pat_resume_reg_0,
      CE => '1',
      D => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg[6]_0\,
      Q => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg_n_0_[6]\,
      R => '0'
    );
\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => wrcal_pat_resume_reg_0,
      CE => '1',
      D => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg[7]_0\,
      Q => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg_n_0_[7]\,
      R => '0'
    );
\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => wrcal_pat_resume_reg_0,
      CE => '1',
      D => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg[7]_0\,
      Q => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg_n_0_[7]\,
      R => '0'
    );
\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => wrcal_pat_resume_reg_0,
      CE => '1',
      D => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg[7]_0\,
      Q => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg_n_0_[7]\,
      R => '0'
    );
\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => wrcal_pat_resume_reg_0,
      CE => '1',
      D => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7]_0\,
      Q => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg_n_0_[7]\,
      R => '0'
    );
\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => wrcal_pat_resume_reg_0,
      CE => '1',
      D => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg[7]_0\,
      Q => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg_n_0_[7]\,
      R => '0'
    );
\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => wrcal_pat_resume_reg_0,
      CE => '1',
      D => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg[7]_0\,
      Q => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg_n_0_[7]\,
      R => '0'
    );
\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => wrcal_pat_resume_reg_0,
      CE => '1',
      D => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg[7]_0\,
      Q => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg_n_0_[7]\,
      R => '0'
    );
\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise3_r_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => wrcal_pat_resume_reg_0,
      CE => '1',
      D => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise3_r_reg[7]_0\,
      Q => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise3_r_reg_n_0_[7]\,
      R => '0'
    );
\gen_pat_match_div4.early1_data_match_r_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00008000"
    )
        port map (
      I0 => early1_match_rise0_and_r,
      I1 => early1_match_fall3_and_r,
      I2 => early1_match_fall0_and_r,
      I3 => early1_match_fall2_and_r,
      I4 => \gen_pat_match_div4.early1_data_match_r_i_2_n_0\,
      O => early1_data_match_r0
    );
\gen_pat_match_div4.early1_data_match_r_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7FFF"
    )
        port map (
      I0 => early1_match_rise2_and_r,
      I1 => early1_match_rise3_and_r,
      I2 => early1_match_rise1_and_r,
      I3 => early1_match_fall1_and_r,
      O => \gen_pat_match_div4.early1_data_match_r_i_2_n_0\
    );
\gen_pat_match_div4.early1_data_match_r_reg\: unisim.vcomponents.FDRE
     port map (
      C => wrcal_pat_resume_reg_0,
      CE => '1',
      D => early1_data_match_r0,
      Q => \gen_pat_match_div4.early1_data_match_r_reg_n_0\,
      R => '0'
    );
\gen_pat_match_div4.early1_match_fall0_and_r_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00008000"
    )
        port map (
      I0 => early1_match_fall0_r(2),
      I1 => early1_match_fall0_r(0),
      I2 => early1_match_fall0_r(6),
      I3 => early1_match_fall0_r(4),
      I4 => \gen_pat_match_div4.early1_match_fall0_and_r_i_2_n_0\,
      O => \gen_pat_match_div4.early1_match_fall0_and_r_i_1_n_0\
    );
\gen_pat_match_div4.early1_match_fall0_and_r_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7FFF"
    )
        port map (
      I0 => early1_match_fall0_r(1),
      I1 => early1_match_fall0_r(3),
      I2 => early1_match_fall0_r(5),
      I3 => early1_match_fall0_r(7),
      O => \gen_pat_match_div4.early1_match_fall0_and_r_i_2_n_0\
    );
\gen_pat_match_div4.early1_match_fall0_and_r_reg\: unisim.vcomponents.FDRE
     port map (
      C => wrcal_pat_resume_reg_0,
      CE => '1',
      D => \gen_pat_match_div4.early1_match_fall0_and_r_i_1_n_0\,
      Q => early1_match_fall0_and_r,
      R => '0'
    );
\gen_pat_match_div4.early1_match_fall1_and_r_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"80000000"
    )
        port map (
      I0 => \gen_pat_match_div4.early1_match_fall1_and_r_i_2_n_0\,
      I1 => \gen_pat_match_div4.gen_pat_match[6].early1_match_fall1_r_reg\,
      I2 => \gen_pat_match_div4.gen_pat_match[3].early1_match_fall1_r_reg\,
      I3 => \gen_pat_match_div4.gen_pat_match[7].early1_match_fall1_r_reg\,
      I4 => \gen_pat_match_div4.gen_pat_match[2].early1_match_fall1_r_reg\,
      O => \gen_pat_match_div4.early1_match_fall1_and_r_i_1_n_0\
    );
\gen_pat_match_div4.early1_match_fall1_and_r_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8000"
    )
        port map (
      I0 => early2_match_fall1_r(0),
      I1 => early2_match_fall1_r(5),
      I2 => early2_match_fall1_r(1),
      I3 => early2_match_fall1_r(4),
      O => \gen_pat_match_div4.early1_match_fall1_and_r_i_2_n_0\
    );
\gen_pat_match_div4.early1_match_fall1_and_r_reg\: unisim.vcomponents.FDRE
     port map (
      C => wrcal_pat_resume_reg_0,
      CE => '1',
      D => \gen_pat_match_div4.early1_match_fall1_and_r_i_1_n_0\,
      Q => early1_match_fall1_and_r,
      R => '0'
    );
\gen_pat_match_div4.early1_match_fall2_and_r_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"80000000"
    )
        port map (
      I0 => \gen_pat_match_div4.early1_match_fall2_and_r_i_2_n_0\,
      I1 => \gen_pat_match_div4.gen_pat_match[6].early1_match_fall2_r_reg\,
      I2 => \gen_pat_match_div4.gen_pat_match[2].early1_match_fall2_r_reg\,
      I3 => early2_match_fall2_r(7),
      I4 => early2_match_fall2_r(3),
      O => \gen_pat_match_div4.early1_match_fall2_and_r_i_1_n_0\
    );
\gen_pat_match_div4.early1_match_fall2_and_r_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8000"
    )
        port map (
      I0 => \gen_pat_match_div4.gen_pat_match[0].pat_match_fall2_r_reg\,
      I1 => \gen_pat_match_div4.gen_pat_match[5].pat_match_fall2_r_reg\,
      I2 => \gen_pat_match_div4.gen_pat_match[1].pat_match_fall2_r_reg\,
      I3 => \gen_pat_match_div4.gen_pat_match[4].pat_match_fall2_r_reg\,
      O => \gen_pat_match_div4.early1_match_fall2_and_r_i_2_n_0\
    );
\gen_pat_match_div4.early1_match_fall2_and_r_reg\: unisim.vcomponents.FDRE
     port map (
      C => wrcal_pat_resume_reg_0,
      CE => '1',
      D => \gen_pat_match_div4.early1_match_fall2_and_r_i_1_n_0\,
      Q => early1_match_fall2_and_r,
      R => '0'
    );
\gen_pat_match_div4.early1_match_fall3_and_r_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"80000000"
    )
        port map (
      I0 => \gen_pat_match_div4.early1_match_fall3_and_r_i_2_n_0\,
      I1 => \gen_pat_match_div4.gen_pat_match[4].early1_match_fall3_r_reg\,
      I2 => \gen_pat_match_div4.gen_pat_match[2].early1_match_fall3_r_reg\,
      I3 => \gen_pat_match_div4.gen_pat_match[6].early1_match_fall3_r_reg\,
      I4 => \gen_pat_match_div4.gen_pat_match[0].early1_match_fall3_r_reg\,
      O => \gen_pat_match_div4.early1_match_fall3_and_r_i_1_n_0\
    );
\gen_pat_match_div4.early1_match_fall3_and_r_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8000"
    )
        port map (
      I0 => early2_match_fall3_r(1),
      I1 => early2_match_fall3_r(5),
      I2 => early2_match_fall3_r(3),
      I3 => early2_match_fall3_r(7),
      O => \gen_pat_match_div4.early1_match_fall3_and_r_i_2_n_0\
    );
\gen_pat_match_div4.early1_match_fall3_and_r_reg\: unisim.vcomponents.FDRE
     port map (
      C => wrcal_pat_resume_reg_0,
      CE => '1',
      D => \gen_pat_match_div4.early1_match_fall3_and_r_i_1_n_0\,
      Q => early1_match_fall3_and_r,
      R => '0'
    );
\gen_pat_match_div4.early1_match_rise0_and_r_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00008000"
    )
        port map (
      I0 => early1_match_rise0_r(2),
      I1 => early1_match_rise0_r(0),
      I2 => early1_match_rise0_r(6),
      I3 => early1_match_rise0_r(4),
      I4 => \gen_pat_match_div4.early1_match_rise0_and_r_i_2_n_0\,
      O => \gen_pat_match_div4.early1_match_rise0_and_r_i_1_n_0\
    );
\gen_pat_match_div4.early1_match_rise0_and_r_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7FFF"
    )
        port map (
      I0 => early1_match_rise0_r(1),
      I1 => early1_match_rise0_r(3),
      I2 => early1_match_rise0_r(5),
      I3 => early1_match_rise0_r(7),
      O => \gen_pat_match_div4.early1_match_rise0_and_r_i_2_n_0\
    );
\gen_pat_match_div4.early1_match_rise0_and_r_reg\: unisim.vcomponents.FDRE
     port map (
      C => wrcal_pat_resume_reg_0,
      CE => '1',
      D => \gen_pat_match_div4.early1_match_rise0_and_r_i_1_n_0\,
      Q => early1_match_rise0_and_r,
      R => '0'
    );
\gen_pat_match_div4.early1_match_rise1_and_r_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"80000000"
    )
        port map (
      I0 => \gen_pat_match_div4.early1_match_rise1_and_r_i_2_n_0\,
      I1 => \gen_pat_match_div4.gen_pat_match[6].early1_match_rise1_r_reg\,
      I2 => \gen_pat_match_div4.gen_pat_match[3].early1_match_rise1_r_reg\,
      I3 => \gen_pat_match_div4.gen_pat_match[7].early1_match_rise1_r_reg\,
      I4 => \gen_pat_match_div4.gen_pat_match[2].early1_match_rise1_r_reg\,
      O => \gen_pat_match_div4.early1_match_rise1_and_r_i_1_n_0\
    );
\gen_pat_match_div4.early1_match_rise1_and_r_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8000"
    )
        port map (
      I0 => early2_match_rise1_r(0),
      I1 => early2_match_rise1_r(5),
      I2 => early2_match_rise1_r(1),
      I3 => early2_match_rise1_r(4),
      O => \gen_pat_match_div4.early1_match_rise1_and_r_i_2_n_0\
    );
\gen_pat_match_div4.early1_match_rise1_and_r_reg\: unisim.vcomponents.FDRE
     port map (
      C => wrcal_pat_resume_reg_0,
      CE => '1',
      D => \gen_pat_match_div4.early1_match_rise1_and_r_i_1_n_0\,
      Q => early1_match_rise1_and_r,
      R => '0'
    );
\gen_pat_match_div4.early1_match_rise2_and_r_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"80000000"
    )
        port map (
      I0 => early2_match_rise2_r(7),
      I1 => early2_match_rise2_r(6),
      I2 => early2_match_rise2_r(3),
      I3 => early2_match_rise2_r(2),
      I4 => \gen_pat_match_div4.early1_match_rise2_and_r_i_2_n_0\,
      O => \gen_pat_match_div4.early1_match_rise2_and_r_i_1_n_0\
    );
\gen_pat_match_div4.early1_match_rise2_and_r_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8000"
    )
        port map (
      I0 => early2_match_rise2_r(0),
      I1 => early2_match_rise2_r(4),
      I2 => \gen_pat_match_div4.gen_pat_match[1].pat_match_rise2_r_reg\,
      I3 => \gen_pat_match_div4.gen_pat_match[5].pat_match_rise2_r_reg\,
      O => \gen_pat_match_div4.early1_match_rise2_and_r_i_2_n_0\
    );
\gen_pat_match_div4.early1_match_rise2_and_r_reg\: unisim.vcomponents.FDRE
     port map (
      C => wrcal_pat_resume_reg_0,
      CE => '1',
      D => \gen_pat_match_div4.early1_match_rise2_and_r_i_1_n_0\,
      Q => early1_match_rise2_and_r,
      R => '0'
    );
\gen_pat_match_div4.early1_match_rise3_and_r_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"80000000"
    )
        port map (
      I0 => \gen_pat_match_div4.early1_match_rise3_and_r_i_2_n_0\,
      I1 => early2_match_rise3_r(5),
      I2 => early2_match_rise3_r(1),
      I3 => \gen_pat_match_div4.gen_pat_match[4].pat_match_rise3_r_reg\,
      I4 => \gen_pat_match_div4.gen_pat_match[0].pat_match_rise3_r_reg\,
      O => \gen_pat_match_div4.early1_match_rise3_and_r_i_1_n_0\
    );
\gen_pat_match_div4.early1_match_rise3_and_r_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8000"
    )
        port map (
      I0 => \gen_pat_match_div4.gen_pat_match[2].pat_match_rise3_r_reg\,
      I1 => early2_match_rise3_r(7),
      I2 => early2_match_rise3_r(3),
      I3 => \gen_pat_match_div4.gen_pat_match[6].pat_match_rise3_r_reg\,
      O => \gen_pat_match_div4.early1_match_rise3_and_r_i_2_n_0\
    );
\gen_pat_match_div4.early1_match_rise3_and_r_reg\: unisim.vcomponents.FDRE
     port map (
      C => wrcal_pat_resume_reg_0,
      CE => '1',
      D => \gen_pat_match_div4.early1_match_rise3_and_r_i_1_n_0\,
      Q => early1_match_rise3_and_r,
      R => '0'
    );
\gen_pat_match_div4.early2_data_match_r_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00008000"
    )
        port map (
      I0 => early2_match_rise3_and_r,
      I1 => early2_match_fall2_and_r,
      I2 => early2_match_fall1_and_r,
      I3 => early2_match_rise0_and_r,
      I4 => \gen_pat_match_div4.early2_data_match_r_i_2_n_0\,
      O => early2_data_match_r0
    );
\gen_pat_match_div4.early2_data_match_r_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7FFF"
    )
        port map (
      I0 => early2_match_fall0_and_r,
      I1 => early2_match_rise2_and_r,
      I2 => early2_match_rise1_and_r,
      I3 => early2_match_fall3_and_r,
      O => \gen_pat_match_div4.early2_data_match_r_i_2_n_0\
    );
\gen_pat_match_div4.early2_data_match_r_reg\: unisim.vcomponents.FDRE
     port map (
      C => wrcal_pat_resume_reg_0,
      CE => '1',
      D => early2_data_match_r0,
      Q => \gen_pat_match_div4.early2_data_match_r_reg_n_0\,
      R => '0'
    );
\gen_pat_match_div4.early2_match_fall0_and_r_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"80000000"
    )
        port map (
      I0 => \gen_pat_match_div4.early2_match_fall0_and_r_i_2_n_0\,
      I1 => early2_match_fall0_r(3),
      I2 => early2_match_fall0_r(1),
      I3 => early2_match_fall0_r(7),
      I4 => early2_match_fall0_r(5),
      O => \gen_pat_match_div4.early2_match_fall0_and_r_i_1_n_0\
    );
\gen_pat_match_div4.early2_match_fall0_and_r_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8000"
    )
        port map (
      I0 => early2_match_fall0_r(4),
      I1 => early2_match_fall0_r(6),
      I2 => early2_match_fall0_r(0),
      I3 => early2_match_fall0_r(2),
      O => \gen_pat_match_div4.early2_match_fall0_and_r_i_2_n_0\
    );
\gen_pat_match_div4.early2_match_fall0_and_r_reg\: unisim.vcomponents.FDRE
     port map (
      C => wrcal_pat_resume_reg_0,
      CE => '1',
      D => \gen_pat_match_div4.early2_match_fall0_and_r_i_1_n_0\,
      Q => early2_match_fall0_and_r,
      R => '0'
    );
\gen_pat_match_div4.early2_match_fall1_and_r_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"80000000"
    )
        port map (
      I0 => early2_match_fall1_r(4),
      I1 => early2_match_fall1_r(1),
      I2 => early2_match_fall1_r(5),
      I3 => early2_match_fall1_r(0),
      I4 => \gen_pat_match_div4.early2_match_fall1_and_r_i_2_n_0\,
      O => \gen_pat_match_div4.early2_match_fall1_and_r_i_1_n_0\
    );
\gen_pat_match_div4.early2_match_fall1_and_r_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8000"
    )
        port map (
      I0 => early2_match_fall1_r(2),
      I1 => early2_match_fall1_r(7),
      I2 => early2_match_fall1_r(3),
      I3 => early2_match_fall1_r(6),
      O => \gen_pat_match_div4.early2_match_fall1_and_r_i_2_n_0\
    );
\gen_pat_match_div4.early2_match_fall1_and_r_reg\: unisim.vcomponents.FDRE
     port map (
      C => wrcal_pat_resume_reg_0,
      CE => '1',
      D => \gen_pat_match_div4.early2_match_fall1_and_r_i_1_n_0\,
      Q => early2_match_fall1_and_r,
      R => '0'
    );
\gen_pat_match_div4.early2_match_fall2_and_r_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00008000"
    )
        port map (
      I0 => early2_match_fall2_r(6),
      I1 => early2_match_fall2_r(1),
      I2 => early2_match_fall2_r(7),
      I3 => early2_match_fall2_r(0),
      I4 => \gen_pat_match_div4.early2_match_fall2_and_r_i_2_n_0\,
      O => \gen_pat_match_div4.early2_match_fall2_and_r_i_1_n_0\
    );
\gen_pat_match_div4.early2_match_fall2_and_r_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7FFF"
    )
        port map (
      I0 => early2_match_fall2_r(2),
      I1 => early2_match_fall2_r(5),
      I2 => early2_match_fall2_r(3),
      I3 => early2_match_fall2_r(4),
      O => \gen_pat_match_div4.early2_match_fall2_and_r_i_2_n_0\
    );
\gen_pat_match_div4.early2_match_fall2_and_r_reg\: unisim.vcomponents.FDRE
     port map (
      C => wrcal_pat_resume_reg_0,
      CE => '1',
      D => \gen_pat_match_div4.early2_match_fall2_and_r_i_1_n_0\,
      Q => early2_match_fall2_and_r,
      R => '0'
    );
\gen_pat_match_div4.early2_match_fall3_and_r_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"80000000"
    )
        port map (
      I0 => early2_match_fall3_r(7),
      I1 => early2_match_fall3_r(3),
      I2 => early2_match_fall3_r(5),
      I3 => early2_match_fall3_r(1),
      I4 => \gen_pat_match_div4.early2_match_fall3_and_r_i_2_n_0\,
      O => \gen_pat_match_div4.early2_match_fall3_and_r_i_1_n_0\
    );
\gen_pat_match_div4.early2_match_fall3_and_r_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8000"
    )
        port map (
      I0 => early2_match_fall3_r(0),
      I1 => early2_match_fall3_r(6),
      I2 => early2_match_fall3_r(4),
      I3 => early2_match_fall3_r(2),
      O => \gen_pat_match_div4.early2_match_fall3_and_r_i_2_n_0\
    );
\gen_pat_match_div4.early2_match_fall3_and_r_reg\: unisim.vcomponents.FDRE
     port map (
      C => wrcal_pat_resume_reg_0,
      CE => '1',
      D => \gen_pat_match_div4.early2_match_fall3_and_r_i_1_n_0\,
      Q => early2_match_fall3_and_r,
      R => '0'
    );
\gen_pat_match_div4.early2_match_rise0_and_r_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"80000000"
    )
        port map (
      I0 => \gen_pat_match_div4.early2_match_rise0_and_r_i_2_n_0\,
      I1 => early2_match_rise0_r(3),
      I2 => early2_match_rise0_r(1),
      I3 => early2_match_rise0_r(7),
      I4 => early2_match_rise0_r(5),
      O => \gen_pat_match_div4.early2_match_rise0_and_r_i_1_n_0\
    );
\gen_pat_match_div4.early2_match_rise0_and_r_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8000"
    )
        port map (
      I0 => early2_match_rise0_r(4),
      I1 => early2_match_rise0_r(6),
      I2 => early2_match_rise0_r(0),
      I3 => early2_match_rise0_r(2),
      O => \gen_pat_match_div4.early2_match_rise0_and_r_i_2_n_0\
    );
\gen_pat_match_div4.early2_match_rise0_and_r_reg\: unisim.vcomponents.FDRE
     port map (
      C => wrcal_pat_resume_reg_0,
      CE => '1',
      D => \gen_pat_match_div4.early2_match_rise0_and_r_i_1_n_0\,
      Q => early2_match_rise0_and_r,
      R => '0'
    );
\gen_pat_match_div4.early2_match_rise1_and_r_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"80000000"
    )
        port map (
      I0 => early2_match_rise1_r(4),
      I1 => early2_match_rise1_r(1),
      I2 => early2_match_rise1_r(5),
      I3 => early2_match_rise1_r(0),
      I4 => \gen_pat_match_div4.early2_match_rise1_and_r_i_2_n_0\,
      O => \gen_pat_match_div4.early2_match_rise1_and_r_i_1_n_0\
    );
\gen_pat_match_div4.early2_match_rise1_and_r_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8000"
    )
        port map (
      I0 => early2_match_rise1_r(2),
      I1 => early2_match_rise1_r(7),
      I2 => early2_match_rise1_r(3),
      I3 => early2_match_rise1_r(6),
      O => \gen_pat_match_div4.early2_match_rise1_and_r_i_2_n_0\
    );
\gen_pat_match_div4.early2_match_rise1_and_r_reg\: unisim.vcomponents.FDRE
     port map (
      C => wrcal_pat_resume_reg_0,
      CE => '1',
      D => \gen_pat_match_div4.early2_match_rise1_and_r_i_1_n_0\,
      Q => early2_match_rise1_and_r,
      R => '0'
    );
\gen_pat_match_div4.early2_match_rise2_and_r_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"80000000"
    )
        port map (
      I0 => \gen_pat_match_div4.early2_match_rise2_and_r_i_2_n_0\,
      I1 => early2_match_rise2_r(4),
      I2 => early2_match_rise2_r(0),
      I3 => early2_match_rise2_r(5),
      I4 => early2_match_rise2_r(1),
      O => \gen_pat_match_div4.early2_match_rise2_and_r_i_1_n_0\
    );
\gen_pat_match_div4.early2_match_rise2_and_r_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8000"
    )
        port map (
      I0 => early2_match_rise2_r(2),
      I1 => early2_match_rise2_r(3),
      I2 => early2_match_rise2_r(6),
      I3 => early2_match_rise2_r(7),
      O => \gen_pat_match_div4.early2_match_rise2_and_r_i_2_n_0\
    );
\gen_pat_match_div4.early2_match_rise2_and_r_reg\: unisim.vcomponents.FDRE
     port map (
      C => wrcal_pat_resume_reg_0,
      CE => '1',
      D => \gen_pat_match_div4.early2_match_rise2_and_r_i_1_n_0\,
      Q => early2_match_rise2_and_r,
      R => '0'
    );
\gen_pat_match_div4.early2_match_rise3_and_r_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00008000"
    )
        port map (
      I0 => early2_match_rise3_r(6),
      I1 => early2_match_rise3_r(5),
      I2 => early2_match_rise3_r(7),
      I3 => early2_match_rise3_r(4),
      I4 => \gen_pat_match_div4.early2_match_rise3_and_r_i_2_n_0\,
      O => \gen_pat_match_div4.early2_match_rise3_and_r_i_1_n_0\
    );
\gen_pat_match_div4.early2_match_rise3_and_r_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7FFF"
    )
        port map (
      I0 => early2_match_rise3_r(0),
      I1 => early2_match_rise3_r(3),
      I2 => early2_match_rise3_r(1),
      I3 => early2_match_rise3_r(2),
      O => \gen_pat_match_div4.early2_match_rise3_and_r_i_2_n_0\
    );
\gen_pat_match_div4.early2_match_rise3_and_r_reg\: unisim.vcomponents.FDRE
     port map (
      C => wrcal_pat_resume_reg_0,
      CE => '1',
      D => \gen_pat_match_div4.early2_match_rise3_and_r_i_1_n_0\,
      Q => early2_match_rise3_and_r,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[0].early1_match_fall0_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => wrcal_pat_resume_reg_0,
      CE => '1',
      D => \gen_sr_div4.gen_sr[0].sr_fall0_r_reg[0]_263\,
      Q => early1_match_fall0_r(0),
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[0].early1_match_fall1_r[0]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr[0].sr_fall1_r_reg[0]_303\,
      O => \gen_pat_match_div4.gen_pat_match[0].early1_match_fall1_r[0]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[0].early1_match_fall1_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => wrcal_pat_resume_reg_0,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[0].early1_match_fall1_r[0]_i_1_n_0\,
      Q => early2_match_fall1_r(0),
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[0].early1_match_fall3_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => wrcal_pat_resume_reg_0,
      CE => '1',
      D => \gen_sr_div4.gen_sr[0].sr_fall3_r_reg[0]_255\,
      Q => \gen_pat_match_div4.gen_pat_match[0].early1_match_fall3_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[0].early1_match_rise0_r[0]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr[0].sr_rise0_r_reg[0]_295\,
      O => \gen_pat_match_div4.gen_pat_match[0].early1_match_rise0_r[0]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[0].early1_match_rise0_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => wrcal_pat_resume_reg_0,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[0].early1_match_rise0_r[0]_i_1_n_0\,
      Q => early1_match_rise0_r(0),
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[0].early1_match_rise1_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => wrcal_pat_resume_reg_0,
      CE => '1',
      D => \gen_sr_div4.gen_sr[0].sr_rise1_r_reg[0]_247\,
      Q => early2_match_rise1_r(0),
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[0].early2_match_fall2_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => wrcal_pat_resume_reg_0,
      CE => '1',
      D => \gen_sr_div4.gen_sr[0].sr_fall2_r_reg[0]_279\,
      Q => early2_match_fall2_r(0),
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[0].early2_match_rise3_r[0]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr[0].sr_rise3_r_reg[0]_287\,
      O => \gen_pat_match_div4.gen_pat_match[0].early2_match_rise3_r[0]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[0].early2_match_rise3_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => wrcal_pat_resume_reg_0,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[0].early2_match_rise3_r[0]_i_1_n_0\,
      Q => early2_match_rise3_r(0),
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[0].pat_match_fall0_r[0]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr[0].sr_fall0_r_reg[0]_263\,
      O => \gen_pat_match_div4.gen_pat_match[0].pat_match_fall0_r[0]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[0].pat_match_fall0_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => wrcal_pat_resume_reg_0,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[0].pat_match_fall0_r[0]_i_1_n_0\,
      Q => early2_match_fall0_r(0),
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[0].pat_match_fall1_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => wrcal_pat_resume_reg_0,
      CE => '1',
      D => \gen_sr_div4.gen_sr[0].sr_fall1_r_reg[0]_303\,
      Q => \gen_pat_match_div4.gen_pat_match[0].pat_match_fall1_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[0].pat_match_fall2_r[0]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr[0].sr_fall2_r_reg[0]_279\,
      O => \gen_pat_match_div4.gen_pat_match[0].pat_match_fall2_r[0]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[0].pat_match_fall2_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => wrcal_pat_resume_reg_0,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[0].pat_match_fall2_r[0]_i_1_n_0\,
      Q => \gen_pat_match_div4.gen_pat_match[0].pat_match_fall2_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[0].pat_match_fall3_r[0]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr[0].sr_fall3_r_reg[0]_255\,
      O => \gen_pat_match_div4.gen_pat_match[0].pat_match_fall3_r[0]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[0].pat_match_fall3_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => wrcal_pat_resume_reg_0,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[0].pat_match_fall3_r[0]_i_1_n_0\,
      Q => early2_match_fall3_r(0),
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[0].pat_match_rise0_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => wrcal_pat_resume_reg_0,
      CE => '1',
      D => \gen_sr_div4.gen_sr[0].sr_rise0_r_reg[0]_295\,
      Q => early2_match_rise0_r(0),
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[0].pat_match_rise1_r[0]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr[0].sr_rise1_r_reg[0]_247\,
      O => \gen_pat_match_div4.gen_pat_match[0].pat_match_rise1_r[0]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[0].pat_match_rise1_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => wrcal_pat_resume_reg_0,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[0].pat_match_rise1_r[0]_i_1_n_0\,
      Q => \gen_pat_match_div4.gen_pat_match[0].pat_match_rise1_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[0].pat_match_rise2_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => wrcal_pat_resume_reg_0,
      CE => '1',
      D => \gen_sr_div4.gen_sr[0].sr_rise2_r_reg[0]_271\,
      Q => early2_match_rise2_r(0),
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[0].pat_match_rise3_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => wrcal_pat_resume_reg_0,
      CE => '1',
      D => \gen_sr_div4.gen_sr[0].sr_rise3_r_reg[0]_287\,
      Q => \gen_pat_match_div4.gen_pat_match[0].pat_match_rise3_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[1].early1_match_fall1_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => wrcal_pat_resume_reg_0,
      CE => '1',
      D => \gen_sr_div4.gen_sr[1].sr_fall1_r_reg[1]_304\,
      Q => early2_match_fall1_r(1),
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[1].early1_match_fall3_r[1]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr[1].sr_fall3_r_reg[1]_256\,
      O => \gen_pat_match_div4.gen_pat_match[1].early1_match_fall3_r[1]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[1].early1_match_fall3_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => wrcal_pat_resume_reg_0,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[1].early1_match_fall3_r[1]_i_1_n_0\,
      Q => early2_match_fall3_r(1),
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[1].early1_match_rise1_r[1]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr[1].sr_rise1_r_reg[1]_248\,
      O => \gen_pat_match_div4.gen_pat_match[1].early1_match_rise1_r[1]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[1].early1_match_rise1_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => wrcal_pat_resume_reg_0,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[1].early1_match_rise1_r[1]_i_1_n_0\,
      Q => early2_match_rise1_r(1),
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[1].early1_match_rise3_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => wrcal_pat_resume_reg_0,
      CE => '1',
      D => \gen_sr_div4.gen_sr[1].sr_rise3_r_reg[1]_288\,
      Q => early2_match_rise3_r(1),
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[1].early2_match_fall0_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => wrcal_pat_resume_reg_0,
      CE => '1',
      D => \gen_sr_div4.gen_sr[1].sr_fall0_r_reg[1]_264\,
      Q => early2_match_fall0_r(1),
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[1].early2_match_fall2_r[1]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr[1].sr_fall2_r_reg[1]_280\,
      O => \gen_pat_match_div4.gen_pat_match[1].early2_match_fall2_r[1]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[1].early2_match_fall2_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => wrcal_pat_resume_reg_0,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[1].early2_match_fall2_r[1]_i_1_n_0\,
      Q => early2_match_fall2_r(1),
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[1].early2_match_rise0_r[1]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr[1].sr_rise0_r_reg[1]_296\,
      O => \gen_pat_match_div4.gen_pat_match[1].early2_match_rise0_r[1]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[1].early2_match_rise0_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => wrcal_pat_resume_reg_0,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[1].early2_match_rise0_r[1]_i_1_n_0\,
      Q => early2_match_rise0_r(1),
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[1].early2_match_rise2_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => wrcal_pat_resume_reg_0,
      CE => '1',
      D => \gen_sr_div4.gen_sr[1].sr_rise2_r_reg[1]_272\,
      Q => early2_match_rise2_r(1),
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[1].pat_match_fall0_r[1]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr[1].sr_fall0_r_reg[1]_264\,
      O => \gen_pat_match_div4.gen_pat_match[1].pat_match_fall0_r[1]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[1].pat_match_fall0_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => wrcal_pat_resume_reg_0,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[1].pat_match_fall0_r[1]_i_1_n_0\,
      Q => early1_match_fall0_r(1),
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[1].pat_match_fall1_r[1]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr[1].sr_fall1_r_reg[1]_304\,
      O => \gen_pat_match_div4.gen_pat_match[1].pat_match_fall1_r[1]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[1].pat_match_fall1_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => wrcal_pat_resume_reg_0,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[1].pat_match_fall1_r[1]_i_1_n_0\,
      Q => \gen_pat_match_div4.gen_pat_match[1].pat_match_fall1_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[1].pat_match_fall2_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => wrcal_pat_resume_reg_0,
      CE => '1',
      D => \gen_sr_div4.gen_sr[1].sr_fall2_r_reg[1]_280\,
      Q => \gen_pat_match_div4.gen_pat_match[1].pat_match_fall2_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[1].pat_match_fall3_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => wrcal_pat_resume_reg_0,
      CE => '1',
      D => \gen_sr_div4.gen_sr[1].sr_fall3_r_reg[1]_256\,
      Q => \gen_pat_match_div4.gen_pat_match[1].pat_match_fall3_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[1].pat_match_rise0_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => wrcal_pat_resume_reg_0,
      CE => '1',
      D => \gen_sr_div4.gen_sr[1].sr_rise0_r_reg[1]_296\,
      Q => early1_match_rise0_r(1),
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[1].pat_match_rise1_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => wrcal_pat_resume_reg_0,
      CE => '1',
      D => \gen_sr_div4.gen_sr[1].sr_rise1_r_reg[1]_248\,
      Q => \gen_pat_match_div4.gen_pat_match[1].pat_match_rise1_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[1].pat_match_rise2_r[1]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr[1].sr_rise2_r_reg[1]_272\,
      O => \gen_pat_match_div4.gen_pat_match[1].pat_match_rise2_r[1]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[1].pat_match_rise2_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => wrcal_pat_resume_reg_0,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[1].pat_match_rise2_r[1]_i_1_n_0\,
      Q => \gen_pat_match_div4.gen_pat_match[1].pat_match_rise2_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[1].pat_match_rise3_r[1]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr[1].sr_rise3_r_reg[1]_288\,
      O => \gen_pat_match_div4.gen_pat_match[1].pat_match_rise3_r[1]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[1].pat_match_rise3_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => wrcal_pat_resume_reg_0,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[1].pat_match_rise3_r[1]_i_1_n_0\,
      Q => \gen_pat_match_div4.gen_pat_match[1].pat_match_rise3_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[2].early1_match_fall0_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => wrcal_pat_resume_reg_0,
      CE => '1',
      D => \gen_sr_div4.gen_sr[2].sr_fall0_r_reg[2]_265\,
      Q => early1_match_fall0_r(2),
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[2].early1_match_fall1_r[2]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr[2].sr_fall1_r_reg[2]_305\,
      O => \gen_pat_match_div4.gen_pat_match[2].early1_match_fall1_r[2]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[2].early1_match_fall1_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => wrcal_pat_resume_reg_0,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[2].early1_match_fall1_r[2]_i_1_n_0\,
      Q => \gen_pat_match_div4.gen_pat_match[2].early1_match_fall1_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[2].early1_match_fall2_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => wrcal_pat_resume_reg_0,
      CE => '1',
      D => \gen_sr_div4.gen_sr[2].sr_fall2_r_reg[2]_281\,
      Q => \gen_pat_match_div4.gen_pat_match[2].early1_match_fall2_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[2].early1_match_fall3_r[2]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr[2].sr_fall3_r_reg[2]_257\,
      O => \gen_pat_match_div4.gen_pat_match[2].early1_match_fall3_r[2]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[2].early1_match_fall3_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => wrcal_pat_resume_reg_0,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[2].early1_match_fall3_r[2]_i_1_n_0\,
      Q => \gen_pat_match_div4.gen_pat_match[2].early1_match_fall3_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[2].early1_match_rise0_r[2]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr[2].sr_rise0_r_reg[2]_297\,
      O => \gen_pat_match_div4.gen_pat_match[2].early1_match_rise0_r[2]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[2].early1_match_rise0_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => wrcal_pat_resume_reg_0,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[2].early1_match_rise0_r[2]_i_1_n_0\,
      Q => early1_match_rise0_r(2),
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[2].early1_match_rise1_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => wrcal_pat_resume_reg_0,
      CE => '1',
      D => \gen_sr_div4.gen_sr[2].sr_rise1_r_reg[2]_249\,
      Q => \gen_pat_match_div4.gen_pat_match[2].early1_match_rise1_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[2].early1_match_rise2_r[2]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr[2].sr_rise2_r_reg[2]_273\,
      O => \gen_pat_match_div4.gen_pat_match[2].early1_match_rise2_r[2]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[2].early1_match_rise2_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => wrcal_pat_resume_reg_0,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[2].early1_match_rise2_r[2]_i_1_n_0\,
      Q => early2_match_rise2_r(2),
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[2].early2_match_rise3_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => wrcal_pat_resume_reg_0,
      CE => '1',
      D => \gen_sr_div4.gen_sr[2].sr_rise3_r_reg[2]_289\,
      Q => early2_match_rise3_r(2),
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[2].pat_match_fall0_r[2]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr[2].sr_fall0_r_reg[2]_265\,
      O => \gen_pat_match_div4.gen_pat_match[2].pat_match_fall0_r[2]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[2].pat_match_fall0_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => wrcal_pat_resume_reg_0,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[2].pat_match_fall0_r[2]_i_1_n_0\,
      Q => early2_match_fall0_r(2),
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[2].pat_match_fall1_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => wrcal_pat_resume_reg_0,
      CE => '1',
      D => \gen_sr_div4.gen_sr[2].sr_fall1_r_reg[2]_305\,
      Q => early2_match_fall1_r(2),
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[2].pat_match_fall2_r[2]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr[2].sr_fall2_r_reg[2]_281\,
      O => \gen_pat_match_div4.gen_pat_match[2].pat_match_fall2_r[2]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[2].pat_match_fall2_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => wrcal_pat_resume_reg_0,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[2].pat_match_fall2_r[2]_i_1_n_0\,
      Q => early2_match_fall2_r(2),
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[2].pat_match_fall3_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => wrcal_pat_resume_reg_0,
      CE => '1',
      D => \gen_sr_div4.gen_sr[2].sr_fall3_r_reg[2]_257\,
      Q => early2_match_fall3_r(2),
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[2].pat_match_rise0_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => wrcal_pat_resume_reg_0,
      CE => '1',
      D => \gen_sr_div4.gen_sr[2].sr_rise0_r_reg[2]_297\,
      Q => early2_match_rise0_r(2),
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[2].pat_match_rise1_r[2]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr[2].sr_rise1_r_reg[2]_249\,
      O => \gen_pat_match_div4.gen_pat_match[2].pat_match_rise1_r[2]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[2].pat_match_rise1_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => wrcal_pat_resume_reg_0,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[2].pat_match_rise1_r[2]_i_1_n_0\,
      Q => early2_match_rise1_r(2),
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[2].pat_match_rise2_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => wrcal_pat_resume_reg_0,
      CE => '1',
      D => \gen_sr_div4.gen_sr[2].sr_rise2_r_reg[2]_273\,
      Q => \gen_pat_match_div4.gen_pat_match[2].pat_match_rise2_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[2].pat_match_rise3_r[2]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr[2].sr_rise3_r_reg[2]_289\,
      O => \gen_pat_match_div4.gen_pat_match[2].pat_match_rise3_r[2]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[2].pat_match_rise3_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => wrcal_pat_resume_reg_0,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[2].pat_match_rise3_r[2]_i_1_n_0\,
      Q => \gen_pat_match_div4.gen_pat_match[2].pat_match_rise3_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[3].early1_match_fall1_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => wrcal_pat_resume_reg_0,
      CE => '1',
      D => \gen_sr_div4.gen_sr[3].sr_fall1_r_reg[3]_306\,
      Q => \gen_pat_match_div4.gen_pat_match[3].early1_match_fall1_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[3].early1_match_fall2_r[3]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr[3].sr_fall2_r_reg[3]_282\,
      O => \gen_pat_match_div4.gen_pat_match[3].early1_match_fall2_r[3]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[3].early1_match_fall2_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => wrcal_pat_resume_reg_0,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[3].early1_match_fall2_r[3]_i_1_n_0\,
      Q => early2_match_fall2_r(3),
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[3].early1_match_rise1_r[3]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr[3].sr_rise1_r_reg[3]_250\,
      O => \gen_pat_match_div4.gen_pat_match[3].early1_match_rise1_r[3]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[3].early1_match_rise1_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => wrcal_pat_resume_reg_0,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[3].early1_match_rise1_r[3]_i_1_n_0\,
      Q => \gen_pat_match_div4.gen_pat_match[3].early1_match_rise1_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[3].early1_match_rise2_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => wrcal_pat_resume_reg_0,
      CE => '1',
      D => \gen_sr_div4.gen_sr[3].sr_rise2_r_reg[3]_274\,
      Q => early2_match_rise2_r(3),
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[3].early2_match_fall0_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => wrcal_pat_resume_reg_0,
      CE => '1',
      D => \gen_sr_div4.gen_sr[3].sr_fall0_r_reg[3]_266\,
      Q => early2_match_fall0_r(3),
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[3].early2_match_rise0_r[3]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr[3].sr_rise0_r_reg[3]_298\,
      O => \gen_pat_match_div4.gen_pat_match[3].early2_match_rise0_r[3]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[3].early2_match_rise0_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => wrcal_pat_resume_reg_0,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[3].early2_match_rise0_r[3]_i_1_n_0\,
      Q => early2_match_rise0_r(3),
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[3].pat_match_fall0_r[3]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr[3].sr_fall0_r_reg[3]_266\,
      O => \gen_pat_match_div4.gen_pat_match[3].pat_match_fall0_r[3]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[3].pat_match_fall0_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => wrcal_pat_resume_reg_0,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[3].pat_match_fall0_r[3]_i_1_n_0\,
      Q => early1_match_fall0_r(3),
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[3].pat_match_fall1_r[3]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr[3].sr_fall1_r_reg[3]_306\,
      O => \gen_pat_match_div4.gen_pat_match[3].pat_match_fall1_r[3]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[3].pat_match_fall1_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => wrcal_pat_resume_reg_0,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[3].pat_match_fall1_r[3]_i_1_n_0\,
      Q => early2_match_fall1_r(3),
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[3].pat_match_fall2_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => wrcal_pat_resume_reg_0,
      CE => '1',
      D => \gen_sr_div4.gen_sr[3].sr_fall2_r_reg[3]_282\,
      Q => \gen_pat_match_div4.gen_pat_match[3].pat_match_fall2_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[3].pat_match_fall3_r[3]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr[3].sr_fall3_r_reg[3]_258\,
      O => \gen_pat_match_div4.gen_pat_match[3].pat_match_fall3_r[3]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[3].pat_match_fall3_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => wrcal_pat_resume_reg_0,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[3].pat_match_fall3_r[3]_i_1_n_0\,
      Q => early2_match_fall3_r(3),
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[3].pat_match_rise0_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => wrcal_pat_resume_reg_0,
      CE => '1',
      D => \gen_sr_div4.gen_sr[3].sr_rise0_r_reg[3]_298\,
      Q => early1_match_rise0_r(3),
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[3].pat_match_rise1_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => wrcal_pat_resume_reg_0,
      CE => '1',
      D => \gen_sr_div4.gen_sr[3].sr_rise1_r_reg[3]_250\,
      Q => early2_match_rise1_r(3),
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[3].pat_match_rise2_r[3]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr[3].sr_rise2_r_reg[3]_274\,
      O => \gen_pat_match_div4.gen_pat_match[3].pat_match_rise2_r[3]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[3].pat_match_rise2_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => wrcal_pat_resume_reg_0,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[3].pat_match_rise2_r[3]_i_1_n_0\,
      Q => \gen_pat_match_div4.gen_pat_match[3].pat_match_rise2_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[3].pat_match_rise3_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => wrcal_pat_resume_reg_0,
      CE => '1',
      D => \gen_sr_div4.gen_sr[3].sr_rise3_r_reg[3]_290\,
      Q => early2_match_rise3_r(3),
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[4].early1_match_fall0_r_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => wrcal_pat_resume_reg_0,
      CE => '1',
      D => \gen_sr_div4.gen_sr[4].sr_fall0_r_reg[4]_267\,
      Q => early1_match_fall0_r(4),
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[4].early1_match_fall1_r[4]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr[4].sr_fall1_r_reg[4]_307\,
      O => \gen_pat_match_div4.gen_pat_match[4].early1_match_fall1_r[4]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[4].early1_match_fall1_r_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => wrcal_pat_resume_reg_0,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[4].early1_match_fall1_r[4]_i_1_n_0\,
      Q => early2_match_fall1_r(4),
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[4].early1_match_fall3_r_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => wrcal_pat_resume_reg_0,
      CE => '1',
      D => \gen_sr_div4.gen_sr[4].sr_fall3_r_reg[4]_259\,
      Q => \gen_pat_match_div4.gen_pat_match[4].early1_match_fall3_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[4].early1_match_rise0_r[4]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr[4].sr_rise0_r_reg[4]_299\,
      O => \gen_pat_match_div4.gen_pat_match[4].early1_match_rise0_r[4]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[4].early1_match_rise0_r_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => wrcal_pat_resume_reg_0,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[4].early1_match_rise0_r[4]_i_1_n_0\,
      Q => early1_match_rise0_r(4),
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[4].early1_match_rise1_r_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => wrcal_pat_resume_reg_0,
      CE => '1',
      D => \gen_sr_div4.gen_sr[4].sr_rise1_r_reg[4]_251\,
      Q => early2_match_rise1_r(4),
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[4].early2_match_fall2_r_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => wrcal_pat_resume_reg_0,
      CE => '1',
      D => \gen_sr_div4.gen_sr[4].sr_fall2_r_reg[4]_283\,
      Q => early2_match_fall2_r(4),
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[4].early2_match_rise3_r[4]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr[4].sr_rise3_r_reg[4]_291\,
      O => \gen_pat_match_div4.gen_pat_match[4].early2_match_rise3_r[4]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[4].early2_match_rise3_r_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => wrcal_pat_resume_reg_0,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[4].early2_match_rise3_r[4]_i_1_n_0\,
      Q => early2_match_rise3_r(4),
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[4].pat_match_fall0_r[4]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr[4].sr_fall0_r_reg[4]_267\,
      O => \gen_pat_match_div4.gen_pat_match[4].pat_match_fall0_r[4]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[4].pat_match_fall0_r_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => wrcal_pat_resume_reg_0,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[4].pat_match_fall0_r[4]_i_1_n_0\,
      Q => early2_match_fall0_r(4),
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[4].pat_match_fall1_r_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => wrcal_pat_resume_reg_0,
      CE => '1',
      D => \gen_sr_div4.gen_sr[4].sr_fall1_r_reg[4]_307\,
      Q => \gen_pat_match_div4.gen_pat_match[4].pat_match_fall1_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[4].pat_match_fall2_r[4]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr[4].sr_fall2_r_reg[4]_283\,
      O => \gen_pat_match_div4.gen_pat_match[4].pat_match_fall2_r[4]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[4].pat_match_fall2_r_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => wrcal_pat_resume_reg_0,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[4].pat_match_fall2_r[4]_i_1_n_0\,
      Q => \gen_pat_match_div4.gen_pat_match[4].pat_match_fall2_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[4].pat_match_fall3_r[4]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr[4].sr_fall3_r_reg[4]_259\,
      O => \gen_pat_match_div4.gen_pat_match[4].pat_match_fall3_r[4]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[4].pat_match_fall3_r_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => wrcal_pat_resume_reg_0,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[4].pat_match_fall3_r[4]_i_1_n_0\,
      Q => early2_match_fall3_r(4),
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[4].pat_match_rise0_r_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => wrcal_pat_resume_reg_0,
      CE => '1',
      D => \gen_sr_div4.gen_sr[4].sr_rise0_r_reg[4]_299\,
      Q => early2_match_rise0_r(4),
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[4].pat_match_rise1_r[4]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr[4].sr_rise1_r_reg[4]_251\,
      O => \gen_pat_match_div4.gen_pat_match[4].pat_match_rise1_r[4]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[4].pat_match_rise1_r_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => wrcal_pat_resume_reg_0,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[4].pat_match_rise1_r[4]_i_1_n_0\,
      Q => \gen_pat_match_div4.gen_pat_match[4].pat_match_rise1_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[4].pat_match_rise2_r_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => wrcal_pat_resume_reg_0,
      CE => '1',
      D => \gen_sr_div4.gen_sr[4].sr_rise2_r_reg[4]_275\,
      Q => early2_match_rise2_r(4),
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[4].pat_match_rise3_r_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => wrcal_pat_resume_reg_0,
      CE => '1',
      D => \gen_sr_div4.gen_sr[4].sr_rise3_r_reg[4]_291\,
      Q => \gen_pat_match_div4.gen_pat_match[4].pat_match_rise3_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[5].early1_match_fall1_r_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => wrcal_pat_resume_reg_0,
      CE => '1',
      D => \gen_sr_div4.gen_sr[5].sr_fall1_r_reg[5]_308\,
      Q => early2_match_fall1_r(5),
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[5].early1_match_fall3_r[5]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr[5].sr_fall3_r_reg[5]_260\,
      O => \gen_pat_match_div4.gen_pat_match[5].early1_match_fall3_r[5]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[5].early1_match_fall3_r_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => wrcal_pat_resume_reg_0,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[5].early1_match_fall3_r[5]_i_1_n_0\,
      Q => early2_match_fall3_r(5),
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[5].early1_match_rise1_r[5]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr[5].sr_rise1_r_reg[5]_252\,
      O => \gen_pat_match_div4.gen_pat_match[5].early1_match_rise1_r[5]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[5].early1_match_rise1_r_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => wrcal_pat_resume_reg_0,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[5].early1_match_rise1_r[5]_i_1_n_0\,
      Q => early2_match_rise1_r(5),
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[5].early1_match_rise3_r_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => wrcal_pat_resume_reg_0,
      CE => '1',
      D => \gen_sr_div4.gen_sr[5].sr_rise3_r_reg[5]_292\,
      Q => early2_match_rise3_r(5),
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[5].early2_match_fall0_r_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => wrcal_pat_resume_reg_0,
      CE => '1',
      D => \gen_sr_div4.gen_sr[5].sr_fall0_r_reg[5]_268\,
      Q => early2_match_fall0_r(5),
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[5].early2_match_fall2_r[5]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr[5].sr_fall2_r_reg[5]_284\,
      O => \gen_pat_match_div4.gen_pat_match[5].early2_match_fall2_r[5]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[5].early2_match_fall2_r_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => wrcal_pat_resume_reg_0,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[5].early2_match_fall2_r[5]_i_1_n_0\,
      Q => early2_match_fall2_r(5),
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[5].early2_match_rise0_r[5]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr[5].sr_rise0_r_reg[5]_300\,
      O => \gen_pat_match_div4.gen_pat_match[5].early2_match_rise0_r[5]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[5].early2_match_rise0_r_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => wrcal_pat_resume_reg_0,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[5].early2_match_rise0_r[5]_i_1_n_0\,
      Q => early2_match_rise0_r(5),
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[5].early2_match_rise2_r_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => wrcal_pat_resume_reg_0,
      CE => '1',
      D => \gen_sr_div4.gen_sr[5].sr_rise2_r_reg[5]_276\,
      Q => early2_match_rise2_r(5),
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[5].pat_match_fall0_r[5]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr[5].sr_fall0_r_reg[5]_268\,
      O => \gen_pat_match_div4.gen_pat_match[5].pat_match_fall0_r[5]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[5].pat_match_fall0_r_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => wrcal_pat_resume_reg_0,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[5].pat_match_fall0_r[5]_i_1_n_0\,
      Q => early1_match_fall0_r(5),
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[5].pat_match_fall1_r[5]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr[5].sr_fall1_r_reg[5]_308\,
      O => \gen_pat_match_div4.gen_pat_match[5].pat_match_fall1_r[5]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[5].pat_match_fall1_r_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => wrcal_pat_resume_reg_0,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[5].pat_match_fall1_r[5]_i_1_n_0\,
      Q => \gen_pat_match_div4.gen_pat_match[5].pat_match_fall1_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[5].pat_match_fall2_r_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => wrcal_pat_resume_reg_0,
      CE => '1',
      D => \gen_sr_div4.gen_sr[5].sr_fall2_r_reg[5]_284\,
      Q => \gen_pat_match_div4.gen_pat_match[5].pat_match_fall2_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[5].pat_match_fall3_r_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => wrcal_pat_resume_reg_0,
      CE => '1',
      D => \gen_sr_div4.gen_sr[5].sr_fall3_r_reg[5]_260\,
      Q => \gen_pat_match_div4.gen_pat_match[5].pat_match_fall3_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[5].pat_match_rise0_r_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => wrcal_pat_resume_reg_0,
      CE => '1',
      D => \gen_sr_div4.gen_sr[5].sr_rise0_r_reg[5]_300\,
      Q => early1_match_rise0_r(5),
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[5].pat_match_rise1_r_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => wrcal_pat_resume_reg_0,
      CE => '1',
      D => \gen_sr_div4.gen_sr[5].sr_rise1_r_reg[5]_252\,
      Q => \gen_pat_match_div4.gen_pat_match[5].pat_match_rise1_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[5].pat_match_rise2_r[5]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr[5].sr_rise2_r_reg[5]_276\,
      O => \gen_pat_match_div4.gen_pat_match[5].pat_match_rise2_r[5]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[5].pat_match_rise2_r_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => wrcal_pat_resume_reg_0,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[5].pat_match_rise2_r[5]_i_1_n_0\,
      Q => \gen_pat_match_div4.gen_pat_match[5].pat_match_rise2_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[5].pat_match_rise3_r[5]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr[5].sr_rise3_r_reg[5]_292\,
      O => \gen_pat_match_div4.gen_pat_match[5].pat_match_rise3_r[5]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[5].pat_match_rise3_r_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => wrcal_pat_resume_reg_0,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[5].pat_match_rise3_r[5]_i_1_n_0\,
      Q => \gen_pat_match_div4.gen_pat_match[5].pat_match_rise3_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[6].early1_match_fall0_r_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => wrcal_pat_resume_reg_0,
      CE => '1',
      D => \gen_sr_div4.gen_sr[6].sr_fall0_r_reg[6]_269\,
      Q => early1_match_fall0_r(6),
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[6].early1_match_fall1_r[6]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr[6].sr_fall1_r_reg[6]_309\,
      O => \gen_pat_match_div4.gen_pat_match[6].early1_match_fall1_r[6]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[6].early1_match_fall1_r_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => wrcal_pat_resume_reg_0,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[6].early1_match_fall1_r[6]_i_1_n_0\,
      Q => \gen_pat_match_div4.gen_pat_match[6].early1_match_fall1_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[6].early1_match_fall2_r_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => wrcal_pat_resume_reg_0,
      CE => '1',
      D => \gen_sr_div4.gen_sr[6].sr_fall2_r_reg[6]_285\,
      Q => \gen_pat_match_div4.gen_pat_match[6].early1_match_fall2_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[6].early1_match_fall3_r[6]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr[6].sr_fall3_r_reg[6]_261\,
      O => \gen_pat_match_div4.gen_pat_match[6].early1_match_fall3_r[6]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[6].early1_match_fall3_r_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => wrcal_pat_resume_reg_0,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[6].early1_match_fall3_r[6]_i_1_n_0\,
      Q => \gen_pat_match_div4.gen_pat_match[6].early1_match_fall3_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[6].early1_match_rise0_r[6]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr[6].sr_rise0_r_reg[6]_301\,
      O => \gen_pat_match_div4.gen_pat_match[6].early1_match_rise0_r[6]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[6].early1_match_rise0_r_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => wrcal_pat_resume_reg_0,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[6].early1_match_rise0_r[6]_i_1_n_0\,
      Q => early1_match_rise0_r(6),
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[6].early1_match_rise1_r_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => wrcal_pat_resume_reg_0,
      CE => '1',
      D => \gen_sr_div4.gen_sr[6].sr_rise1_r_reg[6]_253\,
      Q => \gen_pat_match_div4.gen_pat_match[6].early1_match_rise1_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[6].early1_match_rise2_r[6]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr[6].sr_rise2_r_reg[6]_277\,
      O => \gen_pat_match_div4.gen_pat_match[6].early1_match_rise2_r[6]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[6].early1_match_rise2_r_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => wrcal_pat_resume_reg_0,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[6].early1_match_rise2_r[6]_i_1_n_0\,
      Q => early2_match_rise2_r(6),
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[6].early2_match_rise3_r_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => wrcal_pat_resume_reg_0,
      CE => '1',
      D => \gen_sr_div4.gen_sr[6].sr_rise3_r_reg[6]_293\,
      Q => early2_match_rise3_r(6),
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[6].pat_match_fall0_r[6]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr[6].sr_fall0_r_reg[6]_269\,
      O => \gen_pat_match_div4.gen_pat_match[6].pat_match_fall0_r[6]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[6].pat_match_fall0_r_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => wrcal_pat_resume_reg_0,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[6].pat_match_fall0_r[6]_i_1_n_0\,
      Q => early2_match_fall0_r(6),
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[6].pat_match_fall1_r_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => wrcal_pat_resume_reg_0,
      CE => '1',
      D => \gen_sr_div4.gen_sr[6].sr_fall1_r_reg[6]_309\,
      Q => early2_match_fall1_r(6),
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[6].pat_match_fall2_r[6]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr[6].sr_fall2_r_reg[6]_285\,
      O => \gen_pat_match_div4.gen_pat_match[6].pat_match_fall2_r[6]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[6].pat_match_fall2_r_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => wrcal_pat_resume_reg_0,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[6].pat_match_fall2_r[6]_i_1_n_0\,
      Q => early2_match_fall2_r(6),
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[6].pat_match_fall3_r_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => wrcal_pat_resume_reg_0,
      CE => '1',
      D => \gen_sr_div4.gen_sr[6].sr_fall3_r_reg[6]_261\,
      Q => early2_match_fall3_r(6),
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[6].pat_match_rise0_r_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => wrcal_pat_resume_reg_0,
      CE => '1',
      D => \gen_sr_div4.gen_sr[6].sr_rise0_r_reg[6]_301\,
      Q => early2_match_rise0_r(6),
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[6].pat_match_rise1_r[6]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr[6].sr_rise1_r_reg[6]_253\,
      O => \gen_pat_match_div4.gen_pat_match[6].pat_match_rise1_r[6]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[6].pat_match_rise1_r_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => wrcal_pat_resume_reg_0,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[6].pat_match_rise1_r[6]_i_1_n_0\,
      Q => early2_match_rise1_r(6),
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[6].pat_match_rise2_r_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => wrcal_pat_resume_reg_0,
      CE => '1',
      D => \gen_sr_div4.gen_sr[6].sr_rise2_r_reg[6]_277\,
      Q => \gen_pat_match_div4.gen_pat_match[6].pat_match_rise2_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[6].pat_match_rise3_r[6]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr[6].sr_rise3_r_reg[6]_293\,
      O => \gen_pat_match_div4.gen_pat_match[6].pat_match_rise3_r[6]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[6].pat_match_rise3_r_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => wrcal_pat_resume_reg_0,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[6].pat_match_rise3_r[6]_i_1_n_0\,
      Q => \gen_pat_match_div4.gen_pat_match[6].pat_match_rise3_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[7].early1_match_fall1_r_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => wrcal_pat_resume_reg_0,
      CE => '1',
      D => \gen_sr_div4.gen_sr[7].sr_fall1_r_reg[7]_310\,
      Q => \gen_pat_match_div4.gen_pat_match[7].early1_match_fall1_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[7].early1_match_fall2_r[7]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr[7].sr_fall2_r_reg[7]_286\,
      O => \gen_pat_match_div4.gen_pat_match[7].early1_match_fall2_r[7]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[7].early1_match_fall2_r_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => wrcal_pat_resume_reg_0,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[7].early1_match_fall2_r[7]_i_1_n_0\,
      Q => early2_match_fall2_r(7),
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[7].early1_match_rise1_r[7]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr[7].sr_rise1_r_reg[7]_254\,
      O => \gen_pat_match_div4.gen_pat_match[7].early1_match_rise1_r[7]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[7].early1_match_rise1_r_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => wrcal_pat_resume_reg_0,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[7].early1_match_rise1_r[7]_i_1_n_0\,
      Q => \gen_pat_match_div4.gen_pat_match[7].early1_match_rise1_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[7].early1_match_rise2_r_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => wrcal_pat_resume_reg_0,
      CE => '1',
      D => \gen_sr_div4.gen_sr[7].sr_rise2_r_reg[7]_278\,
      Q => early2_match_rise2_r(7),
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[7].early2_match_fall0_r_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => wrcal_pat_resume_reg_0,
      CE => '1',
      D => \gen_sr_div4.gen_sr[7].sr_fall0_r_reg[7]_270\,
      Q => early2_match_fall0_r(7),
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[7].early2_match_rise0_r[7]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr[7].sr_rise0_r_reg[7]_302\,
      O => \gen_pat_match_div4.gen_pat_match[7].early2_match_rise0_r[7]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[7].early2_match_rise0_r_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => wrcal_pat_resume_reg_0,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[7].early2_match_rise0_r[7]_i_1_n_0\,
      Q => early2_match_rise0_r(7),
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[7].pat_match_fall0_r[7]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr[7].sr_fall0_r_reg[7]_270\,
      O => \gen_pat_match_div4.gen_pat_match[7].pat_match_fall0_r[7]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[7].pat_match_fall0_r_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => wrcal_pat_resume_reg_0,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[7].pat_match_fall0_r[7]_i_1_n_0\,
      Q => early1_match_fall0_r(7),
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[7].pat_match_fall1_r[7]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr[7].sr_fall1_r_reg[7]_310\,
      O => \gen_pat_match_div4.gen_pat_match[7].pat_match_fall1_r[7]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[7].pat_match_fall1_r_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => wrcal_pat_resume_reg_0,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[7].pat_match_fall1_r[7]_i_1_n_0\,
      Q => early2_match_fall1_r(7),
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[7].pat_match_fall2_r_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => wrcal_pat_resume_reg_0,
      CE => '1',
      D => \gen_sr_div4.gen_sr[7].sr_fall2_r_reg[7]_286\,
      Q => \gen_pat_match_div4.gen_pat_match[7].pat_match_fall2_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[7].pat_match_fall3_r[7]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr[7].sr_fall3_r_reg[7]_262\,
      O => \gen_pat_match_div4.gen_pat_match[7].pat_match_fall3_r[7]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[7].pat_match_fall3_r_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => wrcal_pat_resume_reg_0,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[7].pat_match_fall3_r[7]_i_1_n_0\,
      Q => early2_match_fall3_r(7),
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[7].pat_match_rise0_r_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => wrcal_pat_resume_reg_0,
      CE => '1',
      D => \gen_sr_div4.gen_sr[7].sr_rise0_r_reg[7]_302\,
      Q => early1_match_rise0_r(7),
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[7].pat_match_rise1_r_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => wrcal_pat_resume_reg_0,
      CE => '1',
      D => \gen_sr_div4.gen_sr[7].sr_rise1_r_reg[7]_254\,
      Q => early2_match_rise1_r(7),
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[7].pat_match_rise2_r[7]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr[7].sr_rise2_r_reg[7]_278\,
      O => \gen_pat_match_div4.gen_pat_match[7].pat_match_rise2_r[7]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[7].pat_match_rise2_r_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => wrcal_pat_resume_reg_0,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[7].pat_match_rise2_r[7]_i_1_n_0\,
      Q => \gen_pat_match_div4.gen_pat_match[7].pat_match_rise2_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[7].pat_match_rise3_r_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => wrcal_pat_resume_reg_0,
      CE => '1',
      D => \gen_sr_div4.gen_sr[7].sr_rise3_r_reg[7]_294\,
      Q => early2_match_rise3_r(7),
      R => '0'
    );
\gen_pat_match_div4.pat_data_match_r_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00008000"
    )
        port map (
      I0 => pat_match_fall0_and_r,
      I1 => pat_match_rise2_and_r,
      I2 => pat_match_rise1_and_r,
      I3 => pat_match_fall1_and_r,
      I4 => \gen_pat_match_div4.pat_data_match_r_i_2_n_0\,
      O => pat_data_match_r0
    );
\gen_pat_match_div4.pat_data_match_r_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7FFF"
    )
        port map (
      I0 => pat_match_rise0_and_r,
      I1 => pat_match_rise3_and_r,
      I2 => pat_match_fall3_and_r,
      I3 => pat_match_fall2_and_r,
      O => \gen_pat_match_div4.pat_data_match_r_i_2_n_0\
    );
\gen_pat_match_div4.pat_data_match_r_reg\: unisim.vcomponents.FDRE
     port map (
      C => wrcal_pat_resume_reg_0,
      CE => '1',
      D => pat_data_match_r0,
      Q => \gen_pat_match_div4.pat_data_match_r_reg_n_0\,
      R => '0'
    );
\gen_pat_match_div4.pat_data_match_valid_r_reg\: unisim.vcomponents.FDRE
     port map (
      C => wrcal_pat_resume_reg_0,
      CE => '1',
      D => rd_active_r3_reg_srl2_n_0,
      Q => \gen_pat_match_div4.pat_data_match_valid_r_reg_n_0\,
      R => '0'
    );
\gen_pat_match_div4.pat_match_fall0_and_r_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00008000"
    )
        port map (
      I0 => early2_match_fall0_r(2),
      I1 => early2_match_fall0_r(0),
      I2 => early2_match_fall0_r(6),
      I3 => early2_match_fall0_r(4),
      I4 => \gen_pat_match_div4.early1_match_fall0_and_r_i_2_n_0\,
      O => \gen_pat_match_div4.pat_match_fall0_and_r_i_1_n_0\
    );
\gen_pat_match_div4.pat_match_fall0_and_r_reg\: unisim.vcomponents.FDRE
     port map (
      C => wrcal_pat_resume_reg_0,
      CE => '1',
      D => \gen_pat_match_div4.pat_match_fall0_and_r_i_1_n_0\,
      Q => pat_match_fall0_and_r,
      R => '0'
    );
\gen_pat_match_div4.pat_match_fall1_and_r_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"80000000"
    )
        port map (
      I0 => \gen_pat_match_div4.early2_match_fall1_and_r_i_2_n_0\,
      I1 => \gen_pat_match_div4.gen_pat_match[4].pat_match_fall1_r_reg\,
      I2 => \gen_pat_match_div4.gen_pat_match[1].pat_match_fall1_r_reg\,
      I3 => \gen_pat_match_div4.gen_pat_match[5].pat_match_fall1_r_reg\,
      I4 => \gen_pat_match_div4.gen_pat_match[0].pat_match_fall1_r_reg\,
      O => \gen_pat_match_div4.pat_match_fall1_and_r_i_1_n_0\
    );
\gen_pat_match_div4.pat_match_fall1_and_r_reg\: unisim.vcomponents.FDRE
     port map (
      C => wrcal_pat_resume_reg_0,
      CE => '1',
      D => \gen_pat_match_div4.pat_match_fall1_and_r_i_1_n_0\,
      Q => pat_match_fall1_and_r,
      R => '0'
    );
\gen_pat_match_div4.pat_match_fall2_and_r_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"80000000"
    )
        port map (
      I0 => \gen_pat_match_div4.early1_match_fall2_and_r_i_2_n_0\,
      I1 => \gen_pat_match_div4.gen_pat_match[7].pat_match_fall2_r_reg\,
      I2 => \gen_pat_match_div4.gen_pat_match[3].pat_match_fall2_r_reg\,
      I3 => early2_match_fall2_r(6),
      I4 => early2_match_fall2_r(2),
      O => \gen_pat_match_div4.pat_match_fall2_and_r_i_1_n_0\
    );
\gen_pat_match_div4.pat_match_fall2_and_r_reg\: unisim.vcomponents.FDRE
     port map (
      C => wrcal_pat_resume_reg_0,
      CE => '1',
      D => \gen_pat_match_div4.pat_match_fall2_and_r_i_1_n_0\,
      Q => pat_match_fall2_and_r,
      R => '0'
    );
\gen_pat_match_div4.pat_match_fall3_and_r_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"80000000"
    )
        port map (
      I0 => \gen_pat_match_div4.early2_match_fall3_and_r_i_2_n_0\,
      I1 => \gen_pat_match_div4.gen_pat_match[5].pat_match_fall3_r_reg\,
      I2 => \gen_pat_match_div4.gen_pat_match[1].pat_match_fall3_r_reg\,
      I3 => early2_match_fall3_r(7),
      I4 => early2_match_fall3_r(3),
      O => \gen_pat_match_div4.pat_match_fall3_and_r_i_1_n_0\
    );
\gen_pat_match_div4.pat_match_fall3_and_r_reg\: unisim.vcomponents.FDRE
     port map (
      C => wrcal_pat_resume_reg_0,
      CE => '1',
      D => \gen_pat_match_div4.pat_match_fall3_and_r_i_1_n_0\,
      Q => pat_match_fall3_and_r,
      R => '0'
    );
\gen_pat_match_div4.pat_match_rise0_and_r_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00008000"
    )
        port map (
      I0 => early2_match_rise0_r(2),
      I1 => early2_match_rise0_r(0),
      I2 => early2_match_rise0_r(6),
      I3 => early2_match_rise0_r(4),
      I4 => \gen_pat_match_div4.early1_match_rise0_and_r_i_2_n_0\,
      O => \gen_pat_match_div4.pat_match_rise0_and_r_i_1_n_0\
    );
\gen_pat_match_div4.pat_match_rise0_and_r_reg\: unisim.vcomponents.FDRE
     port map (
      C => wrcal_pat_resume_reg_0,
      CE => '1',
      D => \gen_pat_match_div4.pat_match_rise0_and_r_i_1_n_0\,
      Q => pat_match_rise0_and_r,
      R => '0'
    );
\gen_pat_match_div4.pat_match_rise1_and_r_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"80000000"
    )
        port map (
      I0 => \gen_pat_match_div4.early2_match_rise1_and_r_i_2_n_0\,
      I1 => \gen_pat_match_div4.gen_pat_match[4].pat_match_rise1_r_reg\,
      I2 => \gen_pat_match_div4.gen_pat_match[1].pat_match_rise1_r_reg\,
      I3 => \gen_pat_match_div4.gen_pat_match[5].pat_match_rise1_r_reg\,
      I4 => \gen_pat_match_div4.gen_pat_match[0].pat_match_rise1_r_reg\,
      O => \gen_pat_match_div4.pat_match_rise1_and_r_i_1_n_0\
    );
\gen_pat_match_div4.pat_match_rise1_and_r_reg\: unisim.vcomponents.FDRE
     port map (
      C => wrcal_pat_resume_reg_0,
      CE => '1',
      D => \gen_pat_match_div4.pat_match_rise1_and_r_i_1_n_0\,
      Q => pat_match_rise1_and_r,
      R => '0'
    );
\gen_pat_match_div4.pat_match_rise2_and_r_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"80000000"
    )
        port map (
      I0 => \gen_pat_match_div4.early1_match_rise2_and_r_i_2_n_0\,
      I1 => \gen_pat_match_div4.gen_pat_match[6].pat_match_rise2_r_reg\,
      I2 => \gen_pat_match_div4.gen_pat_match[3].pat_match_rise2_r_reg\,
      I3 => \gen_pat_match_div4.gen_pat_match[7].pat_match_rise2_r_reg\,
      I4 => \gen_pat_match_div4.gen_pat_match[2].pat_match_rise2_r_reg\,
      O => \gen_pat_match_div4.pat_match_rise2_and_r_i_1_n_0\
    );
\gen_pat_match_div4.pat_match_rise2_and_r_reg\: unisim.vcomponents.FDRE
     port map (
      C => wrcal_pat_resume_reg_0,
      CE => '1',
      D => \gen_pat_match_div4.pat_match_rise2_and_r_i_1_n_0\,
      Q => pat_match_rise2_and_r,
      R => '0'
    );
\gen_pat_match_div4.pat_match_rise3_and_r_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"80000000"
    )
        port map (
      I0 => \gen_pat_match_div4.early1_match_rise3_and_r_i_2_n_0\,
      I1 => \gen_pat_match_div4.gen_pat_match[5].pat_match_rise3_r_reg\,
      I2 => \gen_pat_match_div4.gen_pat_match[1].pat_match_rise3_r_reg\,
      I3 => \gen_pat_match_div4.gen_pat_match[4].pat_match_rise3_r_reg\,
      I4 => \gen_pat_match_div4.gen_pat_match[0].pat_match_rise3_r_reg\,
      O => \gen_pat_match_div4.pat_match_rise3_and_r_i_1_n_0\
    );
\gen_pat_match_div4.pat_match_rise3_and_r_reg\: unisim.vcomponents.FDRE
     port map (
      C => wrcal_pat_resume_reg_0,
      CE => '1',
      D => \gen_pat_match_div4.pat_match_rise3_and_r_i_1_n_0\,
      Q => pat_match_rise3_and_r,
      R => '0'
    );
\gen_sr_div4.gen_sr[0].sr_fall0_r_reg[0][0]\: unisim.vcomponents.FDRE
     port map (
      C => wrcal_pat_resume_reg_0,
      CE => '1',
      D => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg_n_0_[0]\,
      Q => \gen_sr_div4.gen_sr[0].sr_fall0_r_reg[0]_263\,
      R => '0'
    );
\gen_sr_div4.gen_sr[0].sr_fall1_r_reg[0][0]\: unisim.vcomponents.FDRE
     port map (
      C => wrcal_pat_resume_reg_0,
      CE => '1',
      D => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg_n_0_[0]\,
      Q => \gen_sr_div4.gen_sr[0].sr_fall1_r_reg[0]_303\,
      R => '0'
    );
\gen_sr_div4.gen_sr[0].sr_fall2_r_reg[0][0]\: unisim.vcomponents.FDRE
     port map (
      C => wrcal_pat_resume_reg_0,
      CE => '1',
      D => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg_n_0_[0]\,
      Q => \gen_sr_div4.gen_sr[0].sr_fall2_r_reg[0]_279\,
      R => '0'
    );
\gen_sr_div4.gen_sr[0].sr_fall3_r_reg[0][0]\: unisim.vcomponents.FDRE
     port map (
      C => wrcal_pat_resume_reg_0,
      CE => '1',
      D => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg_n_0_[0]\,
      Q => \gen_sr_div4.gen_sr[0].sr_fall3_r_reg[0]_255\,
      R => '0'
    );
\gen_sr_div4.gen_sr[0].sr_rise0_r_reg[0][0]\: unisim.vcomponents.FDRE
     port map (
      C => wrcal_pat_resume_reg_0,
      CE => '1',
      D => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg_n_0_[0]\,
      Q => \gen_sr_div4.gen_sr[0].sr_rise0_r_reg[0]_295\,
      R => '0'
    );
\gen_sr_div4.gen_sr[0].sr_rise1_r_reg[0][0]\: unisim.vcomponents.FDRE
     port map (
      C => wrcal_pat_resume_reg_0,
      CE => '1',
      D => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg_n_0_[0]\,
      Q => \gen_sr_div4.gen_sr[0].sr_rise1_r_reg[0]_247\,
      R => '0'
    );
\gen_sr_div4.gen_sr[0].sr_rise2_r_reg[0][0]\: unisim.vcomponents.FDRE
     port map (
      C => wrcal_pat_resume_reg_0,
      CE => '1',
      D => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise2_r_reg_n_0_[0]\,
      Q => \gen_sr_div4.gen_sr[0].sr_rise2_r_reg[0]_271\,
      R => '0'
    );
\gen_sr_div4.gen_sr[0].sr_rise3_r_reg[0][0]\: unisim.vcomponents.FDRE
     port map (
      C => wrcal_pat_resume_reg_0,
      CE => '1',
      D => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg_n_0_[0]\,
      Q => \gen_sr_div4.gen_sr[0].sr_rise3_r_reg[0]_287\,
      R => '0'
    );
\gen_sr_div4.gen_sr[1].sr_fall0_r_reg[1][0]\: unisim.vcomponents.FDRE
     port map (
      C => wrcal_pat_resume_reg_0,
      CE => '1',
      D => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg_n_0_[1]\,
      Q => \gen_sr_div4.gen_sr[1].sr_fall0_r_reg[1]_264\,
      R => '0'
    );
\gen_sr_div4.gen_sr[1].sr_fall1_r_reg[1][0]\: unisim.vcomponents.FDRE
     port map (
      C => wrcal_pat_resume_reg_0,
      CE => '1',
      D => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg_n_0_[1]\,
      Q => \gen_sr_div4.gen_sr[1].sr_fall1_r_reg[1]_304\,
      R => '0'
    );
\gen_sr_div4.gen_sr[1].sr_fall2_r_reg[1][0]\: unisim.vcomponents.FDRE
     port map (
      C => wrcal_pat_resume_reg_0,
      CE => '1',
      D => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg_n_0_[1]\,
      Q => \gen_sr_div4.gen_sr[1].sr_fall2_r_reg[1]_280\,
      R => '0'
    );
\gen_sr_div4.gen_sr[1].sr_fall3_r_reg[1][0]\: unisim.vcomponents.FDRE
     port map (
      C => wrcal_pat_resume_reg_0,
      CE => '1',
      D => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg_n_0_[1]\,
      Q => \gen_sr_div4.gen_sr[1].sr_fall3_r_reg[1]_256\,
      R => '0'
    );
\gen_sr_div4.gen_sr[1].sr_rise0_r_reg[1][0]\: unisim.vcomponents.FDRE
     port map (
      C => wrcal_pat_resume_reg_0,
      CE => '1',
      D => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg_n_0_[1]\,
      Q => \gen_sr_div4.gen_sr[1].sr_rise0_r_reg[1]_296\,
      R => '0'
    );
\gen_sr_div4.gen_sr[1].sr_rise1_r_reg[1][0]\: unisim.vcomponents.FDRE
     port map (
      C => wrcal_pat_resume_reg_0,
      CE => '1',
      D => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg_n_0_[1]\,
      Q => \gen_sr_div4.gen_sr[1].sr_rise1_r_reg[1]_248\,
      R => '0'
    );
\gen_sr_div4.gen_sr[1].sr_rise2_r_reg[1][0]\: unisim.vcomponents.FDRE
     port map (
      C => wrcal_pat_resume_reg_0,
      CE => '1',
      D => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg_n_0_[1]\,
      Q => \gen_sr_div4.gen_sr[1].sr_rise2_r_reg[1]_272\,
      R => '0'
    );
\gen_sr_div4.gen_sr[1].sr_rise3_r_reg[1][0]\: unisim.vcomponents.FDRE
     port map (
      C => wrcal_pat_resume_reg_0,
      CE => '1',
      D => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg_n_0_[1]\,
      Q => \gen_sr_div4.gen_sr[1].sr_rise3_r_reg[1]_288\,
      R => '0'
    );
\gen_sr_div4.gen_sr[2].sr_fall0_r_reg[2][0]\: unisim.vcomponents.FDRE
     port map (
      C => wrcal_pat_resume_reg_0,
      CE => '1',
      D => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg_n_0_[2]\,
      Q => \gen_sr_div4.gen_sr[2].sr_fall0_r_reg[2]_265\,
      R => '0'
    );
\gen_sr_div4.gen_sr[2].sr_fall1_r_reg[2][0]\: unisim.vcomponents.FDRE
     port map (
      C => wrcal_pat_resume_reg_0,
      CE => '1',
      D => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg_n_0_[2]\,
      Q => \gen_sr_div4.gen_sr[2].sr_fall1_r_reg[2]_305\,
      R => '0'
    );
\gen_sr_div4.gen_sr[2].sr_fall2_r_reg[2][0]\: unisim.vcomponents.FDRE
     port map (
      C => wrcal_pat_resume_reg_0,
      CE => '1',
      D => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg_n_0_[2]\,
      Q => \gen_sr_div4.gen_sr[2].sr_fall2_r_reg[2]_281\,
      R => '0'
    );
\gen_sr_div4.gen_sr[2].sr_fall3_r_reg[2][0]\: unisim.vcomponents.FDRE
     port map (
      C => wrcal_pat_resume_reg_0,
      CE => '1',
      D => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg_n_0_[2]\,
      Q => \gen_sr_div4.gen_sr[2].sr_fall3_r_reg[2]_257\,
      R => '0'
    );
\gen_sr_div4.gen_sr[2].sr_rise0_r_reg[2][0]\: unisim.vcomponents.FDRE
     port map (
      C => wrcal_pat_resume_reg_0,
      CE => '1',
      D => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg_n_0_[2]\,
      Q => \gen_sr_div4.gen_sr[2].sr_rise0_r_reg[2]_297\,
      R => '0'
    );
\gen_sr_div4.gen_sr[2].sr_rise1_r_reg[2][0]\: unisim.vcomponents.FDRE
     port map (
      C => wrcal_pat_resume_reg_0,
      CE => '1',
      D => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg_n_0_[2]\,
      Q => \gen_sr_div4.gen_sr[2].sr_rise1_r_reg[2]_249\,
      R => '0'
    );
\gen_sr_div4.gen_sr[2].sr_rise2_r_reg[2][0]\: unisim.vcomponents.FDRE
     port map (
      C => wrcal_pat_resume_reg_0,
      CE => '1',
      D => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg_n_0_[2]\,
      Q => \gen_sr_div4.gen_sr[2].sr_rise2_r_reg[2]_273\,
      R => '0'
    );
\gen_sr_div4.gen_sr[2].sr_rise3_r_reg[2][0]\: unisim.vcomponents.FDRE
     port map (
      C => wrcal_pat_resume_reg_0,
      CE => '1',
      D => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg_n_0_[2]\,
      Q => \gen_sr_div4.gen_sr[2].sr_rise3_r_reg[2]_289\,
      R => '0'
    );
\gen_sr_div4.gen_sr[3].sr_fall0_r_reg[3][0]\: unisim.vcomponents.FDRE
     port map (
      C => wrcal_pat_resume_reg_0,
      CE => '1',
      D => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg_n_0_[3]\,
      Q => \gen_sr_div4.gen_sr[3].sr_fall0_r_reg[3]_266\,
      R => '0'
    );
\gen_sr_div4.gen_sr[3].sr_fall1_r_reg[3][0]\: unisim.vcomponents.FDRE
     port map (
      C => wrcal_pat_resume_reg_0,
      CE => '1',
      D => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg_n_0_[3]\,
      Q => \gen_sr_div4.gen_sr[3].sr_fall1_r_reg[3]_306\,
      R => '0'
    );
\gen_sr_div4.gen_sr[3].sr_fall2_r_reg[3][0]\: unisim.vcomponents.FDRE
     port map (
      C => wrcal_pat_resume_reg_0,
      CE => '1',
      D => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg_n_0_[3]\,
      Q => \gen_sr_div4.gen_sr[3].sr_fall2_r_reg[3]_282\,
      R => '0'
    );
\gen_sr_div4.gen_sr[3].sr_fall3_r_reg[3][0]\: unisim.vcomponents.FDRE
     port map (
      C => wrcal_pat_resume_reg_0,
      CE => '1',
      D => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg_n_0_[3]\,
      Q => \gen_sr_div4.gen_sr[3].sr_fall3_r_reg[3]_258\,
      R => '0'
    );
\gen_sr_div4.gen_sr[3].sr_rise0_r_reg[3][0]\: unisim.vcomponents.FDRE
     port map (
      C => wrcal_pat_resume_reg_0,
      CE => '1',
      D => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg_n_0_[3]\,
      Q => \gen_sr_div4.gen_sr[3].sr_rise0_r_reg[3]_298\,
      R => '0'
    );
\gen_sr_div4.gen_sr[3].sr_rise1_r_reg[3][0]\: unisim.vcomponents.FDRE
     port map (
      C => wrcal_pat_resume_reg_0,
      CE => '1',
      D => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg_n_0_[3]\,
      Q => \gen_sr_div4.gen_sr[3].sr_rise1_r_reg[3]_250\,
      R => '0'
    );
\gen_sr_div4.gen_sr[3].sr_rise2_r_reg[3][0]\: unisim.vcomponents.FDRE
     port map (
      C => wrcal_pat_resume_reg_0,
      CE => '1',
      D => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg_n_0_[3]\,
      Q => \gen_sr_div4.gen_sr[3].sr_rise2_r_reg[3]_274\,
      R => '0'
    );
\gen_sr_div4.gen_sr[3].sr_rise3_r_reg[3][0]\: unisim.vcomponents.FDRE
     port map (
      C => wrcal_pat_resume_reg_0,
      CE => '1',
      D => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise3_r_reg_n_0_[3]\,
      Q => \gen_sr_div4.gen_sr[3].sr_rise3_r_reg[3]_290\,
      R => '0'
    );
\gen_sr_div4.gen_sr[4].sr_fall0_r_reg[4][0]\: unisim.vcomponents.FDRE
     port map (
      C => wrcal_pat_resume_reg_0,
      CE => '1',
      D => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg_n_0_[4]\,
      Q => \gen_sr_div4.gen_sr[4].sr_fall0_r_reg[4]_267\,
      R => '0'
    );
\gen_sr_div4.gen_sr[4].sr_fall1_r_reg[4][0]\: unisim.vcomponents.FDRE
     port map (
      C => wrcal_pat_resume_reg_0,
      CE => '1',
      D => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg_n_0_[4]\,
      Q => \gen_sr_div4.gen_sr[4].sr_fall1_r_reg[4]_307\,
      R => '0'
    );
\gen_sr_div4.gen_sr[4].sr_fall2_r_reg[4][0]\: unisim.vcomponents.FDRE
     port map (
      C => wrcal_pat_resume_reg_0,
      CE => '1',
      D => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg_n_0_[4]\,
      Q => \gen_sr_div4.gen_sr[4].sr_fall2_r_reg[4]_283\,
      R => '0'
    );
\gen_sr_div4.gen_sr[4].sr_fall3_r_reg[4][0]\: unisim.vcomponents.FDRE
     port map (
      C => wrcal_pat_resume_reg_0,
      CE => '1',
      D => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg_n_0_[4]\,
      Q => \gen_sr_div4.gen_sr[4].sr_fall3_r_reg[4]_259\,
      R => '0'
    );
\gen_sr_div4.gen_sr[4].sr_rise0_r_reg[4][0]\: unisim.vcomponents.FDRE
     port map (
      C => wrcal_pat_resume_reg_0,
      CE => '1',
      D => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg_n_0_[4]\,
      Q => \gen_sr_div4.gen_sr[4].sr_rise0_r_reg[4]_299\,
      R => '0'
    );
\gen_sr_div4.gen_sr[4].sr_rise1_r_reg[4][0]\: unisim.vcomponents.FDRE
     port map (
      C => wrcal_pat_resume_reg_0,
      CE => '1',
      D => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg_n_0_[4]\,
      Q => \gen_sr_div4.gen_sr[4].sr_rise1_r_reg[4]_251\,
      R => '0'
    );
\gen_sr_div4.gen_sr[4].sr_rise2_r_reg[4][0]\: unisim.vcomponents.FDRE
     port map (
      C => wrcal_pat_resume_reg_0,
      CE => '1',
      D => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise2_r_reg_n_0_[4]\,
      Q => \gen_sr_div4.gen_sr[4].sr_rise2_r_reg[4]_275\,
      R => '0'
    );
\gen_sr_div4.gen_sr[4].sr_rise3_r_reg[4][0]\: unisim.vcomponents.FDRE
     port map (
      C => wrcal_pat_resume_reg_0,
      CE => '1',
      D => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg_n_0_[4]\,
      Q => \gen_sr_div4.gen_sr[4].sr_rise3_r_reg[4]_291\,
      R => '0'
    );
\gen_sr_div4.gen_sr[5].sr_fall0_r_reg[5][0]\: unisim.vcomponents.FDRE
     port map (
      C => wrcal_pat_resume_reg_0,
      CE => '1',
      D => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg_n_0_[5]\,
      Q => \gen_sr_div4.gen_sr[5].sr_fall0_r_reg[5]_268\,
      R => '0'
    );
\gen_sr_div4.gen_sr[5].sr_fall1_r_reg[5][0]\: unisim.vcomponents.FDRE
     port map (
      C => wrcal_pat_resume_reg_0,
      CE => '1',
      D => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg_n_0_[5]\,
      Q => \gen_sr_div4.gen_sr[5].sr_fall1_r_reg[5]_308\,
      R => '0'
    );
\gen_sr_div4.gen_sr[5].sr_fall2_r_reg[5][0]\: unisim.vcomponents.FDRE
     port map (
      C => wrcal_pat_resume_reg_0,
      CE => '1',
      D => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg_n_0_[5]\,
      Q => \gen_sr_div4.gen_sr[5].sr_fall2_r_reg[5]_284\,
      R => '0'
    );
\gen_sr_div4.gen_sr[5].sr_fall3_r_reg[5][0]\: unisim.vcomponents.FDRE
     port map (
      C => wrcal_pat_resume_reg_0,
      CE => '1',
      D => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg_n_0_[5]\,
      Q => \gen_sr_div4.gen_sr[5].sr_fall3_r_reg[5]_260\,
      R => '0'
    );
\gen_sr_div4.gen_sr[5].sr_rise0_r_reg[5][0]\: unisim.vcomponents.FDRE
     port map (
      C => wrcal_pat_resume_reg_0,
      CE => '1',
      D => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg_n_0_[5]\,
      Q => \gen_sr_div4.gen_sr[5].sr_rise0_r_reg[5]_300\,
      R => '0'
    );
\gen_sr_div4.gen_sr[5].sr_rise1_r_reg[5][0]\: unisim.vcomponents.FDRE
     port map (
      C => wrcal_pat_resume_reg_0,
      CE => '1',
      D => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg_n_0_[5]\,
      Q => \gen_sr_div4.gen_sr[5].sr_rise1_r_reg[5]_252\,
      R => '0'
    );
\gen_sr_div4.gen_sr[5].sr_rise2_r_reg[5][0]\: unisim.vcomponents.FDRE
     port map (
      C => wrcal_pat_resume_reg_0,
      CE => '1',
      D => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg_n_0_[5]\,
      Q => \gen_sr_div4.gen_sr[5].sr_rise2_r_reg[5]_276\,
      R => '0'
    );
\gen_sr_div4.gen_sr[5].sr_rise3_r_reg[5][0]\: unisim.vcomponents.FDRE
     port map (
      C => wrcal_pat_resume_reg_0,
      CE => '1',
      D => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg_n_0_[5]\,
      Q => \gen_sr_div4.gen_sr[5].sr_rise3_r_reg[5]_292\,
      R => '0'
    );
\gen_sr_div4.gen_sr[6].sr_fall0_r_reg[6][0]\: unisim.vcomponents.FDRE
     port map (
      C => wrcal_pat_resume_reg_0,
      CE => '1',
      D => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg_n_0_[6]\,
      Q => \gen_sr_div4.gen_sr[6].sr_fall0_r_reg[6]_269\,
      R => '0'
    );
\gen_sr_div4.gen_sr[6].sr_fall1_r_reg[6][0]\: unisim.vcomponents.FDRE
     port map (
      C => wrcal_pat_resume_reg_0,
      CE => '1',
      D => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg_n_0_[6]\,
      Q => \gen_sr_div4.gen_sr[6].sr_fall1_r_reg[6]_309\,
      R => '0'
    );
\gen_sr_div4.gen_sr[6].sr_fall2_r_reg[6][0]\: unisim.vcomponents.FDRE
     port map (
      C => wrcal_pat_resume_reg_0,
      CE => '1',
      D => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg_n_0_[6]\,
      Q => \gen_sr_div4.gen_sr[6].sr_fall2_r_reg[6]_285\,
      R => '0'
    );
\gen_sr_div4.gen_sr[6].sr_fall3_r_reg[6][0]\: unisim.vcomponents.FDRE
     port map (
      C => wrcal_pat_resume_reg_0,
      CE => '1',
      D => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg_n_0_[6]\,
      Q => \gen_sr_div4.gen_sr[6].sr_fall3_r_reg[6]_261\,
      R => '0'
    );
\gen_sr_div4.gen_sr[6].sr_rise0_r_reg[6][0]\: unisim.vcomponents.FDRE
     port map (
      C => wrcal_pat_resume_reg_0,
      CE => '1',
      D => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg_n_0_[6]\,
      Q => \gen_sr_div4.gen_sr[6].sr_rise0_r_reg[6]_301\,
      R => '0'
    );
\gen_sr_div4.gen_sr[6].sr_rise1_r_reg[6][0]\: unisim.vcomponents.FDRE
     port map (
      C => wrcal_pat_resume_reg_0,
      CE => '1',
      D => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg_n_0_[6]\,
      Q => \gen_sr_div4.gen_sr[6].sr_rise1_r_reg[6]_253\,
      R => '0'
    );
\gen_sr_div4.gen_sr[6].sr_rise2_r_reg[6][0]\: unisim.vcomponents.FDRE
     port map (
      C => wrcal_pat_resume_reg_0,
      CE => '1',
      D => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg_n_0_[6]\,
      Q => \gen_sr_div4.gen_sr[6].sr_rise2_r_reg[6]_277\,
      R => '0'
    );
\gen_sr_div4.gen_sr[6].sr_rise3_r_reg[6][0]\: unisim.vcomponents.FDRE
     port map (
      C => wrcal_pat_resume_reg_0,
      CE => '1',
      D => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg_n_0_[6]\,
      Q => \gen_sr_div4.gen_sr[6].sr_rise3_r_reg[6]_293\,
      R => '0'
    );
\gen_sr_div4.gen_sr[7].sr_fall0_r_reg[7][0]\: unisim.vcomponents.FDRE
     port map (
      C => wrcal_pat_resume_reg_0,
      CE => '1',
      D => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg_n_0_[7]\,
      Q => \gen_sr_div4.gen_sr[7].sr_fall0_r_reg[7]_270\,
      R => '0'
    );
\gen_sr_div4.gen_sr[7].sr_fall1_r_reg[7][0]\: unisim.vcomponents.FDRE
     port map (
      C => wrcal_pat_resume_reg_0,
      CE => '1',
      D => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg_n_0_[7]\,
      Q => \gen_sr_div4.gen_sr[7].sr_fall1_r_reg[7]_310\,
      R => '0'
    );
\gen_sr_div4.gen_sr[7].sr_fall2_r_reg[7][0]\: unisim.vcomponents.FDRE
     port map (
      C => wrcal_pat_resume_reg_0,
      CE => '1',
      D => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg_n_0_[7]\,
      Q => \gen_sr_div4.gen_sr[7].sr_fall2_r_reg[7]_286\,
      R => '0'
    );
\gen_sr_div4.gen_sr[7].sr_fall3_r_reg[7][0]\: unisim.vcomponents.FDRE
     port map (
      C => wrcal_pat_resume_reg_0,
      CE => '1',
      D => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg_n_0_[7]\,
      Q => \gen_sr_div4.gen_sr[7].sr_fall3_r_reg[7]_262\,
      R => '0'
    );
\gen_sr_div4.gen_sr[7].sr_rise0_r_reg[7][0]\: unisim.vcomponents.FDRE
     port map (
      C => wrcal_pat_resume_reg_0,
      CE => '1',
      D => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg_n_0_[7]\,
      Q => \gen_sr_div4.gen_sr[7].sr_rise0_r_reg[7]_302\,
      R => '0'
    );
\gen_sr_div4.gen_sr[7].sr_rise1_r_reg[7][0]\: unisim.vcomponents.FDRE
     port map (
      C => wrcal_pat_resume_reg_0,
      CE => '1',
      D => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg_n_0_[7]\,
      Q => \gen_sr_div4.gen_sr[7].sr_rise1_r_reg[7]_254\,
      R => '0'
    );
\gen_sr_div4.gen_sr[7].sr_rise2_r_reg[7][0]\: unisim.vcomponents.FDRE
     port map (
      C => wrcal_pat_resume_reg_0,
      CE => '1',
      D => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg_n_0_[7]\,
      Q => \gen_sr_div4.gen_sr[7].sr_rise2_r_reg[7]_278\,
      R => '0'
    );
\gen_sr_div4.gen_sr[7].sr_rise3_r_reg[7][0]\: unisim.vcomponents.FDRE
     port map (
      C => wrcal_pat_resume_reg_0,
      CE => '1',
      D => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise3_r_reg_n_0_[7]\,
      Q => \gen_sr_div4.gen_sr[7].sr_rise3_r_reg[7]_294\,
      R => '0'
    );
idelay_ld_done_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFCFF00000080"
    )
        port map (
      I0 => idelay_ld_done_i_2_n_0,
      I1 => \cal2_state_r_reg_n_0_[0]\,
      I2 => \cal2_state_r_reg_n_0_[2]\,
      I3 => \cal2_state_r_reg_n_0_[1]\,
      I4 => \cal2_state_r_reg_n_0_[3]\,
      I5 => idelay_ld_done_reg_n_0,
      O => idelay_ld_done_i_1_n_0
    );
idelay_ld_done_i_2: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0002"
    )
        port map (
      I0 => tap_inc_wait_cnt_reg(2),
      I1 => tap_inc_wait_cnt_reg(0),
      I2 => tap_inc_wait_cnt_reg(1),
      I3 => tap_inc_wait_cnt_reg(3),
      O => idelay_ld_done_i_2_n_0
    );
idelay_ld_done_reg: unisim.vcomponents.FDRE
     port map (
      C => wrcal_pat_resume_reg_0,
      CE => '1',
      D => idelay_ld_done_i_1_n_0,
      Q => idelay_ld_done_reg_n_0,
      R => cal2_done_r_reg_0(0)
    );
idelay_ld_i_1: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F20"
    )
        port map (
      I0 => \gen_pat_match_div4.pat_data_match_valid_r_reg_n_0\,
      I1 => \cal2_state_r_reg_n_0_[2]\,
      I2 => idelay_ld_i_2_n_0,
      I3 => idelay_ld,
      O => idelay_ld_i_1_n_0
    );
idelay_ld_i_2: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000540400000000"
    )
        port map (
      I0 => \cal2_state_r_reg_n_0_[3]\,
      I1 => \cal2_state_r[2]_i_2_n_0\,
      I2 => \cal2_state_r_reg_n_0_[2]\,
      I3 => idelay_ld_done_i_2_n_0,
      I4 => \cal2_state_r_reg_n_0_[1]\,
      I5 => \cal2_state_r_reg_n_0_[0]\,
      O => idelay_ld_i_2_n_0
    );
idelay_ld_reg: unisim.vcomponents.FDRE
     port map (
      C => wrcal_pat_resume_reg_0,
      CE => '1',
      D => idelay_ld_i_1_n_0,
      Q => idelay_ld,
      R => cal2_if_reset_reg_0
    );
\idelay_tap_cnt_r[0][0][4]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFF888888F8"
    )
        port map (
      I0 => \idelay_tap_cnt_r_reg[0][4][4]_0\,
      I1 => \idelay_tap_cnt_r_reg[0][0][4]\,
      I2 => \idelay_tap_cnt_r[0][0][4]_i_5_n_0\,
      I3 => \^q\(0),
      I4 => \^q\(1),
      I5 => \idelay_tap_cnt_r_reg[0][0][4]_0\,
      O => \po_stg2_wrcal_cnt_reg[0]_4\(0)
    );
\idelay_tap_cnt_r[0][0][4]_i_5\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0010"
    )
        port map (
      I0 => \^q\(2),
      I1 => \^q\(3),
      I2 => idelay_ld,
      I3 => idelay_ce_int,
      O => \idelay_tap_cnt_r[0][0][4]_i_5_n_0\
    );
\idelay_tap_cnt_r[0][1][4]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFF202020"
    )
        port map (
      I0 => \^q\(0),
      I1 => \^q\(1),
      I2 => \idelay_tap_cnt_r[0][0][4]_i_5_n_0\,
      I3 => \idelay_tap_cnt_r_reg[0][1][4]\,
      I4 => \idelay_tap_cnt_r_reg[0][5][4]\,
      I5 => \idelay_tap_cnt_r_reg[0][0][4]_0\,
      O => \po_stg2_wrcal_cnt_reg[0]_7\(0)
    );
\idelay_tap_cnt_r[0][2][4]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFAEAA"
    )
        port map (
      I0 => \idelay_tap_cnt_r_reg[0][2][4]\,
      I1 => \idelay_tap_cnt_r[0][0][4]_i_5_n_0\,
      I2 => \^q\(0),
      I3 => \^q\(1),
      I4 => \idelay_tap_cnt_r_reg[0][0][4]_0\,
      O => \po_stg2_wrcal_cnt_reg[0]_8\(0)
    );
\idelay_tap_cnt_r[0][3][4]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFF8080FF80"
    )
        port map (
      I0 => \^q\(1),
      I1 => \^q\(0),
      I2 => \idelay_tap_cnt_r[0][0][4]_i_5_n_0\,
      I3 => \idelay_tap_cnt_r_reg[0][1][4]\,
      I4 => \idelay_tap_cnt_r_reg[0][7][4]\,
      I5 => \idelay_tap_cnt_r_reg[0][0][4]_0\,
      O => \po_stg2_wrcal_cnt_reg[1]_2\(0)
    );
\idelay_tap_cnt_r[0][4][4]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFF4444444F"
    )
        port map (
      I0 => \idelay_tap_cnt_r_reg[0][4][4]\,
      I1 => \idelay_tap_cnt_r_reg[0][4][4]_0\,
      I2 => \^q\(0),
      I3 => \^q\(1),
      I4 => \idelay_tap_cnt_r[0][4][4]_i_3_n_0\,
      I5 => \idelay_tap_cnt_r_reg[0][4][4]_1\,
      O => \po_stg2_wrcal_cnt_reg[0]_3\(0)
    );
\idelay_tap_cnt_r[0][4][4]_i_3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FBFF"
    )
        port map (
      I0 => \^q\(3),
      I1 => idelay_ld,
      I2 => idelay_ce_int,
      I3 => \^q\(2),
      O => \idelay_tap_cnt_r[0][4][4]_i_3_n_0\
    );
\idelay_tap_cnt_r[0][5][4]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFF0404FF04"
    )
        port map (
      I0 => \idelay_tap_cnt_r[0][4][4]_i_3_n_0\,
      I1 => \^q\(0),
      I2 => \^q\(1),
      I3 => \idelay_tap_cnt_r_reg[0][5][4]\,
      I4 => \idelay_tap_cnt_r_reg[0][5][4]_0\,
      I5 => \idelay_tap_cnt_r_reg[0][0][4]_0\,
      O => \po_stg2_wrcal_cnt_reg[0]_5\(0)
    );
\idelay_tap_cnt_r[0][6][4]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFAABA"
    )
        port map (
      I0 => \idelay_tap_cnt_r_reg[0][6][4]\,
      I1 => \^q\(0),
      I2 => \^q\(1),
      I3 => \idelay_tap_cnt_r[0][4][4]_i_3_n_0\,
      I4 => \idelay_tap_cnt_r_reg[0][0][4]_0\,
      O => \po_stg2_wrcal_cnt_reg[0]_6\(0)
    );
\idelay_tap_cnt_r[0][7][4]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFF404040FF"
    )
        port map (
      I0 => \idelay_tap_cnt_r[0][4][4]_i_3_n_0\,
      I1 => \^q\(1),
      I2 => \^q\(0),
      I3 => \idelay_tap_cnt_r_reg[0][7][4]\,
      I4 => \idelay_tap_cnt_r_reg[0][5][4]_0\,
      I5 => \idelay_tap_cnt_r_reg[0][0][4]_0\,
      O => \po_stg2_wrcal_cnt_reg[1]_1\(0)
    );
\init_state_r[2]_i_35\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"7FFFFFFF"
    )
        port map (
      I0 => \^wrcal_done_reg_0\,
      I1 => \init_state_r[3]_i_13\,
      I2 => wrlvl_done_r1,
      I3 => \init_state_r[2]_i_14\,
      I4 => \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[508]\,
      O => wrcal_done_reg_2
    );
\init_state_r[3]_i_23\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"F7"
    )
        port map (
      I0 => \^wrcal_done_reg_0\,
      I1 => \init_state_r[3]_i_13\,
      I2 => \init_state_r[3]_i_13_0\,
      O => wrcal_done_reg_3
    );
\init_state_r[4]_i_28\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"FE"
    )
        port map (
      I0 => \^wrlvl_byte_redo\,
      I1 => \init_state_r[4]_i_27\,
      I2 => \^wrcal_done_reg_0\,
      O => wrlvl_byte_redo_reg_0
    );
\input_[1].iserdes_dq_.idelay_dq.idelaye2_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFF40404050"
    )
        port map (
      I0 => \input_[9].iserdes_dq_.idelay_dq.idelaye2\(0),
      I1 => calib_in_common,
      I2 => idelay_ld,
      I3 => \input_[9].iserdes_dq_.idelay_dq.idelaye2_0\,
      I4 => \input_[9].iserdes_dq_.idelay_dq.idelaye2_1\,
      I5 => idelay_ld_rst,
      O => LD0
    );
\input_[1].iserdes_dq_.idelay_dq.idelaye2_i_2__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFF40404050"
    )
        port map (
      I0 => \input_[9].iserdes_dq_.idelay_dq.idelaye2\(1),
      I1 => calib_in_common,
      I2 => idelay_ld,
      I3 => \input_[9].iserdes_dq_.idelay_dq.idelaye2_0\,
      I4 => \input_[9].iserdes_dq_.idelay_dq.idelaye2_1\,
      I5 => idelay_ld_rst_10,
      O => LD0_3
    );
\input_[2].iserdes_dq_.idelay_dq.idelaye2_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFF44005400"
    )
        port map (
      I0 => \input_[9].iserdes_dq_.idelay_dq.idelaye2\(0),
      I1 => calib_in_common,
      I2 => \input_[9].iserdes_dq_.idelay_dq.idelaye2_0\,
      I3 => idelay_ld,
      I4 => \input_[9].iserdes_dq_.idelay_dq.idelaye2_1\,
      I5 => idelay_ld_rst_7,
      O => LD0_0
    );
\input_[2].iserdes_dq_.idelay_dq.idelaye2_i_2__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFF45004400"
    )
        port map (
      I0 => \input_[9].iserdes_dq_.idelay_dq.idelaye2\(0),
      I1 => calib_in_common,
      I2 => \input_[9].iserdes_dq_.idelay_dq.idelaye2_0\,
      I3 => idelay_ld,
      I4 => \input_[9].iserdes_dq_.idelay_dq.idelaye2_1\,
      I5 => idelay_ld_rst_8,
      O => LD0_1
    );
\input_[2].iserdes_dq_.idelay_dq.idelaye2_i_2__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFF54440000"
    )
        port map (
      I0 => \input_[9].iserdes_dq_.idelay_dq.idelaye2\(0),
      I1 => calib_in_common,
      I2 => \input_[9].iserdes_dq_.idelay_dq.idelaye2_1\,
      I3 => \input_[9].iserdes_dq_.idelay_dq.idelaye2_0\,
      I4 => idelay_ld,
      I5 => idelay_ld_rst_9,
      O => LD0_2
    );
\input_[2].iserdes_dq_.idelay_dq.idelaye2_i_2__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFF44005400"
    )
        port map (
      I0 => \input_[9].iserdes_dq_.idelay_dq.idelaye2\(1),
      I1 => calib_in_common,
      I2 => \input_[9].iserdes_dq_.idelay_dq.idelaye2_0\,
      I3 => idelay_ld,
      I4 => \input_[9].iserdes_dq_.idelay_dq.idelaye2_1\,
      I5 => idelay_ld_rst_11,
      O => LD0_4
    );
\input_[2].iserdes_dq_.idelay_dq.idelaye2_i_2__3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFF45004400"
    )
        port map (
      I0 => \input_[9].iserdes_dq_.idelay_dq.idelaye2\(1),
      I1 => calib_in_common,
      I2 => \input_[9].iserdes_dq_.idelay_dq.idelaye2_0\,
      I3 => idelay_ld,
      I4 => \input_[9].iserdes_dq_.idelay_dq.idelaye2_1\,
      I5 => idelay_ld_rst_12,
      O => LD0_5
    );
\input_[2].iserdes_dq_.idelay_dq.idelaye2_i_2__4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFF54440000"
    )
        port map (
      I0 => \input_[9].iserdes_dq_.idelay_dq.idelaye2\(1),
      I1 => calib_in_common,
      I2 => \input_[9].iserdes_dq_.idelay_dq.idelaye2_1\,
      I3 => \input_[9].iserdes_dq_.idelay_dq.idelaye2_0\,
      I4 => idelay_ld,
      I5 => idelay_ld_rst_13,
      O => LD0_6
    );
\not_empty_wait_cnt[0]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \not_empty_wait_cnt_reg_n_0_[0]\,
      O => p_0_in(0)
    );
\not_empty_wait_cnt[1]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \not_empty_wait_cnt_reg_n_0_[0]\,
      I1 => \not_empty_wait_cnt_reg_n_0_[1]\,
      O => p_0_in(1)
    );
\not_empty_wait_cnt[2]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"78"
    )
        port map (
      I0 => \not_empty_wait_cnt_reg_n_0_[1]\,
      I1 => \not_empty_wait_cnt_reg_n_0_[0]\,
      I2 => \not_empty_wait_cnt_reg_n_0_[2]\,
      O => p_0_in(2)
    );
\not_empty_wait_cnt[3]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6AAA"
    )
        port map (
      I0 => \not_empty_wait_cnt_reg_n_0_[3]\,
      I1 => \not_empty_wait_cnt_reg_n_0_[1]\,
      I2 => \not_empty_wait_cnt_reg_n_0_[2]\,
      I3 => \not_empty_wait_cnt_reg_n_0_[0]\,
      O => p_0_in(3)
    );
\not_empty_wait_cnt[4]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFEFFFFFFFFFFFF"
    )
        port map (
      I0 => \not_empty_wait_cnt_reg[4]_0\,
      I1 => \cal2_state_r_reg_n_0_[3]\,
      I2 => \cal2_state_r_reg_n_0_[2]\,
      I3 => \cal2_state_r_reg_n_0_[1]\,
      I4 => \cal2_state_r_reg_n_0_[0]\,
      I5 => wrcal_rd_wait,
      O => \not_empty_wait_cnt[4]_i_1_n_0\
    );
\not_empty_wait_cnt[4]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"6AAAAAAA"
    )
        port map (
      I0 => \not_empty_wait_cnt_reg_n_0_[4]\,
      I1 => \not_empty_wait_cnt_reg_n_0_[0]\,
      I2 => \not_empty_wait_cnt_reg_n_0_[2]\,
      I3 => \not_empty_wait_cnt_reg_n_0_[1]\,
      I4 => \not_empty_wait_cnt_reg_n_0_[3]\,
      O => p_0_in(4)
    );
\not_empty_wait_cnt_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => wrcal_pat_resume_reg_0,
      CE => '1',
      D => p_0_in(0),
      Q => \not_empty_wait_cnt_reg_n_0_[0]\,
      R => \not_empty_wait_cnt[4]_i_1_n_0\
    );
\not_empty_wait_cnt_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => wrcal_pat_resume_reg_0,
      CE => '1',
      D => p_0_in(1),
      Q => \not_empty_wait_cnt_reg_n_0_[1]\,
      R => \not_empty_wait_cnt[4]_i_1_n_0\
    );
\not_empty_wait_cnt_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => wrcal_pat_resume_reg_0,
      CE => '1',
      D => p_0_in(2),
      Q => \not_empty_wait_cnt_reg_n_0_[2]\,
      R => \not_empty_wait_cnt[4]_i_1_n_0\
    );
\not_empty_wait_cnt_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => wrcal_pat_resume_reg_0,
      CE => '1',
      D => p_0_in(3),
      Q => \not_empty_wait_cnt_reg_n_0_[3]\,
      R => \not_empty_wait_cnt[4]_i_1_n_0\
    );
\not_empty_wait_cnt_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => wrcal_pat_resume_reg_0,
      CE => '1',
      D => p_0_in(4),
      Q => \not_empty_wait_cnt_reg_n_0_[4]\,
      R => \not_empty_wait_cnt[4]_i_1_n_0\
    );
\po_stg2_wrcal_cnt_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => wrcal_pat_resume_reg_0,
      CE => '1',
      D => \wrcal_dqs_cnt_r_reg_n_0_[0]\,
      Q => \^q\(0),
      R => '0'
    );
\po_stg2_wrcal_cnt_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => wrcal_pat_resume_reg_0,
      CE => '1',
      D => \wrcal_dqs_cnt_r_reg_n_0_[1]\,
      Q => \^q\(1),
      R => '0'
    );
\po_stg2_wrcal_cnt_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => wrcal_pat_resume_reg_0,
      CE => '1',
      D => \wrcal_dqs_cnt_r_reg_n_0_[2]\,
      Q => \^q\(2),
      R => '0'
    );
\po_stg2_wrcal_cnt_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => wrcal_pat_resume_reg_0,
      CE => '1',
      D => wrcal_dqs_cnt_r(3),
      Q => \^q\(3),
      R => '0'
    );
rd_active_r1_reg: unisim.vcomponents.FDRE
     port map (
      C => wrcal_pat_resume_reg_0,
      CE => '1',
      D => \^e\(0),
      Q => rd_active_r1,
      R => '0'
    );
rd_active_r3_reg_srl2: unisim.vcomponents.SRL16E
     port map (
      A0 => '1',
      A1 => '0',
      A2 => '0',
      A3 => '0',
      CE => '1',
      CLK => wrcal_pat_resume_reg_0,
      D => rd_active_r1,
      Q => rd_active_r3_reg_srl2_n_0
    );
rd_active_r_reg: unisim.vcomponents.FDRE
     port map (
      C => wrcal_pat_resume_reg_0,
      CE => '1',
      D => phy_rddata_en,
      Q => \^e\(0),
      R => '0'
    );
\tap_inc_wait_cnt[0]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => tap_inc_wait_cnt_reg(0),
      O => \p_0_in__0\(0)
    );
\tap_inc_wait_cnt[1]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => tap_inc_wait_cnt_reg(1),
      I1 => tap_inc_wait_cnt_reg(0),
      O => \p_0_in__0\(1)
    );
\tap_inc_wait_cnt[2]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"6A"
    )
        port map (
      I0 => tap_inc_wait_cnt_reg(2),
      I1 => tap_inc_wait_cnt_reg(0),
      I2 => tap_inc_wait_cnt_reg(1),
      O => \p_0_in__0\(2)
    );
\tap_inc_wait_cnt[3]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFAFEF"
    )
        port map (
      I0 => \cal2_state_r_reg_n_0_[3]\,
      I1 => \cal2_state_r_reg_n_0_[1]\,
      I2 => \cal2_state_r_reg_n_0_[2]\,
      I3 => \cal2_state_r_reg_n_0_[0]\,
      I4 => \not_empty_wait_cnt_reg[4]_0\,
      O => \tap_inc_wait_cnt[3]_i_1_n_0\
    );
\tap_inc_wait_cnt[3]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6AAA"
    )
        port map (
      I0 => tap_inc_wait_cnt_reg(3),
      I1 => tap_inc_wait_cnt_reg(1),
      I2 => tap_inc_wait_cnt_reg(0),
      I3 => tap_inc_wait_cnt_reg(2),
      O => \p_0_in__0\(3)
    );
\tap_inc_wait_cnt_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => wrcal_pat_resume_reg_0,
      CE => '1',
      D => \p_0_in__0\(0),
      Q => tap_inc_wait_cnt_reg(0),
      R => \tap_inc_wait_cnt[3]_i_1_n_0\
    );
\tap_inc_wait_cnt_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => wrcal_pat_resume_reg_0,
      CE => '1',
      D => \p_0_in__0\(1),
      Q => tap_inc_wait_cnt_reg(1),
      R => \tap_inc_wait_cnt[3]_i_1_n_0\
    );
\tap_inc_wait_cnt_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => wrcal_pat_resume_reg_0,
      CE => '1',
      D => \p_0_in__0\(2),
      Q => tap_inc_wait_cnt_reg(2),
      R => \tap_inc_wait_cnt[3]_i_1_n_0\
    );
\tap_inc_wait_cnt_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => wrcal_pat_resume_reg_0,
      CE => '1',
      D => \p_0_in__0\(3),
      Q => tap_inc_wait_cnt_reg(3),
      R => \tap_inc_wait_cnt[3]_i_1_n_0\
    );
\wl_tap_count_r[5]_i_3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \^wrlvl_byte_redo\,
      I1 => wrlvl_byte_redo_r,
      O => \^done_dqs_dec238_out\
    );
wrcal_done_i_1: unisim.vcomponents.LUT5
    generic map(
      INIT => X"45454500"
    )
        port map (
      I0 => \not_empty_wait_cnt_reg[4]_0\,
      I1 => wrcal_sanity_chk_r_reg_n_0,
      I2 => wrcal_sanity_chk,
      I3 => \^wrcal_done_reg_0\,
      I4 => cal2_done_r,
      O => wrcal_done_i_1_n_0
    );
wrcal_done_reg: unisim.vcomponents.FDRE
     port map (
      C => wrcal_pat_resume_reg_0,
      CE => '1',
      D => wrcal_done_i_1_n_0,
      Q => \^wrcal_done_reg_0\,
      R => '0'
    );
\wrcal_dqs_cnt_r[0]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \wrcal_dqs_cnt_r_reg_n_0_[0]\,
      I1 => \cal2_state_r_reg_n_0_[2]\,
      O => \wrcal_dqs_cnt_r[0]_i_1_n_0\
    );
\wrcal_dqs_cnt_r[1]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"06"
    )
        port map (
      I0 => \wrcal_dqs_cnt_r_reg_n_0_[0]\,
      I1 => \wrcal_dqs_cnt_r_reg_n_0_[1]\,
      I2 => \cal2_state_r_reg_n_0_[2]\,
      O => \wrcal_dqs_cnt_r[1]_i_1_n_0\
    );
\wrcal_dqs_cnt_r[2]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"006A"
    )
        port map (
      I0 => \wrcal_dqs_cnt_r_reg_n_0_[2]\,
      I1 => \wrcal_dqs_cnt_r_reg_n_0_[1]\,
      I2 => \wrcal_dqs_cnt_r_reg_n_0_[0]\,
      I3 => \cal2_state_r_reg_n_0_[2]\,
      O => \wrcal_dqs_cnt_r[2]_i_1_n_0\
    );
\wrcal_dqs_cnt_r[3]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"04"
    )
        port map (
      I0 => \cal2_state_r_reg_n_0_[3]\,
      I1 => \wrcal_dqs_cnt_r[3]_i_3_n_0\,
      I2 => \cal2_state_r_reg_n_0_[0]\,
      O => \wrcal_dqs_cnt_r[3]_i_1_n_0\
    );
\wrcal_dqs_cnt_r[3]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00007F80"
    )
        port map (
      I0 => \wrcal_dqs_cnt_r_reg_n_0_[1]\,
      I1 => \wrcal_dqs_cnt_r_reg_n_0_[0]\,
      I2 => \wrcal_dqs_cnt_r_reg_n_0_[2]\,
      I3 => wrcal_dqs_cnt_r(3),
      I4 => \cal2_state_r_reg_n_0_[2]\,
      O => \wrcal_dqs_cnt_r[3]_i_2_n_0\
    );
\wrcal_dqs_cnt_r[3]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"55C800C800000000"
    )
        port map (
      I0 => wrcal_sanity_chk_r_reg_n_0,
      I1 => \wrcal_dqs_cnt_r[3]_i_4_n_0\,
      I2 => prech_done,
      I3 => \cal2_state_r_reg_n_0_[2]\,
      I4 => wrcal_sanity_chk,
      I5 => \cal2_state_r_reg_n_0_[1]\,
      O => \wrcal_dqs_cnt_r[3]_i_3_n_0\
    );
\wrcal_dqs_cnt_r[3]_i_4\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FF7F"
    )
        port map (
      I0 => \wrcal_dqs_cnt_r_reg_n_0_[1]\,
      I1 => \wrcal_dqs_cnt_r_reg_n_0_[0]\,
      I2 => \wrcal_dqs_cnt_r_reg_n_0_[2]\,
      I3 => wrcal_dqs_cnt_r(3),
      O => \wrcal_dqs_cnt_r[3]_i_4_n_0\
    );
\wrcal_dqs_cnt_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => wrcal_pat_resume_reg_0,
      CE => \wrcal_dqs_cnt_r[3]_i_1_n_0\,
      D => \wrcal_dqs_cnt_r[0]_i_1_n_0\,
      Q => \wrcal_dqs_cnt_r_reg_n_0_[0]\,
      R => cal2_done_r_reg_0(0)
    );
\wrcal_dqs_cnt_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => wrcal_pat_resume_reg_0,
      CE => \wrcal_dqs_cnt_r[3]_i_1_n_0\,
      D => \wrcal_dqs_cnt_r[1]_i_1_n_0\,
      Q => \wrcal_dqs_cnt_r_reg_n_0_[1]\,
      R => cal2_done_r_reg_0(0)
    );
\wrcal_dqs_cnt_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => wrcal_pat_resume_reg_0,
      CE => \wrcal_dqs_cnt_r[3]_i_1_n_0\,
      D => \wrcal_dqs_cnt_r[2]_i_1_n_0\,
      Q => \wrcal_dqs_cnt_r_reg_n_0_[2]\,
      R => cal2_done_r_reg_0(0)
    );
\wrcal_dqs_cnt_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => wrcal_pat_resume_reg_0,
      CE => \wrcal_dqs_cnt_r[3]_i_1_n_0\,
      D => \wrcal_dqs_cnt_r[3]_i_2_n_0\,
      Q => wrcal_dqs_cnt_r(3),
      R => cal2_done_r_reg_0(0)
    );
wrcal_pat_resume_r2_reg_srl2: unisim.vcomponents.SRL16E
     port map (
      A0 => '1',
      A1 => '0',
      A2 => '0',
      A3 => '0',
      CE => '1',
      CLK => wrcal_pat_resume_reg_0,
      D => wrcal_pat_resume_r,
      Q => wrcal_pat_resume_r2_reg_srl2_n_0
    );
wrcal_pat_resume_r_i_1: unisim.vcomponents.LUT5
    generic map(
      INIT => X"F8FFF800"
    )
        port map (
      I0 => \cal2_state_r_reg_n_0_[2]\,
      I1 => idelay_ld_done_reg_n_0,
      I2 => \cal2_state_r_reg_n_0_[1]\,
      I3 => wrcal_pat_resume_r_i_2_n_0,
      I4 => wrcal_pat_resume_r,
      O => wrcal_pat_resume_r_i_1_n_0
    );
wrcal_pat_resume_r_i_2: unisim.vcomponents.LUT6
    generic map(
      INIT => X"08000800033C003C"
    )
        port map (
      I0 => \cal2_state_r[3]_i_7_n_0\,
      I1 => \cal2_state_r_reg_n_0_[0]\,
      I2 => \cal2_state_r_reg_n_0_[3]\,
      I3 => \cal2_state_r_reg_n_0_[2]\,
      I4 => wrcal_pat_resume_r_i_3_n_0,
      I5 => \cal2_state_r_reg_n_0_[1]\,
      O => wrcal_pat_resume_r_i_2_n_0
    );
wrcal_pat_resume_r_i_3: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000800000000000"
    )
        port map (
      I0 => tap_inc_wait_cnt_reg(2),
      I1 => idelay_ld_done_reg_n_0,
      I2 => tap_inc_wait_cnt_reg(0),
      I3 => tap_inc_wait_cnt_reg(1),
      I4 => wrcal_sanity_chk_r_reg_n_0,
      I5 => tap_inc_wait_cnt_reg(3),
      O => wrcal_pat_resume_r_i_3_n_0
    );
wrcal_pat_resume_r_reg: unisim.vcomponents.FDRE
     port map (
      C => wrcal_pat_resume_reg_0,
      CE => '1',
      D => wrcal_pat_resume_r_i_1_n_0,
      Q => wrcal_pat_resume_r,
      R => cal2_done_r_reg_0(0)
    );
wrcal_pat_resume_reg: unisim.vcomponents.FDRE
     port map (
      C => wrcal_pat_resume_reg_0,
      CE => '1',
      D => wrcal_pat_resume_r2_reg_srl2_n_0,
      Q => wrcal_resume_w,
      R => '0'
    );
wrcal_prech_req_reg: unisim.vcomponents.FDRE
     port map (
      C => wrcal_pat_resume_reg_0,
      CE => '1',
      D => cal2_prech_req_r,
      Q => wrcal_prech_req,
      R => cal2_done_r_reg_0(0)
    );
wrcal_sanity_chk_done_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFF00004000"
    )
        port map (
      I0 => \cal2_state_r_reg_n_0_[3]\,
      I1 => \cal2_state_r_reg_n_0_[2]\,
      I2 => wrcal_sanity_chk_r_reg_n_0,
      I3 => \cal2_state_r_reg_n_0_[1]\,
      I4 => \cal2_state_r_reg_n_0_[0]\,
      I5 => \^wrcal_sanity_chk_done_reg_0\,
      O => wrcal_sanity_chk_done_i_1_n_0
    );
wrcal_sanity_chk_done_reg: unisim.vcomponents.FDRE
     port map (
      C => wrcal_pat_resume_reg_0,
      CE => '1',
      D => wrcal_sanity_chk_done_i_1_n_0,
      Q => \^wrcal_sanity_chk_done_reg_0\,
      R => cal2_if_reset_reg_0
    );
wrcal_sanity_chk_r_reg: unisim.vcomponents.FDRE
     port map (
      C => wrcal_pat_resume_reg_0,
      CE => '1',
      D => wrcal_sanity_chk,
      Q => wrcal_sanity_chk_r_reg_n_0,
      R => '0'
    );
\wrdq_div1_4to1_wrcal_first.phy_wrdata[445]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \^wrcal_done_reg_0\,
      O => wrcal_done_reg_1
    );
\wrdq_div1_4to1_wrcal_first.phy_wrdata[508]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"7"
    )
        port map (
      I0 => \^wrcal_done_reg_0\,
      I1 => \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[508]\,
      O => wrcal_done_reg_4
    );
wrlvl_byte_done_r_reg: unisim.vcomponents.FDRE
     port map (
      C => wrcal_pat_resume_reg_0,
      CE => '1',
      D => wrlvl_byte_done,
      Q => wrlvl_byte_done_r,
      R => '0'
    );
wrlvl_byte_redo_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0EFFFFFF0E000000"
    )
        port map (
      I0 => \gen_pat_match_div4.early2_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.early1_data_match_r_reg_n_0\,
      I2 => \cal2_state_r_reg_n_0_[1]\,
      I3 => wrlvl_byte_redo_i_2_n_0,
      I4 => \cal2_state_r_reg_n_0_[0]\,
      I5 => \^wrlvl_byte_redo\,
      O => wrlvl_byte_redo_i_1_n_0
    );
wrlvl_byte_redo_i_2: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000022222E22"
    )
        port map (
      I0 => wrlvl_byte_redo_i_3_n_0,
      I1 => \cal2_state_r_reg_n_0_[1]\,
      I2 => \cal2_state_r_reg_n_0_[2]\,
      I3 => wrlvl_byte_done,
      I4 => wrlvl_byte_done_r,
      I5 => \cal2_state_r_reg_n_0_[3]\,
      O => wrlvl_byte_redo_i_2_n_0
    );
wrlvl_byte_redo_i_3: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000005040"
    )
        port map (
      I0 => \gen_pat_match_div4.pat_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.early1_data_match_r_reg_n_0\,
      I2 => \gen_pat_match_div4.pat_data_match_valid_r_reg_n_0\,
      I3 => \gen_pat_match_div4.early2_data_match_r_reg_n_0\,
      I4 => wrcal_sanity_chk_r_reg_n_0,
      I5 => \cal2_state_r_reg_n_0_[2]\,
      O => wrlvl_byte_redo_i_3_n_0
    );
wrlvl_byte_redo_reg: unisim.vcomponents.FDRE
     port map (
      C => wrcal_pat_resume_reg_0,
      CE => '1',
      D => wrlvl_byte_redo_i_1_n_0,
      Q => \^wrlvl_byte_redo\,
      R => cal2_done_r_reg_0(0)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mig_mig_7series_v4_2_ddr_phy_wrlvl is
  port (
    wr_level_done_r5 : out STD_LOGIC;
    wrlvl_byte_redo_r : out STD_LOGIC;
    dqs_po_dec_done : out STD_LOGIC;
    dqs_po_en_stg2_f : out STD_LOGIC;
    po_cnt_dec_reg_0 : out STD_LOGIC;
    wr_level_done_reg_0 : out STD_LOGIC;
    wrlvl_rank_done : out STD_LOGIC;
    \FSM_sequential_wl_state_r_reg[4]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \dqs_count_r_reg[3]_0\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    \dqs_count_r_reg[2]_rep__0_0\ : out STD_LOGIC;
    \calib_sel_reg[1]\ : out STD_LOGIC;
    \calib_sel_reg[1]_0\ : out STD_LOGIC;
    \calib_sel_reg[1]_1\ : out STD_LOGIC;
    dqs_wl_po_stg2_c_incdec_reg_0 : out STD_LOGIC;
    \calib_sel_reg[1]_2\ : out STD_LOGIC;
    \calib_sel_reg[1]_3\ : out STD_LOGIC;
    \calib_sel_reg[1]_4\ : out STD_LOGIC;
    \calib_sel_reg[0]\ : out STD_LOGIC;
    \calib_sel_reg[1]_5\ : out STD_LOGIC;
    \calib_sel_reg[1]_6\ : out STD_LOGIC;
    \calib_sel_reg[1]_7\ : out STD_LOGIC;
    dqs_wl_po_stg2_c_incdec_reg_1 : out STD_LOGIC;
    \calib_sel_reg[1]_8\ : out STD_LOGIC;
    \calib_sel_reg[1]_9\ : out STD_LOGIC;
    \calib_sel_reg[1]_10\ : out STD_LOGIC;
    \calib_sel_reg[0]_0\ : out STD_LOGIC;
    C_po_coarse_enable26_out : out STD_LOGIC;
    \gen_byte_sel_div2.calib_in_common_reg\ : out STD_LOGIC;
    \gen_byte_sel_div2.calib_in_common_reg_0\ : out STD_LOGIC;
    C_po_fine_enable23_out : out STD_LOGIC;
    \gen_byte_sel_div2.calib_in_common_reg_1\ : out STD_LOGIC;
    \gen_byte_sel_div2.calib_in_common_reg_2\ : out STD_LOGIC;
    dqs_po_stg2_f_incdec_reg_0 : out STD_LOGIC;
    dqs_po_stg2_f_incdec_reg_1 : out STD_LOGIC;
    dqs_po_stg2_f_incdec_reg_2 : out STD_LOGIC;
    dqs_po_stg2_f_incdec_reg_3 : out STD_LOGIC;
    dqs_po_stg2_f_incdec_reg_4 : out STD_LOGIC;
    dqs_po_stg2_f_incdec_reg_5 : out STD_LOGIC;
    dqs_po_stg2_f_incdec_reg_6 : out STD_LOGIC;
    dqs_po_stg2_f_incdec_reg_7 : out STD_LOGIC;
    C_po_fine_inc29_out : out STD_LOGIC;
    dqs_po_stg2_f_incdec_reg_8 : out STD_LOGIC;
    dqs_po_stg2_f_incdec_reg_9 : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_0\ : out STD_LOGIC;
    \FSM_sequential_wl_state_r_reg[2]_0\ : out STD_LOGIC;
    \dqs_count_r_reg[0]_rep_0\ : out STD_LOGIC;
    \dqs_count_r_reg[1]_rep_0\ : out STD_LOGIC;
    done_dqs_tap_inc : out STD_LOGIC;
    SS : out STD_LOGIC_VECTOR ( 0 to 0 );
    cmd_delay_start0 : out STD_LOGIC;
    wrlvl_byte_done : out STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 0 to 0 );
    \dqs_count_r_reg[2]_rep__0_1\ : in STD_LOGIC;
    wrlvl_byte_redo : in STD_LOGIC;
    wr_level_start_r_reg_0 : in STD_LOGIC;
    \fine_dec_cnt_reg[5]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \corse_inc_reg[6][2]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \wl_dqs_tap_count_r_reg[0][5][5]_0\ : in STD_LOGIC;
    wl_sm_start : in STD_LOGIC;
    phaser_out : in STD_LOGIC;
    phaser_out_0 : in STD_LOGIC;
    po_enstg2_f : in STD_LOGIC_VECTOR ( 0 to 0 );
    calib_in_common : in STD_LOGIC;
    phaser_out_1 : in STD_LOGIC_VECTOR ( 2 downto 0 );
    ck_po_stg2_f_indec : in STD_LOGIC;
    \single_rank.done_dqs_dec_reg_0\ : in STD_LOGIC;
    done_dqs_dec238_out : in STD_LOGIC;
    \dqs_count_r_reg[3]_1\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
    \corse_cnt_reg[7][0]_0\ : in STD_LOGIC;
    \corse_cnt_reg[7][0]_1\ : in STD_LOGIC;
    \corse_cnt_reg[6][0]_0\ : in STD_LOGIC;
    \corse_cnt_reg[5][0]_0\ : in STD_LOGIC;
    \corse_cnt_reg[4][0]_0\ : in STD_LOGIC;
    \corse_cnt_reg[3][0]_0\ : in STD_LOGIC;
    \FSM_sequential_wl_state_r_reg[0]_0\ : in STD_LOGIC;
    \wrlvl_redo_corse_inc[2]_i_4_0\ : in STD_LOGIC;
    \po_rdval_cnt_reg[7]_0\ : in STD_LOGIC;
    \po_rdval_cnt_reg[8]_0\ : in STD_LOGIC;
    \po_rdval_cnt_reg[0]_0\ : in STD_LOGIC;
    \po_rdval_cnt_reg[1]_0\ : in STD_LOGIC;
    \po_rdval_cnt_reg[2]_0\ : in STD_LOGIC;
    \po_rdval_cnt_reg[3]_0\ : in STD_LOGIC;
    \po_rdval_cnt_reg[4]_0\ : in STD_LOGIC;
    \po_rdval_cnt_reg[5]_0\ : in STD_LOGIC;
    \po_rdval_cnt_reg[6]_0\ : in STD_LOGIC;
    \wrlvl_redo_corse_inc_reg[2]_0\ : in STD_LOGIC;
    pi_fine_dly_dec_done : in STD_LOGIC;
    delaydec_cnt_r10_in : in STD_LOGIC;
    \fine_inc_reg[6][3]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dqs_count_r_reg[2]_rep__0_2\ : in STD_LOGIC;
    \corse_dec_reg[7][0]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \wait_cnt_reg[0]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \gen_rd[0].rd_data_rise_wl_r_reg[0]_0\ : in STD_LOGIC;
    \gen_rd[0].rd_data_rise_wl_r_reg[0]_1\ : in STD_LOGIC;
    \gen_rd[0].rd_data_rise_wl_r_reg[0]_2\ : in STD_LOGIC;
    \gen_rd[0].rd_data_rise_wl_r_reg[0]_3\ : in STD_LOGIC;
    \gen_rd[0].rd_data_rise_wl_r_reg[0]_4\ : in STD_LOGIC;
    \gen_rd[0].rd_data_rise_wl_r_reg[0]_5\ : in STD_LOGIC;
    \gen_rd[0].rd_data_rise_wl_r_reg[0]_6\ : in STD_LOGIC;
    \gen_rd[0].rd_data_rise_wl_r_reg[0]_7\ : in STD_LOGIC;
    \gen_rd[1].rd_data_rise_wl_r_reg[1]_0\ : in STD_LOGIC;
    \gen_rd[1].rd_data_rise_wl_r_reg[1]_1\ : in STD_LOGIC;
    \gen_rd[1].rd_data_rise_wl_r_reg[1]_2\ : in STD_LOGIC;
    \gen_rd[1].rd_data_rise_wl_r_reg[1]_3\ : in STD_LOGIC;
    \gen_rd[1].rd_data_rise_wl_r_reg[1]_4\ : in STD_LOGIC;
    \gen_rd[1].rd_data_rise_wl_r_reg[1]_5\ : in STD_LOGIC;
    \gen_rd[1].rd_data_rise_wl_r_reg[1]_6\ : in STD_LOGIC;
    \gen_rd[1].rd_data_rise_wl_r_reg[1]_7\ : in STD_LOGIC;
    \gen_rd[2].rd_data_rise_wl_r_reg[2]_0\ : in STD_LOGIC;
    \gen_rd[2].rd_data_rise_wl_r_reg[2]_1\ : in STD_LOGIC;
    \gen_rd[2].rd_data_rise_wl_r_reg[2]_2\ : in STD_LOGIC;
    \gen_rd[2].rd_data_rise_wl_r_reg[2]_3\ : in STD_LOGIC;
    \gen_rd[2].rd_data_rise_wl_r_reg[2]_4\ : in STD_LOGIC;
    \gen_rd[2].rd_data_rise_wl_r_reg[2]_5\ : in STD_LOGIC;
    \gen_rd[2].rd_data_rise_wl_r_reg[2]_6\ : in STD_LOGIC;
    \gen_rd[2].rd_data_rise_wl_r_reg[2]_7\ : in STD_LOGIC;
    \gen_rd[3].rd_data_rise_wl_r_reg[3]_0\ : in STD_LOGIC;
    \gen_rd[3].rd_data_rise_wl_r_reg[3]_1\ : in STD_LOGIC;
    \gen_rd[3].rd_data_rise_wl_r_reg[3]_2\ : in STD_LOGIC;
    \gen_rd[3].rd_data_rise_wl_r_reg[3]_3\ : in STD_LOGIC;
    \gen_rd[3].rd_data_rise_wl_r_reg[3]_4\ : in STD_LOGIC;
    \gen_rd[3].rd_data_rise_wl_r_reg[3]_5\ : in STD_LOGIC;
    \gen_rd[3].rd_data_rise_wl_r_reg[3]_6\ : in STD_LOGIC;
    \gen_rd[3].rd_data_rise_wl_r_reg[3]_7\ : in STD_LOGIC;
    \gen_rd[4].rd_data_rise_wl_r_reg[4]_0\ : in STD_LOGIC;
    \gen_rd[4].rd_data_rise_wl_r_reg[4]_1\ : in STD_LOGIC;
    \gen_rd[4].rd_data_rise_wl_r_reg[4]_2\ : in STD_LOGIC;
    \gen_rd[4].rd_data_rise_wl_r_reg[4]_3\ : in STD_LOGIC;
    \gen_rd[4].rd_data_rise_wl_r_reg[4]_4\ : in STD_LOGIC;
    \gen_rd[4].rd_data_rise_wl_r_reg[4]_5\ : in STD_LOGIC;
    \gen_rd[4].rd_data_rise_wl_r_reg[4]_6\ : in STD_LOGIC;
    \gen_rd[4].rd_data_rise_wl_r_reg[4]_7\ : in STD_LOGIC;
    \gen_rd[5].rd_data_rise_wl_r_reg[5]_0\ : in STD_LOGIC;
    \gen_rd[5].rd_data_rise_wl_r_reg[5]_1\ : in STD_LOGIC;
    \gen_rd[5].rd_data_rise_wl_r_reg[5]_2\ : in STD_LOGIC;
    \gen_rd[5].rd_data_rise_wl_r_reg[5]_3\ : in STD_LOGIC;
    \gen_rd[5].rd_data_rise_wl_r_reg[5]_4\ : in STD_LOGIC;
    \gen_rd[5].rd_data_rise_wl_r_reg[5]_5\ : in STD_LOGIC;
    \gen_rd[5].rd_data_rise_wl_r_reg[5]_6\ : in STD_LOGIC;
    \gen_rd[5].rd_data_rise_wl_r_reg[5]_7\ : in STD_LOGIC;
    \gen_rd[6].rd_data_rise_wl_r_reg[6]_0\ : in STD_LOGIC;
    \gen_rd[6].rd_data_rise_wl_r_reg[6]_1\ : in STD_LOGIC;
    \gen_rd[6].rd_data_rise_wl_r_reg[6]_2\ : in STD_LOGIC;
    \gen_rd[6].rd_data_rise_wl_r_reg[6]_3\ : in STD_LOGIC;
    \gen_rd[6].rd_data_rise_wl_r_reg[6]_4\ : in STD_LOGIC;
    \gen_rd[6].rd_data_rise_wl_r_reg[6]_5\ : in STD_LOGIC;
    \gen_rd[6].rd_data_rise_wl_r_reg[6]_6\ : in STD_LOGIC;
    \gen_rd[6].rd_data_rise_wl_r_reg[6]_7\ : in STD_LOGIC;
    \gen_rd[7].rd_data_rise_wl_r_reg[7]_0\ : in STD_LOGIC;
    \gen_rd[7].rd_data_rise_wl_r_reg[7]_1\ : in STD_LOGIC;
    \gen_rd[7].rd_data_rise_wl_r_reg[7]_2\ : in STD_LOGIC;
    \gen_rd[7].rd_data_rise_wl_r_reg[7]_3\ : in STD_LOGIC;
    \gen_rd[7].rd_data_rise_wl_r_reg[7]_4\ : in STD_LOGIC;
    \gen_rd[7].rd_data_rise_wl_r_reg[7]_5\ : in STD_LOGIC;
    \gen_rd[7].rd_data_rise_wl_r_reg[7]_6\ : in STD_LOGIC;
    \gen_rd[7].rd_data_rise_wl_r_reg[7]_7\ : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of mig_mig_7series_v4_2_ddr_phy_wrlvl : entity is "mig_7series_v4_2_ddr_phy_wrlvl";
end mig_mig_7series_v4_2_ddr_phy_wrlvl;

architecture STRUCTURE of mig_mig_7series_v4_2_ddr_phy_wrlvl is
  signal \FSM_sequential_wl_state_r[0]_i_10_n_0\ : STD_LOGIC;
  signal \FSM_sequential_wl_state_r[0]_i_11_n_0\ : STD_LOGIC;
  signal \FSM_sequential_wl_state_r[0]_i_12_n_0\ : STD_LOGIC;
  signal \FSM_sequential_wl_state_r[0]_i_14_n_0\ : STD_LOGIC;
  signal \FSM_sequential_wl_state_r[0]_i_15_n_0\ : STD_LOGIC;
  signal \FSM_sequential_wl_state_r[0]_i_1_n_0\ : STD_LOGIC;
  signal \FSM_sequential_wl_state_r[0]_i_2_n_0\ : STD_LOGIC;
  signal \FSM_sequential_wl_state_r[0]_i_3_n_0\ : STD_LOGIC;
  signal \FSM_sequential_wl_state_r[0]_i_4_n_0\ : STD_LOGIC;
  signal \FSM_sequential_wl_state_r[0]_i_5_n_0\ : STD_LOGIC;
  signal \FSM_sequential_wl_state_r[0]_i_6_n_0\ : STD_LOGIC;
  signal \FSM_sequential_wl_state_r[0]_i_7_n_0\ : STD_LOGIC;
  signal \FSM_sequential_wl_state_r[0]_i_8_n_0\ : STD_LOGIC;
  signal \FSM_sequential_wl_state_r[0]_i_9_n_0\ : STD_LOGIC;
  signal \FSM_sequential_wl_state_r[1]_i_10_n_0\ : STD_LOGIC;
  signal \FSM_sequential_wl_state_r[1]_i_11_n_0\ : STD_LOGIC;
  signal \FSM_sequential_wl_state_r[1]_i_1_n_0\ : STD_LOGIC;
  signal \FSM_sequential_wl_state_r[1]_i_2_n_0\ : STD_LOGIC;
  signal \FSM_sequential_wl_state_r[1]_i_3_n_0\ : STD_LOGIC;
  signal \FSM_sequential_wl_state_r[1]_i_4_n_0\ : STD_LOGIC;
  signal \FSM_sequential_wl_state_r[1]_i_5_n_0\ : STD_LOGIC;
  signal \FSM_sequential_wl_state_r[1]_i_6_n_0\ : STD_LOGIC;
  signal \FSM_sequential_wl_state_r[1]_i_7_n_0\ : STD_LOGIC;
  signal \FSM_sequential_wl_state_r[1]_i_8_n_0\ : STD_LOGIC;
  signal \FSM_sequential_wl_state_r[1]_i_9_n_0\ : STD_LOGIC;
  signal \FSM_sequential_wl_state_r[2]_i_10_n_0\ : STD_LOGIC;
  signal \FSM_sequential_wl_state_r[2]_i_11_n_0\ : STD_LOGIC;
  signal \FSM_sequential_wl_state_r[2]_i_12_n_0\ : STD_LOGIC;
  signal \FSM_sequential_wl_state_r[2]_i_13_n_0\ : STD_LOGIC;
  signal \FSM_sequential_wl_state_r[2]_i_14_n_0\ : STD_LOGIC;
  signal \FSM_sequential_wl_state_r[2]_i_1_n_0\ : STD_LOGIC;
  signal \FSM_sequential_wl_state_r[2]_i_2_n_0\ : STD_LOGIC;
  signal \FSM_sequential_wl_state_r[2]_i_3_n_0\ : STD_LOGIC;
  signal \FSM_sequential_wl_state_r[2]_i_4_n_0\ : STD_LOGIC;
  signal \FSM_sequential_wl_state_r[2]_i_5_n_0\ : STD_LOGIC;
  signal \FSM_sequential_wl_state_r[2]_i_6_n_0\ : STD_LOGIC;
  signal \FSM_sequential_wl_state_r[2]_i_7_n_0\ : STD_LOGIC;
  signal \FSM_sequential_wl_state_r[2]_i_8_n_0\ : STD_LOGIC;
  signal \FSM_sequential_wl_state_r[2]_i_9_n_0\ : STD_LOGIC;
  signal \FSM_sequential_wl_state_r[3]_i_10_n_0\ : STD_LOGIC;
  signal \FSM_sequential_wl_state_r[3]_i_11_n_0\ : STD_LOGIC;
  signal \FSM_sequential_wl_state_r[3]_i_12_n_0\ : STD_LOGIC;
  signal \FSM_sequential_wl_state_r[3]_i_13_n_0\ : STD_LOGIC;
  signal \FSM_sequential_wl_state_r[3]_i_14_n_0\ : STD_LOGIC;
  signal \FSM_sequential_wl_state_r[3]_i_1_n_0\ : STD_LOGIC;
  signal \FSM_sequential_wl_state_r[3]_i_2_n_0\ : STD_LOGIC;
  signal \FSM_sequential_wl_state_r[3]_i_3_n_0\ : STD_LOGIC;
  signal \FSM_sequential_wl_state_r[3]_i_4_n_0\ : STD_LOGIC;
  signal \FSM_sequential_wl_state_r[3]_i_5_n_0\ : STD_LOGIC;
  signal \FSM_sequential_wl_state_r[3]_i_6_n_0\ : STD_LOGIC;
  signal \FSM_sequential_wl_state_r[3]_i_7_n_0\ : STD_LOGIC;
  signal \FSM_sequential_wl_state_r[3]_i_8_n_0\ : STD_LOGIC;
  signal \FSM_sequential_wl_state_r[3]_i_9_n_0\ : STD_LOGIC;
  signal \FSM_sequential_wl_state_r[4]_i_10_n_0\ : STD_LOGIC;
  signal \FSM_sequential_wl_state_r[4]_i_11_n_0\ : STD_LOGIC;
  signal \FSM_sequential_wl_state_r[4]_i_12_n_0\ : STD_LOGIC;
  signal \FSM_sequential_wl_state_r[4]_i_13_n_0\ : STD_LOGIC;
  signal \FSM_sequential_wl_state_r[4]_i_14_n_0\ : STD_LOGIC;
  signal \FSM_sequential_wl_state_r[4]_i_15_n_0\ : STD_LOGIC;
  signal \FSM_sequential_wl_state_r[4]_i_16_n_0\ : STD_LOGIC;
  signal \FSM_sequential_wl_state_r[4]_i_17_n_0\ : STD_LOGIC;
  signal \FSM_sequential_wl_state_r[4]_i_18_n_0\ : STD_LOGIC;
  signal \FSM_sequential_wl_state_r[4]_i_1_n_0\ : STD_LOGIC;
  signal \FSM_sequential_wl_state_r[4]_i_20_n_0\ : STD_LOGIC;
  signal \FSM_sequential_wl_state_r[4]_i_2_n_0\ : STD_LOGIC;
  signal \FSM_sequential_wl_state_r[4]_i_3_n_0\ : STD_LOGIC;
  signal \FSM_sequential_wl_state_r[4]_i_4_n_0\ : STD_LOGIC;
  signal \FSM_sequential_wl_state_r[4]_i_5_n_0\ : STD_LOGIC;
  signal \FSM_sequential_wl_state_r[4]_i_6_n_0\ : STD_LOGIC;
  signal \FSM_sequential_wl_state_r[4]_i_8_n_0\ : STD_LOGIC;
  signal \FSM_sequential_wl_state_r[4]_i_9_n_0\ : STD_LOGIC;
  signal \^fsm_sequential_wl_state_r_reg[2]_0\ : STD_LOGIC;
  signal \^fsm_sequential_wl_state_r_reg[4]_0\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \FSM_sequential_wl_state_r_reg[4]_i_7_n_0\ : STD_LOGIC;
  signal corse_cnt : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal \corse_cnt[0][0]_i_1_n_0\ : STD_LOGIC;
  signal \corse_cnt[0][0]_i_3_n_0\ : STD_LOGIC;
  signal \corse_cnt[0][0]_i_4_n_0\ : STD_LOGIC;
  signal \corse_cnt[0][0]_i_5_n_0\ : STD_LOGIC;
  signal \corse_cnt[0][0]_i_6_n_0\ : STD_LOGIC;
  signal \corse_cnt[0][0]_i_7_n_0\ : STD_LOGIC;
  signal \corse_cnt[0][0]_i_8_n_0\ : STD_LOGIC;
  signal \corse_cnt[0][0]_i_9_n_0\ : STD_LOGIC;
  signal \corse_cnt[0][1]_i_1_n_0\ : STD_LOGIC;
  signal \corse_cnt[0][1]_i_3_n_0\ : STD_LOGIC;
  signal \corse_cnt[0][1]_i_4_n_0\ : STD_LOGIC;
  signal \corse_cnt[0][1]_i_5_n_0\ : STD_LOGIC;
  signal \corse_cnt[0][1]_i_6_n_0\ : STD_LOGIC;
  signal \corse_cnt[0][2]_i_11_n_0\ : STD_LOGIC;
  signal \corse_cnt[0][2]_i_12_n_0\ : STD_LOGIC;
  signal \corse_cnt[0][2]_i_13_n_0\ : STD_LOGIC;
  signal \corse_cnt[0][2]_i_1_n_0\ : STD_LOGIC;
  signal \corse_cnt[0][2]_i_3_n_0\ : STD_LOGIC;
  signal \corse_cnt[0][2]_i_4_n_0\ : STD_LOGIC;
  signal \corse_cnt[0][2]_i_5_n_0\ : STD_LOGIC;
  signal \corse_cnt[0][2]_i_6_n_0\ : STD_LOGIC;
  signal \corse_cnt[0][2]_i_7_n_0\ : STD_LOGIC;
  signal \corse_cnt[0][2]_i_8_n_0\ : STD_LOGIC;
  signal \corse_cnt[1][0]_i_1_n_0\ : STD_LOGIC;
  signal \corse_cnt[1][1]_i_1_n_0\ : STD_LOGIC;
  signal \corse_cnt[1][2]_i_1_n_0\ : STD_LOGIC;
  signal \corse_cnt[1][2]_i_2_n_0\ : STD_LOGIC;
  signal \corse_cnt[2][0]_i_1_n_0\ : STD_LOGIC;
  signal \corse_cnt[2][1]_i_1_n_0\ : STD_LOGIC;
  signal \corse_cnt[2][2]_i_1_n_0\ : STD_LOGIC;
  signal \corse_cnt[2][2]_i_2_n_0\ : STD_LOGIC;
  signal \corse_cnt[3][0]_i_1_n_0\ : STD_LOGIC;
  signal \corse_cnt[3][1]_i_1_n_0\ : STD_LOGIC;
  signal \corse_cnt[3][2]_i_1_n_0\ : STD_LOGIC;
  signal \corse_cnt[3][2]_i_2_n_0\ : STD_LOGIC;
  signal \corse_cnt[4][0]_i_1_n_0\ : STD_LOGIC;
  signal \corse_cnt[4][1]_i_1_n_0\ : STD_LOGIC;
  signal \corse_cnt[4][2]_i_1_n_0\ : STD_LOGIC;
  signal \corse_cnt[4][2]_i_2_n_0\ : STD_LOGIC;
  signal \corse_cnt[5][0]_i_1_n_0\ : STD_LOGIC;
  signal \corse_cnt[5][1]_i_1_n_0\ : STD_LOGIC;
  signal \corse_cnt[5][2]_i_1_n_0\ : STD_LOGIC;
  signal \corse_cnt[5][2]_i_2_n_0\ : STD_LOGIC;
  signal \corse_cnt[6][0]_i_1_n_0\ : STD_LOGIC;
  signal \corse_cnt[6][1]_i_1_n_0\ : STD_LOGIC;
  signal \corse_cnt[6][2]_i_1_n_0\ : STD_LOGIC;
  signal \corse_cnt[6][2]_i_2_n_0\ : STD_LOGIC;
  signal \corse_cnt[7][0]_i_1_n_0\ : STD_LOGIC;
  signal \corse_cnt[7][1]_i_1_n_0\ : STD_LOGIC;
  signal \corse_cnt[7][2]_i_1_n_0\ : STD_LOGIC;
  signal \corse_cnt[7][2]_i_2_n_0\ : STD_LOGIC;
  signal \corse_cnt_reg_n_0_[0][0]\ : STD_LOGIC;
  signal \corse_cnt_reg_n_0_[0][1]\ : STD_LOGIC;
  signal \corse_cnt_reg_n_0_[0][2]\ : STD_LOGIC;
  signal \corse_cnt_reg_n_0_[1][0]\ : STD_LOGIC;
  signal \corse_cnt_reg_n_0_[1][1]\ : STD_LOGIC;
  signal \corse_cnt_reg_n_0_[1][2]\ : STD_LOGIC;
  signal \corse_cnt_reg_n_0_[2][0]\ : STD_LOGIC;
  signal \corse_cnt_reg_n_0_[2][1]\ : STD_LOGIC;
  signal \corse_cnt_reg_n_0_[2][2]\ : STD_LOGIC;
  signal \corse_cnt_reg_n_0_[3][0]\ : STD_LOGIC;
  signal \corse_cnt_reg_n_0_[3][1]\ : STD_LOGIC;
  signal \corse_cnt_reg_n_0_[3][2]\ : STD_LOGIC;
  signal \corse_cnt_reg_n_0_[4][0]\ : STD_LOGIC;
  signal \corse_cnt_reg_n_0_[4][1]\ : STD_LOGIC;
  signal \corse_cnt_reg_n_0_[4][2]\ : STD_LOGIC;
  signal \corse_cnt_reg_n_0_[5][0]\ : STD_LOGIC;
  signal \corse_cnt_reg_n_0_[5][1]\ : STD_LOGIC;
  signal \corse_cnt_reg_n_0_[5][2]\ : STD_LOGIC;
  signal \corse_cnt_reg_n_0_[6][0]\ : STD_LOGIC;
  signal \corse_cnt_reg_n_0_[6][1]\ : STD_LOGIC;
  signal \corse_cnt_reg_n_0_[6][2]\ : STD_LOGIC;
  signal \corse_cnt_reg_n_0_[7][0]\ : STD_LOGIC;
  signal \corse_cnt_reg_n_0_[7][1]\ : STD_LOGIC;
  signal \corse_cnt_reg_n_0_[7][2]\ : STD_LOGIC;
  signal corse_dec : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \corse_dec[0][0]_i_1_n_0\ : STD_LOGIC;
  signal \corse_dec[0][1]_i_1_n_0\ : STD_LOGIC;
  signal \corse_dec[0][2]_i_11_n_0\ : STD_LOGIC;
  signal \corse_dec[0][2]_i_12_n_0\ : STD_LOGIC;
  signal \corse_dec[0][2]_i_1_n_0\ : STD_LOGIC;
  signal \corse_dec[0][2]_i_4_n_0\ : STD_LOGIC;
  signal \corse_dec[0][2]_i_5_n_0\ : STD_LOGIC;
  signal \corse_dec[0][2]_i_6_n_0\ : STD_LOGIC;
  signal \corse_dec[0][2]_i_7_n_0\ : STD_LOGIC;
  signal \corse_dec[0][2]_i_8_n_0\ : STD_LOGIC;
  signal \corse_dec[0][2]_i_9_n_0\ : STD_LOGIC;
  signal \corse_dec[1][0]_i_1_n_0\ : STD_LOGIC;
  signal \corse_dec[1][1]_i_1_n_0\ : STD_LOGIC;
  signal \corse_dec[1][2]_i_1_n_0\ : STD_LOGIC;
  signal \corse_dec[2][0]_i_1_n_0\ : STD_LOGIC;
  signal \corse_dec[2][1]_i_1_n_0\ : STD_LOGIC;
  signal \corse_dec[2][2]_i_1_n_0\ : STD_LOGIC;
  signal \corse_dec[3][0]_i_1_n_0\ : STD_LOGIC;
  signal \corse_dec[3][1]_i_1_n_0\ : STD_LOGIC;
  signal \corse_dec[3][2]_i_1_n_0\ : STD_LOGIC;
  signal \corse_dec[4][0]_i_1_n_0\ : STD_LOGIC;
  signal \corse_dec[4][1]_i_1_n_0\ : STD_LOGIC;
  signal \corse_dec[4][2]_i_1_n_0\ : STD_LOGIC;
  signal \corse_dec[5][0]_i_1_n_0\ : STD_LOGIC;
  signal \corse_dec[5][1]_i_1_n_0\ : STD_LOGIC;
  signal \corse_dec[5][2]_i_1_n_0\ : STD_LOGIC;
  signal \corse_dec[6][0]_i_1_n_0\ : STD_LOGIC;
  signal \corse_dec[6][1]_i_1_n_0\ : STD_LOGIC;
  signal \corse_dec[6][2]_i_1_n_0\ : STD_LOGIC;
  signal \corse_dec[7][0]_i_1_n_0\ : STD_LOGIC;
  signal \corse_dec[7][1]_i_1_n_0\ : STD_LOGIC;
  signal \corse_dec[7][2]_i_1_n_0\ : STD_LOGIC;
  signal \corse_dec_reg[0][2]_i_10_n_0\ : STD_LOGIC;
  signal \corse_dec_reg[0][2]_i_2_n_0\ : STD_LOGIC;
  signal \corse_dec_reg[0][2]_i_3_n_0\ : STD_LOGIC;
  signal \corse_dec_reg[0]_21\ : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal \corse_dec_reg[1]_22\ : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal \corse_dec_reg[2]_23\ : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal \corse_dec_reg[3]_24\ : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal \corse_dec_reg[4]_25\ : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal \corse_dec_reg[5]_26\ : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal \corse_dec_reg[6]_27\ : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal \corse_dec_reg[7]_28\ : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal corse_inc : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal \corse_inc[0][0]_i_1_n_0\ : STD_LOGIC;
  signal \corse_inc[0][1]_i_1_n_0\ : STD_LOGIC;
  signal \corse_inc[0][1]_i_5_n_0\ : STD_LOGIC;
  signal \corse_inc[0][1]_i_6_n_0\ : STD_LOGIC;
  signal \corse_inc[0][1]_i_7_n_0\ : STD_LOGIC;
  signal \corse_inc[0][1]_i_8_n_0\ : STD_LOGIC;
  signal \corse_inc[0][2]_i_1_n_0\ : STD_LOGIC;
  signal \corse_inc[0][2]_i_3_n_0\ : STD_LOGIC;
  signal \corse_inc[0][2]_i_4_n_0\ : STD_LOGIC;
  signal \corse_inc[0][2]_i_5_n_0\ : STD_LOGIC;
  signal \corse_inc[0][2]_i_7_n_0\ : STD_LOGIC;
  signal \corse_inc[0][2]_i_8_n_0\ : STD_LOGIC;
  signal \corse_inc[0][2]_i_9_n_0\ : STD_LOGIC;
  signal \corse_inc[1][0]_i_1_n_0\ : STD_LOGIC;
  signal \corse_inc[1][0]_i_2_n_0\ : STD_LOGIC;
  signal \corse_inc[1][1]_i_1_n_0\ : STD_LOGIC;
  signal \corse_inc[1][1]_i_2_n_0\ : STD_LOGIC;
  signal \corse_inc[1][2]_i_1_n_0\ : STD_LOGIC;
  signal \corse_inc[1][2]_i_2_n_0\ : STD_LOGIC;
  signal \corse_inc[2][0]_i_1_n_0\ : STD_LOGIC;
  signal \corse_inc[2][0]_i_2_n_0\ : STD_LOGIC;
  signal \corse_inc[2][1]_i_1_n_0\ : STD_LOGIC;
  signal \corse_inc[2][1]_i_2_n_0\ : STD_LOGIC;
  signal \corse_inc[2][2]_i_1_n_0\ : STD_LOGIC;
  signal \corse_inc[2][2]_i_2_n_0\ : STD_LOGIC;
  signal \corse_inc[3][0]_i_1_n_0\ : STD_LOGIC;
  signal \corse_inc[3][0]_i_2_n_0\ : STD_LOGIC;
  signal \corse_inc[3][1]_i_1_n_0\ : STD_LOGIC;
  signal \corse_inc[3][1]_i_2_n_0\ : STD_LOGIC;
  signal \corse_inc[3][2]_i_1_n_0\ : STD_LOGIC;
  signal \corse_inc[3][2]_i_2_n_0\ : STD_LOGIC;
  signal \corse_inc[4][0]_i_1_n_0\ : STD_LOGIC;
  signal \corse_inc[4][0]_i_2_n_0\ : STD_LOGIC;
  signal \corse_inc[4][1]_i_1_n_0\ : STD_LOGIC;
  signal \corse_inc[4][1]_i_2_n_0\ : STD_LOGIC;
  signal \corse_inc[4][2]_i_1_n_0\ : STD_LOGIC;
  signal \corse_inc[4][2]_i_2_n_0\ : STD_LOGIC;
  signal \corse_inc[5][0]_i_1_n_0\ : STD_LOGIC;
  signal \corse_inc[5][0]_i_2_n_0\ : STD_LOGIC;
  signal \corse_inc[5][1]_i_1_n_0\ : STD_LOGIC;
  signal \corse_inc[5][1]_i_2_n_0\ : STD_LOGIC;
  signal \corse_inc[5][2]_i_1_n_0\ : STD_LOGIC;
  signal \corse_inc[5][2]_i_2_n_0\ : STD_LOGIC;
  signal \corse_inc[6][0]_i_1_n_0\ : STD_LOGIC;
  signal \corse_inc[6][0]_i_2_n_0\ : STD_LOGIC;
  signal \corse_inc[6][1]_i_1_n_0\ : STD_LOGIC;
  signal \corse_inc[6][1]_i_2_n_0\ : STD_LOGIC;
  signal \corse_inc[6][2]_i_1_n_0\ : STD_LOGIC;
  signal \corse_inc[6][2]_i_2_n_0\ : STD_LOGIC;
  signal \corse_inc[7][0]_i_1_n_0\ : STD_LOGIC;
  signal \corse_inc[7][0]_i_2_n_0\ : STD_LOGIC;
  signal \corse_inc[7][1]_i_1_n_0\ : STD_LOGIC;
  signal \corse_inc[7][1]_i_2_n_0\ : STD_LOGIC;
  signal \corse_inc[7][2]_i_1_n_0\ : STD_LOGIC;
  signal \corse_inc[7][2]_i_2_n_0\ : STD_LOGIC;
  signal \corse_inc_reg[0][1]_i_3_n_0\ : STD_LOGIC;
  signal \corse_inc_reg[0][1]_i_4_n_0\ : STD_LOGIC;
  signal \corse_inc_reg[0][2]_i_6_n_0\ : STD_LOGIC;
  signal \corse_inc_reg[0]_37\ : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal \corse_inc_reg[1]_38\ : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal \corse_inc_reg[2]_39\ : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal \corse_inc_reg[3]_40\ : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal \corse_inc_reg[4]_41\ : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal \corse_inc_reg[5]_42\ : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal \corse_inc_reg[6]_43\ : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal \corse_inc_reg[7]_44\ : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal \^done_dqs_tap_inc\ : STD_LOGIC;
  signal dq_cnt_inc_i_1_n_0 : STD_LOGIC;
  signal dq_cnt_inc_i_2_n_0 : STD_LOGIC;
  signal dq_cnt_inc_i_3_n_0 : STD_LOGIC;
  signal dqs_count_r : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal \dqs_count_r[0]_i_1_n_0\ : STD_LOGIC;
  signal \dqs_count_r[0]_i_2_n_0\ : STD_LOGIC;
  signal \dqs_count_r[0]_i_3_n_0\ : STD_LOGIC;
  signal \dqs_count_r[0]_i_4_n_0\ : STD_LOGIC;
  signal \dqs_count_r[0]_i_5_n_0\ : STD_LOGIC;
  signal \dqs_count_r[1]_i_1_n_0\ : STD_LOGIC;
  signal \dqs_count_r[1]_i_2_n_0\ : STD_LOGIC;
  signal \dqs_count_r[1]_i_3_n_0\ : STD_LOGIC;
  signal \dqs_count_r[1]_i_4_n_0\ : STD_LOGIC;
  signal \dqs_count_r[1]_i_5_n_0\ : STD_LOGIC;
  signal \dqs_count_r[1]_i_6_n_0\ : STD_LOGIC;
  signal \dqs_count_r[1]_rep_i_1_n_0\ : STD_LOGIC;
  signal \dqs_count_r[2]_i_1_n_0\ : STD_LOGIC;
  signal \dqs_count_r[2]_i_2_n_0\ : STD_LOGIC;
  signal \dqs_count_r[2]_i_3_n_0\ : STD_LOGIC;
  signal \dqs_count_r[2]_i_4_n_0\ : STD_LOGIC;
  signal \dqs_count_r[2]_i_5_n_0\ : STD_LOGIC;
  signal \dqs_count_r[2]_i_6_n_0\ : STD_LOGIC;
  signal \dqs_count_r[2]_i_7_n_0\ : STD_LOGIC;
  signal \dqs_count_r[2]_i_8_n_0\ : STD_LOGIC;
  signal \dqs_count_r[2]_rep__0_i_1_n_0\ : STD_LOGIC;
  signal \dqs_count_r[2]_rep_i_1_n_0\ : STD_LOGIC;
  signal \dqs_count_r[3]_i_10_n_0\ : STD_LOGIC;
  signal \dqs_count_r[3]_i_11_n_0\ : STD_LOGIC;
  signal \dqs_count_r[3]_i_12_n_0\ : STD_LOGIC;
  signal \dqs_count_r[3]_i_1_n_0\ : STD_LOGIC;
  signal \dqs_count_r[3]_i_2_n_0\ : STD_LOGIC;
  signal \dqs_count_r[3]_i_3_n_0\ : STD_LOGIC;
  signal \dqs_count_r[3]_i_4_n_0\ : STD_LOGIC;
  signal \dqs_count_r[3]_i_5_n_0\ : STD_LOGIC;
  signal \dqs_count_r[3]_i_6_n_0\ : STD_LOGIC;
  signal \dqs_count_r[3]_i_7_n_0\ : STD_LOGIC;
  signal \dqs_count_r[3]_i_8_n_0\ : STD_LOGIC;
  signal \dqs_count_r[3]_i_9_n_0\ : STD_LOGIC;
  signal \^dqs_count_r_reg[0]_rep_0\ : STD_LOGIC;
  signal \^dqs_count_r_reg[1]_rep_0\ : STD_LOGIC;
  signal \^dqs_count_r_reg[2]_rep__0_0\ : STD_LOGIC;
  signal \dqs_count_r_reg[2]_rep_n_0\ : STD_LOGIC;
  signal \^dqs_count_r_reg[3]_0\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \^dqs_po_dec_done\ : STD_LOGIC;
  signal dqs_po_en_stg2_f_i_1_n_0 : STD_LOGIC;
  signal dqs_po_stg2_f_incdec : STD_LOGIC;
  signal dqs_po_stg2_f_incdec_i_1_n_0 : STD_LOGIC;
  signal dqs_po_stg2_f_incdec_i_2_n_0 : STD_LOGIC;
  signal dqs_wl_po_stg2_c_incdec_i_1_n_0 : STD_LOGIC;
  signal \final_coarse_tap_reg_n_0_[0][0]\ : STD_LOGIC;
  signal \final_coarse_tap_reg_n_0_[0][1]\ : STD_LOGIC;
  signal \final_coarse_tap_reg_n_0_[0][2]\ : STD_LOGIC;
  signal \final_coarse_tap_reg_n_0_[1][0]\ : STD_LOGIC;
  signal \final_coarse_tap_reg_n_0_[1][1]\ : STD_LOGIC;
  signal \final_coarse_tap_reg_n_0_[1][2]\ : STD_LOGIC;
  signal \final_coarse_tap_reg_n_0_[2][0]\ : STD_LOGIC;
  signal \final_coarse_tap_reg_n_0_[2][1]\ : STD_LOGIC;
  signal \final_coarse_tap_reg_n_0_[2][2]\ : STD_LOGIC;
  signal \final_coarse_tap_reg_n_0_[3][0]\ : STD_LOGIC;
  signal \final_coarse_tap_reg_n_0_[3][1]\ : STD_LOGIC;
  signal \final_coarse_tap_reg_n_0_[3][2]\ : STD_LOGIC;
  signal \final_coarse_tap_reg_n_0_[4][0]\ : STD_LOGIC;
  signal \final_coarse_tap_reg_n_0_[4][1]\ : STD_LOGIC;
  signal \final_coarse_tap_reg_n_0_[4][2]\ : STD_LOGIC;
  signal \final_coarse_tap_reg_n_0_[5][0]\ : STD_LOGIC;
  signal \final_coarse_tap_reg_n_0_[5][1]\ : STD_LOGIC;
  signal \final_coarse_tap_reg_n_0_[5][2]\ : STD_LOGIC;
  signal \final_coarse_tap_reg_n_0_[6][0]\ : STD_LOGIC;
  signal \final_coarse_tap_reg_n_0_[6][1]\ : STD_LOGIC;
  signal \final_coarse_tap_reg_n_0_[6][2]\ : STD_LOGIC;
  signal \final_coarse_tap_reg_n_0_[7][0]\ : STD_LOGIC;
  signal \final_coarse_tap_reg_n_0_[7][1]\ : STD_LOGIC;
  signal \final_coarse_tap_reg_n_0_[7][2]\ : STD_LOGIC;
  signal fine_dec_cnt : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal \fine_dec_cnt[3]_i_2_n_0\ : STD_LOGIC;
  signal \fine_dec_cnt[4]_i_2_n_0\ : STD_LOGIC;
  signal \fine_dec_cnt[5]_i_10_n_0\ : STD_LOGIC;
  signal \fine_dec_cnt[5]_i_1_n_0\ : STD_LOGIC;
  signal \fine_dec_cnt[5]_i_3_n_0\ : STD_LOGIC;
  signal \fine_dec_cnt[5]_i_4_n_0\ : STD_LOGIC;
  signal \fine_dec_cnt[5]_i_5_n_0\ : STD_LOGIC;
  signal \fine_dec_cnt[5]_i_6_n_0\ : STD_LOGIC;
  signal \fine_dec_cnt[5]_i_7_n_0\ : STD_LOGIC;
  signal \fine_dec_cnt[5]_i_8_n_0\ : STD_LOGIC;
  signal \fine_dec_cnt[5]_i_9_n_0\ : STD_LOGIC;
  signal \fine_dec_cnt_reg_n_0_[0]\ : STD_LOGIC;
  signal \fine_dec_cnt_reg_n_0_[1]\ : STD_LOGIC;
  signal \fine_dec_cnt_reg_n_0_[2]\ : STD_LOGIC;
  signal \fine_dec_cnt_reg_n_0_[3]\ : STD_LOGIC;
  signal \fine_dec_cnt_reg_n_0_[4]\ : STD_LOGIC;
  signal \fine_dec_cnt_reg_n_0_[5]\ : STD_LOGIC;
  signal fine_inc : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal \fine_inc[0][1]_i_4_n_0\ : STD_LOGIC;
  signal \fine_inc[0][1]_i_5_n_0\ : STD_LOGIC;
  signal \fine_inc[0][1]_i_6_n_0\ : STD_LOGIC;
  signal \fine_inc[0][1]_i_7_n_0\ : STD_LOGIC;
  signal \fine_inc[0][2]_i_3_n_0\ : STD_LOGIC;
  signal \fine_inc[0][2]_i_4_n_0\ : STD_LOGIC;
  signal \fine_inc[0][2]_i_5_n_0\ : STD_LOGIC;
  signal \fine_inc[0][3]_i_3_n_0\ : STD_LOGIC;
  signal \fine_inc[0][3]_i_4_n_0\ : STD_LOGIC;
  signal \fine_inc[0][3]_i_5_n_0\ : STD_LOGIC;
  signal \fine_inc[0][4]_i_2_n_0\ : STD_LOGIC;
  signal \fine_inc[0][5]_i_10_n_0\ : STD_LOGIC;
  signal \fine_inc[0][5]_i_11_n_0\ : STD_LOGIC;
  signal \fine_inc[0][5]_i_12_n_0\ : STD_LOGIC;
  signal \fine_inc[0][5]_i_13_n_0\ : STD_LOGIC;
  signal \fine_inc[0][5]_i_1_n_0\ : STD_LOGIC;
  signal \fine_inc[0][5]_i_3_n_0\ : STD_LOGIC;
  signal \fine_inc[0][5]_i_4_n_0\ : STD_LOGIC;
  signal \fine_inc[0][5]_i_5_n_0\ : STD_LOGIC;
  signal \fine_inc[0][5]_i_6_n_0\ : STD_LOGIC;
  signal \fine_inc[0][5]_i_8_n_0\ : STD_LOGIC;
  signal \fine_inc[1][0]_i_1_n_0\ : STD_LOGIC;
  signal \fine_inc[1][1]_i_1_n_0\ : STD_LOGIC;
  signal \fine_inc[1][2]_i_1_n_0\ : STD_LOGIC;
  signal \fine_inc[1][3]_i_1_n_0\ : STD_LOGIC;
  signal \fine_inc[1][4]_i_1_n_0\ : STD_LOGIC;
  signal \fine_inc[1][5]_i_1_n_0\ : STD_LOGIC;
  signal \fine_inc[1][5]_i_2_n_0\ : STD_LOGIC;
  signal \fine_inc[1][5]_i_3_n_0\ : STD_LOGIC;
  signal \fine_inc[2][0]_i_1_n_0\ : STD_LOGIC;
  signal \fine_inc[2][1]_i_1_n_0\ : STD_LOGIC;
  signal \fine_inc[2][2]_i_1_n_0\ : STD_LOGIC;
  signal \fine_inc[2][3]_i_1_n_0\ : STD_LOGIC;
  signal \fine_inc[2][4]_i_1_n_0\ : STD_LOGIC;
  signal \fine_inc[2][5]_i_1_n_0\ : STD_LOGIC;
  signal \fine_inc[2][5]_i_2_n_0\ : STD_LOGIC;
  signal \fine_inc[2][5]_i_3_n_0\ : STD_LOGIC;
  signal \fine_inc[3][0]_i_1_n_0\ : STD_LOGIC;
  signal \fine_inc[3][1]_i_1_n_0\ : STD_LOGIC;
  signal \fine_inc[3][2]_i_1_n_0\ : STD_LOGIC;
  signal \fine_inc[3][3]_i_1_n_0\ : STD_LOGIC;
  signal \fine_inc[3][4]_i_1_n_0\ : STD_LOGIC;
  signal \fine_inc[3][5]_i_1_n_0\ : STD_LOGIC;
  signal \fine_inc[3][5]_i_2_n_0\ : STD_LOGIC;
  signal \fine_inc[3][5]_i_3_n_0\ : STD_LOGIC;
  signal \fine_inc[4][0]_i_1_n_0\ : STD_LOGIC;
  signal \fine_inc[4][1]_i_1_n_0\ : STD_LOGIC;
  signal \fine_inc[4][2]_i_1_n_0\ : STD_LOGIC;
  signal \fine_inc[4][3]_i_1_n_0\ : STD_LOGIC;
  signal \fine_inc[4][4]_i_1_n_0\ : STD_LOGIC;
  signal \fine_inc[4][5]_i_1_n_0\ : STD_LOGIC;
  signal \fine_inc[4][5]_i_2_n_0\ : STD_LOGIC;
  signal \fine_inc[4][5]_i_3_n_0\ : STD_LOGIC;
  signal \fine_inc[5][0]_i_1_n_0\ : STD_LOGIC;
  signal \fine_inc[5][1]_i_1_n_0\ : STD_LOGIC;
  signal \fine_inc[5][2]_i_1_n_0\ : STD_LOGIC;
  signal \fine_inc[5][3]_i_1_n_0\ : STD_LOGIC;
  signal \fine_inc[5][4]_i_1_n_0\ : STD_LOGIC;
  signal \fine_inc[5][5]_i_1_n_0\ : STD_LOGIC;
  signal \fine_inc[5][5]_i_2_n_0\ : STD_LOGIC;
  signal \fine_inc[5][5]_i_3_n_0\ : STD_LOGIC;
  signal \fine_inc[6][0]_i_1_n_0\ : STD_LOGIC;
  signal \fine_inc[6][1]_i_1_n_0\ : STD_LOGIC;
  signal \fine_inc[6][2]_i_1_n_0\ : STD_LOGIC;
  signal \fine_inc[6][3]_i_1_n_0\ : STD_LOGIC;
  signal \fine_inc[6][4]_i_1_n_0\ : STD_LOGIC;
  signal \fine_inc[6][5]_i_1_n_0\ : STD_LOGIC;
  signal \fine_inc[6][5]_i_2_n_0\ : STD_LOGIC;
  signal \fine_inc[6][5]_i_3_n_0\ : STD_LOGIC;
  signal \fine_inc[7][0]_i_1_n_0\ : STD_LOGIC;
  signal \fine_inc[7][1]_i_1_n_0\ : STD_LOGIC;
  signal \fine_inc[7][2]_i_1_n_0\ : STD_LOGIC;
  signal \fine_inc[7][3]_i_1_n_0\ : STD_LOGIC;
  signal \fine_inc[7][4]_i_1_n_0\ : STD_LOGIC;
  signal \fine_inc[7][5]_i_1_n_0\ : STD_LOGIC;
  signal \fine_inc[7][5]_i_2_n_0\ : STD_LOGIC;
  signal \fine_inc[7][5]_i_3_n_0\ : STD_LOGIC;
  signal \fine_inc_reg[0][1]_i_2_n_0\ : STD_LOGIC;
  signal \fine_inc_reg[0][1]_i_3_n_0\ : STD_LOGIC;
  signal \fine_inc_reg[0][2]_i_2_n_0\ : STD_LOGIC;
  signal \fine_inc_reg[0][3]_i_2_n_0\ : STD_LOGIC;
  signal \fine_inc_reg[0][5]_i_7_n_0\ : STD_LOGIC;
  signal \fine_inc_reg[0][5]_i_9_n_0\ : STD_LOGIC;
  signal \fine_inc_reg[0]_5\ : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal \fine_inc_reg[1]_6\ : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal \fine_inc_reg[2]_7\ : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal \fine_inc_reg[3]_8\ : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal \fine_inc_reg[4]_9\ : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal \fine_inc_reg[5]_10\ : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal \fine_inc_reg[6]_11\ : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal \fine_inc_reg[7]_12\ : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal flag_ck_negedge09_out : STD_LOGIC;
  signal flag_ck_negedge_i_1_n_0 : STD_LOGIC;
  signal flag_ck_negedge_i_2_n_0 : STD_LOGIC;
  signal flag_ck_negedge_i_4_n_0 : STD_LOGIC;
  signal flag_ck_negedge_i_5_n_0 : STD_LOGIC;
  signal flag_ck_negedge_i_6_n_0 : STD_LOGIC;
  signal flag_ck_negedge_reg_n_0 : STD_LOGIC;
  signal flag_init : STD_LOGIC;
  signal flag_init_i_1_n_0 : STD_LOGIC;
  signal flag_init_i_2_n_0 : STD_LOGIC;
  signal \gen_final_tap[0].final_val[0][5]_i_1_n_0\ : STD_LOGIC;
  signal \gen_final_tap[0].final_val_reg_n_0_[0][0]\ : STD_LOGIC;
  signal \gen_final_tap[0].final_val_reg_n_0_[0][1]\ : STD_LOGIC;
  signal \gen_final_tap[0].final_val_reg_n_0_[0][2]\ : STD_LOGIC;
  signal \gen_final_tap[0].final_val_reg_n_0_[0][3]\ : STD_LOGIC;
  signal \gen_final_tap[0].final_val_reg_n_0_[0][4]\ : STD_LOGIC;
  signal \gen_final_tap[0].final_val_reg_n_0_[0][5]\ : STD_LOGIC;
  signal \gen_final_tap[1].final_val_reg_n_0_[1][0]\ : STD_LOGIC;
  signal \gen_final_tap[1].final_val_reg_n_0_[1][1]\ : STD_LOGIC;
  signal \gen_final_tap[1].final_val_reg_n_0_[1][2]\ : STD_LOGIC;
  signal \gen_final_tap[1].final_val_reg_n_0_[1][3]\ : STD_LOGIC;
  signal \gen_final_tap[1].final_val_reg_n_0_[1][4]\ : STD_LOGIC;
  signal \gen_final_tap[1].final_val_reg_n_0_[1][5]\ : STD_LOGIC;
  signal \gen_final_tap[2].final_val_reg_n_0_[2][0]\ : STD_LOGIC;
  signal \gen_final_tap[2].final_val_reg_n_0_[2][1]\ : STD_LOGIC;
  signal \gen_final_tap[2].final_val_reg_n_0_[2][2]\ : STD_LOGIC;
  signal \gen_final_tap[2].final_val_reg_n_0_[2][3]\ : STD_LOGIC;
  signal \gen_final_tap[2].final_val_reg_n_0_[2][4]\ : STD_LOGIC;
  signal \gen_final_tap[2].final_val_reg_n_0_[2][5]\ : STD_LOGIC;
  signal \gen_final_tap[3].final_val_reg_n_0_[3][0]\ : STD_LOGIC;
  signal \gen_final_tap[3].final_val_reg_n_0_[3][1]\ : STD_LOGIC;
  signal \gen_final_tap[3].final_val_reg_n_0_[3][2]\ : STD_LOGIC;
  signal \gen_final_tap[3].final_val_reg_n_0_[3][3]\ : STD_LOGIC;
  signal \gen_final_tap[3].final_val_reg_n_0_[3][4]\ : STD_LOGIC;
  signal \gen_final_tap[3].final_val_reg_n_0_[3][5]\ : STD_LOGIC;
  signal \gen_final_tap[4].final_val_reg_n_0_[4][0]\ : STD_LOGIC;
  signal \gen_final_tap[4].final_val_reg_n_0_[4][1]\ : STD_LOGIC;
  signal \gen_final_tap[4].final_val_reg_n_0_[4][2]\ : STD_LOGIC;
  signal \gen_final_tap[4].final_val_reg_n_0_[4][3]\ : STD_LOGIC;
  signal \gen_final_tap[4].final_val_reg_n_0_[4][4]\ : STD_LOGIC;
  signal \gen_final_tap[4].final_val_reg_n_0_[4][5]\ : STD_LOGIC;
  signal \gen_final_tap[5].final_val_reg_n_0_[5][0]\ : STD_LOGIC;
  signal \gen_final_tap[5].final_val_reg_n_0_[5][1]\ : STD_LOGIC;
  signal \gen_final_tap[5].final_val_reg_n_0_[5][2]\ : STD_LOGIC;
  signal \gen_final_tap[5].final_val_reg_n_0_[5][3]\ : STD_LOGIC;
  signal \gen_final_tap[5].final_val_reg_n_0_[5][4]\ : STD_LOGIC;
  signal \gen_final_tap[5].final_val_reg_n_0_[5][5]\ : STD_LOGIC;
  signal \gen_final_tap[6].final_val_reg_n_0_[6][0]\ : STD_LOGIC;
  signal \gen_final_tap[6].final_val_reg_n_0_[6][1]\ : STD_LOGIC;
  signal \gen_final_tap[6].final_val_reg_n_0_[6][2]\ : STD_LOGIC;
  signal \gen_final_tap[6].final_val_reg_n_0_[6][3]\ : STD_LOGIC;
  signal \gen_final_tap[6].final_val_reg_n_0_[6][4]\ : STD_LOGIC;
  signal \gen_final_tap[6].final_val_reg_n_0_[6][5]\ : STD_LOGIC;
  signal \gen_final_tap[7].final_val_reg_n_0_[7][0]\ : STD_LOGIC;
  signal \gen_final_tap[7].final_val_reg_n_0_[7][1]\ : STD_LOGIC;
  signal \gen_final_tap[7].final_val_reg_n_0_[7][2]\ : STD_LOGIC;
  signal \gen_final_tap[7].final_val_reg_n_0_[7][3]\ : STD_LOGIC;
  signal \gen_final_tap[7].final_val_reg_n_0_[7][4]\ : STD_LOGIC;
  signal \gen_final_tap[7].final_val_reg_n_0_[7][5]\ : STD_LOGIC;
  signal \gen_rd[0].rd_data_rise_wl_r_reg_n_0_[0]\ : STD_LOGIC;
  signal \gen_rd[1].rd_data_rise_wl_r_reg_n_0_[1]\ : STD_LOGIC;
  signal \gen_rd[2].rd_data_rise_wl_r_reg_n_0_[2]\ : STD_LOGIC;
  signal \gen_rd[3].rd_data_rise_wl_r_reg_n_0_[3]\ : STD_LOGIC;
  signal \gen_rd[4].rd_data_rise_wl_r_reg_n_0_[4]\ : STD_LOGIC;
  signal \gen_rd[5].rd_data_rise_wl_r_reg_n_0_[5]\ : STD_LOGIC;
  signal \gen_rd[6].rd_data_rise_wl_r_reg_n_0_[6]\ : STD_LOGIC;
  signal \gen_rd[7].rd_data_rise_wl_r_reg_n_0_[7]\ : STD_LOGIC;
  signal \incdec_wait_cnt[3]_i_1_n_0\ : STD_LOGIC;
  signal incdec_wait_cnt_reg : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal inhibit_edge_detect_r_i_1_n_0 : STD_LOGIC;
  signal inhibit_edge_detect_r_i_2_n_0 : STD_LOGIC;
  signal inhibit_edge_detect_r_i_3_n_0 : STD_LOGIC;
  signal inhibit_edge_detect_r_i_4_n_0 : STD_LOGIC;
  signal inhibit_edge_detect_r_i_5_n_0 : STD_LOGIC;
  signal inhibit_edge_detect_r_reg_n_0 : STD_LOGIC;
  signal largest : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal p_0_in : STD_LOGIC;
  signal \p_0_in__0\ : STD_LOGIC;
  signal \p_0_in__1\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \p_0_in__2\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \p_0_out_inferred__18/gen_rd[0].rd_data_rise_wl_r[0]_i_2_n_0\ : STD_LOGIC;
  signal \p_0_out_inferred__19/gen_rd[1].rd_data_rise_wl_r[1]_i_1_n_0\ : STD_LOGIC;
  signal \p_0_out_inferred__19/gen_rd[1].rd_data_rise_wl_r[1]_i_2_n_0\ : STD_LOGIC;
  signal \p_0_out_inferred__20/gen_rd[2].rd_data_rise_wl_r[2]_i_1_n_0\ : STD_LOGIC;
  signal \p_0_out_inferred__20/gen_rd[2].rd_data_rise_wl_r[2]_i_2_n_0\ : STD_LOGIC;
  signal \p_0_out_inferred__21/gen_rd[3].rd_data_rise_wl_r[3]_i_1_n_0\ : STD_LOGIC;
  signal \p_0_out_inferred__21/gen_rd[3].rd_data_rise_wl_r[3]_i_2_n_0\ : STD_LOGIC;
  signal \p_0_out_inferred__22/gen_rd[4].rd_data_rise_wl_r[4]_i_1_n_0\ : STD_LOGIC;
  signal \p_0_out_inferred__22/gen_rd[4].rd_data_rise_wl_r[4]_i_2_n_0\ : STD_LOGIC;
  signal \p_0_out_inferred__23/gen_rd[5].rd_data_rise_wl_r[5]_i_1_n_0\ : STD_LOGIC;
  signal \p_0_out_inferred__23/gen_rd[5].rd_data_rise_wl_r[5]_i_2_n_0\ : STD_LOGIC;
  signal \p_0_out_inferred__24/gen_rd[6].rd_data_rise_wl_r[6]_i_1_n_0\ : STD_LOGIC;
  signal \p_0_out_inferred__24/gen_rd[6].rd_data_rise_wl_r[6]_i_2_n_0\ : STD_LOGIC;
  signal \p_0_out_inferred__25/gen_rd[7].rd_data_rise_wl_r[7]_i_1_n_0\ : STD_LOGIC;
  signal \p_0_out_inferred__25/gen_rd[7].rd_data_rise_wl_r[7]_i_2_n_0\ : STD_LOGIC;
  signal phy_ctl_ready_r4_reg_srl4_n_0 : STD_LOGIC;
  signal phy_ctl_ready_r5 : STD_LOGIC;
  signal phy_ctl_ready_r6_reg_n_0 : STD_LOGIC;
  signal po_cnt_dec_i_1_n_0 : STD_LOGIC;
  signal po_cnt_dec_i_2_n_0 : STD_LOGIC;
  signal \^po_cnt_dec_reg_0\ : STD_LOGIC;
  signal po_dec_done : STD_LOGIC;
  signal po_dec_done_i_1_n_0 : STD_LOGIC;
  signal po_dec_done_i_2_n_0 : STD_LOGIC;
  signal po_rdval_cnt : STD_LOGIC_VECTOR ( 8 downto 0 );
  signal \po_rdval_cnt[0]_i_1_n_0\ : STD_LOGIC;
  signal \po_rdval_cnt[1]_i_1_n_0\ : STD_LOGIC;
  signal \po_rdval_cnt[2]_i_1_n_0\ : STD_LOGIC;
  signal \po_rdval_cnt[3]_i_1_n_0\ : STD_LOGIC;
  signal \po_rdval_cnt[3]_i_3_n_0\ : STD_LOGIC;
  signal \po_rdval_cnt[4]_i_1_n_0\ : STD_LOGIC;
  signal \po_rdval_cnt[4]_i_3_n_0\ : STD_LOGIC;
  signal \po_rdval_cnt[5]_i_1_n_0\ : STD_LOGIC;
  signal \po_rdval_cnt[6]_i_1_n_0\ : STD_LOGIC;
  signal \po_rdval_cnt[6]_i_3_n_0\ : STD_LOGIC;
  signal \po_rdval_cnt[6]_i_4_n_0\ : STD_LOGIC;
  signal \po_rdval_cnt[7]_i_1_n_0\ : STD_LOGIC;
  signal \po_rdval_cnt[8]_i_1_n_0\ : STD_LOGIC;
  signal \po_rdval_cnt[8]_i_2_n_0\ : STD_LOGIC;
  signal \po_rdval_cnt[8]_i_3_n_0\ : STD_LOGIC;
  signal \po_rdval_cnt[8]_i_5_n_0\ : STD_LOGIC;
  signal \po_rdval_cnt[8]_i_6_n_0\ : STD_LOGIC;
  signal po_stg2_cincdec : STD_LOGIC_VECTOR ( 2 to 2 );
  signal \^po_stg2_wrcal_cnt_reg[2]\ : STD_LOGIC;
  signal \^po_stg2_wrcal_cnt_reg[2]_0\ : STD_LOGIC;
  signal \rank_cnt_r[0]_i_1_n_0\ : STD_LOGIC;
  signal \rank_cnt_r[1]_i_1_n_0\ : STD_LOGIC;
  signal \rank_cnt_r[1]_i_2_n_0\ : STD_LOGIC;
  signal \rank_cnt_r_reg_n_0_[0]\ : STD_LOGIC;
  signal \rank_cnt_r_reg_n_0_[1]\ : STD_LOGIC;
  signal rd_data_edge_detect_r0 : STD_LOGIC;
  signal \rd_data_edge_detect_r[0]_i_1_n_0\ : STD_LOGIC;
  signal \rd_data_edge_detect_r[1]_i_1_n_0\ : STD_LOGIC;
  signal \rd_data_edge_detect_r[2]_i_1_n_0\ : STD_LOGIC;
  signal \rd_data_edge_detect_r[3]_i_1_n_0\ : STD_LOGIC;
  signal \rd_data_edge_detect_r[4]_i_1_n_0\ : STD_LOGIC;
  signal \rd_data_edge_detect_r[5]_i_1_n_0\ : STD_LOGIC;
  signal \rd_data_edge_detect_r[6]_i_1_n_0\ : STD_LOGIC;
  signal \rd_data_edge_detect_r[7]_i_10_n_0\ : STD_LOGIC;
  signal \rd_data_edge_detect_r[7]_i_11_n_0\ : STD_LOGIC;
  signal \rd_data_edge_detect_r[7]_i_2_n_0\ : STD_LOGIC;
  signal \rd_data_edge_detect_r[7]_i_3_n_0\ : STD_LOGIC;
  signal \rd_data_edge_detect_r[7]_i_4_n_0\ : STD_LOGIC;
  signal \rd_data_edge_detect_r[7]_i_6_n_0\ : STD_LOGIC;
  signal \rd_data_edge_detect_r[7]_i_7_n_0\ : STD_LOGIC;
  signal \rd_data_edge_detect_r[7]_i_8_n_0\ : STD_LOGIC;
  signal \rd_data_edge_detect_r_reg[7]_i_5_n_0\ : STD_LOGIC;
  signal \rd_data_edge_detect_r_reg[7]_i_9_n_0\ : STD_LOGIC;
  signal \rd_data_edge_detect_r_reg_n_0_[0]\ : STD_LOGIC;
  signal \rd_data_edge_detect_r_reg_n_0_[1]\ : STD_LOGIC;
  signal \rd_data_edge_detect_r_reg_n_0_[2]\ : STD_LOGIC;
  signal \rd_data_edge_detect_r_reg_n_0_[3]\ : STD_LOGIC;
  signal \rd_data_edge_detect_r_reg_n_0_[4]\ : STD_LOGIC;
  signal \rd_data_edge_detect_r_reg_n_0_[5]\ : STD_LOGIC;
  signal \rd_data_edge_detect_r_reg_n_0_[6]\ : STD_LOGIC;
  signal \rd_data_edge_detect_r_reg_n_0_[7]\ : STD_LOGIC;
  signal rd_data_previous_r0 : STD_LOGIC;
  signal \rd_data_previous_r[7]_i_2_n_0\ : STD_LOGIC;
  signal \rd_data_previous_r[7]_i_3_n_0\ : STD_LOGIC;
  signal \rd_data_previous_r[7]_i_4_n_0\ : STD_LOGIC;
  signal \rd_data_previous_r[7]_i_5_n_0\ : STD_LOGIC;
  signal \rd_data_previous_r_reg_n_0_[0]\ : STD_LOGIC;
  signal \rd_data_previous_r_reg_n_0_[1]\ : STD_LOGIC;
  signal \rd_data_previous_r_reg_n_0_[2]\ : STD_LOGIC;
  signal \rd_data_previous_r_reg_n_0_[3]\ : STD_LOGIC;
  signal \rd_data_previous_r_reg_n_0_[4]\ : STD_LOGIC;
  signal \rd_data_previous_r_reg_n_0_[5]\ : STD_LOGIC;
  signal \rd_data_previous_r_reg_n_0_[6]\ : STD_LOGIC;
  signal \rd_data_previous_r_reg_n_0_[7]\ : STD_LOGIC;
  signal \single_rank.done_dqs_dec_i_1_n_0\ : STD_LOGIC;
  signal \smallest[0][0]_i_3_n_0\ : STD_LOGIC;
  signal \smallest[0][0]_i_4_n_0\ : STD_LOGIC;
  signal \smallest[0][1]_i_3_n_0\ : STD_LOGIC;
  signal \smallest[0][1]_i_4_n_0\ : STD_LOGIC;
  signal \smallest[0][2]_i_3_n_0\ : STD_LOGIC;
  signal \smallest[0][2]_i_4_n_0\ : STD_LOGIC;
  signal \smallest[0][3]_i_3_n_0\ : STD_LOGIC;
  signal \smallest[0][3]_i_4_n_0\ : STD_LOGIC;
  signal \smallest[0][4]_i_3_n_0\ : STD_LOGIC;
  signal \smallest[0][4]_i_4_n_0\ : STD_LOGIC;
  signal \smallest[0][5]_i_1_n_0\ : STD_LOGIC;
  signal \smallest[0][5]_i_3_n_0\ : STD_LOGIC;
  signal \smallest[0][5]_i_5_n_0\ : STD_LOGIC;
  signal \smallest[0][5]_i_6_n_0\ : STD_LOGIC;
  signal \smallest[1][0]_i_1_n_0\ : STD_LOGIC;
  signal \smallest[1][1]_i_1_n_0\ : STD_LOGIC;
  signal \smallest[1][2]_i_1_n_0\ : STD_LOGIC;
  signal \smallest[1][3]_i_1_n_0\ : STD_LOGIC;
  signal \smallest[1][4]_i_1_n_0\ : STD_LOGIC;
  signal \smallest[1][5]_i_1_n_0\ : STD_LOGIC;
  signal \smallest[1][5]_i_2_n_0\ : STD_LOGIC;
  signal \smallest[2][0]_i_1_n_0\ : STD_LOGIC;
  signal \smallest[2][1]_i_1_n_0\ : STD_LOGIC;
  signal \smallest[2][2]_i_1_n_0\ : STD_LOGIC;
  signal \smallest[2][3]_i_1_n_0\ : STD_LOGIC;
  signal \smallest[2][4]_i_1_n_0\ : STD_LOGIC;
  signal \smallest[2][5]_i_1_n_0\ : STD_LOGIC;
  signal \smallest[2][5]_i_2_n_0\ : STD_LOGIC;
  signal \smallest[3][0]_i_1_n_0\ : STD_LOGIC;
  signal \smallest[3][1]_i_1_n_0\ : STD_LOGIC;
  signal \smallest[3][2]_i_1_n_0\ : STD_LOGIC;
  signal \smallest[3][3]_i_1_n_0\ : STD_LOGIC;
  signal \smallest[3][4]_i_1_n_0\ : STD_LOGIC;
  signal \smallest[3][5]_i_1_n_0\ : STD_LOGIC;
  signal \smallest[3][5]_i_2_n_0\ : STD_LOGIC;
  signal \smallest[4][0]_i_1_n_0\ : STD_LOGIC;
  signal \smallest[4][1]_i_1_n_0\ : STD_LOGIC;
  signal \smallest[4][2]_i_1_n_0\ : STD_LOGIC;
  signal \smallest[4][3]_i_1_n_0\ : STD_LOGIC;
  signal \smallest[4][4]_i_1_n_0\ : STD_LOGIC;
  signal \smallest[4][5]_i_1_n_0\ : STD_LOGIC;
  signal \smallest[4][5]_i_2_n_0\ : STD_LOGIC;
  signal \smallest[5][0]_i_1_n_0\ : STD_LOGIC;
  signal \smallest[5][1]_i_1_n_0\ : STD_LOGIC;
  signal \smallest[5][2]_i_1_n_0\ : STD_LOGIC;
  signal \smallest[5][3]_i_1_n_0\ : STD_LOGIC;
  signal \smallest[5][4]_i_1_n_0\ : STD_LOGIC;
  signal \smallest[5][5]_i_1_n_0\ : STD_LOGIC;
  signal \smallest[5][5]_i_2_n_0\ : STD_LOGIC;
  signal \smallest[6][0]_i_1_n_0\ : STD_LOGIC;
  signal \smallest[6][1]_i_1_n_0\ : STD_LOGIC;
  signal \smallest[6][2]_i_1_n_0\ : STD_LOGIC;
  signal \smallest[6][3]_i_1_n_0\ : STD_LOGIC;
  signal \smallest[6][4]_i_1_n_0\ : STD_LOGIC;
  signal \smallest[6][5]_i_1_n_0\ : STD_LOGIC;
  signal \smallest[6][5]_i_2_n_0\ : STD_LOGIC;
  signal \smallest[7][0]_i_1_n_0\ : STD_LOGIC;
  signal \smallest[7][1]_i_1_n_0\ : STD_LOGIC;
  signal \smallest[7][2]_i_1_n_0\ : STD_LOGIC;
  signal \smallest[7][3]_i_1_n_0\ : STD_LOGIC;
  signal \smallest[7][4]_i_1_n_0\ : STD_LOGIC;
  signal \smallest[7][5]_i_1_n_0\ : STD_LOGIC;
  signal \smallest[7][5]_i_2_n_0\ : STD_LOGIC;
  signal \smallest_reg[0][0]_i_2_n_0\ : STD_LOGIC;
  signal \smallest_reg[0][1]_i_2_n_0\ : STD_LOGIC;
  signal \smallest_reg[0][2]_i_2_n_0\ : STD_LOGIC;
  signal \smallest_reg[0][3]_i_2_n_0\ : STD_LOGIC;
  signal \smallest_reg[0][4]_i_2_n_0\ : STD_LOGIC;
  signal \smallest_reg[0][5]_i_4_n_0\ : STD_LOGIC;
  signal \smallest_reg[0]_13\ : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal \smallest_reg[1]_14\ : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal \smallest_reg[2]_15\ : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal \smallest_reg[3]_16\ : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal \smallest_reg[4]_17\ : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal \smallest_reg[5]_18\ : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal \smallest_reg[6]_19\ : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal \smallest_reg[7]_20\ : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal stable_cnt : STD_LOGIC;
  signal stable_cnt0 : STD_LOGIC;
  signal \stable_cnt[3]_i_4_n_0\ : STD_LOGIC;
  signal \stable_cnt[3]_i_5_n_0\ : STD_LOGIC;
  signal \stable_cnt[3]_i_6_n_0\ : STD_LOGIC;
  signal \stable_cnt[3]_i_7_n_0\ : STD_LOGIC;
  signal \stable_cnt[3]_i_8_n_0\ : STD_LOGIC;
  signal \stable_cnt[3]_i_9_n_0\ : STD_LOGIC;
  signal \stable_cnt_reg_n_0_[0]\ : STD_LOGIC;
  signal \stable_cnt_reg_n_0_[1]\ : STD_LOGIC;
  signal \stable_cnt_reg_n_0_[2]\ : STD_LOGIC;
  signal \stable_cnt_reg_n_0_[3]\ : STD_LOGIC;
  signal wait_cnt0 : STD_LOGIC;
  signal \wait_cnt0__0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \wait_cnt[1]_i_1_n_0\ : STD_LOGIC;
  signal wait_cnt_reg : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal wl_corse_cnt : STD_LOGIC;
  signal \wl_corse_cnt[0][0][0]_i_2_n_0\ : STD_LOGIC;
  signal \wl_corse_cnt[0][0][0]_i_3_n_0\ : STD_LOGIC;
  signal \wl_corse_cnt[0][0][1]_i_2_n_0\ : STD_LOGIC;
  signal \wl_corse_cnt[0][0][1]_i_3_n_0\ : STD_LOGIC;
  signal \wl_corse_cnt[0][0][2]_i_2_n_0\ : STD_LOGIC;
  signal \wl_corse_cnt[0][0][2]_i_3_n_0\ : STD_LOGIC;
  signal \wl_corse_cnt_reg[0][0][0]_i_1_n_0\ : STD_LOGIC;
  signal \wl_corse_cnt_reg[0][0][1]_i_1_n_0\ : STD_LOGIC;
  signal \wl_corse_cnt_reg[0][0][2]_i_1_n_0\ : STD_LOGIC;
  signal \wl_corse_cnt_reg[0][0]_29\ : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal \wl_corse_cnt_reg[0][1]_30\ : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal \wl_corse_cnt_reg[0][2]_31\ : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal \wl_corse_cnt_reg[0][3]_32\ : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal \wl_corse_cnt_reg[0][4]_33\ : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal \wl_corse_cnt_reg[0][5]_34\ : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal \wl_corse_cnt_reg[0][6]_35\ : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal \wl_corse_cnt_reg[0][7]_36\ : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal \wl_dqs_tap_count_r[0][0][5]_i_2_n_0\ : STD_LOGIC;
  signal \wl_dqs_tap_count_r[0][0][5]_i_3_n_0\ : STD_LOGIC;
  signal \wl_dqs_tap_count_r[0][1][5]_i_1_n_0\ : STD_LOGIC;
  signal \wl_dqs_tap_count_r[0][2][5]_i_1_n_0\ : STD_LOGIC;
  signal \wl_dqs_tap_count_r[0][3][5]_i_1_n_0\ : STD_LOGIC;
  signal \wl_dqs_tap_count_r[0][4][5]_i_1_n_0\ : STD_LOGIC;
  signal \wl_dqs_tap_count_r[0][5][5]_i_1_n_0\ : STD_LOGIC;
  signal \wl_dqs_tap_count_r[0][6][5]_i_1_n_0\ : STD_LOGIC;
  signal \wl_dqs_tap_count_r[0][7][5]_i_1_n_0\ : STD_LOGIC;
  signal \wl_dqs_tap_count_r_reg_n_0_[0][0][0]\ : STD_LOGIC;
  signal \wl_dqs_tap_count_r_reg_n_0_[0][0][1]\ : STD_LOGIC;
  signal \wl_dqs_tap_count_r_reg_n_0_[0][0][2]\ : STD_LOGIC;
  signal \wl_dqs_tap_count_r_reg_n_0_[0][0][3]\ : STD_LOGIC;
  signal \wl_dqs_tap_count_r_reg_n_0_[0][0][4]\ : STD_LOGIC;
  signal \wl_dqs_tap_count_r_reg_n_0_[0][0][5]\ : STD_LOGIC;
  signal \wl_dqs_tap_count_r_reg_n_0_[0][1][0]\ : STD_LOGIC;
  signal \wl_dqs_tap_count_r_reg_n_0_[0][1][1]\ : STD_LOGIC;
  signal \wl_dqs_tap_count_r_reg_n_0_[0][1][2]\ : STD_LOGIC;
  signal \wl_dqs_tap_count_r_reg_n_0_[0][1][3]\ : STD_LOGIC;
  signal \wl_dqs_tap_count_r_reg_n_0_[0][1][4]\ : STD_LOGIC;
  signal \wl_dqs_tap_count_r_reg_n_0_[0][1][5]\ : STD_LOGIC;
  signal \wl_dqs_tap_count_r_reg_n_0_[0][2][0]\ : STD_LOGIC;
  signal \wl_dqs_tap_count_r_reg_n_0_[0][2][1]\ : STD_LOGIC;
  signal \wl_dqs_tap_count_r_reg_n_0_[0][2][2]\ : STD_LOGIC;
  signal \wl_dqs_tap_count_r_reg_n_0_[0][2][3]\ : STD_LOGIC;
  signal \wl_dqs_tap_count_r_reg_n_0_[0][2][4]\ : STD_LOGIC;
  signal \wl_dqs_tap_count_r_reg_n_0_[0][2][5]\ : STD_LOGIC;
  signal \wl_dqs_tap_count_r_reg_n_0_[0][3][0]\ : STD_LOGIC;
  signal \wl_dqs_tap_count_r_reg_n_0_[0][3][1]\ : STD_LOGIC;
  signal \wl_dqs_tap_count_r_reg_n_0_[0][3][2]\ : STD_LOGIC;
  signal \wl_dqs_tap_count_r_reg_n_0_[0][3][3]\ : STD_LOGIC;
  signal \wl_dqs_tap_count_r_reg_n_0_[0][3][4]\ : STD_LOGIC;
  signal \wl_dqs_tap_count_r_reg_n_0_[0][3][5]\ : STD_LOGIC;
  signal \wl_dqs_tap_count_r_reg_n_0_[0][4][0]\ : STD_LOGIC;
  signal \wl_dqs_tap_count_r_reg_n_0_[0][4][1]\ : STD_LOGIC;
  signal \wl_dqs_tap_count_r_reg_n_0_[0][4][2]\ : STD_LOGIC;
  signal \wl_dqs_tap_count_r_reg_n_0_[0][4][3]\ : STD_LOGIC;
  signal \wl_dqs_tap_count_r_reg_n_0_[0][4][4]\ : STD_LOGIC;
  signal \wl_dqs_tap_count_r_reg_n_0_[0][4][5]\ : STD_LOGIC;
  signal \wl_dqs_tap_count_r_reg_n_0_[0][5][0]\ : STD_LOGIC;
  signal \wl_dqs_tap_count_r_reg_n_0_[0][5][1]\ : STD_LOGIC;
  signal \wl_dqs_tap_count_r_reg_n_0_[0][5][2]\ : STD_LOGIC;
  signal \wl_dqs_tap_count_r_reg_n_0_[0][5][3]\ : STD_LOGIC;
  signal \wl_dqs_tap_count_r_reg_n_0_[0][5][4]\ : STD_LOGIC;
  signal \wl_dqs_tap_count_r_reg_n_0_[0][5][5]\ : STD_LOGIC;
  signal \wl_dqs_tap_count_r_reg_n_0_[0][6][0]\ : STD_LOGIC;
  signal \wl_dqs_tap_count_r_reg_n_0_[0][6][1]\ : STD_LOGIC;
  signal \wl_dqs_tap_count_r_reg_n_0_[0][6][2]\ : STD_LOGIC;
  signal \wl_dqs_tap_count_r_reg_n_0_[0][6][3]\ : STD_LOGIC;
  signal \wl_dqs_tap_count_r_reg_n_0_[0][6][4]\ : STD_LOGIC;
  signal \wl_dqs_tap_count_r_reg_n_0_[0][6][5]\ : STD_LOGIC;
  signal \wl_dqs_tap_count_r_reg_n_0_[0][7][0]\ : STD_LOGIC;
  signal \wl_dqs_tap_count_r_reg_n_0_[0][7][1]\ : STD_LOGIC;
  signal \wl_dqs_tap_count_r_reg_n_0_[0][7][2]\ : STD_LOGIC;
  signal \wl_dqs_tap_count_r_reg_n_0_[0][7][3]\ : STD_LOGIC;
  signal \wl_dqs_tap_count_r_reg_n_0_[0][7][4]\ : STD_LOGIC;
  signal \wl_dqs_tap_count_r_reg_n_0_[0][7][5]\ : STD_LOGIC;
  signal wl_edge_detect_valid_r_i_1_n_0 : STD_LOGIC;
  signal wl_edge_detect_valid_r_reg_n_0 : STD_LOGIC;
  signal \wl_state_r1[0]_i_1_n_0\ : STD_LOGIC;
  signal \wl_state_r1[1]_i_1_n_0\ : STD_LOGIC;
  signal \wl_state_r1[2]_i_1_n_0\ : STD_LOGIC;
  signal \wl_state_r1[3]_i_1_n_0\ : STD_LOGIC;
  signal \wl_state_r1[4]_i_1_n_0\ : STD_LOGIC;
  signal \wl_state_r1_reg_n_0_[0]\ : STD_LOGIC;
  signal \wl_state_r1_reg_n_0_[1]\ : STD_LOGIC;
  signal \wl_state_r1_reg_n_0_[2]\ : STD_LOGIC;
  signal \wl_state_r1_reg_n_0_[3]\ : STD_LOGIC;
  signal \wl_state_r1_reg_n_0_[4]\ : STD_LOGIC;
  signal \wl_state_r__0\ : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal wl_tap_count_r : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal \wl_tap_count_r[0]_i_3_n_0\ : STD_LOGIC;
  signal \wl_tap_count_r[0]_i_4_n_0\ : STD_LOGIC;
  signal \wl_tap_count_r[1]_i_3_n_0\ : STD_LOGIC;
  signal \wl_tap_count_r[1]_i_4_n_0\ : STD_LOGIC;
  signal \wl_tap_count_r[2]_i_2_n_0\ : STD_LOGIC;
  signal \wl_tap_count_r[2]_i_4_n_0\ : STD_LOGIC;
  signal \wl_tap_count_r[2]_i_5_n_0\ : STD_LOGIC;
  signal \wl_tap_count_r[3]_i_3_n_0\ : STD_LOGIC;
  signal \wl_tap_count_r[3]_i_4_n_0\ : STD_LOGIC;
  signal \wl_tap_count_r[3]_i_5_n_0\ : STD_LOGIC;
  signal \wl_tap_count_r[4]_i_2_n_0\ : STD_LOGIC;
  signal \wl_tap_count_r[4]_i_3_n_0\ : STD_LOGIC;
  signal \wl_tap_count_r[4]_i_4_n_0\ : STD_LOGIC;
  signal \wl_tap_count_r[4]_i_6_n_0\ : STD_LOGIC;
  signal \wl_tap_count_r[4]_i_7_n_0\ : STD_LOGIC;
  signal \wl_tap_count_r[5]_i_1_n_0\ : STD_LOGIC;
  signal \wl_tap_count_r[5]_i_4_n_0\ : STD_LOGIC;
  signal \wl_tap_count_r[5]_i_6_n_0\ : STD_LOGIC;
  signal \wl_tap_count_r[5]_i_7_n_0\ : STD_LOGIC;
  signal \wl_tap_count_r_reg[0]_i_2_n_0\ : STD_LOGIC;
  signal \wl_tap_count_r_reg[1]_i_2_n_0\ : STD_LOGIC;
  signal \wl_tap_count_r_reg[2]_i_3_n_0\ : STD_LOGIC;
  signal \wl_tap_count_r_reg[3]_i_2_n_0\ : STD_LOGIC;
  signal \wl_tap_count_r_reg[4]_i_5_n_0\ : STD_LOGIC;
  signal \wl_tap_count_r_reg[5]_i_5_n_0\ : STD_LOGIC;
  signal \wl_tap_count_r_reg_n_0_[0]\ : STD_LOGIC;
  signal \wl_tap_count_r_reg_n_0_[1]\ : STD_LOGIC;
  signal \wl_tap_count_r_reg_n_0_[2]\ : STD_LOGIC;
  signal \wl_tap_count_r_reg_n_0_[3]\ : STD_LOGIC;
  signal \wl_tap_count_r_reg_n_0_[4]\ : STD_LOGIC;
  signal \wl_tap_count_r_reg_n_0_[5]\ : STD_LOGIC;
  signal wr_level_done_i_1_n_0 : STD_LOGIC;
  signal wr_level_done_r1 : STD_LOGIC;
  signal wr_level_done_r2 : STD_LOGIC;
  signal wr_level_done_r3 : STD_LOGIC;
  signal wr_level_done_r4 : STD_LOGIC;
  signal \^wr_level_done_r5\ : STD_LOGIC;
  signal wr_level_done_r_i_1_n_0 : STD_LOGIC;
  signal wr_level_done_r_i_2_n_0 : STD_LOGIC;
  signal wr_level_done_r_reg_n_0 : STD_LOGIC;
  signal wr_level_start_r : STD_LOGIC;
  signal \^wrlvl_byte_done\ : STD_LOGIC;
  signal wrlvl_byte_done_i_1_n_0 : STD_LOGIC;
  signal \^wrlvl_byte_redo_r\ : STD_LOGIC;
  signal \^wrlvl_rank_done\ : STD_LOGIC;
  signal wrlvl_rank_done_r_i_1_n_0 : STD_LOGIC;
  signal wrlvl_rank_done_r_i_2_n_0 : STD_LOGIC;
  signal wrlvl_rank_done_r_i_3_n_0 : STD_LOGIC;
  signal \wrlvl_redo_corse_inc[0]_i_1_n_0\ : STD_LOGIC;
  signal \wrlvl_redo_corse_inc[1]_i_1_n_0\ : STD_LOGIC;
  signal \wrlvl_redo_corse_inc[2]_i_10_n_0\ : STD_LOGIC;
  signal \wrlvl_redo_corse_inc[2]_i_11_n_0\ : STD_LOGIC;
  signal \wrlvl_redo_corse_inc[2]_i_12_n_0\ : STD_LOGIC;
  signal \wrlvl_redo_corse_inc[2]_i_1_n_0\ : STD_LOGIC;
  signal \wrlvl_redo_corse_inc[2]_i_2_n_0\ : STD_LOGIC;
  signal \wrlvl_redo_corse_inc[2]_i_3_n_0\ : STD_LOGIC;
  signal \wrlvl_redo_corse_inc[2]_i_4_n_0\ : STD_LOGIC;
  signal \wrlvl_redo_corse_inc[2]_i_7_n_0\ : STD_LOGIC;
  signal \wrlvl_redo_corse_inc[2]_i_8_n_0\ : STD_LOGIC;
  signal \wrlvl_redo_corse_inc[2]_i_9_n_0\ : STD_LOGIC;
  signal \wrlvl_redo_corse_inc_reg_n_0_[0]\ : STD_LOGIC;
  signal \wrlvl_redo_corse_inc_reg_n_0_[1]\ : STD_LOGIC;
  signal \wrlvl_redo_corse_inc_reg_n_0_[2]\ : STD_LOGIC;
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \FSM_sequential_wl_state_r[0]_i_11\ : label is "soft_lutpair380";
  attribute SOFT_HLUTNM of \FSM_sequential_wl_state_r[0]_i_12\ : label is "soft_lutpair372";
  attribute SOFT_HLUTNM of \FSM_sequential_wl_state_r[0]_i_14\ : label is "soft_lutpair303";
  attribute SOFT_HLUTNM of \FSM_sequential_wl_state_r[0]_i_15\ : label is "soft_lutpair301";
  attribute SOFT_HLUTNM of \FSM_sequential_wl_state_r[0]_i_3\ : label is "soft_lutpair313";
  attribute SOFT_HLUTNM of \FSM_sequential_wl_state_r[0]_i_9\ : label is "soft_lutpair306";
  attribute SOFT_HLUTNM of \FSM_sequential_wl_state_r[1]_i_10\ : label is "soft_lutpair322";
  attribute SOFT_HLUTNM of \FSM_sequential_wl_state_r[1]_i_11\ : label is "soft_lutpair359";
  attribute SOFT_HLUTNM of \FSM_sequential_wl_state_r[1]_i_2\ : label is "soft_lutpair300";
  attribute SOFT_HLUTNM of \FSM_sequential_wl_state_r[1]_i_9\ : label is "soft_lutpair381";
  attribute SOFT_HLUTNM of \FSM_sequential_wl_state_r[2]_i_14\ : label is "soft_lutpair315";
  attribute SOFT_HLUTNM of \FSM_sequential_wl_state_r[2]_i_3\ : label is "soft_lutpair327";
  attribute SOFT_HLUTNM of \FSM_sequential_wl_state_r[2]_i_5\ : label is "soft_lutpair356";
  attribute SOFT_HLUTNM of \FSM_sequential_wl_state_r[2]_i_7\ : label is "soft_lutpair304";
  attribute SOFT_HLUTNM of \FSM_sequential_wl_state_r[2]_i_8\ : label is "soft_lutpair381";
  attribute SOFT_HLUTNM of \FSM_sequential_wl_state_r[3]_i_10\ : label is "soft_lutpair380";
  attribute SOFT_HLUTNM of \FSM_sequential_wl_state_r[3]_i_11\ : label is "soft_lutpair357";
  attribute SOFT_HLUTNM of \FSM_sequential_wl_state_r[3]_i_13\ : label is "soft_lutpair344";
  attribute SOFT_HLUTNM of \FSM_sequential_wl_state_r[3]_i_14\ : label is "soft_lutpair351";
  attribute SOFT_HLUTNM of \FSM_sequential_wl_state_r[3]_i_2\ : label is "soft_lutpair345";
  attribute SOFT_HLUTNM of \FSM_sequential_wl_state_r[3]_i_3\ : label is "soft_lutpair301";
  attribute SOFT_HLUTNM of \FSM_sequential_wl_state_r[3]_i_7\ : label is "soft_lutpair375";
  attribute SOFT_HLUTNM of \FSM_sequential_wl_state_r[4]_i_11\ : label is "soft_lutpair361";
  attribute SOFT_HLUTNM of \FSM_sequential_wl_state_r[4]_i_13\ : label is "soft_lutpair347";
  attribute SOFT_HLUTNM of \FSM_sequential_wl_state_r[4]_i_16\ : label is "soft_lutpair306";
  attribute SOFT_HLUTNM of \FSM_sequential_wl_state_r[4]_i_19\ : label is "soft_lutpair303";
  attribute SOFT_HLUTNM of \FSM_sequential_wl_state_r[4]_i_20\ : label is "soft_lutpair346";
  attribute SOFT_HLUTNM of \FSM_sequential_wl_state_r[4]_i_4\ : label is "soft_lutpair328";
  attribute SOFT_HLUTNM of \FSM_sequential_wl_state_r[4]_i_5\ : label is "soft_lutpair326";
  attribute FSM_ENCODED_STATES : string;
  attribute FSM_ENCODED_STATES of \FSM_sequential_wl_state_r_reg[0]\ : label is "WL_FINE_DEC:00000,WL_2RANK_DQS_CNT:00010,WL_2RANK_TAP_DEC:00100,WL_CORSE_INC_WAIT2:00101,WL_CORSE_INC_WAIT1:00111,WL_INIT_FINE_INC_WAIT1:01000,WL_CORSE_INC_WAIT:01010,WL_INIT_FINE_INC:01100,WL_CORSE_INC_WAIT_TMP:10000,WL_CORSE_INC:01011,WL_FINE_DEC_WAIT1:00001,WL_INIT:10010,WL_FINE_INC_WAIT:10011,WL_CORSE_DEC_WAIT1:10101,WL_DQS_CNT:10100,WL_IDLE:01110,WL_INIT_FINE_DEC_WAIT1:10111,WL_DQS_CHECK:00011,WL_2RANK_FINAL_TAP:01111,WL_FINE_INC:01101,WL_CORSE_DEC_WAIT:11010,WL_INIT_FINE_DEC_WAIT:11000,WL_CORSE_DEC:10110,WL_EDGE_CHECK:11011,WL_WAIT:00110,WL_INIT_FINE_DEC:11001,WL_FINE_DEC_WAIT:10001,WL_INIT_FINE_INC_WAIT:01001";
  attribute FSM_ENCODED_STATES of \FSM_sequential_wl_state_r_reg[1]\ : label is "WL_FINE_DEC:00000,WL_2RANK_DQS_CNT:00010,WL_2RANK_TAP_DEC:00100,WL_CORSE_INC_WAIT2:00101,WL_CORSE_INC_WAIT1:00111,WL_INIT_FINE_INC_WAIT1:01000,WL_CORSE_INC_WAIT:01010,WL_INIT_FINE_INC:01100,WL_CORSE_INC_WAIT_TMP:10000,WL_CORSE_INC:01011,WL_FINE_DEC_WAIT1:00001,WL_INIT:10010,WL_FINE_INC_WAIT:10011,WL_CORSE_DEC_WAIT1:10101,WL_DQS_CNT:10100,WL_IDLE:01110,WL_INIT_FINE_DEC_WAIT1:10111,WL_DQS_CHECK:00011,WL_2RANK_FINAL_TAP:01111,WL_FINE_INC:01101,WL_CORSE_DEC_WAIT:11010,WL_INIT_FINE_DEC_WAIT:11000,WL_CORSE_DEC:10110,WL_EDGE_CHECK:11011,WL_WAIT:00110,WL_INIT_FINE_DEC:11001,WL_FINE_DEC_WAIT:10001,WL_INIT_FINE_INC_WAIT:01001";
  attribute FSM_ENCODED_STATES of \FSM_sequential_wl_state_r_reg[2]\ : label is "WL_FINE_DEC:00000,WL_2RANK_DQS_CNT:00010,WL_2RANK_TAP_DEC:00100,WL_CORSE_INC_WAIT2:00101,WL_CORSE_INC_WAIT1:00111,WL_INIT_FINE_INC_WAIT1:01000,WL_CORSE_INC_WAIT:01010,WL_INIT_FINE_INC:01100,WL_CORSE_INC_WAIT_TMP:10000,WL_CORSE_INC:01011,WL_FINE_DEC_WAIT1:00001,WL_INIT:10010,WL_FINE_INC_WAIT:10011,WL_CORSE_DEC_WAIT1:10101,WL_DQS_CNT:10100,WL_IDLE:01110,WL_INIT_FINE_DEC_WAIT1:10111,WL_DQS_CHECK:00011,WL_2RANK_FINAL_TAP:01111,WL_FINE_INC:01101,WL_CORSE_DEC_WAIT:11010,WL_INIT_FINE_DEC_WAIT:11000,WL_CORSE_DEC:10110,WL_EDGE_CHECK:11011,WL_WAIT:00110,WL_INIT_FINE_DEC:11001,WL_FINE_DEC_WAIT:10001,WL_INIT_FINE_INC_WAIT:01001";
  attribute FSM_ENCODED_STATES of \FSM_sequential_wl_state_r_reg[3]\ : label is "WL_FINE_DEC:00000,WL_2RANK_DQS_CNT:00010,WL_2RANK_TAP_DEC:00100,WL_CORSE_INC_WAIT2:00101,WL_CORSE_INC_WAIT1:00111,WL_INIT_FINE_INC_WAIT1:01000,WL_CORSE_INC_WAIT:01010,WL_INIT_FINE_INC:01100,WL_CORSE_INC_WAIT_TMP:10000,WL_CORSE_INC:01011,WL_FINE_DEC_WAIT1:00001,WL_INIT:10010,WL_FINE_INC_WAIT:10011,WL_CORSE_DEC_WAIT1:10101,WL_DQS_CNT:10100,WL_IDLE:01110,WL_INIT_FINE_DEC_WAIT1:10111,WL_DQS_CHECK:00011,WL_2RANK_FINAL_TAP:01111,WL_FINE_INC:01101,WL_CORSE_DEC_WAIT:11010,WL_INIT_FINE_DEC_WAIT:11000,WL_CORSE_DEC:10110,WL_EDGE_CHECK:11011,WL_WAIT:00110,WL_INIT_FINE_DEC:11001,WL_FINE_DEC_WAIT:10001,WL_INIT_FINE_INC_WAIT:01001";
  attribute FSM_ENCODED_STATES of \FSM_sequential_wl_state_r_reg[4]\ : label is "WL_FINE_DEC:00000,WL_2RANK_DQS_CNT:00010,WL_2RANK_TAP_DEC:00100,WL_CORSE_INC_WAIT2:00101,WL_CORSE_INC_WAIT1:00111,WL_INIT_FINE_INC_WAIT1:01000,WL_CORSE_INC_WAIT:01010,WL_INIT_FINE_INC:01100,WL_CORSE_INC_WAIT_TMP:10000,WL_CORSE_INC:01011,WL_FINE_DEC_WAIT1:00001,WL_INIT:10010,WL_FINE_INC_WAIT:10011,WL_CORSE_DEC_WAIT1:10101,WL_DQS_CNT:10100,WL_IDLE:01110,WL_INIT_FINE_DEC_WAIT1:10111,WL_DQS_CHECK:00011,WL_2RANK_FINAL_TAP:01111,WL_FINE_INC:01101,WL_CORSE_DEC_WAIT:11010,WL_INIT_FINE_DEC_WAIT:11000,WL_CORSE_DEC:10110,WL_EDGE_CHECK:11011,WL_WAIT:00110,WL_INIT_FINE_DEC:11001,WL_FINE_DEC_WAIT:10001,WL_INIT_FINE_INC_WAIT:01001";
  attribute SOFT_HLUTNM of \corse_cnt[0][0]_i_1\ : label is "soft_lutpair366";
  attribute SOFT_HLUTNM of \corse_cnt[0][0]_i_3\ : label is "soft_lutpair304";
  attribute SOFT_HLUTNM of \corse_cnt[0][0]_i_9\ : label is "soft_lutpair346";
  attribute SOFT_HLUTNM of \corse_cnt[0][1]_i_1\ : label is "soft_lutpair367";
  attribute SOFT_HLUTNM of \corse_cnt[0][2]_i_1\ : label is "soft_lutpair365";
  attribute SOFT_HLUTNM of \corse_cnt[0][2]_i_5\ : label is "soft_lutpair375";
  attribute SOFT_HLUTNM of \corse_cnt[0][2]_i_7\ : label is "soft_lutpair356";
  attribute SOFT_HLUTNM of \corse_cnt[0][2]_i_8\ : label is "soft_lutpair300";
  attribute SOFT_HLUTNM of \corse_cnt[1][0]_i_1\ : label is "soft_lutpair368";
  attribute SOFT_HLUTNM of \corse_cnt[1][1]_i_1\ : label is "soft_lutpair367";
  attribute SOFT_HLUTNM of \corse_cnt[1][2]_i_1\ : label is "soft_lutpair365";
  attribute SOFT_HLUTNM of \corse_cnt[2][0]_i_1\ : label is "soft_lutpair366";
  attribute SOFT_HLUTNM of \corse_cnt[2][1]_i_1\ : label is "soft_lutpair370";
  attribute SOFT_HLUTNM of \corse_cnt[2][2]_i_1\ : label is "soft_lutpair373";
  attribute SOFT_HLUTNM of \corse_cnt[3][0]_i_1\ : label is "soft_lutpair368";
  attribute SOFT_HLUTNM of \corse_cnt[3][1]_i_1\ : label is "soft_lutpair377";
  attribute SOFT_HLUTNM of \corse_cnt[3][2]_i_1\ : label is "soft_lutpair373";
  attribute SOFT_HLUTNM of \corse_cnt[4][0]_i_1\ : label is "soft_lutpair369";
  attribute SOFT_HLUTNM of \corse_cnt[4][1]_i_1\ : label is "soft_lutpair379";
  attribute SOFT_HLUTNM of \corse_cnt[4][2]_i_1\ : label is "soft_lutpair376";
  attribute SOFT_HLUTNM of \corse_cnt[5][0]_i_1\ : label is "soft_lutpair369";
  attribute SOFT_HLUTNM of \corse_cnt[5][1]_i_1\ : label is "soft_lutpair379";
  attribute SOFT_HLUTNM of \corse_cnt[5][2]_i_1\ : label is "soft_lutpair378";
  attribute SOFT_HLUTNM of \corse_cnt[6][0]_i_1\ : label is "soft_lutpair374";
  attribute SOFT_HLUTNM of \corse_cnt[6][1]_i_1\ : label is "soft_lutpair377";
  attribute SOFT_HLUTNM of \corse_cnt[6][2]_i_1\ : label is "soft_lutpair378";
  attribute SOFT_HLUTNM of \corse_cnt[7][0]_i_1\ : label is "soft_lutpair374";
  attribute SOFT_HLUTNM of \corse_cnt[7][1]_i_1\ : label is "soft_lutpair370";
  attribute SOFT_HLUTNM of \corse_cnt[7][2]_i_1\ : label is "soft_lutpair376";
  attribute SOFT_HLUTNM of \corse_dec[0][0]_i_2\ : label is "soft_lutpair364";
  attribute SOFT_HLUTNM of \corse_dec[0][2]_i_4\ : label is "soft_lutpair364";
  attribute SOFT_HLUTNM of \corse_dec[0][2]_i_5\ : label is "soft_lutpair331";
  attribute SOFT_HLUTNM of \corse_inc[0][0]_i_2\ : label is "soft_lutpair309";
  attribute SOFT_HLUTNM of \corse_inc[0][2]_i_3\ : label is "soft_lutpair315";
  attribute SOFT_HLUTNM of \corse_inc[0][2]_i_4\ : label is "soft_lutpair358";
  attribute SOFT_HLUTNM of \corse_inc[0][2]_i_5\ : label is "soft_lutpair337";
  attribute SOFT_HLUTNM of \corse_inc[1][0]_i_2\ : label is "soft_lutpair310";
  attribute SOFT_HLUTNM of \corse_inc[2][0]_i_2\ : label is "soft_lutpair311";
  attribute SOFT_HLUTNM of \corse_inc[3][0]_i_2\ : label is "soft_lutpair312";
  attribute SOFT_HLUTNM of \corse_inc[4][0]_i_2\ : label is "soft_lutpair313";
  attribute SOFT_HLUTNM of \ctl_lane_cnt[1]_i_2\ : label is "soft_lutpair348";
  attribute SOFT_HLUTNM of \delaydec_cnt_r[5]_i_1\ : label is "soft_lutpair348";
  attribute SOFT_HLUTNM of dq_cnt_inc_i_2 : label is "soft_lutpair312";
  attribute SOFT_HLUTNM of dq_cnt_inc_i_3 : label is "soft_lutpair331";
  attribute SOFT_HLUTNM of \dqs_count_r[1]_i_3\ : label is "soft_lutpair302";
  attribute SOFT_HLUTNM of \dqs_count_r[1]_i_6\ : label is "soft_lutpair362";
  attribute SOFT_HLUTNM of \dqs_count_r[2]_i_5\ : label is "soft_lutpair323";
  attribute SOFT_HLUTNM of \dqs_count_r[2]_i_6\ : label is "soft_lutpair337";
  attribute SOFT_HLUTNM of \dqs_count_r[2]_i_7\ : label is "soft_lutpair371";
  attribute SOFT_HLUTNM of \dqs_count_r[2]_i_8\ : label is "soft_lutpair355";
  attribute SOFT_HLUTNM of \dqs_count_r[3]_i_10\ : label is "soft_lutpair371";
  attribute SOFT_HLUTNM of \dqs_count_r[3]_i_11\ : label is "soft_lutpair361";
  attribute SOFT_HLUTNM of \dqs_count_r[3]_i_12\ : label is "soft_lutpair358";
  attribute SOFT_HLUTNM of \dqs_count_r[3]_i_4\ : label is "soft_lutpair310";
  attribute SOFT_HLUTNM of \dqs_count_r[3]_i_5\ : label is "soft_lutpair362";
  attribute SOFT_HLUTNM of \dqs_count_r[3]_i_9\ : label is "soft_lutpair345";
  attribute MAX_FANOUT : string;
  attribute MAX_FANOUT of \dqs_count_r_reg[0]\ : label is "50";
  attribute ORIG_CELL_NAME : string;
  attribute ORIG_CELL_NAME of \dqs_count_r_reg[0]\ : label is "dqs_count_r_reg[0]";
  attribute IS_FANOUT_CONSTRAINED : integer;
  attribute IS_FANOUT_CONSTRAINED of \dqs_count_r_reg[0]_rep\ : label is 1;
  attribute MAX_FANOUT of \dqs_count_r_reg[0]_rep\ : label is "50";
  attribute ORIG_CELL_NAME of \dqs_count_r_reg[0]_rep\ : label is "dqs_count_r_reg[0]";
  attribute MAX_FANOUT of \dqs_count_r_reg[1]\ : label is "50";
  attribute ORIG_CELL_NAME of \dqs_count_r_reg[1]\ : label is "dqs_count_r_reg[1]";
  attribute IS_FANOUT_CONSTRAINED of \dqs_count_r_reg[1]_rep\ : label is 1;
  attribute MAX_FANOUT of \dqs_count_r_reg[1]_rep\ : label is "50";
  attribute ORIG_CELL_NAME of \dqs_count_r_reg[1]_rep\ : label is "dqs_count_r_reg[1]";
  attribute MAX_FANOUT of \dqs_count_r_reg[2]\ : label is "50";
  attribute ORIG_CELL_NAME of \dqs_count_r_reg[2]\ : label is "dqs_count_r_reg[2]";
  attribute IS_FANOUT_CONSTRAINED of \dqs_count_r_reg[2]_rep\ : label is 1;
  attribute MAX_FANOUT of \dqs_count_r_reg[2]_rep\ : label is "50";
  attribute ORIG_CELL_NAME of \dqs_count_r_reg[2]_rep\ : label is "dqs_count_r_reg[2]";
  attribute IS_FANOUT_CONSTRAINED of \dqs_count_r_reg[2]_rep__0\ : label is 1;
  attribute MAX_FANOUT of \dqs_count_r_reg[2]_rep__0\ : label is "50";
  attribute ORIG_CELL_NAME of \dqs_count_r_reg[2]_rep__0\ : label is "dqs_count_r_reg[2]";
  attribute MAX_FANOUT of \dqs_count_r_reg[3]\ : label is "50";
  attribute syn_maxfan : string;
  attribute syn_maxfan of dqs_po_dec_done_reg : label is "2";
  attribute SOFT_HLUTNM of dqs_wl_po_stg2_c_incdec_i_1 : label is "soft_lutpair341";
  attribute SOFT_HLUTNM of \fine_dec_cnt[4]_i_2\ : label is "soft_lutpair336";
  attribute SOFT_HLUTNM of \fine_dec_cnt[5]_i_4\ : label is "soft_lutpair344";
  attribute SOFT_HLUTNM of \fine_dec_cnt[5]_i_5\ : label is "soft_lutpair349";
  attribute SOFT_HLUTNM of \fine_dec_cnt[5]_i_7\ : label is "soft_lutpair336";
  attribute SOFT_HLUTNM of \fine_dec_cnt[5]_i_8\ : label is "soft_lutpair335";
  attribute SOFT_HLUTNM of \fine_dec_cnt[5]_i_9\ : label is "soft_lutpair327";
  attribute SOFT_HLUTNM of \fine_inc[0][3]_i_3\ : label is "soft_lutpair299";
  attribute SOFT_HLUTNM of \fine_inc[0][4]_i_1\ : label is "soft_lutpair321";
  attribute SOFT_HLUTNM of \fine_inc[0][4]_i_2\ : label is "soft_lutpair360";
  attribute SOFT_HLUTNM of \fine_inc[0][5]_i_3\ : label is "soft_lutpair299";
  attribute SOFT_HLUTNM of \fine_inc[0][5]_i_4\ : label is "soft_lutpair353";
  attribute SOFT_HLUTNM of \fine_inc[0][5]_i_5\ : label is "soft_lutpair343";
  attribute SOFT_HLUTNM of \fine_inc[0][5]_i_6\ : label is "soft_lutpair307";
  attribute SOFT_HLUTNM of \fine_inc[0][5]_i_8\ : label is "soft_lutpair360";
  attribute SOFT_HLUTNM of \fine_inc[1][4]_i_1\ : label is "soft_lutpair322";
  attribute SOFT_HLUTNM of \fine_inc[1][5]_i_3\ : label is "soft_lutpair353";
  attribute SOFT_HLUTNM of \fine_inc[2][4]_i_1\ : label is "soft_lutpair323";
  attribute SOFT_HLUTNM of \fine_inc[2][5]_i_3\ : label is "soft_lutpair352";
  attribute SOFT_HLUTNM of \fine_inc[3][4]_i_1\ : label is "soft_lutpair324";
  attribute SOFT_HLUTNM of \fine_inc[3][5]_i_3\ : label is "soft_lutpair352";
  attribute SOFT_HLUTNM of \fine_inc[4][5]_i_3\ : label is "soft_lutpair354";
  attribute SOFT_HLUTNM of \fine_inc[5][5]_i_3\ : label is "soft_lutpair354";
  attribute SOFT_HLUTNM of \fine_inc[6][4]_i_1\ : label is "soft_lutpair307";
  attribute SOFT_HLUTNM of \fine_inc[6][5]_i_3\ : label is "soft_lutpair355";
  attribute SOFT_HLUTNM of \fine_inc[7][5]_i_3\ : label is "soft_lutpair302";
  attribute SOFT_HLUTNM of flag_ck_negedge_i_2 : label is "soft_lutpair305";
  attribute SOFT_HLUTNM of flag_ck_negedge_i_5 : label is "soft_lutpair319";
  attribute SOFT_HLUTNM of flag_ck_negedge_i_6 : label is "soft_lutpair319";
  attribute SOFT_HLUTNM of flag_init_i_2 : label is "soft_lutpair333";
  attribute SOFT_HLUTNM of \incdec_wait_cnt[1]_i_1\ : label is "soft_lutpair384";
  attribute SOFT_HLUTNM of \incdec_wait_cnt[2]_i_1\ : label is "soft_lutpair384";
  attribute SOFT_HLUTNM of \incdec_wait_cnt[3]_i_2\ : label is "soft_lutpair347";
  attribute SOFT_HLUTNM of inhibit_edge_detect_r_i_5 : label is "soft_lutpair338";
  attribute SOFT_HLUTNM of phaser_out_i_1 : label is "soft_lutpair329";
  attribute SOFT_HLUTNM of \phaser_out_i_1__0\ : label is "soft_lutpair329";
  attribute SOFT_HLUTNM of \phaser_out_i_1__1\ : label is "soft_lutpair330";
  attribute SOFT_HLUTNM of \phaser_out_i_1__2\ : label is "soft_lutpair330";
  attribute SOFT_HLUTNM of \phaser_out_i_1__3\ : label is "soft_lutpair332";
  attribute SOFT_HLUTNM of \phaser_out_i_1__4\ : label is "soft_lutpair332";
  attribute SOFT_HLUTNM of \phaser_out_i_1__5\ : label is "soft_lutpair339";
  attribute SOFT_HLUTNM of \phaser_out_i_1__6\ : label is "soft_lutpair339";
  attribute SOFT_HLUTNM of \phaser_out_i_1__7\ : label is "soft_lutpair340";
  attribute SOFT_HLUTNM of \phaser_out_i_1__8\ : label is "soft_lutpair340";
  attribute SOFT_HLUTNM of phaser_out_i_2 : label is "soft_lutpair314";
  attribute SOFT_HLUTNM of \phaser_out_i_2__0\ : label is "soft_lutpair314";
  attribute SOFT_HLUTNM of \phaser_out_i_2__1\ : label is "soft_lutpair320";
  attribute SOFT_HLUTNM of \phaser_out_i_2__2\ : label is "soft_lutpair320";
  attribute SOFT_HLUTNM of \phaser_out_i_2__3\ : label is "soft_lutpair317";
  attribute SOFT_HLUTNM of \phaser_out_i_2__4\ : label is "soft_lutpair318";
  attribute SOFT_HLUTNM of \phaser_out_i_2__5\ : label is "soft_lutpair317";
  attribute SOFT_HLUTNM of \phaser_out_i_2__6\ : label is "soft_lutpair318";
  attribute SOFT_HLUTNM of phaser_out_i_3 : label is "soft_lutpair308";
  attribute SOFT_HLUTNM of \phaser_out_i_3__0\ : label is "soft_lutpair308";
  attribute srl_name : string;
  attribute srl_name of phy_ctl_ready_r4_reg_srl4 : label is "\u_mig_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/mb_wrlvl_inst.u_ddr_phy_wrlvl/phy_ctl_ready_r4_reg_srl4 ";
  attribute SOFT_HLUTNM of \po_rdval_cnt[0]_i_1\ : label is "soft_lutpair325";
  attribute SOFT_HLUTNM of \po_rdval_cnt[4]_i_3\ : label is "soft_lutpair316";
  attribute SOFT_HLUTNM of \po_rdval_cnt[6]_i_3\ : label is "soft_lutpair325";
  attribute SOFT_HLUTNM of \po_rdval_cnt[6]_i_4\ : label is "soft_lutpair316";
  attribute SOFT_HLUTNM of \rank_cnt_r[1]_i_2\ : label is "soft_lutpair321";
  attribute SOFT_HLUTNM of \rd_data_edge_detect_r[7]_i_6\ : label is "soft_lutpair351";
  attribute SOFT_HLUTNM of \rd_data_previous_r[7]_i_4\ : label is "soft_lutpair350";
  attribute SOFT_HLUTNM of \rd_data_previous_r[7]_i_5\ : label is "soft_lutpair309";
  attribute SOFT_HLUTNM of \smallest[0][5]_i_3\ : label is "soft_lutpair326";
  attribute SOFT_HLUTNM of \stable_cnt[0]_i_1\ : label is "soft_lutpair305";
  attribute SOFT_HLUTNM of \stable_cnt[1]_i_1\ : label is "soft_lutpair383";
  attribute SOFT_HLUTNM of \stable_cnt[2]_i_1\ : label is "soft_lutpair383";
  attribute SOFT_HLUTNM of \stable_cnt[3]_i_3\ : label is "soft_lutpair349";
  attribute SOFT_HLUTNM of \stable_cnt[3]_i_8\ : label is "soft_lutpair350";
  attribute SOFT_HLUTNM of \stable_cnt[3]_i_9\ : label is "soft_lutpair357";
  attribute SOFT_HLUTNM of \wait_cnt[1]_i_1\ : label is "soft_lutpair382";
  attribute SOFT_HLUTNM of \wait_cnt[2]_i_1\ : label is "soft_lutpair382";
  attribute SOFT_HLUTNM of \wl_dqs_tap_count_r[0][0][5]_i_3\ : label is "soft_lutpair334";
  attribute SOFT_HLUTNM of \wl_state_r1[0]_i_1\ : label is "soft_lutpair342";
  attribute SOFT_HLUTNM of \wl_state_r1[1]_i_1\ : label is "soft_lutpair333";
  attribute SOFT_HLUTNM of \wl_state_r1[2]_i_1\ : label is "soft_lutpair342";
  attribute SOFT_HLUTNM of \wl_state_r1[3]_i_1\ : label is "soft_lutpair343";
  attribute SOFT_HLUTNM of \wl_state_r1[4]_i_1\ : label is "soft_lutpair341";
  attribute SOFT_HLUTNM of \wl_tap_count_r[2]_i_1\ : label is "soft_lutpair335";
  attribute SOFT_HLUTNM of \wl_tap_count_r[3]_i_3\ : label is "soft_lutpair363";
  attribute SOFT_HLUTNM of \wl_tap_count_r[4]_i_2\ : label is "soft_lutpair328";
  attribute SOFT_HLUTNM of \wl_tap_count_r[4]_i_3\ : label is "soft_lutpair363";
  attribute SOFT_HLUTNM of \wl_tap_count_r[4]_i_4\ : label is "soft_lutpair311";
  attribute SOFT_HLUTNM of \wl_tap_count_r[5]_i_2\ : label is "soft_lutpair338";
  attribute SOFT_HLUTNM of wr_level_done_r_i_1 : label is "soft_lutpair334";
  attribute syn_maxfan of wr_level_done_reg : label is "2";
  attribute SOFT_HLUTNM of wrlvl_rank_done_r_i_3 : label is "soft_lutpair324";
  attribute SOFT_HLUTNM of \wrlvl_redo_corse_inc[0]_i_1\ : label is "soft_lutpair372";
  attribute SOFT_HLUTNM of \wrlvl_redo_corse_inc[2]_i_12\ : label is "soft_lutpair359";
begin
  \FSM_sequential_wl_state_r_reg[2]_0\ <= \^fsm_sequential_wl_state_r_reg[2]_0\;
  \FSM_sequential_wl_state_r_reg[4]_0\(1 downto 0) <= \^fsm_sequential_wl_state_r_reg[4]_0\(1 downto 0);
  done_dqs_tap_inc <= \^done_dqs_tap_inc\;
  \dqs_count_r_reg[0]_rep_0\ <= \^dqs_count_r_reg[0]_rep_0\;
  \dqs_count_r_reg[1]_rep_0\ <= \^dqs_count_r_reg[1]_rep_0\;
  \dqs_count_r_reg[2]_rep__0_0\ <= \^dqs_count_r_reg[2]_rep__0_0\;
  \dqs_count_r_reg[3]_0\(0) <= \^dqs_count_r_reg[3]_0\(0);
  dqs_po_dec_done <= \^dqs_po_dec_done\;
  po_cnt_dec_reg_0 <= \^po_cnt_dec_reg_0\;
  \po_stg2_wrcal_cnt_reg[2]\ <= \^po_stg2_wrcal_cnt_reg[2]\;
  \po_stg2_wrcal_cnt_reg[2]_0\ <= \^po_stg2_wrcal_cnt_reg[2]_0\;
  wr_level_done_r5 <= \^wr_level_done_r5\;
  wrlvl_byte_done <= \^wrlvl_byte_done\;
  wrlvl_byte_redo_r <= \^wrlvl_byte_redo_r\;
  wrlvl_rank_done <= \^wrlvl_rank_done\;
\FSM_sequential_wl_state_r[0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000FFFFEAAA"
    )
        port map (
      I0 => \FSM_sequential_wl_state_r[0]_i_2_n_0\,
      I1 => \wl_state_r__0\(1),
      I2 => \FSM_sequential_wl_state_r[0]_i_3_n_0\,
      I3 => \FSM_sequential_wl_state_r[0]_i_4_n_0\,
      I4 => \FSM_sequential_wl_state_r[0]_i_5_n_0\,
      I5 => \FSM_sequential_wl_state_r[0]_i_6_n_0\,
      O => \FSM_sequential_wl_state_r[0]_i_1_n_0\
    );
\FSM_sequential_wl_state_r[0]_i_10\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FA0FFACFFACFFACF"
    )
        port map (
      I0 => \fine_dec_cnt[5]_i_5_n_0\,
      I1 => \FSM_sequential_wl_state_r[4]_i_17_n_0\,
      I2 => \^fsm_sequential_wl_state_r_reg[4]_0\(1),
      I3 => \^fsm_sequential_wl_state_r_reg[4]_0\(0),
      I4 => wrlvl_byte_redo,
      I5 => \FSM_sequential_wl_state_r[2]_i_9_n_0\,
      O => \FSM_sequential_wl_state_r[0]_i_10_n_0\
    );
\FSM_sequential_wl_state_r[0]_i_11\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"BE"
    )
        port map (
      I0 => \wl_state_r__0\(0),
      I1 => \wl_state_r__0\(2),
      I2 => \^fsm_sequential_wl_state_r_reg[4]_0\(1),
      O => \FSM_sequential_wl_state_r[0]_i_11_n_0\
    );
\FSM_sequential_wl_state_r[0]_i_12\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"45"
    )
        port map (
      I0 => \wl_state_r__0\(2),
      I1 => \wl_state_r__0\(0),
      I2 => \FSM_sequential_wl_state_r[4]_i_17_n_0\,
      O => \FSM_sequential_wl_state_r[0]_i_12_n_0\
    );
\FSM_sequential_wl_state_r[0]_i_14\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FF5DFFFF"
    )
        port map (
      I0 => \fine_inc[7][5]_i_3_n_0\,
      I1 => wrlvl_byte_redo,
      I2 => \wl_state_r__0\(0),
      I3 => \wl_state_r__0\(2),
      I4 => \wl_state_r__0\(1),
      O => \FSM_sequential_wl_state_r[0]_i_14_n_0\
    );
\FSM_sequential_wl_state_r[0]_i_15\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"80"
    )
        port map (
      I0 => \wl_tap_count_r_reg_n_0_[3]\,
      I1 => \wl_tap_count_r_reg_n_0_[4]\,
      I2 => \wl_tap_count_r_reg_n_0_[5]\,
      O => \FSM_sequential_wl_state_r[0]_i_15_n_0\
    );
\FSM_sequential_wl_state_r[0]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"2000022200000222"
    )
        port map (
      I0 => \FSM_sequential_wl_state_r[0]_i_7_n_0\,
      I1 => \^fsm_sequential_wl_state_r_reg[4]_0\(1),
      I2 => \wl_state_r__0\(2),
      I3 => \^fsm_sequential_wl_state_r_reg[4]_0\(0),
      I4 => \wl_state_r__0\(0),
      I5 => \^wr_level_done_r5\,
      O => \FSM_sequential_wl_state_r[0]_i_2_n_0\
    );
\FSM_sequential_wl_state_r[0]_i_3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \^fsm_sequential_wl_state_r_reg[4]_0\(1),
      I1 => \wl_state_r__0\(2),
      O => \FSM_sequential_wl_state_r[0]_i_3_n_0\
    );
\FSM_sequential_wl_state_r[0]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"44444F4444444444"
    )
        port map (
      I0 => \FSM_sequential_wl_state_r[0]_i_8_n_0\,
      I1 => \FSM_sequential_wl_state_r[0]_i_9_n_0\,
      I2 => \FSM_sequential_wl_state_r[2]_i_9_n_0\,
      I3 => \rd_data_edge_detect_r[7]_i_4_n_0\,
      I4 => \^fsm_sequential_wl_state_r_reg[4]_0\(0),
      I5 => wrlvl_byte_redo,
      O => \FSM_sequential_wl_state_r[0]_i_4_n_0\
    );
\FSM_sequential_wl_state_r[0]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000F4F400FF"
    )
        port map (
      I0 => \wl_state_r__0\(0),
      I1 => \^fsm_sequential_wl_state_r_reg[4]_0\(0),
      I2 => \FSM_sequential_wl_state_r[0]_i_10_n_0\,
      I3 => \FSM_sequential_wl_state_r[0]_i_11_n_0\,
      I4 => \FSM_sequential_wl_state_r[0]_i_12_n_0\,
      I5 => \wl_state_r__0\(1),
      O => \FSM_sequential_wl_state_r[0]_i_5_n_0\
    );
\FSM_sequential_wl_state_r[0]_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000AA2000"
    )
        port map (
      I0 => \fine_inc[0][5]_i_3_n_0\,
      I1 => \FSM_sequential_wl_state_r_reg[0]_0\,
      I2 => \FSM_sequential_wl_state_r[4]_i_11_n_0\,
      I3 => \^fsm_sequential_wl_state_r_reg[4]_0\(0),
      I4 => \^fsm_sequential_wl_state_r_reg[4]_0\(1),
      I5 => \FSM_sequential_wl_state_r[0]_i_14_n_0\,
      O => \FSM_sequential_wl_state_r[0]_i_6_n_0\
    );
\FSM_sequential_wl_state_r[0]_i_7\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFFBF"
    )
        port map (
      I0 => \wl_state_r__0\(0),
      I1 => \^fsm_sequential_wl_state_r_reg[4]_0\(0),
      I2 => wrlvl_byte_redo,
      I3 => \wrlvl_redo_corse_inc_reg_n_0_[1]\,
      I4 => \wrlvl_redo_corse_inc_reg_n_0_[0]\,
      I5 => \wrlvl_redo_corse_inc_reg_n_0_[2]\,
      O => \FSM_sequential_wl_state_r[0]_i_7_n_0\
    );
\FSM_sequential_wl_state_r[0]_i_8\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000FB00FFFF0000"
    )
        port map (
      I0 => \rd_data_edge_detect_r_reg[7]_i_5_n_0\,
      I1 => wl_edge_detect_valid_r_reg_n_0,
      I2 => \FSM_sequential_wl_state_r[0]_i_15_n_0\,
      I3 => \^fsm_sequential_wl_state_r_reg[4]_0\(0),
      I4 => \wl_state_r__0\(2),
      I5 => \wl_state_r__0\(0),
      O => \FSM_sequential_wl_state_r[0]_i_8_n_0\
    );
\FSM_sequential_wl_state_r[0]_i_9\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFEF0F0"
    )
        port map (
      I0 => \corse_dec_reg[0][2]_i_2_n_0\,
      I1 => \corse_dec_reg[0][2]_i_3_n_0\,
      I2 => \wl_state_r__0\(0),
      I3 => \corse_dec_reg[0][2]_i_10_n_0\,
      I4 => \^fsm_sequential_wl_state_r_reg[4]_0\(0),
      O => \FSM_sequential_wl_state_r[0]_i_9_n_0\
    );
\FSM_sequential_wl_state_r[1]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFF4FFF4FFFFFFF4"
    )
        port map (
      I0 => \FSM_sequential_wl_state_r[1]_i_2_n_0\,
      I1 => \FSM_sequential_wl_state_r[1]_i_3_n_0\,
      I2 => \FSM_sequential_wl_state_r[1]_i_4_n_0\,
      I3 => \FSM_sequential_wl_state_r[1]_i_5_n_0\,
      I4 => \FSM_sequential_wl_state_r[1]_i_6_n_0\,
      I5 => \FSM_sequential_wl_state_r[1]_i_7_n_0\,
      O => \FSM_sequential_wl_state_r[1]_i_1_n_0\
    );
\FSM_sequential_wl_state_r[1]_i_10\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \^fsm_sequential_wl_state_r_reg[4]_0\(1),
      I1 => \wl_state_r__0\(1),
      O => \FSM_sequential_wl_state_r[1]_i_10_n_0\
    );
\FSM_sequential_wl_state_r[1]_i_11\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0100"
    )
        port map (
      I0 => \wrlvl_redo_corse_inc_reg_n_0_[2]\,
      I1 => \wrlvl_redo_corse_inc_reg_n_0_[0]\,
      I2 => \wrlvl_redo_corse_inc_reg_n_0_[1]\,
      I3 => wrlvl_byte_redo,
      O => \FSM_sequential_wl_state_r[1]_i_11_n_0\
    );
\FSM_sequential_wl_state_r[1]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"DD5FDD55"
    )
        port map (
      I0 => \wl_state_r__0\(0),
      I1 => \wl_state_r__0\(1),
      I2 => \^fsm_sequential_wl_state_r_reg[4]_0\(1),
      I3 => \wl_state_r__0\(2),
      I4 => \FSM_sequential_wl_state_r[3]_i_14_n_0\,
      O => \FSM_sequential_wl_state_r[1]_i_2_n_0\
    );
\FSM_sequential_wl_state_r[1]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFF22E2FFFFCCCC"
    )
        port map (
      I0 => \fine_inc[0][5]_i_3_n_0\,
      I1 => \^fsm_sequential_wl_state_r_reg[4]_0\(0),
      I2 => \^fsm_sequential_wl_state_r_reg[4]_0\(1),
      I3 => \FSM_sequential_wl_state_r[1]_i_8_n_0\,
      I4 => \wl_state_r__0\(2),
      I5 => \wl_state_r__0\(1),
      O => \FSM_sequential_wl_state_r[1]_i_3_n_0\
    );
\FSM_sequential_wl_state_r[1]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00190019FF000000"
    )
        port map (
      I0 => \wl_state_r__0\(2),
      I1 => \^fsm_sequential_wl_state_r_reg[4]_0\(0),
      I2 => \FSM_sequential_wl_state_r[4]_i_11_n_0\,
      I3 => \^fsm_sequential_wl_state_r_reg[4]_0\(1),
      I4 => \FSM_sequential_wl_state_r[4]_i_17_n_0\,
      I5 => \wl_state_r__0\(1),
      O => \FSM_sequential_wl_state_r[1]_i_4_n_0\
    );
\FSM_sequential_wl_state_r[1]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"5504555555045504"
    )
        port map (
      I0 => \wl_state_r__0\(0),
      I1 => \rd_data_edge_detect_r[7]_i_4_n_0\,
      I2 => \FSM_sequential_wl_state_r[1]_i_9_n_0\,
      I3 => \FSM_sequential_wl_state_r[3]_i_2_n_0\,
      I4 => \^fsm_sequential_wl_state_r_reg[4]_0\(0),
      I5 => \FSM_sequential_wl_state_r[1]_i_10_n_0\,
      O => \FSM_sequential_wl_state_r[1]_i_5_n_0\
    );
\FSM_sequential_wl_state_r[1]_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FEFFFEFEFFFFFFFF"
    )
        port map (
      I0 => \fine_inc[0][5]_i_3_n_0\,
      I1 => wrlvl_byte_redo,
      I2 => \^fsm_sequential_wl_state_r_reg[4]_0\(1),
      I3 => \^wr_level_done_r5\,
      I4 => wl_sm_start,
      I5 => \FSM_sequential_wl_state_r[4]_i_11_n_0\,
      O => \FSM_sequential_wl_state_r[1]_i_6_n_0\
    );
\FSM_sequential_wl_state_r[1]_i_7\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F7FFF7F3FFFFFFFF"
    )
        port map (
      I0 => \FSM_sequential_wl_state_r[4]_i_16_n_0\,
      I1 => \wl_state_r__0\(1),
      I2 => \wl_state_r__0\(0),
      I3 => \^fsm_sequential_wl_state_r_reg[4]_0\(1),
      I4 => \FSM_sequential_wl_state_r[1]_i_11_n_0\,
      I5 => \^fsm_sequential_wl_state_r_reg[4]_0\(0),
      O => \FSM_sequential_wl_state_r[1]_i_7_n_0\
    );
\FSM_sequential_wl_state_r[1]_i_8\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8AAAAAAAAAAAAAAA"
    )
        port map (
      I0 => wl_edge_detect_valid_r_reg_n_0,
      I1 => \rd_data_edge_detect_r_reg[7]_i_5_n_0\,
      I2 => \wl_tap_count_r_reg_n_0_[5]\,
      I3 => \wl_tap_count_r_reg_n_0_[4]\,
      I4 => \wl_tap_count_r_reg_n_0_[3]\,
      I5 => \FSM_sequential_wl_state_r[3]_i_7_n_0\,
      O => \FSM_sequential_wl_state_r[1]_i_8_n_0\
    );
\FSM_sequential_wl_state_r[1]_i_9\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"DF"
    )
        port map (
      I0 => \^fsm_sequential_wl_state_r_reg[4]_0\(1),
      I1 => \^fsm_sequential_wl_state_r_reg[4]_0\(0),
      I2 => wrlvl_byte_redo,
      O => \FSM_sequential_wl_state_r[1]_i_9_n_0\
    );
\FSM_sequential_wl_state_r[2]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAA8AAAAA8A8A8A8"
    )
        port map (
      I0 => \FSM_sequential_wl_state_r[2]_i_2_n_0\,
      I1 => \FSM_sequential_wl_state_r[2]_i_3_n_0\,
      I2 => \FSM_sequential_wl_state_r[2]_i_4_n_0\,
      I3 => \FSM_sequential_wl_state_r[2]_i_5_n_0\,
      I4 => \FSM_sequential_wl_state_r[2]_i_6_n_0\,
      I5 => \FSM_sequential_wl_state_r[2]_i_7_n_0\,
      O => \FSM_sequential_wl_state_r[2]_i_1_n_0\
    );
\FSM_sequential_wl_state_r[2]_i_10\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFF5200F200"
    )
        port map (
      I0 => \^fsm_sequential_wl_state_r_reg[4]_0\(0),
      I1 => \fine_dec_cnt[5]_i_5_n_0\,
      I2 => \wl_state_r__0\(2),
      I3 => \wl_state_r__0\(0),
      I4 => \^wr_level_done_r5\,
      I5 => \FSM_sequential_wl_state_r[2]_i_14_n_0\,
      O => \FSM_sequential_wl_state_r[2]_i_10_n_0\
    );
\FSM_sequential_wl_state_r[2]_i_11\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"08"
    )
        port map (
      I0 => wr_level_start_r,
      I1 => wl_sm_start,
      I2 => wr_level_done_r_reg_n_0,
      O => \FSM_sequential_wl_state_r[2]_i_11_n_0\
    );
\FSM_sequential_wl_state_r[2]_i_12\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FE00FFFFFFFFFFFF"
    )
        port map (
      I0 => \wrlvl_redo_corse_inc_reg_n_0_[1]\,
      I1 => \wrlvl_redo_corse_inc_reg_n_0_[0]\,
      I2 => \wrlvl_redo_corse_inc_reg_n_0_[2]\,
      I3 => wrlvl_byte_redo,
      I4 => \dqs_count_r[3]_i_12_n_0\,
      I5 => \wl_tap_count_r[4]_i_4_n_0\,
      O => \FSM_sequential_wl_state_r[2]_i_12_n_0\
    );
\FSM_sequential_wl_state_r[2]_i_13\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"333337333333F733"
    )
        port map (
      I0 => p_0_in,
      I1 => \wl_state_r__0\(1),
      I2 => \wl_state_r__0\(2),
      I3 => \wl_state_r__0\(0),
      I4 => \^fsm_sequential_wl_state_r_reg[4]_0\(0),
      I5 => \^fsm_sequential_wl_state_r_reg[4]_0\(1),
      O => \FSM_sequential_wl_state_r[2]_i_13_n_0\
    );
\FSM_sequential_wl_state_r[2]_i_14\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFC800"
    )
        port map (
      I0 => \FSM_sequential_wl_state_r[4]_i_17_n_0\,
      I1 => \^fsm_sequential_wl_state_r_reg[4]_0\(0),
      I2 => \wl_state_r__0\(0),
      I3 => \^fsm_sequential_wl_state_r_reg[4]_0\(1),
      I4 => \wl_state_r__0\(1),
      O => \FSM_sequential_wl_state_r[2]_i_14_n_0\
    );
\FSM_sequential_wl_state_r[2]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFF80000000"
    )
        port map (
      I0 => \FSM_sequential_wl_state_r[2]_i_8_n_0\,
      I1 => \^fsm_sequential_wl_state_r_reg[4]_0\(1),
      I2 => \wl_state_r__0\(0),
      I3 => wrlvl_byte_redo,
      I4 => \FSM_sequential_wl_state_r[2]_i_9_n_0\,
      I5 => \FSM_sequential_wl_state_r[2]_i_10_n_0\,
      O => \FSM_sequential_wl_state_r[2]_i_2_n_0\
    );
\FSM_sequential_wl_state_r[2]_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"80A00020"
    )
        port map (
      I0 => \wl_state_r__0\(2),
      I1 => \wl_state_r__0\(0),
      I2 => \^fsm_sequential_wl_state_r_reg[4]_0\(0),
      I3 => \FSM_sequential_wl_state_r[2]_i_11_n_0\,
      I4 => \FSM_sequential_wl_state_r[4]_i_11_n_0\,
      O => \FSM_sequential_wl_state_r[2]_i_3_n_0\
    );
\FSM_sequential_wl_state_r[2]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFF54545554"
    )
        port map (
      I0 => \FSM_sequential_wl_state_r[2]_i_12_n_0\,
      I1 => \FSM_sequential_wl_state_r[4]_i_11_n_0\,
      I2 => wrlvl_byte_redo,
      I3 => wl_sm_start,
      I4 => \^wr_level_done_r5\,
      I5 => \FSM_sequential_wl_state_r[2]_i_13_n_0\,
      O => \FSM_sequential_wl_state_r[2]_i_4_n_0\
    );
\FSM_sequential_wl_state_r[2]_i_5\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"008F"
    )
        port map (
      I0 => \FSM_sequential_wl_state_r[2]_i_9_n_0\,
      I1 => \rd_data_edge_detect_r[7]_i_4_n_0\,
      I2 => wrlvl_byte_redo,
      I3 => \^fsm_sequential_wl_state_r_reg[4]_0\(0),
      O => \FSM_sequential_wl_state_r[2]_i_5_n_0\
    );
\FSM_sequential_wl_state_r[2]_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"20202020FFFF00FF"
    )
        port map (
      I0 => \FSM_sequential_wl_state_r[3]_i_3_n_0\,
      I1 => \rd_data_edge_detect_r_reg[7]_i_5_n_0\,
      I2 => wl_edge_detect_valid_r_reg_n_0,
      I3 => \^fsm_sequential_wl_state_r_reg[4]_0\(0),
      I4 => \FSM_sequential_wl_state_r[4]_i_16_n_0\,
      I5 => \wl_state_r__0\(0),
      O => \FSM_sequential_wl_state_r[2]_i_6_n_0\
    );
\FSM_sequential_wl_state_r[2]_i_7\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \^fsm_sequential_wl_state_r_reg[4]_0\(1),
      I1 => \wl_state_r__0\(2),
      O => \FSM_sequential_wl_state_r[2]_i_7_n_0\
    );
\FSM_sequential_wl_state_r[2]_i_8\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => \^fsm_sequential_wl_state_r_reg[4]_0\(0),
      I1 => \FSM_sequential_wl_state_r[4]_i_17_n_0\,
      O => \FSM_sequential_wl_state_r[2]_i_8_n_0\
    );
\FSM_sequential_wl_state_r[2]_i_9\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFE888E8880000"
    )
        port map (
      I0 => \wl_corse_cnt_reg[0][0][1]_i_1_n_0\,
      I1 => \wrlvl_redo_corse_inc_reg_n_0_[1]\,
      I2 => \wl_corse_cnt_reg[0][0][0]_i_1_n_0\,
      I3 => \wrlvl_redo_corse_inc_reg_n_0_[0]\,
      I4 => \wl_corse_cnt_reg[0][0][2]_i_1_n_0\,
      I5 => \wrlvl_redo_corse_inc_reg_n_0_[2]\,
      O => \FSM_sequential_wl_state_r[2]_i_9_n_0\
    );
\FSM_sequential_wl_state_r[3]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFBA00"
    )
        port map (
      I0 => \FSM_sequential_wl_state_r[3]_i_2_n_0\,
      I1 => \FSM_sequential_wl_state_r[3]_i_3_n_0\,
      I2 => \FSM_sequential_wl_state_r[3]_i_4_n_0\,
      I3 => \^fsm_sequential_wl_state_r_reg[4]_0\(1),
      I4 => \FSM_sequential_wl_state_r[3]_i_5_n_0\,
      I5 => \FSM_sequential_wl_state_r[3]_i_6_n_0\,
      O => \FSM_sequential_wl_state_r[3]_i_1_n_0\
    );
\FSM_sequential_wl_state_r[3]_i_10\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \^fsm_sequential_wl_state_r_reg[4]_0\(0),
      I1 => \wl_state_r__0\(0),
      O => \FSM_sequential_wl_state_r[3]_i_10_n_0\
    );
\FSM_sequential_wl_state_r[3]_i_11\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0100"
    )
        port map (
      I0 => p_0_in,
      I1 => \^fsm_sequential_wl_state_r_reg[4]_0\(0),
      I2 => \wl_state_r__0\(2),
      I3 => \wl_state_r__0\(0),
      O => \FSM_sequential_wl_state_r[3]_i_11_n_0\
    );
\FSM_sequential_wl_state_r[3]_i_12\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"000000FB00000000"
    )
        port map (
      I0 => wrlvl_byte_redo,
      I1 => wl_sm_start,
      I2 => \^wr_level_done_r5\,
      I3 => \wl_state_r__0\(0),
      I4 => \wl_state_r__0\(2),
      I5 => \wl_tap_count_r[4]_i_4_n_0\,
      O => \FSM_sequential_wl_state_r[3]_i_12_n_0\
    );
\FSM_sequential_wl_state_r[3]_i_13\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"82A22020"
    )
        port map (
      I0 => \wl_state_r__0\(2),
      I1 => \wl_state_r__0\(0),
      I2 => \^fsm_sequential_wl_state_r_reg[4]_0\(0),
      I3 => \FSM_sequential_wl_state_r[2]_i_11_n_0\,
      I4 => \wl_state_r__0\(1),
      O => \FSM_sequential_wl_state_r[3]_i_13_n_0\
    );
\FSM_sequential_wl_state_r[3]_i_14\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"BFFF"
    )
        port map (
      I0 => \rd_data_edge_detect_r_reg[7]_i_9_n_0\,
      I1 => \stable_cnt_reg_n_0_[3]\,
      I2 => \stable_cnt_reg_n_0_[1]\,
      I3 => \stable_cnt_reg_n_0_[2]\,
      O => \FSM_sequential_wl_state_r[3]_i_14_n_0\
    );
\FSM_sequential_wl_state_r[3]_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \wl_state_r__0\(1),
      I1 => \wl_state_r__0\(2),
      O => \FSM_sequential_wl_state_r[3]_i_2_n_0\
    );
\FSM_sequential_wl_state_r[3]_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00008000"
    )
        port map (
      I0 => \^fsm_sequential_wl_state_r_reg[4]_0\(0),
      I1 => \wl_tap_count_r_reg_n_0_[3]\,
      I2 => \wl_tap_count_r_reg_n_0_[4]\,
      I3 => \wl_tap_count_r_reg_n_0_[5]\,
      I4 => \FSM_sequential_wl_state_r[3]_i_7_n_0\,
      O => \FSM_sequential_wl_state_r[3]_i_3_n_0\
    );
\FSM_sequential_wl_state_r[3]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00002F00AFAFAFAF"
    )
        port map (
      I0 => wl_edge_detect_valid_r_reg_n_0,
      I1 => \rd_data_edge_detect_r_reg[7]_i_5_n_0\,
      I2 => \^fsm_sequential_wl_state_r_reg[4]_0\(0),
      I3 => \wl_state_r__0\(0),
      I4 => \FSM_sequential_wl_state_r[3]_i_8_n_0\,
      I5 => \FSM_sequential_wl_state_r[3]_i_9_n_0\,
      O => \FSM_sequential_wl_state_r[3]_i_4_n_0\
    );
\FSM_sequential_wl_state_r[3]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFF404"
    )
        port map (
      I0 => \FSM_sequential_wl_state_r[4]_i_17_n_0\,
      I1 => \FSM_sequential_wl_state_r[3]_i_10_n_0\,
      I2 => \wl_state_r__0\(1),
      I3 => \FSM_sequential_wl_state_r[3]_i_11_n_0\,
      I4 => \FSM_sequential_wl_state_r[3]_i_12_n_0\,
      I5 => \FSM_sequential_wl_state_r[3]_i_13_n_0\,
      O => \FSM_sequential_wl_state_r[3]_i_5_n_0\
    );
\FSM_sequential_wl_state_r[3]_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0002000000020002"
    )
        port map (
      I0 => \^fsm_sequential_wl_state_r_reg[4]_0\(0),
      I1 => \wl_state_r__0\(1),
      I2 => \^fsm_sequential_wl_state_r_reg[4]_0\(1),
      I3 => \wl_state_r__0\(2),
      I4 => \FSM_sequential_wl_state_r[3]_i_14_n_0\,
      I5 => \wl_state_r__0\(0),
      O => \FSM_sequential_wl_state_r[3]_i_6_n_0\
    );
\FSM_sequential_wl_state_r[3]_i_7\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"80"
    )
        port map (
      I0 => \wl_corse_cnt_reg[0][0][2]_i_1_n_0\,
      I1 => \wl_corse_cnt_reg[0][0][1]_i_1_n_0\,
      I2 => \wl_corse_cnt_reg[0][0][0]_i_1_n_0\,
      O => \FSM_sequential_wl_state_r[3]_i_7_n_0\
    );
\FSM_sequential_wl_state_r[3]_i_8\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => \wl_state_r__0\(2),
      I1 => \wl_state_r__0\(1),
      O => \FSM_sequential_wl_state_r[3]_i_8_n_0\
    );
\FSM_sequential_wl_state_r[3]_i_9\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"4F4F4F4FFF4F4F4F"
    )
        port map (
      I0 => \FSM_sequential_wl_state_r[4]_i_17_n_0\,
      I1 => \wl_state_r__0\(0),
      I2 => \dqs_count_r[3]_i_4_n_0\,
      I3 => \wl_state_r__0\(1),
      I4 => wrlvl_byte_redo,
      I5 => \rd_data_edge_detect_r[7]_i_4_n_0\,
      O => \FSM_sequential_wl_state_r[3]_i_9_n_0\
    );
\FSM_sequential_wl_state_r[4]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFF0054FF54"
    )
        port map (
      I0 => \FSM_sequential_wl_state_r[4]_i_3_n_0\,
      I1 => \FSM_sequential_wl_state_r[4]_i_4_n_0\,
      I2 => \FSM_sequential_wl_state_r[4]_i_5_n_0\,
      I3 => \^fsm_sequential_wl_state_r_reg[4]_0\(1),
      I4 => \FSM_sequential_wl_state_r[4]_i_6_n_0\,
      I5 => \FSM_sequential_wl_state_r_reg[4]_i_7_n_0\,
      O => \FSM_sequential_wl_state_r[4]_i_1_n_0\
    );
\FSM_sequential_wl_state_r[4]_i_10\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"CA000A00FFFFFFFF"
    )
        port map (
      I0 => \fine_dec_cnt[5]_i_5_n_0\,
      I1 => \rd_data_edge_detect_r_reg[7]_i_5_n_0\,
      I2 => \^fsm_sequential_wl_state_r_reg[4]_0\(1),
      I3 => \^fsm_sequential_wl_state_r_reg[4]_0\(0),
      I4 => wl_edge_detect_valid_r_reg_n_0,
      I5 => \FSM_sequential_wl_state_r[4]_i_20_n_0\,
      O => \FSM_sequential_wl_state_r[4]_i_10_n_0\
    );
\FSM_sequential_wl_state_r[4]_i_11\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \corse_inc[0][2]_i_7_n_0\,
      I1 => \corse_inc_reg[0][2]_i_6_n_0\,
      O => \FSM_sequential_wl_state_r[4]_i_11_n_0\
    );
\FSM_sequential_wl_state_r[4]_i_12\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"7070707000707070"
    )
        port map (
      I0 => \wrlvl_redo_corse_inc[2]_i_4_0\,
      I1 => done_dqs_dec238_out,
      I2 => \wl_state_r__0\(1),
      I3 => wr_level_start_r,
      I4 => wl_sm_start,
      I5 => wr_level_done_r_reg_n_0,
      O => \FSM_sequential_wl_state_r[4]_i_12_n_0\
    );
\FSM_sequential_wl_state_r[4]_i_13\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFEF"
    )
        port map (
      I0 => incdec_wait_cnt_reg(1),
      I1 => incdec_wait_cnt_reg(0),
      I2 => incdec_wait_cnt_reg(3),
      I3 => incdec_wait_cnt_reg(2),
      O => \FSM_sequential_wl_state_r[4]_i_13_n_0\
    );
\FSM_sequential_wl_state_r[4]_i_14\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"08A008AF"
    )
        port map (
      I0 => wl_sm_start,
      I1 => \wl_state_r__0\(0),
      I2 => \^fsm_sequential_wl_state_r_reg[4]_0\(0),
      I3 => \wl_state_r__0\(2),
      I4 => \FSM_sequential_wl_state_r[4]_i_13_n_0\,
      O => \FSM_sequential_wl_state_r[4]_i_14_n_0\
    );
\FSM_sequential_wl_state_r[4]_i_15\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"55551110"
    )
        port map (
      I0 => \wl_state_r__0\(2),
      I1 => \^fsm_sequential_wl_state_r_reg[4]_0\(0),
      I2 => wl_sm_start,
      I3 => wrlvl_byte_redo,
      I4 => \wl_state_r__0\(0),
      O => \FSM_sequential_wl_state_r[4]_i_15_n_0\
    );
\FSM_sequential_wl_state_r[4]_i_16\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"01"
    )
        port map (
      I0 => \corse_dec_reg[0][2]_i_2_n_0\,
      I1 => \corse_dec_reg[0][2]_i_3_n_0\,
      I2 => \corse_dec_reg[0][2]_i_10_n_0\,
      O => \FSM_sequential_wl_state_r[4]_i_16_n_0\
    );
\FSM_sequential_wl_state_r[4]_i_17\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000000001"
    )
        port map (
      I0 => \fine_dec_cnt_reg_n_0_[3]\,
      I1 => \fine_dec_cnt_reg_n_0_[0]\,
      I2 => \fine_dec_cnt_reg_n_0_[1]\,
      I3 => \fine_dec_cnt_reg_n_0_[2]\,
      I4 => \fine_dec_cnt_reg_n_0_[4]\,
      I5 => \fine_dec_cnt_reg_n_0_[5]\,
      O => \FSM_sequential_wl_state_r[4]_i_17_n_0\
    );
\FSM_sequential_wl_state_r[4]_i_18\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"4444000040000000"
    )
        port map (
      I0 => \wl_state_r__0\(1),
      I1 => \wl_state_r__0\(0),
      I2 => \^wr_level_done_r5\,
      I3 => \wl_state_r__0\(2),
      I4 => \^fsm_sequential_wl_state_r_reg[4]_0\(0),
      I5 => \^fsm_sequential_wl_state_r_reg[4]_0\(1),
      O => \FSM_sequential_wl_state_r[4]_i_18_n_0\
    );
\FSM_sequential_wl_state_r[4]_i_19\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"08"
    )
        port map (
      I0 => \wl_state_r__0\(2),
      I1 => \wl_state_r__0\(1),
      I2 => \wl_state_r__0\(0),
      O => \^fsm_sequential_wl_state_r_reg[2]_0\
    );
\FSM_sequential_wl_state_r[4]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FEEEFEEEEEEEFEEE"
    )
        port map (
      I0 => \FSM_sequential_wl_state_r[4]_i_8_n_0\,
      I1 => \FSM_sequential_wl_state_r[4]_i_9_n_0\,
      I2 => \FSM_sequential_wl_state_r[4]_i_10_n_0\,
      I3 => \wl_state_r__0\(0),
      I4 => \wl_state_r__0\(2),
      I5 => \^fsm_sequential_wl_state_r_reg[4]_0\(1),
      O => \FSM_sequential_wl_state_r[4]_i_2_n_0\
    );
\FSM_sequential_wl_state_r[4]_i_20\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"55550510"
    )
        port map (
      I0 => \wl_state_r__0\(2),
      I1 => p_0_in,
      I2 => \wl_state_r__0\(1),
      I3 => \^fsm_sequential_wl_state_r_reg[4]_0\(0),
      I4 => \^fsm_sequential_wl_state_r_reg[4]_0\(1),
      O => \FSM_sequential_wl_state_r[4]_i_20_n_0\
    );
\FSM_sequential_wl_state_r[4]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"000F010F00F0F0F0"
    )
        port map (
      I0 => wrlvl_byte_redo,
      I1 => \^wr_level_done_r5\,
      I2 => \wl_state_r__0\(2),
      I3 => \wl_state_r__0\(1),
      I4 => wl_sm_start,
      I5 => \^fsm_sequential_wl_state_r_reg[4]_0\(0),
      O => \FSM_sequential_wl_state_r[4]_i_3_n_0\
    );
\FSM_sequential_wl_state_r[4]_i_4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"70000000"
    )
        port map (
      I0 => \FSM_sequential_wl_state_r[4]_i_11_n_0\,
      I1 => \fine_inc[0][5]_i_3_n_0\,
      I2 => \wl_state_r__0\(0),
      I3 => \wl_state_r__0\(1),
      I4 => \^wr_level_done_r5\,
      O => \FSM_sequential_wl_state_r[4]_i_4_n_0\
    );
\FSM_sequential_wl_state_r[4]_i_5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"7E7E7EFF"
    )
        port map (
      I0 => \wl_state_r__0\(2),
      I1 => \wl_state_r__0\(1),
      I2 => \^fsm_sequential_wl_state_r_reg[4]_0\(0),
      I3 => \FSM_sequential_wl_state_r[4]_i_12_n_0\,
      I4 => \wl_state_r__0\(0),
      O => \FSM_sequential_wl_state_r[4]_i_5_n_0\
    );
\FSM_sequential_wl_state_r[4]_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FF8A0075FF8A7075"
    )
        port map (
      I0 => \wl_state_r__0\(0),
      I1 => \FSM_sequential_wl_state_r[4]_i_13_n_0\,
      I2 => \wl_state_r__0\(1),
      I3 => \^fsm_sequential_wl_state_r_reg[4]_0\(0),
      I4 => \wl_state_r__0\(2),
      I5 => wl_sm_start,
      O => \FSM_sequential_wl_state_r[4]_i_6_n_0\
    );
\FSM_sequential_wl_state_r[4]_i_8\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000080000880888"
    )
        port map (
      I0 => \^fsm_sequential_wl_state_r_reg[4]_0\(0),
      I1 => \^fsm_sequential_wl_state_r_reg[4]_0\(1),
      I2 => \wl_state_r__0\(0),
      I3 => \wl_state_r__0\(1),
      I4 => \FSM_sequential_wl_state_r[4]_i_16_n_0\,
      I5 => \FSM_sequential_wl_state_r[4]_i_17_n_0\,
      O => \FSM_sequential_wl_state_r[4]_i_8_n_0\
    );
\FSM_sequential_wl_state_r[4]_i_9\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"BFBBBBBBAAAAAAAA"
    )
        port map (
      I0 => \FSM_sequential_wl_state_r[4]_i_18_n_0\,
      I1 => \^fsm_sequential_wl_state_r_reg[4]_0\(0),
      I2 => wr_level_done_r_reg_n_0,
      I3 => wl_sm_start,
      I4 => wr_level_start_r,
      I5 => \^fsm_sequential_wl_state_r_reg[2]_0\,
      O => \FSM_sequential_wl_state_r[4]_i_9_n_0\
    );
\FSM_sequential_wl_state_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => \FSM_sequential_wl_state_r[4]_i_1_n_0\,
      D => \FSM_sequential_wl_state_r[0]_i_1_n_0\,
      Q => \wl_state_r__0\(0),
      R => \fine_inc_reg[6][3]_0\(1)
    );
\FSM_sequential_wl_state_r_reg[1]\: unisim.vcomponents.FDSE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => \FSM_sequential_wl_state_r[4]_i_1_n_0\,
      D => \FSM_sequential_wl_state_r[1]_i_1_n_0\,
      Q => \wl_state_r__0\(1),
      S => \fine_inc_reg[6][3]_0\(1)
    );
\FSM_sequential_wl_state_r_reg[2]\: unisim.vcomponents.FDSE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => \FSM_sequential_wl_state_r[4]_i_1_n_0\,
      D => \FSM_sequential_wl_state_r[2]_i_1_n_0\,
      Q => \wl_state_r__0\(2),
      S => \fine_inc_reg[6][3]_0\(1)
    );
\FSM_sequential_wl_state_r_reg[3]\: unisim.vcomponents.FDSE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => \FSM_sequential_wl_state_r[4]_i_1_n_0\,
      D => \FSM_sequential_wl_state_r[3]_i_1_n_0\,
      Q => \^fsm_sequential_wl_state_r_reg[4]_0\(0),
      S => \fine_inc_reg[6][3]_0\(1)
    );
\FSM_sequential_wl_state_r_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => \FSM_sequential_wl_state_r[4]_i_1_n_0\,
      D => \FSM_sequential_wl_state_r[4]_i_2_n_0\,
      Q => \^fsm_sequential_wl_state_r_reg[4]_0\(1),
      R => \fine_inc_reg[6][3]_0\(1)
    );
\FSM_sequential_wl_state_r_reg[4]_i_7\: unisim.vcomponents.MUXF7
     port map (
      I0 => \FSM_sequential_wl_state_r[4]_i_14_n_0\,
      I1 => \FSM_sequential_wl_state_r[4]_i_15_n_0\,
      O => \FSM_sequential_wl_state_r_reg[4]_i_7_n_0\,
      S => \wl_state_r__0\(1)
    );
\corse_cnt[0][0]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => corse_cnt(0),
      I1 => \corse_cnt[0][2]_i_3_n_0\,
      I2 => \corse_cnt_reg_n_0_[0][0]\,
      O => \corse_cnt[0][0]_i_1_n_0\
    );
\corse_cnt[0][0]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"88888A88AAAAAAAA"
    )
        port map (
      I0 => \wl_state_r__0\(1),
      I1 => \corse_cnt[0][0]_i_3_n_0\,
      I2 => \wl_corse_cnt_reg[0][0][0]_i_1_n_0\,
      I3 => \^fsm_sequential_wl_state_r_reg[4]_0\(0),
      I4 => \wl_state_r__0\(2),
      I5 => \corse_cnt[0][0]_i_4_n_0\,
      O => corse_cnt(0)
    );
\corse_cnt[0][0]_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0C080008"
    )
        port map (
      I0 => \corse_cnt[0][0]_i_5_n_0\,
      I1 => \^fsm_sequential_wl_state_r_reg[4]_0\(1),
      I2 => \wl_state_r__0\(2),
      I3 => \^dqs_count_r_reg[2]_rep__0_0\,
      I4 => \corse_cnt[0][0]_i_6_n_0\,
      O => \corse_cnt[0][0]_i_3_n_0\
    );
\corse_cnt[0][0]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000FF1BFFFF"
    )
        port map (
      I0 => \dqs_count_r_reg[3]_1\(2),
      I1 => \corse_cnt[0][0]_i_7_n_0\,
      I2 => \corse_cnt[0][0]_i_8_n_0\,
      I3 => \^fsm_sequential_wl_state_r_reg[4]_0\(1),
      I4 => \wl_state_r__0\(2),
      I5 => \corse_cnt[0][0]_i_9_n_0\,
      O => \corse_cnt[0][0]_i_4_n_0\
    );
\corse_cnt[0][0]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \final_coarse_tap_reg_n_0_[3][0]\,
      I1 => \final_coarse_tap_reg_n_0_[2][0]\,
      I2 => \^dqs_count_r_reg[1]_rep_0\,
      I3 => \final_coarse_tap_reg_n_0_[1][0]\,
      I4 => \^dqs_count_r_reg[0]_rep_0\,
      I5 => \final_coarse_tap_reg_n_0_[0][0]\,
      O => \corse_cnt[0][0]_i_5_n_0\
    );
\corse_cnt[0][0]_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \final_coarse_tap_reg_n_0_[7][0]\,
      I1 => \final_coarse_tap_reg_n_0_[6][0]\,
      I2 => \^dqs_count_r_reg[1]_rep_0\,
      I3 => \final_coarse_tap_reg_n_0_[5][0]\,
      I4 => \^dqs_count_r_reg[0]_rep_0\,
      I5 => \final_coarse_tap_reg_n_0_[4][0]\,
      O => \corse_cnt[0][0]_i_6_n_0\
    );
\corse_cnt[0][0]_i_7\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \final_coarse_tap_reg_n_0_[3][0]\,
      I1 => \final_coarse_tap_reg_n_0_[2][0]\,
      I2 => \dqs_count_r_reg[3]_1\(1),
      I3 => \final_coarse_tap_reg_n_0_[1][0]\,
      I4 => \dqs_count_r_reg[3]_1\(0),
      I5 => \final_coarse_tap_reg_n_0_[0][0]\,
      O => \corse_cnt[0][0]_i_7_n_0\
    );
\corse_cnt[0][0]_i_8\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \final_coarse_tap_reg_n_0_[7][0]\,
      I1 => \final_coarse_tap_reg_n_0_[6][0]\,
      I2 => \dqs_count_r_reg[3]_1\(1),
      I3 => \final_coarse_tap_reg_n_0_[5][0]\,
      I4 => \dqs_count_r_reg[3]_1\(0),
      I5 => \final_coarse_tap_reg_n_0_[4][0]\,
      O => \corse_cnt[0][0]_i_8_n_0\
    );
\corse_cnt[0][0]_i_9\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"02"
    )
        port map (
      I0 => p_0_in,
      I1 => \^fsm_sequential_wl_state_r_reg[4]_0\(0),
      I2 => \^fsm_sequential_wl_state_r_reg[4]_0\(1),
      O => \corse_cnt[0][0]_i_9_n_0\
    );
\corse_cnt[0][1]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => corse_cnt(1),
      I1 => \corse_cnt[0][2]_i_3_n_0\,
      I2 => \corse_cnt_reg_n_0_[0][1]\,
      O => \corse_cnt[0][1]_i_1_n_0\
    );
\corse_cnt[0][1]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"888A8A8888888888"
    )
        port map (
      I0 => \wl_state_r__0\(1),
      I1 => \corse_cnt[0][1]_i_3_n_0\,
      I2 => \wl_state_r__0\(2),
      I3 => \wl_corse_cnt_reg[0][0][0]_i_1_n_0\,
      I4 => \wl_corse_cnt_reg[0][0][1]_i_1_n_0\,
      I5 => \^fsm_sequential_wl_state_r_reg[4]_0\(0),
      O => corse_cnt(1)
    );
\corse_cnt[0][1]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AEAAAEAAAFAFAEAA"
    )
        port map (
      I0 => \corse_cnt[0][1]_i_4_n_0\,
      I1 => \^po_stg2_wrcal_cnt_reg[2]\,
      I2 => \^fsm_sequential_wl_state_r_reg[4]_0\(1),
      I3 => \wl_state_r__0\(2),
      I4 => p_0_in,
      I5 => \^fsm_sequential_wl_state_r_reg[4]_0\(0),
      O => \corse_cnt[0][1]_i_3_n_0\
    );
\corse_cnt[0][1]_i_4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0C080008"
    )
        port map (
      I0 => \corse_cnt[0][1]_i_5_n_0\,
      I1 => \^fsm_sequential_wl_state_r_reg[4]_0\(1),
      I2 => \wl_state_r__0\(2),
      I3 => \^dqs_count_r_reg[2]_rep__0_0\,
      I4 => \corse_cnt[0][1]_i_6_n_0\,
      O => \corse_cnt[0][1]_i_4_n_0\
    );
\corse_cnt[0][1]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \final_coarse_tap_reg_n_0_[3][1]\,
      I1 => \final_coarse_tap_reg_n_0_[2][1]\,
      I2 => \^dqs_count_r_reg[1]_rep_0\,
      I3 => \final_coarse_tap_reg_n_0_[1][1]\,
      I4 => \^dqs_count_r_reg[0]_rep_0\,
      I5 => \final_coarse_tap_reg_n_0_[0][1]\,
      O => \corse_cnt[0][1]_i_5_n_0\
    );
\corse_cnt[0][1]_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \final_coarse_tap_reg_n_0_[7][1]\,
      I1 => \final_coarse_tap_reg_n_0_[6][1]\,
      I2 => \^dqs_count_r_reg[1]_rep_0\,
      I3 => \final_coarse_tap_reg_n_0_[5][1]\,
      I4 => \^dqs_count_r_reg[0]_rep_0\,
      I5 => \final_coarse_tap_reg_n_0_[4][1]\,
      O => \corse_cnt[0][1]_i_6_n_0\
    );
\corse_cnt[0][2]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => corse_cnt(2),
      I1 => \corse_cnt[0][2]_i_3_n_0\,
      I2 => \corse_cnt_reg_n_0_[0][2]\,
      O => \corse_cnt[0][2]_i_1_n_0\
    );
\corse_cnt[0][2]_i_11\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0C080008"
    )
        port map (
      I0 => \corse_cnt[0][2]_i_12_n_0\,
      I1 => \^fsm_sequential_wl_state_r_reg[4]_0\(1),
      I2 => \wl_state_r__0\(2),
      I3 => \^dqs_count_r_reg[2]_rep__0_0\,
      I4 => \corse_cnt[0][2]_i_13_n_0\,
      O => \corse_cnt[0][2]_i_11_n_0\
    );
\corse_cnt[0][2]_i_12\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \final_coarse_tap_reg_n_0_[3][2]\,
      I1 => \final_coarse_tap_reg_n_0_[2][2]\,
      I2 => \^dqs_count_r_reg[1]_rep_0\,
      I3 => \final_coarse_tap_reg_n_0_[1][2]\,
      I4 => \^dqs_count_r_reg[0]_rep_0\,
      I5 => \final_coarse_tap_reg_n_0_[0][2]\,
      O => \corse_cnt[0][2]_i_12_n_0\
    );
\corse_cnt[0][2]_i_13\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \final_coarse_tap_reg_n_0_[7][2]\,
      I1 => \final_coarse_tap_reg_n_0_[6][2]\,
      I2 => \^dqs_count_r_reg[1]_rep_0\,
      I3 => \final_coarse_tap_reg_n_0_[5][2]\,
      I4 => \^dqs_count_r_reg[0]_rep_0\,
      I5 => \final_coarse_tap_reg_n_0_[4][2]\,
      O => \corse_cnt[0][2]_i_13_n_0\
    );
\corse_cnt[0][2]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8A88888888888A88"
    )
        port map (
      I0 => \wl_state_r__0\(1),
      I1 => \corse_cnt[0][2]_i_4_n_0\,
      I2 => \wl_state_r__0\(2),
      I3 => \^fsm_sequential_wl_state_r_reg[4]_0\(0),
      I4 => \wl_corse_cnt_reg[0][0][2]_i_1_n_0\,
      I5 => \corse_cnt[0][2]_i_5_n_0\,
      O => corse_cnt(2)
    );
\corse_cnt[0][2]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"BA00BA00BA00FFFF"
    )
        port map (
      I0 => \corse_cnt[0][2]_i_6_n_0\,
      I1 => \corse_cnt[0][2]_i_7_n_0\,
      I2 => \fine_inc[0][5]_i_4_n_0\,
      I3 => \corse_cnt[0][2]_i_8_n_0\,
      I4 => \corse_cnt_reg[3][0]_0\,
      I5 => \corse_cnt_reg[4][0]_0\,
      O => \corse_cnt[0][2]_i_3_n_0\
    );
\corse_cnt[0][2]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0F0F0F0F8F8FFF8"
    )
        port map (
      I0 => \wl_state_r__0\(2),
      I1 => \^po_stg2_wrcal_cnt_reg[2]_0\,
      I2 => \corse_cnt[0][2]_i_11_n_0\,
      I3 => p_0_in,
      I4 => \^fsm_sequential_wl_state_r_reg[4]_0\(0),
      I5 => \^fsm_sequential_wl_state_r_reg[4]_0\(1),
      O => \corse_cnt[0][2]_i_4_n_0\
    );
\corse_cnt[0][2]_i_5\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"7"
    )
        port map (
      I0 => \wl_corse_cnt_reg[0][0][0]_i_1_n_0\,
      I1 => \wl_corse_cnt_reg[0][0][1]_i_1_n_0\,
      O => \corse_cnt[0][2]_i_5_n_0\
    );
\corse_cnt[0][2]_i_6\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \^fsm_sequential_wl_state_r_reg[4]_0\(0),
      I1 => p_0_in,
      O => \corse_cnt[0][2]_i_6_n_0\
    );
\corse_cnt[0][2]_i_7\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"4F"
    )
        port map (
      I0 => wrlvl_byte_redo,
      I1 => \^wr_level_done_r5\,
      I2 => \^fsm_sequential_wl_state_r_reg[4]_0\(0),
      O => \corse_cnt[0][2]_i_7_n_0\
    );
\corse_cnt[0][2]_i_8\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0040"
    )
        port map (
      I0 => \^fsm_sequential_wl_state_r_reg[4]_0\(1),
      I1 => \wl_state_r__0\(0),
      I2 => \wl_state_r__0\(1),
      I3 => \wl_state_r__0\(2),
      O => \corse_cnt[0][2]_i_8_n_0\
    );
\corse_cnt[1][0]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => corse_cnt(0),
      I1 => \corse_cnt[1][2]_i_2_n_0\,
      I2 => \corse_cnt_reg_n_0_[1][0]\,
      O => \corse_cnt[1][0]_i_1_n_0\
    );
\corse_cnt[1][1]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => corse_cnt(1),
      I1 => \corse_cnt[1][2]_i_2_n_0\,
      I2 => \corse_cnt_reg_n_0_[1][1]\,
      O => \corse_cnt[1][1]_i_1_n_0\
    );
\corse_cnt[1][2]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => corse_cnt(2),
      I1 => \corse_cnt[1][2]_i_2_n_0\,
      I2 => \corse_cnt_reg_n_0_[1][2]\,
      O => \corse_cnt[1][2]_i_1_n_0\
    );
\corse_cnt[1][2]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"BA00BA00BA00FFFF"
    )
        port map (
      I0 => \corse_cnt[0][2]_i_6_n_0\,
      I1 => \corse_cnt[0][2]_i_7_n_0\,
      I2 => \fine_inc[1][5]_i_3_n_0\,
      I3 => \corse_cnt[0][2]_i_8_n_0\,
      I4 => \corse_cnt_reg[3][0]_0\,
      I5 => \corse_cnt_reg[5][0]_0\,
      O => \corse_cnt[1][2]_i_2_n_0\
    );
\corse_cnt[2][0]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => corse_cnt(0),
      I1 => \corse_cnt[2][2]_i_2_n_0\,
      I2 => \corse_cnt_reg_n_0_[2][0]\,
      O => \corse_cnt[2][0]_i_1_n_0\
    );
\corse_cnt[2][1]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => corse_cnt(1),
      I1 => \corse_cnt[2][2]_i_2_n_0\,
      I2 => \corse_cnt_reg_n_0_[2][1]\,
      O => \corse_cnt[2][1]_i_1_n_0\
    );
\corse_cnt[2][2]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => corse_cnt(2),
      I1 => \corse_cnt[2][2]_i_2_n_0\,
      I2 => \corse_cnt_reg_n_0_[2][2]\,
      O => \corse_cnt[2][2]_i_1_n_0\
    );
\corse_cnt[2][2]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"BA00BA00BA00FFFF"
    )
        port map (
      I0 => \corse_cnt[0][2]_i_6_n_0\,
      I1 => \corse_cnt[0][2]_i_7_n_0\,
      I2 => \fine_inc[2][5]_i_3_n_0\,
      I3 => \corse_cnt[0][2]_i_8_n_0\,
      I4 => \corse_cnt_reg[3][0]_0\,
      I5 => \corse_cnt_reg[6][0]_0\,
      O => \corse_cnt[2][2]_i_2_n_0\
    );
\corse_cnt[3][0]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => corse_cnt(0),
      I1 => \corse_cnt[3][2]_i_2_n_0\,
      I2 => \corse_cnt_reg_n_0_[3][0]\,
      O => \corse_cnt[3][0]_i_1_n_0\
    );
\corse_cnt[3][1]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => corse_cnt(1),
      I1 => \corse_cnt[3][2]_i_2_n_0\,
      I2 => \corse_cnt_reg_n_0_[3][1]\,
      O => \corse_cnt[3][1]_i_1_n_0\
    );
\corse_cnt[3][2]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => corse_cnt(2),
      I1 => \corse_cnt[3][2]_i_2_n_0\,
      I2 => \corse_cnt_reg_n_0_[3][2]\,
      O => \corse_cnt[3][2]_i_1_n_0\
    );
\corse_cnt[3][2]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"BA00BA00BA00FFFF"
    )
        port map (
      I0 => \corse_cnt[0][2]_i_6_n_0\,
      I1 => \corse_cnt[0][2]_i_7_n_0\,
      I2 => \fine_inc[3][5]_i_3_n_0\,
      I3 => \corse_cnt[0][2]_i_8_n_0\,
      I4 => \corse_cnt_reg[3][0]_0\,
      I5 => \corse_cnt_reg[7][0]_1\,
      O => \corse_cnt[3][2]_i_2_n_0\
    );
\corse_cnt[4][0]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => corse_cnt(0),
      I1 => \corse_cnt[4][2]_i_2_n_0\,
      I2 => \corse_cnt_reg_n_0_[4][0]\,
      O => \corse_cnt[4][0]_i_1_n_0\
    );
\corse_cnt[4][1]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => corse_cnt(1),
      I1 => \corse_cnt[4][2]_i_2_n_0\,
      I2 => \corse_cnt_reg_n_0_[4][1]\,
      O => \corse_cnt[4][1]_i_1_n_0\
    );
\corse_cnt[4][2]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => corse_cnt(2),
      I1 => \corse_cnt[4][2]_i_2_n_0\,
      I2 => \corse_cnt_reg_n_0_[4][2]\,
      O => \corse_cnt[4][2]_i_1_n_0\
    );
\corse_cnt[4][2]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"BA00BA00BA00FFFF"
    )
        port map (
      I0 => \corse_cnt[0][2]_i_6_n_0\,
      I1 => \corse_cnt[0][2]_i_7_n_0\,
      I2 => \fine_inc[4][5]_i_3_n_0\,
      I3 => \corse_cnt[0][2]_i_8_n_0\,
      I4 => \corse_cnt_reg[7][0]_0\,
      I5 => \corse_cnt_reg[4][0]_0\,
      O => \corse_cnt[4][2]_i_2_n_0\
    );
\corse_cnt[5][0]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => corse_cnt(0),
      I1 => \corse_cnt[5][2]_i_2_n_0\,
      I2 => \corse_cnt_reg_n_0_[5][0]\,
      O => \corse_cnt[5][0]_i_1_n_0\
    );
\corse_cnt[5][1]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => corse_cnt(1),
      I1 => \corse_cnt[5][2]_i_2_n_0\,
      I2 => \corse_cnt_reg_n_0_[5][1]\,
      O => \corse_cnt[5][1]_i_1_n_0\
    );
\corse_cnt[5][2]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => corse_cnt(2),
      I1 => \corse_cnt[5][2]_i_2_n_0\,
      I2 => \corse_cnt_reg_n_0_[5][2]\,
      O => \corse_cnt[5][2]_i_1_n_0\
    );
\corse_cnt[5][2]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"BA00BA00BA00FFFF"
    )
        port map (
      I0 => \corse_cnt[0][2]_i_6_n_0\,
      I1 => \corse_cnt[0][2]_i_7_n_0\,
      I2 => \fine_inc[5][5]_i_3_n_0\,
      I3 => \corse_cnt[0][2]_i_8_n_0\,
      I4 => \corse_cnt_reg[7][0]_0\,
      I5 => \corse_cnt_reg[5][0]_0\,
      O => \corse_cnt[5][2]_i_2_n_0\
    );
\corse_cnt[6][0]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => corse_cnt(0),
      I1 => \corse_cnt[6][2]_i_2_n_0\,
      I2 => \corse_cnt_reg_n_0_[6][0]\,
      O => \corse_cnt[6][0]_i_1_n_0\
    );
\corse_cnt[6][1]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => corse_cnt(1),
      I1 => \corse_cnt[6][2]_i_2_n_0\,
      I2 => \corse_cnt_reg_n_0_[6][1]\,
      O => \corse_cnt[6][1]_i_1_n_0\
    );
\corse_cnt[6][2]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => corse_cnt(2),
      I1 => \corse_cnt[6][2]_i_2_n_0\,
      I2 => \corse_cnt_reg_n_0_[6][2]\,
      O => \corse_cnt[6][2]_i_1_n_0\
    );
\corse_cnt[6][2]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"BA00BA00BA00FFFF"
    )
        port map (
      I0 => \corse_cnt[0][2]_i_6_n_0\,
      I1 => \corse_cnt[0][2]_i_7_n_0\,
      I2 => \fine_inc[6][5]_i_3_n_0\,
      I3 => \corse_cnt[0][2]_i_8_n_0\,
      I4 => \corse_cnt_reg[7][0]_0\,
      I5 => \corse_cnt_reg[6][0]_0\,
      O => \corse_cnt[6][2]_i_2_n_0\
    );
\corse_cnt[7][0]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => corse_cnt(0),
      I1 => \corse_cnt[7][2]_i_2_n_0\,
      I2 => \corse_cnt_reg_n_0_[7][0]\,
      O => \corse_cnt[7][0]_i_1_n_0\
    );
\corse_cnt[7][1]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => corse_cnt(1),
      I1 => \corse_cnt[7][2]_i_2_n_0\,
      I2 => \corse_cnt_reg_n_0_[7][1]\,
      O => \corse_cnt[7][1]_i_1_n_0\
    );
\corse_cnt[7][2]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => corse_cnt(2),
      I1 => \corse_cnt[7][2]_i_2_n_0\,
      I2 => \corse_cnt_reg_n_0_[7][2]\,
      O => \corse_cnt[7][2]_i_1_n_0\
    );
\corse_cnt[7][2]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"BA00BA00BA00FFFF"
    )
        port map (
      I0 => \corse_cnt[0][2]_i_6_n_0\,
      I1 => \corse_cnt[0][2]_i_7_n_0\,
      I2 => \fine_inc[7][5]_i_3_n_0\,
      I3 => \corse_cnt[0][2]_i_8_n_0\,
      I4 => \corse_cnt_reg[7][0]_0\,
      I5 => \corse_cnt_reg[7][0]_1\,
      O => \corse_cnt[7][2]_i_2_n_0\
    );
\corse_cnt_reg[0][0]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => '1',
      D => \corse_cnt[0][0]_i_1_n_0\,
      Q => \corse_cnt_reg_n_0_[0][0]\,
      R => \corse_inc_reg[6][2]_0\(1)
    );
\corse_cnt_reg[0][1]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => '1',
      D => \corse_cnt[0][1]_i_1_n_0\,
      Q => \corse_cnt_reg_n_0_[0][1]\,
      R => \corse_inc_reg[6][2]_0\(1)
    );
\corse_cnt_reg[0][2]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => '1',
      D => \corse_cnt[0][2]_i_1_n_0\,
      Q => \corse_cnt_reg_n_0_[0][2]\,
      R => \corse_inc_reg[6][2]_0\(1)
    );
\corse_cnt_reg[1][0]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => '1',
      D => \corse_cnt[1][0]_i_1_n_0\,
      Q => \corse_cnt_reg_n_0_[1][0]\,
      R => \corse_inc_reg[6][2]_0\(1)
    );
\corse_cnt_reg[1][1]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => '1',
      D => \corse_cnt[1][1]_i_1_n_0\,
      Q => \corse_cnt_reg_n_0_[1][1]\,
      R => \corse_inc_reg[6][2]_0\(1)
    );
\corse_cnt_reg[1][2]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => '1',
      D => \corse_cnt[1][2]_i_1_n_0\,
      Q => \corse_cnt_reg_n_0_[1][2]\,
      R => \corse_inc_reg[6][2]_0\(1)
    );
\corse_cnt_reg[2][0]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => '1',
      D => \corse_cnt[2][0]_i_1_n_0\,
      Q => \corse_cnt_reg_n_0_[2][0]\,
      R => \corse_inc_reg[6][2]_0\(1)
    );
\corse_cnt_reg[2][1]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => '1',
      D => \corse_cnt[2][1]_i_1_n_0\,
      Q => \corse_cnt_reg_n_0_[2][1]\,
      R => \corse_inc_reg[6][2]_0\(1)
    );
\corse_cnt_reg[2][2]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => '1',
      D => \corse_cnt[2][2]_i_1_n_0\,
      Q => \corse_cnt_reg_n_0_[2][2]\,
      R => \corse_inc_reg[6][2]_0\(1)
    );
\corse_cnt_reg[3][0]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => '1',
      D => \corse_cnt[3][0]_i_1_n_0\,
      Q => \corse_cnt_reg_n_0_[3][0]\,
      R => \corse_inc_reg[6][2]_0\(1)
    );
\corse_cnt_reg[3][1]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => '1',
      D => \corse_cnt[3][1]_i_1_n_0\,
      Q => \corse_cnt_reg_n_0_[3][1]\,
      R => \corse_inc_reg[6][2]_0\(1)
    );
\corse_cnt_reg[3][2]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => '1',
      D => \corse_cnt[3][2]_i_1_n_0\,
      Q => \corse_cnt_reg_n_0_[3][2]\,
      R => \corse_inc_reg[6][2]_0\(1)
    );
\corse_cnt_reg[4][0]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => '1',
      D => \corse_cnt[4][0]_i_1_n_0\,
      Q => \corse_cnt_reg_n_0_[4][0]\,
      R => \corse_inc_reg[6][2]_0\(1)
    );
\corse_cnt_reg[4][1]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => '1',
      D => \corse_cnt[4][1]_i_1_n_0\,
      Q => \corse_cnt_reg_n_0_[4][1]\,
      R => \corse_inc_reg[6][2]_0\(1)
    );
\corse_cnt_reg[4][2]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => '1',
      D => \corse_cnt[4][2]_i_1_n_0\,
      Q => \corse_cnt_reg_n_0_[4][2]\,
      R => \corse_inc_reg[6][2]_0\(1)
    );
\corse_cnt_reg[5][0]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => '1',
      D => \corse_cnt[5][0]_i_1_n_0\,
      Q => \corse_cnt_reg_n_0_[5][0]\,
      R => \corse_inc_reg[6][2]_0\(1)
    );
\corse_cnt_reg[5][1]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => '1',
      D => \corse_cnt[5][1]_i_1_n_0\,
      Q => \corse_cnt_reg_n_0_[5][1]\,
      R => \corse_inc_reg[6][2]_0\(1)
    );
\corse_cnt_reg[5][2]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => '1',
      D => \corse_cnt[5][2]_i_1_n_0\,
      Q => \corse_cnt_reg_n_0_[5][2]\,
      R => \corse_inc_reg[6][2]_0\(1)
    );
\corse_cnt_reg[6][0]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => '1',
      D => \corse_cnt[6][0]_i_1_n_0\,
      Q => \corse_cnt_reg_n_0_[6][0]\,
      R => \corse_inc_reg[6][2]_0\(1)
    );
\corse_cnt_reg[6][1]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => '1',
      D => \corse_cnt[6][1]_i_1_n_0\,
      Q => \corse_cnt_reg_n_0_[6][1]\,
      R => \corse_inc_reg[6][2]_0\(1)
    );
\corse_cnt_reg[6][2]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => '1',
      D => \corse_cnt[6][2]_i_1_n_0\,
      Q => \corse_cnt_reg_n_0_[6][2]\,
      R => \corse_inc_reg[6][2]_0\(1)
    );
\corse_cnt_reg[7][0]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => '1',
      D => \corse_cnt[7][0]_i_1_n_0\,
      Q => \corse_cnt_reg_n_0_[7][0]\,
      R => \corse_inc_reg[6][2]_0\(1)
    );
\corse_cnt_reg[7][1]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => '1',
      D => \corse_cnt[7][1]_i_1_n_0\,
      Q => \corse_cnt_reg_n_0_[7][1]\,
      R => \corse_inc_reg[6][2]_0\(1)
    );
\corse_cnt_reg[7][2]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => '1',
      D => \corse_cnt[7][2]_i_1_n_0\,
      Q => \corse_cnt_reg_n_0_[7][2]\,
      R => \corse_inc_reg[6][2]_0\(1)
    );
\corse_dec[0][0]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FB08"
    )
        port map (
      I0 => corse_dec(0),
      I1 => \fine_inc[0][5]_i_4_n_0\,
      I2 => \corse_dec[0][2]_i_5_n_0\,
      I3 => \corse_dec_reg[0]_21\(0),
      O => \corse_dec[0][0]_i_1_n_0\
    );
\corse_dec[0][0]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0004"
    )
        port map (
      I0 => \corse_dec_reg[0][2]_i_3_n_0\,
      I1 => \^fsm_sequential_wl_state_r_reg[4]_0\(1),
      I2 => \^fsm_sequential_wl_state_r_reg[4]_0\(0),
      I3 => \FSM_sequential_wl_state_r[4]_i_16_n_0\,
      O => corse_dec(0)
    );
\corse_dec[0][1]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FB08"
    )
        port map (
      I0 => corse_dec(1),
      I1 => \fine_inc[0][5]_i_4_n_0\,
      I2 => \corse_dec[0][2]_i_5_n_0\,
      I3 => \corse_dec_reg[0]_21\(1),
      O => \corse_dec[0][1]_i_1_n_0\
    );
\corse_dec[0][1]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"30000055"
    )
        port map (
      I0 => \corse_dec[0][2]_i_4_n_0\,
      I1 => \^fsm_sequential_wl_state_r_reg[4]_0\(0),
      I2 => \^fsm_sequential_wl_state_r_reg[4]_0\(1),
      I3 => \corse_dec_reg[0][2]_i_3_n_0\,
      I4 => \corse_dec_reg[0][2]_i_2_n_0\,
      O => corse_dec(1)
    );
\corse_dec[0][2]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFF0EFF00000E00"
    )
        port map (
      I0 => \corse_dec_reg[0][2]_i_2_n_0\,
      I1 => \corse_dec_reg[0][2]_i_3_n_0\,
      I2 => \corse_dec[0][2]_i_4_n_0\,
      I3 => \fine_inc[0][5]_i_4_n_0\,
      I4 => \corse_dec[0][2]_i_5_n_0\,
      I5 => \corse_dec_reg[0]_21\(2),
      O => \corse_dec[0][2]_i_1_n_0\
    );
\corse_dec[0][2]_i_11\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \corse_dec_reg[3]_24\(2),
      I1 => \corse_dec_reg[2]_23\(2),
      I2 => dqs_count_r(1),
      I3 => \corse_dec_reg[1]_22\(2),
      I4 => dqs_count_r(0),
      I5 => \corse_dec_reg[0]_21\(2),
      O => \corse_dec[0][2]_i_11_n_0\
    );
\corse_dec[0][2]_i_12\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \corse_dec_reg[7]_28\(2),
      I1 => \corse_dec_reg[6]_27\(2),
      I2 => dqs_count_r(1),
      I3 => \corse_dec_reg[5]_26\(2),
      I4 => dqs_count_r(0),
      I5 => \corse_dec_reg[4]_25\(2),
      O => \corse_dec[0][2]_i_12_n_0\
    );
\corse_dec[0][2]_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"BF"
    )
        port map (
      I0 => \^fsm_sequential_wl_state_r_reg[4]_0\(0),
      I1 => \^fsm_sequential_wl_state_r_reg[4]_0\(1),
      I2 => \corse_dec_reg[0][2]_i_10_n_0\,
      O => \corse_dec[0][2]_i_4_n_0\
    );
\corse_dec[0][2]_i_5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFDFFF"
    )
        port map (
      I0 => \wl_state_r__0\(1),
      I1 => \wl_state_r__0\(0),
      I2 => \^fsm_sequential_wl_state_r_reg[4]_0\(1),
      I3 => \wl_state_r__0\(2),
      I4 => \^fsm_sequential_wl_state_r_reg[4]_0\(0),
      O => \corse_dec[0][2]_i_5_n_0\
    );
\corse_dec[0][2]_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \corse_dec_reg[3]_24\(1),
      I1 => \corse_dec_reg[2]_23\(1),
      I2 => dqs_count_r(1),
      I3 => \corse_dec_reg[1]_22\(1),
      I4 => dqs_count_r(0),
      I5 => \corse_dec_reg[0]_21\(1),
      O => \corse_dec[0][2]_i_6_n_0\
    );
\corse_dec[0][2]_i_7\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \corse_dec_reg[7]_28\(1),
      I1 => \corse_dec_reg[6]_27\(1),
      I2 => dqs_count_r(1),
      I3 => \corse_dec_reg[5]_26\(1),
      I4 => dqs_count_r(0),
      I5 => \corse_dec_reg[4]_25\(1),
      O => \corse_dec[0][2]_i_7_n_0\
    );
\corse_dec[0][2]_i_8\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \corse_dec_reg[3]_24\(0),
      I1 => \corse_dec_reg[2]_23\(0),
      I2 => dqs_count_r(1),
      I3 => \corse_dec_reg[1]_22\(0),
      I4 => dqs_count_r(0),
      I5 => \corse_dec_reg[0]_21\(0),
      O => \corse_dec[0][2]_i_8_n_0\
    );
\corse_dec[0][2]_i_9\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \corse_dec_reg[7]_28\(0),
      I1 => \corse_dec_reg[6]_27\(0),
      I2 => dqs_count_r(1),
      I3 => \corse_dec_reg[5]_26\(0),
      I4 => dqs_count_r(0),
      I5 => \corse_dec_reg[4]_25\(0),
      O => \corse_dec[0][2]_i_9_n_0\
    );
\corse_dec[1][0]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FB08"
    )
        port map (
      I0 => corse_dec(0),
      I1 => \fine_inc[1][5]_i_3_n_0\,
      I2 => \corse_dec[0][2]_i_5_n_0\,
      I3 => \corse_dec_reg[1]_22\(0),
      O => \corse_dec[1][0]_i_1_n_0\
    );
\corse_dec[1][1]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FB08"
    )
        port map (
      I0 => corse_dec(1),
      I1 => \fine_inc[1][5]_i_3_n_0\,
      I2 => \corse_dec[0][2]_i_5_n_0\,
      I3 => \corse_dec_reg[1]_22\(1),
      O => \corse_dec[1][1]_i_1_n_0\
    );
\corse_dec[1][2]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFF0EFF00000E00"
    )
        port map (
      I0 => \corse_dec_reg[0][2]_i_2_n_0\,
      I1 => \corse_dec_reg[0][2]_i_3_n_0\,
      I2 => \corse_dec[0][2]_i_4_n_0\,
      I3 => \fine_inc[1][5]_i_3_n_0\,
      I4 => \corse_dec[0][2]_i_5_n_0\,
      I5 => \corse_dec_reg[1]_22\(2),
      O => \corse_dec[1][2]_i_1_n_0\
    );
\corse_dec[2][0]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FB08"
    )
        port map (
      I0 => corse_dec(0),
      I1 => \fine_inc[2][5]_i_3_n_0\,
      I2 => \corse_dec[0][2]_i_5_n_0\,
      I3 => \corse_dec_reg[2]_23\(0),
      O => \corse_dec[2][0]_i_1_n_0\
    );
\corse_dec[2][1]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FB08"
    )
        port map (
      I0 => corse_dec(1),
      I1 => \fine_inc[2][5]_i_3_n_0\,
      I2 => \corse_dec[0][2]_i_5_n_0\,
      I3 => \corse_dec_reg[2]_23\(1),
      O => \corse_dec[2][1]_i_1_n_0\
    );
\corse_dec[2][2]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFF0EFF00000E00"
    )
        port map (
      I0 => \corse_dec_reg[0][2]_i_2_n_0\,
      I1 => \corse_dec_reg[0][2]_i_3_n_0\,
      I2 => \corse_dec[0][2]_i_4_n_0\,
      I3 => \fine_inc[2][5]_i_3_n_0\,
      I4 => \corse_dec[0][2]_i_5_n_0\,
      I5 => \corse_dec_reg[2]_23\(2),
      O => \corse_dec[2][2]_i_1_n_0\
    );
\corse_dec[3][0]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FB08"
    )
        port map (
      I0 => corse_dec(0),
      I1 => \fine_inc[3][5]_i_3_n_0\,
      I2 => \corse_dec[0][2]_i_5_n_0\,
      I3 => \corse_dec_reg[3]_24\(0),
      O => \corse_dec[3][0]_i_1_n_0\
    );
\corse_dec[3][1]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FB08"
    )
        port map (
      I0 => corse_dec(1),
      I1 => \fine_inc[3][5]_i_3_n_0\,
      I2 => \corse_dec[0][2]_i_5_n_0\,
      I3 => \corse_dec_reg[3]_24\(1),
      O => \corse_dec[3][1]_i_1_n_0\
    );
\corse_dec[3][2]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFF0EFF00000E00"
    )
        port map (
      I0 => \corse_dec_reg[0][2]_i_2_n_0\,
      I1 => \corse_dec_reg[0][2]_i_3_n_0\,
      I2 => \corse_dec[0][2]_i_4_n_0\,
      I3 => \fine_inc[3][5]_i_3_n_0\,
      I4 => \corse_dec[0][2]_i_5_n_0\,
      I5 => \corse_dec_reg[3]_24\(2),
      O => \corse_dec[3][2]_i_1_n_0\
    );
\corse_dec[4][0]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FB08"
    )
        port map (
      I0 => corse_dec(0),
      I1 => \fine_inc[4][5]_i_3_n_0\,
      I2 => \corse_dec[0][2]_i_5_n_0\,
      I3 => \corse_dec_reg[4]_25\(0),
      O => \corse_dec[4][0]_i_1_n_0\
    );
\corse_dec[4][1]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FB08"
    )
        port map (
      I0 => corse_dec(1),
      I1 => \fine_inc[4][5]_i_3_n_0\,
      I2 => \corse_dec[0][2]_i_5_n_0\,
      I3 => \corse_dec_reg[4]_25\(1),
      O => \corse_dec[4][1]_i_1_n_0\
    );
\corse_dec[4][2]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFF0EFF00000E00"
    )
        port map (
      I0 => \corse_dec_reg[0][2]_i_2_n_0\,
      I1 => \corse_dec_reg[0][2]_i_3_n_0\,
      I2 => \corse_dec[0][2]_i_4_n_0\,
      I3 => \fine_inc[4][5]_i_3_n_0\,
      I4 => \corse_dec[0][2]_i_5_n_0\,
      I5 => \corse_dec_reg[4]_25\(2),
      O => \corse_dec[4][2]_i_1_n_0\
    );
\corse_dec[5][0]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FB08"
    )
        port map (
      I0 => corse_dec(0),
      I1 => \fine_inc[5][5]_i_3_n_0\,
      I2 => \corse_dec[0][2]_i_5_n_0\,
      I3 => \corse_dec_reg[5]_26\(0),
      O => \corse_dec[5][0]_i_1_n_0\
    );
\corse_dec[5][1]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FB08"
    )
        port map (
      I0 => corse_dec(1),
      I1 => \fine_inc[5][5]_i_3_n_0\,
      I2 => \corse_dec[0][2]_i_5_n_0\,
      I3 => \corse_dec_reg[5]_26\(1),
      O => \corse_dec[5][1]_i_1_n_0\
    );
\corse_dec[5][2]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFF0EFF00000E00"
    )
        port map (
      I0 => \corse_dec_reg[0][2]_i_2_n_0\,
      I1 => \corse_dec_reg[0][2]_i_3_n_0\,
      I2 => \corse_dec[0][2]_i_4_n_0\,
      I3 => \fine_inc[5][5]_i_3_n_0\,
      I4 => \corse_dec[0][2]_i_5_n_0\,
      I5 => \corse_dec_reg[5]_26\(2),
      O => \corse_dec[5][2]_i_1_n_0\
    );
\corse_dec[6][0]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FB08"
    )
        port map (
      I0 => corse_dec(0),
      I1 => \fine_inc[6][5]_i_3_n_0\,
      I2 => \corse_dec[0][2]_i_5_n_0\,
      I3 => \corse_dec_reg[6]_27\(0),
      O => \corse_dec[6][0]_i_1_n_0\
    );
\corse_dec[6][1]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FB08"
    )
        port map (
      I0 => corse_dec(1),
      I1 => \fine_inc[6][5]_i_3_n_0\,
      I2 => \corse_dec[0][2]_i_5_n_0\,
      I3 => \corse_dec_reg[6]_27\(1),
      O => \corse_dec[6][1]_i_1_n_0\
    );
\corse_dec[6][2]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFF0EFF00000E00"
    )
        port map (
      I0 => \corse_dec_reg[0][2]_i_2_n_0\,
      I1 => \corse_dec_reg[0][2]_i_3_n_0\,
      I2 => \corse_dec[0][2]_i_4_n_0\,
      I3 => \fine_inc[6][5]_i_3_n_0\,
      I4 => \corse_dec[0][2]_i_5_n_0\,
      I5 => \corse_dec_reg[6]_27\(2),
      O => \corse_dec[6][2]_i_1_n_0\
    );
\corse_dec[7][0]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FB08"
    )
        port map (
      I0 => corse_dec(0),
      I1 => \fine_inc[7][5]_i_3_n_0\,
      I2 => \corse_dec[0][2]_i_5_n_0\,
      I3 => \corse_dec_reg[7]_28\(0),
      O => \corse_dec[7][0]_i_1_n_0\
    );
\corse_dec[7][1]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FB08"
    )
        port map (
      I0 => corse_dec(1),
      I1 => \fine_inc[7][5]_i_3_n_0\,
      I2 => \corse_dec[0][2]_i_5_n_0\,
      I3 => \corse_dec_reg[7]_28\(1),
      O => \corse_dec[7][1]_i_1_n_0\
    );
\corse_dec[7][2]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFF0EFF00000E00"
    )
        port map (
      I0 => \corse_dec_reg[0][2]_i_2_n_0\,
      I1 => \corse_dec_reg[0][2]_i_3_n_0\,
      I2 => \corse_dec[0][2]_i_4_n_0\,
      I3 => \fine_inc[7][5]_i_3_n_0\,
      I4 => \corse_dec[0][2]_i_5_n_0\,
      I5 => \corse_dec_reg[7]_28\(2),
      O => \corse_dec[7][2]_i_1_n_0\
    );
\corse_dec_reg[0][0]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => '1',
      D => \corse_dec[0][0]_i_1_n_0\,
      Q => \corse_dec_reg[0]_21\(0),
      R => \corse_dec_reg[7][0]_0\(1)
    );
\corse_dec_reg[0][1]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => '1',
      D => \corse_dec[0][1]_i_1_n_0\,
      Q => \corse_dec_reg[0]_21\(1),
      R => \corse_dec_reg[7][0]_0\(1)
    );
\corse_dec_reg[0][2]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => '1',
      D => \corse_dec[0][2]_i_1_n_0\,
      Q => \corse_dec_reg[0]_21\(2),
      R => \corse_dec_reg[7][0]_0\(1)
    );
\corse_dec_reg[0][2]_i_10\: unisim.vcomponents.MUXF7
     port map (
      I0 => \corse_dec[0][2]_i_11_n_0\,
      I1 => \corse_dec[0][2]_i_12_n_0\,
      O => \corse_dec_reg[0][2]_i_10_n_0\,
      S => dqs_count_r(2)
    );
\corse_dec_reg[0][2]_i_2\: unisim.vcomponents.MUXF7
     port map (
      I0 => \corse_dec[0][2]_i_6_n_0\,
      I1 => \corse_dec[0][2]_i_7_n_0\,
      O => \corse_dec_reg[0][2]_i_2_n_0\,
      S => dqs_count_r(2)
    );
\corse_dec_reg[0][2]_i_3\: unisim.vcomponents.MUXF7
     port map (
      I0 => \corse_dec[0][2]_i_8_n_0\,
      I1 => \corse_dec[0][2]_i_9_n_0\,
      O => \corse_dec_reg[0][2]_i_3_n_0\,
      S => dqs_count_r(2)
    );
\corse_dec_reg[1][0]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => '1',
      D => \corse_dec[1][0]_i_1_n_0\,
      Q => \corse_dec_reg[1]_22\(0),
      R => \corse_dec_reg[7][0]_0\(1)
    );
\corse_dec_reg[1][1]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => '1',
      D => \corse_dec[1][1]_i_1_n_0\,
      Q => \corse_dec_reg[1]_22\(1),
      R => \corse_dec_reg[7][0]_0\(1)
    );
\corse_dec_reg[1][2]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => '1',
      D => \corse_dec[1][2]_i_1_n_0\,
      Q => \corse_dec_reg[1]_22\(2),
      R => \corse_dec_reg[7][0]_0\(1)
    );
\corse_dec_reg[2][0]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => '1',
      D => \corse_dec[2][0]_i_1_n_0\,
      Q => \corse_dec_reg[2]_23\(0),
      R => \corse_dec_reg[7][0]_0\(1)
    );
\corse_dec_reg[2][1]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => '1',
      D => \corse_dec[2][1]_i_1_n_0\,
      Q => \corse_dec_reg[2]_23\(1),
      R => \corse_dec_reg[7][0]_0\(1)
    );
\corse_dec_reg[2][2]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => '1',
      D => \corse_dec[2][2]_i_1_n_0\,
      Q => \corse_dec_reg[2]_23\(2),
      R => \corse_dec_reg[7][0]_0\(1)
    );
\corse_dec_reg[3][0]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => '1',
      D => \corse_dec[3][0]_i_1_n_0\,
      Q => \corse_dec_reg[3]_24\(0),
      R => \corse_dec_reg[7][0]_0\(1)
    );
\corse_dec_reg[3][1]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => '1',
      D => \corse_dec[3][1]_i_1_n_0\,
      Q => \corse_dec_reg[3]_24\(1),
      R => \corse_dec_reg[7][0]_0\(1)
    );
\corse_dec_reg[3][2]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => '1',
      D => \corse_dec[3][2]_i_1_n_0\,
      Q => \corse_dec_reg[3]_24\(2),
      R => \corse_dec_reg[7][0]_0\(1)
    );
\corse_dec_reg[4][0]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => '1',
      D => \corse_dec[4][0]_i_1_n_0\,
      Q => \corse_dec_reg[4]_25\(0),
      R => \corse_dec_reg[7][0]_0\(1)
    );
\corse_dec_reg[4][1]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => '1',
      D => \corse_dec[4][1]_i_1_n_0\,
      Q => \corse_dec_reg[4]_25\(1),
      R => \corse_dec_reg[7][0]_0\(1)
    );
\corse_dec_reg[4][2]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => '1',
      D => \corse_dec[4][2]_i_1_n_0\,
      Q => \corse_dec_reg[4]_25\(2),
      R => \corse_dec_reg[7][0]_0\(1)
    );
\corse_dec_reg[5][0]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => '1',
      D => \corse_dec[5][0]_i_1_n_0\,
      Q => \corse_dec_reg[5]_26\(0),
      R => \corse_dec_reg[7][0]_0\(1)
    );
\corse_dec_reg[5][1]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => '1',
      D => \corse_dec[5][1]_i_1_n_0\,
      Q => \corse_dec_reg[5]_26\(1),
      R => \corse_dec_reg[7][0]_0\(1)
    );
\corse_dec_reg[5][2]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => '1',
      D => \corse_dec[5][2]_i_1_n_0\,
      Q => \corse_dec_reg[5]_26\(2),
      R => \corse_dec_reg[7][0]_0\(1)
    );
\corse_dec_reg[6][0]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => '1',
      D => \corse_dec[6][0]_i_1_n_0\,
      Q => \corse_dec_reg[6]_27\(0),
      R => \corse_dec_reg[7][0]_0\(1)
    );
\corse_dec_reg[6][1]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => '1',
      D => \corse_dec[6][1]_i_1_n_0\,
      Q => \corse_dec_reg[6]_27\(1),
      R => \corse_dec_reg[7][0]_0\(1)
    );
\corse_dec_reg[6][2]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => '1',
      D => \corse_dec[6][2]_i_1_n_0\,
      Q => \corse_dec_reg[6]_27\(2),
      R => \corse_dec_reg[7][0]_0\(1)
    );
\corse_dec_reg[7][0]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => '1',
      D => \corse_dec[7][0]_i_1_n_0\,
      Q => \corse_dec_reg[7]_28\(0),
      R => \corse_dec_reg[7][0]_0\(1)
    );
\corse_dec_reg[7][1]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => '1',
      D => \corse_dec[7][1]_i_1_n_0\,
      Q => \corse_dec_reg[7]_28\(1),
      R => \corse_dec_reg[7][0]_0\(1)
    );
\corse_dec_reg[7][2]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => '1',
      D => \corse_dec[7][2]_i_1_n_0\,
      Q => \corse_dec_reg[7]_28\(2),
      R => \corse_dec_reg[7][0]_0\(1)
    );
\corse_inc[0][0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"BBBBFFBF88880080"
    )
        port map (
      I0 => corse_inc(0),
      I1 => \corse_inc[0][2]_i_3_n_0\,
      I2 => \fine_inc[0][5]_i_4_n_0\,
      I3 => \corse_inc[0][2]_i_4_n_0\,
      I4 => \corse_inc[0][2]_i_5_n_0\,
      I5 => \corse_inc_reg[0]_37\(0),
      O => \corse_inc[0][0]_i_1_n_0\
    );
\corse_inc[0][0]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"11B11111"
    )
        port map (
      I0 => \wl_state_r__0\(2),
      I1 => \corse_inc_reg[0][1]_i_3_n_0\,
      I2 => \^fsm_sequential_wl_state_r_reg[4]_0\(0),
      I3 => \^fsm_sequential_wl_state_r_reg[4]_0\(1),
      I4 => \final_coarse_tap_reg_n_0_[0][0]\,
      O => corse_inc(0)
    );
\corse_inc[0][1]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"BBBBFFBF88880080"
    )
        port map (
      I0 => corse_inc(1),
      I1 => \corse_inc[0][2]_i_3_n_0\,
      I2 => \fine_inc[0][5]_i_4_n_0\,
      I3 => \corse_inc[0][2]_i_4_n_0\,
      I4 => \corse_inc[0][2]_i_5_n_0\,
      I5 => \corse_inc_reg[0]_37\(1),
      O => \corse_inc[0][1]_i_1_n_0\
    );
\corse_inc[0][1]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"4141EB4141414141"
    )
        port map (
      I0 => \wl_state_r__0\(2),
      I1 => \corse_inc_reg[0][1]_i_3_n_0\,
      I2 => \corse_inc_reg[0][1]_i_4_n_0\,
      I3 => \^fsm_sequential_wl_state_r_reg[4]_0\(0),
      I4 => \^fsm_sequential_wl_state_r_reg[4]_0\(1),
      I5 => \final_coarse_tap_reg_n_0_[0][1]\,
      O => corse_inc(1)
    );
\corse_inc[0][1]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \corse_inc_reg[3]_40\(0),
      I1 => \corse_inc_reg[2]_39\(0),
      I2 => \^dqs_count_r_reg[1]_rep_0\,
      I3 => \corse_inc_reg[1]_38\(0),
      I4 => \^dqs_count_r_reg[0]_rep_0\,
      I5 => \corse_inc_reg[0]_37\(0),
      O => \corse_inc[0][1]_i_5_n_0\
    );
\corse_inc[0][1]_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \corse_inc_reg[7]_44\(0),
      I1 => \corse_inc_reg[6]_43\(0),
      I2 => \^dqs_count_r_reg[1]_rep_0\,
      I3 => \corse_inc_reg[5]_42\(0),
      I4 => \^dqs_count_r_reg[0]_rep_0\,
      I5 => \corse_inc_reg[4]_41\(0),
      O => \corse_inc[0][1]_i_6_n_0\
    );
\corse_inc[0][1]_i_7\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \corse_inc_reg[3]_40\(1),
      I1 => \corse_inc_reg[2]_39\(1),
      I2 => \^dqs_count_r_reg[1]_rep_0\,
      I3 => \corse_inc_reg[1]_38\(1),
      I4 => \^dqs_count_r_reg[0]_rep_0\,
      I5 => \corse_inc_reg[0]_37\(1),
      O => \corse_inc[0][1]_i_7_n_0\
    );
\corse_inc[0][1]_i_8\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \corse_inc_reg[7]_44\(1),
      I1 => \corse_inc_reg[6]_43\(1),
      I2 => \^dqs_count_r_reg[1]_rep_0\,
      I3 => \corse_inc_reg[5]_42\(1),
      I4 => \^dqs_count_r_reg[0]_rep_0\,
      I5 => \corse_inc_reg[4]_41\(1),
      O => \corse_inc[0][1]_i_8_n_0\
    );
\corse_inc[0][2]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"BBBBFFBF88880080"
    )
        port map (
      I0 => corse_inc(2),
      I1 => \corse_inc[0][2]_i_3_n_0\,
      I2 => \fine_inc[0][5]_i_4_n_0\,
      I3 => \corse_inc[0][2]_i_4_n_0\,
      I4 => \corse_inc[0][2]_i_5_n_0\,
      I5 => \corse_inc_reg[0]_37\(2),
      O => \corse_inc[0][2]_i_1_n_0\
    );
\corse_inc[0][2]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0606F60606060606"
    )
        port map (
      I0 => \corse_inc_reg[0][2]_i_6_n_0\,
      I1 => \corse_inc[0][2]_i_7_n_0\,
      I2 => \wl_state_r__0\(2),
      I3 => \^fsm_sequential_wl_state_r_reg[4]_0\(0),
      I4 => \^fsm_sequential_wl_state_r_reg[4]_0\(1),
      I5 => \final_coarse_tap_reg_n_0_[0][2]\,
      O => corse_inc(2)
    );
\corse_inc[0][2]_i_3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4000"
    )
        port map (
      I0 => \^fsm_sequential_wl_state_r_reg[4]_0\(1),
      I1 => \wl_state_r__0\(1),
      I2 => \^fsm_sequential_wl_state_r_reg[4]_0\(0),
      I3 => \wl_state_r__0\(0),
      O => \corse_inc[0][2]_i_3_n_0\
    );
\corse_inc[0][2]_i_4\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFFB"
    )
        port map (
      I0 => \FSM_sequential_wl_state_r[4]_i_11_n_0\,
      I1 => \^wr_level_done_r5\,
      I2 => wrlvl_byte_redo,
      I3 => \wl_state_r__0\(2),
      O => \corse_inc[0][2]_i_4_n_0\
    );
\corse_inc[0][2]_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"08"
    )
        port map (
      I0 => \wl_state_r__0\(2),
      I1 => wr_level_done_r4,
      I2 => \^wr_level_done_r5\,
      O => \corse_inc[0][2]_i_5_n_0\
    );
\corse_inc[0][2]_i_7\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \corse_inc_reg[0][1]_i_4_n_0\,
      I1 => \corse_inc_reg[0][1]_i_3_n_0\,
      O => \corse_inc[0][2]_i_7_n_0\
    );
\corse_inc[0][2]_i_8\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \corse_inc_reg[3]_40\(2),
      I1 => \corse_inc_reg[2]_39\(2),
      I2 => \^dqs_count_r_reg[1]_rep_0\,
      I3 => \corse_inc_reg[1]_38\(2),
      I4 => \^dqs_count_r_reg[0]_rep_0\,
      I5 => \corse_inc_reg[0]_37\(2),
      O => \corse_inc[0][2]_i_8_n_0\
    );
\corse_inc[0][2]_i_9\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \corse_inc_reg[7]_44\(2),
      I1 => \corse_inc_reg[6]_43\(2),
      I2 => \^dqs_count_r_reg[1]_rep_0\,
      I3 => \corse_inc_reg[5]_42\(2),
      I4 => \^dqs_count_r_reg[0]_rep_0\,
      I5 => \corse_inc_reg[4]_41\(2),
      O => \corse_inc[0][2]_i_9_n_0\
    );
\corse_inc[1][0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"BBBBFFBF88880080"
    )
        port map (
      I0 => \corse_inc[1][0]_i_2_n_0\,
      I1 => \corse_inc[0][2]_i_3_n_0\,
      I2 => \fine_inc[1][5]_i_3_n_0\,
      I3 => \corse_inc[0][2]_i_4_n_0\,
      I4 => \corse_inc[0][2]_i_5_n_0\,
      I5 => \corse_inc_reg[1]_38\(0),
      O => \corse_inc[1][0]_i_1_n_0\
    );
\corse_inc[1][0]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"11B11111"
    )
        port map (
      I0 => \wl_state_r__0\(2),
      I1 => \corse_inc_reg[0][1]_i_3_n_0\,
      I2 => \^fsm_sequential_wl_state_r_reg[4]_0\(0),
      I3 => \^fsm_sequential_wl_state_r_reg[4]_0\(1),
      I4 => \final_coarse_tap_reg_n_0_[1][0]\,
      O => \corse_inc[1][0]_i_2_n_0\
    );
\corse_inc[1][1]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"BBBBFFBF88880080"
    )
        port map (
      I0 => \corse_inc[1][1]_i_2_n_0\,
      I1 => \corse_inc[0][2]_i_3_n_0\,
      I2 => \fine_inc[1][5]_i_3_n_0\,
      I3 => \corse_inc[0][2]_i_4_n_0\,
      I4 => \corse_inc[0][2]_i_5_n_0\,
      I5 => \corse_inc_reg[1]_38\(1),
      O => \corse_inc[1][1]_i_1_n_0\
    );
\corse_inc[1][1]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"4141EB4141414141"
    )
        port map (
      I0 => \wl_state_r__0\(2),
      I1 => \corse_inc_reg[0][1]_i_3_n_0\,
      I2 => \corse_inc_reg[0][1]_i_4_n_0\,
      I3 => \^fsm_sequential_wl_state_r_reg[4]_0\(0),
      I4 => \^fsm_sequential_wl_state_r_reg[4]_0\(1),
      I5 => \final_coarse_tap_reg_n_0_[1][1]\,
      O => \corse_inc[1][1]_i_2_n_0\
    );
\corse_inc[1][2]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"BBBBFFBF88880080"
    )
        port map (
      I0 => \corse_inc[1][2]_i_2_n_0\,
      I1 => \corse_inc[0][2]_i_3_n_0\,
      I2 => \fine_inc[1][5]_i_3_n_0\,
      I3 => \corse_inc[0][2]_i_4_n_0\,
      I4 => \corse_inc[0][2]_i_5_n_0\,
      I5 => \corse_inc_reg[1]_38\(2),
      O => \corse_inc[1][2]_i_1_n_0\
    );
\corse_inc[1][2]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0606F60606060606"
    )
        port map (
      I0 => \corse_inc_reg[0][2]_i_6_n_0\,
      I1 => \corse_inc[0][2]_i_7_n_0\,
      I2 => \wl_state_r__0\(2),
      I3 => \^fsm_sequential_wl_state_r_reg[4]_0\(0),
      I4 => \^fsm_sequential_wl_state_r_reg[4]_0\(1),
      I5 => \final_coarse_tap_reg_n_0_[1][2]\,
      O => \corse_inc[1][2]_i_2_n_0\
    );
\corse_inc[2][0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"BBBBFFBF88880080"
    )
        port map (
      I0 => \corse_inc[2][0]_i_2_n_0\,
      I1 => \corse_inc[0][2]_i_3_n_0\,
      I2 => \fine_inc[2][5]_i_3_n_0\,
      I3 => \corse_inc[0][2]_i_4_n_0\,
      I4 => \corse_inc[0][2]_i_5_n_0\,
      I5 => \corse_inc_reg[2]_39\(0),
      O => \corse_inc[2][0]_i_1_n_0\
    );
\corse_inc[2][0]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"11B11111"
    )
        port map (
      I0 => \wl_state_r__0\(2),
      I1 => \corse_inc_reg[0][1]_i_3_n_0\,
      I2 => \^fsm_sequential_wl_state_r_reg[4]_0\(0),
      I3 => \^fsm_sequential_wl_state_r_reg[4]_0\(1),
      I4 => \final_coarse_tap_reg_n_0_[2][0]\,
      O => \corse_inc[2][0]_i_2_n_0\
    );
\corse_inc[2][1]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"BBBBFFBF88880080"
    )
        port map (
      I0 => \corse_inc[2][1]_i_2_n_0\,
      I1 => \corse_inc[0][2]_i_3_n_0\,
      I2 => \fine_inc[2][5]_i_3_n_0\,
      I3 => \corse_inc[0][2]_i_4_n_0\,
      I4 => \corse_inc[0][2]_i_5_n_0\,
      I5 => \corse_inc_reg[2]_39\(1),
      O => \corse_inc[2][1]_i_1_n_0\
    );
\corse_inc[2][1]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"4141EB4141414141"
    )
        port map (
      I0 => \wl_state_r__0\(2),
      I1 => \corse_inc_reg[0][1]_i_3_n_0\,
      I2 => \corse_inc_reg[0][1]_i_4_n_0\,
      I3 => \^fsm_sequential_wl_state_r_reg[4]_0\(0),
      I4 => \^fsm_sequential_wl_state_r_reg[4]_0\(1),
      I5 => \final_coarse_tap_reg_n_0_[2][1]\,
      O => \corse_inc[2][1]_i_2_n_0\
    );
\corse_inc[2][2]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"BBBBFFBF88880080"
    )
        port map (
      I0 => \corse_inc[2][2]_i_2_n_0\,
      I1 => \corse_inc[0][2]_i_3_n_0\,
      I2 => \fine_inc[2][5]_i_3_n_0\,
      I3 => \corse_inc[0][2]_i_4_n_0\,
      I4 => \corse_inc[0][2]_i_5_n_0\,
      I5 => \corse_inc_reg[2]_39\(2),
      O => \corse_inc[2][2]_i_1_n_0\
    );
\corse_inc[2][2]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0606F60606060606"
    )
        port map (
      I0 => \corse_inc_reg[0][2]_i_6_n_0\,
      I1 => \corse_inc[0][2]_i_7_n_0\,
      I2 => \wl_state_r__0\(2),
      I3 => \^fsm_sequential_wl_state_r_reg[4]_0\(0),
      I4 => \^fsm_sequential_wl_state_r_reg[4]_0\(1),
      I5 => \final_coarse_tap_reg_n_0_[2][2]\,
      O => \corse_inc[2][2]_i_2_n_0\
    );
\corse_inc[3][0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"BBBBFFBF88880080"
    )
        port map (
      I0 => \corse_inc[3][0]_i_2_n_0\,
      I1 => \corse_inc[0][2]_i_3_n_0\,
      I2 => \fine_inc[3][5]_i_3_n_0\,
      I3 => \corse_inc[0][2]_i_4_n_0\,
      I4 => \corse_inc[0][2]_i_5_n_0\,
      I5 => \corse_inc_reg[3]_40\(0),
      O => \corse_inc[3][0]_i_1_n_0\
    );
\corse_inc[3][0]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"11B11111"
    )
        port map (
      I0 => \wl_state_r__0\(2),
      I1 => \corse_inc_reg[0][1]_i_3_n_0\,
      I2 => \^fsm_sequential_wl_state_r_reg[4]_0\(0),
      I3 => \^fsm_sequential_wl_state_r_reg[4]_0\(1),
      I4 => \final_coarse_tap_reg_n_0_[3][0]\,
      O => \corse_inc[3][0]_i_2_n_0\
    );
\corse_inc[3][1]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"BBBBFFBF88880080"
    )
        port map (
      I0 => \corse_inc[3][1]_i_2_n_0\,
      I1 => \corse_inc[0][2]_i_3_n_0\,
      I2 => \fine_inc[3][5]_i_3_n_0\,
      I3 => \corse_inc[0][2]_i_4_n_0\,
      I4 => \corse_inc[0][2]_i_5_n_0\,
      I5 => \corse_inc_reg[3]_40\(1),
      O => \corse_inc[3][1]_i_1_n_0\
    );
\corse_inc[3][1]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"4141EB4141414141"
    )
        port map (
      I0 => \wl_state_r__0\(2),
      I1 => \corse_inc_reg[0][1]_i_3_n_0\,
      I2 => \corse_inc_reg[0][1]_i_4_n_0\,
      I3 => \^fsm_sequential_wl_state_r_reg[4]_0\(0),
      I4 => \^fsm_sequential_wl_state_r_reg[4]_0\(1),
      I5 => \final_coarse_tap_reg_n_0_[3][1]\,
      O => \corse_inc[3][1]_i_2_n_0\
    );
\corse_inc[3][2]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"BBBBFFBF88880080"
    )
        port map (
      I0 => \corse_inc[3][2]_i_2_n_0\,
      I1 => \corse_inc[0][2]_i_3_n_0\,
      I2 => \fine_inc[3][5]_i_3_n_0\,
      I3 => \corse_inc[0][2]_i_4_n_0\,
      I4 => \corse_inc[0][2]_i_5_n_0\,
      I5 => \corse_inc_reg[3]_40\(2),
      O => \corse_inc[3][2]_i_1_n_0\
    );
\corse_inc[3][2]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0606F60606060606"
    )
        port map (
      I0 => \corse_inc_reg[0][2]_i_6_n_0\,
      I1 => \corse_inc[0][2]_i_7_n_0\,
      I2 => \wl_state_r__0\(2),
      I3 => \^fsm_sequential_wl_state_r_reg[4]_0\(0),
      I4 => \^fsm_sequential_wl_state_r_reg[4]_0\(1),
      I5 => \final_coarse_tap_reg_n_0_[3][2]\,
      O => \corse_inc[3][2]_i_2_n_0\
    );
\corse_inc[4][0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"BBBBFFBF88880080"
    )
        port map (
      I0 => \corse_inc[4][0]_i_2_n_0\,
      I1 => \corse_inc[0][2]_i_3_n_0\,
      I2 => \fine_inc[4][5]_i_3_n_0\,
      I3 => \corse_inc[0][2]_i_4_n_0\,
      I4 => \corse_inc[0][2]_i_5_n_0\,
      I5 => \corse_inc_reg[4]_41\(0),
      O => \corse_inc[4][0]_i_1_n_0\
    );
\corse_inc[4][0]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"11B11111"
    )
        port map (
      I0 => \wl_state_r__0\(2),
      I1 => \corse_inc_reg[0][1]_i_3_n_0\,
      I2 => \^fsm_sequential_wl_state_r_reg[4]_0\(0),
      I3 => \^fsm_sequential_wl_state_r_reg[4]_0\(1),
      I4 => \final_coarse_tap_reg_n_0_[4][0]\,
      O => \corse_inc[4][0]_i_2_n_0\
    );
\corse_inc[4][1]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"BBBBFFBF88880080"
    )
        port map (
      I0 => \corse_inc[4][1]_i_2_n_0\,
      I1 => \corse_inc[0][2]_i_3_n_0\,
      I2 => \fine_inc[4][5]_i_3_n_0\,
      I3 => \corse_inc[0][2]_i_4_n_0\,
      I4 => \corse_inc[0][2]_i_5_n_0\,
      I5 => \corse_inc_reg[4]_41\(1),
      O => \corse_inc[4][1]_i_1_n_0\
    );
\corse_inc[4][1]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"4141EB4141414141"
    )
        port map (
      I0 => \wl_state_r__0\(2),
      I1 => \corse_inc_reg[0][1]_i_3_n_0\,
      I2 => \corse_inc_reg[0][1]_i_4_n_0\,
      I3 => \^fsm_sequential_wl_state_r_reg[4]_0\(0),
      I4 => \^fsm_sequential_wl_state_r_reg[4]_0\(1),
      I5 => \final_coarse_tap_reg_n_0_[4][1]\,
      O => \corse_inc[4][1]_i_2_n_0\
    );
\corse_inc[4][2]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"BBBBFFBF88880080"
    )
        port map (
      I0 => \corse_inc[4][2]_i_2_n_0\,
      I1 => \corse_inc[0][2]_i_3_n_0\,
      I2 => \fine_inc[4][5]_i_3_n_0\,
      I3 => \corse_inc[0][2]_i_4_n_0\,
      I4 => \corse_inc[0][2]_i_5_n_0\,
      I5 => \corse_inc_reg[4]_41\(2),
      O => \corse_inc[4][2]_i_1_n_0\
    );
\corse_inc[4][2]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0606F60606060606"
    )
        port map (
      I0 => \corse_inc_reg[0][2]_i_6_n_0\,
      I1 => \corse_inc[0][2]_i_7_n_0\,
      I2 => \wl_state_r__0\(2),
      I3 => \^fsm_sequential_wl_state_r_reg[4]_0\(0),
      I4 => \^fsm_sequential_wl_state_r_reg[4]_0\(1),
      I5 => \final_coarse_tap_reg_n_0_[4][2]\,
      O => \corse_inc[4][2]_i_2_n_0\
    );
\corse_inc[5][0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"BBBBFFBF88880080"
    )
        port map (
      I0 => \corse_inc[5][0]_i_2_n_0\,
      I1 => \corse_inc[0][2]_i_3_n_0\,
      I2 => \fine_inc[5][5]_i_3_n_0\,
      I3 => \corse_inc[0][2]_i_4_n_0\,
      I4 => \corse_inc[0][2]_i_5_n_0\,
      I5 => \corse_inc_reg[5]_42\(0),
      O => \corse_inc[5][0]_i_1_n_0\
    );
\corse_inc[5][0]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"11B11111"
    )
        port map (
      I0 => \wl_state_r__0\(2),
      I1 => \corse_inc_reg[0][1]_i_3_n_0\,
      I2 => \^fsm_sequential_wl_state_r_reg[4]_0\(0),
      I3 => \^fsm_sequential_wl_state_r_reg[4]_0\(1),
      I4 => \final_coarse_tap_reg_n_0_[5][0]\,
      O => \corse_inc[5][0]_i_2_n_0\
    );
\corse_inc[5][1]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"BBBBFFBF88880080"
    )
        port map (
      I0 => \corse_inc[5][1]_i_2_n_0\,
      I1 => \corse_inc[0][2]_i_3_n_0\,
      I2 => \fine_inc[5][5]_i_3_n_0\,
      I3 => \corse_inc[0][2]_i_4_n_0\,
      I4 => \corse_inc[0][2]_i_5_n_0\,
      I5 => \corse_inc_reg[5]_42\(1),
      O => \corse_inc[5][1]_i_1_n_0\
    );
\corse_inc[5][1]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"4141EB4141414141"
    )
        port map (
      I0 => \wl_state_r__0\(2),
      I1 => \corse_inc_reg[0][1]_i_3_n_0\,
      I2 => \corse_inc_reg[0][1]_i_4_n_0\,
      I3 => \^fsm_sequential_wl_state_r_reg[4]_0\(0),
      I4 => \^fsm_sequential_wl_state_r_reg[4]_0\(1),
      I5 => \final_coarse_tap_reg_n_0_[5][1]\,
      O => \corse_inc[5][1]_i_2_n_0\
    );
\corse_inc[5][2]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"BBBBFFBF88880080"
    )
        port map (
      I0 => \corse_inc[5][2]_i_2_n_0\,
      I1 => \corse_inc[0][2]_i_3_n_0\,
      I2 => \fine_inc[5][5]_i_3_n_0\,
      I3 => \corse_inc[0][2]_i_4_n_0\,
      I4 => \corse_inc[0][2]_i_5_n_0\,
      I5 => \corse_inc_reg[5]_42\(2),
      O => \corse_inc[5][2]_i_1_n_0\
    );
\corse_inc[5][2]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0606F60606060606"
    )
        port map (
      I0 => \corse_inc_reg[0][2]_i_6_n_0\,
      I1 => \corse_inc[0][2]_i_7_n_0\,
      I2 => \wl_state_r__0\(2),
      I3 => \^fsm_sequential_wl_state_r_reg[4]_0\(0),
      I4 => \^fsm_sequential_wl_state_r_reg[4]_0\(1),
      I5 => \final_coarse_tap_reg_n_0_[5][2]\,
      O => \corse_inc[5][2]_i_2_n_0\
    );
\corse_inc[6][0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"BBBBFFBF88880080"
    )
        port map (
      I0 => \corse_inc[6][0]_i_2_n_0\,
      I1 => \corse_inc[0][2]_i_3_n_0\,
      I2 => \fine_inc[6][5]_i_3_n_0\,
      I3 => \corse_inc[0][2]_i_4_n_0\,
      I4 => \corse_inc[0][2]_i_5_n_0\,
      I5 => \corse_inc_reg[6]_43\(0),
      O => \corse_inc[6][0]_i_1_n_0\
    );
\corse_inc[6][0]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"11B11111"
    )
        port map (
      I0 => \wl_state_r__0\(2),
      I1 => \corse_inc_reg[0][1]_i_3_n_0\,
      I2 => \^fsm_sequential_wl_state_r_reg[4]_0\(0),
      I3 => \^fsm_sequential_wl_state_r_reg[4]_0\(1),
      I4 => \final_coarse_tap_reg_n_0_[6][0]\,
      O => \corse_inc[6][0]_i_2_n_0\
    );
\corse_inc[6][1]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"BBBBFFBF88880080"
    )
        port map (
      I0 => \corse_inc[6][1]_i_2_n_0\,
      I1 => \corse_inc[0][2]_i_3_n_0\,
      I2 => \fine_inc[6][5]_i_3_n_0\,
      I3 => \corse_inc[0][2]_i_4_n_0\,
      I4 => \corse_inc[0][2]_i_5_n_0\,
      I5 => \corse_inc_reg[6]_43\(1),
      O => \corse_inc[6][1]_i_1_n_0\
    );
\corse_inc[6][1]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"4141EB4141414141"
    )
        port map (
      I0 => \wl_state_r__0\(2),
      I1 => \corse_inc_reg[0][1]_i_3_n_0\,
      I2 => \corse_inc_reg[0][1]_i_4_n_0\,
      I3 => \^fsm_sequential_wl_state_r_reg[4]_0\(0),
      I4 => \^fsm_sequential_wl_state_r_reg[4]_0\(1),
      I5 => \final_coarse_tap_reg_n_0_[6][1]\,
      O => \corse_inc[6][1]_i_2_n_0\
    );
\corse_inc[6][2]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"BBBBFFBF88880080"
    )
        port map (
      I0 => \corse_inc[6][2]_i_2_n_0\,
      I1 => \corse_inc[0][2]_i_3_n_0\,
      I2 => \fine_inc[6][5]_i_3_n_0\,
      I3 => \corse_inc[0][2]_i_4_n_0\,
      I4 => \corse_inc[0][2]_i_5_n_0\,
      I5 => \corse_inc_reg[6]_43\(2),
      O => \corse_inc[6][2]_i_1_n_0\
    );
\corse_inc[6][2]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0606F60606060606"
    )
        port map (
      I0 => \corse_inc_reg[0][2]_i_6_n_0\,
      I1 => \corse_inc[0][2]_i_7_n_0\,
      I2 => \wl_state_r__0\(2),
      I3 => \^fsm_sequential_wl_state_r_reg[4]_0\(0),
      I4 => \^fsm_sequential_wl_state_r_reg[4]_0\(1),
      I5 => \final_coarse_tap_reg_n_0_[6][2]\,
      O => \corse_inc[6][2]_i_2_n_0\
    );
\corse_inc[7][0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"BBBBFFBF88880080"
    )
        port map (
      I0 => \corse_inc[7][0]_i_2_n_0\,
      I1 => \corse_inc[0][2]_i_3_n_0\,
      I2 => \fine_inc[7][5]_i_3_n_0\,
      I3 => \corse_inc[0][2]_i_4_n_0\,
      I4 => \corse_inc[0][2]_i_5_n_0\,
      I5 => \corse_inc_reg[7]_44\(0),
      O => \corse_inc[7][0]_i_1_n_0\
    );
\corse_inc[7][0]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"11B11111"
    )
        port map (
      I0 => \wl_state_r__0\(2),
      I1 => \corse_inc_reg[0][1]_i_3_n_0\,
      I2 => \^fsm_sequential_wl_state_r_reg[4]_0\(0),
      I3 => \^fsm_sequential_wl_state_r_reg[4]_0\(1),
      I4 => \final_coarse_tap_reg_n_0_[7][0]\,
      O => \corse_inc[7][0]_i_2_n_0\
    );
\corse_inc[7][1]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"BBBBFFBF88880080"
    )
        port map (
      I0 => \corse_inc[7][1]_i_2_n_0\,
      I1 => \corse_inc[0][2]_i_3_n_0\,
      I2 => \fine_inc[7][5]_i_3_n_0\,
      I3 => \corse_inc[0][2]_i_4_n_0\,
      I4 => \corse_inc[0][2]_i_5_n_0\,
      I5 => \corse_inc_reg[7]_44\(1),
      O => \corse_inc[7][1]_i_1_n_0\
    );
\corse_inc[7][1]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"4141EB4141414141"
    )
        port map (
      I0 => \wl_state_r__0\(2),
      I1 => \corse_inc_reg[0][1]_i_3_n_0\,
      I2 => \corse_inc_reg[0][1]_i_4_n_0\,
      I3 => \^fsm_sequential_wl_state_r_reg[4]_0\(0),
      I4 => \^fsm_sequential_wl_state_r_reg[4]_0\(1),
      I5 => \final_coarse_tap_reg_n_0_[7][1]\,
      O => \corse_inc[7][1]_i_2_n_0\
    );
\corse_inc[7][2]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"BBBBFFBF88880080"
    )
        port map (
      I0 => \corse_inc[7][2]_i_2_n_0\,
      I1 => \corse_inc[0][2]_i_3_n_0\,
      I2 => \fine_inc[7][5]_i_3_n_0\,
      I3 => \corse_inc[0][2]_i_4_n_0\,
      I4 => \corse_inc[0][2]_i_5_n_0\,
      I5 => \corse_inc_reg[7]_44\(2),
      O => \corse_inc[7][2]_i_1_n_0\
    );
\corse_inc[7][2]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0606F60606060606"
    )
        port map (
      I0 => \corse_inc_reg[0][2]_i_6_n_0\,
      I1 => \corse_inc[0][2]_i_7_n_0\,
      I2 => \wl_state_r__0\(2),
      I3 => \^fsm_sequential_wl_state_r_reg[4]_0\(0),
      I4 => \^fsm_sequential_wl_state_r_reg[4]_0\(1),
      I5 => \final_coarse_tap_reg_n_0_[7][2]\,
      O => \corse_inc[7][2]_i_2_n_0\
    );
\corse_inc_reg[0][0]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => '1',
      D => \corse_inc[0][0]_i_1_n_0\,
      Q => \corse_inc_reg[0]_37\(0),
      R => \corse_inc_reg[6][2]_0\(0)
    );
\corse_inc_reg[0][1]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => '1',
      D => \corse_inc[0][1]_i_1_n_0\,
      Q => \corse_inc_reg[0]_37\(1),
      R => \corse_inc_reg[6][2]_0\(0)
    );
\corse_inc_reg[0][1]_i_3\: unisim.vcomponents.MUXF7
     port map (
      I0 => \corse_inc[0][1]_i_5_n_0\,
      I1 => \corse_inc[0][1]_i_6_n_0\,
      O => \corse_inc_reg[0][1]_i_3_n_0\,
      S => dqs_count_r(2)
    );
\corse_inc_reg[0][1]_i_4\: unisim.vcomponents.MUXF7
     port map (
      I0 => \corse_inc[0][1]_i_7_n_0\,
      I1 => \corse_inc[0][1]_i_8_n_0\,
      O => \corse_inc_reg[0][1]_i_4_n_0\,
      S => dqs_count_r(2)
    );
\corse_inc_reg[0][2]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => '1',
      D => \corse_inc[0][2]_i_1_n_0\,
      Q => \corse_inc_reg[0]_37\(2),
      R => \corse_inc_reg[6][2]_0\(1)
    );
\corse_inc_reg[0][2]_i_6\: unisim.vcomponents.MUXF7
     port map (
      I0 => \corse_inc[0][2]_i_8_n_0\,
      I1 => \corse_inc[0][2]_i_9_n_0\,
      O => \corse_inc_reg[0][2]_i_6_n_0\,
      S => dqs_count_r(2)
    );
\corse_inc_reg[1][0]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => '1',
      D => \corse_inc[1][0]_i_1_n_0\,
      Q => \corse_inc_reg[1]_38\(0),
      R => \corse_inc_reg[6][2]_0\(0)
    );
\corse_inc_reg[1][1]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => '1',
      D => \corse_inc[1][1]_i_1_n_0\,
      Q => \corse_inc_reg[1]_38\(1),
      R => \corse_inc_reg[6][2]_0\(0)
    );
\corse_inc_reg[1][2]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => '1',
      D => \corse_inc[1][2]_i_1_n_0\,
      Q => \corse_inc_reg[1]_38\(2),
      R => \corse_inc_reg[6][2]_0\(1)
    );
\corse_inc_reg[2][0]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => '1',
      D => \corse_inc[2][0]_i_1_n_0\,
      Q => \corse_inc_reg[2]_39\(0),
      R => \corse_inc_reg[6][2]_0\(0)
    );
\corse_inc_reg[2][1]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => '1',
      D => \corse_inc[2][1]_i_1_n_0\,
      Q => \corse_inc_reg[2]_39\(1),
      R => \corse_inc_reg[6][2]_0\(0)
    );
\corse_inc_reg[2][2]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => '1',
      D => \corse_inc[2][2]_i_1_n_0\,
      Q => \corse_inc_reg[2]_39\(2),
      R => \corse_inc_reg[6][2]_0\(1)
    );
\corse_inc_reg[3][0]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => '1',
      D => \corse_inc[3][0]_i_1_n_0\,
      Q => \corse_inc_reg[3]_40\(0),
      R => \corse_inc_reg[6][2]_0\(0)
    );
\corse_inc_reg[3][1]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => '1',
      D => \corse_inc[3][1]_i_1_n_0\,
      Q => \corse_inc_reg[3]_40\(1),
      R => \corse_inc_reg[6][2]_0\(0)
    );
\corse_inc_reg[3][2]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => '1',
      D => \corse_inc[3][2]_i_1_n_0\,
      Q => \corse_inc_reg[3]_40\(2),
      R => \corse_inc_reg[6][2]_0\(1)
    );
\corse_inc_reg[4][0]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => '1',
      D => \corse_inc[4][0]_i_1_n_0\,
      Q => \corse_inc_reg[4]_41\(0),
      R => \corse_inc_reg[6][2]_0\(0)
    );
\corse_inc_reg[4][1]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => '1',
      D => \corse_inc[4][1]_i_1_n_0\,
      Q => \corse_inc_reg[4]_41\(1),
      R => \corse_inc_reg[6][2]_0\(0)
    );
\corse_inc_reg[4][2]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => '1',
      D => \corse_inc[4][2]_i_1_n_0\,
      Q => \corse_inc_reg[4]_41\(2),
      R => \corse_inc_reg[6][2]_0\(1)
    );
\corse_inc_reg[5][0]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => '1',
      D => \corse_inc[5][0]_i_1_n_0\,
      Q => \corse_inc_reg[5]_42\(0),
      R => \corse_inc_reg[6][2]_0\(0)
    );
\corse_inc_reg[5][1]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => '1',
      D => \corse_inc[5][1]_i_1_n_0\,
      Q => \corse_inc_reg[5]_42\(1),
      R => \corse_inc_reg[6][2]_0\(0)
    );
\corse_inc_reg[5][2]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => '1',
      D => \corse_inc[5][2]_i_1_n_0\,
      Q => \corse_inc_reg[5]_42\(2),
      R => \corse_inc_reg[6][2]_0\(1)
    );
\corse_inc_reg[6][0]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => '1',
      D => \corse_inc[6][0]_i_1_n_0\,
      Q => \corse_inc_reg[6]_43\(0),
      R => \corse_inc_reg[6][2]_0\(0)
    );
\corse_inc_reg[6][1]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => '1',
      D => \corse_inc[6][1]_i_1_n_0\,
      Q => \corse_inc_reg[6]_43\(1),
      R => \corse_inc_reg[6][2]_0\(0)
    );
\corse_inc_reg[6][2]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => '1',
      D => \corse_inc[6][2]_i_1_n_0\,
      Q => \corse_inc_reg[6]_43\(2),
      R => \corse_inc_reg[6][2]_0\(1)
    );
\corse_inc_reg[7][0]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => '1',
      D => \corse_inc[7][0]_i_1_n_0\,
      Q => \corse_inc_reg[7]_44\(0),
      R => \corse_inc_reg[6][2]_0\(0)
    );
\corse_inc_reg[7][1]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => '1',
      D => \corse_inc[7][1]_i_1_n_0\,
      Q => \corse_inc_reg[7]_44\(1),
      R => \corse_inc_reg[6][2]_0\(0)
    );
\corse_inc_reg[7][2]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => '1',
      D => \corse_inc[7][2]_i_1_n_0\,
      Q => \corse_inc_reg[7]_44\(2),
      R => \corse_inc_reg[6][2]_0\(1)
    );
\ctl_lane_cnt[1]_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^dqs_po_dec_done\,
      I1 => pi_fine_dly_dec_done,
      O => cmd_delay_start0
    );
\delaydec_cnt_r[5]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFF7"
    )
        port map (
      I0 => \^dqs_po_dec_done\,
      I1 => pi_fine_dly_dec_done,
      I2 => \single_rank.done_dqs_dec_reg_0\,
      I3 => delaydec_cnt_r10_in,
      O => SS(0)
    );
dq_cnt_inc_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"005DFFFF005D0000"
    )
        port map (
      I0 => \wl_state_r__0\(2),
      I1 => dq_cnt_inc_i_2_n_0,
      I2 => wrlvl_byte_redo,
      I3 => \fine_inc[7][5]_i_3_n_0\,
      I4 => dq_cnt_inc_i_3_n_0,
      I5 => p_0_in,
      O => dq_cnt_inc_i_1_n_0
    );
dq_cnt_inc_i_2: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \^fsm_sequential_wl_state_r_reg[4]_0\(1),
      I1 => \^fsm_sequential_wl_state_r_reg[4]_0\(0),
      O => dq_cnt_inc_i_2_n_0
    );
dq_cnt_inc_i_3: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000042"
    )
        port map (
      I0 => \wl_state_r__0\(1),
      I1 => \^fsm_sequential_wl_state_r_reg[4]_0\(1),
      I2 => \wl_state_r__0\(2),
      I3 => \wl_state_r__0\(0),
      I4 => \^fsm_sequential_wl_state_r_reg[4]_0\(0),
      O => dq_cnt_inc_i_3_n_0
    );
dq_cnt_inc_reg: unisim.vcomponents.FDSE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => '1',
      D => dq_cnt_inc_i_1_n_0,
      Q => p_0_in,
      S => \corse_inc_reg[6][2]_0\(0)
    );
\dqs_count_r[0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFF200F2"
    )
        port map (
      I0 => dqs_count_r(0),
      I1 => \dqs_count_r[0]_i_2_n_0\,
      I2 => \dqs_count_r[0]_i_3_n_0\,
      I3 => \^fsm_sequential_wl_state_r_reg[4]_0\(1),
      I4 => \dqs_count_r[0]_i_4_n_0\,
      I5 => \dqs_count_r[0]_i_5_n_0\,
      O => \dqs_count_r[0]_i_1_n_0\
    );
\dqs_count_r[0]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFF7777777F"
    )
        port map (
      I0 => \wl_state_r__0\(1),
      I1 => \wl_state_r__0\(0),
      I2 => wrlvl_byte_redo,
      I3 => p_0_in,
      I4 => \wl_state_r__0\(2),
      I5 => \corse_inc[0][2]_i_5_n_0\,
      O => \dqs_count_r[0]_i_2_n_0\
    );
\dqs_count_r[0]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000AC000000"
    )
        port map (
      I0 => \dqs_count_r_reg[3]_1\(0),
      I1 => dqs_count_r(0),
      I2 => done_dqs_dec238_out,
      I3 => \wl_state_r__0\(2),
      I4 => \wl_state_r__0\(1),
      I5 => \wl_state_r__0\(0),
      O => \dqs_count_r[0]_i_3_n_0\
    );
\dqs_count_r[0]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000F0DAC3DA"
    )
        port map (
      I0 => \fine_inc[0][5]_i_3_n_0\,
      I1 => \fine_inc[7][5]_i_3_n_0\,
      I2 => dqs_count_r(0),
      I3 => \wl_state_r__0\(2),
      I4 => wrlvl_byte_redo,
      I5 => \^fsm_sequential_wl_state_r_reg[4]_0\(0),
      O => \dqs_count_r[0]_i_4_n_0\
    );
\dqs_count_r[0]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F8780000FF0F0000"
    )
        port map (
      I0 => \dqs_count_r[3]_i_11_n_0\,
      I1 => \fine_inc[0][5]_i_3_n_0\,
      I2 => dqs_count_r(0),
      I3 => \fine_inc[7][5]_i_3_n_0\,
      I4 => \dqs_count_r[3]_i_12_n_0\,
      I5 => \^fsm_sequential_wl_state_r_reg[4]_0\(0),
      O => \dqs_count_r[0]_i_5_n_0\
    );
\dqs_count_r[1]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFF55554055"
    )
        port map (
      I0 => \dqs_count_r[1]_i_2_n_0\,
      I1 => \dqs_count_r[3]_i_4_n_0\,
      I2 => \dqs_count_r[1]_i_3_n_0\,
      I3 => \^fsm_sequential_wl_state_r_reg[4]_0\(1),
      I4 => \dqs_count_r[1]_i_4_n_0\,
      I5 => \dqs_count_r[1]_i_5_n_0\,
      O => \dqs_count_r[1]_i_1_n_0\
    );
\dqs_count_r[1]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000DD0D"
    )
        port map (
      I0 => dqs_count_r(1),
      I1 => \dqs_count_r[3]_i_8_n_0\,
      I2 => \dqs_count_r_reg[3]_1\(1),
      I3 => \dqs_count_r[3]_i_9_n_0\,
      I4 => \^fsm_sequential_wl_state_r_reg[4]_0\(1),
      O => \dqs_count_r[1]_i_2_n_0\
    );
\dqs_count_r[1]_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"66E6CCCC"
    )
        port map (
      I0 => dqs_count_r(0),
      I1 => dqs_count_r(1),
      I2 => \^dqs_count_r_reg[2]_rep__0_0\,
      I3 => \^dqs_count_r_reg[3]_0\(0),
      I4 => \fine_inc[0][5]_i_3_n_0\,
      O => \dqs_count_r[1]_i_3_n_0\
    );
\dqs_count_r[1]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"4400440044000440"
    )
        port map (
      I0 => \^fsm_sequential_wl_state_r_reg[4]_0\(0),
      I1 => \wl_state_r__0\(2),
      I2 => dqs_count_r(0),
      I3 => dqs_count_r(1),
      I4 => \fine_inc[7][5]_i_3_n_0\,
      I5 => wrlvl_byte_redo,
      O => \dqs_count_r[1]_i_4_n_0\
    );
\dqs_count_r[1]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"4CEC000000FF0000"
    )
        port map (
      I0 => \dqs_count_r[3]_i_11_n_0\,
      I1 => dqs_count_r(1),
      I2 => \fine_inc[0][5]_i_3_n_0\,
      I3 => \dqs_count_r[1]_i_6_n_0\,
      I4 => \dqs_count_r[3]_i_12_n_0\,
      I5 => \^fsm_sequential_wl_state_r_reg[4]_0\(0),
      O => \dqs_count_r[1]_i_5_n_0\
    );
\dqs_count_r[1]_i_6\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9919"
    )
        port map (
      I0 => dqs_count_r(0),
      I1 => dqs_count_r(1),
      I2 => \^dqs_count_r_reg[2]_rep__0_0\,
      I3 => \^dqs_count_r_reg[3]_0\(0),
      O => \dqs_count_r[1]_i_6_n_0\
    );
\dqs_count_r[1]_rep_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFF55554055"
    )
        port map (
      I0 => \dqs_count_r[1]_i_2_n_0\,
      I1 => \dqs_count_r[3]_i_4_n_0\,
      I2 => \dqs_count_r[1]_i_3_n_0\,
      I3 => \^fsm_sequential_wl_state_r_reg[4]_0\(1),
      I4 => \dqs_count_r[1]_i_4_n_0\,
      I5 => \dqs_count_r[1]_i_5_n_0\,
      O => \dqs_count_r[1]_rep_i_1_n_0\
    );
\dqs_count_r[2]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFF2E22"
    )
        port map (
      I0 => \dqs_count_r[2]_i_2_n_0\,
      I1 => \^fsm_sequential_wl_state_r_reg[4]_0\(1),
      I2 => \^fsm_sequential_wl_state_r_reg[4]_0\(0),
      I3 => \dqs_count_r[2]_i_3_n_0\,
      I4 => \dqs_count_r[2]_i_4_n_0\,
      O => \dqs_count_r[2]_i_1_n_0\
    );
\dqs_count_r[2]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FF80A280A280A280"
    )
        port map (
      I0 => \^fsm_sequential_wl_state_r_reg[2]_0\,
      I1 => done_dqs_dec238_out,
      I2 => \dqs_count_r_reg[3]_1\(2),
      I3 => \dqs_count_r_reg[2]_rep_n_0\,
      I4 => \dqs_count_r[2]_i_5_n_0\,
      I5 => \dqs_count_r[2]_i_6_n_0\,
      O => \dqs_count_r[2]_i_2_n_0\
    );
\dqs_count_r[2]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FF8FFFBF00770044"
    )
        port map (
      I0 => wrlvl_byte_redo,
      I1 => \wl_state_r__0\(2),
      I2 => \^dqs_count_r_reg[3]_0\(0),
      I3 => \dqs_count_r[2]_i_7_n_0\,
      I4 => \fine_inc[0][5]_i_3_n_0\,
      I5 => \^dqs_count_r_reg[2]_rep__0_0\,
      O => \dqs_count_r[2]_i_3_n_0\
    );
\dqs_count_r[2]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"4CEC000000FF0000"
    )
        port map (
      I0 => \dqs_count_r[3]_i_11_n_0\,
      I1 => \^dqs_count_r_reg[2]_rep__0_0\,
      I2 => \fine_inc[0][5]_i_3_n_0\,
      I3 => \dqs_count_r[2]_i_8_n_0\,
      I4 => \dqs_count_r[3]_i_12_n_0\,
      I5 => \^fsm_sequential_wl_state_r_reg[4]_0\(0),
      O => \dqs_count_r[2]_i_4_n_0\
    );
\dqs_count_r[2]_i_5\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \wl_state_r__0\(0),
      I1 => \wl_state_r__0\(1),
      O => \dqs_count_r[2]_i_5_n_0\
    );
\dqs_count_r[2]_i_6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"BFBFBFB0"
    )
        port map (
      I0 => \^wr_level_done_r5\,
      I1 => wr_level_done_r4,
      I2 => \wl_state_r__0\(2),
      I3 => p_0_in,
      I4 => wrlvl_byte_redo,
      O => \dqs_count_r[2]_i_6_n_0\
    );
\dqs_count_r[2]_i_7\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"7"
    )
        port map (
      I0 => dqs_count_r(1),
      I1 => dqs_count_r(0),
      O => \dqs_count_r[2]_i_7_n_0\
    );
\dqs_count_r[2]_i_8\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"803F"
    )
        port map (
      I0 => \^dqs_count_r_reg[3]_0\(0),
      I1 => dqs_count_r(1),
      I2 => dqs_count_r(0),
      I3 => \^dqs_count_r_reg[2]_rep__0_0\,
      O => \dqs_count_r[2]_i_8_n_0\
    );
\dqs_count_r[2]_rep__0_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFF2E22"
    )
        port map (
      I0 => \dqs_count_r[2]_i_2_n_0\,
      I1 => \^fsm_sequential_wl_state_r_reg[4]_0\(1),
      I2 => \^fsm_sequential_wl_state_r_reg[4]_0\(0),
      I3 => \dqs_count_r[2]_i_3_n_0\,
      I4 => \dqs_count_r[2]_i_4_n_0\,
      O => \dqs_count_r[2]_rep__0_i_1_n_0\
    );
\dqs_count_r[2]_rep_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFF2E22"
    )
        port map (
      I0 => \dqs_count_r[2]_i_2_n_0\,
      I1 => \^fsm_sequential_wl_state_r_reg[4]_0\(1),
      I2 => \^fsm_sequential_wl_state_r_reg[4]_0\(0),
      I3 => \dqs_count_r[2]_i_3_n_0\,
      I4 => \dqs_count_r[2]_i_4_n_0\,
      O => \dqs_count_r[2]_rep_i_1_n_0\
    );
\dqs_count_r[3]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0282108A"
    )
        port map (
      I0 => \wl_state_r__0\(1),
      I1 => \^fsm_sequential_wl_state_r_reg[4]_0\(0),
      I2 => \wl_state_r__0\(2),
      I3 => \^fsm_sequential_wl_state_r_reg[4]_0\(1),
      I4 => \wl_state_r__0\(0),
      O => \dqs_count_r[3]_i_1_n_0\
    );
\dqs_count_r[3]_i_10\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"7F"
    )
        port map (
      I0 => dqs_count_r(0),
      I1 => dqs_count_r(1),
      I2 => \^dqs_count_r_reg[2]_rep__0_0\,
      O => \dqs_count_r[3]_i_10_n_0\
    );
\dqs_count_r[3]_i_11\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0400"
    )
        port map (
      I0 => \corse_inc_reg[0][2]_i_6_n_0\,
      I1 => \corse_inc[0][2]_i_7_n_0\,
      I2 => wrlvl_byte_redo,
      I3 => \^wr_level_done_r5\,
      O => \dqs_count_r[3]_i_11_n_0\
    );
\dqs_count_r[3]_i_12\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \wl_state_r__0\(0),
      I1 => \wl_state_r__0\(2),
      O => \dqs_count_r[3]_i_12_n_0\
    );
\dqs_count_r[3]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFF55554000"
    )
        port map (
      I0 => \dqs_count_r[3]_i_3_n_0\,
      I1 => \^dqs_count_r_reg[3]_0\(0),
      I2 => \dqs_count_r[3]_i_4_n_0\,
      I3 => \dqs_count_r[3]_i_5_n_0\,
      I4 => \dqs_count_r[3]_i_6_n_0\,
      I5 => \dqs_count_r[3]_i_7_n_0\,
      O => \dqs_count_r[3]_i_2_n_0\
    );
\dqs_count_r[3]_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000DD0D"
    )
        port map (
      I0 => \^dqs_count_r_reg[3]_0\(0),
      I1 => \dqs_count_r[3]_i_8_n_0\,
      I2 => \dqs_count_r_reg[3]_1\(3),
      I3 => \dqs_count_r[3]_i_9_n_0\,
      I4 => \^fsm_sequential_wl_state_r_reg[4]_0\(1),
      O => \dqs_count_r[3]_i_3_n_0\
    );
\dqs_count_r[3]_i_4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \^fsm_sequential_wl_state_r_reg[4]_0\(0),
      I1 => \wl_state_r__0\(2),
      O => \dqs_count_r[3]_i_4_n_0\
    );
\dqs_count_r[3]_i_5\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7FFF"
    )
        port map (
      I0 => \^dqs_count_r_reg[2]_rep__0_0\,
      I1 => dqs_count_r(1),
      I2 => dqs_count_r(0),
      I3 => \fine_inc[0][5]_i_3_n_0\,
      O => \dqs_count_r[3]_i_5_n_0\
    );
\dqs_count_r[3]_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"20202000FFFFFFFF"
    )
        port map (
      I0 => \^dqs_count_r_reg[3]_0\(0),
      I1 => \^fsm_sequential_wl_state_r_reg[4]_0\(0),
      I2 => \wl_state_r__0\(2),
      I3 => wrlvl_byte_redo,
      I4 => \dqs_count_r[3]_i_10_n_0\,
      I5 => \^fsm_sequential_wl_state_r_reg[4]_0\(1),
      O => \dqs_count_r[3]_i_6_n_0\
    );
\dqs_count_r[3]_i_7\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F000F00070000000"
    )
        port map (
      I0 => \dqs_count_r[3]_i_11_n_0\,
      I1 => \fine_inc[0][5]_i_3_n_0\,
      I2 => \^dqs_count_r_reg[3]_0\(0),
      I3 => \dqs_count_r[3]_i_12_n_0\,
      I4 => \^fsm_sequential_wl_state_r_reg[4]_0\(0),
      I5 => \dqs_count_r[3]_i_10_n_0\,
      O => \dqs_count_r[3]_i_7_n_0\
    );
\dqs_count_r[3]_i_8\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"5555FFFF0CFFFFFF"
    )
        port map (
      I0 => \dqs_count_r[2]_i_6_n_0\,
      I1 => wrlvl_byte_redo,
      I2 => \^wrlvl_byte_redo_r\,
      I3 => \wl_state_r__0\(2),
      I4 => \wl_state_r__0\(1),
      I5 => \wl_state_r__0\(0),
      O => \dqs_count_r[3]_i_8_n_0\
    );
\dqs_count_r[3]_i_9\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFF7FF"
    )
        port map (
      I0 => \wl_state_r__0\(2),
      I1 => \wl_state_r__0\(1),
      I2 => \^wrlvl_byte_redo_r\,
      I3 => wrlvl_byte_redo,
      I4 => \wl_state_r__0\(0),
      O => \dqs_count_r[3]_i_9_n_0\
    );
\dqs_count_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => \dqs_count_r[3]_i_1_n_0\,
      D => \dqs_count_r[0]_i_1_n_0\,
      Q => dqs_count_r(0),
      R => \fine_inc_reg[6][3]_0\(1)
    );
\dqs_count_r_reg[0]_rep\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => \dqs_count_r[3]_i_1_n_0\,
      D => \dqs_count_r[0]_i_1_n_0\,
      Q => \^dqs_count_r_reg[0]_rep_0\,
      R => \dqs_count_r_reg[2]_rep__0_2\
    );
\dqs_count_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => \dqs_count_r[3]_i_1_n_0\,
      D => \dqs_count_r[1]_i_1_n_0\,
      Q => dqs_count_r(1),
      R => \fine_inc_reg[6][3]_0\(1)
    );
\dqs_count_r_reg[1]_rep\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => \dqs_count_r[3]_i_1_n_0\,
      D => \dqs_count_r[1]_rep_i_1_n_0\,
      Q => \^dqs_count_r_reg[1]_rep_0\,
      R => \dqs_count_r_reg[2]_rep__0_2\
    );
\dqs_count_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => \dqs_count_r[3]_i_1_n_0\,
      D => \dqs_count_r[2]_i_1_n_0\,
      Q => dqs_count_r(2),
      R => \fine_inc_reg[6][3]_0\(1)
    );
\dqs_count_r_reg[2]_rep\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => \dqs_count_r[3]_i_1_n_0\,
      D => \dqs_count_r[2]_rep_i_1_n_0\,
      Q => \dqs_count_r_reg[2]_rep_n_0\,
      R => \dqs_count_r_reg[2]_rep__0_2\
    );
\dqs_count_r_reg[2]_rep__0\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => \dqs_count_r[3]_i_1_n_0\,
      D => \dqs_count_r[2]_rep__0_i_1_n_0\,
      Q => \^dqs_count_r_reg[2]_rep__0_0\,
      R => \dqs_count_r_reg[2]_rep__0_2\
    );
\dqs_count_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => \dqs_count_r[3]_i_1_n_0\,
      D => \dqs_count_r[3]_i_2_n_0\,
      Q => \^dqs_count_r_reg[3]_0\(0),
      R => \fine_inc_reg[6][3]_0\(1)
    );
dqs_po_dec_done_reg: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => '1',
      D => po_dec_done,
      Q => \^dqs_po_dec_done\,
      R => '0'
    );
dqs_po_en_stg2_f_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AABAAABAAAEAAAAB"
    )
        port map (
      I0 => \^po_cnt_dec_reg_0\,
      I1 => \^fsm_sequential_wl_state_r_reg[4]_0\(1),
      I2 => \^fsm_sequential_wl_state_r_reg[4]_0\(0),
      I3 => \wl_state_r__0\(1),
      I4 => \wl_state_r__0\(0),
      I5 => \wl_state_r__0\(2),
      O => dqs_po_en_stg2_f_i_1_n_0
    );
dqs_po_en_stg2_f_reg: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => '1',
      D => dqs_po_en_stg2_f_i_1_n_0,
      Q => dqs_po_en_stg2_f,
      R => \fine_dec_cnt_reg[5]_0\(0)
    );
dqs_po_stg2_f_incdec_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000200000"
    )
        port map (
      I0 => dqs_po_stg2_f_incdec_i_2_n_0,
      I1 => \wl_state_r__0\(1),
      I2 => \wl_state_r__0\(2),
      I3 => \^fsm_sequential_wl_state_r_reg[4]_0\(1),
      I4 => \^fsm_sequential_wl_state_r_reg[4]_0\(0),
      I5 => \single_rank.done_dqs_dec_reg_0\,
      O => dqs_po_stg2_f_incdec_i_1_n_0
    );
dqs_po_stg2_f_incdec_i_2: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000FBFFFFFE"
    )
        port map (
      I0 => \wl_state_r__0\(2),
      I1 => \wl_state_r__0\(0),
      I2 => \wl_state_r__0\(1),
      I3 => \^fsm_sequential_wl_state_r_reg[4]_0\(0),
      I4 => \^fsm_sequential_wl_state_r_reg[4]_0\(1),
      I5 => \^po_cnt_dec_reg_0\,
      O => dqs_po_stg2_f_incdec_i_2_n_0
    );
dqs_po_stg2_f_incdec_reg: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => '1',
      D => dqs_po_stg2_f_incdec_i_1_n_0,
      Q => dqs_po_stg2_f_incdec,
      R => '0'
    );
dqs_wl_po_stg2_c_incdec_i_1: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000080"
    )
        port map (
      I0 => \wl_state_r__0\(0),
      I1 => \^fsm_sequential_wl_state_r_reg[4]_0\(0),
      I2 => \wl_state_r__0\(1),
      I3 => \^fsm_sequential_wl_state_r_reg[4]_0\(1),
      I4 => \wl_state_r__0\(2),
      O => dqs_wl_po_stg2_c_incdec_i_1_n_0
    );
dqs_wl_po_stg2_c_incdec_reg: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => '1',
      D => dqs_wl_po_stg2_c_incdec_i_1_n_0,
      Q => po_stg2_cincdec(2),
      R => \corse_inc_reg[6][2]_0\(0)
    );
\final_coarse_tap_reg[0][0]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => '1',
      D => \wl_corse_cnt_reg[0][0]_29\(0),
      Q => \final_coarse_tap_reg_n_0_[0][0]\,
      R => '0'
    );
\final_coarse_tap_reg[0][1]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => '1',
      D => \wl_corse_cnt_reg[0][0]_29\(1),
      Q => \final_coarse_tap_reg_n_0_[0][1]\,
      R => '0'
    );
\final_coarse_tap_reg[0][2]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => '1',
      D => \wl_corse_cnt_reg[0][0]_29\(2),
      Q => \final_coarse_tap_reg_n_0_[0][2]\,
      R => '0'
    );
\final_coarse_tap_reg[1][0]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => '1',
      D => \wl_corse_cnt_reg[0][1]_30\(0),
      Q => \final_coarse_tap_reg_n_0_[1][0]\,
      R => '0'
    );
\final_coarse_tap_reg[1][1]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => '1',
      D => \wl_corse_cnt_reg[0][1]_30\(1),
      Q => \final_coarse_tap_reg_n_0_[1][1]\,
      R => '0'
    );
\final_coarse_tap_reg[1][2]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => '1',
      D => \wl_corse_cnt_reg[0][1]_30\(2),
      Q => \final_coarse_tap_reg_n_0_[1][2]\,
      R => '0'
    );
\final_coarse_tap_reg[2][0]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => '1',
      D => \wl_corse_cnt_reg[0][2]_31\(0),
      Q => \final_coarse_tap_reg_n_0_[2][0]\,
      R => '0'
    );
\final_coarse_tap_reg[2][1]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => '1',
      D => \wl_corse_cnt_reg[0][2]_31\(1),
      Q => \final_coarse_tap_reg_n_0_[2][1]\,
      R => '0'
    );
\final_coarse_tap_reg[2][2]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => '1',
      D => \wl_corse_cnt_reg[0][2]_31\(2),
      Q => \final_coarse_tap_reg_n_0_[2][2]\,
      R => '0'
    );
\final_coarse_tap_reg[3][0]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => '1',
      D => \wl_corse_cnt_reg[0][3]_32\(0),
      Q => \final_coarse_tap_reg_n_0_[3][0]\,
      R => '0'
    );
\final_coarse_tap_reg[3][1]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => '1',
      D => \wl_corse_cnt_reg[0][3]_32\(1),
      Q => \final_coarse_tap_reg_n_0_[3][1]\,
      R => '0'
    );
\final_coarse_tap_reg[3][2]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => '1',
      D => \wl_corse_cnt_reg[0][3]_32\(2),
      Q => \final_coarse_tap_reg_n_0_[3][2]\,
      R => '0'
    );
\final_coarse_tap_reg[4][0]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => '1',
      D => \wl_corse_cnt_reg[0][4]_33\(0),
      Q => \final_coarse_tap_reg_n_0_[4][0]\,
      R => '0'
    );
\final_coarse_tap_reg[4][1]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => '1',
      D => \wl_corse_cnt_reg[0][4]_33\(1),
      Q => \final_coarse_tap_reg_n_0_[4][1]\,
      R => '0'
    );
\final_coarse_tap_reg[4][2]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => '1',
      D => \wl_corse_cnt_reg[0][4]_33\(2),
      Q => \final_coarse_tap_reg_n_0_[4][2]\,
      R => '0'
    );
\final_coarse_tap_reg[5][0]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => '1',
      D => \wl_corse_cnt_reg[0][5]_34\(0),
      Q => \final_coarse_tap_reg_n_0_[5][0]\,
      R => '0'
    );
\final_coarse_tap_reg[5][1]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => '1',
      D => \wl_corse_cnt_reg[0][5]_34\(1),
      Q => \final_coarse_tap_reg_n_0_[5][1]\,
      R => '0'
    );
\final_coarse_tap_reg[5][2]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => '1',
      D => \wl_corse_cnt_reg[0][5]_34\(2),
      Q => \final_coarse_tap_reg_n_0_[5][2]\,
      R => '0'
    );
\final_coarse_tap_reg[6][0]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => '1',
      D => \wl_corse_cnt_reg[0][6]_35\(0),
      Q => \final_coarse_tap_reg_n_0_[6][0]\,
      R => '0'
    );
\final_coarse_tap_reg[6][1]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => '1',
      D => \wl_corse_cnt_reg[0][6]_35\(1),
      Q => \final_coarse_tap_reg_n_0_[6][1]\,
      R => '0'
    );
\final_coarse_tap_reg[6][2]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => '1',
      D => \wl_corse_cnt_reg[0][6]_35\(2),
      Q => \final_coarse_tap_reg_n_0_[6][2]\,
      R => '0'
    );
\final_coarse_tap_reg[7][0]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => '1',
      D => \wl_corse_cnt_reg[0][7]_36\(0),
      Q => \final_coarse_tap_reg_n_0_[7][0]\,
      R => '0'
    );
\final_coarse_tap_reg[7][1]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => '1',
      D => \wl_corse_cnt_reg[0][7]_36\(1),
      Q => \final_coarse_tap_reg_n_0_[7][1]\,
      R => '0'
    );
\final_coarse_tap_reg[7][2]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => '1',
      D => \wl_corse_cnt_reg[0][7]_36\(2),
      Q => \final_coarse_tap_reg_n_0_[7][2]\,
      R => '0'
    );
\fine_dec_cnt[0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000CCCC55C5"
    )
        port map (
      I0 => \fine_dec_cnt_reg_n_0_[0]\,
      I1 => \wl_tap_count_r_reg_n_0_[0]\,
      I2 => \^fsm_sequential_wl_state_r_reg[4]_0\(0),
      I3 => \^fsm_sequential_wl_state_r_reg[4]_0\(1),
      I4 => \wl_state_r__0\(1),
      I5 => \wl_state_r__0\(2),
      O => fine_dec_cnt(0)
    );
\fine_dec_cnt[1]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000E22E"
    )
        port map (
      I0 => \wl_tap_count_r_reg_n_0_[1]\,
      I1 => \fine_dec_cnt[5]_i_8_n_0\,
      I2 => \fine_dec_cnt_reg_n_0_[1]\,
      I3 => \fine_dec_cnt_reg_n_0_[0]\,
      I4 => \wl_state_r__0\(2),
      O => fine_dec_cnt(1)
    );
\fine_dec_cnt[2]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000A9A9FF00"
    )
        port map (
      I0 => \fine_dec_cnt_reg_n_0_[2]\,
      I1 => \fine_dec_cnt_reg_n_0_[1]\,
      I2 => \fine_dec_cnt_reg_n_0_[0]\,
      I3 => \wl_tap_count_r_reg_n_0_[2]\,
      I4 => \fine_dec_cnt[5]_i_8_n_0\,
      I5 => \wl_state_r__0\(2),
      O => fine_dec_cnt(2)
    );
\fine_dec_cnt[3]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"000099F0"
    )
        port map (
      I0 => \fine_dec_cnt_reg_n_0_[3]\,
      I1 => \fine_dec_cnt[3]_i_2_n_0\,
      I2 => \wl_tap_count_r_reg_n_0_[3]\,
      I3 => \fine_dec_cnt[5]_i_8_n_0\,
      I4 => \wl_state_r__0\(2),
      O => fine_dec_cnt(3)
    );
\fine_dec_cnt[3]_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"FE"
    )
        port map (
      I0 => \fine_dec_cnt_reg_n_0_[2]\,
      I1 => \fine_dec_cnt_reg_n_0_[1]\,
      I2 => \fine_dec_cnt_reg_n_0_[0]\,
      O => \fine_dec_cnt[3]_i_2_n_0\
    );
\fine_dec_cnt[4]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"000099F0"
    )
        port map (
      I0 => \fine_dec_cnt[4]_i_2_n_0\,
      I1 => \fine_dec_cnt_reg_n_0_[4]\,
      I2 => \wl_tap_count_r_reg_n_0_[4]\,
      I3 => \fine_dec_cnt[5]_i_8_n_0\,
      I4 => \wl_state_r__0\(2),
      O => fine_dec_cnt(4)
    );
\fine_dec_cnt[4]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFFE"
    )
        port map (
      I0 => \fine_dec_cnt_reg_n_0_[3]\,
      I1 => \fine_dec_cnt_reg_n_0_[0]\,
      I2 => \fine_dec_cnt_reg_n_0_[1]\,
      I3 => \fine_dec_cnt_reg_n_0_[2]\,
      O => \fine_dec_cnt[4]_i_2_n_0\
    );
\fine_dec_cnt[5]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"BBBBBAAAAAAAAAAA"
    )
        port map (
      I0 => \fine_dec_cnt[5]_i_3_n_0\,
      I1 => \fine_dec_cnt[5]_i_4_n_0\,
      I2 => \fine_dec_cnt[5]_i_5_n_0\,
      I3 => wl_sm_start,
      I4 => \^fsm_sequential_wl_state_r_reg[4]_0\(1),
      I5 => \fine_dec_cnt[5]_i_6_n_0\,
      O => \fine_dec_cnt[5]_i_1_n_0\
    );
\fine_dec_cnt[5]_i_10\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"BFFF"
    )
        port map (
      I0 => \rd_data_edge_detect_r_reg[7]_i_5_n_0\,
      I1 => \wl_tap_count_r_reg_n_0_[5]\,
      I2 => \wl_tap_count_r_reg_n_0_[4]\,
      I3 => \wl_tap_count_r_reg_n_0_[3]\,
      O => \fine_dec_cnt[5]_i_10_n_0\
    );
\fine_dec_cnt[5]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"000066F0"
    )
        port map (
      I0 => \fine_dec_cnt_reg_n_0_[5]\,
      I1 => \fine_dec_cnt[5]_i_7_n_0\,
      I2 => \wl_tap_count_r_reg_n_0_[5]\,
      I3 => \fine_dec_cnt[5]_i_8_n_0\,
      I4 => \wl_state_r__0\(2),
      O => fine_dec_cnt(5)
    );
\fine_dec_cnt[5]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0002808200020002"
    )
        port map (
      I0 => \fine_dec_cnt[5]_i_9_n_0\,
      I1 => \^fsm_sequential_wl_state_r_reg[4]_0\(1),
      I2 => \wl_state_r__0\(1),
      I3 => \FSM_sequential_wl_state_r[4]_i_17_n_0\,
      I4 => \rd_data_edge_detect_r[7]_i_4_n_0\,
      I5 => wrlvl_byte_redo,
      O => \fine_dec_cnt[5]_i_3_n_0\
    );
\fine_dec_cnt[5]_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"DF"
    )
        port map (
      I0 => \wl_state_r__0\(0),
      I1 => \wl_state_r__0\(2),
      I2 => \^fsm_sequential_wl_state_r_reg[4]_0\(0),
      O => \fine_dec_cnt[5]_i_4_n_0\
    );
\fine_dec_cnt[5]_i_5\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8000"
    )
        port map (
      I0 => \rd_data_edge_detect_r_reg[7]_i_9_n_0\,
      I1 => \stable_cnt_reg_n_0_[3]\,
      I2 => \stable_cnt_reg_n_0_[1]\,
      I3 => \stable_cnt_reg_n_0_[2]\,
      O => \fine_dec_cnt[5]_i_5_n_0\
    );
\fine_dec_cnt[5]_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"040004FF00FF00FF"
    )
        port map (
      I0 => \FSM_sequential_wl_state_r[3]_i_7_n_0\,
      I1 => wl_edge_detect_valid_r_reg_n_0,
      I2 => \fine_dec_cnt[5]_i_10_n_0\,
      I3 => \wl_state_r__0\(1),
      I4 => \FSM_sequential_wl_state_r[4]_i_17_n_0\,
      I5 => \^fsm_sequential_wl_state_r_reg[4]_0\(1),
      O => \fine_dec_cnt[5]_i_6_n_0\
    );
\fine_dec_cnt[5]_i_7\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000001"
    )
        port map (
      I0 => \fine_dec_cnt_reg_n_0_[4]\,
      I1 => \fine_dec_cnt_reg_n_0_[2]\,
      I2 => \fine_dec_cnt_reg_n_0_[1]\,
      I3 => \fine_dec_cnt_reg_n_0_[0]\,
      I4 => \fine_dec_cnt_reg_n_0_[3]\,
      O => \fine_dec_cnt[5]_i_7_n_0\
    );
\fine_dec_cnt[5]_i_8\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"45"
    )
        port map (
      I0 => \wl_state_r__0\(1),
      I1 => \^fsm_sequential_wl_state_r_reg[4]_0\(1),
      I2 => \^fsm_sequential_wl_state_r_reg[4]_0\(0),
      O => \fine_dec_cnt[5]_i_8_n_0\
    );
\fine_dec_cnt[5]_i_9\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"01"
    )
        port map (
      I0 => \wl_state_r__0\(2),
      I1 => \wl_state_r__0\(0),
      I2 => \^fsm_sequential_wl_state_r_reg[4]_0\(0),
      O => \fine_dec_cnt[5]_i_9_n_0\
    );
\fine_dec_cnt_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => \fine_dec_cnt[5]_i_1_n_0\,
      D => fine_dec_cnt(0),
      Q => \fine_dec_cnt_reg_n_0_[0]\,
      R => \fine_dec_cnt_reg[5]_0\(0)
    );
\fine_dec_cnt_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => \fine_dec_cnt[5]_i_1_n_0\,
      D => fine_dec_cnt(1),
      Q => \fine_dec_cnt_reg_n_0_[1]\,
      R => \fine_dec_cnt_reg[5]_0\(0)
    );
\fine_dec_cnt_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => \fine_dec_cnt[5]_i_1_n_0\,
      D => fine_dec_cnt(2),
      Q => \fine_dec_cnt_reg_n_0_[2]\,
      R => \fine_dec_cnt_reg[5]_0\(0)
    );
\fine_dec_cnt_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => \fine_dec_cnt[5]_i_1_n_0\,
      D => fine_dec_cnt(3),
      Q => \fine_dec_cnt_reg_n_0_[3]\,
      R => \fine_dec_cnt_reg[5]_0\(0)
    );
\fine_dec_cnt_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => \fine_dec_cnt[5]_i_1_n_0\,
      D => fine_dec_cnt(4),
      Q => \fine_dec_cnt_reg_n_0_[4]\,
      R => \fine_dec_cnt_reg[5]_0\(0)
    );
\fine_dec_cnt_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => \fine_dec_cnt[5]_i_1_n_0\,
      D => fine_dec_cnt(5),
      Q => \fine_dec_cnt_reg_n_0_[5]\,
      R => \fine_dec_cnt_reg[5]_0\(0)
    );
\fine_inc[0][0]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0B000100"
    )
        port map (
      I0 => \wl_state_r__0\(1),
      I1 => \fine_inc_reg[0][1]_i_2_n_0\,
      I2 => \^fsm_sequential_wl_state_r_reg[4]_0\(1),
      I3 => \wl_state_r__0\(0),
      I4 => \gen_final_tap[0].final_val_reg_n_0_[0][0]\,
      O => fine_inc(0)
    );
\fine_inc[0][1]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00EB000000410000"
    )
        port map (
      I0 => \wl_state_r__0\(1),
      I1 => \fine_inc_reg[0][1]_i_2_n_0\,
      I2 => \fine_inc_reg[0][1]_i_3_n_0\,
      I3 => \^fsm_sequential_wl_state_r_reg[4]_0\(1),
      I4 => \wl_state_r__0\(0),
      I5 => \gen_final_tap[0].final_val_reg_n_0_[0][1]\,
      O => fine_inc(1)
    );
\fine_inc[0][1]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \fine_inc_reg[3]_8\(0),
      I1 => \fine_inc_reg[2]_7\(0),
      I2 => \^dqs_count_r_reg[1]_rep_0\,
      I3 => \fine_inc_reg[1]_6\(0),
      I4 => \^dqs_count_r_reg[0]_rep_0\,
      I5 => \fine_inc_reg[0]_5\(0),
      O => \fine_inc[0][1]_i_4_n_0\
    );
\fine_inc[0][1]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \fine_inc_reg[7]_12\(0),
      I1 => \fine_inc_reg[6]_11\(0),
      I2 => \^dqs_count_r_reg[1]_rep_0\,
      I3 => \fine_inc_reg[5]_10\(0),
      I4 => \^dqs_count_r_reg[0]_rep_0\,
      I5 => \fine_inc_reg[4]_9\(0),
      O => \fine_inc[0][1]_i_5_n_0\
    );
\fine_inc[0][1]_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \fine_inc_reg[3]_8\(1),
      I1 => \fine_inc_reg[2]_7\(1),
      I2 => \^dqs_count_r_reg[1]_rep_0\,
      I3 => \fine_inc_reg[1]_6\(1),
      I4 => \^dqs_count_r_reg[0]_rep_0\,
      I5 => \fine_inc_reg[0]_5\(1),
      O => \fine_inc[0][1]_i_6_n_0\
    );
\fine_inc[0][1]_i_7\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \fine_inc_reg[7]_12\(1),
      I1 => \fine_inc_reg[6]_11\(1),
      I2 => \^dqs_count_r_reg[1]_rep_0\,
      I3 => \fine_inc_reg[5]_10\(1),
      I4 => \^dqs_count_r_reg[0]_rep_0\,
      I5 => \fine_inc_reg[4]_9\(1),
      O => \fine_inc[0][1]_i_7_n_0\
    );
\fine_inc[0][2]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00EB000000410000"
    )
        port map (
      I0 => \wl_state_r__0\(1),
      I1 => \fine_inc_reg[0][2]_i_2_n_0\,
      I2 => \fine_inc[0][2]_i_3_n_0\,
      I3 => \^fsm_sequential_wl_state_r_reg[4]_0\(1),
      I4 => \wl_state_r__0\(0),
      I5 => \gen_final_tap[0].final_val_reg_n_0_[0][2]\,
      O => fine_inc(2)
    );
\fine_inc[0][2]_i_3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => \fine_inc_reg[0][1]_i_3_n_0\,
      I1 => \fine_inc_reg[0][1]_i_2_n_0\,
      O => \fine_inc[0][2]_i_3_n_0\
    );
\fine_inc[0][2]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \fine_inc_reg[3]_8\(2),
      I1 => \fine_inc_reg[2]_7\(2),
      I2 => \^dqs_count_r_reg[1]_rep_0\,
      I3 => \fine_inc_reg[1]_6\(2),
      I4 => \^dqs_count_r_reg[0]_rep_0\,
      I5 => \fine_inc_reg[0]_5\(2),
      O => \fine_inc[0][2]_i_4_n_0\
    );
\fine_inc[0][2]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \fine_inc_reg[7]_12\(2),
      I1 => \fine_inc_reg[6]_11\(2),
      I2 => \^dqs_count_r_reg[1]_rep_0\,
      I3 => \fine_inc_reg[5]_10\(2),
      I4 => \^dqs_count_r_reg[0]_rep_0\,
      I5 => \fine_inc_reg[4]_9\(2),
      O => \fine_inc[0][2]_i_5_n_0\
    );
\fine_inc[0][3]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00EB000000410000"
    )
        port map (
      I0 => \wl_state_r__0\(1),
      I1 => \fine_inc_reg[0][3]_i_2_n_0\,
      I2 => \fine_inc[0][3]_i_3_n_0\,
      I3 => \^fsm_sequential_wl_state_r_reg[4]_0\(1),
      I4 => \wl_state_r__0\(0),
      I5 => \gen_final_tap[0].final_val_reg_n_0_[0][3]\,
      O => fine_inc(3)
    );
\fine_inc[0][3]_i_3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => \fine_inc[0][2]_i_3_n_0\,
      I1 => \fine_inc_reg[0][2]_i_2_n_0\,
      O => \fine_inc[0][3]_i_3_n_0\
    );
\fine_inc[0][3]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \fine_inc_reg[3]_8\(3),
      I1 => \fine_inc_reg[2]_7\(3),
      I2 => \^dqs_count_r_reg[1]_rep_0\,
      I3 => \fine_inc_reg[1]_6\(3),
      I4 => \^dqs_count_r_reg[0]_rep_0\,
      I5 => \fine_inc_reg[0]_5\(3),
      O => \fine_inc[0][3]_i_4_n_0\
    );
\fine_inc[0][3]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \fine_inc_reg[7]_12\(3),
      I1 => \fine_inc_reg[6]_11\(3),
      I2 => \^dqs_count_r_reg[1]_rep_0\,
      I3 => \fine_inc_reg[5]_10\(3),
      I4 => \^dqs_count_r_reg[0]_rep_0\,
      I5 => \fine_inc_reg[4]_9\(3),
      O => \fine_inc[0][3]_i_5_n_0\
    );
\fine_inc[0][4]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"40004444"
    )
        port map (
      I0 => \^fsm_sequential_wl_state_r_reg[4]_0\(1),
      I1 => \wl_state_r__0\(0),
      I2 => \wl_state_r__0\(1),
      I3 => \gen_final_tap[0].final_val_reg_n_0_[0][4]\,
      I4 => \fine_inc[0][4]_i_2_n_0\,
      O => fine_inc(4)
    );
\fine_inc[0][4]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"BBBE"
    )
        port map (
      I0 => \wl_state_r__0\(1),
      I1 => \fine_inc_reg[0][5]_i_9_n_0\,
      I2 => \fine_inc[0][3]_i_3_n_0\,
      I3 => \fine_inc_reg[0][3]_i_2_n_0\,
      O => \fine_inc[0][4]_i_2_n_0\
    );
\fine_inc[0][5]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"202C202000000000"
    )
        port map (
      I0 => wr_level_done_r4,
      I1 => \^wr_level_done_r5\,
      I2 => \wl_state_r__0\(1),
      I3 => \fine_inc[0][5]_i_3_n_0\,
      I4 => \fine_inc[0][5]_i_4_n_0\,
      I5 => \fine_inc[0][5]_i_5_n_0\,
      O => \fine_inc[0][5]_i_1_n_0\
    );
\fine_inc[0][5]_i_10\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \fine_inc_reg[3]_8\(5),
      I1 => \fine_inc_reg[2]_7\(5),
      I2 => \^dqs_count_r_reg[1]_rep_0\,
      I3 => \fine_inc_reg[1]_6\(5),
      I4 => \^dqs_count_r_reg[0]_rep_0\,
      I5 => \fine_inc_reg[0]_5\(5),
      O => \fine_inc[0][5]_i_10_n_0\
    );
\fine_inc[0][5]_i_11\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \fine_inc_reg[7]_12\(5),
      I1 => \fine_inc_reg[6]_11\(5),
      I2 => \^dqs_count_r_reg[1]_rep_0\,
      I3 => \fine_inc_reg[5]_10\(5),
      I4 => \^dqs_count_r_reg[0]_rep_0\,
      I5 => \fine_inc_reg[4]_9\(5),
      O => \fine_inc[0][5]_i_11_n_0\
    );
\fine_inc[0][5]_i_12\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \fine_inc_reg[3]_8\(4),
      I1 => \fine_inc_reg[2]_7\(4),
      I2 => \^dqs_count_r_reg[1]_rep_0\,
      I3 => \fine_inc_reg[1]_6\(4),
      I4 => \^dqs_count_r_reg[0]_rep_0\,
      I5 => \fine_inc_reg[0]_5\(4),
      O => \fine_inc[0][5]_i_12_n_0\
    );
\fine_inc[0][5]_i_13\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \fine_inc_reg[7]_12\(4),
      I1 => \fine_inc_reg[6]_11\(4),
      I2 => \^dqs_count_r_reg[1]_rep_0\,
      I3 => \fine_inc_reg[5]_10\(4),
      I4 => \^dqs_count_r_reg[0]_rep_0\,
      I5 => \fine_inc_reg[4]_9\(4),
      O => \fine_inc[0][5]_i_13_n_0\
    );
\fine_inc[0][5]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"A280A280A28080A2"
    )
        port map (
      I0 => \fine_inc[0][5]_i_6_n_0\,
      I1 => \wl_state_r__0\(1),
      I2 => \gen_final_tap[0].final_val_reg_n_0_[0][5]\,
      I3 => \fine_inc_reg[0][5]_i_7_n_0\,
      I4 => \fine_inc[0][5]_i_8_n_0\,
      I5 => \fine_inc_reg[0][5]_i_9_n_0\,
      O => fine_inc(5)
    );
\fine_inc[0][5]_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000001"
    )
        port map (
      I0 => \fine_inc[0][2]_i_3_n_0\,
      I1 => \fine_inc_reg[0][2]_i_2_n_0\,
      I2 => \fine_inc_reg[0][3]_i_2_n_0\,
      I3 => \fine_inc_reg[0][5]_i_9_n_0\,
      I4 => \fine_inc_reg[0][5]_i_7_n_0\,
      O => \fine_inc[0][5]_i_3_n_0\
    );
\fine_inc[0][5]_i_4\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0001"
    )
        port map (
      I0 => dqs_count_r(0),
      I1 => dqs_count_r(1),
      I2 => \^dqs_count_r_reg[2]_rep__0_0\,
      I3 => \^dqs_count_r_reg[3]_0\(0),
      O => \fine_inc[0][5]_i_4_n_0\
    );
\fine_inc[0][5]_i_5\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4000"
    )
        port map (
      I0 => \^fsm_sequential_wl_state_r_reg[4]_0\(1),
      I1 => \wl_state_r__0\(0),
      I2 => \wl_state_r__0\(2),
      I3 => \^fsm_sequential_wl_state_r_reg[4]_0\(0),
      O => \fine_inc[0][5]_i_5_n_0\
    );
\fine_inc[0][5]_i_6\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \wl_state_r__0\(0),
      I1 => \^fsm_sequential_wl_state_r_reg[4]_0\(1),
      O => \fine_inc[0][5]_i_6_n_0\
    );
\fine_inc[0][5]_i_8\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => \fine_inc[0][3]_i_3_n_0\,
      I1 => \fine_inc_reg[0][3]_i_2_n_0\,
      O => \fine_inc[0][5]_i_8_n_0\
    );
\fine_inc[1][0]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0B000100"
    )
        port map (
      I0 => \wl_state_r__0\(1),
      I1 => \fine_inc_reg[0][1]_i_2_n_0\,
      I2 => \^fsm_sequential_wl_state_r_reg[4]_0\(1),
      I3 => \wl_state_r__0\(0),
      I4 => \gen_final_tap[1].final_val_reg_n_0_[1][0]\,
      O => \fine_inc[1][0]_i_1_n_0\
    );
\fine_inc[1][1]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00EB000000410000"
    )
        port map (
      I0 => \wl_state_r__0\(1),
      I1 => \fine_inc_reg[0][1]_i_2_n_0\,
      I2 => \fine_inc_reg[0][1]_i_3_n_0\,
      I3 => \^fsm_sequential_wl_state_r_reg[4]_0\(1),
      I4 => \wl_state_r__0\(0),
      I5 => \gen_final_tap[1].final_val_reg_n_0_[1][1]\,
      O => \fine_inc[1][1]_i_1_n_0\
    );
\fine_inc[1][2]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00EB000000410000"
    )
        port map (
      I0 => \wl_state_r__0\(1),
      I1 => \fine_inc_reg[0][2]_i_2_n_0\,
      I2 => \fine_inc[0][2]_i_3_n_0\,
      I3 => \^fsm_sequential_wl_state_r_reg[4]_0\(1),
      I4 => \wl_state_r__0\(0),
      I5 => \gen_final_tap[1].final_val_reg_n_0_[1][2]\,
      O => \fine_inc[1][2]_i_1_n_0\
    );
\fine_inc[1][3]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00EB000000410000"
    )
        port map (
      I0 => \wl_state_r__0\(1),
      I1 => \fine_inc_reg[0][3]_i_2_n_0\,
      I2 => \fine_inc[0][3]_i_3_n_0\,
      I3 => \^fsm_sequential_wl_state_r_reg[4]_0\(1),
      I4 => \wl_state_r__0\(0),
      I5 => \gen_final_tap[1].final_val_reg_n_0_[1][3]\,
      O => \fine_inc[1][3]_i_1_n_0\
    );
\fine_inc[1][4]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"40004444"
    )
        port map (
      I0 => \^fsm_sequential_wl_state_r_reg[4]_0\(1),
      I1 => \wl_state_r__0\(0),
      I2 => \wl_state_r__0\(1),
      I3 => \gen_final_tap[1].final_val_reg_n_0_[1][4]\,
      I4 => \fine_inc[0][4]_i_2_n_0\,
      O => \fine_inc[1][4]_i_1_n_0\
    );
\fine_inc[1][5]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0020AA0000200000"
    )
        port map (
      I0 => \fine_inc[0][5]_i_5_n_0\,
      I1 => \fine_inc[0][5]_i_3_n_0\,
      I2 => \fine_inc[1][5]_i_3_n_0\,
      I3 => \wl_state_r__0\(1),
      I4 => \^wr_level_done_r5\,
      I5 => wr_level_done_r4,
      O => \fine_inc[1][5]_i_1_n_0\
    );
\fine_inc[1][5]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"A280A280A28080A2"
    )
        port map (
      I0 => \fine_inc[0][5]_i_6_n_0\,
      I1 => \wl_state_r__0\(1),
      I2 => \gen_final_tap[1].final_val_reg_n_0_[1][5]\,
      I3 => \fine_inc_reg[0][5]_i_7_n_0\,
      I4 => \fine_inc[0][5]_i_8_n_0\,
      I5 => \fine_inc_reg[0][5]_i_9_n_0\,
      O => \fine_inc[1][5]_i_2_n_0\
    );
\fine_inc[1][5]_i_3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0004"
    )
        port map (
      I0 => dqs_count_r(1),
      I1 => dqs_count_r(0),
      I2 => \^dqs_count_r_reg[2]_rep__0_0\,
      I3 => \^dqs_count_r_reg[3]_0\(0),
      O => \fine_inc[1][5]_i_3_n_0\
    );
\fine_inc[2][0]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0B000100"
    )
        port map (
      I0 => \wl_state_r__0\(1),
      I1 => \fine_inc_reg[0][1]_i_2_n_0\,
      I2 => \^fsm_sequential_wl_state_r_reg[4]_0\(1),
      I3 => \wl_state_r__0\(0),
      I4 => \gen_final_tap[2].final_val_reg_n_0_[2][0]\,
      O => \fine_inc[2][0]_i_1_n_0\
    );
\fine_inc[2][1]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00EB000000410000"
    )
        port map (
      I0 => \wl_state_r__0\(1),
      I1 => \fine_inc_reg[0][1]_i_2_n_0\,
      I2 => \fine_inc_reg[0][1]_i_3_n_0\,
      I3 => \^fsm_sequential_wl_state_r_reg[4]_0\(1),
      I4 => \wl_state_r__0\(0),
      I5 => \gen_final_tap[2].final_val_reg_n_0_[2][1]\,
      O => \fine_inc[2][1]_i_1_n_0\
    );
\fine_inc[2][2]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00EB000000410000"
    )
        port map (
      I0 => \wl_state_r__0\(1),
      I1 => \fine_inc_reg[0][2]_i_2_n_0\,
      I2 => \fine_inc[0][2]_i_3_n_0\,
      I3 => \^fsm_sequential_wl_state_r_reg[4]_0\(1),
      I4 => \wl_state_r__0\(0),
      I5 => \gen_final_tap[2].final_val_reg_n_0_[2][2]\,
      O => \fine_inc[2][2]_i_1_n_0\
    );
\fine_inc[2][3]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00EB000000410000"
    )
        port map (
      I0 => \wl_state_r__0\(1),
      I1 => \fine_inc_reg[0][3]_i_2_n_0\,
      I2 => \fine_inc[0][3]_i_3_n_0\,
      I3 => \^fsm_sequential_wl_state_r_reg[4]_0\(1),
      I4 => \wl_state_r__0\(0),
      I5 => \gen_final_tap[2].final_val_reg_n_0_[2][3]\,
      O => \fine_inc[2][3]_i_1_n_0\
    );
\fine_inc[2][4]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"40004444"
    )
        port map (
      I0 => \^fsm_sequential_wl_state_r_reg[4]_0\(1),
      I1 => \wl_state_r__0\(0),
      I2 => \wl_state_r__0\(1),
      I3 => \gen_final_tap[2].final_val_reg_n_0_[2][4]\,
      I4 => \fine_inc[0][4]_i_2_n_0\,
      O => \fine_inc[2][4]_i_1_n_0\
    );
\fine_inc[2][5]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0020AA0000200000"
    )
        port map (
      I0 => \fine_inc[0][5]_i_5_n_0\,
      I1 => \fine_inc[0][5]_i_3_n_0\,
      I2 => \fine_inc[2][5]_i_3_n_0\,
      I3 => \wl_state_r__0\(1),
      I4 => \^wr_level_done_r5\,
      I5 => wr_level_done_r4,
      O => \fine_inc[2][5]_i_1_n_0\
    );
\fine_inc[2][5]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"A280A280A28080A2"
    )
        port map (
      I0 => \fine_inc[0][5]_i_6_n_0\,
      I1 => \wl_state_r__0\(1),
      I2 => \gen_final_tap[2].final_val_reg_n_0_[2][5]\,
      I3 => \fine_inc_reg[0][5]_i_7_n_0\,
      I4 => \fine_inc[0][5]_i_8_n_0\,
      I5 => \fine_inc_reg[0][5]_i_9_n_0\,
      O => \fine_inc[2][5]_i_2_n_0\
    );
\fine_inc[2][5]_i_3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0004"
    )
        port map (
      I0 => dqs_count_r(0),
      I1 => dqs_count_r(1),
      I2 => \dqs_count_r_reg[2]_rep_n_0\,
      I3 => \^dqs_count_r_reg[3]_0\(0),
      O => \fine_inc[2][5]_i_3_n_0\
    );
\fine_inc[3][0]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0B000100"
    )
        port map (
      I0 => \wl_state_r__0\(1),
      I1 => \fine_inc_reg[0][1]_i_2_n_0\,
      I2 => \^fsm_sequential_wl_state_r_reg[4]_0\(1),
      I3 => \wl_state_r__0\(0),
      I4 => \gen_final_tap[3].final_val_reg_n_0_[3][0]\,
      O => \fine_inc[3][0]_i_1_n_0\
    );
\fine_inc[3][1]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00EB000000410000"
    )
        port map (
      I0 => \wl_state_r__0\(1),
      I1 => \fine_inc_reg[0][1]_i_2_n_0\,
      I2 => \fine_inc_reg[0][1]_i_3_n_0\,
      I3 => \^fsm_sequential_wl_state_r_reg[4]_0\(1),
      I4 => \wl_state_r__0\(0),
      I5 => \gen_final_tap[3].final_val_reg_n_0_[3][1]\,
      O => \fine_inc[3][1]_i_1_n_0\
    );
\fine_inc[3][2]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00EB000000410000"
    )
        port map (
      I0 => \wl_state_r__0\(1),
      I1 => \fine_inc_reg[0][2]_i_2_n_0\,
      I2 => \fine_inc[0][2]_i_3_n_0\,
      I3 => \^fsm_sequential_wl_state_r_reg[4]_0\(1),
      I4 => \wl_state_r__0\(0),
      I5 => \gen_final_tap[3].final_val_reg_n_0_[3][2]\,
      O => \fine_inc[3][2]_i_1_n_0\
    );
\fine_inc[3][3]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00EB000000410000"
    )
        port map (
      I0 => \wl_state_r__0\(1),
      I1 => \fine_inc_reg[0][3]_i_2_n_0\,
      I2 => \fine_inc[0][3]_i_3_n_0\,
      I3 => \^fsm_sequential_wl_state_r_reg[4]_0\(1),
      I4 => \wl_state_r__0\(0),
      I5 => \gen_final_tap[3].final_val_reg_n_0_[3][3]\,
      O => \fine_inc[3][3]_i_1_n_0\
    );
\fine_inc[3][4]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"40004444"
    )
        port map (
      I0 => \^fsm_sequential_wl_state_r_reg[4]_0\(1),
      I1 => \wl_state_r__0\(0),
      I2 => \wl_state_r__0\(1),
      I3 => \gen_final_tap[3].final_val_reg_n_0_[3][4]\,
      I4 => \fine_inc[0][4]_i_2_n_0\,
      O => \fine_inc[3][4]_i_1_n_0\
    );
\fine_inc[3][5]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0020AA0000200000"
    )
        port map (
      I0 => \fine_inc[0][5]_i_5_n_0\,
      I1 => \fine_inc[0][5]_i_3_n_0\,
      I2 => \fine_inc[3][5]_i_3_n_0\,
      I3 => \wl_state_r__0\(1),
      I4 => \^wr_level_done_r5\,
      I5 => wr_level_done_r4,
      O => \fine_inc[3][5]_i_1_n_0\
    );
\fine_inc[3][5]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"A280A280A28080A2"
    )
        port map (
      I0 => \fine_inc[0][5]_i_6_n_0\,
      I1 => \wl_state_r__0\(1),
      I2 => \gen_final_tap[3].final_val_reg_n_0_[3][5]\,
      I3 => \fine_inc_reg[0][5]_i_7_n_0\,
      I4 => \fine_inc[0][5]_i_8_n_0\,
      I5 => \fine_inc_reg[0][5]_i_9_n_0\,
      O => \fine_inc[3][5]_i_2_n_0\
    );
\fine_inc[3][5]_i_3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"1000"
    )
        port map (
      I0 => \dqs_count_r_reg[2]_rep_n_0\,
      I1 => \^dqs_count_r_reg[3]_0\(0),
      I2 => dqs_count_r(0),
      I3 => dqs_count_r(1),
      O => \fine_inc[3][5]_i_3_n_0\
    );
\fine_inc[4][0]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0B000100"
    )
        port map (
      I0 => \wl_state_r__0\(1),
      I1 => \fine_inc_reg[0][1]_i_2_n_0\,
      I2 => \^fsm_sequential_wl_state_r_reg[4]_0\(1),
      I3 => \wl_state_r__0\(0),
      I4 => \gen_final_tap[4].final_val_reg_n_0_[4][0]\,
      O => \fine_inc[4][0]_i_1_n_0\
    );
\fine_inc[4][1]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00EB000000410000"
    )
        port map (
      I0 => \wl_state_r__0\(1),
      I1 => \fine_inc_reg[0][1]_i_2_n_0\,
      I2 => \fine_inc_reg[0][1]_i_3_n_0\,
      I3 => \^fsm_sequential_wl_state_r_reg[4]_0\(1),
      I4 => \wl_state_r__0\(0),
      I5 => \gen_final_tap[4].final_val_reg_n_0_[4][1]\,
      O => \fine_inc[4][1]_i_1_n_0\
    );
\fine_inc[4][2]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00EB000000410000"
    )
        port map (
      I0 => \wl_state_r__0\(1),
      I1 => \fine_inc_reg[0][2]_i_2_n_0\,
      I2 => \fine_inc[0][2]_i_3_n_0\,
      I3 => \^fsm_sequential_wl_state_r_reg[4]_0\(1),
      I4 => \wl_state_r__0\(0),
      I5 => \gen_final_tap[4].final_val_reg_n_0_[4][2]\,
      O => \fine_inc[4][2]_i_1_n_0\
    );
\fine_inc[4][3]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00EB000000410000"
    )
        port map (
      I0 => \wl_state_r__0\(1),
      I1 => \fine_inc_reg[0][3]_i_2_n_0\,
      I2 => \fine_inc[0][3]_i_3_n_0\,
      I3 => \^fsm_sequential_wl_state_r_reg[4]_0\(1),
      I4 => \wl_state_r__0\(0),
      I5 => \gen_final_tap[4].final_val_reg_n_0_[4][3]\,
      O => \fine_inc[4][3]_i_1_n_0\
    );
\fine_inc[4][4]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"40004444"
    )
        port map (
      I0 => \^fsm_sequential_wl_state_r_reg[4]_0\(1),
      I1 => \wl_state_r__0\(0),
      I2 => \wl_state_r__0\(1),
      I3 => \gen_final_tap[4].final_val_reg_n_0_[4][4]\,
      I4 => \fine_inc[0][4]_i_2_n_0\,
      O => \fine_inc[4][4]_i_1_n_0\
    );
\fine_inc[4][5]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0020AA0000200000"
    )
        port map (
      I0 => \fine_inc[0][5]_i_5_n_0\,
      I1 => \fine_inc[0][5]_i_3_n_0\,
      I2 => \fine_inc[4][5]_i_3_n_0\,
      I3 => \wl_state_r__0\(1),
      I4 => \^wr_level_done_r5\,
      I5 => wr_level_done_r4,
      O => \fine_inc[4][5]_i_1_n_0\
    );
\fine_inc[4][5]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"A280A280A28080A2"
    )
        port map (
      I0 => \fine_inc[0][5]_i_6_n_0\,
      I1 => \wl_state_r__0\(1),
      I2 => \gen_final_tap[4].final_val_reg_n_0_[4][5]\,
      I3 => \fine_inc_reg[0][5]_i_7_n_0\,
      I4 => \fine_inc[0][5]_i_8_n_0\,
      I5 => \fine_inc_reg[0][5]_i_9_n_0\,
      O => \fine_inc[4][5]_i_2_n_0\
    );
\fine_inc[4][5]_i_3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0010"
    )
        port map (
      I0 => dqs_count_r(0),
      I1 => dqs_count_r(1),
      I2 => \^dqs_count_r_reg[2]_rep__0_0\,
      I3 => \^dqs_count_r_reg[3]_0\(0),
      O => \fine_inc[4][5]_i_3_n_0\
    );
\fine_inc[5][0]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0B000100"
    )
        port map (
      I0 => \wl_state_r__0\(1),
      I1 => \fine_inc_reg[0][1]_i_2_n_0\,
      I2 => \^fsm_sequential_wl_state_r_reg[4]_0\(1),
      I3 => \wl_state_r__0\(0),
      I4 => \gen_final_tap[5].final_val_reg_n_0_[5][0]\,
      O => \fine_inc[5][0]_i_1_n_0\
    );
\fine_inc[5][1]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00EB000000410000"
    )
        port map (
      I0 => \wl_state_r__0\(1),
      I1 => \fine_inc_reg[0][1]_i_2_n_0\,
      I2 => \fine_inc_reg[0][1]_i_3_n_0\,
      I3 => \^fsm_sequential_wl_state_r_reg[4]_0\(1),
      I4 => \wl_state_r__0\(0),
      I5 => \gen_final_tap[5].final_val_reg_n_0_[5][1]\,
      O => \fine_inc[5][1]_i_1_n_0\
    );
\fine_inc[5][2]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00EB000000410000"
    )
        port map (
      I0 => \wl_state_r__0\(1),
      I1 => \fine_inc_reg[0][2]_i_2_n_0\,
      I2 => \fine_inc[0][2]_i_3_n_0\,
      I3 => \^fsm_sequential_wl_state_r_reg[4]_0\(1),
      I4 => \wl_state_r__0\(0),
      I5 => \gen_final_tap[5].final_val_reg_n_0_[5][2]\,
      O => \fine_inc[5][2]_i_1_n_0\
    );
\fine_inc[5][3]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00EB000000410000"
    )
        port map (
      I0 => \wl_state_r__0\(1),
      I1 => \fine_inc_reg[0][3]_i_2_n_0\,
      I2 => \fine_inc[0][3]_i_3_n_0\,
      I3 => \^fsm_sequential_wl_state_r_reg[4]_0\(1),
      I4 => \wl_state_r__0\(0),
      I5 => \gen_final_tap[5].final_val_reg_n_0_[5][3]\,
      O => \fine_inc[5][3]_i_1_n_0\
    );
\fine_inc[5][4]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"40004444"
    )
        port map (
      I0 => \^fsm_sequential_wl_state_r_reg[4]_0\(1),
      I1 => \wl_state_r__0\(0),
      I2 => \wl_state_r__0\(1),
      I3 => \gen_final_tap[5].final_val_reg_n_0_[5][4]\,
      I4 => \fine_inc[0][4]_i_2_n_0\,
      O => \fine_inc[5][4]_i_1_n_0\
    );
\fine_inc[5][5]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0020AA0000200000"
    )
        port map (
      I0 => \fine_inc[0][5]_i_5_n_0\,
      I1 => \fine_inc[0][5]_i_3_n_0\,
      I2 => \fine_inc[5][5]_i_3_n_0\,
      I3 => \wl_state_r__0\(1),
      I4 => \^wr_level_done_r5\,
      I5 => wr_level_done_r4,
      O => \fine_inc[5][5]_i_1_n_0\
    );
\fine_inc[5][5]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"A280A280A28080A2"
    )
        port map (
      I0 => \fine_inc[0][5]_i_6_n_0\,
      I1 => \wl_state_r__0\(1),
      I2 => \gen_final_tap[5].final_val_reg_n_0_[5][5]\,
      I3 => \fine_inc_reg[0][5]_i_7_n_0\,
      I4 => \fine_inc[0][5]_i_8_n_0\,
      I5 => \fine_inc_reg[0][5]_i_9_n_0\,
      O => \fine_inc[5][5]_i_2_n_0\
    );
\fine_inc[5][5]_i_3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0040"
    )
        port map (
      I0 => dqs_count_r(1),
      I1 => dqs_count_r(0),
      I2 => \^dqs_count_r_reg[2]_rep__0_0\,
      I3 => \^dqs_count_r_reg[3]_0\(0),
      O => \fine_inc[5][5]_i_3_n_0\
    );
\fine_inc[6][0]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0B000100"
    )
        port map (
      I0 => \wl_state_r__0\(1),
      I1 => \fine_inc_reg[0][1]_i_2_n_0\,
      I2 => \^fsm_sequential_wl_state_r_reg[4]_0\(1),
      I3 => \wl_state_r__0\(0),
      I4 => \gen_final_tap[6].final_val_reg_n_0_[6][0]\,
      O => \fine_inc[6][0]_i_1_n_0\
    );
\fine_inc[6][1]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00EB000000410000"
    )
        port map (
      I0 => \wl_state_r__0\(1),
      I1 => \fine_inc_reg[0][1]_i_2_n_0\,
      I2 => \fine_inc_reg[0][1]_i_3_n_0\,
      I3 => \^fsm_sequential_wl_state_r_reg[4]_0\(1),
      I4 => \wl_state_r__0\(0),
      I5 => \gen_final_tap[6].final_val_reg_n_0_[6][1]\,
      O => \fine_inc[6][1]_i_1_n_0\
    );
\fine_inc[6][2]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00EB000000410000"
    )
        port map (
      I0 => \wl_state_r__0\(1),
      I1 => \fine_inc_reg[0][2]_i_2_n_0\,
      I2 => \fine_inc[0][2]_i_3_n_0\,
      I3 => \^fsm_sequential_wl_state_r_reg[4]_0\(1),
      I4 => \wl_state_r__0\(0),
      I5 => \gen_final_tap[6].final_val_reg_n_0_[6][2]\,
      O => \fine_inc[6][2]_i_1_n_0\
    );
\fine_inc[6][3]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00EB000000410000"
    )
        port map (
      I0 => \wl_state_r__0\(1),
      I1 => \fine_inc_reg[0][3]_i_2_n_0\,
      I2 => \fine_inc[0][3]_i_3_n_0\,
      I3 => \^fsm_sequential_wl_state_r_reg[4]_0\(1),
      I4 => \wl_state_r__0\(0),
      I5 => \gen_final_tap[6].final_val_reg_n_0_[6][3]\,
      O => \fine_inc[6][3]_i_1_n_0\
    );
\fine_inc[6][4]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"40004444"
    )
        port map (
      I0 => \^fsm_sequential_wl_state_r_reg[4]_0\(1),
      I1 => \wl_state_r__0\(0),
      I2 => \wl_state_r__0\(1),
      I3 => \gen_final_tap[6].final_val_reg_n_0_[6][4]\,
      I4 => \fine_inc[0][4]_i_2_n_0\,
      O => \fine_inc[6][4]_i_1_n_0\
    );
\fine_inc[6][5]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0020AA0000200000"
    )
        port map (
      I0 => \fine_inc[0][5]_i_5_n_0\,
      I1 => \fine_inc[0][5]_i_3_n_0\,
      I2 => \fine_inc[6][5]_i_3_n_0\,
      I3 => \wl_state_r__0\(1),
      I4 => \^wr_level_done_r5\,
      I5 => wr_level_done_r4,
      O => \fine_inc[6][5]_i_1_n_0\
    );
\fine_inc[6][5]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"A280A280A28080A2"
    )
        port map (
      I0 => \fine_inc[0][5]_i_6_n_0\,
      I1 => \wl_state_r__0\(1),
      I2 => \gen_final_tap[6].final_val_reg_n_0_[6][5]\,
      I3 => \fine_inc_reg[0][5]_i_7_n_0\,
      I4 => \fine_inc[0][5]_i_8_n_0\,
      I5 => \fine_inc_reg[0][5]_i_9_n_0\,
      O => \fine_inc[6][5]_i_2_n_0\
    );
\fine_inc[6][5]_i_3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0040"
    )
        port map (
      I0 => dqs_count_r(0),
      I1 => dqs_count_r(1),
      I2 => \^dqs_count_r_reg[2]_rep__0_0\,
      I3 => \^dqs_count_r_reg[3]_0\(0),
      O => \fine_inc[6][5]_i_3_n_0\
    );
\fine_inc[7][0]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0B000100"
    )
        port map (
      I0 => \wl_state_r__0\(1),
      I1 => \fine_inc_reg[0][1]_i_2_n_0\,
      I2 => \^fsm_sequential_wl_state_r_reg[4]_0\(1),
      I3 => \wl_state_r__0\(0),
      I4 => \gen_final_tap[7].final_val_reg_n_0_[7][0]\,
      O => \fine_inc[7][0]_i_1_n_0\
    );
\fine_inc[7][1]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00EB000000410000"
    )
        port map (
      I0 => \wl_state_r__0\(1),
      I1 => \fine_inc_reg[0][1]_i_2_n_0\,
      I2 => \fine_inc_reg[0][1]_i_3_n_0\,
      I3 => \^fsm_sequential_wl_state_r_reg[4]_0\(1),
      I4 => \wl_state_r__0\(0),
      I5 => \gen_final_tap[7].final_val_reg_n_0_[7][1]\,
      O => \fine_inc[7][1]_i_1_n_0\
    );
\fine_inc[7][2]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00EB000000410000"
    )
        port map (
      I0 => \wl_state_r__0\(1),
      I1 => \fine_inc_reg[0][2]_i_2_n_0\,
      I2 => \fine_inc[0][2]_i_3_n_0\,
      I3 => \^fsm_sequential_wl_state_r_reg[4]_0\(1),
      I4 => \wl_state_r__0\(0),
      I5 => \gen_final_tap[7].final_val_reg_n_0_[7][2]\,
      O => \fine_inc[7][2]_i_1_n_0\
    );
\fine_inc[7][3]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00EB000000410000"
    )
        port map (
      I0 => \wl_state_r__0\(1),
      I1 => \fine_inc_reg[0][3]_i_2_n_0\,
      I2 => \fine_inc[0][3]_i_3_n_0\,
      I3 => \^fsm_sequential_wl_state_r_reg[4]_0\(1),
      I4 => \wl_state_r__0\(0),
      I5 => \gen_final_tap[7].final_val_reg_n_0_[7][3]\,
      O => \fine_inc[7][3]_i_1_n_0\
    );
\fine_inc[7][4]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"40004444"
    )
        port map (
      I0 => \^fsm_sequential_wl_state_r_reg[4]_0\(1),
      I1 => \wl_state_r__0\(0),
      I2 => \wl_state_r__0\(1),
      I3 => \gen_final_tap[7].final_val_reg_n_0_[7][4]\,
      I4 => \fine_inc[0][4]_i_2_n_0\,
      O => \fine_inc[7][4]_i_1_n_0\
    );
\fine_inc[7][5]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0020AA0000200000"
    )
        port map (
      I0 => \fine_inc[0][5]_i_5_n_0\,
      I1 => \fine_inc[0][5]_i_3_n_0\,
      I2 => \fine_inc[7][5]_i_3_n_0\,
      I3 => \wl_state_r__0\(1),
      I4 => \^wr_level_done_r5\,
      I5 => wr_level_done_r4,
      O => \fine_inc[7][5]_i_1_n_0\
    );
\fine_inc[7][5]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"A280A280A28080A2"
    )
        port map (
      I0 => \fine_inc[0][5]_i_6_n_0\,
      I1 => \wl_state_r__0\(1),
      I2 => \gen_final_tap[7].final_val_reg_n_0_[7][5]\,
      I3 => \fine_inc_reg[0][5]_i_7_n_0\,
      I4 => \fine_inc[0][5]_i_8_n_0\,
      I5 => \fine_inc_reg[0][5]_i_9_n_0\,
      O => \fine_inc[7][5]_i_2_n_0\
    );
\fine_inc[7][5]_i_3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4000"
    )
        port map (
      I0 => \^dqs_count_r_reg[3]_0\(0),
      I1 => \^dqs_count_r_reg[2]_rep__0_0\,
      I2 => dqs_count_r(1),
      I3 => dqs_count_r(0),
      O => \fine_inc[7][5]_i_3_n_0\
    );
\fine_inc_reg[0][0]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => \fine_inc[0][5]_i_1_n_0\,
      D => fine_inc(0),
      Q => \fine_inc_reg[0]_5\(0),
      R => \fine_inc_reg[6][3]_0\(0)
    );
\fine_inc_reg[0][1]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => \fine_inc[0][5]_i_1_n_0\,
      D => fine_inc(1),
      Q => \fine_inc_reg[0]_5\(1),
      R => \fine_inc_reg[6][3]_0\(0)
    );
\fine_inc_reg[0][1]_i_2\: unisim.vcomponents.MUXF7
     port map (
      I0 => \fine_inc[0][1]_i_4_n_0\,
      I1 => \fine_inc[0][1]_i_5_n_0\,
      O => \fine_inc_reg[0][1]_i_2_n_0\,
      S => dqs_count_r(2)
    );
\fine_inc_reg[0][1]_i_3\: unisim.vcomponents.MUXF7
     port map (
      I0 => \fine_inc[0][1]_i_6_n_0\,
      I1 => \fine_inc[0][1]_i_7_n_0\,
      O => \fine_inc_reg[0][1]_i_3_n_0\,
      S => dqs_count_r(2)
    );
\fine_inc_reg[0][2]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => \fine_inc[0][5]_i_1_n_0\,
      D => fine_inc(2),
      Q => \fine_inc_reg[0]_5\(2),
      R => \fine_inc_reg[6][3]_0\(0)
    );
\fine_inc_reg[0][2]_i_2\: unisim.vcomponents.MUXF7
     port map (
      I0 => \fine_inc[0][2]_i_4_n_0\,
      I1 => \fine_inc[0][2]_i_5_n_0\,
      O => \fine_inc_reg[0][2]_i_2_n_0\,
      S => dqs_count_r(2)
    );
\fine_inc_reg[0][3]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => \fine_inc[0][5]_i_1_n_0\,
      D => fine_inc(3),
      Q => \fine_inc_reg[0]_5\(3),
      R => \fine_inc_reg[6][3]_0\(1)
    );
\fine_inc_reg[0][3]_i_2\: unisim.vcomponents.MUXF7
     port map (
      I0 => \fine_inc[0][3]_i_4_n_0\,
      I1 => \fine_inc[0][3]_i_5_n_0\,
      O => \fine_inc_reg[0][3]_i_2_n_0\,
      S => dqs_count_r(2)
    );
\fine_inc_reg[0][4]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => \fine_inc[0][5]_i_1_n_0\,
      D => fine_inc(4),
      Q => \fine_inc_reg[0]_5\(4),
      R => \fine_inc_reg[6][3]_0\(1)
    );
\fine_inc_reg[0][5]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => \fine_inc[0][5]_i_1_n_0\,
      D => fine_inc(5),
      Q => \fine_inc_reg[0]_5\(5),
      R => \fine_inc_reg[6][3]_0\(1)
    );
\fine_inc_reg[0][5]_i_7\: unisim.vcomponents.MUXF7
     port map (
      I0 => \fine_inc[0][5]_i_10_n_0\,
      I1 => \fine_inc[0][5]_i_11_n_0\,
      O => \fine_inc_reg[0][5]_i_7_n_0\,
      S => dqs_count_r(2)
    );
\fine_inc_reg[0][5]_i_9\: unisim.vcomponents.MUXF7
     port map (
      I0 => \fine_inc[0][5]_i_12_n_0\,
      I1 => \fine_inc[0][5]_i_13_n_0\,
      O => \fine_inc_reg[0][5]_i_9_n_0\,
      S => dqs_count_r(2)
    );
\fine_inc_reg[1][0]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => \fine_inc[1][5]_i_1_n_0\,
      D => \fine_inc[1][0]_i_1_n_0\,
      Q => \fine_inc_reg[1]_6\(0),
      R => \fine_inc_reg[6][3]_0\(0)
    );
\fine_inc_reg[1][1]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => \fine_inc[1][5]_i_1_n_0\,
      D => \fine_inc[1][1]_i_1_n_0\,
      Q => \fine_inc_reg[1]_6\(1),
      R => \fine_inc_reg[6][3]_0\(0)
    );
\fine_inc_reg[1][2]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => \fine_inc[1][5]_i_1_n_0\,
      D => \fine_inc[1][2]_i_1_n_0\,
      Q => \fine_inc_reg[1]_6\(2),
      R => \fine_inc_reg[6][3]_0\(0)
    );
\fine_inc_reg[1][3]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => \fine_inc[1][5]_i_1_n_0\,
      D => \fine_inc[1][3]_i_1_n_0\,
      Q => \fine_inc_reg[1]_6\(3),
      R => \fine_inc_reg[6][3]_0\(1)
    );
\fine_inc_reg[1][4]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => \fine_inc[1][5]_i_1_n_0\,
      D => \fine_inc[1][4]_i_1_n_0\,
      Q => \fine_inc_reg[1]_6\(4),
      R => \fine_inc_reg[6][3]_0\(1)
    );
\fine_inc_reg[1][5]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => \fine_inc[1][5]_i_1_n_0\,
      D => \fine_inc[1][5]_i_2_n_0\,
      Q => \fine_inc_reg[1]_6\(5),
      R => \fine_inc_reg[6][3]_0\(1)
    );
\fine_inc_reg[2][0]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => \fine_inc[2][5]_i_1_n_0\,
      D => \fine_inc[2][0]_i_1_n_0\,
      Q => \fine_inc_reg[2]_7\(0),
      R => \fine_inc_reg[6][3]_0\(0)
    );
\fine_inc_reg[2][1]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => \fine_inc[2][5]_i_1_n_0\,
      D => \fine_inc[2][1]_i_1_n_0\,
      Q => \fine_inc_reg[2]_7\(1),
      R => \fine_inc_reg[6][3]_0\(0)
    );
\fine_inc_reg[2][2]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => \fine_inc[2][5]_i_1_n_0\,
      D => \fine_inc[2][2]_i_1_n_0\,
      Q => \fine_inc_reg[2]_7\(2),
      R => \fine_inc_reg[6][3]_0\(0)
    );
\fine_inc_reg[2][3]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => \fine_inc[2][5]_i_1_n_0\,
      D => \fine_inc[2][3]_i_1_n_0\,
      Q => \fine_inc_reg[2]_7\(3),
      R => \fine_inc_reg[6][3]_0\(1)
    );
\fine_inc_reg[2][4]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => \fine_inc[2][5]_i_1_n_0\,
      D => \fine_inc[2][4]_i_1_n_0\,
      Q => \fine_inc_reg[2]_7\(4),
      R => \fine_inc_reg[6][3]_0\(1)
    );
\fine_inc_reg[2][5]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => \fine_inc[2][5]_i_1_n_0\,
      D => \fine_inc[2][5]_i_2_n_0\,
      Q => \fine_inc_reg[2]_7\(5),
      R => \fine_inc_reg[6][3]_0\(1)
    );
\fine_inc_reg[3][0]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => \fine_inc[3][5]_i_1_n_0\,
      D => \fine_inc[3][0]_i_1_n_0\,
      Q => \fine_inc_reg[3]_8\(0),
      R => \fine_inc_reg[6][3]_0\(0)
    );
\fine_inc_reg[3][1]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => \fine_inc[3][5]_i_1_n_0\,
      D => \fine_inc[3][1]_i_1_n_0\,
      Q => \fine_inc_reg[3]_8\(1),
      R => \fine_inc_reg[6][3]_0\(0)
    );
\fine_inc_reg[3][2]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => \fine_inc[3][5]_i_1_n_0\,
      D => \fine_inc[3][2]_i_1_n_0\,
      Q => \fine_inc_reg[3]_8\(2),
      R => \fine_inc_reg[6][3]_0\(0)
    );
\fine_inc_reg[3][3]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => \fine_inc[3][5]_i_1_n_0\,
      D => \fine_inc[3][3]_i_1_n_0\,
      Q => \fine_inc_reg[3]_8\(3),
      R => \fine_inc_reg[6][3]_0\(1)
    );
\fine_inc_reg[3][4]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => \fine_inc[3][5]_i_1_n_0\,
      D => \fine_inc[3][4]_i_1_n_0\,
      Q => \fine_inc_reg[3]_8\(4),
      R => \fine_inc_reg[6][3]_0\(1)
    );
\fine_inc_reg[3][5]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => \fine_inc[3][5]_i_1_n_0\,
      D => \fine_inc[3][5]_i_2_n_0\,
      Q => \fine_inc_reg[3]_8\(5),
      R => \fine_inc_reg[6][3]_0\(1)
    );
\fine_inc_reg[4][0]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => \fine_inc[4][5]_i_1_n_0\,
      D => \fine_inc[4][0]_i_1_n_0\,
      Q => \fine_inc_reg[4]_9\(0),
      R => \fine_inc_reg[6][3]_0\(0)
    );
\fine_inc_reg[4][1]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => \fine_inc[4][5]_i_1_n_0\,
      D => \fine_inc[4][1]_i_1_n_0\,
      Q => \fine_inc_reg[4]_9\(1),
      R => \fine_inc_reg[6][3]_0\(0)
    );
\fine_inc_reg[4][2]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => \fine_inc[4][5]_i_1_n_0\,
      D => \fine_inc[4][2]_i_1_n_0\,
      Q => \fine_inc_reg[4]_9\(2),
      R => \fine_inc_reg[6][3]_0\(0)
    );
\fine_inc_reg[4][3]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => \fine_inc[4][5]_i_1_n_0\,
      D => \fine_inc[4][3]_i_1_n_0\,
      Q => \fine_inc_reg[4]_9\(3),
      R => \fine_inc_reg[6][3]_0\(1)
    );
\fine_inc_reg[4][4]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => \fine_inc[4][5]_i_1_n_0\,
      D => \fine_inc[4][4]_i_1_n_0\,
      Q => \fine_inc_reg[4]_9\(4),
      R => \fine_inc_reg[6][3]_0\(1)
    );
\fine_inc_reg[4][5]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => \fine_inc[4][5]_i_1_n_0\,
      D => \fine_inc[4][5]_i_2_n_0\,
      Q => \fine_inc_reg[4]_9\(5),
      R => \fine_inc_reg[6][3]_0\(1)
    );
\fine_inc_reg[5][0]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => \fine_inc[5][5]_i_1_n_0\,
      D => \fine_inc[5][0]_i_1_n_0\,
      Q => \fine_inc_reg[5]_10\(0),
      R => \fine_inc_reg[6][3]_0\(0)
    );
\fine_inc_reg[5][1]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => \fine_inc[5][5]_i_1_n_0\,
      D => \fine_inc[5][1]_i_1_n_0\,
      Q => \fine_inc_reg[5]_10\(1),
      R => \fine_inc_reg[6][3]_0\(0)
    );
\fine_inc_reg[5][2]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => \fine_inc[5][5]_i_1_n_0\,
      D => \fine_inc[5][2]_i_1_n_0\,
      Q => \fine_inc_reg[5]_10\(2),
      R => \fine_inc_reg[6][3]_0\(0)
    );
\fine_inc_reg[5][3]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => \fine_inc[5][5]_i_1_n_0\,
      D => \fine_inc[5][3]_i_1_n_0\,
      Q => \fine_inc_reg[5]_10\(3),
      R => \fine_inc_reg[6][3]_0\(1)
    );
\fine_inc_reg[5][4]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => \fine_inc[5][5]_i_1_n_0\,
      D => \fine_inc[5][4]_i_1_n_0\,
      Q => \fine_inc_reg[5]_10\(4),
      R => \fine_inc_reg[6][3]_0\(1)
    );
\fine_inc_reg[5][5]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => \fine_inc[5][5]_i_1_n_0\,
      D => \fine_inc[5][5]_i_2_n_0\,
      Q => \fine_inc_reg[5]_10\(5),
      R => \fine_inc_reg[6][3]_0\(1)
    );
\fine_inc_reg[6][0]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => \fine_inc[6][5]_i_1_n_0\,
      D => \fine_inc[6][0]_i_1_n_0\,
      Q => \fine_inc_reg[6]_11\(0),
      R => \fine_inc_reg[6][3]_0\(0)
    );
\fine_inc_reg[6][1]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => \fine_inc[6][5]_i_1_n_0\,
      D => \fine_inc[6][1]_i_1_n_0\,
      Q => \fine_inc_reg[6]_11\(1),
      R => \fine_inc_reg[6][3]_0\(0)
    );
\fine_inc_reg[6][2]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => \fine_inc[6][5]_i_1_n_0\,
      D => \fine_inc[6][2]_i_1_n_0\,
      Q => \fine_inc_reg[6]_11\(2),
      R => \fine_inc_reg[6][3]_0\(0)
    );
\fine_inc_reg[6][3]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => \fine_inc[6][5]_i_1_n_0\,
      D => \fine_inc[6][3]_i_1_n_0\,
      Q => \fine_inc_reg[6]_11\(3),
      R => \fine_inc_reg[6][3]_0\(1)
    );
\fine_inc_reg[6][4]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => \fine_inc[6][5]_i_1_n_0\,
      D => \fine_inc[6][4]_i_1_n_0\,
      Q => \fine_inc_reg[6]_11\(4),
      R => \fine_inc_reg[6][3]_0\(1)
    );
\fine_inc_reg[6][5]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => \fine_inc[6][5]_i_1_n_0\,
      D => \fine_inc[6][5]_i_2_n_0\,
      Q => \fine_inc_reg[6]_11\(5),
      R => \fine_inc_reg[6][3]_0\(1)
    );
\fine_inc_reg[7][0]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => \fine_inc[7][5]_i_1_n_0\,
      D => \fine_inc[7][0]_i_1_n_0\,
      Q => \fine_inc_reg[7]_12\(0),
      R => \fine_inc_reg[6][3]_0\(0)
    );
\fine_inc_reg[7][1]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => \fine_inc[7][5]_i_1_n_0\,
      D => \fine_inc[7][1]_i_1_n_0\,
      Q => \fine_inc_reg[7]_12\(1),
      R => \fine_inc_reg[6][3]_0\(0)
    );
\fine_inc_reg[7][2]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => \fine_inc[7][5]_i_1_n_0\,
      D => \fine_inc[7][2]_i_1_n_0\,
      Q => \fine_inc_reg[7]_12\(2),
      R => \fine_inc_reg[6][3]_0\(0)
    );
\fine_inc_reg[7][3]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => \fine_inc[7][5]_i_1_n_0\,
      D => \fine_inc[7][3]_i_1_n_0\,
      Q => \fine_inc_reg[7]_12\(3),
      R => \fine_inc_reg[6][3]_0\(1)
    );
\fine_inc_reg[7][4]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => \fine_inc[7][5]_i_1_n_0\,
      D => \fine_inc[7][4]_i_1_n_0\,
      Q => \fine_inc_reg[7]_12\(4),
      R => \fine_inc_reg[6][3]_0\(1)
    );
\fine_inc_reg[7][5]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => \fine_inc[7][5]_i_1_n_0\,
      D => \fine_inc[7][5]_i_2_n_0\,
      Q => \fine_inc_reg[7]_12\(5),
      R => \fine_inc_reg[6][3]_0\(1)
    );
flag_ck_negedge_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"2222222220222222"
    )
        port map (
      I0 => \stable_cnt[3]_i_5_n_0\,
      I1 => flag_ck_negedge_i_2_n_0,
      I2 => \wl_state_r__0\(2),
      I3 => \wl_state_r__0\(1),
      I4 => \fine_inc[0][5]_i_6_n_0\,
      I5 => \^fsm_sequential_wl_state_r_reg[4]_0\(0),
      O => flag_ck_negedge_i_1_n_0
    );
flag_ck_negedge_i_2: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ABABABAF"
    )
        port map (
      I0 => wr_level_done_r_reg_n_0,
      I1 => flag_ck_negedge_reg_n_0,
      I2 => flag_ck_negedge09_out,
      I3 => \stable_cnt_reg_n_0_[0]\,
      I4 => \FSM_sequential_wl_state_r[3]_i_14_n_0\,
      O => flag_ck_negedge_i_2_n_0
    );
flag_ck_negedge_i_3: unisim.vcomponents.LUT6
    generic map(
      INIT => X"4000FFFF40004000"
    )
        port map (
      I0 => \wl_state_r__0\(2),
      I1 => \rank_cnt_r[1]_i_2_n_0\,
      I2 => \^fsm_sequential_wl_state_r_reg[4]_0\(0),
      I3 => \wl_state_r__0\(0),
      I4 => flag_ck_negedge_i_4_n_0,
      I5 => \rd_data_edge_detect_r_reg[7]_i_9_n_0\,
      O => flag_ck_negedge09_out
    );
flag_ck_negedge_i_4: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000010000"
    )
        port map (
      I0 => \stable_cnt_reg_n_0_[1]\,
      I1 => \stable_cnt_reg_n_0_[0]\,
      I2 => \stable_cnt_reg_n_0_[3]\,
      I3 => \stable_cnt_reg_n_0_[2]\,
      I4 => flag_ck_negedge_i_5_n_0,
      I5 => flag_ck_negedge_i_6_n_0,
      O => flag_ck_negedge_i_4_n_0
    );
flag_ck_negedge_i_5: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFFEFF"
    )
        port map (
      I0 => \^fsm_sequential_wl_state_r_reg[4]_0\(0),
      I1 => \^fsm_sequential_wl_state_r_reg[4]_0\(1),
      I2 => \wl_state_r__0\(2),
      I3 => \wl_state_r__0\(0),
      I4 => \wl_state_r__0\(1),
      O => flag_ck_negedge_i_5_n_0
    );
flag_ck_negedge_i_6: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000401"
    )
        port map (
      I0 => \wl_state_r__0\(1),
      I1 => \^fsm_sequential_wl_state_r_reg[4]_0\(1),
      I2 => \wl_state_r__0\(2),
      I3 => \wl_state_r__0\(0),
      I4 => \^fsm_sequential_wl_state_r_reg[4]_0\(0),
      O => flag_ck_negedge_i_6_n_0
    );
flag_ck_negedge_reg: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => '1',
      D => flag_ck_negedge_i_1_n_0,
      Q => flag_ck_negedge_reg_n_0,
      R => '0'
    );
flag_init_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAA8AAAAAAAAAA"
    )
        port map (
      I0 => flag_init,
      I1 => \wl_state_r1_reg_n_0_[0]\,
      I2 => \wl_state_r1_reg_n_0_[3]\,
      I3 => \wl_state_r1_reg_n_0_[2]\,
      I4 => \wl_state_r1_reg_n_0_[4]\,
      I5 => flag_init_i_2_n_0,
      O => flag_init_i_1_n_0
    );
flag_init_i_2: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000040"
    )
        port map (
      I0 => \wl_state_r__0\(0),
      I1 => \wl_state_r__0\(1),
      I2 => \wl_state_r__0\(2),
      I3 => \^fsm_sequential_wl_state_r_reg[4]_0\(0),
      I4 => \^fsm_sequential_wl_state_r_reg[4]_0\(1),
      O => flag_init_i_2_n_0
    );
flag_init_reg: unisim.vcomponents.FDSE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => '1',
      D => flag_init_i_1_n_0,
      Q => flag_init,
      S => \wl_dqs_tap_count_r_reg[0][5][5]_0\
    );
\gen_final_tap[0].final_val[0][5]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => wr_level_done_r2,
      I1 => wr_level_done_r3,
      O => \gen_final_tap[0].final_val[0][5]_i_1_n_0\
    );
\gen_final_tap[0].final_val_reg[0][0]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => \gen_final_tap[0].final_val[0][5]_i_1_n_0\,
      D => \smallest_reg[0]_13\(0),
      Q => \gen_final_tap[0].final_val_reg_n_0_[0][0]\,
      R => \corse_dec_reg[7][0]_0\(1)
    );
\gen_final_tap[0].final_val_reg[0][1]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => \gen_final_tap[0].final_val[0][5]_i_1_n_0\,
      D => \smallest_reg[0]_13\(1),
      Q => \gen_final_tap[0].final_val_reg_n_0_[0][1]\,
      R => \corse_dec_reg[7][0]_0\(1)
    );
\gen_final_tap[0].final_val_reg[0][2]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => \gen_final_tap[0].final_val[0][5]_i_1_n_0\,
      D => \smallest_reg[0]_13\(2),
      Q => \gen_final_tap[0].final_val_reg_n_0_[0][2]\,
      R => \corse_dec_reg[7][0]_0\(1)
    );
\gen_final_tap[0].final_val_reg[0][3]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => \gen_final_tap[0].final_val[0][5]_i_1_n_0\,
      D => \smallest_reg[0]_13\(3),
      Q => \gen_final_tap[0].final_val_reg_n_0_[0][3]\,
      R => \corse_dec_reg[7][0]_0\(1)
    );
\gen_final_tap[0].final_val_reg[0][4]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => \gen_final_tap[0].final_val[0][5]_i_1_n_0\,
      D => \smallest_reg[0]_13\(4),
      Q => \gen_final_tap[0].final_val_reg_n_0_[0][4]\,
      R => \corse_dec_reg[7][0]_0\(1)
    );
\gen_final_tap[0].final_val_reg[0][5]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => \gen_final_tap[0].final_val[0][5]_i_1_n_0\,
      D => \smallest_reg[0]_13\(5),
      Q => \gen_final_tap[0].final_val_reg_n_0_[0][5]\,
      R => \corse_dec_reg[7][0]_0\(1)
    );
\gen_final_tap[1].final_val_reg[1][0]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => \gen_final_tap[0].final_val[0][5]_i_1_n_0\,
      D => \smallest_reg[1]_14\(0),
      Q => \gen_final_tap[1].final_val_reg_n_0_[1][0]\,
      R => \corse_dec_reg[7][0]_0\(1)
    );
\gen_final_tap[1].final_val_reg[1][1]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => \gen_final_tap[0].final_val[0][5]_i_1_n_0\,
      D => \smallest_reg[1]_14\(1),
      Q => \gen_final_tap[1].final_val_reg_n_0_[1][1]\,
      R => \corse_dec_reg[7][0]_0\(1)
    );
\gen_final_tap[1].final_val_reg[1][2]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => \gen_final_tap[0].final_val[0][5]_i_1_n_0\,
      D => \smallest_reg[1]_14\(2),
      Q => \gen_final_tap[1].final_val_reg_n_0_[1][2]\,
      R => \corse_dec_reg[7][0]_0\(1)
    );
\gen_final_tap[1].final_val_reg[1][3]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => \gen_final_tap[0].final_val[0][5]_i_1_n_0\,
      D => \smallest_reg[1]_14\(3),
      Q => \gen_final_tap[1].final_val_reg_n_0_[1][3]\,
      R => \corse_dec_reg[7][0]_0\(1)
    );
\gen_final_tap[1].final_val_reg[1][4]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => \gen_final_tap[0].final_val[0][5]_i_1_n_0\,
      D => \smallest_reg[1]_14\(4),
      Q => \gen_final_tap[1].final_val_reg_n_0_[1][4]\,
      R => \corse_dec_reg[7][0]_0\(1)
    );
\gen_final_tap[1].final_val_reg[1][5]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => \gen_final_tap[0].final_val[0][5]_i_1_n_0\,
      D => \smallest_reg[1]_14\(5),
      Q => \gen_final_tap[1].final_val_reg_n_0_[1][5]\,
      R => \corse_dec_reg[7][0]_0\(1)
    );
\gen_final_tap[2].final_val_reg[2][0]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => \gen_final_tap[0].final_val[0][5]_i_1_n_0\,
      D => \smallest_reg[2]_15\(0),
      Q => \gen_final_tap[2].final_val_reg_n_0_[2][0]\,
      R => \wl_dqs_tap_count_r_reg[0][5][5]_0\
    );
\gen_final_tap[2].final_val_reg[2][1]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => \gen_final_tap[0].final_val[0][5]_i_1_n_0\,
      D => \smallest_reg[2]_15\(1),
      Q => \gen_final_tap[2].final_val_reg_n_0_[2][1]\,
      R => \wl_dqs_tap_count_r_reg[0][5][5]_0\
    );
\gen_final_tap[2].final_val_reg[2][2]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => \gen_final_tap[0].final_val[0][5]_i_1_n_0\,
      D => \smallest_reg[2]_15\(2),
      Q => \gen_final_tap[2].final_val_reg_n_0_[2][2]\,
      R => \wl_dqs_tap_count_r_reg[0][5][5]_0\
    );
\gen_final_tap[2].final_val_reg[2][3]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => \gen_final_tap[0].final_val[0][5]_i_1_n_0\,
      D => \smallest_reg[2]_15\(3),
      Q => \gen_final_tap[2].final_val_reg_n_0_[2][3]\,
      R => \wl_dqs_tap_count_r_reg[0][5][5]_0\
    );
\gen_final_tap[2].final_val_reg[2][4]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => \gen_final_tap[0].final_val[0][5]_i_1_n_0\,
      D => \smallest_reg[2]_15\(4),
      Q => \gen_final_tap[2].final_val_reg_n_0_[2][4]\,
      R => \wl_dqs_tap_count_r_reg[0][5][5]_0\
    );
\gen_final_tap[2].final_val_reg[2][5]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => \gen_final_tap[0].final_val[0][5]_i_1_n_0\,
      D => \smallest_reg[2]_15\(5),
      Q => \gen_final_tap[2].final_val_reg_n_0_[2][5]\,
      R => \wl_dqs_tap_count_r_reg[0][5][5]_0\
    );
\gen_final_tap[3].final_val_reg[3][0]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => \gen_final_tap[0].final_val[0][5]_i_1_n_0\,
      D => \smallest_reg[3]_16\(0),
      Q => \gen_final_tap[3].final_val_reg_n_0_[3][0]\,
      R => \corse_dec_reg[7][0]_0\(1)
    );
\gen_final_tap[3].final_val_reg[3][1]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => \gen_final_tap[0].final_val[0][5]_i_1_n_0\,
      D => \smallest_reg[3]_16\(1),
      Q => \gen_final_tap[3].final_val_reg_n_0_[3][1]\,
      R => \corse_dec_reg[7][0]_0\(1)
    );
\gen_final_tap[3].final_val_reg[3][2]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => \gen_final_tap[0].final_val[0][5]_i_1_n_0\,
      D => \smallest_reg[3]_16\(2),
      Q => \gen_final_tap[3].final_val_reg_n_0_[3][2]\,
      R => \corse_dec_reg[7][0]_0\(1)
    );
\gen_final_tap[3].final_val_reg[3][3]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => \gen_final_tap[0].final_val[0][5]_i_1_n_0\,
      D => \smallest_reg[3]_16\(3),
      Q => \gen_final_tap[3].final_val_reg_n_0_[3][3]\,
      R => \corse_dec_reg[7][0]_0\(1)
    );
\gen_final_tap[3].final_val_reg[3][4]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => \gen_final_tap[0].final_val[0][5]_i_1_n_0\,
      D => \smallest_reg[3]_16\(4),
      Q => \gen_final_tap[3].final_val_reg_n_0_[3][4]\,
      R => \corse_dec_reg[7][0]_0\(1)
    );
\gen_final_tap[3].final_val_reg[3][5]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => \gen_final_tap[0].final_val[0][5]_i_1_n_0\,
      D => \smallest_reg[3]_16\(5),
      Q => \gen_final_tap[3].final_val_reg_n_0_[3][5]\,
      R => \corse_dec_reg[7][0]_0\(1)
    );
\gen_final_tap[4].final_val_reg[4][0]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => \gen_final_tap[0].final_val[0][5]_i_1_n_0\,
      D => \smallest_reg[4]_17\(0),
      Q => \gen_final_tap[4].final_val_reg_n_0_[4][0]\,
      R => \wl_dqs_tap_count_r_reg[0][5][5]_0\
    );
\gen_final_tap[4].final_val_reg[4][1]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => \gen_final_tap[0].final_val[0][5]_i_1_n_0\,
      D => \smallest_reg[4]_17\(1),
      Q => \gen_final_tap[4].final_val_reg_n_0_[4][1]\,
      R => \wl_dqs_tap_count_r_reg[0][5][5]_0\
    );
\gen_final_tap[4].final_val_reg[4][2]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => \gen_final_tap[0].final_val[0][5]_i_1_n_0\,
      D => \smallest_reg[4]_17\(2),
      Q => \gen_final_tap[4].final_val_reg_n_0_[4][2]\,
      R => \wl_dqs_tap_count_r_reg[0][5][5]_0\
    );
\gen_final_tap[4].final_val_reg[4][3]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => \gen_final_tap[0].final_val[0][5]_i_1_n_0\,
      D => \smallest_reg[4]_17\(3),
      Q => \gen_final_tap[4].final_val_reg_n_0_[4][3]\,
      R => \wl_dqs_tap_count_r_reg[0][5][5]_0\
    );
\gen_final_tap[4].final_val_reg[4][4]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => \gen_final_tap[0].final_val[0][5]_i_1_n_0\,
      D => \smallest_reg[4]_17\(4),
      Q => \gen_final_tap[4].final_val_reg_n_0_[4][4]\,
      R => \wl_dqs_tap_count_r_reg[0][5][5]_0\
    );
\gen_final_tap[4].final_val_reg[4][5]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => \gen_final_tap[0].final_val[0][5]_i_1_n_0\,
      D => \smallest_reg[4]_17\(5),
      Q => \gen_final_tap[4].final_val_reg_n_0_[4][5]\,
      R => \wl_dqs_tap_count_r_reg[0][5][5]_0\
    );
\gen_final_tap[5].final_val_reg[5][0]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => \gen_final_tap[0].final_val[0][5]_i_1_n_0\,
      D => \smallest_reg[5]_18\(0),
      Q => \gen_final_tap[5].final_val_reg_n_0_[5][0]\,
      R => \corse_inc_reg[6][2]_0\(1)
    );
\gen_final_tap[5].final_val_reg[5][1]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => \gen_final_tap[0].final_val[0][5]_i_1_n_0\,
      D => \smallest_reg[5]_18\(1),
      Q => \gen_final_tap[5].final_val_reg_n_0_[5][1]\,
      R => \corse_dec_reg[7][0]_0\(1)
    );
\gen_final_tap[5].final_val_reg[5][2]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => \gen_final_tap[0].final_val[0][5]_i_1_n_0\,
      D => \smallest_reg[5]_18\(2),
      Q => \gen_final_tap[5].final_val_reg_n_0_[5][2]\,
      R => \corse_dec_reg[7][0]_0\(1)
    );
\gen_final_tap[5].final_val_reg[5][3]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => \gen_final_tap[0].final_val[0][5]_i_1_n_0\,
      D => \smallest_reg[5]_18\(3),
      Q => \gen_final_tap[5].final_val_reg_n_0_[5][3]\,
      R => \corse_dec_reg[7][0]_0\(1)
    );
\gen_final_tap[5].final_val_reg[5][4]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => \gen_final_tap[0].final_val[0][5]_i_1_n_0\,
      D => \smallest_reg[5]_18\(4),
      Q => \gen_final_tap[5].final_val_reg_n_0_[5][4]\,
      R => \corse_dec_reg[7][0]_0\(1)
    );
\gen_final_tap[5].final_val_reg[5][5]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => \gen_final_tap[0].final_val[0][5]_i_1_n_0\,
      D => \smallest_reg[5]_18\(5),
      Q => \gen_final_tap[5].final_val_reg_n_0_[5][5]\,
      R => \corse_dec_reg[7][0]_0\(1)
    );
\gen_final_tap[6].final_val_reg[6][0]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => \gen_final_tap[0].final_val[0][5]_i_1_n_0\,
      D => \smallest_reg[6]_19\(0),
      Q => \gen_final_tap[6].final_val_reg_n_0_[6][0]\,
      R => \wl_dqs_tap_count_r_reg[0][5][5]_0\
    );
\gen_final_tap[6].final_val_reg[6][1]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => \gen_final_tap[0].final_val[0][5]_i_1_n_0\,
      D => \smallest_reg[6]_19\(1),
      Q => \gen_final_tap[6].final_val_reg_n_0_[6][1]\,
      R => \wl_dqs_tap_count_r_reg[0][5][5]_0\
    );
\gen_final_tap[6].final_val_reg[6][2]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => \gen_final_tap[0].final_val[0][5]_i_1_n_0\,
      D => \smallest_reg[6]_19\(2),
      Q => \gen_final_tap[6].final_val_reg_n_0_[6][2]\,
      R => \wl_dqs_tap_count_r_reg[0][5][5]_0\
    );
\gen_final_tap[6].final_val_reg[6][3]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => \gen_final_tap[0].final_val[0][5]_i_1_n_0\,
      D => \smallest_reg[6]_19\(3),
      Q => \gen_final_tap[6].final_val_reg_n_0_[6][3]\,
      R => \wl_dqs_tap_count_r_reg[0][5][5]_0\
    );
\gen_final_tap[6].final_val_reg[6][4]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => \gen_final_tap[0].final_val[0][5]_i_1_n_0\,
      D => \smallest_reg[6]_19\(4),
      Q => \gen_final_tap[6].final_val_reg_n_0_[6][4]\,
      R => \wl_dqs_tap_count_r_reg[0][5][5]_0\
    );
\gen_final_tap[6].final_val_reg[6][5]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => \gen_final_tap[0].final_val[0][5]_i_1_n_0\,
      D => \smallest_reg[6]_19\(5),
      Q => \gen_final_tap[6].final_val_reg_n_0_[6][5]\,
      R => \wl_dqs_tap_count_r_reg[0][5][5]_0\
    );
\gen_final_tap[7].final_val_reg[7][0]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => \gen_final_tap[0].final_val[0][5]_i_1_n_0\,
      D => \smallest_reg[7]_20\(0),
      Q => \gen_final_tap[7].final_val_reg_n_0_[7][0]\,
      R => \corse_inc_reg[6][2]_0\(1)
    );
\gen_final_tap[7].final_val_reg[7][1]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => \gen_final_tap[0].final_val[0][5]_i_1_n_0\,
      D => \smallest_reg[7]_20\(1),
      Q => \gen_final_tap[7].final_val_reg_n_0_[7][1]\,
      R => \corse_inc_reg[6][2]_0\(1)
    );
\gen_final_tap[7].final_val_reg[7][2]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => \gen_final_tap[0].final_val[0][5]_i_1_n_0\,
      D => \smallest_reg[7]_20\(2),
      Q => \gen_final_tap[7].final_val_reg_n_0_[7][2]\,
      R => \corse_inc_reg[6][2]_0\(1)
    );
\gen_final_tap[7].final_val_reg[7][3]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => \gen_final_tap[0].final_val[0][5]_i_1_n_0\,
      D => \smallest_reg[7]_20\(3),
      Q => \gen_final_tap[7].final_val_reg_n_0_[7][3]\,
      R => \corse_inc_reg[6][2]_0\(1)
    );
\gen_final_tap[7].final_val_reg[7][4]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => \gen_final_tap[0].final_val[0][5]_i_1_n_0\,
      D => \smallest_reg[7]_20\(4),
      Q => \gen_final_tap[7].final_val_reg_n_0_[7][4]\,
      R => \corse_inc_reg[6][2]_0\(1)
    );
\gen_final_tap[7].final_val_reg[7][5]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => \gen_final_tap[0].final_val[0][5]_i_1_n_0\,
      D => \smallest_reg[7]_20\(5),
      Q => \gen_final_tap[7].final_val_reg_n_0_[7][5]\,
      R => \corse_inc_reg[6][2]_0\(1)
    );
\gen_rd[0].rd_data_rise_wl_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => '1',
      D => \p_0_in__0\,
      Q => \gen_rd[0].rd_data_rise_wl_r_reg_n_0_[0]\,
      R => '0'
    );
\gen_rd[1].rd_data_rise_wl_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => '1',
      D => \p_0_out_inferred__19/gen_rd[1].rd_data_rise_wl_r[1]_i_1_n_0\,
      Q => \gen_rd[1].rd_data_rise_wl_r_reg_n_0_[1]\,
      R => '0'
    );
\gen_rd[2].rd_data_rise_wl_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => '1',
      D => \p_0_out_inferred__20/gen_rd[2].rd_data_rise_wl_r[2]_i_1_n_0\,
      Q => \gen_rd[2].rd_data_rise_wl_r_reg_n_0_[2]\,
      R => '0'
    );
\gen_rd[3].rd_data_rise_wl_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => '1',
      D => \p_0_out_inferred__21/gen_rd[3].rd_data_rise_wl_r[3]_i_1_n_0\,
      Q => \gen_rd[3].rd_data_rise_wl_r_reg_n_0_[3]\,
      R => '0'
    );
\gen_rd[4].rd_data_rise_wl_r_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => '1',
      D => \p_0_out_inferred__22/gen_rd[4].rd_data_rise_wl_r[4]_i_1_n_0\,
      Q => \gen_rd[4].rd_data_rise_wl_r_reg_n_0_[4]\,
      R => '0'
    );
\gen_rd[5].rd_data_rise_wl_r_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => '1',
      D => \p_0_out_inferred__23/gen_rd[5].rd_data_rise_wl_r[5]_i_1_n_0\,
      Q => \gen_rd[5].rd_data_rise_wl_r_reg_n_0_[5]\,
      R => '0'
    );
\gen_rd[6].rd_data_rise_wl_r_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => '1',
      D => \p_0_out_inferred__24/gen_rd[6].rd_data_rise_wl_r[6]_i_1_n_0\,
      Q => \gen_rd[6].rd_data_rise_wl_r_reg_n_0_[6]\,
      R => '0'
    );
\gen_rd[7].rd_data_rise_wl_r_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => '1',
      D => \p_0_out_inferred__25/gen_rd[7].rd_data_rise_wl_r[7]_i_1_n_0\,
      Q => \gen_rd[7].rd_data_rise_wl_r_reg_n_0_[7]\,
      R => '0'
    );
\incdec_wait_cnt[0]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => incdec_wait_cnt_reg(0),
      O => \p_0_in__2\(0)
    );
\incdec_wait_cnt[1]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => incdec_wait_cnt_reg(0),
      I1 => incdec_wait_cnt_reg(1),
      O => \p_0_in__2\(1)
    );
\incdec_wait_cnt[2]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"6A"
    )
        port map (
      I0 => incdec_wait_cnt_reg(2),
      I1 => incdec_wait_cnt_reg(1),
      I2 => incdec_wait_cnt_reg(0),
      O => \p_0_in__2\(2)
    );
\incdec_wait_cnt[3]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"EFFFFFFEFFFFFEFF"
    )
        port map (
      I0 => \single_rank.done_dqs_dec_reg_0\,
      I1 => \^fsm_sequential_wl_state_r_reg[4]_0\(0),
      I2 => \wl_state_r__0\(2),
      I3 => \wl_state_r__0\(0),
      I4 => \wl_state_r__0\(1),
      I5 => \^fsm_sequential_wl_state_r_reg[4]_0\(1),
      O => \incdec_wait_cnt[3]_i_1_n_0\
    );
\incdec_wait_cnt[3]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6AAA"
    )
        port map (
      I0 => incdec_wait_cnt_reg(3),
      I1 => incdec_wait_cnt_reg(0),
      I2 => incdec_wait_cnt_reg(1),
      I3 => incdec_wait_cnt_reg(2),
      O => \p_0_in__2\(3)
    );
\incdec_wait_cnt_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => '1',
      D => \p_0_in__2\(0),
      Q => incdec_wait_cnt_reg(0),
      R => \incdec_wait_cnt[3]_i_1_n_0\
    );
\incdec_wait_cnt_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => '1',
      D => \p_0_in__2\(1),
      Q => incdec_wait_cnt_reg(1),
      R => \incdec_wait_cnt[3]_i_1_n_0\
    );
\incdec_wait_cnt_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => '1',
      D => \p_0_in__2\(2),
      Q => incdec_wait_cnt_reg(2),
      R => \incdec_wait_cnt[3]_i_1_n_0\
    );
\incdec_wait_cnt_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => '1',
      D => \p_0_in__2\(3),
      Q => incdec_wait_cnt_reg(3),
      R => \incdec_wait_cnt[3]_i_1_n_0\
    );
inhibit_edge_detect_r_i_1: unisim.vcomponents.LUT5
    generic map(
      INIT => X"EEEFEEE0"
    )
        port map (
      I0 => \wl_state_r__0\(2),
      I1 => inhibit_edge_detect_r_i_2_n_0,
      I2 => inhibit_edge_detect_r_i_3_n_0,
      I3 => inhibit_edge_detect_r_i_4_n_0,
      I4 => inhibit_edge_detect_r_reg_n_0,
      O => inhibit_edge_detect_r_i_1_n_0
    );
inhibit_edge_detect_r_i_2: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00E2FFE2FFE2FFE2"
    )
        port map (
      I0 => \rd_data_edge_detect_r_reg[7]_i_9_n_0\,
      I1 => \wl_state_r__0\(1),
      I2 => wrlvl_byte_redo,
      I3 => \^fsm_sequential_wl_state_r_reg[4]_0\(1),
      I4 => \^fsm_sequential_wl_state_r_reg[4]_0\(0),
      I5 => \FSM_sequential_wl_state_r[4]_i_17_n_0\,
      O => inhibit_edge_detect_r_i_2_n_0
    );
inhibit_edge_detect_r_i_3: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0101000008FF0000"
    )
        port map (
      I0 => \^fsm_sequential_wl_state_r_reg[4]_0\(0),
      I1 => \wl_state_r__0\(2),
      I2 => \wl_state_r__0\(0),
      I3 => \FSM_sequential_wl_state_r[0]_i_7_n_0\,
      I4 => \wl_state_r__0\(1),
      I5 => \^fsm_sequential_wl_state_r_reg[4]_0\(1),
      O => inhibit_edge_detect_r_i_3_n_0
    );
inhibit_edge_detect_r_i_4: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0020022000200020"
    )
        port map (
      I0 => inhibit_edge_detect_r_i_5_n_0,
      I1 => \wl_state_r__0\(2),
      I2 => \^fsm_sequential_wl_state_r_reg[4]_0\(1),
      I3 => \wl_state_r__0\(0),
      I4 => \FSM_sequential_wl_state_r[3]_i_14_n_0\,
      I5 => wl_sm_start,
      O => inhibit_edge_detect_r_i_4_n_0
    );
inhibit_edge_detect_r_i_5: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \^fsm_sequential_wl_state_r_reg[4]_0\(0),
      I1 => \wl_state_r__0\(1),
      O => inhibit_edge_detect_r_i_5_n_0
    );
inhibit_edge_detect_r_reg: unisim.vcomponents.FDSE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => '1',
      D => inhibit_edge_detect_r_i_1_n_0,
      Q => inhibit_edge_detect_r_reg_n_0,
      S => \corse_inc_reg[6][2]_0\(0)
    );
\p_0_out_inferred__18/gen_rd[0].rd_data_rise_wl_r[0]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFFFFE"
    )
        port map (
      I0 => \gen_rd[0].rd_data_rise_wl_r_reg[0]_0\,
      I1 => \gen_rd[0].rd_data_rise_wl_r_reg[0]_1\,
      I2 => \gen_rd[0].rd_data_rise_wl_r_reg[0]_2\,
      I3 => \gen_rd[0].rd_data_rise_wl_r_reg[0]_3\,
      I4 => \p_0_out_inferred__18/gen_rd[0].rd_data_rise_wl_r[0]_i_2_n_0\,
      O => \p_0_in__0\
    );
\p_0_out_inferred__18/gen_rd[0].rd_data_rise_wl_r[0]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFFE"
    )
        port map (
      I0 => \gen_rd[0].rd_data_rise_wl_r_reg[0]_4\,
      I1 => \gen_rd[0].rd_data_rise_wl_r_reg[0]_5\,
      I2 => \gen_rd[0].rd_data_rise_wl_r_reg[0]_6\,
      I3 => \gen_rd[0].rd_data_rise_wl_r_reg[0]_7\,
      O => \p_0_out_inferred__18/gen_rd[0].rd_data_rise_wl_r[0]_i_2_n_0\
    );
\p_0_out_inferred__19/gen_rd[1].rd_data_rise_wl_r[1]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFFFFE"
    )
        port map (
      I0 => \gen_rd[1].rd_data_rise_wl_r_reg[1]_0\,
      I1 => \gen_rd[1].rd_data_rise_wl_r_reg[1]_1\,
      I2 => \gen_rd[1].rd_data_rise_wl_r_reg[1]_2\,
      I3 => \gen_rd[1].rd_data_rise_wl_r_reg[1]_3\,
      I4 => \p_0_out_inferred__19/gen_rd[1].rd_data_rise_wl_r[1]_i_2_n_0\,
      O => \p_0_out_inferred__19/gen_rd[1].rd_data_rise_wl_r[1]_i_1_n_0\
    );
\p_0_out_inferred__19/gen_rd[1].rd_data_rise_wl_r[1]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFFE"
    )
        port map (
      I0 => \gen_rd[1].rd_data_rise_wl_r_reg[1]_4\,
      I1 => \gen_rd[1].rd_data_rise_wl_r_reg[1]_5\,
      I2 => \gen_rd[1].rd_data_rise_wl_r_reg[1]_6\,
      I3 => \gen_rd[1].rd_data_rise_wl_r_reg[1]_7\,
      O => \p_0_out_inferred__19/gen_rd[1].rd_data_rise_wl_r[1]_i_2_n_0\
    );
\p_0_out_inferred__20/gen_rd[2].rd_data_rise_wl_r[2]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFFFFE"
    )
        port map (
      I0 => \gen_rd[2].rd_data_rise_wl_r_reg[2]_0\,
      I1 => \gen_rd[2].rd_data_rise_wl_r_reg[2]_1\,
      I2 => \gen_rd[2].rd_data_rise_wl_r_reg[2]_2\,
      I3 => \gen_rd[2].rd_data_rise_wl_r_reg[2]_3\,
      I4 => \p_0_out_inferred__20/gen_rd[2].rd_data_rise_wl_r[2]_i_2_n_0\,
      O => \p_0_out_inferred__20/gen_rd[2].rd_data_rise_wl_r[2]_i_1_n_0\
    );
\p_0_out_inferred__20/gen_rd[2].rd_data_rise_wl_r[2]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFFE"
    )
        port map (
      I0 => \gen_rd[2].rd_data_rise_wl_r_reg[2]_4\,
      I1 => \gen_rd[2].rd_data_rise_wl_r_reg[2]_5\,
      I2 => \gen_rd[2].rd_data_rise_wl_r_reg[2]_6\,
      I3 => \gen_rd[2].rd_data_rise_wl_r_reg[2]_7\,
      O => \p_0_out_inferred__20/gen_rd[2].rd_data_rise_wl_r[2]_i_2_n_0\
    );
\p_0_out_inferred__21/gen_rd[3].rd_data_rise_wl_r[3]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFFFFE"
    )
        port map (
      I0 => \gen_rd[3].rd_data_rise_wl_r_reg[3]_0\,
      I1 => \gen_rd[3].rd_data_rise_wl_r_reg[3]_1\,
      I2 => \gen_rd[3].rd_data_rise_wl_r_reg[3]_2\,
      I3 => \gen_rd[3].rd_data_rise_wl_r_reg[3]_3\,
      I4 => \p_0_out_inferred__21/gen_rd[3].rd_data_rise_wl_r[3]_i_2_n_0\,
      O => \p_0_out_inferred__21/gen_rd[3].rd_data_rise_wl_r[3]_i_1_n_0\
    );
\p_0_out_inferred__21/gen_rd[3].rd_data_rise_wl_r[3]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFFE"
    )
        port map (
      I0 => \gen_rd[3].rd_data_rise_wl_r_reg[3]_4\,
      I1 => \gen_rd[3].rd_data_rise_wl_r_reg[3]_5\,
      I2 => \gen_rd[3].rd_data_rise_wl_r_reg[3]_6\,
      I3 => \gen_rd[3].rd_data_rise_wl_r_reg[3]_7\,
      O => \p_0_out_inferred__21/gen_rd[3].rd_data_rise_wl_r[3]_i_2_n_0\
    );
\p_0_out_inferred__22/gen_rd[4].rd_data_rise_wl_r[4]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFFFFE"
    )
        port map (
      I0 => \gen_rd[4].rd_data_rise_wl_r_reg[4]_0\,
      I1 => \gen_rd[4].rd_data_rise_wl_r_reg[4]_1\,
      I2 => \gen_rd[4].rd_data_rise_wl_r_reg[4]_2\,
      I3 => \gen_rd[4].rd_data_rise_wl_r_reg[4]_3\,
      I4 => \p_0_out_inferred__22/gen_rd[4].rd_data_rise_wl_r[4]_i_2_n_0\,
      O => \p_0_out_inferred__22/gen_rd[4].rd_data_rise_wl_r[4]_i_1_n_0\
    );
\p_0_out_inferred__22/gen_rd[4].rd_data_rise_wl_r[4]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFFE"
    )
        port map (
      I0 => \gen_rd[4].rd_data_rise_wl_r_reg[4]_4\,
      I1 => \gen_rd[4].rd_data_rise_wl_r_reg[4]_5\,
      I2 => \gen_rd[4].rd_data_rise_wl_r_reg[4]_6\,
      I3 => \gen_rd[4].rd_data_rise_wl_r_reg[4]_7\,
      O => \p_0_out_inferred__22/gen_rd[4].rd_data_rise_wl_r[4]_i_2_n_0\
    );
\p_0_out_inferred__23/gen_rd[5].rd_data_rise_wl_r[5]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFFFFE"
    )
        port map (
      I0 => \gen_rd[5].rd_data_rise_wl_r_reg[5]_0\,
      I1 => \gen_rd[5].rd_data_rise_wl_r_reg[5]_1\,
      I2 => \gen_rd[5].rd_data_rise_wl_r_reg[5]_2\,
      I3 => \gen_rd[5].rd_data_rise_wl_r_reg[5]_3\,
      I4 => \p_0_out_inferred__23/gen_rd[5].rd_data_rise_wl_r[5]_i_2_n_0\,
      O => \p_0_out_inferred__23/gen_rd[5].rd_data_rise_wl_r[5]_i_1_n_0\
    );
\p_0_out_inferred__23/gen_rd[5].rd_data_rise_wl_r[5]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFFE"
    )
        port map (
      I0 => \gen_rd[5].rd_data_rise_wl_r_reg[5]_4\,
      I1 => \gen_rd[5].rd_data_rise_wl_r_reg[5]_5\,
      I2 => \gen_rd[5].rd_data_rise_wl_r_reg[5]_6\,
      I3 => \gen_rd[5].rd_data_rise_wl_r_reg[5]_7\,
      O => \p_0_out_inferred__23/gen_rd[5].rd_data_rise_wl_r[5]_i_2_n_0\
    );
\p_0_out_inferred__24/gen_rd[6].rd_data_rise_wl_r[6]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFFFFE"
    )
        port map (
      I0 => \gen_rd[6].rd_data_rise_wl_r_reg[6]_0\,
      I1 => \gen_rd[6].rd_data_rise_wl_r_reg[6]_1\,
      I2 => \gen_rd[6].rd_data_rise_wl_r_reg[6]_2\,
      I3 => \gen_rd[6].rd_data_rise_wl_r_reg[6]_3\,
      I4 => \p_0_out_inferred__24/gen_rd[6].rd_data_rise_wl_r[6]_i_2_n_0\,
      O => \p_0_out_inferred__24/gen_rd[6].rd_data_rise_wl_r[6]_i_1_n_0\
    );
\p_0_out_inferred__24/gen_rd[6].rd_data_rise_wl_r[6]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFFE"
    )
        port map (
      I0 => \gen_rd[6].rd_data_rise_wl_r_reg[6]_4\,
      I1 => \gen_rd[6].rd_data_rise_wl_r_reg[6]_5\,
      I2 => \gen_rd[6].rd_data_rise_wl_r_reg[6]_6\,
      I3 => \gen_rd[6].rd_data_rise_wl_r_reg[6]_7\,
      O => \p_0_out_inferred__24/gen_rd[6].rd_data_rise_wl_r[6]_i_2_n_0\
    );
\p_0_out_inferred__25/gen_rd[7].rd_data_rise_wl_r[7]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFFFFE"
    )
        port map (
      I0 => \gen_rd[7].rd_data_rise_wl_r_reg[7]_0\,
      I1 => \gen_rd[7].rd_data_rise_wl_r_reg[7]_1\,
      I2 => \gen_rd[7].rd_data_rise_wl_r_reg[7]_2\,
      I3 => \gen_rd[7].rd_data_rise_wl_r_reg[7]_3\,
      I4 => \p_0_out_inferred__25/gen_rd[7].rd_data_rise_wl_r[7]_i_2_n_0\,
      O => \p_0_out_inferred__25/gen_rd[7].rd_data_rise_wl_r[7]_i_1_n_0\
    );
\p_0_out_inferred__25/gen_rd[7].rd_data_rise_wl_r[7]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFFE"
    )
        port map (
      I0 => \gen_rd[7].rd_data_rise_wl_r_reg[7]_4\,
      I1 => \gen_rd[7].rd_data_rise_wl_r_reg[7]_5\,
      I2 => \gen_rd[7].rd_data_rise_wl_r_reg[7]_6\,
      I3 => \gen_rd[7].rd_data_rise_wl_r_reg[7]_7\,
      O => \p_0_out_inferred__25/gen_rd[7].rd_data_rise_wl_r[7]_i_2_n_0\
    );
phaser_out_i_1: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000F010"
    )
        port map (
      I0 => phaser_out,
      I1 => phaser_out_0,
      I2 => po_stg2_cincdec(2),
      I3 => calib_in_common,
      I4 => phaser_out_1(0),
      O => \calib_sel_reg[1]_0\
    );
\phaser_out_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000CC40"
    )
        port map (
      I0 => phaser_out,
      I1 => po_stg2_cincdec(2),
      I2 => phaser_out_0,
      I3 => calib_in_common,
      I4 => phaser_out_1(0),
      O => \calib_sel_reg[1]_1\
    );
\phaser_out_i_1__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000AA80"
    )
        port map (
      I0 => po_stg2_cincdec(2),
      I1 => phaser_out_0,
      I2 => phaser_out,
      I3 => calib_in_common,
      I4 => phaser_out_1(0),
      O => dqs_wl_po_stg2_c_incdec_reg_0
    );
\phaser_out_i_1__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000CC08"
    )
        port map (
      I0 => phaser_out,
      I1 => po_stg2_cincdec(2),
      I2 => phaser_out_0,
      I3 => calib_in_common,
      I4 => phaser_out_1(0),
      O => \calib_sel_reg[1]_2\
    );
\phaser_out_i_1__3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000F010"
    )
        port map (
      I0 => phaser_out,
      I1 => phaser_out_0,
      I2 => po_stg2_cincdec(2),
      I3 => calib_in_common,
      I4 => phaser_out_1(2),
      O => \calib_sel_reg[1]_6\
    );
\phaser_out_i_1__4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000CC40"
    )
        port map (
      I0 => phaser_out,
      I1 => po_stg2_cincdec(2),
      I2 => phaser_out_0,
      I3 => calib_in_common,
      I4 => phaser_out_1(2),
      O => \calib_sel_reg[1]_7\
    );
\phaser_out_i_1__5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000AA80"
    )
        port map (
      I0 => po_stg2_cincdec(2),
      I1 => phaser_out_0,
      I2 => phaser_out,
      I3 => calib_in_common,
      I4 => phaser_out_1(2),
      O => dqs_wl_po_stg2_c_incdec_reg_1
    );
\phaser_out_i_1__6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000CC08"
    )
        port map (
      I0 => phaser_out,
      I1 => po_stg2_cincdec(2),
      I2 => phaser_out_0,
      I3 => calib_in_common,
      I4 => phaser_out_1(2),
      O => \calib_sel_reg[1]_8\
    );
\phaser_out_i_1__7\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00001000"
    )
        port map (
      I0 => calib_in_common,
      I1 => phaser_out_0,
      I2 => po_stg2_cincdec(2),
      I3 => phaser_out,
      I4 => phaser_out_1(1),
      O => C_po_coarse_enable26_out
    );
\phaser_out_i_1__8\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000040"
    )
        port map (
      I0 => calib_in_common,
      I1 => phaser_out_0,
      I2 => po_stg2_cincdec(2),
      I3 => phaser_out,
      I4 => phaser_out_1(1),
      O => \gen_byte_sel_div2.calib_in_common_reg\
    );
\phaser_out_i_1__9\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00004000"
    )
        port map (
      I0 => calib_in_common,
      I1 => phaser_out,
      I2 => phaser_out_0,
      I3 => po_stg2_cincdec(2),
      I4 => phaser_out_1(1),
      O => \gen_byte_sel_div2.calib_in_common_reg_0\
    );
phaser_out_i_2: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000F010"
    )
        port map (
      I0 => phaser_out,
      I1 => phaser_out_0,
      I2 => po_enstg2_f(0),
      I3 => calib_in_common,
      I4 => phaser_out_1(0),
      O => \calib_sel_reg[1]\
    );
\phaser_out_i_2__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000CC40"
    )
        port map (
      I0 => phaser_out,
      I1 => po_enstg2_f(0),
      I2 => phaser_out_0,
      I3 => calib_in_common,
      I4 => phaser_out_1(0),
      O => \calib_sel_reg[1]_3\
    );
\phaser_out_i_2__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000CC08"
    )
        port map (
      I0 => phaser_out,
      I1 => po_enstg2_f(0),
      I2 => phaser_out_0,
      I3 => calib_in_common,
      I4 => phaser_out_1(0),
      O => \calib_sel_reg[1]_4\
    );
\phaser_out_i_2__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000AA80"
    )
        port map (
      I0 => po_enstg2_f(0),
      I1 => phaser_out_0,
      I2 => phaser_out,
      I3 => calib_in_common,
      I4 => phaser_out_1(0),
      O => \calib_sel_reg[0]\
    );
\phaser_out_i_2__3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000F010"
    )
        port map (
      I0 => phaser_out,
      I1 => phaser_out_0,
      I2 => po_enstg2_f(0),
      I3 => calib_in_common,
      I4 => phaser_out_1(2),
      O => \calib_sel_reg[1]_5\
    );
\phaser_out_i_2__4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000CC40"
    )
        port map (
      I0 => phaser_out,
      I1 => po_enstg2_f(0),
      I2 => phaser_out_0,
      I3 => calib_in_common,
      I4 => phaser_out_1(2),
      O => \calib_sel_reg[1]_9\
    );
\phaser_out_i_2__5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000CC08"
    )
        port map (
      I0 => phaser_out,
      I1 => po_enstg2_f(0),
      I2 => phaser_out_0,
      I3 => calib_in_common,
      I4 => phaser_out_1(2),
      O => \calib_sel_reg[1]_10\
    );
\phaser_out_i_2__6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000AA80"
    )
        port map (
      I0 => po_enstg2_f(0),
      I1 => phaser_out_0,
      I2 => phaser_out,
      I3 => calib_in_common,
      I4 => phaser_out_1(2),
      O => \calib_sel_reg[0]_0\
    );
phaser_out_i_3: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00001000"
    )
        port map (
      I0 => calib_in_common,
      I1 => phaser_out_0,
      I2 => po_enstg2_f(0),
      I3 => phaser_out,
      I4 => phaser_out_1(1),
      O => C_po_fine_enable23_out
    );
\phaser_out_i_3__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000040"
    )
        port map (
      I0 => calib_in_common,
      I1 => phaser_out_0,
      I2 => po_enstg2_f(0),
      I3 => phaser_out,
      I4 => phaser_out_1(1),
      O => \gen_byte_sel_div2.calib_in_common_reg_1\
    );
\phaser_out_i_3__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00004000"
    )
        port map (
      I0 => calib_in_common,
      I1 => phaser_out,
      I2 => phaser_out_0,
      I3 => po_enstg2_f(0),
      I4 => phaser_out_1(1),
      O => \gen_byte_sel_div2.calib_in_common_reg_2\
    );
\phaser_out_i_3__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000EEEE000E"
    )
        port map (
      I0 => dqs_po_stg2_f_incdec,
      I1 => ck_po_stg2_f_indec,
      I2 => phaser_out,
      I3 => phaser_out_0,
      I4 => calib_in_common,
      I5 => phaser_out_1(0),
      O => dqs_po_stg2_f_incdec_reg_0
    );
\phaser_out_i_3__3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000EEEE0E00"
    )
        port map (
      I0 => dqs_po_stg2_f_incdec,
      I1 => ck_po_stg2_f_indec,
      I2 => phaser_out,
      I3 => phaser_out_0,
      I4 => calib_in_common,
      I5 => phaser_out_1(0),
      O => dqs_po_stg2_f_incdec_reg_1
    );
\phaser_out_i_3__4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000EEEE00E0"
    )
        port map (
      I0 => dqs_po_stg2_f_incdec,
      I1 => ck_po_stg2_f_indec,
      I2 => phaser_out,
      I3 => phaser_out_0,
      I4 => calib_in_common,
      I5 => phaser_out_1(0),
      O => dqs_po_stg2_f_incdec_reg_2
    );
\phaser_out_i_3__5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000EEEEE000"
    )
        port map (
      I0 => dqs_po_stg2_f_incdec,
      I1 => ck_po_stg2_f_indec,
      I2 => phaser_out_0,
      I3 => phaser_out,
      I4 => calib_in_common,
      I5 => phaser_out_1(0),
      O => dqs_po_stg2_f_incdec_reg_3
    );
\phaser_out_i_3__6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000EEEE000E"
    )
        port map (
      I0 => dqs_po_stg2_f_incdec,
      I1 => ck_po_stg2_f_indec,
      I2 => phaser_out,
      I3 => phaser_out_0,
      I4 => calib_in_common,
      I5 => phaser_out_1(2),
      O => dqs_po_stg2_f_incdec_reg_4
    );
\phaser_out_i_3__7\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000EEEE0E00"
    )
        port map (
      I0 => dqs_po_stg2_f_incdec,
      I1 => ck_po_stg2_f_indec,
      I2 => phaser_out,
      I3 => phaser_out_0,
      I4 => calib_in_common,
      I5 => phaser_out_1(2),
      O => dqs_po_stg2_f_incdec_reg_5
    );
\phaser_out_i_3__8\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000EEEE00E0"
    )
        port map (
      I0 => dqs_po_stg2_f_incdec,
      I1 => ck_po_stg2_f_indec,
      I2 => phaser_out,
      I3 => phaser_out_0,
      I4 => calib_in_common,
      I5 => phaser_out_1(2),
      O => dqs_po_stg2_f_incdec_reg_6
    );
\phaser_out_i_3__9\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000EEEEE000"
    )
        port map (
      I0 => dqs_po_stg2_f_incdec,
      I1 => ck_po_stg2_f_indec,
      I2 => phaser_out_0,
      I3 => phaser_out,
      I4 => calib_in_common,
      I5 => phaser_out_1(2),
      O => dqs_po_stg2_f_incdec_reg_7
    );
phaser_out_i_4: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000000E0000"
    )
        port map (
      I0 => dqs_po_stg2_f_incdec,
      I1 => ck_po_stg2_f_indec,
      I2 => calib_in_common,
      I3 => phaser_out_0,
      I4 => phaser_out,
      I5 => phaser_out_1(1),
      O => C_po_fine_inc29_out
    );
\phaser_out_i_4__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000000E00"
    )
        port map (
      I0 => dqs_po_stg2_f_incdec,
      I1 => ck_po_stg2_f_indec,
      I2 => calib_in_common,
      I3 => phaser_out_0,
      I4 => phaser_out,
      I5 => phaser_out_1(1),
      O => dqs_po_stg2_f_incdec_reg_8
    );
\phaser_out_i_4__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"000000000E000000"
    )
        port map (
      I0 => dqs_po_stg2_f_incdec,
      I1 => ck_po_stg2_f_indec,
      I2 => calib_in_common,
      I3 => phaser_out,
      I4 => phaser_out_0,
      I5 => phaser_out_1(1),
      O => dqs_po_stg2_f_incdec_reg_9
    );
phy_ctl_ready_r4_reg_srl4: unisim.vcomponents.SRL16E
     port map (
      A0 => '1',
      A1 => '1',
      A2 => '0',
      A3 => '0',
      CE => '1',
      CLK => \dqs_count_r_reg[2]_rep__0_1\,
      D => Q(0),
      Q => phy_ctl_ready_r4_reg_srl4_n_0
    );
phy_ctl_ready_r5_reg: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => '1',
      D => phy_ctl_ready_r4_reg_srl4_n_0,
      Q => phy_ctl_ready_r5,
      R => '0'
    );
phy_ctl_ready_r6_reg: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => '1',
      D => phy_ctl_ready_r5,
      Q => phy_ctl_ready_r6_reg_n_0,
      R => '0'
    );
po_cnt_dec_i_1: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => po_cnt_dec_i_2_n_0,
      I1 => \po_rdval_cnt[8]_i_3_n_0\,
      O => po_cnt_dec_i_1_n_0
    );
po_cnt_dec_i_2: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000200000000"
    )
        port map (
      I0 => wait_cnt_reg(0),
      I1 => wait_cnt_reg(1),
      I2 => \single_rank.done_dqs_dec_reg_0\,
      I3 => wait_cnt_reg(2),
      I4 => wait_cnt_reg(3),
      I5 => phy_ctl_ready_r6_reg_n_0,
      O => po_cnt_dec_i_2_n_0
    );
po_cnt_dec_reg: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => '1',
      D => po_cnt_dec_i_1_n_0,
      Q => \^po_cnt_dec_reg_0\,
      R => '0'
    );
po_dec_done_i_1: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFEA"
    )
        port map (
      I0 => po_dec_done_i_2_n_0,
      I1 => phy_ctl_ready_r6_reg_n_0,
      I2 => \po_rdval_cnt[8]_i_3_n_0\,
      I3 => po_dec_done,
      O => po_dec_done_i_1_n_0
    );
po_dec_done_i_2: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000080"
    )
        port map (
      I0 => \po_rdval_cnt[8]_i_6_n_0\,
      I1 => \^po_cnt_dec_reg_0\,
      I2 => po_rdval_cnt(0),
      I3 => po_rdval_cnt(5),
      I4 => po_rdval_cnt(6),
      O => po_dec_done_i_2_n_0
    );
po_dec_done_reg: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => '1',
      D => po_dec_done_i_1_n_0,
      Q => po_dec_done,
      R => \wl_dqs_tap_count_r_reg[0][5][5]_0\
    );
\po_rdval_cnt[0]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0303AA03"
    )
        port map (
      I0 => \po_rdval_cnt_reg[0]_0\,
      I1 => po_rdval_cnt(0),
      I2 => \po_rdval_cnt[8]_i_3_n_0\,
      I3 => phy_ctl_ready_r5,
      I4 => phy_ctl_ready_r6_reg_n_0,
      O => \po_rdval_cnt[0]_i_1_n_0\
    );
\po_rdval_cnt[1]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"08FB0808080808FB"
    )
        port map (
      I0 => \po_rdval_cnt_reg[1]_0\,
      I1 => phy_ctl_ready_r5,
      I2 => phy_ctl_ready_r6_reg_n_0,
      I3 => \po_rdval_cnt[8]_i_3_n_0\,
      I4 => po_rdval_cnt(0),
      I5 => po_rdval_cnt(1),
      O => \po_rdval_cnt[1]_i_1_n_0\
    );
\po_rdval_cnt[2]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"88888888BBB8888B"
    )
        port map (
      I0 => \po_rdval_cnt_reg[2]_0\,
      I1 => \po_rdval_cnt[6]_i_3_n_0\,
      I2 => po_rdval_cnt(1),
      I3 => po_rdval_cnt(0),
      I4 => po_rdval_cnt(2),
      I5 => \po_rdval_cnt[8]_i_3_n_0\,
      O => \po_rdval_cnt[2]_i_1_n_0\
    );
\po_rdval_cnt[3]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"88888888BB8B88B8"
    )
        port map (
      I0 => \po_rdval_cnt_reg[3]_0\,
      I1 => \po_rdval_cnt[6]_i_3_n_0\,
      I2 => \po_rdval_cnt[3]_i_3_n_0\,
      I3 => po_rdval_cnt(2),
      I4 => po_rdval_cnt(3),
      I5 => \po_rdval_cnt[8]_i_3_n_0\,
      O => \po_rdval_cnt[3]_i_1_n_0\
    );
\po_rdval_cnt[3]_i_3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => po_rdval_cnt(1),
      I1 => po_rdval_cnt(0),
      O => \po_rdval_cnt[3]_i_3_n_0\
    );
\po_rdval_cnt[4]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"08080808FB0808FB"
    )
        port map (
      I0 => \po_rdval_cnt_reg[4]_0\,
      I1 => phy_ctl_ready_r5,
      I2 => phy_ctl_ready_r6_reg_n_0,
      I3 => \po_rdval_cnt[4]_i_3_n_0\,
      I4 => po_rdval_cnt(4),
      I5 => \po_rdval_cnt[8]_i_3_n_0\,
      O => \po_rdval_cnt[4]_i_1_n_0\
    );
\po_rdval_cnt[4]_i_3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFFE"
    )
        port map (
      I0 => po_rdval_cnt(3),
      I1 => po_rdval_cnt(2),
      I2 => po_rdval_cnt(0),
      I3 => po_rdval_cnt(1),
      O => \po_rdval_cnt[4]_i_3_n_0\
    );
\po_rdval_cnt[5]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0808080808FBFB08"
    )
        port map (
      I0 => \po_rdval_cnt_reg[5]_0\,
      I1 => phy_ctl_ready_r5,
      I2 => phy_ctl_ready_r6_reg_n_0,
      I3 => \po_rdval_cnt[6]_i_4_n_0\,
      I4 => po_rdval_cnt(5),
      I5 => \po_rdval_cnt[8]_i_3_n_0\,
      O => \po_rdval_cnt[5]_i_1_n_0\
    );
\po_rdval_cnt[6]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"88888888BB8B88B8"
    )
        port map (
      I0 => \po_rdval_cnt_reg[6]_0\,
      I1 => \po_rdval_cnt[6]_i_3_n_0\,
      I2 => \po_rdval_cnt[6]_i_4_n_0\,
      I3 => po_rdval_cnt(5),
      I4 => po_rdval_cnt(6),
      I5 => \po_rdval_cnt[8]_i_3_n_0\,
      O => \po_rdval_cnt[6]_i_1_n_0\
    );
\po_rdval_cnt[6]_i_3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => phy_ctl_ready_r5,
      I1 => phy_ctl_ready_r6_reg_n_0,
      O => \po_rdval_cnt[6]_i_3_n_0\
    );
\po_rdval_cnt[6]_i_4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000001"
    )
        port map (
      I0 => po_rdval_cnt(4),
      I1 => po_rdval_cnt(1),
      I2 => po_rdval_cnt(0),
      I3 => po_rdval_cnt(2),
      I4 => po_rdval_cnt(3),
      O => \po_rdval_cnt[6]_i_4_n_0\
    );
\po_rdval_cnt[7]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"08FBFB08"
    )
        port map (
      I0 => \po_rdval_cnt_reg[7]_0\,
      I1 => phy_ctl_ready_r5,
      I2 => phy_ctl_ready_r6_reg_n_0,
      I3 => po_rdval_cnt(7),
      I4 => \po_rdval_cnt[8]_i_5_n_0\,
      O => \po_rdval_cnt[7]_i_1_n_0\
    );
\po_rdval_cnt[8]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFF4"
    )
        port map (
      I0 => phy_ctl_ready_r6_reg_n_0,
      I1 => phy_ctl_ready_r5,
      I2 => \po_rdval_cnt[8]_i_3_n_0\,
      I3 => \^po_cnt_dec_reg_0\,
      O => \po_rdval_cnt[8]_i_1_n_0\
    );
\po_rdval_cnt[8]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FB080808FB08FB08"
    )
        port map (
      I0 => \po_rdval_cnt_reg[8]_0\,
      I1 => phy_ctl_ready_r5,
      I2 => phy_ctl_ready_r6_reg_n_0,
      I3 => po_rdval_cnt(8),
      I4 => po_rdval_cnt(7),
      I5 => \po_rdval_cnt[8]_i_5_n_0\,
      O => \po_rdval_cnt[8]_i_2_n_0\
    );
\po_rdval_cnt[8]_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000002"
    )
        port map (
      I0 => \po_rdval_cnt[6]_i_4_n_0\,
      I1 => po_rdval_cnt(8),
      I2 => po_rdval_cnt(7),
      I3 => po_rdval_cnt(5),
      I4 => po_rdval_cnt(6),
      O => \po_rdval_cnt[8]_i_3_n_0\
    );
\po_rdval_cnt[8]_i_5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"000000B0"
    )
        port map (
      I0 => po_rdval_cnt(0),
      I1 => \po_rdval_cnt[8]_i_6_n_0\,
      I2 => \po_rdval_cnt[6]_i_4_n_0\,
      I3 => po_rdval_cnt(5),
      I4 => po_rdval_cnt(6),
      O => \po_rdval_cnt[8]_i_5_n_0\
    );
\po_rdval_cnt[8]_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000000001"
    )
        port map (
      I0 => po_rdval_cnt(4),
      I1 => po_rdval_cnt(2),
      I2 => po_rdval_cnt(3),
      I3 => po_rdval_cnt(8),
      I4 => po_rdval_cnt(7),
      I5 => po_rdval_cnt(1),
      O => \po_rdval_cnt[8]_i_6_n_0\
    );
\po_rdval_cnt_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => \po_rdval_cnt[8]_i_1_n_0\,
      D => \po_rdval_cnt[0]_i_1_n_0\,
      Q => po_rdval_cnt(0),
      R => \corse_inc_reg[6][2]_0\(0)
    );
\po_rdval_cnt_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => \po_rdval_cnt[8]_i_1_n_0\,
      D => \po_rdval_cnt[1]_i_1_n_0\,
      Q => po_rdval_cnt(1),
      R => \corse_inc_reg[6][2]_0\(0)
    );
\po_rdval_cnt_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => \po_rdval_cnt[8]_i_1_n_0\,
      D => \po_rdval_cnt[2]_i_1_n_0\,
      Q => po_rdval_cnt(2),
      R => \corse_inc_reg[6][2]_0\(0)
    );
\po_rdval_cnt_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => \po_rdval_cnt[8]_i_1_n_0\,
      D => \po_rdval_cnt[3]_i_1_n_0\,
      Q => po_rdval_cnt(3),
      R => \corse_inc_reg[6][2]_0\(0)
    );
\po_rdval_cnt_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => \po_rdval_cnt[8]_i_1_n_0\,
      D => \po_rdval_cnt[4]_i_1_n_0\,
      Q => po_rdval_cnt(4),
      R => \corse_inc_reg[6][2]_0\(0)
    );
\po_rdval_cnt_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => \po_rdval_cnt[8]_i_1_n_0\,
      D => \po_rdval_cnt[5]_i_1_n_0\,
      Q => po_rdval_cnt(5),
      R => \corse_inc_reg[6][2]_0\(0)
    );
\po_rdval_cnt_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => \po_rdval_cnt[8]_i_1_n_0\,
      D => \po_rdval_cnt[6]_i_1_n_0\,
      Q => po_rdval_cnt(6),
      R => \corse_inc_reg[6][2]_0\(0)
    );
\po_rdval_cnt_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => \po_rdval_cnt[8]_i_1_n_0\,
      D => \po_rdval_cnt[7]_i_1_n_0\,
      Q => po_rdval_cnt(7),
      R => \corse_inc_reg[6][2]_0\(0)
    );
\po_rdval_cnt_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => \po_rdval_cnt[8]_i_1_n_0\,
      D => \po_rdval_cnt[8]_i_2_n_0\,
      Q => po_rdval_cnt(8),
      R => \corse_inc_reg[6][2]_0\(0)
    );
\rank_cnt_r[0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FF3FFFFF00800000"
    )
        port map (
      I0 => \rank_cnt_r_reg_n_0_[1]\,
      I1 => \wl_state_r__0\(0),
      I2 => \dqs_count_r[3]_i_4_n_0\,
      I3 => p_0_in,
      I4 => \rank_cnt_r[1]_i_2_n_0\,
      I5 => \rank_cnt_r_reg_n_0_[0]\,
      O => \rank_cnt_r[0]_i_1_n_0\
    );
\rank_cnt_r[1]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FF7FFFFF00800000"
    )
        port map (
      I0 => \rank_cnt_r_reg_n_0_[0]\,
      I1 => \wl_state_r__0\(0),
      I2 => \dqs_count_r[3]_i_4_n_0\,
      I3 => p_0_in,
      I4 => \rank_cnt_r[1]_i_2_n_0\,
      I5 => \rank_cnt_r_reg_n_0_[1]\,
      O => \rank_cnt_r[1]_i_1_n_0\
    );
\rank_cnt_r[1]_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \wl_state_r__0\(1),
      I1 => \^fsm_sequential_wl_state_r_reg[4]_0\(1),
      O => \rank_cnt_r[1]_i_2_n_0\
    );
\rank_cnt_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => '1',
      D => \rank_cnt_r[0]_i_1_n_0\,
      Q => \rank_cnt_r_reg_n_0_[0]\,
      R => \fine_inc_reg[6][3]_0\(0)
    );
\rank_cnt_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => '1',
      D => \rank_cnt_r[1]_i_1_n_0\,
      Q => \rank_cnt_r_reg_n_0_[1]\,
      R => \fine_inc_reg[6][3]_0\(0)
    );
\rd_data_edge_detect_r[0]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0020"
    )
        port map (
      I0 => \rd_data_edge_detect_r[7]_i_6_n_0\,
      I1 => \rd_data_previous_r_reg_n_0_[0]\,
      I2 => \gen_rd[0].rd_data_rise_wl_r_reg_n_0_[0]\,
      I3 => \rd_data_edge_detect_r_reg[7]_i_5_n_0\,
      O => \rd_data_edge_detect_r[0]_i_1_n_0\
    );
\rd_data_edge_detect_r[1]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0020"
    )
        port map (
      I0 => \rd_data_edge_detect_r[7]_i_6_n_0\,
      I1 => \rd_data_previous_r_reg_n_0_[1]\,
      I2 => \gen_rd[1].rd_data_rise_wl_r_reg_n_0_[1]\,
      I3 => \rd_data_edge_detect_r_reg[7]_i_5_n_0\,
      O => \rd_data_edge_detect_r[1]_i_1_n_0\
    );
\rd_data_edge_detect_r[2]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0020"
    )
        port map (
      I0 => \rd_data_edge_detect_r[7]_i_6_n_0\,
      I1 => \rd_data_previous_r_reg_n_0_[2]\,
      I2 => \gen_rd[2].rd_data_rise_wl_r_reg_n_0_[2]\,
      I3 => \rd_data_edge_detect_r_reg[7]_i_5_n_0\,
      O => \rd_data_edge_detect_r[2]_i_1_n_0\
    );
\rd_data_edge_detect_r[3]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0020"
    )
        port map (
      I0 => \rd_data_edge_detect_r[7]_i_6_n_0\,
      I1 => \rd_data_previous_r_reg_n_0_[3]\,
      I2 => \gen_rd[3].rd_data_rise_wl_r_reg_n_0_[3]\,
      I3 => \rd_data_edge_detect_r_reg[7]_i_5_n_0\,
      O => \rd_data_edge_detect_r[3]_i_1_n_0\
    );
\rd_data_edge_detect_r[4]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0020"
    )
        port map (
      I0 => \rd_data_edge_detect_r[7]_i_6_n_0\,
      I1 => \rd_data_previous_r_reg_n_0_[4]\,
      I2 => \gen_rd[4].rd_data_rise_wl_r_reg_n_0_[4]\,
      I3 => \rd_data_edge_detect_r_reg[7]_i_5_n_0\,
      O => \rd_data_edge_detect_r[4]_i_1_n_0\
    );
\rd_data_edge_detect_r[5]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0020"
    )
        port map (
      I0 => \rd_data_edge_detect_r[7]_i_6_n_0\,
      I1 => \rd_data_previous_r_reg_n_0_[5]\,
      I2 => \gen_rd[5].rd_data_rise_wl_r_reg_n_0_[5]\,
      I3 => \rd_data_edge_detect_r_reg[7]_i_5_n_0\,
      O => \rd_data_edge_detect_r[5]_i_1_n_0\
    );
\rd_data_edge_detect_r[6]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0020"
    )
        port map (
      I0 => \rd_data_edge_detect_r[7]_i_6_n_0\,
      I1 => \rd_data_previous_r_reg_n_0_[6]\,
      I2 => \gen_rd[6].rd_data_rise_wl_r_reg_n_0_[6]\,
      I3 => \rd_data_edge_detect_r_reg[7]_i_5_n_0\,
      O => \rd_data_edge_detect_r[6]_i_1_n_0\
    );
\rd_data_edge_detect_r[7]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFFFFE"
    )
        port map (
      I0 => \rd_data_edge_detect_r[7]_i_4_n_0\,
      I1 => flag_init,
      I2 => inhibit_edge_detect_r_reg_n_0,
      I3 => \single_rank.done_dqs_dec_reg_0\,
      I4 => flag_ck_negedge_reg_n_0,
      O => rd_data_edge_detect_r0
    );
\rd_data_edge_detect_r[7]_i_10\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \rd_data_previous_r_reg_n_0_[3]\,
      I1 => \rd_data_previous_r_reg_n_0_[2]\,
      I2 => dqs_count_r(1),
      I3 => \rd_data_previous_r_reg_n_0_[1]\,
      I4 => dqs_count_r(0),
      I5 => \rd_data_previous_r_reg_n_0_[0]\,
      O => \rd_data_edge_detect_r[7]_i_10_n_0\
    );
\rd_data_edge_detect_r[7]_i_11\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \rd_data_previous_r_reg_n_0_[7]\,
      I1 => \rd_data_previous_r_reg_n_0_[6]\,
      I2 => dqs_count_r(1),
      I3 => \rd_data_previous_r_reg_n_0_[5]\,
      I4 => dqs_count_r(0),
      I5 => \rd_data_previous_r_reg_n_0_[4]\,
      O => \rd_data_edge_detect_r[7]_i_11_n_0\
    );
\rd_data_edge_detect_r[7]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"06130411FFFFFFFF"
    )
        port map (
      I0 => \wl_state_r__0\(2),
      I1 => \^fsm_sequential_wl_state_r_reg[4]_0\(0),
      I2 => \^fsm_sequential_wl_state_r_reg[4]_0\(1),
      I3 => \wl_state_r__0\(1),
      I4 => \wl_state_r__0\(0),
      I5 => \rd_data_edge_detect_r_reg[7]_i_5_n_0\,
      O => \rd_data_edge_detect_r[7]_i_2_n_0\
    );
\rd_data_edge_detect_r[7]_i_3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0020"
    )
        port map (
      I0 => \rd_data_edge_detect_r[7]_i_6_n_0\,
      I1 => \rd_data_previous_r_reg_n_0_[7]\,
      I2 => \gen_rd[7].rd_data_rise_wl_r_reg_n_0_[7]\,
      I3 => \rd_data_edge_detect_r_reg[7]_i_5_n_0\,
      O => \rd_data_edge_detect_r[7]_i_3_n_0\
    );
\rd_data_edge_detect_r[7]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000000001"
    )
        port map (
      I0 => \wl_tap_count_r_reg_n_0_[1]\,
      I1 => \wl_tap_count_r_reg_n_0_[0]\,
      I2 => \wl_tap_count_r_reg_n_0_[3]\,
      I3 => \wl_tap_count_r_reg_n_0_[2]\,
      I4 => \wl_tap_count_r_reg_n_0_[5]\,
      I5 => \wl_tap_count_r_reg_n_0_[4]\,
      O => \rd_data_edge_detect_r[7]_i_4_n_0\
    );
\rd_data_edge_detect_r[7]_i_6\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"D555"
    )
        port map (
      I0 => \rd_data_edge_detect_r_reg[7]_i_9_n_0\,
      I1 => \stable_cnt_reg_n_0_[3]\,
      I2 => \stable_cnt_reg_n_0_[1]\,
      I3 => \stable_cnt_reg_n_0_[2]\,
      O => \rd_data_edge_detect_r[7]_i_6_n_0\
    );
\rd_data_edge_detect_r[7]_i_7\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \rd_data_edge_detect_r_reg_n_0_[3]\,
      I1 => \rd_data_edge_detect_r_reg_n_0_[2]\,
      I2 => \^dqs_count_r_reg[1]_rep_0\,
      I3 => \rd_data_edge_detect_r_reg_n_0_[1]\,
      I4 => \^dqs_count_r_reg[0]_rep_0\,
      I5 => \rd_data_edge_detect_r_reg_n_0_[0]\,
      O => \rd_data_edge_detect_r[7]_i_7_n_0\
    );
\rd_data_edge_detect_r[7]_i_8\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \rd_data_edge_detect_r_reg_n_0_[7]\,
      I1 => \rd_data_edge_detect_r_reg_n_0_[6]\,
      I2 => \^dqs_count_r_reg[1]_rep_0\,
      I3 => \rd_data_edge_detect_r_reg_n_0_[5]\,
      I4 => \^dqs_count_r_reg[0]_rep_0\,
      I5 => \rd_data_edge_detect_r_reg_n_0_[4]\,
      O => \rd_data_edge_detect_r[7]_i_8_n_0\
    );
\rd_data_edge_detect_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => \rd_data_edge_detect_r[7]_i_2_n_0\,
      D => \rd_data_edge_detect_r[0]_i_1_n_0\,
      Q => \rd_data_edge_detect_r_reg_n_0_[0]\,
      R => rd_data_edge_detect_r0
    );
\rd_data_edge_detect_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => \rd_data_edge_detect_r[7]_i_2_n_0\,
      D => \rd_data_edge_detect_r[1]_i_1_n_0\,
      Q => \rd_data_edge_detect_r_reg_n_0_[1]\,
      R => rd_data_edge_detect_r0
    );
\rd_data_edge_detect_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => \rd_data_edge_detect_r[7]_i_2_n_0\,
      D => \rd_data_edge_detect_r[2]_i_1_n_0\,
      Q => \rd_data_edge_detect_r_reg_n_0_[2]\,
      R => rd_data_edge_detect_r0
    );
\rd_data_edge_detect_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => \rd_data_edge_detect_r[7]_i_2_n_0\,
      D => \rd_data_edge_detect_r[3]_i_1_n_0\,
      Q => \rd_data_edge_detect_r_reg_n_0_[3]\,
      R => rd_data_edge_detect_r0
    );
\rd_data_edge_detect_r_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => \rd_data_edge_detect_r[7]_i_2_n_0\,
      D => \rd_data_edge_detect_r[4]_i_1_n_0\,
      Q => \rd_data_edge_detect_r_reg_n_0_[4]\,
      R => rd_data_edge_detect_r0
    );
\rd_data_edge_detect_r_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => \rd_data_edge_detect_r[7]_i_2_n_0\,
      D => \rd_data_edge_detect_r[5]_i_1_n_0\,
      Q => \rd_data_edge_detect_r_reg_n_0_[5]\,
      R => rd_data_edge_detect_r0
    );
\rd_data_edge_detect_r_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => \rd_data_edge_detect_r[7]_i_2_n_0\,
      D => \rd_data_edge_detect_r[6]_i_1_n_0\,
      Q => \rd_data_edge_detect_r_reg_n_0_[6]\,
      R => rd_data_edge_detect_r0
    );
\rd_data_edge_detect_r_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => \rd_data_edge_detect_r[7]_i_2_n_0\,
      D => \rd_data_edge_detect_r[7]_i_3_n_0\,
      Q => \rd_data_edge_detect_r_reg_n_0_[7]\,
      R => rd_data_edge_detect_r0
    );
\rd_data_edge_detect_r_reg[7]_i_5\: unisim.vcomponents.MUXF7
     port map (
      I0 => \rd_data_edge_detect_r[7]_i_7_n_0\,
      I1 => \rd_data_edge_detect_r[7]_i_8_n_0\,
      O => \rd_data_edge_detect_r_reg[7]_i_5_n_0\,
      S => dqs_count_r(2)
    );
\rd_data_edge_detect_r_reg[7]_i_9\: unisim.vcomponents.MUXF7
     port map (
      I0 => \rd_data_edge_detect_r[7]_i_10_n_0\,
      I1 => \rd_data_edge_detect_r[7]_i_11_n_0\,
      O => \rd_data_edge_detect_r_reg[7]_i_9_n_0\,
      S => dqs_count_r(2)
    );
\rd_data_previous_r[7]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"555775DD55777577"
    )
        port map (
      I0 => \rd_data_previous_r[7]_i_2_n_0\,
      I1 => \^fsm_sequential_wl_state_r_reg[4]_0\(0),
      I2 => \wl_state_r__0\(0),
      I3 => \wl_state_r__0\(2),
      I4 => \^fsm_sequential_wl_state_r_reg[4]_0\(1),
      I5 => \wl_state_r__0\(1),
      O => rd_data_previous_r0
    );
\rd_data_previous_r[7]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"5555555555555545"
    )
        port map (
      I0 => \rd_data_previous_r[7]_i_3_n_0\,
      I1 => \rd_data_previous_r[7]_i_4_n_0\,
      I2 => \rd_data_previous_r[7]_i_5_n_0\,
      I3 => \wl_state_r__0\(0),
      I4 => \wl_state_r__0\(1),
      I5 => \wl_state_r1_reg_n_0_[1]\,
      O => \rd_data_previous_r[7]_i_2_n_0\
    );
\rd_data_previous_r[7]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000800000000000"
    )
        port map (
      I0 => \wl_state_r__0\(1),
      I1 => \^fsm_sequential_wl_state_r_reg[4]_0\(1),
      I2 => wl_edge_detect_valid_r_reg_n_0,
      I3 => \^fsm_sequential_wl_state_r_reg[4]_0\(0),
      I4 => \wl_state_r__0\(2),
      I5 => \wl_state_r__0\(0),
      O => \rd_data_previous_r[7]_i_3_n_0\
    );
\rd_data_previous_r[7]_i_4\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFEF"
    )
        port map (
      I0 => \wl_state_r1_reg_n_0_[0]\,
      I1 => \wl_state_r1_reg_n_0_[3]\,
      I2 => \wl_state_r1_reg_n_0_[2]\,
      I3 => \wl_state_r1_reg_n_0_[4]\,
      O => \rd_data_previous_r[7]_i_4_n_0\
    );
\rd_data_previous_r[7]_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"08"
    )
        port map (
      I0 => \wl_state_r__0\(2),
      I1 => \^fsm_sequential_wl_state_r_reg[4]_0\(0),
      I2 => \^fsm_sequential_wl_state_r_reg[4]_0\(1),
      O => \rd_data_previous_r[7]_i_5_n_0\
    );
\rd_data_previous_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => rd_data_previous_r0,
      D => \gen_rd[0].rd_data_rise_wl_r_reg_n_0_[0]\,
      Q => \rd_data_previous_r_reg_n_0_[0]\,
      R => '0'
    );
\rd_data_previous_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => rd_data_previous_r0,
      D => \gen_rd[1].rd_data_rise_wl_r_reg_n_0_[1]\,
      Q => \rd_data_previous_r_reg_n_0_[1]\,
      R => '0'
    );
\rd_data_previous_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => rd_data_previous_r0,
      D => \gen_rd[2].rd_data_rise_wl_r_reg_n_0_[2]\,
      Q => \rd_data_previous_r_reg_n_0_[2]\,
      R => '0'
    );
\rd_data_previous_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => rd_data_previous_r0,
      D => \gen_rd[3].rd_data_rise_wl_r_reg_n_0_[3]\,
      Q => \rd_data_previous_r_reg_n_0_[3]\,
      R => '0'
    );
\rd_data_previous_r_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => rd_data_previous_r0,
      D => \gen_rd[4].rd_data_rise_wl_r_reg_n_0_[4]\,
      Q => \rd_data_previous_r_reg_n_0_[4]\,
      R => '0'
    );
\rd_data_previous_r_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => rd_data_previous_r0,
      D => \gen_rd[5].rd_data_rise_wl_r_reg_n_0_[5]\,
      Q => \rd_data_previous_r_reg_n_0_[5]\,
      R => '0'
    );
\rd_data_previous_r_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => rd_data_previous_r0,
      D => \gen_rd[6].rd_data_rise_wl_r_reg_n_0_[6]\,
      Q => \rd_data_previous_r_reg_n_0_[6]\,
      R => '0'
    );
\rd_data_previous_r_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => rd_data_previous_r0,
      D => \gen_rd[7].rd_data_rise_wl_r_reg_n_0_[7]\,
      Q => \rd_data_previous_r_reg_n_0_[7]\,
      R => '0'
    );
\single_rank.done_dqs_dec_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"000000BA"
    )
        port map (
      I0 => \^done_dqs_tap_inc\,
      I1 => wr_level_done_r4,
      I2 => wr_level_done_r3,
      I3 => done_dqs_dec238_out,
      I4 => \single_rank.done_dqs_dec_reg_0\,
      O => \single_rank.done_dqs_dec_i_1_n_0\
    );
\single_rank.done_dqs_dec_reg\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => '1',
      D => \single_rank.done_dqs_dec_i_1_n_0\,
      Q => \^done_dqs_tap_inc\,
      R => '0'
    );
\smallest[0][0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFEFFFF00020000"
    )
        port map (
      I0 => \smallest_reg[0][0]_i_2_n_0\,
      I1 => \^fsm_sequential_wl_state_r_reg[4]_0\(0),
      I2 => \wl_state_r__0\(0),
      I3 => \wl_state_r__0\(1),
      I4 => \wl_state_r__0\(2),
      I5 => \wl_dqs_tap_count_r_reg_n_0_[0][0][0]\,
      O => largest(0)
    );
\smallest[0][0]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \wl_dqs_tap_count_r_reg_n_0_[0][3][0]\,
      I1 => \wl_dqs_tap_count_r_reg_n_0_[0][2][0]\,
      I2 => \^dqs_count_r_reg[1]_rep_0\,
      I3 => \wl_dqs_tap_count_r_reg_n_0_[0][1][0]\,
      I4 => \^dqs_count_r_reg[0]_rep_0\,
      I5 => \wl_dqs_tap_count_r_reg_n_0_[0][0][0]\,
      O => \smallest[0][0]_i_3_n_0\
    );
\smallest[0][0]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \wl_dqs_tap_count_r_reg_n_0_[0][7][0]\,
      I1 => \wl_dqs_tap_count_r_reg_n_0_[0][6][0]\,
      I2 => \^dqs_count_r_reg[1]_rep_0\,
      I3 => \wl_dqs_tap_count_r_reg_n_0_[0][5][0]\,
      I4 => \^dqs_count_r_reg[0]_rep_0\,
      I5 => \wl_dqs_tap_count_r_reg_n_0_[0][4][0]\,
      O => \smallest[0][0]_i_4_n_0\
    );
\smallest[0][1]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFEFFFF00020000"
    )
        port map (
      I0 => \smallest_reg[0][1]_i_2_n_0\,
      I1 => \^fsm_sequential_wl_state_r_reg[4]_0\(0),
      I2 => \wl_state_r__0\(0),
      I3 => \wl_state_r__0\(1),
      I4 => \wl_state_r__0\(2),
      I5 => \wl_dqs_tap_count_r_reg_n_0_[0][0][1]\,
      O => largest(1)
    );
\smallest[0][1]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \wl_dqs_tap_count_r_reg_n_0_[0][3][1]\,
      I1 => \wl_dqs_tap_count_r_reg_n_0_[0][2][1]\,
      I2 => \^dqs_count_r_reg[1]_rep_0\,
      I3 => \wl_dqs_tap_count_r_reg_n_0_[0][1][1]\,
      I4 => \^dqs_count_r_reg[0]_rep_0\,
      I5 => \wl_dqs_tap_count_r_reg_n_0_[0][0][1]\,
      O => \smallest[0][1]_i_3_n_0\
    );
\smallest[0][1]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \wl_dqs_tap_count_r_reg_n_0_[0][7][1]\,
      I1 => \wl_dqs_tap_count_r_reg_n_0_[0][6][1]\,
      I2 => \^dqs_count_r_reg[1]_rep_0\,
      I3 => \wl_dqs_tap_count_r_reg_n_0_[0][5][1]\,
      I4 => \^dqs_count_r_reg[0]_rep_0\,
      I5 => \wl_dqs_tap_count_r_reg_n_0_[0][4][1]\,
      O => \smallest[0][1]_i_4_n_0\
    );
\smallest[0][2]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFEFFFF00020000"
    )
        port map (
      I0 => \smallest_reg[0][2]_i_2_n_0\,
      I1 => \^fsm_sequential_wl_state_r_reg[4]_0\(0),
      I2 => \wl_state_r__0\(0),
      I3 => \wl_state_r__0\(1),
      I4 => \wl_state_r__0\(2),
      I5 => \wl_dqs_tap_count_r_reg_n_0_[0][0][2]\,
      O => largest(2)
    );
\smallest[0][2]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \wl_dqs_tap_count_r_reg_n_0_[0][3][2]\,
      I1 => \wl_dqs_tap_count_r_reg_n_0_[0][2][2]\,
      I2 => \^dqs_count_r_reg[1]_rep_0\,
      I3 => \wl_dqs_tap_count_r_reg_n_0_[0][1][2]\,
      I4 => \^dqs_count_r_reg[0]_rep_0\,
      I5 => \wl_dqs_tap_count_r_reg_n_0_[0][0][2]\,
      O => \smallest[0][2]_i_3_n_0\
    );
\smallest[0][2]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \wl_dqs_tap_count_r_reg_n_0_[0][7][2]\,
      I1 => \wl_dqs_tap_count_r_reg_n_0_[0][6][2]\,
      I2 => \^dqs_count_r_reg[1]_rep_0\,
      I3 => \wl_dqs_tap_count_r_reg_n_0_[0][5][2]\,
      I4 => \^dqs_count_r_reg[0]_rep_0\,
      I5 => \wl_dqs_tap_count_r_reg_n_0_[0][4][2]\,
      O => \smallest[0][2]_i_4_n_0\
    );
\smallest[0][3]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFEFFFF00020000"
    )
        port map (
      I0 => \smallest_reg[0][3]_i_2_n_0\,
      I1 => \^fsm_sequential_wl_state_r_reg[4]_0\(0),
      I2 => \wl_state_r__0\(0),
      I3 => \wl_state_r__0\(1),
      I4 => \wl_state_r__0\(2),
      I5 => \wl_dqs_tap_count_r_reg_n_0_[0][0][3]\,
      O => largest(3)
    );
\smallest[0][3]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \wl_dqs_tap_count_r_reg_n_0_[0][3][3]\,
      I1 => \wl_dqs_tap_count_r_reg_n_0_[0][2][3]\,
      I2 => \^dqs_count_r_reg[1]_rep_0\,
      I3 => \wl_dqs_tap_count_r_reg_n_0_[0][1][3]\,
      I4 => \^dqs_count_r_reg[0]_rep_0\,
      I5 => \wl_dqs_tap_count_r_reg_n_0_[0][0][3]\,
      O => \smallest[0][3]_i_3_n_0\
    );
\smallest[0][3]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \wl_dqs_tap_count_r_reg_n_0_[0][7][3]\,
      I1 => \wl_dqs_tap_count_r_reg_n_0_[0][6][3]\,
      I2 => \^dqs_count_r_reg[1]_rep_0\,
      I3 => \wl_dqs_tap_count_r_reg_n_0_[0][5][3]\,
      I4 => \^dqs_count_r_reg[0]_rep_0\,
      I5 => \wl_dqs_tap_count_r_reg_n_0_[0][4][3]\,
      O => \smallest[0][3]_i_4_n_0\
    );
\smallest[0][4]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFEFFFF00020000"
    )
        port map (
      I0 => \smallest_reg[0][4]_i_2_n_0\,
      I1 => \^fsm_sequential_wl_state_r_reg[4]_0\(0),
      I2 => \wl_state_r__0\(0),
      I3 => \wl_state_r__0\(1),
      I4 => \wl_state_r__0\(2),
      I5 => \wl_dqs_tap_count_r_reg_n_0_[0][0][4]\,
      O => largest(4)
    );
\smallest[0][4]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \wl_dqs_tap_count_r_reg_n_0_[0][3][4]\,
      I1 => \wl_dqs_tap_count_r_reg_n_0_[0][2][4]\,
      I2 => dqs_count_r(1),
      I3 => \wl_dqs_tap_count_r_reg_n_0_[0][1][4]\,
      I4 => \^dqs_count_r_reg[0]_rep_0\,
      I5 => \wl_dqs_tap_count_r_reg_n_0_[0][0][4]\,
      O => \smallest[0][4]_i_3_n_0\
    );
\smallest[0][4]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \wl_dqs_tap_count_r_reg_n_0_[0][7][4]\,
      I1 => \wl_dqs_tap_count_r_reg_n_0_[0][6][4]\,
      I2 => \^dqs_count_r_reg[1]_rep_0\,
      I3 => \wl_dqs_tap_count_r_reg_n_0_[0][5][4]\,
      I4 => \^dqs_count_r_reg[0]_rep_0\,
      I5 => \wl_dqs_tap_count_r_reg_n_0_[0][4][4]\,
      O => \smallest[0][4]_i_4_n_0\
    );
\smallest[0][5]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00010000"
    )
        port map (
      I0 => \^dqs_count_r_reg[3]_0\(0),
      I1 => \dqs_count_r_reg[2]_rep_n_0\,
      I2 => dqs_count_r(1),
      I3 => dqs_count_r(0),
      I4 => \smallest[0][5]_i_3_n_0\,
      O => \smallest[0][5]_i_1_n_0\
    );
\smallest[0][5]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFEFFFF00020000"
    )
        port map (
      I0 => \smallest_reg[0][5]_i_4_n_0\,
      I1 => \^fsm_sequential_wl_state_r_reg[4]_0\(0),
      I2 => \wl_state_r__0\(0),
      I3 => \wl_state_r__0\(1),
      I4 => \wl_state_r__0\(2),
      I5 => \wl_dqs_tap_count_r_reg_n_0_[0][0][5]\,
      O => largest(5)
    );
\smallest[0][5]_i_3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0100"
    )
        port map (
      I0 => \^fsm_sequential_wl_state_r_reg[4]_0\(0),
      I1 => \wl_state_r__0\(0),
      I2 => \wl_state_r__0\(1),
      I3 => \wl_state_r__0\(2),
      O => \smallest[0][5]_i_3_n_0\
    );
\smallest[0][5]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \wl_dqs_tap_count_r_reg_n_0_[0][3][5]\,
      I1 => \wl_dqs_tap_count_r_reg_n_0_[0][2][5]\,
      I2 => dqs_count_r(1),
      I3 => \wl_dqs_tap_count_r_reg_n_0_[0][1][5]\,
      I4 => dqs_count_r(0),
      I5 => \wl_dqs_tap_count_r_reg_n_0_[0][0][5]\,
      O => \smallest[0][5]_i_5_n_0\
    );
\smallest[0][5]_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \wl_dqs_tap_count_r_reg_n_0_[0][7][5]\,
      I1 => \wl_dqs_tap_count_r_reg_n_0_[0][6][5]\,
      I2 => dqs_count_r(1),
      I3 => \wl_dqs_tap_count_r_reg_n_0_[0][5][5]\,
      I4 => dqs_count_r(0),
      I5 => \wl_dqs_tap_count_r_reg_n_0_[0][4][5]\,
      O => \smallest[0][5]_i_6_n_0\
    );
\smallest[1][0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFEFFFF00020000"
    )
        port map (
      I0 => \smallest_reg[0][0]_i_2_n_0\,
      I1 => \^fsm_sequential_wl_state_r_reg[4]_0\(0),
      I2 => \wl_state_r__0\(0),
      I3 => \wl_state_r__0\(1),
      I4 => \wl_state_r__0\(2),
      I5 => \wl_dqs_tap_count_r_reg_n_0_[0][1][0]\,
      O => \smallest[1][0]_i_1_n_0\
    );
\smallest[1][1]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFEFFFF00020000"
    )
        port map (
      I0 => \smallest_reg[0][1]_i_2_n_0\,
      I1 => \^fsm_sequential_wl_state_r_reg[4]_0\(0),
      I2 => \wl_state_r__0\(0),
      I3 => \wl_state_r__0\(1),
      I4 => \wl_state_r__0\(2),
      I5 => \wl_dqs_tap_count_r_reg_n_0_[0][1][1]\,
      O => \smallest[1][1]_i_1_n_0\
    );
\smallest[1][2]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFEFFFF00020000"
    )
        port map (
      I0 => \smallest_reg[0][2]_i_2_n_0\,
      I1 => \^fsm_sequential_wl_state_r_reg[4]_0\(0),
      I2 => \wl_state_r__0\(0),
      I3 => \wl_state_r__0\(1),
      I4 => \wl_state_r__0\(2),
      I5 => \wl_dqs_tap_count_r_reg_n_0_[0][1][2]\,
      O => \smallest[1][2]_i_1_n_0\
    );
\smallest[1][3]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFEFFFF00020000"
    )
        port map (
      I0 => \smallest_reg[0][3]_i_2_n_0\,
      I1 => \^fsm_sequential_wl_state_r_reg[4]_0\(0),
      I2 => \wl_state_r__0\(0),
      I3 => \wl_state_r__0\(1),
      I4 => \wl_state_r__0\(2),
      I5 => \wl_dqs_tap_count_r_reg_n_0_[0][1][3]\,
      O => \smallest[1][3]_i_1_n_0\
    );
\smallest[1][4]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFEFFFF00020000"
    )
        port map (
      I0 => \smallest_reg[0][4]_i_2_n_0\,
      I1 => \^fsm_sequential_wl_state_r_reg[4]_0\(0),
      I2 => \wl_state_r__0\(0),
      I3 => \wl_state_r__0\(1),
      I4 => \wl_state_r__0\(2),
      I5 => \wl_dqs_tap_count_r_reg_n_0_[0][1][4]\,
      O => \smallest[1][4]_i_1_n_0\
    );
\smallest[1][5]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000200"
    )
        port map (
      I0 => \smallest[0][5]_i_3_n_0\,
      I1 => \^dqs_count_r_reg[3]_0\(0),
      I2 => \dqs_count_r_reg[2]_rep_n_0\,
      I3 => dqs_count_r(0),
      I4 => dqs_count_r(1),
      O => \smallest[1][5]_i_1_n_0\
    );
\smallest[1][5]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFEFFFF00020000"
    )
        port map (
      I0 => \smallest_reg[0][5]_i_4_n_0\,
      I1 => \^fsm_sequential_wl_state_r_reg[4]_0\(0),
      I2 => \wl_state_r__0\(0),
      I3 => \wl_state_r__0\(1),
      I4 => \wl_state_r__0\(2),
      I5 => \wl_dqs_tap_count_r_reg_n_0_[0][1][5]\,
      O => \smallest[1][5]_i_2_n_0\
    );
\smallest[2][0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFEFFFF00020000"
    )
        port map (
      I0 => \smallest_reg[0][0]_i_2_n_0\,
      I1 => \^fsm_sequential_wl_state_r_reg[4]_0\(0),
      I2 => \wl_state_r__0\(0),
      I3 => \wl_state_r__0\(1),
      I4 => \wl_state_r__0\(2),
      I5 => \wl_dqs_tap_count_r_reg_n_0_[0][2][0]\,
      O => \smallest[2][0]_i_1_n_0\
    );
\smallest[2][1]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFEFFFF00020000"
    )
        port map (
      I0 => \smallest_reg[0][1]_i_2_n_0\,
      I1 => \^fsm_sequential_wl_state_r_reg[4]_0\(0),
      I2 => \wl_state_r__0\(0),
      I3 => \wl_state_r__0\(1),
      I4 => \wl_state_r__0\(2),
      I5 => \wl_dqs_tap_count_r_reg_n_0_[0][2][1]\,
      O => \smallest[2][1]_i_1_n_0\
    );
\smallest[2][2]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFEFFFF00020000"
    )
        port map (
      I0 => \smallest_reg[0][2]_i_2_n_0\,
      I1 => \^fsm_sequential_wl_state_r_reg[4]_0\(0),
      I2 => \wl_state_r__0\(0),
      I3 => \wl_state_r__0\(1),
      I4 => \wl_state_r__0\(2),
      I5 => \wl_dqs_tap_count_r_reg_n_0_[0][2][2]\,
      O => \smallest[2][2]_i_1_n_0\
    );
\smallest[2][3]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFEFFFF00020000"
    )
        port map (
      I0 => \smallest_reg[0][3]_i_2_n_0\,
      I1 => \^fsm_sequential_wl_state_r_reg[4]_0\(0),
      I2 => \wl_state_r__0\(0),
      I3 => \wl_state_r__0\(1),
      I4 => \wl_state_r__0\(2),
      I5 => \wl_dqs_tap_count_r_reg_n_0_[0][2][3]\,
      O => \smallest[2][3]_i_1_n_0\
    );
\smallest[2][4]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFEFFFF00020000"
    )
        port map (
      I0 => \smallest_reg[0][4]_i_2_n_0\,
      I1 => \^fsm_sequential_wl_state_r_reg[4]_0\(0),
      I2 => \wl_state_r__0\(0),
      I3 => \wl_state_r__0\(1),
      I4 => \wl_state_r__0\(2),
      I5 => \wl_dqs_tap_count_r_reg_n_0_[0][2][4]\,
      O => \smallest[2][4]_i_1_n_0\
    );
\smallest[2][5]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000200"
    )
        port map (
      I0 => \smallest[0][5]_i_3_n_0\,
      I1 => \^dqs_count_r_reg[3]_0\(0),
      I2 => \dqs_count_r_reg[2]_rep_n_0\,
      I3 => dqs_count_r(1),
      I4 => dqs_count_r(0),
      O => \smallest[2][5]_i_1_n_0\
    );
\smallest[2][5]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFEFFFF00020000"
    )
        port map (
      I0 => \smallest_reg[0][5]_i_4_n_0\,
      I1 => \^fsm_sequential_wl_state_r_reg[4]_0\(0),
      I2 => \wl_state_r__0\(0),
      I3 => \wl_state_r__0\(1),
      I4 => \wl_state_r__0\(2),
      I5 => \wl_dqs_tap_count_r_reg_n_0_[0][2][5]\,
      O => \smallest[2][5]_i_2_n_0\
    );
\smallest[3][0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFEFFFF00020000"
    )
        port map (
      I0 => \smallest_reg[0][0]_i_2_n_0\,
      I1 => \^fsm_sequential_wl_state_r_reg[4]_0\(0),
      I2 => \wl_state_r__0\(0),
      I3 => \wl_state_r__0\(1),
      I4 => \wl_state_r__0\(2),
      I5 => \wl_dqs_tap_count_r_reg_n_0_[0][3][0]\,
      O => \smallest[3][0]_i_1_n_0\
    );
\smallest[3][1]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFEFFFF00020000"
    )
        port map (
      I0 => \smallest_reg[0][1]_i_2_n_0\,
      I1 => \^fsm_sequential_wl_state_r_reg[4]_0\(0),
      I2 => \wl_state_r__0\(0),
      I3 => \wl_state_r__0\(1),
      I4 => \wl_state_r__0\(2),
      I5 => \wl_dqs_tap_count_r_reg_n_0_[0][3][1]\,
      O => \smallest[3][1]_i_1_n_0\
    );
\smallest[3][2]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFEFFFF00020000"
    )
        port map (
      I0 => \smallest_reg[0][2]_i_2_n_0\,
      I1 => \^fsm_sequential_wl_state_r_reg[4]_0\(0),
      I2 => \wl_state_r__0\(0),
      I3 => \wl_state_r__0\(1),
      I4 => \wl_state_r__0\(2),
      I5 => \wl_dqs_tap_count_r_reg_n_0_[0][3][2]\,
      O => \smallest[3][2]_i_1_n_0\
    );
\smallest[3][3]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFEFFFF00020000"
    )
        port map (
      I0 => \smallest_reg[0][3]_i_2_n_0\,
      I1 => \^fsm_sequential_wl_state_r_reg[4]_0\(0),
      I2 => \wl_state_r__0\(0),
      I3 => \wl_state_r__0\(1),
      I4 => \wl_state_r__0\(2),
      I5 => \wl_dqs_tap_count_r_reg_n_0_[0][3][3]\,
      O => \smallest[3][3]_i_1_n_0\
    );
\smallest[3][4]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFEFFFF00020000"
    )
        port map (
      I0 => \smallest_reg[0][4]_i_2_n_0\,
      I1 => \^fsm_sequential_wl_state_r_reg[4]_0\(0),
      I2 => \wl_state_r__0\(0),
      I3 => \wl_state_r__0\(1),
      I4 => \wl_state_r__0\(2),
      I5 => \wl_dqs_tap_count_r_reg_n_0_[0][3][4]\,
      O => \smallest[3][4]_i_1_n_0\
    );
\smallest[3][5]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000080"
    )
        port map (
      I0 => \smallest[0][5]_i_3_n_0\,
      I1 => dqs_count_r(1),
      I2 => dqs_count_r(0),
      I3 => \^dqs_count_r_reg[3]_0\(0),
      I4 => \dqs_count_r_reg[2]_rep_n_0\,
      O => \smallest[3][5]_i_1_n_0\
    );
\smallest[3][5]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFEFFFF00020000"
    )
        port map (
      I0 => \smallest_reg[0][5]_i_4_n_0\,
      I1 => \^fsm_sequential_wl_state_r_reg[4]_0\(0),
      I2 => \wl_state_r__0\(0),
      I3 => \wl_state_r__0\(1),
      I4 => \wl_state_r__0\(2),
      I5 => \wl_dqs_tap_count_r_reg_n_0_[0][3][5]\,
      O => \smallest[3][5]_i_2_n_0\
    );
\smallest[4][0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFEFFFF00020000"
    )
        port map (
      I0 => \smallest_reg[0][0]_i_2_n_0\,
      I1 => \^fsm_sequential_wl_state_r_reg[4]_0\(0),
      I2 => \wl_state_r__0\(0),
      I3 => \wl_state_r__0\(1),
      I4 => \wl_state_r__0\(2),
      I5 => \wl_dqs_tap_count_r_reg_n_0_[0][4][0]\,
      O => \smallest[4][0]_i_1_n_0\
    );
\smallest[4][1]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFEFFFF00020000"
    )
        port map (
      I0 => \smallest_reg[0][1]_i_2_n_0\,
      I1 => \^fsm_sequential_wl_state_r_reg[4]_0\(0),
      I2 => \wl_state_r__0\(0),
      I3 => \wl_state_r__0\(1),
      I4 => \wl_state_r__0\(2),
      I5 => \wl_dqs_tap_count_r_reg_n_0_[0][4][1]\,
      O => \smallest[4][1]_i_1_n_0\
    );
\smallest[4][2]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFEFFFF00020000"
    )
        port map (
      I0 => \smallest_reg[0][2]_i_2_n_0\,
      I1 => \^fsm_sequential_wl_state_r_reg[4]_0\(0),
      I2 => \wl_state_r__0\(0),
      I3 => \wl_state_r__0\(1),
      I4 => \wl_state_r__0\(2),
      I5 => \wl_dqs_tap_count_r_reg_n_0_[0][4][2]\,
      O => \smallest[4][2]_i_1_n_0\
    );
\smallest[4][3]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFEFFFF00020000"
    )
        port map (
      I0 => \smallest_reg[0][3]_i_2_n_0\,
      I1 => \^fsm_sequential_wl_state_r_reg[4]_0\(0),
      I2 => \wl_state_r__0\(0),
      I3 => \wl_state_r__0\(1),
      I4 => \wl_state_r__0\(2),
      I5 => \wl_dqs_tap_count_r_reg_n_0_[0][4][3]\,
      O => \smallest[4][3]_i_1_n_0\
    );
\smallest[4][4]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFEFFFF00020000"
    )
        port map (
      I0 => \smallest_reg[0][4]_i_2_n_0\,
      I1 => \^fsm_sequential_wl_state_r_reg[4]_0\(0),
      I2 => \wl_state_r__0\(0),
      I3 => \wl_state_r__0\(1),
      I4 => \wl_state_r__0\(2),
      I5 => \wl_dqs_tap_count_r_reg_n_0_[0][4][4]\,
      O => \smallest[4][4]_i_1_n_0\
    );
\smallest[4][5]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000020"
    )
        port map (
      I0 => \smallest[0][5]_i_3_n_0\,
      I1 => \^dqs_count_r_reg[3]_0\(0),
      I2 => \dqs_count_r_reg[2]_rep_n_0\,
      I3 => dqs_count_r(1),
      I4 => dqs_count_r(0),
      O => \smallest[4][5]_i_1_n_0\
    );
\smallest[4][5]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFEFFFF00020000"
    )
        port map (
      I0 => \smallest_reg[0][5]_i_4_n_0\,
      I1 => \^fsm_sequential_wl_state_r_reg[4]_0\(0),
      I2 => \wl_state_r__0\(0),
      I3 => \wl_state_r__0\(1),
      I4 => \wl_state_r__0\(2),
      I5 => \wl_dqs_tap_count_r_reg_n_0_[0][4][5]\,
      O => \smallest[4][5]_i_2_n_0\
    );
\smallest[5][0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFEFFFF00020000"
    )
        port map (
      I0 => \smallest_reg[0][0]_i_2_n_0\,
      I1 => \^fsm_sequential_wl_state_r_reg[4]_0\(0),
      I2 => \wl_state_r__0\(0),
      I3 => \wl_state_r__0\(1),
      I4 => \wl_state_r__0\(2),
      I5 => \wl_dqs_tap_count_r_reg_n_0_[0][5][0]\,
      O => \smallest[5][0]_i_1_n_0\
    );
\smallest[5][1]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFEFFFF00020000"
    )
        port map (
      I0 => \smallest_reg[0][1]_i_2_n_0\,
      I1 => \^fsm_sequential_wl_state_r_reg[4]_0\(0),
      I2 => \wl_state_r__0\(0),
      I3 => \wl_state_r__0\(1),
      I4 => \wl_state_r__0\(2),
      I5 => \wl_dqs_tap_count_r_reg_n_0_[0][5][1]\,
      O => \smallest[5][1]_i_1_n_0\
    );
\smallest[5][2]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFEFFFF00020000"
    )
        port map (
      I0 => \smallest_reg[0][2]_i_2_n_0\,
      I1 => \^fsm_sequential_wl_state_r_reg[4]_0\(0),
      I2 => \wl_state_r__0\(0),
      I3 => \wl_state_r__0\(1),
      I4 => \wl_state_r__0\(2),
      I5 => \wl_dqs_tap_count_r_reg_n_0_[0][5][2]\,
      O => \smallest[5][2]_i_1_n_0\
    );
\smallest[5][3]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFEFFFF00020000"
    )
        port map (
      I0 => \smallest_reg[0][3]_i_2_n_0\,
      I1 => \^fsm_sequential_wl_state_r_reg[4]_0\(0),
      I2 => \wl_state_r__0\(0),
      I3 => \wl_state_r__0\(1),
      I4 => \wl_state_r__0\(2),
      I5 => \wl_dqs_tap_count_r_reg_n_0_[0][5][3]\,
      O => \smallest[5][3]_i_1_n_0\
    );
\smallest[5][4]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFEFFFF00020000"
    )
        port map (
      I0 => \smallest_reg[0][4]_i_2_n_0\,
      I1 => \^fsm_sequential_wl_state_r_reg[4]_0\(0),
      I2 => \wl_state_r__0\(0),
      I3 => \wl_state_r__0\(1),
      I4 => \wl_state_r__0\(2),
      I5 => \wl_dqs_tap_count_r_reg_n_0_[0][5][4]\,
      O => \smallest[5][4]_i_1_n_0\
    );
\smallest[5][5]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00002000"
    )
        port map (
      I0 => \smallest[0][5]_i_3_n_0\,
      I1 => \^dqs_count_r_reg[3]_0\(0),
      I2 => \dqs_count_r_reg[2]_rep_n_0\,
      I3 => dqs_count_r(0),
      I4 => dqs_count_r(1),
      O => \smallest[5][5]_i_1_n_0\
    );
\smallest[5][5]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFEFFFF00020000"
    )
        port map (
      I0 => \smallest_reg[0][5]_i_4_n_0\,
      I1 => \^fsm_sequential_wl_state_r_reg[4]_0\(0),
      I2 => \wl_state_r__0\(0),
      I3 => \wl_state_r__0\(1),
      I4 => \wl_state_r__0\(2),
      I5 => \wl_dqs_tap_count_r_reg_n_0_[0][5][5]\,
      O => \smallest[5][5]_i_2_n_0\
    );
\smallest[6][0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFEFFFF00020000"
    )
        port map (
      I0 => \smallest_reg[0][0]_i_2_n_0\,
      I1 => \^fsm_sequential_wl_state_r_reg[4]_0\(0),
      I2 => \wl_state_r__0\(0),
      I3 => \wl_state_r__0\(1),
      I4 => \wl_state_r__0\(2),
      I5 => \wl_dqs_tap_count_r_reg_n_0_[0][6][0]\,
      O => \smallest[6][0]_i_1_n_0\
    );
\smallest[6][1]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFEFFFF00020000"
    )
        port map (
      I0 => \smallest_reg[0][1]_i_2_n_0\,
      I1 => \^fsm_sequential_wl_state_r_reg[4]_0\(0),
      I2 => \wl_state_r__0\(0),
      I3 => \wl_state_r__0\(1),
      I4 => \wl_state_r__0\(2),
      I5 => \wl_dqs_tap_count_r_reg_n_0_[0][6][1]\,
      O => \smallest[6][1]_i_1_n_0\
    );
\smallest[6][2]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFEFFFF00020000"
    )
        port map (
      I0 => \smallest_reg[0][2]_i_2_n_0\,
      I1 => \^fsm_sequential_wl_state_r_reg[4]_0\(0),
      I2 => \wl_state_r__0\(0),
      I3 => \wl_state_r__0\(1),
      I4 => \wl_state_r__0\(2),
      I5 => \wl_dqs_tap_count_r_reg_n_0_[0][6][2]\,
      O => \smallest[6][2]_i_1_n_0\
    );
\smallest[6][3]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFEFFFF00020000"
    )
        port map (
      I0 => \smallest_reg[0][3]_i_2_n_0\,
      I1 => \^fsm_sequential_wl_state_r_reg[4]_0\(0),
      I2 => \wl_state_r__0\(0),
      I3 => \wl_state_r__0\(1),
      I4 => \wl_state_r__0\(2),
      I5 => \wl_dqs_tap_count_r_reg_n_0_[0][6][3]\,
      O => \smallest[6][3]_i_1_n_0\
    );
\smallest[6][4]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFEFFFF00020000"
    )
        port map (
      I0 => \smallest_reg[0][4]_i_2_n_0\,
      I1 => \^fsm_sequential_wl_state_r_reg[4]_0\(0),
      I2 => \wl_state_r__0\(0),
      I3 => \wl_state_r__0\(1),
      I4 => \wl_state_r__0\(2),
      I5 => \wl_dqs_tap_count_r_reg_n_0_[0][6][4]\,
      O => \smallest[6][4]_i_1_n_0\
    );
\smallest[6][5]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00002000"
    )
        port map (
      I0 => \smallest[0][5]_i_3_n_0\,
      I1 => \^dqs_count_r_reg[3]_0\(0),
      I2 => \dqs_count_r_reg[2]_rep_n_0\,
      I3 => dqs_count_r(1),
      I4 => dqs_count_r(0),
      O => \smallest[6][5]_i_1_n_0\
    );
\smallest[6][5]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFEFFFF00020000"
    )
        port map (
      I0 => \smallest_reg[0][5]_i_4_n_0\,
      I1 => \^fsm_sequential_wl_state_r_reg[4]_0\(0),
      I2 => \wl_state_r__0\(0),
      I3 => \wl_state_r__0\(1),
      I4 => \wl_state_r__0\(2),
      I5 => \wl_dqs_tap_count_r_reg_n_0_[0][6][5]\,
      O => \smallest[6][5]_i_2_n_0\
    );
\smallest[7][0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFEFFFF00020000"
    )
        port map (
      I0 => \smallest_reg[0][0]_i_2_n_0\,
      I1 => \^fsm_sequential_wl_state_r_reg[4]_0\(0),
      I2 => \wl_state_r__0\(0),
      I3 => \wl_state_r__0\(1),
      I4 => \wl_state_r__0\(2),
      I5 => \wl_dqs_tap_count_r_reg_n_0_[0][7][0]\,
      O => \smallest[7][0]_i_1_n_0\
    );
\smallest[7][1]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFEFFFF00020000"
    )
        port map (
      I0 => \smallest_reg[0][1]_i_2_n_0\,
      I1 => \^fsm_sequential_wl_state_r_reg[4]_0\(0),
      I2 => \wl_state_r__0\(0),
      I3 => \wl_state_r__0\(1),
      I4 => \wl_state_r__0\(2),
      I5 => \wl_dqs_tap_count_r_reg_n_0_[0][7][1]\,
      O => \smallest[7][1]_i_1_n_0\
    );
\smallest[7][2]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFEFFFF00020000"
    )
        port map (
      I0 => \smallest_reg[0][2]_i_2_n_0\,
      I1 => \^fsm_sequential_wl_state_r_reg[4]_0\(0),
      I2 => \wl_state_r__0\(0),
      I3 => \wl_state_r__0\(1),
      I4 => \wl_state_r__0\(2),
      I5 => \wl_dqs_tap_count_r_reg_n_0_[0][7][2]\,
      O => \smallest[7][2]_i_1_n_0\
    );
\smallest[7][3]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFEFFFF00020000"
    )
        port map (
      I0 => \smallest_reg[0][3]_i_2_n_0\,
      I1 => \^fsm_sequential_wl_state_r_reg[4]_0\(0),
      I2 => \wl_state_r__0\(0),
      I3 => \wl_state_r__0\(1),
      I4 => \wl_state_r__0\(2),
      I5 => \wl_dqs_tap_count_r_reg_n_0_[0][7][3]\,
      O => \smallest[7][3]_i_1_n_0\
    );
\smallest[7][4]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFEFFFF00020000"
    )
        port map (
      I0 => \smallest_reg[0][4]_i_2_n_0\,
      I1 => \^fsm_sequential_wl_state_r_reg[4]_0\(0),
      I2 => \wl_state_r__0\(0),
      I3 => \wl_state_r__0\(1),
      I4 => \wl_state_r__0\(2),
      I5 => \wl_dqs_tap_count_r_reg_n_0_[0][7][4]\,
      O => \smallest[7][4]_i_1_n_0\
    );
\smallest[7][5]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00800000"
    )
        port map (
      I0 => dqs_count_r(0),
      I1 => dqs_count_r(1),
      I2 => \dqs_count_r_reg[2]_rep_n_0\,
      I3 => \^dqs_count_r_reg[3]_0\(0),
      I4 => \smallest[0][5]_i_3_n_0\,
      O => \smallest[7][5]_i_1_n_0\
    );
\smallest[7][5]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFEFFFF00020000"
    )
        port map (
      I0 => \smallest_reg[0][5]_i_4_n_0\,
      I1 => \^fsm_sequential_wl_state_r_reg[4]_0\(0),
      I2 => \wl_state_r__0\(0),
      I3 => \wl_state_r__0\(1),
      I4 => \wl_state_r__0\(2),
      I5 => \wl_dqs_tap_count_r_reg_n_0_[0][7][5]\,
      O => \smallest[7][5]_i_2_n_0\
    );
\smallest_reg[0][0]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => \smallest[0][5]_i_1_n_0\,
      D => largest(0),
      Q => \smallest_reg[0]_13\(0),
      R => \corse_dec_reg[7][0]_0\(0)
    );
\smallest_reg[0][0]_i_2\: unisim.vcomponents.MUXF7
     port map (
      I0 => \smallest[0][0]_i_3_n_0\,
      I1 => \smallest[0][0]_i_4_n_0\,
      O => \smallest_reg[0][0]_i_2_n_0\,
      S => dqs_count_r(2)
    );
\smallest_reg[0][1]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => \smallest[0][5]_i_1_n_0\,
      D => largest(1),
      Q => \smallest_reg[0]_13\(1),
      R => \corse_dec_reg[7][0]_0\(0)
    );
\smallest_reg[0][1]_i_2\: unisim.vcomponents.MUXF7
     port map (
      I0 => \smallest[0][1]_i_3_n_0\,
      I1 => \smallest[0][1]_i_4_n_0\,
      O => \smallest_reg[0][1]_i_2_n_0\,
      S => dqs_count_r(2)
    );
\smallest_reg[0][2]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => \smallest[0][5]_i_1_n_0\,
      D => largest(2),
      Q => \smallest_reg[0]_13\(2),
      R => \corse_dec_reg[7][0]_0\(0)
    );
\smallest_reg[0][2]_i_2\: unisim.vcomponents.MUXF7
     port map (
      I0 => \smallest[0][2]_i_3_n_0\,
      I1 => \smallest[0][2]_i_4_n_0\,
      O => \smallest_reg[0][2]_i_2_n_0\,
      S => dqs_count_r(2)
    );
\smallest_reg[0][3]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => \smallest[0][5]_i_1_n_0\,
      D => largest(3),
      Q => \smallest_reg[0]_13\(3),
      R => \corse_dec_reg[7][0]_0\(0)
    );
\smallest_reg[0][3]_i_2\: unisim.vcomponents.MUXF7
     port map (
      I0 => \smallest[0][3]_i_3_n_0\,
      I1 => \smallest[0][3]_i_4_n_0\,
      O => \smallest_reg[0][3]_i_2_n_0\,
      S => dqs_count_r(2)
    );
\smallest_reg[0][4]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => \smallest[0][5]_i_1_n_0\,
      D => largest(4),
      Q => \smallest_reg[0]_13\(4),
      R => \corse_dec_reg[7][0]_0\(0)
    );
\smallest_reg[0][4]_i_2\: unisim.vcomponents.MUXF7
     port map (
      I0 => \smallest[0][4]_i_3_n_0\,
      I1 => \smallest[0][4]_i_4_n_0\,
      O => \smallest_reg[0][4]_i_2_n_0\,
      S => dqs_count_r(2)
    );
\smallest_reg[0][5]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => \smallest[0][5]_i_1_n_0\,
      D => largest(5),
      Q => \smallest_reg[0]_13\(5),
      R => \corse_dec_reg[7][0]_0\(0)
    );
\smallest_reg[0][5]_i_4\: unisim.vcomponents.MUXF7
     port map (
      I0 => \smallest[0][5]_i_5_n_0\,
      I1 => \smallest[0][5]_i_6_n_0\,
      O => \smallest_reg[0][5]_i_4_n_0\,
      S => dqs_count_r(2)
    );
\smallest_reg[1][0]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => \smallest[1][5]_i_1_n_0\,
      D => \smallest[1][0]_i_1_n_0\,
      Q => \smallest_reg[1]_14\(0),
      R => \corse_dec_reg[7][0]_0\(0)
    );
\smallest_reg[1][1]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => \smallest[1][5]_i_1_n_0\,
      D => \smallest[1][1]_i_1_n_0\,
      Q => \smallest_reg[1]_14\(1),
      R => \corse_dec_reg[7][0]_0\(0)
    );
\smallest_reg[1][2]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => \smallest[1][5]_i_1_n_0\,
      D => \smallest[1][2]_i_1_n_0\,
      Q => \smallest_reg[1]_14\(2),
      R => \corse_dec_reg[7][0]_0\(0)
    );
\smallest_reg[1][3]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => \smallest[1][5]_i_1_n_0\,
      D => \smallest[1][3]_i_1_n_0\,
      Q => \smallest_reg[1]_14\(3),
      R => \corse_dec_reg[7][0]_0\(0)
    );
\smallest_reg[1][4]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => \smallest[1][5]_i_1_n_0\,
      D => \smallest[1][4]_i_1_n_0\,
      Q => \smallest_reg[1]_14\(4),
      R => \corse_dec_reg[7][0]_0\(0)
    );
\smallest_reg[1][5]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => \smallest[1][5]_i_1_n_0\,
      D => \smallest[1][5]_i_2_n_0\,
      Q => \smallest_reg[1]_14\(5),
      R => \corse_dec_reg[7][0]_0\(0)
    );
\smallest_reg[2][0]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => \smallest[2][5]_i_1_n_0\,
      D => \smallest[2][0]_i_1_n_0\,
      Q => \smallest_reg[2]_15\(0),
      R => \corse_dec_reg[7][0]_0\(0)
    );
\smallest_reg[2][1]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => \smallest[2][5]_i_1_n_0\,
      D => \smallest[2][1]_i_1_n_0\,
      Q => \smallest_reg[2]_15\(1),
      R => \corse_dec_reg[7][0]_0\(0)
    );
\smallest_reg[2][2]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => \smallest[2][5]_i_1_n_0\,
      D => \smallest[2][2]_i_1_n_0\,
      Q => \smallest_reg[2]_15\(2),
      R => \corse_dec_reg[7][0]_0\(0)
    );
\smallest_reg[2][3]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => \smallest[2][5]_i_1_n_0\,
      D => \smallest[2][3]_i_1_n_0\,
      Q => \smallest_reg[2]_15\(3),
      R => \corse_dec_reg[7][0]_0\(0)
    );
\smallest_reg[2][4]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => \smallest[2][5]_i_1_n_0\,
      D => \smallest[2][4]_i_1_n_0\,
      Q => \smallest_reg[2]_15\(4),
      R => \corse_dec_reg[7][0]_0\(0)
    );
\smallest_reg[2][5]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => \smallest[2][5]_i_1_n_0\,
      D => \smallest[2][5]_i_2_n_0\,
      Q => \smallest_reg[2]_15\(5),
      R => \corse_dec_reg[7][0]_0\(0)
    );
\smallest_reg[3][0]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => \smallest[3][5]_i_1_n_0\,
      D => \smallest[3][0]_i_1_n_0\,
      Q => \smallest_reg[3]_16\(0),
      R => \corse_dec_reg[7][0]_0\(0)
    );
\smallest_reg[3][1]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => \smallest[3][5]_i_1_n_0\,
      D => \smallest[3][1]_i_1_n_0\,
      Q => \smallest_reg[3]_16\(1),
      R => \corse_dec_reg[7][0]_0\(0)
    );
\smallest_reg[3][2]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => \smallest[3][5]_i_1_n_0\,
      D => \smallest[3][2]_i_1_n_0\,
      Q => \smallest_reg[3]_16\(2),
      R => \corse_dec_reg[7][0]_0\(0)
    );
\smallest_reg[3][3]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => \smallest[3][5]_i_1_n_0\,
      D => \smallest[3][3]_i_1_n_0\,
      Q => \smallest_reg[3]_16\(3),
      R => \corse_dec_reg[7][0]_0\(0)
    );
\smallest_reg[3][4]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => \smallest[3][5]_i_1_n_0\,
      D => \smallest[3][4]_i_1_n_0\,
      Q => \smallest_reg[3]_16\(4),
      R => \corse_dec_reg[7][0]_0\(0)
    );
\smallest_reg[3][5]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => \smallest[3][5]_i_1_n_0\,
      D => \smallest[3][5]_i_2_n_0\,
      Q => \smallest_reg[3]_16\(5),
      R => \corse_dec_reg[7][0]_0\(0)
    );
\smallest_reg[4][0]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => \smallest[4][5]_i_1_n_0\,
      D => \smallest[4][0]_i_1_n_0\,
      Q => \smallest_reg[4]_17\(0),
      R => \corse_dec_reg[7][0]_0\(0)
    );
\smallest_reg[4][1]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => \smallest[4][5]_i_1_n_0\,
      D => \smallest[4][1]_i_1_n_0\,
      Q => \smallest_reg[4]_17\(1),
      R => \corse_dec_reg[7][0]_0\(0)
    );
\smallest_reg[4][2]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => \smallest[4][5]_i_1_n_0\,
      D => \smallest[4][2]_i_1_n_0\,
      Q => \smallest_reg[4]_17\(2),
      R => \corse_dec_reg[7][0]_0\(0)
    );
\smallest_reg[4][3]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => \smallest[4][5]_i_1_n_0\,
      D => \smallest[4][3]_i_1_n_0\,
      Q => \smallest_reg[4]_17\(3),
      R => \corse_dec_reg[7][0]_0\(0)
    );
\smallest_reg[4][4]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => \smallest[4][5]_i_1_n_0\,
      D => \smallest[4][4]_i_1_n_0\,
      Q => \smallest_reg[4]_17\(4),
      R => \corse_dec_reg[7][0]_0\(0)
    );
\smallest_reg[4][5]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => \smallest[4][5]_i_1_n_0\,
      D => \smallest[4][5]_i_2_n_0\,
      Q => \smallest_reg[4]_17\(5),
      R => \corse_dec_reg[7][0]_0\(0)
    );
\smallest_reg[5][0]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => \smallest[5][5]_i_1_n_0\,
      D => \smallest[5][0]_i_1_n_0\,
      Q => \smallest_reg[5]_18\(0),
      R => \corse_dec_reg[7][0]_0\(0)
    );
\smallest_reg[5][1]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => \smallest[5][5]_i_1_n_0\,
      D => \smallest[5][1]_i_1_n_0\,
      Q => \smallest_reg[5]_18\(1),
      R => \corse_dec_reg[7][0]_0\(0)
    );
\smallest_reg[5][2]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => \smallest[5][5]_i_1_n_0\,
      D => \smallest[5][2]_i_1_n_0\,
      Q => \smallest_reg[5]_18\(2),
      R => \corse_dec_reg[7][0]_0\(0)
    );
\smallest_reg[5][3]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => \smallest[5][5]_i_1_n_0\,
      D => \smallest[5][3]_i_1_n_0\,
      Q => \smallest_reg[5]_18\(3),
      R => \corse_dec_reg[7][0]_0\(0)
    );
\smallest_reg[5][4]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => \smallest[5][5]_i_1_n_0\,
      D => \smallest[5][4]_i_1_n_0\,
      Q => \smallest_reg[5]_18\(4),
      R => \corse_dec_reg[7][0]_0\(0)
    );
\smallest_reg[5][5]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => \smallest[5][5]_i_1_n_0\,
      D => \smallest[5][5]_i_2_n_0\,
      Q => \smallest_reg[5]_18\(5),
      R => \corse_dec_reg[7][0]_0\(0)
    );
\smallest_reg[6][0]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => \smallest[6][5]_i_1_n_0\,
      D => \smallest[6][0]_i_1_n_0\,
      Q => \smallest_reg[6]_19\(0),
      R => \corse_dec_reg[7][0]_0\(0)
    );
\smallest_reg[6][1]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => \smallest[6][5]_i_1_n_0\,
      D => \smallest[6][1]_i_1_n_0\,
      Q => \smallest_reg[6]_19\(1),
      R => \corse_dec_reg[7][0]_0\(0)
    );
\smallest_reg[6][2]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => \smallest[6][5]_i_1_n_0\,
      D => \smallest[6][2]_i_1_n_0\,
      Q => \smallest_reg[6]_19\(2),
      R => \corse_dec_reg[7][0]_0\(0)
    );
\smallest_reg[6][3]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => \smallest[6][5]_i_1_n_0\,
      D => \smallest[6][3]_i_1_n_0\,
      Q => \smallest_reg[6]_19\(3),
      R => \corse_dec_reg[7][0]_0\(0)
    );
\smallest_reg[6][4]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => \smallest[6][5]_i_1_n_0\,
      D => \smallest[6][4]_i_1_n_0\,
      Q => \smallest_reg[6]_19\(4),
      R => \corse_dec_reg[7][0]_0\(0)
    );
\smallest_reg[6][5]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => \smallest[6][5]_i_1_n_0\,
      D => \smallest[6][5]_i_2_n_0\,
      Q => \smallest_reg[6]_19\(5),
      R => \corse_dec_reg[7][0]_0\(0)
    );
\smallest_reg[7][0]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => \smallest[7][5]_i_1_n_0\,
      D => \smallest[7][0]_i_1_n_0\,
      Q => \smallest_reg[7]_20\(0),
      R => \corse_dec_reg[7][0]_0\(0)
    );
\smallest_reg[7][1]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => \smallest[7][5]_i_1_n_0\,
      D => \smallest[7][1]_i_1_n_0\,
      Q => \smallest_reg[7]_20\(1),
      R => \corse_dec_reg[7][0]_0\(0)
    );
\smallest_reg[7][2]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => \smallest[7][5]_i_1_n_0\,
      D => \smallest[7][2]_i_1_n_0\,
      Q => \smallest_reg[7]_20\(2),
      R => \corse_dec_reg[7][0]_0\(0)
    );
\smallest_reg[7][3]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => \smallest[7][5]_i_1_n_0\,
      D => \smallest[7][3]_i_1_n_0\,
      Q => \smallest_reg[7]_20\(3),
      R => \corse_dec_reg[7][0]_0\(0)
    );
\smallest_reg[7][4]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => \smallest[7][5]_i_1_n_0\,
      D => \smallest[7][4]_i_1_n_0\,
      Q => \smallest_reg[7]_20\(4),
      R => \corse_dec_reg[7][0]_0\(0)
    );
\smallest_reg[7][5]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => \smallest[7][5]_i_1_n_0\,
      D => \smallest[7][5]_i_2_n_0\,
      Q => \smallest_reg[7]_20\(5),
      R => \corse_dec_reg[7][0]_0\(0)
    );
\stable_cnt[0]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \stable_cnt_reg_n_0_[0]\,
      O => \p_0_in__1\(0)
    );
\stable_cnt[1]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \stable_cnt_reg_n_0_[0]\,
      I1 => \stable_cnt_reg_n_0_[1]\,
      O => \p_0_in__1\(1)
    );
\stable_cnt[2]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"6A"
    )
        port map (
      I0 => \stable_cnt_reg_n_0_[2]\,
      I1 => \stable_cnt_reg_n_0_[1]\,
      I2 => \stable_cnt_reg_n_0_[0]\,
      O => \p_0_in__1\(2)
    );
\stable_cnt[3]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"55555557FFFFFFFF"
    )
        port map (
      I0 => \stable_cnt[3]_i_4_n_0\,
      I1 => \wl_state_r__0\(0),
      I2 => \wl_state_r__0\(1),
      I3 => \^fsm_sequential_wl_state_r_reg[4]_0\(1),
      I4 => \^fsm_sequential_wl_state_r_reg[4]_0\(0),
      I5 => \stable_cnt[3]_i_5_n_0\,
      O => stable_cnt0
    );
\stable_cnt[3]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00001555"
    )
        port map (
      I0 => \rd_data_edge_detect_r[7]_i_4_n_0\,
      I1 => \stable_cnt_reg_n_0_[3]\,
      I2 => \stable_cnt_reg_n_0_[1]\,
      I3 => \stable_cnt_reg_n_0_[2]\,
      I4 => \rd_data_previous_r[7]_i_2_n_0\,
      O => stable_cnt
    );
\stable_cnt[3]_i_3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6AAA"
    )
        port map (
      I0 => \stable_cnt_reg_n_0_[3]\,
      I1 => \stable_cnt_reg_n_0_[0]\,
      I2 => \stable_cnt_reg_n_0_[1]\,
      I3 => \stable_cnt_reg_n_0_[2]\,
      O => \p_0_in__1\(3)
    );
\stable_cnt[3]_i_4\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"56A6"
    )
        port map (
      I0 => \rd_data_edge_detect_r_reg[7]_i_9_n_0\,
      I1 => \stable_cnt[3]_i_6_n_0\,
      I2 => \^dqs_count_r_reg[2]_rep__0_0\,
      I3 => \stable_cnt[3]_i_7_n_0\,
      O => \stable_cnt[3]_i_4_n_0\
    );
\stable_cnt[3]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000FBFB00FB"
    )
        port map (
      I0 => \stable_cnt[3]_i_8_n_0\,
      I1 => \wl_state_r1_reg_n_0_[0]\,
      I2 => \wl_state_r1_reg_n_0_[1]\,
      I3 => \stable_cnt[3]_i_9_n_0\,
      I4 => \wl_state_r__0\(1),
      I5 => \single_rank.done_dqs_dec_reg_0\,
      O => \stable_cnt[3]_i_5_n_0\
    );
\stable_cnt[3]_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"505F3030505F3F3F"
    )
        port map (
      I0 => \gen_rd[3].rd_data_rise_wl_r_reg_n_0_[3]\,
      I1 => \gen_rd[2].rd_data_rise_wl_r_reg_n_0_[2]\,
      I2 => \^dqs_count_r_reg[1]_rep_0\,
      I3 => \gen_rd[1].rd_data_rise_wl_r_reg_n_0_[1]\,
      I4 => \^dqs_count_r_reg[0]_rep_0\,
      I5 => \gen_rd[0].rd_data_rise_wl_r_reg_n_0_[0]\,
      O => \stable_cnt[3]_i_6_n_0\
    );
\stable_cnt[3]_i_7\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"05F5030305F5F3F3"
    )
        port map (
      I0 => \gen_rd[5].rd_data_rise_wl_r_reg_n_0_[5]\,
      I1 => \gen_rd[4].rd_data_rise_wl_r_reg_n_0_[4]\,
      I2 => \^dqs_count_r_reg[1]_rep_0\,
      I3 => \gen_rd[7].rd_data_rise_wl_r_reg_n_0_[7]\,
      I4 => \^dqs_count_r_reg[0]_rep_0\,
      I5 => \gen_rd[6].rd_data_rise_wl_r_reg_n_0_[6]\,
      O => \stable_cnt[3]_i_7_n_0\
    );
\stable_cnt[3]_i_8\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"FB"
    )
        port map (
      I0 => \wl_state_r1_reg_n_0_[4]\,
      I1 => \wl_state_r1_reg_n_0_[2]\,
      I2 => \wl_state_r1_reg_n_0_[3]\,
      O => \stable_cnt[3]_i_8_n_0\
    );
\stable_cnt[3]_i_9\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0040"
    )
        port map (
      I0 => \^fsm_sequential_wl_state_r_reg[4]_0\(0),
      I1 => \wl_state_r__0\(2),
      I2 => \^fsm_sequential_wl_state_r_reg[4]_0\(1),
      I3 => \wl_state_r__0\(0),
      O => \stable_cnt[3]_i_9_n_0\
    );
\stable_cnt_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => stable_cnt,
      D => \p_0_in__1\(0),
      Q => \stable_cnt_reg_n_0_[0]\,
      R => stable_cnt0
    );
\stable_cnt_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => stable_cnt,
      D => \p_0_in__1\(1),
      Q => \stable_cnt_reg_n_0_[1]\,
      R => stable_cnt0
    );
\stable_cnt_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => stable_cnt,
      D => \p_0_in__1\(2),
      Q => \stable_cnt_reg_n_0_[2]\,
      R => stable_cnt0
    );
\stable_cnt_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => stable_cnt,
      D => \p_0_in__1\(3),
      Q => \stable_cnt_reg_n_0_[3]\,
      R => stable_cnt0
    );
\wait_cnt[0]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => wait_cnt_reg(0),
      O => \wait_cnt0__0\(0)
    );
\wait_cnt[1]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => wait_cnt_reg(0),
      I1 => wait_cnt_reg(1),
      O => \wait_cnt[1]_i_1_n_0\
    );
\wait_cnt[2]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"A9"
    )
        port map (
      I0 => wait_cnt_reg(2),
      I1 => wait_cnt_reg(1),
      I2 => wait_cnt_reg(0),
      O => \wait_cnt0__0\(2)
    );
\wait_cnt[3]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AAAAAAA8"
    )
        port map (
      I0 => phy_ctl_ready_r6_reg_n_0,
      I1 => wait_cnt_reg(3),
      I2 => wait_cnt_reg(1),
      I3 => wait_cnt_reg(0),
      I4 => wait_cnt_reg(2),
      O => wait_cnt0
    );
\wait_cnt[3]_i_3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"AAA9"
    )
        port map (
      I0 => wait_cnt_reg(3),
      I1 => wait_cnt_reg(2),
      I2 => wait_cnt_reg(0),
      I3 => wait_cnt_reg(1),
      O => \wait_cnt0__0\(3)
    );
\wait_cnt_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => wait_cnt0,
      D => \wait_cnt0__0\(0),
      Q => wait_cnt_reg(0),
      R => \wait_cnt_reg[0]_0\(0)
    );
\wait_cnt_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => wait_cnt0,
      D => \wait_cnt[1]_i_1_n_0\,
      Q => wait_cnt_reg(1),
      R => \wait_cnt_reg[0]_0\(0)
    );
\wait_cnt_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => wait_cnt0,
      D => \wait_cnt0__0\(2),
      Q => wait_cnt_reg(2),
      R => \wait_cnt_reg[0]_0\(0)
    );
\wait_cnt_reg[3]\: unisim.vcomponents.FDSE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => wait_cnt0,
      D => \wait_cnt0__0\(3),
      Q => wait_cnt_reg(3),
      S => \wait_cnt_reg[0]_0\(0)
    );
\wl_corse_cnt[0][0][0]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \corse_cnt_reg_n_0_[3][0]\,
      I1 => \corse_cnt_reg_n_0_[2][0]\,
      I2 => \^dqs_count_r_reg[1]_rep_0\,
      I3 => \corse_cnt_reg_n_0_[1][0]\,
      I4 => \^dqs_count_r_reg[0]_rep_0\,
      I5 => \corse_cnt_reg_n_0_[0][0]\,
      O => \wl_corse_cnt[0][0][0]_i_2_n_0\
    );
\wl_corse_cnt[0][0][0]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \corse_cnt_reg_n_0_[7][0]\,
      I1 => \corse_cnt_reg_n_0_[6][0]\,
      I2 => \^dqs_count_r_reg[1]_rep_0\,
      I3 => \corse_cnt_reg_n_0_[5][0]\,
      I4 => \^dqs_count_r_reg[0]_rep_0\,
      I5 => \corse_cnt_reg_n_0_[4][0]\,
      O => \wl_corse_cnt[0][0][0]_i_3_n_0\
    );
\wl_corse_cnt[0][0][1]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \corse_cnt_reg_n_0_[3][1]\,
      I1 => \corse_cnt_reg_n_0_[2][1]\,
      I2 => \^dqs_count_r_reg[1]_rep_0\,
      I3 => \corse_cnt_reg_n_0_[1][1]\,
      I4 => \^dqs_count_r_reg[0]_rep_0\,
      I5 => \corse_cnt_reg_n_0_[0][1]\,
      O => \wl_corse_cnt[0][0][1]_i_2_n_0\
    );
\wl_corse_cnt[0][0][1]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \corse_cnt_reg_n_0_[7][1]\,
      I1 => \corse_cnt_reg_n_0_[6][1]\,
      I2 => \^dqs_count_r_reg[1]_rep_0\,
      I3 => \corse_cnt_reg_n_0_[5][1]\,
      I4 => \^dqs_count_r_reg[0]_rep_0\,
      I5 => \corse_cnt_reg_n_0_[4][1]\,
      O => \wl_corse_cnt[0][0][1]_i_3_n_0\
    );
\wl_corse_cnt[0][0][2]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \corse_cnt_reg_n_0_[3][2]\,
      I1 => \corse_cnt_reg_n_0_[2][2]\,
      I2 => \^dqs_count_r_reg[1]_rep_0\,
      I3 => \corse_cnt_reg_n_0_[1][2]\,
      I4 => \^dqs_count_r_reg[0]_rep_0\,
      I5 => \corse_cnt_reg_n_0_[0][2]\,
      O => \wl_corse_cnt[0][0][2]_i_2_n_0\
    );
\wl_corse_cnt[0][0][2]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \corse_cnt_reg_n_0_[7][2]\,
      I1 => \corse_cnt_reg_n_0_[6][2]\,
      I2 => \^dqs_count_r_reg[1]_rep_0\,
      I3 => \corse_cnt_reg_n_0_[5][2]\,
      I4 => \^dqs_count_r_reg[0]_rep_0\,
      I5 => \corse_cnt_reg_n_0_[4][2]\,
      O => \wl_corse_cnt[0][0][2]_i_3_n_0\
    );
\wl_corse_cnt_reg[0][0][0]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => wl_corse_cnt,
      D => \wl_corse_cnt_reg[0][0][0]_i_1_n_0\,
      Q => \wl_corse_cnt_reg[0][0]_29\(0),
      R => \corse_inc_reg[6][2]_0\(1)
    );
\wl_corse_cnt_reg[0][0][0]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \wl_corse_cnt[0][0][0]_i_2_n_0\,
      I1 => \wl_corse_cnt[0][0][0]_i_3_n_0\,
      O => \wl_corse_cnt_reg[0][0][0]_i_1_n_0\,
      S => dqs_count_r(2)
    );
\wl_corse_cnt_reg[0][0][1]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => wl_corse_cnt,
      D => \wl_corse_cnt_reg[0][0][1]_i_1_n_0\,
      Q => \wl_corse_cnt_reg[0][0]_29\(1),
      R => \corse_inc_reg[6][2]_0\(1)
    );
\wl_corse_cnt_reg[0][0][1]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \wl_corse_cnt[0][0][1]_i_2_n_0\,
      I1 => \wl_corse_cnt[0][0][1]_i_3_n_0\,
      O => \wl_corse_cnt_reg[0][0][1]_i_1_n_0\,
      S => dqs_count_r(2)
    );
\wl_corse_cnt_reg[0][0][2]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => wl_corse_cnt,
      D => \wl_corse_cnt_reg[0][0][2]_i_1_n_0\,
      Q => \wl_corse_cnt_reg[0][0]_29\(2),
      R => \corse_inc_reg[6][2]_0\(1)
    );
\wl_corse_cnt_reg[0][0][2]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \wl_corse_cnt[0][0][2]_i_2_n_0\,
      I1 => \wl_corse_cnt[0][0][2]_i_3_n_0\,
      O => \wl_corse_cnt_reg[0][0][2]_i_1_n_0\,
      S => dqs_count_r(2)
    );
\wl_corse_cnt_reg[0][1][0]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => \wl_dqs_tap_count_r[0][1][5]_i_1_n_0\,
      D => \wl_corse_cnt_reg[0][0][0]_i_1_n_0\,
      Q => \wl_corse_cnt_reg[0][1]_30\(0),
      R => \wl_dqs_tap_count_r_reg[0][5][5]_0\
    );
\wl_corse_cnt_reg[0][1][1]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => \wl_dqs_tap_count_r[0][1][5]_i_1_n_0\,
      D => \wl_corse_cnt_reg[0][0][1]_i_1_n_0\,
      Q => \wl_corse_cnt_reg[0][1]_30\(1),
      R => \wl_dqs_tap_count_r_reg[0][5][5]_0\
    );
\wl_corse_cnt_reg[0][1][2]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => \wl_dqs_tap_count_r[0][1][5]_i_1_n_0\,
      D => \wl_corse_cnt_reg[0][0][2]_i_1_n_0\,
      Q => \wl_corse_cnt_reg[0][1]_30\(2),
      R => \wl_dqs_tap_count_r_reg[0][5][5]_0\
    );
\wl_corse_cnt_reg[0][2][0]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => \wl_dqs_tap_count_r[0][2][5]_i_1_n_0\,
      D => \wl_corse_cnt_reg[0][0][0]_i_1_n_0\,
      Q => \wl_corse_cnt_reg[0][2]_31\(0),
      R => \corse_inc_reg[6][2]_0\(1)
    );
\wl_corse_cnt_reg[0][2][1]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => \wl_dqs_tap_count_r[0][2][5]_i_1_n_0\,
      D => \wl_corse_cnt_reg[0][0][1]_i_1_n_0\,
      Q => \wl_corse_cnt_reg[0][2]_31\(1),
      R => \corse_inc_reg[6][2]_0\(1)
    );
\wl_corse_cnt_reg[0][2][2]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => \wl_dqs_tap_count_r[0][2][5]_i_1_n_0\,
      D => \wl_corse_cnt_reg[0][0][2]_i_1_n_0\,
      Q => \wl_corse_cnt_reg[0][2]_31\(2),
      R => \corse_inc_reg[6][2]_0\(1)
    );
\wl_corse_cnt_reg[0][3][0]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => \wl_dqs_tap_count_r[0][3][5]_i_1_n_0\,
      D => \wl_corse_cnt_reg[0][0][0]_i_1_n_0\,
      Q => \wl_corse_cnt_reg[0][3]_32\(0),
      R => \wl_dqs_tap_count_r_reg[0][5][5]_0\
    );
\wl_corse_cnt_reg[0][3][1]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => \wl_dqs_tap_count_r[0][3][5]_i_1_n_0\,
      D => \wl_corse_cnt_reg[0][0][1]_i_1_n_0\,
      Q => \wl_corse_cnt_reg[0][3]_32\(1),
      R => \wl_dqs_tap_count_r_reg[0][5][5]_0\
    );
\wl_corse_cnt_reg[0][3][2]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => \wl_dqs_tap_count_r[0][3][5]_i_1_n_0\,
      D => \wl_corse_cnt_reg[0][0][2]_i_1_n_0\,
      Q => \wl_corse_cnt_reg[0][3]_32\(2),
      R => \wl_dqs_tap_count_r_reg[0][5][5]_0\
    );
\wl_corse_cnt_reg[0][4][0]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => \wl_dqs_tap_count_r[0][4][5]_i_1_n_0\,
      D => \wl_corse_cnt_reg[0][0][0]_i_1_n_0\,
      Q => \wl_corse_cnt_reg[0][4]_33\(0),
      R => \corse_inc_reg[6][2]_0\(1)
    );
\wl_corse_cnt_reg[0][4][1]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => \wl_dqs_tap_count_r[0][4][5]_i_1_n_0\,
      D => \wl_corse_cnt_reg[0][0][1]_i_1_n_0\,
      Q => \wl_corse_cnt_reg[0][4]_33\(1),
      R => \corse_inc_reg[6][2]_0\(1)
    );
\wl_corse_cnt_reg[0][4][2]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => \wl_dqs_tap_count_r[0][4][5]_i_1_n_0\,
      D => \wl_corse_cnt_reg[0][0][2]_i_1_n_0\,
      Q => \wl_corse_cnt_reg[0][4]_33\(2),
      R => \corse_inc_reg[6][2]_0\(1)
    );
\wl_corse_cnt_reg[0][5][0]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => \wl_dqs_tap_count_r[0][5][5]_i_1_n_0\,
      D => \wl_corse_cnt_reg[0][0][0]_i_1_n_0\,
      Q => \wl_corse_cnt_reg[0][5]_34\(0),
      R => \wl_dqs_tap_count_r_reg[0][5][5]_0\
    );
\wl_corse_cnt_reg[0][5][1]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => \wl_dqs_tap_count_r[0][5][5]_i_1_n_0\,
      D => \wl_corse_cnt_reg[0][0][1]_i_1_n_0\,
      Q => \wl_corse_cnt_reg[0][5]_34\(1),
      R => \wl_dqs_tap_count_r_reg[0][5][5]_0\
    );
\wl_corse_cnt_reg[0][5][2]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => \wl_dqs_tap_count_r[0][5][5]_i_1_n_0\,
      D => \wl_corse_cnt_reg[0][0][2]_i_1_n_0\,
      Q => \wl_corse_cnt_reg[0][5]_34\(2),
      R => \wl_dqs_tap_count_r_reg[0][5][5]_0\
    );
\wl_corse_cnt_reg[0][6][0]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => \wl_dqs_tap_count_r[0][6][5]_i_1_n_0\,
      D => \wl_corse_cnt_reg[0][0][0]_i_1_n_0\,
      Q => \wl_corse_cnt_reg[0][6]_35\(0),
      R => \corse_inc_reg[6][2]_0\(0)
    );
\wl_corse_cnt_reg[0][6][1]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => \wl_dqs_tap_count_r[0][6][5]_i_1_n_0\,
      D => \wl_corse_cnt_reg[0][0][1]_i_1_n_0\,
      Q => \wl_corse_cnt_reg[0][6]_35\(1),
      R => \corse_inc_reg[6][2]_0\(0)
    );
\wl_corse_cnt_reg[0][6][2]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => \wl_dqs_tap_count_r[0][6][5]_i_1_n_0\,
      D => \wl_corse_cnt_reg[0][0][2]_i_1_n_0\,
      Q => \wl_corse_cnt_reg[0][6]_35\(2),
      R => \corse_inc_reg[6][2]_0\(1)
    );
\wl_corse_cnt_reg[0][7][0]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => \wl_dqs_tap_count_r[0][7][5]_i_1_n_0\,
      D => \wl_corse_cnt_reg[0][0][0]_i_1_n_0\,
      Q => \wl_corse_cnt_reg[0][7]_36\(0),
      R => \wl_dqs_tap_count_r_reg[0][5][5]_0\
    );
\wl_corse_cnt_reg[0][7][1]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => \wl_dqs_tap_count_r[0][7][5]_i_1_n_0\,
      D => \wl_corse_cnt_reg[0][0][1]_i_1_n_0\,
      Q => \wl_corse_cnt_reg[0][7]_36\(1),
      R => \wl_dqs_tap_count_r_reg[0][5][5]_0\
    );
\wl_corse_cnt_reg[0][7][2]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => \wl_dqs_tap_count_r[0][7][5]_i_1_n_0\,
      D => \wl_corse_cnt_reg[0][0][2]_i_1_n_0\,
      Q => \wl_corse_cnt_reg[0][7]_36\(2),
      R => \wl_dqs_tap_count_r_reg[0][5][5]_0\
    );
\wl_dqs_tap_count_r[0][0][5]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00010000"
    )
        port map (
      I0 => \^dqs_count_r_reg[3]_0\(0),
      I1 => \dqs_count_r_reg[2]_rep_n_0\,
      I2 => dqs_count_r(1),
      I3 => dqs_count_r(0),
      I4 => \wl_dqs_tap_count_r[0][0][5]_i_2_n_0\,
      O => wl_corse_cnt
    );
\wl_dqs_tap_count_r[0][0][5]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000000220A0"
    )
        port map (
      I0 => \wl_dqs_tap_count_r[0][0][5]_i_3_n_0\,
      I1 => \^fsm_sequential_wl_state_r_reg[4]_0\(1),
      I2 => \wl_state_r__0\(2),
      I3 => \wl_state_r__0\(1),
      I4 => \wl_state_r__0\(0),
      I5 => \^fsm_sequential_wl_state_r_reg[4]_0\(0),
      O => \wl_dqs_tap_count_r[0][0][5]_i_2_n_0\
    );
\wl_dqs_tap_count_r[0][0][5]_i_3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \rank_cnt_r_reg_n_0_[0]\,
      I1 => \rank_cnt_r_reg_n_0_[1]\,
      O => \wl_dqs_tap_count_r[0][0][5]_i_3_n_0\
    );
\wl_dqs_tap_count_r[0][1][5]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000200"
    )
        port map (
      I0 => \wl_dqs_tap_count_r[0][0][5]_i_2_n_0\,
      I1 => \^dqs_count_r_reg[3]_0\(0),
      I2 => \dqs_count_r_reg[2]_rep_n_0\,
      I3 => dqs_count_r(0),
      I4 => dqs_count_r(1),
      O => \wl_dqs_tap_count_r[0][1][5]_i_1_n_0\
    );
\wl_dqs_tap_count_r[0][2][5]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000200"
    )
        port map (
      I0 => \wl_dqs_tap_count_r[0][0][5]_i_2_n_0\,
      I1 => \^dqs_count_r_reg[3]_0\(0),
      I2 => \dqs_count_r_reg[2]_rep_n_0\,
      I3 => dqs_count_r(1),
      I4 => dqs_count_r(0),
      O => \wl_dqs_tap_count_r[0][2][5]_i_1_n_0\
    );
\wl_dqs_tap_count_r[0][3][5]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000080"
    )
        port map (
      I0 => \wl_dqs_tap_count_r[0][0][5]_i_2_n_0\,
      I1 => dqs_count_r(1),
      I2 => dqs_count_r(0),
      I3 => \^dqs_count_r_reg[3]_0\(0),
      I4 => \dqs_count_r_reg[2]_rep_n_0\,
      O => \wl_dqs_tap_count_r[0][3][5]_i_1_n_0\
    );
\wl_dqs_tap_count_r[0][4][5]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000020"
    )
        port map (
      I0 => \wl_dqs_tap_count_r[0][0][5]_i_2_n_0\,
      I1 => \^dqs_count_r_reg[3]_0\(0),
      I2 => \dqs_count_r_reg[2]_rep_n_0\,
      I3 => dqs_count_r(1),
      I4 => dqs_count_r(0),
      O => \wl_dqs_tap_count_r[0][4][5]_i_1_n_0\
    );
\wl_dqs_tap_count_r[0][5][5]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00002000"
    )
        port map (
      I0 => \wl_dqs_tap_count_r[0][0][5]_i_2_n_0\,
      I1 => \^dqs_count_r_reg[3]_0\(0),
      I2 => \dqs_count_r_reg[2]_rep_n_0\,
      I3 => dqs_count_r(0),
      I4 => dqs_count_r(1),
      O => \wl_dqs_tap_count_r[0][5][5]_i_1_n_0\
    );
\wl_dqs_tap_count_r[0][6][5]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00002000"
    )
        port map (
      I0 => \wl_dqs_tap_count_r[0][0][5]_i_2_n_0\,
      I1 => \^dqs_count_r_reg[3]_0\(0),
      I2 => \dqs_count_r_reg[2]_rep_n_0\,
      I3 => dqs_count_r(1),
      I4 => dqs_count_r(0),
      O => \wl_dqs_tap_count_r[0][6][5]_i_1_n_0\
    );
\wl_dqs_tap_count_r[0][7][5]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00008000"
    )
        port map (
      I0 => \wl_dqs_tap_count_r[0][0][5]_i_2_n_0\,
      I1 => dqs_count_r(0),
      I2 => dqs_count_r(1),
      I3 => \dqs_count_r_reg[2]_rep_n_0\,
      I4 => \^dqs_count_r_reg[3]_0\(0),
      O => \wl_dqs_tap_count_r[0][7][5]_i_1_n_0\
    );
\wl_dqs_tap_count_r_reg[0][0][0]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => wl_corse_cnt,
      D => \wl_tap_count_r_reg_n_0_[0]\,
      Q => \wl_dqs_tap_count_r_reg_n_0_[0][0][0]\,
      R => \fine_inc_reg[6][3]_0\(0)
    );
\wl_dqs_tap_count_r_reg[0][0][1]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => wl_corse_cnt,
      D => \wl_tap_count_r_reg_n_0_[1]\,
      Q => \wl_dqs_tap_count_r_reg_n_0_[0][0][1]\,
      R => \fine_inc_reg[6][3]_0\(0)
    );
\wl_dqs_tap_count_r_reg[0][0][2]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => wl_corse_cnt,
      D => \wl_tap_count_r_reg_n_0_[2]\,
      Q => \wl_dqs_tap_count_r_reg_n_0_[0][0][2]\,
      R => \fine_inc_reg[6][3]_0\(0)
    );
\wl_dqs_tap_count_r_reg[0][0][3]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => wl_corse_cnt,
      D => \wl_tap_count_r_reg_n_0_[3]\,
      Q => \wl_dqs_tap_count_r_reg_n_0_[0][0][3]\,
      R => \fine_inc_reg[6][3]_0\(0)
    );
\wl_dqs_tap_count_r_reg[0][0][4]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => wl_corse_cnt,
      D => \wl_tap_count_r_reg_n_0_[4]\,
      Q => \wl_dqs_tap_count_r_reg_n_0_[0][0][4]\,
      R => \fine_inc_reg[6][3]_0\(0)
    );
\wl_dqs_tap_count_r_reg[0][0][5]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => wl_corse_cnt,
      D => \wl_tap_count_r_reg_n_0_[5]\,
      Q => \wl_dqs_tap_count_r_reg_n_0_[0][0][5]\,
      R => \fine_inc_reg[6][3]_0\(0)
    );
\wl_dqs_tap_count_r_reg[0][1][0]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => \wl_dqs_tap_count_r[0][1][5]_i_1_n_0\,
      D => \wl_tap_count_r_reg_n_0_[0]\,
      Q => \wl_dqs_tap_count_r_reg_n_0_[0][1][0]\,
      R => \fine_inc_reg[6][3]_0\(1)
    );
\wl_dqs_tap_count_r_reg[0][1][1]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => \wl_dqs_tap_count_r[0][1][5]_i_1_n_0\,
      D => \wl_tap_count_r_reg_n_0_[1]\,
      Q => \wl_dqs_tap_count_r_reg_n_0_[0][1][1]\,
      R => \fine_inc_reg[6][3]_0\(1)
    );
\wl_dqs_tap_count_r_reg[0][1][2]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => \wl_dqs_tap_count_r[0][1][5]_i_1_n_0\,
      D => \wl_tap_count_r_reg_n_0_[2]\,
      Q => \wl_dqs_tap_count_r_reg_n_0_[0][1][2]\,
      R => \fine_inc_reg[6][3]_0\(1)
    );
\wl_dqs_tap_count_r_reg[0][1][3]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => \wl_dqs_tap_count_r[0][1][5]_i_1_n_0\,
      D => \wl_tap_count_r_reg_n_0_[3]\,
      Q => \wl_dqs_tap_count_r_reg_n_0_[0][1][3]\,
      R => \fine_inc_reg[6][3]_0\(1)
    );
\wl_dqs_tap_count_r_reg[0][1][4]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => \wl_dqs_tap_count_r[0][1][5]_i_1_n_0\,
      D => \wl_tap_count_r_reg_n_0_[4]\,
      Q => \wl_dqs_tap_count_r_reg_n_0_[0][1][4]\,
      R => \fine_inc_reg[6][3]_0\(0)
    );
\wl_dqs_tap_count_r_reg[0][1][5]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => \wl_dqs_tap_count_r[0][1][5]_i_1_n_0\,
      D => \wl_tap_count_r_reg_n_0_[5]\,
      Q => \wl_dqs_tap_count_r_reg_n_0_[0][1][5]\,
      R => \fine_inc_reg[6][3]_0\(0)
    );
\wl_dqs_tap_count_r_reg[0][2][0]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => \wl_dqs_tap_count_r[0][2][5]_i_1_n_0\,
      D => \wl_tap_count_r_reg_n_0_[0]\,
      Q => \wl_dqs_tap_count_r_reg_n_0_[0][2][0]\,
      R => \fine_inc_reg[6][3]_0\(0)
    );
\wl_dqs_tap_count_r_reg[0][2][1]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => \wl_dqs_tap_count_r[0][2][5]_i_1_n_0\,
      D => \wl_tap_count_r_reg_n_0_[1]\,
      Q => \wl_dqs_tap_count_r_reg_n_0_[0][2][1]\,
      R => \fine_inc_reg[6][3]_0\(0)
    );
\wl_dqs_tap_count_r_reg[0][2][2]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => \wl_dqs_tap_count_r[0][2][5]_i_1_n_0\,
      D => \wl_tap_count_r_reg_n_0_[2]\,
      Q => \wl_dqs_tap_count_r_reg_n_0_[0][2][2]\,
      R => \fine_inc_reg[6][3]_0\(0)
    );
\wl_dqs_tap_count_r_reg[0][2][3]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => \wl_dqs_tap_count_r[0][2][5]_i_1_n_0\,
      D => \wl_tap_count_r_reg_n_0_[3]\,
      Q => \wl_dqs_tap_count_r_reg_n_0_[0][2][3]\,
      R => \fine_inc_reg[6][3]_0\(0)
    );
\wl_dqs_tap_count_r_reg[0][2][4]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => \wl_dqs_tap_count_r[0][2][5]_i_1_n_0\,
      D => \wl_tap_count_r_reg_n_0_[4]\,
      Q => \wl_dqs_tap_count_r_reg_n_0_[0][2][4]\,
      R => \fine_inc_reg[6][3]_0\(0)
    );
\wl_dqs_tap_count_r_reg[0][2][5]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => \wl_dqs_tap_count_r[0][2][5]_i_1_n_0\,
      D => \wl_tap_count_r_reg_n_0_[5]\,
      Q => \wl_dqs_tap_count_r_reg_n_0_[0][2][5]\,
      R => \fine_inc_reg[6][3]_0\(0)
    );
\wl_dqs_tap_count_r_reg[0][3][0]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => \wl_dqs_tap_count_r[0][3][5]_i_1_n_0\,
      D => \wl_tap_count_r_reg_n_0_[0]\,
      Q => \wl_dqs_tap_count_r_reg_n_0_[0][3][0]\,
      R => \fine_inc_reg[6][3]_0\(1)
    );
\wl_dqs_tap_count_r_reg[0][3][1]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => \wl_dqs_tap_count_r[0][3][5]_i_1_n_0\,
      D => \wl_tap_count_r_reg_n_0_[1]\,
      Q => \wl_dqs_tap_count_r_reg_n_0_[0][3][1]\,
      R => \fine_inc_reg[6][3]_0\(1)
    );
\wl_dqs_tap_count_r_reg[0][3][2]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => \wl_dqs_tap_count_r[0][3][5]_i_1_n_0\,
      D => \wl_tap_count_r_reg_n_0_[2]\,
      Q => \wl_dqs_tap_count_r_reg_n_0_[0][3][2]\,
      R => \fine_inc_reg[6][3]_0\(1)
    );
\wl_dqs_tap_count_r_reg[0][3][3]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => \wl_dqs_tap_count_r[0][3][5]_i_1_n_0\,
      D => \wl_tap_count_r_reg_n_0_[3]\,
      Q => \wl_dqs_tap_count_r_reg_n_0_[0][3][3]\,
      R => \fine_inc_reg[6][3]_0\(1)
    );
\wl_dqs_tap_count_r_reg[0][3][4]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => \wl_dqs_tap_count_r[0][3][5]_i_1_n_0\,
      D => \wl_tap_count_r_reg_n_0_[4]\,
      Q => \wl_dqs_tap_count_r_reg_n_0_[0][3][4]\,
      R => \fine_inc_reg[6][3]_0\(1)
    );
\wl_dqs_tap_count_r_reg[0][3][5]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => \wl_dqs_tap_count_r[0][3][5]_i_1_n_0\,
      D => \wl_tap_count_r_reg_n_0_[5]\,
      Q => \wl_dqs_tap_count_r_reg_n_0_[0][3][5]\,
      R => \fine_inc_reg[6][3]_0\(1)
    );
\wl_dqs_tap_count_r_reg[0][4][0]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => \wl_dqs_tap_count_r[0][4][5]_i_1_n_0\,
      D => \wl_tap_count_r_reg_n_0_[0]\,
      Q => \wl_dqs_tap_count_r_reg_n_0_[0][4][0]\,
      R => \fine_inc_reg[6][3]_0\(0)
    );
\wl_dqs_tap_count_r_reg[0][4][1]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => \wl_dqs_tap_count_r[0][4][5]_i_1_n_0\,
      D => \wl_tap_count_r_reg_n_0_[1]\,
      Q => \wl_dqs_tap_count_r_reg_n_0_[0][4][1]\,
      R => \fine_inc_reg[6][3]_0\(0)
    );
\wl_dqs_tap_count_r_reg[0][4][2]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => \wl_dqs_tap_count_r[0][4][5]_i_1_n_0\,
      D => \wl_tap_count_r_reg_n_0_[2]\,
      Q => \wl_dqs_tap_count_r_reg_n_0_[0][4][2]\,
      R => \fine_inc_reg[6][3]_0\(0)
    );
\wl_dqs_tap_count_r_reg[0][4][3]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => \wl_dqs_tap_count_r[0][4][5]_i_1_n_0\,
      D => \wl_tap_count_r_reg_n_0_[3]\,
      Q => \wl_dqs_tap_count_r_reg_n_0_[0][4][3]\,
      R => \fine_inc_reg[6][3]_0\(0)
    );
\wl_dqs_tap_count_r_reg[0][4][4]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => \wl_dqs_tap_count_r[0][4][5]_i_1_n_0\,
      D => \wl_tap_count_r_reg_n_0_[4]\,
      Q => \wl_dqs_tap_count_r_reg_n_0_[0][4][4]\,
      R => \fine_inc_reg[6][3]_0\(0)
    );
\wl_dqs_tap_count_r_reg[0][4][5]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => \wl_dqs_tap_count_r[0][4][5]_i_1_n_0\,
      D => \wl_tap_count_r_reg_n_0_[5]\,
      Q => \wl_dqs_tap_count_r_reg_n_0_[0][4][5]\,
      R => \fine_inc_reg[6][3]_0\(0)
    );
\wl_dqs_tap_count_r_reg[0][5][0]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => \wl_dqs_tap_count_r[0][5][5]_i_1_n_0\,
      D => \wl_tap_count_r_reg_n_0_[0]\,
      Q => \wl_dqs_tap_count_r_reg_n_0_[0][5][0]\,
      R => \wl_dqs_tap_count_r_reg[0][5][5]_0\
    );
\wl_dqs_tap_count_r_reg[0][5][1]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => \wl_dqs_tap_count_r[0][5][5]_i_1_n_0\,
      D => \wl_tap_count_r_reg_n_0_[1]\,
      Q => \wl_dqs_tap_count_r_reg_n_0_[0][5][1]\,
      R => \wl_dqs_tap_count_r_reg[0][5][5]_0\
    );
\wl_dqs_tap_count_r_reg[0][5][2]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => \wl_dqs_tap_count_r[0][5][5]_i_1_n_0\,
      D => \wl_tap_count_r_reg_n_0_[2]\,
      Q => \wl_dqs_tap_count_r_reg_n_0_[0][5][2]\,
      R => \wl_dqs_tap_count_r_reg[0][5][5]_0\
    );
\wl_dqs_tap_count_r_reg[0][5][3]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => \wl_dqs_tap_count_r[0][5][5]_i_1_n_0\,
      D => \wl_tap_count_r_reg_n_0_[3]\,
      Q => \wl_dqs_tap_count_r_reg_n_0_[0][5][3]\,
      R => \wl_dqs_tap_count_r_reg[0][5][5]_0\
    );
\wl_dqs_tap_count_r_reg[0][5][4]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => \wl_dqs_tap_count_r[0][5][5]_i_1_n_0\,
      D => \wl_tap_count_r_reg_n_0_[4]\,
      Q => \wl_dqs_tap_count_r_reg_n_0_[0][5][4]\,
      R => \wl_dqs_tap_count_r_reg[0][5][5]_0\
    );
\wl_dqs_tap_count_r_reg[0][5][5]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => \wl_dqs_tap_count_r[0][5][5]_i_1_n_0\,
      D => \wl_tap_count_r_reg_n_0_[5]\,
      Q => \wl_dqs_tap_count_r_reg_n_0_[0][5][5]\,
      R => \wl_dqs_tap_count_r_reg[0][5][5]_0\
    );
\wl_dqs_tap_count_r_reg[0][6][0]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => \wl_dqs_tap_count_r[0][6][5]_i_1_n_0\,
      D => \wl_tap_count_r_reg_n_0_[0]\,
      Q => \wl_dqs_tap_count_r_reg_n_0_[0][6][0]\,
      R => \corse_dec_reg[7][0]_0\(0)
    );
\wl_dqs_tap_count_r_reg[0][6][1]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => \wl_dqs_tap_count_r[0][6][5]_i_1_n_0\,
      D => \wl_tap_count_r_reg_n_0_[1]\,
      Q => \wl_dqs_tap_count_r_reg_n_0_[0][6][1]\,
      R => \corse_dec_reg[7][0]_0\(1)
    );
\wl_dqs_tap_count_r_reg[0][6][2]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => \wl_dqs_tap_count_r[0][6][5]_i_1_n_0\,
      D => \wl_tap_count_r_reg_n_0_[2]\,
      Q => \wl_dqs_tap_count_r_reg_n_0_[0][6][2]\,
      R => \corse_dec_reg[7][0]_0\(1)
    );
\wl_dqs_tap_count_r_reg[0][6][3]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => \wl_dqs_tap_count_r[0][6][5]_i_1_n_0\,
      D => \wl_tap_count_r_reg_n_0_[3]\,
      Q => \wl_dqs_tap_count_r_reg_n_0_[0][6][3]\,
      R => \fine_inc_reg[6][3]_0\(0)
    );
\wl_dqs_tap_count_r_reg[0][6][4]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => \wl_dqs_tap_count_r[0][6][5]_i_1_n_0\,
      D => \wl_tap_count_r_reg_n_0_[4]\,
      Q => \wl_dqs_tap_count_r_reg_n_0_[0][6][4]\,
      R => \fine_inc_reg[6][3]_0\(0)
    );
\wl_dqs_tap_count_r_reg[0][6][5]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => \wl_dqs_tap_count_r[0][6][5]_i_1_n_0\,
      D => \wl_tap_count_r_reg_n_0_[5]\,
      Q => \wl_dqs_tap_count_r_reg_n_0_[0][6][5]\,
      R => \fine_inc_reg[6][3]_0\(0)
    );
\wl_dqs_tap_count_r_reg[0][7][0]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => \wl_dqs_tap_count_r[0][7][5]_i_1_n_0\,
      D => \wl_tap_count_r_reg_n_0_[0]\,
      Q => \wl_dqs_tap_count_r_reg_n_0_[0][7][0]\,
      R => \wl_dqs_tap_count_r_reg[0][5][5]_0\
    );
\wl_dqs_tap_count_r_reg[0][7][1]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => \wl_dqs_tap_count_r[0][7][5]_i_1_n_0\,
      D => \wl_tap_count_r_reg_n_0_[1]\,
      Q => \wl_dqs_tap_count_r_reg_n_0_[0][7][1]\,
      R => \wl_dqs_tap_count_r_reg[0][5][5]_0\
    );
\wl_dqs_tap_count_r_reg[0][7][2]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => \wl_dqs_tap_count_r[0][7][5]_i_1_n_0\,
      D => \wl_tap_count_r_reg_n_0_[2]\,
      Q => \wl_dqs_tap_count_r_reg_n_0_[0][7][2]\,
      R => \wl_dqs_tap_count_r_reg[0][5][5]_0\
    );
\wl_dqs_tap_count_r_reg[0][7][3]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => \wl_dqs_tap_count_r[0][7][5]_i_1_n_0\,
      D => \wl_tap_count_r_reg_n_0_[3]\,
      Q => \wl_dqs_tap_count_r_reg_n_0_[0][7][3]\,
      R => \wl_dqs_tap_count_r_reg[0][5][5]_0\
    );
\wl_dqs_tap_count_r_reg[0][7][4]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => \wl_dqs_tap_count_r[0][7][5]_i_1_n_0\,
      D => \wl_tap_count_r_reg_n_0_[4]\,
      Q => \wl_dqs_tap_count_r_reg_n_0_[0][7][4]\,
      R => \wl_dqs_tap_count_r_reg[0][5][5]_0\
    );
\wl_dqs_tap_count_r_reg[0][7][5]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => \wl_dqs_tap_count_r[0][7][5]_i_1_n_0\,
      D => \wl_tap_count_r_reg_n_0_[5]\,
      Q => \wl_dqs_tap_count_r_reg_n_0_[0][7][5]\,
      R => \wl_dqs_tap_count_r_reg[0][5][5]_0\
    );
wl_edge_detect_valid_r_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AEAAAA2AA88AA8A8"
    )
        port map (
      I0 => wl_edge_detect_valid_r_reg_n_0,
      I1 => \^fsm_sequential_wl_state_r_reg[4]_0\(0),
      I2 => \wl_state_r__0\(2),
      I3 => \wl_state_r__0\(1),
      I4 => \^fsm_sequential_wl_state_r_reg[4]_0\(1),
      I5 => \wl_state_r__0\(0),
      O => wl_edge_detect_valid_r_i_1_n_0
    );
wl_edge_detect_valid_r_reg: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => '1',
      D => wl_edge_detect_valid_r_i_1_n_0,
      Q => wl_edge_detect_valid_r_reg_n_0,
      R => \wl_dqs_tap_count_r_reg[0][5][5]_0\
    );
\wl_state_r1[0]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"9293ADAE"
    )
        port map (
      I0 => \^fsm_sequential_wl_state_r_reg[4]_0\(1),
      I1 => \wl_state_r__0\(1),
      I2 => \wl_state_r__0\(0),
      I3 => \^fsm_sequential_wl_state_r_reg[4]_0\(0),
      I4 => \wl_state_r__0\(2),
      O => \wl_state_r1[0]_i_1_n_0\
    );
\wl_state_r1[1]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"04FF0C3F"
    )
        port map (
      I0 => \^fsm_sequential_wl_state_r_reg[4]_0\(1),
      I1 => \wl_state_r__0\(0),
      I2 => \^fsm_sequential_wl_state_r_reg[4]_0\(0),
      I3 => \wl_state_r__0\(1),
      I4 => \wl_state_r__0\(2),
      O => \wl_state_r1[1]_i_1_n_0\
    );
\wl_state_r1[2]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"37D83005"
    )
        port map (
      I0 => \wl_state_r__0\(2),
      I1 => \wl_state_r__0\(1),
      I2 => \^fsm_sequential_wl_state_r_reg[4]_0\(0),
      I3 => \wl_state_r__0\(0),
      I4 => \^fsm_sequential_wl_state_r_reg[4]_0\(1),
      O => \wl_state_r1[2]_i_1_n_0\
    );
\wl_state_r1[3]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"C2808775"
    )
        port map (
      I0 => \wl_state_r__0\(2),
      I1 => \wl_state_r__0\(0),
      I2 => \wl_state_r__0\(1),
      I3 => \^fsm_sequential_wl_state_r_reg[4]_0\(1),
      I4 => \^fsm_sequential_wl_state_r_reg[4]_0\(0),
      O => \wl_state_r1[3]_i_1_n_0\
    );
\wl_state_r1[4]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"DEC5E214"
    )
        port map (
      I0 => \^fsm_sequential_wl_state_r_reg[4]_0\(0),
      I1 => \wl_state_r__0\(2),
      I2 => \^fsm_sequential_wl_state_r_reg[4]_0\(1),
      I3 => \wl_state_r__0\(1),
      I4 => \wl_state_r__0\(0),
      O => \wl_state_r1[4]_i_1_n_0\
    );
\wl_state_r1_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => '1',
      D => \wl_state_r1[0]_i_1_n_0\,
      Q => \wl_state_r1_reg_n_0_[0]\,
      R => \corse_inc_reg[6][2]_0\(0)
    );
\wl_state_r1_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => '1',
      D => \wl_state_r1[1]_i_1_n_0\,
      Q => \wl_state_r1_reg_n_0_[1]\,
      R => \corse_inc_reg[6][2]_0\(0)
    );
\wl_state_r1_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => '1',
      D => \wl_state_r1[2]_i_1_n_0\,
      Q => \wl_state_r1_reg_n_0_[2]\,
      R => \corse_inc_reg[6][2]_0\(0)
    );
\wl_state_r1_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => '1',
      D => \wl_state_r1[3]_i_1_n_0\,
      Q => \wl_state_r1_reg_n_0_[3]\,
      R => \corse_inc_reg[6][2]_0\(0)
    );
\wl_state_r1_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => '1',
      D => \wl_state_r1[4]_i_1_n_0\,
      Q => \wl_state_r1_reg_n_0_[4]\,
      R => \corse_inc_reg[6][2]_0\(0)
    );
\wl_tap_count_r[0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"80808080808C8C8C"
    )
        port map (
      I0 => \wl_tap_count_r_reg[0]_i_2_n_0\,
      I1 => \wl_tap_count_r[4]_i_4_n_0\,
      I2 => \wl_state_r__0\(1),
      I3 => \^wr_level_done_r5\,
      I4 => \wl_state_r__0\(0),
      I5 => \wl_tap_count_r_reg_n_0_[0]\,
      O => wl_tap_count_r(0)
    );
\wl_tap_count_r[0]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \smallest_reg[3]_16\(0),
      I1 => \smallest_reg[2]_15\(0),
      I2 => \dqs_count_r_reg[3]_1\(1),
      I3 => \smallest_reg[1]_14\(0),
      I4 => \dqs_count_r_reg[3]_1\(0),
      I5 => \smallest_reg[0]_13\(0),
      O => \wl_tap_count_r[0]_i_3_n_0\
    );
\wl_tap_count_r[0]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \smallest_reg[7]_20\(0),
      I1 => \smallest_reg[6]_19\(0),
      I2 => \dqs_count_r_reg[3]_1\(1),
      I3 => \smallest_reg[5]_18\(0),
      I4 => \dqs_count_r_reg[3]_1\(0),
      I5 => \smallest_reg[4]_17\(0),
      O => \wl_tap_count_r[0]_i_4_n_0\
    );
\wl_tap_count_r[1]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"80808080808C8C80"
    )
        port map (
      I0 => \wl_tap_count_r_reg[1]_i_2_n_0\,
      I1 => \wl_tap_count_r[4]_i_4_n_0\,
      I2 => \wl_state_r__0\(1),
      I3 => \wl_tap_count_r_reg_n_0_[0]\,
      I4 => \wl_tap_count_r_reg_n_0_[1]\,
      I5 => \wl_tap_count_r[4]_i_2_n_0\,
      O => wl_tap_count_r(1)
    );
\wl_tap_count_r[1]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \smallest_reg[3]_16\(1),
      I1 => \smallest_reg[2]_15\(1),
      I2 => \dqs_count_r_reg[3]_1\(1),
      I3 => \smallest_reg[1]_14\(1),
      I4 => \dqs_count_r_reg[3]_1\(0),
      I5 => \smallest_reg[0]_13\(1),
      O => \wl_tap_count_r[1]_i_3_n_0\
    );
\wl_tap_count_r[1]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \smallest_reg[7]_20\(1),
      I1 => \smallest_reg[6]_19\(1),
      I2 => \dqs_count_r_reg[3]_1\(1),
      I3 => \smallest_reg[5]_18\(1),
      I4 => \dqs_count_r_reg[3]_1\(0),
      I5 => \smallest_reg[4]_17\(1),
      O => \wl_tap_count_r[1]_i_4_n_0\
    );
\wl_tap_count_r[2]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00008A00"
    )
        port map (
      I0 => \wl_tap_count_r[2]_i_2_n_0\,
      I1 => \wl_tap_count_r_reg[2]_i_3_n_0\,
      I2 => \wl_state_r__0\(1),
      I3 => \^fsm_sequential_wl_state_r_reg[4]_0\(0),
      I4 => \^fsm_sequential_wl_state_r_reg[4]_0\(1),
      O => wl_tap_count_r(2)
    );
\wl_tap_count_r[2]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAABEEEBEEEBEEE"
    )
        port map (
      I0 => \wl_state_r__0\(1),
      I1 => \wl_tap_count_r_reg_n_0_[2]\,
      I2 => \wl_tap_count_r_reg_n_0_[0]\,
      I3 => \wl_tap_count_r_reg_n_0_[1]\,
      I4 => \wl_state_r__0\(0),
      I5 => \^wr_level_done_r5\,
      O => \wl_tap_count_r[2]_i_2_n_0\
    );
\wl_tap_count_r[2]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \smallest_reg[3]_16\(2),
      I1 => \smallest_reg[2]_15\(2),
      I2 => \dqs_count_r_reg[3]_1\(1),
      I3 => \smallest_reg[1]_14\(2),
      I4 => \dqs_count_r_reg[3]_1\(0),
      I5 => \smallest_reg[0]_13\(2),
      O => \wl_tap_count_r[2]_i_4_n_0\
    );
\wl_tap_count_r[2]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \smallest_reg[7]_20\(2),
      I1 => \smallest_reg[6]_19\(2),
      I2 => \dqs_count_r_reg[3]_1\(1),
      I3 => \smallest_reg[5]_18\(2),
      I4 => \dqs_count_r_reg[3]_1\(0),
      I5 => \smallest_reg[4]_17\(2),
      O => \wl_tap_count_r[2]_i_5_n_0\
    );
\wl_tap_count_r[3]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"80808080808C8C80"
    )
        port map (
      I0 => \wl_tap_count_r_reg[3]_i_2_n_0\,
      I1 => \wl_tap_count_r[4]_i_4_n_0\,
      I2 => \wl_state_r__0\(1),
      I3 => \wl_tap_count_r_reg_n_0_[3]\,
      I4 => \wl_tap_count_r[3]_i_3_n_0\,
      I5 => \wl_tap_count_r[4]_i_2_n_0\,
      O => wl_tap_count_r(3)
    );
\wl_tap_count_r[3]_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"80"
    )
        port map (
      I0 => \wl_tap_count_r_reg_n_0_[1]\,
      I1 => \wl_tap_count_r_reg_n_0_[0]\,
      I2 => \wl_tap_count_r_reg_n_0_[2]\,
      O => \wl_tap_count_r[3]_i_3_n_0\
    );
\wl_tap_count_r[3]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \smallest_reg[3]_16\(3),
      I1 => \smallest_reg[2]_15\(3),
      I2 => \dqs_count_r_reg[3]_1\(1),
      I3 => \smallest_reg[1]_14\(3),
      I4 => \dqs_count_r_reg[3]_1\(0),
      I5 => \smallest_reg[0]_13\(3),
      O => \wl_tap_count_r[3]_i_4_n_0\
    );
\wl_tap_count_r[3]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \smallest_reg[7]_20\(3),
      I1 => \smallest_reg[6]_19\(3),
      I2 => \dqs_count_r_reg[3]_1\(1),
      I3 => \smallest_reg[5]_18\(3),
      I4 => \dqs_count_r_reg[3]_1\(0),
      I5 => \smallest_reg[4]_17\(3),
      O => \wl_tap_count_r[3]_i_5_n_0\
    );
\wl_tap_count_r[4]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FF00140000001400"
    )
        port map (
      I0 => \wl_tap_count_r[4]_i_2_n_0\,
      I1 => \wl_tap_count_r[4]_i_3_n_0\,
      I2 => \wl_tap_count_r_reg_n_0_[4]\,
      I3 => \wl_tap_count_r[4]_i_4_n_0\,
      I4 => \wl_state_r__0\(1),
      I5 => \wl_tap_count_r_reg[4]_i_5_n_0\,
      O => wl_tap_count_r(4)
    );
\wl_tap_count_r[4]_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^wr_level_done_r5\,
      I1 => \wl_state_r__0\(0),
      O => \wl_tap_count_r[4]_i_2_n_0\
    );
\wl_tap_count_r[4]_i_3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8000"
    )
        port map (
      I0 => \wl_tap_count_r_reg_n_0_[2]\,
      I1 => \wl_tap_count_r_reg_n_0_[0]\,
      I2 => \wl_tap_count_r_reg_n_0_[1]\,
      I3 => \wl_tap_count_r_reg_n_0_[3]\,
      O => \wl_tap_count_r[4]_i_3_n_0\
    );
\wl_tap_count_r[4]_i_4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \^fsm_sequential_wl_state_r_reg[4]_0\(0),
      I1 => \^fsm_sequential_wl_state_r_reg[4]_0\(1),
      O => \wl_tap_count_r[4]_i_4_n_0\
    );
\wl_tap_count_r[4]_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \smallest_reg[3]_16\(4),
      I1 => \smallest_reg[2]_15\(4),
      I2 => \dqs_count_r_reg[3]_1\(1),
      I3 => \smallest_reg[1]_14\(4),
      I4 => \dqs_count_r_reg[3]_1\(0),
      I5 => \smallest_reg[0]_13\(4),
      O => \wl_tap_count_r[4]_i_6_n_0\
    );
\wl_tap_count_r[4]_i_7\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \smallest_reg[7]_20\(4),
      I1 => \smallest_reg[6]_19\(4),
      I2 => \dqs_count_r_reg[3]_1\(1),
      I3 => \smallest_reg[5]_18\(4),
      I4 => \dqs_count_r_reg[3]_1\(0),
      I5 => \smallest_reg[4]_17\(4),
      O => \wl_tap_count_r[4]_i_7_n_0\
    );
\wl_tap_count_r[5]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"000330C020003003"
    )
        port map (
      I0 => done_dqs_dec238_out,
      I1 => \^fsm_sequential_wl_state_r_reg[4]_0\(1),
      I2 => \^fsm_sequential_wl_state_r_reg[4]_0\(0),
      I3 => \wl_state_r__0\(2),
      I4 => \wl_state_r__0\(1),
      I5 => \wl_state_r__0\(0),
      O => \wl_tap_count_r[5]_i_1_n_0\
    );
\wl_tap_count_r[5]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000CA00"
    )
        port map (
      I0 => \wl_tap_count_r[5]_i_4_n_0\,
      I1 => \wl_tap_count_r_reg[5]_i_5_n_0\,
      I2 => \wl_state_r__0\(1),
      I3 => \^fsm_sequential_wl_state_r_reg[4]_0\(0),
      I4 => \^fsm_sequential_wl_state_r_reg[4]_0\(1),
      O => wl_tap_count_r(5)
    );
\wl_tap_count_r[5]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0770770077007700"
    )
        port map (
      I0 => \^wr_level_done_r5\,
      I1 => \wl_state_r__0\(0),
      I2 => \wl_tap_count_r[3]_i_3_n_0\,
      I3 => \wl_tap_count_r_reg_n_0_[5]\,
      I4 => \wl_tap_count_r_reg_n_0_[4]\,
      I5 => \wl_tap_count_r_reg_n_0_[3]\,
      O => \wl_tap_count_r[5]_i_4_n_0\
    );
\wl_tap_count_r[5]_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \smallest_reg[3]_16\(5),
      I1 => \smallest_reg[2]_15\(5),
      I2 => \dqs_count_r_reg[3]_1\(1),
      I3 => \smallest_reg[1]_14\(5),
      I4 => \dqs_count_r_reg[3]_1\(0),
      I5 => \smallest_reg[0]_13\(5),
      O => \wl_tap_count_r[5]_i_6_n_0\
    );
\wl_tap_count_r[5]_i_7\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \smallest_reg[7]_20\(5),
      I1 => \smallest_reg[6]_19\(5),
      I2 => \dqs_count_r_reg[3]_1\(1),
      I3 => \smallest_reg[5]_18\(5),
      I4 => \dqs_count_r_reg[3]_1\(0),
      I5 => \smallest_reg[4]_17\(5),
      O => \wl_tap_count_r[5]_i_7_n_0\
    );
\wl_tap_count_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => \wl_tap_count_r[5]_i_1_n_0\,
      D => wl_tap_count_r(0),
      Q => \wl_tap_count_r_reg_n_0_[0]\,
      R => \fine_inc_reg[6][3]_0\(1)
    );
\wl_tap_count_r_reg[0]_i_2\: unisim.vcomponents.MUXF7
     port map (
      I0 => \wl_tap_count_r[0]_i_3_n_0\,
      I1 => \wl_tap_count_r[0]_i_4_n_0\,
      O => \wl_tap_count_r_reg[0]_i_2_n_0\,
      S => \dqs_count_r_reg[3]_1\(2)
    );
\wl_tap_count_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => \wl_tap_count_r[5]_i_1_n_0\,
      D => wl_tap_count_r(1),
      Q => \wl_tap_count_r_reg_n_0_[1]\,
      R => \fine_inc_reg[6][3]_0\(1)
    );
\wl_tap_count_r_reg[1]_i_2\: unisim.vcomponents.MUXF7
     port map (
      I0 => \wl_tap_count_r[1]_i_3_n_0\,
      I1 => \wl_tap_count_r[1]_i_4_n_0\,
      O => \wl_tap_count_r_reg[1]_i_2_n_0\,
      S => \dqs_count_r_reg[3]_1\(2)
    );
\wl_tap_count_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => \wl_tap_count_r[5]_i_1_n_0\,
      D => wl_tap_count_r(2),
      Q => \wl_tap_count_r_reg_n_0_[2]\,
      R => \fine_inc_reg[6][3]_0\(1)
    );
\wl_tap_count_r_reg[2]_i_3\: unisim.vcomponents.MUXF7
     port map (
      I0 => \wl_tap_count_r[2]_i_4_n_0\,
      I1 => \wl_tap_count_r[2]_i_5_n_0\,
      O => \wl_tap_count_r_reg[2]_i_3_n_0\,
      S => \dqs_count_r_reg[3]_1\(2)
    );
\wl_tap_count_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => \wl_tap_count_r[5]_i_1_n_0\,
      D => wl_tap_count_r(3),
      Q => \wl_tap_count_r_reg_n_0_[3]\,
      R => \fine_inc_reg[6][3]_0\(1)
    );
\wl_tap_count_r_reg[3]_i_2\: unisim.vcomponents.MUXF7
     port map (
      I0 => \wl_tap_count_r[3]_i_4_n_0\,
      I1 => \wl_tap_count_r[3]_i_5_n_0\,
      O => \wl_tap_count_r_reg[3]_i_2_n_0\,
      S => \dqs_count_r_reg[3]_1\(2)
    );
\wl_tap_count_r_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => \wl_tap_count_r[5]_i_1_n_0\,
      D => wl_tap_count_r(4),
      Q => \wl_tap_count_r_reg_n_0_[4]\,
      R => \fine_inc_reg[6][3]_0\(1)
    );
\wl_tap_count_r_reg[4]_i_5\: unisim.vcomponents.MUXF7
     port map (
      I0 => \wl_tap_count_r[4]_i_6_n_0\,
      I1 => \wl_tap_count_r[4]_i_7_n_0\,
      O => \wl_tap_count_r_reg[4]_i_5_n_0\,
      S => \dqs_count_r_reg[3]_1\(2)
    );
\wl_tap_count_r_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => \wl_tap_count_r[5]_i_1_n_0\,
      D => wl_tap_count_r(5),
      Q => \wl_tap_count_r_reg_n_0_[5]\,
      R => \fine_inc_reg[6][3]_0\(1)
    );
\wl_tap_count_r_reg[5]_i_5\: unisim.vcomponents.MUXF7
     port map (
      I0 => \wl_tap_count_r[5]_i_6_n_0\,
      I1 => \wl_tap_count_r[5]_i_7_n_0\,
      O => \wl_tap_count_r_reg[5]_i_5_n_0\,
      S => \dqs_count_r_reg[3]_1\(2)
    );
wr_level_done_i_1: unisim.vcomponents.LUT3
    generic map(
      INIT => X"8A"
    )
        port map (
      I0 => \^done_dqs_tap_inc\,
      I1 => \^wrlvl_byte_redo_r\,
      I2 => wrlvl_byte_redo,
      O => wr_level_done_i_1_n_0
    );
wr_level_done_r1_reg: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => '1',
      D => wr_level_done_r_reg_n_0,
      Q => wr_level_done_r1,
      R => '0'
    );
wr_level_done_r2_reg: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => '1',
      D => wr_level_done_r1,
      Q => wr_level_done_r2,
      R => '0'
    );
wr_level_done_r3_reg: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => '1',
      D => wr_level_done_r2,
      Q => wr_level_done_r3,
      R => '0'
    );
wr_level_done_r4_reg: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => '1',
      D => wr_level_done_r3,
      Q => wr_level_done_r4,
      R => '0'
    );
wr_level_done_r5_reg: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => '1',
      D => wr_level_done_r4,
      Q => \^wr_level_done_r5\,
      R => '0'
    );
wr_level_done_r_i_1: unisim.vcomponents.LUT5
    generic map(
      INIT => X"01FF0100"
    )
        port map (
      I0 => \rank_cnt_r_reg_n_0_[1]\,
      I1 => \rank_cnt_r_reg_n_0_[0]\,
      I2 => \wl_state_r__0\(2),
      I3 => wr_level_done_r_i_2_n_0,
      I4 => wr_level_done_r_reg_n_0,
      O => wr_level_done_r_i_1_n_0
    );
wr_level_done_r_i_2: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00A0000003000000"
    )
        port map (
      I0 => done_dqs_dec238_out,
      I1 => p_0_in,
      I2 => \^fsm_sequential_wl_state_r_reg[4]_0\(0),
      I3 => \wl_state_r__0\(0),
      I4 => \rank_cnt_r[1]_i_2_n_0\,
      I5 => \wl_state_r__0\(2),
      O => wr_level_done_r_i_2_n_0
    );
wr_level_done_r_reg: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => '1',
      D => wr_level_done_r_i_1_n_0,
      Q => wr_level_done_r_reg_n_0,
      R => \wl_dqs_tap_count_r_reg[0][5][5]_0\
    );
wr_level_done_reg: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => '1',
      D => wr_level_done_i_1_n_0,
      Q => wr_level_done_reg_0,
      R => '0'
    );
wr_level_start_r_reg: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => '1',
      D => wr_level_start_r_reg_0,
      Q => wr_level_start_r,
      R => '0'
    );
wrlvl_byte_done_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000BAAA00AA"
    )
        port map (
      I0 => \^wrlvl_byte_done\,
      I1 => wr_level_done_r4,
      I2 => wr_level_done_r3,
      I3 => wrlvl_byte_redo,
      I4 => \^wrlvl_byte_redo_r\,
      I5 => \single_rank.done_dqs_dec_reg_0\,
      O => wrlvl_byte_done_i_1_n_0
    );
wrlvl_byte_done_reg: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => '1',
      D => wrlvl_byte_done_i_1_n_0,
      Q => \^wrlvl_byte_done\,
      R => '0'
    );
wrlvl_byte_redo_r_reg: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => '1',
      D => wrlvl_byte_redo,
      Q => \^wrlvl_byte_redo_r\,
      R => '0'
    );
wrlvl_rank_done_r_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"4573557700220022"
    )
        port map (
      I0 => wrlvl_rank_done_r_i_2_n_0,
      I1 => \^fsm_sequential_wl_state_r_reg[4]_0\(1),
      I2 => \^fsm_sequential_wl_state_r_reg[4]_0\(0),
      I3 => \wl_state_r__0\(2),
      I4 => wrlvl_rank_done_r_i_3_n_0,
      I5 => \^wrlvl_rank_done\,
      O => wrlvl_rank_done_r_i_1_n_0
    );
wrlvl_rank_done_r_i_2: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000200000000"
    )
        port map (
      I0 => \wl_state_r__0\(0),
      I1 => \wl_state_r__0\(2),
      I2 => \^fsm_sequential_wl_state_r_reg[4]_0\(0),
      I3 => p_0_in,
      I4 => \^fsm_sequential_wl_state_r_reg[4]_0\(1),
      I5 => \wl_state_r__0\(1),
      O => wrlvl_rank_done_r_i_2_n_0
    );
wrlvl_rank_done_r_i_3: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \wl_state_r__0\(1),
      I1 => \wl_state_r__0\(0),
      O => wrlvl_rank_done_r_i_3_n_0
    );
wrlvl_rank_done_r_reg: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => '1',
      D => wrlvl_rank_done_r_i_1_n_0,
      Q => \^wrlvl_rank_done\,
      R => \corse_inc_reg[6][2]_0\(0)
    );
\wrlvl_redo_corse_inc[0]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"34"
    )
        port map (
      I0 => \wl_state_r__0\(2),
      I1 => \wrlvl_redo_corse_inc[2]_i_4_n_0\,
      I2 => \wrlvl_redo_corse_inc_reg_n_0_[0]\,
      O => \wrlvl_redo_corse_inc[0]_i_1_n_0\
    );
\wrlvl_redo_corse_inc[1]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"4440FFFF40440000"
    )
        port map (
      I0 => \^fsm_sequential_wl_state_r_reg[4]_0\(1),
      I1 => \wl_state_r__0\(1),
      I2 => \wl_state_r__0\(2),
      I3 => \wrlvl_redo_corse_inc_reg_n_0_[0]\,
      I4 => \wrlvl_redo_corse_inc[2]_i_4_n_0\,
      I5 => \wrlvl_redo_corse_inc_reg_n_0_[1]\,
      O => \wrlvl_redo_corse_inc[1]_i_1_n_0\
    );
\wrlvl_redo_corse_inc[2]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"D100FFFFE2000000"
    )
        port map (
      I0 => \wrlvl_redo_corse_inc[2]_i_2_n_0\,
      I1 => \wl_state_r__0\(2),
      I2 => \wrlvl_redo_corse_inc[2]_i_3_n_0\,
      I3 => \rank_cnt_r[1]_i_2_n_0\,
      I4 => \wrlvl_redo_corse_inc[2]_i_4_n_0\,
      I5 => \wrlvl_redo_corse_inc_reg_n_0_[2]\,
      O => \wrlvl_redo_corse_inc[2]_i_1_n_0\
    );
\wrlvl_redo_corse_inc[2]_i_10\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \final_coarse_tap_reg_n_0_[3][2]\,
      I1 => \final_coarse_tap_reg_n_0_[2][2]\,
      I2 => \dqs_count_r_reg[3]_1\(1),
      I3 => \final_coarse_tap_reg_n_0_[1][2]\,
      I4 => \dqs_count_r_reg[3]_1\(0),
      I5 => \final_coarse_tap_reg_n_0_[0][2]\,
      O => \wrlvl_redo_corse_inc[2]_i_10_n_0\
    );
\wrlvl_redo_corse_inc[2]_i_11\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \final_coarse_tap_reg_n_0_[7][2]\,
      I1 => \final_coarse_tap_reg_n_0_[6][2]\,
      I2 => \dqs_count_r_reg[3]_1\(1),
      I3 => \final_coarse_tap_reg_n_0_[5][2]\,
      I4 => \dqs_count_r_reg[3]_1\(0),
      I5 => \final_coarse_tap_reg_n_0_[4][2]\,
      O => \wrlvl_redo_corse_inc[2]_i_11_n_0\
    );
\wrlvl_redo_corse_inc[2]_i_12\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"AAA8"
    )
        port map (
      I0 => wrlvl_byte_redo,
      I1 => \wrlvl_redo_corse_inc_reg_n_0_[2]\,
      I2 => \wrlvl_redo_corse_inc_reg_n_0_[0]\,
      I3 => \wrlvl_redo_corse_inc_reg_n_0_[1]\,
      O => \wrlvl_redo_corse_inc[2]_i_12_n_0\
    );
\wrlvl_redo_corse_inc[2]_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \wrlvl_redo_corse_inc_reg_n_0_[0]\,
      I1 => \wrlvl_redo_corse_inc_reg_n_0_[1]\,
      O => \wrlvl_redo_corse_inc[2]_i_2_n_0\
    );
\wrlvl_redo_corse_inc[2]_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"D5"
    )
        port map (
      I0 => \wrlvl_redo_corse_inc_reg[2]_0\,
      I1 => \^po_stg2_wrcal_cnt_reg[2]\,
      I2 => \^po_stg2_wrcal_cnt_reg[2]_0\,
      O => \wrlvl_redo_corse_inc[2]_i_3_n_0\
    );
\wrlvl_redo_corse_inc[2]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0808080000000000"
    )
        port map (
      I0 => \wrlvl_redo_corse_inc[2]_i_7_n_0\,
      I1 => \wl_state_r__0\(1),
      I2 => \^fsm_sequential_wl_state_r_reg[4]_0\(1),
      I3 => \wl_state_r__0\(2),
      I4 => \wl_state_r__0\(0),
      I5 => \^fsm_sequential_wl_state_r_reg[4]_0\(0),
      O => \wrlvl_redo_corse_inc[2]_i_4_n_0\
    );
\wrlvl_redo_corse_inc[2]_i_7\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"44444444444F4444"
    )
        port map (
      I0 => \wl_state_r__0\(2),
      I1 => \wrlvl_redo_corse_inc[2]_i_12_n_0\,
      I2 => \wrlvl_redo_corse_inc[2]_i_4_0\,
      I3 => \wl_state_r__0\(0),
      I4 => wrlvl_byte_redo,
      I5 => \^wrlvl_byte_redo_r\,
      O => \wrlvl_redo_corse_inc[2]_i_7_n_0\
    );
\wrlvl_redo_corse_inc[2]_i_8\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \final_coarse_tap_reg_n_0_[3][1]\,
      I1 => \final_coarse_tap_reg_n_0_[2][1]\,
      I2 => \dqs_count_r_reg[3]_1\(1),
      I3 => \final_coarse_tap_reg_n_0_[1][1]\,
      I4 => \dqs_count_r_reg[3]_1\(0),
      I5 => \final_coarse_tap_reg_n_0_[0][1]\,
      O => \wrlvl_redo_corse_inc[2]_i_8_n_0\
    );
\wrlvl_redo_corse_inc[2]_i_9\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \final_coarse_tap_reg_n_0_[7][1]\,
      I1 => \final_coarse_tap_reg_n_0_[6][1]\,
      I2 => \dqs_count_r_reg[3]_1\(1),
      I3 => \final_coarse_tap_reg_n_0_[5][1]\,
      I4 => \dqs_count_r_reg[3]_1\(0),
      I5 => \final_coarse_tap_reg_n_0_[4][1]\,
      O => \wrlvl_redo_corse_inc[2]_i_9_n_0\
    );
\wrlvl_redo_corse_inc_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => '1',
      D => \wrlvl_redo_corse_inc[0]_i_1_n_0\,
      Q => \wrlvl_redo_corse_inc_reg_n_0_[0]\,
      R => \wl_dqs_tap_count_r_reg[0][5][5]_0\
    );
\wrlvl_redo_corse_inc_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => '1',
      D => \wrlvl_redo_corse_inc[1]_i_1_n_0\,
      Q => \wrlvl_redo_corse_inc_reg_n_0_[1]\,
      R => \wl_dqs_tap_count_r_reg[0][5][5]_0\
    );
\wrlvl_redo_corse_inc_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \dqs_count_r_reg[2]_rep__0_1\,
      CE => '1',
      D => \wrlvl_redo_corse_inc[2]_i_1_n_0\,
      Q => \wrlvl_redo_corse_inc_reg_n_0_[2]\,
      R => \wl_dqs_tap_count_r_reg[0][5][5]_0\
    );
\wrlvl_redo_corse_inc_reg[2]_i_5\: unisim.vcomponents.MUXF7
     port map (
      I0 => \wrlvl_redo_corse_inc[2]_i_8_n_0\,
      I1 => \wrlvl_redo_corse_inc[2]_i_9_n_0\,
      O => \^po_stg2_wrcal_cnt_reg[2]\,
      S => \dqs_count_r_reg[3]_1\(2)
    );
\wrlvl_redo_corse_inc_reg[2]_i_6\: unisim.vcomponents.MUXF7
     port map (
      I0 => \wrlvl_redo_corse_inc[2]_i_10_n_0\,
      I1 => \wrlvl_redo_corse_inc[2]_i_11_n_0\,
      O => \^po_stg2_wrcal_cnt_reg[2]_0\,
      S => \dqs_count_r_reg[3]_1\(2)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mig_mig_7series_v4_2_ddr_prbs_gen is
  port (
    phy_if_empty_r_reg_0 : out STD_LOGIC;
    first_wrcal_pat_r_reg : out STD_LOGIC;
    first_wrcal_pat_r_reg_0 : out STD_LOGIC;
    \dout_o_reg[9]_0\ : out STD_LOGIC;
    \dout_o_reg[9]_1\ : out STD_LOGIC;
    \dout_o_reg[10]_0\ : out STD_LOGIC;
    \dout_o_reg[10]_1\ : out STD_LOGIC;
    \dout_o_reg[11]_0\ : out STD_LOGIC;
    \dout_o_reg[11]_1\ : out STD_LOGIC;
    \dout_o_reg[12]_0\ : out STD_LOGIC;
    \dout_o_reg[12]_1\ : out STD_LOGIC;
    \dout_o_reg[12]_2\ : out STD_LOGIC;
    \dout_o_reg[12]_3\ : out STD_LOGIC;
    \dout_o_reg[13]_0\ : out STD_LOGIC;
    \dout_o_reg[13]_1\ : out STD_LOGIC;
    \dout_o_reg[13]_2\ : out STD_LOGIC;
    \dout_o_reg[13]_3\ : out STD_LOGIC;
    \dout_o_reg[14]_0\ : out STD_LOGIC;
    \dout_o_reg[14]_1\ : out STD_LOGIC;
    \dout_o_reg[8]_0\ : out STD_LOGIC;
    \dout_o_reg[8]_1\ : out STD_LOGIC;
    \dout_o_reg[8]_2\ : out STD_LOGIC;
    \dout_o_reg[8]_3\ : out STD_LOGIC;
    rdlvl_stg1_done_int_reg : out STD_LOGIC;
    \dout_o_reg[9]_2\ : out STD_LOGIC;
    rdlvl_stg1_done_int_reg_0 : out STD_LOGIC;
    rdlvl_stg1_done_int_reg_1 : out STD_LOGIC;
    \dout_o_reg[9]_3\ : out STD_LOGIC;
    rdlvl_stg1_done_int_reg_2 : out STD_LOGIC;
    \dout_o_reg[10]_2\ : out STD_LOGIC;
    rdlvl_stg1_done_int_reg_3 : out STD_LOGIC;
    \dout_o_reg[10]_3\ : out STD_LOGIC;
    rdlvl_stg1_done_int_reg_4 : out STD_LOGIC;
    \dout_o_reg[11]_2\ : out STD_LOGIC;
    \dout_o_reg[11]_3\ : out STD_LOGIC;
    \dout_o_reg[12]_4\ : out STD_LOGIC;
    \dout_o_reg[12]_5\ : out STD_LOGIC;
    rdlvl_stg1_done_int_reg_5 : out STD_LOGIC;
    rdlvl_stg1_done_int_reg_6 : out STD_LOGIC;
    \dout_o_reg[6]_0\ : out STD_LOGIC;
    wrcal_done_reg : out STD_LOGIC;
    \dout_o_reg[15]_0\ : out STD_LOGIC;
    wrcal_done_reg_0 : out STD_LOGIC;
    \dout_o_reg[15]_1\ : out STD_LOGIC;
    wrcal_done_reg_1 : out STD_LOGIC;
    Q : out STD_LOGIC_VECTOR ( 0 to 0 );
    prbs_out : out STD_LOGIC_VECTOR ( 63 downto 0 );
    if_empty : in STD_LOGIC;
    \dout_o_reg[15]_2\ : in STD_LOGIC;
    first_wrcal_pat_r : in STD_LOGIC;
    \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[511]\ : in STD_LOGIC;
    \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[511]_0\ : in STD_LOGIC;
    first_rdlvl_pat_r : in STD_LOGIC;
    \rd_addr_reg[3]_0\ : in STD_LOGIC;
    \rd_addr_reg[0]_0\ : in STD_LOGIC;
    \victim_sel_rotate.sel_reg[56]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    D : in STD_LOGIC_VECTOR ( 7 downto 0 );
    SR : in STD_LOGIC_VECTOR ( 0 to 0 );
    E : in STD_LOGIC_VECTOR ( 0 to 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of mig_mig_7series_v4_2_ddr_prbs_gen : entity is "mig_7series_v4_2_ddr_prbs_gen";
end mig_mig_7series_v4_2_ddr_prbs_gen;

architecture STRUCTURE of mig_mig_7series_v4_2_ddr_prbs_gen is
  signal \^q\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \dout_o[0]_i_1_n_0\ : STD_LOGIC;
  signal \dout_o[0]_i_2_n_0\ : STD_LOGIC;
  signal \dout_o[0]_i_3_n_0\ : STD_LOGIC;
  signal \dout_o[0]_i_4_n_0\ : STD_LOGIC;
  signal \dout_o[10]_i_1_n_0\ : STD_LOGIC;
  signal \dout_o[10]_i_2_n_0\ : STD_LOGIC;
  signal \dout_o[10]_i_3_n_0\ : STD_LOGIC;
  signal \dout_o[11]_i_1_n_0\ : STD_LOGIC;
  signal \dout_o[11]_i_2_n_0\ : STD_LOGIC;
  signal \dout_o[11]_i_3_n_0\ : STD_LOGIC;
  signal \dout_o[11]_i_4_n_0\ : STD_LOGIC;
  signal \dout_o[12]_i_1_n_0\ : STD_LOGIC;
  signal \dout_o[12]_i_2_n_0\ : STD_LOGIC;
  signal \dout_o[12]_i_3_n_0\ : STD_LOGIC;
  signal \dout_o[12]_i_4_n_0\ : STD_LOGIC;
  signal \dout_o[13]_i_1_n_0\ : STD_LOGIC;
  signal \dout_o[13]_i_2_n_0\ : STD_LOGIC;
  signal \dout_o[13]_i_3_n_0\ : STD_LOGIC;
  signal \dout_o[13]_i_4_n_0\ : STD_LOGIC;
  signal \dout_o[14]_i_1_n_0\ : STD_LOGIC;
  signal \dout_o[14]_i_2_n_0\ : STD_LOGIC;
  signal \dout_o[14]_i_3_n_0\ : STD_LOGIC;
  signal \dout_o[14]_i_4_n_0\ : STD_LOGIC;
  signal \dout_o[15]_i_1_n_0\ : STD_LOGIC;
  signal \dout_o[15]_i_2_n_0\ : STD_LOGIC;
  signal \dout_o[15]_i_3_n_0\ : STD_LOGIC;
  signal \dout_o[15]_i_4_n_0\ : STD_LOGIC;
  signal \dout_o[1]_i_1_n_0\ : STD_LOGIC;
  signal \dout_o[1]_i_2_n_0\ : STD_LOGIC;
  signal \dout_o[1]_i_3_n_0\ : STD_LOGIC;
  signal \dout_o[1]_i_4_n_0\ : STD_LOGIC;
  signal \dout_o[2]_i_1_n_0\ : STD_LOGIC;
  signal \dout_o[2]_i_2_n_0\ : STD_LOGIC;
  signal \dout_o[2]_i_3_n_0\ : STD_LOGIC;
  signal \dout_o[2]_i_4_n_0\ : STD_LOGIC;
  signal \dout_o[3]_i_1_n_0\ : STD_LOGIC;
  signal \dout_o[3]_i_2_n_0\ : STD_LOGIC;
  signal \dout_o[3]_i_3_n_0\ : STD_LOGIC;
  signal \dout_o[3]_i_4_n_0\ : STD_LOGIC;
  signal \dout_o[4]_i_1_n_0\ : STD_LOGIC;
  signal \dout_o[4]_i_2_n_0\ : STD_LOGIC;
  signal \dout_o[4]_i_3_n_0\ : STD_LOGIC;
  signal \dout_o[4]_i_4_n_0\ : STD_LOGIC;
  signal \dout_o[5]_i_1_n_0\ : STD_LOGIC;
  signal \dout_o[5]_i_2_n_0\ : STD_LOGIC;
  signal \dout_o[5]_i_3_n_0\ : STD_LOGIC;
  signal \dout_o[5]_i_4_n_0\ : STD_LOGIC;
  signal \dout_o[6]_i_1_n_0\ : STD_LOGIC;
  signal \dout_o[6]_i_2_n_0\ : STD_LOGIC;
  signal \dout_o[6]_i_3_n_0\ : STD_LOGIC;
  signal \dout_o[6]_i_4_n_0\ : STD_LOGIC;
  signal \dout_o[7]_i_1_n_0\ : STD_LOGIC;
  signal \dout_o[7]_i_2_n_0\ : STD_LOGIC;
  signal \dout_o[7]_i_3_n_0\ : STD_LOGIC;
  signal \dout_o[7]_i_4_n_0\ : STD_LOGIC;
  signal \dout_o[8]_i_1_n_0\ : STD_LOGIC;
  signal \dout_o[8]_i_2_n_0\ : STD_LOGIC;
  signal \dout_o[8]_i_3_n_0\ : STD_LOGIC;
  signal \dout_o[8]_i_4_n_0\ : STD_LOGIC;
  signal \dout_o[9]_i_1_n_0\ : STD_LOGIC;
  signal \dout_o[9]_i_2_n_0\ : STD_LOGIC;
  signal \dout_o[9]_i_3_n_0\ : STD_LOGIC;
  signal \dout_o[9]_i_4_n_0\ : STD_LOGIC;
  signal \dout_o_reg_n_0_[0]\ : STD_LOGIC;
  signal p_0_in222_in : STD_LOGIC;
  signal p_0_in226_in : STD_LOGIC;
  signal p_0_in230_in : STD_LOGIC;
  signal p_0_in234_in : STD_LOGIC;
  signal p_0_in238_in : STD_LOGIC;
  signal p_0_in242_in : STD_LOGIC;
  signal p_0_in246_in : STD_LOGIC;
  signal p_0_in250_in : STD_LOGIC;
  signal p_1_in : STD_LOGIC;
  signal p_1_in1032_in : STD_LOGIC;
  signal p_1_in252_in : STD_LOGIC;
  signal p_1_in382_in : STD_LOGIC;
  signal p_1_in512_in : STD_LOGIC;
  signal p_1_in642_in : STD_LOGIC;
  signal p_1_in772_in : STD_LOGIC;
  signal p_1_in902_in : STD_LOGIC;
  signal \p_1_in__0\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal p_2_in : STD_LOGIC;
  signal p_2_in254_in : STD_LOGIC;
  signal p_2_in384_in : STD_LOGIC;
  signal p_2_in514_in : STD_LOGIC;
  signal p_2_in644_in : STD_LOGIC;
  signal p_2_in774_in : STD_LOGIC;
  signal p_2_in904_in : STD_LOGIC;
  signal \rd_addr[2]_i_2_n_0\ : STD_LOGIC;
  signal \rd_addr[3]_i_2_n_0\ : STD_LOGIC;
  signal \rd_addr[4]_i_2_n_0\ : STD_LOGIC;
  signal \rd_addr[7]_i_4_n_0\ : STD_LOGIC;
  signal \rd_addr[7]_i_5_n_0\ : STD_LOGIC;
  signal \rd_addr[7]_i_6_n_0\ : STD_LOGIC;
  signal \rd_addr[7]_i_7_n_0\ : STD_LOGIC;
  signal \rd_addr_reg_n_0_[0]\ : STD_LOGIC;
  signal \rd_addr_reg_n_0_[2]\ : STD_LOGIC;
  signal \rd_addr_reg_n_0_[3]\ : STD_LOGIC;
  signal \rd_addr_reg_n_0_[4]\ : STD_LOGIC;
  signal \rd_addr_reg_n_0_[5]\ : STD_LOGIC;
  signal \rd_addr_reg_n_0_[6]\ : STD_LOGIC;
  signal \rd_addr_reg_n_0_[7]\ : STD_LOGIC;
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \gen_mux_rd[0].compare_data_fall0_r1[0]_i_1\ : label is "soft_lutpair558";
  attribute SOFT_HLUTNM of \gen_mux_rd[0].compare_data_fall1_r1[0]_i_1\ : label is "soft_lutpair574";
  attribute SOFT_HLUTNM of \gen_mux_rd[0].compare_data_fall2_r1[0]_i_1\ : label is "soft_lutpair600";
  attribute SOFT_HLUTNM of \gen_mux_rd[0].compare_data_fall3_r1[0]_i_1\ : label is "soft_lutpair595";
  attribute SOFT_HLUTNM of \gen_mux_rd[0].compare_data_rise0_r1[0]_i_1\ : label is "soft_lutpair601";
  attribute SOFT_HLUTNM of \gen_mux_rd[0].compare_data_rise1_r1[0]_i_1\ : label is "soft_lutpair576";
  attribute SOFT_HLUTNM of \gen_mux_rd[0].compare_data_rise2_r1[0]_i_1\ : label is "soft_lutpair563";
  attribute SOFT_HLUTNM of \gen_mux_rd[0].compare_data_rise3_r1[0]_i_1\ : label is "soft_lutpair598";
  attribute SOFT_HLUTNM of \gen_mux_rd[1].compare_data_fall0_r1[1]_i_1\ : label is "soft_lutpair608";
  attribute SOFT_HLUTNM of \gen_mux_rd[1].compare_data_fall1_r1[1]_i_1\ : label is "soft_lutpair577";
  attribute SOFT_HLUTNM of \gen_mux_rd[1].compare_data_fall2_r1[1]_i_1\ : label is "soft_lutpair585";
  attribute SOFT_HLUTNM of \gen_mux_rd[1].compare_data_fall3_r1[1]_i_1\ : label is "soft_lutpair559";
  attribute SOFT_HLUTNM of \gen_mux_rd[1].compare_data_rise0_r1[1]_i_1\ : label is "soft_lutpair602";
  attribute SOFT_HLUTNM of \gen_mux_rd[1].compare_data_rise1_r1[1]_i_1\ : label is "soft_lutpair605";
  attribute SOFT_HLUTNM of \gen_mux_rd[1].compare_data_rise2_r1[1]_i_1\ : label is "soft_lutpair593";
  attribute SOFT_HLUTNM of \gen_mux_rd[1].compare_data_rise3_r1[1]_i_1\ : label is "soft_lutpair598";
  attribute SOFT_HLUTNM of \gen_mux_rd[2].compare_data_fall0_r1[2]_i_1\ : label is "soft_lutpair608";
  attribute SOFT_HLUTNM of \gen_mux_rd[2].compare_data_fall1_r1[2]_i_1\ : label is "soft_lutpair603";
  attribute SOFT_HLUTNM of \gen_mux_rd[2].compare_data_fall2_r1[2]_i_1\ : label is "soft_lutpair573";
  attribute SOFT_HLUTNM of \gen_mux_rd[2].compare_data_fall3_r1[2]_i_1\ : label is "soft_lutpair595";
  attribute SOFT_HLUTNM of \gen_mux_rd[2].compare_data_rise0_r1[2]_i_1\ : label is "soft_lutpair557";
  attribute SOFT_HLUTNM of \gen_mux_rd[2].compare_data_rise1_r1[2]_i_1\ : label is "soft_lutpair570";
  attribute SOFT_HLUTNM of \gen_mux_rd[2].compare_data_rise2_r1[2]_i_1\ : label is "soft_lutpair591";
  attribute SOFT_HLUTNM of \gen_mux_rd[2].compare_data_rise3_r1[2]_i_1\ : label is "soft_lutpair572";
  attribute SOFT_HLUTNM of \gen_mux_rd[3].compare_data_fall0_r1[3]_i_1\ : label is "soft_lutpair607";
  attribute SOFT_HLUTNM of \gen_mux_rd[3].compare_data_fall1_r1[3]_i_1\ : label is "soft_lutpair582";
  attribute SOFT_HLUTNM of \gen_mux_rd[3].compare_data_fall2_r1[3]_i_1\ : label is "soft_lutpair600";
  attribute SOFT_HLUTNM of \gen_mux_rd[3].compare_data_fall3_r1[3]_i_1\ : label is "soft_lutpair561";
  attribute SOFT_HLUTNM of \gen_mux_rd[3].compare_data_rise0_r1[3]_i_1\ : label is "soft_lutpair609";
  attribute SOFT_HLUTNM of \gen_mux_rd[3].compare_data_rise1_r1[3]_i_1\ : label is "soft_lutpair605";
  attribute SOFT_HLUTNM of \gen_mux_rd[3].compare_data_rise2_r1[3]_i_1\ : label is "soft_lutpair587";
  attribute SOFT_HLUTNM of \gen_mux_rd[3].compare_data_rise3_r1[3]_i_1\ : label is "soft_lutpair597";
  attribute SOFT_HLUTNM of \gen_mux_rd[4].compare_data_fall0_r1[4]_i_1\ : label is "soft_lutpair567";
  attribute SOFT_HLUTNM of \gen_mux_rd[4].compare_data_fall1_r1[4]_i_1\ : label is "soft_lutpair562";
  attribute SOFT_HLUTNM of \gen_mux_rd[4].compare_data_fall2_r1[4]_i_1\ : label is "soft_lutpair583";
  attribute SOFT_HLUTNM of \gen_mux_rd[4].compare_data_fall3_r1[4]_i_1\ : label is "soft_lutpair594";
  attribute SOFT_HLUTNM of \gen_mux_rd[4].compare_data_rise0_r1[4]_i_1\ : label is "soft_lutpair609";
  attribute SOFT_HLUTNM of \gen_mux_rd[4].compare_data_rise1_r1[4]_i_1\ : label is "soft_lutpair575";
  attribute SOFT_HLUTNM of \gen_mux_rd[4].compare_data_rise2_r1[4]_i_1\ : label is "soft_lutpair564";
  attribute SOFT_HLUTNM of \gen_mux_rd[4].compare_data_rise3_r1[4]_i_1\ : label is "soft_lutpair597";
  attribute SOFT_HLUTNM of \gen_mux_rd[5].compare_data_fall0_r1[5]_i_1\ : label is "soft_lutpair607";
  attribute SOFT_HLUTNM of \gen_mux_rd[5].compare_data_fall1_r1[5]_i_1\ : label is "soft_lutpair579";
  attribute SOFT_HLUTNM of \gen_mux_rd[5].compare_data_fall2_r1[5]_i_1\ : label is "soft_lutpair599";
  attribute SOFT_HLUTNM of \gen_mux_rd[5].compare_data_fall3_r1[5]_i_1\ : label is "soft_lutpair560";
  attribute SOFT_HLUTNM of \gen_mux_rd[5].compare_data_rise0_r1[5]_i_1\ : label is "soft_lutpair602";
  attribute SOFT_HLUTNM of \gen_mux_rd[5].compare_data_rise1_r1[5]_i_1\ : label is "soft_lutpair604";
  attribute SOFT_HLUTNM of \gen_mux_rd[5].compare_data_rise2_r1[5]_i_1\ : label is "soft_lutpair593";
  attribute SOFT_HLUTNM of \gen_mux_rd[5].compare_data_rise3_r1[5]_i_1\ : label is "soft_lutpair596";
  attribute SOFT_HLUTNM of \gen_mux_rd[6].compare_data_fall0_r1[6]_i_1\ : label is "soft_lutpair606";
  attribute SOFT_HLUTNM of \gen_mux_rd[6].compare_data_fall1_r1[6]_i_1\ : label is "soft_lutpair603";
  attribute SOFT_HLUTNM of \gen_mux_rd[6].compare_data_fall2_r1[6]_i_1\ : label is "soft_lutpair566";
  attribute SOFT_HLUTNM of \gen_mux_rd[6].compare_data_fall3_r1[6]_i_1\ : label is "soft_lutpair594";
  attribute SOFT_HLUTNM of \gen_mux_rd[6].compare_data_rise0_r1[6]_i_1\ : label is "soft_lutpair569";
  attribute SOFT_HLUTNM of \gen_mux_rd[6].compare_data_rise1_r1[6]_i_1\ : label is "soft_lutpair568";
  attribute SOFT_HLUTNM of \gen_mux_rd[6].compare_data_rise2_r1[6]_i_1\ : label is "soft_lutpair591";
  attribute SOFT_HLUTNM of \gen_mux_rd[6].compare_data_rise3_r1[6]_i_1\ : label is "soft_lutpair571";
  attribute SOFT_HLUTNM of \gen_mux_rd[7].compare_data_fall0_r1[7]_i_1\ : label is "soft_lutpair606";
  attribute SOFT_HLUTNM of \gen_mux_rd[7].compare_data_fall1_r1[7]_i_1\ : label is "soft_lutpair586";
  attribute SOFT_HLUTNM of \gen_mux_rd[7].compare_data_fall2_r1[7]_i_1\ : label is "soft_lutpair599";
  attribute SOFT_HLUTNM of \gen_mux_rd[7].compare_data_fall3_r1[7]_i_1\ : label is "soft_lutpair565";
  attribute SOFT_HLUTNM of \gen_mux_rd[7].compare_data_rise0_r1[7]_i_1\ : label is "soft_lutpair601";
  attribute SOFT_HLUTNM of \gen_mux_rd[7].compare_data_rise1_r1[7]_i_1\ : label is "soft_lutpair604";
  attribute SOFT_HLUTNM of \gen_mux_rd[7].compare_data_rise2_r1[7]_i_1\ : label is "soft_lutpair588";
  attribute SOFT_HLUTNM of \gen_mux_rd[7].compare_data_rise3_r1[7]_i_1\ : label is "soft_lutpair596";
  attribute SOFT_HLUTNM of \rd_addr[0]_i_1\ : label is "soft_lutpair590";
  attribute SOFT_HLUTNM of \rd_addr[2]_i_1\ : label is "soft_lutpair590";
  attribute SOFT_HLUTNM of \rd_addr[4]_i_2\ : label is "soft_lutpair556";
  attribute SOFT_HLUTNM of \rd_addr[6]_i_1\ : label is "soft_lutpair592";
  attribute SOFT_HLUTNM of \rd_addr[7]_i_6\ : label is "soft_lutpair556";
  attribute SOFT_HLUTNM of \rd_addr[7]_i_7\ : label is "soft_lutpair592";
  attribute RAM_STYLE : string;
  attribute RAM_STYLE of \rd_addr_reg[0]\ : label is "distributed";
  attribute RAM_STYLE of \rd_addr_reg[1]\ : label is "distributed";
  attribute RAM_STYLE of \rd_addr_reg[2]\ : label is "distributed";
  attribute RAM_STYLE of \rd_addr_reg[3]\ : label is "distributed";
  attribute RAM_STYLE of \rd_addr_reg[4]\ : label is "distributed";
  attribute RAM_STYLE of \rd_addr_reg[5]\ : label is "distributed";
  attribute RAM_STYLE of \rd_addr_reg[6]\ : label is "distributed";
  attribute RAM_STYLE of \rd_addr_reg[7]\ : label is "distributed";
  attribute SOFT_HLUTNM of \wrdq_div1_4to1_wrcal_first.phy_wrdata[120]_i_1\ : label is "soft_lutpair558";
  attribute SOFT_HLUTNM of \wrdq_div1_4to1_wrcal_first.phy_wrdata[124]_i_1\ : label is "soft_lutpair567";
  attribute SOFT_HLUTNM of \wrdq_div1_4to1_wrcal_first.phy_wrdata[184]_i_1\ : label is "soft_lutpair576";
  attribute SOFT_HLUTNM of \wrdq_div1_4to1_wrcal_first.phy_wrdata[186]_i_1\ : label is "soft_lutpair570";
  attribute SOFT_HLUTNM of \wrdq_div1_4to1_wrcal_first.phy_wrdata[187]_i_1\ : label is "soft_lutpair589";
  attribute SOFT_HLUTNM of \wrdq_div1_4to1_wrcal_first.phy_wrdata[188]_i_1\ : label is "soft_lutpair575";
  attribute SOFT_HLUTNM of \wrdq_div1_4to1_wrcal_first.phy_wrdata[190]_i_2\ : label is "soft_lutpair568";
  attribute SOFT_HLUTNM of \wrdq_div1_4to1_wrcal_first.phy_wrdata[191]_i_1\ : label is "soft_lutpair589";
  attribute SOFT_HLUTNM of \wrdq_div1_4to1_wrcal_first.phy_wrdata[248]_i_1\ : label is "soft_lutpair574";
  attribute SOFT_HLUTNM of \wrdq_div1_4to1_wrcal_first.phy_wrdata[249]_i_1\ : label is "soft_lutpair577";
  attribute SOFT_HLUTNM of \wrdq_div1_4to1_wrcal_first.phy_wrdata[251]_i_1\ : label is "soft_lutpair582";
  attribute SOFT_HLUTNM of \wrdq_div1_4to1_wrcal_first.phy_wrdata[252]_i_1\ : label is "soft_lutpair562";
  attribute SOFT_HLUTNM of \wrdq_div1_4to1_wrcal_first.phy_wrdata[253]_i_1\ : label is "soft_lutpair579";
  attribute SOFT_HLUTNM of \wrdq_div1_4to1_wrcal_first.phy_wrdata[255]_i_1\ : label is "soft_lutpair586";
  attribute SOFT_HLUTNM of \wrdq_div1_4to1_wrcal_first.phy_wrdata[312]_i_1\ : label is "soft_lutpair563";
  attribute SOFT_HLUTNM of \wrdq_div1_4to1_wrcal_first.phy_wrdata[315]_i_1\ : label is "soft_lutpair587";
  attribute SOFT_HLUTNM of \wrdq_div1_4to1_wrcal_first.phy_wrdata[316]_i_1\ : label is "soft_lutpair564";
  attribute SOFT_HLUTNM of \wrdq_div1_4to1_wrcal_first.phy_wrdata[319]_i_1\ : label is "soft_lutpair588";
  attribute SOFT_HLUTNM of \wrdq_div1_4to1_wrcal_first.phy_wrdata[376]_i_1\ : label is "soft_lutpair584";
  attribute SOFT_HLUTNM of \wrdq_div1_4to1_wrcal_first.phy_wrdata[377]_i_1\ : label is "soft_lutpair585";
  attribute SOFT_HLUTNM of \wrdq_div1_4to1_wrcal_first.phy_wrdata[378]_i_1\ : label is "soft_lutpair573";
  attribute SOFT_HLUTNM of \wrdq_div1_4to1_wrcal_first.phy_wrdata[380]_i_1\ : label is "soft_lutpair583";
  attribute SOFT_HLUTNM of \wrdq_div1_4to1_wrcal_first.phy_wrdata[381]_i_1\ : label is "soft_lutpair584";
  attribute SOFT_HLUTNM of \wrdq_div1_4to1_wrcal_first.phy_wrdata[382]_i_1\ : label is "soft_lutpair566";
  attribute SOFT_HLUTNM of \wrdq_div1_4to1_wrcal_first.phy_wrdata[440]_i_1\ : label is "soft_lutpair581";
  attribute SOFT_HLUTNM of \wrdq_div1_4to1_wrcal_first.phy_wrdata[441]_i_1\ : label is "soft_lutpair580";
  attribute SOFT_HLUTNM of \wrdq_div1_4to1_wrcal_first.phy_wrdata[442]_i_1\ : label is "soft_lutpair572";
  attribute SOFT_HLUTNM of \wrdq_div1_4to1_wrcal_first.phy_wrdata[443]_i_1\ : label is "soft_lutpair581";
  attribute SOFT_HLUTNM of \wrdq_div1_4to1_wrcal_first.phy_wrdata[444]_i_1\ : label is "soft_lutpair580";
  attribute SOFT_HLUTNM of \wrdq_div1_4to1_wrcal_first.phy_wrdata[445]_i_2\ : label is "soft_lutpair578";
  attribute SOFT_HLUTNM of \wrdq_div1_4to1_wrcal_first.phy_wrdata[446]_i_1\ : label is "soft_lutpair571";
  attribute SOFT_HLUTNM of \wrdq_div1_4to1_wrcal_first.phy_wrdata[447]_i_1\ : label is "soft_lutpair578";
  attribute SOFT_HLUTNM of \wrdq_div1_4to1_wrcal_first.phy_wrdata[505]_i_1\ : label is "soft_lutpair559";
  attribute SOFT_HLUTNM of \wrdq_div1_4to1_wrcal_first.phy_wrdata[507]_i_1\ : label is "soft_lutpair561";
  attribute SOFT_HLUTNM of \wrdq_div1_4to1_wrcal_first.phy_wrdata[509]_i_1\ : label is "soft_lutpair560";
  attribute SOFT_HLUTNM of \wrdq_div1_4to1_wrcal_first.phy_wrdata[511]_i_2\ : label is "soft_lutpair565";
  attribute SOFT_HLUTNM of \wrdq_div1_4to1_wrcal_first.phy_wrdata[58]_i_1\ : label is "soft_lutpair557";
  attribute SOFT_HLUTNM of \wrdq_div1_4to1_wrcal_first.phy_wrdata[62]_i_1\ : label is "soft_lutpair569";
begin
  Q(0) <= \^q\(0);
\dout_o[0]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FCBBFC88"
    )
        port map (
      I0 => \dout_o[0]_i_2_n_0\,
      I1 => \rd_addr_reg_n_0_[6]\,
      I2 => \dout_o[0]_i_3_n_0\,
      I3 => \rd_addr_reg_n_0_[7]\,
      I4 => \dout_o[0]_i_4_n_0\,
      O => \dout_o[0]_i_1_n_0\
    );
\dout_o[0]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FBA702DC40FD7BA7"
    )
        port map (
      I0 => \rd_addr_reg_n_0_[5]\,
      I1 => \rd_addr_reg_n_0_[3]\,
      I2 => \rd_addr_reg_n_0_[2]\,
      I3 => \rd_addr_reg_n_0_[0]\,
      I4 => \^q\(0),
      I5 => \rd_addr_reg_n_0_[4]\,
      O => \dout_o[0]_i_2_n_0\
    );
\dout_o[0]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFF941DDE1"
    )
        port map (
      I0 => \rd_addr_reg_n_0_[4]\,
      I1 => \^q\(0),
      I2 => \rd_addr_reg_n_0_[0]\,
      I3 => \rd_addr_reg_n_0_[2]\,
      I4 => \rd_addr_reg_n_0_[3]\,
      I5 => \rd_addr_reg_n_0_[5]\,
      O => \dout_o[0]_i_3_n_0\
    );
\dout_o[0]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"5F74ABA8D4EB4862"
    )
        port map (
      I0 => \rd_addr_reg_n_0_[5]\,
      I1 => \rd_addr_reg_n_0_[3]\,
      I2 => \rd_addr_reg_n_0_[2]\,
      I3 => \rd_addr_reg_n_0_[0]\,
      I4 => \rd_addr_reg_n_0_[4]\,
      I5 => \^q\(0),
      O => \dout_o[0]_i_4_n_0\
    );
\dout_o[10]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"30BB3088"
    )
        port map (
      I0 => \dout_o[12]_i_2_n_0\,
      I1 => \rd_addr_reg_n_0_[6]\,
      I2 => \dout_o[10]_i_2_n_0\,
      I3 => \rd_addr_reg_n_0_[7]\,
      I4 => \dout_o[10]_i_3_n_0\,
      O => \dout_o[10]_i_1_n_0\
    );
\dout_o[10]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"000000004599CD27"
    )
        port map (
      I0 => \rd_addr_reg_n_0_[4]\,
      I1 => \^q\(0),
      I2 => \rd_addr_reg_n_0_[0]\,
      I3 => \rd_addr_reg_n_0_[2]\,
      I4 => \rd_addr_reg_n_0_[3]\,
      I5 => \rd_addr_reg_n_0_[5]\,
      O => \dout_o[10]_i_2_n_0\
    );
\dout_o[10]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"139126016C0923FA"
    )
        port map (
      I0 => \rd_addr_reg_n_0_[5]\,
      I1 => \rd_addr_reg_n_0_[3]\,
      I2 => \rd_addr_reg_n_0_[2]\,
      I3 => \rd_addr_reg_n_0_[0]\,
      I4 => \^q\(0),
      I5 => \rd_addr_reg_n_0_[4]\,
      O => \dout_o[10]_i_3_n_0\
    );
\dout_o[11]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"30BB3088"
    )
        port map (
      I0 => \dout_o[11]_i_2_n_0\,
      I1 => \rd_addr_reg_n_0_[6]\,
      I2 => \dout_o[11]_i_3_n_0\,
      I3 => \rd_addr_reg_n_0_[7]\,
      I4 => \dout_o[11]_i_4_n_0\,
      O => \dout_o[11]_i_1_n_0\
    );
\dout_o[11]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"713DD3CC4AE43A65"
    )
        port map (
      I0 => \rd_addr_reg_n_0_[5]\,
      I1 => \rd_addr_reg_n_0_[3]\,
      I2 => \rd_addr_reg_n_0_[2]\,
      I3 => \rd_addr_reg_n_0_[0]\,
      I4 => \rd_addr_reg_n_0_[4]\,
      I5 => \^q\(0),
      O => \dout_o[11]_i_2_n_0\
    );
\dout_o[11]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000322002AD"
    )
        port map (
      I0 => \^q\(0),
      I1 => \rd_addr_reg_n_0_[4]\,
      I2 => \rd_addr_reg_n_0_[0]\,
      I3 => \rd_addr_reg_n_0_[2]\,
      I4 => \rd_addr_reg_n_0_[3]\,
      I5 => \rd_addr_reg_n_0_[5]\,
      O => \dout_o[11]_i_3_n_0\
    );
\dout_o[11]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"7BB6E4333589857B"
    )
        port map (
      I0 => \rd_addr_reg_n_0_[5]\,
      I1 => \rd_addr_reg_n_0_[3]\,
      I2 => \rd_addr_reg_n_0_[2]\,
      I3 => \^q\(0),
      I4 => \rd_addr_reg_n_0_[4]\,
      I5 => \rd_addr_reg_n_0_[0]\,
      O => \dout_o[11]_i_4_n_0\
    );
\dout_o[12]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"30BB3088"
    )
        port map (
      I0 => \dout_o[12]_i_2_n_0\,
      I1 => \rd_addr_reg_n_0_[6]\,
      I2 => \dout_o[12]_i_3_n_0\,
      I3 => \rd_addr_reg_n_0_[7]\,
      I4 => \dout_o[12]_i_4_n_0\,
      O => \dout_o[12]_i_1_n_0\
    );
\dout_o[12]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"9100E82800132190"
    )
        port map (
      I0 => \rd_addr_reg_n_0_[5]\,
      I1 => \rd_addr_reg_n_0_[3]\,
      I2 => \rd_addr_reg_n_0_[2]\,
      I3 => \rd_addr_reg_n_0_[0]\,
      I4 => \rd_addr_reg_n_0_[4]\,
      I5 => \^q\(0),
      O => \dout_o[12]_i_2_n_0\
    );
\dout_o[12]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000031C1E208"
    )
        port map (
      I0 => \rd_addr_reg_n_0_[0]\,
      I1 => \rd_addr_reg_n_0_[4]\,
      I2 => \^q\(0),
      I3 => \rd_addr_reg_n_0_[2]\,
      I4 => \rd_addr_reg_n_0_[3]\,
      I5 => \rd_addr_reg_n_0_[5]\,
      O => \dout_o[12]_i_3_n_0\
    );
\dout_o[12]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"447C4014C71C60A6"
    )
        port map (
      I0 => \rd_addr_reg_n_0_[5]\,
      I1 => \rd_addr_reg_n_0_[3]\,
      I2 => \rd_addr_reg_n_0_[2]\,
      I3 => \rd_addr_reg_n_0_[4]\,
      I4 => \^q\(0),
      I5 => \rd_addr_reg_n_0_[0]\,
      O => \dout_o[12]_i_4_n_0\
    );
\dout_o[13]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"30BB3088"
    )
        port map (
      I0 => \dout_o[13]_i_2_n_0\,
      I1 => \rd_addr_reg_n_0_[6]\,
      I2 => \dout_o[13]_i_3_n_0\,
      I3 => \rd_addr_reg_n_0_[7]\,
      I4 => \dout_o[13]_i_4_n_0\,
      O => \dout_o[13]_i_1_n_0\
    );
\dout_o[13]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"5D37E7F8E29A3F4D"
    )
        port map (
      I0 => \rd_addr_reg_n_0_[5]\,
      I1 => \rd_addr_reg_n_0_[2]\,
      I2 => \rd_addr_reg_n_0_[3]\,
      I3 => \rd_addr_reg_n_0_[0]\,
      I4 => \rd_addr_reg_n_0_[4]\,
      I5 => \^q\(0),
      O => \dout_o[13]_i_2_n_0\
    );
\dout_o[13]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000040055161"
    )
        port map (
      I0 => \rd_addr_reg_n_0_[4]\,
      I1 => \^q\(0),
      I2 => \rd_addr_reg_n_0_[0]\,
      I3 => \rd_addr_reg_n_0_[2]\,
      I4 => \rd_addr_reg_n_0_[3]\,
      I5 => \rd_addr_reg_n_0_[5]\,
      O => \dout_o[13]_i_3_n_0\
    );
\dout_o[13]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"6EEDFF5CF2C694A7"
    )
        port map (
      I0 => \rd_addr_reg_n_0_[5]\,
      I1 => \rd_addr_reg_n_0_[3]\,
      I2 => \rd_addr_reg_n_0_[2]\,
      I3 => \rd_addr_reg_n_0_[0]\,
      I4 => \rd_addr_reg_n_0_[4]\,
      I5 => \^q\(0),
      O => \dout_o[13]_i_4_n_0\
    );
\dout_o[14]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"30BB3088"
    )
        port map (
      I0 => \dout_o[14]_i_2_n_0\,
      I1 => \rd_addr_reg_n_0_[6]\,
      I2 => \dout_o[14]_i_3_n_0\,
      I3 => \rd_addr_reg_n_0_[7]\,
      I4 => \dout_o[14]_i_4_n_0\,
      O => \dout_o[14]_i_1_n_0\
    );
\dout_o[14]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"9100682100130190"
    )
        port map (
      I0 => \rd_addr_reg_n_0_[5]\,
      I1 => \rd_addr_reg_n_0_[3]\,
      I2 => \rd_addr_reg_n_0_[2]\,
      I3 => \rd_addr_reg_n_0_[0]\,
      I4 => \rd_addr_reg_n_0_[4]\,
      I5 => \^q\(0),
      O => \dout_o[14]_i_2_n_0\
    );
\dout_o[14]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000118A8B19"
    )
        port map (
      I0 => \^q\(0),
      I1 => \rd_addr_reg_n_0_[4]\,
      I2 => \rd_addr_reg_n_0_[0]\,
      I3 => \rd_addr_reg_n_0_[2]\,
      I4 => \rd_addr_reg_n_0_[3]\,
      I5 => \rd_addr_reg_n_0_[5]\,
      O => \dout_o[14]_i_3_n_0\
    );
\dout_o[14]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"D473D375410D7424"
    )
        port map (
      I0 => \rd_addr_reg_n_0_[5]\,
      I1 => \rd_addr_reg_n_0_[3]\,
      I2 => \rd_addr_reg_n_0_[2]\,
      I3 => \rd_addr_reg_n_0_[4]\,
      I4 => \rd_addr_reg_n_0_[0]\,
      I5 => \^q\(0),
      O => \dout_o[14]_i_4_n_0\
    );
\dout_o[15]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"30BB3088"
    )
        port map (
      I0 => \dout_o[15]_i_2_n_0\,
      I1 => \rd_addr_reg_n_0_[6]\,
      I2 => \dout_o[15]_i_3_n_0\,
      I3 => \rd_addr_reg_n_0_[7]\,
      I4 => \dout_o[15]_i_4_n_0\,
      O => \dout_o[15]_i_1_n_0\
    );
\dout_o[15]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"5D27F5EADA9A3F4D"
    )
        port map (
      I0 => \rd_addr_reg_n_0_[5]\,
      I1 => \rd_addr_reg_n_0_[2]\,
      I2 => \rd_addr_reg_n_0_[3]\,
      I3 => \rd_addr_reg_n_0_[0]\,
      I4 => \rd_addr_reg_n_0_[4]\,
      I5 => \^q\(0),
      O => \dout_o[15]_i_2_n_0\
    );
\dout_o[15]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"000000004115533E"
    )
        port map (
      I0 => \rd_addr_reg_n_0_[4]\,
      I1 => \^q\(0),
      I2 => \rd_addr_reg_n_0_[0]\,
      I3 => \rd_addr_reg_n_0_[2]\,
      I4 => \rd_addr_reg_n_0_[3]\,
      I5 => \rd_addr_reg_n_0_[5]\,
      O => \dout_o[15]_i_3_n_0\
    );
\dout_o[15]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"5EF9FF567BFFCDB5"
    )
        port map (
      I0 => \rd_addr_reg_n_0_[5]\,
      I1 => \rd_addr_reg_n_0_[3]\,
      I2 => \rd_addr_reg_n_0_[2]\,
      I3 => \rd_addr_reg_n_0_[0]\,
      I4 => \^q\(0),
      I5 => \rd_addr_reg_n_0_[4]\,
      O => \dout_o[15]_i_4_n_0\
    );
\dout_o[1]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"30BB3088"
    )
        port map (
      I0 => \dout_o[1]_i_2_n_0\,
      I1 => \rd_addr_reg_n_0_[6]\,
      I2 => \dout_o[1]_i_3_n_0\,
      I3 => \rd_addr_reg_n_0_[7]\,
      I4 => \dout_o[1]_i_4_n_0\,
      O => \dout_o[1]_i_1_n_0\
    );
\dout_o[1]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"E7E55AE75A58865A"
    )
        port map (
      I0 => \rd_addr_reg_n_0_[5]\,
      I1 => \rd_addr_reg_n_0_[3]\,
      I2 => \rd_addr_reg_n_0_[2]\,
      I3 => \rd_addr_reg_n_0_[4]\,
      I4 => \^q\(0),
      I5 => \rd_addr_reg_n_0_[0]\,
      O => \dout_o[1]_i_2_n_0\
    );
\dout_o[1]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000051880521"
    )
        port map (
      I0 => \rd_addr_reg_n_0_[4]\,
      I1 => \^q\(0),
      I2 => \rd_addr_reg_n_0_[0]\,
      I3 => \rd_addr_reg_n_0_[2]\,
      I4 => \rd_addr_reg_n_0_[3]\,
      I5 => \rd_addr_reg_n_0_[5]\,
      O => \dout_o[1]_i_3_n_0\
    );
\dout_o[1]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"7ADF52E8C4A8E711"
    )
        port map (
      I0 => \rd_addr_reg_n_0_[5]\,
      I1 => \rd_addr_reg_n_0_[3]\,
      I2 => \rd_addr_reg_n_0_[4]\,
      I3 => \rd_addr_reg_n_0_[2]\,
      I4 => \rd_addr_reg_n_0_[0]\,
      I5 => \^q\(0),
      O => \dout_o[1]_i_4_n_0\
    );
\dout_o[2]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"30BB3088"
    )
        port map (
      I0 => \dout_o[2]_i_2_n_0\,
      I1 => \rd_addr_reg_n_0_[6]\,
      I2 => \dout_o[2]_i_3_n_0\,
      I3 => \rd_addr_reg_n_0_[7]\,
      I4 => \dout_o[2]_i_4_n_0\,
      O => \dout_o[2]_i_1_n_0\
    );
\dout_o[2]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FB02235842E57B02"
    )
        port map (
      I0 => \rd_addr_reg_n_0_[5]\,
      I1 => \rd_addr_reg_n_0_[3]\,
      I2 => \rd_addr_reg_n_0_[2]\,
      I3 => \rd_addr_reg_n_0_[0]\,
      I4 => \^q\(0),
      I5 => \rd_addr_reg_n_0_[4]\,
      O => \dout_o[2]_i_2_n_0\
    );
\dout_o[2]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000020DCBD5"
    )
        port map (
      I0 => \rd_addr_reg_n_0_[0]\,
      I1 => \^q\(0),
      I2 => \rd_addr_reg_n_0_[4]\,
      I3 => \rd_addr_reg_n_0_[2]\,
      I4 => \rd_addr_reg_n_0_[3]\,
      I5 => \rd_addr_reg_n_0_[5]\,
      O => \dout_o[2]_i_3_n_0\
    );
\dout_o[2]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"CF45D0CFCE2B8950"
    )
        port map (
      I0 => \rd_addr_reg_n_0_[5]\,
      I1 => \rd_addr_reg_n_0_[3]\,
      I2 => \rd_addr_reg_n_0_[2]\,
      I3 => \rd_addr_reg_n_0_[0]\,
      I4 => \^q\(0),
      I5 => \rd_addr_reg_n_0_[4]\,
      O => \dout_o[2]_i_4_n_0\
    );
\dout_o[3]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"30BB3088"
    )
        port map (
      I0 => \dout_o[3]_i_2_n_0\,
      I1 => \rd_addr_reg_n_0_[6]\,
      I2 => \dout_o[3]_i_3_n_0\,
      I3 => \rd_addr_reg_n_0_[7]\,
      I4 => \dout_o[3]_i_4_n_0\,
      O => \dout_o[3]_i_1_n_0\
    );
\dout_o[3]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"46E55AC658188658"
    )
        port map (
      I0 => \rd_addr_reg_n_0_[5]\,
      I1 => \rd_addr_reg_n_0_[3]\,
      I2 => \rd_addr_reg_n_0_[2]\,
      I3 => \rd_addr_reg_n_0_[4]\,
      I4 => \^q\(0),
      I5 => \rd_addr_reg_n_0_[0]\,
      O => \dout_o[3]_i_2_n_0\
    );
\dout_o[3]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000019C0421"
    )
        port map (
      I0 => \rd_addr_reg_n_0_[4]\,
      I1 => \^q\(0),
      I2 => \rd_addr_reg_n_0_[0]\,
      I3 => \rd_addr_reg_n_0_[2]\,
      I4 => \rd_addr_reg_n_0_[3]\,
      I5 => \rd_addr_reg_n_0_[5]\,
      O => \dout_o[3]_i_3_n_0\
    );
\dout_o[3]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"2DCA4E194B652751"
    )
        port map (
      I0 => \rd_addr_reg_n_0_[5]\,
      I1 => \rd_addr_reg_n_0_[3]\,
      I2 => \rd_addr_reg_n_0_[2]\,
      I3 => \^q\(0),
      I4 => \rd_addr_reg_n_0_[4]\,
      I5 => \rd_addr_reg_n_0_[0]\,
      O => \dout_o[3]_i_4_n_0\
    );
\dout_o[4]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"30BB3088"
    )
        port map (
      I0 => \dout_o[4]_i_2_n_0\,
      I1 => \rd_addr_reg_n_0_[6]\,
      I2 => \dout_o[4]_i_3_n_0\,
      I3 => \rd_addr_reg_n_0_[7]\,
      I4 => \dout_o[4]_i_4_n_0\,
      O => \dout_o[4]_i_1_n_0\
    );
\dout_o[4]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"D87BBD58DE86587B"
    )
        port map (
      I0 => \rd_addr_reg_n_0_[5]\,
      I1 => \rd_addr_reg_n_0_[3]\,
      I2 => \rd_addr_reg_n_0_[2]\,
      I3 => \rd_addr_reg_n_0_[0]\,
      I4 => \rd_addr_reg_n_0_[4]\,
      I5 => \^q\(0),
      O => \dout_o[4]_i_2_n_0\
    );
\dout_o[4]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"000000000455F0E2"
    )
        port map (
      I0 => \rd_addr_reg_n_0_[4]\,
      I1 => \rd_addr_reg_n_0_[0]\,
      I2 => \^q\(0),
      I3 => \rd_addr_reg_n_0_[2]\,
      I4 => \rd_addr_reg_n_0_[3]\,
      I5 => \rd_addr_reg_n_0_[5]\,
      O => \dout_o[4]_i_3_n_0\
    );
\dout_o[4]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"1A563E3E1BBEA40C"
    )
        port map (
      I0 => \rd_addr_reg_n_0_[5]\,
      I1 => \rd_addr_reg_n_0_[3]\,
      I2 => \rd_addr_reg_n_0_[2]\,
      I3 => \rd_addr_reg_n_0_[4]\,
      I4 => \^q\(0),
      I5 => \rd_addr_reg_n_0_[0]\,
      O => \dout_o[4]_i_4_n_0\
    );
\dout_o[5]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"30BB3088"
    )
        port map (
      I0 => \dout_o[5]_i_2_n_0\,
      I1 => \rd_addr_reg_n_0_[6]\,
      I2 => \dout_o[5]_i_3_n_0\,
      I3 => \rd_addr_reg_n_0_[7]\,
      I4 => \dout_o[5]_i_4_n_0\,
      O => \dout_o[5]_i_1_n_0\
    );
\dout_o[5]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"42588642FDA55AFD"
    )
        port map (
      I0 => \rd_addr_reg_n_0_[5]\,
      I1 => \rd_addr_reg_n_0_[3]\,
      I2 => \rd_addr_reg_n_0_[2]\,
      I3 => \rd_addr_reg_n_0_[4]\,
      I4 => \^q\(0),
      I5 => \rd_addr_reg_n_0_[0]\,
      O => \dout_o[5]_i_2_n_0\
    );
\dout_o[5]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000013A810A9"
    )
        port map (
      I0 => \^q\(0),
      I1 => \rd_addr_reg_n_0_[4]\,
      I2 => \rd_addr_reg_n_0_[0]\,
      I3 => \rd_addr_reg_n_0_[2]\,
      I4 => \rd_addr_reg_n_0_[3]\,
      I5 => \rd_addr_reg_n_0_[5]\,
      O => \dout_o[5]_i_3_n_0\
    );
\dout_o[5]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"183B5DF6A40A3E0D"
    )
        port map (
      I0 => \rd_addr_reg_n_0_[5]\,
      I1 => \rd_addr_reg_n_0_[3]\,
      I2 => \rd_addr_reg_n_0_[2]\,
      I3 => \rd_addr_reg_n_0_[0]\,
      I4 => \rd_addr_reg_n_0_[4]\,
      I5 => \^q\(0),
      O => \dout_o[5]_i_4_n_0\
    );
\dout_o[6]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"30BB3088"
    )
        port map (
      I0 => \dout_o[6]_i_2_n_0\,
      I1 => \rd_addr_reg_n_0_[6]\,
      I2 => \dout_o[6]_i_3_n_0\,
      I3 => \rd_addr_reg_n_0_[7]\,
      I4 => \dout_o[6]_i_4_n_0\,
      O => \dout_o[6]_i_1_n_0\
    );
\dout_o[6]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"A35A585A84A7235A"
    )
        port map (
      I0 => \rd_addr_reg_n_0_[5]\,
      I1 => \rd_addr_reg_n_0_[3]\,
      I2 => \rd_addr_reg_n_0_[2]\,
      I3 => \rd_addr_reg_n_0_[0]\,
      I4 => \rd_addr_reg_n_0_[4]\,
      I5 => \^q\(0),
      O => \dout_o[6]_i_2_n_0\
    );
\dout_o[6]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"000000004441C9B1"
    )
        port map (
      I0 => \rd_addr_reg_n_0_[4]\,
      I1 => \^q\(0),
      I2 => \rd_addr_reg_n_0_[0]\,
      I3 => \rd_addr_reg_n_0_[2]\,
      I4 => \rd_addr_reg_n_0_[3]\,
      I5 => \rd_addr_reg_n_0_[5]\,
      O => \dout_o[6]_i_3_n_0\
    );
\dout_o[6]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00D98F5FB527B08E"
    )
        port map (
      I0 => \rd_addr_reg_n_0_[5]\,
      I1 => \rd_addr_reg_n_0_[3]\,
      I2 => \rd_addr_reg_n_0_[2]\,
      I3 => \rd_addr_reg_n_0_[4]\,
      I4 => \rd_addr_reg_n_0_[0]\,
      I5 => \^q\(0),
      O => \dout_o[6]_i_4_n_0\
    );
\dout_o[7]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"30BB3088"
    )
        port map (
      I0 => \dout_o[7]_i_2_n_0\,
      I1 => \rd_addr_reg_n_0_[6]\,
      I2 => \dout_o[7]_i_3_n_0\,
      I3 => \rd_addr_reg_n_0_[7]\,
      I4 => \dout_o[7]_i_4_n_0\,
      O => \dout_o[7]_i_1_n_0\
    );
\dout_o[7]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"5C00BF1AFFA5DC00"
    )
        port map (
      I0 => \rd_addr_reg_n_0_[5]\,
      I1 => \rd_addr_reg_n_0_[3]\,
      I2 => \rd_addr_reg_n_0_[2]\,
      I3 => \rd_addr_reg_n_0_[0]\,
      I4 => \rd_addr_reg_n_0_[4]\,
      I5 => \^q\(0),
      O => \dout_o[7]_i_2_n_0\
    );
\dout_o[7]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000016D00494"
    )
        port map (
      I0 => \rd_addr_reg_n_0_[4]\,
      I1 => \^q\(0),
      I2 => \rd_addr_reg_n_0_[0]\,
      I3 => \rd_addr_reg_n_0_[2]\,
      I4 => \rd_addr_reg_n_0_[3]\,
      I5 => \rd_addr_reg_n_0_[5]\,
      O => \dout_o[7]_i_3_n_0\
    );
\dout_o[7]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AA852B305155E79F"
    )
        port map (
      I0 => \rd_addr_reg_n_0_[5]\,
      I1 => \rd_addr_reg_n_0_[3]\,
      I2 => \rd_addr_reg_n_0_[2]\,
      I3 => \rd_addr_reg_n_0_[0]\,
      I4 => \^q\(0),
      I5 => \rd_addr_reg_n_0_[4]\,
      O => \dout_o[7]_i_4_n_0\
    );
\dout_o[8]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FCBBFC88"
    )
        port map (
      I0 => \dout_o[8]_i_2_n_0\,
      I1 => \rd_addr_reg_n_0_[6]\,
      I2 => \dout_o[8]_i_3_n_0\,
      I3 => \rd_addr_reg_n_0_[7]\,
      I4 => \dout_o[8]_i_4_n_0\,
      O => \dout_o[8]_i_1_n_0\
    );
\dout_o[8]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"91C9002800211311"
    )
        port map (
      I0 => \rd_addr_reg_n_0_[5]\,
      I1 => \rd_addr_reg_n_0_[3]\,
      I2 => \rd_addr_reg_n_0_[2]\,
      I3 => \rd_addr_reg_n_0_[4]\,
      I4 => \rd_addr_reg_n_0_[0]\,
      I5 => \^q\(0),
      O => \dout_o[8]_i_2_n_0\
    );
\dout_o[8]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFD8D3F245"
    )
        port map (
      I0 => \rd_addr_reg_n_0_[0]\,
      I1 => \rd_addr_reg_n_0_[4]\,
      I2 => \^q\(0),
      I3 => \rd_addr_reg_n_0_[2]\,
      I4 => \rd_addr_reg_n_0_[3]\,
      I5 => \rd_addr_reg_n_0_[5]\,
      O => \dout_o[8]_i_3_n_0\
    );
\dout_o[8]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0A06800432120528"
    )
        port map (
      I0 => \rd_addr_reg_n_0_[5]\,
      I1 => \rd_addr_reg_n_0_[3]\,
      I2 => \^q\(0),
      I3 => \rd_addr_reg_n_0_[4]\,
      I4 => \rd_addr_reg_n_0_[0]\,
      I5 => \rd_addr_reg_n_0_[2]\,
      O => \dout_o[8]_i_4_n_0\
    );
\dout_o[9]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"30BB3088"
    )
        port map (
      I0 => \dout_o[9]_i_2_n_0\,
      I1 => \rd_addr_reg_n_0_[6]\,
      I2 => \dout_o[9]_i_3_n_0\,
      I3 => \rd_addr_reg_n_0_[7]\,
      I4 => \dout_o[9]_i_4_n_0\,
      O => \dout_o[9]_i_1_n_0\
    );
\dout_o[9]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F3F5C3DC0AE47A65"
    )
        port map (
      I0 => \rd_addr_reg_n_0_[5]\,
      I1 => \rd_addr_reg_n_0_[3]\,
      I2 => \rd_addr_reg_n_0_[2]\,
      I3 => \rd_addr_reg_n_0_[0]\,
      I4 => \rd_addr_reg_n_0_[4]\,
      I5 => \^q\(0),
      O => \dout_o[9]_i_2_n_0\
    );
\dout_o[9]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000040E06D5"
    )
        port map (
      I0 => \rd_addr_reg_n_0_[0]\,
      I1 => \^q\(0),
      I2 => \rd_addr_reg_n_0_[4]\,
      I3 => \rd_addr_reg_n_0_[2]\,
      I4 => \rd_addr_reg_n_0_[3]\,
      I5 => \rd_addr_reg_n_0_[5]\,
      O => \dout_o[9]_i_3_n_0\
    );
\dout_o[9]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"20350802BEE285FB"
    )
        port map (
      I0 => \rd_addr_reg_n_0_[5]\,
      I1 => \rd_addr_reg_n_0_[3]\,
      I2 => \rd_addr_reg_n_0_[4]\,
      I3 => \rd_addr_reg_n_0_[2]\,
      I4 => \rd_addr_reg_n_0_[0]\,
      I5 => \^q\(0),
      O => \dout_o[9]_i_4_n_0\
    );
\dout_o_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \dout_o_reg[15]_2\,
      CE => '1',
      D => \dout_o[0]_i_1_n_0\,
      Q => \dout_o_reg_n_0_[0]\,
      R => '0'
    );
\dout_o_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => \dout_o_reg[15]_2\,
      CE => '1',
      D => \dout_o[10]_i_1_n_0\,
      Q => p_1_in772_in,
      R => '0'
    );
\dout_o_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => \dout_o_reg[15]_2\,
      CE => '1',
      D => \dout_o[11]_i_1_n_0\,
      Q => p_1_in642_in,
      R => '0'
    );
\dout_o_reg[12]\: unisim.vcomponents.FDRE
     port map (
      C => \dout_o_reg[15]_2\,
      CE => '1',
      D => \dout_o[12]_i_1_n_0\,
      Q => p_1_in512_in,
      R => '0'
    );
\dout_o_reg[13]\: unisim.vcomponents.FDRE
     port map (
      C => \dout_o_reg[15]_2\,
      CE => '1',
      D => \dout_o[13]_i_1_n_0\,
      Q => p_1_in382_in,
      R => '0'
    );
\dout_o_reg[14]\: unisim.vcomponents.FDRE
     port map (
      C => \dout_o_reg[15]_2\,
      CE => '1',
      D => \dout_o[14]_i_1_n_0\,
      Q => p_1_in252_in,
      R => '0'
    );
\dout_o_reg[15]\: unisim.vcomponents.FDRE
     port map (
      C => \dout_o_reg[15]_2\,
      CE => '1',
      D => \dout_o[15]_i_1_n_0\,
      Q => p_1_in,
      R => '0'
    );
\dout_o_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \dout_o_reg[15]_2\,
      CE => '1',
      D => \dout_o[1]_i_1_n_0\,
      Q => p_2_in904_in,
      R => '0'
    );
\dout_o_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \dout_o_reg[15]_2\,
      CE => '1',
      D => \dout_o[2]_i_1_n_0\,
      Q => p_2_in774_in,
      R => '0'
    );
\dout_o_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => \dout_o_reg[15]_2\,
      CE => '1',
      D => \dout_o[3]_i_1_n_0\,
      Q => p_2_in644_in,
      R => '0'
    );
\dout_o_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => \dout_o_reg[15]_2\,
      CE => '1',
      D => \dout_o[4]_i_1_n_0\,
      Q => p_2_in514_in,
      R => '0'
    );
\dout_o_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => \dout_o_reg[15]_2\,
      CE => '1',
      D => \dout_o[5]_i_1_n_0\,
      Q => p_2_in384_in,
      R => '0'
    );
\dout_o_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => \dout_o_reg[15]_2\,
      CE => '1',
      D => \dout_o[6]_i_1_n_0\,
      Q => p_2_in254_in,
      R => '0'
    );
\dout_o_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => \dout_o_reg[15]_2\,
      CE => '1',
      D => \dout_o[7]_i_1_n_0\,
      Q => p_2_in,
      R => '0'
    );
\dout_o_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => \dout_o_reg[15]_2\,
      CE => '1',
      D => \dout_o[8]_i_1_n_0\,
      Q => p_1_in1032_in,
      R => '0'
    );
\dout_o_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => \dout_o_reg[15]_2\,
      CE => '1',
      D => \dout_o[9]_i_1_n_0\,
      Q => p_1_in902_in,
      R => '0'
    );
\gen_mux_rd[0].compare_data_fall0_r1[0]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => p_2_in254_in,
      I1 => p_0_in222_in,
      I2 => p_1_in252_in,
      O => prbs_out(8)
    );
\gen_mux_rd[0].compare_data_fall1_r1[0]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => p_2_in514_in,
      I1 => p_0_in222_in,
      I2 => p_1_in512_in,
      O => prbs_out(24)
    );
\gen_mux_rd[0].compare_data_fall2_r1[0]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => p_2_in774_in,
      I1 => p_0_in222_in,
      I2 => p_1_in772_in,
      O => prbs_out(40)
    );
\gen_mux_rd[0].compare_data_fall3_r1[0]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \dout_o_reg_n_0_[0]\,
      I1 => p_0_in222_in,
      I2 => p_1_in1032_in,
      O => prbs_out(56)
    );
\gen_mux_rd[0].compare_data_rise0_r1[0]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => p_2_in,
      I1 => p_0_in222_in,
      I2 => p_1_in,
      O => prbs_out(0)
    );
\gen_mux_rd[0].compare_data_rise1_r1[0]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => p_2_in384_in,
      I1 => p_0_in222_in,
      I2 => p_1_in382_in,
      O => prbs_out(16)
    );
\gen_mux_rd[0].compare_data_rise2_r1[0]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => p_2_in644_in,
      I1 => p_0_in222_in,
      I2 => p_1_in642_in,
      O => prbs_out(32)
    );
\gen_mux_rd[0].compare_data_rise3_r1[0]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => p_2_in904_in,
      I1 => p_0_in222_in,
      I2 => p_1_in902_in,
      O => prbs_out(48)
    );
\gen_mux_rd[1].compare_data_fall0_r1[1]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => p_2_in254_in,
      I1 => p_0_in226_in,
      I2 => p_1_in252_in,
      O => prbs_out(9)
    );
\gen_mux_rd[1].compare_data_fall1_r1[1]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => p_2_in514_in,
      I1 => p_0_in226_in,
      I2 => p_1_in512_in,
      O => prbs_out(25)
    );
\gen_mux_rd[1].compare_data_fall2_r1[1]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => p_2_in774_in,
      I1 => p_0_in226_in,
      I2 => p_1_in772_in,
      O => prbs_out(41)
    );
\gen_mux_rd[1].compare_data_fall3_r1[1]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \dout_o_reg_n_0_[0]\,
      I1 => p_0_in226_in,
      I2 => p_1_in1032_in,
      O => prbs_out(57)
    );
\gen_mux_rd[1].compare_data_rise0_r1[1]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => p_2_in,
      I1 => p_0_in226_in,
      I2 => p_1_in,
      O => prbs_out(1)
    );
\gen_mux_rd[1].compare_data_rise1_r1[1]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => p_2_in384_in,
      I1 => p_0_in226_in,
      I2 => p_1_in382_in,
      O => prbs_out(17)
    );
\gen_mux_rd[1].compare_data_rise2_r1[1]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => p_2_in644_in,
      I1 => p_0_in226_in,
      I2 => p_1_in642_in,
      O => prbs_out(33)
    );
\gen_mux_rd[1].compare_data_rise3_r1[1]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => p_2_in904_in,
      I1 => p_0_in226_in,
      I2 => p_1_in902_in,
      O => prbs_out(49)
    );
\gen_mux_rd[2].compare_data_fall0_r1[2]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => p_2_in254_in,
      I1 => p_0_in230_in,
      I2 => p_1_in252_in,
      O => prbs_out(10)
    );
\gen_mux_rd[2].compare_data_fall1_r1[2]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => p_2_in514_in,
      I1 => p_0_in230_in,
      I2 => p_1_in512_in,
      O => prbs_out(26)
    );
\gen_mux_rd[2].compare_data_fall2_r1[2]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => p_2_in774_in,
      I1 => p_0_in230_in,
      I2 => p_1_in772_in,
      O => prbs_out(42)
    );
\gen_mux_rd[2].compare_data_fall3_r1[2]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \dout_o_reg_n_0_[0]\,
      I1 => p_0_in230_in,
      I2 => p_1_in1032_in,
      O => prbs_out(58)
    );
\gen_mux_rd[2].compare_data_rise0_r1[2]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => p_2_in,
      I1 => p_0_in230_in,
      I2 => p_1_in,
      O => prbs_out(2)
    );
\gen_mux_rd[2].compare_data_rise1_r1[2]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => p_2_in384_in,
      I1 => p_0_in230_in,
      I2 => p_1_in382_in,
      O => prbs_out(18)
    );
\gen_mux_rd[2].compare_data_rise2_r1[2]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => p_2_in644_in,
      I1 => p_0_in230_in,
      I2 => p_1_in642_in,
      O => prbs_out(34)
    );
\gen_mux_rd[2].compare_data_rise3_r1[2]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => p_2_in904_in,
      I1 => p_0_in230_in,
      I2 => p_1_in902_in,
      O => prbs_out(50)
    );
\gen_mux_rd[3].compare_data_fall0_r1[3]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => p_2_in254_in,
      I1 => p_0_in234_in,
      I2 => p_1_in252_in,
      O => prbs_out(11)
    );
\gen_mux_rd[3].compare_data_fall1_r1[3]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => p_2_in514_in,
      I1 => p_0_in234_in,
      I2 => p_1_in512_in,
      O => prbs_out(27)
    );
\gen_mux_rd[3].compare_data_fall2_r1[3]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => p_2_in774_in,
      I1 => p_0_in234_in,
      I2 => p_1_in772_in,
      O => prbs_out(43)
    );
\gen_mux_rd[3].compare_data_fall3_r1[3]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \dout_o_reg_n_0_[0]\,
      I1 => p_0_in234_in,
      I2 => p_1_in1032_in,
      O => prbs_out(59)
    );
\gen_mux_rd[3].compare_data_rise0_r1[3]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => p_2_in,
      I1 => p_0_in234_in,
      I2 => p_1_in,
      O => prbs_out(3)
    );
\gen_mux_rd[3].compare_data_rise1_r1[3]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => p_2_in384_in,
      I1 => p_0_in234_in,
      I2 => p_1_in382_in,
      O => prbs_out(19)
    );
\gen_mux_rd[3].compare_data_rise2_r1[3]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => p_2_in644_in,
      I1 => p_0_in234_in,
      I2 => p_1_in642_in,
      O => prbs_out(35)
    );
\gen_mux_rd[3].compare_data_rise3_r1[3]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => p_2_in904_in,
      I1 => p_0_in234_in,
      I2 => p_1_in902_in,
      O => prbs_out(51)
    );
\gen_mux_rd[4].compare_data_fall0_r1[4]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => p_2_in254_in,
      I1 => p_0_in238_in,
      I2 => p_1_in252_in,
      O => prbs_out(12)
    );
\gen_mux_rd[4].compare_data_fall1_r1[4]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => p_2_in514_in,
      I1 => p_0_in238_in,
      I2 => p_1_in512_in,
      O => prbs_out(28)
    );
\gen_mux_rd[4].compare_data_fall2_r1[4]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => p_2_in774_in,
      I1 => p_0_in238_in,
      I2 => p_1_in772_in,
      O => prbs_out(44)
    );
\gen_mux_rd[4].compare_data_fall3_r1[4]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \dout_o_reg_n_0_[0]\,
      I1 => p_0_in238_in,
      I2 => p_1_in1032_in,
      O => prbs_out(60)
    );
\gen_mux_rd[4].compare_data_rise0_r1[4]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => p_2_in,
      I1 => p_0_in238_in,
      I2 => p_1_in,
      O => prbs_out(4)
    );
\gen_mux_rd[4].compare_data_rise1_r1[4]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => p_2_in384_in,
      I1 => p_0_in238_in,
      I2 => p_1_in382_in,
      O => prbs_out(20)
    );
\gen_mux_rd[4].compare_data_rise2_r1[4]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => p_2_in644_in,
      I1 => p_0_in238_in,
      I2 => p_1_in642_in,
      O => prbs_out(36)
    );
\gen_mux_rd[4].compare_data_rise3_r1[4]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => p_2_in904_in,
      I1 => p_0_in238_in,
      I2 => p_1_in902_in,
      O => prbs_out(52)
    );
\gen_mux_rd[5].compare_data_fall0_r1[5]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => p_2_in254_in,
      I1 => p_0_in242_in,
      I2 => p_1_in252_in,
      O => prbs_out(13)
    );
\gen_mux_rd[5].compare_data_fall1_r1[5]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => p_2_in514_in,
      I1 => p_0_in242_in,
      I2 => p_1_in512_in,
      O => prbs_out(29)
    );
\gen_mux_rd[5].compare_data_fall2_r1[5]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => p_2_in774_in,
      I1 => p_0_in242_in,
      I2 => p_1_in772_in,
      O => prbs_out(45)
    );
\gen_mux_rd[5].compare_data_fall3_r1[5]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \dout_o_reg_n_0_[0]\,
      I1 => p_0_in242_in,
      I2 => p_1_in1032_in,
      O => prbs_out(61)
    );
\gen_mux_rd[5].compare_data_rise0_r1[5]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => p_2_in,
      I1 => p_0_in242_in,
      I2 => p_1_in,
      O => prbs_out(5)
    );
\gen_mux_rd[5].compare_data_rise1_r1[5]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => p_2_in384_in,
      I1 => p_0_in242_in,
      I2 => p_1_in382_in,
      O => prbs_out(21)
    );
\gen_mux_rd[5].compare_data_rise2_r1[5]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => p_2_in644_in,
      I1 => p_0_in242_in,
      I2 => p_1_in642_in,
      O => prbs_out(37)
    );
\gen_mux_rd[5].compare_data_rise3_r1[5]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => p_2_in904_in,
      I1 => p_0_in242_in,
      I2 => p_1_in902_in,
      O => prbs_out(53)
    );
\gen_mux_rd[6].compare_data_fall0_r1[6]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => p_2_in254_in,
      I1 => p_0_in246_in,
      I2 => p_1_in252_in,
      O => prbs_out(14)
    );
\gen_mux_rd[6].compare_data_fall1_r1[6]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => p_2_in514_in,
      I1 => p_0_in246_in,
      I2 => p_1_in512_in,
      O => prbs_out(30)
    );
\gen_mux_rd[6].compare_data_fall2_r1[6]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => p_2_in774_in,
      I1 => p_0_in246_in,
      I2 => p_1_in772_in,
      O => prbs_out(46)
    );
\gen_mux_rd[6].compare_data_fall3_r1[6]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \dout_o_reg_n_0_[0]\,
      I1 => p_0_in246_in,
      I2 => p_1_in1032_in,
      O => prbs_out(62)
    );
\gen_mux_rd[6].compare_data_rise0_r1[6]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => p_2_in,
      I1 => p_0_in246_in,
      I2 => p_1_in,
      O => prbs_out(6)
    );
\gen_mux_rd[6].compare_data_rise1_r1[6]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => p_2_in384_in,
      I1 => p_0_in246_in,
      I2 => p_1_in382_in,
      O => prbs_out(22)
    );
\gen_mux_rd[6].compare_data_rise2_r1[6]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => p_2_in644_in,
      I1 => p_0_in246_in,
      I2 => p_1_in642_in,
      O => prbs_out(38)
    );
\gen_mux_rd[6].compare_data_rise3_r1[6]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => p_2_in904_in,
      I1 => p_0_in246_in,
      I2 => p_1_in902_in,
      O => prbs_out(54)
    );
\gen_mux_rd[7].compare_data_fall0_r1[7]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => p_2_in254_in,
      I1 => p_0_in250_in,
      I2 => p_1_in252_in,
      O => prbs_out(15)
    );
\gen_mux_rd[7].compare_data_fall1_r1[7]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => p_2_in514_in,
      I1 => p_0_in250_in,
      I2 => p_1_in512_in,
      O => prbs_out(31)
    );
\gen_mux_rd[7].compare_data_fall2_r1[7]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => p_2_in774_in,
      I1 => p_0_in250_in,
      I2 => p_1_in772_in,
      O => prbs_out(47)
    );
\gen_mux_rd[7].compare_data_fall3_r1[7]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \dout_o_reg_n_0_[0]\,
      I1 => p_0_in250_in,
      I2 => p_1_in1032_in,
      O => prbs_out(63)
    );
\gen_mux_rd[7].compare_data_rise0_r1[7]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => p_2_in,
      I1 => p_0_in250_in,
      I2 => p_1_in,
      O => prbs_out(7)
    );
\gen_mux_rd[7].compare_data_rise1_r1[7]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => p_2_in384_in,
      I1 => p_0_in250_in,
      I2 => p_1_in382_in,
      O => prbs_out(23)
    );
\gen_mux_rd[7].compare_data_rise2_r1[7]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => p_2_in644_in,
      I1 => p_0_in250_in,
      I2 => p_1_in642_in,
      O => prbs_out(39)
    );
\gen_mux_rd[7].compare_data_rise3_r1[7]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => p_2_in904_in,
      I1 => p_0_in250_in,
      I2 => p_1_in902_in,
      O => prbs_out(55)
    );
phy_if_empty_r_reg: unisim.vcomponents.FDRE
     port map (
      C => \dout_o_reg[15]_2\,
      CE => '1',
      D => if_empty,
      Q => phy_if_empty_r_reg_0,
      R => '0'
    );
\rd_addr[0]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"3233"
    )
        port map (
      I0 => \rd_addr[2]_i_2_n_0\,
      I1 => \rd_addr_reg_n_0_[0]\,
      I2 => \^q\(0),
      I3 => \rd_addr_reg_n_0_[2]\,
      O => \p_1_in__0\(0)
    );
\rd_addr[1]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \rd_addr_reg_n_0_[0]\,
      I1 => \^q\(0),
      O => \p_1_in__0\(1)
    );
\rd_addr[2]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7868"
    )
        port map (
      I0 => \rd_addr_reg_n_0_[0]\,
      I1 => \^q\(0),
      I2 => \rd_addr_reg_n_0_[2]\,
      I3 => \rd_addr[2]_i_2_n_0\,
      O => \p_1_in__0\(2)
    );
\rd_addr[2]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFF7FFF7FFFF"
    )
        port map (
      I0 => \rd_addr_reg_n_0_[4]\,
      I1 => \rd_addr_reg_n_0_[7]\,
      I2 => \rd_addr_reg_n_0_[5]\,
      I3 => \rd_addr_reg_n_0_[6]\,
      I4 => \rd_addr_reg[0]_0\,
      I5 => \rd_addr_reg_n_0_[3]\,
      O => \rd_addr[2]_i_2_n_0\
    );
\rd_addr[3]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"BFFFFFBFFAAAAAAA"
    )
        port map (
      I0 => \rd_addr[3]_i_2_n_0\,
      I1 => \rd_addr_reg[3]_0\,
      I2 => \rd_addr_reg_n_0_[2]\,
      I3 => \rd_addr_reg_n_0_[0]\,
      I4 => \^q\(0),
      I5 => \rd_addr_reg_n_0_[3]\,
      O => \p_1_in__0\(3)
    );
\rd_addr[3]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"4444444444440444"
    )
        port map (
      I0 => \^q\(0),
      I1 => \rd_addr_reg_n_0_[3]\,
      I2 => \rd_addr_reg_n_0_[7]\,
      I3 => \rd_addr_reg_n_0_[4]\,
      I4 => \rd_addr_reg_n_0_[5]\,
      I5 => \rd_addr_reg_n_0_[6]\,
      O => \rd_addr[3]_i_2_n_0\
    );
\rd_addr[4]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFF2222000F2222"
    )
        port map (
      I0 => \rd_addr_reg_n_0_[3]\,
      I1 => \rd_addr[4]_i_2_n_0\,
      I2 => \rd_addr_reg_n_0_[7]\,
      I3 => \^q\(0),
      I4 => \rd_addr_reg_n_0_[4]\,
      I5 => \rd_addr[7]_i_4_n_0\,
      O => \p_1_in__0\(4)
    );
\rd_addr[4]_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"7F"
    )
        port map (
      I0 => \^q\(0),
      I1 => \rd_addr_reg_n_0_[0]\,
      I2 => \rd_addr_reg_n_0_[2]\,
      O => \rd_addr[4]_i_2_n_0\
    );
\rd_addr[5]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"7FFFFFFF80000000"
    )
        port map (
      I0 => \^q\(0),
      I1 => \rd_addr_reg_n_0_[0]\,
      I2 => \rd_addr_reg_n_0_[2]\,
      I3 => \rd_addr_reg_n_0_[3]\,
      I4 => \rd_addr_reg_n_0_[4]\,
      I5 => \rd_addr_reg_n_0_[5]\,
      O => \p_1_in__0\(5)
    );
\rd_addr[6]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"D2"
    )
        port map (
      I0 => \rd_addr_reg_n_0_[5]\,
      I1 => \rd_addr[7]_i_6_n_0\,
      I2 => \rd_addr_reg_n_0_[6]\,
      O => \p_1_in__0\(6)
    );
\rd_addr[7]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"E0A0E0AFF0F0F0FF"
    )
        port map (
      I0 => \rd_addr[7]_i_4_n_0\,
      I1 => \^q\(0),
      I2 => \rd_addr_reg_n_0_[7]\,
      I3 => \rd_addr[7]_i_5_n_0\,
      I4 => \rd_addr[7]_i_6_n_0\,
      I5 => \rd_addr_reg_n_0_[4]\,
      O => \p_1_in__0\(7)
    );
\rd_addr[7]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"77FDFFFFFFFF77FD"
    )
        port map (
      I0 => \rd_addr_reg_n_0_[2]\,
      I1 => \rd_addr_reg_n_0_[0]\,
      I2 => \rd_addr[7]_i_7_n_0\,
      I3 => \^q\(0),
      I4 => \rd_addr_reg[3]_0\,
      I5 => \rd_addr_reg_n_0_[3]\,
      O => \rd_addr[7]_i_4_n_0\
    );
\rd_addr[7]_i_5\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"7"
    )
        port map (
      I0 => \rd_addr_reg_n_0_[5]\,
      I1 => \rd_addr_reg_n_0_[6]\,
      O => \rd_addr[7]_i_5_n_0\
    );
\rd_addr[7]_i_6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"7FFFFFFF"
    )
        port map (
      I0 => \rd_addr_reg_n_0_[4]\,
      I1 => \rd_addr_reg_n_0_[3]\,
      I2 => \rd_addr_reg_n_0_[2]\,
      I3 => \rd_addr_reg_n_0_[0]\,
      I4 => \^q\(0),
      O => \rd_addr[7]_i_6_n_0\
    );
\rd_addr[7]_i_7\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => \rd_addr_reg_n_0_[5]\,
      I1 => \rd_addr_reg_n_0_[6]\,
      O => \rd_addr[7]_i_7_n_0\
    );
\rd_addr_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \dout_o_reg[15]_2\,
      CE => E(0),
      D => \p_1_in__0\(0),
      Q => \rd_addr_reg_n_0_[0]\,
      R => SR(0)
    );
\rd_addr_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \dout_o_reg[15]_2\,
      CE => E(0),
      D => \p_1_in__0\(1),
      Q => \^q\(0),
      R => SR(0)
    );
\rd_addr_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \dout_o_reg[15]_2\,
      CE => E(0),
      D => \p_1_in__0\(2),
      Q => \rd_addr_reg_n_0_[2]\,
      R => SR(0)
    );
\rd_addr_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => \dout_o_reg[15]_2\,
      CE => E(0),
      D => \p_1_in__0\(3),
      Q => \rd_addr_reg_n_0_[3]\,
      R => SR(0)
    );
\rd_addr_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => \dout_o_reg[15]_2\,
      CE => E(0),
      D => \p_1_in__0\(4),
      Q => \rd_addr_reg_n_0_[4]\,
      R => SR(0)
    );
\rd_addr_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => \dout_o_reg[15]_2\,
      CE => E(0),
      D => \p_1_in__0\(5),
      Q => \rd_addr_reg_n_0_[5]\,
      R => SR(0)
    );
\rd_addr_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => \dout_o_reg[15]_2\,
      CE => E(0),
      D => \p_1_in__0\(6),
      Q => \rd_addr_reg_n_0_[6]\,
      R => SR(0)
    );
\rd_addr_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => \dout_o_reg[15]_2\,
      CE => E(0),
      D => \p_1_in__0\(7),
      Q => \rd_addr_reg_n_0_[7]\,
      R => SR(0)
    );
\victim_sel_rotate.sel_reg[56]\: unisim.vcomponents.FDRE
     port map (
      C => \dout_o_reg[15]_2\,
      CE => '1',
      D => D(0),
      Q => p_0_in222_in,
      R => \victim_sel_rotate.sel_reg[56]_0\(0)
    );
\victim_sel_rotate.sel_reg[57]\: unisim.vcomponents.FDRE
     port map (
      C => \dout_o_reg[15]_2\,
      CE => '1',
      D => D(1),
      Q => p_0_in226_in,
      R => \victim_sel_rotate.sel_reg[56]_0\(0)
    );
\victim_sel_rotate.sel_reg[58]\: unisim.vcomponents.FDRE
     port map (
      C => \dout_o_reg[15]_2\,
      CE => '1',
      D => D(2),
      Q => p_0_in230_in,
      R => \victim_sel_rotate.sel_reg[56]_0\(0)
    );
\victim_sel_rotate.sel_reg[59]\: unisim.vcomponents.FDRE
     port map (
      C => \dout_o_reg[15]_2\,
      CE => '1',
      D => D(3),
      Q => p_0_in234_in,
      R => \victim_sel_rotate.sel_reg[56]_0\(0)
    );
\victim_sel_rotate.sel_reg[60]\: unisim.vcomponents.FDRE
     port map (
      C => \dout_o_reg[15]_2\,
      CE => '1',
      D => D(4),
      Q => p_0_in238_in,
      R => \victim_sel_rotate.sel_reg[56]_0\(0)
    );
\victim_sel_rotate.sel_reg[61]\: unisim.vcomponents.FDRE
     port map (
      C => \dout_o_reg[15]_2\,
      CE => '1',
      D => D(5),
      Q => p_0_in242_in,
      R => \victim_sel_rotate.sel_reg[56]_0\(0)
    );
\victim_sel_rotate.sel_reg[62]\: unisim.vcomponents.FDRE
     port map (
      C => \dout_o_reg[15]_2\,
      CE => '1',
      D => D(6),
      Q => p_0_in246_in,
      R => \victim_sel_rotate.sel_reg[56]_0\(0)
    );
\victim_sel_rotate.sel_reg[63]\: unisim.vcomponents.FDRE
     port map (
      C => \dout_o_reg[15]_2\,
      CE => '1',
      D => D(7),
      Q => p_0_in250_in,
      R => \victim_sel_rotate.sel_reg[56]_0\(0)
    );
\wrdq_div1_4to1_wrcal_first.phy_wrdata[120]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"E2FFFFFF"
    )
        port map (
      I0 => p_1_in252_in,
      I1 => p_0_in222_in,
      I2 => p_2_in254_in,
      I3 => \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[511]_0\,
      I4 => \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[511]\,
      O => \dout_o_reg[14]_1\
    );
\wrdq_div1_4to1_wrcal_first.phy_wrdata[121]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"A0AAA00088888888"
    )
        port map (
      I0 => \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[511]\,
      I1 => first_rdlvl_pat_r,
      I2 => p_2_in254_in,
      I3 => p_0_in226_in,
      I4 => p_1_in252_in,
      I5 => \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[511]_0\,
      O => wrcal_done_reg
    );
\wrdq_div1_4to1_wrcal_first.phy_wrdata[124]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"E2FFFFFF"
    )
        port map (
      I0 => p_1_in252_in,
      I1 => p_0_in238_in,
      I2 => p_2_in254_in,
      I3 => \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[511]_0\,
      I4 => \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[511]\,
      O => \dout_o_reg[14]_0\
    );
\wrdq_div1_4to1_wrcal_first.phy_wrdata[125]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"B800FF00B8000000"
    )
        port map (
      I0 => p_2_in254_in,
      I1 => p_0_in242_in,
      I2 => p_1_in252_in,
      I3 => \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[511]\,
      I4 => \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[511]_0\,
      I5 => first_rdlvl_pat_r,
      O => \dout_o_reg[6]_0\
    );
\wrdq_div1_4to1_wrcal_first.phy_wrdata[184]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E2FF"
    )
        port map (
      I0 => p_1_in382_in,
      I1 => p_0_in222_in,
      I2 => p_2_in384_in,
      I3 => \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[511]_0\,
      O => \dout_o_reg[13]_3\
    );
\wrdq_div1_4to1_wrcal_first.phy_wrdata[186]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"E2FFFFFF"
    )
        port map (
      I0 => p_1_in382_in,
      I1 => p_0_in230_in,
      I2 => p_2_in384_in,
      I3 => \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[511]_0\,
      I4 => \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[511]\,
      O => \dout_o_reg[13]_2\
    );
\wrdq_div1_4to1_wrcal_first.phy_wrdata[187]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"A808"
    )
        port map (
      I0 => \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[511]_0\,
      I1 => p_1_in382_in,
      I2 => p_0_in234_in,
      I3 => p_2_in384_in,
      O => rdlvl_stg1_done_int_reg_6
    );
\wrdq_div1_4to1_wrcal_first.phy_wrdata[188]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E2FF"
    )
        port map (
      I0 => p_1_in382_in,
      I1 => p_0_in238_in,
      I2 => p_2_in384_in,
      I3 => \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[511]_0\,
      O => \dout_o_reg[13]_1\
    );
\wrdq_div1_4to1_wrcal_first.phy_wrdata[190]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"E2FFFFFF"
    )
        port map (
      I0 => p_1_in382_in,
      I1 => p_0_in246_in,
      I2 => p_2_in384_in,
      I3 => \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[511]_0\,
      I4 => \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[511]\,
      O => \dout_o_reg[13]_0\
    );
\wrdq_div1_4to1_wrcal_first.phy_wrdata[191]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"A808"
    )
        port map (
      I0 => \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[511]_0\,
      I1 => p_1_in382_in,
      I2 => p_0_in250_in,
      I3 => p_2_in384_in,
      O => rdlvl_stg1_done_int_reg_5
    );
\wrdq_div1_4to1_wrcal_first.phy_wrdata[248]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"E2000000"
    )
        port map (
      I0 => p_1_in512_in,
      I1 => p_0_in222_in,
      I2 => p_2_in514_in,
      I3 => \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[511]_0\,
      I4 => \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[511]\,
      O => \dout_o_reg[12]_5\
    );
\wrdq_div1_4to1_wrcal_first.phy_wrdata[249]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E2FF"
    )
        port map (
      I0 => p_1_in512_in,
      I1 => p_0_in226_in,
      I2 => p_2_in514_in,
      I3 => \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[511]_0\,
      O => \dout_o_reg[12]_3\
    );
\wrdq_div1_4to1_wrcal_first.phy_wrdata[251]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E2FF"
    )
        port map (
      I0 => p_1_in512_in,
      I1 => p_0_in234_in,
      I2 => p_2_in514_in,
      I3 => \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[511]_0\,
      O => \dout_o_reg[12]_2\
    );
\wrdq_div1_4to1_wrcal_first.phy_wrdata[252]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"E2000000"
    )
        port map (
      I0 => p_1_in512_in,
      I1 => p_0_in238_in,
      I2 => p_2_in514_in,
      I3 => \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[511]_0\,
      I4 => \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[511]\,
      O => \dout_o_reg[12]_4\
    );
\wrdq_div1_4to1_wrcal_first.phy_wrdata[253]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E2FF"
    )
        port map (
      I0 => p_1_in512_in,
      I1 => p_0_in242_in,
      I2 => p_2_in514_in,
      I3 => \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[511]_0\,
      O => \dout_o_reg[12]_1\
    );
\wrdq_div1_4to1_wrcal_first.phy_wrdata[255]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E2FF"
    )
        port map (
      I0 => p_1_in512_in,
      I1 => p_0_in250_in,
      I2 => p_2_in514_in,
      I3 => \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[511]_0\,
      O => \dout_o_reg[12]_0\
    );
\wrdq_div1_4to1_wrcal_first.phy_wrdata[312]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"E2000000"
    )
        port map (
      I0 => p_1_in642_in,
      I1 => p_0_in222_in,
      I2 => p_2_in644_in,
      I3 => \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[511]_0\,
      I4 => \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[511]\,
      O => \dout_o_reg[11]_3\
    );
\wrdq_div1_4to1_wrcal_first.phy_wrdata[315]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E2FF"
    )
        port map (
      I0 => p_1_in642_in,
      I1 => p_0_in234_in,
      I2 => p_2_in644_in,
      I3 => \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[511]_0\,
      O => \dout_o_reg[11]_1\
    );
\wrdq_div1_4to1_wrcal_first.phy_wrdata[316]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"E2000000"
    )
        port map (
      I0 => p_1_in642_in,
      I1 => p_0_in238_in,
      I2 => p_2_in644_in,
      I3 => \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[511]_0\,
      I4 => \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[511]\,
      O => \dout_o_reg[11]_2\
    );
\wrdq_div1_4to1_wrcal_first.phy_wrdata[319]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E2FF"
    )
        port map (
      I0 => p_1_in642_in,
      I1 => p_0_in250_in,
      I2 => p_2_in644_in,
      I3 => \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[511]_0\,
      O => \dout_o_reg[11]_0\
    );
\wrdq_div1_4to1_wrcal_first.phy_wrdata[376]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E2FF"
    )
        port map (
      I0 => p_1_in772_in,
      I1 => p_0_in222_in,
      I2 => p_2_in774_in,
      I3 => \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[511]_0\,
      O => \dout_o_reg[10]_1\
    );
\wrdq_div1_4to1_wrcal_first.phy_wrdata[377]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"A808"
    )
        port map (
      I0 => \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[511]_0\,
      I1 => p_1_in772_in,
      I2 => p_0_in226_in,
      I3 => p_2_in774_in,
      O => rdlvl_stg1_done_int_reg_4
    );
\wrdq_div1_4to1_wrcal_first.phy_wrdata[378]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"E2000000"
    )
        port map (
      I0 => p_1_in772_in,
      I1 => p_0_in230_in,
      I2 => p_2_in774_in,
      I3 => \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[511]_0\,
      I4 => \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[511]\,
      O => \dout_o_reg[10]_3\
    );
\wrdq_div1_4to1_wrcal_first.phy_wrdata[380]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E2FF"
    )
        port map (
      I0 => p_1_in772_in,
      I1 => p_0_in238_in,
      I2 => p_2_in774_in,
      I3 => \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[511]_0\,
      O => \dout_o_reg[10]_0\
    );
\wrdq_div1_4to1_wrcal_first.phy_wrdata[381]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"A808"
    )
        port map (
      I0 => \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[511]_0\,
      I1 => p_1_in772_in,
      I2 => p_0_in242_in,
      I3 => p_2_in774_in,
      O => rdlvl_stg1_done_int_reg_3
    );
\wrdq_div1_4to1_wrcal_first.phy_wrdata[382]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"E2000000"
    )
        port map (
      I0 => p_1_in772_in,
      I1 => p_0_in246_in,
      I2 => p_2_in774_in,
      I3 => \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[511]_0\,
      I4 => \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[511]\,
      O => \dout_o_reg[10]_2\
    );
\wrdq_div1_4to1_wrcal_first.phy_wrdata[440]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"A808"
    )
        port map (
      I0 => \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[511]_0\,
      I1 => p_1_in902_in,
      I2 => p_0_in222_in,
      I3 => p_2_in904_in,
      O => rdlvl_stg1_done_int_reg_2
    );
\wrdq_div1_4to1_wrcal_first.phy_wrdata[441]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E2FF"
    )
        port map (
      I0 => p_1_in902_in,
      I1 => p_0_in226_in,
      I2 => p_2_in904_in,
      I3 => \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[511]_0\,
      O => \dout_o_reg[9]_1\
    );
\wrdq_div1_4to1_wrcal_first.phy_wrdata[442]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"E2000000"
    )
        port map (
      I0 => p_1_in902_in,
      I1 => p_0_in230_in,
      I2 => p_2_in904_in,
      I3 => \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[511]_0\,
      I4 => \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[511]\,
      O => \dout_o_reg[9]_3\
    );
\wrdq_div1_4to1_wrcal_first.phy_wrdata[443]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"A808"
    )
        port map (
      I0 => \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[511]_0\,
      I1 => p_1_in902_in,
      I2 => p_0_in234_in,
      I3 => p_2_in904_in,
      O => rdlvl_stg1_done_int_reg_1
    );
\wrdq_div1_4to1_wrcal_first.phy_wrdata[444]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"A808"
    )
        port map (
      I0 => \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[511]_0\,
      I1 => p_1_in902_in,
      I2 => p_0_in238_in,
      I3 => p_2_in904_in,
      O => rdlvl_stg1_done_int_reg_0
    );
\wrdq_div1_4to1_wrcal_first.phy_wrdata[445]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E2FF"
    )
        port map (
      I0 => p_1_in902_in,
      I1 => p_0_in242_in,
      I2 => p_2_in904_in,
      I3 => \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[511]_0\,
      O => \dout_o_reg[9]_0\
    );
\wrdq_div1_4to1_wrcal_first.phy_wrdata[446]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"E2000000"
    )
        port map (
      I0 => p_1_in902_in,
      I1 => p_0_in246_in,
      I2 => p_2_in904_in,
      I3 => \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[511]_0\,
      I4 => \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[511]\,
      O => \dout_o_reg[9]_2\
    );
\wrdq_div1_4to1_wrcal_first.phy_wrdata[447]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"A808"
    )
        port map (
      I0 => \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[511]_0\,
      I1 => p_1_in902_in,
      I2 => p_0_in250_in,
      I3 => p_2_in904_in,
      O => rdlvl_stg1_done_int_reg
    );
\wrdq_div1_4to1_wrcal_first.phy_wrdata[505]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"E2000000"
    )
        port map (
      I0 => p_1_in1032_in,
      I1 => p_0_in226_in,
      I2 => \dout_o_reg_n_0_[0]\,
      I3 => \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[511]_0\,
      I4 => \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[511]\,
      O => \dout_o_reg[8]_3\
    );
\wrdq_div1_4to1_wrcal_first.phy_wrdata[506]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"EE2EEEEEEE2E2E2E"
    )
        port map (
      I0 => first_wrcal_pat_r,
      I1 => \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[511]\,
      I2 => \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[511]_0\,
      I3 => \dout_o_reg_n_0_[0]\,
      I4 => p_0_in230_in,
      I5 => p_1_in1032_in,
      O => first_wrcal_pat_r_reg_0
    );
\wrdq_div1_4to1_wrcal_first.phy_wrdata[507]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"E2000000"
    )
        port map (
      I0 => p_1_in1032_in,
      I1 => p_0_in234_in,
      I2 => \dout_o_reg_n_0_[0]\,
      I3 => \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[511]_0\,
      I4 => \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[511]\,
      O => \dout_o_reg[8]_2\
    );
\wrdq_div1_4to1_wrcal_first.phy_wrdata[509]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"E2000000"
    )
        port map (
      I0 => p_1_in1032_in,
      I1 => p_0_in242_in,
      I2 => \dout_o_reg_n_0_[0]\,
      I3 => \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[511]_0\,
      I4 => \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[511]\,
      O => \dout_o_reg[8]_1\
    );
\wrdq_div1_4to1_wrcal_first.phy_wrdata[510]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"EE2EEEEEEE2E2E2E"
    )
        port map (
      I0 => first_wrcal_pat_r,
      I1 => \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[511]\,
      I2 => \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[511]_0\,
      I3 => \dout_o_reg_n_0_[0]\,
      I4 => p_0_in246_in,
      I5 => p_1_in1032_in,
      O => first_wrcal_pat_r_reg
    );
\wrdq_div1_4to1_wrcal_first.phy_wrdata[511]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"E2000000"
    )
        port map (
      I0 => p_1_in1032_in,
      I1 => p_0_in250_in,
      I2 => \dout_o_reg_n_0_[0]\,
      I3 => \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[511]_0\,
      I4 => \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[511]\,
      O => \dout_o_reg[8]_0\
    );
\wrdq_div1_4to1_wrcal_first.phy_wrdata[57]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F5FFF55577777777"
    )
        port map (
      I0 => \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[511]\,
      I1 => first_rdlvl_pat_r,
      I2 => p_2_in,
      I3 => p_0_in226_in,
      I4 => p_1_in,
      I5 => \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[511]_0\,
      O => wrcal_done_reg_1
    );
\wrdq_div1_4to1_wrcal_first.phy_wrdata[58]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"E2000000"
    )
        port map (
      I0 => p_1_in,
      I1 => p_0_in230_in,
      I2 => p_2_in,
      I3 => \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[511]_0\,
      I4 => \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[511]\,
      O => \dout_o_reg[15]_1\
    );
\wrdq_div1_4to1_wrcal_first.phy_wrdata[61]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F5FFF55577777777"
    )
        port map (
      I0 => \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[511]\,
      I1 => first_rdlvl_pat_r,
      I2 => p_2_in,
      I3 => p_0_in242_in,
      I4 => p_1_in,
      I5 => \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[511]_0\,
      O => wrcal_done_reg_0
    );
\wrdq_div1_4to1_wrcal_first.phy_wrdata[62]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"E2000000"
    )
        port map (
      I0 => p_1_in,
      I1 => p_0_in246_in,
      I2 => p_2_in,
      I3 => \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[511]_0\,
      I4 => \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[511]\,
      O => \dout_o_reg[15]_0\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mig_mig_7series_v4_2_infrastructure is
  port (
    \gen_mmcm.mmcm_i_i_1_0\ : out STD_LOGIC;
    \gen_mmcm.mmcm_i_0\ : out STD_LOGIC;
    mmcm_ps_clk : out STD_LOGIC;
    freq_refclk : out STD_LOGIC;
    mem_refclk : out STD_LOGIC;
    sync_pulse : out STD_LOGIC;
    rst_sync_r1 : out STD_LOGIC;
    rstdiv0_sync_r1_reg_rep_0 : out STD_LOGIC;
    SR : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \rstdiv0_sync_r1_reg_rep__2_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \rstdiv0_sync_r1_reg_rep__5_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \rstdiv0_sync_r1_reg_rep__7_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \rstdiv0_sync_r1_reg_rep__8_0\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    \rstdiv0_sync_r1_reg_rep__9_0\ : out STD_LOGIC;
    \rstdiv0_sync_r1_reg_rep__10_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \rstdiv0_sync_r1_reg_rep__12_0\ : out STD_LOGIC;
    \rstdiv0_sync_r1_reg_rep__13_0\ : out STD_LOGIC;
    \rstdiv0_sync_r1_reg_rep__14_0\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    \rstdiv0_sync_r1_reg_rep__15_0\ : out STD_LOGIC;
    \rstdiv0_sync_r1_reg_rep__16_0\ : out STD_LOGIC;
    \rstdiv0_sync_r1_reg_rep__17_0\ : out STD_LOGIC;
    \rstdiv0_sync_r1_reg_rep__18_0\ : out STD_LOGIC;
    \rstdiv0_sync_r1_reg_rep__19_0\ : out STD_LOGIC;
    \rstdiv0_sync_r1_reg_rep__20_0\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    \rstdiv0_sync_r1_reg_rep__21_0\ : out STD_LOGIC;
    \rstdiv0_sync_r1_reg_rep__22_0\ : out STD_LOGIC;
    \rstdiv0_sync_r1_reg_rep__23_0\ : out STD_LOGIC;
    \rstdiv0_sync_r1_reg_rep__24_0\ : out STD_LOGIC;
    \rstdiv0_sync_r1_reg_rep__25_0\ : out STD_LOGIC;
    RST0 : out STD_LOGIC;
    pll_locked : out STD_LOGIC;
    bm_end_r1_reg : out STD_LOGIC;
    bm_end_r1_reg_0 : out STD_LOGIC;
    bm_end_r1_reg_1 : out STD_LOGIC;
    \generate_maint_cmds.insert_maint_r_lcl_reg\ : out STD_LOGIC;
    SS : out STD_LOGIC_VECTOR ( 0 to 0 );
    po_cnt_dec_reg : out STD_LOGIC_VECTOR ( 0 to 0 );
    fine_adjust_reg : out STD_LOGIC;
    new_cnt_cpt_r_reg : out STD_LOGIC_VECTOR ( 0 to 0 );
    rdlvl_stg1_start_reg : out STD_LOGIC_VECTOR ( 0 to 0 );
    samp_edge_cnt0_en_r_reg : out STD_LOGIC;
    pi_cnt_dec_reg : out STD_LOGIC_VECTOR ( 0 to 0 );
    new_cnt_dqs_r_reg : out STD_LOGIC;
    \rstdiv0_sync_r1_reg_rep__23_1\ : out STD_LOGIC;
    prbs_rdlvl_done_pulse_reg : out STD_LOGIC;
    \out\ : in STD_LOGIC;
    AS : in STD_LOGIC_VECTOR ( 0 to 0 );
    rst_tmp : in STD_LOGIC;
    bm_end_r1 : in STD_LOGIC;
    bm_end_r1_0 : in STD_LOGIC;
    bm_end_r1_1 : in STD_LOGIC;
    insert_maint_r : in STD_LOGIC;
    po_cnt_dec : in STD_LOGIC;
    po_cnt_dec_2 : in STD_LOGIC;
    \pi_rst_stg1_cal_r_reg[1]\ : in STD_LOGIC;
    \tap_cnt_cpt_r_reg[5]\ : in STD_LOGIC;
    \cnt_shift_r_reg[0]\ : in STD_LOGIC;
    samp_edge_cnt0_en_r : in STD_LOGIC;
    pi_cnt_dec : in STD_LOGIC;
    \cmp_err_4to1.compare_err_f3_reg\ : in STD_LOGIC;
    \en_cnt_div4.enable_wrlvl_cnt_reg[4]\ : in STD_LOGIC;
    prbs_rdlvl_done_pulse : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of mig_mig_7series_v4_2_infrastructure : entity is "mig_7series_v4_2_infrastructure";
end mig_mig_7series_v4_2_infrastructure;

architecture STRUCTURE of mig_mig_7series_v4_2_infrastructure is
  signal RST0_0 : STD_LOGIC;
  signal clk_div2_bufg_in : STD_LOGIC;
  signal clk_pll_i : STD_LOGIC;
  signal \^gen_mmcm.mmcm_i_0\ : STD_LOGIC;
  signal \^gen_mmcm.mmcm_i_i_1_0\ : STD_LOGIC;
  signal \gen_mmcm.mmcm_i_n_17\ : STD_LOGIC;
  signal \gen_mmcm.u_bufg_clk_div2_n_0\ : STD_LOGIC;
  signal \^mmcm_ps_clk\ : STD_LOGIC;
  signal mmcm_ps_clk_bufg_in : STD_LOGIC;
  signal p_0_in : STD_LOGIC;
  signal pll_clk3 : STD_LOGIC;
  signal pll_clk3_out : STD_LOGIC;
  signal pll_clkfbout : STD_LOGIC;
  signal pll_locked_i : STD_LOGIC;
  signal rst_sync_r : STD_LOGIC_VECTOR ( 11 downto 0 );
  signal rstdiv0_sync_r : STD_LOGIC_VECTOR ( 11 downto 0 );
  signal \rstdiv0_sync_r1_reg_rep__0_n_0\ : STD_LOGIC;
  signal \rstdiv0_sync_r1_reg_rep__10_n_0\ : STD_LOGIC;
  signal \rstdiv0_sync_r1_reg_rep__11_n_0\ : STD_LOGIC;
  signal \rstdiv0_sync_r1_reg_rep__12_n_0\ : STD_LOGIC;
  signal \rstdiv0_sync_r1_reg_rep__13_n_0\ : STD_LOGIC;
  signal \rstdiv0_sync_r1_reg_rep__14_n_0\ : STD_LOGIC;
  signal \rstdiv0_sync_r1_reg_rep__15_n_0\ : STD_LOGIC;
  signal \rstdiv0_sync_r1_reg_rep__16_n_0\ : STD_LOGIC;
  signal \rstdiv0_sync_r1_reg_rep__17_n_0\ : STD_LOGIC;
  signal \rstdiv0_sync_r1_reg_rep__18_n_0\ : STD_LOGIC;
  signal \rstdiv0_sync_r1_reg_rep__19_n_0\ : STD_LOGIC;
  signal \rstdiv0_sync_r1_reg_rep__1_n_0\ : STD_LOGIC;
  signal \rstdiv0_sync_r1_reg_rep__20_n_0\ : STD_LOGIC;
  signal \^rstdiv0_sync_r1_reg_rep__21_0\ : STD_LOGIC;
  signal \rstdiv0_sync_r1_reg_rep__21_n_0\ : STD_LOGIC;
  signal \^rstdiv0_sync_r1_reg_rep__22_0\ : STD_LOGIC;
  signal \rstdiv0_sync_r1_reg_rep__22_n_0\ : STD_LOGIC;
  signal \^rstdiv0_sync_r1_reg_rep__23_0\ : STD_LOGIC;
  signal \rstdiv0_sync_r1_reg_rep__23_n_0\ : STD_LOGIC;
  signal \rstdiv0_sync_r1_reg_rep__24_n_0\ : STD_LOGIC;
  signal \^rstdiv0_sync_r1_reg_rep__25_0\ : STD_LOGIC;
  signal \rstdiv0_sync_r1_reg_rep__25_n_0\ : STD_LOGIC;
  signal \rstdiv0_sync_r1_reg_rep__2_n_0\ : STD_LOGIC;
  signal \rstdiv0_sync_r1_reg_rep__3_n_0\ : STD_LOGIC;
  signal \rstdiv0_sync_r1_reg_rep__4_n_0\ : STD_LOGIC;
  signal \rstdiv0_sync_r1_reg_rep__5_n_0\ : STD_LOGIC;
  signal \rstdiv0_sync_r1_reg_rep__6_n_0\ : STD_LOGIC;
  signal \rstdiv0_sync_r1_reg_rep__7_n_0\ : STD_LOGIC;
  signal \rstdiv0_sync_r1_reg_rep__8_n_0\ : STD_LOGIC;
  signal \rstdiv0_sync_r1_reg_rep__9_n_0\ : STD_LOGIC;
  signal rstdiv0_sync_r1_reg_rep_n_0 : STD_LOGIC;
  signal rstdiv2_sync_r1 : STD_LOGIC;
  attribute MAX_FANOUT : string;
  attribute MAX_FANOUT of rstdiv2_sync_r1 : signal is "10";
  attribute RTL_MAX_FANOUT : string;
  attribute RTL_MAX_FANOUT of rstdiv2_sync_r1 : signal is "found";
  attribute syn_maxfan : string;
  attribute syn_maxfan of rstdiv2_sync_r1 : signal is "10";
  signal \rstdiv2_sync_r_reg_n_0_[0]\ : STD_LOGIC;
  signal \rstdiv2_sync_r_reg_n_0_[10]\ : STD_LOGIC;
  signal \rstdiv2_sync_r_reg_n_0_[1]\ : STD_LOGIC;
  signal \rstdiv2_sync_r_reg_n_0_[2]\ : STD_LOGIC;
  signal \rstdiv2_sync_r_reg_n_0_[3]\ : STD_LOGIC;
  signal \rstdiv2_sync_r_reg_n_0_[4]\ : STD_LOGIC;
  signal \rstdiv2_sync_r_reg_n_0_[5]\ : STD_LOGIC;
  signal \rstdiv2_sync_r_reg_n_0_[6]\ : STD_LOGIC;
  signal \rstdiv2_sync_r_reg_n_0_[7]\ : STD_LOGIC;
  signal \rstdiv2_sync_r_reg_n_0_[8]\ : STD_LOGIC;
  signal \rstdiv2_sync_r_reg_n_0_[9]\ : STD_LOGIC;
  signal \NLW_gen_mmcm.mmcm_i_CLKFBOUTB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gen_mmcm.mmcm_i_CLKFBSTOPPED_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gen_mmcm.mmcm_i_CLKINSTOPPED_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gen_mmcm.mmcm_i_CLKOUT0B_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gen_mmcm.mmcm_i_CLKOUT1B_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gen_mmcm.mmcm_i_CLKOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gen_mmcm.mmcm_i_CLKOUT2B_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gen_mmcm.mmcm_i_CLKOUT3_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gen_mmcm.mmcm_i_CLKOUT3B_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gen_mmcm.mmcm_i_CLKOUT4_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gen_mmcm.mmcm_i_CLKOUT5_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gen_mmcm.mmcm_i_CLKOUT6_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gen_mmcm.mmcm_i_DRDY_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gen_mmcm.mmcm_i_DO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal NLW_plle2_i_CLKOUT4_UNCONNECTED : STD_LOGIC;
  signal NLW_plle2_i_CLKOUT5_UNCONNECTED : STD_LOGIC;
  signal NLW_plle2_i_DRDY_UNCONNECTED : STD_LOGIC;
  signal NLW_plle2_i_DO_UNCONNECTED : STD_LOGIC_VECTOR ( 15 downto 0 );
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \cmp_err_4to1.compare_err_i_3\ : label is "soft_lutpair10";
  attribute SOFT_HLUTNM of \cnt_shift_r[3]_i_1\ : label is "soft_lutpair11";
  attribute SOFT_HLUTNM of \complex_num_writes[2]_i_6\ : label is "soft_lutpair9";
  attribute SOFT_HLUTNM of \en_cnt_div4.enable_wrlvl_cnt[4]_i_2\ : label is "soft_lutpair9";
  attribute BOX_TYPE : string;
  attribute BOX_TYPE of \gen_mmcm.mmcm_i\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \gen_mmcm.u_bufg_clk_div2\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \gen_mmcm.u_bufg_mmcm_ps_clk\ : label is "PRIMITIVE";
  attribute SOFT_HLUTNM of phaser_ref_i_i_1 : label is "soft_lutpair12";
  attribute SOFT_HLUTNM of phy_control_i_i_1 : label is "soft_lutpair12";
  attribute SOFT_HLUTNM of \pi_rst_stg1_cal_r[1]_i_2\ : label is "soft_lutpair13";
  attribute BOX_TYPE of plle2_i : label is "PRIMITIVE";
  attribute SOFT_HLUTNM of \ras_timer_r[1]_i_4__0\ : label is "soft_lutpair7";
  attribute SOFT_HLUTNM of \ras_timer_r[1]_i_4__1\ : label is "soft_lutpair7";
  attribute SOFT_HLUTNM of ras_timer_zero_r_i_3 : label is "soft_lutpair8";
  attribute SOFT_HLUTNM of \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r[3]_i_3\ : label is "soft_lutpair8";
  attribute IS_FANOUT_CONSTRAINED : integer;
  attribute IS_FANOUT_CONSTRAINED of rstdiv0_sync_r1_inst_rep : label is 1;
  attribute IS_FANOUT_CONSTRAINED of \rstdiv0_sync_r1_inst_rep__0\ : label is 1;
  attribute IS_FANOUT_CONSTRAINED of \rstdiv0_sync_r1_inst_rep__1\ : label is 1;
  attribute IS_FANOUT_CONSTRAINED of \rstdiv0_sync_r1_inst_rep__10\ : label is 1;
  attribute IS_FANOUT_CONSTRAINED of \rstdiv0_sync_r1_inst_rep__11\ : label is 1;
  attribute IS_FANOUT_CONSTRAINED of \rstdiv0_sync_r1_inst_rep__12\ : label is 1;
  attribute IS_FANOUT_CONSTRAINED of \rstdiv0_sync_r1_inst_rep__13\ : label is 1;
  attribute IS_FANOUT_CONSTRAINED of \rstdiv0_sync_r1_inst_rep__14\ : label is 1;
  attribute IS_FANOUT_CONSTRAINED of \rstdiv0_sync_r1_inst_rep__15\ : label is 1;
  attribute IS_FANOUT_CONSTRAINED of \rstdiv0_sync_r1_inst_rep__16\ : label is 1;
  attribute IS_FANOUT_CONSTRAINED of \rstdiv0_sync_r1_inst_rep__17\ : label is 1;
  attribute IS_FANOUT_CONSTRAINED of \rstdiv0_sync_r1_inst_rep__18\ : label is 1;
  attribute IS_FANOUT_CONSTRAINED of \rstdiv0_sync_r1_inst_rep__19\ : label is 1;
  attribute IS_FANOUT_CONSTRAINED of \rstdiv0_sync_r1_inst_rep__2\ : label is 1;
  attribute IS_FANOUT_CONSTRAINED of \rstdiv0_sync_r1_inst_rep__20\ : label is 1;
  attribute IS_FANOUT_CONSTRAINED of \rstdiv0_sync_r1_inst_rep__21\ : label is 1;
  attribute IS_FANOUT_CONSTRAINED of \rstdiv0_sync_r1_inst_rep__22\ : label is 1;
  attribute IS_FANOUT_CONSTRAINED of \rstdiv0_sync_r1_inst_rep__23\ : label is 1;
  attribute IS_FANOUT_CONSTRAINED of \rstdiv0_sync_r1_inst_rep__24\ : label is 1;
  attribute IS_FANOUT_CONSTRAINED of \rstdiv0_sync_r1_inst_rep__3\ : label is 1;
  attribute IS_FANOUT_CONSTRAINED of \rstdiv0_sync_r1_inst_rep__4\ : label is 1;
  attribute IS_FANOUT_CONSTRAINED of \rstdiv0_sync_r1_inst_rep__5\ : label is 1;
  attribute IS_FANOUT_CONSTRAINED of \rstdiv0_sync_r1_inst_rep__6\ : label is 1;
  attribute IS_FANOUT_CONSTRAINED of \rstdiv0_sync_r1_inst_rep__7\ : label is 1;
  attribute IS_FANOUT_CONSTRAINED of \rstdiv0_sync_r1_inst_rep__8\ : label is 1;
  attribute IS_FANOUT_CONSTRAINED of \rstdiv0_sync_r1_inst_rep__9\ : label is 1;
  attribute ORIG_CELL_NAME : string;
  attribute ORIG_CELL_NAME of rstdiv0_sync_r1_reg_rep : label is "rstdiv0_sync_r1_reg";
  attribute ORIG_CELL_NAME of \rstdiv0_sync_r1_reg_rep__0\ : label is "rstdiv0_sync_r1_reg";
  attribute ORIG_CELL_NAME of \rstdiv0_sync_r1_reg_rep__1\ : label is "rstdiv0_sync_r1_reg";
  attribute ORIG_CELL_NAME of \rstdiv0_sync_r1_reg_rep__10\ : label is "rstdiv0_sync_r1_reg";
  attribute ORIG_CELL_NAME of \rstdiv0_sync_r1_reg_rep__11\ : label is "rstdiv0_sync_r1_reg";
  attribute ORIG_CELL_NAME of \rstdiv0_sync_r1_reg_rep__12\ : label is "rstdiv0_sync_r1_reg";
  attribute ORIG_CELL_NAME of \rstdiv0_sync_r1_reg_rep__13\ : label is "rstdiv0_sync_r1_reg";
  attribute ORIG_CELL_NAME of \rstdiv0_sync_r1_reg_rep__14\ : label is "rstdiv0_sync_r1_reg";
  attribute ORIG_CELL_NAME of \rstdiv0_sync_r1_reg_rep__15\ : label is "rstdiv0_sync_r1_reg";
  attribute ORIG_CELL_NAME of \rstdiv0_sync_r1_reg_rep__16\ : label is "rstdiv0_sync_r1_reg";
  attribute ORIG_CELL_NAME of \rstdiv0_sync_r1_reg_rep__17\ : label is "rstdiv0_sync_r1_reg";
  attribute ORIG_CELL_NAME of \rstdiv0_sync_r1_reg_rep__18\ : label is "rstdiv0_sync_r1_reg";
  attribute ORIG_CELL_NAME of \rstdiv0_sync_r1_reg_rep__19\ : label is "rstdiv0_sync_r1_reg";
  attribute ORIG_CELL_NAME of \rstdiv0_sync_r1_reg_rep__2\ : label is "rstdiv0_sync_r1_reg";
  attribute ORIG_CELL_NAME of \rstdiv0_sync_r1_reg_rep__20\ : label is "rstdiv0_sync_r1_reg";
  attribute ORIG_CELL_NAME of \rstdiv0_sync_r1_reg_rep__21\ : label is "rstdiv0_sync_r1_reg";
  attribute ORIG_CELL_NAME of \rstdiv0_sync_r1_reg_rep__22\ : label is "rstdiv0_sync_r1_reg";
  attribute ORIG_CELL_NAME of \rstdiv0_sync_r1_reg_rep__23\ : label is "rstdiv0_sync_r1_reg";
  attribute ORIG_CELL_NAME of \rstdiv0_sync_r1_reg_rep__24\ : label is "rstdiv0_sync_r1_reg";
  attribute ORIG_CELL_NAME of \rstdiv0_sync_r1_reg_rep__25\ : label is "rstdiv0_sync_r1_reg";
  attribute ORIG_CELL_NAME of \rstdiv0_sync_r1_reg_rep__3\ : label is "rstdiv0_sync_r1_reg";
  attribute ORIG_CELL_NAME of \rstdiv0_sync_r1_reg_rep__4\ : label is "rstdiv0_sync_r1_reg";
  attribute ORIG_CELL_NAME of \rstdiv0_sync_r1_reg_rep__5\ : label is "rstdiv0_sync_r1_reg";
  attribute ORIG_CELL_NAME of \rstdiv0_sync_r1_reg_rep__6\ : label is "rstdiv0_sync_r1_reg";
  attribute ORIG_CELL_NAME of \rstdiv0_sync_r1_reg_rep__7\ : label is "rstdiv0_sync_r1_reg";
  attribute ORIG_CELL_NAME of \rstdiv0_sync_r1_reg_rep__8\ : label is "rstdiv0_sync_r1_reg";
  attribute ORIG_CELL_NAME of \rstdiv0_sync_r1_reg_rep__9\ : label is "rstdiv0_sync_r1_reg";
  attribute RTL_MAX_FANOUT of rstdiv2_sync_r1_reg : label is "found";
  attribute syn_maxfan of rstdiv2_sync_r1_reg : label is "10";
  attribute SOFT_HLUTNM of \samp_edge_cnt0_r[0]_i_1\ : label is "soft_lutpair13";
  attribute SOFT_HLUTNM of \tap_cnt_cpt_r[5]_i_1\ : label is "soft_lutpair6";
  attribute BOX_TYPE of u_bufg_clkdiv0 : label is "PRIMITIVE";
  attribute BOX_TYPE of u_bufh_pll_clk3 : label is "PRIMITIVE";
  attribute SOFT_HLUTNM of \wait_cnt[3]_i_1\ : label is "soft_lutpair6";
  attribute SOFT_HLUTNM of \wait_cnt_r[3]_i_1\ : label is "soft_lutpair11";
  attribute SOFT_HLUTNM of \wait_cnt_r[3]_i_1__0\ : label is "soft_lutpair10";
begin
  \gen_mmcm.mmcm_i_0\ <= \^gen_mmcm.mmcm_i_0\;
  \gen_mmcm.mmcm_i_i_1_0\ <= \^gen_mmcm.mmcm_i_i_1_0\;
  mmcm_ps_clk <= \^mmcm_ps_clk\;
  \rstdiv0_sync_r1_reg_rep__21_0\ <= \^rstdiv0_sync_r1_reg_rep__21_0\;
  \rstdiv0_sync_r1_reg_rep__22_0\ <= \^rstdiv0_sync_r1_reg_rep__22_0\;
  \rstdiv0_sync_r1_reg_rep__23_0\ <= \^rstdiv0_sync_r1_reg_rep__23_0\;
  \rstdiv0_sync_r1_reg_rep__25_0\ <= \^rstdiv0_sync_r1_reg_rep__25_0\;
\cmp_err_4to1.compare_err_i_3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => \^rstdiv0_sync_r1_reg_rep__22_0\,
      I1 => \cmp_err_4to1.compare_err_f3_reg\,
      O => new_cnt_dqs_r_reg
    );
\cnt_shift_r[3]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => \^rstdiv0_sync_r1_reg_rep__21_0\,
      I1 => \cnt_shift_r_reg[0]\,
      O => rdlvl_stg1_start_reg(0)
    );
\complex_num_writes[2]_i_6\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \^rstdiv0_sync_r1_reg_rep__23_0\,
      I1 => prbs_rdlvl_done_pulse,
      O => prbs_rdlvl_done_pulse_reg
    );
\en_cnt_div4.enable_wrlvl_cnt[4]_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => \^rstdiv0_sync_r1_reg_rep__23_0\,
      I1 => \en_cnt_div4.enable_wrlvl_cnt_reg[4]\,
      O => \rstdiv0_sync_r1_reg_rep__23_1\
    );
\gen_mmcm.mmcm_i\: unisim.vcomponents.MMCME2_ADV
    generic map(
      BANDWIDTH => "HIGH",
      CLKFBOUT_MULT_F => 8.000000,
      CLKFBOUT_PHASE => 0.000000,
      CLKFBOUT_USE_FINE_PS => false,
      CLKIN1_PERIOD => 10.000000,
      CLKIN2_PERIOD => 0.000000,
      CLKOUT0_DIVIDE_F => 16.000000,
      CLKOUT0_DUTY_CYCLE => 0.500000,
      CLKOUT0_PHASE => 0.000000,
      CLKOUT0_USE_FINE_PS => true,
      CLKOUT1_DIVIDE => 4,
      CLKOUT1_DUTY_CYCLE => 0.500000,
      CLKOUT1_PHASE => 0.000000,
      CLKOUT1_USE_FINE_PS => false,
      CLKOUT2_DIVIDE => 1,
      CLKOUT2_DUTY_CYCLE => 0.500000,
      CLKOUT2_PHASE => 0.000000,
      CLKOUT2_USE_FINE_PS => false,
      CLKOUT3_DIVIDE => 1,
      CLKOUT3_DUTY_CYCLE => 0.500000,
      CLKOUT3_PHASE => 0.000000,
      CLKOUT3_USE_FINE_PS => false,
      CLKOUT4_CASCADE => false,
      CLKOUT4_DIVIDE => 1,
      CLKOUT4_DUTY_CYCLE => 0.500000,
      CLKOUT4_PHASE => 0.000000,
      CLKOUT4_USE_FINE_PS => false,
      CLKOUT5_DIVIDE => 1,
      CLKOUT5_DUTY_CYCLE => 0.500000,
      CLKOUT5_PHASE => 0.000000,
      CLKOUT5_USE_FINE_PS => false,
      CLKOUT6_DIVIDE => 1,
      CLKOUT6_DUTY_CYCLE => 0.500000,
      CLKOUT6_PHASE => 0.000000,
      CLKOUT6_USE_FINE_PS => false,
      COMPENSATION => "BUF_IN",
      DIVCLK_DIVIDE => 1,
      IS_CLKINSEL_INVERTED => '0',
      IS_PSEN_INVERTED => '0',
      IS_PSINCDEC_INVERTED => '0',
      IS_PWRDWN_INVERTED => '0',
      IS_RST_INVERTED => '0',
      REF_JITTER1 => 0.000000,
      REF_JITTER2 => 0.010000,
      SS_EN => "FALSE",
      SS_MODE => "CENTER_HIGH",
      SS_MOD_PERIOD => 10000,
      STARTUP_WAIT => false
    )
        port map (
      CLKFBIN => \^gen_mmcm.mmcm_i_0\,
      CLKFBOUT => clk_pll_i,
      CLKFBOUTB => \NLW_gen_mmcm.mmcm_i_CLKFBOUTB_UNCONNECTED\,
      CLKFBSTOPPED => \NLW_gen_mmcm.mmcm_i_CLKFBSTOPPED_UNCONNECTED\,
      CLKIN1 => pll_clk3,
      CLKIN2 => '0',
      CLKINSEL => '1',
      CLKINSTOPPED => \NLW_gen_mmcm.mmcm_i_CLKINSTOPPED_UNCONNECTED\,
      CLKOUT0 => mmcm_ps_clk_bufg_in,
      CLKOUT0B => \NLW_gen_mmcm.mmcm_i_CLKOUT0B_UNCONNECTED\,
      CLKOUT1 => clk_div2_bufg_in,
      CLKOUT1B => \NLW_gen_mmcm.mmcm_i_CLKOUT1B_UNCONNECTED\,
      CLKOUT2 => \NLW_gen_mmcm.mmcm_i_CLKOUT2_UNCONNECTED\,
      CLKOUT2B => \NLW_gen_mmcm.mmcm_i_CLKOUT2B_UNCONNECTED\,
      CLKOUT3 => \NLW_gen_mmcm.mmcm_i_CLKOUT3_UNCONNECTED\,
      CLKOUT3B => \NLW_gen_mmcm.mmcm_i_CLKOUT3B_UNCONNECTED\,
      CLKOUT4 => \NLW_gen_mmcm.mmcm_i_CLKOUT4_UNCONNECTED\,
      CLKOUT5 => \NLW_gen_mmcm.mmcm_i_CLKOUT5_UNCONNECTED\,
      CLKOUT6 => \NLW_gen_mmcm.mmcm_i_CLKOUT6_UNCONNECTED\,
      DADDR(6 downto 0) => B"0000000",
      DCLK => '0',
      DEN => '0',
      DI(15 downto 0) => B"0000000000000000",
      DO(15 downto 0) => \NLW_gen_mmcm.mmcm_i_DO_UNCONNECTED\(15 downto 0),
      DRDY => \NLW_gen_mmcm.mmcm_i_DRDY_UNCONNECTED\,
      DWE => '0',
      LOCKED => \^gen_mmcm.mmcm_i_i_1_0\,
      PSCLK => \^gen_mmcm.mmcm_i_0\,
      PSDONE => \gen_mmcm.mmcm_i_n_17\,
      PSEN => '0',
      PSINCDEC => '0',
      PWRDWN => '0',
      RST => RST0_0
    );
\gen_mmcm.mmcm_i_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => pll_locked_i,
      O => RST0_0
    );
\gen_mmcm.u_bufg_clk_div2\: unisim.vcomponents.BUFG
     port map (
      I => clk_div2_bufg_in,
      O => \gen_mmcm.u_bufg_clk_div2_n_0\
    );
\gen_mmcm.u_bufg_mmcm_ps_clk\: unisim.vcomponents.BUFG
     port map (
      I => mmcm_ps_clk_bufg_in,
      O => \^mmcm_ps_clk\
    );
phaser_ref_i_i_1: unisim.vcomponents.LUT2
    generic map(
      INIT => X"7"
    )
        port map (
      I0 => pll_locked_i,
      I1 => \^gen_mmcm.mmcm_i_i_1_0\,
      O => RST0
    );
phy_control_i_i_1: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => pll_locked_i,
      I1 => \^gen_mmcm.mmcm_i_i_1_0\,
      O => pll_locked
    );
\pi_rst_stg1_cal_r[1]_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \^rstdiv0_sync_r1_reg_rep__21_0\,
      I1 => \pi_rst_stg1_cal_r_reg[1]\,
      O => fine_adjust_reg
    );
plle2_i: unisim.vcomponents.PLLE2_ADV
    generic map(
      BANDWIDTH => "OPTIMIZED",
      CLKFBOUT_MULT => 4,
      CLKFBOUT_PHASE => 0.000000,
      CLKIN1_PERIOD => 5.000000,
      CLKIN2_PERIOD => 0.000000,
      CLKOUT0_DIVIDE => 1,
      CLKOUT0_DUTY_CYCLE => 0.500000,
      CLKOUT0_PHASE => 0.000000,
      CLKOUT1_DIVIDE => 2,
      CLKOUT1_DUTY_CYCLE => 0.500000,
      CLKOUT1_PHASE => 0.000000,
      CLKOUT2_DIVIDE => 32,
      CLKOUT2_DUTY_CYCLE => 0.062500,
      CLKOUT2_PHASE => 9.843750,
      CLKOUT3_DIVIDE => 8,
      CLKOUT3_DUTY_CYCLE => 0.500000,
      CLKOUT3_PHASE => 0.000000,
      CLKOUT4_DIVIDE => 4,
      CLKOUT4_DUTY_CYCLE => 0.500000,
      CLKOUT4_PHASE => 168.750000,
      CLKOUT5_DIVIDE => 1,
      CLKOUT5_DUTY_CYCLE => 0.500000,
      CLKOUT5_PHASE => 0.000000,
      COMPENSATION => "INTERNAL",
      DIVCLK_DIVIDE => 1,
      IS_CLKINSEL_INVERTED => '0',
      IS_PWRDWN_INVERTED => '0',
      IS_RST_INVERTED => '0',
      REF_JITTER1 => 0.010000,
      REF_JITTER2 => 0.010000,
      STARTUP_WAIT => "FALSE"
    )
        port map (
      CLKFBIN => pll_clkfbout,
      CLKFBOUT => pll_clkfbout,
      CLKIN1 => \out\,
      CLKIN2 => '0',
      CLKINSEL => '1',
      CLKOUT0 => freq_refclk,
      CLKOUT1 => mem_refclk,
      CLKOUT2 => sync_pulse,
      CLKOUT3 => pll_clk3_out,
      CLKOUT4 => NLW_plle2_i_CLKOUT4_UNCONNECTED,
      CLKOUT5 => NLW_plle2_i_CLKOUT5_UNCONNECTED,
      DADDR(6 downto 0) => B"0000000",
      DCLK => '0',
      DEN => '0',
      DI(15 downto 0) => B"0000000000000000",
      DO(15 downto 0) => NLW_plle2_i_DO_UNCONNECTED(15 downto 0),
      DRDY => NLW_plle2_i_DRDY_UNCONNECTED,
      DWE => '0',
      LOCKED => pll_locked_i,
      PWRDWN => '0',
      RST => AS(0)
    );
\ras_timer_r[1]_i_4__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => \^rstdiv0_sync_r1_reg_rep__25_0\,
      I1 => bm_end_r1,
      O => bm_end_r1_reg
    );
\ras_timer_r[1]_i_4__1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => \^rstdiv0_sync_r1_reg_rep__25_0\,
      I1 => bm_end_r1_0,
      O => bm_end_r1_reg_0
    );
ras_timer_zero_r_i_3: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => \^rstdiv0_sync_r1_reg_rep__25_0\,
      I1 => bm_end_r1_1,
      O => bm_end_r1_reg_1
    );
\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r[3]_i_3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \^rstdiv0_sync_r1_reg_rep__25_0\,
      I1 => insert_maint_r,
      O => \generate_maint_cmds.insert_maint_r_lcl_reg\
    );
rst_sync_r1_reg: unisim.vcomponents.FDPE
     port map (
      C => \^mmcm_ps_clk\,
      CE => '1',
      D => rst_sync_r(11),
      PRE => rst_tmp,
      Q => rst_sync_r1
    );
\rst_sync_r_reg[0]\: unisim.vcomponents.FDPE
     port map (
      C => \^mmcm_ps_clk\,
      CE => '1',
      D => '0',
      PRE => rst_tmp,
      Q => rst_sync_r(0)
    );
\rst_sync_r_reg[10]\: unisim.vcomponents.FDPE
     port map (
      C => \^mmcm_ps_clk\,
      CE => '1',
      D => rst_sync_r(9),
      PRE => rst_tmp,
      Q => rst_sync_r(10)
    );
\rst_sync_r_reg[11]\: unisim.vcomponents.FDPE
     port map (
      C => \^mmcm_ps_clk\,
      CE => '1',
      D => rst_sync_r(10),
      PRE => rst_tmp,
      Q => rst_sync_r(11)
    );
\rst_sync_r_reg[1]\: unisim.vcomponents.FDPE
     port map (
      C => \^mmcm_ps_clk\,
      CE => '1',
      D => rst_sync_r(0),
      PRE => rst_tmp,
      Q => rst_sync_r(1)
    );
\rst_sync_r_reg[2]\: unisim.vcomponents.FDPE
     port map (
      C => \^mmcm_ps_clk\,
      CE => '1',
      D => rst_sync_r(1),
      PRE => rst_tmp,
      Q => rst_sync_r(2)
    );
\rst_sync_r_reg[3]\: unisim.vcomponents.FDPE
     port map (
      C => \^mmcm_ps_clk\,
      CE => '1',
      D => rst_sync_r(2),
      PRE => rst_tmp,
      Q => rst_sync_r(3)
    );
\rst_sync_r_reg[4]\: unisim.vcomponents.FDPE
     port map (
      C => \^mmcm_ps_clk\,
      CE => '1',
      D => rst_sync_r(3),
      PRE => rst_tmp,
      Q => rst_sync_r(4)
    );
\rst_sync_r_reg[5]\: unisim.vcomponents.FDPE
     port map (
      C => \^mmcm_ps_clk\,
      CE => '1',
      D => rst_sync_r(4),
      PRE => rst_tmp,
      Q => rst_sync_r(5)
    );
\rst_sync_r_reg[6]\: unisim.vcomponents.FDPE
     port map (
      C => \^mmcm_ps_clk\,
      CE => '1',
      D => rst_sync_r(5),
      PRE => rst_tmp,
      Q => rst_sync_r(6)
    );
\rst_sync_r_reg[7]\: unisim.vcomponents.FDPE
     port map (
      C => \^mmcm_ps_clk\,
      CE => '1',
      D => rst_sync_r(6),
      PRE => rst_tmp,
      Q => rst_sync_r(7)
    );
\rst_sync_r_reg[8]\: unisim.vcomponents.FDPE
     port map (
      C => \^mmcm_ps_clk\,
      CE => '1',
      D => rst_sync_r(7),
      PRE => rst_tmp,
      Q => rst_sync_r(8)
    );
\rst_sync_r_reg[9]\: unisim.vcomponents.FDPE
     port map (
      C => \^mmcm_ps_clk\,
      CE => '1',
      D => rst_sync_r(8),
      PRE => rst_tmp,
      Q => rst_sync_r(9)
    );
rstdiv0_sync_r1_inst: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => rstdiv0_sync_r1_reg_rep_n_0,
      O => rstdiv0_sync_r1_reg_rep_0
    );
rstdiv0_sync_r1_inst_rep: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \rstdiv0_sync_r1_reg_rep__0_n_0\,
      O => SR(0)
    );
\rstdiv0_sync_r1_inst_rep__0\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \rstdiv0_sync_r1_reg_rep__1_n_0\,
      O => SR(1)
    );
\rstdiv0_sync_r1_inst_rep__1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \rstdiv0_sync_r1_reg_rep__2_n_0\,
      O => \rstdiv0_sync_r1_reg_rep__2_0\(1)
    );
\rstdiv0_sync_r1_inst_rep__10\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \rstdiv0_sync_r1_reg_rep__11_n_0\,
      O => \rstdiv0_sync_r1_reg_rep__10_0\(0)
    );
\rstdiv0_sync_r1_inst_rep__11\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \rstdiv0_sync_r1_reg_rep__12_n_0\,
      O => \rstdiv0_sync_r1_reg_rep__12_0\
    );
\rstdiv0_sync_r1_inst_rep__12\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \rstdiv0_sync_r1_reg_rep__13_n_0\,
      O => \rstdiv0_sync_r1_reg_rep__13_0\
    );
\rstdiv0_sync_r1_inst_rep__13\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \rstdiv0_sync_r1_reg_rep__14_n_0\,
      O => \rstdiv0_sync_r1_reg_rep__14_0\(0)
    );
\rstdiv0_sync_r1_inst_rep__14\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \rstdiv0_sync_r1_reg_rep__15_n_0\,
      O => \rstdiv0_sync_r1_reg_rep__15_0\
    );
\rstdiv0_sync_r1_inst_rep__15\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \rstdiv0_sync_r1_reg_rep__16_n_0\,
      O => \rstdiv0_sync_r1_reg_rep__16_0\
    );
\rstdiv0_sync_r1_inst_rep__16\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \rstdiv0_sync_r1_reg_rep__17_n_0\,
      O => \rstdiv0_sync_r1_reg_rep__17_0\
    );
\rstdiv0_sync_r1_inst_rep__17\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \rstdiv0_sync_r1_reg_rep__18_n_0\,
      O => \rstdiv0_sync_r1_reg_rep__18_0\
    );
\rstdiv0_sync_r1_inst_rep__18\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \rstdiv0_sync_r1_reg_rep__19_n_0\,
      O => \rstdiv0_sync_r1_reg_rep__19_0\
    );
\rstdiv0_sync_r1_inst_rep__19\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \rstdiv0_sync_r1_reg_rep__20_n_0\,
      O => \rstdiv0_sync_r1_reg_rep__20_0\(0)
    );
\rstdiv0_sync_r1_inst_rep__2\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \rstdiv0_sync_r1_reg_rep__3_n_0\,
      O => \rstdiv0_sync_r1_reg_rep__2_0\(0)
    );
\rstdiv0_sync_r1_inst_rep__20\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \rstdiv0_sync_r1_reg_rep__21_n_0\,
      O => \^rstdiv0_sync_r1_reg_rep__21_0\
    );
\rstdiv0_sync_r1_inst_rep__21\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \rstdiv0_sync_r1_reg_rep__22_n_0\,
      O => \^rstdiv0_sync_r1_reg_rep__22_0\
    );
\rstdiv0_sync_r1_inst_rep__22\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \rstdiv0_sync_r1_reg_rep__23_n_0\,
      O => \^rstdiv0_sync_r1_reg_rep__23_0\
    );
\rstdiv0_sync_r1_inst_rep__23\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \rstdiv0_sync_r1_reg_rep__24_n_0\,
      O => \rstdiv0_sync_r1_reg_rep__24_0\
    );
\rstdiv0_sync_r1_inst_rep__24\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \rstdiv0_sync_r1_reg_rep__25_n_0\,
      O => \^rstdiv0_sync_r1_reg_rep__25_0\
    );
\rstdiv0_sync_r1_inst_rep__3\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \rstdiv0_sync_r1_reg_rep__4_n_0\,
      O => \rstdiv0_sync_r1_reg_rep__5_0\(0)
    );
\rstdiv0_sync_r1_inst_rep__4\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \rstdiv0_sync_r1_reg_rep__5_n_0\,
      O => \rstdiv0_sync_r1_reg_rep__5_0\(1)
    );
\rstdiv0_sync_r1_inst_rep__5\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \rstdiv0_sync_r1_reg_rep__6_n_0\,
      O => \rstdiv0_sync_r1_reg_rep__7_0\(0)
    );
\rstdiv0_sync_r1_inst_rep__6\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \rstdiv0_sync_r1_reg_rep__7_n_0\,
      O => \rstdiv0_sync_r1_reg_rep__7_0\(1)
    );
\rstdiv0_sync_r1_inst_rep__7\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \rstdiv0_sync_r1_reg_rep__8_n_0\,
      O => \rstdiv0_sync_r1_reg_rep__8_0\(0)
    );
\rstdiv0_sync_r1_inst_rep__8\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \rstdiv0_sync_r1_reg_rep__9_n_0\,
      O => \rstdiv0_sync_r1_reg_rep__9_0\
    );
\rstdiv0_sync_r1_inst_rep__9\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \rstdiv0_sync_r1_reg_rep__10_n_0\,
      O => \rstdiv0_sync_r1_reg_rep__10_0\(1)
    );
rstdiv0_sync_r1_reg_rep: unisim.vcomponents.FDPE
     port map (
      C => \^gen_mmcm.mmcm_i_0\,
      CE => '1',
      D => rstdiv0_sync_r(11),
      PRE => rst_tmp,
      Q => rstdiv0_sync_r1_reg_rep_n_0
    );
\rstdiv0_sync_r1_reg_rep__0\: unisim.vcomponents.FDPE
     port map (
      C => \^gen_mmcm.mmcm_i_0\,
      CE => '1',
      D => rstdiv0_sync_r(11),
      PRE => rst_tmp,
      Q => \rstdiv0_sync_r1_reg_rep__0_n_0\
    );
\rstdiv0_sync_r1_reg_rep__1\: unisim.vcomponents.FDPE
     port map (
      C => \^gen_mmcm.mmcm_i_0\,
      CE => '1',
      D => rstdiv0_sync_r(11),
      PRE => rst_tmp,
      Q => \rstdiv0_sync_r1_reg_rep__1_n_0\
    );
\rstdiv0_sync_r1_reg_rep__10\: unisim.vcomponents.FDPE
     port map (
      C => \^gen_mmcm.mmcm_i_0\,
      CE => '1',
      D => rstdiv0_sync_r(11),
      PRE => rst_tmp,
      Q => \rstdiv0_sync_r1_reg_rep__10_n_0\
    );
\rstdiv0_sync_r1_reg_rep__11\: unisim.vcomponents.FDPE
     port map (
      C => \^gen_mmcm.mmcm_i_0\,
      CE => '1',
      D => rstdiv0_sync_r(11),
      PRE => rst_tmp,
      Q => \rstdiv0_sync_r1_reg_rep__11_n_0\
    );
\rstdiv0_sync_r1_reg_rep__12\: unisim.vcomponents.FDPE
     port map (
      C => \^gen_mmcm.mmcm_i_0\,
      CE => '1',
      D => rstdiv0_sync_r(11),
      PRE => rst_tmp,
      Q => \rstdiv0_sync_r1_reg_rep__12_n_0\
    );
\rstdiv0_sync_r1_reg_rep__13\: unisim.vcomponents.FDPE
     port map (
      C => \^gen_mmcm.mmcm_i_0\,
      CE => '1',
      D => rstdiv0_sync_r(11),
      PRE => rst_tmp,
      Q => \rstdiv0_sync_r1_reg_rep__13_n_0\
    );
\rstdiv0_sync_r1_reg_rep__14\: unisim.vcomponents.FDPE
     port map (
      C => \^gen_mmcm.mmcm_i_0\,
      CE => '1',
      D => rstdiv0_sync_r(11),
      PRE => rst_tmp,
      Q => \rstdiv0_sync_r1_reg_rep__14_n_0\
    );
\rstdiv0_sync_r1_reg_rep__15\: unisim.vcomponents.FDPE
     port map (
      C => \^gen_mmcm.mmcm_i_0\,
      CE => '1',
      D => rstdiv0_sync_r(11),
      PRE => rst_tmp,
      Q => \rstdiv0_sync_r1_reg_rep__15_n_0\
    );
\rstdiv0_sync_r1_reg_rep__16\: unisim.vcomponents.FDPE
     port map (
      C => \^gen_mmcm.mmcm_i_0\,
      CE => '1',
      D => rstdiv0_sync_r(11),
      PRE => rst_tmp,
      Q => \rstdiv0_sync_r1_reg_rep__16_n_0\
    );
\rstdiv0_sync_r1_reg_rep__17\: unisim.vcomponents.FDPE
     port map (
      C => \^gen_mmcm.mmcm_i_0\,
      CE => '1',
      D => rstdiv0_sync_r(11),
      PRE => rst_tmp,
      Q => \rstdiv0_sync_r1_reg_rep__17_n_0\
    );
\rstdiv0_sync_r1_reg_rep__18\: unisim.vcomponents.FDPE
     port map (
      C => \^gen_mmcm.mmcm_i_0\,
      CE => '1',
      D => rstdiv0_sync_r(11),
      PRE => rst_tmp,
      Q => \rstdiv0_sync_r1_reg_rep__18_n_0\
    );
\rstdiv0_sync_r1_reg_rep__19\: unisim.vcomponents.FDPE
     port map (
      C => \^gen_mmcm.mmcm_i_0\,
      CE => '1',
      D => rstdiv0_sync_r(11),
      PRE => rst_tmp,
      Q => \rstdiv0_sync_r1_reg_rep__19_n_0\
    );
\rstdiv0_sync_r1_reg_rep__2\: unisim.vcomponents.FDPE
     port map (
      C => \^gen_mmcm.mmcm_i_0\,
      CE => '1',
      D => rstdiv0_sync_r(11),
      PRE => rst_tmp,
      Q => \rstdiv0_sync_r1_reg_rep__2_n_0\
    );
\rstdiv0_sync_r1_reg_rep__20\: unisim.vcomponents.FDPE
     port map (
      C => \^gen_mmcm.mmcm_i_0\,
      CE => '1',
      D => rstdiv0_sync_r(11),
      PRE => rst_tmp,
      Q => \rstdiv0_sync_r1_reg_rep__20_n_0\
    );
\rstdiv0_sync_r1_reg_rep__21\: unisim.vcomponents.FDPE
     port map (
      C => \^gen_mmcm.mmcm_i_0\,
      CE => '1',
      D => rstdiv0_sync_r(11),
      PRE => rst_tmp,
      Q => \rstdiv0_sync_r1_reg_rep__21_n_0\
    );
\rstdiv0_sync_r1_reg_rep__22\: unisim.vcomponents.FDPE
     port map (
      C => \^gen_mmcm.mmcm_i_0\,
      CE => '1',
      D => rstdiv0_sync_r(11),
      PRE => rst_tmp,
      Q => \rstdiv0_sync_r1_reg_rep__22_n_0\
    );
\rstdiv0_sync_r1_reg_rep__23\: unisim.vcomponents.FDPE
     port map (
      C => \^gen_mmcm.mmcm_i_0\,
      CE => '1',
      D => rstdiv0_sync_r(11),
      PRE => rst_tmp,
      Q => \rstdiv0_sync_r1_reg_rep__23_n_0\
    );
\rstdiv0_sync_r1_reg_rep__24\: unisim.vcomponents.FDPE
     port map (
      C => \^gen_mmcm.mmcm_i_0\,
      CE => '1',
      D => rstdiv0_sync_r(11),
      PRE => rst_tmp,
      Q => \rstdiv0_sync_r1_reg_rep__24_n_0\
    );
\rstdiv0_sync_r1_reg_rep__25\: unisim.vcomponents.FDPE
     port map (
      C => \^gen_mmcm.mmcm_i_0\,
      CE => '1',
      D => rstdiv0_sync_r(11),
      PRE => rst_tmp,
      Q => \rstdiv0_sync_r1_reg_rep__25_n_0\
    );
\rstdiv0_sync_r1_reg_rep__3\: unisim.vcomponents.FDPE
     port map (
      C => \^gen_mmcm.mmcm_i_0\,
      CE => '1',
      D => rstdiv0_sync_r(11),
      PRE => rst_tmp,
      Q => \rstdiv0_sync_r1_reg_rep__3_n_0\
    );
\rstdiv0_sync_r1_reg_rep__4\: unisim.vcomponents.FDPE
     port map (
      C => \^gen_mmcm.mmcm_i_0\,
      CE => '1',
      D => rstdiv0_sync_r(11),
      PRE => rst_tmp,
      Q => \rstdiv0_sync_r1_reg_rep__4_n_0\
    );
\rstdiv0_sync_r1_reg_rep__5\: unisim.vcomponents.FDPE
     port map (
      C => \^gen_mmcm.mmcm_i_0\,
      CE => '1',
      D => rstdiv0_sync_r(11),
      PRE => rst_tmp,
      Q => \rstdiv0_sync_r1_reg_rep__5_n_0\
    );
\rstdiv0_sync_r1_reg_rep__6\: unisim.vcomponents.FDPE
     port map (
      C => \^gen_mmcm.mmcm_i_0\,
      CE => '1',
      D => rstdiv0_sync_r(11),
      PRE => rst_tmp,
      Q => \rstdiv0_sync_r1_reg_rep__6_n_0\
    );
\rstdiv0_sync_r1_reg_rep__7\: unisim.vcomponents.FDPE
     port map (
      C => \^gen_mmcm.mmcm_i_0\,
      CE => '1',
      D => rstdiv0_sync_r(11),
      PRE => rst_tmp,
      Q => \rstdiv0_sync_r1_reg_rep__7_n_0\
    );
\rstdiv0_sync_r1_reg_rep__8\: unisim.vcomponents.FDPE
     port map (
      C => \^gen_mmcm.mmcm_i_0\,
      CE => '1',
      D => rstdiv0_sync_r(11),
      PRE => rst_tmp,
      Q => \rstdiv0_sync_r1_reg_rep__8_n_0\
    );
\rstdiv0_sync_r1_reg_rep__9\: unisim.vcomponents.FDPE
     port map (
      C => \^gen_mmcm.mmcm_i_0\,
      CE => '1',
      D => rstdiv0_sync_r(11),
      PRE => rst_tmp,
      Q => \rstdiv0_sync_r1_reg_rep__9_n_0\
    );
\rstdiv0_sync_r_reg[0]\: unisim.vcomponents.FDPE
     port map (
      C => \^gen_mmcm.mmcm_i_0\,
      CE => '1',
      D => '0',
      PRE => rst_tmp,
      Q => rstdiv0_sync_r(0)
    );
\rstdiv0_sync_r_reg[10]\: unisim.vcomponents.FDPE
     port map (
      C => \^gen_mmcm.mmcm_i_0\,
      CE => '1',
      D => rstdiv0_sync_r(9),
      PRE => rst_tmp,
      Q => rstdiv0_sync_r(10)
    );
\rstdiv0_sync_r_reg[11]\: unisim.vcomponents.FDPE
     port map (
      C => \^gen_mmcm.mmcm_i_0\,
      CE => '1',
      D => rstdiv0_sync_r(10),
      PRE => rst_tmp,
      Q => rstdiv0_sync_r(11)
    );
\rstdiv0_sync_r_reg[1]\: unisim.vcomponents.FDPE
     port map (
      C => \^gen_mmcm.mmcm_i_0\,
      CE => '1',
      D => rstdiv0_sync_r(0),
      PRE => rst_tmp,
      Q => rstdiv0_sync_r(1)
    );
\rstdiv0_sync_r_reg[2]\: unisim.vcomponents.FDPE
     port map (
      C => \^gen_mmcm.mmcm_i_0\,
      CE => '1',
      D => rstdiv0_sync_r(1),
      PRE => rst_tmp,
      Q => rstdiv0_sync_r(2)
    );
\rstdiv0_sync_r_reg[3]\: unisim.vcomponents.FDPE
     port map (
      C => \^gen_mmcm.mmcm_i_0\,
      CE => '1',
      D => rstdiv0_sync_r(2),
      PRE => rst_tmp,
      Q => rstdiv0_sync_r(3)
    );
\rstdiv0_sync_r_reg[4]\: unisim.vcomponents.FDPE
     port map (
      C => \^gen_mmcm.mmcm_i_0\,
      CE => '1',
      D => rstdiv0_sync_r(3),
      PRE => rst_tmp,
      Q => rstdiv0_sync_r(4)
    );
\rstdiv0_sync_r_reg[5]\: unisim.vcomponents.FDPE
     port map (
      C => \^gen_mmcm.mmcm_i_0\,
      CE => '1',
      D => rstdiv0_sync_r(4),
      PRE => rst_tmp,
      Q => rstdiv0_sync_r(5)
    );
\rstdiv0_sync_r_reg[6]\: unisim.vcomponents.FDPE
     port map (
      C => \^gen_mmcm.mmcm_i_0\,
      CE => '1',
      D => rstdiv0_sync_r(5),
      PRE => rst_tmp,
      Q => rstdiv0_sync_r(6)
    );
\rstdiv0_sync_r_reg[7]\: unisim.vcomponents.FDPE
     port map (
      C => \^gen_mmcm.mmcm_i_0\,
      CE => '1',
      D => rstdiv0_sync_r(6),
      PRE => rst_tmp,
      Q => rstdiv0_sync_r(7)
    );
\rstdiv0_sync_r_reg[8]\: unisim.vcomponents.FDPE
     port map (
      C => \^gen_mmcm.mmcm_i_0\,
      CE => '1',
      D => rstdiv0_sync_r(7),
      PRE => rst_tmp,
      Q => rstdiv0_sync_r(8)
    );
\rstdiv0_sync_r_reg[9]\: unisim.vcomponents.FDPE
     port map (
      C => \^gen_mmcm.mmcm_i_0\,
      CE => '1',
      D => rstdiv0_sync_r(8),
      PRE => rst_tmp,
      Q => rstdiv0_sync_r(9)
    );
rstdiv2_sync_r1_reg: unisim.vcomponents.FDPE
     port map (
      C => \gen_mmcm.u_bufg_clk_div2_n_0\,
      CE => '1',
      D => p_0_in,
      PRE => rst_tmp,
      Q => rstdiv2_sync_r1
    );
\rstdiv2_sync_r_reg[0]\: unisim.vcomponents.FDPE
     port map (
      C => \gen_mmcm.u_bufg_clk_div2_n_0\,
      CE => '1',
      D => '0',
      PRE => rst_tmp,
      Q => \rstdiv2_sync_r_reg_n_0_[0]\
    );
\rstdiv2_sync_r_reg[10]\: unisim.vcomponents.FDPE
     port map (
      C => \gen_mmcm.u_bufg_clk_div2_n_0\,
      CE => '1',
      D => \rstdiv2_sync_r_reg_n_0_[9]\,
      PRE => rst_tmp,
      Q => \rstdiv2_sync_r_reg_n_0_[10]\
    );
\rstdiv2_sync_r_reg[11]\: unisim.vcomponents.FDPE
     port map (
      C => \gen_mmcm.u_bufg_clk_div2_n_0\,
      CE => '1',
      D => \rstdiv2_sync_r_reg_n_0_[10]\,
      PRE => rst_tmp,
      Q => p_0_in
    );
\rstdiv2_sync_r_reg[1]\: unisim.vcomponents.FDPE
     port map (
      C => \gen_mmcm.u_bufg_clk_div2_n_0\,
      CE => '1',
      D => \rstdiv2_sync_r_reg_n_0_[0]\,
      PRE => rst_tmp,
      Q => \rstdiv2_sync_r_reg_n_0_[1]\
    );
\rstdiv2_sync_r_reg[2]\: unisim.vcomponents.FDPE
     port map (
      C => \gen_mmcm.u_bufg_clk_div2_n_0\,
      CE => '1',
      D => \rstdiv2_sync_r_reg_n_0_[1]\,
      PRE => rst_tmp,
      Q => \rstdiv2_sync_r_reg_n_0_[2]\
    );
\rstdiv2_sync_r_reg[3]\: unisim.vcomponents.FDPE
     port map (
      C => \gen_mmcm.u_bufg_clk_div2_n_0\,
      CE => '1',
      D => \rstdiv2_sync_r_reg_n_0_[2]\,
      PRE => rst_tmp,
      Q => \rstdiv2_sync_r_reg_n_0_[3]\
    );
\rstdiv2_sync_r_reg[4]\: unisim.vcomponents.FDPE
     port map (
      C => \gen_mmcm.u_bufg_clk_div2_n_0\,
      CE => '1',
      D => \rstdiv2_sync_r_reg_n_0_[3]\,
      PRE => rst_tmp,
      Q => \rstdiv2_sync_r_reg_n_0_[4]\
    );
\rstdiv2_sync_r_reg[5]\: unisim.vcomponents.FDPE
     port map (
      C => \gen_mmcm.u_bufg_clk_div2_n_0\,
      CE => '1',
      D => \rstdiv2_sync_r_reg_n_0_[4]\,
      PRE => rst_tmp,
      Q => \rstdiv2_sync_r_reg_n_0_[5]\
    );
\rstdiv2_sync_r_reg[6]\: unisim.vcomponents.FDPE
     port map (
      C => \gen_mmcm.u_bufg_clk_div2_n_0\,
      CE => '1',
      D => \rstdiv2_sync_r_reg_n_0_[5]\,
      PRE => rst_tmp,
      Q => \rstdiv2_sync_r_reg_n_0_[6]\
    );
\rstdiv2_sync_r_reg[7]\: unisim.vcomponents.FDPE
     port map (
      C => \gen_mmcm.u_bufg_clk_div2_n_0\,
      CE => '1',
      D => \rstdiv2_sync_r_reg_n_0_[6]\,
      PRE => rst_tmp,
      Q => \rstdiv2_sync_r_reg_n_0_[7]\
    );
\rstdiv2_sync_r_reg[8]\: unisim.vcomponents.FDPE
     port map (
      C => \gen_mmcm.u_bufg_clk_div2_n_0\,
      CE => '1',
      D => \rstdiv2_sync_r_reg_n_0_[7]\,
      PRE => rst_tmp,
      Q => \rstdiv2_sync_r_reg_n_0_[8]\
    );
\rstdiv2_sync_r_reg[9]\: unisim.vcomponents.FDPE
     port map (
      C => \gen_mmcm.u_bufg_clk_div2_n_0\,
      CE => '1',
      D => \rstdiv2_sync_r_reg_n_0_[8]\,
      PRE => rst_tmp,
      Q => \rstdiv2_sync_r_reg_n_0_[9]\
    );
\samp_edge_cnt0_r[0]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => \^rstdiv0_sync_r1_reg_rep__21_0\,
      I1 => samp_edge_cnt0_en_r,
      O => samp_edge_cnt0_en_r_reg
    );
\tap_cnt_cpt_r[5]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => \^rstdiv0_sync_r1_reg_rep__21_0\,
      I1 => \tap_cnt_cpt_r_reg[5]\,
      O => new_cnt_cpt_r_reg(0)
    );
u_bufg_clkdiv0: unisim.vcomponents.BUFG
     port map (
      I => clk_pll_i,
      O => \^gen_mmcm.mmcm_i_0\
    );
u_bufh_pll_clk3: unisim.vcomponents.BUFH
     port map (
      I => pll_clk3_out,
      O => pll_clk3
    );
\wait_cnt[3]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => \^rstdiv0_sync_r1_reg_rep__21_0\,
      I1 => po_cnt_dec,
      O => SS(0)
    );
\wait_cnt_r[3]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => \^rstdiv0_sync_r1_reg_rep__21_0\,
      I1 => po_cnt_dec_2,
      O => po_cnt_dec_reg(0)
    );
\wait_cnt_r[3]_i_1__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => \^rstdiv0_sync_r1_reg_rep__22_0\,
      I1 => pi_cnt_dec,
      O => pi_cnt_dec_reg(0)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mig_mig_7series_v4_2_iodelay_ctrl is
  port (
    iodelay_ctrl_rdy : out STD_LOGIC_VECTOR ( 0 to 0 );
    \out\ : out STD_LOGIC;
    AS : out STD_LOGIC_VECTOR ( 0 to 0 );
    clk_ref_i : in STD_LOGIC;
    sys_rst : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of mig_mig_7series_v4_2_iodelay_ctrl : entity is "mig_7series_v4_2_iodelay_ctrl";
end mig_mig_7series_v4_2_iodelay_ctrl;

architecture STRUCTURE of mig_mig_7series_v4_2_iodelay_ctrl is
  signal \^as\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal rst_ref : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \rst_ref_sync_r_reg_n_0_[0][0]\ : STD_LOGIC;
  signal \rst_ref_sync_r_reg_n_0_[0][10]\ : STD_LOGIC;
  signal \rst_ref_sync_r_reg_n_0_[0][11]\ : STD_LOGIC;
  signal \rst_ref_sync_r_reg_n_0_[0][12]\ : STD_LOGIC;
  signal \rst_ref_sync_r_reg_n_0_[0][13]\ : STD_LOGIC;
  signal \rst_ref_sync_r_reg_n_0_[0][1]\ : STD_LOGIC;
  signal \rst_ref_sync_r_reg_n_0_[0][2]\ : STD_LOGIC;
  signal \rst_ref_sync_r_reg_n_0_[0][3]\ : STD_LOGIC;
  signal \rst_ref_sync_r_reg_n_0_[0][4]\ : STD_LOGIC;
  signal \rst_ref_sync_r_reg_n_0_[0][5]\ : STD_LOGIC;
  signal \rst_ref_sync_r_reg_n_0_[0][6]\ : STD_LOGIC;
  signal \rst_ref_sync_r_reg_n_0_[0][7]\ : STD_LOGIC;
  signal \rst_ref_sync_r_reg_n_0_[0][8]\ : STD_LOGIC;
  signal \rst_ref_sync_r_reg_n_0_[0][9]\ : STD_LOGIC;
  signal sys_rst_i : STD_LOGIC;
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of sys_rst_i : signal is "true";
  attribute syn_maxfan : string;
  attribute syn_maxfan of \rst_ref_sync_r_reg[0][0]\ : label is "10";
  attribute syn_maxfan of \rst_ref_sync_r_reg[0][10]\ : label is "10";
  attribute syn_maxfan of \rst_ref_sync_r_reg[0][11]\ : label is "10";
  attribute syn_maxfan of \rst_ref_sync_r_reg[0][12]\ : label is "10";
  attribute syn_maxfan of \rst_ref_sync_r_reg[0][13]\ : label is "10";
  attribute syn_maxfan of \rst_ref_sync_r_reg[0][14]\ : label is "10";
  attribute syn_maxfan of \rst_ref_sync_r_reg[0][1]\ : label is "10";
  attribute syn_maxfan of \rst_ref_sync_r_reg[0][2]\ : label is "10";
  attribute syn_maxfan of \rst_ref_sync_r_reg[0][3]\ : label is "10";
  attribute syn_maxfan of \rst_ref_sync_r_reg[0][4]\ : label is "10";
  attribute syn_maxfan of \rst_ref_sync_r_reg[0][5]\ : label is "10";
  attribute syn_maxfan of \rst_ref_sync_r_reg[0][6]\ : label is "10";
  attribute syn_maxfan of \rst_ref_sync_r_reg[0][7]\ : label is "10";
  attribute syn_maxfan of \rst_ref_sync_r_reg[0][8]\ : label is "10";
  attribute syn_maxfan of \rst_ref_sync_r_reg[0][9]\ : label is "10";
  attribute BOX_TYPE : string;
  attribute BOX_TYPE of u_idelayctrl_200 : label is "PRIMITIVE";
  attribute IODELAY_GROUP : string;
  attribute IODELAY_GROUP of u_idelayctrl_200 : label is "MIG_IODELAY_MIG0";
begin
  AS(0) <= \^as\(0);
  \out\ <= sys_rst_i;
  sys_rst_i <= sys_rst;
plle2_i_i_1: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => sys_rst_i,
      O => \^as\(0)
    );
\rst_ref_sync_r_reg[0][0]\: unisim.vcomponents.FDPE
     port map (
      C => clk_ref_i,
      CE => '1',
      D => '0',
      PRE => \^as\(0),
      Q => \rst_ref_sync_r_reg_n_0_[0][0]\
    );
\rst_ref_sync_r_reg[0][10]\: unisim.vcomponents.FDPE
     port map (
      C => clk_ref_i,
      CE => '1',
      D => \rst_ref_sync_r_reg_n_0_[0][9]\,
      PRE => \^as\(0),
      Q => \rst_ref_sync_r_reg_n_0_[0][10]\
    );
\rst_ref_sync_r_reg[0][11]\: unisim.vcomponents.FDPE
     port map (
      C => clk_ref_i,
      CE => '1',
      D => \rst_ref_sync_r_reg_n_0_[0][10]\,
      PRE => \^as\(0),
      Q => \rst_ref_sync_r_reg_n_0_[0][11]\
    );
\rst_ref_sync_r_reg[0][12]\: unisim.vcomponents.FDPE
     port map (
      C => clk_ref_i,
      CE => '1',
      D => \rst_ref_sync_r_reg_n_0_[0][11]\,
      PRE => \^as\(0),
      Q => \rst_ref_sync_r_reg_n_0_[0][12]\
    );
\rst_ref_sync_r_reg[0][13]\: unisim.vcomponents.FDPE
     port map (
      C => clk_ref_i,
      CE => '1',
      D => \rst_ref_sync_r_reg_n_0_[0][12]\,
      PRE => \^as\(0),
      Q => \rst_ref_sync_r_reg_n_0_[0][13]\
    );
\rst_ref_sync_r_reg[0][14]\: unisim.vcomponents.FDPE
     port map (
      C => clk_ref_i,
      CE => '1',
      D => \rst_ref_sync_r_reg_n_0_[0][13]\,
      PRE => \^as\(0),
      Q => rst_ref(0)
    );
\rst_ref_sync_r_reg[0][1]\: unisim.vcomponents.FDPE
     port map (
      C => clk_ref_i,
      CE => '1',
      D => \rst_ref_sync_r_reg_n_0_[0][0]\,
      PRE => \^as\(0),
      Q => \rst_ref_sync_r_reg_n_0_[0][1]\
    );
\rst_ref_sync_r_reg[0][2]\: unisim.vcomponents.FDPE
     port map (
      C => clk_ref_i,
      CE => '1',
      D => \rst_ref_sync_r_reg_n_0_[0][1]\,
      PRE => \^as\(0),
      Q => \rst_ref_sync_r_reg_n_0_[0][2]\
    );
\rst_ref_sync_r_reg[0][3]\: unisim.vcomponents.FDPE
     port map (
      C => clk_ref_i,
      CE => '1',
      D => \rst_ref_sync_r_reg_n_0_[0][2]\,
      PRE => \^as\(0),
      Q => \rst_ref_sync_r_reg_n_0_[0][3]\
    );
\rst_ref_sync_r_reg[0][4]\: unisim.vcomponents.FDPE
     port map (
      C => clk_ref_i,
      CE => '1',
      D => \rst_ref_sync_r_reg_n_0_[0][3]\,
      PRE => \^as\(0),
      Q => \rst_ref_sync_r_reg_n_0_[0][4]\
    );
\rst_ref_sync_r_reg[0][5]\: unisim.vcomponents.FDPE
     port map (
      C => clk_ref_i,
      CE => '1',
      D => \rst_ref_sync_r_reg_n_0_[0][4]\,
      PRE => \^as\(0),
      Q => \rst_ref_sync_r_reg_n_0_[0][5]\
    );
\rst_ref_sync_r_reg[0][6]\: unisim.vcomponents.FDPE
     port map (
      C => clk_ref_i,
      CE => '1',
      D => \rst_ref_sync_r_reg_n_0_[0][5]\,
      PRE => \^as\(0),
      Q => \rst_ref_sync_r_reg_n_0_[0][6]\
    );
\rst_ref_sync_r_reg[0][7]\: unisim.vcomponents.FDPE
     port map (
      C => clk_ref_i,
      CE => '1',
      D => \rst_ref_sync_r_reg_n_0_[0][6]\,
      PRE => \^as\(0),
      Q => \rst_ref_sync_r_reg_n_0_[0][7]\
    );
\rst_ref_sync_r_reg[0][8]\: unisim.vcomponents.FDPE
     port map (
      C => clk_ref_i,
      CE => '1',
      D => \rst_ref_sync_r_reg_n_0_[0][7]\,
      PRE => \^as\(0),
      Q => \rst_ref_sync_r_reg_n_0_[0][8]\
    );
\rst_ref_sync_r_reg[0][9]\: unisim.vcomponents.FDPE
     port map (
      C => clk_ref_i,
      CE => '1',
      D => \rst_ref_sync_r_reg_n_0_[0][8]\,
      PRE => \^as\(0),
      Q => \rst_ref_sync_r_reg_n_0_[0][9]\
    );
u_idelayctrl_200: unisim.vcomponents.IDELAYCTRL
    generic map(
      SIM_DEVICE => "7SERIES"
    )
        port map (
      RDY => iodelay_ctrl_rdy(0),
      REFCLK => clk_ref_i,
      RST => rst_ref(0)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mig_mig_7series_v4_2_poc_pd is
  port (
    mmcm_ps_clk : in STD_LOGIC;
    in_dqs_lpbk_to_iddr_0 : in STD_LOGIC;
    rst_sync_r1 : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of mig_mig_7series_v4_2_poc_pd : entity is "mig_7series_v4_2_poc_pd";
end mig_mig_7series_v4_2_poc_pd;

architecture STRUCTURE of mig_mig_7series_v4_2_poc_pd is
  signal q1 : STD_LOGIC;
  signal NLW_u_phase_detector_Q2_UNCONNECTED : STD_LOGIC;
  attribute BOX_TYPE : string;
  attribute BOX_TYPE of u_phase_detector : label is "PRIMITIVE";
  attribute \__SRVAL\ : string;
  attribute \__SRVAL\ of u_phase_detector : label is "FALSE";
begin
u_phase_detector: unisim.vcomponents.IDDR
    generic map(
      DDR_CLK_EDGE => "OPPOSITE_EDGE",
      INIT_Q1 => '0',
      INIT_Q2 => '0',
      IS_C_INVERTED => '0',
      IS_D_INVERTED => '0',
      SRTYPE => "SYNC"
    )
        port map (
      C => mmcm_ps_clk,
      CE => '1',
      D => in_dqs_lpbk_to_iddr_0,
      Q1 => q1,
      Q2 => NLW_u_phase_detector_Q2_UNCONNECTED,
      R => rst_sync_r1,
      S => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mig_mig_7series_v4_2_poc_pd_10 is
  port (
    mmcm_ps_clk : in STD_LOGIC;
    in_dqs_lpbk_to_iddr_6 : in STD_LOGIC;
    rst_sync_r1 : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of mig_mig_7series_v4_2_poc_pd_10 : entity is "mig_7series_v4_2_poc_pd";
end mig_mig_7series_v4_2_poc_pd_10;

architecture STRUCTURE of mig_mig_7series_v4_2_poc_pd_10 is
  signal q1 : STD_LOGIC;
  signal NLW_u_phase_detector_Q2_UNCONNECTED : STD_LOGIC;
  attribute BOX_TYPE : string;
  attribute BOX_TYPE of u_phase_detector : label is "PRIMITIVE";
  attribute \__SRVAL\ : string;
  attribute \__SRVAL\ of u_phase_detector : label is "FALSE";
begin
u_phase_detector: unisim.vcomponents.IDDR
    generic map(
      DDR_CLK_EDGE => "OPPOSITE_EDGE",
      INIT_Q1 => '0',
      INIT_Q2 => '0',
      IS_C_INVERTED => '0',
      IS_D_INVERTED => '0',
      SRTYPE => "SYNC"
    )
        port map (
      C => mmcm_ps_clk,
      CE => '1',
      D => in_dqs_lpbk_to_iddr_6,
      Q1 => q1,
      Q2 => NLW_u_phase_detector_Q2_UNCONNECTED,
      R => rst_sync_r1,
      S => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mig_mig_7series_v4_2_poc_pd_11 is
  port (
    mmcm_ps_clk : in STD_LOGIC;
    in_dqs_lpbk_to_iddr_7 : in STD_LOGIC;
    rst_sync_r1 : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of mig_mig_7series_v4_2_poc_pd_11 : entity is "mig_7series_v4_2_poc_pd";
end mig_mig_7series_v4_2_poc_pd_11;

architecture STRUCTURE of mig_mig_7series_v4_2_poc_pd_11 is
  signal q1 : STD_LOGIC;
  signal NLW_u_phase_detector_Q2_UNCONNECTED : STD_LOGIC;
  attribute BOX_TYPE : string;
  attribute BOX_TYPE of u_phase_detector : label is "PRIMITIVE";
  attribute \__SRVAL\ : string;
  attribute \__SRVAL\ of u_phase_detector : label is "FALSE";
begin
u_phase_detector: unisim.vcomponents.IDDR
    generic map(
      DDR_CLK_EDGE => "OPPOSITE_EDGE",
      INIT_Q1 => '0',
      INIT_Q2 => '0',
      IS_C_INVERTED => '0',
      IS_D_INVERTED => '0',
      SRTYPE => "SYNC"
    )
        port map (
      C => mmcm_ps_clk,
      CE => '1',
      D => in_dqs_lpbk_to_iddr_7,
      Q1 => q1,
      Q2 => NLW_u_phase_detector_Q2_UNCONNECTED,
      R => rst_sync_r1,
      S => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mig_mig_7series_v4_2_poc_pd_5 is
  port (
    mmcm_ps_clk : in STD_LOGIC;
    in_dqs_lpbk_to_iddr_1 : in STD_LOGIC;
    rst_sync_r1 : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of mig_mig_7series_v4_2_poc_pd_5 : entity is "mig_7series_v4_2_poc_pd";
end mig_mig_7series_v4_2_poc_pd_5;

architecture STRUCTURE of mig_mig_7series_v4_2_poc_pd_5 is
  signal q1 : STD_LOGIC;
  signal NLW_u_phase_detector_Q2_UNCONNECTED : STD_LOGIC;
  attribute BOX_TYPE : string;
  attribute BOX_TYPE of u_phase_detector : label is "PRIMITIVE";
  attribute \__SRVAL\ : string;
  attribute \__SRVAL\ of u_phase_detector : label is "FALSE";
begin
u_phase_detector: unisim.vcomponents.IDDR
    generic map(
      DDR_CLK_EDGE => "OPPOSITE_EDGE",
      INIT_Q1 => '0',
      INIT_Q2 => '0',
      IS_C_INVERTED => '0',
      IS_D_INVERTED => '0',
      SRTYPE => "SYNC"
    )
        port map (
      C => mmcm_ps_clk,
      CE => '1',
      D => in_dqs_lpbk_to_iddr_1,
      Q1 => q1,
      Q2 => NLW_u_phase_detector_Q2_UNCONNECTED,
      R => rst_sync_r1,
      S => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mig_mig_7series_v4_2_poc_pd_6 is
  port (
    mmcm_ps_clk : in STD_LOGIC;
    in_dqs_lpbk_to_iddr_2 : in STD_LOGIC;
    rst_sync_r1 : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of mig_mig_7series_v4_2_poc_pd_6 : entity is "mig_7series_v4_2_poc_pd";
end mig_mig_7series_v4_2_poc_pd_6;

architecture STRUCTURE of mig_mig_7series_v4_2_poc_pd_6 is
  signal q1 : STD_LOGIC;
  signal NLW_u_phase_detector_Q2_UNCONNECTED : STD_LOGIC;
  attribute BOX_TYPE : string;
  attribute BOX_TYPE of u_phase_detector : label is "PRIMITIVE";
  attribute \__SRVAL\ : string;
  attribute \__SRVAL\ of u_phase_detector : label is "FALSE";
begin
u_phase_detector: unisim.vcomponents.IDDR
    generic map(
      DDR_CLK_EDGE => "OPPOSITE_EDGE",
      INIT_Q1 => '0',
      INIT_Q2 => '0',
      IS_C_INVERTED => '0',
      IS_D_INVERTED => '0',
      SRTYPE => "SYNC"
    )
        port map (
      C => mmcm_ps_clk,
      CE => '1',
      D => in_dqs_lpbk_to_iddr_2,
      Q1 => q1,
      Q2 => NLW_u_phase_detector_Q2_UNCONNECTED,
      R => rst_sync_r1,
      S => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mig_mig_7series_v4_2_poc_pd_7 is
  port (
    mmcm_ps_clk : in STD_LOGIC;
    in_dqs_lpbk_to_iddr_3 : in STD_LOGIC;
    rst_sync_r1 : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of mig_mig_7series_v4_2_poc_pd_7 : entity is "mig_7series_v4_2_poc_pd";
end mig_mig_7series_v4_2_poc_pd_7;

architecture STRUCTURE of mig_mig_7series_v4_2_poc_pd_7 is
  signal q1 : STD_LOGIC;
  signal NLW_u_phase_detector_Q2_UNCONNECTED : STD_LOGIC;
  attribute BOX_TYPE : string;
  attribute BOX_TYPE of u_phase_detector : label is "PRIMITIVE";
  attribute \__SRVAL\ : string;
  attribute \__SRVAL\ of u_phase_detector : label is "FALSE";
begin
u_phase_detector: unisim.vcomponents.IDDR
    generic map(
      DDR_CLK_EDGE => "OPPOSITE_EDGE",
      INIT_Q1 => '0',
      INIT_Q2 => '0',
      IS_C_INVERTED => '0',
      IS_D_INVERTED => '0',
      SRTYPE => "SYNC"
    )
        port map (
      C => mmcm_ps_clk,
      CE => '1',
      D => in_dqs_lpbk_to_iddr_3,
      Q1 => q1,
      Q2 => NLW_u_phase_detector_Q2_UNCONNECTED,
      R => rst_sync_r1,
      S => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mig_mig_7series_v4_2_poc_pd_8 is
  port (
    mmcm_ps_clk : in STD_LOGIC;
    in_dqs_lpbk_to_iddr_4 : in STD_LOGIC;
    rst_sync_r1 : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of mig_mig_7series_v4_2_poc_pd_8 : entity is "mig_7series_v4_2_poc_pd";
end mig_mig_7series_v4_2_poc_pd_8;

architecture STRUCTURE of mig_mig_7series_v4_2_poc_pd_8 is
  signal q1 : STD_LOGIC;
  signal NLW_u_phase_detector_Q2_UNCONNECTED : STD_LOGIC;
  attribute BOX_TYPE : string;
  attribute BOX_TYPE of u_phase_detector : label is "PRIMITIVE";
  attribute \__SRVAL\ : string;
  attribute \__SRVAL\ of u_phase_detector : label is "FALSE";
begin
u_phase_detector: unisim.vcomponents.IDDR
    generic map(
      DDR_CLK_EDGE => "OPPOSITE_EDGE",
      INIT_Q1 => '0',
      INIT_Q2 => '0',
      IS_C_INVERTED => '0',
      IS_D_INVERTED => '0',
      SRTYPE => "SYNC"
    )
        port map (
      C => mmcm_ps_clk,
      CE => '1',
      D => in_dqs_lpbk_to_iddr_4,
      Q1 => q1,
      Q2 => NLW_u_phase_detector_Q2_UNCONNECTED,
      R => rst_sync_r1,
      S => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mig_mig_7series_v4_2_poc_pd_9 is
  port (
    mmcm_ps_clk : in STD_LOGIC;
    in_dqs_lpbk_to_iddr_5 : in STD_LOGIC;
    rst_sync_r1 : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of mig_mig_7series_v4_2_poc_pd_9 : entity is "mig_7series_v4_2_poc_pd";
end mig_mig_7series_v4_2_poc_pd_9;

architecture STRUCTURE of mig_mig_7series_v4_2_poc_pd_9 is
  signal q1 : STD_LOGIC;
  signal NLW_u_phase_detector_Q2_UNCONNECTED : STD_LOGIC;
  attribute BOX_TYPE : string;
  attribute BOX_TYPE of u_phase_detector : label is "PRIMITIVE";
  attribute \__SRVAL\ : string;
  attribute \__SRVAL\ of u_phase_detector : label is "FALSE";
begin
u_phase_detector: unisim.vcomponents.IDDR
    generic map(
      DDR_CLK_EDGE => "OPPOSITE_EDGE",
      INIT_Q1 => '0',
      INIT_Q2 => '0',
      IS_C_INVERTED => '0',
      IS_D_INVERTED => '0',
      SRTYPE => "SYNC"
    )
        port map (
      C => mmcm_ps_clk,
      CE => '1',
      D => in_dqs_lpbk_to_iddr_5,
      Q1 => q1,
      Q2 => NLW_u_phase_detector_Q2_UNCONNECTED,
      R => rst_sync_r1,
      S => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mig_mig_7series_v4_2_rank_cntrl is
  port (
    \inhbt_act_faw.act_delayed\ : out STD_LOGIC;
    \periodic_rd_generation.read_this_rank_r\ : out STD_LOGIC;
    inhbt_act_faw_r : out STD_LOGIC;
    \periodic_rd_generation.periodic_rd_request_r\ : out STD_LOGIC;
    \periodic_rd_generation.periodic_rd_cntr1_r\ : out STD_LOGIC;
    \refresh_generation.refresh_bank_r_reg[0]_0\ : out STD_LOGIC;
    \wtr_timer.wtr_cnt_r_reg[1]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \periodic_rd_generation.periodic_rd_timer_r_reg[2]_0\ : out STD_LOGIC;
    \inhbt_act_faw.faw_cnt_r_reg[2]_0\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
    \rtw_timer.rtw_cnt_r_reg[1]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    act_this_rank : in STD_LOGIC;
    \periodic_rd_generation.periodic_rd_request_r_reg_0\ : in STD_LOGIC;
    \periodic_rd_generation.read_this_rank\ : in STD_LOGIC;
    SR : in STD_LOGIC_VECTOR ( 0 to 0 );
    \periodic_rd_generation.periodic_rd_request_r_reg_1\ : in STD_LOGIC;
    \periodic_rd_generation.periodic_rd_cntr1_r_reg_0\ : in STD_LOGIC;
    \periodic_rd_generation.periodic_rd_cntr1_r_reg_1\ : in STD_LOGIC;
    \refresh_generation.refresh_bank_r_reg[0]_1\ : in STD_LOGIC;
    \periodic_rd_generation.periodic_rd_timer_r_reg[2]_1\ : in STD_LOGIC;
    \periodic_rd_generation.periodic_rd_timer_r_reg[2]_2\ : in STD_LOGIC;
    maint_prescaler_tick_r : in STD_LOGIC;
    \wtr_timer.wtr_cnt_r_reg[1]_1\ : in STD_LOGIC;
    \wtr_timer.wtr_cnt_r_reg[1]_2\ : in STD_LOGIC;
    \inhbt_act_faw.inhbt_act_faw_r_reg_0\ : in STD_LOGIC;
    \inhbt_act_faw.inhbt_act_faw_r_reg_1\ : in STD_LOGIC;
    \inhbt_act_faw.faw_cnt_r_reg[2]_1\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
    \wtr_timer.wtr_cnt_r_reg[0]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \rtw_timer.rtw_cnt_r_reg[1]_1\ : in STD_LOGIC_VECTOR ( 1 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of mig_mig_7series_v4_2_rank_cntrl : entity is "mig_7series_v4_2_rank_cntrl";
end mig_mig_7series_v4_2_rank_cntrl;

architecture STRUCTURE of mig_mig_7series_v4_2_rank_cntrl is
  signal \^inhbt_act_faw.act_delayed\ : STD_LOGIC;
  signal \^inhbt_act_faw.faw_cnt_r_reg[2]_0\ : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal \inhbt_act_faw.inhbt_act_faw_r_i_1_n_0\ : STD_LOGIC;
  signal \periodic_rd_generation.periodic_rd_timer_r\ : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal \periodic_rd_generation.periodic_rd_timer_r[0]_i_1_n_0\ : STD_LOGIC;
  signal \periodic_rd_generation.periodic_rd_timer_r[1]_i_1_n_0\ : STD_LOGIC;
  signal \periodic_rd_generation.periodic_rd_timer_r[2]_i_1_n_0\ : STD_LOGIC;
  signal \wtr_timer.wtr_cnt_ns\ : STD_LOGIC_VECTOR ( 1 to 1 );
  signal \^wtr_timer.wtr_cnt_r_reg[1]_0\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_inhbt_act_faw.SRLC32E0_Q31_UNCONNECTED\ : STD_LOGIC;
  attribute BOX_TYPE : string;
  attribute BOX_TYPE of \inhbt_act_faw.SRLC32E0\ : label is "PRIMITIVE";
  attribute srl_bus_name : string;
  attribute srl_bus_name of \inhbt_act_faw.SRLC32E0\ : label is "\u_mig_mig/u_memc_ui_top_std/mem_intfc0/mc0/rank_mach0/rank_cntrl ";
  attribute srl_name : string;
  attribute srl_name of \inhbt_act_faw.SRLC32E0\ : label is "\u_mig_mig/u_memc_ui_top_std/mem_intfc0/mc0/rank_mach0/rank_cntrl[0].rank_cntrl0/inhbt_act_faw.SRLC32E0 ";
begin
  \inhbt_act_faw.act_delayed\ <= \^inhbt_act_faw.act_delayed\;
  \inhbt_act_faw.faw_cnt_r_reg[2]_0\(2 downto 0) <= \^inhbt_act_faw.faw_cnt_r_reg[2]_0\(2 downto 0);
  \wtr_timer.wtr_cnt_r_reg[1]_0\(1 downto 0) <= \^wtr_timer.wtr_cnt_r_reg[1]_0\(1 downto 0);
\i___20_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0040"
    )
        port map (
      I0 => \periodic_rd_generation.periodic_rd_timer_r\(2),
      I1 => \periodic_rd_generation.periodic_rd_timer_r\(0),
      I2 => maint_prescaler_tick_r,
      I3 => \periodic_rd_generation.periodic_rd_timer_r\(1),
      O => \periodic_rd_generation.periodic_rd_timer_r_reg[2]_0\
    );
\inhbt_act_faw.SRLC32E0\: unisim.vcomponents.SRLC32E
    generic map(
      INIT => X"00000000",
      IS_CLK_INVERTED => '0'
    )
        port map (
      A(4 downto 0) => B"00000",
      CE => '1',
      CLK => \periodic_rd_generation.periodic_rd_request_r_reg_0\,
      D => act_this_rank,
      Q => \^inhbt_act_faw.act_delayed\,
      Q31 => \NLW_inhbt_act_faw.SRLC32E0_Q31_UNCONNECTED\
    );
\inhbt_act_faw.faw_cnt_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \periodic_rd_generation.periodic_rd_request_r_reg_0\,
      CE => '1',
      D => \inhbt_act_faw.faw_cnt_r_reg[2]_1\(0),
      Q => \^inhbt_act_faw.faw_cnt_r_reg[2]_0\(0),
      R => '0'
    );
\inhbt_act_faw.faw_cnt_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \periodic_rd_generation.periodic_rd_request_r_reg_0\,
      CE => '1',
      D => \inhbt_act_faw.faw_cnt_r_reg[2]_1\(1),
      Q => \^inhbt_act_faw.faw_cnt_r_reg[2]_0\(1),
      R => '0'
    );
\inhbt_act_faw.faw_cnt_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \periodic_rd_generation.periodic_rd_request_r_reg_0\,
      CE => '1',
      D => \inhbt_act_faw.faw_cnt_r_reg[2]_1\(2),
      Q => \^inhbt_act_faw.faw_cnt_r_reg[2]_0\(2),
      R => '0'
    );
\inhbt_act_faw.inhbt_act_faw_r_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0001000020000220"
    )
        port map (
      I0 => \^inhbt_act_faw.faw_cnt_r_reg[2]_0\(2),
      I1 => \inhbt_act_faw.inhbt_act_faw_r_reg_0\,
      I2 => \^inhbt_act_faw.act_delayed\,
      I3 => \inhbt_act_faw.inhbt_act_faw_r_reg_1\,
      I4 => \^inhbt_act_faw.faw_cnt_r_reg[2]_0\(0),
      I5 => \^inhbt_act_faw.faw_cnt_r_reg[2]_0\(1),
      O => \inhbt_act_faw.inhbt_act_faw_r_i_1_n_0\
    );
\inhbt_act_faw.inhbt_act_faw_r_reg\: unisim.vcomponents.FDRE
     port map (
      C => \periodic_rd_generation.periodic_rd_request_r_reg_0\,
      CE => '1',
      D => \inhbt_act_faw.inhbt_act_faw_r_i_1_n_0\,
      Q => inhbt_act_faw_r,
      R => '0'
    );
\periodic_rd_generation.periodic_rd_cntr1_r_reg\: unisim.vcomponents.FDRE
     port map (
      C => \periodic_rd_generation.periodic_rd_request_r_reg_0\,
      CE => '1',
      D => \periodic_rd_generation.periodic_rd_cntr1_r_reg_1\,
      Q => \periodic_rd_generation.periodic_rd_cntr1_r\,
      R => \periodic_rd_generation.periodic_rd_cntr1_r_reg_0\
    );
\periodic_rd_generation.periodic_rd_request_r_reg\: unisim.vcomponents.FDRE
     port map (
      C => \periodic_rd_generation.periodic_rd_request_r_reg_0\,
      CE => '1',
      D => \periodic_rd_generation.periodic_rd_request_r_reg_1\,
      Q => \periodic_rd_generation.periodic_rd_request_r\,
      R => SR(0)
    );
\periodic_rd_generation.periodic_rd_timer_r[0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"BBFFFFBBBFFBFFBB"
    )
        port map (
      I0 => \periodic_rd_generation.periodic_rd_timer_r_reg[2]_1\,
      I1 => \periodic_rd_generation.periodic_rd_timer_r_reg[2]_2\,
      I2 => \periodic_rd_generation.periodic_rd_timer_r\(2),
      I3 => \periodic_rd_generation.periodic_rd_timer_r\(0),
      I4 => maint_prescaler_tick_r,
      I5 => \periodic_rd_generation.periodic_rd_timer_r\(1),
      O => \periodic_rd_generation.periodic_rd_timer_r[0]_i_1_n_0\
    );
\periodic_rd_generation.periodic_rd_timer_r[1]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"4400444400400000"
    )
        port map (
      I0 => \periodic_rd_generation.periodic_rd_timer_r_reg[2]_1\,
      I1 => \periodic_rd_generation.periodic_rd_timer_r_reg[2]_2\,
      I2 => \periodic_rd_generation.periodic_rd_timer_r\(2),
      I3 => \periodic_rd_generation.periodic_rd_timer_r\(0),
      I4 => maint_prescaler_tick_r,
      I5 => \periodic_rd_generation.periodic_rd_timer_r\(1),
      O => \periodic_rd_generation.periodic_rd_timer_r[1]_i_1_n_0\
    );
\periodic_rd_generation.periodic_rd_timer_r[2]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FBFBFBFBFFBBFBFB"
    )
        port map (
      I0 => \periodic_rd_generation.periodic_rd_timer_r_reg[2]_1\,
      I1 => \periodic_rd_generation.periodic_rd_timer_r_reg[2]_2\,
      I2 => \periodic_rd_generation.periodic_rd_timer_r\(2),
      I3 => \periodic_rd_generation.periodic_rd_timer_r\(0),
      I4 => maint_prescaler_tick_r,
      I5 => \periodic_rd_generation.periodic_rd_timer_r\(1),
      O => \periodic_rd_generation.periodic_rd_timer_r[2]_i_1_n_0\
    );
\periodic_rd_generation.periodic_rd_timer_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \periodic_rd_generation.periodic_rd_request_r_reg_0\,
      CE => '1',
      D => \periodic_rd_generation.periodic_rd_timer_r[0]_i_1_n_0\,
      Q => \periodic_rd_generation.periodic_rd_timer_r\(0),
      R => '0'
    );
\periodic_rd_generation.periodic_rd_timer_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \periodic_rd_generation.periodic_rd_request_r_reg_0\,
      CE => '1',
      D => \periodic_rd_generation.periodic_rd_timer_r[1]_i_1_n_0\,
      Q => \periodic_rd_generation.periodic_rd_timer_r\(1),
      R => '0'
    );
\periodic_rd_generation.periodic_rd_timer_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \periodic_rd_generation.periodic_rd_request_r_reg_0\,
      CE => '1',
      D => \periodic_rd_generation.periodic_rd_timer_r[2]_i_1_n_0\,
      Q => \periodic_rd_generation.periodic_rd_timer_r\(2),
      R => '0'
    );
\periodic_rd_generation.read_this_rank_r_reg\: unisim.vcomponents.FDRE
     port map (
      C => \periodic_rd_generation.periodic_rd_request_r_reg_0\,
      CE => '1',
      D => \periodic_rd_generation.read_this_rank\,
      Q => \periodic_rd_generation.read_this_rank_r\,
      R => '0'
    );
\refresh_generation.refresh_bank_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \periodic_rd_generation.periodic_rd_request_r_reg_0\,
      CE => '1',
      D => \refresh_generation.refresh_bank_r_reg[0]_1\,
      Q => \refresh_generation.refresh_bank_r_reg[0]_0\,
      R => '0'
    );
\rtw_timer.rtw_cnt_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \periodic_rd_generation.periodic_rd_request_r_reg_0\,
      CE => '1',
      D => \rtw_timer.rtw_cnt_r_reg[1]_1\(0),
      Q => \rtw_timer.rtw_cnt_r_reg[1]_0\(0),
      R => '0'
    );
\rtw_timer.rtw_cnt_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \periodic_rd_generation.periodic_rd_request_r_reg_0\,
      CE => '1',
      D => \rtw_timer.rtw_cnt_r_reg[1]_1\(1),
      Q => \rtw_timer.rtw_cnt_r_reg[1]_0\(1),
      R => '0'
    );
\wtr_timer.wtr_cnt_r[1]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"00D5"
    )
        port map (
      I0 => \wtr_timer.wtr_cnt_r_reg[1]_1\,
      I1 => \^wtr_timer.wtr_cnt_r_reg[1]_0\(0),
      I2 => \^wtr_timer.wtr_cnt_r_reg[1]_0\(1),
      I3 => \wtr_timer.wtr_cnt_r_reg[1]_2\,
      O => \wtr_timer.wtr_cnt_ns\(1)
    );
\wtr_timer.wtr_cnt_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \periodic_rd_generation.periodic_rd_request_r_reg_0\,
      CE => '1',
      D => \wtr_timer.wtr_cnt_r_reg[0]_0\(0),
      Q => \^wtr_timer.wtr_cnt_r_reg[1]_0\(0),
      R => '0'
    );
\wtr_timer.wtr_cnt_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \periodic_rd_generation.periodic_rd_request_r_reg_0\,
      CE => '1',
      D => \wtr_timer.wtr_cnt_ns\(1),
      Q => \^wtr_timer.wtr_cnt_r_reg[1]_0\(1),
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mig_mig_7series_v4_2_round_robin_arb is
  port (
    \maintenance_request.maint_sre_ns\ : out STD_LOGIC;
    Q : out STD_LOGIC_VECTOR ( 2 downto 0 );
    \maintenance_request.maint_sre_r_lcl_reg\ : out STD_LOGIC;
    \last_master_r_reg[2]_0\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
    \maintenance_request.maint_zq_r_lcl_reg\ : out STD_LOGIC;
    \maintenance_request.maint_sre_r_lcl_reg_0\ : in STD_LOGIC;
    app_sr_req : in STD_LOGIC;
    \sr_cntrl.ckesr_timer.ckesr_timer_r\ : in STD_LOGIC;
    \last_master_r_reg[2]_1\ : in STD_LOGIC;
    \maintenance_request.maint_srx_r_lcl_reg\ : in STD_LOGIC;
    D : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \grant_r_reg[0]_0\ : in STD_LOGIC;
    \grant_r_reg[0]_1\ : in STD_LOGIC;
    \grant_r_reg[0]_2\ : in STD_LOGIC;
    \grant_r_reg[0]_3\ : in STD_LOGIC;
    \grant_r_reg[2]_0\ : in STD_LOGIC;
    \last_master_r_reg[2]_2\ : in STD_LOGIC;
    \last_master_r_reg[2]_3\ : in STD_LOGIC;
    \maintenance_request.maint_zq_r_lcl_reg_0\ : in STD_LOGIC;
    \last_master_r_reg[2]_4\ : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of mig_mig_7series_v4_2_round_robin_arb : entity is "mig_7series_v4_2_round_robin_arb";
end mig_mig_7series_v4_2_round_robin_arb;

architecture STRUCTURE of mig_mig_7series_v4_2_round_robin_arb is
  signal \^q\ : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal \grant_r[0]_i_1_n_0\ : STD_LOGIC;
  signal \grant_r[1]_i_1_n_0\ : STD_LOGIC;
  signal \grant_r[1]_i_2_n_0\ : STD_LOGIC;
  signal \grant_r[1]_i_3_n_0\ : STD_LOGIC;
  signal \grant_r[2]_i_1_n_0\ : STD_LOGIC;
  signal \last_master_r[2]_i_1_n_0\ : STD_LOGIC;
  signal \^last_master_r_reg[2]_0\ : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal \maintenance_request.maint_sre_r_lcl_i_2_n_0\ : STD_LOGIC;
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \grant_r[1]_i_2\ : label is "soft_lutpair1199";
  attribute SOFT_HLUTNM of \last_master_r[2]_i_1\ : label is "soft_lutpair1198";
  attribute SOFT_HLUTNM of \maintenance_request.maint_sre_r_lcl_i_2\ : label is "soft_lutpair1198";
  attribute SOFT_HLUTNM of \maintenance_request.maint_zq_r_lcl_i_1\ : label is "soft_lutpair1199";
begin
  Q(2 downto 0) <= \^q\(2 downto 0);
  \last_master_r_reg[2]_0\(2 downto 0) <= \^last_master_r_reg[2]_0\(2 downto 0);
\grant_r[0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000C04040C0C"
    )
        port map (
      I0 => D(1),
      I1 => \grant_r_reg[0]_0\,
      I2 => \grant_r_reg[0]_1\,
      I3 => \grant_r_reg[0]_2\,
      I4 => \grant_r_reg[0]_3\,
      I5 => D(0),
      O => \grant_r[0]_i_1_n_0\
    );
\grant_r[1]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AA80000080800000"
    )
        port map (
      I0 => \grant_r_reg[0]_2\,
      I1 => \grant_r_reg[2]_0\,
      I2 => \grant_r[1]_i_2_n_0\,
      I3 => \grant_r_reg[0]_1\,
      I4 => \grant_r_reg[0]_0\,
      I5 => \grant_r[1]_i_3_n_0\,
      O => \grant_r[1]_i_1_n_0\
    );
\grant_r[1]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"04F7"
    )
        port map (
      I0 => \^q\(1),
      I1 => \last_master_r_reg[2]_2\,
      I2 => \last_master_r_reg[2]_3\,
      I3 => \^last_master_r_reg[2]_0\(1),
      O => \grant_r[1]_i_2_n_0\
    );
\grant_r[1]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFF7F777FFF"
    )
        port map (
      I0 => \grant_r_reg[0]_3\,
      I1 => \grant_r_reg[0]_0\,
      I2 => \^q\(1),
      I3 => \maintenance_request.maint_sre_r_lcl_i_2_n_0\,
      I4 => \^last_master_r_reg[2]_0\(1),
      I5 => \last_master_r_reg[2]_1\,
      O => \grant_r[1]_i_3_n_0\
    );
\grant_r[2]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"7070300000000000"
    )
        port map (
      I0 => D(0),
      I1 => \grant_r_reg[0]_2\,
      I2 => \grant_r_reg[0]_0\,
      I3 => \grant_r_reg[0]_1\,
      I4 => \grant_r_reg[2]_0\,
      I5 => \grant_r_reg[0]_3\,
      O => \grant_r[2]_i_1_n_0\
    );
\grant_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \last_master_r_reg[2]_4\,
      CE => '1',
      D => \grant_r[0]_i_1_n_0\,
      Q => \^q\(0),
      R => '0'
    );
\grant_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \last_master_r_reg[2]_4\,
      CE => '1',
      D => \grant_r[1]_i_1_n_0\,
      Q => \^q\(1),
      R => '0'
    );
\grant_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \last_master_r_reg[2]_4\,
      CE => '1',
      D => \grant_r[2]_i_1_n_0\,
      Q => \^q\(2),
      R => '0'
    );
\last_master_r[2]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFFB08"
    )
        port map (
      I0 => \^q\(2),
      I1 => \last_master_r_reg[2]_2\,
      I2 => \last_master_r_reg[2]_3\,
      I3 => \^last_master_r_reg[2]_0\(2),
      I4 => \last_master_r_reg[2]_1\,
      O => \last_master_r[2]_i_1_n_0\
    );
\last_master_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \last_master_r_reg[2]_4\,
      CE => '1',
      D => D(0),
      Q => \^last_master_r_reg[2]_0\(0),
      R => '0'
    );
\last_master_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \last_master_r_reg[2]_4\,
      CE => '1',
      D => D(1),
      Q => \^last_master_r_reg[2]_0\(1),
      R => '0'
    );
\last_master_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \last_master_r_reg[2]_4\,
      CE => '1',
      D => \last_master_r[2]_i_1_n_0\,
      Q => \^last_master_r_reg[2]_0\(2),
      R => '0'
    );
\maintenance_request.maint_sre_r_lcl_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000FFA800A8"
    )
        port map (
      I0 => \maintenance_request.maint_sre_r_lcl_reg_0\,
      I1 => app_sr_req,
      I2 => \sr_cntrl.ckesr_timer.ckesr_timer_r\,
      I3 => \maintenance_request.maint_sre_r_lcl_i_2_n_0\,
      I4 => \^q\(2),
      I5 => \last_master_r_reg[2]_1\,
      O => \maintenance_request.maint_sre_ns\
    );
\maintenance_request.maint_sre_r_lcl_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \last_master_r_reg[2]_2\,
      I1 => \last_master_r_reg[2]_3\,
      O => \maintenance_request.maint_sre_r_lcl_i_2_n_0\
    );
\maintenance_request.maint_srx_r_lcl_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"5702575702020202"
    )
        port map (
      I0 => \maintenance_request.maint_sre_r_lcl_reg_0\,
      I1 => app_sr_req,
      I2 => \sr_cntrl.ckesr_timer.ckesr_timer_r\,
      I3 => \^q\(2),
      I4 => \maintenance_request.maint_sre_r_lcl_i_2_n_0\,
      I5 => \maintenance_request.maint_srx_r_lcl_reg\,
      O => \maintenance_request.maint_sre_r_lcl_reg\
    );
\maintenance_request.maint_zq_r_lcl_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"BA8A"
    )
        port map (
      I0 => \maintenance_request.maint_zq_r_lcl_reg_0\,
      I1 => \last_master_r_reg[2]_3\,
      I2 => \last_master_r_reg[2]_2\,
      I3 => \^q\(1),
      O => \maintenance_request.maint_zq_r_lcl_reg\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \mig_mig_7series_v4_2_round_robin_arb__parameterized1\ is
  port (
    granted_col_r_reg : out STD_LOGIC;
    \grant_r_reg[2]_0\ : out STD_LOGIC;
    \periodic_rd_generation.read_this_rank_r_reg\ : out STD_LOGIC;
    Q : out STD_LOGIC_VECTOR ( 3 downto 0 );
    \periodic_rd_generation.read_this_rank\ : out STD_LOGIC;
    DIC : out STD_LOGIC_VECTOR ( 0 to 0 );
    mc_odt_ns : out STD_LOGIC_VECTOR ( 0 to 0 );
    D : out STD_LOGIC_VECTOR ( 0 to 0 );
    granted_col_r_reg_0 : out STD_LOGIC_VECTOR ( 0 to 0 );
    granted_col_r_reg_1 : out STD_LOGIC_VECTOR ( 0 to 0 );
    E : out STD_LOGIC_VECTOR ( 0 to 0 );
    \rtw_timer.rtw_cnt_r_reg[1]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    col_rd_wr : out STD_LOGIC;
    \grant_r_reg[0]_0\ : out STD_LOGIC;
    \wr_this_rank_r_reg[0]\ : out STD_LOGIC;
    \wr_this_rank_r_reg[0]_0\ : out STD_LOGIC;
    \grant_r_reg[3]_0\ : out STD_LOGIC;
    rnk_config_valid_r_lcl_reg : out STD_LOGIC;
    rnk_config_valid_r_lcl_reg_0 : out STD_LOGIC;
    rnk_config_valid_r_lcl_reg_1 : out STD_LOGIC;
    rnk_config_valid_r_lcl_reg_2 : out STD_LOGIC;
    col_wr_data_buf_addr : out STD_LOGIC_VECTOR ( 3 downto 0 );
    granted_col_r_reg_2 : out STD_LOGIC_VECTOR ( 2 downto 0 );
    granted_col_r_reg_3 : out STD_LOGIC_VECTOR ( 10 downto 0 );
    req_bank_rdy_r_reg : out STD_LOGIC;
    \rtw_timer.rtw_cnt_r_reg[1]_0\ : out STD_LOGIC;
    \wtr_timer.wtr_cnt_r_reg[1]\ : out STD_LOGIC;
    \grant_r_reg[0]_1\ : out STD_LOGIC;
    \cmd_pipe_plus.mc_data_offset_2_reg[0]\ : in STD_LOGIC;
    \grant_r_reg[0]_2\ : in STD_LOGIC;
    \grant_r_reg[0]_3\ : in STD_LOGIC;
    \grant_r_reg[2]_1\ : in STD_LOGIC;
    \grant_r_reg[0]_4\ : in STD_LOGIC;
    \periodic_rd_generation.read_this_rank_r\ : in STD_LOGIC;
    rd_this_rank_r : in STD_LOGIC_VECTOR ( 3 downto 0 );
    req_periodic_rd_r : in STD_LOGIC_VECTOR ( 3 downto 0 );
    \rtw_timer.rtw_cnt_r_reg[0]\ : in STD_LOGIC;
    \col_mux.col_periodic_rd_r\ : in STD_LOGIC;
    \cmd_pipe_plus.mc_odt_reg[0]\ : in STD_LOGIC;
    O : in STD_LOGIC_VECTOR ( 0 to 0 );
    \cmd_pipe_plus.mc_data_offset_1_reg[3]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \cmd_pipe_plus.mc_data_offset_reg[3]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \rtw_timer.rtw_cnt_r_reg[1]_1\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \cmd_pipe_plus.mc_data_offset_2_reg[0]_0\ : in STD_LOGIC;
    \cmd_pipe_plus.mc_data_offset_2_reg[0]_1\ : in STD_LOGIC;
    \i___22_i_1_0\ : in STD_LOGIC;
    rd_wr_r : in STD_LOGIC_VECTOR ( 0 to 0 );
    col_rd_wr_r : in STD_LOGIC;
    wr_this_rank_r : in STD_LOGIC_VECTOR ( 3 downto 0 );
    \grant_r[3]_i_8\ : in STD_LOGIC;
    \grant_r[3]_i_8_0\ : in STD_LOGIC;
    \grant_r[3]_i_10\ : in STD_LOGIC;
    ofs_rdy_r : in STD_LOGIC;
    \genblk3[1].rnk_config_strobe_r_reg\ : in STD_LOGIC;
    \genblk3[2].rnk_config_strobe_r_reg\ : in STD_LOGIC;
    rnk_config_strobe : in STD_LOGIC;
    ofs_rdy_r_0 : in STD_LOGIC;
    ofs_rdy_r_1 : in STD_LOGIC;
    ofs_rdy_r_2 : in STD_LOGIC;
    \last_master_r_reg[1]_0\ : in STD_LOGIC;
    req_data_buf_addr_r : in STD_LOGIC_VECTOR ( 15 downto 0 );
    \delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
    \cmd_pipe_plus.mc_bank_reg[5]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
    \cmd_pipe_plus.mc_bank_reg[5]_0\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
    \cmd_pipe_plus.mc_bank_reg[5]_1\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
    \cmd_pipe_plus.mc_bank_reg[5]_2\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
    \cmd_pipe_plus.mc_address_reg[23]\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
    \cmd_pipe_plus.mc_address_reg[23]_0\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
    \cmd_pipe_plus.mc_address_reg[23]_1\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
    \cmd_pipe_plus.mc_address_reg[23]_2\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
    \cmd_pipe_plus.mc_address_reg[24]\ : in STD_LOGIC;
    \cmd_pipe_plus.mc_address_reg[24]_0\ : in STD_LOGIC;
    \cmd_pipe_plus.mc_address_reg[24]_1\ : in STD_LOGIC;
    \cmd_pipe_plus.mc_address_reg[24]_2\ : in STD_LOGIC;
    req_bank_rdy_r : in STD_LOGIC;
    \grant_r[2]_i_3\ : in STD_LOGIC;
    \grant_r[2]_i_3_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \last_master_r_reg[3]_0\ : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \mig_mig_7series_v4_2_round_robin_arb__parameterized1\ : entity is "mig_7series_v4_2_round_robin_arb";
end \mig_mig_7series_v4_2_round_robin_arb__parameterized1\;

architecture STRUCTURE of \mig_mig_7series_v4_2_round_robin_arb__parameterized1\ is
  signal \^q\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \cmd_pipe_plus.mc_address[14]_i_2_n_0\ : STD_LOGIC;
  signal \cmd_pipe_plus.mc_address[15]_i_2_n_0\ : STD_LOGIC;
  signal \cmd_pipe_plus.mc_address[16]_i_2_n_0\ : STD_LOGIC;
  signal \cmd_pipe_plus.mc_address[17]_i_2_n_0\ : STD_LOGIC;
  signal \cmd_pipe_plus.mc_address[18]_i_2_n_0\ : STD_LOGIC;
  signal \cmd_pipe_plus.mc_address[19]_i_2_n_0\ : STD_LOGIC;
  signal \cmd_pipe_plus.mc_address[20]_i_2_n_0\ : STD_LOGIC;
  signal \cmd_pipe_plus.mc_address[21]_i_2_n_0\ : STD_LOGIC;
  signal \cmd_pipe_plus.mc_address[22]_i_2_n_0\ : STD_LOGIC;
  signal \cmd_pipe_plus.mc_address[23]_i_2_n_0\ : STD_LOGIC;
  signal \cmd_pipe_plus.mc_address[24]_i_2_n_0\ : STD_LOGIC;
  signal \cmd_pipe_plus.mc_bank[3]_i_2_n_0\ : STD_LOGIC;
  signal \cmd_pipe_plus.mc_bank[4]_i_2_n_0\ : STD_LOGIC;
  signal \cmd_pipe_plus.mc_bank[5]_i_2_n_0\ : STD_LOGIC;
  signal \col_mux.col_periodic_rd_r_i_2_n_0\ : STD_LOGIC;
  signal \delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r[0]_i_2_n_0\ : STD_LOGIC;
  signal \delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r[1]_i_2_n_0\ : STD_LOGIC;
  signal \delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r[2]_i_2_n_0\ : STD_LOGIC;
  signal \delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r[3]_i_2_n_0\ : STD_LOGIC;
  signal \grant_r[0]_i_1__0_n_0\ : STD_LOGIC;
  signal \grant_r[1]_i_1__1_n_0\ : STD_LOGIC;
  signal \grant_r[2]_i_1__0_n_0\ : STD_LOGIC;
  signal \grant_r[2]_i_2_n_0\ : STD_LOGIC;
  signal \grant_r[3]_i_17_n_0\ : STD_LOGIC;
  signal \grant_r[3]_i_1__0_n_0\ : STD_LOGIC;
  signal \grant_r[3]_i_4_n_0\ : STD_LOGIC;
  signal \^grant_r_reg[2]_0\ : STD_LOGIC;
  signal \i___22_i_2_n_0\ : STD_LOGIC;
  signal \i___22_i_3_n_0\ : STD_LOGIC;
  signal last_master_r : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \last_master_r[0]_i_1_n_0\ : STD_LOGIC;
  signal \last_master_r[1]_i_1_n_0\ : STD_LOGIC;
  signal \last_master_r[2]_i_1__0_n_0\ : STD_LOGIC;
  signal \last_master_r[3]_i_1_n_0\ : STD_LOGIC;
  signal \periodic_rd_generation.read_this_rank_r_i_2_n_0\ : STD_LOGIC;
  signal \rtw_timer.rtw_cnt_r[1]_i_2_n_0\ : STD_LOGIC;
  signal \^wr_this_rank_r_reg[0]\ : STD_LOGIC;
  signal \^wr_this_rank_r_reg[0]_0\ : STD_LOGIC;
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \cmd_pipe_plus.mc_address[23]_i_1\ : label is "soft_lutpair1144";
  attribute SOFT_HLUTNM of \cmd_pipe_plus.mc_bank[3]_i_1\ : label is "soft_lutpair1145";
  attribute SOFT_HLUTNM of \cmd_pipe_plus.mc_cmd[1]_i_1\ : label is "soft_lutpair1144";
  attribute SOFT_HLUTNM of \cmd_pipe_plus.mc_data_offset[3]_i_1\ : label is "soft_lutpair1148";
  attribute SOFT_HLUTNM of \cmd_pipe_plus.mc_data_offset[5]_i_1\ : label is "soft_lutpair1145";
  attribute SOFT_HLUTNM of \cmd_pipe_plus.mc_data_offset_1[3]_i_1\ : label is "soft_lutpair1147";
  attribute SOFT_HLUTNM of \cmd_pipe_plus.mc_data_offset_2[3]_i_1\ : label is "soft_lutpair1147";
  attribute SOFT_HLUTNM of \cmd_pipe_plus.mc_odt[0]_i_1\ : label is "soft_lutpair1148";
  attribute SOFT_HLUTNM of \demand_priority_r_i_4__0\ : label is "soft_lutpair1146";
  attribute SOFT_HLUTNM of \i___22_i_3\ : label is "soft_lutpair1142";
  attribute SOFT_HLUTNM of \i___24_i_1\ : label is "soft_lutpair1141";
  attribute SOFT_HLUTNM of \last_master_r[1]_i_1\ : label is "soft_lutpair1146";
  attribute SOFT_HLUTNM of \rtw_timer.rtw_cnt_r[0]_i_1\ : label is "soft_lutpair1143";
  attribute SOFT_HLUTNM of \rtw_timer.rtw_cnt_r[1]_i_1\ : label is "soft_lutpair1143";
  attribute SOFT_HLUTNM of \rtw_timer.rtw_cnt_r[1]_i_2\ : label is "soft_lutpair1142";
  attribute SOFT_HLUTNM of \wtr_timer.wtr_cnt_r[1]_i_2\ : label is "soft_lutpair1141";
begin
  Q(3 downto 0) <= \^q\(3 downto 0);
  \grant_r_reg[2]_0\ <= \^grant_r_reg[2]_0\;
  \wr_this_rank_r_reg[0]\ <= \^wr_this_rank_r_reg[0]\;
  \wr_this_rank_r_reg[0]_0\ <= \^wr_this_rank_r_reg[0]_0\;
\cmd_pipe_plus.mc_address[14]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F737"
    )
        port map (
      I0 => \cmd_pipe_plus.mc_address[14]_i_2_n_0\,
      I1 => \cmd_pipe_plus.mc_data_offset_2_reg[0]\,
      I2 => \^q\(3),
      I3 => \cmd_pipe_plus.mc_address_reg[23]\(0),
      O => granted_col_r_reg_3(0)
    );
\cmd_pipe_plus.mc_address[14]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000F77FFFF0F77"
    )
        port map (
      I0 => \cmd_pipe_plus.mc_address_reg[23]_0\(0),
      I1 => \^q\(0),
      I2 => \cmd_pipe_plus.mc_address_reg[23]_1\(0),
      I3 => \^q\(1),
      I4 => \^q\(2),
      I5 => \cmd_pipe_plus.mc_address_reg[23]_2\(0),
      O => \cmd_pipe_plus.mc_address[14]_i_2_n_0\
    );
\cmd_pipe_plus.mc_address[15]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F737"
    )
        port map (
      I0 => \cmd_pipe_plus.mc_address[15]_i_2_n_0\,
      I1 => \cmd_pipe_plus.mc_data_offset_2_reg[0]\,
      I2 => \^q\(3),
      I3 => \cmd_pipe_plus.mc_address_reg[23]\(1),
      O => granted_col_r_reg_3(1)
    );
\cmd_pipe_plus.mc_address[15]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000F77FFFF0F77"
    )
        port map (
      I0 => \cmd_pipe_plus.mc_address_reg[23]_0\(1),
      I1 => \^q\(0),
      I2 => \cmd_pipe_plus.mc_address_reg[23]_1\(1),
      I3 => \^q\(1),
      I4 => \^q\(2),
      I5 => \cmd_pipe_plus.mc_address_reg[23]_2\(1),
      O => \cmd_pipe_plus.mc_address[15]_i_2_n_0\
    );
\cmd_pipe_plus.mc_address[16]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F737"
    )
        port map (
      I0 => \cmd_pipe_plus.mc_address[16]_i_2_n_0\,
      I1 => \cmd_pipe_plus.mc_data_offset_2_reg[0]\,
      I2 => \^q\(3),
      I3 => \cmd_pipe_plus.mc_address_reg[23]\(2),
      O => granted_col_r_reg_3(2)
    );
\cmd_pipe_plus.mc_address[16]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000F77FFFF0F77"
    )
        port map (
      I0 => \cmd_pipe_plus.mc_address_reg[23]_0\(2),
      I1 => \^q\(0),
      I2 => \cmd_pipe_plus.mc_address_reg[23]_1\(2),
      I3 => \^q\(1),
      I4 => \^q\(2),
      I5 => \cmd_pipe_plus.mc_address_reg[23]_2\(2),
      O => \cmd_pipe_plus.mc_address[16]_i_2_n_0\
    );
\cmd_pipe_plus.mc_address[17]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F737"
    )
        port map (
      I0 => \cmd_pipe_plus.mc_address[17]_i_2_n_0\,
      I1 => \cmd_pipe_plus.mc_data_offset_2_reg[0]\,
      I2 => \^q\(3),
      I3 => \cmd_pipe_plus.mc_address_reg[23]\(3),
      O => granted_col_r_reg_3(3)
    );
\cmd_pipe_plus.mc_address[17]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000F77FFFF0F77"
    )
        port map (
      I0 => \cmd_pipe_plus.mc_address_reg[23]_0\(3),
      I1 => \^q\(0),
      I2 => \cmd_pipe_plus.mc_address_reg[23]_1\(3),
      I3 => \^q\(1),
      I4 => \^q\(2),
      I5 => \cmd_pipe_plus.mc_address_reg[23]_2\(3),
      O => \cmd_pipe_plus.mc_address[17]_i_2_n_0\
    );
\cmd_pipe_plus.mc_address[18]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F737"
    )
        port map (
      I0 => \cmd_pipe_plus.mc_address[18]_i_2_n_0\,
      I1 => \cmd_pipe_plus.mc_data_offset_2_reg[0]\,
      I2 => \^q\(3),
      I3 => \cmd_pipe_plus.mc_address_reg[23]\(4),
      O => granted_col_r_reg_3(4)
    );
\cmd_pipe_plus.mc_address[18]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000F77FFFF0F77"
    )
        port map (
      I0 => \cmd_pipe_plus.mc_address_reg[23]_0\(4),
      I1 => \^q\(0),
      I2 => \cmd_pipe_plus.mc_address_reg[23]_1\(4),
      I3 => \^q\(1),
      I4 => \^q\(2),
      I5 => \cmd_pipe_plus.mc_address_reg[23]_2\(4),
      O => \cmd_pipe_plus.mc_address[18]_i_2_n_0\
    );
\cmd_pipe_plus.mc_address[19]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F737"
    )
        port map (
      I0 => \cmd_pipe_plus.mc_address[19]_i_2_n_0\,
      I1 => \cmd_pipe_plus.mc_data_offset_2_reg[0]\,
      I2 => \^q\(3),
      I3 => \cmd_pipe_plus.mc_address_reg[23]\(5),
      O => granted_col_r_reg_3(5)
    );
\cmd_pipe_plus.mc_address[19]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000F77FFFF0F77"
    )
        port map (
      I0 => \cmd_pipe_plus.mc_address_reg[23]_0\(5),
      I1 => \^q\(0),
      I2 => \cmd_pipe_plus.mc_address_reg[23]_1\(5),
      I3 => \^q\(1),
      I4 => \^q\(2),
      I5 => \cmd_pipe_plus.mc_address_reg[23]_2\(5),
      O => \cmd_pipe_plus.mc_address[19]_i_2_n_0\
    );
\cmd_pipe_plus.mc_address[20]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F737"
    )
        port map (
      I0 => \cmd_pipe_plus.mc_address[20]_i_2_n_0\,
      I1 => \cmd_pipe_plus.mc_data_offset_2_reg[0]\,
      I2 => \^q\(3),
      I3 => \cmd_pipe_plus.mc_address_reg[23]\(6),
      O => granted_col_r_reg_3(6)
    );
\cmd_pipe_plus.mc_address[20]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000F77FFFF0F77"
    )
        port map (
      I0 => \cmd_pipe_plus.mc_address_reg[23]_0\(6),
      I1 => \^q\(0),
      I2 => \cmd_pipe_plus.mc_address_reg[23]_1\(6),
      I3 => \^q\(1),
      I4 => \^q\(2),
      I5 => \cmd_pipe_plus.mc_address_reg[23]_2\(6),
      O => \cmd_pipe_plus.mc_address[20]_i_2_n_0\
    );
\cmd_pipe_plus.mc_address[21]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F737"
    )
        port map (
      I0 => \cmd_pipe_plus.mc_address[21]_i_2_n_0\,
      I1 => \cmd_pipe_plus.mc_data_offset_2_reg[0]\,
      I2 => \^q\(3),
      I3 => \cmd_pipe_plus.mc_address_reg[23]\(7),
      O => granted_col_r_reg_3(7)
    );
\cmd_pipe_plus.mc_address[21]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000F77FFFF0F77"
    )
        port map (
      I0 => \cmd_pipe_plus.mc_address_reg[23]_0\(7),
      I1 => \^q\(0),
      I2 => \cmd_pipe_plus.mc_address_reg[23]_1\(7),
      I3 => \^q\(1),
      I4 => \^q\(2),
      I5 => \cmd_pipe_plus.mc_address_reg[23]_2\(7),
      O => \cmd_pipe_plus.mc_address[21]_i_2_n_0\
    );
\cmd_pipe_plus.mc_address[22]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F737"
    )
        port map (
      I0 => \cmd_pipe_plus.mc_address[22]_i_2_n_0\,
      I1 => \cmd_pipe_plus.mc_data_offset_2_reg[0]\,
      I2 => \^q\(3),
      I3 => \cmd_pipe_plus.mc_address_reg[23]\(8),
      O => granted_col_r_reg_3(8)
    );
\cmd_pipe_plus.mc_address[22]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000F77FFFF0F77"
    )
        port map (
      I0 => \cmd_pipe_plus.mc_address_reg[23]_0\(8),
      I1 => \^q\(0),
      I2 => \cmd_pipe_plus.mc_address_reg[23]_1\(8),
      I3 => \^q\(1),
      I4 => \^q\(2),
      I5 => \cmd_pipe_plus.mc_address_reg[23]_2\(8),
      O => \cmd_pipe_plus.mc_address[22]_i_2_n_0\
    );
\cmd_pipe_plus.mc_address[23]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F737"
    )
        port map (
      I0 => \cmd_pipe_plus.mc_address[23]_i_2_n_0\,
      I1 => \cmd_pipe_plus.mc_data_offset_2_reg[0]\,
      I2 => \^q\(3),
      I3 => \cmd_pipe_plus.mc_address_reg[23]\(9),
      O => granted_col_r_reg_3(9)
    );
\cmd_pipe_plus.mc_address[23]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000F77FFFF0F77"
    )
        port map (
      I0 => \cmd_pipe_plus.mc_address_reg[23]_0\(9),
      I1 => \^q\(0),
      I2 => \cmd_pipe_plus.mc_address_reg[23]_1\(9),
      I3 => \^q\(1),
      I4 => \^q\(2),
      I5 => \cmd_pipe_plus.mc_address_reg[23]_2\(9),
      O => \cmd_pipe_plus.mc_address[23]_i_2_n_0\
    );
\cmd_pipe_plus.mc_address[24]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F737"
    )
        port map (
      I0 => \cmd_pipe_plus.mc_address[24]_i_2_n_0\,
      I1 => \cmd_pipe_plus.mc_data_offset_2_reg[0]\,
      I2 => \^q\(3),
      I3 => \cmd_pipe_plus.mc_address_reg[24]\,
      O => granted_col_r_reg_3(10)
    );
\cmd_pipe_plus.mc_address[24]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000F77FFFF0F77"
    )
        port map (
      I0 => \cmd_pipe_plus.mc_address_reg[24]_0\,
      I1 => \^q\(0),
      I2 => \cmd_pipe_plus.mc_address_reg[24]_1\,
      I3 => \^q\(1),
      I4 => \^q\(2),
      I5 => \cmd_pipe_plus.mc_address_reg[24]_2\,
      O => \cmd_pipe_plus.mc_address[24]_i_2_n_0\
    );
\cmd_pipe_plus.mc_bank[3]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F737"
    )
        port map (
      I0 => \cmd_pipe_plus.mc_bank[3]_i_2_n_0\,
      I1 => \cmd_pipe_plus.mc_data_offset_2_reg[0]\,
      I2 => \^q\(3),
      I3 => \cmd_pipe_plus.mc_bank_reg[5]\(0),
      O => granted_col_r_reg_2(0)
    );
\cmd_pipe_plus.mc_bank[3]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000F77FFFF0F77"
    )
        port map (
      I0 => \cmd_pipe_plus.mc_bank_reg[5]_0\(0),
      I1 => \^q\(0),
      I2 => \cmd_pipe_plus.mc_bank_reg[5]_1\(0),
      I3 => \^q\(1),
      I4 => \^q\(2),
      I5 => \cmd_pipe_plus.mc_bank_reg[5]_2\(0),
      O => \cmd_pipe_plus.mc_bank[3]_i_2_n_0\
    );
\cmd_pipe_plus.mc_bank[4]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F737"
    )
        port map (
      I0 => \cmd_pipe_plus.mc_bank[4]_i_2_n_0\,
      I1 => \cmd_pipe_plus.mc_data_offset_2_reg[0]\,
      I2 => \^q\(3),
      I3 => \cmd_pipe_plus.mc_bank_reg[5]\(1),
      O => granted_col_r_reg_2(1)
    );
\cmd_pipe_plus.mc_bank[4]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000F77FFFF0F77"
    )
        port map (
      I0 => \cmd_pipe_plus.mc_bank_reg[5]_0\(1),
      I1 => \^q\(0),
      I2 => \cmd_pipe_plus.mc_bank_reg[5]_1\(1),
      I3 => \^q\(1),
      I4 => \^q\(2),
      I5 => \cmd_pipe_plus.mc_bank_reg[5]_2\(1),
      O => \cmd_pipe_plus.mc_bank[4]_i_2_n_0\
    );
\cmd_pipe_plus.mc_bank[5]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F737"
    )
        port map (
      I0 => \cmd_pipe_plus.mc_bank[5]_i_2_n_0\,
      I1 => \cmd_pipe_plus.mc_data_offset_2_reg[0]\,
      I2 => \^q\(3),
      I3 => \cmd_pipe_plus.mc_bank_reg[5]\(2),
      O => granted_col_r_reg_2(2)
    );
\cmd_pipe_plus.mc_bank[5]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000F77FFFF0F77"
    )
        port map (
      I0 => \cmd_pipe_plus.mc_bank_reg[5]_0\(2),
      I1 => \^q\(0),
      I2 => \cmd_pipe_plus.mc_bank_reg[5]_1\(2),
      I3 => \^q\(1),
      I4 => \^q\(2),
      I5 => \cmd_pipe_plus.mc_bank_reg[5]_2\(2),
      O => \cmd_pipe_plus.mc_bank[5]_i_2_n_0\
    );
\cmd_pipe_plus.mc_cmd[1]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \cmd_pipe_plus.mc_data_offset_2_reg[0]\,
      I1 => \^grant_r_reg[2]_0\,
      O => E(0)
    );
\cmd_pipe_plus.mc_data_offset[3]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"A8"
    )
        port map (
      I0 => \cmd_pipe_plus.mc_data_offset_2_reg[0]\,
      I1 => \^grant_r_reg[2]_0\,
      I2 => \cmd_pipe_plus.mc_data_offset_reg[3]\(0),
      O => granted_col_r_reg_1(0)
    );
\cmd_pipe_plus.mc_data_offset[5]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"D"
    )
        port map (
      I0 => \cmd_pipe_plus.mc_data_offset_2_reg[0]\,
      I1 => \^grant_r_reg[2]_0\,
      O => granted_col_r_reg
    );
\cmd_pipe_plus.mc_data_offset_1[3]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"A8"
    )
        port map (
      I0 => \cmd_pipe_plus.mc_data_offset_2_reg[0]\,
      I1 => \^grant_r_reg[2]_0\,
      I2 => \cmd_pipe_plus.mc_data_offset_1_reg[3]\(0),
      O => granted_col_r_reg_0(0)
    );
\cmd_pipe_plus.mc_data_offset_2[3]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"A8"
    )
        port map (
      I0 => \cmd_pipe_plus.mc_data_offset_2_reg[0]\,
      I1 => \^grant_r_reg[2]_0\,
      I2 => O(0),
      O => D(0)
    );
\cmd_pipe_plus.mc_odt[0]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"EA"
    )
        port map (
      I0 => \cmd_pipe_plus.mc_odt_reg[0]\,
      I1 => \cmd_pipe_plus.mc_data_offset_2_reg[0]\,
      I2 => \^grant_r_reg[2]_0\,
      O => mc_odt_ns(0)
    );
\cmd_pipe_plus.mc_we_n[1]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"55555554FFFFFFFF"
    )
        port map (
      I0 => \^grant_r_reg[2]_0\,
      I1 => \^q\(0),
      I2 => \^q\(1),
      I3 => \^q\(2),
      I4 => \^q\(3),
      I5 => \cmd_pipe_plus.mc_data_offset_2_reg[0]\,
      O => \grant_r_reg[0]_1\
    );
\col_mux.col_periodic_rd_r_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFCA00CA"
    )
        port map (
      I0 => \col_mux.col_periodic_rd_r_i_2_n_0\,
      I1 => req_periodic_rd_r(2),
      I2 => \^q\(2),
      I3 => \^q\(3),
      I4 => req_periodic_rd_r(3),
      O => DIC(0)
    );
\col_mux.col_periodic_rd_r_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAFF00AAAA3030"
    )
        port map (
      I0 => req_periodic_rd_r(1),
      I1 => \rtw_timer.rtw_cnt_r_reg[0]\,
      I2 => \col_mux.col_periodic_rd_r\,
      I3 => req_periodic_rd_r(0),
      I4 => \^q\(1),
      I5 => \^q\(0),
      O => \col_mux.col_periodic_rd_r_i_2_n_0\
    );
\col_mux.col_rd_wr_r_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \^grant_r_reg[2]_0\,
      O => col_rd_wr
    );
\delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r[0]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8BBB888"
    )
        port map (
      I0 => req_data_buf_addr_r(12),
      I1 => \^q\(3),
      I2 => req_data_buf_addr_r(8),
      I3 => \^q\(2),
      I4 => \delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r[0]_i_2_n_0\,
      O => col_wr_data_buf_addr(0)
    );
\delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r[0]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8BBB888"
    )
        port map (
      I0 => req_data_buf_addr_r(4),
      I1 => \^q\(1),
      I2 => req_data_buf_addr_r(0),
      I3 => \^q\(0),
      I4 => \delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r_reg[3]\(0),
      O => \delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r[0]_i_2_n_0\
    );
\delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r[1]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8BBB888"
    )
        port map (
      I0 => req_data_buf_addr_r(13),
      I1 => \^q\(3),
      I2 => req_data_buf_addr_r(9),
      I3 => \^q\(2),
      I4 => \delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r[1]_i_2_n_0\,
      O => col_wr_data_buf_addr(1)
    );
\delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r[1]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8BBB888"
    )
        port map (
      I0 => req_data_buf_addr_r(5),
      I1 => \^q\(1),
      I2 => req_data_buf_addr_r(1),
      I3 => \^q\(0),
      I4 => \delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r_reg[3]\(1),
      O => \delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r[1]_i_2_n_0\
    );
\delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r[2]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8BBB888"
    )
        port map (
      I0 => req_data_buf_addr_r(14),
      I1 => \^q\(3),
      I2 => req_data_buf_addr_r(10),
      I3 => \^q\(2),
      I4 => \delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r[2]_i_2_n_0\,
      O => col_wr_data_buf_addr(2)
    );
\delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r[2]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8BBB888"
    )
        port map (
      I0 => req_data_buf_addr_r(6),
      I1 => \^q\(1),
      I2 => req_data_buf_addr_r(2),
      I3 => \^q\(0),
      I4 => \delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r_reg[3]\(2),
      O => \delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r[2]_i_2_n_0\
    );
\delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r[3]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8BBB888"
    )
        port map (
      I0 => req_data_buf_addr_r(15),
      I1 => \^q\(3),
      I2 => req_data_buf_addr_r(11),
      I3 => \^q\(2),
      I4 => \delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r[3]_i_2_n_0\,
      O => col_wr_data_buf_addr(3)
    );
\delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r[3]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8BBB888"
    )
        port map (
      I0 => req_data_buf_addr_r(7),
      I1 => \^q\(1),
      I2 => req_data_buf_addr_r(3),
      I3 => \^q\(0),
      I4 => \delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r_reg[3]\(3),
      O => \delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r[3]_i_2_n_0\
    );
\demand_priority_r_i_4__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"DF"
    )
        port map (
      I0 => req_bank_rdy_r,
      I1 => \^q\(1),
      I2 => \cmd_pipe_plus.mc_data_offset_2_reg[0]\,
      O => req_bank_rdy_r_reg
    );
\grant_r[0]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000AA020202"
    )
        port map (
      I0 => \grant_r[2]_i_2_n_0\,
      I1 => \last_master_r[0]_i_1_n_0\,
      I2 => \last_master_r[1]_i_1_n_0\,
      I3 => \grant_r_reg[0]_2\,
      I4 => \grant_r_reg[0]_4\,
      I5 => \grant_r_reg[0]_3\,
      O => \grant_r[0]_i_1__0_n_0\
    );
\grant_r[1]_i_1__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"800080008000F000"
    )
        port map (
      I0 => \grant_r_reg[0]_2\,
      I1 => \grant_r_reg[0]_3\,
      I2 => \grant_r[3]_i_4_n_0\,
      I3 => \grant_r_reg[2]_1\,
      I4 => \last_master_r[2]_i_1__0_n_0\,
      I5 => \last_master_r[1]_i_1_n_0\,
      O => \grant_r[1]_i_1__1_n_0\
    );
\grant_r[2]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000080808AA"
    )
        port map (
      I0 => \grant_r[2]_i_2_n_0\,
      I1 => \grant_r_reg[0]_3\,
      I2 => \grant_r_reg[2]_1\,
      I3 => \last_master_r[2]_i_1__0_n_0\,
      I4 => \last_master_r[3]_i_1_n_0\,
      I5 => \grant_r_reg[0]_4\,
      O => \grant_r[2]_i_1__0_n_0\
    );
\grant_r[2]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7077"
    )
        port map (
      I0 => \grant_r_reg[2]_1\,
      I1 => \last_master_r[0]_i_1_n_0\,
      I2 => \grant_r_reg[0]_2\,
      I3 => \last_master_r[2]_i_1__0_n_0\,
      O => \grant_r[2]_i_2_n_0\
    );
\grant_r[2]_i_7\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFFDF"
    )
        port map (
      I0 => \grant_r[3]_i_10\,
      I1 => \^q\(0),
      I2 => ofs_rdy_r_0,
      I3 => \genblk3[1].rnk_config_strobe_r_reg\,
      I4 => \genblk3[2].rnk_config_strobe_r_reg\,
      I5 => rnk_config_strobe,
      O => rnk_config_valid_r_lcl_reg_0
    );
\grant_r[3]_i_14\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"2A2AFF2AFF2AFF2A"
    )
        port map (
      I0 => \^q\(3),
      I1 => \cmd_pipe_plus.mc_data_offset_2_reg[0]_1\,
      I2 => \grant_r[3]_i_8\,
      I3 => \^q\(2),
      I4 => \cmd_pipe_plus.mc_data_offset_2_reg[0]_0\,
      I5 => \grant_r[3]_i_8_0\,
      O => \grant_r_reg[3]_0\
    );
\grant_r[3]_i_16\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFFDF"
    )
        port map (
      I0 => \grant_r[3]_i_10\,
      I1 => \^q\(1),
      I2 => ofs_rdy_r_2,
      I3 => \genblk3[1].rnk_config_strobe_r_reg\,
      I4 => \genblk3[2].rnk_config_strobe_r_reg\,
      I5 => rnk_config_strobe,
      O => rnk_config_valid_r_lcl_reg_2
    );
\grant_r[3]_i_17\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F808"
    )
        port map (
      I0 => \^q\(2),
      I1 => \cmd_pipe_plus.mc_data_offset_2_reg[0]_0\,
      I2 => \^q\(3),
      I3 => \cmd_pipe_plus.mc_data_offset_2_reg[0]_1\,
      O => \grant_r[3]_i_17_n_0\
    );
\grant_r[3]_i_18\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFFDF"
    )
        port map (
      I0 => \grant_r[3]_i_10\,
      I1 => \^q\(2),
      I2 => ofs_rdy_r,
      I3 => \genblk3[1].rnk_config_strobe_r_reg\,
      I4 => \genblk3[2].rnk_config_strobe_r_reg\,
      I5 => rnk_config_strobe,
      O => rnk_config_valid_r_lcl_reg
    );
\grant_r[3]_i_19\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFFDF"
    )
        port map (
      I0 => \grant_r[3]_i_10\,
      I1 => \^q\(3),
      I2 => ofs_rdy_r_1,
      I3 => \genblk3[1].rnk_config_strobe_r_reg\,
      I4 => \genblk3[2].rnk_config_strobe_r_reg\,
      I5 => rnk_config_strobe,
      O => rnk_config_valid_r_lcl_reg_1
    );
\grant_r[3]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000444F0000"
    )
        port map (
      I0 => \grant_r_reg[2]_1\,
      I1 => \grant_r_reg[0]_4\,
      I2 => \last_master_r[0]_i_1_n_0\,
      I3 => \last_master_r[3]_i_1_n_0\,
      I4 => \grant_r[3]_i_4_n_0\,
      I5 => \grant_r_reg[0]_2\,
      O => \grant_r[3]_i_1__0_n_0\
    );
\grant_r[3]_i_4\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"D0DD"
    )
        port map (
      I0 => \last_master_r[3]_i_1_n_0\,
      I1 => \grant_r_reg[0]_3\,
      I2 => \grant_r_reg[0]_4\,
      I3 => \last_master_r[1]_i_1_n_0\,
      O => \grant_r[3]_i_4_n_0\
    );
\grant_r[3]_i_7\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FF04"
    )
        port map (
      I0 => \^wr_this_rank_r_reg[0]\,
      I1 => \^wr_this_rank_r_reg[0]_0\,
      I2 => \grant_r[2]_i_3_0\(0),
      I3 => \grant_r[2]_i_3\,
      O => \wtr_timer.wtr_cnt_r_reg[1]\
    );
\grant_r[3]_i_9\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FF00FF4F"
    )
        port map (
      I0 => \grant_r[3]_i_17_n_0\,
      I1 => \i___22_i_2_n_0\,
      I2 => \rtw_timer.rtw_cnt_r[1]_i_2_n_0\,
      I3 => \grant_r[2]_i_3\,
      I4 => \rtw_timer.rtw_cnt_r_reg[1]_1\(1),
      O => \rtw_timer.rtw_cnt_r_reg[1]_0\
    );
\grant_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \last_master_r_reg[3]_0\,
      CE => '1',
      D => \grant_r[0]_i_1__0_n_0\,
      Q => \^q\(0),
      R => '0'
    );
\grant_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \last_master_r_reg[3]_0\,
      CE => '1',
      D => \grant_r[1]_i_1__1_n_0\,
      Q => \^q\(1),
      R => '0'
    );
\grant_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \last_master_r_reg[3]_0\,
      CE => '1',
      D => \grant_r[2]_i_1__0_n_0\,
      Q => \^q\(2),
      R => '0'
    );
\grant_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => \last_master_r_reg[3]_0\,
      CE => '1',
      D => \grant_r[3]_i_1__0_n_0\,
      Q => \^q\(3),
      R => '0'
    );
\i___20_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAA888A888A888"
    )
        port map (
      I0 => \periodic_rd_generation.read_this_rank_r\,
      I1 => \periodic_rd_generation.read_this_rank_r_i_2_n_0\,
      I2 => rd_this_rank_r(3),
      I3 => \^q\(3),
      I4 => rd_this_rank_r(0),
      I5 => \^q\(0),
      O => \periodic_rd_generation.read_this_rank_r_reg\
    );
\i___22_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000022222220222"
    )
        port map (
      I0 => \i___22_i_2_n_0\,
      I1 => \i___22_i_3_n_0\,
      I2 => \^q\(2),
      I3 => \cmd_pipe_plus.mc_data_offset_2_reg[0]_0\,
      I4 => \^q\(3),
      I5 => \cmd_pipe_plus.mc_data_offset_2_reg[0]_1\,
      O => \^grant_r_reg[2]_0\
    );
\i___22_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"EFEEEFFFEFFFEFFF"
    )
        port map (
      I0 => \^q\(3),
      I1 => \^q\(2),
      I2 => \i___22_i_1_0\,
      I3 => \^q\(1),
      I4 => rd_wr_r(0),
      I5 => \^q\(0),
      O => \i___22_i_2_n_0\
    );
\i___22_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000002"
    )
        port map (
      I0 => col_rd_wr_r,
      I1 => \^q\(0),
      I2 => \^q\(1),
      I3 => \^q\(2),
      I4 => \^q\(3),
      O => \i___22_i_3_n_0\
    );
\i___24_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0777"
    )
        port map (
      I0 => wr_this_rank_r(3),
      I1 => \^q\(3),
      I2 => wr_this_rank_r(0),
      I3 => \^q\(0),
      O => \^wr_this_rank_r_reg[0]_0\
    );
\i___24_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F888"
    )
        port map (
      I0 => wr_this_rank_r(1),
      I1 => \^q\(1),
      I2 => wr_this_rank_r(2),
      I3 => \^q\(2),
      O => \^wr_this_rank_r_reg[0]\
    );
\last_master_r[0]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"00E2"
    )
        port map (
      I0 => last_master_r(0),
      I1 => \cmd_pipe_plus.mc_data_offset_2_reg[0]\,
      I2 => \^q\(0),
      I3 => \last_master_r_reg[1]_0\,
      O => \last_master_r[0]_i_1_n_0\
    );
\last_master_r[1]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"00E2"
    )
        port map (
      I0 => last_master_r(1),
      I1 => \cmd_pipe_plus.mc_data_offset_2_reg[0]\,
      I2 => \^q\(1),
      I3 => \last_master_r_reg[1]_0\,
      O => \last_master_r[1]_i_1_n_0\
    );
\last_master_r[2]_i_1__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"00E2"
    )
        port map (
      I0 => last_master_r(2),
      I1 => \cmd_pipe_plus.mc_data_offset_2_reg[0]\,
      I2 => \^q\(2),
      I3 => \last_master_r_reg[1]_0\,
      O => \last_master_r[2]_i_1__0_n_0\
    );
\last_master_r[3]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FEAE"
    )
        port map (
      I0 => \last_master_r_reg[1]_0\,
      I1 => last_master_r(3),
      I2 => \cmd_pipe_plus.mc_data_offset_2_reg[0]\,
      I3 => \^q\(3),
      O => \last_master_r[3]_i_1_n_0\
    );
\last_master_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \last_master_r_reg[3]_0\,
      CE => '1',
      D => \last_master_r[0]_i_1_n_0\,
      Q => last_master_r(0),
      R => '0'
    );
\last_master_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \last_master_r_reg[3]_0\,
      CE => '1',
      D => \last_master_r[1]_i_1_n_0\,
      Q => last_master_r(1),
      R => '0'
    );
\last_master_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \last_master_r_reg[3]_0\,
      CE => '1',
      D => \last_master_r[2]_i_1__0_n_0\,
      Q => last_master_r(2),
      R => '0'
    );
\last_master_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => \last_master_r_reg[3]_0\,
      CE => '1',
      D => \last_master_r[3]_i_1_n_0\,
      Q => last_master_r(3),
      R => '0'
    );
\periodic_rd_generation.read_this_rank_r_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFEAEAEA"
    )
        port map (
      I0 => \periodic_rd_generation.read_this_rank_r_i_2_n_0\,
      I1 => rd_this_rank_r(3),
      I2 => \^q\(3),
      I3 => rd_this_rank_r(0),
      I4 => \^q\(0),
      O => \periodic_rd_generation.read_this_rank\
    );
\periodic_rd_generation.read_this_rank_r_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F888"
    )
        port map (
      I0 => rd_this_rank_r(1),
      I1 => \^q\(1),
      I2 => rd_this_rank_r(2),
      I3 => \^q\(2),
      O => \periodic_rd_generation.read_this_rank_r_i_2_n_0\
    );
\rtw_timer.rtw_cnt_r[0]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"000000D0"
    )
        port map (
      I0 => \rtw_timer.rtw_cnt_r[1]_i_2_n_0\,
      I1 => \^grant_r_reg[2]_0\,
      I2 => \rtw_timer.rtw_cnt_r_reg[1]_1\(1),
      I3 => \rtw_timer.rtw_cnt_r_reg[0]\,
      I4 => \rtw_timer.rtw_cnt_r_reg[1]_1\(0),
      O => \rtw_timer.rtw_cnt_r_reg[1]\(0)
    );
\rtw_timer.rtw_cnt_r[1]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00F40044"
    )
        port map (
      I0 => \^grant_r_reg[2]_0\,
      I1 => \rtw_timer.rtw_cnt_r[1]_i_2_n_0\,
      I2 => \rtw_timer.rtw_cnt_r_reg[1]_1\(1),
      I3 => \rtw_timer.rtw_cnt_r_reg[0]\,
      I4 => \rtw_timer.rtw_cnt_r_reg[1]_1\(0),
      O => \rtw_timer.rtw_cnt_r_reg[1]\(1)
    );
\rtw_timer.rtw_cnt_r[1]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFFE"
    )
        port map (
      I0 => \^q\(3),
      I1 => \^q\(2),
      I2 => \^q\(1),
      I3 => \^q\(0),
      O => \rtw_timer.rtw_cnt_r[1]_i_2_n_0\
    );
\wtr_timer.wtr_cnt_r[1]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000777"
    )
        port map (
      I0 => \^q\(0),
      I1 => wr_this_rank_r(0),
      I2 => \^q\(3),
      I3 => wr_this_rank_r(3),
      I4 => \^wr_this_rank_r_reg[0]\,
      O => \grant_r_reg[0]_0\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \mig_mig_7series_v4_2_round_robin_arb__parameterized1_3\ is
  port (
    Q : out STD_LOGIC_VECTOR ( 3 downto 0 );
    \last_master_r_reg[3]_0\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    \pre_4_1_1T_arb.granted_pre_r_reg\ : out STD_LOGIC_VECTOR ( 13 downto 0 );
    \pre_4_1_1T_arb.granted_pre_r_reg_0\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
    mc_cas_n_ns : out STD_LOGIC_VECTOR ( 0 to 0 );
    mc_we_n_ns : out STD_LOGIC_VECTOR ( 0 to 0 );
    \grant_r_reg[0]_0\ : in STD_LOGIC;
    \grant_r_reg[0]_1\ : in STD_LOGIC;
    \grant_r_reg[0]_2\ : in STD_LOGIC;
    \grant_r_reg[1]_0\ : in STD_LOGIC;
    \grant_r_reg[3]_0\ : in STD_LOGIC;
    \cmd_pipe_plus.mc_address_reg[41]\ : in STD_LOGIC;
    \last_master_r_reg[1]_0\ : in STD_LOGIC;
    \cmd_pipe_plus.mc_address_reg[38]\ : in STD_LOGIC;
    req_row_r : in STD_LOGIC_VECTOR ( 34 downto 0 );
    \cmd_pipe_plus.mc_we_n_reg[2]\ : in STD_LOGIC;
    \cmd_pipe_plus.mc_we_n_reg[2]_0\ : in STD_LOGIC;
    \cmd_pipe_plus.mc_bank_reg[8]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
    \cmd_pipe_plus.mc_bank_reg[8]_0\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
    \cmd_pipe_plus.mc_bank_reg[8]_1\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
    \cmd_pipe_plus.mc_bank_reg[8]_2\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
    \cmd_pipe_plus.mc_we_n_reg[2]_1\ : in STD_LOGIC;
    \cmd_pipe_plus.mc_we_n_reg[2]_2\ : in STD_LOGIC;
    \cmd_pipe_plus.mc_address_reg[41]_0\ : in STD_LOGIC_VECTOR ( 18 downto 0 );
    \last_master_r_reg[3]_1\ : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \mig_mig_7series_v4_2_round_robin_arb__parameterized1_3\ : entity is "mig_7series_v4_2_round_robin_arb";
end \mig_mig_7series_v4_2_round_robin_arb__parameterized1_3\;

architecture STRUCTURE of \mig_mig_7series_v4_2_round_robin_arb__parameterized1_3\ is
  signal \^q\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \cmd_pipe_plus.mc_address[28]_i_2_n_0\ : STD_LOGIC;
  signal \cmd_pipe_plus.mc_address[29]_i_2_n_0\ : STD_LOGIC;
  signal \cmd_pipe_plus.mc_address[30]_i_2_n_0\ : STD_LOGIC;
  signal \cmd_pipe_plus.mc_address[31]_i_2_n_0\ : STD_LOGIC;
  signal \cmd_pipe_plus.mc_address[32]_i_2_n_0\ : STD_LOGIC;
  signal \cmd_pipe_plus.mc_address[33]_i_2_n_0\ : STD_LOGIC;
  signal \cmd_pipe_plus.mc_address[34]_i_2_n_0\ : STD_LOGIC;
  signal \cmd_pipe_plus.mc_address[35]_i_2_n_0\ : STD_LOGIC;
  signal \cmd_pipe_plus.mc_address[36]_i_2_n_0\ : STD_LOGIC;
  signal \cmd_pipe_plus.mc_address[37]_i_2_n_0\ : STD_LOGIC;
  signal \cmd_pipe_plus.mc_address[38]_i_2_n_0\ : STD_LOGIC;
  signal \cmd_pipe_plus.mc_address[39]_i_2_n_0\ : STD_LOGIC;
  signal \cmd_pipe_plus.mc_address[40]_i_2_n_0\ : STD_LOGIC;
  signal \cmd_pipe_plus.mc_address[41]_i_2_n_0\ : STD_LOGIC;
  signal \cmd_pipe_plus.mc_bank[6]_i_2_n_0\ : STD_LOGIC;
  signal \cmd_pipe_plus.mc_bank[7]_i_2_n_0\ : STD_LOGIC;
  signal \cmd_pipe_plus.mc_bank[8]_i_2_n_0\ : STD_LOGIC;
  signal \cmd_pipe_plus.mc_we_n[2]_i_2_n_0\ : STD_LOGIC;
  signal \grant_r[0]_i_1__2_n_0\ : STD_LOGIC;
  signal \grant_r[1]_i_1__0_n_0\ : STD_LOGIC;
  signal \grant_r[2]_i_1__2_n_0\ : STD_LOGIC;
  signal \grant_r[2]_i_2__1_n_0\ : STD_LOGIC;
  signal \grant_r[3]_i_1_n_0\ : STD_LOGIC;
  signal \grant_r[3]_i_4__0_n_0\ : STD_LOGIC;
  signal last_master_r : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal \last_master_r[0]_i_1__0_n_0\ : STD_LOGIC;
  signal \last_master_r[1]_i_1__0_n_0\ : STD_LOGIC;
  signal \last_master_r[2]_i_1__1_n_0\ : STD_LOGIC;
  signal \last_master_r[3]_i_1__0_n_0\ : STD_LOGIC;
  signal \^last_master_r_reg[3]_0\ : STD_LOGIC_VECTOR ( 0 to 0 );
begin
  Q(3 downto 0) <= \^q\(3 downto 0);
  \last_master_r_reg[3]_0\(0) <= \^last_master_r_reg[3]_0\(0);
\cmd_pipe_plus.mc_address[28]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F377"
    )
        port map (
      I0 => \cmd_pipe_plus.mc_address[28]_i_2_n_0\,
      I1 => \cmd_pipe_plus.mc_address_reg[41]\,
      I2 => req_row_r(23),
      I3 => \^q\(3),
      O => \pre_4_1_1T_arb.granted_pre_r_reg\(0)
    );
\cmd_pipe_plus.mc_address[28]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"000007F7FFFF07F7"
    )
        port map (
      I0 => \cmd_pipe_plus.mc_address_reg[41]_0\(0),
      I1 => \^q\(0),
      I2 => \^q\(1),
      I3 => req_row_r(3),
      I4 => \^q\(2),
      I5 => req_row_r(12),
      O => \cmd_pipe_plus.mc_address[28]_i_2_n_0\
    );
\cmd_pipe_plus.mc_address[29]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F377"
    )
        port map (
      I0 => \cmd_pipe_plus.mc_address[29]_i_2_n_0\,
      I1 => \cmd_pipe_plus.mc_address_reg[41]\,
      I2 => req_row_r(24),
      I3 => \^q\(3),
      O => \pre_4_1_1T_arb.granted_pre_r_reg\(1)
    );
\cmd_pipe_plus.mc_address[29]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"000007F7FFFF07F7"
    )
        port map (
      I0 => \cmd_pipe_plus.mc_address_reg[41]_0\(1),
      I1 => \^q\(0),
      I2 => \^q\(1),
      I3 => req_row_r(4),
      I4 => \^q\(2),
      I5 => req_row_r(13),
      O => \cmd_pipe_plus.mc_address[29]_i_2_n_0\
    );
\cmd_pipe_plus.mc_address[30]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F377"
    )
        port map (
      I0 => \cmd_pipe_plus.mc_address[30]_i_2_n_0\,
      I1 => \cmd_pipe_plus.mc_address_reg[41]\,
      I2 => req_row_r(25),
      I3 => \^q\(3),
      O => \pre_4_1_1T_arb.granted_pre_r_reg\(2)
    );
\cmd_pipe_plus.mc_address[30]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"000007F7FFFF07F7"
    )
        port map (
      I0 => \cmd_pipe_plus.mc_address_reg[41]_0\(2),
      I1 => \^q\(0),
      I2 => \^q\(1),
      I3 => req_row_r(5),
      I4 => \^q\(2),
      I5 => req_row_r(14),
      O => \cmd_pipe_plus.mc_address[30]_i_2_n_0\
    );
\cmd_pipe_plus.mc_address[31]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F377"
    )
        port map (
      I0 => \cmd_pipe_plus.mc_address[31]_i_2_n_0\,
      I1 => \cmd_pipe_plus.mc_address_reg[41]\,
      I2 => req_row_r(26),
      I3 => \^q\(3),
      O => \pre_4_1_1T_arb.granted_pre_r_reg\(3)
    );
\cmd_pipe_plus.mc_address[31]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"000007F7FFFF07F7"
    )
        port map (
      I0 => \cmd_pipe_plus.mc_address_reg[41]_0\(3),
      I1 => \^q\(0),
      I2 => \^q\(1),
      I3 => req_row_r(6),
      I4 => \^q\(2),
      I5 => req_row_r(15),
      O => \cmd_pipe_plus.mc_address[31]_i_2_n_0\
    );
\cmd_pipe_plus.mc_address[32]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F377"
    )
        port map (
      I0 => \cmd_pipe_plus.mc_address[32]_i_2_n_0\,
      I1 => \cmd_pipe_plus.mc_address_reg[41]\,
      I2 => req_row_r(27),
      I3 => \^q\(3),
      O => \pre_4_1_1T_arb.granted_pre_r_reg\(4)
    );
\cmd_pipe_plus.mc_address[32]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"000007F7FFFF07F7"
    )
        port map (
      I0 => \cmd_pipe_plus.mc_address_reg[41]_0\(4),
      I1 => \^q\(0),
      I2 => \^q\(1),
      I3 => req_row_r(7),
      I4 => \^q\(2),
      I5 => req_row_r(16),
      O => \cmd_pipe_plus.mc_address[32]_i_2_n_0\
    );
\cmd_pipe_plus.mc_address[33]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F377"
    )
        port map (
      I0 => \cmd_pipe_plus.mc_address[33]_i_2_n_0\,
      I1 => \cmd_pipe_plus.mc_address_reg[41]\,
      I2 => req_row_r(28),
      I3 => \^q\(3),
      O => \pre_4_1_1T_arb.granted_pre_r_reg\(5)
    );
\cmd_pipe_plus.mc_address[33]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"000007F7FFFF07F7"
    )
        port map (
      I0 => \cmd_pipe_plus.mc_address_reg[41]_0\(5),
      I1 => \^q\(0),
      I2 => \^q\(1),
      I3 => req_row_r(8),
      I4 => \^q\(2),
      I5 => req_row_r(17),
      O => \cmd_pipe_plus.mc_address[33]_i_2_n_0\
    );
\cmd_pipe_plus.mc_address[34]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F377"
    )
        port map (
      I0 => \cmd_pipe_plus.mc_address[34]_i_2_n_0\,
      I1 => \cmd_pipe_plus.mc_address_reg[41]\,
      I2 => req_row_r(29),
      I3 => \^q\(3),
      O => \pre_4_1_1T_arb.granted_pre_r_reg\(6)
    );
\cmd_pipe_plus.mc_address[34]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"000007F7FFFF07F7"
    )
        port map (
      I0 => \cmd_pipe_plus.mc_address_reg[41]_0\(6),
      I1 => \^q\(0),
      I2 => \^q\(1),
      I3 => req_row_r(9),
      I4 => \^q\(2),
      I5 => req_row_r(18),
      O => \cmd_pipe_plus.mc_address[34]_i_2_n_0\
    );
\cmd_pipe_plus.mc_address[35]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F377"
    )
        port map (
      I0 => \cmd_pipe_plus.mc_address[35]_i_2_n_0\,
      I1 => \cmd_pipe_plus.mc_address_reg[41]\,
      I2 => req_row_r(30),
      I3 => \^q\(3),
      O => \pre_4_1_1T_arb.granted_pre_r_reg\(7)
    );
\cmd_pipe_plus.mc_address[35]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"000007F7FFFF07F7"
    )
        port map (
      I0 => \cmd_pipe_plus.mc_address_reg[41]_0\(7),
      I1 => \^q\(0),
      I2 => \^q\(1),
      I3 => req_row_r(10),
      I4 => \^q\(2),
      I5 => req_row_r(19),
      O => \cmd_pipe_plus.mc_address[35]_i_2_n_0\
    );
\cmd_pipe_plus.mc_address[36]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F377"
    )
        port map (
      I0 => \cmd_pipe_plus.mc_address[36]_i_2_n_0\,
      I1 => \cmd_pipe_plus.mc_address_reg[41]\,
      I2 => req_row_r(31),
      I3 => \^q\(3),
      O => \pre_4_1_1T_arb.granted_pre_r_reg\(8)
    );
\cmd_pipe_plus.mc_address[36]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"000007F7FFFF07F7"
    )
        port map (
      I0 => \cmd_pipe_plus.mc_address_reg[41]_0\(8),
      I1 => \^q\(0),
      I2 => \^q\(1),
      I3 => req_row_r(11),
      I4 => \^q\(2),
      I5 => req_row_r(20),
      O => \cmd_pipe_plus.mc_address[36]_i_2_n_0\
    );
\cmd_pipe_plus.mc_address[37]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F377"
    )
        port map (
      I0 => \cmd_pipe_plus.mc_address[37]_i_2_n_0\,
      I1 => \cmd_pipe_plus.mc_address_reg[41]\,
      I2 => req_row_r(32),
      I3 => \^q\(3),
      O => \pre_4_1_1T_arb.granted_pre_r_reg\(9)
    );
\cmd_pipe_plus.mc_address[37]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"000007F7FFFF07F7"
    )
        port map (
      I0 => req_row_r(0),
      I1 => \^q\(0),
      I2 => \^q\(1),
      I3 => \cmd_pipe_plus.mc_address_reg[41]_0\(11),
      I4 => \^q\(2),
      I5 => req_row_r(21),
      O => \cmd_pipe_plus.mc_address[37]_i_2_n_0\
    );
\cmd_pipe_plus.mc_address[38]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FF0FDFDF0F0FDFDF"
    )
        port map (
      I0 => \cmd_pipe_plus.mc_address[38]_i_2_n_0\,
      I1 => \cmd_pipe_plus.mc_address_reg[38]\,
      I2 => \cmd_pipe_plus.mc_address_reg[41]\,
      I3 => req_row_r(33),
      I4 => \^q\(3),
      I5 => \cmd_pipe_plus.mc_we_n_reg[2]\,
      O => \pre_4_1_1T_arb.granted_pre_r_reg\(10)
    );
\cmd_pipe_plus.mc_address[38]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFFF7F"
    )
        port map (
      I0 => \cmd_pipe_plus.mc_we_n_reg[2]_0\,
      I1 => req_row_r(1),
      I2 => \^q\(0),
      I3 => \^q\(1),
      I4 => \^q\(2),
      O => \cmd_pipe_plus.mc_address[38]_i_2_n_0\
    );
\cmd_pipe_plus.mc_address[39]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F377"
    )
        port map (
      I0 => \cmd_pipe_plus.mc_address[39]_i_2_n_0\,
      I1 => \cmd_pipe_plus.mc_address_reg[41]\,
      I2 => req_row_r(34),
      I3 => \^q\(3),
      O => \pre_4_1_1T_arb.granted_pre_r_reg\(11)
    );
\cmd_pipe_plus.mc_address[39]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"000007F7FFFF07F7"
    )
        port map (
      I0 => req_row_r(2),
      I1 => \^q\(0),
      I2 => \^q\(1),
      I3 => \cmd_pipe_plus.mc_address_reg[41]_0\(12),
      I4 => \^q\(2),
      I5 => req_row_r(22),
      O => \cmd_pipe_plus.mc_address[39]_i_2_n_0\
    );
\cmd_pipe_plus.mc_address[40]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F377"
    )
        port map (
      I0 => \cmd_pipe_plus.mc_address[40]_i_2_n_0\,
      I1 => \cmd_pipe_plus.mc_address_reg[41]\,
      I2 => \cmd_pipe_plus.mc_address_reg[41]_0\(17),
      I3 => \^q\(3),
      O => \pre_4_1_1T_arb.granted_pre_r_reg\(12)
    );
\cmd_pipe_plus.mc_address[40]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"000007F7FFFF07F7"
    )
        port map (
      I0 => \cmd_pipe_plus.mc_address_reg[41]_0\(9),
      I1 => \^q\(0),
      I2 => \^q\(1),
      I3 => \cmd_pipe_plus.mc_address_reg[41]_0\(13),
      I4 => \^q\(2),
      I5 => \cmd_pipe_plus.mc_address_reg[41]_0\(15),
      O => \cmd_pipe_plus.mc_address[40]_i_2_n_0\
    );
\cmd_pipe_plus.mc_address[41]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F377"
    )
        port map (
      I0 => \cmd_pipe_plus.mc_address[41]_i_2_n_0\,
      I1 => \cmd_pipe_plus.mc_address_reg[41]\,
      I2 => \cmd_pipe_plus.mc_address_reg[41]_0\(18),
      I3 => \^q\(3),
      O => \pre_4_1_1T_arb.granted_pre_r_reg\(13)
    );
\cmd_pipe_plus.mc_address[41]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"000007F7FFFF07F7"
    )
        port map (
      I0 => \cmd_pipe_plus.mc_address_reg[41]_0\(10),
      I1 => \^q\(0),
      I2 => \^q\(1),
      I3 => \cmd_pipe_plus.mc_address_reg[41]_0\(14),
      I4 => \^q\(2),
      I5 => \cmd_pipe_plus.mc_address_reg[41]_0\(16),
      O => \cmd_pipe_plus.mc_address[41]_i_2_n_0\
    );
\cmd_pipe_plus.mc_bank[6]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F737"
    )
        port map (
      I0 => \cmd_pipe_plus.mc_bank[6]_i_2_n_0\,
      I1 => \cmd_pipe_plus.mc_address_reg[41]\,
      I2 => \^q\(3),
      I3 => \cmd_pipe_plus.mc_bank_reg[8]\(0),
      O => \pre_4_1_1T_arb.granted_pre_r_reg_0\(0)
    );
\cmd_pipe_plus.mc_bank[6]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000F77FFFF0F77"
    )
        port map (
      I0 => \cmd_pipe_plus.mc_bank_reg[8]_0\(0),
      I1 => \^q\(0),
      I2 => \cmd_pipe_plus.mc_bank_reg[8]_1\(0),
      I3 => \^q\(1),
      I4 => \^q\(2),
      I5 => \cmd_pipe_plus.mc_bank_reg[8]_2\(0),
      O => \cmd_pipe_plus.mc_bank[6]_i_2_n_0\
    );
\cmd_pipe_plus.mc_bank[7]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F737"
    )
        port map (
      I0 => \cmd_pipe_plus.mc_bank[7]_i_2_n_0\,
      I1 => \cmd_pipe_plus.mc_address_reg[41]\,
      I2 => \^q\(3),
      I3 => \cmd_pipe_plus.mc_bank_reg[8]\(1),
      O => \pre_4_1_1T_arb.granted_pre_r_reg_0\(1)
    );
\cmd_pipe_plus.mc_bank[7]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000F77FFFF0F77"
    )
        port map (
      I0 => \cmd_pipe_plus.mc_bank_reg[8]_0\(1),
      I1 => \^q\(0),
      I2 => \cmd_pipe_plus.mc_bank_reg[8]_1\(1),
      I3 => \^q\(1),
      I4 => \^q\(2),
      I5 => \cmd_pipe_plus.mc_bank_reg[8]_2\(1),
      O => \cmd_pipe_plus.mc_bank[7]_i_2_n_0\
    );
\cmd_pipe_plus.mc_bank[8]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F737"
    )
        port map (
      I0 => \cmd_pipe_plus.mc_bank[8]_i_2_n_0\,
      I1 => \cmd_pipe_plus.mc_address_reg[41]\,
      I2 => \^q\(3),
      I3 => \cmd_pipe_plus.mc_bank_reg[8]\(2),
      O => \pre_4_1_1T_arb.granted_pre_r_reg_0\(2)
    );
\cmd_pipe_plus.mc_bank[8]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000F77FFFF0F77"
    )
        port map (
      I0 => \cmd_pipe_plus.mc_bank_reg[8]_0\(2),
      I1 => \^q\(0),
      I2 => \cmd_pipe_plus.mc_bank_reg[8]_1\(2),
      I3 => \^q\(1),
      I4 => \^q\(2),
      I5 => \cmd_pipe_plus.mc_bank_reg[8]_2\(2),
      O => \cmd_pipe_plus.mc_bank[8]_i_2_n_0\
    );
\cmd_pipe_plus.mc_cas_n[2]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFFFFD"
    )
        port map (
      I0 => \cmd_pipe_plus.mc_address_reg[41]\,
      I1 => \^q\(3),
      I2 => \^q\(1),
      I3 => \^q\(2),
      I4 => \^q\(0),
      O => mc_cas_n_ns(0)
    );
\cmd_pipe_plus.mc_we_n[2]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F377"
    )
        port map (
      I0 => \cmd_pipe_plus.mc_we_n[2]_i_2_n_0\,
      I1 => \cmd_pipe_plus.mc_address_reg[41]\,
      I2 => \cmd_pipe_plus.mc_we_n_reg[2]\,
      I3 => \^q\(3),
      O => mc_we_n_ns(0)
    );
\cmd_pipe_plus.mc_we_n[2]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000F77FFFF0F77"
    )
        port map (
      I0 => \cmd_pipe_plus.mc_we_n_reg[2]_0\,
      I1 => \^q\(0),
      I2 => \cmd_pipe_plus.mc_we_n_reg[2]_1\,
      I3 => \^q\(1),
      I4 => \^q\(2),
      I5 => \cmd_pipe_plus.mc_we_n_reg[2]_2\,
      O => \cmd_pipe_plus.mc_we_n[2]_i_2_n_0\
    );
\grant_r[0]_i_1__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"020202AA00000000"
    )
        port map (
      I0 => \grant_r[2]_i_2__1_n_0\,
      I1 => \last_master_r[0]_i_1__0_n_0\,
      I2 => \last_master_r[1]_i_1__0_n_0\,
      I3 => \grant_r_reg[0]_0\,
      I4 => \grant_r_reg[0]_1\,
      I5 => \grant_r_reg[0]_2\,
      O => \grant_r[0]_i_1__2_n_0\
    );
\grant_r[1]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"020202AA00000000"
    )
        port map (
      I0 => \grant_r[3]_i_4__0_n_0\,
      I1 => \last_master_r[2]_i_1__1_n_0\,
      I2 => \last_master_r[1]_i_1__0_n_0\,
      I3 => \grant_r_reg[0]_2\,
      I4 => \grant_r_reg[0]_0\,
      I5 => \grant_r_reg[1]_0\,
      O => \grant_r[1]_i_1__0_n_0\
    );
\grant_r[2]_i_1__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"202020AA00000000"
    )
        port map (
      I0 => \grant_r[2]_i_2__1_n_0\,
      I1 => \last_master_r[2]_i_1__1_n_0\,
      I2 => \grant_r_reg[3]_0\,
      I3 => \grant_r_reg[0]_2\,
      I4 => \grant_r_reg[1]_0\,
      I5 => \grant_r_reg[0]_1\,
      O => \grant_r[2]_i_1__2_n_0\
    );
\grant_r[2]_i_2__1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0777"
    )
        port map (
      I0 => \grant_r_reg[1]_0\,
      I1 => \last_master_r[0]_i_1__0_n_0\,
      I2 => \grant_r_reg[0]_0\,
      I3 => \last_master_r[2]_i_1__1_n_0\,
      O => \grant_r[2]_i_2__1_n_0\
    );
\grant_r[3]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"222F000000000000"
    )
        port map (
      I0 => \grant_r_reg[3]_0\,
      I1 => \last_master_r[0]_i_1__0_n_0\,
      I2 => \grant_r_reg[0]_1\,
      I3 => \grant_r_reg[1]_0\,
      I4 => \grant_r[3]_i_4__0_n_0\,
      I5 => \grant_r_reg[0]_0\,
      O => \grant_r[3]_i_1_n_0\
    );
\grant_r[3]_i_4__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7077"
    )
        port map (
      I0 => \grant_r_reg[0]_1\,
      I1 => \last_master_r[1]_i_1__0_n_0\,
      I2 => \grant_r_reg[3]_0\,
      I3 => \grant_r_reg[0]_2\,
      O => \grant_r[3]_i_4__0_n_0\
    );
\grant_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \last_master_r_reg[3]_1\,
      CE => '1',
      D => \grant_r[0]_i_1__2_n_0\,
      Q => \^q\(0),
      R => '0'
    );
\grant_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \last_master_r_reg[3]_1\,
      CE => '1',
      D => \grant_r[1]_i_1__0_n_0\,
      Q => \^q\(1),
      R => '0'
    );
\grant_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \last_master_r_reg[3]_1\,
      CE => '1',
      D => \grant_r[2]_i_1__2_n_0\,
      Q => \^q\(2),
      R => '0'
    );
\grant_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => \last_master_r_reg[3]_1\,
      CE => '1',
      D => \grant_r[3]_i_1_n_0\,
      Q => \^q\(3),
      R => '0'
    );
\last_master_r[0]_i_1__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"00E2"
    )
        port map (
      I0 => last_master_r(0),
      I1 => \cmd_pipe_plus.mc_address_reg[41]\,
      I2 => \^q\(0),
      I3 => \last_master_r_reg[1]_0\,
      O => \last_master_r[0]_i_1__0_n_0\
    );
\last_master_r[1]_i_1__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"00E2"
    )
        port map (
      I0 => last_master_r(1),
      I1 => \cmd_pipe_plus.mc_address_reg[41]\,
      I2 => \^q\(1),
      I3 => \last_master_r_reg[1]_0\,
      O => \last_master_r[1]_i_1__0_n_0\
    );
\last_master_r[2]_i_1__1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"00E2"
    )
        port map (
      I0 => last_master_r(2),
      I1 => \cmd_pipe_plus.mc_address_reg[41]\,
      I2 => \^q\(2),
      I3 => \last_master_r_reg[1]_0\,
      O => \last_master_r[2]_i_1__1_n_0\
    );
\last_master_r[3]_i_1__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFB8"
    )
        port map (
      I0 => \^q\(3),
      I1 => \cmd_pipe_plus.mc_address_reg[41]\,
      I2 => \^last_master_r_reg[3]_0\(0),
      I3 => \last_master_r_reg[1]_0\,
      O => \last_master_r[3]_i_1__0_n_0\
    );
\last_master_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \last_master_r_reg[3]_1\,
      CE => '1',
      D => \last_master_r[0]_i_1__0_n_0\,
      Q => last_master_r(0),
      R => '0'
    );
\last_master_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \last_master_r_reg[3]_1\,
      CE => '1',
      D => \last_master_r[1]_i_1__0_n_0\,
      Q => last_master_r(1),
      R => '0'
    );
\last_master_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \last_master_r_reg[3]_1\,
      CE => '1',
      D => \last_master_r[2]_i_1__1_n_0\,
      Q => last_master_r(2),
      R => '0'
    );
\last_master_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => \last_master_r_reg[3]_1\,
      CE => '1',
      D => \last_master_r[3]_i_1__0_n_0\,
      Q => \^last_master_r_reg[3]_0\(0),
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \mig_mig_7series_v4_2_round_robin_arb__parameterized1_4\ is
  port (
    granted_row_ns : out STD_LOGIC;
    mc_we_n_ns : out STD_LOGIC_VECTOR ( 0 to 0 );
    Q : out STD_LOGIC_VECTOR ( 3 downto 0 );
    mc_cas_n_ns : out STD_LOGIC_VECTOR ( 0 to 0 );
    mc_ras_n_ns : out STD_LOGIC_VECTOR ( 0 to 0 );
    \grant_r_reg[0]_0\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
    \req_row_r_lcl_reg[13]\ : out STD_LOGIC_VECTOR ( 13 downto 0 );
    \grant_r_reg[1]_0\ : out STD_LOGIC;
    \grant_r_reg[0]_1\ : out STD_LOGIC;
    act_this_rank : out STD_LOGIC;
    \grant_r_reg[0]_2\ : out STD_LOGIC;
    \grant_r_reg[3]_0\ : in STD_LOGIC;
    granted_row_r_reg : in STD_LOGIC;
    \grant_r_reg[3]_1\ : in STD_LOGIC;
    \cmd_pipe_plus.mc_we_n_reg[0]\ : in STD_LOGIC;
    \cmd_pipe_plus.mc_we_n_reg[0]_0\ : in STD_LOGIC;
    \cmd_pipe_plus.mc_address_reg[0]\ : in STD_LOGIC;
    \cmd_pipe_plus.mc_cas_n_reg[0]\ : in STD_LOGIC;
    \cmd_pipe_plus.mc_ras_n_reg[0]\ : in STD_LOGIC;
    maint_zq_r : in STD_LOGIC;
    maint_srx_r : in STD_LOGIC;
    \last_master_r_reg[2]_0\ : in STD_LOGIC;
    \cmd_pipe_plus.mc_bank_reg[2]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
    \cmd_pipe_plus.mc_address_reg[3]\ : in STD_LOGIC;
    \cmd_pipe_plus.mc_bank_reg[2]_0\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
    \cmd_pipe_plus.mc_address_reg[0]_0\ : in STD_LOGIC;
    \cmd_pipe_plus.mc_bank_reg[2]_1\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
    \cmd_pipe_plus.mc_bank_reg[2]_2\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
    \cmd_pipe_plus.mc_address_reg[13]\ : in STD_LOGIC_VECTOR ( 19 downto 0 );
    req_row_r : in STD_LOGIC_VECTOR ( 33 downto 0 );
    \cmd_pipe_plus.mc_address_reg[10]\ : in STD_LOGIC;
    \cmd_pipe_plus.mc_address_reg[10]_0\ : in STD_LOGIC;
    \cmd_pipe_plus.mc_we_n_reg[0]_1\ : in STD_LOGIC;
    \cmd_pipe_plus.mc_we_n_reg[0]_2\ : in STD_LOGIC;
    \grant_r_reg[3]_2\ : in STD_LOGIC;
    \i___70\ : in STD_LOGIC;
    inhbt_act_faw_r : in STD_LOGIC;
    act_this_rank_r : in STD_LOGIC_VECTOR ( 3 downto 0 );
    \last_master_r_reg[3]_0\ : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \mig_mig_7series_v4_2_round_robin_arb__parameterized1_4\ : entity is "mig_7series_v4_2_round_robin_arb";
end \mig_mig_7series_v4_2_round_robin_arb__parameterized1_4\;

architecture STRUCTURE of \mig_mig_7series_v4_2_round_robin_arb__parameterized1_4\ is
  signal \^q\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \cmd_pipe_plus.mc_address[0]_i_2_n_0\ : STD_LOGIC;
  signal \cmd_pipe_plus.mc_address[10]_i_2_n_0\ : STD_LOGIC;
  signal \cmd_pipe_plus.mc_address[11]_i_2_n_0\ : STD_LOGIC;
  signal \cmd_pipe_plus.mc_address[12]_i_2_n_0\ : STD_LOGIC;
  signal \cmd_pipe_plus.mc_address[13]_i_2_n_0\ : STD_LOGIC;
  signal \cmd_pipe_plus.mc_address[1]_i_2_n_0\ : STD_LOGIC;
  signal \cmd_pipe_plus.mc_address[2]_i_2_n_0\ : STD_LOGIC;
  signal \cmd_pipe_plus.mc_address[3]_i_2_n_0\ : STD_LOGIC;
  signal \cmd_pipe_plus.mc_address[4]_i_2_n_0\ : STD_LOGIC;
  signal \cmd_pipe_plus.mc_address[5]_i_2_n_0\ : STD_LOGIC;
  signal \cmd_pipe_plus.mc_address[6]_i_2_n_0\ : STD_LOGIC;
  signal \cmd_pipe_plus.mc_address[7]_i_2_n_0\ : STD_LOGIC;
  signal \cmd_pipe_plus.mc_address[8]_i_2_n_0\ : STD_LOGIC;
  signal \cmd_pipe_plus.mc_address[9]_i_2_n_0\ : STD_LOGIC;
  signal \cmd_pipe_plus.mc_bank[0]_i_2_n_0\ : STD_LOGIC;
  signal \cmd_pipe_plus.mc_bank[1]_i_2_n_0\ : STD_LOGIC;
  signal \cmd_pipe_plus.mc_bank[2]_i_2_n_0\ : STD_LOGIC;
  signal \cmd_pipe_plus.mc_ras_n[0]_i_2_n_0\ : STD_LOGIC;
  signal \cmd_pipe_plus.mc_we_n[0]_i_2_n_0\ : STD_LOGIC;
  signal \grant_r[0]_i_1__1_n_0\ : STD_LOGIC;
  signal \grant_r[1]_i_1__2_n_0\ : STD_LOGIC;
  signal \grant_r[2]_i_1__1_n_0\ : STD_LOGIC;
  signal \grant_r[2]_i_2__0_n_0\ : STD_LOGIC;
  signal \grant_r[3]_i_1__1_n_0\ : STD_LOGIC;
  signal \grant_r[3]_i_2__0_n_0\ : STD_LOGIC;
  signal \grant_r[3]_i_3__0_n_0\ : STD_LOGIC;
  signal \^grant_r_reg[0]_2\ : STD_LOGIC;
  signal \^grant_r_reg[1]_0\ : STD_LOGIC;
  signal \i___79_i_2_n_0\ : STD_LOGIC;
  signal last_master_r : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \last_master_r[0]_i_1__1_n_0\ : STD_LOGIC;
  signal \last_master_r[1]_i_1__1_n_0\ : STD_LOGIC;
  signal \last_master_r[2]_i_1__2_n_0\ : STD_LOGIC;
  signal \last_master_r[3]_i_1__1_n_0\ : STD_LOGIC;
begin
  Q(3 downto 0) <= \^q\(3 downto 0);
  \grant_r_reg[0]_2\ <= \^grant_r_reg[0]_2\;
  \grant_r_reg[1]_0\ <= \^grant_r_reg[1]_0\;
\cmd_pipe_plus.mc_address[0]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"F800F8F8"
    )
        port map (
      I0 => \cmd_pipe_plus.mc_address_reg[13]\(0),
      I1 => \^q\(0),
      I2 => \cmd_pipe_plus.mc_address_reg[0]\,
      I3 => \cmd_pipe_plus.mc_address[0]_i_2_n_0\,
      I4 => \cmd_pipe_plus.mc_address_reg[0]_0\,
      O => \req_row_r_lcl_reg[13]\(0)
    );
\cmd_pipe_plus.mc_address[0]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF8080000F808"
    )
        port map (
      I0 => \^q\(1),
      I1 => req_row_r(3),
      I2 => \^q\(2),
      I3 => req_row_r(12),
      I4 => \^q\(3),
      I5 => req_row_r(23),
      O => \cmd_pipe_plus.mc_address[0]_i_2_n_0\
    );
\cmd_pipe_plus.mc_address[10]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FF800000FF80FF80"
    )
        port map (
      I0 => \^q\(0),
      I1 => \cmd_pipe_plus.mc_address_reg[10]\,
      I2 => req_row_r(1),
      I3 => \cmd_pipe_plus.mc_address_reg[0]\,
      I4 => \cmd_pipe_plus.mc_address[10]_i_2_n_0\,
      I5 => \cmd_pipe_plus.mc_address_reg[0]_0\,
      O => \req_row_r_lcl_reg[13]\(10)
    );
\cmd_pipe_plus.mc_address[10]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAEAAAAAAAAA"
    )
        port map (
      I0 => \cmd_pipe_plus.mc_address_reg[10]_0\,
      I1 => \cmd_pipe_plus.mc_we_n_reg[0]_0\,
      I2 => \^q\(1),
      I3 => \^q\(3),
      I4 => \^q\(2),
      I5 => \cmd_pipe_plus.mc_address_reg[13]\(12),
      O => \cmd_pipe_plus.mc_address[10]_i_2_n_0\
    );
\cmd_pipe_plus.mc_address[11]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F800F8F8F800F800"
    )
        port map (
      I0 => req_row_r(2),
      I1 => \^q\(0),
      I2 => \cmd_pipe_plus.mc_address_reg[0]\,
      I3 => \cmd_pipe_plus.mc_address[11]_i_2_n_0\,
      I4 => \cmd_pipe_plus.mc_address_reg[3]\,
      I5 => \cmd_pipe_plus.mc_address_reg[13]\(13),
      O => \req_row_r_lcl_reg[13]\(11)
    );
\cmd_pipe_plus.mc_address[11]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFD555D5"
    )
        port map (
      I0 => \cmd_pipe_plus.mc_address_reg[0]_0\,
      I1 => req_row_r(22),
      I2 => \^q\(2),
      I3 => \^q\(3),
      I4 => req_row_r(33),
      O => \cmd_pipe_plus.mc_address[11]_i_2_n_0\
    );
\cmd_pipe_plus.mc_address[12]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F800F8F8F800F800"
    )
        port map (
      I0 => \cmd_pipe_plus.mc_address_reg[13]\(9),
      I1 => \^q\(0),
      I2 => \cmd_pipe_plus.mc_address_reg[0]\,
      I3 => \cmd_pipe_plus.mc_address[12]_i_2_n_0\,
      I4 => \cmd_pipe_plus.mc_address_reg[3]\,
      I5 => \cmd_pipe_plus.mc_address_reg[13]\(14),
      O => \req_row_r_lcl_reg[13]\(12)
    );
\cmd_pipe_plus.mc_address[12]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFD555D5"
    )
        port map (
      I0 => \cmd_pipe_plus.mc_address_reg[0]_0\,
      I1 => \cmd_pipe_plus.mc_address_reg[13]\(16),
      I2 => \^q\(2),
      I3 => \^q\(3),
      I4 => \cmd_pipe_plus.mc_address_reg[13]\(18),
      O => \cmd_pipe_plus.mc_address[12]_i_2_n_0\
    );
\cmd_pipe_plus.mc_address[13]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"F800F8F8"
    )
        port map (
      I0 => \cmd_pipe_plus.mc_address_reg[13]\(10),
      I1 => \^q\(0),
      I2 => \cmd_pipe_plus.mc_address_reg[0]\,
      I3 => \cmd_pipe_plus.mc_address[13]_i_2_n_0\,
      I4 => \cmd_pipe_plus.mc_address_reg[0]_0\,
      O => \req_row_r_lcl_reg[13]\(13)
    );
\cmd_pipe_plus.mc_address[13]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF8080000F808"
    )
        port map (
      I0 => \^q\(1),
      I1 => \cmd_pipe_plus.mc_address_reg[13]\(15),
      I2 => \^q\(2),
      I3 => \cmd_pipe_plus.mc_address_reg[13]\(17),
      I4 => \^q\(3),
      I5 => \cmd_pipe_plus.mc_address_reg[13]\(19),
      O => \cmd_pipe_plus.mc_address[13]_i_2_n_0\
    );
\cmd_pipe_plus.mc_address[1]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"F800F8F8"
    )
        port map (
      I0 => \cmd_pipe_plus.mc_address_reg[13]\(1),
      I1 => \^q\(0),
      I2 => \cmd_pipe_plus.mc_address_reg[0]\,
      I3 => \cmd_pipe_plus.mc_address[1]_i_2_n_0\,
      I4 => \cmd_pipe_plus.mc_address_reg[0]_0\,
      O => \req_row_r_lcl_reg[13]\(1)
    );
\cmd_pipe_plus.mc_address[1]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF8080000F808"
    )
        port map (
      I0 => \^q\(1),
      I1 => req_row_r(4),
      I2 => \^q\(2),
      I3 => req_row_r(13),
      I4 => \^q\(3),
      I5 => req_row_r(24),
      O => \cmd_pipe_plus.mc_address[1]_i_2_n_0\
    );
\cmd_pipe_plus.mc_address[2]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"F800F8F8"
    )
        port map (
      I0 => \cmd_pipe_plus.mc_address_reg[13]\(2),
      I1 => \^q\(0),
      I2 => \cmd_pipe_plus.mc_address_reg[0]\,
      I3 => \cmd_pipe_plus.mc_address[2]_i_2_n_0\,
      I4 => \cmd_pipe_plus.mc_address_reg[0]_0\,
      O => \req_row_r_lcl_reg[13]\(2)
    );
\cmd_pipe_plus.mc_address[2]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF8080000F808"
    )
        port map (
      I0 => \^q\(1),
      I1 => req_row_r(5),
      I2 => \^q\(2),
      I3 => req_row_r(14),
      I4 => \^q\(3),
      I5 => req_row_r(25),
      O => \cmd_pipe_plus.mc_address[2]_i_2_n_0\
    );
\cmd_pipe_plus.mc_address[3]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F800F8F8F800F800"
    )
        port map (
      I0 => \cmd_pipe_plus.mc_address_reg[13]\(3),
      I1 => \^q\(0),
      I2 => \cmd_pipe_plus.mc_address_reg[0]\,
      I3 => \cmd_pipe_plus.mc_address[3]_i_2_n_0\,
      I4 => \cmd_pipe_plus.mc_address_reg[3]\,
      I5 => req_row_r(6),
      O => \req_row_r_lcl_reg[13]\(3)
    );
\cmd_pipe_plus.mc_address[3]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFD555D5"
    )
        port map (
      I0 => \cmd_pipe_plus.mc_address_reg[0]_0\,
      I1 => req_row_r(15),
      I2 => \^q\(2),
      I3 => \^q\(3),
      I4 => req_row_r(26),
      O => \cmd_pipe_plus.mc_address[3]_i_2_n_0\
    );
\cmd_pipe_plus.mc_address[4]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"F800F8F8"
    )
        port map (
      I0 => \cmd_pipe_plus.mc_address_reg[13]\(4),
      I1 => \^q\(0),
      I2 => \cmd_pipe_plus.mc_address_reg[0]\,
      I3 => \cmd_pipe_plus.mc_address[4]_i_2_n_0\,
      I4 => \cmd_pipe_plus.mc_address_reg[0]_0\,
      O => \req_row_r_lcl_reg[13]\(4)
    );
\cmd_pipe_plus.mc_address[4]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF8080000F808"
    )
        port map (
      I0 => \^q\(1),
      I1 => req_row_r(7),
      I2 => \^q\(2),
      I3 => req_row_r(16),
      I4 => \^q\(3),
      I5 => req_row_r(27),
      O => \cmd_pipe_plus.mc_address[4]_i_2_n_0\
    );
\cmd_pipe_plus.mc_address[5]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F800F8F8F800F800"
    )
        port map (
      I0 => \cmd_pipe_plus.mc_address_reg[13]\(5),
      I1 => \^q\(0),
      I2 => \cmd_pipe_plus.mc_address_reg[0]\,
      I3 => \cmd_pipe_plus.mc_address[5]_i_2_n_0\,
      I4 => \cmd_pipe_plus.mc_address_reg[3]\,
      I5 => req_row_r(8),
      O => \req_row_r_lcl_reg[13]\(5)
    );
\cmd_pipe_plus.mc_address[5]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFD555D5"
    )
        port map (
      I0 => \cmd_pipe_plus.mc_address_reg[0]_0\,
      I1 => req_row_r(17),
      I2 => \^q\(2),
      I3 => \^q\(3),
      I4 => req_row_r(28),
      O => \cmd_pipe_plus.mc_address[5]_i_2_n_0\
    );
\cmd_pipe_plus.mc_address[6]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"F800F8F8"
    )
        port map (
      I0 => \cmd_pipe_plus.mc_address_reg[13]\(6),
      I1 => \^q\(0),
      I2 => \cmd_pipe_plus.mc_address_reg[0]\,
      I3 => \cmd_pipe_plus.mc_address[6]_i_2_n_0\,
      I4 => \cmd_pipe_plus.mc_address_reg[0]_0\,
      O => \req_row_r_lcl_reg[13]\(6)
    );
\cmd_pipe_plus.mc_address[6]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF8080000F808"
    )
        port map (
      I0 => \^q\(1),
      I1 => req_row_r(9),
      I2 => \^q\(2),
      I3 => req_row_r(18),
      I4 => \^q\(3),
      I5 => req_row_r(29),
      O => \cmd_pipe_plus.mc_address[6]_i_2_n_0\
    );
\cmd_pipe_plus.mc_address[7]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"F800F8F8"
    )
        port map (
      I0 => \cmd_pipe_plus.mc_address_reg[13]\(7),
      I1 => \^q\(0),
      I2 => \cmd_pipe_plus.mc_address_reg[0]\,
      I3 => \cmd_pipe_plus.mc_address[7]_i_2_n_0\,
      I4 => \cmd_pipe_plus.mc_address_reg[0]_0\,
      O => \req_row_r_lcl_reg[13]\(7)
    );
\cmd_pipe_plus.mc_address[7]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF8080000F808"
    )
        port map (
      I0 => \^q\(1),
      I1 => req_row_r(10),
      I2 => \^q\(2),
      I3 => req_row_r(19),
      I4 => \^q\(3),
      I5 => req_row_r(30),
      O => \cmd_pipe_plus.mc_address[7]_i_2_n_0\
    );
\cmd_pipe_plus.mc_address[8]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"F800F8F8"
    )
        port map (
      I0 => \cmd_pipe_plus.mc_address_reg[13]\(8),
      I1 => \^q\(0),
      I2 => \cmd_pipe_plus.mc_address_reg[0]\,
      I3 => \cmd_pipe_plus.mc_address[8]_i_2_n_0\,
      I4 => \cmd_pipe_plus.mc_address_reg[0]_0\,
      O => \req_row_r_lcl_reg[13]\(8)
    );
\cmd_pipe_plus.mc_address[8]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF8080000F808"
    )
        port map (
      I0 => \^q\(1),
      I1 => req_row_r(11),
      I2 => \^q\(2),
      I3 => req_row_r(20),
      I4 => \^q\(3),
      I5 => req_row_r(31),
      O => \cmd_pipe_plus.mc_address[8]_i_2_n_0\
    );
\cmd_pipe_plus.mc_address[9]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"F800F8F8"
    )
        port map (
      I0 => req_row_r(0),
      I1 => \^q\(0),
      I2 => \cmd_pipe_plus.mc_address_reg[0]\,
      I3 => \cmd_pipe_plus.mc_address[9]_i_2_n_0\,
      I4 => \cmd_pipe_plus.mc_address_reg[0]_0\,
      O => \req_row_r_lcl_reg[13]\(9)
    );
\cmd_pipe_plus.mc_address[9]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF8080000F808"
    )
        port map (
      I0 => \^q\(1),
      I1 => \cmd_pipe_plus.mc_address_reg[13]\(11),
      I2 => \^q\(2),
      I3 => req_row_r(21),
      I4 => \^q\(3),
      I5 => req_row_r(32),
      O => \cmd_pipe_plus.mc_address[9]_i_2_n_0\
    );
\cmd_pipe_plus.mc_bank[0]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"F800F8F8"
    )
        port map (
      I0 => \^q\(0),
      I1 => \cmd_pipe_plus.mc_bank_reg[2]\(0),
      I2 => \cmd_pipe_plus.mc_address_reg[0]\,
      I3 => \cmd_pipe_plus.mc_bank[0]_i_2_n_0\,
      I4 => \cmd_pipe_plus.mc_address_reg[0]_0\,
      O => \grant_r_reg[0]_0\(0)
    );
\cmd_pipe_plus.mc_bank[0]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF0880000F088"
    )
        port map (
      I0 => \^q\(1),
      I1 => \cmd_pipe_plus.mc_bank_reg[2]_0\(0),
      I2 => \cmd_pipe_plus.mc_bank_reg[2]_1\(0),
      I3 => \^q\(2),
      I4 => \^q\(3),
      I5 => \cmd_pipe_plus.mc_bank_reg[2]_2\(0),
      O => \cmd_pipe_plus.mc_bank[0]_i_2_n_0\
    );
\cmd_pipe_plus.mc_bank[1]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F800F8F8F800F800"
    )
        port map (
      I0 => \^q\(0),
      I1 => \cmd_pipe_plus.mc_bank_reg[2]\(1),
      I2 => \cmd_pipe_plus.mc_address_reg[0]\,
      I3 => \cmd_pipe_plus.mc_bank[1]_i_2_n_0\,
      I4 => \cmd_pipe_plus.mc_address_reg[3]\,
      I5 => \cmd_pipe_plus.mc_bank_reg[2]_0\(1),
      O => \grant_r_reg[0]_0\(1)
    );
\cmd_pipe_plus.mc_bank[1]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFD555D5"
    )
        port map (
      I0 => \cmd_pipe_plus.mc_address_reg[0]_0\,
      I1 => \cmd_pipe_plus.mc_bank_reg[2]_1\(1),
      I2 => \^q\(2),
      I3 => \^q\(3),
      I4 => \cmd_pipe_plus.mc_bank_reg[2]_2\(1),
      O => \cmd_pipe_plus.mc_bank[1]_i_2_n_0\
    );
\cmd_pipe_plus.mc_bank[2]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"EA00EAEAEA00EA00"
    )
        port map (
      I0 => \cmd_pipe_plus.mc_address_reg[0]\,
      I1 => \^q\(0),
      I2 => \cmd_pipe_plus.mc_bank_reg[2]\(2),
      I3 => \cmd_pipe_plus.mc_bank[2]_i_2_n_0\,
      I4 => \cmd_pipe_plus.mc_address_reg[3]\,
      I5 => \cmd_pipe_plus.mc_bank_reg[2]_0\(2),
      O => \grant_r_reg[0]_0\(2)
    );
\cmd_pipe_plus.mc_bank[2]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFD555D5"
    )
        port map (
      I0 => \cmd_pipe_plus.mc_address_reg[0]_0\,
      I1 => \cmd_pipe_plus.mc_bank_reg[2]_1\(2),
      I2 => \^q\(2),
      I3 => \^q\(3),
      I4 => \cmd_pipe_plus.mc_bank_reg[2]_2\(2),
      O => \cmd_pipe_plus.mc_bank[2]_i_2_n_0\
    );
\cmd_pipe_plus.mc_cas_n[0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FBFAFBFAFBFAFAFA"
    )
        port map (
      I0 => \cmd_pipe_plus.mc_address_reg[0]\,
      I1 => \cmd_pipe_plus.mc_cas_n_reg[0]\,
      I2 => \^q\(0),
      I3 => \cmd_pipe_plus.mc_ras_n_reg[0]\,
      I4 => maint_zq_r,
      I5 => maint_srx_r,
      O => mc_cas_n_ns(0)
    );
\cmd_pipe_plus.mc_ras_n[0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"000200020002FFFF"
    )
        port map (
      I0 => \cmd_pipe_plus.mc_ras_n[0]_i_2_n_0\,
      I1 => \^q\(1),
      I2 => \^q\(2),
      I3 => \^q\(3),
      I4 => \cmd_pipe_plus.mc_ras_n_reg[0]\,
      I5 => \last_master_r_reg[2]_0\,
      O => mc_ras_n_ns(0)
    );
\cmd_pipe_plus.mc_ras_n[0]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"10101000"
    )
        port map (
      I0 => \cmd_pipe_plus.mc_cas_n_reg[0]\,
      I1 => \^q\(0),
      I2 => \cmd_pipe_plus.mc_ras_n_reg[0]\,
      I3 => maint_zq_r,
      I4 => maint_srx_r,
      O => \cmd_pipe_plus.mc_ras_n[0]_i_2_n_0\
    );
\cmd_pipe_plus.mc_we_n[0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"CCCCCCCCCCCCFCDD"
    )
        port map (
      I0 => \cmd_pipe_plus.mc_we_n_reg[0]\,
      I1 => \cmd_pipe_plus.mc_we_n[0]_i_2_n_0\,
      I2 => \cmd_pipe_plus.mc_we_n_reg[0]_0\,
      I3 => \^q\(1),
      I4 => \^q\(3),
      I5 => \^q\(2),
      O => mc_we_n_ns(0)
    );
\cmd_pipe_plus.mc_we_n[0]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F088F088F088FFFF"
    )
        port map (
      I0 => \^q\(2),
      I1 => \cmd_pipe_plus.mc_we_n_reg[0]_1\,
      I2 => \cmd_pipe_plus.mc_we_n_reg[0]_2\,
      I3 => \^q\(3),
      I4 => \cmd_pipe_plus.mc_ras_n_reg[0]\,
      I5 => \last_master_r_reg[2]_0\,
      O => \cmd_pipe_plus.mc_we_n[0]_i_2_n_0\
    );
\grant_r[0]_i_1__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0202AA0200000000"
    )
        port map (
      I0 => \grant_r[2]_i_2__0_n_0\,
      I1 => \last_master_r[0]_i_1__1_n_0\,
      I2 => \last_master_r[1]_i_1__1_n_0\,
      I3 => \grant_r[3]_i_2__0_n_0\,
      I4 => \grant_r_reg[3]_0\,
      I5 => granted_row_r_reg,
      O => \grant_r[0]_i_1__1_n_0\
    );
\grant_r[1]_i_1__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"100010001000F000"
    )
        port map (
      I0 => \grant_r_reg[3]_0\,
      I1 => granted_row_r_reg,
      I2 => \grant_r[3]_i_3__0_n_0\,
      I3 => \grant_r_reg[3]_1\,
      I4 => \last_master_r[2]_i_1__2_n_0\,
      I5 => \last_master_r[1]_i_1__1_n_0\,
      O => \grant_r[1]_i_1__2_n_0\
    );
\grant_r[2]_i_1__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000020202AA"
    )
        port map (
      I0 => \grant_r[2]_i_2__0_n_0\,
      I1 => granted_row_r_reg,
      I2 => \grant_r_reg[3]_1\,
      I3 => \last_master_r[2]_i_1__2_n_0\,
      I4 => \last_master_r[3]_i_1__1_n_0\,
      I5 => \grant_r[3]_i_2__0_n_0\,
      O => \grant_r[2]_i_1__1_n_0\
    );
\grant_r[2]_i_2__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0777"
    )
        port map (
      I0 => \grant_r_reg[3]_1\,
      I1 => \last_master_r[0]_i_1__1_n_0\,
      I2 => \grant_r_reg[3]_0\,
      I3 => \last_master_r[2]_i_1__2_n_0\,
      O => \grant_r[2]_i_2__0_n_0\
    );
\grant_r[3]_i_1__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"222F000000000000"
    )
        port map (
      I0 => \grant_r[3]_i_2__0_n_0\,
      I1 => \grant_r_reg[3]_1\,
      I2 => \last_master_r[0]_i_1__1_n_0\,
      I3 => \last_master_r[3]_i_1__1_n_0\,
      I4 => \grant_r[3]_i_3__0_n_0\,
      I5 => \grant_r_reg[3]_0\,
      O => \grant_r[3]_i_1__1_n_0\
    );
\grant_r[3]_i_2__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFFEEE"
    )
        port map (
      I0 => \grant_r_reg[3]_2\,
      I1 => \^q\(2),
      I2 => \^q\(0),
      I3 => \cmd_pipe_plus.mc_address_reg[10]\,
      I4 => \^grant_r_reg[1]_0\,
      O => \grant_r[3]_i_2__0_n_0\
    );
\grant_r[3]_i_3__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0BBB"
    )
        port map (
      I0 => \grant_r[3]_i_2__0_n_0\,
      I1 => \last_master_r[1]_i_1__1_n_0\,
      I2 => granted_row_r_reg,
      I3 => \last_master_r[3]_i_1__1_n_0\,
      O => \grant_r[3]_i_3__0_n_0\
    );
\grant_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \last_master_r_reg[3]_0\,
      CE => '1',
      D => \grant_r[0]_i_1__1_n_0\,
      Q => \^q\(0),
      R => '0'
    );
\grant_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \last_master_r_reg[3]_0\,
      CE => '1',
      D => \grant_r[1]_i_1__2_n_0\,
      Q => \^q\(1),
      R => '0'
    );
\grant_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \last_master_r_reg[3]_0\,
      CE => '1',
      D => \grant_r[2]_i_1__1_n_0\,
      Q => \^q\(2),
      R => '0'
    );
\grant_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => \last_master_r_reg[3]_0\,
      CE => '1',
      D => \grant_r[3]_i_1__1_n_0\,
      Q => \^q\(3),
      R => '0'
    );
granted_row_r_i_1: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFFD"
    )
        port map (
      I0 => \grant_r[3]_i_2__0_n_0\,
      I1 => \grant_r_reg[3]_1\,
      I2 => \grant_r_reg[3]_0\,
      I3 => granted_row_r_reg,
      O => granted_row_ns
    );
\i___70_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFF888"
    )
        port map (
      I0 => \^q\(1),
      I1 => \cmd_pipe_plus.mc_we_n_reg[0]_0\,
      I2 => \cmd_pipe_plus.mc_we_n_reg[0]_2\,
      I3 => \^q\(3),
      I4 => \i___70\,
      I5 => inhbt_act_faw_r,
      O => \^grant_r_reg[1]_0\
    );
\i___73_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFF888"
    )
        port map (
      I0 => \^q\(0),
      I1 => \cmd_pipe_plus.mc_address_reg[10]\,
      I2 => \cmd_pipe_plus.mc_we_n_reg[0]_1\,
      I3 => \^q\(2),
      I4 => \i___70\,
      I5 => inhbt_act_faw_r,
      O => \grant_r_reg[0]_1\
    );
\i___79_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000777"
    )
        port map (
      I0 => \^q\(0),
      I1 => act_this_rank_r(0),
      I2 => \^q\(3),
      I3 => act_this_rank_r(3),
      I4 => \i___79_i_2_n_0\,
      O => \^grant_r_reg[0]_2\
    );
\i___79_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F888"
    )
        port map (
      I0 => act_this_rank_r(2),
      I1 => \^q\(2),
      I2 => act_this_rank_r(1),
      I3 => \^q\(1),
      O => \i___79_i_2_n_0\
    );
\inhbt_act_faw.SRLC32E0_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \^grant_r_reg[0]_2\,
      O => act_this_rank
    );
\last_master_r[0]_i_1__1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"00E2"
    )
        port map (
      I0 => last_master_r(0),
      I1 => \last_master_r_reg[2]_0\,
      I2 => \^q\(0),
      I3 => \cmd_pipe_plus.mc_cas_n_reg[0]\,
      O => \last_master_r[0]_i_1__1_n_0\
    );
\last_master_r[1]_i_1__1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"00E2"
    )
        port map (
      I0 => last_master_r(1),
      I1 => \last_master_r_reg[2]_0\,
      I2 => \^q\(1),
      I3 => \cmd_pipe_plus.mc_cas_n_reg[0]\,
      O => \last_master_r[1]_i_1__1_n_0\
    );
\last_master_r[2]_i_1__2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"00E2"
    )
        port map (
      I0 => last_master_r(2),
      I1 => \last_master_r_reg[2]_0\,
      I2 => \^q\(2),
      I3 => \cmd_pipe_plus.mc_cas_n_reg[0]\,
      O => \last_master_r[2]_i_1__2_n_0\
    );
\last_master_r[3]_i_1__1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FEAE"
    )
        port map (
      I0 => \cmd_pipe_plus.mc_cas_n_reg[0]\,
      I1 => last_master_r(3),
      I2 => \last_master_r_reg[2]_0\,
      I3 => \^q\(3),
      O => \last_master_r[3]_i_1__1_n_0\
    );
\last_master_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \last_master_r_reg[3]_0\,
      CE => '1',
      D => \last_master_r[0]_i_1__1_n_0\,
      Q => last_master_r(0),
      R => '0'
    );
\last_master_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \last_master_r_reg[3]_0\,
      CE => '1',
      D => \last_master_r[1]_i_1__1_n_0\,
      Q => last_master_r(1),
      R => '0'
    );
\last_master_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \last_master_r_reg[3]_0\,
      CE => '1',
      D => \last_master_r[2]_i_1__2_n_0\,
      Q => last_master_r(2),
      R => '0'
    );
\last_master_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => \last_master_r_reg[3]_0\,
      CE => '1',
      D => \last_master_r[3]_i_1__1_n_0\,
      Q => last_master_r(3),
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mig_mig_7series_v4_2_tempmon is
  port (
    \out\ : out STD_LOGIC_VECTOR ( 11 downto 0 );
    D : out STD_LOGIC_VECTOR ( 11 downto 0 );
    clk_ref_i : in STD_LOGIC;
    \xadc_supplied_temperature.rst_r1_reg_0\ : in STD_LOGIC;
    \sync_cntr_reg[3]_0\ : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of mig_mig_7series_v4_2_tempmon : entity is "mig_7series_v4_2_tempmon";
end mig_mig_7series_v4_2_tempmon;

architecture STRUCTURE of mig_mig_7series_v4_2_tempmon is
  signal \FSM_onehot_xadc_supplied_temperature.tempmon_state[3]_i_1_n_0\ : STD_LOGIC;
  signal \FSM_onehot_xadc_supplied_temperature.tempmon_state_reg_n_0_[0]\ : STD_LOGIC;
  signal \FSM_onehot_xadc_supplied_temperature.tempmon_state_reg_n_0_[2]\ : STD_LOGIC;
  signal \device_temp_101[11]_i_2_n_0\ : STD_LOGIC;
  signal \device_temp_101[11]_i_4_n_0\ : STD_LOGIC;
  signal \device_temp_101[11]_i_5_n_0\ : STD_LOGIC;
  signal device_temp_lcl : STD_LOGIC_VECTOR ( 11 downto 0 );
  signal device_temp_r : STD_LOGIC_VECTOR ( 11 downto 0 );
  attribute async_reg : string;
  attribute async_reg of device_temp_r : signal is "true";
  signal \device_temp_r[11]_i_1_n_0\ : STD_LOGIC;
  signal device_temp_sync_r1 : STD_LOGIC_VECTOR ( 11 downto 0 );
  attribute async_reg of device_temp_sync_r1 : signal is "true";
  signal device_temp_sync_r2 : STD_LOGIC_VECTOR ( 11 downto 0 );
  attribute async_reg of device_temp_sync_r2 : signal is "true";
  signal device_temp_sync_r3 : STD_LOGIC_VECTOR ( 11 downto 0 );
  attribute async_reg of device_temp_sync_r3 : signal is "true";
  attribute syn_srlstyle : string;
  attribute syn_srlstyle of device_temp_sync_r3 : signal is "registers";
  signal device_temp_sync_r4 : STD_LOGIC_VECTOR ( 11 downto 0 );
  attribute async_reg of device_temp_sync_r4 : signal is "true";
  signal device_temp_sync_r4_neq_r3 : STD_LOGIC;
  signal device_temp_sync_r4_neq_r3_i_2_n_0 : STD_LOGIC;
  signal device_temp_sync_r4_neq_r3_i_3_n_0 : STD_LOGIC;
  signal device_temp_sync_r4_neq_r3_i_4_n_0 : STD_LOGIC;
  signal device_temp_sync_r4_neq_r3_i_5_n_0 : STD_LOGIC;
  signal device_temp_sync_r4_neq_r3_reg_i_1_n_0 : STD_LOGIC;
  signal device_temp_sync_r4_neq_r3_reg_i_1_n_1 : STD_LOGIC;
  signal device_temp_sync_r4_neq_r3_reg_i_1_n_2 : STD_LOGIC;
  signal device_temp_sync_r4_neq_r3_reg_i_1_n_3 : STD_LOGIC;
  signal device_temp_sync_r5 : STD_LOGIC_VECTOR ( 11 downto 0 );
  attribute async_reg of device_temp_sync_r5 : signal is "true";
  signal \p_0_in__0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \p_0_in__1\ : STD_LOGIC_VECTOR ( 10 downto 0 );
  signal sync_cntr0 : STD_LOGIC;
  signal \sync_cntr[2]_i_1_n_0\ : STD_LOGIC;
  signal \sync_cntr[3]_i_2_n_0\ : STD_LOGIC;
  signal sync_cntr_reg : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_tempmon_0/device_temp_low\ : STD_LOGIC;
  signal \xadc_supplied_temperature.rst_r1\ : STD_LOGIC;
  attribute async_reg of \xadc_supplied_temperature.rst_r1\ : signal is "true";
  signal \xadc_supplied_temperature.rst_r2\ : STD_LOGIC;
  attribute async_reg of \xadc_supplied_temperature.rst_r2\ : signal is "true";
  signal \xadc_supplied_temperature.sample_en\ : STD_LOGIC;
  signal \xadc_supplied_temperature.sample_en_i_1_n_0\ : STD_LOGIC;
  signal \xadc_supplied_temperature.sample_en_i_2_n_0\ : STD_LOGIC;
  signal \xadc_supplied_temperature.sample_timer0\ : STD_LOGIC;
  signal \xadc_supplied_temperature.sample_timer[10]_i_3_n_0\ : STD_LOGIC;
  signal \xadc_supplied_temperature.sample_timer_clr\ : STD_LOGIC;
  signal \xadc_supplied_temperature.sample_timer_clr_i_1_n_0\ : STD_LOGIC;
  signal \xadc_supplied_temperature.sample_timer_en\ : STD_LOGIC;
  signal \xadc_supplied_temperature.sample_timer_en_i_1_n_0\ : STD_LOGIC;
  signal \xadc_supplied_temperature.sample_timer_reg\ : STD_LOGIC_VECTOR ( 10 downto 0 );
  signal \xadc_supplied_temperature.temperature\ : STD_LOGIC;
  signal \xadc_supplied_temperature.xadc_den\ : STD_LOGIC;
  signal \xadc_supplied_temperature.xadc_do\ : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal \xadc_supplied_temperature.xadc_do_r\ : STD_LOGIC_VECTOR ( 15 downto 4 );
  signal \xadc_supplied_temperature.xadc_drdy\ : STD_LOGIC;
  signal \xadc_supplied_temperature.xadc_drdy_r\ : STD_LOGIC;
  signal NLW_device_temp_sync_r4_neq_r3_reg_i_1_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \NLW_xadc_supplied_temperature.XADC_inst_BUSY_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_xadc_supplied_temperature.XADC_inst_EOC_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_xadc_supplied_temperature.XADC_inst_EOS_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_xadc_supplied_temperature.XADC_inst_JTAGBUSY_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_xadc_supplied_temperature.XADC_inst_JTAGLOCKED_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_xadc_supplied_temperature.XADC_inst_JTAGMODIFIED_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_xadc_supplied_temperature.XADC_inst_OT_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_xadc_supplied_temperature.XADC_inst_ALM_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \NLW_xadc_supplied_temperature.XADC_inst_CHANNEL_UNCONNECTED\ : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal \NLW_xadc_supplied_temperature.XADC_inst_MUXADDR_UNCONNECTED\ : STD_LOGIC_VECTOR ( 4 downto 0 );
  attribute FSM_ENCODED_STATES : string;
  attribute FSM_ENCODED_STATES of \FSM_onehot_xadc_supplied_temperature.tempmon_state_reg[0]\ : label is "INIT_IDLE:0001,REQUEST_READ_TEMP:1000,WAIT_FOR_READ:0100,READ:0010,";
  attribute FSM_ENCODED_STATES of \FSM_onehot_xadc_supplied_temperature.tempmon_state_reg[1]\ : label is "INIT_IDLE:0001,REQUEST_READ_TEMP:1000,WAIT_FOR_READ:0100,READ:0010,";
  attribute FSM_ENCODED_STATES of \FSM_onehot_xadc_supplied_temperature.tempmon_state_reg[2]\ : label is "INIT_IDLE:0001,REQUEST_READ_TEMP:1000,WAIT_FOR_READ:0100,READ:0010,";
  attribute FSM_ENCODED_STATES of \FSM_onehot_xadc_supplied_temperature.tempmon_state_reg[3]\ : label is "INIT_IDLE:0001,REQUEST_READ_TEMP:1000,WAIT_FOR_READ:0100,READ:0010,";
  attribute ASYNC_REG_boolean : boolean;
  attribute ASYNC_REG_boolean of \device_temp_r_reg[0]\ : label is std.standard.true;
  attribute KEEP : string;
  attribute KEEP of \device_temp_r_reg[0]\ : label is "yes";
  attribute ASYNC_REG_boolean of \device_temp_r_reg[10]\ : label is std.standard.true;
  attribute KEEP of \device_temp_r_reg[10]\ : label is "yes";
  attribute ASYNC_REG_boolean of \device_temp_r_reg[11]\ : label is std.standard.true;
  attribute KEEP of \device_temp_r_reg[11]\ : label is "yes";
  attribute ASYNC_REG_boolean of \device_temp_r_reg[1]\ : label is std.standard.true;
  attribute KEEP of \device_temp_r_reg[1]\ : label is "yes";
  attribute ASYNC_REG_boolean of \device_temp_r_reg[2]\ : label is std.standard.true;
  attribute KEEP of \device_temp_r_reg[2]\ : label is "yes";
  attribute ASYNC_REG_boolean of \device_temp_r_reg[3]\ : label is std.standard.true;
  attribute KEEP of \device_temp_r_reg[3]\ : label is "yes";
  attribute ASYNC_REG_boolean of \device_temp_r_reg[4]\ : label is std.standard.true;
  attribute KEEP of \device_temp_r_reg[4]\ : label is "yes";
  attribute ASYNC_REG_boolean of \device_temp_r_reg[5]\ : label is std.standard.true;
  attribute KEEP of \device_temp_r_reg[5]\ : label is "yes";
  attribute ASYNC_REG_boolean of \device_temp_r_reg[6]\ : label is std.standard.true;
  attribute KEEP of \device_temp_r_reg[6]\ : label is "yes";
  attribute ASYNC_REG_boolean of \device_temp_r_reg[7]\ : label is std.standard.true;
  attribute KEEP of \device_temp_r_reg[7]\ : label is "yes";
  attribute ASYNC_REG_boolean of \device_temp_r_reg[8]\ : label is std.standard.true;
  attribute KEEP of \device_temp_r_reg[8]\ : label is "yes";
  attribute ASYNC_REG_boolean of \device_temp_r_reg[9]\ : label is std.standard.true;
  attribute KEEP of \device_temp_r_reg[9]\ : label is "yes";
  attribute ASYNC_REG_boolean of \device_temp_sync_r1_reg[0]\ : label is std.standard.true;
  attribute KEEP of \device_temp_sync_r1_reg[0]\ : label is "yes";
  attribute ASYNC_REG_boolean of \device_temp_sync_r1_reg[10]\ : label is std.standard.true;
  attribute KEEP of \device_temp_sync_r1_reg[10]\ : label is "yes";
  attribute ASYNC_REG_boolean of \device_temp_sync_r1_reg[11]\ : label is std.standard.true;
  attribute KEEP of \device_temp_sync_r1_reg[11]\ : label is "yes";
  attribute ASYNC_REG_boolean of \device_temp_sync_r1_reg[1]\ : label is std.standard.true;
  attribute KEEP of \device_temp_sync_r1_reg[1]\ : label is "yes";
  attribute ASYNC_REG_boolean of \device_temp_sync_r1_reg[2]\ : label is std.standard.true;
  attribute KEEP of \device_temp_sync_r1_reg[2]\ : label is "yes";
  attribute ASYNC_REG_boolean of \device_temp_sync_r1_reg[3]\ : label is std.standard.true;
  attribute KEEP of \device_temp_sync_r1_reg[3]\ : label is "yes";
  attribute ASYNC_REG_boolean of \device_temp_sync_r1_reg[4]\ : label is std.standard.true;
  attribute KEEP of \device_temp_sync_r1_reg[4]\ : label is "yes";
  attribute ASYNC_REG_boolean of \device_temp_sync_r1_reg[5]\ : label is std.standard.true;
  attribute KEEP of \device_temp_sync_r1_reg[5]\ : label is "yes";
  attribute ASYNC_REG_boolean of \device_temp_sync_r1_reg[6]\ : label is std.standard.true;
  attribute KEEP of \device_temp_sync_r1_reg[6]\ : label is "yes";
  attribute ASYNC_REG_boolean of \device_temp_sync_r1_reg[7]\ : label is std.standard.true;
  attribute KEEP of \device_temp_sync_r1_reg[7]\ : label is "yes";
  attribute ASYNC_REG_boolean of \device_temp_sync_r1_reg[8]\ : label is std.standard.true;
  attribute KEEP of \device_temp_sync_r1_reg[8]\ : label is "yes";
  attribute ASYNC_REG_boolean of \device_temp_sync_r1_reg[9]\ : label is std.standard.true;
  attribute KEEP of \device_temp_sync_r1_reg[9]\ : label is "yes";
  attribute ASYNC_REG_boolean of \device_temp_sync_r2_reg[0]\ : label is std.standard.true;
  attribute KEEP of \device_temp_sync_r2_reg[0]\ : label is "yes";
  attribute ASYNC_REG_boolean of \device_temp_sync_r2_reg[10]\ : label is std.standard.true;
  attribute KEEP of \device_temp_sync_r2_reg[10]\ : label is "yes";
  attribute ASYNC_REG_boolean of \device_temp_sync_r2_reg[11]\ : label is std.standard.true;
  attribute KEEP of \device_temp_sync_r2_reg[11]\ : label is "yes";
  attribute ASYNC_REG_boolean of \device_temp_sync_r2_reg[1]\ : label is std.standard.true;
  attribute KEEP of \device_temp_sync_r2_reg[1]\ : label is "yes";
  attribute ASYNC_REG_boolean of \device_temp_sync_r2_reg[2]\ : label is std.standard.true;
  attribute KEEP of \device_temp_sync_r2_reg[2]\ : label is "yes";
  attribute ASYNC_REG_boolean of \device_temp_sync_r2_reg[3]\ : label is std.standard.true;
  attribute KEEP of \device_temp_sync_r2_reg[3]\ : label is "yes";
  attribute ASYNC_REG_boolean of \device_temp_sync_r2_reg[4]\ : label is std.standard.true;
  attribute KEEP of \device_temp_sync_r2_reg[4]\ : label is "yes";
  attribute ASYNC_REG_boolean of \device_temp_sync_r2_reg[5]\ : label is std.standard.true;
  attribute KEEP of \device_temp_sync_r2_reg[5]\ : label is "yes";
  attribute ASYNC_REG_boolean of \device_temp_sync_r2_reg[6]\ : label is std.standard.true;
  attribute KEEP of \device_temp_sync_r2_reg[6]\ : label is "yes";
  attribute ASYNC_REG_boolean of \device_temp_sync_r2_reg[7]\ : label is std.standard.true;
  attribute KEEP of \device_temp_sync_r2_reg[7]\ : label is "yes";
  attribute ASYNC_REG_boolean of \device_temp_sync_r2_reg[8]\ : label is std.standard.true;
  attribute KEEP of \device_temp_sync_r2_reg[8]\ : label is "yes";
  attribute ASYNC_REG_boolean of \device_temp_sync_r2_reg[9]\ : label is std.standard.true;
  attribute KEEP of \device_temp_sync_r2_reg[9]\ : label is "yes";
  attribute ASYNC_REG_boolean of \device_temp_sync_r3_reg[0]\ : label is std.standard.true;
  attribute KEEP of \device_temp_sync_r3_reg[0]\ : label is "yes";
  attribute syn_srlstyle of \device_temp_sync_r3_reg[0]\ : label is "registers";
  attribute ASYNC_REG_boolean of \device_temp_sync_r3_reg[10]\ : label is std.standard.true;
  attribute KEEP of \device_temp_sync_r3_reg[10]\ : label is "yes";
  attribute syn_srlstyle of \device_temp_sync_r3_reg[10]\ : label is "registers";
  attribute ASYNC_REG_boolean of \device_temp_sync_r3_reg[11]\ : label is std.standard.true;
  attribute KEEP of \device_temp_sync_r3_reg[11]\ : label is "yes";
  attribute syn_srlstyle of \device_temp_sync_r3_reg[11]\ : label is "registers";
  attribute ASYNC_REG_boolean of \device_temp_sync_r3_reg[1]\ : label is std.standard.true;
  attribute KEEP of \device_temp_sync_r3_reg[1]\ : label is "yes";
  attribute syn_srlstyle of \device_temp_sync_r3_reg[1]\ : label is "registers";
  attribute ASYNC_REG_boolean of \device_temp_sync_r3_reg[2]\ : label is std.standard.true;
  attribute KEEP of \device_temp_sync_r3_reg[2]\ : label is "yes";
  attribute syn_srlstyle of \device_temp_sync_r3_reg[2]\ : label is "registers";
  attribute ASYNC_REG_boolean of \device_temp_sync_r3_reg[3]\ : label is std.standard.true;
  attribute KEEP of \device_temp_sync_r3_reg[3]\ : label is "yes";
  attribute syn_srlstyle of \device_temp_sync_r3_reg[3]\ : label is "registers";
  attribute ASYNC_REG_boolean of \device_temp_sync_r3_reg[4]\ : label is std.standard.true;
  attribute KEEP of \device_temp_sync_r3_reg[4]\ : label is "yes";
  attribute syn_srlstyle of \device_temp_sync_r3_reg[4]\ : label is "registers";
  attribute ASYNC_REG_boolean of \device_temp_sync_r3_reg[5]\ : label is std.standard.true;
  attribute KEEP of \device_temp_sync_r3_reg[5]\ : label is "yes";
  attribute syn_srlstyle of \device_temp_sync_r3_reg[5]\ : label is "registers";
  attribute ASYNC_REG_boolean of \device_temp_sync_r3_reg[6]\ : label is std.standard.true;
  attribute KEEP of \device_temp_sync_r3_reg[6]\ : label is "yes";
  attribute syn_srlstyle of \device_temp_sync_r3_reg[6]\ : label is "registers";
  attribute ASYNC_REG_boolean of \device_temp_sync_r3_reg[7]\ : label is std.standard.true;
  attribute KEEP of \device_temp_sync_r3_reg[7]\ : label is "yes";
  attribute syn_srlstyle of \device_temp_sync_r3_reg[7]\ : label is "registers";
  attribute ASYNC_REG_boolean of \device_temp_sync_r3_reg[8]\ : label is std.standard.true;
  attribute KEEP of \device_temp_sync_r3_reg[8]\ : label is "yes";
  attribute syn_srlstyle of \device_temp_sync_r3_reg[8]\ : label is "registers";
  attribute ASYNC_REG_boolean of \device_temp_sync_r3_reg[9]\ : label is std.standard.true;
  attribute KEEP of \device_temp_sync_r3_reg[9]\ : label is "yes";
  attribute syn_srlstyle of \device_temp_sync_r3_reg[9]\ : label is "registers";
  attribute ASYNC_REG_boolean of \device_temp_sync_r4_reg[0]\ : label is std.standard.true;
  attribute KEEP of \device_temp_sync_r4_reg[0]\ : label is "yes";
  attribute ASYNC_REG_boolean of \device_temp_sync_r4_reg[10]\ : label is std.standard.true;
  attribute KEEP of \device_temp_sync_r4_reg[10]\ : label is "yes";
  attribute ASYNC_REG_boolean of \device_temp_sync_r4_reg[11]\ : label is std.standard.true;
  attribute KEEP of \device_temp_sync_r4_reg[11]\ : label is "yes";
  attribute ASYNC_REG_boolean of \device_temp_sync_r4_reg[1]\ : label is std.standard.true;
  attribute KEEP of \device_temp_sync_r4_reg[1]\ : label is "yes";
  attribute ASYNC_REG_boolean of \device_temp_sync_r4_reg[2]\ : label is std.standard.true;
  attribute KEEP of \device_temp_sync_r4_reg[2]\ : label is "yes";
  attribute ASYNC_REG_boolean of \device_temp_sync_r4_reg[3]\ : label is std.standard.true;
  attribute KEEP of \device_temp_sync_r4_reg[3]\ : label is "yes";
  attribute ASYNC_REG_boolean of \device_temp_sync_r4_reg[4]\ : label is std.standard.true;
  attribute KEEP of \device_temp_sync_r4_reg[4]\ : label is "yes";
  attribute ASYNC_REG_boolean of \device_temp_sync_r4_reg[5]\ : label is std.standard.true;
  attribute KEEP of \device_temp_sync_r4_reg[5]\ : label is "yes";
  attribute ASYNC_REG_boolean of \device_temp_sync_r4_reg[6]\ : label is std.standard.true;
  attribute KEEP of \device_temp_sync_r4_reg[6]\ : label is "yes";
  attribute ASYNC_REG_boolean of \device_temp_sync_r4_reg[7]\ : label is std.standard.true;
  attribute KEEP of \device_temp_sync_r4_reg[7]\ : label is "yes";
  attribute ASYNC_REG_boolean of \device_temp_sync_r4_reg[8]\ : label is std.standard.true;
  attribute KEEP of \device_temp_sync_r4_reg[8]\ : label is "yes";
  attribute ASYNC_REG_boolean of \device_temp_sync_r4_reg[9]\ : label is std.standard.true;
  attribute KEEP of \device_temp_sync_r4_reg[9]\ : label is "yes";
  attribute ASYNC_REG_boolean of \device_temp_sync_r5_reg[0]\ : label is std.standard.true;
  attribute KEEP of \device_temp_sync_r5_reg[0]\ : label is "yes";
  attribute ASYNC_REG_boolean of \device_temp_sync_r5_reg[10]\ : label is std.standard.true;
  attribute KEEP of \device_temp_sync_r5_reg[10]\ : label is "yes";
  attribute ASYNC_REG_boolean of \device_temp_sync_r5_reg[11]\ : label is std.standard.true;
  attribute KEEP of \device_temp_sync_r5_reg[11]\ : label is "yes";
  attribute ASYNC_REG_boolean of \device_temp_sync_r5_reg[1]\ : label is std.standard.true;
  attribute KEEP of \device_temp_sync_r5_reg[1]\ : label is "yes";
  attribute ASYNC_REG_boolean of \device_temp_sync_r5_reg[2]\ : label is std.standard.true;
  attribute KEEP of \device_temp_sync_r5_reg[2]\ : label is "yes";
  attribute ASYNC_REG_boolean of \device_temp_sync_r5_reg[3]\ : label is std.standard.true;
  attribute KEEP of \device_temp_sync_r5_reg[3]\ : label is "yes";
  attribute ASYNC_REG_boolean of \device_temp_sync_r5_reg[4]\ : label is std.standard.true;
  attribute KEEP of \device_temp_sync_r5_reg[4]\ : label is "yes";
  attribute ASYNC_REG_boolean of \device_temp_sync_r5_reg[5]\ : label is std.standard.true;
  attribute KEEP of \device_temp_sync_r5_reg[5]\ : label is "yes";
  attribute ASYNC_REG_boolean of \device_temp_sync_r5_reg[6]\ : label is std.standard.true;
  attribute KEEP of \device_temp_sync_r5_reg[6]\ : label is "yes";
  attribute ASYNC_REG_boolean of \device_temp_sync_r5_reg[7]\ : label is std.standard.true;
  attribute KEEP of \device_temp_sync_r5_reg[7]\ : label is "yes";
  attribute ASYNC_REG_boolean of \device_temp_sync_r5_reg[8]\ : label is std.standard.true;
  attribute KEEP of \device_temp_sync_r5_reg[8]\ : label is "yes";
  attribute ASYNC_REG_boolean of \device_temp_sync_r5_reg[9]\ : label is std.standard.true;
  attribute KEEP of \device_temp_sync_r5_reg[9]\ : label is "yes";
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \sync_cntr[0]_i_1\ : label is "soft_lutpair5";
  attribute SOFT_HLUTNM of \sync_cntr[1]_i_1\ : label is "soft_lutpair5";
  attribute SOFT_HLUTNM of \sync_cntr[2]_i_1\ : label is "soft_lutpair2";
  attribute SOFT_HLUTNM of \sync_cntr[3]_i_3\ : label is "soft_lutpair2";
  attribute BOX_TYPE : string;
  attribute BOX_TYPE of \xadc_supplied_temperature.XADC_inst\ : label is "PRIMITIVE";
  attribute ASYNC_REG_boolean of \xadc_supplied_temperature.rst_r1_reg\ : label is std.standard.true;
  attribute KEEP of \xadc_supplied_temperature.rst_r1_reg\ : label is "yes";
  attribute ASYNC_REG_boolean of \xadc_supplied_temperature.rst_r2_reg\ : label is std.standard.true;
  attribute KEEP of \xadc_supplied_temperature.rst_r2_reg\ : label is "yes";
  attribute SOFT_HLUTNM of \xadc_supplied_temperature.sample_timer[1]_i_1\ : label is "soft_lutpair3";
  attribute SOFT_HLUTNM of \xadc_supplied_temperature.sample_timer[2]_i_1\ : label is "soft_lutpair3";
  attribute SOFT_HLUTNM of \xadc_supplied_temperature.sample_timer[3]_i_1\ : label is "soft_lutpair0";
  attribute SOFT_HLUTNM of \xadc_supplied_temperature.sample_timer[4]_i_1\ : label is "soft_lutpair0";
  attribute SOFT_HLUTNM of \xadc_supplied_temperature.sample_timer[6]_i_1\ : label is "soft_lutpair4";
  attribute SOFT_HLUTNM of \xadc_supplied_temperature.sample_timer[7]_i_1\ : label is "soft_lutpair4";
  attribute SOFT_HLUTNM of \xadc_supplied_temperature.sample_timer[8]_i_1\ : label is "soft_lutpair1";
  attribute SOFT_HLUTNM of \xadc_supplied_temperature.sample_timer[9]_i_1\ : label is "soft_lutpair1";
begin
  \out\(11 downto 0) <= device_temp_r(11 downto 0);
\FSM_onehot_xadc_supplied_temperature.tempmon_state[3]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFEEEFEEEFEEE"
    )
        port map (
      I0 => \xadc_supplied_temperature.temperature\,
      I1 => \xadc_supplied_temperature.sample_timer_clr\,
      I2 => \FSM_onehot_xadc_supplied_temperature.tempmon_state_reg_n_0_[0]\,
      I3 => \xadc_supplied_temperature.sample_en\,
      I4 => \FSM_onehot_xadc_supplied_temperature.tempmon_state_reg_n_0_[2]\,
      I5 => \xadc_supplied_temperature.xadc_drdy_r\,
      O => \FSM_onehot_xadc_supplied_temperature.tempmon_state[3]_i_1_n_0\
    );
\FSM_onehot_xadc_supplied_temperature.tempmon_state_reg[0]\: unisim.vcomponents.FDSE
    generic map(
      INIT => '1'
    )
        port map (
      C => clk_ref_i,
      CE => \FSM_onehot_xadc_supplied_temperature.tempmon_state[3]_i_1_n_0\,
      D => \xadc_supplied_temperature.temperature\,
      Q => \FSM_onehot_xadc_supplied_temperature.tempmon_state_reg_n_0_[0]\,
      S => \xadc_supplied_temperature.rst_r2\
    );
\FSM_onehot_xadc_supplied_temperature.tempmon_state_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk_ref_i,
      CE => \FSM_onehot_xadc_supplied_temperature.tempmon_state[3]_i_1_n_0\,
      D => \FSM_onehot_xadc_supplied_temperature.tempmon_state_reg_n_0_[2]\,
      Q => \xadc_supplied_temperature.temperature\,
      R => \xadc_supplied_temperature.rst_r2\
    );
\FSM_onehot_xadc_supplied_temperature.tempmon_state_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk_ref_i,
      CE => \FSM_onehot_xadc_supplied_temperature.tempmon_state[3]_i_1_n_0\,
      D => \xadc_supplied_temperature.sample_timer_clr\,
      Q => \FSM_onehot_xadc_supplied_temperature.tempmon_state_reg_n_0_[2]\,
      R => \xadc_supplied_temperature.rst_r2\
    );
\FSM_onehot_xadc_supplied_temperature.tempmon_state_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk_ref_i,
      CE => \FSM_onehot_xadc_supplied_temperature.tempmon_state[3]_i_1_n_0\,
      D => \FSM_onehot_xadc_supplied_temperature.tempmon_state_reg_n_0_[0]\,
      Q => \xadc_supplied_temperature.sample_timer_clr\,
      R => \xadc_supplied_temperature.rst_r2\
    );
\device_temp_101[0]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0700"
    )
        port map (
      I0 => device_temp_r(10),
      I1 => \device_temp_101[11]_i_2_n_0\,
      I2 => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_tempmon_0/device_temp_low\,
      I3 => device_temp_r(0),
      O => D(0)
    );
\device_temp_101[10]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"8A"
    )
        port map (
      I0 => device_temp_r(10),
      I1 => \device_temp_101[11]_i_2_n_0\,
      I2 => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_tempmon_0/device_temp_low\,
      O => D(10)
    );
\device_temp_101[11]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFF8"
    )
        port map (
      I0 => device_temp_r(10),
      I1 => \device_temp_101[11]_i_2_n_0\,
      I2 => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_tempmon_0/device_temp_low\,
      I3 => device_temp_r(11),
      O => D(11)
    );
\device_temp_101[11]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAAAAAA88888"
    )
        port map (
      I0 => device_temp_r(11),
      I1 => device_temp_r(9),
      I2 => device_temp_r(6),
      I3 => \device_temp_101[11]_i_4_n_0\,
      I4 => device_temp_r(7),
      I5 => device_temp_r(8),
      O => \device_temp_101[11]_i_2_n_0\
    );
\device_temp_101[11]_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0100FFFF"
    )
        port map (
      I0 => device_temp_r(8),
      I1 => device_temp_r(10),
      I2 => device_temp_r(9),
      I3 => \device_temp_101[11]_i_5_n_0\,
      I4 => device_temp_r(11),
      O => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_tempmon_0/device_temp_low\
    );
\device_temp_101[11]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAAAAAA88888"
    )
        port map (
      I0 => device_temp_r(5),
      I1 => device_temp_r(4),
      I2 => device_temp_r(1),
      I3 => device_temp_r(0),
      I4 => device_temp_r(2),
      I5 => device_temp_r(3),
      O => \device_temp_101[11]_i_4_n_0\
    );
\device_temp_101[11]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00155555FFFFFFFF"
    )
        port map (
      I0 => device_temp_r(6),
      I1 => device_temp_r(2),
      I2 => device_temp_r(3),
      I3 => device_temp_r(4),
      I4 => device_temp_r(5),
      I5 => device_temp_r(7),
      O => \device_temp_101[11]_i_5_n_0\
    );
\device_temp_101[1]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0700"
    )
        port map (
      I0 => device_temp_r(10),
      I1 => \device_temp_101[11]_i_2_n_0\,
      I2 => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_tempmon_0/device_temp_low\,
      I3 => device_temp_r(1),
      O => D(1)
    );
\device_temp_101[2]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFF8"
    )
        port map (
      I0 => device_temp_r(10),
      I1 => \device_temp_101[11]_i_2_n_0\,
      I2 => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_tempmon_0/device_temp_low\,
      I3 => device_temp_r(2),
      O => D(2)
    );
\device_temp_101[3]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F7F0"
    )
        port map (
      I0 => device_temp_r(10),
      I1 => \device_temp_101[11]_i_2_n_0\,
      I2 => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_tempmon_0/device_temp_low\,
      I3 => device_temp_r(3),
      O => D(3)
    );
\device_temp_101[4]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0700"
    )
        port map (
      I0 => device_temp_r(10),
      I1 => \device_temp_101[11]_i_2_n_0\,
      I2 => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_tempmon_0/device_temp_low\,
      I3 => device_temp_r(4),
      O => D(4)
    );
\device_temp_101[5]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFF8"
    )
        port map (
      I0 => device_temp_r(10),
      I1 => \device_temp_101[11]_i_2_n_0\,
      I2 => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_tempmon_0/device_temp_low\,
      I3 => device_temp_r(5),
      O => D(5)
    );
\device_temp_101[6]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0700"
    )
        port map (
      I0 => device_temp_r(10),
      I1 => \device_temp_101[11]_i_2_n_0\,
      I2 => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_tempmon_0/device_temp_low\,
      I3 => device_temp_r(6),
      O => D(6)
    );
\device_temp_101[7]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFF8"
    )
        port map (
      I0 => device_temp_r(10),
      I1 => \device_temp_101[11]_i_2_n_0\,
      I2 => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_tempmon_0/device_temp_low\,
      I3 => device_temp_r(7),
      O => D(7)
    );
\device_temp_101[8]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0700"
    )
        port map (
      I0 => device_temp_r(10),
      I1 => \device_temp_101[11]_i_2_n_0\,
      I2 => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_tempmon_0/device_temp_low\,
      I3 => device_temp_r(8),
      O => D(8)
    );
\device_temp_101[9]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0700"
    )
        port map (
      I0 => device_temp_r(10),
      I1 => \device_temp_101[11]_i_2_n_0\,
      I2 => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_tempmon_0/device_temp_low\,
      I3 => device_temp_r(9),
      O => D(9)
    );
\device_temp_r[11]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8000"
    )
        port map (
      I0 => sync_cntr_reg(1),
      I1 => sync_cntr_reg(0),
      I2 => sync_cntr_reg(3),
      I3 => sync_cntr_reg(2),
      O => \device_temp_r[11]_i_1_n_0\
    );
\device_temp_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \sync_cntr_reg[3]_0\,
      CE => \device_temp_r[11]_i_1_n_0\,
      D => device_temp_sync_r5(0),
      Q => device_temp_r(0),
      R => '0'
    );
\device_temp_r_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => \sync_cntr_reg[3]_0\,
      CE => \device_temp_r[11]_i_1_n_0\,
      D => device_temp_sync_r5(10),
      Q => device_temp_r(10),
      R => '0'
    );
\device_temp_r_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => \sync_cntr_reg[3]_0\,
      CE => \device_temp_r[11]_i_1_n_0\,
      D => device_temp_sync_r5(11),
      Q => device_temp_r(11),
      R => '0'
    );
\device_temp_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \sync_cntr_reg[3]_0\,
      CE => \device_temp_r[11]_i_1_n_0\,
      D => device_temp_sync_r5(1),
      Q => device_temp_r(1),
      R => '0'
    );
\device_temp_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \sync_cntr_reg[3]_0\,
      CE => \device_temp_r[11]_i_1_n_0\,
      D => device_temp_sync_r5(2),
      Q => device_temp_r(2),
      R => '0'
    );
\device_temp_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => \sync_cntr_reg[3]_0\,
      CE => \device_temp_r[11]_i_1_n_0\,
      D => device_temp_sync_r5(3),
      Q => device_temp_r(3),
      R => '0'
    );
\device_temp_r_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => \sync_cntr_reg[3]_0\,
      CE => \device_temp_r[11]_i_1_n_0\,
      D => device_temp_sync_r5(4),
      Q => device_temp_r(4),
      R => '0'
    );
\device_temp_r_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => \sync_cntr_reg[3]_0\,
      CE => \device_temp_r[11]_i_1_n_0\,
      D => device_temp_sync_r5(5),
      Q => device_temp_r(5),
      R => '0'
    );
\device_temp_r_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => \sync_cntr_reg[3]_0\,
      CE => \device_temp_r[11]_i_1_n_0\,
      D => device_temp_sync_r5(6),
      Q => device_temp_r(6),
      R => '0'
    );
\device_temp_r_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => \sync_cntr_reg[3]_0\,
      CE => \device_temp_r[11]_i_1_n_0\,
      D => device_temp_sync_r5(7),
      Q => device_temp_r(7),
      R => '0'
    );
\device_temp_r_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => \sync_cntr_reg[3]_0\,
      CE => \device_temp_r[11]_i_1_n_0\,
      D => device_temp_sync_r5(8),
      Q => device_temp_r(8),
      R => '0'
    );
\device_temp_r_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => \sync_cntr_reg[3]_0\,
      CE => \device_temp_r[11]_i_1_n_0\,
      D => device_temp_sync_r5(9),
      Q => device_temp_r(9),
      R => '0'
    );
\device_temp_sync_r1_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \sync_cntr_reg[3]_0\,
      CE => '1',
      D => device_temp_lcl(0),
      Q => device_temp_sync_r1(0),
      R => '0'
    );
\device_temp_sync_r1_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => \sync_cntr_reg[3]_0\,
      CE => '1',
      D => device_temp_lcl(10),
      Q => device_temp_sync_r1(10),
      R => '0'
    );
\device_temp_sync_r1_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => \sync_cntr_reg[3]_0\,
      CE => '1',
      D => device_temp_lcl(11),
      Q => device_temp_sync_r1(11),
      R => '0'
    );
\device_temp_sync_r1_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \sync_cntr_reg[3]_0\,
      CE => '1',
      D => device_temp_lcl(1),
      Q => device_temp_sync_r1(1),
      R => '0'
    );
\device_temp_sync_r1_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \sync_cntr_reg[3]_0\,
      CE => '1',
      D => device_temp_lcl(2),
      Q => device_temp_sync_r1(2),
      R => '0'
    );
\device_temp_sync_r1_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => \sync_cntr_reg[3]_0\,
      CE => '1',
      D => device_temp_lcl(3),
      Q => device_temp_sync_r1(3),
      R => '0'
    );
\device_temp_sync_r1_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => \sync_cntr_reg[3]_0\,
      CE => '1',
      D => device_temp_lcl(4),
      Q => device_temp_sync_r1(4),
      R => '0'
    );
\device_temp_sync_r1_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => \sync_cntr_reg[3]_0\,
      CE => '1',
      D => device_temp_lcl(5),
      Q => device_temp_sync_r1(5),
      R => '0'
    );
\device_temp_sync_r1_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => \sync_cntr_reg[3]_0\,
      CE => '1',
      D => device_temp_lcl(6),
      Q => device_temp_sync_r1(6),
      R => '0'
    );
\device_temp_sync_r1_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => \sync_cntr_reg[3]_0\,
      CE => '1',
      D => device_temp_lcl(7),
      Q => device_temp_sync_r1(7),
      R => '0'
    );
\device_temp_sync_r1_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => \sync_cntr_reg[3]_0\,
      CE => '1',
      D => device_temp_lcl(8),
      Q => device_temp_sync_r1(8),
      R => '0'
    );
\device_temp_sync_r1_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => \sync_cntr_reg[3]_0\,
      CE => '1',
      D => device_temp_lcl(9),
      Q => device_temp_sync_r1(9),
      R => '0'
    );
\device_temp_sync_r2_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \sync_cntr_reg[3]_0\,
      CE => '1',
      D => device_temp_sync_r1(0),
      Q => device_temp_sync_r2(0),
      R => '0'
    );
\device_temp_sync_r2_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => \sync_cntr_reg[3]_0\,
      CE => '1',
      D => device_temp_sync_r1(10),
      Q => device_temp_sync_r2(10),
      R => '0'
    );
\device_temp_sync_r2_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => \sync_cntr_reg[3]_0\,
      CE => '1',
      D => device_temp_sync_r1(11),
      Q => device_temp_sync_r2(11),
      R => '0'
    );
\device_temp_sync_r2_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \sync_cntr_reg[3]_0\,
      CE => '1',
      D => device_temp_sync_r1(1),
      Q => device_temp_sync_r2(1),
      R => '0'
    );
\device_temp_sync_r2_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \sync_cntr_reg[3]_0\,
      CE => '1',
      D => device_temp_sync_r1(2),
      Q => device_temp_sync_r2(2),
      R => '0'
    );
\device_temp_sync_r2_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => \sync_cntr_reg[3]_0\,
      CE => '1',
      D => device_temp_sync_r1(3),
      Q => device_temp_sync_r2(3),
      R => '0'
    );
\device_temp_sync_r2_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => \sync_cntr_reg[3]_0\,
      CE => '1',
      D => device_temp_sync_r1(4),
      Q => device_temp_sync_r2(4),
      R => '0'
    );
\device_temp_sync_r2_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => \sync_cntr_reg[3]_0\,
      CE => '1',
      D => device_temp_sync_r1(5),
      Q => device_temp_sync_r2(5),
      R => '0'
    );
\device_temp_sync_r2_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => \sync_cntr_reg[3]_0\,
      CE => '1',
      D => device_temp_sync_r1(6),
      Q => device_temp_sync_r2(6),
      R => '0'
    );
\device_temp_sync_r2_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => \sync_cntr_reg[3]_0\,
      CE => '1',
      D => device_temp_sync_r1(7),
      Q => device_temp_sync_r2(7),
      R => '0'
    );
\device_temp_sync_r2_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => \sync_cntr_reg[3]_0\,
      CE => '1',
      D => device_temp_sync_r1(8),
      Q => device_temp_sync_r2(8),
      R => '0'
    );
\device_temp_sync_r2_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => \sync_cntr_reg[3]_0\,
      CE => '1',
      D => device_temp_sync_r1(9),
      Q => device_temp_sync_r2(9),
      R => '0'
    );
\device_temp_sync_r3_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \sync_cntr_reg[3]_0\,
      CE => '1',
      D => device_temp_sync_r2(0),
      Q => device_temp_sync_r3(0),
      R => '0'
    );
\device_temp_sync_r3_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => \sync_cntr_reg[3]_0\,
      CE => '1',
      D => device_temp_sync_r2(10),
      Q => device_temp_sync_r3(10),
      R => '0'
    );
\device_temp_sync_r3_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => \sync_cntr_reg[3]_0\,
      CE => '1',
      D => device_temp_sync_r2(11),
      Q => device_temp_sync_r3(11),
      R => '0'
    );
\device_temp_sync_r3_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \sync_cntr_reg[3]_0\,
      CE => '1',
      D => device_temp_sync_r2(1),
      Q => device_temp_sync_r3(1),
      R => '0'
    );
\device_temp_sync_r3_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \sync_cntr_reg[3]_0\,
      CE => '1',
      D => device_temp_sync_r2(2),
      Q => device_temp_sync_r3(2),
      R => '0'
    );
\device_temp_sync_r3_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => \sync_cntr_reg[3]_0\,
      CE => '1',
      D => device_temp_sync_r2(3),
      Q => device_temp_sync_r3(3),
      R => '0'
    );
\device_temp_sync_r3_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => \sync_cntr_reg[3]_0\,
      CE => '1',
      D => device_temp_sync_r2(4),
      Q => device_temp_sync_r3(4),
      R => '0'
    );
\device_temp_sync_r3_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => \sync_cntr_reg[3]_0\,
      CE => '1',
      D => device_temp_sync_r2(5),
      Q => device_temp_sync_r3(5),
      R => '0'
    );
\device_temp_sync_r3_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => \sync_cntr_reg[3]_0\,
      CE => '1',
      D => device_temp_sync_r2(6),
      Q => device_temp_sync_r3(6),
      R => '0'
    );
\device_temp_sync_r3_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => \sync_cntr_reg[3]_0\,
      CE => '1',
      D => device_temp_sync_r2(7),
      Q => device_temp_sync_r3(7),
      R => '0'
    );
\device_temp_sync_r3_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => \sync_cntr_reg[3]_0\,
      CE => '1',
      D => device_temp_sync_r2(8),
      Q => device_temp_sync_r3(8),
      R => '0'
    );
\device_temp_sync_r3_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => \sync_cntr_reg[3]_0\,
      CE => '1',
      D => device_temp_sync_r2(9),
      Q => device_temp_sync_r3(9),
      R => '0'
    );
device_temp_sync_r4_neq_r3_i_2: unisim.vcomponents.LUT6
    generic map(
      INIT => X"9009000000009009"
    )
        port map (
      I0 => device_temp_sync_r4(9),
      I1 => device_temp_sync_r3(9),
      I2 => device_temp_sync_r3(11),
      I3 => device_temp_sync_r4(11),
      I4 => device_temp_sync_r3(10),
      I5 => device_temp_sync_r4(10),
      O => device_temp_sync_r4_neq_r3_i_2_n_0
    );
device_temp_sync_r4_neq_r3_i_3: unisim.vcomponents.LUT6
    generic map(
      INIT => X"9009000000009009"
    )
        port map (
      I0 => device_temp_sync_r4(6),
      I1 => device_temp_sync_r3(6),
      I2 => device_temp_sync_r3(8),
      I3 => device_temp_sync_r4(8),
      I4 => device_temp_sync_r3(7),
      I5 => device_temp_sync_r4(7),
      O => device_temp_sync_r4_neq_r3_i_3_n_0
    );
device_temp_sync_r4_neq_r3_i_4: unisim.vcomponents.LUT6
    generic map(
      INIT => X"9009000000009009"
    )
        port map (
      I0 => device_temp_sync_r4(3),
      I1 => device_temp_sync_r3(3),
      I2 => device_temp_sync_r3(5),
      I3 => device_temp_sync_r4(5),
      I4 => device_temp_sync_r3(4),
      I5 => device_temp_sync_r4(4),
      O => device_temp_sync_r4_neq_r3_i_4_n_0
    );
device_temp_sync_r4_neq_r3_i_5: unisim.vcomponents.LUT6
    generic map(
      INIT => X"9009000000009009"
    )
        port map (
      I0 => device_temp_sync_r4(0),
      I1 => device_temp_sync_r3(0),
      I2 => device_temp_sync_r3(2),
      I3 => device_temp_sync_r4(2),
      I4 => device_temp_sync_r3(1),
      I5 => device_temp_sync_r4(1),
      O => device_temp_sync_r4_neq_r3_i_5_n_0
    );
device_temp_sync_r4_neq_r3_reg: unisim.vcomponents.FDRE
     port map (
      C => \sync_cntr_reg[3]_0\,
      CE => '1',
      D => device_temp_sync_r4_neq_r3_reg_i_1_n_0,
      Q => device_temp_sync_r4_neq_r3,
      R => '0'
    );
device_temp_sync_r4_neq_r3_reg_i_1: unisim.vcomponents.CARRY4
     port map (
      CI => '0',
      CO(3) => device_temp_sync_r4_neq_r3_reg_i_1_n_0,
      CO(2) => device_temp_sync_r4_neq_r3_reg_i_1_n_1,
      CO(1) => device_temp_sync_r4_neq_r3_reg_i_1_n_2,
      CO(0) => device_temp_sync_r4_neq_r3_reg_i_1_n_3,
      CYINIT => '0',
      DI(3 downto 0) => B"1111",
      O(3 downto 0) => NLW_device_temp_sync_r4_neq_r3_reg_i_1_O_UNCONNECTED(3 downto 0),
      S(3) => device_temp_sync_r4_neq_r3_i_2_n_0,
      S(2) => device_temp_sync_r4_neq_r3_i_3_n_0,
      S(1) => device_temp_sync_r4_neq_r3_i_4_n_0,
      S(0) => device_temp_sync_r4_neq_r3_i_5_n_0
    );
\device_temp_sync_r4_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \sync_cntr_reg[3]_0\,
      CE => '1',
      D => device_temp_sync_r3(0),
      Q => device_temp_sync_r4(0),
      R => '0'
    );
\device_temp_sync_r4_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => \sync_cntr_reg[3]_0\,
      CE => '1',
      D => device_temp_sync_r3(10),
      Q => device_temp_sync_r4(10),
      R => '0'
    );
\device_temp_sync_r4_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => \sync_cntr_reg[3]_0\,
      CE => '1',
      D => device_temp_sync_r3(11),
      Q => device_temp_sync_r4(11),
      R => '0'
    );
\device_temp_sync_r4_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \sync_cntr_reg[3]_0\,
      CE => '1',
      D => device_temp_sync_r3(1),
      Q => device_temp_sync_r4(1),
      R => '0'
    );
\device_temp_sync_r4_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \sync_cntr_reg[3]_0\,
      CE => '1',
      D => device_temp_sync_r3(2),
      Q => device_temp_sync_r4(2),
      R => '0'
    );
\device_temp_sync_r4_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => \sync_cntr_reg[3]_0\,
      CE => '1',
      D => device_temp_sync_r3(3),
      Q => device_temp_sync_r4(3),
      R => '0'
    );
\device_temp_sync_r4_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => \sync_cntr_reg[3]_0\,
      CE => '1',
      D => device_temp_sync_r3(4),
      Q => device_temp_sync_r4(4),
      R => '0'
    );
\device_temp_sync_r4_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => \sync_cntr_reg[3]_0\,
      CE => '1',
      D => device_temp_sync_r3(5),
      Q => device_temp_sync_r4(5),
      R => '0'
    );
\device_temp_sync_r4_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => \sync_cntr_reg[3]_0\,
      CE => '1',
      D => device_temp_sync_r3(6),
      Q => device_temp_sync_r4(6),
      R => '0'
    );
\device_temp_sync_r4_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => \sync_cntr_reg[3]_0\,
      CE => '1',
      D => device_temp_sync_r3(7),
      Q => device_temp_sync_r4(7),
      R => '0'
    );
\device_temp_sync_r4_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => \sync_cntr_reg[3]_0\,
      CE => '1',
      D => device_temp_sync_r3(8),
      Q => device_temp_sync_r4(8),
      R => '0'
    );
\device_temp_sync_r4_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => \sync_cntr_reg[3]_0\,
      CE => '1',
      D => device_temp_sync_r3(9),
      Q => device_temp_sync_r4(9),
      R => '0'
    );
\device_temp_sync_r5_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \sync_cntr_reg[3]_0\,
      CE => '1',
      D => device_temp_sync_r4(0),
      Q => device_temp_sync_r5(0),
      R => '0'
    );
\device_temp_sync_r5_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => \sync_cntr_reg[3]_0\,
      CE => '1',
      D => device_temp_sync_r4(10),
      Q => device_temp_sync_r5(10),
      R => '0'
    );
\device_temp_sync_r5_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => \sync_cntr_reg[3]_0\,
      CE => '1',
      D => device_temp_sync_r4(11),
      Q => device_temp_sync_r5(11),
      R => '0'
    );
\device_temp_sync_r5_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \sync_cntr_reg[3]_0\,
      CE => '1',
      D => device_temp_sync_r4(1),
      Q => device_temp_sync_r5(1),
      R => '0'
    );
\device_temp_sync_r5_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \sync_cntr_reg[3]_0\,
      CE => '1',
      D => device_temp_sync_r4(2),
      Q => device_temp_sync_r5(2),
      R => '0'
    );
\device_temp_sync_r5_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => \sync_cntr_reg[3]_0\,
      CE => '1',
      D => device_temp_sync_r4(3),
      Q => device_temp_sync_r5(3),
      R => '0'
    );
\device_temp_sync_r5_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => \sync_cntr_reg[3]_0\,
      CE => '1',
      D => device_temp_sync_r4(4),
      Q => device_temp_sync_r5(4),
      R => '0'
    );
\device_temp_sync_r5_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => \sync_cntr_reg[3]_0\,
      CE => '1',
      D => device_temp_sync_r4(5),
      Q => device_temp_sync_r5(5),
      R => '0'
    );
\device_temp_sync_r5_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => \sync_cntr_reg[3]_0\,
      CE => '1',
      D => device_temp_sync_r4(6),
      Q => device_temp_sync_r5(6),
      R => '0'
    );
\device_temp_sync_r5_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => \sync_cntr_reg[3]_0\,
      CE => '1',
      D => device_temp_sync_r4(7),
      Q => device_temp_sync_r5(7),
      R => '0'
    );
\device_temp_sync_r5_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => \sync_cntr_reg[3]_0\,
      CE => '1',
      D => device_temp_sync_r4(8),
      Q => device_temp_sync_r5(8),
      R => '0'
    );
\device_temp_sync_r5_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => \sync_cntr_reg[3]_0\,
      CE => '1',
      D => device_temp_sync_r4(9),
      Q => device_temp_sync_r5(9),
      R => '0'
    );
\sync_cntr[0]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => sync_cntr_reg(0),
      O => \p_0_in__0\(0)
    );
\sync_cntr[1]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => sync_cntr_reg(0),
      I1 => sync_cntr_reg(1),
      O => \p_0_in__0\(1)
    );
\sync_cntr[2]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"78"
    )
        port map (
      I0 => sync_cntr_reg(1),
      I1 => sync_cntr_reg(0),
      I2 => sync_cntr_reg(2),
      O => \sync_cntr[2]_i_1_n_0\
    );
\sync_cntr[3]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => \xadc_supplied_temperature.rst_r1_reg_0\,
      I1 => device_temp_sync_r4_neq_r3,
      O => sync_cntr0
    );
\sync_cntr[3]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7FFF"
    )
        port map (
      I0 => sync_cntr_reg(2),
      I1 => sync_cntr_reg(3),
      I2 => sync_cntr_reg(0),
      I3 => sync_cntr_reg(1),
      O => \sync_cntr[3]_i_2_n_0\
    );
\sync_cntr[3]_i_3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7F80"
    )
        port map (
      I0 => sync_cntr_reg(0),
      I1 => sync_cntr_reg(1),
      I2 => sync_cntr_reg(2),
      I3 => sync_cntr_reg(3),
      O => \p_0_in__0\(3)
    );
\sync_cntr_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \sync_cntr_reg[3]_0\,
      CE => \sync_cntr[3]_i_2_n_0\,
      D => \p_0_in__0\(0),
      Q => sync_cntr_reg(0),
      R => sync_cntr0
    );
\sync_cntr_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \sync_cntr_reg[3]_0\,
      CE => \sync_cntr[3]_i_2_n_0\,
      D => \p_0_in__0\(1),
      Q => sync_cntr_reg(1),
      R => sync_cntr0
    );
\sync_cntr_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \sync_cntr_reg[3]_0\,
      CE => \sync_cntr[3]_i_2_n_0\,
      D => \sync_cntr[2]_i_1_n_0\,
      Q => sync_cntr_reg(2),
      R => sync_cntr0
    );
\sync_cntr_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \sync_cntr_reg[3]_0\,
      CE => \sync_cntr[3]_i_2_n_0\,
      D => \p_0_in__0\(3),
      Q => sync_cntr_reg(3),
      R => sync_cntr0
    );
\xadc_supplied_temperature.XADC_inst\: unisim.vcomponents.XADC
    generic map(
      INIT_40 => X"1000",
      INIT_41 => X"2FFF",
      INIT_42 => X"0800",
      INIT_43 => X"0000",
      INIT_44 => X"0000",
      INIT_45 => X"0000",
      INIT_46 => X"0000",
      INIT_47 => X"0000",
      INIT_48 => X"0101",
      INIT_49 => X"0000",
      INIT_4A => X"0100",
      INIT_4B => X"0000",
      INIT_4C => X"0000",
      INIT_4D => X"0000",
      INIT_4E => X"0000",
      INIT_4F => X"0000",
      INIT_50 => X"B5ED",
      INIT_51 => X"57E4",
      INIT_52 => X"A147",
      INIT_53 => X"CA33",
      INIT_54 => X"A93A",
      INIT_55 => X"52C6",
      INIT_56 => X"9555",
      INIT_57 => X"AE4E",
      INIT_58 => X"5999",
      INIT_59 => X"0000",
      INIT_5A => X"0000",
      INIT_5B => X"0000",
      INIT_5C => X"5111",
      INIT_5D => X"0000",
      INIT_5E => X"0000",
      INIT_5F => X"0000",
      IS_CONVSTCLK_INVERTED => '0',
      IS_DCLK_INVERTED => '0',
      SIM_DEVICE => "7SERIES",
      SIM_MONITOR_FILE => "design.txt"
    )
        port map (
      ALM(7 downto 0) => \NLW_xadc_supplied_temperature.XADC_inst_ALM_UNCONNECTED\(7 downto 0),
      BUSY => \NLW_xadc_supplied_temperature.XADC_inst_BUSY_UNCONNECTED\,
      CHANNEL(4 downto 0) => \NLW_xadc_supplied_temperature.XADC_inst_CHANNEL_UNCONNECTED\(4 downto 0),
      CONVST => '0',
      CONVSTCLK => '0',
      DADDR(6 downto 0) => B"0000000",
      DCLK => clk_ref_i,
      DEN => \xadc_supplied_temperature.xadc_den\,
      DI(15 downto 0) => B"0000000000000000",
      DO(15 downto 0) => \xadc_supplied_temperature.xadc_do\(15 downto 0),
      DRDY => \xadc_supplied_temperature.xadc_drdy\,
      DWE => '0',
      EOC => \NLW_xadc_supplied_temperature.XADC_inst_EOC_UNCONNECTED\,
      EOS => \NLW_xadc_supplied_temperature.XADC_inst_EOS_UNCONNECTED\,
      JTAGBUSY => \NLW_xadc_supplied_temperature.XADC_inst_JTAGBUSY_UNCONNECTED\,
      JTAGLOCKED => \NLW_xadc_supplied_temperature.XADC_inst_JTAGLOCKED_UNCONNECTED\,
      JTAGMODIFIED => \NLW_xadc_supplied_temperature.XADC_inst_JTAGMODIFIED_UNCONNECTED\,
      MUXADDR(4 downto 0) => \NLW_xadc_supplied_temperature.XADC_inst_MUXADDR_UNCONNECTED\(4 downto 0),
      OT => \NLW_xadc_supplied_temperature.XADC_inst_OT_UNCONNECTED\,
      RESET => '0',
      VAUXN(15 downto 0) => B"0000000000000000",
      VAUXP(15 downto 0) => B"0000000000000000",
      VN => '0',
      VP => '0'
    );
\xadc_supplied_temperature.rst_r1_reg\: unisim.vcomponents.FDRE
     port map (
      C => clk_ref_i,
      CE => '1',
      D => \xadc_supplied_temperature.rst_r1_reg_0\,
      Q => \xadc_supplied_temperature.rst_r1\,
      R => '0'
    );
\xadc_supplied_temperature.rst_r2_reg\: unisim.vcomponents.FDRE
     port map (
      C => clk_ref_i,
      CE => '1',
      D => \xadc_supplied_temperature.rst_r1\,
      Q => \xadc_supplied_temperature.rst_r2\,
      R => '0'
    );
\xadc_supplied_temperature.sample_en_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8000000000000000"
    )
        port map (
      I0 => \xadc_supplied_temperature.sample_timer_reg\(10),
      I1 => \xadc_supplied_temperature.sample_en_i_2_n_0\,
      I2 => \xadc_supplied_temperature.sample_timer_reg\(6),
      I3 => \xadc_supplied_temperature.sample_timer_reg\(8),
      I4 => \xadc_supplied_temperature.sample_timer_reg\(7),
      I5 => \xadc_supplied_temperature.sample_timer_reg\(9),
      O => \xadc_supplied_temperature.sample_en_i_1_n_0\
    );
\xadc_supplied_temperature.sample_en_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000000400"
    )
        port map (
      I0 => \xadc_supplied_temperature.sample_timer_reg\(0),
      I1 => \xadc_supplied_temperature.sample_timer_reg\(1),
      I2 => \xadc_supplied_temperature.sample_timer_reg\(2),
      I3 => \xadc_supplied_temperature.sample_timer_reg\(3),
      I4 => \xadc_supplied_temperature.sample_timer_reg\(5),
      I5 => \xadc_supplied_temperature.sample_timer_reg\(4),
      O => \xadc_supplied_temperature.sample_en_i_2_n_0\
    );
\xadc_supplied_temperature.sample_en_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk_ref_i,
      CE => '1',
      D => \xadc_supplied_temperature.sample_en_i_1_n_0\,
      Q => \xadc_supplied_temperature.sample_en\,
      R => '0'
    );
\xadc_supplied_temperature.sample_timer[0]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \xadc_supplied_temperature.sample_timer_reg\(0),
      O => \p_0_in__1\(0)
    );
\xadc_supplied_temperature.sample_timer[10]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => \xadc_supplied_temperature.rst_r2\,
      I1 => \xadc_supplied_temperature.xadc_den\,
      O => \xadc_supplied_temperature.sample_timer0\
    );
\xadc_supplied_temperature.sample_timer[10]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"7FFFFFFF80000000"
    )
        port map (
      I0 => \xadc_supplied_temperature.sample_timer_reg\(8),
      I1 => \xadc_supplied_temperature.sample_timer_reg\(6),
      I2 => \xadc_supplied_temperature.sample_timer[10]_i_3_n_0\,
      I3 => \xadc_supplied_temperature.sample_timer_reg\(7),
      I4 => \xadc_supplied_temperature.sample_timer_reg\(9),
      I5 => \xadc_supplied_temperature.sample_timer_reg\(10),
      O => \p_0_in__1\(10)
    );
\xadc_supplied_temperature.sample_timer[10]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8000000000000000"
    )
        port map (
      I0 => \xadc_supplied_temperature.sample_timer_reg\(5),
      I1 => \xadc_supplied_temperature.sample_timer_reg\(3),
      I2 => \xadc_supplied_temperature.sample_timer_reg\(1),
      I3 => \xadc_supplied_temperature.sample_timer_reg\(0),
      I4 => \xadc_supplied_temperature.sample_timer_reg\(2),
      I5 => \xadc_supplied_temperature.sample_timer_reg\(4),
      O => \xadc_supplied_temperature.sample_timer[10]_i_3_n_0\
    );
\xadc_supplied_temperature.sample_timer[1]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \xadc_supplied_temperature.sample_timer_reg\(0),
      I1 => \xadc_supplied_temperature.sample_timer_reg\(1),
      O => \p_0_in__1\(1)
    );
\xadc_supplied_temperature.sample_timer[2]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"78"
    )
        port map (
      I0 => \xadc_supplied_temperature.sample_timer_reg\(0),
      I1 => \xadc_supplied_temperature.sample_timer_reg\(1),
      I2 => \xadc_supplied_temperature.sample_timer_reg\(2),
      O => \p_0_in__1\(2)
    );
\xadc_supplied_temperature.sample_timer[3]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7F80"
    )
        port map (
      I0 => \xadc_supplied_temperature.sample_timer_reg\(1),
      I1 => \xadc_supplied_temperature.sample_timer_reg\(0),
      I2 => \xadc_supplied_temperature.sample_timer_reg\(2),
      I3 => \xadc_supplied_temperature.sample_timer_reg\(3),
      O => \p_0_in__1\(3)
    );
\xadc_supplied_temperature.sample_timer[4]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"7FFF8000"
    )
        port map (
      I0 => \xadc_supplied_temperature.sample_timer_reg\(2),
      I1 => \xadc_supplied_temperature.sample_timer_reg\(0),
      I2 => \xadc_supplied_temperature.sample_timer_reg\(1),
      I3 => \xadc_supplied_temperature.sample_timer_reg\(3),
      I4 => \xadc_supplied_temperature.sample_timer_reg\(4),
      O => \p_0_in__1\(4)
    );
\xadc_supplied_temperature.sample_timer[5]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"7FFFFFFF80000000"
    )
        port map (
      I0 => \xadc_supplied_temperature.sample_timer_reg\(3),
      I1 => \xadc_supplied_temperature.sample_timer_reg\(1),
      I2 => \xadc_supplied_temperature.sample_timer_reg\(0),
      I3 => \xadc_supplied_temperature.sample_timer_reg\(2),
      I4 => \xadc_supplied_temperature.sample_timer_reg\(4),
      I5 => \xadc_supplied_temperature.sample_timer_reg\(5),
      O => \p_0_in__1\(5)
    );
\xadc_supplied_temperature.sample_timer[6]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \xadc_supplied_temperature.sample_timer[10]_i_3_n_0\,
      I1 => \xadc_supplied_temperature.sample_timer_reg\(6),
      O => \p_0_in__1\(6)
    );
\xadc_supplied_temperature.sample_timer[7]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"78"
    )
        port map (
      I0 => \xadc_supplied_temperature.sample_timer[10]_i_3_n_0\,
      I1 => \xadc_supplied_temperature.sample_timer_reg\(6),
      I2 => \xadc_supplied_temperature.sample_timer_reg\(7),
      O => \p_0_in__1\(7)
    );
\xadc_supplied_temperature.sample_timer[8]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7F80"
    )
        port map (
      I0 => \xadc_supplied_temperature.sample_timer_reg\(6),
      I1 => \xadc_supplied_temperature.sample_timer[10]_i_3_n_0\,
      I2 => \xadc_supplied_temperature.sample_timer_reg\(7),
      I3 => \xadc_supplied_temperature.sample_timer_reg\(8),
      O => \p_0_in__1\(8)
    );
\xadc_supplied_temperature.sample_timer[9]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"7FFF8000"
    )
        port map (
      I0 => \xadc_supplied_temperature.sample_timer_reg\(7),
      I1 => \xadc_supplied_temperature.sample_timer[10]_i_3_n_0\,
      I2 => \xadc_supplied_temperature.sample_timer_reg\(6),
      I3 => \xadc_supplied_temperature.sample_timer_reg\(8),
      I4 => \xadc_supplied_temperature.sample_timer_reg\(9),
      O => \p_0_in__1\(9)
    );
\xadc_supplied_temperature.sample_timer_clr_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"000E"
    )
        port map (
      I0 => \xadc_supplied_temperature.xadc_den\,
      I1 => \xadc_supplied_temperature.sample_timer_clr\,
      I2 => \FSM_onehot_xadc_supplied_temperature.tempmon_state_reg_n_0_[2]\,
      I3 => \xadc_supplied_temperature.rst_r2\,
      O => \xadc_supplied_temperature.sample_timer_clr_i_1_n_0\
    );
\xadc_supplied_temperature.sample_timer_clr_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk_ref_i,
      CE => '1',
      D => \xadc_supplied_temperature.sample_timer_clr_i_1_n_0\,
      Q => \xadc_supplied_temperature.xadc_den\,
      R => '0'
    );
\xadc_supplied_temperature.sample_timer_en_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"000000FE"
    )
        port map (
      I0 => \xadc_supplied_temperature.sample_timer_en\,
      I1 => \FSM_onehot_xadc_supplied_temperature.tempmon_state_reg_n_0_[0]\,
      I2 => \xadc_supplied_temperature.temperature\,
      I3 => \xadc_supplied_temperature.sample_timer_clr\,
      I4 => \xadc_supplied_temperature.rst_r2\,
      O => \xadc_supplied_temperature.sample_timer_en_i_1_n_0\
    );
\xadc_supplied_temperature.sample_timer_en_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk_ref_i,
      CE => '1',
      D => \xadc_supplied_temperature.sample_timer_en_i_1_n_0\,
      Q => \xadc_supplied_temperature.sample_timer_en\,
      R => '0'
    );
\xadc_supplied_temperature.sample_timer_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk_ref_i,
      CE => \xadc_supplied_temperature.sample_timer_en\,
      D => \p_0_in__1\(0),
      Q => \xadc_supplied_temperature.sample_timer_reg\(0),
      R => \xadc_supplied_temperature.sample_timer0\
    );
\xadc_supplied_temperature.sample_timer_reg[10]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk_ref_i,
      CE => \xadc_supplied_temperature.sample_timer_en\,
      D => \p_0_in__1\(10),
      Q => \xadc_supplied_temperature.sample_timer_reg\(10),
      R => \xadc_supplied_temperature.sample_timer0\
    );
\xadc_supplied_temperature.sample_timer_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk_ref_i,
      CE => \xadc_supplied_temperature.sample_timer_en\,
      D => \p_0_in__1\(1),
      Q => \xadc_supplied_temperature.sample_timer_reg\(1),
      R => \xadc_supplied_temperature.sample_timer0\
    );
\xadc_supplied_temperature.sample_timer_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk_ref_i,
      CE => \xadc_supplied_temperature.sample_timer_en\,
      D => \p_0_in__1\(2),
      Q => \xadc_supplied_temperature.sample_timer_reg\(2),
      R => \xadc_supplied_temperature.sample_timer0\
    );
\xadc_supplied_temperature.sample_timer_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk_ref_i,
      CE => \xadc_supplied_temperature.sample_timer_en\,
      D => \p_0_in__1\(3),
      Q => \xadc_supplied_temperature.sample_timer_reg\(3),
      R => \xadc_supplied_temperature.sample_timer0\
    );
\xadc_supplied_temperature.sample_timer_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk_ref_i,
      CE => \xadc_supplied_temperature.sample_timer_en\,
      D => \p_0_in__1\(4),
      Q => \xadc_supplied_temperature.sample_timer_reg\(4),
      R => \xadc_supplied_temperature.sample_timer0\
    );
\xadc_supplied_temperature.sample_timer_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk_ref_i,
      CE => \xadc_supplied_temperature.sample_timer_en\,
      D => \p_0_in__1\(5),
      Q => \xadc_supplied_temperature.sample_timer_reg\(5),
      R => \xadc_supplied_temperature.sample_timer0\
    );
\xadc_supplied_temperature.sample_timer_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk_ref_i,
      CE => \xadc_supplied_temperature.sample_timer_en\,
      D => \p_0_in__1\(6),
      Q => \xadc_supplied_temperature.sample_timer_reg\(6),
      R => \xadc_supplied_temperature.sample_timer0\
    );
\xadc_supplied_temperature.sample_timer_reg[7]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk_ref_i,
      CE => \xadc_supplied_temperature.sample_timer_en\,
      D => \p_0_in__1\(7),
      Q => \xadc_supplied_temperature.sample_timer_reg\(7),
      R => \xadc_supplied_temperature.sample_timer0\
    );
\xadc_supplied_temperature.sample_timer_reg[8]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk_ref_i,
      CE => \xadc_supplied_temperature.sample_timer_en\,
      D => \p_0_in__1\(8),
      Q => \xadc_supplied_temperature.sample_timer_reg\(8),
      R => \xadc_supplied_temperature.sample_timer0\
    );
\xadc_supplied_temperature.sample_timer_reg[9]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk_ref_i,
      CE => \xadc_supplied_temperature.sample_timer_en\,
      D => \p_0_in__1\(9),
      Q => \xadc_supplied_temperature.sample_timer_reg\(9),
      R => \xadc_supplied_temperature.sample_timer0\
    );
\xadc_supplied_temperature.temperature_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk_ref_i,
      CE => \xadc_supplied_temperature.temperature\,
      D => \xadc_supplied_temperature.xadc_do_r\(4),
      Q => device_temp_lcl(0),
      R => \xadc_supplied_temperature.rst_r2\
    );
\xadc_supplied_temperature.temperature_reg[10]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk_ref_i,
      CE => \xadc_supplied_temperature.temperature\,
      D => \xadc_supplied_temperature.xadc_do_r\(14),
      Q => device_temp_lcl(10),
      R => \xadc_supplied_temperature.rst_r2\
    );
\xadc_supplied_temperature.temperature_reg[11]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk_ref_i,
      CE => \xadc_supplied_temperature.temperature\,
      D => \xadc_supplied_temperature.xadc_do_r\(15),
      Q => device_temp_lcl(11),
      R => \xadc_supplied_temperature.rst_r2\
    );
\xadc_supplied_temperature.temperature_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk_ref_i,
      CE => \xadc_supplied_temperature.temperature\,
      D => \xadc_supplied_temperature.xadc_do_r\(5),
      Q => device_temp_lcl(1),
      R => \xadc_supplied_temperature.rst_r2\
    );
\xadc_supplied_temperature.temperature_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk_ref_i,
      CE => \xadc_supplied_temperature.temperature\,
      D => \xadc_supplied_temperature.xadc_do_r\(6),
      Q => device_temp_lcl(2),
      R => \xadc_supplied_temperature.rst_r2\
    );
\xadc_supplied_temperature.temperature_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk_ref_i,
      CE => \xadc_supplied_temperature.temperature\,
      D => \xadc_supplied_temperature.xadc_do_r\(7),
      Q => device_temp_lcl(3),
      R => \xadc_supplied_temperature.rst_r2\
    );
\xadc_supplied_temperature.temperature_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk_ref_i,
      CE => \xadc_supplied_temperature.temperature\,
      D => \xadc_supplied_temperature.xadc_do_r\(8),
      Q => device_temp_lcl(4),
      R => \xadc_supplied_temperature.rst_r2\
    );
\xadc_supplied_temperature.temperature_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk_ref_i,
      CE => \xadc_supplied_temperature.temperature\,
      D => \xadc_supplied_temperature.xadc_do_r\(9),
      Q => device_temp_lcl(5),
      R => \xadc_supplied_temperature.rst_r2\
    );
\xadc_supplied_temperature.temperature_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk_ref_i,
      CE => \xadc_supplied_temperature.temperature\,
      D => \xadc_supplied_temperature.xadc_do_r\(10),
      Q => device_temp_lcl(6),
      R => \xadc_supplied_temperature.rst_r2\
    );
\xadc_supplied_temperature.temperature_reg[7]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk_ref_i,
      CE => \xadc_supplied_temperature.temperature\,
      D => \xadc_supplied_temperature.xadc_do_r\(11),
      Q => device_temp_lcl(7),
      R => \xadc_supplied_temperature.rst_r2\
    );
\xadc_supplied_temperature.temperature_reg[8]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk_ref_i,
      CE => \xadc_supplied_temperature.temperature\,
      D => \xadc_supplied_temperature.xadc_do_r\(12),
      Q => device_temp_lcl(8),
      R => \xadc_supplied_temperature.rst_r2\
    );
\xadc_supplied_temperature.temperature_reg[9]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk_ref_i,
      CE => \xadc_supplied_temperature.temperature\,
      D => \xadc_supplied_temperature.xadc_do_r\(13),
      Q => device_temp_lcl(9),
      R => \xadc_supplied_temperature.rst_r2\
    );
\xadc_supplied_temperature.xadc_do_r_reg[10]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk_ref_i,
      CE => '1',
      D => \xadc_supplied_temperature.xadc_do\(10),
      Q => \xadc_supplied_temperature.xadc_do_r\(10),
      R => \xadc_supplied_temperature.rst_r2\
    );
\xadc_supplied_temperature.xadc_do_r_reg[11]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk_ref_i,
      CE => '1',
      D => \xadc_supplied_temperature.xadc_do\(11),
      Q => \xadc_supplied_temperature.xadc_do_r\(11),
      R => \xadc_supplied_temperature.rst_r2\
    );
\xadc_supplied_temperature.xadc_do_r_reg[12]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk_ref_i,
      CE => '1',
      D => \xadc_supplied_temperature.xadc_do\(12),
      Q => \xadc_supplied_temperature.xadc_do_r\(12),
      R => \xadc_supplied_temperature.rst_r2\
    );
\xadc_supplied_temperature.xadc_do_r_reg[13]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk_ref_i,
      CE => '1',
      D => \xadc_supplied_temperature.xadc_do\(13),
      Q => \xadc_supplied_temperature.xadc_do_r\(13),
      R => \xadc_supplied_temperature.rst_r2\
    );
\xadc_supplied_temperature.xadc_do_r_reg[14]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk_ref_i,
      CE => '1',
      D => \xadc_supplied_temperature.xadc_do\(14),
      Q => \xadc_supplied_temperature.xadc_do_r\(14),
      R => \xadc_supplied_temperature.rst_r2\
    );
\xadc_supplied_temperature.xadc_do_r_reg[15]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk_ref_i,
      CE => '1',
      D => \xadc_supplied_temperature.xadc_do\(15),
      Q => \xadc_supplied_temperature.xadc_do_r\(15),
      R => \xadc_supplied_temperature.rst_r2\
    );
\xadc_supplied_temperature.xadc_do_r_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk_ref_i,
      CE => '1',
      D => \xadc_supplied_temperature.xadc_do\(4),
      Q => \xadc_supplied_temperature.xadc_do_r\(4),
      R => \xadc_supplied_temperature.rst_r2\
    );
\xadc_supplied_temperature.xadc_do_r_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk_ref_i,
      CE => '1',
      D => \xadc_supplied_temperature.xadc_do\(5),
      Q => \xadc_supplied_temperature.xadc_do_r\(5),
      R => \xadc_supplied_temperature.rst_r2\
    );
\xadc_supplied_temperature.xadc_do_r_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk_ref_i,
      CE => '1',
      D => \xadc_supplied_temperature.xadc_do\(6),
      Q => \xadc_supplied_temperature.xadc_do_r\(6),
      R => \xadc_supplied_temperature.rst_r2\
    );
\xadc_supplied_temperature.xadc_do_r_reg[7]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk_ref_i,
      CE => '1',
      D => \xadc_supplied_temperature.xadc_do\(7),
      Q => \xadc_supplied_temperature.xadc_do_r\(7),
      R => \xadc_supplied_temperature.rst_r2\
    );
\xadc_supplied_temperature.xadc_do_r_reg[8]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk_ref_i,
      CE => '1',
      D => \xadc_supplied_temperature.xadc_do\(8),
      Q => \xadc_supplied_temperature.xadc_do_r\(8),
      R => \xadc_supplied_temperature.rst_r2\
    );
\xadc_supplied_temperature.xadc_do_r_reg[9]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk_ref_i,
      CE => '1',
      D => \xadc_supplied_temperature.xadc_do\(9),
      Q => \xadc_supplied_temperature.xadc_do_r\(9),
      R => \xadc_supplied_temperature.rst_r2\
    );
\xadc_supplied_temperature.xadc_drdy_r_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk_ref_i,
      CE => '1',
      D => \xadc_supplied_temperature.xadc_drdy\,
      Q => \xadc_supplied_temperature.xadc_drdy_r\,
      R => \xadc_supplied_temperature.rst_r2\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mig_mig_7series_v4_2_ui_cmd is
  port (
    E : out STD_LOGIC_VECTOR ( 0 to 0 );
    \app_addr_r1_reg[23]_0\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    \app_addr_r1_reg[22]_0\ : out STD_LOGIC;
    \app_addr_r1_reg[23]_1\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    \app_addr_r1_reg[23]_2\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    \app_addr_r1_reg[23]_3\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    S : out STD_LOGIC_VECTOR ( 2 downto 0 );
    D : out STD_LOGIC_VECTOR ( 12 downto 0 );
    \req_row_r_lcl_reg[10]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    \req_bank_r_lcl_reg[0]\ : out STD_LOGIC;
    \app_addr_r1_reg[24]_0\ : out STD_LOGIC;
    \app_addr_r1_reg[25]_0\ : out STD_LOGIC;
    \app_addr_r1_reg[26]_0\ : out STD_LOGIC;
    \req_bank_r_lcl_reg[0]_0\ : out STD_LOGIC;
    \req_bank_r_lcl_reg[2]\ : out STD_LOGIC;
    \req_bank_r_lcl_reg[2]_0\ : out STD_LOGIC;
    \wr_req_counter.wr_req_cnt_r_reg[1]\ : out STD_LOGIC;
    app_cmd_r2 : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \wr_req_counter.wr_req_cnt_r_reg[0]\ : out STD_LOGIC;
    \read_data_indx.rd_data_upd_indx_r_reg\ : out STD_LOGIC;
    wr_accepted : out STD_LOGIC;
    reset_reg : out STD_LOGIC_VECTOR ( 3 downto 0 );
    use_addr : out STD_LOGIC;
    app_en_r2_reg_0 : out STD_LOGIC;
    \strict_mode.rd_data_buf_addr_r_lcl_reg[0]\ : out STD_LOGIC;
    \strict_mode.rd_data_buf_addr_r_lcl_reg[1]\ : out STD_LOGIC;
    cmd : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \app_addr_r1_reg[9]_0\ : out STD_LOGIC_VECTOR ( 9 downto 0 );
    app_rdy_ns : in STD_LOGIC;
    \app_cmd_r2_reg[0]_0\ : in STD_LOGIC;
    row_hit_r_reg : in STD_LOGIC_VECTOR ( 19 downto 0 );
    req_bank_r : in STD_LOGIC_VECTOR ( 11 downto 0 );
    app_en : in STD_LOGIC;
    \app_addr_r1_reg[0]_0\ : in STD_LOGIC;
    \wr_req_counter.wr_req_cnt_r\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    p_0_in : in STD_LOGIC_VECTOR ( 0 to 0 );
    wr_data_buf_addr : in STD_LOGIC_VECTOR ( 3 downto 0 );
    \strict_mode.rd_data_buf_addr_r_lcl\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
    app_addr : in STD_LOGIC_VECTOR ( 26 downto 0 );
    app_cmd : in STD_LOGIC_VECTOR ( 1 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of mig_mig_7series_v4_2_ui_cmd : entity is "mig_7series_v4_2_ui_cmd";
end mig_mig_7series_v4_2_ui_cmd;

architecture STRUCTURE of mig_mig_7series_v4_2_ui_cmd is
  signal \^d\ : STD_LOGIC_VECTOR ( 12 downto 0 );
  signal \^e\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal app_addr_r10 : STD_LOGIC;
  signal \^app_addr_r1_reg[22]_0\ : STD_LOGIC;
  signal \^app_addr_r1_reg[24]_0\ : STD_LOGIC;
  signal \^app_addr_r1_reg[25]_0\ : STD_LOGIC;
  signal \^app_addr_r1_reg[26]_0\ : STD_LOGIC;
  signal \app_addr_r1_reg_n_0_[0]\ : STD_LOGIC;
  signal \app_addr_r1_reg_n_0_[10]\ : STD_LOGIC;
  signal \app_addr_r1_reg_n_0_[11]\ : STD_LOGIC;
  signal \app_addr_r1_reg_n_0_[12]\ : STD_LOGIC;
  signal \app_addr_r1_reg_n_0_[13]\ : STD_LOGIC;
  signal \app_addr_r1_reg_n_0_[14]\ : STD_LOGIC;
  signal \app_addr_r1_reg_n_0_[15]\ : STD_LOGIC;
  signal \app_addr_r1_reg_n_0_[16]\ : STD_LOGIC;
  signal \app_addr_r1_reg_n_0_[17]\ : STD_LOGIC;
  signal \app_addr_r1_reg_n_0_[18]\ : STD_LOGIC;
  signal \app_addr_r1_reg_n_0_[19]\ : STD_LOGIC;
  signal \app_addr_r1_reg_n_0_[1]\ : STD_LOGIC;
  signal \app_addr_r1_reg_n_0_[20]\ : STD_LOGIC;
  signal \app_addr_r1_reg_n_0_[21]\ : STD_LOGIC;
  signal \app_addr_r1_reg_n_0_[22]\ : STD_LOGIC;
  signal \app_addr_r1_reg_n_0_[23]\ : STD_LOGIC;
  signal \app_addr_r1_reg_n_0_[2]\ : STD_LOGIC;
  signal \app_addr_r1_reg_n_0_[3]\ : STD_LOGIC;
  signal \app_addr_r1_reg_n_0_[4]\ : STD_LOGIC;
  signal \app_addr_r1_reg_n_0_[5]\ : STD_LOGIC;
  signal \app_addr_r1_reg_n_0_[6]\ : STD_LOGIC;
  signal \app_addr_r1_reg_n_0_[7]\ : STD_LOGIC;
  signal \app_addr_r1_reg_n_0_[8]\ : STD_LOGIC;
  signal \app_addr_r1_reg_n_0_[9]\ : STD_LOGIC;
  signal \app_addr_r2_reg_n_0_[0]\ : STD_LOGIC;
  signal \app_addr_r2_reg_n_0_[10]\ : STD_LOGIC;
  signal \app_addr_r2_reg_n_0_[11]\ : STD_LOGIC;
  signal \app_addr_r2_reg_n_0_[12]\ : STD_LOGIC;
  signal \app_addr_r2_reg_n_0_[13]\ : STD_LOGIC;
  signal \app_addr_r2_reg_n_0_[14]\ : STD_LOGIC;
  signal \app_addr_r2_reg_n_0_[15]\ : STD_LOGIC;
  signal \app_addr_r2_reg_n_0_[16]\ : STD_LOGIC;
  signal \app_addr_r2_reg_n_0_[17]\ : STD_LOGIC;
  signal \app_addr_r2_reg_n_0_[18]\ : STD_LOGIC;
  signal \app_addr_r2_reg_n_0_[19]\ : STD_LOGIC;
  signal \app_addr_r2_reg_n_0_[1]\ : STD_LOGIC;
  signal \app_addr_r2_reg_n_0_[20]\ : STD_LOGIC;
  signal \app_addr_r2_reg_n_0_[21]\ : STD_LOGIC;
  signal \app_addr_r2_reg_n_0_[22]\ : STD_LOGIC;
  signal \app_addr_r2_reg_n_0_[23]\ : STD_LOGIC;
  signal \app_addr_r2_reg_n_0_[2]\ : STD_LOGIC;
  signal \app_addr_r2_reg_n_0_[3]\ : STD_LOGIC;
  signal \app_addr_r2_reg_n_0_[4]\ : STD_LOGIC;
  signal \app_addr_r2_reg_n_0_[5]\ : STD_LOGIC;
  signal \app_addr_r2_reg_n_0_[6]\ : STD_LOGIC;
  signal \app_addr_r2_reg_n_0_[7]\ : STD_LOGIC;
  signal \app_addr_r2_reg_n_0_[8]\ : STD_LOGIC;
  signal \app_addr_r2_reg_n_0_[9]\ : STD_LOGIC;
  signal app_cmd_r1 : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \^app_cmd_r2\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal app_en_ns1 : STD_LOGIC;
  signal app_en_ns2 : STD_LOGIC;
  signal app_en_r1 : STD_LOGIC;
  signal app_en_r2 : STD_LOGIC;
  signal p_0_in_0 : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal p_1_in : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal \^strict_mode.rd_data_buf_addr_r_lcl_reg[0]\ : STD_LOGIC;
  signal \^strict_mode.rd_data_buf_addr_r_lcl_reg[1]\ : STD_LOGIC;
  signal \^use_addr\ : STD_LOGIC;
  signal \write__0\ : STD_LOGIC;
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of app_en_r1_i_1 : label is "soft_lutpair1216";
  attribute SOFT_HLUTNM of app_en_r2_i_1 : label is "soft_lutpair1216";
  attribute syn_maxfan : string;
  attribute syn_maxfan of app_rdy_r_reg : label is "10";
  attribute SOFT_HLUTNM of \data_buf_address_counter.data_buf_addr_cnt_r[3]_i_1\ : label is "soft_lutpair1214";
  attribute SOFT_HLUTNM of \i___42_i_1\ : label is "soft_lutpair1215";
  attribute SOFT_HLUTNM of \i___59_i_1\ : label is "soft_lutpair1224";
  attribute SOFT_HLUTNM of \req_bank_r_lcl[0]_i_1\ : label is "soft_lutpair1225";
  attribute SOFT_HLUTNM of \req_bank_r_lcl[1]_i_1\ : label is "soft_lutpair1224";
  attribute SOFT_HLUTNM of \req_bank_r_lcl[2]_i_1\ : label is "soft_lutpair1223";
  attribute SOFT_HLUTNM of \req_col_r[0]_i_1\ : label is "soft_lutpair1226";
  attribute SOFT_HLUTNM of \req_col_r[1]_i_1\ : label is "soft_lutpair1230";
  attribute SOFT_HLUTNM of \req_col_r[3]_i_1\ : label is "soft_lutpair1230";
  attribute SOFT_HLUTNM of \req_col_r[4]_i_1\ : label is "soft_lutpair1229";
  attribute SOFT_HLUTNM of \req_col_r[5]_i_1\ : label is "soft_lutpair1227";
  attribute SOFT_HLUTNM of \req_col_r[6]_i_1\ : label is "soft_lutpair1229";
  attribute SOFT_HLUTNM of \req_col_r[7]_i_1\ : label is "soft_lutpair1228";
  attribute SOFT_HLUTNM of \req_col_r[8]_i_1\ : label is "soft_lutpair1228";
  attribute SOFT_HLUTNM of \req_col_r[9]_i_1\ : label is "soft_lutpair1227";
  attribute SOFT_HLUTNM of \req_data_buf_addr_r[1]_i_1\ : label is "soft_lutpair1213";
  attribute SOFT_HLUTNM of \req_data_buf_addr_r[3]_i_2\ : label is "soft_lutpair1213";
  attribute SOFT_HLUTNM of \req_row_r_lcl[0]_i_1\ : label is "soft_lutpair1222";
  attribute SOFT_HLUTNM of \req_row_r_lcl[10]_i_1\ : label is "soft_lutpair1220";
  attribute SOFT_HLUTNM of \req_row_r_lcl[11]_i_1\ : label is "soft_lutpair1221";
  attribute SOFT_HLUTNM of \req_row_r_lcl[12]_i_1\ : label is "soft_lutpair1218";
  attribute SOFT_HLUTNM of \req_row_r_lcl[13]_i_1\ : label is "soft_lutpair1226";
  attribute SOFT_HLUTNM of \req_row_r_lcl[1]_i_1\ : label is "soft_lutpair1221";
  attribute SOFT_HLUTNM of \req_row_r_lcl[2]_i_1\ : label is "soft_lutpair1220";
  attribute SOFT_HLUTNM of \req_row_r_lcl[3]_i_1\ : label is "soft_lutpair1219";
  attribute SOFT_HLUTNM of \req_row_r_lcl[4]_i_1\ : label is "soft_lutpair1218";
  attribute SOFT_HLUTNM of \req_row_r_lcl[5]_i_1\ : label is "soft_lutpair1217";
  attribute SOFT_HLUTNM of \req_row_r_lcl[6]_i_1\ : label is "soft_lutpair1223";
  attribute SOFT_HLUTNM of \req_row_r_lcl[7]_i_1\ : label is "soft_lutpair1222";
  attribute SOFT_HLUTNM of \req_row_r_lcl[8]_i_1\ : label is "soft_lutpair1217";
  attribute SOFT_HLUTNM of \req_row_r_lcl[9]_i_1\ : label is "soft_lutpair1219";
  attribute SOFT_HLUTNM of req_wr_r_lcl_i_2 : label is "soft_lutpair1225";
  attribute SOFT_HLUTNM of \strict_mode.rd_data_buf_addr_r_lcl[0]_i_1\ : label is "soft_lutpair1215";
  attribute SOFT_HLUTNM of \wr_req_counter.wr_req_cnt_r[4]_i_3\ : label is "soft_lutpair1214";
begin
  D(12 downto 0) <= \^d\(12 downto 0);
  E(0) <= \^e\(0);
  \app_addr_r1_reg[22]_0\ <= \^app_addr_r1_reg[22]_0\;
  \app_addr_r1_reg[24]_0\ <= \^app_addr_r1_reg[24]_0\;
  \app_addr_r1_reg[25]_0\ <= \^app_addr_r1_reg[25]_0\;
  \app_addr_r1_reg[26]_0\ <= \^app_addr_r1_reg[26]_0\;
  app_cmd_r2(1 downto 0) <= \^app_cmd_r2\(1 downto 0);
  \strict_mode.rd_data_buf_addr_r_lcl_reg[0]\ <= \^strict_mode.rd_data_buf_addr_r_lcl_reg[0]\;
  \strict_mode.rd_data_buf_addr_r_lcl_reg[1]\ <= \^strict_mode.rd_data_buf_addr_r_lcl_reg[1]\;
  use_addr <= \^use_addr\;
\app_addr_r1[26]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^e\(0),
      I1 => app_en,
      O => app_addr_r10
    );
\app_addr_r1_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \app_cmd_r2_reg[0]_0\,
      CE => app_addr_r10,
      D => app_addr(0),
      Q => \app_addr_r1_reg_n_0_[0]\,
      R => \app_addr_r1_reg[0]_0\
    );
\app_addr_r1_reg[10]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \app_cmd_r2_reg[0]_0\,
      CE => app_addr_r10,
      D => app_addr(10),
      Q => \app_addr_r1_reg_n_0_[10]\,
      R => \app_addr_r1_reg[0]_0\
    );
\app_addr_r1_reg[11]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \app_cmd_r2_reg[0]_0\,
      CE => app_addr_r10,
      D => app_addr(11),
      Q => \app_addr_r1_reg_n_0_[11]\,
      R => \app_addr_r1_reg[0]_0\
    );
\app_addr_r1_reg[12]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \app_cmd_r2_reg[0]_0\,
      CE => app_addr_r10,
      D => app_addr(12),
      Q => \app_addr_r1_reg_n_0_[12]\,
      R => \app_addr_r1_reg[0]_0\
    );
\app_addr_r1_reg[13]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \app_cmd_r2_reg[0]_0\,
      CE => app_addr_r10,
      D => app_addr(13),
      Q => \app_addr_r1_reg_n_0_[13]\,
      R => \app_addr_r1_reg[0]_0\
    );
\app_addr_r1_reg[14]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \app_cmd_r2_reg[0]_0\,
      CE => app_addr_r10,
      D => app_addr(14),
      Q => \app_addr_r1_reg_n_0_[14]\,
      R => \app_addr_r1_reg[0]_0\
    );
\app_addr_r1_reg[15]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \app_cmd_r2_reg[0]_0\,
      CE => app_addr_r10,
      D => app_addr(15),
      Q => \app_addr_r1_reg_n_0_[15]\,
      R => \app_addr_r1_reg[0]_0\
    );
\app_addr_r1_reg[16]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \app_cmd_r2_reg[0]_0\,
      CE => app_addr_r10,
      D => app_addr(16),
      Q => \app_addr_r1_reg_n_0_[16]\,
      R => \app_addr_r1_reg[0]_0\
    );
\app_addr_r1_reg[17]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \app_cmd_r2_reg[0]_0\,
      CE => app_addr_r10,
      D => app_addr(17),
      Q => \app_addr_r1_reg_n_0_[17]\,
      R => \app_addr_r1_reg[0]_0\
    );
\app_addr_r1_reg[18]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \app_cmd_r2_reg[0]_0\,
      CE => app_addr_r10,
      D => app_addr(18),
      Q => \app_addr_r1_reg_n_0_[18]\,
      R => \app_addr_r1_reg[0]_0\
    );
\app_addr_r1_reg[19]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \app_cmd_r2_reg[0]_0\,
      CE => app_addr_r10,
      D => app_addr(19),
      Q => \app_addr_r1_reg_n_0_[19]\,
      R => \app_addr_r1_reg[0]_0\
    );
\app_addr_r1_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \app_cmd_r2_reg[0]_0\,
      CE => app_addr_r10,
      D => app_addr(1),
      Q => \app_addr_r1_reg_n_0_[1]\,
      R => \app_addr_r1_reg[0]_0\
    );
\app_addr_r1_reg[20]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \app_cmd_r2_reg[0]_0\,
      CE => app_addr_r10,
      D => app_addr(20),
      Q => \app_addr_r1_reg_n_0_[20]\,
      R => \app_addr_r1_reg[0]_0\
    );
\app_addr_r1_reg[21]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \app_cmd_r2_reg[0]_0\,
      CE => app_addr_r10,
      D => app_addr(21),
      Q => \app_addr_r1_reg_n_0_[21]\,
      R => \app_addr_r1_reg[0]_0\
    );
\app_addr_r1_reg[22]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \app_cmd_r2_reg[0]_0\,
      CE => app_addr_r10,
      D => app_addr(22),
      Q => \app_addr_r1_reg_n_0_[22]\,
      R => \app_addr_r1_reg[0]_0\
    );
\app_addr_r1_reg[23]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \app_cmd_r2_reg[0]_0\,
      CE => app_addr_r10,
      D => app_addr(23),
      Q => \app_addr_r1_reg_n_0_[23]\,
      R => \app_addr_r1_reg[0]_0\
    );
\app_addr_r1_reg[24]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \app_cmd_r2_reg[0]_0\,
      CE => app_addr_r10,
      D => app_addr(24),
      Q => p_1_in(0),
      R => \app_addr_r1_reg[0]_0\
    );
\app_addr_r1_reg[25]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \app_cmd_r2_reg[0]_0\,
      CE => app_addr_r10,
      D => app_addr(25),
      Q => p_1_in(1),
      R => \app_addr_r1_reg[0]_0\
    );
\app_addr_r1_reg[26]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \app_cmd_r2_reg[0]_0\,
      CE => app_addr_r10,
      D => app_addr(26),
      Q => p_1_in(2),
      R => \app_addr_r1_reg[0]_0\
    );
\app_addr_r1_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \app_cmd_r2_reg[0]_0\,
      CE => app_addr_r10,
      D => app_addr(2),
      Q => \app_addr_r1_reg_n_0_[2]\,
      R => \app_addr_r1_reg[0]_0\
    );
\app_addr_r1_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \app_cmd_r2_reg[0]_0\,
      CE => app_addr_r10,
      D => app_addr(3),
      Q => \app_addr_r1_reg_n_0_[3]\,
      R => \app_addr_r1_reg[0]_0\
    );
\app_addr_r1_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \app_cmd_r2_reg[0]_0\,
      CE => app_addr_r10,
      D => app_addr(4),
      Q => \app_addr_r1_reg_n_0_[4]\,
      R => \app_addr_r1_reg[0]_0\
    );
\app_addr_r1_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \app_cmd_r2_reg[0]_0\,
      CE => app_addr_r10,
      D => app_addr(5),
      Q => \app_addr_r1_reg_n_0_[5]\,
      R => \app_addr_r1_reg[0]_0\
    );
\app_addr_r1_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \app_cmd_r2_reg[0]_0\,
      CE => app_addr_r10,
      D => app_addr(6),
      Q => \app_addr_r1_reg_n_0_[6]\,
      R => \app_addr_r1_reg[0]_0\
    );
\app_addr_r1_reg[7]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \app_cmd_r2_reg[0]_0\,
      CE => app_addr_r10,
      D => app_addr(7),
      Q => \app_addr_r1_reg_n_0_[7]\,
      R => \app_addr_r1_reg[0]_0\
    );
\app_addr_r1_reg[8]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \app_cmd_r2_reg[0]_0\,
      CE => app_addr_r10,
      D => app_addr(8),
      Q => \app_addr_r1_reg_n_0_[8]\,
      R => \app_addr_r1_reg[0]_0\
    );
\app_addr_r1_reg[9]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \app_cmd_r2_reg[0]_0\,
      CE => app_addr_r10,
      D => app_addr(9),
      Q => \app_addr_r1_reg_n_0_[9]\,
      R => \app_addr_r1_reg[0]_0\
    );
\app_addr_r2_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \app_cmd_r2_reg[0]_0\,
      CE => \^e\(0),
      D => \app_addr_r1_reg_n_0_[0]\,
      Q => \app_addr_r2_reg_n_0_[0]\,
      R => \app_addr_r1_reg[0]_0\
    );
\app_addr_r2_reg[10]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \app_cmd_r2_reg[0]_0\,
      CE => \^e\(0),
      D => \app_addr_r1_reg_n_0_[10]\,
      Q => \app_addr_r2_reg_n_0_[10]\,
      R => \app_addr_r1_reg[0]_0\
    );
\app_addr_r2_reg[11]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \app_cmd_r2_reg[0]_0\,
      CE => \^e\(0),
      D => \app_addr_r1_reg_n_0_[11]\,
      Q => \app_addr_r2_reg_n_0_[11]\,
      R => \app_addr_r1_reg[0]_0\
    );
\app_addr_r2_reg[12]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \app_cmd_r2_reg[0]_0\,
      CE => \^e\(0),
      D => \app_addr_r1_reg_n_0_[12]\,
      Q => \app_addr_r2_reg_n_0_[12]\,
      R => \app_addr_r1_reg[0]_0\
    );
\app_addr_r2_reg[13]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \app_cmd_r2_reg[0]_0\,
      CE => \^e\(0),
      D => \app_addr_r1_reg_n_0_[13]\,
      Q => \app_addr_r2_reg_n_0_[13]\,
      R => \app_addr_r1_reg[0]_0\
    );
\app_addr_r2_reg[14]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \app_cmd_r2_reg[0]_0\,
      CE => \^e\(0),
      D => \app_addr_r1_reg_n_0_[14]\,
      Q => \app_addr_r2_reg_n_0_[14]\,
      R => \app_addr_r1_reg[0]_0\
    );
\app_addr_r2_reg[15]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \app_cmd_r2_reg[0]_0\,
      CE => \^e\(0),
      D => \app_addr_r1_reg_n_0_[15]\,
      Q => \app_addr_r2_reg_n_0_[15]\,
      R => \app_addr_r1_reg[0]_0\
    );
\app_addr_r2_reg[16]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \app_cmd_r2_reg[0]_0\,
      CE => \^e\(0),
      D => \app_addr_r1_reg_n_0_[16]\,
      Q => \app_addr_r2_reg_n_0_[16]\,
      R => \app_addr_r1_reg[0]_0\
    );
\app_addr_r2_reg[17]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \app_cmd_r2_reg[0]_0\,
      CE => \^e\(0),
      D => \app_addr_r1_reg_n_0_[17]\,
      Q => \app_addr_r2_reg_n_0_[17]\,
      R => \app_addr_r1_reg[0]_0\
    );
\app_addr_r2_reg[18]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \app_cmd_r2_reg[0]_0\,
      CE => \^e\(0),
      D => \app_addr_r1_reg_n_0_[18]\,
      Q => \app_addr_r2_reg_n_0_[18]\,
      R => \app_addr_r1_reg[0]_0\
    );
\app_addr_r2_reg[19]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \app_cmd_r2_reg[0]_0\,
      CE => \^e\(0),
      D => \app_addr_r1_reg_n_0_[19]\,
      Q => \app_addr_r2_reg_n_0_[19]\,
      R => \app_addr_r1_reg[0]_0\
    );
\app_addr_r2_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \app_cmd_r2_reg[0]_0\,
      CE => \^e\(0),
      D => \app_addr_r1_reg_n_0_[1]\,
      Q => \app_addr_r2_reg_n_0_[1]\,
      R => \app_addr_r1_reg[0]_0\
    );
\app_addr_r2_reg[20]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \app_cmd_r2_reg[0]_0\,
      CE => \^e\(0),
      D => \app_addr_r1_reg_n_0_[20]\,
      Q => \app_addr_r2_reg_n_0_[20]\,
      R => \app_addr_r1_reg[0]_0\
    );
\app_addr_r2_reg[21]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \app_cmd_r2_reg[0]_0\,
      CE => \^e\(0),
      D => \app_addr_r1_reg_n_0_[21]\,
      Q => \app_addr_r2_reg_n_0_[21]\,
      R => \app_addr_r1_reg[0]_0\
    );
\app_addr_r2_reg[22]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \app_cmd_r2_reg[0]_0\,
      CE => \^e\(0),
      D => \app_addr_r1_reg_n_0_[22]\,
      Q => \app_addr_r2_reg_n_0_[22]\,
      R => \app_addr_r1_reg[0]_0\
    );
\app_addr_r2_reg[23]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \app_cmd_r2_reg[0]_0\,
      CE => \^e\(0),
      D => \app_addr_r1_reg_n_0_[23]\,
      Q => \app_addr_r2_reg_n_0_[23]\,
      R => \app_addr_r1_reg[0]_0\
    );
\app_addr_r2_reg[24]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \app_cmd_r2_reg[0]_0\,
      CE => \^e\(0),
      D => p_1_in(0),
      Q => p_0_in_0(0),
      R => \app_addr_r1_reg[0]_0\
    );
\app_addr_r2_reg[25]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \app_cmd_r2_reg[0]_0\,
      CE => \^e\(0),
      D => p_1_in(1),
      Q => p_0_in_0(1),
      R => \app_addr_r1_reg[0]_0\
    );
\app_addr_r2_reg[26]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \app_cmd_r2_reg[0]_0\,
      CE => \^e\(0),
      D => p_1_in(2),
      Q => p_0_in_0(2),
      R => \app_addr_r1_reg[0]_0\
    );
\app_addr_r2_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \app_cmd_r2_reg[0]_0\,
      CE => \^e\(0),
      D => \app_addr_r1_reg_n_0_[2]\,
      Q => \app_addr_r2_reg_n_0_[2]\,
      R => \app_addr_r1_reg[0]_0\
    );
\app_addr_r2_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \app_cmd_r2_reg[0]_0\,
      CE => \^e\(0),
      D => \app_addr_r1_reg_n_0_[3]\,
      Q => \app_addr_r2_reg_n_0_[3]\,
      R => \app_addr_r1_reg[0]_0\
    );
\app_addr_r2_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \app_cmd_r2_reg[0]_0\,
      CE => \^e\(0),
      D => \app_addr_r1_reg_n_0_[4]\,
      Q => \app_addr_r2_reg_n_0_[4]\,
      R => \app_addr_r1_reg[0]_0\
    );
\app_addr_r2_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \app_cmd_r2_reg[0]_0\,
      CE => \^e\(0),
      D => \app_addr_r1_reg_n_0_[5]\,
      Q => \app_addr_r2_reg_n_0_[5]\,
      R => \app_addr_r1_reg[0]_0\
    );
\app_addr_r2_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \app_cmd_r2_reg[0]_0\,
      CE => \^e\(0),
      D => \app_addr_r1_reg_n_0_[6]\,
      Q => \app_addr_r2_reg_n_0_[6]\,
      R => \app_addr_r1_reg[0]_0\
    );
\app_addr_r2_reg[7]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \app_cmd_r2_reg[0]_0\,
      CE => \^e\(0),
      D => \app_addr_r1_reg_n_0_[7]\,
      Q => \app_addr_r2_reg_n_0_[7]\,
      R => \app_addr_r1_reg[0]_0\
    );
\app_addr_r2_reg[8]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \app_cmd_r2_reg[0]_0\,
      CE => \^e\(0),
      D => \app_addr_r1_reg_n_0_[8]\,
      Q => \app_addr_r2_reg_n_0_[8]\,
      R => \app_addr_r1_reg[0]_0\
    );
\app_addr_r2_reg[9]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \app_cmd_r2_reg[0]_0\,
      CE => \^e\(0),
      D => \app_addr_r1_reg_n_0_[9]\,
      Q => \app_addr_r2_reg_n_0_[9]\,
      R => \app_addr_r1_reg[0]_0\
    );
\app_cmd_r1_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \app_cmd_r2_reg[0]_0\,
      CE => \^e\(0),
      D => app_cmd(0),
      Q => app_cmd_r1(0),
      R => '0'
    );
\app_cmd_r1_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \app_cmd_r2_reg[0]_0\,
      CE => \^e\(0),
      D => app_cmd(1),
      Q => app_cmd_r1(1),
      R => '0'
    );
\app_cmd_r2_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \app_cmd_r2_reg[0]_0\,
      CE => \^e\(0),
      D => app_cmd_r1(0),
      Q => \^app_cmd_r2\(0),
      R => '0'
    );
\app_cmd_r2_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \app_cmd_r2_reg[0]_0\,
      CE => \^e\(0),
      D => app_cmd_r1(1),
      Q => \^app_cmd_r2\(1),
      R => '0'
    );
app_en_r1_i_1: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2230"
    )
        port map (
      I0 => app_en,
      I1 => \app_addr_r1_reg[0]_0\,
      I2 => app_en_r1,
      I3 => \^e\(0),
      O => app_en_ns1
    );
app_en_r1_reg: unisim.vcomponents.FDRE
     port map (
      C => \app_cmd_r2_reg[0]_0\,
      CE => '1',
      D => app_en_ns1,
      Q => app_en_r1,
      R => '0'
    );
app_en_r2_i_1: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2230"
    )
        port map (
      I0 => app_en_r1,
      I1 => \app_addr_r1_reg[0]_0\,
      I2 => app_en_r2,
      I3 => \^e\(0),
      O => app_en_ns2
    );
app_en_r2_reg: unisim.vcomponents.FDRE
     port map (
      C => \app_cmd_r2_reg[0]_0\,
      CE => '1',
      D => app_en_ns2,
      Q => app_en_r2,
      R => '0'
    );
app_rdy_r_i_4: unisim.vcomponents.LUT6
    generic map(
      INIT => X"D55555D540000040"
    )
        port map (
      I0 => \wr_req_counter.wr_req_cnt_r\(1),
      I1 => \^e\(0),
      I2 => app_en_r2,
      I3 => \^app_cmd_r2\(0),
      I4 => \^app_cmd_r2\(1),
      I5 => \wr_req_counter.wr_req_cnt_r\(0),
      O => \wr_req_counter.wr_req_cnt_r_reg[1]\
    );
app_rdy_r_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \app_cmd_r2_reg[0]_0\,
      CE => '1',
      D => app_rdy_ns,
      Q => \^e\(0),
      R => '0'
    );
\data_buf_address_counter.data_buf_addr_cnt_r[3]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8008"
    )
        port map (
      I0 => \^e\(0),
      I1 => app_en_r2,
      I2 => \^app_cmd_r2\(0),
      I3 => \^app_cmd_r2\(1),
      O => wr_accepted
    );
\i___42_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => app_en_r2,
      I1 => \^e\(0),
      O => \^use_addr\
    );
\i___59_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_cmd_r1(0),
      I1 => \^e\(0),
      I2 => \^app_cmd_r2\(0),
      O => cmd(0)
    );
rb_hit_busy_r_i_2: unisim.vcomponents.LUT6
    generic map(
      INIT => X"6FF6FFFFFFFF6FF6"
    )
        port map (
      I0 => \^app_addr_r1_reg[24]_0\,
      I1 => req_bank_r(0),
      I2 => req_bank_r(1),
      I3 => \^app_addr_r1_reg[25]_0\,
      I4 => req_bank_r(2),
      I5 => \^app_addr_r1_reg[26]_0\,
      O => \req_bank_r_lcl_reg[0]\
    );
\rb_hit_busy_r_i_2__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"6FF6FFFFFFFF6FF6"
    )
        port map (
      I0 => \^app_addr_r1_reg[24]_0\,
      I1 => req_bank_r(3),
      I2 => req_bank_r(4),
      I3 => \^app_addr_r1_reg[25]_0\,
      I4 => req_bank_r(5),
      I5 => \^app_addr_r1_reg[26]_0\,
      O => \req_bank_r_lcl_reg[0]_0\
    );
\rb_hit_busy_r_i_2__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"6FF6FFFFFFFF6FF6"
    )
        port map (
      I0 => \^app_addr_r1_reg[26]_0\,
      I1 => req_bank_r(8),
      I2 => req_bank_r(7),
      I3 => \^app_addr_r1_reg[25]_0\,
      I4 => req_bank_r(6),
      I5 => \^app_addr_r1_reg[24]_0\,
      O => \req_bank_r_lcl_reg[2]\
    );
\rb_hit_busy_r_i_2__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"6FF6FFFFFFFF6FF6"
    )
        port map (
      I0 => \^app_addr_r1_reg[26]_0\,
      I1 => req_bank_r(11),
      I2 => req_bank_r(10),
      I3 => \^app_addr_r1_reg[25]_0\,
      I4 => req_bank_r(9),
      I5 => \^app_addr_r1_reg[24]_0\,
      O => \req_bank_r_lcl_reg[2]_0\
    );
\req_bank_r_lcl[0]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => p_1_in(0),
      I1 => \^e\(0),
      I2 => p_0_in_0(0),
      O => \^app_addr_r1_reg[24]_0\
    );
\req_bank_r_lcl[1]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => p_1_in(1),
      I1 => \^e\(0),
      I2 => p_0_in_0(1),
      O => \^app_addr_r1_reg[25]_0\
    );
\req_bank_r_lcl[2]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => p_1_in(2),
      I1 => \^e\(0),
      I2 => p_0_in_0(2),
      O => \^app_addr_r1_reg[26]_0\
    );
\req_col_r[0]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \app_addr_r1_reg_n_0_[0]\,
      I1 => \^e\(0),
      I2 => \app_addr_r2_reg_n_0_[0]\,
      O => \app_addr_r1_reg[9]_0\(0)
    );
\req_col_r[1]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \app_addr_r1_reg_n_0_[1]\,
      I1 => \^e\(0),
      I2 => \app_addr_r2_reg_n_0_[1]\,
      O => \app_addr_r1_reg[9]_0\(1)
    );
\req_col_r[2]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \app_addr_r1_reg_n_0_[2]\,
      I1 => \^e\(0),
      I2 => \app_addr_r2_reg_n_0_[2]\,
      O => \app_addr_r1_reg[9]_0\(2)
    );
\req_col_r[3]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \app_addr_r1_reg_n_0_[3]\,
      I1 => \^e\(0),
      I2 => \app_addr_r2_reg_n_0_[3]\,
      O => \app_addr_r1_reg[9]_0\(3)
    );
\req_col_r[4]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \app_addr_r1_reg_n_0_[4]\,
      I1 => \^e\(0),
      I2 => \app_addr_r2_reg_n_0_[4]\,
      O => \app_addr_r1_reg[9]_0\(4)
    );
\req_col_r[5]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \app_addr_r1_reg_n_0_[5]\,
      I1 => \^e\(0),
      I2 => \app_addr_r2_reg_n_0_[5]\,
      O => \app_addr_r1_reg[9]_0\(5)
    );
\req_col_r[6]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \app_addr_r1_reg_n_0_[6]\,
      I1 => \^e\(0),
      I2 => \app_addr_r2_reg_n_0_[6]\,
      O => \app_addr_r1_reg[9]_0\(6)
    );
\req_col_r[7]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \app_addr_r1_reg_n_0_[7]\,
      I1 => \^e\(0),
      I2 => \app_addr_r2_reg_n_0_[7]\,
      O => \app_addr_r1_reg[9]_0\(7)
    );
\req_col_r[8]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \app_addr_r1_reg_n_0_[8]\,
      I1 => \^e\(0),
      I2 => \app_addr_r2_reg_n_0_[8]\,
      O => \app_addr_r1_reg[9]_0\(8)
    );
\req_col_r[9]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \app_addr_r1_reg_n_0_[9]\,
      I1 => \^e\(0),
      I2 => \app_addr_r2_reg_n_0_[9]\,
      O => \app_addr_r1_reg[9]_0\(9)
    );
\req_data_buf_addr_r[0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"82B282BE828E8282"
    )
        port map (
      I0 => wr_data_buf_addr(0),
      I1 => \^app_cmd_r2\(0),
      I2 => \^app_cmd_r2\(1),
      I3 => \app_addr_r1_reg[0]_0\,
      I4 => \^use_addr\,
      I5 => \strict_mode.rd_data_buf_addr_r_lcl\(0),
      O => reset_reg(0)
    );
\req_data_buf_addr_r[1]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"82BE8282"
    )
        port map (
      I0 => wr_data_buf_addr(1),
      I1 => \^app_cmd_r2\(0),
      I2 => \^app_cmd_r2\(1),
      I3 => \app_addr_r1_reg[0]_0\,
      I4 => \^strict_mode.rd_data_buf_addr_r_lcl_reg[0]\,
      O => reset_reg(1)
    );
\req_data_buf_addr_r[2]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"828282BE82BE8282"
    )
        port map (
      I0 => wr_data_buf_addr(2),
      I1 => \^app_cmd_r2\(0),
      I2 => \^app_cmd_r2\(1),
      I3 => \app_addr_r1_reg[0]_0\,
      I4 => \strict_mode.rd_data_buf_addr_r_lcl\(2),
      I5 => \^strict_mode.rd_data_buf_addr_r_lcl_reg[1]\,
      O => reset_reg(2)
    );
\req_data_buf_addr_r[3]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"888B8B8B8B888888"
    )
        port map (
      I0 => wr_data_buf_addr(3),
      I1 => \write__0\,
      I2 => \app_addr_r1_reg[0]_0\,
      I3 => \^strict_mode.rd_data_buf_addr_r_lcl_reg[1]\,
      I4 => \strict_mode.rd_data_buf_addr_r_lcl\(2),
      I5 => \strict_mode.rd_data_buf_addr_r_lcl\(3),
      O => reset_reg(3)
    );
\req_data_buf_addr_r[3]_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => \^app_cmd_r2\(1),
      I1 => \^app_cmd_r2\(0),
      O => \write__0\
    );
\req_data_buf_addr_r[3]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0800000000000000"
    )
        port map (
      I0 => \strict_mode.rd_data_buf_addr_r_lcl\(1),
      I1 => \strict_mode.rd_data_buf_addr_r_lcl\(0),
      I2 => \^app_cmd_r2\(1),
      I3 => \^app_cmd_r2\(0),
      I4 => \^e\(0),
      I5 => app_en_r2,
      O => \^strict_mode.rd_data_buf_addr_r_lcl_reg[1]\
    );
\req_row_r_lcl[0]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \app_addr_r1_reg_n_0_[10]\,
      I1 => \^e\(0),
      I2 => \app_addr_r2_reg_n_0_[10]\,
      O => \^d\(0)
    );
\req_row_r_lcl[10]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \app_addr_r1_reg_n_0_[20]\,
      I1 => \^e\(0),
      I2 => \app_addr_r2_reg_n_0_[20]\,
      O => \^d\(10)
    );
\req_row_r_lcl[11]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \app_addr_r1_reg_n_0_[21]\,
      I1 => \^e\(0),
      I2 => \app_addr_r2_reg_n_0_[21]\,
      O => \^d\(11)
    );
\req_row_r_lcl[12]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \app_addr_r1_reg_n_0_[22]\,
      I1 => \^e\(0),
      I2 => \app_addr_r2_reg_n_0_[22]\,
      O => \^app_addr_r1_reg[22]_0\
    );
\req_row_r_lcl[13]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \app_addr_r1_reg_n_0_[23]\,
      I1 => \^e\(0),
      I2 => \app_addr_r2_reg_n_0_[23]\,
      O => \^d\(12)
    );
\req_row_r_lcl[1]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \app_addr_r1_reg_n_0_[11]\,
      I1 => \^e\(0),
      I2 => \app_addr_r2_reg_n_0_[11]\,
      O => \^d\(1)
    );
\req_row_r_lcl[2]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \app_addr_r1_reg_n_0_[12]\,
      I1 => \^e\(0),
      I2 => \app_addr_r2_reg_n_0_[12]\,
      O => \^d\(2)
    );
\req_row_r_lcl[3]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \app_addr_r1_reg_n_0_[13]\,
      I1 => \^e\(0),
      I2 => \app_addr_r2_reg_n_0_[13]\,
      O => \^d\(3)
    );
\req_row_r_lcl[4]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \app_addr_r1_reg_n_0_[14]\,
      I1 => \^e\(0),
      I2 => \app_addr_r2_reg_n_0_[14]\,
      O => \^d\(4)
    );
\req_row_r_lcl[5]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \app_addr_r1_reg_n_0_[15]\,
      I1 => \^e\(0),
      I2 => \app_addr_r2_reg_n_0_[15]\,
      O => \^d\(5)
    );
\req_row_r_lcl[6]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \app_addr_r1_reg_n_0_[16]\,
      I1 => \^e\(0),
      I2 => \app_addr_r2_reg_n_0_[16]\,
      O => \^d\(6)
    );
\req_row_r_lcl[7]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \app_addr_r1_reg_n_0_[17]\,
      I1 => \^e\(0),
      I2 => \app_addr_r2_reg_n_0_[17]\,
      O => \^d\(7)
    );
\req_row_r_lcl[8]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \app_addr_r1_reg_n_0_[18]\,
      I1 => \^e\(0),
      I2 => \app_addr_r2_reg_n_0_[18]\,
      O => \^d\(8)
    );
\req_row_r_lcl[9]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \app_addr_r1_reg_n_0_[19]\,
      I1 => \^e\(0),
      I2 => \app_addr_r2_reg_n_0_[19]\,
      O => \^d\(9)
    );
req_wr_r_lcl_i_2: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_cmd_r1(1),
      I1 => \^e\(0),
      I2 => \^app_cmd_r2\(1),
      O => cmd(1)
    );
\row_hit_ns_carry__0_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"B80000B847000047"
    )
        port map (
      I0 => \app_addr_r1_reg_n_0_[23]\,
      I1 => \^e\(0),
      I2 => \app_addr_r2_reg_n_0_[23]\,
      I3 => \^app_addr_r1_reg[22]_0\,
      I4 => row_hit_r_reg(9),
      I5 => row_hit_r_reg(10),
      O => \app_addr_r1_reg[23]_0\(0)
    );
\row_hit_ns_carry__0_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"B80000B847000047"
    )
        port map (
      I0 => \app_addr_r1_reg_n_0_[23]\,
      I1 => \^e\(0),
      I2 => \app_addr_r2_reg_n_0_[23]\,
      I3 => \^app_addr_r1_reg[22]_0\,
      I4 => row_hit_r_reg(14),
      I5 => row_hit_r_reg(15),
      O => \app_addr_r1_reg[23]_1\(0)
    );
\row_hit_ns_carry__0_i_1__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"B80000B847000047"
    )
        port map (
      I0 => \app_addr_r1_reg_n_0_[23]\,
      I1 => \^e\(0),
      I2 => \app_addr_r2_reg_n_0_[23]\,
      I3 => \^app_addr_r1_reg[22]_0\,
      I4 => row_hit_r_reg(16),
      I5 => row_hit_r_reg(17),
      O => \app_addr_r1_reg[23]_2\(0)
    );
\row_hit_ns_carry__0_i_1__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"B80000B847000047"
    )
        port map (
      I0 => \app_addr_r1_reg_n_0_[23]\,
      I1 => \^e\(0),
      I2 => \app_addr_r2_reg_n_0_[23]\,
      I3 => \^app_addr_r1_reg[22]_0\,
      I4 => row_hit_r_reg(18),
      I5 => row_hit_r_reg(19),
      O => \app_addr_r1_reg[23]_3\(0)
    );
\row_hit_ns_carry_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"9009000000009009"
    )
        port map (
      I0 => \^d\(10),
      I1 => row_hit_r_reg(12),
      I2 => row_hit_r_reg(13),
      I3 => \^d\(11),
      I4 => row_hit_r_reg(11),
      I5 => \^d\(9),
      O => \req_row_r_lcl_reg[10]\(0)
    );
row_hit_ns_carry_i_2: unisim.vcomponents.LUT6
    generic map(
      INIT => X"9009000000009009"
    )
        port map (
      I0 => \^d\(7),
      I1 => row_hit_r_reg(7),
      I2 => row_hit_r_reg(8),
      I3 => \^d\(8),
      I4 => row_hit_r_reg(6),
      I5 => \^d\(6),
      O => S(2)
    );
row_hit_ns_carry_i_3: unisim.vcomponents.LUT6
    generic map(
      INIT => X"9009000000009009"
    )
        port map (
      I0 => \^d\(4),
      I1 => row_hit_r_reg(4),
      I2 => row_hit_r_reg(5),
      I3 => \^d\(5),
      I4 => row_hit_r_reg(3),
      I5 => \^d\(3),
      O => S(1)
    );
row_hit_ns_carry_i_4: unisim.vcomponents.LUT6
    generic map(
      INIT => X"9009000000009009"
    )
        port map (
      I0 => \^d\(1),
      I1 => row_hit_r_reg(1),
      I2 => row_hit_r_reg(2),
      I3 => \^d\(2),
      I4 => row_hit_r_reg(0),
      I5 => \^d\(0),
      O => S(0)
    );
\strict_mode.rd_data_buf_addr_r_lcl[0]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FF7F0080"
    )
        port map (
      I0 => app_en_r2,
      I1 => \^e\(0),
      I2 => \^app_cmd_r2\(0),
      I3 => \^app_cmd_r2\(1),
      I4 => \strict_mode.rd_data_buf_addr_r_lcl\(0),
      O => app_en_r2_reg_0
    );
\strict_mode.rd_data_buf_addr_r_lcl[1]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"DFFFFFFF20000000"
    )
        port map (
      I0 => \strict_mode.rd_data_buf_addr_r_lcl\(0),
      I1 => \^app_cmd_r2\(1),
      I2 => \^app_cmd_r2\(0),
      I3 => \^e\(0),
      I4 => app_en_r2,
      I5 => \strict_mode.rd_data_buf_addr_r_lcl\(1),
      O => \^strict_mode.rd_data_buf_addr_r_lcl_reg[0]\
    );
\wr_req_counter.wr_req_cnt_r[0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"9669666666666666"
    )
        port map (
      I0 => \wr_req_counter.wr_req_cnt_r\(0),
      I1 => p_0_in(0),
      I2 => \^app_cmd_r2\(1),
      I3 => \^app_cmd_r2\(0),
      I4 => app_en_r2,
      I5 => \^e\(0),
      O => \wr_req_counter.wr_req_cnt_r_reg[0]\
    );
\wr_req_counter.wr_req_cnt_r[4]_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"69AAAAAA"
    )
        port map (
      I0 => p_0_in(0),
      I1 => \^app_cmd_r2\(1),
      I2 => \^app_cmd_r2\(0),
      I3 => app_en_r2,
      I4 => \^e\(0),
      O => \read_data_indx.rd_data_upd_indx_r_reg\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mig_mig_7series_v4_2_ui_rd_data is
  port (
    \rd_buf_indx.ram_init_done_r_lcl_reg_0\ : out STD_LOGIC;
    \strict_mode.rd_data_buf_addr_r_lcl\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
    ADDRD : out STD_LOGIC_VECTOR ( 3 downto 0 );
    \pointer_ram.pointer_wr_data\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
    \strict_mode.rd_data_buf_addr_r_lcl_reg[0]_0\ : in STD_LOGIC;
    use_addr : in STD_LOGIC;
    app_cmd_r2 : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \strict_mode.rd_data_buf_addr_r_lcl_reg[3]_0\ : in STD_LOGIC;
    \strict_mode.rd_data_buf_addr_r_lcl_reg[0]_1\ : in STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 3 downto 0 );
    wr_data_addr : in STD_LOGIC_VECTOR ( 3 downto 0 );
    \strict_mode.rd_data_buf_addr_r_lcl_reg[1]_0\ : in STD_LOGIC;
    \strict_mode.rd_data_buf_addr_r_lcl_reg[0]_2\ : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of mig_mig_7series_v4_2_ui_rd_data : entity is "mig_7series_v4_2_ui_rd_data";
end mig_mig_7series_v4_2_ui_rd_data;

architecture STRUCTURE of mig_mig_7series_v4_2_ui_rd_data is
  signal \p_0_in__2\ : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal ram_init_addr : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \rd_buf_indx.ram_init_done_ns\ : STD_LOGIC;
  signal \rd_buf_indx.ram_init_done_r_lcl_i_2_n_0\ : STD_LOGIC;
  signal \^rd_buf_indx.ram_init_done_r_lcl_reg_0\ : STD_LOGIC;
  signal \rd_buf_indx.rd_buf_indx_r[4]_i_1_n_0\ : STD_LOGIC;
  signal \rd_buf_indx.rd_buf_indx_r_reg\ : STD_LOGIC_VECTOR ( 4 to 4 );
  signal \^strict_mode.rd_data_buf_addr_r_lcl\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \strict_mode.rd_data_buf_addr_r_lcl[2]_i_1_n_0\ : STD_LOGIC;
  signal \strict_mode.rd_data_buf_addr_r_lcl[3]_i_1_n_0\ : STD_LOGIC;
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \rd_buf_indx.ram_init_done_r_lcl_i_2\ : label is "soft_lutpair1231";
  attribute syn_maxfan : string;
  attribute syn_maxfan of \rd_buf_indx.ram_init_done_r_lcl_reg\ : label is "10";
  attribute SOFT_HLUTNM of \rd_buf_indx.rd_buf_indx_r[0]_i_1\ : label is "soft_lutpair1233";
  attribute SOFT_HLUTNM of \rd_buf_indx.rd_buf_indx_r[1]_i_1\ : label is "soft_lutpair1233";
  attribute SOFT_HLUTNM of \rd_buf_indx.rd_buf_indx_r[2]_i_1\ : label is "soft_lutpair1232";
  attribute SOFT_HLUTNM of \rd_buf_indx.rd_buf_indx_r[3]_i_1\ : label is "soft_lutpair1232";
  attribute SOFT_HLUTNM of \rd_buf_indx.rd_buf_indx_r[4]_i_2\ : label is "soft_lutpair1231";
begin
  \rd_buf_indx.ram_init_done_r_lcl_reg_0\ <= \^rd_buf_indx.ram_init_done_r_lcl_reg_0\;
  \strict_mode.rd_data_buf_addr_r_lcl\(3 downto 0) <= \^strict_mode.rd_data_buf_addr_r_lcl\(3 downto 0);
\pointer_ram.rams[0].RAM32M0_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => wr_data_addr(1),
      I1 => \^rd_buf_indx.ram_init_done_r_lcl_reg_0\,
      I2 => ram_init_addr(1),
      O => \pointer_ram.pointer_wr_data\(1)
    );
\pointer_ram.rams[0].RAM32M0_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => wr_data_addr(0),
      I1 => \^rd_buf_indx.ram_init_done_r_lcl_reg_0\,
      I2 => ram_init_addr(0),
      O => \pointer_ram.pointer_wr_data\(0)
    );
\pointer_ram.rams[0].RAM32M0_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(3),
      I1 => \^rd_buf_indx.ram_init_done_r_lcl_reg_0\,
      I2 => ram_init_addr(3),
      O => ADDRD(3)
    );
\pointer_ram.rams[0].RAM32M0_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(2),
      I1 => \^rd_buf_indx.ram_init_done_r_lcl_reg_0\,
      I2 => ram_init_addr(2),
      O => ADDRD(2)
    );
\pointer_ram.rams[0].RAM32M0_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(1),
      I1 => \^rd_buf_indx.ram_init_done_r_lcl_reg_0\,
      I2 => ram_init_addr(1),
      O => ADDRD(1)
    );
\pointer_ram.rams[0].RAM32M0_i_7\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(0),
      I1 => \^rd_buf_indx.ram_init_done_r_lcl_reg_0\,
      I2 => ram_init_addr(0),
      O => ADDRD(0)
    );
\pointer_ram.rams[1].RAM32M0_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => wr_data_addr(3),
      I1 => \^rd_buf_indx.ram_init_done_r_lcl_reg_0\,
      I2 => ram_init_addr(3),
      O => \pointer_ram.pointer_wr_data\(3)
    );
\pointer_ram.rams[1].RAM32M0_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => wr_data_addr(2),
      I1 => \^rd_buf_indx.ram_init_done_r_lcl_reg_0\,
      I2 => ram_init_addr(2),
      O => \pointer_ram.pointer_wr_data\(2)
    );
\rd_buf_indx.ram_init_done_r_lcl_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0F04"
    )
        port map (
      I0 => \rd_buf_indx.ram_init_done_r_lcl_i_2_n_0\,
      I1 => \rd_buf_indx.rd_buf_indx_r_reg\(4),
      I2 => \strict_mode.rd_data_buf_addr_r_lcl_reg[0]_1\,
      I3 => \^rd_buf_indx.ram_init_done_r_lcl_reg_0\,
      O => \rd_buf_indx.ram_init_done_ns\
    );
\rd_buf_indx.ram_init_done_r_lcl_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7FFF"
    )
        port map (
      I0 => ram_init_addr(2),
      I1 => ram_init_addr(1),
      I2 => ram_init_addr(0),
      I3 => ram_init_addr(3),
      O => \rd_buf_indx.ram_init_done_r_lcl_i_2_n_0\
    );
\rd_buf_indx.ram_init_done_r_lcl_reg\: unisim.vcomponents.FDRE
     port map (
      C => \strict_mode.rd_data_buf_addr_r_lcl_reg[0]_0\,
      CE => '1',
      D => \rd_buf_indx.ram_init_done_ns\,
      Q => \^rd_buf_indx.ram_init_done_r_lcl_reg_0\,
      R => '0'
    );
\rd_buf_indx.rd_buf_indx_r[0]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => ram_init_addr(0),
      O => \p_0_in__2\(0)
    );
\rd_buf_indx.rd_buf_indx_r[1]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => ram_init_addr(0),
      I1 => ram_init_addr(1),
      O => \p_0_in__2\(1)
    );
\rd_buf_indx.rd_buf_indx_r[2]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"78"
    )
        port map (
      I0 => ram_init_addr(0),
      I1 => ram_init_addr(1),
      I2 => ram_init_addr(2),
      O => \p_0_in__2\(2)
    );
\rd_buf_indx.rd_buf_indx_r[3]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7F80"
    )
        port map (
      I0 => ram_init_addr(2),
      I1 => ram_init_addr(1),
      I2 => ram_init_addr(0),
      I3 => ram_init_addr(3),
      O => \p_0_in__2\(3)
    );
\rd_buf_indx.rd_buf_indx_r[4]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \^rd_buf_indx.ram_init_done_r_lcl_reg_0\,
      O => \rd_buf_indx.rd_buf_indx_r[4]_i_1_n_0\
    );
\rd_buf_indx.rd_buf_indx_r[4]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"7FFF8000"
    )
        port map (
      I0 => ram_init_addr(3),
      I1 => ram_init_addr(0),
      I2 => ram_init_addr(1),
      I3 => ram_init_addr(2),
      I4 => \rd_buf_indx.rd_buf_indx_r_reg\(4),
      O => \p_0_in__2\(4)
    );
\rd_buf_indx.rd_buf_indx_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \strict_mode.rd_data_buf_addr_r_lcl_reg[0]_0\,
      CE => \rd_buf_indx.rd_buf_indx_r[4]_i_1_n_0\,
      D => \p_0_in__2\(0),
      Q => ram_init_addr(0),
      R => \strict_mode.rd_data_buf_addr_r_lcl_reg[0]_1\
    );
\rd_buf_indx.rd_buf_indx_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \strict_mode.rd_data_buf_addr_r_lcl_reg[0]_0\,
      CE => \rd_buf_indx.rd_buf_indx_r[4]_i_1_n_0\,
      D => \p_0_in__2\(1),
      Q => ram_init_addr(1),
      R => \strict_mode.rd_data_buf_addr_r_lcl_reg[0]_1\
    );
\rd_buf_indx.rd_buf_indx_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \strict_mode.rd_data_buf_addr_r_lcl_reg[0]_0\,
      CE => \rd_buf_indx.rd_buf_indx_r[4]_i_1_n_0\,
      D => \p_0_in__2\(2),
      Q => ram_init_addr(2),
      R => \strict_mode.rd_data_buf_addr_r_lcl_reg[0]_1\
    );
\rd_buf_indx.rd_buf_indx_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => \strict_mode.rd_data_buf_addr_r_lcl_reg[0]_0\,
      CE => \rd_buf_indx.rd_buf_indx_r[4]_i_1_n_0\,
      D => \p_0_in__2\(3),
      Q => ram_init_addr(3),
      R => \strict_mode.rd_data_buf_addr_r_lcl_reg[0]_1\
    );
\rd_buf_indx.rd_buf_indx_r_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => \strict_mode.rd_data_buf_addr_r_lcl_reg[0]_0\,
      CE => \rd_buf_indx.rd_buf_indx_r[4]_i_1_n_0\,
      D => \p_0_in__2\(4),
      Q => \rd_buf_indx.rd_buf_indx_r_reg\(4),
      R => \strict_mode.rd_data_buf_addr_r_lcl_reg[0]_1\
    );
\strict_mode.rd_data_buf_addr_r_lcl[2]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AA6AAAAAAAAAAAAA"
    )
        port map (
      I0 => \^strict_mode.rd_data_buf_addr_r_lcl\(2),
      I1 => use_addr,
      I2 => app_cmd_r2(0),
      I3 => app_cmd_r2(1),
      I4 => \^strict_mode.rd_data_buf_addr_r_lcl\(0),
      I5 => \^strict_mode.rd_data_buf_addr_r_lcl\(1),
      O => \strict_mode.rd_data_buf_addr_r_lcl[2]_i_1_n_0\
    );
\strict_mode.rd_data_buf_addr_r_lcl[3]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"78"
    )
        port map (
      I0 => \strict_mode.rd_data_buf_addr_r_lcl_reg[3]_0\,
      I1 => \^strict_mode.rd_data_buf_addr_r_lcl\(2),
      I2 => \^strict_mode.rd_data_buf_addr_r_lcl\(3),
      O => \strict_mode.rd_data_buf_addr_r_lcl[3]_i_1_n_0\
    );
\strict_mode.rd_data_buf_addr_r_lcl_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \strict_mode.rd_data_buf_addr_r_lcl_reg[0]_0\,
      CE => '1',
      D => \strict_mode.rd_data_buf_addr_r_lcl_reg[0]_2\,
      Q => \^strict_mode.rd_data_buf_addr_r_lcl\(0),
      R => \strict_mode.rd_data_buf_addr_r_lcl_reg[0]_1\
    );
\strict_mode.rd_data_buf_addr_r_lcl_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \strict_mode.rd_data_buf_addr_r_lcl_reg[0]_0\,
      CE => '1',
      D => \strict_mode.rd_data_buf_addr_r_lcl_reg[1]_0\,
      Q => \^strict_mode.rd_data_buf_addr_r_lcl\(1),
      R => \strict_mode.rd_data_buf_addr_r_lcl_reg[0]_1\
    );
\strict_mode.rd_data_buf_addr_r_lcl_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \strict_mode.rd_data_buf_addr_r_lcl_reg[0]_0\,
      CE => '1',
      D => \strict_mode.rd_data_buf_addr_r_lcl[2]_i_1_n_0\,
      Q => \^strict_mode.rd_data_buf_addr_r_lcl\(2),
      R => \strict_mode.rd_data_buf_addr_r_lcl_reg[0]_1\
    );
\strict_mode.rd_data_buf_addr_r_lcl_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => \strict_mode.rd_data_buf_addr_r_lcl_reg[0]_0\,
      CE => '1',
      D => \strict_mode.rd_data_buf_addr_r_lcl[3]_i_1_n_0\,
      Q => \^strict_mode.rd_data_buf_addr_r_lcl\(3),
      R => \strict_mode.rd_data_buf_addr_r_lcl_reg[0]_1\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mig_mig_7series_v4_2_ui_wr_data is
  port (
    wr_data_buf_addr : out STD_LOGIC_VECTOR ( 3 downto 0 );
    p_0_in : out STD_LOGIC_VECTOR ( 0 to 0 );
    app_wdf_rdy : out STD_LOGIC;
    app_rdy_ns : out STD_LOGIC;
    \wr_req_counter.wr_req_cnt_r_reg[1]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    Q : out STD_LOGIC_VECTOR ( 3 downto 0 );
    \write_buffer.wr_buf_out_data_reg[575]_0\ : out STD_LOGIC_VECTOR ( 575 downto 0 );
    \wr_req_counter.wr_req_cnt_r_reg[0]_0\ : in STD_LOGIC;
    \pointer_ram.pointer_we\ : in STD_LOGIC;
    \pointer_ram.pointer_wr_data\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
    ADDRD : in STD_LOGIC_VECTOR ( 3 downto 0 );
    wr_data_addr : in STD_LOGIC_VECTOR ( 3 downto 0 );
    E : in STD_LOGIC_VECTOR ( 0 to 0 );
    accept_ns : in STD_LOGIC;
    \wr_req_counter.wr_req_cnt_r_reg[0]_1\ : in STD_LOGIC;
    wr_accepted : in STD_LOGIC;
    \wr_req_counter.wr_req_cnt_r_reg[4]_0\ : in STD_LOGIC;
    app_rdy_r_reg : in STD_LOGIC;
    app_wdf_wren : in STD_LOGIC;
    app_wdf_end : in STD_LOGIC;
    ram_init_done_r : in STD_LOGIC;
    app_wdf_mask : in STD_LOGIC_VECTOR ( 63 downto 0 );
    app_wdf_data : in STD_LOGIC_VECTOR ( 511 downto 0 );
    \wr_req_counter.wr_req_cnt_r_reg[0]_2\ : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of mig_mig_7series_v4_2_ui_wr_data : entity is "mig_7series_v4_2_ui_wr_data";
end mig_mig_7series_v4_2_ui_wr_data;

architecture STRUCTURE of mig_mig_7series_v4_2_ui_wr_data is
  signal \^q\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal app_rdy_r_i_2_n_0 : STD_LOGIC;
  signal app_rdy_r_i_3_n_0 : STD_LOGIC;
  signal app_wdf_data_r1 : STD_LOGIC_VECTOR ( 511 downto 0 );
  signal app_wdf_end_ns1 : STD_LOGIC;
  signal app_wdf_end_r1 : STD_LOGIC;
  signal app_wdf_mask_r1 : STD_LOGIC_VECTOR ( 63 downto 0 );
  signal app_wdf_rdy_r_copy1 : STD_LOGIC;
  signal app_wdf_rdy_r_copy2 : STD_LOGIC;
  signal app_wdf_rdy_r_copy3 : STD_LOGIC;
  signal app_wdf_wren_ns1 : STD_LOGIC;
  signal app_wdf_wren_r1 : STD_LOGIC;
  signal \data_buf_address_counter.data_buf_addr_cnt_r_reg\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \occupied_counter.occ_cnt[15]_i_1_n_0\ : STD_LOGIC;
  signal \occupied_counter.occ_cnt_reg_n_0_[0]\ : STD_LOGIC;
  signal \occupied_counter.occ_cnt_reg_n_0_[10]\ : STD_LOGIC;
  signal \occupied_counter.occ_cnt_reg_n_0_[11]\ : STD_LOGIC;
  signal \occupied_counter.occ_cnt_reg_n_0_[12]\ : STD_LOGIC;
  signal \occupied_counter.occ_cnt_reg_n_0_[13]\ : STD_LOGIC;
  signal \occupied_counter.occ_cnt_reg_n_0_[15]\ : STD_LOGIC;
  signal \occupied_counter.occ_cnt_reg_n_0_[1]\ : STD_LOGIC;
  signal \occupied_counter.occ_cnt_reg_n_0_[2]\ : STD_LOGIC;
  signal \occupied_counter.occ_cnt_reg_n_0_[3]\ : STD_LOGIC;
  signal \occupied_counter.occ_cnt_reg_n_0_[4]\ : STD_LOGIC;
  signal \occupied_counter.occ_cnt_reg_n_0_[5]\ : STD_LOGIC;
  signal \occupied_counter.occ_cnt_reg_n_0_[6]\ : STD_LOGIC;
  signal \occupied_counter.occ_cnt_reg_n_0_[7]\ : STD_LOGIC;
  signal \occupied_counter.occ_cnt_reg_n_0_[8]\ : STD_LOGIC;
  signal \occupied_counter.occ_cnt_reg_n_0_[9]\ : STD_LOGIC;
  signal \^p_0_in\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \p_0_in__0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \p_0_in__0_0\ : STD_LOGIC_VECTOR ( 1 to 1 );
  signal \p_0_in__0__0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \p_0_in__1\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal p_1_in : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal p_4_in : STD_LOGIC;
  signal wb_wr_data_addr_w : STD_LOGIC_VECTOR ( 4 downto 1 );
  signal wdf_rdy_ns : STD_LOGIC;
  signal wr_buf_out_data_w : STD_LOGIC_VECTOR ( 575 downto 0 );
  signal wr_data_pntr : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \wr_req_counter.wr_req_cnt_r\ : STD_LOGIC_VECTOR ( 4 downto 2 );
  signal \wr_req_counter.wr_req_cnt_r[1]_i_1_n_0\ : STD_LOGIC;
  signal \wr_req_counter.wr_req_cnt_r[2]_i_1_n_0\ : STD_LOGIC;
  signal \wr_req_counter.wr_req_cnt_r[3]_i_1_n_0\ : STD_LOGIC;
  signal \wr_req_counter.wr_req_cnt_r[4]_i_1_n_0\ : STD_LOGIC;
  signal \wr_req_counter.wr_req_cnt_r[4]_i_2_n_0\ : STD_LOGIC;
  signal \^wr_req_counter.wr_req_cnt_r_reg[1]_0\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \write_buffer.wr_buf_in_data\ : STD_LOGIC_VECTOR ( 575 downto 0 );
  signal \write_data_control.wb_wr_data_addr0_ns\ : STD_LOGIC;
  signal \write_data_control.wb_wr_data_addr0_r\ : STD_LOGIC;
  signal \write_data_control.wb_wr_data_addr_r\ : STD_LOGIC_VECTOR ( 4 downto 1 );
  signal \write_data_control.wr_data_addr_le\ : STD_LOGIC;
  signal \write_data_control.wr_data_indx_r[3]_i_3_n_0\ : STD_LOGIC;
  signal \write_data_control.wr_data_indx_r_reg\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \NLW_pointer_ram.rams[0].RAM32M0_DOA_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_pointer_ram.rams[0].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_pointer_ram.rams[1].RAM32M0_DOA_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_pointer_ram.rams[1].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_write_buffer.wr_buffer_ram[0].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_write_buffer.wr_buffer_ram[10].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_write_buffer.wr_buffer_ram[11].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_write_buffer.wr_buffer_ram[12].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_write_buffer.wr_buffer_ram[13].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_write_buffer.wr_buffer_ram[14].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_write_buffer.wr_buffer_ram[15].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_write_buffer.wr_buffer_ram[16].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_write_buffer.wr_buffer_ram[17].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_write_buffer.wr_buffer_ram[18].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_write_buffer.wr_buffer_ram[19].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_write_buffer.wr_buffer_ram[1].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_write_buffer.wr_buffer_ram[20].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_write_buffer.wr_buffer_ram[21].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_write_buffer.wr_buffer_ram[22].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_write_buffer.wr_buffer_ram[23].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_write_buffer.wr_buffer_ram[24].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_write_buffer.wr_buffer_ram[25].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_write_buffer.wr_buffer_ram[26].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_write_buffer.wr_buffer_ram[27].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_write_buffer.wr_buffer_ram[28].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_write_buffer.wr_buffer_ram[29].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_write_buffer.wr_buffer_ram[2].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_write_buffer.wr_buffer_ram[30].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_write_buffer.wr_buffer_ram[31].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_write_buffer.wr_buffer_ram[32].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_write_buffer.wr_buffer_ram[33].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_write_buffer.wr_buffer_ram[34].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_write_buffer.wr_buffer_ram[35].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_write_buffer.wr_buffer_ram[36].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_write_buffer.wr_buffer_ram[37].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_write_buffer.wr_buffer_ram[38].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_write_buffer.wr_buffer_ram[39].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_write_buffer.wr_buffer_ram[3].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_write_buffer.wr_buffer_ram[40].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_write_buffer.wr_buffer_ram[41].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_write_buffer.wr_buffer_ram[42].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_write_buffer.wr_buffer_ram[43].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_write_buffer.wr_buffer_ram[44].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_write_buffer.wr_buffer_ram[45].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_write_buffer.wr_buffer_ram[46].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_write_buffer.wr_buffer_ram[47].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_write_buffer.wr_buffer_ram[48].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_write_buffer.wr_buffer_ram[49].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_write_buffer.wr_buffer_ram[4].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_write_buffer.wr_buffer_ram[50].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_write_buffer.wr_buffer_ram[51].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_write_buffer.wr_buffer_ram[52].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_write_buffer.wr_buffer_ram[53].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_write_buffer.wr_buffer_ram[54].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_write_buffer.wr_buffer_ram[55].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_write_buffer.wr_buffer_ram[56].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_write_buffer.wr_buffer_ram[57].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_write_buffer.wr_buffer_ram[58].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_write_buffer.wr_buffer_ram[59].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_write_buffer.wr_buffer_ram[5].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_write_buffer.wr_buffer_ram[60].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_write_buffer.wr_buffer_ram[61].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_write_buffer.wr_buffer_ram[62].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_write_buffer.wr_buffer_ram[63].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_write_buffer.wr_buffer_ram[64].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_write_buffer.wr_buffer_ram[65].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_write_buffer.wr_buffer_ram[66].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_write_buffer.wr_buffer_ram[67].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_write_buffer.wr_buffer_ram[68].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_write_buffer.wr_buffer_ram[69].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_write_buffer.wr_buffer_ram[6].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_write_buffer.wr_buffer_ram[70].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_write_buffer.wr_buffer_ram[71].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_write_buffer.wr_buffer_ram[72].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_write_buffer.wr_buffer_ram[73].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_write_buffer.wr_buffer_ram[74].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_write_buffer.wr_buffer_ram[75].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_write_buffer.wr_buffer_ram[76].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_write_buffer.wr_buffer_ram[77].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_write_buffer.wr_buffer_ram[78].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_write_buffer.wr_buffer_ram[79].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_write_buffer.wr_buffer_ram[7].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_write_buffer.wr_buffer_ram[80].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_write_buffer.wr_buffer_ram[81].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_write_buffer.wr_buffer_ram[82].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_write_buffer.wr_buffer_ram[83].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_write_buffer.wr_buffer_ram[84].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_write_buffer.wr_buffer_ram[85].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_write_buffer.wr_buffer_ram[86].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_write_buffer.wr_buffer_ram[87].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_write_buffer.wr_buffer_ram[88].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_write_buffer.wr_buffer_ram[89].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_write_buffer.wr_buffer_ram[8].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_write_buffer.wr_buffer_ram[90].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_write_buffer.wr_buffer_ram[91].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_write_buffer.wr_buffer_ram[92].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_write_buffer.wr_buffer_ram[93].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_write_buffer.wr_buffer_ram[94].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_write_buffer.wr_buffer_ram[95].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_write_buffer.wr_buffer_ram[9].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  attribute equivalent_register_removal : string;
  attribute equivalent_register_removal of app_wdf_rdy_r_copy1_reg : label is "no";
  attribute equivalent_register_removal of app_wdf_rdy_r_copy2_reg : label is "no";
  attribute equivalent_register_removal of app_wdf_rdy_r_copy3_reg : label is "no";
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \data_buf_address_counter.data_buf_addr_cnt_r[0]_i_1\ : label is "soft_lutpair1241";
  attribute SOFT_HLUTNM of \data_buf_address_counter.data_buf_addr_cnt_r[1]_i_1\ : label is "soft_lutpair1241";
  attribute SOFT_HLUTNM of \data_buf_address_counter.data_buf_addr_cnt_r[2]_i_1\ : label is "soft_lutpair1240";
  attribute SOFT_HLUTNM of \data_buf_address_counter.data_buf_addr_cnt_r[3]_i_2\ : label is "soft_lutpair1240";
  attribute SOFT_HLUTNM of \occupied_counter.app_wdf_rdy_r_i_2\ : label is "soft_lutpair1234";
  attribute equivalent_register_removal of \occupied_counter.app_wdf_rdy_r_reg\ : label is "no";
  attribute SOFT_HLUTNM of \occupied_counter.occ_cnt[0]_i_1\ : label is "soft_lutpair1236";
  attribute SOFT_HLUTNM of \occupied_counter.occ_cnt[13]_i_1\ : label is "soft_lutpair1237";
  attribute SOFT_HLUTNM of \occupied_counter.occ_cnt[15]_i_2\ : label is "soft_lutpair1237";
  attribute SOFT_HLUTNM of \occupied_counter.occ_cnt[2]_i_1\ : label is "soft_lutpair1236";
  attribute SOFT_HLUTNM of \occupied_counter.occ_cnt[8]_i_1\ : label is "soft_lutpair1234";
  attribute BOX_TYPE : string;
  attribute BOX_TYPE of \pointer_ram.rams[0].RAM32M0\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \pointer_ram.rams[1].RAM32M0\ : label is "PRIMITIVE";
  attribute SOFT_HLUTNM of \read_data_indx.rd_data_indx_r[0]_i_1\ : label is "soft_lutpair1242";
  attribute SOFT_HLUTNM of \read_data_indx.rd_data_indx_r[1]_i_1\ : label is "soft_lutpair1242";
  attribute SOFT_HLUTNM of \read_data_indx.rd_data_indx_r[2]_i_1\ : label is "soft_lutpair1239";
  attribute SOFT_HLUTNM of \read_data_indx.rd_data_indx_r[3]_i_1\ : label is "soft_lutpair1239";
  attribute SOFT_HLUTNM of \wr_req_counter.wr_req_cnt_r[1]_i_1\ : label is "soft_lutpair1235";
  attribute SOFT_HLUTNM of \wr_req_counter.wr_req_cnt_r[2]_i_1\ : label is "soft_lutpair1235";
  attribute BOX_TYPE of \write_buffer.wr_buffer_ram[0].RAM32M0\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \write_buffer.wr_buffer_ram[10].RAM32M0\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \write_buffer.wr_buffer_ram[11].RAM32M0\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \write_buffer.wr_buffer_ram[12].RAM32M0\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \write_buffer.wr_buffer_ram[13].RAM32M0\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \write_buffer.wr_buffer_ram[14].RAM32M0\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \write_buffer.wr_buffer_ram[15].RAM32M0\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \write_buffer.wr_buffer_ram[16].RAM32M0\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \write_buffer.wr_buffer_ram[17].RAM32M0\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \write_buffer.wr_buffer_ram[18].RAM32M0\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \write_buffer.wr_buffer_ram[19].RAM32M0\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \write_buffer.wr_buffer_ram[1].RAM32M0\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \write_buffer.wr_buffer_ram[20].RAM32M0\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \write_buffer.wr_buffer_ram[21].RAM32M0\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \write_buffer.wr_buffer_ram[22].RAM32M0\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \write_buffer.wr_buffer_ram[23].RAM32M0\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \write_buffer.wr_buffer_ram[24].RAM32M0\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \write_buffer.wr_buffer_ram[25].RAM32M0\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \write_buffer.wr_buffer_ram[26].RAM32M0\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \write_buffer.wr_buffer_ram[27].RAM32M0\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \write_buffer.wr_buffer_ram[28].RAM32M0\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \write_buffer.wr_buffer_ram[29].RAM32M0\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \write_buffer.wr_buffer_ram[2].RAM32M0\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \write_buffer.wr_buffer_ram[30].RAM32M0\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \write_buffer.wr_buffer_ram[31].RAM32M0\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \write_buffer.wr_buffer_ram[32].RAM32M0\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \write_buffer.wr_buffer_ram[33].RAM32M0\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \write_buffer.wr_buffer_ram[34].RAM32M0\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \write_buffer.wr_buffer_ram[35].RAM32M0\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \write_buffer.wr_buffer_ram[36].RAM32M0\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \write_buffer.wr_buffer_ram[37].RAM32M0\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \write_buffer.wr_buffer_ram[38].RAM32M0\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \write_buffer.wr_buffer_ram[39].RAM32M0\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \write_buffer.wr_buffer_ram[3].RAM32M0\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \write_buffer.wr_buffer_ram[40].RAM32M0\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \write_buffer.wr_buffer_ram[41].RAM32M0\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \write_buffer.wr_buffer_ram[42].RAM32M0\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \write_buffer.wr_buffer_ram[43].RAM32M0\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \write_buffer.wr_buffer_ram[44].RAM32M0\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \write_buffer.wr_buffer_ram[45].RAM32M0\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \write_buffer.wr_buffer_ram[46].RAM32M0\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \write_buffer.wr_buffer_ram[47].RAM32M0\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \write_buffer.wr_buffer_ram[48].RAM32M0\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \write_buffer.wr_buffer_ram[49].RAM32M0\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \write_buffer.wr_buffer_ram[4].RAM32M0\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \write_buffer.wr_buffer_ram[50].RAM32M0\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \write_buffer.wr_buffer_ram[51].RAM32M0\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \write_buffer.wr_buffer_ram[52].RAM32M0\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \write_buffer.wr_buffer_ram[53].RAM32M0\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \write_buffer.wr_buffer_ram[54].RAM32M0\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \write_buffer.wr_buffer_ram[55].RAM32M0\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \write_buffer.wr_buffer_ram[56].RAM32M0\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \write_buffer.wr_buffer_ram[57].RAM32M0\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \write_buffer.wr_buffer_ram[58].RAM32M0\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \write_buffer.wr_buffer_ram[59].RAM32M0\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \write_buffer.wr_buffer_ram[5].RAM32M0\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \write_buffer.wr_buffer_ram[60].RAM32M0\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \write_buffer.wr_buffer_ram[61].RAM32M0\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \write_buffer.wr_buffer_ram[62].RAM32M0\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \write_buffer.wr_buffer_ram[63].RAM32M0\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \write_buffer.wr_buffer_ram[64].RAM32M0\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \write_buffer.wr_buffer_ram[65].RAM32M0\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \write_buffer.wr_buffer_ram[66].RAM32M0\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \write_buffer.wr_buffer_ram[67].RAM32M0\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \write_buffer.wr_buffer_ram[68].RAM32M0\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \write_buffer.wr_buffer_ram[69].RAM32M0\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \write_buffer.wr_buffer_ram[6].RAM32M0\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \write_buffer.wr_buffer_ram[70].RAM32M0\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \write_buffer.wr_buffer_ram[71].RAM32M0\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \write_buffer.wr_buffer_ram[72].RAM32M0\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \write_buffer.wr_buffer_ram[73].RAM32M0\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \write_buffer.wr_buffer_ram[74].RAM32M0\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \write_buffer.wr_buffer_ram[75].RAM32M0\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \write_buffer.wr_buffer_ram[76].RAM32M0\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \write_buffer.wr_buffer_ram[77].RAM32M0\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \write_buffer.wr_buffer_ram[78].RAM32M0\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \write_buffer.wr_buffer_ram[79].RAM32M0\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \write_buffer.wr_buffer_ram[7].RAM32M0\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \write_buffer.wr_buffer_ram[80].RAM32M0\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \write_buffer.wr_buffer_ram[81].RAM32M0\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \write_buffer.wr_buffer_ram[82].RAM32M0\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \write_buffer.wr_buffer_ram[83].RAM32M0\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \write_buffer.wr_buffer_ram[84].RAM32M0\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \write_buffer.wr_buffer_ram[85].RAM32M0\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \write_buffer.wr_buffer_ram[86].RAM32M0\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \write_buffer.wr_buffer_ram[87].RAM32M0\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \write_buffer.wr_buffer_ram[88].RAM32M0\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \write_buffer.wr_buffer_ram[89].RAM32M0\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \write_buffer.wr_buffer_ram[8].RAM32M0\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \write_buffer.wr_buffer_ram[90].RAM32M0\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \write_buffer.wr_buffer_ram[91].RAM32M0\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \write_buffer.wr_buffer_ram[92].RAM32M0\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \write_buffer.wr_buffer_ram[93].RAM32M0\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \write_buffer.wr_buffer_ram[94].RAM32M0\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \write_buffer.wr_buffer_ram[95].RAM32M0\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \write_buffer.wr_buffer_ram[9].RAM32M0\ : label is "PRIMITIVE";
  attribute SOFT_HLUTNM of \write_data_control.wr_data_indx_r[2]_i_1\ : label is "soft_lutpair1238";
  attribute SOFT_HLUTNM of \write_data_control.wr_data_indx_r[3]_i_2\ : label is "soft_lutpair1238";
begin
  Q(3 downto 0) <= \^q\(3 downto 0);
  p_0_in(0) <= \^p_0_in\(0);
  \wr_req_counter.wr_req_cnt_r_reg[1]_0\(1 downto 0) <= \^wr_req_counter.wr_req_cnt_r_reg[1]_0\(1 downto 0);
app_rdy_r_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFCCC8CCCC"
    )
        port map (
      I0 => \wr_req_counter.wr_req_cnt_r[3]_i_1_n_0\,
      I1 => accept_ns,
      I2 => \wr_req_counter.wr_req_cnt_r[1]_i_1_n_0\,
      I3 => \wr_req_counter.wr_req_cnt_r_reg[0]_1\,
      I4 => app_rdy_r_i_2_n_0,
      I5 => app_rdy_r_i_3_n_0,
      O => app_rdy_ns
    );
app_rdy_r_i_2: unisim.vcomponents.LUT6
    generic map(
      INIT => X"6AAAAAA9AAAAAAAA"
    )
        port map (
      I0 => \wr_req_counter.wr_req_cnt_r\(4),
      I1 => \wr_req_counter.wr_req_cnt_r\(3),
      I2 => \wr_req_counter.wr_req_cnt_r\(2),
      I3 => \^wr_req_counter.wr_req_cnt_r_reg[1]_0\(1),
      I4 => app_rdy_r_reg,
      I5 => \wr_req_counter.wr_req_cnt_r_reg[4]_0\,
      O => app_rdy_r_i_2_n_0
    );
app_rdy_r_i_3: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AA2AAAAA88A22288"
    )
        port map (
      I0 => accept_ns,
      I1 => \^wr_req_counter.wr_req_cnt_r_reg[1]_0\(0),
      I2 => \^wr_req_counter.wr_req_cnt_r_reg[1]_0\(1),
      I3 => \^p_0_in\(0),
      I4 => wr_accepted,
      I5 => \wr_req_counter.wr_req_cnt_r\(2),
      O => app_rdy_r_i_3_n_0
    );
\app_wdf_data_r1_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(0),
      Q => app_wdf_data_r1(0),
      R => '0'
    );
\app_wdf_data_r1_reg[100]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(100),
      Q => app_wdf_data_r1(100),
      R => '0'
    );
\app_wdf_data_r1_reg[101]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(101),
      Q => app_wdf_data_r1(101),
      R => '0'
    );
\app_wdf_data_r1_reg[102]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(102),
      Q => app_wdf_data_r1(102),
      R => '0'
    );
\app_wdf_data_r1_reg[103]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(103),
      Q => app_wdf_data_r1(103),
      R => '0'
    );
\app_wdf_data_r1_reg[104]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(104),
      Q => app_wdf_data_r1(104),
      R => '0'
    );
\app_wdf_data_r1_reg[105]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(105),
      Q => app_wdf_data_r1(105),
      R => '0'
    );
\app_wdf_data_r1_reg[106]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(106),
      Q => app_wdf_data_r1(106),
      R => '0'
    );
\app_wdf_data_r1_reg[107]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(107),
      Q => app_wdf_data_r1(107),
      R => '0'
    );
\app_wdf_data_r1_reg[108]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(108),
      Q => app_wdf_data_r1(108),
      R => '0'
    );
\app_wdf_data_r1_reg[109]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(109),
      Q => app_wdf_data_r1(109),
      R => '0'
    );
\app_wdf_data_r1_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(10),
      Q => app_wdf_data_r1(10),
      R => '0'
    );
\app_wdf_data_r1_reg[110]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(110),
      Q => app_wdf_data_r1(110),
      R => '0'
    );
\app_wdf_data_r1_reg[111]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(111),
      Q => app_wdf_data_r1(111),
      R => '0'
    );
\app_wdf_data_r1_reg[112]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(112),
      Q => app_wdf_data_r1(112),
      R => '0'
    );
\app_wdf_data_r1_reg[113]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(113),
      Q => app_wdf_data_r1(113),
      R => '0'
    );
\app_wdf_data_r1_reg[114]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(114),
      Q => app_wdf_data_r1(114),
      R => '0'
    );
\app_wdf_data_r1_reg[115]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(115),
      Q => app_wdf_data_r1(115),
      R => '0'
    );
\app_wdf_data_r1_reg[116]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(116),
      Q => app_wdf_data_r1(116),
      R => '0'
    );
\app_wdf_data_r1_reg[117]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(117),
      Q => app_wdf_data_r1(117),
      R => '0'
    );
\app_wdf_data_r1_reg[118]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(118),
      Q => app_wdf_data_r1(118),
      R => '0'
    );
\app_wdf_data_r1_reg[119]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(119),
      Q => app_wdf_data_r1(119),
      R => '0'
    );
\app_wdf_data_r1_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(11),
      Q => app_wdf_data_r1(11),
      R => '0'
    );
\app_wdf_data_r1_reg[120]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(120),
      Q => app_wdf_data_r1(120),
      R => '0'
    );
\app_wdf_data_r1_reg[121]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(121),
      Q => app_wdf_data_r1(121),
      R => '0'
    );
\app_wdf_data_r1_reg[122]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(122),
      Q => app_wdf_data_r1(122),
      R => '0'
    );
\app_wdf_data_r1_reg[123]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(123),
      Q => app_wdf_data_r1(123),
      R => '0'
    );
\app_wdf_data_r1_reg[124]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(124),
      Q => app_wdf_data_r1(124),
      R => '0'
    );
\app_wdf_data_r1_reg[125]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(125),
      Q => app_wdf_data_r1(125),
      R => '0'
    );
\app_wdf_data_r1_reg[126]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(126),
      Q => app_wdf_data_r1(126),
      R => '0'
    );
\app_wdf_data_r1_reg[127]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(127),
      Q => app_wdf_data_r1(127),
      R => '0'
    );
\app_wdf_data_r1_reg[128]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(128),
      Q => app_wdf_data_r1(128),
      R => '0'
    );
\app_wdf_data_r1_reg[129]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(129),
      Q => app_wdf_data_r1(129),
      R => '0'
    );
\app_wdf_data_r1_reg[12]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(12),
      Q => app_wdf_data_r1(12),
      R => '0'
    );
\app_wdf_data_r1_reg[130]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(130),
      Q => app_wdf_data_r1(130),
      R => '0'
    );
\app_wdf_data_r1_reg[131]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(131),
      Q => app_wdf_data_r1(131),
      R => '0'
    );
\app_wdf_data_r1_reg[132]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(132),
      Q => app_wdf_data_r1(132),
      R => '0'
    );
\app_wdf_data_r1_reg[133]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(133),
      Q => app_wdf_data_r1(133),
      R => '0'
    );
\app_wdf_data_r1_reg[134]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(134),
      Q => app_wdf_data_r1(134),
      R => '0'
    );
\app_wdf_data_r1_reg[135]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(135),
      Q => app_wdf_data_r1(135),
      R => '0'
    );
\app_wdf_data_r1_reg[136]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(136),
      Q => app_wdf_data_r1(136),
      R => '0'
    );
\app_wdf_data_r1_reg[137]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(137),
      Q => app_wdf_data_r1(137),
      R => '0'
    );
\app_wdf_data_r1_reg[138]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(138),
      Q => app_wdf_data_r1(138),
      R => '0'
    );
\app_wdf_data_r1_reg[139]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(139),
      Q => app_wdf_data_r1(139),
      R => '0'
    );
\app_wdf_data_r1_reg[13]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(13),
      Q => app_wdf_data_r1(13),
      R => '0'
    );
\app_wdf_data_r1_reg[140]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(140),
      Q => app_wdf_data_r1(140),
      R => '0'
    );
\app_wdf_data_r1_reg[141]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(141),
      Q => app_wdf_data_r1(141),
      R => '0'
    );
\app_wdf_data_r1_reg[142]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(142),
      Q => app_wdf_data_r1(142),
      R => '0'
    );
\app_wdf_data_r1_reg[143]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(143),
      Q => app_wdf_data_r1(143),
      R => '0'
    );
\app_wdf_data_r1_reg[144]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(144),
      Q => app_wdf_data_r1(144),
      R => '0'
    );
\app_wdf_data_r1_reg[145]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(145),
      Q => app_wdf_data_r1(145),
      R => '0'
    );
\app_wdf_data_r1_reg[146]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(146),
      Q => app_wdf_data_r1(146),
      R => '0'
    );
\app_wdf_data_r1_reg[147]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(147),
      Q => app_wdf_data_r1(147),
      R => '0'
    );
\app_wdf_data_r1_reg[148]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(148),
      Q => app_wdf_data_r1(148),
      R => '0'
    );
\app_wdf_data_r1_reg[149]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(149),
      Q => app_wdf_data_r1(149),
      R => '0'
    );
\app_wdf_data_r1_reg[14]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(14),
      Q => app_wdf_data_r1(14),
      R => '0'
    );
\app_wdf_data_r1_reg[150]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(150),
      Q => app_wdf_data_r1(150),
      R => '0'
    );
\app_wdf_data_r1_reg[151]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(151),
      Q => app_wdf_data_r1(151),
      R => '0'
    );
\app_wdf_data_r1_reg[152]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(152),
      Q => app_wdf_data_r1(152),
      R => '0'
    );
\app_wdf_data_r1_reg[153]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(153),
      Q => app_wdf_data_r1(153),
      R => '0'
    );
\app_wdf_data_r1_reg[154]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(154),
      Q => app_wdf_data_r1(154),
      R => '0'
    );
\app_wdf_data_r1_reg[155]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(155),
      Q => app_wdf_data_r1(155),
      R => '0'
    );
\app_wdf_data_r1_reg[156]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(156),
      Q => app_wdf_data_r1(156),
      R => '0'
    );
\app_wdf_data_r1_reg[157]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(157),
      Q => app_wdf_data_r1(157),
      R => '0'
    );
\app_wdf_data_r1_reg[158]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(158),
      Q => app_wdf_data_r1(158),
      R => '0'
    );
\app_wdf_data_r1_reg[159]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(159),
      Q => app_wdf_data_r1(159),
      R => '0'
    );
\app_wdf_data_r1_reg[15]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(15),
      Q => app_wdf_data_r1(15),
      R => '0'
    );
\app_wdf_data_r1_reg[160]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(160),
      Q => app_wdf_data_r1(160),
      R => '0'
    );
\app_wdf_data_r1_reg[161]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(161),
      Q => app_wdf_data_r1(161),
      R => '0'
    );
\app_wdf_data_r1_reg[162]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(162),
      Q => app_wdf_data_r1(162),
      R => '0'
    );
\app_wdf_data_r1_reg[163]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(163),
      Q => app_wdf_data_r1(163),
      R => '0'
    );
\app_wdf_data_r1_reg[164]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(164),
      Q => app_wdf_data_r1(164),
      R => '0'
    );
\app_wdf_data_r1_reg[165]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(165),
      Q => app_wdf_data_r1(165),
      R => '0'
    );
\app_wdf_data_r1_reg[166]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(166),
      Q => app_wdf_data_r1(166),
      R => '0'
    );
\app_wdf_data_r1_reg[167]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(167),
      Q => app_wdf_data_r1(167),
      R => '0'
    );
\app_wdf_data_r1_reg[168]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(168),
      Q => app_wdf_data_r1(168),
      R => '0'
    );
\app_wdf_data_r1_reg[169]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(169),
      Q => app_wdf_data_r1(169),
      R => '0'
    );
\app_wdf_data_r1_reg[16]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(16),
      Q => app_wdf_data_r1(16),
      R => '0'
    );
\app_wdf_data_r1_reg[170]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(170),
      Q => app_wdf_data_r1(170),
      R => '0'
    );
\app_wdf_data_r1_reg[171]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(171),
      Q => app_wdf_data_r1(171),
      R => '0'
    );
\app_wdf_data_r1_reg[172]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(172),
      Q => app_wdf_data_r1(172),
      R => '0'
    );
\app_wdf_data_r1_reg[173]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(173),
      Q => app_wdf_data_r1(173),
      R => '0'
    );
\app_wdf_data_r1_reg[174]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(174),
      Q => app_wdf_data_r1(174),
      R => '0'
    );
\app_wdf_data_r1_reg[175]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(175),
      Q => app_wdf_data_r1(175),
      R => '0'
    );
\app_wdf_data_r1_reg[176]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(176),
      Q => app_wdf_data_r1(176),
      R => '0'
    );
\app_wdf_data_r1_reg[177]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(177),
      Q => app_wdf_data_r1(177),
      R => '0'
    );
\app_wdf_data_r1_reg[178]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(178),
      Q => app_wdf_data_r1(178),
      R => '0'
    );
\app_wdf_data_r1_reg[179]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(179),
      Q => app_wdf_data_r1(179),
      R => '0'
    );
\app_wdf_data_r1_reg[17]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(17),
      Q => app_wdf_data_r1(17),
      R => '0'
    );
\app_wdf_data_r1_reg[180]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(180),
      Q => app_wdf_data_r1(180),
      R => '0'
    );
\app_wdf_data_r1_reg[181]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(181),
      Q => app_wdf_data_r1(181),
      R => '0'
    );
\app_wdf_data_r1_reg[182]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(182),
      Q => app_wdf_data_r1(182),
      R => '0'
    );
\app_wdf_data_r1_reg[183]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(183),
      Q => app_wdf_data_r1(183),
      R => '0'
    );
\app_wdf_data_r1_reg[184]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(184),
      Q => app_wdf_data_r1(184),
      R => '0'
    );
\app_wdf_data_r1_reg[185]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(185),
      Q => app_wdf_data_r1(185),
      R => '0'
    );
\app_wdf_data_r1_reg[186]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(186),
      Q => app_wdf_data_r1(186),
      R => '0'
    );
\app_wdf_data_r1_reg[187]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(187),
      Q => app_wdf_data_r1(187),
      R => '0'
    );
\app_wdf_data_r1_reg[188]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(188),
      Q => app_wdf_data_r1(188),
      R => '0'
    );
\app_wdf_data_r1_reg[189]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(189),
      Q => app_wdf_data_r1(189),
      R => '0'
    );
\app_wdf_data_r1_reg[18]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(18),
      Q => app_wdf_data_r1(18),
      R => '0'
    );
\app_wdf_data_r1_reg[190]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(190),
      Q => app_wdf_data_r1(190),
      R => '0'
    );
\app_wdf_data_r1_reg[191]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(191),
      Q => app_wdf_data_r1(191),
      R => '0'
    );
\app_wdf_data_r1_reg[192]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(192),
      Q => app_wdf_data_r1(192),
      R => '0'
    );
\app_wdf_data_r1_reg[193]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(193),
      Q => app_wdf_data_r1(193),
      R => '0'
    );
\app_wdf_data_r1_reg[194]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(194),
      Q => app_wdf_data_r1(194),
      R => '0'
    );
\app_wdf_data_r1_reg[195]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(195),
      Q => app_wdf_data_r1(195),
      R => '0'
    );
\app_wdf_data_r1_reg[196]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(196),
      Q => app_wdf_data_r1(196),
      R => '0'
    );
\app_wdf_data_r1_reg[197]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(197),
      Q => app_wdf_data_r1(197),
      R => '0'
    );
\app_wdf_data_r1_reg[198]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(198),
      Q => app_wdf_data_r1(198),
      R => '0'
    );
\app_wdf_data_r1_reg[199]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(199),
      Q => app_wdf_data_r1(199),
      R => '0'
    );
\app_wdf_data_r1_reg[19]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(19),
      Q => app_wdf_data_r1(19),
      R => '0'
    );
\app_wdf_data_r1_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(1),
      Q => app_wdf_data_r1(1),
      R => '0'
    );
\app_wdf_data_r1_reg[200]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(200),
      Q => app_wdf_data_r1(200),
      R => '0'
    );
\app_wdf_data_r1_reg[201]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(201),
      Q => app_wdf_data_r1(201),
      R => '0'
    );
\app_wdf_data_r1_reg[202]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(202),
      Q => app_wdf_data_r1(202),
      R => '0'
    );
\app_wdf_data_r1_reg[203]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(203),
      Q => app_wdf_data_r1(203),
      R => '0'
    );
\app_wdf_data_r1_reg[204]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(204),
      Q => app_wdf_data_r1(204),
      R => '0'
    );
\app_wdf_data_r1_reg[205]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(205),
      Q => app_wdf_data_r1(205),
      R => '0'
    );
\app_wdf_data_r1_reg[206]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(206),
      Q => app_wdf_data_r1(206),
      R => '0'
    );
\app_wdf_data_r1_reg[207]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(207),
      Q => app_wdf_data_r1(207),
      R => '0'
    );
\app_wdf_data_r1_reg[208]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(208),
      Q => app_wdf_data_r1(208),
      R => '0'
    );
\app_wdf_data_r1_reg[209]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(209),
      Q => app_wdf_data_r1(209),
      R => '0'
    );
\app_wdf_data_r1_reg[20]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(20),
      Q => app_wdf_data_r1(20),
      R => '0'
    );
\app_wdf_data_r1_reg[210]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(210),
      Q => app_wdf_data_r1(210),
      R => '0'
    );
\app_wdf_data_r1_reg[211]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(211),
      Q => app_wdf_data_r1(211),
      R => '0'
    );
\app_wdf_data_r1_reg[212]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(212),
      Q => app_wdf_data_r1(212),
      R => '0'
    );
\app_wdf_data_r1_reg[213]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(213),
      Q => app_wdf_data_r1(213),
      R => '0'
    );
\app_wdf_data_r1_reg[214]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(214),
      Q => app_wdf_data_r1(214),
      R => '0'
    );
\app_wdf_data_r1_reg[215]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(215),
      Q => app_wdf_data_r1(215),
      R => '0'
    );
\app_wdf_data_r1_reg[216]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(216),
      Q => app_wdf_data_r1(216),
      R => '0'
    );
\app_wdf_data_r1_reg[217]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(217),
      Q => app_wdf_data_r1(217),
      R => '0'
    );
\app_wdf_data_r1_reg[218]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(218),
      Q => app_wdf_data_r1(218),
      R => '0'
    );
\app_wdf_data_r1_reg[219]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(219),
      Q => app_wdf_data_r1(219),
      R => '0'
    );
\app_wdf_data_r1_reg[21]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(21),
      Q => app_wdf_data_r1(21),
      R => '0'
    );
\app_wdf_data_r1_reg[220]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(220),
      Q => app_wdf_data_r1(220),
      R => '0'
    );
\app_wdf_data_r1_reg[221]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(221),
      Q => app_wdf_data_r1(221),
      R => '0'
    );
\app_wdf_data_r1_reg[222]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(222),
      Q => app_wdf_data_r1(222),
      R => '0'
    );
\app_wdf_data_r1_reg[223]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(223),
      Q => app_wdf_data_r1(223),
      R => '0'
    );
\app_wdf_data_r1_reg[224]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(224),
      Q => app_wdf_data_r1(224),
      R => '0'
    );
\app_wdf_data_r1_reg[225]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(225),
      Q => app_wdf_data_r1(225),
      R => '0'
    );
\app_wdf_data_r1_reg[226]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(226),
      Q => app_wdf_data_r1(226),
      R => '0'
    );
\app_wdf_data_r1_reg[227]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(227),
      Q => app_wdf_data_r1(227),
      R => '0'
    );
\app_wdf_data_r1_reg[228]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(228),
      Q => app_wdf_data_r1(228),
      R => '0'
    );
\app_wdf_data_r1_reg[229]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(229),
      Q => app_wdf_data_r1(229),
      R => '0'
    );
\app_wdf_data_r1_reg[22]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(22),
      Q => app_wdf_data_r1(22),
      R => '0'
    );
\app_wdf_data_r1_reg[230]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(230),
      Q => app_wdf_data_r1(230),
      R => '0'
    );
\app_wdf_data_r1_reg[231]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(231),
      Q => app_wdf_data_r1(231),
      R => '0'
    );
\app_wdf_data_r1_reg[232]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(232),
      Q => app_wdf_data_r1(232),
      R => '0'
    );
\app_wdf_data_r1_reg[233]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(233),
      Q => app_wdf_data_r1(233),
      R => '0'
    );
\app_wdf_data_r1_reg[234]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(234),
      Q => app_wdf_data_r1(234),
      R => '0'
    );
\app_wdf_data_r1_reg[235]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(235),
      Q => app_wdf_data_r1(235),
      R => '0'
    );
\app_wdf_data_r1_reg[236]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(236),
      Q => app_wdf_data_r1(236),
      R => '0'
    );
\app_wdf_data_r1_reg[237]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(237),
      Q => app_wdf_data_r1(237),
      R => '0'
    );
\app_wdf_data_r1_reg[238]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(238),
      Q => app_wdf_data_r1(238),
      R => '0'
    );
\app_wdf_data_r1_reg[239]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(239),
      Q => app_wdf_data_r1(239),
      R => '0'
    );
\app_wdf_data_r1_reg[23]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(23),
      Q => app_wdf_data_r1(23),
      R => '0'
    );
\app_wdf_data_r1_reg[240]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(240),
      Q => app_wdf_data_r1(240),
      R => '0'
    );
\app_wdf_data_r1_reg[241]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(241),
      Q => app_wdf_data_r1(241),
      R => '0'
    );
\app_wdf_data_r1_reg[242]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(242),
      Q => app_wdf_data_r1(242),
      R => '0'
    );
\app_wdf_data_r1_reg[243]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(243),
      Q => app_wdf_data_r1(243),
      R => '0'
    );
\app_wdf_data_r1_reg[244]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(244),
      Q => app_wdf_data_r1(244),
      R => '0'
    );
\app_wdf_data_r1_reg[245]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(245),
      Q => app_wdf_data_r1(245),
      R => '0'
    );
\app_wdf_data_r1_reg[246]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(246),
      Q => app_wdf_data_r1(246),
      R => '0'
    );
\app_wdf_data_r1_reg[247]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(247),
      Q => app_wdf_data_r1(247),
      R => '0'
    );
\app_wdf_data_r1_reg[248]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(248),
      Q => app_wdf_data_r1(248),
      R => '0'
    );
\app_wdf_data_r1_reg[249]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(249),
      Q => app_wdf_data_r1(249),
      R => '0'
    );
\app_wdf_data_r1_reg[24]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(24),
      Q => app_wdf_data_r1(24),
      R => '0'
    );
\app_wdf_data_r1_reg[250]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(250),
      Q => app_wdf_data_r1(250),
      R => '0'
    );
\app_wdf_data_r1_reg[251]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(251),
      Q => app_wdf_data_r1(251),
      R => '0'
    );
\app_wdf_data_r1_reg[252]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(252),
      Q => app_wdf_data_r1(252),
      R => '0'
    );
\app_wdf_data_r1_reg[253]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(253),
      Q => app_wdf_data_r1(253),
      R => '0'
    );
\app_wdf_data_r1_reg[254]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(254),
      Q => app_wdf_data_r1(254),
      R => '0'
    );
\app_wdf_data_r1_reg[255]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(255),
      Q => app_wdf_data_r1(255),
      R => '0'
    );
\app_wdf_data_r1_reg[256]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(256),
      Q => app_wdf_data_r1(256),
      R => '0'
    );
\app_wdf_data_r1_reg[257]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(257),
      Q => app_wdf_data_r1(257),
      R => '0'
    );
\app_wdf_data_r1_reg[258]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(258),
      Q => app_wdf_data_r1(258),
      R => '0'
    );
\app_wdf_data_r1_reg[259]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(259),
      Q => app_wdf_data_r1(259),
      R => '0'
    );
\app_wdf_data_r1_reg[25]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(25),
      Q => app_wdf_data_r1(25),
      R => '0'
    );
\app_wdf_data_r1_reg[260]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(260),
      Q => app_wdf_data_r1(260),
      R => '0'
    );
\app_wdf_data_r1_reg[261]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(261),
      Q => app_wdf_data_r1(261),
      R => '0'
    );
\app_wdf_data_r1_reg[262]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(262),
      Q => app_wdf_data_r1(262),
      R => '0'
    );
\app_wdf_data_r1_reg[263]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(263),
      Q => app_wdf_data_r1(263),
      R => '0'
    );
\app_wdf_data_r1_reg[264]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(264),
      Q => app_wdf_data_r1(264),
      R => '0'
    );
\app_wdf_data_r1_reg[265]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(265),
      Q => app_wdf_data_r1(265),
      R => '0'
    );
\app_wdf_data_r1_reg[266]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(266),
      Q => app_wdf_data_r1(266),
      R => '0'
    );
\app_wdf_data_r1_reg[267]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(267),
      Q => app_wdf_data_r1(267),
      R => '0'
    );
\app_wdf_data_r1_reg[268]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(268),
      Q => app_wdf_data_r1(268),
      R => '0'
    );
\app_wdf_data_r1_reg[269]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(269),
      Q => app_wdf_data_r1(269),
      R => '0'
    );
\app_wdf_data_r1_reg[26]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(26),
      Q => app_wdf_data_r1(26),
      R => '0'
    );
\app_wdf_data_r1_reg[270]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(270),
      Q => app_wdf_data_r1(270),
      R => '0'
    );
\app_wdf_data_r1_reg[271]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(271),
      Q => app_wdf_data_r1(271),
      R => '0'
    );
\app_wdf_data_r1_reg[272]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(272),
      Q => app_wdf_data_r1(272),
      R => '0'
    );
\app_wdf_data_r1_reg[273]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(273),
      Q => app_wdf_data_r1(273),
      R => '0'
    );
\app_wdf_data_r1_reg[274]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(274),
      Q => app_wdf_data_r1(274),
      R => '0'
    );
\app_wdf_data_r1_reg[275]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(275),
      Q => app_wdf_data_r1(275),
      R => '0'
    );
\app_wdf_data_r1_reg[276]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(276),
      Q => app_wdf_data_r1(276),
      R => '0'
    );
\app_wdf_data_r1_reg[277]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(277),
      Q => app_wdf_data_r1(277),
      R => '0'
    );
\app_wdf_data_r1_reg[278]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(278),
      Q => app_wdf_data_r1(278),
      R => '0'
    );
\app_wdf_data_r1_reg[279]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(279),
      Q => app_wdf_data_r1(279),
      R => '0'
    );
\app_wdf_data_r1_reg[27]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(27),
      Q => app_wdf_data_r1(27),
      R => '0'
    );
\app_wdf_data_r1_reg[280]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(280),
      Q => app_wdf_data_r1(280),
      R => '0'
    );
\app_wdf_data_r1_reg[281]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(281),
      Q => app_wdf_data_r1(281),
      R => '0'
    );
\app_wdf_data_r1_reg[282]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(282),
      Q => app_wdf_data_r1(282),
      R => '0'
    );
\app_wdf_data_r1_reg[283]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(283),
      Q => app_wdf_data_r1(283),
      R => '0'
    );
\app_wdf_data_r1_reg[284]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(284),
      Q => app_wdf_data_r1(284),
      R => '0'
    );
\app_wdf_data_r1_reg[285]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(285),
      Q => app_wdf_data_r1(285),
      R => '0'
    );
\app_wdf_data_r1_reg[286]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(286),
      Q => app_wdf_data_r1(286),
      R => '0'
    );
\app_wdf_data_r1_reg[287]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(287),
      Q => app_wdf_data_r1(287),
      R => '0'
    );
\app_wdf_data_r1_reg[288]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(288),
      Q => app_wdf_data_r1(288),
      R => '0'
    );
\app_wdf_data_r1_reg[289]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(289),
      Q => app_wdf_data_r1(289),
      R => '0'
    );
\app_wdf_data_r1_reg[28]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(28),
      Q => app_wdf_data_r1(28),
      R => '0'
    );
\app_wdf_data_r1_reg[290]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(290),
      Q => app_wdf_data_r1(290),
      R => '0'
    );
\app_wdf_data_r1_reg[291]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(291),
      Q => app_wdf_data_r1(291),
      R => '0'
    );
\app_wdf_data_r1_reg[292]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(292),
      Q => app_wdf_data_r1(292),
      R => '0'
    );
\app_wdf_data_r1_reg[293]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(293),
      Q => app_wdf_data_r1(293),
      R => '0'
    );
\app_wdf_data_r1_reg[294]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(294),
      Q => app_wdf_data_r1(294),
      R => '0'
    );
\app_wdf_data_r1_reg[295]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(295),
      Q => app_wdf_data_r1(295),
      R => '0'
    );
\app_wdf_data_r1_reg[296]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(296),
      Q => app_wdf_data_r1(296),
      R => '0'
    );
\app_wdf_data_r1_reg[297]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(297),
      Q => app_wdf_data_r1(297),
      R => '0'
    );
\app_wdf_data_r1_reg[298]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(298),
      Q => app_wdf_data_r1(298),
      R => '0'
    );
\app_wdf_data_r1_reg[299]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(299),
      Q => app_wdf_data_r1(299),
      R => '0'
    );
\app_wdf_data_r1_reg[29]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(29),
      Q => app_wdf_data_r1(29),
      R => '0'
    );
\app_wdf_data_r1_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(2),
      Q => app_wdf_data_r1(2),
      R => '0'
    );
\app_wdf_data_r1_reg[300]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(300),
      Q => app_wdf_data_r1(300),
      R => '0'
    );
\app_wdf_data_r1_reg[301]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(301),
      Q => app_wdf_data_r1(301),
      R => '0'
    );
\app_wdf_data_r1_reg[302]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(302),
      Q => app_wdf_data_r1(302),
      R => '0'
    );
\app_wdf_data_r1_reg[303]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(303),
      Q => app_wdf_data_r1(303),
      R => '0'
    );
\app_wdf_data_r1_reg[304]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(304),
      Q => app_wdf_data_r1(304),
      R => '0'
    );
\app_wdf_data_r1_reg[305]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(305),
      Q => app_wdf_data_r1(305),
      R => '0'
    );
\app_wdf_data_r1_reg[306]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(306),
      Q => app_wdf_data_r1(306),
      R => '0'
    );
\app_wdf_data_r1_reg[307]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(307),
      Q => app_wdf_data_r1(307),
      R => '0'
    );
\app_wdf_data_r1_reg[308]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(308),
      Q => app_wdf_data_r1(308),
      R => '0'
    );
\app_wdf_data_r1_reg[309]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(309),
      Q => app_wdf_data_r1(309),
      R => '0'
    );
\app_wdf_data_r1_reg[30]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(30),
      Q => app_wdf_data_r1(30),
      R => '0'
    );
\app_wdf_data_r1_reg[310]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(310),
      Q => app_wdf_data_r1(310),
      R => '0'
    );
\app_wdf_data_r1_reg[311]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(311),
      Q => app_wdf_data_r1(311),
      R => '0'
    );
\app_wdf_data_r1_reg[312]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(312),
      Q => app_wdf_data_r1(312),
      R => '0'
    );
\app_wdf_data_r1_reg[313]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(313),
      Q => app_wdf_data_r1(313),
      R => '0'
    );
\app_wdf_data_r1_reg[314]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(314),
      Q => app_wdf_data_r1(314),
      R => '0'
    );
\app_wdf_data_r1_reg[315]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(315),
      Q => app_wdf_data_r1(315),
      R => '0'
    );
\app_wdf_data_r1_reg[316]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(316),
      Q => app_wdf_data_r1(316),
      R => '0'
    );
\app_wdf_data_r1_reg[317]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(317),
      Q => app_wdf_data_r1(317),
      R => '0'
    );
\app_wdf_data_r1_reg[318]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(318),
      Q => app_wdf_data_r1(318),
      R => '0'
    );
\app_wdf_data_r1_reg[319]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(319),
      Q => app_wdf_data_r1(319),
      R => '0'
    );
\app_wdf_data_r1_reg[31]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(31),
      Q => app_wdf_data_r1(31),
      R => '0'
    );
\app_wdf_data_r1_reg[320]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(320),
      Q => app_wdf_data_r1(320),
      R => '0'
    );
\app_wdf_data_r1_reg[321]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(321),
      Q => app_wdf_data_r1(321),
      R => '0'
    );
\app_wdf_data_r1_reg[322]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(322),
      Q => app_wdf_data_r1(322),
      R => '0'
    );
\app_wdf_data_r1_reg[323]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(323),
      Q => app_wdf_data_r1(323),
      R => '0'
    );
\app_wdf_data_r1_reg[324]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(324),
      Q => app_wdf_data_r1(324),
      R => '0'
    );
\app_wdf_data_r1_reg[325]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(325),
      Q => app_wdf_data_r1(325),
      R => '0'
    );
\app_wdf_data_r1_reg[326]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(326),
      Q => app_wdf_data_r1(326),
      R => '0'
    );
\app_wdf_data_r1_reg[327]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(327),
      Q => app_wdf_data_r1(327),
      R => '0'
    );
\app_wdf_data_r1_reg[328]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(328),
      Q => app_wdf_data_r1(328),
      R => '0'
    );
\app_wdf_data_r1_reg[329]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(329),
      Q => app_wdf_data_r1(329),
      R => '0'
    );
\app_wdf_data_r1_reg[32]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(32),
      Q => app_wdf_data_r1(32),
      R => '0'
    );
\app_wdf_data_r1_reg[330]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(330),
      Q => app_wdf_data_r1(330),
      R => '0'
    );
\app_wdf_data_r1_reg[331]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(331),
      Q => app_wdf_data_r1(331),
      R => '0'
    );
\app_wdf_data_r1_reg[332]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(332),
      Q => app_wdf_data_r1(332),
      R => '0'
    );
\app_wdf_data_r1_reg[333]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(333),
      Q => app_wdf_data_r1(333),
      R => '0'
    );
\app_wdf_data_r1_reg[334]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(334),
      Q => app_wdf_data_r1(334),
      R => '0'
    );
\app_wdf_data_r1_reg[335]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(335),
      Q => app_wdf_data_r1(335),
      R => '0'
    );
\app_wdf_data_r1_reg[336]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(336),
      Q => app_wdf_data_r1(336),
      R => '0'
    );
\app_wdf_data_r1_reg[337]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(337),
      Q => app_wdf_data_r1(337),
      R => '0'
    );
\app_wdf_data_r1_reg[338]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(338),
      Q => app_wdf_data_r1(338),
      R => '0'
    );
\app_wdf_data_r1_reg[339]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(339),
      Q => app_wdf_data_r1(339),
      R => '0'
    );
\app_wdf_data_r1_reg[33]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(33),
      Q => app_wdf_data_r1(33),
      R => '0'
    );
\app_wdf_data_r1_reg[340]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(340),
      Q => app_wdf_data_r1(340),
      R => '0'
    );
\app_wdf_data_r1_reg[341]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(341),
      Q => app_wdf_data_r1(341),
      R => '0'
    );
\app_wdf_data_r1_reg[342]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(342),
      Q => app_wdf_data_r1(342),
      R => '0'
    );
\app_wdf_data_r1_reg[343]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(343),
      Q => app_wdf_data_r1(343),
      R => '0'
    );
\app_wdf_data_r1_reg[344]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(344),
      Q => app_wdf_data_r1(344),
      R => '0'
    );
\app_wdf_data_r1_reg[345]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(345),
      Q => app_wdf_data_r1(345),
      R => '0'
    );
\app_wdf_data_r1_reg[346]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(346),
      Q => app_wdf_data_r1(346),
      R => '0'
    );
\app_wdf_data_r1_reg[347]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(347),
      Q => app_wdf_data_r1(347),
      R => '0'
    );
\app_wdf_data_r1_reg[348]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(348),
      Q => app_wdf_data_r1(348),
      R => '0'
    );
\app_wdf_data_r1_reg[349]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(349),
      Q => app_wdf_data_r1(349),
      R => '0'
    );
\app_wdf_data_r1_reg[34]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(34),
      Q => app_wdf_data_r1(34),
      R => '0'
    );
\app_wdf_data_r1_reg[350]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(350),
      Q => app_wdf_data_r1(350),
      R => '0'
    );
\app_wdf_data_r1_reg[351]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(351),
      Q => app_wdf_data_r1(351),
      R => '0'
    );
\app_wdf_data_r1_reg[352]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(352),
      Q => app_wdf_data_r1(352),
      R => '0'
    );
\app_wdf_data_r1_reg[353]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(353),
      Q => app_wdf_data_r1(353),
      R => '0'
    );
\app_wdf_data_r1_reg[354]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(354),
      Q => app_wdf_data_r1(354),
      R => '0'
    );
\app_wdf_data_r1_reg[355]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(355),
      Q => app_wdf_data_r1(355),
      R => '0'
    );
\app_wdf_data_r1_reg[356]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(356),
      Q => app_wdf_data_r1(356),
      R => '0'
    );
\app_wdf_data_r1_reg[357]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(357),
      Q => app_wdf_data_r1(357),
      R => '0'
    );
\app_wdf_data_r1_reg[358]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(358),
      Q => app_wdf_data_r1(358),
      R => '0'
    );
\app_wdf_data_r1_reg[359]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(359),
      Q => app_wdf_data_r1(359),
      R => '0'
    );
\app_wdf_data_r1_reg[35]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(35),
      Q => app_wdf_data_r1(35),
      R => '0'
    );
\app_wdf_data_r1_reg[360]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(360),
      Q => app_wdf_data_r1(360),
      R => '0'
    );
\app_wdf_data_r1_reg[361]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(361),
      Q => app_wdf_data_r1(361),
      R => '0'
    );
\app_wdf_data_r1_reg[362]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(362),
      Q => app_wdf_data_r1(362),
      R => '0'
    );
\app_wdf_data_r1_reg[363]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(363),
      Q => app_wdf_data_r1(363),
      R => '0'
    );
\app_wdf_data_r1_reg[364]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(364),
      Q => app_wdf_data_r1(364),
      R => '0'
    );
\app_wdf_data_r1_reg[365]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(365),
      Q => app_wdf_data_r1(365),
      R => '0'
    );
\app_wdf_data_r1_reg[366]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(366),
      Q => app_wdf_data_r1(366),
      R => '0'
    );
\app_wdf_data_r1_reg[367]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(367),
      Q => app_wdf_data_r1(367),
      R => '0'
    );
\app_wdf_data_r1_reg[368]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(368),
      Q => app_wdf_data_r1(368),
      R => '0'
    );
\app_wdf_data_r1_reg[369]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(369),
      Q => app_wdf_data_r1(369),
      R => '0'
    );
\app_wdf_data_r1_reg[36]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(36),
      Q => app_wdf_data_r1(36),
      R => '0'
    );
\app_wdf_data_r1_reg[370]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(370),
      Q => app_wdf_data_r1(370),
      R => '0'
    );
\app_wdf_data_r1_reg[371]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(371),
      Q => app_wdf_data_r1(371),
      R => '0'
    );
\app_wdf_data_r1_reg[372]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(372),
      Q => app_wdf_data_r1(372),
      R => '0'
    );
\app_wdf_data_r1_reg[373]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(373),
      Q => app_wdf_data_r1(373),
      R => '0'
    );
\app_wdf_data_r1_reg[374]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(374),
      Q => app_wdf_data_r1(374),
      R => '0'
    );
\app_wdf_data_r1_reg[375]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(375),
      Q => app_wdf_data_r1(375),
      R => '0'
    );
\app_wdf_data_r1_reg[376]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(376),
      Q => app_wdf_data_r1(376),
      R => '0'
    );
\app_wdf_data_r1_reg[377]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(377),
      Q => app_wdf_data_r1(377),
      R => '0'
    );
\app_wdf_data_r1_reg[378]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(378),
      Q => app_wdf_data_r1(378),
      R => '0'
    );
\app_wdf_data_r1_reg[379]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(379),
      Q => app_wdf_data_r1(379),
      R => '0'
    );
\app_wdf_data_r1_reg[37]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(37),
      Q => app_wdf_data_r1(37),
      R => '0'
    );
\app_wdf_data_r1_reg[380]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(380),
      Q => app_wdf_data_r1(380),
      R => '0'
    );
\app_wdf_data_r1_reg[381]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(381),
      Q => app_wdf_data_r1(381),
      R => '0'
    );
\app_wdf_data_r1_reg[382]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(382),
      Q => app_wdf_data_r1(382),
      R => '0'
    );
\app_wdf_data_r1_reg[383]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(383),
      Q => app_wdf_data_r1(383),
      R => '0'
    );
\app_wdf_data_r1_reg[384]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(384),
      Q => app_wdf_data_r1(384),
      R => '0'
    );
\app_wdf_data_r1_reg[385]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(385),
      Q => app_wdf_data_r1(385),
      R => '0'
    );
\app_wdf_data_r1_reg[386]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(386),
      Q => app_wdf_data_r1(386),
      R => '0'
    );
\app_wdf_data_r1_reg[387]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(387),
      Q => app_wdf_data_r1(387),
      R => '0'
    );
\app_wdf_data_r1_reg[388]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(388),
      Q => app_wdf_data_r1(388),
      R => '0'
    );
\app_wdf_data_r1_reg[389]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(389),
      Q => app_wdf_data_r1(389),
      R => '0'
    );
\app_wdf_data_r1_reg[38]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(38),
      Q => app_wdf_data_r1(38),
      R => '0'
    );
\app_wdf_data_r1_reg[390]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(390),
      Q => app_wdf_data_r1(390),
      R => '0'
    );
\app_wdf_data_r1_reg[391]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(391),
      Q => app_wdf_data_r1(391),
      R => '0'
    );
\app_wdf_data_r1_reg[392]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(392),
      Q => app_wdf_data_r1(392),
      R => '0'
    );
\app_wdf_data_r1_reg[393]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(393),
      Q => app_wdf_data_r1(393),
      R => '0'
    );
\app_wdf_data_r1_reg[394]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(394),
      Q => app_wdf_data_r1(394),
      R => '0'
    );
\app_wdf_data_r1_reg[395]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(395),
      Q => app_wdf_data_r1(395),
      R => '0'
    );
\app_wdf_data_r1_reg[396]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(396),
      Q => app_wdf_data_r1(396),
      R => '0'
    );
\app_wdf_data_r1_reg[397]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(397),
      Q => app_wdf_data_r1(397),
      R => '0'
    );
\app_wdf_data_r1_reg[398]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(398),
      Q => app_wdf_data_r1(398),
      R => '0'
    );
\app_wdf_data_r1_reg[399]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(399),
      Q => app_wdf_data_r1(399),
      R => '0'
    );
\app_wdf_data_r1_reg[39]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(39),
      Q => app_wdf_data_r1(39),
      R => '0'
    );
\app_wdf_data_r1_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(3),
      Q => app_wdf_data_r1(3),
      R => '0'
    );
\app_wdf_data_r1_reg[400]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(400),
      Q => app_wdf_data_r1(400),
      R => '0'
    );
\app_wdf_data_r1_reg[401]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(401),
      Q => app_wdf_data_r1(401),
      R => '0'
    );
\app_wdf_data_r1_reg[402]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(402),
      Q => app_wdf_data_r1(402),
      R => '0'
    );
\app_wdf_data_r1_reg[403]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(403),
      Q => app_wdf_data_r1(403),
      R => '0'
    );
\app_wdf_data_r1_reg[404]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(404),
      Q => app_wdf_data_r1(404),
      R => '0'
    );
\app_wdf_data_r1_reg[405]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(405),
      Q => app_wdf_data_r1(405),
      R => '0'
    );
\app_wdf_data_r1_reg[406]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(406),
      Q => app_wdf_data_r1(406),
      R => '0'
    );
\app_wdf_data_r1_reg[407]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(407),
      Q => app_wdf_data_r1(407),
      R => '0'
    );
\app_wdf_data_r1_reg[408]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(408),
      Q => app_wdf_data_r1(408),
      R => '0'
    );
\app_wdf_data_r1_reg[409]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(409),
      Q => app_wdf_data_r1(409),
      R => '0'
    );
\app_wdf_data_r1_reg[40]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(40),
      Q => app_wdf_data_r1(40),
      R => '0'
    );
\app_wdf_data_r1_reg[410]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(410),
      Q => app_wdf_data_r1(410),
      R => '0'
    );
\app_wdf_data_r1_reg[411]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(411),
      Q => app_wdf_data_r1(411),
      R => '0'
    );
\app_wdf_data_r1_reg[412]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(412),
      Q => app_wdf_data_r1(412),
      R => '0'
    );
\app_wdf_data_r1_reg[413]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(413),
      Q => app_wdf_data_r1(413),
      R => '0'
    );
\app_wdf_data_r1_reg[414]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(414),
      Q => app_wdf_data_r1(414),
      R => '0'
    );
\app_wdf_data_r1_reg[415]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(415),
      Q => app_wdf_data_r1(415),
      R => '0'
    );
\app_wdf_data_r1_reg[416]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(416),
      Q => app_wdf_data_r1(416),
      R => '0'
    );
\app_wdf_data_r1_reg[417]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(417),
      Q => app_wdf_data_r1(417),
      R => '0'
    );
\app_wdf_data_r1_reg[418]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(418),
      Q => app_wdf_data_r1(418),
      R => '0'
    );
\app_wdf_data_r1_reg[419]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(419),
      Q => app_wdf_data_r1(419),
      R => '0'
    );
\app_wdf_data_r1_reg[41]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(41),
      Q => app_wdf_data_r1(41),
      R => '0'
    );
\app_wdf_data_r1_reg[420]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(420),
      Q => app_wdf_data_r1(420),
      R => '0'
    );
\app_wdf_data_r1_reg[421]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(421),
      Q => app_wdf_data_r1(421),
      R => '0'
    );
\app_wdf_data_r1_reg[422]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(422),
      Q => app_wdf_data_r1(422),
      R => '0'
    );
\app_wdf_data_r1_reg[423]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(423),
      Q => app_wdf_data_r1(423),
      R => '0'
    );
\app_wdf_data_r1_reg[424]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(424),
      Q => app_wdf_data_r1(424),
      R => '0'
    );
\app_wdf_data_r1_reg[425]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(425),
      Q => app_wdf_data_r1(425),
      R => '0'
    );
\app_wdf_data_r1_reg[426]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(426),
      Q => app_wdf_data_r1(426),
      R => '0'
    );
\app_wdf_data_r1_reg[427]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(427),
      Q => app_wdf_data_r1(427),
      R => '0'
    );
\app_wdf_data_r1_reg[428]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(428),
      Q => app_wdf_data_r1(428),
      R => '0'
    );
\app_wdf_data_r1_reg[429]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(429),
      Q => app_wdf_data_r1(429),
      R => '0'
    );
\app_wdf_data_r1_reg[42]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(42),
      Q => app_wdf_data_r1(42),
      R => '0'
    );
\app_wdf_data_r1_reg[430]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(430),
      Q => app_wdf_data_r1(430),
      R => '0'
    );
\app_wdf_data_r1_reg[431]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(431),
      Q => app_wdf_data_r1(431),
      R => '0'
    );
\app_wdf_data_r1_reg[432]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(432),
      Q => app_wdf_data_r1(432),
      R => '0'
    );
\app_wdf_data_r1_reg[433]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(433),
      Q => app_wdf_data_r1(433),
      R => '0'
    );
\app_wdf_data_r1_reg[434]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(434),
      Q => app_wdf_data_r1(434),
      R => '0'
    );
\app_wdf_data_r1_reg[435]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(435),
      Q => app_wdf_data_r1(435),
      R => '0'
    );
\app_wdf_data_r1_reg[436]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(436),
      Q => app_wdf_data_r1(436),
      R => '0'
    );
\app_wdf_data_r1_reg[437]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(437),
      Q => app_wdf_data_r1(437),
      R => '0'
    );
\app_wdf_data_r1_reg[438]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(438),
      Q => app_wdf_data_r1(438),
      R => '0'
    );
\app_wdf_data_r1_reg[439]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(439),
      Q => app_wdf_data_r1(439),
      R => '0'
    );
\app_wdf_data_r1_reg[43]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(43),
      Q => app_wdf_data_r1(43),
      R => '0'
    );
\app_wdf_data_r1_reg[440]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(440),
      Q => app_wdf_data_r1(440),
      R => '0'
    );
\app_wdf_data_r1_reg[441]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(441),
      Q => app_wdf_data_r1(441),
      R => '0'
    );
\app_wdf_data_r1_reg[442]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(442),
      Q => app_wdf_data_r1(442),
      R => '0'
    );
\app_wdf_data_r1_reg[443]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(443),
      Q => app_wdf_data_r1(443),
      R => '0'
    );
\app_wdf_data_r1_reg[444]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(444),
      Q => app_wdf_data_r1(444),
      R => '0'
    );
\app_wdf_data_r1_reg[445]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(445),
      Q => app_wdf_data_r1(445),
      R => '0'
    );
\app_wdf_data_r1_reg[446]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(446),
      Q => app_wdf_data_r1(446),
      R => '0'
    );
\app_wdf_data_r1_reg[447]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(447),
      Q => app_wdf_data_r1(447),
      R => '0'
    );
\app_wdf_data_r1_reg[448]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(448),
      Q => app_wdf_data_r1(448),
      R => '0'
    );
\app_wdf_data_r1_reg[449]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(449),
      Q => app_wdf_data_r1(449),
      R => '0'
    );
\app_wdf_data_r1_reg[44]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(44),
      Q => app_wdf_data_r1(44),
      R => '0'
    );
\app_wdf_data_r1_reg[450]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(450),
      Q => app_wdf_data_r1(450),
      R => '0'
    );
\app_wdf_data_r1_reg[451]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(451),
      Q => app_wdf_data_r1(451),
      R => '0'
    );
\app_wdf_data_r1_reg[452]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(452),
      Q => app_wdf_data_r1(452),
      R => '0'
    );
\app_wdf_data_r1_reg[453]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(453),
      Q => app_wdf_data_r1(453),
      R => '0'
    );
\app_wdf_data_r1_reg[454]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(454),
      Q => app_wdf_data_r1(454),
      R => '0'
    );
\app_wdf_data_r1_reg[455]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(455),
      Q => app_wdf_data_r1(455),
      R => '0'
    );
\app_wdf_data_r1_reg[456]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(456),
      Q => app_wdf_data_r1(456),
      R => '0'
    );
\app_wdf_data_r1_reg[457]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(457),
      Q => app_wdf_data_r1(457),
      R => '0'
    );
\app_wdf_data_r1_reg[458]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(458),
      Q => app_wdf_data_r1(458),
      R => '0'
    );
\app_wdf_data_r1_reg[459]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(459),
      Q => app_wdf_data_r1(459),
      R => '0'
    );
\app_wdf_data_r1_reg[45]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(45),
      Q => app_wdf_data_r1(45),
      R => '0'
    );
\app_wdf_data_r1_reg[460]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(460),
      Q => app_wdf_data_r1(460),
      R => '0'
    );
\app_wdf_data_r1_reg[461]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(461),
      Q => app_wdf_data_r1(461),
      R => '0'
    );
\app_wdf_data_r1_reg[462]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(462),
      Q => app_wdf_data_r1(462),
      R => '0'
    );
\app_wdf_data_r1_reg[463]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(463),
      Q => app_wdf_data_r1(463),
      R => '0'
    );
\app_wdf_data_r1_reg[464]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(464),
      Q => app_wdf_data_r1(464),
      R => '0'
    );
\app_wdf_data_r1_reg[465]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(465),
      Q => app_wdf_data_r1(465),
      R => '0'
    );
\app_wdf_data_r1_reg[466]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(466),
      Q => app_wdf_data_r1(466),
      R => '0'
    );
\app_wdf_data_r1_reg[467]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(467),
      Q => app_wdf_data_r1(467),
      R => '0'
    );
\app_wdf_data_r1_reg[468]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(468),
      Q => app_wdf_data_r1(468),
      R => '0'
    );
\app_wdf_data_r1_reg[469]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(469),
      Q => app_wdf_data_r1(469),
      R => '0'
    );
\app_wdf_data_r1_reg[46]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(46),
      Q => app_wdf_data_r1(46),
      R => '0'
    );
\app_wdf_data_r1_reg[470]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(470),
      Q => app_wdf_data_r1(470),
      R => '0'
    );
\app_wdf_data_r1_reg[471]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(471),
      Q => app_wdf_data_r1(471),
      R => '0'
    );
\app_wdf_data_r1_reg[472]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(472),
      Q => app_wdf_data_r1(472),
      R => '0'
    );
\app_wdf_data_r1_reg[473]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(473),
      Q => app_wdf_data_r1(473),
      R => '0'
    );
\app_wdf_data_r1_reg[474]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(474),
      Q => app_wdf_data_r1(474),
      R => '0'
    );
\app_wdf_data_r1_reg[475]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(475),
      Q => app_wdf_data_r1(475),
      R => '0'
    );
\app_wdf_data_r1_reg[476]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(476),
      Q => app_wdf_data_r1(476),
      R => '0'
    );
\app_wdf_data_r1_reg[477]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(477),
      Q => app_wdf_data_r1(477),
      R => '0'
    );
\app_wdf_data_r1_reg[478]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(478),
      Q => app_wdf_data_r1(478),
      R => '0'
    );
\app_wdf_data_r1_reg[479]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(479),
      Q => app_wdf_data_r1(479),
      R => '0'
    );
\app_wdf_data_r1_reg[47]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(47),
      Q => app_wdf_data_r1(47),
      R => '0'
    );
\app_wdf_data_r1_reg[480]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(480),
      Q => app_wdf_data_r1(480),
      R => '0'
    );
\app_wdf_data_r1_reg[481]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(481),
      Q => app_wdf_data_r1(481),
      R => '0'
    );
\app_wdf_data_r1_reg[482]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(482),
      Q => app_wdf_data_r1(482),
      R => '0'
    );
\app_wdf_data_r1_reg[483]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(483),
      Q => app_wdf_data_r1(483),
      R => '0'
    );
\app_wdf_data_r1_reg[484]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(484),
      Q => app_wdf_data_r1(484),
      R => '0'
    );
\app_wdf_data_r1_reg[485]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(485),
      Q => app_wdf_data_r1(485),
      R => '0'
    );
\app_wdf_data_r1_reg[486]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(486),
      Q => app_wdf_data_r1(486),
      R => '0'
    );
\app_wdf_data_r1_reg[487]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(487),
      Q => app_wdf_data_r1(487),
      R => '0'
    );
\app_wdf_data_r1_reg[488]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(488),
      Q => app_wdf_data_r1(488),
      R => '0'
    );
\app_wdf_data_r1_reg[489]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(489),
      Q => app_wdf_data_r1(489),
      R => '0'
    );
\app_wdf_data_r1_reg[48]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(48),
      Q => app_wdf_data_r1(48),
      R => '0'
    );
\app_wdf_data_r1_reg[490]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(490),
      Q => app_wdf_data_r1(490),
      R => '0'
    );
\app_wdf_data_r1_reg[491]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(491),
      Q => app_wdf_data_r1(491),
      R => '0'
    );
\app_wdf_data_r1_reg[492]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(492),
      Q => app_wdf_data_r1(492),
      R => '0'
    );
\app_wdf_data_r1_reg[493]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(493),
      Q => app_wdf_data_r1(493),
      R => '0'
    );
\app_wdf_data_r1_reg[494]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(494),
      Q => app_wdf_data_r1(494),
      R => '0'
    );
\app_wdf_data_r1_reg[495]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(495),
      Q => app_wdf_data_r1(495),
      R => '0'
    );
\app_wdf_data_r1_reg[496]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(496),
      Q => app_wdf_data_r1(496),
      R => '0'
    );
\app_wdf_data_r1_reg[497]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(497),
      Q => app_wdf_data_r1(497),
      R => '0'
    );
\app_wdf_data_r1_reg[498]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(498),
      Q => app_wdf_data_r1(498),
      R => '0'
    );
\app_wdf_data_r1_reg[499]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(499),
      Q => app_wdf_data_r1(499),
      R => '0'
    );
\app_wdf_data_r1_reg[49]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(49),
      Q => app_wdf_data_r1(49),
      R => '0'
    );
\app_wdf_data_r1_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(4),
      Q => app_wdf_data_r1(4),
      R => '0'
    );
\app_wdf_data_r1_reg[500]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(500),
      Q => app_wdf_data_r1(500),
      R => '0'
    );
\app_wdf_data_r1_reg[501]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(501),
      Q => app_wdf_data_r1(501),
      R => '0'
    );
\app_wdf_data_r1_reg[502]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(502),
      Q => app_wdf_data_r1(502),
      R => '0'
    );
\app_wdf_data_r1_reg[503]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(503),
      Q => app_wdf_data_r1(503),
      R => '0'
    );
\app_wdf_data_r1_reg[504]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(504),
      Q => app_wdf_data_r1(504),
      R => '0'
    );
\app_wdf_data_r1_reg[505]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(505),
      Q => app_wdf_data_r1(505),
      R => '0'
    );
\app_wdf_data_r1_reg[506]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(506),
      Q => app_wdf_data_r1(506),
      R => '0'
    );
\app_wdf_data_r1_reg[507]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(507),
      Q => app_wdf_data_r1(507),
      R => '0'
    );
\app_wdf_data_r1_reg[508]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(508),
      Q => app_wdf_data_r1(508),
      R => '0'
    );
\app_wdf_data_r1_reg[509]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(509),
      Q => app_wdf_data_r1(509),
      R => '0'
    );
\app_wdf_data_r1_reg[50]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(50),
      Q => app_wdf_data_r1(50),
      R => '0'
    );
\app_wdf_data_r1_reg[510]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(510),
      Q => app_wdf_data_r1(510),
      R => '0'
    );
\app_wdf_data_r1_reg[511]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(511),
      Q => app_wdf_data_r1(511),
      R => '0'
    );
\app_wdf_data_r1_reg[51]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(51),
      Q => app_wdf_data_r1(51),
      R => '0'
    );
\app_wdf_data_r1_reg[52]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(52),
      Q => app_wdf_data_r1(52),
      R => '0'
    );
\app_wdf_data_r1_reg[53]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(53),
      Q => app_wdf_data_r1(53),
      R => '0'
    );
\app_wdf_data_r1_reg[54]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(54),
      Q => app_wdf_data_r1(54),
      R => '0'
    );
\app_wdf_data_r1_reg[55]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(55),
      Q => app_wdf_data_r1(55),
      R => '0'
    );
\app_wdf_data_r1_reg[56]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(56),
      Q => app_wdf_data_r1(56),
      R => '0'
    );
\app_wdf_data_r1_reg[57]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(57),
      Q => app_wdf_data_r1(57),
      R => '0'
    );
\app_wdf_data_r1_reg[58]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(58),
      Q => app_wdf_data_r1(58),
      R => '0'
    );
\app_wdf_data_r1_reg[59]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(59),
      Q => app_wdf_data_r1(59),
      R => '0'
    );
\app_wdf_data_r1_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(5),
      Q => app_wdf_data_r1(5),
      R => '0'
    );
\app_wdf_data_r1_reg[60]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(60),
      Q => app_wdf_data_r1(60),
      R => '0'
    );
\app_wdf_data_r1_reg[61]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(61),
      Q => app_wdf_data_r1(61),
      R => '0'
    );
\app_wdf_data_r1_reg[62]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(62),
      Q => app_wdf_data_r1(62),
      R => '0'
    );
\app_wdf_data_r1_reg[63]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(63),
      Q => app_wdf_data_r1(63),
      R => '0'
    );
\app_wdf_data_r1_reg[64]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(64),
      Q => app_wdf_data_r1(64),
      R => '0'
    );
\app_wdf_data_r1_reg[65]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(65),
      Q => app_wdf_data_r1(65),
      R => '0'
    );
\app_wdf_data_r1_reg[66]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(66),
      Q => app_wdf_data_r1(66),
      R => '0'
    );
\app_wdf_data_r1_reg[67]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(67),
      Q => app_wdf_data_r1(67),
      R => '0'
    );
\app_wdf_data_r1_reg[68]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(68),
      Q => app_wdf_data_r1(68),
      R => '0'
    );
\app_wdf_data_r1_reg[69]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(69),
      Q => app_wdf_data_r1(69),
      R => '0'
    );
\app_wdf_data_r1_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(6),
      Q => app_wdf_data_r1(6),
      R => '0'
    );
\app_wdf_data_r1_reg[70]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(70),
      Q => app_wdf_data_r1(70),
      R => '0'
    );
\app_wdf_data_r1_reg[71]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(71),
      Q => app_wdf_data_r1(71),
      R => '0'
    );
\app_wdf_data_r1_reg[72]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(72),
      Q => app_wdf_data_r1(72),
      R => '0'
    );
\app_wdf_data_r1_reg[73]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(73),
      Q => app_wdf_data_r1(73),
      R => '0'
    );
\app_wdf_data_r1_reg[74]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(74),
      Q => app_wdf_data_r1(74),
      R => '0'
    );
\app_wdf_data_r1_reg[75]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(75),
      Q => app_wdf_data_r1(75),
      R => '0'
    );
\app_wdf_data_r1_reg[76]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(76),
      Q => app_wdf_data_r1(76),
      R => '0'
    );
\app_wdf_data_r1_reg[77]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(77),
      Q => app_wdf_data_r1(77),
      R => '0'
    );
\app_wdf_data_r1_reg[78]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(78),
      Q => app_wdf_data_r1(78),
      R => '0'
    );
\app_wdf_data_r1_reg[79]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(79),
      Q => app_wdf_data_r1(79),
      R => '0'
    );
\app_wdf_data_r1_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(7),
      Q => app_wdf_data_r1(7),
      R => '0'
    );
\app_wdf_data_r1_reg[80]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(80),
      Q => app_wdf_data_r1(80),
      R => '0'
    );
\app_wdf_data_r1_reg[81]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(81),
      Q => app_wdf_data_r1(81),
      R => '0'
    );
\app_wdf_data_r1_reg[82]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(82),
      Q => app_wdf_data_r1(82),
      R => '0'
    );
\app_wdf_data_r1_reg[83]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(83),
      Q => app_wdf_data_r1(83),
      R => '0'
    );
\app_wdf_data_r1_reg[84]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(84),
      Q => app_wdf_data_r1(84),
      R => '0'
    );
\app_wdf_data_r1_reg[85]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(85),
      Q => app_wdf_data_r1(85),
      R => '0'
    );
\app_wdf_data_r1_reg[86]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(86),
      Q => app_wdf_data_r1(86),
      R => '0'
    );
\app_wdf_data_r1_reg[87]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(87),
      Q => app_wdf_data_r1(87),
      R => '0'
    );
\app_wdf_data_r1_reg[88]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(88),
      Q => app_wdf_data_r1(88),
      R => '0'
    );
\app_wdf_data_r1_reg[89]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(89),
      Q => app_wdf_data_r1(89),
      R => '0'
    );
\app_wdf_data_r1_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(8),
      Q => app_wdf_data_r1(8),
      R => '0'
    );
\app_wdf_data_r1_reg[90]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(90),
      Q => app_wdf_data_r1(90),
      R => '0'
    );
\app_wdf_data_r1_reg[91]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(91),
      Q => app_wdf_data_r1(91),
      R => '0'
    );
\app_wdf_data_r1_reg[92]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(92),
      Q => app_wdf_data_r1(92),
      R => '0'
    );
\app_wdf_data_r1_reg[93]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(93),
      Q => app_wdf_data_r1(93),
      R => '0'
    );
\app_wdf_data_r1_reg[94]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(94),
      Q => app_wdf_data_r1(94),
      R => '0'
    );
\app_wdf_data_r1_reg[95]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(95),
      Q => app_wdf_data_r1(95),
      R => '0'
    );
\app_wdf_data_r1_reg[96]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(96),
      Q => app_wdf_data_r1(96),
      R => '0'
    );
\app_wdf_data_r1_reg[97]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(97),
      Q => app_wdf_data_r1(97),
      R => '0'
    );
\app_wdf_data_r1_reg[98]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(98),
      Q => app_wdf_data_r1(98),
      R => '0'
    );
\app_wdf_data_r1_reg[99]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(99),
      Q => app_wdf_data_r1(99),
      R => '0'
    );
\app_wdf_data_r1_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(9),
      Q => app_wdf_data_r1(9),
      R => '0'
    );
app_wdf_end_r1_i_1: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2230"
    )
        port map (
      I0 => app_wdf_end,
      I1 => \wr_req_counter.wr_req_cnt_r_reg[0]_1\,
      I2 => app_wdf_end_r1,
      I3 => app_wdf_rdy_r_copy2,
      O => app_wdf_end_ns1
    );
app_wdf_end_r1_reg: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => app_wdf_end_ns1,
      Q => app_wdf_end_r1,
      R => '0'
    );
\app_wdf_mask_r1_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_mask(0),
      Q => app_wdf_mask_r1(0),
      R => '0'
    );
\app_wdf_mask_r1_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_mask(10),
      Q => app_wdf_mask_r1(10),
      R => '0'
    );
\app_wdf_mask_r1_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_mask(11),
      Q => app_wdf_mask_r1(11),
      R => '0'
    );
\app_wdf_mask_r1_reg[12]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_mask(12),
      Q => app_wdf_mask_r1(12),
      R => '0'
    );
\app_wdf_mask_r1_reg[13]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_mask(13),
      Q => app_wdf_mask_r1(13),
      R => '0'
    );
\app_wdf_mask_r1_reg[14]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_mask(14),
      Q => app_wdf_mask_r1(14),
      R => '0'
    );
\app_wdf_mask_r1_reg[15]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_mask(15),
      Q => app_wdf_mask_r1(15),
      R => '0'
    );
\app_wdf_mask_r1_reg[16]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_mask(16),
      Q => app_wdf_mask_r1(16),
      R => '0'
    );
\app_wdf_mask_r1_reg[17]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_mask(17),
      Q => app_wdf_mask_r1(17),
      R => '0'
    );
\app_wdf_mask_r1_reg[18]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_mask(18),
      Q => app_wdf_mask_r1(18),
      R => '0'
    );
\app_wdf_mask_r1_reg[19]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_mask(19),
      Q => app_wdf_mask_r1(19),
      R => '0'
    );
\app_wdf_mask_r1_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_mask(1),
      Q => app_wdf_mask_r1(1),
      R => '0'
    );
\app_wdf_mask_r1_reg[20]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_mask(20),
      Q => app_wdf_mask_r1(20),
      R => '0'
    );
\app_wdf_mask_r1_reg[21]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_mask(21),
      Q => app_wdf_mask_r1(21),
      R => '0'
    );
\app_wdf_mask_r1_reg[22]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_mask(22),
      Q => app_wdf_mask_r1(22),
      R => '0'
    );
\app_wdf_mask_r1_reg[23]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_mask(23),
      Q => app_wdf_mask_r1(23),
      R => '0'
    );
\app_wdf_mask_r1_reg[24]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_mask(24),
      Q => app_wdf_mask_r1(24),
      R => '0'
    );
\app_wdf_mask_r1_reg[25]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_mask(25),
      Q => app_wdf_mask_r1(25),
      R => '0'
    );
\app_wdf_mask_r1_reg[26]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_mask(26),
      Q => app_wdf_mask_r1(26),
      R => '0'
    );
\app_wdf_mask_r1_reg[27]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_mask(27),
      Q => app_wdf_mask_r1(27),
      R => '0'
    );
\app_wdf_mask_r1_reg[28]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_mask(28),
      Q => app_wdf_mask_r1(28),
      R => '0'
    );
\app_wdf_mask_r1_reg[29]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_mask(29),
      Q => app_wdf_mask_r1(29),
      R => '0'
    );
\app_wdf_mask_r1_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_mask(2),
      Q => app_wdf_mask_r1(2),
      R => '0'
    );
\app_wdf_mask_r1_reg[30]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_mask(30),
      Q => app_wdf_mask_r1(30),
      R => '0'
    );
\app_wdf_mask_r1_reg[31]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_mask(31),
      Q => app_wdf_mask_r1(31),
      R => '0'
    );
\app_wdf_mask_r1_reg[32]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_mask(32),
      Q => app_wdf_mask_r1(32),
      R => '0'
    );
\app_wdf_mask_r1_reg[33]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_mask(33),
      Q => app_wdf_mask_r1(33),
      R => '0'
    );
\app_wdf_mask_r1_reg[34]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_mask(34),
      Q => app_wdf_mask_r1(34),
      R => '0'
    );
\app_wdf_mask_r1_reg[35]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_mask(35),
      Q => app_wdf_mask_r1(35),
      R => '0'
    );
\app_wdf_mask_r1_reg[36]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_mask(36),
      Q => app_wdf_mask_r1(36),
      R => '0'
    );
\app_wdf_mask_r1_reg[37]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_mask(37),
      Q => app_wdf_mask_r1(37),
      R => '0'
    );
\app_wdf_mask_r1_reg[38]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_mask(38),
      Q => app_wdf_mask_r1(38),
      R => '0'
    );
\app_wdf_mask_r1_reg[39]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_mask(39),
      Q => app_wdf_mask_r1(39),
      R => '0'
    );
\app_wdf_mask_r1_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_mask(3),
      Q => app_wdf_mask_r1(3),
      R => '0'
    );
\app_wdf_mask_r1_reg[40]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_mask(40),
      Q => app_wdf_mask_r1(40),
      R => '0'
    );
\app_wdf_mask_r1_reg[41]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_mask(41),
      Q => app_wdf_mask_r1(41),
      R => '0'
    );
\app_wdf_mask_r1_reg[42]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_mask(42),
      Q => app_wdf_mask_r1(42),
      R => '0'
    );
\app_wdf_mask_r1_reg[43]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_mask(43),
      Q => app_wdf_mask_r1(43),
      R => '0'
    );
\app_wdf_mask_r1_reg[44]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_mask(44),
      Q => app_wdf_mask_r1(44),
      R => '0'
    );
\app_wdf_mask_r1_reg[45]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_mask(45),
      Q => app_wdf_mask_r1(45),
      R => '0'
    );
\app_wdf_mask_r1_reg[46]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_mask(46),
      Q => app_wdf_mask_r1(46),
      R => '0'
    );
\app_wdf_mask_r1_reg[47]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_mask(47),
      Q => app_wdf_mask_r1(47),
      R => '0'
    );
\app_wdf_mask_r1_reg[48]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_mask(48),
      Q => app_wdf_mask_r1(48),
      R => '0'
    );
\app_wdf_mask_r1_reg[49]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_mask(49),
      Q => app_wdf_mask_r1(49),
      R => '0'
    );
\app_wdf_mask_r1_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_mask(4),
      Q => app_wdf_mask_r1(4),
      R => '0'
    );
\app_wdf_mask_r1_reg[50]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_mask(50),
      Q => app_wdf_mask_r1(50),
      R => '0'
    );
\app_wdf_mask_r1_reg[51]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_mask(51),
      Q => app_wdf_mask_r1(51),
      R => '0'
    );
\app_wdf_mask_r1_reg[52]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_mask(52),
      Q => app_wdf_mask_r1(52),
      R => '0'
    );
\app_wdf_mask_r1_reg[53]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_mask(53),
      Q => app_wdf_mask_r1(53),
      R => '0'
    );
\app_wdf_mask_r1_reg[54]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_mask(54),
      Q => app_wdf_mask_r1(54),
      R => '0'
    );
\app_wdf_mask_r1_reg[55]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_mask(55),
      Q => app_wdf_mask_r1(55),
      R => '0'
    );
\app_wdf_mask_r1_reg[56]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_mask(56),
      Q => app_wdf_mask_r1(56),
      R => '0'
    );
\app_wdf_mask_r1_reg[57]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_mask(57),
      Q => app_wdf_mask_r1(57),
      R => '0'
    );
\app_wdf_mask_r1_reg[58]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_mask(58),
      Q => app_wdf_mask_r1(58),
      R => '0'
    );
\app_wdf_mask_r1_reg[59]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_mask(59),
      Q => app_wdf_mask_r1(59),
      R => '0'
    );
\app_wdf_mask_r1_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_mask(5),
      Q => app_wdf_mask_r1(5),
      R => '0'
    );
\app_wdf_mask_r1_reg[60]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_mask(60),
      Q => app_wdf_mask_r1(60),
      R => '0'
    );
\app_wdf_mask_r1_reg[61]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_mask(61),
      Q => app_wdf_mask_r1(61),
      R => '0'
    );
\app_wdf_mask_r1_reg[62]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_mask(62),
      Q => app_wdf_mask_r1(62),
      R => '0'
    );
\app_wdf_mask_r1_reg[63]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_mask(63),
      Q => app_wdf_mask_r1(63),
      R => '0'
    );
\app_wdf_mask_r1_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_mask(6),
      Q => app_wdf_mask_r1(6),
      R => '0'
    );
\app_wdf_mask_r1_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_mask(7),
      Q => app_wdf_mask_r1(7),
      R => '0'
    );
\app_wdf_mask_r1_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_mask(8),
      Q => app_wdf_mask_r1(8),
      R => '0'
    );
\app_wdf_mask_r1_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_mask(9),
      Q => app_wdf_mask_r1(9),
      R => '0'
    );
app_wdf_rdy_r_copy1_reg: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wdf_rdy_ns,
      Q => app_wdf_rdy_r_copy1,
      R => '0'
    );
app_wdf_rdy_r_copy2_reg: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wdf_rdy_ns,
      Q => app_wdf_rdy_r_copy2,
      R => '0'
    );
app_wdf_rdy_r_copy3_reg: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wdf_rdy_ns,
      Q => app_wdf_rdy_r_copy3,
      R => '0'
    );
app_wdf_wren_r1_i_1: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2230"
    )
        port map (
      I0 => app_wdf_wren,
      I1 => \wr_req_counter.wr_req_cnt_r_reg[0]_1\,
      I2 => app_wdf_wren_r1,
      I3 => app_wdf_rdy_r_copy2,
      O => app_wdf_wren_ns1
    );
app_wdf_wren_r1_reg: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => app_wdf_wren_ns1,
      Q => app_wdf_wren_r1,
      R => '0'
    );
\data_buf_address_counter.data_buf_addr_cnt_r[0]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \data_buf_address_counter.data_buf_addr_cnt_r_reg\(0),
      O => \p_0_in__0\(0)
    );
\data_buf_address_counter.data_buf_addr_cnt_r[1]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \data_buf_address_counter.data_buf_addr_cnt_r_reg\(0),
      I1 => \data_buf_address_counter.data_buf_addr_cnt_r_reg\(1),
      O => \p_0_in__0\(1)
    );
\data_buf_address_counter.data_buf_addr_cnt_r[2]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"78"
    )
        port map (
      I0 => \data_buf_address_counter.data_buf_addr_cnt_r_reg\(0),
      I1 => \data_buf_address_counter.data_buf_addr_cnt_r_reg\(1),
      I2 => \data_buf_address_counter.data_buf_addr_cnt_r_reg\(2),
      O => \p_0_in__0\(2)
    );
\data_buf_address_counter.data_buf_addr_cnt_r[3]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7F80"
    )
        port map (
      I0 => \data_buf_address_counter.data_buf_addr_cnt_r_reg\(2),
      I1 => \data_buf_address_counter.data_buf_addr_cnt_r_reg\(1),
      I2 => \data_buf_address_counter.data_buf_addr_cnt_r_reg\(0),
      I3 => \data_buf_address_counter.data_buf_addr_cnt_r_reg\(3),
      O => \p_0_in__0\(3)
    );
\data_buf_address_counter.data_buf_addr_cnt_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => wr_accepted,
      D => \p_0_in__0\(0),
      Q => \data_buf_address_counter.data_buf_addr_cnt_r_reg\(0),
      R => \wr_req_counter.wr_req_cnt_r_reg[0]_1\
    );
\data_buf_address_counter.data_buf_addr_cnt_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => wr_accepted,
      D => \p_0_in__0\(1),
      Q => \data_buf_address_counter.data_buf_addr_cnt_r_reg\(1),
      R => \wr_req_counter.wr_req_cnt_r_reg[0]_1\
    );
\data_buf_address_counter.data_buf_addr_cnt_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => wr_accepted,
      D => \p_0_in__0\(2),
      Q => \data_buf_address_counter.data_buf_addr_cnt_r_reg\(2),
      R => \wr_req_counter.wr_req_cnt_r_reg[0]_1\
    );
\data_buf_address_counter.data_buf_addr_cnt_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => wr_accepted,
      D => \p_0_in__0\(3),
      Q => \data_buf_address_counter.data_buf_addr_cnt_r_reg\(3),
      R => \wr_req_counter.wr_req_cnt_r_reg[0]_1\
    );
\occupied_counter.app_wdf_rdy_r_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"5000501050105010"
    )
        port map (
      I0 => \wr_req_counter.wr_req_cnt_r_reg[0]_1\,
      I1 => \occupied_counter.occ_cnt_reg_n_0_[15]\,
      I2 => ram_init_done_r,
      I3 => \^p_0_in\(0),
      I4 => p_4_in,
      I5 => \p_0_in__0_0\(1),
      O => wdf_rdy_ns
    );
\occupied_counter.app_wdf_rdy_r_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"80"
    )
        port map (
      I0 => app_wdf_wren_r1,
      I1 => app_wdf_end_r1,
      I2 => app_wdf_rdy_r_copy1,
      O => \p_0_in__0_0\(1)
    );
\occupied_counter.app_wdf_rdy_r_reg\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wdf_rdy_ns,
      Q => app_wdf_rdy,
      R => '0'
    );
\occupied_counter.occ_cnt[0]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FF80"
    )
        port map (
      I0 => app_wdf_rdy_r_copy1,
      I1 => app_wdf_end_r1,
      I2 => app_wdf_wren_r1,
      I3 => \occupied_counter.occ_cnt_reg_n_0_[1]\,
      O => p_1_in(0)
    );
\occupied_counter.occ_cnt[10]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"BFFF8000"
    )
        port map (
      I0 => \occupied_counter.occ_cnt_reg_n_0_[9]\,
      I1 => app_wdf_wren_r1,
      I2 => app_wdf_end_r1,
      I3 => app_wdf_rdy_r_copy1,
      I4 => \occupied_counter.occ_cnt_reg_n_0_[11]\,
      O => p_1_in(10)
    );
\occupied_counter.occ_cnt[11]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"BFFF8000"
    )
        port map (
      I0 => \occupied_counter.occ_cnt_reg_n_0_[10]\,
      I1 => app_wdf_wren_r1,
      I2 => app_wdf_end_r1,
      I3 => app_wdf_rdy_r_copy1,
      I4 => \occupied_counter.occ_cnt_reg_n_0_[12]\,
      O => p_1_in(11)
    );
\occupied_counter.occ_cnt[12]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"BFFF8000"
    )
        port map (
      I0 => \occupied_counter.occ_cnt_reg_n_0_[11]\,
      I1 => app_wdf_wren_r1,
      I2 => app_wdf_end_r1,
      I3 => app_wdf_rdy_r_copy1,
      I4 => \occupied_counter.occ_cnt_reg_n_0_[13]\,
      O => p_1_in(12)
    );
\occupied_counter.occ_cnt[13]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"BFFF8000"
    )
        port map (
      I0 => \occupied_counter.occ_cnt_reg_n_0_[12]\,
      I1 => app_wdf_wren_r1,
      I2 => app_wdf_end_r1,
      I3 => app_wdf_rdy_r_copy1,
      I4 => p_4_in,
      O => p_1_in(13)
    );
\occupied_counter.occ_cnt[14]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"BFFF8000"
    )
        port map (
      I0 => \occupied_counter.occ_cnt_reg_n_0_[13]\,
      I1 => app_wdf_wren_r1,
      I2 => app_wdf_end_r1,
      I3 => app_wdf_rdy_r_copy1,
      I4 => \occupied_counter.occ_cnt_reg_n_0_[15]\,
      O => p_1_in(14)
    );
\occupied_counter.occ_cnt[15]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6AAA"
    )
        port map (
      I0 => \^p_0_in\(0),
      I1 => app_wdf_rdy_r_copy1,
      I2 => app_wdf_end_r1,
      I3 => app_wdf_wren_r1,
      O => \occupied_counter.occ_cnt[15]_i_1_n_0\
    );
\occupied_counter.occ_cnt[15]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8000"
    )
        port map (
      I0 => app_wdf_rdy_r_copy1,
      I1 => app_wdf_end_r1,
      I2 => app_wdf_wren_r1,
      I3 => p_4_in,
      O => p_1_in(15)
    );
\occupied_counter.occ_cnt[1]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"BFFF8000"
    )
        port map (
      I0 => \occupied_counter.occ_cnt_reg_n_0_[0]\,
      I1 => app_wdf_wren_r1,
      I2 => app_wdf_end_r1,
      I3 => app_wdf_rdy_r_copy1,
      I4 => \occupied_counter.occ_cnt_reg_n_0_[2]\,
      O => p_1_in(1)
    );
\occupied_counter.occ_cnt[2]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"BFFF8000"
    )
        port map (
      I0 => \occupied_counter.occ_cnt_reg_n_0_[1]\,
      I1 => app_wdf_wren_r1,
      I2 => app_wdf_end_r1,
      I3 => app_wdf_rdy_r_copy1,
      I4 => \occupied_counter.occ_cnt_reg_n_0_[3]\,
      O => p_1_in(2)
    );
\occupied_counter.occ_cnt[3]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"BFFF8000"
    )
        port map (
      I0 => \occupied_counter.occ_cnt_reg_n_0_[2]\,
      I1 => app_wdf_wren_r1,
      I2 => app_wdf_end_r1,
      I3 => app_wdf_rdy_r_copy1,
      I4 => \occupied_counter.occ_cnt_reg_n_0_[4]\,
      O => p_1_in(3)
    );
\occupied_counter.occ_cnt[4]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"BFFF8000"
    )
        port map (
      I0 => \occupied_counter.occ_cnt_reg_n_0_[3]\,
      I1 => app_wdf_wren_r1,
      I2 => app_wdf_end_r1,
      I3 => app_wdf_rdy_r_copy1,
      I4 => \occupied_counter.occ_cnt_reg_n_0_[5]\,
      O => p_1_in(4)
    );
\occupied_counter.occ_cnt[5]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"BFFF8000"
    )
        port map (
      I0 => \occupied_counter.occ_cnt_reg_n_0_[4]\,
      I1 => app_wdf_wren_r1,
      I2 => app_wdf_end_r1,
      I3 => app_wdf_rdy_r_copy1,
      I4 => \occupied_counter.occ_cnt_reg_n_0_[6]\,
      O => p_1_in(5)
    );
\occupied_counter.occ_cnt[6]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"BFFF8000"
    )
        port map (
      I0 => \occupied_counter.occ_cnt_reg_n_0_[5]\,
      I1 => app_wdf_wren_r1,
      I2 => app_wdf_end_r1,
      I3 => app_wdf_rdy_r_copy1,
      I4 => \occupied_counter.occ_cnt_reg_n_0_[7]\,
      O => p_1_in(6)
    );
\occupied_counter.occ_cnt[7]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"BFFF8000"
    )
        port map (
      I0 => \occupied_counter.occ_cnt_reg_n_0_[6]\,
      I1 => app_wdf_wren_r1,
      I2 => app_wdf_end_r1,
      I3 => app_wdf_rdy_r_copy1,
      I4 => \occupied_counter.occ_cnt_reg_n_0_[8]\,
      O => p_1_in(7)
    );
\occupied_counter.occ_cnt[8]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"BFFF8000"
    )
        port map (
      I0 => \occupied_counter.occ_cnt_reg_n_0_[7]\,
      I1 => app_wdf_wren_r1,
      I2 => app_wdf_end_r1,
      I3 => app_wdf_rdy_r_copy1,
      I4 => \occupied_counter.occ_cnt_reg_n_0_[9]\,
      O => p_1_in(8)
    );
\occupied_counter.occ_cnt[9]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"BFFF8000"
    )
        port map (
      I0 => \occupied_counter.occ_cnt_reg_n_0_[8]\,
      I1 => app_wdf_wren_r1,
      I2 => app_wdf_end_r1,
      I3 => app_wdf_rdy_r_copy1,
      I4 => \occupied_counter.occ_cnt_reg_n_0_[10]\,
      O => p_1_in(9)
    );
\occupied_counter.occ_cnt_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => \occupied_counter.occ_cnt[15]_i_1_n_0\,
      D => p_1_in(0),
      Q => \occupied_counter.occ_cnt_reg_n_0_[0]\,
      R => \wr_req_counter.wr_req_cnt_r_reg[0]_1\
    );
\occupied_counter.occ_cnt_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => \occupied_counter.occ_cnt[15]_i_1_n_0\,
      D => p_1_in(10),
      Q => \occupied_counter.occ_cnt_reg_n_0_[10]\,
      R => \wr_req_counter.wr_req_cnt_r_reg[0]_1\
    );
\occupied_counter.occ_cnt_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => \occupied_counter.occ_cnt[15]_i_1_n_0\,
      D => p_1_in(11),
      Q => \occupied_counter.occ_cnt_reg_n_0_[11]\,
      R => \wr_req_counter.wr_req_cnt_r_reg[0]_1\
    );
\occupied_counter.occ_cnt_reg[12]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => \occupied_counter.occ_cnt[15]_i_1_n_0\,
      D => p_1_in(12),
      Q => \occupied_counter.occ_cnt_reg_n_0_[12]\,
      R => \wr_req_counter.wr_req_cnt_r_reg[0]_1\
    );
\occupied_counter.occ_cnt_reg[13]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => \occupied_counter.occ_cnt[15]_i_1_n_0\,
      D => p_1_in(13),
      Q => \occupied_counter.occ_cnt_reg_n_0_[13]\,
      R => \wr_req_counter.wr_req_cnt_r_reg[0]_1\
    );
\occupied_counter.occ_cnt_reg[14]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => \occupied_counter.occ_cnt[15]_i_1_n_0\,
      D => p_1_in(14),
      Q => p_4_in,
      R => \wr_req_counter.wr_req_cnt_r_reg[0]_1\
    );
\occupied_counter.occ_cnt_reg[15]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => \occupied_counter.occ_cnt[15]_i_1_n_0\,
      D => p_1_in(15),
      Q => \occupied_counter.occ_cnt_reg_n_0_[15]\,
      R => \wr_req_counter.wr_req_cnt_r_reg[0]_1\
    );
\occupied_counter.occ_cnt_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => \occupied_counter.occ_cnt[15]_i_1_n_0\,
      D => p_1_in(1),
      Q => \occupied_counter.occ_cnt_reg_n_0_[1]\,
      R => \wr_req_counter.wr_req_cnt_r_reg[0]_1\
    );
\occupied_counter.occ_cnt_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => \occupied_counter.occ_cnt[15]_i_1_n_0\,
      D => p_1_in(2),
      Q => \occupied_counter.occ_cnt_reg_n_0_[2]\,
      R => \wr_req_counter.wr_req_cnt_r_reg[0]_1\
    );
\occupied_counter.occ_cnt_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => \occupied_counter.occ_cnt[15]_i_1_n_0\,
      D => p_1_in(3),
      Q => \occupied_counter.occ_cnt_reg_n_0_[3]\,
      R => \wr_req_counter.wr_req_cnt_r_reg[0]_1\
    );
\occupied_counter.occ_cnt_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => \occupied_counter.occ_cnt[15]_i_1_n_0\,
      D => p_1_in(4),
      Q => \occupied_counter.occ_cnt_reg_n_0_[4]\,
      R => \wr_req_counter.wr_req_cnt_r_reg[0]_1\
    );
\occupied_counter.occ_cnt_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => \occupied_counter.occ_cnt[15]_i_1_n_0\,
      D => p_1_in(5),
      Q => \occupied_counter.occ_cnt_reg_n_0_[5]\,
      R => \wr_req_counter.wr_req_cnt_r_reg[0]_1\
    );
\occupied_counter.occ_cnt_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => \occupied_counter.occ_cnt[15]_i_1_n_0\,
      D => p_1_in(6),
      Q => \occupied_counter.occ_cnt_reg_n_0_[6]\,
      R => \wr_req_counter.wr_req_cnt_r_reg[0]_1\
    );
\occupied_counter.occ_cnt_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => \occupied_counter.occ_cnt[15]_i_1_n_0\,
      D => p_1_in(7),
      Q => \occupied_counter.occ_cnt_reg_n_0_[7]\,
      R => \wr_req_counter.wr_req_cnt_r_reg[0]_1\
    );
\occupied_counter.occ_cnt_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => \occupied_counter.occ_cnt[15]_i_1_n_0\,
      D => p_1_in(8),
      Q => \occupied_counter.occ_cnt_reg_n_0_[8]\,
      R => \wr_req_counter.wr_req_cnt_r_reg[0]_1\
    );
\occupied_counter.occ_cnt_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => \occupied_counter.occ_cnt[15]_i_1_n_0\,
      D => p_1_in(9),
      Q => \occupied_counter.occ_cnt_reg_n_0_[9]\,
      R => \wr_req_counter.wr_req_cnt_r_reg[0]_1\
    );
\pointer_ram.rams[0].RAM32M0\: unisim.vcomponents.RAM32M
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      IS_WCLK_INVERTED => '0'
    )
        port map (
      ADDRA(4 downto 0) => B"00000",
      ADDRB(4) => '0',
      ADDRB(3 downto 0) => \data_buf_address_counter.data_buf_addr_cnt_r_reg\(3 downto 0),
      ADDRC(4) => '0',
      ADDRC(3 downto 0) => \write_data_control.wr_data_indx_r_reg\(3 downto 0),
      ADDRD(4) => '0',
      ADDRD(3 downto 0) => ADDRD(3 downto 0),
      DIA(1 downto 0) => B"00",
      DIB(1 downto 0) => \pointer_ram.pointer_wr_data\(1 downto 0),
      DIC(1 downto 0) => \pointer_ram.pointer_wr_data\(1 downto 0),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => \NLW_pointer_ram.rams[0].RAM32M0_DOA_UNCONNECTED\(1 downto 0),
      DOB(1 downto 0) => wr_data_buf_addr(1 downto 0),
      DOC(1 downto 0) => wr_data_pntr(1 downto 0),
      DOD(1 downto 0) => \NLW_pointer_ram.rams[0].RAM32M0_DOD_UNCONNECTED\(1 downto 0),
      WCLK => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      WE => \pointer_ram.pointer_we\
    );
\pointer_ram.rams[1].RAM32M0\: unisim.vcomponents.RAM32M
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      IS_WCLK_INVERTED => '0'
    )
        port map (
      ADDRA(4 downto 0) => B"00000",
      ADDRB(4) => '0',
      ADDRB(3 downto 0) => \data_buf_address_counter.data_buf_addr_cnt_r_reg\(3 downto 0),
      ADDRC(4) => '0',
      ADDRC(3 downto 0) => \write_data_control.wr_data_indx_r_reg\(3 downto 0),
      ADDRD(4) => '0',
      ADDRD(3 downto 0) => ADDRD(3 downto 0),
      DIA(1 downto 0) => B"00",
      DIB(1 downto 0) => \pointer_ram.pointer_wr_data\(3 downto 2),
      DIC(1 downto 0) => \pointer_ram.pointer_wr_data\(3 downto 2),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => \NLW_pointer_ram.rams[1].RAM32M0_DOA_UNCONNECTED\(1 downto 0),
      DOB(1 downto 0) => wr_data_buf_addr(3 downto 2),
      DOC(1 downto 0) => wr_data_pntr(3 downto 2),
      DOD(1 downto 0) => \NLW_pointer_ram.rams[1].RAM32M0_DOD_UNCONNECTED\(1 downto 0),
      WCLK => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      WE => \pointer_ram.pointer_we\
    );
\read_data_indx.rd_data_indx_r[0]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \^q\(0),
      O => \p_0_in__1\(0)
    );
\read_data_indx.rd_data_indx_r[1]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \^q\(0),
      I1 => \^q\(1),
      O => \p_0_in__1\(1)
    );
\read_data_indx.rd_data_indx_r[2]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"78"
    )
        port map (
      I0 => \^q\(0),
      I1 => \^q\(1),
      I2 => \^q\(2),
      O => \p_0_in__1\(2)
    );
\read_data_indx.rd_data_indx_r[3]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7F80"
    )
        port map (
      I0 => \^q\(2),
      I1 => \^q\(1),
      I2 => \^q\(0),
      I3 => \^q\(3),
      O => \p_0_in__1\(3)
    );
\read_data_indx.rd_data_indx_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => E(0),
      D => \p_0_in__1\(0),
      Q => \^q\(0),
      R => \wr_req_counter.wr_req_cnt_r_reg[0]_1\
    );
\read_data_indx.rd_data_indx_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => E(0),
      D => \p_0_in__1\(1),
      Q => \^q\(1),
      R => \wr_req_counter.wr_req_cnt_r_reg[0]_1\
    );
\read_data_indx.rd_data_indx_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => E(0),
      D => \p_0_in__1\(2),
      Q => \^q\(2),
      R => \wr_req_counter.wr_req_cnt_r_reg[0]_1\
    );
\read_data_indx.rd_data_indx_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => E(0),
      D => \p_0_in__1\(3),
      Q => \^q\(3),
      R => \wr_req_counter.wr_req_cnt_r_reg[0]_1\
    );
\read_data_indx.rd_data_upd_indx_r_reg\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => E(0),
      Q => \^p_0_in\(0),
      R => '0'
    );
\wr_req_counter.wr_req_cnt_r[1]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"DB24"
    )
        port map (
      I0 => \^wr_req_counter.wr_req_cnt_r_reg[1]_0\(0),
      I1 => \^p_0_in\(0),
      I2 => wr_accepted,
      I3 => \^wr_req_counter.wr_req_cnt_r_reg[1]_0\(1),
      O => \wr_req_counter.wr_req_cnt_r[1]_i_1_n_0\
    );
\wr_req_counter.wr_req_cnt_r[2]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"F7EF0810"
    )
        port map (
      I0 => \^wr_req_counter.wr_req_cnt_r_reg[1]_0\(0),
      I1 => \^wr_req_counter.wr_req_cnt_r_reg[1]_0\(1),
      I2 => \^p_0_in\(0),
      I3 => wr_accepted,
      I4 => \wr_req_counter.wr_req_cnt_r\(2),
      O => \wr_req_counter.wr_req_cnt_r[2]_i_1_n_0\
    );
\wr_req_counter.wr_req_cnt_r[3]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FF7FFEFF00800100"
    )
        port map (
      I0 => \wr_req_counter.wr_req_cnt_r\(2),
      I1 => \^wr_req_counter.wr_req_cnt_r_reg[1]_0\(0),
      I2 => \^wr_req_counter.wr_req_cnt_r_reg[1]_0\(1),
      I3 => \^p_0_in\(0),
      I4 => wr_accepted,
      I5 => \wr_req_counter.wr_req_cnt_r\(3),
      O => \wr_req_counter.wr_req_cnt_r[3]_i_1_n_0\
    );
\wr_req_counter.wr_req_cnt_r[4]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"000000006AA9AAAA"
    )
        port map (
      I0 => \wr_req_counter.wr_req_cnt_r\(4),
      I1 => \wr_req_counter.wr_req_cnt_r\(3),
      I2 => \wr_req_counter.wr_req_cnt_r\(2),
      I3 => \wr_req_counter.wr_req_cnt_r[4]_i_2_n_0\,
      I4 => \wr_req_counter.wr_req_cnt_r_reg[4]_0\,
      I5 => \wr_req_counter.wr_req_cnt_r_reg[0]_1\,
      O => \wr_req_counter.wr_req_cnt_r[4]_i_1_n_0\
    );
\wr_req_counter.wr_req_cnt_r[4]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"80FE"
    )
        port map (
      I0 => \^wr_req_counter.wr_req_cnt_r_reg[1]_0\(1),
      I1 => wr_accepted,
      I2 => \^wr_req_counter.wr_req_cnt_r_reg[1]_0\(0),
      I3 => \wr_req_counter.wr_req_cnt_r\(2),
      O => \wr_req_counter.wr_req_cnt_r[4]_i_2_n_0\
    );
\wr_req_counter.wr_req_cnt_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => \wr_req_counter.wr_req_cnt_r_reg[0]_2\,
      Q => \^wr_req_counter.wr_req_cnt_r_reg[1]_0\(0),
      R => \wr_req_counter.wr_req_cnt_r_reg[0]_1\
    );
\wr_req_counter.wr_req_cnt_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => \wr_req_counter.wr_req_cnt_r[1]_i_1_n_0\,
      Q => \^wr_req_counter.wr_req_cnt_r_reg[1]_0\(1),
      R => \wr_req_counter.wr_req_cnt_r_reg[0]_1\
    );
\wr_req_counter.wr_req_cnt_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => \wr_req_counter.wr_req_cnt_r[2]_i_1_n_0\,
      Q => \wr_req_counter.wr_req_cnt_r\(2),
      R => \wr_req_counter.wr_req_cnt_r_reg[0]_1\
    );
\wr_req_counter.wr_req_cnt_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => \wr_req_counter.wr_req_cnt_r[3]_i_1_n_0\,
      Q => \wr_req_counter.wr_req_cnt_r\(3),
      R => \wr_req_counter.wr_req_cnt_r_reg[0]_1\
    );
\wr_req_counter.wr_req_cnt_r_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => \wr_req_counter.wr_req_cnt_r[4]_i_1_n_0\,
      Q => \wr_req_counter.wr_req_cnt_r\(4),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(0),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(0),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[100]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(100),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(100),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[101]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(101),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(101),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[102]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(102),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(102),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[103]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(103),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(103),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[104]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(104),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(104),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[105]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(105),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(105),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[106]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(106),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(106),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[107]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(107),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(107),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[108]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(108),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(108),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[109]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(109),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(109),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(10),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(10),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[110]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(110),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(110),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[111]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(111),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(111),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[112]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(112),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(112),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[113]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(113),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(113),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[114]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(114),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(114),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[115]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(115),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(115),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[116]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(116),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(116),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[117]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(117),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(117),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[118]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(118),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(118),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[119]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(119),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(119),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(11),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(11),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[120]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(120),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(120),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[121]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(121),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(121),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[122]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(122),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(122),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[123]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(123),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(123),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[124]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(124),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(124),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[125]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(125),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(125),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[126]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(126),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(126),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[127]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(127),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(127),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[128]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(128),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(128),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[129]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(129),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(129),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[12]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(12),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(12),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[130]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(130),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(130),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[131]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(131),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(131),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[132]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(132),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(132),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[133]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(133),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(133),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[134]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(134),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(134),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[135]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(135),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(135),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[136]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(136),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(136),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[137]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(137),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(137),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[138]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(138),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(138),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[139]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(139),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(139),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[13]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(13),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(13),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[140]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(140),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(140),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[141]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(141),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(141),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[142]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(142),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(142),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[143]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(143),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(143),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[144]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(144),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(144),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[145]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(145),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(145),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[146]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(146),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(146),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[147]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(147),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(147),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[148]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(148),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(148),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[149]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(149),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(149),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[14]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(14),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(14),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[150]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(150),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(150),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[151]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(151),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(151),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[152]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(152),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(152),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[153]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(153),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(153),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[154]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(154),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(154),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[155]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(155),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(155),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[156]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(156),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(156),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[157]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(157),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(157),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[158]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(158),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(158),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[159]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(159),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(159),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[15]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(15),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(15),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[160]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(160),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(160),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[161]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(161),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(161),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[162]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(162),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(162),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[163]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(163),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(163),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[164]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(164),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(164),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[165]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(165),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(165),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[166]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(166),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(166),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[167]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(167),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(167),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[168]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(168),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(168),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[169]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(169),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(169),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[16]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(16),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(16),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[170]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(170),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(170),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[171]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(171),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(171),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[172]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(172),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(172),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[173]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(173),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(173),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[174]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(174),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(174),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[175]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(175),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(175),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[176]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(176),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(176),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[177]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(177),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(177),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[178]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(178),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(178),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[179]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(179),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(179),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[17]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(17),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(17),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[180]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(180),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(180),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[181]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(181),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(181),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[182]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(182),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(182),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[183]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(183),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(183),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[184]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(184),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(184),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[185]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(185),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(185),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[186]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(186),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(186),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[187]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(187),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(187),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[188]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(188),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(188),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[189]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(189),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(189),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[18]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(18),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(18),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[190]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(190),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(190),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[191]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(191),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(191),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[192]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(192),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(192),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[193]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(193),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(193),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[194]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(194),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(194),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[195]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(195),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(195),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[196]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(196),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(196),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[197]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(197),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(197),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[198]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(198),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(198),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[199]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(199),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(199),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[19]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(19),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(19),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(1),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(1),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[200]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(200),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(200),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[201]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(201),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(201),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[202]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(202),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(202),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[203]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(203),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(203),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[204]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(204),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(204),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[205]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(205),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(205),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[206]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(206),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(206),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[207]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(207),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(207),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[208]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(208),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(208),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[209]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(209),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(209),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[20]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(20),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(20),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[210]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(210),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(210),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[211]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(211),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(211),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[212]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(212),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(212),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[213]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(213),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(213),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[214]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(214),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(214),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[215]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(215),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(215),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[216]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(216),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(216),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[217]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(217),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(217),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[218]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(218),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(218),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[219]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(219),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(219),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[21]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(21),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(21),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[220]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(220),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(220),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[221]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(221),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(221),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[222]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(222),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(222),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[223]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(223),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(223),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[224]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(224),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(224),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[225]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(225),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(225),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[226]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(226),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(226),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[227]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(227),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(227),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[228]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(228),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(228),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[229]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(229),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(229),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[22]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(22),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(22),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[230]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(230),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(230),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[231]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(231),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(231),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[232]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(232),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(232),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[233]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(233),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(233),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[234]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(234),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(234),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[235]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(235),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(235),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[236]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(236),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(236),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[237]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(237),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(237),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[238]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(238),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(238),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[239]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(239),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(239),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[23]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(23),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(23),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[240]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(240),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(240),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[241]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(241),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(241),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[242]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(242),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(242),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[243]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(243),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(243),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[244]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(244),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(244),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[245]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(245),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(245),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[246]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(246),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(246),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[247]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(247),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(247),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[248]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(248),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(248),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[249]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(249),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(249),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[24]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(24),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(24),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[250]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(250),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(250),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[251]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(251),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(251),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[252]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(252),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(252),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[253]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(253),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(253),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[254]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(254),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(254),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[255]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(255),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(255),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[256]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(256),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(256),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[257]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(257),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(257),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[258]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(258),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(258),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[259]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(259),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(259),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[25]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(25),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(25),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[260]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(260),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(260),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[261]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(261),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(261),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[262]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(262),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(262),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[263]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(263),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(263),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[264]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(264),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(264),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[265]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(265),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(265),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[266]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(266),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(266),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[267]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(267),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(267),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[268]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(268),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(268),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[269]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(269),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(269),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[26]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(26),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(26),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[270]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(270),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(270),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[271]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(271),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(271),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[272]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(272),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(272),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[273]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(273),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(273),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[274]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(274),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(274),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[275]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(275),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(275),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[276]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(276),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(276),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[277]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(277),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(277),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[278]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(278),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(278),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[279]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(279),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(279),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[27]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(27),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(27),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[280]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(280),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(280),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[281]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(281),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(281),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[282]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(282),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(282),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[283]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(283),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(283),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[284]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(284),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(284),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[285]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(285),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(285),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[286]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(286),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(286),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[287]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(287),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(287),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[288]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(288),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(288),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[289]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(289),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(289),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[28]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(28),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(28),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[290]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(290),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(290),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[291]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(291),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(291),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[292]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(292),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(292),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[293]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(293),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(293),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[294]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(294),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(294),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[295]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(295),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(295),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[296]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(296),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(296),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[297]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(297),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(297),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[298]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(298),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(298),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[299]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(299),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(299),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[29]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(29),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(29),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(2),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(2),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[300]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(300),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(300),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[301]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(301),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(301),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[302]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(302),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(302),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[303]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(303),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(303),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[304]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(304),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(304),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[305]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(305),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(305),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[306]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(306),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(306),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[307]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(307),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(307),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[308]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(308),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(308),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[309]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(309),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(309),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[30]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(30),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(30),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[310]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(310),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(310),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[311]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(311),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(311),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[312]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(312),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(312),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[313]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(313),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(313),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[314]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(314),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(314),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[315]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(315),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(315),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[316]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(316),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(316),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[317]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(317),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(317),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[318]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(318),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(318),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[319]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(319),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(319),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[31]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(31),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(31),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[320]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(320),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(320),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[321]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(321),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(321),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[322]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(322),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(322),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[323]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(323),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(323),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[324]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(324),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(324),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[325]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(325),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(325),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[326]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(326),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(326),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[327]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(327),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(327),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[328]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(328),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(328),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[329]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(329),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(329),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[32]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(32),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(32),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[330]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(330),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(330),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[331]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(331),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(331),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[332]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(332),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(332),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[333]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(333),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(333),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[334]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(334),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(334),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[335]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(335),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(335),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[336]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(336),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(336),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[337]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(337),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(337),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[338]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(338),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(338),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[339]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(339),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(339),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[33]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(33),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(33),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[340]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(340),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(340),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[341]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(341),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(341),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[342]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(342),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(342),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[343]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(343),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(343),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[344]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(344),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(344),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[345]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(345),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(345),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[346]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(346),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(346),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[347]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(347),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(347),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[348]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(348),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(348),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[349]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(349),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(349),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[34]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(34),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(34),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[350]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(350),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(350),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[351]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(351),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(351),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[352]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(352),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(352),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[353]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(353),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(353),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[354]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(354),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(354),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[355]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(355),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(355),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[356]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(356),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(356),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[357]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(357),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(357),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[358]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(358),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(358),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[359]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(359),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(359),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[35]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(35),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(35),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[360]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(360),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(360),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[361]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(361),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(361),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[362]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(362),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(362),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[363]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(363),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(363),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[364]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(364),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(364),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[365]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(365),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(365),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[366]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(366),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(366),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[367]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(367),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(367),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[368]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(368),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(368),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[369]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(369),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(369),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[36]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(36),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(36),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[370]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(370),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(370),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[371]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(371),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(371),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[372]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(372),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(372),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[373]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(373),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(373),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[374]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(374),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(374),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[375]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(375),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(375),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[376]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(376),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(376),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[377]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(377),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(377),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[378]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(378),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(378),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[379]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(379),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(379),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[37]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(37),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(37),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[380]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(380),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(380),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[381]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(381),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(381),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[382]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(382),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(382),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[383]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(383),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(383),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[384]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(384),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(384),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[385]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(385),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(385),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[386]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(386),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(386),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[387]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(387),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(387),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[388]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(388),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(388),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[389]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(389),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(389),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[38]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(38),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(38),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[390]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(390),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(390),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[391]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(391),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(391),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[392]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(392),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(392),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[393]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(393),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(393),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[394]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(394),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(394),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[395]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(395),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(395),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[396]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(396),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(396),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[397]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(397),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(397),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[398]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(398),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(398),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[399]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(399),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(399),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[39]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(39),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(39),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(3),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(3),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[400]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(400),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(400),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[401]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(401),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(401),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[402]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(402),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(402),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[403]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(403),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(403),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[404]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(404),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(404),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[405]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(405),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(405),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[406]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(406),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(406),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[407]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(407),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(407),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[408]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(408),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(408),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[409]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(409),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(409),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[40]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(40),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(40),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[410]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(410),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(410),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[411]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(411),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(411),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[412]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(412),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(412),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[413]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(413),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(413),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[414]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(414),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(414),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[415]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(415),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(415),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[416]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(416),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(416),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[417]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(417),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(417),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[418]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(418),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(418),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[419]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(419),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(419),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[41]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(41),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(41),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[420]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(420),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(420),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[421]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(421),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(421),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[422]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(422),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(422),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[423]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(423),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(423),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[424]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(424),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(424),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[425]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(425),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(425),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[426]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(426),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(426),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[427]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(427),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(427),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[428]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(428),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(428),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[429]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(429),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(429),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[42]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(42),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(42),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[430]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(430),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(430),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[431]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(431),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(431),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[432]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(432),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(432),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[433]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(433),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(433),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[434]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(434),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(434),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[435]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(435),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(435),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[436]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(436),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(436),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[437]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(437),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(437),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[438]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(438),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(438),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[439]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(439),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(439),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[43]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(43),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(43),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[440]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(440),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(440),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[441]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(441),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(441),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[442]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(442),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(442),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[443]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(443),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(443),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[444]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(444),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(444),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[445]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(445),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(445),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[446]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(446),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(446),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[447]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(447),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(447),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[448]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(448),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(448),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[449]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(449),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(449),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[44]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(44),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(44),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[450]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(450),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(450),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[451]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(451),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(451),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[452]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(452),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(452),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[453]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(453),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(453),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[454]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(454),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(454),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[455]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(455),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(455),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[456]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(456),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(456),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[457]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(457),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(457),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[458]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(458),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(458),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[459]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(459),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(459),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[45]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(45),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(45),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[460]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(460),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(460),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[461]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(461),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(461),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[462]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(462),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(462),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[463]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(463),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(463),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[464]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(464),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(464),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[465]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(465),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(465),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[466]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(466),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(466),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[467]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(467),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(467),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[468]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(468),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(468),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[469]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(469),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(469),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[46]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(46),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(46),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[470]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(470),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(470),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[471]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(471),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(471),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[472]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(472),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(472),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[473]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(473),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(473),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[474]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(474),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(474),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[475]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(475),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(475),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[476]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(476),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(476),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[477]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(477),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(477),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[478]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(478),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(478),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[479]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(479),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(479),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[47]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(47),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(47),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[480]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(480),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(480),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[481]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(481),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(481),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[482]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(482),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(482),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[483]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(483),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(483),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[484]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(484),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(484),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[485]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(485),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(485),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[486]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(486),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(486),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[487]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(487),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(487),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[488]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(488),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(488),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[489]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(489),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(489),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[48]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(48),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(48),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[490]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(490),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(490),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[491]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(491),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(491),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[492]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(492),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(492),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[493]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(493),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(493),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[494]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(494),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(494),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[495]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(495),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(495),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[496]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(496),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(496),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[497]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(497),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(497),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[498]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(498),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(498),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[499]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(499),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(499),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[49]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(49),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(49),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(4),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(4),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[500]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(500),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(500),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[501]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(501),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(501),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[502]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(502),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(502),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[503]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(503),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(503),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[504]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(504),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(504),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[505]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(505),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(505),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[506]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(506),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(506),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[507]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(507),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(507),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[508]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(508),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(508),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[509]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(509),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(509),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[50]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(50),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(50),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[510]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(510),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(510),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[511]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(511),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(511),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[512]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(512),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(512),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[513]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(513),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(513),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[514]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(514),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(514),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[515]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(515),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(515),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[516]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(516),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(516),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[517]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(517),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(517),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[518]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(518),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(518),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[519]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(519),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(519),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[51]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(51),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(51),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[520]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(520),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(520),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[521]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(521),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(521),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[522]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(522),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(522),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[523]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(523),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(523),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[524]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(524),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(524),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[525]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(525),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(525),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[526]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(526),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(526),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[527]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(527),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(527),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[528]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(528),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(528),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[529]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(529),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(529),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[52]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(52),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(52),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[530]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(530),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(530),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[531]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(531),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(531),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[532]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(532),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(532),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[533]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(533),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(533),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[534]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(534),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(534),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[535]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(535),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(535),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[536]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(536),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(536),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[537]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(537),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(537),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[538]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(538),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(538),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[539]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(539),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(539),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[53]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(53),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(53),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[540]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(540),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(540),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[541]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(541),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(541),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[542]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(542),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(542),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[543]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(543),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(543),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[544]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(544),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(544),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[545]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(545),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(545),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[546]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(546),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(546),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[547]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(547),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(547),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[548]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(548),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(548),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[549]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(549),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(549),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[54]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(54),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(54),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[550]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(550),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(550),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[551]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(551),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(551),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[552]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(552),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(552),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[553]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(553),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(553),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[554]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(554),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(554),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[555]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(555),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(555),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[556]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(556),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(556),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[557]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(557),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(557),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[558]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(558),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(558),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[559]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(559),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(559),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[55]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(55),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(55),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[560]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(560),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(560),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[561]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(561),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(561),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[562]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(562),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(562),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[563]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(563),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(563),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[564]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(564),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(564),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[565]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(565),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(565),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[566]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(566),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(566),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[567]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(567),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(567),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[568]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(568),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(568),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[569]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(569),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(569),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[56]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(56),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(56),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[570]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(570),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(570),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[571]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(571),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(571),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[572]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(572),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(572),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[573]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(573),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(573),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[574]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(574),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(574),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[575]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(575),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(575),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[57]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(57),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(57),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[58]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(58),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(58),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[59]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(59),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(59),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(5),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(5),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[60]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(60),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(60),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[61]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(61),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(61),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[62]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(62),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(62),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[63]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(63),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(63),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[64]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(64),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(64),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[65]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(65),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(65),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[66]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(66),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(66),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[67]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(67),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(67),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[68]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(68),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(68),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[69]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(69),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(69),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(6),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(6),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[70]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(70),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(70),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[71]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(71),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(71),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[72]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(72),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(72),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[73]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(73),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(73),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[74]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(74),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(74),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[75]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(75),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(75),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[76]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(76),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(76),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[77]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(77),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(77),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[78]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(78),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(78),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[79]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(79),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(79),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(7),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(7),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[80]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(80),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(80),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[81]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(81),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(81),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[82]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(82),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(82),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[83]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(83),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(83),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[84]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(84),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(84),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[85]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(85),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(85),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[86]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(86),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(86),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[87]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(87),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(87),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[88]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(88),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(88),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[89]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(89),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(89),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(8),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(8),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[90]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(90),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(90),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[91]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(91),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(91),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[92]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(92),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(92),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[93]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(93),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(93),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[94]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(94),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(94),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[95]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(95),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(95),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[96]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(96),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(96),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[97]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(97),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(97),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[98]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(98),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(98),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[99]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(99),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(99),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wr_buf_out_data_w(9),
      Q => \write_buffer.wr_buf_out_data_reg[575]_0\(9),
      R => '0'
    );
\write_buffer.wr_buffer_ram[0].RAM32M0\: unisim.vcomponents.RAM32M
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      IS_WCLK_INVERTED => '0'
    )
        port map (
      ADDRA(4 downto 1) => wr_data_addr(3 downto 0),
      ADDRA(0) => '0',
      ADDRB(4 downto 1) => wr_data_addr(3 downto 0),
      ADDRB(0) => '0',
      ADDRC(4 downto 1) => wr_data_addr(3 downto 0),
      ADDRC(0) => '0',
      ADDRD(4 downto 1) => wb_wr_data_addr_w(4 downto 1),
      ADDRD(0) => \write_data_control.wb_wr_data_addr0_ns\,
      DIA(1 downto 0) => \write_buffer.wr_buf_in_data\(5 downto 4),
      DIB(1 downto 0) => \write_buffer.wr_buf_in_data\(3 downto 2),
      DIC(1 downto 0) => \write_buffer.wr_buf_in_data\(1 downto 0),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => wr_buf_out_data_w(5 downto 4),
      DOB(1 downto 0) => wr_buf_out_data_w(3 downto 2),
      DOC(1 downto 0) => wr_buf_out_data_w(1 downto 0),
      DOD(1 downto 0) => \NLW_write_buffer.wr_buffer_ram[0].RAM32M0_DOD_UNCONNECTED\(1 downto 0),
      WCLK => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      WE => wdf_rdy_ns
    );
\write_buffer.wr_buffer_ram[0].RAM32M0_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(5),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(5),
      O => \write_buffer.wr_buf_in_data\(5)
    );
\write_buffer.wr_buffer_ram[0].RAM32M0_i_10\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"00AC"
    )
        port map (
      I0 => wr_data_pntr(0),
      I1 => \write_data_control.wb_wr_data_addr_r\(1),
      I2 => \write_data_control.wr_data_addr_le\,
      I3 => \wr_req_counter.wr_req_cnt_r_reg[0]_1\,
      O => wb_wr_data_addr_w(1)
    );
\write_buffer.wr_buffer_ram[0].RAM32M0_i_11\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"02020F00"
    )
        port map (
      I0 => app_wdf_rdy_r_copy3,
      I1 => app_wdf_end_r1,
      I2 => \wr_req_counter.wr_req_cnt_r_reg[0]_1\,
      I3 => \write_data_control.wb_wr_data_addr0_r\,
      I4 => app_wdf_wren_r1,
      O => \write_data_control.wb_wr_data_addr0_ns\
    );
\write_buffer.wr_buffer_ram[0].RAM32M0_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(4),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(4),
      O => \write_buffer.wr_buf_in_data\(4)
    );
\write_buffer.wr_buffer_ram[0].RAM32M0_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(3),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(3),
      O => \write_buffer.wr_buf_in_data\(3)
    );
\write_buffer.wr_buffer_ram[0].RAM32M0_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(2),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(2),
      O => \write_buffer.wr_buf_in_data\(2)
    );
\write_buffer.wr_buffer_ram[0].RAM32M0_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(1),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(1),
      O => \write_buffer.wr_buf_in_data\(1)
    );
\write_buffer.wr_buffer_ram[0].RAM32M0_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(0),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(0),
      O => \write_buffer.wr_buf_in_data\(0)
    );
\write_buffer.wr_buffer_ram[0].RAM32M0_i_7\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"00AC"
    )
        port map (
      I0 => wr_data_pntr(3),
      I1 => \write_data_control.wb_wr_data_addr_r\(4),
      I2 => \write_data_control.wr_data_addr_le\,
      I3 => \wr_req_counter.wr_req_cnt_r_reg[0]_1\,
      O => wb_wr_data_addr_w(4)
    );
\write_buffer.wr_buffer_ram[0].RAM32M0_i_8\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"00AC"
    )
        port map (
      I0 => wr_data_pntr(2),
      I1 => \write_data_control.wb_wr_data_addr_r\(3),
      I2 => \write_data_control.wr_data_addr_le\,
      I3 => \wr_req_counter.wr_req_cnt_r_reg[0]_1\,
      O => wb_wr_data_addr_w(3)
    );
\write_buffer.wr_buffer_ram[0].RAM32M0_i_9\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"00AC"
    )
        port map (
      I0 => wr_data_pntr(1),
      I1 => \write_data_control.wb_wr_data_addr_r\(2),
      I2 => \write_data_control.wr_data_addr_le\,
      I3 => \wr_req_counter.wr_req_cnt_r_reg[0]_1\,
      O => wb_wr_data_addr_w(2)
    );
\write_buffer.wr_buffer_ram[10].RAM32M0\: unisim.vcomponents.RAM32M
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      IS_WCLK_INVERTED => '0'
    )
        port map (
      ADDRA(4 downto 1) => wr_data_addr(3 downto 0),
      ADDRA(0) => '0',
      ADDRB(4 downto 1) => wr_data_addr(3 downto 0),
      ADDRB(0) => '0',
      ADDRC(4 downto 1) => wr_data_addr(3 downto 0),
      ADDRC(0) => '0',
      ADDRD(4 downto 1) => wb_wr_data_addr_w(4 downto 1),
      ADDRD(0) => \write_data_control.wb_wr_data_addr0_ns\,
      DIA(1 downto 0) => \write_buffer.wr_buf_in_data\(65 downto 64),
      DIB(1 downto 0) => \write_buffer.wr_buf_in_data\(63 downto 62),
      DIC(1 downto 0) => \write_buffer.wr_buf_in_data\(61 downto 60),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => wr_buf_out_data_w(65 downto 64),
      DOB(1 downto 0) => wr_buf_out_data_w(63 downto 62),
      DOC(1 downto 0) => wr_buf_out_data_w(61 downto 60),
      DOD(1 downto 0) => \NLW_write_buffer.wr_buffer_ram[10].RAM32M0_DOD_UNCONNECTED\(1 downto 0),
      WCLK => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      WE => wdf_rdy_ns
    );
\write_buffer.wr_buffer_ram[10].RAM32M0_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(65),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(65),
      O => \write_buffer.wr_buf_in_data\(65)
    );
\write_buffer.wr_buffer_ram[10].RAM32M0_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(64),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(64),
      O => \write_buffer.wr_buf_in_data\(64)
    );
\write_buffer.wr_buffer_ram[10].RAM32M0_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(63),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(63),
      O => \write_buffer.wr_buf_in_data\(63)
    );
\write_buffer.wr_buffer_ram[10].RAM32M0_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(62),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(62),
      O => \write_buffer.wr_buf_in_data\(62)
    );
\write_buffer.wr_buffer_ram[10].RAM32M0_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(61),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(61),
      O => \write_buffer.wr_buf_in_data\(61)
    );
\write_buffer.wr_buffer_ram[10].RAM32M0_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(60),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(60),
      O => \write_buffer.wr_buf_in_data\(60)
    );
\write_buffer.wr_buffer_ram[11].RAM32M0\: unisim.vcomponents.RAM32M
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      IS_WCLK_INVERTED => '0'
    )
        port map (
      ADDRA(4 downto 1) => wr_data_addr(3 downto 0),
      ADDRA(0) => '0',
      ADDRB(4 downto 1) => wr_data_addr(3 downto 0),
      ADDRB(0) => '0',
      ADDRC(4 downto 1) => wr_data_addr(3 downto 0),
      ADDRC(0) => '0',
      ADDRD(4 downto 1) => wb_wr_data_addr_w(4 downto 1),
      ADDRD(0) => \write_data_control.wb_wr_data_addr0_ns\,
      DIA(1 downto 0) => \write_buffer.wr_buf_in_data\(71 downto 70),
      DIB(1 downto 0) => \write_buffer.wr_buf_in_data\(69 downto 68),
      DIC(1 downto 0) => \write_buffer.wr_buf_in_data\(67 downto 66),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => wr_buf_out_data_w(71 downto 70),
      DOB(1 downto 0) => wr_buf_out_data_w(69 downto 68),
      DOC(1 downto 0) => wr_buf_out_data_w(67 downto 66),
      DOD(1 downto 0) => \NLW_write_buffer.wr_buffer_ram[11].RAM32M0_DOD_UNCONNECTED\(1 downto 0),
      WCLK => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      WE => wdf_rdy_ns
    );
\write_buffer.wr_buffer_ram[11].RAM32M0_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(71),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(71),
      O => \write_buffer.wr_buf_in_data\(71)
    );
\write_buffer.wr_buffer_ram[11].RAM32M0_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(70),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(70),
      O => \write_buffer.wr_buf_in_data\(70)
    );
\write_buffer.wr_buffer_ram[11].RAM32M0_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(69),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(69),
      O => \write_buffer.wr_buf_in_data\(69)
    );
\write_buffer.wr_buffer_ram[11].RAM32M0_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(68),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(68),
      O => \write_buffer.wr_buf_in_data\(68)
    );
\write_buffer.wr_buffer_ram[11].RAM32M0_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(67),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(67),
      O => \write_buffer.wr_buf_in_data\(67)
    );
\write_buffer.wr_buffer_ram[11].RAM32M0_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(66),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(66),
      O => \write_buffer.wr_buf_in_data\(66)
    );
\write_buffer.wr_buffer_ram[12].RAM32M0\: unisim.vcomponents.RAM32M
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      IS_WCLK_INVERTED => '0'
    )
        port map (
      ADDRA(4 downto 1) => wr_data_addr(3 downto 0),
      ADDRA(0) => '0',
      ADDRB(4 downto 1) => wr_data_addr(3 downto 0),
      ADDRB(0) => '0',
      ADDRC(4 downto 1) => wr_data_addr(3 downto 0),
      ADDRC(0) => '0',
      ADDRD(4 downto 1) => wb_wr_data_addr_w(4 downto 1),
      ADDRD(0) => \write_data_control.wb_wr_data_addr0_ns\,
      DIA(1 downto 0) => \write_buffer.wr_buf_in_data\(77 downto 76),
      DIB(1 downto 0) => \write_buffer.wr_buf_in_data\(75 downto 74),
      DIC(1 downto 0) => \write_buffer.wr_buf_in_data\(73 downto 72),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => wr_buf_out_data_w(77 downto 76),
      DOB(1 downto 0) => wr_buf_out_data_w(75 downto 74),
      DOC(1 downto 0) => wr_buf_out_data_w(73 downto 72),
      DOD(1 downto 0) => \NLW_write_buffer.wr_buffer_ram[12].RAM32M0_DOD_UNCONNECTED\(1 downto 0),
      WCLK => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      WE => wdf_rdy_ns
    );
\write_buffer.wr_buffer_ram[12].RAM32M0_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(77),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(77),
      O => \write_buffer.wr_buf_in_data\(77)
    );
\write_buffer.wr_buffer_ram[12].RAM32M0_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(76),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(76),
      O => \write_buffer.wr_buf_in_data\(76)
    );
\write_buffer.wr_buffer_ram[12].RAM32M0_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(75),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(75),
      O => \write_buffer.wr_buf_in_data\(75)
    );
\write_buffer.wr_buffer_ram[12].RAM32M0_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(74),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(74),
      O => \write_buffer.wr_buf_in_data\(74)
    );
\write_buffer.wr_buffer_ram[12].RAM32M0_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(73),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(73),
      O => \write_buffer.wr_buf_in_data\(73)
    );
\write_buffer.wr_buffer_ram[12].RAM32M0_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(72),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(72),
      O => \write_buffer.wr_buf_in_data\(72)
    );
\write_buffer.wr_buffer_ram[13].RAM32M0\: unisim.vcomponents.RAM32M
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      IS_WCLK_INVERTED => '0'
    )
        port map (
      ADDRA(4 downto 1) => wr_data_addr(3 downto 0),
      ADDRA(0) => '0',
      ADDRB(4 downto 1) => wr_data_addr(3 downto 0),
      ADDRB(0) => '0',
      ADDRC(4 downto 1) => wr_data_addr(3 downto 0),
      ADDRC(0) => '0',
      ADDRD(4 downto 1) => wb_wr_data_addr_w(4 downto 1),
      ADDRD(0) => \write_data_control.wb_wr_data_addr0_ns\,
      DIA(1 downto 0) => \write_buffer.wr_buf_in_data\(83 downto 82),
      DIB(1 downto 0) => \write_buffer.wr_buf_in_data\(81 downto 80),
      DIC(1 downto 0) => \write_buffer.wr_buf_in_data\(79 downto 78),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => wr_buf_out_data_w(83 downto 82),
      DOB(1 downto 0) => wr_buf_out_data_w(81 downto 80),
      DOC(1 downto 0) => wr_buf_out_data_w(79 downto 78),
      DOD(1 downto 0) => \NLW_write_buffer.wr_buffer_ram[13].RAM32M0_DOD_UNCONNECTED\(1 downto 0),
      WCLK => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      WE => wdf_rdy_ns
    );
\write_buffer.wr_buffer_ram[13].RAM32M0_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(83),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(83),
      O => \write_buffer.wr_buf_in_data\(83)
    );
\write_buffer.wr_buffer_ram[13].RAM32M0_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(82),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(82),
      O => \write_buffer.wr_buf_in_data\(82)
    );
\write_buffer.wr_buffer_ram[13].RAM32M0_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(81),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(81),
      O => \write_buffer.wr_buf_in_data\(81)
    );
\write_buffer.wr_buffer_ram[13].RAM32M0_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(80),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(80),
      O => \write_buffer.wr_buf_in_data\(80)
    );
\write_buffer.wr_buffer_ram[13].RAM32M0_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(79),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(79),
      O => \write_buffer.wr_buf_in_data\(79)
    );
\write_buffer.wr_buffer_ram[13].RAM32M0_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(78),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(78),
      O => \write_buffer.wr_buf_in_data\(78)
    );
\write_buffer.wr_buffer_ram[14].RAM32M0\: unisim.vcomponents.RAM32M
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      IS_WCLK_INVERTED => '0'
    )
        port map (
      ADDRA(4 downto 1) => wr_data_addr(3 downto 0),
      ADDRA(0) => '0',
      ADDRB(4 downto 1) => wr_data_addr(3 downto 0),
      ADDRB(0) => '0',
      ADDRC(4 downto 1) => wr_data_addr(3 downto 0),
      ADDRC(0) => '0',
      ADDRD(4 downto 1) => wb_wr_data_addr_w(4 downto 1),
      ADDRD(0) => \write_data_control.wb_wr_data_addr0_ns\,
      DIA(1 downto 0) => \write_buffer.wr_buf_in_data\(89 downto 88),
      DIB(1 downto 0) => \write_buffer.wr_buf_in_data\(87 downto 86),
      DIC(1 downto 0) => \write_buffer.wr_buf_in_data\(85 downto 84),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => wr_buf_out_data_w(89 downto 88),
      DOB(1 downto 0) => wr_buf_out_data_w(87 downto 86),
      DOC(1 downto 0) => wr_buf_out_data_w(85 downto 84),
      DOD(1 downto 0) => \NLW_write_buffer.wr_buffer_ram[14].RAM32M0_DOD_UNCONNECTED\(1 downto 0),
      WCLK => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      WE => wdf_rdy_ns
    );
\write_buffer.wr_buffer_ram[14].RAM32M0_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(89),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(89),
      O => \write_buffer.wr_buf_in_data\(89)
    );
\write_buffer.wr_buffer_ram[14].RAM32M0_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(88),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(88),
      O => \write_buffer.wr_buf_in_data\(88)
    );
\write_buffer.wr_buffer_ram[14].RAM32M0_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(87),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(87),
      O => \write_buffer.wr_buf_in_data\(87)
    );
\write_buffer.wr_buffer_ram[14].RAM32M0_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(86),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(86),
      O => \write_buffer.wr_buf_in_data\(86)
    );
\write_buffer.wr_buffer_ram[14].RAM32M0_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(85),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(85),
      O => \write_buffer.wr_buf_in_data\(85)
    );
\write_buffer.wr_buffer_ram[14].RAM32M0_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(84),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(84),
      O => \write_buffer.wr_buf_in_data\(84)
    );
\write_buffer.wr_buffer_ram[15].RAM32M0\: unisim.vcomponents.RAM32M
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      IS_WCLK_INVERTED => '0'
    )
        port map (
      ADDRA(4 downto 1) => wr_data_addr(3 downto 0),
      ADDRA(0) => '0',
      ADDRB(4 downto 1) => wr_data_addr(3 downto 0),
      ADDRB(0) => '0',
      ADDRC(4 downto 1) => wr_data_addr(3 downto 0),
      ADDRC(0) => '0',
      ADDRD(4 downto 1) => wb_wr_data_addr_w(4 downto 1),
      ADDRD(0) => \write_data_control.wb_wr_data_addr0_ns\,
      DIA(1 downto 0) => \write_buffer.wr_buf_in_data\(95 downto 94),
      DIB(1 downto 0) => \write_buffer.wr_buf_in_data\(93 downto 92),
      DIC(1 downto 0) => \write_buffer.wr_buf_in_data\(91 downto 90),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => wr_buf_out_data_w(95 downto 94),
      DOB(1 downto 0) => wr_buf_out_data_w(93 downto 92),
      DOC(1 downto 0) => wr_buf_out_data_w(91 downto 90),
      DOD(1 downto 0) => \NLW_write_buffer.wr_buffer_ram[15].RAM32M0_DOD_UNCONNECTED\(1 downto 0),
      WCLK => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      WE => wdf_rdy_ns
    );
\write_buffer.wr_buffer_ram[15].RAM32M0_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(95),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(95),
      O => \write_buffer.wr_buf_in_data\(95)
    );
\write_buffer.wr_buffer_ram[15].RAM32M0_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(94),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(94),
      O => \write_buffer.wr_buf_in_data\(94)
    );
\write_buffer.wr_buffer_ram[15].RAM32M0_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(93),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(93),
      O => \write_buffer.wr_buf_in_data\(93)
    );
\write_buffer.wr_buffer_ram[15].RAM32M0_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(92),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(92),
      O => \write_buffer.wr_buf_in_data\(92)
    );
\write_buffer.wr_buffer_ram[15].RAM32M0_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(91),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(91),
      O => \write_buffer.wr_buf_in_data\(91)
    );
\write_buffer.wr_buffer_ram[15].RAM32M0_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(90),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(90),
      O => \write_buffer.wr_buf_in_data\(90)
    );
\write_buffer.wr_buffer_ram[16].RAM32M0\: unisim.vcomponents.RAM32M
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      IS_WCLK_INVERTED => '0'
    )
        port map (
      ADDRA(4 downto 1) => wr_data_addr(3 downto 0),
      ADDRA(0) => '0',
      ADDRB(4 downto 1) => wr_data_addr(3 downto 0),
      ADDRB(0) => '0',
      ADDRC(4 downto 1) => wr_data_addr(3 downto 0),
      ADDRC(0) => '0',
      ADDRD(4 downto 1) => wb_wr_data_addr_w(4 downto 1),
      ADDRD(0) => \write_data_control.wb_wr_data_addr0_ns\,
      DIA(1 downto 0) => \write_buffer.wr_buf_in_data\(101 downto 100),
      DIB(1 downto 0) => \write_buffer.wr_buf_in_data\(99 downto 98),
      DIC(1 downto 0) => \write_buffer.wr_buf_in_data\(97 downto 96),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => wr_buf_out_data_w(101 downto 100),
      DOB(1 downto 0) => wr_buf_out_data_w(99 downto 98),
      DOC(1 downto 0) => wr_buf_out_data_w(97 downto 96),
      DOD(1 downto 0) => \NLW_write_buffer.wr_buffer_ram[16].RAM32M0_DOD_UNCONNECTED\(1 downto 0),
      WCLK => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      WE => wdf_rdy_ns
    );
\write_buffer.wr_buffer_ram[16].RAM32M0_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(101),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(101),
      O => \write_buffer.wr_buf_in_data\(101)
    );
\write_buffer.wr_buffer_ram[16].RAM32M0_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(100),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(100),
      O => \write_buffer.wr_buf_in_data\(100)
    );
\write_buffer.wr_buffer_ram[16].RAM32M0_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(99),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(99),
      O => \write_buffer.wr_buf_in_data\(99)
    );
\write_buffer.wr_buffer_ram[16].RAM32M0_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(98),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(98),
      O => \write_buffer.wr_buf_in_data\(98)
    );
\write_buffer.wr_buffer_ram[16].RAM32M0_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(97),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(97),
      O => \write_buffer.wr_buf_in_data\(97)
    );
\write_buffer.wr_buffer_ram[16].RAM32M0_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(96),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(96),
      O => \write_buffer.wr_buf_in_data\(96)
    );
\write_buffer.wr_buffer_ram[17].RAM32M0\: unisim.vcomponents.RAM32M
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      IS_WCLK_INVERTED => '0'
    )
        port map (
      ADDRA(4 downto 1) => wr_data_addr(3 downto 0),
      ADDRA(0) => '0',
      ADDRB(4 downto 1) => wr_data_addr(3 downto 0),
      ADDRB(0) => '0',
      ADDRC(4 downto 1) => wr_data_addr(3 downto 0),
      ADDRC(0) => '0',
      ADDRD(4 downto 1) => wb_wr_data_addr_w(4 downto 1),
      ADDRD(0) => \write_data_control.wb_wr_data_addr0_ns\,
      DIA(1 downto 0) => \write_buffer.wr_buf_in_data\(107 downto 106),
      DIB(1 downto 0) => \write_buffer.wr_buf_in_data\(105 downto 104),
      DIC(1 downto 0) => \write_buffer.wr_buf_in_data\(103 downto 102),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => wr_buf_out_data_w(107 downto 106),
      DOB(1 downto 0) => wr_buf_out_data_w(105 downto 104),
      DOC(1 downto 0) => wr_buf_out_data_w(103 downto 102),
      DOD(1 downto 0) => \NLW_write_buffer.wr_buffer_ram[17].RAM32M0_DOD_UNCONNECTED\(1 downto 0),
      WCLK => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      WE => wdf_rdy_ns
    );
\write_buffer.wr_buffer_ram[17].RAM32M0_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(107),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(107),
      O => \write_buffer.wr_buf_in_data\(107)
    );
\write_buffer.wr_buffer_ram[17].RAM32M0_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(106),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(106),
      O => \write_buffer.wr_buf_in_data\(106)
    );
\write_buffer.wr_buffer_ram[17].RAM32M0_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(105),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(105),
      O => \write_buffer.wr_buf_in_data\(105)
    );
\write_buffer.wr_buffer_ram[17].RAM32M0_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(104),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(104),
      O => \write_buffer.wr_buf_in_data\(104)
    );
\write_buffer.wr_buffer_ram[17].RAM32M0_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(103),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(103),
      O => \write_buffer.wr_buf_in_data\(103)
    );
\write_buffer.wr_buffer_ram[17].RAM32M0_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(102),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(102),
      O => \write_buffer.wr_buf_in_data\(102)
    );
\write_buffer.wr_buffer_ram[18].RAM32M0\: unisim.vcomponents.RAM32M
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      IS_WCLK_INVERTED => '0'
    )
        port map (
      ADDRA(4 downto 1) => wr_data_addr(3 downto 0),
      ADDRA(0) => '0',
      ADDRB(4 downto 1) => wr_data_addr(3 downto 0),
      ADDRB(0) => '0',
      ADDRC(4 downto 1) => wr_data_addr(3 downto 0),
      ADDRC(0) => '0',
      ADDRD(4 downto 1) => wb_wr_data_addr_w(4 downto 1),
      ADDRD(0) => \write_data_control.wb_wr_data_addr0_ns\,
      DIA(1 downto 0) => \write_buffer.wr_buf_in_data\(113 downto 112),
      DIB(1 downto 0) => \write_buffer.wr_buf_in_data\(111 downto 110),
      DIC(1 downto 0) => \write_buffer.wr_buf_in_data\(109 downto 108),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => wr_buf_out_data_w(113 downto 112),
      DOB(1 downto 0) => wr_buf_out_data_w(111 downto 110),
      DOC(1 downto 0) => wr_buf_out_data_w(109 downto 108),
      DOD(1 downto 0) => \NLW_write_buffer.wr_buffer_ram[18].RAM32M0_DOD_UNCONNECTED\(1 downto 0),
      WCLK => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      WE => wdf_rdy_ns
    );
\write_buffer.wr_buffer_ram[18].RAM32M0_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(113),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(113),
      O => \write_buffer.wr_buf_in_data\(113)
    );
\write_buffer.wr_buffer_ram[18].RAM32M0_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(112),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(112),
      O => \write_buffer.wr_buf_in_data\(112)
    );
\write_buffer.wr_buffer_ram[18].RAM32M0_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(111),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(111),
      O => \write_buffer.wr_buf_in_data\(111)
    );
\write_buffer.wr_buffer_ram[18].RAM32M0_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(110),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(110),
      O => \write_buffer.wr_buf_in_data\(110)
    );
\write_buffer.wr_buffer_ram[18].RAM32M0_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(109),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(109),
      O => \write_buffer.wr_buf_in_data\(109)
    );
\write_buffer.wr_buffer_ram[18].RAM32M0_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(108),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(108),
      O => \write_buffer.wr_buf_in_data\(108)
    );
\write_buffer.wr_buffer_ram[19].RAM32M0\: unisim.vcomponents.RAM32M
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      IS_WCLK_INVERTED => '0'
    )
        port map (
      ADDRA(4 downto 1) => wr_data_addr(3 downto 0),
      ADDRA(0) => '0',
      ADDRB(4 downto 1) => wr_data_addr(3 downto 0),
      ADDRB(0) => '0',
      ADDRC(4 downto 1) => wr_data_addr(3 downto 0),
      ADDRC(0) => '0',
      ADDRD(4 downto 1) => wb_wr_data_addr_w(4 downto 1),
      ADDRD(0) => \write_data_control.wb_wr_data_addr0_ns\,
      DIA(1 downto 0) => \write_buffer.wr_buf_in_data\(119 downto 118),
      DIB(1 downto 0) => \write_buffer.wr_buf_in_data\(117 downto 116),
      DIC(1 downto 0) => \write_buffer.wr_buf_in_data\(115 downto 114),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => wr_buf_out_data_w(119 downto 118),
      DOB(1 downto 0) => wr_buf_out_data_w(117 downto 116),
      DOC(1 downto 0) => wr_buf_out_data_w(115 downto 114),
      DOD(1 downto 0) => \NLW_write_buffer.wr_buffer_ram[19].RAM32M0_DOD_UNCONNECTED\(1 downto 0),
      WCLK => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      WE => wdf_rdy_ns
    );
\write_buffer.wr_buffer_ram[19].RAM32M0_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(119),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(119),
      O => \write_buffer.wr_buf_in_data\(119)
    );
\write_buffer.wr_buffer_ram[19].RAM32M0_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(118),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(118),
      O => \write_buffer.wr_buf_in_data\(118)
    );
\write_buffer.wr_buffer_ram[19].RAM32M0_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(117),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(117),
      O => \write_buffer.wr_buf_in_data\(117)
    );
\write_buffer.wr_buffer_ram[19].RAM32M0_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(116),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(116),
      O => \write_buffer.wr_buf_in_data\(116)
    );
\write_buffer.wr_buffer_ram[19].RAM32M0_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(115),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(115),
      O => \write_buffer.wr_buf_in_data\(115)
    );
\write_buffer.wr_buffer_ram[19].RAM32M0_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(114),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(114),
      O => \write_buffer.wr_buf_in_data\(114)
    );
\write_buffer.wr_buffer_ram[1].RAM32M0\: unisim.vcomponents.RAM32M
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      IS_WCLK_INVERTED => '0'
    )
        port map (
      ADDRA(4 downto 1) => wr_data_addr(3 downto 0),
      ADDRA(0) => '0',
      ADDRB(4 downto 1) => wr_data_addr(3 downto 0),
      ADDRB(0) => '0',
      ADDRC(4 downto 1) => wr_data_addr(3 downto 0),
      ADDRC(0) => '0',
      ADDRD(4 downto 1) => wb_wr_data_addr_w(4 downto 1),
      ADDRD(0) => \write_data_control.wb_wr_data_addr0_ns\,
      DIA(1 downto 0) => \write_buffer.wr_buf_in_data\(11 downto 10),
      DIB(1 downto 0) => \write_buffer.wr_buf_in_data\(9 downto 8),
      DIC(1 downto 0) => \write_buffer.wr_buf_in_data\(7 downto 6),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => wr_buf_out_data_w(11 downto 10),
      DOB(1 downto 0) => wr_buf_out_data_w(9 downto 8),
      DOC(1 downto 0) => wr_buf_out_data_w(7 downto 6),
      DOD(1 downto 0) => \NLW_write_buffer.wr_buffer_ram[1].RAM32M0_DOD_UNCONNECTED\(1 downto 0),
      WCLK => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      WE => wdf_rdy_ns
    );
\write_buffer.wr_buffer_ram[1].RAM32M0_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(11),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(11),
      O => \write_buffer.wr_buf_in_data\(11)
    );
\write_buffer.wr_buffer_ram[1].RAM32M0_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(10),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(10),
      O => \write_buffer.wr_buf_in_data\(10)
    );
\write_buffer.wr_buffer_ram[1].RAM32M0_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(9),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(9),
      O => \write_buffer.wr_buf_in_data\(9)
    );
\write_buffer.wr_buffer_ram[1].RAM32M0_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(8),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(8),
      O => \write_buffer.wr_buf_in_data\(8)
    );
\write_buffer.wr_buffer_ram[1].RAM32M0_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(7),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(7),
      O => \write_buffer.wr_buf_in_data\(7)
    );
\write_buffer.wr_buffer_ram[1].RAM32M0_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(6),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(6),
      O => \write_buffer.wr_buf_in_data\(6)
    );
\write_buffer.wr_buffer_ram[20].RAM32M0\: unisim.vcomponents.RAM32M
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      IS_WCLK_INVERTED => '0'
    )
        port map (
      ADDRA(4 downto 1) => wr_data_addr(3 downto 0),
      ADDRA(0) => '0',
      ADDRB(4 downto 1) => wr_data_addr(3 downto 0),
      ADDRB(0) => '0',
      ADDRC(4 downto 1) => wr_data_addr(3 downto 0),
      ADDRC(0) => '0',
      ADDRD(4 downto 1) => wb_wr_data_addr_w(4 downto 1),
      ADDRD(0) => \write_data_control.wb_wr_data_addr0_ns\,
      DIA(1 downto 0) => \write_buffer.wr_buf_in_data\(125 downto 124),
      DIB(1 downto 0) => \write_buffer.wr_buf_in_data\(123 downto 122),
      DIC(1 downto 0) => \write_buffer.wr_buf_in_data\(121 downto 120),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => wr_buf_out_data_w(125 downto 124),
      DOB(1 downto 0) => wr_buf_out_data_w(123 downto 122),
      DOC(1 downto 0) => wr_buf_out_data_w(121 downto 120),
      DOD(1 downto 0) => \NLW_write_buffer.wr_buffer_ram[20].RAM32M0_DOD_UNCONNECTED\(1 downto 0),
      WCLK => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      WE => wdf_rdy_ns
    );
\write_buffer.wr_buffer_ram[20].RAM32M0_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(125),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(125),
      O => \write_buffer.wr_buf_in_data\(125)
    );
\write_buffer.wr_buffer_ram[20].RAM32M0_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(124),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(124),
      O => \write_buffer.wr_buf_in_data\(124)
    );
\write_buffer.wr_buffer_ram[20].RAM32M0_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(123),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(123),
      O => \write_buffer.wr_buf_in_data\(123)
    );
\write_buffer.wr_buffer_ram[20].RAM32M0_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(122),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(122),
      O => \write_buffer.wr_buf_in_data\(122)
    );
\write_buffer.wr_buffer_ram[20].RAM32M0_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(121),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(121),
      O => \write_buffer.wr_buf_in_data\(121)
    );
\write_buffer.wr_buffer_ram[20].RAM32M0_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(120),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(120),
      O => \write_buffer.wr_buf_in_data\(120)
    );
\write_buffer.wr_buffer_ram[21].RAM32M0\: unisim.vcomponents.RAM32M
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      IS_WCLK_INVERTED => '0'
    )
        port map (
      ADDRA(4 downto 1) => wr_data_addr(3 downto 0),
      ADDRA(0) => '0',
      ADDRB(4 downto 1) => wr_data_addr(3 downto 0),
      ADDRB(0) => '0',
      ADDRC(4 downto 1) => wr_data_addr(3 downto 0),
      ADDRC(0) => '0',
      ADDRD(4 downto 1) => wb_wr_data_addr_w(4 downto 1),
      ADDRD(0) => \write_data_control.wb_wr_data_addr0_ns\,
      DIA(1 downto 0) => \write_buffer.wr_buf_in_data\(131 downto 130),
      DIB(1 downto 0) => \write_buffer.wr_buf_in_data\(129 downto 128),
      DIC(1 downto 0) => \write_buffer.wr_buf_in_data\(127 downto 126),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => wr_buf_out_data_w(131 downto 130),
      DOB(1 downto 0) => wr_buf_out_data_w(129 downto 128),
      DOC(1 downto 0) => wr_buf_out_data_w(127 downto 126),
      DOD(1 downto 0) => \NLW_write_buffer.wr_buffer_ram[21].RAM32M0_DOD_UNCONNECTED\(1 downto 0),
      WCLK => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      WE => wdf_rdy_ns
    );
\write_buffer.wr_buffer_ram[21].RAM32M0_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(131),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(131),
      O => \write_buffer.wr_buf_in_data\(131)
    );
\write_buffer.wr_buffer_ram[21].RAM32M0_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(130),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(130),
      O => \write_buffer.wr_buf_in_data\(130)
    );
\write_buffer.wr_buffer_ram[21].RAM32M0_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(129),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(129),
      O => \write_buffer.wr_buf_in_data\(129)
    );
\write_buffer.wr_buffer_ram[21].RAM32M0_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(128),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(128),
      O => \write_buffer.wr_buf_in_data\(128)
    );
\write_buffer.wr_buffer_ram[21].RAM32M0_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(127),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(127),
      O => \write_buffer.wr_buf_in_data\(127)
    );
\write_buffer.wr_buffer_ram[21].RAM32M0_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(126),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(126),
      O => \write_buffer.wr_buf_in_data\(126)
    );
\write_buffer.wr_buffer_ram[22].RAM32M0\: unisim.vcomponents.RAM32M
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      IS_WCLK_INVERTED => '0'
    )
        port map (
      ADDRA(4 downto 1) => wr_data_addr(3 downto 0),
      ADDRA(0) => '0',
      ADDRB(4 downto 1) => wr_data_addr(3 downto 0),
      ADDRB(0) => '0',
      ADDRC(4 downto 1) => wr_data_addr(3 downto 0),
      ADDRC(0) => '0',
      ADDRD(4 downto 1) => wb_wr_data_addr_w(4 downto 1),
      ADDRD(0) => \write_data_control.wb_wr_data_addr0_ns\,
      DIA(1 downto 0) => \write_buffer.wr_buf_in_data\(137 downto 136),
      DIB(1 downto 0) => \write_buffer.wr_buf_in_data\(135 downto 134),
      DIC(1 downto 0) => \write_buffer.wr_buf_in_data\(133 downto 132),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => wr_buf_out_data_w(137 downto 136),
      DOB(1 downto 0) => wr_buf_out_data_w(135 downto 134),
      DOC(1 downto 0) => wr_buf_out_data_w(133 downto 132),
      DOD(1 downto 0) => \NLW_write_buffer.wr_buffer_ram[22].RAM32M0_DOD_UNCONNECTED\(1 downto 0),
      WCLK => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      WE => wdf_rdy_ns
    );
\write_buffer.wr_buffer_ram[22].RAM32M0_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(137),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(137),
      O => \write_buffer.wr_buf_in_data\(137)
    );
\write_buffer.wr_buffer_ram[22].RAM32M0_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(136),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(136),
      O => \write_buffer.wr_buf_in_data\(136)
    );
\write_buffer.wr_buffer_ram[22].RAM32M0_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(135),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(135),
      O => \write_buffer.wr_buf_in_data\(135)
    );
\write_buffer.wr_buffer_ram[22].RAM32M0_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(134),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(134),
      O => \write_buffer.wr_buf_in_data\(134)
    );
\write_buffer.wr_buffer_ram[22].RAM32M0_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(133),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(133),
      O => \write_buffer.wr_buf_in_data\(133)
    );
\write_buffer.wr_buffer_ram[22].RAM32M0_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(132),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(132),
      O => \write_buffer.wr_buf_in_data\(132)
    );
\write_buffer.wr_buffer_ram[23].RAM32M0\: unisim.vcomponents.RAM32M
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      IS_WCLK_INVERTED => '0'
    )
        port map (
      ADDRA(4 downto 1) => wr_data_addr(3 downto 0),
      ADDRA(0) => '0',
      ADDRB(4 downto 1) => wr_data_addr(3 downto 0),
      ADDRB(0) => '0',
      ADDRC(4 downto 1) => wr_data_addr(3 downto 0),
      ADDRC(0) => '0',
      ADDRD(4 downto 1) => wb_wr_data_addr_w(4 downto 1),
      ADDRD(0) => \write_data_control.wb_wr_data_addr0_ns\,
      DIA(1 downto 0) => \write_buffer.wr_buf_in_data\(143 downto 142),
      DIB(1 downto 0) => \write_buffer.wr_buf_in_data\(141 downto 140),
      DIC(1 downto 0) => \write_buffer.wr_buf_in_data\(139 downto 138),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => wr_buf_out_data_w(143 downto 142),
      DOB(1 downto 0) => wr_buf_out_data_w(141 downto 140),
      DOC(1 downto 0) => wr_buf_out_data_w(139 downto 138),
      DOD(1 downto 0) => \NLW_write_buffer.wr_buffer_ram[23].RAM32M0_DOD_UNCONNECTED\(1 downto 0),
      WCLK => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      WE => wdf_rdy_ns
    );
\write_buffer.wr_buffer_ram[23].RAM32M0_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(143),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(143),
      O => \write_buffer.wr_buf_in_data\(143)
    );
\write_buffer.wr_buffer_ram[23].RAM32M0_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(142),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(142),
      O => \write_buffer.wr_buf_in_data\(142)
    );
\write_buffer.wr_buffer_ram[23].RAM32M0_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(141),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(141),
      O => \write_buffer.wr_buf_in_data\(141)
    );
\write_buffer.wr_buffer_ram[23].RAM32M0_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(140),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(140),
      O => \write_buffer.wr_buf_in_data\(140)
    );
\write_buffer.wr_buffer_ram[23].RAM32M0_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(139),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(139),
      O => \write_buffer.wr_buf_in_data\(139)
    );
\write_buffer.wr_buffer_ram[23].RAM32M0_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(138),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(138),
      O => \write_buffer.wr_buf_in_data\(138)
    );
\write_buffer.wr_buffer_ram[24].RAM32M0\: unisim.vcomponents.RAM32M
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      IS_WCLK_INVERTED => '0'
    )
        port map (
      ADDRA(4 downto 1) => wr_data_addr(3 downto 0),
      ADDRA(0) => '0',
      ADDRB(4 downto 1) => wr_data_addr(3 downto 0),
      ADDRB(0) => '0',
      ADDRC(4 downto 1) => wr_data_addr(3 downto 0),
      ADDRC(0) => '0',
      ADDRD(4 downto 1) => wb_wr_data_addr_w(4 downto 1),
      ADDRD(0) => \write_data_control.wb_wr_data_addr0_ns\,
      DIA(1 downto 0) => \write_buffer.wr_buf_in_data\(149 downto 148),
      DIB(1 downto 0) => \write_buffer.wr_buf_in_data\(147 downto 146),
      DIC(1 downto 0) => \write_buffer.wr_buf_in_data\(145 downto 144),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => wr_buf_out_data_w(149 downto 148),
      DOB(1 downto 0) => wr_buf_out_data_w(147 downto 146),
      DOC(1 downto 0) => wr_buf_out_data_w(145 downto 144),
      DOD(1 downto 0) => \NLW_write_buffer.wr_buffer_ram[24].RAM32M0_DOD_UNCONNECTED\(1 downto 0),
      WCLK => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      WE => wdf_rdy_ns
    );
\write_buffer.wr_buffer_ram[24].RAM32M0_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(149),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(149),
      O => \write_buffer.wr_buf_in_data\(149)
    );
\write_buffer.wr_buffer_ram[24].RAM32M0_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(148),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(148),
      O => \write_buffer.wr_buf_in_data\(148)
    );
\write_buffer.wr_buffer_ram[24].RAM32M0_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(147),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(147),
      O => \write_buffer.wr_buf_in_data\(147)
    );
\write_buffer.wr_buffer_ram[24].RAM32M0_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(146),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(146),
      O => \write_buffer.wr_buf_in_data\(146)
    );
\write_buffer.wr_buffer_ram[24].RAM32M0_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(145),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(145),
      O => \write_buffer.wr_buf_in_data\(145)
    );
\write_buffer.wr_buffer_ram[24].RAM32M0_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(144),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(144),
      O => \write_buffer.wr_buf_in_data\(144)
    );
\write_buffer.wr_buffer_ram[25].RAM32M0\: unisim.vcomponents.RAM32M
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      IS_WCLK_INVERTED => '0'
    )
        port map (
      ADDRA(4 downto 1) => wr_data_addr(3 downto 0),
      ADDRA(0) => '0',
      ADDRB(4 downto 1) => wr_data_addr(3 downto 0),
      ADDRB(0) => '0',
      ADDRC(4 downto 1) => wr_data_addr(3 downto 0),
      ADDRC(0) => '0',
      ADDRD(4 downto 1) => wb_wr_data_addr_w(4 downto 1),
      ADDRD(0) => \write_data_control.wb_wr_data_addr0_ns\,
      DIA(1 downto 0) => \write_buffer.wr_buf_in_data\(155 downto 154),
      DIB(1 downto 0) => \write_buffer.wr_buf_in_data\(153 downto 152),
      DIC(1 downto 0) => \write_buffer.wr_buf_in_data\(151 downto 150),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => wr_buf_out_data_w(155 downto 154),
      DOB(1 downto 0) => wr_buf_out_data_w(153 downto 152),
      DOC(1 downto 0) => wr_buf_out_data_w(151 downto 150),
      DOD(1 downto 0) => \NLW_write_buffer.wr_buffer_ram[25].RAM32M0_DOD_UNCONNECTED\(1 downto 0),
      WCLK => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      WE => wdf_rdy_ns
    );
\write_buffer.wr_buffer_ram[25].RAM32M0_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(155),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(155),
      O => \write_buffer.wr_buf_in_data\(155)
    );
\write_buffer.wr_buffer_ram[25].RAM32M0_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(154),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(154),
      O => \write_buffer.wr_buf_in_data\(154)
    );
\write_buffer.wr_buffer_ram[25].RAM32M0_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(153),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(153),
      O => \write_buffer.wr_buf_in_data\(153)
    );
\write_buffer.wr_buffer_ram[25].RAM32M0_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(152),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(152),
      O => \write_buffer.wr_buf_in_data\(152)
    );
\write_buffer.wr_buffer_ram[25].RAM32M0_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(151),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(151),
      O => \write_buffer.wr_buf_in_data\(151)
    );
\write_buffer.wr_buffer_ram[25].RAM32M0_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(150),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(150),
      O => \write_buffer.wr_buf_in_data\(150)
    );
\write_buffer.wr_buffer_ram[26].RAM32M0\: unisim.vcomponents.RAM32M
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      IS_WCLK_INVERTED => '0'
    )
        port map (
      ADDRA(4 downto 1) => wr_data_addr(3 downto 0),
      ADDRA(0) => '0',
      ADDRB(4 downto 1) => wr_data_addr(3 downto 0),
      ADDRB(0) => '0',
      ADDRC(4 downto 1) => wr_data_addr(3 downto 0),
      ADDRC(0) => '0',
      ADDRD(4 downto 1) => wb_wr_data_addr_w(4 downto 1),
      ADDRD(0) => \write_data_control.wb_wr_data_addr0_ns\,
      DIA(1 downto 0) => \write_buffer.wr_buf_in_data\(161 downto 160),
      DIB(1 downto 0) => \write_buffer.wr_buf_in_data\(159 downto 158),
      DIC(1 downto 0) => \write_buffer.wr_buf_in_data\(157 downto 156),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => wr_buf_out_data_w(161 downto 160),
      DOB(1 downto 0) => wr_buf_out_data_w(159 downto 158),
      DOC(1 downto 0) => wr_buf_out_data_w(157 downto 156),
      DOD(1 downto 0) => \NLW_write_buffer.wr_buffer_ram[26].RAM32M0_DOD_UNCONNECTED\(1 downto 0),
      WCLK => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      WE => wdf_rdy_ns
    );
\write_buffer.wr_buffer_ram[26].RAM32M0_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(161),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(161),
      O => \write_buffer.wr_buf_in_data\(161)
    );
\write_buffer.wr_buffer_ram[26].RAM32M0_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(160),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(160),
      O => \write_buffer.wr_buf_in_data\(160)
    );
\write_buffer.wr_buffer_ram[26].RAM32M0_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(159),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(159),
      O => \write_buffer.wr_buf_in_data\(159)
    );
\write_buffer.wr_buffer_ram[26].RAM32M0_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(158),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(158),
      O => \write_buffer.wr_buf_in_data\(158)
    );
\write_buffer.wr_buffer_ram[26].RAM32M0_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(157),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(157),
      O => \write_buffer.wr_buf_in_data\(157)
    );
\write_buffer.wr_buffer_ram[26].RAM32M0_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(156),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(156),
      O => \write_buffer.wr_buf_in_data\(156)
    );
\write_buffer.wr_buffer_ram[27].RAM32M0\: unisim.vcomponents.RAM32M
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      IS_WCLK_INVERTED => '0'
    )
        port map (
      ADDRA(4 downto 1) => wr_data_addr(3 downto 0),
      ADDRA(0) => '0',
      ADDRB(4 downto 1) => wr_data_addr(3 downto 0),
      ADDRB(0) => '0',
      ADDRC(4 downto 1) => wr_data_addr(3 downto 0),
      ADDRC(0) => '0',
      ADDRD(4 downto 1) => wb_wr_data_addr_w(4 downto 1),
      ADDRD(0) => \write_data_control.wb_wr_data_addr0_ns\,
      DIA(1 downto 0) => \write_buffer.wr_buf_in_data\(167 downto 166),
      DIB(1 downto 0) => \write_buffer.wr_buf_in_data\(165 downto 164),
      DIC(1 downto 0) => \write_buffer.wr_buf_in_data\(163 downto 162),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => wr_buf_out_data_w(167 downto 166),
      DOB(1 downto 0) => wr_buf_out_data_w(165 downto 164),
      DOC(1 downto 0) => wr_buf_out_data_w(163 downto 162),
      DOD(1 downto 0) => \NLW_write_buffer.wr_buffer_ram[27].RAM32M0_DOD_UNCONNECTED\(1 downto 0),
      WCLK => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      WE => wdf_rdy_ns
    );
\write_buffer.wr_buffer_ram[27].RAM32M0_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(167),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(167),
      O => \write_buffer.wr_buf_in_data\(167)
    );
\write_buffer.wr_buffer_ram[27].RAM32M0_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(166),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(166),
      O => \write_buffer.wr_buf_in_data\(166)
    );
\write_buffer.wr_buffer_ram[27].RAM32M0_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(165),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(165),
      O => \write_buffer.wr_buf_in_data\(165)
    );
\write_buffer.wr_buffer_ram[27].RAM32M0_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(164),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(164),
      O => \write_buffer.wr_buf_in_data\(164)
    );
\write_buffer.wr_buffer_ram[27].RAM32M0_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(163),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(163),
      O => \write_buffer.wr_buf_in_data\(163)
    );
\write_buffer.wr_buffer_ram[27].RAM32M0_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(162),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(162),
      O => \write_buffer.wr_buf_in_data\(162)
    );
\write_buffer.wr_buffer_ram[28].RAM32M0\: unisim.vcomponents.RAM32M
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      IS_WCLK_INVERTED => '0'
    )
        port map (
      ADDRA(4 downto 1) => wr_data_addr(3 downto 0),
      ADDRA(0) => '0',
      ADDRB(4 downto 1) => wr_data_addr(3 downto 0),
      ADDRB(0) => '0',
      ADDRC(4 downto 1) => wr_data_addr(3 downto 0),
      ADDRC(0) => '0',
      ADDRD(4 downto 1) => wb_wr_data_addr_w(4 downto 1),
      ADDRD(0) => \write_data_control.wb_wr_data_addr0_ns\,
      DIA(1 downto 0) => \write_buffer.wr_buf_in_data\(173 downto 172),
      DIB(1 downto 0) => \write_buffer.wr_buf_in_data\(171 downto 170),
      DIC(1 downto 0) => \write_buffer.wr_buf_in_data\(169 downto 168),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => wr_buf_out_data_w(173 downto 172),
      DOB(1 downto 0) => wr_buf_out_data_w(171 downto 170),
      DOC(1 downto 0) => wr_buf_out_data_w(169 downto 168),
      DOD(1 downto 0) => \NLW_write_buffer.wr_buffer_ram[28].RAM32M0_DOD_UNCONNECTED\(1 downto 0),
      WCLK => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      WE => wdf_rdy_ns
    );
\write_buffer.wr_buffer_ram[28].RAM32M0_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(173),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(173),
      O => \write_buffer.wr_buf_in_data\(173)
    );
\write_buffer.wr_buffer_ram[28].RAM32M0_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(172),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(172),
      O => \write_buffer.wr_buf_in_data\(172)
    );
\write_buffer.wr_buffer_ram[28].RAM32M0_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(171),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(171),
      O => \write_buffer.wr_buf_in_data\(171)
    );
\write_buffer.wr_buffer_ram[28].RAM32M0_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(170),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(170),
      O => \write_buffer.wr_buf_in_data\(170)
    );
\write_buffer.wr_buffer_ram[28].RAM32M0_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(169),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(169),
      O => \write_buffer.wr_buf_in_data\(169)
    );
\write_buffer.wr_buffer_ram[28].RAM32M0_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(168),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(168),
      O => \write_buffer.wr_buf_in_data\(168)
    );
\write_buffer.wr_buffer_ram[29].RAM32M0\: unisim.vcomponents.RAM32M
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      IS_WCLK_INVERTED => '0'
    )
        port map (
      ADDRA(4 downto 1) => wr_data_addr(3 downto 0),
      ADDRA(0) => '0',
      ADDRB(4 downto 1) => wr_data_addr(3 downto 0),
      ADDRB(0) => '0',
      ADDRC(4 downto 1) => wr_data_addr(3 downto 0),
      ADDRC(0) => '0',
      ADDRD(4 downto 1) => wb_wr_data_addr_w(4 downto 1),
      ADDRD(0) => \write_data_control.wb_wr_data_addr0_ns\,
      DIA(1 downto 0) => \write_buffer.wr_buf_in_data\(179 downto 178),
      DIB(1 downto 0) => \write_buffer.wr_buf_in_data\(177 downto 176),
      DIC(1 downto 0) => \write_buffer.wr_buf_in_data\(175 downto 174),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => wr_buf_out_data_w(179 downto 178),
      DOB(1 downto 0) => wr_buf_out_data_w(177 downto 176),
      DOC(1 downto 0) => wr_buf_out_data_w(175 downto 174),
      DOD(1 downto 0) => \NLW_write_buffer.wr_buffer_ram[29].RAM32M0_DOD_UNCONNECTED\(1 downto 0),
      WCLK => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      WE => wdf_rdy_ns
    );
\write_buffer.wr_buffer_ram[29].RAM32M0_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(179),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(179),
      O => \write_buffer.wr_buf_in_data\(179)
    );
\write_buffer.wr_buffer_ram[29].RAM32M0_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(178),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(178),
      O => \write_buffer.wr_buf_in_data\(178)
    );
\write_buffer.wr_buffer_ram[29].RAM32M0_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(177),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(177),
      O => \write_buffer.wr_buf_in_data\(177)
    );
\write_buffer.wr_buffer_ram[29].RAM32M0_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(176),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(176),
      O => \write_buffer.wr_buf_in_data\(176)
    );
\write_buffer.wr_buffer_ram[29].RAM32M0_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(175),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(175),
      O => \write_buffer.wr_buf_in_data\(175)
    );
\write_buffer.wr_buffer_ram[29].RAM32M0_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(174),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(174),
      O => \write_buffer.wr_buf_in_data\(174)
    );
\write_buffer.wr_buffer_ram[2].RAM32M0\: unisim.vcomponents.RAM32M
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      IS_WCLK_INVERTED => '0'
    )
        port map (
      ADDRA(4 downto 1) => wr_data_addr(3 downto 0),
      ADDRA(0) => '0',
      ADDRB(4 downto 1) => wr_data_addr(3 downto 0),
      ADDRB(0) => '0',
      ADDRC(4 downto 1) => wr_data_addr(3 downto 0),
      ADDRC(0) => '0',
      ADDRD(4 downto 1) => wb_wr_data_addr_w(4 downto 1),
      ADDRD(0) => \write_data_control.wb_wr_data_addr0_ns\,
      DIA(1 downto 0) => \write_buffer.wr_buf_in_data\(17 downto 16),
      DIB(1 downto 0) => \write_buffer.wr_buf_in_data\(15 downto 14),
      DIC(1 downto 0) => \write_buffer.wr_buf_in_data\(13 downto 12),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => wr_buf_out_data_w(17 downto 16),
      DOB(1 downto 0) => wr_buf_out_data_w(15 downto 14),
      DOC(1 downto 0) => wr_buf_out_data_w(13 downto 12),
      DOD(1 downto 0) => \NLW_write_buffer.wr_buffer_ram[2].RAM32M0_DOD_UNCONNECTED\(1 downto 0),
      WCLK => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      WE => wdf_rdy_ns
    );
\write_buffer.wr_buffer_ram[2].RAM32M0_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(17),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(17),
      O => \write_buffer.wr_buf_in_data\(17)
    );
\write_buffer.wr_buffer_ram[2].RAM32M0_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(16),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(16),
      O => \write_buffer.wr_buf_in_data\(16)
    );
\write_buffer.wr_buffer_ram[2].RAM32M0_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(15),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(15),
      O => \write_buffer.wr_buf_in_data\(15)
    );
\write_buffer.wr_buffer_ram[2].RAM32M0_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(14),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(14),
      O => \write_buffer.wr_buf_in_data\(14)
    );
\write_buffer.wr_buffer_ram[2].RAM32M0_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(13),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(13),
      O => \write_buffer.wr_buf_in_data\(13)
    );
\write_buffer.wr_buffer_ram[2].RAM32M0_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(12),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(12),
      O => \write_buffer.wr_buf_in_data\(12)
    );
\write_buffer.wr_buffer_ram[30].RAM32M0\: unisim.vcomponents.RAM32M
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      IS_WCLK_INVERTED => '0'
    )
        port map (
      ADDRA(4 downto 1) => wr_data_addr(3 downto 0),
      ADDRA(0) => '0',
      ADDRB(4 downto 1) => wr_data_addr(3 downto 0),
      ADDRB(0) => '0',
      ADDRC(4 downto 1) => wr_data_addr(3 downto 0),
      ADDRC(0) => '0',
      ADDRD(4 downto 1) => wb_wr_data_addr_w(4 downto 1),
      ADDRD(0) => \write_data_control.wb_wr_data_addr0_ns\,
      DIA(1 downto 0) => \write_buffer.wr_buf_in_data\(185 downto 184),
      DIB(1 downto 0) => \write_buffer.wr_buf_in_data\(183 downto 182),
      DIC(1 downto 0) => \write_buffer.wr_buf_in_data\(181 downto 180),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => wr_buf_out_data_w(185 downto 184),
      DOB(1 downto 0) => wr_buf_out_data_w(183 downto 182),
      DOC(1 downto 0) => wr_buf_out_data_w(181 downto 180),
      DOD(1 downto 0) => \NLW_write_buffer.wr_buffer_ram[30].RAM32M0_DOD_UNCONNECTED\(1 downto 0),
      WCLK => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      WE => wdf_rdy_ns
    );
\write_buffer.wr_buffer_ram[30].RAM32M0_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(185),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(185),
      O => \write_buffer.wr_buf_in_data\(185)
    );
\write_buffer.wr_buffer_ram[30].RAM32M0_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(184),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(184),
      O => \write_buffer.wr_buf_in_data\(184)
    );
\write_buffer.wr_buffer_ram[30].RAM32M0_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(183),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(183),
      O => \write_buffer.wr_buf_in_data\(183)
    );
\write_buffer.wr_buffer_ram[30].RAM32M0_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(182),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(182),
      O => \write_buffer.wr_buf_in_data\(182)
    );
\write_buffer.wr_buffer_ram[30].RAM32M0_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(181),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(181),
      O => \write_buffer.wr_buf_in_data\(181)
    );
\write_buffer.wr_buffer_ram[30].RAM32M0_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(180),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(180),
      O => \write_buffer.wr_buf_in_data\(180)
    );
\write_buffer.wr_buffer_ram[31].RAM32M0\: unisim.vcomponents.RAM32M
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      IS_WCLK_INVERTED => '0'
    )
        port map (
      ADDRA(4 downto 1) => wr_data_addr(3 downto 0),
      ADDRA(0) => '0',
      ADDRB(4 downto 1) => wr_data_addr(3 downto 0),
      ADDRB(0) => '0',
      ADDRC(4 downto 1) => wr_data_addr(3 downto 0),
      ADDRC(0) => '0',
      ADDRD(4 downto 1) => wb_wr_data_addr_w(4 downto 1),
      ADDRD(0) => \write_data_control.wb_wr_data_addr0_ns\,
      DIA(1 downto 0) => \write_buffer.wr_buf_in_data\(191 downto 190),
      DIB(1 downto 0) => \write_buffer.wr_buf_in_data\(189 downto 188),
      DIC(1 downto 0) => \write_buffer.wr_buf_in_data\(187 downto 186),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => wr_buf_out_data_w(191 downto 190),
      DOB(1 downto 0) => wr_buf_out_data_w(189 downto 188),
      DOC(1 downto 0) => wr_buf_out_data_w(187 downto 186),
      DOD(1 downto 0) => \NLW_write_buffer.wr_buffer_ram[31].RAM32M0_DOD_UNCONNECTED\(1 downto 0),
      WCLK => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      WE => wdf_rdy_ns
    );
\write_buffer.wr_buffer_ram[31].RAM32M0_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(191),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(191),
      O => \write_buffer.wr_buf_in_data\(191)
    );
\write_buffer.wr_buffer_ram[31].RAM32M0_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(190),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(190),
      O => \write_buffer.wr_buf_in_data\(190)
    );
\write_buffer.wr_buffer_ram[31].RAM32M0_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(189),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(189),
      O => \write_buffer.wr_buf_in_data\(189)
    );
\write_buffer.wr_buffer_ram[31].RAM32M0_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(188),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(188),
      O => \write_buffer.wr_buf_in_data\(188)
    );
\write_buffer.wr_buffer_ram[31].RAM32M0_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(187),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(187),
      O => \write_buffer.wr_buf_in_data\(187)
    );
\write_buffer.wr_buffer_ram[31].RAM32M0_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(186),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(186),
      O => \write_buffer.wr_buf_in_data\(186)
    );
\write_buffer.wr_buffer_ram[32].RAM32M0\: unisim.vcomponents.RAM32M
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      IS_WCLK_INVERTED => '0'
    )
        port map (
      ADDRA(4 downto 1) => wr_data_addr(3 downto 0),
      ADDRA(0) => '0',
      ADDRB(4 downto 1) => wr_data_addr(3 downto 0),
      ADDRB(0) => '0',
      ADDRC(4 downto 1) => wr_data_addr(3 downto 0),
      ADDRC(0) => '0',
      ADDRD(4 downto 1) => wb_wr_data_addr_w(4 downto 1),
      ADDRD(0) => \write_data_control.wb_wr_data_addr0_ns\,
      DIA(1 downto 0) => \write_buffer.wr_buf_in_data\(197 downto 196),
      DIB(1 downto 0) => \write_buffer.wr_buf_in_data\(195 downto 194),
      DIC(1 downto 0) => \write_buffer.wr_buf_in_data\(193 downto 192),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => wr_buf_out_data_w(197 downto 196),
      DOB(1 downto 0) => wr_buf_out_data_w(195 downto 194),
      DOC(1 downto 0) => wr_buf_out_data_w(193 downto 192),
      DOD(1 downto 0) => \NLW_write_buffer.wr_buffer_ram[32].RAM32M0_DOD_UNCONNECTED\(1 downto 0),
      WCLK => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      WE => wdf_rdy_ns
    );
\write_buffer.wr_buffer_ram[32].RAM32M0_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(197),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(197),
      O => \write_buffer.wr_buf_in_data\(197)
    );
\write_buffer.wr_buffer_ram[32].RAM32M0_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(196),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(196),
      O => \write_buffer.wr_buf_in_data\(196)
    );
\write_buffer.wr_buffer_ram[32].RAM32M0_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(195),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(195),
      O => \write_buffer.wr_buf_in_data\(195)
    );
\write_buffer.wr_buffer_ram[32].RAM32M0_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(194),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(194),
      O => \write_buffer.wr_buf_in_data\(194)
    );
\write_buffer.wr_buffer_ram[32].RAM32M0_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(193),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(193),
      O => \write_buffer.wr_buf_in_data\(193)
    );
\write_buffer.wr_buffer_ram[32].RAM32M0_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(192),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(192),
      O => \write_buffer.wr_buf_in_data\(192)
    );
\write_buffer.wr_buffer_ram[33].RAM32M0\: unisim.vcomponents.RAM32M
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      IS_WCLK_INVERTED => '0'
    )
        port map (
      ADDRA(4 downto 1) => wr_data_addr(3 downto 0),
      ADDRA(0) => '0',
      ADDRB(4 downto 1) => wr_data_addr(3 downto 0),
      ADDRB(0) => '0',
      ADDRC(4 downto 1) => wr_data_addr(3 downto 0),
      ADDRC(0) => '0',
      ADDRD(4 downto 1) => wb_wr_data_addr_w(4 downto 1),
      ADDRD(0) => \write_data_control.wb_wr_data_addr0_ns\,
      DIA(1 downto 0) => \write_buffer.wr_buf_in_data\(203 downto 202),
      DIB(1 downto 0) => \write_buffer.wr_buf_in_data\(201 downto 200),
      DIC(1 downto 0) => \write_buffer.wr_buf_in_data\(199 downto 198),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => wr_buf_out_data_w(203 downto 202),
      DOB(1 downto 0) => wr_buf_out_data_w(201 downto 200),
      DOC(1 downto 0) => wr_buf_out_data_w(199 downto 198),
      DOD(1 downto 0) => \NLW_write_buffer.wr_buffer_ram[33].RAM32M0_DOD_UNCONNECTED\(1 downto 0),
      WCLK => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      WE => wdf_rdy_ns
    );
\write_buffer.wr_buffer_ram[33].RAM32M0_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(203),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(203),
      O => \write_buffer.wr_buf_in_data\(203)
    );
\write_buffer.wr_buffer_ram[33].RAM32M0_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(202),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(202),
      O => \write_buffer.wr_buf_in_data\(202)
    );
\write_buffer.wr_buffer_ram[33].RAM32M0_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(201),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(201),
      O => \write_buffer.wr_buf_in_data\(201)
    );
\write_buffer.wr_buffer_ram[33].RAM32M0_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(200),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(200),
      O => \write_buffer.wr_buf_in_data\(200)
    );
\write_buffer.wr_buffer_ram[33].RAM32M0_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(199),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(199),
      O => \write_buffer.wr_buf_in_data\(199)
    );
\write_buffer.wr_buffer_ram[33].RAM32M0_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(198),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(198),
      O => \write_buffer.wr_buf_in_data\(198)
    );
\write_buffer.wr_buffer_ram[34].RAM32M0\: unisim.vcomponents.RAM32M
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      IS_WCLK_INVERTED => '0'
    )
        port map (
      ADDRA(4 downto 1) => wr_data_addr(3 downto 0),
      ADDRA(0) => '0',
      ADDRB(4 downto 1) => wr_data_addr(3 downto 0),
      ADDRB(0) => '0',
      ADDRC(4 downto 1) => wr_data_addr(3 downto 0),
      ADDRC(0) => '0',
      ADDRD(4 downto 1) => wb_wr_data_addr_w(4 downto 1),
      ADDRD(0) => \write_data_control.wb_wr_data_addr0_ns\,
      DIA(1 downto 0) => \write_buffer.wr_buf_in_data\(209 downto 208),
      DIB(1 downto 0) => \write_buffer.wr_buf_in_data\(207 downto 206),
      DIC(1 downto 0) => \write_buffer.wr_buf_in_data\(205 downto 204),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => wr_buf_out_data_w(209 downto 208),
      DOB(1 downto 0) => wr_buf_out_data_w(207 downto 206),
      DOC(1 downto 0) => wr_buf_out_data_w(205 downto 204),
      DOD(1 downto 0) => \NLW_write_buffer.wr_buffer_ram[34].RAM32M0_DOD_UNCONNECTED\(1 downto 0),
      WCLK => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      WE => wdf_rdy_ns
    );
\write_buffer.wr_buffer_ram[34].RAM32M0_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(209),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(209),
      O => \write_buffer.wr_buf_in_data\(209)
    );
\write_buffer.wr_buffer_ram[34].RAM32M0_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(208),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(208),
      O => \write_buffer.wr_buf_in_data\(208)
    );
\write_buffer.wr_buffer_ram[34].RAM32M0_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(207),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(207),
      O => \write_buffer.wr_buf_in_data\(207)
    );
\write_buffer.wr_buffer_ram[34].RAM32M0_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(206),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(206),
      O => \write_buffer.wr_buf_in_data\(206)
    );
\write_buffer.wr_buffer_ram[34].RAM32M0_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(205),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(205),
      O => \write_buffer.wr_buf_in_data\(205)
    );
\write_buffer.wr_buffer_ram[34].RAM32M0_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(204),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(204),
      O => \write_buffer.wr_buf_in_data\(204)
    );
\write_buffer.wr_buffer_ram[35].RAM32M0\: unisim.vcomponents.RAM32M
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      IS_WCLK_INVERTED => '0'
    )
        port map (
      ADDRA(4 downto 1) => wr_data_addr(3 downto 0),
      ADDRA(0) => '0',
      ADDRB(4 downto 1) => wr_data_addr(3 downto 0),
      ADDRB(0) => '0',
      ADDRC(4 downto 1) => wr_data_addr(3 downto 0),
      ADDRC(0) => '0',
      ADDRD(4 downto 1) => wb_wr_data_addr_w(4 downto 1),
      ADDRD(0) => \write_data_control.wb_wr_data_addr0_ns\,
      DIA(1 downto 0) => \write_buffer.wr_buf_in_data\(215 downto 214),
      DIB(1 downto 0) => \write_buffer.wr_buf_in_data\(213 downto 212),
      DIC(1 downto 0) => \write_buffer.wr_buf_in_data\(211 downto 210),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => wr_buf_out_data_w(215 downto 214),
      DOB(1 downto 0) => wr_buf_out_data_w(213 downto 212),
      DOC(1 downto 0) => wr_buf_out_data_w(211 downto 210),
      DOD(1 downto 0) => \NLW_write_buffer.wr_buffer_ram[35].RAM32M0_DOD_UNCONNECTED\(1 downto 0),
      WCLK => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      WE => wdf_rdy_ns
    );
\write_buffer.wr_buffer_ram[35].RAM32M0_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(215),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(215),
      O => \write_buffer.wr_buf_in_data\(215)
    );
\write_buffer.wr_buffer_ram[35].RAM32M0_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(214),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(214),
      O => \write_buffer.wr_buf_in_data\(214)
    );
\write_buffer.wr_buffer_ram[35].RAM32M0_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(213),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(213),
      O => \write_buffer.wr_buf_in_data\(213)
    );
\write_buffer.wr_buffer_ram[35].RAM32M0_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(212),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(212),
      O => \write_buffer.wr_buf_in_data\(212)
    );
\write_buffer.wr_buffer_ram[35].RAM32M0_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(211),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(211),
      O => \write_buffer.wr_buf_in_data\(211)
    );
\write_buffer.wr_buffer_ram[35].RAM32M0_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(210),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(210),
      O => \write_buffer.wr_buf_in_data\(210)
    );
\write_buffer.wr_buffer_ram[36].RAM32M0\: unisim.vcomponents.RAM32M
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      IS_WCLK_INVERTED => '0'
    )
        port map (
      ADDRA(4 downto 1) => wr_data_addr(3 downto 0),
      ADDRA(0) => '0',
      ADDRB(4 downto 1) => wr_data_addr(3 downto 0),
      ADDRB(0) => '0',
      ADDRC(4 downto 1) => wr_data_addr(3 downto 0),
      ADDRC(0) => '0',
      ADDRD(4 downto 1) => wb_wr_data_addr_w(4 downto 1),
      ADDRD(0) => \write_data_control.wb_wr_data_addr0_ns\,
      DIA(1 downto 0) => \write_buffer.wr_buf_in_data\(221 downto 220),
      DIB(1 downto 0) => \write_buffer.wr_buf_in_data\(219 downto 218),
      DIC(1 downto 0) => \write_buffer.wr_buf_in_data\(217 downto 216),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => wr_buf_out_data_w(221 downto 220),
      DOB(1 downto 0) => wr_buf_out_data_w(219 downto 218),
      DOC(1 downto 0) => wr_buf_out_data_w(217 downto 216),
      DOD(1 downto 0) => \NLW_write_buffer.wr_buffer_ram[36].RAM32M0_DOD_UNCONNECTED\(1 downto 0),
      WCLK => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      WE => wdf_rdy_ns
    );
\write_buffer.wr_buffer_ram[36].RAM32M0_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(221),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(221),
      O => \write_buffer.wr_buf_in_data\(221)
    );
\write_buffer.wr_buffer_ram[36].RAM32M0_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(220),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(220),
      O => \write_buffer.wr_buf_in_data\(220)
    );
\write_buffer.wr_buffer_ram[36].RAM32M0_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(219),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(219),
      O => \write_buffer.wr_buf_in_data\(219)
    );
\write_buffer.wr_buffer_ram[36].RAM32M0_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(218),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(218),
      O => \write_buffer.wr_buf_in_data\(218)
    );
\write_buffer.wr_buffer_ram[36].RAM32M0_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(217),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(217),
      O => \write_buffer.wr_buf_in_data\(217)
    );
\write_buffer.wr_buffer_ram[36].RAM32M0_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(216),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(216),
      O => \write_buffer.wr_buf_in_data\(216)
    );
\write_buffer.wr_buffer_ram[37].RAM32M0\: unisim.vcomponents.RAM32M
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      IS_WCLK_INVERTED => '0'
    )
        port map (
      ADDRA(4 downto 1) => wr_data_addr(3 downto 0),
      ADDRA(0) => '0',
      ADDRB(4 downto 1) => wr_data_addr(3 downto 0),
      ADDRB(0) => '0',
      ADDRC(4 downto 1) => wr_data_addr(3 downto 0),
      ADDRC(0) => '0',
      ADDRD(4 downto 1) => wb_wr_data_addr_w(4 downto 1),
      ADDRD(0) => \write_data_control.wb_wr_data_addr0_ns\,
      DIA(1 downto 0) => \write_buffer.wr_buf_in_data\(227 downto 226),
      DIB(1 downto 0) => \write_buffer.wr_buf_in_data\(225 downto 224),
      DIC(1 downto 0) => \write_buffer.wr_buf_in_data\(223 downto 222),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => wr_buf_out_data_w(227 downto 226),
      DOB(1 downto 0) => wr_buf_out_data_w(225 downto 224),
      DOC(1 downto 0) => wr_buf_out_data_w(223 downto 222),
      DOD(1 downto 0) => \NLW_write_buffer.wr_buffer_ram[37].RAM32M0_DOD_UNCONNECTED\(1 downto 0),
      WCLK => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      WE => wdf_rdy_ns
    );
\write_buffer.wr_buffer_ram[37].RAM32M0_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(227),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(227),
      O => \write_buffer.wr_buf_in_data\(227)
    );
\write_buffer.wr_buffer_ram[37].RAM32M0_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(226),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(226),
      O => \write_buffer.wr_buf_in_data\(226)
    );
\write_buffer.wr_buffer_ram[37].RAM32M0_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(225),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(225),
      O => \write_buffer.wr_buf_in_data\(225)
    );
\write_buffer.wr_buffer_ram[37].RAM32M0_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(224),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(224),
      O => \write_buffer.wr_buf_in_data\(224)
    );
\write_buffer.wr_buffer_ram[37].RAM32M0_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(223),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(223),
      O => \write_buffer.wr_buf_in_data\(223)
    );
\write_buffer.wr_buffer_ram[37].RAM32M0_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(222),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(222),
      O => \write_buffer.wr_buf_in_data\(222)
    );
\write_buffer.wr_buffer_ram[38].RAM32M0\: unisim.vcomponents.RAM32M
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      IS_WCLK_INVERTED => '0'
    )
        port map (
      ADDRA(4 downto 1) => wr_data_addr(3 downto 0),
      ADDRA(0) => '0',
      ADDRB(4 downto 1) => wr_data_addr(3 downto 0),
      ADDRB(0) => '0',
      ADDRC(4 downto 1) => wr_data_addr(3 downto 0),
      ADDRC(0) => '0',
      ADDRD(4 downto 1) => wb_wr_data_addr_w(4 downto 1),
      ADDRD(0) => \write_data_control.wb_wr_data_addr0_ns\,
      DIA(1 downto 0) => \write_buffer.wr_buf_in_data\(233 downto 232),
      DIB(1 downto 0) => \write_buffer.wr_buf_in_data\(231 downto 230),
      DIC(1 downto 0) => \write_buffer.wr_buf_in_data\(229 downto 228),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => wr_buf_out_data_w(233 downto 232),
      DOB(1 downto 0) => wr_buf_out_data_w(231 downto 230),
      DOC(1 downto 0) => wr_buf_out_data_w(229 downto 228),
      DOD(1 downto 0) => \NLW_write_buffer.wr_buffer_ram[38].RAM32M0_DOD_UNCONNECTED\(1 downto 0),
      WCLK => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      WE => wdf_rdy_ns
    );
\write_buffer.wr_buffer_ram[38].RAM32M0_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(233),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(233),
      O => \write_buffer.wr_buf_in_data\(233)
    );
\write_buffer.wr_buffer_ram[38].RAM32M0_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(232),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(232),
      O => \write_buffer.wr_buf_in_data\(232)
    );
\write_buffer.wr_buffer_ram[38].RAM32M0_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(231),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(231),
      O => \write_buffer.wr_buf_in_data\(231)
    );
\write_buffer.wr_buffer_ram[38].RAM32M0_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(230),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(230),
      O => \write_buffer.wr_buf_in_data\(230)
    );
\write_buffer.wr_buffer_ram[38].RAM32M0_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(229),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(229),
      O => \write_buffer.wr_buf_in_data\(229)
    );
\write_buffer.wr_buffer_ram[38].RAM32M0_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(228),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(228),
      O => \write_buffer.wr_buf_in_data\(228)
    );
\write_buffer.wr_buffer_ram[39].RAM32M0\: unisim.vcomponents.RAM32M
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      IS_WCLK_INVERTED => '0'
    )
        port map (
      ADDRA(4 downto 1) => wr_data_addr(3 downto 0),
      ADDRA(0) => '0',
      ADDRB(4 downto 1) => wr_data_addr(3 downto 0),
      ADDRB(0) => '0',
      ADDRC(4 downto 1) => wr_data_addr(3 downto 0),
      ADDRC(0) => '0',
      ADDRD(4 downto 1) => wb_wr_data_addr_w(4 downto 1),
      ADDRD(0) => \write_data_control.wb_wr_data_addr0_ns\,
      DIA(1 downto 0) => \write_buffer.wr_buf_in_data\(239 downto 238),
      DIB(1 downto 0) => \write_buffer.wr_buf_in_data\(237 downto 236),
      DIC(1 downto 0) => \write_buffer.wr_buf_in_data\(235 downto 234),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => wr_buf_out_data_w(239 downto 238),
      DOB(1 downto 0) => wr_buf_out_data_w(237 downto 236),
      DOC(1 downto 0) => wr_buf_out_data_w(235 downto 234),
      DOD(1 downto 0) => \NLW_write_buffer.wr_buffer_ram[39].RAM32M0_DOD_UNCONNECTED\(1 downto 0),
      WCLK => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      WE => wdf_rdy_ns
    );
\write_buffer.wr_buffer_ram[39].RAM32M0_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(239),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(239),
      O => \write_buffer.wr_buf_in_data\(239)
    );
\write_buffer.wr_buffer_ram[39].RAM32M0_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(238),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(238),
      O => \write_buffer.wr_buf_in_data\(238)
    );
\write_buffer.wr_buffer_ram[39].RAM32M0_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(237),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(237),
      O => \write_buffer.wr_buf_in_data\(237)
    );
\write_buffer.wr_buffer_ram[39].RAM32M0_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(236),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(236),
      O => \write_buffer.wr_buf_in_data\(236)
    );
\write_buffer.wr_buffer_ram[39].RAM32M0_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(235),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(235),
      O => \write_buffer.wr_buf_in_data\(235)
    );
\write_buffer.wr_buffer_ram[39].RAM32M0_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(234),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(234),
      O => \write_buffer.wr_buf_in_data\(234)
    );
\write_buffer.wr_buffer_ram[3].RAM32M0\: unisim.vcomponents.RAM32M
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      IS_WCLK_INVERTED => '0'
    )
        port map (
      ADDRA(4 downto 1) => wr_data_addr(3 downto 0),
      ADDRA(0) => '0',
      ADDRB(4 downto 1) => wr_data_addr(3 downto 0),
      ADDRB(0) => '0',
      ADDRC(4 downto 1) => wr_data_addr(3 downto 0),
      ADDRC(0) => '0',
      ADDRD(4 downto 1) => wb_wr_data_addr_w(4 downto 1),
      ADDRD(0) => \write_data_control.wb_wr_data_addr0_ns\,
      DIA(1 downto 0) => \write_buffer.wr_buf_in_data\(23 downto 22),
      DIB(1 downto 0) => \write_buffer.wr_buf_in_data\(21 downto 20),
      DIC(1 downto 0) => \write_buffer.wr_buf_in_data\(19 downto 18),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => wr_buf_out_data_w(23 downto 22),
      DOB(1 downto 0) => wr_buf_out_data_w(21 downto 20),
      DOC(1 downto 0) => wr_buf_out_data_w(19 downto 18),
      DOD(1 downto 0) => \NLW_write_buffer.wr_buffer_ram[3].RAM32M0_DOD_UNCONNECTED\(1 downto 0),
      WCLK => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      WE => wdf_rdy_ns
    );
\write_buffer.wr_buffer_ram[3].RAM32M0_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(23),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(23),
      O => \write_buffer.wr_buf_in_data\(23)
    );
\write_buffer.wr_buffer_ram[3].RAM32M0_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(22),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(22),
      O => \write_buffer.wr_buf_in_data\(22)
    );
\write_buffer.wr_buffer_ram[3].RAM32M0_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(21),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(21),
      O => \write_buffer.wr_buf_in_data\(21)
    );
\write_buffer.wr_buffer_ram[3].RAM32M0_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(20),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(20),
      O => \write_buffer.wr_buf_in_data\(20)
    );
\write_buffer.wr_buffer_ram[3].RAM32M0_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(19),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(19),
      O => \write_buffer.wr_buf_in_data\(19)
    );
\write_buffer.wr_buffer_ram[3].RAM32M0_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(18),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(18),
      O => \write_buffer.wr_buf_in_data\(18)
    );
\write_buffer.wr_buffer_ram[40].RAM32M0\: unisim.vcomponents.RAM32M
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      IS_WCLK_INVERTED => '0'
    )
        port map (
      ADDRA(4 downto 1) => wr_data_addr(3 downto 0),
      ADDRA(0) => '0',
      ADDRB(4 downto 1) => wr_data_addr(3 downto 0),
      ADDRB(0) => '0',
      ADDRC(4 downto 1) => wr_data_addr(3 downto 0),
      ADDRC(0) => '0',
      ADDRD(4 downto 1) => wb_wr_data_addr_w(4 downto 1),
      ADDRD(0) => \write_data_control.wb_wr_data_addr0_ns\,
      DIA(1 downto 0) => \write_buffer.wr_buf_in_data\(245 downto 244),
      DIB(1 downto 0) => \write_buffer.wr_buf_in_data\(243 downto 242),
      DIC(1 downto 0) => \write_buffer.wr_buf_in_data\(241 downto 240),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => wr_buf_out_data_w(245 downto 244),
      DOB(1 downto 0) => wr_buf_out_data_w(243 downto 242),
      DOC(1 downto 0) => wr_buf_out_data_w(241 downto 240),
      DOD(1 downto 0) => \NLW_write_buffer.wr_buffer_ram[40].RAM32M0_DOD_UNCONNECTED\(1 downto 0),
      WCLK => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      WE => wdf_rdy_ns
    );
\write_buffer.wr_buffer_ram[40].RAM32M0_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(245),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(245),
      O => \write_buffer.wr_buf_in_data\(245)
    );
\write_buffer.wr_buffer_ram[40].RAM32M0_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(244),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(244),
      O => \write_buffer.wr_buf_in_data\(244)
    );
\write_buffer.wr_buffer_ram[40].RAM32M0_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(243),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(243),
      O => \write_buffer.wr_buf_in_data\(243)
    );
\write_buffer.wr_buffer_ram[40].RAM32M0_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(242),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(242),
      O => \write_buffer.wr_buf_in_data\(242)
    );
\write_buffer.wr_buffer_ram[40].RAM32M0_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(241),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(241),
      O => \write_buffer.wr_buf_in_data\(241)
    );
\write_buffer.wr_buffer_ram[40].RAM32M0_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(240),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(240),
      O => \write_buffer.wr_buf_in_data\(240)
    );
\write_buffer.wr_buffer_ram[41].RAM32M0\: unisim.vcomponents.RAM32M
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      IS_WCLK_INVERTED => '0'
    )
        port map (
      ADDRA(4 downto 1) => wr_data_addr(3 downto 0),
      ADDRA(0) => '0',
      ADDRB(4 downto 1) => wr_data_addr(3 downto 0),
      ADDRB(0) => '0',
      ADDRC(4 downto 1) => wr_data_addr(3 downto 0),
      ADDRC(0) => '0',
      ADDRD(4 downto 1) => wb_wr_data_addr_w(4 downto 1),
      ADDRD(0) => \write_data_control.wb_wr_data_addr0_ns\,
      DIA(1 downto 0) => \write_buffer.wr_buf_in_data\(251 downto 250),
      DIB(1 downto 0) => \write_buffer.wr_buf_in_data\(249 downto 248),
      DIC(1 downto 0) => \write_buffer.wr_buf_in_data\(247 downto 246),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => wr_buf_out_data_w(251 downto 250),
      DOB(1 downto 0) => wr_buf_out_data_w(249 downto 248),
      DOC(1 downto 0) => wr_buf_out_data_w(247 downto 246),
      DOD(1 downto 0) => \NLW_write_buffer.wr_buffer_ram[41].RAM32M0_DOD_UNCONNECTED\(1 downto 0),
      WCLK => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      WE => wdf_rdy_ns
    );
\write_buffer.wr_buffer_ram[41].RAM32M0_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(251),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(251),
      O => \write_buffer.wr_buf_in_data\(251)
    );
\write_buffer.wr_buffer_ram[41].RAM32M0_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(250),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(250),
      O => \write_buffer.wr_buf_in_data\(250)
    );
\write_buffer.wr_buffer_ram[41].RAM32M0_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(249),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(249),
      O => \write_buffer.wr_buf_in_data\(249)
    );
\write_buffer.wr_buffer_ram[41].RAM32M0_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(248),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(248),
      O => \write_buffer.wr_buf_in_data\(248)
    );
\write_buffer.wr_buffer_ram[41].RAM32M0_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(247),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(247),
      O => \write_buffer.wr_buf_in_data\(247)
    );
\write_buffer.wr_buffer_ram[41].RAM32M0_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(246),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(246),
      O => \write_buffer.wr_buf_in_data\(246)
    );
\write_buffer.wr_buffer_ram[42].RAM32M0\: unisim.vcomponents.RAM32M
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      IS_WCLK_INVERTED => '0'
    )
        port map (
      ADDRA(4 downto 1) => wr_data_addr(3 downto 0),
      ADDRA(0) => '0',
      ADDRB(4 downto 1) => wr_data_addr(3 downto 0),
      ADDRB(0) => '0',
      ADDRC(4 downto 1) => wr_data_addr(3 downto 0),
      ADDRC(0) => '0',
      ADDRD(4 downto 1) => wb_wr_data_addr_w(4 downto 1),
      ADDRD(0) => \write_data_control.wb_wr_data_addr0_ns\,
      DIA(1 downto 0) => \write_buffer.wr_buf_in_data\(257 downto 256),
      DIB(1 downto 0) => \write_buffer.wr_buf_in_data\(255 downto 254),
      DIC(1 downto 0) => \write_buffer.wr_buf_in_data\(253 downto 252),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => wr_buf_out_data_w(257 downto 256),
      DOB(1 downto 0) => wr_buf_out_data_w(255 downto 254),
      DOC(1 downto 0) => wr_buf_out_data_w(253 downto 252),
      DOD(1 downto 0) => \NLW_write_buffer.wr_buffer_ram[42].RAM32M0_DOD_UNCONNECTED\(1 downto 0),
      WCLK => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      WE => wdf_rdy_ns
    );
\write_buffer.wr_buffer_ram[42].RAM32M0_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(257),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(257),
      O => \write_buffer.wr_buf_in_data\(257)
    );
\write_buffer.wr_buffer_ram[42].RAM32M0_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(256),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(256),
      O => \write_buffer.wr_buf_in_data\(256)
    );
\write_buffer.wr_buffer_ram[42].RAM32M0_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(255),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(255),
      O => \write_buffer.wr_buf_in_data\(255)
    );
\write_buffer.wr_buffer_ram[42].RAM32M0_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(254),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(254),
      O => \write_buffer.wr_buf_in_data\(254)
    );
\write_buffer.wr_buffer_ram[42].RAM32M0_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(253),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(253),
      O => \write_buffer.wr_buf_in_data\(253)
    );
\write_buffer.wr_buffer_ram[42].RAM32M0_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(252),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(252),
      O => \write_buffer.wr_buf_in_data\(252)
    );
\write_buffer.wr_buffer_ram[43].RAM32M0\: unisim.vcomponents.RAM32M
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      IS_WCLK_INVERTED => '0'
    )
        port map (
      ADDRA(4 downto 1) => wr_data_addr(3 downto 0),
      ADDRA(0) => '0',
      ADDRB(4 downto 1) => wr_data_addr(3 downto 0),
      ADDRB(0) => '0',
      ADDRC(4 downto 1) => wr_data_addr(3 downto 0),
      ADDRC(0) => '0',
      ADDRD(4 downto 1) => wb_wr_data_addr_w(4 downto 1),
      ADDRD(0) => \write_data_control.wb_wr_data_addr0_ns\,
      DIA(1 downto 0) => \write_buffer.wr_buf_in_data\(263 downto 262),
      DIB(1 downto 0) => \write_buffer.wr_buf_in_data\(261 downto 260),
      DIC(1 downto 0) => \write_buffer.wr_buf_in_data\(259 downto 258),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => wr_buf_out_data_w(263 downto 262),
      DOB(1 downto 0) => wr_buf_out_data_w(261 downto 260),
      DOC(1 downto 0) => wr_buf_out_data_w(259 downto 258),
      DOD(1 downto 0) => \NLW_write_buffer.wr_buffer_ram[43].RAM32M0_DOD_UNCONNECTED\(1 downto 0),
      WCLK => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      WE => wdf_rdy_ns
    );
\write_buffer.wr_buffer_ram[43].RAM32M0_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(263),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(263),
      O => \write_buffer.wr_buf_in_data\(263)
    );
\write_buffer.wr_buffer_ram[43].RAM32M0_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(262),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(262),
      O => \write_buffer.wr_buf_in_data\(262)
    );
\write_buffer.wr_buffer_ram[43].RAM32M0_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(261),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(261),
      O => \write_buffer.wr_buf_in_data\(261)
    );
\write_buffer.wr_buffer_ram[43].RAM32M0_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(260),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(260),
      O => \write_buffer.wr_buf_in_data\(260)
    );
\write_buffer.wr_buffer_ram[43].RAM32M0_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(259),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(259),
      O => \write_buffer.wr_buf_in_data\(259)
    );
\write_buffer.wr_buffer_ram[43].RAM32M0_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(258),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(258),
      O => \write_buffer.wr_buf_in_data\(258)
    );
\write_buffer.wr_buffer_ram[44].RAM32M0\: unisim.vcomponents.RAM32M
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      IS_WCLK_INVERTED => '0'
    )
        port map (
      ADDRA(4 downto 1) => wr_data_addr(3 downto 0),
      ADDRA(0) => '0',
      ADDRB(4 downto 1) => wr_data_addr(3 downto 0),
      ADDRB(0) => '0',
      ADDRC(4 downto 1) => wr_data_addr(3 downto 0),
      ADDRC(0) => '0',
      ADDRD(4 downto 1) => wb_wr_data_addr_w(4 downto 1),
      ADDRD(0) => \write_data_control.wb_wr_data_addr0_ns\,
      DIA(1 downto 0) => \write_buffer.wr_buf_in_data\(269 downto 268),
      DIB(1 downto 0) => \write_buffer.wr_buf_in_data\(267 downto 266),
      DIC(1 downto 0) => \write_buffer.wr_buf_in_data\(265 downto 264),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => wr_buf_out_data_w(269 downto 268),
      DOB(1 downto 0) => wr_buf_out_data_w(267 downto 266),
      DOC(1 downto 0) => wr_buf_out_data_w(265 downto 264),
      DOD(1 downto 0) => \NLW_write_buffer.wr_buffer_ram[44].RAM32M0_DOD_UNCONNECTED\(1 downto 0),
      WCLK => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      WE => wdf_rdy_ns
    );
\write_buffer.wr_buffer_ram[44].RAM32M0_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(269),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(269),
      O => \write_buffer.wr_buf_in_data\(269)
    );
\write_buffer.wr_buffer_ram[44].RAM32M0_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(268),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(268),
      O => \write_buffer.wr_buf_in_data\(268)
    );
\write_buffer.wr_buffer_ram[44].RAM32M0_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(267),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(267),
      O => \write_buffer.wr_buf_in_data\(267)
    );
\write_buffer.wr_buffer_ram[44].RAM32M0_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(266),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(266),
      O => \write_buffer.wr_buf_in_data\(266)
    );
\write_buffer.wr_buffer_ram[44].RAM32M0_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(265),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(265),
      O => \write_buffer.wr_buf_in_data\(265)
    );
\write_buffer.wr_buffer_ram[44].RAM32M0_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(264),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(264),
      O => \write_buffer.wr_buf_in_data\(264)
    );
\write_buffer.wr_buffer_ram[45].RAM32M0\: unisim.vcomponents.RAM32M
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      IS_WCLK_INVERTED => '0'
    )
        port map (
      ADDRA(4 downto 1) => wr_data_addr(3 downto 0),
      ADDRA(0) => '0',
      ADDRB(4 downto 1) => wr_data_addr(3 downto 0),
      ADDRB(0) => '0',
      ADDRC(4 downto 1) => wr_data_addr(3 downto 0),
      ADDRC(0) => '0',
      ADDRD(4 downto 1) => wb_wr_data_addr_w(4 downto 1),
      ADDRD(0) => \write_data_control.wb_wr_data_addr0_ns\,
      DIA(1 downto 0) => \write_buffer.wr_buf_in_data\(275 downto 274),
      DIB(1 downto 0) => \write_buffer.wr_buf_in_data\(273 downto 272),
      DIC(1 downto 0) => \write_buffer.wr_buf_in_data\(271 downto 270),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => wr_buf_out_data_w(275 downto 274),
      DOB(1 downto 0) => wr_buf_out_data_w(273 downto 272),
      DOC(1 downto 0) => wr_buf_out_data_w(271 downto 270),
      DOD(1 downto 0) => \NLW_write_buffer.wr_buffer_ram[45].RAM32M0_DOD_UNCONNECTED\(1 downto 0),
      WCLK => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      WE => wdf_rdy_ns
    );
\write_buffer.wr_buffer_ram[45].RAM32M0_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(275),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(275),
      O => \write_buffer.wr_buf_in_data\(275)
    );
\write_buffer.wr_buffer_ram[45].RAM32M0_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(274),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(274),
      O => \write_buffer.wr_buf_in_data\(274)
    );
\write_buffer.wr_buffer_ram[45].RAM32M0_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(273),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(273),
      O => \write_buffer.wr_buf_in_data\(273)
    );
\write_buffer.wr_buffer_ram[45].RAM32M0_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(272),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(272),
      O => \write_buffer.wr_buf_in_data\(272)
    );
\write_buffer.wr_buffer_ram[45].RAM32M0_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(271),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(271),
      O => \write_buffer.wr_buf_in_data\(271)
    );
\write_buffer.wr_buffer_ram[45].RAM32M0_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(270),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(270),
      O => \write_buffer.wr_buf_in_data\(270)
    );
\write_buffer.wr_buffer_ram[46].RAM32M0\: unisim.vcomponents.RAM32M
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      IS_WCLK_INVERTED => '0'
    )
        port map (
      ADDRA(4 downto 1) => wr_data_addr(3 downto 0),
      ADDRA(0) => '0',
      ADDRB(4 downto 1) => wr_data_addr(3 downto 0),
      ADDRB(0) => '0',
      ADDRC(4 downto 1) => wr_data_addr(3 downto 0),
      ADDRC(0) => '0',
      ADDRD(4 downto 1) => wb_wr_data_addr_w(4 downto 1),
      ADDRD(0) => \write_data_control.wb_wr_data_addr0_ns\,
      DIA(1 downto 0) => \write_buffer.wr_buf_in_data\(281 downto 280),
      DIB(1 downto 0) => \write_buffer.wr_buf_in_data\(279 downto 278),
      DIC(1 downto 0) => \write_buffer.wr_buf_in_data\(277 downto 276),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => wr_buf_out_data_w(281 downto 280),
      DOB(1 downto 0) => wr_buf_out_data_w(279 downto 278),
      DOC(1 downto 0) => wr_buf_out_data_w(277 downto 276),
      DOD(1 downto 0) => \NLW_write_buffer.wr_buffer_ram[46].RAM32M0_DOD_UNCONNECTED\(1 downto 0),
      WCLK => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      WE => wdf_rdy_ns
    );
\write_buffer.wr_buffer_ram[46].RAM32M0_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(281),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(281),
      O => \write_buffer.wr_buf_in_data\(281)
    );
\write_buffer.wr_buffer_ram[46].RAM32M0_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(280),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(280),
      O => \write_buffer.wr_buf_in_data\(280)
    );
\write_buffer.wr_buffer_ram[46].RAM32M0_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(279),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(279),
      O => \write_buffer.wr_buf_in_data\(279)
    );
\write_buffer.wr_buffer_ram[46].RAM32M0_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(278),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(278),
      O => \write_buffer.wr_buf_in_data\(278)
    );
\write_buffer.wr_buffer_ram[46].RAM32M0_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(277),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(277),
      O => \write_buffer.wr_buf_in_data\(277)
    );
\write_buffer.wr_buffer_ram[46].RAM32M0_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(276),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(276),
      O => \write_buffer.wr_buf_in_data\(276)
    );
\write_buffer.wr_buffer_ram[47].RAM32M0\: unisim.vcomponents.RAM32M
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      IS_WCLK_INVERTED => '0'
    )
        port map (
      ADDRA(4 downto 1) => wr_data_addr(3 downto 0),
      ADDRA(0) => '0',
      ADDRB(4 downto 1) => wr_data_addr(3 downto 0),
      ADDRB(0) => '0',
      ADDRC(4 downto 1) => wr_data_addr(3 downto 0),
      ADDRC(0) => '0',
      ADDRD(4 downto 1) => wb_wr_data_addr_w(4 downto 1),
      ADDRD(0) => \write_data_control.wb_wr_data_addr0_ns\,
      DIA(1 downto 0) => \write_buffer.wr_buf_in_data\(287 downto 286),
      DIB(1 downto 0) => \write_buffer.wr_buf_in_data\(285 downto 284),
      DIC(1 downto 0) => \write_buffer.wr_buf_in_data\(283 downto 282),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => wr_buf_out_data_w(287 downto 286),
      DOB(1 downto 0) => wr_buf_out_data_w(285 downto 284),
      DOC(1 downto 0) => wr_buf_out_data_w(283 downto 282),
      DOD(1 downto 0) => \NLW_write_buffer.wr_buffer_ram[47].RAM32M0_DOD_UNCONNECTED\(1 downto 0),
      WCLK => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      WE => wdf_rdy_ns
    );
\write_buffer.wr_buffer_ram[47].RAM32M0_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(287),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(287),
      O => \write_buffer.wr_buf_in_data\(287)
    );
\write_buffer.wr_buffer_ram[47].RAM32M0_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(286),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(286),
      O => \write_buffer.wr_buf_in_data\(286)
    );
\write_buffer.wr_buffer_ram[47].RAM32M0_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(285),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(285),
      O => \write_buffer.wr_buf_in_data\(285)
    );
\write_buffer.wr_buffer_ram[47].RAM32M0_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(284),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(284),
      O => \write_buffer.wr_buf_in_data\(284)
    );
\write_buffer.wr_buffer_ram[47].RAM32M0_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(283),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(283),
      O => \write_buffer.wr_buf_in_data\(283)
    );
\write_buffer.wr_buffer_ram[47].RAM32M0_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(282),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(282),
      O => \write_buffer.wr_buf_in_data\(282)
    );
\write_buffer.wr_buffer_ram[48].RAM32M0\: unisim.vcomponents.RAM32M
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      IS_WCLK_INVERTED => '0'
    )
        port map (
      ADDRA(4 downto 1) => wr_data_addr(3 downto 0),
      ADDRA(0) => '0',
      ADDRB(4 downto 1) => wr_data_addr(3 downto 0),
      ADDRB(0) => '0',
      ADDRC(4 downto 1) => wr_data_addr(3 downto 0),
      ADDRC(0) => '0',
      ADDRD(4 downto 1) => wb_wr_data_addr_w(4 downto 1),
      ADDRD(0) => \write_data_control.wb_wr_data_addr0_ns\,
      DIA(1 downto 0) => \write_buffer.wr_buf_in_data\(293 downto 292),
      DIB(1 downto 0) => \write_buffer.wr_buf_in_data\(291 downto 290),
      DIC(1 downto 0) => \write_buffer.wr_buf_in_data\(289 downto 288),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => wr_buf_out_data_w(293 downto 292),
      DOB(1 downto 0) => wr_buf_out_data_w(291 downto 290),
      DOC(1 downto 0) => wr_buf_out_data_w(289 downto 288),
      DOD(1 downto 0) => \NLW_write_buffer.wr_buffer_ram[48].RAM32M0_DOD_UNCONNECTED\(1 downto 0),
      WCLK => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      WE => wdf_rdy_ns
    );
\write_buffer.wr_buffer_ram[48].RAM32M0_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(293),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(293),
      O => \write_buffer.wr_buf_in_data\(293)
    );
\write_buffer.wr_buffer_ram[48].RAM32M0_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(292),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(292),
      O => \write_buffer.wr_buf_in_data\(292)
    );
\write_buffer.wr_buffer_ram[48].RAM32M0_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(291),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(291),
      O => \write_buffer.wr_buf_in_data\(291)
    );
\write_buffer.wr_buffer_ram[48].RAM32M0_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(290),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(290),
      O => \write_buffer.wr_buf_in_data\(290)
    );
\write_buffer.wr_buffer_ram[48].RAM32M0_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(289),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(289),
      O => \write_buffer.wr_buf_in_data\(289)
    );
\write_buffer.wr_buffer_ram[48].RAM32M0_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(288),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(288),
      O => \write_buffer.wr_buf_in_data\(288)
    );
\write_buffer.wr_buffer_ram[49].RAM32M0\: unisim.vcomponents.RAM32M
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      IS_WCLK_INVERTED => '0'
    )
        port map (
      ADDRA(4 downto 1) => wr_data_addr(3 downto 0),
      ADDRA(0) => '0',
      ADDRB(4 downto 1) => wr_data_addr(3 downto 0),
      ADDRB(0) => '0',
      ADDRC(4 downto 1) => wr_data_addr(3 downto 0),
      ADDRC(0) => '0',
      ADDRD(4 downto 1) => wb_wr_data_addr_w(4 downto 1),
      ADDRD(0) => \write_data_control.wb_wr_data_addr0_ns\,
      DIA(1 downto 0) => \write_buffer.wr_buf_in_data\(299 downto 298),
      DIB(1 downto 0) => \write_buffer.wr_buf_in_data\(297 downto 296),
      DIC(1 downto 0) => \write_buffer.wr_buf_in_data\(295 downto 294),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => wr_buf_out_data_w(299 downto 298),
      DOB(1 downto 0) => wr_buf_out_data_w(297 downto 296),
      DOC(1 downto 0) => wr_buf_out_data_w(295 downto 294),
      DOD(1 downto 0) => \NLW_write_buffer.wr_buffer_ram[49].RAM32M0_DOD_UNCONNECTED\(1 downto 0),
      WCLK => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      WE => wdf_rdy_ns
    );
\write_buffer.wr_buffer_ram[49].RAM32M0_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(299),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(299),
      O => \write_buffer.wr_buf_in_data\(299)
    );
\write_buffer.wr_buffer_ram[49].RAM32M0_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(298),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(298),
      O => \write_buffer.wr_buf_in_data\(298)
    );
\write_buffer.wr_buffer_ram[49].RAM32M0_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(297),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(297),
      O => \write_buffer.wr_buf_in_data\(297)
    );
\write_buffer.wr_buffer_ram[49].RAM32M0_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(296),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(296),
      O => \write_buffer.wr_buf_in_data\(296)
    );
\write_buffer.wr_buffer_ram[49].RAM32M0_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(295),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(295),
      O => \write_buffer.wr_buf_in_data\(295)
    );
\write_buffer.wr_buffer_ram[49].RAM32M0_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(294),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(294),
      O => \write_buffer.wr_buf_in_data\(294)
    );
\write_buffer.wr_buffer_ram[4].RAM32M0\: unisim.vcomponents.RAM32M
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      IS_WCLK_INVERTED => '0'
    )
        port map (
      ADDRA(4 downto 1) => wr_data_addr(3 downto 0),
      ADDRA(0) => '0',
      ADDRB(4 downto 1) => wr_data_addr(3 downto 0),
      ADDRB(0) => '0',
      ADDRC(4 downto 1) => wr_data_addr(3 downto 0),
      ADDRC(0) => '0',
      ADDRD(4 downto 1) => wb_wr_data_addr_w(4 downto 1),
      ADDRD(0) => \write_data_control.wb_wr_data_addr0_ns\,
      DIA(1 downto 0) => \write_buffer.wr_buf_in_data\(29 downto 28),
      DIB(1 downto 0) => \write_buffer.wr_buf_in_data\(27 downto 26),
      DIC(1 downto 0) => \write_buffer.wr_buf_in_data\(25 downto 24),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => wr_buf_out_data_w(29 downto 28),
      DOB(1 downto 0) => wr_buf_out_data_w(27 downto 26),
      DOC(1 downto 0) => wr_buf_out_data_w(25 downto 24),
      DOD(1 downto 0) => \NLW_write_buffer.wr_buffer_ram[4].RAM32M0_DOD_UNCONNECTED\(1 downto 0),
      WCLK => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      WE => wdf_rdy_ns
    );
\write_buffer.wr_buffer_ram[4].RAM32M0_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(29),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(29),
      O => \write_buffer.wr_buf_in_data\(29)
    );
\write_buffer.wr_buffer_ram[4].RAM32M0_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(28),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(28),
      O => \write_buffer.wr_buf_in_data\(28)
    );
\write_buffer.wr_buffer_ram[4].RAM32M0_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(27),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(27),
      O => \write_buffer.wr_buf_in_data\(27)
    );
\write_buffer.wr_buffer_ram[4].RAM32M0_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(26),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(26),
      O => \write_buffer.wr_buf_in_data\(26)
    );
\write_buffer.wr_buffer_ram[4].RAM32M0_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(25),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(25),
      O => \write_buffer.wr_buf_in_data\(25)
    );
\write_buffer.wr_buffer_ram[4].RAM32M0_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(24),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(24),
      O => \write_buffer.wr_buf_in_data\(24)
    );
\write_buffer.wr_buffer_ram[50].RAM32M0\: unisim.vcomponents.RAM32M
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      IS_WCLK_INVERTED => '0'
    )
        port map (
      ADDRA(4 downto 1) => wr_data_addr(3 downto 0),
      ADDRA(0) => '0',
      ADDRB(4 downto 1) => wr_data_addr(3 downto 0),
      ADDRB(0) => '0',
      ADDRC(4 downto 1) => wr_data_addr(3 downto 0),
      ADDRC(0) => '0',
      ADDRD(4 downto 1) => wb_wr_data_addr_w(4 downto 1),
      ADDRD(0) => \write_data_control.wb_wr_data_addr0_ns\,
      DIA(1 downto 0) => \write_buffer.wr_buf_in_data\(305 downto 304),
      DIB(1 downto 0) => \write_buffer.wr_buf_in_data\(303 downto 302),
      DIC(1 downto 0) => \write_buffer.wr_buf_in_data\(301 downto 300),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => wr_buf_out_data_w(305 downto 304),
      DOB(1 downto 0) => wr_buf_out_data_w(303 downto 302),
      DOC(1 downto 0) => wr_buf_out_data_w(301 downto 300),
      DOD(1 downto 0) => \NLW_write_buffer.wr_buffer_ram[50].RAM32M0_DOD_UNCONNECTED\(1 downto 0),
      WCLK => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      WE => wdf_rdy_ns
    );
\write_buffer.wr_buffer_ram[50].RAM32M0_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(305),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(305),
      O => \write_buffer.wr_buf_in_data\(305)
    );
\write_buffer.wr_buffer_ram[50].RAM32M0_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(304),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(304),
      O => \write_buffer.wr_buf_in_data\(304)
    );
\write_buffer.wr_buffer_ram[50].RAM32M0_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(303),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(303),
      O => \write_buffer.wr_buf_in_data\(303)
    );
\write_buffer.wr_buffer_ram[50].RAM32M0_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(302),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(302),
      O => \write_buffer.wr_buf_in_data\(302)
    );
\write_buffer.wr_buffer_ram[50].RAM32M0_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(301),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(301),
      O => \write_buffer.wr_buf_in_data\(301)
    );
\write_buffer.wr_buffer_ram[50].RAM32M0_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(300),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(300),
      O => \write_buffer.wr_buf_in_data\(300)
    );
\write_buffer.wr_buffer_ram[51].RAM32M0\: unisim.vcomponents.RAM32M
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      IS_WCLK_INVERTED => '0'
    )
        port map (
      ADDRA(4 downto 1) => wr_data_addr(3 downto 0),
      ADDRA(0) => '0',
      ADDRB(4 downto 1) => wr_data_addr(3 downto 0),
      ADDRB(0) => '0',
      ADDRC(4 downto 1) => wr_data_addr(3 downto 0),
      ADDRC(0) => '0',
      ADDRD(4 downto 1) => wb_wr_data_addr_w(4 downto 1),
      ADDRD(0) => \write_data_control.wb_wr_data_addr0_ns\,
      DIA(1 downto 0) => \write_buffer.wr_buf_in_data\(311 downto 310),
      DIB(1 downto 0) => \write_buffer.wr_buf_in_data\(309 downto 308),
      DIC(1 downto 0) => \write_buffer.wr_buf_in_data\(307 downto 306),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => wr_buf_out_data_w(311 downto 310),
      DOB(1 downto 0) => wr_buf_out_data_w(309 downto 308),
      DOC(1 downto 0) => wr_buf_out_data_w(307 downto 306),
      DOD(1 downto 0) => \NLW_write_buffer.wr_buffer_ram[51].RAM32M0_DOD_UNCONNECTED\(1 downto 0),
      WCLK => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      WE => wdf_rdy_ns
    );
\write_buffer.wr_buffer_ram[51].RAM32M0_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(311),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(311),
      O => \write_buffer.wr_buf_in_data\(311)
    );
\write_buffer.wr_buffer_ram[51].RAM32M0_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(310),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(310),
      O => \write_buffer.wr_buf_in_data\(310)
    );
\write_buffer.wr_buffer_ram[51].RAM32M0_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(309),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(309),
      O => \write_buffer.wr_buf_in_data\(309)
    );
\write_buffer.wr_buffer_ram[51].RAM32M0_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(308),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(308),
      O => \write_buffer.wr_buf_in_data\(308)
    );
\write_buffer.wr_buffer_ram[51].RAM32M0_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(307),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(307),
      O => \write_buffer.wr_buf_in_data\(307)
    );
\write_buffer.wr_buffer_ram[51].RAM32M0_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(306),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(306),
      O => \write_buffer.wr_buf_in_data\(306)
    );
\write_buffer.wr_buffer_ram[52].RAM32M0\: unisim.vcomponents.RAM32M
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      IS_WCLK_INVERTED => '0'
    )
        port map (
      ADDRA(4 downto 1) => wr_data_addr(3 downto 0),
      ADDRA(0) => '0',
      ADDRB(4 downto 1) => wr_data_addr(3 downto 0),
      ADDRB(0) => '0',
      ADDRC(4 downto 1) => wr_data_addr(3 downto 0),
      ADDRC(0) => '0',
      ADDRD(4 downto 1) => wb_wr_data_addr_w(4 downto 1),
      ADDRD(0) => \write_data_control.wb_wr_data_addr0_ns\,
      DIA(1 downto 0) => \write_buffer.wr_buf_in_data\(317 downto 316),
      DIB(1 downto 0) => \write_buffer.wr_buf_in_data\(315 downto 314),
      DIC(1 downto 0) => \write_buffer.wr_buf_in_data\(313 downto 312),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => wr_buf_out_data_w(317 downto 316),
      DOB(1 downto 0) => wr_buf_out_data_w(315 downto 314),
      DOC(1 downto 0) => wr_buf_out_data_w(313 downto 312),
      DOD(1 downto 0) => \NLW_write_buffer.wr_buffer_ram[52].RAM32M0_DOD_UNCONNECTED\(1 downto 0),
      WCLK => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      WE => wdf_rdy_ns
    );
\write_buffer.wr_buffer_ram[52].RAM32M0_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(317),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(317),
      O => \write_buffer.wr_buf_in_data\(317)
    );
\write_buffer.wr_buffer_ram[52].RAM32M0_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(316),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(316),
      O => \write_buffer.wr_buf_in_data\(316)
    );
\write_buffer.wr_buffer_ram[52].RAM32M0_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(315),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(315),
      O => \write_buffer.wr_buf_in_data\(315)
    );
\write_buffer.wr_buffer_ram[52].RAM32M0_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(314),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(314),
      O => \write_buffer.wr_buf_in_data\(314)
    );
\write_buffer.wr_buffer_ram[52].RAM32M0_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(313),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(313),
      O => \write_buffer.wr_buf_in_data\(313)
    );
\write_buffer.wr_buffer_ram[52].RAM32M0_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(312),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(312),
      O => \write_buffer.wr_buf_in_data\(312)
    );
\write_buffer.wr_buffer_ram[53].RAM32M0\: unisim.vcomponents.RAM32M
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      IS_WCLK_INVERTED => '0'
    )
        port map (
      ADDRA(4 downto 1) => wr_data_addr(3 downto 0),
      ADDRA(0) => '0',
      ADDRB(4 downto 1) => wr_data_addr(3 downto 0),
      ADDRB(0) => '0',
      ADDRC(4 downto 1) => wr_data_addr(3 downto 0),
      ADDRC(0) => '0',
      ADDRD(4 downto 1) => wb_wr_data_addr_w(4 downto 1),
      ADDRD(0) => \write_data_control.wb_wr_data_addr0_ns\,
      DIA(1 downto 0) => \write_buffer.wr_buf_in_data\(323 downto 322),
      DIB(1 downto 0) => \write_buffer.wr_buf_in_data\(321 downto 320),
      DIC(1 downto 0) => \write_buffer.wr_buf_in_data\(319 downto 318),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => wr_buf_out_data_w(323 downto 322),
      DOB(1 downto 0) => wr_buf_out_data_w(321 downto 320),
      DOC(1 downto 0) => wr_buf_out_data_w(319 downto 318),
      DOD(1 downto 0) => \NLW_write_buffer.wr_buffer_ram[53].RAM32M0_DOD_UNCONNECTED\(1 downto 0),
      WCLK => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      WE => wdf_rdy_ns
    );
\write_buffer.wr_buffer_ram[53].RAM32M0_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(323),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(323),
      O => \write_buffer.wr_buf_in_data\(323)
    );
\write_buffer.wr_buffer_ram[53].RAM32M0_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(322),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(322),
      O => \write_buffer.wr_buf_in_data\(322)
    );
\write_buffer.wr_buffer_ram[53].RAM32M0_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(321),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(321),
      O => \write_buffer.wr_buf_in_data\(321)
    );
\write_buffer.wr_buffer_ram[53].RAM32M0_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(320),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(320),
      O => \write_buffer.wr_buf_in_data\(320)
    );
\write_buffer.wr_buffer_ram[53].RAM32M0_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(319),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(319),
      O => \write_buffer.wr_buf_in_data\(319)
    );
\write_buffer.wr_buffer_ram[53].RAM32M0_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(318),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(318),
      O => \write_buffer.wr_buf_in_data\(318)
    );
\write_buffer.wr_buffer_ram[54].RAM32M0\: unisim.vcomponents.RAM32M
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      IS_WCLK_INVERTED => '0'
    )
        port map (
      ADDRA(4 downto 1) => wr_data_addr(3 downto 0),
      ADDRA(0) => '0',
      ADDRB(4 downto 1) => wr_data_addr(3 downto 0),
      ADDRB(0) => '0',
      ADDRC(4 downto 1) => wr_data_addr(3 downto 0),
      ADDRC(0) => '0',
      ADDRD(4 downto 1) => wb_wr_data_addr_w(4 downto 1),
      ADDRD(0) => \write_data_control.wb_wr_data_addr0_ns\,
      DIA(1 downto 0) => \write_buffer.wr_buf_in_data\(329 downto 328),
      DIB(1 downto 0) => \write_buffer.wr_buf_in_data\(327 downto 326),
      DIC(1 downto 0) => \write_buffer.wr_buf_in_data\(325 downto 324),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => wr_buf_out_data_w(329 downto 328),
      DOB(1 downto 0) => wr_buf_out_data_w(327 downto 326),
      DOC(1 downto 0) => wr_buf_out_data_w(325 downto 324),
      DOD(1 downto 0) => \NLW_write_buffer.wr_buffer_ram[54].RAM32M0_DOD_UNCONNECTED\(1 downto 0),
      WCLK => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      WE => wdf_rdy_ns
    );
\write_buffer.wr_buffer_ram[54].RAM32M0_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(329),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(329),
      O => \write_buffer.wr_buf_in_data\(329)
    );
\write_buffer.wr_buffer_ram[54].RAM32M0_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(328),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(328),
      O => \write_buffer.wr_buf_in_data\(328)
    );
\write_buffer.wr_buffer_ram[54].RAM32M0_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(327),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(327),
      O => \write_buffer.wr_buf_in_data\(327)
    );
\write_buffer.wr_buffer_ram[54].RAM32M0_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(326),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(326),
      O => \write_buffer.wr_buf_in_data\(326)
    );
\write_buffer.wr_buffer_ram[54].RAM32M0_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(325),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(325),
      O => \write_buffer.wr_buf_in_data\(325)
    );
\write_buffer.wr_buffer_ram[54].RAM32M0_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(324),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(324),
      O => \write_buffer.wr_buf_in_data\(324)
    );
\write_buffer.wr_buffer_ram[55].RAM32M0\: unisim.vcomponents.RAM32M
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      IS_WCLK_INVERTED => '0'
    )
        port map (
      ADDRA(4 downto 1) => wr_data_addr(3 downto 0),
      ADDRA(0) => '0',
      ADDRB(4 downto 1) => wr_data_addr(3 downto 0),
      ADDRB(0) => '0',
      ADDRC(4 downto 1) => wr_data_addr(3 downto 0),
      ADDRC(0) => '0',
      ADDRD(4 downto 1) => wb_wr_data_addr_w(4 downto 1),
      ADDRD(0) => \write_data_control.wb_wr_data_addr0_ns\,
      DIA(1 downto 0) => \write_buffer.wr_buf_in_data\(335 downto 334),
      DIB(1 downto 0) => \write_buffer.wr_buf_in_data\(333 downto 332),
      DIC(1 downto 0) => \write_buffer.wr_buf_in_data\(331 downto 330),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => wr_buf_out_data_w(335 downto 334),
      DOB(1 downto 0) => wr_buf_out_data_w(333 downto 332),
      DOC(1 downto 0) => wr_buf_out_data_w(331 downto 330),
      DOD(1 downto 0) => \NLW_write_buffer.wr_buffer_ram[55].RAM32M0_DOD_UNCONNECTED\(1 downto 0),
      WCLK => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      WE => wdf_rdy_ns
    );
\write_buffer.wr_buffer_ram[55].RAM32M0_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(335),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(335),
      O => \write_buffer.wr_buf_in_data\(335)
    );
\write_buffer.wr_buffer_ram[55].RAM32M0_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(334),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(334),
      O => \write_buffer.wr_buf_in_data\(334)
    );
\write_buffer.wr_buffer_ram[55].RAM32M0_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(333),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(333),
      O => \write_buffer.wr_buf_in_data\(333)
    );
\write_buffer.wr_buffer_ram[55].RAM32M0_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(332),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(332),
      O => \write_buffer.wr_buf_in_data\(332)
    );
\write_buffer.wr_buffer_ram[55].RAM32M0_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(331),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(331),
      O => \write_buffer.wr_buf_in_data\(331)
    );
\write_buffer.wr_buffer_ram[55].RAM32M0_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(330),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(330),
      O => \write_buffer.wr_buf_in_data\(330)
    );
\write_buffer.wr_buffer_ram[56].RAM32M0\: unisim.vcomponents.RAM32M
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      IS_WCLK_INVERTED => '0'
    )
        port map (
      ADDRA(4 downto 1) => wr_data_addr(3 downto 0),
      ADDRA(0) => '0',
      ADDRB(4 downto 1) => wr_data_addr(3 downto 0),
      ADDRB(0) => '0',
      ADDRC(4 downto 1) => wr_data_addr(3 downto 0),
      ADDRC(0) => '0',
      ADDRD(4 downto 1) => wb_wr_data_addr_w(4 downto 1),
      ADDRD(0) => \write_data_control.wb_wr_data_addr0_ns\,
      DIA(1 downto 0) => \write_buffer.wr_buf_in_data\(341 downto 340),
      DIB(1 downto 0) => \write_buffer.wr_buf_in_data\(339 downto 338),
      DIC(1 downto 0) => \write_buffer.wr_buf_in_data\(337 downto 336),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => wr_buf_out_data_w(341 downto 340),
      DOB(1 downto 0) => wr_buf_out_data_w(339 downto 338),
      DOC(1 downto 0) => wr_buf_out_data_w(337 downto 336),
      DOD(1 downto 0) => \NLW_write_buffer.wr_buffer_ram[56].RAM32M0_DOD_UNCONNECTED\(1 downto 0),
      WCLK => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      WE => wdf_rdy_ns
    );
\write_buffer.wr_buffer_ram[56].RAM32M0_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(341),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(341),
      O => \write_buffer.wr_buf_in_data\(341)
    );
\write_buffer.wr_buffer_ram[56].RAM32M0_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(340),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(340),
      O => \write_buffer.wr_buf_in_data\(340)
    );
\write_buffer.wr_buffer_ram[56].RAM32M0_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(339),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(339),
      O => \write_buffer.wr_buf_in_data\(339)
    );
\write_buffer.wr_buffer_ram[56].RAM32M0_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(338),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(338),
      O => \write_buffer.wr_buf_in_data\(338)
    );
\write_buffer.wr_buffer_ram[56].RAM32M0_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(337),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(337),
      O => \write_buffer.wr_buf_in_data\(337)
    );
\write_buffer.wr_buffer_ram[56].RAM32M0_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(336),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(336),
      O => \write_buffer.wr_buf_in_data\(336)
    );
\write_buffer.wr_buffer_ram[57].RAM32M0\: unisim.vcomponents.RAM32M
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      IS_WCLK_INVERTED => '0'
    )
        port map (
      ADDRA(4 downto 1) => wr_data_addr(3 downto 0),
      ADDRA(0) => '0',
      ADDRB(4 downto 1) => wr_data_addr(3 downto 0),
      ADDRB(0) => '0',
      ADDRC(4 downto 1) => wr_data_addr(3 downto 0),
      ADDRC(0) => '0',
      ADDRD(4 downto 1) => wb_wr_data_addr_w(4 downto 1),
      ADDRD(0) => \write_data_control.wb_wr_data_addr0_ns\,
      DIA(1 downto 0) => \write_buffer.wr_buf_in_data\(347 downto 346),
      DIB(1 downto 0) => \write_buffer.wr_buf_in_data\(345 downto 344),
      DIC(1 downto 0) => \write_buffer.wr_buf_in_data\(343 downto 342),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => wr_buf_out_data_w(347 downto 346),
      DOB(1 downto 0) => wr_buf_out_data_w(345 downto 344),
      DOC(1 downto 0) => wr_buf_out_data_w(343 downto 342),
      DOD(1 downto 0) => \NLW_write_buffer.wr_buffer_ram[57].RAM32M0_DOD_UNCONNECTED\(1 downto 0),
      WCLK => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      WE => wdf_rdy_ns
    );
\write_buffer.wr_buffer_ram[57].RAM32M0_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(347),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(347),
      O => \write_buffer.wr_buf_in_data\(347)
    );
\write_buffer.wr_buffer_ram[57].RAM32M0_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(346),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(346),
      O => \write_buffer.wr_buf_in_data\(346)
    );
\write_buffer.wr_buffer_ram[57].RAM32M0_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(345),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(345),
      O => \write_buffer.wr_buf_in_data\(345)
    );
\write_buffer.wr_buffer_ram[57].RAM32M0_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(344),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(344),
      O => \write_buffer.wr_buf_in_data\(344)
    );
\write_buffer.wr_buffer_ram[57].RAM32M0_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(343),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(343),
      O => \write_buffer.wr_buf_in_data\(343)
    );
\write_buffer.wr_buffer_ram[57].RAM32M0_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(342),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(342),
      O => \write_buffer.wr_buf_in_data\(342)
    );
\write_buffer.wr_buffer_ram[58].RAM32M0\: unisim.vcomponents.RAM32M
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      IS_WCLK_INVERTED => '0'
    )
        port map (
      ADDRA(4 downto 1) => wr_data_addr(3 downto 0),
      ADDRA(0) => '0',
      ADDRB(4 downto 1) => wr_data_addr(3 downto 0),
      ADDRB(0) => '0',
      ADDRC(4 downto 1) => wr_data_addr(3 downto 0),
      ADDRC(0) => '0',
      ADDRD(4 downto 1) => wb_wr_data_addr_w(4 downto 1),
      ADDRD(0) => \write_data_control.wb_wr_data_addr0_ns\,
      DIA(1 downto 0) => \write_buffer.wr_buf_in_data\(353 downto 352),
      DIB(1 downto 0) => \write_buffer.wr_buf_in_data\(351 downto 350),
      DIC(1 downto 0) => \write_buffer.wr_buf_in_data\(349 downto 348),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => wr_buf_out_data_w(353 downto 352),
      DOB(1 downto 0) => wr_buf_out_data_w(351 downto 350),
      DOC(1 downto 0) => wr_buf_out_data_w(349 downto 348),
      DOD(1 downto 0) => \NLW_write_buffer.wr_buffer_ram[58].RAM32M0_DOD_UNCONNECTED\(1 downto 0),
      WCLK => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      WE => wdf_rdy_ns
    );
\write_buffer.wr_buffer_ram[58].RAM32M0_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(353),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(353),
      O => \write_buffer.wr_buf_in_data\(353)
    );
\write_buffer.wr_buffer_ram[58].RAM32M0_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(352),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(352),
      O => \write_buffer.wr_buf_in_data\(352)
    );
\write_buffer.wr_buffer_ram[58].RAM32M0_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(351),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(351),
      O => \write_buffer.wr_buf_in_data\(351)
    );
\write_buffer.wr_buffer_ram[58].RAM32M0_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(350),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(350),
      O => \write_buffer.wr_buf_in_data\(350)
    );
\write_buffer.wr_buffer_ram[58].RAM32M0_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(349),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(349),
      O => \write_buffer.wr_buf_in_data\(349)
    );
\write_buffer.wr_buffer_ram[58].RAM32M0_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(348),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(348),
      O => \write_buffer.wr_buf_in_data\(348)
    );
\write_buffer.wr_buffer_ram[59].RAM32M0\: unisim.vcomponents.RAM32M
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      IS_WCLK_INVERTED => '0'
    )
        port map (
      ADDRA(4 downto 1) => wr_data_addr(3 downto 0),
      ADDRA(0) => '0',
      ADDRB(4 downto 1) => wr_data_addr(3 downto 0),
      ADDRB(0) => '0',
      ADDRC(4 downto 1) => wr_data_addr(3 downto 0),
      ADDRC(0) => '0',
      ADDRD(4 downto 1) => wb_wr_data_addr_w(4 downto 1),
      ADDRD(0) => \write_data_control.wb_wr_data_addr0_ns\,
      DIA(1 downto 0) => \write_buffer.wr_buf_in_data\(359 downto 358),
      DIB(1 downto 0) => \write_buffer.wr_buf_in_data\(357 downto 356),
      DIC(1 downto 0) => \write_buffer.wr_buf_in_data\(355 downto 354),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => wr_buf_out_data_w(359 downto 358),
      DOB(1 downto 0) => wr_buf_out_data_w(357 downto 356),
      DOC(1 downto 0) => wr_buf_out_data_w(355 downto 354),
      DOD(1 downto 0) => \NLW_write_buffer.wr_buffer_ram[59].RAM32M0_DOD_UNCONNECTED\(1 downto 0),
      WCLK => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      WE => wdf_rdy_ns
    );
\write_buffer.wr_buffer_ram[59].RAM32M0_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(359),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(359),
      O => \write_buffer.wr_buf_in_data\(359)
    );
\write_buffer.wr_buffer_ram[59].RAM32M0_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(358),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(358),
      O => \write_buffer.wr_buf_in_data\(358)
    );
\write_buffer.wr_buffer_ram[59].RAM32M0_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(357),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(357),
      O => \write_buffer.wr_buf_in_data\(357)
    );
\write_buffer.wr_buffer_ram[59].RAM32M0_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(356),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(356),
      O => \write_buffer.wr_buf_in_data\(356)
    );
\write_buffer.wr_buffer_ram[59].RAM32M0_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(355),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(355),
      O => \write_buffer.wr_buf_in_data\(355)
    );
\write_buffer.wr_buffer_ram[59].RAM32M0_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(354),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(354),
      O => \write_buffer.wr_buf_in_data\(354)
    );
\write_buffer.wr_buffer_ram[5].RAM32M0\: unisim.vcomponents.RAM32M
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      IS_WCLK_INVERTED => '0'
    )
        port map (
      ADDRA(4 downto 1) => wr_data_addr(3 downto 0),
      ADDRA(0) => '0',
      ADDRB(4 downto 1) => wr_data_addr(3 downto 0),
      ADDRB(0) => '0',
      ADDRC(4 downto 1) => wr_data_addr(3 downto 0),
      ADDRC(0) => '0',
      ADDRD(4 downto 1) => wb_wr_data_addr_w(4 downto 1),
      ADDRD(0) => \write_data_control.wb_wr_data_addr0_ns\,
      DIA(1 downto 0) => \write_buffer.wr_buf_in_data\(35 downto 34),
      DIB(1 downto 0) => \write_buffer.wr_buf_in_data\(33 downto 32),
      DIC(1 downto 0) => \write_buffer.wr_buf_in_data\(31 downto 30),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => wr_buf_out_data_w(35 downto 34),
      DOB(1 downto 0) => wr_buf_out_data_w(33 downto 32),
      DOC(1 downto 0) => wr_buf_out_data_w(31 downto 30),
      DOD(1 downto 0) => \NLW_write_buffer.wr_buffer_ram[5].RAM32M0_DOD_UNCONNECTED\(1 downto 0),
      WCLK => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      WE => wdf_rdy_ns
    );
\write_buffer.wr_buffer_ram[5].RAM32M0_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(35),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(35),
      O => \write_buffer.wr_buf_in_data\(35)
    );
\write_buffer.wr_buffer_ram[5].RAM32M0_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(34),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(34),
      O => \write_buffer.wr_buf_in_data\(34)
    );
\write_buffer.wr_buffer_ram[5].RAM32M0_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(33),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(33),
      O => \write_buffer.wr_buf_in_data\(33)
    );
\write_buffer.wr_buffer_ram[5].RAM32M0_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(32),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(32),
      O => \write_buffer.wr_buf_in_data\(32)
    );
\write_buffer.wr_buffer_ram[5].RAM32M0_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(31),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(31),
      O => \write_buffer.wr_buf_in_data\(31)
    );
\write_buffer.wr_buffer_ram[5].RAM32M0_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(30),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(30),
      O => \write_buffer.wr_buf_in_data\(30)
    );
\write_buffer.wr_buffer_ram[60].RAM32M0\: unisim.vcomponents.RAM32M
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      IS_WCLK_INVERTED => '0'
    )
        port map (
      ADDRA(4 downto 1) => wr_data_addr(3 downto 0),
      ADDRA(0) => '0',
      ADDRB(4 downto 1) => wr_data_addr(3 downto 0),
      ADDRB(0) => '0',
      ADDRC(4 downto 1) => wr_data_addr(3 downto 0),
      ADDRC(0) => '0',
      ADDRD(4 downto 1) => wb_wr_data_addr_w(4 downto 1),
      ADDRD(0) => \write_data_control.wb_wr_data_addr0_ns\,
      DIA(1 downto 0) => \write_buffer.wr_buf_in_data\(365 downto 364),
      DIB(1 downto 0) => \write_buffer.wr_buf_in_data\(363 downto 362),
      DIC(1 downto 0) => \write_buffer.wr_buf_in_data\(361 downto 360),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => wr_buf_out_data_w(365 downto 364),
      DOB(1 downto 0) => wr_buf_out_data_w(363 downto 362),
      DOC(1 downto 0) => wr_buf_out_data_w(361 downto 360),
      DOD(1 downto 0) => \NLW_write_buffer.wr_buffer_ram[60].RAM32M0_DOD_UNCONNECTED\(1 downto 0),
      WCLK => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      WE => wdf_rdy_ns
    );
\write_buffer.wr_buffer_ram[60].RAM32M0_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(365),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(365),
      O => \write_buffer.wr_buf_in_data\(365)
    );
\write_buffer.wr_buffer_ram[60].RAM32M0_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(364),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(364),
      O => \write_buffer.wr_buf_in_data\(364)
    );
\write_buffer.wr_buffer_ram[60].RAM32M0_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(363),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(363),
      O => \write_buffer.wr_buf_in_data\(363)
    );
\write_buffer.wr_buffer_ram[60].RAM32M0_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(362),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(362),
      O => \write_buffer.wr_buf_in_data\(362)
    );
\write_buffer.wr_buffer_ram[60].RAM32M0_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(361),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(361),
      O => \write_buffer.wr_buf_in_data\(361)
    );
\write_buffer.wr_buffer_ram[60].RAM32M0_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(360),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(360),
      O => \write_buffer.wr_buf_in_data\(360)
    );
\write_buffer.wr_buffer_ram[61].RAM32M0\: unisim.vcomponents.RAM32M
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      IS_WCLK_INVERTED => '0'
    )
        port map (
      ADDRA(4 downto 1) => wr_data_addr(3 downto 0),
      ADDRA(0) => '0',
      ADDRB(4 downto 1) => wr_data_addr(3 downto 0),
      ADDRB(0) => '0',
      ADDRC(4 downto 1) => wr_data_addr(3 downto 0),
      ADDRC(0) => '0',
      ADDRD(4 downto 1) => wb_wr_data_addr_w(4 downto 1),
      ADDRD(0) => \write_data_control.wb_wr_data_addr0_ns\,
      DIA(1 downto 0) => \write_buffer.wr_buf_in_data\(371 downto 370),
      DIB(1 downto 0) => \write_buffer.wr_buf_in_data\(369 downto 368),
      DIC(1 downto 0) => \write_buffer.wr_buf_in_data\(367 downto 366),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => wr_buf_out_data_w(371 downto 370),
      DOB(1 downto 0) => wr_buf_out_data_w(369 downto 368),
      DOC(1 downto 0) => wr_buf_out_data_w(367 downto 366),
      DOD(1 downto 0) => \NLW_write_buffer.wr_buffer_ram[61].RAM32M0_DOD_UNCONNECTED\(1 downto 0),
      WCLK => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      WE => wdf_rdy_ns
    );
\write_buffer.wr_buffer_ram[61].RAM32M0_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(371),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(371),
      O => \write_buffer.wr_buf_in_data\(371)
    );
\write_buffer.wr_buffer_ram[61].RAM32M0_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(370),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(370),
      O => \write_buffer.wr_buf_in_data\(370)
    );
\write_buffer.wr_buffer_ram[61].RAM32M0_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(369),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(369),
      O => \write_buffer.wr_buf_in_data\(369)
    );
\write_buffer.wr_buffer_ram[61].RAM32M0_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(368),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(368),
      O => \write_buffer.wr_buf_in_data\(368)
    );
\write_buffer.wr_buffer_ram[61].RAM32M0_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(367),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(367),
      O => \write_buffer.wr_buf_in_data\(367)
    );
\write_buffer.wr_buffer_ram[61].RAM32M0_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(366),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(366),
      O => \write_buffer.wr_buf_in_data\(366)
    );
\write_buffer.wr_buffer_ram[62].RAM32M0\: unisim.vcomponents.RAM32M
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      IS_WCLK_INVERTED => '0'
    )
        port map (
      ADDRA(4 downto 1) => wr_data_addr(3 downto 0),
      ADDRA(0) => '0',
      ADDRB(4 downto 1) => wr_data_addr(3 downto 0),
      ADDRB(0) => '0',
      ADDRC(4 downto 1) => wr_data_addr(3 downto 0),
      ADDRC(0) => '0',
      ADDRD(4 downto 1) => wb_wr_data_addr_w(4 downto 1),
      ADDRD(0) => \write_data_control.wb_wr_data_addr0_ns\,
      DIA(1 downto 0) => \write_buffer.wr_buf_in_data\(377 downto 376),
      DIB(1 downto 0) => \write_buffer.wr_buf_in_data\(375 downto 374),
      DIC(1 downto 0) => \write_buffer.wr_buf_in_data\(373 downto 372),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => wr_buf_out_data_w(377 downto 376),
      DOB(1 downto 0) => wr_buf_out_data_w(375 downto 374),
      DOC(1 downto 0) => wr_buf_out_data_w(373 downto 372),
      DOD(1 downto 0) => \NLW_write_buffer.wr_buffer_ram[62].RAM32M0_DOD_UNCONNECTED\(1 downto 0),
      WCLK => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      WE => wdf_rdy_ns
    );
\write_buffer.wr_buffer_ram[62].RAM32M0_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(377),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(377),
      O => \write_buffer.wr_buf_in_data\(377)
    );
\write_buffer.wr_buffer_ram[62].RAM32M0_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(376),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(376),
      O => \write_buffer.wr_buf_in_data\(376)
    );
\write_buffer.wr_buffer_ram[62].RAM32M0_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(375),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(375),
      O => \write_buffer.wr_buf_in_data\(375)
    );
\write_buffer.wr_buffer_ram[62].RAM32M0_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(374),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(374),
      O => \write_buffer.wr_buf_in_data\(374)
    );
\write_buffer.wr_buffer_ram[62].RAM32M0_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(373),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(373),
      O => \write_buffer.wr_buf_in_data\(373)
    );
\write_buffer.wr_buffer_ram[62].RAM32M0_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(372),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(372),
      O => \write_buffer.wr_buf_in_data\(372)
    );
\write_buffer.wr_buffer_ram[63].RAM32M0\: unisim.vcomponents.RAM32M
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      IS_WCLK_INVERTED => '0'
    )
        port map (
      ADDRA(4 downto 1) => wr_data_addr(3 downto 0),
      ADDRA(0) => '0',
      ADDRB(4 downto 1) => wr_data_addr(3 downto 0),
      ADDRB(0) => '0',
      ADDRC(4 downto 1) => wr_data_addr(3 downto 0),
      ADDRC(0) => '0',
      ADDRD(4 downto 1) => wb_wr_data_addr_w(4 downto 1),
      ADDRD(0) => \write_data_control.wb_wr_data_addr0_ns\,
      DIA(1 downto 0) => \write_buffer.wr_buf_in_data\(383 downto 382),
      DIB(1 downto 0) => \write_buffer.wr_buf_in_data\(381 downto 380),
      DIC(1 downto 0) => \write_buffer.wr_buf_in_data\(379 downto 378),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => wr_buf_out_data_w(383 downto 382),
      DOB(1 downto 0) => wr_buf_out_data_w(381 downto 380),
      DOC(1 downto 0) => wr_buf_out_data_w(379 downto 378),
      DOD(1 downto 0) => \NLW_write_buffer.wr_buffer_ram[63].RAM32M0_DOD_UNCONNECTED\(1 downto 0),
      WCLK => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      WE => wdf_rdy_ns
    );
\write_buffer.wr_buffer_ram[63].RAM32M0_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(383),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(383),
      O => \write_buffer.wr_buf_in_data\(383)
    );
\write_buffer.wr_buffer_ram[63].RAM32M0_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(382),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(382),
      O => \write_buffer.wr_buf_in_data\(382)
    );
\write_buffer.wr_buffer_ram[63].RAM32M0_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(381),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(381),
      O => \write_buffer.wr_buf_in_data\(381)
    );
\write_buffer.wr_buffer_ram[63].RAM32M0_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(380),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(380),
      O => \write_buffer.wr_buf_in_data\(380)
    );
\write_buffer.wr_buffer_ram[63].RAM32M0_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(379),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(379),
      O => \write_buffer.wr_buf_in_data\(379)
    );
\write_buffer.wr_buffer_ram[63].RAM32M0_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(378),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(378),
      O => \write_buffer.wr_buf_in_data\(378)
    );
\write_buffer.wr_buffer_ram[64].RAM32M0\: unisim.vcomponents.RAM32M
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      IS_WCLK_INVERTED => '0'
    )
        port map (
      ADDRA(4 downto 1) => wr_data_addr(3 downto 0),
      ADDRA(0) => '0',
      ADDRB(4 downto 1) => wr_data_addr(3 downto 0),
      ADDRB(0) => '0',
      ADDRC(4 downto 1) => wr_data_addr(3 downto 0),
      ADDRC(0) => '0',
      ADDRD(4 downto 1) => wb_wr_data_addr_w(4 downto 1),
      ADDRD(0) => \write_data_control.wb_wr_data_addr0_ns\,
      DIA(1 downto 0) => \write_buffer.wr_buf_in_data\(389 downto 388),
      DIB(1 downto 0) => \write_buffer.wr_buf_in_data\(387 downto 386),
      DIC(1 downto 0) => \write_buffer.wr_buf_in_data\(385 downto 384),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => wr_buf_out_data_w(389 downto 388),
      DOB(1 downto 0) => wr_buf_out_data_w(387 downto 386),
      DOC(1 downto 0) => wr_buf_out_data_w(385 downto 384),
      DOD(1 downto 0) => \NLW_write_buffer.wr_buffer_ram[64].RAM32M0_DOD_UNCONNECTED\(1 downto 0),
      WCLK => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      WE => wdf_rdy_ns
    );
\write_buffer.wr_buffer_ram[64].RAM32M0_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(389),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(389),
      O => \write_buffer.wr_buf_in_data\(389)
    );
\write_buffer.wr_buffer_ram[64].RAM32M0_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(388),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(388),
      O => \write_buffer.wr_buf_in_data\(388)
    );
\write_buffer.wr_buffer_ram[64].RAM32M0_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(387),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(387),
      O => \write_buffer.wr_buf_in_data\(387)
    );
\write_buffer.wr_buffer_ram[64].RAM32M0_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(386),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(386),
      O => \write_buffer.wr_buf_in_data\(386)
    );
\write_buffer.wr_buffer_ram[64].RAM32M0_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(385),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(385),
      O => \write_buffer.wr_buf_in_data\(385)
    );
\write_buffer.wr_buffer_ram[64].RAM32M0_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(384),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(384),
      O => \write_buffer.wr_buf_in_data\(384)
    );
\write_buffer.wr_buffer_ram[65].RAM32M0\: unisim.vcomponents.RAM32M
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      IS_WCLK_INVERTED => '0'
    )
        port map (
      ADDRA(4 downto 1) => wr_data_addr(3 downto 0),
      ADDRA(0) => '0',
      ADDRB(4 downto 1) => wr_data_addr(3 downto 0),
      ADDRB(0) => '0',
      ADDRC(4 downto 1) => wr_data_addr(3 downto 0),
      ADDRC(0) => '0',
      ADDRD(4 downto 1) => wb_wr_data_addr_w(4 downto 1),
      ADDRD(0) => \write_data_control.wb_wr_data_addr0_ns\,
      DIA(1 downto 0) => \write_buffer.wr_buf_in_data\(395 downto 394),
      DIB(1 downto 0) => \write_buffer.wr_buf_in_data\(393 downto 392),
      DIC(1 downto 0) => \write_buffer.wr_buf_in_data\(391 downto 390),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => wr_buf_out_data_w(395 downto 394),
      DOB(1 downto 0) => wr_buf_out_data_w(393 downto 392),
      DOC(1 downto 0) => wr_buf_out_data_w(391 downto 390),
      DOD(1 downto 0) => \NLW_write_buffer.wr_buffer_ram[65].RAM32M0_DOD_UNCONNECTED\(1 downto 0),
      WCLK => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      WE => wdf_rdy_ns
    );
\write_buffer.wr_buffer_ram[65].RAM32M0_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(395),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(395),
      O => \write_buffer.wr_buf_in_data\(395)
    );
\write_buffer.wr_buffer_ram[65].RAM32M0_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(394),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(394),
      O => \write_buffer.wr_buf_in_data\(394)
    );
\write_buffer.wr_buffer_ram[65].RAM32M0_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(393),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(393),
      O => \write_buffer.wr_buf_in_data\(393)
    );
\write_buffer.wr_buffer_ram[65].RAM32M0_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(392),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(392),
      O => \write_buffer.wr_buf_in_data\(392)
    );
\write_buffer.wr_buffer_ram[65].RAM32M0_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(391),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(391),
      O => \write_buffer.wr_buf_in_data\(391)
    );
\write_buffer.wr_buffer_ram[65].RAM32M0_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(390),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(390),
      O => \write_buffer.wr_buf_in_data\(390)
    );
\write_buffer.wr_buffer_ram[66].RAM32M0\: unisim.vcomponents.RAM32M
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      IS_WCLK_INVERTED => '0'
    )
        port map (
      ADDRA(4 downto 1) => wr_data_addr(3 downto 0),
      ADDRA(0) => '0',
      ADDRB(4 downto 1) => wr_data_addr(3 downto 0),
      ADDRB(0) => '0',
      ADDRC(4 downto 1) => wr_data_addr(3 downto 0),
      ADDRC(0) => '0',
      ADDRD(4 downto 1) => wb_wr_data_addr_w(4 downto 1),
      ADDRD(0) => \write_data_control.wb_wr_data_addr0_ns\,
      DIA(1 downto 0) => \write_buffer.wr_buf_in_data\(401 downto 400),
      DIB(1 downto 0) => \write_buffer.wr_buf_in_data\(399 downto 398),
      DIC(1 downto 0) => \write_buffer.wr_buf_in_data\(397 downto 396),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => wr_buf_out_data_w(401 downto 400),
      DOB(1 downto 0) => wr_buf_out_data_w(399 downto 398),
      DOC(1 downto 0) => wr_buf_out_data_w(397 downto 396),
      DOD(1 downto 0) => \NLW_write_buffer.wr_buffer_ram[66].RAM32M0_DOD_UNCONNECTED\(1 downto 0),
      WCLK => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      WE => wdf_rdy_ns
    );
\write_buffer.wr_buffer_ram[66].RAM32M0_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(401),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(401),
      O => \write_buffer.wr_buf_in_data\(401)
    );
\write_buffer.wr_buffer_ram[66].RAM32M0_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(400),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(400),
      O => \write_buffer.wr_buf_in_data\(400)
    );
\write_buffer.wr_buffer_ram[66].RAM32M0_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(399),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(399),
      O => \write_buffer.wr_buf_in_data\(399)
    );
\write_buffer.wr_buffer_ram[66].RAM32M0_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(398),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(398),
      O => \write_buffer.wr_buf_in_data\(398)
    );
\write_buffer.wr_buffer_ram[66].RAM32M0_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(397),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(397),
      O => \write_buffer.wr_buf_in_data\(397)
    );
\write_buffer.wr_buffer_ram[66].RAM32M0_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(396),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(396),
      O => \write_buffer.wr_buf_in_data\(396)
    );
\write_buffer.wr_buffer_ram[67].RAM32M0\: unisim.vcomponents.RAM32M
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      IS_WCLK_INVERTED => '0'
    )
        port map (
      ADDRA(4 downto 1) => wr_data_addr(3 downto 0),
      ADDRA(0) => '0',
      ADDRB(4 downto 1) => wr_data_addr(3 downto 0),
      ADDRB(0) => '0',
      ADDRC(4 downto 1) => wr_data_addr(3 downto 0),
      ADDRC(0) => '0',
      ADDRD(4 downto 1) => wb_wr_data_addr_w(4 downto 1),
      ADDRD(0) => \write_data_control.wb_wr_data_addr0_ns\,
      DIA(1 downto 0) => \write_buffer.wr_buf_in_data\(407 downto 406),
      DIB(1 downto 0) => \write_buffer.wr_buf_in_data\(405 downto 404),
      DIC(1 downto 0) => \write_buffer.wr_buf_in_data\(403 downto 402),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => wr_buf_out_data_w(407 downto 406),
      DOB(1 downto 0) => wr_buf_out_data_w(405 downto 404),
      DOC(1 downto 0) => wr_buf_out_data_w(403 downto 402),
      DOD(1 downto 0) => \NLW_write_buffer.wr_buffer_ram[67].RAM32M0_DOD_UNCONNECTED\(1 downto 0),
      WCLK => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      WE => wdf_rdy_ns
    );
\write_buffer.wr_buffer_ram[67].RAM32M0_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(407),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(407),
      O => \write_buffer.wr_buf_in_data\(407)
    );
\write_buffer.wr_buffer_ram[67].RAM32M0_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(406),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(406),
      O => \write_buffer.wr_buf_in_data\(406)
    );
\write_buffer.wr_buffer_ram[67].RAM32M0_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(405),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(405),
      O => \write_buffer.wr_buf_in_data\(405)
    );
\write_buffer.wr_buffer_ram[67].RAM32M0_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(404),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(404),
      O => \write_buffer.wr_buf_in_data\(404)
    );
\write_buffer.wr_buffer_ram[67].RAM32M0_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(403),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(403),
      O => \write_buffer.wr_buf_in_data\(403)
    );
\write_buffer.wr_buffer_ram[67].RAM32M0_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(402),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(402),
      O => \write_buffer.wr_buf_in_data\(402)
    );
\write_buffer.wr_buffer_ram[68].RAM32M0\: unisim.vcomponents.RAM32M
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      IS_WCLK_INVERTED => '0'
    )
        port map (
      ADDRA(4 downto 1) => wr_data_addr(3 downto 0),
      ADDRA(0) => '0',
      ADDRB(4 downto 1) => wr_data_addr(3 downto 0),
      ADDRB(0) => '0',
      ADDRC(4 downto 1) => wr_data_addr(3 downto 0),
      ADDRC(0) => '0',
      ADDRD(4 downto 1) => wb_wr_data_addr_w(4 downto 1),
      ADDRD(0) => \write_data_control.wb_wr_data_addr0_ns\,
      DIA(1 downto 0) => \write_buffer.wr_buf_in_data\(413 downto 412),
      DIB(1 downto 0) => \write_buffer.wr_buf_in_data\(411 downto 410),
      DIC(1 downto 0) => \write_buffer.wr_buf_in_data\(409 downto 408),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => wr_buf_out_data_w(413 downto 412),
      DOB(1 downto 0) => wr_buf_out_data_w(411 downto 410),
      DOC(1 downto 0) => wr_buf_out_data_w(409 downto 408),
      DOD(1 downto 0) => \NLW_write_buffer.wr_buffer_ram[68].RAM32M0_DOD_UNCONNECTED\(1 downto 0),
      WCLK => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      WE => wdf_rdy_ns
    );
\write_buffer.wr_buffer_ram[68].RAM32M0_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(413),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(413),
      O => \write_buffer.wr_buf_in_data\(413)
    );
\write_buffer.wr_buffer_ram[68].RAM32M0_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(412),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(412),
      O => \write_buffer.wr_buf_in_data\(412)
    );
\write_buffer.wr_buffer_ram[68].RAM32M0_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(411),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(411),
      O => \write_buffer.wr_buf_in_data\(411)
    );
\write_buffer.wr_buffer_ram[68].RAM32M0_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(410),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(410),
      O => \write_buffer.wr_buf_in_data\(410)
    );
\write_buffer.wr_buffer_ram[68].RAM32M0_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(409),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(409),
      O => \write_buffer.wr_buf_in_data\(409)
    );
\write_buffer.wr_buffer_ram[68].RAM32M0_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(408),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(408),
      O => \write_buffer.wr_buf_in_data\(408)
    );
\write_buffer.wr_buffer_ram[69].RAM32M0\: unisim.vcomponents.RAM32M
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      IS_WCLK_INVERTED => '0'
    )
        port map (
      ADDRA(4 downto 1) => wr_data_addr(3 downto 0),
      ADDRA(0) => '0',
      ADDRB(4 downto 1) => wr_data_addr(3 downto 0),
      ADDRB(0) => '0',
      ADDRC(4 downto 1) => wr_data_addr(3 downto 0),
      ADDRC(0) => '0',
      ADDRD(4 downto 1) => wb_wr_data_addr_w(4 downto 1),
      ADDRD(0) => \write_data_control.wb_wr_data_addr0_ns\,
      DIA(1 downto 0) => \write_buffer.wr_buf_in_data\(419 downto 418),
      DIB(1 downto 0) => \write_buffer.wr_buf_in_data\(417 downto 416),
      DIC(1 downto 0) => \write_buffer.wr_buf_in_data\(415 downto 414),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => wr_buf_out_data_w(419 downto 418),
      DOB(1 downto 0) => wr_buf_out_data_w(417 downto 416),
      DOC(1 downto 0) => wr_buf_out_data_w(415 downto 414),
      DOD(1 downto 0) => \NLW_write_buffer.wr_buffer_ram[69].RAM32M0_DOD_UNCONNECTED\(1 downto 0),
      WCLK => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      WE => wdf_rdy_ns
    );
\write_buffer.wr_buffer_ram[69].RAM32M0_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(419),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(419),
      O => \write_buffer.wr_buf_in_data\(419)
    );
\write_buffer.wr_buffer_ram[69].RAM32M0_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(418),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(418),
      O => \write_buffer.wr_buf_in_data\(418)
    );
\write_buffer.wr_buffer_ram[69].RAM32M0_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(417),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(417),
      O => \write_buffer.wr_buf_in_data\(417)
    );
\write_buffer.wr_buffer_ram[69].RAM32M0_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(416),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(416),
      O => \write_buffer.wr_buf_in_data\(416)
    );
\write_buffer.wr_buffer_ram[69].RAM32M0_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(415),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(415),
      O => \write_buffer.wr_buf_in_data\(415)
    );
\write_buffer.wr_buffer_ram[69].RAM32M0_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(414),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(414),
      O => \write_buffer.wr_buf_in_data\(414)
    );
\write_buffer.wr_buffer_ram[6].RAM32M0\: unisim.vcomponents.RAM32M
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      IS_WCLK_INVERTED => '0'
    )
        port map (
      ADDRA(4 downto 1) => wr_data_addr(3 downto 0),
      ADDRA(0) => '0',
      ADDRB(4 downto 1) => wr_data_addr(3 downto 0),
      ADDRB(0) => '0',
      ADDRC(4 downto 1) => wr_data_addr(3 downto 0),
      ADDRC(0) => '0',
      ADDRD(4 downto 1) => wb_wr_data_addr_w(4 downto 1),
      ADDRD(0) => \write_data_control.wb_wr_data_addr0_ns\,
      DIA(1 downto 0) => \write_buffer.wr_buf_in_data\(41 downto 40),
      DIB(1 downto 0) => \write_buffer.wr_buf_in_data\(39 downto 38),
      DIC(1 downto 0) => \write_buffer.wr_buf_in_data\(37 downto 36),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => wr_buf_out_data_w(41 downto 40),
      DOB(1 downto 0) => wr_buf_out_data_w(39 downto 38),
      DOC(1 downto 0) => wr_buf_out_data_w(37 downto 36),
      DOD(1 downto 0) => \NLW_write_buffer.wr_buffer_ram[6].RAM32M0_DOD_UNCONNECTED\(1 downto 0),
      WCLK => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      WE => wdf_rdy_ns
    );
\write_buffer.wr_buffer_ram[6].RAM32M0_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(41),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(41),
      O => \write_buffer.wr_buf_in_data\(41)
    );
\write_buffer.wr_buffer_ram[6].RAM32M0_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(40),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(40),
      O => \write_buffer.wr_buf_in_data\(40)
    );
\write_buffer.wr_buffer_ram[6].RAM32M0_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(39),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(39),
      O => \write_buffer.wr_buf_in_data\(39)
    );
\write_buffer.wr_buffer_ram[6].RAM32M0_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(38),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(38),
      O => \write_buffer.wr_buf_in_data\(38)
    );
\write_buffer.wr_buffer_ram[6].RAM32M0_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(37),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(37),
      O => \write_buffer.wr_buf_in_data\(37)
    );
\write_buffer.wr_buffer_ram[6].RAM32M0_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(36),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(36),
      O => \write_buffer.wr_buf_in_data\(36)
    );
\write_buffer.wr_buffer_ram[70].RAM32M0\: unisim.vcomponents.RAM32M
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      IS_WCLK_INVERTED => '0'
    )
        port map (
      ADDRA(4 downto 1) => wr_data_addr(3 downto 0),
      ADDRA(0) => '0',
      ADDRB(4 downto 1) => wr_data_addr(3 downto 0),
      ADDRB(0) => '0',
      ADDRC(4 downto 1) => wr_data_addr(3 downto 0),
      ADDRC(0) => '0',
      ADDRD(4 downto 1) => wb_wr_data_addr_w(4 downto 1),
      ADDRD(0) => \write_data_control.wb_wr_data_addr0_ns\,
      DIA(1 downto 0) => \write_buffer.wr_buf_in_data\(425 downto 424),
      DIB(1 downto 0) => \write_buffer.wr_buf_in_data\(423 downto 422),
      DIC(1 downto 0) => \write_buffer.wr_buf_in_data\(421 downto 420),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => wr_buf_out_data_w(425 downto 424),
      DOB(1 downto 0) => wr_buf_out_data_w(423 downto 422),
      DOC(1 downto 0) => wr_buf_out_data_w(421 downto 420),
      DOD(1 downto 0) => \NLW_write_buffer.wr_buffer_ram[70].RAM32M0_DOD_UNCONNECTED\(1 downto 0),
      WCLK => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      WE => wdf_rdy_ns
    );
\write_buffer.wr_buffer_ram[70].RAM32M0_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(425),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(425),
      O => \write_buffer.wr_buf_in_data\(425)
    );
\write_buffer.wr_buffer_ram[70].RAM32M0_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(424),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(424),
      O => \write_buffer.wr_buf_in_data\(424)
    );
\write_buffer.wr_buffer_ram[70].RAM32M0_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(423),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(423),
      O => \write_buffer.wr_buf_in_data\(423)
    );
\write_buffer.wr_buffer_ram[70].RAM32M0_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(422),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(422),
      O => \write_buffer.wr_buf_in_data\(422)
    );
\write_buffer.wr_buffer_ram[70].RAM32M0_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(421),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(421),
      O => \write_buffer.wr_buf_in_data\(421)
    );
\write_buffer.wr_buffer_ram[70].RAM32M0_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(420),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(420),
      O => \write_buffer.wr_buf_in_data\(420)
    );
\write_buffer.wr_buffer_ram[71].RAM32M0\: unisim.vcomponents.RAM32M
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      IS_WCLK_INVERTED => '0'
    )
        port map (
      ADDRA(4 downto 1) => wr_data_addr(3 downto 0),
      ADDRA(0) => '0',
      ADDRB(4 downto 1) => wr_data_addr(3 downto 0),
      ADDRB(0) => '0',
      ADDRC(4 downto 1) => wr_data_addr(3 downto 0),
      ADDRC(0) => '0',
      ADDRD(4 downto 1) => wb_wr_data_addr_w(4 downto 1),
      ADDRD(0) => \write_data_control.wb_wr_data_addr0_ns\,
      DIA(1 downto 0) => \write_buffer.wr_buf_in_data\(431 downto 430),
      DIB(1 downto 0) => \write_buffer.wr_buf_in_data\(429 downto 428),
      DIC(1 downto 0) => \write_buffer.wr_buf_in_data\(427 downto 426),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => wr_buf_out_data_w(431 downto 430),
      DOB(1 downto 0) => wr_buf_out_data_w(429 downto 428),
      DOC(1 downto 0) => wr_buf_out_data_w(427 downto 426),
      DOD(1 downto 0) => \NLW_write_buffer.wr_buffer_ram[71].RAM32M0_DOD_UNCONNECTED\(1 downto 0),
      WCLK => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      WE => wdf_rdy_ns
    );
\write_buffer.wr_buffer_ram[71].RAM32M0_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(431),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(431),
      O => \write_buffer.wr_buf_in_data\(431)
    );
\write_buffer.wr_buffer_ram[71].RAM32M0_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(430),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(430),
      O => \write_buffer.wr_buf_in_data\(430)
    );
\write_buffer.wr_buffer_ram[71].RAM32M0_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(429),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(429),
      O => \write_buffer.wr_buf_in_data\(429)
    );
\write_buffer.wr_buffer_ram[71].RAM32M0_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(428),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(428),
      O => \write_buffer.wr_buf_in_data\(428)
    );
\write_buffer.wr_buffer_ram[71].RAM32M0_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(427),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(427),
      O => \write_buffer.wr_buf_in_data\(427)
    );
\write_buffer.wr_buffer_ram[71].RAM32M0_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(426),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(426),
      O => \write_buffer.wr_buf_in_data\(426)
    );
\write_buffer.wr_buffer_ram[72].RAM32M0\: unisim.vcomponents.RAM32M
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      IS_WCLK_INVERTED => '0'
    )
        port map (
      ADDRA(4 downto 1) => wr_data_addr(3 downto 0),
      ADDRA(0) => '0',
      ADDRB(4 downto 1) => wr_data_addr(3 downto 0),
      ADDRB(0) => '0',
      ADDRC(4 downto 1) => wr_data_addr(3 downto 0),
      ADDRC(0) => '0',
      ADDRD(4 downto 1) => wb_wr_data_addr_w(4 downto 1),
      ADDRD(0) => \write_data_control.wb_wr_data_addr0_ns\,
      DIA(1 downto 0) => \write_buffer.wr_buf_in_data\(437 downto 436),
      DIB(1 downto 0) => \write_buffer.wr_buf_in_data\(435 downto 434),
      DIC(1 downto 0) => \write_buffer.wr_buf_in_data\(433 downto 432),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => wr_buf_out_data_w(437 downto 436),
      DOB(1 downto 0) => wr_buf_out_data_w(435 downto 434),
      DOC(1 downto 0) => wr_buf_out_data_w(433 downto 432),
      DOD(1 downto 0) => \NLW_write_buffer.wr_buffer_ram[72].RAM32M0_DOD_UNCONNECTED\(1 downto 0),
      WCLK => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      WE => wdf_rdy_ns
    );
\write_buffer.wr_buffer_ram[72].RAM32M0_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(437),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(437),
      O => \write_buffer.wr_buf_in_data\(437)
    );
\write_buffer.wr_buffer_ram[72].RAM32M0_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(436),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(436),
      O => \write_buffer.wr_buf_in_data\(436)
    );
\write_buffer.wr_buffer_ram[72].RAM32M0_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(435),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(435),
      O => \write_buffer.wr_buf_in_data\(435)
    );
\write_buffer.wr_buffer_ram[72].RAM32M0_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(434),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(434),
      O => \write_buffer.wr_buf_in_data\(434)
    );
\write_buffer.wr_buffer_ram[72].RAM32M0_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(433),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(433),
      O => \write_buffer.wr_buf_in_data\(433)
    );
\write_buffer.wr_buffer_ram[72].RAM32M0_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(432),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(432),
      O => \write_buffer.wr_buf_in_data\(432)
    );
\write_buffer.wr_buffer_ram[73].RAM32M0\: unisim.vcomponents.RAM32M
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      IS_WCLK_INVERTED => '0'
    )
        port map (
      ADDRA(4 downto 1) => wr_data_addr(3 downto 0),
      ADDRA(0) => '0',
      ADDRB(4 downto 1) => wr_data_addr(3 downto 0),
      ADDRB(0) => '0',
      ADDRC(4 downto 1) => wr_data_addr(3 downto 0),
      ADDRC(0) => '0',
      ADDRD(4 downto 1) => wb_wr_data_addr_w(4 downto 1),
      ADDRD(0) => \write_data_control.wb_wr_data_addr0_ns\,
      DIA(1 downto 0) => \write_buffer.wr_buf_in_data\(443 downto 442),
      DIB(1 downto 0) => \write_buffer.wr_buf_in_data\(441 downto 440),
      DIC(1 downto 0) => \write_buffer.wr_buf_in_data\(439 downto 438),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => wr_buf_out_data_w(443 downto 442),
      DOB(1 downto 0) => wr_buf_out_data_w(441 downto 440),
      DOC(1 downto 0) => wr_buf_out_data_w(439 downto 438),
      DOD(1 downto 0) => \NLW_write_buffer.wr_buffer_ram[73].RAM32M0_DOD_UNCONNECTED\(1 downto 0),
      WCLK => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      WE => wdf_rdy_ns
    );
\write_buffer.wr_buffer_ram[73].RAM32M0_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(443),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(443),
      O => \write_buffer.wr_buf_in_data\(443)
    );
\write_buffer.wr_buffer_ram[73].RAM32M0_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(442),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(442),
      O => \write_buffer.wr_buf_in_data\(442)
    );
\write_buffer.wr_buffer_ram[73].RAM32M0_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(441),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(441),
      O => \write_buffer.wr_buf_in_data\(441)
    );
\write_buffer.wr_buffer_ram[73].RAM32M0_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(440),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(440),
      O => \write_buffer.wr_buf_in_data\(440)
    );
\write_buffer.wr_buffer_ram[73].RAM32M0_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(439),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(439),
      O => \write_buffer.wr_buf_in_data\(439)
    );
\write_buffer.wr_buffer_ram[73].RAM32M0_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(438),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(438),
      O => \write_buffer.wr_buf_in_data\(438)
    );
\write_buffer.wr_buffer_ram[74].RAM32M0\: unisim.vcomponents.RAM32M
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      IS_WCLK_INVERTED => '0'
    )
        port map (
      ADDRA(4 downto 1) => wr_data_addr(3 downto 0),
      ADDRA(0) => '0',
      ADDRB(4 downto 1) => wr_data_addr(3 downto 0),
      ADDRB(0) => '0',
      ADDRC(4 downto 1) => wr_data_addr(3 downto 0),
      ADDRC(0) => '0',
      ADDRD(4 downto 1) => wb_wr_data_addr_w(4 downto 1),
      ADDRD(0) => \write_data_control.wb_wr_data_addr0_ns\,
      DIA(1 downto 0) => \write_buffer.wr_buf_in_data\(449 downto 448),
      DIB(1 downto 0) => \write_buffer.wr_buf_in_data\(447 downto 446),
      DIC(1 downto 0) => \write_buffer.wr_buf_in_data\(445 downto 444),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => wr_buf_out_data_w(449 downto 448),
      DOB(1 downto 0) => wr_buf_out_data_w(447 downto 446),
      DOC(1 downto 0) => wr_buf_out_data_w(445 downto 444),
      DOD(1 downto 0) => \NLW_write_buffer.wr_buffer_ram[74].RAM32M0_DOD_UNCONNECTED\(1 downto 0),
      WCLK => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      WE => wdf_rdy_ns
    );
\write_buffer.wr_buffer_ram[74].RAM32M0_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(449),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(449),
      O => \write_buffer.wr_buf_in_data\(449)
    );
\write_buffer.wr_buffer_ram[74].RAM32M0_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(448),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(448),
      O => \write_buffer.wr_buf_in_data\(448)
    );
\write_buffer.wr_buffer_ram[74].RAM32M0_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(447),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(447),
      O => \write_buffer.wr_buf_in_data\(447)
    );
\write_buffer.wr_buffer_ram[74].RAM32M0_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(446),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(446),
      O => \write_buffer.wr_buf_in_data\(446)
    );
\write_buffer.wr_buffer_ram[74].RAM32M0_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(445),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(445),
      O => \write_buffer.wr_buf_in_data\(445)
    );
\write_buffer.wr_buffer_ram[74].RAM32M0_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(444),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(444),
      O => \write_buffer.wr_buf_in_data\(444)
    );
\write_buffer.wr_buffer_ram[75].RAM32M0\: unisim.vcomponents.RAM32M
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      IS_WCLK_INVERTED => '0'
    )
        port map (
      ADDRA(4 downto 1) => wr_data_addr(3 downto 0),
      ADDRA(0) => '0',
      ADDRB(4 downto 1) => wr_data_addr(3 downto 0),
      ADDRB(0) => '0',
      ADDRC(4 downto 1) => wr_data_addr(3 downto 0),
      ADDRC(0) => '0',
      ADDRD(4 downto 1) => wb_wr_data_addr_w(4 downto 1),
      ADDRD(0) => \write_data_control.wb_wr_data_addr0_ns\,
      DIA(1 downto 0) => \write_buffer.wr_buf_in_data\(455 downto 454),
      DIB(1 downto 0) => \write_buffer.wr_buf_in_data\(453 downto 452),
      DIC(1 downto 0) => \write_buffer.wr_buf_in_data\(451 downto 450),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => wr_buf_out_data_w(455 downto 454),
      DOB(1 downto 0) => wr_buf_out_data_w(453 downto 452),
      DOC(1 downto 0) => wr_buf_out_data_w(451 downto 450),
      DOD(1 downto 0) => \NLW_write_buffer.wr_buffer_ram[75].RAM32M0_DOD_UNCONNECTED\(1 downto 0),
      WCLK => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      WE => wdf_rdy_ns
    );
\write_buffer.wr_buffer_ram[75].RAM32M0_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(455),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(455),
      O => \write_buffer.wr_buf_in_data\(455)
    );
\write_buffer.wr_buffer_ram[75].RAM32M0_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(454),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(454),
      O => \write_buffer.wr_buf_in_data\(454)
    );
\write_buffer.wr_buffer_ram[75].RAM32M0_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(453),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(453),
      O => \write_buffer.wr_buf_in_data\(453)
    );
\write_buffer.wr_buffer_ram[75].RAM32M0_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(452),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(452),
      O => \write_buffer.wr_buf_in_data\(452)
    );
\write_buffer.wr_buffer_ram[75].RAM32M0_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(451),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(451),
      O => \write_buffer.wr_buf_in_data\(451)
    );
\write_buffer.wr_buffer_ram[75].RAM32M0_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(450),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(450),
      O => \write_buffer.wr_buf_in_data\(450)
    );
\write_buffer.wr_buffer_ram[76].RAM32M0\: unisim.vcomponents.RAM32M
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      IS_WCLK_INVERTED => '0'
    )
        port map (
      ADDRA(4 downto 1) => wr_data_addr(3 downto 0),
      ADDRA(0) => '0',
      ADDRB(4 downto 1) => wr_data_addr(3 downto 0),
      ADDRB(0) => '0',
      ADDRC(4 downto 1) => wr_data_addr(3 downto 0),
      ADDRC(0) => '0',
      ADDRD(4 downto 1) => wb_wr_data_addr_w(4 downto 1),
      ADDRD(0) => \write_data_control.wb_wr_data_addr0_ns\,
      DIA(1 downto 0) => \write_buffer.wr_buf_in_data\(461 downto 460),
      DIB(1 downto 0) => \write_buffer.wr_buf_in_data\(459 downto 458),
      DIC(1 downto 0) => \write_buffer.wr_buf_in_data\(457 downto 456),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => wr_buf_out_data_w(461 downto 460),
      DOB(1 downto 0) => wr_buf_out_data_w(459 downto 458),
      DOC(1 downto 0) => wr_buf_out_data_w(457 downto 456),
      DOD(1 downto 0) => \NLW_write_buffer.wr_buffer_ram[76].RAM32M0_DOD_UNCONNECTED\(1 downto 0),
      WCLK => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      WE => wdf_rdy_ns
    );
\write_buffer.wr_buffer_ram[76].RAM32M0_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(461),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(461),
      O => \write_buffer.wr_buf_in_data\(461)
    );
\write_buffer.wr_buffer_ram[76].RAM32M0_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(460),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(460),
      O => \write_buffer.wr_buf_in_data\(460)
    );
\write_buffer.wr_buffer_ram[76].RAM32M0_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(459),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(459),
      O => \write_buffer.wr_buf_in_data\(459)
    );
\write_buffer.wr_buffer_ram[76].RAM32M0_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(458),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(458),
      O => \write_buffer.wr_buf_in_data\(458)
    );
\write_buffer.wr_buffer_ram[76].RAM32M0_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(457),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(457),
      O => \write_buffer.wr_buf_in_data\(457)
    );
\write_buffer.wr_buffer_ram[76].RAM32M0_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(456),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(456),
      O => \write_buffer.wr_buf_in_data\(456)
    );
\write_buffer.wr_buffer_ram[77].RAM32M0\: unisim.vcomponents.RAM32M
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      IS_WCLK_INVERTED => '0'
    )
        port map (
      ADDRA(4 downto 1) => wr_data_addr(3 downto 0),
      ADDRA(0) => '0',
      ADDRB(4 downto 1) => wr_data_addr(3 downto 0),
      ADDRB(0) => '0',
      ADDRC(4 downto 1) => wr_data_addr(3 downto 0),
      ADDRC(0) => '0',
      ADDRD(4 downto 1) => wb_wr_data_addr_w(4 downto 1),
      ADDRD(0) => \write_data_control.wb_wr_data_addr0_ns\,
      DIA(1 downto 0) => \write_buffer.wr_buf_in_data\(467 downto 466),
      DIB(1 downto 0) => \write_buffer.wr_buf_in_data\(465 downto 464),
      DIC(1 downto 0) => \write_buffer.wr_buf_in_data\(463 downto 462),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => wr_buf_out_data_w(467 downto 466),
      DOB(1 downto 0) => wr_buf_out_data_w(465 downto 464),
      DOC(1 downto 0) => wr_buf_out_data_w(463 downto 462),
      DOD(1 downto 0) => \NLW_write_buffer.wr_buffer_ram[77].RAM32M0_DOD_UNCONNECTED\(1 downto 0),
      WCLK => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      WE => wdf_rdy_ns
    );
\write_buffer.wr_buffer_ram[77].RAM32M0_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(467),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(467),
      O => \write_buffer.wr_buf_in_data\(467)
    );
\write_buffer.wr_buffer_ram[77].RAM32M0_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(466),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(466),
      O => \write_buffer.wr_buf_in_data\(466)
    );
\write_buffer.wr_buffer_ram[77].RAM32M0_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(465),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(465),
      O => \write_buffer.wr_buf_in_data\(465)
    );
\write_buffer.wr_buffer_ram[77].RAM32M0_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(464),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(464),
      O => \write_buffer.wr_buf_in_data\(464)
    );
\write_buffer.wr_buffer_ram[77].RAM32M0_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(463),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(463),
      O => \write_buffer.wr_buf_in_data\(463)
    );
\write_buffer.wr_buffer_ram[77].RAM32M0_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(462),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(462),
      O => \write_buffer.wr_buf_in_data\(462)
    );
\write_buffer.wr_buffer_ram[78].RAM32M0\: unisim.vcomponents.RAM32M
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      IS_WCLK_INVERTED => '0'
    )
        port map (
      ADDRA(4 downto 1) => wr_data_addr(3 downto 0),
      ADDRA(0) => '0',
      ADDRB(4 downto 1) => wr_data_addr(3 downto 0),
      ADDRB(0) => '0',
      ADDRC(4 downto 1) => wr_data_addr(3 downto 0),
      ADDRC(0) => '0',
      ADDRD(4 downto 1) => wb_wr_data_addr_w(4 downto 1),
      ADDRD(0) => \write_data_control.wb_wr_data_addr0_ns\,
      DIA(1 downto 0) => \write_buffer.wr_buf_in_data\(473 downto 472),
      DIB(1 downto 0) => \write_buffer.wr_buf_in_data\(471 downto 470),
      DIC(1 downto 0) => \write_buffer.wr_buf_in_data\(469 downto 468),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => wr_buf_out_data_w(473 downto 472),
      DOB(1 downto 0) => wr_buf_out_data_w(471 downto 470),
      DOC(1 downto 0) => wr_buf_out_data_w(469 downto 468),
      DOD(1 downto 0) => \NLW_write_buffer.wr_buffer_ram[78].RAM32M0_DOD_UNCONNECTED\(1 downto 0),
      WCLK => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      WE => wdf_rdy_ns
    );
\write_buffer.wr_buffer_ram[78].RAM32M0_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(473),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(473),
      O => \write_buffer.wr_buf_in_data\(473)
    );
\write_buffer.wr_buffer_ram[78].RAM32M0_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(472),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(472),
      O => \write_buffer.wr_buf_in_data\(472)
    );
\write_buffer.wr_buffer_ram[78].RAM32M0_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(471),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(471),
      O => \write_buffer.wr_buf_in_data\(471)
    );
\write_buffer.wr_buffer_ram[78].RAM32M0_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(470),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(470),
      O => \write_buffer.wr_buf_in_data\(470)
    );
\write_buffer.wr_buffer_ram[78].RAM32M0_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(469),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(469),
      O => \write_buffer.wr_buf_in_data\(469)
    );
\write_buffer.wr_buffer_ram[78].RAM32M0_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(468),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(468),
      O => \write_buffer.wr_buf_in_data\(468)
    );
\write_buffer.wr_buffer_ram[79].RAM32M0\: unisim.vcomponents.RAM32M
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      IS_WCLK_INVERTED => '0'
    )
        port map (
      ADDRA(4 downto 1) => wr_data_addr(3 downto 0),
      ADDRA(0) => '0',
      ADDRB(4 downto 1) => wr_data_addr(3 downto 0),
      ADDRB(0) => '0',
      ADDRC(4 downto 1) => wr_data_addr(3 downto 0),
      ADDRC(0) => '0',
      ADDRD(4 downto 1) => wb_wr_data_addr_w(4 downto 1),
      ADDRD(0) => \write_data_control.wb_wr_data_addr0_ns\,
      DIA(1 downto 0) => \write_buffer.wr_buf_in_data\(479 downto 478),
      DIB(1 downto 0) => \write_buffer.wr_buf_in_data\(477 downto 476),
      DIC(1 downto 0) => \write_buffer.wr_buf_in_data\(475 downto 474),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => wr_buf_out_data_w(479 downto 478),
      DOB(1 downto 0) => wr_buf_out_data_w(477 downto 476),
      DOC(1 downto 0) => wr_buf_out_data_w(475 downto 474),
      DOD(1 downto 0) => \NLW_write_buffer.wr_buffer_ram[79].RAM32M0_DOD_UNCONNECTED\(1 downto 0),
      WCLK => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      WE => wdf_rdy_ns
    );
\write_buffer.wr_buffer_ram[79].RAM32M0_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(479),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(479),
      O => \write_buffer.wr_buf_in_data\(479)
    );
\write_buffer.wr_buffer_ram[79].RAM32M0_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(478),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(478),
      O => \write_buffer.wr_buf_in_data\(478)
    );
\write_buffer.wr_buffer_ram[79].RAM32M0_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(477),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(477),
      O => \write_buffer.wr_buf_in_data\(477)
    );
\write_buffer.wr_buffer_ram[79].RAM32M0_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(476),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(476),
      O => \write_buffer.wr_buf_in_data\(476)
    );
\write_buffer.wr_buffer_ram[79].RAM32M0_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(475),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(475),
      O => \write_buffer.wr_buf_in_data\(475)
    );
\write_buffer.wr_buffer_ram[79].RAM32M0_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(474),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(474),
      O => \write_buffer.wr_buf_in_data\(474)
    );
\write_buffer.wr_buffer_ram[7].RAM32M0\: unisim.vcomponents.RAM32M
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      IS_WCLK_INVERTED => '0'
    )
        port map (
      ADDRA(4 downto 1) => wr_data_addr(3 downto 0),
      ADDRA(0) => '0',
      ADDRB(4 downto 1) => wr_data_addr(3 downto 0),
      ADDRB(0) => '0',
      ADDRC(4 downto 1) => wr_data_addr(3 downto 0),
      ADDRC(0) => '0',
      ADDRD(4 downto 1) => wb_wr_data_addr_w(4 downto 1),
      ADDRD(0) => \write_data_control.wb_wr_data_addr0_ns\,
      DIA(1 downto 0) => \write_buffer.wr_buf_in_data\(47 downto 46),
      DIB(1 downto 0) => \write_buffer.wr_buf_in_data\(45 downto 44),
      DIC(1 downto 0) => \write_buffer.wr_buf_in_data\(43 downto 42),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => wr_buf_out_data_w(47 downto 46),
      DOB(1 downto 0) => wr_buf_out_data_w(45 downto 44),
      DOC(1 downto 0) => wr_buf_out_data_w(43 downto 42),
      DOD(1 downto 0) => \NLW_write_buffer.wr_buffer_ram[7].RAM32M0_DOD_UNCONNECTED\(1 downto 0),
      WCLK => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      WE => wdf_rdy_ns
    );
\write_buffer.wr_buffer_ram[7].RAM32M0_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(47),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(47),
      O => \write_buffer.wr_buf_in_data\(47)
    );
\write_buffer.wr_buffer_ram[7].RAM32M0_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(46),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(46),
      O => \write_buffer.wr_buf_in_data\(46)
    );
\write_buffer.wr_buffer_ram[7].RAM32M0_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(45),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(45),
      O => \write_buffer.wr_buf_in_data\(45)
    );
\write_buffer.wr_buffer_ram[7].RAM32M0_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(44),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(44),
      O => \write_buffer.wr_buf_in_data\(44)
    );
\write_buffer.wr_buffer_ram[7].RAM32M0_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(43),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(43),
      O => \write_buffer.wr_buf_in_data\(43)
    );
\write_buffer.wr_buffer_ram[7].RAM32M0_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(42),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(42),
      O => \write_buffer.wr_buf_in_data\(42)
    );
\write_buffer.wr_buffer_ram[80].RAM32M0\: unisim.vcomponents.RAM32M
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      IS_WCLK_INVERTED => '0'
    )
        port map (
      ADDRA(4 downto 1) => wr_data_addr(3 downto 0),
      ADDRA(0) => '0',
      ADDRB(4 downto 1) => wr_data_addr(3 downto 0),
      ADDRB(0) => '0',
      ADDRC(4 downto 1) => wr_data_addr(3 downto 0),
      ADDRC(0) => '0',
      ADDRD(4 downto 1) => wb_wr_data_addr_w(4 downto 1),
      ADDRD(0) => \write_data_control.wb_wr_data_addr0_ns\,
      DIA(1 downto 0) => \write_buffer.wr_buf_in_data\(485 downto 484),
      DIB(1 downto 0) => \write_buffer.wr_buf_in_data\(483 downto 482),
      DIC(1 downto 0) => \write_buffer.wr_buf_in_data\(481 downto 480),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => wr_buf_out_data_w(485 downto 484),
      DOB(1 downto 0) => wr_buf_out_data_w(483 downto 482),
      DOC(1 downto 0) => wr_buf_out_data_w(481 downto 480),
      DOD(1 downto 0) => \NLW_write_buffer.wr_buffer_ram[80].RAM32M0_DOD_UNCONNECTED\(1 downto 0),
      WCLK => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      WE => wdf_rdy_ns
    );
\write_buffer.wr_buffer_ram[80].RAM32M0_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(485),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(485),
      O => \write_buffer.wr_buf_in_data\(485)
    );
\write_buffer.wr_buffer_ram[80].RAM32M0_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(484),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(484),
      O => \write_buffer.wr_buf_in_data\(484)
    );
\write_buffer.wr_buffer_ram[80].RAM32M0_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(483),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(483),
      O => \write_buffer.wr_buf_in_data\(483)
    );
\write_buffer.wr_buffer_ram[80].RAM32M0_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(482),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(482),
      O => \write_buffer.wr_buf_in_data\(482)
    );
\write_buffer.wr_buffer_ram[80].RAM32M0_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(481),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(481),
      O => \write_buffer.wr_buf_in_data\(481)
    );
\write_buffer.wr_buffer_ram[80].RAM32M0_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(480),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(480),
      O => \write_buffer.wr_buf_in_data\(480)
    );
\write_buffer.wr_buffer_ram[81].RAM32M0\: unisim.vcomponents.RAM32M
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      IS_WCLK_INVERTED => '0'
    )
        port map (
      ADDRA(4 downto 1) => wr_data_addr(3 downto 0),
      ADDRA(0) => '0',
      ADDRB(4 downto 1) => wr_data_addr(3 downto 0),
      ADDRB(0) => '0',
      ADDRC(4 downto 1) => wr_data_addr(3 downto 0),
      ADDRC(0) => '0',
      ADDRD(4 downto 1) => wb_wr_data_addr_w(4 downto 1),
      ADDRD(0) => \write_data_control.wb_wr_data_addr0_ns\,
      DIA(1 downto 0) => \write_buffer.wr_buf_in_data\(491 downto 490),
      DIB(1 downto 0) => \write_buffer.wr_buf_in_data\(489 downto 488),
      DIC(1 downto 0) => \write_buffer.wr_buf_in_data\(487 downto 486),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => wr_buf_out_data_w(491 downto 490),
      DOB(1 downto 0) => wr_buf_out_data_w(489 downto 488),
      DOC(1 downto 0) => wr_buf_out_data_w(487 downto 486),
      DOD(1 downto 0) => \NLW_write_buffer.wr_buffer_ram[81].RAM32M0_DOD_UNCONNECTED\(1 downto 0),
      WCLK => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      WE => wdf_rdy_ns
    );
\write_buffer.wr_buffer_ram[81].RAM32M0_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(491),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(491),
      O => \write_buffer.wr_buf_in_data\(491)
    );
\write_buffer.wr_buffer_ram[81].RAM32M0_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(490),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(490),
      O => \write_buffer.wr_buf_in_data\(490)
    );
\write_buffer.wr_buffer_ram[81].RAM32M0_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(489),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(489),
      O => \write_buffer.wr_buf_in_data\(489)
    );
\write_buffer.wr_buffer_ram[81].RAM32M0_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(488),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(488),
      O => \write_buffer.wr_buf_in_data\(488)
    );
\write_buffer.wr_buffer_ram[81].RAM32M0_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(487),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(487),
      O => \write_buffer.wr_buf_in_data\(487)
    );
\write_buffer.wr_buffer_ram[81].RAM32M0_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(486),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(486),
      O => \write_buffer.wr_buf_in_data\(486)
    );
\write_buffer.wr_buffer_ram[82].RAM32M0\: unisim.vcomponents.RAM32M
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      IS_WCLK_INVERTED => '0'
    )
        port map (
      ADDRA(4 downto 1) => wr_data_addr(3 downto 0),
      ADDRA(0) => '0',
      ADDRB(4 downto 1) => wr_data_addr(3 downto 0),
      ADDRB(0) => '0',
      ADDRC(4 downto 1) => wr_data_addr(3 downto 0),
      ADDRC(0) => '0',
      ADDRD(4 downto 1) => wb_wr_data_addr_w(4 downto 1),
      ADDRD(0) => \write_data_control.wb_wr_data_addr0_ns\,
      DIA(1 downto 0) => \write_buffer.wr_buf_in_data\(497 downto 496),
      DIB(1 downto 0) => \write_buffer.wr_buf_in_data\(495 downto 494),
      DIC(1 downto 0) => \write_buffer.wr_buf_in_data\(493 downto 492),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => wr_buf_out_data_w(497 downto 496),
      DOB(1 downto 0) => wr_buf_out_data_w(495 downto 494),
      DOC(1 downto 0) => wr_buf_out_data_w(493 downto 492),
      DOD(1 downto 0) => \NLW_write_buffer.wr_buffer_ram[82].RAM32M0_DOD_UNCONNECTED\(1 downto 0),
      WCLK => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      WE => wdf_rdy_ns
    );
\write_buffer.wr_buffer_ram[82].RAM32M0_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(497),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(497),
      O => \write_buffer.wr_buf_in_data\(497)
    );
\write_buffer.wr_buffer_ram[82].RAM32M0_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(496),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(496),
      O => \write_buffer.wr_buf_in_data\(496)
    );
\write_buffer.wr_buffer_ram[82].RAM32M0_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(495),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(495),
      O => \write_buffer.wr_buf_in_data\(495)
    );
\write_buffer.wr_buffer_ram[82].RAM32M0_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(494),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(494),
      O => \write_buffer.wr_buf_in_data\(494)
    );
\write_buffer.wr_buffer_ram[82].RAM32M0_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(493),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(493),
      O => \write_buffer.wr_buf_in_data\(493)
    );
\write_buffer.wr_buffer_ram[82].RAM32M0_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(492),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(492),
      O => \write_buffer.wr_buf_in_data\(492)
    );
\write_buffer.wr_buffer_ram[83].RAM32M0\: unisim.vcomponents.RAM32M
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      IS_WCLK_INVERTED => '0'
    )
        port map (
      ADDRA(4 downto 1) => wr_data_addr(3 downto 0),
      ADDRA(0) => '0',
      ADDRB(4 downto 1) => wr_data_addr(3 downto 0),
      ADDRB(0) => '0',
      ADDRC(4 downto 1) => wr_data_addr(3 downto 0),
      ADDRC(0) => '0',
      ADDRD(4 downto 1) => wb_wr_data_addr_w(4 downto 1),
      ADDRD(0) => \write_data_control.wb_wr_data_addr0_ns\,
      DIA(1 downto 0) => \write_buffer.wr_buf_in_data\(503 downto 502),
      DIB(1 downto 0) => \write_buffer.wr_buf_in_data\(501 downto 500),
      DIC(1 downto 0) => \write_buffer.wr_buf_in_data\(499 downto 498),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => wr_buf_out_data_w(503 downto 502),
      DOB(1 downto 0) => wr_buf_out_data_w(501 downto 500),
      DOC(1 downto 0) => wr_buf_out_data_w(499 downto 498),
      DOD(1 downto 0) => \NLW_write_buffer.wr_buffer_ram[83].RAM32M0_DOD_UNCONNECTED\(1 downto 0),
      WCLK => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      WE => wdf_rdy_ns
    );
\write_buffer.wr_buffer_ram[83].RAM32M0_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(503),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(503),
      O => \write_buffer.wr_buf_in_data\(503)
    );
\write_buffer.wr_buffer_ram[83].RAM32M0_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(502),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(502),
      O => \write_buffer.wr_buf_in_data\(502)
    );
\write_buffer.wr_buffer_ram[83].RAM32M0_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(501),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(501),
      O => \write_buffer.wr_buf_in_data\(501)
    );
\write_buffer.wr_buffer_ram[83].RAM32M0_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(500),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(500),
      O => \write_buffer.wr_buf_in_data\(500)
    );
\write_buffer.wr_buffer_ram[83].RAM32M0_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(499),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(499),
      O => \write_buffer.wr_buf_in_data\(499)
    );
\write_buffer.wr_buffer_ram[83].RAM32M0_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(498),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(498),
      O => \write_buffer.wr_buf_in_data\(498)
    );
\write_buffer.wr_buffer_ram[84].RAM32M0\: unisim.vcomponents.RAM32M
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      IS_WCLK_INVERTED => '0'
    )
        port map (
      ADDRA(4 downto 1) => wr_data_addr(3 downto 0),
      ADDRA(0) => '0',
      ADDRB(4 downto 1) => wr_data_addr(3 downto 0),
      ADDRB(0) => '0',
      ADDRC(4 downto 1) => wr_data_addr(3 downto 0),
      ADDRC(0) => '0',
      ADDRD(4 downto 1) => wb_wr_data_addr_w(4 downto 1),
      ADDRD(0) => \write_data_control.wb_wr_data_addr0_ns\,
      DIA(1 downto 0) => \write_buffer.wr_buf_in_data\(509 downto 508),
      DIB(1 downto 0) => \write_buffer.wr_buf_in_data\(507 downto 506),
      DIC(1 downto 0) => \write_buffer.wr_buf_in_data\(505 downto 504),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => wr_buf_out_data_w(509 downto 508),
      DOB(1 downto 0) => wr_buf_out_data_w(507 downto 506),
      DOC(1 downto 0) => wr_buf_out_data_w(505 downto 504),
      DOD(1 downto 0) => \NLW_write_buffer.wr_buffer_ram[84].RAM32M0_DOD_UNCONNECTED\(1 downto 0),
      WCLK => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      WE => wdf_rdy_ns
    );
\write_buffer.wr_buffer_ram[84].RAM32M0_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(509),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(509),
      O => \write_buffer.wr_buf_in_data\(509)
    );
\write_buffer.wr_buffer_ram[84].RAM32M0_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(508),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(508),
      O => \write_buffer.wr_buf_in_data\(508)
    );
\write_buffer.wr_buffer_ram[84].RAM32M0_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(507),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(507),
      O => \write_buffer.wr_buf_in_data\(507)
    );
\write_buffer.wr_buffer_ram[84].RAM32M0_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(506),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(506),
      O => \write_buffer.wr_buf_in_data\(506)
    );
\write_buffer.wr_buffer_ram[84].RAM32M0_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(505),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(505),
      O => \write_buffer.wr_buf_in_data\(505)
    );
\write_buffer.wr_buffer_ram[84].RAM32M0_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(504),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(504),
      O => \write_buffer.wr_buf_in_data\(504)
    );
\write_buffer.wr_buffer_ram[85].RAM32M0\: unisim.vcomponents.RAM32M
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      IS_WCLK_INVERTED => '0'
    )
        port map (
      ADDRA(4 downto 1) => wr_data_addr(3 downto 0),
      ADDRA(0) => '0',
      ADDRB(4 downto 1) => wr_data_addr(3 downto 0),
      ADDRB(0) => '0',
      ADDRC(4 downto 1) => wr_data_addr(3 downto 0),
      ADDRC(0) => '0',
      ADDRD(4 downto 1) => wb_wr_data_addr_w(4 downto 1),
      ADDRD(0) => \write_data_control.wb_wr_data_addr0_ns\,
      DIA(1 downto 0) => \write_buffer.wr_buf_in_data\(515 downto 514),
      DIB(1 downto 0) => \write_buffer.wr_buf_in_data\(513 downto 512),
      DIC(1 downto 0) => \write_buffer.wr_buf_in_data\(511 downto 510),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => wr_buf_out_data_w(515 downto 514),
      DOB(1 downto 0) => wr_buf_out_data_w(513 downto 512),
      DOC(1 downto 0) => wr_buf_out_data_w(511 downto 510),
      DOD(1 downto 0) => \NLW_write_buffer.wr_buffer_ram[85].RAM32M0_DOD_UNCONNECTED\(1 downto 0),
      WCLK => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      WE => wdf_rdy_ns
    );
\write_buffer.wr_buffer_ram[85].RAM32M0_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_mask(3),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_mask_r1(3),
      O => \write_buffer.wr_buf_in_data\(515)
    );
\write_buffer.wr_buffer_ram[85].RAM32M0_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_mask(2),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_mask_r1(2),
      O => \write_buffer.wr_buf_in_data\(514)
    );
\write_buffer.wr_buffer_ram[85].RAM32M0_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_mask(1),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_mask_r1(1),
      O => \write_buffer.wr_buf_in_data\(513)
    );
\write_buffer.wr_buffer_ram[85].RAM32M0_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_mask(0),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_mask_r1(0),
      O => \write_buffer.wr_buf_in_data\(512)
    );
\write_buffer.wr_buffer_ram[85].RAM32M0_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(511),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(511),
      O => \write_buffer.wr_buf_in_data\(511)
    );
\write_buffer.wr_buffer_ram[85].RAM32M0_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(510),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(510),
      O => \write_buffer.wr_buf_in_data\(510)
    );
\write_buffer.wr_buffer_ram[86].RAM32M0\: unisim.vcomponents.RAM32M
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      IS_WCLK_INVERTED => '0'
    )
        port map (
      ADDRA(4 downto 1) => wr_data_addr(3 downto 0),
      ADDRA(0) => '0',
      ADDRB(4 downto 1) => wr_data_addr(3 downto 0),
      ADDRB(0) => '0',
      ADDRC(4 downto 1) => wr_data_addr(3 downto 0),
      ADDRC(0) => '0',
      ADDRD(4 downto 1) => wb_wr_data_addr_w(4 downto 1),
      ADDRD(0) => \write_data_control.wb_wr_data_addr0_ns\,
      DIA(1 downto 0) => \write_buffer.wr_buf_in_data\(521 downto 520),
      DIB(1 downto 0) => \write_buffer.wr_buf_in_data\(519 downto 518),
      DIC(1 downto 0) => \write_buffer.wr_buf_in_data\(517 downto 516),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => wr_buf_out_data_w(521 downto 520),
      DOB(1 downto 0) => wr_buf_out_data_w(519 downto 518),
      DOC(1 downto 0) => wr_buf_out_data_w(517 downto 516),
      DOD(1 downto 0) => \NLW_write_buffer.wr_buffer_ram[86].RAM32M0_DOD_UNCONNECTED\(1 downto 0),
      WCLK => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      WE => wdf_rdy_ns
    );
\write_buffer.wr_buffer_ram[86].RAM32M0_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_mask(9),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_mask_r1(9),
      O => \write_buffer.wr_buf_in_data\(521)
    );
\write_buffer.wr_buffer_ram[86].RAM32M0_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_mask(8),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_mask_r1(8),
      O => \write_buffer.wr_buf_in_data\(520)
    );
\write_buffer.wr_buffer_ram[86].RAM32M0_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_mask(7),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_mask_r1(7),
      O => \write_buffer.wr_buf_in_data\(519)
    );
\write_buffer.wr_buffer_ram[86].RAM32M0_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_mask(6),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_mask_r1(6),
      O => \write_buffer.wr_buf_in_data\(518)
    );
\write_buffer.wr_buffer_ram[86].RAM32M0_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_mask(5),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_mask_r1(5),
      O => \write_buffer.wr_buf_in_data\(517)
    );
\write_buffer.wr_buffer_ram[86].RAM32M0_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_mask(4),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_mask_r1(4),
      O => \write_buffer.wr_buf_in_data\(516)
    );
\write_buffer.wr_buffer_ram[87].RAM32M0\: unisim.vcomponents.RAM32M
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      IS_WCLK_INVERTED => '0'
    )
        port map (
      ADDRA(4 downto 1) => wr_data_addr(3 downto 0),
      ADDRA(0) => '0',
      ADDRB(4 downto 1) => wr_data_addr(3 downto 0),
      ADDRB(0) => '0',
      ADDRC(4 downto 1) => wr_data_addr(3 downto 0),
      ADDRC(0) => '0',
      ADDRD(4 downto 1) => wb_wr_data_addr_w(4 downto 1),
      ADDRD(0) => \write_data_control.wb_wr_data_addr0_ns\,
      DIA(1 downto 0) => \write_buffer.wr_buf_in_data\(527 downto 526),
      DIB(1 downto 0) => \write_buffer.wr_buf_in_data\(525 downto 524),
      DIC(1 downto 0) => \write_buffer.wr_buf_in_data\(523 downto 522),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => wr_buf_out_data_w(527 downto 526),
      DOB(1 downto 0) => wr_buf_out_data_w(525 downto 524),
      DOC(1 downto 0) => wr_buf_out_data_w(523 downto 522),
      DOD(1 downto 0) => \NLW_write_buffer.wr_buffer_ram[87].RAM32M0_DOD_UNCONNECTED\(1 downto 0),
      WCLK => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      WE => wdf_rdy_ns
    );
\write_buffer.wr_buffer_ram[87].RAM32M0_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_mask(15),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_mask_r1(15),
      O => \write_buffer.wr_buf_in_data\(527)
    );
\write_buffer.wr_buffer_ram[87].RAM32M0_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_mask(14),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_mask_r1(14),
      O => \write_buffer.wr_buf_in_data\(526)
    );
\write_buffer.wr_buffer_ram[87].RAM32M0_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_mask(13),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_mask_r1(13),
      O => \write_buffer.wr_buf_in_data\(525)
    );
\write_buffer.wr_buffer_ram[87].RAM32M0_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_mask(12),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_mask_r1(12),
      O => \write_buffer.wr_buf_in_data\(524)
    );
\write_buffer.wr_buffer_ram[87].RAM32M0_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_mask(11),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_mask_r1(11),
      O => \write_buffer.wr_buf_in_data\(523)
    );
\write_buffer.wr_buffer_ram[87].RAM32M0_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_mask(10),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_mask_r1(10),
      O => \write_buffer.wr_buf_in_data\(522)
    );
\write_buffer.wr_buffer_ram[88].RAM32M0\: unisim.vcomponents.RAM32M
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      IS_WCLK_INVERTED => '0'
    )
        port map (
      ADDRA(4 downto 1) => wr_data_addr(3 downto 0),
      ADDRA(0) => '0',
      ADDRB(4 downto 1) => wr_data_addr(3 downto 0),
      ADDRB(0) => '0',
      ADDRC(4 downto 1) => wr_data_addr(3 downto 0),
      ADDRC(0) => '0',
      ADDRD(4 downto 1) => wb_wr_data_addr_w(4 downto 1),
      ADDRD(0) => \write_data_control.wb_wr_data_addr0_ns\,
      DIA(1 downto 0) => \write_buffer.wr_buf_in_data\(533 downto 532),
      DIB(1 downto 0) => \write_buffer.wr_buf_in_data\(531 downto 530),
      DIC(1 downto 0) => \write_buffer.wr_buf_in_data\(529 downto 528),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => wr_buf_out_data_w(533 downto 532),
      DOB(1 downto 0) => wr_buf_out_data_w(531 downto 530),
      DOC(1 downto 0) => wr_buf_out_data_w(529 downto 528),
      DOD(1 downto 0) => \NLW_write_buffer.wr_buffer_ram[88].RAM32M0_DOD_UNCONNECTED\(1 downto 0),
      WCLK => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      WE => wdf_rdy_ns
    );
\write_buffer.wr_buffer_ram[88].RAM32M0_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_mask(21),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_mask_r1(21),
      O => \write_buffer.wr_buf_in_data\(533)
    );
\write_buffer.wr_buffer_ram[88].RAM32M0_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_mask(20),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_mask_r1(20),
      O => \write_buffer.wr_buf_in_data\(532)
    );
\write_buffer.wr_buffer_ram[88].RAM32M0_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_mask(19),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_mask_r1(19),
      O => \write_buffer.wr_buf_in_data\(531)
    );
\write_buffer.wr_buffer_ram[88].RAM32M0_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_mask(18),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_mask_r1(18),
      O => \write_buffer.wr_buf_in_data\(530)
    );
\write_buffer.wr_buffer_ram[88].RAM32M0_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_mask(17),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_mask_r1(17),
      O => \write_buffer.wr_buf_in_data\(529)
    );
\write_buffer.wr_buffer_ram[88].RAM32M0_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_mask(16),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_mask_r1(16),
      O => \write_buffer.wr_buf_in_data\(528)
    );
\write_buffer.wr_buffer_ram[89].RAM32M0\: unisim.vcomponents.RAM32M
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      IS_WCLK_INVERTED => '0'
    )
        port map (
      ADDRA(4 downto 1) => wr_data_addr(3 downto 0),
      ADDRA(0) => '0',
      ADDRB(4 downto 1) => wr_data_addr(3 downto 0),
      ADDRB(0) => '0',
      ADDRC(4 downto 1) => wr_data_addr(3 downto 0),
      ADDRC(0) => '0',
      ADDRD(4 downto 1) => wb_wr_data_addr_w(4 downto 1),
      ADDRD(0) => \write_data_control.wb_wr_data_addr0_ns\,
      DIA(1 downto 0) => \write_buffer.wr_buf_in_data\(539 downto 538),
      DIB(1 downto 0) => \write_buffer.wr_buf_in_data\(537 downto 536),
      DIC(1 downto 0) => \write_buffer.wr_buf_in_data\(535 downto 534),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => wr_buf_out_data_w(539 downto 538),
      DOB(1 downto 0) => wr_buf_out_data_w(537 downto 536),
      DOC(1 downto 0) => wr_buf_out_data_w(535 downto 534),
      DOD(1 downto 0) => \NLW_write_buffer.wr_buffer_ram[89].RAM32M0_DOD_UNCONNECTED\(1 downto 0),
      WCLK => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      WE => wdf_rdy_ns
    );
\write_buffer.wr_buffer_ram[89].RAM32M0_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_mask(27),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_mask_r1(27),
      O => \write_buffer.wr_buf_in_data\(539)
    );
\write_buffer.wr_buffer_ram[89].RAM32M0_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_mask(26),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_mask_r1(26),
      O => \write_buffer.wr_buf_in_data\(538)
    );
\write_buffer.wr_buffer_ram[89].RAM32M0_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_mask(25),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_mask_r1(25),
      O => \write_buffer.wr_buf_in_data\(537)
    );
\write_buffer.wr_buffer_ram[89].RAM32M0_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_mask(24),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_mask_r1(24),
      O => \write_buffer.wr_buf_in_data\(536)
    );
\write_buffer.wr_buffer_ram[89].RAM32M0_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_mask(23),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_mask_r1(23),
      O => \write_buffer.wr_buf_in_data\(535)
    );
\write_buffer.wr_buffer_ram[89].RAM32M0_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_mask(22),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_mask_r1(22),
      O => \write_buffer.wr_buf_in_data\(534)
    );
\write_buffer.wr_buffer_ram[8].RAM32M0\: unisim.vcomponents.RAM32M
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      IS_WCLK_INVERTED => '0'
    )
        port map (
      ADDRA(4 downto 1) => wr_data_addr(3 downto 0),
      ADDRA(0) => '0',
      ADDRB(4 downto 1) => wr_data_addr(3 downto 0),
      ADDRB(0) => '0',
      ADDRC(4 downto 1) => wr_data_addr(3 downto 0),
      ADDRC(0) => '0',
      ADDRD(4 downto 1) => wb_wr_data_addr_w(4 downto 1),
      ADDRD(0) => \write_data_control.wb_wr_data_addr0_ns\,
      DIA(1 downto 0) => \write_buffer.wr_buf_in_data\(53 downto 52),
      DIB(1 downto 0) => \write_buffer.wr_buf_in_data\(51 downto 50),
      DIC(1 downto 0) => \write_buffer.wr_buf_in_data\(49 downto 48),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => wr_buf_out_data_w(53 downto 52),
      DOB(1 downto 0) => wr_buf_out_data_w(51 downto 50),
      DOC(1 downto 0) => wr_buf_out_data_w(49 downto 48),
      DOD(1 downto 0) => \NLW_write_buffer.wr_buffer_ram[8].RAM32M0_DOD_UNCONNECTED\(1 downto 0),
      WCLK => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      WE => wdf_rdy_ns
    );
\write_buffer.wr_buffer_ram[8].RAM32M0_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(53),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(53),
      O => \write_buffer.wr_buf_in_data\(53)
    );
\write_buffer.wr_buffer_ram[8].RAM32M0_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(52),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(52),
      O => \write_buffer.wr_buf_in_data\(52)
    );
\write_buffer.wr_buffer_ram[8].RAM32M0_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(51),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(51),
      O => \write_buffer.wr_buf_in_data\(51)
    );
\write_buffer.wr_buffer_ram[8].RAM32M0_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(50),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(50),
      O => \write_buffer.wr_buf_in_data\(50)
    );
\write_buffer.wr_buffer_ram[8].RAM32M0_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(49),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(49),
      O => \write_buffer.wr_buf_in_data\(49)
    );
\write_buffer.wr_buffer_ram[8].RAM32M0_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(48),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(48),
      O => \write_buffer.wr_buf_in_data\(48)
    );
\write_buffer.wr_buffer_ram[90].RAM32M0\: unisim.vcomponents.RAM32M
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      IS_WCLK_INVERTED => '0'
    )
        port map (
      ADDRA(4 downto 1) => wr_data_addr(3 downto 0),
      ADDRA(0) => '0',
      ADDRB(4 downto 1) => wr_data_addr(3 downto 0),
      ADDRB(0) => '0',
      ADDRC(4 downto 1) => wr_data_addr(3 downto 0),
      ADDRC(0) => '0',
      ADDRD(4 downto 1) => wb_wr_data_addr_w(4 downto 1),
      ADDRD(0) => \write_data_control.wb_wr_data_addr0_ns\,
      DIA(1 downto 0) => \write_buffer.wr_buf_in_data\(545 downto 544),
      DIB(1 downto 0) => \write_buffer.wr_buf_in_data\(543 downto 542),
      DIC(1 downto 0) => \write_buffer.wr_buf_in_data\(541 downto 540),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => wr_buf_out_data_w(545 downto 544),
      DOB(1 downto 0) => wr_buf_out_data_w(543 downto 542),
      DOC(1 downto 0) => wr_buf_out_data_w(541 downto 540),
      DOD(1 downto 0) => \NLW_write_buffer.wr_buffer_ram[90].RAM32M0_DOD_UNCONNECTED\(1 downto 0),
      WCLK => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      WE => wdf_rdy_ns
    );
\write_buffer.wr_buffer_ram[90].RAM32M0_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_mask(33),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_mask_r1(33),
      O => \write_buffer.wr_buf_in_data\(545)
    );
\write_buffer.wr_buffer_ram[90].RAM32M0_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_mask(32),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_mask_r1(32),
      O => \write_buffer.wr_buf_in_data\(544)
    );
\write_buffer.wr_buffer_ram[90].RAM32M0_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_mask(31),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_mask_r1(31),
      O => \write_buffer.wr_buf_in_data\(543)
    );
\write_buffer.wr_buffer_ram[90].RAM32M0_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_mask(30),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_mask_r1(30),
      O => \write_buffer.wr_buf_in_data\(542)
    );
\write_buffer.wr_buffer_ram[90].RAM32M0_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_mask(29),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_mask_r1(29),
      O => \write_buffer.wr_buf_in_data\(541)
    );
\write_buffer.wr_buffer_ram[90].RAM32M0_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_mask(28),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_mask_r1(28),
      O => \write_buffer.wr_buf_in_data\(540)
    );
\write_buffer.wr_buffer_ram[91].RAM32M0\: unisim.vcomponents.RAM32M
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      IS_WCLK_INVERTED => '0'
    )
        port map (
      ADDRA(4 downto 1) => wr_data_addr(3 downto 0),
      ADDRA(0) => '0',
      ADDRB(4 downto 1) => wr_data_addr(3 downto 0),
      ADDRB(0) => '0',
      ADDRC(4 downto 1) => wr_data_addr(3 downto 0),
      ADDRC(0) => '0',
      ADDRD(4 downto 1) => wb_wr_data_addr_w(4 downto 1),
      ADDRD(0) => \write_data_control.wb_wr_data_addr0_ns\,
      DIA(1 downto 0) => \write_buffer.wr_buf_in_data\(551 downto 550),
      DIB(1 downto 0) => \write_buffer.wr_buf_in_data\(549 downto 548),
      DIC(1 downto 0) => \write_buffer.wr_buf_in_data\(547 downto 546),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => wr_buf_out_data_w(551 downto 550),
      DOB(1 downto 0) => wr_buf_out_data_w(549 downto 548),
      DOC(1 downto 0) => wr_buf_out_data_w(547 downto 546),
      DOD(1 downto 0) => \NLW_write_buffer.wr_buffer_ram[91].RAM32M0_DOD_UNCONNECTED\(1 downto 0),
      WCLK => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      WE => wdf_rdy_ns
    );
\write_buffer.wr_buffer_ram[91].RAM32M0_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_mask(39),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_mask_r1(39),
      O => \write_buffer.wr_buf_in_data\(551)
    );
\write_buffer.wr_buffer_ram[91].RAM32M0_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_mask(38),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_mask_r1(38),
      O => \write_buffer.wr_buf_in_data\(550)
    );
\write_buffer.wr_buffer_ram[91].RAM32M0_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_mask(37),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_mask_r1(37),
      O => \write_buffer.wr_buf_in_data\(549)
    );
\write_buffer.wr_buffer_ram[91].RAM32M0_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_mask(36),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_mask_r1(36),
      O => \write_buffer.wr_buf_in_data\(548)
    );
\write_buffer.wr_buffer_ram[91].RAM32M0_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_mask(35),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_mask_r1(35),
      O => \write_buffer.wr_buf_in_data\(547)
    );
\write_buffer.wr_buffer_ram[91].RAM32M0_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_mask(34),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_mask_r1(34),
      O => \write_buffer.wr_buf_in_data\(546)
    );
\write_buffer.wr_buffer_ram[92].RAM32M0\: unisim.vcomponents.RAM32M
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      IS_WCLK_INVERTED => '0'
    )
        port map (
      ADDRA(4 downto 1) => wr_data_addr(3 downto 0),
      ADDRA(0) => '0',
      ADDRB(4 downto 1) => wr_data_addr(3 downto 0),
      ADDRB(0) => '0',
      ADDRC(4 downto 1) => wr_data_addr(3 downto 0),
      ADDRC(0) => '0',
      ADDRD(4 downto 1) => wb_wr_data_addr_w(4 downto 1),
      ADDRD(0) => \write_data_control.wb_wr_data_addr0_ns\,
      DIA(1 downto 0) => \write_buffer.wr_buf_in_data\(557 downto 556),
      DIB(1 downto 0) => \write_buffer.wr_buf_in_data\(555 downto 554),
      DIC(1 downto 0) => \write_buffer.wr_buf_in_data\(553 downto 552),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => wr_buf_out_data_w(557 downto 556),
      DOB(1 downto 0) => wr_buf_out_data_w(555 downto 554),
      DOC(1 downto 0) => wr_buf_out_data_w(553 downto 552),
      DOD(1 downto 0) => \NLW_write_buffer.wr_buffer_ram[92].RAM32M0_DOD_UNCONNECTED\(1 downto 0),
      WCLK => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      WE => wdf_rdy_ns
    );
\write_buffer.wr_buffer_ram[92].RAM32M0_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_mask(45),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_mask_r1(45),
      O => \write_buffer.wr_buf_in_data\(557)
    );
\write_buffer.wr_buffer_ram[92].RAM32M0_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_mask(44),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_mask_r1(44),
      O => \write_buffer.wr_buf_in_data\(556)
    );
\write_buffer.wr_buffer_ram[92].RAM32M0_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_mask(43),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_mask_r1(43),
      O => \write_buffer.wr_buf_in_data\(555)
    );
\write_buffer.wr_buffer_ram[92].RAM32M0_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_mask(42),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_mask_r1(42),
      O => \write_buffer.wr_buf_in_data\(554)
    );
\write_buffer.wr_buffer_ram[92].RAM32M0_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_mask(41),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_mask_r1(41),
      O => \write_buffer.wr_buf_in_data\(553)
    );
\write_buffer.wr_buffer_ram[92].RAM32M0_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_mask(40),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_mask_r1(40),
      O => \write_buffer.wr_buf_in_data\(552)
    );
\write_buffer.wr_buffer_ram[93].RAM32M0\: unisim.vcomponents.RAM32M
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      IS_WCLK_INVERTED => '0'
    )
        port map (
      ADDRA(4 downto 1) => wr_data_addr(3 downto 0),
      ADDRA(0) => '0',
      ADDRB(4 downto 1) => wr_data_addr(3 downto 0),
      ADDRB(0) => '0',
      ADDRC(4 downto 1) => wr_data_addr(3 downto 0),
      ADDRC(0) => '0',
      ADDRD(4 downto 1) => wb_wr_data_addr_w(4 downto 1),
      ADDRD(0) => \write_data_control.wb_wr_data_addr0_ns\,
      DIA(1 downto 0) => \write_buffer.wr_buf_in_data\(563 downto 562),
      DIB(1 downto 0) => \write_buffer.wr_buf_in_data\(561 downto 560),
      DIC(1 downto 0) => \write_buffer.wr_buf_in_data\(559 downto 558),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => wr_buf_out_data_w(563 downto 562),
      DOB(1 downto 0) => wr_buf_out_data_w(561 downto 560),
      DOC(1 downto 0) => wr_buf_out_data_w(559 downto 558),
      DOD(1 downto 0) => \NLW_write_buffer.wr_buffer_ram[93].RAM32M0_DOD_UNCONNECTED\(1 downto 0),
      WCLK => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      WE => wdf_rdy_ns
    );
\write_buffer.wr_buffer_ram[93].RAM32M0_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_mask(51),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_mask_r1(51),
      O => \write_buffer.wr_buf_in_data\(563)
    );
\write_buffer.wr_buffer_ram[93].RAM32M0_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_mask(50),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_mask_r1(50),
      O => \write_buffer.wr_buf_in_data\(562)
    );
\write_buffer.wr_buffer_ram[93].RAM32M0_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_mask(49),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_mask_r1(49),
      O => \write_buffer.wr_buf_in_data\(561)
    );
\write_buffer.wr_buffer_ram[93].RAM32M0_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_mask(48),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_mask_r1(48),
      O => \write_buffer.wr_buf_in_data\(560)
    );
\write_buffer.wr_buffer_ram[93].RAM32M0_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_mask(47),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_mask_r1(47),
      O => \write_buffer.wr_buf_in_data\(559)
    );
\write_buffer.wr_buffer_ram[93].RAM32M0_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_mask(46),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_mask_r1(46),
      O => \write_buffer.wr_buf_in_data\(558)
    );
\write_buffer.wr_buffer_ram[94].RAM32M0\: unisim.vcomponents.RAM32M
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      IS_WCLK_INVERTED => '0'
    )
        port map (
      ADDRA(4 downto 1) => wr_data_addr(3 downto 0),
      ADDRA(0) => '0',
      ADDRB(4 downto 1) => wr_data_addr(3 downto 0),
      ADDRB(0) => '0',
      ADDRC(4 downto 1) => wr_data_addr(3 downto 0),
      ADDRC(0) => '0',
      ADDRD(4 downto 1) => wb_wr_data_addr_w(4 downto 1),
      ADDRD(0) => \write_data_control.wb_wr_data_addr0_ns\,
      DIA(1 downto 0) => \write_buffer.wr_buf_in_data\(569 downto 568),
      DIB(1 downto 0) => \write_buffer.wr_buf_in_data\(567 downto 566),
      DIC(1 downto 0) => \write_buffer.wr_buf_in_data\(565 downto 564),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => wr_buf_out_data_w(569 downto 568),
      DOB(1 downto 0) => wr_buf_out_data_w(567 downto 566),
      DOC(1 downto 0) => wr_buf_out_data_w(565 downto 564),
      DOD(1 downto 0) => \NLW_write_buffer.wr_buffer_ram[94].RAM32M0_DOD_UNCONNECTED\(1 downto 0),
      WCLK => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      WE => wdf_rdy_ns
    );
\write_buffer.wr_buffer_ram[94].RAM32M0_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_mask(57),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_mask_r1(57),
      O => \write_buffer.wr_buf_in_data\(569)
    );
\write_buffer.wr_buffer_ram[94].RAM32M0_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_mask(56),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_mask_r1(56),
      O => \write_buffer.wr_buf_in_data\(568)
    );
\write_buffer.wr_buffer_ram[94].RAM32M0_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_mask(55),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_mask_r1(55),
      O => \write_buffer.wr_buf_in_data\(567)
    );
\write_buffer.wr_buffer_ram[94].RAM32M0_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_mask(54),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_mask_r1(54),
      O => \write_buffer.wr_buf_in_data\(566)
    );
\write_buffer.wr_buffer_ram[94].RAM32M0_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_mask(53),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_mask_r1(53),
      O => \write_buffer.wr_buf_in_data\(565)
    );
\write_buffer.wr_buffer_ram[94].RAM32M0_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_mask(52),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_mask_r1(52),
      O => \write_buffer.wr_buf_in_data\(564)
    );
\write_buffer.wr_buffer_ram[95].RAM32M0\: unisim.vcomponents.RAM32M
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      IS_WCLK_INVERTED => '0'
    )
        port map (
      ADDRA(4 downto 1) => wr_data_addr(3 downto 0),
      ADDRA(0) => '0',
      ADDRB(4 downto 1) => wr_data_addr(3 downto 0),
      ADDRB(0) => '0',
      ADDRC(4 downto 1) => wr_data_addr(3 downto 0),
      ADDRC(0) => '0',
      ADDRD(4 downto 1) => wb_wr_data_addr_w(4 downto 1),
      ADDRD(0) => \write_data_control.wb_wr_data_addr0_ns\,
      DIA(1 downto 0) => \write_buffer.wr_buf_in_data\(575 downto 574),
      DIB(1 downto 0) => \write_buffer.wr_buf_in_data\(573 downto 572),
      DIC(1 downto 0) => \write_buffer.wr_buf_in_data\(571 downto 570),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => wr_buf_out_data_w(575 downto 574),
      DOB(1 downto 0) => wr_buf_out_data_w(573 downto 572),
      DOC(1 downto 0) => wr_buf_out_data_w(571 downto 570),
      DOD(1 downto 0) => \NLW_write_buffer.wr_buffer_ram[95].RAM32M0_DOD_UNCONNECTED\(1 downto 0),
      WCLK => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      WE => wdf_rdy_ns
    );
\write_buffer.wr_buffer_ram[95].RAM32M0_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_mask(63),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_mask_r1(63),
      O => \write_buffer.wr_buf_in_data\(575)
    );
\write_buffer.wr_buffer_ram[95].RAM32M0_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_mask(62),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_mask_r1(62),
      O => \write_buffer.wr_buf_in_data\(574)
    );
\write_buffer.wr_buffer_ram[95].RAM32M0_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_mask(61),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_mask_r1(61),
      O => \write_buffer.wr_buf_in_data\(573)
    );
\write_buffer.wr_buffer_ram[95].RAM32M0_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_mask(60),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_mask_r1(60),
      O => \write_buffer.wr_buf_in_data\(572)
    );
\write_buffer.wr_buffer_ram[95].RAM32M0_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_mask(59),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_mask_r1(59),
      O => \write_buffer.wr_buf_in_data\(571)
    );
\write_buffer.wr_buffer_ram[95].RAM32M0_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_mask(58),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_mask_r1(58),
      O => \write_buffer.wr_buf_in_data\(570)
    );
\write_buffer.wr_buffer_ram[9].RAM32M0\: unisim.vcomponents.RAM32M
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      IS_WCLK_INVERTED => '0'
    )
        port map (
      ADDRA(4 downto 1) => wr_data_addr(3 downto 0),
      ADDRA(0) => '0',
      ADDRB(4 downto 1) => wr_data_addr(3 downto 0),
      ADDRB(0) => '0',
      ADDRC(4 downto 1) => wr_data_addr(3 downto 0),
      ADDRC(0) => '0',
      ADDRD(4 downto 1) => wb_wr_data_addr_w(4 downto 1),
      ADDRD(0) => \write_data_control.wb_wr_data_addr0_ns\,
      DIA(1 downto 0) => \write_buffer.wr_buf_in_data\(59 downto 58),
      DIB(1 downto 0) => \write_buffer.wr_buf_in_data\(57 downto 56),
      DIC(1 downto 0) => \write_buffer.wr_buf_in_data\(55 downto 54),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => wr_buf_out_data_w(59 downto 58),
      DOB(1 downto 0) => wr_buf_out_data_w(57 downto 56),
      DOC(1 downto 0) => wr_buf_out_data_w(55 downto 54),
      DOD(1 downto 0) => \NLW_write_buffer.wr_buffer_ram[9].RAM32M0_DOD_UNCONNECTED\(1 downto 0),
      WCLK => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      WE => wdf_rdy_ns
    );
\write_buffer.wr_buffer_ram[9].RAM32M0_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(59),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(59),
      O => \write_buffer.wr_buf_in_data\(59)
    );
\write_buffer.wr_buffer_ram[9].RAM32M0_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(58),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(58),
      O => \write_buffer.wr_buf_in_data\(58)
    );
\write_buffer.wr_buffer_ram[9].RAM32M0_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(57),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(57),
      O => \write_buffer.wr_buf_in_data\(57)
    );
\write_buffer.wr_buffer_ram[9].RAM32M0_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(56),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(56),
      O => \write_buffer.wr_buf_in_data\(56)
    );
\write_buffer.wr_buffer_ram[9].RAM32M0_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(55),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(55),
      O => \write_buffer.wr_buf_in_data\(55)
    );
\write_buffer.wr_buffer_ram[9].RAM32M0_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(54),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(54),
      O => \write_buffer.wr_buf_in_data\(54)
    );
\write_data_control.wb_wr_data_addr0_r_reg\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => \write_data_control.wb_wr_data_addr0_ns\,
      Q => \write_data_control.wb_wr_data_addr0_r\,
      R => '0'
    );
\write_data_control.wb_wr_data_addr_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wb_wr_data_addr_w(1),
      Q => \write_data_control.wb_wr_data_addr_r\(1),
      R => '0'
    );
\write_data_control.wb_wr_data_addr_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wb_wr_data_addr_w(2),
      Q => \write_data_control.wb_wr_data_addr_r\(2),
      R => '0'
    );
\write_data_control.wb_wr_data_addr_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wb_wr_data_addr_w(3),
      Q => \write_data_control.wb_wr_data_addr_r\(3),
      R => '0'
    );
\write_data_control.wb_wr_data_addr_r_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => '1',
      D => wb_wr_data_addr_w(4),
      Q => \write_data_control.wb_wr_data_addr_r\(4),
      R => '0'
    );
\write_data_control.wr_data_indx_r[0]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \write_data_control.wr_data_indx_r_reg\(0),
      O => \p_0_in__0__0\(0)
    );
\write_data_control.wr_data_indx_r[1]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \write_data_control.wr_data_indx_r_reg\(0),
      I1 => \write_data_control.wr_data_indx_r_reg\(1),
      O => \p_0_in__0__0\(1)
    );
\write_data_control.wr_data_indx_r[2]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"78"
    )
        port map (
      I0 => \write_data_control.wr_data_indx_r_reg\(0),
      I1 => \write_data_control.wr_data_indx_r_reg\(1),
      I2 => \write_data_control.wr_data_indx_r_reg\(2),
      O => \p_0_in__0__0\(2)
    );
\write_data_control.wr_data_indx_r[3]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"1100FFFF01000100"
    )
        port map (
      I0 => \write_data_control.wr_data_indx_r[3]_i_3_n_0\,
      I1 => \wr_req_counter.wr_req_cnt_r_reg[0]_1\,
      I2 => \occupied_counter.occ_cnt_reg_n_0_[15]\,
      I3 => \p_0_in__0_0\(1),
      I4 => app_wdf_rdy_r_copy1,
      I5 => \^p_0_in\(0),
      O => \write_data_control.wr_data_addr_le\
    );
\write_data_control.wr_data_indx_r[3]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7F80"
    )
        port map (
      I0 => \write_data_control.wr_data_indx_r_reg\(2),
      I1 => \write_data_control.wr_data_indx_r_reg\(1),
      I2 => \write_data_control.wr_data_indx_r_reg\(0),
      I3 => \write_data_control.wr_data_indx_r_reg\(3),
      O => \p_0_in__0__0\(3)
    );
\write_data_control.wr_data_indx_r[3]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00008000FFFFFFFF"
    )
        port map (
      I0 => app_wdf_wren_r1,
      I1 => app_wdf_end_r1,
      I2 => app_wdf_rdy_r_copy1,
      I3 => p_4_in,
      I4 => \^p_0_in\(0),
      I5 => ram_init_done_r,
      O => \write_data_control.wr_data_indx_r[3]_i_3_n_0\
    );
\write_data_control.wr_data_indx_r_reg[0]\: unisim.vcomponents.FDSE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => \write_data_control.wr_data_addr_le\,
      D => \p_0_in__0__0\(0),
      Q => \write_data_control.wr_data_indx_r_reg\(0),
      S => \wr_req_counter.wr_req_cnt_r_reg[0]_1\
    );
\write_data_control.wr_data_indx_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => \write_data_control.wr_data_addr_le\,
      D => \p_0_in__0__0\(1),
      Q => \write_data_control.wr_data_indx_r_reg\(1),
      R => \wr_req_counter.wr_req_cnt_r_reg[0]_1\
    );
\write_data_control.wr_data_indx_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => \write_data_control.wr_data_addr_le\,
      D => \p_0_in__0__0\(2),
      Q => \write_data_control.wr_data_indx_r_reg\(2),
      R => \wr_req_counter.wr_req_cnt_r_reg[0]_1\
    );
\write_data_control.wr_data_indx_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      CE => \write_data_control.wr_data_addr_le\,
      D => \p_0_in__0__0\(3),
      Q => \write_data_control.wr_data_indx_r_reg\(3),
      R => \wr_req_counter.wr_req_cnt_r_reg[0]_1\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mig_mig_7series_v4_2_arb_row_col is
  port (
    granted_row_r_reg_0 : out STD_LOGIC;
    granted_col_r_reg_0 : out STD_LOGIC;
    insert_maint_r1_lcl_reg_0 : out STD_LOGIC;
    \pre_4_1_1T_arb.granted_pre_r_reg_0\ : out STD_LOGIC;
    rnk_config_valid_r_lcl_reg_0 : out STD_LOGIC;
    granted_col_r_reg_1 : out STD_LOGIC;
    \grant_r_reg[2]\ : out STD_LOGIC;
    \periodic_rd_generation.read_this_rank_r_reg\ : out STD_LOGIC;
    Q : out STD_LOGIC_VECTOR ( 3 downto 0 );
    \periodic_rd_generation.read_this_rank\ : out STD_LOGIC;
    DIC : out STD_LOGIC_VECTOR ( 0 to 0 );
    mc_odt_ns : out STD_LOGIC_VECTOR ( 0 to 0 );
    D : out STD_LOGIC_VECTOR ( 0 to 0 );
    granted_col_r_reg_2 : out STD_LOGIC_VECTOR ( 0 to 0 );
    granted_col_r_reg_3 : out STD_LOGIC_VECTOR ( 0 to 0 );
    E : out STD_LOGIC_VECTOR ( 0 to 0 );
    \rtw_timer.rtw_cnt_r_reg[1]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    col_rd_wr : out STD_LOGIC;
    \grant_r_reg[0]\ : out STD_LOGIC;
    \wr_this_rank_r_reg[0]\ : out STD_LOGIC;
    \wr_this_rank_r_reg[0]_0\ : out STD_LOGIC;
    \grant_r_reg[3]\ : out STD_LOGIC;
    mc_we_n_ns : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \grant_r_reg[3]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
    mc_cas_n_ns : out STD_LOGIC_VECTOR ( 2 downto 0 );
    mc_ras_n_ns : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \pre_4_1_1T_arb.granted_pre_r_reg_1\ : out STD_LOGIC_VECTOR ( 8 downto 0 );
    \pre_4_1_1T_arb.granted_pre_r_reg_2\ : out STD_LOGIC_VECTOR ( 38 downto 0 );
    mc_cs_n_ns : out STD_LOGIC_VECTOR ( 0 to 0 );
    \grant_r_reg[1]\ : out STD_LOGIC;
    \rnk_config_strobe_r_reg[0]_0\ : out STD_LOGIC;
    rnk_config_valid_r_lcl_reg_1 : out STD_LOGIC;
    rnk_config_valid_r_lcl_reg_2 : out STD_LOGIC;
    rnk_config_valid_r_lcl_reg_3 : out STD_LOGIC;
    rnk_config_valid_r_lcl_reg_4 : out STD_LOGIC;
    override_demand_ns : out STD_LOGIC;
    \grant_r_reg[0]_0\ : out STD_LOGIC;
    \grant_r_reg[3]_1\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
    \last_master_r_reg[3]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    col_wr_data_buf_addr : out STD_LOGIC_VECTOR ( 3 downto 0 );
    act_this_rank : out STD_LOGIC;
    \grant_r_reg[0]_1\ : out STD_LOGIC;
    req_bank_rdy_r_reg : out STD_LOGIC;
    \rtw_timer.rtw_cnt_r_reg[1]_0\ : out STD_LOGIC;
    \wtr_timer.wtr_cnt_r_reg[1]\ : out STD_LOGIC;
    \grant_r_reg[0]_2\ : out STD_LOGIC;
    \last_master_r_reg[3]_0\ : in STD_LOGIC;
    rnk_config_strobe_ns : in STD_LOGIC;
    granted_col_ns : in STD_LOGIC;
    insert_maint_r1_lcl_reg_1 : in STD_LOGIC;
    \pre_4_1_1T_arb.granted_pre_ns\ : in STD_LOGIC;
    SR : in STD_LOGIC_VECTOR ( 0 to 0 );
    rnk_config_valid_r_lcl_reg_5 : in STD_LOGIC;
    \grant_r_reg[0]_3\ : in STD_LOGIC;
    \grant_r_reg[0]_4\ : in STD_LOGIC;
    \grant_r_reg[2]_0\ : in STD_LOGIC;
    \grant_r_reg[0]_5\ : in STD_LOGIC;
    \grant_r_reg[3]_2\ : in STD_LOGIC;
    granted_row_r_reg_1 : in STD_LOGIC;
    \grant_r_reg[3]_3\ : in STD_LOGIC;
    \periodic_rd_generation.read_this_rank_r\ : in STD_LOGIC;
    rd_this_rank_r : in STD_LOGIC_VECTOR ( 3 downto 0 );
    req_periodic_rd_r : in STD_LOGIC_VECTOR ( 3 downto 0 );
    \rtw_timer.rtw_cnt_r_reg[0]\ : in STD_LOGIC;
    \col_mux.col_periodic_rd_r\ : in STD_LOGIC;
    \cmd_pipe_plus.mc_odt_reg[0]\ : in STD_LOGIC;
    O : in STD_LOGIC_VECTOR ( 0 to 0 );
    \cmd_pipe_plus.mc_data_offset_1_reg[3]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \cmd_pipe_plus.mc_data_offset_reg[3]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \rtw_timer.rtw_cnt_r_reg[1]_1\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \cmd_pipe_plus.mc_data_offset_2_reg[0]\ : in STD_LOGIC;
    \cmd_pipe_plus.mc_data_offset_2_reg[0]_0\ : in STD_LOGIC;
    \i___22_i_1\ : in STD_LOGIC;
    rd_wr_r : in STD_LOGIC_VECTOR ( 0 to 0 );
    col_rd_wr_r : in STD_LOGIC;
    wr_this_rank_r : in STD_LOGIC_VECTOR ( 3 downto 0 );
    \grant_r[3]_i_8\ : in STD_LOGIC;
    \grant_r[3]_i_8_0\ : in STD_LOGIC;
    \cmd_pipe_plus.mc_we_n_reg[0]\ : in STD_LOGIC;
    \cmd_pipe_plus.mc_we_n_reg[0]_0\ : in STD_LOGIC;
    \cmd_pipe_plus.mc_address_reg[0]\ : in STD_LOGIC;
    \cmd_pipe_plus.mc_cas_n_reg[0]\ : in STD_LOGIC;
    maint_zq_r : in STD_LOGIC;
    maint_srx_r : in STD_LOGIC;
    \cmd_pipe_plus.mc_bank_reg[2]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
    \cmd_pipe_plus.mc_address_reg[3]\ : in STD_LOGIC;
    \cmd_pipe_plus.mc_bank_reg[2]_0\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
    \cmd_pipe_plus.mc_address_reg[0]_0\ : in STD_LOGIC;
    \cmd_pipe_plus.mc_bank_reg[2]_1\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
    \cmd_pipe_plus.mc_bank_reg[8]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
    \cmd_pipe_plus.mc_address_reg[41]\ : in STD_LOGIC_VECTOR ( 19 downto 0 );
    req_row_r : in STD_LOGIC_VECTOR ( 34 downto 0 );
    \cmd_pipe_plus.mc_address_reg[10]\ : in STD_LOGIC;
    \cmd_pipe_plus.mc_address_reg[10]_0\ : in STD_LOGIC;
    \cmd_pipe_plus.mc_we_n_reg[0]_1\ : in STD_LOGIC;
    \cmd_pipe_plus.mc_we_n_reg[2]\ : in STD_LOGIC;
    \grant_r_reg[0]_6\ : in STD_LOGIC;
    \grant_r_reg[0]_7\ : in STD_LOGIC;
    \grant_r_reg[0]_8\ : in STD_LOGIC;
    \grant_r_reg[1]_0\ : in STD_LOGIC;
    \grant_r_reg[3]_4\ : in STD_LOGIC;
    \grant_r_reg[3]_5\ : in STD_LOGIC;
    ofs_rdy_r : in STD_LOGIC;
    ofs_rdy_r_0 : in STD_LOGIC;
    ofs_rdy_r_1 : in STD_LOGIC;
    ofs_rdy_r_2 : in STD_LOGIC;
    inhbt_act_faw_r : in STD_LOGIC;
    req_data_buf_addr_r : in STD_LOGIC_VECTOR ( 15 downto 0 );
    \delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
    act_this_rank_r : in STD_LOGIC_VECTOR ( 3 downto 0 );
    \cmd_pipe_plus.mc_address_reg[23]\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
    \cmd_pipe_plus.mc_address_reg[23]_0\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
    \cmd_pipe_plus.mc_address_reg[23]_1\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
    \cmd_pipe_plus.mc_address_reg[23]_2\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
    \cmd_pipe_plus.mc_address_reg[24]\ : in STD_LOGIC;
    \cmd_pipe_plus.mc_address_reg[24]_0\ : in STD_LOGIC;
    \cmd_pipe_plus.mc_address_reg[24]_1\ : in STD_LOGIC;
    \cmd_pipe_plus.mc_address_reg[24]_2\ : in STD_LOGIC;
    \cmd_pipe_plus.mc_address_reg[38]\ : in STD_LOGIC;
    req_bank_rdy_r : in STD_LOGIC;
    \grant_r[2]_i_3\ : in STD_LOGIC;
    \grant_r[2]_i_3_0\ : in STD_LOGIC_VECTOR ( 0 to 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of mig_mig_7series_v4_2_arb_row_col : entity is "mig_7series_v4_2_arb_row_col";
end mig_mig_7series_v4_2_arb_row_col;

architecture STRUCTURE of mig_mig_7series_v4_2_arb_row_col is
  signal \genblk3[1].rnk_config_strobe_r_reg\ : STD_LOGIC;
  signal \genblk3[2].rnk_config_strobe_r_reg\ : STD_LOGIC;
  signal \^granted_col_r_reg_0\ : STD_LOGIC;
  signal granted_row_ns : STD_LOGIC;
  signal \^granted_row_r_reg_0\ : STD_LOGIC;
  signal \^insert_maint_r1_lcl_reg_0\ : STD_LOGIC;
  signal \^pre_4_1_1t_arb.granted_pre_r_reg_0\ : STD_LOGIC;
  signal rnk_config_strobe : STD_LOGIC;
  signal \^rnk_config_valid_r_lcl_reg_0\ : STD_LOGIC;
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of override_demand_r_i_1 : label is "soft_lutpair1149";
  attribute SOFT_HLUTNM of \rnk_config_strobe_r[0]_i_3\ : label is "soft_lutpair1149";
begin
  granted_col_r_reg_0 <= \^granted_col_r_reg_0\;
  granted_row_r_reg_0 <= \^granted_row_r_reg_0\;
  insert_maint_r1_lcl_reg_0 <= \^insert_maint_r1_lcl_reg_0\;
  \pre_4_1_1T_arb.granted_pre_r_reg_0\ <= \^pre_4_1_1t_arb.granted_pre_r_reg_0\;
  rnk_config_valid_r_lcl_reg_0 <= \^rnk_config_valid_r_lcl_reg_0\;
\cmd_pipe_plus.mc_cas_n[1]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \^granted_col_r_reg_0\,
      O => mc_cas_n_ns(1)
    );
\cmd_pipe_plus.mc_cs_n[0]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \^insert_maint_r1_lcl_reg_0\,
      I1 => \^granted_row_r_reg_0\,
      O => mc_cs_n_ns(0)
    );
\cmd_pipe_plus.mc_ras_n[2]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \^pre_4_1_1t_arb.granted_pre_r_reg_0\,
      O => mc_ras_n_ns(1)
    );
col_arb0: entity work.\mig_mig_7series_v4_2_round_robin_arb__parameterized1\
     port map (
      D(0) => D(0),
      DIC(0) => DIC(0),
      E(0) => E(0),
      O(0) => O(0),
      Q(3 downto 0) => Q(3 downto 0),
      \cmd_pipe_plus.mc_address_reg[23]\(9 downto 0) => \cmd_pipe_plus.mc_address_reg[23]\(9 downto 0),
      \cmd_pipe_plus.mc_address_reg[23]_0\(9 downto 0) => \cmd_pipe_plus.mc_address_reg[23]_0\(9 downto 0),
      \cmd_pipe_plus.mc_address_reg[23]_1\(9 downto 0) => \cmd_pipe_plus.mc_address_reg[23]_1\(9 downto 0),
      \cmd_pipe_plus.mc_address_reg[23]_2\(9 downto 0) => \cmd_pipe_plus.mc_address_reg[23]_2\(9 downto 0),
      \cmd_pipe_plus.mc_address_reg[24]\ => \cmd_pipe_plus.mc_address_reg[24]\,
      \cmd_pipe_plus.mc_address_reg[24]_0\ => \cmd_pipe_plus.mc_address_reg[24]_0\,
      \cmd_pipe_plus.mc_address_reg[24]_1\ => \cmd_pipe_plus.mc_address_reg[24]_1\,
      \cmd_pipe_plus.mc_address_reg[24]_2\ => \cmd_pipe_plus.mc_address_reg[24]_2\,
      \cmd_pipe_plus.mc_bank_reg[5]\(2 downto 0) => \cmd_pipe_plus.mc_bank_reg[8]\(2 downto 0),
      \cmd_pipe_plus.mc_bank_reg[5]_0\(2 downto 0) => \cmd_pipe_plus.mc_bank_reg[2]\(2 downto 0),
      \cmd_pipe_plus.mc_bank_reg[5]_1\(2 downto 0) => \cmd_pipe_plus.mc_bank_reg[2]_0\(2 downto 0),
      \cmd_pipe_plus.mc_bank_reg[5]_2\(2 downto 0) => \cmd_pipe_plus.mc_bank_reg[2]_1\(2 downto 0),
      \cmd_pipe_plus.mc_data_offset_1_reg[3]\(0) => \cmd_pipe_plus.mc_data_offset_1_reg[3]\(0),
      \cmd_pipe_plus.mc_data_offset_2_reg[0]\ => \^granted_col_r_reg_0\,
      \cmd_pipe_plus.mc_data_offset_2_reg[0]_0\ => \cmd_pipe_plus.mc_data_offset_2_reg[0]\,
      \cmd_pipe_plus.mc_data_offset_2_reg[0]_1\ => \cmd_pipe_plus.mc_data_offset_2_reg[0]_0\,
      \cmd_pipe_plus.mc_data_offset_reg[3]\(0) => \cmd_pipe_plus.mc_data_offset_reg[3]\(0),
      \cmd_pipe_plus.mc_odt_reg[0]\ => \cmd_pipe_plus.mc_odt_reg[0]\,
      \col_mux.col_periodic_rd_r\ => \col_mux.col_periodic_rd_r\,
      col_rd_wr => col_rd_wr,
      col_rd_wr_r => col_rd_wr_r,
      col_wr_data_buf_addr(3 downto 0) => col_wr_data_buf_addr(3 downto 0),
      \delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r_reg[3]\(3 downto 0) => \delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r_reg[3]\(3 downto 0),
      \genblk3[1].rnk_config_strobe_r_reg\ => \genblk3[1].rnk_config_strobe_r_reg\,
      \genblk3[2].rnk_config_strobe_r_reg\ => \genblk3[2].rnk_config_strobe_r_reg\,
      \grant_r[2]_i_3\ => \grant_r[2]_i_3\,
      \grant_r[2]_i_3_0\(0) => \grant_r[2]_i_3_0\(0),
      \grant_r[3]_i_10\ => \^rnk_config_valid_r_lcl_reg_0\,
      \grant_r[3]_i_8\ => \grant_r[3]_i_8\,
      \grant_r[3]_i_8_0\ => \grant_r[3]_i_8_0\,
      \grant_r_reg[0]_0\ => \grant_r_reg[0]\,
      \grant_r_reg[0]_1\ => \grant_r_reg[0]_2\,
      \grant_r_reg[0]_2\ => \grant_r_reg[0]_3\,
      \grant_r_reg[0]_3\ => \grant_r_reg[0]_4\,
      \grant_r_reg[0]_4\ => \grant_r_reg[0]_5\,
      \grant_r_reg[2]_0\ => \grant_r_reg[2]\,
      \grant_r_reg[2]_1\ => \grant_r_reg[2]_0\,
      \grant_r_reg[3]_0\ => \grant_r_reg[3]\,
      granted_col_r_reg => granted_col_r_reg_1,
      granted_col_r_reg_0(0) => granted_col_r_reg_2(0),
      granted_col_r_reg_1(0) => granted_col_r_reg_3(0),
      granted_col_r_reg_2(2 downto 0) => \pre_4_1_1T_arb.granted_pre_r_reg_1\(5 downto 3),
      granted_col_r_reg_3(10 downto 0) => \pre_4_1_1T_arb.granted_pre_r_reg_2\(24 downto 14),
      \i___22_i_1_0\ => \i___22_i_1\,
      \last_master_r_reg[1]_0\ => \cmd_pipe_plus.mc_cas_n_reg[0]\,
      \last_master_r_reg[3]_0\ => \last_master_r_reg[3]_0\,
      mc_odt_ns(0) => mc_odt_ns(0),
      ofs_rdy_r => ofs_rdy_r,
      ofs_rdy_r_0 => ofs_rdy_r_0,
      ofs_rdy_r_1 => ofs_rdy_r_1,
      ofs_rdy_r_2 => ofs_rdy_r_2,
      \periodic_rd_generation.read_this_rank\ => \periodic_rd_generation.read_this_rank\,
      \periodic_rd_generation.read_this_rank_r\ => \periodic_rd_generation.read_this_rank_r\,
      \periodic_rd_generation.read_this_rank_r_reg\ => \periodic_rd_generation.read_this_rank_r_reg\,
      rd_this_rank_r(3 downto 0) => rd_this_rank_r(3 downto 0),
      rd_wr_r(0) => rd_wr_r(0),
      req_bank_rdy_r => req_bank_rdy_r,
      req_bank_rdy_r_reg => req_bank_rdy_r_reg,
      req_data_buf_addr_r(15 downto 0) => req_data_buf_addr_r(15 downto 0),
      req_periodic_rd_r(3 downto 0) => req_periodic_rd_r(3 downto 0),
      rnk_config_strobe => rnk_config_strobe,
      rnk_config_valid_r_lcl_reg => rnk_config_valid_r_lcl_reg_1,
      rnk_config_valid_r_lcl_reg_0 => rnk_config_valid_r_lcl_reg_2,
      rnk_config_valid_r_lcl_reg_1 => rnk_config_valid_r_lcl_reg_3,
      rnk_config_valid_r_lcl_reg_2 => rnk_config_valid_r_lcl_reg_4,
      \rtw_timer.rtw_cnt_r_reg[0]\ => \rtw_timer.rtw_cnt_r_reg[0]\,
      \rtw_timer.rtw_cnt_r_reg[1]\(1 downto 0) => \rtw_timer.rtw_cnt_r_reg[1]\(1 downto 0),
      \rtw_timer.rtw_cnt_r_reg[1]_0\ => \rtw_timer.rtw_cnt_r_reg[1]_0\,
      \rtw_timer.rtw_cnt_r_reg[1]_1\(1 downto 0) => \rtw_timer.rtw_cnt_r_reg[1]_1\(1 downto 0),
      wr_this_rank_r(3 downto 0) => wr_this_rank_r(3 downto 0),
      \wr_this_rank_r_reg[0]\ => \wr_this_rank_r_reg[0]\,
      \wr_this_rank_r_reg[0]_0\ => \wr_this_rank_r_reg[0]_0\,
      \wtr_timer.wtr_cnt_r_reg[1]\ => \wtr_timer.wtr_cnt_r_reg[1]\
    );
\genblk3[1].rnk_config_strobe_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \last_master_r_reg[3]_0\,
      CE => '1',
      D => rnk_config_strobe,
      Q => \genblk3[1].rnk_config_strobe_r_reg\,
      R => '0'
    );
\genblk3[2].rnk_config_strobe_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \last_master_r_reg[3]_0\,
      CE => '1',
      D => \genblk3[1].rnk_config_strobe_r_reg\,
      Q => \genblk3[2].rnk_config_strobe_r_reg\,
      R => '0'
    );
granted_col_r_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \last_master_r_reg[3]_0\,
      CE => '1',
      D => granted_col_ns,
      Q => \^granted_col_r_reg_0\,
      R => '0'
    );
granted_row_r_reg: unisim.vcomponents.FDRE
     port map (
      C => \last_master_r_reg[3]_0\,
      CE => '1',
      D => granted_row_ns,
      Q => \^granted_row_r_reg_0\,
      R => '0'
    );
insert_maint_r1_lcl_reg: unisim.vcomponents.FDRE
     port map (
      C => \last_master_r_reg[3]_0\,
      CE => '1',
      D => insert_maint_r1_lcl_reg_1,
      Q => \^insert_maint_r1_lcl_reg_0\,
      R => '0'
    );
override_demand_r_i_1: unisim.vcomponents.LUT3
    generic map(
      INIT => X"FE"
    )
        port map (
      I0 => \genblk3[1].rnk_config_strobe_r_reg\,
      I1 => \genblk3[2].rnk_config_strobe_r_reg\,
      I2 => rnk_config_strobe,
      O => override_demand_ns
    );
\pre_4_1_1T_arb.granted_pre_r_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \last_master_r_reg[3]_0\,
      CE => '1',
      D => \pre_4_1_1T_arb.granted_pre_ns\,
      Q => \^pre_4_1_1t_arb.granted_pre_r_reg_0\,
      R => '0'
    );
\pre_4_1_1T_arb.pre_arb0\: entity work.\mig_mig_7series_v4_2_round_robin_arb__parameterized1_3\
     port map (
      Q(3 downto 0) => \grant_r_reg[3]_1\(3 downto 0),
      \cmd_pipe_plus.mc_address_reg[38]\ => \cmd_pipe_plus.mc_address_reg[38]\,
      \cmd_pipe_plus.mc_address_reg[41]\ => \^pre_4_1_1t_arb.granted_pre_r_reg_0\,
      \cmd_pipe_plus.mc_address_reg[41]_0\(18 downto 12) => \cmd_pipe_plus.mc_address_reg[41]\(19 downto 13),
      \cmd_pipe_plus.mc_address_reg[41]_0\(11 downto 0) => \cmd_pipe_plus.mc_address_reg[41]\(11 downto 0),
      \cmd_pipe_plus.mc_bank_reg[8]\(2 downto 0) => \cmd_pipe_plus.mc_bank_reg[8]\(2 downto 0),
      \cmd_pipe_plus.mc_bank_reg[8]_0\(2 downto 0) => \cmd_pipe_plus.mc_bank_reg[2]\(2 downto 0),
      \cmd_pipe_plus.mc_bank_reg[8]_1\(2 downto 0) => \cmd_pipe_plus.mc_bank_reg[2]_0\(2 downto 0),
      \cmd_pipe_plus.mc_bank_reg[8]_2\(2 downto 0) => \cmd_pipe_plus.mc_bank_reg[2]_1\(2 downto 0),
      \cmd_pipe_plus.mc_we_n_reg[2]\ => \cmd_pipe_plus.mc_we_n_reg[2]\,
      \cmd_pipe_plus.mc_we_n_reg[2]_0\ => \cmd_pipe_plus.mc_address_reg[10]\,
      \cmd_pipe_plus.mc_we_n_reg[2]_1\ => \cmd_pipe_plus.mc_we_n_reg[0]_0\,
      \cmd_pipe_plus.mc_we_n_reg[2]_2\ => \cmd_pipe_plus.mc_we_n_reg[0]_1\,
      \grant_r_reg[0]_0\ => \grant_r_reg[0]_6\,
      \grant_r_reg[0]_1\ => \grant_r_reg[0]_7\,
      \grant_r_reg[0]_2\ => \grant_r_reg[0]_8\,
      \grant_r_reg[1]_0\ => \grant_r_reg[1]_0\,
      \grant_r_reg[3]_0\ => \grant_r_reg[3]_4\,
      \last_master_r_reg[1]_0\ => \cmd_pipe_plus.mc_cas_n_reg[0]\,
      \last_master_r_reg[3]_0\(0) => \last_master_r_reg[3]\(0),
      \last_master_r_reg[3]_1\ => \last_master_r_reg[3]_0\,
      mc_cas_n_ns(0) => mc_cas_n_ns(2),
      mc_we_n_ns(0) => mc_we_n_ns(1),
      \pre_4_1_1T_arb.granted_pre_r_reg\(13 downto 0) => \pre_4_1_1T_arb.granted_pre_r_reg_2\(38 downto 25),
      \pre_4_1_1T_arb.granted_pre_r_reg_0\(2 downto 0) => \pre_4_1_1T_arb.granted_pre_r_reg_1\(8 downto 6),
      req_row_r(34 downto 0) => req_row_r(34 downto 0)
    );
\rnk_config_strobe_r[0]_i_3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFFE"
    )
        port map (
      I0 => rnk_config_strobe,
      I1 => \genblk3[2].rnk_config_strobe_r_reg\,
      I2 => \genblk3[1].rnk_config_strobe_r_reg\,
      I3 => \^rnk_config_valid_r_lcl_reg_0\,
      O => \rnk_config_strobe_r_reg[0]_0\
    );
\rnk_config_strobe_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \last_master_r_reg[3]_0\,
      CE => '1',
      D => rnk_config_strobe_ns,
      Q => rnk_config_strobe,
      R => '0'
    );
rnk_config_valid_r_lcl_reg: unisim.vcomponents.FDRE
     port map (
      C => \last_master_r_reg[3]_0\,
      CE => '1',
      D => rnk_config_valid_r_lcl_reg_5,
      Q => \^rnk_config_valid_r_lcl_reg_0\,
      R => SR(0)
    );
row_arb0: entity work.\mig_mig_7series_v4_2_round_robin_arb__parameterized1_4\
     port map (
      Q(3 downto 0) => \grant_r_reg[3]_0\(3 downto 0),
      act_this_rank => act_this_rank,
      act_this_rank_r(3 downto 0) => act_this_rank_r(3 downto 0),
      \cmd_pipe_plus.mc_address_reg[0]\ => \cmd_pipe_plus.mc_address_reg[0]\,
      \cmd_pipe_plus.mc_address_reg[0]_0\ => \cmd_pipe_plus.mc_address_reg[0]_0\,
      \cmd_pipe_plus.mc_address_reg[10]\ => \cmd_pipe_plus.mc_address_reg[10]\,
      \cmd_pipe_plus.mc_address_reg[10]_0\ => \cmd_pipe_plus.mc_address_reg[10]_0\,
      \cmd_pipe_plus.mc_address_reg[13]\(19 downto 0) => \cmd_pipe_plus.mc_address_reg[41]\(19 downto 0),
      \cmd_pipe_plus.mc_address_reg[3]\ => \cmd_pipe_plus.mc_address_reg[3]\,
      \cmd_pipe_plus.mc_bank_reg[2]\(2 downto 0) => \cmd_pipe_plus.mc_bank_reg[2]\(2 downto 0),
      \cmd_pipe_plus.mc_bank_reg[2]_0\(2 downto 0) => \cmd_pipe_plus.mc_bank_reg[2]_0\(2 downto 0),
      \cmd_pipe_plus.mc_bank_reg[2]_1\(2 downto 0) => \cmd_pipe_plus.mc_bank_reg[2]_1\(2 downto 0),
      \cmd_pipe_plus.mc_bank_reg[2]_2\(2 downto 0) => \cmd_pipe_plus.mc_bank_reg[8]\(2 downto 0),
      \cmd_pipe_plus.mc_cas_n_reg[0]\ => \cmd_pipe_plus.mc_cas_n_reg[0]\,
      \cmd_pipe_plus.mc_ras_n_reg[0]\ => \^insert_maint_r1_lcl_reg_0\,
      \cmd_pipe_plus.mc_we_n_reg[0]\ => \cmd_pipe_plus.mc_we_n_reg[0]\,
      \cmd_pipe_plus.mc_we_n_reg[0]_0\ => \cmd_pipe_plus.mc_we_n_reg[0]_0\,
      \cmd_pipe_plus.mc_we_n_reg[0]_1\ => \cmd_pipe_plus.mc_we_n_reg[0]_1\,
      \cmd_pipe_plus.mc_we_n_reg[0]_2\ => \cmd_pipe_plus.mc_we_n_reg[2]\,
      \grant_r_reg[0]_0\(2 downto 0) => \pre_4_1_1T_arb.granted_pre_r_reg_1\(2 downto 0),
      \grant_r_reg[0]_1\ => \grant_r_reg[0]_0\,
      \grant_r_reg[0]_2\ => \grant_r_reg[0]_1\,
      \grant_r_reg[1]_0\ => \grant_r_reg[1]\,
      \grant_r_reg[3]_0\ => \grant_r_reg[3]_2\,
      \grant_r_reg[3]_1\ => \grant_r_reg[3]_3\,
      \grant_r_reg[3]_2\ => \grant_r_reg[3]_5\,
      granted_row_ns => granted_row_ns,
      granted_row_r_reg => granted_row_r_reg_1,
      \i___70\ => insert_maint_r1_lcl_reg_1,
      inhbt_act_faw_r => inhbt_act_faw_r,
      \last_master_r_reg[2]_0\ => \^granted_row_r_reg_0\,
      \last_master_r_reg[3]_0\ => \last_master_r_reg[3]_0\,
      maint_srx_r => maint_srx_r,
      maint_zq_r => maint_zq_r,
      mc_cas_n_ns(0) => mc_cas_n_ns(0),
      mc_ras_n_ns(0) => mc_ras_n_ns(0),
      mc_we_n_ns(0) => mc_we_n_ns(0),
      req_row_r(33) => req_row_r(34),
      req_row_r(32 downto 0) => req_row_r(32 downto 0),
      \req_row_r_lcl_reg[13]\(13 downto 0) => \pre_4_1_1T_arb.granted_pre_r_reg_2\(13 downto 0)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mig_mig_7series_v4_2_bank_cntrl is
  port (
    rb_hit_busy_r_reg : out STD_LOGIC;
    E : out STD_LOGIC_VECTOR ( 0 to 0 );
    req_periodic_rd_r : out STD_LOGIC_VECTOR ( 0 to 0 );
    rd_wr_r : out STD_LOGIC_VECTOR ( 0 to 0 );
    pre_bm_end_r_reg : out STD_LOGIC;
    act_wait_r_lcl_reg : out STD_LOGIC;
    col_wait_r_reg : out STD_LOGIC;
    act_this_rank_r : out STD_LOGIC_VECTOR ( 0 to 0 );
    demand_priority_r_reg : out STD_LOGIC;
    demanded_prior_r_reg : out STD_LOGIC;
    ofs_rdy_r : out STD_LOGIC;
    wr_this_rank_r : out STD_LOGIC_VECTOR ( 0 to 0 );
    rd_this_rank_r : out STD_LOGIC_VECTOR ( 0 to 0 );
    q_has_rd : out STD_LOGIC;
    q_has_priority : out STD_LOGIC;
    pass_open_bank_r_lcl_reg : out STD_LOGIC;
    wait_for_maint_r : out STD_LOGIC;
    tail_r : out STD_LOGIC;
    head_r_lcl_reg : out STD_LOGIC;
    auto_pre_r_lcl_reg : out STD_LOGIC;
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[1]\ : out STD_LOGIC;
    idle_r_lcl_reg : out STD_LOGIC;
    rb_hit_busies_r : out STD_LOGIC_VECTOR ( 1 downto 0 );
    rd_wr_r_lcl_reg : out STD_LOGIC;
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[2]\ : out STD_LOGIC;
    bm_end_r1_reg : out STD_LOGIC;
    bm_end_r1_reg_0 : out STD_LOGIC;
    idle_r_lcl_reg_0 : out STD_LOGIC;
    idle_r_lcl_reg_1 : out STD_LOGIC;
    idle_r_lcl_reg_2 : out STD_LOGIC;
    q_entry_ns : out STD_LOGIC_VECTOR ( 0 to 0 );
    p_9_in : out STD_LOGIC;
    idle_r_lcl_reg_3 : out STD_LOGIC;
    idle_r_lcl_reg_4 : out STD_LOGIC;
    \q_entry_r_reg[0]\ : out STD_LOGIC;
    \q_entry_r_reg[0]_0\ : out STD_LOGIC;
    \q_entry_r_reg[1]\ : out STD_LOGIC;
    rb_hit_busy_r_reg_0 : out STD_LOGIC;
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]\ : out STD_LOGIC;
    rb_hit_busy_r_reg_1 : out STD_LOGIC;
    idle_r_lcl_reg_5 : out STD_LOGIC;
    ordered_r_lcl_reg : out STD_LOGIC;
    rd_wr_r_lcl_reg_0 : out STD_LOGIC;
    ordered_r_lcl_reg_0 : out STD_LOGIC;
    rnk_config_valid_r_lcl_reg : out STD_LOGIC;
    rd_wr_r_lcl_reg_1 : out STD_LOGIC;
    pre_passing_open_bank_r_reg : out STD_LOGIC;
    row_hit_r_reg : out STD_LOGIC;
    idle_r_lcl_reg_6 : out STD_LOGIC;
    act_wait_r_lcl_reg_0 : out STD_LOGIC;
    \compute_tail.tail_r_lcl_reg\ : out STD_LOGIC;
    idle_r_lcl_reg_7 : out STD_LOGIC;
    auto_pre_r_lcl_reg_0 : out STD_LOGIC;
    \req_row_r_lcl_reg[13]\ : out STD_LOGIC_VECTOR ( 13 downto 0 );
    demanded_prior_r_reg_0 : out STD_LOGIC;
    ofs_rdy_r0 : out STD_LOGIC;
    ofs_rdy_r0_0 : out STD_LOGIC;
    ofs_rdy_r0_1 : out STD_LOGIC;
    \req_data_buf_addr_r_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
    \req_bank_r_lcl_reg[2]\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
    \req_col_r_reg[9]\ : out STD_LOGIC_VECTOR ( 9 downto 0 );
    ofs_rdy_r_reg : in STD_LOGIC;
    periodic_rd_insert : in STD_LOGIC;
    req_wr_r_lcl0 : in STD_LOGIC;
    hi_priority : in STD_LOGIC;
    col_wait_r_reg_0 : in STD_LOGIC;
    phy_mc_ctl_full_r_reg : in STD_LOGIC;
    phy_mc_ctl_full : in STD_LOGIC;
    phy_mc_cmd_full_r_reg : in STD_LOGIC;
    of_ctl_full_v : in STD_LOGIC_VECTOR ( 0 to 0 );
    q_has_rd_r_reg : in STD_LOGIC;
    q_has_priority_r_reg : in STD_LOGIC;
    wait_for_maint_r_lcl_reg : in STD_LOGIC;
    wait_for_maint_r_lcl_reg_0 : in STD_LOGIC;
    \compute_tail.tail_r_lcl_reg_0\ : in STD_LOGIC;
    head_r_lcl_reg_0 : in STD_LOGIC;
    auto_pre_r_lcl_reg_1 : in STD_LOGIC;
    S : in STD_LOGIC_VECTOR ( 2 downto 0 );
    row_hit_r_reg_0 : in STD_LOGIC_VECTOR ( 0 to 0 );
    accept_internal_r_reg : in STD_LOGIC;
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[1]_0\ : in STD_LOGIC;
    accept_internal_r_reg_0 : in STD_LOGIC;
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_0\ : in STD_LOGIC;
    accept_internal_r_reg_1 : in STD_LOGIC;
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_0\ : in STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \rtp_timer_r_reg[1]\ : in STD_LOGIC;
    granted_col_r_reg : in STD_LOGIC;
    granted_col_r_reg_0 : in STD_LOGIC;
    granted_col_r_reg_1 : in STD_LOGIC;
    act_wait_r_lcl_reg_1 : in STD_LOGIC;
    pre_wait_r_reg : in STD_LOGIC;
    \ras_timer_r_reg[0]\ : in STD_LOGIC;
    \ras_timer_r_reg[0]_0\ : in STD_LOGIC;
    \ras_timer_r_reg[0]_1\ : in STD_LOGIC;
    \ras_timer_r_reg[0]_2\ : in STD_LOGIC;
    \q_entry_r_reg[1]_0\ : in STD_LOGIC;
    \q_entry_r_reg[1]_1\ : in STD_LOGIC;
    \q_entry_r_reg[1]_2\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \q_entry_r_reg[1]_3\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \q_entry_r_reg[1]_4\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \q_entry_r_reg[1]_5\ : in STD_LOGIC;
    \q_entry_r_reg[1]_6\ : in STD_LOGIC;
    \q_entry_r_reg[1]_7\ : in STD_LOGIC;
    accept_internal_r_reg_2 : in STD_LOGIC;
    head_r_lcl_reg_1 : in STD_LOGIC;
    \q_entry_r_reg[0]_1\ : in STD_LOGIC;
    \q_entry_r_reg[0]_2\ : in STD_LOGIC;
    \q_entry_r_reg[0]_3\ : in STD_LOGIC;
    \q_entry_r_reg[0]_4\ : in STD_LOGIC;
    \i___3_i_4\ : in STD_LOGIC;
    \order_q_r_reg[0]\ : in STD_LOGIC;
    \order_q_r_reg[0]_0\ : in STD_LOGIC;
    \order_q_r_reg[0]_1\ : in STD_LOGIC;
    req_bank_rdy_ns : in STD_LOGIC;
    rnk_config_valid_r : in STD_LOGIC;
    override_demand_ns : in STD_LOGIC;
    \rnk_config_strobe_r_reg[0]\ : in STD_LOGIC;
    req_bank_rdy_r_reg : in STD_LOGIC;
    req_bank_rdy_r_reg_0 : in STD_LOGIC;
    req_bank_rdy_r_reg_1 : in STD_LOGIC;
    rb_hit_busy_r_reg_2 : in STD_LOGIC;
    rd_wr_r_lcl_reg_2 : in STD_LOGIC;
    use_addr : in STD_LOGIC;
    accept_internal_r_reg_3 : in STD_LOGIC;
    accept_internal_r_reg_4 : in STD_LOGIC;
    pre_bm_end_r_reg_0 : in STD_LOGIC_VECTOR ( 0 to 0 );
    pass_open_bank_r_lcl_reg_0 : in STD_LOGIC;
    maint_req_r : in STD_LOGIC;
    pass_open_bank_r_lcl_reg_1 : in STD_LOGIC;
    pass_open_bank_r_lcl_reg_2 : in STD_LOGIC;
    auto_pre_r_lcl_reg_2 : in STD_LOGIC;
    pre_wait_r_reg_0 : in STD_LOGIC;
    demanded_prior_r_reg_1 : in STD_LOGIC;
    \grant_r[2]_i_3\ : in STD_LOGIC;
    override_demand_r : in STD_LOGIC;
    \grant_r[2]_i_3_0\ : in STD_LOGIC;
    \req_row_r_lcl_reg[13]_0\ : in STD_LOGIC_VECTOR ( 13 downto 0 );
    \ras_timer_r[1]_i_3\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \ras_timer_r_reg[0]_3\ : in STD_LOGIC;
    \ras_timer_r_reg[0]_4\ : in STD_LOGIC;
    \ras_timer_r_reg[0]_5\ : in STD_LOGIC;
    \ras_timer_r_reg[1]\ : in STD_LOGIC;
    \ras_timer_r_reg[1]_0\ : in STD_LOGIC;
    \ras_timer_r_reg[1]_1\ : in STD_LOGIC;
    demanded_prior_r_reg_2 : in STD_LOGIC;
    demanded_prior_r : in STD_LOGIC;
    demand_priority_r_reg_0 : in STD_LOGIC;
    phy_mc_data_full : in STD_LOGIC;
    ofs_rdy_r_reg_0 : in STD_LOGIC;
    ofs_rdy_r_reg_1 : in STD_LOGIC;
    ofs_rdy_r_reg_2 : in STD_LOGIC;
    \rtp_timer_r_reg[0]\ : in STD_LOGIC;
    \req_data_buf_addr_r_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
    \req_bank_r_lcl_reg[2]_0\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
    \req_col_r_reg[9]_0\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_1\ : in STD_LOGIC;
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_1\ : in STD_LOGIC;
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[1]_1\ : in STD_LOGIC;
    \q_entry_r_reg[0]_5\ : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of mig_mig_7series_v4_2_bank_cntrl : entity is "mig_7series_v4_2_bank_cntrl";
end mig_mig_7series_v4_2_bank_cntrl;

architecture STRUCTURE of mig_mig_7series_v4_2_bank_cntrl is
  signal \^e\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \^act_wait_r_lcl_reg\ : STD_LOGIC;
  signal \^auto_pre_r_lcl_reg\ : STD_LOGIC;
  signal bank_compare0_n_7 : STD_LOGIC;
  signal bank_compare0_n_9 : STD_LOGIC;
  signal bank_queue0_n_34 : STD_LOGIC;
  signal bank_state0_n_16 : STD_LOGIC;
  signal \^bm_end_r1_reg\ : STD_LOGIC;
  signal \^bm_end_r1_reg_0\ : STD_LOGIC;
  signal \^col_wait_r_reg\ : STD_LOGIC;
  signal idle_ns : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \^idle_r_lcl_reg\ : STD_LOGIC;
  signal ordered_r_lcl : STD_LOGIC;
  signal \^ordered_r_lcl_reg_0\ : STD_LOGIC;
  signal p_145_out : STD_LOGIC;
  signal pass_open_bank_ns : STD_LOGIC;
  signal pass_open_bank_r : STD_LOGIC;
  signal pre_bm_end_ns : STD_LOGIC;
  signal \^pre_bm_end_r_reg\ : STD_LOGIC;
  signal pre_passing_open_bank_ns : STD_LOGIC;
  signal pre_wait_r : STD_LOGIC;
  signal \^q_has_rd\ : STD_LOGIC;
  signal ras_timer_passed_ns : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal ras_timer_zero_r : STD_LOGIC;
  signal \^rb_hit_busy_r_reg\ : STD_LOGIC;
  signal \^rb_hit_busy_r_reg_0\ : STD_LOGIC;
  signal \^rb_hit_busy_r_reg_1\ : STD_LOGIC;
  signal \^rd_wr_r\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \^rd_wr_r_lcl_reg_0\ : STD_LOGIC;
  signal \^rd_wr_r_lcl_reg_1\ : STD_LOGIC;
  signal req_bank_rdy_ns_0 : STD_LOGIC;
  signal req_priority_r : STD_LOGIC;
  signal req_wr_r : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \^row_hit_r_reg\ : STD_LOGIC;
  signal start_wtp_timer0 : STD_LOGIC;
  signal \^wait_for_maint_r\ : STD_LOGIC;
begin
  E(0) <= \^e\(0);
  act_wait_r_lcl_reg <= \^act_wait_r_lcl_reg\;
  auto_pre_r_lcl_reg <= \^auto_pre_r_lcl_reg\;
  bm_end_r1_reg <= \^bm_end_r1_reg\;
  bm_end_r1_reg_0 <= \^bm_end_r1_reg_0\;
  col_wait_r_reg <= \^col_wait_r_reg\;
  idle_r_lcl_reg <= \^idle_r_lcl_reg\;
  ordered_r_lcl_reg_0 <= \^ordered_r_lcl_reg_0\;
  pre_bm_end_r_reg <= \^pre_bm_end_r_reg\;
  q_has_rd <= \^q_has_rd\;
  rb_hit_busy_r_reg <= \^rb_hit_busy_r_reg\;
  rb_hit_busy_r_reg_0 <= \^rb_hit_busy_r_reg_0\;
  rb_hit_busy_r_reg_1 <= \^rb_hit_busy_r_reg_1\;
  rd_wr_r(0) <= \^rd_wr_r\(0);
  rd_wr_r_lcl_reg_0 <= \^rd_wr_r_lcl_reg_0\;
  rd_wr_r_lcl_reg_1 <= \^rd_wr_r_lcl_reg_1\;
  row_hit_r_reg <= \^row_hit_r_reg\;
  wait_for_maint_r <= \^wait_for_maint_r\;
bank_compare0: entity work.mig_mig_7series_v4_2_bank_compare_2
     port map (
      E(0) => idle_ns(0),
      Q(0) => Q(0),
      S(2 downto 0) => S(2 downto 0),
      \grant_r_reg[0]\ => bank_compare0_n_7,
      hi_priority => hi_priority,
      maint_req_r => maint_req_r,
      \order_q_r_reg[1]\ => \order_q_r_reg[0]\,
      \order_q_r_reg[1]_0\ => \order_q_r_reg[0]_0\,
      \order_q_r_reg[1]_1\ => \order_q_r_reg[0]_1\,
      ordered_r_lcl => ordered_r_lcl,
      ordered_r_lcl_reg => \^ordered_r_lcl_reg_0\,
      ordered_r_lcl_reg_0 => \q_entry_r_reg[0]_1\,
      ordered_r_lcl_reg_1 => pre_wait_r_reg,
      p_145_out => p_145_out,
      pass_open_bank_r_lcl_reg => pass_open_bank_r_lcl_reg_1,
      pass_open_bank_r_lcl_reg_0 => pass_open_bank_r_lcl_reg_2,
      periodic_rd_insert => periodic_rd_insert,
      \q_entry_r[0]_i_2__1\ => \q_entry_r_reg[0]_2\,
      \q_entry_r[0]_i_2__1_0\ => \q_entry_r_reg[0]_3\,
      \q_entry_r[0]_i_2__1_1\ => \q_entry_r_reg[0]_4\,
      rb_hit_busy_r_reg_0 => \^rb_hit_busy_r_reg\,
      rb_hit_busy_r_reg_1 => \^rb_hit_busy_r_reg_1\,
      rb_hit_busy_r_reg_2 => \^rb_hit_busy_r_reg_0\,
      rd_wr_r_lcl_reg_0 => \^rd_wr_r\(0),
      rd_wr_r_lcl_reg_1 => \^rd_wr_r_lcl_reg_0\,
      rd_wr_r_lcl_reg_2 => \^rd_wr_r_lcl_reg_1\,
      rd_wr_r_lcl_reg_3 => bank_compare0_n_9,
      rd_wr_r_lcl_reg_4 => \^idle_r_lcl_reg\,
      rd_wr_r_lcl_reg_5 => rd_wr_r_lcl_reg_2,
      \req_bank_r_lcl_reg[2]_0\(2 downto 0) => \req_bank_r_lcl_reg[2]\(2 downto 0),
      \req_bank_r_lcl_reg[2]_1\(2 downto 0) => \req_bank_r_lcl_reg[2]_0\(2 downto 0),
      req_bank_rdy_r_reg => req_bank_rdy_r_reg,
      req_bank_rdy_r_reg_0 => req_bank_rdy_r_reg_0,
      req_bank_rdy_r_reg_1 => req_bank_rdy_r_reg_1,
      \req_col_r_reg[9]_0\(9 downto 0) => \req_col_r_reg[9]\(9 downto 0),
      \req_col_r_reg[9]_1\ => ofs_rdy_r_reg,
      \req_col_r_reg[9]_2\(9 downto 0) => \req_col_r_reg[9]_0\(9 downto 0),
      \req_data_buf_addr_r_reg[3]_0\(3 downto 0) => \req_data_buf_addr_r_reg[3]\(3 downto 0),
      \req_data_buf_addr_r_reg[3]_1\ => \^e\(0),
      \req_data_buf_addr_r_reg[3]_2\(3 downto 0) => \req_data_buf_addr_r_reg[3]_0\(3 downto 0),
      req_periodic_rd_r(0) => req_periodic_rd_r(0),
      req_priority_r => req_priority_r,
      \req_row_r_lcl_reg[13]_0\(13 downto 0) => \req_row_r_lcl_reg[13]\(13 downto 0),
      \req_row_r_lcl_reg[13]_1\(13 downto 0) => \req_row_r_lcl_reg[13]_0\(13 downto 0),
      req_wr_r(0) => req_wr_r(0),
      req_wr_r_lcl0 => req_wr_r_lcl0,
      row_hit_r_reg_0 => \^row_hit_r_reg\,
      row_hit_r_reg_1(0) => row_hit_r_reg_0(0),
      start_wtp_timer0 => start_wtp_timer0,
      wait_for_maint_r => \^wait_for_maint_r\
    );
bank_queue0: entity work.mig_mig_7series_v4_2_bank_queue
     port map (
      D(1 downto 0) => ras_timer_passed_ns(1 downto 0),
      E(0) => idle_ns(0),
      Q(0) => Q(0),
      accept_internal_r_reg => accept_internal_r_reg,
      accept_internal_r_reg_0 => accept_internal_r_reg_0,
      accept_internal_r_reg_1 => accept_internal_r_reg_1,
      accept_internal_r_reg_2 => accept_internal_r_reg_2,
      accept_internal_r_reg_3 => accept_internal_r_reg_3,
      accept_internal_r_reg_4 => accept_internal_r_reg_4,
      act_wait_r_lcl_reg => act_wait_r_lcl_reg_0,
      auto_pre_r_lcl_reg_0 => \^auto_pre_r_lcl_reg\,
      auto_pre_r_lcl_reg_1 => auto_pre_r_lcl_reg_1,
      auto_pre_r_lcl_reg_2 => auto_pre_r_lcl_reg_2,
      bm_end_r1_reg => \^rd_wr_r\(0),
      \compute_tail.tail_r_lcl_reg_0\ => \compute_tail.tail_r_lcl_reg\,
      \compute_tail.tail_r_lcl_reg_1\ => \compute_tail.tail_r_lcl_reg_0\,
      \grant_r[2]_i_3_0\ => req_bank_rdy_r_reg,
      \grant_r[2]_i_3_1\ => \^rd_wr_r_lcl_reg_1\,
      \grant_r[2]_i_3_2\ => req_bank_rdy_r_reg_0,
      \grant_r[2]_i_3_3\ => req_bank_rdy_r_reg_1,
      granted_col_r_reg => granted_col_r_reg,
      granted_col_r_reg_0 => granted_col_r_reg_0,
      granted_col_r_reg_1 => bank_state0_n_16,
      granted_col_r_reg_2 => granted_col_r_reg_1,
      head_r_lcl_reg_0 => head_r_lcl_reg,
      head_r_lcl_reg_1 => phy_mc_cmd_full_r_reg,
      head_r_lcl_reg_2 => head_r_lcl_reg_0,
      head_r_lcl_reg_3 => head_r_lcl_reg_1,
      \i___3_i_4\ => \i___3_i_4\,
      \i___70\ => \^act_wait_r_lcl_reg\,
      idle_r_lcl_reg_0 => \^e\(0),
      idle_r_lcl_reg_1 => \^idle_r_lcl_reg\,
      idle_r_lcl_reg_2 => idle_r_lcl_reg_0,
      idle_r_lcl_reg_3 => idle_r_lcl_reg_1,
      idle_r_lcl_reg_4 => idle_r_lcl_reg_2,
      idle_r_lcl_reg_5 => idle_r_lcl_reg_3,
      idle_r_lcl_reg_6 => idle_r_lcl_reg_4,
      idle_r_lcl_reg_7 => idle_r_lcl_reg_5,
      idle_r_lcl_reg_8 => idle_r_lcl_reg_6,
      idle_r_lcl_reg_9 => idle_r_lcl_reg_7,
      \order_q_r_reg[0]_0\ => bank_queue0_n_34,
      \order_q_r_reg[0]_1\ => \order_q_r_reg[0]\,
      \order_q_r_reg[0]_2\ => \order_q_r_reg[0]_0\,
      \order_q_r_reg[0]_3\ => \order_q_r_reg[0]_1\,
      \order_q_r_reg[0]_4\ => \rtp_timer_r_reg[1]\,
      \order_q_r_reg[1]_0\ => \^ordered_r_lcl_reg_0\,
      ordered_r_lcl => ordered_r_lcl,
      ordered_r_lcl_reg_0 => ordered_r_lcl_reg,
      ordered_r_lcl_reg_1 => bank_compare0_n_7,
      p_145_out => p_145_out,
      p_9_in => p_9_in,
      pass_open_bank_ns => pass_open_bank_ns,
      pass_open_bank_r => pass_open_bank_r,
      pass_open_bank_r_lcl_reg_0 => pass_open_bank_r_lcl_reg,
      pass_open_bank_r_lcl_reg_1 => pass_open_bank_r_lcl_reg_0,
      pass_open_bank_r_lcl_reg_2 => \^row_hit_r_reg\,
      pre_bm_end_ns => pre_bm_end_ns,
      pre_bm_end_r_reg_0 => \^pre_bm_end_r_reg\,
      pre_passing_open_bank_ns => pre_passing_open_bank_ns,
      pre_passing_open_bank_r_reg_0 => pre_passing_open_bank_r_reg,
      pre_wait_r => pre_wait_r,
      q_entry_ns(0) => q_entry_ns(0),
      \q_entry_r_reg[0]_0\ => \q_entry_r_reg[0]\,
      \q_entry_r_reg[0]_1\ => \q_entry_r_reg[0]_0\,
      \q_entry_r_reg[0]_2\ => \q_entry_r_reg[0]_1\,
      \q_entry_r_reg[0]_3\ => \q_entry_r_reg[0]_2\,
      \q_entry_r_reg[0]_4\ => \q_entry_r_reg[0]_3\,
      \q_entry_r_reg[0]_5\ => \q_entry_r_reg[0]_4\,
      \q_entry_r_reg[0]_6\ => \^rb_hit_busy_r_reg\,
      \q_entry_r_reg[0]_7\ => \q_entry_r_reg[0]_5\,
      \q_entry_r_reg[1]_0\ => \q_entry_r_reg[1]\,
      \q_entry_r_reg[1]_1\ => \q_entry_r_reg[1]_0\,
      \q_entry_r_reg[1]_10\ => \^rb_hit_busy_r_reg_1\,
      \q_entry_r_reg[1]_2\ => \q_entry_r_reg[1]_1\,
      \q_entry_r_reg[1]_3\(0) => \q_entry_r_reg[1]_2\(0),
      \q_entry_r_reg[1]_4\(0) => \q_entry_r_reg[1]_3\(0),
      \q_entry_r_reg[1]_5\(0) => \q_entry_r_reg[1]_4\(0),
      \q_entry_r_reg[1]_6\ => \q_entry_r_reg[1]_5\,
      \q_entry_r_reg[1]_7\ => \q_entry_r_reg[1]_6\,
      \q_entry_r_reg[1]_8\ => \q_entry_r_reg[1]_7\,
      \q_entry_r_reg[1]_9\ => \^rb_hit_busy_r_reg_0\,
      q_has_priority => q_has_priority,
      q_has_priority_r_reg_0 => q_has_priority_r_reg,
      q_has_priority_r_reg_1 => pre_wait_r_reg,
      q_has_rd => \^q_has_rd\,
      q_has_rd_r_reg_0 => ofs_rdy_r_reg,
      q_has_rd_r_reg_1 => q_has_rd_r_reg,
      \ras_timer_r_reg[0]\ => \^bm_end_r1_reg\,
      \ras_timer_r_reg[0]_0\ => \ras_timer_r_reg[0]\,
      \ras_timer_r_reg[0]_1\ => \ras_timer_r_reg[0]_0\,
      \ras_timer_r_reg[0]_2\ => \ras_timer_r_reg[0]_1\,
      \ras_timer_r_reg[0]_3\ => \ras_timer_r_reg[0]_2\,
      \ras_timer_r_reg[0]_4\ => \ras_timer_r_reg[0]_3\,
      \ras_timer_r_reg[0]_5\ => \ras_timer_r_reg[0]_4\,
      \ras_timer_r_reg[0]_6\ => \ras_timer_r_reg[0]_5\,
      \ras_timer_r_reg[1]\ => \^bm_end_r1_reg_0\,
      \ras_timer_r_reg[1]_0\ => \ras_timer_r_reg[1]\,
      \ras_timer_r_reg[1]_1\ => \ras_timer_r_reg[1]_0\,
      \ras_timer_r_reg[1]_2\ => \ras_timer_r_reg[1]_1\,
      ras_timer_zero_r => ras_timer_zero_r,
      \rb_hit_busies.rb_hit_busies_r_lcl_reg[1]_0\ => \rb_hit_busies.rb_hit_busies_r_lcl_reg[1]\,
      \rb_hit_busies.rb_hit_busies_r_lcl_reg[1]_1\ => \rb_hit_busies.rb_hit_busies_r_lcl_reg[1]_0\,
      \rb_hit_busies.rb_hit_busies_r_lcl_reg[1]_2\ => \rb_hit_busies.rb_hit_busies_r_lcl_reg[1]_1\,
      \rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_0\ => rb_hit_busies_r(0),
      \rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_1\ => \rb_hit_busies.rb_hit_busies_r_lcl_reg[2]\,
      \rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_2\ => \rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_0\,
      \rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_3\ => \rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_1\,
      \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_0\ => rb_hit_busies_r(1),
      \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_1\ => \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]\,
      \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_2\ => \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_0\,
      \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_3\ => \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_1\,
      rb_hit_busy_r_reg => rb_hit_busy_r_reg_2,
      rd_wr_r_lcl_reg => rd_wr_r_lcl_reg,
      req_bank_rdy_ns => req_bank_rdy_ns_0,
      req_bank_rdy_r_reg => \^rd_wr_r_lcl_reg_0\,
      req_bank_rdy_r_reg_0 => \^col_wait_r_reg\,
      req_priority_r => req_priority_r,
      req_wr_r(0) => req_wr_r(0),
      tail_r => tail_r,
      use_addr => use_addr,
      wait_for_maint_r => \^wait_for_maint_r\,
      wait_for_maint_r_lcl_reg_0 => wait_for_maint_r_lcl_reg,
      wait_for_maint_r_lcl_reg_1 => wait_for_maint_r_lcl_reg_0
    );
bank_state0: entity work.mig_mig_7series_v4_2_bank_state
     port map (
      D(1 downto 0) => ras_timer_passed_ns(1 downto 0),
      Q(1 downto 0) => Q(1 downto 0),
      act_this_rank_r(0) => act_this_rank_r(0),
      act_wait_r_lcl_reg_0 => \^act_wait_r_lcl_reg\,
      act_wait_r_lcl_reg_1 => act_wait_r_lcl_reg_1,
      auto_pre_r_lcl_reg => auto_pre_r_lcl_reg_0,
      bm_end_r1_reg_0 => \^bm_end_r1_reg_0\,
      bm_end_r1_reg_1 => \^bm_end_r1_reg\,
      bm_end_r1_reg_2 => \^pre_bm_end_r_reg\,
      col_wait_r_reg_0 => \^col_wait_r_reg\,
      col_wait_r_reg_1 => col_wait_r_reg_0,
      demand_priority_r_reg_0 => demand_priority_r_reg,
      demand_priority_r_reg_1 => bank_state0_n_16,
      demand_priority_r_reg_2 => \^idle_r_lcl_reg\,
      demand_priority_r_reg_3 => bank_queue0_n_34,
      demand_priority_r_reg_4 => demand_priority_r_reg_0,
      demanded_prior_r => demanded_prior_r,
      demanded_prior_r_reg_0 => demanded_prior_r_reg,
      demanded_prior_r_reg_1 => demanded_prior_r_reg_0,
      demanded_prior_r_reg_2 => demanded_prior_r_reg_1,
      demanded_prior_r_reg_3 => demanded_prior_r_reg_2,
      \grant_r[2]_i_3\ => \grant_r[2]_i_3\,
      \grant_r[2]_i_3_0\ => \grant_r[2]_i_3_0\,
      of_ctl_full_v(0) => of_ctl_full_v(0),
      ofs_rdy_r => ofs_rdy_r,
      ofs_rdy_r0 => ofs_rdy_r0,
      ofs_rdy_r0_0 => ofs_rdy_r0_0,
      ofs_rdy_r0_1 => ofs_rdy_r0_1,
      ofs_rdy_r_reg_0 => ofs_rdy_r_reg,
      ofs_rdy_r_reg_1 => ofs_rdy_r_reg_0,
      ofs_rdy_r_reg_2 => ofs_rdy_r_reg_1,
      ofs_rdy_r_reg_3 => ofs_rdy_r_reg_2,
      override_demand_ns => override_demand_ns,
      override_demand_r => override_demand_r,
      pass_open_bank_ns => pass_open_bank_ns,
      pass_open_bank_r => pass_open_bank_r,
      phy_mc_cmd_full_r_reg_0 => phy_mc_cmd_full_r_reg,
      phy_mc_ctl_full => phy_mc_ctl_full,
      phy_mc_ctl_full_r_reg_0 => phy_mc_ctl_full_r_reg,
      phy_mc_data_full => phy_mc_data_full,
      pre_bm_end_ns => pre_bm_end_ns,
      pre_bm_end_r_reg(0) => pre_bm_end_r_reg_0(0),
      pre_bm_end_r_reg_0 => \^auto_pre_r_lcl_reg\,
      pre_passing_open_bank_ns => pre_passing_open_bank_ns,
      pre_wait_r => pre_wait_r,
      pre_wait_r_reg_0 => pre_wait_r_reg,
      pre_wait_r_reg_1 => pre_wait_r_reg_0,
      q_has_rd => \^q_has_rd\,
      \ras_timer_r[1]_i_3_0\(0) => \ras_timer_r[1]_i_3\(0),
      ras_timer_zero_r => ras_timer_zero_r,
      ras_timer_zero_r_reg_0 => bank_compare0_n_9,
      rd_this_rank_r(0) => rd_this_rank_r(0),
      \rd_this_rank_r_reg[0]_0\ => \^rd_wr_r\(0),
      req_bank_rdy_ns => req_bank_rdy_ns,
      req_bank_rdy_ns_0 => req_bank_rdy_ns_0,
      req_wr_r(0) => req_wr_r(0),
      \rnk_config_strobe_r_reg[0]\ => \rnk_config_strobe_r_reg[0]\,
      rnk_config_valid_r => rnk_config_valid_r,
      rnk_config_valid_r_lcl_reg => rnk_config_valid_r_lcl_reg,
      \rtp_timer_r_reg[0]_0\ => \rtp_timer_r_reg[0]\,
      \rtp_timer_r_reg[1]_0\ => \rtp_timer_r_reg[1]\,
      start_wtp_timer0 => start_wtp_timer0,
      wr_this_rank_r(0) => wr_this_rank_r(0)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \mig_mig_7series_v4_2_bank_cntrl__parameterized0\ is
  port (
    rb_hit_busy_r_reg : out STD_LOGIC;
    E : out STD_LOGIC_VECTOR ( 0 to 0 );
    req_periodic_rd_r : out STD_LOGIC_VECTOR ( 0 to 0 );
    rd_wr_r_lcl_reg : out STD_LOGIC;
    req_wr_r_lcl_reg : out STD_LOGIC;
    act_wait_r_lcl_reg : out STD_LOGIC;
    act_this_rank_r : out STD_LOGIC_VECTOR ( 0 to 0 );
    wr_this_rank_r : out STD_LOGIC_VECTOR ( 0 to 0 );
    rd_this_rank_r : out STD_LOGIC_VECTOR ( 0 to 0 );
    bm_end_r1 : out STD_LOGIC;
    col_wait_r_reg : out STD_LOGIC;
    req_bank_rdy_r : out STD_LOGIC;
    req_bank_rdy_ns : out STD_LOGIC;
    demand_priority_r_reg : out STD_LOGIC;
    demanded_prior_r_reg : out STD_LOGIC;
    ofs_rdy_r : out STD_LOGIC;
    pass_open_bank_r_lcl_reg : out STD_LOGIC;
    pre_bm_end_r : out STD_LOGIC;
    q_has_rd_3 : out STD_LOGIC;
    q_has_priority : out STD_LOGIC;
    wait_for_maint_r_13 : out STD_LOGIC;
    head_r_lcl_reg : out STD_LOGIC;
    ordered_r_lcl_reg : out STD_LOGIC;
    tail_r_16 : out STD_LOGIC;
    auto_pre_r_lcl_reg : out STD_LOGIC;
    granted_col_ns : out STD_LOGIC;
    rd_wr_r_lcl_reg_0 : out STD_LOGIC;
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    idle_r_lcl_reg : out STD_LOGIC;
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[5]\ : out STD_LOGIC;
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_0\ : out STD_LOGIC;
    pre_passing_open_bank_r_reg : out STD_LOGIC;
    row_hit_r_reg : out STD_LOGIC;
    pre_bm_end_r_reg : out STD_LOGIC;
    rnk_config_strobe_ns : out STD_LOGIC;
    demand_priority_r_reg_0 : out STD_LOGIC;
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[2]\ : out STD_LOGIC;
    \q_entry_r_reg[0]\ : out STD_LOGIC;
    \q_entry_r_reg[0]_0\ : out STD_LOGIC;
    \q_entry_r_reg[1]\ : out STD_LOGIC;
    \q_entry_r_reg[1]_0\ : out STD_LOGIC;
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_0\ : out STD_LOGIC;
    bm_end_r1_reg : out STD_LOGIC;
    \ras_timer_r_reg[1]\ : out STD_LOGIC;
    \compute_tail.tail_r_lcl_reg\ : out STD_LOGIC;
    act_wait_r_lcl_reg_0 : out STD_LOGIC;
    auto_pre_r_lcl_reg_0 : out STD_LOGIC;
    \req_row_r_lcl_reg[13]\ : out STD_LOGIC_VECTOR ( 13 downto 0 );
    demanded_prior_r_reg_0 : out STD_LOGIC;
    \req_data_buf_addr_r_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
    \req_bank_r_lcl_reg[2]\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
    \req_col_r_reg[9]\ : out STD_LOGIC_VECTOR ( 9 downto 0 );
    demand_priority_r_reg_1 : in STD_LOGIC;
    periodic_rd_insert : in STD_LOGIC;
    req_wr_r_lcl0 : in STD_LOGIC;
    hi_priority : in STD_LOGIC;
    col_wait_r_reg_0 : in STD_LOGIC;
    ofs_rdy_r_reg : in STD_LOGIC;
    ofs_rdy_r0 : in STD_LOGIC;
    q_has_rd_r_reg : in STD_LOGIC;
    auto_pre_r_lcl_reg_1 : in STD_LOGIC;
    q_has_priority_r_reg : in STD_LOGIC;
    wait_for_maint_r_lcl_reg : in STD_LOGIC;
    wait_for_maint_r_lcl_reg_0 : in STD_LOGIC;
    head_r_lcl_reg_0 : in STD_LOGIC;
    \compute_tail.tail_r_lcl_reg_0\ : in STD_LOGIC;
    auto_pre_r_lcl_reg_2 : in STD_LOGIC;
    row_hit_r_reg_0 : in STD_LOGIC_VECTOR ( 0 to 0 );
    row_hit_r_reg_1 : in STD_LOGIC_VECTOR ( 0 to 0 );
    granted_col_r_reg : in STD_LOGIC;
    granted_col_r_reg_0 : in STD_LOGIC;
    granted_col_r_reg_1 : in STD_LOGIC;
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_0\ : in STD_LOGIC;
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_1\ : in STD_LOGIC;
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_1\ : in STD_LOGIC;
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_2\ : in STD_LOGIC;
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[4]\ : in STD_LOGIC;
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_0\ : in STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \rtp_timer_r_reg[1]\ : in STD_LOGIC;
    granted_col_r_reg_2 : in STD_LOGIC;
    granted_col_r_reg_3 : in STD_LOGIC;
    granted_col_r_reg_4 : in STD_LOGIC;
    rb_hit_busies_r : in STD_LOGIC_VECTOR ( 0 to 0 );
    rb_hit_busies_r_0 : in STD_LOGIC_VECTOR ( 0 to 0 );
    rb_hit_busy_r_reg_0 : in STD_LOGIC;
    rd_wr_r_lcl_reg_1 : in STD_LOGIC;
    use_addr : in STD_LOGIC;
    rb_hit_busy_r_reg_1 : in STD_LOGIC;
    rb_hit_busy_r_reg_2 : in STD_LOGIC;
    pre_bm_end_r_reg_0 : in STD_LOGIC_VECTOR ( 0 to 0 );
    act_wait_r_lcl_reg_1 : in STD_LOGIC;
    pass_open_bank_r_lcl_reg_0 : in STD_LOGIC;
    \rnk_config_strobe_r_reg[0]\ : in STD_LOGIC;
    req_bank_rdy_ns_1 : in STD_LOGIC;
    \rnk_config_strobe_r_reg[0]_0\ : in STD_LOGIC;
    \rnk_config_strobe_r_reg[0]_1\ : in STD_LOGIC;
    req_bank_rdy_r_reg : in STD_LOGIC;
    \grant_r[3]_i_2\ : in STD_LOGIC;
    \grant_r[3]_i_2_0\ : in STD_LOGIC;
    \grant_r[3]_i_2_1\ : in STD_LOGIC;
    \grant_r[3]_i_2_2\ : in STD_LOGIC;
    \order_q_r_reg[1]\ : in STD_LOGIC;
    head_r_lcl_reg_1 : in STD_LOGIC;
    head_r_lcl_reg_2 : in STD_LOGIC;
    head_r_lcl_reg_3 : in STD_LOGIC;
    act_wait_r_lcl_reg_2 : in STD_LOGIC_VECTOR ( 0 to 0 );
    \ras_timer_r_reg[0]\ : in STD_LOGIC;
    \ras_timer_r_reg[0]_0\ : in STD_LOGIC;
    \ras_timer_r_reg[0]_1\ : in STD_LOGIC;
    \grant_r[3]_i_2_3\ : in STD_LOGIC;
    \ras_timer_r_reg[0]_2\ : in STD_LOGIC;
    \i___34\ : in STD_LOGIC;
    \i___34_0\ : in STD_LOGIC;
    \i___34_1\ : in STD_LOGIC;
    \ras_timer_r_reg[1]_0\ : in STD_LOGIC;
    \ras_timer_r_reg[1]_1\ : in STD_LOGIC;
    \ras_timer_r_reg[1]_2\ : in STD_LOGIC;
    \ras_timer_r_reg[0]_3\ : in STD_LOGIC;
    \ras_timer_r_reg[0]_4\ : in STD_LOGIC;
    \ras_timer_r_reg[0]_5\ : in STD_LOGIC;
    maint_req_r : in STD_LOGIC;
    pass_open_bank_r_lcl_reg_1 : in STD_LOGIC;
    pass_open_bank_r_lcl_reg_2 : in STD_LOGIC;
    auto_pre_r_lcl_reg_3 : in STD_LOGIC;
    ras_timer_zero_r_reg : in STD_LOGIC;
    \req_row_r_lcl_reg[13]_0\ : in STD_LOGIC_VECTOR ( 13 downto 0 );
    ras_timer_zero_r_reg_0 : in STD_LOGIC;
    demanded_prior_r_reg_1 : in STD_LOGIC;
    demanded_prior_r_reg_2 : in STD_LOGIC;
    demanded_prior_r_reg_3 : in STD_LOGIC;
    demand_priority_r_reg_2 : in STD_LOGIC;
    \starve_limit_cntr_r_reg[0]\ : in STD_LOGIC;
    \rtp_timer_r_reg[0]\ : in STD_LOGIC;
    \req_data_buf_addr_r_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
    \req_bank_r_lcl_reg[2]_0\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
    \req_col_r_reg[9]_0\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_2\ : in STD_LOGIC;
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_3\ : in STD_LOGIC;
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_1\ : in STD_LOGIC;
    q_entry_ns : in STD_LOGIC_VECTOR ( 0 to 0 );
    \q_entry_r_reg[1]_1\ : in STD_LOGIC;
    \q_entry_r_reg[0]_1\ : in STD_LOGIC;
    \q_entry_r_reg[0]_2\ : in STD_LOGIC;
    \order_q_r_reg[1]_0\ : in STD_LOGIC;
    \order_q_r_reg[0]\ : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \mig_mig_7series_v4_2_bank_cntrl__parameterized0\ : entity is "mig_7series_v4_2_bank_cntrl";
end \mig_mig_7series_v4_2_bank_cntrl__parameterized0\;

architecture STRUCTURE of \mig_mig_7series_v4_2_bank_cntrl__parameterized0\ is
  signal \^e\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \^act_wait_r_lcl_reg\ : STD_LOGIC;
  signal \^auto_pre_r_lcl_reg\ : STD_LOGIC;
  signal bank_compare0_n_5 : STD_LOGIC;
  signal bank_queue0_n_23 : STD_LOGIC;
  signal \^bm_end_r1_reg\ : STD_LOGIC;
  signal \^col_wait_r_reg\ : STD_LOGIC;
  signal idle_ns : STD_LOGIC_VECTOR ( 1 to 1 );
  signal \^idle_r_lcl_reg\ : STD_LOGIC;
  signal \^ordered_r_lcl_reg\ : STD_LOGIC;
  signal p_106_out : STD_LOGIC;
  signal p_91_out : STD_LOGIC;
  signal pass_open_bank_ns : STD_LOGIC;
  signal \^pass_open_bank_r_lcl_reg\ : STD_LOGIC;
  signal pre_bm_end_ns : STD_LOGIC;
  signal \^pre_bm_end_r_reg\ : STD_LOGIC;
  signal pre_passing_open_bank_ns : STD_LOGIC;
  signal pre_wait_r : STD_LOGIC;
  signal \^q_has_rd_3\ : STD_LOGIC;
  signal ras_timer_passed_ns : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \^ras_timer_r_reg[1]\ : STD_LOGIC;
  signal ras_timer_zero_r : STD_LOGIC;
  signal \^rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_0\ : STD_LOGIC;
  signal \^rb_hit_busy_r_reg\ : STD_LOGIC;
  signal \^rd_wr_r_lcl_reg\ : STD_LOGIC;
  signal \^req_bank_rdy_ns\ : STD_LOGIC;
  signal req_priority_r : STD_LOGIC;
  signal \^req_wr_r_lcl_reg\ : STD_LOGIC;
  signal \^row_hit_r_reg\ : STD_LOGIC;
  signal start_wtp_timer0 : STD_LOGIC;
  signal \^wait_for_maint_r_13\ : STD_LOGIC;
begin
  E(0) <= \^e\(0);
  act_wait_r_lcl_reg <= \^act_wait_r_lcl_reg\;
  auto_pre_r_lcl_reg <= \^auto_pre_r_lcl_reg\;
  bm_end_r1_reg <= \^bm_end_r1_reg\;
  col_wait_r_reg <= \^col_wait_r_reg\;
  idle_r_lcl_reg <= \^idle_r_lcl_reg\;
  ordered_r_lcl_reg <= \^ordered_r_lcl_reg\;
  pass_open_bank_r_lcl_reg <= \^pass_open_bank_r_lcl_reg\;
  pre_bm_end_r_reg <= \^pre_bm_end_r_reg\;
  q_has_rd_3 <= \^q_has_rd_3\;
  \ras_timer_r_reg[1]\ <= \^ras_timer_r_reg[1]\;
  \rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_0\ <= \^rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_0\;
  rb_hit_busy_r_reg <= \^rb_hit_busy_r_reg\;
  rd_wr_r_lcl_reg <= \^rd_wr_r_lcl_reg\;
  req_bank_rdy_ns <= \^req_bank_rdy_ns\;
  req_wr_r_lcl_reg <= \^req_wr_r_lcl_reg\;
  row_hit_r_reg <= \^row_hit_r_reg\;
  wait_for_maint_r_13 <= \^wait_for_maint_r_13\;
bank_compare0: entity work.mig_mig_7series_v4_2_bank_compare_1
     port map (
      E(0) => idle_ns(1),
      Q(0) => Q(0),
      \grant_r_reg[1]\ => bank_compare0_n_5,
      hi_priority => hi_priority,
      maint_req_r => maint_req_r,
      ordered_r_lcl_reg => \order_q_r_reg[1]\,
      ordered_r_lcl_reg_0 => \^ordered_r_lcl_reg\,
      ordered_r_lcl_reg_1 => act_wait_r_lcl_reg_1,
      p_106_out => p_106_out,
      pass_open_bank_r_lcl_reg => pass_open_bank_r_lcl_reg_1,
      pass_open_bank_r_lcl_reg_0 => pass_open_bank_r_lcl_reg_2,
      periodic_rd_insert => periodic_rd_insert,
      rb_hit_busy_r_reg_0 => \^rb_hit_busy_r_reg\,
      rd_wr_r_lcl_reg_0 => \^rd_wr_r_lcl_reg\,
      rd_wr_r_lcl_reg_1 => \^idle_r_lcl_reg\,
      rd_wr_r_lcl_reg_2 => rd_wr_r_lcl_reg_1,
      \req_bank_r_lcl_reg[2]_0\(2 downto 0) => \req_bank_r_lcl_reg[2]\(2 downto 0),
      \req_bank_r_lcl_reg[2]_1\(2 downto 0) => \req_bank_r_lcl_reg[2]_0\(2 downto 0),
      \req_col_r_reg[9]_0\(9 downto 0) => \req_col_r_reg[9]\(9 downto 0),
      \req_col_r_reg[9]_1\(9 downto 0) => \req_col_r_reg[9]_0\(9 downto 0),
      \req_data_buf_addr_r_reg[3]_0\(3 downto 0) => \req_data_buf_addr_r_reg[3]\(3 downto 0),
      \req_data_buf_addr_r_reg[3]_1\(0) => \^e\(0),
      \req_data_buf_addr_r_reg[3]_2\(3 downto 0) => \req_data_buf_addr_r_reg[3]_0\(3 downto 0),
      req_periodic_rd_r(0) => req_periodic_rd_r(0),
      req_priority_r => req_priority_r,
      \req_row_r_lcl_reg[13]_0\(13 downto 0) => \req_row_r_lcl_reg[13]\(13 downto 0),
      \req_row_r_lcl_reg[13]_1\(13 downto 0) => \req_row_r_lcl_reg[13]_0\(13 downto 0),
      req_wr_r_lcl0 => req_wr_r_lcl0,
      req_wr_r_lcl_reg_0 => \^req_wr_r_lcl_reg\,
      row_hit_r_reg_0 => \^row_hit_r_reg\,
      row_hit_r_reg_1 => demand_priority_r_reg_1,
      row_hit_r_reg_2(0) => row_hit_r_reg_0(0),
      row_hit_r_reg_3(0) => row_hit_r_reg_1(0),
      start_wtp_timer0 => start_wtp_timer0,
      wait_for_maint_r_13 => \^wait_for_maint_r_13\
    );
bank_queue0: entity work.\mig_mig_7series_v4_2_bank_queue__parameterized0\
     port map (
      D(1 downto 0) => ras_timer_passed_ns(1 downto 0),
      E(0) => idle_ns(1),
      Q(0) => Q(0),
      act_wait_r_lcl_reg => act_wait_r_lcl_reg_0,
      auto_pre_r_lcl_reg_0 => \^auto_pre_r_lcl_reg\,
      auto_pre_r_lcl_reg_1 => auto_pre_r_lcl_reg_1,
      auto_pre_r_lcl_reg_2 => auto_pre_r_lcl_reg_2,
      auto_pre_r_lcl_reg_3 => auto_pre_r_lcl_reg_3,
      auto_pre_r_lcl_reg_4 => \^rb_hit_busy_r_reg\,
      bm_end_r1_reg => \^rd_wr_r_lcl_reg\,
      bm_end_r1_reg_0 => \^req_wr_r_lcl_reg\,
      \compute_tail.tail_r_lcl_reg_0\ => \compute_tail.tail_r_lcl_reg\,
      \compute_tail.tail_r_lcl_reg_1\ => \compute_tail.tail_r_lcl_reg_0\,
      \grant_r[3]_i_2_0\ => \grant_r[3]_i_2\,
      \grant_r[3]_i_2_1\ => \grant_r[3]_i_2_0\,
      \grant_r[3]_i_2_2\ => \grant_r[3]_i_2_1\,
      \grant_r[3]_i_2_3\ => \grant_r[3]_i_2_2\,
      \grant_r[3]_i_2_4\ => \grant_r[3]_i_2_3\,
      granted_col_ns => granted_col_ns,
      granted_col_r_reg => granted_col_r_reg,
      granted_col_r_reg_0 => granted_col_r_reg_0,
      granted_col_r_reg_1 => granted_col_r_reg_1,
      granted_col_r_reg_2 => granted_col_r_reg_2,
      granted_col_r_reg_3 => granted_col_r_reg_3,
      granted_col_r_reg_4 => granted_col_r_reg_4,
      head_r_lcl_reg_0 => head_r_lcl_reg,
      head_r_lcl_reg_1 => ofs_rdy_r_reg,
      head_r_lcl_reg_2 => head_r_lcl_reg_0,
      head_r_lcl_reg_3 => head_r_lcl_reg_1,
      head_r_lcl_reg_4 => head_r_lcl_reg_2,
      head_r_lcl_reg_5 => head_r_lcl_reg_3,
      \i___34\ => \i___34\,
      \i___34_0\ => \i___34_0\,
      \i___34_1\ => \i___34_1\,
      \i___73\ => \^act_wait_r_lcl_reg\,
      idle_r_lcl_reg_0(0) => \^e\(0),
      idle_r_lcl_reg_1 => \^idle_r_lcl_reg\,
      \order_q_r_reg[0]_0\ => bank_queue0_n_23,
      \order_q_r_reg[0]_1\ => \order_q_r_reg[0]\,
      \order_q_r_reg[0]_2\ => act_wait_r_lcl_reg_1,
      \order_q_r_reg[1]_0\ => demand_priority_r_reg_1,
      \order_q_r_reg[1]_1\ => \order_q_r_reg[1]\,
      \order_q_r_reg[1]_2\ => \order_q_r_reg[1]_0\,
      \order_q_r_reg[1]_3\ => \rtp_timer_r_reg[1]\,
      ordered_r_lcl_reg_0 => \^ordered_r_lcl_reg\,
      ordered_r_lcl_reg_1 => bank_compare0_n_5,
      p_106_out => p_106_out,
      p_91_out => p_91_out,
      pass_open_bank_ns => pass_open_bank_ns,
      pass_open_bank_r_lcl_reg_0 => \^pass_open_bank_r_lcl_reg\,
      pass_open_bank_r_lcl_reg_1 => pass_open_bank_r_lcl_reg_0,
      pass_open_bank_r_lcl_reg_2 => \^row_hit_r_reg\,
      pre_bm_end_ns => pre_bm_end_ns,
      pre_bm_end_r => pre_bm_end_r,
      pre_bm_end_r_reg_0 => \^pre_bm_end_r_reg\,
      pre_passing_open_bank_ns => pre_passing_open_bank_ns,
      pre_passing_open_bank_r_reg_0 => pre_passing_open_bank_r_reg,
      pre_wait_r => pre_wait_r,
      q_entry_ns(0) => q_entry_ns(0),
      \q_entry_r_reg[0]_0\ => \q_entry_r_reg[0]\,
      \q_entry_r_reg[0]_1\ => \q_entry_r_reg[0]_0\,
      \q_entry_r_reg[0]_2\ => \q_entry_r_reg[0]_1\,
      \q_entry_r_reg[0]_3\ => \q_entry_r_reg[0]_2\,
      \q_entry_r_reg[1]_0\ => \q_entry_r_reg[1]\,
      \q_entry_r_reg[1]_1\ => \q_entry_r_reg[1]_0\,
      \q_entry_r_reg[1]_2\ => \q_entry_r_reg[1]_1\,
      q_has_priority => q_has_priority,
      q_has_priority_r_reg_0 => q_has_priority_r_reg,
      q_has_rd_3 => \^q_has_rd_3\,
      q_has_rd_r_reg_0 => q_has_rd_r_reg,
      \ras_timer_r_reg[0]\ => \^bm_end_r1_reg\,
      \ras_timer_r_reg[0]_0\ => \ras_timer_r_reg[0]\,
      \ras_timer_r_reg[0]_1\ => \ras_timer_r_reg[0]_0\,
      \ras_timer_r_reg[0]_2\ => \ras_timer_r_reg[0]_1\,
      \ras_timer_r_reg[0]_3\ => \ras_timer_r_reg[0]_2\,
      \ras_timer_r_reg[0]_4\ => \ras_timer_r_reg[0]_3\,
      \ras_timer_r_reg[0]_5\ => \ras_timer_r_reg[0]_4\,
      \ras_timer_r_reg[0]_6\ => \ras_timer_r_reg[0]_5\,
      \ras_timer_r_reg[1]\ => \^ras_timer_r_reg[1]\,
      \ras_timer_r_reg[1]_0\ => \ras_timer_r_reg[1]_0\,
      \ras_timer_r_reg[1]_1\ => \ras_timer_r_reg[1]_1\,
      \ras_timer_r_reg[1]_2\ => \ras_timer_r_reg[1]_2\,
      ras_timer_zero_r => ras_timer_zero_r,
      \rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_0\ => \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]\(0),
      \rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_1\ => \rb_hit_busies.rb_hit_busies_r_lcl_reg[2]\,
      \rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_2\ => \^rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_0\,
      \rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_3\ => \rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_1\,
      \rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_4\ => \rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_2\,
      \rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_5\ => \rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_3\,
      \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_0\ => \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]\(1),
      \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_1\ => \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_0\,
      \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_2\ => \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_1\,
      \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_3\ => \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_2\,
      \rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_0\ => \rb_hit_busies.rb_hit_busies_r_lcl_reg[4]\,
      \rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_1\ => \rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_0\,
      \rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_2\ => \rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_1\,
      \rb_hit_busies.rb_hit_busies_r_lcl_reg[5]\ => \rb_hit_busies.rb_hit_busies_r_lcl_reg[5]\,
      \rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_0\ => \rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_0\,
      rb_hit_busies_r(0) => rb_hit_busies_r(0),
      rb_hit_busies_r_0(0) => rb_hit_busies_r_0(0),
      rb_hit_busy_r_reg => rb_hit_busy_r_reg_0,
      rb_hit_busy_r_reg_0 => rb_hit_busy_r_reg_1,
      rb_hit_busy_r_reg_1 => rb_hit_busy_r_reg_2,
      rd_wr_r_lcl_reg => rd_wr_r_lcl_reg_0,
      req_bank_rdy_ns => \^req_bank_rdy_ns\,
      req_bank_rdy_r_reg => req_bank_rdy_r_reg,
      req_bank_rdy_r_reg_0 => \^col_wait_r_reg\,
      req_priority_r => req_priority_r,
      tail_r_16 => tail_r_16,
      use_addr => use_addr,
      wait_for_maint_r_13 => \^wait_for_maint_r_13\,
      wait_for_maint_r_lcl_reg_0 => wait_for_maint_r_lcl_reg,
      wait_for_maint_r_lcl_reg_1 => wait_for_maint_r_lcl_reg_0
    );
bank_state0: entity work.\mig_mig_7series_v4_2_bank_state__parameterized0\
     port map (
      D(1 downto 0) => ras_timer_passed_ns(1 downto 0),
      Q(1 downto 0) => Q(1 downto 0),
      act_this_rank_r(0) => act_this_rank_r(0),
      act_wait_r_lcl_reg_0 => \^act_wait_r_lcl_reg\,
      act_wait_r_lcl_reg_1 => act_wait_r_lcl_reg_1,
      act_wait_r_lcl_reg_2 => \^pre_bm_end_r_reg\,
      act_wait_r_lcl_reg_3(0) => act_wait_r_lcl_reg_2(0),
      act_wait_r_lcl_reg_4 => \^rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_0\,
      auto_pre_r_lcl_reg => auto_pre_r_lcl_reg_0,
      bm_end_r1 => bm_end_r1,
      bm_end_r1_reg_0 => \^bm_end_r1_reg\,
      col_wait_r_reg_0 => \^col_wait_r_reg\,
      col_wait_r_reg_1 => col_wait_r_reg_0,
      demand_priority_r_reg_0 => demand_priority_r_reg,
      demand_priority_r_reg_1 => demand_priority_r_reg_0,
      demand_priority_r_reg_2 => demand_priority_r_reg_1,
      demand_priority_r_reg_3 => \^idle_r_lcl_reg\,
      demand_priority_r_reg_4 => bank_queue0_n_23,
      demand_priority_r_reg_5 => \^req_wr_r_lcl_reg\,
      demand_priority_r_reg_6 => demand_priority_r_reg_2,
      demanded_prior_r_reg_0 => demanded_prior_r_reg,
      demanded_prior_r_reg_1 => demanded_prior_r_reg_0,
      demanded_prior_r_reg_2 => demanded_prior_r_reg_1,
      demanded_prior_r_reg_3 => demanded_prior_r_reg_2,
      demanded_prior_r_reg_4 => demanded_prior_r_reg_3,
      ofs_rdy_r => ofs_rdy_r,
      ofs_rdy_r0 => ofs_rdy_r0,
      ofs_rdy_r_reg_0 => ofs_rdy_r_reg,
      p_91_out => p_91_out,
      pass_open_bank_ns => pass_open_bank_ns,
      pre_bm_end_ns => pre_bm_end_ns,
      pre_bm_end_r_reg(0) => pre_bm_end_r_reg_0(0),
      pre_bm_end_r_reg_0 => \^auto_pre_r_lcl_reg\,
      pre_passing_open_bank_ns => pre_passing_open_bank_ns,
      pre_wait_r => pre_wait_r,
      q_has_rd_3 => \^q_has_rd_3\,
      \ras_timer_r_reg[1]_0\ => \^ras_timer_r_reg[1]\,
      ras_timer_zero_r => ras_timer_zero_r,
      ras_timer_zero_r_reg_0 => ras_timer_zero_r_reg,
      ras_timer_zero_r_reg_1 => ras_timer_zero_r_reg_0,
      rd_this_rank_r(0) => rd_this_rank_r(0),
      \rd_this_rank_r_reg[0]_0\ => \^rd_wr_r_lcl_reg\,
      req_bank_rdy_ns => \^req_bank_rdy_ns\,
      req_bank_rdy_ns_1 => req_bank_rdy_ns_1,
      req_bank_rdy_r => req_bank_rdy_r,
      rnk_config_strobe_ns => rnk_config_strobe_ns,
      \rnk_config_strobe_r_reg[0]\ => \rnk_config_strobe_r_reg[0]\,
      \rnk_config_strobe_r_reg[0]_0\ => \rnk_config_strobe_r_reg[0]_0\,
      \rnk_config_strobe_r_reg[0]_1\ => \rnk_config_strobe_r_reg[0]_1\,
      \rtp_timer_r_reg[0]_0\ => \rtp_timer_r_reg[0]\,
      \rtp_timer_r_reg[1]_0\ => \^pass_open_bank_r_lcl_reg\,
      \rtp_timer_r_reg[1]_1\ => \rtp_timer_r_reg[1]\,
      start_wtp_timer0 => start_wtp_timer0,
      \starve_limit_cntr_r_reg[0]_0\ => \starve_limit_cntr_r_reg[0]\,
      wr_this_rank_r(0) => wr_this_rank_r(0)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \mig_mig_7series_v4_2_bank_cntrl__parameterized1\ is
  port (
    rb_hit_busy_r_reg : out STD_LOGIC;
    E : out STD_LOGIC_VECTOR ( 0 to 0 );
    req_periodic_rd_r : out STD_LOGIC_VECTOR ( 0 to 0 );
    rd_wr_r_lcl_reg : out STD_LOGIC;
    req_wr_r_lcl_reg : out STD_LOGIC;
    act_wait_r_lcl_reg : out STD_LOGIC;
    act_this_rank_r : out STD_LOGIC_VECTOR ( 0 to 0 );
    wr_this_rank_r : out STD_LOGIC_VECTOR ( 0 to 0 );
    rd_this_rank_r : out STD_LOGIC_VECTOR ( 0 to 0 );
    bm_end_r1_0 : out STD_LOGIC;
    pre_bm_end_r_reg : out STD_LOGIC;
    col_wait_r_reg : out STD_LOGIC;
    req_bank_rdy_ns : out STD_LOGIC;
    demand_priority_r_reg : out STD_LOGIC;
    demanded_prior_r_reg : out STD_LOGIC;
    override_demand_r : out STD_LOGIC;
    ofs_rdy_r : out STD_LOGIC;
    q_has_rd_7 : out STD_LOGIC;
    q_has_priority : out STD_LOGIC;
    pass_open_bank_r_lcl_reg : out STD_LOGIC;
    wait_for_maint_r_14 : out STD_LOGIC;
    head_r_lcl_reg : out STD_LOGIC;
    ordered_r_lcl_reg : out STD_LOGIC;
    tail_r_17 : out STD_LOGIC;
    auto_pre_r_lcl_reg : out STD_LOGIC;
    rb_hit_busies_r : out STD_LOGIC_VECTOR ( 1 downto 0 );
    idle_r_lcl_reg : out STD_LOGIC;
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[4]\ : out STD_LOGIC;
    rd_wr_r_lcl_reg_0 : out STD_LOGIC;
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]\ : out STD_LOGIC;
    bm_end_r1_reg : out STD_LOGIC;
    \ras_timer_r_reg[1]\ : out STD_LOGIC;
    \q_entry_r_reg[1]\ : out STD_LOGIC;
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[5]\ : out STD_LOGIC;
    \q_entry_r_reg[1]_0\ : out STD_LOGIC;
    \q_entry_r_reg[0]\ : out STD_LOGIC;
    \q_entry_r_reg[0]_0\ : out STD_LOGIC;
    idle_r_lcl_reg_0 : out STD_LOGIC;
    \order_q_r_reg[1]\ : out STD_LOGIC;
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[2]\ : out STD_LOGIC;
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[6]\ : out STD_LOGIC;
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_0\ : out STD_LOGIC;
    pre_passing_open_bank_r_reg : out STD_LOGIC;
    row_hit_r_reg : out STD_LOGIC;
    \compute_tail.tail_r_lcl_reg\ : out STD_LOGIC;
    ras_timer_zero_r_reg : out STD_LOGIC;
    act_wait_r_lcl_reg_0 : out STD_LOGIC;
    auto_pre_r_lcl_reg_0 : out STD_LOGIC;
    \req_row_r_lcl_reg[13]\ : out STD_LOGIC_VECTOR ( 13 downto 0 );
    demand_priority_r_reg_0 : out STD_LOGIC;
    act_wait_r_lcl_reg_1 : out STD_LOGIC;
    \req_data_buf_addr_r_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
    \req_bank_r_lcl_reg[2]\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
    \req_col_r_reg[9]\ : out STD_LOGIC_VECTOR ( 9 downto 0 );
    ofs_rdy_r_reg : in STD_LOGIC;
    periodic_rd_insert : in STD_LOGIC;
    req_wr_r_lcl0 : in STD_LOGIC;
    hi_priority : in STD_LOGIC;
    col_wait_r_reg_0 : in STD_LOGIC;
    override_demand_ns : in STD_LOGIC;
    ofs_rdy_r_reg_0 : in STD_LOGIC;
    ofs_rdy_r0 : in STD_LOGIC;
    q_has_rd_r_reg : in STD_LOGIC;
    q_has_priority_r_reg : in STD_LOGIC;
    wait_for_maint_r_lcl_reg : in STD_LOGIC;
    wait_for_maint_r_lcl_reg_0 : in STD_LOGIC;
    head_r_lcl_reg_0 : in STD_LOGIC;
    \compute_tail.tail_r_lcl_reg_0\ : in STD_LOGIC;
    auto_pre_r_lcl_reg_1 : in STD_LOGIC;
    row_hit_r_reg_0 : in STD_LOGIC_VECTOR ( 0 to 0 );
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_0\ : in STD_LOGIC;
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_1\ : in STD_LOGIC;
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_0\ : in STD_LOGIC;
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_1\ : in STD_LOGIC;
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_0\ : in STD_LOGIC;
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_1\ : in STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 1 downto 0 );
    pre_wait_r_reg : in STD_LOGIC;
    granted_col_r_reg : in STD_LOGIC;
    granted_col_r_reg_0 : in STD_LOGIC;
    granted_col_r_reg_1 : in STD_LOGIC;
    granted_col_r_reg_2 : in STD_LOGIC;
    act_wait_r_lcl_reg_2 : in STD_LOGIC_VECTOR ( 0 to 0 );
    \ras_timer_r_reg[0]\ : in STD_LOGIC;
    \ras_timer_r_reg[0]_0\ : in STD_LOGIC;
    \ras_timer_r_reg[0]_1\ : in STD_LOGIC;
    \ras_timer_r_reg[0]_2\ : in STD_LOGIC;
    head_r_lcl_reg_1 : in STD_LOGIC;
    head_r_lcl_reg_2 : in STD_LOGIC;
    \order_q_r_reg[1]_0\ : in STD_LOGIC;
    head_r_lcl_reg_3 : in STD_LOGIC;
    \q_entry_r_reg[1]_1\ : in STD_LOGIC;
    \i___5_i_4\ : in STD_LOGIC;
    \i___5_i_4_0\ : in STD_LOGIC;
    \i___5_i_4_1\ : in STD_LOGIC;
    req_bank_rdy_r_reg : in STD_LOGIC;
    \grant_r[3]_i_3\ : in STD_LOGIC;
    \grant_r[3]_i_3_0\ : in STD_LOGIC;
    \grant_r[3]_i_3_1\ : in STD_LOGIC;
    \grant_r[3]_i_3_2\ : in STD_LOGIC;
    rnk_config_valid_r_lcl_reg : in STD_LOGIC;
    rnk_config_valid_r_lcl_reg_0 : in STD_LOGIC;
    rb_hit_busy_r_reg_0 : in STD_LOGIC;
    rd_wr_r_lcl_reg_1 : in STD_LOGIC;
    use_addr : in STD_LOGIC;
    rb_hit_busy_r_reg_1 : in STD_LOGIC;
    rb_hit_busy_r_reg_2 : in STD_LOGIC;
    \ras_timer_r_reg[1]_0\ : in STD_LOGIC;
    \ras_timer_r_reg[1]_1\ : in STD_LOGIC;
    \ras_timer_r_reg[1]_2\ : in STD_LOGIC;
    \ras_timer_r_reg[0]_3\ : in STD_LOGIC;
    \ras_timer_r_reg[0]_4\ : in STD_LOGIC;
    \ras_timer_r_reg[0]_5\ : in STD_LOGIC;
    \grant_r[3]_i_6\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    rb_hit_busies_r_0 : in STD_LOGIC_VECTOR ( 0 to 0 );
    rb_hit_busies_r_1 : in STD_LOGIC_VECTOR ( 0 to 0 );
    pre_bm_end_r_reg_0 : in STD_LOGIC_VECTOR ( 1 downto 0 );
    pass_open_bank_r_lcl_reg_0 : in STD_LOGIC;
    maint_req_r : in STD_LOGIC;
    pass_open_bank_r_lcl_reg_1 : in STD_LOGIC;
    pass_open_bank_r_lcl_reg_2 : in STD_LOGIC;
    auto_pre_r_lcl_reg_2 : in STD_LOGIC;
    \pre_4_1_1T_arb.granted_pre_r_reg\ : in STD_LOGIC;
    ras_timer_zero_r_reg_0 : in STD_LOGIC;
    \req_row_r_lcl_reg[13]_0\ : in STD_LOGIC_VECTOR ( 13 downto 0 );
    ras_timer_zero_r_reg_1 : in STD_LOGIC;
    demand_priority_r_1 : in STD_LOGIC;
    demanded_prior_r_reg_0 : in STD_LOGIC;
    demanded_prior_r_2 : in STD_LOGIC;
    \cmd_pipe_plus.mc_address_reg[38]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    row_cmd_wr : in STD_LOGIC_VECTOR ( 0 to 0 );
    demand_priority_r_reg_1 : in STD_LOGIC;
    \rtp_timer_r_reg[0]\ : in STD_LOGIC;
    \req_data_buf_addr_r_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
    \req_bank_r_lcl_reg[2]_0\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
    \req_col_r_reg[9]_0\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_2\ : in STD_LOGIC;
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_2\ : in STD_LOGIC;
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_2\ : in STD_LOGIC;
    \q_entry_r_reg[1]_2\ : in STD_LOGIC;
    \q_entry_r_reg[1]_3\ : in STD_LOGIC;
    \q_entry_r_reg[0]_1\ : in STD_LOGIC;
    \order_q_r_reg[1]_1\ : in STD_LOGIC;
    \order_q_r_reg[0]\ : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \mig_mig_7series_v4_2_bank_cntrl__parameterized1\ : entity is "mig_7series_v4_2_bank_cntrl";
end \mig_mig_7series_v4_2_bank_cntrl__parameterized1\;

architecture STRUCTURE of \mig_mig_7series_v4_2_bank_cntrl__parameterized1\ is
  signal \^e\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \^act_wait_r_lcl_reg\ : STD_LOGIC;
  signal \^auto_pre_r_lcl_reg\ : STD_LOGIC;
  signal bank_compare0_n_5 : STD_LOGIC;
  signal bank_queue0_n_27 : STD_LOGIC;
  signal \^bm_end_r1_reg\ : STD_LOGIC;
  signal \^col_wait_r_reg\ : STD_LOGIC;
  signal idle_ns : STD_LOGIC_VECTOR ( 2 to 2 );
  signal \^idle_r_lcl_reg\ : STD_LOGIC;
  signal \^ordered_r_lcl_reg\ : STD_LOGIC;
  signal p_67_out : STD_LOGIC;
  signal pass_open_bank_ns : STD_LOGIC;
  signal pass_open_bank_r : STD_LOGIC;
  signal pre_bm_end_ns : STD_LOGIC;
  signal \^pre_bm_end_r_reg\ : STD_LOGIC;
  signal pre_passing_open_bank_ns : STD_LOGIC;
  signal pre_wait_r : STD_LOGIC;
  signal \^q_has_rd_7\ : STD_LOGIC;
  signal ras_timer_passed_ns : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \^ras_timer_r_reg[1]\ : STD_LOGIC;
  signal ras_timer_zero_r : STD_LOGIC;
  signal \^rb_hit_busies.rb_hit_busies_r_lcl_reg[3]\ : STD_LOGIC;
  signal \^rb_hit_busy_r_reg\ : STD_LOGIC;
  signal \^rd_wr_r_lcl_reg\ : STD_LOGIC;
  signal \^req_bank_rdy_ns\ : STD_LOGIC;
  signal req_priority_r : STD_LOGIC;
  signal \^req_row_r_lcl_reg[13]\ : STD_LOGIC_VECTOR ( 13 downto 0 );
  signal \^req_wr_r_lcl_reg\ : STD_LOGIC;
  signal \^row_hit_r_reg\ : STD_LOGIC;
  signal start_wtp_timer0 : STD_LOGIC;
  signal \^wait_for_maint_r_14\ : STD_LOGIC;
begin
  E(0) <= \^e\(0);
  act_wait_r_lcl_reg <= \^act_wait_r_lcl_reg\;
  auto_pre_r_lcl_reg <= \^auto_pre_r_lcl_reg\;
  bm_end_r1_reg <= \^bm_end_r1_reg\;
  col_wait_r_reg <= \^col_wait_r_reg\;
  idle_r_lcl_reg <= \^idle_r_lcl_reg\;
  ordered_r_lcl_reg <= \^ordered_r_lcl_reg\;
  pre_bm_end_r_reg <= \^pre_bm_end_r_reg\;
  q_has_rd_7 <= \^q_has_rd_7\;
  \ras_timer_r_reg[1]\ <= \^ras_timer_r_reg[1]\;
  \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]\ <= \^rb_hit_busies.rb_hit_busies_r_lcl_reg[3]\;
  rb_hit_busy_r_reg <= \^rb_hit_busy_r_reg\;
  rd_wr_r_lcl_reg <= \^rd_wr_r_lcl_reg\;
  req_bank_rdy_ns <= \^req_bank_rdy_ns\;
  \req_row_r_lcl_reg[13]\(13 downto 0) <= \^req_row_r_lcl_reg[13]\(13 downto 0);
  req_wr_r_lcl_reg <= \^req_wr_r_lcl_reg\;
  row_hit_r_reg <= \^row_hit_r_reg\;
  wait_for_maint_r_14 <= \^wait_for_maint_r_14\;
bank_compare0: entity work.mig_mig_7series_v4_2_bank_compare_0
     port map (
      E(0) => idle_ns(2),
      Q(0) => Q(1),
      \grant_r_reg[2]\ => bank_compare0_n_5,
      hi_priority => hi_priority,
      maint_req_r => maint_req_r,
      ordered_r_lcl_reg => \order_q_r_reg[1]_0\,
      ordered_r_lcl_reg_0 => \^ordered_r_lcl_reg\,
      ordered_r_lcl_reg_1 => pre_wait_r_reg,
      p_67_out => p_67_out,
      pass_open_bank_r_lcl_reg => pass_open_bank_r_lcl_reg_1,
      pass_open_bank_r_lcl_reg_0 => pass_open_bank_r_lcl_reg_2,
      periodic_rd_insert => periodic_rd_insert,
      rb_hit_busy_r_reg_0 => \^rb_hit_busy_r_reg\,
      rd_wr_r_lcl_reg_0 => \^rd_wr_r_lcl_reg\,
      rd_wr_r_lcl_reg_1 => \^idle_r_lcl_reg\,
      rd_wr_r_lcl_reg_2 => rd_wr_r_lcl_reg_1,
      \req_bank_r_lcl_reg[2]_0\(2 downto 0) => \req_bank_r_lcl_reg[2]\(2 downto 0),
      \req_bank_r_lcl_reg[2]_1\(2 downto 0) => \req_bank_r_lcl_reg[2]_0\(2 downto 0),
      \req_col_r_reg[9]_0\(9 downto 0) => \req_col_r_reg[9]\(9 downto 0),
      \req_col_r_reg[9]_1\ => ofs_rdy_r_reg,
      \req_col_r_reg[9]_2\(9 downto 0) => \req_col_r_reg[9]_0\(9 downto 0),
      \req_data_buf_addr_r_reg[3]_0\(3 downto 0) => \req_data_buf_addr_r_reg[3]\(3 downto 0),
      \req_data_buf_addr_r_reg[3]_1\ => \^e\(0),
      \req_data_buf_addr_r_reg[3]_2\(3 downto 0) => \req_data_buf_addr_r_reg[3]_0\(3 downto 0),
      req_periodic_rd_r(0) => req_periodic_rd_r(0),
      req_priority_r => req_priority_r,
      \req_row_r_lcl_reg[13]_0\(13 downto 0) => \^req_row_r_lcl_reg[13]\(13 downto 0),
      \req_row_r_lcl_reg[13]_1\(13 downto 0) => \req_row_r_lcl_reg[13]_0\(13 downto 0),
      req_wr_r_lcl0 => req_wr_r_lcl0,
      req_wr_r_lcl_reg_0 => \^req_wr_r_lcl_reg\,
      row_hit_r_reg_0 => \^row_hit_r_reg\,
      row_hit_r_reg_1(0) => row_hit_r_reg_0(0),
      start_wtp_timer0 => start_wtp_timer0,
      wait_for_maint_r_14 => \^wait_for_maint_r_14\
    );
bank_queue0: entity work.\mig_mig_7series_v4_2_bank_queue__parameterized1\
     port map (
      D(1 downto 0) => ras_timer_passed_ns(1 downto 0),
      E(0) => idle_ns(2),
      Q(0) => Q(1),
      act_wait_r_lcl_reg => act_wait_r_lcl_reg_0,
      auto_pre_r_lcl_reg_0 => \^auto_pre_r_lcl_reg\,
      auto_pre_r_lcl_reg_1 => auto_pre_r_lcl_reg_1,
      auto_pre_r_lcl_reg_2 => auto_pre_r_lcl_reg_2,
      auto_pre_r_lcl_reg_3 => \^rb_hit_busy_r_reg\,
      \compute_tail.tail_r_lcl_reg_0\ => \compute_tail.tail_r_lcl_reg\,
      \compute_tail.tail_r_lcl_reg_1\ => \compute_tail.tail_r_lcl_reg_0\,
      \grant_r[3]_i_2__0\ => \^act_wait_r_lcl_reg\,
      \grant_r[3]_i_3_0\ => \grant_r[3]_i_3\,
      \grant_r[3]_i_3_1\ => \grant_r[3]_i_3_0\,
      \grant_r[3]_i_3_2\ => \grant_r[3]_i_3_1\,
      \grant_r[3]_i_3_3\ => \grant_r[3]_i_3_2\,
      \grant_r[3]_i_6\(0) => \grant_r[3]_i_6\(0),
      granted_col_r_reg => granted_col_r_reg,
      granted_col_r_reg_0 => granted_col_r_reg_0,
      granted_col_r_reg_1 => granted_col_r_reg_1,
      granted_col_r_reg_2 => granted_col_r_reg_2,
      head_r_lcl_reg_0 => head_r_lcl_reg,
      head_r_lcl_reg_1 => ofs_rdy_r_reg_0,
      head_r_lcl_reg_2 => head_r_lcl_reg_0,
      head_r_lcl_reg_3 => head_r_lcl_reg_1,
      head_r_lcl_reg_4 => head_r_lcl_reg_2,
      head_r_lcl_reg_5 => head_r_lcl_reg_3,
      \i___5_i_4\ => \i___5_i_4\,
      \i___5_i_4_0\ => \i___5_i_4_0\,
      \i___5_i_4_1\ => \i___5_i_4_1\,
      idle_r_lcl_reg_0 => \^e\(0),
      idle_r_lcl_reg_1 => \^idle_r_lcl_reg\,
      idle_r_lcl_reg_2 => idle_r_lcl_reg_0,
      \order_q_r_reg[0]_0\ => bank_queue0_n_27,
      \order_q_r_reg[0]_1\ => \order_q_r_reg[0]\,
      \order_q_r_reg[1]_0\ => \order_q_r_reg[1]\,
      \order_q_r_reg[1]_1\ => \order_q_r_reg[1]_0\,
      \order_q_r_reg[1]_2\ => \order_q_r_reg[1]_1\,
      ordered_r_lcl_reg_0 => \^ordered_r_lcl_reg\,
      ordered_r_lcl_reg_1 => bank_compare0_n_5,
      p_67_out => p_67_out,
      pass_open_bank_ns => pass_open_bank_ns,
      pass_open_bank_r => pass_open_bank_r,
      pass_open_bank_r_lcl_reg_0 => pass_open_bank_r_lcl_reg,
      pass_open_bank_r_lcl_reg_1 => pass_open_bank_r_lcl_reg_0,
      pass_open_bank_r_lcl_reg_2 => \^row_hit_r_reg\,
      pre_bm_end_ns => pre_bm_end_ns,
      pre_bm_end_r_reg_0 => \^pre_bm_end_r_reg\,
      pre_passing_open_bank_ns => pre_passing_open_bank_ns,
      pre_passing_open_bank_r_reg_0 => pre_passing_open_bank_r_reg,
      pre_wait_r => pre_wait_r,
      \q_entry_r_reg[0]_0\ => \q_entry_r_reg[0]\,
      \q_entry_r_reg[0]_1\ => \q_entry_r_reg[0]_0\,
      \q_entry_r_reg[0]_2\ => \q_entry_r_reg[0]_1\,
      \q_entry_r_reg[1]_0\ => \q_entry_r_reg[1]\,
      \q_entry_r_reg[1]_1\ => \q_entry_r_reg[1]_0\,
      \q_entry_r_reg[1]_2\ => \q_entry_r_reg[1]_1\,
      \q_entry_r_reg[1]_3\ => \q_entry_r_reg[1]_2\,
      \q_entry_r_reg[1]_4\ => \q_entry_r_reg[1]_3\,
      q_has_priority => q_has_priority,
      q_has_priority_r_reg_0 => q_has_priority_r_reg,
      q_has_priority_r_reg_1 => \^rd_wr_r_lcl_reg\,
      q_has_priority_r_reg_2 => \^req_wr_r_lcl_reg\,
      q_has_priority_r_reg_3 => pre_wait_r_reg,
      q_has_rd_7 => \^q_has_rd_7\,
      q_has_rd_r_reg_0 => ofs_rdy_r_reg,
      q_has_rd_r_reg_1 => q_has_rd_r_reg,
      \ras_timer_r_reg[0]\ => \^bm_end_r1_reg\,
      \ras_timer_r_reg[0]_0\ => \ras_timer_r_reg[0]\,
      \ras_timer_r_reg[0]_1\ => \ras_timer_r_reg[0]_0\,
      \ras_timer_r_reg[0]_2\ => \ras_timer_r_reg[0]_1\,
      \ras_timer_r_reg[0]_3\ => \ras_timer_r_reg[0]_2\,
      \ras_timer_r_reg[0]_4\ => \ras_timer_r_reg[0]_3\,
      \ras_timer_r_reg[0]_5\ => \ras_timer_r_reg[0]_4\,
      \ras_timer_r_reg[0]_6\ => \ras_timer_r_reg[0]_5\,
      \ras_timer_r_reg[1]\ => \^ras_timer_r_reg[1]\,
      \ras_timer_r_reg[1]_0\ => \ras_timer_r_reg[1]_0\,
      \ras_timer_r_reg[1]_1\ => \ras_timer_r_reg[1]_1\,
      \ras_timer_r_reg[1]_2\ => \ras_timer_r_reg[1]_2\,
      ras_timer_zero_r => ras_timer_zero_r,
      \rb_hit_busies.rb_hit_busies_r_lcl_reg[2]\ => \rb_hit_busies.rb_hit_busies_r_lcl_reg[2]\,
      \rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_0\ => \rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_0\,
      \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_0\ => rb_hit_busies_r(0),
      \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_1\ => \^rb_hit_busies.rb_hit_busies_r_lcl_reg[3]\,
      \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_2\ => \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_0\,
      \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_3\ => \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_1\,
      \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_4\ => \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_2\,
      \rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_0\ => \rb_hit_busies.rb_hit_busies_r_lcl_reg[4]\,
      \rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_1\ => \rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_0\,
      \rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_2\ => \rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_1\,
      \rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_3\ => \rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_2\,
      \rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_0\ => rb_hit_busies_r(1),
      \rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_1\ => \rb_hit_busies.rb_hit_busies_r_lcl_reg[5]\,
      \rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_2\ => \rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_0\,
      \rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_3\ => \rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_1\,
      \rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_4\ => \rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_2\,
      \rb_hit_busies.rb_hit_busies_r_lcl_reg[6]\ => \rb_hit_busies.rb_hit_busies_r_lcl_reg[6]\,
      rb_hit_busies_r_0(0) => rb_hit_busies_r_0(0),
      rb_hit_busies_r_1(0) => rb_hit_busies_r_1(0),
      rb_hit_busy_r_reg => rb_hit_busy_r_reg_0,
      rb_hit_busy_r_reg_0 => rb_hit_busy_r_reg_1,
      rb_hit_busy_r_reg_1 => rb_hit_busy_r_reg_2,
      rd_wr_r_lcl_reg => rd_wr_r_lcl_reg_0,
      req_bank_rdy_ns => \^req_bank_rdy_ns\,
      req_bank_rdy_r_reg => req_bank_rdy_r_reg,
      req_bank_rdy_r_reg_0 => \^col_wait_r_reg\,
      req_priority_r => req_priority_r,
      rnk_config_valid_r_lcl_reg => rnk_config_valid_r_lcl_reg,
      rnk_config_valid_r_lcl_reg_0 => rnk_config_valid_r_lcl_reg_0,
      tail_r_17 => tail_r_17,
      use_addr => use_addr,
      wait_for_maint_r_14 => \^wait_for_maint_r_14\,
      wait_for_maint_r_lcl_reg_0 => wait_for_maint_r_lcl_reg,
      wait_for_maint_r_lcl_reg_1 => wait_for_maint_r_lcl_reg_0
    );
bank_state0: entity work.\mig_mig_7series_v4_2_bank_state__parameterized1\
     port map (
      D(1 downto 0) => ras_timer_passed_ns(1 downto 0),
      Q(1 downto 0) => Q(1 downto 0),
      act_this_rank_r(0) => act_this_rank_r(0),
      act_wait_r_lcl_reg_0 => \^act_wait_r_lcl_reg\,
      act_wait_r_lcl_reg_1 => act_wait_r_lcl_reg_1,
      act_wait_r_lcl_reg_2(0) => act_wait_r_lcl_reg_2(0),
      act_wait_r_lcl_reg_3 => \^rb_hit_busies.rb_hit_busies_r_lcl_reg[3]\,
      auto_pre_r_lcl_reg => auto_pre_r_lcl_reg_0,
      bm_end_r1_0 => bm_end_r1_0,
      bm_end_r1_reg_0 => \^bm_end_r1_reg\,
      bm_end_r1_reg_1 => \^pre_bm_end_r_reg\,
      \cmd_pipe_plus.mc_address_reg[38]\(0) => \^req_row_r_lcl_reg[13]\(10),
      \cmd_pipe_plus.mc_address_reg[38]_0\(0) => \cmd_pipe_plus.mc_address_reg[38]\(0),
      col_wait_r_reg_0 => \^col_wait_r_reg\,
      col_wait_r_reg_1 => col_wait_r_reg_0,
      demand_priority_r_1 => demand_priority_r_1,
      demand_priority_r_reg_0 => demand_priority_r_reg,
      demand_priority_r_reg_1 => demand_priority_r_reg_0,
      demand_priority_r_reg_2 => \^idle_r_lcl_reg\,
      demand_priority_r_reg_3 => bank_queue0_n_27,
      demand_priority_r_reg_4 => demand_priority_r_reg_1,
      demand_priority_r_reg_5 => \^req_wr_r_lcl_reg\,
      demanded_prior_r_2 => demanded_prior_r_2,
      demanded_prior_r_reg_0 => demanded_prior_r_reg,
      demanded_prior_r_reg_1 => demanded_prior_r_reg_0,
      ofs_rdy_r => ofs_rdy_r,
      ofs_rdy_r0 => ofs_rdy_r0,
      ofs_rdy_r_reg_0 => ofs_rdy_r_reg,
      ofs_rdy_r_reg_1 => ofs_rdy_r_reg_0,
      override_demand_ns => override_demand_ns,
      override_demand_r => override_demand_r,
      pass_open_bank_ns => pass_open_bank_ns,
      pass_open_bank_r => pass_open_bank_r,
      \pre_4_1_1T_arb.granted_pre_r_reg\ => \pre_4_1_1T_arb.granted_pre_r_reg\,
      pre_bm_end_ns => pre_bm_end_ns,
      pre_bm_end_r_reg(1 downto 0) => pre_bm_end_r_reg_0(1 downto 0),
      pre_bm_end_r_reg_0 => \^auto_pre_r_lcl_reg\,
      pre_passing_open_bank_ns => pre_passing_open_bank_ns,
      pre_wait_r => pre_wait_r,
      pre_wait_r_reg_0 => pre_wait_r_reg,
      q_has_rd_7 => \^q_has_rd_7\,
      \ras_timer_r_reg[1]_0\ => \^ras_timer_r_reg[1]\,
      ras_timer_zero_r => ras_timer_zero_r,
      ras_timer_zero_r_reg_0 => ras_timer_zero_r_reg,
      ras_timer_zero_r_reg_1 => ras_timer_zero_r_reg_0,
      ras_timer_zero_r_reg_2 => ras_timer_zero_r_reg_1,
      rd_this_rank_r(0) => rd_this_rank_r(0),
      \rd_this_rank_r_reg[0]_0\ => \^rd_wr_r_lcl_reg\,
      req_bank_rdy_ns => \^req_bank_rdy_ns\,
      row_cmd_wr(0) => row_cmd_wr(0),
      \rtp_timer_r_reg[0]_0\ => \rtp_timer_r_reg[0]\,
      start_wtp_timer0 => start_wtp_timer0,
      wr_this_rank_r(0) => wr_this_rank_r(0)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \mig_mig_7series_v4_2_bank_cntrl__parameterized2\ is
  port (
    rb_hit_busy_r_reg : out STD_LOGIC;
    E : out STD_LOGIC_VECTOR ( 0 to 0 );
    req_periodic_rd_r : out STD_LOGIC_VECTOR ( 0 to 0 );
    rd_wr_r_lcl_reg : out STD_LOGIC;
    req_wr_r_lcl_reg : out STD_LOGIC;
    act_wait_r_lcl_reg : out STD_LOGIC;
    act_this_rank_r : out STD_LOGIC_VECTOR ( 0 to 0 );
    wr_this_rank_r : out STD_LOGIC_VECTOR ( 0 to 0 );
    rd_this_rank_r : out STD_LOGIC_VECTOR ( 0 to 0 );
    bm_end_r1_1 : out STD_LOGIC;
    col_wait_r_reg : out STD_LOGIC;
    req_bank_rdy_ns : out STD_LOGIC;
    demand_priority_r_reg : out STD_LOGIC;
    demanded_prior_r_0 : out STD_LOGIC;
    ofs_rdy_r : out STD_LOGIC;
    pass_open_bank_r_lcl_reg : out STD_LOGIC;
    pre_bm_end_r_11 : out STD_LOGIC;
    q_has_rd_12 : out STD_LOGIC;
    q_has_priority : out STD_LOGIC;
    wait_for_maint_r_15 : out STD_LOGIC;
    head_r_lcl_reg : out STD_LOGIC;
    ordered_r_lcl_reg : out STD_LOGIC;
    tail_r_18 : out STD_LOGIC;
    auto_pre_r_lcl_reg : out STD_LOGIC;
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[6]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    idle_r_lcl_reg : out STD_LOGIC;
    rd_wr_r_lcl_reg_0 : out STD_LOGIC;
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[6]_0\ : out STD_LOGIC;
    bm_end_r1_reg : out STD_LOGIC;
    \ras_timer_r_reg[1]\ : out STD_LOGIC;
    pre_bm_end_r_reg : out STD_LOGIC;
    pre_bm_end_r_reg_0 : out STD_LOGIC;
    \q_entry_r_reg[1]\ : out STD_LOGIC;
    \q_entry_r_reg[0]\ : out STD_LOGIC;
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[4]\ : out STD_LOGIC;
    \q_entry_r_reg[0]_0\ : out STD_LOGIC;
    pre_bm_end_r_reg_1 : out STD_LOGIC;
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]\ : out STD_LOGIC;
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_0\ : out STD_LOGIC;
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_1\ : out STD_LOGIC;
    pre_passing_open_bank_r_reg : out STD_LOGIC;
    row_hit_r_reg : out STD_LOGIC;
    \compute_tail.tail_r_lcl_reg\ : out STD_LOGIC;
    \pre_4_1_1T_arb.granted_pre_ns\ : out STD_LOGIC;
    act_wait_r_lcl_reg_0 : out STD_LOGIC;
    auto_pre_r_lcl_reg_0 : out STD_LOGIC;
    \req_row_r_lcl_reg[13]\ : out STD_LOGIC_VECTOR ( 13 downto 0 );
    act_wait_r_lcl_reg_1 : out STD_LOGIC;
    demand_priority_r_reg_0 : out STD_LOGIC;
    \grant_r_reg[3]\ : out STD_LOGIC;
    \req_data_buf_addr_r_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
    \req_bank_r_lcl_reg[2]\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
    \req_col_r_reg[9]\ : out STD_LOGIC_VECTOR ( 9 downto 0 );
    demand_priority_r_reg_1 : in STD_LOGIC;
    periodic_rd_insert : in STD_LOGIC;
    req_wr_r_lcl0 : in STD_LOGIC;
    hi_priority : in STD_LOGIC;
    col_wait_r_reg_0 : in STD_LOGIC;
    ofs_rdy_r_reg : in STD_LOGIC;
    ofs_rdy_r0 : in STD_LOGIC;
    q_has_rd_r_reg : in STD_LOGIC;
    auto_pre_r_lcl_reg_1 : in STD_LOGIC;
    q_has_priority_r_reg : in STD_LOGIC;
    wait_for_maint_r_lcl_reg : in STD_LOGIC;
    wait_for_maint_r_lcl_reg_0 : in STD_LOGIC;
    head_r_lcl_reg_0 : in STD_LOGIC;
    \compute_tail.tail_r_lcl_reg_0\ : in STD_LOGIC;
    auto_pre_r_lcl_reg_2 : in STD_LOGIC;
    row_hit_r_reg_0 : in STD_LOGIC_VECTOR ( 0 to 0 );
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[5]\ : in STD_LOGIC;
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_0\ : in STD_LOGIC;
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[6]_1\ : in STD_LOGIC;
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[6]_2\ : in STD_LOGIC;
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_0\ : in STD_LOGIC;
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_1\ : in STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 1 downto 0 );
    pre_wait_r_reg : in STD_LOGIC;
    granted_col_r_reg : in STD_LOGIC;
    granted_col_r_reg_0 : in STD_LOGIC;
    granted_col_r_reg_1 : in STD_LOGIC;
    act_wait_r_lcl_reg_2 : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \ras_timer_r_reg[0]\ : in STD_LOGIC;
    \ras_timer_r_reg[0]_0\ : in STD_LOGIC;
    \ras_timer_r_reg[0]_1\ : in STD_LOGIC;
    \grant_r[3]_i_5\ : in STD_LOGIC;
    \ras_timer_r_reg[0]_2\ : in STD_LOGIC;
    \compute_tail.tail_r_lcl_reg_1\ : in STD_LOGIC;
    \compute_tail.tail_r_lcl_reg_2\ : in STD_LOGIC;
    \q_entry_r_reg[1]_0\ : in STD_LOGIC;
    \q_entry_r_reg[1]_1\ : in STD_LOGIC;
    \order_q_r_reg[1]\ : in STD_LOGIC;
    head_r_lcl_reg_1 : in STD_LOGIC;
    head_r_lcl_reg_2 : in STD_LOGIC;
    head_r_lcl_reg_3 : in STD_LOGIC;
    \compute_tail.tail_r_lcl_reg_3\ : in STD_LOGIC;
    req_bank_rdy_r_reg : in STD_LOGIC;
    \grant_r[3]_i_5_0\ : in STD_LOGIC;
    \grant_r[3]_i_5_1\ : in STD_LOGIC;
    \grant_r[3]_i_5_2\ : in STD_LOGIC;
    \grant_r[3]_i_5_3\ : in STD_LOGIC;
    rb_hit_busy_r_reg_0 : in STD_LOGIC;
    rd_wr_r_lcl_reg_1 : in STD_LOGIC;
    use_addr : in STD_LOGIC;
    rb_hit_busy_r_reg_1 : in STD_LOGIC;
    rb_hit_busy_r_reg_2 : in STD_LOGIC;
    \ras_timer_r_reg[1]_0\ : in STD_LOGIC;
    \ras_timer_r_reg[1]_1\ : in STD_LOGIC;
    \ras_timer_r_reg[1]_2\ : in STD_LOGIC;
    \ras_timer_r_reg[0]_3\ : in STD_LOGIC;
    \ras_timer_r_reg[0]_4\ : in STD_LOGIC;
    \ras_timer_r_reg[0]_5\ : in STD_LOGIC;
    \grant_r[3]_i_6\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    rb_hit_busies_r : in STD_LOGIC_VECTOR ( 0 to 0 );
    rb_hit_busies_r_1 : in STD_LOGIC_VECTOR ( 0 to 0 );
    pre_bm_end_r_reg_2 : in STD_LOGIC_VECTOR ( 0 to 0 );
    pass_open_bank_r_lcl_reg_0 : in STD_LOGIC;
    maint_req_r : in STD_LOGIC;
    pass_open_bank_r_lcl_reg_1 : in STD_LOGIC;
    pass_open_bank_r_lcl_reg_2 : in STD_LOGIC;
    auto_pre_r_lcl_reg_3 : in STD_LOGIC;
    \pre_4_1_1T_arb.granted_pre_r_reg\ : in STD_LOGIC;
    \pre_4_1_1T_arb.granted_pre_r_reg_0\ : in STD_LOGIC;
    \ras_timer_r_reg[0]_6\ : in STD_LOGIC;
    \req_row_r_lcl_reg[13]_0\ : in STD_LOGIC_VECTOR ( 13 downto 0 );
    row_cmd_wr : in STD_LOGIC_VECTOR ( 0 to 0 );
    \cmd_pipe_plus.mc_address[10]_i_2\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    ras_timer_zero_r_reg : in STD_LOGIC;
    demanded_prior_r_reg : in STD_LOGIC;
    demand_priority_r : in STD_LOGIC;
    demanded_prior_r : in STD_LOGIC;
    demand_priority_r_reg_2 : in STD_LOGIC;
    \rtp_timer_r_reg[0]\ : in STD_LOGIC;
    \req_data_buf_addr_r_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
    \req_bank_r_lcl_reg[2]_0\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
    \req_col_r_reg[9]_0\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[6]_3\ : in STD_LOGIC;
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_1\ : in STD_LOGIC;
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_2\ : in STD_LOGIC;
    \q_entry_r_reg[1]_2\ : in STD_LOGIC;
    \q_entry_r_reg[1]_3\ : in STD_LOGIC;
    \q_entry_r_reg[1]_4\ : in STD_LOGIC;
    \q_entry_r_reg[0]_1\ : in STD_LOGIC;
    \order_q_r_reg[1]_0\ : in STD_LOGIC;
    \order_q_r_reg[0]\ : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \mig_mig_7series_v4_2_bank_cntrl__parameterized2\ : entity is "mig_7series_v4_2_bank_cntrl";
end \mig_mig_7series_v4_2_bank_cntrl__parameterized2\;

architecture STRUCTURE of \mig_mig_7series_v4_2_bank_cntrl__parameterized2\ is
  signal \^e\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \^act_wait_r_lcl_reg\ : STD_LOGIC;
  signal \^auto_pre_r_lcl_reg\ : STD_LOGIC;
  signal bank_compare0_n_5 : STD_LOGIC;
  signal bank_queue0_n_26 : STD_LOGIC;
  signal \^bm_end_r1_reg\ : STD_LOGIC;
  signal \^col_wait_r_reg\ : STD_LOGIC;
  signal idle_ns : STD_LOGIC_VECTOR ( 3 to 3 );
  signal \^idle_r_lcl_reg\ : STD_LOGIC;
  signal \^ordered_r_lcl_reg\ : STD_LOGIC;
  signal p_13_out : STD_LOGIC;
  signal p_28_out : STD_LOGIC;
  signal pass_open_bank_ns : STD_LOGIC;
  signal \^pass_open_bank_r_lcl_reg\ : STD_LOGIC;
  signal pre_bm_end_ns : STD_LOGIC;
  signal \^pre_bm_end_r_reg\ : STD_LOGIC;
  signal pre_passing_open_bank_ns : STD_LOGIC;
  signal pre_wait_r : STD_LOGIC;
  signal \^q_has_rd_12\ : STD_LOGIC;
  signal ras_timer_passed_ns : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \^ras_timer_r_reg[1]\ : STD_LOGIC;
  signal ras_timer_zero_r : STD_LOGIC;
  signal \^rb_hit_busies.rb_hit_busies_r_lcl_reg[6]_0\ : STD_LOGIC;
  signal \^rb_hit_busy_r_reg\ : STD_LOGIC;
  signal \^rd_wr_r_lcl_reg\ : STD_LOGIC;
  signal \^req_bank_rdy_ns\ : STD_LOGIC;
  signal req_priority_r : STD_LOGIC;
  signal \^req_row_r_lcl_reg[13]\ : STD_LOGIC_VECTOR ( 13 downto 0 );
  signal \^req_wr_r_lcl_reg\ : STD_LOGIC;
  signal \^row_hit_r_reg\ : STD_LOGIC;
  signal start_wtp_timer0 : STD_LOGIC;
  signal \^wait_for_maint_r_15\ : STD_LOGIC;
begin
  E(0) <= \^e\(0);
  act_wait_r_lcl_reg <= \^act_wait_r_lcl_reg\;
  auto_pre_r_lcl_reg <= \^auto_pre_r_lcl_reg\;
  bm_end_r1_reg <= \^bm_end_r1_reg\;
  col_wait_r_reg <= \^col_wait_r_reg\;
  idle_r_lcl_reg <= \^idle_r_lcl_reg\;
  ordered_r_lcl_reg <= \^ordered_r_lcl_reg\;
  pass_open_bank_r_lcl_reg <= \^pass_open_bank_r_lcl_reg\;
  pre_bm_end_r_reg <= \^pre_bm_end_r_reg\;
  q_has_rd_12 <= \^q_has_rd_12\;
  \ras_timer_r_reg[1]\ <= \^ras_timer_r_reg[1]\;
  \rb_hit_busies.rb_hit_busies_r_lcl_reg[6]_0\ <= \^rb_hit_busies.rb_hit_busies_r_lcl_reg[6]_0\;
  rb_hit_busy_r_reg <= \^rb_hit_busy_r_reg\;
  rd_wr_r_lcl_reg <= \^rd_wr_r_lcl_reg\;
  req_bank_rdy_ns <= \^req_bank_rdy_ns\;
  \req_row_r_lcl_reg[13]\(13 downto 0) <= \^req_row_r_lcl_reg[13]\(13 downto 0);
  req_wr_r_lcl_reg <= \^req_wr_r_lcl_reg\;
  row_hit_r_reg <= \^row_hit_r_reg\;
  wait_for_maint_r_15 <= \^wait_for_maint_r_15\;
bank_compare0: entity work.mig_mig_7series_v4_2_bank_compare
     port map (
      E(0) => idle_ns(3),
      Q(0) => Q(1),
      \grant_r_reg[3]\ => bank_compare0_n_5,
      hi_priority => hi_priority,
      maint_req_r => maint_req_r,
      ordered_r_lcl_reg => \order_q_r_reg[1]\,
      ordered_r_lcl_reg_0 => \^ordered_r_lcl_reg\,
      ordered_r_lcl_reg_1 => pre_wait_r_reg,
      p_28_out => p_28_out,
      pass_open_bank_r_lcl_reg => pass_open_bank_r_lcl_reg_1,
      pass_open_bank_r_lcl_reg_0 => pass_open_bank_r_lcl_reg_2,
      periodic_rd_insert => periodic_rd_insert,
      rb_hit_busy_r_reg_0 => \^rb_hit_busy_r_reg\,
      rd_wr_r_lcl_reg_0 => \^rd_wr_r_lcl_reg\,
      rd_wr_r_lcl_reg_1 => \^idle_r_lcl_reg\,
      rd_wr_r_lcl_reg_2 => rd_wr_r_lcl_reg_1,
      \req_bank_r_lcl_reg[2]_0\(2 downto 0) => \req_bank_r_lcl_reg[2]\(2 downto 0),
      \req_bank_r_lcl_reg[2]_1\(2 downto 0) => \req_bank_r_lcl_reg[2]_0\(2 downto 0),
      \req_col_r_reg[9]_0\(9 downto 0) => \req_col_r_reg[9]\(9 downto 0),
      \req_col_r_reg[9]_1\(9 downto 0) => \req_col_r_reg[9]_0\(9 downto 0),
      \req_data_buf_addr_r_reg[3]_0\(3 downto 0) => \req_data_buf_addr_r_reg[3]\(3 downto 0),
      \req_data_buf_addr_r_reg[3]_1\(0) => \^e\(0),
      \req_data_buf_addr_r_reg[3]_2\(3 downto 0) => \req_data_buf_addr_r_reg[3]_0\(3 downto 0),
      req_periodic_rd_r(0) => req_periodic_rd_r(0),
      req_priority_r => req_priority_r,
      \req_row_r_lcl_reg[13]_0\(13 downto 0) => \^req_row_r_lcl_reg[13]\(13 downto 0),
      \req_row_r_lcl_reg[13]_1\(13 downto 0) => \req_row_r_lcl_reg[13]_0\(13 downto 0),
      req_wr_r_lcl0 => req_wr_r_lcl0,
      req_wr_r_lcl_reg_0 => \^req_wr_r_lcl_reg\,
      row_hit_r_reg_0 => \^row_hit_r_reg\,
      row_hit_r_reg_1 => demand_priority_r_reg_1,
      row_hit_r_reg_2(0) => row_hit_r_reg_0(0),
      start_wtp_timer0 => start_wtp_timer0,
      wait_for_maint_r_15 => \^wait_for_maint_r_15\
    );
bank_queue0: entity work.\mig_mig_7series_v4_2_bank_queue__parameterized2\
     port map (
      D(1 downto 0) => ras_timer_passed_ns(1 downto 0),
      E(0) => idle_ns(3),
      Q(0) => Q(1),
      act_wait_r_lcl_reg => act_wait_r_lcl_reg_0,
      auto_pre_r_lcl_reg_0 => \^auto_pre_r_lcl_reg\,
      auto_pre_r_lcl_reg_1 => auto_pre_r_lcl_reg_1,
      auto_pre_r_lcl_reg_2 => auto_pre_r_lcl_reg_2,
      auto_pre_r_lcl_reg_3 => \^rb_hit_busy_r_reg\,
      auto_pre_r_lcl_reg_4 => auto_pre_r_lcl_reg_3,
      bm_end_r1_reg => \^rd_wr_r_lcl_reg\,
      bm_end_r1_reg_0 => \^req_wr_r_lcl_reg\,
      \compute_tail.tail_r_lcl_reg_0\ => \compute_tail.tail_r_lcl_reg\,
      \compute_tail.tail_r_lcl_reg_1\ => \compute_tail.tail_r_lcl_reg_0\,
      \compute_tail.tail_r_lcl_reg_2\ => \compute_tail.tail_r_lcl_reg_1\,
      \compute_tail.tail_r_lcl_reg_3\ => \compute_tail.tail_r_lcl_reg_2\,
      \compute_tail.tail_r_lcl_reg_4\ => \compute_tail.tail_r_lcl_reg_3\,
      \grant_r[3]_i_5_0\ => \grant_r[3]_i_5\,
      \grant_r[3]_i_5_1\ => \grant_r[3]_i_5_0\,
      \grant_r[3]_i_5_2\ => \grant_r[3]_i_5_1\,
      \grant_r[3]_i_5_3\ => \grant_r[3]_i_5_2\,
      \grant_r[3]_i_5_4\ => \grant_r[3]_i_5_3\,
      \grant_r[3]_i_6\(0) => \grant_r[3]_i_6\(0),
      granted_col_r_reg => granted_col_r_reg,
      granted_col_r_reg_0 => granted_col_r_reg_0,
      granted_col_r_reg_1 => granted_col_r_reg_1,
      head_r_lcl_reg_0 => head_r_lcl_reg,
      head_r_lcl_reg_1 => ofs_rdy_r_reg,
      head_r_lcl_reg_2 => head_r_lcl_reg_0,
      head_r_lcl_reg_3 => head_r_lcl_reg_1,
      head_r_lcl_reg_4 => head_r_lcl_reg_2,
      head_r_lcl_reg_5 => head_r_lcl_reg_3,
      \i___74\ => \^act_wait_r_lcl_reg\,
      idle_r_lcl_reg_0(0) => \^e\(0),
      idle_r_lcl_reg_1 => \^idle_r_lcl_reg\,
      \order_q_r_reg[0]_0\ => bank_queue0_n_26,
      \order_q_r_reg[0]_1\ => pre_wait_r_reg,
      \order_q_r_reg[0]_2\ => \order_q_r_reg[0]\,
      \order_q_r_reg[1]_0\ => demand_priority_r_reg_1,
      \order_q_r_reg[1]_1\ => \order_q_r_reg[1]\,
      \order_q_r_reg[1]_2\ => \order_q_r_reg[1]_0\,
      ordered_r_lcl_reg_0 => \^ordered_r_lcl_reg\,
      ordered_r_lcl_reg_1 => bank_compare0_n_5,
      p_13_out => p_13_out,
      p_28_out => p_28_out,
      pass_open_bank_ns => pass_open_bank_ns,
      pass_open_bank_r_lcl_reg_0 => \^pass_open_bank_r_lcl_reg\,
      pass_open_bank_r_lcl_reg_1 => pass_open_bank_r_lcl_reg_0,
      pass_open_bank_r_lcl_reg_2 => \^row_hit_r_reg\,
      pre_bm_end_ns => pre_bm_end_ns,
      pre_bm_end_r_11 => pre_bm_end_r_11,
      pre_bm_end_r_reg_0 => pre_bm_end_r_reg_0,
      pre_bm_end_r_reg_1 => \^pre_bm_end_r_reg\,
      pre_bm_end_r_reg_2 => pre_bm_end_r_reg_1,
      pre_passing_open_bank_ns => pre_passing_open_bank_ns,
      pre_passing_open_bank_r_reg_0 => pre_passing_open_bank_r_reg,
      pre_wait_r => pre_wait_r,
      \q_entry_r_reg[0]_0\ => \q_entry_r_reg[0]\,
      \q_entry_r_reg[0]_1\ => \q_entry_r_reg[0]_0\,
      \q_entry_r_reg[0]_2\ => \q_entry_r_reg[0]_1\,
      \q_entry_r_reg[1]_0\ => \q_entry_r_reg[1]\,
      \q_entry_r_reg[1]_1\ => \q_entry_r_reg[1]_0\,
      \q_entry_r_reg[1]_2\ => \q_entry_r_reg[1]_1\,
      \q_entry_r_reg[1]_3\ => \q_entry_r_reg[1]_2\,
      \q_entry_r_reg[1]_4\ => \q_entry_r_reg[1]_3\,
      \q_entry_r_reg[1]_5\ => \q_entry_r_reg[1]_4\,
      q_has_priority => q_has_priority,
      q_has_priority_r_reg_0 => q_has_priority_r_reg,
      q_has_rd_12 => \^q_has_rd_12\,
      q_has_rd_r_reg_0 => q_has_rd_r_reg,
      \ras_timer_r_reg[0]\ => \^bm_end_r1_reg\,
      \ras_timer_r_reg[0]_0\ => \ras_timer_r_reg[0]\,
      \ras_timer_r_reg[0]_1\ => \ras_timer_r_reg[0]_0\,
      \ras_timer_r_reg[0]_2\ => \ras_timer_r_reg[0]_1\,
      \ras_timer_r_reg[0]_3\ => \ras_timer_r_reg[0]_2\,
      \ras_timer_r_reg[0]_4\ => \ras_timer_r_reg[0]_3\,
      \ras_timer_r_reg[0]_5\ => \ras_timer_r_reg[0]_4\,
      \ras_timer_r_reg[0]_6\ => \ras_timer_r_reg[0]_5\,
      \ras_timer_r_reg[1]\ => \^ras_timer_r_reg[1]\,
      \ras_timer_r_reg[1]_0\ => \ras_timer_r_reg[1]_0\,
      \ras_timer_r_reg[1]_1\ => \ras_timer_r_reg[1]_1\,
      \ras_timer_r_reg[1]_2\ => \ras_timer_r_reg[1]_2\,
      ras_timer_zero_r => ras_timer_zero_r,
      \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]\ => \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]\,
      \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_0\ => \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_0\,
      \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_1\ => \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_1\,
      \rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_0\ => \rb_hit_busies.rb_hit_busies_r_lcl_reg[4]\,
      \rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_1\ => \rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_0\,
      \rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_2\ => \rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_1\,
      \rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_3\ => \rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_2\,
      \rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_0\ => \rb_hit_busies.rb_hit_busies_r_lcl_reg[6]\(0),
      \rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_1\ => \rb_hit_busies.rb_hit_busies_r_lcl_reg[5]\,
      \rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_2\ => \rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_0\,
      \rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_3\ => \rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_1\,
      \rb_hit_busies.rb_hit_busies_r_lcl_reg[6]_0\ => \rb_hit_busies.rb_hit_busies_r_lcl_reg[6]\(1),
      \rb_hit_busies.rb_hit_busies_r_lcl_reg[6]_1\ => \^rb_hit_busies.rb_hit_busies_r_lcl_reg[6]_0\,
      \rb_hit_busies.rb_hit_busies_r_lcl_reg[6]_2\ => \rb_hit_busies.rb_hit_busies_r_lcl_reg[6]_1\,
      \rb_hit_busies.rb_hit_busies_r_lcl_reg[6]_3\ => \rb_hit_busies.rb_hit_busies_r_lcl_reg[6]_2\,
      \rb_hit_busies.rb_hit_busies_r_lcl_reg[6]_4\ => \rb_hit_busies.rb_hit_busies_r_lcl_reg[6]_3\,
      rb_hit_busies_r(0) => rb_hit_busies_r(0),
      rb_hit_busies_r_1(0) => rb_hit_busies_r_1(0),
      rb_hit_busy_r_reg => rb_hit_busy_r_reg_0,
      rb_hit_busy_r_reg_0 => rb_hit_busy_r_reg_1,
      rb_hit_busy_r_reg_1 => rb_hit_busy_r_reg_2,
      rd_wr_r_lcl_reg => rd_wr_r_lcl_reg_0,
      req_bank_rdy_ns => \^req_bank_rdy_ns\,
      req_bank_rdy_r_reg => \^col_wait_r_reg\,
      req_bank_rdy_r_reg_0 => req_bank_rdy_r_reg,
      req_priority_r => req_priority_r,
      tail_r_18 => tail_r_18,
      use_addr => use_addr,
      wait_for_maint_r_15 => \^wait_for_maint_r_15\,
      wait_for_maint_r_lcl_reg_0 => wait_for_maint_r_lcl_reg,
      wait_for_maint_r_lcl_reg_1 => wait_for_maint_r_lcl_reg_0
    );
bank_state0: entity work.\mig_mig_7series_v4_2_bank_state__parameterized2\
     port map (
      D(1 downto 0) => ras_timer_passed_ns(1 downto 0),
      Q(1 downto 0) => Q(1 downto 0),
      act_this_rank_r(0) => act_this_rank_r(0),
      act_wait_r_lcl_reg_0 => \^act_wait_r_lcl_reg\,
      act_wait_r_lcl_reg_1 => act_wait_r_lcl_reg_1,
      act_wait_r_lcl_reg_2 => \^pre_bm_end_r_reg\,
      act_wait_r_lcl_reg_3(1 downto 0) => act_wait_r_lcl_reg_2(1 downto 0),
      act_wait_r_lcl_reg_4 => \^rb_hit_busies.rb_hit_busies_r_lcl_reg[6]_0\,
      auto_pre_r_lcl_reg => auto_pre_r_lcl_reg_0,
      bm_end_r1_1 => bm_end_r1_1,
      bm_end_r1_reg_0 => \^bm_end_r1_reg\,
      \cmd_pipe_plus.mc_address[10]_i_2\(0) => \^req_row_r_lcl_reg[13]\(10),
      \cmd_pipe_plus.mc_address[10]_i_2_0\(0) => \cmd_pipe_plus.mc_address[10]_i_2\(0),
      col_wait_r_reg_0 => \^col_wait_r_reg\,
      col_wait_r_reg_1 => col_wait_r_reg_0,
      demand_priority_r => demand_priority_r,
      demand_priority_r_reg_0 => demand_priority_r_reg,
      demand_priority_r_reg_1 => demand_priority_r_reg_0,
      demand_priority_r_reg_2 => demand_priority_r_reg_1,
      demand_priority_r_reg_3 => \^idle_r_lcl_reg\,
      demand_priority_r_reg_4 => bank_queue0_n_26,
      demand_priority_r_reg_5 => demand_priority_r_reg_2,
      demand_priority_r_reg_6 => \^req_wr_r_lcl_reg\,
      demanded_prior_r => demanded_prior_r,
      demanded_prior_r_reg_0 => demanded_prior_r_0,
      demanded_prior_r_reg_1 => demanded_prior_r_reg,
      \grant_r_reg[3]\ => \grant_r_reg[3]\,
      ofs_rdy_r => ofs_rdy_r,
      ofs_rdy_r0 => ofs_rdy_r0,
      ofs_rdy_r_reg_0 => ofs_rdy_r_reg,
      p_13_out => p_13_out,
      pass_open_bank_ns => pass_open_bank_ns,
      \pre_4_1_1T_arb.granted_pre_ns\ => \pre_4_1_1T_arb.granted_pre_ns\,
      \pre_4_1_1T_arb.granted_pre_r_reg\ => \pre_4_1_1T_arb.granted_pre_r_reg\,
      \pre_4_1_1T_arb.granted_pre_r_reg_0\ => \pre_4_1_1T_arb.granted_pre_r_reg_0\,
      pre_bm_end_ns => pre_bm_end_ns,
      pre_bm_end_r_reg(0) => pre_bm_end_r_reg_2(0),
      pre_bm_end_r_reg_0 => \^auto_pre_r_lcl_reg\,
      pre_passing_open_bank_ns => pre_passing_open_bank_ns,
      pre_wait_r => pre_wait_r,
      pre_wait_r_reg_0 => pre_wait_r_reg,
      q_has_rd_12 => \^q_has_rd_12\,
      \ras_timer_r_reg[0]_0\ => \ras_timer_r_reg[0]_6\,
      \ras_timer_r_reg[1]_0\ => \^ras_timer_r_reg[1]\,
      ras_timer_zero_r => ras_timer_zero_r,
      ras_timer_zero_r_reg_0 => ras_timer_zero_r_reg,
      rd_this_rank_r(0) => rd_this_rank_r(0),
      \rd_this_rank_r_reg[0]_0\ => \^rd_wr_r_lcl_reg\,
      req_bank_rdy_ns => \^req_bank_rdy_ns\,
      row_cmd_wr(0) => row_cmd_wr(0),
      \rtp_timer_r_reg[0]_0\ => \rtp_timer_r_reg[0]\,
      \rtp_timer_r_reg[1]_0\ => \^pass_open_bank_r_lcl_reg\,
      start_wtp_timer0 => start_wtp_timer0,
      wr_this_rank_r(0) => wr_this_rank_r(0)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mig_mig_7series_v4_2_ddr_byte_lane is
  port (
    out_dqs_0 : out STD_LOGIC;
    ts_dqs_0 : out STD_LOGIC;
    A_rst_primitives_reg : out STD_LOGIC;
    mem_dq_out : out STD_LOGIC_VECTOR ( 8 downto 0 );
    mem_dq_ts : out STD_LOGIC_VECTOR ( 8 downto 0 );
    in0 : out STD_LOGIC_VECTOR ( 0 to 0 );
    A_rst_primitives_reg_0 : out STD_LOGIC;
    COUNTERREADVAL : out STD_LOGIC_VECTOR ( 5 downto 0 );
    A_rst_primitives_reg_1 : out STD_LOGIC_VECTOR ( 8 downto 0 );
    if_empty_r : out STD_LOGIC_VECTOR ( 0 to 0 );
    \my_empty_reg[4]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    idelay_ld_rst_3 : out STD_LOGIC;
    \my_empty_reg[1]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_0\ : out STD_LOGIC;
    \rd_ptr_reg[3]\ : out STD_LOGIC_VECTOR ( 63 downto 0 );
    Q : out STD_LOGIC_VECTOR ( 2 downto 0 );
    \wr_ptr_timing_reg[3]\ : in STD_LOGIC;
    \input_[9].iserdes_dq_.iserdesdq\ : in STD_LOGIC;
    mem_dq_in : in STD_LOGIC_VECTOR ( 7 downto 0 );
    idelay_inc : in STD_LOGIC;
    LD0_10 : in STD_LOGIC;
    A_rst_primitives : in STD_LOGIC;
    CLKB0_10 : in STD_LOGIC;
    phaser_ctl_bus : in STD_LOGIC_VECTOR ( 3 downto 0 );
    \pi_dqs_found_lanes_r1_reg[8]\ : in STD_LOGIC;
    \pi_dqs_found_lanes_r1_reg[8]_0\ : in STD_LOGIC;
    \pi_dqs_found_lanes_r1_reg[8]_1\ : in STD_LOGIC;
    \pi_dqs_found_lanes_r1_reg[8]_2\ : in STD_LOGIC;
    freq_refclk : in STD_LOGIC;
    mem_refclk : in STD_LOGIC;
    mem_dqs_in : in STD_LOGIC_VECTOR ( 0 to 0 );
    ififo_rst_reg_0 : in STD_LOGIC;
    sync_pulse : in STD_LOGIC;
    PCENABLECALIB : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \pi_dqs_found_lanes_r1_reg[8]_3\ : in STD_LOGIC_VECTOR ( 5 downto 0 );
    \po_counter_read_val_reg[8]\ : in STD_LOGIC;
    \po_counter_read_val_reg[8]_0\ : in STD_LOGIC;
    \po_counter_read_val_reg[8]_1\ : in STD_LOGIC;
    \my_empty_reg[7]\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    D2 : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \my_empty_reg[7]_0\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \my_empty_reg[7]_1\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \my_empty_reg[7]_2\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \my_empty_reg[7]_3\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \my_empty_reg[7]_4\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \my_empty_reg[7]_5\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    phy_if_reset : in STD_LOGIC;
    \my_full_reg[1]\ : in STD_LOGIC;
    phy_data_wr_en : in STD_LOGIC;
    rst_r4 : in STD_LOGIC;
    out_fifo_0 : in STD_LOGIC;
    out_fifo_1 : in STD_LOGIC_VECTOR ( 7 downto 0 );
    out_fifo_2 : in STD_LOGIC;
    \out_fifo_i_75__0\ : in STD_LOGIC_VECTOR ( 71 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of mig_mig_7series_v4_2_ddr_byte_lane : entity is "mig_7series_v4_2_ddr_byte_lane";
end mig_mig_7series_v4_2_ddr_byte_lane;

architecture STRUCTURE of mig_mig_7series_v4_2_ddr_byte_lane is
  signal \^a_rst_primitives_reg\ : STD_LOGIC;
  signal if_d1 : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal if_d2 : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal if_d3 : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal if_d4 : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal if_d5 : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal if_d6 : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal if_d7 : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal if_d9 : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \if_empty_\ : STD_LOGIC;
  signal \^if_empty_r\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal ififo_rst : STD_LOGIC;
  signal ififo_wr_enable : STD_LOGIC;
  signal \in_fifo_gen.in_fifo_n_0\ : STD_LOGIC;
  signal \in_fifo_gen.in_fifo_n_1\ : STD_LOGIC;
  signal \in_fifo_gen.in_fifo_n_3\ : STD_LOGIC;
  signal iserdes_clkdiv : STD_LOGIC;
  signal of_d0 : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal of_dqbus : STD_LOGIC_VECTOR ( 39 downto 0 );
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_0\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_2\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_3\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_4\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_5\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_6\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_7\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_8\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_9\ : STD_LOGIC;
  signal ofifo_rst : STD_LOGIC;
  signal oserdes_clk : STD_LOGIC;
  signal oserdes_clk_delayed : STD_LOGIC;
  signal oserdes_clkdiv : STD_LOGIC;
  signal oserdes_dq_ts : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal oserdes_dqs : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal oserdes_dqs_ts : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal out_fifo_n_0 : STD_LOGIC;
  signal out_fifo_n_1 : STD_LOGIC;
  signal out_fifo_n_2 : STD_LOGIC;
  signal out_fifo_n_3 : STD_LOGIC;
  signal \phaser_in_gen.phaser_in_n_1\ : STD_LOGIC;
  signal \phaser_in_gen.phaser_in_n_2\ : STD_LOGIC;
  signal \phaser_in_gen.phaser_in_n_5\ : STD_LOGIC;
  signal \phaser_in_gen.phaser_in_n_7\ : STD_LOGIC;
  signal phaser_out_n_0 : STD_LOGIC;
  signal phaser_out_n_1 : STD_LOGIC;
  signal po_oserdes_rst : STD_LOGIC;
  signal po_rd_enable : STD_LOGIC;
  signal rd_data : STD_LOGIC_VECTOR ( 79 downto 0 );
  signal rd_data_r : STD_LOGIC_VECTOR ( 79 downto 6 );
  signal \NLW_in_fifo_gen.in_fifo_D5_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 4 );
  signal \NLW_in_fifo_gen.in_fifo_D6_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 4 );
  signal NLW_out_fifo_Q5_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 4 );
  signal NLW_out_fifo_Q6_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 4 );
  signal NLW_phaser_out_PHASEREFCLK_UNCONNECTED : STD_LOGIC;
  attribute syn_maxfan : string;
  attribute syn_maxfan of \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]\ : label is "3";
  attribute BOX_TYPE : string;
  attribute BOX_TYPE of \in_fifo_gen.in_fifo\ : label is "PRIMITIVE";
  attribute BOX_TYPE of out_fifo : label is "PRIMITIVE";
  attribute BOX_TYPE of \phaser_in_gen.phaser_in\ : label is "PRIMITIVE";
  attribute BOX_TYPE of phaser_out : label is "PRIMITIVE";
begin
  A_rst_primitives_reg <= \^a_rst_primitives_reg\;
  if_empty_r(0) <= \^if_empty_r\(0);
ddr_byte_group_io: entity work.mig_mig_7series_v4_2_ddr_byte_group_io
     port map (
      A_rst_primitives => A_rst_primitives,
      CLKB0_10 => CLKB0_10,
      CTSBUS(0) => oserdes_dqs_ts(0),
      D1(3 downto 0) => if_d1(3 downto 0),
      D2(3 downto 0) => if_d2(3 downto 0),
      D3(3 downto 0) => if_d3(3 downto 0),
      D4(3 downto 0) => if_d4(3 downto 0),
      D5(3 downto 0) => if_d5(3 downto 0),
      D6(3 downto 0) => if_d6(3 downto 0),
      D7(3 downto 0) => if_d7(3 downto 0),
      D9(3 downto 0) => if_d9(3 downto 0),
      DQSBUS(1 downto 0) => oserdes_dqs(1 downto 0),
      DTSBUS(1 downto 0) => oserdes_dq_ts(1 downto 0),
      LD0_10 => LD0_10,
      \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]\ => \^a_rst_primitives_reg\,
      idelay_inc => idelay_inc,
      idelay_ld_rst_3 => idelay_ld_rst_3,
      idelay_ld_rst_reg_0 => \wr_ptr_timing_reg[3]\,
      \input_[9].iserdes_dq_.iserdesdq_0\ => \input_[9].iserdes_dq_.iserdesdq\,
      iserdes_clkdiv => iserdes_clkdiv,
      mem_dq_in(7 downto 0) => mem_dq_in(7 downto 0),
      mem_dq_out(8 downto 0) => mem_dq_out(8 downto 0),
      mem_dq_ts(8 downto 0) => mem_dq_ts(8 downto 0),
      of_dqbus(35 downto 32) => of_dqbus(39 downto 36),
      of_dqbus(31 downto 0) => of_dqbus(31 downto 0),
      oserdes_clk => oserdes_clk,
      oserdes_clk_delayed => oserdes_clk_delayed,
      oserdes_clkdiv => oserdes_clkdiv,
      out_dqs_0 => out_dqs_0,
      po_oserdes_rst => po_oserdes_rst,
      rst_r4 => rst_r4,
      ts_dqs_0 => ts_dqs_0
    );
\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_ptr_timing_reg[3]\,
      CE => '1',
      D => \if_empty_\,
      Q => \^if_empty_r\(0),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_ptr_timing_reg[3]\,
      CE => '1',
      D => rd_data(10),
      Q => rd_data_r(10),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_ptr_timing_reg[3]\,
      CE => '1',
      D => rd_data(11),
      Q => rd_data_r(11),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_ptr_timing_reg[3]\,
      CE => '1',
      D => rd_data(12),
      Q => rd_data_r(12),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_ptr_timing_reg[3]\,
      CE => '1',
      D => rd_data(13),
      Q => rd_data_r(13),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_ptr_timing_reg[3]\,
      CE => '1',
      D => rd_data(14),
      Q => rd_data_r(14),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_ptr_timing_reg[3]\,
      CE => '1',
      D => rd_data(15),
      Q => rd_data_r(15),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_ptr_timing_reg[3]\,
      CE => '1',
      D => rd_data(16),
      Q => rd_data_r(16),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_ptr_timing_reg[3]\,
      CE => '1',
      D => rd_data(17),
      Q => rd_data_r(17),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_ptr_timing_reg[3]\,
      CE => '1',
      D => rd_data(18),
      Q => rd_data_r(18),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_ptr_timing_reg[3]\,
      CE => '1',
      D => rd_data(19),
      Q => rd_data_r(19),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_ptr_timing_reg[3]\,
      CE => '1',
      D => rd_data(20),
      Q => rd_data_r(20),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_ptr_timing_reg[3]\,
      CE => '1',
      D => rd_data(21),
      Q => rd_data_r(21),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_ptr_timing_reg[3]\,
      CE => '1',
      D => rd_data(22),
      Q => rd_data_r(22),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_ptr_timing_reg[3]\,
      CE => '1',
      D => rd_data(23),
      Q => rd_data_r(23),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_ptr_timing_reg[3]\,
      CE => '1',
      D => rd_data(24),
      Q => rd_data_r(24),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_ptr_timing_reg[3]\,
      CE => '1',
      D => rd_data(25),
      Q => rd_data_r(25),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_ptr_timing_reg[3]\,
      CE => '1',
      D => rd_data(26),
      Q => rd_data_r(26),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_ptr_timing_reg[3]\,
      CE => '1',
      D => rd_data(27),
      Q => rd_data_r(27),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_ptr_timing_reg[3]\,
      CE => '1',
      D => rd_data(28),
      Q => rd_data_r(28),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_ptr_timing_reg[3]\,
      CE => '1',
      D => rd_data(29),
      Q => rd_data_r(29),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_ptr_timing_reg[3]\,
      CE => '1',
      D => rd_data(30),
      Q => rd_data_r(30),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_ptr_timing_reg[3]\,
      CE => '1',
      D => rd_data(31),
      Q => rd_data_r(31),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_ptr_timing_reg[3]\,
      CE => '1',
      D => rd_data(32),
      Q => rd_data_r(32),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_ptr_timing_reg[3]\,
      CE => '1',
      D => rd_data(33),
      Q => rd_data_r(33),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_ptr_timing_reg[3]\,
      CE => '1',
      D => rd_data(34),
      Q => rd_data_r(34),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_ptr_timing_reg[3]\,
      CE => '1',
      D => rd_data(35),
      Q => rd_data_r(35),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_ptr_timing_reg[3]\,
      CE => '1',
      D => rd_data(36),
      Q => rd_data_r(36),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_ptr_timing_reg[3]\,
      CE => '1',
      D => rd_data(37),
      Q => rd_data_r(37),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_ptr_timing_reg[3]\,
      CE => '1',
      D => rd_data(38),
      Q => rd_data_r(38),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_ptr_timing_reg[3]\,
      CE => '1',
      D => rd_data(39),
      Q => rd_data_r(39),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_ptr_timing_reg[3]\,
      CE => '1',
      D => rd_data(40),
      Q => rd_data_r(40),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_ptr_timing_reg[3]\,
      CE => '1',
      D => rd_data(41),
      Q => rd_data_r(41),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_ptr_timing_reg[3]\,
      CE => '1',
      D => rd_data(42),
      Q => rd_data_r(42),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_ptr_timing_reg[3]\,
      CE => '1',
      D => rd_data(43),
      Q => rd_data_r(43),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_ptr_timing_reg[3]\,
      CE => '1',
      D => rd_data(44),
      Q => rd_data_r(44),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_ptr_timing_reg[3]\,
      CE => '1',
      D => rd_data(45),
      Q => rd_data_r(45),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_ptr_timing_reg[3]\,
      CE => '1',
      D => rd_data(46),
      Q => rd_data_r(46),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_ptr_timing_reg[3]\,
      CE => '1',
      D => rd_data(47),
      Q => rd_data_r(47),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_ptr_timing_reg[3]\,
      CE => '1',
      D => rd_data(48),
      Q => rd_data_r(48),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_ptr_timing_reg[3]\,
      CE => '1',
      D => rd_data(49),
      Q => rd_data_r(49),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_ptr_timing_reg[3]\,
      CE => '1',
      D => rd_data(50),
      Q => rd_data_r(50),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_ptr_timing_reg[3]\,
      CE => '1',
      D => rd_data(51),
      Q => rd_data_r(51),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_ptr_timing_reg[3]\,
      CE => '1',
      D => rd_data(52),
      Q => rd_data_r(52),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_ptr_timing_reg[3]\,
      CE => '1',
      D => rd_data(53),
      Q => rd_data_r(53),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_ptr_timing_reg[3]\,
      CE => '1',
      D => rd_data(54),
      Q => rd_data_r(54),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_ptr_timing_reg[3]\,
      CE => '1',
      D => rd_data(55),
      Q => rd_data_r(55),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_ptr_timing_reg[3]\,
      CE => '1',
      D => rd_data(56),
      Q => rd_data_r(56),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_ptr_timing_reg[3]\,
      CE => '1',
      D => rd_data(57),
      Q => rd_data_r(57),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_ptr_timing_reg[3]\,
      CE => '1',
      D => rd_data(58),
      Q => rd_data_r(58),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_ptr_timing_reg[3]\,
      CE => '1',
      D => rd_data(59),
      Q => rd_data_r(59),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_ptr_timing_reg[3]\,
      CE => '1',
      D => rd_data(60),
      Q => rd_data_r(60),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_ptr_timing_reg[3]\,
      CE => '1',
      D => rd_data(61),
      Q => rd_data_r(61),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_ptr_timing_reg[3]\,
      CE => '1',
      D => rd_data(62),
      Q => rd_data_r(62),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_ptr_timing_reg[3]\,
      CE => '1',
      D => rd_data(63),
      Q => rd_data_r(63),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_ptr_timing_reg[3]\,
      CE => '1',
      D => rd_data(64),
      Q => rd_data_r(64),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_ptr_timing_reg[3]\,
      CE => '1',
      D => rd_data(65),
      Q => rd_data_r(65),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_ptr_timing_reg[3]\,
      CE => '1',
      D => rd_data(6),
      Q => rd_data_r(6),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_ptr_timing_reg[3]\,
      CE => '1',
      D => rd_data(72),
      Q => rd_data_r(72),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_ptr_timing_reg[3]\,
      CE => '1',
      D => rd_data(73),
      Q => rd_data_r(73),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_ptr_timing_reg[3]\,
      CE => '1',
      D => rd_data(74),
      Q => rd_data_r(74),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_ptr_timing_reg[3]\,
      CE => '1',
      D => rd_data(75),
      Q => rd_data_r(75),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_ptr_timing_reg[3]\,
      CE => '1',
      D => rd_data(76),
      Q => rd_data_r(76),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_ptr_timing_reg[3]\,
      CE => '1',
      D => rd_data(77),
      Q => rd_data_r(77),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_ptr_timing_reg[3]\,
      CE => '1',
      D => rd_data(78),
      Q => rd_data_r(78),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_ptr_timing_reg[3]\,
      CE => '1',
      D => rd_data(79),
      Q => rd_data_r(79),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_ptr_timing_reg[3]\,
      CE => '1',
      D => rd_data(7),
      Q => rd_data_r(7),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_ptr_timing_reg[3]\,
      CE => '1',
      D => rd_data(8),
      Q => rd_data_r(8),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_ptr_timing_reg[3]\,
      CE => '1',
      D => rd_data(9),
      Q => rd_data_r(9),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo\: entity work.mig_mig_7series_v4_2_ddr_if_post_fifo_20
     port map (
      Q(67 downto 60) => rd_data_r(79 downto 72),
      Q(59 downto 0) => rd_data_r(65 downto 6),
      \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]\ => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_0\,
      ififo_rst => ififo_rst,
      \my_empty_reg[4]_0\ => \my_empty_reg[4]\(0),
      \my_full_reg[1]_0\ => \^if_empty_r\(0),
      \my_full_reg[1]_1\ => \my_full_reg[1]\,
      \rd_ptr_reg[1]_0\ => \wr_ptr_timing_reg[3]\
    );
ififo_rst_reg: unisim.vcomponents.FDSE
    generic map(
      INIT => '1'
    )
        port map (
      C => \wr_ptr_timing_reg[3]\,
      CE => '1',
      D => ififo_rst_reg_0,
      Q => ififo_rst,
      S => phy_if_reset
    );
\in_fifo_gen.in_fifo\: unisim.vcomponents.IN_FIFO
    generic map(
      ALMOST_EMPTY_VALUE => 1,
      ALMOST_FULL_VALUE => 1,
      ARRAY_MODE => "ARRAY_MODE_4_X_8",
      SYNCHRONOUS_MODE => "FALSE"
    )
        port map (
      ALMOSTEMPTY => \in_fifo_gen.in_fifo_n_0\,
      ALMOSTFULL => \in_fifo_gen.in_fifo_n_1\,
      D0(3 downto 0) => B"0000",
      D1(3 downto 0) => if_d1(3 downto 0),
      D2(3 downto 0) => if_d2(3 downto 0),
      D3(3 downto 0) => if_d3(3 downto 0),
      D4(3 downto 0) => if_d4(3 downto 0),
      D5(7 downto 4) => \NLW_in_fifo_gen.in_fifo_D5_UNCONNECTED\(7 downto 4),
      D5(3 downto 0) => if_d5(3 downto 0),
      D6(7 downto 4) => \NLW_in_fifo_gen.in_fifo_D6_UNCONNECTED\(7 downto 4),
      D6(3 downto 0) => if_d6(3 downto 0),
      D7(3 downto 0) => if_d7(3 downto 0),
      D8(3 downto 0) => B"0000",
      D9(3 downto 0) => if_d9(3 downto 0),
      EMPTY => \if_empty_\,
      FULL => \in_fifo_gen.in_fifo_n_3\,
      Q0(7 downto 0) => rd_data(7 downto 0),
      Q1(7 downto 0) => rd_data(15 downto 8),
      Q2(7 downto 0) => rd_data(23 downto 16),
      Q3(7 downto 0) => rd_data(31 downto 24),
      Q4(7 downto 0) => rd_data(39 downto 32),
      Q5(7 downto 0) => rd_data(47 downto 40),
      Q6(7 downto 0) => rd_data(55 downto 48),
      Q7(7 downto 0) => rd_data(63 downto 56),
      Q8(7 downto 0) => rd_data(71 downto 64),
      Q9(7 downto 0) => rd_data(79 downto 72),
      RDCLK => \wr_ptr_timing_reg[3]\,
      RDEN => '1',
      RESET => ififo_rst,
      WRCLK => iserdes_clkdiv,
      WREN => ififo_wr_enable
    );
\of_pre_fifo_gen.u_ddr_of_pre_fifo\: entity work.\mig_mig_7series_v4_2_ddr_of_pre_fifo__parameterized1_21\
     port map (
      D0(7 downto 0) => of_d0(7 downto 0),
      D8(7) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_2\,
      D8(6) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_3\,
      D8(5) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_4\,
      D8(4) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_5\,
      D8(3) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_6\,
      D8(2) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_7\,
      D8(1) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_8\,
      D8(0) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_9\,
      Q(2 downto 0) => Q(2 downto 0),
      \my_empty_reg[1]_0\ => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_0\,
      \my_empty_reg[1]_1\ => \my_empty_reg[1]\,
      \my_empty_reg[7]_0\ => out_fifo_n_3,
      ofifo_rst => ofifo_rst,
      out_fifo => out_fifo_0,
      out_fifo_0(7 downto 0) => out_fifo_1(7 downto 0),
      out_fifo_1 => out_fifo_2,
      \out_fifo_i_75__0\(71 downto 0) => \out_fifo_i_75__0\(71 downto 0),
      phy_data_wr_en => phy_data_wr_en,
      \rd_ptr_reg[3]_0\(63 downto 0) => \rd_ptr_reg[3]\(63 downto 0),
      \wr_ptr_timing_reg[3]_0\ => \wr_ptr_timing_reg[3]\
    );
ofifo_rst_reg: unisim.vcomponents.FDSE
    generic map(
      INIT => '1'
    )
        port map (
      C => \wr_ptr_timing_reg[3]\,
      CE => '1',
      D => ififo_rst_reg_0,
      Q => ofifo_rst,
      S => A_rst_primitives
    );
out_fifo: unisim.vcomponents.OUT_FIFO
    generic map(
      ALMOST_EMPTY_VALUE => 1,
      ALMOST_FULL_VALUE => 1,
      ARRAY_MODE => "ARRAY_MODE_8_X_4",
      OUTPUT_DISABLE => "FALSE",
      SYNCHRONOUS_MODE => "FALSE"
    )
        port map (
      ALMOSTEMPTY => out_fifo_n_0,
      ALMOSTFULL => out_fifo_n_1,
      D0(7 downto 0) => of_d0(7 downto 0),
      D1(7 downto 0) => \my_empty_reg[7]\(7 downto 0),
      D2(7 downto 0) => D2(7 downto 0),
      D3(7 downto 0) => \my_empty_reg[7]_0\(7 downto 0),
      D4(7 downto 0) => \my_empty_reg[7]_1\(7 downto 0),
      D5(7 downto 0) => \my_empty_reg[7]_2\(7 downto 0),
      D6(7 downto 0) => \my_empty_reg[7]_3\(7 downto 0),
      D7(7 downto 0) => \my_empty_reg[7]_4\(7 downto 0),
      D8(7) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_2\,
      D8(6) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_3\,
      D8(5) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_4\,
      D8(4) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_5\,
      D8(3) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_6\,
      D8(2) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_7\,
      D8(1) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_8\,
      D8(0) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_9\,
      D9(7 downto 0) => \my_empty_reg[7]_5\(7 downto 0),
      EMPTY => out_fifo_n_2,
      FULL => out_fifo_n_3,
      Q0(3 downto 0) => of_dqbus(3 downto 0),
      Q1(3 downto 0) => of_dqbus(7 downto 4),
      Q2(3 downto 0) => of_dqbus(11 downto 8),
      Q3(3 downto 0) => of_dqbus(15 downto 12),
      Q4(3 downto 0) => of_dqbus(19 downto 16),
      Q5(7 downto 4) => NLW_out_fifo_Q5_UNCONNECTED(7 downto 4),
      Q5(3 downto 0) => of_dqbus(23 downto 20),
      Q6(7 downto 4) => NLW_out_fifo_Q6_UNCONNECTED(7 downto 4),
      Q6(3 downto 0) => of_dqbus(27 downto 24),
      Q7(3 downto 0) => of_dqbus(31 downto 28),
      Q8(3 downto 0) => of_dqbus(35 downto 32),
      Q9(3 downto 0) => of_dqbus(39 downto 36),
      RDCLK => oserdes_clkdiv,
      RDEN => po_rd_enable,
      RESET => ofifo_rst,
      WRCLK => \wr_ptr_timing_reg[3]\,
      WREN => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_0\
    );
\phaser_in_gen.phaser_in\: unisim.vcomponents.PHASER_IN_PHY
    generic map(
      BURST_MODE => "TRUE",
      CLKOUT_DIV => 2,
      DQS_AUTO_RECAL => '1',
      DQS_BIAS_MODE => "FALSE",
      DQS_FIND_PATTERN => B"000",
      FINE_DELAY => 33,
      FREQ_REF_DIV => "DIV2",
      IS_RST_INVERTED => '0',
      MEMREFCLK_PERIOD => 2.500000,
      OUTPUT_CLK_SRC => "DELAYED_REF",
      PHASEREFCLK_PERIOD => 2.500000,
      REFCLK_PERIOD => 1.250000,
      SEL_CLK_OFFSET => 6,
      SYNC_IN_DIV_RST => "TRUE",
      WR_CYCLES => "FALSE"
    )
        port map (
      BURSTPENDINGPHY => phaser_ctl_bus(1),
      COUNTERLOADEN => \pi_dqs_found_lanes_r1_reg[8]\,
      COUNTERLOADVAL(5 downto 0) => \pi_dqs_found_lanes_r1_reg[8]_3\(5 downto 0),
      COUNTERREADEN => \pi_dqs_found_lanes_r1_reg[8]_0\,
      COUNTERREADVAL(5 downto 0) => COUNTERREADVAL(5 downto 0),
      DQSFOUND => in0(0),
      DQSOUTOFRANGE => \phaser_in_gen.phaser_in_n_1\,
      ENCALIBPHY(1 downto 0) => PCENABLECALIB(1 downto 0),
      FINEENABLE => \pi_dqs_found_lanes_r1_reg[8]_1\,
      FINEINC => \pi_dqs_found_lanes_r1_reg[8]_2\,
      FINEOVERFLOW => \phaser_in_gen.phaser_in_n_2\,
      FREQREFCLK => freq_refclk,
      ICLK => \^a_rst_primitives_reg\,
      ICLKDIV => iserdes_clkdiv,
      ISERDESRST => \phaser_in_gen.phaser_in_n_5\,
      MEMREFCLK => mem_refclk,
      PHASELOCKED => A_rst_primitives_reg_0,
      PHASEREFCLK => mem_dqs_in(0),
      RANKSELPHY(1 downto 0) => phaser_ctl_bus(3 downto 2),
      RCLK => \phaser_in_gen.phaser_in_n_7\,
      RST => A_rst_primitives,
      RSTDQSFIND => ififo_rst_reg_0,
      SYNCIN => sync_pulse,
      SYSCLK => \wr_ptr_timing_reg[3]\,
      WRENABLE => ififo_wr_enable
    );
phaser_out: unisim.vcomponents.PHASER_OUT_PHY
    generic map(
      CLKOUT_DIV => 2,
      COARSE_BYPASS => "FALSE",
      COARSE_DELAY => 0,
      DATA_CTL_N => "TRUE",
      DATA_RD_CYCLES => "FALSE",
      FINE_DELAY => 60,
      IS_RST_INVERTED => '0',
      MEMREFCLK_PERIOD => 2.500000,
      OCLKDELAY_INV => "FALSE",
      OCLK_DELAY => 0,
      OUTPUT_CLK_SRC => "DELAYED_REF",
      PHASEREFCLK_PERIOD => 1.000000,
      PO => B"111",
      REFCLK_PERIOD => 1.250000,
      SYNC_IN_DIV_RST => "TRUE"
    )
        port map (
      BURSTPENDINGPHY => phaser_ctl_bus(0),
      COARSEENABLE => \po_counter_read_val_reg[8]\,
      COARSEINC => \po_counter_read_val_reg[8]\,
      COARSEOVERFLOW => phaser_out_n_0,
      COUNTERLOADEN => '0',
      COUNTERLOADVAL(8 downto 0) => B"000000000",
      COUNTERREADEN => \pi_dqs_found_lanes_r1_reg[8]_0\,
      COUNTERREADVAL(8 downto 0) => A_rst_primitives_reg_1(8 downto 0),
      CTSBUS(1 downto 0) => oserdes_dqs_ts(1 downto 0),
      DQSBUS(1 downto 0) => oserdes_dqs(1 downto 0),
      DTSBUS(1 downto 0) => oserdes_dq_ts(1 downto 0),
      ENCALIBPHY(1 downto 0) => PCENABLECALIB(1 downto 0),
      FINEENABLE => \po_counter_read_val_reg[8]_0\,
      FINEINC => \po_counter_read_val_reg[8]_1\,
      FINEOVERFLOW => phaser_out_n_1,
      FREQREFCLK => freq_refclk,
      MEMREFCLK => mem_refclk,
      OCLK => oserdes_clk,
      OCLKDELAYED => oserdes_clk_delayed,
      OCLKDIV => oserdes_clkdiv,
      OSERDESRST => po_oserdes_rst,
      PHASEREFCLK => NLW_phaser_out_PHASEREFCLK_UNCONNECTED,
      RDENABLE => po_rd_enable,
      RST => A_rst_primitives,
      SELFINEOCLKDELAY => '0',
      SYNCIN => sync_pulse,
      SYSCLK => \wr_ptr_timing_reg[3]\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mig_mig_7series_v4_2_ddr_byte_lane_25 is
  port (
    out_dqs_4 : out STD_LOGIC;
    ts_dqs_4 : out STD_LOGIC;
    A_rst_primitives_reg : out STD_LOGIC;
    mem_dq_out : out STD_LOGIC_VECTOR ( 8 downto 0 );
    mem_dq_ts : out STD_LOGIC_VECTOR ( 8 downto 0 );
    in0 : out STD_LOGIC_VECTOR ( 0 to 0 );
    A_rst_primitives_reg_0 : out STD_LOGIC;
    COUNTERREADVAL : out STD_LOGIC_VECTOR ( 5 downto 0 );
    A_rst_primitives_reg_1 : out STD_LOGIC_VECTOR ( 8 downto 0 );
    idelay_ld_rst : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1\ : out STD_LOGIC;
    if_empty : out STD_LOGIC;
    \my_empty_reg[1]\ : out STD_LOGIC;
    phy_rddata_en : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_0\ : out STD_LOGIC;
    \rd_ptr_reg[3]\ : out STD_LOGIC_VECTOR ( 63 downto 0 );
    Q : out STD_LOGIC_VECTOR ( 2 downto 0 );
    \my_full_reg[4]\ : in STD_LOGIC;
    \input_[9].iserdes_dq_.iserdesdq\ : in STD_LOGIC;
    mem_dq_in : in STD_LOGIC_VECTOR ( 7 downto 0 );
    idelay_inc : in STD_LOGIC;
    LD0 : in STD_LOGIC;
    A_rst_primitives : in STD_LOGIC;
    CLKB0 : in STD_LOGIC;
    phaser_ctl_bus : in STD_LOGIC_VECTOR ( 3 downto 0 );
    \pi_dqs_found_lanes_r1_reg[0]\ : in STD_LOGIC;
    \pi_dqs_found_lanes_r1_reg[0]_0\ : in STD_LOGIC;
    \pi_dqs_found_lanes_r1_reg[0]_1\ : in STD_LOGIC;
    \pi_dqs_found_lanes_r1_reg[0]_2\ : in STD_LOGIC;
    freq_refclk : in STD_LOGIC;
    mem_refclk : in STD_LOGIC;
    mem_dqs_in : in STD_LOGIC_VECTOR ( 0 to 0 );
    ififo_rst_reg_0 : in STD_LOGIC;
    sync_pulse : in STD_LOGIC;
    PCENABLECALIB : in STD_LOGIC_VECTOR ( 1 downto 0 );
    COUNTERLOADVAL : in STD_LOGIC_VECTOR ( 5 downto 0 );
    \po_counter_read_val_reg[8]\ : in STD_LOGIC;
    \po_counter_read_val_reg[8]_0\ : in STD_LOGIC;
    \po_counter_read_val_reg[8]_1\ : in STD_LOGIC;
    \my_empty_reg[7]\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \my_empty_reg[7]_0\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \my_empty_reg[7]_1\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \my_empty_reg[7]_2\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \my_empty_reg[7]_3\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \my_empty_reg[7]_4\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \my_empty_reg[7]_5\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \my_empty_reg[7]_6\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    phy_if_reset : in STD_LOGIC;
    my_empty : in STD_LOGIC_VECTOR ( 1 downto 0 );
    if_empty_r : in STD_LOGIC_VECTOR ( 0 to 0 );
    \my_full_reg[1]\ : in STD_LOGIC;
    my_empty_0 : in STD_LOGIC_VECTOR ( 0 to 0 );
    \wr_ptr[1]_i_2\ : in STD_LOGIC;
    phy_if_empty_r_reg : in STD_LOGIC;
    if_empty_v : in STD_LOGIC_VECTOR ( 0 to 0 );
    phy_data_wr_en : in STD_LOGIC;
    rst_r4 : in STD_LOGIC;
    out_fifo_0 : in STD_LOGIC;
    out_fifo_1 : in STD_LOGIC_VECTOR ( 7 downto 0 );
    out_fifo_2 : in STD_LOGIC;
    phy_dout : in STD_LOGIC_VECTOR ( 71 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of mig_mig_7series_v4_2_ddr_byte_lane_25 : entity is "mig_7series_v4_2_ddr_byte_lane";
end mig_mig_7series_v4_2_ddr_byte_lane_25;

architecture STRUCTURE of mig_mig_7series_v4_2_ddr_byte_lane_25 is
  signal \^a_rst_primitives_reg\ : STD_LOGIC;
  signal if_d1 : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal if_d2 : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal if_d3 : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal if_d4 : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal if_d5 : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal if_d6 : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal if_d7 : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal if_d9 : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \if_empty_\ : STD_LOGIC;
  signal if_empty_r_0 : STD_LOGIC_VECTOR ( 3 to 3 );
  signal ififo_rst : STD_LOGIC;
  signal ififo_wr_enable : STD_LOGIC;
  signal \in_fifo_gen.in_fifo_n_0\ : STD_LOGIC;
  signal \in_fifo_gen.in_fifo_n_1\ : STD_LOGIC;
  signal \in_fifo_gen.in_fifo_n_3\ : STD_LOGIC;
  signal iserdes_clkdiv : STD_LOGIC;
  signal of_d0 : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal of_dqbus : STD_LOGIC_VECTOR ( 39 downto 0 );
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_0\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_2\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_3\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_4\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_5\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_6\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_7\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_8\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_9\ : STD_LOGIC;
  signal ofifo_rst : STD_LOGIC;
  signal oserdes_clk : STD_LOGIC;
  signal oserdes_clk_delayed : STD_LOGIC;
  signal oserdes_clkdiv : STD_LOGIC;
  signal oserdes_dq_ts : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal oserdes_dqs : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal oserdes_dqs_ts : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal out_fifo_n_0 : STD_LOGIC;
  signal out_fifo_n_1 : STD_LOGIC;
  signal out_fifo_n_2 : STD_LOGIC;
  signal out_fifo_n_3 : STD_LOGIC;
  signal \phaser_in_gen.phaser_in_n_1\ : STD_LOGIC;
  signal \phaser_in_gen.phaser_in_n_2\ : STD_LOGIC;
  signal \phaser_in_gen.phaser_in_n_5\ : STD_LOGIC;
  signal \phaser_in_gen.phaser_in_n_7\ : STD_LOGIC;
  signal phaser_out_n_0 : STD_LOGIC;
  signal phaser_out_n_1 : STD_LOGIC;
  signal po_oserdes_rst : STD_LOGIC;
  signal po_rd_enable : STD_LOGIC;
  signal rd_data : STD_LOGIC_VECTOR ( 79 downto 0 );
  signal rd_data_r : STD_LOGIC_VECTOR ( 79 downto 6 );
  signal \NLW_in_fifo_gen.in_fifo_D5_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 4 );
  signal \NLW_in_fifo_gen.in_fifo_D6_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 4 );
  signal NLW_out_fifo_Q5_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 4 );
  signal NLW_out_fifo_Q6_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 4 );
  signal NLW_phaser_out_PHASEREFCLK_UNCONNECTED : STD_LOGIC;
  attribute syn_maxfan : string;
  attribute syn_maxfan of \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]\ : label is "3";
  attribute BOX_TYPE : string;
  attribute BOX_TYPE of \in_fifo_gen.in_fifo\ : label is "PRIMITIVE";
  attribute BOX_TYPE of out_fifo : label is "PRIMITIVE";
  attribute BOX_TYPE of \phaser_in_gen.phaser_in\ : label is "PRIMITIVE";
  attribute BOX_TYPE of phaser_out : label is "PRIMITIVE";
begin
  A_rst_primitives_reg <= \^a_rst_primitives_reg\;
ddr_byte_group_io: entity work.mig_mig_7series_v4_2_ddr_byte_group_io_38
     port map (
      A_rst_primitives => A_rst_primitives,
      CLKB0 => CLKB0,
      CTSBUS(0) => oserdes_dqs_ts(0),
      D1(3 downto 0) => if_d1(3 downto 0),
      D2(3 downto 0) => if_d2(3 downto 0),
      D3(3 downto 0) => if_d3(3 downto 0),
      D4(3 downto 0) => if_d4(3 downto 0),
      D5(3 downto 0) => if_d5(3 downto 0),
      D6(3 downto 0) => if_d6(3 downto 0),
      D7(3 downto 0) => if_d7(3 downto 0),
      D9(3 downto 0) => if_d9(3 downto 0),
      DQSBUS(1 downto 0) => oserdes_dqs(1 downto 0),
      DTSBUS(1 downto 0) => oserdes_dq_ts(1 downto 0),
      LD0 => LD0,
      \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]\ => \^a_rst_primitives_reg\,
      idelay_inc => idelay_inc,
      idelay_ld_rst => idelay_ld_rst,
      idelay_ld_rst_reg_0 => \my_full_reg[4]\,
      \input_[9].iserdes_dq_.iserdesdq_0\ => \input_[9].iserdes_dq_.iserdesdq\,
      iserdes_clkdiv => iserdes_clkdiv,
      mem_dq_in(7 downto 0) => mem_dq_in(7 downto 0),
      mem_dq_out(8 downto 0) => mem_dq_out(8 downto 0),
      mem_dq_ts(8 downto 0) => mem_dq_ts(8 downto 0),
      of_dqbus(35 downto 32) => of_dqbus(39 downto 36),
      of_dqbus(31 downto 0) => of_dqbus(31 downto 0),
      oserdes_clk => oserdes_clk,
      oserdes_clk_delayed => oserdes_clk_delayed,
      oserdes_clkdiv => oserdes_clkdiv,
      out_dqs_4 => out_dqs_4,
      po_oserdes_rst => po_oserdes_rst,
      rst_r4 => rst_r4,
      ts_dqs_4 => ts_dqs_4
    );
\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => \my_full_reg[4]\,
      CE => '1',
      D => \if_empty_\,
      Q => if_empty_r_0(3),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => \my_full_reg[4]\,
      CE => '1',
      D => rd_data(10),
      Q => rd_data_r(10),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => \my_full_reg[4]\,
      CE => '1',
      D => rd_data(11),
      Q => rd_data_r(11),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]\: unisim.vcomponents.FDRE
     port map (
      C => \my_full_reg[4]\,
      CE => '1',
      D => rd_data(12),
      Q => rd_data_r(12),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]\: unisim.vcomponents.FDRE
     port map (
      C => \my_full_reg[4]\,
      CE => '1',
      D => rd_data(13),
      Q => rd_data_r(13),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]\: unisim.vcomponents.FDRE
     port map (
      C => \my_full_reg[4]\,
      CE => '1',
      D => rd_data(14),
      Q => rd_data_r(14),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]\: unisim.vcomponents.FDRE
     port map (
      C => \my_full_reg[4]\,
      CE => '1',
      D => rd_data(15),
      Q => rd_data_r(15),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]\: unisim.vcomponents.FDRE
     port map (
      C => \my_full_reg[4]\,
      CE => '1',
      D => rd_data(16),
      Q => rd_data_r(16),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]\: unisim.vcomponents.FDRE
     port map (
      C => \my_full_reg[4]\,
      CE => '1',
      D => rd_data(17),
      Q => rd_data_r(17),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]\: unisim.vcomponents.FDRE
     port map (
      C => \my_full_reg[4]\,
      CE => '1',
      D => rd_data(18),
      Q => rd_data_r(18),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]\: unisim.vcomponents.FDRE
     port map (
      C => \my_full_reg[4]\,
      CE => '1',
      D => rd_data(19),
      Q => rd_data_r(19),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]\: unisim.vcomponents.FDRE
     port map (
      C => \my_full_reg[4]\,
      CE => '1',
      D => rd_data(20),
      Q => rd_data_r(20),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]\: unisim.vcomponents.FDRE
     port map (
      C => \my_full_reg[4]\,
      CE => '1',
      D => rd_data(21),
      Q => rd_data_r(21),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]\: unisim.vcomponents.FDRE
     port map (
      C => \my_full_reg[4]\,
      CE => '1',
      D => rd_data(22),
      Q => rd_data_r(22),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]\: unisim.vcomponents.FDRE
     port map (
      C => \my_full_reg[4]\,
      CE => '1',
      D => rd_data(23),
      Q => rd_data_r(23),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]\: unisim.vcomponents.FDRE
     port map (
      C => \my_full_reg[4]\,
      CE => '1',
      D => rd_data(24),
      Q => rd_data_r(24),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]\: unisim.vcomponents.FDRE
     port map (
      C => \my_full_reg[4]\,
      CE => '1',
      D => rd_data(25),
      Q => rd_data_r(25),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]\: unisim.vcomponents.FDRE
     port map (
      C => \my_full_reg[4]\,
      CE => '1',
      D => rd_data(26),
      Q => rd_data_r(26),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]\: unisim.vcomponents.FDRE
     port map (
      C => \my_full_reg[4]\,
      CE => '1',
      D => rd_data(27),
      Q => rd_data_r(27),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]\: unisim.vcomponents.FDRE
     port map (
      C => \my_full_reg[4]\,
      CE => '1',
      D => rd_data(28),
      Q => rd_data_r(28),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]\: unisim.vcomponents.FDRE
     port map (
      C => \my_full_reg[4]\,
      CE => '1',
      D => rd_data(29),
      Q => rd_data_r(29),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]\: unisim.vcomponents.FDRE
     port map (
      C => \my_full_reg[4]\,
      CE => '1',
      D => rd_data(30),
      Q => rd_data_r(30),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]\: unisim.vcomponents.FDRE
     port map (
      C => \my_full_reg[4]\,
      CE => '1',
      D => rd_data(31),
      Q => rd_data_r(31),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]\: unisim.vcomponents.FDRE
     port map (
      C => \my_full_reg[4]\,
      CE => '1',
      D => rd_data(32),
      Q => rd_data_r(32),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]\: unisim.vcomponents.FDRE
     port map (
      C => \my_full_reg[4]\,
      CE => '1',
      D => rd_data(33),
      Q => rd_data_r(33),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]\: unisim.vcomponents.FDRE
     port map (
      C => \my_full_reg[4]\,
      CE => '1',
      D => rd_data(34),
      Q => rd_data_r(34),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]\: unisim.vcomponents.FDRE
     port map (
      C => \my_full_reg[4]\,
      CE => '1',
      D => rd_data(35),
      Q => rd_data_r(35),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]\: unisim.vcomponents.FDRE
     port map (
      C => \my_full_reg[4]\,
      CE => '1',
      D => rd_data(36),
      Q => rd_data_r(36),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]\: unisim.vcomponents.FDRE
     port map (
      C => \my_full_reg[4]\,
      CE => '1',
      D => rd_data(37),
      Q => rd_data_r(37),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]\: unisim.vcomponents.FDRE
     port map (
      C => \my_full_reg[4]\,
      CE => '1',
      D => rd_data(38),
      Q => rd_data_r(38),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]\: unisim.vcomponents.FDRE
     port map (
      C => \my_full_reg[4]\,
      CE => '1',
      D => rd_data(39),
      Q => rd_data_r(39),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]\: unisim.vcomponents.FDRE
     port map (
      C => \my_full_reg[4]\,
      CE => '1',
      D => rd_data(40),
      Q => rd_data_r(40),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]\: unisim.vcomponents.FDRE
     port map (
      C => \my_full_reg[4]\,
      CE => '1',
      D => rd_data(41),
      Q => rd_data_r(41),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]\: unisim.vcomponents.FDRE
     port map (
      C => \my_full_reg[4]\,
      CE => '1',
      D => rd_data(42),
      Q => rd_data_r(42),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]\: unisim.vcomponents.FDRE
     port map (
      C => \my_full_reg[4]\,
      CE => '1',
      D => rd_data(43),
      Q => rd_data_r(43),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]\: unisim.vcomponents.FDRE
     port map (
      C => \my_full_reg[4]\,
      CE => '1',
      D => rd_data(44),
      Q => rd_data_r(44),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]\: unisim.vcomponents.FDRE
     port map (
      C => \my_full_reg[4]\,
      CE => '1',
      D => rd_data(45),
      Q => rd_data_r(45),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]\: unisim.vcomponents.FDRE
     port map (
      C => \my_full_reg[4]\,
      CE => '1',
      D => rd_data(46),
      Q => rd_data_r(46),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]\: unisim.vcomponents.FDRE
     port map (
      C => \my_full_reg[4]\,
      CE => '1',
      D => rd_data(47),
      Q => rd_data_r(47),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]\: unisim.vcomponents.FDRE
     port map (
      C => \my_full_reg[4]\,
      CE => '1',
      D => rd_data(48),
      Q => rd_data_r(48),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]\: unisim.vcomponents.FDRE
     port map (
      C => \my_full_reg[4]\,
      CE => '1',
      D => rd_data(49),
      Q => rd_data_r(49),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]\: unisim.vcomponents.FDRE
     port map (
      C => \my_full_reg[4]\,
      CE => '1',
      D => rd_data(50),
      Q => rd_data_r(50),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]\: unisim.vcomponents.FDRE
     port map (
      C => \my_full_reg[4]\,
      CE => '1',
      D => rd_data(51),
      Q => rd_data_r(51),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]\: unisim.vcomponents.FDRE
     port map (
      C => \my_full_reg[4]\,
      CE => '1',
      D => rd_data(52),
      Q => rd_data_r(52),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]\: unisim.vcomponents.FDRE
     port map (
      C => \my_full_reg[4]\,
      CE => '1',
      D => rd_data(53),
      Q => rd_data_r(53),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]\: unisim.vcomponents.FDRE
     port map (
      C => \my_full_reg[4]\,
      CE => '1',
      D => rd_data(54),
      Q => rd_data_r(54),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]\: unisim.vcomponents.FDRE
     port map (
      C => \my_full_reg[4]\,
      CE => '1',
      D => rd_data(55),
      Q => rd_data_r(55),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]\: unisim.vcomponents.FDRE
     port map (
      C => \my_full_reg[4]\,
      CE => '1',
      D => rd_data(56),
      Q => rd_data_r(56),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]\: unisim.vcomponents.FDRE
     port map (
      C => \my_full_reg[4]\,
      CE => '1',
      D => rd_data(57),
      Q => rd_data_r(57),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]\: unisim.vcomponents.FDRE
     port map (
      C => \my_full_reg[4]\,
      CE => '1',
      D => rd_data(58),
      Q => rd_data_r(58),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]\: unisim.vcomponents.FDRE
     port map (
      C => \my_full_reg[4]\,
      CE => '1',
      D => rd_data(59),
      Q => rd_data_r(59),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]\: unisim.vcomponents.FDRE
     port map (
      C => \my_full_reg[4]\,
      CE => '1',
      D => rd_data(60),
      Q => rd_data_r(60),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]\: unisim.vcomponents.FDRE
     port map (
      C => \my_full_reg[4]\,
      CE => '1',
      D => rd_data(61),
      Q => rd_data_r(61),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]\: unisim.vcomponents.FDRE
     port map (
      C => \my_full_reg[4]\,
      CE => '1',
      D => rd_data(62),
      Q => rd_data_r(62),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]\: unisim.vcomponents.FDRE
     port map (
      C => \my_full_reg[4]\,
      CE => '1',
      D => rd_data(63),
      Q => rd_data_r(63),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]\: unisim.vcomponents.FDRE
     port map (
      C => \my_full_reg[4]\,
      CE => '1',
      D => rd_data(64),
      Q => rd_data_r(64),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]\: unisim.vcomponents.FDRE
     port map (
      C => \my_full_reg[4]\,
      CE => '1',
      D => rd_data(65),
      Q => rd_data_r(65),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => \my_full_reg[4]\,
      CE => '1',
      D => rd_data(6),
      Q => rd_data_r(6),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]\: unisim.vcomponents.FDRE
     port map (
      C => \my_full_reg[4]\,
      CE => '1',
      D => rd_data(72),
      Q => rd_data_r(72),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]\: unisim.vcomponents.FDRE
     port map (
      C => \my_full_reg[4]\,
      CE => '1',
      D => rd_data(73),
      Q => rd_data_r(73),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]\: unisim.vcomponents.FDRE
     port map (
      C => \my_full_reg[4]\,
      CE => '1',
      D => rd_data(74),
      Q => rd_data_r(74),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]\: unisim.vcomponents.FDRE
     port map (
      C => \my_full_reg[4]\,
      CE => '1',
      D => rd_data(75),
      Q => rd_data_r(75),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]\: unisim.vcomponents.FDRE
     port map (
      C => \my_full_reg[4]\,
      CE => '1',
      D => rd_data(76),
      Q => rd_data_r(76),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]\: unisim.vcomponents.FDRE
     port map (
      C => \my_full_reg[4]\,
      CE => '1',
      D => rd_data(77),
      Q => rd_data_r(77),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]\: unisim.vcomponents.FDRE
     port map (
      C => \my_full_reg[4]\,
      CE => '1',
      D => rd_data(78),
      Q => rd_data_r(78),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]\: unisim.vcomponents.FDRE
     port map (
      C => \my_full_reg[4]\,
      CE => '1',
      D => rd_data(79),
      Q => rd_data_r(79),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => \my_full_reg[4]\,
      CE => '1',
      D => rd_data(7),
      Q => rd_data_r(7),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => \my_full_reg[4]\,
      CE => '1',
      D => rd_data(8),
      Q => rd_data_r(8),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => \my_full_reg[4]\,
      CE => '1',
      D => rd_data(9),
      Q => rd_data_r(9),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo\: entity work.mig_mig_7series_v4_2_ddr_if_post_fifo_39
     port map (
      Q(67 downto 60) => rd_data_r(79 downto 72),
      Q(59 downto 0) => rd_data_r(65 downto 6),
      \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]\ => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0\,
      \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0\ => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1\,
      \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1\ => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_0\,
      if_empty => if_empty,
      if_empty_r(0) => if_empty_r(0),
      if_empty_r_0(0) => if_empty_r_0(3),
      if_empty_v(0) => if_empty_v(0),
      ififo_rst => ififo_rst,
      my_empty(1 downto 0) => my_empty(1 downto 0),
      my_empty_0(0) => my_empty_0(0),
      \my_full_reg[1]_0\ => \my_full_reg[1]\,
      phy_if_empty_r_reg => phy_if_empty_r_reg,
      phy_rddata_en => phy_rddata_en,
      \rd_ptr_timing_reg[1]_0\ => \my_full_reg[4]\,
      \wr_ptr[1]_i_2\ => \wr_ptr[1]_i_2\
    );
ififo_rst_reg: unisim.vcomponents.FDSE
    generic map(
      INIT => '1'
    )
        port map (
      C => \my_full_reg[4]\,
      CE => '1',
      D => ififo_rst_reg_0,
      Q => ififo_rst,
      S => phy_if_reset
    );
\in_fifo_gen.in_fifo\: unisim.vcomponents.IN_FIFO
    generic map(
      ALMOST_EMPTY_VALUE => 1,
      ALMOST_FULL_VALUE => 1,
      ARRAY_MODE => "ARRAY_MODE_4_X_8",
      SYNCHRONOUS_MODE => "FALSE"
    )
        port map (
      ALMOSTEMPTY => \in_fifo_gen.in_fifo_n_0\,
      ALMOSTFULL => \in_fifo_gen.in_fifo_n_1\,
      D0(3 downto 0) => B"0000",
      D1(3 downto 0) => if_d1(3 downto 0),
      D2(3 downto 0) => if_d2(3 downto 0),
      D3(3 downto 0) => if_d3(3 downto 0),
      D4(3 downto 0) => if_d4(3 downto 0),
      D5(7 downto 4) => \NLW_in_fifo_gen.in_fifo_D5_UNCONNECTED\(7 downto 4),
      D5(3 downto 0) => if_d5(3 downto 0),
      D6(7 downto 4) => \NLW_in_fifo_gen.in_fifo_D6_UNCONNECTED\(7 downto 4),
      D6(3 downto 0) => if_d6(3 downto 0),
      D7(3 downto 0) => if_d7(3 downto 0),
      D8(3 downto 0) => B"0000",
      D9(3 downto 0) => if_d9(3 downto 0),
      EMPTY => \if_empty_\,
      FULL => \in_fifo_gen.in_fifo_n_3\,
      Q0(7 downto 0) => rd_data(7 downto 0),
      Q1(7 downto 0) => rd_data(15 downto 8),
      Q2(7 downto 0) => rd_data(23 downto 16),
      Q3(7 downto 0) => rd_data(31 downto 24),
      Q4(7 downto 0) => rd_data(39 downto 32),
      Q5(7 downto 0) => rd_data(47 downto 40),
      Q6(7 downto 0) => rd_data(55 downto 48),
      Q7(7 downto 0) => rd_data(63 downto 56),
      Q8(7 downto 0) => rd_data(71 downto 64),
      Q9(7 downto 0) => rd_data(79 downto 72),
      RDCLK => \my_full_reg[4]\,
      RDEN => '1',
      RESET => ififo_rst,
      WRCLK => iserdes_clkdiv,
      WREN => ififo_wr_enable
    );
\of_pre_fifo_gen.u_ddr_of_pre_fifo\: entity work.\mig_mig_7series_v4_2_ddr_of_pre_fifo__parameterized1_40\
     port map (
      D0(7 downto 0) => of_d0(7 downto 0),
      D8(7) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_2\,
      D8(6) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_3\,
      D8(5) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_4\,
      D8(4) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_5\,
      D8(3) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_6\,
      D8(2) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_7\,
      D8(1) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_8\,
      D8(0) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_9\,
      Q(2 downto 0) => Q(2 downto 0),
      \my_empty_reg[1]_0\ => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_0\,
      \my_empty_reg[1]_1\ => \my_empty_reg[1]\,
      \my_empty_reg[7]_0\ => out_fifo_n_3,
      \my_full_reg[4]_0\ => \my_full_reg[4]\,
      ofifo_rst => ofifo_rst,
      out_fifo => out_fifo_0,
      out_fifo_0(7 downto 0) => out_fifo_1(7 downto 0),
      out_fifo_1 => out_fifo_2,
      phy_data_wr_en => phy_data_wr_en,
      phy_dout(71 downto 0) => phy_dout(71 downto 0),
      \rd_ptr_reg[3]_0\(63 downto 0) => \rd_ptr_reg[3]\(63 downto 0)
    );
ofifo_rst_reg: unisim.vcomponents.FDSE
    generic map(
      INIT => '1'
    )
        port map (
      C => \my_full_reg[4]\,
      CE => '1',
      D => ififo_rst_reg_0,
      Q => ofifo_rst,
      S => A_rst_primitives
    );
out_fifo: unisim.vcomponents.OUT_FIFO
    generic map(
      ALMOST_EMPTY_VALUE => 1,
      ALMOST_FULL_VALUE => 1,
      ARRAY_MODE => "ARRAY_MODE_8_X_4",
      OUTPUT_DISABLE => "FALSE",
      SYNCHRONOUS_MODE => "FALSE"
    )
        port map (
      ALMOSTEMPTY => out_fifo_n_0,
      ALMOSTFULL => out_fifo_n_1,
      D0(7 downto 0) => of_d0(7 downto 0),
      D1(7 downto 0) => \my_empty_reg[7]\(7 downto 0),
      D2(7 downto 0) => \my_empty_reg[7]_0\(7 downto 0),
      D3(7 downto 0) => \my_empty_reg[7]_1\(7 downto 0),
      D4(7 downto 0) => \my_empty_reg[7]_2\(7 downto 0),
      D5(7 downto 0) => \my_empty_reg[7]_3\(7 downto 0),
      D6(7 downto 0) => \my_empty_reg[7]_4\(7 downto 0),
      D7(7 downto 0) => \my_empty_reg[7]_5\(7 downto 0),
      D8(7) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_2\,
      D8(6) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_3\,
      D8(5) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_4\,
      D8(4) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_5\,
      D8(3) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_6\,
      D8(2) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_7\,
      D8(1) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_8\,
      D8(0) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_9\,
      D9(7 downto 0) => \my_empty_reg[7]_6\(7 downto 0),
      EMPTY => out_fifo_n_2,
      FULL => out_fifo_n_3,
      Q0(3 downto 0) => of_dqbus(3 downto 0),
      Q1(3 downto 0) => of_dqbus(7 downto 4),
      Q2(3 downto 0) => of_dqbus(11 downto 8),
      Q3(3 downto 0) => of_dqbus(15 downto 12),
      Q4(3 downto 0) => of_dqbus(19 downto 16),
      Q5(7 downto 4) => NLW_out_fifo_Q5_UNCONNECTED(7 downto 4),
      Q5(3 downto 0) => of_dqbus(23 downto 20),
      Q6(7 downto 4) => NLW_out_fifo_Q6_UNCONNECTED(7 downto 4),
      Q6(3 downto 0) => of_dqbus(27 downto 24),
      Q7(3 downto 0) => of_dqbus(31 downto 28),
      Q8(3 downto 0) => of_dqbus(35 downto 32),
      Q9(3 downto 0) => of_dqbus(39 downto 36),
      RDCLK => oserdes_clkdiv,
      RDEN => po_rd_enable,
      RESET => ofifo_rst,
      WRCLK => \my_full_reg[4]\,
      WREN => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_0\
    );
\phaser_in_gen.phaser_in\: unisim.vcomponents.PHASER_IN_PHY
    generic map(
      BURST_MODE => "TRUE",
      CLKOUT_DIV => 2,
      DQS_AUTO_RECAL => '1',
      DQS_BIAS_MODE => "FALSE",
      DQS_FIND_PATTERN => B"000",
      FINE_DELAY => 33,
      FREQ_REF_DIV => "DIV2",
      IS_RST_INVERTED => '0',
      MEMREFCLK_PERIOD => 2.500000,
      OUTPUT_CLK_SRC => "DELAYED_REF",
      PHASEREFCLK_PERIOD => 2.500000,
      REFCLK_PERIOD => 1.250000,
      SEL_CLK_OFFSET => 6,
      SYNC_IN_DIV_RST => "TRUE",
      WR_CYCLES => "FALSE"
    )
        port map (
      BURSTPENDINGPHY => phaser_ctl_bus(1),
      COUNTERLOADEN => \pi_dqs_found_lanes_r1_reg[0]\,
      COUNTERLOADVAL(5 downto 0) => COUNTERLOADVAL(5 downto 0),
      COUNTERREADEN => \pi_dqs_found_lanes_r1_reg[0]_0\,
      COUNTERREADVAL(5 downto 0) => COUNTERREADVAL(5 downto 0),
      DQSFOUND => in0(0),
      DQSOUTOFRANGE => \phaser_in_gen.phaser_in_n_1\,
      ENCALIBPHY(1 downto 0) => PCENABLECALIB(1 downto 0),
      FINEENABLE => \pi_dqs_found_lanes_r1_reg[0]_1\,
      FINEINC => \pi_dqs_found_lanes_r1_reg[0]_2\,
      FINEOVERFLOW => \phaser_in_gen.phaser_in_n_2\,
      FREQREFCLK => freq_refclk,
      ICLK => \^a_rst_primitives_reg\,
      ICLKDIV => iserdes_clkdiv,
      ISERDESRST => \phaser_in_gen.phaser_in_n_5\,
      MEMREFCLK => mem_refclk,
      PHASELOCKED => A_rst_primitives_reg_0,
      PHASEREFCLK => mem_dqs_in(0),
      RANKSELPHY(1 downto 0) => phaser_ctl_bus(3 downto 2),
      RCLK => \phaser_in_gen.phaser_in_n_7\,
      RST => A_rst_primitives,
      RSTDQSFIND => ififo_rst_reg_0,
      SYNCIN => sync_pulse,
      SYSCLK => \my_full_reg[4]\,
      WRENABLE => ififo_wr_enable
    );
phaser_out: unisim.vcomponents.PHASER_OUT_PHY
    generic map(
      CLKOUT_DIV => 2,
      COARSE_BYPASS => "FALSE",
      COARSE_DELAY => 0,
      DATA_CTL_N => "TRUE",
      DATA_RD_CYCLES => "FALSE",
      FINE_DELAY => 60,
      IS_RST_INVERTED => '0',
      MEMREFCLK_PERIOD => 2.500000,
      OCLKDELAY_INV => "FALSE",
      OCLK_DELAY => 0,
      OUTPUT_CLK_SRC => "DELAYED_REF",
      PHASEREFCLK_PERIOD => 1.000000,
      PO => B"111",
      REFCLK_PERIOD => 1.250000,
      SYNC_IN_DIV_RST => "TRUE"
    )
        port map (
      BURSTPENDINGPHY => phaser_ctl_bus(0),
      COARSEENABLE => \po_counter_read_val_reg[8]\,
      COARSEINC => \po_counter_read_val_reg[8]\,
      COARSEOVERFLOW => phaser_out_n_0,
      COUNTERLOADEN => '0',
      COUNTERLOADVAL(8 downto 0) => B"000000000",
      COUNTERREADEN => \pi_dqs_found_lanes_r1_reg[0]_0\,
      COUNTERREADVAL(8 downto 0) => A_rst_primitives_reg_1(8 downto 0),
      CTSBUS(1 downto 0) => oserdes_dqs_ts(1 downto 0),
      DQSBUS(1 downto 0) => oserdes_dqs(1 downto 0),
      DTSBUS(1 downto 0) => oserdes_dq_ts(1 downto 0),
      ENCALIBPHY(1 downto 0) => PCENABLECALIB(1 downto 0),
      FINEENABLE => \po_counter_read_val_reg[8]_0\,
      FINEINC => \po_counter_read_val_reg[8]_1\,
      FINEOVERFLOW => phaser_out_n_1,
      FREQREFCLK => freq_refclk,
      MEMREFCLK => mem_refclk,
      OCLK => oserdes_clk,
      OCLKDELAYED => oserdes_clk_delayed,
      OCLKDIV => oserdes_clkdiv,
      OSERDESRST => po_oserdes_rst,
      PHASEREFCLK => NLW_phaser_out_PHASEREFCLK_UNCONNECTED,
      RDENABLE => po_rd_enable,
      RST => A_rst_primitives,
      SELFINEOCLKDELAY => '0',
      SYNCIN => sync_pulse,
      SYSCLK => \my_full_reg[4]\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \mig_mig_7series_v4_2_ddr_byte_lane__parameterized0\ is
  port (
    out_dqs_1 : out STD_LOGIC;
    ts_dqs_1 : out STD_LOGIC;
    A_rst_primitives_reg : out STD_LOGIC;
    mem_dq_out : out STD_LOGIC_VECTOR ( 8 downto 0 );
    mem_dq_ts : out STD_LOGIC_VECTOR ( 8 downto 0 );
    in0 : out STD_LOGIC_VECTOR ( 0 to 0 );
    A_rst_primitives_reg_0 : out STD_LOGIC;
    B_rclk : out STD_LOGIC;
    if_empty_r : out STD_LOGIC_VECTOR ( 0 to 0 );
    \my_empty_reg[4]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    idelay_ld_rst_4 : out STD_LOGIC;
    \my_empty_reg[1]\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[0]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_0\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[0]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[0]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_0\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[0]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[0]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_0\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[0]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[0]_5\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_0\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[0]_6\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_0\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[0]_7\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_0\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[0]_8\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_0\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[0]_9\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_0\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[0]_10\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_0\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[0]_11\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_0\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[0]_12\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_0\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[0]_13\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_0\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[0]_14\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_0\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[0]_15\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_0\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[0]_16\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_0\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[0]_17\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_0\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[0]_18\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_0\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[0]_19\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_0\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[0]_20\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_0\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[0]_21\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_0\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[0]_22\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_0\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[0]_23\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_0\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[0]_24\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_0\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[0]_25\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_0\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[0]_26\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_0\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[0]_27\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_0\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[0]_28\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_0\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[0]_29\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_0\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[0]_30\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_0\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[0]_31\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_0\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[0]_32\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_0\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[0]_33\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_0\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[0]_34\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_0\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[0]_35\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_0\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[0]_36\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_0\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[0]_37\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_0\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[0]_38\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_0\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[0]_39\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_0\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[0]_40\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_0\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[0]_41\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_0\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[0]_42\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_0\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[0]_43\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_0\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[0]_44\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_0\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[0]_45\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_0\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[0]_46\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_0\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[0]_47\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_0\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[0]_48\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_0\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[0]_49\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_0\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[0]_50\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_0\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[0]_51\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_0\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[0]_52\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_0\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[0]_53\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_0\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[0]_54\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_0\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[0]_55\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_0\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[0]_56\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_0\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[0]_57\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_0\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[0]_58\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_0\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[0]_59\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_0\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[0]_60\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_0\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[0]_61\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_0\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[0]_62\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0\ : out STD_LOGIC;
    \rd_ptr_reg[3]\ : out STD_LOGIC_VECTOR ( 63 downto 0 );
    D : out STD_LOGIC_VECTOR ( 5 downto 0 );
    \calib_sel_reg[1]\ : out STD_LOGIC_VECTOR ( 8 downto 0 );
    Q : out STD_LOGIC_VECTOR ( 2 downto 0 );
    \entry_cnt_reg[4]\ : in STD_LOGIC;
    \input_[9].iserdes_dq_.iserdesdq\ : in STD_LOGIC;
    mem_dq_in : in STD_LOGIC_VECTOR ( 7 downto 0 );
    idelay_inc : in STD_LOGIC;
    LD0_11 : in STD_LOGIC;
    A_rst_primitives : in STD_LOGIC;
    CLKB0_11 : in STD_LOGIC;
    phaser_ctl_bus : in STD_LOGIC_VECTOR ( 3 downto 0 );
    \pi_dqs_found_lanes_r1_reg[9]\ : in STD_LOGIC;
    \pi_dqs_found_lanes_r1_reg[9]_0\ : in STD_LOGIC;
    \pi_dqs_found_lanes_r1_reg[9]_1\ : in STD_LOGIC;
    \pi_dqs_found_lanes_r1_reg[9]_2\ : in STD_LOGIC;
    freq_refclk : in STD_LOGIC;
    mem_refclk : in STD_LOGIC;
    mem_dqs_in : in STD_LOGIC_VECTOR ( 0 to 0 );
    ififo_rst_reg_0 : in STD_LOGIC;
    sync_pulse : in STD_LOGIC;
    PCENABLECALIB : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \pi_dqs_found_lanes_r1_reg[9]_3\ : in STD_LOGIC_VECTOR ( 5 downto 0 );
    \po_counter_read_val_reg[8]\ : in STD_LOGIC;
    \po_counter_read_val_reg[8]_0\ : in STD_LOGIC;
    \po_counter_read_val_reg[8]_1\ : in STD_LOGIC;
    \my_empty_reg[7]\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \my_empty_reg[7]_0\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \my_empty_reg[7]_1\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \my_empty_reg[7]_2\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \my_empty_reg[7]_3\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \my_empty_reg[7]_4\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \my_empty_reg[7]_5\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \my_empty_reg[7]_6\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    phy_if_reset : in STD_LOGIC;
    \my_full_reg[1]\ : in STD_LOGIC;
    phy_data_wr_en : in STD_LOGIC;
    rst_r4 : in STD_LOGIC;
    \gen_mux_rd[0].mux_rd_rise0_r_reg[0]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \gen_mux_rd[0].mux_rd_rise0_r_reg[0]_0\ : in STD_LOGIC;
    \gen_mux_rd[0].mux_rd_rise0_r_reg[0]_1\ : in STD_LOGIC;
    \gen_mux_rd[0].mux_rd_rise0_r_reg[0]_2\ : in STD_LOGIC;
    \gen_mux_rd[1].mux_rd_rise0_r_reg[1]\ : in STD_LOGIC;
    \gen_mux_rd[1].mux_rd_rise0_r_reg[1]_0\ : in STD_LOGIC;
    \gen_mux_rd[1].mux_rd_rise0_r_reg[1]_1\ : in STD_LOGIC;
    \gen_mux_rd[2].mux_rd_rise0_r_reg[2]\ : in STD_LOGIC;
    \gen_mux_rd[2].mux_rd_rise0_r_reg[2]_0\ : in STD_LOGIC;
    \gen_mux_rd[2].mux_rd_rise0_r_reg[2]_1\ : in STD_LOGIC;
    \gen_mux_rd[3].mux_rd_rise0_r_reg[3]\ : in STD_LOGIC;
    \gen_mux_rd[3].mux_rd_rise0_r_reg[3]_0\ : in STD_LOGIC;
    \gen_mux_rd[3].mux_rd_rise0_r_reg[3]_1\ : in STD_LOGIC;
    \gen_mux_rd[4].mux_rd_rise0_r_reg[4]\ : in STD_LOGIC;
    \gen_mux_rd[4].mux_rd_rise0_r_reg[4]_0\ : in STD_LOGIC;
    \gen_mux_rd[4].mux_rd_rise0_r_reg[4]_1\ : in STD_LOGIC;
    \gen_mux_rd[5].mux_rd_rise0_r_reg[5]\ : in STD_LOGIC;
    \gen_mux_rd[5].mux_rd_rise0_r_reg[5]_0\ : in STD_LOGIC;
    \gen_mux_rd[5].mux_rd_rise0_r_reg[5]_1\ : in STD_LOGIC;
    \gen_mux_rd[6].mux_rd_rise0_r_reg[6]\ : in STD_LOGIC;
    \gen_mux_rd[6].mux_rd_rise0_r_reg[6]_0\ : in STD_LOGIC;
    \gen_mux_rd[6].mux_rd_rise0_r_reg[6]_1\ : in STD_LOGIC;
    \gen_mux_rd[7].mux_rd_rise0_r_reg[7]\ : in STD_LOGIC;
    \gen_mux_rd[7].mux_rd_rise0_r_reg[7]_0\ : in STD_LOGIC;
    \gen_mux_rd[7].mux_rd_rise0_r_reg[7]_1\ : in STD_LOGIC;
    \gen_mux_rd[0].mux_rd_fall0_r_reg[0]\ : in STD_LOGIC;
    \gen_mux_rd[0].mux_rd_fall0_r_reg[0]_0\ : in STD_LOGIC;
    \gen_mux_rd[0].mux_rd_fall0_r_reg[0]_1\ : in STD_LOGIC;
    \gen_mux_rd[1].mux_rd_fall0_r_reg[1]\ : in STD_LOGIC;
    \gen_mux_rd[1].mux_rd_fall0_r_reg[1]_0\ : in STD_LOGIC;
    \gen_mux_rd[1].mux_rd_fall0_r_reg[1]_1\ : in STD_LOGIC;
    \gen_mux_rd[2].mux_rd_fall0_r_reg[2]\ : in STD_LOGIC;
    \gen_mux_rd[2].mux_rd_fall0_r_reg[2]_0\ : in STD_LOGIC;
    \gen_mux_rd[2].mux_rd_fall0_r_reg[2]_1\ : in STD_LOGIC;
    \gen_mux_rd[3].mux_rd_fall0_r_reg[3]\ : in STD_LOGIC;
    \gen_mux_rd[3].mux_rd_fall0_r_reg[3]_0\ : in STD_LOGIC;
    \gen_mux_rd[3].mux_rd_fall0_r_reg[3]_1\ : in STD_LOGIC;
    \gen_mux_rd[4].mux_rd_fall0_r_reg[4]\ : in STD_LOGIC;
    \gen_mux_rd[4].mux_rd_fall0_r_reg[4]_0\ : in STD_LOGIC;
    \gen_mux_rd[4].mux_rd_fall0_r_reg[4]_1\ : in STD_LOGIC;
    \gen_mux_rd[5].mux_rd_fall0_r_reg[5]\ : in STD_LOGIC;
    \gen_mux_rd[5].mux_rd_fall0_r_reg[5]_0\ : in STD_LOGIC;
    \gen_mux_rd[5].mux_rd_fall0_r_reg[5]_1\ : in STD_LOGIC;
    \gen_mux_rd[6].mux_rd_fall0_r_reg[6]\ : in STD_LOGIC;
    \gen_mux_rd[6].mux_rd_fall0_r_reg[6]_0\ : in STD_LOGIC;
    \gen_mux_rd[6].mux_rd_fall0_r_reg[6]_1\ : in STD_LOGIC;
    \gen_mux_rd[7].mux_rd_fall0_r_reg[7]\ : in STD_LOGIC;
    \gen_mux_rd[7].mux_rd_fall0_r_reg[7]_0\ : in STD_LOGIC;
    \gen_mux_rd[7].mux_rd_fall0_r_reg[7]_1\ : in STD_LOGIC;
    \gen_mux_rd[0].mux_rd_rise1_r_reg[0]\ : in STD_LOGIC;
    \gen_mux_rd[0].mux_rd_rise1_r_reg[0]_0\ : in STD_LOGIC;
    \gen_mux_rd[0].mux_rd_rise1_r_reg[0]_1\ : in STD_LOGIC;
    \gen_mux_rd[1].mux_rd_rise1_r_reg[1]\ : in STD_LOGIC;
    \gen_mux_rd[1].mux_rd_rise1_r_reg[1]_0\ : in STD_LOGIC;
    \gen_mux_rd[1].mux_rd_rise1_r_reg[1]_1\ : in STD_LOGIC;
    \gen_mux_rd[2].mux_rd_rise1_r_reg[2]\ : in STD_LOGIC;
    \gen_mux_rd[2].mux_rd_rise1_r_reg[2]_0\ : in STD_LOGIC;
    \gen_mux_rd[2].mux_rd_rise1_r_reg[2]_1\ : in STD_LOGIC;
    \gen_mux_rd[3].mux_rd_rise1_r_reg[3]\ : in STD_LOGIC;
    \gen_mux_rd[3].mux_rd_rise1_r_reg[3]_0\ : in STD_LOGIC;
    \gen_mux_rd[3].mux_rd_rise1_r_reg[3]_1\ : in STD_LOGIC;
    \gen_mux_rd[4].mux_rd_rise1_r_reg[4]\ : in STD_LOGIC;
    \gen_mux_rd[4].mux_rd_rise1_r_reg[4]_0\ : in STD_LOGIC;
    \gen_mux_rd[4].mux_rd_rise1_r_reg[4]_1\ : in STD_LOGIC;
    \gen_mux_rd[5].mux_rd_rise1_r_reg[5]\ : in STD_LOGIC;
    \gen_mux_rd[5].mux_rd_rise1_r_reg[5]_0\ : in STD_LOGIC;
    \gen_mux_rd[5].mux_rd_rise1_r_reg[5]_1\ : in STD_LOGIC;
    \gen_mux_rd[6].mux_rd_rise1_r_reg[6]\ : in STD_LOGIC;
    \gen_mux_rd[6].mux_rd_rise1_r_reg[6]_0\ : in STD_LOGIC;
    \gen_mux_rd[6].mux_rd_rise1_r_reg[6]_1\ : in STD_LOGIC;
    \gen_mux_rd[7].mux_rd_rise1_r_reg[7]\ : in STD_LOGIC;
    \gen_mux_rd[7].mux_rd_rise1_r_reg[7]_0\ : in STD_LOGIC;
    \gen_mux_rd[7].mux_rd_rise1_r_reg[7]_1\ : in STD_LOGIC;
    \gen_mux_rd[0].mux_rd_fall1_r_reg[0]\ : in STD_LOGIC;
    \gen_mux_rd[0].mux_rd_fall1_r_reg[0]_0\ : in STD_LOGIC;
    \gen_mux_rd[0].mux_rd_fall1_r_reg[0]_1\ : in STD_LOGIC;
    \gen_mux_rd[1].mux_rd_fall1_r_reg[1]\ : in STD_LOGIC;
    \gen_mux_rd[1].mux_rd_fall1_r_reg[1]_0\ : in STD_LOGIC;
    \gen_mux_rd[1].mux_rd_fall1_r_reg[1]_1\ : in STD_LOGIC;
    \gen_mux_rd[2].mux_rd_fall1_r_reg[2]\ : in STD_LOGIC;
    \gen_mux_rd[2].mux_rd_fall1_r_reg[2]_0\ : in STD_LOGIC;
    \gen_mux_rd[2].mux_rd_fall1_r_reg[2]_1\ : in STD_LOGIC;
    \gen_mux_rd[3].mux_rd_fall1_r_reg[3]\ : in STD_LOGIC;
    \gen_mux_rd[3].mux_rd_fall1_r_reg[3]_0\ : in STD_LOGIC;
    \gen_mux_rd[3].mux_rd_fall1_r_reg[3]_1\ : in STD_LOGIC;
    \gen_mux_rd[4].mux_rd_fall1_r_reg[4]\ : in STD_LOGIC;
    \gen_mux_rd[4].mux_rd_fall1_r_reg[4]_0\ : in STD_LOGIC;
    \gen_mux_rd[4].mux_rd_fall1_r_reg[4]_1\ : in STD_LOGIC;
    \gen_mux_rd[5].mux_rd_fall1_r_reg[5]\ : in STD_LOGIC;
    \gen_mux_rd[5].mux_rd_fall1_r_reg[5]_0\ : in STD_LOGIC;
    \gen_mux_rd[5].mux_rd_fall1_r_reg[5]_1\ : in STD_LOGIC;
    \gen_mux_rd[6].mux_rd_fall1_r_reg[6]\ : in STD_LOGIC;
    \gen_mux_rd[6].mux_rd_fall1_r_reg[6]_0\ : in STD_LOGIC;
    \gen_mux_rd[6].mux_rd_fall1_r_reg[6]_1\ : in STD_LOGIC;
    \gen_mux_rd[7].mux_rd_fall1_r_reg[7]\ : in STD_LOGIC;
    \gen_mux_rd[7].mux_rd_fall1_r_reg[7]_0\ : in STD_LOGIC;
    \gen_mux_rd[7].mux_rd_fall1_r_reg[7]_1\ : in STD_LOGIC;
    \gen_mux_rd[0].mux_rd_rise2_r_reg[0]\ : in STD_LOGIC;
    \gen_mux_rd[0].mux_rd_rise2_r_reg[0]_0\ : in STD_LOGIC;
    \gen_mux_rd[0].mux_rd_rise2_r_reg[0]_1\ : in STD_LOGIC;
    \gen_mux_rd[1].mux_rd_rise2_r_reg[1]\ : in STD_LOGIC;
    \gen_mux_rd[1].mux_rd_rise2_r_reg[1]_0\ : in STD_LOGIC;
    \gen_mux_rd[1].mux_rd_rise2_r_reg[1]_1\ : in STD_LOGIC;
    \gen_mux_rd[2].mux_rd_rise2_r_reg[2]\ : in STD_LOGIC;
    \gen_mux_rd[2].mux_rd_rise2_r_reg[2]_0\ : in STD_LOGIC;
    \gen_mux_rd[2].mux_rd_rise2_r_reg[2]_1\ : in STD_LOGIC;
    \gen_mux_rd[3].mux_rd_rise2_r_reg[3]\ : in STD_LOGIC;
    \gen_mux_rd[3].mux_rd_rise2_r_reg[3]_0\ : in STD_LOGIC;
    \gen_mux_rd[3].mux_rd_rise2_r_reg[3]_1\ : in STD_LOGIC;
    \gen_mux_rd[4].mux_rd_rise2_r_reg[4]\ : in STD_LOGIC;
    \gen_mux_rd[4].mux_rd_rise2_r_reg[4]_0\ : in STD_LOGIC;
    \gen_mux_rd[4].mux_rd_rise2_r_reg[4]_1\ : in STD_LOGIC;
    \gen_mux_rd[5].mux_rd_rise2_r_reg[5]\ : in STD_LOGIC;
    \gen_mux_rd[5].mux_rd_rise2_r_reg[5]_0\ : in STD_LOGIC;
    \gen_mux_rd[5].mux_rd_rise2_r_reg[5]_1\ : in STD_LOGIC;
    \gen_mux_rd[6].mux_rd_rise2_r_reg[6]\ : in STD_LOGIC;
    \gen_mux_rd[6].mux_rd_rise2_r_reg[6]_0\ : in STD_LOGIC;
    \gen_mux_rd[6].mux_rd_rise2_r_reg[6]_1\ : in STD_LOGIC;
    \gen_mux_rd[7].mux_rd_rise2_r_reg[7]\ : in STD_LOGIC;
    \gen_mux_rd[7].mux_rd_rise2_r_reg[7]_0\ : in STD_LOGIC;
    \gen_mux_rd[7].mux_rd_rise2_r_reg[7]_1\ : in STD_LOGIC;
    \gen_mux_rd[0].mux_rd_fall2_r_reg[0]\ : in STD_LOGIC;
    \gen_mux_rd[0].mux_rd_fall2_r_reg[0]_0\ : in STD_LOGIC;
    \gen_mux_rd[0].mux_rd_fall2_r_reg[0]_1\ : in STD_LOGIC;
    \gen_mux_rd[1].mux_rd_fall2_r_reg[1]\ : in STD_LOGIC;
    \gen_mux_rd[1].mux_rd_fall2_r_reg[1]_0\ : in STD_LOGIC;
    \gen_mux_rd[1].mux_rd_fall2_r_reg[1]_1\ : in STD_LOGIC;
    \gen_mux_rd[2].mux_rd_fall2_r_reg[2]\ : in STD_LOGIC;
    \gen_mux_rd[2].mux_rd_fall2_r_reg[2]_0\ : in STD_LOGIC;
    \gen_mux_rd[2].mux_rd_fall2_r_reg[2]_1\ : in STD_LOGIC;
    \gen_mux_rd[3].mux_rd_fall2_r_reg[3]\ : in STD_LOGIC;
    \gen_mux_rd[3].mux_rd_fall2_r_reg[3]_0\ : in STD_LOGIC;
    \gen_mux_rd[3].mux_rd_fall2_r_reg[3]_1\ : in STD_LOGIC;
    \gen_mux_rd[4].mux_rd_fall2_r_reg[4]\ : in STD_LOGIC;
    \gen_mux_rd[4].mux_rd_fall2_r_reg[4]_0\ : in STD_LOGIC;
    \gen_mux_rd[4].mux_rd_fall2_r_reg[4]_1\ : in STD_LOGIC;
    \gen_mux_rd[5].mux_rd_fall2_r_reg[5]\ : in STD_LOGIC;
    \gen_mux_rd[5].mux_rd_fall2_r_reg[5]_0\ : in STD_LOGIC;
    \gen_mux_rd[5].mux_rd_fall2_r_reg[5]_1\ : in STD_LOGIC;
    \gen_mux_rd[6].mux_rd_fall2_r_reg[6]\ : in STD_LOGIC;
    \gen_mux_rd[6].mux_rd_fall2_r_reg[6]_0\ : in STD_LOGIC;
    \gen_mux_rd[6].mux_rd_fall2_r_reg[6]_1\ : in STD_LOGIC;
    \gen_mux_rd[7].mux_rd_fall2_r_reg[7]\ : in STD_LOGIC;
    \gen_mux_rd[7].mux_rd_fall2_r_reg[7]_0\ : in STD_LOGIC;
    \gen_mux_rd[7].mux_rd_fall2_r_reg[7]_1\ : in STD_LOGIC;
    \gen_mux_rd[0].mux_rd_rise3_r_reg[0]\ : in STD_LOGIC;
    \gen_mux_rd[0].mux_rd_rise3_r_reg[0]_0\ : in STD_LOGIC;
    \gen_mux_rd[0].mux_rd_rise3_r_reg[0]_1\ : in STD_LOGIC;
    \gen_mux_rd[1].mux_rd_rise3_r_reg[1]\ : in STD_LOGIC;
    \gen_mux_rd[1].mux_rd_rise3_r_reg[1]_0\ : in STD_LOGIC;
    \gen_mux_rd[1].mux_rd_rise3_r_reg[1]_1\ : in STD_LOGIC;
    \gen_mux_rd[2].mux_rd_rise3_r_reg[2]\ : in STD_LOGIC;
    \gen_mux_rd[2].mux_rd_rise3_r_reg[2]_0\ : in STD_LOGIC;
    \gen_mux_rd[2].mux_rd_rise3_r_reg[2]_1\ : in STD_LOGIC;
    \gen_mux_rd[3].mux_rd_rise3_r_reg[3]\ : in STD_LOGIC;
    \gen_mux_rd[3].mux_rd_rise3_r_reg[3]_0\ : in STD_LOGIC;
    \gen_mux_rd[3].mux_rd_rise3_r_reg[3]_1\ : in STD_LOGIC;
    \gen_mux_rd[4].mux_rd_rise3_r_reg[4]\ : in STD_LOGIC;
    \gen_mux_rd[4].mux_rd_rise3_r_reg[4]_0\ : in STD_LOGIC;
    \gen_mux_rd[4].mux_rd_rise3_r_reg[4]_1\ : in STD_LOGIC;
    \gen_mux_rd[5].mux_rd_rise3_r_reg[5]\ : in STD_LOGIC;
    \gen_mux_rd[5].mux_rd_rise3_r_reg[5]_0\ : in STD_LOGIC;
    \gen_mux_rd[5].mux_rd_rise3_r_reg[5]_1\ : in STD_LOGIC;
    \gen_mux_rd[6].mux_rd_rise3_r_reg[6]\ : in STD_LOGIC;
    \gen_mux_rd[6].mux_rd_rise3_r_reg[6]_0\ : in STD_LOGIC;
    \gen_mux_rd[6].mux_rd_rise3_r_reg[6]_1\ : in STD_LOGIC;
    \gen_mux_rd[7].mux_rd_rise3_r_reg[7]\ : in STD_LOGIC;
    \gen_mux_rd[7].mux_rd_rise3_r_reg[7]_0\ : in STD_LOGIC;
    \gen_mux_rd[7].mux_rd_rise3_r_reg[7]_1\ : in STD_LOGIC;
    \gen_mux_rd[0].mux_rd_fall3_r_reg[0]\ : in STD_LOGIC;
    \gen_mux_rd[0].mux_rd_fall3_r_reg[0]_0\ : in STD_LOGIC;
    \gen_mux_rd[0].mux_rd_fall3_r_reg[0]_1\ : in STD_LOGIC;
    \gen_mux_rd[1].mux_rd_fall3_r_reg[1]\ : in STD_LOGIC;
    \gen_mux_rd[1].mux_rd_fall3_r_reg[1]_0\ : in STD_LOGIC;
    \gen_mux_rd[1].mux_rd_fall3_r_reg[1]_1\ : in STD_LOGIC;
    \gen_mux_rd[2].mux_rd_fall3_r_reg[2]\ : in STD_LOGIC;
    \gen_mux_rd[2].mux_rd_fall3_r_reg[2]_0\ : in STD_LOGIC;
    \gen_mux_rd[2].mux_rd_fall3_r_reg[2]_1\ : in STD_LOGIC;
    \gen_mux_rd[3].mux_rd_fall3_r_reg[3]\ : in STD_LOGIC;
    \gen_mux_rd[3].mux_rd_fall3_r_reg[3]_0\ : in STD_LOGIC;
    \gen_mux_rd[3].mux_rd_fall3_r_reg[3]_1\ : in STD_LOGIC;
    \gen_mux_rd[4].mux_rd_fall3_r_reg[4]\ : in STD_LOGIC;
    \gen_mux_rd[4].mux_rd_fall3_r_reg[4]_0\ : in STD_LOGIC;
    \gen_mux_rd[4].mux_rd_fall3_r_reg[4]_1\ : in STD_LOGIC;
    \gen_mux_rd[5].mux_rd_fall3_r_reg[5]\ : in STD_LOGIC;
    \gen_mux_rd[5].mux_rd_fall3_r_reg[5]_0\ : in STD_LOGIC;
    \gen_mux_rd[5].mux_rd_fall3_r_reg[5]_1\ : in STD_LOGIC;
    \gen_mux_rd[6].mux_rd_fall3_r_reg[6]\ : in STD_LOGIC;
    \gen_mux_rd[6].mux_rd_fall3_r_reg[6]_0\ : in STD_LOGIC;
    \gen_mux_rd[6].mux_rd_fall3_r_reg[6]_1\ : in STD_LOGIC;
    \gen_mux_rd[7].mux_rd_fall3_r_reg[7]\ : in STD_LOGIC;
    \gen_mux_rd[7].mux_rd_fall3_r_reg[7]_0\ : in STD_LOGIC;
    \gen_mux_rd[7].mux_rd_fall3_r_reg[7]_1\ : in STD_LOGIC;
    out_fifo_0 : in STD_LOGIC;
    out_fifo_1 : in STD_LOGIC_VECTOR ( 7 downto 0 );
    out_fifo_2 : in STD_LOGIC;
    \out_fifo_i_75__1\ : in STD_LOGIC_VECTOR ( 71 downto 0 );
    COUNTERREADVAL : in STD_LOGIC_VECTOR ( 5 downto 0 );
    \pi_counter_read_val_reg[5]\ : in STD_LOGIC_VECTOR ( 5 downto 0 );
    calib_sel : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \pi_counter_read_val_reg[5]_0\ : in STD_LOGIC_VECTOR ( 5 downto 0 );
    \po_counter_read_val_reg[8]_2\ : in STD_LOGIC_VECTOR ( 8 downto 0 );
    \po_counter_read_val_reg[8]_3\ : in STD_LOGIC_VECTOR ( 8 downto 0 );
    \po_counter_read_val_reg[8]_4\ : in STD_LOGIC_VECTOR ( 8 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \mig_mig_7series_v4_2_ddr_byte_lane__parameterized0\ : entity is "mig_7series_v4_2_ddr_byte_lane";
end \mig_mig_7series_v4_2_ddr_byte_lane__parameterized0\;

architecture STRUCTURE of \mig_mig_7series_v4_2_ddr_byte_lane__parameterized0\ is
  signal \^a_rst_primitives_reg\ : STD_LOGIC;
  signal B_pi_counter_read_val : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal B_po_counter_read_val : STD_LOGIC_VECTOR ( 8 downto 0 );
  signal if_d2 : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal if_d3 : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal if_d4 : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal if_d5 : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal if_d6 : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal if_d7 : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal if_d8 : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal if_d9 : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \if_empty_\ : STD_LOGIC;
  signal \^if_empty_r\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal ififo_rst : STD_LOGIC;
  signal ififo_wr_enable : STD_LOGIC;
  signal \in_fifo_gen.in_fifo_n_0\ : STD_LOGIC;
  signal \in_fifo_gen.in_fifo_n_1\ : STD_LOGIC;
  signal \in_fifo_gen.in_fifo_n_3\ : STD_LOGIC;
  signal iserdes_clkdiv : STD_LOGIC;
  signal of_d1 : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal of_dqbus : STD_LOGIC_VECTOR ( 39 downto 0 );
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_0\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_2\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_3\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_4\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_5\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_6\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_7\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_8\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_9\ : STD_LOGIC;
  signal ofifo_rst : STD_LOGIC;
  signal oserdes_clk : STD_LOGIC;
  signal oserdes_clk_delayed : STD_LOGIC;
  signal oserdes_clkdiv : STD_LOGIC;
  signal oserdes_dq_ts : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal oserdes_dqs : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal oserdes_dqs_ts : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal out_fifo_n_0 : STD_LOGIC;
  signal out_fifo_n_1 : STD_LOGIC;
  signal out_fifo_n_2 : STD_LOGIC;
  signal out_fifo_n_3 : STD_LOGIC;
  signal \phaser_in_gen.phaser_in_n_1\ : STD_LOGIC;
  signal \phaser_in_gen.phaser_in_n_2\ : STD_LOGIC;
  signal \phaser_in_gen.phaser_in_n_5\ : STD_LOGIC;
  signal phaser_out_n_0 : STD_LOGIC;
  signal phaser_out_n_1 : STD_LOGIC;
  signal po_oserdes_rst : STD_LOGIC;
  signal po_rd_enable : STD_LOGIC;
  signal rd_data : STD_LOGIC_VECTOR ( 79 downto 0 );
  signal rd_data_r : STD_LOGIC_VECTOR ( 79 downto 12 );
  signal \NLW_in_fifo_gen.in_fifo_D5_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 4 );
  signal \NLW_in_fifo_gen.in_fifo_D6_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 4 );
  signal NLW_out_fifo_Q5_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 4 );
  signal NLW_out_fifo_Q6_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 4 );
  signal NLW_phaser_out_PHASEREFCLK_UNCONNECTED : STD_LOGIC;
  attribute syn_maxfan : string;
  attribute syn_maxfan of \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]\ : label is "3";
  attribute BOX_TYPE : string;
  attribute BOX_TYPE of \in_fifo_gen.in_fifo\ : label is "PRIMITIVE";
  attribute BOX_TYPE of out_fifo : label is "PRIMITIVE";
  attribute BOX_TYPE of \phaser_in_gen.phaser_in\ : label is "PRIMITIVE";
  attribute BOX_TYPE of phaser_out : label is "PRIMITIVE";
begin
  A_rst_primitives_reg <= \^a_rst_primitives_reg\;
  if_empty_r(0) <= \^if_empty_r\(0);
ddr_byte_group_io: entity work.\mig_mig_7series_v4_2_ddr_byte_group_io__parameterized0_17\
     port map (
      A_rst_primitives => A_rst_primitives,
      CLKB0_11 => CLKB0_11,
      CTSBUS(0) => oserdes_dqs_ts(0),
      D2(3 downto 0) => if_d2(3 downto 0),
      D3(3 downto 0) => if_d3(3 downto 0),
      D4(3 downto 0) => if_d4(3 downto 0),
      D5(3 downto 0) => if_d5(3 downto 0),
      D6(3 downto 0) => if_d6(3 downto 0),
      D7(3 downto 0) => if_d7(3 downto 0),
      D8(3 downto 0) => if_d8(3 downto 0),
      D9(3 downto 0) => if_d9(3 downto 0),
      DQSBUS(1 downto 0) => oserdes_dqs(1 downto 0),
      DTSBUS(1 downto 0) => oserdes_dq_ts(1 downto 0),
      LD0_11 => LD0_11,
      \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]\ => \^a_rst_primitives_reg\,
      idelay_inc => idelay_inc,
      idelay_ld_rst_4 => idelay_ld_rst_4,
      idelay_ld_rst_reg_0 => \entry_cnt_reg[4]\,
      \input_[9].iserdes_dq_.iserdesdq_0\ => \input_[9].iserdes_dq_.iserdesdq\,
      iserdes_clkdiv => iserdes_clkdiv,
      mem_dq_in(7 downto 0) => mem_dq_in(7 downto 0),
      mem_dq_out(8 downto 0) => mem_dq_out(8 downto 0),
      mem_dq_ts(8 downto 0) => mem_dq_ts(8 downto 0),
      of_dqbus(35 downto 0) => of_dqbus(39 downto 4),
      oserdes_clk => oserdes_clk,
      oserdes_clk_delayed => oserdes_clk_delayed,
      oserdes_clkdiv => oserdes_clkdiv,
      out_dqs_1 => out_dqs_1,
      po_oserdes_rst => po_oserdes_rst,
      rst_r4 => rst_r4,
      ts_dqs_1 => ts_dqs_1
    );
\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => \if_empty_\,
      Q => \^if_empty_r\(0),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => rd_data(12),
      Q => rd_data_r(12),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => rd_data(13),
      Q => rd_data_r(13),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => rd_data(14),
      Q => rd_data_r(14),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => rd_data(15),
      Q => rd_data_r(15),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => rd_data(16),
      Q => rd_data_r(16),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => rd_data(17),
      Q => rd_data_r(17),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => rd_data(18),
      Q => rd_data_r(18),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => rd_data(19),
      Q => rd_data_r(19),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => rd_data(20),
      Q => rd_data_r(20),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => rd_data(21),
      Q => rd_data_r(21),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => rd_data(22),
      Q => rd_data_r(22),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => rd_data(23),
      Q => rd_data_r(23),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => rd_data(24),
      Q => rd_data_r(24),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => rd_data(25),
      Q => rd_data_r(25),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => rd_data(26),
      Q => rd_data_r(26),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => rd_data(27),
      Q => rd_data_r(27),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => rd_data(28),
      Q => rd_data_r(28),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => rd_data(29),
      Q => rd_data_r(29),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => rd_data(30),
      Q => rd_data_r(30),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => rd_data(31),
      Q => rd_data_r(31),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => rd_data(32),
      Q => rd_data_r(32),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => rd_data(33),
      Q => rd_data_r(33),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => rd_data(34),
      Q => rd_data_r(34),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => rd_data(35),
      Q => rd_data_r(35),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => rd_data(36),
      Q => rd_data_r(36),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => rd_data(37),
      Q => rd_data_r(37),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => rd_data(38),
      Q => rd_data_r(38),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => rd_data(39),
      Q => rd_data_r(39),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => rd_data(40),
      Q => rd_data_r(40),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => rd_data(41),
      Q => rd_data_r(41),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => rd_data(42),
      Q => rd_data_r(42),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => rd_data(43),
      Q => rd_data_r(43),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => rd_data(44),
      Q => rd_data_r(44),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => rd_data(45),
      Q => rd_data_r(45),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => rd_data(46),
      Q => rd_data_r(46),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => rd_data(47),
      Q => rd_data_r(47),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => rd_data(48),
      Q => rd_data_r(48),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => rd_data(49),
      Q => rd_data_r(49),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => rd_data(50),
      Q => rd_data_r(50),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => rd_data(51),
      Q => rd_data_r(51),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => rd_data(52),
      Q => rd_data_r(52),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => rd_data(53),
      Q => rd_data_r(53),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => rd_data(54),
      Q => rd_data_r(54),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => rd_data(55),
      Q => rd_data_r(55),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => rd_data(56),
      Q => rd_data_r(56),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => rd_data(57),
      Q => rd_data_r(57),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => rd_data(58),
      Q => rd_data_r(58),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => rd_data(59),
      Q => rd_data_r(59),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => rd_data(60),
      Q => rd_data_r(60),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => rd_data(61),
      Q => rd_data_r(61),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => rd_data(62),
      Q => rd_data_r(62),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => rd_data(63),
      Q => rd_data_r(63),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => rd_data(64),
      Q => rd_data_r(64),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => rd_data(65),
      Q => rd_data_r(65),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => rd_data(66),
      Q => rd_data_r(66),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => rd_data(67),
      Q => rd_data_r(67),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => rd_data(68),
      Q => rd_data_r(68),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => rd_data(69),
      Q => rd_data_r(69),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => rd_data(70),
      Q => rd_data_r(70),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => rd_data(71),
      Q => rd_data_r(71),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => rd_data(72),
      Q => rd_data_r(72),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => rd_data(73),
      Q => rd_data_r(73),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => rd_data(74),
      Q => rd_data_r(74),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => rd_data(75),
      Q => rd_data_r(75),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => rd_data(76),
      Q => rd_data_r(76),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => rd_data(77),
      Q => rd_data_r(77),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => rd_data(78),
      Q => rd_data_r(78),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => rd_data(79),
      Q => rd_data_r(79),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo\: entity work.mig_mig_7series_v4_2_ddr_if_post_fifo_18
     port map (
      Q(67 downto 0) => rd_data_r(79 downto 12),
      \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]\ => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0\,
      \gen_mux_rd[0].mux_rd_fall0_r_reg[0]\ => \gen_mux_rd[0].mux_rd_fall0_r_reg[0]\,
      \gen_mux_rd[0].mux_rd_fall0_r_reg[0]_0\ => \gen_mux_rd[0].mux_rd_fall0_r_reg[0]_0\,
      \gen_mux_rd[0].mux_rd_fall0_r_reg[0]_1\ => \gen_mux_rd[0].mux_rd_fall0_r_reg[0]_1\,
      \gen_mux_rd[0].mux_rd_fall1_r_reg[0]\ => \gen_mux_rd[0].mux_rd_fall1_r_reg[0]\,
      \gen_mux_rd[0].mux_rd_fall1_r_reg[0]_0\ => \gen_mux_rd[0].mux_rd_fall1_r_reg[0]_0\,
      \gen_mux_rd[0].mux_rd_fall1_r_reg[0]_1\ => \gen_mux_rd[0].mux_rd_fall1_r_reg[0]_1\,
      \gen_mux_rd[0].mux_rd_fall2_r_reg[0]\ => \gen_mux_rd[0].mux_rd_fall2_r_reg[0]\,
      \gen_mux_rd[0].mux_rd_fall2_r_reg[0]_0\ => \gen_mux_rd[0].mux_rd_fall2_r_reg[0]_0\,
      \gen_mux_rd[0].mux_rd_fall2_r_reg[0]_1\ => \gen_mux_rd[0].mux_rd_fall2_r_reg[0]_1\,
      \gen_mux_rd[0].mux_rd_fall3_r_reg[0]\ => \gen_mux_rd[0].mux_rd_fall3_r_reg[0]\,
      \gen_mux_rd[0].mux_rd_fall3_r_reg[0]_0\ => \gen_mux_rd[0].mux_rd_fall3_r_reg[0]_0\,
      \gen_mux_rd[0].mux_rd_fall3_r_reg[0]_1\ => \gen_mux_rd[0].mux_rd_fall3_r_reg[0]_1\,
      \gen_mux_rd[0].mux_rd_rise0_r_reg[0]\(1 downto 0) => \gen_mux_rd[0].mux_rd_rise0_r_reg[0]\(1 downto 0),
      \gen_mux_rd[0].mux_rd_rise0_r_reg[0]_0\ => \gen_mux_rd[0].mux_rd_rise0_r_reg[0]_0\,
      \gen_mux_rd[0].mux_rd_rise0_r_reg[0]_1\ => \gen_mux_rd[0].mux_rd_rise0_r_reg[0]_1\,
      \gen_mux_rd[0].mux_rd_rise0_r_reg[0]_2\ => \gen_mux_rd[0].mux_rd_rise0_r_reg[0]_2\,
      \gen_mux_rd[0].mux_rd_rise1_r_reg[0]\ => \gen_mux_rd[0].mux_rd_rise1_r_reg[0]\,
      \gen_mux_rd[0].mux_rd_rise1_r_reg[0]_0\ => \gen_mux_rd[0].mux_rd_rise1_r_reg[0]_0\,
      \gen_mux_rd[0].mux_rd_rise1_r_reg[0]_1\ => \gen_mux_rd[0].mux_rd_rise1_r_reg[0]_1\,
      \gen_mux_rd[0].mux_rd_rise2_r_reg[0]\ => \gen_mux_rd[0].mux_rd_rise2_r_reg[0]\,
      \gen_mux_rd[0].mux_rd_rise2_r_reg[0]_0\ => \gen_mux_rd[0].mux_rd_rise2_r_reg[0]_0\,
      \gen_mux_rd[0].mux_rd_rise2_r_reg[0]_1\ => \gen_mux_rd[0].mux_rd_rise2_r_reg[0]_1\,
      \gen_mux_rd[0].mux_rd_rise3_r_reg[0]\ => \gen_mux_rd[0].mux_rd_rise3_r_reg[0]\,
      \gen_mux_rd[0].mux_rd_rise3_r_reg[0]_0\ => \gen_mux_rd[0].mux_rd_rise3_r_reg[0]_0\,
      \gen_mux_rd[0].mux_rd_rise3_r_reg[0]_1\ => \gen_mux_rd[0].mux_rd_rise3_r_reg[0]_1\,
      \gen_mux_rd[1].mux_rd_fall0_r_reg[1]\ => \gen_mux_rd[1].mux_rd_fall0_r_reg[1]\,
      \gen_mux_rd[1].mux_rd_fall0_r_reg[1]_0\ => \gen_mux_rd[1].mux_rd_fall0_r_reg[1]_0\,
      \gen_mux_rd[1].mux_rd_fall0_r_reg[1]_1\ => \gen_mux_rd[1].mux_rd_fall0_r_reg[1]_1\,
      \gen_mux_rd[1].mux_rd_fall1_r_reg[1]\ => \gen_mux_rd[1].mux_rd_fall1_r_reg[1]\,
      \gen_mux_rd[1].mux_rd_fall1_r_reg[1]_0\ => \gen_mux_rd[1].mux_rd_fall1_r_reg[1]_0\,
      \gen_mux_rd[1].mux_rd_fall1_r_reg[1]_1\ => \gen_mux_rd[1].mux_rd_fall1_r_reg[1]_1\,
      \gen_mux_rd[1].mux_rd_fall2_r_reg[1]\ => \gen_mux_rd[1].mux_rd_fall2_r_reg[1]\,
      \gen_mux_rd[1].mux_rd_fall2_r_reg[1]_0\ => \gen_mux_rd[1].mux_rd_fall2_r_reg[1]_0\,
      \gen_mux_rd[1].mux_rd_fall2_r_reg[1]_1\ => \gen_mux_rd[1].mux_rd_fall2_r_reg[1]_1\,
      \gen_mux_rd[1].mux_rd_fall3_r_reg[1]\ => \gen_mux_rd[1].mux_rd_fall3_r_reg[1]\,
      \gen_mux_rd[1].mux_rd_fall3_r_reg[1]_0\ => \gen_mux_rd[1].mux_rd_fall3_r_reg[1]_0\,
      \gen_mux_rd[1].mux_rd_fall3_r_reg[1]_1\ => \gen_mux_rd[1].mux_rd_fall3_r_reg[1]_1\,
      \gen_mux_rd[1].mux_rd_rise0_r_reg[1]\ => \gen_mux_rd[1].mux_rd_rise0_r_reg[1]\,
      \gen_mux_rd[1].mux_rd_rise0_r_reg[1]_0\ => \gen_mux_rd[1].mux_rd_rise0_r_reg[1]_0\,
      \gen_mux_rd[1].mux_rd_rise0_r_reg[1]_1\ => \gen_mux_rd[1].mux_rd_rise0_r_reg[1]_1\,
      \gen_mux_rd[1].mux_rd_rise1_r_reg[1]\ => \gen_mux_rd[1].mux_rd_rise1_r_reg[1]\,
      \gen_mux_rd[1].mux_rd_rise1_r_reg[1]_0\ => \gen_mux_rd[1].mux_rd_rise1_r_reg[1]_0\,
      \gen_mux_rd[1].mux_rd_rise1_r_reg[1]_1\ => \gen_mux_rd[1].mux_rd_rise1_r_reg[1]_1\,
      \gen_mux_rd[1].mux_rd_rise2_r_reg[1]\ => \gen_mux_rd[1].mux_rd_rise2_r_reg[1]\,
      \gen_mux_rd[1].mux_rd_rise2_r_reg[1]_0\ => \gen_mux_rd[1].mux_rd_rise2_r_reg[1]_0\,
      \gen_mux_rd[1].mux_rd_rise2_r_reg[1]_1\ => \gen_mux_rd[1].mux_rd_rise2_r_reg[1]_1\,
      \gen_mux_rd[1].mux_rd_rise3_r_reg[1]\ => \gen_mux_rd[1].mux_rd_rise3_r_reg[1]\,
      \gen_mux_rd[1].mux_rd_rise3_r_reg[1]_0\ => \gen_mux_rd[1].mux_rd_rise3_r_reg[1]_0\,
      \gen_mux_rd[1].mux_rd_rise3_r_reg[1]_1\ => \gen_mux_rd[1].mux_rd_rise3_r_reg[1]_1\,
      \gen_mux_rd[2].mux_rd_fall0_r_reg[2]\ => \gen_mux_rd[2].mux_rd_fall0_r_reg[2]\,
      \gen_mux_rd[2].mux_rd_fall0_r_reg[2]_0\ => \gen_mux_rd[2].mux_rd_fall0_r_reg[2]_0\,
      \gen_mux_rd[2].mux_rd_fall0_r_reg[2]_1\ => \gen_mux_rd[2].mux_rd_fall0_r_reg[2]_1\,
      \gen_mux_rd[2].mux_rd_fall1_r_reg[2]\ => \gen_mux_rd[2].mux_rd_fall1_r_reg[2]\,
      \gen_mux_rd[2].mux_rd_fall1_r_reg[2]_0\ => \gen_mux_rd[2].mux_rd_fall1_r_reg[2]_0\,
      \gen_mux_rd[2].mux_rd_fall1_r_reg[2]_1\ => \gen_mux_rd[2].mux_rd_fall1_r_reg[2]_1\,
      \gen_mux_rd[2].mux_rd_fall2_r_reg[2]\ => \gen_mux_rd[2].mux_rd_fall2_r_reg[2]\,
      \gen_mux_rd[2].mux_rd_fall2_r_reg[2]_0\ => \gen_mux_rd[2].mux_rd_fall2_r_reg[2]_0\,
      \gen_mux_rd[2].mux_rd_fall2_r_reg[2]_1\ => \gen_mux_rd[2].mux_rd_fall2_r_reg[2]_1\,
      \gen_mux_rd[2].mux_rd_fall3_r_reg[2]\ => \gen_mux_rd[2].mux_rd_fall3_r_reg[2]\,
      \gen_mux_rd[2].mux_rd_fall3_r_reg[2]_0\ => \gen_mux_rd[2].mux_rd_fall3_r_reg[2]_0\,
      \gen_mux_rd[2].mux_rd_fall3_r_reg[2]_1\ => \gen_mux_rd[2].mux_rd_fall3_r_reg[2]_1\,
      \gen_mux_rd[2].mux_rd_rise0_r_reg[2]\ => \gen_mux_rd[2].mux_rd_rise0_r_reg[2]\,
      \gen_mux_rd[2].mux_rd_rise0_r_reg[2]_0\ => \gen_mux_rd[2].mux_rd_rise0_r_reg[2]_0\,
      \gen_mux_rd[2].mux_rd_rise0_r_reg[2]_1\ => \gen_mux_rd[2].mux_rd_rise0_r_reg[2]_1\,
      \gen_mux_rd[2].mux_rd_rise1_r_reg[2]\ => \gen_mux_rd[2].mux_rd_rise1_r_reg[2]\,
      \gen_mux_rd[2].mux_rd_rise1_r_reg[2]_0\ => \gen_mux_rd[2].mux_rd_rise1_r_reg[2]_0\,
      \gen_mux_rd[2].mux_rd_rise1_r_reg[2]_1\ => \gen_mux_rd[2].mux_rd_rise1_r_reg[2]_1\,
      \gen_mux_rd[2].mux_rd_rise2_r_reg[2]\ => \gen_mux_rd[2].mux_rd_rise2_r_reg[2]\,
      \gen_mux_rd[2].mux_rd_rise2_r_reg[2]_0\ => \gen_mux_rd[2].mux_rd_rise2_r_reg[2]_0\,
      \gen_mux_rd[2].mux_rd_rise2_r_reg[2]_1\ => \gen_mux_rd[2].mux_rd_rise2_r_reg[2]_1\,
      \gen_mux_rd[2].mux_rd_rise3_r_reg[2]\ => \gen_mux_rd[2].mux_rd_rise3_r_reg[2]\,
      \gen_mux_rd[2].mux_rd_rise3_r_reg[2]_0\ => \gen_mux_rd[2].mux_rd_rise3_r_reg[2]_0\,
      \gen_mux_rd[2].mux_rd_rise3_r_reg[2]_1\ => \gen_mux_rd[2].mux_rd_rise3_r_reg[2]_1\,
      \gen_mux_rd[3].mux_rd_fall0_r_reg[3]\ => \gen_mux_rd[3].mux_rd_fall0_r_reg[3]\,
      \gen_mux_rd[3].mux_rd_fall0_r_reg[3]_0\ => \gen_mux_rd[3].mux_rd_fall0_r_reg[3]_0\,
      \gen_mux_rd[3].mux_rd_fall0_r_reg[3]_1\ => \gen_mux_rd[3].mux_rd_fall0_r_reg[3]_1\,
      \gen_mux_rd[3].mux_rd_fall1_r_reg[3]\ => \gen_mux_rd[3].mux_rd_fall1_r_reg[3]\,
      \gen_mux_rd[3].mux_rd_fall1_r_reg[3]_0\ => \gen_mux_rd[3].mux_rd_fall1_r_reg[3]_0\,
      \gen_mux_rd[3].mux_rd_fall1_r_reg[3]_1\ => \gen_mux_rd[3].mux_rd_fall1_r_reg[3]_1\,
      \gen_mux_rd[3].mux_rd_fall2_r_reg[3]\ => \gen_mux_rd[3].mux_rd_fall2_r_reg[3]\,
      \gen_mux_rd[3].mux_rd_fall2_r_reg[3]_0\ => \gen_mux_rd[3].mux_rd_fall2_r_reg[3]_0\,
      \gen_mux_rd[3].mux_rd_fall2_r_reg[3]_1\ => \gen_mux_rd[3].mux_rd_fall2_r_reg[3]_1\,
      \gen_mux_rd[3].mux_rd_fall3_r_reg[3]\ => \gen_mux_rd[3].mux_rd_fall3_r_reg[3]\,
      \gen_mux_rd[3].mux_rd_fall3_r_reg[3]_0\ => \gen_mux_rd[3].mux_rd_fall3_r_reg[3]_0\,
      \gen_mux_rd[3].mux_rd_fall3_r_reg[3]_1\ => \gen_mux_rd[3].mux_rd_fall3_r_reg[3]_1\,
      \gen_mux_rd[3].mux_rd_rise0_r_reg[3]\ => \gen_mux_rd[3].mux_rd_rise0_r_reg[3]\,
      \gen_mux_rd[3].mux_rd_rise0_r_reg[3]_0\ => \gen_mux_rd[3].mux_rd_rise0_r_reg[3]_0\,
      \gen_mux_rd[3].mux_rd_rise0_r_reg[3]_1\ => \gen_mux_rd[3].mux_rd_rise0_r_reg[3]_1\,
      \gen_mux_rd[3].mux_rd_rise1_r_reg[3]\ => \gen_mux_rd[3].mux_rd_rise1_r_reg[3]\,
      \gen_mux_rd[3].mux_rd_rise1_r_reg[3]_0\ => \gen_mux_rd[3].mux_rd_rise1_r_reg[3]_0\,
      \gen_mux_rd[3].mux_rd_rise1_r_reg[3]_1\ => \gen_mux_rd[3].mux_rd_rise1_r_reg[3]_1\,
      \gen_mux_rd[3].mux_rd_rise2_r_reg[3]\ => \gen_mux_rd[3].mux_rd_rise2_r_reg[3]\,
      \gen_mux_rd[3].mux_rd_rise2_r_reg[3]_0\ => \gen_mux_rd[3].mux_rd_rise2_r_reg[3]_0\,
      \gen_mux_rd[3].mux_rd_rise2_r_reg[3]_1\ => \gen_mux_rd[3].mux_rd_rise2_r_reg[3]_1\,
      \gen_mux_rd[3].mux_rd_rise3_r_reg[3]\ => \gen_mux_rd[3].mux_rd_rise3_r_reg[3]\,
      \gen_mux_rd[3].mux_rd_rise3_r_reg[3]_0\ => \gen_mux_rd[3].mux_rd_rise3_r_reg[3]_0\,
      \gen_mux_rd[3].mux_rd_rise3_r_reg[3]_1\ => \gen_mux_rd[3].mux_rd_rise3_r_reg[3]_1\,
      \gen_mux_rd[4].mux_rd_fall0_r_reg[4]\ => \gen_mux_rd[4].mux_rd_fall0_r_reg[4]\,
      \gen_mux_rd[4].mux_rd_fall0_r_reg[4]_0\ => \gen_mux_rd[4].mux_rd_fall0_r_reg[4]_0\,
      \gen_mux_rd[4].mux_rd_fall0_r_reg[4]_1\ => \gen_mux_rd[4].mux_rd_fall0_r_reg[4]_1\,
      \gen_mux_rd[4].mux_rd_fall1_r_reg[4]\ => \gen_mux_rd[4].mux_rd_fall1_r_reg[4]\,
      \gen_mux_rd[4].mux_rd_fall1_r_reg[4]_0\ => \gen_mux_rd[4].mux_rd_fall1_r_reg[4]_0\,
      \gen_mux_rd[4].mux_rd_fall1_r_reg[4]_1\ => \gen_mux_rd[4].mux_rd_fall1_r_reg[4]_1\,
      \gen_mux_rd[4].mux_rd_fall2_r_reg[4]\ => \gen_mux_rd[4].mux_rd_fall2_r_reg[4]\,
      \gen_mux_rd[4].mux_rd_fall2_r_reg[4]_0\ => \gen_mux_rd[4].mux_rd_fall2_r_reg[4]_0\,
      \gen_mux_rd[4].mux_rd_fall2_r_reg[4]_1\ => \gen_mux_rd[4].mux_rd_fall2_r_reg[4]_1\,
      \gen_mux_rd[4].mux_rd_fall3_r_reg[4]\ => \gen_mux_rd[4].mux_rd_fall3_r_reg[4]\,
      \gen_mux_rd[4].mux_rd_fall3_r_reg[4]_0\ => \gen_mux_rd[4].mux_rd_fall3_r_reg[4]_0\,
      \gen_mux_rd[4].mux_rd_fall3_r_reg[4]_1\ => \gen_mux_rd[4].mux_rd_fall3_r_reg[4]_1\,
      \gen_mux_rd[4].mux_rd_rise0_r_reg[4]\ => \gen_mux_rd[4].mux_rd_rise0_r_reg[4]\,
      \gen_mux_rd[4].mux_rd_rise0_r_reg[4]_0\ => \gen_mux_rd[4].mux_rd_rise0_r_reg[4]_0\,
      \gen_mux_rd[4].mux_rd_rise0_r_reg[4]_1\ => \gen_mux_rd[4].mux_rd_rise0_r_reg[4]_1\,
      \gen_mux_rd[4].mux_rd_rise1_r_reg[4]\ => \gen_mux_rd[4].mux_rd_rise1_r_reg[4]\,
      \gen_mux_rd[4].mux_rd_rise1_r_reg[4]_0\ => \gen_mux_rd[4].mux_rd_rise1_r_reg[4]_0\,
      \gen_mux_rd[4].mux_rd_rise1_r_reg[4]_1\ => \gen_mux_rd[4].mux_rd_rise1_r_reg[4]_1\,
      \gen_mux_rd[4].mux_rd_rise2_r_reg[4]\ => \gen_mux_rd[4].mux_rd_rise2_r_reg[4]\,
      \gen_mux_rd[4].mux_rd_rise2_r_reg[4]_0\ => \gen_mux_rd[4].mux_rd_rise2_r_reg[4]_0\,
      \gen_mux_rd[4].mux_rd_rise2_r_reg[4]_1\ => \gen_mux_rd[4].mux_rd_rise2_r_reg[4]_1\,
      \gen_mux_rd[4].mux_rd_rise3_r_reg[4]\ => \gen_mux_rd[4].mux_rd_rise3_r_reg[4]\,
      \gen_mux_rd[4].mux_rd_rise3_r_reg[4]_0\ => \gen_mux_rd[4].mux_rd_rise3_r_reg[4]_0\,
      \gen_mux_rd[4].mux_rd_rise3_r_reg[4]_1\ => \gen_mux_rd[4].mux_rd_rise3_r_reg[4]_1\,
      \gen_mux_rd[5].mux_rd_fall0_r_reg[5]\ => \gen_mux_rd[5].mux_rd_fall0_r_reg[5]\,
      \gen_mux_rd[5].mux_rd_fall0_r_reg[5]_0\ => \gen_mux_rd[5].mux_rd_fall0_r_reg[5]_0\,
      \gen_mux_rd[5].mux_rd_fall0_r_reg[5]_1\ => \gen_mux_rd[5].mux_rd_fall0_r_reg[5]_1\,
      \gen_mux_rd[5].mux_rd_fall1_r_reg[5]\ => \gen_mux_rd[5].mux_rd_fall1_r_reg[5]\,
      \gen_mux_rd[5].mux_rd_fall1_r_reg[5]_0\ => \gen_mux_rd[5].mux_rd_fall1_r_reg[5]_0\,
      \gen_mux_rd[5].mux_rd_fall1_r_reg[5]_1\ => \gen_mux_rd[5].mux_rd_fall1_r_reg[5]_1\,
      \gen_mux_rd[5].mux_rd_fall2_r_reg[5]\ => \gen_mux_rd[5].mux_rd_fall2_r_reg[5]\,
      \gen_mux_rd[5].mux_rd_fall2_r_reg[5]_0\ => \gen_mux_rd[5].mux_rd_fall2_r_reg[5]_0\,
      \gen_mux_rd[5].mux_rd_fall2_r_reg[5]_1\ => \gen_mux_rd[5].mux_rd_fall2_r_reg[5]_1\,
      \gen_mux_rd[5].mux_rd_fall3_r_reg[5]\ => \gen_mux_rd[5].mux_rd_fall3_r_reg[5]\,
      \gen_mux_rd[5].mux_rd_fall3_r_reg[5]_0\ => \gen_mux_rd[5].mux_rd_fall3_r_reg[5]_0\,
      \gen_mux_rd[5].mux_rd_fall3_r_reg[5]_1\ => \gen_mux_rd[5].mux_rd_fall3_r_reg[5]_1\,
      \gen_mux_rd[5].mux_rd_rise0_r_reg[5]\ => \gen_mux_rd[5].mux_rd_rise0_r_reg[5]\,
      \gen_mux_rd[5].mux_rd_rise0_r_reg[5]_0\ => \gen_mux_rd[5].mux_rd_rise0_r_reg[5]_0\,
      \gen_mux_rd[5].mux_rd_rise0_r_reg[5]_1\ => \gen_mux_rd[5].mux_rd_rise0_r_reg[5]_1\,
      \gen_mux_rd[5].mux_rd_rise1_r_reg[5]\ => \gen_mux_rd[5].mux_rd_rise1_r_reg[5]\,
      \gen_mux_rd[5].mux_rd_rise1_r_reg[5]_0\ => \gen_mux_rd[5].mux_rd_rise1_r_reg[5]_0\,
      \gen_mux_rd[5].mux_rd_rise1_r_reg[5]_1\ => \gen_mux_rd[5].mux_rd_rise1_r_reg[5]_1\,
      \gen_mux_rd[5].mux_rd_rise2_r_reg[5]\ => \gen_mux_rd[5].mux_rd_rise2_r_reg[5]\,
      \gen_mux_rd[5].mux_rd_rise2_r_reg[5]_0\ => \gen_mux_rd[5].mux_rd_rise2_r_reg[5]_0\,
      \gen_mux_rd[5].mux_rd_rise2_r_reg[5]_1\ => \gen_mux_rd[5].mux_rd_rise2_r_reg[5]_1\,
      \gen_mux_rd[5].mux_rd_rise3_r_reg[5]\ => \gen_mux_rd[5].mux_rd_rise3_r_reg[5]\,
      \gen_mux_rd[5].mux_rd_rise3_r_reg[5]_0\ => \gen_mux_rd[5].mux_rd_rise3_r_reg[5]_0\,
      \gen_mux_rd[5].mux_rd_rise3_r_reg[5]_1\ => \gen_mux_rd[5].mux_rd_rise3_r_reg[5]_1\,
      \gen_mux_rd[6].mux_rd_fall0_r_reg[6]\ => \gen_mux_rd[6].mux_rd_fall0_r_reg[6]\,
      \gen_mux_rd[6].mux_rd_fall0_r_reg[6]_0\ => \gen_mux_rd[6].mux_rd_fall0_r_reg[6]_0\,
      \gen_mux_rd[6].mux_rd_fall0_r_reg[6]_1\ => \gen_mux_rd[6].mux_rd_fall0_r_reg[6]_1\,
      \gen_mux_rd[6].mux_rd_fall1_r_reg[6]\ => \gen_mux_rd[6].mux_rd_fall1_r_reg[6]\,
      \gen_mux_rd[6].mux_rd_fall1_r_reg[6]_0\ => \gen_mux_rd[6].mux_rd_fall1_r_reg[6]_0\,
      \gen_mux_rd[6].mux_rd_fall1_r_reg[6]_1\ => \gen_mux_rd[6].mux_rd_fall1_r_reg[6]_1\,
      \gen_mux_rd[6].mux_rd_fall2_r_reg[6]\ => \gen_mux_rd[6].mux_rd_fall2_r_reg[6]\,
      \gen_mux_rd[6].mux_rd_fall2_r_reg[6]_0\ => \gen_mux_rd[6].mux_rd_fall2_r_reg[6]_0\,
      \gen_mux_rd[6].mux_rd_fall2_r_reg[6]_1\ => \gen_mux_rd[6].mux_rd_fall2_r_reg[6]_1\,
      \gen_mux_rd[6].mux_rd_fall3_r_reg[6]\ => \gen_mux_rd[6].mux_rd_fall3_r_reg[6]\,
      \gen_mux_rd[6].mux_rd_fall3_r_reg[6]_0\ => \gen_mux_rd[6].mux_rd_fall3_r_reg[6]_0\,
      \gen_mux_rd[6].mux_rd_fall3_r_reg[6]_1\ => \gen_mux_rd[6].mux_rd_fall3_r_reg[6]_1\,
      \gen_mux_rd[6].mux_rd_rise0_r_reg[6]\ => \gen_mux_rd[6].mux_rd_rise0_r_reg[6]\,
      \gen_mux_rd[6].mux_rd_rise0_r_reg[6]_0\ => \gen_mux_rd[6].mux_rd_rise0_r_reg[6]_0\,
      \gen_mux_rd[6].mux_rd_rise0_r_reg[6]_1\ => \gen_mux_rd[6].mux_rd_rise0_r_reg[6]_1\,
      \gen_mux_rd[6].mux_rd_rise1_r_reg[6]\ => \gen_mux_rd[6].mux_rd_rise1_r_reg[6]\,
      \gen_mux_rd[6].mux_rd_rise1_r_reg[6]_0\ => \gen_mux_rd[6].mux_rd_rise1_r_reg[6]_0\,
      \gen_mux_rd[6].mux_rd_rise1_r_reg[6]_1\ => \gen_mux_rd[6].mux_rd_rise1_r_reg[6]_1\,
      \gen_mux_rd[6].mux_rd_rise2_r_reg[6]\ => \gen_mux_rd[6].mux_rd_rise2_r_reg[6]\,
      \gen_mux_rd[6].mux_rd_rise2_r_reg[6]_0\ => \gen_mux_rd[6].mux_rd_rise2_r_reg[6]_0\,
      \gen_mux_rd[6].mux_rd_rise2_r_reg[6]_1\ => \gen_mux_rd[6].mux_rd_rise2_r_reg[6]_1\,
      \gen_mux_rd[6].mux_rd_rise3_r_reg[6]\ => \gen_mux_rd[6].mux_rd_rise3_r_reg[6]\,
      \gen_mux_rd[6].mux_rd_rise3_r_reg[6]_0\ => \gen_mux_rd[6].mux_rd_rise3_r_reg[6]_0\,
      \gen_mux_rd[6].mux_rd_rise3_r_reg[6]_1\ => \gen_mux_rd[6].mux_rd_rise3_r_reg[6]_1\,
      \gen_mux_rd[7].mux_rd_fall0_r_reg[7]\ => \gen_mux_rd[7].mux_rd_fall0_r_reg[7]\,
      \gen_mux_rd[7].mux_rd_fall0_r_reg[7]_0\ => \gen_mux_rd[7].mux_rd_fall0_r_reg[7]_0\,
      \gen_mux_rd[7].mux_rd_fall0_r_reg[7]_1\ => \gen_mux_rd[7].mux_rd_fall0_r_reg[7]_1\,
      \gen_mux_rd[7].mux_rd_fall1_r_reg[7]\ => \gen_mux_rd[7].mux_rd_fall1_r_reg[7]\,
      \gen_mux_rd[7].mux_rd_fall1_r_reg[7]_0\ => \gen_mux_rd[7].mux_rd_fall1_r_reg[7]_0\,
      \gen_mux_rd[7].mux_rd_fall1_r_reg[7]_1\ => \gen_mux_rd[7].mux_rd_fall1_r_reg[7]_1\,
      \gen_mux_rd[7].mux_rd_fall2_r_reg[7]\ => \gen_mux_rd[7].mux_rd_fall2_r_reg[7]\,
      \gen_mux_rd[7].mux_rd_fall2_r_reg[7]_0\ => \gen_mux_rd[7].mux_rd_fall2_r_reg[7]_0\,
      \gen_mux_rd[7].mux_rd_fall2_r_reg[7]_1\ => \gen_mux_rd[7].mux_rd_fall2_r_reg[7]_1\,
      \gen_mux_rd[7].mux_rd_fall3_r_reg[7]\ => \gen_mux_rd[7].mux_rd_fall3_r_reg[7]\,
      \gen_mux_rd[7].mux_rd_fall3_r_reg[7]_0\ => \gen_mux_rd[7].mux_rd_fall3_r_reg[7]_0\,
      \gen_mux_rd[7].mux_rd_fall3_r_reg[7]_1\ => \gen_mux_rd[7].mux_rd_fall3_r_reg[7]_1\,
      \gen_mux_rd[7].mux_rd_rise0_r_reg[7]\ => \gen_mux_rd[7].mux_rd_rise0_r_reg[7]\,
      \gen_mux_rd[7].mux_rd_rise0_r_reg[7]_0\ => \gen_mux_rd[7].mux_rd_rise0_r_reg[7]_0\,
      \gen_mux_rd[7].mux_rd_rise0_r_reg[7]_1\ => \gen_mux_rd[7].mux_rd_rise0_r_reg[7]_1\,
      \gen_mux_rd[7].mux_rd_rise1_r_reg[7]\ => \gen_mux_rd[7].mux_rd_rise1_r_reg[7]\,
      \gen_mux_rd[7].mux_rd_rise1_r_reg[7]_0\ => \gen_mux_rd[7].mux_rd_rise1_r_reg[7]_0\,
      \gen_mux_rd[7].mux_rd_rise1_r_reg[7]_1\ => \gen_mux_rd[7].mux_rd_rise1_r_reg[7]_1\,
      \gen_mux_rd[7].mux_rd_rise2_r_reg[7]\ => \gen_mux_rd[7].mux_rd_rise2_r_reg[7]\,
      \gen_mux_rd[7].mux_rd_rise2_r_reg[7]_0\ => \gen_mux_rd[7].mux_rd_rise2_r_reg[7]_0\,
      \gen_mux_rd[7].mux_rd_rise2_r_reg[7]_1\ => \gen_mux_rd[7].mux_rd_rise2_r_reg[7]_1\,
      \gen_mux_rd[7].mux_rd_rise3_r_reg[7]\ => \gen_mux_rd[7].mux_rd_rise3_r_reg[7]\,
      \gen_mux_rd[7].mux_rd_rise3_r_reg[7]_0\ => \gen_mux_rd[7].mux_rd_rise3_r_reg[7]_0\,
      \gen_mux_rd[7].mux_rd_rise3_r_reg[7]_1\ => \gen_mux_rd[7].mux_rd_rise3_r_reg[7]_1\,
      ififo_rst => ififo_rst,
      \my_empty_reg[4]_0\ => \my_empty_reg[4]\(0),
      \my_empty_reg[4]_1\(0) => \my_empty_reg[4]\(1),
      \my_full_reg[1]_0\ => \^if_empty_r\(0),
      \my_full_reg[1]_1\ => \my_full_reg[1]\,
      \rd_mux_sel_r_reg[0]\ => \rd_mux_sel_r_reg[0]\,
      \rd_mux_sel_r_reg[0]_0\ => \rd_mux_sel_r_reg[0]_0\,
      \rd_mux_sel_r_reg[0]_1\ => \rd_mux_sel_r_reg[0]_1\,
      \rd_mux_sel_r_reg[0]_10\ => \rd_mux_sel_r_reg[0]_10\,
      \rd_mux_sel_r_reg[0]_11\ => \rd_mux_sel_r_reg[0]_11\,
      \rd_mux_sel_r_reg[0]_12\ => \rd_mux_sel_r_reg[0]_12\,
      \rd_mux_sel_r_reg[0]_13\ => \rd_mux_sel_r_reg[0]_13\,
      \rd_mux_sel_r_reg[0]_14\ => \rd_mux_sel_r_reg[0]_14\,
      \rd_mux_sel_r_reg[0]_15\ => \rd_mux_sel_r_reg[0]_15\,
      \rd_mux_sel_r_reg[0]_16\ => \rd_mux_sel_r_reg[0]_16\,
      \rd_mux_sel_r_reg[0]_17\ => \rd_mux_sel_r_reg[0]_17\,
      \rd_mux_sel_r_reg[0]_18\ => \rd_mux_sel_r_reg[0]_18\,
      \rd_mux_sel_r_reg[0]_19\ => \rd_mux_sel_r_reg[0]_19\,
      \rd_mux_sel_r_reg[0]_2\ => \rd_mux_sel_r_reg[0]_2\,
      \rd_mux_sel_r_reg[0]_20\ => \rd_mux_sel_r_reg[0]_20\,
      \rd_mux_sel_r_reg[0]_21\ => \rd_mux_sel_r_reg[0]_21\,
      \rd_mux_sel_r_reg[0]_22\ => \rd_mux_sel_r_reg[0]_22\,
      \rd_mux_sel_r_reg[0]_23\ => \rd_mux_sel_r_reg[0]_23\,
      \rd_mux_sel_r_reg[0]_24\ => \rd_mux_sel_r_reg[0]_24\,
      \rd_mux_sel_r_reg[0]_25\ => \rd_mux_sel_r_reg[0]_25\,
      \rd_mux_sel_r_reg[0]_26\ => \rd_mux_sel_r_reg[0]_26\,
      \rd_mux_sel_r_reg[0]_27\ => \rd_mux_sel_r_reg[0]_27\,
      \rd_mux_sel_r_reg[0]_28\ => \rd_mux_sel_r_reg[0]_28\,
      \rd_mux_sel_r_reg[0]_29\ => \rd_mux_sel_r_reg[0]_29\,
      \rd_mux_sel_r_reg[0]_3\ => \rd_mux_sel_r_reg[0]_3\,
      \rd_mux_sel_r_reg[0]_30\ => \rd_mux_sel_r_reg[0]_30\,
      \rd_mux_sel_r_reg[0]_31\ => \rd_mux_sel_r_reg[0]_31\,
      \rd_mux_sel_r_reg[0]_32\ => \rd_mux_sel_r_reg[0]_32\,
      \rd_mux_sel_r_reg[0]_33\ => \rd_mux_sel_r_reg[0]_33\,
      \rd_mux_sel_r_reg[0]_34\ => \rd_mux_sel_r_reg[0]_34\,
      \rd_mux_sel_r_reg[0]_35\ => \rd_mux_sel_r_reg[0]_35\,
      \rd_mux_sel_r_reg[0]_36\ => \rd_mux_sel_r_reg[0]_36\,
      \rd_mux_sel_r_reg[0]_37\ => \rd_mux_sel_r_reg[0]_37\,
      \rd_mux_sel_r_reg[0]_38\ => \rd_mux_sel_r_reg[0]_38\,
      \rd_mux_sel_r_reg[0]_39\ => \rd_mux_sel_r_reg[0]_39\,
      \rd_mux_sel_r_reg[0]_4\ => \rd_mux_sel_r_reg[0]_4\,
      \rd_mux_sel_r_reg[0]_40\ => \rd_mux_sel_r_reg[0]_40\,
      \rd_mux_sel_r_reg[0]_41\ => \rd_mux_sel_r_reg[0]_41\,
      \rd_mux_sel_r_reg[0]_42\ => \rd_mux_sel_r_reg[0]_42\,
      \rd_mux_sel_r_reg[0]_43\ => \rd_mux_sel_r_reg[0]_43\,
      \rd_mux_sel_r_reg[0]_44\ => \rd_mux_sel_r_reg[0]_44\,
      \rd_mux_sel_r_reg[0]_45\ => \rd_mux_sel_r_reg[0]_45\,
      \rd_mux_sel_r_reg[0]_46\ => \rd_mux_sel_r_reg[0]_46\,
      \rd_mux_sel_r_reg[0]_47\ => \rd_mux_sel_r_reg[0]_47\,
      \rd_mux_sel_r_reg[0]_48\ => \rd_mux_sel_r_reg[0]_48\,
      \rd_mux_sel_r_reg[0]_49\ => \rd_mux_sel_r_reg[0]_49\,
      \rd_mux_sel_r_reg[0]_5\ => \rd_mux_sel_r_reg[0]_5\,
      \rd_mux_sel_r_reg[0]_50\ => \rd_mux_sel_r_reg[0]_50\,
      \rd_mux_sel_r_reg[0]_51\ => \rd_mux_sel_r_reg[0]_51\,
      \rd_mux_sel_r_reg[0]_52\ => \rd_mux_sel_r_reg[0]_52\,
      \rd_mux_sel_r_reg[0]_53\ => \rd_mux_sel_r_reg[0]_53\,
      \rd_mux_sel_r_reg[0]_54\ => \rd_mux_sel_r_reg[0]_54\,
      \rd_mux_sel_r_reg[0]_55\ => \rd_mux_sel_r_reg[0]_55\,
      \rd_mux_sel_r_reg[0]_56\ => \rd_mux_sel_r_reg[0]_56\,
      \rd_mux_sel_r_reg[0]_57\ => \rd_mux_sel_r_reg[0]_57\,
      \rd_mux_sel_r_reg[0]_58\ => \rd_mux_sel_r_reg[0]_58\,
      \rd_mux_sel_r_reg[0]_59\ => \rd_mux_sel_r_reg[0]_59\,
      \rd_mux_sel_r_reg[0]_6\ => \rd_mux_sel_r_reg[0]_6\,
      \rd_mux_sel_r_reg[0]_60\ => \rd_mux_sel_r_reg[0]_60\,
      \rd_mux_sel_r_reg[0]_61\ => \rd_mux_sel_r_reg[0]_61\,
      \rd_mux_sel_r_reg[0]_62\ => \rd_mux_sel_r_reg[0]_62\,
      \rd_mux_sel_r_reg[0]_7\ => \rd_mux_sel_r_reg[0]_7\,
      \rd_mux_sel_r_reg[0]_8\ => \rd_mux_sel_r_reg[0]_8\,
      \rd_mux_sel_r_reg[0]_9\ => \rd_mux_sel_r_reg[0]_9\,
      \rd_ptr_timing_reg[1]_0\ => \entry_cnt_reg[4]\
    );
ififo_rst_reg: unisim.vcomponents.FDSE
    generic map(
      INIT => '1'
    )
        port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => ififo_rst_reg_0,
      Q => ififo_rst,
      S => phy_if_reset
    );
\in_fifo_gen.in_fifo\: unisim.vcomponents.IN_FIFO
    generic map(
      ALMOST_EMPTY_VALUE => 1,
      ALMOST_FULL_VALUE => 1,
      ARRAY_MODE => "ARRAY_MODE_4_X_8",
      SYNCHRONOUS_MODE => "FALSE"
    )
        port map (
      ALMOSTEMPTY => \in_fifo_gen.in_fifo_n_0\,
      ALMOSTFULL => \in_fifo_gen.in_fifo_n_1\,
      D0(3 downto 0) => B"0000",
      D1(3 downto 0) => B"0000",
      D2(3 downto 0) => if_d2(3 downto 0),
      D3(3 downto 0) => if_d3(3 downto 0),
      D4(3 downto 0) => if_d4(3 downto 0),
      D5(7 downto 4) => \NLW_in_fifo_gen.in_fifo_D5_UNCONNECTED\(7 downto 4),
      D5(3 downto 0) => if_d5(3 downto 0),
      D6(7 downto 4) => \NLW_in_fifo_gen.in_fifo_D6_UNCONNECTED\(7 downto 4),
      D6(3 downto 0) => if_d6(3 downto 0),
      D7(3 downto 0) => if_d7(3 downto 0),
      D8(3 downto 0) => if_d8(3 downto 0),
      D9(3 downto 0) => if_d9(3 downto 0),
      EMPTY => \if_empty_\,
      FULL => \in_fifo_gen.in_fifo_n_3\,
      Q0(7 downto 0) => rd_data(7 downto 0),
      Q1(7 downto 0) => rd_data(15 downto 8),
      Q2(7 downto 0) => rd_data(23 downto 16),
      Q3(7 downto 0) => rd_data(31 downto 24),
      Q4(7 downto 0) => rd_data(39 downto 32),
      Q5(7 downto 0) => rd_data(47 downto 40),
      Q6(7 downto 0) => rd_data(55 downto 48),
      Q7(7 downto 0) => rd_data(63 downto 56),
      Q8(7 downto 0) => rd_data(71 downto 64),
      Q9(7 downto 0) => rd_data(79 downto 72),
      RDCLK => \entry_cnt_reg[4]\,
      RDEN => '1',
      RESET => ififo_rst,
      WRCLK => iserdes_clkdiv,
      WREN => ififo_wr_enable
    );
\of_pre_fifo_gen.u_ddr_of_pre_fifo\: entity work.\mig_mig_7series_v4_2_ddr_of_pre_fifo__parameterized1_19\
     port map (
      D0(7) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_2\,
      D0(6) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_3\,
      D0(5) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_4\,
      D0(4) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_5\,
      D0(3) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_6\,
      D0(2) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_7\,
      D0(1) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_8\,
      D0(0) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_9\,
      D1(7 downto 0) => of_d1(7 downto 0),
      Q(2 downto 0) => Q(2 downto 0),
      \entry_cnt_reg[4]_0\ => \entry_cnt_reg[4]\,
      \my_empty_reg[1]_0\ => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_0\,
      \my_empty_reg[1]_1\ => \my_empty_reg[1]\,
      \my_empty_reg[7]_0\ => out_fifo_n_3,
      ofifo_rst => ofifo_rst,
      out_fifo => out_fifo_0,
      out_fifo_0(7 downto 0) => out_fifo_1(7 downto 0),
      out_fifo_1 => out_fifo_2,
      \out_fifo_i_75__1\(71 downto 0) => \out_fifo_i_75__1\(71 downto 0),
      phy_data_wr_en => phy_data_wr_en,
      \rd_ptr_reg[3]_0\(63 downto 0) => \rd_ptr_reg[3]\(63 downto 0)
    );
ofifo_rst_reg: unisim.vcomponents.FDSE
    generic map(
      INIT => '1'
    )
        port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => ififo_rst_reg_0,
      Q => ofifo_rst,
      S => A_rst_primitives
    );
out_fifo: unisim.vcomponents.OUT_FIFO
    generic map(
      ALMOST_EMPTY_VALUE => 1,
      ALMOST_FULL_VALUE => 1,
      ARRAY_MODE => "ARRAY_MODE_8_X_4",
      OUTPUT_DISABLE => "FALSE",
      SYNCHRONOUS_MODE => "FALSE"
    )
        port map (
      ALMOSTEMPTY => out_fifo_n_0,
      ALMOSTFULL => out_fifo_n_1,
      D0(7) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_2\,
      D0(6) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_3\,
      D0(5) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_4\,
      D0(4) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_5\,
      D0(3) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_6\,
      D0(2) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_7\,
      D0(1) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_8\,
      D0(0) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_9\,
      D1(7 downto 0) => of_d1(7 downto 0),
      D2(7 downto 0) => \my_empty_reg[7]\(7 downto 0),
      D3(7 downto 0) => \my_empty_reg[7]_0\(7 downto 0),
      D4(7 downto 0) => \my_empty_reg[7]_1\(7 downto 0),
      D5(7 downto 0) => \my_empty_reg[7]_2\(7 downto 0),
      D6(7 downto 0) => \my_empty_reg[7]_3\(7 downto 0),
      D7(7 downto 0) => \my_empty_reg[7]_4\(7 downto 0),
      D8(7 downto 0) => \my_empty_reg[7]_5\(7 downto 0),
      D9(7 downto 0) => \my_empty_reg[7]_6\(7 downto 0),
      EMPTY => out_fifo_n_2,
      FULL => out_fifo_n_3,
      Q0(3 downto 0) => of_dqbus(3 downto 0),
      Q1(3 downto 0) => of_dqbus(7 downto 4),
      Q2(3 downto 0) => of_dqbus(11 downto 8),
      Q3(3 downto 0) => of_dqbus(15 downto 12),
      Q4(3 downto 0) => of_dqbus(19 downto 16),
      Q5(7 downto 4) => NLW_out_fifo_Q5_UNCONNECTED(7 downto 4),
      Q5(3 downto 0) => of_dqbus(23 downto 20),
      Q6(7 downto 4) => NLW_out_fifo_Q6_UNCONNECTED(7 downto 4),
      Q6(3 downto 0) => of_dqbus(27 downto 24),
      Q7(3 downto 0) => of_dqbus(31 downto 28),
      Q8(3 downto 0) => of_dqbus(35 downto 32),
      Q9(3 downto 0) => of_dqbus(39 downto 36),
      RDCLK => oserdes_clkdiv,
      RDEN => po_rd_enable,
      RESET => ofifo_rst,
      WRCLK => \entry_cnt_reg[4]\,
      WREN => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_0\
    );
\phaser_in_gen.phaser_in\: unisim.vcomponents.PHASER_IN_PHY
    generic map(
      BURST_MODE => "TRUE",
      CLKOUT_DIV => 2,
      DQS_AUTO_RECAL => '1',
      DQS_BIAS_MODE => "FALSE",
      DQS_FIND_PATTERN => B"000",
      FINE_DELAY => 33,
      FREQ_REF_DIV => "DIV2",
      IS_RST_INVERTED => '0',
      MEMREFCLK_PERIOD => 2.500000,
      OUTPUT_CLK_SRC => "DELAYED_REF",
      PHASEREFCLK_PERIOD => 2.500000,
      REFCLK_PERIOD => 1.250000,
      SEL_CLK_OFFSET => 6,
      SYNC_IN_DIV_RST => "TRUE",
      WR_CYCLES => "FALSE"
    )
        port map (
      BURSTPENDINGPHY => phaser_ctl_bus(1),
      COUNTERLOADEN => \pi_dqs_found_lanes_r1_reg[9]\,
      COUNTERLOADVAL(5 downto 0) => \pi_dqs_found_lanes_r1_reg[9]_3\(5 downto 0),
      COUNTERREADEN => \pi_dqs_found_lanes_r1_reg[9]_0\,
      COUNTERREADVAL(5 downto 0) => B_pi_counter_read_val(5 downto 0),
      DQSFOUND => in0(0),
      DQSOUTOFRANGE => \phaser_in_gen.phaser_in_n_1\,
      ENCALIBPHY(1 downto 0) => PCENABLECALIB(1 downto 0),
      FINEENABLE => \pi_dqs_found_lanes_r1_reg[9]_1\,
      FINEINC => \pi_dqs_found_lanes_r1_reg[9]_2\,
      FINEOVERFLOW => \phaser_in_gen.phaser_in_n_2\,
      FREQREFCLK => freq_refclk,
      ICLK => \^a_rst_primitives_reg\,
      ICLKDIV => iserdes_clkdiv,
      ISERDESRST => \phaser_in_gen.phaser_in_n_5\,
      MEMREFCLK => mem_refclk,
      PHASELOCKED => A_rst_primitives_reg_0,
      PHASEREFCLK => mem_dqs_in(0),
      RANKSELPHY(1 downto 0) => phaser_ctl_bus(3 downto 2),
      RCLK => B_rclk,
      RST => A_rst_primitives,
      RSTDQSFIND => ififo_rst_reg_0,
      SYNCIN => sync_pulse,
      SYSCLK => \entry_cnt_reg[4]\,
      WRENABLE => ififo_wr_enable
    );
phaser_out: unisim.vcomponents.PHASER_OUT_PHY
    generic map(
      CLKOUT_DIV => 2,
      COARSE_BYPASS => "FALSE",
      COARSE_DELAY => 0,
      DATA_CTL_N => "TRUE",
      DATA_RD_CYCLES => "FALSE",
      FINE_DELAY => 60,
      IS_RST_INVERTED => '0',
      MEMREFCLK_PERIOD => 2.500000,
      OCLKDELAY_INV => "FALSE",
      OCLK_DELAY => 0,
      OUTPUT_CLK_SRC => "DELAYED_REF",
      PHASEREFCLK_PERIOD => 1.000000,
      PO => B"111",
      REFCLK_PERIOD => 1.250000,
      SYNC_IN_DIV_RST => "TRUE"
    )
        port map (
      BURSTPENDINGPHY => phaser_ctl_bus(0),
      COARSEENABLE => \po_counter_read_val_reg[8]\,
      COARSEINC => \po_counter_read_val_reg[8]\,
      COARSEOVERFLOW => phaser_out_n_0,
      COUNTERLOADEN => '0',
      COUNTERLOADVAL(8 downto 0) => B"000000000",
      COUNTERREADEN => \pi_dqs_found_lanes_r1_reg[9]_0\,
      COUNTERREADVAL(8 downto 0) => B_po_counter_read_val(8 downto 0),
      CTSBUS(1 downto 0) => oserdes_dqs_ts(1 downto 0),
      DQSBUS(1 downto 0) => oserdes_dqs(1 downto 0),
      DTSBUS(1 downto 0) => oserdes_dq_ts(1 downto 0),
      ENCALIBPHY(1 downto 0) => PCENABLECALIB(1 downto 0),
      FINEENABLE => \po_counter_read_val_reg[8]_0\,
      FINEINC => \po_counter_read_val_reg[8]_1\,
      FINEOVERFLOW => phaser_out_n_1,
      FREQREFCLK => freq_refclk,
      MEMREFCLK => mem_refclk,
      OCLK => oserdes_clk,
      OCLKDELAYED => oserdes_clk_delayed,
      OCLKDIV => oserdes_clkdiv,
      OSERDESRST => po_oserdes_rst,
      PHASEREFCLK => NLW_phaser_out_PHASEREFCLK_UNCONNECTED,
      RDENABLE => po_rd_enable,
      RST => A_rst_primitives,
      SELFINEOCLKDELAY => '0',
      SYNCIN => sync_pulse,
      SYSCLK => \entry_cnt_reg[4]\
    );
\pi_counter_read_val[0]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0AAFFCCF0AA00CC"
    )
        port map (
      I0 => B_pi_counter_read_val(0),
      I1 => COUNTERREADVAL(0),
      I2 => \pi_counter_read_val_reg[5]\(0),
      I3 => calib_sel(1),
      I4 => calib_sel(0),
      I5 => \pi_counter_read_val_reg[5]_0\(0),
      O => D(0)
    );
\pi_counter_read_val[1]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0AAFFCCF0AA00CC"
    )
        port map (
      I0 => B_pi_counter_read_val(1),
      I1 => COUNTERREADVAL(1),
      I2 => \pi_counter_read_val_reg[5]\(1),
      I3 => calib_sel(1),
      I4 => calib_sel(0),
      I5 => \pi_counter_read_val_reg[5]_0\(1),
      O => D(1)
    );
\pi_counter_read_val[2]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0AAFFCCF0AA00CC"
    )
        port map (
      I0 => B_pi_counter_read_val(2),
      I1 => COUNTERREADVAL(2),
      I2 => \pi_counter_read_val_reg[5]\(2),
      I3 => calib_sel(1),
      I4 => calib_sel(0),
      I5 => \pi_counter_read_val_reg[5]_0\(2),
      O => D(2)
    );
\pi_counter_read_val[3]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0AAFFCCF0AA00CC"
    )
        port map (
      I0 => B_pi_counter_read_val(3),
      I1 => COUNTERREADVAL(3),
      I2 => \pi_counter_read_val_reg[5]\(3),
      I3 => calib_sel(1),
      I4 => calib_sel(0),
      I5 => \pi_counter_read_val_reg[5]_0\(3),
      O => D(3)
    );
\pi_counter_read_val[4]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0AAFFCCF0AA00CC"
    )
        port map (
      I0 => B_pi_counter_read_val(4),
      I1 => COUNTERREADVAL(4),
      I2 => \pi_counter_read_val_reg[5]\(4),
      I3 => calib_sel(1),
      I4 => calib_sel(0),
      I5 => \pi_counter_read_val_reg[5]_0\(4),
      O => D(4)
    );
\pi_counter_read_val[5]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0AAFFCCF0AA00CC"
    )
        port map (
      I0 => B_pi_counter_read_val(5),
      I1 => COUNTERREADVAL(5),
      I2 => \pi_counter_read_val_reg[5]\(5),
      I3 => calib_sel(1),
      I4 => calib_sel(0),
      I5 => \pi_counter_read_val_reg[5]_0\(5),
      O => D(5)
    );
\po_counter_read_val[0]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0AAFFCCF0AA00CC"
    )
        port map (
      I0 => B_po_counter_read_val(0),
      I1 => \po_counter_read_val_reg[8]_2\(0),
      I2 => \po_counter_read_val_reg[8]_3\(0),
      I3 => calib_sel(1),
      I4 => calib_sel(0),
      I5 => \po_counter_read_val_reg[8]_4\(0),
      O => \calib_sel_reg[1]\(0)
    );
\po_counter_read_val[1]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0AAFFCCF0AA00CC"
    )
        port map (
      I0 => B_po_counter_read_val(1),
      I1 => \po_counter_read_val_reg[8]_2\(1),
      I2 => \po_counter_read_val_reg[8]_3\(1),
      I3 => calib_sel(1),
      I4 => calib_sel(0),
      I5 => \po_counter_read_val_reg[8]_4\(1),
      O => \calib_sel_reg[1]\(1)
    );
\po_counter_read_val[2]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0AAFFCCF0AA00CC"
    )
        port map (
      I0 => B_po_counter_read_val(2),
      I1 => \po_counter_read_val_reg[8]_2\(2),
      I2 => \po_counter_read_val_reg[8]_3\(2),
      I3 => calib_sel(1),
      I4 => calib_sel(0),
      I5 => \po_counter_read_val_reg[8]_4\(2),
      O => \calib_sel_reg[1]\(2)
    );
\po_counter_read_val[3]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0AAFFCCF0AA00CC"
    )
        port map (
      I0 => B_po_counter_read_val(3),
      I1 => \po_counter_read_val_reg[8]_2\(3),
      I2 => \po_counter_read_val_reg[8]_3\(3),
      I3 => calib_sel(1),
      I4 => calib_sel(0),
      I5 => \po_counter_read_val_reg[8]_4\(3),
      O => \calib_sel_reg[1]\(3)
    );
\po_counter_read_val[4]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0AAFFCCF0AA00CC"
    )
        port map (
      I0 => B_po_counter_read_val(4),
      I1 => \po_counter_read_val_reg[8]_2\(4),
      I2 => \po_counter_read_val_reg[8]_3\(4),
      I3 => calib_sel(1),
      I4 => calib_sel(0),
      I5 => \po_counter_read_val_reg[8]_4\(4),
      O => \calib_sel_reg[1]\(4)
    );
\po_counter_read_val[5]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0AAFFCCF0AA00CC"
    )
        port map (
      I0 => B_po_counter_read_val(5),
      I1 => \po_counter_read_val_reg[8]_2\(5),
      I2 => \po_counter_read_val_reg[8]_3\(5),
      I3 => calib_sel(1),
      I4 => calib_sel(0),
      I5 => \po_counter_read_val_reg[8]_4\(5),
      O => \calib_sel_reg[1]\(5)
    );
\po_counter_read_val[6]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0AAFFCCF0AA00CC"
    )
        port map (
      I0 => B_po_counter_read_val(6),
      I1 => \po_counter_read_val_reg[8]_2\(6),
      I2 => \po_counter_read_val_reg[8]_3\(6),
      I3 => calib_sel(1),
      I4 => calib_sel(0),
      I5 => \po_counter_read_val_reg[8]_4\(6),
      O => \calib_sel_reg[1]\(6)
    );
\po_counter_read_val[7]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0AAFFCCF0AA00CC"
    )
        port map (
      I0 => B_po_counter_read_val(7),
      I1 => \po_counter_read_val_reg[8]_2\(7),
      I2 => \po_counter_read_val_reg[8]_3\(7),
      I3 => calib_sel(1),
      I4 => calib_sel(0),
      I5 => \po_counter_read_val_reg[8]_4\(7),
      O => \calib_sel_reg[1]\(7)
    );
\po_counter_read_val[8]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0AAFFCCF0AA00CC"
    )
        port map (
      I0 => B_po_counter_read_val(8),
      I1 => \po_counter_read_val_reg[8]_2\(8),
      I2 => \po_counter_read_val_reg[8]_3\(8),
      I3 => calib_sel(1),
      I4 => calib_sel(0),
      I5 => \po_counter_read_val_reg[8]_4\(8),
      O => \calib_sel_reg[1]\(8)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \mig_mig_7series_v4_2_ddr_byte_lane__parameterized0_26\ is
  port (
    out_dqs_5 : out STD_LOGIC;
    ts_dqs_5 : out STD_LOGIC;
    A_rst_primitives_reg : out STD_LOGIC;
    mem_dq_out : out STD_LOGIC_VECTOR ( 8 downto 0 );
    mem_dq_ts : out STD_LOGIC_VECTOR ( 8 downto 0 );
    in0 : out STD_LOGIC_VECTOR ( 0 to 0 );
    A_rst_primitives_reg_0 : out STD_LOGIC;
    B_rclk : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0\ : out STD_LOGIC;
    \my_empty_reg[4]\ : out STD_LOGIC;
    idelay_ld_rst_0 : out STD_LOGIC;
    \my_empty_reg[4]_0\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1\ : out STD_LOGIC;
    \my_empty_reg[1]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_0\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_1\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_2\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_3\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_4\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_5\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_6\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_7\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_8\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_9\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_10\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_11\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_12\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_13\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_14\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_15\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_16\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_17\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_18\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_19\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_20\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_21\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_22\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_23\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_24\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_25\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_26\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_27\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_28\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_29\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_30\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_31\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_32\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_33\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_34\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_35\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_36\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_37\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_38\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_39\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_40\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_41\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_42\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_43\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_44\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_45\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_46\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_47\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_48\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_49\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_50\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_51\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_52\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_53\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_54\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_55\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_56\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_57\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_58\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_59\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_60\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_61\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_62\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_2\ : out STD_LOGIC;
    \rd_ptr_reg[3]\ : out STD_LOGIC_VECTOR ( 63 downto 0 );
    D : out STD_LOGIC_VECTOR ( 5 downto 0 );
    \calib_sel_reg[1]\ : out STD_LOGIC_VECTOR ( 8 downto 0 );
    Q : out STD_LOGIC_VECTOR ( 2 downto 0 );
    \entry_cnt_reg[4]\ : in STD_LOGIC;
    \input_[9].iserdes_dq_.iserdesdq\ : in STD_LOGIC;
    mem_dq_in : in STD_LOGIC_VECTOR ( 7 downto 0 );
    idelay_inc : in STD_LOGIC;
    LD0_7 : in STD_LOGIC;
    A_rst_primitives : in STD_LOGIC;
    CLKB0_7 : in STD_LOGIC;
    phaser_ctl_bus : in STD_LOGIC_VECTOR ( 3 downto 0 );
    \pi_dqs_found_lanes_r1_reg[1]\ : in STD_LOGIC;
    \pi_dqs_found_lanes_r1_reg[1]_0\ : in STD_LOGIC;
    \pi_dqs_found_lanes_r1_reg[1]_1\ : in STD_LOGIC;
    \pi_dqs_found_lanes_r1_reg[1]_2\ : in STD_LOGIC;
    freq_refclk : in STD_LOGIC;
    mem_refclk : in STD_LOGIC;
    mem_dqs_in : in STD_LOGIC_VECTOR ( 0 to 0 );
    ififo_rst_reg_0 : in STD_LOGIC;
    sync_pulse : in STD_LOGIC;
    PCENABLECALIB : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \pi_dqs_found_lanes_r1_reg[1]_3\ : in STD_LOGIC_VECTOR ( 5 downto 0 );
    \po_counter_read_val_reg[8]\ : in STD_LOGIC;
    \po_counter_read_val_reg[8]_0\ : in STD_LOGIC;
    \po_counter_read_val_reg[8]_1\ : in STD_LOGIC;
    \my_empty_reg[7]\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \my_empty_reg[7]_0\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \my_empty_reg[7]_1\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \my_empty_reg[7]_2\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \my_empty_reg[7]_3\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \my_empty_reg[7]_4\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \my_empty_reg[7]_5\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \my_empty_reg[7]_6\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    phy_if_reset : in STD_LOGIC;
    \my_full_reg[1]\ : in STD_LOGIC;
    my_empty : in STD_LOGIC_VECTOR ( 0 to 0 );
    \wr_ptr[1]_i_2__0\ : in STD_LOGIC;
    phy_data_wr_en : in STD_LOGIC;
    rst_r4 : in STD_LOGIC;
    \gen_mux_rd[0].mux_rd_rise0_r_reg[0]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \gen_mux_rd[0].mux_rd_rise0_r_reg[0]_0\ : in STD_LOGIC;
    \gen_mux_rd[0].mux_rd_rise0_r_reg[0]_1\ : in STD_LOGIC;
    \gen_mux_rd[0].mux_rd_rise0_r_reg[0]_2\ : in STD_LOGIC;
    \gen_mux_rd[1].mux_rd_rise0_r_reg[1]\ : in STD_LOGIC;
    \gen_mux_rd[1].mux_rd_rise0_r_reg[1]_0\ : in STD_LOGIC;
    \gen_mux_rd[1].mux_rd_rise0_r_reg[1]_1\ : in STD_LOGIC;
    \gen_mux_rd[2].mux_rd_rise0_r_reg[2]\ : in STD_LOGIC;
    \gen_mux_rd[2].mux_rd_rise0_r_reg[2]_0\ : in STD_LOGIC;
    \gen_mux_rd[2].mux_rd_rise0_r_reg[2]_1\ : in STD_LOGIC;
    \gen_mux_rd[3].mux_rd_rise0_r_reg[3]\ : in STD_LOGIC;
    \gen_mux_rd[3].mux_rd_rise0_r_reg[3]_0\ : in STD_LOGIC;
    \gen_mux_rd[3].mux_rd_rise0_r_reg[3]_1\ : in STD_LOGIC;
    \gen_mux_rd[4].mux_rd_rise0_r_reg[4]\ : in STD_LOGIC;
    \gen_mux_rd[4].mux_rd_rise0_r_reg[4]_0\ : in STD_LOGIC;
    \gen_mux_rd[4].mux_rd_rise0_r_reg[4]_1\ : in STD_LOGIC;
    \gen_mux_rd[5].mux_rd_rise0_r_reg[5]\ : in STD_LOGIC;
    \gen_mux_rd[5].mux_rd_rise0_r_reg[5]_0\ : in STD_LOGIC;
    \gen_mux_rd[5].mux_rd_rise0_r_reg[5]_1\ : in STD_LOGIC;
    \gen_mux_rd[6].mux_rd_rise0_r_reg[6]\ : in STD_LOGIC;
    \gen_mux_rd[6].mux_rd_rise0_r_reg[6]_0\ : in STD_LOGIC;
    \gen_mux_rd[6].mux_rd_rise0_r_reg[6]_1\ : in STD_LOGIC;
    \gen_mux_rd[7].mux_rd_rise0_r_reg[7]\ : in STD_LOGIC;
    \gen_mux_rd[7].mux_rd_rise0_r_reg[7]_0\ : in STD_LOGIC;
    \gen_mux_rd[7].mux_rd_rise0_r_reg[7]_1\ : in STD_LOGIC;
    \gen_mux_rd[0].mux_rd_fall0_r_reg[0]\ : in STD_LOGIC;
    \gen_mux_rd[0].mux_rd_fall0_r_reg[0]_0\ : in STD_LOGIC;
    \gen_mux_rd[0].mux_rd_fall0_r_reg[0]_1\ : in STD_LOGIC;
    \gen_mux_rd[1].mux_rd_fall0_r_reg[1]\ : in STD_LOGIC;
    \gen_mux_rd[1].mux_rd_fall0_r_reg[1]_0\ : in STD_LOGIC;
    \gen_mux_rd[1].mux_rd_fall0_r_reg[1]_1\ : in STD_LOGIC;
    \gen_mux_rd[2].mux_rd_fall0_r_reg[2]\ : in STD_LOGIC;
    \gen_mux_rd[2].mux_rd_fall0_r_reg[2]_0\ : in STD_LOGIC;
    \gen_mux_rd[2].mux_rd_fall0_r_reg[2]_1\ : in STD_LOGIC;
    \gen_mux_rd[3].mux_rd_fall0_r_reg[3]\ : in STD_LOGIC;
    \gen_mux_rd[3].mux_rd_fall0_r_reg[3]_0\ : in STD_LOGIC;
    \gen_mux_rd[3].mux_rd_fall0_r_reg[3]_1\ : in STD_LOGIC;
    \gen_mux_rd[4].mux_rd_fall0_r_reg[4]\ : in STD_LOGIC;
    \gen_mux_rd[4].mux_rd_fall0_r_reg[4]_0\ : in STD_LOGIC;
    \gen_mux_rd[4].mux_rd_fall0_r_reg[4]_1\ : in STD_LOGIC;
    \gen_mux_rd[5].mux_rd_fall0_r_reg[5]\ : in STD_LOGIC;
    \gen_mux_rd[5].mux_rd_fall0_r_reg[5]_0\ : in STD_LOGIC;
    \gen_mux_rd[5].mux_rd_fall0_r_reg[5]_1\ : in STD_LOGIC;
    \gen_mux_rd[6].mux_rd_fall0_r_reg[6]\ : in STD_LOGIC;
    \gen_mux_rd[6].mux_rd_fall0_r_reg[6]_0\ : in STD_LOGIC;
    \gen_mux_rd[6].mux_rd_fall0_r_reg[6]_1\ : in STD_LOGIC;
    \gen_mux_rd[7].mux_rd_fall0_r_reg[7]\ : in STD_LOGIC;
    \gen_mux_rd[7].mux_rd_fall0_r_reg[7]_0\ : in STD_LOGIC;
    \gen_mux_rd[7].mux_rd_fall0_r_reg[7]_1\ : in STD_LOGIC;
    \gen_mux_rd[0].mux_rd_rise1_r_reg[0]\ : in STD_LOGIC;
    \gen_mux_rd[0].mux_rd_rise1_r_reg[0]_0\ : in STD_LOGIC;
    \gen_mux_rd[0].mux_rd_rise1_r_reg[0]_1\ : in STD_LOGIC;
    \gen_mux_rd[1].mux_rd_rise1_r_reg[1]\ : in STD_LOGIC;
    \gen_mux_rd[1].mux_rd_rise1_r_reg[1]_0\ : in STD_LOGIC;
    \gen_mux_rd[1].mux_rd_rise1_r_reg[1]_1\ : in STD_LOGIC;
    \gen_mux_rd[2].mux_rd_rise1_r_reg[2]\ : in STD_LOGIC;
    \gen_mux_rd[2].mux_rd_rise1_r_reg[2]_0\ : in STD_LOGIC;
    \gen_mux_rd[2].mux_rd_rise1_r_reg[2]_1\ : in STD_LOGIC;
    \gen_mux_rd[3].mux_rd_rise1_r_reg[3]\ : in STD_LOGIC;
    \gen_mux_rd[3].mux_rd_rise1_r_reg[3]_0\ : in STD_LOGIC;
    \gen_mux_rd[3].mux_rd_rise1_r_reg[3]_1\ : in STD_LOGIC;
    \gen_mux_rd[4].mux_rd_rise1_r_reg[4]\ : in STD_LOGIC;
    \gen_mux_rd[4].mux_rd_rise1_r_reg[4]_0\ : in STD_LOGIC;
    \gen_mux_rd[4].mux_rd_rise1_r_reg[4]_1\ : in STD_LOGIC;
    \gen_mux_rd[5].mux_rd_rise1_r_reg[5]\ : in STD_LOGIC;
    \gen_mux_rd[5].mux_rd_rise1_r_reg[5]_0\ : in STD_LOGIC;
    \gen_mux_rd[5].mux_rd_rise1_r_reg[5]_1\ : in STD_LOGIC;
    \gen_mux_rd[6].mux_rd_rise1_r_reg[6]\ : in STD_LOGIC;
    \gen_mux_rd[6].mux_rd_rise1_r_reg[6]_0\ : in STD_LOGIC;
    \gen_mux_rd[6].mux_rd_rise1_r_reg[6]_1\ : in STD_LOGIC;
    \gen_mux_rd[7].mux_rd_rise1_r_reg[7]\ : in STD_LOGIC;
    \gen_mux_rd[7].mux_rd_rise1_r_reg[7]_0\ : in STD_LOGIC;
    \gen_mux_rd[7].mux_rd_rise1_r_reg[7]_1\ : in STD_LOGIC;
    \gen_mux_rd[0].mux_rd_fall1_r_reg[0]\ : in STD_LOGIC;
    \gen_mux_rd[0].mux_rd_fall1_r_reg[0]_0\ : in STD_LOGIC;
    \gen_mux_rd[0].mux_rd_fall1_r_reg[0]_1\ : in STD_LOGIC;
    \gen_mux_rd[1].mux_rd_fall1_r_reg[1]\ : in STD_LOGIC;
    \gen_mux_rd[1].mux_rd_fall1_r_reg[1]_0\ : in STD_LOGIC;
    \gen_mux_rd[1].mux_rd_fall1_r_reg[1]_1\ : in STD_LOGIC;
    \gen_mux_rd[2].mux_rd_fall1_r_reg[2]\ : in STD_LOGIC;
    \gen_mux_rd[2].mux_rd_fall1_r_reg[2]_0\ : in STD_LOGIC;
    \gen_mux_rd[2].mux_rd_fall1_r_reg[2]_1\ : in STD_LOGIC;
    \gen_mux_rd[3].mux_rd_fall1_r_reg[3]\ : in STD_LOGIC;
    \gen_mux_rd[3].mux_rd_fall1_r_reg[3]_0\ : in STD_LOGIC;
    \gen_mux_rd[3].mux_rd_fall1_r_reg[3]_1\ : in STD_LOGIC;
    \gen_mux_rd[4].mux_rd_fall1_r_reg[4]\ : in STD_LOGIC;
    \gen_mux_rd[4].mux_rd_fall1_r_reg[4]_0\ : in STD_LOGIC;
    \gen_mux_rd[4].mux_rd_fall1_r_reg[4]_1\ : in STD_LOGIC;
    \gen_mux_rd[5].mux_rd_fall1_r_reg[5]\ : in STD_LOGIC;
    \gen_mux_rd[5].mux_rd_fall1_r_reg[5]_0\ : in STD_LOGIC;
    \gen_mux_rd[5].mux_rd_fall1_r_reg[5]_1\ : in STD_LOGIC;
    \gen_mux_rd[6].mux_rd_fall1_r_reg[6]\ : in STD_LOGIC;
    \gen_mux_rd[6].mux_rd_fall1_r_reg[6]_0\ : in STD_LOGIC;
    \gen_mux_rd[6].mux_rd_fall1_r_reg[6]_1\ : in STD_LOGIC;
    \gen_mux_rd[7].mux_rd_fall1_r_reg[7]\ : in STD_LOGIC;
    \gen_mux_rd[7].mux_rd_fall1_r_reg[7]_0\ : in STD_LOGIC;
    \gen_mux_rd[7].mux_rd_fall1_r_reg[7]_1\ : in STD_LOGIC;
    \gen_mux_rd[0].mux_rd_rise2_r_reg[0]\ : in STD_LOGIC;
    \gen_mux_rd[0].mux_rd_rise2_r_reg[0]_0\ : in STD_LOGIC;
    \gen_mux_rd[0].mux_rd_rise2_r_reg[0]_1\ : in STD_LOGIC;
    \gen_mux_rd[1].mux_rd_rise2_r_reg[1]\ : in STD_LOGIC;
    \gen_mux_rd[1].mux_rd_rise2_r_reg[1]_0\ : in STD_LOGIC;
    \gen_mux_rd[1].mux_rd_rise2_r_reg[1]_1\ : in STD_LOGIC;
    \gen_mux_rd[2].mux_rd_rise2_r_reg[2]\ : in STD_LOGIC;
    \gen_mux_rd[2].mux_rd_rise2_r_reg[2]_0\ : in STD_LOGIC;
    \gen_mux_rd[2].mux_rd_rise2_r_reg[2]_1\ : in STD_LOGIC;
    \gen_mux_rd[3].mux_rd_rise2_r_reg[3]\ : in STD_LOGIC;
    \gen_mux_rd[3].mux_rd_rise2_r_reg[3]_0\ : in STD_LOGIC;
    \gen_mux_rd[3].mux_rd_rise2_r_reg[3]_1\ : in STD_LOGIC;
    \gen_mux_rd[4].mux_rd_rise2_r_reg[4]\ : in STD_LOGIC;
    \gen_mux_rd[4].mux_rd_rise2_r_reg[4]_0\ : in STD_LOGIC;
    \gen_mux_rd[4].mux_rd_rise2_r_reg[4]_1\ : in STD_LOGIC;
    \gen_mux_rd[5].mux_rd_rise2_r_reg[5]\ : in STD_LOGIC;
    \gen_mux_rd[5].mux_rd_rise2_r_reg[5]_0\ : in STD_LOGIC;
    \gen_mux_rd[5].mux_rd_rise2_r_reg[5]_1\ : in STD_LOGIC;
    \gen_mux_rd[6].mux_rd_rise2_r_reg[6]\ : in STD_LOGIC;
    \gen_mux_rd[6].mux_rd_rise2_r_reg[6]_0\ : in STD_LOGIC;
    \gen_mux_rd[6].mux_rd_rise2_r_reg[6]_1\ : in STD_LOGIC;
    \gen_mux_rd[7].mux_rd_rise2_r_reg[7]\ : in STD_LOGIC;
    \gen_mux_rd[7].mux_rd_rise2_r_reg[7]_0\ : in STD_LOGIC;
    \gen_mux_rd[7].mux_rd_rise2_r_reg[7]_1\ : in STD_LOGIC;
    \gen_mux_rd[0].mux_rd_fall2_r_reg[0]\ : in STD_LOGIC;
    \gen_mux_rd[0].mux_rd_fall2_r_reg[0]_0\ : in STD_LOGIC;
    \gen_mux_rd[0].mux_rd_fall2_r_reg[0]_1\ : in STD_LOGIC;
    \gen_mux_rd[1].mux_rd_fall2_r_reg[1]\ : in STD_LOGIC;
    \gen_mux_rd[1].mux_rd_fall2_r_reg[1]_0\ : in STD_LOGIC;
    \gen_mux_rd[1].mux_rd_fall2_r_reg[1]_1\ : in STD_LOGIC;
    \gen_mux_rd[2].mux_rd_fall2_r_reg[2]\ : in STD_LOGIC;
    \gen_mux_rd[2].mux_rd_fall2_r_reg[2]_0\ : in STD_LOGIC;
    \gen_mux_rd[2].mux_rd_fall2_r_reg[2]_1\ : in STD_LOGIC;
    \gen_mux_rd[3].mux_rd_fall2_r_reg[3]\ : in STD_LOGIC;
    \gen_mux_rd[3].mux_rd_fall2_r_reg[3]_0\ : in STD_LOGIC;
    \gen_mux_rd[3].mux_rd_fall2_r_reg[3]_1\ : in STD_LOGIC;
    \gen_mux_rd[4].mux_rd_fall2_r_reg[4]\ : in STD_LOGIC;
    \gen_mux_rd[4].mux_rd_fall2_r_reg[4]_0\ : in STD_LOGIC;
    \gen_mux_rd[4].mux_rd_fall2_r_reg[4]_1\ : in STD_LOGIC;
    \gen_mux_rd[5].mux_rd_fall2_r_reg[5]\ : in STD_LOGIC;
    \gen_mux_rd[5].mux_rd_fall2_r_reg[5]_0\ : in STD_LOGIC;
    \gen_mux_rd[5].mux_rd_fall2_r_reg[5]_1\ : in STD_LOGIC;
    \gen_mux_rd[6].mux_rd_fall2_r_reg[6]\ : in STD_LOGIC;
    \gen_mux_rd[6].mux_rd_fall2_r_reg[6]_0\ : in STD_LOGIC;
    \gen_mux_rd[6].mux_rd_fall2_r_reg[6]_1\ : in STD_LOGIC;
    \gen_mux_rd[7].mux_rd_fall2_r_reg[7]\ : in STD_LOGIC;
    \gen_mux_rd[7].mux_rd_fall2_r_reg[7]_0\ : in STD_LOGIC;
    \gen_mux_rd[7].mux_rd_fall2_r_reg[7]_1\ : in STD_LOGIC;
    \gen_mux_rd[0].mux_rd_rise3_r_reg[0]\ : in STD_LOGIC;
    \gen_mux_rd[0].mux_rd_rise3_r_reg[0]_0\ : in STD_LOGIC;
    \gen_mux_rd[0].mux_rd_rise3_r_reg[0]_1\ : in STD_LOGIC;
    \gen_mux_rd[1].mux_rd_rise3_r_reg[1]\ : in STD_LOGIC;
    \gen_mux_rd[1].mux_rd_rise3_r_reg[1]_0\ : in STD_LOGIC;
    \gen_mux_rd[1].mux_rd_rise3_r_reg[1]_1\ : in STD_LOGIC;
    \gen_mux_rd[2].mux_rd_rise3_r_reg[2]\ : in STD_LOGIC;
    \gen_mux_rd[2].mux_rd_rise3_r_reg[2]_0\ : in STD_LOGIC;
    \gen_mux_rd[2].mux_rd_rise3_r_reg[2]_1\ : in STD_LOGIC;
    \gen_mux_rd[3].mux_rd_rise3_r_reg[3]\ : in STD_LOGIC;
    \gen_mux_rd[3].mux_rd_rise3_r_reg[3]_0\ : in STD_LOGIC;
    \gen_mux_rd[3].mux_rd_rise3_r_reg[3]_1\ : in STD_LOGIC;
    \gen_mux_rd[4].mux_rd_rise3_r_reg[4]\ : in STD_LOGIC;
    \gen_mux_rd[4].mux_rd_rise3_r_reg[4]_0\ : in STD_LOGIC;
    \gen_mux_rd[4].mux_rd_rise3_r_reg[4]_1\ : in STD_LOGIC;
    \gen_mux_rd[5].mux_rd_rise3_r_reg[5]\ : in STD_LOGIC;
    \gen_mux_rd[5].mux_rd_rise3_r_reg[5]_0\ : in STD_LOGIC;
    \gen_mux_rd[5].mux_rd_rise3_r_reg[5]_1\ : in STD_LOGIC;
    \gen_mux_rd[6].mux_rd_rise3_r_reg[6]\ : in STD_LOGIC;
    \gen_mux_rd[6].mux_rd_rise3_r_reg[6]_0\ : in STD_LOGIC;
    \gen_mux_rd[6].mux_rd_rise3_r_reg[6]_1\ : in STD_LOGIC;
    \gen_mux_rd[7].mux_rd_rise3_r_reg[7]\ : in STD_LOGIC;
    \gen_mux_rd[7].mux_rd_rise3_r_reg[7]_0\ : in STD_LOGIC;
    \gen_mux_rd[7].mux_rd_rise3_r_reg[7]_1\ : in STD_LOGIC;
    \gen_mux_rd[0].mux_rd_fall3_r_reg[0]\ : in STD_LOGIC;
    \gen_mux_rd[0].mux_rd_fall3_r_reg[0]_0\ : in STD_LOGIC;
    \gen_mux_rd[0].mux_rd_fall3_r_reg[0]_1\ : in STD_LOGIC;
    \gen_mux_rd[1].mux_rd_fall3_r_reg[1]\ : in STD_LOGIC;
    \gen_mux_rd[1].mux_rd_fall3_r_reg[1]_0\ : in STD_LOGIC;
    \gen_mux_rd[1].mux_rd_fall3_r_reg[1]_1\ : in STD_LOGIC;
    \gen_mux_rd[2].mux_rd_fall3_r_reg[2]\ : in STD_LOGIC;
    \gen_mux_rd[2].mux_rd_fall3_r_reg[2]_0\ : in STD_LOGIC;
    \gen_mux_rd[2].mux_rd_fall3_r_reg[2]_1\ : in STD_LOGIC;
    \gen_mux_rd[3].mux_rd_fall3_r_reg[3]\ : in STD_LOGIC;
    \gen_mux_rd[3].mux_rd_fall3_r_reg[3]_0\ : in STD_LOGIC;
    \gen_mux_rd[3].mux_rd_fall3_r_reg[3]_1\ : in STD_LOGIC;
    \gen_mux_rd[4].mux_rd_fall3_r_reg[4]\ : in STD_LOGIC;
    \gen_mux_rd[4].mux_rd_fall3_r_reg[4]_0\ : in STD_LOGIC;
    \gen_mux_rd[4].mux_rd_fall3_r_reg[4]_1\ : in STD_LOGIC;
    \gen_mux_rd[5].mux_rd_fall3_r_reg[5]\ : in STD_LOGIC;
    \gen_mux_rd[5].mux_rd_fall3_r_reg[5]_0\ : in STD_LOGIC;
    \gen_mux_rd[5].mux_rd_fall3_r_reg[5]_1\ : in STD_LOGIC;
    \gen_mux_rd[6].mux_rd_fall3_r_reg[6]\ : in STD_LOGIC;
    \gen_mux_rd[6].mux_rd_fall3_r_reg[6]_0\ : in STD_LOGIC;
    \gen_mux_rd[6].mux_rd_fall3_r_reg[6]_1\ : in STD_LOGIC;
    \gen_mux_rd[7].mux_rd_fall3_r_reg[7]\ : in STD_LOGIC;
    \gen_mux_rd[7].mux_rd_fall3_r_reg[7]_0\ : in STD_LOGIC;
    \gen_mux_rd[7].mux_rd_fall3_r_reg[7]_1\ : in STD_LOGIC;
    out_fifo_0 : in STD_LOGIC;
    out_fifo_1 : in STD_LOGIC_VECTOR ( 7 downto 0 );
    out_fifo_2 : in STD_LOGIC;
    \gen_mux_rd[1].mux_rd_rise0_r_reg[1]_2\ : in STD_LOGIC;
    \gen_mux_rd[1].mux_rd_rise0_r_reg[1]_3\ : in STD_LOGIC;
    \gen_mux_rd[2].mux_rd_rise0_r_reg[2]_2\ : in STD_LOGIC;
    \gen_mux_rd[3].mux_rd_rise0_r_reg[3]_2\ : in STD_LOGIC;
    \gen_mux_rd[5].mux_rd_rise0_r_reg[5]_2\ : in STD_LOGIC;
    \gen_mux_rd[6].mux_rd_rise0_r_reg[6]_2\ : in STD_LOGIC;
    \gen_mux_rd[7].mux_rd_rise0_r_reg[7]_2\ : in STD_LOGIC;
    \gen_mux_rd[1].mux_rd_fall0_r_reg[1]_2\ : in STD_LOGIC;
    \gen_mux_rd[3].mux_rd_fall0_r_reg[3]_2\ : in STD_LOGIC;
    \gen_mux_rd[5].mux_rd_fall0_r_reg[5]_2\ : in STD_LOGIC;
    \gen_mux_rd[6].mux_rd_fall0_r_reg[6]_2\ : in STD_LOGIC;
    \gen_mux_rd[7].mux_rd_fall0_r_reg[7]_2\ : in STD_LOGIC;
    \gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2\ : in STD_LOGIC;
    \gen_mux_rd[1].mux_rd_rise1_r_reg[1]_2\ : in STD_LOGIC;
    \gen_mux_rd[3].mux_rd_rise1_r_reg[3]_2\ : in STD_LOGIC;
    \gen_mux_rd[5].mux_rd_rise1_r_reg[5]_2\ : in STD_LOGIC;
    \gen_mux_rd[6].mux_rd_rise1_r_reg[6]_2\ : in STD_LOGIC;
    \gen_mux_rd[7].mux_rd_rise1_r_reg[7]_2\ : in STD_LOGIC;
    \gen_mux_rd[1].mux_rd_fall1_r_reg[1]_2\ : in STD_LOGIC;
    \gen_mux_rd[3].mux_rd_fall1_r_reg[3]_2\ : in STD_LOGIC;
    \gen_mux_rd[5].mux_rd_fall1_r_reg[5]_2\ : in STD_LOGIC;
    \gen_mux_rd[6].mux_rd_fall1_r_reg[6]_2\ : in STD_LOGIC;
    \gen_mux_rd[7].mux_rd_fall1_r_reg[7]_2\ : in STD_LOGIC;
    \gen_mux_rd[0].mux_rd_rise2_r_reg[0]_2\ : in STD_LOGIC;
    \gen_mux_rd[1].mux_rd_rise2_r_reg[1]_2\ : in STD_LOGIC;
    \gen_mux_rd[2].mux_rd_rise2_r_reg[2]_2\ : in STD_LOGIC;
    \gen_mux_rd[3].mux_rd_rise2_r_reg[3]_2\ : in STD_LOGIC;
    \gen_mux_rd[5].mux_rd_rise2_r_reg[5]_2\ : in STD_LOGIC;
    \gen_mux_rd[6].mux_rd_rise2_r_reg[6]_2\ : in STD_LOGIC;
    \gen_mux_rd[7].mux_rd_rise2_r_reg[7]_2\ : in STD_LOGIC;
    \gen_mux_rd[1].mux_rd_fall2_r_reg[1]_2\ : in STD_LOGIC;
    \gen_mux_rd[2].mux_rd_fall2_r_reg[2]_2\ : in STD_LOGIC;
    \gen_mux_rd[3].mux_rd_fall2_r_reg[3]_2\ : in STD_LOGIC;
    \gen_mux_rd[5].mux_rd_fall2_r_reg[5]_2\ : in STD_LOGIC;
    \gen_mux_rd[6].mux_rd_fall2_r_reg[6]_2\ : in STD_LOGIC;
    \gen_mux_rd[7].mux_rd_fall2_r_reg[7]_2\ : in STD_LOGIC;
    \gen_mux_rd[1].mux_rd_rise3_r_reg[1]_2\ : in STD_LOGIC;
    \gen_mux_rd[2].mux_rd_rise3_r_reg[2]_2\ : in STD_LOGIC;
    \gen_mux_rd[3].mux_rd_rise3_r_reg[3]_2\ : in STD_LOGIC;
    \gen_mux_rd[5].mux_rd_rise3_r_reg[5]_2\ : in STD_LOGIC;
    \gen_mux_rd[6].mux_rd_rise3_r_reg[6]_2\ : in STD_LOGIC;
    \gen_mux_rd[7].mux_rd_rise3_r_reg[7]_2\ : in STD_LOGIC;
    \gen_mux_rd[0].mux_rd_fall3_r_reg[0]_2\ : in STD_LOGIC;
    \gen_mux_rd[1].mux_rd_fall3_r_reg[1]_2\ : in STD_LOGIC;
    \gen_mux_rd[2].mux_rd_fall3_r_reg[2]_2\ : in STD_LOGIC;
    \gen_mux_rd[3].mux_rd_fall3_r_reg[3]_2\ : in STD_LOGIC;
    \gen_mux_rd[4].mux_rd_fall3_r_reg[4]_2\ : in STD_LOGIC;
    \gen_mux_rd[5].mux_rd_fall3_r_reg[5]_2\ : in STD_LOGIC;
    \gen_mux_rd[6].mux_rd_fall3_r_reg[6]_2\ : in STD_LOGIC;
    \gen_mux_rd[7].mux_rd_fall3_r_reg[7]_2\ : in STD_LOGIC;
    \gen_mux_rd[0].mux_rd_rise0_r_reg[0]_3\ : in STD_LOGIC;
    \gen_mux_rd[4].mux_rd_rise0_r_reg[4]_2\ : in STD_LOGIC;
    \gen_mux_rd[0].mux_rd_fall0_r_reg[0]_2\ : in STD_LOGIC;
    \gen_mux_rd[2].mux_rd_fall0_r_reg[2]_2\ : in STD_LOGIC;
    \gen_mux_rd[4].mux_rd_fall0_r_reg[4]_2\ : in STD_LOGIC;
    \gen_mux_rd[2].mux_rd_rise1_r_reg[2]_2\ : in STD_LOGIC;
    \gen_mux_rd[4].mux_rd_rise1_r_reg[4]_2\ : in STD_LOGIC;
    \gen_mux_rd[0].mux_rd_fall1_r_reg[0]_2\ : in STD_LOGIC;
    \gen_mux_rd[2].mux_rd_fall1_r_reg[2]_2\ : in STD_LOGIC;
    \gen_mux_rd[4].mux_rd_fall1_r_reg[4]_2\ : in STD_LOGIC;
    \gen_mux_rd[4].mux_rd_rise2_r_reg[4]_2\ : in STD_LOGIC;
    \gen_mux_rd[0].mux_rd_fall2_r_reg[0]_2\ : in STD_LOGIC;
    \gen_mux_rd[4].mux_rd_fall2_r_reg[4]_2\ : in STD_LOGIC;
    \gen_mux_rd[0].mux_rd_rise3_r_reg[0]_2\ : in STD_LOGIC;
    \gen_mux_rd[4].mux_rd_rise3_r_reg[4]_2\ : in STD_LOGIC;
    \out_fifo_i_75__5\ : in STD_LOGIC_VECTOR ( 71 downto 0 );
    COUNTERREADVAL : in STD_LOGIC_VECTOR ( 5 downto 0 );
    \pi_counter_read_val_reg[5]\ : in STD_LOGIC_VECTOR ( 5 downto 0 );
    calib_sel : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \pi_counter_read_val_reg[5]_0\ : in STD_LOGIC_VECTOR ( 5 downto 0 );
    \po_counter_read_val_reg[8]_2\ : in STD_LOGIC_VECTOR ( 8 downto 0 );
    \po_counter_read_val_reg[8]_3\ : in STD_LOGIC_VECTOR ( 8 downto 0 );
    \po_counter_read_val_reg[8]_4\ : in STD_LOGIC_VECTOR ( 8 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \mig_mig_7series_v4_2_ddr_byte_lane__parameterized0_26\ : entity is "mig_7series_v4_2_ddr_byte_lane";
end \mig_mig_7series_v4_2_ddr_byte_lane__parameterized0_26\;

architecture STRUCTURE of \mig_mig_7series_v4_2_ddr_byte_lane__parameterized0_26\ is
  signal \^a_rst_primitives_reg\ : STD_LOGIC;
  signal B_pi_counter_read_val : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal B_po_counter_read_val : STD_LOGIC_VECTOR ( 8 downto 0 );
  signal \^dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0\ : STD_LOGIC;
  signal if_d2 : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal if_d3 : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal if_d4 : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal if_d5 : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal if_d6 : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal if_d7 : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal if_d8 : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal if_d9 : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \if_empty_\ : STD_LOGIC;
  signal ififo_rst : STD_LOGIC;
  signal ififo_wr_enable : STD_LOGIC;
  signal \in_fifo_gen.in_fifo_n_0\ : STD_LOGIC;
  signal \in_fifo_gen.in_fifo_n_1\ : STD_LOGIC;
  signal \in_fifo_gen.in_fifo_n_3\ : STD_LOGIC;
  signal iserdes_clkdiv : STD_LOGIC;
  signal of_d1 : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal of_dqbus : STD_LOGIC_VECTOR ( 39 downto 0 );
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_0\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_2\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_3\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_4\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_5\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_6\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_7\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_8\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_9\ : STD_LOGIC;
  signal ofifo_rst : STD_LOGIC;
  signal oserdes_clk : STD_LOGIC;
  signal oserdes_clk_delayed : STD_LOGIC;
  signal oserdes_clkdiv : STD_LOGIC;
  signal oserdes_dq_ts : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal oserdes_dqs : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal oserdes_dqs_ts : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal out_fifo_n_0 : STD_LOGIC;
  signal out_fifo_n_1 : STD_LOGIC;
  signal out_fifo_n_2 : STD_LOGIC;
  signal out_fifo_n_3 : STD_LOGIC;
  signal \phaser_in_gen.phaser_in_n_1\ : STD_LOGIC;
  signal \phaser_in_gen.phaser_in_n_2\ : STD_LOGIC;
  signal \phaser_in_gen.phaser_in_n_5\ : STD_LOGIC;
  signal phaser_out_n_0 : STD_LOGIC;
  signal phaser_out_n_1 : STD_LOGIC;
  signal po_oserdes_rst : STD_LOGIC;
  signal po_rd_enable : STD_LOGIC;
  signal rd_data : STD_LOGIC_VECTOR ( 79 downto 0 );
  signal rd_data_r : STD_LOGIC_VECTOR ( 79 downto 12 );
  signal \NLW_in_fifo_gen.in_fifo_D5_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 4 );
  signal \NLW_in_fifo_gen.in_fifo_D6_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 4 );
  signal NLW_out_fifo_Q5_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 4 );
  signal NLW_out_fifo_Q6_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 4 );
  signal NLW_phaser_out_PHASEREFCLK_UNCONNECTED : STD_LOGIC;
  attribute syn_maxfan : string;
  attribute syn_maxfan of \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]\ : label is "3";
  attribute BOX_TYPE : string;
  attribute BOX_TYPE of \in_fifo_gen.in_fifo\ : label is "PRIMITIVE";
  attribute BOX_TYPE of out_fifo : label is "PRIMITIVE";
  attribute BOX_TYPE of \phaser_in_gen.phaser_in\ : label is "PRIMITIVE";
  attribute BOX_TYPE of phaser_out : label is "PRIMITIVE";
begin
  A_rst_primitives_reg <= \^a_rst_primitives_reg\;
  \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0\ <= \^dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0\;
ddr_byte_group_io: entity work.\mig_mig_7series_v4_2_ddr_byte_group_io__parameterized0_35\
     port map (
      A_rst_primitives => A_rst_primitives,
      CLKB0_7 => CLKB0_7,
      CTSBUS(0) => oserdes_dqs_ts(0),
      D2(3 downto 0) => if_d2(3 downto 0),
      D3(3 downto 0) => if_d3(3 downto 0),
      D4(3 downto 0) => if_d4(3 downto 0),
      D5(3 downto 0) => if_d5(3 downto 0),
      D6(3 downto 0) => if_d6(3 downto 0),
      D7(3 downto 0) => if_d7(3 downto 0),
      D8(3 downto 0) => if_d8(3 downto 0),
      D9(3 downto 0) => if_d9(3 downto 0),
      DQSBUS(1 downto 0) => oserdes_dqs(1 downto 0),
      DTSBUS(1 downto 0) => oserdes_dq_ts(1 downto 0),
      LD0_7 => LD0_7,
      \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]\ => \^a_rst_primitives_reg\,
      idelay_inc => idelay_inc,
      idelay_ld_rst_0 => idelay_ld_rst_0,
      idelay_ld_rst_reg_0 => \entry_cnt_reg[4]\,
      \input_[9].iserdes_dq_.iserdesdq_0\ => \input_[9].iserdes_dq_.iserdesdq\,
      iserdes_clkdiv => iserdes_clkdiv,
      mem_dq_in(7 downto 0) => mem_dq_in(7 downto 0),
      mem_dq_out(8 downto 0) => mem_dq_out(8 downto 0),
      mem_dq_ts(8 downto 0) => mem_dq_ts(8 downto 0),
      of_dqbus(35 downto 0) => of_dqbus(39 downto 4),
      oserdes_clk => oserdes_clk,
      oserdes_clk_delayed => oserdes_clk_delayed,
      oserdes_clkdiv => oserdes_clkdiv,
      out_dqs_5 => out_dqs_5,
      po_oserdes_rst => po_oserdes_rst,
      rst_r4 => rst_r4,
      ts_dqs_5 => ts_dqs_5
    );
\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => \if_empty_\,
      Q => \^dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0\,
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => rd_data(12),
      Q => rd_data_r(12),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => rd_data(13),
      Q => rd_data_r(13),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => rd_data(14),
      Q => rd_data_r(14),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => rd_data(15),
      Q => rd_data_r(15),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => rd_data(16),
      Q => rd_data_r(16),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => rd_data(17),
      Q => rd_data_r(17),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => rd_data(18),
      Q => rd_data_r(18),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => rd_data(19),
      Q => rd_data_r(19),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => rd_data(20),
      Q => rd_data_r(20),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => rd_data(21),
      Q => rd_data_r(21),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => rd_data(22),
      Q => rd_data_r(22),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => rd_data(23),
      Q => rd_data_r(23),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => rd_data(24),
      Q => rd_data_r(24),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => rd_data(25),
      Q => rd_data_r(25),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => rd_data(26),
      Q => rd_data_r(26),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => rd_data(27),
      Q => rd_data_r(27),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => rd_data(28),
      Q => rd_data_r(28),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => rd_data(29),
      Q => rd_data_r(29),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => rd_data(30),
      Q => rd_data_r(30),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => rd_data(31),
      Q => rd_data_r(31),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => rd_data(32),
      Q => rd_data_r(32),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => rd_data(33),
      Q => rd_data_r(33),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => rd_data(34),
      Q => rd_data_r(34),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => rd_data(35),
      Q => rd_data_r(35),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => rd_data(36),
      Q => rd_data_r(36),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => rd_data(37),
      Q => rd_data_r(37),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => rd_data(38),
      Q => rd_data_r(38),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => rd_data(39),
      Q => rd_data_r(39),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => rd_data(40),
      Q => rd_data_r(40),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => rd_data(41),
      Q => rd_data_r(41),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => rd_data(42),
      Q => rd_data_r(42),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => rd_data(43),
      Q => rd_data_r(43),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => rd_data(44),
      Q => rd_data_r(44),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => rd_data(45),
      Q => rd_data_r(45),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => rd_data(46),
      Q => rd_data_r(46),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => rd_data(47),
      Q => rd_data_r(47),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => rd_data(48),
      Q => rd_data_r(48),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => rd_data(49),
      Q => rd_data_r(49),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => rd_data(50),
      Q => rd_data_r(50),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => rd_data(51),
      Q => rd_data_r(51),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => rd_data(52),
      Q => rd_data_r(52),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => rd_data(53),
      Q => rd_data_r(53),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => rd_data(54),
      Q => rd_data_r(54),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => rd_data(55),
      Q => rd_data_r(55),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => rd_data(56),
      Q => rd_data_r(56),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => rd_data(57),
      Q => rd_data_r(57),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => rd_data(58),
      Q => rd_data_r(58),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => rd_data(59),
      Q => rd_data_r(59),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => rd_data(60),
      Q => rd_data_r(60),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => rd_data(61),
      Q => rd_data_r(61),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => rd_data(62),
      Q => rd_data_r(62),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => rd_data(63),
      Q => rd_data_r(63),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => rd_data(64),
      Q => rd_data_r(64),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => rd_data(65),
      Q => rd_data_r(65),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => rd_data(66),
      Q => rd_data_r(66),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => rd_data(67),
      Q => rd_data_r(67),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => rd_data(68),
      Q => rd_data_r(68),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => rd_data(69),
      Q => rd_data_r(69),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => rd_data(70),
      Q => rd_data_r(70),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => rd_data(71),
      Q => rd_data_r(71),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => rd_data(72),
      Q => rd_data_r(72),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => rd_data(73),
      Q => rd_data_r(73),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => rd_data(74),
      Q => rd_data_r(74),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => rd_data(75),
      Q => rd_data_r(75),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => rd_data(76),
      Q => rd_data_r(76),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => rd_data(77),
      Q => rd_data_r(77),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => rd_data(78),
      Q => rd_data_r(78),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => rd_data(79),
      Q => rd_data_r(79),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo\: entity work.mig_mig_7series_v4_2_ddr_if_post_fifo_36
     port map (
      Q(67 downto 0) => rd_data_r(79 downto 12),
      \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]\ => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1\,
      \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0\ => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0\,
      \gen_mux_rd[0].mux_rd_fall0_r_reg[0]\ => \gen_mux_rd[0].mux_rd_fall0_r_reg[0]\,
      \gen_mux_rd[0].mux_rd_fall0_r_reg[0]_0\ => \gen_mux_rd[0].mux_rd_fall0_r_reg[0]_0\,
      \gen_mux_rd[0].mux_rd_fall0_r_reg[0]_1\ => \gen_mux_rd[0].mux_rd_fall0_r_reg[0]_1\,
      \gen_mux_rd[0].mux_rd_fall0_r_reg[0]_2\ => \gen_mux_rd[0].mux_rd_fall0_r_reg[0]_2\,
      \gen_mux_rd[0].mux_rd_fall1_r_reg[0]\ => \gen_mux_rd[0].mux_rd_fall1_r_reg[0]\,
      \gen_mux_rd[0].mux_rd_fall1_r_reg[0]_0\ => \gen_mux_rd[0].mux_rd_fall1_r_reg[0]_0\,
      \gen_mux_rd[0].mux_rd_fall1_r_reg[0]_1\ => \gen_mux_rd[0].mux_rd_fall1_r_reg[0]_1\,
      \gen_mux_rd[0].mux_rd_fall1_r_reg[0]_2\ => \gen_mux_rd[0].mux_rd_fall1_r_reg[0]_2\,
      \gen_mux_rd[0].mux_rd_fall2_r_reg[0]\ => \gen_mux_rd[0].mux_rd_fall2_r_reg[0]\,
      \gen_mux_rd[0].mux_rd_fall2_r_reg[0]_0\ => \gen_mux_rd[0].mux_rd_fall2_r_reg[0]_0\,
      \gen_mux_rd[0].mux_rd_fall2_r_reg[0]_1\ => \gen_mux_rd[0].mux_rd_fall2_r_reg[0]_1\,
      \gen_mux_rd[0].mux_rd_fall2_r_reg[0]_2\ => \gen_mux_rd[0].mux_rd_fall2_r_reg[0]_2\,
      \gen_mux_rd[0].mux_rd_fall3_r_reg[0]\ => \gen_mux_rd[0].mux_rd_fall3_r_reg[0]\,
      \gen_mux_rd[0].mux_rd_fall3_r_reg[0]_0\ => \gen_mux_rd[0].mux_rd_fall3_r_reg[0]_0\,
      \gen_mux_rd[0].mux_rd_fall3_r_reg[0]_1\ => \gen_mux_rd[0].mux_rd_fall3_r_reg[0]_1\,
      \gen_mux_rd[0].mux_rd_fall3_r_reg[0]_2\ => \gen_mux_rd[0].mux_rd_fall3_r_reg[0]_2\,
      \gen_mux_rd[0].mux_rd_rise0_r_reg[0]\(1 downto 0) => \gen_mux_rd[0].mux_rd_rise0_r_reg[0]\(1 downto 0),
      \gen_mux_rd[0].mux_rd_rise0_r_reg[0]_0\ => \gen_mux_rd[0].mux_rd_rise0_r_reg[0]_0\,
      \gen_mux_rd[0].mux_rd_rise0_r_reg[0]_1\ => \gen_mux_rd[0].mux_rd_rise0_r_reg[0]_1\,
      \gen_mux_rd[0].mux_rd_rise0_r_reg[0]_2\ => \gen_mux_rd[0].mux_rd_rise0_r_reg[0]_2\,
      \gen_mux_rd[0].mux_rd_rise0_r_reg[0]_3\ => \gen_mux_rd[0].mux_rd_rise0_r_reg[0]_3\,
      \gen_mux_rd[0].mux_rd_rise1_r_reg[0]\ => \gen_mux_rd[0].mux_rd_rise1_r_reg[0]\,
      \gen_mux_rd[0].mux_rd_rise1_r_reg[0]_0\ => \gen_mux_rd[0].mux_rd_rise1_r_reg[0]_0\,
      \gen_mux_rd[0].mux_rd_rise1_r_reg[0]_1\ => \gen_mux_rd[0].mux_rd_rise1_r_reg[0]_1\,
      \gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2\ => \gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2\,
      \gen_mux_rd[0].mux_rd_rise2_r_reg[0]\ => \gen_mux_rd[0].mux_rd_rise2_r_reg[0]\,
      \gen_mux_rd[0].mux_rd_rise2_r_reg[0]_0\ => \gen_mux_rd[0].mux_rd_rise2_r_reg[0]_0\,
      \gen_mux_rd[0].mux_rd_rise2_r_reg[0]_1\ => \gen_mux_rd[0].mux_rd_rise2_r_reg[0]_1\,
      \gen_mux_rd[0].mux_rd_rise2_r_reg[0]_2\ => \gen_mux_rd[0].mux_rd_rise2_r_reg[0]_2\,
      \gen_mux_rd[0].mux_rd_rise3_r_reg[0]\ => \gen_mux_rd[0].mux_rd_rise3_r_reg[0]\,
      \gen_mux_rd[0].mux_rd_rise3_r_reg[0]_0\ => \gen_mux_rd[0].mux_rd_rise3_r_reg[0]_0\,
      \gen_mux_rd[0].mux_rd_rise3_r_reg[0]_1\ => \gen_mux_rd[0].mux_rd_rise3_r_reg[0]_1\,
      \gen_mux_rd[0].mux_rd_rise3_r_reg[0]_2\ => \gen_mux_rd[0].mux_rd_rise3_r_reg[0]_2\,
      \gen_mux_rd[1].mux_rd_fall0_r_reg[1]\ => \gen_mux_rd[1].mux_rd_fall0_r_reg[1]\,
      \gen_mux_rd[1].mux_rd_fall0_r_reg[1]_0\ => \gen_mux_rd[1].mux_rd_fall0_r_reg[1]_0\,
      \gen_mux_rd[1].mux_rd_fall0_r_reg[1]_1\ => \gen_mux_rd[1].mux_rd_fall0_r_reg[1]_1\,
      \gen_mux_rd[1].mux_rd_fall0_r_reg[1]_2\ => \gen_mux_rd[1].mux_rd_fall0_r_reg[1]_2\,
      \gen_mux_rd[1].mux_rd_fall1_r_reg[1]\ => \gen_mux_rd[1].mux_rd_fall1_r_reg[1]\,
      \gen_mux_rd[1].mux_rd_fall1_r_reg[1]_0\ => \gen_mux_rd[1].mux_rd_fall1_r_reg[1]_0\,
      \gen_mux_rd[1].mux_rd_fall1_r_reg[1]_1\ => \gen_mux_rd[1].mux_rd_fall1_r_reg[1]_1\,
      \gen_mux_rd[1].mux_rd_fall1_r_reg[1]_2\ => \gen_mux_rd[1].mux_rd_fall1_r_reg[1]_2\,
      \gen_mux_rd[1].mux_rd_fall2_r_reg[1]\ => \gen_mux_rd[1].mux_rd_fall2_r_reg[1]\,
      \gen_mux_rd[1].mux_rd_fall2_r_reg[1]_0\ => \gen_mux_rd[1].mux_rd_fall2_r_reg[1]_0\,
      \gen_mux_rd[1].mux_rd_fall2_r_reg[1]_1\ => \gen_mux_rd[1].mux_rd_fall2_r_reg[1]_1\,
      \gen_mux_rd[1].mux_rd_fall2_r_reg[1]_2\ => \gen_mux_rd[1].mux_rd_fall2_r_reg[1]_2\,
      \gen_mux_rd[1].mux_rd_fall3_r_reg[1]\ => \gen_mux_rd[1].mux_rd_fall3_r_reg[1]\,
      \gen_mux_rd[1].mux_rd_fall3_r_reg[1]_0\ => \gen_mux_rd[1].mux_rd_fall3_r_reg[1]_0\,
      \gen_mux_rd[1].mux_rd_fall3_r_reg[1]_1\ => \gen_mux_rd[1].mux_rd_fall3_r_reg[1]_1\,
      \gen_mux_rd[1].mux_rd_fall3_r_reg[1]_2\ => \gen_mux_rd[1].mux_rd_fall3_r_reg[1]_2\,
      \gen_mux_rd[1].mux_rd_rise0_r_reg[1]\ => \gen_mux_rd[1].mux_rd_rise0_r_reg[1]\,
      \gen_mux_rd[1].mux_rd_rise0_r_reg[1]_0\ => \gen_mux_rd[1].mux_rd_rise0_r_reg[1]_0\,
      \gen_mux_rd[1].mux_rd_rise0_r_reg[1]_1\ => \gen_mux_rd[1].mux_rd_rise0_r_reg[1]_1\,
      \gen_mux_rd[1].mux_rd_rise0_r_reg[1]_2\ => \gen_mux_rd[1].mux_rd_rise0_r_reg[1]_2\,
      \gen_mux_rd[1].mux_rd_rise0_r_reg[1]_3\ => \gen_mux_rd[1].mux_rd_rise0_r_reg[1]_3\,
      \gen_mux_rd[1].mux_rd_rise1_r_reg[1]\ => \gen_mux_rd[1].mux_rd_rise1_r_reg[1]\,
      \gen_mux_rd[1].mux_rd_rise1_r_reg[1]_0\ => \gen_mux_rd[1].mux_rd_rise1_r_reg[1]_0\,
      \gen_mux_rd[1].mux_rd_rise1_r_reg[1]_1\ => \gen_mux_rd[1].mux_rd_rise1_r_reg[1]_1\,
      \gen_mux_rd[1].mux_rd_rise1_r_reg[1]_2\ => \gen_mux_rd[1].mux_rd_rise1_r_reg[1]_2\,
      \gen_mux_rd[1].mux_rd_rise2_r_reg[1]\ => \gen_mux_rd[1].mux_rd_rise2_r_reg[1]\,
      \gen_mux_rd[1].mux_rd_rise2_r_reg[1]_0\ => \gen_mux_rd[1].mux_rd_rise2_r_reg[1]_0\,
      \gen_mux_rd[1].mux_rd_rise2_r_reg[1]_1\ => \gen_mux_rd[1].mux_rd_rise2_r_reg[1]_1\,
      \gen_mux_rd[1].mux_rd_rise2_r_reg[1]_2\ => \gen_mux_rd[1].mux_rd_rise2_r_reg[1]_2\,
      \gen_mux_rd[1].mux_rd_rise3_r_reg[1]\ => \gen_mux_rd[1].mux_rd_rise3_r_reg[1]\,
      \gen_mux_rd[1].mux_rd_rise3_r_reg[1]_0\ => \gen_mux_rd[1].mux_rd_rise3_r_reg[1]_0\,
      \gen_mux_rd[1].mux_rd_rise3_r_reg[1]_1\ => \gen_mux_rd[1].mux_rd_rise3_r_reg[1]_1\,
      \gen_mux_rd[1].mux_rd_rise3_r_reg[1]_2\ => \gen_mux_rd[1].mux_rd_rise3_r_reg[1]_2\,
      \gen_mux_rd[2].mux_rd_fall0_r_reg[2]\ => \gen_mux_rd[2].mux_rd_fall0_r_reg[2]\,
      \gen_mux_rd[2].mux_rd_fall0_r_reg[2]_0\ => \gen_mux_rd[2].mux_rd_fall0_r_reg[2]_0\,
      \gen_mux_rd[2].mux_rd_fall0_r_reg[2]_1\ => \gen_mux_rd[2].mux_rd_fall0_r_reg[2]_1\,
      \gen_mux_rd[2].mux_rd_fall0_r_reg[2]_2\ => \gen_mux_rd[2].mux_rd_fall0_r_reg[2]_2\,
      \gen_mux_rd[2].mux_rd_fall1_r_reg[2]\ => \gen_mux_rd[2].mux_rd_fall1_r_reg[2]\,
      \gen_mux_rd[2].mux_rd_fall1_r_reg[2]_0\ => \gen_mux_rd[2].mux_rd_fall1_r_reg[2]_0\,
      \gen_mux_rd[2].mux_rd_fall1_r_reg[2]_1\ => \gen_mux_rd[2].mux_rd_fall1_r_reg[2]_1\,
      \gen_mux_rd[2].mux_rd_fall1_r_reg[2]_2\ => \gen_mux_rd[2].mux_rd_fall1_r_reg[2]_2\,
      \gen_mux_rd[2].mux_rd_fall2_r_reg[2]\ => \gen_mux_rd[2].mux_rd_fall2_r_reg[2]\,
      \gen_mux_rd[2].mux_rd_fall2_r_reg[2]_0\ => \gen_mux_rd[2].mux_rd_fall2_r_reg[2]_0\,
      \gen_mux_rd[2].mux_rd_fall2_r_reg[2]_1\ => \gen_mux_rd[2].mux_rd_fall2_r_reg[2]_1\,
      \gen_mux_rd[2].mux_rd_fall2_r_reg[2]_2\ => \gen_mux_rd[2].mux_rd_fall2_r_reg[2]_2\,
      \gen_mux_rd[2].mux_rd_fall3_r_reg[2]\ => \gen_mux_rd[2].mux_rd_fall3_r_reg[2]\,
      \gen_mux_rd[2].mux_rd_fall3_r_reg[2]_0\ => \gen_mux_rd[2].mux_rd_fall3_r_reg[2]_0\,
      \gen_mux_rd[2].mux_rd_fall3_r_reg[2]_1\ => \gen_mux_rd[2].mux_rd_fall3_r_reg[2]_1\,
      \gen_mux_rd[2].mux_rd_fall3_r_reg[2]_2\ => \gen_mux_rd[2].mux_rd_fall3_r_reg[2]_2\,
      \gen_mux_rd[2].mux_rd_rise0_r_reg[2]\ => \gen_mux_rd[2].mux_rd_rise0_r_reg[2]\,
      \gen_mux_rd[2].mux_rd_rise0_r_reg[2]_0\ => \gen_mux_rd[2].mux_rd_rise0_r_reg[2]_0\,
      \gen_mux_rd[2].mux_rd_rise0_r_reg[2]_1\ => \gen_mux_rd[2].mux_rd_rise0_r_reg[2]_1\,
      \gen_mux_rd[2].mux_rd_rise0_r_reg[2]_2\ => \gen_mux_rd[2].mux_rd_rise0_r_reg[2]_2\,
      \gen_mux_rd[2].mux_rd_rise1_r_reg[2]\ => \gen_mux_rd[2].mux_rd_rise1_r_reg[2]\,
      \gen_mux_rd[2].mux_rd_rise1_r_reg[2]_0\ => \gen_mux_rd[2].mux_rd_rise1_r_reg[2]_0\,
      \gen_mux_rd[2].mux_rd_rise1_r_reg[2]_1\ => \gen_mux_rd[2].mux_rd_rise1_r_reg[2]_1\,
      \gen_mux_rd[2].mux_rd_rise1_r_reg[2]_2\ => \gen_mux_rd[2].mux_rd_rise1_r_reg[2]_2\,
      \gen_mux_rd[2].mux_rd_rise2_r_reg[2]\ => \gen_mux_rd[2].mux_rd_rise2_r_reg[2]\,
      \gen_mux_rd[2].mux_rd_rise2_r_reg[2]_0\ => \gen_mux_rd[2].mux_rd_rise2_r_reg[2]_0\,
      \gen_mux_rd[2].mux_rd_rise2_r_reg[2]_1\ => \gen_mux_rd[2].mux_rd_rise2_r_reg[2]_1\,
      \gen_mux_rd[2].mux_rd_rise2_r_reg[2]_2\ => \gen_mux_rd[2].mux_rd_rise2_r_reg[2]_2\,
      \gen_mux_rd[2].mux_rd_rise3_r_reg[2]\ => \gen_mux_rd[2].mux_rd_rise3_r_reg[2]\,
      \gen_mux_rd[2].mux_rd_rise3_r_reg[2]_0\ => \gen_mux_rd[2].mux_rd_rise3_r_reg[2]_0\,
      \gen_mux_rd[2].mux_rd_rise3_r_reg[2]_1\ => \gen_mux_rd[2].mux_rd_rise3_r_reg[2]_1\,
      \gen_mux_rd[2].mux_rd_rise3_r_reg[2]_2\ => \gen_mux_rd[2].mux_rd_rise3_r_reg[2]_2\,
      \gen_mux_rd[3].mux_rd_fall0_r_reg[3]\ => \gen_mux_rd[3].mux_rd_fall0_r_reg[3]\,
      \gen_mux_rd[3].mux_rd_fall0_r_reg[3]_0\ => \gen_mux_rd[3].mux_rd_fall0_r_reg[3]_0\,
      \gen_mux_rd[3].mux_rd_fall0_r_reg[3]_1\ => \gen_mux_rd[3].mux_rd_fall0_r_reg[3]_1\,
      \gen_mux_rd[3].mux_rd_fall0_r_reg[3]_2\ => \gen_mux_rd[3].mux_rd_fall0_r_reg[3]_2\,
      \gen_mux_rd[3].mux_rd_fall1_r_reg[3]\ => \gen_mux_rd[3].mux_rd_fall1_r_reg[3]\,
      \gen_mux_rd[3].mux_rd_fall1_r_reg[3]_0\ => \gen_mux_rd[3].mux_rd_fall1_r_reg[3]_0\,
      \gen_mux_rd[3].mux_rd_fall1_r_reg[3]_1\ => \gen_mux_rd[3].mux_rd_fall1_r_reg[3]_1\,
      \gen_mux_rd[3].mux_rd_fall1_r_reg[3]_2\ => \gen_mux_rd[3].mux_rd_fall1_r_reg[3]_2\,
      \gen_mux_rd[3].mux_rd_fall2_r_reg[3]\ => \gen_mux_rd[3].mux_rd_fall2_r_reg[3]\,
      \gen_mux_rd[3].mux_rd_fall2_r_reg[3]_0\ => \gen_mux_rd[3].mux_rd_fall2_r_reg[3]_0\,
      \gen_mux_rd[3].mux_rd_fall2_r_reg[3]_1\ => \gen_mux_rd[3].mux_rd_fall2_r_reg[3]_1\,
      \gen_mux_rd[3].mux_rd_fall2_r_reg[3]_2\ => \gen_mux_rd[3].mux_rd_fall2_r_reg[3]_2\,
      \gen_mux_rd[3].mux_rd_fall3_r_reg[3]\ => \gen_mux_rd[3].mux_rd_fall3_r_reg[3]\,
      \gen_mux_rd[3].mux_rd_fall3_r_reg[3]_0\ => \gen_mux_rd[3].mux_rd_fall3_r_reg[3]_0\,
      \gen_mux_rd[3].mux_rd_fall3_r_reg[3]_1\ => \gen_mux_rd[3].mux_rd_fall3_r_reg[3]_1\,
      \gen_mux_rd[3].mux_rd_fall3_r_reg[3]_2\ => \gen_mux_rd[3].mux_rd_fall3_r_reg[3]_2\,
      \gen_mux_rd[3].mux_rd_rise0_r_reg[3]\ => \gen_mux_rd[3].mux_rd_rise0_r_reg[3]\,
      \gen_mux_rd[3].mux_rd_rise0_r_reg[3]_0\ => \gen_mux_rd[3].mux_rd_rise0_r_reg[3]_0\,
      \gen_mux_rd[3].mux_rd_rise0_r_reg[3]_1\ => \gen_mux_rd[3].mux_rd_rise0_r_reg[3]_1\,
      \gen_mux_rd[3].mux_rd_rise0_r_reg[3]_2\ => \gen_mux_rd[3].mux_rd_rise0_r_reg[3]_2\,
      \gen_mux_rd[3].mux_rd_rise1_r_reg[3]\ => \gen_mux_rd[3].mux_rd_rise1_r_reg[3]\,
      \gen_mux_rd[3].mux_rd_rise1_r_reg[3]_0\ => \gen_mux_rd[3].mux_rd_rise1_r_reg[3]_0\,
      \gen_mux_rd[3].mux_rd_rise1_r_reg[3]_1\ => \gen_mux_rd[3].mux_rd_rise1_r_reg[3]_1\,
      \gen_mux_rd[3].mux_rd_rise1_r_reg[3]_2\ => \gen_mux_rd[3].mux_rd_rise1_r_reg[3]_2\,
      \gen_mux_rd[3].mux_rd_rise2_r_reg[3]\ => \gen_mux_rd[3].mux_rd_rise2_r_reg[3]\,
      \gen_mux_rd[3].mux_rd_rise2_r_reg[3]_0\ => \gen_mux_rd[3].mux_rd_rise2_r_reg[3]_0\,
      \gen_mux_rd[3].mux_rd_rise2_r_reg[3]_1\ => \gen_mux_rd[3].mux_rd_rise2_r_reg[3]_1\,
      \gen_mux_rd[3].mux_rd_rise2_r_reg[3]_2\ => \gen_mux_rd[3].mux_rd_rise2_r_reg[3]_2\,
      \gen_mux_rd[3].mux_rd_rise3_r_reg[3]\ => \gen_mux_rd[3].mux_rd_rise3_r_reg[3]\,
      \gen_mux_rd[3].mux_rd_rise3_r_reg[3]_0\ => \gen_mux_rd[3].mux_rd_rise3_r_reg[3]_0\,
      \gen_mux_rd[3].mux_rd_rise3_r_reg[3]_1\ => \gen_mux_rd[3].mux_rd_rise3_r_reg[3]_1\,
      \gen_mux_rd[3].mux_rd_rise3_r_reg[3]_2\ => \gen_mux_rd[3].mux_rd_rise3_r_reg[3]_2\,
      \gen_mux_rd[4].mux_rd_fall0_r_reg[4]\ => \gen_mux_rd[4].mux_rd_fall0_r_reg[4]\,
      \gen_mux_rd[4].mux_rd_fall0_r_reg[4]_0\ => \gen_mux_rd[4].mux_rd_fall0_r_reg[4]_0\,
      \gen_mux_rd[4].mux_rd_fall0_r_reg[4]_1\ => \gen_mux_rd[4].mux_rd_fall0_r_reg[4]_1\,
      \gen_mux_rd[4].mux_rd_fall0_r_reg[4]_2\ => \gen_mux_rd[4].mux_rd_fall0_r_reg[4]_2\,
      \gen_mux_rd[4].mux_rd_fall1_r_reg[4]\ => \gen_mux_rd[4].mux_rd_fall1_r_reg[4]\,
      \gen_mux_rd[4].mux_rd_fall1_r_reg[4]_0\ => \gen_mux_rd[4].mux_rd_fall1_r_reg[4]_0\,
      \gen_mux_rd[4].mux_rd_fall1_r_reg[4]_1\ => \gen_mux_rd[4].mux_rd_fall1_r_reg[4]_1\,
      \gen_mux_rd[4].mux_rd_fall1_r_reg[4]_2\ => \gen_mux_rd[4].mux_rd_fall1_r_reg[4]_2\,
      \gen_mux_rd[4].mux_rd_fall2_r_reg[4]\ => \gen_mux_rd[4].mux_rd_fall2_r_reg[4]\,
      \gen_mux_rd[4].mux_rd_fall2_r_reg[4]_0\ => \gen_mux_rd[4].mux_rd_fall2_r_reg[4]_0\,
      \gen_mux_rd[4].mux_rd_fall2_r_reg[4]_1\ => \gen_mux_rd[4].mux_rd_fall2_r_reg[4]_1\,
      \gen_mux_rd[4].mux_rd_fall2_r_reg[4]_2\ => \gen_mux_rd[4].mux_rd_fall2_r_reg[4]_2\,
      \gen_mux_rd[4].mux_rd_fall3_r_reg[4]\ => \gen_mux_rd[4].mux_rd_fall3_r_reg[4]\,
      \gen_mux_rd[4].mux_rd_fall3_r_reg[4]_0\ => \gen_mux_rd[4].mux_rd_fall3_r_reg[4]_0\,
      \gen_mux_rd[4].mux_rd_fall3_r_reg[4]_1\ => \gen_mux_rd[4].mux_rd_fall3_r_reg[4]_1\,
      \gen_mux_rd[4].mux_rd_fall3_r_reg[4]_2\ => \gen_mux_rd[4].mux_rd_fall3_r_reg[4]_2\,
      \gen_mux_rd[4].mux_rd_rise0_r_reg[4]\ => \gen_mux_rd[4].mux_rd_rise0_r_reg[4]\,
      \gen_mux_rd[4].mux_rd_rise0_r_reg[4]_0\ => \gen_mux_rd[4].mux_rd_rise0_r_reg[4]_0\,
      \gen_mux_rd[4].mux_rd_rise0_r_reg[4]_1\ => \gen_mux_rd[4].mux_rd_rise0_r_reg[4]_1\,
      \gen_mux_rd[4].mux_rd_rise0_r_reg[4]_2\ => \gen_mux_rd[4].mux_rd_rise0_r_reg[4]_2\,
      \gen_mux_rd[4].mux_rd_rise1_r_reg[4]\ => \gen_mux_rd[4].mux_rd_rise1_r_reg[4]\,
      \gen_mux_rd[4].mux_rd_rise1_r_reg[4]_0\ => \gen_mux_rd[4].mux_rd_rise1_r_reg[4]_0\,
      \gen_mux_rd[4].mux_rd_rise1_r_reg[4]_1\ => \gen_mux_rd[4].mux_rd_rise1_r_reg[4]_1\,
      \gen_mux_rd[4].mux_rd_rise1_r_reg[4]_2\ => \gen_mux_rd[4].mux_rd_rise1_r_reg[4]_2\,
      \gen_mux_rd[4].mux_rd_rise2_r_reg[4]\ => \gen_mux_rd[4].mux_rd_rise2_r_reg[4]\,
      \gen_mux_rd[4].mux_rd_rise2_r_reg[4]_0\ => \gen_mux_rd[4].mux_rd_rise2_r_reg[4]_0\,
      \gen_mux_rd[4].mux_rd_rise2_r_reg[4]_1\ => \gen_mux_rd[4].mux_rd_rise2_r_reg[4]_1\,
      \gen_mux_rd[4].mux_rd_rise2_r_reg[4]_2\ => \gen_mux_rd[4].mux_rd_rise2_r_reg[4]_2\,
      \gen_mux_rd[4].mux_rd_rise3_r_reg[4]\ => \gen_mux_rd[4].mux_rd_rise3_r_reg[4]\,
      \gen_mux_rd[4].mux_rd_rise3_r_reg[4]_0\ => \gen_mux_rd[4].mux_rd_rise3_r_reg[4]_0\,
      \gen_mux_rd[4].mux_rd_rise3_r_reg[4]_1\ => \gen_mux_rd[4].mux_rd_rise3_r_reg[4]_1\,
      \gen_mux_rd[4].mux_rd_rise3_r_reg[4]_2\ => \gen_mux_rd[4].mux_rd_rise3_r_reg[4]_2\,
      \gen_mux_rd[5].mux_rd_fall0_r_reg[5]\ => \gen_mux_rd[5].mux_rd_fall0_r_reg[5]\,
      \gen_mux_rd[5].mux_rd_fall0_r_reg[5]_0\ => \gen_mux_rd[5].mux_rd_fall0_r_reg[5]_0\,
      \gen_mux_rd[5].mux_rd_fall0_r_reg[5]_1\ => \gen_mux_rd[5].mux_rd_fall0_r_reg[5]_1\,
      \gen_mux_rd[5].mux_rd_fall0_r_reg[5]_2\ => \gen_mux_rd[5].mux_rd_fall0_r_reg[5]_2\,
      \gen_mux_rd[5].mux_rd_fall1_r_reg[5]\ => \gen_mux_rd[5].mux_rd_fall1_r_reg[5]\,
      \gen_mux_rd[5].mux_rd_fall1_r_reg[5]_0\ => \gen_mux_rd[5].mux_rd_fall1_r_reg[5]_0\,
      \gen_mux_rd[5].mux_rd_fall1_r_reg[5]_1\ => \gen_mux_rd[5].mux_rd_fall1_r_reg[5]_1\,
      \gen_mux_rd[5].mux_rd_fall1_r_reg[5]_2\ => \gen_mux_rd[5].mux_rd_fall1_r_reg[5]_2\,
      \gen_mux_rd[5].mux_rd_fall2_r_reg[5]\ => \gen_mux_rd[5].mux_rd_fall2_r_reg[5]\,
      \gen_mux_rd[5].mux_rd_fall2_r_reg[5]_0\ => \gen_mux_rd[5].mux_rd_fall2_r_reg[5]_0\,
      \gen_mux_rd[5].mux_rd_fall2_r_reg[5]_1\ => \gen_mux_rd[5].mux_rd_fall2_r_reg[5]_1\,
      \gen_mux_rd[5].mux_rd_fall2_r_reg[5]_2\ => \gen_mux_rd[5].mux_rd_fall2_r_reg[5]_2\,
      \gen_mux_rd[5].mux_rd_fall3_r_reg[5]\ => \gen_mux_rd[5].mux_rd_fall3_r_reg[5]\,
      \gen_mux_rd[5].mux_rd_fall3_r_reg[5]_0\ => \gen_mux_rd[5].mux_rd_fall3_r_reg[5]_0\,
      \gen_mux_rd[5].mux_rd_fall3_r_reg[5]_1\ => \gen_mux_rd[5].mux_rd_fall3_r_reg[5]_1\,
      \gen_mux_rd[5].mux_rd_fall3_r_reg[5]_2\ => \gen_mux_rd[5].mux_rd_fall3_r_reg[5]_2\,
      \gen_mux_rd[5].mux_rd_rise0_r_reg[5]\ => \gen_mux_rd[5].mux_rd_rise0_r_reg[5]\,
      \gen_mux_rd[5].mux_rd_rise0_r_reg[5]_0\ => \gen_mux_rd[5].mux_rd_rise0_r_reg[5]_0\,
      \gen_mux_rd[5].mux_rd_rise0_r_reg[5]_1\ => \gen_mux_rd[5].mux_rd_rise0_r_reg[5]_1\,
      \gen_mux_rd[5].mux_rd_rise0_r_reg[5]_2\ => \gen_mux_rd[5].mux_rd_rise0_r_reg[5]_2\,
      \gen_mux_rd[5].mux_rd_rise1_r_reg[5]\ => \gen_mux_rd[5].mux_rd_rise1_r_reg[5]\,
      \gen_mux_rd[5].mux_rd_rise1_r_reg[5]_0\ => \gen_mux_rd[5].mux_rd_rise1_r_reg[5]_0\,
      \gen_mux_rd[5].mux_rd_rise1_r_reg[5]_1\ => \gen_mux_rd[5].mux_rd_rise1_r_reg[5]_1\,
      \gen_mux_rd[5].mux_rd_rise1_r_reg[5]_2\ => \gen_mux_rd[5].mux_rd_rise1_r_reg[5]_2\,
      \gen_mux_rd[5].mux_rd_rise2_r_reg[5]\ => \gen_mux_rd[5].mux_rd_rise2_r_reg[5]\,
      \gen_mux_rd[5].mux_rd_rise2_r_reg[5]_0\ => \gen_mux_rd[5].mux_rd_rise2_r_reg[5]_0\,
      \gen_mux_rd[5].mux_rd_rise2_r_reg[5]_1\ => \gen_mux_rd[5].mux_rd_rise2_r_reg[5]_1\,
      \gen_mux_rd[5].mux_rd_rise2_r_reg[5]_2\ => \gen_mux_rd[5].mux_rd_rise2_r_reg[5]_2\,
      \gen_mux_rd[5].mux_rd_rise3_r_reg[5]\ => \gen_mux_rd[5].mux_rd_rise3_r_reg[5]\,
      \gen_mux_rd[5].mux_rd_rise3_r_reg[5]_0\ => \gen_mux_rd[5].mux_rd_rise3_r_reg[5]_0\,
      \gen_mux_rd[5].mux_rd_rise3_r_reg[5]_1\ => \gen_mux_rd[5].mux_rd_rise3_r_reg[5]_1\,
      \gen_mux_rd[5].mux_rd_rise3_r_reg[5]_2\ => \gen_mux_rd[5].mux_rd_rise3_r_reg[5]_2\,
      \gen_mux_rd[6].mux_rd_fall0_r_reg[6]\ => \gen_mux_rd[6].mux_rd_fall0_r_reg[6]\,
      \gen_mux_rd[6].mux_rd_fall0_r_reg[6]_0\ => \gen_mux_rd[6].mux_rd_fall0_r_reg[6]_0\,
      \gen_mux_rd[6].mux_rd_fall0_r_reg[6]_1\ => \gen_mux_rd[6].mux_rd_fall0_r_reg[6]_1\,
      \gen_mux_rd[6].mux_rd_fall0_r_reg[6]_2\ => \gen_mux_rd[6].mux_rd_fall0_r_reg[6]_2\,
      \gen_mux_rd[6].mux_rd_fall1_r_reg[6]\ => \gen_mux_rd[6].mux_rd_fall1_r_reg[6]\,
      \gen_mux_rd[6].mux_rd_fall1_r_reg[6]_0\ => \gen_mux_rd[6].mux_rd_fall1_r_reg[6]_0\,
      \gen_mux_rd[6].mux_rd_fall1_r_reg[6]_1\ => \gen_mux_rd[6].mux_rd_fall1_r_reg[6]_1\,
      \gen_mux_rd[6].mux_rd_fall1_r_reg[6]_2\ => \gen_mux_rd[6].mux_rd_fall1_r_reg[6]_2\,
      \gen_mux_rd[6].mux_rd_fall2_r_reg[6]\ => \gen_mux_rd[6].mux_rd_fall2_r_reg[6]\,
      \gen_mux_rd[6].mux_rd_fall2_r_reg[6]_0\ => \gen_mux_rd[6].mux_rd_fall2_r_reg[6]_0\,
      \gen_mux_rd[6].mux_rd_fall2_r_reg[6]_1\ => \gen_mux_rd[6].mux_rd_fall2_r_reg[6]_1\,
      \gen_mux_rd[6].mux_rd_fall2_r_reg[6]_2\ => \gen_mux_rd[6].mux_rd_fall2_r_reg[6]_2\,
      \gen_mux_rd[6].mux_rd_fall3_r_reg[6]\ => \gen_mux_rd[6].mux_rd_fall3_r_reg[6]\,
      \gen_mux_rd[6].mux_rd_fall3_r_reg[6]_0\ => \gen_mux_rd[6].mux_rd_fall3_r_reg[6]_0\,
      \gen_mux_rd[6].mux_rd_fall3_r_reg[6]_1\ => \gen_mux_rd[6].mux_rd_fall3_r_reg[6]_1\,
      \gen_mux_rd[6].mux_rd_fall3_r_reg[6]_2\ => \gen_mux_rd[6].mux_rd_fall3_r_reg[6]_2\,
      \gen_mux_rd[6].mux_rd_rise0_r_reg[6]\ => \gen_mux_rd[6].mux_rd_rise0_r_reg[6]\,
      \gen_mux_rd[6].mux_rd_rise0_r_reg[6]_0\ => \gen_mux_rd[6].mux_rd_rise0_r_reg[6]_0\,
      \gen_mux_rd[6].mux_rd_rise0_r_reg[6]_1\ => \gen_mux_rd[6].mux_rd_rise0_r_reg[6]_1\,
      \gen_mux_rd[6].mux_rd_rise0_r_reg[6]_2\ => \gen_mux_rd[6].mux_rd_rise0_r_reg[6]_2\,
      \gen_mux_rd[6].mux_rd_rise1_r_reg[6]\ => \gen_mux_rd[6].mux_rd_rise1_r_reg[6]\,
      \gen_mux_rd[6].mux_rd_rise1_r_reg[6]_0\ => \gen_mux_rd[6].mux_rd_rise1_r_reg[6]_0\,
      \gen_mux_rd[6].mux_rd_rise1_r_reg[6]_1\ => \gen_mux_rd[6].mux_rd_rise1_r_reg[6]_1\,
      \gen_mux_rd[6].mux_rd_rise1_r_reg[6]_2\ => \gen_mux_rd[6].mux_rd_rise1_r_reg[6]_2\,
      \gen_mux_rd[6].mux_rd_rise2_r_reg[6]\ => \gen_mux_rd[6].mux_rd_rise2_r_reg[6]\,
      \gen_mux_rd[6].mux_rd_rise2_r_reg[6]_0\ => \gen_mux_rd[6].mux_rd_rise2_r_reg[6]_0\,
      \gen_mux_rd[6].mux_rd_rise2_r_reg[6]_1\ => \gen_mux_rd[6].mux_rd_rise2_r_reg[6]_1\,
      \gen_mux_rd[6].mux_rd_rise2_r_reg[6]_2\ => \gen_mux_rd[6].mux_rd_rise2_r_reg[6]_2\,
      \gen_mux_rd[6].mux_rd_rise3_r_reg[6]\ => \gen_mux_rd[6].mux_rd_rise3_r_reg[6]\,
      \gen_mux_rd[6].mux_rd_rise3_r_reg[6]_0\ => \gen_mux_rd[6].mux_rd_rise3_r_reg[6]_0\,
      \gen_mux_rd[6].mux_rd_rise3_r_reg[6]_1\ => \gen_mux_rd[6].mux_rd_rise3_r_reg[6]_1\,
      \gen_mux_rd[6].mux_rd_rise3_r_reg[6]_2\ => \gen_mux_rd[6].mux_rd_rise3_r_reg[6]_2\,
      \gen_mux_rd[7].mux_rd_fall0_r_reg[7]\ => \gen_mux_rd[7].mux_rd_fall0_r_reg[7]\,
      \gen_mux_rd[7].mux_rd_fall0_r_reg[7]_0\ => \gen_mux_rd[7].mux_rd_fall0_r_reg[7]_0\,
      \gen_mux_rd[7].mux_rd_fall0_r_reg[7]_1\ => \gen_mux_rd[7].mux_rd_fall0_r_reg[7]_1\,
      \gen_mux_rd[7].mux_rd_fall0_r_reg[7]_2\ => \gen_mux_rd[7].mux_rd_fall0_r_reg[7]_2\,
      \gen_mux_rd[7].mux_rd_fall1_r_reg[7]\ => \gen_mux_rd[7].mux_rd_fall1_r_reg[7]\,
      \gen_mux_rd[7].mux_rd_fall1_r_reg[7]_0\ => \gen_mux_rd[7].mux_rd_fall1_r_reg[7]_0\,
      \gen_mux_rd[7].mux_rd_fall1_r_reg[7]_1\ => \gen_mux_rd[7].mux_rd_fall1_r_reg[7]_1\,
      \gen_mux_rd[7].mux_rd_fall1_r_reg[7]_2\ => \gen_mux_rd[7].mux_rd_fall1_r_reg[7]_2\,
      \gen_mux_rd[7].mux_rd_fall2_r_reg[7]\ => \gen_mux_rd[7].mux_rd_fall2_r_reg[7]\,
      \gen_mux_rd[7].mux_rd_fall2_r_reg[7]_0\ => \gen_mux_rd[7].mux_rd_fall2_r_reg[7]_0\,
      \gen_mux_rd[7].mux_rd_fall2_r_reg[7]_1\ => \gen_mux_rd[7].mux_rd_fall2_r_reg[7]_1\,
      \gen_mux_rd[7].mux_rd_fall2_r_reg[7]_2\ => \gen_mux_rd[7].mux_rd_fall2_r_reg[7]_2\,
      \gen_mux_rd[7].mux_rd_fall3_r_reg[7]\ => \gen_mux_rd[7].mux_rd_fall3_r_reg[7]\,
      \gen_mux_rd[7].mux_rd_fall3_r_reg[7]_0\ => \gen_mux_rd[7].mux_rd_fall3_r_reg[7]_0\,
      \gen_mux_rd[7].mux_rd_fall3_r_reg[7]_1\ => \gen_mux_rd[7].mux_rd_fall3_r_reg[7]_1\,
      \gen_mux_rd[7].mux_rd_fall3_r_reg[7]_2\ => \gen_mux_rd[7].mux_rd_fall3_r_reg[7]_2\,
      \gen_mux_rd[7].mux_rd_rise0_r_reg[7]\ => \gen_mux_rd[7].mux_rd_rise0_r_reg[7]\,
      \gen_mux_rd[7].mux_rd_rise0_r_reg[7]_0\ => \gen_mux_rd[7].mux_rd_rise0_r_reg[7]_0\,
      \gen_mux_rd[7].mux_rd_rise0_r_reg[7]_1\ => \gen_mux_rd[7].mux_rd_rise0_r_reg[7]_1\,
      \gen_mux_rd[7].mux_rd_rise0_r_reg[7]_2\ => \gen_mux_rd[7].mux_rd_rise0_r_reg[7]_2\,
      \gen_mux_rd[7].mux_rd_rise1_r_reg[7]\ => \gen_mux_rd[7].mux_rd_rise1_r_reg[7]\,
      \gen_mux_rd[7].mux_rd_rise1_r_reg[7]_0\ => \gen_mux_rd[7].mux_rd_rise1_r_reg[7]_0\,
      \gen_mux_rd[7].mux_rd_rise1_r_reg[7]_1\ => \gen_mux_rd[7].mux_rd_rise1_r_reg[7]_1\,
      \gen_mux_rd[7].mux_rd_rise1_r_reg[7]_2\ => \gen_mux_rd[7].mux_rd_rise1_r_reg[7]_2\,
      \gen_mux_rd[7].mux_rd_rise2_r_reg[7]\ => \gen_mux_rd[7].mux_rd_rise2_r_reg[7]\,
      \gen_mux_rd[7].mux_rd_rise2_r_reg[7]_0\ => \gen_mux_rd[7].mux_rd_rise2_r_reg[7]_0\,
      \gen_mux_rd[7].mux_rd_rise2_r_reg[7]_1\ => \gen_mux_rd[7].mux_rd_rise2_r_reg[7]_1\,
      \gen_mux_rd[7].mux_rd_rise2_r_reg[7]_2\ => \gen_mux_rd[7].mux_rd_rise2_r_reg[7]_2\,
      \gen_mux_rd[7].mux_rd_rise3_r_reg[7]\ => \gen_mux_rd[7].mux_rd_rise3_r_reg[7]\,
      \gen_mux_rd[7].mux_rd_rise3_r_reg[7]_0\ => \gen_mux_rd[7].mux_rd_rise3_r_reg[7]_0\,
      \gen_mux_rd[7].mux_rd_rise3_r_reg[7]_1\ => \gen_mux_rd[7].mux_rd_rise3_r_reg[7]_1\,
      \gen_mux_rd[7].mux_rd_rise3_r_reg[7]_2\ => \gen_mux_rd[7].mux_rd_rise3_r_reg[7]_2\,
      ififo_rst => ififo_rst,
      my_empty(0) => my_empty(0),
      \my_empty_reg[4]_0\ => \my_empty_reg[4]\,
      \my_empty_reg[4]_1\(0) => \my_empty_reg[4]_0\(0),
      \my_full_reg[1]_0\ => \my_full_reg[1]\,
      \rd_mux_sel_r_reg[2]\ => \rd_mux_sel_r_reg[2]\,
      \rd_mux_sel_r_reg[2]_0\ => \rd_mux_sel_r_reg[2]_0\,
      \rd_mux_sel_r_reg[2]_1\ => \rd_mux_sel_r_reg[2]_1\,
      \rd_mux_sel_r_reg[2]_10\ => \rd_mux_sel_r_reg[2]_10\,
      \rd_mux_sel_r_reg[2]_11\ => \rd_mux_sel_r_reg[2]_11\,
      \rd_mux_sel_r_reg[2]_12\ => \rd_mux_sel_r_reg[2]_12\,
      \rd_mux_sel_r_reg[2]_13\ => \rd_mux_sel_r_reg[2]_13\,
      \rd_mux_sel_r_reg[2]_14\ => \rd_mux_sel_r_reg[2]_14\,
      \rd_mux_sel_r_reg[2]_15\ => \rd_mux_sel_r_reg[2]_15\,
      \rd_mux_sel_r_reg[2]_16\ => \rd_mux_sel_r_reg[2]_16\,
      \rd_mux_sel_r_reg[2]_17\ => \rd_mux_sel_r_reg[2]_17\,
      \rd_mux_sel_r_reg[2]_18\ => \rd_mux_sel_r_reg[2]_18\,
      \rd_mux_sel_r_reg[2]_19\ => \rd_mux_sel_r_reg[2]_19\,
      \rd_mux_sel_r_reg[2]_2\ => \rd_mux_sel_r_reg[2]_2\,
      \rd_mux_sel_r_reg[2]_20\ => \rd_mux_sel_r_reg[2]_20\,
      \rd_mux_sel_r_reg[2]_21\ => \rd_mux_sel_r_reg[2]_21\,
      \rd_mux_sel_r_reg[2]_22\ => \rd_mux_sel_r_reg[2]_22\,
      \rd_mux_sel_r_reg[2]_23\ => \rd_mux_sel_r_reg[2]_23\,
      \rd_mux_sel_r_reg[2]_24\ => \rd_mux_sel_r_reg[2]_24\,
      \rd_mux_sel_r_reg[2]_25\ => \rd_mux_sel_r_reg[2]_25\,
      \rd_mux_sel_r_reg[2]_26\ => \rd_mux_sel_r_reg[2]_26\,
      \rd_mux_sel_r_reg[2]_27\ => \rd_mux_sel_r_reg[2]_27\,
      \rd_mux_sel_r_reg[2]_28\ => \rd_mux_sel_r_reg[2]_28\,
      \rd_mux_sel_r_reg[2]_29\ => \rd_mux_sel_r_reg[2]_29\,
      \rd_mux_sel_r_reg[2]_3\ => \rd_mux_sel_r_reg[2]_3\,
      \rd_mux_sel_r_reg[2]_30\ => \rd_mux_sel_r_reg[2]_30\,
      \rd_mux_sel_r_reg[2]_31\ => \rd_mux_sel_r_reg[2]_31\,
      \rd_mux_sel_r_reg[2]_32\ => \rd_mux_sel_r_reg[2]_32\,
      \rd_mux_sel_r_reg[2]_33\ => \rd_mux_sel_r_reg[2]_33\,
      \rd_mux_sel_r_reg[2]_34\ => \rd_mux_sel_r_reg[2]_34\,
      \rd_mux_sel_r_reg[2]_35\ => \rd_mux_sel_r_reg[2]_35\,
      \rd_mux_sel_r_reg[2]_36\ => \rd_mux_sel_r_reg[2]_36\,
      \rd_mux_sel_r_reg[2]_37\ => \rd_mux_sel_r_reg[2]_37\,
      \rd_mux_sel_r_reg[2]_38\ => \rd_mux_sel_r_reg[2]_38\,
      \rd_mux_sel_r_reg[2]_39\ => \rd_mux_sel_r_reg[2]_39\,
      \rd_mux_sel_r_reg[2]_4\ => \rd_mux_sel_r_reg[2]_4\,
      \rd_mux_sel_r_reg[2]_40\ => \rd_mux_sel_r_reg[2]_40\,
      \rd_mux_sel_r_reg[2]_41\ => \rd_mux_sel_r_reg[2]_41\,
      \rd_mux_sel_r_reg[2]_42\ => \rd_mux_sel_r_reg[2]_42\,
      \rd_mux_sel_r_reg[2]_43\ => \rd_mux_sel_r_reg[2]_43\,
      \rd_mux_sel_r_reg[2]_44\ => \rd_mux_sel_r_reg[2]_44\,
      \rd_mux_sel_r_reg[2]_45\ => \rd_mux_sel_r_reg[2]_45\,
      \rd_mux_sel_r_reg[2]_46\ => \rd_mux_sel_r_reg[2]_46\,
      \rd_mux_sel_r_reg[2]_47\ => \rd_mux_sel_r_reg[2]_47\,
      \rd_mux_sel_r_reg[2]_48\ => \rd_mux_sel_r_reg[2]_48\,
      \rd_mux_sel_r_reg[2]_49\ => \rd_mux_sel_r_reg[2]_49\,
      \rd_mux_sel_r_reg[2]_5\ => \rd_mux_sel_r_reg[2]_5\,
      \rd_mux_sel_r_reg[2]_50\ => \rd_mux_sel_r_reg[2]_50\,
      \rd_mux_sel_r_reg[2]_51\ => \rd_mux_sel_r_reg[2]_51\,
      \rd_mux_sel_r_reg[2]_52\ => \rd_mux_sel_r_reg[2]_52\,
      \rd_mux_sel_r_reg[2]_53\ => \rd_mux_sel_r_reg[2]_53\,
      \rd_mux_sel_r_reg[2]_54\ => \rd_mux_sel_r_reg[2]_54\,
      \rd_mux_sel_r_reg[2]_55\ => \rd_mux_sel_r_reg[2]_55\,
      \rd_mux_sel_r_reg[2]_56\ => \rd_mux_sel_r_reg[2]_56\,
      \rd_mux_sel_r_reg[2]_57\ => \rd_mux_sel_r_reg[2]_57\,
      \rd_mux_sel_r_reg[2]_58\ => \rd_mux_sel_r_reg[2]_58\,
      \rd_mux_sel_r_reg[2]_59\ => \rd_mux_sel_r_reg[2]_59\,
      \rd_mux_sel_r_reg[2]_6\ => \rd_mux_sel_r_reg[2]_6\,
      \rd_mux_sel_r_reg[2]_60\ => \rd_mux_sel_r_reg[2]_60\,
      \rd_mux_sel_r_reg[2]_61\ => \rd_mux_sel_r_reg[2]_61\,
      \rd_mux_sel_r_reg[2]_62\ => \rd_mux_sel_r_reg[2]_62\,
      \rd_mux_sel_r_reg[2]_7\ => \rd_mux_sel_r_reg[2]_7\,
      \rd_mux_sel_r_reg[2]_8\ => \rd_mux_sel_r_reg[2]_8\,
      \rd_mux_sel_r_reg[2]_9\ => \rd_mux_sel_r_reg[2]_9\,
      \rd_ptr_reg[1]_0\ => \entry_cnt_reg[4]\,
      \wr_ptr[1]_i_2__0\ => \wr_ptr[1]_i_2__0\,
      \wr_ptr_reg[0]_0\ => \^dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0\
    );
ififo_rst_reg: unisim.vcomponents.FDSE
    generic map(
      INIT => '1'
    )
        port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => ififo_rst_reg_0,
      Q => ififo_rst,
      S => phy_if_reset
    );
\in_fifo_gen.in_fifo\: unisim.vcomponents.IN_FIFO
    generic map(
      ALMOST_EMPTY_VALUE => 1,
      ALMOST_FULL_VALUE => 1,
      ARRAY_MODE => "ARRAY_MODE_4_X_8",
      SYNCHRONOUS_MODE => "FALSE"
    )
        port map (
      ALMOSTEMPTY => \in_fifo_gen.in_fifo_n_0\,
      ALMOSTFULL => \in_fifo_gen.in_fifo_n_1\,
      D0(3 downto 0) => B"0000",
      D1(3 downto 0) => B"0000",
      D2(3 downto 0) => if_d2(3 downto 0),
      D3(3 downto 0) => if_d3(3 downto 0),
      D4(3 downto 0) => if_d4(3 downto 0),
      D5(7 downto 4) => \NLW_in_fifo_gen.in_fifo_D5_UNCONNECTED\(7 downto 4),
      D5(3 downto 0) => if_d5(3 downto 0),
      D6(7 downto 4) => \NLW_in_fifo_gen.in_fifo_D6_UNCONNECTED\(7 downto 4),
      D6(3 downto 0) => if_d6(3 downto 0),
      D7(3 downto 0) => if_d7(3 downto 0),
      D8(3 downto 0) => if_d8(3 downto 0),
      D9(3 downto 0) => if_d9(3 downto 0),
      EMPTY => \if_empty_\,
      FULL => \in_fifo_gen.in_fifo_n_3\,
      Q0(7 downto 0) => rd_data(7 downto 0),
      Q1(7 downto 0) => rd_data(15 downto 8),
      Q2(7 downto 0) => rd_data(23 downto 16),
      Q3(7 downto 0) => rd_data(31 downto 24),
      Q4(7 downto 0) => rd_data(39 downto 32),
      Q5(7 downto 0) => rd_data(47 downto 40),
      Q6(7 downto 0) => rd_data(55 downto 48),
      Q7(7 downto 0) => rd_data(63 downto 56),
      Q8(7 downto 0) => rd_data(71 downto 64),
      Q9(7 downto 0) => rd_data(79 downto 72),
      RDCLK => \entry_cnt_reg[4]\,
      RDEN => '1',
      RESET => ififo_rst,
      WRCLK => iserdes_clkdiv,
      WREN => ififo_wr_enable
    );
\of_pre_fifo_gen.u_ddr_of_pre_fifo\: entity work.\mig_mig_7series_v4_2_ddr_of_pre_fifo__parameterized1_37\
     port map (
      D0(7) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_2\,
      D0(6) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_3\,
      D0(5) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_4\,
      D0(4) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_5\,
      D0(3) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_6\,
      D0(2) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_7\,
      D0(1) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_8\,
      D0(0) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_9\,
      D1(7 downto 0) => of_d1(7 downto 0),
      Q(2 downto 0) => Q(2 downto 0),
      \entry_cnt_reg[4]_0\ => \entry_cnt_reg[4]\,
      \my_empty_reg[1]_0\ => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_0\,
      \my_empty_reg[1]_1\ => \my_empty_reg[1]\,
      \my_empty_reg[7]_0\ => out_fifo_n_3,
      ofifo_rst => ofifo_rst,
      out_fifo => out_fifo_0,
      out_fifo_0(7 downto 0) => out_fifo_1(7 downto 0),
      out_fifo_1 => out_fifo_2,
      \out_fifo_i_75__5\(71 downto 0) => \out_fifo_i_75__5\(71 downto 0),
      phy_data_wr_en => phy_data_wr_en,
      \rd_ptr_reg[3]_0\(63 downto 0) => \rd_ptr_reg[3]\(63 downto 0)
    );
ofifo_rst_reg: unisim.vcomponents.FDSE
    generic map(
      INIT => '1'
    )
        port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => ififo_rst_reg_0,
      Q => ofifo_rst,
      S => A_rst_primitives
    );
out_fifo: unisim.vcomponents.OUT_FIFO
    generic map(
      ALMOST_EMPTY_VALUE => 1,
      ALMOST_FULL_VALUE => 1,
      ARRAY_MODE => "ARRAY_MODE_8_X_4",
      OUTPUT_DISABLE => "FALSE",
      SYNCHRONOUS_MODE => "FALSE"
    )
        port map (
      ALMOSTEMPTY => out_fifo_n_0,
      ALMOSTFULL => out_fifo_n_1,
      D0(7) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_2\,
      D0(6) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_3\,
      D0(5) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_4\,
      D0(4) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_5\,
      D0(3) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_6\,
      D0(2) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_7\,
      D0(1) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_8\,
      D0(0) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_9\,
      D1(7 downto 0) => of_d1(7 downto 0),
      D2(7 downto 0) => \my_empty_reg[7]\(7 downto 0),
      D3(7 downto 0) => \my_empty_reg[7]_0\(7 downto 0),
      D4(7 downto 0) => \my_empty_reg[7]_1\(7 downto 0),
      D5(7 downto 0) => \my_empty_reg[7]_2\(7 downto 0),
      D6(7 downto 0) => \my_empty_reg[7]_3\(7 downto 0),
      D7(7 downto 0) => \my_empty_reg[7]_4\(7 downto 0),
      D8(7 downto 0) => \my_empty_reg[7]_5\(7 downto 0),
      D9(7 downto 0) => \my_empty_reg[7]_6\(7 downto 0),
      EMPTY => out_fifo_n_2,
      FULL => out_fifo_n_3,
      Q0(3 downto 0) => of_dqbus(3 downto 0),
      Q1(3 downto 0) => of_dqbus(7 downto 4),
      Q2(3 downto 0) => of_dqbus(11 downto 8),
      Q3(3 downto 0) => of_dqbus(15 downto 12),
      Q4(3 downto 0) => of_dqbus(19 downto 16),
      Q5(7 downto 4) => NLW_out_fifo_Q5_UNCONNECTED(7 downto 4),
      Q5(3 downto 0) => of_dqbus(23 downto 20),
      Q6(7 downto 4) => NLW_out_fifo_Q6_UNCONNECTED(7 downto 4),
      Q6(3 downto 0) => of_dqbus(27 downto 24),
      Q7(3 downto 0) => of_dqbus(31 downto 28),
      Q8(3 downto 0) => of_dqbus(35 downto 32),
      Q9(3 downto 0) => of_dqbus(39 downto 36),
      RDCLK => oserdes_clkdiv,
      RDEN => po_rd_enable,
      RESET => ofifo_rst,
      WRCLK => \entry_cnt_reg[4]\,
      WREN => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_0\
    );
\phaser_in_gen.phaser_in\: unisim.vcomponents.PHASER_IN_PHY
    generic map(
      BURST_MODE => "TRUE",
      CLKOUT_DIV => 2,
      DQS_AUTO_RECAL => '1',
      DQS_BIAS_MODE => "FALSE",
      DQS_FIND_PATTERN => B"000",
      FINE_DELAY => 33,
      FREQ_REF_DIV => "DIV2",
      IS_RST_INVERTED => '0',
      MEMREFCLK_PERIOD => 2.500000,
      OUTPUT_CLK_SRC => "DELAYED_REF",
      PHASEREFCLK_PERIOD => 2.500000,
      REFCLK_PERIOD => 1.250000,
      SEL_CLK_OFFSET => 6,
      SYNC_IN_DIV_RST => "TRUE",
      WR_CYCLES => "FALSE"
    )
        port map (
      BURSTPENDINGPHY => phaser_ctl_bus(1),
      COUNTERLOADEN => \pi_dqs_found_lanes_r1_reg[1]\,
      COUNTERLOADVAL(5 downto 0) => \pi_dqs_found_lanes_r1_reg[1]_3\(5 downto 0),
      COUNTERREADEN => \pi_dqs_found_lanes_r1_reg[1]_0\,
      COUNTERREADVAL(5 downto 0) => B_pi_counter_read_val(5 downto 0),
      DQSFOUND => in0(0),
      DQSOUTOFRANGE => \phaser_in_gen.phaser_in_n_1\,
      ENCALIBPHY(1 downto 0) => PCENABLECALIB(1 downto 0),
      FINEENABLE => \pi_dqs_found_lanes_r1_reg[1]_1\,
      FINEINC => \pi_dqs_found_lanes_r1_reg[1]_2\,
      FINEOVERFLOW => \phaser_in_gen.phaser_in_n_2\,
      FREQREFCLK => freq_refclk,
      ICLK => \^a_rst_primitives_reg\,
      ICLKDIV => iserdes_clkdiv,
      ISERDESRST => \phaser_in_gen.phaser_in_n_5\,
      MEMREFCLK => mem_refclk,
      PHASELOCKED => A_rst_primitives_reg_0,
      PHASEREFCLK => mem_dqs_in(0),
      RANKSELPHY(1 downto 0) => phaser_ctl_bus(3 downto 2),
      RCLK => B_rclk,
      RST => A_rst_primitives,
      RSTDQSFIND => ififo_rst_reg_0,
      SYNCIN => sync_pulse,
      SYSCLK => \entry_cnt_reg[4]\,
      WRENABLE => ififo_wr_enable
    );
phaser_out: unisim.vcomponents.PHASER_OUT_PHY
    generic map(
      CLKOUT_DIV => 2,
      COARSE_BYPASS => "FALSE",
      COARSE_DELAY => 0,
      DATA_CTL_N => "TRUE",
      DATA_RD_CYCLES => "FALSE",
      FINE_DELAY => 60,
      IS_RST_INVERTED => '0',
      MEMREFCLK_PERIOD => 2.500000,
      OCLKDELAY_INV => "FALSE",
      OCLK_DELAY => 0,
      OUTPUT_CLK_SRC => "DELAYED_REF",
      PHASEREFCLK_PERIOD => 1.000000,
      PO => B"111",
      REFCLK_PERIOD => 1.250000,
      SYNC_IN_DIV_RST => "TRUE"
    )
        port map (
      BURSTPENDINGPHY => phaser_ctl_bus(0),
      COARSEENABLE => \po_counter_read_val_reg[8]\,
      COARSEINC => \po_counter_read_val_reg[8]\,
      COARSEOVERFLOW => phaser_out_n_0,
      COUNTERLOADEN => '0',
      COUNTERLOADVAL(8 downto 0) => B"000000000",
      COUNTERREADEN => \pi_dqs_found_lanes_r1_reg[1]_0\,
      COUNTERREADVAL(8 downto 0) => B_po_counter_read_val(8 downto 0),
      CTSBUS(1 downto 0) => oserdes_dqs_ts(1 downto 0),
      DQSBUS(1 downto 0) => oserdes_dqs(1 downto 0),
      DTSBUS(1 downto 0) => oserdes_dq_ts(1 downto 0),
      ENCALIBPHY(1 downto 0) => PCENABLECALIB(1 downto 0),
      FINEENABLE => \po_counter_read_val_reg[8]_0\,
      FINEINC => \po_counter_read_val_reg[8]_1\,
      FINEOVERFLOW => phaser_out_n_1,
      FREQREFCLK => freq_refclk,
      MEMREFCLK => mem_refclk,
      OCLK => oserdes_clk,
      OCLKDELAYED => oserdes_clk_delayed,
      OCLKDIV => oserdes_clkdiv,
      OSERDESRST => po_oserdes_rst,
      PHASEREFCLK => NLW_phaser_out_PHASEREFCLK_UNCONNECTED,
      RDENABLE => po_rd_enable,
      RST => A_rst_primitives,
      SELFINEOCLKDELAY => '0',
      SYNCIN => sync_pulse,
      SYSCLK => \entry_cnt_reg[4]\
    );
\pi_counter_read_val[0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0AAFFCCF0AA00CC"
    )
        port map (
      I0 => B_pi_counter_read_val(0),
      I1 => COUNTERREADVAL(0),
      I2 => \pi_counter_read_val_reg[5]\(0),
      I3 => calib_sel(1),
      I4 => calib_sel(0),
      I5 => \pi_counter_read_val_reg[5]_0\(0),
      O => D(0)
    );
\pi_counter_read_val[1]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0AAFFCCF0AA00CC"
    )
        port map (
      I0 => B_pi_counter_read_val(1),
      I1 => COUNTERREADVAL(1),
      I2 => \pi_counter_read_val_reg[5]\(1),
      I3 => calib_sel(1),
      I4 => calib_sel(0),
      I5 => \pi_counter_read_val_reg[5]_0\(1),
      O => D(1)
    );
\pi_counter_read_val[2]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0AAFFCCF0AA00CC"
    )
        port map (
      I0 => B_pi_counter_read_val(2),
      I1 => COUNTERREADVAL(2),
      I2 => \pi_counter_read_val_reg[5]\(2),
      I3 => calib_sel(1),
      I4 => calib_sel(0),
      I5 => \pi_counter_read_val_reg[5]_0\(2),
      O => D(2)
    );
\pi_counter_read_val[3]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0AAFFCCF0AA00CC"
    )
        port map (
      I0 => B_pi_counter_read_val(3),
      I1 => COUNTERREADVAL(3),
      I2 => \pi_counter_read_val_reg[5]\(3),
      I3 => calib_sel(1),
      I4 => calib_sel(0),
      I5 => \pi_counter_read_val_reg[5]_0\(3),
      O => D(3)
    );
\pi_counter_read_val[4]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0AAFFCCF0AA00CC"
    )
        port map (
      I0 => B_pi_counter_read_val(4),
      I1 => COUNTERREADVAL(4),
      I2 => \pi_counter_read_val_reg[5]\(4),
      I3 => calib_sel(1),
      I4 => calib_sel(0),
      I5 => \pi_counter_read_val_reg[5]_0\(4),
      O => D(4)
    );
\pi_counter_read_val[5]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0AAFFCCF0AA00CC"
    )
        port map (
      I0 => B_pi_counter_read_val(5),
      I1 => COUNTERREADVAL(5),
      I2 => \pi_counter_read_val_reg[5]\(5),
      I3 => calib_sel(1),
      I4 => calib_sel(0),
      I5 => \pi_counter_read_val_reg[5]_0\(5),
      O => D(5)
    );
\po_counter_read_val[0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0AAFFCCF0AA00CC"
    )
        port map (
      I0 => B_po_counter_read_val(0),
      I1 => \po_counter_read_val_reg[8]_2\(0),
      I2 => \po_counter_read_val_reg[8]_3\(0),
      I3 => calib_sel(1),
      I4 => calib_sel(0),
      I5 => \po_counter_read_val_reg[8]_4\(0),
      O => \calib_sel_reg[1]\(0)
    );
\po_counter_read_val[1]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0AAFFCCF0AA00CC"
    )
        port map (
      I0 => B_po_counter_read_val(1),
      I1 => \po_counter_read_val_reg[8]_2\(1),
      I2 => \po_counter_read_val_reg[8]_3\(1),
      I3 => calib_sel(1),
      I4 => calib_sel(0),
      I5 => \po_counter_read_val_reg[8]_4\(1),
      O => \calib_sel_reg[1]\(1)
    );
\po_counter_read_val[2]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0AAFFCCF0AA00CC"
    )
        port map (
      I0 => B_po_counter_read_val(2),
      I1 => \po_counter_read_val_reg[8]_2\(2),
      I2 => \po_counter_read_val_reg[8]_3\(2),
      I3 => calib_sel(1),
      I4 => calib_sel(0),
      I5 => \po_counter_read_val_reg[8]_4\(2),
      O => \calib_sel_reg[1]\(2)
    );
\po_counter_read_val[3]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0AAFFCCF0AA00CC"
    )
        port map (
      I0 => B_po_counter_read_val(3),
      I1 => \po_counter_read_val_reg[8]_2\(3),
      I2 => \po_counter_read_val_reg[8]_3\(3),
      I3 => calib_sel(1),
      I4 => calib_sel(0),
      I5 => \po_counter_read_val_reg[8]_4\(3),
      O => \calib_sel_reg[1]\(3)
    );
\po_counter_read_val[4]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0AAFFCCF0AA00CC"
    )
        port map (
      I0 => B_po_counter_read_val(4),
      I1 => \po_counter_read_val_reg[8]_2\(4),
      I2 => \po_counter_read_val_reg[8]_3\(4),
      I3 => calib_sel(1),
      I4 => calib_sel(0),
      I5 => \po_counter_read_val_reg[8]_4\(4),
      O => \calib_sel_reg[1]\(4)
    );
\po_counter_read_val[5]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0AAFFCCF0AA00CC"
    )
        port map (
      I0 => B_po_counter_read_val(5),
      I1 => \po_counter_read_val_reg[8]_2\(5),
      I2 => \po_counter_read_val_reg[8]_3\(5),
      I3 => calib_sel(1),
      I4 => calib_sel(0),
      I5 => \po_counter_read_val_reg[8]_4\(5),
      O => \calib_sel_reg[1]\(5)
    );
\po_counter_read_val[6]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0AAFFCCF0AA00CC"
    )
        port map (
      I0 => B_po_counter_read_val(6),
      I1 => \po_counter_read_val_reg[8]_2\(6),
      I2 => \po_counter_read_val_reg[8]_3\(6),
      I3 => calib_sel(1),
      I4 => calib_sel(0),
      I5 => \po_counter_read_val_reg[8]_4\(6),
      O => \calib_sel_reg[1]\(6)
    );
\po_counter_read_val[7]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0AAFFCCF0AA00CC"
    )
        port map (
      I0 => B_po_counter_read_val(7),
      I1 => \po_counter_read_val_reg[8]_2\(7),
      I2 => \po_counter_read_val_reg[8]_3\(7),
      I3 => calib_sel(1),
      I4 => calib_sel(0),
      I5 => \po_counter_read_val_reg[8]_4\(7),
      O => \calib_sel_reg[1]\(7)
    );
\po_counter_read_val[8]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0AAFFCCF0AA00CC"
    )
        port map (
      I0 => B_po_counter_read_val(8),
      I1 => \po_counter_read_val_reg[8]_2\(8),
      I2 => \po_counter_read_val_reg[8]_3\(8),
      I3 => calib_sel(1),
      I4 => calib_sel(0),
      I5 => \po_counter_read_val_reg[8]_4\(8),
      O => \calib_sel_reg[1]\(8)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \mig_mig_7series_v4_2_ddr_byte_lane__parameterized1\ is
  port (
    out_dqs_2 : out STD_LOGIC;
    ts_dqs_2 : out STD_LOGIC;
    A_rst_primitives_reg : out STD_LOGIC;
    mem_dq_out : out STD_LOGIC_VECTOR ( 8 downto 0 );
    mem_dq_ts : out STD_LOGIC_VECTOR ( 8 downto 0 );
    in0 : out STD_LOGIC_VECTOR ( 0 to 0 );
    A_rst_primitives_reg_0 : out STD_LOGIC;
    A_rst_primitives_reg_1 : out STD_LOGIC_VECTOR ( 5 downto 0 );
    A_rst_primitives_reg_2 : out STD_LOGIC_VECTOR ( 8 downto 0 );
    idelay_ld_rst_5 : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0\ : out STD_LOGIC;
    \my_empty_reg[1]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_3\ : out STD_LOGIC;
    \rd_ptr_reg[3]\ : out STD_LOGIC_VECTOR ( 63 downto 0 );
    Q : out STD_LOGIC_VECTOR ( 2 downto 0 );
    \wr_ptr_timing_reg[3]\ : in STD_LOGIC;
    \input_[9].iserdes_dq_.iserdesdq\ : in STD_LOGIC;
    mem_dq_in : in STD_LOGIC_VECTOR ( 7 downto 0 );
    idelay_inc : in STD_LOGIC;
    LD0_12 : in STD_LOGIC;
    A_rst_primitives : in STD_LOGIC;
    CLKB0_12 : in STD_LOGIC;
    phaser_ctl_bus : in STD_LOGIC_VECTOR ( 3 downto 0 );
    \pi_dqs_found_lanes_r1_reg[10]\ : in STD_LOGIC;
    \pi_dqs_found_lanes_r1_reg[10]_0\ : in STD_LOGIC;
    \pi_dqs_found_lanes_r1_reg[10]_1\ : in STD_LOGIC;
    \pi_dqs_found_lanes_r1_reg[10]_2\ : in STD_LOGIC;
    freq_refclk : in STD_LOGIC;
    mem_refclk : in STD_LOGIC;
    mem_dqs_in : in STD_LOGIC_VECTOR ( 0 to 0 );
    ififo_rst_reg_0 : in STD_LOGIC;
    sync_pulse : in STD_LOGIC;
    PCENABLECALIB : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \pi_dqs_found_lanes_r1_reg[10]_3\ : in STD_LOGIC_VECTOR ( 5 downto 0 );
    \po_counter_read_val_reg[8]\ : in STD_LOGIC;
    \po_counter_read_val_reg[8]_0\ : in STD_LOGIC;
    \po_counter_read_val_reg[8]_1\ : in STD_LOGIC;
    \my_empty_reg[7]\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \my_empty_reg[7]_0\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \my_empty_reg[7]_1\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \my_empty_reg[7]_2\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \my_empty_reg[7]_3\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \my_empty_reg[7]_4\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \my_empty_reg[7]_5\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \my_empty_reg[7]_6\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    phy_if_reset : in STD_LOGIC;
    \my_full_reg[1]\ : in STD_LOGIC;
    \wr_ptr[1]_i_2__2\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    if_empty_r : in STD_LOGIC_VECTOR ( 0 to 0 );
    phy_data_wr_en : in STD_LOGIC;
    rst_r4 : in STD_LOGIC;
    out_fifo_0 : in STD_LOGIC;
    out_fifo_1 : in STD_LOGIC_VECTOR ( 7 downto 0 );
    out_fifo_2 : in STD_LOGIC;
    \my_full_reg[1]_0\ : in STD_LOGIC;
    \my_full_reg[1]_1\ : in STD_LOGIC;
    \my_full_reg[1]_2\ : in STD_LOGIC;
    \my_full_reg[1]_3\ : in STD_LOGIC;
    \my_full_reg[1]_4\ : in STD_LOGIC;
    \out_fifo_i_75__2\ : in STD_LOGIC_VECTOR ( 71 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \mig_mig_7series_v4_2_ddr_byte_lane__parameterized1\ : entity is "mig_7series_v4_2_ddr_byte_lane";
end \mig_mig_7series_v4_2_ddr_byte_lane__parameterized1\;

architecture STRUCTURE of \mig_mig_7series_v4_2_ddr_byte_lane__parameterized1\ is
  signal \^a_rst_primitives_reg\ : STD_LOGIC;
  signal if_d2 : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal if_d3 : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal if_d4 : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal if_d5 : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal if_d6 : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal if_d7 : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal if_d8 : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal if_d9 : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \if_empty_\ : STD_LOGIC;
  signal if_empty_r_0 : STD_LOGIC_VECTOR ( 3 to 3 );
  signal ififo_rst : STD_LOGIC;
  signal ififo_wr_enable : STD_LOGIC;
  signal \in_fifo_gen.in_fifo_n_0\ : STD_LOGIC;
  signal \in_fifo_gen.in_fifo_n_1\ : STD_LOGIC;
  signal \in_fifo_gen.in_fifo_n_3\ : STD_LOGIC;
  signal iserdes_clkdiv : STD_LOGIC;
  signal of_d1 : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal of_dqbus : STD_LOGIC_VECTOR ( 39 downto 0 );
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_0\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_2\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_3\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_4\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_5\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_6\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_7\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_8\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_9\ : STD_LOGIC;
  signal ofifo_rst : STD_LOGIC;
  signal oserdes_clk : STD_LOGIC;
  signal oserdes_clk_delayed : STD_LOGIC;
  signal oserdes_clkdiv : STD_LOGIC;
  signal oserdes_dq_ts : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal oserdes_dqs : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal oserdes_dqs_ts : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal out_fifo_n_0 : STD_LOGIC;
  signal out_fifo_n_1 : STD_LOGIC;
  signal out_fifo_n_2 : STD_LOGIC;
  signal out_fifo_n_3 : STD_LOGIC;
  signal \phaser_in_gen.phaser_in_n_1\ : STD_LOGIC;
  signal \phaser_in_gen.phaser_in_n_2\ : STD_LOGIC;
  signal \phaser_in_gen.phaser_in_n_5\ : STD_LOGIC;
  signal \phaser_in_gen.phaser_in_n_7\ : STD_LOGIC;
  signal phaser_out_n_0 : STD_LOGIC;
  signal phaser_out_n_1 : STD_LOGIC;
  signal po_oserdes_rst : STD_LOGIC;
  signal po_rd_enable : STD_LOGIC;
  signal rd_data : STD_LOGIC_VECTOR ( 79 downto 0 );
  signal rd_data_r : STD_LOGIC_VECTOR ( 79 downto 12 );
  signal \NLW_in_fifo_gen.in_fifo_D5_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 4 );
  signal \NLW_in_fifo_gen.in_fifo_D6_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 4 );
  signal NLW_out_fifo_Q5_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 4 );
  signal NLW_out_fifo_Q6_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 4 );
  signal NLW_phaser_out_PHASEREFCLK_UNCONNECTED : STD_LOGIC;
  attribute syn_maxfan : string;
  attribute syn_maxfan of \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]\ : label is "3";
  attribute BOX_TYPE : string;
  attribute BOX_TYPE of \in_fifo_gen.in_fifo\ : label is "PRIMITIVE";
  attribute BOX_TYPE of out_fifo : label is "PRIMITIVE";
  attribute BOX_TYPE of \phaser_in_gen.phaser_in\ : label is "PRIMITIVE";
  attribute BOX_TYPE of phaser_out : label is "PRIMITIVE";
begin
  A_rst_primitives_reg <= \^a_rst_primitives_reg\;
ddr_byte_group_io: entity work.\mig_mig_7series_v4_2_ddr_byte_group_io__parameterized0_14\
     port map (
      A_rst_primitives => A_rst_primitives,
      CLKB0_12 => CLKB0_12,
      CTSBUS(0) => oserdes_dqs_ts(0),
      D2(3 downto 0) => if_d2(3 downto 0),
      D3(3 downto 0) => if_d3(3 downto 0),
      D4(3 downto 0) => if_d4(3 downto 0),
      D5(3 downto 0) => if_d5(3 downto 0),
      D6(3 downto 0) => if_d6(3 downto 0),
      D7(3 downto 0) => if_d7(3 downto 0),
      D8(3 downto 0) => if_d8(3 downto 0),
      D9(3 downto 0) => if_d9(3 downto 0),
      DQSBUS(1 downto 0) => oserdes_dqs(1 downto 0),
      DTSBUS(1 downto 0) => oserdes_dq_ts(1 downto 0),
      LD0_12 => LD0_12,
      \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]\ => \^a_rst_primitives_reg\,
      idelay_inc => idelay_inc,
      idelay_ld_rst_5 => idelay_ld_rst_5,
      idelay_ld_rst_reg_0 => \wr_ptr_timing_reg[3]\,
      \input_[9].iserdes_dq_.iserdesdq_0\ => \input_[9].iserdes_dq_.iserdesdq\,
      iserdes_clkdiv => iserdes_clkdiv,
      mem_dq_in(7 downto 0) => mem_dq_in(7 downto 0),
      mem_dq_out(8 downto 0) => mem_dq_out(8 downto 0),
      mem_dq_ts(8 downto 0) => mem_dq_ts(8 downto 0),
      of_dqbus(35 downto 0) => of_dqbus(39 downto 4),
      oserdes_clk => oserdes_clk,
      oserdes_clk_delayed => oserdes_clk_delayed,
      oserdes_clkdiv => oserdes_clkdiv,
      out_dqs_2 => out_dqs_2,
      po_oserdes_rst => po_oserdes_rst,
      rst_r4 => rst_r4,
      ts_dqs_2 => ts_dqs_2
    );
\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_ptr_timing_reg[3]\,
      CE => '1',
      D => \if_empty_\,
      Q => if_empty_r_0(3),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_ptr_timing_reg[3]\,
      CE => '1',
      D => rd_data(12),
      Q => rd_data_r(12),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_ptr_timing_reg[3]\,
      CE => '1',
      D => rd_data(13),
      Q => rd_data_r(13),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_ptr_timing_reg[3]\,
      CE => '1',
      D => rd_data(14),
      Q => rd_data_r(14),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_ptr_timing_reg[3]\,
      CE => '1',
      D => rd_data(15),
      Q => rd_data_r(15),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_ptr_timing_reg[3]\,
      CE => '1',
      D => rd_data(16),
      Q => rd_data_r(16),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_ptr_timing_reg[3]\,
      CE => '1',
      D => rd_data(17),
      Q => rd_data_r(17),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_ptr_timing_reg[3]\,
      CE => '1',
      D => rd_data(18),
      Q => rd_data_r(18),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_ptr_timing_reg[3]\,
      CE => '1',
      D => rd_data(19),
      Q => rd_data_r(19),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_ptr_timing_reg[3]\,
      CE => '1',
      D => rd_data(20),
      Q => rd_data_r(20),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_ptr_timing_reg[3]\,
      CE => '1',
      D => rd_data(21),
      Q => rd_data_r(21),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_ptr_timing_reg[3]\,
      CE => '1',
      D => rd_data(22),
      Q => rd_data_r(22),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_ptr_timing_reg[3]\,
      CE => '1',
      D => rd_data(23),
      Q => rd_data_r(23),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_ptr_timing_reg[3]\,
      CE => '1',
      D => rd_data(24),
      Q => rd_data_r(24),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_ptr_timing_reg[3]\,
      CE => '1',
      D => rd_data(25),
      Q => rd_data_r(25),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_ptr_timing_reg[3]\,
      CE => '1',
      D => rd_data(26),
      Q => rd_data_r(26),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_ptr_timing_reg[3]\,
      CE => '1',
      D => rd_data(27),
      Q => rd_data_r(27),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_ptr_timing_reg[3]\,
      CE => '1',
      D => rd_data(28),
      Q => rd_data_r(28),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_ptr_timing_reg[3]\,
      CE => '1',
      D => rd_data(29),
      Q => rd_data_r(29),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_ptr_timing_reg[3]\,
      CE => '1',
      D => rd_data(30),
      Q => rd_data_r(30),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_ptr_timing_reg[3]\,
      CE => '1',
      D => rd_data(31),
      Q => rd_data_r(31),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_ptr_timing_reg[3]\,
      CE => '1',
      D => rd_data(32),
      Q => rd_data_r(32),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_ptr_timing_reg[3]\,
      CE => '1',
      D => rd_data(33),
      Q => rd_data_r(33),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_ptr_timing_reg[3]\,
      CE => '1',
      D => rd_data(34),
      Q => rd_data_r(34),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_ptr_timing_reg[3]\,
      CE => '1',
      D => rd_data(35),
      Q => rd_data_r(35),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_ptr_timing_reg[3]\,
      CE => '1',
      D => rd_data(36),
      Q => rd_data_r(36),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_ptr_timing_reg[3]\,
      CE => '1',
      D => rd_data(37),
      Q => rd_data_r(37),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_ptr_timing_reg[3]\,
      CE => '1',
      D => rd_data(38),
      Q => rd_data_r(38),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_ptr_timing_reg[3]\,
      CE => '1',
      D => rd_data(39),
      Q => rd_data_r(39),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_ptr_timing_reg[3]\,
      CE => '1',
      D => rd_data(40),
      Q => rd_data_r(40),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_ptr_timing_reg[3]\,
      CE => '1',
      D => rd_data(41),
      Q => rd_data_r(41),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_ptr_timing_reg[3]\,
      CE => '1',
      D => rd_data(42),
      Q => rd_data_r(42),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_ptr_timing_reg[3]\,
      CE => '1',
      D => rd_data(43),
      Q => rd_data_r(43),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_ptr_timing_reg[3]\,
      CE => '1',
      D => rd_data(44),
      Q => rd_data_r(44),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_ptr_timing_reg[3]\,
      CE => '1',
      D => rd_data(45),
      Q => rd_data_r(45),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_ptr_timing_reg[3]\,
      CE => '1',
      D => rd_data(46),
      Q => rd_data_r(46),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_ptr_timing_reg[3]\,
      CE => '1',
      D => rd_data(47),
      Q => rd_data_r(47),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_ptr_timing_reg[3]\,
      CE => '1',
      D => rd_data(48),
      Q => rd_data_r(48),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_ptr_timing_reg[3]\,
      CE => '1',
      D => rd_data(49),
      Q => rd_data_r(49),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_ptr_timing_reg[3]\,
      CE => '1',
      D => rd_data(50),
      Q => rd_data_r(50),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_ptr_timing_reg[3]\,
      CE => '1',
      D => rd_data(51),
      Q => rd_data_r(51),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_ptr_timing_reg[3]\,
      CE => '1',
      D => rd_data(52),
      Q => rd_data_r(52),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_ptr_timing_reg[3]\,
      CE => '1',
      D => rd_data(53),
      Q => rd_data_r(53),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_ptr_timing_reg[3]\,
      CE => '1',
      D => rd_data(54),
      Q => rd_data_r(54),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_ptr_timing_reg[3]\,
      CE => '1',
      D => rd_data(55),
      Q => rd_data_r(55),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_ptr_timing_reg[3]\,
      CE => '1',
      D => rd_data(56),
      Q => rd_data_r(56),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_ptr_timing_reg[3]\,
      CE => '1',
      D => rd_data(57),
      Q => rd_data_r(57),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_ptr_timing_reg[3]\,
      CE => '1',
      D => rd_data(58),
      Q => rd_data_r(58),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_ptr_timing_reg[3]\,
      CE => '1',
      D => rd_data(59),
      Q => rd_data_r(59),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_ptr_timing_reg[3]\,
      CE => '1',
      D => rd_data(60),
      Q => rd_data_r(60),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_ptr_timing_reg[3]\,
      CE => '1',
      D => rd_data(61),
      Q => rd_data_r(61),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_ptr_timing_reg[3]\,
      CE => '1',
      D => rd_data(62),
      Q => rd_data_r(62),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_ptr_timing_reg[3]\,
      CE => '1',
      D => rd_data(63),
      Q => rd_data_r(63),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_ptr_timing_reg[3]\,
      CE => '1',
      D => rd_data(64),
      Q => rd_data_r(64),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_ptr_timing_reg[3]\,
      CE => '1',
      D => rd_data(65),
      Q => rd_data_r(65),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_ptr_timing_reg[3]\,
      CE => '1',
      D => rd_data(66),
      Q => rd_data_r(66),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_ptr_timing_reg[3]\,
      CE => '1',
      D => rd_data(67),
      Q => rd_data_r(67),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_ptr_timing_reg[3]\,
      CE => '1',
      D => rd_data(68),
      Q => rd_data_r(68),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_ptr_timing_reg[3]\,
      CE => '1',
      D => rd_data(69),
      Q => rd_data_r(69),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_ptr_timing_reg[3]\,
      CE => '1',
      D => rd_data(70),
      Q => rd_data_r(70),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_ptr_timing_reg[3]\,
      CE => '1',
      D => rd_data(71),
      Q => rd_data_r(71),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_ptr_timing_reg[3]\,
      CE => '1',
      D => rd_data(72),
      Q => rd_data_r(72),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_ptr_timing_reg[3]\,
      CE => '1',
      D => rd_data(73),
      Q => rd_data_r(73),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_ptr_timing_reg[3]\,
      CE => '1',
      D => rd_data(74),
      Q => rd_data_r(74),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_ptr_timing_reg[3]\,
      CE => '1',
      D => rd_data(75),
      Q => rd_data_r(75),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_ptr_timing_reg[3]\,
      CE => '1',
      D => rd_data(76),
      Q => rd_data_r(76),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_ptr_timing_reg[3]\,
      CE => '1',
      D => rd_data(77),
      Q => rd_data_r(77),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_ptr_timing_reg[3]\,
      CE => '1',
      D => rd_data(78),
      Q => rd_data_r(78),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_ptr_timing_reg[3]\,
      CE => '1',
      D => rd_data(79),
      Q => rd_data_r(79),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo\: entity work.mig_mig_7series_v4_2_ddr_if_post_fifo_15
     port map (
      Q(67 downto 0) => rd_data_r(79 downto 12),
      \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]\ => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0\,
      \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0\ => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1\,
      \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1\ => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_2\,
      \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_2\ => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0\,
      if_empty_r(0) => if_empty_r(0),
      if_empty_r_0(0) => if_empty_r_0(3),
      ififo_rst => ififo_rst,
      \my_full_reg[1]_0\ => \my_full_reg[1]\,
      \my_full_reg[1]_1\ => \my_full_reg[1]_0\,
      \my_full_reg[1]_2\ => \my_full_reg[1]_1\,
      \my_full_reg[1]_3\ => \my_full_reg[1]_2\,
      \my_full_reg[1]_4\ => \my_full_reg[1]_3\,
      \my_full_reg[1]_5\ => \my_full_reg[1]_4\,
      \rd_ptr_reg[1]_0\ => \wr_ptr_timing_reg[3]\,
      \wr_ptr[1]_i_2__2\(1 downto 0) => \wr_ptr[1]_i_2__2\(1 downto 0)
    );
ififo_rst_reg: unisim.vcomponents.FDSE
    generic map(
      INIT => '1'
    )
        port map (
      C => \wr_ptr_timing_reg[3]\,
      CE => '1',
      D => ififo_rst_reg_0,
      Q => ififo_rst,
      S => phy_if_reset
    );
\in_fifo_gen.in_fifo\: unisim.vcomponents.IN_FIFO
    generic map(
      ALMOST_EMPTY_VALUE => 1,
      ALMOST_FULL_VALUE => 1,
      ARRAY_MODE => "ARRAY_MODE_4_X_8",
      SYNCHRONOUS_MODE => "FALSE"
    )
        port map (
      ALMOSTEMPTY => \in_fifo_gen.in_fifo_n_0\,
      ALMOSTFULL => \in_fifo_gen.in_fifo_n_1\,
      D0(3 downto 0) => B"0000",
      D1(3 downto 0) => B"0000",
      D2(3 downto 0) => if_d2(3 downto 0),
      D3(3 downto 0) => if_d3(3 downto 0),
      D4(3 downto 0) => if_d4(3 downto 0),
      D5(7 downto 4) => \NLW_in_fifo_gen.in_fifo_D5_UNCONNECTED\(7 downto 4),
      D5(3 downto 0) => if_d5(3 downto 0),
      D6(7 downto 4) => \NLW_in_fifo_gen.in_fifo_D6_UNCONNECTED\(7 downto 4),
      D6(3 downto 0) => if_d6(3 downto 0),
      D7(3 downto 0) => if_d7(3 downto 0),
      D8(3 downto 0) => if_d8(3 downto 0),
      D9(3 downto 0) => if_d9(3 downto 0),
      EMPTY => \if_empty_\,
      FULL => \in_fifo_gen.in_fifo_n_3\,
      Q0(7 downto 0) => rd_data(7 downto 0),
      Q1(7 downto 0) => rd_data(15 downto 8),
      Q2(7 downto 0) => rd_data(23 downto 16),
      Q3(7 downto 0) => rd_data(31 downto 24),
      Q4(7 downto 0) => rd_data(39 downto 32),
      Q5(7 downto 0) => rd_data(47 downto 40),
      Q6(7 downto 0) => rd_data(55 downto 48),
      Q7(7 downto 0) => rd_data(63 downto 56),
      Q8(7 downto 0) => rd_data(71 downto 64),
      Q9(7 downto 0) => rd_data(79 downto 72),
      RDCLK => \wr_ptr_timing_reg[3]\,
      RDEN => '1',
      RESET => ififo_rst,
      WRCLK => iserdes_clkdiv,
      WREN => ififo_wr_enable
    );
\of_pre_fifo_gen.u_ddr_of_pre_fifo\: entity work.\mig_mig_7series_v4_2_ddr_of_pre_fifo__parameterized1_16\
     port map (
      D0(7) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_2\,
      D0(6) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_3\,
      D0(5) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_4\,
      D0(4) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_5\,
      D0(3) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_6\,
      D0(2) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_7\,
      D0(1) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_8\,
      D0(0) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_9\,
      D1(7 downto 0) => of_d1(7 downto 0),
      Q(2 downto 0) => Q(2 downto 0),
      \my_empty_reg[1]_0\ => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_0\,
      \my_empty_reg[1]_1\ => \my_empty_reg[1]\,
      \my_empty_reg[7]_0\ => out_fifo_n_3,
      ofifo_rst => ofifo_rst,
      out_fifo => out_fifo_0,
      out_fifo_0(7 downto 0) => out_fifo_1(7 downto 0),
      out_fifo_1 => out_fifo_2,
      \out_fifo_i_75__2\(71 downto 0) => \out_fifo_i_75__2\(71 downto 0),
      phy_data_wr_en => phy_data_wr_en,
      \rd_ptr_reg[3]_0\(63 downto 0) => \rd_ptr_reg[3]\(63 downto 0),
      \wr_ptr_timing_reg[3]_0\ => \wr_ptr_timing_reg[3]\
    );
ofifo_rst_reg: unisim.vcomponents.FDSE
    generic map(
      INIT => '1'
    )
        port map (
      C => \wr_ptr_timing_reg[3]\,
      CE => '1',
      D => ififo_rst_reg_0,
      Q => ofifo_rst,
      S => A_rst_primitives
    );
out_fifo: unisim.vcomponents.OUT_FIFO
    generic map(
      ALMOST_EMPTY_VALUE => 1,
      ALMOST_FULL_VALUE => 1,
      ARRAY_MODE => "ARRAY_MODE_8_X_4",
      OUTPUT_DISABLE => "FALSE",
      SYNCHRONOUS_MODE => "FALSE"
    )
        port map (
      ALMOSTEMPTY => out_fifo_n_0,
      ALMOSTFULL => out_fifo_n_1,
      D0(7) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_2\,
      D0(6) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_3\,
      D0(5) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_4\,
      D0(4) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_5\,
      D0(3) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_6\,
      D0(2) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_7\,
      D0(1) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_8\,
      D0(0) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_9\,
      D1(7 downto 0) => of_d1(7 downto 0),
      D2(7 downto 0) => \my_empty_reg[7]\(7 downto 0),
      D3(7 downto 0) => \my_empty_reg[7]_0\(7 downto 0),
      D4(7 downto 0) => \my_empty_reg[7]_1\(7 downto 0),
      D5(7 downto 0) => \my_empty_reg[7]_2\(7 downto 0),
      D6(7 downto 0) => \my_empty_reg[7]_3\(7 downto 0),
      D7(7 downto 0) => \my_empty_reg[7]_4\(7 downto 0),
      D8(7 downto 0) => \my_empty_reg[7]_5\(7 downto 0),
      D9(7 downto 0) => \my_empty_reg[7]_6\(7 downto 0),
      EMPTY => out_fifo_n_2,
      FULL => out_fifo_n_3,
      Q0(3 downto 0) => of_dqbus(3 downto 0),
      Q1(3 downto 0) => of_dqbus(7 downto 4),
      Q2(3 downto 0) => of_dqbus(11 downto 8),
      Q3(3 downto 0) => of_dqbus(15 downto 12),
      Q4(3 downto 0) => of_dqbus(19 downto 16),
      Q5(7 downto 4) => NLW_out_fifo_Q5_UNCONNECTED(7 downto 4),
      Q5(3 downto 0) => of_dqbus(23 downto 20),
      Q6(7 downto 4) => NLW_out_fifo_Q6_UNCONNECTED(7 downto 4),
      Q6(3 downto 0) => of_dqbus(27 downto 24),
      Q7(3 downto 0) => of_dqbus(31 downto 28),
      Q8(3 downto 0) => of_dqbus(35 downto 32),
      Q9(3 downto 0) => of_dqbus(39 downto 36),
      RDCLK => oserdes_clkdiv,
      RDEN => po_rd_enable,
      RESET => ofifo_rst,
      WRCLK => \wr_ptr_timing_reg[3]\,
      WREN => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_0\
    );
\phaser_in_gen.phaser_in\: unisim.vcomponents.PHASER_IN_PHY
    generic map(
      BURST_MODE => "TRUE",
      CLKOUT_DIV => 2,
      DQS_AUTO_RECAL => '1',
      DQS_BIAS_MODE => "FALSE",
      DQS_FIND_PATTERN => B"000",
      FINE_DELAY => 33,
      FREQ_REF_DIV => "DIV2",
      IS_RST_INVERTED => '0',
      MEMREFCLK_PERIOD => 2.500000,
      OUTPUT_CLK_SRC => "DELAYED_REF",
      PHASEREFCLK_PERIOD => 2.500000,
      REFCLK_PERIOD => 1.250000,
      SEL_CLK_OFFSET => 6,
      SYNC_IN_DIV_RST => "TRUE",
      WR_CYCLES => "FALSE"
    )
        port map (
      BURSTPENDINGPHY => phaser_ctl_bus(1),
      COUNTERLOADEN => \pi_dqs_found_lanes_r1_reg[10]\,
      COUNTERLOADVAL(5 downto 0) => \pi_dqs_found_lanes_r1_reg[10]_3\(5 downto 0),
      COUNTERREADEN => \pi_dqs_found_lanes_r1_reg[10]_0\,
      COUNTERREADVAL(5 downto 0) => A_rst_primitives_reg_1(5 downto 0),
      DQSFOUND => in0(0),
      DQSOUTOFRANGE => \phaser_in_gen.phaser_in_n_1\,
      ENCALIBPHY(1 downto 0) => PCENABLECALIB(1 downto 0),
      FINEENABLE => \pi_dqs_found_lanes_r1_reg[10]_1\,
      FINEINC => \pi_dqs_found_lanes_r1_reg[10]_2\,
      FINEOVERFLOW => \phaser_in_gen.phaser_in_n_2\,
      FREQREFCLK => freq_refclk,
      ICLK => \^a_rst_primitives_reg\,
      ICLKDIV => iserdes_clkdiv,
      ISERDESRST => \phaser_in_gen.phaser_in_n_5\,
      MEMREFCLK => mem_refclk,
      PHASELOCKED => A_rst_primitives_reg_0,
      PHASEREFCLK => mem_dqs_in(0),
      RANKSELPHY(1 downto 0) => phaser_ctl_bus(3 downto 2),
      RCLK => \phaser_in_gen.phaser_in_n_7\,
      RST => A_rst_primitives,
      RSTDQSFIND => ififo_rst_reg_0,
      SYNCIN => sync_pulse,
      SYSCLK => \wr_ptr_timing_reg[3]\,
      WRENABLE => ififo_wr_enable
    );
phaser_out: unisim.vcomponents.PHASER_OUT_PHY
    generic map(
      CLKOUT_DIV => 2,
      COARSE_BYPASS => "FALSE",
      COARSE_DELAY => 0,
      DATA_CTL_N => "TRUE",
      DATA_RD_CYCLES => "FALSE",
      FINE_DELAY => 60,
      IS_RST_INVERTED => '0',
      MEMREFCLK_PERIOD => 2.500000,
      OCLKDELAY_INV => "FALSE",
      OCLK_DELAY => 0,
      OUTPUT_CLK_SRC => "DELAYED_REF",
      PHASEREFCLK_PERIOD => 1.000000,
      PO => B"111",
      REFCLK_PERIOD => 1.250000,
      SYNC_IN_DIV_RST => "TRUE"
    )
        port map (
      BURSTPENDINGPHY => phaser_ctl_bus(0),
      COARSEENABLE => \po_counter_read_val_reg[8]\,
      COARSEINC => \po_counter_read_val_reg[8]\,
      COARSEOVERFLOW => phaser_out_n_0,
      COUNTERLOADEN => '0',
      COUNTERLOADVAL(8 downto 0) => B"000000000",
      COUNTERREADEN => \pi_dqs_found_lanes_r1_reg[10]_0\,
      COUNTERREADVAL(8 downto 0) => A_rst_primitives_reg_2(8 downto 0),
      CTSBUS(1 downto 0) => oserdes_dqs_ts(1 downto 0),
      DQSBUS(1 downto 0) => oserdes_dqs(1 downto 0),
      DTSBUS(1 downto 0) => oserdes_dq_ts(1 downto 0),
      ENCALIBPHY(1 downto 0) => PCENABLECALIB(1 downto 0),
      FINEENABLE => \po_counter_read_val_reg[8]_0\,
      FINEINC => \po_counter_read_val_reg[8]_1\,
      FINEOVERFLOW => phaser_out_n_1,
      FREQREFCLK => freq_refclk,
      MEMREFCLK => mem_refclk,
      OCLK => oserdes_clk,
      OCLKDELAYED => oserdes_clk_delayed,
      OCLKDIV => oserdes_clkdiv,
      OSERDESRST => po_oserdes_rst,
      PHASEREFCLK => NLW_phaser_out_PHASEREFCLK_UNCONNECTED,
      RDENABLE => po_rd_enable,
      RST => A_rst_primitives,
      SELFINEOCLKDELAY => '0',
      SYNCIN => sync_pulse,
      SYSCLK => \wr_ptr_timing_reg[3]\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \mig_mig_7series_v4_2_ddr_byte_lane__parameterized1_27\ is
  port (
    out_dqs_6 : out STD_LOGIC;
    ts_dqs_6 : out STD_LOGIC;
    A_rst_primitives_reg : out STD_LOGIC;
    mem_dq_out : out STD_LOGIC_VECTOR ( 8 downto 0 );
    mem_dq_ts : out STD_LOGIC_VECTOR ( 8 downto 0 );
    in0 : out STD_LOGIC_VECTOR ( 0 to 0 );
    A_rst_primitives_reg_0 : out STD_LOGIC_VECTOR ( 5 downto 0 );
    A_rst_primitives_reg_1 : out STD_LOGIC_VECTOR ( 8 downto 0 );
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0\ : out STD_LOGIC;
    \my_empty_reg[4]\ : out STD_LOGIC;
    idelay_ld_rst_1 : out STD_LOGIC;
    \my_empty_reg[4]_0\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    phy_mc_data_full : out STD_LOGIC;
    \my_empty_reg[1]\ : out STD_LOGIC;
    A_rst_primitives_reg_2 : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_2\ : out STD_LOGIC;
    \rd_ptr_reg[3]\ : out STD_LOGIC_VECTOR ( 63 downto 0 );
    Q : out STD_LOGIC_VECTOR ( 2 downto 0 );
    \my_full_reg[4]\ : in STD_LOGIC;
    \input_[9].iserdes_dq_.iserdesdq\ : in STD_LOGIC;
    mem_dq_in : in STD_LOGIC_VECTOR ( 7 downto 0 );
    idelay_inc : in STD_LOGIC;
    LD0_8 : in STD_LOGIC;
    A_rst_primitives : in STD_LOGIC;
    CLKB0_8 : in STD_LOGIC;
    phaser_ctl_bus : in STD_LOGIC_VECTOR ( 3 downto 0 );
    \pi_dqs_found_lanes_r1_reg[2]\ : in STD_LOGIC;
    \pi_dqs_found_lanes_r1_reg[2]_0\ : in STD_LOGIC;
    \pi_dqs_found_lanes_r1_reg[2]_1\ : in STD_LOGIC;
    \pi_dqs_found_lanes_r1_reg[2]_2\ : in STD_LOGIC;
    freq_refclk : in STD_LOGIC;
    mem_refclk : in STD_LOGIC;
    mem_dqs_in : in STD_LOGIC_VECTOR ( 0 to 0 );
    ififo_rst_reg_0 : in STD_LOGIC;
    sync_pulse : in STD_LOGIC;
    PCENABLECALIB : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \pi_dqs_found_lanes_r1_reg[2]_3\ : in STD_LOGIC_VECTOR ( 5 downto 0 );
    \po_counter_read_val_reg[8]\ : in STD_LOGIC;
    \po_counter_read_val_reg[8]_0\ : in STD_LOGIC;
    \po_counter_read_val_reg[8]_1\ : in STD_LOGIC;
    \my_empty_reg[7]\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \my_empty_reg[7]_0\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \my_empty_reg[7]_1\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \my_empty_reg[7]_2\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \my_empty_reg[7]_3\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \my_empty_reg[7]_4\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \my_empty_reg[7]_5\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \my_empty_reg[7]_6\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    phy_if_reset : in STD_LOGIC;
    \my_full_reg[1]\ : in STD_LOGIC;
    ofs_rdy_r_reg : in STD_LOGIC;
    ofs_rdy_r_reg_0 : in STD_LOGIC;
    ofs_rdy_r_reg_1 : in STD_LOGIC;
    ofs_rdy_r_reg_2 : in STD_LOGIC;
    phy_data_wr_en : in STD_LOGIC;
    pi_phase_locked_all_r1_reg : in STD_LOGIC;
    pi_phase_locked_all_r1_reg_0 : in STD_LOGIC;
    pi_phase_locked_all_r1_reg_1 : in STD_LOGIC;
    pi_phase_locked_all_r1_reg_2 : in STD_LOGIC;
    rst_r4 : in STD_LOGIC;
    \wr_ptr[1]_i_2__6\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    if_empty_r : in STD_LOGIC_VECTOR ( 0 to 0 );
    out_fifo_0 : in STD_LOGIC;
    out_fifo_1 : in STD_LOGIC_VECTOR ( 7 downto 0 );
    out_fifo_2 : in STD_LOGIC;
    \my_full_reg[1]_0\ : in STD_LOGIC;
    \my_full_reg[1]_1\ : in STD_LOGIC;
    \my_full_reg[1]_2\ : in STD_LOGIC;
    \my_full_reg[1]_3\ : in STD_LOGIC;
    \my_full_reg[1]_4\ : in STD_LOGIC;
    \out_fifo_i_75__6\ : in STD_LOGIC_VECTOR ( 71 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \mig_mig_7series_v4_2_ddr_byte_lane__parameterized1_27\ : entity is "mig_7series_v4_2_ddr_byte_lane";
end \mig_mig_7series_v4_2_ddr_byte_lane__parameterized1_27\;

architecture STRUCTURE of \mig_mig_7series_v4_2_ddr_byte_lane__parameterized1_27\ is
  signal \^a_rst_primitives_reg\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0\ : STD_LOGIC;
  signal if_d2 : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal if_d3 : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal if_d4 : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal if_d5 : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal if_d6 : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal if_d7 : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal if_d8 : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal if_d9 : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \if_empty_\ : STD_LOGIC;
  signal ififo_rst : STD_LOGIC;
  signal ififo_wr_enable : STD_LOGIC;
  signal \in_fifo_gen.in_fifo_n_0\ : STD_LOGIC;
  signal \in_fifo_gen.in_fifo_n_1\ : STD_LOGIC;
  signal \in_fifo_gen.in_fifo_n_3\ : STD_LOGIC;
  signal iserdes_clkdiv : STD_LOGIC;
  signal of_d1 : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal of_dqbus : STD_LOGIC_VECTOR ( 39 downto 0 );
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_1\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_10\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_3\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_4\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_5\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_6\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_7\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_8\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_9\ : STD_LOGIC;
  signal ofifo_rst : STD_LOGIC;
  signal oserdes_clk : STD_LOGIC;
  signal oserdes_clk_delayed : STD_LOGIC;
  signal oserdes_clkdiv : STD_LOGIC;
  signal oserdes_dq_ts : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal oserdes_dqs : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal oserdes_dqs_ts : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal out_fifo_n_0 : STD_LOGIC;
  signal out_fifo_n_1 : STD_LOGIC;
  signal out_fifo_n_2 : STD_LOGIC;
  signal out_fifo_n_3 : STD_LOGIC;
  signal \phaser_in_gen.phaser_in_n_1\ : STD_LOGIC;
  signal \phaser_in_gen.phaser_in_n_2\ : STD_LOGIC;
  signal \phaser_in_gen.phaser_in_n_5\ : STD_LOGIC;
  signal \phaser_in_gen.phaser_in_n_6\ : STD_LOGIC;
  signal \phaser_in_gen.phaser_in_n_7\ : STD_LOGIC;
  signal phaser_out_n_0 : STD_LOGIC;
  signal phaser_out_n_1 : STD_LOGIC;
  signal po_oserdes_rst : STD_LOGIC;
  signal po_rd_enable : STD_LOGIC;
  signal rd_data : STD_LOGIC_VECTOR ( 79 downto 0 );
  signal rd_data_r : STD_LOGIC_VECTOR ( 79 downto 12 );
  signal \NLW_in_fifo_gen.in_fifo_D5_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 4 );
  signal \NLW_in_fifo_gen.in_fifo_D6_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 4 );
  signal NLW_out_fifo_Q5_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 4 );
  signal NLW_out_fifo_Q6_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 4 );
  signal NLW_phaser_out_PHASEREFCLK_UNCONNECTED : STD_LOGIC;
  attribute syn_maxfan : string;
  attribute syn_maxfan of \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]\ : label is "3";
  attribute BOX_TYPE : string;
  attribute BOX_TYPE of \in_fifo_gen.in_fifo\ : label is "PRIMITIVE";
  attribute BOX_TYPE of out_fifo : label is "PRIMITIVE";
  attribute BOX_TYPE of \phaser_in_gen.phaser_in\ : label is "PRIMITIVE";
  attribute BOX_TYPE of phaser_out : label is "PRIMITIVE";
begin
  A_rst_primitives_reg <= \^a_rst_primitives_reg\;
  \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0\ <= \^dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0\;
ddr_byte_group_io: entity work.\mig_mig_7series_v4_2_ddr_byte_group_io__parameterized0_32\
     port map (
      A_rst_primitives => A_rst_primitives,
      CLKB0_8 => CLKB0_8,
      CTSBUS(0) => oserdes_dqs_ts(0),
      D2(3 downto 0) => if_d2(3 downto 0),
      D3(3 downto 0) => if_d3(3 downto 0),
      D4(3 downto 0) => if_d4(3 downto 0),
      D5(3 downto 0) => if_d5(3 downto 0),
      D6(3 downto 0) => if_d6(3 downto 0),
      D7(3 downto 0) => if_d7(3 downto 0),
      D8(3 downto 0) => if_d8(3 downto 0),
      D9(3 downto 0) => if_d9(3 downto 0),
      DQSBUS(1 downto 0) => oserdes_dqs(1 downto 0),
      DTSBUS(1 downto 0) => oserdes_dq_ts(1 downto 0),
      LD0_8 => LD0_8,
      \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]\ => \^a_rst_primitives_reg\,
      idelay_inc => idelay_inc,
      idelay_ld_rst_1 => idelay_ld_rst_1,
      idelay_ld_rst_reg_0 => \my_full_reg[4]\,
      \input_[9].iserdes_dq_.iserdesdq_0\ => \input_[9].iserdes_dq_.iserdesdq\,
      iserdes_clkdiv => iserdes_clkdiv,
      mem_dq_in(7 downto 0) => mem_dq_in(7 downto 0),
      mem_dq_out(8 downto 0) => mem_dq_out(8 downto 0),
      mem_dq_ts(8 downto 0) => mem_dq_ts(8 downto 0),
      of_dqbus(35 downto 0) => of_dqbus(39 downto 4),
      oserdes_clk => oserdes_clk,
      oserdes_clk_delayed => oserdes_clk_delayed,
      oserdes_clkdiv => oserdes_clkdiv,
      out_dqs_6 => out_dqs_6,
      po_oserdes_rst => po_oserdes_rst,
      rst_r4 => rst_r4,
      ts_dqs_6 => ts_dqs_6
    );
\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => \my_full_reg[4]\,
      CE => '1',
      D => \if_empty_\,
      Q => \^dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0\,
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]\: unisim.vcomponents.FDRE
     port map (
      C => \my_full_reg[4]\,
      CE => '1',
      D => rd_data(12),
      Q => rd_data_r(12),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]\: unisim.vcomponents.FDRE
     port map (
      C => \my_full_reg[4]\,
      CE => '1',
      D => rd_data(13),
      Q => rd_data_r(13),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]\: unisim.vcomponents.FDRE
     port map (
      C => \my_full_reg[4]\,
      CE => '1',
      D => rd_data(14),
      Q => rd_data_r(14),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]\: unisim.vcomponents.FDRE
     port map (
      C => \my_full_reg[4]\,
      CE => '1',
      D => rd_data(15),
      Q => rd_data_r(15),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]\: unisim.vcomponents.FDRE
     port map (
      C => \my_full_reg[4]\,
      CE => '1',
      D => rd_data(16),
      Q => rd_data_r(16),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]\: unisim.vcomponents.FDRE
     port map (
      C => \my_full_reg[4]\,
      CE => '1',
      D => rd_data(17),
      Q => rd_data_r(17),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]\: unisim.vcomponents.FDRE
     port map (
      C => \my_full_reg[4]\,
      CE => '1',
      D => rd_data(18),
      Q => rd_data_r(18),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]\: unisim.vcomponents.FDRE
     port map (
      C => \my_full_reg[4]\,
      CE => '1',
      D => rd_data(19),
      Q => rd_data_r(19),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]\: unisim.vcomponents.FDRE
     port map (
      C => \my_full_reg[4]\,
      CE => '1',
      D => rd_data(20),
      Q => rd_data_r(20),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]\: unisim.vcomponents.FDRE
     port map (
      C => \my_full_reg[4]\,
      CE => '1',
      D => rd_data(21),
      Q => rd_data_r(21),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]\: unisim.vcomponents.FDRE
     port map (
      C => \my_full_reg[4]\,
      CE => '1',
      D => rd_data(22),
      Q => rd_data_r(22),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]\: unisim.vcomponents.FDRE
     port map (
      C => \my_full_reg[4]\,
      CE => '1',
      D => rd_data(23),
      Q => rd_data_r(23),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]\: unisim.vcomponents.FDRE
     port map (
      C => \my_full_reg[4]\,
      CE => '1',
      D => rd_data(24),
      Q => rd_data_r(24),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]\: unisim.vcomponents.FDRE
     port map (
      C => \my_full_reg[4]\,
      CE => '1',
      D => rd_data(25),
      Q => rd_data_r(25),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]\: unisim.vcomponents.FDRE
     port map (
      C => \my_full_reg[4]\,
      CE => '1',
      D => rd_data(26),
      Q => rd_data_r(26),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]\: unisim.vcomponents.FDRE
     port map (
      C => \my_full_reg[4]\,
      CE => '1',
      D => rd_data(27),
      Q => rd_data_r(27),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]\: unisim.vcomponents.FDRE
     port map (
      C => \my_full_reg[4]\,
      CE => '1',
      D => rd_data(28),
      Q => rd_data_r(28),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]\: unisim.vcomponents.FDRE
     port map (
      C => \my_full_reg[4]\,
      CE => '1',
      D => rd_data(29),
      Q => rd_data_r(29),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]\: unisim.vcomponents.FDRE
     port map (
      C => \my_full_reg[4]\,
      CE => '1',
      D => rd_data(30),
      Q => rd_data_r(30),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]\: unisim.vcomponents.FDRE
     port map (
      C => \my_full_reg[4]\,
      CE => '1',
      D => rd_data(31),
      Q => rd_data_r(31),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]\: unisim.vcomponents.FDRE
     port map (
      C => \my_full_reg[4]\,
      CE => '1',
      D => rd_data(32),
      Q => rd_data_r(32),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]\: unisim.vcomponents.FDRE
     port map (
      C => \my_full_reg[4]\,
      CE => '1',
      D => rd_data(33),
      Q => rd_data_r(33),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]\: unisim.vcomponents.FDRE
     port map (
      C => \my_full_reg[4]\,
      CE => '1',
      D => rd_data(34),
      Q => rd_data_r(34),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]\: unisim.vcomponents.FDRE
     port map (
      C => \my_full_reg[4]\,
      CE => '1',
      D => rd_data(35),
      Q => rd_data_r(35),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]\: unisim.vcomponents.FDRE
     port map (
      C => \my_full_reg[4]\,
      CE => '1',
      D => rd_data(36),
      Q => rd_data_r(36),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]\: unisim.vcomponents.FDRE
     port map (
      C => \my_full_reg[4]\,
      CE => '1',
      D => rd_data(37),
      Q => rd_data_r(37),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]\: unisim.vcomponents.FDRE
     port map (
      C => \my_full_reg[4]\,
      CE => '1',
      D => rd_data(38),
      Q => rd_data_r(38),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]\: unisim.vcomponents.FDRE
     port map (
      C => \my_full_reg[4]\,
      CE => '1',
      D => rd_data(39),
      Q => rd_data_r(39),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]\: unisim.vcomponents.FDRE
     port map (
      C => \my_full_reg[4]\,
      CE => '1',
      D => rd_data(40),
      Q => rd_data_r(40),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]\: unisim.vcomponents.FDRE
     port map (
      C => \my_full_reg[4]\,
      CE => '1',
      D => rd_data(41),
      Q => rd_data_r(41),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]\: unisim.vcomponents.FDRE
     port map (
      C => \my_full_reg[4]\,
      CE => '1',
      D => rd_data(42),
      Q => rd_data_r(42),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]\: unisim.vcomponents.FDRE
     port map (
      C => \my_full_reg[4]\,
      CE => '1',
      D => rd_data(43),
      Q => rd_data_r(43),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]\: unisim.vcomponents.FDRE
     port map (
      C => \my_full_reg[4]\,
      CE => '1',
      D => rd_data(44),
      Q => rd_data_r(44),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]\: unisim.vcomponents.FDRE
     port map (
      C => \my_full_reg[4]\,
      CE => '1',
      D => rd_data(45),
      Q => rd_data_r(45),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]\: unisim.vcomponents.FDRE
     port map (
      C => \my_full_reg[4]\,
      CE => '1',
      D => rd_data(46),
      Q => rd_data_r(46),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]\: unisim.vcomponents.FDRE
     port map (
      C => \my_full_reg[4]\,
      CE => '1',
      D => rd_data(47),
      Q => rd_data_r(47),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]\: unisim.vcomponents.FDRE
     port map (
      C => \my_full_reg[4]\,
      CE => '1',
      D => rd_data(48),
      Q => rd_data_r(48),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]\: unisim.vcomponents.FDRE
     port map (
      C => \my_full_reg[4]\,
      CE => '1',
      D => rd_data(49),
      Q => rd_data_r(49),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]\: unisim.vcomponents.FDRE
     port map (
      C => \my_full_reg[4]\,
      CE => '1',
      D => rd_data(50),
      Q => rd_data_r(50),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]\: unisim.vcomponents.FDRE
     port map (
      C => \my_full_reg[4]\,
      CE => '1',
      D => rd_data(51),
      Q => rd_data_r(51),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]\: unisim.vcomponents.FDRE
     port map (
      C => \my_full_reg[4]\,
      CE => '1',
      D => rd_data(52),
      Q => rd_data_r(52),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]\: unisim.vcomponents.FDRE
     port map (
      C => \my_full_reg[4]\,
      CE => '1',
      D => rd_data(53),
      Q => rd_data_r(53),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]\: unisim.vcomponents.FDRE
     port map (
      C => \my_full_reg[4]\,
      CE => '1',
      D => rd_data(54),
      Q => rd_data_r(54),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]\: unisim.vcomponents.FDRE
     port map (
      C => \my_full_reg[4]\,
      CE => '1',
      D => rd_data(55),
      Q => rd_data_r(55),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]\: unisim.vcomponents.FDRE
     port map (
      C => \my_full_reg[4]\,
      CE => '1',
      D => rd_data(56),
      Q => rd_data_r(56),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]\: unisim.vcomponents.FDRE
     port map (
      C => \my_full_reg[4]\,
      CE => '1',
      D => rd_data(57),
      Q => rd_data_r(57),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]\: unisim.vcomponents.FDRE
     port map (
      C => \my_full_reg[4]\,
      CE => '1',
      D => rd_data(58),
      Q => rd_data_r(58),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]\: unisim.vcomponents.FDRE
     port map (
      C => \my_full_reg[4]\,
      CE => '1',
      D => rd_data(59),
      Q => rd_data_r(59),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]\: unisim.vcomponents.FDRE
     port map (
      C => \my_full_reg[4]\,
      CE => '1',
      D => rd_data(60),
      Q => rd_data_r(60),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]\: unisim.vcomponents.FDRE
     port map (
      C => \my_full_reg[4]\,
      CE => '1',
      D => rd_data(61),
      Q => rd_data_r(61),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]\: unisim.vcomponents.FDRE
     port map (
      C => \my_full_reg[4]\,
      CE => '1',
      D => rd_data(62),
      Q => rd_data_r(62),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]\: unisim.vcomponents.FDRE
     port map (
      C => \my_full_reg[4]\,
      CE => '1',
      D => rd_data(63),
      Q => rd_data_r(63),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]\: unisim.vcomponents.FDRE
     port map (
      C => \my_full_reg[4]\,
      CE => '1',
      D => rd_data(64),
      Q => rd_data_r(64),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]\: unisim.vcomponents.FDRE
     port map (
      C => \my_full_reg[4]\,
      CE => '1',
      D => rd_data(65),
      Q => rd_data_r(65),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]\: unisim.vcomponents.FDRE
     port map (
      C => \my_full_reg[4]\,
      CE => '1',
      D => rd_data(66),
      Q => rd_data_r(66),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]\: unisim.vcomponents.FDRE
     port map (
      C => \my_full_reg[4]\,
      CE => '1',
      D => rd_data(67),
      Q => rd_data_r(67),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]\: unisim.vcomponents.FDRE
     port map (
      C => \my_full_reg[4]\,
      CE => '1',
      D => rd_data(68),
      Q => rd_data_r(68),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]\: unisim.vcomponents.FDRE
     port map (
      C => \my_full_reg[4]\,
      CE => '1',
      D => rd_data(69),
      Q => rd_data_r(69),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]\: unisim.vcomponents.FDRE
     port map (
      C => \my_full_reg[4]\,
      CE => '1',
      D => rd_data(70),
      Q => rd_data_r(70),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]\: unisim.vcomponents.FDRE
     port map (
      C => \my_full_reg[4]\,
      CE => '1',
      D => rd_data(71),
      Q => rd_data_r(71),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]\: unisim.vcomponents.FDRE
     port map (
      C => \my_full_reg[4]\,
      CE => '1',
      D => rd_data(72),
      Q => rd_data_r(72),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]\: unisim.vcomponents.FDRE
     port map (
      C => \my_full_reg[4]\,
      CE => '1',
      D => rd_data(73),
      Q => rd_data_r(73),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]\: unisim.vcomponents.FDRE
     port map (
      C => \my_full_reg[4]\,
      CE => '1',
      D => rd_data(74),
      Q => rd_data_r(74),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]\: unisim.vcomponents.FDRE
     port map (
      C => \my_full_reg[4]\,
      CE => '1',
      D => rd_data(75),
      Q => rd_data_r(75),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]\: unisim.vcomponents.FDRE
     port map (
      C => \my_full_reg[4]\,
      CE => '1',
      D => rd_data(76),
      Q => rd_data_r(76),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]\: unisim.vcomponents.FDRE
     port map (
      C => \my_full_reg[4]\,
      CE => '1',
      D => rd_data(77),
      Q => rd_data_r(77),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]\: unisim.vcomponents.FDRE
     port map (
      C => \my_full_reg[4]\,
      CE => '1',
      D => rd_data(78),
      Q => rd_data_r(78),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]\: unisim.vcomponents.FDRE
     port map (
      C => \my_full_reg[4]\,
      CE => '1',
      D => rd_data(79),
      Q => rd_data_r(79),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo\: entity work.mig_mig_7series_v4_2_ddr_if_post_fifo_33
     port map (
      Q(67 downto 0) => rd_data_r(79 downto 12),
      \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]\ => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1\,
      \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0\ => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0\,
      if_empty_r(0) => if_empty_r(0),
      ififo_rst => ififo_rst,
      \my_empty_reg[4]_0\ => \my_empty_reg[4]\,
      \my_empty_reg[4]_1\(0) => \my_empty_reg[4]_0\(0),
      \my_full_reg[1]_0\ => \my_full_reg[1]\,
      \my_full_reg[1]_1\ => \my_full_reg[1]_0\,
      \my_full_reg[1]_2\ => \my_full_reg[1]_1\,
      \my_full_reg[1]_3\ => \my_full_reg[1]_2\,
      \my_full_reg[1]_4\ => \my_full_reg[1]_3\,
      \my_full_reg[1]_5\ => \my_full_reg[1]_4\,
      \rd_ptr_timing_reg[1]_0\ => \my_full_reg[4]\,
      \wr_ptr[1]_i_2__6\(0) => \wr_ptr[1]_i_2__6\(0),
      \wr_ptr_reg[0]_0\ => \^dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0\
    );
ififo_rst_reg: unisim.vcomponents.FDSE
    generic map(
      INIT => '1'
    )
        port map (
      C => \my_full_reg[4]\,
      CE => '1',
      D => ififo_rst_reg_0,
      Q => ififo_rst,
      S => phy_if_reset
    );
\in_fifo_gen.in_fifo\: unisim.vcomponents.IN_FIFO
    generic map(
      ALMOST_EMPTY_VALUE => 1,
      ALMOST_FULL_VALUE => 1,
      ARRAY_MODE => "ARRAY_MODE_4_X_8",
      SYNCHRONOUS_MODE => "FALSE"
    )
        port map (
      ALMOSTEMPTY => \in_fifo_gen.in_fifo_n_0\,
      ALMOSTFULL => \in_fifo_gen.in_fifo_n_1\,
      D0(3 downto 0) => B"0000",
      D1(3 downto 0) => B"0000",
      D2(3 downto 0) => if_d2(3 downto 0),
      D3(3 downto 0) => if_d3(3 downto 0),
      D4(3 downto 0) => if_d4(3 downto 0),
      D5(7 downto 4) => \NLW_in_fifo_gen.in_fifo_D5_UNCONNECTED\(7 downto 4),
      D5(3 downto 0) => if_d5(3 downto 0),
      D6(7 downto 4) => \NLW_in_fifo_gen.in_fifo_D6_UNCONNECTED\(7 downto 4),
      D6(3 downto 0) => if_d6(3 downto 0),
      D7(3 downto 0) => if_d7(3 downto 0),
      D8(3 downto 0) => if_d8(3 downto 0),
      D9(3 downto 0) => if_d9(3 downto 0),
      EMPTY => \if_empty_\,
      FULL => \in_fifo_gen.in_fifo_n_3\,
      Q0(7 downto 0) => rd_data(7 downto 0),
      Q1(7 downto 0) => rd_data(15 downto 8),
      Q2(7 downto 0) => rd_data(23 downto 16),
      Q3(7 downto 0) => rd_data(31 downto 24),
      Q4(7 downto 0) => rd_data(39 downto 32),
      Q5(7 downto 0) => rd_data(47 downto 40),
      Q6(7 downto 0) => rd_data(55 downto 48),
      Q7(7 downto 0) => rd_data(63 downto 56),
      Q8(7 downto 0) => rd_data(71 downto 64),
      Q9(7 downto 0) => rd_data(79 downto 72),
      RDCLK => \my_full_reg[4]\,
      RDEN => '1',
      RESET => ififo_rst,
      WRCLK => iserdes_clkdiv,
      WREN => ififo_wr_enable
    );
\of_pre_fifo_gen.u_ddr_of_pre_fifo\: entity work.\mig_mig_7series_v4_2_ddr_of_pre_fifo__parameterized1_34\
     port map (
      D0(7) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_3\,
      D0(6) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_4\,
      D0(5) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_5\,
      D0(4) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_6\,
      D0(3) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_7\,
      D0(2) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_8\,
      D0(1) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_9\,
      D0(0) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_10\,
      D1(7 downto 0) => of_d1(7 downto 0),
      Q(2 downto 0) => Q(2 downto 0),
      \my_empty_reg[1]_0\ => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_1\,
      \my_empty_reg[1]_1\ => \my_empty_reg[1]\,
      \my_empty_reg[7]_0\ => out_fifo_n_3,
      \my_full_reg[4]_0\ => \my_full_reg[4]\,
      ofifo_rst => ofifo_rst,
      ofs_rdy_r_reg => ofs_rdy_r_reg,
      ofs_rdy_r_reg_0 => ofs_rdy_r_reg_0,
      ofs_rdy_r_reg_1 => ofs_rdy_r_reg_1,
      ofs_rdy_r_reg_2 => ofs_rdy_r_reg_2,
      out_fifo => out_fifo_0,
      out_fifo_0(7 downto 0) => out_fifo_1(7 downto 0),
      out_fifo_1 => out_fifo_2,
      \out_fifo_i_75__6\(71 downto 0) => \out_fifo_i_75__6\(71 downto 0),
      phy_data_wr_en => phy_data_wr_en,
      phy_mc_data_full => phy_mc_data_full,
      \rd_ptr_reg[3]_0\(63 downto 0) => \rd_ptr_reg[3]\(63 downto 0)
    );
ofifo_rst_reg: unisim.vcomponents.FDSE
    generic map(
      INIT => '1'
    )
        port map (
      C => \my_full_reg[4]\,
      CE => '1',
      D => ififo_rst_reg_0,
      Q => ofifo_rst,
      S => A_rst_primitives
    );
out_fifo: unisim.vcomponents.OUT_FIFO
    generic map(
      ALMOST_EMPTY_VALUE => 1,
      ALMOST_FULL_VALUE => 1,
      ARRAY_MODE => "ARRAY_MODE_8_X_4",
      OUTPUT_DISABLE => "FALSE",
      SYNCHRONOUS_MODE => "FALSE"
    )
        port map (
      ALMOSTEMPTY => out_fifo_n_0,
      ALMOSTFULL => out_fifo_n_1,
      D0(7) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_3\,
      D0(6) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_4\,
      D0(5) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_5\,
      D0(4) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_6\,
      D0(3) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_7\,
      D0(2) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_8\,
      D0(1) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_9\,
      D0(0) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_10\,
      D1(7 downto 0) => of_d1(7 downto 0),
      D2(7 downto 0) => \my_empty_reg[7]\(7 downto 0),
      D3(7 downto 0) => \my_empty_reg[7]_0\(7 downto 0),
      D4(7 downto 0) => \my_empty_reg[7]_1\(7 downto 0),
      D5(7 downto 0) => \my_empty_reg[7]_2\(7 downto 0),
      D6(7 downto 0) => \my_empty_reg[7]_3\(7 downto 0),
      D7(7 downto 0) => \my_empty_reg[7]_4\(7 downto 0),
      D8(7 downto 0) => \my_empty_reg[7]_5\(7 downto 0),
      D9(7 downto 0) => \my_empty_reg[7]_6\(7 downto 0),
      EMPTY => out_fifo_n_2,
      FULL => out_fifo_n_3,
      Q0(3 downto 0) => of_dqbus(3 downto 0),
      Q1(3 downto 0) => of_dqbus(7 downto 4),
      Q2(3 downto 0) => of_dqbus(11 downto 8),
      Q3(3 downto 0) => of_dqbus(15 downto 12),
      Q4(3 downto 0) => of_dqbus(19 downto 16),
      Q5(7 downto 4) => NLW_out_fifo_Q5_UNCONNECTED(7 downto 4),
      Q5(3 downto 0) => of_dqbus(23 downto 20),
      Q6(7 downto 4) => NLW_out_fifo_Q6_UNCONNECTED(7 downto 4),
      Q6(3 downto 0) => of_dqbus(27 downto 24),
      Q7(3 downto 0) => of_dqbus(31 downto 28),
      Q8(3 downto 0) => of_dqbus(35 downto 32),
      Q9(3 downto 0) => of_dqbus(39 downto 36),
      RDCLK => oserdes_clkdiv,
      RDEN => po_rd_enable,
      RESET => ofifo_rst,
      WRCLK => \my_full_reg[4]\,
      WREN => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_1\
    );
\phaser_in_gen.phaser_in\: unisim.vcomponents.PHASER_IN_PHY
    generic map(
      BURST_MODE => "TRUE",
      CLKOUT_DIV => 2,
      DQS_AUTO_RECAL => '1',
      DQS_BIAS_MODE => "FALSE",
      DQS_FIND_PATTERN => B"000",
      FINE_DELAY => 33,
      FREQ_REF_DIV => "DIV2",
      IS_RST_INVERTED => '0',
      MEMREFCLK_PERIOD => 2.500000,
      OUTPUT_CLK_SRC => "DELAYED_REF",
      PHASEREFCLK_PERIOD => 2.500000,
      REFCLK_PERIOD => 1.250000,
      SEL_CLK_OFFSET => 6,
      SYNC_IN_DIV_RST => "TRUE",
      WR_CYCLES => "FALSE"
    )
        port map (
      BURSTPENDINGPHY => phaser_ctl_bus(1),
      COUNTERLOADEN => \pi_dqs_found_lanes_r1_reg[2]\,
      COUNTERLOADVAL(5 downto 0) => \pi_dqs_found_lanes_r1_reg[2]_3\(5 downto 0),
      COUNTERREADEN => \pi_dqs_found_lanes_r1_reg[2]_0\,
      COUNTERREADVAL(5 downto 0) => A_rst_primitives_reg_0(5 downto 0),
      DQSFOUND => in0(0),
      DQSOUTOFRANGE => \phaser_in_gen.phaser_in_n_1\,
      ENCALIBPHY(1 downto 0) => PCENABLECALIB(1 downto 0),
      FINEENABLE => \pi_dqs_found_lanes_r1_reg[2]_1\,
      FINEINC => \pi_dqs_found_lanes_r1_reg[2]_2\,
      FINEOVERFLOW => \phaser_in_gen.phaser_in_n_2\,
      FREQREFCLK => freq_refclk,
      ICLK => \^a_rst_primitives_reg\,
      ICLKDIV => iserdes_clkdiv,
      ISERDESRST => \phaser_in_gen.phaser_in_n_5\,
      MEMREFCLK => mem_refclk,
      PHASELOCKED => \phaser_in_gen.phaser_in_n_6\,
      PHASEREFCLK => mem_dqs_in(0),
      RANKSELPHY(1 downto 0) => phaser_ctl_bus(3 downto 2),
      RCLK => \phaser_in_gen.phaser_in_n_7\,
      RST => A_rst_primitives,
      RSTDQSFIND => ififo_rst_reg_0,
      SYNCIN => sync_pulse,
      SYSCLK => \my_full_reg[4]\,
      WRENABLE => ififo_wr_enable
    );
phaser_out: unisim.vcomponents.PHASER_OUT_PHY
    generic map(
      CLKOUT_DIV => 2,
      COARSE_BYPASS => "FALSE",
      COARSE_DELAY => 0,
      DATA_CTL_N => "TRUE",
      DATA_RD_CYCLES => "FALSE",
      FINE_DELAY => 60,
      IS_RST_INVERTED => '0',
      MEMREFCLK_PERIOD => 2.500000,
      OCLKDELAY_INV => "FALSE",
      OCLK_DELAY => 0,
      OUTPUT_CLK_SRC => "DELAYED_REF",
      PHASEREFCLK_PERIOD => 1.000000,
      PO => B"111",
      REFCLK_PERIOD => 1.250000,
      SYNC_IN_DIV_RST => "TRUE"
    )
        port map (
      BURSTPENDINGPHY => phaser_ctl_bus(0),
      COARSEENABLE => \po_counter_read_val_reg[8]\,
      COARSEINC => \po_counter_read_val_reg[8]\,
      COARSEOVERFLOW => phaser_out_n_0,
      COUNTERLOADEN => '0',
      COUNTERLOADVAL(8 downto 0) => B"000000000",
      COUNTERREADEN => \pi_dqs_found_lanes_r1_reg[2]_0\,
      COUNTERREADVAL(8 downto 0) => A_rst_primitives_reg_1(8 downto 0),
      CTSBUS(1 downto 0) => oserdes_dqs_ts(1 downto 0),
      DQSBUS(1 downto 0) => oserdes_dqs(1 downto 0),
      DTSBUS(1 downto 0) => oserdes_dq_ts(1 downto 0),
      ENCALIBPHY(1 downto 0) => PCENABLECALIB(1 downto 0),
      FINEENABLE => \po_counter_read_val_reg[8]_0\,
      FINEINC => \po_counter_read_val_reg[8]_1\,
      FINEOVERFLOW => phaser_out_n_1,
      FREQREFCLK => freq_refclk,
      MEMREFCLK => mem_refclk,
      OCLK => oserdes_clk,
      OCLKDELAYED => oserdes_clk_delayed,
      OCLKDIV => oserdes_clkdiv,
      OSERDESRST => po_oserdes_rst,
      PHASEREFCLK => NLW_phaser_out_PHASEREFCLK_UNCONNECTED,
      RDENABLE => po_rd_enable,
      RST => A_rst_primitives,
      SELFINEOCLKDELAY => '0',
      SYNCIN => sync_pulse,
      SYSCLK => \my_full_reg[4]\
    );
pi_phase_locked_all_inferred_i_1: unisim.vcomponents.LUT5
    generic map(
      INIT => X"80000000"
    )
        port map (
      I0 => \phaser_in_gen.phaser_in_n_6\,
      I1 => pi_phase_locked_all_r1_reg,
      I2 => pi_phase_locked_all_r1_reg_0,
      I3 => pi_phase_locked_all_r1_reg_1,
      I4 => pi_phase_locked_all_r1_reg_2,
      O => A_rst_primitives_reg_2
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \mig_mig_7series_v4_2_ddr_byte_lane__parameterized2\ is
  port (
    out_dqs_3 : out STD_LOGIC;
    ts_dqs_3 : out STD_LOGIC;
    A_rst_primitives_reg : out STD_LOGIC;
    mem_dq_out : out STD_LOGIC_VECTOR ( 8 downto 0 );
    mem_dq_ts : out STD_LOGIC_VECTOR ( 8 downto 0 );
    in0 : out STD_LOGIC_VECTOR ( 0 to 0 );
    A_rst_primitives_reg_0 : out STD_LOGIC_VECTOR ( 5 downto 0 );
    A_rst_primitives_reg_1 : out STD_LOGIC_VECTOR ( 8 downto 0 );
    idelay_ld_rst_6 : out STD_LOGIC;
    rst_r4 : out STD_LOGIC;
    \my_empty_reg[1]\ : out STD_LOGIC;
    A_rst_primitives_reg_2 : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_0\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_0\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_0\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_5\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_0\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_6\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_0\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_7\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_0\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_8\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_0\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_9\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_0\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_10\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_0\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_11\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_0\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_12\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_0\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_13\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_0\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_14\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_0\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_15\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_0\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_16\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_0\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_17\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_0\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_18\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_0\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_19\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_0\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_20\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_0\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_21\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_0\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_22\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_0\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_23\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_0\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_24\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_0\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_25\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_0\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_26\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_0\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_27\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_0\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_28\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_0\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_29\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_0\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_30\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_0\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_31\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_0\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_32\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_0\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_33\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_0\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_34\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_0\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_35\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_0\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_36\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_0\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_37\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_0\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_38\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_0\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_39\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_0\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_40\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_0\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_41\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_0\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_42\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_0\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_43\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_0\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_44\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_0\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_45\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_0\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_46\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_0\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_47\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_0\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_48\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_0\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_49\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_0\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_50\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_0\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_51\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_0\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_52\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_0\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_53\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_0\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_54\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_0\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_55\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_0\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_56\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_0\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_57\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_0\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_58\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_0\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_59\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_0\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_60\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_0\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_61\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_0\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_62\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0\ : out STD_LOGIC;
    p_0_out : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_0\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_1\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_2\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_3\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_4\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_5\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_6\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_7\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_8\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_9\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_10\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_11\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_12\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_13\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_14\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_15\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_16\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_17\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_18\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_19\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_20\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_21\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_22\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_23\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_24\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_25\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_26\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_27\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_28\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_29\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_30\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_31\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_32\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_33\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_34\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_35\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_36\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_37\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_38\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_39\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_40\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_41\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_42\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_43\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_44\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_45\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_46\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_47\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_48\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_49\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_50\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_51\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_52\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_53\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_54\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_55\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_56\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_57\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_58\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_59\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_60\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_61\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_3\ : out STD_LOGIC;
    if_empty_v : out STD_LOGIC_VECTOR ( 0 to 0 );
    \rd_ptr_reg[3]\ : out STD_LOGIC_VECTOR ( 63 downto 0 );
    Q : out STD_LOGIC_VECTOR ( 2 downto 0 );
    \entry_cnt_reg[4]\ : in STD_LOGIC;
    \input_[9].iserdes_dq_.iserdesdq\ : in STD_LOGIC;
    mem_dq_in : in STD_LOGIC_VECTOR ( 7 downto 0 );
    idelay_inc : in STD_LOGIC;
    LD0_13 : in STD_LOGIC;
    A_rst_primitives : in STD_LOGIC;
    CLKB0_13 : in STD_LOGIC;
    phaser_ctl_bus : in STD_LOGIC_VECTOR ( 3 downto 0 );
    \pi_dqs_found_lanes_r1_reg[11]\ : in STD_LOGIC;
    \pi_dqs_found_lanes_r1_reg[11]_0\ : in STD_LOGIC;
    \pi_dqs_found_lanes_r1_reg[11]_1\ : in STD_LOGIC;
    \pi_dqs_found_lanes_r1_reg[11]_2\ : in STD_LOGIC;
    freq_refclk : in STD_LOGIC;
    mem_refclk : in STD_LOGIC;
    mem_dqs_in : in STD_LOGIC_VECTOR ( 0 to 0 );
    ififo_rst_reg_0 : in STD_LOGIC;
    sync_pulse : in STD_LOGIC;
    PCENABLECALIB : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \pi_dqs_found_lanes_r1_reg[11]_3\ : in STD_LOGIC_VECTOR ( 5 downto 0 );
    \po_counter_read_val_reg[8]\ : in STD_LOGIC;
    \po_counter_read_val_reg[8]_0\ : in STD_LOGIC;
    \po_counter_read_val_reg[8]_1\ : in STD_LOGIC;
    \my_empty_reg[7]\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \my_empty_reg[7]_0\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \my_empty_reg[7]_1\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \my_empty_reg[7]_2\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \my_empty_reg[7]_3\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \my_empty_reg[7]_4\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \my_empty_reg[7]_5\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \my_empty_reg[7]_6\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    phy_if_reset : in STD_LOGIC;
    \my_full_reg[1]\ : in STD_LOGIC;
    phy_data_wr_en : in STD_LOGIC;
    out_fifo_0 : in STD_LOGIC;
    out_fifo_1 : in STD_LOGIC_VECTOR ( 7 downto 0 );
    out_fifo_2 : in STD_LOGIC;
    pi_phase_locked_all_r1_reg : in STD_LOGIC;
    pi_phase_locked_all_r1_reg_0 : in STD_LOGIC;
    pi_phase_locked_all_r1_reg_1 : in STD_LOGIC;
    \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
    \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg[0]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg[0]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg[0]_1\ : in STD_LOGIC;
    \gen_mux_rd[1].mux_rd_rise0_r1_reg[1]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg[1]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg[1]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg[1]_1\ : in STD_LOGIC;
    \gen_mux_rd[2].mux_rd_rise0_r1_reg[2]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg[2]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg[2]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg[2]_1\ : in STD_LOGIC;
    \gen_mux_rd[3].mux_rd_rise0_r1_reg[3]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg[3]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg[3]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg[3]_1\ : in STD_LOGIC;
    \gen_mux_rd[4].mux_rd_rise0_r1_reg[4]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg[4]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg[4]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg[4]_1\ : in STD_LOGIC;
    \gen_mux_rd[5].mux_rd_rise0_r1_reg[5]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg[5]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg[5]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg[5]_1\ : in STD_LOGIC;
    \gen_mux_rd[6].mux_rd_rise0_r1_reg[6]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg[6]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg[6]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg[6]_1\ : in STD_LOGIC;
    \gen_mux_rd[7].mux_rd_rise0_r1_reg[7]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg[7]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg[7]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg[7]_1\ : in STD_LOGIC;
    \gen_mux_rd[0].mux_rd_fall0_r1_reg[0]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg[0]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg[0]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg[0]_1\ : in STD_LOGIC;
    \gen_mux_rd[1].mux_rd_fall0_r1_reg[1]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg[1]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg[1]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg[1]_1\ : in STD_LOGIC;
    \gen_mux_rd[2].mux_rd_fall0_r1_reg[2]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg[2]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg[2]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg[2]_1\ : in STD_LOGIC;
    \gen_mux_rd[3].mux_rd_fall0_r1_reg[3]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg[3]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg[3]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg[3]_1\ : in STD_LOGIC;
    \gen_mux_rd[4].mux_rd_fall0_r1_reg[4]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg[4]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg[4]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg[4]_1\ : in STD_LOGIC;
    \gen_mux_rd[5].mux_rd_fall0_r1_reg[5]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg[5]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg[5]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg[5]_1\ : in STD_LOGIC;
    \gen_mux_rd[6].mux_rd_fall0_r1_reg[6]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg[6]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg[6]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg[6]_1\ : in STD_LOGIC;
    \gen_mux_rd[7].mux_rd_fall0_r1_reg[7]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg[7]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg[7]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg[7]_1\ : in STD_LOGIC;
    \gen_mux_rd[0].mux_rd_rise1_r1_reg[0]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_1\ : in STD_LOGIC;
    \gen_mux_rd[1].mux_rd_rise1_r1_reg[1]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg[1]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg[1]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg[1]_1\ : in STD_LOGIC;
    \gen_mux_rd[2].mux_rd_rise1_r1_reg[2]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg[2]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg[2]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg[2]_1\ : in STD_LOGIC;
    \gen_mux_rd[3].mux_rd_rise1_r1_reg[3]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg[3]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg[3]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg[3]_1\ : in STD_LOGIC;
    \gen_mux_rd[4].mux_rd_rise1_r1_reg[4]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg[4]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg[4]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg[4]_1\ : in STD_LOGIC;
    \gen_mux_rd[5].mux_rd_rise1_r1_reg[5]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg[5]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg[5]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg[5]_1\ : in STD_LOGIC;
    \gen_mux_rd[6].mux_rd_rise1_r1_reg[6]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg[6]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg[6]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg[6]_1\ : in STD_LOGIC;
    \gen_mux_rd[7].mux_rd_rise1_r1_reg[7]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg[7]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg[7]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg[7]_1\ : in STD_LOGIC;
    \gen_mux_rd[0].mux_rd_fall1_r1_reg[0]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg[0]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg[0]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg[0]_1\ : in STD_LOGIC;
    \gen_mux_rd[1].mux_rd_fall1_r1_reg[1]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg[1]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg[1]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg[1]_1\ : in STD_LOGIC;
    \gen_mux_rd[2].mux_rd_fall1_r1_reg[2]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg[2]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg[2]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg[2]_1\ : in STD_LOGIC;
    \gen_mux_rd[3].mux_rd_fall1_r1_reg[3]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg[3]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg[3]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg[3]_1\ : in STD_LOGIC;
    \gen_mux_rd[4].mux_rd_fall1_r1_reg[4]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg[4]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg[4]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg[4]_1\ : in STD_LOGIC;
    \gen_mux_rd[5].mux_rd_fall1_r1_reg[5]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg[5]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg[5]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg[5]_1\ : in STD_LOGIC;
    \gen_mux_rd[6].mux_rd_fall1_r1_reg[6]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg[6]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg[6]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg[6]_1\ : in STD_LOGIC;
    \gen_mux_rd[7].mux_rd_fall1_r1_reg[7]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg[7]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg[7]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg[7]_1\ : in STD_LOGIC;
    \gen_mux_rd[0].mux_rd_rise2_r1_reg[0]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise2_r_reg[0]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise2_r_reg[0]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise2_r_reg[0]_1\ : in STD_LOGIC;
    \gen_mux_rd[1].mux_rd_rise2_r1_reg[1]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg[1]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg[1]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg[1]_1\ : in STD_LOGIC;
    \gen_mux_rd[2].mux_rd_rise2_r1_reg[2]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg[2]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg[2]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg[2]_1\ : in STD_LOGIC;
    \gen_mux_rd[3].mux_rd_rise2_r1_reg[3]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg[3]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg[3]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg[3]_1\ : in STD_LOGIC;
    \gen_mux_rd[4].mux_rd_rise2_r1_reg[4]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise2_r_reg[4]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise2_r_reg[4]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise2_r_reg[4]_1\ : in STD_LOGIC;
    \gen_mux_rd[5].mux_rd_rise2_r1_reg[5]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg[5]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg[5]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg[5]_1\ : in STD_LOGIC;
    \gen_mux_rd[6].mux_rd_rise2_r1_reg[6]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg[6]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg[6]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg[6]_1\ : in STD_LOGIC;
    \gen_mux_rd[7].mux_rd_rise2_r1_reg[7]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg[7]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg[7]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg[7]_1\ : in STD_LOGIC;
    \gen_mux_rd[0].mux_rd_fall2_r1_reg[0]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg[0]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg[0]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg[0]_1\ : in STD_LOGIC;
    \gen_mux_rd[1].mux_rd_fall2_r1_reg[1]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg[1]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg[1]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg[1]_1\ : in STD_LOGIC;
    \gen_mux_rd[2].mux_rd_fall2_r1_reg[2]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg[2]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg[2]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg[2]_1\ : in STD_LOGIC;
    \gen_mux_rd[3].mux_rd_fall2_r1_reg[3]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg[3]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg[3]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg[3]_1\ : in STD_LOGIC;
    \gen_mux_rd[4].mux_rd_fall2_r1_reg[4]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg[4]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg[4]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg[4]_1\ : in STD_LOGIC;
    \gen_mux_rd[5].mux_rd_fall2_r1_reg[5]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg[5]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg[5]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg[5]_1\ : in STD_LOGIC;
    \gen_mux_rd[6].mux_rd_fall2_r1_reg[6]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg[6]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg[6]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg[6]_1\ : in STD_LOGIC;
    \gen_mux_rd[7].mux_rd_fall2_r1_reg[7]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg[7]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg[7]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg[7]_1\ : in STD_LOGIC;
    \gen_mux_rd[0].mux_rd_rise3_r1_reg[0]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg[0]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg[0]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg[0]_1\ : in STD_LOGIC;
    \gen_mux_rd[1].mux_rd_rise3_r1_reg[1]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg[1]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg[1]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg[1]_1\ : in STD_LOGIC;
    \gen_mux_rd[2].mux_rd_rise3_r1_reg[2]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg[2]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg[2]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg[2]_1\ : in STD_LOGIC;
    \gen_mux_rd[3].mux_rd_rise3_r1_reg[3]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise3_r_reg[3]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise3_r_reg[3]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise3_r_reg[3]_1\ : in STD_LOGIC;
    \gen_mux_rd[4].mux_rd_rise3_r1_reg[4]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg[4]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg[4]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg[4]_1\ : in STD_LOGIC;
    \gen_mux_rd[5].mux_rd_rise3_r1_reg[5]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg[5]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg[5]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg[5]_1\ : in STD_LOGIC;
    \gen_mux_rd[6].mux_rd_rise3_r1_reg[6]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg[6]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg[6]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg[6]_1\ : in STD_LOGIC;
    \gen_mux_rd[7].mux_rd_rise3_r1_reg[7]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise3_r_reg[7]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise3_r_reg[7]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise3_r_reg[7]_1\ : in STD_LOGIC;
    \gen_mux_rd[0].mux_rd_fall3_r1_reg[0]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg[0]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg[0]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg[0]_1\ : in STD_LOGIC;
    \gen_mux_rd[1].mux_rd_fall3_r1_reg[1]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg[1]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg[1]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg[1]_1\ : in STD_LOGIC;
    \gen_mux_rd[2].mux_rd_fall3_r1_reg[2]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg[2]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg[2]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg[2]_1\ : in STD_LOGIC;
    \gen_mux_rd[3].mux_rd_fall3_r1_reg[3]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg[3]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg[3]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg[3]_1\ : in STD_LOGIC;
    \gen_mux_rd[4].mux_rd_fall3_r1_reg[4]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg[4]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg[4]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg[4]_1\ : in STD_LOGIC;
    \gen_mux_rd[5].mux_rd_fall3_r1_reg[5]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg[5]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg[5]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg[5]_1\ : in STD_LOGIC;
    \gen_mux_rd[6].mux_rd_fall3_r1_reg[6]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg[6]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg[6]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg[6]_1\ : in STD_LOGIC;
    \gen_mux_rd[7].mux_rd_fall3_r1_reg[7]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7]_1\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_3\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg[1]_2\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg[2]_2\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg[3]_2\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg[4]_2\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg[5]_2\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg[6]_2\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg[7]_2\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg[0]_2\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg[1]_2\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg[2]_2\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg[3]_2\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg[4]_2\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg[5]_2\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg[6]_2\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7]_2\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg[0]_2\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg[1]_2\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg[2]_2\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg[3]_2\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg[4]_2\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg[5]_2\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg[6]_2\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg[7]_2\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise2_r_reg[0]_2\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg[1]_2\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg[2]_2\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg[3]_2\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise2_r_reg[4]_2\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg[5]_2\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg[6]_2\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg[7]_2\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg[0]_2\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg[1]_2\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg[2]_2\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg[3]_2\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg[4]_2\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg[5]_2\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg[6]_2\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg[7]_2\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg[0]_2\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg[1]_2\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg[2]_2\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise3_r_reg[3]_2\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg[4]_2\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg[5]_2\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg[6]_2\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise3_r_reg[7]_2\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg[0]_2\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg[1]_2\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg[2]_2\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg[3]_2\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg[4]_2\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg[5]_2\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg[6]_2\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg[7]_2\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg[0]_2\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg[1]_2\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg[2]_2\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg[3]_2\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg[4]_2\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg[5]_2\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg[6]_2\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg[7]_2\ : in STD_LOGIC;
    \my_full_reg[1]_0\ : in STD_LOGIC;
    \my_full_reg[1]_1\ : in STD_LOGIC;
    \my_full_reg[1]_2\ : in STD_LOGIC;
    \my_full_reg[1]_3\ : in STD_LOGIC;
    \my_full_reg[1]_4\ : in STD_LOGIC;
    phy_if_empty_r_reg : in STD_LOGIC_VECTOR ( 0 to 0 );
    if_empty_r : in STD_LOGIC_VECTOR ( 0 to 0 );
    phy_if_empty_r_reg_0 : in STD_LOGIC;
    \out_fifo_i_75__3\ : in STD_LOGIC_VECTOR ( 71 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \mig_mig_7series_v4_2_ddr_byte_lane__parameterized2\ : entity is "mig_7series_v4_2_ddr_byte_lane";
end \mig_mig_7series_v4_2_ddr_byte_lane__parameterized2\;

architecture STRUCTURE of \mig_mig_7series_v4_2_ddr_byte_lane__parameterized2\ is
  signal \^a_rst_primitives_reg\ : STD_LOGIC;
  signal if_d2 : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal if_d3 : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal if_d4 : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal if_d5 : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal if_d6 : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal if_d7 : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal if_d8 : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal if_d9 : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \if_empty_\ : STD_LOGIC;
  signal if_empty_r_0 : STD_LOGIC_VECTOR ( 3 to 3 );
  signal ififo_rst : STD_LOGIC;
  signal ififo_wr_enable : STD_LOGIC;
  signal \in_fifo_gen.in_fifo_n_0\ : STD_LOGIC;
  signal \in_fifo_gen.in_fifo_n_1\ : STD_LOGIC;
  signal \in_fifo_gen.in_fifo_n_3\ : STD_LOGIC;
  signal iserdes_clkdiv : STD_LOGIC;
  signal of_d1 : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal of_dqbus : STD_LOGIC_VECTOR ( 39 downto 0 );
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_0\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_2\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_3\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_4\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_5\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_6\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_7\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_8\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_9\ : STD_LOGIC;
  signal ofifo_rst : STD_LOGIC;
  signal oserdes_clk : STD_LOGIC;
  signal oserdes_clk_delayed : STD_LOGIC;
  signal oserdes_clkdiv : STD_LOGIC;
  signal oserdes_dq_ts : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal oserdes_dqs : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal oserdes_dqs_ts : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal out_fifo_n_0 : STD_LOGIC;
  signal out_fifo_n_1 : STD_LOGIC;
  signal out_fifo_n_2 : STD_LOGIC;
  signal out_fifo_n_3 : STD_LOGIC;
  signal \phaser_in_gen.phaser_in_n_1\ : STD_LOGIC;
  signal \phaser_in_gen.phaser_in_n_2\ : STD_LOGIC;
  signal \phaser_in_gen.phaser_in_n_5\ : STD_LOGIC;
  signal \phaser_in_gen.phaser_in_n_6\ : STD_LOGIC;
  signal \phaser_in_gen.phaser_in_n_7\ : STD_LOGIC;
  signal phaser_out_n_0 : STD_LOGIC;
  signal phaser_out_n_1 : STD_LOGIC;
  signal po_oserdes_rst : STD_LOGIC;
  signal po_rd_enable : STD_LOGIC;
  signal rd_data : STD_LOGIC_VECTOR ( 79 downto 0 );
  signal rd_data_r : STD_LOGIC_VECTOR ( 79 downto 12 );
  signal \NLW_in_fifo_gen.in_fifo_D5_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 4 );
  signal \NLW_in_fifo_gen.in_fifo_D6_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 4 );
  signal NLW_out_fifo_Q5_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 4 );
  signal NLW_out_fifo_Q6_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 4 );
  signal NLW_phaser_out_PHASEREFCLK_UNCONNECTED : STD_LOGIC;
  attribute syn_maxfan : string;
  attribute syn_maxfan of \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]\ : label is "3";
  attribute BOX_TYPE : string;
  attribute BOX_TYPE of \in_fifo_gen.in_fifo\ : label is "PRIMITIVE";
  attribute BOX_TYPE of out_fifo : label is "PRIMITIVE";
  attribute BOX_TYPE of \phaser_in_gen.phaser_in\ : label is "PRIMITIVE";
  attribute BOX_TYPE of phaser_out : label is "PRIMITIVE";
begin
  A_rst_primitives_reg <= \^a_rst_primitives_reg\;
ddr_byte_group_io: entity work.\mig_mig_7series_v4_2_ddr_byte_group_io__parameterized0\
     port map (
      A_rst_primitives => A_rst_primitives,
      CLKB0_13 => CLKB0_13,
      CTSBUS(0) => oserdes_dqs_ts(0),
      D2(3 downto 0) => if_d2(3 downto 0),
      D3(3 downto 0) => if_d3(3 downto 0),
      D4(3 downto 0) => if_d4(3 downto 0),
      D5(3 downto 0) => if_d5(3 downto 0),
      D6(3 downto 0) => if_d6(3 downto 0),
      D7(3 downto 0) => if_d7(3 downto 0),
      D8(3 downto 0) => if_d8(3 downto 0),
      D9(3 downto 0) => if_d9(3 downto 0),
      DQSBUS(1 downto 0) => oserdes_dqs(1 downto 0),
      DTSBUS(1 downto 0) => oserdes_dq_ts(1 downto 0),
      LD0_13 => LD0_13,
      \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]\ => \^a_rst_primitives_reg\,
      idelay_inc => idelay_inc,
      idelay_ld_rst_6 => idelay_ld_rst_6,
      idelay_ld_rst_reg_0 => \entry_cnt_reg[4]\,
      \input_[9].iserdes_dq_.iserdesdq_0\ => \input_[9].iserdes_dq_.iserdesdq\,
      iserdes_clkdiv => iserdes_clkdiv,
      mem_dq_in(7 downto 0) => mem_dq_in(7 downto 0),
      mem_dq_out(8 downto 0) => mem_dq_out(8 downto 0),
      mem_dq_ts(8 downto 0) => mem_dq_ts(8 downto 0),
      of_dqbus(35 downto 0) => of_dqbus(39 downto 4),
      oserdes_clk => oserdes_clk,
      oserdes_clk_delayed => oserdes_clk_delayed,
      oserdes_clkdiv => oserdes_clkdiv,
      out_dqs_3 => out_dqs_3,
      po_oserdes_rst => po_oserdes_rst,
      rst_r4 => rst_r4,
      ts_dqs_3 => ts_dqs_3
    );
\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => \if_empty_\,
      Q => if_empty_r_0(3),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => rd_data(12),
      Q => rd_data_r(12),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => rd_data(13),
      Q => rd_data_r(13),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => rd_data(14),
      Q => rd_data_r(14),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => rd_data(15),
      Q => rd_data_r(15),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => rd_data(16),
      Q => rd_data_r(16),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => rd_data(17),
      Q => rd_data_r(17),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => rd_data(18),
      Q => rd_data_r(18),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => rd_data(19),
      Q => rd_data_r(19),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => rd_data(20),
      Q => rd_data_r(20),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => rd_data(21),
      Q => rd_data_r(21),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => rd_data(22),
      Q => rd_data_r(22),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => rd_data(23),
      Q => rd_data_r(23),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => rd_data(24),
      Q => rd_data_r(24),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => rd_data(25),
      Q => rd_data_r(25),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => rd_data(26),
      Q => rd_data_r(26),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => rd_data(27),
      Q => rd_data_r(27),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => rd_data(28),
      Q => rd_data_r(28),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => rd_data(29),
      Q => rd_data_r(29),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => rd_data(30),
      Q => rd_data_r(30),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => rd_data(31),
      Q => rd_data_r(31),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => rd_data(32),
      Q => rd_data_r(32),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => rd_data(33),
      Q => rd_data_r(33),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => rd_data(34),
      Q => rd_data_r(34),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => rd_data(35),
      Q => rd_data_r(35),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => rd_data(36),
      Q => rd_data_r(36),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => rd_data(37),
      Q => rd_data_r(37),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => rd_data(38),
      Q => rd_data_r(38),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => rd_data(39),
      Q => rd_data_r(39),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => rd_data(40),
      Q => rd_data_r(40),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => rd_data(41),
      Q => rd_data_r(41),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => rd_data(42),
      Q => rd_data_r(42),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => rd_data(43),
      Q => rd_data_r(43),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => rd_data(44),
      Q => rd_data_r(44),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => rd_data(45),
      Q => rd_data_r(45),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => rd_data(46),
      Q => rd_data_r(46),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => rd_data(47),
      Q => rd_data_r(47),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => rd_data(48),
      Q => rd_data_r(48),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => rd_data(49),
      Q => rd_data_r(49),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => rd_data(50),
      Q => rd_data_r(50),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => rd_data(51),
      Q => rd_data_r(51),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => rd_data(52),
      Q => rd_data_r(52),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => rd_data(53),
      Q => rd_data_r(53),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => rd_data(54),
      Q => rd_data_r(54),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => rd_data(55),
      Q => rd_data_r(55),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => rd_data(56),
      Q => rd_data_r(56),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => rd_data(57),
      Q => rd_data_r(57),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => rd_data(58),
      Q => rd_data_r(58),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => rd_data(59),
      Q => rd_data_r(59),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => rd_data(60),
      Q => rd_data_r(60),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => rd_data(61),
      Q => rd_data_r(61),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => rd_data(62),
      Q => rd_data_r(62),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => rd_data(63),
      Q => rd_data_r(63),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => rd_data(64),
      Q => rd_data_r(64),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => rd_data(65),
      Q => rd_data_r(65),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => rd_data(66),
      Q => rd_data_r(66),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => rd_data(67),
      Q => rd_data_r(67),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => rd_data(68),
      Q => rd_data_r(68),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => rd_data(69),
      Q => rd_data_r(69),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => rd_data(70),
      Q => rd_data_r(70),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => rd_data(71),
      Q => rd_data_r(71),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => rd_data(72),
      Q => rd_data_r(72),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => rd_data(73),
      Q => rd_data_r(73),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => rd_data(74),
      Q => rd_data_r(74),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => rd_data(75),
      Q => rd_data_r(75),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => rd_data(76),
      Q => rd_data_r(76),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => rd_data(77),
      Q => rd_data_r(77),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => rd_data(78),
      Q => rd_data_r(78),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => rd_data(79),
      Q => rd_data_r(79),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo\: entity work.mig_mig_7series_v4_2_ddr_if_post_fifo
     port map (
      Q(67 downto 0) => rd_data_r(79 downto 12),
      \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]\ => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0\,
      \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0\ => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1\,
      \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1\ => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_2\,
      \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_2\ => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0\,
      \gen_mux_rd[0].mux_rd_fall0_r1_reg[0]\ => \gen_mux_rd[0].mux_rd_fall0_r1_reg[0]\,
      \gen_mux_rd[0].mux_rd_fall1_r1_reg[0]\ => \gen_mux_rd[0].mux_rd_fall1_r1_reg[0]\,
      \gen_mux_rd[0].mux_rd_fall2_r1_reg[0]\ => \gen_mux_rd[0].mux_rd_fall2_r1_reg[0]\,
      \gen_mux_rd[0].mux_rd_fall3_r1_reg[0]\ => \gen_mux_rd[0].mux_rd_fall3_r1_reg[0]\,
      \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]\(2 downto 0) => \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]\(2 downto 0),
      \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]_0\ => \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]_0\,
      \gen_mux_rd[0].mux_rd_rise1_r1_reg[0]\ => \gen_mux_rd[0].mux_rd_rise1_r1_reg[0]\,
      \gen_mux_rd[0].mux_rd_rise2_r1_reg[0]\ => \gen_mux_rd[0].mux_rd_rise2_r1_reg[0]\,
      \gen_mux_rd[0].mux_rd_rise3_r1_reg[0]\ => \gen_mux_rd[0].mux_rd_rise3_r1_reg[0]\,
      \gen_mux_rd[1].mux_rd_fall0_r1_reg[1]\ => \gen_mux_rd[1].mux_rd_fall0_r1_reg[1]\,
      \gen_mux_rd[1].mux_rd_fall1_r1_reg[1]\ => \gen_mux_rd[1].mux_rd_fall1_r1_reg[1]\,
      \gen_mux_rd[1].mux_rd_fall2_r1_reg[1]\ => \gen_mux_rd[1].mux_rd_fall2_r1_reg[1]\,
      \gen_mux_rd[1].mux_rd_fall3_r1_reg[1]\ => \gen_mux_rd[1].mux_rd_fall3_r1_reg[1]\,
      \gen_mux_rd[1].mux_rd_rise0_r1_reg[1]\ => \gen_mux_rd[1].mux_rd_rise0_r1_reg[1]\,
      \gen_mux_rd[1].mux_rd_rise1_r1_reg[1]\ => \gen_mux_rd[1].mux_rd_rise1_r1_reg[1]\,
      \gen_mux_rd[1].mux_rd_rise2_r1_reg[1]\ => \gen_mux_rd[1].mux_rd_rise2_r1_reg[1]\,
      \gen_mux_rd[1].mux_rd_rise3_r1_reg[1]\ => \gen_mux_rd[1].mux_rd_rise3_r1_reg[1]\,
      \gen_mux_rd[2].mux_rd_fall0_r1_reg[2]\ => \gen_mux_rd[2].mux_rd_fall0_r1_reg[2]\,
      \gen_mux_rd[2].mux_rd_fall1_r1_reg[2]\ => \gen_mux_rd[2].mux_rd_fall1_r1_reg[2]\,
      \gen_mux_rd[2].mux_rd_fall2_r1_reg[2]\ => \gen_mux_rd[2].mux_rd_fall2_r1_reg[2]\,
      \gen_mux_rd[2].mux_rd_fall3_r1_reg[2]\ => \gen_mux_rd[2].mux_rd_fall3_r1_reg[2]\,
      \gen_mux_rd[2].mux_rd_rise0_r1_reg[2]\ => \gen_mux_rd[2].mux_rd_rise0_r1_reg[2]\,
      \gen_mux_rd[2].mux_rd_rise1_r1_reg[2]\ => \gen_mux_rd[2].mux_rd_rise1_r1_reg[2]\,
      \gen_mux_rd[2].mux_rd_rise2_r1_reg[2]\ => \gen_mux_rd[2].mux_rd_rise2_r1_reg[2]\,
      \gen_mux_rd[2].mux_rd_rise3_r1_reg[2]\ => \gen_mux_rd[2].mux_rd_rise3_r1_reg[2]\,
      \gen_mux_rd[3].mux_rd_fall0_r1_reg[3]\ => \gen_mux_rd[3].mux_rd_fall0_r1_reg[3]\,
      \gen_mux_rd[3].mux_rd_fall1_r1_reg[3]\ => \gen_mux_rd[3].mux_rd_fall1_r1_reg[3]\,
      \gen_mux_rd[3].mux_rd_fall2_r1_reg[3]\ => \gen_mux_rd[3].mux_rd_fall2_r1_reg[3]\,
      \gen_mux_rd[3].mux_rd_fall3_r1_reg[3]\ => \gen_mux_rd[3].mux_rd_fall3_r1_reg[3]\,
      \gen_mux_rd[3].mux_rd_rise0_r1_reg[3]\ => \gen_mux_rd[3].mux_rd_rise0_r1_reg[3]\,
      \gen_mux_rd[3].mux_rd_rise1_r1_reg[3]\ => \gen_mux_rd[3].mux_rd_rise1_r1_reg[3]\,
      \gen_mux_rd[3].mux_rd_rise2_r1_reg[3]\ => \gen_mux_rd[3].mux_rd_rise2_r1_reg[3]\,
      \gen_mux_rd[3].mux_rd_rise3_r1_reg[3]\ => \gen_mux_rd[3].mux_rd_rise3_r1_reg[3]\,
      \gen_mux_rd[4].mux_rd_fall0_r1_reg[4]\ => \gen_mux_rd[4].mux_rd_fall0_r1_reg[4]\,
      \gen_mux_rd[4].mux_rd_fall1_r1_reg[4]\ => \gen_mux_rd[4].mux_rd_fall1_r1_reg[4]\,
      \gen_mux_rd[4].mux_rd_fall2_r1_reg[4]\ => \gen_mux_rd[4].mux_rd_fall2_r1_reg[4]\,
      \gen_mux_rd[4].mux_rd_fall3_r1_reg[4]\ => \gen_mux_rd[4].mux_rd_fall3_r1_reg[4]\,
      \gen_mux_rd[4].mux_rd_rise0_r1_reg[4]\ => \gen_mux_rd[4].mux_rd_rise0_r1_reg[4]\,
      \gen_mux_rd[4].mux_rd_rise1_r1_reg[4]\ => \gen_mux_rd[4].mux_rd_rise1_r1_reg[4]\,
      \gen_mux_rd[4].mux_rd_rise2_r1_reg[4]\ => \gen_mux_rd[4].mux_rd_rise2_r1_reg[4]\,
      \gen_mux_rd[4].mux_rd_rise3_r1_reg[4]\ => \gen_mux_rd[4].mux_rd_rise3_r1_reg[4]\,
      \gen_mux_rd[5].mux_rd_fall0_r1_reg[5]\ => \gen_mux_rd[5].mux_rd_fall0_r1_reg[5]\,
      \gen_mux_rd[5].mux_rd_fall1_r1_reg[5]\ => \gen_mux_rd[5].mux_rd_fall1_r1_reg[5]\,
      \gen_mux_rd[5].mux_rd_fall2_r1_reg[5]\ => \gen_mux_rd[5].mux_rd_fall2_r1_reg[5]\,
      \gen_mux_rd[5].mux_rd_fall3_r1_reg[5]\ => \gen_mux_rd[5].mux_rd_fall3_r1_reg[5]\,
      \gen_mux_rd[5].mux_rd_rise0_r1_reg[5]\ => \gen_mux_rd[5].mux_rd_rise0_r1_reg[5]\,
      \gen_mux_rd[5].mux_rd_rise1_r1_reg[5]\ => \gen_mux_rd[5].mux_rd_rise1_r1_reg[5]\,
      \gen_mux_rd[5].mux_rd_rise2_r1_reg[5]\ => \gen_mux_rd[5].mux_rd_rise2_r1_reg[5]\,
      \gen_mux_rd[5].mux_rd_rise3_r1_reg[5]\ => \gen_mux_rd[5].mux_rd_rise3_r1_reg[5]\,
      \gen_mux_rd[6].mux_rd_fall0_r1_reg[6]\ => \gen_mux_rd[6].mux_rd_fall0_r1_reg[6]\,
      \gen_mux_rd[6].mux_rd_fall1_r1_reg[6]\ => \gen_mux_rd[6].mux_rd_fall1_r1_reg[6]\,
      \gen_mux_rd[6].mux_rd_fall2_r1_reg[6]\ => \gen_mux_rd[6].mux_rd_fall2_r1_reg[6]\,
      \gen_mux_rd[6].mux_rd_fall3_r1_reg[6]\ => \gen_mux_rd[6].mux_rd_fall3_r1_reg[6]\,
      \gen_mux_rd[6].mux_rd_rise0_r1_reg[6]\ => \gen_mux_rd[6].mux_rd_rise0_r1_reg[6]\,
      \gen_mux_rd[6].mux_rd_rise1_r1_reg[6]\ => \gen_mux_rd[6].mux_rd_rise1_r1_reg[6]\,
      \gen_mux_rd[6].mux_rd_rise2_r1_reg[6]\ => \gen_mux_rd[6].mux_rd_rise2_r1_reg[6]\,
      \gen_mux_rd[6].mux_rd_rise3_r1_reg[6]\ => \gen_mux_rd[6].mux_rd_rise3_r1_reg[6]\,
      \gen_mux_rd[7].mux_rd_fall0_r1_reg[7]\ => \gen_mux_rd[7].mux_rd_fall0_r1_reg[7]\,
      \gen_mux_rd[7].mux_rd_fall1_r1_reg[7]\ => \gen_mux_rd[7].mux_rd_fall1_r1_reg[7]\,
      \gen_mux_rd[7].mux_rd_fall2_r1_reg[7]\ => \gen_mux_rd[7].mux_rd_fall2_r1_reg[7]\,
      \gen_mux_rd[7].mux_rd_fall3_r1_reg[7]\ => \gen_mux_rd[7].mux_rd_fall3_r1_reg[7]\,
      \gen_mux_rd[7].mux_rd_rise0_r1_reg[7]\ => \gen_mux_rd[7].mux_rd_rise0_r1_reg[7]\,
      \gen_mux_rd[7].mux_rd_rise1_r1_reg[7]\ => \gen_mux_rd[7].mux_rd_rise1_r1_reg[7]\,
      \gen_mux_rd[7].mux_rd_rise2_r1_reg[7]\ => \gen_mux_rd[7].mux_rd_rise2_r1_reg[7]\,
      \gen_mux_rd[7].mux_rd_rise3_r1_reg[7]\ => \gen_mux_rd[7].mux_rd_rise3_r1_reg[7]\,
      \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg[0]\ => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg[0]\,
      \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg[0]_0\ => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg[0]_0\,
      \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg[0]_1\ => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg[0]_1\,
      \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg[0]_2\ => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg[0]_2\,
      \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg[0]\ => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg[0]\,
      \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg[0]_0\ => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg[0]_0\,
      \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg[0]_1\ => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg[0]_1\,
      \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg[0]_2\ => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg[0]_2\,
      \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg[0]\ => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg[0]\,
      \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg[0]_0\ => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg[0]_0\,
      \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg[0]_1\ => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg[0]_1\,
      \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg[0]_2\ => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg[0]_2\,
      \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg[0]\ => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg[0]\,
      \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg[0]_0\ => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg[0]_0\,
      \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg[0]_1\ => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg[0]_1\,
      \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg[0]_2\ => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg[0]_2\,
      \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg[0]\ => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg[0]\,
      \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg[0]_0\ => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg[0]_0\,
      \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg[0]_1\ => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg[0]_1\,
      \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg[0]_2\ => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg[0]_2\,
      \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]\ => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]\,
      \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_0\ => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_0\,
      \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_1\ => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_1\,
      \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2\(2 downto 0) => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2\(2 downto 0),
      \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_3\ => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_3\,
      \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise2_r_reg[0]\ => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise2_r_reg[0]\,
      \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise2_r_reg[0]_0\ => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise2_r_reg[0]_0\,
      \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise2_r_reg[0]_1\ => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise2_r_reg[0]_1\,
      \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise2_r_reg[0]_2\ => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise2_r_reg[0]_2\,
      \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg[0]\ => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg[0]\,
      \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg[0]_0\ => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg[0]_0\,
      \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg[0]_1\ => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg[0]_1\,
      \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg[0]_2\ => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg[0]_2\,
      \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg[1]\ => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg[1]\,
      \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg[1]_0\ => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg[1]_0\,
      \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg[1]_1\ => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg[1]_1\,
      \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg[1]_2\ => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg[1]_2\,
      \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg[1]\ => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg[1]\,
      \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg[1]_0\ => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg[1]_0\,
      \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg[1]_1\ => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg[1]_1\,
      \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg[1]_2\ => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg[1]_2\,
      \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg[1]\ => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg[1]\,
      \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg[1]_0\ => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg[1]_0\,
      \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg[1]_1\ => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg[1]_1\,
      \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg[1]_2\ => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg[1]_2\,
      \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg[1]\ => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg[1]\,
      \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg[1]_0\ => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg[1]_0\,
      \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg[1]_1\ => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg[1]_1\,
      \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg[1]_2\ => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg[1]_2\,
      \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg[1]\ => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg[1]\,
      \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg[1]_0\ => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg[1]_0\,
      \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg[1]_1\ => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg[1]_1\,
      \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg[1]_2\ => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg[1]_2\,
      \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg[1]\ => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg[1]\,
      \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg[1]_0\ => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg[1]_0\,
      \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg[1]_1\ => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg[1]_1\,
      \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg[1]_2\ => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg[1]_2\,
      \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg[1]\ => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg[1]\,
      \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg[1]_0\ => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg[1]_0\,
      \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg[1]_1\ => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg[1]_1\,
      \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg[1]_2\ => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg[1]_2\,
      \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg[1]\ => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg[1]\,
      \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg[1]_0\ => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg[1]_0\,
      \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg[1]_1\ => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg[1]_1\,
      \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg[1]_2\ => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg[1]_2\,
      \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg[2]\ => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg[2]\,
      \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg[2]_0\ => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg[2]_0\,
      \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg[2]_1\ => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg[2]_1\,
      \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg[2]_2\ => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg[2]_2\,
      \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg[2]\ => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg[2]\,
      \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg[2]_0\ => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg[2]_0\,
      \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg[2]_1\ => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg[2]_1\,
      \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg[2]_2\ => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg[2]_2\,
      \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg[2]\ => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg[2]\,
      \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg[2]_0\ => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg[2]_0\,
      \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg[2]_1\ => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg[2]_1\,
      \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg[2]_2\ => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg[2]_2\,
      \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg[2]\ => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg[2]\,
      \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg[2]_0\ => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg[2]_0\,
      \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg[2]_1\ => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg[2]_1\,
      \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg[2]_2\ => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg[2]_2\,
      \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg[2]\ => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg[2]\,
      \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg[2]_0\ => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg[2]_0\,
      \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg[2]_1\ => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg[2]_1\,
      \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg[2]_2\ => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg[2]_2\,
      \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg[2]\ => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg[2]\,
      \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg[2]_0\ => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg[2]_0\,
      \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg[2]_1\ => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg[2]_1\,
      \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg[2]_2\ => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg[2]_2\,
      \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg[2]\ => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg[2]\,
      \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg[2]_0\ => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg[2]_0\,
      \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg[2]_1\ => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg[2]_1\,
      \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg[2]_2\ => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg[2]_2\,
      \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg[2]\ => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg[2]\,
      \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg[2]_0\ => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg[2]_0\,
      \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg[2]_1\ => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg[2]_1\,
      \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg[2]_2\ => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg[2]_2\,
      \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg[3]\ => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg[3]\,
      \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg[3]_0\ => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg[3]_0\,
      \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg[3]_1\ => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg[3]_1\,
      \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg[3]_2\ => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg[3]_2\,
      \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg[3]\ => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg[3]\,
      \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg[3]_0\ => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg[3]_0\,
      \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg[3]_1\ => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg[3]_1\,
      \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg[3]_2\ => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg[3]_2\,
      \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg[3]\ => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg[3]\,
      \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg[3]_0\ => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg[3]_0\,
      \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg[3]_1\ => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg[3]_1\,
      \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg[3]_2\ => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg[3]_2\,
      \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg[3]\ => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg[3]\,
      \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg[3]_0\ => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg[3]_0\,
      \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg[3]_1\ => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg[3]_1\,
      \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg[3]_2\ => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg[3]_2\,
      \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg[3]\ => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg[3]\,
      \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg[3]_0\ => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg[3]_0\,
      \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg[3]_1\ => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg[3]_1\,
      \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg[3]_2\ => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg[3]_2\,
      \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg[3]\ => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg[3]\,
      \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg[3]_0\ => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg[3]_0\,
      \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg[3]_1\ => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg[3]_1\,
      \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg[3]_2\ => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg[3]_2\,
      \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg[3]\ => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg[3]\,
      \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg[3]_0\ => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg[3]_0\,
      \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg[3]_1\ => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg[3]_1\,
      \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg[3]_2\ => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg[3]_2\,
      \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise3_r_reg[3]\ => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise3_r_reg[3]\,
      \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise3_r_reg[3]_0\ => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise3_r_reg[3]_0\,
      \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise3_r_reg[3]_1\ => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise3_r_reg[3]_1\,
      \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise3_r_reg[3]_2\ => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise3_r_reg[3]_2\,
      \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg[4]\ => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg[4]\,
      \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg[4]_0\ => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg[4]_0\,
      \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg[4]_1\ => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg[4]_1\,
      \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg[4]_2\ => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg[4]_2\,
      \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg[4]\ => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg[4]\,
      \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg[4]_0\ => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg[4]_0\,
      \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg[4]_1\ => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg[4]_1\,
      \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg[4]_2\ => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg[4]_2\,
      \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg[4]\ => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg[4]\,
      \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg[4]_0\ => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg[4]_0\,
      \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg[4]_1\ => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg[4]_1\,
      \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg[4]_2\ => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg[4]_2\,
      \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg[4]\ => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg[4]\,
      \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg[4]_0\ => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg[4]_0\,
      \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg[4]_1\ => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg[4]_1\,
      \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg[4]_2\ => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg[4]_2\,
      \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg[4]\ => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg[4]\,
      \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg[4]_0\ => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg[4]_0\,
      \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg[4]_1\ => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg[4]_1\,
      \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg[4]_2\ => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg[4]_2\,
      \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg[4]\ => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg[4]\,
      \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg[4]_0\ => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg[4]_0\,
      \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg[4]_1\ => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg[4]_1\,
      \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg[4]_2\ => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg[4]_2\,
      \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise2_r_reg[4]\ => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise2_r_reg[4]\,
      \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise2_r_reg[4]_0\ => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise2_r_reg[4]_0\,
      \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise2_r_reg[4]_1\ => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise2_r_reg[4]_1\,
      \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise2_r_reg[4]_2\ => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise2_r_reg[4]_2\,
      \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg[4]\ => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg[4]\,
      \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg[4]_0\ => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg[4]_0\,
      \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg[4]_1\ => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg[4]_1\,
      \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg[4]_2\ => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg[4]_2\,
      \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg[5]\ => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg[5]\,
      \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg[5]_0\ => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg[5]_0\,
      \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg[5]_1\ => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg[5]_1\,
      \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg[5]_2\ => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg[5]_2\,
      \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg[5]\ => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg[5]\,
      \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg[5]_0\ => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg[5]_0\,
      \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg[5]_1\ => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg[5]_1\,
      \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg[5]_2\ => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg[5]_2\,
      \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg[5]\ => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg[5]\,
      \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg[5]_0\ => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg[5]_0\,
      \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg[5]_1\ => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg[5]_1\,
      \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg[5]_2\ => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg[5]_2\,
      \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg[5]\ => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg[5]\,
      \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg[5]_0\ => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg[5]_0\,
      \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg[5]_1\ => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg[5]_1\,
      \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg[5]_2\ => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg[5]_2\,
      \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg[5]\ => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg[5]\,
      \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg[5]_0\ => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg[5]_0\,
      \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg[5]_1\ => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg[5]_1\,
      \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg[5]_2\ => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg[5]_2\,
      \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg[5]\ => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg[5]\,
      \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg[5]_0\ => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg[5]_0\,
      \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg[5]_1\ => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg[5]_1\,
      \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg[5]_2\ => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg[5]_2\,
      \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg[5]\ => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg[5]\,
      \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg[5]_0\ => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg[5]_0\,
      \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg[5]_1\ => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg[5]_1\,
      \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg[5]_2\ => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg[5]_2\,
      \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg[5]\ => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg[5]\,
      \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg[5]_0\ => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg[5]_0\,
      \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg[5]_1\ => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg[5]_1\,
      \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg[5]_2\ => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg[5]_2\,
      \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg[6]\ => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg[6]\,
      \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg[6]_0\ => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg[6]_0\,
      \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg[6]_1\ => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg[6]_1\,
      \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg[6]_2\ => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg[6]_2\,
      \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg[6]\ => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg[6]\,
      \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg[6]_0\ => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg[6]_0\,
      \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg[6]_1\ => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg[6]_1\,
      \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg[6]_2\ => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg[6]_2\,
      \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg[6]\ => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg[6]\,
      \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg[6]_0\ => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg[6]_0\,
      \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg[6]_1\ => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg[6]_1\,
      \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg[6]_2\ => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg[6]_2\,
      \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg[6]\ => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg[6]\,
      \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg[6]_0\ => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg[6]_0\,
      \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg[6]_1\ => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg[6]_1\,
      \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg[6]_2\ => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg[6]_2\,
      \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg[6]\ => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg[6]\,
      \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg[6]_0\ => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg[6]_0\,
      \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg[6]_1\ => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg[6]_1\,
      \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg[6]_2\ => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg[6]_2\,
      \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg[6]\ => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg[6]\,
      \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg[6]_0\ => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg[6]_0\,
      \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg[6]_1\ => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg[6]_1\,
      \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg[6]_2\ => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg[6]_2\,
      \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg[6]\ => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg[6]\,
      \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg[6]_0\ => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg[6]_0\,
      \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg[6]_1\ => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg[6]_1\,
      \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg[6]_2\ => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg[6]_2\,
      \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg[6]\ => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg[6]\,
      \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg[6]_0\ => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg[6]_0\,
      \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg[6]_1\ => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg[6]_1\,
      \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg[6]_2\ => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg[6]_2\,
      \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg[7]\ => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg[7]\,
      \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg[7]_0\ => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg[7]_0\,
      \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg[7]_1\ => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg[7]_1\,
      \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg[7]_2\ => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg[7]_2\,
      \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg[7]\ => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg[7]\,
      \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg[7]_0\ => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg[7]_0\,
      \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg[7]_1\ => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg[7]_1\,
      \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg[7]_2\ => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg[7]_2\,
      \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg[7]\ => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg[7]\,
      \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg[7]_0\ => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg[7]_0\,
      \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg[7]_1\ => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg[7]_1\,
      \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg[7]_2\ => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg[7]_2\,
      \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7]\ => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7]\,
      \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7]_0\ => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7]_0\,
      \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7]_1\ => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7]_1\,
      \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7]_2\ => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7]_2\,
      \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg[7]\ => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg[7]\,
      \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg[7]_0\ => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg[7]_0\,
      \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg[7]_1\ => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg[7]_1\,
      \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg[7]_2\ => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg[7]_2\,
      \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg[7]\ => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg[7]\,
      \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg[7]_0\ => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg[7]_0\,
      \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg[7]_1\ => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg[7]_1\,
      \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg[7]_2\ => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg[7]_2\,
      \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg[7]\ => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg[7]\,
      \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg[7]_0\ => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg[7]_0\,
      \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg[7]_1\ => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg[7]_1\,
      \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg[7]_2\ => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg[7]_2\,
      \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise3_r_reg[7]\ => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise3_r_reg[7]\,
      \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise3_r_reg[7]_0\ => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise3_r_reg[7]_0\,
      \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise3_r_reg[7]_1\ => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise3_r_reg[7]_1\,
      \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise3_r_reg[7]_2\ => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise3_r_reg[7]_2\,
      if_empty_r(0) => if_empty_r(0),
      if_empty_r_0(0) => if_empty_r_0(3),
      if_empty_v(0) => if_empty_v(0),
      ififo_rst => ififo_rst,
      \my_full_reg[1]_0\ => \my_full_reg[1]\,
      \my_full_reg[1]_1\ => \my_full_reg[1]_0\,
      \my_full_reg[1]_2\ => \my_full_reg[1]_1\,
      \my_full_reg[1]_3\ => \my_full_reg[1]_2\,
      \my_full_reg[1]_4\ => \my_full_reg[1]_3\,
      \my_full_reg[1]_5\ => \my_full_reg[1]_4\,
      p_0_out => p_0_out,
      phy_if_empty_r_reg(0) => phy_if_empty_r_reg(0),
      phy_if_empty_r_reg_0 => phy_if_empty_r_reg_0,
      \po_stg2_wrcal_cnt_reg[2]\ => \po_stg2_wrcal_cnt_reg[2]\,
      \po_stg2_wrcal_cnt_reg[2]_0\ => \po_stg2_wrcal_cnt_reg[2]_0\,
      \po_stg2_wrcal_cnt_reg[2]_1\ => \po_stg2_wrcal_cnt_reg[2]_1\,
      \po_stg2_wrcal_cnt_reg[2]_10\ => \po_stg2_wrcal_cnt_reg[2]_10\,
      \po_stg2_wrcal_cnt_reg[2]_11\ => \po_stg2_wrcal_cnt_reg[2]_11\,
      \po_stg2_wrcal_cnt_reg[2]_12\ => \po_stg2_wrcal_cnt_reg[2]_12\,
      \po_stg2_wrcal_cnt_reg[2]_13\ => \po_stg2_wrcal_cnt_reg[2]_13\,
      \po_stg2_wrcal_cnt_reg[2]_14\ => \po_stg2_wrcal_cnt_reg[2]_14\,
      \po_stg2_wrcal_cnt_reg[2]_15\ => \po_stg2_wrcal_cnt_reg[2]_15\,
      \po_stg2_wrcal_cnt_reg[2]_16\ => \po_stg2_wrcal_cnt_reg[2]_16\,
      \po_stg2_wrcal_cnt_reg[2]_17\ => \po_stg2_wrcal_cnt_reg[2]_17\,
      \po_stg2_wrcal_cnt_reg[2]_18\ => \po_stg2_wrcal_cnt_reg[2]_18\,
      \po_stg2_wrcal_cnt_reg[2]_19\ => \po_stg2_wrcal_cnt_reg[2]_19\,
      \po_stg2_wrcal_cnt_reg[2]_2\ => \po_stg2_wrcal_cnt_reg[2]_2\,
      \po_stg2_wrcal_cnt_reg[2]_20\ => \po_stg2_wrcal_cnt_reg[2]_20\,
      \po_stg2_wrcal_cnt_reg[2]_21\ => \po_stg2_wrcal_cnt_reg[2]_21\,
      \po_stg2_wrcal_cnt_reg[2]_22\ => \po_stg2_wrcal_cnt_reg[2]_22\,
      \po_stg2_wrcal_cnt_reg[2]_23\ => \po_stg2_wrcal_cnt_reg[2]_23\,
      \po_stg2_wrcal_cnt_reg[2]_24\ => \po_stg2_wrcal_cnt_reg[2]_24\,
      \po_stg2_wrcal_cnt_reg[2]_25\ => \po_stg2_wrcal_cnt_reg[2]_25\,
      \po_stg2_wrcal_cnt_reg[2]_26\ => \po_stg2_wrcal_cnt_reg[2]_26\,
      \po_stg2_wrcal_cnt_reg[2]_27\ => \po_stg2_wrcal_cnt_reg[2]_27\,
      \po_stg2_wrcal_cnt_reg[2]_28\ => \po_stg2_wrcal_cnt_reg[2]_28\,
      \po_stg2_wrcal_cnt_reg[2]_29\ => \po_stg2_wrcal_cnt_reg[2]_29\,
      \po_stg2_wrcal_cnt_reg[2]_3\ => \po_stg2_wrcal_cnt_reg[2]_3\,
      \po_stg2_wrcal_cnt_reg[2]_30\ => \po_stg2_wrcal_cnt_reg[2]_30\,
      \po_stg2_wrcal_cnt_reg[2]_31\ => \po_stg2_wrcal_cnt_reg[2]_31\,
      \po_stg2_wrcal_cnt_reg[2]_32\ => \po_stg2_wrcal_cnt_reg[2]_32\,
      \po_stg2_wrcal_cnt_reg[2]_33\ => \po_stg2_wrcal_cnt_reg[2]_33\,
      \po_stg2_wrcal_cnt_reg[2]_34\ => \po_stg2_wrcal_cnt_reg[2]_34\,
      \po_stg2_wrcal_cnt_reg[2]_35\ => \po_stg2_wrcal_cnt_reg[2]_35\,
      \po_stg2_wrcal_cnt_reg[2]_36\ => \po_stg2_wrcal_cnt_reg[2]_36\,
      \po_stg2_wrcal_cnt_reg[2]_37\ => \po_stg2_wrcal_cnt_reg[2]_37\,
      \po_stg2_wrcal_cnt_reg[2]_38\ => \po_stg2_wrcal_cnt_reg[2]_38\,
      \po_stg2_wrcal_cnt_reg[2]_39\ => \po_stg2_wrcal_cnt_reg[2]_39\,
      \po_stg2_wrcal_cnt_reg[2]_4\ => \po_stg2_wrcal_cnt_reg[2]_4\,
      \po_stg2_wrcal_cnt_reg[2]_40\ => \po_stg2_wrcal_cnt_reg[2]_40\,
      \po_stg2_wrcal_cnt_reg[2]_41\ => \po_stg2_wrcal_cnt_reg[2]_41\,
      \po_stg2_wrcal_cnt_reg[2]_42\ => \po_stg2_wrcal_cnt_reg[2]_42\,
      \po_stg2_wrcal_cnt_reg[2]_43\ => \po_stg2_wrcal_cnt_reg[2]_43\,
      \po_stg2_wrcal_cnt_reg[2]_44\ => \po_stg2_wrcal_cnt_reg[2]_44\,
      \po_stg2_wrcal_cnt_reg[2]_45\ => \po_stg2_wrcal_cnt_reg[2]_45\,
      \po_stg2_wrcal_cnt_reg[2]_46\ => \po_stg2_wrcal_cnt_reg[2]_46\,
      \po_stg2_wrcal_cnt_reg[2]_47\ => \po_stg2_wrcal_cnt_reg[2]_47\,
      \po_stg2_wrcal_cnt_reg[2]_48\ => \po_stg2_wrcal_cnt_reg[2]_48\,
      \po_stg2_wrcal_cnt_reg[2]_49\ => \po_stg2_wrcal_cnt_reg[2]_49\,
      \po_stg2_wrcal_cnt_reg[2]_5\ => \po_stg2_wrcal_cnt_reg[2]_5\,
      \po_stg2_wrcal_cnt_reg[2]_50\ => \po_stg2_wrcal_cnt_reg[2]_50\,
      \po_stg2_wrcal_cnt_reg[2]_51\ => \po_stg2_wrcal_cnt_reg[2]_51\,
      \po_stg2_wrcal_cnt_reg[2]_52\ => \po_stg2_wrcal_cnt_reg[2]_52\,
      \po_stg2_wrcal_cnt_reg[2]_53\ => \po_stg2_wrcal_cnt_reg[2]_53\,
      \po_stg2_wrcal_cnt_reg[2]_54\ => \po_stg2_wrcal_cnt_reg[2]_54\,
      \po_stg2_wrcal_cnt_reg[2]_55\ => \po_stg2_wrcal_cnt_reg[2]_55\,
      \po_stg2_wrcal_cnt_reg[2]_56\ => \po_stg2_wrcal_cnt_reg[2]_56\,
      \po_stg2_wrcal_cnt_reg[2]_57\ => \po_stg2_wrcal_cnt_reg[2]_57\,
      \po_stg2_wrcal_cnt_reg[2]_58\ => \po_stg2_wrcal_cnt_reg[2]_58\,
      \po_stg2_wrcal_cnt_reg[2]_59\ => \po_stg2_wrcal_cnt_reg[2]_59\,
      \po_stg2_wrcal_cnt_reg[2]_6\ => \po_stg2_wrcal_cnt_reg[2]_6\,
      \po_stg2_wrcal_cnt_reg[2]_60\ => \po_stg2_wrcal_cnt_reg[2]_60\,
      \po_stg2_wrcal_cnt_reg[2]_61\ => \po_stg2_wrcal_cnt_reg[2]_61\,
      \po_stg2_wrcal_cnt_reg[2]_7\ => \po_stg2_wrcal_cnt_reg[2]_7\,
      \po_stg2_wrcal_cnt_reg[2]_8\ => \po_stg2_wrcal_cnt_reg[2]_8\,
      \po_stg2_wrcal_cnt_reg[2]_9\ => \po_stg2_wrcal_cnt_reg[2]_9\,
      \rd_mux_sel_r_reg[2]\ => \rd_mux_sel_r_reg[2]\,
      \rd_mux_sel_r_reg[2]_0\ => \rd_mux_sel_r_reg[2]_0\,
      \rd_mux_sel_r_reg[2]_1\ => \rd_mux_sel_r_reg[2]_1\,
      \rd_mux_sel_r_reg[2]_10\ => \rd_mux_sel_r_reg[2]_10\,
      \rd_mux_sel_r_reg[2]_11\ => \rd_mux_sel_r_reg[2]_11\,
      \rd_mux_sel_r_reg[2]_12\ => \rd_mux_sel_r_reg[2]_12\,
      \rd_mux_sel_r_reg[2]_13\ => \rd_mux_sel_r_reg[2]_13\,
      \rd_mux_sel_r_reg[2]_14\ => \rd_mux_sel_r_reg[2]_14\,
      \rd_mux_sel_r_reg[2]_15\ => \rd_mux_sel_r_reg[2]_15\,
      \rd_mux_sel_r_reg[2]_16\ => \rd_mux_sel_r_reg[2]_16\,
      \rd_mux_sel_r_reg[2]_17\ => \rd_mux_sel_r_reg[2]_17\,
      \rd_mux_sel_r_reg[2]_18\ => \rd_mux_sel_r_reg[2]_18\,
      \rd_mux_sel_r_reg[2]_19\ => \rd_mux_sel_r_reg[2]_19\,
      \rd_mux_sel_r_reg[2]_2\ => \rd_mux_sel_r_reg[2]_2\,
      \rd_mux_sel_r_reg[2]_20\ => \rd_mux_sel_r_reg[2]_20\,
      \rd_mux_sel_r_reg[2]_21\ => \rd_mux_sel_r_reg[2]_21\,
      \rd_mux_sel_r_reg[2]_22\ => \rd_mux_sel_r_reg[2]_22\,
      \rd_mux_sel_r_reg[2]_23\ => \rd_mux_sel_r_reg[2]_23\,
      \rd_mux_sel_r_reg[2]_24\ => \rd_mux_sel_r_reg[2]_24\,
      \rd_mux_sel_r_reg[2]_25\ => \rd_mux_sel_r_reg[2]_25\,
      \rd_mux_sel_r_reg[2]_26\ => \rd_mux_sel_r_reg[2]_26\,
      \rd_mux_sel_r_reg[2]_27\ => \rd_mux_sel_r_reg[2]_27\,
      \rd_mux_sel_r_reg[2]_28\ => \rd_mux_sel_r_reg[2]_28\,
      \rd_mux_sel_r_reg[2]_29\ => \rd_mux_sel_r_reg[2]_29\,
      \rd_mux_sel_r_reg[2]_3\ => \rd_mux_sel_r_reg[2]_3\,
      \rd_mux_sel_r_reg[2]_30\ => \rd_mux_sel_r_reg[2]_30\,
      \rd_mux_sel_r_reg[2]_31\ => \rd_mux_sel_r_reg[2]_31\,
      \rd_mux_sel_r_reg[2]_32\ => \rd_mux_sel_r_reg[2]_32\,
      \rd_mux_sel_r_reg[2]_33\ => \rd_mux_sel_r_reg[2]_33\,
      \rd_mux_sel_r_reg[2]_34\ => \rd_mux_sel_r_reg[2]_34\,
      \rd_mux_sel_r_reg[2]_35\ => \rd_mux_sel_r_reg[2]_35\,
      \rd_mux_sel_r_reg[2]_36\ => \rd_mux_sel_r_reg[2]_36\,
      \rd_mux_sel_r_reg[2]_37\ => \rd_mux_sel_r_reg[2]_37\,
      \rd_mux_sel_r_reg[2]_38\ => \rd_mux_sel_r_reg[2]_38\,
      \rd_mux_sel_r_reg[2]_39\ => \rd_mux_sel_r_reg[2]_39\,
      \rd_mux_sel_r_reg[2]_4\ => \rd_mux_sel_r_reg[2]_4\,
      \rd_mux_sel_r_reg[2]_40\ => \rd_mux_sel_r_reg[2]_40\,
      \rd_mux_sel_r_reg[2]_41\ => \rd_mux_sel_r_reg[2]_41\,
      \rd_mux_sel_r_reg[2]_42\ => \rd_mux_sel_r_reg[2]_42\,
      \rd_mux_sel_r_reg[2]_43\ => \rd_mux_sel_r_reg[2]_43\,
      \rd_mux_sel_r_reg[2]_44\ => \rd_mux_sel_r_reg[2]_44\,
      \rd_mux_sel_r_reg[2]_45\ => \rd_mux_sel_r_reg[2]_45\,
      \rd_mux_sel_r_reg[2]_46\ => \rd_mux_sel_r_reg[2]_46\,
      \rd_mux_sel_r_reg[2]_47\ => \rd_mux_sel_r_reg[2]_47\,
      \rd_mux_sel_r_reg[2]_48\ => \rd_mux_sel_r_reg[2]_48\,
      \rd_mux_sel_r_reg[2]_49\ => \rd_mux_sel_r_reg[2]_49\,
      \rd_mux_sel_r_reg[2]_5\ => \rd_mux_sel_r_reg[2]_5\,
      \rd_mux_sel_r_reg[2]_50\ => \rd_mux_sel_r_reg[2]_50\,
      \rd_mux_sel_r_reg[2]_51\ => \rd_mux_sel_r_reg[2]_51\,
      \rd_mux_sel_r_reg[2]_52\ => \rd_mux_sel_r_reg[2]_52\,
      \rd_mux_sel_r_reg[2]_53\ => \rd_mux_sel_r_reg[2]_53\,
      \rd_mux_sel_r_reg[2]_54\ => \rd_mux_sel_r_reg[2]_54\,
      \rd_mux_sel_r_reg[2]_55\ => \rd_mux_sel_r_reg[2]_55\,
      \rd_mux_sel_r_reg[2]_56\ => \rd_mux_sel_r_reg[2]_56\,
      \rd_mux_sel_r_reg[2]_57\ => \rd_mux_sel_r_reg[2]_57\,
      \rd_mux_sel_r_reg[2]_58\ => \rd_mux_sel_r_reg[2]_58\,
      \rd_mux_sel_r_reg[2]_59\ => \rd_mux_sel_r_reg[2]_59\,
      \rd_mux_sel_r_reg[2]_6\ => \rd_mux_sel_r_reg[2]_6\,
      \rd_mux_sel_r_reg[2]_60\ => \rd_mux_sel_r_reg[2]_60\,
      \rd_mux_sel_r_reg[2]_61\ => \rd_mux_sel_r_reg[2]_61\,
      \rd_mux_sel_r_reg[2]_62\ => \rd_mux_sel_r_reg[2]_62\,
      \rd_mux_sel_r_reg[2]_7\ => \rd_mux_sel_r_reg[2]_7\,
      \rd_mux_sel_r_reg[2]_8\ => \rd_mux_sel_r_reg[2]_8\,
      \rd_mux_sel_r_reg[2]_9\ => \rd_mux_sel_r_reg[2]_9\,
      \rd_ptr_timing_reg[1]_0\ => \entry_cnt_reg[4]\
    );
ififo_rst_reg: unisim.vcomponents.FDSE
    generic map(
      INIT => '1'
    )
        port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => ififo_rst_reg_0,
      Q => ififo_rst,
      S => phy_if_reset
    );
\in_fifo_gen.in_fifo\: unisim.vcomponents.IN_FIFO
    generic map(
      ALMOST_EMPTY_VALUE => 1,
      ALMOST_FULL_VALUE => 1,
      ARRAY_MODE => "ARRAY_MODE_4_X_8",
      SYNCHRONOUS_MODE => "FALSE"
    )
        port map (
      ALMOSTEMPTY => \in_fifo_gen.in_fifo_n_0\,
      ALMOSTFULL => \in_fifo_gen.in_fifo_n_1\,
      D0(3 downto 0) => B"0000",
      D1(3 downto 0) => B"0000",
      D2(3 downto 0) => if_d2(3 downto 0),
      D3(3 downto 0) => if_d3(3 downto 0),
      D4(3 downto 0) => if_d4(3 downto 0),
      D5(7 downto 4) => \NLW_in_fifo_gen.in_fifo_D5_UNCONNECTED\(7 downto 4),
      D5(3 downto 0) => if_d5(3 downto 0),
      D6(7 downto 4) => \NLW_in_fifo_gen.in_fifo_D6_UNCONNECTED\(7 downto 4),
      D6(3 downto 0) => if_d6(3 downto 0),
      D7(3 downto 0) => if_d7(3 downto 0),
      D8(3 downto 0) => if_d8(3 downto 0),
      D9(3 downto 0) => if_d9(3 downto 0),
      EMPTY => \if_empty_\,
      FULL => \in_fifo_gen.in_fifo_n_3\,
      Q0(7 downto 0) => rd_data(7 downto 0),
      Q1(7 downto 0) => rd_data(15 downto 8),
      Q2(7 downto 0) => rd_data(23 downto 16),
      Q3(7 downto 0) => rd_data(31 downto 24),
      Q4(7 downto 0) => rd_data(39 downto 32),
      Q5(7 downto 0) => rd_data(47 downto 40),
      Q6(7 downto 0) => rd_data(55 downto 48),
      Q7(7 downto 0) => rd_data(63 downto 56),
      Q8(7 downto 0) => rd_data(71 downto 64),
      Q9(7 downto 0) => rd_data(79 downto 72),
      RDCLK => \entry_cnt_reg[4]\,
      RDEN => '1',
      RESET => ififo_rst,
      WRCLK => iserdes_clkdiv,
      WREN => ififo_wr_enable
    );
\of_pre_fifo_gen.u_ddr_of_pre_fifo\: entity work.\mig_mig_7series_v4_2_ddr_of_pre_fifo__parameterized1\
     port map (
      D0(7) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_2\,
      D0(6) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_3\,
      D0(5) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_4\,
      D0(4) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_5\,
      D0(3) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_6\,
      D0(2) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_7\,
      D0(1) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_8\,
      D0(0) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_9\,
      D1(7 downto 0) => of_d1(7 downto 0),
      Q(2 downto 0) => Q(2 downto 0),
      \entry_cnt_reg[4]_0\ => \entry_cnt_reg[4]\,
      \my_empty_reg[1]_0\ => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_0\,
      \my_empty_reg[1]_1\ => \my_empty_reg[1]\,
      \my_empty_reg[7]_0\ => out_fifo_n_3,
      ofifo_rst => ofifo_rst,
      out_fifo => out_fifo_0,
      out_fifo_0(7 downto 0) => out_fifo_1(7 downto 0),
      out_fifo_1 => out_fifo_2,
      \out_fifo_i_75__3\(71 downto 0) => \out_fifo_i_75__3\(71 downto 0),
      phy_data_wr_en => phy_data_wr_en,
      \rd_ptr_reg[3]_0\(63 downto 0) => \rd_ptr_reg[3]\(63 downto 0)
    );
ofifo_rst_reg: unisim.vcomponents.FDSE
    generic map(
      INIT => '1'
    )
        port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => ififo_rst_reg_0,
      Q => ofifo_rst,
      S => A_rst_primitives
    );
out_fifo: unisim.vcomponents.OUT_FIFO
    generic map(
      ALMOST_EMPTY_VALUE => 1,
      ALMOST_FULL_VALUE => 1,
      ARRAY_MODE => "ARRAY_MODE_8_X_4",
      OUTPUT_DISABLE => "FALSE",
      SYNCHRONOUS_MODE => "FALSE"
    )
        port map (
      ALMOSTEMPTY => out_fifo_n_0,
      ALMOSTFULL => out_fifo_n_1,
      D0(7) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_2\,
      D0(6) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_3\,
      D0(5) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_4\,
      D0(4) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_5\,
      D0(3) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_6\,
      D0(2) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_7\,
      D0(1) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_8\,
      D0(0) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_9\,
      D1(7 downto 0) => of_d1(7 downto 0),
      D2(7 downto 0) => \my_empty_reg[7]\(7 downto 0),
      D3(7 downto 0) => \my_empty_reg[7]_0\(7 downto 0),
      D4(7 downto 0) => \my_empty_reg[7]_1\(7 downto 0),
      D5(7 downto 0) => \my_empty_reg[7]_2\(7 downto 0),
      D6(7 downto 0) => \my_empty_reg[7]_3\(7 downto 0),
      D7(7 downto 0) => \my_empty_reg[7]_4\(7 downto 0),
      D8(7 downto 0) => \my_empty_reg[7]_5\(7 downto 0),
      D9(7 downto 0) => \my_empty_reg[7]_6\(7 downto 0),
      EMPTY => out_fifo_n_2,
      FULL => out_fifo_n_3,
      Q0(3 downto 0) => of_dqbus(3 downto 0),
      Q1(3 downto 0) => of_dqbus(7 downto 4),
      Q2(3 downto 0) => of_dqbus(11 downto 8),
      Q3(3 downto 0) => of_dqbus(15 downto 12),
      Q4(3 downto 0) => of_dqbus(19 downto 16),
      Q5(7 downto 4) => NLW_out_fifo_Q5_UNCONNECTED(7 downto 4),
      Q5(3 downto 0) => of_dqbus(23 downto 20),
      Q6(7 downto 4) => NLW_out_fifo_Q6_UNCONNECTED(7 downto 4),
      Q6(3 downto 0) => of_dqbus(27 downto 24),
      Q7(3 downto 0) => of_dqbus(31 downto 28),
      Q8(3 downto 0) => of_dqbus(35 downto 32),
      Q9(3 downto 0) => of_dqbus(39 downto 36),
      RDCLK => oserdes_clkdiv,
      RDEN => po_rd_enable,
      RESET => ofifo_rst,
      WRCLK => \entry_cnt_reg[4]\,
      WREN => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_0\
    );
\phaser_in_gen.phaser_in\: unisim.vcomponents.PHASER_IN_PHY
    generic map(
      BURST_MODE => "TRUE",
      CLKOUT_DIV => 2,
      DQS_AUTO_RECAL => '1',
      DQS_BIAS_MODE => "FALSE",
      DQS_FIND_PATTERN => B"000",
      FINE_DELAY => 33,
      FREQ_REF_DIV => "DIV2",
      IS_RST_INVERTED => '0',
      MEMREFCLK_PERIOD => 2.500000,
      OUTPUT_CLK_SRC => "DELAYED_REF",
      PHASEREFCLK_PERIOD => 2.500000,
      REFCLK_PERIOD => 1.250000,
      SEL_CLK_OFFSET => 6,
      SYNC_IN_DIV_RST => "TRUE",
      WR_CYCLES => "FALSE"
    )
        port map (
      BURSTPENDINGPHY => phaser_ctl_bus(1),
      COUNTERLOADEN => \pi_dqs_found_lanes_r1_reg[11]\,
      COUNTERLOADVAL(5 downto 0) => \pi_dqs_found_lanes_r1_reg[11]_3\(5 downto 0),
      COUNTERREADEN => \pi_dqs_found_lanes_r1_reg[11]_0\,
      COUNTERREADVAL(5 downto 0) => A_rst_primitives_reg_0(5 downto 0),
      DQSFOUND => in0(0),
      DQSOUTOFRANGE => \phaser_in_gen.phaser_in_n_1\,
      ENCALIBPHY(1 downto 0) => PCENABLECALIB(1 downto 0),
      FINEENABLE => \pi_dqs_found_lanes_r1_reg[11]_1\,
      FINEINC => \pi_dqs_found_lanes_r1_reg[11]_2\,
      FINEOVERFLOW => \phaser_in_gen.phaser_in_n_2\,
      FREQREFCLK => freq_refclk,
      ICLK => \^a_rst_primitives_reg\,
      ICLKDIV => iserdes_clkdiv,
      ISERDESRST => \phaser_in_gen.phaser_in_n_5\,
      MEMREFCLK => mem_refclk,
      PHASELOCKED => \phaser_in_gen.phaser_in_n_6\,
      PHASEREFCLK => mem_dqs_in(0),
      RANKSELPHY(1 downto 0) => phaser_ctl_bus(3 downto 2),
      RCLK => \phaser_in_gen.phaser_in_n_7\,
      RST => A_rst_primitives,
      RSTDQSFIND => ififo_rst_reg_0,
      SYNCIN => sync_pulse,
      SYSCLK => \entry_cnt_reg[4]\,
      WRENABLE => ififo_wr_enable
    );
phaser_out: unisim.vcomponents.PHASER_OUT_PHY
    generic map(
      CLKOUT_DIV => 2,
      COARSE_BYPASS => "FALSE",
      COARSE_DELAY => 0,
      DATA_CTL_N => "TRUE",
      DATA_RD_CYCLES => "FALSE",
      FINE_DELAY => 60,
      IS_RST_INVERTED => '0',
      MEMREFCLK_PERIOD => 2.500000,
      OCLKDELAY_INV => "FALSE",
      OCLK_DELAY => 0,
      OUTPUT_CLK_SRC => "DELAYED_REF",
      PHASEREFCLK_PERIOD => 1.000000,
      PO => B"111",
      REFCLK_PERIOD => 1.250000,
      SYNC_IN_DIV_RST => "TRUE"
    )
        port map (
      BURSTPENDINGPHY => phaser_ctl_bus(0),
      COARSEENABLE => \po_counter_read_val_reg[8]\,
      COARSEINC => \po_counter_read_val_reg[8]\,
      COARSEOVERFLOW => phaser_out_n_0,
      COUNTERLOADEN => '0',
      COUNTERLOADVAL(8 downto 0) => B"000000000",
      COUNTERREADEN => \pi_dqs_found_lanes_r1_reg[11]_0\,
      COUNTERREADVAL(8 downto 0) => A_rst_primitives_reg_1(8 downto 0),
      CTSBUS(1 downto 0) => oserdes_dqs_ts(1 downto 0),
      DQSBUS(1 downto 0) => oserdes_dqs(1 downto 0),
      DTSBUS(1 downto 0) => oserdes_dq_ts(1 downto 0),
      ENCALIBPHY(1 downto 0) => PCENABLECALIB(1 downto 0),
      FINEENABLE => \po_counter_read_val_reg[8]_0\,
      FINEINC => \po_counter_read_val_reg[8]_1\,
      FINEOVERFLOW => phaser_out_n_1,
      FREQREFCLK => freq_refclk,
      MEMREFCLK => mem_refclk,
      OCLK => oserdes_clk,
      OCLKDELAYED => oserdes_clk_delayed,
      OCLKDIV => oserdes_clkdiv,
      OSERDESRST => po_oserdes_rst,
      PHASEREFCLK => NLW_phaser_out_PHASEREFCLK_UNCONNECTED,
      RDENABLE => po_rd_enable,
      RST => A_rst_primitives,
      SELFINEOCLKDELAY => '0',
      SYNCIN => sync_pulse,
      SYSCLK => \entry_cnt_reg[4]\
    );
pi_phase_locked_all_inferred_i_2: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8000"
    )
        port map (
      I0 => \phaser_in_gen.phaser_in_n_6\,
      I1 => pi_phase_locked_all_r1_reg,
      I2 => pi_phase_locked_all_r1_reg_0,
      I3 => pi_phase_locked_all_r1_reg_1,
      O => A_rst_primitives_reg_2
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \mig_mig_7series_v4_2_ddr_byte_lane__parameterized2_28\ is
  port (
    out_dqs_7 : out STD_LOGIC;
    ts_dqs_7 : out STD_LOGIC;
    A_rst_primitives_reg : out STD_LOGIC;
    mem_dq_out : out STD_LOGIC_VECTOR ( 8 downto 0 );
    mem_dq_ts : out STD_LOGIC_VECTOR ( 8 downto 0 );
    in0 : out STD_LOGIC_VECTOR ( 0 to 0 );
    A_rst_primitives_reg_0 : out STD_LOGIC;
    A_rst_primitives_reg_1 : out STD_LOGIC_VECTOR ( 5 downto 0 );
    A_rst_primitives_reg_2 : out STD_LOGIC_VECTOR ( 8 downto 0 );
    if_empty_r_0 : out STD_LOGIC_VECTOR ( 0 to 0 );
    \my_empty_reg[4]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    idelay_ld_rst_2 : out STD_LOGIC;
    rst_r4 : out STD_LOGIC;
    \my_empty_reg[1]\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[1]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_0\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[1]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[1]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_0\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[1]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[1]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_0\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[1]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[1]_5\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_0\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[1]_6\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_0\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[1]_7\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_0\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[1]_8\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_0\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[1]_9\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_0\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[1]_10\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_0\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[1]_11\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_0\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[1]_12\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_0\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[1]_13\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_0\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[1]_14\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_0\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[1]_15\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_0\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[1]_16\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_0\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[1]_17\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_0\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[1]_18\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_0\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[1]_19\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_0\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[1]_20\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_0\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[1]_21\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_0\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[1]_22\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_0\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[1]_23\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_0\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[1]_24\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_0\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[1]_25\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_0\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[1]_26\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_0\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[1]_27\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_0\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[1]_28\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_0\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[1]_29\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_0\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[1]_30\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_0\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[1]_31\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_0\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[1]_32\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_0\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[1]_33\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_0\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[1]_34\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_0\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[1]_35\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_0\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[1]_36\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_0\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[1]_37\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_0\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[1]_38\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_0\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[1]_39\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_0\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[1]_40\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_0\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[1]_41\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_0\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[1]_42\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_0\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[1]_43\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_0\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[1]_44\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_0\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[1]_45\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_0\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[1]_46\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_0\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[1]_47\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_0\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[1]_48\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_0\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[1]_49\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_0\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[1]_50\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_0\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[1]_51\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_0\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[1]_52\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_0\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[1]_53\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_0\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[1]_54\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_0\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[1]_55\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_0\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[1]_56\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_0\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[1]_57\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_0\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[1]_58\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_0\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[1]_59\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_0\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[1]_60\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_0\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[1]_61\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_0\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[1]_62\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_0\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_1\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_2\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_3\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_4\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_5\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_6\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_7\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_8\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_9\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_10\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_11\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_12\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_13\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_14\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_15\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_16\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_17\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_18\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_19\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_20\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_21\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_22\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_23\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_24\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_25\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_26\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_27\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_28\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_29\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_30\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_31\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_32\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_33\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_34\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_35\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_36\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_37\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_38\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_39\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_40\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_41\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_42\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_43\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_44\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_45\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_46\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_47\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_48\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_49\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_50\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_51\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_52\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_53\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_54\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_55\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_56\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_57\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_58\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_59\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_60\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_61\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_62\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_3\ : out STD_LOGIC;
    \rd_ptr_reg[3]\ : out STD_LOGIC_VECTOR ( 63 downto 0 );
    Q : out STD_LOGIC_VECTOR ( 2 downto 0 );
    \entry_cnt_reg[4]\ : in STD_LOGIC;
    \input_[9].iserdes_dq_.iserdesdq\ : in STD_LOGIC;
    mem_dq_in : in STD_LOGIC_VECTOR ( 7 downto 0 );
    idelay_inc : in STD_LOGIC;
    LD0_9 : in STD_LOGIC;
    A_rst_primitives : in STD_LOGIC;
    CLKB0_9 : in STD_LOGIC;
    phaser_ctl_bus : in STD_LOGIC_VECTOR ( 3 downto 0 );
    \pi_dqs_found_lanes_r1_reg[3]\ : in STD_LOGIC;
    \pi_dqs_found_lanes_r1_reg[3]_0\ : in STD_LOGIC;
    \pi_dqs_found_lanes_r1_reg[3]_1\ : in STD_LOGIC;
    \pi_dqs_found_lanes_r1_reg[3]_2\ : in STD_LOGIC;
    freq_refclk : in STD_LOGIC;
    mem_refclk : in STD_LOGIC;
    mem_dqs_in : in STD_LOGIC_VECTOR ( 0 to 0 );
    ififo_rst_reg_0 : in STD_LOGIC;
    sync_pulse : in STD_LOGIC;
    PCENABLECALIB : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \pi_dqs_found_lanes_r1_reg[3]_3\ : in STD_LOGIC_VECTOR ( 5 downto 0 );
    \po_counter_read_val_reg[8]\ : in STD_LOGIC;
    \po_counter_read_val_reg[8]_0\ : in STD_LOGIC;
    \po_counter_read_val_reg[8]_1\ : in STD_LOGIC;
    \my_empty_reg[7]\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \my_empty_reg[7]_0\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \my_empty_reg[7]_1\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \my_empty_reg[7]_2\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \my_empty_reg[7]_3\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \my_empty_reg[7]_4\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \my_empty_reg[7]_5\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \my_empty_reg[7]_6\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    phy_if_reset : in STD_LOGIC;
    \my_full_reg[1]\ : in STD_LOGIC;
    phy_data_wr_en : in STD_LOGIC;
    out_fifo_0 : in STD_LOGIC;
    out_fifo_1 : in STD_LOGIC_VECTOR ( 7 downto 0 );
    out_fifo_2 : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg[0]\ : in STD_LOGIC;
    \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg[0]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg[0]_1\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg[1]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg[1]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg[1]_1\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg[2]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg[2]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg[2]_1\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg[3]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg[3]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg[3]_1\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg[4]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg[4]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg[4]_1\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg[5]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg[5]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg[5]_1\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg[6]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg[6]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg[6]_1\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg[7]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg[7]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg[7]_1\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg[0]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg[0]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg[0]_1\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg[1]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg[1]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg[1]_1\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg[2]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg[2]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg[2]_1\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg[3]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg[3]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg[3]_1\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg[4]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg[4]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg[4]_1\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg[5]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg[5]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg[5]_1\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg[6]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg[6]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg[6]_1\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg[7]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg[7]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg[7]_1\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_1\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg[1]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg[1]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg[1]_1\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg[2]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg[2]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg[2]_1\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg[3]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg[3]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg[3]_1\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg[4]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg[4]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg[4]_1\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg[5]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg[5]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg[5]_1\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg[6]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg[6]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg[6]_1\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg[7]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg[7]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg[7]_1\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg[0]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg[0]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg[0]_1\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg[1]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg[1]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg[1]_1\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg[2]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg[2]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg[2]_1\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg[3]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg[3]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg[3]_1\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg[4]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg[4]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg[4]_1\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg[5]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg[5]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg[5]_1\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg[6]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg[6]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg[6]_1\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg[7]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg[7]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg[7]_1\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise2_r_reg[0]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise2_r_reg[0]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise2_r_reg[0]_1\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg[1]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg[1]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg[1]_1\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg[2]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg[2]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg[2]_1\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg[3]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg[3]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg[3]_1\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise2_r_reg[4]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise2_r_reg[4]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise2_r_reg[4]_1\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg[5]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg[5]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg[5]_1\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg[6]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg[6]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg[6]_1\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg[7]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg[7]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg[7]_1\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg[0]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg[0]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg[0]_1\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg[1]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg[1]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg[1]_1\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg[2]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg[2]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg[2]_1\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg[3]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg[3]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg[3]_1\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg[4]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg[4]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg[4]_1\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg[5]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg[5]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg[5]_1\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg[6]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg[6]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg[6]_1\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg[7]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg[7]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg[7]_1\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg[0]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg[0]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg[0]_1\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg[1]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg[1]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg[1]_1\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg[2]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg[2]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg[2]_1\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise3_r_reg[3]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise3_r_reg[3]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise3_r_reg[3]_1\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg[4]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg[4]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg[4]_1\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg[5]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg[5]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg[5]_1\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg[6]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg[6]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg[6]_1\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise3_r_reg[7]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise3_r_reg[7]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise3_r_reg[7]_1\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg[0]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg[0]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg[0]_1\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg[1]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg[1]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg[1]_1\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg[2]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg[2]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg[2]_1\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg[3]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg[3]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg[3]_1\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg[4]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg[4]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg[4]_1\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg[5]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg[5]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg[5]_1\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg[6]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg[6]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg[6]_1\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7]_1\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \my_full_reg[1]_0\ : in STD_LOGIC;
    \my_full_reg[1]_1\ : in STD_LOGIC;
    \my_full_reg[1]_2\ : in STD_LOGIC;
    \my_full_reg[1]_3\ : in STD_LOGIC;
    \my_full_reg[1]_4\ : in STD_LOGIC;
    \my_full_reg[1]_5\ : in STD_LOGIC;
    \my_full_reg[1]_6\ : in STD_LOGIC;
    \my_full_reg[1]_7\ : in STD_LOGIC;
    \wr_ptr[1]_i_2__2\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    if_empty_r : in STD_LOGIC_VECTOR ( 0 to 0 );
    \out_fifo_i_75__7\ : in STD_LOGIC_VECTOR ( 71 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \mig_mig_7series_v4_2_ddr_byte_lane__parameterized2_28\ : entity is "mig_7series_v4_2_ddr_byte_lane";
end \mig_mig_7series_v4_2_ddr_byte_lane__parameterized2_28\;

architecture STRUCTURE of \mig_mig_7series_v4_2_ddr_byte_lane__parameterized2_28\ is
  signal \^a_rst_primitives_reg\ : STD_LOGIC;
  signal if_d2 : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal if_d3 : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal if_d4 : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal if_d5 : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal if_d6 : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal if_d7 : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal if_d8 : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal if_d9 : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \if_empty_\ : STD_LOGIC;
  signal \^if_empty_r_0\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal ififo_rst : STD_LOGIC;
  signal ififo_wr_enable : STD_LOGIC;
  signal \in_fifo_gen.in_fifo_n_0\ : STD_LOGIC;
  signal \in_fifo_gen.in_fifo_n_1\ : STD_LOGIC;
  signal \in_fifo_gen.in_fifo_n_3\ : STD_LOGIC;
  signal iserdes_clkdiv : STD_LOGIC;
  signal of_d1 : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal of_dqbus : STD_LOGIC_VECTOR ( 39 downto 0 );
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_0\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_2\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_3\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_4\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_5\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_6\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_7\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_8\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_9\ : STD_LOGIC;
  signal ofifo_rst : STD_LOGIC;
  signal oserdes_clk : STD_LOGIC;
  signal oserdes_clk_delayed : STD_LOGIC;
  signal oserdes_clkdiv : STD_LOGIC;
  signal oserdes_dq_ts : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal oserdes_dqs : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal oserdes_dqs_ts : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal out_fifo_n_0 : STD_LOGIC;
  signal out_fifo_n_1 : STD_LOGIC;
  signal out_fifo_n_2 : STD_LOGIC;
  signal out_fifo_n_3 : STD_LOGIC;
  signal \phaser_in_gen.phaser_in_n_1\ : STD_LOGIC;
  signal \phaser_in_gen.phaser_in_n_2\ : STD_LOGIC;
  signal \phaser_in_gen.phaser_in_n_5\ : STD_LOGIC;
  signal \phaser_in_gen.phaser_in_n_7\ : STD_LOGIC;
  signal phaser_out_n_0 : STD_LOGIC;
  signal phaser_out_n_1 : STD_LOGIC;
  signal po_oserdes_rst : STD_LOGIC;
  signal po_rd_enable : STD_LOGIC;
  signal rd_data : STD_LOGIC_VECTOR ( 79 downto 0 );
  signal rd_data_r : STD_LOGIC_VECTOR ( 79 downto 12 );
  signal \NLW_in_fifo_gen.in_fifo_D5_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 4 );
  signal \NLW_in_fifo_gen.in_fifo_D6_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 4 );
  signal NLW_out_fifo_Q5_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 4 );
  signal NLW_out_fifo_Q6_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 4 );
  signal NLW_phaser_out_PHASEREFCLK_UNCONNECTED : STD_LOGIC;
  attribute syn_maxfan : string;
  attribute syn_maxfan of \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]\ : label is "3";
  attribute BOX_TYPE : string;
  attribute BOX_TYPE of \in_fifo_gen.in_fifo\ : label is "PRIMITIVE";
  attribute BOX_TYPE of out_fifo : label is "PRIMITIVE";
  attribute BOX_TYPE of \phaser_in_gen.phaser_in\ : label is "PRIMITIVE";
  attribute BOX_TYPE of phaser_out : label is "PRIMITIVE";
begin
  A_rst_primitives_reg <= \^a_rst_primitives_reg\;
  if_empty_r_0(0) <= \^if_empty_r_0\(0);
ddr_byte_group_io: entity work.\mig_mig_7series_v4_2_ddr_byte_group_io__parameterized0_29\
     port map (
      A_rst_primitives => A_rst_primitives,
      CLKB0_9 => CLKB0_9,
      CTSBUS(0) => oserdes_dqs_ts(0),
      D2(3 downto 0) => if_d2(3 downto 0),
      D3(3 downto 0) => if_d3(3 downto 0),
      D4(3 downto 0) => if_d4(3 downto 0),
      D5(3 downto 0) => if_d5(3 downto 0),
      D6(3 downto 0) => if_d6(3 downto 0),
      D7(3 downto 0) => if_d7(3 downto 0),
      D8(3 downto 0) => if_d8(3 downto 0),
      D9(3 downto 0) => if_d9(3 downto 0),
      DQSBUS(1 downto 0) => oserdes_dqs(1 downto 0),
      DTSBUS(1 downto 0) => oserdes_dq_ts(1 downto 0),
      LD0_9 => LD0_9,
      \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]\ => \^a_rst_primitives_reg\,
      idelay_inc => idelay_inc,
      idelay_ld_rst_2 => idelay_ld_rst_2,
      idelay_ld_rst_reg_0 => \entry_cnt_reg[4]\,
      \input_[9].iserdes_dq_.iserdesdq_0\ => \input_[9].iserdes_dq_.iserdesdq\,
      iserdes_clkdiv => iserdes_clkdiv,
      mem_dq_in(7 downto 0) => mem_dq_in(7 downto 0),
      mem_dq_out(8 downto 0) => mem_dq_out(8 downto 0),
      mem_dq_ts(8 downto 0) => mem_dq_ts(8 downto 0),
      of_dqbus(35 downto 0) => of_dqbus(39 downto 4),
      oserdes_clk => oserdes_clk,
      oserdes_clk_delayed => oserdes_clk_delayed,
      oserdes_clkdiv => oserdes_clkdiv,
      out_dqs_7 => out_dqs_7,
      po_oserdes_rst => po_oserdes_rst,
      rst_r4 => rst_r4,
      ts_dqs_7 => ts_dqs_7
    );
\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => \if_empty_\,
      Q => \^if_empty_r_0\(0),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => rd_data(12),
      Q => rd_data_r(12),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => rd_data(13),
      Q => rd_data_r(13),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => rd_data(14),
      Q => rd_data_r(14),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => rd_data(15),
      Q => rd_data_r(15),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => rd_data(16),
      Q => rd_data_r(16),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => rd_data(17),
      Q => rd_data_r(17),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => rd_data(18),
      Q => rd_data_r(18),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => rd_data(19),
      Q => rd_data_r(19),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => rd_data(20),
      Q => rd_data_r(20),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => rd_data(21),
      Q => rd_data_r(21),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => rd_data(22),
      Q => rd_data_r(22),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => rd_data(23),
      Q => rd_data_r(23),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => rd_data(24),
      Q => rd_data_r(24),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => rd_data(25),
      Q => rd_data_r(25),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => rd_data(26),
      Q => rd_data_r(26),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => rd_data(27),
      Q => rd_data_r(27),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => rd_data(28),
      Q => rd_data_r(28),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => rd_data(29),
      Q => rd_data_r(29),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => rd_data(30),
      Q => rd_data_r(30),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => rd_data(31),
      Q => rd_data_r(31),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => rd_data(32),
      Q => rd_data_r(32),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => rd_data(33),
      Q => rd_data_r(33),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => rd_data(34),
      Q => rd_data_r(34),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => rd_data(35),
      Q => rd_data_r(35),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => rd_data(36),
      Q => rd_data_r(36),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => rd_data(37),
      Q => rd_data_r(37),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => rd_data(38),
      Q => rd_data_r(38),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => rd_data(39),
      Q => rd_data_r(39),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => rd_data(40),
      Q => rd_data_r(40),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => rd_data(41),
      Q => rd_data_r(41),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => rd_data(42),
      Q => rd_data_r(42),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => rd_data(43),
      Q => rd_data_r(43),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => rd_data(44),
      Q => rd_data_r(44),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => rd_data(45),
      Q => rd_data_r(45),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => rd_data(46),
      Q => rd_data_r(46),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => rd_data(47),
      Q => rd_data_r(47),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => rd_data(48),
      Q => rd_data_r(48),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => rd_data(49),
      Q => rd_data_r(49),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => rd_data(50),
      Q => rd_data_r(50),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => rd_data(51),
      Q => rd_data_r(51),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => rd_data(52),
      Q => rd_data_r(52),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => rd_data(53),
      Q => rd_data_r(53),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => rd_data(54),
      Q => rd_data_r(54),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => rd_data(55),
      Q => rd_data_r(55),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => rd_data(56),
      Q => rd_data_r(56),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => rd_data(57),
      Q => rd_data_r(57),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => rd_data(58),
      Q => rd_data_r(58),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => rd_data(59),
      Q => rd_data_r(59),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => rd_data(60),
      Q => rd_data_r(60),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => rd_data(61),
      Q => rd_data_r(61),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => rd_data(62),
      Q => rd_data_r(62),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => rd_data(63),
      Q => rd_data_r(63),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => rd_data(64),
      Q => rd_data_r(64),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => rd_data(65),
      Q => rd_data_r(65),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => rd_data(66),
      Q => rd_data_r(66),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => rd_data(67),
      Q => rd_data_r(67),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => rd_data(68),
      Q => rd_data_r(68),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => rd_data(69),
      Q => rd_data_r(69),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => rd_data(70),
      Q => rd_data_r(70),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => rd_data(71),
      Q => rd_data_r(71),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => rd_data(72),
      Q => rd_data_r(72),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => rd_data(73),
      Q => rd_data_r(73),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => rd_data(74),
      Q => rd_data_r(74),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => rd_data(75),
      Q => rd_data_r(75),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => rd_data(76),
      Q => rd_data_r(76),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => rd_data(77),
      Q => rd_data_r(77),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => rd_data(78),
      Q => rd_data_r(78),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => rd_data(79),
      Q => rd_data_r(79),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo\: entity work.mig_mig_7series_v4_2_ddr_if_post_fifo_30
     port map (
      Q(67 downto 0) => rd_data_r(79 downto 12),
      \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]\ => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0\,
      \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0\ => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1\,
      \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1\ => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_2\,
      \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_2\ => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0\,
      \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]\(1 downto 0) => \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]\(1 downto 0),
      \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg[0]\ => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg[0]\,
      \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg[0]_0\ => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg[0]_0\,
      \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg[0]_1\ => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg[0]_1\,
      \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg[0]\ => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg[0]\,
      \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg[0]_0\ => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg[0]_0\,
      \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg[0]_1\ => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg[0]_1\,
      \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg[0]\ => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg[0]\,
      \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg[0]_0\ => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg[0]_0\,
      \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg[0]_1\ => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg[0]_1\,
      \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg[0]\ => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg[0]\,
      \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg[0]_0\ => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg[0]_0\,
      \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg[0]_1\ => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg[0]_1\,
      \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg[0]\ => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg[0]\,
      \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg[0]_0\ => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg[0]_0\,
      \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg[0]_1\ => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg[0]_1\,
      \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]\ => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]\,
      \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_0\ => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_0\,
      \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_1\ => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_1\,
      \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2\(1 downto 0) => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2\(1 downto 0),
      \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise2_r_reg[0]\ => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise2_r_reg[0]\,
      \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise2_r_reg[0]_0\ => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise2_r_reg[0]_0\,
      \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise2_r_reg[0]_1\ => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise2_r_reg[0]_1\,
      \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg[0]\ => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg[0]\,
      \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg[0]_0\ => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg[0]_0\,
      \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg[0]_1\ => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg[0]_1\,
      \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg[1]\ => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg[1]\,
      \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg[1]_0\ => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg[1]_0\,
      \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg[1]_1\ => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg[1]_1\,
      \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg[1]\ => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg[1]\,
      \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg[1]_0\ => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg[1]_0\,
      \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg[1]_1\ => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg[1]_1\,
      \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg[1]\ => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg[1]\,
      \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg[1]_0\ => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg[1]_0\,
      \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg[1]_1\ => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg[1]_1\,
      \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg[1]\ => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg[1]\,
      \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg[1]_0\ => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg[1]_0\,
      \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg[1]_1\ => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg[1]_1\,
      \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg[1]\ => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg[1]\,
      \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg[1]_0\ => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg[1]_0\,
      \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg[1]_1\ => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg[1]_1\,
      \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg[1]\ => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg[1]\,
      \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg[1]_0\ => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg[1]_0\,
      \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg[1]_1\ => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg[1]_1\,
      \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg[1]\ => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg[1]\,
      \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg[1]_0\ => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg[1]_0\,
      \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg[1]_1\ => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg[1]_1\,
      \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg[1]\ => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg[1]\,
      \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg[1]_0\ => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg[1]_0\,
      \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg[1]_1\ => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg[1]_1\,
      \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg[2]\ => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg[2]\,
      \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg[2]_0\ => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg[2]_0\,
      \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg[2]_1\ => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg[2]_1\,
      \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg[2]\ => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg[2]\,
      \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg[2]_0\ => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg[2]_0\,
      \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg[2]_1\ => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg[2]_1\,
      \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg[2]\ => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg[2]\,
      \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg[2]_0\ => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg[2]_0\,
      \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg[2]_1\ => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg[2]_1\,
      \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg[2]\ => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg[2]\,
      \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg[2]_0\ => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg[2]_0\,
      \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg[2]_1\ => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg[2]_1\,
      \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg[2]\ => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg[2]\,
      \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg[2]_0\ => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg[2]_0\,
      \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg[2]_1\ => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg[2]_1\,
      \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg[2]\ => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg[2]\,
      \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg[2]_0\ => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg[2]_0\,
      \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg[2]_1\ => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg[2]_1\,
      \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg[2]\ => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg[2]\,
      \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg[2]_0\ => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg[2]_0\,
      \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg[2]_1\ => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg[2]_1\,
      \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg[2]\ => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg[2]\,
      \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg[2]_0\ => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg[2]_0\,
      \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg[2]_1\ => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg[2]_1\,
      \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg[3]\ => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg[3]\,
      \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg[3]_0\ => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg[3]_0\,
      \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg[3]_1\ => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg[3]_1\,
      \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg[3]\ => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg[3]\,
      \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg[3]_0\ => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg[3]_0\,
      \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg[3]_1\ => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg[3]_1\,
      \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg[3]\ => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg[3]\,
      \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg[3]_0\ => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg[3]_0\,
      \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg[3]_1\ => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg[3]_1\,
      \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg[3]\ => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg[3]\,
      \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg[3]_0\ => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg[3]_0\,
      \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg[3]_1\ => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg[3]_1\,
      \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg[3]\ => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg[3]\,
      \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg[3]_0\ => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg[3]_0\,
      \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg[3]_1\ => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg[3]_1\,
      \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg[3]\ => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg[3]\,
      \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg[3]_0\ => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg[3]_0\,
      \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg[3]_1\ => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg[3]_1\,
      \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg[3]\ => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg[3]\,
      \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg[3]_0\ => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg[3]_0\,
      \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg[3]_1\ => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg[3]_1\,
      \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise3_r_reg[3]\ => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise3_r_reg[3]\,
      \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise3_r_reg[3]_0\ => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise3_r_reg[3]_0\,
      \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise3_r_reg[3]_1\ => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise3_r_reg[3]_1\,
      \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg[4]\ => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg[4]\,
      \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg[4]_0\ => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg[4]_0\,
      \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg[4]_1\ => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg[4]_1\,
      \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg[4]\ => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg[4]\,
      \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg[4]_0\ => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg[4]_0\,
      \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg[4]_1\ => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg[4]_1\,
      \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg[4]\ => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg[4]\,
      \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg[4]_0\ => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg[4]_0\,
      \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg[4]_1\ => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg[4]_1\,
      \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg[4]\ => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg[4]\,
      \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg[4]_0\ => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg[4]_0\,
      \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg[4]_1\ => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg[4]_1\,
      \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg[4]\ => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg[4]\,
      \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg[4]_0\ => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg[4]_0\,
      \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg[4]_1\ => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg[4]_1\,
      \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg[4]\ => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg[4]\,
      \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg[4]_0\ => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg[4]_0\,
      \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg[4]_1\ => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg[4]_1\,
      \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise2_r_reg[4]\ => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise2_r_reg[4]\,
      \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise2_r_reg[4]_0\ => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise2_r_reg[4]_0\,
      \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise2_r_reg[4]_1\ => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise2_r_reg[4]_1\,
      \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg[4]\ => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg[4]\,
      \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg[4]_0\ => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg[4]_0\,
      \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg[4]_1\ => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg[4]_1\,
      \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg[5]\ => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg[5]\,
      \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg[5]_0\ => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg[5]_0\,
      \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg[5]_1\ => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg[5]_1\,
      \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg[5]\ => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg[5]\,
      \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg[5]_0\ => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg[5]_0\,
      \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg[5]_1\ => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg[5]_1\,
      \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg[5]\ => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg[5]\,
      \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg[5]_0\ => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg[5]_0\,
      \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg[5]_1\ => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg[5]_1\,
      \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg[5]\ => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg[5]\,
      \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg[5]_0\ => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg[5]_0\,
      \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg[5]_1\ => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg[5]_1\,
      \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg[5]\ => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg[5]\,
      \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg[5]_0\ => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg[5]_0\,
      \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg[5]_1\ => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg[5]_1\,
      \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg[5]\ => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg[5]\,
      \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg[5]_0\ => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg[5]_0\,
      \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg[5]_1\ => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg[5]_1\,
      \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg[5]\ => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg[5]\,
      \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg[5]_0\ => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg[5]_0\,
      \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg[5]_1\ => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg[5]_1\,
      \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg[5]\ => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg[5]\,
      \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg[5]_0\ => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg[5]_0\,
      \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg[5]_1\ => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg[5]_1\,
      \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg[6]\ => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg[6]\,
      \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg[6]_0\ => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg[6]_0\,
      \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg[6]_1\ => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg[6]_1\,
      \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg[6]\ => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg[6]\,
      \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg[6]_0\ => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg[6]_0\,
      \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg[6]_1\ => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg[6]_1\,
      \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg[6]\ => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg[6]\,
      \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg[6]_0\ => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg[6]_0\,
      \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg[6]_1\ => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg[6]_1\,
      \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg[6]\ => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg[6]\,
      \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg[6]_0\ => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg[6]_0\,
      \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg[6]_1\ => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg[6]_1\,
      \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg[6]\ => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg[6]\,
      \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg[6]_0\ => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg[6]_0\,
      \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg[6]_1\ => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg[6]_1\,
      \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg[6]\ => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg[6]\,
      \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg[6]_0\ => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg[6]_0\,
      \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg[6]_1\ => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg[6]_1\,
      \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg[6]\ => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg[6]\,
      \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg[6]_0\ => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg[6]_0\,
      \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg[6]_1\ => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg[6]_1\,
      \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg[6]\ => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg[6]\,
      \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg[6]_0\ => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg[6]_0\,
      \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg[6]_1\ => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg[6]_1\,
      \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg[7]\ => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg[7]\,
      \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg[7]_0\ => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg[7]_0\,
      \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg[7]_1\ => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg[7]_1\,
      \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg[7]\ => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg[7]\,
      \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg[7]_0\ => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg[7]_0\,
      \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg[7]_1\ => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg[7]_1\,
      \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg[7]\ => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg[7]\,
      \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg[7]_0\ => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg[7]_0\,
      \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg[7]_1\ => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg[7]_1\,
      \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7]\ => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7]\,
      \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7]_0\ => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7]_0\,
      \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7]_1\ => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7]_1\,
      \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg[7]\ => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg[7]\,
      \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg[7]_0\ => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg[7]_0\,
      \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg[7]_1\ => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg[7]_1\,
      \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg[7]\ => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg[7]\,
      \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg[7]_0\ => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg[7]_0\,
      \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg[7]_1\ => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg[7]_1\,
      \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg[7]\ => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg[7]\,
      \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg[7]_0\ => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg[7]_0\,
      \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg[7]_1\ => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg[7]_1\,
      \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise3_r_reg[7]\ => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise3_r_reg[7]\,
      \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise3_r_reg[7]_0\ => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise3_r_reg[7]_0\,
      \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise3_r_reg[7]_1\ => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise3_r_reg[7]_1\,
      if_empty_r(0) => if_empty_r(0),
      ififo_rst => ififo_rst,
      \my_empty_reg[4]_0\ => \my_empty_reg[4]\(0),
      \my_empty_reg[4]_1\(0) => \my_empty_reg[4]\(1),
      \my_full_reg[1]_0\ => \^if_empty_r_0\(0),
      \my_full_reg[1]_1\ => \my_full_reg[1]\,
      \my_full_reg[1]_2\ => \my_full_reg[1]_0\,
      \my_full_reg[1]_3\ => \my_full_reg[1]_1\,
      \my_full_reg[1]_4\ => \my_full_reg[1]_2\,
      \my_full_reg[1]_5\ => \my_full_reg[1]_3\,
      \my_full_reg[1]_6\ => \my_full_reg[1]_4\,
      \my_full_reg[1]_7\ => \my_full_reg[1]_5\,
      \my_full_reg[1]_8\ => \my_full_reg[1]_6\,
      \my_full_reg[1]_9\ => \my_full_reg[1]_7\,
      \po_stg2_wrcal_cnt_reg[1]\ => \po_stg2_wrcal_cnt_reg[1]\,
      \po_stg2_wrcal_cnt_reg[1]_0\ => \po_stg2_wrcal_cnt_reg[1]_0\,
      \po_stg2_wrcal_cnt_reg[1]_1\ => \po_stg2_wrcal_cnt_reg[1]_1\,
      \po_stg2_wrcal_cnt_reg[1]_10\ => \po_stg2_wrcal_cnt_reg[1]_10\,
      \po_stg2_wrcal_cnt_reg[1]_11\ => \po_stg2_wrcal_cnt_reg[1]_11\,
      \po_stg2_wrcal_cnt_reg[1]_12\ => \po_stg2_wrcal_cnt_reg[1]_12\,
      \po_stg2_wrcal_cnt_reg[1]_13\ => \po_stg2_wrcal_cnt_reg[1]_13\,
      \po_stg2_wrcal_cnt_reg[1]_14\ => \po_stg2_wrcal_cnt_reg[1]_14\,
      \po_stg2_wrcal_cnt_reg[1]_15\ => \po_stg2_wrcal_cnt_reg[1]_15\,
      \po_stg2_wrcal_cnt_reg[1]_16\ => \po_stg2_wrcal_cnt_reg[1]_16\,
      \po_stg2_wrcal_cnt_reg[1]_17\ => \po_stg2_wrcal_cnt_reg[1]_17\,
      \po_stg2_wrcal_cnt_reg[1]_18\ => \po_stg2_wrcal_cnt_reg[1]_18\,
      \po_stg2_wrcal_cnt_reg[1]_19\ => \po_stg2_wrcal_cnt_reg[1]_19\,
      \po_stg2_wrcal_cnt_reg[1]_2\ => \po_stg2_wrcal_cnt_reg[1]_2\,
      \po_stg2_wrcal_cnt_reg[1]_20\ => \po_stg2_wrcal_cnt_reg[1]_20\,
      \po_stg2_wrcal_cnt_reg[1]_21\ => \po_stg2_wrcal_cnt_reg[1]_21\,
      \po_stg2_wrcal_cnt_reg[1]_22\ => \po_stg2_wrcal_cnt_reg[1]_22\,
      \po_stg2_wrcal_cnt_reg[1]_23\ => \po_stg2_wrcal_cnt_reg[1]_23\,
      \po_stg2_wrcal_cnt_reg[1]_24\ => \po_stg2_wrcal_cnt_reg[1]_24\,
      \po_stg2_wrcal_cnt_reg[1]_25\ => \po_stg2_wrcal_cnt_reg[1]_25\,
      \po_stg2_wrcal_cnt_reg[1]_26\ => \po_stg2_wrcal_cnt_reg[1]_26\,
      \po_stg2_wrcal_cnt_reg[1]_27\ => \po_stg2_wrcal_cnt_reg[1]_27\,
      \po_stg2_wrcal_cnt_reg[1]_28\ => \po_stg2_wrcal_cnt_reg[1]_28\,
      \po_stg2_wrcal_cnt_reg[1]_29\ => \po_stg2_wrcal_cnt_reg[1]_29\,
      \po_stg2_wrcal_cnt_reg[1]_3\ => \po_stg2_wrcal_cnt_reg[1]_3\,
      \po_stg2_wrcal_cnt_reg[1]_30\ => \po_stg2_wrcal_cnt_reg[1]_30\,
      \po_stg2_wrcal_cnt_reg[1]_31\ => \po_stg2_wrcal_cnt_reg[1]_31\,
      \po_stg2_wrcal_cnt_reg[1]_32\ => \po_stg2_wrcal_cnt_reg[1]_32\,
      \po_stg2_wrcal_cnt_reg[1]_33\ => \po_stg2_wrcal_cnt_reg[1]_33\,
      \po_stg2_wrcal_cnt_reg[1]_34\ => \po_stg2_wrcal_cnt_reg[1]_34\,
      \po_stg2_wrcal_cnt_reg[1]_35\ => \po_stg2_wrcal_cnt_reg[1]_35\,
      \po_stg2_wrcal_cnt_reg[1]_36\ => \po_stg2_wrcal_cnt_reg[1]_36\,
      \po_stg2_wrcal_cnt_reg[1]_37\ => \po_stg2_wrcal_cnt_reg[1]_37\,
      \po_stg2_wrcal_cnt_reg[1]_38\ => \po_stg2_wrcal_cnt_reg[1]_38\,
      \po_stg2_wrcal_cnt_reg[1]_39\ => \po_stg2_wrcal_cnt_reg[1]_39\,
      \po_stg2_wrcal_cnt_reg[1]_4\ => \po_stg2_wrcal_cnt_reg[1]_4\,
      \po_stg2_wrcal_cnt_reg[1]_40\ => \po_stg2_wrcal_cnt_reg[1]_40\,
      \po_stg2_wrcal_cnt_reg[1]_41\ => \po_stg2_wrcal_cnt_reg[1]_41\,
      \po_stg2_wrcal_cnt_reg[1]_42\ => \po_stg2_wrcal_cnt_reg[1]_42\,
      \po_stg2_wrcal_cnt_reg[1]_43\ => \po_stg2_wrcal_cnt_reg[1]_43\,
      \po_stg2_wrcal_cnt_reg[1]_44\ => \po_stg2_wrcal_cnt_reg[1]_44\,
      \po_stg2_wrcal_cnt_reg[1]_45\ => \po_stg2_wrcal_cnt_reg[1]_45\,
      \po_stg2_wrcal_cnt_reg[1]_46\ => \po_stg2_wrcal_cnt_reg[1]_46\,
      \po_stg2_wrcal_cnt_reg[1]_47\ => \po_stg2_wrcal_cnt_reg[1]_47\,
      \po_stg2_wrcal_cnt_reg[1]_48\ => \po_stg2_wrcal_cnt_reg[1]_48\,
      \po_stg2_wrcal_cnt_reg[1]_49\ => \po_stg2_wrcal_cnt_reg[1]_49\,
      \po_stg2_wrcal_cnt_reg[1]_5\ => \po_stg2_wrcal_cnt_reg[1]_5\,
      \po_stg2_wrcal_cnt_reg[1]_50\ => \po_stg2_wrcal_cnt_reg[1]_50\,
      \po_stg2_wrcal_cnt_reg[1]_51\ => \po_stg2_wrcal_cnt_reg[1]_51\,
      \po_stg2_wrcal_cnt_reg[1]_52\ => \po_stg2_wrcal_cnt_reg[1]_52\,
      \po_stg2_wrcal_cnt_reg[1]_53\ => \po_stg2_wrcal_cnt_reg[1]_53\,
      \po_stg2_wrcal_cnt_reg[1]_54\ => \po_stg2_wrcal_cnt_reg[1]_54\,
      \po_stg2_wrcal_cnt_reg[1]_55\ => \po_stg2_wrcal_cnt_reg[1]_55\,
      \po_stg2_wrcal_cnt_reg[1]_56\ => \po_stg2_wrcal_cnt_reg[1]_56\,
      \po_stg2_wrcal_cnt_reg[1]_57\ => \po_stg2_wrcal_cnt_reg[1]_57\,
      \po_stg2_wrcal_cnt_reg[1]_58\ => \po_stg2_wrcal_cnt_reg[1]_58\,
      \po_stg2_wrcal_cnt_reg[1]_59\ => \po_stg2_wrcal_cnt_reg[1]_59\,
      \po_stg2_wrcal_cnt_reg[1]_6\ => \po_stg2_wrcal_cnt_reg[1]_6\,
      \po_stg2_wrcal_cnt_reg[1]_60\ => \po_stg2_wrcal_cnt_reg[1]_60\,
      \po_stg2_wrcal_cnt_reg[1]_61\ => \po_stg2_wrcal_cnt_reg[1]_61\,
      \po_stg2_wrcal_cnt_reg[1]_62\ => \po_stg2_wrcal_cnt_reg[1]_62\,
      \po_stg2_wrcal_cnt_reg[1]_7\ => \po_stg2_wrcal_cnt_reg[1]_7\,
      \po_stg2_wrcal_cnt_reg[1]_8\ => \po_stg2_wrcal_cnt_reg[1]_8\,
      \po_stg2_wrcal_cnt_reg[1]_9\ => \po_stg2_wrcal_cnt_reg[1]_9\,
      \rd_mux_sel_r_reg[1]\ => \rd_mux_sel_r_reg[1]\,
      \rd_mux_sel_r_reg[1]_0\ => \rd_mux_sel_r_reg[1]_0\,
      \rd_mux_sel_r_reg[1]_1\ => \rd_mux_sel_r_reg[1]_1\,
      \rd_mux_sel_r_reg[1]_10\ => \rd_mux_sel_r_reg[1]_10\,
      \rd_mux_sel_r_reg[1]_11\ => \rd_mux_sel_r_reg[1]_11\,
      \rd_mux_sel_r_reg[1]_12\ => \rd_mux_sel_r_reg[1]_12\,
      \rd_mux_sel_r_reg[1]_13\ => \rd_mux_sel_r_reg[1]_13\,
      \rd_mux_sel_r_reg[1]_14\ => \rd_mux_sel_r_reg[1]_14\,
      \rd_mux_sel_r_reg[1]_15\ => \rd_mux_sel_r_reg[1]_15\,
      \rd_mux_sel_r_reg[1]_16\ => \rd_mux_sel_r_reg[1]_16\,
      \rd_mux_sel_r_reg[1]_17\ => \rd_mux_sel_r_reg[1]_17\,
      \rd_mux_sel_r_reg[1]_18\ => \rd_mux_sel_r_reg[1]_18\,
      \rd_mux_sel_r_reg[1]_19\ => \rd_mux_sel_r_reg[1]_19\,
      \rd_mux_sel_r_reg[1]_2\ => \rd_mux_sel_r_reg[1]_2\,
      \rd_mux_sel_r_reg[1]_20\ => \rd_mux_sel_r_reg[1]_20\,
      \rd_mux_sel_r_reg[1]_21\ => \rd_mux_sel_r_reg[1]_21\,
      \rd_mux_sel_r_reg[1]_22\ => \rd_mux_sel_r_reg[1]_22\,
      \rd_mux_sel_r_reg[1]_23\ => \rd_mux_sel_r_reg[1]_23\,
      \rd_mux_sel_r_reg[1]_24\ => \rd_mux_sel_r_reg[1]_24\,
      \rd_mux_sel_r_reg[1]_25\ => \rd_mux_sel_r_reg[1]_25\,
      \rd_mux_sel_r_reg[1]_26\ => \rd_mux_sel_r_reg[1]_26\,
      \rd_mux_sel_r_reg[1]_27\ => \rd_mux_sel_r_reg[1]_27\,
      \rd_mux_sel_r_reg[1]_28\ => \rd_mux_sel_r_reg[1]_28\,
      \rd_mux_sel_r_reg[1]_29\ => \rd_mux_sel_r_reg[1]_29\,
      \rd_mux_sel_r_reg[1]_3\ => \rd_mux_sel_r_reg[1]_3\,
      \rd_mux_sel_r_reg[1]_30\ => \rd_mux_sel_r_reg[1]_30\,
      \rd_mux_sel_r_reg[1]_31\ => \rd_mux_sel_r_reg[1]_31\,
      \rd_mux_sel_r_reg[1]_32\ => \rd_mux_sel_r_reg[1]_32\,
      \rd_mux_sel_r_reg[1]_33\ => \rd_mux_sel_r_reg[1]_33\,
      \rd_mux_sel_r_reg[1]_34\ => \rd_mux_sel_r_reg[1]_34\,
      \rd_mux_sel_r_reg[1]_35\ => \rd_mux_sel_r_reg[1]_35\,
      \rd_mux_sel_r_reg[1]_36\ => \rd_mux_sel_r_reg[1]_36\,
      \rd_mux_sel_r_reg[1]_37\ => \rd_mux_sel_r_reg[1]_37\,
      \rd_mux_sel_r_reg[1]_38\ => \rd_mux_sel_r_reg[1]_38\,
      \rd_mux_sel_r_reg[1]_39\ => \rd_mux_sel_r_reg[1]_39\,
      \rd_mux_sel_r_reg[1]_4\ => \rd_mux_sel_r_reg[1]_4\,
      \rd_mux_sel_r_reg[1]_40\ => \rd_mux_sel_r_reg[1]_40\,
      \rd_mux_sel_r_reg[1]_41\ => \rd_mux_sel_r_reg[1]_41\,
      \rd_mux_sel_r_reg[1]_42\ => \rd_mux_sel_r_reg[1]_42\,
      \rd_mux_sel_r_reg[1]_43\ => \rd_mux_sel_r_reg[1]_43\,
      \rd_mux_sel_r_reg[1]_44\ => \rd_mux_sel_r_reg[1]_44\,
      \rd_mux_sel_r_reg[1]_45\ => \rd_mux_sel_r_reg[1]_45\,
      \rd_mux_sel_r_reg[1]_46\ => \rd_mux_sel_r_reg[1]_46\,
      \rd_mux_sel_r_reg[1]_47\ => \rd_mux_sel_r_reg[1]_47\,
      \rd_mux_sel_r_reg[1]_48\ => \rd_mux_sel_r_reg[1]_48\,
      \rd_mux_sel_r_reg[1]_49\ => \rd_mux_sel_r_reg[1]_49\,
      \rd_mux_sel_r_reg[1]_5\ => \rd_mux_sel_r_reg[1]_5\,
      \rd_mux_sel_r_reg[1]_50\ => \rd_mux_sel_r_reg[1]_50\,
      \rd_mux_sel_r_reg[1]_51\ => \rd_mux_sel_r_reg[1]_51\,
      \rd_mux_sel_r_reg[1]_52\ => \rd_mux_sel_r_reg[1]_52\,
      \rd_mux_sel_r_reg[1]_53\ => \rd_mux_sel_r_reg[1]_53\,
      \rd_mux_sel_r_reg[1]_54\ => \rd_mux_sel_r_reg[1]_54\,
      \rd_mux_sel_r_reg[1]_55\ => \rd_mux_sel_r_reg[1]_55\,
      \rd_mux_sel_r_reg[1]_56\ => \rd_mux_sel_r_reg[1]_56\,
      \rd_mux_sel_r_reg[1]_57\ => \rd_mux_sel_r_reg[1]_57\,
      \rd_mux_sel_r_reg[1]_58\ => \rd_mux_sel_r_reg[1]_58\,
      \rd_mux_sel_r_reg[1]_59\ => \rd_mux_sel_r_reg[1]_59\,
      \rd_mux_sel_r_reg[1]_6\ => \rd_mux_sel_r_reg[1]_6\,
      \rd_mux_sel_r_reg[1]_60\ => \rd_mux_sel_r_reg[1]_60\,
      \rd_mux_sel_r_reg[1]_61\ => \rd_mux_sel_r_reg[1]_61\,
      \rd_mux_sel_r_reg[1]_62\ => \rd_mux_sel_r_reg[1]_62\,
      \rd_mux_sel_r_reg[1]_7\ => \rd_mux_sel_r_reg[1]_7\,
      \rd_mux_sel_r_reg[1]_8\ => \rd_mux_sel_r_reg[1]_8\,
      \rd_mux_sel_r_reg[1]_9\ => \rd_mux_sel_r_reg[1]_9\,
      \rd_ptr_reg[1]_0\ => \entry_cnt_reg[4]\,
      \wr_ptr[1]_i_2__2\(0) => \wr_ptr[1]_i_2__2\(0)
    );
ififo_rst_reg: unisim.vcomponents.FDSE
    generic map(
      INIT => '1'
    )
        port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => ififo_rst_reg_0,
      Q => ififo_rst,
      S => phy_if_reset
    );
\in_fifo_gen.in_fifo\: unisim.vcomponents.IN_FIFO
    generic map(
      ALMOST_EMPTY_VALUE => 1,
      ALMOST_FULL_VALUE => 1,
      ARRAY_MODE => "ARRAY_MODE_4_X_8",
      SYNCHRONOUS_MODE => "FALSE"
    )
        port map (
      ALMOSTEMPTY => \in_fifo_gen.in_fifo_n_0\,
      ALMOSTFULL => \in_fifo_gen.in_fifo_n_1\,
      D0(3 downto 0) => B"0000",
      D1(3 downto 0) => B"0000",
      D2(3 downto 0) => if_d2(3 downto 0),
      D3(3 downto 0) => if_d3(3 downto 0),
      D4(3 downto 0) => if_d4(3 downto 0),
      D5(7 downto 4) => \NLW_in_fifo_gen.in_fifo_D5_UNCONNECTED\(7 downto 4),
      D5(3 downto 0) => if_d5(3 downto 0),
      D6(7 downto 4) => \NLW_in_fifo_gen.in_fifo_D6_UNCONNECTED\(7 downto 4),
      D6(3 downto 0) => if_d6(3 downto 0),
      D7(3 downto 0) => if_d7(3 downto 0),
      D8(3 downto 0) => if_d8(3 downto 0),
      D9(3 downto 0) => if_d9(3 downto 0),
      EMPTY => \if_empty_\,
      FULL => \in_fifo_gen.in_fifo_n_3\,
      Q0(7 downto 0) => rd_data(7 downto 0),
      Q1(7 downto 0) => rd_data(15 downto 8),
      Q2(7 downto 0) => rd_data(23 downto 16),
      Q3(7 downto 0) => rd_data(31 downto 24),
      Q4(7 downto 0) => rd_data(39 downto 32),
      Q5(7 downto 0) => rd_data(47 downto 40),
      Q6(7 downto 0) => rd_data(55 downto 48),
      Q7(7 downto 0) => rd_data(63 downto 56),
      Q8(7 downto 0) => rd_data(71 downto 64),
      Q9(7 downto 0) => rd_data(79 downto 72),
      RDCLK => \entry_cnt_reg[4]\,
      RDEN => '1',
      RESET => ififo_rst,
      WRCLK => iserdes_clkdiv,
      WREN => ififo_wr_enable
    );
\of_pre_fifo_gen.u_ddr_of_pre_fifo\: entity work.\mig_mig_7series_v4_2_ddr_of_pre_fifo__parameterized1_31\
     port map (
      D0(7) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_2\,
      D0(6) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_3\,
      D0(5) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_4\,
      D0(4) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_5\,
      D0(3) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_6\,
      D0(2) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_7\,
      D0(1) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_8\,
      D0(0) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_9\,
      D1(7 downto 0) => of_d1(7 downto 0),
      Q(2 downto 0) => Q(2 downto 0),
      \entry_cnt_reg[4]_0\ => \entry_cnt_reg[4]\,
      \my_empty_reg[1]_0\ => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_0\,
      \my_empty_reg[1]_1\ => \my_empty_reg[1]\,
      \my_empty_reg[7]_0\ => out_fifo_n_3,
      ofifo_rst => ofifo_rst,
      out_fifo => out_fifo_0,
      out_fifo_0(7 downto 0) => out_fifo_1(7 downto 0),
      out_fifo_1 => out_fifo_2,
      \out_fifo_i_75__7\(71 downto 0) => \out_fifo_i_75__7\(71 downto 0),
      phy_data_wr_en => phy_data_wr_en,
      \rd_ptr_reg[3]_0\(63 downto 0) => \rd_ptr_reg[3]\(63 downto 0)
    );
ofifo_rst_reg: unisim.vcomponents.FDSE
    generic map(
      INIT => '1'
    )
        port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => ififo_rst_reg_0,
      Q => ofifo_rst,
      S => A_rst_primitives
    );
out_fifo: unisim.vcomponents.OUT_FIFO
    generic map(
      ALMOST_EMPTY_VALUE => 1,
      ALMOST_FULL_VALUE => 1,
      ARRAY_MODE => "ARRAY_MODE_8_X_4",
      OUTPUT_DISABLE => "FALSE",
      SYNCHRONOUS_MODE => "FALSE"
    )
        port map (
      ALMOSTEMPTY => out_fifo_n_0,
      ALMOSTFULL => out_fifo_n_1,
      D0(7) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_2\,
      D0(6) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_3\,
      D0(5) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_4\,
      D0(4) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_5\,
      D0(3) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_6\,
      D0(2) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_7\,
      D0(1) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_8\,
      D0(0) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_9\,
      D1(7 downto 0) => of_d1(7 downto 0),
      D2(7 downto 0) => \my_empty_reg[7]\(7 downto 0),
      D3(7 downto 0) => \my_empty_reg[7]_0\(7 downto 0),
      D4(7 downto 0) => \my_empty_reg[7]_1\(7 downto 0),
      D5(7 downto 0) => \my_empty_reg[7]_2\(7 downto 0),
      D6(7 downto 0) => \my_empty_reg[7]_3\(7 downto 0),
      D7(7 downto 0) => \my_empty_reg[7]_4\(7 downto 0),
      D8(7 downto 0) => \my_empty_reg[7]_5\(7 downto 0),
      D9(7 downto 0) => \my_empty_reg[7]_6\(7 downto 0),
      EMPTY => out_fifo_n_2,
      FULL => out_fifo_n_3,
      Q0(3 downto 0) => of_dqbus(3 downto 0),
      Q1(3 downto 0) => of_dqbus(7 downto 4),
      Q2(3 downto 0) => of_dqbus(11 downto 8),
      Q3(3 downto 0) => of_dqbus(15 downto 12),
      Q4(3 downto 0) => of_dqbus(19 downto 16),
      Q5(7 downto 4) => NLW_out_fifo_Q5_UNCONNECTED(7 downto 4),
      Q5(3 downto 0) => of_dqbus(23 downto 20),
      Q6(7 downto 4) => NLW_out_fifo_Q6_UNCONNECTED(7 downto 4),
      Q6(3 downto 0) => of_dqbus(27 downto 24),
      Q7(3 downto 0) => of_dqbus(31 downto 28),
      Q8(3 downto 0) => of_dqbus(35 downto 32),
      Q9(3 downto 0) => of_dqbus(39 downto 36),
      RDCLK => oserdes_clkdiv,
      RDEN => po_rd_enable,
      RESET => ofifo_rst,
      WRCLK => \entry_cnt_reg[4]\,
      WREN => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_0\
    );
\phaser_in_gen.phaser_in\: unisim.vcomponents.PHASER_IN_PHY
    generic map(
      BURST_MODE => "TRUE",
      CLKOUT_DIV => 2,
      DQS_AUTO_RECAL => '1',
      DQS_BIAS_MODE => "FALSE",
      DQS_FIND_PATTERN => B"000",
      FINE_DELAY => 33,
      FREQ_REF_DIV => "DIV2",
      IS_RST_INVERTED => '0',
      MEMREFCLK_PERIOD => 2.500000,
      OUTPUT_CLK_SRC => "DELAYED_REF",
      PHASEREFCLK_PERIOD => 2.500000,
      REFCLK_PERIOD => 1.250000,
      SEL_CLK_OFFSET => 6,
      SYNC_IN_DIV_RST => "TRUE",
      WR_CYCLES => "FALSE"
    )
        port map (
      BURSTPENDINGPHY => phaser_ctl_bus(1),
      COUNTERLOADEN => \pi_dqs_found_lanes_r1_reg[3]\,
      COUNTERLOADVAL(5 downto 0) => \pi_dqs_found_lanes_r1_reg[3]_3\(5 downto 0),
      COUNTERREADEN => \pi_dqs_found_lanes_r1_reg[3]_0\,
      COUNTERREADVAL(5 downto 0) => A_rst_primitives_reg_1(5 downto 0),
      DQSFOUND => in0(0),
      DQSOUTOFRANGE => \phaser_in_gen.phaser_in_n_1\,
      ENCALIBPHY(1 downto 0) => PCENABLECALIB(1 downto 0),
      FINEENABLE => \pi_dqs_found_lanes_r1_reg[3]_1\,
      FINEINC => \pi_dqs_found_lanes_r1_reg[3]_2\,
      FINEOVERFLOW => \phaser_in_gen.phaser_in_n_2\,
      FREQREFCLK => freq_refclk,
      ICLK => \^a_rst_primitives_reg\,
      ICLKDIV => iserdes_clkdiv,
      ISERDESRST => \phaser_in_gen.phaser_in_n_5\,
      MEMREFCLK => mem_refclk,
      PHASELOCKED => A_rst_primitives_reg_0,
      PHASEREFCLK => mem_dqs_in(0),
      RANKSELPHY(1 downto 0) => phaser_ctl_bus(3 downto 2),
      RCLK => \phaser_in_gen.phaser_in_n_7\,
      RST => A_rst_primitives,
      RSTDQSFIND => ififo_rst_reg_0,
      SYNCIN => sync_pulse,
      SYSCLK => \entry_cnt_reg[4]\,
      WRENABLE => ififo_wr_enable
    );
phaser_out: unisim.vcomponents.PHASER_OUT_PHY
    generic map(
      CLKOUT_DIV => 2,
      COARSE_BYPASS => "FALSE",
      COARSE_DELAY => 0,
      DATA_CTL_N => "TRUE",
      DATA_RD_CYCLES => "FALSE",
      FINE_DELAY => 60,
      IS_RST_INVERTED => '0',
      MEMREFCLK_PERIOD => 2.500000,
      OCLKDELAY_INV => "FALSE",
      OCLK_DELAY => 0,
      OUTPUT_CLK_SRC => "DELAYED_REF",
      PHASEREFCLK_PERIOD => 1.000000,
      PO => B"111",
      REFCLK_PERIOD => 1.250000,
      SYNC_IN_DIV_RST => "TRUE"
    )
        port map (
      BURSTPENDINGPHY => phaser_ctl_bus(0),
      COARSEENABLE => \po_counter_read_val_reg[8]\,
      COARSEINC => \po_counter_read_val_reg[8]\,
      COARSEOVERFLOW => phaser_out_n_0,
      COUNTERLOADEN => '0',
      COUNTERLOADVAL(8 downto 0) => B"000000000",
      COUNTERREADEN => \pi_dqs_found_lanes_r1_reg[3]_0\,
      COUNTERREADVAL(8 downto 0) => A_rst_primitives_reg_2(8 downto 0),
      CTSBUS(1 downto 0) => oserdes_dqs_ts(1 downto 0),
      DQSBUS(1 downto 0) => oserdes_dqs(1 downto 0),
      DTSBUS(1 downto 0) => oserdes_dq_ts(1 downto 0),
      ENCALIBPHY(1 downto 0) => PCENABLECALIB(1 downto 0),
      FINEENABLE => \po_counter_read_val_reg[8]_0\,
      FINEINC => \po_counter_read_val_reg[8]_1\,
      FINEOVERFLOW => phaser_out_n_1,
      FREQREFCLK => freq_refclk,
      MEMREFCLK => mem_refclk,
      OCLK => oserdes_clk,
      OCLKDELAYED => oserdes_clk_delayed,
      OCLKDIV => oserdes_clkdiv,
      OSERDESRST => po_oserdes_rst,
      PHASEREFCLK => NLW_phaser_out_PHASEREFCLK_UNCONNECTED,
      RDENABLE => po_rd_enable,
      RST => A_rst_primitives,
      SELFINEOCLKDELAY => '0',
      SYNCIN => sync_pulse,
      SYSCLK => \entry_cnt_reg[4]\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \mig_mig_7series_v4_2_ddr_byte_lane__parameterized3\ is
  port (
    SR : out STD_LOGIC_VECTOR ( 0 to 0 );
    \my_empty_reg[1]\ : out STD_LOGIC;
    of_ctl_full_v : out STD_LOGIC_VECTOR ( 0 to 0 );
    mem_out : out STD_LOGIC_VECTOR ( 11 downto 0 );
    mem_dq_out : out STD_LOGIC_VECTOR ( 5 downto 0 );
    D : out STD_LOGIC_VECTOR ( 8 downto 0 );
    OUTBURSTPENDING : in STD_LOGIC_VECTOR ( 0 to 0 );
    \po_counter_read_val_reg[8]\ : in STD_LOGIC;
    \po_counter_read_val_reg[8]_0\ : in STD_LOGIC;
    \po_counter_read_val_reg[8]_1\ : in STD_LOGIC;
    \po_counter_read_val_reg[8]_2\ : in STD_LOGIC;
    freq_refclk : in STD_LOGIC;
    mem_refclk : in STD_LOGIC;
    B_rst_primitives : in STD_LOGIC;
    sync_pulse : in STD_LOGIC;
    \my_full_reg[3]\ : in STD_LOGIC;
    PCENABLECALIB : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \my_full_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
    \my_full_reg[3]_1\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \my_full_reg[3]_2\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \my_full_reg[3]_3\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \my_full_reg[3]_4\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
    phy_cmd_wr_en : in STD_LOGIC;
    mc_we_n : in STD_LOGIC_VECTOR ( 1 downto 0 );
    out_fifo_0 : in STD_LOGIC;
    mc_ras_n : in STD_LOGIC_VECTOR ( 1 downto 0 );
    mc_cs_n : in STD_LOGIC_VECTOR ( 0 to 0 );
    mc_cas_n : in STD_LOGIC_VECTOR ( 1 downto 0 );
    C_of_full : in STD_LOGIC;
    D_of_full : in STD_LOGIC;
    \out_fifo_i_47__8\ : in STD_LOGIC_VECTOR ( 12 downto 0 );
    COUNTERREADVAL : in STD_LOGIC_VECTOR ( 8 downto 0 );
    calib_sel : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \po_counter_read_val_reg[8]_3\ : in STD_LOGIC_VECTOR ( 8 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \mig_mig_7series_v4_2_ddr_byte_lane__parameterized3\ : entity is "mig_7series_v4_2_ddr_byte_lane";
end \mig_mig_7series_v4_2_ddr_byte_lane__parameterized3\;

architecture STRUCTURE of \mig_mig_7series_v4_2_ddr_byte_lane__parameterized3\ is
  signal B_of_a_full : STD_LOGIC;
  signal B_of_full : STD_LOGIC;
  signal B_po_coarse_overflow : STD_LOGIC;
  signal B_po_counter_read_val : STD_LOGIC_VECTOR ( 8 downto 0 );
  signal B_po_fine_overflow : STD_LOGIC;
  signal \^sr\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal of_d4 : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal of_d5 : STD_LOGIC_VECTOR ( 6 downto 0 );
  signal of_d6 : STD_LOGIC_VECTOR ( 6 downto 4 );
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_1\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_12\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_15\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_18\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_19\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_2\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_20\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_21\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_22\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_23\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_24\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_25\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_26\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_27\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_28\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_29\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_3\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_30\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_31\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_32\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_33\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_34\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_35\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_36\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_37\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_4\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_5\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_6\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_9\ : STD_LOGIC;
  signal of_q0 : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal of_q1 : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal of_q2 : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal of_q3 : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal of_q4 : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal of_q5 : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal of_q6 : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal of_q7 : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal of_q8 : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal of_q9 : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal oserdes_clk : STD_LOGIC;
  signal oserdes_clk_delayed : STD_LOGIC;
  signal oserdes_clkdiv : STD_LOGIC;
  signal oserdes_dq_ts : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal oserdes_dqs : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal oserdes_dqs_ts : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal out_fifo_n_0 : STD_LOGIC;
  signal out_fifo_n_2 : STD_LOGIC;
  signal po_oserdes_rst : STD_LOGIC;
  signal po_rd_enable : STD_LOGIC;
  signal NLW_phaser_out_PHASEREFCLK_UNCONNECTED : STD_LOGIC;
  attribute BOX_TYPE : string;
  attribute BOX_TYPE of out_fifo : label is "PRIMITIVE";
  attribute BOX_TYPE of phaser_out : label is "PRIMITIVE";
begin
  SR(0) <= \^sr\(0);
ddr_byte_group_io: entity work.\mig_mig_7series_v4_2_ddr_byte_group_io__parameterized1\
     port map (
      mem_dq_out(5 downto 0) => mem_dq_out(5 downto 0),
      oserdes_clk => oserdes_clk,
      oserdes_clkdiv => oserdes_clkdiv,
      oserdes_dq(23 downto 20) => of_q6(7 downto 4),
      oserdes_dq(19 downto 16) => of_q5(7 downto 4),
      oserdes_dq(15 downto 12) => of_q7(3 downto 0),
      oserdes_dq(11 downto 8) => of_q5(3 downto 0),
      oserdes_dq(7 downto 4) => of_q4(3 downto 0),
      oserdes_dq(3 downto 0) => of_q2(3 downto 0),
      po_oserdes_rst => po_oserdes_rst
    );
\of_pre_fifo_gen.u_ddr_of_pre_fifo\: entity work.\mig_mig_7series_v4_2_ddr_of_pre_fifo__parameterized1_24\
     port map (
      B_of_full => B_of_full,
      D1(3) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_30\,
      D1(2) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_31\,
      D1(1) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_32\,
      D1(0) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_33\,
      D2(3) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_34\,
      D2(2) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_35\,
      D2(1) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_36\,
      D2(0) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_37\,
      D3(7) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_22\,
      D3(6) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_23\,
      D3(5) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_24\,
      D3(4) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_25\,
      D3(3) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_26\,
      D3(2) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_27\,
      D3(1) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_28\,
      D3(0) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_29\,
      D4(6) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_2\,
      D4(5) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_3\,
      D4(4) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_4\,
      D4(3) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_5\,
      D4(2) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_6\,
      D4(1) => of_d4(2),
      D4(0) => of_d4(0),
      D5(5) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_9\,
      D5(4) => of_d5(6),
      D5(3) => of_d5(4),
      D5(2) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_12\,
      D5(1) => of_d5(2),
      D5(0) => of_d5(0),
      D6(6) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_15\,
      D6(5) => of_d6(6),
      D6(4) => of_d6(4),
      D6(3) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_18\,
      D6(2) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_19\,
      D6(1) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_20\,
      D6(0) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_21\,
      SR(0) => \^sr\(0),
      mc_cas_n(1 downto 0) => mc_cas_n(1 downto 0),
      mc_cs_n(0) => mc_cs_n(0),
      mc_ras_n(1 downto 0) => mc_ras_n(1 downto 0),
      mc_we_n(1 downto 0) => mc_we_n(1 downto 0),
      mem_out(11 downto 0) => mem_out(11 downto 0),
      \my_empty_reg[1]_0\ => \my_empty_reg[1]\,
      \my_empty_reg[1]_1\ => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_1\,
      \my_full_reg[3]_0\ => \my_full_reg[3]\,
      out_fifo => out_fifo_0,
      \out_fifo_i_47__8\(12 downto 0) => \out_fifo_i_47__8\(12 downto 0),
      phy_cmd_wr_en => phy_cmd_wr_en
    );
ofifo_rst_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '1'
    )
        port map (
      C => \my_full_reg[3]\,
      CE => '1',
      D => B_rst_primitives,
      Q => \^sr\(0),
      R => '0'
    );
out_fifo: unisim.vcomponents.OUT_FIFO
    generic map(
      ALMOST_EMPTY_VALUE => 1,
      ALMOST_FULL_VALUE => 1,
      ARRAY_MODE => "ARRAY_MODE_4_X_4",
      OUTPUT_DISABLE => "FALSE",
      SYNCHRONOUS_MODE => "FALSE"
    )
        port map (
      ALMOSTEMPTY => out_fifo_n_0,
      ALMOSTFULL => B_of_a_full,
      D0(7) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_28\,
      D0(6) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_29\,
      D0(5) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_24\,
      D0(4) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_25\,
      D0(3) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_26\,
      D0(2) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_27\,
      D0(1) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_28\,
      D0(0) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_29\,
      D1(7) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_30\,
      D1(6) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_31\,
      D1(5) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_32\,
      D1(4) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_33\,
      D1(3) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_24\,
      D1(2) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_25\,
      D1(1) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_26\,
      D1(0) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_27\,
      D2(7) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_34\,
      D2(6) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_35\,
      D2(5) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_36\,
      D2(4) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_37\,
      D2(3 downto 0) => \my_full_reg[3]_0\(3 downto 0),
      D3(7) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_22\,
      D3(6) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_23\,
      D3(5) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_24\,
      D3(4) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_25\,
      D3(3) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_26\,
      D3(2) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_27\,
      D3(1) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_28\,
      D3(0) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_29\,
      D4(7) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_2\,
      D4(6) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_3\,
      D4(5) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_4\,
      D4(4) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_5\,
      D4(3) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_6\,
      D4(2) => of_d4(2),
      D4(1) => \my_full_reg[3]_1\(0),
      D4(0) => of_d4(0),
      D5(7) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_9\,
      D5(6) => of_d5(6),
      D5(5) => \my_full_reg[3]_2\(1),
      D5(4) => of_d5(4),
      D5(3) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_12\,
      D5(2) => of_d5(2),
      D5(1) => \my_full_reg[3]_2\(0),
      D5(0) => of_d5(0),
      D6(7) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_15\,
      D6(6) => of_d6(6),
      D6(5) => \my_full_reg[3]_3\(0),
      D6(4) => of_d6(4),
      D6(3) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_18\,
      D6(2) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_19\,
      D6(1) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_20\,
      D6(0) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_21\,
      D7(7) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_26\,
      D7(6) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_27\,
      D7(5) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_28\,
      D7(4) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_29\,
      D7(3 downto 0) => \my_full_reg[3]_4\(3 downto 0),
      D8(7) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_24\,
      D8(6) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_25\,
      D8(5) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_26\,
      D8(4) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_27\,
      D8(3) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_28\,
      D8(2) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_29\,
      D8(1) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_24\,
      D8(0) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_25\,
      D9(7) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_28\,
      D9(6) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_29\,
      D9(5) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_24\,
      D9(4) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_25\,
      D9(3) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_26\,
      D9(2) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_27\,
      D9(1) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_28\,
      D9(0) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_29\,
      EMPTY => out_fifo_n_2,
      FULL => B_of_full,
      Q0(3 downto 0) => of_q0(3 downto 0),
      Q1(3 downto 0) => of_q1(3 downto 0),
      Q2(3 downto 0) => of_q2(3 downto 0),
      Q3(3 downto 0) => of_q3(3 downto 0),
      Q4(3 downto 0) => of_q4(3 downto 0),
      Q5(7 downto 0) => of_q5(7 downto 0),
      Q6(7 downto 0) => of_q6(7 downto 0),
      Q7(3 downto 0) => of_q7(3 downto 0),
      Q8(3 downto 0) => of_q8(3 downto 0),
      Q9(3 downto 0) => of_q9(3 downto 0),
      RDCLK => oserdes_clkdiv,
      RDEN => po_rd_enable,
      RESET => \^sr\(0),
      WRCLK => \my_full_reg[3]\,
      WREN => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_1\
    );
phaser_out: unisim.vcomponents.PHASER_OUT_PHY
    generic map(
      CLKOUT_DIV => 4,
      COARSE_BYPASS => "FALSE",
      COARSE_DELAY => 0,
      DATA_CTL_N => "FALSE",
      DATA_RD_CYCLES => "FALSE",
      FINE_DELAY => 60,
      IS_RST_INVERTED => '0',
      MEMREFCLK_PERIOD => 2.500000,
      OCLKDELAY_INV => "FALSE",
      OCLK_DELAY => 0,
      OUTPUT_CLK_SRC => "DELAYED_REF",
      PHASEREFCLK_PERIOD => 1.000000,
      PO => B"111",
      REFCLK_PERIOD => 1.250000,
      SYNC_IN_DIV_RST => "TRUE"
    )
        port map (
      BURSTPENDINGPHY => OUTBURSTPENDING(0),
      COARSEENABLE => \po_counter_read_val_reg[8]\,
      COARSEINC => \po_counter_read_val_reg[8]\,
      COARSEOVERFLOW => B_po_coarse_overflow,
      COUNTERLOADEN => '0',
      COUNTERLOADVAL(8 downto 0) => B"000000000",
      COUNTERREADEN => \po_counter_read_val_reg[8]_0\,
      COUNTERREADVAL(8 downto 0) => B_po_counter_read_val(8 downto 0),
      CTSBUS(1 downto 0) => oserdes_dqs_ts(1 downto 0),
      DQSBUS(1 downto 0) => oserdes_dqs(1 downto 0),
      DTSBUS(1 downto 0) => oserdes_dq_ts(1 downto 0),
      ENCALIBPHY(1 downto 0) => PCENABLECALIB(1 downto 0),
      FINEENABLE => \po_counter_read_val_reg[8]_1\,
      FINEINC => \po_counter_read_val_reg[8]_2\,
      FINEOVERFLOW => B_po_fine_overflow,
      FREQREFCLK => freq_refclk,
      MEMREFCLK => mem_refclk,
      OCLK => oserdes_clk,
      OCLKDELAYED => oserdes_clk_delayed,
      OCLKDIV => oserdes_clkdiv,
      OSERDESRST => po_oserdes_rst,
      PHASEREFCLK => NLW_phaser_out_PHASEREFCLK_UNCONNECTED,
      RDENABLE => po_rd_enable,
      RST => B_rst_primitives,
      SELFINEOCLKDELAY => '0',
      SYNCIN => sync_pulse,
      SYSCLK => \my_full_reg[3]\
    );
phy_mc_cmd_full_r_i_1: unisim.vcomponents.LUT3
    generic map(
      INIT => X"FE"
    )
        port map (
      I0 => B_of_full,
      I1 => C_of_full,
      I2 => D_of_full,
      O => of_ctl_full_v(0)
    );
\po_counter_read_val[0]_i_1__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"CAF0CA00"
    )
        port map (
      I0 => B_po_counter_read_val(0),
      I1 => COUNTERREADVAL(0),
      I2 => calib_sel(1),
      I3 => calib_sel(0),
      I4 => \po_counter_read_val_reg[8]_3\(0),
      O => D(0)
    );
\po_counter_read_val[1]_i_1__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"CAF0CA00"
    )
        port map (
      I0 => B_po_counter_read_val(1),
      I1 => COUNTERREADVAL(1),
      I2 => calib_sel(1),
      I3 => calib_sel(0),
      I4 => \po_counter_read_val_reg[8]_3\(1),
      O => D(1)
    );
\po_counter_read_val[2]_i_1__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"CAF0CA00"
    )
        port map (
      I0 => B_po_counter_read_val(2),
      I1 => COUNTERREADVAL(2),
      I2 => calib_sel(1),
      I3 => calib_sel(0),
      I4 => \po_counter_read_val_reg[8]_3\(2),
      O => D(2)
    );
\po_counter_read_val[3]_i_1__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"CAF0CA00"
    )
        port map (
      I0 => B_po_counter_read_val(3),
      I1 => COUNTERREADVAL(3),
      I2 => calib_sel(1),
      I3 => calib_sel(0),
      I4 => \po_counter_read_val_reg[8]_3\(3),
      O => D(3)
    );
\po_counter_read_val[4]_i_1__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"CAF0CA00"
    )
        port map (
      I0 => B_po_counter_read_val(4),
      I1 => COUNTERREADVAL(4),
      I2 => calib_sel(1),
      I3 => calib_sel(0),
      I4 => \po_counter_read_val_reg[8]_3\(4),
      O => D(4)
    );
\po_counter_read_val[5]_i_1__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"CAF0CA00"
    )
        port map (
      I0 => B_po_counter_read_val(5),
      I1 => COUNTERREADVAL(5),
      I2 => calib_sel(1),
      I3 => calib_sel(0),
      I4 => \po_counter_read_val_reg[8]_3\(5),
      O => D(5)
    );
\po_counter_read_val[6]_i_1__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"CAF0CA00"
    )
        port map (
      I0 => B_po_counter_read_val(6),
      I1 => COUNTERREADVAL(6),
      I2 => calib_sel(1),
      I3 => calib_sel(0),
      I4 => \po_counter_read_val_reg[8]_3\(6),
      O => D(6)
    );
\po_counter_read_val[7]_i_1__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"CAF0CA00"
    )
        port map (
      I0 => B_po_counter_read_val(7),
      I1 => COUNTERREADVAL(7),
      I2 => calib_sel(1),
      I3 => calib_sel(0),
      I4 => \po_counter_read_val_reg[8]_3\(7),
      O => D(7)
    );
\po_counter_read_val[8]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"CAF0CA00"
    )
        port map (
      I0 => B_po_counter_read_val(8),
      I1 => COUNTERREADVAL(8),
      I2 => calib_sel(1),
      I3 => calib_sel(0),
      I4 => \po_counter_read_val_reg[8]_3\(8),
      O => D(8)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \mig_mig_7series_v4_2_ddr_byte_lane__parameterized4\ is
  port (
    ddr_ck_out : out STD_LOGIC_VECTOR ( 1 downto 0 );
    mem_dq_out : out STD_LOGIC_VECTOR ( 5 downto 0 );
    B_rst_primitives_reg : out STD_LOGIC_VECTOR ( 8 downto 0 );
    C_of_full : out STD_LOGIC;
    \my_empty_reg[1]\ : out STD_LOGIC;
    \rd_ptr_reg[3]\ : out STD_LOGIC_VECTOR ( 23 downto 0 );
    SR : in STD_LOGIC_VECTOR ( 0 to 0 );
    \wr_ptr_timing_reg[3]\ : in STD_LOGIC;
    OUTBURSTPENDING : in STD_LOGIC_VECTOR ( 0 to 0 );
    C_po_coarse_enable26_out : in STD_LOGIC;
    C_po_counter_read_en38_out : in STD_LOGIC;
    C_po_fine_enable23_out : in STD_LOGIC;
    C_po_fine_inc29_out : in STD_LOGIC;
    freq_refclk : in STD_LOGIC;
    mem_refclk : in STD_LOGIC;
    B_rst_primitives : in STD_LOGIC;
    sync_pulse : in STD_LOGIC;
    PCENABLECALIB : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \my_empty_reg[7]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
    \my_empty_reg[7]_0\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \my_empty_reg[7]_1\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
    \my_empty_reg[7]_2\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
    D9 : in STD_LOGIC_VECTOR ( 3 downto 0 );
    phy_cmd_wr_en : in STD_LOGIC;
    phy_dout : in STD_LOGIC_VECTOR ( 23 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \mig_mig_7series_v4_2_ddr_byte_lane__parameterized4\ : entity is "mig_7series_v4_2_ddr_byte_lane";
end \mig_mig_7series_v4_2_ddr_byte_lane__parameterized4\;

architecture STRUCTURE of \mig_mig_7series_v4_2_ddr_byte_lane__parameterized4\ is
  signal \^c_of_full\ : STD_LOGIC;
  signal ddr_ck_out_q : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_0\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_10\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_11\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_12\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_13\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_14\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_15\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_16\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_17\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_18\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_19\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_2\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_20\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_21\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_22\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_23\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_24\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_25\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_26\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_27\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_28\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_29\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_3\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_30\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_31\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_4\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_5\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_6\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_7\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_8\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_9\ : STD_LOGIC;
  signal of_q0 : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal of_q1 : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal of_q2 : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal of_q3 : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal of_q4 : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal of_q5 : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal of_q6 : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal of_q7 : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal of_q8 : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal of_q9 : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal oserdes_clk : STD_LOGIC;
  signal oserdes_clk_delayed : STD_LOGIC;
  signal oserdes_clkdiv : STD_LOGIC;
  signal oserdes_dq_ts : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal oserdes_dqs : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal oserdes_dqs_ts : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal out_fifo_n_0 : STD_LOGIC;
  signal out_fifo_n_1 : STD_LOGIC;
  signal out_fifo_n_2 : STD_LOGIC;
  signal phaser_out_n_0 : STD_LOGIC;
  signal phaser_out_n_1 : STD_LOGIC;
  signal po_oserdes_rst : STD_LOGIC;
  signal po_rd_enable : STD_LOGIC;
  signal \NLW_ddr_ck_gen_loop[0].ddr_ck_gen.ddr_ck_S_UNCONNECTED\ : STD_LOGIC;
  signal NLW_phaser_out_PHASEREFCLK_UNCONNECTED : STD_LOGIC;
  attribute BOX_TYPE : string;
  attribute BOX_TYPE of \ddr_ck_gen_loop[0].ddr_ck_gen.ddr_ck\ : label is "PRIMITIVE";
  attribute \__SRVAL\ : string;
  attribute \__SRVAL\ of \ddr_ck_gen_loop[0].ddr_ck_gen.ddr_ck\ : label is "FALSE";
  attribute BOX_TYPE of \ddr_ck_gen_loop[0].ddr_ck_gen.ddr_ck_obuf\ : label is "PRIMITIVE";
  attribute CAPACITANCE : string;
  attribute CAPACITANCE of \ddr_ck_gen_loop[0].ddr_ck_gen.ddr_ck_obuf\ : label is "DONT_CARE";
  attribute XILINX_LEGACY_PRIM : string;
  attribute XILINX_LEGACY_PRIM of \ddr_ck_gen_loop[0].ddr_ck_gen.ddr_ck_obuf\ : label is "OBUFDS";
  attribute BOX_TYPE of out_fifo : label is "PRIMITIVE";
  attribute BOX_TYPE of phaser_out : label is "PRIMITIVE";
begin
  C_of_full <= \^c_of_full\;
ddr_byte_group_io: entity work.\mig_mig_7series_v4_2_ddr_byte_group_io__parameterized2\
     port map (
      mem_dq_out(5 downto 0) => mem_dq_out(5 downto 0),
      oserdes_clk => oserdes_clk,
      oserdes_clkdiv => oserdes_clkdiv,
      oserdes_dq(23 downto 20) => of_q6(7 downto 4),
      oserdes_dq(19 downto 16) => of_q5(7 downto 4),
      oserdes_dq(15 downto 12) => of_q9(3 downto 0),
      oserdes_dq(11 downto 8) => of_q8(3 downto 0),
      oserdes_dq(7 downto 4) => of_q5(3 downto 0),
      oserdes_dq(3 downto 0) => of_q4(3 downto 0),
      po_oserdes_rst => po_oserdes_rst
    );
\ddr_ck_gen_loop[0].ddr_ck_gen.ddr_ck\: unisim.vcomponents.ODDR
    generic map(
      DDR_CLK_EDGE => "SAME_EDGE",
      INIT => '0',
      IS_C_INVERTED => '0',
      IS_D1_INVERTED => '0',
      IS_D2_INVERTED => '0',
      SRTYPE => "SYNC"
    )
        port map (
      C => oserdes_clk,
      CE => '1',
      D1 => '0',
      D2 => '1',
      Q => ddr_ck_out_q(0),
      R => '0',
      S => \NLW_ddr_ck_gen_loop[0].ddr_ck_gen.ddr_ck_S_UNCONNECTED\
    );
\ddr_ck_gen_loop[0].ddr_ck_gen.ddr_ck_obuf\: unisim.vcomponents.OBUFDS
    generic map(
      IOSTANDARD => "DEFAULT"
    )
        port map (
      I => ddr_ck_out_q(0),
      O => ddr_ck_out(0),
      OB => ddr_ck_out(1)
    );
\of_pre_fifo_gen.u_ddr_of_pre_fifo\: entity work.\mig_mig_7series_v4_2_ddr_of_pre_fifo__parameterized1_23\
     port map (
      D0(5) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_2\,
      D0(4) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_3\,
      D0(3) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_4\,
      D0(2) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_5\,
      D0(1) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_6\,
      D0(0) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_7\,
      D3(1) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_8\,
      D3(0) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_9\,
      D4(3) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_10\,
      D4(2) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_11\,
      D4(1) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_12\,
      D4(0) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_13\,
      D6(3) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_14\,
      D6(2) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_15\,
      D6(1) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_16\,
      D6(0) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_17\,
      D7(7) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_18\,
      D7(6) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_19\,
      D7(5) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_20\,
      D7(4) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_21\,
      D7(3) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_22\,
      D7(2) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_23\,
      D7(1) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_24\,
      D7(0) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_25\,
      D8(3) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_26\,
      D8(2) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_27\,
      D8(1) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_28\,
      D8(0) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_29\,
      D9(1) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_30\,
      D9(0) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_31\,
      SR(0) => SR(0),
      \my_empty_reg[1]_0\ => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_0\,
      \my_empty_reg[1]_1\ => \my_empty_reg[1]\,
      \my_empty_reg[7]_0\ => \^c_of_full\,
      phy_cmd_wr_en => phy_cmd_wr_en,
      phy_dout(23 downto 0) => phy_dout(23 downto 0),
      \rd_ptr_reg[3]_0\(23 downto 0) => \rd_ptr_reg[3]\(23 downto 0),
      \wr_ptr_timing_reg[3]_0\ => \wr_ptr_timing_reg[3]\
    );
out_fifo: unisim.vcomponents.OUT_FIFO
    generic map(
      ALMOST_EMPTY_VALUE => 1,
      ALMOST_FULL_VALUE => 1,
      ARRAY_MODE => "ARRAY_MODE_4_X_4",
      OUTPUT_DISABLE => "FALSE",
      SYNCHRONOUS_MODE => "FALSE"
    )
        port map (
      ALMOSTEMPTY => out_fifo_n_0,
      ALMOSTFULL => out_fifo_n_1,
      D0(7) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_2\,
      D0(6) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_3\,
      D0(5) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_4\,
      D0(4) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_5\,
      D0(3) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_6\,
      D0(2) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_7\,
      D0(1) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_2\,
      D0(0) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_3\,
      D1(7) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_6\,
      D1(6) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_7\,
      D1(5) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_2\,
      D1(4) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_3\,
      D1(3) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_4\,
      D1(2) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_5\,
      D1(1) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_6\,
      D1(0) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_7\,
      D2(7) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_4\,
      D2(6) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_5\,
      D2(5) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_6\,
      D2(4) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_7\,
      D2(3) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_2\,
      D2(2) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_3\,
      D2(1) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_4\,
      D2(0) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_5\,
      D3(7) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_8\,
      D3(6) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_9\,
      D3(5) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_4\,
      D3(4) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_5\,
      D3(3) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_6\,
      D3(2) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_7\,
      D3(1) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_2\,
      D3(0) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_3\,
      D4(7) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_10\,
      D4(6) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_11\,
      D4(5) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_12\,
      D4(4) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_13\,
      D4(3 downto 0) => \my_empty_reg[7]\(3 downto 0),
      D5(7 downto 0) => \my_empty_reg[7]_0\(7 downto 0),
      D6(7 downto 4) => \my_empty_reg[7]_1\(3 downto 0),
      D6(3) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_14\,
      D6(2) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_15\,
      D6(1) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_16\,
      D6(0) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_17\,
      D7(7) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_18\,
      D7(6) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_19\,
      D7(5) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_20\,
      D7(4) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_21\,
      D7(3) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_22\,
      D7(2) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_23\,
      D7(1) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_24\,
      D7(0) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_25\,
      D8(7) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_26\,
      D8(6) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_27\,
      D8(5) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_28\,
      D8(4) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_29\,
      D8(3 downto 0) => \my_empty_reg[7]_2\(3 downto 0),
      D9(7) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_2\,
      D9(6) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_3\,
      D9(5) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_30\,
      D9(4) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_31\,
      D9(3 downto 0) => D9(3 downto 0),
      EMPTY => out_fifo_n_2,
      FULL => \^c_of_full\,
      Q0(3 downto 0) => of_q0(3 downto 0),
      Q1(3 downto 0) => of_q1(3 downto 0),
      Q2(3 downto 0) => of_q2(3 downto 0),
      Q3(3 downto 0) => of_q3(3 downto 0),
      Q4(3 downto 0) => of_q4(3 downto 0),
      Q5(7 downto 0) => of_q5(7 downto 0),
      Q6(7 downto 0) => of_q6(7 downto 0),
      Q7(3 downto 0) => of_q7(3 downto 0),
      Q8(3 downto 0) => of_q8(3 downto 0),
      Q9(3 downto 0) => of_q9(3 downto 0),
      RDCLK => oserdes_clkdiv,
      RDEN => po_rd_enable,
      RESET => SR(0),
      WRCLK => \wr_ptr_timing_reg[3]\,
      WREN => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_0\
    );
phaser_out: unisim.vcomponents.PHASER_OUT_PHY
    generic map(
      CLKOUT_DIV => 4,
      COARSE_BYPASS => "FALSE",
      COARSE_DELAY => 0,
      DATA_CTL_N => "FALSE",
      DATA_RD_CYCLES => "FALSE",
      FINE_DELAY => 60,
      IS_RST_INVERTED => '0',
      MEMREFCLK_PERIOD => 2.500000,
      OCLKDELAY_INV => "FALSE",
      OCLK_DELAY => 0,
      OUTPUT_CLK_SRC => "DELAYED_REF",
      PHASEREFCLK_PERIOD => 1.000000,
      PO => B"111",
      REFCLK_PERIOD => 1.250000,
      SYNC_IN_DIV_RST => "TRUE"
    )
        port map (
      BURSTPENDINGPHY => OUTBURSTPENDING(0),
      COARSEENABLE => C_po_coarse_enable26_out,
      COARSEINC => C_po_coarse_enable26_out,
      COARSEOVERFLOW => phaser_out_n_0,
      COUNTERLOADEN => '0',
      COUNTERLOADVAL(8 downto 0) => B"000000000",
      COUNTERREADEN => C_po_counter_read_en38_out,
      COUNTERREADVAL(8 downto 0) => B_rst_primitives_reg(8 downto 0),
      CTSBUS(1 downto 0) => oserdes_dqs_ts(1 downto 0),
      DQSBUS(1 downto 0) => oserdes_dqs(1 downto 0),
      DTSBUS(1 downto 0) => oserdes_dq_ts(1 downto 0),
      ENCALIBPHY(1 downto 0) => PCENABLECALIB(1 downto 0),
      FINEENABLE => C_po_fine_enable23_out,
      FINEINC => C_po_fine_inc29_out,
      FINEOVERFLOW => phaser_out_n_1,
      FREQREFCLK => freq_refclk,
      MEMREFCLK => mem_refclk,
      OCLK => oserdes_clk,
      OCLKDELAYED => oserdes_clk_delayed,
      OCLKDIV => oserdes_clkdiv,
      OSERDESRST => po_oserdes_rst,
      PHASEREFCLK => NLW_phaser_out_PHASEREFCLK_UNCONNECTED,
      RDENABLE => po_rd_enable,
      RST => B_rst_primitives,
      SELFINEOCLKDELAY => '0',
      SYNCIN => sync_pulse,
      SYSCLK => \wr_ptr_timing_reg[3]\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \mig_mig_7series_v4_2_ddr_byte_lane__parameterized5\ is
  port (
    COUNTERREADVAL : out STD_LOGIC_VECTOR ( 8 downto 0 );
    D_of_full : out STD_LOGIC;
    \my_empty_reg[1]\ : out STD_LOGIC;
    \rd_ptr_reg[3]\ : out STD_LOGIC_VECTOR ( 35 downto 0 );
    mem_dq_out : out STD_LOGIC_VECTOR ( 10 downto 0 );
    OUTBURSTPENDING : in STD_LOGIC_VECTOR ( 0 to 0 );
    \po_counter_read_val_reg[8]\ : in STD_LOGIC;
    \po_counter_read_val_reg[8]_0\ : in STD_LOGIC;
    \po_counter_read_val_reg[8]_1\ : in STD_LOGIC;
    \po_counter_read_val_reg[8]_2\ : in STD_LOGIC;
    freq_refclk : in STD_LOGIC;
    mem_refclk : in STD_LOGIC;
    B_rst_primitives : in STD_LOGIC;
    sync_pulse : in STD_LOGIC;
    \wr_ptr_timing_reg[3]\ : in STD_LOGIC;
    PCENABLECALIB : in STD_LOGIC_VECTOR ( 1 downto 0 );
    SR : in STD_LOGIC_VECTOR ( 0 to 0 );
    D1 : in STD_LOGIC_VECTOR ( 3 downto 0 );
    D3 : in STD_LOGIC_VECTOR ( 3 downto 0 );
    D4 : in STD_LOGIC_VECTOR ( 3 downto 0 );
    D5 : in STD_LOGIC_VECTOR ( 3 downto 0 );
    D6 : in STD_LOGIC_VECTOR ( 7 downto 0 );
    D7 : in STD_LOGIC_VECTOR ( 3 downto 0 );
    D8 : in STD_LOGIC_VECTOR ( 3 downto 0 );
    \rd_ptr_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
    phy_cmd_wr_en : in STD_LOGIC;
    out_fifo_0 : in STD_LOGIC;
    mc_cas_n : in STD_LOGIC_VECTOR ( 0 to 0 );
    mc_address : in STD_LOGIC_VECTOR ( 3 downto 0 );
    out_fifo_1 : in STD_LOGIC;
    d_in : in STD_LOGIC_VECTOR ( 41 downto 0 );
    out_fifo_2 : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \mig_mig_7series_v4_2_ddr_byte_lane__parameterized5\ : entity is "mig_7series_v4_2_ddr_byte_lane";
end \mig_mig_7series_v4_2_ddr_byte_lane__parameterized5\;

architecture STRUCTURE of \mig_mig_7series_v4_2_ddr_byte_lane__parameterized5\ is
  signal D_of_a_full : STD_LOGIC;
  signal \^d_of_full\ : STD_LOGIC;
  signal D_po_coarse_overflow : STD_LOGIC;
  signal D_po_fine_overflow : STD_LOGIC;
  signal of_d2 : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal of_d5 : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_1\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_10\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_11\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_12\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_13\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_14\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_15\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_16\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_17\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_2\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_22\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_23\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_24\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_25\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_26\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_27\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_28\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_29\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_3\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_30\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_31\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_32\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_33\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_34\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_35\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_36\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_37\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_38\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_39\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_4\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_5\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_6\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_7\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_8\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_9\ : STD_LOGIC;
  signal of_q0 : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal of_q1 : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal of_q2 : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal of_q3 : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal of_q4 : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal of_q5 : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal of_q6 : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal of_q7 : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal of_q8 : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal of_q9 : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal oserdes_clk : STD_LOGIC;
  signal oserdes_clk_delayed : STD_LOGIC;
  signal oserdes_clkdiv : STD_LOGIC;
  signal oserdes_dq_ts : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal oserdes_dqs : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal oserdes_dqs_ts : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal out_fifo_n_0 : STD_LOGIC;
  signal out_fifo_n_2 : STD_LOGIC;
  signal po_oserdes_rst : STD_LOGIC;
  signal po_rd_enable : STD_LOGIC;
  signal NLW_phaser_out_PHASEREFCLK_UNCONNECTED : STD_LOGIC;
  attribute BOX_TYPE : string;
  attribute BOX_TYPE of out_fifo : label is "PRIMITIVE";
  attribute BOX_TYPE of phaser_out : label is "PRIMITIVE";
begin
  D_of_full <= \^d_of_full\;
ddr_byte_group_io: entity work.\mig_mig_7series_v4_2_ddr_byte_group_io__parameterized3\
     port map (
      mem_dq_out(10 downto 0) => mem_dq_out(10 downto 0),
      oserdes_clk => oserdes_clk,
      oserdes_clkdiv => oserdes_clkdiv,
      oserdes_dq(43 downto 40) => of_q6(7 downto 4),
      oserdes_dq(39 downto 36) => of_q5(7 downto 4),
      oserdes_dq(35 downto 32) => of_q9(3 downto 0),
      oserdes_dq(31 downto 28) => of_q8(3 downto 0),
      oserdes_dq(27 downto 24) => of_q7(3 downto 0),
      oserdes_dq(23 downto 20) => of_q6(3 downto 0),
      oserdes_dq(19 downto 16) => of_q5(3 downto 0),
      oserdes_dq(15 downto 12) => of_q4(3 downto 0),
      oserdes_dq(11 downto 8) => of_q3(3 downto 0),
      oserdes_dq(7 downto 4) => of_q2(3 downto 0),
      oserdes_dq(3 downto 0) => of_q1(3 downto 0),
      po_oserdes_rst => po_oserdes_rst
    );
\of_pre_fifo_gen.u_ddr_of_pre_fifo\: entity work.\mig_mig_7series_v4_2_ddr_of_pre_fifo__parameterized1_22\
     port map (
      D0(7) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_2\,
      D0(6) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_3\,
      D0(5) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_4\,
      D0(4) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_5\,
      D0(3) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_6\,
      D0(2) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_7\,
      D0(1) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_8\,
      D0(0) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_9\,
      D1(3) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_10\,
      D1(2) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_11\,
      D1(1) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_12\,
      D1(0) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_13\,
      D2(7) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_14\,
      D2(6) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_15\,
      D2(5) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_16\,
      D2(4) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_17\,
      D2(3 downto 0) => of_d2(3 downto 0),
      D3(3) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_22\,
      D3(2) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_23\,
      D3(1) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_24\,
      D3(0) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_25\,
      D4(3) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_26\,
      D4(2) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_27\,
      D4(1) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_28\,
      D4(0) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_29\,
      D5(3 downto 0) => of_d5(3 downto 0),
      D7(3) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_30\,
      D7(2) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_31\,
      D7(1) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_32\,
      D7(0) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_33\,
      D8(3) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_34\,
      D8(2) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_35\,
      D8(1) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_36\,
      D8(0) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_37\,
      D9(1) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_38\,
      D9(0) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_39\,
      SR(0) => SR(0),
      d_in(41 downto 0) => d_in(41 downto 0),
      mc_address(3 downto 0) => mc_address(3 downto 0),
      mc_cas_n(0) => mc_cas_n(0),
      \my_empty_reg[1]_0\ => \my_empty_reg[1]\,
      \my_empty_reg[1]_1\ => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_1\,
      out_fifo => out_fifo_0,
      out_fifo_0 => out_fifo_1,
      out_fifo_1 => out_fifo_2,
      phy_cmd_wr_en => phy_cmd_wr_en,
      \rd_ptr_reg[3]_0\(35 downto 0) => \rd_ptr_reg[3]\(35 downto 0),
      \rd_ptr_reg[3]_1\ => \^d_of_full\,
      \wr_ptr_timing_reg[3]_0\ => \wr_ptr_timing_reg[3]\
    );
out_fifo: unisim.vcomponents.OUT_FIFO
    generic map(
      ALMOST_EMPTY_VALUE => 1,
      ALMOST_FULL_VALUE => 1,
      ARRAY_MODE => "ARRAY_MODE_4_X_4",
      OUTPUT_DISABLE => "FALSE",
      SYNCHRONOUS_MODE => "FALSE"
    )
        port map (
      ALMOSTEMPTY => out_fifo_n_0,
      ALMOSTFULL => D_of_a_full,
      D0(7) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_2\,
      D0(6) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_3\,
      D0(5) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_4\,
      D0(4) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_5\,
      D0(3) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_6\,
      D0(2) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_7\,
      D0(1) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_8\,
      D0(0) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_9\,
      D1(7) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_10\,
      D1(6) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_11\,
      D1(5) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_12\,
      D1(4) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_13\,
      D1(3 downto 0) => D1(3 downto 0),
      D2(7) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_14\,
      D2(6) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_15\,
      D2(5) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_16\,
      D2(4) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_17\,
      D2(3 downto 0) => of_d2(3 downto 0),
      D3(7) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_22\,
      D3(6) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_23\,
      D3(5) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_24\,
      D3(4) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_25\,
      D3(3 downto 0) => D3(3 downto 0),
      D4(7) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_26\,
      D4(6) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_27\,
      D4(5) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_28\,
      D4(4) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_29\,
      D4(3 downto 0) => D4(3 downto 0),
      D5(7 downto 4) => D5(3 downto 0),
      D5(3 downto 0) => of_d5(3 downto 0),
      D6(7 downto 0) => D6(7 downto 0),
      D7(7) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_30\,
      D7(6) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_31\,
      D7(5) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_32\,
      D7(4) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_33\,
      D7(3 downto 0) => D7(3 downto 0),
      D8(7) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_34\,
      D8(6) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_35\,
      D8(5) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_36\,
      D8(4) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_37\,
      D8(3 downto 0) => D8(3 downto 0),
      D9(7) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_8\,
      D9(6) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_9\,
      D9(5) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_38\,
      D9(4) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_39\,
      D9(3 downto 0) => \rd_ptr_reg[3]_0\(3 downto 0),
      EMPTY => out_fifo_n_2,
      FULL => \^d_of_full\,
      Q0(3 downto 0) => of_q0(3 downto 0),
      Q1(3 downto 0) => of_q1(3 downto 0),
      Q2(3 downto 0) => of_q2(3 downto 0),
      Q3(3 downto 0) => of_q3(3 downto 0),
      Q4(3 downto 0) => of_q4(3 downto 0),
      Q5(7 downto 0) => of_q5(7 downto 0),
      Q6(7 downto 0) => of_q6(7 downto 0),
      Q7(3 downto 0) => of_q7(3 downto 0),
      Q8(3 downto 0) => of_q8(3 downto 0),
      Q9(3 downto 0) => of_q9(3 downto 0),
      RDCLK => oserdes_clkdiv,
      RDEN => po_rd_enable,
      RESET => SR(0),
      WRCLK => \wr_ptr_timing_reg[3]\,
      WREN => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_1\
    );
phaser_out: unisim.vcomponents.PHASER_OUT_PHY
    generic map(
      CLKOUT_DIV => 4,
      COARSE_BYPASS => "FALSE",
      COARSE_DELAY => 0,
      DATA_CTL_N => "FALSE",
      DATA_RD_CYCLES => "FALSE",
      FINE_DELAY => 60,
      IS_RST_INVERTED => '0',
      MEMREFCLK_PERIOD => 2.500000,
      OCLKDELAY_INV => "FALSE",
      OCLK_DELAY => 0,
      OUTPUT_CLK_SRC => "DELAYED_REF",
      PHASEREFCLK_PERIOD => 1.000000,
      PO => B"111",
      REFCLK_PERIOD => 1.250000,
      SYNC_IN_DIV_RST => "TRUE"
    )
        port map (
      BURSTPENDINGPHY => OUTBURSTPENDING(0),
      COARSEENABLE => \po_counter_read_val_reg[8]\,
      COARSEINC => \po_counter_read_val_reg[8]\,
      COARSEOVERFLOW => D_po_coarse_overflow,
      COUNTERLOADEN => '0',
      COUNTERLOADVAL(8 downto 0) => B"000000000",
      COUNTERREADEN => \po_counter_read_val_reg[8]_0\,
      COUNTERREADVAL(8 downto 0) => COUNTERREADVAL(8 downto 0),
      CTSBUS(1 downto 0) => oserdes_dqs_ts(1 downto 0),
      DQSBUS(1 downto 0) => oserdes_dqs(1 downto 0),
      DTSBUS(1 downto 0) => oserdes_dq_ts(1 downto 0),
      ENCALIBPHY(1 downto 0) => PCENABLECALIB(1 downto 0),
      FINEENABLE => \po_counter_read_val_reg[8]_1\,
      FINEINC => \po_counter_read_val_reg[8]_2\,
      FINEOVERFLOW => D_po_fine_overflow,
      FREQREFCLK => freq_refclk,
      MEMREFCLK => mem_refclk,
      OCLK => oserdes_clk,
      OCLKDELAYED => oserdes_clk_delayed,
      OCLKDIV => oserdes_clkdiv,
      OSERDESRST => po_oserdes_rst,
      PHASEREFCLK => NLW_phaser_out_PHASEREFCLK_UNCONNECTED,
      RDENABLE => po_rd_enable,
      RST => B_rst_primitives,
      SELFINEOCLKDELAY => '0',
      SYNCIN => sync_pulse,
      SYSCLK => \wr_ptr_timing_reg[3]\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mig_mig_7series_v4_2_ddr_calib_top is
  port (
    po_cnt_dec_reg : out STD_LOGIC;
    po_cnt_dec_2 : out STD_LOGIC;
    fine_adjust_reg : out STD_LOGIC;
    new_cnt_cpt_r_reg : out STD_LOGIC;
    rdlvl_stg1_start_reg : out STD_LOGIC;
    samp_edge_cnt0_en_r : out STD_LOGIC;
    pi_counter_load_en : out STD_LOGIC;
    pi_cnt_dec_reg : out STD_LOGIC;
    E : out STD_LOGIC_VECTOR ( 0 to 0 );
    prbs_rdlvl_done_pulse_reg : out STD_LOGIC;
    phy_write_calib : out STD_LOGIC;
    phy_read_calib : out STD_LOGIC;
    phy_if_reset : out STD_LOGIC;
    idelay_inc : out STD_LOGIC;
    d_in : out STD_LOGIC_VECTOR ( 37 downto 0 );
    init_calib_complete_reg_rep_0 : out STD_LOGIC;
    \init_calib_complete_reg_rep__0_0\ : out STD_LOGIC;
    \init_calib_complete_reg_rep__11_0\ : out STD_LOGIC;
    \init_calib_complete_reg_rep__12_0\ : out STD_LOGIC;
    \init_calib_complete_reg_rep__24_0\ : out STD_LOGIC;
    \init_calib_complete_reg_rep__25_0\ : out STD_LOGIC;
    \init_calib_complete_reg_rep__26_0\ : out STD_LOGIC;
    pi_fine_enable : out STD_LOGIC;
    pi_fine_inc : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
    \rd_mux_sel_r_reg[2]\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[1]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    phy_dout : out STD_LOGIC_VECTOR ( 23 downto 0 );
    init_complete_r1_timing_reg : out STD_LOGIC;
    \write_buffer.wr_buf_out_data_reg[455]\ : out STD_LOGIC_VECTOR ( 71 downto 0 );
    \write_buffer.wr_buf_out_data_reg[463]\ : out STD_LOGIC_VECTOR ( 71 downto 0 );
    \write_buffer.wr_buf_out_data_reg[471]\ : out STD_LOGIC_VECTOR ( 71 downto 0 );
    \write_buffer.wr_buf_out_data_reg[479]\ : out STD_LOGIC_VECTOR ( 71 downto 0 );
    \write_buffer.wr_buf_out_data_reg[487]\ : out STD_LOGIC_VECTOR ( 71 downto 0 );
    \write_buffer.wr_buf_out_data_reg[495]\ : out STD_LOGIC_VECTOR ( 71 downto 0 );
    \write_buffer.wr_buf_out_data_reg[503]\ : out STD_LOGIC_VECTOR ( 71 downto 0 );
    \write_buffer.wr_buf_out_data_reg[511]\ : out STD_LOGIC_VECTOR ( 71 downto 0 );
    LD0 : out STD_LOGIC;
    calib_sel : out STD_LOGIC_VECTOR ( 3 downto 0 );
    LD0_0 : out STD_LOGIC;
    LD0_1 : out STD_LOGIC;
    LD0_2 : out STD_LOGIC;
    LD0_3 : out STD_LOGIC;
    LD0_4 : out STD_LOGIC;
    LD0_5 : out STD_LOGIC;
    LD0_6 : out STD_LOGIC;
    \calib_sel_reg[1]_0\ : out STD_LOGIC;
    \calib_sel_reg[1]_1\ : out STD_LOGIC;
    \calib_sel_reg[1]_2\ : out STD_LOGIC;
    \calib_sel_reg[1]_3\ : out STD_LOGIC;
    \calib_sel_reg[1]_4\ : out STD_LOGIC;
    \calib_sel_reg[1]_5\ : out STD_LOGIC;
    \calib_sel_reg[1]_6\ : out STD_LOGIC;
    \calib_sel_reg[1]_7\ : out STD_LOGIC;
    \calib_sel_reg[1]_8\ : out STD_LOGIC;
    dqs_wl_po_stg2_c_incdec_reg : out STD_LOGIC;
    \calib_sel_reg[1]_9\ : out STD_LOGIC;
    \calib_sel_reg[1]_10\ : out STD_LOGIC;
    \calib_sel_reg[1]_11\ : out STD_LOGIC;
    \calib_sel_reg[0]_0\ : out STD_LOGIC;
    \calib_sel_reg[1]_12\ : out STD_LOGIC;
    \calib_sel_reg[1]_13\ : out STD_LOGIC;
    \calib_sel_reg[1]_14\ : out STD_LOGIC;
    \calib_sel_reg[1]_15\ : out STD_LOGIC;
    \calib_sel_reg[1]_16\ : out STD_LOGIC;
    \calib_sel_reg[1]_17\ : out STD_LOGIC;
    \calib_sel_reg[1]_18\ : out STD_LOGIC;
    \calib_sel_reg[1]_19\ : out STD_LOGIC;
    \calib_sel_reg[1]_20\ : out STD_LOGIC;
    \calib_sel_reg[1]_21\ : out STD_LOGIC;
    \calib_sel_reg[1]_22\ : out STD_LOGIC;
    \calib_sel_reg[1]_23\ : out STD_LOGIC;
    idelay_ce_r2_reg_0 : out STD_LOGIC;
    \calib_sel_reg[0]_1\ : out STD_LOGIC;
    \pi_rst_stg1_cal_reg[0]\ : out STD_LOGIC;
    \calib_sel_reg[0]_2\ : out STD_LOGIC;
    \calib_sel_reg[0]_3\ : out STD_LOGIC;
    pi_stg2_load_reg : out STD_LOGIC;
    \calib_sel_reg[1]_24\ : out STD_LOGIC;
    \calib_sel_reg[1]_25\ : out STD_LOGIC;
    \calib_sel_reg[1]_26\ : out STD_LOGIC;
    \calib_sel_reg[1]_27\ : out STD_LOGIC;
    \calib_sel_reg[1]_28\ : out STD_LOGIC;
    \calib_sel_reg[1]_29\ : out STD_LOGIC;
    \calib_sel_reg[1]_30\ : out STD_LOGIC;
    \calib_sel_reg[1]_31\ : out STD_LOGIC;
    \calib_sel_reg[1]_32\ : out STD_LOGIC;
    dqs_wl_po_stg2_c_incdec_reg_0 : out STD_LOGIC;
    \calib_sel_reg[1]_33\ : out STD_LOGIC;
    \calib_sel_reg[1]_34\ : out STD_LOGIC;
    \calib_sel_reg[1]_35\ : out STD_LOGIC;
    \calib_sel_reg[0]_4\ : out STD_LOGIC;
    \calib_sel_reg[1]_36\ : out STD_LOGIC;
    \calib_sel_reg[1]_37\ : out STD_LOGIC;
    \calib_sel_reg[1]_38\ : out STD_LOGIC;
    \calib_sel_reg[1]_39\ : out STD_LOGIC;
    \calib_sel_reg[1]_40\ : out STD_LOGIC;
    \calib_sel_reg[1]_41\ : out STD_LOGIC;
    \calib_sel_reg[1]_42\ : out STD_LOGIC;
    \calib_sel_reg[1]_43\ : out STD_LOGIC;
    \calib_sel_reg[1]_44\ : out STD_LOGIC;
    \calib_sel_reg[1]_45\ : out STD_LOGIC;
    \calib_sel_reg[1]_46\ : out STD_LOGIC;
    \calib_sel_reg[1]_47\ : out STD_LOGIC;
    idelay_ce_r2_reg_1 : out STD_LOGIC;
    \calib_sel_reg[0]_5\ : out STD_LOGIC;
    \pi_rst_stg1_cal_reg[2]\ : out STD_LOGIC;
    \calib_sel_reg[0]_6\ : out STD_LOGIC;
    \calib_sel_reg[0]_7\ : out STD_LOGIC;
    pi_stg2_load_reg_0 : out STD_LOGIC;
    C_po_coarse_enable26_out : out STD_LOGIC;
    \gen_byte_sel_div2.calib_in_common_reg_0\ : out STD_LOGIC;
    \gen_byte_sel_div2.calib_in_common_reg_1\ : out STD_LOGIC;
    C_po_fine_enable23_out : out STD_LOGIC;
    \gen_byte_sel_div2.calib_in_common_reg_2\ : out STD_LOGIC;
    \gen_byte_sel_div2.calib_in_common_reg_3\ : out STD_LOGIC;
    \gen_byte_sel_div2.calib_in_common_reg_4\ : out STD_LOGIC;
    \gen_byte_sel_div2.calib_in_common_reg_5\ : out STD_LOGIC;
    C_po_counter_read_en38_out : out STD_LOGIC;
    dqs_po_stg2_f_incdec_reg : out STD_LOGIC;
    dqs_po_stg2_f_incdec_reg_0 : out STD_LOGIC;
    dqs_po_stg2_f_incdec_reg_1 : out STD_LOGIC;
    dqs_po_stg2_f_incdec_reg_2 : out STD_LOGIC;
    dqs_po_stg2_f_incdec_reg_3 : out STD_LOGIC;
    dqs_po_stg2_f_incdec_reg_4 : out STD_LOGIC;
    dqs_po_stg2_f_incdec_reg_5 : out STD_LOGIC;
    dqs_po_stg2_f_incdec_reg_6 : out STD_LOGIC;
    C_po_fine_inc29_out : out STD_LOGIC;
    dqs_po_stg2_f_incdec_reg_7 : out STD_LOGIC;
    dqs_po_stg2_f_incdec_reg_8 : out STD_LOGIC;
    D6 : out STD_LOGIC_VECTOR ( 7 downto 0 );
    D8 : out STD_LOGIC_VECTOR ( 3 downto 0 );
    \gen_no_mirror.div_clk_loop[0].phy_address_reg[2]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
    D5 : out STD_LOGIC_VECTOR ( 3 downto 0 );
    D4 : out STD_LOGIC_VECTOR ( 3 downto 0 );
    D7 : out STD_LOGIC_VECTOR ( 3 downto 0 );
    D9 : out STD_LOGIC_VECTOR ( 3 downto 0 );
    D1 : out STD_LOGIC_VECTOR ( 3 downto 0 );
    \gen_no_mirror.div_clk_loop[0].phy_address_reg[8]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
    \gen_no_mirror.div_clk_loop[0].phy_address_reg[9]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
    D3 : out STD_LOGIC_VECTOR ( 3 downto 0 );
    \gen_no_mirror.div_clk_loop[0].phy_bank_reg[0]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
    \gen_no_mirror.div_clk_loop[0].phy_bank_reg[1]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
    \write_buffer.wr_buf_out_data_reg[448]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
    D2 : out STD_LOGIC_VECTOR ( 7 downto 0 );
    \write_buffer.wr_buf_out_data_reg[450]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
    \write_buffer.wr_buf_out_data_reg[451]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
    \write_buffer.wr_buf_out_data_reg[452]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
    \write_buffer.wr_buf_out_data_reg[453]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
    \write_buffer.wr_buf_out_data_reg[454]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
    \write_buffer.wr_buf_out_data_reg[455]_0\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
    \write_buffer.wr_buf_out_data_reg[456]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
    \write_buffer.wr_buf_out_data_reg[457]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
    \write_buffer.wr_buf_out_data_reg[458]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
    \write_buffer.wr_buf_out_data_reg[459]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
    \write_buffer.wr_buf_out_data_reg[460]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
    \write_buffer.wr_buf_out_data_reg[461]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
    \write_buffer.wr_buf_out_data_reg[462]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
    \write_buffer.wr_buf_out_data_reg[463]_0\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
    \write_buffer.wr_buf_out_data_reg[464]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
    \write_buffer.wr_buf_out_data_reg[465]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
    \write_buffer.wr_buf_out_data_reg[466]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
    \write_buffer.wr_buf_out_data_reg[467]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
    \write_buffer.wr_buf_out_data_reg[468]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
    \write_buffer.wr_buf_out_data_reg[469]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
    \write_buffer.wr_buf_out_data_reg[470]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
    \write_buffer.wr_buf_out_data_reg[471]_0\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
    \write_buffer.wr_buf_out_data_reg[472]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
    \write_buffer.wr_buf_out_data_reg[473]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
    \write_buffer.wr_buf_out_data_reg[474]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
    \write_buffer.wr_buf_out_data_reg[475]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
    \write_buffer.wr_buf_out_data_reg[476]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
    \write_buffer.wr_buf_out_data_reg[477]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
    \write_buffer.wr_buf_out_data_reg[478]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
    \write_buffer.wr_buf_out_data_reg[479]_0\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
    \write_buffer.wr_buf_out_data_reg[480]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
    \write_buffer.wr_buf_out_data_reg[481]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
    \write_buffer.wr_buf_out_data_reg[482]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
    \write_buffer.wr_buf_out_data_reg[483]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
    \write_buffer.wr_buf_out_data_reg[484]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
    \write_buffer.wr_buf_out_data_reg[485]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
    \write_buffer.wr_buf_out_data_reg[486]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
    \write_buffer.wr_buf_out_data_reg[487]_0\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
    \write_buffer.wr_buf_out_data_reg[488]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
    \write_buffer.wr_buf_out_data_reg[489]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
    \write_buffer.wr_buf_out_data_reg[490]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
    \write_buffer.wr_buf_out_data_reg[491]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
    \write_buffer.wr_buf_out_data_reg[492]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
    \write_buffer.wr_buf_out_data_reg[493]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
    \write_buffer.wr_buf_out_data_reg[494]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
    \write_buffer.wr_buf_out_data_reg[495]_0\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
    \write_buffer.wr_buf_out_data_reg[496]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
    \write_buffer.wr_buf_out_data_reg[497]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
    \write_buffer.wr_buf_out_data_reg[498]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
    \write_buffer.wr_buf_out_data_reg[499]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
    \write_buffer.wr_buf_out_data_reg[500]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
    \write_buffer.wr_buf_out_data_reg[501]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
    \write_buffer.wr_buf_out_data_reg[502]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
    \write_buffer.wr_buf_out_data_reg[503]_0\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
    \write_buffer.wr_buf_out_data_reg[504]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
    \write_buffer.wr_buf_out_data_reg[505]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
    \write_buffer.wr_buf_out_data_reg[506]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
    \write_buffer.wr_buf_out_data_reg[507]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
    \write_buffer.wr_buf_out_data_reg[508]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
    \write_buffer.wr_buf_out_data_reg[509]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
    \write_buffer.wr_buf_out_data_reg[510]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
    \write_buffer.wr_buf_out_data_reg[511]_0\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
    \cmd_pipe_plus.mc_ras_n_reg[1]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \cmd_pipe_plus.mc_cas_n_reg[1]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    \cmd_pipe_plus.mc_odt_reg[0]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
    \cmd_pipe_plus.mc_cke_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
    \cmd_pipe_plus.mc_we_n_reg[1]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    \init_calib_complete_reg_rep__26_1\ : out STD_LOGIC;
    app_rd_data_valid : out STD_LOGIC;
    \read_fifo.tail_r_reg[0]\ : out STD_LOGIC;
    \rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][0]\ : out STD_LOGIC;
    \rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][5]\ : out STD_LOGIC_VECTOR ( 5 downto 0 );
    \rank_final_loop[0].bank_final_loop[1].final_data_offset_mc_reg[0][6]\ : out STD_LOGIC;
    \rank_final_loop[0].bank_final_loop[1].final_data_offset_mc_reg[0][11]\ : out STD_LOGIC_VECTOR ( 5 downto 0 );
    \rank_final_loop[0].bank_final_loop[2].final_data_offset_mc_reg[0][12]\ : out STD_LOGIC;
    \rank_final_loop[0].bank_final_loop[2].final_data_offset_mc_reg[0][17]\ : out STD_LOGIC_VECTOR ( 5 downto 0 );
    \init_state_r_reg[4]\ : out STD_LOGIC;
    SR : out STD_LOGIC_VECTOR ( 0 to 0 );
    pi_rst_dqs_find : out STD_LOGIC_VECTOR ( 2 downto 0 );
    pi_counter_load_val : out STD_LOGIC_VECTOR ( 5 downto 0 );
    \rd_mux_sel_r_reg[2]_0\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
    D : out STD_LOGIC_VECTOR ( 10 downto 0 );
    COUNTERLOADVAL : out STD_LOGIC_VECTOR ( 5 downto 0 );
    \calib_sel_reg[1]_48\ : out STD_LOGIC_VECTOR ( 5 downto 0 );
    \calib_sel_reg[1]_49\ : out STD_LOGIC_VECTOR ( 5 downto 0 );
    \pi_stg2_reg_l_reg[5]\ : out STD_LOGIC_VECTOR ( 5 downto 0 );
    \calib_sel_reg[1]_50\ : out STD_LOGIC_VECTOR ( 5 downto 0 );
    \calib_sel_reg[1]_51\ : out STD_LOGIC_VECTOR ( 5 downto 0 );
    \calib_sel_reg[1]_52\ : out STD_LOGIC_VECTOR ( 5 downto 0 );
    \pi_stg2_reg_l_reg[5]_0\ : out STD_LOGIC_VECTOR ( 5 downto 0 );
    \cmd_pipe_plus.mc_data_offset_1_reg[5]\ : out STD_LOGIC_VECTOR ( 5 downto 0 );
    \cmd_pipe_plus.mc_data_offset_2_reg[5]\ : out STD_LOGIC_VECTOR ( 5 downto 0 );
    phy_data_wr_en : out STD_LOGIC;
    phy_cmd_wr_en : out STD_LOGIC;
    mux_reset_n : out STD_LOGIC;
    \cmd_pipe_plus.mc_cke_reg[3]_0\ : out STD_LOGIC_VECTOR ( 5 downto 0 );
    Q : in STD_LOGIC_VECTOR ( 0 to 0 );
    \dout_o_reg[15]\ : in STD_LOGIC;
    \fine_dec_cnt_reg[5]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \corse_inc_reg[6][2]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \wl_dqs_tap_count_r_reg[0][5][5]\ : in STD_LOGIC;
    po_en_stg2_f_reg : in STD_LOGIC;
    in0 : in STD_LOGIC_VECTOR ( 7 downto 0 );
    first_fail_detect_reg : in STD_LOGIC;
    \rdlvl_dqs_tap_cnt_r_reg[0][0][2]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \gen_mux_rd[0].mux_rd_rise0_r_reg[0]\ : in STD_LOGIC;
    \gen_mux_rd[1].mux_rd_rise0_r_reg[1]\ : in STD_LOGIC;
    \gen_mux_rd[2].mux_rd_rise0_r_reg[2]\ : in STD_LOGIC;
    \gen_mux_rd[3].mux_rd_rise0_r_reg[3]\ : in STD_LOGIC;
    \gen_mux_rd[4].mux_rd_rise0_r_reg[4]\ : in STD_LOGIC;
    \gen_mux_rd[5].mux_rd_rise0_r_reg[5]\ : in STD_LOGIC;
    \gen_mux_rd[6].mux_rd_rise0_r_reg[6]\ : in STD_LOGIC;
    \gen_mux_rd[7].mux_rd_rise0_r_reg[7]\ : in STD_LOGIC;
    \gen_mux_rd[0].mux_rd_fall0_r_reg[0]\ : in STD_LOGIC;
    \gen_mux_rd[1].mux_rd_fall0_r_reg[1]\ : in STD_LOGIC;
    \gen_mux_rd[2].mux_rd_fall0_r_reg[2]\ : in STD_LOGIC;
    \gen_mux_rd[3].mux_rd_fall0_r_reg[3]\ : in STD_LOGIC;
    \gen_mux_rd[4].mux_rd_fall0_r_reg[4]\ : in STD_LOGIC;
    \gen_mux_rd[5].mux_rd_fall0_r_reg[5]\ : in STD_LOGIC;
    \gen_mux_rd[6].mux_rd_fall0_r_reg[6]\ : in STD_LOGIC;
    \gen_mux_rd[7].mux_rd_fall0_r_reg[7]\ : in STD_LOGIC;
    \gen_mux_rd[0].mux_rd_rise1_r_reg[0]\ : in STD_LOGIC;
    \gen_mux_rd[1].mux_rd_rise1_r_reg[1]\ : in STD_LOGIC;
    \gen_mux_rd[2].mux_rd_rise1_r_reg[2]\ : in STD_LOGIC;
    \gen_mux_rd[3].mux_rd_rise1_r_reg[3]\ : in STD_LOGIC;
    \gen_mux_rd[4].mux_rd_rise1_r_reg[4]\ : in STD_LOGIC;
    \gen_mux_rd[5].mux_rd_rise1_r_reg[5]\ : in STD_LOGIC;
    \gen_mux_rd[6].mux_rd_rise1_r_reg[6]\ : in STD_LOGIC;
    \gen_mux_rd[7].mux_rd_rise1_r_reg[7]\ : in STD_LOGIC;
    \gen_mux_rd[0].mux_rd_fall1_r_reg[0]\ : in STD_LOGIC;
    \gen_mux_rd[1].mux_rd_fall1_r_reg[1]\ : in STD_LOGIC;
    \gen_mux_rd[2].mux_rd_fall1_r_reg[2]\ : in STD_LOGIC;
    \gen_mux_rd[3].mux_rd_fall1_r_reg[3]\ : in STD_LOGIC;
    \gen_mux_rd[4].mux_rd_fall1_r_reg[4]\ : in STD_LOGIC;
    \gen_mux_rd[5].mux_rd_fall1_r_reg[5]\ : in STD_LOGIC;
    \gen_mux_rd[6].mux_rd_fall1_r_reg[6]\ : in STD_LOGIC;
    \gen_mux_rd[7].mux_rd_fall1_r_reg[7]\ : in STD_LOGIC;
    \gen_mux_rd[0].mux_rd_rise2_r_reg[0]\ : in STD_LOGIC;
    \gen_mux_rd[1].mux_rd_rise2_r_reg[1]\ : in STD_LOGIC;
    \gen_mux_rd[2].mux_rd_rise2_r_reg[2]\ : in STD_LOGIC;
    \gen_mux_rd[3].mux_rd_rise2_r_reg[3]\ : in STD_LOGIC;
    \gen_mux_rd[4].mux_rd_rise2_r_reg[4]\ : in STD_LOGIC;
    \gen_mux_rd[5].mux_rd_rise2_r_reg[5]\ : in STD_LOGIC;
    \gen_mux_rd[6].mux_rd_rise2_r_reg[6]\ : in STD_LOGIC;
    \gen_mux_rd[7].mux_rd_rise2_r_reg[7]\ : in STD_LOGIC;
    \gen_mux_rd[0].mux_rd_fall2_r_reg[0]\ : in STD_LOGIC;
    \gen_mux_rd[1].mux_rd_fall2_r_reg[1]\ : in STD_LOGIC;
    \gen_mux_rd[2].mux_rd_fall2_r_reg[2]\ : in STD_LOGIC;
    \gen_mux_rd[3].mux_rd_fall2_r_reg[3]\ : in STD_LOGIC;
    \gen_mux_rd[4].mux_rd_fall2_r_reg[4]\ : in STD_LOGIC;
    \gen_mux_rd[5].mux_rd_fall2_r_reg[5]\ : in STD_LOGIC;
    \gen_mux_rd[6].mux_rd_fall2_r_reg[6]\ : in STD_LOGIC;
    \gen_mux_rd[7].mux_rd_fall2_r_reg[7]\ : in STD_LOGIC;
    \gen_mux_rd[0].mux_rd_rise3_r_reg[0]\ : in STD_LOGIC;
    \gen_mux_rd[1].mux_rd_rise3_r_reg[1]\ : in STD_LOGIC;
    \gen_mux_rd[2].mux_rd_rise3_r_reg[2]\ : in STD_LOGIC;
    \gen_mux_rd[3].mux_rd_rise3_r_reg[3]\ : in STD_LOGIC;
    \gen_mux_rd[4].mux_rd_rise3_r_reg[4]\ : in STD_LOGIC;
    \gen_mux_rd[5].mux_rd_rise3_r_reg[5]\ : in STD_LOGIC;
    \gen_mux_rd[6].mux_rd_rise3_r_reg[6]\ : in STD_LOGIC;
    \gen_mux_rd[7].mux_rd_rise3_r_reg[7]\ : in STD_LOGIC;
    \gen_mux_rd[0].mux_rd_fall3_r_reg[0]\ : in STD_LOGIC;
    \gen_mux_rd[1].mux_rd_fall3_r_reg[1]\ : in STD_LOGIC;
    \gen_mux_rd[2].mux_rd_fall3_r_reg[2]\ : in STD_LOGIC;
    \gen_mux_rd[3].mux_rd_fall3_r_reg[3]\ : in STD_LOGIC;
    \gen_mux_rd[4].mux_rd_fall3_r_reg[4]\ : in STD_LOGIC;
    \gen_mux_rd[5].mux_rd_fall3_r_reg[5]\ : in STD_LOGIC;
    \gen_mux_rd[6].mux_rd_fall3_r_reg[6]\ : in STD_LOGIC;
    \gen_mux_rd[7].mux_rd_fall3_r_reg[7]\ : in STD_LOGIC;
    \samp_edge_cnt1_r_reg[0]\ : in STD_LOGIC;
    \FSM_onehot_cal1_state_r_reg[7]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \samples_cnt_r_reg[0]\ : in STD_LOGIC;
    \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]\ : in STD_LOGIC;
    \gen_mux_rd[1].mux_rd_rise0_r1_reg[1]\ : in STD_LOGIC;
    \gen_mux_rd[2].mux_rd_rise0_r1_reg[2]\ : in STD_LOGIC;
    \gen_mux_rd[3].mux_rd_rise0_r1_reg[3]\ : in STD_LOGIC;
    \gen_mux_rd[4].mux_rd_rise0_r1_reg[4]\ : in STD_LOGIC;
    \gen_mux_rd[5].mux_rd_rise0_r1_reg[5]\ : in STD_LOGIC;
    \gen_mux_rd[6].mux_rd_rise0_r1_reg[6]\ : in STD_LOGIC;
    \gen_mux_rd[7].mux_rd_rise0_r1_reg[7]\ : in STD_LOGIC;
    \gen_mux_rd[0].mux_rd_fall0_r1_reg[0]\ : in STD_LOGIC;
    \gen_mux_rd[1].mux_rd_fall0_r1_reg[1]\ : in STD_LOGIC;
    \gen_mux_rd[2].mux_rd_fall0_r1_reg[2]\ : in STD_LOGIC;
    \gen_mux_rd[3].mux_rd_fall0_r1_reg[3]\ : in STD_LOGIC;
    \gen_mux_rd[4].mux_rd_fall0_r1_reg[4]\ : in STD_LOGIC;
    \gen_mux_rd[5].mux_rd_fall0_r1_reg[5]\ : in STD_LOGIC;
    \gen_mux_rd[6].mux_rd_fall0_r1_reg[6]\ : in STD_LOGIC;
    \gen_mux_rd[7].mux_rd_fall0_r1_reg[7]\ : in STD_LOGIC;
    \gen_mux_rd[0].mux_rd_rise1_r1_reg[0]\ : in STD_LOGIC;
    \gen_mux_rd[1].mux_rd_rise1_r1_reg[1]\ : in STD_LOGIC;
    \gen_mux_rd[2].mux_rd_rise1_r1_reg[2]\ : in STD_LOGIC;
    \gen_mux_rd[3].mux_rd_rise1_r1_reg[3]\ : in STD_LOGIC;
    \gen_mux_rd[4].mux_rd_rise1_r1_reg[4]\ : in STD_LOGIC;
    \gen_mux_rd[5].mux_rd_rise1_r1_reg[5]\ : in STD_LOGIC;
    \gen_mux_rd[6].mux_rd_rise1_r1_reg[6]\ : in STD_LOGIC;
    \gen_mux_rd[7].mux_rd_rise1_r1_reg[7]\ : in STD_LOGIC;
    \gen_mux_rd[0].mux_rd_fall1_r1_reg[0]\ : in STD_LOGIC;
    \gen_mux_rd[1].mux_rd_fall1_r1_reg[1]\ : in STD_LOGIC;
    \gen_mux_rd[2].mux_rd_fall1_r1_reg[2]\ : in STD_LOGIC;
    \gen_mux_rd[3].mux_rd_fall1_r1_reg[3]\ : in STD_LOGIC;
    \gen_mux_rd[4].mux_rd_fall1_r1_reg[4]\ : in STD_LOGIC;
    \gen_mux_rd[5].mux_rd_fall1_r1_reg[5]\ : in STD_LOGIC;
    \gen_mux_rd[6].mux_rd_fall1_r1_reg[6]\ : in STD_LOGIC;
    \gen_mux_rd[7].mux_rd_fall1_r1_reg[7]\ : in STD_LOGIC;
    \gen_mux_rd[0].mux_rd_rise2_r1_reg[0]\ : in STD_LOGIC;
    \gen_mux_rd[1].mux_rd_rise2_r1_reg[1]\ : in STD_LOGIC;
    \gen_mux_rd[2].mux_rd_rise2_r1_reg[2]\ : in STD_LOGIC;
    \gen_mux_rd[3].mux_rd_rise2_r1_reg[3]\ : in STD_LOGIC;
    \gen_mux_rd[4].mux_rd_rise2_r1_reg[4]\ : in STD_LOGIC;
    \gen_mux_rd[5].mux_rd_rise2_r1_reg[5]\ : in STD_LOGIC;
    \gen_mux_rd[6].mux_rd_rise2_r1_reg[6]\ : in STD_LOGIC;
    \gen_mux_rd[7].mux_rd_rise2_r1_reg[7]\ : in STD_LOGIC;
    \gen_mux_rd[0].mux_rd_fall2_r1_reg[0]\ : in STD_LOGIC;
    \gen_mux_rd[1].mux_rd_fall2_r1_reg[1]\ : in STD_LOGIC;
    \gen_mux_rd[2].mux_rd_fall2_r1_reg[2]\ : in STD_LOGIC;
    \gen_mux_rd[3].mux_rd_fall2_r1_reg[3]\ : in STD_LOGIC;
    \gen_mux_rd[4].mux_rd_fall2_r1_reg[4]\ : in STD_LOGIC;
    \gen_mux_rd[5].mux_rd_fall2_r1_reg[5]\ : in STD_LOGIC;
    \gen_mux_rd[6].mux_rd_fall2_r1_reg[6]\ : in STD_LOGIC;
    \gen_mux_rd[7].mux_rd_fall2_r1_reg[7]\ : in STD_LOGIC;
    \gen_mux_rd[0].mux_rd_rise3_r1_reg[0]\ : in STD_LOGIC;
    \gen_mux_rd[1].mux_rd_rise3_r1_reg[1]\ : in STD_LOGIC;
    \gen_mux_rd[2].mux_rd_rise3_r1_reg[2]\ : in STD_LOGIC;
    \gen_mux_rd[3].mux_rd_rise3_r1_reg[3]\ : in STD_LOGIC;
    \gen_mux_rd[4].mux_rd_rise3_r1_reg[4]\ : in STD_LOGIC;
    \gen_mux_rd[5].mux_rd_rise3_r1_reg[5]\ : in STD_LOGIC;
    \gen_mux_rd[6].mux_rd_rise3_r1_reg[6]\ : in STD_LOGIC;
    \gen_mux_rd[7].mux_rd_rise3_r1_reg[7]\ : in STD_LOGIC;
    \gen_mux_rd[0].mux_rd_fall3_r1_reg[0]\ : in STD_LOGIC;
    \gen_mux_rd[1].mux_rd_fall3_r1_reg[1]\ : in STD_LOGIC;
    \gen_mux_rd[2].mux_rd_fall3_r1_reg[2]\ : in STD_LOGIC;
    \gen_mux_rd[3].mux_rd_fall3_r1_reg[3]\ : in STD_LOGIC;
    \gen_mux_rd[4].mux_rd_fall3_r1_reg[4]\ : in STD_LOGIC;
    \gen_mux_rd[5].mux_rd_fall3_r1_reg[5]\ : in STD_LOGIC;
    \gen_mux_rd[6].mux_rd_fall3_r1_reg[6]\ : in STD_LOGIC;
    \gen_mux_rd[7].mux_rd_fall3_r1_reg[7]\ : in STD_LOGIC;
    \en_cnt_div4.enable_wrlvl_cnt_reg[2]\ : in STD_LOGIC;
    pi_phase_locked_all_r1_reg : in STD_LOGIC;
    \victim_sel_reg[0]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \four_dec_min_limit_reg[0]\ : in STD_LOGIC;
    mc_ref_zq_wip : in STD_LOGIC;
    \one_dec_min_limit_reg[11]\ : in STD_LOGIC;
    \one_dec_max_limit_reg[2]\ : in STD_LOGIC;
    phy_rddata_en : in STD_LOGIC;
    if_empty : in STD_LOGIC;
    p_0_out : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg[1]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg[2]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg[3]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg[4]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg[5]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg[6]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg[7]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg[0]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg[1]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg[2]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg[3]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg[4]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg[5]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg[6]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg[0]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg[1]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg[2]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg[3]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg[4]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg[5]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg[6]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg[7]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise2_r_reg[0]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg[1]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg[2]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg[3]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise2_r_reg[4]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg[5]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg[6]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg[7]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg[0]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg[1]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg[2]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg[3]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg[4]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg[5]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg[6]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg[7]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg[0]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg[1]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg[2]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise3_r_reg[3]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg[4]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg[5]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg[6]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise3_r_reg[7]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg[0]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg[1]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg[2]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg[3]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg[4]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg[5]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg[6]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg[7]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg[0]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg[1]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg[2]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg[3]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg[4]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg[5]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg[6]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg[7]\ : in STD_LOGIC;
    cal2_if_reset_reg : in STD_LOGIC;
    \idelay_tap_cnt_r_reg[0][0][4]\ : in STD_LOGIC;
    \not_empty_wait_cnt_reg[4]\ : in STD_LOGIC;
    \complex_num_writes_reg[1]\ : in STD_LOGIC;
    mem_reg_0_15_12_17 : in STD_LOGIC_VECTOR ( 575 downto 0 );
    idelay_ld_rst : in STD_LOGIC;
    idelay_ld_rst_7 : in STD_LOGIC;
    idelay_ld_rst_8 : in STD_LOGIC;
    idelay_ld_rst_9 : in STD_LOGIC;
    idelay_ld_rst_10 : in STD_LOGIC;
    idelay_ld_rst_11 : in STD_LOGIC;
    idelay_ld_rst_12 : in STD_LOGIC;
    idelay_ld_rst_13 : in STD_LOGIC;
    \out\ : in STD_LOGIC;
    ififo_rst_reg : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \pi_dqs_found_lanes_r1_reg[0]\ : in STD_LOGIC;
    \pi_dqs_found_lanes_r1_reg[0]_0\ : in STD_LOGIC;
    mc_address : in STD_LOGIC_VECTOR ( 34 downto 0 );
    mem_out : in STD_LOGIC_VECTOR ( 35 downto 0 );
    out_fifo : in STD_LOGIC;
    out_fifo_0 : in STD_LOGIC_VECTOR ( 23 downto 0 );
    out_fifo_1 : in STD_LOGIC;
    mc_ras_n : in STD_LOGIC_VECTOR ( 0 to 0 );
    mc_bank : in STD_LOGIC_VECTOR ( 8 downto 0 );
    out_fifo_2 : in STD_LOGIC_VECTOR ( 63 downto 0 );
    out_fifo_3 : in STD_LOGIC;
    out_fifo_4 : in STD_LOGIC_VECTOR ( 63 downto 0 );
    out_fifo_5 : in STD_LOGIC;
    out_fifo_6 : in STD_LOGIC_VECTOR ( 63 downto 0 );
    out_fifo_7 : in STD_LOGIC;
    out_fifo_8 : in STD_LOGIC_VECTOR ( 63 downto 0 );
    out_fifo_9 : in STD_LOGIC;
    out_fifo_10 : in STD_LOGIC_VECTOR ( 63 downto 0 );
    out_fifo_11 : in STD_LOGIC;
    out_fifo_12 : in STD_LOGIC_VECTOR ( 63 downto 0 );
    out_fifo_13 : in STD_LOGIC;
    out_fifo_14 : in STD_LOGIC_VECTOR ( 63 downto 0 );
    out_fifo_15 : in STD_LOGIC;
    out_fifo_16 : in STD_LOGIC_VECTOR ( 63 downto 0 );
    out_fifo_17 : in STD_LOGIC;
    mc_cas_n : in STD_LOGIC_VECTOR ( 0 to 0 );
    out_fifo_18 : in STD_LOGIC_VECTOR ( 11 downto 0 );
    out_fifo_19 : in STD_LOGIC;
    mc_odt : in STD_LOGIC_VECTOR ( 0 to 0 );
    mc_cke : in STD_LOGIC_VECTOR ( 0 to 0 );
    mc_we_n : in STD_LOGIC_VECTOR ( 0 to 0 );
    app_rd_data_valid_0 : in STD_LOGIC_VECTOR ( 0 to 0 );
    \read_fifo.tail_r\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \idelay_tap_cnt_r_reg[0][4][4]\ : in STD_LOGIC;
    \po_rdval_cnt_reg[7]\ : in STD_LOGIC;
    \po_rdval_cnt_reg[8]\ : in STD_LOGIC;
    \po_rdval_cnt_reg[0]\ : in STD_LOGIC;
    \po_rdval_cnt_reg[1]\ : in STD_LOGIC;
    \po_rdval_cnt_reg[2]\ : in STD_LOGIC;
    \po_rdval_cnt_reg[3]\ : in STD_LOGIC;
    \po_rdval_cnt_reg[4]\ : in STD_LOGIC;
    \po_rdval_cnt_reg[5]\ : in STD_LOGIC;
    \po_rdval_cnt_reg[6]\ : in STD_LOGIC;
    \pi_rst_stg1_cal_r_reg[1]\ : in STD_LOGIC;
    \cmp_err_4to1.compare_err_f3_reg\ : in STD_LOGIC;
    \fine_inc_reg[6][3]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \corse_dec_reg[7][0]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    SS : in STD_LOGIC_VECTOR ( 0 to 0 );
    \wait_cnt_r_reg[0]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \tap_cnt_cpt_r_reg[5]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \cnt_shift_r_reg[0]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \wait_cnt_r_reg[0]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \en_cnt_div4.enable_wrlvl_cnt_reg[4]\ : in STD_LOGIC;
    \device_temp_101_reg[11]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
    \gen_rd[0].rd_data_rise_wl_r_reg[0]\ : in STD_LOGIC;
    \gen_rd[0].rd_data_rise_wl_r_reg[0]_0\ : in STD_LOGIC;
    \gen_rd[0].rd_data_rise_wl_r_reg[0]_1\ : in STD_LOGIC;
    \gen_rd[0].rd_data_rise_wl_r_reg[0]_2\ : in STD_LOGIC;
    \gen_rd[0].rd_data_rise_wl_r_reg[0]_3\ : in STD_LOGIC;
    \gen_rd[0].rd_data_rise_wl_r_reg[0]_4\ : in STD_LOGIC;
    \gen_rd[0].rd_data_rise_wl_r_reg[0]_5\ : in STD_LOGIC;
    \gen_rd[0].rd_data_rise_wl_r_reg[0]_6\ : in STD_LOGIC;
    \gen_rd[1].rd_data_rise_wl_r_reg[1]\ : in STD_LOGIC;
    \gen_rd[1].rd_data_rise_wl_r_reg[1]_0\ : in STD_LOGIC;
    \gen_rd[1].rd_data_rise_wl_r_reg[1]_1\ : in STD_LOGIC;
    \gen_rd[1].rd_data_rise_wl_r_reg[1]_2\ : in STD_LOGIC;
    \gen_rd[1].rd_data_rise_wl_r_reg[1]_3\ : in STD_LOGIC;
    \gen_rd[1].rd_data_rise_wl_r_reg[1]_4\ : in STD_LOGIC;
    \gen_rd[1].rd_data_rise_wl_r_reg[1]_5\ : in STD_LOGIC;
    \gen_rd[1].rd_data_rise_wl_r_reg[1]_6\ : in STD_LOGIC;
    \gen_rd[2].rd_data_rise_wl_r_reg[2]\ : in STD_LOGIC;
    \gen_rd[2].rd_data_rise_wl_r_reg[2]_0\ : in STD_LOGIC;
    \gen_rd[2].rd_data_rise_wl_r_reg[2]_1\ : in STD_LOGIC;
    \gen_rd[2].rd_data_rise_wl_r_reg[2]_2\ : in STD_LOGIC;
    \gen_rd[2].rd_data_rise_wl_r_reg[2]_3\ : in STD_LOGIC;
    \gen_rd[2].rd_data_rise_wl_r_reg[2]_4\ : in STD_LOGIC;
    \gen_rd[2].rd_data_rise_wl_r_reg[2]_5\ : in STD_LOGIC;
    \gen_rd[2].rd_data_rise_wl_r_reg[2]_6\ : in STD_LOGIC;
    \gen_rd[3].rd_data_rise_wl_r_reg[3]\ : in STD_LOGIC;
    \gen_rd[3].rd_data_rise_wl_r_reg[3]_0\ : in STD_LOGIC;
    \gen_rd[3].rd_data_rise_wl_r_reg[3]_1\ : in STD_LOGIC;
    \gen_rd[3].rd_data_rise_wl_r_reg[3]_2\ : in STD_LOGIC;
    \gen_rd[3].rd_data_rise_wl_r_reg[3]_3\ : in STD_LOGIC;
    \gen_rd[3].rd_data_rise_wl_r_reg[3]_4\ : in STD_LOGIC;
    \gen_rd[3].rd_data_rise_wl_r_reg[3]_5\ : in STD_LOGIC;
    \gen_rd[3].rd_data_rise_wl_r_reg[3]_6\ : in STD_LOGIC;
    \gen_rd[4].rd_data_rise_wl_r_reg[4]\ : in STD_LOGIC;
    \gen_rd[4].rd_data_rise_wl_r_reg[4]_0\ : in STD_LOGIC;
    \gen_rd[4].rd_data_rise_wl_r_reg[4]_1\ : in STD_LOGIC;
    \gen_rd[4].rd_data_rise_wl_r_reg[4]_2\ : in STD_LOGIC;
    \gen_rd[4].rd_data_rise_wl_r_reg[4]_3\ : in STD_LOGIC;
    \gen_rd[4].rd_data_rise_wl_r_reg[4]_4\ : in STD_LOGIC;
    \gen_rd[4].rd_data_rise_wl_r_reg[4]_5\ : in STD_LOGIC;
    \gen_rd[4].rd_data_rise_wl_r_reg[4]_6\ : in STD_LOGIC;
    \gen_rd[5].rd_data_rise_wl_r_reg[5]\ : in STD_LOGIC;
    \gen_rd[5].rd_data_rise_wl_r_reg[5]_0\ : in STD_LOGIC;
    \gen_rd[5].rd_data_rise_wl_r_reg[5]_1\ : in STD_LOGIC;
    \gen_rd[5].rd_data_rise_wl_r_reg[5]_2\ : in STD_LOGIC;
    \gen_rd[5].rd_data_rise_wl_r_reg[5]_3\ : in STD_LOGIC;
    \gen_rd[5].rd_data_rise_wl_r_reg[5]_4\ : in STD_LOGIC;
    \gen_rd[5].rd_data_rise_wl_r_reg[5]_5\ : in STD_LOGIC;
    \gen_rd[5].rd_data_rise_wl_r_reg[5]_6\ : in STD_LOGIC;
    \gen_rd[6].rd_data_rise_wl_r_reg[6]\ : in STD_LOGIC;
    \gen_rd[6].rd_data_rise_wl_r_reg[6]_0\ : in STD_LOGIC;
    \gen_rd[6].rd_data_rise_wl_r_reg[6]_1\ : in STD_LOGIC;
    \gen_rd[6].rd_data_rise_wl_r_reg[6]_2\ : in STD_LOGIC;
    \gen_rd[6].rd_data_rise_wl_r_reg[6]_3\ : in STD_LOGIC;
    \gen_rd[6].rd_data_rise_wl_r_reg[6]_4\ : in STD_LOGIC;
    \gen_rd[6].rd_data_rise_wl_r_reg[6]_5\ : in STD_LOGIC;
    \gen_rd[6].rd_data_rise_wl_r_reg[6]_6\ : in STD_LOGIC;
    \gen_rd[7].rd_data_rise_wl_r_reg[7]\ : in STD_LOGIC;
    \gen_rd[7].rd_data_rise_wl_r_reg[7]_0\ : in STD_LOGIC;
    \gen_rd[7].rd_data_rise_wl_r_reg[7]_1\ : in STD_LOGIC;
    \gen_rd[7].rd_data_rise_wl_r_reg[7]_2\ : in STD_LOGIC;
    \gen_rd[7].rd_data_rise_wl_r_reg[7]_3\ : in STD_LOGIC;
    \gen_rd[7].rd_data_rise_wl_r_reg[7]_4\ : in STD_LOGIC;
    \gen_rd[7].rd_data_rise_wl_r_reg[7]_5\ : in STD_LOGIC;
    \gen_rd[7].rd_data_rise_wl_r_reg[7]_6\ : in STD_LOGIC;
    \pi_dqs_found_lanes_r1_reg[0]_1\ : in STD_LOGIC_VECTOR ( 5 downto 0 );
    \rdlvl_cpt_tap_cnt_reg[5]\ : in STD_LOGIC_VECTOR ( 5 downto 0 );
    \rdlvl_cpt_tap_cnt_reg[5]_0\ : in STD_LOGIC_VECTOR ( 5 downto 0 );
    \data_offset_1_i1_reg[0]\ : in STD_LOGIC;
    \data_offset_1_i1_reg[1]\ : in STD_LOGIC;
    \data_offset_1_i1_reg[2]\ : in STD_LOGIC;
    mc_data_offset_1 : in STD_LOGIC_VECTOR ( 0 to 0 );
    \data_offset_1_i1_reg[4]\ : in STD_LOGIC;
    \data_offset_1_i1_reg[5]\ : in STD_LOGIC;
    \data_offset_2_i1_reg[0]\ : in STD_LOGIC;
    \data_offset_2_i1_reg[1]\ : in STD_LOGIC;
    \data_offset_2_i1_reg[2]\ : in STD_LOGIC;
    mc_data_offset_2 : in STD_LOGIC_VECTOR ( 0 to 0 );
    \data_offset_2_i1_reg[4]\ : in STD_LOGIC;
    \data_offset_2_i1_reg[5]\ : in STD_LOGIC;
    mc_cmd : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \phy_ctl_wd_i1_reg[17]\ : in STD_LOGIC;
    \phy_ctl_wd_i1_reg[18]\ : in STD_LOGIC;
    \phy_ctl_wd_i1_reg[19]\ : in STD_LOGIC;
    mc_data_offset : in STD_LOGIC_VECTOR ( 0 to 0 );
    \phy_ctl_wd_i1_reg[21]\ : in STD_LOGIC;
    \phy_ctl_wd_i1_reg[22]\ : in STD_LOGIC;
    mc_wrdata_en : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of mig_mig_7series_v4_2_ddr_calib_top : entity is "mig_7series_v4_2_ddr_calib_top";
end mig_mig_7series_v4_2_ddr_calib_top;

architecture STRUCTURE of mig_mig_7series_v4_2_ddr_calib_top is
  signal calib_complete : STD_LOGIC;
  signal calib_in_common : STD_LOGIC;
  signal calib_in_common4_out : STD_LOGIC;
  signal \^calib_sel\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \calib_sel1__1\ : STD_LOGIC;
  signal \calib_sel[1]_i_3_n_0\ : STD_LOGIC;
  signal calib_zero_inputs : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal ck_addr_cmd_delay_done : STD_LOGIC;
  signal ck_po_stg2_f_en : STD_LOGIC;
  signal ck_po_stg2_f_indec : STD_LOGIC;
  signal cmd_delay_start0 : STD_LOGIC;
  signal cmd_po_en_stg2_f : STD_LOGIC;
  signal complex_act_start : STD_LOGIC;
  signal complex_ocal_reset_rd_addr : STD_LOGIC;
  signal complex_pi_incdec_done : STD_LOGIC;
  signal ctl_lane_cnt : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal ctl_lane_sel : STD_LOGIC;
  signal \ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_1\ : STD_LOGIC;
  signal \ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_11\ : STD_LOGIC;
  signal \ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_12\ : STD_LOGIC;
  signal \ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_13\ : STD_LOGIC;
  signal \ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_14\ : STD_LOGIC;
  signal \ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_15\ : STD_LOGIC;
  signal \ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_16\ : STD_LOGIC;
  signal \ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_17\ : STD_LOGIC;
  signal \ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_18\ : STD_LOGIC;
  signal \ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_19\ : STD_LOGIC;
  signal \ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_2\ : STD_LOGIC;
  signal \ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_20\ : STD_LOGIC;
  signal \ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_22\ : STD_LOGIC;
  signal \ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_23\ : STD_LOGIC;
  signal \ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_25\ : STD_LOGIC;
  signal \ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_26\ : STD_LOGIC;
  signal \ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_27\ : STD_LOGIC;
  signal \ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_28\ : STD_LOGIC;
  signal \ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_29\ : STD_LOGIC;
  signal \ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_7\ : STD_LOGIC;
  attribute MAX_FANOUT : string;
  attribute MAX_FANOUT of \ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_7\ : signal is "100";
  attribute RTL_MAX_FANOUT : string;
  attribute RTL_MAX_FANOUT of \ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_7\ : signal is "found";
  signal \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_10\ : STD_LOGIC;
  signal \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_14\ : STD_LOGIC;
  signal \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_15\ : STD_LOGIC;
  signal \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_19\ : STD_LOGIC;
  signal \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_20\ : STD_LOGIC;
  signal \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_22\ : STD_LOGIC;
  signal \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_23\ : STD_LOGIC;
  signal \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_24\ : STD_LOGIC;
  signal \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_25\ : STD_LOGIC;
  signal \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_26\ : STD_LOGIC;
  signal \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_27\ : STD_LOGIC;
  signal \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_28\ : STD_LOGIC;
  signal \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_30\ : STD_LOGIC;
  signal ddr_phy_tempmon_0_n_2 : STD_LOGIC;
  signal ddr_phy_tempmon_0_n_3 : STD_LOGIC;
  signal ddr_phy_tempmon_0_n_4 : STD_LOGIC;
  signal ddr_phy_tempmon_0_n_5 : STD_LOGIC;
  signal ddr_phy_tempmon_0_n_6 : STD_LOGIC;
  signal delaydec_cnt_r10_in : STD_LOGIC;
  signal detect_pi_found_dqs : STD_LOGIC;
  signal done_dqs_dec238_out : STD_LOGIC;
  signal done_dqs_tap_inc : STD_LOGIC;
  signal dqs_count_r : STD_LOGIC_VECTOR ( 3 to 3 );
  signal dqs_found_prech_req : STD_LOGIC;
  signal dqs_po_dec_done : STD_LOGIC;
  signal dqs_po_en_stg2_f : STD_LOGIC;
  signal \dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_2\ : STD_LOGIC;
  signal \dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_28\ : STD_LOGIC;
  signal \dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_29\ : STD_LOGIC;
  signal \dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_30\ : STD_LOGIC;
  signal \dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_34\ : STD_LOGIC;
  signal \dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_35\ : STD_LOGIC;
  signal \dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_36\ : STD_LOGIC;
  signal \dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_37\ : STD_LOGIC;
  signal \dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_38\ : STD_LOGIC;
  signal \dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_39\ : STD_LOGIC;
  signal \dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_40\ : STD_LOGIC;
  signal \dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_41\ : STD_LOGIC;
  signal \dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_42\ : STD_LOGIC;
  signal \dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_43\ : STD_LOGIC;
  signal \dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_44\ : STD_LOGIC;
  signal \dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_45\ : STD_LOGIC;
  signal \dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_46\ : STD_LOGIC;
  signal \dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_47\ : STD_LOGIC;
  signal \dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_48\ : STD_LOGIC;
  signal \dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_49\ : STD_LOGIC;
  signal \dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_50\ : STD_LOGIC;
  signal \dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_51\ : STD_LOGIC;
  signal \dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_52\ : STD_LOGIC;
  signal \dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_53\ : STD_LOGIC;
  signal \dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_54\ : STD_LOGIC;
  signal \dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_56\ : STD_LOGIC;
  signal \dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_57\ : STD_LOGIC;
  signal \dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_58\ : STD_LOGIC;
  signal \dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_59\ : STD_LOGIC;
  signal \dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_61\ : STD_LOGIC;
  signal \dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_62\ : STD_LOGIC;
  signal first_rdlvl_pat_r : STD_LOGIC;
  signal first_wrcal_pat_r : STD_LOGIC;
  signal \gen_byte_sel_div2.byte_sel_cnt_reg_n_0_[0]\ : STD_LOGIC;
  signal \gen_byte_sel_div2.byte_sel_cnt_reg_n_0_[1]\ : STD_LOGIC;
  signal \gen_byte_sel_div2.byte_sel_cnt_reg_n_0_[2]\ : STD_LOGIC;
  signal \gen_byte_sel_div2.byte_sel_cnt_reg_n_0_[3]\ : STD_LOGIC;
  signal \gen_byte_sel_div2.ctl_lane_sel_reg_n_0_[0]\ : STD_LOGIC;
  signal \gen_byte_sel_div2.ctl_lane_sel_reg_n_0_[1]\ : STD_LOGIC;
  signal \gen_byte_sel_div2.ctl_lane_sel_reg_n_0_[2]\ : STD_LOGIC;
  signal idelay_ce : STD_LOGIC;
  signal idelay_ce_int : STD_LOGIC;
  signal idelay_ce_r1 : STD_LOGIC;
  signal idelay_inc_int : STD_LOGIC;
  signal idelay_inc_r1 : STD_LOGIC;
  signal \^init_calib_complete_reg_rep__0_0\ : STD_LOGIC;
  signal \init_calib_complete_reg_rep__10_n_0\ : STD_LOGIC;
  attribute MAX_FANOUT of \init_calib_complete_reg_rep__10_n_0\ : signal is "50";
  attribute RTL_MAX_FANOUT of \init_calib_complete_reg_rep__10_n_0\ : signal is "found";
  attribute syn_maxfan : string;
  attribute syn_maxfan of \init_calib_complete_reg_rep__10_n_0\ : signal is "10";
  signal \^init_calib_complete_reg_rep__11_0\ : STD_LOGIC;
  signal \^init_calib_complete_reg_rep__12_0\ : STD_LOGIC;
  signal \init_calib_complete_reg_rep__13_n_0\ : STD_LOGIC;
  attribute MAX_FANOUT of \init_calib_complete_reg_rep__13_n_0\ : signal is "50";
  attribute RTL_MAX_FANOUT of \init_calib_complete_reg_rep__13_n_0\ : signal is "found";
  attribute syn_maxfan of \init_calib_complete_reg_rep__13_n_0\ : signal is "10";
  signal \init_calib_complete_reg_rep__14_n_0\ : STD_LOGIC;
  attribute MAX_FANOUT of \init_calib_complete_reg_rep__14_n_0\ : signal is "50";
  attribute RTL_MAX_FANOUT of \init_calib_complete_reg_rep__14_n_0\ : signal is "found";
  attribute syn_maxfan of \init_calib_complete_reg_rep__14_n_0\ : signal is "10";
  signal \init_calib_complete_reg_rep__15_n_0\ : STD_LOGIC;
  attribute MAX_FANOUT of \init_calib_complete_reg_rep__15_n_0\ : signal is "50";
  attribute RTL_MAX_FANOUT of \init_calib_complete_reg_rep__15_n_0\ : signal is "found";
  attribute syn_maxfan of \init_calib_complete_reg_rep__15_n_0\ : signal is "10";
  signal \init_calib_complete_reg_rep__16_n_0\ : STD_LOGIC;
  attribute MAX_FANOUT of \init_calib_complete_reg_rep__16_n_0\ : signal is "50";
  attribute RTL_MAX_FANOUT of \init_calib_complete_reg_rep__16_n_0\ : signal is "found";
  attribute syn_maxfan of \init_calib_complete_reg_rep__16_n_0\ : signal is "10";
  signal \init_calib_complete_reg_rep__17_n_0\ : STD_LOGIC;
  attribute MAX_FANOUT of \init_calib_complete_reg_rep__17_n_0\ : signal is "50";
  attribute RTL_MAX_FANOUT of \init_calib_complete_reg_rep__17_n_0\ : signal is "found";
  attribute syn_maxfan of \init_calib_complete_reg_rep__17_n_0\ : signal is "10";
  signal \init_calib_complete_reg_rep__18_n_0\ : STD_LOGIC;
  attribute MAX_FANOUT of \init_calib_complete_reg_rep__18_n_0\ : signal is "50";
  attribute RTL_MAX_FANOUT of \init_calib_complete_reg_rep__18_n_0\ : signal is "found";
  attribute syn_maxfan of \init_calib_complete_reg_rep__18_n_0\ : signal is "10";
  signal \init_calib_complete_reg_rep__19_n_0\ : STD_LOGIC;
  attribute MAX_FANOUT of \init_calib_complete_reg_rep__19_n_0\ : signal is "50";
  attribute RTL_MAX_FANOUT of \init_calib_complete_reg_rep__19_n_0\ : signal is "found";
  attribute syn_maxfan of \init_calib_complete_reg_rep__19_n_0\ : signal is "10";
  signal \init_calib_complete_reg_rep__1_n_0\ : STD_LOGIC;
  attribute MAX_FANOUT of \init_calib_complete_reg_rep__1_n_0\ : signal is "50";
  attribute RTL_MAX_FANOUT of \init_calib_complete_reg_rep__1_n_0\ : signal is "found";
  attribute syn_maxfan of \init_calib_complete_reg_rep__1_n_0\ : signal is "10";
  signal \init_calib_complete_reg_rep__20_n_0\ : STD_LOGIC;
  attribute MAX_FANOUT of \init_calib_complete_reg_rep__20_n_0\ : signal is "50";
  attribute RTL_MAX_FANOUT of \init_calib_complete_reg_rep__20_n_0\ : signal is "found";
  attribute syn_maxfan of \init_calib_complete_reg_rep__20_n_0\ : signal is "10";
  signal \init_calib_complete_reg_rep__21_n_0\ : STD_LOGIC;
  attribute MAX_FANOUT of \init_calib_complete_reg_rep__21_n_0\ : signal is "50";
  attribute RTL_MAX_FANOUT of \init_calib_complete_reg_rep__21_n_0\ : signal is "found";
  attribute syn_maxfan of \init_calib_complete_reg_rep__21_n_0\ : signal is "10";
  signal \init_calib_complete_reg_rep__22_n_0\ : STD_LOGIC;
  attribute MAX_FANOUT of \init_calib_complete_reg_rep__22_n_0\ : signal is "50";
  attribute RTL_MAX_FANOUT of \init_calib_complete_reg_rep__22_n_0\ : signal is "found";
  attribute syn_maxfan of \init_calib_complete_reg_rep__22_n_0\ : signal is "10";
  signal \init_calib_complete_reg_rep__23_n_0\ : STD_LOGIC;
  attribute MAX_FANOUT of \init_calib_complete_reg_rep__23_n_0\ : signal is "50";
  attribute RTL_MAX_FANOUT of \init_calib_complete_reg_rep__23_n_0\ : signal is "found";
  attribute syn_maxfan of \init_calib_complete_reg_rep__23_n_0\ : signal is "10";
  signal \^init_calib_complete_reg_rep__24_0\ : STD_LOGIC;
  signal \^init_calib_complete_reg_rep__25_0\ : STD_LOGIC;
  signal \^init_calib_complete_reg_rep__26_0\ : STD_LOGIC;
  signal \init_calib_complete_reg_rep__2_n_0\ : STD_LOGIC;
  attribute MAX_FANOUT of \init_calib_complete_reg_rep__2_n_0\ : signal is "50";
  attribute RTL_MAX_FANOUT of \init_calib_complete_reg_rep__2_n_0\ : signal is "found";
  attribute syn_maxfan of \init_calib_complete_reg_rep__2_n_0\ : signal is "10";
  signal \init_calib_complete_reg_rep__3_n_0\ : STD_LOGIC;
  attribute MAX_FANOUT of \init_calib_complete_reg_rep__3_n_0\ : signal is "50";
  attribute RTL_MAX_FANOUT of \init_calib_complete_reg_rep__3_n_0\ : signal is "found";
  attribute syn_maxfan of \init_calib_complete_reg_rep__3_n_0\ : signal is "10";
  signal \init_calib_complete_reg_rep__4_n_0\ : STD_LOGIC;
  attribute MAX_FANOUT of \init_calib_complete_reg_rep__4_n_0\ : signal is "50";
  attribute RTL_MAX_FANOUT of \init_calib_complete_reg_rep__4_n_0\ : signal is "found";
  attribute syn_maxfan of \init_calib_complete_reg_rep__4_n_0\ : signal is "10";
  signal \init_calib_complete_reg_rep__5_n_0\ : STD_LOGIC;
  attribute MAX_FANOUT of \init_calib_complete_reg_rep__5_n_0\ : signal is "50";
  attribute RTL_MAX_FANOUT of \init_calib_complete_reg_rep__5_n_0\ : signal is "found";
  attribute syn_maxfan of \init_calib_complete_reg_rep__5_n_0\ : signal is "10";
  signal \init_calib_complete_reg_rep__6_n_0\ : STD_LOGIC;
  attribute MAX_FANOUT of \init_calib_complete_reg_rep__6_n_0\ : signal is "50";
  attribute RTL_MAX_FANOUT of \init_calib_complete_reg_rep__6_n_0\ : signal is "found";
  attribute syn_maxfan of \init_calib_complete_reg_rep__6_n_0\ : signal is "10";
  signal \init_calib_complete_reg_rep__7_n_0\ : STD_LOGIC;
  attribute MAX_FANOUT of \init_calib_complete_reg_rep__7_n_0\ : signal is "50";
  attribute RTL_MAX_FANOUT of \init_calib_complete_reg_rep__7_n_0\ : signal is "found";
  attribute syn_maxfan of \init_calib_complete_reg_rep__7_n_0\ : signal is "10";
  signal \init_calib_complete_reg_rep__8_n_0\ : STD_LOGIC;
  attribute MAX_FANOUT of \init_calib_complete_reg_rep__8_n_0\ : signal is "50";
  attribute RTL_MAX_FANOUT of \init_calib_complete_reg_rep__8_n_0\ : signal is "found";
  attribute syn_maxfan of \init_calib_complete_reg_rep__8_n_0\ : signal is "10";
  signal \init_calib_complete_reg_rep__9_n_0\ : STD_LOGIC;
  attribute MAX_FANOUT of \init_calib_complete_reg_rep__9_n_0\ : signal is "50";
  attribute RTL_MAX_FANOUT of \init_calib_complete_reg_rep__9_n_0\ : signal is "found";
  attribute syn_maxfan of \init_calib_complete_reg_rep__9_n_0\ : signal is "10";
  signal init_dqsfound_done_r2 : STD_LOGIC;
  signal \mb_wrlvl_inst.u_ddr_phy_ck_addr_cmd_delay_n_7\ : STD_LOGIC;
  signal \mb_wrlvl_inst.u_ddr_phy_wrlvl_n_10\ : STD_LOGIC;
  signal \mb_wrlvl_inst.u_ddr_phy_wrlvl_n_44\ : STD_LOGIC;
  signal \mb_wrlvl_inst.u_ddr_phy_wrlvl_n_45\ : STD_LOGIC;
  signal \mb_wrlvl_inst.u_ddr_phy_wrlvl_n_46\ : STD_LOGIC;
  signal \mb_wrlvl_inst.u_ddr_phy_wrlvl_n_47\ : STD_LOGIC;
  signal \mb_wrlvl_inst.u_ddr_phy_wrlvl_n_48\ : STD_LOGIC;
  signal \mb_wrlvl_inst.u_ddr_phy_wrlvl_n_5\ : STD_LOGIC;
  signal \mb_wrlvl_inst.u_ddr_phy_wrlvl_n_50\ : STD_LOGIC;
  signal mux_rd_valid_r0 : STD_LOGIC;
  signal num_samples_done_r : STD_LOGIC;
  signal p_1_in : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal p_1_in_0 : STD_LOGIC;
  signal \phy_if_reset0__0\ : STD_LOGIC;
  signal phy_if_reset_w : STD_LOGIC;
  signal pi_calib_done : STD_LOGIC;
  signal pi_dqs_found_done_r1 : STD_LOGIC;
  signal pi_dqs_found_rank_done : STD_LOGIC;
  signal pi_fine_dly_dec_done : STD_LOGIC;
  signal po_enstg2_f : STD_LOGIC_VECTOR ( 2 to 2 );
  signal po_stg2_wrcal_cnt : STD_LOGIC_VECTOR ( 3 to 3 );
  signal \^po_stg2_wrcal_cnt_reg[2]\ : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal prbs_last_byte_done : STD_LOGIC;
  signal prbs_out : STD_LOGIC_VECTOR ( 511 downto 56 );
  signal prbs_pi_stg2_f_en : STD_LOGIC;
  signal prbs_pi_stg2_f_incdec : STD_LOGIC;
  signal prbs_rdlvl_done_pulse0 : STD_LOGIC;
  signal prbs_rdlvl_done_r1 : STD_LOGIC;
  signal prbs_rdlvl_start_r : STD_LOGIC;
  signal prech_done : STD_LOGIC;
  signal prech_req : STD_LOGIC;
  signal rd_active_r : STD_LOGIC;
  signal rd_data_offset_ranks_0 : STD_LOGIC_VECTOR ( 3 to 3 );
  signal rd_data_offset_ranks_1 : STD_LOGIC_VECTOR ( 3 to 3 );
  signal rd_data_offset_ranks_2 : STD_LOGIC_VECTOR ( 3 to 3 );
  signal rdlvl_last_byte_done : STD_LOGIC;
  signal rdlvl_pi_incdec : STD_LOGIC;
  signal rdlvl_pi_stg2_f_en : STD_LOGIC;
  signal rdlvl_pi_stg2_f_incdec : STD_LOGIC;
  signal rdlvl_prech_req : STD_LOGIC;
  signal rdlvl_stg1_done_r1 : STD_LOGIC;
  signal rdlvl_stg1_rank_done : STD_LOGIC;
  signal \^rdlvl_stg1_start_reg\ : STD_LOGIC;
  signal reset_if : STD_LOGIC;
  signal reset_if_r8_reg_srl8_n_0 : STD_LOGIC;
  signal reset_if_r9 : STD_LOGIC;
  signal reset_rd_addr : STD_LOGIC;
  signal reset_rd_addr0 : STD_LOGIC;
  signal samples_cnt_r : STD_LOGIC;
  signal sel : STD_LOGIC;
  signal stg1_wr_done : STD_LOGIC;
  signal tempmon_pi_f_en_r : STD_LOGIC;
  signal tempmon_pi_f_inc : STD_LOGIC;
  signal tempmon_pi_f_inc_r : STD_LOGIC;
  signal tempmon_sel_pi_incdec : STD_LOGIC;
  signal u_ddr_phy_init_n_13 : STD_LOGIC;
  signal u_ddr_phy_init_n_15 : STD_LOGIC;
  signal u_ddr_phy_init_n_22 : STD_LOGIC;
  signal u_ddr_phy_init_n_23 : STD_LOGIC;
  signal u_ddr_phy_init_n_24 : STD_LOGIC;
  signal u_ddr_phy_init_n_25 : STD_LOGIC;
  signal u_ddr_phy_init_n_26 : STD_LOGIC;
  signal u_ddr_phy_init_n_27 : STD_LOGIC;
  signal u_ddr_phy_init_n_28 : STD_LOGIC;
  signal u_ddr_phy_init_n_29 : STD_LOGIC;
  signal u_ddr_phy_init_n_3 : STD_LOGIC;
  signal u_ddr_phy_init_n_677 : STD_LOGIC;
  signal u_ddr_phy_init_n_679 : STD_LOGIC;
  signal u_ddr_phy_init_n_680 : STD_LOGIC;
  signal u_ddr_phy_init_n_683 : STD_LOGIC;
  signal u_ddr_phy_init_n_684 : STD_LOGIC;
  signal u_ddr_phy_init_n_686 : STD_LOGIC;
  signal u_ddr_phy_init_n_687 : STD_LOGIC;
  signal u_ddr_phy_init_n_688 : STD_LOGIC;
  signal u_ddr_phy_init_n_689 : STD_LOGIC;
  signal u_ddr_phy_init_n_699 : STD_LOGIC;
  signal u_ddr_phy_init_n_700 : STD_LOGIC;
  signal u_ddr_phy_init_n_701 : STD_LOGIC;
  signal u_ddr_phy_wrcal_n_22 : STD_LOGIC;
  signal u_ddr_phy_wrcal_n_23 : STD_LOGIC;
  signal u_ddr_phy_wrcal_n_24 : STD_LOGIC;
  signal u_ddr_phy_wrcal_n_25 : STD_LOGIC;
  signal u_ddr_phy_wrcal_n_26 : STD_LOGIC;
  signal u_ddr_phy_wrcal_n_27 : STD_LOGIC;
  signal u_ddr_phy_wrcal_n_28 : STD_LOGIC;
  signal u_ddr_phy_wrcal_n_29 : STD_LOGIC;
  signal u_ddr_phy_wrcal_n_3 : STD_LOGIC;
  signal u_ddr_phy_wrcal_n_30 : STD_LOGIC;
  signal u_ddr_phy_wrcal_n_31 : STD_LOGIC;
  signal u_ddr_phy_wrcal_n_32 : STD_LOGIC;
  signal u_ddr_phy_wrcal_n_33 : STD_LOGIC;
  signal u_ddr_phy_wrcal_n_34 : STD_LOGIC;
  signal u_ddr_phy_wrcal_n_35 : STD_LOGIC;
  signal u_ddr_phy_wrcal_n_36 : STD_LOGIC;
  signal u_ddr_phy_wrcal_n_37 : STD_LOGIC;
  signal u_ddr_phy_wrcal_n_38 : STD_LOGIC;
  signal u_ddr_phy_wrcal_n_39 : STD_LOGIC;
  signal u_ddr_phy_wrcal_n_4 : STD_LOGIC;
  signal u_ddr_phy_wrcal_n_40 : STD_LOGIC;
  signal u_ddr_phy_wrcal_n_6 : STD_LOGIC;
  signal u_ddr_phy_wrcal_n_8 : STD_LOGIC;
  signal u_ddr_prbs_gen_n_0 : STD_LOGIC;
  signal u_ddr_prbs_gen_n_1 : STD_LOGIC;
  signal u_ddr_prbs_gen_n_10 : STD_LOGIC;
  signal u_ddr_prbs_gen_n_11 : STD_LOGIC;
  signal u_ddr_prbs_gen_n_12 : STD_LOGIC;
  signal u_ddr_prbs_gen_n_13 : STD_LOGIC;
  signal u_ddr_prbs_gen_n_14 : STD_LOGIC;
  signal u_ddr_prbs_gen_n_15 : STD_LOGIC;
  signal u_ddr_prbs_gen_n_16 : STD_LOGIC;
  signal u_ddr_prbs_gen_n_17 : STD_LOGIC;
  signal u_ddr_prbs_gen_n_18 : STD_LOGIC;
  signal u_ddr_prbs_gen_n_19 : STD_LOGIC;
  signal u_ddr_prbs_gen_n_2 : STD_LOGIC;
  signal u_ddr_prbs_gen_n_20 : STD_LOGIC;
  signal u_ddr_prbs_gen_n_21 : STD_LOGIC;
  signal u_ddr_prbs_gen_n_22 : STD_LOGIC;
  signal u_ddr_prbs_gen_n_23 : STD_LOGIC;
  signal u_ddr_prbs_gen_n_24 : STD_LOGIC;
  signal u_ddr_prbs_gen_n_25 : STD_LOGIC;
  signal u_ddr_prbs_gen_n_26 : STD_LOGIC;
  signal u_ddr_prbs_gen_n_27 : STD_LOGIC;
  signal u_ddr_prbs_gen_n_28 : STD_LOGIC;
  signal u_ddr_prbs_gen_n_29 : STD_LOGIC;
  signal u_ddr_prbs_gen_n_3 : STD_LOGIC;
  signal u_ddr_prbs_gen_n_30 : STD_LOGIC;
  signal u_ddr_prbs_gen_n_31 : STD_LOGIC;
  signal u_ddr_prbs_gen_n_32 : STD_LOGIC;
  signal u_ddr_prbs_gen_n_33 : STD_LOGIC;
  signal u_ddr_prbs_gen_n_34 : STD_LOGIC;
  signal u_ddr_prbs_gen_n_35 : STD_LOGIC;
  signal u_ddr_prbs_gen_n_36 : STD_LOGIC;
  signal u_ddr_prbs_gen_n_37 : STD_LOGIC;
  signal u_ddr_prbs_gen_n_38 : STD_LOGIC;
  signal u_ddr_prbs_gen_n_39 : STD_LOGIC;
  signal u_ddr_prbs_gen_n_4 : STD_LOGIC;
  signal u_ddr_prbs_gen_n_40 : STD_LOGIC;
  signal u_ddr_prbs_gen_n_41 : STD_LOGIC;
  signal u_ddr_prbs_gen_n_42 : STD_LOGIC;
  signal u_ddr_prbs_gen_n_43 : STD_LOGIC;
  signal u_ddr_prbs_gen_n_44 : STD_LOGIC;
  signal u_ddr_prbs_gen_n_45 : STD_LOGIC;
  signal u_ddr_prbs_gen_n_5 : STD_LOGIC;
  signal u_ddr_prbs_gen_n_6 : STD_LOGIC;
  signal u_ddr_prbs_gen_n_7 : STD_LOGIC;
  signal u_ddr_prbs_gen_n_8 : STD_LOGIC;
  signal u_ddr_prbs_gen_n_9 : STD_LOGIC;
  signal wl_sm_start : STD_LOGIC;
  signal \wl_state_r__0\ : STD_LOGIC_VECTOR ( 4 downto 3 );
  signal wr_level_done_r5 : STD_LOGIC;
  signal wrcal_prech_req : STD_LOGIC;
  signal wrcal_rd_wait : STD_LOGIC;
  signal wrcal_resume_w : STD_LOGIC;
  signal wrcal_sanity_chk : STD_LOGIC;
  signal wrlvl_byte_done : STD_LOGIC;
  signal wrlvl_byte_redo : STD_LOGIC;
  signal wrlvl_byte_redo_r : STD_LOGIC;
  signal wrlvl_done_r1 : STD_LOGIC;
  signal wrlvl_final_if_rst : STD_LOGIC;
  signal wrlvl_rank_done : STD_LOGIC;
  attribute syn_maxfan of \calib_sel_reg[0]\ : label is "10";
  attribute syn_maxfan of \calib_sel_reg[1]\ : label is "10";
  attribute syn_maxfan of \calib_sel_reg[3]\ : label is "10";
  attribute syn_maxfan of \calib_sel_reg[4]\ : label is "10";
  attribute syn_maxfan of \calib_zero_inputs_reg[0]\ : label is "10";
  attribute syn_maxfan of \calib_zero_inputs_reg[1]\ : label is "10";
  attribute syn_maxfan of \calib_zero_inputs_reg[2]\ : label is "10";
  attribute syn_maxfan of \gen_byte_sel_div2.calib_in_common_reg\ : label is "10";
  attribute syn_maxfan of idelay_inc_r2_reg : label is "30";
  attribute ORIG_CELL_NAME : string;
  attribute ORIG_CELL_NAME of init_calib_complete_reg : label is "init_calib_complete_reg";
  attribute IS_FANOUT_CONSTRAINED : integer;
  attribute IS_FANOUT_CONSTRAINED of init_calib_complete_reg_rep : label is 1;
  attribute ORIG_CELL_NAME of init_calib_complete_reg_rep : label is "init_calib_complete_reg";
  attribute IS_FANOUT_CONSTRAINED of \init_calib_complete_reg_rep__0\ : label is 1;
  attribute ORIG_CELL_NAME of \init_calib_complete_reg_rep__0\ : label is "init_calib_complete_reg";
  attribute IS_FANOUT_CONSTRAINED of \init_calib_complete_reg_rep__1\ : label is 1;
  attribute ORIG_CELL_NAME of \init_calib_complete_reg_rep__1\ : label is "init_calib_complete_reg";
  attribute RTL_MAX_FANOUT of \init_calib_complete_reg_rep__1\ : label is "found";
  attribute syn_maxfan of \init_calib_complete_reg_rep__1\ : label is "10";
  attribute IS_FANOUT_CONSTRAINED of \init_calib_complete_reg_rep__10\ : label is 1;
  attribute ORIG_CELL_NAME of \init_calib_complete_reg_rep__10\ : label is "init_calib_complete_reg";
  attribute RTL_MAX_FANOUT of \init_calib_complete_reg_rep__10\ : label is "found";
  attribute syn_maxfan of \init_calib_complete_reg_rep__10\ : label is "10";
  attribute IS_FANOUT_CONSTRAINED of \init_calib_complete_reg_rep__11\ : label is 1;
  attribute ORIG_CELL_NAME of \init_calib_complete_reg_rep__11\ : label is "init_calib_complete_reg";
  attribute IS_FANOUT_CONSTRAINED of \init_calib_complete_reg_rep__12\ : label is 1;
  attribute ORIG_CELL_NAME of \init_calib_complete_reg_rep__12\ : label is "init_calib_complete_reg";
  attribute IS_FANOUT_CONSTRAINED of \init_calib_complete_reg_rep__13\ : label is 1;
  attribute ORIG_CELL_NAME of \init_calib_complete_reg_rep__13\ : label is "init_calib_complete_reg";
  attribute RTL_MAX_FANOUT of \init_calib_complete_reg_rep__13\ : label is "found";
  attribute syn_maxfan of \init_calib_complete_reg_rep__13\ : label is "10";
  attribute IS_FANOUT_CONSTRAINED of \init_calib_complete_reg_rep__14\ : label is 1;
  attribute ORIG_CELL_NAME of \init_calib_complete_reg_rep__14\ : label is "init_calib_complete_reg";
  attribute RTL_MAX_FANOUT of \init_calib_complete_reg_rep__14\ : label is "found";
  attribute syn_maxfan of \init_calib_complete_reg_rep__14\ : label is "10";
  attribute IS_FANOUT_CONSTRAINED of \init_calib_complete_reg_rep__15\ : label is 1;
  attribute ORIG_CELL_NAME of \init_calib_complete_reg_rep__15\ : label is "init_calib_complete_reg";
  attribute RTL_MAX_FANOUT of \init_calib_complete_reg_rep__15\ : label is "found";
  attribute syn_maxfan of \init_calib_complete_reg_rep__15\ : label is "10";
  attribute IS_FANOUT_CONSTRAINED of \init_calib_complete_reg_rep__16\ : label is 1;
  attribute ORIG_CELL_NAME of \init_calib_complete_reg_rep__16\ : label is "init_calib_complete_reg";
  attribute RTL_MAX_FANOUT of \init_calib_complete_reg_rep__16\ : label is "found";
  attribute syn_maxfan of \init_calib_complete_reg_rep__16\ : label is "10";
  attribute IS_FANOUT_CONSTRAINED of \init_calib_complete_reg_rep__17\ : label is 1;
  attribute ORIG_CELL_NAME of \init_calib_complete_reg_rep__17\ : label is "init_calib_complete_reg";
  attribute RTL_MAX_FANOUT of \init_calib_complete_reg_rep__17\ : label is "found";
  attribute syn_maxfan of \init_calib_complete_reg_rep__17\ : label is "10";
  attribute IS_FANOUT_CONSTRAINED of \init_calib_complete_reg_rep__18\ : label is 1;
  attribute ORIG_CELL_NAME of \init_calib_complete_reg_rep__18\ : label is "init_calib_complete_reg";
  attribute RTL_MAX_FANOUT of \init_calib_complete_reg_rep__18\ : label is "found";
  attribute syn_maxfan of \init_calib_complete_reg_rep__18\ : label is "10";
  attribute IS_FANOUT_CONSTRAINED of \init_calib_complete_reg_rep__19\ : label is 1;
  attribute ORIG_CELL_NAME of \init_calib_complete_reg_rep__19\ : label is "init_calib_complete_reg";
  attribute RTL_MAX_FANOUT of \init_calib_complete_reg_rep__19\ : label is "found";
  attribute syn_maxfan of \init_calib_complete_reg_rep__19\ : label is "10";
  attribute IS_FANOUT_CONSTRAINED of \init_calib_complete_reg_rep__2\ : label is 1;
  attribute ORIG_CELL_NAME of \init_calib_complete_reg_rep__2\ : label is "init_calib_complete_reg";
  attribute RTL_MAX_FANOUT of \init_calib_complete_reg_rep__2\ : label is "found";
  attribute syn_maxfan of \init_calib_complete_reg_rep__2\ : label is "10";
  attribute IS_FANOUT_CONSTRAINED of \init_calib_complete_reg_rep__20\ : label is 1;
  attribute ORIG_CELL_NAME of \init_calib_complete_reg_rep__20\ : label is "init_calib_complete_reg";
  attribute RTL_MAX_FANOUT of \init_calib_complete_reg_rep__20\ : label is "found";
  attribute syn_maxfan of \init_calib_complete_reg_rep__20\ : label is "10";
  attribute IS_FANOUT_CONSTRAINED of \init_calib_complete_reg_rep__21\ : label is 1;
  attribute ORIG_CELL_NAME of \init_calib_complete_reg_rep__21\ : label is "init_calib_complete_reg";
  attribute RTL_MAX_FANOUT of \init_calib_complete_reg_rep__21\ : label is "found";
  attribute syn_maxfan of \init_calib_complete_reg_rep__21\ : label is "10";
  attribute IS_FANOUT_CONSTRAINED of \init_calib_complete_reg_rep__22\ : label is 1;
  attribute ORIG_CELL_NAME of \init_calib_complete_reg_rep__22\ : label is "init_calib_complete_reg";
  attribute RTL_MAX_FANOUT of \init_calib_complete_reg_rep__22\ : label is "found";
  attribute syn_maxfan of \init_calib_complete_reg_rep__22\ : label is "10";
  attribute IS_FANOUT_CONSTRAINED of \init_calib_complete_reg_rep__23\ : label is 1;
  attribute ORIG_CELL_NAME of \init_calib_complete_reg_rep__23\ : label is "init_calib_complete_reg";
  attribute RTL_MAX_FANOUT of \init_calib_complete_reg_rep__23\ : label is "found";
  attribute syn_maxfan of \init_calib_complete_reg_rep__23\ : label is "10";
  attribute IS_FANOUT_CONSTRAINED of \init_calib_complete_reg_rep__24\ : label is 1;
  attribute ORIG_CELL_NAME of \init_calib_complete_reg_rep__24\ : label is "init_calib_complete_reg";
  attribute IS_FANOUT_CONSTRAINED of \init_calib_complete_reg_rep__25\ : label is 1;
  attribute ORIG_CELL_NAME of \init_calib_complete_reg_rep__25\ : label is "init_calib_complete_reg";
  attribute IS_FANOUT_CONSTRAINED of \init_calib_complete_reg_rep__26\ : label is 1;
  attribute ORIG_CELL_NAME of \init_calib_complete_reg_rep__26\ : label is "init_calib_complete_reg";
  attribute IS_FANOUT_CONSTRAINED of \init_calib_complete_reg_rep__3\ : label is 1;
  attribute ORIG_CELL_NAME of \init_calib_complete_reg_rep__3\ : label is "init_calib_complete_reg";
  attribute RTL_MAX_FANOUT of \init_calib_complete_reg_rep__3\ : label is "found";
  attribute syn_maxfan of \init_calib_complete_reg_rep__3\ : label is "10";
  attribute IS_FANOUT_CONSTRAINED of \init_calib_complete_reg_rep__4\ : label is 1;
  attribute ORIG_CELL_NAME of \init_calib_complete_reg_rep__4\ : label is "init_calib_complete_reg";
  attribute RTL_MAX_FANOUT of \init_calib_complete_reg_rep__4\ : label is "found";
  attribute syn_maxfan of \init_calib_complete_reg_rep__4\ : label is "10";
  attribute IS_FANOUT_CONSTRAINED of \init_calib_complete_reg_rep__5\ : label is 1;
  attribute ORIG_CELL_NAME of \init_calib_complete_reg_rep__5\ : label is "init_calib_complete_reg";
  attribute RTL_MAX_FANOUT of \init_calib_complete_reg_rep__5\ : label is "found";
  attribute syn_maxfan of \init_calib_complete_reg_rep__5\ : label is "10";
  attribute IS_FANOUT_CONSTRAINED of \init_calib_complete_reg_rep__6\ : label is 1;
  attribute ORIG_CELL_NAME of \init_calib_complete_reg_rep__6\ : label is "init_calib_complete_reg";
  attribute RTL_MAX_FANOUT of \init_calib_complete_reg_rep__6\ : label is "found";
  attribute syn_maxfan of \init_calib_complete_reg_rep__6\ : label is "10";
  attribute IS_FANOUT_CONSTRAINED of \init_calib_complete_reg_rep__7\ : label is 1;
  attribute ORIG_CELL_NAME of \init_calib_complete_reg_rep__7\ : label is "init_calib_complete_reg";
  attribute RTL_MAX_FANOUT of \init_calib_complete_reg_rep__7\ : label is "found";
  attribute syn_maxfan of \init_calib_complete_reg_rep__7\ : label is "10";
  attribute IS_FANOUT_CONSTRAINED of \init_calib_complete_reg_rep__8\ : label is 1;
  attribute ORIG_CELL_NAME of \init_calib_complete_reg_rep__8\ : label is "init_calib_complete_reg";
  attribute RTL_MAX_FANOUT of \init_calib_complete_reg_rep__8\ : label is "found";
  attribute syn_maxfan of \init_calib_complete_reg_rep__8\ : label is "10";
  attribute IS_FANOUT_CONSTRAINED of \init_calib_complete_reg_rep__9\ : label is 1;
  attribute ORIG_CELL_NAME of \init_calib_complete_reg_rep__9\ : label is "init_calib_complete_reg";
  attribute RTL_MAX_FANOUT of \init_calib_complete_reg_rep__9\ : label is "found";
  attribute syn_maxfan of \init_calib_complete_reg_rep__9\ : label is "10";
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \input_[1].iserdes_dq_.idelay_dq.idelaye2_i_1\ : label is "soft_lutpair621";
  attribute SOFT_HLUTNM of \input_[1].iserdes_dq_.idelay_dq.idelaye2_i_1__0\ : label is "soft_lutpair623";
  attribute SOFT_HLUTNM of \input_[2].iserdes_dq_.idelay_dq.idelaye2_i_1\ : label is "soft_lutpair621";
  attribute SOFT_HLUTNM of \input_[2].iserdes_dq_.idelay_dq.idelaye2_i_1__0\ : label is "soft_lutpair622";
  attribute SOFT_HLUTNM of \input_[2].iserdes_dq_.idelay_dq.idelaye2_i_1__1\ : label is "soft_lutpair622";
  attribute SOFT_HLUTNM of \input_[2].iserdes_dq_.idelay_dq.idelaye2_i_1__2\ : label is "soft_lutpair623";
  attribute SOFT_HLUTNM of \input_[2].iserdes_dq_.idelay_dq.idelaye2_i_1__3\ : label is "soft_lutpair624";
  attribute SOFT_HLUTNM of \input_[2].iserdes_dq_.idelay_dq.idelaye2_i_1__4\ : label is "soft_lutpair624";
  attribute SOFT_HLUTNM of \phaser_in_gen.phaser_in_i_1\ : label is "soft_lutpair629";
  attribute SOFT_HLUTNM of \phaser_in_gen.phaser_in_i_10\ : label is "soft_lutpair646";
  attribute SOFT_HLUTNM of \phaser_in_gen.phaser_in_i_10__0\ : label is "soft_lutpair646";
  attribute SOFT_HLUTNM of \phaser_in_gen.phaser_in_i_10__1\ : label is "soft_lutpair651";
  attribute SOFT_HLUTNM of \phaser_in_gen.phaser_in_i_10__2\ : label is "soft_lutpair651";
  attribute SOFT_HLUTNM of \phaser_in_gen.phaser_in_i_10__3\ : label is "soft_lutpair633";
  attribute SOFT_HLUTNM of \phaser_in_gen.phaser_in_i_10__4\ : label is "soft_lutpair639";
  attribute SOFT_HLUTNM of \phaser_in_gen.phaser_in_i_10__5\ : label is "soft_lutpair639";
  attribute SOFT_HLUTNM of \phaser_in_gen.phaser_in_i_10__6\ : label is "soft_lutpair633";
  attribute SOFT_HLUTNM of \phaser_in_gen.phaser_in_i_11\ : label is "soft_lutpair647";
  attribute SOFT_HLUTNM of \phaser_in_gen.phaser_in_i_11__0\ : label is "soft_lutpair647";
  attribute SOFT_HLUTNM of \phaser_in_gen.phaser_in_i_11__1\ : label is "soft_lutpair650";
  attribute SOFT_HLUTNM of \phaser_in_gen.phaser_in_i_11__2\ : label is "soft_lutpair650";
  attribute SOFT_HLUTNM of \phaser_in_gen.phaser_in_i_11__3\ : label is "soft_lutpair610";
  attribute SOFT_HLUTNM of \phaser_in_gen.phaser_in_i_11__4\ : label is "soft_lutpair642";
  attribute SOFT_HLUTNM of \phaser_in_gen.phaser_in_i_11__5\ : label is "soft_lutpair642";
  attribute SOFT_HLUTNM of \phaser_in_gen.phaser_in_i_11__6\ : label is "soft_lutpair610";
  attribute SOFT_HLUTNM of \phaser_in_gen.phaser_in_i_1__0\ : label is "soft_lutpair629";
  attribute SOFT_HLUTNM of \phaser_in_gen.phaser_in_i_1__1\ : label is "soft_lutpair630";
  attribute SOFT_HLUTNM of \phaser_in_gen.phaser_in_i_1__2\ : label is "soft_lutpair630";
  attribute SOFT_HLUTNM of \phaser_in_gen.phaser_in_i_1__3\ : label is "soft_lutpair631";
  attribute SOFT_HLUTNM of \phaser_in_gen.phaser_in_i_1__4\ : label is "soft_lutpair631";
  attribute SOFT_HLUTNM of \phaser_in_gen.phaser_in_i_1__5\ : label is "soft_lutpair632";
  attribute SOFT_HLUTNM of \phaser_in_gen.phaser_in_i_1__6\ : label is "soft_lutpair632";
  attribute SOFT_HLUTNM of \phaser_in_gen.phaser_in_i_2\ : label is "soft_lutpair654";
  attribute SOFT_HLUTNM of \phaser_in_gen.phaser_in_i_2__0\ : label is "soft_lutpair654";
  attribute SOFT_HLUTNM of \phaser_in_gen.phaser_in_i_2__1\ : label is "soft_lutpair657";
  attribute SOFT_HLUTNM of \phaser_in_gen.phaser_in_i_2__2\ : label is "soft_lutpair657";
  attribute SOFT_HLUTNM of \phaser_in_gen.phaser_in_i_2__3\ : label is "soft_lutpair656";
  attribute SOFT_HLUTNM of \phaser_in_gen.phaser_in_i_2__4\ : label is "soft_lutpair656";
  attribute SOFT_HLUTNM of \phaser_in_gen.phaser_in_i_2__5\ : label is "soft_lutpair658";
  attribute SOFT_HLUTNM of \phaser_in_gen.phaser_in_i_2__6\ : label is "soft_lutpair658";
  attribute SOFT_HLUTNM of \phaser_in_gen.phaser_in_i_3\ : label is "soft_lutpair612";
  attribute SOFT_HLUTNM of \phaser_in_gen.phaser_in_i_3__0\ : label is "soft_lutpair612";
  attribute SOFT_HLUTNM of \phaser_in_gen.phaser_in_i_3__1\ : label is "soft_lutpair613";
  attribute SOFT_HLUTNM of \phaser_in_gen.phaser_in_i_3__2\ : label is "soft_lutpair613";
  attribute SOFT_HLUTNM of \phaser_in_gen.phaser_in_i_3__3\ : label is "soft_lutpair614";
  attribute SOFT_HLUTNM of \phaser_in_gen.phaser_in_i_3__4\ : label is "soft_lutpair614";
  attribute SOFT_HLUTNM of \phaser_in_gen.phaser_in_i_3__5\ : label is "soft_lutpair615";
  attribute SOFT_HLUTNM of \phaser_in_gen.phaser_in_i_3__6\ : label is "soft_lutpair615";
  attribute SOFT_HLUTNM of \phaser_in_gen.phaser_in_i_4\ : label is "soft_lutpair617";
  attribute SOFT_HLUTNM of \phaser_in_gen.phaser_in_i_4__0\ : label is "soft_lutpair617";
  attribute SOFT_HLUTNM of \phaser_in_gen.phaser_in_i_4__1\ : label is "soft_lutpair618";
  attribute SOFT_HLUTNM of \phaser_in_gen.phaser_in_i_4__2\ : label is "soft_lutpair618";
  attribute SOFT_HLUTNM of \phaser_in_gen.phaser_in_i_4__3\ : label is "soft_lutpair619";
  attribute SOFT_HLUTNM of \phaser_in_gen.phaser_in_i_4__4\ : label is "soft_lutpair619";
  attribute SOFT_HLUTNM of \phaser_in_gen.phaser_in_i_4__5\ : label is "soft_lutpair620";
  attribute SOFT_HLUTNM of \phaser_in_gen.phaser_in_i_4__6\ : label is "soft_lutpair620";
  attribute SOFT_HLUTNM of \phaser_in_gen.phaser_in_i_5\ : label is "soft_lutpair625";
  attribute SOFT_HLUTNM of \phaser_in_gen.phaser_in_i_5__0\ : label is "soft_lutpair625";
  attribute SOFT_HLUTNM of \phaser_in_gen.phaser_in_i_5__1\ : label is "soft_lutpair626";
  attribute SOFT_HLUTNM of \phaser_in_gen.phaser_in_i_5__2\ : label is "soft_lutpair626";
  attribute SOFT_HLUTNM of \phaser_in_gen.phaser_in_i_5__3\ : label is "soft_lutpair627";
  attribute SOFT_HLUTNM of \phaser_in_gen.phaser_in_i_5__4\ : label is "soft_lutpair627";
  attribute SOFT_HLUTNM of \phaser_in_gen.phaser_in_i_5__5\ : label is "soft_lutpair628";
  attribute SOFT_HLUTNM of \phaser_in_gen.phaser_in_i_5__6\ : label is "soft_lutpair628";
  attribute SOFT_HLUTNM of \phaser_in_gen.phaser_in_i_6\ : label is "soft_lutpair641";
  attribute SOFT_HLUTNM of \phaser_in_gen.phaser_in_i_6__0\ : label is "soft_lutpair649";
  attribute SOFT_HLUTNM of \phaser_in_gen.phaser_in_i_6__1\ : label is "soft_lutpair641";
  attribute SOFT_HLUTNM of \phaser_in_gen.phaser_in_i_6__2\ : label is "soft_lutpair649";
  attribute SOFT_HLUTNM of \phaser_in_gen.phaser_in_i_6__3\ : label is "soft_lutpair635";
  attribute SOFT_HLUTNM of \phaser_in_gen.phaser_in_i_6__4\ : label is "soft_lutpair643";
  attribute SOFT_HLUTNM of \phaser_in_gen.phaser_in_i_6__5\ : label is "soft_lutpair635";
  attribute SOFT_HLUTNM of \phaser_in_gen.phaser_in_i_6__6\ : label is "soft_lutpair643";
  attribute SOFT_HLUTNM of \phaser_in_gen.phaser_in_i_7\ : label is "soft_lutpair634";
  attribute SOFT_HLUTNM of \phaser_in_gen.phaser_in_i_7__0\ : label is "soft_lutpair648";
  attribute SOFT_HLUTNM of \phaser_in_gen.phaser_in_i_7__1\ : label is "soft_lutpair634";
  attribute SOFT_HLUTNM of \phaser_in_gen.phaser_in_i_7__2\ : label is "soft_lutpair648";
  attribute SOFT_HLUTNM of \phaser_in_gen.phaser_in_i_7__3\ : label is "soft_lutpair611";
  attribute SOFT_HLUTNM of \phaser_in_gen.phaser_in_i_7__4\ : label is "soft_lutpair636";
  attribute SOFT_HLUTNM of \phaser_in_gen.phaser_in_i_7__5\ : label is "soft_lutpair636";
  attribute SOFT_HLUTNM of \phaser_in_gen.phaser_in_i_7__6\ : label is "soft_lutpair611";
  attribute SOFT_HLUTNM of \phaser_in_gen.phaser_in_i_8\ : label is "soft_lutpair644";
  attribute SOFT_HLUTNM of \phaser_in_gen.phaser_in_i_8__0\ : label is "soft_lutpair644";
  attribute SOFT_HLUTNM of \phaser_in_gen.phaser_in_i_8__1\ : label is "soft_lutpair653";
  attribute SOFT_HLUTNM of \phaser_in_gen.phaser_in_i_8__2\ : label is "soft_lutpair653";
  attribute SOFT_HLUTNM of \phaser_in_gen.phaser_in_i_8__3\ : label is "soft_lutpair616";
  attribute SOFT_HLUTNM of \phaser_in_gen.phaser_in_i_8__4\ : label is "soft_lutpair637";
  attribute SOFT_HLUTNM of \phaser_in_gen.phaser_in_i_8__5\ : label is "soft_lutpair637";
  attribute SOFT_HLUTNM of \phaser_in_gen.phaser_in_i_8__6\ : label is "soft_lutpair616";
  attribute SOFT_HLUTNM of \phaser_in_gen.phaser_in_i_9\ : label is "soft_lutpair645";
  attribute SOFT_HLUTNM of \phaser_in_gen.phaser_in_i_9__0\ : label is "soft_lutpair645";
  attribute SOFT_HLUTNM of \phaser_in_gen.phaser_in_i_9__1\ : label is "soft_lutpair652";
  attribute SOFT_HLUTNM of \phaser_in_gen.phaser_in_i_9__2\ : label is "soft_lutpair652";
  attribute SOFT_HLUTNM of \phaser_in_gen.phaser_in_i_9__3\ : label is "soft_lutpair638";
  attribute SOFT_HLUTNM of \phaser_in_gen.phaser_in_i_9__4\ : label is "soft_lutpair640";
  attribute SOFT_HLUTNM of \phaser_in_gen.phaser_in_i_9__5\ : label is "soft_lutpair638";
  attribute SOFT_HLUTNM of \phaser_in_gen.phaser_in_i_9__6\ : label is "soft_lutpair640";
  attribute SOFT_HLUTNM of \phaser_out_i_2__7\ : label is "soft_lutpair655";
  attribute SOFT_HLUTNM of \phaser_out_i_2__8\ : label is "soft_lutpair655";
  attribute SOFT_HLUTNM of \phaser_out_i_2__9\ : label is "soft_lutpair659";
  attribute SOFT_HLUTNM of \po_counter_read_val[8]_i_1__1\ : label is "soft_lutpair659";
  attribute srl_name : string;
  attribute srl_name of reset_if_r8_reg_srl8 : label is "\u_mig_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/reset_if_r8_reg_srl8 ";
begin
  calib_sel(3 downto 0) <= \^calib_sel\(3 downto 0);
  \init_calib_complete_reg_rep__0_0\ <= \^init_calib_complete_reg_rep__0_0\;
  \init_calib_complete_reg_rep__11_0\ <= \^init_calib_complete_reg_rep__11_0\;
  \init_calib_complete_reg_rep__12_0\ <= \^init_calib_complete_reg_rep__12_0\;
  \init_calib_complete_reg_rep__24_0\ <= \^init_calib_complete_reg_rep__24_0\;
  \init_calib_complete_reg_rep__25_0\ <= \^init_calib_complete_reg_rep__25_0\;
  \init_calib_complete_reg_rep__26_0\ <= \^init_calib_complete_reg_rep__26_0\;
  \po_stg2_wrcal_cnt_reg[2]\(2 downto 0) <= \^po_stg2_wrcal_cnt_reg[2]\(2 downto 0);
  rdlvl_stg1_start_reg <= \^rdlvl_stg1_start_reg\;
\calib_sel[1]_i_3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \gen_byte_sel_div2.byte_sel_cnt_reg_n_0_[1]\,
      I1 => \gen_byte_sel_div2.byte_sel_cnt_reg_n_0_[3]\,
      O => \calib_sel[1]_i_3_n_0\
    );
\calib_sel_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \dout_o_reg[15]\,
      CE => '1',
      D => \dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_59\,
      Q => \^calib_sel\(0),
      R => ddr_phy_tempmon_0_n_5
    );
\calib_sel_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \dout_o_reg[15]\,
      CE => '1',
      D => \dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_61\,
      Q => \^calib_sel\(1),
      R => ddr_phy_tempmon_0_n_5
    );
\calib_sel_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => \dout_o_reg[15]\,
      CE => '1',
      D => ctl_lane_sel,
      Q => \^calib_sel\(2),
      R => ddr_phy_tempmon_0_n_5
    );
\calib_sel_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => \dout_o_reg[15]\,
      CE => '1',
      D => \dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_62\,
      Q => \^calib_sel\(3),
      R => ddr_phy_tempmon_0_n_5
    );
\calib_zero_inputs_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \dout_o_reg[15]\,
      CE => '1',
      D => ddr_phy_tempmon_0_n_4,
      Q => calib_zero_inputs(0),
      R => '0'
    );
\calib_zero_inputs_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \dout_o_reg[15]\,
      CE => '1',
      D => ddr_phy_tempmon_0_n_3,
      Q => calib_zero_inputs(1),
      R => '0'
    );
\calib_zero_inputs_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \dout_o_reg[15]\,
      CE => '1',
      D => ddr_phy_tempmon_0_n_2,
      Q => calib_zero_inputs(2),
      R => '0'
    );
\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl\: entity work.mig_mig_7series_v4_2_ddr_phy_prbs_rdlvl
     port map (
      D(5) => \ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_12\,
      D(4) => \ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_13\,
      D(3) => \ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_14\,
      D(2) => \ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_15\,
      D(1) => \ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_16\,
      D(0) => \ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_17\,
      E(0) => samples_cnt_r,
      Q(3) => po_stg2_wrcal_cnt(3),
      Q(2 downto 0) => \^po_stg2_wrcal_cnt_reg[2]\(2 downto 0),
      \bit_cnt_reg[7]_0\ => \dout_o_reg[15]\,
      \cmp_err_4to1.compare_err_f3_reg_0\ => \cmp_err_4to1.compare_err_f3_reg\,
      complex_act_start => complex_act_start,
      complex_ocal_reset_rd_addr => complex_ocal_reset_rd_addr,
      complex_pi_incdec_done => complex_pi_incdec_done,
      complex_victim_inc_reg_0 => \ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_1\,
      dqs_found_done_r_reg => \ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_23\,
      \gen_byte_sel_div2.byte_sel_cnt_reg[0]\ => \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_10\,
      \gen_byte_sel_div2.byte_sel_cnt_reg[0]_0\ => u_ddr_phy_wrcal_n_3,
      \gen_mux_rd[0].mux_rd_fall0_r1_reg[0]_0\ => \gen_mux_rd[0].mux_rd_fall0_r1_reg[0]\,
      \gen_mux_rd[0].mux_rd_fall1_r1_reg[0]_0\ => \gen_mux_rd[0].mux_rd_fall1_r1_reg[0]\,
      \gen_mux_rd[0].mux_rd_fall2_r1_reg[0]_0\ => \gen_mux_rd[0].mux_rd_fall2_r1_reg[0]\,
      \gen_mux_rd[0].mux_rd_fall3_r1_reg[0]_0\ => \gen_mux_rd[0].mux_rd_fall3_r1_reg[0]\,
      \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]_0\ => \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]\,
      \gen_mux_rd[0].mux_rd_rise1_r1_reg[0]_0\ => \gen_mux_rd[0].mux_rd_rise1_r1_reg[0]\,
      \gen_mux_rd[0].mux_rd_rise2_r1_reg[0]_0\ => \gen_mux_rd[0].mux_rd_rise2_r1_reg[0]\,
      \gen_mux_rd[0].mux_rd_rise3_r1_reg[0]_0\ => \gen_mux_rd[0].mux_rd_rise3_r1_reg[0]\,
      \gen_mux_rd[1].mux_rd_fall0_r1_reg[1]_0\ => \gen_mux_rd[1].mux_rd_fall0_r1_reg[1]\,
      \gen_mux_rd[1].mux_rd_fall1_r1_reg[1]_0\ => \gen_mux_rd[1].mux_rd_fall1_r1_reg[1]\,
      \gen_mux_rd[1].mux_rd_fall2_r1_reg[1]_0\ => \gen_mux_rd[1].mux_rd_fall2_r1_reg[1]\,
      \gen_mux_rd[1].mux_rd_fall3_r1_reg[1]_0\ => \gen_mux_rd[1].mux_rd_fall3_r1_reg[1]\,
      \gen_mux_rd[1].mux_rd_rise0_r1_reg[1]_0\ => \gen_mux_rd[1].mux_rd_rise0_r1_reg[1]\,
      \gen_mux_rd[1].mux_rd_rise1_r1_reg[1]_0\ => \gen_mux_rd[1].mux_rd_rise1_r1_reg[1]\,
      \gen_mux_rd[1].mux_rd_rise2_r1_reg[1]_0\ => \gen_mux_rd[1].mux_rd_rise2_r1_reg[1]\,
      \gen_mux_rd[1].mux_rd_rise3_r1_reg[1]_0\ => \gen_mux_rd[1].mux_rd_rise3_r1_reg[1]\,
      \gen_mux_rd[2].mux_rd_fall0_r1_reg[2]_0\ => \gen_mux_rd[2].mux_rd_fall0_r1_reg[2]\,
      \gen_mux_rd[2].mux_rd_fall1_r1_reg[2]_0\ => \gen_mux_rd[2].mux_rd_fall1_r1_reg[2]\,
      \gen_mux_rd[2].mux_rd_fall2_r1_reg[2]_0\ => \gen_mux_rd[2].mux_rd_fall2_r1_reg[2]\,
      \gen_mux_rd[2].mux_rd_fall3_r1_reg[2]_0\ => \gen_mux_rd[2].mux_rd_fall3_r1_reg[2]\,
      \gen_mux_rd[2].mux_rd_rise0_r1_reg[2]_0\ => \gen_mux_rd[2].mux_rd_rise0_r1_reg[2]\,
      \gen_mux_rd[2].mux_rd_rise1_r1_reg[2]_0\ => \gen_mux_rd[2].mux_rd_rise1_r1_reg[2]\,
      \gen_mux_rd[2].mux_rd_rise2_r1_reg[2]_0\ => \gen_mux_rd[2].mux_rd_rise2_r1_reg[2]\,
      \gen_mux_rd[2].mux_rd_rise3_r1_reg[2]_0\ => \gen_mux_rd[2].mux_rd_rise3_r1_reg[2]\,
      \gen_mux_rd[3].mux_rd_fall0_r1_reg[3]_0\ => \gen_mux_rd[3].mux_rd_fall0_r1_reg[3]\,
      \gen_mux_rd[3].mux_rd_fall1_r1_reg[3]_0\ => \gen_mux_rd[3].mux_rd_fall1_r1_reg[3]\,
      \gen_mux_rd[3].mux_rd_fall2_r1_reg[3]_0\ => \gen_mux_rd[3].mux_rd_fall2_r1_reg[3]\,
      \gen_mux_rd[3].mux_rd_fall3_r1_reg[3]_0\ => \gen_mux_rd[3].mux_rd_fall3_r1_reg[3]\,
      \gen_mux_rd[3].mux_rd_rise0_r1_reg[3]_0\ => \gen_mux_rd[3].mux_rd_rise0_r1_reg[3]\,
      \gen_mux_rd[3].mux_rd_rise1_r1_reg[3]_0\ => \gen_mux_rd[3].mux_rd_rise1_r1_reg[3]\,
      \gen_mux_rd[3].mux_rd_rise2_r1_reg[3]_0\ => \gen_mux_rd[3].mux_rd_rise2_r1_reg[3]\,
      \gen_mux_rd[3].mux_rd_rise3_r1_reg[3]_0\ => \gen_mux_rd[3].mux_rd_rise3_r1_reg[3]\,
      \gen_mux_rd[4].mux_rd_fall0_r1_reg[4]_0\ => \gen_mux_rd[4].mux_rd_fall0_r1_reg[4]\,
      \gen_mux_rd[4].mux_rd_fall1_r1_reg[4]_0\ => \gen_mux_rd[4].mux_rd_fall1_r1_reg[4]\,
      \gen_mux_rd[4].mux_rd_fall2_r1_reg[4]_0\ => \gen_mux_rd[4].mux_rd_fall2_r1_reg[4]\,
      \gen_mux_rd[4].mux_rd_fall3_r1_reg[4]_0\ => \gen_mux_rd[4].mux_rd_fall3_r1_reg[4]\,
      \gen_mux_rd[4].mux_rd_rise0_r1_reg[4]_0\ => \gen_mux_rd[4].mux_rd_rise0_r1_reg[4]\,
      \gen_mux_rd[4].mux_rd_rise1_r1_reg[4]_0\ => \gen_mux_rd[4].mux_rd_rise1_r1_reg[4]\,
      \gen_mux_rd[4].mux_rd_rise2_r1_reg[4]_0\ => \gen_mux_rd[4].mux_rd_rise2_r1_reg[4]\,
      \gen_mux_rd[4].mux_rd_rise3_r1_reg[4]_0\ => \gen_mux_rd[4].mux_rd_rise3_r1_reg[4]\,
      \gen_mux_rd[5].mux_rd_fall0_r1_reg[5]_0\ => \gen_mux_rd[5].mux_rd_fall0_r1_reg[5]\,
      \gen_mux_rd[5].mux_rd_fall1_r1_reg[5]_0\ => \gen_mux_rd[5].mux_rd_fall1_r1_reg[5]\,
      \gen_mux_rd[5].mux_rd_fall2_r1_reg[5]_0\ => \gen_mux_rd[5].mux_rd_fall2_r1_reg[5]\,
      \gen_mux_rd[5].mux_rd_fall3_r1_reg[5]_0\ => \gen_mux_rd[5].mux_rd_fall3_r1_reg[5]\,
      \gen_mux_rd[5].mux_rd_rise0_r1_reg[5]_0\ => \gen_mux_rd[5].mux_rd_rise0_r1_reg[5]\,
      \gen_mux_rd[5].mux_rd_rise1_r1_reg[5]_0\ => \gen_mux_rd[5].mux_rd_rise1_r1_reg[5]\,
      \gen_mux_rd[5].mux_rd_rise2_r1_reg[5]_0\ => \gen_mux_rd[5].mux_rd_rise2_r1_reg[5]\,
      \gen_mux_rd[5].mux_rd_rise3_r1_reg[5]_0\ => \gen_mux_rd[5].mux_rd_rise3_r1_reg[5]\,
      \gen_mux_rd[6].mux_rd_fall0_r1_reg[6]_0\ => \gen_mux_rd[6].mux_rd_fall0_r1_reg[6]\,
      \gen_mux_rd[6].mux_rd_fall1_r1_reg[6]_0\ => \gen_mux_rd[6].mux_rd_fall1_r1_reg[6]\,
      \gen_mux_rd[6].mux_rd_fall2_r1_reg[6]_0\ => \gen_mux_rd[6].mux_rd_fall2_r1_reg[6]\,
      \gen_mux_rd[6].mux_rd_fall3_r1_reg[6]_0\ => \gen_mux_rd[6].mux_rd_fall3_r1_reg[6]\,
      \gen_mux_rd[6].mux_rd_rise0_r1_reg[6]_0\ => \gen_mux_rd[6].mux_rd_rise0_r1_reg[6]\,
      \gen_mux_rd[6].mux_rd_rise1_r1_reg[6]_0\ => \gen_mux_rd[6].mux_rd_rise1_r1_reg[6]\,
      \gen_mux_rd[6].mux_rd_rise2_r1_reg[6]_0\ => \gen_mux_rd[6].mux_rd_rise2_r1_reg[6]\,
      \gen_mux_rd[6].mux_rd_rise3_r1_reg[6]_0\ => \gen_mux_rd[6].mux_rd_rise3_r1_reg[6]\,
      \gen_mux_rd[7].mux_rd_fall0_r1_reg[7]_0\ => \gen_mux_rd[7].mux_rd_fall0_r1_reg[7]\,
      \gen_mux_rd[7].mux_rd_fall1_r1_reg[7]_0\ => \gen_mux_rd[7].mux_rd_fall1_r1_reg[7]\,
      \gen_mux_rd[7].mux_rd_fall2_r1_reg[7]_0\ => \gen_mux_rd[7].mux_rd_fall2_r1_reg[7]\,
      \gen_mux_rd[7].mux_rd_fall3_r1_reg[7]_0\ => \gen_mux_rd[7].mux_rd_fall3_r1_reg[7]\,
      \gen_mux_rd[7].mux_rd_rise0_r1_reg[7]_0\ => \gen_mux_rd[7].mux_rd_rise0_r1_reg[7]\,
      \gen_mux_rd[7].mux_rd_rise1_r1_reg[7]_0\ => \gen_mux_rd[7].mux_rd_rise1_r1_reg[7]\,
      \gen_mux_rd[7].mux_rd_rise2_r1_reg[7]_0\ => \gen_mux_rd[7].mux_rd_rise2_r1_reg[7]\,
      \gen_mux_rd[7].mux_rd_rise3_r1_reg[7]_0\ => \gen_mux_rd[7].mux_rd_rise3_r1_reg[7]\,
      \init_state_r[0]_i_27\ => \dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_2\,
      \init_state_r[0]_i_27_0\ => u_ddr_phy_init_n_13,
      \match_flag_and_reg[7]_0\ => \en_cnt_div4.enable_wrlvl_cnt_reg[2]\,
      mux_rd_valid_r0 => mux_rd_valid_r0,
      new_cnt_dqs_r_reg_0 => E(0),
      new_cnt_dqs_r_reg_1 => u_ddr_phy_init_n_680,
      no_err_win_detected_reg_0 => po_en_stg2_f_reg,
      num_samples_done_r => num_samples_done_r,
      \prbs_dec_tap_cnt_reg[0]_0\(0) => \fine_dec_cnt_reg[5]\(0),
      \prbs_dqs_cnt_r_reg[0]_0\ => \ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_25\,
      \prbs_dqs_cnt_r_reg[0]_1\ => cal2_if_reset_reg,
      \prbs_dqs_cnt_r_reg[1]_0\ => \ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_26\,
      \prbs_dqs_cnt_r_reg[2]_0\ => \ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_27\,
      \prbs_dqs_cnt_r_reg[3]_0\ => \ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_28\,
      prbs_found_2nd_edge_r_reg_0 => first_fail_detect_reg,
      prbs_last_byte_done => prbs_last_byte_done,
      prbs_out(63 downto 56) => prbs_out(511 downto 504),
      prbs_out(55 downto 48) => prbs_out(447 downto 440),
      prbs_out(47 downto 40) => prbs_out(383 downto 376),
      prbs_out(39 downto 32) => prbs_out(319 downto 312),
      prbs_out(31 downto 24) => prbs_out(255 downto 248),
      prbs_out(23 downto 16) => prbs_out(191 downto 184),
      prbs_out(15 downto 8) => prbs_out(127 downto 120),
      prbs_out(7 downto 0) => prbs_out(63 downto 56),
      prbs_pi_stg2_f_en => prbs_pi_stg2_f_en,
      prbs_pi_stg2_f_incdec => prbs_pi_stg2_f_incdec,
      prbs_rdlvl_done_pulse0 => prbs_rdlvl_done_pulse0,
      prbs_rdlvl_done_r1 => prbs_rdlvl_done_r1,
      prbs_rdlvl_done_reg_0 => \ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_7\,
      prbs_rdlvl_done_reg_1 => \ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_22\,
      prbs_rdlvl_prech_req_reg_0 => \ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_2\,
      prbs_rdlvl_start_r => prbs_rdlvl_start_r,
      prbs_rdlvl_start_r_reg_0 => u_ddr_phy_init_n_679,
      prech_done => prech_done,
      \rd_mux_sel_r_reg[2]_0\(2 downto 0) => \rd_mux_sel_r_reg[2]_0\(2 downto 0),
      \rd_victim_sel_reg[0]_0\ => \ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_19\,
      \rd_victim_sel_reg[1]_0\ => \ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_20\,
      \rd_victim_sel_reg[2]_0\ => \ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_18\,
      \rd_victim_sel_reg[2]_1\ => \idelay_tap_cnt_r_reg[0][0][4]\,
      \rdlvl_cpt_tap_cnt_reg[5]_0\ => \^calib_sel\(2),
      \rdlvl_cpt_tap_cnt_reg[5]_1\(5 downto 0) => \rdlvl_cpt_tap_cnt_reg[5]\(5 downto 0),
      \rdlvl_cpt_tap_cnt_reg[5]_2\ => \^calib_sel\(3),
      \rdlvl_cpt_tap_cnt_reg[5]_3\(5 downto 0) => \rdlvl_cpt_tap_cnt_reg[5]_0\(5 downto 0),
      rdlvl_last_byte_done => rdlvl_last_byte_done,
      rdlvl_stg1_done_r1 => rdlvl_stg1_done_r1,
      reset_if => reset_if,
      reset_if_r9 => reset_if_r9,
      reset_if_r9_reg => \ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_29\,
      reset_if_reg => \not_empty_wait_cnt_reg[4]\,
      reset_rd_addr => reset_rd_addr,
      reset_rd_addr0 => reset_rd_addr0,
      \samples_cnt_r_reg[0]_0\ => \samples_cnt_r_reg[0]\,
      \samples_cnt_r_reg[11]_0\ => \ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_11\
    );
\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl\: entity work.mig_mig_7series_v4_2_ddr_phy_rdlvl
     port map (
      D(5) => \ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_12\,
      D(4) => \ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_13\,
      D(3) => \ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_14\,
      D(2) => \ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_15\,
      D(1) => \ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_16\,
      D(0) => \ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_17\,
      E(0) => rd_active_r,
      Q(1 downto 0) => \rd_mux_sel_r_reg[1]\(1 downto 0),
      SR(1) => \FSM_onehot_cal1_state_r_reg[7]\(0),
      SR(0) => \corse_inc_reg[6][2]\(0),
      \cal1_cnt_cpt_r_reg[0]_0\ => \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_23\,
      \cal1_cnt_cpt_r_reg[0]_1\ => \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_24\,
      \cal1_cnt_cpt_r_reg[2]_0\ => \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_15\,
      \cal1_cnt_cpt_r_reg[2]_1\ => \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_22\,
      cal1_dq_idel_ce_reg_0 => \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_25\,
      cal1_dq_idel_ce_reg_1 => \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_27\,
      cal1_dq_idel_ce_reg_2 => \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_28\,
      \cnt_shift_r_reg[0]_0\(0) => \cnt_shift_r_reg[0]\(0),
      \done_cnt_reg[2]_0\ => \idelay_tap_cnt_r_reg[0][4][4]\,
      dqs_found_prech_req => dqs_found_prech_req,
      dqs_po_dec_done => dqs_po_dec_done,
      found_second_edge_r_reg_0 => first_fail_detect_reg,
      \gen_byte_sel_div2.byte_sel_cnt_reg[0]\ => \ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_25\,
      \gen_byte_sel_div2.byte_sel_cnt_reg[0]_0\ => \mb_wrlvl_inst.u_ddr_phy_wrlvl_n_47\,
      \gen_byte_sel_div2.byte_sel_cnt_reg[1]\ => \ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_26\,
      \gen_byte_sel_div2.byte_sel_cnt_reg[1]_0\ => \mb_wrlvl_inst.u_ddr_phy_wrlvl_n_48\,
      \gen_byte_sel_div2.byte_sel_cnt_reg[2]\ => \ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_27\,
      \gen_byte_sel_div2.byte_sel_cnt_reg[2]_0\ => \mb_wrlvl_inst.u_ddr_phy_wrlvl_n_10\,
      \gen_byte_sel_div2.byte_sel_cnt_reg[3]\ => \ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_28\,
      \gen_byte_sel_div2.byte_sel_cnt_reg[3]_0\ => \mb_wrlvl_inst.u_ddr_phy_wrlvl_n_5\,
      \gen_byte_sel_div2.byte_sel_cnt_reg[3]_1\(0) => dqs_count_r(3),
      \gen_mux_rd[0].mux_rd_fall0_r_reg[0]_0\ => \gen_mux_rd[0].mux_rd_fall0_r_reg[0]\,
      \gen_mux_rd[0].mux_rd_fall1_r_reg[0]_0\ => \gen_mux_rd[0].mux_rd_fall1_r_reg[0]\,
      \gen_mux_rd[0].mux_rd_fall2_r_reg[0]_0\ => \gen_mux_rd[0].mux_rd_fall2_r_reg[0]\,
      \gen_mux_rd[0].mux_rd_fall3_r_reg[0]_0\ => \gen_mux_rd[0].mux_rd_fall3_r_reg[0]\,
      \gen_mux_rd[0].mux_rd_rise0_r_reg[0]_0\ => \gen_mux_rd[0].mux_rd_rise0_r_reg[0]\,
      \gen_mux_rd[0].mux_rd_rise1_r_reg[0]_0\ => \gen_mux_rd[0].mux_rd_rise1_r_reg[0]\,
      \gen_mux_rd[0].mux_rd_rise2_r_reg[0]_0\ => \gen_mux_rd[0].mux_rd_rise2_r_reg[0]\,
      \gen_mux_rd[0].mux_rd_rise3_r_reg[0]_0\ => \gen_mux_rd[0].mux_rd_rise3_r_reg[0]\,
      \gen_mux_rd[1].mux_rd_fall0_r_reg[1]_0\ => \gen_mux_rd[1].mux_rd_fall0_r_reg[1]\,
      \gen_mux_rd[1].mux_rd_fall1_r_reg[1]_0\ => \gen_mux_rd[1].mux_rd_fall1_r_reg[1]\,
      \gen_mux_rd[1].mux_rd_fall2_r_reg[1]_0\ => \gen_mux_rd[1].mux_rd_fall2_r_reg[1]\,
      \gen_mux_rd[1].mux_rd_fall3_r_reg[1]_0\ => \gen_mux_rd[1].mux_rd_fall3_r_reg[1]\,
      \gen_mux_rd[1].mux_rd_rise0_r_reg[1]_0\ => \gen_mux_rd[1].mux_rd_rise0_r_reg[1]\,
      \gen_mux_rd[1].mux_rd_rise1_r_reg[1]_0\ => \gen_mux_rd[1].mux_rd_rise1_r_reg[1]\,
      \gen_mux_rd[1].mux_rd_rise2_r_reg[1]_0\ => \gen_mux_rd[1].mux_rd_rise2_r_reg[1]\,
      \gen_mux_rd[1].mux_rd_rise3_r_reg[1]_0\ => \gen_mux_rd[1].mux_rd_rise3_r_reg[1]\,
      \gen_mux_rd[2].mux_rd_fall0_r_reg[2]_0\ => \gen_mux_rd[2].mux_rd_fall0_r_reg[2]\,
      \gen_mux_rd[2].mux_rd_fall1_r_reg[2]_0\ => \gen_mux_rd[2].mux_rd_fall1_r_reg[2]\,
      \gen_mux_rd[2].mux_rd_fall2_r_reg[2]_0\ => \gen_mux_rd[2].mux_rd_fall2_r_reg[2]\,
      \gen_mux_rd[2].mux_rd_fall3_r_reg[2]_0\ => \gen_mux_rd[2].mux_rd_fall3_r_reg[2]\,
      \gen_mux_rd[2].mux_rd_rise0_r_reg[2]_0\ => \gen_mux_rd[2].mux_rd_rise0_r_reg[2]\,
      \gen_mux_rd[2].mux_rd_rise1_r_reg[2]_0\ => \gen_mux_rd[2].mux_rd_rise1_r_reg[2]\,
      \gen_mux_rd[2].mux_rd_rise2_r_reg[2]_0\ => \gen_mux_rd[2].mux_rd_rise2_r_reg[2]\,
      \gen_mux_rd[2].mux_rd_rise3_r_reg[2]_0\ => \gen_mux_rd[2].mux_rd_rise3_r_reg[2]\,
      \gen_mux_rd[3].mux_rd_fall0_r_reg[3]_0\ => \gen_mux_rd[3].mux_rd_fall0_r_reg[3]\,
      \gen_mux_rd[3].mux_rd_fall1_r_reg[3]_0\ => \gen_mux_rd[3].mux_rd_fall1_r_reg[3]\,
      \gen_mux_rd[3].mux_rd_fall2_r_reg[3]_0\ => \gen_mux_rd[3].mux_rd_fall2_r_reg[3]\,
      \gen_mux_rd[3].mux_rd_fall3_r_reg[3]_0\ => \gen_mux_rd[3].mux_rd_fall3_r_reg[3]\,
      \gen_mux_rd[3].mux_rd_rise0_r_reg[3]_0\ => \gen_mux_rd[3].mux_rd_rise0_r_reg[3]\,
      \gen_mux_rd[3].mux_rd_rise1_r_reg[3]_0\ => \gen_mux_rd[3].mux_rd_rise1_r_reg[3]\,
      \gen_mux_rd[3].mux_rd_rise2_r_reg[3]_0\ => \gen_mux_rd[3].mux_rd_rise2_r_reg[3]\,
      \gen_mux_rd[3].mux_rd_rise3_r_reg[3]_0\ => \gen_mux_rd[3].mux_rd_rise3_r_reg[3]\,
      \gen_mux_rd[4].mux_rd_fall0_r_reg[4]_0\ => \gen_mux_rd[4].mux_rd_fall0_r_reg[4]\,
      \gen_mux_rd[4].mux_rd_fall1_r_reg[4]_0\ => \gen_mux_rd[4].mux_rd_fall1_r_reg[4]\,
      \gen_mux_rd[4].mux_rd_fall2_r_reg[4]_0\ => \gen_mux_rd[4].mux_rd_fall2_r_reg[4]\,
      \gen_mux_rd[4].mux_rd_fall3_r_reg[4]_0\ => \gen_mux_rd[4].mux_rd_fall3_r_reg[4]\,
      \gen_mux_rd[4].mux_rd_rise0_r_reg[4]_0\ => \gen_mux_rd[4].mux_rd_rise0_r_reg[4]\,
      \gen_mux_rd[4].mux_rd_rise1_r_reg[4]_0\ => \gen_mux_rd[4].mux_rd_rise1_r_reg[4]\,
      \gen_mux_rd[4].mux_rd_rise2_r_reg[4]_0\ => \gen_mux_rd[4].mux_rd_rise2_r_reg[4]\,
      \gen_mux_rd[4].mux_rd_rise3_r_reg[4]_0\ => \gen_mux_rd[4].mux_rd_rise3_r_reg[4]\,
      \gen_mux_rd[5].mux_rd_fall0_r_reg[5]_0\ => \gen_mux_rd[5].mux_rd_fall0_r_reg[5]\,
      \gen_mux_rd[5].mux_rd_fall1_r_reg[5]_0\ => \gen_mux_rd[5].mux_rd_fall1_r_reg[5]\,
      \gen_mux_rd[5].mux_rd_fall2_r_reg[5]_0\ => \gen_mux_rd[5].mux_rd_fall2_r_reg[5]\,
      \gen_mux_rd[5].mux_rd_fall3_r_reg[5]_0\ => \gen_mux_rd[5].mux_rd_fall3_r_reg[5]\,
      \gen_mux_rd[5].mux_rd_rise0_r_reg[5]_0\ => \gen_mux_rd[5].mux_rd_rise0_r_reg[5]\,
      \gen_mux_rd[5].mux_rd_rise1_r_reg[5]_0\ => \gen_mux_rd[5].mux_rd_rise1_r_reg[5]\,
      \gen_mux_rd[5].mux_rd_rise2_r_reg[5]_0\ => \gen_mux_rd[5].mux_rd_rise2_r_reg[5]\,
      \gen_mux_rd[5].mux_rd_rise3_r_reg[5]_0\ => \gen_mux_rd[5].mux_rd_rise3_r_reg[5]\,
      \gen_mux_rd[6].mux_rd_fall0_r_reg[6]_0\ => \gen_mux_rd[6].mux_rd_fall0_r_reg[6]\,
      \gen_mux_rd[6].mux_rd_fall1_r_reg[6]_0\ => \gen_mux_rd[6].mux_rd_fall1_r_reg[6]\,
      \gen_mux_rd[6].mux_rd_fall2_r_reg[6]_0\ => \gen_mux_rd[6].mux_rd_fall2_r_reg[6]\,
      \gen_mux_rd[6].mux_rd_fall3_r_reg[6]_0\ => \gen_mux_rd[6].mux_rd_fall3_r_reg[6]\,
      \gen_mux_rd[6].mux_rd_rise0_r_reg[6]_0\ => \gen_mux_rd[6].mux_rd_rise0_r_reg[6]\,
      \gen_mux_rd[6].mux_rd_rise1_r_reg[6]_0\ => \gen_mux_rd[6].mux_rd_rise1_r_reg[6]\,
      \gen_mux_rd[6].mux_rd_rise2_r_reg[6]_0\ => \gen_mux_rd[6].mux_rd_rise2_r_reg[6]\,
      \gen_mux_rd[6].mux_rd_rise3_r_reg[6]_0\ => \gen_mux_rd[6].mux_rd_rise3_r_reg[6]\,
      \gen_mux_rd[7].mux_rd_fall0_r_reg[7]_0\ => \gen_mux_rd[7].mux_rd_fall0_r_reg[7]\,
      \gen_mux_rd[7].mux_rd_fall1_r_reg[7]_0\ => \gen_mux_rd[7].mux_rd_fall1_r_reg[7]\,
      \gen_mux_rd[7].mux_rd_fall2_r_reg[7]_0\ => \gen_mux_rd[7].mux_rd_fall2_r_reg[7]\,
      \gen_mux_rd[7].mux_rd_fall3_r_reg[7]_0\ => \gen_mux_rd[7].mux_rd_fall3_r_reg[7]\,
      \gen_mux_rd[7].mux_rd_rise0_r_reg[7]_0\ => \gen_mux_rd[7].mux_rd_rise0_r_reg[7]\,
      \gen_mux_rd[7].mux_rd_rise1_r_reg[7]_0\ => \gen_mux_rd[7].mux_rd_rise1_r_reg[7]\,
      \gen_mux_rd[7].mux_rd_rise2_r_reg[7]_0\ => \gen_mux_rd[7].mux_rd_rise2_r_reg[7]\,
      \gen_mux_rd[7].mux_rd_rise3_r_reg[7]_0\ => \gen_mux_rd[7].mux_rd_rise3_r_reg[7]\,
      idelay_ce_int => idelay_ce_int,
      idelay_inc_int => idelay_inc_int,
      \idelay_tap_cnt_r_reg[0][0][4]_0\(0) => u_ddr_phy_wrcal_n_30,
      \idelay_tap_cnt_r_reg[0][1][4]_0\(0) => u_ddr_phy_wrcal_n_34,
      \idelay_tap_cnt_r_reg[0][2][4]_0\(0) => u_ddr_phy_wrcal_n_35,
      \idelay_tap_cnt_r_reg[0][3][4]_0\(0) => u_ddr_phy_wrcal_n_36,
      \idelay_tap_cnt_r_reg[0][4][4]_0\(0) => u_ddr_phy_wrcal_n_29,
      \idelay_tap_cnt_r_reg[0][5][4]_0\(0) => u_ddr_phy_wrcal_n_31,
      \idelay_tap_cnt_r_reg[0][6][4]_0\(0) => u_ddr_phy_wrcal_n_32,
      \idelay_tap_cnt_r_reg[0][7][4]_0\(0) => u_ddr_phy_wrcal_n_33,
      \init_state_r[1]_i_16\(0) => u_ddr_phy_init_n_29,
      mpr_rdlvl_start_r_reg_0 => u_ddr_phy_init_n_701,
      new_cnt_cpt_r_reg_0 => new_cnt_cpt_r_reg,
      p_1_in => p_1_in_0,
      pi_cnt_dec_reg_0 => pi_cnt_dec_reg,
      pi_fine_dly_dec_done => pi_fine_dly_dec_done,
      pi_stg2_f_incdec_timing_reg_0 => \idelay_tap_cnt_r_reg[0][0][4]\,
      pi_stg2_load_reg_0 => pi_counter_load_en,
      \pi_stg2_reg_l_reg[5]_0\(5 downto 0) => pi_counter_load_val(5 downto 0),
      prech_done => prech_done,
      prech_req => prech_req,
      prech_req_r_reg => \ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_2\,
      prech_req_r_reg_0 => u_ddr_phy_init_n_683,
      \rd_mux_sel_r_reg[2]_0\ => \rd_mux_sel_r_reg[2]\,
      \rdlvl_dqs_tap_cnt_r_reg[0][0][2]_0\(1 downto 0) => \rdlvl_dqs_tap_cnt_r_reg[0][0][2]\(1 downto 0),
      rdlvl_last_byte_done => rdlvl_last_byte_done,
      rdlvl_pi_incdec => rdlvl_pi_incdec,
      rdlvl_pi_incdec_reg_0 => \dout_o_reg[15]\,
      rdlvl_pi_stg2_f_en => rdlvl_pi_stg2_f_en,
      rdlvl_pi_stg2_f_incdec => rdlvl_pi_stg2_f_incdec,
      rdlvl_prech_req => rdlvl_prech_req,
      rdlvl_stg1_done_int_reg_0 => \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_10\,
      rdlvl_stg1_done_int_reg_1 => \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_19\,
      rdlvl_stg1_done_int_reg_2(0) => \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_20\,
      rdlvl_stg1_done_int_reg_3(3 downto 0) => p_1_in(3 downto 0),
      rdlvl_stg1_done_r1 => rdlvl_stg1_done_r1,
      rdlvl_stg1_done_r1_reg => \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_30\,
      rdlvl_stg1_rank_done => rdlvl_stg1_rank_done,
      rdlvl_stg1_start_r_reg_0 => \^rdlvl_stg1_start_reg\,
      \rnk_cnt_r_reg[0]_0\ => \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_26\,
      \rnk_cnt_r_reg[1]_0\ => \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_14\,
      samp_edge_cnt0_en_r => samp_edge_cnt0_en_r,
      \samp_edge_cnt1_r_reg[0]_0\ => \samp_edge_cnt1_r_reg[0]\,
      sr_valid_r_reg_0 => po_en_stg2_f_reg,
      stg1_wr_done => stg1_wr_done,
      \stg1_wr_rd_cnt_reg[3]\ => \not_empty_wait_cnt_reg[4]\,
      \tap_cnt_cpt_r_reg[5]_0\(0) => \tap_cnt_cpt_r_reg[5]\(0),
      \wait_cnt_r_reg[0]_0\(0) => \wait_cnt_r_reg[0]_0\(0),
      wrcal_prech_req => wrcal_prech_req,
      \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[56]\ => u_ddr_phy_wrcal_n_3,
      \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[56]_0\ => \ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_7\
    );
ddr_phy_tempmon_0: entity work.mig_mig_7series_v4_2_ddr_phy_tempmon
     port map (
      D(2) => ddr_phy_tempmon_0_n_2,
      D(1) => ddr_phy_tempmon_0_n_3,
      D(0) => ddr_phy_tempmon_0_n_4,
      Q(1) => \gen_byte_sel_div2.byte_sel_cnt_reg_n_0_[3]\,
      Q(0) => \gen_byte_sel_div2.byte_sel_cnt_reg_n_0_[2]\,
      calib_complete => calib_complete,
      calib_in_common => calib_in_common,
      calib_in_common4_out => calib_in_common4_out,
      \calib_sel1__1\ => \calib_sel1__1\,
      \calib_sel_reg[0]\ => \not_empty_wait_cnt_reg[4]\,
      \calib_zero_inputs_reg[2]\ => \dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_54\,
      cmd_delay_start0 => cmd_delay_start0,
      \device_temp_101_reg[0]_0\ => first_fail_detect_reg,
      \device_temp_101_reg[11]_0\(11 downto 0) => \device_temp_101_reg[11]\(11 downto 0),
      dqs_po_dec_done => dqs_po_dec_done,
      \four_dec_min_limit_reg[0]_0\ => \four_dec_min_limit_reg[0]\,
      \gen_byte_sel_div2.calib_in_common_i_2\ => \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_10\,
      \gen_byte_sel_div2.calib_in_common_i_2_0\ => u_ddr_phy_wrcal_n_3,
      \gen_byte_sel_div2.calib_in_common_i_2_1\ => \mb_wrlvl_inst.u_ddr_phy_wrlvl_n_5\,
      \gen_byte_sel_div2.calib_in_common_i_3\ => \ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_7\,
      mc_ref_zq_wip => mc_ref_zq_wip,
      \neutral_max_limit_reg[11]_0\ => po_en_stg2_f_reg,
      \one_dec_max_limit_reg[2]_0\ => \one_dec_max_limit_reg[2]\,
      \one_dec_min_limit_reg[11]_0\ => \one_dec_min_limit_reg[11]\,
      pi_f_dec_reg_0 => \dout_o_reg[15]\,
      pi_f_dec_reg_1(0) => \victim_sel_reg[0]\(0),
      pi_f_inc_reg_0 => ddr_phy_tempmon_0_n_5,
      pi_fine_dly_dec_done => pi_fine_dly_dec_done,
      rdlvl_stg1_done_int_reg => ddr_phy_tempmon_0_n_6,
      tempmon_pi_f_inc => tempmon_pi_f_inc,
      tempmon_sel_pi_incdec => tempmon_sel_pi_incdec
    );
\dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr\: entity work.mig_mig_7series_v4_2_ddr_phy_dqs_found_cal_hr
     port map (
      Q(0) => \dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_28\,
      SR(0) => \dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_58\,
      calib_in_common => calib_in_common,
      calib_in_common4_out => calib_in_common4_out,
      \calib_sel1__1\ => \calib_sel1__1\,
      \calib_sel_reg[0]\(2) => \gen_byte_sel_div2.byte_sel_cnt_reg_n_0_[3]\,
      \calib_sel_reg[0]\(1) => \gen_byte_sel_div2.byte_sel_cnt_reg_n_0_[2]\,
      \calib_sel_reg[0]\(0) => \gen_byte_sel_div2.byte_sel_cnt_reg_n_0_[0]\,
      \calib_sel_reg[1]\ => \calib_sel[1]_i_3_n_0\,
      ck_addr_cmd_delay_done => ck_addr_cmd_delay_done,
      ck_po_stg2_f_en => ck_po_stg2_f_en,
      ck_po_stg2_f_indec => ck_po_stg2_f_indec,
      cmd_delay_start0 => cmd_delay_start0,
      ctl_lane_cnt(2 downto 0) => ctl_lane_cnt(2 downto 0),
      \ctl_lane_cnt_reg[0]_0\ => \dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_57\,
      \ctl_lane_cnt_reg[1]_0\ => \dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_56\,
      \ctl_lane_cnt_reg[2]_0\ => \dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_53\,
      ctl_lane_sel => ctl_lane_sel,
      delay_done_r4_reg => \dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_52\,
      delay_done_r4_reg_0 => \dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_62\,
      detect_pi_found_dqs => detect_pi_found_dqs,
      dqs_found_done_r_reg_0 => \dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_2\,
      dqs_found_done_r_reg_1 => \dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_49\,
      dqs_found_done_r_reg_2 => \dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_50\,
      dqs_found_prech_req => dqs_found_prech_req,
      dqs_found_start_r_reg_0 => u_ddr_phy_init_n_700,
      dqs_po_dec_done => dqs_po_dec_done,
      fine_adjust_reg_0 => fine_adjust_reg,
      first_fail_detect_reg_0 => first_fail_detect_reg,
      \gen_byte_sel_div2.byte_sel_cnt_reg[0]\ => \not_empty_wait_cnt_reg[4]\,
      \gen_byte_sel_div2.calib_in_common_reg\ => ddr_phy_tempmon_0_n_6,
      \gen_byte_sel_div2.ctl_lane_sel_reg[0]\ => \gen_byte_sel_div2.ctl_lane_sel_reg_n_0_[0]\,
      \gen_byte_sel_div2.ctl_lane_sel_reg[1]\ => \gen_byte_sel_div2.ctl_lane_sel_reg_n_0_[1]\,
      \gen_byte_sel_div2.ctl_lane_sel_reg[2]\ => \dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_59\,
      \gen_byte_sel_div2.ctl_lane_sel_reg[2]_0\ => \dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_61\,
      \gen_byte_sel_div2.ctl_lane_sel_reg[2]_1\ => \gen_byte_sel_div2.ctl_lane_sel_reg_n_0_[2]\,
      \gen_no_mirror.div_clk_loop[0].phy_address_reg[10]\ => \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_10\,
      \gen_no_mirror.div_clk_loop[0].phy_address_reg[10]_0\ => \ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_7\,
      in0(7 downto 0) => in0(7 downto 0),
      \init_dec_cnt_reg[4]_0\(0) => \rdlvl_dqs_tap_cnt_r_reg[0][0][2]\(0),
      init_dqsfound_done_r2 => init_dqsfound_done_r2,
      init_dqsfound_done_r5_reg_0 => \dout_o_reg[15]\,
      init_dqsfound_done_r_reg_0 => \idelay_tap_cnt_r_reg[0][4][4]\,
      \init_state_r[0]_i_10\ => u_ddr_phy_init_n_3,
      \init_state_r[2]_i_10\ => u_ddr_phy_wrcal_n_3,
      pi_calib_done => pi_calib_done,
      \pi_dqs_found_any_bank_reg[0]_0\(1 downto 0) => \fine_dec_cnt_reg[5]\(1 downto 0),
      pi_dqs_found_done_r1 => pi_dqs_found_done_r1,
      pi_dqs_found_done_r1_reg => \dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_34\,
      pi_dqs_found_done_r1_reg_0 => \dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_35\,
      pi_dqs_found_done_r1_reg_1 => \dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_36\,
      pi_dqs_found_done_r1_reg_10 => \dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_45\,
      pi_dqs_found_done_r1_reg_11 => \dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_46\,
      pi_dqs_found_done_r1_reg_12 => \dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_47\,
      pi_dqs_found_done_r1_reg_13 => \dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_48\,
      pi_dqs_found_done_r1_reg_2 => \dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_37\,
      pi_dqs_found_done_r1_reg_3 => \dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_38\,
      pi_dqs_found_done_r1_reg_4 => \dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_39\,
      pi_dqs_found_done_r1_reg_5 => \dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_40\,
      pi_dqs_found_done_r1_reg_6 => \dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_41\,
      pi_dqs_found_done_r1_reg_7 => \dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_42\,
      pi_dqs_found_done_r1_reg_8 => \dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_43\,
      pi_dqs_found_done_r1_reg_9 => \dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_44\,
      pi_dqs_found_rank_done => pi_dqs_found_rank_done,
      pi_fine_dly_dec_done => pi_fine_dly_dec_done,
      \pi_rst_stg1_cal_r_reg[1]_0\ => \pi_rst_stg1_cal_r_reg[1]\,
      \pi_rst_stg1_cal_reg[0]_0\ => \dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_54\,
      \pi_rst_stg1_cal_reg[2]_0\(2 downto 0) => pi_rst_dqs_find(2 downto 0),
      prech_done => prech_done,
      rank_done_r_reg_0 => \dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_51\,
      \rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][0]_0\ => \rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][0]\,
      \rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][5]_0\(5 downto 0) => \rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][5]\(5 downto 0),
      \rank_final_loop[0].bank_final_loop[0].final_data_offset_reg[0][3]_0\(0) => rd_data_offset_ranks_0(3),
      \rank_final_loop[0].bank_final_loop[1].final_data_offset_mc_reg[0][11]_0\(5 downto 0) => \rank_final_loop[0].bank_final_loop[1].final_data_offset_mc_reg[0][11]\(5 downto 0),
      \rank_final_loop[0].bank_final_loop[1].final_data_offset_mc_reg[0][6]_0\ => \rank_final_loop[0].bank_final_loop[1].final_data_offset_mc_reg[0][6]\,
      \rank_final_loop[0].bank_final_loop[1].final_data_offset_reg[0][9]_0\(0) => rd_data_offset_ranks_1(3),
      \rank_final_loop[0].bank_final_loop[2].final_data_offset_mc_reg[0][12]_0\ => \rank_final_loop[0].bank_final_loop[2].final_data_offset_mc_reg[0][12]\,
      \rank_final_loop[0].bank_final_loop[2].final_data_offset_mc_reg[0][17]_0\(5 downto 0) => \rank_final_loop[0].bank_final_loop[2].final_data_offset_mc_reg[0][17]\(5 downto 0),
      \rank_final_loop[0].bank_final_loop[2].final_data_offset_reg[0][15]_0\(0) => rd_data_offset_ranks_2(3),
      \rd_byte_data_offset_reg[0][15]_0\(0) => \dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_30\,
      \rd_byte_data_offset_reg[0][9]_0\(0) => \dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_29\,
      \stable_pass_cnt_reg[0]_0\ => cal2_if_reset_reg
    );
\gen_byte_sel_div2.byte_sel_cnt_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \dout_o_reg[15]\,
      CE => \mb_wrlvl_inst.u_ddr_phy_ck_addr_cmd_delay_n_7\,
      D => p_1_in(0),
      Q => \gen_byte_sel_div2.byte_sel_cnt_reg_n_0_[0]\,
      R => \dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_58\
    );
\gen_byte_sel_div2.byte_sel_cnt_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \dout_o_reg[15]\,
      CE => \mb_wrlvl_inst.u_ddr_phy_ck_addr_cmd_delay_n_7\,
      D => p_1_in(1),
      Q => \gen_byte_sel_div2.byte_sel_cnt_reg_n_0_[1]\,
      R => \dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_58\
    );
\gen_byte_sel_div2.byte_sel_cnt_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \dout_o_reg[15]\,
      CE => \mb_wrlvl_inst.u_ddr_phy_ck_addr_cmd_delay_n_7\,
      D => p_1_in(2),
      Q => \gen_byte_sel_div2.byte_sel_cnt_reg_n_0_[2]\,
      R => \dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_58\
    );
\gen_byte_sel_div2.byte_sel_cnt_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => \dout_o_reg[15]\,
      CE => \mb_wrlvl_inst.u_ddr_phy_ck_addr_cmd_delay_n_7\,
      D => p_1_in(3),
      Q => \gen_byte_sel_div2.byte_sel_cnt_reg_n_0_[3]\,
      R => \dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_58\
    );
\gen_byte_sel_div2.calib_in_common_reg\: unisim.vcomponents.FDRE
     port map (
      C => \dout_o_reg[15]\,
      CE => '1',
      D => \dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_52\,
      Q => calib_in_common,
      R => \corse_inc_reg[6][2]\(0)
    );
\gen_byte_sel_div2.ctl_lane_sel_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \dout_o_reg[15]\,
      CE => '1',
      D => \dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_57\,
      Q => \gen_byte_sel_div2.ctl_lane_sel_reg_n_0_[0]\,
      R => \corse_inc_reg[6][2]\(0)
    );
\gen_byte_sel_div2.ctl_lane_sel_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \dout_o_reg[15]\,
      CE => '1',
      D => \dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_56\,
      Q => \gen_byte_sel_div2.ctl_lane_sel_reg_n_0_[1]\,
      R => \corse_inc_reg[6][2]\(0)
    );
\gen_byte_sel_div2.ctl_lane_sel_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \dout_o_reg[15]\,
      CE => '1',
      D => \dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_53\,
      Q => \gen_byte_sel_div2.ctl_lane_sel_reg_n_0_[2]\,
      R => \corse_inc_reg[6][2]\(0)
    );
idelay_ce_r1_reg: unisim.vcomponents.FDRE
     port map (
      C => \dout_o_reg[15]\,
      CE => '1',
      D => idelay_ce_int,
      Q => idelay_ce_r1,
      R => \corse_inc_reg[6][2]\(0)
    );
idelay_ce_r2_reg: unisim.vcomponents.FDRE
     port map (
      C => \dout_o_reg[15]\,
      CE => '1',
      D => idelay_ce_r1,
      Q => idelay_ce,
      R => \corse_inc_reg[6][2]\(0)
    );
idelay_inc_r1_reg: unisim.vcomponents.FDRE
     port map (
      C => \dout_o_reg[15]\,
      CE => '1',
      D => idelay_inc_int,
      Q => idelay_inc_r1,
      R => \corse_inc_reg[6][2]\(0)
    );
idelay_inc_r2_reg: unisim.vcomponents.FDRE
     port map (
      C => \dout_o_reg[15]\,
      CE => '1',
      D => idelay_inc_r1,
      Q => idelay_inc,
      R => \corse_inc_reg[6][2]\(0)
    );
init_calib_complete_reg: unisim.vcomponents.FDRE
     port map (
      C => \dout_o_reg[15]\,
      CE => '1',
      D => calib_complete,
      Q => d_in(13),
      R => '0'
    );
init_calib_complete_reg_rep: unisim.vcomponents.FDRE
     port map (
      C => \dout_o_reg[15]\,
      CE => '1',
      D => calib_complete,
      Q => init_calib_complete_reg_rep_0,
      R => '0'
    );
\init_calib_complete_reg_rep__0\: unisim.vcomponents.FDRE
     port map (
      C => \dout_o_reg[15]\,
      CE => '1',
      D => calib_complete,
      Q => \^init_calib_complete_reg_rep__0_0\,
      R => '0'
    );
\init_calib_complete_reg_rep__1\: unisim.vcomponents.FDRE
     port map (
      C => \dout_o_reg[15]\,
      CE => '1',
      D => calib_complete,
      Q => \init_calib_complete_reg_rep__1_n_0\,
      R => '0'
    );
\init_calib_complete_reg_rep__10\: unisim.vcomponents.FDRE
     port map (
      C => \dout_o_reg[15]\,
      CE => '1',
      D => calib_complete,
      Q => \init_calib_complete_reg_rep__10_n_0\,
      R => '0'
    );
\init_calib_complete_reg_rep__11\: unisim.vcomponents.FDRE
     port map (
      C => \dout_o_reg[15]\,
      CE => '1',
      D => calib_complete,
      Q => \^init_calib_complete_reg_rep__11_0\,
      R => '0'
    );
\init_calib_complete_reg_rep__12\: unisim.vcomponents.FDRE
     port map (
      C => \dout_o_reg[15]\,
      CE => '1',
      D => calib_complete,
      Q => \^init_calib_complete_reg_rep__12_0\,
      R => '0'
    );
\init_calib_complete_reg_rep__13\: unisim.vcomponents.FDRE
     port map (
      C => \dout_o_reg[15]\,
      CE => '1',
      D => calib_complete,
      Q => \init_calib_complete_reg_rep__13_n_0\,
      R => '0'
    );
\init_calib_complete_reg_rep__14\: unisim.vcomponents.FDRE
     port map (
      C => \dout_o_reg[15]\,
      CE => '1',
      D => calib_complete,
      Q => \init_calib_complete_reg_rep__14_n_0\,
      R => '0'
    );
\init_calib_complete_reg_rep__15\: unisim.vcomponents.FDRE
     port map (
      C => \dout_o_reg[15]\,
      CE => '1',
      D => calib_complete,
      Q => \init_calib_complete_reg_rep__15_n_0\,
      R => '0'
    );
\init_calib_complete_reg_rep__16\: unisim.vcomponents.FDRE
     port map (
      C => \dout_o_reg[15]\,
      CE => '1',
      D => calib_complete,
      Q => \init_calib_complete_reg_rep__16_n_0\,
      R => '0'
    );
\init_calib_complete_reg_rep__17\: unisim.vcomponents.FDRE
     port map (
      C => \dout_o_reg[15]\,
      CE => '1',
      D => calib_complete,
      Q => \init_calib_complete_reg_rep__17_n_0\,
      R => '0'
    );
\init_calib_complete_reg_rep__18\: unisim.vcomponents.FDRE
     port map (
      C => \dout_o_reg[15]\,
      CE => '1',
      D => calib_complete,
      Q => \init_calib_complete_reg_rep__18_n_0\,
      R => '0'
    );
\init_calib_complete_reg_rep__19\: unisim.vcomponents.FDRE
     port map (
      C => \dout_o_reg[15]\,
      CE => '1',
      D => calib_complete,
      Q => \init_calib_complete_reg_rep__19_n_0\,
      R => '0'
    );
\init_calib_complete_reg_rep__2\: unisim.vcomponents.FDRE
     port map (
      C => \dout_o_reg[15]\,
      CE => '1',
      D => calib_complete,
      Q => \init_calib_complete_reg_rep__2_n_0\,
      R => '0'
    );
\init_calib_complete_reg_rep__20\: unisim.vcomponents.FDRE
     port map (
      C => \dout_o_reg[15]\,
      CE => '1',
      D => calib_complete,
      Q => \init_calib_complete_reg_rep__20_n_0\,
      R => '0'
    );
\init_calib_complete_reg_rep__21\: unisim.vcomponents.FDRE
     port map (
      C => \dout_o_reg[15]\,
      CE => '1',
      D => calib_complete,
      Q => \init_calib_complete_reg_rep__21_n_0\,
      R => '0'
    );
\init_calib_complete_reg_rep__22\: unisim.vcomponents.FDRE
     port map (
      C => \dout_o_reg[15]\,
      CE => '1',
      D => calib_complete,
      Q => \init_calib_complete_reg_rep__22_n_0\,
      R => '0'
    );
\init_calib_complete_reg_rep__23\: unisim.vcomponents.FDRE
     port map (
      C => \dout_o_reg[15]\,
      CE => '1',
      D => calib_complete,
      Q => \init_calib_complete_reg_rep__23_n_0\,
      R => '0'
    );
\init_calib_complete_reg_rep__24\: unisim.vcomponents.FDRE
     port map (
      C => \dout_o_reg[15]\,
      CE => '1',
      D => calib_complete,
      Q => \^init_calib_complete_reg_rep__24_0\,
      R => '0'
    );
\init_calib_complete_reg_rep__25\: unisim.vcomponents.FDRE
     port map (
      C => \dout_o_reg[15]\,
      CE => '1',
      D => calib_complete,
      Q => \^init_calib_complete_reg_rep__25_0\,
      R => '0'
    );
\init_calib_complete_reg_rep__26\: unisim.vcomponents.FDRE
     port map (
      C => \dout_o_reg[15]\,
      CE => '1',
      D => calib_complete,
      Q => \^init_calib_complete_reg_rep__26_0\,
      R => '0'
    );
\init_calib_complete_reg_rep__3\: unisim.vcomponents.FDRE
     port map (
      C => \dout_o_reg[15]\,
      CE => '1',
      D => calib_complete,
      Q => \init_calib_complete_reg_rep__3_n_0\,
      R => '0'
    );
\init_calib_complete_reg_rep__4\: unisim.vcomponents.FDRE
     port map (
      C => \dout_o_reg[15]\,
      CE => '1',
      D => calib_complete,
      Q => \init_calib_complete_reg_rep__4_n_0\,
      R => '0'
    );
\init_calib_complete_reg_rep__5\: unisim.vcomponents.FDRE
     port map (
      C => \dout_o_reg[15]\,
      CE => '1',
      D => calib_complete,
      Q => \init_calib_complete_reg_rep__5_n_0\,
      R => '0'
    );
\init_calib_complete_reg_rep__6\: unisim.vcomponents.FDRE
     port map (
      C => \dout_o_reg[15]\,
      CE => '1',
      D => calib_complete,
      Q => \init_calib_complete_reg_rep__6_n_0\,
      R => '0'
    );
\init_calib_complete_reg_rep__7\: unisim.vcomponents.FDRE
     port map (
      C => \dout_o_reg[15]\,
      CE => '1',
      D => calib_complete,
      Q => \init_calib_complete_reg_rep__7_n_0\,
      R => '0'
    );
\init_calib_complete_reg_rep__8\: unisim.vcomponents.FDRE
     port map (
      C => \dout_o_reg[15]\,
      CE => '1',
      D => calib_complete,
      Q => \init_calib_complete_reg_rep__8_n_0\,
      R => '0'
    );
\init_calib_complete_reg_rep__9\: unisim.vcomponents.FDRE
     port map (
      C => \dout_o_reg[15]\,
      CE => '1',
      D => calib_complete,
      Q => \init_calib_complete_reg_rep__9_n_0\,
      R => '0'
    );
\input_[1].iserdes_dq_.idelay_dq.idelaye2_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000F010"
    )
        port map (
      I0 => \^calib_sel\(1),
      I1 => \^calib_sel\(0),
      I2 => idelay_ce,
      I3 => calib_in_common,
      I4 => calib_zero_inputs(0),
      O => \calib_sel_reg[1]_3\
    );
\input_[1].iserdes_dq_.idelay_dq.idelaye2_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000F010"
    )
        port map (
      I0 => \^calib_sel\(1),
      I1 => \^calib_sel\(0),
      I2 => idelay_ce,
      I3 => calib_in_common,
      I4 => calib_zero_inputs(2),
      O => \calib_sel_reg[1]_27\
    );
\input_[2].iserdes_dq_.idelay_dq.idelaye2_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000CC40"
    )
        port map (
      I0 => \^calib_sel\(1),
      I1 => idelay_ce,
      I2 => \^calib_sel\(0),
      I3 => calib_in_common,
      I4 => calib_zero_inputs(0),
      O => \calib_sel_reg[1]_12\
    );
\input_[2].iserdes_dq_.idelay_dq.idelaye2_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000CC08"
    )
        port map (
      I0 => \^calib_sel\(1),
      I1 => idelay_ce,
      I2 => \^calib_sel\(0),
      I3 => calib_in_common,
      I4 => calib_zero_inputs(0),
      O => \calib_sel_reg[1]_18\
    );
\input_[2].iserdes_dq_.idelay_dq.idelaye2_i_1__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000AA80"
    )
        port map (
      I0 => idelay_ce,
      I1 => \^calib_sel\(0),
      I2 => \^calib_sel\(1),
      I3 => calib_in_common,
      I4 => calib_zero_inputs(0),
      O => idelay_ce_r2_reg_0
    );
\input_[2].iserdes_dq_.idelay_dq.idelaye2_i_1__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000CC40"
    )
        port map (
      I0 => \^calib_sel\(1),
      I1 => idelay_ce,
      I2 => \^calib_sel\(0),
      I3 => calib_in_common,
      I4 => calib_zero_inputs(2),
      O => \calib_sel_reg[1]_36\
    );
\input_[2].iserdes_dq_.idelay_dq.idelaye2_i_1__3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000CC08"
    )
        port map (
      I0 => \^calib_sel\(1),
      I1 => idelay_ce,
      I2 => \^calib_sel\(0),
      I3 => calib_in_common,
      I4 => calib_zero_inputs(2),
      O => \calib_sel_reg[1]_42\
    );
\input_[2].iserdes_dq_.idelay_dq.idelaye2_i_1__4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000AA80"
    )
        port map (
      I0 => idelay_ce,
      I1 => \^calib_sel\(0),
      I2 => \^calib_sel\(1),
      I3 => calib_in_common,
      I4 => calib_zero_inputs(2),
      O => idelay_ce_r2_reg_1
    );
\mb_wrlvl_inst.u_ddr_phy_ck_addr_cmd_delay\: entity work.mig_mig_7series_v4_2_ddr_phy_ck_addr_cmd_delay
     port map (
      E(0) => \mb_wrlvl_inst.u_ddr_phy_ck_addr_cmd_delay_n_7\,
      SS(0) => \mb_wrlvl_inst.u_ddr_phy_wrlvl_n_50\,
      ck_addr_cmd_delay_done => ck_addr_cmd_delay_done,
      cmd_delay_start0 => cmd_delay_start0,
      cmd_po_en_stg2_f => cmd_po_en_stg2_f,
      ctl_lane_cnt(2 downto 0) => ctl_lane_cnt(2 downto 0),
      \ctl_lane_cnt_reg[1]_0\ => \idelay_tap_cnt_r_reg[0][4][4]\,
      delay_done_r4_reg_0 => \dout_o_reg[15]\,
      delaydec_cnt_r10_in => delaydec_cnt_r10_in,
      dqs_po_dec_done => dqs_po_dec_done,
      \gen_byte_sel_div2.byte_sel_cnt_reg[0]\ => \mb_wrlvl_inst.u_ddr_phy_wrlvl_n_5\,
      \gen_byte_sel_div2.byte_sel_cnt_reg[0]_0\ => u_ddr_phy_wrcal_n_3,
      \gen_byte_sel_div2.byte_sel_cnt_reg[0]_1\ => \ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_7\,
      \gen_byte_sel_div2.byte_sel_cnt_reg[0]_2\ => \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_10\,
      p_1_in => p_1_in_0,
      pi_fine_dly_dec_done => pi_fine_dly_dec_done,
      po_cnt_dec_2 => po_cnt_dec_2,
      po_en_stg2_f_reg_0 => po_en_stg2_f_reg,
      tempmon_sel_pi_incdec => tempmon_sel_pi_incdec,
      \wait_cnt_r_reg[0]_0\(0) => \wait_cnt_r_reg[0]\(0)
    );
\mb_wrlvl_inst.u_ddr_phy_wrlvl\: entity work.mig_mig_7series_v4_2_ddr_phy_wrlvl
     port map (
      C_po_coarse_enable26_out => C_po_coarse_enable26_out,
      C_po_fine_enable23_out => C_po_fine_enable23_out,
      C_po_fine_inc29_out => C_po_fine_inc29_out,
      \FSM_sequential_wl_state_r_reg[0]_0\ => u_ddr_phy_init_n_677,
      \FSM_sequential_wl_state_r_reg[2]_0\ => \mb_wrlvl_inst.u_ddr_phy_wrlvl_n_46\,
      \FSM_sequential_wl_state_r_reg[4]_0\(1 downto 0) => \wl_state_r__0\(4 downto 3),
      Q(0) => Q(0),
      SS(0) => \mb_wrlvl_inst.u_ddr_phy_wrlvl_n_50\,
      calib_in_common => calib_in_common,
      \calib_sel_reg[0]\ => \calib_sel_reg[0]_1\,
      \calib_sel_reg[0]_0\ => \calib_sel_reg[0]_5\,
      \calib_sel_reg[1]\ => \calib_sel_reg[1]_2\,
      \calib_sel_reg[1]_0\ => \calib_sel_reg[1]_4\,
      \calib_sel_reg[1]_1\ => \calib_sel_reg[1]_8\,
      \calib_sel_reg[1]_10\ => \calib_sel_reg[1]_43\,
      \calib_sel_reg[1]_2\ => \calib_sel_reg[1]_10\,
      \calib_sel_reg[1]_3\ => \calib_sel_reg[1]_13\,
      \calib_sel_reg[1]_4\ => \calib_sel_reg[1]_19\,
      \calib_sel_reg[1]_5\ => \calib_sel_reg[1]_26\,
      \calib_sel_reg[1]_6\ => \calib_sel_reg[1]_28\,
      \calib_sel_reg[1]_7\ => \calib_sel_reg[1]_32\,
      \calib_sel_reg[1]_8\ => \calib_sel_reg[1]_34\,
      \calib_sel_reg[1]_9\ => \calib_sel_reg[1]_37\,
      ck_po_stg2_f_indec => ck_po_stg2_f_indec,
      cmd_delay_start0 => cmd_delay_start0,
      \corse_cnt_reg[3][0]_0\ => u_ddr_phy_wrcal_n_23,
      \corse_cnt_reg[4][0]_0\ => u_ddr_phy_wrcal_n_25,
      \corse_cnt_reg[5][0]_0\ => u_ddr_phy_wrcal_n_26,
      \corse_cnt_reg[6][0]_0\ => u_ddr_phy_wrcal_n_27,
      \corse_cnt_reg[7][0]_0\ => u_ddr_phy_wrcal_n_8,
      \corse_cnt_reg[7][0]_1\ => u_ddr_phy_wrcal_n_28,
      \corse_dec_reg[7][0]_0\(1 downto 0) => \corse_dec_reg[7][0]\(1 downto 0),
      \corse_inc_reg[6][2]_0\(1 downto 0) => \corse_inc_reg[6][2]\(1 downto 0),
      delaydec_cnt_r10_in => delaydec_cnt_r10_in,
      done_dqs_dec238_out => done_dqs_dec238_out,
      done_dqs_tap_inc => done_dqs_tap_inc,
      \dqs_count_r_reg[0]_rep_0\ => \mb_wrlvl_inst.u_ddr_phy_wrlvl_n_47\,
      \dqs_count_r_reg[1]_rep_0\ => \mb_wrlvl_inst.u_ddr_phy_wrlvl_n_48\,
      \dqs_count_r_reg[2]_rep__0_0\ => \mb_wrlvl_inst.u_ddr_phy_wrlvl_n_10\,
      \dqs_count_r_reg[2]_rep__0_1\ => \dout_o_reg[15]\,
      \dqs_count_r_reg[2]_rep__0_2\ => cal2_if_reset_reg,
      \dqs_count_r_reg[3]_0\(0) => dqs_count_r(3),
      \dqs_count_r_reg[3]_1\(3) => po_stg2_wrcal_cnt(3),
      \dqs_count_r_reg[3]_1\(2 downto 0) => \^po_stg2_wrcal_cnt_reg[2]\(2 downto 0),
      dqs_po_dec_done => dqs_po_dec_done,
      dqs_po_en_stg2_f => dqs_po_en_stg2_f,
      dqs_po_stg2_f_incdec_reg_0 => dqs_po_stg2_f_incdec_reg,
      dqs_po_stg2_f_incdec_reg_1 => dqs_po_stg2_f_incdec_reg_0,
      dqs_po_stg2_f_incdec_reg_2 => dqs_po_stg2_f_incdec_reg_1,
      dqs_po_stg2_f_incdec_reg_3 => dqs_po_stg2_f_incdec_reg_2,
      dqs_po_stg2_f_incdec_reg_4 => dqs_po_stg2_f_incdec_reg_3,
      dqs_po_stg2_f_incdec_reg_5 => dqs_po_stg2_f_incdec_reg_4,
      dqs_po_stg2_f_incdec_reg_6 => dqs_po_stg2_f_incdec_reg_5,
      dqs_po_stg2_f_incdec_reg_7 => dqs_po_stg2_f_incdec_reg_6,
      dqs_po_stg2_f_incdec_reg_8 => dqs_po_stg2_f_incdec_reg_7,
      dqs_po_stg2_f_incdec_reg_9 => dqs_po_stg2_f_incdec_reg_8,
      dqs_wl_po_stg2_c_incdec_reg_0 => dqs_wl_po_stg2_c_incdec_reg,
      dqs_wl_po_stg2_c_incdec_reg_1 => dqs_wl_po_stg2_c_incdec_reg_0,
      \fine_dec_cnt_reg[5]_0\(0) => \fine_dec_cnt_reg[5]\(1),
      \fine_inc_reg[6][3]_0\(1 downto 0) => \fine_inc_reg[6][3]\(1 downto 0),
      \gen_byte_sel_div2.calib_in_common_reg\ => \gen_byte_sel_div2.calib_in_common_reg_0\,
      \gen_byte_sel_div2.calib_in_common_reg_0\ => \gen_byte_sel_div2.calib_in_common_reg_1\,
      \gen_byte_sel_div2.calib_in_common_reg_1\ => \gen_byte_sel_div2.calib_in_common_reg_2\,
      \gen_byte_sel_div2.calib_in_common_reg_2\ => \gen_byte_sel_div2.calib_in_common_reg_3\,
      \gen_rd[0].rd_data_rise_wl_r_reg[0]_0\ => \gen_rd[0].rd_data_rise_wl_r_reg[0]\,
      \gen_rd[0].rd_data_rise_wl_r_reg[0]_1\ => \gen_rd[0].rd_data_rise_wl_r_reg[0]_0\,
      \gen_rd[0].rd_data_rise_wl_r_reg[0]_2\ => \gen_rd[0].rd_data_rise_wl_r_reg[0]_1\,
      \gen_rd[0].rd_data_rise_wl_r_reg[0]_3\ => \gen_rd[0].rd_data_rise_wl_r_reg[0]_2\,
      \gen_rd[0].rd_data_rise_wl_r_reg[0]_4\ => \gen_rd[0].rd_data_rise_wl_r_reg[0]_3\,
      \gen_rd[0].rd_data_rise_wl_r_reg[0]_5\ => \gen_rd[0].rd_data_rise_wl_r_reg[0]_4\,
      \gen_rd[0].rd_data_rise_wl_r_reg[0]_6\ => \gen_rd[0].rd_data_rise_wl_r_reg[0]_5\,
      \gen_rd[0].rd_data_rise_wl_r_reg[0]_7\ => \gen_rd[0].rd_data_rise_wl_r_reg[0]_6\,
      \gen_rd[1].rd_data_rise_wl_r_reg[1]_0\ => \gen_rd[1].rd_data_rise_wl_r_reg[1]\,
      \gen_rd[1].rd_data_rise_wl_r_reg[1]_1\ => \gen_rd[1].rd_data_rise_wl_r_reg[1]_0\,
      \gen_rd[1].rd_data_rise_wl_r_reg[1]_2\ => \gen_rd[1].rd_data_rise_wl_r_reg[1]_1\,
      \gen_rd[1].rd_data_rise_wl_r_reg[1]_3\ => \gen_rd[1].rd_data_rise_wl_r_reg[1]_2\,
      \gen_rd[1].rd_data_rise_wl_r_reg[1]_4\ => \gen_rd[1].rd_data_rise_wl_r_reg[1]_3\,
      \gen_rd[1].rd_data_rise_wl_r_reg[1]_5\ => \gen_rd[1].rd_data_rise_wl_r_reg[1]_4\,
      \gen_rd[1].rd_data_rise_wl_r_reg[1]_6\ => \gen_rd[1].rd_data_rise_wl_r_reg[1]_5\,
      \gen_rd[1].rd_data_rise_wl_r_reg[1]_7\ => \gen_rd[1].rd_data_rise_wl_r_reg[1]_6\,
      \gen_rd[2].rd_data_rise_wl_r_reg[2]_0\ => \gen_rd[2].rd_data_rise_wl_r_reg[2]\,
      \gen_rd[2].rd_data_rise_wl_r_reg[2]_1\ => \gen_rd[2].rd_data_rise_wl_r_reg[2]_0\,
      \gen_rd[2].rd_data_rise_wl_r_reg[2]_2\ => \gen_rd[2].rd_data_rise_wl_r_reg[2]_1\,
      \gen_rd[2].rd_data_rise_wl_r_reg[2]_3\ => \gen_rd[2].rd_data_rise_wl_r_reg[2]_2\,
      \gen_rd[2].rd_data_rise_wl_r_reg[2]_4\ => \gen_rd[2].rd_data_rise_wl_r_reg[2]_3\,
      \gen_rd[2].rd_data_rise_wl_r_reg[2]_5\ => \gen_rd[2].rd_data_rise_wl_r_reg[2]_4\,
      \gen_rd[2].rd_data_rise_wl_r_reg[2]_6\ => \gen_rd[2].rd_data_rise_wl_r_reg[2]_5\,
      \gen_rd[2].rd_data_rise_wl_r_reg[2]_7\ => \gen_rd[2].rd_data_rise_wl_r_reg[2]_6\,
      \gen_rd[3].rd_data_rise_wl_r_reg[3]_0\ => \gen_rd[3].rd_data_rise_wl_r_reg[3]\,
      \gen_rd[3].rd_data_rise_wl_r_reg[3]_1\ => \gen_rd[3].rd_data_rise_wl_r_reg[3]_0\,
      \gen_rd[3].rd_data_rise_wl_r_reg[3]_2\ => \gen_rd[3].rd_data_rise_wl_r_reg[3]_1\,
      \gen_rd[3].rd_data_rise_wl_r_reg[3]_3\ => \gen_rd[3].rd_data_rise_wl_r_reg[3]_2\,
      \gen_rd[3].rd_data_rise_wl_r_reg[3]_4\ => \gen_rd[3].rd_data_rise_wl_r_reg[3]_3\,
      \gen_rd[3].rd_data_rise_wl_r_reg[3]_5\ => \gen_rd[3].rd_data_rise_wl_r_reg[3]_4\,
      \gen_rd[3].rd_data_rise_wl_r_reg[3]_6\ => \gen_rd[3].rd_data_rise_wl_r_reg[3]_5\,
      \gen_rd[3].rd_data_rise_wl_r_reg[3]_7\ => \gen_rd[3].rd_data_rise_wl_r_reg[3]_6\,
      \gen_rd[4].rd_data_rise_wl_r_reg[4]_0\ => \gen_rd[4].rd_data_rise_wl_r_reg[4]\,
      \gen_rd[4].rd_data_rise_wl_r_reg[4]_1\ => \gen_rd[4].rd_data_rise_wl_r_reg[4]_0\,
      \gen_rd[4].rd_data_rise_wl_r_reg[4]_2\ => \gen_rd[4].rd_data_rise_wl_r_reg[4]_1\,
      \gen_rd[4].rd_data_rise_wl_r_reg[4]_3\ => \gen_rd[4].rd_data_rise_wl_r_reg[4]_2\,
      \gen_rd[4].rd_data_rise_wl_r_reg[4]_4\ => \gen_rd[4].rd_data_rise_wl_r_reg[4]_3\,
      \gen_rd[4].rd_data_rise_wl_r_reg[4]_5\ => \gen_rd[4].rd_data_rise_wl_r_reg[4]_4\,
      \gen_rd[4].rd_data_rise_wl_r_reg[4]_6\ => \gen_rd[4].rd_data_rise_wl_r_reg[4]_5\,
      \gen_rd[4].rd_data_rise_wl_r_reg[4]_7\ => \gen_rd[4].rd_data_rise_wl_r_reg[4]_6\,
      \gen_rd[5].rd_data_rise_wl_r_reg[5]_0\ => \gen_rd[5].rd_data_rise_wl_r_reg[5]\,
      \gen_rd[5].rd_data_rise_wl_r_reg[5]_1\ => \gen_rd[5].rd_data_rise_wl_r_reg[5]_0\,
      \gen_rd[5].rd_data_rise_wl_r_reg[5]_2\ => \gen_rd[5].rd_data_rise_wl_r_reg[5]_1\,
      \gen_rd[5].rd_data_rise_wl_r_reg[5]_3\ => \gen_rd[5].rd_data_rise_wl_r_reg[5]_2\,
      \gen_rd[5].rd_data_rise_wl_r_reg[5]_4\ => \gen_rd[5].rd_data_rise_wl_r_reg[5]_3\,
      \gen_rd[5].rd_data_rise_wl_r_reg[5]_5\ => \gen_rd[5].rd_data_rise_wl_r_reg[5]_4\,
      \gen_rd[5].rd_data_rise_wl_r_reg[5]_6\ => \gen_rd[5].rd_data_rise_wl_r_reg[5]_5\,
      \gen_rd[5].rd_data_rise_wl_r_reg[5]_7\ => \gen_rd[5].rd_data_rise_wl_r_reg[5]_6\,
      \gen_rd[6].rd_data_rise_wl_r_reg[6]_0\ => \gen_rd[6].rd_data_rise_wl_r_reg[6]\,
      \gen_rd[6].rd_data_rise_wl_r_reg[6]_1\ => \gen_rd[6].rd_data_rise_wl_r_reg[6]_0\,
      \gen_rd[6].rd_data_rise_wl_r_reg[6]_2\ => \gen_rd[6].rd_data_rise_wl_r_reg[6]_1\,
      \gen_rd[6].rd_data_rise_wl_r_reg[6]_3\ => \gen_rd[6].rd_data_rise_wl_r_reg[6]_2\,
      \gen_rd[6].rd_data_rise_wl_r_reg[6]_4\ => \gen_rd[6].rd_data_rise_wl_r_reg[6]_3\,
      \gen_rd[6].rd_data_rise_wl_r_reg[6]_5\ => \gen_rd[6].rd_data_rise_wl_r_reg[6]_4\,
      \gen_rd[6].rd_data_rise_wl_r_reg[6]_6\ => \gen_rd[6].rd_data_rise_wl_r_reg[6]_5\,
      \gen_rd[6].rd_data_rise_wl_r_reg[6]_7\ => \gen_rd[6].rd_data_rise_wl_r_reg[6]_6\,
      \gen_rd[7].rd_data_rise_wl_r_reg[7]_0\ => \gen_rd[7].rd_data_rise_wl_r_reg[7]\,
      \gen_rd[7].rd_data_rise_wl_r_reg[7]_1\ => \gen_rd[7].rd_data_rise_wl_r_reg[7]_0\,
      \gen_rd[7].rd_data_rise_wl_r_reg[7]_2\ => \gen_rd[7].rd_data_rise_wl_r_reg[7]_1\,
      \gen_rd[7].rd_data_rise_wl_r_reg[7]_3\ => \gen_rd[7].rd_data_rise_wl_r_reg[7]_2\,
      \gen_rd[7].rd_data_rise_wl_r_reg[7]_4\ => \gen_rd[7].rd_data_rise_wl_r_reg[7]_3\,
      \gen_rd[7].rd_data_rise_wl_r_reg[7]_5\ => \gen_rd[7].rd_data_rise_wl_r_reg[7]_4\,
      \gen_rd[7].rd_data_rise_wl_r_reg[7]_6\ => \gen_rd[7].rd_data_rise_wl_r_reg[7]_5\,
      \gen_rd[7].rd_data_rise_wl_r_reg[7]_7\ => \gen_rd[7].rd_data_rise_wl_r_reg[7]_6\,
      phaser_out => \^calib_sel\(1),
      phaser_out_0 => \^calib_sel\(0),
      phaser_out_1(2 downto 0) => calib_zero_inputs(2 downto 0),
      pi_fine_dly_dec_done => pi_fine_dly_dec_done,
      po_cnt_dec_reg_0 => po_cnt_dec_reg,
      po_enstg2_f(0) => po_enstg2_f(2),
      \po_rdval_cnt_reg[0]_0\ => \po_rdval_cnt_reg[0]\,
      \po_rdval_cnt_reg[1]_0\ => \po_rdval_cnt_reg[1]\,
      \po_rdval_cnt_reg[2]_0\ => \po_rdval_cnt_reg[2]\,
      \po_rdval_cnt_reg[3]_0\ => \po_rdval_cnt_reg[3]\,
      \po_rdval_cnt_reg[4]_0\ => \po_rdval_cnt_reg[4]\,
      \po_rdval_cnt_reg[5]_0\ => \po_rdval_cnt_reg[5]\,
      \po_rdval_cnt_reg[6]_0\ => \po_rdval_cnt_reg[6]\,
      \po_rdval_cnt_reg[7]_0\ => \po_rdval_cnt_reg[7]\,
      \po_rdval_cnt_reg[8]_0\ => \po_rdval_cnt_reg[8]\,
      \po_stg2_wrcal_cnt_reg[2]\ => \mb_wrlvl_inst.u_ddr_phy_wrlvl_n_44\,
      \po_stg2_wrcal_cnt_reg[2]_0\ => \mb_wrlvl_inst.u_ddr_phy_wrlvl_n_45\,
      \single_rank.done_dqs_dec_reg_0\ => \idelay_tap_cnt_r_reg[0][4][4]\,
      \wait_cnt_reg[0]_0\(0) => SS(0),
      \wl_dqs_tap_count_r_reg[0][5][5]_0\ => \wl_dqs_tap_count_r_reg[0][5][5]\,
      wl_sm_start => wl_sm_start,
      wr_level_done_r5 => wr_level_done_r5,
      wr_level_done_reg_0 => \mb_wrlvl_inst.u_ddr_phy_wrlvl_n_5\,
      wr_level_start_r_reg_0 => u_ddr_phy_init_n_15,
      wrlvl_byte_done => wrlvl_byte_done,
      wrlvl_byte_redo => wrlvl_byte_redo,
      wrlvl_byte_redo_r => wrlvl_byte_redo_r,
      wrlvl_rank_done => wrlvl_rank_done,
      \wrlvl_redo_corse_inc[2]_i_4_0\ => u_ddr_phy_wrcal_n_24,
      \wrlvl_redo_corse_inc_reg[2]_0\ => u_ddr_phy_wrcal_n_6
    );
mc_read_idle_r_i_1: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \^init_calib_complete_reg_rep__26_0\,
      O => \init_calib_complete_reg_rep__26_1\
    );
mem_reg_0_15_0_5_i_2: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^init_calib_complete_reg_rep__25_0\,
      I1 => mem_reg_0_15_12_17(520),
      O => \write_buffer.wr_buf_out_data_reg[455]\(1)
    );
\mem_reg_0_15_0_5_i_2__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^init_calib_complete_reg_rep__25_0\,
      I1 => mem_reg_0_15_12_17(524),
      O => \write_buffer.wr_buf_out_data_reg[487]\(1)
    );
mem_reg_0_15_0_5_i_3: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^init_calib_complete_reg_rep__25_0\,
      I1 => mem_reg_0_15_12_17(512),
      O => \write_buffer.wr_buf_out_data_reg[455]\(0)
    );
\mem_reg_0_15_0_5_i_3__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^init_calib_complete_reg_rep__25_0\,
      I1 => mem_reg_0_15_12_17(516),
      O => \write_buffer.wr_buf_out_data_reg[487]\(0)
    );
mem_reg_0_15_0_5_i_4: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^init_calib_complete_reg_rep__25_0\,
      I1 => mem_reg_0_15_12_17(536),
      O => \write_buffer.wr_buf_out_data_reg[455]\(3)
    );
\mem_reg_0_15_0_5_i_4__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^init_calib_complete_reg_rep__25_0\,
      I1 => mem_reg_0_15_12_17(540),
      O => \write_buffer.wr_buf_out_data_reg[487]\(3)
    );
mem_reg_0_15_0_5_i_5: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^init_calib_complete_reg_rep__25_0\,
      I1 => mem_reg_0_15_12_17(528),
      O => \write_buffer.wr_buf_out_data_reg[455]\(2)
    );
\mem_reg_0_15_0_5_i_5__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^init_calib_complete_reg_rep__25_0\,
      I1 => mem_reg_0_15_12_17(532),
      O => \write_buffer.wr_buf_out_data_reg[487]\(2)
    );
mem_reg_0_15_0_5_i_6: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^init_calib_complete_reg_rep__25_0\,
      I1 => mem_reg_0_15_12_17(552),
      O => \write_buffer.wr_buf_out_data_reg[455]\(5)
    );
\mem_reg_0_15_0_5_i_6__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^init_calib_complete_reg_rep__26_0\,
      I1 => mem_reg_0_15_12_17(556),
      O => \write_buffer.wr_buf_out_data_reg[487]\(5)
    );
mem_reg_0_15_0_5_i_7: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^init_calib_complete_reg_rep__25_0\,
      I1 => mem_reg_0_15_12_17(544),
      O => \write_buffer.wr_buf_out_data_reg[455]\(4)
    );
\mem_reg_0_15_0_5_i_7__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^init_calib_complete_reg_rep__25_0\,
      I1 => mem_reg_0_15_12_17(548),
      O => \write_buffer.wr_buf_out_data_reg[487]\(4)
    );
mem_reg_0_15_12_17_i_1: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \init_calib_complete_reg_rep__14_n_0\,
      I1 => mc_cas_n(0),
      O => d_in(12)
    );
\mem_reg_0_15_12_17_i_1__3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^init_calib_complete_reg_rep__25_0\,
      I1 => mem_reg_0_15_12_17(553),
      O => \write_buffer.wr_buf_out_data_reg[463]\(5)
    );
\mem_reg_0_15_12_17_i_1__4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^init_calib_complete_reg_rep__25_0\,
      I1 => mem_reg_0_15_12_17(554),
      O => \write_buffer.wr_buf_out_data_reg[471]\(5)
    );
\mem_reg_0_15_12_17_i_1__5\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^init_calib_complete_reg_rep__25_0\,
      I1 => mem_reg_0_15_12_17(555),
      O => \write_buffer.wr_buf_out_data_reg[479]\(5)
    );
\mem_reg_0_15_12_17_i_1__6\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^init_calib_complete_reg_rep__26_0\,
      I1 => mem_reg_0_15_12_17(557),
      O => \write_buffer.wr_buf_out_data_reg[495]\(5)
    );
\mem_reg_0_15_12_17_i_1__7\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^init_calib_complete_reg_rep__26_0\,
      I1 => mem_reg_0_15_12_17(558),
      O => \write_buffer.wr_buf_out_data_reg[503]\(5)
    );
\mem_reg_0_15_12_17_i_1__8\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^init_calib_complete_reg_rep__26_0\,
      I1 => mem_reg_0_15_12_17(559),
      O => \write_buffer.wr_buf_out_data_reg[511]\(5)
    );
\mem_reg_0_15_12_17_i_2__2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^init_calib_complete_reg_rep__25_0\,
      I1 => mem_reg_0_15_12_17(545),
      O => \write_buffer.wr_buf_out_data_reg[463]\(4)
    );
\mem_reg_0_15_12_17_i_2__3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^init_calib_complete_reg_rep__25_0\,
      I1 => mem_reg_0_15_12_17(546),
      O => \write_buffer.wr_buf_out_data_reg[471]\(4)
    );
\mem_reg_0_15_12_17_i_2__4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^init_calib_complete_reg_rep__25_0\,
      I1 => mem_reg_0_15_12_17(547),
      O => \write_buffer.wr_buf_out_data_reg[479]\(4)
    );
\mem_reg_0_15_12_17_i_2__5\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^init_calib_complete_reg_rep__25_0\,
      I1 => mem_reg_0_15_12_17(549),
      O => \write_buffer.wr_buf_out_data_reg[495]\(4)
    );
\mem_reg_0_15_12_17_i_2__6\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^init_calib_complete_reg_rep__25_0\,
      I1 => mem_reg_0_15_12_17(550),
      O => \write_buffer.wr_buf_out_data_reg[503]\(4)
    );
\mem_reg_0_15_12_17_i_2__7\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^init_calib_complete_reg_rep__25_0\,
      I1 => mem_reg_0_15_12_17(551),
      O => \write_buffer.wr_buf_out_data_reg[511]\(4)
    );
\mem_reg_0_15_12_17_i_3__1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^init_calib_complete_reg_rep__26_0\,
      I1 => mem_reg_0_15_12_17(569),
      O => \write_buffer.wr_buf_out_data_reg[463]\(7)
    );
\mem_reg_0_15_12_17_i_3__2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^init_calib_complete_reg_rep__26_0\,
      I1 => mem_reg_0_15_12_17(570),
      O => \write_buffer.wr_buf_out_data_reg[471]\(7)
    );
\mem_reg_0_15_12_17_i_3__3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^init_calib_complete_reg_rep__26_0\,
      I1 => mem_reg_0_15_12_17(571),
      O => \write_buffer.wr_buf_out_data_reg[479]\(7)
    );
\mem_reg_0_15_12_17_i_3__4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^init_calib_complete_reg_rep__26_0\,
      I1 => mem_reg_0_15_12_17(573),
      O => \write_buffer.wr_buf_out_data_reg[495]\(7)
    );
\mem_reg_0_15_12_17_i_3__5\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^init_calib_complete_reg_rep__26_0\,
      I1 => mem_reg_0_15_12_17(574),
      O => \write_buffer.wr_buf_out_data_reg[503]\(7)
    );
\mem_reg_0_15_12_17_i_3__6\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^init_calib_complete_reg_rep__26_0\,
      I1 => mem_reg_0_15_12_17(575),
      O => \write_buffer.wr_buf_out_data_reg[511]\(7)
    );
\mem_reg_0_15_12_17_i_4__1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^init_calib_complete_reg_rep__26_0\,
      I1 => mem_reg_0_15_12_17(561),
      O => \write_buffer.wr_buf_out_data_reg[463]\(6)
    );
\mem_reg_0_15_12_17_i_4__2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^init_calib_complete_reg_rep__26_0\,
      I1 => mem_reg_0_15_12_17(562),
      O => \write_buffer.wr_buf_out_data_reg[471]\(6)
    );
\mem_reg_0_15_12_17_i_4__3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^init_calib_complete_reg_rep__26_0\,
      I1 => mem_reg_0_15_12_17(563),
      O => \write_buffer.wr_buf_out_data_reg[479]\(6)
    );
\mem_reg_0_15_12_17_i_4__4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^init_calib_complete_reg_rep__26_0\,
      I1 => mem_reg_0_15_12_17(565),
      O => \write_buffer.wr_buf_out_data_reg[495]\(6)
    );
\mem_reg_0_15_12_17_i_4__5\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^init_calib_complete_reg_rep__26_0\,
      I1 => mem_reg_0_15_12_17(566),
      O => \write_buffer.wr_buf_out_data_reg[503]\(6)
    );
\mem_reg_0_15_12_17_i_4__6\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^init_calib_complete_reg_rep__26_0\,
      I1 => mem_reg_0_15_12_17(567),
      O => \write_buffer.wr_buf_out_data_reg[511]\(6)
    );
\mem_reg_0_15_6_11_i_1__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^init_calib_complete_reg_rep__25_0\,
      I1 => mem_reg_0_15_12_17(521),
      O => \write_buffer.wr_buf_out_data_reg[463]\(1)
    );
\mem_reg_0_15_6_11_i_1__1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^init_calib_complete_reg_rep__25_0\,
      I1 => mem_reg_0_15_12_17(522),
      O => \write_buffer.wr_buf_out_data_reg[471]\(1)
    );
\mem_reg_0_15_6_11_i_1__2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^init_calib_complete_reg_rep__25_0\,
      I1 => mem_reg_0_15_12_17(523),
      O => \write_buffer.wr_buf_out_data_reg[479]\(1)
    );
\mem_reg_0_15_6_11_i_1__3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^init_calib_complete_reg_rep__25_0\,
      I1 => mem_reg_0_15_12_17(525),
      O => \write_buffer.wr_buf_out_data_reg[495]\(1)
    );
\mem_reg_0_15_6_11_i_1__4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^init_calib_complete_reg_rep__25_0\,
      I1 => mem_reg_0_15_12_17(526),
      O => \write_buffer.wr_buf_out_data_reg[503]\(1)
    );
\mem_reg_0_15_6_11_i_1__5\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^init_calib_complete_reg_rep__25_0\,
      I1 => mem_reg_0_15_12_17(527),
      O => \write_buffer.wr_buf_out_data_reg[511]\(1)
    );
\mem_reg_0_15_6_11_i_1__6\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^init_calib_complete_reg_rep__26_0\,
      I1 => mem_reg_0_15_12_17(568),
      O => \write_buffer.wr_buf_out_data_reg[455]\(7)
    );
\mem_reg_0_15_6_11_i_1__7\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^init_calib_complete_reg_rep__26_0\,
      I1 => mem_reg_0_15_12_17(572),
      O => \write_buffer.wr_buf_out_data_reg[487]\(7)
    );
\mem_reg_0_15_6_11_i_2__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^init_calib_complete_reg_rep__25_0\,
      I1 => mem_reg_0_15_12_17(513),
      O => \write_buffer.wr_buf_out_data_reg[463]\(0)
    );
\mem_reg_0_15_6_11_i_2__1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^init_calib_complete_reg_rep__25_0\,
      I1 => mem_reg_0_15_12_17(514),
      O => \write_buffer.wr_buf_out_data_reg[471]\(0)
    );
\mem_reg_0_15_6_11_i_2__2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^init_calib_complete_reg_rep__25_0\,
      I1 => mem_reg_0_15_12_17(515),
      O => \write_buffer.wr_buf_out_data_reg[479]\(0)
    );
\mem_reg_0_15_6_11_i_2__3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^init_calib_complete_reg_rep__25_0\,
      I1 => mem_reg_0_15_12_17(517),
      O => \write_buffer.wr_buf_out_data_reg[495]\(0)
    );
\mem_reg_0_15_6_11_i_2__4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^init_calib_complete_reg_rep__25_0\,
      I1 => mem_reg_0_15_12_17(518),
      O => \write_buffer.wr_buf_out_data_reg[503]\(0)
    );
\mem_reg_0_15_6_11_i_2__5\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^init_calib_complete_reg_rep__25_0\,
      I1 => mem_reg_0_15_12_17(519),
      O => \write_buffer.wr_buf_out_data_reg[511]\(0)
    );
\mem_reg_0_15_6_11_i_2__6\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^init_calib_complete_reg_rep__26_0\,
      I1 => mem_reg_0_15_12_17(560),
      O => \write_buffer.wr_buf_out_data_reg[455]\(6)
    );
\mem_reg_0_15_6_11_i_2__7\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^init_calib_complete_reg_rep__26_0\,
      I1 => mem_reg_0_15_12_17(564),
      O => \write_buffer.wr_buf_out_data_reg[487]\(6)
    );
\mem_reg_0_15_6_11_i_3__2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^init_calib_complete_reg_rep__25_0\,
      I1 => mem_reg_0_15_12_17(537),
      O => \write_buffer.wr_buf_out_data_reg[463]\(3)
    );
\mem_reg_0_15_6_11_i_3__3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^init_calib_complete_reg_rep__25_0\,
      I1 => mem_reg_0_15_12_17(538),
      O => \write_buffer.wr_buf_out_data_reg[471]\(3)
    );
\mem_reg_0_15_6_11_i_3__4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^init_calib_complete_reg_rep__25_0\,
      I1 => mem_reg_0_15_12_17(539),
      O => \write_buffer.wr_buf_out_data_reg[479]\(3)
    );
\mem_reg_0_15_6_11_i_3__5\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^init_calib_complete_reg_rep__25_0\,
      I1 => mem_reg_0_15_12_17(541),
      O => \write_buffer.wr_buf_out_data_reg[495]\(3)
    );
\mem_reg_0_15_6_11_i_3__6\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^init_calib_complete_reg_rep__25_0\,
      I1 => mem_reg_0_15_12_17(542),
      O => \write_buffer.wr_buf_out_data_reg[503]\(3)
    );
\mem_reg_0_15_6_11_i_3__7\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^init_calib_complete_reg_rep__25_0\,
      I1 => mem_reg_0_15_12_17(543),
      O => \write_buffer.wr_buf_out_data_reg[511]\(3)
    );
\mem_reg_0_15_6_11_i_4__2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^init_calib_complete_reg_rep__25_0\,
      I1 => mem_reg_0_15_12_17(529),
      O => \write_buffer.wr_buf_out_data_reg[463]\(2)
    );
\mem_reg_0_15_6_11_i_4__3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^init_calib_complete_reg_rep__25_0\,
      I1 => mem_reg_0_15_12_17(530),
      O => \write_buffer.wr_buf_out_data_reg[471]\(2)
    );
\mem_reg_0_15_6_11_i_4__4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^init_calib_complete_reg_rep__25_0\,
      I1 => mem_reg_0_15_12_17(531),
      O => \write_buffer.wr_buf_out_data_reg[479]\(2)
    );
\mem_reg_0_15_6_11_i_4__5\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^init_calib_complete_reg_rep__25_0\,
      I1 => mem_reg_0_15_12_17(533),
      O => \write_buffer.wr_buf_out_data_reg[495]\(2)
    );
\mem_reg_0_15_6_11_i_4__6\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^init_calib_complete_reg_rep__25_0\,
      I1 => mem_reg_0_15_12_17(534),
      O => \write_buffer.wr_buf_out_data_reg[503]\(2)
    );
\mem_reg_0_15_6_11_i_4__7\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^init_calib_complete_reg_rep__25_0\,
      I1 => mem_reg_0_15_12_17(535),
      O => \write_buffer.wr_buf_out_data_reg[511]\(2)
    );
\phaser_in_gen.phaser_in_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000F010"
    )
        port map (
      I0 => \^calib_sel\(1),
      I1 => \^calib_sel\(0),
      I2 => \pi_dqs_found_lanes_r1_reg[0]_0\,
      I3 => calib_in_common,
      I4 => calib_zero_inputs(0),
      O => \calib_sel_reg[1]_7\
    );
\phaser_in_gen.phaser_in_i_10\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000F010"
    )
        port map (
      I0 => \^calib_sel\(1),
      I1 => \^calib_sel\(0),
      I2 => \pi_dqs_found_lanes_r1_reg[0]_1\(1),
      I3 => calib_in_common,
      I4 => calib_zero_inputs(0),
      O => COUNTERLOADVAL(1)
    );
\phaser_in_gen.phaser_in_i_10__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000CC40"
    )
        port map (
      I0 => \^calib_sel\(1),
      I1 => \pi_dqs_found_lanes_r1_reg[0]_1\(1),
      I2 => \^calib_sel\(0),
      I3 => calib_in_common,
      I4 => calib_zero_inputs(0),
      O => \calib_sel_reg[1]_48\(1)
    );
\phaser_in_gen.phaser_in_i_10__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000CC08"
    )
        port map (
      I0 => \^calib_sel\(1),
      I1 => \pi_dqs_found_lanes_r1_reg[0]_1\(1),
      I2 => \^calib_sel\(0),
      I3 => calib_in_common,
      I4 => calib_zero_inputs(0),
      O => \calib_sel_reg[1]_49\(1)
    );
\phaser_in_gen.phaser_in_i_10__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000AA80"
    )
        port map (
      I0 => \pi_dqs_found_lanes_r1_reg[0]_1\(1),
      I1 => \^calib_sel\(0),
      I2 => \^calib_sel\(1),
      I3 => calib_in_common,
      I4 => calib_zero_inputs(0),
      O => \pi_stg2_reg_l_reg[5]\(1)
    );
\phaser_in_gen.phaser_in_i_10__3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000F010"
    )
        port map (
      I0 => \^calib_sel\(1),
      I1 => \^calib_sel\(0),
      I2 => \pi_dqs_found_lanes_r1_reg[0]_1\(1),
      I3 => calib_in_common,
      I4 => calib_zero_inputs(2),
      O => \calib_sel_reg[1]_50\(1)
    );
\phaser_in_gen.phaser_in_i_10__4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000CC40"
    )
        port map (
      I0 => \^calib_sel\(1),
      I1 => \pi_dqs_found_lanes_r1_reg[0]_1\(1),
      I2 => \^calib_sel\(0),
      I3 => calib_in_common,
      I4 => calib_zero_inputs(2),
      O => \calib_sel_reg[1]_51\(1)
    );
\phaser_in_gen.phaser_in_i_10__5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000CC08"
    )
        port map (
      I0 => \^calib_sel\(1),
      I1 => \pi_dqs_found_lanes_r1_reg[0]_1\(1),
      I2 => \^calib_sel\(0),
      I3 => calib_in_common,
      I4 => calib_zero_inputs(2),
      O => \calib_sel_reg[1]_52\(1)
    );
\phaser_in_gen.phaser_in_i_10__6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000AA80"
    )
        port map (
      I0 => \pi_dqs_found_lanes_r1_reg[0]_1\(1),
      I1 => \^calib_sel\(0),
      I2 => \^calib_sel\(1),
      I3 => calib_in_common,
      I4 => calib_zero_inputs(2),
      O => \pi_stg2_reg_l_reg[5]_0\(1)
    );
\phaser_in_gen.phaser_in_i_11\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000F010"
    )
        port map (
      I0 => \^calib_sel\(1),
      I1 => \^calib_sel\(0),
      I2 => \pi_dqs_found_lanes_r1_reg[0]_1\(0),
      I3 => calib_in_common,
      I4 => calib_zero_inputs(0),
      O => COUNTERLOADVAL(0)
    );
\phaser_in_gen.phaser_in_i_11__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000CC40"
    )
        port map (
      I0 => \^calib_sel\(1),
      I1 => \pi_dqs_found_lanes_r1_reg[0]_1\(0),
      I2 => \^calib_sel\(0),
      I3 => calib_in_common,
      I4 => calib_zero_inputs(0),
      O => \calib_sel_reg[1]_48\(0)
    );
\phaser_in_gen.phaser_in_i_11__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000CC08"
    )
        port map (
      I0 => \^calib_sel\(1),
      I1 => \pi_dqs_found_lanes_r1_reg[0]_1\(0),
      I2 => \^calib_sel\(0),
      I3 => calib_in_common,
      I4 => calib_zero_inputs(0),
      O => \calib_sel_reg[1]_49\(0)
    );
\phaser_in_gen.phaser_in_i_11__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000AA80"
    )
        port map (
      I0 => \pi_dqs_found_lanes_r1_reg[0]_1\(0),
      I1 => \^calib_sel\(0),
      I2 => \^calib_sel\(1),
      I3 => calib_in_common,
      I4 => calib_zero_inputs(0),
      O => \pi_stg2_reg_l_reg[5]\(0)
    );
\phaser_in_gen.phaser_in_i_11__3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000F010"
    )
        port map (
      I0 => \^calib_sel\(1),
      I1 => \^calib_sel\(0),
      I2 => \pi_dqs_found_lanes_r1_reg[0]_1\(0),
      I3 => calib_in_common,
      I4 => calib_zero_inputs(2),
      O => \calib_sel_reg[1]_50\(0)
    );
\phaser_in_gen.phaser_in_i_11__4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000CC40"
    )
        port map (
      I0 => \^calib_sel\(1),
      I1 => \pi_dqs_found_lanes_r1_reg[0]_1\(0),
      I2 => \^calib_sel\(0),
      I3 => calib_in_common,
      I4 => calib_zero_inputs(2),
      O => \calib_sel_reg[1]_51\(0)
    );
\phaser_in_gen.phaser_in_i_11__5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000CC08"
    )
        port map (
      I0 => \^calib_sel\(1),
      I1 => \pi_dqs_found_lanes_r1_reg[0]_1\(0),
      I2 => \^calib_sel\(0),
      I3 => calib_in_common,
      I4 => calib_zero_inputs(2),
      O => \calib_sel_reg[1]_52\(0)
    );
\phaser_in_gen.phaser_in_i_11__6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000AA80"
    )
        port map (
      I0 => \pi_dqs_found_lanes_r1_reg[0]_1\(0),
      I1 => \^calib_sel\(0),
      I2 => \^calib_sel\(1),
      I3 => calib_in_common,
      I4 => calib_zero_inputs(2),
      O => \pi_stg2_reg_l_reg[5]_0\(0)
    );
\phaser_in_gen.phaser_in_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000CC40"
    )
        port map (
      I0 => \^calib_sel\(1),
      I1 => \pi_dqs_found_lanes_r1_reg[0]_0\,
      I2 => \^calib_sel\(0),
      I3 => calib_in_common,
      I4 => calib_zero_inputs(0),
      O => \calib_sel_reg[1]_17\
    );
\phaser_in_gen.phaser_in_i_1__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000CC08"
    )
        port map (
      I0 => \^calib_sel\(1),
      I1 => \pi_dqs_found_lanes_r1_reg[0]_0\,
      I2 => \^calib_sel\(0),
      I3 => calib_in_common,
      I4 => calib_zero_inputs(0),
      O => \calib_sel_reg[1]_23\
    );
\phaser_in_gen.phaser_in_i_1__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000AA80"
    )
        port map (
      I0 => \pi_dqs_found_lanes_r1_reg[0]_0\,
      I1 => \^calib_sel\(0),
      I2 => \^calib_sel\(1),
      I3 => calib_in_common,
      I4 => calib_zero_inputs(0),
      O => pi_stg2_load_reg
    );
\phaser_in_gen.phaser_in_i_1__3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000F010"
    )
        port map (
      I0 => \^calib_sel\(1),
      I1 => \^calib_sel\(0),
      I2 => \pi_dqs_found_lanes_r1_reg[0]_0\,
      I3 => calib_in_common,
      I4 => calib_zero_inputs(2),
      O => \calib_sel_reg[1]_31\
    );
\phaser_in_gen.phaser_in_i_1__4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000CC40"
    )
        port map (
      I0 => \^calib_sel\(1),
      I1 => \pi_dqs_found_lanes_r1_reg[0]_0\,
      I2 => \^calib_sel\(0),
      I3 => calib_in_common,
      I4 => calib_zero_inputs(2),
      O => \calib_sel_reg[1]_41\
    );
\phaser_in_gen.phaser_in_i_1__5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000CC08"
    )
        port map (
      I0 => \^calib_sel\(1),
      I1 => \pi_dqs_found_lanes_r1_reg[0]_0\,
      I2 => \^calib_sel\(0),
      I3 => calib_in_common,
      I4 => calib_zero_inputs(2),
      O => \calib_sel_reg[1]_47\
    );
\phaser_in_gen.phaser_in_i_1__6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000AA80"
    )
        port map (
      I0 => \pi_dqs_found_lanes_r1_reg[0]_0\,
      I1 => \^calib_sel\(0),
      I2 => \^calib_sel\(1),
      I3 => calib_in_common,
      I4 => calib_zero_inputs(2),
      O => pi_stg2_load_reg_0
    );
\phaser_in_gen.phaser_in_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"00F1"
    )
        port map (
      I0 => \^calib_sel\(1),
      I1 => \^calib_sel\(0),
      I2 => calib_in_common,
      I3 => calib_zero_inputs(0),
      O => \calib_sel_reg[1]_0\
    );
\phaser_in_gen.phaser_in_i_2__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"00F8"
    )
        port map (
      I0 => \^calib_sel\(1),
      I1 => \^calib_sel\(0),
      I2 => calib_in_common,
      I3 => calib_zero_inputs(0),
      O => \calib_sel_reg[1]_9\
    );
\phaser_in_gen.phaser_in_i_2__1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"00F2"
    )
        port map (
      I0 => \^calib_sel\(1),
      I1 => \^calib_sel\(0),
      I2 => calib_in_common,
      I3 => calib_zero_inputs(0),
      O => \calib_sel_reg[1]_11\
    );
\phaser_in_gen.phaser_in_i_2__2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"00F2"
    )
        port map (
      I0 => \^calib_sel\(0),
      I1 => \^calib_sel\(1),
      I2 => calib_in_common,
      I3 => calib_zero_inputs(0),
      O => \calib_sel_reg[0]_0\
    );
\phaser_in_gen.phaser_in_i_2__3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"00F1"
    )
        port map (
      I0 => \^calib_sel\(1),
      I1 => \^calib_sel\(0),
      I2 => calib_in_common,
      I3 => calib_zero_inputs(2),
      O => \calib_sel_reg[1]_24\
    );
\phaser_in_gen.phaser_in_i_2__4\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"00F8"
    )
        port map (
      I0 => \^calib_sel\(1),
      I1 => \^calib_sel\(0),
      I2 => calib_in_common,
      I3 => calib_zero_inputs(2),
      O => \calib_sel_reg[1]_33\
    );
\phaser_in_gen.phaser_in_i_2__5\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"00F2"
    )
        port map (
      I0 => \^calib_sel\(1),
      I1 => \^calib_sel\(0),
      I2 => calib_in_common,
      I3 => calib_zero_inputs(2),
      O => \calib_sel_reg[1]_35\
    );
\phaser_in_gen.phaser_in_i_2__6\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"00F2"
    )
        port map (
      I0 => \^calib_sel\(0),
      I1 => \^calib_sel\(1),
      I2 => calib_in_common,
      I3 => calib_zero_inputs(2),
      O => \calib_sel_reg[0]_4\
    );
\phaser_in_gen.phaser_in_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000F010"
    )
        port map (
      I0 => \^calib_sel\(1),
      I1 => \^calib_sel\(0),
      I2 => \out\,
      I3 => calib_in_common,
      I4 => calib_zero_inputs(0),
      O => \calib_sel_reg[1]_1\
    );
\phaser_in_gen.phaser_in_i_3__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000CC40"
    )
        port map (
      I0 => \^calib_sel\(1),
      I1 => \out\,
      I2 => \^calib_sel\(0),
      I3 => calib_in_common,
      I4 => calib_zero_inputs(0),
      O => \calib_sel_reg[1]_15\
    );
\phaser_in_gen.phaser_in_i_3__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000CC08"
    )
        port map (
      I0 => \^calib_sel\(1),
      I1 => \out\,
      I2 => \^calib_sel\(0),
      I3 => calib_in_common,
      I4 => calib_zero_inputs(0),
      O => \calib_sel_reg[1]_21\
    );
\phaser_in_gen.phaser_in_i_3__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000AA80"
    )
        port map (
      I0 => \out\,
      I1 => \^calib_sel\(0),
      I2 => \^calib_sel\(1),
      I3 => calib_in_common,
      I4 => calib_zero_inputs(0),
      O => \calib_sel_reg[0]_2\
    );
\phaser_in_gen.phaser_in_i_3__3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000F010"
    )
        port map (
      I0 => \^calib_sel\(1),
      I1 => \^calib_sel\(0),
      I2 => \out\,
      I3 => calib_in_common,
      I4 => calib_zero_inputs(2),
      O => \calib_sel_reg[1]_25\
    );
\phaser_in_gen.phaser_in_i_3__4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000CC40"
    )
        port map (
      I0 => \^calib_sel\(1),
      I1 => \out\,
      I2 => \^calib_sel\(0),
      I3 => calib_in_common,
      I4 => calib_zero_inputs(2),
      O => \calib_sel_reg[1]_39\
    );
\phaser_in_gen.phaser_in_i_3__5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000CC08"
    )
        port map (
      I0 => \^calib_sel\(1),
      I1 => \out\,
      I2 => \^calib_sel\(0),
      I3 => calib_in_common,
      I4 => calib_zero_inputs(2),
      O => \calib_sel_reg[1]_45\
    );
\phaser_in_gen.phaser_in_i_3__6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000AA80"
    )
        port map (
      I0 => \out\,
      I1 => \^calib_sel\(0),
      I2 => \^calib_sel\(1),
      I3 => calib_in_common,
      I4 => calib_zero_inputs(2),
      O => \calib_sel_reg[0]_6\
    );
\phaser_in_gen.phaser_in_i_4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000F010"
    )
        port map (
      I0 => \^calib_sel\(1),
      I1 => \^calib_sel\(0),
      I2 => \pi_dqs_found_lanes_r1_reg[0]\,
      I3 => calib_in_common,
      I4 => calib_zero_inputs(0),
      O => \calib_sel_reg[1]_6\
    );
\phaser_in_gen.phaser_in_i_4__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000CC40"
    )
        port map (
      I0 => \^calib_sel\(1),
      I1 => \pi_dqs_found_lanes_r1_reg[0]\,
      I2 => \^calib_sel\(0),
      I3 => calib_in_common,
      I4 => calib_zero_inputs(0),
      O => \calib_sel_reg[1]_16\
    );
\phaser_in_gen.phaser_in_i_4__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000CC08"
    )
        port map (
      I0 => \^calib_sel\(1),
      I1 => \pi_dqs_found_lanes_r1_reg[0]\,
      I2 => \^calib_sel\(0),
      I3 => calib_in_common,
      I4 => calib_zero_inputs(0),
      O => \calib_sel_reg[1]_22\
    );
\phaser_in_gen.phaser_in_i_4__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000AA80"
    )
        port map (
      I0 => \pi_dqs_found_lanes_r1_reg[0]\,
      I1 => \^calib_sel\(0),
      I2 => \^calib_sel\(1),
      I3 => calib_in_common,
      I4 => calib_zero_inputs(0),
      O => \calib_sel_reg[0]_3\
    );
\phaser_in_gen.phaser_in_i_4__3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000F010"
    )
        port map (
      I0 => \^calib_sel\(1),
      I1 => \^calib_sel\(0),
      I2 => \pi_dqs_found_lanes_r1_reg[0]\,
      I3 => calib_in_common,
      I4 => calib_zero_inputs(2),
      O => \calib_sel_reg[1]_30\
    );
\phaser_in_gen.phaser_in_i_4__4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000CC40"
    )
        port map (
      I0 => \^calib_sel\(1),
      I1 => \pi_dqs_found_lanes_r1_reg[0]\,
      I2 => \^calib_sel\(0),
      I3 => calib_in_common,
      I4 => calib_zero_inputs(2),
      O => \calib_sel_reg[1]_40\
    );
\phaser_in_gen.phaser_in_i_4__5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000CC08"
    )
        port map (
      I0 => \^calib_sel\(1),
      I1 => \pi_dqs_found_lanes_r1_reg[0]\,
      I2 => \^calib_sel\(0),
      I3 => calib_in_common,
      I4 => calib_zero_inputs(2),
      O => \calib_sel_reg[1]_46\
    );
\phaser_in_gen.phaser_in_i_4__6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000AA80"
    )
        port map (
      I0 => \pi_dqs_found_lanes_r1_reg[0]\,
      I1 => \^calib_sel\(0),
      I2 => \^calib_sel\(1),
      I3 => calib_in_common,
      I4 => calib_zero_inputs(2),
      O => \calib_sel_reg[0]_7\
    );
\phaser_in_gen.phaser_in_i_5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000F010"
    )
        port map (
      I0 => \^calib_sel\(1),
      I1 => \^calib_sel\(0),
      I2 => ififo_rst_reg(0),
      I3 => calib_in_common,
      I4 => calib_zero_inputs(0),
      O => \calib_sel_reg[1]_5\
    );
\phaser_in_gen.phaser_in_i_5__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000CC40"
    )
        port map (
      I0 => \^calib_sel\(1),
      I1 => ififo_rst_reg(0),
      I2 => \^calib_sel\(0),
      I3 => calib_in_common,
      I4 => calib_zero_inputs(0),
      O => \calib_sel_reg[1]_14\
    );
\phaser_in_gen.phaser_in_i_5__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000CC08"
    )
        port map (
      I0 => \^calib_sel\(1),
      I1 => ififo_rst_reg(0),
      I2 => \^calib_sel\(0),
      I3 => calib_in_common,
      I4 => calib_zero_inputs(0),
      O => \calib_sel_reg[1]_20\
    );
\phaser_in_gen.phaser_in_i_5__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000AA80"
    )
        port map (
      I0 => ififo_rst_reg(0),
      I1 => \^calib_sel\(0),
      I2 => \^calib_sel\(1),
      I3 => calib_in_common,
      I4 => calib_zero_inputs(0),
      O => \pi_rst_stg1_cal_reg[0]\
    );
\phaser_in_gen.phaser_in_i_5__3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000F010"
    )
        port map (
      I0 => \^calib_sel\(1),
      I1 => \^calib_sel\(0),
      I2 => ififo_rst_reg(1),
      I3 => calib_in_common,
      I4 => calib_zero_inputs(2),
      O => \calib_sel_reg[1]_29\
    );
\phaser_in_gen.phaser_in_i_5__4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000CC40"
    )
        port map (
      I0 => \^calib_sel\(1),
      I1 => ififo_rst_reg(1),
      I2 => \^calib_sel\(0),
      I3 => calib_in_common,
      I4 => calib_zero_inputs(2),
      O => \calib_sel_reg[1]_38\
    );
\phaser_in_gen.phaser_in_i_5__5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000CC08"
    )
        port map (
      I0 => \^calib_sel\(1),
      I1 => ififo_rst_reg(1),
      I2 => \^calib_sel\(0),
      I3 => calib_in_common,
      I4 => calib_zero_inputs(2),
      O => \calib_sel_reg[1]_44\
    );
\phaser_in_gen.phaser_in_i_5__6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000AA80"
    )
        port map (
      I0 => ififo_rst_reg(1),
      I1 => \^calib_sel\(0),
      I2 => \^calib_sel\(1),
      I3 => calib_in_common,
      I4 => calib_zero_inputs(2),
      O => \pi_rst_stg1_cal_reg[2]\
    );
\phaser_in_gen.phaser_in_i_6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000F010"
    )
        port map (
      I0 => \^calib_sel\(1),
      I1 => \^calib_sel\(0),
      I2 => \pi_dqs_found_lanes_r1_reg[0]_1\(5),
      I3 => calib_in_common,
      I4 => calib_zero_inputs(0),
      O => COUNTERLOADVAL(5)
    );
\phaser_in_gen.phaser_in_i_6__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000CC40"
    )
        port map (
      I0 => \^calib_sel\(1),
      I1 => \pi_dqs_found_lanes_r1_reg[0]_1\(5),
      I2 => \^calib_sel\(0),
      I3 => calib_in_common,
      I4 => calib_zero_inputs(0),
      O => \calib_sel_reg[1]_48\(5)
    );
\phaser_in_gen.phaser_in_i_6__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000CC08"
    )
        port map (
      I0 => \^calib_sel\(1),
      I1 => \pi_dqs_found_lanes_r1_reg[0]_1\(5),
      I2 => \^calib_sel\(0),
      I3 => calib_in_common,
      I4 => calib_zero_inputs(0),
      O => \calib_sel_reg[1]_49\(5)
    );
\phaser_in_gen.phaser_in_i_6__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000AA80"
    )
        port map (
      I0 => \pi_dqs_found_lanes_r1_reg[0]_1\(5),
      I1 => \^calib_sel\(0),
      I2 => \^calib_sel\(1),
      I3 => calib_in_common,
      I4 => calib_zero_inputs(0),
      O => \pi_stg2_reg_l_reg[5]\(5)
    );
\phaser_in_gen.phaser_in_i_6__3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000F010"
    )
        port map (
      I0 => \^calib_sel\(1),
      I1 => \^calib_sel\(0),
      I2 => \pi_dqs_found_lanes_r1_reg[0]_1\(5),
      I3 => calib_in_common,
      I4 => calib_zero_inputs(2),
      O => \calib_sel_reg[1]_50\(5)
    );
\phaser_in_gen.phaser_in_i_6__4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000CC40"
    )
        port map (
      I0 => \^calib_sel\(1),
      I1 => \pi_dqs_found_lanes_r1_reg[0]_1\(5),
      I2 => \^calib_sel\(0),
      I3 => calib_in_common,
      I4 => calib_zero_inputs(2),
      O => \calib_sel_reg[1]_51\(5)
    );
\phaser_in_gen.phaser_in_i_6__5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000CC08"
    )
        port map (
      I0 => \^calib_sel\(1),
      I1 => \pi_dqs_found_lanes_r1_reg[0]_1\(5),
      I2 => \^calib_sel\(0),
      I3 => calib_in_common,
      I4 => calib_zero_inputs(2),
      O => \calib_sel_reg[1]_52\(5)
    );
\phaser_in_gen.phaser_in_i_6__6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000AA80"
    )
        port map (
      I0 => \pi_dqs_found_lanes_r1_reg[0]_1\(5),
      I1 => \^calib_sel\(0),
      I2 => \^calib_sel\(1),
      I3 => calib_in_common,
      I4 => calib_zero_inputs(2),
      O => \pi_stg2_reg_l_reg[5]_0\(5)
    );
\phaser_in_gen.phaser_in_i_7\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000F010"
    )
        port map (
      I0 => \^calib_sel\(1),
      I1 => \^calib_sel\(0),
      I2 => \pi_dqs_found_lanes_r1_reg[0]_1\(4),
      I3 => calib_in_common,
      I4 => calib_zero_inputs(0),
      O => COUNTERLOADVAL(4)
    );
\phaser_in_gen.phaser_in_i_7__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000CC40"
    )
        port map (
      I0 => \^calib_sel\(1),
      I1 => \pi_dqs_found_lanes_r1_reg[0]_1\(4),
      I2 => \^calib_sel\(0),
      I3 => calib_in_common,
      I4 => calib_zero_inputs(0),
      O => \calib_sel_reg[1]_48\(4)
    );
\phaser_in_gen.phaser_in_i_7__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000CC08"
    )
        port map (
      I0 => \^calib_sel\(1),
      I1 => \pi_dqs_found_lanes_r1_reg[0]_1\(4),
      I2 => \^calib_sel\(0),
      I3 => calib_in_common,
      I4 => calib_zero_inputs(0),
      O => \calib_sel_reg[1]_49\(4)
    );
\phaser_in_gen.phaser_in_i_7__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000AA80"
    )
        port map (
      I0 => \pi_dqs_found_lanes_r1_reg[0]_1\(4),
      I1 => \^calib_sel\(0),
      I2 => \^calib_sel\(1),
      I3 => calib_in_common,
      I4 => calib_zero_inputs(0),
      O => \pi_stg2_reg_l_reg[5]\(4)
    );
\phaser_in_gen.phaser_in_i_7__3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000F010"
    )
        port map (
      I0 => \^calib_sel\(1),
      I1 => \^calib_sel\(0),
      I2 => \pi_dqs_found_lanes_r1_reg[0]_1\(4),
      I3 => calib_in_common,
      I4 => calib_zero_inputs(2),
      O => \calib_sel_reg[1]_50\(4)
    );
\phaser_in_gen.phaser_in_i_7__4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000CC40"
    )
        port map (
      I0 => \^calib_sel\(1),
      I1 => \pi_dqs_found_lanes_r1_reg[0]_1\(4),
      I2 => \^calib_sel\(0),
      I3 => calib_in_common,
      I4 => calib_zero_inputs(2),
      O => \calib_sel_reg[1]_51\(4)
    );
\phaser_in_gen.phaser_in_i_7__5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000CC08"
    )
        port map (
      I0 => \^calib_sel\(1),
      I1 => \pi_dqs_found_lanes_r1_reg[0]_1\(4),
      I2 => \^calib_sel\(0),
      I3 => calib_in_common,
      I4 => calib_zero_inputs(2),
      O => \calib_sel_reg[1]_52\(4)
    );
\phaser_in_gen.phaser_in_i_7__6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000AA80"
    )
        port map (
      I0 => \pi_dqs_found_lanes_r1_reg[0]_1\(4),
      I1 => \^calib_sel\(0),
      I2 => \^calib_sel\(1),
      I3 => calib_in_common,
      I4 => calib_zero_inputs(2),
      O => \pi_stg2_reg_l_reg[5]_0\(4)
    );
\phaser_in_gen.phaser_in_i_8\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000F010"
    )
        port map (
      I0 => \^calib_sel\(1),
      I1 => \^calib_sel\(0),
      I2 => \pi_dqs_found_lanes_r1_reg[0]_1\(3),
      I3 => calib_in_common,
      I4 => calib_zero_inputs(0),
      O => COUNTERLOADVAL(3)
    );
\phaser_in_gen.phaser_in_i_8__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000CC40"
    )
        port map (
      I0 => \^calib_sel\(1),
      I1 => \pi_dqs_found_lanes_r1_reg[0]_1\(3),
      I2 => \^calib_sel\(0),
      I3 => calib_in_common,
      I4 => calib_zero_inputs(0),
      O => \calib_sel_reg[1]_48\(3)
    );
\phaser_in_gen.phaser_in_i_8__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000CC08"
    )
        port map (
      I0 => \^calib_sel\(1),
      I1 => \pi_dqs_found_lanes_r1_reg[0]_1\(3),
      I2 => \^calib_sel\(0),
      I3 => calib_in_common,
      I4 => calib_zero_inputs(0),
      O => \calib_sel_reg[1]_49\(3)
    );
\phaser_in_gen.phaser_in_i_8__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000AA80"
    )
        port map (
      I0 => \pi_dqs_found_lanes_r1_reg[0]_1\(3),
      I1 => \^calib_sel\(0),
      I2 => \^calib_sel\(1),
      I3 => calib_in_common,
      I4 => calib_zero_inputs(0),
      O => \pi_stg2_reg_l_reg[5]\(3)
    );
\phaser_in_gen.phaser_in_i_8__3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000F010"
    )
        port map (
      I0 => \^calib_sel\(1),
      I1 => \^calib_sel\(0),
      I2 => \pi_dqs_found_lanes_r1_reg[0]_1\(3),
      I3 => calib_in_common,
      I4 => calib_zero_inputs(2),
      O => \calib_sel_reg[1]_50\(3)
    );
\phaser_in_gen.phaser_in_i_8__4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000CC40"
    )
        port map (
      I0 => \^calib_sel\(1),
      I1 => \pi_dqs_found_lanes_r1_reg[0]_1\(3),
      I2 => \^calib_sel\(0),
      I3 => calib_in_common,
      I4 => calib_zero_inputs(2),
      O => \calib_sel_reg[1]_51\(3)
    );
\phaser_in_gen.phaser_in_i_8__5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000CC08"
    )
        port map (
      I0 => \^calib_sel\(1),
      I1 => \pi_dqs_found_lanes_r1_reg[0]_1\(3),
      I2 => \^calib_sel\(0),
      I3 => calib_in_common,
      I4 => calib_zero_inputs(2),
      O => \calib_sel_reg[1]_52\(3)
    );
\phaser_in_gen.phaser_in_i_8__6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000AA80"
    )
        port map (
      I0 => \pi_dqs_found_lanes_r1_reg[0]_1\(3),
      I1 => \^calib_sel\(0),
      I2 => \^calib_sel\(1),
      I3 => calib_in_common,
      I4 => calib_zero_inputs(2),
      O => \pi_stg2_reg_l_reg[5]_0\(3)
    );
\phaser_in_gen.phaser_in_i_9\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000F010"
    )
        port map (
      I0 => \^calib_sel\(1),
      I1 => \^calib_sel\(0),
      I2 => \pi_dqs_found_lanes_r1_reg[0]_1\(2),
      I3 => calib_in_common,
      I4 => calib_zero_inputs(0),
      O => COUNTERLOADVAL(2)
    );
\phaser_in_gen.phaser_in_i_9__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000CC40"
    )
        port map (
      I0 => \^calib_sel\(1),
      I1 => \pi_dqs_found_lanes_r1_reg[0]_1\(2),
      I2 => \^calib_sel\(0),
      I3 => calib_in_common,
      I4 => calib_zero_inputs(0),
      O => \calib_sel_reg[1]_48\(2)
    );
\phaser_in_gen.phaser_in_i_9__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000CC08"
    )
        port map (
      I0 => \^calib_sel\(1),
      I1 => \pi_dqs_found_lanes_r1_reg[0]_1\(2),
      I2 => \^calib_sel\(0),
      I3 => calib_in_common,
      I4 => calib_zero_inputs(0),
      O => \calib_sel_reg[1]_49\(2)
    );
\phaser_in_gen.phaser_in_i_9__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000AA80"
    )
        port map (
      I0 => \pi_dqs_found_lanes_r1_reg[0]_1\(2),
      I1 => \^calib_sel\(0),
      I2 => \^calib_sel\(1),
      I3 => calib_in_common,
      I4 => calib_zero_inputs(0),
      O => \pi_stg2_reg_l_reg[5]\(2)
    );
\phaser_in_gen.phaser_in_i_9__3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000F010"
    )
        port map (
      I0 => \^calib_sel\(1),
      I1 => \^calib_sel\(0),
      I2 => \pi_dqs_found_lanes_r1_reg[0]_1\(2),
      I3 => calib_in_common,
      I4 => calib_zero_inputs(2),
      O => \calib_sel_reg[1]_50\(2)
    );
\phaser_in_gen.phaser_in_i_9__4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000CC40"
    )
        port map (
      I0 => \^calib_sel\(1),
      I1 => \pi_dqs_found_lanes_r1_reg[0]_1\(2),
      I2 => \^calib_sel\(0),
      I3 => calib_in_common,
      I4 => calib_zero_inputs(2),
      O => \calib_sel_reg[1]_51\(2)
    );
\phaser_in_gen.phaser_in_i_9__5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000CC08"
    )
        port map (
      I0 => \^calib_sel\(1),
      I1 => \pi_dqs_found_lanes_r1_reg[0]_1\(2),
      I2 => \^calib_sel\(0),
      I3 => calib_in_common,
      I4 => calib_zero_inputs(2),
      O => \calib_sel_reg[1]_52\(2)
    );
\phaser_in_gen.phaser_in_i_9__6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000AA80"
    )
        port map (
      I0 => \pi_dqs_found_lanes_r1_reg[0]_1\(2),
      I1 => \^calib_sel\(0),
      I2 => \^calib_sel\(1),
      I3 => calib_in_common,
      I4 => calib_zero_inputs(2),
      O => \pi_stg2_reg_l_reg[5]_0\(2)
    );
\phaser_out_i_2__7\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0040"
    )
        port map (
      I0 => calib_in_common,
      I1 => \^calib_sel\(1),
      I2 => \^calib_sel\(0),
      I3 => calib_zero_inputs(1),
      O => \gen_byte_sel_div2.calib_in_common_reg_4\
    );
\phaser_out_i_2__8\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0004"
    )
        port map (
      I0 => calib_in_common,
      I1 => \^calib_sel\(0),
      I2 => \^calib_sel\(1),
      I3 => calib_zero_inputs(1),
      O => \gen_byte_sel_div2.calib_in_common_reg_5\
    );
\phaser_out_i_2__9\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0004"
    )
        port map (
      I0 => calib_in_common,
      I1 => \^calib_sel\(1),
      I2 => \^calib_sel\(0),
      I3 => calib_zero_inputs(1),
      O => C_po_counter_read_en38_out
    );
phy_if_reset0: unisim.vcomponents.LUT3
    generic map(
      INIT => X"FE"
    )
        port map (
      I0 => phy_if_reset_w,
      I1 => reset_if,
      I2 => wrlvl_final_if_rst,
      O => \phy_if_reset0__0\
    );
phy_if_reset_reg: unisim.vcomponents.FDRE
     port map (
      C => \dout_o_reg[15]\,
      CE => '1',
      D => \phy_if_reset0__0\,
      Q => phy_if_reset,
      R => '0'
    );
pi_en_stg2_f: unisim.vcomponents.LUT3
    generic map(
      INIT => X"FE"
    )
        port map (
      I0 => tempmon_pi_f_en_r,
      I1 => rdlvl_pi_stg2_f_en,
      I2 => prbs_pi_stg2_f_en,
      O => pi_fine_enable
    );
pi_stg2_f_incdec: unisim.vcomponents.LUT3
    generic map(
      INIT => X"FE"
    )
        port map (
      I0 => tempmon_pi_f_inc_r,
      I1 => rdlvl_pi_stg2_f_incdec,
      I2 => prbs_pi_stg2_f_incdec,
      O => pi_fine_inc
    );
\po_counter_read_val[8]_i_1__1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \^calib_sel\(0),
      I1 => \^calib_sel\(1),
      O => SR(0)
    );
po_en_stg2_f0: unisim.vcomponents.LUT3
    generic map(
      INIT => X"FE"
    )
        port map (
      I0 => dqs_po_en_stg2_f,
      I1 => cmd_po_en_stg2_f,
      I2 => ck_po_stg2_f_en,
      O => po_enstg2_f(2)
    );
prbs_rdlvl_done_r1_reg: unisim.vcomponents.FDRE
     port map (
      C => \dout_o_reg[15]\,
      CE => '1',
      D => \ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_7\,
      Q => prbs_rdlvl_done_r1,
      R => '0'
    );
rdlvl_stg1_done_r1_reg: unisim.vcomponents.FDRE
     port map (
      C => \dout_o_reg[15]\,
      CE => '1',
      D => \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_10\,
      Q => rdlvl_stg1_done_r1,
      R => '0'
    );
reset_if_r8_reg_srl8: unisim.vcomponents.SRL16E
     port map (
      A0 => '1',
      A1 => '1',
      A2 => '1',
      A3 => '0',
      CE => '1',
      CLK => \dout_o_reg[15]\,
      D => reset_if,
      Q => reset_if_r8_reg_srl8_n_0
    );
reset_if_r9_reg: unisim.vcomponents.FDRE
     port map (
      C => \dout_o_reg[15]\,
      CE => '1',
      D => reset_if_r8_reg_srl8_n_0,
      Q => reset_if_r9,
      R => '0'
    );
reset_if_reg: unisim.vcomponents.FDRE
     port map (
      C => \dout_o_reg[15]\,
      CE => '1',
      D => \ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_29\,
      Q => reset_if,
      R => '0'
    );
tempmon_pi_f_en_r_reg: unisim.vcomponents.FDRE
     port map (
      C => \dout_o_reg[15]\,
      CE => '1',
      D => tempmon_sel_pi_incdec,
      Q => tempmon_pi_f_en_r,
      R => \corse_inc_reg[6][2]\(0)
    );
tempmon_pi_f_inc_r_reg: unisim.vcomponents.FDRE
     port map (
      C => \dout_o_reg[15]\,
      CE => '1',
      D => tempmon_pi_f_inc,
      Q => tempmon_pi_f_inc_r,
      R => \corse_inc_reg[6][2]\(0)
    );
u_ddr_phy_init: entity work.mig_mig_7series_v4_2_ddr_phy_init
     port map (
      D(7) => sel,
      D(6) => u_ddr_phy_init_n_22,
      D(5) => u_ddr_phy_init_n_23,
      D(4) => u_ddr_phy_init_n_24,
      D(3) => u_ddr_phy_init_n_25,
      D(2) => u_ddr_phy_init_n_26,
      D(1) => u_ddr_phy_init_n_27,
      D(0) => u_ddr_phy_init_n_28,
      D1(3 downto 0) => D1(3 downto 0),
      D2(7 downto 0) => D2(7 downto 0),
      D3(3 downto 0) => D3(3 downto 0),
      D4(3 downto 0) => D4(3 downto 0),
      D5(3 downto 0) => D5(3 downto 0),
      D6(7 downto 0) => D6(7 downto 0),
      D7(3 downto 0) => D7(3 downto 0),
      D8(3 downto 0) => D8(3 downto 0),
      D9(3 downto 0) => D9(3 downto 0),
      E(0) => samples_cnt_r,
      Q(0) => u_ddr_phy_init_n_29,
      SR(0) => u_ddr_phy_init_n_689,
      app_rd_data_valid => app_rd_data_valid,
      app_rd_data_valid_0(0) => app_rd_data_valid_0(0),
      calib_complete => calib_complete,
      \calib_data_offset_0_reg[0]_0\ => \dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_38\,
      \calib_data_offset_0_reg[1]_0\ => \dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_37\,
      \calib_data_offset_0_reg[2]_0\ => \dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_36\,
      \calib_data_offset_0_reg[3]_0\(0) => rd_data_offset_ranks_0(3),
      \calib_data_offset_0_reg[3]_1\(0) => \dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_28\,
      \calib_data_offset_0_reg[4]_0\ => \dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_35\,
      \calib_data_offset_0_reg[5]_0\ => \dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_34\,
      \calib_data_offset_1_reg[0]_0\ => \dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_43\,
      \calib_data_offset_1_reg[1]_0\ => \dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_42\,
      \calib_data_offset_1_reg[2]_0\ => \dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_41\,
      \calib_data_offset_1_reg[3]_0\(0) => rd_data_offset_ranks_1(3),
      \calib_data_offset_1_reg[3]_1\(0) => \dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_29\,
      \calib_data_offset_1_reg[4]_0\ => \dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_40\,
      \calib_data_offset_1_reg[5]_0\ => \dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_39\,
      \calib_data_offset_2_reg[0]_0\ => \dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_48\,
      \calib_data_offset_2_reg[1]_0\ => \dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_47\,
      \calib_data_offset_2_reg[2]_0\ => \dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_46\,
      \calib_data_offset_2_reg[3]_0\(0) => rd_data_offset_ranks_2(3),
      \calib_data_offset_2_reg[3]_1\(0) => \dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_30\,
      \calib_data_offset_2_reg[4]_0\ => \dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_45\,
      \calib_data_offset_2_reg[5]_0\ => \dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_44\,
      \calib_seq_reg[0]_0\(0) => Q(0),
      \calib_seq_reg[1]_0\(10 downto 0) => D(10 downto 0),
      ck_addr_cmd_delay_done => ck_addr_cmd_delay_done,
      \cmd_pipe_plus.mc_cas_n_reg[1]\(0) => \cmd_pipe_plus.mc_cas_n_reg[1]\(0),
      \cmd_pipe_plus.mc_cke_reg[3]\(3 downto 0) => \cmd_pipe_plus.mc_cke_reg[3]\(3 downto 0),
      \cmd_pipe_plus.mc_cke_reg[3]_0\(5 downto 0) => \cmd_pipe_plus.mc_cke_reg[3]_0\(5 downto 0),
      \cmd_pipe_plus.mc_data_offset_1_reg[5]\(5 downto 0) => \cmd_pipe_plus.mc_data_offset_1_reg[5]\(5 downto 0),
      \cmd_pipe_plus.mc_data_offset_2_reg[5]\(5 downto 0) => \cmd_pipe_plus.mc_data_offset_2_reg[5]\(5 downto 0),
      \cmd_pipe_plus.mc_odt_reg[0]\(3 downto 0) => \cmd_pipe_plus.mc_odt_reg[0]\(3 downto 0),
      \cmd_pipe_plus.mc_ras_n_reg[1]\(1 downto 0) => \cmd_pipe_plus.mc_ras_n_reg[1]\(1 downto 0),
      \cmd_pipe_plus.mc_we_n_reg[1]\(0) => \cmd_pipe_plus.mc_we_n_reg[1]\(0),
      \cnt_pwron_ce_r_reg[0]_0\ => cal2_if_reset_reg,
      complex_act_start => complex_act_start,
      \complex_num_writes_reg[1]_0\ => \complex_num_writes_reg[1]\,
      complex_ocal_reset_rd_addr => complex_ocal_reset_rd_addr,
      complex_oclkdelay_calib_done_r1_reg_0 => \ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_7\,
      complex_pi_incdec_done => complex_pi_incdec_done,
      d_in(35 downto 12) => d_in(37 downto 14),
      d_in(11 downto 0) => d_in(11 downto 0),
      \data_offset_1_i1_reg[0]\ => \data_offset_1_i1_reg[0]\,
      \data_offset_1_i1_reg[1]\ => \data_offset_1_i1_reg[1]\,
      \data_offset_1_i1_reg[2]\ => \data_offset_1_i1_reg[2]\,
      \data_offset_1_i1_reg[4]\ => \data_offset_1_i1_reg[4]\,
      \data_offset_1_i1_reg[5]\ => \data_offset_1_i1_reg[5]\,
      \data_offset_2_i1_reg[0]\ => \data_offset_2_i1_reg[0]\,
      \data_offset_2_i1_reg[1]\ => \data_offset_2_i1_reg[1]\,
      \data_offset_2_i1_reg[2]\ => \data_offset_2_i1_reg[2]\,
      \data_offset_2_i1_reg[4]\ => \data_offset_2_i1_reg[4]\,
      \data_offset_2_i1_reg[5]\ => \data_offset_2_i1_reg[5]\,
      ddr3_lm_done_r_reg_0 => u_ddr_phy_wrcal_n_3,
      detect_pi_found_dqs => detect_pi_found_dqs,
      done_dqs_tap_inc => done_dqs_tap_inc,
      dqs_found_prech_req => dqs_found_prech_req,
      \en_cnt_div4.enable_wrlvl_cnt_reg[2]_0\ => \en_cnt_div4.enable_wrlvl_cnt_reg[2]\,
      \en_cnt_div4.enable_wrlvl_cnt_reg[4]_0\ => \en_cnt_div4.enable_wrlvl_cnt_reg[4]\,
      first_rdlvl_pat_r => first_rdlvl_pat_r,
      first_wrcal_pat_r => first_wrcal_pat_r,
      \gen_no_mirror.div_clk_loop[0].phy_address_reg[10]_0\ => \dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_49\,
      \gen_no_mirror.div_clk_loop[0].phy_address_reg[2]_0\(3 downto 0) => \gen_no_mirror.div_clk_loop[0].phy_address_reg[2]\(3 downto 0),
      \gen_no_mirror.div_clk_loop[0].phy_address_reg[8]_0\(3 downto 0) => \gen_no_mirror.div_clk_loop[0].phy_address_reg[8]\(3 downto 0),
      \gen_no_mirror.div_clk_loop[0].phy_address_reg[9]_0\(3 downto 0) => \gen_no_mirror.div_clk_loop[0].phy_address_reg[9]\(3 downto 0),
      \gen_no_mirror.div_clk_loop[0].phy_bank_reg[0]_0\(3 downto 0) => \gen_no_mirror.div_clk_loop[0].phy_bank_reg[0]\(3 downto 0),
      \gen_no_mirror.div_clk_loop[0].phy_bank_reg[1]_0\(7 downto 0) => \gen_no_mirror.div_clk_loop[0].phy_bank_reg[1]\(7 downto 0),
      if_empty => if_empty,
      init_complete_r1_timing_reg_0 => init_complete_r1_timing_reg,
      init_dqsfound_done_r2 => init_dqsfound_done_r2,
      \init_state_r[0]_i_14_0\ => \ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_23\,
      \init_state_r[0]_i_4_0\ => u_ddr_phy_wrcal_n_4,
      \init_state_r[0]_i_4_1\ => \dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_51\,
      \init_state_r[1]_i_6_0\ => \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_30\,
      \init_state_r[2]_i_3_0\ => \dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_50\,
      \init_state_r[2]_i_4_0\ => u_ddr_phy_wrcal_n_37,
      \init_state_r[3]_i_4_0\ => u_ddr_phy_wrcal_n_38,
      \init_state_r[4]_i_10_0\ => \ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_22\,
      \init_state_r[4]_i_17_0\ => u_ddr_phy_wrcal_n_39,
      \init_state_r_reg[4]_0\ => \init_state_r_reg[4]\,
      \init_state_r_reg[4]_1\ => u_ddr_phy_init_n_683,
      mc_address(34 downto 0) => mc_address(34 downto 0),
      mc_bank(8 downto 0) => mc_bank(8 downto 0),
      mc_cas_n(0) => mc_cas_n(0),
      mc_cke(0) => mc_cke(0),
      mc_cmd(1 downto 0) => mc_cmd(1 downto 0),
      mc_data_offset(0) => mc_data_offset(0),
      mc_data_offset_1(0) => mc_data_offset_1(0),
      mc_data_offset_2(0) => mc_data_offset_2(0),
      mc_odt(0) => mc_odt(0),
      mc_ras_n(0) => mc_ras_n(0),
      mc_we_n(0) => mc_we_n(0),
      mc_wrdata_en => mc_wrdata_en,
      mem_out(35 downto 0) => mem_out(35 downto 0),
      mem_reg_0_15_18_23 => \init_calib_complete_reg_rep__19_n_0\,
      mem_reg_0_15_18_23_0 => \init_calib_complete_reg_rep__20_n_0\,
      mem_reg_0_15_36_41 => \init_calib_complete_reg_rep__14_n_0\,
      mem_reg_0_15_36_41_0 => \init_calib_complete_reg_rep__21_n_0\,
      mem_reg_0_15_36_41_1 => \init_calib_complete_reg_rep__22_n_0\,
      mem_reg_0_15_48_53 => \init_calib_complete_reg_rep__15_n_0\,
      mem_reg_0_15_54_59 => \init_calib_complete_reg_rep__16_n_0\,
      mem_reg_0_15_54_59_0 => \init_calib_complete_reg_rep__23_n_0\,
      mem_reg_0_15_66_71 => \init_calib_complete_reg_rep__17_n_0\,
      mem_reg_0_15_72_77 => \init_calib_complete_reg_rep__18_n_0\,
      mem_reg_0_15_78_79(511 downto 0) => mem_reg_0_15_12_17(511 downto 0),
      mem_reg_0_15_78_79_0 => \^init_calib_complete_reg_rep__24_0\,
      mpr_rdlvl_start_reg_0 => u_ddr_phy_init_n_701,
      mux_rd_valid_r0 => mux_rd_valid_r0,
      mux_reset_n => mux_reset_n,
      num_samples_done_r => num_samples_done_r,
      \one_rank.stg1_wr_done_reg_0\ => u_ddr_phy_init_n_13,
      out_fifo => out_fifo,
      out_fifo_0(23 downto 0) => out_fifo_0(23 downto 0),
      out_fifo_1 => out_fifo_1,
      out_fifo_10 => out_fifo_9,
      out_fifo_11 => \init_calib_complete_reg_rep__10_n_0\,
      out_fifo_12(63 downto 0) => out_fifo_10(63 downto 0),
      out_fifo_13 => out_fifo_11,
      out_fifo_14(63 downto 0) => out_fifo_12(63 downto 0),
      out_fifo_15 => out_fifo_13,
      out_fifo_16(63 downto 0) => out_fifo_14(63 downto 0),
      out_fifo_17 => out_fifo_15,
      out_fifo_18(63 downto 0) => out_fifo_16(63 downto 0),
      out_fifo_19 => out_fifo_17,
      out_fifo_2 => \^init_calib_complete_reg_rep__11_0\,
      out_fifo_20 => \init_calib_complete_reg_rep__9_n_0\,
      out_fifo_21 => \init_calib_complete_reg_rep__8_n_0\,
      out_fifo_22 => \init_calib_complete_reg_rep__7_n_0\,
      out_fifo_23 => \init_calib_complete_reg_rep__6_n_0\,
      out_fifo_24 => \init_calib_complete_reg_rep__5_n_0\,
      out_fifo_25 => \init_calib_complete_reg_rep__4_n_0\,
      out_fifo_26 => \init_calib_complete_reg_rep__3_n_0\,
      out_fifo_27 => \init_calib_complete_reg_rep__2_n_0\,
      out_fifo_28 => \init_calib_complete_reg_rep__1_n_0\,
      out_fifo_29(11 downto 0) => out_fifo_18(11 downto 0),
      out_fifo_3(63 downto 0) => out_fifo_2(63 downto 0),
      out_fifo_30 => out_fifo_19,
      out_fifo_31 => \^init_calib_complete_reg_rep__0_0\,
      out_fifo_4 => out_fifo_3,
      out_fifo_5(63 downto 0) => out_fifo_4(63 downto 0),
      out_fifo_6 => out_fifo_5,
      out_fifo_7(63 downto 0) => out_fifo_6(63 downto 0),
      out_fifo_8 => out_fifo_7,
      out_fifo_9(63 downto 0) => out_fifo_8(63 downto 0),
      phy_cmd_wr_en => phy_cmd_wr_en,
      \phy_ctl_wd_i1_reg[0]\ => \init_calib_complete_reg_rep__13_n_0\,
      \phy_ctl_wd_i1_reg[17]\ => \phy_ctl_wd_i1_reg[17]\,
      \phy_ctl_wd_i1_reg[18]\ => \phy_ctl_wd_i1_reg[18]\,
      \phy_ctl_wd_i1_reg[19]\ => \phy_ctl_wd_i1_reg[19]\,
      \phy_ctl_wd_i1_reg[21]\ => \phy_ctl_wd_i1_reg[21]\,
      \phy_ctl_wd_i1_reg[22]\ => \phy_ctl_wd_i1_reg[22]\,
      phy_ctl_wr_i1_reg => \^init_calib_complete_reg_rep__12_0\,
      phy_data_wr_en => phy_data_wr_en,
      phy_dout(23 downto 0) => phy_dout(23 downto 0),
      phy_read_calib => phy_read_calib,
      phy_write_calib => phy_write_calib,
      pi_calib_done => pi_calib_done,
      pi_dqs_found_done_r1 => pi_dqs_found_done_r1,
      pi_dqs_found_done_r1_reg_0 => \dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_2\,
      pi_dqs_found_rank_done => pi_dqs_found_rank_done,
      pi_dqs_found_start_reg_0 => u_ddr_phy_init_n_700,
      pi_phase_locked_all_r1_reg_0 => pi_phase_locked_all_r1_reg,
      prbs_last_byte_done => prbs_last_byte_done,
      prbs_out(19) => prbs_out(508),
      prbs_out(18) => prbs_out(504),
      prbs_out(17) => prbs_out(383),
      prbs_out(16) => prbs_out(379),
      prbs_out(15 downto 14) => prbs_out(318 downto 317),
      prbs_out(13 downto 12) => prbs_out(314 downto 313),
      prbs_out(11) => prbs_out(254),
      prbs_out(10) => prbs_out(250),
      prbs_out(9) => prbs_out(189),
      prbs_out(8) => prbs_out(185),
      prbs_out(7 downto 6) => prbs_out(127 downto 126),
      prbs_out(5 downto 4) => prbs_out(123 downto 122),
      prbs_out(3) => prbs_out(63),
      prbs_out(2 downto 1) => prbs_out(60 downto 59),
      prbs_out(0) => prbs_out(56),
      prbs_rdlvl_done_pulse0 => prbs_rdlvl_done_pulse0,
      prbs_rdlvl_done_pulse_reg_0 => prbs_rdlvl_done_pulse_reg,
      prbs_rdlvl_done_r1 => prbs_rdlvl_done_r1,
      prbs_rdlvl_done_reg(0) => u_ddr_phy_init_n_686,
      prbs_rdlvl_done_reg_0 => u_ddr_phy_init_n_688,
      prbs_rdlvl_start_r => prbs_rdlvl_start_r,
      prbs_rdlvl_start_reg_0 => u_ddr_phy_init_n_679,
      prbs_rdlvl_start_reg_1 => u_ddr_phy_init_n_680,
      prbs_rdlvl_start_reg_2 => \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_10\,
      prech_done => prech_done,
      prech_req => prech_req,
      prech_req_posedge_r_reg_0 => u_ddr_phy_init_n_3,
      prech_req_posedge_r_reg_1 => \ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_2\,
      \rd_addr_reg[1]\ => u_ddr_phy_init_n_687,
      \rd_addr_reg[3]\(0) => u_ddr_prbs_gen_n_45,
      \rd_addr_reg[7]\ => \idelay_tap_cnt_r_reg[0][0][4]\,
      \rd_addr_reg[7]_0\ => u_ddr_prbs_gen_n_0,
      rdlvl_last_byte_done => rdlvl_last_byte_done,
      rdlvl_pi_incdec => rdlvl_pi_incdec,
      rdlvl_prech_req => rdlvl_prech_req,
      \rdlvl_start_dly0_r_reg[14]_0\ => \dout_o_reg[15]\,
      rdlvl_stg1_done_r1 => rdlvl_stg1_done_r1,
      rdlvl_stg1_rank_done => rdlvl_stg1_rank_done,
      rdlvl_stg1_start_int_reg_0 => u_ddr_phy_init_n_684,
      rdlvl_stg1_start_reg_0 => \^rdlvl_stg1_start_reg\,
      \read_fifo.tail_r\(0) => \read_fifo.tail_r\(0),
      \read_fifo.tail_r_reg[0]\ => \read_fifo.tail_r_reg[0]\,
      reset_rd_addr => reset_rd_addr,
      reset_rd_addr0 => reset_rd_addr0,
      \row_cnt_victim_rotate.complex_row_cnt_reg[1]_0\ => \ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_19\,
      \row_cnt_victim_rotate.complex_row_cnt_reg[2]_0\ => \ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_20\,
      \row_cnt_victim_rotate.complex_row_cnt_reg[3]_0\ => \ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_18\,
      \row_cnt_victim_rotate.complex_row_cnt_reg[6]_0\ => \ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_1\,
      \samples_cnt_r_reg[11]\ => \ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_11\,
      stg1_wr_done => stg1_wr_done,
      \stg1_wr_rd_cnt_reg[3]_0\ => \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_19\,
      \victim_sel_reg[0]_0\(0) => \victim_sel_reg[0]\(0),
      wl_sm_start => wl_sm_start,
      wl_sm_start_reg_0 => u_ddr_phy_init_n_677,
      wr_level_done_r5 => wr_level_done_r5,
      wr_lvl_start_reg_0 => u_ddr_phy_init_n_15,
      wrcal_prech_req => wrcal_prech_req,
      wrcal_rd_wait => wrcal_rd_wait,
      wrcal_resume_w => wrcal_resume_w,
      wrcal_sanity_chk => wrcal_sanity_chk,
      wrcal_start_reg_0 => u_ddr_phy_init_n_699,
      \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[120]_0\ => u_ddr_prbs_gen_n_18,
      \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[121]_0\ => u_ddr_prbs_gen_n_40,
      \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[124]_0\ => u_ddr_prbs_gen_n_17,
      \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[125]_0\ => u_ddr_prbs_gen_n_39,
      \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[184]_0\ => u_ddr_prbs_gen_n_16,
      \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[186]_0\ => u_ddr_prbs_gen_n_15,
      \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[187]_0\ => u_ddr_phy_wrcal_n_22,
      \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[187]_1\ => u_ddr_prbs_gen_n_38,
      \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[188]_0\ => u_ddr_prbs_gen_n_14,
      \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[190]_0\ => u_ddr_prbs_gen_n_13,
      \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[191]_0\ => u_ddr_prbs_gen_n_37,
      \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[248]_0\ => u_ddr_prbs_gen_n_36,
      \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[249]_0\ => u_ddr_prbs_gen_n_12,
      \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[251]_0\ => u_ddr_prbs_gen_n_11,
      \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[252]_0\ => u_ddr_prbs_gen_n_35,
      \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[253]_0\ => u_ddr_prbs_gen_n_10,
      \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[255]_0\ => u_ddr_prbs_gen_n_9,
      \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[312]_0\ => u_ddr_prbs_gen_n_34,
      \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[315]_0\ => u_ddr_prbs_gen_n_8,
      \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[316]_0\ => u_ddr_prbs_gen_n_33,
      \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[319]_0\ => u_ddr_prbs_gen_n_7,
      \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[376]_0\ => u_ddr_prbs_gen_n_6,
      \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[377]_0\ => u_ddr_prbs_gen_n_32,
      \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[378]_0\ => u_ddr_prbs_gen_n_31,
      \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[380]_0\ => u_ddr_prbs_gen_n_5,
      \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[381]_0\ => u_ddr_prbs_gen_n_30,
      \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[382]_0\ => u_ddr_prbs_gen_n_29,
      \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[440]_0\ => u_ddr_prbs_gen_n_28,
      \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[441]_0\ => u_ddr_prbs_gen_n_4,
      \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[442]_0\ => u_ddr_prbs_gen_n_27,
      \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[443]_0\ => u_ddr_prbs_gen_n_26,
      \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[444]_0\ => u_ddr_prbs_gen_n_25,
      \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[445]_0\ => u_ddr_prbs_gen_n_3,
      \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[446]_0\ => u_ddr_prbs_gen_n_24,
      \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[447]_0\ => u_ddr_prbs_gen_n_23,
      \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[505]_0\ => u_ddr_prbs_gen_n_22,
      \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[506]_0\ => u_ddr_prbs_gen_n_2,
      \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[507]_0\ => u_ddr_prbs_gen_n_21,
      \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[508]_0\ => u_ddr_phy_wrcal_n_40,
      \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[509]_0\ => u_ddr_prbs_gen_n_20,
      \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[510]_0\ => u_ddr_prbs_gen_n_1,
      \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[511]_0\ => u_ddr_prbs_gen_n_19,
      \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[56]_0\(0) => \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_20\,
      \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[57]_0\ => u_ddr_prbs_gen_n_44,
      \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[58]_0\ => u_ddr_prbs_gen_n_43,
      \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[61]_0\ => u_ddr_prbs_gen_n_42,
      \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[62]_0\ => u_ddr_prbs_gen_n_41,
      \write_buffer.wr_buf_out_data_reg[448]\(7 downto 0) => \write_buffer.wr_buf_out_data_reg[448]\(7 downto 0),
      \write_buffer.wr_buf_out_data_reg[450]\(7 downto 0) => \write_buffer.wr_buf_out_data_reg[450]\(7 downto 0),
      \write_buffer.wr_buf_out_data_reg[451]\(7 downto 0) => \write_buffer.wr_buf_out_data_reg[451]\(7 downto 0),
      \write_buffer.wr_buf_out_data_reg[452]\(7 downto 0) => \write_buffer.wr_buf_out_data_reg[452]\(7 downto 0),
      \write_buffer.wr_buf_out_data_reg[453]\(7 downto 0) => \write_buffer.wr_buf_out_data_reg[453]\(7 downto 0),
      \write_buffer.wr_buf_out_data_reg[454]\(7 downto 0) => \write_buffer.wr_buf_out_data_reg[454]\(7 downto 0),
      \write_buffer.wr_buf_out_data_reg[455]\(7 downto 0) => \write_buffer.wr_buf_out_data_reg[455]_0\(7 downto 0),
      \write_buffer.wr_buf_out_data_reg[455]_0\(63 downto 0) => \write_buffer.wr_buf_out_data_reg[455]\(71 downto 8),
      \write_buffer.wr_buf_out_data_reg[456]\(7 downto 0) => \write_buffer.wr_buf_out_data_reg[456]\(7 downto 0),
      \write_buffer.wr_buf_out_data_reg[457]\(7 downto 0) => \write_buffer.wr_buf_out_data_reg[457]\(7 downto 0),
      \write_buffer.wr_buf_out_data_reg[458]\(7 downto 0) => \write_buffer.wr_buf_out_data_reg[458]\(7 downto 0),
      \write_buffer.wr_buf_out_data_reg[459]\(7 downto 0) => \write_buffer.wr_buf_out_data_reg[459]\(7 downto 0),
      \write_buffer.wr_buf_out_data_reg[460]\(7 downto 0) => \write_buffer.wr_buf_out_data_reg[460]\(7 downto 0),
      \write_buffer.wr_buf_out_data_reg[461]\(7 downto 0) => \write_buffer.wr_buf_out_data_reg[461]\(7 downto 0),
      \write_buffer.wr_buf_out_data_reg[462]\(7 downto 0) => \write_buffer.wr_buf_out_data_reg[462]\(7 downto 0),
      \write_buffer.wr_buf_out_data_reg[463]\(7 downto 0) => \write_buffer.wr_buf_out_data_reg[463]_0\(7 downto 0),
      \write_buffer.wr_buf_out_data_reg[463]_0\(63 downto 0) => \write_buffer.wr_buf_out_data_reg[463]\(71 downto 8),
      \write_buffer.wr_buf_out_data_reg[464]\(7 downto 0) => \write_buffer.wr_buf_out_data_reg[464]\(7 downto 0),
      \write_buffer.wr_buf_out_data_reg[465]\(7 downto 0) => \write_buffer.wr_buf_out_data_reg[465]\(7 downto 0),
      \write_buffer.wr_buf_out_data_reg[466]\(7 downto 0) => \write_buffer.wr_buf_out_data_reg[466]\(7 downto 0),
      \write_buffer.wr_buf_out_data_reg[467]\(7 downto 0) => \write_buffer.wr_buf_out_data_reg[467]\(7 downto 0),
      \write_buffer.wr_buf_out_data_reg[468]\(7 downto 0) => \write_buffer.wr_buf_out_data_reg[468]\(7 downto 0),
      \write_buffer.wr_buf_out_data_reg[469]\(7 downto 0) => \write_buffer.wr_buf_out_data_reg[469]\(7 downto 0),
      \write_buffer.wr_buf_out_data_reg[470]\(7 downto 0) => \write_buffer.wr_buf_out_data_reg[470]\(7 downto 0),
      \write_buffer.wr_buf_out_data_reg[471]\(7 downto 0) => \write_buffer.wr_buf_out_data_reg[471]_0\(7 downto 0),
      \write_buffer.wr_buf_out_data_reg[471]_0\(63 downto 0) => \write_buffer.wr_buf_out_data_reg[471]\(71 downto 8),
      \write_buffer.wr_buf_out_data_reg[472]\(7 downto 0) => \write_buffer.wr_buf_out_data_reg[472]\(7 downto 0),
      \write_buffer.wr_buf_out_data_reg[473]\(7 downto 0) => \write_buffer.wr_buf_out_data_reg[473]\(7 downto 0),
      \write_buffer.wr_buf_out_data_reg[474]\(7 downto 0) => \write_buffer.wr_buf_out_data_reg[474]\(7 downto 0),
      \write_buffer.wr_buf_out_data_reg[475]\(7 downto 0) => \write_buffer.wr_buf_out_data_reg[475]\(7 downto 0),
      \write_buffer.wr_buf_out_data_reg[476]\(7 downto 0) => \write_buffer.wr_buf_out_data_reg[476]\(7 downto 0),
      \write_buffer.wr_buf_out_data_reg[477]\(7 downto 0) => \write_buffer.wr_buf_out_data_reg[477]\(7 downto 0),
      \write_buffer.wr_buf_out_data_reg[478]\(7 downto 0) => \write_buffer.wr_buf_out_data_reg[478]\(7 downto 0),
      \write_buffer.wr_buf_out_data_reg[479]\(7 downto 0) => \write_buffer.wr_buf_out_data_reg[479]_0\(7 downto 0),
      \write_buffer.wr_buf_out_data_reg[479]_0\(63 downto 0) => \write_buffer.wr_buf_out_data_reg[479]\(71 downto 8),
      \write_buffer.wr_buf_out_data_reg[480]\(7 downto 0) => \write_buffer.wr_buf_out_data_reg[480]\(7 downto 0),
      \write_buffer.wr_buf_out_data_reg[481]\(7 downto 0) => \write_buffer.wr_buf_out_data_reg[481]\(7 downto 0),
      \write_buffer.wr_buf_out_data_reg[482]\(7 downto 0) => \write_buffer.wr_buf_out_data_reg[482]\(7 downto 0),
      \write_buffer.wr_buf_out_data_reg[483]\(7 downto 0) => \write_buffer.wr_buf_out_data_reg[483]\(7 downto 0),
      \write_buffer.wr_buf_out_data_reg[484]\(7 downto 0) => \write_buffer.wr_buf_out_data_reg[484]\(7 downto 0),
      \write_buffer.wr_buf_out_data_reg[485]\(7 downto 0) => \write_buffer.wr_buf_out_data_reg[485]\(7 downto 0),
      \write_buffer.wr_buf_out_data_reg[486]\(7 downto 0) => \write_buffer.wr_buf_out_data_reg[486]\(7 downto 0),
      \write_buffer.wr_buf_out_data_reg[487]\(7 downto 0) => \write_buffer.wr_buf_out_data_reg[487]_0\(7 downto 0),
      \write_buffer.wr_buf_out_data_reg[487]_0\(63 downto 0) => \write_buffer.wr_buf_out_data_reg[487]\(71 downto 8),
      \write_buffer.wr_buf_out_data_reg[488]\(7 downto 0) => \write_buffer.wr_buf_out_data_reg[488]\(7 downto 0),
      \write_buffer.wr_buf_out_data_reg[489]\(7 downto 0) => \write_buffer.wr_buf_out_data_reg[489]\(7 downto 0),
      \write_buffer.wr_buf_out_data_reg[490]\(7 downto 0) => \write_buffer.wr_buf_out_data_reg[490]\(7 downto 0),
      \write_buffer.wr_buf_out_data_reg[491]\(7 downto 0) => \write_buffer.wr_buf_out_data_reg[491]\(7 downto 0),
      \write_buffer.wr_buf_out_data_reg[492]\(7 downto 0) => \write_buffer.wr_buf_out_data_reg[492]\(7 downto 0),
      \write_buffer.wr_buf_out_data_reg[493]\(7 downto 0) => \write_buffer.wr_buf_out_data_reg[493]\(7 downto 0),
      \write_buffer.wr_buf_out_data_reg[494]\(7 downto 0) => \write_buffer.wr_buf_out_data_reg[494]\(7 downto 0),
      \write_buffer.wr_buf_out_data_reg[495]\(7 downto 0) => \write_buffer.wr_buf_out_data_reg[495]_0\(7 downto 0),
      \write_buffer.wr_buf_out_data_reg[495]_0\(63 downto 0) => \write_buffer.wr_buf_out_data_reg[495]\(71 downto 8),
      \write_buffer.wr_buf_out_data_reg[496]\(7 downto 0) => \write_buffer.wr_buf_out_data_reg[496]\(7 downto 0),
      \write_buffer.wr_buf_out_data_reg[497]\(7 downto 0) => \write_buffer.wr_buf_out_data_reg[497]\(7 downto 0),
      \write_buffer.wr_buf_out_data_reg[498]\(7 downto 0) => \write_buffer.wr_buf_out_data_reg[498]\(7 downto 0),
      \write_buffer.wr_buf_out_data_reg[499]\(7 downto 0) => \write_buffer.wr_buf_out_data_reg[499]\(7 downto 0),
      \write_buffer.wr_buf_out_data_reg[500]\(7 downto 0) => \write_buffer.wr_buf_out_data_reg[500]\(7 downto 0),
      \write_buffer.wr_buf_out_data_reg[501]\(7 downto 0) => \write_buffer.wr_buf_out_data_reg[501]\(7 downto 0),
      \write_buffer.wr_buf_out_data_reg[502]\(7 downto 0) => \write_buffer.wr_buf_out_data_reg[502]\(7 downto 0),
      \write_buffer.wr_buf_out_data_reg[503]\(7 downto 0) => \write_buffer.wr_buf_out_data_reg[503]_0\(7 downto 0),
      \write_buffer.wr_buf_out_data_reg[503]_0\(63 downto 0) => \write_buffer.wr_buf_out_data_reg[503]\(71 downto 8),
      \write_buffer.wr_buf_out_data_reg[504]\(7 downto 0) => \write_buffer.wr_buf_out_data_reg[504]\(7 downto 0),
      \write_buffer.wr_buf_out_data_reg[505]\(7 downto 0) => \write_buffer.wr_buf_out_data_reg[505]\(7 downto 0),
      \write_buffer.wr_buf_out_data_reg[506]\(7 downto 0) => \write_buffer.wr_buf_out_data_reg[506]\(7 downto 0),
      \write_buffer.wr_buf_out_data_reg[507]\(7 downto 0) => \write_buffer.wr_buf_out_data_reg[507]\(7 downto 0),
      \write_buffer.wr_buf_out_data_reg[508]\(7 downto 0) => \write_buffer.wr_buf_out_data_reg[508]\(7 downto 0),
      \write_buffer.wr_buf_out_data_reg[509]\(7 downto 0) => \write_buffer.wr_buf_out_data_reg[509]\(7 downto 0),
      \write_buffer.wr_buf_out_data_reg[510]\(7 downto 0) => \write_buffer.wr_buf_out_data_reg[510]\(7 downto 0),
      \write_buffer.wr_buf_out_data_reg[511]\(7 downto 0) => \write_buffer.wr_buf_out_data_reg[511]_0\(7 downto 0),
      \write_buffer.wr_buf_out_data_reg[511]_0\(63 downto 0) => \write_buffer.wr_buf_out_data_reg[511]\(71 downto 8),
      write_calib_reg_0 => \not_empty_wait_cnt_reg[4]\,
      wrlvl_byte_redo => wrlvl_byte_redo,
      wrlvl_done_r1 => wrlvl_done_r1,
      wrlvl_done_r_reg_0 => \mb_wrlvl_inst.u_ddr_phy_wrlvl_n_5\,
      wrlvl_final_if_rst => wrlvl_final_if_rst,
      wrlvl_rank_done => wrlvl_rank_done
    );
u_ddr_phy_wrcal: entity work.mig_mig_7series_v4_2_ddr_phy_wrcal
     port map (
      E(0) => rd_active_r,
      LD0 => LD0,
      LD0_0 => LD0_0,
      LD0_1 => LD0_1,
      LD0_2 => LD0_2,
      LD0_3 => LD0_3,
      LD0_4 => LD0_4,
      LD0_5 => LD0_5,
      LD0_6 => LD0_6,
      Q(3) => po_stg2_wrcal_cnt(3),
      Q(2 downto 0) => \^po_stg2_wrcal_cnt_reg[2]\(2 downto 0),
      cal2_done_r_reg_0(0) => \rdlvl_dqs_tap_cnt_r_reg[0][0][2]\(0),
      cal2_if_reset_reg_0 => cal2_if_reset_reg,
      \cal2_state_r_reg[0]_0\ => u_ddr_phy_init_n_699,
      calib_in_common => calib_in_common,
      \corse_cnt[0][2]_i_3\(1 downto 0) => \wl_state_r__0\(4 downto 3),
      \corse_cnt[0][2]_i_3_0\ => \mb_wrlvl_inst.u_ddr_phy_wrlvl_n_46\,
      done_dqs_dec238_out => done_dqs_dec238_out,
      early1_data_reg_0 => u_ddr_phy_wrcal_n_6,
      early1_data_reg_1 => u_ddr_phy_wrcal_n_24,
      \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg[0]_0\ => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg[0]\,
      \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg[0]_0\ => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg[0]\,
      \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg[0]_0\ => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg[0]\,
      \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg[0]_0\ => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg[0]\,
      \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg[0]_0\ => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg[0]\,
      \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise2_r_reg[0]_0\ => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise2_r_reg[0]\,
      \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg[0]_0\ => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg[0]\,
      \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg[1]_0\ => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg[1]\,
      \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg[1]_0\ => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg[1]\,
      \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg[1]_0\ => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg[1]\,
      \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg[1]_0\ => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg[1]\,
      \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg[1]_0\ => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg[1]\,
      \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg[1]_0\ => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg[1]\,
      \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg[1]_0\ => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg[1]\,
      \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg[1]_0\ => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg[1]\,
      \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg[2]_0\ => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg[2]\,
      \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg[2]_0\ => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg[2]\,
      \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg[2]_0\ => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg[2]\,
      \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg[2]_0\ => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg[2]\,
      \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg[2]_0\ => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg[2]\,
      \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg[2]_0\ => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg[2]\,
      \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg[2]_0\ => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg[2]\,
      \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg[2]_0\ => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg[2]\,
      \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg[3]_0\ => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg[3]\,
      \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg[3]_0\ => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg[3]\,
      \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg[3]_0\ => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg[3]\,
      \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg[3]_0\ => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg[3]\,
      \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg[3]_0\ => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg[3]\,
      \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg[3]_0\ => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg[3]\,
      \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg[3]_0\ => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg[3]\,
      \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise3_r_reg[3]_0\ => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise3_r_reg[3]\,
      \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg[4]_0\ => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg[4]\,
      \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg[4]_0\ => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg[4]\,
      \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg[4]_0\ => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg[4]\,
      \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg[4]_0\ => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg[4]\,
      \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg[4]_0\ => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg[4]\,
      \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg[4]_0\ => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg[4]\,
      \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise2_r_reg[4]_0\ => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise2_r_reg[4]\,
      \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg[4]_0\ => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg[4]\,
      \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg[5]_0\ => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg[5]\,
      \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg[5]_0\ => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg[5]\,
      \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg[5]_0\ => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg[5]\,
      \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg[5]_0\ => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg[5]\,
      \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg[5]_0\ => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg[5]\,
      \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg[5]_0\ => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg[5]\,
      \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg[5]_0\ => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg[5]\,
      \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg[5]_0\ => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg[5]\,
      \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg[6]_0\ => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg[6]\,
      \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg[6]_0\ => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg[6]\,
      \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg[6]_0\ => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg[6]\,
      \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg[6]_0\ => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg[6]\,
      \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg[6]_0\ => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg[6]\,
      \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg[6]_0\ => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg[6]\,
      \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg[6]_0\ => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg[6]\,
      \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg[6]_0\ => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg[6]\,
      \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg[7]_0\ => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg[7]\,
      \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg[7]_0\ => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg[7]\,
      \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg[7]_0\ => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg[7]\,
      \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7]_0\ => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7]\,
      \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg[7]_0\ => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg[7]\,
      \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg[7]_0\ => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg[7]\,
      \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg[7]_0\ => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg[7]\,
      \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise3_r_reg[7]_0\ => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise3_r_reg[7]\,
      idelay_ce_int => idelay_ce_int,
      idelay_ld_rst => idelay_ld_rst,
      idelay_ld_rst_10 => idelay_ld_rst_10,
      idelay_ld_rst_11 => idelay_ld_rst_11,
      idelay_ld_rst_12 => idelay_ld_rst_12,
      idelay_ld_rst_13 => idelay_ld_rst_13,
      idelay_ld_rst_7 => idelay_ld_rst_7,
      idelay_ld_rst_8 => idelay_ld_rst_8,
      idelay_ld_rst_9 => idelay_ld_rst_9,
      \idelay_tap_cnt_r_reg[0][0][4]\ => \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_15\,
      \idelay_tap_cnt_r_reg[0][0][4]_0\ => \idelay_tap_cnt_r_reg[0][0][4]\,
      \idelay_tap_cnt_r_reg[0][1][4]\ => \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_26\,
      \idelay_tap_cnt_r_reg[0][2][4]\ => \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_25\,
      \idelay_tap_cnt_r_reg[0][4][4]\ => \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_14\,
      \idelay_tap_cnt_r_reg[0][4][4]_0\ => \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_23\,
      \idelay_tap_cnt_r_reg[0][4][4]_1\ => \idelay_tap_cnt_r_reg[0][4][4]\,
      \idelay_tap_cnt_r_reg[0][5][4]\ => \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_27\,
      \idelay_tap_cnt_r_reg[0][5][4]_0\ => \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_22\,
      \idelay_tap_cnt_r_reg[0][6][4]\ => \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_24\,
      \idelay_tap_cnt_r_reg[0][7][4]\ => \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_28\,
      \init_state_r[2]_i_14\ => \ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_7\,
      \init_state_r[3]_i_13\ => \dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_2\,
      \init_state_r[3]_i_13_0\ => u_ddr_phy_init_n_684,
      \init_state_r[4]_i_27\ => u_ddr_phy_init_n_3,
      \input_[9].iserdes_dq_.idelay_dq.idelaye2\(1) => calib_zero_inputs(2),
      \input_[9].iserdes_dq_.idelay_dq.idelaye2\(0) => calib_zero_inputs(0),
      \input_[9].iserdes_dq_.idelay_dq.idelaye2_0\ => \^calib_sel\(0),
      \input_[9].iserdes_dq_.idelay_dq.idelaye2_1\ => \^calib_sel\(1),
      \not_empty_wait_cnt_reg[4]_0\ => \not_empty_wait_cnt_reg[4]\,
      p_0_out => p_0_out,
      phy_if_reset_w => phy_if_reset_w,
      phy_rddata_en => phy_rddata_en,
      \po_stg2_wrcal_cnt_reg[0]_0\ => u_ddr_phy_wrcal_n_25,
      \po_stg2_wrcal_cnt_reg[0]_1\ => u_ddr_phy_wrcal_n_27,
      \po_stg2_wrcal_cnt_reg[0]_2\ => u_ddr_phy_wrcal_n_28,
      \po_stg2_wrcal_cnt_reg[0]_3\(0) => u_ddr_phy_wrcal_n_29,
      \po_stg2_wrcal_cnt_reg[0]_4\(0) => u_ddr_phy_wrcal_n_30,
      \po_stg2_wrcal_cnt_reg[0]_5\(0) => u_ddr_phy_wrcal_n_31,
      \po_stg2_wrcal_cnt_reg[0]_6\(0) => u_ddr_phy_wrcal_n_32,
      \po_stg2_wrcal_cnt_reg[0]_7\(0) => u_ddr_phy_wrcal_n_34,
      \po_stg2_wrcal_cnt_reg[0]_8\(0) => u_ddr_phy_wrcal_n_35,
      \po_stg2_wrcal_cnt_reg[1]_0\ => u_ddr_phy_wrcal_n_26,
      \po_stg2_wrcal_cnt_reg[1]_1\(0) => u_ddr_phy_wrcal_n_33,
      \po_stg2_wrcal_cnt_reg[1]_2\(0) => u_ddr_phy_wrcal_n_36,
      \po_stg2_wrcal_cnt_reg[2]_0\ => u_ddr_phy_wrcal_n_23,
      \po_stg2_wrcal_cnt_reg[3]_0\ => u_ddr_phy_wrcal_n_8,
      prech_done => prech_done,
      wrcal_done_reg_0 => u_ddr_phy_wrcal_n_3,
      wrcal_done_reg_1 => u_ddr_phy_wrcal_n_22,
      wrcal_done_reg_2 => u_ddr_phy_wrcal_n_37,
      wrcal_done_reg_3 => u_ddr_phy_wrcal_n_38,
      wrcal_done_reg_4 => u_ddr_phy_wrcal_n_40,
      wrcal_pat_resume_reg_0 => \dout_o_reg[15]\,
      wrcal_prech_req => wrcal_prech_req,
      wrcal_rd_wait => wrcal_rd_wait,
      wrcal_resume_w => wrcal_resume_w,
      wrcal_sanity_chk => wrcal_sanity_chk,
      wrcal_sanity_chk_done_reg_0 => u_ddr_phy_wrcal_n_4,
      \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[508]\ => \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_10\,
      wrlvl_byte_done => wrlvl_byte_done,
      wrlvl_byte_redo => wrlvl_byte_redo,
      wrlvl_byte_redo_r => wrlvl_byte_redo_r,
      wrlvl_byte_redo_reg_0 => u_ddr_phy_wrcal_n_39,
      wrlvl_done_r1 => wrlvl_done_r1,
      \wrlvl_redo_corse_inc[2]_i_7\ => \mb_wrlvl_inst.u_ddr_phy_wrlvl_n_45\,
      \wrlvl_redo_corse_inc[2]_i_7_0\ => \mb_wrlvl_inst.u_ddr_phy_wrlvl_n_44\
    );
u_ddr_prbs_gen: entity work.mig_mig_7series_v4_2_ddr_prbs_gen
     port map (
      D(7) => sel,
      D(6) => u_ddr_phy_init_n_22,
      D(5) => u_ddr_phy_init_n_23,
      D(4) => u_ddr_phy_init_n_24,
      D(3) => u_ddr_phy_init_n_25,
      D(2) => u_ddr_phy_init_n_26,
      D(1) => u_ddr_phy_init_n_27,
      D(0) => u_ddr_phy_init_n_28,
      E(0) => u_ddr_phy_init_n_686,
      Q(0) => u_ddr_prbs_gen_n_45,
      SR(0) => u_ddr_phy_init_n_689,
      \dout_o_reg[10]_0\ => u_ddr_prbs_gen_n_5,
      \dout_o_reg[10]_1\ => u_ddr_prbs_gen_n_6,
      \dout_o_reg[10]_2\ => u_ddr_prbs_gen_n_29,
      \dout_o_reg[10]_3\ => u_ddr_prbs_gen_n_31,
      \dout_o_reg[11]_0\ => u_ddr_prbs_gen_n_7,
      \dout_o_reg[11]_1\ => u_ddr_prbs_gen_n_8,
      \dout_o_reg[11]_2\ => u_ddr_prbs_gen_n_33,
      \dout_o_reg[11]_3\ => u_ddr_prbs_gen_n_34,
      \dout_o_reg[12]_0\ => u_ddr_prbs_gen_n_9,
      \dout_o_reg[12]_1\ => u_ddr_prbs_gen_n_10,
      \dout_o_reg[12]_2\ => u_ddr_prbs_gen_n_11,
      \dout_o_reg[12]_3\ => u_ddr_prbs_gen_n_12,
      \dout_o_reg[12]_4\ => u_ddr_prbs_gen_n_35,
      \dout_o_reg[12]_5\ => u_ddr_prbs_gen_n_36,
      \dout_o_reg[13]_0\ => u_ddr_prbs_gen_n_13,
      \dout_o_reg[13]_1\ => u_ddr_prbs_gen_n_14,
      \dout_o_reg[13]_2\ => u_ddr_prbs_gen_n_15,
      \dout_o_reg[13]_3\ => u_ddr_prbs_gen_n_16,
      \dout_o_reg[14]_0\ => u_ddr_prbs_gen_n_17,
      \dout_o_reg[14]_1\ => u_ddr_prbs_gen_n_18,
      \dout_o_reg[15]_0\ => u_ddr_prbs_gen_n_41,
      \dout_o_reg[15]_1\ => u_ddr_prbs_gen_n_43,
      \dout_o_reg[15]_2\ => \dout_o_reg[15]\,
      \dout_o_reg[6]_0\ => u_ddr_prbs_gen_n_39,
      \dout_o_reg[8]_0\ => u_ddr_prbs_gen_n_19,
      \dout_o_reg[8]_1\ => u_ddr_prbs_gen_n_20,
      \dout_o_reg[8]_2\ => u_ddr_prbs_gen_n_21,
      \dout_o_reg[8]_3\ => u_ddr_prbs_gen_n_22,
      \dout_o_reg[9]_0\ => u_ddr_prbs_gen_n_3,
      \dout_o_reg[9]_1\ => u_ddr_prbs_gen_n_4,
      \dout_o_reg[9]_2\ => u_ddr_prbs_gen_n_24,
      \dout_o_reg[9]_3\ => u_ddr_prbs_gen_n_27,
      first_rdlvl_pat_r => first_rdlvl_pat_r,
      first_wrcal_pat_r => first_wrcal_pat_r,
      first_wrcal_pat_r_reg => u_ddr_prbs_gen_n_1,
      first_wrcal_pat_r_reg_0 => u_ddr_prbs_gen_n_2,
      if_empty => if_empty,
      phy_if_empty_r_reg_0 => u_ddr_prbs_gen_n_0,
      prbs_out(63 downto 56) => prbs_out(511 downto 504),
      prbs_out(55 downto 48) => prbs_out(447 downto 440),
      prbs_out(47 downto 40) => prbs_out(383 downto 376),
      prbs_out(39 downto 32) => prbs_out(319 downto 312),
      prbs_out(31 downto 24) => prbs_out(255 downto 248),
      prbs_out(23 downto 16) => prbs_out(191 downto 184),
      prbs_out(15 downto 8) => prbs_out(127 downto 120),
      prbs_out(7 downto 0) => prbs_out(63 downto 56),
      \rd_addr_reg[0]_0\ => u_ddr_phy_init_n_688,
      \rd_addr_reg[3]_0\ => u_ddr_phy_init_n_687,
      rdlvl_stg1_done_int_reg => u_ddr_prbs_gen_n_23,
      rdlvl_stg1_done_int_reg_0 => u_ddr_prbs_gen_n_25,
      rdlvl_stg1_done_int_reg_1 => u_ddr_prbs_gen_n_26,
      rdlvl_stg1_done_int_reg_2 => u_ddr_prbs_gen_n_28,
      rdlvl_stg1_done_int_reg_3 => u_ddr_prbs_gen_n_30,
      rdlvl_stg1_done_int_reg_4 => u_ddr_prbs_gen_n_32,
      rdlvl_stg1_done_int_reg_5 => u_ddr_prbs_gen_n_37,
      rdlvl_stg1_done_int_reg_6 => u_ddr_prbs_gen_n_38,
      \victim_sel_rotate.sel_reg[56]_0\(0) => \rdlvl_dqs_tap_cnt_r_reg[0][0][2]\(0),
      wrcal_done_reg => u_ddr_prbs_gen_n_40,
      wrcal_done_reg_0 => u_ddr_prbs_gen_n_42,
      wrcal_done_reg_1 => u_ddr_prbs_gen_n_44,
      \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[511]\ => u_ddr_phy_wrcal_n_3,
      \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[511]_0\ => \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_10\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mig_mig_7series_v4_2_rank_common is
  port (
    maint_prescaler_tick_r : out STD_LOGIC;
    \maintenance_request.maint_sre_r_lcl_reg_0\ : out STD_LOGIC;
    \maintenance_request.upd_last_master_r_reg_0\ : out STD_LOGIC;
    \maintenance_request.new_maint_rank_r_reg_0\ : out STD_LOGIC;
    maint_req_r : out STD_LOGIC;
    \periodic_read_request.upd_last_master_r\ : out STD_LOGIC;
    app_ref_ack : out STD_LOGIC;
    app_zq_ack : out STD_LOGIC;
    \zq_cntrl.zq_request_logic.zq_request_r_reg_0\ : out STD_LOGIC;
    \maintenance_request.maint_srx_r_lcl_reg_0\ : out STD_LOGIC;
    \sr_cntrl.sre_request_logic.sre_request_r_reg_0\ : out STD_LOGIC;
    \maintenance_request.maint_zq_r_lcl_reg_0\ : out STD_LOGIC;
    periodic_rd_r : out STD_LOGIC;
    app_ref_r : out STD_LOGIC;
    app_zq_r : out STD_LOGIC;
    \periodic_read_request.periodic_rd_r_cnt\ : out STD_LOGIC;
    \periodic_read_request.periodic_rd_grant_r\ : out STD_LOGIC;
    app_sr_active : out STD_LOGIC;
    maint_ref_zq_wip : out STD_LOGIC;
    Q : out STD_LOGIC_VECTOR ( 4 downto 0 );
    \init_calib_complete_reg_rep__26\ : out STD_LOGIC;
    \refresh_timer.refresh_timer_r_reg[5]_0\ : out STD_LOGIC;
    \refresh_timer.refresh_timer_r_reg[1]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \init_calib_complete_reg_rep__26_0\ : out STD_LOGIC;
    mc_cke_ns : out STD_LOGIC_VECTOR ( 0 to 0 );
    \grant_r_reg[2]\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
    \last_master_r_reg[2]\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
    S : out STD_LOGIC_VECTOR ( 3 downto 0 );
    \zq_cntrl.zq_timer.zq_timer_r_reg[7]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
    \zq_cntrl.zq_timer.zq_timer_r_reg[11]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
    \zq_cntrl.zq_timer.zq_timer_r_reg[15]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
    \zq_cntrl.zq_timer.zq_timer_r_reg[19]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
    \maintenance_request.maint_srx_r_lcl_reg_1\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    \maintenance_request.maint_sre_r_lcl_reg_1\ : out STD_LOGIC;
    \last_master_r_reg[2]_0\ : in STD_LOGIC;
    \maintenance_request.upd_last_master_r_reg_1\ : in STD_LOGIC;
    \zq_cntrl.zq_request_logic.zq_request_r_reg_1\ : in STD_LOGIC;
    \zq_cntrl.zq_request_logic.zq_request_r_reg_2\ : in STD_LOGIC;
    SR : in STD_LOGIC_VECTOR ( 0 to 0 );
    \sr_cntrl.sre_request_logic.sre_request_r_reg_1\ : in STD_LOGIC;
    \periodic_read_request.periodic_rd_r_lcl_reg_0\ : in STD_LOGIC;
    \periodic_read_request.periodic_rd_r_lcl_reg_1\ : in STD_LOGIC;
    app_ref_r_reg_0 : in STD_LOGIC;
    app_zq_r_reg_0 : in STD_LOGIC;
    \periodic_read_request.periodic_rd_r_cnt_reg_0\ : in STD_LOGIC;
    \periodic_read_request.periodic_rd_r_cnt_reg_1\ : in STD_LOGIC;
    \periodic_read_request.periodic_rd_grant_r_reg[0]_0\ : in STD_LOGIC;
    app_sr_active_r_reg_0 : in STD_LOGIC;
    maint_ref_zq_wip_r_reg_0 : in STD_LOGIC;
    O : in STD_LOGIC_VECTOR ( 3 downto 0 );
    \zq_cntrl.zq_timer.zq_timer_r_reg[7]_1\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
    \zq_cntrl.zq_timer.zq_timer_r_reg[11]_1\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
    \zq_cntrl.zq_timer.zq_timer_r_reg[15]_1\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
    \zq_cntrl.zq_timer.zq_timer_r_reg[19]_1\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
    \grant_r_reg[0]\ : in STD_LOGIC;
    \grant_r_reg[0]_0\ : in STD_LOGIC;
    app_ref_req : in STD_LOGIC;
    insert_maint_r1 : in STD_LOGIC;
    cke_r : in STD_LOGIC;
    app_sr_req : in STD_LOGIC;
    \last_master_r_reg[2]_1\ : in STD_LOGIC;
    D : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \grant_r_reg[2]_0\ : in STD_LOGIC;
    \periodic_rd_generation.periodic_rd_request_r\ : in STD_LOGIC;
    \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[0]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[0]_0\ : in STD_LOGIC;
    SS : in STD_LOGIC_VECTOR ( 0 to 0 );
    \maint_prescaler.maint_prescaler_r_reg[1]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \refresh_timer.refresh_timer_r_reg[5]_1\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \refresh_timer.refresh_timer_r_reg[1]_1\ : in STD_LOGIC_VECTOR ( 0 to 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of mig_mig_7series_v4_2_rank_common : entity is "mig_7series_v4_2_rank_common";
end mig_mig_7series_v4_2_rank_common;

architecture STRUCTURE of mig_mig_7series_v4_2_rank_common is
  signal \^q\ : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal app_ref_ack_ns : STD_LOGIC;
  signal \^app_ref_r\ : STD_LOGIC;
  signal app_zq_ack_ns : STD_LOGIC;
  signal \^app_zq_r\ : STD_LOGIC;
  signal \i___13_i_2_n_0\ : STD_LOGIC;
  signal \^init_calib_complete_reg_rep__26_0\ : STD_LOGIC;
  signal \maint_prescaler.maint_prescaler_r0\ : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal \maint_prescaler.maint_prescaler_tick_ns\ : STD_LOGIC;
  signal \^maint_prescaler_tick_r\ : STD_LOGIC;
  signal \maintenance_request.maint_arb0_n_4\ : STD_LOGIC;
  signal \maintenance_request.maint_arb0_n_8\ : STD_LOGIC;
  signal \maintenance_request.maint_sre_ns\ : STD_LOGIC;
  signal \^maintenance_request.maint_sre_r_lcl_reg_0\ : STD_LOGIC;
  signal \^maintenance_request.maint_srx_r_lcl_reg_0\ : STD_LOGIC;
  signal \^maintenance_request.maint_zq_r_lcl_reg_0\ : STD_LOGIC;
  signal \^maintenance_request.new_maint_rank_r_reg_0\ : STD_LOGIC;
  signal \^maintenance_request.upd_last_master_r_reg_0\ : STD_LOGIC;
  signal \^periodic_rd_r\ : STD_LOGIC;
  signal \periodic_read_request.upd_last_master_ns\ : STD_LOGIC;
  signal \^periodic_read_request.upd_last_master_r\ : STD_LOGIC;
  signal \refresh_generation.refresh_bank_r[0]_i_2_n_0\ : STD_LOGIC;
  signal \refresh_timer.refresh_timer_r0\ : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal \refresh_timer.refresh_timer_r0_0\ : STD_LOGIC;
  signal \refresh_timer.refresh_timer_r[5]_i_3_n_0\ : STD_LOGIC;
  signal \refresh_timer.refresh_timer_r_reg\ : STD_LOGIC_VECTOR ( 5 downto 2 );
  signal \^refresh_timer.refresh_timer_r_reg[1]_0\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \^refresh_timer.refresh_timer_r_reg[5]_0\ : STD_LOGIC;
  signal sel : STD_LOGIC;
  signal \sr_cntrl.ckesr_timer.ckesr_timer_r\ : STD_LOGIC;
  signal \sr_cntrl.ckesr_timer.ckesr_timer_r[0]_i_1_n_0\ : STD_LOGIC;
  signal \^sr_cntrl.sre_request_logic.sre_request_r_reg_0\ : STD_LOGIC;
  signal \^zq_cntrl.zq_request_logic.zq_request_r_reg_0\ : STD_LOGIC;
  signal \zq_cntrl.zq_timer.zq_timer_r0\ : STD_LOGIC;
  signal \zq_cntrl.zq_timer.zq_timer_r[0]_i_10_n_0\ : STD_LOGIC;
  signal \zq_cntrl.zq_timer.zq_timer_r[0]_i_11_n_0\ : STD_LOGIC;
  signal \zq_cntrl.zq_timer.zq_timer_r[0]_i_12_n_0\ : STD_LOGIC;
  signal \zq_cntrl.zq_timer.zq_timer_r[0]_i_2_n_0\ : STD_LOGIC;
  signal \zq_cntrl.zq_timer.zq_timer_r[0]_i_4_n_0\ : STD_LOGIC;
  signal \zq_cntrl.zq_timer.zq_timer_r[0]_i_9_n_0\ : STD_LOGIC;
  signal \zq_cntrl.zq_timer.zq_timer_r_reg\ : STD_LOGIC_VECTOR ( 19 downto 0 );
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of app_ref_ack_r_i_1 : label is "soft_lutpair1205";
  attribute SOFT_HLUTNM of app_zq_ack_r_i_1 : label is "soft_lutpair1205";
  attribute SOFT_HLUTNM of cke_r_i_1 : label is "soft_lutpair1202";
  attribute SOFT_HLUTNM of \maint_prescaler.maint_prescaler_r[0]_i_1\ : label is "soft_lutpair1203";
  attribute SOFT_HLUTNM of \maint_prescaler.maint_prescaler_r[2]_i_1\ : label is "soft_lutpair1201";
  attribute SOFT_HLUTNM of \maint_prescaler.maint_prescaler_r[3]_i_1\ : label is "soft_lutpair1203";
  attribute SOFT_HLUTNM of \maint_prescaler.maint_prescaler_r[4]_i_2\ : label is "soft_lutpair1201";
  attribute SOFT_HLUTNM of \refresh_generation.refresh_bank_r[0]_i_2\ : label is "soft_lutpair1202";
  attribute SOFT_HLUTNM of \refresh_timer.refresh_timer_r[2]_i_1\ : label is "soft_lutpair1204";
  attribute SOFT_HLUTNM of \refresh_timer.refresh_timer_r[3]_i_1\ : label is "soft_lutpair1200";
  attribute SOFT_HLUTNM of \refresh_timer.refresh_timer_r[4]_i_1\ : label is "soft_lutpair1200";
  attribute SOFT_HLUTNM of \refresh_timer.refresh_timer_r[5]_i_3\ : label is "soft_lutpair1204";
begin
  Q(4 downto 0) <= \^q\(4 downto 0);
  app_ref_r <= \^app_ref_r\;
  app_zq_r <= \^app_zq_r\;
  \init_calib_complete_reg_rep__26_0\ <= \^init_calib_complete_reg_rep__26_0\;
  maint_prescaler_tick_r <= \^maint_prescaler_tick_r\;
  \maintenance_request.maint_sre_r_lcl_reg_0\ <= \^maintenance_request.maint_sre_r_lcl_reg_0\;
  \maintenance_request.maint_srx_r_lcl_reg_0\ <= \^maintenance_request.maint_srx_r_lcl_reg_0\;
  \maintenance_request.maint_zq_r_lcl_reg_0\ <= \^maintenance_request.maint_zq_r_lcl_reg_0\;
  \maintenance_request.new_maint_rank_r_reg_0\ <= \^maintenance_request.new_maint_rank_r_reg_0\;
  \maintenance_request.upd_last_master_r_reg_0\ <= \^maintenance_request.upd_last_master_r_reg_0\;
  periodic_rd_r <= \^periodic_rd_r\;
  \periodic_read_request.upd_last_master_r\ <= \^periodic_read_request.upd_last_master_r\;
  \refresh_timer.refresh_timer_r_reg[1]_0\(1 downto 0) <= \^refresh_timer.refresh_timer_r_reg[1]_0\(1 downto 0);
  \refresh_timer.refresh_timer_r_reg[5]_0\ <= \^refresh_timer.refresh_timer_r_reg[5]_0\;
  \sr_cntrl.sre_request_logic.sre_request_r_reg_0\ <= \^sr_cntrl.sre_request_logic.sre_request_r_reg_0\;
  \zq_cntrl.zq_request_logic.zq_request_r_reg_0\ <= \^zq_cntrl.zq_request_logic.zq_request_r_reg_0\;
app_ref_ack_r_i_1: unisim.vcomponents.LUT3
    generic map(
      INIT => X"8A"
    )
        port map (
      I0 => \^app_ref_r\,
      I1 => \grant_r_reg[0]_0\,
      I2 => \grant_r_reg[0]\,
      O => app_ref_ack_ns
    );
app_ref_ack_r_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \last_master_r_reg[2]_0\,
      CE => '1',
      D => app_ref_ack_ns,
      Q => app_ref_ack,
      R => '0'
    );
app_ref_r_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \last_master_r_reg[2]_0\,
      CE => '1',
      D => app_ref_r_reg_0,
      Q => \^app_ref_r\,
      R => \periodic_read_request.periodic_rd_r_lcl_reg_0\
    );
app_sr_active_r_reg: unisim.vcomponents.FDRE
     port map (
      C => \last_master_r_reg[2]_0\,
      CE => '1',
      D => app_sr_active_r_reg_0,
      Q => app_sr_active,
      R => '0'
    );
app_zq_ack_r_i_1: unisim.vcomponents.LUT3
    generic map(
      INIT => X"2A"
    )
        port map (
      I0 => \^app_zq_r\,
      I1 => \grant_r_reg[0]\,
      I2 => \^zq_cntrl.zq_request_logic.zq_request_r_reg_0\,
      O => app_zq_ack_ns
    );
app_zq_ack_r_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \last_master_r_reg[2]_0\,
      CE => '1',
      D => app_zq_ack_ns,
      Q => app_zq_ack,
      R => '0'
    );
app_zq_r_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \last_master_r_reg[2]_0\,
      CE => '1',
      D => app_zq_r_reg_0,
      Q => \^app_zq_r\,
      R => \periodic_read_request.periodic_rd_r_lcl_reg_0\
    );
cke_r_i_1: unisim.vcomponents.LUT4
    generic map(
      INIT => X"3F20"
    )
        port map (
      I0 => \^maintenance_request.maint_srx_r_lcl_reg_0\,
      I1 => \^maintenance_request.maint_sre_r_lcl_reg_0\,
      I2 => insert_maint_r1,
      I3 => cke_r,
      O => mc_cke_ns(0)
    );
\i___13_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000040000"
    )
        port map (
      I0 => \refresh_timer.refresh_timer_r_reg\(5),
      I1 => \^maint_prescaler_tick_r\,
      I2 => \refresh_timer.refresh_timer_r_reg\(2),
      I3 => \^refresh_timer.refresh_timer_r_reg[1]_0\(1),
      I4 => \^refresh_timer.refresh_timer_r_reg[1]_0\(0),
      I5 => \i___13_i_2_n_0\,
      O => \^refresh_timer.refresh_timer_r_reg[5]_0\
    );
\i___13_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => \refresh_timer.refresh_timer_r_reg\(3),
      I1 => \refresh_timer.refresh_timer_r_reg\(4),
      O => \i___13_i_2_n_0\
    );
\i___14_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"8AAAAAAA"
    )
        port map (
      I0 => \grant_r_reg[0]\,
      I1 => \zq_cntrl.zq_timer.zq_timer_r_reg\(1),
      I2 => \zq_cntrl.zq_timer.zq_timer_r_reg\(0),
      I3 => \^maint_prescaler_tick_r\,
      I4 => \zq_cntrl.zq_timer.zq_timer_r[0]_i_4_n_0\,
      O => \^init_calib_complete_reg_rep__26_0\
    );
\maint_prescaler.maint_prescaler_r[0]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \^q\(0),
      O => \maint_prescaler.maint_prescaler_r0\(0)
    );
\maint_prescaler.maint_prescaler_r[2]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"A9"
    )
        port map (
      I0 => \^q\(2),
      I1 => \^q\(1),
      I2 => \^q\(0),
      O => \maint_prescaler.maint_prescaler_r0\(2)
    );
\maint_prescaler.maint_prescaler_r[3]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"AAA9"
    )
        port map (
      I0 => \^q\(3),
      I1 => \^q\(2),
      I2 => \^q\(0),
      I3 => \^q\(1),
      O => \maint_prescaler.maint_prescaler_r0\(3)
    );
\maint_prescaler.maint_prescaler_r[4]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFFFFE"
    )
        port map (
      I0 => \^q\(4),
      I1 => \^q\(3),
      I2 => \^q\(1),
      I3 => \^q\(0),
      I4 => \^q\(2),
      O => sel
    );
\maint_prescaler.maint_prescaler_r[4]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AAAAAAA9"
    )
        port map (
      I0 => \^q\(4),
      I1 => \^q\(3),
      I2 => \^q\(1),
      I3 => \^q\(0),
      I4 => \^q\(2),
      O => \maint_prescaler.maint_prescaler_r0\(4)
    );
\maint_prescaler.maint_prescaler_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \last_master_r_reg[2]_0\,
      CE => sel,
      D => \maint_prescaler.maint_prescaler_r0\(0),
      Q => \^q\(0),
      R => SS(0)
    );
\maint_prescaler.maint_prescaler_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \last_master_r_reg[2]_0\,
      CE => sel,
      D => \maint_prescaler.maint_prescaler_r_reg[1]_0\(0),
      Q => \^q\(1),
      R => SS(0)
    );
\maint_prescaler.maint_prescaler_r_reg[2]\: unisim.vcomponents.FDSE
     port map (
      C => \last_master_r_reg[2]_0\,
      CE => sel,
      D => \maint_prescaler.maint_prescaler_r0\(2),
      Q => \^q\(2),
      S => SS(0)
    );
\maint_prescaler.maint_prescaler_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => \last_master_r_reg[2]_0\,
      CE => sel,
      D => \maint_prescaler.maint_prescaler_r0\(3),
      Q => \^q\(3),
      R => SS(0)
    );
\maint_prescaler.maint_prescaler_r_reg[4]\: unisim.vcomponents.FDSE
     port map (
      C => \last_master_r_reg[2]_0\,
      CE => sel,
      D => \maint_prescaler.maint_prescaler_r0\(4),
      Q => \^q\(4),
      S => SS(0)
    );
\maint_prescaler.maint_prescaler_tick_r_lcl_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000100"
    )
        port map (
      I0 => \^q\(4),
      I1 => \^q\(3),
      I2 => \^q\(1),
      I3 => \^q\(0),
      I4 => \^q\(2),
      O => \maint_prescaler.maint_prescaler_tick_ns\
    );
\maint_prescaler.maint_prescaler_tick_r_lcl_reg\: unisim.vcomponents.FDRE
     port map (
      C => \last_master_r_reg[2]_0\,
      CE => '1',
      D => \maint_prescaler.maint_prescaler_tick_ns\,
      Q => \^maint_prescaler_tick_r\,
      R => '0'
    );
maint_ref_zq_wip_r_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \last_master_r_reg[2]_0\,
      CE => '1',
      D => maint_ref_zq_wip_r_reg_0,
      Q => maint_ref_zq_wip,
      R => \periodic_read_request.periodic_rd_r_cnt_reg_0\
    );
\maintenance_request.maint_arb0\: entity work.mig_mig_7series_v4_2_round_robin_arb
     port map (
      D(1 downto 0) => D(1 downto 0),
      Q(2 downto 0) => \grant_r_reg[2]\(2 downto 0),
      app_sr_req => app_sr_req,
      \grant_r_reg[0]_0\ => \grant_r_reg[0]\,
      \grant_r_reg[0]_1\ => \grant_r_reg[0]_0\,
      \grant_r_reg[0]_2\ => \^zq_cntrl.zq_request_logic.zq_request_r_reg_0\,
      \grant_r_reg[0]_3\ => \^sr_cntrl.sre_request_logic.sre_request_r_reg_0\,
      \grant_r_reg[2]_0\ => \grant_r_reg[2]_0\,
      \last_master_r_reg[2]_0\(2 downto 0) => \last_master_r_reg[2]\(2 downto 0),
      \last_master_r_reg[2]_1\ => \last_master_r_reg[2]_1\,
      \last_master_r_reg[2]_2\ => \^maintenance_request.upd_last_master_r_reg_0\,
      \last_master_r_reg[2]_3\ => \^maintenance_request.new_maint_rank_r_reg_0\,
      \last_master_r_reg[2]_4\ => \last_master_r_reg[2]_0\,
      \maintenance_request.maint_sre_ns\ => \maintenance_request.maint_sre_ns\,
      \maintenance_request.maint_sre_r_lcl_reg\ => \maintenance_request.maint_arb0_n_4\,
      \maintenance_request.maint_sre_r_lcl_reg_0\ => \^maintenance_request.maint_sre_r_lcl_reg_0\,
      \maintenance_request.maint_srx_r_lcl_reg\ => \^maintenance_request.maint_srx_r_lcl_reg_0\,
      \maintenance_request.maint_zq_r_lcl_reg\ => \maintenance_request.maint_arb0_n_8\,
      \maintenance_request.maint_zq_r_lcl_reg_0\ => \^maintenance_request.maint_zq_r_lcl_reg_0\,
      \sr_cntrl.ckesr_timer.ckesr_timer_r\ => \sr_cntrl.ckesr_timer.ckesr_timer_r\
    );
\maintenance_request.maint_req_r_lcl_reg\: unisim.vcomponents.FDRE
     port map (
      C => \last_master_r_reg[2]_0\,
      CE => '1',
      D => \^maintenance_request.new_maint_rank_r_reg_0\,
      Q => maint_req_r,
      R => '0'
    );
\maintenance_request.maint_sre_r_lcl_reg\: unisim.vcomponents.FDRE
     port map (
      C => \last_master_r_reg[2]_0\,
      CE => '1',
      D => \maintenance_request.maint_sre_ns\,
      Q => \^maintenance_request.maint_sre_r_lcl_reg_0\,
      R => '0'
    );
\maintenance_request.maint_srx_r_lcl_reg\: unisim.vcomponents.FDRE
     port map (
      C => \last_master_r_reg[2]_0\,
      CE => '1',
      D => \maintenance_request.maint_arb0_n_4\,
      Q => \^maintenance_request.maint_srx_r_lcl_reg_0\,
      R => SR(0)
    );
\maintenance_request.maint_zq_r_lcl_reg\: unisim.vcomponents.FDRE
     port map (
      C => \last_master_r_reg[2]_0\,
      CE => '1',
      D => \maintenance_request.maint_arb0_n_8\,
      Q => \^maintenance_request.maint_zq_r_lcl_reg_0\,
      R => SR(0)
    );
\maintenance_request.new_maint_rank_r_reg\: unisim.vcomponents.FDRE
     port map (
      C => \last_master_r_reg[2]_0\,
      CE => '1',
      D => \^maintenance_request.upd_last_master_r_reg_0\,
      Q => \^maintenance_request.new_maint_rank_r_reg_0\,
      R => '0'
    );
\maintenance_request.upd_last_master_r_reg\: unisim.vcomponents.FDRE
     port map (
      C => \last_master_r_reg[2]_0\,
      CE => '1',
      D => \maintenance_request.upd_last_master_r_reg_1\,
      Q => \^maintenance_request.upd_last_master_r_reg_0\,
      R => '0'
    );
\periodic_read_request.periodic_rd_grant_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \last_master_r_reg[2]_0\,
      CE => '1',
      D => \periodic_read_request.periodic_rd_grant_r_reg[0]_0\,
      Q => \periodic_read_request.periodic_rd_grant_r\,
      R => '0'
    );
\periodic_read_request.periodic_rd_r_cnt_reg\: unisim.vcomponents.FDRE
     port map (
      C => \last_master_r_reg[2]_0\,
      CE => '1',
      D => \periodic_read_request.periodic_rd_r_cnt_reg_1\,
      Q => \periodic_read_request.periodic_rd_r_cnt\,
      R => \periodic_read_request.periodic_rd_r_cnt_reg_0\
    );
\periodic_read_request.periodic_rd_r_lcl_reg\: unisim.vcomponents.FDRE
     port map (
      C => \last_master_r_reg[2]_0\,
      CE => '1',
      D => \periodic_read_request.periodic_rd_r_lcl_reg_1\,
      Q => \^periodic_rd_r\,
      R => \periodic_read_request.periodic_rd_r_lcl_reg_0\
    );
\periodic_read_request.upd_last_master_r_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0008"
    )
        port map (
      I0 => \periodic_rd_generation.periodic_rd_request_r\,
      I1 => \grant_r_reg[0]\,
      I2 => \^periodic_read_request.upd_last_master_r\,
      I3 => \^periodic_rd_r\,
      O => \periodic_read_request.upd_last_master_ns\
    );
\periodic_read_request.upd_last_master_r_reg\: unisim.vcomponents.FDRE
     port map (
      C => \last_master_r_reg[2]_0\,
      CE => '1',
      D => \periodic_read_request.upd_last_master_ns\,
      Q => \^periodic_read_request.upd_last_master_r\,
      R => '0'
    );
\refresh_generation.refresh_bank_r[0]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88820008"
    )
        port map (
      I0 => \grant_r_reg[0]\,
      I1 => \grant_r_reg[0]_0\,
      I2 => app_ref_req,
      I3 => \^refresh_timer.refresh_timer_r_reg[5]_0\,
      I4 => \refresh_generation.refresh_bank_r[0]_i_2_n_0\,
      O => \init_calib_complete_reg_rep__26\
    );
\refresh_generation.refresh_bank_r[0]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0100"
    )
        port map (
      I0 => \^maintenance_request.maint_sre_r_lcl_reg_0\,
      I1 => \^maintenance_request.maint_zq_r_lcl_reg_0\,
      I2 => \^maintenance_request.maint_srx_r_lcl_reg_0\,
      I3 => insert_maint_r1,
      O => \refresh_generation.refresh_bank_r[0]_i_2_n_0\
    );
\refresh_timer.refresh_timer_r[0]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \^refresh_timer.refresh_timer_r_reg[1]_0\(0),
      O => \refresh_timer.refresh_timer_r0\(0)
    );
\refresh_timer.refresh_timer_r[2]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"A9"
    )
        port map (
      I0 => \refresh_timer.refresh_timer_r_reg\(2),
      I1 => \^refresh_timer.refresh_timer_r_reg[1]_0\(1),
      I2 => \^refresh_timer.refresh_timer_r_reg[1]_0\(0),
      O => \refresh_timer.refresh_timer_r0\(2)
    );
\refresh_timer.refresh_timer_r[3]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"AAA9"
    )
        port map (
      I0 => \refresh_timer.refresh_timer_r_reg\(3),
      I1 => \refresh_timer.refresh_timer_r_reg\(2),
      I2 => \^refresh_timer.refresh_timer_r_reg[1]_0\(0),
      I3 => \^refresh_timer.refresh_timer_r_reg[1]_0\(1),
      O => \refresh_timer.refresh_timer_r0\(3)
    );
\refresh_timer.refresh_timer_r[4]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AAAAAAA9"
    )
        port map (
      I0 => \refresh_timer.refresh_timer_r_reg\(4),
      I1 => \refresh_timer.refresh_timer_r_reg\(3),
      I2 => \^refresh_timer.refresh_timer_r_reg[1]_0\(1),
      I3 => \^refresh_timer.refresh_timer_r_reg[1]_0\(0),
      I4 => \refresh_timer.refresh_timer_r_reg\(2),
      O => \refresh_timer.refresh_timer_r0\(4)
    );
\refresh_timer.refresh_timer_r[5]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AAAAAA8A"
    )
        port map (
      I0 => \^maint_prescaler_tick_r\,
      I1 => \refresh_timer.refresh_timer_r_reg\(5),
      I2 => \refresh_timer.refresh_timer_r[5]_i_3_n_0\,
      I3 => \refresh_timer.refresh_timer_r_reg\(4),
      I4 => \refresh_timer.refresh_timer_r_reg\(3),
      O => \refresh_timer.refresh_timer_r0_0\
    );
\refresh_timer.refresh_timer_r[5]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAAAAAAAAAA9"
    )
        port map (
      I0 => \refresh_timer.refresh_timer_r_reg\(5),
      I1 => \refresh_timer.refresh_timer_r_reg\(3),
      I2 => \refresh_timer.refresh_timer_r_reg\(4),
      I3 => \^refresh_timer.refresh_timer_r_reg[1]_0\(1),
      I4 => \^refresh_timer.refresh_timer_r_reg[1]_0\(0),
      I5 => \refresh_timer.refresh_timer_r_reg\(2),
      O => \refresh_timer.refresh_timer_r0\(5)
    );
\refresh_timer.refresh_timer_r[5]_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"01"
    )
        port map (
      I0 => \^refresh_timer.refresh_timer_r_reg[1]_0\(1),
      I1 => \^refresh_timer.refresh_timer_r_reg[1]_0\(0),
      I2 => \refresh_timer.refresh_timer_r_reg\(2),
      O => \refresh_timer.refresh_timer_r[5]_i_3_n_0\
    );
\refresh_timer.refresh_timer_r_reg[0]\: unisim.vcomponents.FDSE
     port map (
      C => \last_master_r_reg[2]_0\,
      CE => \refresh_timer.refresh_timer_r0_0\,
      D => \refresh_timer.refresh_timer_r0\(0),
      Q => \^refresh_timer.refresh_timer_r_reg[1]_0\(0),
      S => \refresh_timer.refresh_timer_r_reg[5]_1\(0)
    );
\refresh_timer.refresh_timer_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \last_master_r_reg[2]_0\,
      CE => \refresh_timer.refresh_timer_r0_0\,
      D => \refresh_timer.refresh_timer_r_reg[1]_1\(0),
      Q => \^refresh_timer.refresh_timer_r_reg[1]_0\(1),
      R => \refresh_timer.refresh_timer_r_reg[5]_1\(0)
    );
\refresh_timer.refresh_timer_r_reg[2]\: unisim.vcomponents.FDSE
     port map (
      C => \last_master_r_reg[2]_0\,
      CE => \refresh_timer.refresh_timer_r0_0\,
      D => \refresh_timer.refresh_timer_r0\(2),
      Q => \refresh_timer.refresh_timer_r_reg\(2),
      S => \refresh_timer.refresh_timer_r_reg[5]_1\(0)
    );
\refresh_timer.refresh_timer_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => \last_master_r_reg[2]_0\,
      CE => \refresh_timer.refresh_timer_r0_0\,
      D => \refresh_timer.refresh_timer_r0\(3),
      Q => \refresh_timer.refresh_timer_r_reg\(3),
      R => \refresh_timer.refresh_timer_r_reg[5]_1\(0)
    );
\refresh_timer.refresh_timer_r_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => \last_master_r_reg[2]_0\,
      CE => \refresh_timer.refresh_timer_r0_0\,
      D => \refresh_timer.refresh_timer_r0\(4),
      Q => \refresh_timer.refresh_timer_r_reg\(4),
      R => \refresh_timer.refresh_timer_r_reg[5]_1\(0)
    );
\refresh_timer.refresh_timer_r_reg[5]\: unisim.vcomponents.FDSE
     port map (
      C => \last_master_r_reg[2]_0\,
      CE => \refresh_timer.refresh_timer_r0_0\,
      D => \refresh_timer.refresh_timer_r0\(5),
      Q => \refresh_timer.refresh_timer_r_reg\(5),
      S => \refresh_timer.refresh_timer_r_reg[5]_1\(0)
    );
\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r[0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000101000000FF"
    )
        port map (
      I0 => \^maintenance_request.maint_srx_r_lcl_reg_0\,
      I1 => \^maintenance_request.maint_zq_r_lcl_reg_0\,
      I2 => \^maintenance_request.maint_sre_r_lcl_reg_0\,
      I3 => \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[0]\(0),
      I4 => \last_master_r_reg[2]_1\,
      I5 => \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[0]_0\,
      O => \maintenance_request.maint_srx_r_lcl_reg_1\(0)
    );
\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r[3]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000100"
    )
        port map (
      I0 => \^maintenance_request.maint_sre_r_lcl_reg_0\,
      I1 => \^maintenance_request.maint_zq_r_lcl_reg_0\,
      I2 => \^maintenance_request.maint_srx_r_lcl_reg_0\,
      I3 => \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[0]_0\,
      I4 => \last_master_r_reg[2]_1\,
      O => \maintenance_request.maint_sre_r_lcl_reg_1\
    );
\sr_cntrl.ckesr_timer.ckesr_timer_r[0]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^maintenance_request.maint_sre_r_lcl_reg_0\,
      I1 => insert_maint_r1,
      O => \sr_cntrl.ckesr_timer.ckesr_timer_r[0]_i_1_n_0\
    );
\sr_cntrl.ckesr_timer.ckesr_timer_r_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \last_master_r_reg[2]_0\,
      CE => '1',
      D => \sr_cntrl.ckesr_timer.ckesr_timer_r[0]_i_1_n_0\,
      Q => \sr_cntrl.ckesr_timer.ckesr_timer_r\,
      R => '0'
    );
\sr_cntrl.sre_request_logic.sre_request_r_reg\: unisim.vcomponents.FDRE
     port map (
      C => \last_master_r_reg[2]_0\,
      CE => '1',
      D => \sr_cntrl.sre_request_logic.sre_request_r_reg_1\,
      Q => \^sr_cntrl.sre_request_logic.sre_request_r_reg_0\,
      R => SR(0)
    );
\zq_cntrl.zq_request_logic.zq_request_r_reg\: unisim.vcomponents.FDRE
     port map (
      C => \last_master_r_reg[2]_0\,
      CE => '1',
      D => \zq_cntrl.zq_request_logic.zq_request_r_reg_2\,
      Q => \^zq_cntrl.zq_request_logic.zq_request_r_reg_0\,
      R => \zq_cntrl.zq_request_logic.zq_request_r_reg_1\
    );
\zq_cntrl.zq_timer.zq_timer_r[0]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \^init_calib_complete_reg_rep__26_0\,
      O => \zq_cntrl.zq_timer.zq_timer_r0\
    );
\zq_cntrl.zq_timer.zq_timer_r[0]_i_10\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFFE"
    )
        port map (
      I0 => \zq_cntrl.zq_timer.zq_timer_r_reg\(7),
      I1 => \zq_cntrl.zq_timer.zq_timer_r_reg\(6),
      I2 => \zq_cntrl.zq_timer.zq_timer_r_reg\(5),
      I3 => \zq_cntrl.zq_timer.zq_timer_r_reg\(4),
      O => \zq_cntrl.zq_timer.zq_timer_r[0]_i_10_n_0\
    );
\zq_cntrl.zq_timer.zq_timer_r[0]_i_11\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0001"
    )
        port map (
      I0 => \zq_cntrl.zq_timer.zq_timer_r_reg\(19),
      I1 => \zq_cntrl.zq_timer.zq_timer_r_reg\(17),
      I2 => \zq_cntrl.zq_timer.zq_timer_r_reg\(18),
      I3 => \zq_cntrl.zq_timer.zq_timer_r_reg\(16),
      O => \zq_cntrl.zq_timer.zq_timer_r[0]_i_11_n_0\
    );
\zq_cntrl.zq_timer.zq_timer_r[0]_i_12\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFFE"
    )
        port map (
      I0 => \zq_cntrl.zq_timer.zq_timer_r_reg\(14),
      I1 => \zq_cntrl.zq_timer.zq_timer_r_reg\(13),
      I2 => \zq_cntrl.zq_timer.zq_timer_r_reg\(15),
      I3 => \zq_cntrl.zq_timer.zq_timer_r_reg\(12),
      O => \zq_cntrl.zq_timer.zq_timer_r[0]_i_12_n_0\
    );
\zq_cntrl.zq_timer.zq_timer_r[0]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"A8AA"
    )
        port map (
      I0 => \^maint_prescaler_tick_r\,
      I1 => \zq_cntrl.zq_timer.zq_timer_r_reg\(1),
      I2 => \zq_cntrl.zq_timer.zq_timer_r_reg\(0),
      I3 => \zq_cntrl.zq_timer.zq_timer_r[0]_i_4_n_0\,
      O => \zq_cntrl.zq_timer.zq_timer_r[0]_i_2_n_0\
    );
\zq_cntrl.zq_timer.zq_timer_r[0]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000000010"
    )
        port map (
      I0 => \zq_cntrl.zq_timer.zq_timer_r[0]_i_9_n_0\,
      I1 => \zq_cntrl.zq_timer.zq_timer_r[0]_i_10_n_0\,
      I2 => \zq_cntrl.zq_timer.zq_timer_r[0]_i_11_n_0\,
      I3 => \zq_cntrl.zq_timer.zq_timer_r[0]_i_12_n_0\,
      I4 => \zq_cntrl.zq_timer.zq_timer_r_reg\(3),
      I5 => \zq_cntrl.zq_timer.zq_timer_r_reg\(2),
      O => \zq_cntrl.zq_timer.zq_timer_r[0]_i_4_n_0\
    );
\zq_cntrl.zq_timer.zq_timer_r[0]_i_5\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \zq_cntrl.zq_timer.zq_timer_r_reg\(3),
      O => S(3)
    );
\zq_cntrl.zq_timer.zq_timer_r[0]_i_6\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \zq_cntrl.zq_timer.zq_timer_r_reg\(2),
      O => S(2)
    );
\zq_cntrl.zq_timer.zq_timer_r[0]_i_7\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \zq_cntrl.zq_timer.zq_timer_r_reg\(1),
      O => S(1)
    );
\zq_cntrl.zq_timer.zq_timer_r[0]_i_8\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \zq_cntrl.zq_timer.zq_timer_r_reg\(0),
      O => S(0)
    );
\zq_cntrl.zq_timer.zq_timer_r[0]_i_9\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFFE"
    )
        port map (
      I0 => \zq_cntrl.zq_timer.zq_timer_r_reg\(10),
      I1 => \zq_cntrl.zq_timer.zq_timer_r_reg\(9),
      I2 => \zq_cntrl.zq_timer.zq_timer_r_reg\(11),
      I3 => \zq_cntrl.zq_timer.zq_timer_r_reg\(8),
      O => \zq_cntrl.zq_timer.zq_timer_r[0]_i_9_n_0\
    );
\zq_cntrl.zq_timer.zq_timer_r[12]_i_2\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \zq_cntrl.zq_timer.zq_timer_r_reg\(15),
      O => \zq_cntrl.zq_timer.zq_timer_r_reg[15]_0\(3)
    );
\zq_cntrl.zq_timer.zq_timer_r[12]_i_3\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \zq_cntrl.zq_timer.zq_timer_r_reg\(14),
      O => \zq_cntrl.zq_timer.zq_timer_r_reg[15]_0\(2)
    );
\zq_cntrl.zq_timer.zq_timer_r[12]_i_4\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \zq_cntrl.zq_timer.zq_timer_r_reg\(13),
      O => \zq_cntrl.zq_timer.zq_timer_r_reg[15]_0\(1)
    );
\zq_cntrl.zq_timer.zq_timer_r[12]_i_5\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \zq_cntrl.zq_timer.zq_timer_r_reg\(12),
      O => \zq_cntrl.zq_timer.zq_timer_r_reg[15]_0\(0)
    );
\zq_cntrl.zq_timer.zq_timer_r[16]_i_2\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \zq_cntrl.zq_timer.zq_timer_r_reg\(19),
      O => \zq_cntrl.zq_timer.zq_timer_r_reg[19]_0\(3)
    );
\zq_cntrl.zq_timer.zq_timer_r[16]_i_3\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \zq_cntrl.zq_timer.zq_timer_r_reg\(18),
      O => \zq_cntrl.zq_timer.zq_timer_r_reg[19]_0\(2)
    );
\zq_cntrl.zq_timer.zq_timer_r[16]_i_4\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \zq_cntrl.zq_timer.zq_timer_r_reg\(17),
      O => \zq_cntrl.zq_timer.zq_timer_r_reg[19]_0\(1)
    );
\zq_cntrl.zq_timer.zq_timer_r[16]_i_5\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \zq_cntrl.zq_timer.zq_timer_r_reg\(16),
      O => \zq_cntrl.zq_timer.zq_timer_r_reg[19]_0\(0)
    );
\zq_cntrl.zq_timer.zq_timer_r[4]_i_2\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \zq_cntrl.zq_timer.zq_timer_r_reg\(7),
      O => \zq_cntrl.zq_timer.zq_timer_r_reg[7]_0\(3)
    );
\zq_cntrl.zq_timer.zq_timer_r[4]_i_3\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \zq_cntrl.zq_timer.zq_timer_r_reg\(6),
      O => \zq_cntrl.zq_timer.zq_timer_r_reg[7]_0\(2)
    );
\zq_cntrl.zq_timer.zq_timer_r[4]_i_4\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \zq_cntrl.zq_timer.zq_timer_r_reg\(5),
      O => \zq_cntrl.zq_timer.zq_timer_r_reg[7]_0\(1)
    );
\zq_cntrl.zq_timer.zq_timer_r[4]_i_5\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \zq_cntrl.zq_timer.zq_timer_r_reg\(4),
      O => \zq_cntrl.zq_timer.zq_timer_r_reg[7]_0\(0)
    );
\zq_cntrl.zq_timer.zq_timer_r[8]_i_2\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \zq_cntrl.zq_timer.zq_timer_r_reg\(11),
      O => \zq_cntrl.zq_timer.zq_timer_r_reg[11]_0\(3)
    );
\zq_cntrl.zq_timer.zq_timer_r[8]_i_3\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \zq_cntrl.zq_timer.zq_timer_r_reg\(10),
      O => \zq_cntrl.zq_timer.zq_timer_r_reg[11]_0\(2)
    );
\zq_cntrl.zq_timer.zq_timer_r[8]_i_4\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \zq_cntrl.zq_timer.zq_timer_r_reg\(9),
      O => \zq_cntrl.zq_timer.zq_timer_r_reg[11]_0\(1)
    );
\zq_cntrl.zq_timer.zq_timer_r[8]_i_5\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \zq_cntrl.zq_timer.zq_timer_r_reg\(8),
      O => \zq_cntrl.zq_timer.zq_timer_r_reg[11]_0\(0)
    );
\zq_cntrl.zq_timer.zq_timer_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \last_master_r_reg[2]_0\,
      CE => \zq_cntrl.zq_timer.zq_timer_r[0]_i_2_n_0\,
      D => O(0),
      Q => \zq_cntrl.zq_timer.zq_timer_r_reg\(0),
      R => \zq_cntrl.zq_timer.zq_timer_r0\
    );
\zq_cntrl.zq_timer.zq_timer_r_reg[10]\: unisim.vcomponents.FDSE
     port map (
      C => \last_master_r_reg[2]_0\,
      CE => \zq_cntrl.zq_timer.zq_timer_r[0]_i_2_n_0\,
      D => \zq_cntrl.zq_timer.zq_timer_r_reg[11]_1\(2),
      Q => \zq_cntrl.zq_timer.zq_timer_r_reg\(10),
      S => \zq_cntrl.zq_timer.zq_timer_r0\
    );
\zq_cntrl.zq_timer.zq_timer_r_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => \last_master_r_reg[2]_0\,
      CE => \zq_cntrl.zq_timer.zq_timer_r[0]_i_2_n_0\,
      D => \zq_cntrl.zq_timer.zq_timer_r_reg[11]_1\(3),
      Q => \zq_cntrl.zq_timer.zq_timer_r_reg\(11),
      R => \zq_cntrl.zq_timer.zq_timer_r0\
    );
\zq_cntrl.zq_timer.zq_timer_r_reg[12]\: unisim.vcomponents.FDRE
     port map (
      C => \last_master_r_reg[2]_0\,
      CE => \zq_cntrl.zq_timer.zq_timer_r[0]_i_2_n_0\,
      D => \zq_cntrl.zq_timer.zq_timer_r_reg[15]_1\(0),
      Q => \zq_cntrl.zq_timer.zq_timer_r_reg\(12),
      R => \zq_cntrl.zq_timer.zq_timer_r0\
    );
\zq_cntrl.zq_timer.zq_timer_r_reg[13]\: unisim.vcomponents.FDRE
     port map (
      C => \last_master_r_reg[2]_0\,
      CE => \zq_cntrl.zq_timer.zq_timer_r[0]_i_2_n_0\,
      D => \zq_cntrl.zq_timer.zq_timer_r_reg[15]_1\(1),
      Q => \zq_cntrl.zq_timer.zq_timer_r_reg\(13),
      R => \zq_cntrl.zq_timer.zq_timer_r0\
    );
\zq_cntrl.zq_timer.zq_timer_r_reg[14]\: unisim.vcomponents.FDSE
     port map (
      C => \last_master_r_reg[2]_0\,
      CE => \zq_cntrl.zq_timer.zq_timer_r[0]_i_2_n_0\,
      D => \zq_cntrl.zq_timer.zq_timer_r_reg[15]_1\(2),
      Q => \zq_cntrl.zq_timer.zq_timer_r_reg\(14),
      S => \zq_cntrl.zq_timer.zq_timer_r0\
    );
\zq_cntrl.zq_timer.zq_timer_r_reg[15]\: unisim.vcomponents.FDSE
     port map (
      C => \last_master_r_reg[2]_0\,
      CE => \zq_cntrl.zq_timer.zq_timer_r[0]_i_2_n_0\,
      D => \zq_cntrl.zq_timer.zq_timer_r_reg[15]_1\(3),
      Q => \zq_cntrl.zq_timer.zq_timer_r_reg\(15),
      S => \zq_cntrl.zq_timer.zq_timer_r0\
    );
\zq_cntrl.zq_timer.zq_timer_r_reg[16]\: unisim.vcomponents.FDSE
     port map (
      C => \last_master_r_reg[2]_0\,
      CE => \zq_cntrl.zq_timer.zq_timer_r[0]_i_2_n_0\,
      D => \zq_cntrl.zq_timer.zq_timer_r_reg[19]_1\(0),
      Q => \zq_cntrl.zq_timer.zq_timer_r_reg\(16),
      S => \zq_cntrl.zq_timer.zq_timer_r0\
    );
\zq_cntrl.zq_timer.zq_timer_r_reg[17]\: unisim.vcomponents.FDRE
     port map (
      C => \last_master_r_reg[2]_0\,
      CE => \zq_cntrl.zq_timer.zq_timer_r[0]_i_2_n_0\,
      D => \zq_cntrl.zq_timer.zq_timer_r_reg[19]_1\(1),
      Q => \zq_cntrl.zq_timer.zq_timer_r_reg\(17),
      R => \zq_cntrl.zq_timer.zq_timer_r0\
    );
\zq_cntrl.zq_timer.zq_timer_r_reg[18]\: unisim.vcomponents.FDRE
     port map (
      C => \last_master_r_reg[2]_0\,
      CE => \zq_cntrl.zq_timer.zq_timer_r[0]_i_2_n_0\,
      D => \zq_cntrl.zq_timer.zq_timer_r_reg[19]_1\(2),
      Q => \zq_cntrl.zq_timer.zq_timer_r_reg\(18),
      R => \zq_cntrl.zq_timer.zq_timer_r0\
    );
\zq_cntrl.zq_timer.zq_timer_r_reg[19]\: unisim.vcomponents.FDSE
     port map (
      C => \last_master_r_reg[2]_0\,
      CE => \zq_cntrl.zq_timer.zq_timer_r[0]_i_2_n_0\,
      D => \zq_cntrl.zq_timer.zq_timer_r_reg[19]_1\(3),
      Q => \zq_cntrl.zq_timer.zq_timer_r_reg\(19),
      S => \zq_cntrl.zq_timer.zq_timer_r0\
    );
\zq_cntrl.zq_timer.zq_timer_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \last_master_r_reg[2]_0\,
      CE => \zq_cntrl.zq_timer.zq_timer_r[0]_i_2_n_0\,
      D => O(1),
      Q => \zq_cntrl.zq_timer.zq_timer_r_reg\(1),
      R => \zq_cntrl.zq_timer.zq_timer_r0\
    );
\zq_cntrl.zq_timer.zq_timer_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \last_master_r_reg[2]_0\,
      CE => \zq_cntrl.zq_timer.zq_timer_r[0]_i_2_n_0\,
      D => O(2),
      Q => \zq_cntrl.zq_timer.zq_timer_r_reg\(2),
      R => \zq_cntrl.zq_timer.zq_timer_r0\
    );
\zq_cntrl.zq_timer.zq_timer_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => \last_master_r_reg[2]_0\,
      CE => \zq_cntrl.zq_timer.zq_timer_r[0]_i_2_n_0\,
      D => O(3),
      Q => \zq_cntrl.zq_timer.zq_timer_r_reg\(3),
      R => \zq_cntrl.zq_timer.zq_timer_r0\
    );
\zq_cntrl.zq_timer.zq_timer_r_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => \last_master_r_reg[2]_0\,
      CE => \zq_cntrl.zq_timer.zq_timer_r[0]_i_2_n_0\,
      D => \zq_cntrl.zq_timer.zq_timer_r_reg[7]_1\(0),
      Q => \zq_cntrl.zq_timer.zq_timer_r_reg\(4),
      R => \zq_cntrl.zq_timer.zq_timer_r0\
    );
\zq_cntrl.zq_timer.zq_timer_r_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => \last_master_r_reg[2]_0\,
      CE => \zq_cntrl.zq_timer.zq_timer_r[0]_i_2_n_0\,
      D => \zq_cntrl.zq_timer.zq_timer_r_reg[7]_1\(1),
      Q => \zq_cntrl.zq_timer.zq_timer_r_reg\(5),
      R => \zq_cntrl.zq_timer.zq_timer_r0\
    );
\zq_cntrl.zq_timer.zq_timer_r_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => \last_master_r_reg[2]_0\,
      CE => \zq_cntrl.zq_timer.zq_timer_r[0]_i_2_n_0\,
      D => \zq_cntrl.zq_timer.zq_timer_r_reg[7]_1\(2),
      Q => \zq_cntrl.zq_timer.zq_timer_r_reg\(6),
      R => \zq_cntrl.zq_timer.zq_timer_r0\
    );
\zq_cntrl.zq_timer.zq_timer_r_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => \last_master_r_reg[2]_0\,
      CE => \zq_cntrl.zq_timer.zq_timer_r[0]_i_2_n_0\,
      D => \zq_cntrl.zq_timer.zq_timer_r_reg[7]_1\(3),
      Q => \zq_cntrl.zq_timer.zq_timer_r_reg\(7),
      R => \zq_cntrl.zq_timer.zq_timer_r0\
    );
\zq_cntrl.zq_timer.zq_timer_r_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => \last_master_r_reg[2]_0\,
      CE => \zq_cntrl.zq_timer.zq_timer_r[0]_i_2_n_0\,
      D => \zq_cntrl.zq_timer.zq_timer_r_reg[11]_1\(0),
      Q => \zq_cntrl.zq_timer.zq_timer_r_reg\(8),
      R => \zq_cntrl.zq_timer.zq_timer_r0\
    );
\zq_cntrl.zq_timer.zq_timer_r_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => \last_master_r_reg[2]_0\,
      CE => \zq_cntrl.zq_timer.zq_timer_r[0]_i_2_n_0\,
      D => \zq_cntrl.zq_timer.zq_timer_r_reg[11]_1\(1),
      Q => \zq_cntrl.zq_timer.zq_timer_r_reg\(9),
      R => \zq_cntrl.zq_timer.zq_timer_r0\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mig_mig_7series_v4_2_ui_top is
  port (
    app_rdy_r_reg : out STD_LOGIC;
    ram_init_done_r : out STD_LOGIC;
    app_wdf_rdy : out STD_LOGIC;
    \app_addr_r1_reg[23]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    D : out STD_LOGIC_VECTOR ( 13 downto 0 );
    \app_addr_r1_reg[23]_0\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    \app_addr_r1_reg[23]_1\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    \app_addr_r1_reg[23]_2\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    S : out STD_LOGIC_VECTOR ( 2 downto 0 );
    \req_row_r_lcl_reg[10]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    \req_bank_r_lcl_reg[0]\ : out STD_LOGIC;
    \app_addr_r1_reg[26]\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
    \req_bank_r_lcl_reg[0]_0\ : out STD_LOGIC;
    \req_bank_r_lcl_reg[2]\ : out STD_LOGIC;
    \req_bank_r_lcl_reg[2]_0\ : out STD_LOGIC;
    reset_reg : out STD_LOGIC_VECTOR ( 3 downto 0 );
    use_addr : out STD_LOGIC;
    cmd : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \app_addr_r1_reg[9]\ : out STD_LOGIC_VECTOR ( 9 downto 0 );
    Q : out STD_LOGIC_VECTOR ( 575 downto 0 );
    \wr_req_counter.wr_req_cnt_r_reg[0]\ : in STD_LOGIC;
    \pointer_ram.pointer_we\ : in STD_LOGIC;
    wr_data_addr : in STD_LOGIC_VECTOR ( 3 downto 0 );
    E : in STD_LOGIC_VECTOR ( 0 to 0 );
    row_hit_r_reg : in STD_LOGIC_VECTOR ( 19 downto 0 );
    req_bank_r : in STD_LOGIC_VECTOR ( 11 downto 0 );
    app_en : in STD_LOGIC;
    \wr_req_counter.wr_req_cnt_r_reg[0]_0\ : in STD_LOGIC;
    accept_ns : in STD_LOGIC;
    app_wdf_wren : in STD_LOGIC;
    app_wdf_end : in STD_LOGIC;
    app_wdf_mask : in STD_LOGIC_VECTOR ( 63 downto 0 );
    app_wdf_data : in STD_LOGIC_VECTOR ( 511 downto 0 );
    app_addr : in STD_LOGIC_VECTOR ( 26 downto 0 );
    app_cmd : in STD_LOGIC_VECTOR ( 1 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of mig_mig_7series_v4_2_ui_top : entity is "mig_7series_v4_2_ui_top";
end mig_mig_7series_v4_2_ui_top;

architecture STRUCTURE of mig_mig_7series_v4_2_ui_top is
  signal app_cmd_r2 : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal app_rdy_ns : STD_LOGIC;
  signal p_0_in : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \pointer_ram.pointer_wr_addr\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \pointer_ram.pointer_wr_data\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \^ram_init_done_r\ : STD_LOGIC;
  signal \read_data_indx.rd_data_indx_r_reg\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \strict_mode.rd_data_buf_addr_r_lcl\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal ui_cmd0_n_30 : STD_LOGIC;
  signal ui_cmd0_n_33 : STD_LOGIC;
  signal ui_cmd0_n_34 : STD_LOGIC;
  signal ui_cmd0_n_41 : STD_LOGIC;
  signal ui_cmd0_n_42 : STD_LOGIC;
  signal ui_cmd0_n_43 : STD_LOGIC;
  signal \^use_addr\ : STD_LOGIC;
  signal wr_accepted : STD_LOGIC;
  signal wr_data_buf_addr : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \wr_req_counter.wr_req_cnt_r\ : STD_LOGIC_VECTOR ( 1 downto 0 );
begin
  ram_init_done_r <= \^ram_init_done_r\;
  use_addr <= \^use_addr\;
ui_cmd0: entity work.mig_mig_7series_v4_2_ui_cmd
     port map (
      D(12) => D(13),
      D(11 downto 0) => D(11 downto 0),
      E(0) => app_rdy_r_reg,
      S(2 downto 0) => S(2 downto 0),
      app_addr(26 downto 0) => app_addr(26 downto 0),
      \app_addr_r1_reg[0]_0\ => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      \app_addr_r1_reg[22]_0\ => D(12),
      \app_addr_r1_reg[23]_0\(0) => \app_addr_r1_reg[23]\(0),
      \app_addr_r1_reg[23]_1\(0) => \app_addr_r1_reg[23]_0\(0),
      \app_addr_r1_reg[23]_2\(0) => \app_addr_r1_reg[23]_1\(0),
      \app_addr_r1_reg[23]_3\(0) => \app_addr_r1_reg[23]_2\(0),
      \app_addr_r1_reg[24]_0\ => \app_addr_r1_reg[26]\(0),
      \app_addr_r1_reg[25]_0\ => \app_addr_r1_reg[26]\(1),
      \app_addr_r1_reg[26]_0\ => \app_addr_r1_reg[26]\(2),
      \app_addr_r1_reg[9]_0\(9 downto 0) => \app_addr_r1_reg[9]\(9 downto 0),
      app_cmd(1 downto 0) => app_cmd(1 downto 0),
      app_cmd_r2(1 downto 0) => app_cmd_r2(1 downto 0),
      \app_cmd_r2_reg[0]_0\ => \wr_req_counter.wr_req_cnt_r_reg[0]\,
      app_en => app_en,
      app_en_r2_reg_0 => ui_cmd0_n_41,
      app_rdy_ns => app_rdy_ns,
      cmd(1 downto 0) => cmd(1 downto 0),
      p_0_in(0) => p_0_in(0),
      \read_data_indx.rd_data_upd_indx_r_reg\ => ui_cmd0_n_34,
      req_bank_r(11 downto 0) => req_bank_r(11 downto 0),
      \req_bank_r_lcl_reg[0]\ => \req_bank_r_lcl_reg[0]\,
      \req_bank_r_lcl_reg[0]_0\ => \req_bank_r_lcl_reg[0]_0\,
      \req_bank_r_lcl_reg[2]\ => \req_bank_r_lcl_reg[2]\,
      \req_bank_r_lcl_reg[2]_0\ => \req_bank_r_lcl_reg[2]_0\,
      \req_row_r_lcl_reg[10]\(0) => \req_row_r_lcl_reg[10]\(0),
      reset_reg(3 downto 0) => reset_reg(3 downto 0),
      row_hit_r_reg(19 downto 0) => row_hit_r_reg(19 downto 0),
      \strict_mode.rd_data_buf_addr_r_lcl\(3 downto 0) => \strict_mode.rd_data_buf_addr_r_lcl\(3 downto 0),
      \strict_mode.rd_data_buf_addr_r_lcl_reg[0]\ => ui_cmd0_n_42,
      \strict_mode.rd_data_buf_addr_r_lcl_reg[1]\ => ui_cmd0_n_43,
      use_addr => \^use_addr\,
      wr_accepted => wr_accepted,
      wr_data_buf_addr(3 downto 0) => wr_data_buf_addr(3 downto 0),
      \wr_req_counter.wr_req_cnt_r\(1 downto 0) => \wr_req_counter.wr_req_cnt_r\(1 downto 0),
      \wr_req_counter.wr_req_cnt_r_reg[0]\ => ui_cmd0_n_33,
      \wr_req_counter.wr_req_cnt_r_reg[1]\ => ui_cmd0_n_30
    );
ui_rd_data0: entity work.mig_mig_7series_v4_2_ui_rd_data
     port map (
      ADDRD(3 downto 0) => \pointer_ram.pointer_wr_addr\(3 downto 0),
      Q(3 downto 0) => \read_data_indx.rd_data_indx_r_reg\(3 downto 0),
      app_cmd_r2(1 downto 0) => app_cmd_r2(1 downto 0),
      \pointer_ram.pointer_wr_data\(3 downto 0) => \pointer_ram.pointer_wr_data\(3 downto 0),
      \rd_buf_indx.ram_init_done_r_lcl_reg_0\ => \^ram_init_done_r\,
      \strict_mode.rd_data_buf_addr_r_lcl\(3 downto 0) => \strict_mode.rd_data_buf_addr_r_lcl\(3 downto 0),
      \strict_mode.rd_data_buf_addr_r_lcl_reg[0]_0\ => \wr_req_counter.wr_req_cnt_r_reg[0]\,
      \strict_mode.rd_data_buf_addr_r_lcl_reg[0]_1\ => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      \strict_mode.rd_data_buf_addr_r_lcl_reg[0]_2\ => ui_cmd0_n_41,
      \strict_mode.rd_data_buf_addr_r_lcl_reg[1]_0\ => ui_cmd0_n_42,
      \strict_mode.rd_data_buf_addr_r_lcl_reg[3]_0\ => ui_cmd0_n_43,
      use_addr => \^use_addr\,
      wr_data_addr(3 downto 0) => wr_data_addr(3 downto 0)
    );
ui_wr_data0: entity work.mig_mig_7series_v4_2_ui_wr_data
     port map (
      ADDRD(3 downto 0) => \pointer_ram.pointer_wr_addr\(3 downto 0),
      E(0) => E(0),
      Q(3 downto 0) => \read_data_indx.rd_data_indx_r_reg\(3 downto 0),
      accept_ns => accept_ns,
      app_rdy_ns => app_rdy_ns,
      app_rdy_r_reg => ui_cmd0_n_30,
      app_wdf_data(511 downto 0) => app_wdf_data(511 downto 0),
      app_wdf_end => app_wdf_end,
      app_wdf_mask(63 downto 0) => app_wdf_mask(63 downto 0),
      app_wdf_rdy => app_wdf_rdy,
      app_wdf_wren => app_wdf_wren,
      p_0_in(0) => p_0_in(0),
      \pointer_ram.pointer_we\ => \pointer_ram.pointer_we\,
      \pointer_ram.pointer_wr_data\(3 downto 0) => \pointer_ram.pointer_wr_data\(3 downto 0),
      ram_init_done_r => \^ram_init_done_r\,
      wr_accepted => wr_accepted,
      wr_data_addr(3 downto 0) => wr_data_addr(3 downto 0),
      wr_data_buf_addr(3 downto 0) => wr_data_buf_addr(3 downto 0),
      \wr_req_counter.wr_req_cnt_r_reg[0]_0\ => \wr_req_counter.wr_req_cnt_r_reg[0]\,
      \wr_req_counter.wr_req_cnt_r_reg[0]_1\ => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      \wr_req_counter.wr_req_cnt_r_reg[0]_2\ => ui_cmd0_n_33,
      \wr_req_counter.wr_req_cnt_r_reg[1]_0\(1 downto 0) => \wr_req_counter.wr_req_cnt_r\(1 downto 0),
      \wr_req_counter.wr_req_cnt_r_reg[4]_0\ => ui_cmd0_n_34,
      \write_buffer.wr_buf_out_data_reg[575]_0\(575 downto 0) => Q(575 downto 0)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mig_mig_7series_v4_2_arb_mux is
  port (
    granted_row_r_reg : out STD_LOGIC;
    granted_col_r_reg : out STD_LOGIC;
    insert_maint_r1_lcl_reg : out STD_LOGIC;
    \pre_4_1_1T_arb.granted_pre_r_reg\ : out STD_LOGIC;
    DIC : out STD_LOGIC_VECTOR ( 0 to 0 );
    col_rd_wr : out STD_LOGIC;
    cke_r : out STD_LOGIC;
    rnk_config_valid_r_lcl_reg : out STD_LOGIC;
    \rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][5]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
    \rank_final_loop[0].bank_final_loop[1].final_data_offset_mc_reg[0][11]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
    \rank_final_loop[0].bank_final_loop[2].final_data_offset_mc_reg[0][17]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
    granted_col_r_reg_0 : out STD_LOGIC;
    \grant_r_reg[2]\ : out STD_LOGIC;
    \periodic_rd_generation.read_this_rank_r_reg\ : out STD_LOGIC;
    Q : out STD_LOGIC_VECTOR ( 3 downto 0 );
    \periodic_rd_generation.read_this_rank\ : out STD_LOGIC;
    mc_odt_ns : out STD_LOGIC_VECTOR ( 0 to 0 );
    D : out STD_LOGIC_VECTOR ( 0 to 0 );
    granted_col_r_reg_1 : out STD_LOGIC_VECTOR ( 0 to 0 );
    granted_col_r_reg_2 : out STD_LOGIC_VECTOR ( 0 to 0 );
    E : out STD_LOGIC_VECTOR ( 0 to 0 );
    \rtw_timer.rtw_cnt_r_reg[1]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \grant_r_reg[0]\ : out STD_LOGIC;
    \wr_this_rank_r_reg[0]\ : out STD_LOGIC;
    \wr_this_rank_r_reg[0]_0\ : out STD_LOGIC;
    \grant_r_reg[3]\ : out STD_LOGIC;
    mc_we_n_ns : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \grant_r_reg[3]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
    mc_cas_n_ns : out STD_LOGIC_VECTOR ( 2 downto 0 );
    mc_ras_n_ns : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \pre_4_1_1T_arb.granted_pre_r_reg_0\ : out STD_LOGIC_VECTOR ( 8 downto 0 );
    \pre_4_1_1T_arb.granted_pre_r_reg_1\ : out STD_LOGIC_VECTOR ( 38 downto 0 );
    mc_cs_n_ns : out STD_LOGIC_VECTOR ( 0 to 0 );
    \grant_r_reg[1]\ : out STD_LOGIC;
    \rnk_config_strobe_r_reg[0]\ : out STD_LOGIC;
    rnk_config_valid_r_lcl_reg_0 : out STD_LOGIC;
    rnk_config_valid_r_lcl_reg_1 : out STD_LOGIC;
    rnk_config_valid_r_lcl_reg_2 : out STD_LOGIC;
    rnk_config_valid_r_lcl_reg_3 : out STD_LOGIC;
    override_demand_ns : out STD_LOGIC;
    \grant_r_reg[0]_0\ : out STD_LOGIC;
    \grant_r_reg[3]_1\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
    \last_master_r_reg[3]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    col_wr_data_buf_addr : out STD_LOGIC_VECTOR ( 3 downto 0 );
    act_this_rank : out STD_LOGIC;
    \grant_r_reg[0]_1\ : out STD_LOGIC;
    req_bank_rdy_r_reg : out STD_LOGIC;
    \rtw_timer.rtw_cnt_r_reg[1]_0\ : out STD_LOGIC;
    \wtr_timer.wtr_cnt_r_reg[1]\ : out STD_LOGIC;
    \grant_r_reg[0]_2\ : out STD_LOGIC;
    cke_r_reg : in STD_LOGIC;
    rnk_config_strobe_ns : in STD_LOGIC;
    granted_col_ns : in STD_LOGIC;
    insert_maint_r1_lcl_reg_0 : in STD_LOGIC;
    \pre_4_1_1T_arb.granted_pre_ns\ : in STD_LOGIC;
    cke_r_reg_0 : in STD_LOGIC;
    mc_cke_ns : in STD_LOGIC_VECTOR ( 0 to 0 );
    SR : in STD_LOGIC_VECTOR ( 0 to 0 );
    rnk_config_valid_r_lcl_reg_4 : in STD_LOGIC;
    \cmd_pipe_plus.mc_data_offset_reg[5]\ : in STD_LOGIC_VECTOR ( 5 downto 0 );
    \cmd_pipe_plus.mc_data_offset_1_reg[5]\ : in STD_LOGIC_VECTOR ( 5 downto 0 );
    \cmd_pipe_plus.mc_data_offset_2_reg[5]\ : in STD_LOGIC_VECTOR ( 5 downto 0 );
    \grant_r_reg[0]_3\ : in STD_LOGIC;
    \grant_r_reg[0]_4\ : in STD_LOGIC;
    \grant_r_reg[2]_0\ : in STD_LOGIC;
    \grant_r_reg[0]_5\ : in STD_LOGIC;
    \grant_r_reg[3]_2\ : in STD_LOGIC;
    granted_row_r_reg_0 : in STD_LOGIC;
    \grant_r_reg[3]_3\ : in STD_LOGIC;
    \periodic_rd_generation.read_this_rank_r\ : in STD_LOGIC;
    rd_this_rank_r : in STD_LOGIC_VECTOR ( 3 downto 0 );
    req_periodic_rd_r : in STD_LOGIC_VECTOR ( 3 downto 0 );
    \rtw_timer.rtw_cnt_r_reg[0]\ : in STD_LOGIC;
    \cmd_pipe_plus.mc_odt_reg[0]\ : in STD_LOGIC;
    \rtw_timer.rtw_cnt_r_reg[1]_1\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \cmd_pipe_plus.mc_data_offset_2_reg[0]\ : in STD_LOGIC;
    \cmd_pipe_plus.mc_data_offset_2_reg[0]_0\ : in STD_LOGIC;
    \i___22_i_1\ : in STD_LOGIC;
    rd_wr_r : in STD_LOGIC_VECTOR ( 0 to 0 );
    wr_this_rank_r : in STD_LOGIC_VECTOR ( 3 downto 0 );
    \grant_r[3]_i_8\ : in STD_LOGIC;
    \grant_r[3]_i_8_0\ : in STD_LOGIC;
    \cmd_pipe_plus.mc_we_n_reg[0]\ : in STD_LOGIC;
    \cmd_pipe_plus.mc_we_n_reg[0]_0\ : in STD_LOGIC;
    \cmd_pipe_plus.mc_address_reg[0]\ : in STD_LOGIC;
    \cmd_pipe_plus.mc_cas_n_reg[0]\ : in STD_LOGIC;
    maint_zq_r : in STD_LOGIC;
    maint_srx_r : in STD_LOGIC;
    \cmd_pipe_plus.mc_bank_reg[2]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
    \cmd_pipe_plus.mc_address_reg[3]\ : in STD_LOGIC;
    \cmd_pipe_plus.mc_bank_reg[2]_0\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
    \cmd_pipe_plus.mc_address_reg[0]_0\ : in STD_LOGIC;
    \cmd_pipe_plus.mc_bank_reg[2]_1\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
    \cmd_pipe_plus.mc_bank_reg[8]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
    \cmd_pipe_plus.mc_address_reg[41]\ : in STD_LOGIC_VECTOR ( 19 downto 0 );
    req_row_r : in STD_LOGIC_VECTOR ( 34 downto 0 );
    \cmd_pipe_plus.mc_address_reg[10]\ : in STD_LOGIC;
    \cmd_pipe_plus.mc_address_reg[10]_0\ : in STD_LOGIC;
    \cmd_pipe_plus.mc_we_n_reg[0]_1\ : in STD_LOGIC;
    \cmd_pipe_plus.mc_we_n_reg[2]\ : in STD_LOGIC;
    \grant_r_reg[0]_6\ : in STD_LOGIC;
    \grant_r_reg[0]_7\ : in STD_LOGIC;
    \grant_r_reg[0]_8\ : in STD_LOGIC;
    \grant_r_reg[1]_0\ : in STD_LOGIC;
    \grant_r_reg[3]_4\ : in STD_LOGIC;
    \grant_r_reg[3]_5\ : in STD_LOGIC;
    ofs_rdy_r : in STD_LOGIC;
    ofs_rdy_r_0 : in STD_LOGIC;
    ofs_rdy_r_1 : in STD_LOGIC;
    ofs_rdy_r_2 : in STD_LOGIC;
    inhbt_act_faw_r : in STD_LOGIC;
    req_data_buf_addr_r : in STD_LOGIC_VECTOR ( 15 downto 0 );
    \delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
    act_this_rank_r : in STD_LOGIC_VECTOR ( 3 downto 0 );
    \cmd_pipe_plus.mc_address_reg[23]\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
    \cmd_pipe_plus.mc_address_reg[23]_0\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
    \cmd_pipe_plus.mc_address_reg[23]_1\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
    \cmd_pipe_plus.mc_address_reg[23]_2\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
    \cmd_pipe_plus.mc_address_reg[24]\ : in STD_LOGIC;
    \cmd_pipe_plus.mc_address_reg[24]_0\ : in STD_LOGIC;
    \cmd_pipe_plus.mc_address_reg[24]_1\ : in STD_LOGIC;
    \cmd_pipe_plus.mc_address_reg[24]_2\ : in STD_LOGIC;
    \cmd_pipe_plus.mc_address_reg[38]\ : in STD_LOGIC;
    req_bank_rdy_r : in STD_LOGIC;
    \grant_r[2]_i_3\ : in STD_LOGIC;
    \grant_r[2]_i_3_0\ : in STD_LOGIC_VECTOR ( 0 to 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of mig_mig_7series_v4_2_arb_mux : entity is "mig_7series_v4_2_arb_mux";
end mig_mig_7series_v4_2_arb_mux;

architecture STRUCTURE of mig_mig_7series_v4_2_arb_mux is
  signal \^dic\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \col_mux.col_periodic_rd_r\ : STD_LOGIC;
  signal \^col_rd_wr\ : STD_LOGIC;
  signal col_rd_wr_r : STD_LOGIC;
  signal mc_data_offset1 : STD_LOGIC_VECTOR ( 3 to 3 );
  signal mc_data_offset_11 : STD_LOGIC_VECTOR ( 3 to 3 );
  signal mc_data_offset_21 : STD_LOGIC_VECTOR ( 3 to 3 );
begin
  DIC(0) <= \^dic\(0);
  col_rd_wr <= \^col_rd_wr\;
arb_row_col0: entity work.mig_mig_7series_v4_2_arb_row_col
     port map (
      D(0) => D(0),
      DIC(0) => \^dic\(0),
      E(0) => E(0),
      O(0) => mc_data_offset_21(3),
      Q(3 downto 0) => Q(3 downto 0),
      SR(0) => SR(0),
      act_this_rank => act_this_rank,
      act_this_rank_r(3 downto 0) => act_this_rank_r(3 downto 0),
      \cmd_pipe_plus.mc_address_reg[0]\ => \cmd_pipe_plus.mc_address_reg[0]\,
      \cmd_pipe_plus.mc_address_reg[0]_0\ => \cmd_pipe_plus.mc_address_reg[0]_0\,
      \cmd_pipe_plus.mc_address_reg[10]\ => \cmd_pipe_plus.mc_address_reg[10]\,
      \cmd_pipe_plus.mc_address_reg[10]_0\ => \cmd_pipe_plus.mc_address_reg[10]_0\,
      \cmd_pipe_plus.mc_address_reg[23]\(9 downto 0) => \cmd_pipe_plus.mc_address_reg[23]\(9 downto 0),
      \cmd_pipe_plus.mc_address_reg[23]_0\(9 downto 0) => \cmd_pipe_plus.mc_address_reg[23]_0\(9 downto 0),
      \cmd_pipe_plus.mc_address_reg[23]_1\(9 downto 0) => \cmd_pipe_plus.mc_address_reg[23]_1\(9 downto 0),
      \cmd_pipe_plus.mc_address_reg[23]_2\(9 downto 0) => \cmd_pipe_plus.mc_address_reg[23]_2\(9 downto 0),
      \cmd_pipe_plus.mc_address_reg[24]\ => \cmd_pipe_plus.mc_address_reg[24]\,
      \cmd_pipe_plus.mc_address_reg[24]_0\ => \cmd_pipe_plus.mc_address_reg[24]_0\,
      \cmd_pipe_plus.mc_address_reg[24]_1\ => \cmd_pipe_plus.mc_address_reg[24]_1\,
      \cmd_pipe_plus.mc_address_reg[24]_2\ => \cmd_pipe_plus.mc_address_reg[24]_2\,
      \cmd_pipe_plus.mc_address_reg[38]\ => \cmd_pipe_plus.mc_address_reg[38]\,
      \cmd_pipe_plus.mc_address_reg[3]\ => \cmd_pipe_plus.mc_address_reg[3]\,
      \cmd_pipe_plus.mc_address_reg[41]\(19 downto 0) => \cmd_pipe_plus.mc_address_reg[41]\(19 downto 0),
      \cmd_pipe_plus.mc_bank_reg[2]\(2 downto 0) => \cmd_pipe_plus.mc_bank_reg[2]\(2 downto 0),
      \cmd_pipe_plus.mc_bank_reg[2]_0\(2 downto 0) => \cmd_pipe_plus.mc_bank_reg[2]_0\(2 downto 0),
      \cmd_pipe_plus.mc_bank_reg[2]_1\(2 downto 0) => \cmd_pipe_plus.mc_bank_reg[2]_1\(2 downto 0),
      \cmd_pipe_plus.mc_bank_reg[8]\(2 downto 0) => \cmd_pipe_plus.mc_bank_reg[8]\(2 downto 0),
      \cmd_pipe_plus.mc_cas_n_reg[0]\ => \cmd_pipe_plus.mc_cas_n_reg[0]\,
      \cmd_pipe_plus.mc_data_offset_1_reg[3]\(0) => mc_data_offset_11(3),
      \cmd_pipe_plus.mc_data_offset_2_reg[0]\ => \cmd_pipe_plus.mc_data_offset_2_reg[0]\,
      \cmd_pipe_plus.mc_data_offset_2_reg[0]_0\ => \cmd_pipe_plus.mc_data_offset_2_reg[0]_0\,
      \cmd_pipe_plus.mc_data_offset_reg[3]\(0) => mc_data_offset1(3),
      \cmd_pipe_plus.mc_odt_reg[0]\ => \cmd_pipe_plus.mc_odt_reg[0]\,
      \cmd_pipe_plus.mc_we_n_reg[0]\ => \cmd_pipe_plus.mc_we_n_reg[0]\,
      \cmd_pipe_plus.mc_we_n_reg[0]_0\ => \cmd_pipe_plus.mc_we_n_reg[0]_0\,
      \cmd_pipe_plus.mc_we_n_reg[0]_1\ => \cmd_pipe_plus.mc_we_n_reg[0]_1\,
      \cmd_pipe_plus.mc_we_n_reg[2]\ => \cmd_pipe_plus.mc_we_n_reg[2]\,
      \col_mux.col_periodic_rd_r\ => \col_mux.col_periodic_rd_r\,
      col_rd_wr => \^col_rd_wr\,
      col_rd_wr_r => col_rd_wr_r,
      col_wr_data_buf_addr(3 downto 0) => col_wr_data_buf_addr(3 downto 0),
      \delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r_reg[3]\(3 downto 0) => \delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r_reg[3]\(3 downto 0),
      \grant_r[2]_i_3\ => \grant_r[2]_i_3\,
      \grant_r[2]_i_3_0\(0) => \grant_r[2]_i_3_0\(0),
      \grant_r[3]_i_8\ => \grant_r[3]_i_8\,
      \grant_r[3]_i_8_0\ => \grant_r[3]_i_8_0\,
      \grant_r_reg[0]\ => \grant_r_reg[0]\,
      \grant_r_reg[0]_0\ => \grant_r_reg[0]_0\,
      \grant_r_reg[0]_1\ => \grant_r_reg[0]_1\,
      \grant_r_reg[0]_2\ => \grant_r_reg[0]_2\,
      \grant_r_reg[0]_3\ => \grant_r_reg[0]_3\,
      \grant_r_reg[0]_4\ => \grant_r_reg[0]_4\,
      \grant_r_reg[0]_5\ => \grant_r_reg[0]_5\,
      \grant_r_reg[0]_6\ => \grant_r_reg[0]_6\,
      \grant_r_reg[0]_7\ => \grant_r_reg[0]_7\,
      \grant_r_reg[0]_8\ => \grant_r_reg[0]_8\,
      \grant_r_reg[1]\ => \grant_r_reg[1]\,
      \grant_r_reg[1]_0\ => \grant_r_reg[1]_0\,
      \grant_r_reg[2]\ => \grant_r_reg[2]\,
      \grant_r_reg[2]_0\ => \grant_r_reg[2]_0\,
      \grant_r_reg[3]\ => \grant_r_reg[3]\,
      \grant_r_reg[3]_0\(3 downto 0) => \grant_r_reg[3]_0\(3 downto 0),
      \grant_r_reg[3]_1\(3 downto 0) => \grant_r_reg[3]_1\(3 downto 0),
      \grant_r_reg[3]_2\ => \grant_r_reg[3]_2\,
      \grant_r_reg[3]_3\ => \grant_r_reg[3]_3\,
      \grant_r_reg[3]_4\ => \grant_r_reg[3]_4\,
      \grant_r_reg[3]_5\ => \grant_r_reg[3]_5\,
      granted_col_ns => granted_col_ns,
      granted_col_r_reg_0 => granted_col_r_reg,
      granted_col_r_reg_1 => granted_col_r_reg_0,
      granted_col_r_reg_2(0) => granted_col_r_reg_1(0),
      granted_col_r_reg_3(0) => granted_col_r_reg_2(0),
      granted_row_r_reg_0 => granted_row_r_reg,
      granted_row_r_reg_1 => granted_row_r_reg_0,
      \i___22_i_1\ => \i___22_i_1\,
      inhbt_act_faw_r => inhbt_act_faw_r,
      insert_maint_r1_lcl_reg_0 => insert_maint_r1_lcl_reg,
      insert_maint_r1_lcl_reg_1 => insert_maint_r1_lcl_reg_0,
      \last_master_r_reg[3]\(0) => \last_master_r_reg[3]\(0),
      \last_master_r_reg[3]_0\ => cke_r_reg,
      maint_srx_r => maint_srx_r,
      maint_zq_r => maint_zq_r,
      mc_cas_n_ns(2 downto 0) => mc_cas_n_ns(2 downto 0),
      mc_cs_n_ns(0) => mc_cs_n_ns(0),
      mc_odt_ns(0) => mc_odt_ns(0),
      mc_ras_n_ns(1 downto 0) => mc_ras_n_ns(1 downto 0),
      mc_we_n_ns(1 downto 0) => mc_we_n_ns(1 downto 0),
      ofs_rdy_r => ofs_rdy_r,
      ofs_rdy_r_0 => ofs_rdy_r_0,
      ofs_rdy_r_1 => ofs_rdy_r_1,
      ofs_rdy_r_2 => ofs_rdy_r_2,
      override_demand_ns => override_demand_ns,
      \periodic_rd_generation.read_this_rank\ => \periodic_rd_generation.read_this_rank\,
      \periodic_rd_generation.read_this_rank_r\ => \periodic_rd_generation.read_this_rank_r\,
      \periodic_rd_generation.read_this_rank_r_reg\ => \periodic_rd_generation.read_this_rank_r_reg\,
      \pre_4_1_1T_arb.granted_pre_ns\ => \pre_4_1_1T_arb.granted_pre_ns\,
      \pre_4_1_1T_arb.granted_pre_r_reg_0\ => \pre_4_1_1T_arb.granted_pre_r_reg\,
      \pre_4_1_1T_arb.granted_pre_r_reg_1\(8 downto 0) => \pre_4_1_1T_arb.granted_pre_r_reg_0\(8 downto 0),
      \pre_4_1_1T_arb.granted_pre_r_reg_2\(38 downto 0) => \pre_4_1_1T_arb.granted_pre_r_reg_1\(38 downto 0),
      rd_this_rank_r(3 downto 0) => rd_this_rank_r(3 downto 0),
      rd_wr_r(0) => rd_wr_r(0),
      req_bank_rdy_r => req_bank_rdy_r,
      req_bank_rdy_r_reg => req_bank_rdy_r_reg,
      req_data_buf_addr_r(15 downto 0) => req_data_buf_addr_r(15 downto 0),
      req_periodic_rd_r(3 downto 0) => req_periodic_rd_r(3 downto 0),
      req_row_r(34 downto 0) => req_row_r(34 downto 0),
      rnk_config_strobe_ns => rnk_config_strobe_ns,
      \rnk_config_strobe_r_reg[0]_0\ => \rnk_config_strobe_r_reg[0]\,
      rnk_config_valid_r_lcl_reg_0 => rnk_config_valid_r_lcl_reg,
      rnk_config_valid_r_lcl_reg_1 => rnk_config_valid_r_lcl_reg_0,
      rnk_config_valid_r_lcl_reg_2 => rnk_config_valid_r_lcl_reg_1,
      rnk_config_valid_r_lcl_reg_3 => rnk_config_valid_r_lcl_reg_2,
      rnk_config_valid_r_lcl_reg_4 => rnk_config_valid_r_lcl_reg_3,
      rnk_config_valid_r_lcl_reg_5 => rnk_config_valid_r_lcl_reg_4,
      \rtw_timer.rtw_cnt_r_reg[0]\ => \rtw_timer.rtw_cnt_r_reg[0]\,
      \rtw_timer.rtw_cnt_r_reg[1]\(1 downto 0) => \rtw_timer.rtw_cnt_r_reg[1]\(1 downto 0),
      \rtw_timer.rtw_cnt_r_reg[1]_0\ => \rtw_timer.rtw_cnt_r_reg[1]_0\,
      \rtw_timer.rtw_cnt_r_reg[1]_1\(1 downto 0) => \rtw_timer.rtw_cnt_r_reg[1]_1\(1 downto 0),
      wr_this_rank_r(3 downto 0) => wr_this_rank_r(3 downto 0),
      \wr_this_rank_r_reg[0]\ => \wr_this_rank_r_reg[0]\,
      \wr_this_rank_r_reg[0]_0\ => \wr_this_rank_r_reg[0]_0\,
      \wtr_timer.wtr_cnt_r_reg[1]\ => \wtr_timer.wtr_cnt_r_reg[1]\
    );
arb_select0: entity work.mig_mig_7series_v4_2_arb_select
     port map (
      DIC(0) => \^dic\(0),
      O(0) => mc_data_offset_21(3),
      cke_r => cke_r,
      cke_r_reg_0 => cke_r_reg,
      cke_r_reg_1 => cke_r_reg_0,
      \cmd_pipe_plus.mc_data_offset_1_reg[5]\(5 downto 0) => \cmd_pipe_plus.mc_data_offset_1_reg[5]\(5 downto 0),
      \cmd_pipe_plus.mc_data_offset_2_reg[5]\(5 downto 0) => \cmd_pipe_plus.mc_data_offset_2_reg[5]\(5 downto 0),
      \cmd_pipe_plus.mc_data_offset_reg[5]\(5 downto 0) => \cmd_pipe_plus.mc_data_offset_reg[5]\(5 downto 0),
      \col_mux.col_periodic_rd_r\ => \col_mux.col_periodic_rd_r\,
      col_rd_wr => \^col_rd_wr\,
      col_rd_wr_r => col_rd_wr_r,
      mc_cke_ns(0) => mc_cke_ns(0),
      \rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][0]\(0) => mc_data_offset1(3),
      \rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][5]\(3 downto 0) => \rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][5]\(3 downto 0),
      \rank_final_loop[0].bank_final_loop[1].final_data_offset_mc_reg[0][11]\(3 downto 0) => \rank_final_loop[0].bank_final_loop[1].final_data_offset_mc_reg[0][11]\(3 downto 0),
      \rank_final_loop[0].bank_final_loop[1].final_data_offset_mc_reg[0][6]\(0) => mc_data_offset_11(3),
      \rank_final_loop[0].bank_final_loop[2].final_data_offset_mc_reg[0][17]\(3 downto 0) => \rank_final_loop[0].bank_final_loop[2].final_data_offset_mc_reg[0][17]\(3 downto 0)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mig_mig_7series_v4_2_ddr_phy_4lanes is
  port (
    out_dqs_4 : out STD_LOGIC;
    ts_dqs_4 : out STD_LOGIC;
    A_rst_primitives_reg_0 : out STD_LOGIC;
    mem_dq_out : out STD_LOGIC_VECTOR ( 35 downto 0 );
    mem_dq_ts : out STD_LOGIC_VECTOR ( 35 downto 0 );
    in0 : out STD_LOGIC_VECTOR ( 3 downto 0 );
    idelay_ld_rst : out STD_LOGIC;
    out_dqs_5 : out STD_LOGIC;
    ts_dqs_5 : out STD_LOGIC;
    A_rst_primitives_reg_1 : out STD_LOGIC;
    if_empty_r : out STD_LOGIC_VECTOR ( 0 to 0 );
    \my_empty_reg[4]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    idelay_ld_rst_0 : out STD_LOGIC;
    out_dqs_6 : out STD_LOGIC;
    ts_dqs_6 : out STD_LOGIC;
    A_rst_primitives_reg_2 : out STD_LOGIC;
    if_empty_r_0 : out STD_LOGIC_VECTOR ( 0 to 0 );
    \my_empty_reg[4]_0\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    idelay_ld_rst_1 : out STD_LOGIC;
    out_dqs_7 : out STD_LOGIC;
    ts_dqs_7 : out STD_LOGIC;
    A_rst_primitives_reg_3 : out STD_LOGIC;
    idelay_ld_rst_2 : out STD_LOGIC;
    \_phy_ctl_full_p__0\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    phy_ctl_wr_i2_reg : out STD_LOGIC;
    \ref_dll_lock_w__0\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    rst_primitives : out STD_LOGIC;
    mcGo_w : out STD_LOGIC_VECTOR ( 0 to 0 );
    rst_out_reg_0 : out STD_LOGIC;
    rclk_delay_11 : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]\ : out STD_LOGIC;
    if_empty : out STD_LOGIC;
    \my_empty_reg[1]\ : out STD_LOGIC;
    phy_mc_data_full : out STD_LOGIC;
    \my_empty_reg[1]_0\ : out STD_LOGIC;
    \my_empty_reg[1]_1\ : out STD_LOGIC;
    \my_empty_reg[1]_2\ : out STD_LOGIC;
    A_rst_primitives_reg_4 : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_1\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_0\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_1\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_2\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_3\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_4\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_5\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_6\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_7\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_8\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_9\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_10\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_11\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_12\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_13\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_14\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_15\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_16\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_17\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_18\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_19\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_20\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_21\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_22\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_23\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_24\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_25\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_26\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_27\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_28\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_29\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_30\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_31\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_32\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_33\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_34\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_35\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_36\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_37\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_38\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_39\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_40\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_41\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_42\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_43\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_44\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_45\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_46\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_47\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_48\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_49\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_50\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_51\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_52\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_53\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_54\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_55\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_56\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_57\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_58\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_59\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_60\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_61\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_62\ : out STD_LOGIC;
    phy_rddata_en : out STD_LOGIC;
    \rd_mux_sel_r_reg[1]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_2\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[1]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_2\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[1]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_2\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[1]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_2\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[1]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_2\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[1]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_2\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[1]_5\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_1\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[1]_6\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_2\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[1]_7\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_2\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[1]_8\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_2\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[1]_9\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_2\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[1]_10\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_2\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[1]_11\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_2\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[1]_12\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_2\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[1]_13\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_1\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[1]_14\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_2\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[1]_15\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_2\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[1]_16\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_2\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[1]_17\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_2\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[1]_18\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_2\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[1]_19\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_2\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[1]_20\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_2\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[1]_21\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_1\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[1]_22\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_2\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[1]_23\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_2\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[1]_24\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_2\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[1]_25\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_2\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[1]_26\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_2\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[1]_27\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_2\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[1]_28\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_2\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[1]_29\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_1\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[1]_30\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_2\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[1]_31\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_2\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[1]_32\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_2\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[1]_33\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_2\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[1]_34\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_2\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[1]_35\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_2\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[1]_36\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_2\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[1]_37\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_1\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[1]_38\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_2\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[1]_39\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_2\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[1]_40\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_2\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[1]_41\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_2\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[1]_42\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_2\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[1]_43\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_2\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[1]_44\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_2\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[1]_45\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_1\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[1]_46\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_2\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[1]_47\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_2\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[1]_48\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_2\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[1]_49\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_2\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[1]_50\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_2\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[1]_51\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_2\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[1]_52\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_2\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[1]_53\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_1\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[1]_54\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_2\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[1]_55\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_2\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[1]_56\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_2\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[1]_57\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_2\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[1]_58\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_2\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[1]_59\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_2\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[1]_60\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_2\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[1]_61\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_1\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[1]_62\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_2\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_0\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_1\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_2\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_3\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_4\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_5\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_6\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_7\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_8\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_9\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_10\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_11\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_12\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_13\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_14\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_15\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_16\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_17\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_18\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_19\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_20\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_21\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_22\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_23\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_24\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_25\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_26\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_27\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_28\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_29\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_30\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_31\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_32\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_33\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_34\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_35\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_36\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_37\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_38\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_39\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_40\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_41\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_42\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_43\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_44\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_45\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_46\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_47\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_48\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_49\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_50\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_51\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_52\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_53\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_54\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_55\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_56\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_57\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_58\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_59\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_60\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_61\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_62\ : out STD_LOGIC;
    \rd_ptr_reg[3]\ : out STD_LOGIC_VECTOR ( 63 downto 0 );
    \rd_ptr_reg[3]_0\ : out STD_LOGIC_VECTOR ( 63 downto 0 );
    \rd_ptr_reg[3]_1\ : out STD_LOGIC_VECTOR ( 63 downto 0 );
    \rd_ptr_reg[3]_2\ : out STD_LOGIC_VECTOR ( 63 downto 0 );
    \po_counter_read_val_reg[8]_0\ : out STD_LOGIC_VECTOR ( 8 downto 0 );
    \pi_counter_read_val_reg[5]_0\ : out STD_LOGIC_VECTOR ( 5 downto 0 );
    \entry_cnt_reg[4]\ : in STD_LOGIC;
    \input_[9].iserdes_dq_.iserdesdq\ : in STD_LOGIC;
    mem_dq_in : in STD_LOGIC_VECTOR ( 31 downto 0 );
    idelay_inc : in STD_LOGIC;
    LD0 : in STD_LOGIC;
    CLKB0 : in STD_LOGIC;
    \pi_dqs_found_lanes_r1_reg[0]\ : in STD_LOGIC;
    \pi_dqs_found_lanes_r1_reg[0]_0\ : in STD_LOGIC;
    \pi_dqs_found_lanes_r1_reg[0]_1\ : in STD_LOGIC;
    \pi_dqs_found_lanes_r1_reg[0]_2\ : in STD_LOGIC;
    freq_refclk : in STD_LOGIC;
    mem_refclk : in STD_LOGIC;
    mem_dqs_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
    ififo_rst_reg : in STD_LOGIC;
    sync_pulse : in STD_LOGIC;
    COUNTERLOADVAL : in STD_LOGIC_VECTOR ( 5 downto 0 );
    \po_counter_read_val_reg[8]_1\ : in STD_LOGIC;
    \po_counter_read_val_reg[8]_2\ : in STD_LOGIC;
    \po_counter_read_val_reg[8]_3\ : in STD_LOGIC;
    \my_empty_reg[7]\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \my_empty_reg[7]_0\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \my_empty_reg[7]_1\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \my_empty_reg[7]_2\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \my_empty_reg[7]_3\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \my_empty_reg[7]_4\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \my_empty_reg[7]_5\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \my_empty_reg[7]_6\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    phy_if_reset : in STD_LOGIC;
    \input_[9].iserdes_dq_.iserdesdq_0\ : in STD_LOGIC;
    LD0_7 : in STD_LOGIC;
    CLKB0_7 : in STD_LOGIC;
    \pi_dqs_found_lanes_r1_reg[1]\ : in STD_LOGIC;
    \pi_dqs_found_lanes_r1_reg[1]_0\ : in STD_LOGIC;
    \pi_dqs_found_lanes_r1_reg[1]_1\ : in STD_LOGIC;
    \pi_dqs_found_lanes_r1_reg[1]_2\ : in STD_LOGIC;
    ififo_rst_reg_0 : in STD_LOGIC;
    \pi_dqs_found_lanes_r1_reg[1]_3\ : in STD_LOGIC_VECTOR ( 5 downto 0 );
    \po_counter_read_val_reg[8]_4\ : in STD_LOGIC;
    \po_counter_read_val_reg[8]_5\ : in STD_LOGIC;
    \po_counter_read_val_reg[8]_6\ : in STD_LOGIC;
    \my_empty_reg[7]_7\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \my_empty_reg[7]_8\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \my_empty_reg[7]_9\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \my_empty_reg[7]_10\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \my_empty_reg[7]_11\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \my_empty_reg[7]_12\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \my_empty_reg[7]_13\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \my_empty_reg[7]_14\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \input_[9].iserdes_dq_.iserdesdq_1\ : in STD_LOGIC;
    LD0_8 : in STD_LOGIC;
    CLKB0_8 : in STD_LOGIC;
    \pi_dqs_found_lanes_r1_reg[2]\ : in STD_LOGIC;
    \pi_dqs_found_lanes_r1_reg[2]_0\ : in STD_LOGIC;
    \pi_dqs_found_lanes_r1_reg[2]_1\ : in STD_LOGIC;
    \pi_dqs_found_lanes_r1_reg[2]_2\ : in STD_LOGIC;
    ififo_rst_reg_1 : in STD_LOGIC;
    \pi_dqs_found_lanes_r1_reg[2]_3\ : in STD_LOGIC_VECTOR ( 5 downto 0 );
    \po_counter_read_val_reg[8]_7\ : in STD_LOGIC;
    \po_counter_read_val_reg[8]_8\ : in STD_LOGIC;
    \po_counter_read_val_reg[8]_9\ : in STD_LOGIC;
    \my_empty_reg[7]_15\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \my_empty_reg[7]_16\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \my_empty_reg[7]_17\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \my_empty_reg[7]_18\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \my_empty_reg[7]_19\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \my_empty_reg[7]_20\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \my_empty_reg[7]_21\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \my_empty_reg[7]_22\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \input_[9].iserdes_dq_.iserdesdq_2\ : in STD_LOGIC;
    LD0_9 : in STD_LOGIC;
    CLKB0_9 : in STD_LOGIC;
    \pi_dqs_found_lanes_r1_reg[3]\ : in STD_LOGIC;
    \pi_dqs_found_lanes_r1_reg[3]_0\ : in STD_LOGIC;
    \pi_dqs_found_lanes_r1_reg[3]_1\ : in STD_LOGIC;
    \pi_dqs_found_lanes_r1_reg[3]_2\ : in STD_LOGIC;
    ififo_rst_reg_2 : in STD_LOGIC;
    \pi_dqs_found_lanes_r1_reg[3]_3\ : in STD_LOGIC_VECTOR ( 5 downto 0 );
    \po_counter_read_val_reg[8]_10\ : in STD_LOGIC;
    \po_counter_read_val_reg[8]_11\ : in STD_LOGIC;
    \po_counter_read_val_reg[8]_12\ : in STD_LOGIC;
    \my_empty_reg[7]_23\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \my_empty_reg[7]_24\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \my_empty_reg[7]_25\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \my_empty_reg[7]_26\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \my_empty_reg[7]_27\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \my_empty_reg[7]_28\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \my_empty_reg[7]_29\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \my_empty_reg[7]_30\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    phy_ctl_mstr_empty : in STD_LOGIC;
    phy_ctl_wr_i2 : in STD_LOGIC;
    pll_locked : in STD_LOGIC;
    phy_read_calib : in STD_LOGIC;
    phy_mc_ctl_full_r_reg : in STD_LOGIC;
    phy_write_calib : in STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 10 downto 0 );
    RST0 : in STD_LOGIC;
    rst_primitives_reg_0 : in STD_LOGIC;
    rst_out_reg_1 : in STD_LOGIC;
    SR : in STD_LOGIC_VECTOR ( 0 to 0 );
    \rclk_delay_reg[11]_0\ : in STD_LOGIC;
    phy_if_empty_r_reg : in STD_LOGIC;
    if_empty_v : in STD_LOGIC_VECTOR ( 0 to 0 );
    phy_data_wr_en : in STD_LOGIC;
    ofs_rdy_r_reg : in STD_LOGIC;
    ofs_rdy_r_reg_0 : in STD_LOGIC;
    pi_phase_locked_all_r1_reg : in STD_LOGIC;
    \gen_mux_rd[0].mux_rd_rise0_r_reg[0]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \gen_mux_rd[0].mux_rd_rise0_r_reg[0]_0\ : in STD_LOGIC;
    \gen_mux_rd[1].mux_rd_rise0_r_reg[1]\ : in STD_LOGIC;
    \gen_mux_rd[2].mux_rd_rise0_r_reg[2]\ : in STD_LOGIC;
    \gen_mux_rd[3].mux_rd_rise0_r_reg[3]\ : in STD_LOGIC;
    \gen_mux_rd[4].mux_rd_rise0_r_reg[4]\ : in STD_LOGIC;
    \gen_mux_rd[5].mux_rd_rise0_r_reg[5]\ : in STD_LOGIC;
    \gen_mux_rd[6].mux_rd_rise0_r_reg[6]\ : in STD_LOGIC;
    \gen_mux_rd[7].mux_rd_rise0_r_reg[7]\ : in STD_LOGIC;
    \gen_mux_rd[0].mux_rd_fall0_r_reg[0]\ : in STD_LOGIC;
    \gen_mux_rd[1].mux_rd_fall0_r_reg[1]\ : in STD_LOGIC;
    \gen_mux_rd[2].mux_rd_fall0_r_reg[2]\ : in STD_LOGIC;
    \gen_mux_rd[3].mux_rd_fall0_r_reg[3]\ : in STD_LOGIC;
    \gen_mux_rd[4].mux_rd_fall0_r_reg[4]\ : in STD_LOGIC;
    \gen_mux_rd[5].mux_rd_fall0_r_reg[5]\ : in STD_LOGIC;
    \gen_mux_rd[6].mux_rd_fall0_r_reg[6]\ : in STD_LOGIC;
    \gen_mux_rd[7].mux_rd_fall0_r_reg[7]\ : in STD_LOGIC;
    \gen_mux_rd[0].mux_rd_rise1_r_reg[0]\ : in STD_LOGIC;
    \gen_mux_rd[1].mux_rd_rise1_r_reg[1]\ : in STD_LOGIC;
    \gen_mux_rd[2].mux_rd_rise1_r_reg[2]\ : in STD_LOGIC;
    \gen_mux_rd[3].mux_rd_rise1_r_reg[3]\ : in STD_LOGIC;
    \gen_mux_rd[4].mux_rd_rise1_r_reg[4]\ : in STD_LOGIC;
    \gen_mux_rd[5].mux_rd_rise1_r_reg[5]\ : in STD_LOGIC;
    \gen_mux_rd[6].mux_rd_rise1_r_reg[6]\ : in STD_LOGIC;
    \gen_mux_rd[7].mux_rd_rise1_r_reg[7]\ : in STD_LOGIC;
    \gen_mux_rd[0].mux_rd_fall1_r_reg[0]\ : in STD_LOGIC;
    \gen_mux_rd[1].mux_rd_fall1_r_reg[1]\ : in STD_LOGIC;
    \gen_mux_rd[2].mux_rd_fall1_r_reg[2]\ : in STD_LOGIC;
    \gen_mux_rd[3].mux_rd_fall1_r_reg[3]\ : in STD_LOGIC;
    \gen_mux_rd[4].mux_rd_fall1_r_reg[4]\ : in STD_LOGIC;
    \gen_mux_rd[5].mux_rd_fall1_r_reg[5]\ : in STD_LOGIC;
    \gen_mux_rd[6].mux_rd_fall1_r_reg[6]\ : in STD_LOGIC;
    \gen_mux_rd[7].mux_rd_fall1_r_reg[7]\ : in STD_LOGIC;
    \gen_mux_rd[0].mux_rd_rise2_r_reg[0]\ : in STD_LOGIC;
    \gen_mux_rd[1].mux_rd_rise2_r_reg[1]\ : in STD_LOGIC;
    \gen_mux_rd[2].mux_rd_rise2_r_reg[2]\ : in STD_LOGIC;
    \gen_mux_rd[3].mux_rd_rise2_r_reg[3]\ : in STD_LOGIC;
    \gen_mux_rd[4].mux_rd_rise2_r_reg[4]\ : in STD_LOGIC;
    \gen_mux_rd[5].mux_rd_rise2_r_reg[5]\ : in STD_LOGIC;
    \gen_mux_rd[6].mux_rd_rise2_r_reg[6]\ : in STD_LOGIC;
    \gen_mux_rd[7].mux_rd_rise2_r_reg[7]\ : in STD_LOGIC;
    \gen_mux_rd[0].mux_rd_fall2_r_reg[0]\ : in STD_LOGIC;
    \gen_mux_rd[1].mux_rd_fall2_r_reg[1]\ : in STD_LOGIC;
    \gen_mux_rd[2].mux_rd_fall2_r_reg[2]\ : in STD_LOGIC;
    \gen_mux_rd[3].mux_rd_fall2_r_reg[3]\ : in STD_LOGIC;
    \gen_mux_rd[4].mux_rd_fall2_r_reg[4]\ : in STD_LOGIC;
    \gen_mux_rd[5].mux_rd_fall2_r_reg[5]\ : in STD_LOGIC;
    \gen_mux_rd[6].mux_rd_fall2_r_reg[6]\ : in STD_LOGIC;
    \gen_mux_rd[7].mux_rd_fall2_r_reg[7]\ : in STD_LOGIC;
    \gen_mux_rd[0].mux_rd_rise3_r_reg[0]\ : in STD_LOGIC;
    \gen_mux_rd[1].mux_rd_rise3_r_reg[1]\ : in STD_LOGIC;
    \gen_mux_rd[2].mux_rd_rise3_r_reg[2]\ : in STD_LOGIC;
    \gen_mux_rd[3].mux_rd_rise3_r_reg[3]\ : in STD_LOGIC;
    \gen_mux_rd[4].mux_rd_rise3_r_reg[4]\ : in STD_LOGIC;
    \gen_mux_rd[5].mux_rd_rise3_r_reg[5]\ : in STD_LOGIC;
    \gen_mux_rd[6].mux_rd_rise3_r_reg[6]\ : in STD_LOGIC;
    \gen_mux_rd[7].mux_rd_rise3_r_reg[7]\ : in STD_LOGIC;
    \gen_mux_rd[0].mux_rd_fall3_r_reg[0]\ : in STD_LOGIC;
    \gen_mux_rd[1].mux_rd_fall3_r_reg[1]\ : in STD_LOGIC;
    \gen_mux_rd[2].mux_rd_fall3_r_reg[2]\ : in STD_LOGIC;
    \gen_mux_rd[3].mux_rd_fall3_r_reg[3]\ : in STD_LOGIC;
    \gen_mux_rd[4].mux_rd_fall3_r_reg[4]\ : in STD_LOGIC;
    \gen_mux_rd[5].mux_rd_fall3_r_reg[5]\ : in STD_LOGIC;
    \gen_mux_rd[6].mux_rd_fall3_r_reg[6]\ : in STD_LOGIC;
    \gen_mux_rd[7].mux_rd_fall3_r_reg[7]\ : in STD_LOGIC;
    out_fifo : in STD_LOGIC;
    out_fifo_0 : in STD_LOGIC_VECTOR ( 31 downto 0 );
    out_fifo_1 : in STD_LOGIC;
    \gen_mux_rd[1].mux_rd_rise0_r_reg[1]_0\ : in STD_LOGIC;
    \gen_mux_rd[1].mux_rd_rise0_r_reg[1]_1\ : in STD_LOGIC;
    \gen_mux_rd[2].mux_rd_rise0_r_reg[2]_0\ : in STD_LOGIC;
    \gen_mux_rd[3].mux_rd_rise0_r_reg[3]_0\ : in STD_LOGIC;
    \gen_mux_rd[5].mux_rd_rise0_r_reg[5]_0\ : in STD_LOGIC;
    \gen_mux_rd[6].mux_rd_rise0_r_reg[6]_0\ : in STD_LOGIC;
    \gen_mux_rd[7].mux_rd_rise0_r_reg[7]_0\ : in STD_LOGIC;
    \gen_mux_rd[1].mux_rd_fall0_r_reg[1]_0\ : in STD_LOGIC;
    \gen_mux_rd[3].mux_rd_fall0_r_reg[3]_0\ : in STD_LOGIC;
    \gen_mux_rd[5].mux_rd_fall0_r_reg[5]_0\ : in STD_LOGIC;
    \gen_mux_rd[6].mux_rd_fall0_r_reg[6]_0\ : in STD_LOGIC;
    \gen_mux_rd[7].mux_rd_fall0_r_reg[7]_0\ : in STD_LOGIC;
    \gen_mux_rd[0].mux_rd_rise1_r_reg[0]_0\ : in STD_LOGIC;
    \gen_mux_rd[1].mux_rd_rise1_r_reg[1]_0\ : in STD_LOGIC;
    \gen_mux_rd[3].mux_rd_rise1_r_reg[3]_0\ : in STD_LOGIC;
    \gen_mux_rd[5].mux_rd_rise1_r_reg[5]_0\ : in STD_LOGIC;
    \gen_mux_rd[6].mux_rd_rise1_r_reg[6]_0\ : in STD_LOGIC;
    \gen_mux_rd[7].mux_rd_rise1_r_reg[7]_0\ : in STD_LOGIC;
    \gen_mux_rd[1].mux_rd_fall1_r_reg[1]_0\ : in STD_LOGIC;
    \gen_mux_rd[3].mux_rd_fall1_r_reg[3]_0\ : in STD_LOGIC;
    \gen_mux_rd[5].mux_rd_fall1_r_reg[5]_0\ : in STD_LOGIC;
    \gen_mux_rd[6].mux_rd_fall1_r_reg[6]_0\ : in STD_LOGIC;
    \gen_mux_rd[7].mux_rd_fall1_r_reg[7]_0\ : in STD_LOGIC;
    \gen_mux_rd[0].mux_rd_rise2_r_reg[0]_0\ : in STD_LOGIC;
    \gen_mux_rd[1].mux_rd_rise2_r_reg[1]_0\ : in STD_LOGIC;
    \gen_mux_rd[2].mux_rd_rise2_r_reg[2]_0\ : in STD_LOGIC;
    \gen_mux_rd[3].mux_rd_rise2_r_reg[3]_0\ : in STD_LOGIC;
    \gen_mux_rd[5].mux_rd_rise2_r_reg[5]_0\ : in STD_LOGIC;
    \gen_mux_rd[6].mux_rd_rise2_r_reg[6]_0\ : in STD_LOGIC;
    \gen_mux_rd[7].mux_rd_rise2_r_reg[7]_0\ : in STD_LOGIC;
    \gen_mux_rd[1].mux_rd_fall2_r_reg[1]_0\ : in STD_LOGIC;
    \gen_mux_rd[2].mux_rd_fall2_r_reg[2]_0\ : in STD_LOGIC;
    \gen_mux_rd[3].mux_rd_fall2_r_reg[3]_0\ : in STD_LOGIC;
    \gen_mux_rd[5].mux_rd_fall2_r_reg[5]_0\ : in STD_LOGIC;
    \gen_mux_rd[6].mux_rd_fall2_r_reg[6]_0\ : in STD_LOGIC;
    \gen_mux_rd[7].mux_rd_fall2_r_reg[7]_0\ : in STD_LOGIC;
    \gen_mux_rd[1].mux_rd_rise3_r_reg[1]_0\ : in STD_LOGIC;
    \gen_mux_rd[2].mux_rd_rise3_r_reg[2]_0\ : in STD_LOGIC;
    \gen_mux_rd[3].mux_rd_rise3_r_reg[3]_0\ : in STD_LOGIC;
    \gen_mux_rd[5].mux_rd_rise3_r_reg[5]_0\ : in STD_LOGIC;
    \gen_mux_rd[6].mux_rd_rise3_r_reg[6]_0\ : in STD_LOGIC;
    \gen_mux_rd[7].mux_rd_rise3_r_reg[7]_0\ : in STD_LOGIC;
    \gen_mux_rd[0].mux_rd_fall3_r_reg[0]_0\ : in STD_LOGIC;
    \gen_mux_rd[1].mux_rd_fall3_r_reg[1]_0\ : in STD_LOGIC;
    \gen_mux_rd[2].mux_rd_fall3_r_reg[2]_0\ : in STD_LOGIC;
    \gen_mux_rd[3].mux_rd_fall3_r_reg[3]_0\ : in STD_LOGIC;
    \gen_mux_rd[4].mux_rd_fall3_r_reg[4]_0\ : in STD_LOGIC;
    \gen_mux_rd[5].mux_rd_fall3_r_reg[5]_0\ : in STD_LOGIC;
    \gen_mux_rd[6].mux_rd_fall3_r_reg[6]_0\ : in STD_LOGIC;
    \gen_mux_rd[7].mux_rd_fall3_r_reg[7]_0\ : in STD_LOGIC;
    \gen_mux_rd[0].mux_rd_rise0_r_reg[0]_1\ : in STD_LOGIC;
    \gen_mux_rd[4].mux_rd_rise0_r_reg[4]_0\ : in STD_LOGIC;
    \gen_mux_rd[0].mux_rd_fall0_r_reg[0]_0\ : in STD_LOGIC;
    \gen_mux_rd[2].mux_rd_fall0_r_reg[2]_0\ : in STD_LOGIC;
    \gen_mux_rd[4].mux_rd_fall0_r_reg[4]_0\ : in STD_LOGIC;
    \gen_mux_rd[2].mux_rd_rise1_r_reg[2]_0\ : in STD_LOGIC;
    \gen_mux_rd[4].mux_rd_rise1_r_reg[4]_0\ : in STD_LOGIC;
    \gen_mux_rd[0].mux_rd_fall1_r_reg[0]_0\ : in STD_LOGIC;
    \gen_mux_rd[2].mux_rd_fall1_r_reg[2]_0\ : in STD_LOGIC;
    \gen_mux_rd[4].mux_rd_fall1_r_reg[4]_0\ : in STD_LOGIC;
    \gen_mux_rd[4].mux_rd_rise2_r_reg[4]_0\ : in STD_LOGIC;
    \gen_mux_rd[0].mux_rd_fall2_r_reg[0]_0\ : in STD_LOGIC;
    \gen_mux_rd[4].mux_rd_fall2_r_reg[4]_0\ : in STD_LOGIC;
    \gen_mux_rd[0].mux_rd_rise3_r_reg[0]_0\ : in STD_LOGIC;
    \gen_mux_rd[4].mux_rd_rise3_r_reg[4]_0\ : in STD_LOGIC;
    \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    phy_dout : in STD_LOGIC_VECTOR ( 71 downto 0 );
    \out_fifo_i_75__5\ : in STD_LOGIC_VECTOR ( 71 downto 0 );
    \out_fifo_i_75__6\ : in STD_LOGIC_VECTOR ( 71 downto 0 );
    \out_fifo_i_75__7\ : in STD_LOGIC_VECTOR ( 71 downto 0 );
    \my_full_reg[1]\ : in STD_LOGIC;
    \my_full_reg[1]_0\ : in STD_LOGIC;
    \my_full_reg[1]_1\ : in STD_LOGIC;
    calib_sel : in STD_LOGIC_VECTOR ( 1 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of mig_mig_7series_v4_2_ddr_phy_4lanes : entity is "mig_7series_v4_2_ddr_phy_4lanes";
end mig_mig_7series_v4_2_ddr_phy_4lanes;

architecture STRUCTURE of mig_mig_7series_v4_2_ddr_phy_4lanes is
  signal A_pi_counter_read_val : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal A_pi_rst_div2 : STD_LOGIC;
  attribute async_reg : string;
  attribute async_reg of A_pi_rst_div2 : signal is "true";
  signal A_po_counter_read_val : STD_LOGIC_VECTOR ( 8 downto 0 );
  signal A_rst_primitives : STD_LOGIC;
  signal B_pi_rst_div2 : STD_LOGIC;
  attribute async_reg of B_pi_rst_div2 : signal is "true";
  signal B_rclk : STD_LOGIC;
  signal C_pi_counter_read_val : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal C_pi_rst_div2 : STD_LOGIC;
  attribute async_reg of C_pi_rst_div2 : signal is "true";
  signal C_po_counter_read_val : STD_LOGIC_VECTOR ( 8 downto 0 );
  signal D_pi_counter_read_val : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal D_pi_rst_div2 : STD_LOGIC;
  attribute async_reg of D_pi_rst_div2 : signal is "true";
  signal D_po_counter_read_val : STD_LOGIC_VECTOR ( 8 downto 0 );
  signal \ddr_byte_lane_A.ddr_byte_lane_A_n_22\ : STD_LOGIC;
  signal \ddr_byte_lane_A.ddr_byte_lane_A_n_40\ : STD_LOGIC;
  signal \ddr_byte_lane_A.ddr_byte_lane_A_n_44\ : STD_LOGIC;
  signal \ddr_byte_lane_B.ddr_byte_lane_B_n_158\ : STD_LOGIC;
  signal \ddr_byte_lane_B.ddr_byte_lane_B_n_22\ : STD_LOGIC;
  signal \ddr_byte_lane_B.ddr_byte_lane_B_n_223\ : STD_LOGIC;
  signal \ddr_byte_lane_B.ddr_byte_lane_B_n_224\ : STD_LOGIC;
  signal \ddr_byte_lane_B.ddr_byte_lane_B_n_225\ : STD_LOGIC;
  signal \ddr_byte_lane_B.ddr_byte_lane_B_n_226\ : STD_LOGIC;
  signal \ddr_byte_lane_B.ddr_byte_lane_B_n_227\ : STD_LOGIC;
  signal \ddr_byte_lane_B.ddr_byte_lane_B_n_228\ : STD_LOGIC;
  signal \ddr_byte_lane_B.ddr_byte_lane_B_n_229\ : STD_LOGIC;
  signal \ddr_byte_lane_B.ddr_byte_lane_B_n_230\ : STD_LOGIC;
  signal \ddr_byte_lane_B.ddr_byte_lane_B_n_231\ : STD_LOGIC;
  signal \ddr_byte_lane_B.ddr_byte_lane_B_n_232\ : STD_LOGIC;
  signal \ddr_byte_lane_B.ddr_byte_lane_B_n_233\ : STD_LOGIC;
  signal \ddr_byte_lane_B.ddr_byte_lane_B_n_234\ : STD_LOGIC;
  signal \ddr_byte_lane_B.ddr_byte_lane_B_n_235\ : STD_LOGIC;
  signal \ddr_byte_lane_B.ddr_byte_lane_B_n_236\ : STD_LOGIC;
  signal \ddr_byte_lane_B.ddr_byte_lane_B_n_237\ : STD_LOGIC;
  signal \ddr_byte_lane_B.ddr_byte_lane_B_n_28\ : STD_LOGIC;
  signal \ddr_byte_lane_C.ddr_byte_lane_C_n_109\ : STD_LOGIC;
  signal \ddr_byte_lane_D.ddr_byte_lane_D_n_22\ : STD_LOGIC;
  signal \ddr_byte_lane_D.ddr_byte_lane_D_n_236\ : STD_LOGIC;
  signal \ddr_byte_lane_D.ddr_byte_lane_D_n_237\ : STD_LOGIC;
  signal \ddr_byte_lane_D.ddr_byte_lane_D_n_238\ : STD_LOGIC;
  signal \ddr_byte_lane_D.ddr_byte_lane_D_n_239\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_0\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_1\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_0\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_1\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_0\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_1\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_0\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_1\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_0\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_1\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_0\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_1\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_0\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_1\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_0\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_1\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_1\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_0\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_1\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_0\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_1\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_0\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_1\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_0\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_1\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_0\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_1\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_0\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_1\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_0\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_1\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_0\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_1\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_0\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_1\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_0\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_1\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_0\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_1\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_0\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_1\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_0\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_1\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_0\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_1\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_0\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_1\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_1\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_0\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_1\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_0\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_1\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_0\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_1\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_0\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_1\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_0\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_1\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_0\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_1\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_0\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_1\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_0\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_1\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_0\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_1\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_0\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_1\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_0\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_1\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_0\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_1\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_0\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_1\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_0\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_1\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_0\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_1\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_1\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_0\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_1\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_0\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_1\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_0\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_1\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_0\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_1\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_0\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_1\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_0\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_1\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_0\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_1\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_0\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_0\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_0\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_0\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_0\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_0\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_0\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_0\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_0\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_1\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_0\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_1\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_0\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_1\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_0\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_1\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_0\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_1\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_0\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_1\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_0\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_1\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_1\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]\ : STD_LOGIC;
  signal \dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/my_empty\ : STD_LOGIC_VECTOR ( 3 to 3 );
  signal \dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/my_empty_2\ : STD_LOGIC_VECTOR ( 3 to 3 );
  signal \dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/my_empty_4\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \^if_empty_r\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \^if_empty_r_0\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal if_empty_r_5 : STD_LOGIC_VECTOR ( 3 to 3 );
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo/entry_cnt_reg\ : STD_LOGIC_VECTOR ( 4 downto 2 );
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo/entry_cnt_reg_0\ : STD_LOGIC_VECTOR ( 4 downto 2 );
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo/entry_cnt_reg_1\ : STD_LOGIC_VECTOR ( 4 downto 2 );
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo/entry_cnt_reg_3\ : STD_LOGIC_VECTOR ( 4 downto 2 );
  signal ofs_rdy_r_i_3_n_0 : STD_LOGIC;
  signal ofs_rdy_r_i_4_n_0 : STD_LOGIC;
  signal phaser_ctl_bus : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal phy_control_i_n_0 : STD_LOGIC;
  signal phy_control_i_n_1 : STD_LOGIC;
  signal phy_control_i_n_14 : STD_LOGIC;
  signal phy_control_i_n_15 : STD_LOGIC;
  signal phy_control_i_n_16 : STD_LOGIC;
  signal phy_control_i_n_17 : STD_LOGIC;
  signal phy_encalib : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \rclk_delay_reg[10]_srl11_n_0\ : STD_LOGIC;
  signal \^ref_dll_lock_w__0\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \^rst_out_reg_0\ : STD_LOGIC;
  signal \^rst_primitives\ : STD_LOGIC;
  signal rst_r4 : STD_LOGIC;
  attribute BOX_TYPE : string;
  attribute BOX_TYPE of phaser_ref_i : label is "PRIMITIVE";
  attribute BOX_TYPE of phy_control_i : label is "PRIMITIVE";
  attribute srl_bus_name : string;
  attribute srl_bus_name of \rclk_delay_reg[10]_srl11\ : label is "\u_mig_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/rclk_delay_reg ";
  attribute srl_name : string;
  attribute srl_name of \rclk_delay_reg[10]_srl11\ : label is "\u_mig_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/rclk_delay_reg[10]_srl11 ";
begin
  \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0\ <= \^dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_0\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_0\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_1\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_1\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_0\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_0\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_1\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_1\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_0\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_0\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_1\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_1\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_0\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_0\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_1\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_1\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_0\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_0\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_1\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_1\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_0\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_0\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_1\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_1\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_0\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_0\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_1\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_1\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_0\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_0\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_1\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_1\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_1\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_1\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_0\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_0\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_1\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_1\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_0\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_0\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_1\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_1\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_0\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_0\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_1\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_1\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_0\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_0\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_1\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_1\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_0\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_0\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_1\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_1\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_0\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_0\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_1\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_1\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_0\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_0\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_1\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_1\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_0\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_0\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_1\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_1\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_0\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_0\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_1\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_1\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_0\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_0\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_1\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_1\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_0\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_0\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_1\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_1\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_0\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_0\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_1\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_1\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_0\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_0\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_1\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_1\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_0\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_0\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_1\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_1\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_0\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_0\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_1\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_1\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_1\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_1\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_0\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_0\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_1\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_1\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_0\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_0\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_1\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_1\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_0\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_0\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_1\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_1\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_0\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_0\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_1\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_1\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_0\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_0\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_1\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_1\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_0\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_0\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_1\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_1\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_0\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_0\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_1\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_1\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_0\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_0\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_1\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_1\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_0\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_0\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_1\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_1\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_0\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_0\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_1\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_1\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_0\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_0\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_1\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_1\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_0\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_0\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_1\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_1\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_0\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_0\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_1\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_1\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_0\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_0\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_1\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_1\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_0\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_0\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_1\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_1\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_1\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_1\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_0\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_0\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_1\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_1\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_0\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_0\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_1\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_1\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_0\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_0\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_1\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_1\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_0\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_0\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_1\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_1\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_0\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_0\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_1\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_1\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_0\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_0\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_1\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_1\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_0\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_0\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_1\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_1\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_0\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_0\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_0\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_0\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_0\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_0\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_0\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_0\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_0\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_0\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_0\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_0\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_0\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_0\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_0\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_0\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_0\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_0\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_1\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_1\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_0\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_0\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_1\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_1\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_0\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_0\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_1\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_1\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_0\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_0\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_1\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_1\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_0\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_0\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_1\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_1\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_0\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_0\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_1\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_1\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_0\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_0\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_1\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_1\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_1\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_1\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]\;
  if_empty_r(0) <= \^if_empty_r\(0);
  if_empty_r_0(0) <= \^if_empty_r_0\(0);
  \ref_dll_lock_w__0\(0) <= \^ref_dll_lock_w__0\(0);
  rst_out_reg_0 <= \^rst_out_reg_0\;
  rst_primitives <= \^rst_primitives\;
A_rst_primitives_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => \^rst_primitives\,
      Q => A_rst_primitives,
      R => '0'
    );
\ddr_byte_lane_A.ddr_byte_lane_A\: entity work.mig_mig_7series_v4_2_ddr_byte_lane_25
     port map (
      A_rst_primitives => A_rst_primitives,
      A_rst_primitives_reg => A_rst_primitives_reg_0,
      A_rst_primitives_reg_0 => \ddr_byte_lane_A.ddr_byte_lane_A_n_22\,
      A_rst_primitives_reg_1(8 downto 0) => A_po_counter_read_val(8 downto 0),
      CLKB0 => CLKB0,
      COUNTERLOADVAL(5 downto 0) => COUNTERLOADVAL(5 downto 0),
      COUNTERREADVAL(5 downto 0) => A_pi_counter_read_val(5 downto 0),
      LD0 => LD0,
      PCENABLECALIB(1 downto 0) => phy_encalib(1 downto 0),
      Q(2 downto 0) => \of_pre_fifo_gen.u_ddr_of_pre_fifo/entry_cnt_reg\(4 downto 2),
      \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0\ => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]\,
      \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1\ => \ddr_byte_lane_A.ddr_byte_lane_A_n_40\,
      \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_2\ => \ddr_byte_lane_A.ddr_byte_lane_A_n_44\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]\,
      freq_refclk => freq_refclk,
      idelay_inc => idelay_inc,
      idelay_ld_rst => idelay_ld_rst,
      if_empty => if_empty,
      if_empty_r(0) => if_empty_r_5(3),
      if_empty_v(0) => if_empty_v(0),
      ififo_rst_reg_0 => ififo_rst_reg,
      in0(0) => in0(0),
      \input_[9].iserdes_dq_.iserdesdq\ => \input_[9].iserdes_dq_.iserdesdq\,
      mem_dq_in(7 downto 0) => mem_dq_in(7 downto 0),
      mem_dq_out(8 downto 0) => mem_dq_out(8 downto 0),
      mem_dq_ts(8 downto 0) => mem_dq_ts(8 downto 0),
      mem_dqs_in(0) => mem_dqs_in(0),
      mem_refclk => mem_refclk,
      my_empty(1) => \dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/my_empty_4\(3),
      my_empty(0) => \dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/my_empty_4\(0),
      my_empty_0(0) => \dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/my_empty_2\(3),
      \my_empty_reg[1]\ => \my_empty_reg[1]\,
      \my_empty_reg[7]\(7 downto 0) => \my_empty_reg[7]\(7 downto 0),
      \my_empty_reg[7]_0\(7 downto 0) => \my_empty_reg[7]_0\(7 downto 0),
      \my_empty_reg[7]_1\(7 downto 0) => \my_empty_reg[7]_1\(7 downto 0),
      \my_empty_reg[7]_2\(7 downto 0) => \my_empty_reg[7]_2\(7 downto 0),
      \my_empty_reg[7]_3\(7 downto 0) => \my_empty_reg[7]_3\(7 downto 0),
      \my_empty_reg[7]_4\(7 downto 0) => \my_empty_reg[7]_4\(7 downto 0),
      \my_empty_reg[7]_5\(7 downto 0) => \my_empty_reg[7]_5\(7 downto 0),
      \my_empty_reg[7]_6\(7 downto 0) => \my_empty_reg[7]_6\(7 downto 0),
      \my_full_reg[1]\ => \ddr_byte_lane_D.ddr_byte_lane_D_n_236\,
      \my_full_reg[4]\ => \entry_cnt_reg[4]\,
      out_dqs_4 => out_dqs_4,
      out_fifo_0 => out_fifo,
      out_fifo_1(7) => out_fifo_0(28),
      out_fifo_1(6) => out_fifo_0(24),
      out_fifo_1(5) => out_fifo_0(20),
      out_fifo_1(4) => out_fifo_0(16),
      out_fifo_1(3) => out_fifo_0(12),
      out_fifo_1(2) => out_fifo_0(8),
      out_fifo_1(1) => out_fifo_0(4),
      out_fifo_1(0) => out_fifo_0(0),
      out_fifo_2 => out_fifo_1,
      phaser_ctl_bus(3 downto 2) => phaser_ctl_bus(9 downto 8),
      phaser_ctl_bus(1) => phaser_ctl_bus(4),
      phaser_ctl_bus(0) => phaser_ctl_bus(0),
      phy_data_wr_en => phy_data_wr_en,
      phy_dout(71 downto 0) => phy_dout(71 downto 0),
      phy_if_empty_r_reg => phy_if_empty_r_reg,
      phy_if_reset => phy_if_reset,
      phy_rddata_en => phy_rddata_en,
      \pi_dqs_found_lanes_r1_reg[0]\ => \pi_dqs_found_lanes_r1_reg[0]\,
      \pi_dqs_found_lanes_r1_reg[0]_0\ => \pi_dqs_found_lanes_r1_reg[0]_0\,
      \pi_dqs_found_lanes_r1_reg[0]_1\ => \pi_dqs_found_lanes_r1_reg[0]_1\,
      \pi_dqs_found_lanes_r1_reg[0]_2\ => \pi_dqs_found_lanes_r1_reg[0]_2\,
      \po_counter_read_val_reg[8]\ => \po_counter_read_val_reg[8]_1\,
      \po_counter_read_val_reg[8]_0\ => \po_counter_read_val_reg[8]_2\,
      \po_counter_read_val_reg[8]_1\ => \po_counter_read_val_reg[8]_3\,
      \rd_ptr_reg[3]\(63 downto 0) => \rd_ptr_reg[3]\(63 downto 0),
      rst_r4 => rst_r4,
      sync_pulse => sync_pulse,
      ts_dqs_4 => ts_dqs_4,
      \wr_ptr[1]_i_2\ => \^if_empty_r_0\(0)
    );
\ddr_byte_lane_B.ddr_byte_lane_B\: entity work.\mig_mig_7series_v4_2_ddr_byte_lane__parameterized0_26\
     port map (
      A_rst_primitives => A_rst_primitives,
      A_rst_primitives_reg => A_rst_primitives_reg_1,
      A_rst_primitives_reg_0 => \ddr_byte_lane_B.ddr_byte_lane_B_n_22\,
      B_rclk => B_rclk,
      CLKB0_7 => CLKB0_7,
      COUNTERREADVAL(5 downto 0) => A_pi_counter_read_val(5 downto 0),
      D(5) => \ddr_byte_lane_B.ddr_byte_lane_B_n_223\,
      D(4) => \ddr_byte_lane_B.ddr_byte_lane_B_n_224\,
      D(3) => \ddr_byte_lane_B.ddr_byte_lane_B_n_225\,
      D(2) => \ddr_byte_lane_B.ddr_byte_lane_B_n_226\,
      D(1) => \ddr_byte_lane_B.ddr_byte_lane_B_n_227\,
      D(0) => \ddr_byte_lane_B.ddr_byte_lane_B_n_228\,
      LD0_7 => LD0_7,
      PCENABLECALIB(1 downto 0) => phy_encalib(1 downto 0),
      Q(2 downto 0) => \of_pre_fifo_gen.u_ddr_of_pre_fifo/entry_cnt_reg_0\(4 downto 2),
      calib_sel(1 downto 0) => calib_sel(1 downto 0),
      \calib_sel_reg[1]\(8) => \ddr_byte_lane_B.ddr_byte_lane_B_n_229\,
      \calib_sel_reg[1]\(7) => \ddr_byte_lane_B.ddr_byte_lane_B_n_230\,
      \calib_sel_reg[1]\(6) => \ddr_byte_lane_B.ddr_byte_lane_B_n_231\,
      \calib_sel_reg[1]\(5) => \ddr_byte_lane_B.ddr_byte_lane_B_n_232\,
      \calib_sel_reg[1]\(4) => \ddr_byte_lane_B.ddr_byte_lane_B_n_233\,
      \calib_sel_reg[1]\(3) => \ddr_byte_lane_B.ddr_byte_lane_B_n_234\,
      \calib_sel_reg[1]\(2) => \ddr_byte_lane_B.ddr_byte_lane_B_n_235\,
      \calib_sel_reg[1]\(1) => \ddr_byte_lane_B.ddr_byte_lane_B_n_236\,
      \calib_sel_reg[1]\(0) => \ddr_byte_lane_B.ddr_byte_lane_B_n_237\,
      \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0\ => \^if_empty_r\(0),
      \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1\ => \ddr_byte_lane_B.ddr_byte_lane_B_n_28\,
      \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_2\ => \ddr_byte_lane_B.ddr_byte_lane_B_n_158\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]\,
      \entry_cnt_reg[4]\ => \entry_cnt_reg[4]\,
      freq_refclk => freq_refclk,
      \gen_mux_rd[0].mux_rd_fall0_r_reg[0]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_0\,
      \gen_mux_rd[0].mux_rd_fall0_r_reg[0]_0\ => \gen_mux_rd[0].mux_rd_fall0_r_reg[0]\,
      \gen_mux_rd[0].mux_rd_fall0_r_reg[0]_1\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]\,
      \gen_mux_rd[0].mux_rd_fall0_r_reg[0]_2\ => \gen_mux_rd[0].mux_rd_fall0_r_reg[0]_0\,
      \gen_mux_rd[0].mux_rd_fall1_r_reg[0]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_0\,
      \gen_mux_rd[0].mux_rd_fall1_r_reg[0]_0\ => \gen_mux_rd[0].mux_rd_fall1_r_reg[0]\,
      \gen_mux_rd[0].mux_rd_fall1_r_reg[0]_1\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]\,
      \gen_mux_rd[0].mux_rd_fall1_r_reg[0]_2\ => \gen_mux_rd[0].mux_rd_fall1_r_reg[0]_0\,
      \gen_mux_rd[0].mux_rd_fall2_r_reg[0]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_0\,
      \gen_mux_rd[0].mux_rd_fall2_r_reg[0]_0\ => \gen_mux_rd[0].mux_rd_fall2_r_reg[0]\,
      \gen_mux_rd[0].mux_rd_fall2_r_reg[0]_1\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]\,
      \gen_mux_rd[0].mux_rd_fall2_r_reg[0]_2\ => \gen_mux_rd[0].mux_rd_fall2_r_reg[0]_0\,
      \gen_mux_rd[0].mux_rd_fall3_r_reg[0]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_0\,
      \gen_mux_rd[0].mux_rd_fall3_r_reg[0]_0\ => \gen_mux_rd[0].mux_rd_fall3_r_reg[0]\,
      \gen_mux_rd[0].mux_rd_fall3_r_reg[0]_1\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]\,
      \gen_mux_rd[0].mux_rd_fall3_r_reg[0]_2\ => \gen_mux_rd[0].mux_rd_fall3_r_reg[0]_0\,
      \gen_mux_rd[0].mux_rd_rise0_r_reg[0]\(1 downto 0) => \gen_mux_rd[0].mux_rd_rise0_r_reg[0]\(1 downto 0),
      \gen_mux_rd[0].mux_rd_rise0_r_reg[0]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_0\,
      \gen_mux_rd[0].mux_rd_rise0_r_reg[0]_1\ => \gen_mux_rd[0].mux_rd_rise0_r_reg[0]_0\,
      \gen_mux_rd[0].mux_rd_rise0_r_reg[0]_2\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]\,
      \gen_mux_rd[0].mux_rd_rise0_r_reg[0]_3\ => \gen_mux_rd[0].mux_rd_rise0_r_reg[0]_1\,
      \gen_mux_rd[0].mux_rd_rise1_r_reg[0]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_0\,
      \gen_mux_rd[0].mux_rd_rise1_r_reg[0]_0\ => \gen_mux_rd[0].mux_rd_rise1_r_reg[0]\,
      \gen_mux_rd[0].mux_rd_rise1_r_reg[0]_1\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]\,
      \gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2\ => \gen_mux_rd[0].mux_rd_rise1_r_reg[0]_0\,
      \gen_mux_rd[0].mux_rd_rise2_r_reg[0]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_0\,
      \gen_mux_rd[0].mux_rd_rise2_r_reg[0]_0\ => \gen_mux_rd[0].mux_rd_rise2_r_reg[0]\,
      \gen_mux_rd[0].mux_rd_rise2_r_reg[0]_1\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]\,
      \gen_mux_rd[0].mux_rd_rise2_r_reg[0]_2\ => \gen_mux_rd[0].mux_rd_rise2_r_reg[0]_0\,
      \gen_mux_rd[0].mux_rd_rise3_r_reg[0]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_0\,
      \gen_mux_rd[0].mux_rd_rise3_r_reg[0]_0\ => \gen_mux_rd[0].mux_rd_rise3_r_reg[0]\,
      \gen_mux_rd[0].mux_rd_rise3_r_reg[0]_1\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]\,
      \gen_mux_rd[0].mux_rd_rise3_r_reg[0]_2\ => \gen_mux_rd[0].mux_rd_rise3_r_reg[0]_0\,
      \gen_mux_rd[1].mux_rd_fall0_r_reg[1]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_0\,
      \gen_mux_rd[1].mux_rd_fall0_r_reg[1]_0\ => \gen_mux_rd[1].mux_rd_fall0_r_reg[1]\,
      \gen_mux_rd[1].mux_rd_fall0_r_reg[1]_1\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_1\,
      \gen_mux_rd[1].mux_rd_fall0_r_reg[1]_2\ => \gen_mux_rd[1].mux_rd_fall0_r_reg[1]_0\,
      \gen_mux_rd[1].mux_rd_fall1_r_reg[1]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_0\,
      \gen_mux_rd[1].mux_rd_fall1_r_reg[1]_0\ => \gen_mux_rd[1].mux_rd_fall1_r_reg[1]\,
      \gen_mux_rd[1].mux_rd_fall1_r_reg[1]_1\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_1\,
      \gen_mux_rd[1].mux_rd_fall1_r_reg[1]_2\ => \gen_mux_rd[1].mux_rd_fall1_r_reg[1]_0\,
      \gen_mux_rd[1].mux_rd_fall2_r_reg[1]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_0\,
      \gen_mux_rd[1].mux_rd_fall2_r_reg[1]_0\ => \gen_mux_rd[1].mux_rd_fall2_r_reg[1]\,
      \gen_mux_rd[1].mux_rd_fall2_r_reg[1]_1\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_1\,
      \gen_mux_rd[1].mux_rd_fall2_r_reg[1]_2\ => \gen_mux_rd[1].mux_rd_fall2_r_reg[1]_0\,
      \gen_mux_rd[1].mux_rd_fall3_r_reg[1]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_0\,
      \gen_mux_rd[1].mux_rd_fall3_r_reg[1]_0\ => \gen_mux_rd[1].mux_rd_fall3_r_reg[1]\,
      \gen_mux_rd[1].mux_rd_fall3_r_reg[1]_1\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_1\,
      \gen_mux_rd[1].mux_rd_fall3_r_reg[1]_2\ => \gen_mux_rd[1].mux_rd_fall3_r_reg[1]_0\,
      \gen_mux_rd[1].mux_rd_rise0_r_reg[1]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0\,
      \gen_mux_rd[1].mux_rd_rise0_r_reg[1]_0\ => \gen_mux_rd[1].mux_rd_rise0_r_reg[1]\,
      \gen_mux_rd[1].mux_rd_rise0_r_reg[1]_1\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_1\,
      \gen_mux_rd[1].mux_rd_rise0_r_reg[1]_2\ => \gen_mux_rd[1].mux_rd_rise0_r_reg[1]_0\,
      \gen_mux_rd[1].mux_rd_rise0_r_reg[1]_3\ => \gen_mux_rd[1].mux_rd_rise0_r_reg[1]_1\,
      \gen_mux_rd[1].mux_rd_rise1_r_reg[1]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_0\,
      \gen_mux_rd[1].mux_rd_rise1_r_reg[1]_0\ => \gen_mux_rd[1].mux_rd_rise1_r_reg[1]\,
      \gen_mux_rd[1].mux_rd_rise1_r_reg[1]_1\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_1\,
      \gen_mux_rd[1].mux_rd_rise1_r_reg[1]_2\ => \gen_mux_rd[1].mux_rd_rise1_r_reg[1]_0\,
      \gen_mux_rd[1].mux_rd_rise2_r_reg[1]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_0\,
      \gen_mux_rd[1].mux_rd_rise2_r_reg[1]_0\ => \gen_mux_rd[1].mux_rd_rise2_r_reg[1]\,
      \gen_mux_rd[1].mux_rd_rise2_r_reg[1]_1\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_1\,
      \gen_mux_rd[1].mux_rd_rise2_r_reg[1]_2\ => \gen_mux_rd[1].mux_rd_rise2_r_reg[1]_0\,
      \gen_mux_rd[1].mux_rd_rise3_r_reg[1]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_0\,
      \gen_mux_rd[1].mux_rd_rise3_r_reg[1]_0\ => \gen_mux_rd[1].mux_rd_rise3_r_reg[1]\,
      \gen_mux_rd[1].mux_rd_rise3_r_reg[1]_1\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_1\,
      \gen_mux_rd[1].mux_rd_rise3_r_reg[1]_2\ => \gen_mux_rd[1].mux_rd_rise3_r_reg[1]_0\,
      \gen_mux_rd[2].mux_rd_fall0_r_reg[2]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_0\,
      \gen_mux_rd[2].mux_rd_fall0_r_reg[2]_0\ => \gen_mux_rd[2].mux_rd_fall0_r_reg[2]\,
      \gen_mux_rd[2].mux_rd_fall0_r_reg[2]_1\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_1\,
      \gen_mux_rd[2].mux_rd_fall0_r_reg[2]_2\ => \gen_mux_rd[2].mux_rd_fall0_r_reg[2]_0\,
      \gen_mux_rd[2].mux_rd_fall1_r_reg[2]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_0\,
      \gen_mux_rd[2].mux_rd_fall1_r_reg[2]_0\ => \gen_mux_rd[2].mux_rd_fall1_r_reg[2]\,
      \gen_mux_rd[2].mux_rd_fall1_r_reg[2]_1\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_1\,
      \gen_mux_rd[2].mux_rd_fall1_r_reg[2]_2\ => \gen_mux_rd[2].mux_rd_fall1_r_reg[2]_0\,
      \gen_mux_rd[2].mux_rd_fall2_r_reg[2]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_0\,
      \gen_mux_rd[2].mux_rd_fall2_r_reg[2]_0\ => \gen_mux_rd[2].mux_rd_fall2_r_reg[2]\,
      \gen_mux_rd[2].mux_rd_fall2_r_reg[2]_1\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_1\,
      \gen_mux_rd[2].mux_rd_fall2_r_reg[2]_2\ => \gen_mux_rd[2].mux_rd_fall2_r_reg[2]_0\,
      \gen_mux_rd[2].mux_rd_fall3_r_reg[2]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_0\,
      \gen_mux_rd[2].mux_rd_fall3_r_reg[2]_0\ => \gen_mux_rd[2].mux_rd_fall3_r_reg[2]\,
      \gen_mux_rd[2].mux_rd_fall3_r_reg[2]_1\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_1\,
      \gen_mux_rd[2].mux_rd_fall3_r_reg[2]_2\ => \gen_mux_rd[2].mux_rd_fall3_r_reg[2]_0\,
      \gen_mux_rd[2].mux_rd_rise0_r_reg[2]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_0\,
      \gen_mux_rd[2].mux_rd_rise0_r_reg[2]_0\ => \gen_mux_rd[2].mux_rd_rise0_r_reg[2]\,
      \gen_mux_rd[2].mux_rd_rise0_r_reg[2]_1\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_1\,
      \gen_mux_rd[2].mux_rd_rise0_r_reg[2]_2\ => \gen_mux_rd[2].mux_rd_rise0_r_reg[2]_0\,
      \gen_mux_rd[2].mux_rd_rise1_r_reg[2]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_0\,
      \gen_mux_rd[2].mux_rd_rise1_r_reg[2]_0\ => \gen_mux_rd[2].mux_rd_rise1_r_reg[2]\,
      \gen_mux_rd[2].mux_rd_rise1_r_reg[2]_1\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_1\,
      \gen_mux_rd[2].mux_rd_rise1_r_reg[2]_2\ => \gen_mux_rd[2].mux_rd_rise1_r_reg[2]_0\,
      \gen_mux_rd[2].mux_rd_rise2_r_reg[2]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_0\,
      \gen_mux_rd[2].mux_rd_rise2_r_reg[2]_0\ => \gen_mux_rd[2].mux_rd_rise2_r_reg[2]\,
      \gen_mux_rd[2].mux_rd_rise2_r_reg[2]_1\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_1\,
      \gen_mux_rd[2].mux_rd_rise2_r_reg[2]_2\ => \gen_mux_rd[2].mux_rd_rise2_r_reg[2]_0\,
      \gen_mux_rd[2].mux_rd_rise3_r_reg[2]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_0\,
      \gen_mux_rd[2].mux_rd_rise3_r_reg[2]_0\ => \gen_mux_rd[2].mux_rd_rise3_r_reg[2]\,
      \gen_mux_rd[2].mux_rd_rise3_r_reg[2]_1\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_1\,
      \gen_mux_rd[2].mux_rd_rise3_r_reg[2]_2\ => \gen_mux_rd[2].mux_rd_rise3_r_reg[2]_0\,
      \gen_mux_rd[3].mux_rd_fall0_r_reg[3]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_0\,
      \gen_mux_rd[3].mux_rd_fall0_r_reg[3]_0\ => \gen_mux_rd[3].mux_rd_fall0_r_reg[3]\,
      \gen_mux_rd[3].mux_rd_fall0_r_reg[3]_1\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_1\,
      \gen_mux_rd[3].mux_rd_fall0_r_reg[3]_2\ => \gen_mux_rd[3].mux_rd_fall0_r_reg[3]_0\,
      \gen_mux_rd[3].mux_rd_fall1_r_reg[3]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_0\,
      \gen_mux_rd[3].mux_rd_fall1_r_reg[3]_0\ => \gen_mux_rd[3].mux_rd_fall1_r_reg[3]\,
      \gen_mux_rd[3].mux_rd_fall1_r_reg[3]_1\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_1\,
      \gen_mux_rd[3].mux_rd_fall1_r_reg[3]_2\ => \gen_mux_rd[3].mux_rd_fall1_r_reg[3]_0\,
      \gen_mux_rd[3].mux_rd_fall2_r_reg[3]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_0\,
      \gen_mux_rd[3].mux_rd_fall2_r_reg[3]_0\ => \gen_mux_rd[3].mux_rd_fall2_r_reg[3]\,
      \gen_mux_rd[3].mux_rd_fall2_r_reg[3]_1\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_1\,
      \gen_mux_rd[3].mux_rd_fall2_r_reg[3]_2\ => \gen_mux_rd[3].mux_rd_fall2_r_reg[3]_0\,
      \gen_mux_rd[3].mux_rd_fall3_r_reg[3]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_0\,
      \gen_mux_rd[3].mux_rd_fall3_r_reg[3]_0\ => \gen_mux_rd[3].mux_rd_fall3_r_reg[3]\,
      \gen_mux_rd[3].mux_rd_fall3_r_reg[3]_1\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_1\,
      \gen_mux_rd[3].mux_rd_fall3_r_reg[3]_2\ => \gen_mux_rd[3].mux_rd_fall3_r_reg[3]_0\,
      \gen_mux_rd[3].mux_rd_rise0_r_reg[3]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0\,
      \gen_mux_rd[3].mux_rd_rise0_r_reg[3]_0\ => \gen_mux_rd[3].mux_rd_rise0_r_reg[3]\,
      \gen_mux_rd[3].mux_rd_rise0_r_reg[3]_1\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_1\,
      \gen_mux_rd[3].mux_rd_rise0_r_reg[3]_2\ => \gen_mux_rd[3].mux_rd_rise0_r_reg[3]_0\,
      \gen_mux_rd[3].mux_rd_rise1_r_reg[3]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_0\,
      \gen_mux_rd[3].mux_rd_rise1_r_reg[3]_0\ => \gen_mux_rd[3].mux_rd_rise1_r_reg[3]\,
      \gen_mux_rd[3].mux_rd_rise1_r_reg[3]_1\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_1\,
      \gen_mux_rd[3].mux_rd_rise1_r_reg[3]_2\ => \gen_mux_rd[3].mux_rd_rise1_r_reg[3]_0\,
      \gen_mux_rd[3].mux_rd_rise2_r_reg[3]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_0\,
      \gen_mux_rd[3].mux_rd_rise2_r_reg[3]_0\ => \gen_mux_rd[3].mux_rd_rise2_r_reg[3]\,
      \gen_mux_rd[3].mux_rd_rise2_r_reg[3]_1\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_1\,
      \gen_mux_rd[3].mux_rd_rise2_r_reg[3]_2\ => \gen_mux_rd[3].mux_rd_rise2_r_reg[3]_0\,
      \gen_mux_rd[3].mux_rd_rise3_r_reg[3]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_0\,
      \gen_mux_rd[3].mux_rd_rise3_r_reg[3]_0\ => \gen_mux_rd[3].mux_rd_rise3_r_reg[3]\,
      \gen_mux_rd[3].mux_rd_rise3_r_reg[3]_1\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_1\,
      \gen_mux_rd[3].mux_rd_rise3_r_reg[3]_2\ => \gen_mux_rd[3].mux_rd_rise3_r_reg[3]_0\,
      \gen_mux_rd[4].mux_rd_fall0_r_reg[4]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_0\,
      \gen_mux_rd[4].mux_rd_fall0_r_reg[4]_0\ => \gen_mux_rd[4].mux_rd_fall0_r_reg[4]\,
      \gen_mux_rd[4].mux_rd_fall0_r_reg[4]_1\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_1\,
      \gen_mux_rd[4].mux_rd_fall0_r_reg[4]_2\ => \gen_mux_rd[4].mux_rd_fall0_r_reg[4]_0\,
      \gen_mux_rd[4].mux_rd_fall1_r_reg[4]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_0\,
      \gen_mux_rd[4].mux_rd_fall1_r_reg[4]_0\ => \gen_mux_rd[4].mux_rd_fall1_r_reg[4]\,
      \gen_mux_rd[4].mux_rd_fall1_r_reg[4]_1\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_1\,
      \gen_mux_rd[4].mux_rd_fall1_r_reg[4]_2\ => \gen_mux_rd[4].mux_rd_fall1_r_reg[4]_0\,
      \gen_mux_rd[4].mux_rd_fall2_r_reg[4]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_0\,
      \gen_mux_rd[4].mux_rd_fall2_r_reg[4]_0\ => \gen_mux_rd[4].mux_rd_fall2_r_reg[4]\,
      \gen_mux_rd[4].mux_rd_fall2_r_reg[4]_1\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_1\,
      \gen_mux_rd[4].mux_rd_fall2_r_reg[4]_2\ => \gen_mux_rd[4].mux_rd_fall2_r_reg[4]_0\,
      \gen_mux_rd[4].mux_rd_fall3_r_reg[4]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_0\,
      \gen_mux_rd[4].mux_rd_fall3_r_reg[4]_0\ => \gen_mux_rd[4].mux_rd_fall3_r_reg[4]\,
      \gen_mux_rd[4].mux_rd_fall3_r_reg[4]_1\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_1\,
      \gen_mux_rd[4].mux_rd_fall3_r_reg[4]_2\ => \gen_mux_rd[4].mux_rd_fall3_r_reg[4]_0\,
      \gen_mux_rd[4].mux_rd_rise0_r_reg[4]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_0\,
      \gen_mux_rd[4].mux_rd_rise0_r_reg[4]_0\ => \gen_mux_rd[4].mux_rd_rise0_r_reg[4]\,
      \gen_mux_rd[4].mux_rd_rise0_r_reg[4]_1\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_1\,
      \gen_mux_rd[4].mux_rd_rise0_r_reg[4]_2\ => \gen_mux_rd[4].mux_rd_rise0_r_reg[4]_0\,
      \gen_mux_rd[4].mux_rd_rise1_r_reg[4]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_0\,
      \gen_mux_rd[4].mux_rd_rise1_r_reg[4]_0\ => \gen_mux_rd[4].mux_rd_rise1_r_reg[4]\,
      \gen_mux_rd[4].mux_rd_rise1_r_reg[4]_1\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_1\,
      \gen_mux_rd[4].mux_rd_rise1_r_reg[4]_2\ => \gen_mux_rd[4].mux_rd_rise1_r_reg[4]_0\,
      \gen_mux_rd[4].mux_rd_rise2_r_reg[4]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_0\,
      \gen_mux_rd[4].mux_rd_rise2_r_reg[4]_0\ => \gen_mux_rd[4].mux_rd_rise2_r_reg[4]\,
      \gen_mux_rd[4].mux_rd_rise2_r_reg[4]_1\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_1\,
      \gen_mux_rd[4].mux_rd_rise2_r_reg[4]_2\ => \gen_mux_rd[4].mux_rd_rise2_r_reg[4]_0\,
      \gen_mux_rd[4].mux_rd_rise3_r_reg[4]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_0\,
      \gen_mux_rd[4].mux_rd_rise3_r_reg[4]_0\ => \gen_mux_rd[4].mux_rd_rise3_r_reg[4]\,
      \gen_mux_rd[4].mux_rd_rise3_r_reg[4]_1\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_1\,
      \gen_mux_rd[4].mux_rd_rise3_r_reg[4]_2\ => \gen_mux_rd[4].mux_rd_rise3_r_reg[4]_0\,
      \gen_mux_rd[5].mux_rd_fall0_r_reg[5]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_0\,
      \gen_mux_rd[5].mux_rd_fall0_r_reg[5]_0\ => \gen_mux_rd[5].mux_rd_fall0_r_reg[5]\,
      \gen_mux_rd[5].mux_rd_fall0_r_reg[5]_1\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_1\,
      \gen_mux_rd[5].mux_rd_fall0_r_reg[5]_2\ => \gen_mux_rd[5].mux_rd_fall0_r_reg[5]_0\,
      \gen_mux_rd[5].mux_rd_fall1_r_reg[5]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_0\,
      \gen_mux_rd[5].mux_rd_fall1_r_reg[5]_0\ => \gen_mux_rd[5].mux_rd_fall1_r_reg[5]\,
      \gen_mux_rd[5].mux_rd_fall1_r_reg[5]_1\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_1\,
      \gen_mux_rd[5].mux_rd_fall1_r_reg[5]_2\ => \gen_mux_rd[5].mux_rd_fall1_r_reg[5]_0\,
      \gen_mux_rd[5].mux_rd_fall2_r_reg[5]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_0\,
      \gen_mux_rd[5].mux_rd_fall2_r_reg[5]_0\ => \gen_mux_rd[5].mux_rd_fall2_r_reg[5]\,
      \gen_mux_rd[5].mux_rd_fall2_r_reg[5]_1\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_1\,
      \gen_mux_rd[5].mux_rd_fall2_r_reg[5]_2\ => \gen_mux_rd[5].mux_rd_fall2_r_reg[5]_0\,
      \gen_mux_rd[5].mux_rd_fall3_r_reg[5]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_0\,
      \gen_mux_rd[5].mux_rd_fall3_r_reg[5]_0\ => \gen_mux_rd[5].mux_rd_fall3_r_reg[5]\,
      \gen_mux_rd[5].mux_rd_fall3_r_reg[5]_1\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_1\,
      \gen_mux_rd[5].mux_rd_fall3_r_reg[5]_2\ => \gen_mux_rd[5].mux_rd_fall3_r_reg[5]_0\,
      \gen_mux_rd[5].mux_rd_rise0_r_reg[5]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0\,
      \gen_mux_rd[5].mux_rd_rise0_r_reg[5]_0\ => \gen_mux_rd[5].mux_rd_rise0_r_reg[5]\,
      \gen_mux_rd[5].mux_rd_rise0_r_reg[5]_1\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_1\,
      \gen_mux_rd[5].mux_rd_rise0_r_reg[5]_2\ => \gen_mux_rd[5].mux_rd_rise0_r_reg[5]_0\,
      \gen_mux_rd[5].mux_rd_rise1_r_reg[5]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_0\,
      \gen_mux_rd[5].mux_rd_rise1_r_reg[5]_0\ => \gen_mux_rd[5].mux_rd_rise1_r_reg[5]\,
      \gen_mux_rd[5].mux_rd_rise1_r_reg[5]_1\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_1\,
      \gen_mux_rd[5].mux_rd_rise1_r_reg[5]_2\ => \gen_mux_rd[5].mux_rd_rise1_r_reg[5]_0\,
      \gen_mux_rd[5].mux_rd_rise2_r_reg[5]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_0\,
      \gen_mux_rd[5].mux_rd_rise2_r_reg[5]_0\ => \gen_mux_rd[5].mux_rd_rise2_r_reg[5]\,
      \gen_mux_rd[5].mux_rd_rise2_r_reg[5]_1\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_1\,
      \gen_mux_rd[5].mux_rd_rise2_r_reg[5]_2\ => \gen_mux_rd[5].mux_rd_rise2_r_reg[5]_0\,
      \gen_mux_rd[5].mux_rd_rise3_r_reg[5]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_0\,
      \gen_mux_rd[5].mux_rd_rise3_r_reg[5]_0\ => \gen_mux_rd[5].mux_rd_rise3_r_reg[5]\,
      \gen_mux_rd[5].mux_rd_rise3_r_reg[5]_1\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_1\,
      \gen_mux_rd[5].mux_rd_rise3_r_reg[5]_2\ => \gen_mux_rd[5].mux_rd_rise3_r_reg[5]_0\,
      \gen_mux_rd[6].mux_rd_fall0_r_reg[6]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_0\,
      \gen_mux_rd[6].mux_rd_fall0_r_reg[6]_0\ => \gen_mux_rd[6].mux_rd_fall0_r_reg[6]\,
      \gen_mux_rd[6].mux_rd_fall0_r_reg[6]_1\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_1\,
      \gen_mux_rd[6].mux_rd_fall0_r_reg[6]_2\ => \gen_mux_rd[6].mux_rd_fall0_r_reg[6]_0\,
      \gen_mux_rd[6].mux_rd_fall1_r_reg[6]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_0\,
      \gen_mux_rd[6].mux_rd_fall1_r_reg[6]_0\ => \gen_mux_rd[6].mux_rd_fall1_r_reg[6]\,
      \gen_mux_rd[6].mux_rd_fall1_r_reg[6]_1\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_1\,
      \gen_mux_rd[6].mux_rd_fall1_r_reg[6]_2\ => \gen_mux_rd[6].mux_rd_fall1_r_reg[6]_0\,
      \gen_mux_rd[6].mux_rd_fall2_r_reg[6]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_0\,
      \gen_mux_rd[6].mux_rd_fall2_r_reg[6]_0\ => \gen_mux_rd[6].mux_rd_fall2_r_reg[6]\,
      \gen_mux_rd[6].mux_rd_fall2_r_reg[6]_1\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_1\,
      \gen_mux_rd[6].mux_rd_fall2_r_reg[6]_2\ => \gen_mux_rd[6].mux_rd_fall2_r_reg[6]_0\,
      \gen_mux_rd[6].mux_rd_fall3_r_reg[6]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_0\,
      \gen_mux_rd[6].mux_rd_fall3_r_reg[6]_0\ => \gen_mux_rd[6].mux_rd_fall3_r_reg[6]\,
      \gen_mux_rd[6].mux_rd_fall3_r_reg[6]_1\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_1\,
      \gen_mux_rd[6].mux_rd_fall3_r_reg[6]_2\ => \gen_mux_rd[6].mux_rd_fall3_r_reg[6]_0\,
      \gen_mux_rd[6].mux_rd_rise0_r_reg[6]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_0\,
      \gen_mux_rd[6].mux_rd_rise0_r_reg[6]_0\ => \gen_mux_rd[6].mux_rd_rise0_r_reg[6]\,
      \gen_mux_rd[6].mux_rd_rise0_r_reg[6]_1\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_1\,
      \gen_mux_rd[6].mux_rd_rise0_r_reg[6]_2\ => \gen_mux_rd[6].mux_rd_rise0_r_reg[6]_0\,
      \gen_mux_rd[6].mux_rd_rise1_r_reg[6]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_0\,
      \gen_mux_rd[6].mux_rd_rise1_r_reg[6]_0\ => \gen_mux_rd[6].mux_rd_rise1_r_reg[6]\,
      \gen_mux_rd[6].mux_rd_rise1_r_reg[6]_1\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_1\,
      \gen_mux_rd[6].mux_rd_rise1_r_reg[6]_2\ => \gen_mux_rd[6].mux_rd_rise1_r_reg[6]_0\,
      \gen_mux_rd[6].mux_rd_rise2_r_reg[6]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_0\,
      \gen_mux_rd[6].mux_rd_rise2_r_reg[6]_0\ => \gen_mux_rd[6].mux_rd_rise2_r_reg[6]\,
      \gen_mux_rd[6].mux_rd_rise2_r_reg[6]_1\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_1\,
      \gen_mux_rd[6].mux_rd_rise2_r_reg[6]_2\ => \gen_mux_rd[6].mux_rd_rise2_r_reg[6]_0\,
      \gen_mux_rd[6].mux_rd_rise3_r_reg[6]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_0\,
      \gen_mux_rd[6].mux_rd_rise3_r_reg[6]_0\ => \gen_mux_rd[6].mux_rd_rise3_r_reg[6]\,
      \gen_mux_rd[6].mux_rd_rise3_r_reg[6]_1\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_1\,
      \gen_mux_rd[6].mux_rd_rise3_r_reg[6]_2\ => \gen_mux_rd[6].mux_rd_rise3_r_reg[6]_0\,
      \gen_mux_rd[7].mux_rd_fall0_r_reg[7]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_0\,
      \gen_mux_rd[7].mux_rd_fall0_r_reg[7]_0\ => \gen_mux_rd[7].mux_rd_fall0_r_reg[7]\,
      \gen_mux_rd[7].mux_rd_fall0_r_reg[7]_1\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_1\,
      \gen_mux_rd[7].mux_rd_fall0_r_reg[7]_2\ => \gen_mux_rd[7].mux_rd_fall0_r_reg[7]_0\,
      \gen_mux_rd[7].mux_rd_fall1_r_reg[7]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_0\,
      \gen_mux_rd[7].mux_rd_fall1_r_reg[7]_0\ => \gen_mux_rd[7].mux_rd_fall1_r_reg[7]\,
      \gen_mux_rd[7].mux_rd_fall1_r_reg[7]_1\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_1\,
      \gen_mux_rd[7].mux_rd_fall1_r_reg[7]_2\ => \gen_mux_rd[7].mux_rd_fall1_r_reg[7]_0\,
      \gen_mux_rd[7].mux_rd_fall2_r_reg[7]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_0\,
      \gen_mux_rd[7].mux_rd_fall2_r_reg[7]_0\ => \gen_mux_rd[7].mux_rd_fall2_r_reg[7]\,
      \gen_mux_rd[7].mux_rd_fall2_r_reg[7]_1\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_1\,
      \gen_mux_rd[7].mux_rd_fall2_r_reg[7]_2\ => \gen_mux_rd[7].mux_rd_fall2_r_reg[7]_0\,
      \gen_mux_rd[7].mux_rd_fall3_r_reg[7]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0\,
      \gen_mux_rd[7].mux_rd_fall3_r_reg[7]_0\ => \gen_mux_rd[7].mux_rd_fall3_r_reg[7]\,
      \gen_mux_rd[7].mux_rd_fall3_r_reg[7]_1\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_1\,
      \gen_mux_rd[7].mux_rd_fall3_r_reg[7]_2\ => \gen_mux_rd[7].mux_rd_fall3_r_reg[7]_0\,
      \gen_mux_rd[7].mux_rd_rise0_r_reg[7]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_0\,
      \gen_mux_rd[7].mux_rd_rise0_r_reg[7]_0\ => \gen_mux_rd[7].mux_rd_rise0_r_reg[7]\,
      \gen_mux_rd[7].mux_rd_rise0_r_reg[7]_1\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_1\,
      \gen_mux_rd[7].mux_rd_rise0_r_reg[7]_2\ => \gen_mux_rd[7].mux_rd_rise0_r_reg[7]_0\,
      \gen_mux_rd[7].mux_rd_rise1_r_reg[7]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_0\,
      \gen_mux_rd[7].mux_rd_rise1_r_reg[7]_0\ => \gen_mux_rd[7].mux_rd_rise1_r_reg[7]\,
      \gen_mux_rd[7].mux_rd_rise1_r_reg[7]_1\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_1\,
      \gen_mux_rd[7].mux_rd_rise1_r_reg[7]_2\ => \gen_mux_rd[7].mux_rd_rise1_r_reg[7]_0\,
      \gen_mux_rd[7].mux_rd_rise2_r_reg[7]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_0\,
      \gen_mux_rd[7].mux_rd_rise2_r_reg[7]_0\ => \gen_mux_rd[7].mux_rd_rise2_r_reg[7]\,
      \gen_mux_rd[7].mux_rd_rise2_r_reg[7]_1\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_1\,
      \gen_mux_rd[7].mux_rd_rise2_r_reg[7]_2\ => \gen_mux_rd[7].mux_rd_rise2_r_reg[7]_0\,
      \gen_mux_rd[7].mux_rd_rise3_r_reg[7]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_0\,
      \gen_mux_rd[7].mux_rd_rise3_r_reg[7]_0\ => \gen_mux_rd[7].mux_rd_rise3_r_reg[7]\,
      \gen_mux_rd[7].mux_rd_rise3_r_reg[7]_1\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_1\,
      \gen_mux_rd[7].mux_rd_rise3_r_reg[7]_2\ => \gen_mux_rd[7].mux_rd_rise3_r_reg[7]_0\,
      idelay_inc => idelay_inc,
      idelay_ld_rst_0 => idelay_ld_rst_0,
      ififo_rst_reg_0 => ififo_rst_reg_0,
      in0(0) => in0(1),
      \input_[9].iserdes_dq_.iserdesdq\ => \input_[9].iserdes_dq_.iserdesdq_0\,
      mem_dq_in(7 downto 0) => mem_dq_in(15 downto 8),
      mem_dq_out(8 downto 0) => mem_dq_out(17 downto 9),
      mem_dq_ts(8 downto 0) => mem_dq_ts(17 downto 9),
      mem_dqs_in(0) => mem_dqs_in(1),
      mem_refclk => mem_refclk,
      my_empty(0) => \dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/my_empty_2\(3),
      \my_empty_reg[1]\ => \my_empty_reg[1]_0\,
      \my_empty_reg[4]\ => \my_empty_reg[4]\(0),
      \my_empty_reg[4]_0\(0) => \dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/my_empty\(3),
      \my_empty_reg[7]\(7 downto 0) => \my_empty_reg[7]_7\(7 downto 0),
      \my_empty_reg[7]_0\(7 downto 0) => \my_empty_reg[7]_8\(7 downto 0),
      \my_empty_reg[7]_1\(7 downto 0) => \my_empty_reg[7]_9\(7 downto 0),
      \my_empty_reg[7]_2\(7 downto 0) => \my_empty_reg[7]_10\(7 downto 0),
      \my_empty_reg[7]_3\(7 downto 0) => \my_empty_reg[7]_11\(7 downto 0),
      \my_empty_reg[7]_4\(7 downto 0) => \my_empty_reg[7]_12\(7 downto 0),
      \my_empty_reg[7]_5\(7 downto 0) => \my_empty_reg[7]_13\(7 downto 0),
      \my_empty_reg[7]_6\(7 downto 0) => \my_empty_reg[7]_14\(7 downto 0),
      \my_full_reg[1]\ => \ddr_byte_lane_D.ddr_byte_lane_D_n_237\,
      out_dqs_5 => out_dqs_5,
      out_fifo_0 => out_fifo,
      out_fifo_1(7) => out_fifo_0(29),
      out_fifo_1(6) => out_fifo_0(25),
      out_fifo_1(5) => out_fifo_0(21),
      out_fifo_1(4) => out_fifo_0(17),
      out_fifo_1(3) => out_fifo_0(13),
      out_fifo_1(2) => out_fifo_0(9),
      out_fifo_1(1) => out_fifo_0(5),
      out_fifo_1(0) => out_fifo_0(1),
      out_fifo_2 => out_fifo_1,
      \out_fifo_i_75__5\(71 downto 0) => \out_fifo_i_75__5\(71 downto 0),
      phaser_ctl_bus(3 downto 2) => phaser_ctl_bus(11 downto 10),
      phaser_ctl_bus(1) => phaser_ctl_bus(5),
      phaser_ctl_bus(0) => phaser_ctl_bus(1),
      phy_data_wr_en => phy_data_wr_en,
      phy_if_reset => phy_if_reset,
      \pi_counter_read_val_reg[5]\(5 downto 0) => D_pi_counter_read_val(5 downto 0),
      \pi_counter_read_val_reg[5]_0\(5 downto 0) => C_pi_counter_read_val(5 downto 0),
      \pi_dqs_found_lanes_r1_reg[1]\ => \pi_dqs_found_lanes_r1_reg[1]\,
      \pi_dqs_found_lanes_r1_reg[1]_0\ => \pi_dqs_found_lanes_r1_reg[1]_0\,
      \pi_dqs_found_lanes_r1_reg[1]_1\ => \pi_dqs_found_lanes_r1_reg[1]_1\,
      \pi_dqs_found_lanes_r1_reg[1]_2\ => \pi_dqs_found_lanes_r1_reg[1]_2\,
      \pi_dqs_found_lanes_r1_reg[1]_3\(5 downto 0) => \pi_dqs_found_lanes_r1_reg[1]_3\(5 downto 0),
      \po_counter_read_val_reg[8]\ => \po_counter_read_val_reg[8]_4\,
      \po_counter_read_val_reg[8]_0\ => \po_counter_read_val_reg[8]_5\,
      \po_counter_read_val_reg[8]_1\ => \po_counter_read_val_reg[8]_6\,
      \po_counter_read_val_reg[8]_2\(8 downto 0) => A_po_counter_read_val(8 downto 0),
      \po_counter_read_val_reg[8]_3\(8 downto 0) => D_po_counter_read_val(8 downto 0),
      \po_counter_read_val_reg[8]_4\(8 downto 0) => C_po_counter_read_val(8 downto 0),
      \rd_mux_sel_r_reg[2]\ => \rd_mux_sel_r_reg[2]\,
      \rd_mux_sel_r_reg[2]_0\ => \rd_mux_sel_r_reg[2]_0\,
      \rd_mux_sel_r_reg[2]_1\ => \rd_mux_sel_r_reg[2]_1\,
      \rd_mux_sel_r_reg[2]_10\ => \rd_mux_sel_r_reg[2]_10\,
      \rd_mux_sel_r_reg[2]_11\ => \rd_mux_sel_r_reg[2]_11\,
      \rd_mux_sel_r_reg[2]_12\ => \rd_mux_sel_r_reg[2]_12\,
      \rd_mux_sel_r_reg[2]_13\ => \rd_mux_sel_r_reg[2]_13\,
      \rd_mux_sel_r_reg[2]_14\ => \rd_mux_sel_r_reg[2]_14\,
      \rd_mux_sel_r_reg[2]_15\ => \rd_mux_sel_r_reg[2]_15\,
      \rd_mux_sel_r_reg[2]_16\ => \rd_mux_sel_r_reg[2]_16\,
      \rd_mux_sel_r_reg[2]_17\ => \rd_mux_sel_r_reg[2]_17\,
      \rd_mux_sel_r_reg[2]_18\ => \rd_mux_sel_r_reg[2]_18\,
      \rd_mux_sel_r_reg[2]_19\ => \rd_mux_sel_r_reg[2]_19\,
      \rd_mux_sel_r_reg[2]_2\ => \rd_mux_sel_r_reg[2]_2\,
      \rd_mux_sel_r_reg[2]_20\ => \rd_mux_sel_r_reg[2]_20\,
      \rd_mux_sel_r_reg[2]_21\ => \rd_mux_sel_r_reg[2]_21\,
      \rd_mux_sel_r_reg[2]_22\ => \rd_mux_sel_r_reg[2]_22\,
      \rd_mux_sel_r_reg[2]_23\ => \rd_mux_sel_r_reg[2]_23\,
      \rd_mux_sel_r_reg[2]_24\ => \rd_mux_sel_r_reg[2]_24\,
      \rd_mux_sel_r_reg[2]_25\ => \rd_mux_sel_r_reg[2]_25\,
      \rd_mux_sel_r_reg[2]_26\ => \rd_mux_sel_r_reg[2]_26\,
      \rd_mux_sel_r_reg[2]_27\ => \rd_mux_sel_r_reg[2]_27\,
      \rd_mux_sel_r_reg[2]_28\ => \rd_mux_sel_r_reg[2]_28\,
      \rd_mux_sel_r_reg[2]_29\ => \rd_mux_sel_r_reg[2]_29\,
      \rd_mux_sel_r_reg[2]_3\ => \rd_mux_sel_r_reg[2]_3\,
      \rd_mux_sel_r_reg[2]_30\ => \rd_mux_sel_r_reg[2]_30\,
      \rd_mux_sel_r_reg[2]_31\ => \rd_mux_sel_r_reg[2]_31\,
      \rd_mux_sel_r_reg[2]_32\ => \rd_mux_sel_r_reg[2]_32\,
      \rd_mux_sel_r_reg[2]_33\ => \rd_mux_sel_r_reg[2]_33\,
      \rd_mux_sel_r_reg[2]_34\ => \rd_mux_sel_r_reg[2]_34\,
      \rd_mux_sel_r_reg[2]_35\ => \rd_mux_sel_r_reg[2]_35\,
      \rd_mux_sel_r_reg[2]_36\ => \rd_mux_sel_r_reg[2]_36\,
      \rd_mux_sel_r_reg[2]_37\ => \rd_mux_sel_r_reg[2]_37\,
      \rd_mux_sel_r_reg[2]_38\ => \rd_mux_sel_r_reg[2]_38\,
      \rd_mux_sel_r_reg[2]_39\ => \rd_mux_sel_r_reg[2]_39\,
      \rd_mux_sel_r_reg[2]_4\ => \rd_mux_sel_r_reg[2]_4\,
      \rd_mux_sel_r_reg[2]_40\ => \rd_mux_sel_r_reg[2]_40\,
      \rd_mux_sel_r_reg[2]_41\ => \rd_mux_sel_r_reg[2]_41\,
      \rd_mux_sel_r_reg[2]_42\ => \rd_mux_sel_r_reg[2]_42\,
      \rd_mux_sel_r_reg[2]_43\ => \rd_mux_sel_r_reg[2]_43\,
      \rd_mux_sel_r_reg[2]_44\ => \rd_mux_sel_r_reg[2]_44\,
      \rd_mux_sel_r_reg[2]_45\ => \rd_mux_sel_r_reg[2]_45\,
      \rd_mux_sel_r_reg[2]_46\ => \rd_mux_sel_r_reg[2]_46\,
      \rd_mux_sel_r_reg[2]_47\ => \rd_mux_sel_r_reg[2]_47\,
      \rd_mux_sel_r_reg[2]_48\ => \rd_mux_sel_r_reg[2]_48\,
      \rd_mux_sel_r_reg[2]_49\ => \rd_mux_sel_r_reg[2]_49\,
      \rd_mux_sel_r_reg[2]_5\ => \rd_mux_sel_r_reg[2]_5\,
      \rd_mux_sel_r_reg[2]_50\ => \rd_mux_sel_r_reg[2]_50\,
      \rd_mux_sel_r_reg[2]_51\ => \rd_mux_sel_r_reg[2]_51\,
      \rd_mux_sel_r_reg[2]_52\ => \rd_mux_sel_r_reg[2]_52\,
      \rd_mux_sel_r_reg[2]_53\ => \rd_mux_sel_r_reg[2]_53\,
      \rd_mux_sel_r_reg[2]_54\ => \rd_mux_sel_r_reg[2]_54\,
      \rd_mux_sel_r_reg[2]_55\ => \rd_mux_sel_r_reg[2]_55\,
      \rd_mux_sel_r_reg[2]_56\ => \rd_mux_sel_r_reg[2]_56\,
      \rd_mux_sel_r_reg[2]_57\ => \rd_mux_sel_r_reg[2]_57\,
      \rd_mux_sel_r_reg[2]_58\ => \rd_mux_sel_r_reg[2]_58\,
      \rd_mux_sel_r_reg[2]_59\ => \rd_mux_sel_r_reg[2]_59\,
      \rd_mux_sel_r_reg[2]_6\ => \rd_mux_sel_r_reg[2]_6\,
      \rd_mux_sel_r_reg[2]_60\ => \rd_mux_sel_r_reg[2]_60\,
      \rd_mux_sel_r_reg[2]_61\ => \rd_mux_sel_r_reg[2]_61\,
      \rd_mux_sel_r_reg[2]_62\ => \rd_mux_sel_r_reg[2]_62\,
      \rd_mux_sel_r_reg[2]_7\ => \rd_mux_sel_r_reg[2]_7\,
      \rd_mux_sel_r_reg[2]_8\ => \rd_mux_sel_r_reg[2]_8\,
      \rd_mux_sel_r_reg[2]_9\ => \rd_mux_sel_r_reg[2]_9\,
      \rd_ptr_reg[3]\(63 downto 0) => \rd_ptr_reg[3]_0\(63 downto 0),
      rst_r4 => rst_r4,
      sync_pulse => sync_pulse,
      ts_dqs_5 => ts_dqs_5,
      \wr_ptr[1]_i_2__0\ => \^if_empty_r_0\(0)
    );
\ddr_byte_lane_C.ddr_byte_lane_C\: entity work.\mig_mig_7series_v4_2_ddr_byte_lane__parameterized1_27\
     port map (
      A_rst_primitives => A_rst_primitives,
      A_rst_primitives_reg => A_rst_primitives_reg_2,
      A_rst_primitives_reg_0(5 downto 0) => C_pi_counter_read_val(5 downto 0),
      A_rst_primitives_reg_1(8 downto 0) => C_po_counter_read_val(8 downto 0),
      A_rst_primitives_reg_2 => A_rst_primitives_reg_4,
      CLKB0_8 => CLKB0_8,
      LD0_8 => LD0_8,
      PCENABLECALIB(1 downto 0) => phy_encalib(1 downto 0),
      Q(2 downto 0) => \of_pre_fifo_gen.u_ddr_of_pre_fifo/entry_cnt_reg_1\(4 downto 2),
      \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0\ => \^if_empty_r_0\(0),
      \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1\ => \^dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0\,
      \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_2\ => \ddr_byte_lane_C.ddr_byte_lane_C_n_109\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0\,
      freq_refclk => freq_refclk,
      idelay_inc => idelay_inc,
      idelay_ld_rst_1 => idelay_ld_rst_1,
      if_empty_r(0) => \^if_empty_r\(0),
      ififo_rst_reg_0 => ififo_rst_reg_1,
      in0(0) => in0(2),
      \input_[9].iserdes_dq_.iserdesdq\ => \input_[9].iserdes_dq_.iserdesdq_1\,
      mem_dq_in(7 downto 0) => mem_dq_in(23 downto 16),
      mem_dq_out(8 downto 0) => mem_dq_out(26 downto 18),
      mem_dq_ts(8 downto 0) => mem_dq_ts(26 downto 18),
      mem_dqs_in(0) => mem_dqs_in(2),
      mem_refclk => mem_refclk,
      \my_empty_reg[1]\ => \my_empty_reg[1]_1\,
      \my_empty_reg[4]\ => \my_empty_reg[4]_0\(0),
      \my_empty_reg[4]_0\(0) => \dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/my_empty_2\(3),
      \my_empty_reg[7]\(7 downto 0) => \my_empty_reg[7]_15\(7 downto 0),
      \my_empty_reg[7]_0\(7 downto 0) => \my_empty_reg[7]_16\(7 downto 0),
      \my_empty_reg[7]_1\(7 downto 0) => \my_empty_reg[7]_17\(7 downto 0),
      \my_empty_reg[7]_2\(7 downto 0) => \my_empty_reg[7]_18\(7 downto 0),
      \my_empty_reg[7]_3\(7 downto 0) => \my_empty_reg[7]_19\(7 downto 0),
      \my_empty_reg[7]_4\(7 downto 0) => \my_empty_reg[7]_20\(7 downto 0),
      \my_empty_reg[7]_5\(7 downto 0) => \my_empty_reg[7]_21\(7 downto 0),
      \my_empty_reg[7]_6\(7 downto 0) => \my_empty_reg[7]_22\(7 downto 0),
      \my_full_reg[1]\ => \ddr_byte_lane_D.ddr_byte_lane_D_n_238\,
      \my_full_reg[1]_0\ => \my_full_reg[1]\,
      \my_full_reg[1]_1\ => \my_full_reg[1]_0\,
      \my_full_reg[1]_2\ => \my_full_reg[1]_1\,
      \my_full_reg[1]_3\ => \ddr_byte_lane_A.ddr_byte_lane_A_n_44\,
      \my_full_reg[1]_4\ => \ddr_byte_lane_D.ddr_byte_lane_D_n_239\,
      \my_full_reg[4]\ => \entry_cnt_reg[4]\,
      ofs_rdy_r_reg => ofs_rdy_r_i_3_n_0,
      ofs_rdy_r_reg_0 => ofs_rdy_r_i_4_n_0,
      ofs_rdy_r_reg_1 => ofs_rdy_r_reg,
      ofs_rdy_r_reg_2 => ofs_rdy_r_reg_0,
      out_dqs_6 => out_dqs_6,
      out_fifo_0 => out_fifo,
      out_fifo_1(7) => out_fifo_0(30),
      out_fifo_1(6) => out_fifo_0(26),
      out_fifo_1(5) => out_fifo_0(22),
      out_fifo_1(4) => out_fifo_0(18),
      out_fifo_1(3) => out_fifo_0(14),
      out_fifo_1(2) => out_fifo_0(10),
      out_fifo_1(1) => out_fifo_0(6),
      out_fifo_1(0) => out_fifo_0(2),
      out_fifo_2 => out_fifo_1,
      \out_fifo_i_75__6\(71 downto 0) => \out_fifo_i_75__6\(71 downto 0),
      phaser_ctl_bus(3 downto 2) => phaser_ctl_bus(13 downto 12),
      phaser_ctl_bus(1) => phaser_ctl_bus(6),
      phaser_ctl_bus(0) => phaser_ctl_bus(2),
      phy_data_wr_en => phy_data_wr_en,
      phy_if_reset => phy_if_reset,
      phy_mc_data_full => phy_mc_data_full,
      \pi_dqs_found_lanes_r1_reg[2]\ => \pi_dqs_found_lanes_r1_reg[2]\,
      \pi_dqs_found_lanes_r1_reg[2]_0\ => \pi_dqs_found_lanes_r1_reg[2]_0\,
      \pi_dqs_found_lanes_r1_reg[2]_1\ => \pi_dqs_found_lanes_r1_reg[2]_1\,
      \pi_dqs_found_lanes_r1_reg[2]_2\ => \pi_dqs_found_lanes_r1_reg[2]_2\,
      \pi_dqs_found_lanes_r1_reg[2]_3\(5 downto 0) => \pi_dqs_found_lanes_r1_reg[2]_3\(5 downto 0),
      pi_phase_locked_all_r1_reg => \ddr_byte_lane_B.ddr_byte_lane_B_n_22\,
      pi_phase_locked_all_r1_reg_0 => \ddr_byte_lane_A.ddr_byte_lane_A_n_22\,
      pi_phase_locked_all_r1_reg_1 => \ddr_byte_lane_D.ddr_byte_lane_D_n_22\,
      pi_phase_locked_all_r1_reg_2 => pi_phase_locked_all_r1_reg,
      \po_counter_read_val_reg[8]\ => \po_counter_read_val_reg[8]_7\,
      \po_counter_read_val_reg[8]_0\ => \po_counter_read_val_reg[8]_8\,
      \po_counter_read_val_reg[8]_1\ => \po_counter_read_val_reg[8]_9\,
      \rd_ptr_reg[3]\(63 downto 0) => \rd_ptr_reg[3]_1\(63 downto 0),
      rst_r4 => rst_r4,
      sync_pulse => sync_pulse,
      ts_dqs_6 => ts_dqs_6,
      \wr_ptr[1]_i_2__6\(0) => \dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/my_empty\(3)
    );
\ddr_byte_lane_D.ddr_byte_lane_D\: entity work.\mig_mig_7series_v4_2_ddr_byte_lane__parameterized2_28\
     port map (
      A_rst_primitives => A_rst_primitives,
      A_rst_primitives_reg => A_rst_primitives_reg_3,
      A_rst_primitives_reg_0 => \ddr_byte_lane_D.ddr_byte_lane_D_n_22\,
      A_rst_primitives_reg_1(5 downto 0) => D_pi_counter_read_val(5 downto 0),
      A_rst_primitives_reg_2(8 downto 0) => D_po_counter_read_val(8 downto 0),
      CLKB0_9 => CLKB0_9,
      LD0_9 => LD0_9,
      PCENABLECALIB(1 downto 0) => phy_encalib(1 downto 0),
      Q(2 downto 0) => \of_pre_fifo_gen.u_ddr_of_pre_fifo/entry_cnt_reg_3\(4 downto 2),
      \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0\ => \ddr_byte_lane_D.ddr_byte_lane_D_n_236\,
      \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1\ => \ddr_byte_lane_D.ddr_byte_lane_D_n_237\,
      \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_2\ => \ddr_byte_lane_D.ddr_byte_lane_D_n_238\,
      \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_3\ => \ddr_byte_lane_D.ddr_byte_lane_D_n_239\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_2\,
      \entry_cnt_reg[4]\ => \entry_cnt_reg[4]\,
      freq_refclk => freq_refclk,
      \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]\(1 downto 0) => \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]\(1 downto 0),
      \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg[0]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_0\,
      \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg[0]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]\,
      \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg[0]_1\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]\,
      \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg[0]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_0\,
      \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg[0]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]\,
      \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg[0]_1\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]\,
      \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg[0]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_0\,
      \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg[0]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]\,
      \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg[0]_1\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]\,
      \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg[0]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_0\,
      \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg[0]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]\,
      \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg[0]_1\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]\,
      \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg[0]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_0\,
      \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg[0]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]\,
      \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg[0]_1\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]\,
      \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_0\,
      \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]\,
      \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_1\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]\,
      \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2\(1 downto 0) => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]\(1 downto 0),
      \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise2_r_reg[0]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_0\,
      \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise2_r_reg[0]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]\,
      \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise2_r_reg[0]_1\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]\,
      \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg[0]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_0\,
      \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg[0]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]\,
      \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg[0]_1\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]\,
      \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg[1]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_0\,
      \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg[1]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]\,
      \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg[1]_1\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_1\,
      \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg[1]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_0\,
      \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg[1]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]\,
      \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg[1]_1\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_1\,
      \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg[1]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_0\,
      \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg[1]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]\,
      \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg[1]_1\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_1\,
      \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg[1]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_0\,
      \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg[1]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]\,
      \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg[1]_1\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_1\,
      \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg[1]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0\,
      \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg[1]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]\,
      \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg[1]_1\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_1\,
      \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg[1]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_0\,
      \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg[1]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]\,
      \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg[1]_1\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_1\,
      \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg[1]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_0\,
      \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg[1]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]\,
      \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg[1]_1\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_1\,
      \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg[1]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_0\,
      \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg[1]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]\,
      \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg[1]_1\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_1\,
      \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg[2]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_0\,
      \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg[2]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]\,
      \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg[2]_1\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_1\,
      \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg[2]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_0\,
      \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg[2]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]\,
      \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg[2]_1\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_1\,
      \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg[2]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_0\,
      \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg[2]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]\,
      \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg[2]_1\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_1\,
      \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg[2]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_0\,
      \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg[2]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]\,
      \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg[2]_1\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_1\,
      \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg[2]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_0\,
      \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg[2]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]\,
      \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg[2]_1\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_1\,
      \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg[2]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_0\,
      \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg[2]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]\,
      \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg[2]_1\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_1\,
      \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg[2]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_0\,
      \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg[2]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]\,
      \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg[2]_1\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_1\,
      \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg[2]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_0\,
      \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg[2]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]\,
      \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg[2]_1\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_1\,
      \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg[3]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_0\,
      \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg[3]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]\,
      \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg[3]_1\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_1\,
      \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg[3]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_0\,
      \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg[3]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]\,
      \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg[3]_1\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_1\,
      \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg[3]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_0\,
      \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg[3]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]\,
      \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg[3]_1\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_1\,
      \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg[3]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_0\,
      \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg[3]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]\,
      \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg[3]_1\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_1\,
      \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg[3]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0\,
      \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg[3]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]\,
      \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg[3]_1\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_1\,
      \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg[3]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_0\,
      \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg[3]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]\,
      \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg[3]_1\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_1\,
      \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg[3]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_0\,
      \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg[3]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]\,
      \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg[3]_1\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_1\,
      \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise3_r_reg[3]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_0\,
      \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise3_r_reg[3]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]\,
      \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise3_r_reg[3]_1\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_1\,
      \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg[4]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_0\,
      \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg[4]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]\,
      \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg[4]_1\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_1\,
      \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg[4]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_0\,
      \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg[4]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]\,
      \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg[4]_1\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_1\,
      \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg[4]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_0\,
      \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg[4]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]\,
      \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg[4]_1\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_1\,
      \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg[4]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_0\,
      \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg[4]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]\,
      \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg[4]_1\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_1\,
      \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg[4]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_0\,
      \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg[4]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]\,
      \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg[4]_1\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_1\,
      \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg[4]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_0\,
      \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg[4]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]\,
      \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg[4]_1\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_1\,
      \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise2_r_reg[4]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_0\,
      \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise2_r_reg[4]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]\,
      \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise2_r_reg[4]_1\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_1\,
      \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg[4]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_0\,
      \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg[4]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]\,
      \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg[4]_1\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_1\,
      \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg[5]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_0\,
      \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg[5]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]\,
      \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg[5]_1\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_1\,
      \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg[5]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_0\,
      \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg[5]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]\,
      \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg[5]_1\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_1\,
      \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg[5]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_0\,
      \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg[5]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]\,
      \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg[5]_1\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_1\,
      \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg[5]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_0\,
      \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg[5]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]\,
      \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg[5]_1\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_1\,
      \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg[5]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0\,
      \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg[5]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]\,
      \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg[5]_1\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_1\,
      \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg[5]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_0\,
      \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg[5]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]\,
      \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg[5]_1\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_1\,
      \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg[5]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_0\,
      \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg[5]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]\,
      \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg[5]_1\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_1\,
      \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg[5]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_0\,
      \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg[5]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]\,
      \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg[5]_1\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_1\,
      \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg[6]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_0\,
      \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg[6]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]\,
      \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg[6]_1\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_1\,
      \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg[6]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_0\,
      \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg[6]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]\,
      \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg[6]_1\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_1\,
      \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg[6]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_0\,
      \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg[6]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]\,
      \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg[6]_1\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_1\,
      \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg[6]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_0\,
      \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg[6]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]\,
      \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg[6]_1\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_1\,
      \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg[6]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_0\,
      \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg[6]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]\,
      \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg[6]_1\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_1\,
      \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg[6]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_0\,
      \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg[6]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]\,
      \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg[6]_1\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_1\,
      \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg[6]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_0\,
      \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg[6]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]\,
      \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg[6]_1\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_1\,
      \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg[6]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_0\,
      \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg[6]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]\,
      \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg[6]_1\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_1\,
      \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg[7]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_0\,
      \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg[7]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]\,
      \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg[7]_1\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_1\,
      \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg[7]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_0\,
      \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg[7]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]\,
      \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg[7]_1\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_1\,
      \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg[7]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_0\,
      \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg[7]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]\,
      \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg[7]_1\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_1\,
      \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0\,
      \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]\,
      \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7]_1\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_1\,
      \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg[7]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_0\,
      \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg[7]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]\,
      \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg[7]_1\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_1\,
      \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg[7]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_0\,
      \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg[7]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]\,
      \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg[7]_1\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_1\,
      \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg[7]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_0\,
      \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg[7]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]\,
      \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg[7]_1\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_1\,
      \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise3_r_reg[7]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_0\,
      \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise3_r_reg[7]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]\,
      \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise3_r_reg[7]_1\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_1\,
      idelay_inc => idelay_inc,
      idelay_ld_rst_2 => idelay_ld_rst_2,
      if_empty_r(0) => \^if_empty_r\(0),
      if_empty_r_0(0) => if_empty_r_5(3),
      ififo_rst_reg_0 => ififo_rst_reg_2,
      in0(0) => in0(3),
      \input_[9].iserdes_dq_.iserdesdq\ => \input_[9].iserdes_dq_.iserdesdq_2\,
      mem_dq_in(7 downto 0) => mem_dq_in(31 downto 24),
      mem_dq_out(8 downto 0) => mem_dq_out(35 downto 27),
      mem_dq_ts(8 downto 0) => mem_dq_ts(35 downto 27),
      mem_dqs_in(0) => mem_dqs_in(3),
      mem_refclk => mem_refclk,
      \my_empty_reg[1]\ => \my_empty_reg[1]_2\,
      \my_empty_reg[4]\(1) => \dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/my_empty_4\(3),
      \my_empty_reg[4]\(0) => \dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/my_empty_4\(0),
      \my_empty_reg[7]\(7 downto 0) => \my_empty_reg[7]_23\(7 downto 0),
      \my_empty_reg[7]_0\(7 downto 0) => \my_empty_reg[7]_24\(7 downto 0),
      \my_empty_reg[7]_1\(7 downto 0) => \my_empty_reg[7]_25\(7 downto 0),
      \my_empty_reg[7]_2\(7 downto 0) => \my_empty_reg[7]_26\(7 downto 0),
      \my_empty_reg[7]_3\(7 downto 0) => \my_empty_reg[7]_27\(7 downto 0),
      \my_empty_reg[7]_4\(7 downto 0) => \my_empty_reg[7]_28\(7 downto 0),
      \my_empty_reg[7]_5\(7 downto 0) => \my_empty_reg[7]_29\(7 downto 0),
      \my_empty_reg[7]_6\(7 downto 0) => \my_empty_reg[7]_30\(7 downto 0),
      \my_full_reg[1]\ => \ddr_byte_lane_C.ddr_byte_lane_C_n_109\,
      \my_full_reg[1]_0\ => \my_full_reg[1]\,
      \my_full_reg[1]_1\ => \my_full_reg[1]_0\,
      \my_full_reg[1]_2\ => \my_full_reg[1]_1\,
      \my_full_reg[1]_3\ => \ddr_byte_lane_B.ddr_byte_lane_B_n_158\,
      \my_full_reg[1]_4\ => \ddr_byte_lane_A.ddr_byte_lane_A_n_40\,
      \my_full_reg[1]_5\ => \ddr_byte_lane_A.ddr_byte_lane_A_n_44\,
      \my_full_reg[1]_6\ => \ddr_byte_lane_B.ddr_byte_lane_B_n_28\,
      \my_full_reg[1]_7\ => \^dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0\,
      out_dqs_7 => out_dqs_7,
      out_fifo_0 => out_fifo,
      out_fifo_1(7) => out_fifo_0(31),
      out_fifo_1(6) => out_fifo_0(27),
      out_fifo_1(5) => out_fifo_0(23),
      out_fifo_1(4) => out_fifo_0(19),
      out_fifo_1(3) => out_fifo_0(15),
      out_fifo_1(2) => out_fifo_0(11),
      out_fifo_1(1) => out_fifo_0(7),
      out_fifo_1(0) => out_fifo_0(3),
      out_fifo_2 => out_fifo_1,
      \out_fifo_i_75__7\(71 downto 0) => \out_fifo_i_75__7\(71 downto 0),
      phaser_ctl_bus(3 downto 2) => phaser_ctl_bus(15 downto 14),
      phaser_ctl_bus(1) => phaser_ctl_bus(7),
      phaser_ctl_bus(0) => phaser_ctl_bus(3),
      phy_data_wr_en => phy_data_wr_en,
      phy_if_reset => phy_if_reset,
      \pi_dqs_found_lanes_r1_reg[3]\ => \pi_dqs_found_lanes_r1_reg[3]\,
      \pi_dqs_found_lanes_r1_reg[3]_0\ => \pi_dqs_found_lanes_r1_reg[3]_0\,
      \pi_dqs_found_lanes_r1_reg[3]_1\ => \pi_dqs_found_lanes_r1_reg[3]_1\,
      \pi_dqs_found_lanes_r1_reg[3]_2\ => \pi_dqs_found_lanes_r1_reg[3]_2\,
      \pi_dqs_found_lanes_r1_reg[3]_3\(5 downto 0) => \pi_dqs_found_lanes_r1_reg[3]_3\(5 downto 0),
      \po_counter_read_val_reg[8]\ => \po_counter_read_val_reg[8]_10\,
      \po_counter_read_val_reg[8]_0\ => \po_counter_read_val_reg[8]_11\,
      \po_counter_read_val_reg[8]_1\ => \po_counter_read_val_reg[8]_12\,
      \po_stg2_wrcal_cnt_reg[1]\ => \po_stg2_wrcal_cnt_reg[1]\,
      \po_stg2_wrcal_cnt_reg[1]_0\ => \po_stg2_wrcal_cnt_reg[1]_0\,
      \po_stg2_wrcal_cnt_reg[1]_1\ => \po_stg2_wrcal_cnt_reg[1]_1\,
      \po_stg2_wrcal_cnt_reg[1]_10\ => \po_stg2_wrcal_cnt_reg[1]_10\,
      \po_stg2_wrcal_cnt_reg[1]_11\ => \po_stg2_wrcal_cnt_reg[1]_11\,
      \po_stg2_wrcal_cnt_reg[1]_12\ => \po_stg2_wrcal_cnt_reg[1]_12\,
      \po_stg2_wrcal_cnt_reg[1]_13\ => \po_stg2_wrcal_cnt_reg[1]_13\,
      \po_stg2_wrcal_cnt_reg[1]_14\ => \po_stg2_wrcal_cnt_reg[1]_14\,
      \po_stg2_wrcal_cnt_reg[1]_15\ => \po_stg2_wrcal_cnt_reg[1]_15\,
      \po_stg2_wrcal_cnt_reg[1]_16\ => \po_stg2_wrcal_cnt_reg[1]_16\,
      \po_stg2_wrcal_cnt_reg[1]_17\ => \po_stg2_wrcal_cnt_reg[1]_17\,
      \po_stg2_wrcal_cnt_reg[1]_18\ => \po_stg2_wrcal_cnt_reg[1]_18\,
      \po_stg2_wrcal_cnt_reg[1]_19\ => \po_stg2_wrcal_cnt_reg[1]_19\,
      \po_stg2_wrcal_cnt_reg[1]_2\ => \po_stg2_wrcal_cnt_reg[1]_2\,
      \po_stg2_wrcal_cnt_reg[1]_20\ => \po_stg2_wrcal_cnt_reg[1]_20\,
      \po_stg2_wrcal_cnt_reg[1]_21\ => \po_stg2_wrcal_cnt_reg[1]_21\,
      \po_stg2_wrcal_cnt_reg[1]_22\ => \po_stg2_wrcal_cnt_reg[1]_22\,
      \po_stg2_wrcal_cnt_reg[1]_23\ => \po_stg2_wrcal_cnt_reg[1]_23\,
      \po_stg2_wrcal_cnt_reg[1]_24\ => \po_stg2_wrcal_cnt_reg[1]_24\,
      \po_stg2_wrcal_cnt_reg[1]_25\ => \po_stg2_wrcal_cnt_reg[1]_25\,
      \po_stg2_wrcal_cnt_reg[1]_26\ => \po_stg2_wrcal_cnt_reg[1]_26\,
      \po_stg2_wrcal_cnt_reg[1]_27\ => \po_stg2_wrcal_cnt_reg[1]_27\,
      \po_stg2_wrcal_cnt_reg[1]_28\ => \po_stg2_wrcal_cnt_reg[1]_28\,
      \po_stg2_wrcal_cnt_reg[1]_29\ => \po_stg2_wrcal_cnt_reg[1]_29\,
      \po_stg2_wrcal_cnt_reg[1]_3\ => \po_stg2_wrcal_cnt_reg[1]_3\,
      \po_stg2_wrcal_cnt_reg[1]_30\ => \po_stg2_wrcal_cnt_reg[1]_30\,
      \po_stg2_wrcal_cnt_reg[1]_31\ => \po_stg2_wrcal_cnt_reg[1]_31\,
      \po_stg2_wrcal_cnt_reg[1]_32\ => \po_stg2_wrcal_cnt_reg[1]_32\,
      \po_stg2_wrcal_cnt_reg[1]_33\ => \po_stg2_wrcal_cnt_reg[1]_33\,
      \po_stg2_wrcal_cnt_reg[1]_34\ => \po_stg2_wrcal_cnt_reg[1]_34\,
      \po_stg2_wrcal_cnt_reg[1]_35\ => \po_stg2_wrcal_cnt_reg[1]_35\,
      \po_stg2_wrcal_cnt_reg[1]_36\ => \po_stg2_wrcal_cnt_reg[1]_36\,
      \po_stg2_wrcal_cnt_reg[1]_37\ => \po_stg2_wrcal_cnt_reg[1]_37\,
      \po_stg2_wrcal_cnt_reg[1]_38\ => \po_stg2_wrcal_cnt_reg[1]_38\,
      \po_stg2_wrcal_cnt_reg[1]_39\ => \po_stg2_wrcal_cnt_reg[1]_39\,
      \po_stg2_wrcal_cnt_reg[1]_4\ => \po_stg2_wrcal_cnt_reg[1]_4\,
      \po_stg2_wrcal_cnt_reg[1]_40\ => \po_stg2_wrcal_cnt_reg[1]_40\,
      \po_stg2_wrcal_cnt_reg[1]_41\ => \po_stg2_wrcal_cnt_reg[1]_41\,
      \po_stg2_wrcal_cnt_reg[1]_42\ => \po_stg2_wrcal_cnt_reg[1]_42\,
      \po_stg2_wrcal_cnt_reg[1]_43\ => \po_stg2_wrcal_cnt_reg[1]_43\,
      \po_stg2_wrcal_cnt_reg[1]_44\ => \po_stg2_wrcal_cnt_reg[1]_44\,
      \po_stg2_wrcal_cnt_reg[1]_45\ => \po_stg2_wrcal_cnt_reg[1]_45\,
      \po_stg2_wrcal_cnt_reg[1]_46\ => \po_stg2_wrcal_cnt_reg[1]_46\,
      \po_stg2_wrcal_cnt_reg[1]_47\ => \po_stg2_wrcal_cnt_reg[1]_47\,
      \po_stg2_wrcal_cnt_reg[1]_48\ => \po_stg2_wrcal_cnt_reg[1]_48\,
      \po_stg2_wrcal_cnt_reg[1]_49\ => \po_stg2_wrcal_cnt_reg[1]_49\,
      \po_stg2_wrcal_cnt_reg[1]_5\ => \po_stg2_wrcal_cnt_reg[1]_5\,
      \po_stg2_wrcal_cnt_reg[1]_50\ => \po_stg2_wrcal_cnt_reg[1]_50\,
      \po_stg2_wrcal_cnt_reg[1]_51\ => \po_stg2_wrcal_cnt_reg[1]_51\,
      \po_stg2_wrcal_cnt_reg[1]_52\ => \po_stg2_wrcal_cnt_reg[1]_52\,
      \po_stg2_wrcal_cnt_reg[1]_53\ => \po_stg2_wrcal_cnt_reg[1]_53\,
      \po_stg2_wrcal_cnt_reg[1]_54\ => \po_stg2_wrcal_cnt_reg[1]_54\,
      \po_stg2_wrcal_cnt_reg[1]_55\ => \po_stg2_wrcal_cnt_reg[1]_55\,
      \po_stg2_wrcal_cnt_reg[1]_56\ => \po_stg2_wrcal_cnt_reg[1]_56\,
      \po_stg2_wrcal_cnt_reg[1]_57\ => \po_stg2_wrcal_cnt_reg[1]_57\,
      \po_stg2_wrcal_cnt_reg[1]_58\ => \po_stg2_wrcal_cnt_reg[1]_58\,
      \po_stg2_wrcal_cnt_reg[1]_59\ => \po_stg2_wrcal_cnt_reg[1]_59\,
      \po_stg2_wrcal_cnt_reg[1]_6\ => \po_stg2_wrcal_cnt_reg[1]_6\,
      \po_stg2_wrcal_cnt_reg[1]_60\ => \po_stg2_wrcal_cnt_reg[1]_60\,
      \po_stg2_wrcal_cnt_reg[1]_61\ => \po_stg2_wrcal_cnt_reg[1]_61\,
      \po_stg2_wrcal_cnt_reg[1]_62\ => \po_stg2_wrcal_cnt_reg[1]_62\,
      \po_stg2_wrcal_cnt_reg[1]_7\ => \po_stg2_wrcal_cnt_reg[1]_7\,
      \po_stg2_wrcal_cnt_reg[1]_8\ => \po_stg2_wrcal_cnt_reg[1]_8\,
      \po_stg2_wrcal_cnt_reg[1]_9\ => \po_stg2_wrcal_cnt_reg[1]_9\,
      \rd_mux_sel_r_reg[1]\ => \rd_mux_sel_r_reg[1]\,
      \rd_mux_sel_r_reg[1]_0\ => \rd_mux_sel_r_reg[1]_0\,
      \rd_mux_sel_r_reg[1]_1\ => \rd_mux_sel_r_reg[1]_1\,
      \rd_mux_sel_r_reg[1]_10\ => \rd_mux_sel_r_reg[1]_10\,
      \rd_mux_sel_r_reg[1]_11\ => \rd_mux_sel_r_reg[1]_11\,
      \rd_mux_sel_r_reg[1]_12\ => \rd_mux_sel_r_reg[1]_12\,
      \rd_mux_sel_r_reg[1]_13\ => \rd_mux_sel_r_reg[1]_13\,
      \rd_mux_sel_r_reg[1]_14\ => \rd_mux_sel_r_reg[1]_14\,
      \rd_mux_sel_r_reg[1]_15\ => \rd_mux_sel_r_reg[1]_15\,
      \rd_mux_sel_r_reg[1]_16\ => \rd_mux_sel_r_reg[1]_16\,
      \rd_mux_sel_r_reg[1]_17\ => \rd_mux_sel_r_reg[1]_17\,
      \rd_mux_sel_r_reg[1]_18\ => \rd_mux_sel_r_reg[1]_18\,
      \rd_mux_sel_r_reg[1]_19\ => \rd_mux_sel_r_reg[1]_19\,
      \rd_mux_sel_r_reg[1]_2\ => \rd_mux_sel_r_reg[1]_2\,
      \rd_mux_sel_r_reg[1]_20\ => \rd_mux_sel_r_reg[1]_20\,
      \rd_mux_sel_r_reg[1]_21\ => \rd_mux_sel_r_reg[1]_21\,
      \rd_mux_sel_r_reg[1]_22\ => \rd_mux_sel_r_reg[1]_22\,
      \rd_mux_sel_r_reg[1]_23\ => \rd_mux_sel_r_reg[1]_23\,
      \rd_mux_sel_r_reg[1]_24\ => \rd_mux_sel_r_reg[1]_24\,
      \rd_mux_sel_r_reg[1]_25\ => \rd_mux_sel_r_reg[1]_25\,
      \rd_mux_sel_r_reg[1]_26\ => \rd_mux_sel_r_reg[1]_26\,
      \rd_mux_sel_r_reg[1]_27\ => \rd_mux_sel_r_reg[1]_27\,
      \rd_mux_sel_r_reg[1]_28\ => \rd_mux_sel_r_reg[1]_28\,
      \rd_mux_sel_r_reg[1]_29\ => \rd_mux_sel_r_reg[1]_29\,
      \rd_mux_sel_r_reg[1]_3\ => \rd_mux_sel_r_reg[1]_3\,
      \rd_mux_sel_r_reg[1]_30\ => \rd_mux_sel_r_reg[1]_30\,
      \rd_mux_sel_r_reg[1]_31\ => \rd_mux_sel_r_reg[1]_31\,
      \rd_mux_sel_r_reg[1]_32\ => \rd_mux_sel_r_reg[1]_32\,
      \rd_mux_sel_r_reg[1]_33\ => \rd_mux_sel_r_reg[1]_33\,
      \rd_mux_sel_r_reg[1]_34\ => \rd_mux_sel_r_reg[1]_34\,
      \rd_mux_sel_r_reg[1]_35\ => \rd_mux_sel_r_reg[1]_35\,
      \rd_mux_sel_r_reg[1]_36\ => \rd_mux_sel_r_reg[1]_36\,
      \rd_mux_sel_r_reg[1]_37\ => \rd_mux_sel_r_reg[1]_37\,
      \rd_mux_sel_r_reg[1]_38\ => \rd_mux_sel_r_reg[1]_38\,
      \rd_mux_sel_r_reg[1]_39\ => \rd_mux_sel_r_reg[1]_39\,
      \rd_mux_sel_r_reg[1]_4\ => \rd_mux_sel_r_reg[1]_4\,
      \rd_mux_sel_r_reg[1]_40\ => \rd_mux_sel_r_reg[1]_40\,
      \rd_mux_sel_r_reg[1]_41\ => \rd_mux_sel_r_reg[1]_41\,
      \rd_mux_sel_r_reg[1]_42\ => \rd_mux_sel_r_reg[1]_42\,
      \rd_mux_sel_r_reg[1]_43\ => \rd_mux_sel_r_reg[1]_43\,
      \rd_mux_sel_r_reg[1]_44\ => \rd_mux_sel_r_reg[1]_44\,
      \rd_mux_sel_r_reg[1]_45\ => \rd_mux_sel_r_reg[1]_45\,
      \rd_mux_sel_r_reg[1]_46\ => \rd_mux_sel_r_reg[1]_46\,
      \rd_mux_sel_r_reg[1]_47\ => \rd_mux_sel_r_reg[1]_47\,
      \rd_mux_sel_r_reg[1]_48\ => \rd_mux_sel_r_reg[1]_48\,
      \rd_mux_sel_r_reg[1]_49\ => \rd_mux_sel_r_reg[1]_49\,
      \rd_mux_sel_r_reg[1]_5\ => \rd_mux_sel_r_reg[1]_5\,
      \rd_mux_sel_r_reg[1]_50\ => \rd_mux_sel_r_reg[1]_50\,
      \rd_mux_sel_r_reg[1]_51\ => \rd_mux_sel_r_reg[1]_51\,
      \rd_mux_sel_r_reg[1]_52\ => \rd_mux_sel_r_reg[1]_52\,
      \rd_mux_sel_r_reg[1]_53\ => \rd_mux_sel_r_reg[1]_53\,
      \rd_mux_sel_r_reg[1]_54\ => \rd_mux_sel_r_reg[1]_54\,
      \rd_mux_sel_r_reg[1]_55\ => \rd_mux_sel_r_reg[1]_55\,
      \rd_mux_sel_r_reg[1]_56\ => \rd_mux_sel_r_reg[1]_56\,
      \rd_mux_sel_r_reg[1]_57\ => \rd_mux_sel_r_reg[1]_57\,
      \rd_mux_sel_r_reg[1]_58\ => \rd_mux_sel_r_reg[1]_58\,
      \rd_mux_sel_r_reg[1]_59\ => \rd_mux_sel_r_reg[1]_59\,
      \rd_mux_sel_r_reg[1]_6\ => \rd_mux_sel_r_reg[1]_6\,
      \rd_mux_sel_r_reg[1]_60\ => \rd_mux_sel_r_reg[1]_60\,
      \rd_mux_sel_r_reg[1]_61\ => \rd_mux_sel_r_reg[1]_61\,
      \rd_mux_sel_r_reg[1]_62\ => \rd_mux_sel_r_reg[1]_62\,
      \rd_mux_sel_r_reg[1]_7\ => \rd_mux_sel_r_reg[1]_7\,
      \rd_mux_sel_r_reg[1]_8\ => \rd_mux_sel_r_reg[1]_8\,
      \rd_mux_sel_r_reg[1]_9\ => \rd_mux_sel_r_reg[1]_9\,
      \rd_ptr_reg[3]\(63 downto 0) => \rd_ptr_reg[3]_2\(63 downto 0),
      rst_r4 => rst_r4,
      sync_pulse => sync_pulse,
      ts_dqs_7 => ts_dqs_7,
      \wr_ptr[1]_i_2__2\(0) => \dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/my_empty\(3)
    );
i_0: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => A_pi_rst_div2
    );
i_1: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => B_pi_rst_div2
    );
i_2: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => C_pi_rst_div2
    );
i_3: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => D_pi_rst_div2
    );
mcGo_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => \^rst_out_reg_0\,
      Q => mcGo_w(0),
      R => '0'
    );
ofs_rdy_r_i_3: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFFFE"
    )
        port map (
      I0 => \of_pre_fifo_gen.u_ddr_of_pre_fifo/entry_cnt_reg_1\(4),
      I1 => \of_pre_fifo_gen.u_ddr_of_pre_fifo/entry_cnt_reg_1\(2),
      I2 => \of_pre_fifo_gen.u_ddr_of_pre_fifo/entry_cnt_reg_1\(3),
      I3 => \of_pre_fifo_gen.u_ddr_of_pre_fifo/entry_cnt_reg_0\(4),
      I4 => \of_pre_fifo_gen.u_ddr_of_pre_fifo/entry_cnt_reg_0\(2),
      I5 => \of_pre_fifo_gen.u_ddr_of_pre_fifo/entry_cnt_reg_0\(3),
      O => ofs_rdy_r_i_3_n_0
    );
ofs_rdy_r_i_4: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFFFE"
    )
        port map (
      I0 => \of_pre_fifo_gen.u_ddr_of_pre_fifo/entry_cnt_reg\(4),
      I1 => \of_pre_fifo_gen.u_ddr_of_pre_fifo/entry_cnt_reg\(2),
      I2 => \of_pre_fifo_gen.u_ddr_of_pre_fifo/entry_cnt_reg\(3),
      I3 => \of_pre_fifo_gen.u_ddr_of_pre_fifo/entry_cnt_reg_3\(4),
      I4 => \of_pre_fifo_gen.u_ddr_of_pre_fifo/entry_cnt_reg_3\(2),
      I5 => \of_pre_fifo_gen.u_ddr_of_pre_fifo/entry_cnt_reg_3\(3),
      O => ofs_rdy_r_i_4_n_0
    );
phaser_ref_i: unisim.vcomponents.PHASER_REF
    generic map(
      IS_PWRDWN_INVERTED => '0',
      IS_RST_INVERTED => '0'
    )
        port map (
      CLKIN => freq_refclk,
      LOCKED => \^ref_dll_lock_w__0\(0),
      PWRDWN => '0',
      RST => RST0
    );
phy_control_i: unisim.vcomponents.PHY_CONTROL
    generic map(
      AO_TOGGLE => 1,
      AO_WRLVL_EN => B"0000",
      BURST_MODE => "TRUE",
      CLK_RATIO => 4,
      CMD_OFFSET => 8,
      CO_DURATION => 1,
      DATA_CTL_A_N => "TRUE",
      DATA_CTL_B_N => "TRUE",
      DATA_CTL_C_N => "TRUE",
      DATA_CTL_D_N => "TRUE",
      DISABLE_SEQ_MATCH => "TRUE",
      DI_DURATION => 1,
      DO_DURATION => 1,
      EVENTS_DELAY => 18,
      FOUR_WINDOW_CLOCKS => 63,
      MULTI_REGION => "TRUE",
      PHY_COUNT_ENABLE => "FALSE",
      RD_CMD_OFFSET_0 => 10,
      RD_CMD_OFFSET_1 => 10,
      RD_CMD_OFFSET_2 => 10,
      RD_CMD_OFFSET_3 => 10,
      RD_DURATION_0 => 6,
      RD_DURATION_1 => 6,
      RD_DURATION_2 => 6,
      RD_DURATION_3 => 6,
      SYNC_MODE => "FALSE",
      WR_CMD_OFFSET_0 => 8,
      WR_CMD_OFFSET_1 => 8,
      WR_CMD_OFFSET_2 => 8,
      WR_CMD_OFFSET_3 => 8,
      WR_DURATION_0 => 7,
      WR_DURATION_1 => 7,
      WR_DURATION_2 => 7,
      WR_DURATION_3 => 7
    )
        port map (
      AUXOUTPUT(3) => phy_control_i_n_14,
      AUXOUTPUT(2) => phy_control_i_n_15,
      AUXOUTPUT(1) => phy_control_i_n_16,
      AUXOUTPUT(0) => phy_control_i_n_17,
      INBURSTPENDING(3 downto 0) => phaser_ctl_bus(7 downto 4),
      INRANKA(1 downto 0) => phaser_ctl_bus(9 downto 8),
      INRANKB(1 downto 0) => phaser_ctl_bus(11 downto 10),
      INRANKC(1 downto 0) => phaser_ctl_bus(13 downto 12),
      INRANKD(1 downto 0) => phaser_ctl_bus(15 downto 14),
      MEMREFCLK => mem_refclk,
      OUTBURSTPENDING(3 downto 0) => phaser_ctl_bus(3 downto 0),
      PCENABLECALIB(1 downto 0) => phy_encalib(1 downto 0),
      PHYCLK => \entry_cnt_reg[4]\,
      PHYCTLALMOSTFULL => phy_control_i_n_0,
      PHYCTLEMPTY => phy_control_i_n_1,
      PHYCTLFULL => \_phy_ctl_full_p__0\(0),
      PHYCTLMSTREMPTY => phy_ctl_mstr_empty,
      PHYCTLREADY => phy_ctl_wr_i2_reg,
      PHYCTLWD(31 downto 25) => B"0000001",
      PHYCTLWD(24 downto 17) => Q(10 downto 3),
      PHYCTLWD(16 downto 3) => B"00000000000000",
      PHYCTLWD(2 downto 0) => Q(2 downto 0),
      PHYCTLWRENABLE => phy_ctl_wr_i2,
      PLLLOCK => pll_locked,
      READCALIBENABLE => phy_read_calib,
      REFDLLLOCK => \^ref_dll_lock_w__0\(0),
      RESET => phy_mc_ctl_full_r_reg,
      SYNCIN => sync_pulse,
      WRITECALIBENABLE => phy_write_calib
    );
\pi_counter_read_val_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => \ddr_byte_lane_B.ddr_byte_lane_B_n_228\,
      Q => \pi_counter_read_val_reg[5]_0\(0),
      R => '0'
    );
\pi_counter_read_val_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => \ddr_byte_lane_B.ddr_byte_lane_B_n_227\,
      Q => \pi_counter_read_val_reg[5]_0\(1),
      R => '0'
    );
\pi_counter_read_val_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => \ddr_byte_lane_B.ddr_byte_lane_B_n_226\,
      Q => \pi_counter_read_val_reg[5]_0\(2),
      R => '0'
    );
\pi_counter_read_val_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => \ddr_byte_lane_B.ddr_byte_lane_B_n_225\,
      Q => \pi_counter_read_val_reg[5]_0\(3),
      R => '0'
    );
\pi_counter_read_val_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => \ddr_byte_lane_B.ddr_byte_lane_B_n_224\,
      Q => \pi_counter_read_val_reg[5]_0\(4),
      R => '0'
    );
\pi_counter_read_val_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => \ddr_byte_lane_B.ddr_byte_lane_B_n_223\,
      Q => \pi_counter_read_val_reg[5]_0\(5),
      R => '0'
    );
\po_counter_read_val_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => \ddr_byte_lane_B.ddr_byte_lane_B_n_237\,
      Q => \po_counter_read_val_reg[8]_0\(0),
      R => '0'
    );
\po_counter_read_val_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => \ddr_byte_lane_B.ddr_byte_lane_B_n_236\,
      Q => \po_counter_read_val_reg[8]_0\(1),
      R => '0'
    );
\po_counter_read_val_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => \ddr_byte_lane_B.ddr_byte_lane_B_n_235\,
      Q => \po_counter_read_val_reg[8]_0\(2),
      R => '0'
    );
\po_counter_read_val_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => \ddr_byte_lane_B.ddr_byte_lane_B_n_234\,
      Q => \po_counter_read_val_reg[8]_0\(3),
      R => '0'
    );
\po_counter_read_val_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => \ddr_byte_lane_B.ddr_byte_lane_B_n_233\,
      Q => \po_counter_read_val_reg[8]_0\(4),
      R => '0'
    );
\po_counter_read_val_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => \ddr_byte_lane_B.ddr_byte_lane_B_n_232\,
      Q => \po_counter_read_val_reg[8]_0\(5),
      R => '0'
    );
\po_counter_read_val_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => \ddr_byte_lane_B.ddr_byte_lane_B_n_231\,
      Q => \po_counter_read_val_reg[8]_0\(6),
      R => '0'
    );
\po_counter_read_val_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => \ddr_byte_lane_B.ddr_byte_lane_B_n_230\,
      Q => \po_counter_read_val_reg[8]_0\(7),
      R => '0'
    );
\po_counter_read_val_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => \ddr_byte_lane_B.ddr_byte_lane_B_n_229\,
      Q => \po_counter_read_val_reg[8]_0\(8),
      R => '0'
    );
\rclk_delay_reg[10]_srl11\: unisim.vcomponents.SRL16E
     port map (
      A0 => '0',
      A1 => '1',
      A2 => '0',
      A3 => '1',
      CE => '1',
      CLK => \entry_cnt_reg[4]\,
      D => \rclk_delay_reg[11]_0\,
      Q => \rclk_delay_reg[10]_srl11_n_0\
    );
\rclk_delay_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => \rclk_delay_reg[10]_srl11_n_0\,
      Q => rclk_delay_11,
      R => '0'
    );
rst_out_reg: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      CLR => SR(0),
      D => rst_out_reg_1,
      Q => \^rst_out_reg_0\
    );
rst_primitives_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => rst_primitives_reg_0,
      Q => \^rst_primitives\,
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mig_mig_7series_v4_2_ddr_phy_4lanes_13 is
  port (
    out_dqs_0 : out STD_LOGIC;
    ts_dqs_0 : out STD_LOGIC;
    A_rst_primitives_reg_0 : out STD_LOGIC;
    mem_dq_out : out STD_LOGIC_VECTOR ( 35 downto 0 );
    mem_dq_ts : out STD_LOGIC_VECTOR ( 35 downto 0 );
    in0 : out STD_LOGIC_VECTOR ( 3 downto 0 );
    idelay_ld_rst_3 : out STD_LOGIC;
    out_dqs_1 : out STD_LOGIC;
    ts_dqs_1 : out STD_LOGIC;
    A_rst_primitives_reg_1 : out STD_LOGIC;
    idelay_ld_rst_4 : out STD_LOGIC;
    out_dqs_2 : out STD_LOGIC;
    ts_dqs_2 : out STD_LOGIC;
    A_rst_primitives_reg_2 : out STD_LOGIC;
    idelay_ld_rst_5 : out STD_LOGIC;
    out_dqs_3 : out STD_LOGIC;
    ts_dqs_3 : out STD_LOGIC;
    A_rst_primitives_reg_3 : out STD_LOGIC;
    idelay_ld_rst_6 : out STD_LOGIC;
    \_phy_ctl_full_p__0\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    phy_ctl_wr_i2_reg : out STD_LOGIC;
    \ref_dll_lock_w__0\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    rst_primitives : out STD_LOGIC;
    mcGo_w : out STD_LOGIC_VECTOR ( 0 to 0 );
    rst_out_reg_0 : out STD_LOGIC;
    rclk_delay_11 : out STD_LOGIC;
    \my_empty_reg[1]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]\ : out STD_LOGIC;
    \my_empty_reg[1]_0\ : out STD_LOGIC;
    \my_empty_reg[1]_1\ : out STD_LOGIC;
    \my_empty_reg[1]_2\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[0]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[0]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_1\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[0]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_1\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[0]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_1\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[0]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_1\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[0]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_1\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[0]_5\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_1\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[0]_6\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_1\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[0]_7\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[0]_8\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_1\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[0]_9\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_1\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[0]_10\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_1\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[0]_11\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_1\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[0]_12\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_1\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[0]_13\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_1\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[0]_14\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_1\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[0]_15\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[0]_16\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_1\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[0]_17\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_1\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[0]_18\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_1\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[0]_19\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_1\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[0]_20\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_1\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[0]_21\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_1\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[0]_22\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_1\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[0]_23\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[0]_24\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_1\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[0]_25\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_1\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[0]_26\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_1\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[0]_27\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_1\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[0]_28\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_1\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[0]_29\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_1\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[0]_30\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_1\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[0]_31\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[0]_32\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_1\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[0]_33\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_1\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[0]_34\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_1\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[0]_35\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_1\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[0]_36\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_1\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[0]_37\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_1\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[0]_38\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_1\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[0]_39\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[0]_40\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_1\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[0]_41\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_1\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[0]_42\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_1\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[0]_43\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_1\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[0]_44\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_1\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[0]_45\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_1\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[0]_46\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_1\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[0]_47\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[0]_48\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_1\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[0]_49\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_1\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[0]_50\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_1\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[0]_51\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_1\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[0]_52\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_1\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[0]_53\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_1\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[0]_54\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_1\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[0]_55\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[0]_56\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_1\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[0]_57\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_1\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[0]_58\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_1\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[0]_59\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_1\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[0]_60\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_1\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[0]_61\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_1\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[0]_62\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_1\ : out STD_LOGIC;
    A_rst_primitives_reg_4 : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_2\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_2\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_2\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_2\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_2\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_2\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_5\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_1\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_6\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_2\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_7\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_2\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_8\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_2\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_9\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_2\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_10\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_2\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_11\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_2\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_12\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_2\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_13\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_1\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_14\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_2\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_15\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_2\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_16\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_2\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_17\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_2\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_18\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_2\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_19\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_2\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_20\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_2\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_21\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_1\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_22\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_2\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_23\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_2\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_24\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_2\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_25\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_2\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_26\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_2\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_27\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_2\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_28\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_2\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_29\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_1\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_30\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_2\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_31\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_2\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_32\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_2\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_33\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_2\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_34\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_2\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_35\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_2\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_36\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_2\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_37\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_1\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_38\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_2\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_39\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_2\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_40\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_2\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_41\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_2\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_42\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_2\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_43\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_2\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_44\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_2\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_45\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_1\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_46\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_2\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_47\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_2\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_48\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_2\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_49\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_2\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_50\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_2\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_51\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_2\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_52\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_2\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_53\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_1\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_54\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_2\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_55\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_2\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_56\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_2\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_57\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_2\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_58\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_2\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_59\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_2\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_60\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_2\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_61\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_1\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_62\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_2\ : out STD_LOGIC;
    p_0_out : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_0\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_1\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_2\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_3\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_4\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_5\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_6\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_7\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_8\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_9\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_10\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_11\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_12\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_13\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_14\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_15\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_16\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_17\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_18\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_19\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_20\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_21\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_22\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_23\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_24\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_25\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_26\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_27\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_28\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_29\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_30\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_31\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_32\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_33\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_34\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_35\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_36\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_37\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_38\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_39\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_40\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_41\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_42\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_43\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_44\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_45\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_46\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_47\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_48\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_49\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_50\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_51\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_52\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_53\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_54\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_55\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_56\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_57\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_58\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_59\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_60\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_61\ : out STD_LOGIC;
    \rd_ptr_reg[3]\ : out STD_LOGIC_VECTOR ( 63 downto 0 );
    \rd_ptr_reg[3]_0\ : out STD_LOGIC_VECTOR ( 63 downto 0 );
    \rd_ptr_reg[3]_1\ : out STD_LOGIC_VECTOR ( 63 downto 0 );
    \rd_ptr_reg[3]_2\ : out STD_LOGIC_VECTOR ( 63 downto 0 );
    \entry_cnt_reg[4]\ : out STD_LOGIC;
    \entry_cnt_reg[4]_0\ : out STD_LOGIC;
    Q : out STD_LOGIC_VECTOR ( 8 downto 0 );
    \pi_counter_read_val_reg[5]_0\ : out STD_LOGIC_VECTOR ( 5 downto 0 );
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1\ : out STD_LOGIC;
    if_empty_v : out STD_LOGIC_VECTOR ( 0 to 0 );
    \entry_cnt_reg[4]_1\ : in STD_LOGIC;
    \input_[9].iserdes_dq_.iserdesdq\ : in STD_LOGIC;
    mem_dq_in : in STD_LOGIC_VECTOR ( 31 downto 0 );
    idelay_inc : in STD_LOGIC;
    LD0_10 : in STD_LOGIC;
    CLKB0_10 : in STD_LOGIC;
    \pi_dqs_found_lanes_r1_reg[8]\ : in STD_LOGIC;
    \pi_dqs_found_lanes_r1_reg[8]_0\ : in STD_LOGIC;
    \pi_dqs_found_lanes_r1_reg[8]_1\ : in STD_LOGIC;
    \pi_dqs_found_lanes_r1_reg[8]_2\ : in STD_LOGIC;
    freq_refclk : in STD_LOGIC;
    mem_refclk : in STD_LOGIC;
    mem_dqs_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
    ififo_rst_reg : in STD_LOGIC;
    sync_pulse : in STD_LOGIC;
    \pi_dqs_found_lanes_r1_reg[8]_3\ : in STD_LOGIC_VECTOR ( 5 downto 0 );
    \po_counter_read_val_reg[8]_0\ : in STD_LOGIC;
    \po_counter_read_val_reg[8]_1\ : in STD_LOGIC;
    \po_counter_read_val_reg[8]_2\ : in STD_LOGIC;
    \my_empty_reg[7]\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    D2 : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \my_empty_reg[7]_0\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \my_empty_reg[7]_1\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \my_empty_reg[7]_2\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \my_empty_reg[7]_3\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \my_empty_reg[7]_4\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \my_empty_reg[7]_5\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    phy_if_reset : in STD_LOGIC;
    \input_[9].iserdes_dq_.iserdesdq_0\ : in STD_LOGIC;
    LD0_11 : in STD_LOGIC;
    CLKB0_11 : in STD_LOGIC;
    \pi_dqs_found_lanes_r1_reg[9]\ : in STD_LOGIC;
    \pi_dqs_found_lanes_r1_reg[9]_0\ : in STD_LOGIC;
    \pi_dqs_found_lanes_r1_reg[9]_1\ : in STD_LOGIC;
    \pi_dqs_found_lanes_r1_reg[9]_2\ : in STD_LOGIC;
    ififo_rst_reg_0 : in STD_LOGIC;
    \pi_dqs_found_lanes_r1_reg[9]_3\ : in STD_LOGIC_VECTOR ( 5 downto 0 );
    \po_counter_read_val_reg[8]_3\ : in STD_LOGIC;
    \po_counter_read_val_reg[8]_4\ : in STD_LOGIC;
    \po_counter_read_val_reg[8]_5\ : in STD_LOGIC;
    \my_empty_reg[7]_6\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \my_empty_reg[7]_7\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \my_empty_reg[7]_8\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \my_empty_reg[7]_9\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \my_empty_reg[7]_10\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \my_empty_reg[7]_11\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \my_empty_reg[7]_12\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \my_empty_reg[7]_13\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \input_[9].iserdes_dq_.iserdesdq_1\ : in STD_LOGIC;
    LD0_12 : in STD_LOGIC;
    CLKB0_12 : in STD_LOGIC;
    \pi_dqs_found_lanes_r1_reg[10]\ : in STD_LOGIC;
    \pi_dqs_found_lanes_r1_reg[10]_0\ : in STD_LOGIC;
    \pi_dqs_found_lanes_r1_reg[10]_1\ : in STD_LOGIC;
    \pi_dqs_found_lanes_r1_reg[10]_2\ : in STD_LOGIC;
    ififo_rst_reg_1 : in STD_LOGIC;
    \pi_dqs_found_lanes_r1_reg[10]_3\ : in STD_LOGIC_VECTOR ( 5 downto 0 );
    \po_counter_read_val_reg[8]_6\ : in STD_LOGIC;
    \po_counter_read_val_reg[8]_7\ : in STD_LOGIC;
    \po_counter_read_val_reg[8]_8\ : in STD_LOGIC;
    \my_empty_reg[7]_14\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \my_empty_reg[7]_15\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \my_empty_reg[7]_16\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \my_empty_reg[7]_17\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \my_empty_reg[7]_18\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \my_empty_reg[7]_19\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \my_empty_reg[7]_20\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \my_empty_reg[7]_21\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \input_[9].iserdes_dq_.iserdesdq_2\ : in STD_LOGIC;
    LD0_13 : in STD_LOGIC;
    CLKB0_13 : in STD_LOGIC;
    \pi_dqs_found_lanes_r1_reg[11]\ : in STD_LOGIC;
    \pi_dqs_found_lanes_r1_reg[11]_0\ : in STD_LOGIC;
    \pi_dqs_found_lanes_r1_reg[11]_1\ : in STD_LOGIC;
    \pi_dqs_found_lanes_r1_reg[11]_2\ : in STD_LOGIC;
    ififo_rst_reg_2 : in STD_LOGIC;
    \pi_dqs_found_lanes_r1_reg[11]_3\ : in STD_LOGIC_VECTOR ( 5 downto 0 );
    \po_counter_read_val_reg[8]_9\ : in STD_LOGIC;
    \po_counter_read_val_reg[8]_10\ : in STD_LOGIC;
    \po_counter_read_val_reg[8]_11\ : in STD_LOGIC;
    \my_empty_reg[7]_22\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \my_empty_reg[7]_23\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \my_empty_reg[7]_24\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \my_empty_reg[7]_25\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \my_empty_reg[7]_26\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \my_empty_reg[7]_27\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \my_empty_reg[7]_28\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \my_empty_reg[7]_29\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    phy_ctl_mstr_empty : in STD_LOGIC;
    phy_ctl_wr_i2 : in STD_LOGIC;
    pll_locked : in STD_LOGIC;
    phy_read_calib : in STD_LOGIC;
    phy_mc_ctl_full_r_reg : in STD_LOGIC;
    phy_write_calib : in STD_LOGIC;
    PHYCTLWD : in STD_LOGIC_VECTOR ( 10 downto 0 );
    RST0 : in STD_LOGIC;
    rst_primitives_reg_0 : in STD_LOGIC;
    rst_out_reg_1 : in STD_LOGIC;
    SR : in STD_LOGIC_VECTOR ( 0 to 0 );
    \rclk_delay_reg[11]_0\ : in STD_LOGIC;
    phy_data_wr_en : in STD_LOGIC;
    \gen_mux_rd[0].mux_rd_rise0_r_reg[0]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \gen_mux_rd[0].mux_rd_rise0_r_reg[0]_0\ : in STD_LOGIC;
    \gen_mux_rd[1].mux_rd_rise0_r_reg[1]\ : in STD_LOGIC;
    \gen_mux_rd[2].mux_rd_rise0_r_reg[2]\ : in STD_LOGIC;
    \gen_mux_rd[3].mux_rd_rise0_r_reg[3]\ : in STD_LOGIC;
    \gen_mux_rd[4].mux_rd_rise0_r_reg[4]\ : in STD_LOGIC;
    \gen_mux_rd[5].mux_rd_rise0_r_reg[5]\ : in STD_LOGIC;
    \gen_mux_rd[6].mux_rd_rise0_r_reg[6]\ : in STD_LOGIC;
    \gen_mux_rd[7].mux_rd_rise0_r_reg[7]\ : in STD_LOGIC;
    \gen_mux_rd[0].mux_rd_fall0_r_reg[0]\ : in STD_LOGIC;
    \gen_mux_rd[1].mux_rd_fall0_r_reg[1]\ : in STD_LOGIC;
    \gen_mux_rd[2].mux_rd_fall0_r_reg[2]\ : in STD_LOGIC;
    \gen_mux_rd[3].mux_rd_fall0_r_reg[3]\ : in STD_LOGIC;
    \gen_mux_rd[4].mux_rd_fall0_r_reg[4]\ : in STD_LOGIC;
    \gen_mux_rd[5].mux_rd_fall0_r_reg[5]\ : in STD_LOGIC;
    \gen_mux_rd[6].mux_rd_fall0_r_reg[6]\ : in STD_LOGIC;
    \gen_mux_rd[7].mux_rd_fall0_r_reg[7]\ : in STD_LOGIC;
    \gen_mux_rd[0].mux_rd_rise1_r_reg[0]\ : in STD_LOGIC;
    \gen_mux_rd[1].mux_rd_rise1_r_reg[1]\ : in STD_LOGIC;
    \gen_mux_rd[2].mux_rd_rise1_r_reg[2]\ : in STD_LOGIC;
    \gen_mux_rd[3].mux_rd_rise1_r_reg[3]\ : in STD_LOGIC;
    \gen_mux_rd[4].mux_rd_rise1_r_reg[4]\ : in STD_LOGIC;
    \gen_mux_rd[5].mux_rd_rise1_r_reg[5]\ : in STD_LOGIC;
    \gen_mux_rd[6].mux_rd_rise1_r_reg[6]\ : in STD_LOGIC;
    \gen_mux_rd[7].mux_rd_rise1_r_reg[7]\ : in STD_LOGIC;
    \gen_mux_rd[0].mux_rd_fall1_r_reg[0]\ : in STD_LOGIC;
    \gen_mux_rd[1].mux_rd_fall1_r_reg[1]\ : in STD_LOGIC;
    \gen_mux_rd[2].mux_rd_fall1_r_reg[2]\ : in STD_LOGIC;
    \gen_mux_rd[3].mux_rd_fall1_r_reg[3]\ : in STD_LOGIC;
    \gen_mux_rd[4].mux_rd_fall1_r_reg[4]\ : in STD_LOGIC;
    \gen_mux_rd[5].mux_rd_fall1_r_reg[5]\ : in STD_LOGIC;
    \gen_mux_rd[6].mux_rd_fall1_r_reg[6]\ : in STD_LOGIC;
    \gen_mux_rd[7].mux_rd_fall1_r_reg[7]\ : in STD_LOGIC;
    \gen_mux_rd[0].mux_rd_rise2_r_reg[0]\ : in STD_LOGIC;
    \gen_mux_rd[1].mux_rd_rise2_r_reg[1]\ : in STD_LOGIC;
    \gen_mux_rd[2].mux_rd_rise2_r_reg[2]\ : in STD_LOGIC;
    \gen_mux_rd[3].mux_rd_rise2_r_reg[3]\ : in STD_LOGIC;
    \gen_mux_rd[4].mux_rd_rise2_r_reg[4]\ : in STD_LOGIC;
    \gen_mux_rd[5].mux_rd_rise2_r_reg[5]\ : in STD_LOGIC;
    \gen_mux_rd[6].mux_rd_rise2_r_reg[6]\ : in STD_LOGIC;
    \gen_mux_rd[7].mux_rd_rise2_r_reg[7]\ : in STD_LOGIC;
    \gen_mux_rd[0].mux_rd_fall2_r_reg[0]\ : in STD_LOGIC;
    \gen_mux_rd[1].mux_rd_fall2_r_reg[1]\ : in STD_LOGIC;
    \gen_mux_rd[2].mux_rd_fall2_r_reg[2]\ : in STD_LOGIC;
    \gen_mux_rd[3].mux_rd_fall2_r_reg[3]\ : in STD_LOGIC;
    \gen_mux_rd[4].mux_rd_fall2_r_reg[4]\ : in STD_LOGIC;
    \gen_mux_rd[5].mux_rd_fall2_r_reg[5]\ : in STD_LOGIC;
    \gen_mux_rd[6].mux_rd_fall2_r_reg[6]\ : in STD_LOGIC;
    \gen_mux_rd[7].mux_rd_fall2_r_reg[7]\ : in STD_LOGIC;
    \gen_mux_rd[0].mux_rd_rise3_r_reg[0]\ : in STD_LOGIC;
    \gen_mux_rd[1].mux_rd_rise3_r_reg[1]\ : in STD_LOGIC;
    \gen_mux_rd[2].mux_rd_rise3_r_reg[2]\ : in STD_LOGIC;
    \gen_mux_rd[3].mux_rd_rise3_r_reg[3]\ : in STD_LOGIC;
    \gen_mux_rd[4].mux_rd_rise3_r_reg[4]\ : in STD_LOGIC;
    \gen_mux_rd[5].mux_rd_rise3_r_reg[5]\ : in STD_LOGIC;
    \gen_mux_rd[6].mux_rd_rise3_r_reg[6]\ : in STD_LOGIC;
    \gen_mux_rd[7].mux_rd_rise3_r_reg[7]\ : in STD_LOGIC;
    \gen_mux_rd[0].mux_rd_fall3_r_reg[0]\ : in STD_LOGIC;
    \gen_mux_rd[1].mux_rd_fall3_r_reg[1]\ : in STD_LOGIC;
    \gen_mux_rd[2].mux_rd_fall3_r_reg[2]\ : in STD_LOGIC;
    \gen_mux_rd[3].mux_rd_fall3_r_reg[3]\ : in STD_LOGIC;
    \gen_mux_rd[4].mux_rd_fall3_r_reg[4]\ : in STD_LOGIC;
    \gen_mux_rd[5].mux_rd_fall3_r_reg[5]\ : in STD_LOGIC;
    \gen_mux_rd[6].mux_rd_fall3_r_reg[6]\ : in STD_LOGIC;
    \gen_mux_rd[7].mux_rd_fall3_r_reg[7]\ : in STD_LOGIC;
    out_fifo : in STD_LOGIC;
    out_fifo_0 : in STD_LOGIC_VECTOR ( 31 downto 0 );
    out_fifo_1 : in STD_LOGIC;
    \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
    \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]_0\ : in STD_LOGIC;
    \gen_mux_rd[1].mux_rd_rise0_r1_reg[1]\ : in STD_LOGIC;
    \gen_mux_rd[2].mux_rd_rise0_r1_reg[2]\ : in STD_LOGIC;
    \gen_mux_rd[3].mux_rd_rise0_r1_reg[3]\ : in STD_LOGIC;
    \gen_mux_rd[4].mux_rd_rise0_r1_reg[4]\ : in STD_LOGIC;
    \gen_mux_rd[5].mux_rd_rise0_r1_reg[5]\ : in STD_LOGIC;
    \gen_mux_rd[6].mux_rd_rise0_r1_reg[6]\ : in STD_LOGIC;
    \gen_mux_rd[7].mux_rd_rise0_r1_reg[7]\ : in STD_LOGIC;
    \gen_mux_rd[0].mux_rd_fall0_r1_reg[0]\ : in STD_LOGIC;
    \gen_mux_rd[1].mux_rd_fall0_r1_reg[1]\ : in STD_LOGIC;
    \gen_mux_rd[2].mux_rd_fall0_r1_reg[2]\ : in STD_LOGIC;
    \gen_mux_rd[3].mux_rd_fall0_r1_reg[3]\ : in STD_LOGIC;
    \gen_mux_rd[4].mux_rd_fall0_r1_reg[4]\ : in STD_LOGIC;
    \gen_mux_rd[5].mux_rd_fall0_r1_reg[5]\ : in STD_LOGIC;
    \gen_mux_rd[6].mux_rd_fall0_r1_reg[6]\ : in STD_LOGIC;
    \gen_mux_rd[7].mux_rd_fall0_r1_reg[7]\ : in STD_LOGIC;
    \gen_mux_rd[0].mux_rd_rise1_r1_reg[0]\ : in STD_LOGIC;
    \gen_mux_rd[1].mux_rd_rise1_r1_reg[1]\ : in STD_LOGIC;
    \gen_mux_rd[2].mux_rd_rise1_r1_reg[2]\ : in STD_LOGIC;
    \gen_mux_rd[3].mux_rd_rise1_r1_reg[3]\ : in STD_LOGIC;
    \gen_mux_rd[4].mux_rd_rise1_r1_reg[4]\ : in STD_LOGIC;
    \gen_mux_rd[5].mux_rd_rise1_r1_reg[5]\ : in STD_LOGIC;
    \gen_mux_rd[6].mux_rd_rise1_r1_reg[6]\ : in STD_LOGIC;
    \gen_mux_rd[7].mux_rd_rise1_r1_reg[7]\ : in STD_LOGIC;
    \gen_mux_rd[0].mux_rd_fall1_r1_reg[0]\ : in STD_LOGIC;
    \gen_mux_rd[1].mux_rd_fall1_r1_reg[1]\ : in STD_LOGIC;
    \gen_mux_rd[2].mux_rd_fall1_r1_reg[2]\ : in STD_LOGIC;
    \gen_mux_rd[3].mux_rd_fall1_r1_reg[3]\ : in STD_LOGIC;
    \gen_mux_rd[4].mux_rd_fall1_r1_reg[4]\ : in STD_LOGIC;
    \gen_mux_rd[5].mux_rd_fall1_r1_reg[5]\ : in STD_LOGIC;
    \gen_mux_rd[6].mux_rd_fall1_r1_reg[6]\ : in STD_LOGIC;
    \gen_mux_rd[7].mux_rd_fall1_r1_reg[7]\ : in STD_LOGIC;
    \gen_mux_rd[0].mux_rd_rise2_r1_reg[0]\ : in STD_LOGIC;
    \gen_mux_rd[1].mux_rd_rise2_r1_reg[1]\ : in STD_LOGIC;
    \gen_mux_rd[2].mux_rd_rise2_r1_reg[2]\ : in STD_LOGIC;
    \gen_mux_rd[3].mux_rd_rise2_r1_reg[3]\ : in STD_LOGIC;
    \gen_mux_rd[4].mux_rd_rise2_r1_reg[4]\ : in STD_LOGIC;
    \gen_mux_rd[5].mux_rd_rise2_r1_reg[5]\ : in STD_LOGIC;
    \gen_mux_rd[6].mux_rd_rise2_r1_reg[6]\ : in STD_LOGIC;
    \gen_mux_rd[7].mux_rd_rise2_r1_reg[7]\ : in STD_LOGIC;
    \gen_mux_rd[0].mux_rd_fall2_r1_reg[0]\ : in STD_LOGIC;
    \gen_mux_rd[1].mux_rd_fall2_r1_reg[1]\ : in STD_LOGIC;
    \gen_mux_rd[2].mux_rd_fall2_r1_reg[2]\ : in STD_LOGIC;
    \gen_mux_rd[3].mux_rd_fall2_r1_reg[3]\ : in STD_LOGIC;
    \gen_mux_rd[4].mux_rd_fall2_r1_reg[4]\ : in STD_LOGIC;
    \gen_mux_rd[5].mux_rd_fall2_r1_reg[5]\ : in STD_LOGIC;
    \gen_mux_rd[6].mux_rd_fall2_r1_reg[6]\ : in STD_LOGIC;
    \gen_mux_rd[7].mux_rd_fall2_r1_reg[7]\ : in STD_LOGIC;
    \gen_mux_rd[0].mux_rd_rise3_r1_reg[0]\ : in STD_LOGIC;
    \gen_mux_rd[1].mux_rd_rise3_r1_reg[1]\ : in STD_LOGIC;
    \gen_mux_rd[2].mux_rd_rise3_r1_reg[2]\ : in STD_LOGIC;
    \gen_mux_rd[3].mux_rd_rise3_r1_reg[3]\ : in STD_LOGIC;
    \gen_mux_rd[4].mux_rd_rise3_r1_reg[4]\ : in STD_LOGIC;
    \gen_mux_rd[5].mux_rd_rise3_r1_reg[5]\ : in STD_LOGIC;
    \gen_mux_rd[6].mux_rd_rise3_r1_reg[6]\ : in STD_LOGIC;
    \gen_mux_rd[7].mux_rd_rise3_r1_reg[7]\ : in STD_LOGIC;
    \gen_mux_rd[0].mux_rd_fall3_r1_reg[0]\ : in STD_LOGIC;
    \gen_mux_rd[1].mux_rd_fall3_r1_reg[1]\ : in STD_LOGIC;
    \gen_mux_rd[2].mux_rd_fall3_r1_reg[2]\ : in STD_LOGIC;
    \gen_mux_rd[3].mux_rd_fall3_r1_reg[3]\ : in STD_LOGIC;
    \gen_mux_rd[4].mux_rd_fall3_r1_reg[4]\ : in STD_LOGIC;
    \gen_mux_rd[5].mux_rd_fall3_r1_reg[5]\ : in STD_LOGIC;
    \gen_mux_rd[6].mux_rd_fall3_r1_reg[6]\ : in STD_LOGIC;
    \gen_mux_rd[7].mux_rd_fall3_r1_reg[7]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg[1]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg[2]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg[3]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg[4]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg[5]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg[6]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg[7]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg[0]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg[1]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg[2]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg[3]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg[4]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg[5]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg[6]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg[0]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg[1]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg[2]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg[3]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg[4]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg[5]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg[6]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg[7]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise2_r_reg[0]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg[1]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg[2]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg[3]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise2_r_reg[4]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg[5]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg[6]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg[7]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg[0]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg[1]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg[2]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg[3]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg[4]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg[5]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg[6]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg[7]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg[0]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg[1]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg[2]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise3_r_reg[3]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg[4]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg[5]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg[6]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise3_r_reg[7]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg[0]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg[1]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg[2]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg[3]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg[4]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg[5]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg[6]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg[7]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg[0]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg[1]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg[2]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg[3]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg[4]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg[5]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg[6]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg[7]\ : in STD_LOGIC;
    \out_fifo_i_75__0\ : in STD_LOGIC_VECTOR ( 71 downto 0 );
    \out_fifo_i_75__1\ : in STD_LOGIC_VECTOR ( 71 downto 0 );
    \out_fifo_i_75__2\ : in STD_LOGIC_VECTOR ( 71 downto 0 );
    \out_fifo_i_75__3\ : in STD_LOGIC_VECTOR ( 71 downto 0 );
    \my_full_reg[1]\ : in STD_LOGIC;
    \my_full_reg[1]_0\ : in STD_LOGIC;
    calib_sel : in STD_LOGIC_VECTOR ( 1 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of mig_mig_7series_v4_2_ddr_phy_4lanes_13 : entity is "mig_7series_v4_2_ddr_phy_4lanes";
end mig_mig_7series_v4_2_ddr_phy_4lanes_13;

architecture STRUCTURE of mig_mig_7series_v4_2_ddr_phy_4lanes_13 is
  signal A_pi_counter_read_val : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal A_pi_rst_div2 : STD_LOGIC;
  attribute async_reg : string;
  attribute async_reg of A_pi_rst_div2 : signal is "true";
  signal A_po_counter_read_val : STD_LOGIC_VECTOR ( 8 downto 0 );
  signal A_rst_primitives : STD_LOGIC;
  signal B_pi_rst_div2 : STD_LOGIC;
  attribute async_reg of B_pi_rst_div2 : signal is "true";
  signal B_rclk : STD_LOGIC;
  signal C_pi_counter_read_val : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal C_pi_rst_div2 : STD_LOGIC;
  attribute async_reg of C_pi_rst_div2 : signal is "true";
  signal C_po_counter_read_val : STD_LOGIC_VECTOR ( 8 downto 0 );
  signal D_pi_counter_read_val : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal D_pi_rst_div2 : STD_LOGIC;
  attribute async_reg of D_pi_rst_div2 : signal is "true";
  signal D_po_counter_read_val : STD_LOGIC_VECTOR ( 8 downto 0 );
  signal \ddr_byte_lane_A.ddr_byte_lane_A_n_22\ : STD_LOGIC;
  signal \ddr_byte_lane_B.ddr_byte_lane_B_n_157\ : STD_LOGIC;
  signal \ddr_byte_lane_B.ddr_byte_lane_B_n_22\ : STD_LOGIC;
  signal \ddr_byte_lane_B.ddr_byte_lane_B_n_222\ : STD_LOGIC;
  signal \ddr_byte_lane_B.ddr_byte_lane_B_n_223\ : STD_LOGIC;
  signal \ddr_byte_lane_B.ddr_byte_lane_B_n_224\ : STD_LOGIC;
  signal \ddr_byte_lane_B.ddr_byte_lane_B_n_225\ : STD_LOGIC;
  signal \ddr_byte_lane_B.ddr_byte_lane_B_n_226\ : STD_LOGIC;
  signal \ddr_byte_lane_B.ddr_byte_lane_B_n_227\ : STD_LOGIC;
  signal \ddr_byte_lane_B.ddr_byte_lane_B_n_228\ : STD_LOGIC;
  signal \ddr_byte_lane_B.ddr_byte_lane_B_n_229\ : STD_LOGIC;
  signal \ddr_byte_lane_B.ddr_byte_lane_B_n_230\ : STD_LOGIC;
  signal \ddr_byte_lane_B.ddr_byte_lane_B_n_231\ : STD_LOGIC;
  signal \ddr_byte_lane_B.ddr_byte_lane_B_n_232\ : STD_LOGIC;
  signal \ddr_byte_lane_B.ddr_byte_lane_B_n_233\ : STD_LOGIC;
  signal \ddr_byte_lane_B.ddr_byte_lane_B_n_234\ : STD_LOGIC;
  signal \ddr_byte_lane_B.ddr_byte_lane_B_n_235\ : STD_LOGIC;
  signal \ddr_byte_lane_B.ddr_byte_lane_B_n_236\ : STD_LOGIC;
  signal \ddr_byte_lane_C.ddr_byte_lane_C_n_106\ : STD_LOGIC;
  signal \ddr_byte_lane_C.ddr_byte_lane_C_n_107\ : STD_LOGIC;
  signal \ddr_byte_lane_C.ddr_byte_lane_C_n_22\ : STD_LOGIC;
  signal \ddr_byte_lane_C.ddr_byte_lane_C_n_41\ : STD_LOGIC;
  signal \ddr_byte_lane_D.ddr_byte_lane_D_n_233\ : STD_LOGIC;
  signal \ddr_byte_lane_D.ddr_byte_lane_D_n_235\ : STD_LOGIC;
  signal \ddr_byte_lane_D.ddr_byte_lane_D_n_236\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_0\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_1\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_0\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_1\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_0\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_1\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_0\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_1\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_0\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_1\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_0\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_1\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_0\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_1\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_0\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_1\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_1\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_0\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_1\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_0\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_1\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_0\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_1\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_0\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_1\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_0\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_1\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_0\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_1\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_0\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_1\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_0\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_1\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_0\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_1\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_0\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_1\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_0\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_1\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_0\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_1\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_0\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_1\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_0\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_1\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_0\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_1\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_1\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_0\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_1\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_0\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_1\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_0\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_1\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_0\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_1\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_0\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_1\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_0\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_1\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_0\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_1\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_0\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_1\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_0\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_1\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_0\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_1\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_0\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_1\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_0\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_1\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_0\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_1\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_0\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_1\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_0\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_1\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_1\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_0\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_1\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_0\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_1\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_0\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_1\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_0\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_1\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_0\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_1\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_0\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_1\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_0\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_1\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_0\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_0\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_0\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_0\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_0\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_0\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_0\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_0\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_0\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_1\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_0\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_1\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_0\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_1\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_0\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_1\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_0\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_1\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_0\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_1\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_0\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_1\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_1\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]\ : STD_LOGIC;
  signal \dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/my_empty\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/my_empty_1\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal if_empty_r : STD_LOGIC_VECTOR ( 3 to 3 );
  signal if_empty_r_2 : STD_LOGIC_VECTOR ( 3 to 3 );
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo/entry_cnt_reg\ : STD_LOGIC_VECTOR ( 4 downto 2 );
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo/entry_cnt_reg_0\ : STD_LOGIC_VECTOR ( 4 downto 2 );
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo/entry_cnt_reg_3\ : STD_LOGIC_VECTOR ( 4 downto 2 );
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo/entry_cnt_reg_4\ : STD_LOGIC_VECTOR ( 4 downto 2 );
  signal phaser_ctl_bus : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal phy_control_i_n_0 : STD_LOGIC;
  signal phy_control_i_n_1 : STD_LOGIC;
  signal phy_control_i_n_14 : STD_LOGIC;
  signal phy_control_i_n_15 : STD_LOGIC;
  signal phy_control_i_n_16 : STD_LOGIC;
  signal phy_control_i_n_17 : STD_LOGIC;
  signal phy_encalib : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \rclk_delay_reg[10]_srl11_n_0\ : STD_LOGIC;
  signal \^ref_dll_lock_w__0\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \^rst_out_reg_0\ : STD_LOGIC;
  signal \^rst_primitives\ : STD_LOGIC;
  signal rst_r4 : STD_LOGIC;
  attribute BOX_TYPE : string;
  attribute BOX_TYPE of phaser_ref_i : label is "PRIMITIVE";
  attribute BOX_TYPE of phy_control_i : label is "PRIMITIVE";
  attribute srl_bus_name : string;
  attribute srl_bus_name of \rclk_delay_reg[10]_srl11\ : label is "\u_mig_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/rclk_delay_reg ";
  attribute srl_name : string;
  attribute srl_name of \rclk_delay_reg[10]_srl11\ : label is "\u_mig_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/rclk_delay_reg[10]_srl11 ";
begin
  \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0\ <= \^dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0\;
  \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1\ <= \^dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_0\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_0\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_1\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_1\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_0\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_0\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_1\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_1\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_0\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_0\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_1\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_1\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_0\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_0\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_1\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_1\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_0\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_0\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_1\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_1\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_0\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_0\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_1\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_1\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_0\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_0\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_1\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_1\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_0\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_0\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_1\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_1\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_1\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_1\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_0\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_0\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_1\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_1\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_0\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_0\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_1\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_1\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_0\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_0\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_1\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_1\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_0\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_0\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_1\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_1\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_0\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_0\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_1\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_1\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_0\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_0\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_1\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_1\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_0\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_0\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_1\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_1\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_0\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_0\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_1\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_1\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_0\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_0\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_1\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_1\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_0\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_0\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_1\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_1\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_0\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_0\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_1\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_1\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_0\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_0\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_1\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_1\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_0\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_0\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_1\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_1\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_0\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_0\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_1\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_1\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_0\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_0\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_1\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_1\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_1\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_1\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_0\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_0\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_1\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_1\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_0\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_0\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_1\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_1\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_0\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_0\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_1\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_1\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_0\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_0\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_1\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_1\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_0\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_0\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_1\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_1\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_0\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_0\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_1\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_1\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_0\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_0\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_1\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_1\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_0\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_0\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_1\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_1\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_0\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_0\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_1\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_1\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_0\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_0\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_1\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_1\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_0\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_0\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_1\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_1\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_0\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_0\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_1\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_1\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_0\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_0\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_1\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_1\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_0\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_0\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_1\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_1\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_0\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_0\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_1\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_1\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_1\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_1\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_0\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_0\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_1\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_1\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_0\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_0\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_1\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_1\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_0\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_0\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_1\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_1\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_0\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_0\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_1\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_1\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_0\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_0\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_1\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_1\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_0\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_0\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_1\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_1\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_0\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_0\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_1\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_1\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_0\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_0\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_0\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_0\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_0\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_0\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_0\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_0\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_0\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_0\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_0\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_0\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_0\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_0\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_0\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_0\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_0\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_0\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_1\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_1\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_0\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_0\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_1\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_1\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_0\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_0\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_1\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_1\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_0\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_0\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_1\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_1\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_0\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_0\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_1\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_1\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_0\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_0\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_1\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_1\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_0\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_0\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_1\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_1\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_1\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_1\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]\;
  \ref_dll_lock_w__0\(0) <= \^ref_dll_lock_w__0\(0);
  rst_out_reg_0 <= \^rst_out_reg_0\;
  rst_primitives <= \^rst_primitives\;
A_rst_primitives_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \entry_cnt_reg[4]_1\,
      CE => '1',
      D => \^rst_primitives\,
      Q => A_rst_primitives,
      R => '0'
    );
\ddr_byte_lane_A.ddr_byte_lane_A\: entity work.mig_mig_7series_v4_2_ddr_byte_lane
     port map (
      A_rst_primitives => A_rst_primitives,
      A_rst_primitives_reg => A_rst_primitives_reg_0,
      A_rst_primitives_reg_0 => \ddr_byte_lane_A.ddr_byte_lane_A_n_22\,
      A_rst_primitives_reg_1(8 downto 0) => A_po_counter_read_val(8 downto 0),
      CLKB0_10 => CLKB0_10,
      COUNTERREADVAL(5 downto 0) => A_pi_counter_read_val(5 downto 0),
      D2(7 downto 0) => D2(7 downto 0),
      LD0_10 => LD0_10,
      PCENABLECALIB(1 downto 0) => phy_encalib(1 downto 0),
      Q(2 downto 0) => \of_pre_fifo_gen.u_ddr_of_pre_fifo/entry_cnt_reg\(4 downto 2),
      \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0\ => \^dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]\,
      freq_refclk => freq_refclk,
      idelay_inc => idelay_inc,
      idelay_ld_rst_3 => idelay_ld_rst_3,
      if_empty_r(0) => if_empty_r(3),
      ififo_rst_reg_0 => ififo_rst_reg,
      in0(0) => in0(0),
      \input_[9].iserdes_dq_.iserdesdq\ => \input_[9].iserdes_dq_.iserdesdq\,
      mem_dq_in(7 downto 0) => mem_dq_in(7 downto 0),
      mem_dq_out(8 downto 0) => mem_dq_out(8 downto 0),
      mem_dq_ts(8 downto 0) => mem_dq_ts(8 downto 0),
      mem_dqs_in(0) => mem_dqs_in(0),
      mem_refclk => mem_refclk,
      \my_empty_reg[1]\ => \my_empty_reg[1]\,
      \my_empty_reg[4]\(0) => \dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/my_empty\(0),
      \my_empty_reg[7]\(7 downto 0) => \my_empty_reg[7]\(7 downto 0),
      \my_empty_reg[7]_0\(7 downto 0) => \my_empty_reg[7]_0\(7 downto 0),
      \my_empty_reg[7]_1\(7 downto 0) => \my_empty_reg[7]_1\(7 downto 0),
      \my_empty_reg[7]_2\(7 downto 0) => \my_empty_reg[7]_2\(7 downto 0),
      \my_empty_reg[7]_3\(7 downto 0) => \my_empty_reg[7]_3\(7 downto 0),
      \my_empty_reg[7]_4\(7 downto 0) => \my_empty_reg[7]_4\(7 downto 0),
      \my_empty_reg[7]_5\(7 downto 0) => \my_empty_reg[7]_5\(7 downto 0),
      \my_full_reg[1]\ => \ddr_byte_lane_D.ddr_byte_lane_D_n_233\,
      out_dqs_0 => out_dqs_0,
      out_fifo_0 => out_fifo,
      out_fifo_1(7) => out_fifo_0(28),
      out_fifo_1(6) => out_fifo_0(24),
      out_fifo_1(5) => out_fifo_0(20),
      out_fifo_1(4) => out_fifo_0(16),
      out_fifo_1(3) => out_fifo_0(12),
      out_fifo_1(2) => out_fifo_0(8),
      out_fifo_1(1) => out_fifo_0(4),
      out_fifo_1(0) => out_fifo_0(0),
      out_fifo_2 => out_fifo_1,
      \out_fifo_i_75__0\(71 downto 0) => \out_fifo_i_75__0\(71 downto 0),
      phaser_ctl_bus(3 downto 2) => phaser_ctl_bus(9 downto 8),
      phaser_ctl_bus(1) => phaser_ctl_bus(4),
      phaser_ctl_bus(0) => phaser_ctl_bus(0),
      phy_data_wr_en => phy_data_wr_en,
      phy_if_reset => phy_if_reset,
      \pi_dqs_found_lanes_r1_reg[8]\ => \pi_dqs_found_lanes_r1_reg[8]\,
      \pi_dqs_found_lanes_r1_reg[8]_0\ => \pi_dqs_found_lanes_r1_reg[8]_0\,
      \pi_dqs_found_lanes_r1_reg[8]_1\ => \pi_dqs_found_lanes_r1_reg[8]_1\,
      \pi_dqs_found_lanes_r1_reg[8]_2\ => \pi_dqs_found_lanes_r1_reg[8]_2\,
      \pi_dqs_found_lanes_r1_reg[8]_3\(5 downto 0) => \pi_dqs_found_lanes_r1_reg[8]_3\(5 downto 0),
      \po_counter_read_val_reg[8]\ => \po_counter_read_val_reg[8]_0\,
      \po_counter_read_val_reg[8]_0\ => \po_counter_read_val_reg[8]_1\,
      \po_counter_read_val_reg[8]_1\ => \po_counter_read_val_reg[8]_2\,
      \rd_ptr_reg[3]\(63 downto 0) => \rd_ptr_reg[3]\(63 downto 0),
      rst_r4 => rst_r4,
      sync_pulse => sync_pulse,
      ts_dqs_0 => ts_dqs_0,
      \wr_ptr_timing_reg[3]\ => \entry_cnt_reg[4]_1\
    );
\ddr_byte_lane_B.ddr_byte_lane_B\: entity work.\mig_mig_7series_v4_2_ddr_byte_lane__parameterized0\
     port map (
      A_rst_primitives => A_rst_primitives,
      A_rst_primitives_reg => A_rst_primitives_reg_1,
      A_rst_primitives_reg_0 => \ddr_byte_lane_B.ddr_byte_lane_B_n_22\,
      B_rclk => B_rclk,
      CLKB0_11 => CLKB0_11,
      COUNTERREADVAL(5 downto 0) => A_pi_counter_read_val(5 downto 0),
      D(5) => \ddr_byte_lane_B.ddr_byte_lane_B_n_222\,
      D(4) => \ddr_byte_lane_B.ddr_byte_lane_B_n_223\,
      D(3) => \ddr_byte_lane_B.ddr_byte_lane_B_n_224\,
      D(2) => \ddr_byte_lane_B.ddr_byte_lane_B_n_225\,
      D(1) => \ddr_byte_lane_B.ddr_byte_lane_B_n_226\,
      D(0) => \ddr_byte_lane_B.ddr_byte_lane_B_n_227\,
      LD0_11 => LD0_11,
      PCENABLECALIB(1 downto 0) => phy_encalib(1 downto 0),
      Q(2 downto 0) => \of_pre_fifo_gen.u_ddr_of_pre_fifo/entry_cnt_reg_0\(4 downto 2),
      calib_sel(1 downto 0) => calib_sel(1 downto 0),
      \calib_sel_reg[1]\(8) => \ddr_byte_lane_B.ddr_byte_lane_B_n_228\,
      \calib_sel_reg[1]\(7) => \ddr_byte_lane_B.ddr_byte_lane_B_n_229\,
      \calib_sel_reg[1]\(6) => \ddr_byte_lane_B.ddr_byte_lane_B_n_230\,
      \calib_sel_reg[1]\(5) => \ddr_byte_lane_B.ddr_byte_lane_B_n_231\,
      \calib_sel_reg[1]\(4) => \ddr_byte_lane_B.ddr_byte_lane_B_n_232\,
      \calib_sel_reg[1]\(3) => \ddr_byte_lane_B.ddr_byte_lane_B_n_233\,
      \calib_sel_reg[1]\(2) => \ddr_byte_lane_B.ddr_byte_lane_B_n_234\,
      \calib_sel_reg[1]\(1) => \ddr_byte_lane_B.ddr_byte_lane_B_n_235\,
      \calib_sel_reg[1]\(0) => \ddr_byte_lane_B.ddr_byte_lane_B_n_236\,
      \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0\ => \ddr_byte_lane_B.ddr_byte_lane_B_n_157\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]\,
      \entry_cnt_reg[4]\ => \entry_cnt_reg[4]_1\,
      freq_refclk => freq_refclk,
      \gen_mux_rd[0].mux_rd_fall0_r_reg[0]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_0\,
      \gen_mux_rd[0].mux_rd_fall0_r_reg[0]_0\ => \gen_mux_rd[0].mux_rd_fall0_r_reg[0]\,
      \gen_mux_rd[0].mux_rd_fall0_r_reg[0]_1\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]\,
      \gen_mux_rd[0].mux_rd_fall1_r_reg[0]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_0\,
      \gen_mux_rd[0].mux_rd_fall1_r_reg[0]_0\ => \gen_mux_rd[0].mux_rd_fall1_r_reg[0]\,
      \gen_mux_rd[0].mux_rd_fall1_r_reg[0]_1\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]\,
      \gen_mux_rd[0].mux_rd_fall2_r_reg[0]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_0\,
      \gen_mux_rd[0].mux_rd_fall2_r_reg[0]_0\ => \gen_mux_rd[0].mux_rd_fall2_r_reg[0]\,
      \gen_mux_rd[0].mux_rd_fall2_r_reg[0]_1\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]\,
      \gen_mux_rd[0].mux_rd_fall3_r_reg[0]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_0\,
      \gen_mux_rd[0].mux_rd_fall3_r_reg[0]_0\ => \gen_mux_rd[0].mux_rd_fall3_r_reg[0]\,
      \gen_mux_rd[0].mux_rd_fall3_r_reg[0]_1\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]\,
      \gen_mux_rd[0].mux_rd_rise0_r_reg[0]\(1 downto 0) => \gen_mux_rd[0].mux_rd_rise0_r_reg[0]\(1 downto 0),
      \gen_mux_rd[0].mux_rd_rise0_r_reg[0]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_0\,
      \gen_mux_rd[0].mux_rd_rise0_r_reg[0]_1\ => \gen_mux_rd[0].mux_rd_rise0_r_reg[0]_0\,
      \gen_mux_rd[0].mux_rd_rise0_r_reg[0]_2\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]\,
      \gen_mux_rd[0].mux_rd_rise1_r_reg[0]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_0\,
      \gen_mux_rd[0].mux_rd_rise1_r_reg[0]_0\ => \gen_mux_rd[0].mux_rd_rise1_r_reg[0]\,
      \gen_mux_rd[0].mux_rd_rise1_r_reg[0]_1\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]\,
      \gen_mux_rd[0].mux_rd_rise2_r_reg[0]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_0\,
      \gen_mux_rd[0].mux_rd_rise2_r_reg[0]_0\ => \gen_mux_rd[0].mux_rd_rise2_r_reg[0]\,
      \gen_mux_rd[0].mux_rd_rise2_r_reg[0]_1\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]\,
      \gen_mux_rd[0].mux_rd_rise3_r_reg[0]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_0\,
      \gen_mux_rd[0].mux_rd_rise3_r_reg[0]_0\ => \gen_mux_rd[0].mux_rd_rise3_r_reg[0]\,
      \gen_mux_rd[0].mux_rd_rise3_r_reg[0]_1\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]\,
      \gen_mux_rd[1].mux_rd_fall0_r_reg[1]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_0\,
      \gen_mux_rd[1].mux_rd_fall0_r_reg[1]_0\ => \gen_mux_rd[1].mux_rd_fall0_r_reg[1]\,
      \gen_mux_rd[1].mux_rd_fall0_r_reg[1]_1\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_1\,
      \gen_mux_rd[1].mux_rd_fall1_r_reg[1]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_0\,
      \gen_mux_rd[1].mux_rd_fall1_r_reg[1]_0\ => \gen_mux_rd[1].mux_rd_fall1_r_reg[1]\,
      \gen_mux_rd[1].mux_rd_fall1_r_reg[1]_1\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_1\,
      \gen_mux_rd[1].mux_rd_fall2_r_reg[1]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_0\,
      \gen_mux_rd[1].mux_rd_fall2_r_reg[1]_0\ => \gen_mux_rd[1].mux_rd_fall2_r_reg[1]\,
      \gen_mux_rd[1].mux_rd_fall2_r_reg[1]_1\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_1\,
      \gen_mux_rd[1].mux_rd_fall3_r_reg[1]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_0\,
      \gen_mux_rd[1].mux_rd_fall3_r_reg[1]_0\ => \gen_mux_rd[1].mux_rd_fall3_r_reg[1]\,
      \gen_mux_rd[1].mux_rd_fall3_r_reg[1]_1\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_1\,
      \gen_mux_rd[1].mux_rd_rise0_r_reg[1]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0\,
      \gen_mux_rd[1].mux_rd_rise0_r_reg[1]_0\ => \gen_mux_rd[1].mux_rd_rise0_r_reg[1]\,
      \gen_mux_rd[1].mux_rd_rise0_r_reg[1]_1\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_1\,
      \gen_mux_rd[1].mux_rd_rise1_r_reg[1]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_0\,
      \gen_mux_rd[1].mux_rd_rise1_r_reg[1]_0\ => \gen_mux_rd[1].mux_rd_rise1_r_reg[1]\,
      \gen_mux_rd[1].mux_rd_rise1_r_reg[1]_1\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_1\,
      \gen_mux_rd[1].mux_rd_rise2_r_reg[1]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_0\,
      \gen_mux_rd[1].mux_rd_rise2_r_reg[1]_0\ => \gen_mux_rd[1].mux_rd_rise2_r_reg[1]\,
      \gen_mux_rd[1].mux_rd_rise2_r_reg[1]_1\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_1\,
      \gen_mux_rd[1].mux_rd_rise3_r_reg[1]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_0\,
      \gen_mux_rd[1].mux_rd_rise3_r_reg[1]_0\ => \gen_mux_rd[1].mux_rd_rise3_r_reg[1]\,
      \gen_mux_rd[1].mux_rd_rise3_r_reg[1]_1\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_1\,
      \gen_mux_rd[2].mux_rd_fall0_r_reg[2]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_0\,
      \gen_mux_rd[2].mux_rd_fall0_r_reg[2]_0\ => \gen_mux_rd[2].mux_rd_fall0_r_reg[2]\,
      \gen_mux_rd[2].mux_rd_fall0_r_reg[2]_1\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_1\,
      \gen_mux_rd[2].mux_rd_fall1_r_reg[2]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_0\,
      \gen_mux_rd[2].mux_rd_fall1_r_reg[2]_0\ => \gen_mux_rd[2].mux_rd_fall1_r_reg[2]\,
      \gen_mux_rd[2].mux_rd_fall1_r_reg[2]_1\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_1\,
      \gen_mux_rd[2].mux_rd_fall2_r_reg[2]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_0\,
      \gen_mux_rd[2].mux_rd_fall2_r_reg[2]_0\ => \gen_mux_rd[2].mux_rd_fall2_r_reg[2]\,
      \gen_mux_rd[2].mux_rd_fall2_r_reg[2]_1\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_1\,
      \gen_mux_rd[2].mux_rd_fall3_r_reg[2]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_0\,
      \gen_mux_rd[2].mux_rd_fall3_r_reg[2]_0\ => \gen_mux_rd[2].mux_rd_fall3_r_reg[2]\,
      \gen_mux_rd[2].mux_rd_fall3_r_reg[2]_1\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_1\,
      \gen_mux_rd[2].mux_rd_rise0_r_reg[2]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_0\,
      \gen_mux_rd[2].mux_rd_rise0_r_reg[2]_0\ => \gen_mux_rd[2].mux_rd_rise0_r_reg[2]\,
      \gen_mux_rd[2].mux_rd_rise0_r_reg[2]_1\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_1\,
      \gen_mux_rd[2].mux_rd_rise1_r_reg[2]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_0\,
      \gen_mux_rd[2].mux_rd_rise1_r_reg[2]_0\ => \gen_mux_rd[2].mux_rd_rise1_r_reg[2]\,
      \gen_mux_rd[2].mux_rd_rise1_r_reg[2]_1\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_1\,
      \gen_mux_rd[2].mux_rd_rise2_r_reg[2]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_0\,
      \gen_mux_rd[2].mux_rd_rise2_r_reg[2]_0\ => \gen_mux_rd[2].mux_rd_rise2_r_reg[2]\,
      \gen_mux_rd[2].mux_rd_rise2_r_reg[2]_1\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_1\,
      \gen_mux_rd[2].mux_rd_rise3_r_reg[2]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_0\,
      \gen_mux_rd[2].mux_rd_rise3_r_reg[2]_0\ => \gen_mux_rd[2].mux_rd_rise3_r_reg[2]\,
      \gen_mux_rd[2].mux_rd_rise3_r_reg[2]_1\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_1\,
      \gen_mux_rd[3].mux_rd_fall0_r_reg[3]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_0\,
      \gen_mux_rd[3].mux_rd_fall0_r_reg[3]_0\ => \gen_mux_rd[3].mux_rd_fall0_r_reg[3]\,
      \gen_mux_rd[3].mux_rd_fall0_r_reg[3]_1\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_1\,
      \gen_mux_rd[3].mux_rd_fall1_r_reg[3]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_0\,
      \gen_mux_rd[3].mux_rd_fall1_r_reg[3]_0\ => \gen_mux_rd[3].mux_rd_fall1_r_reg[3]\,
      \gen_mux_rd[3].mux_rd_fall1_r_reg[3]_1\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_1\,
      \gen_mux_rd[3].mux_rd_fall2_r_reg[3]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_0\,
      \gen_mux_rd[3].mux_rd_fall2_r_reg[3]_0\ => \gen_mux_rd[3].mux_rd_fall2_r_reg[3]\,
      \gen_mux_rd[3].mux_rd_fall2_r_reg[3]_1\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_1\,
      \gen_mux_rd[3].mux_rd_fall3_r_reg[3]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_0\,
      \gen_mux_rd[3].mux_rd_fall3_r_reg[3]_0\ => \gen_mux_rd[3].mux_rd_fall3_r_reg[3]\,
      \gen_mux_rd[3].mux_rd_fall3_r_reg[3]_1\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_1\,
      \gen_mux_rd[3].mux_rd_rise0_r_reg[3]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0\,
      \gen_mux_rd[3].mux_rd_rise0_r_reg[3]_0\ => \gen_mux_rd[3].mux_rd_rise0_r_reg[3]\,
      \gen_mux_rd[3].mux_rd_rise0_r_reg[3]_1\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_1\,
      \gen_mux_rd[3].mux_rd_rise1_r_reg[3]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_0\,
      \gen_mux_rd[3].mux_rd_rise1_r_reg[3]_0\ => \gen_mux_rd[3].mux_rd_rise1_r_reg[3]\,
      \gen_mux_rd[3].mux_rd_rise1_r_reg[3]_1\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_1\,
      \gen_mux_rd[3].mux_rd_rise2_r_reg[3]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_0\,
      \gen_mux_rd[3].mux_rd_rise2_r_reg[3]_0\ => \gen_mux_rd[3].mux_rd_rise2_r_reg[3]\,
      \gen_mux_rd[3].mux_rd_rise2_r_reg[3]_1\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_1\,
      \gen_mux_rd[3].mux_rd_rise3_r_reg[3]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_0\,
      \gen_mux_rd[3].mux_rd_rise3_r_reg[3]_0\ => \gen_mux_rd[3].mux_rd_rise3_r_reg[3]\,
      \gen_mux_rd[3].mux_rd_rise3_r_reg[3]_1\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_1\,
      \gen_mux_rd[4].mux_rd_fall0_r_reg[4]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_0\,
      \gen_mux_rd[4].mux_rd_fall0_r_reg[4]_0\ => \gen_mux_rd[4].mux_rd_fall0_r_reg[4]\,
      \gen_mux_rd[4].mux_rd_fall0_r_reg[4]_1\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_1\,
      \gen_mux_rd[4].mux_rd_fall1_r_reg[4]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_0\,
      \gen_mux_rd[4].mux_rd_fall1_r_reg[4]_0\ => \gen_mux_rd[4].mux_rd_fall1_r_reg[4]\,
      \gen_mux_rd[4].mux_rd_fall1_r_reg[4]_1\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_1\,
      \gen_mux_rd[4].mux_rd_fall2_r_reg[4]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_0\,
      \gen_mux_rd[4].mux_rd_fall2_r_reg[4]_0\ => \gen_mux_rd[4].mux_rd_fall2_r_reg[4]\,
      \gen_mux_rd[4].mux_rd_fall2_r_reg[4]_1\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_1\,
      \gen_mux_rd[4].mux_rd_fall3_r_reg[4]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_0\,
      \gen_mux_rd[4].mux_rd_fall3_r_reg[4]_0\ => \gen_mux_rd[4].mux_rd_fall3_r_reg[4]\,
      \gen_mux_rd[4].mux_rd_fall3_r_reg[4]_1\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_1\,
      \gen_mux_rd[4].mux_rd_rise0_r_reg[4]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_0\,
      \gen_mux_rd[4].mux_rd_rise0_r_reg[4]_0\ => \gen_mux_rd[4].mux_rd_rise0_r_reg[4]\,
      \gen_mux_rd[4].mux_rd_rise0_r_reg[4]_1\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_1\,
      \gen_mux_rd[4].mux_rd_rise1_r_reg[4]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_0\,
      \gen_mux_rd[4].mux_rd_rise1_r_reg[4]_0\ => \gen_mux_rd[4].mux_rd_rise1_r_reg[4]\,
      \gen_mux_rd[4].mux_rd_rise1_r_reg[4]_1\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_1\,
      \gen_mux_rd[4].mux_rd_rise2_r_reg[4]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_0\,
      \gen_mux_rd[4].mux_rd_rise2_r_reg[4]_0\ => \gen_mux_rd[4].mux_rd_rise2_r_reg[4]\,
      \gen_mux_rd[4].mux_rd_rise2_r_reg[4]_1\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_1\,
      \gen_mux_rd[4].mux_rd_rise3_r_reg[4]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_0\,
      \gen_mux_rd[4].mux_rd_rise3_r_reg[4]_0\ => \gen_mux_rd[4].mux_rd_rise3_r_reg[4]\,
      \gen_mux_rd[4].mux_rd_rise3_r_reg[4]_1\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_1\,
      \gen_mux_rd[5].mux_rd_fall0_r_reg[5]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_0\,
      \gen_mux_rd[5].mux_rd_fall0_r_reg[5]_0\ => \gen_mux_rd[5].mux_rd_fall0_r_reg[5]\,
      \gen_mux_rd[5].mux_rd_fall0_r_reg[5]_1\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_1\,
      \gen_mux_rd[5].mux_rd_fall1_r_reg[5]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_0\,
      \gen_mux_rd[5].mux_rd_fall1_r_reg[5]_0\ => \gen_mux_rd[5].mux_rd_fall1_r_reg[5]\,
      \gen_mux_rd[5].mux_rd_fall1_r_reg[5]_1\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_1\,
      \gen_mux_rd[5].mux_rd_fall2_r_reg[5]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_0\,
      \gen_mux_rd[5].mux_rd_fall2_r_reg[5]_0\ => \gen_mux_rd[5].mux_rd_fall2_r_reg[5]\,
      \gen_mux_rd[5].mux_rd_fall2_r_reg[5]_1\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_1\,
      \gen_mux_rd[5].mux_rd_fall3_r_reg[5]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_0\,
      \gen_mux_rd[5].mux_rd_fall3_r_reg[5]_0\ => \gen_mux_rd[5].mux_rd_fall3_r_reg[5]\,
      \gen_mux_rd[5].mux_rd_fall3_r_reg[5]_1\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_1\,
      \gen_mux_rd[5].mux_rd_rise0_r_reg[5]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0\,
      \gen_mux_rd[5].mux_rd_rise0_r_reg[5]_0\ => \gen_mux_rd[5].mux_rd_rise0_r_reg[5]\,
      \gen_mux_rd[5].mux_rd_rise0_r_reg[5]_1\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_1\,
      \gen_mux_rd[5].mux_rd_rise1_r_reg[5]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_0\,
      \gen_mux_rd[5].mux_rd_rise1_r_reg[5]_0\ => \gen_mux_rd[5].mux_rd_rise1_r_reg[5]\,
      \gen_mux_rd[5].mux_rd_rise1_r_reg[5]_1\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_1\,
      \gen_mux_rd[5].mux_rd_rise2_r_reg[5]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_0\,
      \gen_mux_rd[5].mux_rd_rise2_r_reg[5]_0\ => \gen_mux_rd[5].mux_rd_rise2_r_reg[5]\,
      \gen_mux_rd[5].mux_rd_rise2_r_reg[5]_1\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_1\,
      \gen_mux_rd[5].mux_rd_rise3_r_reg[5]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_0\,
      \gen_mux_rd[5].mux_rd_rise3_r_reg[5]_0\ => \gen_mux_rd[5].mux_rd_rise3_r_reg[5]\,
      \gen_mux_rd[5].mux_rd_rise3_r_reg[5]_1\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_1\,
      \gen_mux_rd[6].mux_rd_fall0_r_reg[6]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_0\,
      \gen_mux_rd[6].mux_rd_fall0_r_reg[6]_0\ => \gen_mux_rd[6].mux_rd_fall0_r_reg[6]\,
      \gen_mux_rd[6].mux_rd_fall0_r_reg[6]_1\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_1\,
      \gen_mux_rd[6].mux_rd_fall1_r_reg[6]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_0\,
      \gen_mux_rd[6].mux_rd_fall1_r_reg[6]_0\ => \gen_mux_rd[6].mux_rd_fall1_r_reg[6]\,
      \gen_mux_rd[6].mux_rd_fall1_r_reg[6]_1\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_1\,
      \gen_mux_rd[6].mux_rd_fall2_r_reg[6]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_0\,
      \gen_mux_rd[6].mux_rd_fall2_r_reg[6]_0\ => \gen_mux_rd[6].mux_rd_fall2_r_reg[6]\,
      \gen_mux_rd[6].mux_rd_fall2_r_reg[6]_1\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_1\,
      \gen_mux_rd[6].mux_rd_fall3_r_reg[6]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_0\,
      \gen_mux_rd[6].mux_rd_fall3_r_reg[6]_0\ => \gen_mux_rd[6].mux_rd_fall3_r_reg[6]\,
      \gen_mux_rd[6].mux_rd_fall3_r_reg[6]_1\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_1\,
      \gen_mux_rd[6].mux_rd_rise0_r_reg[6]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_0\,
      \gen_mux_rd[6].mux_rd_rise0_r_reg[6]_0\ => \gen_mux_rd[6].mux_rd_rise0_r_reg[6]\,
      \gen_mux_rd[6].mux_rd_rise0_r_reg[6]_1\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_1\,
      \gen_mux_rd[6].mux_rd_rise1_r_reg[6]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_0\,
      \gen_mux_rd[6].mux_rd_rise1_r_reg[6]_0\ => \gen_mux_rd[6].mux_rd_rise1_r_reg[6]\,
      \gen_mux_rd[6].mux_rd_rise1_r_reg[6]_1\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_1\,
      \gen_mux_rd[6].mux_rd_rise2_r_reg[6]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_0\,
      \gen_mux_rd[6].mux_rd_rise2_r_reg[6]_0\ => \gen_mux_rd[6].mux_rd_rise2_r_reg[6]\,
      \gen_mux_rd[6].mux_rd_rise2_r_reg[6]_1\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_1\,
      \gen_mux_rd[6].mux_rd_rise3_r_reg[6]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_0\,
      \gen_mux_rd[6].mux_rd_rise3_r_reg[6]_0\ => \gen_mux_rd[6].mux_rd_rise3_r_reg[6]\,
      \gen_mux_rd[6].mux_rd_rise3_r_reg[6]_1\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_1\,
      \gen_mux_rd[7].mux_rd_fall0_r_reg[7]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_0\,
      \gen_mux_rd[7].mux_rd_fall0_r_reg[7]_0\ => \gen_mux_rd[7].mux_rd_fall0_r_reg[7]\,
      \gen_mux_rd[7].mux_rd_fall0_r_reg[7]_1\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_1\,
      \gen_mux_rd[7].mux_rd_fall1_r_reg[7]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_0\,
      \gen_mux_rd[7].mux_rd_fall1_r_reg[7]_0\ => \gen_mux_rd[7].mux_rd_fall1_r_reg[7]\,
      \gen_mux_rd[7].mux_rd_fall1_r_reg[7]_1\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_1\,
      \gen_mux_rd[7].mux_rd_fall2_r_reg[7]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_0\,
      \gen_mux_rd[7].mux_rd_fall2_r_reg[7]_0\ => \gen_mux_rd[7].mux_rd_fall2_r_reg[7]\,
      \gen_mux_rd[7].mux_rd_fall2_r_reg[7]_1\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_1\,
      \gen_mux_rd[7].mux_rd_fall3_r_reg[7]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0\,
      \gen_mux_rd[7].mux_rd_fall3_r_reg[7]_0\ => \gen_mux_rd[7].mux_rd_fall3_r_reg[7]\,
      \gen_mux_rd[7].mux_rd_fall3_r_reg[7]_1\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_1\,
      \gen_mux_rd[7].mux_rd_rise0_r_reg[7]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_0\,
      \gen_mux_rd[7].mux_rd_rise0_r_reg[7]_0\ => \gen_mux_rd[7].mux_rd_rise0_r_reg[7]\,
      \gen_mux_rd[7].mux_rd_rise0_r_reg[7]_1\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_1\,
      \gen_mux_rd[7].mux_rd_rise1_r_reg[7]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_0\,
      \gen_mux_rd[7].mux_rd_rise1_r_reg[7]_0\ => \gen_mux_rd[7].mux_rd_rise1_r_reg[7]\,
      \gen_mux_rd[7].mux_rd_rise1_r_reg[7]_1\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_1\,
      \gen_mux_rd[7].mux_rd_rise2_r_reg[7]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_0\,
      \gen_mux_rd[7].mux_rd_rise2_r_reg[7]_0\ => \gen_mux_rd[7].mux_rd_rise2_r_reg[7]\,
      \gen_mux_rd[7].mux_rd_rise2_r_reg[7]_1\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_1\,
      \gen_mux_rd[7].mux_rd_rise3_r_reg[7]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_0\,
      \gen_mux_rd[7].mux_rd_rise3_r_reg[7]_0\ => \gen_mux_rd[7].mux_rd_rise3_r_reg[7]\,
      \gen_mux_rd[7].mux_rd_rise3_r_reg[7]_1\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_1\,
      idelay_inc => idelay_inc,
      idelay_ld_rst_4 => idelay_ld_rst_4,
      if_empty_r(0) => if_empty_r_2(3),
      ififo_rst_reg_0 => ififo_rst_reg_0,
      in0(0) => in0(1),
      \input_[9].iserdes_dq_.iserdesdq\ => \input_[9].iserdes_dq_.iserdesdq_0\,
      mem_dq_in(7 downto 0) => mem_dq_in(15 downto 8),
      mem_dq_out(8 downto 0) => mem_dq_out(17 downto 9),
      mem_dq_ts(8 downto 0) => mem_dq_ts(17 downto 9),
      mem_dqs_in(0) => mem_dqs_in(1),
      mem_refclk => mem_refclk,
      \my_empty_reg[1]\ => \my_empty_reg[1]_0\,
      \my_empty_reg[4]\(1) => \dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/my_empty_1\(3),
      \my_empty_reg[4]\(0) => \dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/my_empty_1\(0),
      \my_empty_reg[7]\(7 downto 0) => \my_empty_reg[7]_6\(7 downto 0),
      \my_empty_reg[7]_0\(7 downto 0) => \my_empty_reg[7]_7\(7 downto 0),
      \my_empty_reg[7]_1\(7 downto 0) => \my_empty_reg[7]_8\(7 downto 0),
      \my_empty_reg[7]_2\(7 downto 0) => \my_empty_reg[7]_9\(7 downto 0),
      \my_empty_reg[7]_3\(7 downto 0) => \my_empty_reg[7]_10\(7 downto 0),
      \my_empty_reg[7]_4\(7 downto 0) => \my_empty_reg[7]_11\(7 downto 0),
      \my_empty_reg[7]_5\(7 downto 0) => \my_empty_reg[7]_12\(7 downto 0),
      \my_empty_reg[7]_6\(7 downto 0) => \my_empty_reg[7]_13\(7 downto 0),
      \my_full_reg[1]\ => \ddr_byte_lane_D.ddr_byte_lane_D_n_235\,
      out_dqs_1 => out_dqs_1,
      out_fifo_0 => out_fifo,
      out_fifo_1(7) => out_fifo_0(29),
      out_fifo_1(6) => out_fifo_0(25),
      out_fifo_1(5) => out_fifo_0(21),
      out_fifo_1(4) => out_fifo_0(17),
      out_fifo_1(3) => out_fifo_0(13),
      out_fifo_1(2) => out_fifo_0(9),
      out_fifo_1(1) => out_fifo_0(5),
      out_fifo_1(0) => out_fifo_0(1),
      out_fifo_2 => out_fifo_1,
      \out_fifo_i_75__1\(71 downto 0) => \out_fifo_i_75__1\(71 downto 0),
      phaser_ctl_bus(3 downto 2) => phaser_ctl_bus(11 downto 10),
      phaser_ctl_bus(1) => phaser_ctl_bus(5),
      phaser_ctl_bus(0) => phaser_ctl_bus(1),
      phy_data_wr_en => phy_data_wr_en,
      phy_if_reset => phy_if_reset,
      \pi_counter_read_val_reg[5]\(5 downto 0) => D_pi_counter_read_val(5 downto 0),
      \pi_counter_read_val_reg[5]_0\(5 downto 0) => C_pi_counter_read_val(5 downto 0),
      \pi_dqs_found_lanes_r1_reg[9]\ => \pi_dqs_found_lanes_r1_reg[9]\,
      \pi_dqs_found_lanes_r1_reg[9]_0\ => \pi_dqs_found_lanes_r1_reg[9]_0\,
      \pi_dqs_found_lanes_r1_reg[9]_1\ => \pi_dqs_found_lanes_r1_reg[9]_1\,
      \pi_dqs_found_lanes_r1_reg[9]_2\ => \pi_dqs_found_lanes_r1_reg[9]_2\,
      \pi_dqs_found_lanes_r1_reg[9]_3\(5 downto 0) => \pi_dqs_found_lanes_r1_reg[9]_3\(5 downto 0),
      \po_counter_read_val_reg[8]\ => \po_counter_read_val_reg[8]_3\,
      \po_counter_read_val_reg[8]_0\ => \po_counter_read_val_reg[8]_4\,
      \po_counter_read_val_reg[8]_1\ => \po_counter_read_val_reg[8]_5\,
      \po_counter_read_val_reg[8]_2\(8 downto 0) => A_po_counter_read_val(8 downto 0),
      \po_counter_read_val_reg[8]_3\(8 downto 0) => D_po_counter_read_val(8 downto 0),
      \po_counter_read_val_reg[8]_4\(8 downto 0) => C_po_counter_read_val(8 downto 0),
      \rd_mux_sel_r_reg[0]\ => \rd_mux_sel_r_reg[0]\,
      \rd_mux_sel_r_reg[0]_0\ => \rd_mux_sel_r_reg[0]_0\,
      \rd_mux_sel_r_reg[0]_1\ => \rd_mux_sel_r_reg[0]_1\,
      \rd_mux_sel_r_reg[0]_10\ => \rd_mux_sel_r_reg[0]_10\,
      \rd_mux_sel_r_reg[0]_11\ => \rd_mux_sel_r_reg[0]_11\,
      \rd_mux_sel_r_reg[0]_12\ => \rd_mux_sel_r_reg[0]_12\,
      \rd_mux_sel_r_reg[0]_13\ => \rd_mux_sel_r_reg[0]_13\,
      \rd_mux_sel_r_reg[0]_14\ => \rd_mux_sel_r_reg[0]_14\,
      \rd_mux_sel_r_reg[0]_15\ => \rd_mux_sel_r_reg[0]_15\,
      \rd_mux_sel_r_reg[0]_16\ => \rd_mux_sel_r_reg[0]_16\,
      \rd_mux_sel_r_reg[0]_17\ => \rd_mux_sel_r_reg[0]_17\,
      \rd_mux_sel_r_reg[0]_18\ => \rd_mux_sel_r_reg[0]_18\,
      \rd_mux_sel_r_reg[0]_19\ => \rd_mux_sel_r_reg[0]_19\,
      \rd_mux_sel_r_reg[0]_2\ => \rd_mux_sel_r_reg[0]_2\,
      \rd_mux_sel_r_reg[0]_20\ => \rd_mux_sel_r_reg[0]_20\,
      \rd_mux_sel_r_reg[0]_21\ => \rd_mux_sel_r_reg[0]_21\,
      \rd_mux_sel_r_reg[0]_22\ => \rd_mux_sel_r_reg[0]_22\,
      \rd_mux_sel_r_reg[0]_23\ => \rd_mux_sel_r_reg[0]_23\,
      \rd_mux_sel_r_reg[0]_24\ => \rd_mux_sel_r_reg[0]_24\,
      \rd_mux_sel_r_reg[0]_25\ => \rd_mux_sel_r_reg[0]_25\,
      \rd_mux_sel_r_reg[0]_26\ => \rd_mux_sel_r_reg[0]_26\,
      \rd_mux_sel_r_reg[0]_27\ => \rd_mux_sel_r_reg[0]_27\,
      \rd_mux_sel_r_reg[0]_28\ => \rd_mux_sel_r_reg[0]_28\,
      \rd_mux_sel_r_reg[0]_29\ => \rd_mux_sel_r_reg[0]_29\,
      \rd_mux_sel_r_reg[0]_3\ => \rd_mux_sel_r_reg[0]_3\,
      \rd_mux_sel_r_reg[0]_30\ => \rd_mux_sel_r_reg[0]_30\,
      \rd_mux_sel_r_reg[0]_31\ => \rd_mux_sel_r_reg[0]_31\,
      \rd_mux_sel_r_reg[0]_32\ => \rd_mux_sel_r_reg[0]_32\,
      \rd_mux_sel_r_reg[0]_33\ => \rd_mux_sel_r_reg[0]_33\,
      \rd_mux_sel_r_reg[0]_34\ => \rd_mux_sel_r_reg[0]_34\,
      \rd_mux_sel_r_reg[0]_35\ => \rd_mux_sel_r_reg[0]_35\,
      \rd_mux_sel_r_reg[0]_36\ => \rd_mux_sel_r_reg[0]_36\,
      \rd_mux_sel_r_reg[0]_37\ => \rd_mux_sel_r_reg[0]_37\,
      \rd_mux_sel_r_reg[0]_38\ => \rd_mux_sel_r_reg[0]_38\,
      \rd_mux_sel_r_reg[0]_39\ => \rd_mux_sel_r_reg[0]_39\,
      \rd_mux_sel_r_reg[0]_4\ => \rd_mux_sel_r_reg[0]_4\,
      \rd_mux_sel_r_reg[0]_40\ => \rd_mux_sel_r_reg[0]_40\,
      \rd_mux_sel_r_reg[0]_41\ => \rd_mux_sel_r_reg[0]_41\,
      \rd_mux_sel_r_reg[0]_42\ => \rd_mux_sel_r_reg[0]_42\,
      \rd_mux_sel_r_reg[0]_43\ => \rd_mux_sel_r_reg[0]_43\,
      \rd_mux_sel_r_reg[0]_44\ => \rd_mux_sel_r_reg[0]_44\,
      \rd_mux_sel_r_reg[0]_45\ => \rd_mux_sel_r_reg[0]_45\,
      \rd_mux_sel_r_reg[0]_46\ => \rd_mux_sel_r_reg[0]_46\,
      \rd_mux_sel_r_reg[0]_47\ => \rd_mux_sel_r_reg[0]_47\,
      \rd_mux_sel_r_reg[0]_48\ => \rd_mux_sel_r_reg[0]_48\,
      \rd_mux_sel_r_reg[0]_49\ => \rd_mux_sel_r_reg[0]_49\,
      \rd_mux_sel_r_reg[0]_5\ => \rd_mux_sel_r_reg[0]_5\,
      \rd_mux_sel_r_reg[0]_50\ => \rd_mux_sel_r_reg[0]_50\,
      \rd_mux_sel_r_reg[0]_51\ => \rd_mux_sel_r_reg[0]_51\,
      \rd_mux_sel_r_reg[0]_52\ => \rd_mux_sel_r_reg[0]_52\,
      \rd_mux_sel_r_reg[0]_53\ => \rd_mux_sel_r_reg[0]_53\,
      \rd_mux_sel_r_reg[0]_54\ => \rd_mux_sel_r_reg[0]_54\,
      \rd_mux_sel_r_reg[0]_55\ => \rd_mux_sel_r_reg[0]_55\,
      \rd_mux_sel_r_reg[0]_56\ => \rd_mux_sel_r_reg[0]_56\,
      \rd_mux_sel_r_reg[0]_57\ => \rd_mux_sel_r_reg[0]_57\,
      \rd_mux_sel_r_reg[0]_58\ => \rd_mux_sel_r_reg[0]_58\,
      \rd_mux_sel_r_reg[0]_59\ => \rd_mux_sel_r_reg[0]_59\,
      \rd_mux_sel_r_reg[0]_6\ => \rd_mux_sel_r_reg[0]_6\,
      \rd_mux_sel_r_reg[0]_60\ => \rd_mux_sel_r_reg[0]_60\,
      \rd_mux_sel_r_reg[0]_61\ => \rd_mux_sel_r_reg[0]_61\,
      \rd_mux_sel_r_reg[0]_62\ => \rd_mux_sel_r_reg[0]_62\,
      \rd_mux_sel_r_reg[0]_7\ => \rd_mux_sel_r_reg[0]_7\,
      \rd_mux_sel_r_reg[0]_8\ => \rd_mux_sel_r_reg[0]_8\,
      \rd_mux_sel_r_reg[0]_9\ => \rd_mux_sel_r_reg[0]_9\,
      \rd_ptr_reg[3]\(63 downto 0) => \rd_ptr_reg[3]_0\(63 downto 0),
      rst_r4 => rst_r4,
      sync_pulse => sync_pulse,
      ts_dqs_1 => ts_dqs_1
    );
\ddr_byte_lane_C.ddr_byte_lane_C\: entity work.\mig_mig_7series_v4_2_ddr_byte_lane__parameterized1\
     port map (
      A_rst_primitives => A_rst_primitives,
      A_rst_primitives_reg => A_rst_primitives_reg_2,
      A_rst_primitives_reg_0 => \ddr_byte_lane_C.ddr_byte_lane_C_n_22\,
      A_rst_primitives_reg_1(5 downto 0) => C_pi_counter_read_val(5 downto 0),
      A_rst_primitives_reg_2(8 downto 0) => C_po_counter_read_val(8 downto 0),
      CLKB0_12 => CLKB0_12,
      LD0_12 => LD0_12,
      PCENABLECALIB(1 downto 0) => phy_encalib(1 downto 0),
      Q(2 downto 0) => \of_pre_fifo_gen.u_ddr_of_pre_fifo/entry_cnt_reg_3\(4 downto 2),
      \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0\ => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]\,
      \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1\ => \ddr_byte_lane_C.ddr_byte_lane_C_n_41\,
      \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_2\ => \ddr_byte_lane_C.ddr_byte_lane_C_n_106\,
      \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_3\ => \ddr_byte_lane_C.ddr_byte_lane_C_n_107\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0\,
      freq_refclk => freq_refclk,
      idelay_inc => idelay_inc,
      idelay_ld_rst_5 => idelay_ld_rst_5,
      if_empty_r(0) => if_empty_r_2(3),
      ififo_rst_reg_0 => ififo_rst_reg_1,
      in0(0) => in0(2),
      \input_[9].iserdes_dq_.iserdesdq\ => \input_[9].iserdes_dq_.iserdesdq_1\,
      mem_dq_in(7 downto 0) => mem_dq_in(23 downto 16),
      mem_dq_out(8 downto 0) => mem_dq_out(26 downto 18),
      mem_dq_ts(8 downto 0) => mem_dq_ts(26 downto 18),
      mem_dqs_in(0) => mem_dqs_in(2),
      mem_refclk => mem_refclk,
      \my_empty_reg[1]\ => \my_empty_reg[1]_1\,
      \my_empty_reg[7]\(7 downto 0) => \my_empty_reg[7]_14\(7 downto 0),
      \my_empty_reg[7]_0\(7 downto 0) => \my_empty_reg[7]_15\(7 downto 0),
      \my_empty_reg[7]_1\(7 downto 0) => \my_empty_reg[7]_16\(7 downto 0),
      \my_empty_reg[7]_2\(7 downto 0) => \my_empty_reg[7]_17\(7 downto 0),
      \my_empty_reg[7]_3\(7 downto 0) => \my_empty_reg[7]_18\(7 downto 0),
      \my_empty_reg[7]_4\(7 downto 0) => \my_empty_reg[7]_19\(7 downto 0),
      \my_empty_reg[7]_5\(7 downto 0) => \my_empty_reg[7]_20\(7 downto 0),
      \my_empty_reg[7]_6\(7 downto 0) => \my_empty_reg[7]_21\(7 downto 0),
      \my_full_reg[1]\ => \ddr_byte_lane_D.ddr_byte_lane_D_n_236\,
      \my_full_reg[1]_0\ => \^dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1\,
      \my_full_reg[1]_1\ => \ddr_byte_lane_B.ddr_byte_lane_B_n_157\,
      \my_full_reg[1]_2\ => \my_full_reg[1]\,
      \my_full_reg[1]_3\ => \my_full_reg[1]_0\,
      \my_full_reg[1]_4\ => \^dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0\,
      out_dqs_2 => out_dqs_2,
      out_fifo_0 => out_fifo,
      out_fifo_1(7) => out_fifo_0(30),
      out_fifo_1(6) => out_fifo_0(26),
      out_fifo_1(5) => out_fifo_0(22),
      out_fifo_1(4) => out_fifo_0(18),
      out_fifo_1(3) => out_fifo_0(14),
      out_fifo_1(2) => out_fifo_0(10),
      out_fifo_1(1) => out_fifo_0(6),
      out_fifo_1(0) => out_fifo_0(2),
      out_fifo_2 => out_fifo_1,
      \out_fifo_i_75__2\(71 downto 0) => \out_fifo_i_75__2\(71 downto 0),
      phaser_ctl_bus(3 downto 2) => phaser_ctl_bus(13 downto 12),
      phaser_ctl_bus(1) => phaser_ctl_bus(6),
      phaser_ctl_bus(0) => phaser_ctl_bus(2),
      phy_data_wr_en => phy_data_wr_en,
      phy_if_reset => phy_if_reset,
      \pi_dqs_found_lanes_r1_reg[10]\ => \pi_dqs_found_lanes_r1_reg[10]\,
      \pi_dqs_found_lanes_r1_reg[10]_0\ => \pi_dqs_found_lanes_r1_reg[10]_0\,
      \pi_dqs_found_lanes_r1_reg[10]_1\ => \pi_dqs_found_lanes_r1_reg[10]_1\,
      \pi_dqs_found_lanes_r1_reg[10]_2\ => \pi_dqs_found_lanes_r1_reg[10]_2\,
      \pi_dqs_found_lanes_r1_reg[10]_3\(5 downto 0) => \pi_dqs_found_lanes_r1_reg[10]_3\(5 downto 0),
      \po_counter_read_val_reg[8]\ => \po_counter_read_val_reg[8]_6\,
      \po_counter_read_val_reg[8]_0\ => \po_counter_read_val_reg[8]_7\,
      \po_counter_read_val_reg[8]_1\ => \po_counter_read_val_reg[8]_8\,
      \rd_ptr_reg[3]\(63 downto 0) => \rd_ptr_reg[3]_1\(63 downto 0),
      rst_r4 => rst_r4,
      sync_pulse => sync_pulse,
      ts_dqs_2 => ts_dqs_2,
      \wr_ptr[1]_i_2__2\(1) => \dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/my_empty_1\(3),
      \wr_ptr[1]_i_2__2\(0) => \dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/my_empty_1\(0),
      \wr_ptr_timing_reg[3]\ => \entry_cnt_reg[4]_1\
    );
\ddr_byte_lane_D.ddr_byte_lane_D\: entity work.\mig_mig_7series_v4_2_ddr_byte_lane__parameterized2\
     port map (
      A_rst_primitives => A_rst_primitives,
      A_rst_primitives_reg => A_rst_primitives_reg_3,
      A_rst_primitives_reg_0(5 downto 0) => D_pi_counter_read_val(5 downto 0),
      A_rst_primitives_reg_1(8 downto 0) => D_po_counter_read_val(8 downto 0),
      A_rst_primitives_reg_2 => A_rst_primitives_reg_4,
      CLKB0_13 => CLKB0_13,
      LD0_13 => LD0_13,
      PCENABLECALIB(1 downto 0) => phy_encalib(1 downto 0),
      Q(2 downto 0) => \of_pre_fifo_gen.u_ddr_of_pre_fifo/entry_cnt_reg_4\(4 downto 2),
      \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0\ => \ddr_byte_lane_D.ddr_byte_lane_D_n_233\,
      \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1\ => \^dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0\,
      \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_2\ => \ddr_byte_lane_D.ddr_byte_lane_D_n_235\,
      \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_3\ => \ddr_byte_lane_D.ddr_byte_lane_D_n_236\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_2\,
      \entry_cnt_reg[4]\ => \entry_cnt_reg[4]_1\,
      freq_refclk => freq_refclk,
      \gen_mux_rd[0].mux_rd_fall0_r1_reg[0]\ => \gen_mux_rd[0].mux_rd_fall0_r1_reg[0]\,
      \gen_mux_rd[0].mux_rd_fall1_r1_reg[0]\ => \gen_mux_rd[0].mux_rd_fall1_r1_reg[0]\,
      \gen_mux_rd[0].mux_rd_fall2_r1_reg[0]\ => \gen_mux_rd[0].mux_rd_fall2_r1_reg[0]\,
      \gen_mux_rd[0].mux_rd_fall3_r1_reg[0]\ => \gen_mux_rd[0].mux_rd_fall3_r1_reg[0]\,
      \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]\(2 downto 0) => \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]\(2 downto 0),
      \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]_0\ => \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]_0\,
      \gen_mux_rd[0].mux_rd_rise1_r1_reg[0]\ => \gen_mux_rd[0].mux_rd_rise1_r1_reg[0]\,
      \gen_mux_rd[0].mux_rd_rise2_r1_reg[0]\ => \gen_mux_rd[0].mux_rd_rise2_r1_reg[0]\,
      \gen_mux_rd[0].mux_rd_rise3_r1_reg[0]\ => \gen_mux_rd[0].mux_rd_rise3_r1_reg[0]\,
      \gen_mux_rd[1].mux_rd_fall0_r1_reg[1]\ => \gen_mux_rd[1].mux_rd_fall0_r1_reg[1]\,
      \gen_mux_rd[1].mux_rd_fall1_r1_reg[1]\ => \gen_mux_rd[1].mux_rd_fall1_r1_reg[1]\,
      \gen_mux_rd[1].mux_rd_fall2_r1_reg[1]\ => \gen_mux_rd[1].mux_rd_fall2_r1_reg[1]\,
      \gen_mux_rd[1].mux_rd_fall3_r1_reg[1]\ => \gen_mux_rd[1].mux_rd_fall3_r1_reg[1]\,
      \gen_mux_rd[1].mux_rd_rise0_r1_reg[1]\ => \gen_mux_rd[1].mux_rd_rise0_r1_reg[1]\,
      \gen_mux_rd[1].mux_rd_rise1_r1_reg[1]\ => \gen_mux_rd[1].mux_rd_rise1_r1_reg[1]\,
      \gen_mux_rd[1].mux_rd_rise2_r1_reg[1]\ => \gen_mux_rd[1].mux_rd_rise2_r1_reg[1]\,
      \gen_mux_rd[1].mux_rd_rise3_r1_reg[1]\ => \gen_mux_rd[1].mux_rd_rise3_r1_reg[1]\,
      \gen_mux_rd[2].mux_rd_fall0_r1_reg[2]\ => \gen_mux_rd[2].mux_rd_fall0_r1_reg[2]\,
      \gen_mux_rd[2].mux_rd_fall1_r1_reg[2]\ => \gen_mux_rd[2].mux_rd_fall1_r1_reg[2]\,
      \gen_mux_rd[2].mux_rd_fall2_r1_reg[2]\ => \gen_mux_rd[2].mux_rd_fall2_r1_reg[2]\,
      \gen_mux_rd[2].mux_rd_fall3_r1_reg[2]\ => \gen_mux_rd[2].mux_rd_fall3_r1_reg[2]\,
      \gen_mux_rd[2].mux_rd_rise0_r1_reg[2]\ => \gen_mux_rd[2].mux_rd_rise0_r1_reg[2]\,
      \gen_mux_rd[2].mux_rd_rise1_r1_reg[2]\ => \gen_mux_rd[2].mux_rd_rise1_r1_reg[2]\,
      \gen_mux_rd[2].mux_rd_rise2_r1_reg[2]\ => \gen_mux_rd[2].mux_rd_rise2_r1_reg[2]\,
      \gen_mux_rd[2].mux_rd_rise3_r1_reg[2]\ => \gen_mux_rd[2].mux_rd_rise3_r1_reg[2]\,
      \gen_mux_rd[3].mux_rd_fall0_r1_reg[3]\ => \gen_mux_rd[3].mux_rd_fall0_r1_reg[3]\,
      \gen_mux_rd[3].mux_rd_fall1_r1_reg[3]\ => \gen_mux_rd[3].mux_rd_fall1_r1_reg[3]\,
      \gen_mux_rd[3].mux_rd_fall2_r1_reg[3]\ => \gen_mux_rd[3].mux_rd_fall2_r1_reg[3]\,
      \gen_mux_rd[3].mux_rd_fall3_r1_reg[3]\ => \gen_mux_rd[3].mux_rd_fall3_r1_reg[3]\,
      \gen_mux_rd[3].mux_rd_rise0_r1_reg[3]\ => \gen_mux_rd[3].mux_rd_rise0_r1_reg[3]\,
      \gen_mux_rd[3].mux_rd_rise1_r1_reg[3]\ => \gen_mux_rd[3].mux_rd_rise1_r1_reg[3]\,
      \gen_mux_rd[3].mux_rd_rise2_r1_reg[3]\ => \gen_mux_rd[3].mux_rd_rise2_r1_reg[3]\,
      \gen_mux_rd[3].mux_rd_rise3_r1_reg[3]\ => \gen_mux_rd[3].mux_rd_rise3_r1_reg[3]\,
      \gen_mux_rd[4].mux_rd_fall0_r1_reg[4]\ => \gen_mux_rd[4].mux_rd_fall0_r1_reg[4]\,
      \gen_mux_rd[4].mux_rd_fall1_r1_reg[4]\ => \gen_mux_rd[4].mux_rd_fall1_r1_reg[4]\,
      \gen_mux_rd[4].mux_rd_fall2_r1_reg[4]\ => \gen_mux_rd[4].mux_rd_fall2_r1_reg[4]\,
      \gen_mux_rd[4].mux_rd_fall3_r1_reg[4]\ => \gen_mux_rd[4].mux_rd_fall3_r1_reg[4]\,
      \gen_mux_rd[4].mux_rd_rise0_r1_reg[4]\ => \gen_mux_rd[4].mux_rd_rise0_r1_reg[4]\,
      \gen_mux_rd[4].mux_rd_rise1_r1_reg[4]\ => \gen_mux_rd[4].mux_rd_rise1_r1_reg[4]\,
      \gen_mux_rd[4].mux_rd_rise2_r1_reg[4]\ => \gen_mux_rd[4].mux_rd_rise2_r1_reg[4]\,
      \gen_mux_rd[4].mux_rd_rise3_r1_reg[4]\ => \gen_mux_rd[4].mux_rd_rise3_r1_reg[4]\,
      \gen_mux_rd[5].mux_rd_fall0_r1_reg[5]\ => \gen_mux_rd[5].mux_rd_fall0_r1_reg[5]\,
      \gen_mux_rd[5].mux_rd_fall1_r1_reg[5]\ => \gen_mux_rd[5].mux_rd_fall1_r1_reg[5]\,
      \gen_mux_rd[5].mux_rd_fall2_r1_reg[5]\ => \gen_mux_rd[5].mux_rd_fall2_r1_reg[5]\,
      \gen_mux_rd[5].mux_rd_fall3_r1_reg[5]\ => \gen_mux_rd[5].mux_rd_fall3_r1_reg[5]\,
      \gen_mux_rd[5].mux_rd_rise0_r1_reg[5]\ => \gen_mux_rd[5].mux_rd_rise0_r1_reg[5]\,
      \gen_mux_rd[5].mux_rd_rise1_r1_reg[5]\ => \gen_mux_rd[5].mux_rd_rise1_r1_reg[5]\,
      \gen_mux_rd[5].mux_rd_rise2_r1_reg[5]\ => \gen_mux_rd[5].mux_rd_rise2_r1_reg[5]\,
      \gen_mux_rd[5].mux_rd_rise3_r1_reg[5]\ => \gen_mux_rd[5].mux_rd_rise3_r1_reg[5]\,
      \gen_mux_rd[6].mux_rd_fall0_r1_reg[6]\ => \gen_mux_rd[6].mux_rd_fall0_r1_reg[6]\,
      \gen_mux_rd[6].mux_rd_fall1_r1_reg[6]\ => \gen_mux_rd[6].mux_rd_fall1_r1_reg[6]\,
      \gen_mux_rd[6].mux_rd_fall2_r1_reg[6]\ => \gen_mux_rd[6].mux_rd_fall2_r1_reg[6]\,
      \gen_mux_rd[6].mux_rd_fall3_r1_reg[6]\ => \gen_mux_rd[6].mux_rd_fall3_r1_reg[6]\,
      \gen_mux_rd[6].mux_rd_rise0_r1_reg[6]\ => \gen_mux_rd[6].mux_rd_rise0_r1_reg[6]\,
      \gen_mux_rd[6].mux_rd_rise1_r1_reg[6]\ => \gen_mux_rd[6].mux_rd_rise1_r1_reg[6]\,
      \gen_mux_rd[6].mux_rd_rise2_r1_reg[6]\ => \gen_mux_rd[6].mux_rd_rise2_r1_reg[6]\,
      \gen_mux_rd[6].mux_rd_rise3_r1_reg[6]\ => \gen_mux_rd[6].mux_rd_rise3_r1_reg[6]\,
      \gen_mux_rd[7].mux_rd_fall0_r1_reg[7]\ => \gen_mux_rd[7].mux_rd_fall0_r1_reg[7]\,
      \gen_mux_rd[7].mux_rd_fall1_r1_reg[7]\ => \gen_mux_rd[7].mux_rd_fall1_r1_reg[7]\,
      \gen_mux_rd[7].mux_rd_fall2_r1_reg[7]\ => \gen_mux_rd[7].mux_rd_fall2_r1_reg[7]\,
      \gen_mux_rd[7].mux_rd_fall3_r1_reg[7]\ => \gen_mux_rd[7].mux_rd_fall3_r1_reg[7]\,
      \gen_mux_rd[7].mux_rd_rise0_r1_reg[7]\ => \gen_mux_rd[7].mux_rd_rise0_r1_reg[7]\,
      \gen_mux_rd[7].mux_rd_rise1_r1_reg[7]\ => \gen_mux_rd[7].mux_rd_rise1_r1_reg[7]\,
      \gen_mux_rd[7].mux_rd_rise2_r1_reg[7]\ => \gen_mux_rd[7].mux_rd_rise2_r1_reg[7]\,
      \gen_mux_rd[7].mux_rd_rise3_r1_reg[7]\ => \gen_mux_rd[7].mux_rd_rise3_r1_reg[7]\,
      \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg[0]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_0\,
      \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg[0]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]\,
      \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg[0]_1\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]\,
      \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg[0]_2\ => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg[0]\,
      \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg[0]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_0\,
      \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg[0]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]\,
      \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg[0]_1\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]\,
      \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg[0]_2\ => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg[0]\,
      \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg[0]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_0\,
      \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg[0]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]\,
      \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg[0]_1\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]\,
      \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg[0]_2\ => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg[0]\,
      \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg[0]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_0\,
      \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg[0]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]\,
      \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg[0]_1\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]\,
      \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg[0]_2\ => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg[0]\,
      \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg[0]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_0\,
      \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg[0]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]\,
      \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg[0]_1\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]\,
      \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg[0]_2\ => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg[0]\,
      \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_0\,
      \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]\,
      \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_1\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]\,
      \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2\(2 downto 0) => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]\(2 downto 0),
      \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_3\ => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_0\,
      \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise2_r_reg[0]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_0\,
      \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise2_r_reg[0]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]\,
      \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise2_r_reg[0]_1\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]\,
      \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise2_r_reg[0]_2\ => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise2_r_reg[0]\,
      \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg[0]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_0\,
      \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg[0]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]\,
      \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg[0]_1\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]\,
      \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg[0]_2\ => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg[0]\,
      \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg[1]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_0\,
      \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg[1]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]\,
      \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg[1]_1\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_1\,
      \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg[1]_2\ => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg[1]\,
      \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg[1]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_0\,
      \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg[1]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]\,
      \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg[1]_1\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_1\,
      \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg[1]_2\ => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg[1]\,
      \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg[1]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_0\,
      \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg[1]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]\,
      \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg[1]_1\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_1\,
      \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg[1]_2\ => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg[1]\,
      \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg[1]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_0\,
      \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg[1]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]\,
      \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg[1]_1\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_1\,
      \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg[1]_2\ => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg[1]\,
      \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg[1]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0\,
      \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg[1]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]\,
      \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg[1]_1\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_1\,
      \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg[1]_2\ => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg[1]\,
      \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg[1]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_0\,
      \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg[1]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]\,
      \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg[1]_1\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_1\,
      \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg[1]_2\ => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg[1]\,
      \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg[1]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_0\,
      \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg[1]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]\,
      \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg[1]_1\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_1\,
      \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg[1]_2\ => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg[1]\,
      \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg[1]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_0\,
      \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg[1]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]\,
      \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg[1]_1\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_1\,
      \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg[1]_2\ => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg[1]\,
      \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg[2]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_0\,
      \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg[2]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]\,
      \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg[2]_1\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_1\,
      \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg[2]_2\ => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg[2]\,
      \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg[2]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_0\,
      \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg[2]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]\,
      \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg[2]_1\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_1\,
      \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg[2]_2\ => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg[2]\,
      \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg[2]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_0\,
      \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg[2]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]\,
      \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg[2]_1\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_1\,
      \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg[2]_2\ => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg[2]\,
      \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg[2]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_0\,
      \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg[2]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]\,
      \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg[2]_1\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_1\,
      \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg[2]_2\ => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg[2]\,
      \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg[2]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_0\,
      \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg[2]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]\,
      \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg[2]_1\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_1\,
      \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg[2]_2\ => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg[2]\,
      \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg[2]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_0\,
      \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg[2]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]\,
      \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg[2]_1\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_1\,
      \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg[2]_2\ => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg[2]\,
      \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg[2]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_0\,
      \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg[2]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]\,
      \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg[2]_1\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_1\,
      \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg[2]_2\ => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg[2]\,
      \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg[2]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_0\,
      \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg[2]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]\,
      \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg[2]_1\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_1\,
      \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg[2]_2\ => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg[2]\,
      \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg[3]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_0\,
      \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg[3]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]\,
      \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg[3]_1\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_1\,
      \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg[3]_2\ => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg[3]\,
      \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg[3]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_0\,
      \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg[3]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]\,
      \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg[3]_1\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_1\,
      \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg[3]_2\ => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg[3]\,
      \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg[3]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_0\,
      \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg[3]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]\,
      \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg[3]_1\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_1\,
      \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg[3]_2\ => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg[3]\,
      \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg[3]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_0\,
      \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg[3]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]\,
      \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg[3]_1\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_1\,
      \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg[3]_2\ => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg[3]\,
      \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg[3]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0\,
      \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg[3]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]\,
      \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg[3]_1\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_1\,
      \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg[3]_2\ => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg[3]\,
      \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg[3]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_0\,
      \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg[3]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]\,
      \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg[3]_1\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_1\,
      \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg[3]_2\ => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg[3]\,
      \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg[3]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_0\,
      \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg[3]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]\,
      \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg[3]_1\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_1\,
      \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg[3]_2\ => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg[3]\,
      \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise3_r_reg[3]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_0\,
      \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise3_r_reg[3]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]\,
      \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise3_r_reg[3]_1\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_1\,
      \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise3_r_reg[3]_2\ => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise3_r_reg[3]\,
      \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg[4]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_0\,
      \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg[4]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]\,
      \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg[4]_1\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_1\,
      \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg[4]_2\ => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg[4]\,
      \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg[4]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_0\,
      \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg[4]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]\,
      \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg[4]_1\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_1\,
      \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg[4]_2\ => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg[4]\,
      \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg[4]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_0\,
      \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg[4]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]\,
      \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg[4]_1\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_1\,
      \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg[4]_2\ => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg[4]\,
      \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg[4]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_0\,
      \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg[4]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]\,
      \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg[4]_1\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_1\,
      \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg[4]_2\ => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg[4]\,
      \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg[4]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_0\,
      \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg[4]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]\,
      \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg[4]_1\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_1\,
      \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg[4]_2\ => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg[4]\,
      \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg[4]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_0\,
      \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg[4]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]\,
      \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg[4]_1\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_1\,
      \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg[4]_2\ => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg[4]\,
      \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise2_r_reg[4]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_0\,
      \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise2_r_reg[4]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]\,
      \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise2_r_reg[4]_1\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_1\,
      \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise2_r_reg[4]_2\ => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise2_r_reg[4]\,
      \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg[4]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_0\,
      \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg[4]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]\,
      \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg[4]_1\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_1\,
      \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg[4]_2\ => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg[4]\,
      \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg[5]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_0\,
      \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg[5]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]\,
      \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg[5]_1\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_1\,
      \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg[5]_2\ => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg[5]\,
      \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg[5]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_0\,
      \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg[5]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]\,
      \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg[5]_1\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_1\,
      \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg[5]_2\ => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg[5]\,
      \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg[5]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_0\,
      \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg[5]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]\,
      \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg[5]_1\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_1\,
      \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg[5]_2\ => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg[5]\,
      \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg[5]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_0\,
      \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg[5]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]\,
      \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg[5]_1\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_1\,
      \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg[5]_2\ => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg[5]\,
      \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg[5]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0\,
      \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg[5]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]\,
      \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg[5]_1\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_1\,
      \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg[5]_2\ => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg[5]\,
      \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg[5]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_0\,
      \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg[5]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]\,
      \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg[5]_1\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_1\,
      \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg[5]_2\ => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg[5]\,
      \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg[5]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_0\,
      \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg[5]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]\,
      \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg[5]_1\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_1\,
      \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg[5]_2\ => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg[5]\,
      \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg[5]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_0\,
      \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg[5]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]\,
      \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg[5]_1\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_1\,
      \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg[5]_2\ => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg[5]\,
      \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg[6]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_0\,
      \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg[6]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]\,
      \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg[6]_1\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_1\,
      \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg[6]_2\ => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg[6]\,
      \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg[6]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_0\,
      \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg[6]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]\,
      \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg[6]_1\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_1\,
      \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg[6]_2\ => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg[6]\,
      \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg[6]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_0\,
      \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg[6]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]\,
      \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg[6]_1\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_1\,
      \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg[6]_2\ => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg[6]\,
      \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg[6]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_0\,
      \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg[6]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]\,
      \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg[6]_1\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_1\,
      \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg[6]_2\ => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg[6]\,
      \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg[6]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_0\,
      \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg[6]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]\,
      \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg[6]_1\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_1\,
      \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg[6]_2\ => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg[6]\,
      \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg[6]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_0\,
      \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg[6]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]\,
      \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg[6]_1\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_1\,
      \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg[6]_2\ => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg[6]\,
      \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg[6]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_0\,
      \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg[6]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]\,
      \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg[6]_1\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_1\,
      \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg[6]_2\ => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg[6]\,
      \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg[6]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_0\,
      \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg[6]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]\,
      \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg[6]_1\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_1\,
      \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg[6]_2\ => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg[6]\,
      \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg[7]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_0\,
      \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg[7]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]\,
      \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg[7]_1\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_1\,
      \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg[7]_2\ => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg[7]\,
      \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg[7]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_0\,
      \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg[7]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]\,
      \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg[7]_1\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_1\,
      \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg[7]_2\ => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg[7]\,
      \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg[7]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_0\,
      \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg[7]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]\,
      \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg[7]_1\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_1\,
      \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg[7]_2\ => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg[7]\,
      \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0\,
      \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]\,
      \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7]_1\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_1\,
      \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7]_2\ => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7]\,
      \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg[7]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_0\,
      \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg[7]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]\,
      \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg[7]_1\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_1\,
      \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg[7]_2\ => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg[7]\,
      \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg[7]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_0\,
      \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg[7]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]\,
      \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg[7]_1\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_1\,
      \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg[7]_2\ => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg[7]\,
      \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg[7]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_0\,
      \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg[7]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]\,
      \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg[7]_1\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_1\,
      \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg[7]_2\ => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg[7]\,
      \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise3_r_reg[7]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_0\,
      \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise3_r_reg[7]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]\,
      \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise3_r_reg[7]_1\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_1\,
      \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise3_r_reg[7]_2\ => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise3_r_reg[7]\,
      idelay_inc => idelay_inc,
      idelay_ld_rst_6 => idelay_ld_rst_6,
      if_empty_r(0) => if_empty_r(3),
      if_empty_v(0) => if_empty_v(0),
      ififo_rst_reg_0 => ififo_rst_reg_2,
      in0(0) => in0(3),
      \input_[9].iserdes_dq_.iserdesdq\ => \input_[9].iserdes_dq_.iserdesdq_2\,
      mem_dq_in(7 downto 0) => mem_dq_in(31 downto 24),
      mem_dq_out(8 downto 0) => mem_dq_out(35 downto 27),
      mem_dq_ts(8 downto 0) => mem_dq_ts(35 downto 27),
      mem_dqs_in(0) => mem_dqs_in(3),
      mem_refclk => mem_refclk,
      \my_empty_reg[1]\ => \my_empty_reg[1]_2\,
      \my_empty_reg[7]\(7 downto 0) => \my_empty_reg[7]_22\(7 downto 0),
      \my_empty_reg[7]_0\(7 downto 0) => \my_empty_reg[7]_23\(7 downto 0),
      \my_empty_reg[7]_1\(7 downto 0) => \my_empty_reg[7]_24\(7 downto 0),
      \my_empty_reg[7]_2\(7 downto 0) => \my_empty_reg[7]_25\(7 downto 0),
      \my_empty_reg[7]_3\(7 downto 0) => \my_empty_reg[7]_26\(7 downto 0),
      \my_empty_reg[7]_4\(7 downto 0) => \my_empty_reg[7]_27\(7 downto 0),
      \my_empty_reg[7]_5\(7 downto 0) => \my_empty_reg[7]_28\(7 downto 0),
      \my_empty_reg[7]_6\(7 downto 0) => \my_empty_reg[7]_29\(7 downto 0),
      \my_full_reg[1]\ => \ddr_byte_lane_C.ddr_byte_lane_C_n_106\,
      \my_full_reg[1]_0\ => \ddr_byte_lane_B.ddr_byte_lane_B_n_157\,
      \my_full_reg[1]_1\ => \ddr_byte_lane_C.ddr_byte_lane_C_n_41\,
      \my_full_reg[1]_2\ => \my_full_reg[1]\,
      \my_full_reg[1]_3\ => \my_full_reg[1]_0\,
      \my_full_reg[1]_4\ => \^dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1\,
      out_dqs_3 => out_dqs_3,
      out_fifo_0 => out_fifo,
      out_fifo_1(7) => out_fifo_0(31),
      out_fifo_1(6) => out_fifo_0(27),
      out_fifo_1(5) => out_fifo_0(23),
      out_fifo_1(4) => out_fifo_0(19),
      out_fifo_1(3) => out_fifo_0(15),
      out_fifo_1(2) => out_fifo_0(11),
      out_fifo_1(1) => out_fifo_0(7),
      out_fifo_1(0) => out_fifo_0(3),
      out_fifo_2 => out_fifo_1,
      \out_fifo_i_75__3\(71 downto 0) => \out_fifo_i_75__3\(71 downto 0),
      p_0_out => p_0_out,
      phaser_ctl_bus(3 downto 2) => phaser_ctl_bus(15 downto 14),
      phaser_ctl_bus(1) => phaser_ctl_bus(7),
      phaser_ctl_bus(0) => phaser_ctl_bus(3),
      phy_data_wr_en => phy_data_wr_en,
      phy_if_empty_r_reg(0) => \dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/my_empty\(0),
      phy_if_empty_r_reg_0 => \ddr_byte_lane_C.ddr_byte_lane_C_n_107\,
      phy_if_reset => phy_if_reset,
      \pi_dqs_found_lanes_r1_reg[11]\ => \pi_dqs_found_lanes_r1_reg[11]\,
      \pi_dqs_found_lanes_r1_reg[11]_0\ => \pi_dqs_found_lanes_r1_reg[11]_0\,
      \pi_dqs_found_lanes_r1_reg[11]_1\ => \pi_dqs_found_lanes_r1_reg[11]_1\,
      \pi_dqs_found_lanes_r1_reg[11]_2\ => \pi_dqs_found_lanes_r1_reg[11]_2\,
      \pi_dqs_found_lanes_r1_reg[11]_3\(5 downto 0) => \pi_dqs_found_lanes_r1_reg[11]_3\(5 downto 0),
      pi_phase_locked_all_r1_reg => \ddr_byte_lane_A.ddr_byte_lane_A_n_22\,
      pi_phase_locked_all_r1_reg_0 => \ddr_byte_lane_B.ddr_byte_lane_B_n_22\,
      pi_phase_locked_all_r1_reg_1 => \ddr_byte_lane_C.ddr_byte_lane_C_n_22\,
      \po_counter_read_val_reg[8]\ => \po_counter_read_val_reg[8]_9\,
      \po_counter_read_val_reg[8]_0\ => \po_counter_read_val_reg[8]_10\,
      \po_counter_read_val_reg[8]_1\ => \po_counter_read_val_reg[8]_11\,
      \po_stg2_wrcal_cnt_reg[2]\ => \po_stg2_wrcal_cnt_reg[2]\,
      \po_stg2_wrcal_cnt_reg[2]_0\ => \po_stg2_wrcal_cnt_reg[2]_0\,
      \po_stg2_wrcal_cnt_reg[2]_1\ => \po_stg2_wrcal_cnt_reg[2]_1\,
      \po_stg2_wrcal_cnt_reg[2]_10\ => \po_stg2_wrcal_cnt_reg[2]_10\,
      \po_stg2_wrcal_cnt_reg[2]_11\ => \po_stg2_wrcal_cnt_reg[2]_11\,
      \po_stg2_wrcal_cnt_reg[2]_12\ => \po_stg2_wrcal_cnt_reg[2]_12\,
      \po_stg2_wrcal_cnt_reg[2]_13\ => \po_stg2_wrcal_cnt_reg[2]_13\,
      \po_stg2_wrcal_cnt_reg[2]_14\ => \po_stg2_wrcal_cnt_reg[2]_14\,
      \po_stg2_wrcal_cnt_reg[2]_15\ => \po_stg2_wrcal_cnt_reg[2]_15\,
      \po_stg2_wrcal_cnt_reg[2]_16\ => \po_stg2_wrcal_cnt_reg[2]_16\,
      \po_stg2_wrcal_cnt_reg[2]_17\ => \po_stg2_wrcal_cnt_reg[2]_17\,
      \po_stg2_wrcal_cnt_reg[2]_18\ => \po_stg2_wrcal_cnt_reg[2]_18\,
      \po_stg2_wrcal_cnt_reg[2]_19\ => \po_stg2_wrcal_cnt_reg[2]_19\,
      \po_stg2_wrcal_cnt_reg[2]_2\ => \po_stg2_wrcal_cnt_reg[2]_2\,
      \po_stg2_wrcal_cnt_reg[2]_20\ => \po_stg2_wrcal_cnt_reg[2]_20\,
      \po_stg2_wrcal_cnt_reg[2]_21\ => \po_stg2_wrcal_cnt_reg[2]_21\,
      \po_stg2_wrcal_cnt_reg[2]_22\ => \po_stg2_wrcal_cnt_reg[2]_22\,
      \po_stg2_wrcal_cnt_reg[2]_23\ => \po_stg2_wrcal_cnt_reg[2]_23\,
      \po_stg2_wrcal_cnt_reg[2]_24\ => \po_stg2_wrcal_cnt_reg[2]_24\,
      \po_stg2_wrcal_cnt_reg[2]_25\ => \po_stg2_wrcal_cnt_reg[2]_25\,
      \po_stg2_wrcal_cnt_reg[2]_26\ => \po_stg2_wrcal_cnt_reg[2]_26\,
      \po_stg2_wrcal_cnt_reg[2]_27\ => \po_stg2_wrcal_cnt_reg[2]_27\,
      \po_stg2_wrcal_cnt_reg[2]_28\ => \po_stg2_wrcal_cnt_reg[2]_28\,
      \po_stg2_wrcal_cnt_reg[2]_29\ => \po_stg2_wrcal_cnt_reg[2]_29\,
      \po_stg2_wrcal_cnt_reg[2]_3\ => \po_stg2_wrcal_cnt_reg[2]_3\,
      \po_stg2_wrcal_cnt_reg[2]_30\ => \po_stg2_wrcal_cnt_reg[2]_30\,
      \po_stg2_wrcal_cnt_reg[2]_31\ => \po_stg2_wrcal_cnt_reg[2]_31\,
      \po_stg2_wrcal_cnt_reg[2]_32\ => \po_stg2_wrcal_cnt_reg[2]_32\,
      \po_stg2_wrcal_cnt_reg[2]_33\ => \po_stg2_wrcal_cnt_reg[2]_33\,
      \po_stg2_wrcal_cnt_reg[2]_34\ => \po_stg2_wrcal_cnt_reg[2]_34\,
      \po_stg2_wrcal_cnt_reg[2]_35\ => \po_stg2_wrcal_cnt_reg[2]_35\,
      \po_stg2_wrcal_cnt_reg[2]_36\ => \po_stg2_wrcal_cnt_reg[2]_36\,
      \po_stg2_wrcal_cnt_reg[2]_37\ => \po_stg2_wrcal_cnt_reg[2]_37\,
      \po_stg2_wrcal_cnt_reg[2]_38\ => \po_stg2_wrcal_cnt_reg[2]_38\,
      \po_stg2_wrcal_cnt_reg[2]_39\ => \po_stg2_wrcal_cnt_reg[2]_39\,
      \po_stg2_wrcal_cnt_reg[2]_4\ => \po_stg2_wrcal_cnt_reg[2]_4\,
      \po_stg2_wrcal_cnt_reg[2]_40\ => \po_stg2_wrcal_cnt_reg[2]_40\,
      \po_stg2_wrcal_cnt_reg[2]_41\ => \po_stg2_wrcal_cnt_reg[2]_41\,
      \po_stg2_wrcal_cnt_reg[2]_42\ => \po_stg2_wrcal_cnt_reg[2]_42\,
      \po_stg2_wrcal_cnt_reg[2]_43\ => \po_stg2_wrcal_cnt_reg[2]_43\,
      \po_stg2_wrcal_cnt_reg[2]_44\ => \po_stg2_wrcal_cnt_reg[2]_44\,
      \po_stg2_wrcal_cnt_reg[2]_45\ => \po_stg2_wrcal_cnt_reg[2]_45\,
      \po_stg2_wrcal_cnt_reg[2]_46\ => \po_stg2_wrcal_cnt_reg[2]_46\,
      \po_stg2_wrcal_cnt_reg[2]_47\ => \po_stg2_wrcal_cnt_reg[2]_47\,
      \po_stg2_wrcal_cnt_reg[2]_48\ => \po_stg2_wrcal_cnt_reg[2]_48\,
      \po_stg2_wrcal_cnt_reg[2]_49\ => \po_stg2_wrcal_cnt_reg[2]_49\,
      \po_stg2_wrcal_cnt_reg[2]_5\ => \po_stg2_wrcal_cnt_reg[2]_5\,
      \po_stg2_wrcal_cnt_reg[2]_50\ => \po_stg2_wrcal_cnt_reg[2]_50\,
      \po_stg2_wrcal_cnt_reg[2]_51\ => \po_stg2_wrcal_cnt_reg[2]_51\,
      \po_stg2_wrcal_cnt_reg[2]_52\ => \po_stg2_wrcal_cnt_reg[2]_52\,
      \po_stg2_wrcal_cnt_reg[2]_53\ => \po_stg2_wrcal_cnt_reg[2]_53\,
      \po_stg2_wrcal_cnt_reg[2]_54\ => \po_stg2_wrcal_cnt_reg[2]_54\,
      \po_stg2_wrcal_cnt_reg[2]_55\ => \po_stg2_wrcal_cnt_reg[2]_55\,
      \po_stg2_wrcal_cnt_reg[2]_56\ => \po_stg2_wrcal_cnt_reg[2]_56\,
      \po_stg2_wrcal_cnt_reg[2]_57\ => \po_stg2_wrcal_cnt_reg[2]_57\,
      \po_stg2_wrcal_cnt_reg[2]_58\ => \po_stg2_wrcal_cnt_reg[2]_58\,
      \po_stg2_wrcal_cnt_reg[2]_59\ => \po_stg2_wrcal_cnt_reg[2]_59\,
      \po_stg2_wrcal_cnt_reg[2]_6\ => \po_stg2_wrcal_cnt_reg[2]_6\,
      \po_stg2_wrcal_cnt_reg[2]_60\ => \po_stg2_wrcal_cnt_reg[2]_60\,
      \po_stg2_wrcal_cnt_reg[2]_61\ => \po_stg2_wrcal_cnt_reg[2]_61\,
      \po_stg2_wrcal_cnt_reg[2]_7\ => \po_stg2_wrcal_cnt_reg[2]_7\,
      \po_stg2_wrcal_cnt_reg[2]_8\ => \po_stg2_wrcal_cnt_reg[2]_8\,
      \po_stg2_wrcal_cnt_reg[2]_9\ => \po_stg2_wrcal_cnt_reg[2]_9\,
      \rd_mux_sel_r_reg[2]\ => \rd_mux_sel_r_reg[2]\,
      \rd_mux_sel_r_reg[2]_0\ => \rd_mux_sel_r_reg[2]_0\,
      \rd_mux_sel_r_reg[2]_1\ => \rd_mux_sel_r_reg[2]_1\,
      \rd_mux_sel_r_reg[2]_10\ => \rd_mux_sel_r_reg[2]_10\,
      \rd_mux_sel_r_reg[2]_11\ => \rd_mux_sel_r_reg[2]_11\,
      \rd_mux_sel_r_reg[2]_12\ => \rd_mux_sel_r_reg[2]_12\,
      \rd_mux_sel_r_reg[2]_13\ => \rd_mux_sel_r_reg[2]_13\,
      \rd_mux_sel_r_reg[2]_14\ => \rd_mux_sel_r_reg[2]_14\,
      \rd_mux_sel_r_reg[2]_15\ => \rd_mux_sel_r_reg[2]_15\,
      \rd_mux_sel_r_reg[2]_16\ => \rd_mux_sel_r_reg[2]_16\,
      \rd_mux_sel_r_reg[2]_17\ => \rd_mux_sel_r_reg[2]_17\,
      \rd_mux_sel_r_reg[2]_18\ => \rd_mux_sel_r_reg[2]_18\,
      \rd_mux_sel_r_reg[2]_19\ => \rd_mux_sel_r_reg[2]_19\,
      \rd_mux_sel_r_reg[2]_2\ => \rd_mux_sel_r_reg[2]_2\,
      \rd_mux_sel_r_reg[2]_20\ => \rd_mux_sel_r_reg[2]_20\,
      \rd_mux_sel_r_reg[2]_21\ => \rd_mux_sel_r_reg[2]_21\,
      \rd_mux_sel_r_reg[2]_22\ => \rd_mux_sel_r_reg[2]_22\,
      \rd_mux_sel_r_reg[2]_23\ => \rd_mux_sel_r_reg[2]_23\,
      \rd_mux_sel_r_reg[2]_24\ => \rd_mux_sel_r_reg[2]_24\,
      \rd_mux_sel_r_reg[2]_25\ => \rd_mux_sel_r_reg[2]_25\,
      \rd_mux_sel_r_reg[2]_26\ => \rd_mux_sel_r_reg[2]_26\,
      \rd_mux_sel_r_reg[2]_27\ => \rd_mux_sel_r_reg[2]_27\,
      \rd_mux_sel_r_reg[2]_28\ => \rd_mux_sel_r_reg[2]_28\,
      \rd_mux_sel_r_reg[2]_29\ => \rd_mux_sel_r_reg[2]_29\,
      \rd_mux_sel_r_reg[2]_3\ => \rd_mux_sel_r_reg[2]_3\,
      \rd_mux_sel_r_reg[2]_30\ => \rd_mux_sel_r_reg[2]_30\,
      \rd_mux_sel_r_reg[2]_31\ => \rd_mux_sel_r_reg[2]_31\,
      \rd_mux_sel_r_reg[2]_32\ => \rd_mux_sel_r_reg[2]_32\,
      \rd_mux_sel_r_reg[2]_33\ => \rd_mux_sel_r_reg[2]_33\,
      \rd_mux_sel_r_reg[2]_34\ => \rd_mux_sel_r_reg[2]_34\,
      \rd_mux_sel_r_reg[2]_35\ => \rd_mux_sel_r_reg[2]_35\,
      \rd_mux_sel_r_reg[2]_36\ => \rd_mux_sel_r_reg[2]_36\,
      \rd_mux_sel_r_reg[2]_37\ => \rd_mux_sel_r_reg[2]_37\,
      \rd_mux_sel_r_reg[2]_38\ => \rd_mux_sel_r_reg[2]_38\,
      \rd_mux_sel_r_reg[2]_39\ => \rd_mux_sel_r_reg[2]_39\,
      \rd_mux_sel_r_reg[2]_4\ => \rd_mux_sel_r_reg[2]_4\,
      \rd_mux_sel_r_reg[2]_40\ => \rd_mux_sel_r_reg[2]_40\,
      \rd_mux_sel_r_reg[2]_41\ => \rd_mux_sel_r_reg[2]_41\,
      \rd_mux_sel_r_reg[2]_42\ => \rd_mux_sel_r_reg[2]_42\,
      \rd_mux_sel_r_reg[2]_43\ => \rd_mux_sel_r_reg[2]_43\,
      \rd_mux_sel_r_reg[2]_44\ => \rd_mux_sel_r_reg[2]_44\,
      \rd_mux_sel_r_reg[2]_45\ => \rd_mux_sel_r_reg[2]_45\,
      \rd_mux_sel_r_reg[2]_46\ => \rd_mux_sel_r_reg[2]_46\,
      \rd_mux_sel_r_reg[2]_47\ => \rd_mux_sel_r_reg[2]_47\,
      \rd_mux_sel_r_reg[2]_48\ => \rd_mux_sel_r_reg[2]_48\,
      \rd_mux_sel_r_reg[2]_49\ => \rd_mux_sel_r_reg[2]_49\,
      \rd_mux_sel_r_reg[2]_5\ => \rd_mux_sel_r_reg[2]_5\,
      \rd_mux_sel_r_reg[2]_50\ => \rd_mux_sel_r_reg[2]_50\,
      \rd_mux_sel_r_reg[2]_51\ => \rd_mux_sel_r_reg[2]_51\,
      \rd_mux_sel_r_reg[2]_52\ => \rd_mux_sel_r_reg[2]_52\,
      \rd_mux_sel_r_reg[2]_53\ => \rd_mux_sel_r_reg[2]_53\,
      \rd_mux_sel_r_reg[2]_54\ => \rd_mux_sel_r_reg[2]_54\,
      \rd_mux_sel_r_reg[2]_55\ => \rd_mux_sel_r_reg[2]_55\,
      \rd_mux_sel_r_reg[2]_56\ => \rd_mux_sel_r_reg[2]_56\,
      \rd_mux_sel_r_reg[2]_57\ => \rd_mux_sel_r_reg[2]_57\,
      \rd_mux_sel_r_reg[2]_58\ => \rd_mux_sel_r_reg[2]_58\,
      \rd_mux_sel_r_reg[2]_59\ => \rd_mux_sel_r_reg[2]_59\,
      \rd_mux_sel_r_reg[2]_6\ => \rd_mux_sel_r_reg[2]_6\,
      \rd_mux_sel_r_reg[2]_60\ => \rd_mux_sel_r_reg[2]_60\,
      \rd_mux_sel_r_reg[2]_61\ => \rd_mux_sel_r_reg[2]_61\,
      \rd_mux_sel_r_reg[2]_62\ => \rd_mux_sel_r_reg[2]_62\,
      \rd_mux_sel_r_reg[2]_7\ => \rd_mux_sel_r_reg[2]_7\,
      \rd_mux_sel_r_reg[2]_8\ => \rd_mux_sel_r_reg[2]_8\,
      \rd_mux_sel_r_reg[2]_9\ => \rd_mux_sel_r_reg[2]_9\,
      \rd_ptr_reg[3]\(63 downto 0) => \rd_ptr_reg[3]_2\(63 downto 0),
      rst_r4 => rst_r4,
      sync_pulse => sync_pulse,
      ts_dqs_3 => ts_dqs_3
    );
i_0: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => A_pi_rst_div2
    );
i_1: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => B_pi_rst_div2
    );
i_2: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => C_pi_rst_div2
    );
i_3: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => D_pi_rst_div2
    );
mcGo_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \entry_cnt_reg[4]_1\,
      CE => '1',
      D => \^rst_out_reg_0\,
      Q => mcGo_w(0),
      R => '0'
    );
ofs_rdy_r_i_5: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFFFE"
    )
        port map (
      I0 => \of_pre_fifo_gen.u_ddr_of_pre_fifo/entry_cnt_reg_3\(4),
      I1 => \of_pre_fifo_gen.u_ddr_of_pre_fifo/entry_cnt_reg_3\(2),
      I2 => \of_pre_fifo_gen.u_ddr_of_pre_fifo/entry_cnt_reg_3\(3),
      I3 => \of_pre_fifo_gen.u_ddr_of_pre_fifo/entry_cnt_reg_0\(4),
      I4 => \of_pre_fifo_gen.u_ddr_of_pre_fifo/entry_cnt_reg_0\(2),
      I5 => \of_pre_fifo_gen.u_ddr_of_pre_fifo/entry_cnt_reg_0\(3),
      O => \entry_cnt_reg[4]_0\
    );
ofs_rdy_r_i_6: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFFFE"
    )
        port map (
      I0 => \of_pre_fifo_gen.u_ddr_of_pre_fifo/entry_cnt_reg\(4),
      I1 => \of_pre_fifo_gen.u_ddr_of_pre_fifo/entry_cnt_reg\(2),
      I2 => \of_pre_fifo_gen.u_ddr_of_pre_fifo/entry_cnt_reg\(3),
      I3 => \of_pre_fifo_gen.u_ddr_of_pre_fifo/entry_cnt_reg_4\(4),
      I4 => \of_pre_fifo_gen.u_ddr_of_pre_fifo/entry_cnt_reg_4\(2),
      I5 => \of_pre_fifo_gen.u_ddr_of_pre_fifo/entry_cnt_reg_4\(3),
      O => \entry_cnt_reg[4]\
    );
phaser_ref_i: unisim.vcomponents.PHASER_REF
    generic map(
      IS_PWRDWN_INVERTED => '0',
      IS_RST_INVERTED => '0'
    )
        port map (
      CLKIN => freq_refclk,
      LOCKED => \^ref_dll_lock_w__0\(0),
      PWRDWN => '0',
      RST => RST0
    );
phy_control_i: unisim.vcomponents.PHY_CONTROL
    generic map(
      AO_TOGGLE => 1,
      AO_WRLVL_EN => B"0000",
      BURST_MODE => "TRUE",
      CLK_RATIO => 4,
      CMD_OFFSET => 8,
      CO_DURATION => 1,
      DATA_CTL_A_N => "TRUE",
      DATA_CTL_B_N => "TRUE",
      DATA_CTL_C_N => "TRUE",
      DATA_CTL_D_N => "TRUE",
      DISABLE_SEQ_MATCH => "TRUE",
      DI_DURATION => 1,
      DO_DURATION => 1,
      EVENTS_DELAY => 18,
      FOUR_WINDOW_CLOCKS => 63,
      MULTI_REGION => "TRUE",
      PHY_COUNT_ENABLE => "FALSE",
      RD_CMD_OFFSET_0 => 10,
      RD_CMD_OFFSET_1 => 10,
      RD_CMD_OFFSET_2 => 10,
      RD_CMD_OFFSET_3 => 10,
      RD_DURATION_0 => 6,
      RD_DURATION_1 => 6,
      RD_DURATION_2 => 6,
      RD_DURATION_3 => 6,
      SYNC_MODE => "FALSE",
      WR_CMD_OFFSET_0 => 8,
      WR_CMD_OFFSET_1 => 8,
      WR_CMD_OFFSET_2 => 8,
      WR_CMD_OFFSET_3 => 8,
      WR_DURATION_0 => 7,
      WR_DURATION_1 => 7,
      WR_DURATION_2 => 7,
      WR_DURATION_3 => 7
    )
        port map (
      AUXOUTPUT(3) => phy_control_i_n_14,
      AUXOUTPUT(2) => phy_control_i_n_15,
      AUXOUTPUT(1) => phy_control_i_n_16,
      AUXOUTPUT(0) => phy_control_i_n_17,
      INBURSTPENDING(3 downto 0) => phaser_ctl_bus(7 downto 4),
      INRANKA(1 downto 0) => phaser_ctl_bus(9 downto 8),
      INRANKB(1 downto 0) => phaser_ctl_bus(11 downto 10),
      INRANKC(1 downto 0) => phaser_ctl_bus(13 downto 12),
      INRANKD(1 downto 0) => phaser_ctl_bus(15 downto 14),
      MEMREFCLK => mem_refclk,
      OUTBURSTPENDING(3 downto 0) => phaser_ctl_bus(3 downto 0),
      PCENABLECALIB(1 downto 0) => phy_encalib(1 downto 0),
      PHYCLK => \entry_cnt_reg[4]_1\,
      PHYCTLALMOSTFULL => phy_control_i_n_0,
      PHYCTLEMPTY => phy_control_i_n_1,
      PHYCTLFULL => \_phy_ctl_full_p__0\(0),
      PHYCTLMSTREMPTY => phy_ctl_mstr_empty,
      PHYCTLREADY => phy_ctl_wr_i2_reg,
      PHYCTLWD(31 downto 25) => B"0000001",
      PHYCTLWD(24 downto 17) => PHYCTLWD(10 downto 3),
      PHYCTLWD(16 downto 3) => B"00000000000000",
      PHYCTLWD(2 downto 0) => PHYCTLWD(2 downto 0),
      PHYCTLWRENABLE => phy_ctl_wr_i2,
      PLLLOCK => pll_locked,
      READCALIBENABLE => phy_read_calib,
      REFDLLLOCK => \^ref_dll_lock_w__0\(0),
      RESET => phy_mc_ctl_full_r_reg,
      SYNCIN => sync_pulse,
      WRITECALIBENABLE => phy_write_calib
    );
\pi_counter_read_val_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]_1\,
      CE => '1',
      D => \ddr_byte_lane_B.ddr_byte_lane_B_n_227\,
      Q => \pi_counter_read_val_reg[5]_0\(0),
      R => '0'
    );
\pi_counter_read_val_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]_1\,
      CE => '1',
      D => \ddr_byte_lane_B.ddr_byte_lane_B_n_226\,
      Q => \pi_counter_read_val_reg[5]_0\(1),
      R => '0'
    );
\pi_counter_read_val_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]_1\,
      CE => '1',
      D => \ddr_byte_lane_B.ddr_byte_lane_B_n_225\,
      Q => \pi_counter_read_val_reg[5]_0\(2),
      R => '0'
    );
\pi_counter_read_val_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]_1\,
      CE => '1',
      D => \ddr_byte_lane_B.ddr_byte_lane_B_n_224\,
      Q => \pi_counter_read_val_reg[5]_0\(3),
      R => '0'
    );
\pi_counter_read_val_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]_1\,
      CE => '1',
      D => \ddr_byte_lane_B.ddr_byte_lane_B_n_223\,
      Q => \pi_counter_read_val_reg[5]_0\(4),
      R => '0'
    );
\pi_counter_read_val_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]_1\,
      CE => '1',
      D => \ddr_byte_lane_B.ddr_byte_lane_B_n_222\,
      Q => \pi_counter_read_val_reg[5]_0\(5),
      R => '0'
    );
\po_counter_read_val_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]_1\,
      CE => '1',
      D => \ddr_byte_lane_B.ddr_byte_lane_B_n_236\,
      Q => Q(0),
      R => '0'
    );
\po_counter_read_val_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]_1\,
      CE => '1',
      D => \ddr_byte_lane_B.ddr_byte_lane_B_n_235\,
      Q => Q(1),
      R => '0'
    );
\po_counter_read_val_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]_1\,
      CE => '1',
      D => \ddr_byte_lane_B.ddr_byte_lane_B_n_234\,
      Q => Q(2),
      R => '0'
    );
\po_counter_read_val_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]_1\,
      CE => '1',
      D => \ddr_byte_lane_B.ddr_byte_lane_B_n_233\,
      Q => Q(3),
      R => '0'
    );
\po_counter_read_val_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]_1\,
      CE => '1',
      D => \ddr_byte_lane_B.ddr_byte_lane_B_n_232\,
      Q => Q(4),
      R => '0'
    );
\po_counter_read_val_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]_1\,
      CE => '1',
      D => \ddr_byte_lane_B.ddr_byte_lane_B_n_231\,
      Q => Q(5),
      R => '0'
    );
\po_counter_read_val_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]_1\,
      CE => '1',
      D => \ddr_byte_lane_B.ddr_byte_lane_B_n_230\,
      Q => Q(6),
      R => '0'
    );
\po_counter_read_val_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]_1\,
      CE => '1',
      D => \ddr_byte_lane_B.ddr_byte_lane_B_n_229\,
      Q => Q(7),
      R => '0'
    );
\po_counter_read_val_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]_1\,
      CE => '1',
      D => \ddr_byte_lane_B.ddr_byte_lane_B_n_228\,
      Q => Q(8),
      R => '0'
    );
\rclk_delay_reg[10]_srl11\: unisim.vcomponents.SRL16E
     port map (
      A0 => '0',
      A1 => '1',
      A2 => '0',
      A3 => '1',
      CE => '1',
      CLK => \entry_cnt_reg[4]_1\,
      D => \rclk_delay_reg[11]_0\,
      Q => \rclk_delay_reg[10]_srl11_n_0\
    );
\rclk_delay_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]_1\,
      CE => '1',
      D => \rclk_delay_reg[10]_srl11_n_0\,
      Q => rclk_delay_11,
      R => '0'
    );
rst_out_reg: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => \entry_cnt_reg[4]_1\,
      CE => '1',
      CLR => SR(0),
      D => rst_out_reg_1,
      Q => \^rst_out_reg_0\
    );
rst_primitives_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \entry_cnt_reg[4]_1\,
      CE => '1',
      D => rst_primitives_reg_0,
      Q => \^rst_primitives\,
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \mig_mig_7series_v4_2_ddr_phy_4lanes__parameterized0\ is
  port (
    phy_ctl_mstr_empty : out STD_LOGIC;
    \_phy_ctl_full_p\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    ref_dll_lock_w : out STD_LOGIC_VECTOR ( 0 to 0 );
    \mcGo_w__0\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    \my_empty_reg[1]\ : out STD_LOGIC;
    \my_empty_reg[1]_0\ : out STD_LOGIC;
    mem_out : out STD_LOGIC_VECTOR ( 11 downto 0 );
    \rd_ptr_reg[3]\ : out STD_LOGIC_VECTOR ( 35 downto 0 );
    mem_dq_out : out STD_LOGIC_VECTOR ( 22 downto 0 );
    \po_counter_read_val_reg[0]_0\ : out STD_LOGIC;
    \po_counter_read_val_reg[1]_0\ : out STD_LOGIC;
    \po_counter_read_val_reg[2]_0\ : out STD_LOGIC;
    \po_counter_read_val_reg[3]_0\ : out STD_LOGIC;
    \po_counter_read_val_reg[4]_0\ : out STD_LOGIC;
    \po_counter_read_val_reg[5]_0\ : out STD_LOGIC;
    \po_counter_read_val_reg[6]_0\ : out STD_LOGIC;
    \po_counter_read_val_reg[7]_0\ : out STD_LOGIC;
    \po_counter_read_val_reg[8]_0\ : out STD_LOGIC;
    ddr_ck_out : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \my_empty_reg[1]_1\ : out STD_LOGIC;
    \rd_ptr_reg[3]_0\ : out STD_LOGIC_VECTOR ( 23 downto 0 );
    of_ctl_full_v : out STD_LOGIC_VECTOR ( 0 to 0 );
    \po_counter_read_val_reg[8]_1\ : in STD_LOGIC;
    \po_counter_read_val_reg[8]_2\ : in STD_LOGIC;
    \po_counter_read_val_reg[8]_3\ : in STD_LOGIC;
    \po_counter_read_val_reg[8]_4\ : in STD_LOGIC;
    freq_refclk : in STD_LOGIC;
    mem_refclk : in STD_LOGIC;
    sync_pulse : in STD_LOGIC;
    \wr_ptr_timing_reg[3]\ : in STD_LOGIC;
    \my_full_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
    \my_full_reg[3]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \my_full_reg[3]_1\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \my_full_reg[3]_2\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \my_full_reg[3]_3\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
    \po_counter_read_val_reg[8]_5\ : in STD_LOGIC;
    \po_counter_read_val_reg[8]_6\ : in STD_LOGIC;
    \po_counter_read_val_reg[8]_7\ : in STD_LOGIC;
    \po_counter_read_val_reg[8]_8\ : in STD_LOGIC;
    D1 : in STD_LOGIC_VECTOR ( 3 downto 0 );
    D3 : in STD_LOGIC_VECTOR ( 3 downto 0 );
    D4 : in STD_LOGIC_VECTOR ( 3 downto 0 );
    D5 : in STD_LOGIC_VECTOR ( 3 downto 0 );
    D6 : in STD_LOGIC_VECTOR ( 7 downto 0 );
    D7 : in STD_LOGIC_VECTOR ( 3 downto 0 );
    D8 : in STD_LOGIC_VECTOR ( 3 downto 0 );
    \rd_ptr_reg[3]_1\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
    phy_ctl_wr_i2 : in STD_LOGIC;
    pll_locked : in STD_LOGIC;
    phy_read_calib : in STD_LOGIC;
    phy_mc_ctl_full_r_reg : in STD_LOGIC;
    phy_write_calib : in STD_LOGIC;
    PHYCTLWD : in STD_LOGIC_VECTOR ( 10 downto 0 );
    RST0 : in STD_LOGIC;
    SR : in STD_LOGIC_VECTOR ( 0 to 0 );
    phy_cmd_wr_en : in STD_LOGIC;
    out_fifo : in STD_LOGIC;
    mc_cas_n : in STD_LOGIC_VECTOR ( 2 downto 0 );
    mc_we_n : in STD_LOGIC_VECTOR ( 1 downto 0 );
    out_fifo_0 : in STD_LOGIC;
    mc_ras_n : in STD_LOGIC_VECTOR ( 1 downto 0 );
    mc_cs_n : in STD_LOGIC_VECTOR ( 0 to 0 );
    mc_address : in STD_LOGIC_VECTOR ( 3 downto 0 );
    \out_fifo_i_47__8\ : in STD_LOGIC_VECTOR ( 12 downto 0 );
    mux_address : in STD_LOGIC_VECTOR ( 48 downto 0 );
    d_in : in STD_LOGIC_VECTOR ( 4 downto 0 );
    \po_counter_read_val_reg[0]_1\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    calib_sel : in STD_LOGIC_VECTOR ( 3 downto 0 );
    Q : in STD_LOGIC_VECTOR ( 8 downto 0 );
    \po_rdval_cnt_reg[8]\ : in STD_LOGIC_VECTOR ( 8 downto 0 );
    C_po_coarse_enable26_out : in STD_LOGIC;
    C_po_counter_read_en38_out : in STD_LOGIC;
    C_po_fine_enable23_out : in STD_LOGIC;
    C_po_fine_inc29_out : in STD_LOGIC;
    \my_empty_reg[7]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
    \my_empty_reg[7]_0\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \my_empty_reg[7]_1\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
    \my_empty_reg[7]_2\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
    D9 : in STD_LOGIC_VECTOR ( 3 downto 0 );
    out_fifo_i_39 : in STD_LOGIC_VECTOR ( 11 downto 0 );
    out_fifo_1 : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \mig_mig_7series_v4_2_ddr_phy_4lanes__parameterized0\ : entity is "mig_7series_v4_2_ddr_phy_4lanes";
end \mig_mig_7series_v4_2_ddr_phy_4lanes__parameterized0\;

architecture STRUCTURE of \mig_mig_7series_v4_2_ddr_phy_4lanes__parameterized0\ is
  signal A_pi_rst_div2 : STD_LOGIC;
  attribute async_reg : string;
  attribute async_reg of A_pi_rst_div2 : signal is "true";
  signal B_pi_rst_div2 : STD_LOGIC;
  attribute async_reg of B_pi_rst_div2 : signal is "true";
  signal B_rst_primitives : STD_LOGIC;
  signal C_of_full : STD_LOGIC;
  signal C_pi_rst_div2 : STD_LOGIC;
  attribute async_reg of C_pi_rst_div2 : signal is "true";
  signal C_po_counter_read_val : STD_LOGIC_VECTOR ( 8 downto 0 );
  signal D_of_full : STD_LOGIC;
  signal D_pi_rst_div2 : STD_LOGIC;
  attribute async_reg of D_pi_rst_div2 : signal is "true";
  signal D_po_counter_read_val : STD_LOGIC_VECTOR ( 8 downto 0 );
  signal \ddr_byte_lane_B.ddr_byte_lane_B_n_21\ : STD_LOGIC;
  signal \ddr_byte_lane_B.ddr_byte_lane_B_n_22\ : STD_LOGIC;
  signal \ddr_byte_lane_B.ddr_byte_lane_B_n_23\ : STD_LOGIC;
  signal \ddr_byte_lane_B.ddr_byte_lane_B_n_24\ : STD_LOGIC;
  signal \ddr_byte_lane_B.ddr_byte_lane_B_n_25\ : STD_LOGIC;
  signal \ddr_byte_lane_B.ddr_byte_lane_B_n_26\ : STD_LOGIC;
  signal \ddr_byte_lane_B.ddr_byte_lane_B_n_27\ : STD_LOGIC;
  signal \ddr_byte_lane_B.ddr_byte_lane_B_n_28\ : STD_LOGIC;
  signal \ddr_byte_lane_B.ddr_byte_lane_B_n_29\ : STD_LOGIC;
  signal ofifo_rst : STD_LOGIC;
  signal phaser_ctl_bus : STD_LOGIC_VECTOR ( 2 to 2 );
  signal phy_control_i_n_0 : STD_LOGIC;
  signal phy_control_i_n_10 : STD_LOGIC;
  signal phy_control_i_n_11 : STD_LOGIC;
  signal phy_control_i_n_14 : STD_LOGIC;
  signal phy_control_i_n_15 : STD_LOGIC;
  signal phy_control_i_n_16 : STD_LOGIC;
  signal phy_control_i_n_17 : STD_LOGIC;
  signal phy_control_i_n_18 : STD_LOGIC;
  signal phy_control_i_n_19 : STD_LOGIC;
  signal phy_control_i_n_20 : STD_LOGIC;
  signal phy_control_i_n_21 : STD_LOGIC;
  signal phy_control_i_n_22 : STD_LOGIC;
  signal phy_control_i_n_24 : STD_LOGIC;
  signal phy_control_i_n_25 : STD_LOGIC;
  signal phy_control_i_n_3 : STD_LOGIC;
  signal phy_control_i_n_4 : STD_LOGIC;
  signal phy_control_i_n_5 : STD_LOGIC;
  signal phy_control_i_n_6 : STD_LOGIC;
  signal phy_control_i_n_7 : STD_LOGIC;
  signal phy_control_i_n_8 : STD_LOGIC;
  signal phy_control_i_n_9 : STD_LOGIC;
  signal \^phy_ctl_mstr_empty\ : STD_LOGIC;
  signal phy_encalib : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \po_counter_read_val_w[1]_4\ : STD_LOGIC_VECTOR ( 8 downto 0 );
  signal rclk_delay_11 : STD_LOGIC;
  signal \rclk_delay_reg[10]_srl11_i_1__1_n_0\ : STD_LOGIC;
  signal \rclk_delay_reg[10]_srl11_n_0\ : STD_LOGIC;
  signal \^ref_dll_lock_w\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \rst_out_i_1__1_n_0\ : STD_LOGIC;
  signal rst_out_reg_n_0 : STD_LOGIC;
  signal rst_primitives : STD_LOGIC;
  signal \rst_primitives_i_1__1_n_0\ : STD_LOGIC;
  attribute BOX_TYPE : string;
  attribute BOX_TYPE of phaser_ref_i : label is "PRIMITIVE";
  attribute BOX_TYPE of phy_control_i : label is "PRIMITIVE";
  attribute srl_bus_name : string;
  attribute srl_bus_name of \rclk_delay_reg[10]_srl11\ : label is "\u_mig_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/rclk_delay_reg ";
  attribute srl_name : string;
  attribute srl_name of \rclk_delay_reg[10]_srl11\ : label is "\u_mig_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/rclk_delay_reg[10]_srl11 ";
begin
  phy_ctl_mstr_empty <= \^phy_ctl_mstr_empty\;
  ref_dll_lock_w(0) <= \^ref_dll_lock_w\(0);
B_rst_primitives_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \wr_ptr_timing_reg[3]\,
      CE => '1',
      D => rst_primitives,
      Q => B_rst_primitives,
      R => '0'
    );
\ddr_byte_lane_B.ddr_byte_lane_B\: entity work.\mig_mig_7series_v4_2_ddr_byte_lane__parameterized3\
     port map (
      B_rst_primitives => B_rst_primitives,
      COUNTERREADVAL(8 downto 0) => D_po_counter_read_val(8 downto 0),
      C_of_full => C_of_full,
      D(8) => \ddr_byte_lane_B.ddr_byte_lane_B_n_21\,
      D(7) => \ddr_byte_lane_B.ddr_byte_lane_B_n_22\,
      D(6) => \ddr_byte_lane_B.ddr_byte_lane_B_n_23\,
      D(5) => \ddr_byte_lane_B.ddr_byte_lane_B_n_24\,
      D(4) => \ddr_byte_lane_B.ddr_byte_lane_B_n_25\,
      D(3) => \ddr_byte_lane_B.ddr_byte_lane_B_n_26\,
      D(2) => \ddr_byte_lane_B.ddr_byte_lane_B_n_27\,
      D(1) => \ddr_byte_lane_B.ddr_byte_lane_B_n_28\,
      D(0) => \ddr_byte_lane_B.ddr_byte_lane_B_n_29\,
      D_of_full => D_of_full,
      OUTBURSTPENDING(0) => phy_control_i_n_24,
      PCENABLECALIB(1 downto 0) => phy_encalib(1 downto 0),
      SR(0) => ofifo_rst,
      calib_sel(1 downto 0) => calib_sel(1 downto 0),
      freq_refclk => freq_refclk,
      mc_cas_n(1) => mc_cas_n(2),
      mc_cas_n(0) => mc_cas_n(0),
      mc_cs_n(0) => mc_cs_n(0),
      mc_ras_n(1 downto 0) => mc_ras_n(1 downto 0),
      mc_we_n(1 downto 0) => mc_we_n(1 downto 0),
      mem_dq_out(5 downto 0) => mem_dq_out(5 downto 0),
      mem_out(11 downto 0) => mem_out(11 downto 0),
      mem_refclk => mem_refclk,
      \my_empty_reg[1]\ => \my_empty_reg[1]\,
      \my_full_reg[3]\ => \wr_ptr_timing_reg[3]\,
      \my_full_reg[3]_0\(3 downto 0) => \my_full_reg[3]\(3 downto 0),
      \my_full_reg[3]_1\(0) => \my_full_reg[3]_0\(0),
      \my_full_reg[3]_2\(1 downto 0) => \my_full_reg[3]_1\(1 downto 0),
      \my_full_reg[3]_3\(0) => \my_full_reg[3]_2\(0),
      \my_full_reg[3]_4\(3 downto 0) => \my_full_reg[3]_3\(3 downto 0),
      of_ctl_full_v(0) => of_ctl_full_v(0),
      out_fifo_0 => out_fifo_0,
      \out_fifo_i_47__8\(12 downto 0) => \out_fifo_i_47__8\(12 downto 0),
      phy_cmd_wr_en => phy_cmd_wr_en,
      \po_counter_read_val_reg[8]\ => \po_counter_read_val_reg[8]_1\,
      \po_counter_read_val_reg[8]_0\ => \po_counter_read_val_reg[8]_2\,
      \po_counter_read_val_reg[8]_1\ => \po_counter_read_val_reg[8]_3\,
      \po_counter_read_val_reg[8]_2\ => \po_counter_read_val_reg[8]_4\,
      \po_counter_read_val_reg[8]_3\(8 downto 0) => C_po_counter_read_val(8 downto 0),
      sync_pulse => sync_pulse
    );
\ddr_byte_lane_C.ddr_byte_lane_C\: entity work.\mig_mig_7series_v4_2_ddr_byte_lane__parameterized4\
     port map (
      B_rst_primitives => B_rst_primitives,
      B_rst_primitives_reg(8 downto 0) => C_po_counter_read_val(8 downto 0),
      C_of_full => C_of_full,
      C_po_coarse_enable26_out => C_po_coarse_enable26_out,
      C_po_counter_read_en38_out => C_po_counter_read_en38_out,
      C_po_fine_enable23_out => C_po_fine_enable23_out,
      C_po_fine_inc29_out => C_po_fine_inc29_out,
      D9(3 downto 0) => D9(3 downto 0),
      OUTBURSTPENDING(0) => phaser_ctl_bus(2),
      PCENABLECALIB(1 downto 0) => phy_encalib(1 downto 0),
      SR(0) => ofifo_rst,
      ddr_ck_out(1 downto 0) => ddr_ck_out(1 downto 0),
      freq_refclk => freq_refclk,
      mem_dq_out(5 downto 0) => mem_dq_out(11 downto 6),
      mem_refclk => mem_refclk,
      \my_empty_reg[1]\ => \my_empty_reg[1]_1\,
      \my_empty_reg[7]\(3 downto 0) => \my_empty_reg[7]\(3 downto 0),
      \my_empty_reg[7]_0\(7 downto 0) => \my_empty_reg[7]_0\(7 downto 0),
      \my_empty_reg[7]_1\(3 downto 0) => \my_empty_reg[7]_1\(3 downto 0),
      \my_empty_reg[7]_2\(3 downto 0) => \my_empty_reg[7]_2\(3 downto 0),
      phy_cmd_wr_en => phy_cmd_wr_en,
      phy_dout(23) => mux_address(43),
      phy_dout(22) => mux_address(31),
      phy_dout(21) => mux_address(18),
      phy_dout(20) => mux_address(6),
      phy_dout(19) => mux_address(39),
      phy_dout(18) => mux_address(27),
      phy_dout(17) => mux_address(14),
      phy_dout(16) => mux_address(2),
      phy_dout(15 downto 4) => out_fifo_i_39(11 downto 0),
      phy_dout(3) => mux_address(45),
      phy_dout(2) => mux_address(33),
      phy_dout(1) => mux_address(20),
      phy_dout(0) => mux_address(8),
      \rd_ptr_reg[3]\(23 downto 0) => \rd_ptr_reg[3]_0\(23 downto 0),
      sync_pulse => sync_pulse,
      \wr_ptr_timing_reg[3]\ => \wr_ptr_timing_reg[3]\
    );
\ddr_byte_lane_D.ddr_byte_lane_D\: entity work.\mig_mig_7series_v4_2_ddr_byte_lane__parameterized5\
     port map (
      B_rst_primitives => B_rst_primitives,
      COUNTERREADVAL(8 downto 0) => D_po_counter_read_val(8 downto 0),
      D1(3 downto 0) => D1(3 downto 0),
      D3(3 downto 0) => D3(3 downto 0),
      D4(3 downto 0) => D4(3 downto 0),
      D5(3 downto 0) => D5(3 downto 0),
      D6(7 downto 0) => D6(7 downto 0),
      D7(3 downto 0) => D7(3 downto 0),
      D8(3 downto 0) => D8(3 downto 0),
      D_of_full => D_of_full,
      OUTBURSTPENDING(0) => phy_control_i_n_22,
      PCENABLECALIB(1 downto 0) => phy_encalib(1 downto 0),
      SR(0) => ofifo_rst,
      d_in(41) => mux_address(46),
      d_in(40) => mux_address(34),
      d_in(39) => mux_address(21),
      d_in(38) => mux_address(9),
      d_in(37) => mux_address(38),
      d_in(36) => mux_address(26),
      d_in(35) => mux_address(13),
      d_in(34) => mux_address(1),
      d_in(33) => mux_address(42),
      d_in(32) => mux_address(30),
      d_in(31) => mux_address(17),
      d_in(30) => mux_address(5),
      d_in(29) => mux_address(37),
      d_in(28) => mux_address(25),
      d_in(27) => mux_address(12),
      d_in(26) => mux_address(0),
      d_in(25) => mux_address(48),
      d_in(24) => mux_address(36),
      d_in(23) => mux_address(23),
      d_in(22) => mux_address(11),
      d_in(21) => mux_address(40),
      d_in(20) => mux_address(28),
      d_in(19) => mux_address(15),
      d_in(18) => mux_address(3),
      d_in(17 downto 16) => d_in(4 downto 3),
      d_in(15) => mux_address(24),
      d_in(14) => d_in(2),
      d_in(13) => mux_address(41),
      d_in(12) => mux_address(29),
      d_in(11) => mux_address(16),
      d_in(10) => mux_address(4),
      d_in(9) => mux_address(47),
      d_in(8) => mux_address(35),
      d_in(7) => mux_address(22),
      d_in(6) => mux_address(10),
      d_in(5 downto 4) => d_in(1 downto 0),
      d_in(3) => mux_address(44),
      d_in(2) => mux_address(32),
      d_in(1) => mux_address(19),
      d_in(0) => mux_address(7),
      freq_refclk => freq_refclk,
      mc_address(3 downto 0) => mc_address(3 downto 0),
      mc_cas_n(0) => mc_cas_n(1),
      mem_dq_out(10 downto 0) => mem_dq_out(22 downto 12),
      mem_refclk => mem_refclk,
      \my_empty_reg[1]\ => \my_empty_reg[1]_0\,
      out_fifo_0 => out_fifo,
      out_fifo_1 => out_fifo_0,
      out_fifo_2 => out_fifo_1,
      phy_cmd_wr_en => phy_cmd_wr_en,
      \po_counter_read_val_reg[8]\ => \po_counter_read_val_reg[8]_5\,
      \po_counter_read_val_reg[8]_0\ => \po_counter_read_val_reg[8]_6\,
      \po_counter_read_val_reg[8]_1\ => \po_counter_read_val_reg[8]_7\,
      \po_counter_read_val_reg[8]_2\ => \po_counter_read_val_reg[8]_8\,
      \rd_ptr_reg[3]\(35 downto 0) => \rd_ptr_reg[3]\(35 downto 0),
      \rd_ptr_reg[3]_0\(3 downto 0) => \rd_ptr_reg[3]_1\(3 downto 0),
      sync_pulse => sync_pulse,
      \wr_ptr_timing_reg[3]\ => \wr_ptr_timing_reg[3]\
    );
i_0: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => B_pi_rst_div2
    );
i_1: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => C_pi_rst_div2
    );
i_2: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => D_pi_rst_div2
    );
i_3: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => A_pi_rst_div2
    );
mcGo_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \wr_ptr_timing_reg[3]\,
      CE => '1',
      D => rst_out_reg_n_0,
      Q => \mcGo_w__0\(0),
      R => '0'
    );
phaser_ref_i: unisim.vcomponents.PHASER_REF
    generic map(
      IS_PWRDWN_INVERTED => '0',
      IS_RST_INVERTED => '0'
    )
        port map (
      CLKIN => freq_refclk,
      LOCKED => \^ref_dll_lock_w\(0),
      PWRDWN => '0',
      RST => RST0
    );
phy_control_i: unisim.vcomponents.PHY_CONTROL
    generic map(
      AO_TOGGLE => 1,
      AO_WRLVL_EN => B"0000",
      BURST_MODE => "TRUE",
      CLK_RATIO => 4,
      CMD_OFFSET => 8,
      CO_DURATION => 1,
      DATA_CTL_A_N => "FALSE",
      DATA_CTL_B_N => "FALSE",
      DATA_CTL_C_N => "FALSE",
      DATA_CTL_D_N => "FALSE",
      DISABLE_SEQ_MATCH => "TRUE",
      DI_DURATION => 1,
      DO_DURATION => 1,
      EVENTS_DELAY => 18,
      FOUR_WINDOW_CLOCKS => 63,
      MULTI_REGION => "TRUE",
      PHY_COUNT_ENABLE => "FALSE",
      RD_CMD_OFFSET_0 => 10,
      RD_CMD_OFFSET_1 => 10,
      RD_CMD_OFFSET_2 => 10,
      RD_CMD_OFFSET_3 => 10,
      RD_DURATION_0 => 6,
      RD_DURATION_1 => 6,
      RD_DURATION_2 => 6,
      RD_DURATION_3 => 6,
      SYNC_MODE => "FALSE",
      WR_CMD_OFFSET_0 => 8,
      WR_CMD_OFFSET_1 => 8,
      WR_CMD_OFFSET_2 => 8,
      WR_CMD_OFFSET_3 => 8,
      WR_DURATION_0 => 7,
      WR_DURATION_1 => 7,
      WR_DURATION_2 => 7,
      WR_DURATION_3 => 7
    )
        port map (
      AUXOUTPUT(3) => phy_control_i_n_14,
      AUXOUTPUT(2) => phy_control_i_n_15,
      AUXOUTPUT(1) => phy_control_i_n_16,
      AUXOUTPUT(0) => phy_control_i_n_17,
      INBURSTPENDING(3) => phy_control_i_n_18,
      INBURSTPENDING(2) => phy_control_i_n_19,
      INBURSTPENDING(1) => phy_control_i_n_20,
      INBURSTPENDING(0) => phy_control_i_n_21,
      INRANKA(1) => phy_control_i_n_4,
      INRANKA(0) => phy_control_i_n_5,
      INRANKB(1) => phy_control_i_n_6,
      INRANKB(0) => phy_control_i_n_7,
      INRANKC(1) => phy_control_i_n_8,
      INRANKC(0) => phy_control_i_n_9,
      INRANKD(1) => phy_control_i_n_10,
      INRANKD(0) => phy_control_i_n_11,
      MEMREFCLK => mem_refclk,
      OUTBURSTPENDING(3) => phy_control_i_n_22,
      OUTBURSTPENDING(2) => phaser_ctl_bus(2),
      OUTBURSTPENDING(1) => phy_control_i_n_24,
      OUTBURSTPENDING(0) => phy_control_i_n_25,
      PCENABLECALIB(1 downto 0) => phy_encalib(1 downto 0),
      PHYCLK => \wr_ptr_timing_reg[3]\,
      PHYCTLALMOSTFULL => phy_control_i_n_0,
      PHYCTLEMPTY => \^phy_ctl_mstr_empty\,
      PHYCTLFULL => \_phy_ctl_full_p\(0),
      PHYCTLMSTREMPTY => \^phy_ctl_mstr_empty\,
      PHYCTLREADY => phy_control_i_n_3,
      PHYCTLWD(31 downto 25) => B"0000001",
      PHYCTLWD(24 downto 17) => PHYCTLWD(10 downto 3),
      PHYCTLWD(16 downto 3) => B"00000000000000",
      PHYCTLWD(2 downto 0) => PHYCTLWD(2 downto 0),
      PHYCTLWRENABLE => phy_ctl_wr_i2,
      PLLLOCK => pll_locked,
      READCALIBENABLE => phy_read_calib,
      REFDLLLOCK => \^ref_dll_lock_w\(0),
      RESET => phy_mc_ctl_full_r_reg,
      SYNCIN => sync_pulse,
      WRITECALIBENABLE => phy_write_calib
    );
\po_counter_read_val_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_ptr_timing_reg[3]\,
      CE => '1',
      D => \ddr_byte_lane_B.ddr_byte_lane_B_n_29\,
      Q => \po_counter_read_val_w[1]_4\(0),
      R => \po_counter_read_val_reg[0]_1\(0)
    );
\po_counter_read_val_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_ptr_timing_reg[3]\,
      CE => '1',
      D => \ddr_byte_lane_B.ddr_byte_lane_B_n_28\,
      Q => \po_counter_read_val_w[1]_4\(1),
      R => \po_counter_read_val_reg[0]_1\(0)
    );
\po_counter_read_val_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_ptr_timing_reg[3]\,
      CE => '1',
      D => \ddr_byte_lane_B.ddr_byte_lane_B_n_27\,
      Q => \po_counter_read_val_w[1]_4\(2),
      R => \po_counter_read_val_reg[0]_1\(0)
    );
\po_counter_read_val_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_ptr_timing_reg[3]\,
      CE => '1',
      D => \ddr_byte_lane_B.ddr_byte_lane_B_n_26\,
      Q => \po_counter_read_val_w[1]_4\(3),
      R => \po_counter_read_val_reg[0]_1\(0)
    );
\po_counter_read_val_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_ptr_timing_reg[3]\,
      CE => '1',
      D => \ddr_byte_lane_B.ddr_byte_lane_B_n_25\,
      Q => \po_counter_read_val_w[1]_4\(4),
      R => \po_counter_read_val_reg[0]_1\(0)
    );
\po_counter_read_val_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_ptr_timing_reg[3]\,
      CE => '1',
      D => \ddr_byte_lane_B.ddr_byte_lane_B_n_24\,
      Q => \po_counter_read_val_w[1]_4\(5),
      R => \po_counter_read_val_reg[0]_1\(0)
    );
\po_counter_read_val_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_ptr_timing_reg[3]\,
      CE => '1',
      D => \ddr_byte_lane_B.ddr_byte_lane_B_n_23\,
      Q => \po_counter_read_val_w[1]_4\(6),
      R => \po_counter_read_val_reg[0]_1\(0)
    );
\po_counter_read_val_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_ptr_timing_reg[3]\,
      CE => '1',
      D => \ddr_byte_lane_B.ddr_byte_lane_B_n_22\,
      Q => \po_counter_read_val_w[1]_4\(7),
      R => \po_counter_read_val_reg[0]_1\(0)
    );
\po_counter_read_val_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_ptr_timing_reg[3]\,
      CE => '1',
      D => \ddr_byte_lane_B.ddr_byte_lane_B_n_21\,
      Q => \po_counter_read_val_w[1]_4\(8),
      R => \po_counter_read_val_reg[0]_1\(0)
    );
\po_rdval_cnt[0]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"30BB3088"
    )
        port map (
      I0 => \po_counter_read_val_w[1]_4\(0),
      I1 => calib_sel(2),
      I2 => Q(0),
      I3 => calib_sel(3),
      I4 => \po_rdval_cnt_reg[8]\(0),
      O => \po_counter_read_val_reg[0]_0\
    );
\po_rdval_cnt[1]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"30BB3088"
    )
        port map (
      I0 => \po_counter_read_val_w[1]_4\(1),
      I1 => calib_sel(2),
      I2 => Q(1),
      I3 => calib_sel(3),
      I4 => \po_rdval_cnt_reg[8]\(1),
      O => \po_counter_read_val_reg[1]_0\
    );
\po_rdval_cnt[2]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"30BB3088"
    )
        port map (
      I0 => \po_counter_read_val_w[1]_4\(2),
      I1 => calib_sel(2),
      I2 => Q(2),
      I3 => calib_sel(3),
      I4 => \po_rdval_cnt_reg[8]\(2),
      O => \po_counter_read_val_reg[2]_0\
    );
\po_rdval_cnt[3]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"30BB3088"
    )
        port map (
      I0 => \po_counter_read_val_w[1]_4\(3),
      I1 => calib_sel(2),
      I2 => Q(3),
      I3 => calib_sel(3),
      I4 => \po_rdval_cnt_reg[8]\(3),
      O => \po_counter_read_val_reg[3]_0\
    );
\po_rdval_cnt[4]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"30BB3088"
    )
        port map (
      I0 => \po_counter_read_val_w[1]_4\(4),
      I1 => calib_sel(2),
      I2 => Q(4),
      I3 => calib_sel(3),
      I4 => \po_rdval_cnt_reg[8]\(4),
      O => \po_counter_read_val_reg[4]_0\
    );
\po_rdval_cnt[5]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"30BB3088"
    )
        port map (
      I0 => \po_counter_read_val_w[1]_4\(5),
      I1 => calib_sel(2),
      I2 => Q(5),
      I3 => calib_sel(3),
      I4 => \po_rdval_cnt_reg[8]\(5),
      O => \po_counter_read_val_reg[5]_0\
    );
\po_rdval_cnt[6]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"30BB3088"
    )
        port map (
      I0 => \po_counter_read_val_w[1]_4\(6),
      I1 => calib_sel(2),
      I2 => Q(6),
      I3 => calib_sel(3),
      I4 => \po_rdval_cnt_reg[8]\(6),
      O => \po_counter_read_val_reg[6]_0\
    );
\po_rdval_cnt[7]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"30BB3088"
    )
        port map (
      I0 => \po_counter_read_val_w[1]_4\(7),
      I1 => calib_sel(2),
      I2 => Q(7),
      I3 => calib_sel(3),
      I4 => \po_rdval_cnt_reg[8]\(7),
      O => \po_counter_read_val_reg[7]_0\
    );
\po_rdval_cnt[8]_i_4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"30BB3088"
    )
        port map (
      I0 => \po_counter_read_val_w[1]_4\(8),
      I1 => calib_sel(2),
      I2 => Q(8),
      I3 => calib_sel(3),
      I4 => \po_rdval_cnt_reg[8]\(8),
      O => \po_counter_read_val_reg[8]_0\
    );
\rclk_delay_reg[10]_srl11\: unisim.vcomponents.SRL16E
     port map (
      A0 => '0',
      A1 => '1',
      A2 => '0',
      A3 => '1',
      CE => '1',
      CLK => \wr_ptr_timing_reg[3]\,
      D => \rclk_delay_reg[10]_srl11_i_1__1_n_0\,
      Q => \rclk_delay_reg[10]_srl11_n_0\
    );
\rclk_delay_reg[10]_srl11_i_1__1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => rst_primitives,
      O => \rclk_delay_reg[10]_srl11_i_1__1_n_0\
    );
\rclk_delay_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => \wr_ptr_timing_reg[3]\,
      CE => '1',
      D => \rclk_delay_reg[10]_srl11_n_0\,
      Q => rclk_delay_11,
      R => '0'
    );
\rst_out_i_1__1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => rclk_delay_11,
      I1 => rst_out_reg_n_0,
      O => \rst_out_i_1__1_n_0\
    );
rst_out_reg: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => \wr_ptr_timing_reg[3]\,
      CE => '1',
      CLR => SR(0),
      D => \rst_out_i_1__1_n_0\,
      Q => rst_out_reg_n_0
    );
\rst_primitives_i_1__1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => phy_control_i_n_3,
      O => \rst_primitives_i_1__1_n_0\
    );
rst_primitives_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \wr_ptr_timing_reg[3]\,
      CE => '1',
      D => \rst_primitives_i_1__1_n_0\,
      Q => rst_primitives,
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mig_mig_7series_v4_2_rank_mach is
  port (
    \inhbt_act_faw.act_delayed\ : out STD_LOGIC;
    maint_sre_r : out STD_LOGIC;
    \maintenance_request.upd_last_master_r\ : out STD_LOGIC;
    \maintenance_request.new_maint_rank_r\ : out STD_LOGIC;
    maint_req_r : out STD_LOGIC;
    \periodic_read_request.upd_last_master_r\ : out STD_LOGIC;
    app_ref_ack : out STD_LOGIC;
    app_zq_ack : out STD_LOGIC;
    \periodic_rd_generation.read_this_rank_r\ : out STD_LOGIC;
    inhbt_act_faw_r : out STD_LOGIC;
    \zq_cntrl.zq_request_logic.zq_request_r\ : out STD_LOGIC;
    maint_srx_r : out STD_LOGIC;
    \sr_cntrl.sre_request_logic.sre_request_r\ : out STD_LOGIC;
    maint_zq_r : out STD_LOGIC;
    \periodic_rd_generation.periodic_rd_request_r\ : out STD_LOGIC;
    periodic_rd_r : out STD_LOGIC;
    app_ref_r : out STD_LOGIC;
    app_zq_r : out STD_LOGIC;
    \periodic_read_request.periodic_rd_r_cnt\ : out STD_LOGIC;
    \periodic_read_request.periodic_rd_grant_r\ : out STD_LOGIC;
    app_sr_active : out STD_LOGIC;
    maint_ref_zq_wip : out STD_LOGIC;
    \periodic_rd_generation.periodic_rd_cntr1_r\ : out STD_LOGIC;
    \refresh_generation.refresh_bank_r\ : out STD_LOGIC;
    Q : out STD_LOGIC_VECTOR ( 4 downto 0 );
    \refresh_timer.refresh_timer_r_reg[5]\ : out STD_LOGIC;
    \refresh_timer.refresh_timer_r_reg[1]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \init_calib_complete_reg_rep__26\ : out STD_LOGIC;
    mc_cke_ns : out STD_LOGIC_VECTOR ( 0 to 0 );
    \grant_r_reg[2]\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
    \last_master_r_reg[2]\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
    S : out STD_LOGIC_VECTOR ( 3 downto 0 );
    \zq_cntrl.zq_timer.zq_timer_r_reg[7]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
    \zq_cntrl.zq_timer.zq_timer_r_reg[11]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
    \zq_cntrl.zq_timer.zq_timer_r_reg[15]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
    \zq_cntrl.zq_timer.zq_timer_r_reg[19]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
    \wtr_timer.wtr_cnt_r_reg[1]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \maintenance_request.maint_srx_r_lcl_reg\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    \maintenance_request.maint_sre_r_lcl_reg\ : out STD_LOGIC;
    \periodic_rd_generation.periodic_rd_timer_r_reg[2]\ : out STD_LOGIC;
    \inhbt_act_faw.faw_cnt_r_reg[2]\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
    \rtw_timer.rtw_cnt_r_reg[1]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    act_this_rank : in STD_LOGIC;
    \last_master_r_reg[2]_0\ : in STD_LOGIC;
    \maintenance_request.upd_last_master_r_reg\ : in STD_LOGIC;
    \periodic_rd_generation.read_this_rank\ : in STD_LOGIC;
    \zq_cntrl.zq_request_logic.zq_request_r_reg\ : in STD_LOGIC;
    \zq_cntrl.zq_request_logic.zq_request_r_reg_0\ : in STD_LOGIC;
    SR : in STD_LOGIC_VECTOR ( 0 to 0 );
    \sr_cntrl.sre_request_logic.sre_request_r_reg\ : in STD_LOGIC;
    \periodic_rd_generation.periodic_rd_request_r_reg\ : in STD_LOGIC;
    \periodic_read_request.periodic_rd_r_lcl_reg\ : in STD_LOGIC;
    \periodic_read_request.periodic_rd_r_lcl_reg_0\ : in STD_LOGIC;
    app_ref_r_reg : in STD_LOGIC;
    app_zq_r_reg : in STD_LOGIC;
    \periodic_read_request.periodic_rd_r_cnt_reg\ : in STD_LOGIC;
    \periodic_read_request.periodic_rd_r_cnt_reg_0\ : in STD_LOGIC;
    \periodic_read_request.periodic_rd_grant_r_reg[0]\ : in STD_LOGIC;
    app_sr_active_r_reg : in STD_LOGIC;
    maint_ref_zq_wip_r_reg : in STD_LOGIC;
    \periodic_rd_generation.periodic_rd_cntr1_r_reg\ : in STD_LOGIC;
    \periodic_rd_generation.periodic_rd_cntr1_r_reg_0\ : in STD_LOGIC;
    O : in STD_LOGIC_VECTOR ( 3 downto 0 );
    \zq_cntrl.zq_timer.zq_timer_r_reg[7]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
    \zq_cntrl.zq_timer.zq_timer_r_reg[11]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
    \zq_cntrl.zq_timer.zq_timer_r_reg[15]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
    \zq_cntrl.zq_timer.zq_timer_r_reg[19]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
    \periodic_rd_generation.periodic_rd_timer_r_reg[2]_0\ : in STD_LOGIC;
    \periodic_rd_generation.periodic_rd_timer_r_reg[2]_1\ : in STD_LOGIC;
    \grant_r_reg[0]\ : in STD_LOGIC;
    app_ref_req : in STD_LOGIC;
    insert_maint_r1 : in STD_LOGIC;
    cke_r : in STD_LOGIC;
    app_sr_req : in STD_LOGIC;
    \last_master_r_reg[2]_1\ : in STD_LOGIC;
    D : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \grant_r_reg[2]_0\ : in STD_LOGIC;
    \wtr_timer.wtr_cnt_r_reg[1]_0\ : in STD_LOGIC;
    \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[0]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[0]_0\ : in STD_LOGIC;
    \inhbt_act_faw.inhbt_act_faw_r_reg\ : in STD_LOGIC;
    \inhbt_act_faw.inhbt_act_faw_r_reg_0\ : in STD_LOGIC;
    \inhbt_act_faw.faw_cnt_r_reg[2]_0\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
    \wtr_timer.wtr_cnt_r_reg[0]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \rtw_timer.rtw_cnt_r_reg[1]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    SS : in STD_LOGIC_VECTOR ( 0 to 0 );
    \maint_prescaler.maint_prescaler_r_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \refresh_timer.refresh_timer_r_reg[5]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \refresh_timer.refresh_timer_r_reg[1]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of mig_mig_7series_v4_2_rank_mach : entity is "mig_7series_v4_2_rank_mach";
end mig_mig_7series_v4_2_rank_mach;

architecture STRUCTURE of mig_mig_7series_v4_2_rank_mach is
  signal maint_prescaler_tick_r : STD_LOGIC;
  signal \^periodic_rd_generation.periodic_rd_request_r\ : STD_LOGIC;
  signal rank_common0_n_24 : STD_LOGIC;
  signal \^refresh_generation.refresh_bank_r\ : STD_LOGIC;
begin
  \periodic_rd_generation.periodic_rd_request_r\ <= \^periodic_rd_generation.periodic_rd_request_r\;
  \refresh_generation.refresh_bank_r\ <= \^refresh_generation.refresh_bank_r\;
\rank_cntrl[0].rank_cntrl0\: entity work.mig_mig_7series_v4_2_rank_cntrl
     port map (
      SR(0) => SR(0),
      act_this_rank => act_this_rank,
      \inhbt_act_faw.act_delayed\ => \inhbt_act_faw.act_delayed\,
      \inhbt_act_faw.faw_cnt_r_reg[2]_0\(2 downto 0) => \inhbt_act_faw.faw_cnt_r_reg[2]\(2 downto 0),
      \inhbt_act_faw.faw_cnt_r_reg[2]_1\(2 downto 0) => \inhbt_act_faw.faw_cnt_r_reg[2]_0\(2 downto 0),
      \inhbt_act_faw.inhbt_act_faw_r_reg_0\ => \inhbt_act_faw.inhbt_act_faw_r_reg\,
      \inhbt_act_faw.inhbt_act_faw_r_reg_1\ => \inhbt_act_faw.inhbt_act_faw_r_reg_0\,
      inhbt_act_faw_r => inhbt_act_faw_r,
      maint_prescaler_tick_r => maint_prescaler_tick_r,
      \periodic_rd_generation.periodic_rd_cntr1_r\ => \periodic_rd_generation.periodic_rd_cntr1_r\,
      \periodic_rd_generation.periodic_rd_cntr1_r_reg_0\ => \periodic_rd_generation.periodic_rd_cntr1_r_reg\,
      \periodic_rd_generation.periodic_rd_cntr1_r_reg_1\ => \periodic_rd_generation.periodic_rd_cntr1_r_reg_0\,
      \periodic_rd_generation.periodic_rd_request_r\ => \^periodic_rd_generation.periodic_rd_request_r\,
      \periodic_rd_generation.periodic_rd_request_r_reg_0\ => \last_master_r_reg[2]_0\,
      \periodic_rd_generation.periodic_rd_request_r_reg_1\ => \periodic_rd_generation.periodic_rd_request_r_reg\,
      \periodic_rd_generation.periodic_rd_timer_r_reg[2]_0\ => \periodic_rd_generation.periodic_rd_timer_r_reg[2]\,
      \periodic_rd_generation.periodic_rd_timer_r_reg[2]_1\ => \periodic_rd_generation.periodic_rd_timer_r_reg[2]_0\,
      \periodic_rd_generation.periodic_rd_timer_r_reg[2]_2\ => \periodic_rd_generation.periodic_rd_timer_r_reg[2]_1\,
      \periodic_rd_generation.read_this_rank\ => \periodic_rd_generation.read_this_rank\,
      \periodic_rd_generation.read_this_rank_r\ => \periodic_rd_generation.read_this_rank_r\,
      \refresh_generation.refresh_bank_r_reg[0]_0\ => \^refresh_generation.refresh_bank_r\,
      \refresh_generation.refresh_bank_r_reg[0]_1\ => rank_common0_n_24,
      \rtw_timer.rtw_cnt_r_reg[1]_0\(1 downto 0) => \rtw_timer.rtw_cnt_r_reg[1]\(1 downto 0),
      \rtw_timer.rtw_cnt_r_reg[1]_1\(1 downto 0) => \rtw_timer.rtw_cnt_r_reg[1]_0\(1 downto 0),
      \wtr_timer.wtr_cnt_r_reg[0]_0\(0) => \wtr_timer.wtr_cnt_r_reg[0]\(0),
      \wtr_timer.wtr_cnt_r_reg[1]_0\(1 downto 0) => \wtr_timer.wtr_cnt_r_reg[1]\(1 downto 0),
      \wtr_timer.wtr_cnt_r_reg[1]_1\ => \wtr_timer.wtr_cnt_r_reg[1]_0\,
      \wtr_timer.wtr_cnt_r_reg[1]_2\ => \last_master_r_reg[2]_1\
    );
rank_common0: entity work.mig_mig_7series_v4_2_rank_common
     port map (
      D(1 downto 0) => D(1 downto 0),
      O(3 downto 0) => O(3 downto 0),
      Q(4 downto 0) => Q(4 downto 0),
      S(3 downto 0) => S(3 downto 0),
      SR(0) => SR(0),
      SS(0) => SS(0),
      app_ref_ack => app_ref_ack,
      app_ref_r => app_ref_r,
      app_ref_r_reg_0 => app_ref_r_reg,
      app_ref_req => app_ref_req,
      app_sr_active => app_sr_active,
      app_sr_active_r_reg_0 => app_sr_active_r_reg,
      app_sr_req => app_sr_req,
      app_zq_ack => app_zq_ack,
      app_zq_r => app_zq_r,
      app_zq_r_reg_0 => app_zq_r_reg,
      cke_r => cke_r,
      \grant_r_reg[0]\ => \grant_r_reg[0]\,
      \grant_r_reg[0]_0\ => \^refresh_generation.refresh_bank_r\,
      \grant_r_reg[2]\(2 downto 0) => \grant_r_reg[2]\(2 downto 0),
      \grant_r_reg[2]_0\ => \grant_r_reg[2]_0\,
      \init_calib_complete_reg_rep__26\ => rank_common0_n_24,
      \init_calib_complete_reg_rep__26_0\ => \init_calib_complete_reg_rep__26\,
      insert_maint_r1 => insert_maint_r1,
      \last_master_r_reg[2]\(2 downto 0) => \last_master_r_reg[2]\(2 downto 0),
      \last_master_r_reg[2]_0\ => \last_master_r_reg[2]_0\,
      \last_master_r_reg[2]_1\ => \last_master_r_reg[2]_1\,
      \maint_prescaler.maint_prescaler_r_reg[1]_0\(0) => \maint_prescaler.maint_prescaler_r_reg[1]\(0),
      maint_prescaler_tick_r => maint_prescaler_tick_r,
      maint_ref_zq_wip => maint_ref_zq_wip,
      maint_ref_zq_wip_r_reg_0 => maint_ref_zq_wip_r_reg,
      maint_req_r => maint_req_r,
      \maintenance_request.maint_sre_r_lcl_reg_0\ => maint_sre_r,
      \maintenance_request.maint_sre_r_lcl_reg_1\ => \maintenance_request.maint_sre_r_lcl_reg\,
      \maintenance_request.maint_srx_r_lcl_reg_0\ => maint_srx_r,
      \maintenance_request.maint_srx_r_lcl_reg_1\(0) => \maintenance_request.maint_srx_r_lcl_reg\(0),
      \maintenance_request.maint_zq_r_lcl_reg_0\ => maint_zq_r,
      \maintenance_request.new_maint_rank_r_reg_0\ => \maintenance_request.new_maint_rank_r\,
      \maintenance_request.upd_last_master_r_reg_0\ => \maintenance_request.upd_last_master_r\,
      \maintenance_request.upd_last_master_r_reg_1\ => \maintenance_request.upd_last_master_r_reg\,
      mc_cke_ns(0) => mc_cke_ns(0),
      \periodic_rd_generation.periodic_rd_request_r\ => \^periodic_rd_generation.periodic_rd_request_r\,
      periodic_rd_r => periodic_rd_r,
      \periodic_read_request.periodic_rd_grant_r\ => \periodic_read_request.periodic_rd_grant_r\,
      \periodic_read_request.periodic_rd_grant_r_reg[0]_0\ => \periodic_read_request.periodic_rd_grant_r_reg[0]\,
      \periodic_read_request.periodic_rd_r_cnt\ => \periodic_read_request.periodic_rd_r_cnt\,
      \periodic_read_request.periodic_rd_r_cnt_reg_0\ => \periodic_read_request.periodic_rd_r_cnt_reg\,
      \periodic_read_request.periodic_rd_r_cnt_reg_1\ => \periodic_read_request.periodic_rd_r_cnt_reg_0\,
      \periodic_read_request.periodic_rd_r_lcl_reg_0\ => \periodic_read_request.periodic_rd_r_lcl_reg\,
      \periodic_read_request.periodic_rd_r_lcl_reg_1\ => \periodic_read_request.periodic_rd_r_lcl_reg_0\,
      \periodic_read_request.upd_last_master_r\ => \periodic_read_request.upd_last_master_r\,
      \refresh_timer.refresh_timer_r_reg[1]_0\(1 downto 0) => \refresh_timer.refresh_timer_r_reg[1]\(1 downto 0),
      \refresh_timer.refresh_timer_r_reg[1]_1\(0) => \refresh_timer.refresh_timer_r_reg[1]_0\(0),
      \refresh_timer.refresh_timer_r_reg[5]_0\ => \refresh_timer.refresh_timer_r_reg[5]\,
      \refresh_timer.refresh_timer_r_reg[5]_1\(0) => \refresh_timer.refresh_timer_r_reg[5]_0\(0),
      \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[0]\(0) => \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[0]\(0),
      \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[0]_0\ => \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[0]_0\,
      \sr_cntrl.sre_request_logic.sre_request_r_reg_0\ => \sr_cntrl.sre_request_logic.sre_request_r\,
      \sr_cntrl.sre_request_logic.sre_request_r_reg_1\ => \sr_cntrl.sre_request_logic.sre_request_r_reg\,
      \zq_cntrl.zq_request_logic.zq_request_r_reg_0\ => \zq_cntrl.zq_request_logic.zq_request_r\,
      \zq_cntrl.zq_request_logic.zq_request_r_reg_1\ => \zq_cntrl.zq_request_logic.zq_request_r_reg\,
      \zq_cntrl.zq_request_logic.zq_request_r_reg_2\ => \zq_cntrl.zq_request_logic.zq_request_r_reg_0\,
      \zq_cntrl.zq_timer.zq_timer_r_reg[11]_0\(3 downto 0) => \zq_cntrl.zq_timer.zq_timer_r_reg[11]\(3 downto 0),
      \zq_cntrl.zq_timer.zq_timer_r_reg[11]_1\(3 downto 0) => \zq_cntrl.zq_timer.zq_timer_r_reg[11]_0\(3 downto 0),
      \zq_cntrl.zq_timer.zq_timer_r_reg[15]_0\(3 downto 0) => \zq_cntrl.zq_timer.zq_timer_r_reg[15]\(3 downto 0),
      \zq_cntrl.zq_timer.zq_timer_r_reg[15]_1\(3 downto 0) => \zq_cntrl.zq_timer.zq_timer_r_reg[15]_0\(3 downto 0),
      \zq_cntrl.zq_timer.zq_timer_r_reg[19]_0\(3 downto 0) => \zq_cntrl.zq_timer.zq_timer_r_reg[19]\(3 downto 0),
      \zq_cntrl.zq_timer.zq_timer_r_reg[19]_1\(3 downto 0) => \zq_cntrl.zq_timer.zq_timer_r_reg[19]_0\(3 downto 0),
      \zq_cntrl.zq_timer.zq_timer_r_reg[7]_0\(3 downto 0) => \zq_cntrl.zq_timer.zq_timer_r_reg[7]\(3 downto 0),
      \zq_cntrl.zq_timer.zq_timer_r_reg[7]_1\(3 downto 0) => \zq_cntrl.zq_timer.zq_timer_r_reg[7]_0\(3 downto 0)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mig_mig_7series_v4_2_bank_mach is
  port (
    sent_row : out STD_LOGIC;
    sent_col : out STD_LOGIC;
    insert_maint_r1 : out STD_LOGIC;
    \generate_maint_cmds.insert_maint_r_lcl_reg\ : out STD_LOGIC;
    cs_en2 : out STD_LOGIC;
    DIC : out STD_LOGIC_VECTOR ( 0 to 0 );
    col_rd_wr : out STD_LOGIC;
    cke_r : out STD_LOGIC;
    accept_internal_r : out STD_LOGIC;
    periodic_rd_ack_r : out STD_LOGIC;
    accept_r_reg : out STD_LOGIC;
    accept_ns : out STD_LOGIC;
    rb_hit_busy_r : out STD_LOGIC_VECTOR ( 3 downto 0 );
    idle_r : out STD_LOGIC_VECTOR ( 3 downto 0 );
    was_wr : out STD_LOGIC;
    rd_wr_r_lcl_reg : out STD_LOGIC_VECTOR ( 2 downto 0 );
    req_wr_r_lcl_reg : out STD_LOGIC_VECTOR ( 2 downto 0 );
    p_130_out : out STD_LOGIC;
    row_cmd_wr : out STD_LOGIC_VECTOR ( 3 downto 0 );
    col_wait_r : out STD_LOGIC;
    demand_priority_r : out STD_LOGIC;
    demanded_prior_r : out STD_LOGIC;
    q_has_rd : out STD_LOGIC;
    bm_end_r1 : out STD_LOGIC;
    col_wait_r_0 : out STD_LOGIC;
    req_bank_rdy_ns : out STD_LOGIC;
    demand_priority_r_1 : out STD_LOGIC;
    demanded_prior_r_2 : out STD_LOGIC;
    pass_open_bank_r : out STD_LOGIC;
    pre_bm_end_r : out STD_LOGIC;
    q_has_rd_3 : out STD_LOGIC;
    bm_end_r1_0 : out STD_LOGIC;
    p_52_out : out STD_LOGIC;
    col_wait_r_4 : out STD_LOGIC;
    demand_priority_r_5 : out STD_LOGIC;
    demanded_prior_r_6 : out STD_LOGIC;
    override_demand_r : out STD_LOGIC;
    override_demand_ns : out STD_LOGIC;
    q_has_rd_7 : out STD_LOGIC;
    bm_end_r1_1 : out STD_LOGIC;
    col_wait_r_8 : out STD_LOGIC;
    demand_priority_r_9 : out STD_LOGIC;
    pass_open_bank_r_10 : out STD_LOGIC;
    pre_bm_end_r_11 : out STD_LOGIC;
    q_has_rd_12 : out STD_LOGIC;
    pass_open_bank_r_lcl_reg : out STD_LOGIC;
    pass_open_bank_r_lcl_reg_0 : out STD_LOGIC;
    rnk_config_valid_r : out STD_LOGIC;
    maint_wip_r : out STD_LOGIC;
    wait_for_maint_r : out STD_LOGIC;
    wait_for_maint_r_13 : out STD_LOGIC;
    wait_for_maint_r_14 : out STD_LOGIC;
    wait_for_maint_r_15 : out STD_LOGIC;
    periodic_rd_cntr_r : out STD_LOGIC;
    tail_r : out STD_LOGIC;
    head_r : out STD_LOGIC_VECTOR ( 3 downto 0 );
    tail_r_16 : out STD_LOGIC;
    tail_r_17 : out STD_LOGIC;
    tail_r_18 : out STD_LOGIC;
    auto_pre_r : out STD_LOGIC;
    auto_pre_r_19 : out STD_LOGIC;
    auto_pre_r_20 : out STD_LOGIC;
    auto_pre_r_21 : out STD_LOGIC;
    \rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][5]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
    \rank_final_loop[0].bank_final_loop[1].final_data_offset_mc_reg[0][11]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
    \rank_final_loop[0].bank_final_loop[2].final_data_offset_mc_reg[0][17]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
    granted_col_r_reg : out STD_LOGIC;
    \grant_r_reg[2]\ : out STD_LOGIC;
    idle_r_lcl_reg : out STD_LOGIC;
    idle_r_lcl_reg_0 : out STD_LOGIC;
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[4]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    idle_r_lcl_reg_1 : out STD_LOGIC;
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[1]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    idle_r_lcl_reg_2 : out STD_LOGIC;
    Q : out STD_LOGIC_VECTOR ( 3 downto 0 );
    clear_periodic_rd_request : out STD_LOGIC;
    \periodic_rd_generation.read_this_rank_r_reg\ : out STD_LOGIC;
    \periodic_rd_generation.read_this_rank\ : out STD_LOGIC;
    mc_odt_ns : out STD_LOGIC_VECTOR ( 0 to 0 );
    D : out STD_LOGIC_VECTOR ( 0 to 0 );
    granted_col_r_reg_0 : out STD_LOGIC_VECTOR ( 0 to 0 );
    granted_col_r_reg_1 : out STD_LOGIC_VECTOR ( 0 to 0 );
    E : out STD_LOGIC_VECTOR ( 0 to 0 );
    \rtw_timer.rtw_cnt_r_reg[1]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \grant_r_reg[0]\ : out STD_LOGIC;
    \wr_this_rank_r_reg[0]\ : out STD_LOGIC;
    \wr_this_rank_r_reg[0]_0\ : out STD_LOGIC;
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[6]\ : out STD_LOGIC;
    pre_bm_end_r_reg : out STD_LOGIC;
    \grant_r_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
    pre_passing_open_bank_r_reg : out STD_LOGIC;
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[2]\ : out STD_LOGIC;
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]\ : out STD_LOGIC;
    pre_passing_open_bank_r_reg_0 : out STD_LOGIC;
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_0\ : out STD_LOGIC;
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[5]\ : out STD_LOGIC;
    pre_bm_end_r_reg_0 : out STD_LOGIC;
    pre_bm_end_r_reg_1 : out STD_LOGIC;
    set_order_q : out STD_LOGIC;
    \q_entry_r_reg[1]\ : out STD_LOGIC;
    \q_entry_r_reg[0]\ : out STD_LOGIC;
    periodic_rd_ack_r_lcl_reg : out STD_LOGIC;
    \grant_r_reg[3]_0\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    rb_hit_busy_r_reg : out STD_LOGIC;
    row_hit_r_reg : out STD_LOGIC;
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_0\ : out STD_LOGIC;
    \q_entry_r_reg[0]_0\ : out STD_LOGIC;
    set_order_q_22 : out STD_LOGIC;
    \q_entry_r_reg[1]_0\ : out STD_LOGIC;
    \q_entry_r_reg[0]_1\ : out STD_LOGIC;
    \q_entry_r_reg[0]_2\ : out STD_LOGIC;
    idle_r_lcl_reg_3 : out STD_LOGIC;
    \q_entry_r_reg[0]_3\ : out STD_LOGIC;
    q_entry_r : out STD_LOGIC_VECTOR ( 1 downto 0 );
    idle_r_lcl_reg_4 : out STD_LOGIC;
    set_order_q_23 : out STD_LOGIC;
    pre_bm_end_r_reg_2 : out STD_LOGIC;
    demand_priority_r_reg : out STD_LOGIC;
    rnk_config_valid_r_lcl_reg : out STD_LOGIC;
    \order_q_r_reg[1]\ : out STD_LOGIC;
    set_order_q_24 : out STD_LOGIC;
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_0\ : out STD_LOGIC;
    \q_entry_r_reg[0]_4\ : out STD_LOGIC;
    \q_entry_r_reg[0]_5\ : out STD_LOGIC;
    \q_entry_r_reg[1]_1\ : out STD_LOGIC;
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_1\ : out STD_LOGIC;
    row_hit_r_reg_0 : out STD_LOGIC;
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_2\ : out STD_LOGIC;
    rb_hit_busy_r_reg_0 : out STD_LOGIC;
    row_hit_r_reg_1 : out STD_LOGIC;
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_1\ : out STD_LOGIC;
    row_hit_r_reg_2 : out STD_LOGIC;
    \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
    mc_we_n_ns : out STD_LOGIC_VECTOR ( 1 downto 0 );
    mc_cas_n_ns : out STD_LOGIC_VECTOR ( 2 downto 0 );
    mc_ras_n_ns : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \pre_4_1_1T_arb.granted_pre_r_reg\ : out STD_LOGIC_VECTOR ( 8 downto 0 );
    \req_bank_r_lcl_reg[2]\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
    \req_bank_r_lcl_reg[2]_0\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
    \req_bank_r_lcl_reg[2]_1\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
    \req_bank_r_lcl_reg[2]_2\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
    \pre_4_1_1T_arb.granted_pre_r_reg_0\ : out STD_LOGIC_VECTOR ( 38 downto 0 );
    \req_row_r_lcl_reg[13]\ : out STD_LOGIC_VECTOR ( 19 downto 0 );
    mc_cs_n_ns : out STD_LOGIC_VECTOR ( 0 to 0 );
    act_wait_r_lcl_reg : out STD_LOGIC;
    \compute_tail.tail_r_lcl_reg\ : out STD_LOGIC;
    \compute_tail.tail_r_lcl_reg_0\ : out STD_LOGIC;
    idle_r_lcl_reg_5 : out STD_LOGIC;
    \compute_tail.tail_r_lcl_reg_1\ : out STD_LOGIC;
    \compute_tail.tail_r_lcl_reg_2\ : out STD_LOGIC;
    act_wait_r_lcl_reg_0 : out STD_LOGIC;
    \grant_r_reg[1]\ : out STD_LOGIC;
    demanded_prior_r_reg : out STD_LOGIC;
    act_wait_r_lcl_reg_1 : out STD_LOGIC;
    \grant_r_reg[0]_0\ : out STD_LOGIC;
    \last_master_r_reg[3]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    col_wr_data_buf_addr : out STD_LOGIC_VECTOR ( 3 downto 0 );
    act_this_rank : out STD_LOGIC;
    \grant_r_reg[0]_1\ : out STD_LOGIC;
    \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[4]\ : out STD_LOGIC;
    \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[7]\ : out STD_LOGIC;
    demanded_prior_r_reg_0 : out STD_LOGIC;
    \grant_r_reg[0]_2\ : out STD_LOGIC;
    \maint_controller.maint_hit_busies_r_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
    \maint_controller.maint_wip_r_lcl_reg\ : in STD_LOGIC;
    cke_r_reg : in STD_LOGIC;
    mc_cke_ns : in STD_LOGIC_VECTOR ( 0 to 0 );
    maint_srx_r : in STD_LOGIC;
    col_wait_r_reg : in STD_LOGIC;
    periodic_rd_cntr_r_reg : in STD_LOGIC;
    phy_mc_ctl_full : in STD_LOGIC;
    ofs_rdy_r_reg : in STD_LOGIC;
    of_ctl_full_v : in STD_LOGIC_VECTOR ( 0 to 0 );
    q_has_rd_r_reg : in STD_LOGIC;
    col_wait_r_reg_0 : in STD_LOGIC;
    q_has_rd_r_reg_0 : in STD_LOGIC;
    col_wait_r_reg_1 : in STD_LOGIC;
    q_has_rd_r_reg_1 : in STD_LOGIC;
    col_wait_r_reg_2 : in STD_LOGIC;
    q_has_rd_r_reg_2 : in STD_LOGIC;
    auto_pre_r_lcl_reg : in STD_LOGIC;
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_0\ : in STD_LOGIC;
    SR : in STD_LOGIC_VECTOR ( 0 to 0 );
    rnk_config_valid_r_lcl_reg_0 : in STD_LOGIC;
    \maint_controller.maint_wip_r_lcl_reg_0\ : in STD_LOGIC;
    \maint_controller.maint_wip_r_lcl_reg_1\ : in STD_LOGIC;
    wait_for_maint_r_lcl_reg : in STD_LOGIC;
    wait_for_maint_r_lcl_reg_0 : in STD_LOGIC;
    wait_for_maint_r_lcl_reg_1 : in STD_LOGIC;
    wait_for_maint_r_lcl_reg_2 : in STD_LOGIC;
    periodic_rd_cntr_r_reg_0 : in STD_LOGIC;
    \compute_tail.tail_r_lcl_reg_3\ : in STD_LOGIC;
    head_r_lcl_reg : in STD_LOGIC;
    head_r_lcl_reg_0 : in STD_LOGIC;
    head_r_lcl_reg_1 : in STD_LOGIC;
    head_r_lcl_reg_2 : in STD_LOGIC;
    \compute_tail.tail_r_lcl_reg_4\ : in STD_LOGIC;
    \compute_tail.tail_r_lcl_reg_5\ : in STD_LOGIC;
    \compute_tail.tail_r_lcl_reg_6\ : in STD_LOGIC;
    auto_pre_r_lcl_reg_0 : in STD_LOGIC;
    auto_pre_r_lcl_reg_1 : in STD_LOGIC;
    auto_pre_r_lcl_reg_2 : in STD_LOGIC;
    auto_pre_r_lcl_reg_3 : in STD_LOGIC;
    \cmd_pipe_plus.mc_data_offset_reg[5]\ : in STD_LOGIC_VECTOR ( 5 downto 0 );
    \cmd_pipe_plus.mc_data_offset_1_reg[5]\ : in STD_LOGIC_VECTOR ( 5 downto 0 );
    \cmd_pipe_plus.mc_data_offset_2_reg[5]\ : in STD_LOGIC_VECTOR ( 5 downto 0 );
    S : in STD_LOGIC_VECTOR ( 2 downto 0 );
    row_hit_r_reg_3 : in STD_LOGIC_VECTOR ( 0 to 0 );
    row_hit_r_reg_4 : in STD_LOGIC_VECTOR ( 0 to 0 );
    row_hit_r_reg_5 : in STD_LOGIC_VECTOR ( 0 to 0 );
    row_hit_r_reg_6 : in STD_LOGIC_VECTOR ( 0 to 0 );
    row_hit_r_reg_7 : in STD_LOGIC_VECTOR ( 0 to 0 );
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_1\ : in STD_LOGIC;
    rb_hit_busy_r_reg_1 : in STD_LOGIC;
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[6]_0\ : in STD_LOGIC;
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_1\ : in STD_LOGIC;
    periodic_rd_r : in STD_LOGIC;
    cmd : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \grant_r_reg[3]_1\ : in STD_LOGIC;
    granted_row_r_reg : in STD_LOGIC;
    \grant_r_reg[3]_2\ : in STD_LOGIC;
    \rtp_timer_r_reg[1]\ : in STD_LOGIC;
    \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[1]\ : in STD_LOGIC;
    \periodic_read_request.periodic_rd_grant_r\ : in STD_LOGIC;
    \periodic_rd_generation.read_this_rank_r\ : in STD_LOGIC;
    \cmd_pipe_plus.mc_odt_reg[0]\ : in STD_LOGIC;
    \rtw_timer.rtw_cnt_r_reg[1]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    granted_col_r_reg_2 : in STD_LOGIC;
    granted_col_r_reg_3 : in STD_LOGIC;
    granted_col_r_reg_4 : in STD_LOGIC;
    granted_col_r_reg_5 : in STD_LOGIC;
    granted_col_r_reg_6 : in STD_LOGIC;
    \ras_timer_r_reg[0]\ : in STD_LOGIC;
    act_wait_r_lcl_reg_2 : in STD_LOGIC;
    \ras_timer_r_reg[0]_0\ : in STD_LOGIC;
    \ras_timer_r_reg[0]_1\ : in STD_LOGIC;
    \q_entry_r_reg[1]_2\ : in STD_LOGIC;
    \maint_controller.maint_hit_busies_r_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
    rd_wr_r_lcl_reg_0 : in STD_LOGIC;
    accept_internal_r_reg : in STD_LOGIC;
    use_addr : in STD_LOGIC;
    req_bank_rdy_r_reg : in STD_LOGIC;
    req_bank_rdy_r_reg_0 : in STD_LOGIC;
    req_bank_rdy_r_reg_1 : in STD_LOGIC;
    \ras_timer_r_reg[0]_2\ : in STD_LOGIC;
    pass_open_bank_r_lcl_reg_1 : in STD_LOGIC;
    pass_open_bank_r_lcl_reg_2 : in STD_LOGIC;
    \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[7]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[3]_0\ : in STD_LOGIC;
    \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[3]_1\ : in STD_LOGIC;
    maint_req_r : in STD_LOGIC;
    \cmd_pipe_plus.mc_we_n_reg[0]\ : in STD_LOGIC;
    \cmd_pipe_plus.mc_address_reg[0]\ : in STD_LOGIC;
    \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[0]\ : in STD_LOGIC;
    maint_zq_r : in STD_LOGIC;
    \cmd_pipe_plus.mc_address_reg[3]\ : in STD_LOGIC;
    \cmd_pipe_plus.mc_address_reg[0]_0\ : in STD_LOGIC;
    \grant_r_reg[3]_3\ : in STD_LOGIC;
    \req_row_r_lcl_reg[13]_0\ : in STD_LOGIC_VECTOR ( 13 downto 0 );
    inhbt_act_faw_r : in STD_LOGIC;
    ras_timer_zero_r_reg : in STD_LOGIC;
    ras_timer_zero_r_reg_0 : in STD_LOGIC;
    ras_timer_zero_r_reg_1 : in STD_LOGIC;
    \delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
    \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[4]_0\ : in STD_LOGIC;
    phy_mc_data_full : in STD_LOGIC;
    \rtp_timer_r_reg[0]\ : in STD_LOGIC;
    \grant_r[2]_i_3\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    was_priority_reg : in STD_LOGIC;
    \req_data_buf_addr_r_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
    \req_bank_r_lcl_reg[2]_3\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
    \req_col_r_reg[9]\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
    \q_entry_r_reg[1]_3\ : in STD_LOGIC;
    \q_entry_r_reg[0]_6\ : in STD_LOGIC;
    \q_entry_r_reg[1]_4\ : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of mig_mig_7series_v4_2_bank_mach : entity is "mig_7series_v4_2_bank_mach";
end mig_mig_7series_v4_2_bank_mach;

architecture STRUCTURE of mig_mig_7series_v4_2_bank_mach is
  signal \^q\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \^accept_internal_r\ : STD_LOGIC;
  signal \^accept_r_reg\ : STD_LOGIC;
  signal act_this_rank_r : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal arb_mux0_n_100 : STD_LOGIC;
  signal arb_mux0_n_101 : STD_LOGIC;
  signal arb_mux0_n_102 : STD_LOGIC;
  signal arb_mux0_n_103 : STD_LOGIC;
  signal arb_mux0_n_104 : STD_LOGIC;
  signal arb_mux0_n_118 : STD_LOGIC;
  signal arb_mux0_n_119 : STD_LOGIC;
  signal arb_mux0_n_120 : STD_LOGIC;
  signal arb_mux0_n_38 : STD_LOGIC;
  signal \arb_row_col0/granted_col_ns\ : STD_LOGIC;
  signal \arb_row_col0/pre_4_1_1T_arb.granted_pre_ns\ : STD_LOGIC;
  signal \arb_row_col0/rnk_config_strobe_ns\ : STD_LOGIC;
  signal \^auto_pre_r\ : STD_LOGIC;
  signal \^auto_pre_r_19\ : STD_LOGIC;
  signal \^auto_pre_r_20\ : STD_LOGIC;
  signal \^auto_pre_r_21\ : STD_LOGIC;
  signal \bank_cntrl[0].bank0_n_24\ : STD_LOGIC;
  signal \bank_cntrl[0].bank0_n_26\ : STD_LOGIC;
  signal \bank_cntrl[0].bank0_n_27\ : STD_LOGIC;
  signal \bank_cntrl[0].bank0_n_28\ : STD_LOGIC;
  signal \bank_cntrl[0].bank0_n_29\ : STD_LOGIC;
  signal \bank_cntrl[0].bank0_n_30\ : STD_LOGIC;
  signal \bank_cntrl[0].bank0_n_33\ : STD_LOGIC;
  signal \bank_cntrl[0].bank0_n_34\ : STD_LOGIC;
  signal \bank_cntrl[0].bank0_n_38\ : STD_LOGIC;
  signal \bank_cntrl[0].bank0_n_39\ : STD_LOGIC;
  signal \bank_cntrl[0].bank0_n_40\ : STD_LOGIC;
  signal \bank_cntrl[0].bank0_n_42\ : STD_LOGIC;
  signal \bank_cntrl[0].bank0_n_43\ : STD_LOGIC;
  signal \bank_cntrl[0].bank0_n_44\ : STD_LOGIC;
  signal \bank_cntrl[0].bank0_n_46\ : STD_LOGIC;
  signal \bank_cntrl[0].bank0_n_49\ : STD_LOGIC;
  signal \bank_cntrl[0].bank0_n_53\ : STD_LOGIC;
  signal \bank_cntrl[1].bank0_n_22\ : STD_LOGIC;
  signal \bank_cntrl[1].bank0_n_26\ : STD_LOGIC;
  signal \bank_cntrl[1].bank0_n_30\ : STD_LOGIC;
  signal \bank_cntrl[1].bank0_n_36\ : STD_LOGIC;
  signal \bank_cntrl[1].bank0_n_41\ : STD_LOGIC;
  signal \bank_cntrl[1].bank0_n_43\ : STD_LOGIC;
  signal \bank_cntrl[1].bank0_n_44\ : STD_LOGIC;
  signal \bank_cntrl[1].bank0_n_47\ : STD_LOGIC;
  signal \bank_cntrl[2].bank0_n_22\ : STD_LOGIC;
  signal \bank_cntrl[2].bank0_n_29\ : STD_LOGIC;
  signal \bank_cntrl[2].bank0_n_31\ : STD_LOGIC;
  signal \bank_cntrl[2].bank0_n_32\ : STD_LOGIC;
  signal \bank_cntrl[2].bank0_n_33\ : STD_LOGIC;
  signal \bank_cntrl[2].bank0_n_34\ : STD_LOGIC;
  signal \bank_cntrl[2].bank0_n_40\ : STD_LOGIC;
  signal \bank_cntrl[2].bank0_n_41\ : STD_LOGIC;
  signal \bank_cntrl[2].bank0_n_43\ : STD_LOGIC;
  signal \bank_cntrl[2].bank0_n_46\ : STD_LOGIC;
  signal \bank_cntrl[2].bank0_n_47\ : STD_LOGIC;
  signal \bank_cntrl[2].bank0_n_48\ : STD_LOGIC;
  signal \bank_cntrl[2].bank0_n_64\ : STD_LOGIC;
  signal \bank_cntrl[3].bank0_n_21\ : STD_LOGIC;
  signal \bank_cntrl[3].bank0_n_27\ : STD_LOGIC;
  signal \bank_cntrl[3].bank0_n_29\ : STD_LOGIC;
  signal \bank_cntrl[3].bank0_n_30\ : STD_LOGIC;
  signal \bank_cntrl[3].bank0_n_38\ : STD_LOGIC;
  signal \bank_cntrl[3].bank0_n_41\ : STD_LOGIC;
  signal \bank_cntrl[3].bank0_n_46\ : STD_LOGIC;
  signal \bank_cntrl[3].bank0_n_61\ : STD_LOGIC;
  signal \bank_cntrl[3].bank0_n_62\ : STD_LOGIC;
  signal \bank_cntrl[3].bank0_n_63\ : STD_LOGIC;
  signal bank_common0_n_11 : STD_LOGIC;
  signal bank_common0_n_13 : STD_LOGIC;
  signal bank_common0_n_15 : STD_LOGIC;
  signal bank_common0_n_17 : STD_LOGIC;
  signal bank_common0_n_24 : STD_LOGIC;
  signal bank_common0_n_25 : STD_LOGIC;
  signal bank_common0_n_26 : STD_LOGIC;
  signal bank_common0_n_28 : STD_LOGIC;
  signal bank_common0_n_30 : STD_LOGIC;
  signal \bank_compare0/req_col_r\ : STD_LOGIC_VECTOR ( 9 downto 0 );
  signal \bank_compare0/req_col_r_10\ : STD_LOGIC_VECTOR ( 9 downto 0 );
  signal \bank_compare0/req_col_r_2\ : STD_LOGIC_VECTOR ( 9 downto 0 );
  signal \bank_compare0/req_col_r_6\ : STD_LOGIC_VECTOR ( 9 downto 0 );
  signal \bank_compare0/req_wr_r_lcl0\ : STD_LOGIC;
  signal \bank_queue0/q_entry_ns\ : STD_LOGIC_VECTOR ( 1 to 1 );
  signal \bank_state0/demanded_prior_r\ : STD_LOGIC;
  signal \bank_state0/ofs_rdy_r\ : STD_LOGIC;
  signal \bank_state0/ofs_rdy_r0\ : STD_LOGIC;
  signal \bank_state0/ofs_rdy_r0_0\ : STD_LOGIC;
  signal \bank_state0/ofs_rdy_r0_1\ : STD_LOGIC;
  signal \bank_state0/ofs_rdy_r_13\ : STD_LOGIC;
  signal \bank_state0/ofs_rdy_r_5\ : STD_LOGIC;
  signal \bank_state0/ofs_rdy_r_9\ : STD_LOGIC;
  signal \bank_state0/req_bank_rdy_ns\ : STD_LOGIC;
  signal \bank_state0/req_bank_rdy_ns_14\ : STD_LOGIC;
  signal \bank_state0/req_bank_rdy_r\ : STD_LOGIC;
  signal \^demand_priority_r\ : STD_LOGIC;
  signal \^demand_priority_r_1\ : STD_LOGIC;
  signal \^demand_priority_r_5\ : STD_LOGIC;
  signal \^demand_priority_r_9\ : STD_LOGIC;
  signal \^demand_priority_r_reg\ : STD_LOGIC;
  signal \^demanded_prior_r\ : STD_LOGIC;
  signal \^demanded_prior_r_2\ : STD_LOGIC;
  signal \^demanded_prior_r_6\ : STD_LOGIC;
  signal \^demanded_prior_r_reg\ : STD_LOGIC;
  signal \^demanded_prior_r_reg_0\ : STD_LOGIC;
  signal \^generate_maint_cmds.insert_maint_r_lcl_reg\ : STD_LOGIC;
  signal \^grant_r_reg[3]\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \^grant_r_reg[3]_0\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \^head_r\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal hi_priority : STD_LOGIC;
  signal \^idle_r\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \^idle_r_lcl_reg\ : STD_LOGIC;
  signal \^idle_r_lcl_reg_0\ : STD_LOGIC;
  signal \^idle_r_lcl_reg_1\ : STD_LOGIC;
  signal \^idle_r_lcl_reg_2\ : STD_LOGIC;
  signal \^maint_wip_r\ : STD_LOGIC;
  signal \^override_demand_ns\ : STD_LOGIC;
  signal \^override_demand_r\ : STD_LOGIC;
  signal \^p_130_out\ : STD_LOGIC;
  signal \^p_52_out\ : STD_LOGIC;
  signal p_9_in : STD_LOGIC;
  signal \^pass_open_bank_r_lcl_reg\ : STD_LOGIC;
  signal \^pass_open_bank_r_lcl_reg_0\ : STD_LOGIC;
  signal \^periodic_rd_ack_r\ : STD_LOGIC;
  signal \^periodic_rd_ack_r_lcl_reg\ : STD_LOGIC;
  signal \^periodic_rd_cntr_r\ : STD_LOGIC;
  signal periodic_rd_insert : STD_LOGIC;
  signal \^pre_bm_end_r_reg\ : STD_LOGIC;
  signal \^pre_bm_end_r_reg_1\ : STD_LOGIC;
  signal \^pre_passing_open_bank_r_reg\ : STD_LOGIC;
  signal \^pre_passing_open_bank_r_reg_0\ : STD_LOGIC;
  signal q_has_priority : STD_LOGIC;
  signal q_has_priority_12 : STD_LOGIC;
  signal q_has_priority_4 : STD_LOGIC;
  signal q_has_priority_8 : STD_LOGIC;
  signal \^rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_0\ : STD_LOGIC;
  signal \^rb_hit_busies.rb_hit_busies_r_lcl_reg[3]\ : STD_LOGIC;
  signal \^rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_0\ : STD_LOGIC;
  signal \^rb_hit_busies.rb_hit_busies_r_lcl_reg[5]\ : STD_LOGIC;
  signal rb_hit_busies_r : STD_LOGIC_VECTOR ( 3 downto 2 );
  signal rb_hit_busies_r_11 : STD_LOGIC_VECTOR ( 6 downto 5 );
  signal rb_hit_busies_r_3 : STD_LOGIC_VECTOR ( 3 downto 2 );
  signal rb_hit_busies_r_7 : STD_LOGIC_VECTOR ( 5 downto 3 );
  signal \^rb_hit_busy_r\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \^rb_hit_busy_r_reg\ : STD_LOGIC;
  signal \^rb_hit_busy_r_reg_0\ : STD_LOGIC;
  signal rd_this_rank_r : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal rd_wr_r : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \^rd_wr_r_lcl_reg\ : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal \^req_bank_r_lcl_reg[2]\ : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal \^req_bank_r_lcl_reg[2]_0\ : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal \^req_bank_r_lcl_reg[2]_1\ : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal \^req_bank_r_lcl_reg[2]_2\ : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal req_data_buf_addr_r : STD_LOGIC_VECTOR ( 18 downto 0 );
  signal req_periodic_rd_r : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal req_row_r : STD_LOGIC_VECTOR ( 53 downto 9 );
  signal \^req_row_r_lcl_reg[13]\ : STD_LOGIC_VECTOR ( 19 downto 0 );
  signal \^req_wr_r_lcl_reg\ : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal \^rnk_config_valid_r\ : STD_LOGIC;
  signal \^rnk_config_valid_r_lcl_reg\ : STD_LOGIC;
  signal \^row_cmd_wr\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal sending_pre : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal \^sent_col\ : STD_LOGIC;
  signal \^set_order_q\ : STD_LOGIC;
  signal \^set_order_q_22\ : STD_LOGIC;
  signal \^set_order_q_23\ : STD_LOGIC;
  signal \^set_order_q_24\ : STD_LOGIC;
  signal wr_this_rank_r : STD_LOGIC_VECTOR ( 3 downto 0 );
begin
  Q(3 downto 0) <= \^q\(3 downto 0);
  accept_internal_r <= \^accept_internal_r\;
  accept_r_reg <= \^accept_r_reg\;
  auto_pre_r <= \^auto_pre_r\;
  auto_pre_r_19 <= \^auto_pre_r_19\;
  auto_pre_r_20 <= \^auto_pre_r_20\;
  auto_pre_r_21 <= \^auto_pre_r_21\;
  demand_priority_r <= \^demand_priority_r\;
  demand_priority_r_1 <= \^demand_priority_r_1\;
  demand_priority_r_5 <= \^demand_priority_r_5\;
  demand_priority_r_9 <= \^demand_priority_r_9\;
  demand_priority_r_reg <= \^demand_priority_r_reg\;
  demanded_prior_r <= \^demanded_prior_r\;
  demanded_prior_r_2 <= \^demanded_prior_r_2\;
  demanded_prior_r_6 <= \^demanded_prior_r_6\;
  demanded_prior_r_reg <= \^demanded_prior_r_reg\;
  demanded_prior_r_reg_0 <= \^demanded_prior_r_reg_0\;
  \generate_maint_cmds.insert_maint_r_lcl_reg\ <= \^generate_maint_cmds.insert_maint_r_lcl_reg\;
  \grant_r_reg[3]\(3 downto 0) <= \^grant_r_reg[3]\(3 downto 0);
  \grant_r_reg[3]_0\(0) <= \^grant_r_reg[3]_0\(0);
  head_r(3 downto 0) <= \^head_r\(3 downto 0);
  idle_r(3 downto 0) <= \^idle_r\(3 downto 0);
  idle_r_lcl_reg <= \^idle_r_lcl_reg\;
  idle_r_lcl_reg_0 <= \^idle_r_lcl_reg_0\;
  idle_r_lcl_reg_1 <= \^idle_r_lcl_reg_1\;
  idle_r_lcl_reg_2 <= \^idle_r_lcl_reg_2\;
  maint_wip_r <= \^maint_wip_r\;
  override_demand_ns <= \^override_demand_ns\;
  override_demand_r <= \^override_demand_r\;
  p_130_out <= \^p_130_out\;
  p_52_out <= \^p_52_out\;
  pass_open_bank_r_lcl_reg <= \^pass_open_bank_r_lcl_reg\;
  pass_open_bank_r_lcl_reg_0 <= \^pass_open_bank_r_lcl_reg_0\;
  periodic_rd_ack_r <= \^periodic_rd_ack_r\;
  periodic_rd_ack_r_lcl_reg <= \^periodic_rd_ack_r_lcl_reg\;
  periodic_rd_cntr_r <= \^periodic_rd_cntr_r\;
  pre_bm_end_r_reg <= \^pre_bm_end_r_reg\;
  pre_bm_end_r_reg_1 <= \^pre_bm_end_r_reg_1\;
  pre_passing_open_bank_r_reg <= \^pre_passing_open_bank_r_reg\;
  pre_passing_open_bank_r_reg_0 <= \^pre_passing_open_bank_r_reg_0\;
  \rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_0\ <= \^rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_0\;
  \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]\ <= \^rb_hit_busies.rb_hit_busies_r_lcl_reg[3]\;
  \rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_0\ <= \^rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_0\;
  \rb_hit_busies.rb_hit_busies_r_lcl_reg[5]\ <= \^rb_hit_busies.rb_hit_busies_r_lcl_reg[5]\;
  rb_hit_busy_r(3 downto 0) <= \^rb_hit_busy_r\(3 downto 0);
  rb_hit_busy_r_reg <= \^rb_hit_busy_r_reg\;
  rb_hit_busy_r_reg_0 <= \^rb_hit_busy_r_reg_0\;
  rd_wr_r_lcl_reg(2 downto 0) <= \^rd_wr_r_lcl_reg\(2 downto 0);
  \req_bank_r_lcl_reg[2]\(2 downto 0) <= \^req_bank_r_lcl_reg[2]\(2 downto 0);
  \req_bank_r_lcl_reg[2]_0\(2 downto 0) <= \^req_bank_r_lcl_reg[2]_0\(2 downto 0);
  \req_bank_r_lcl_reg[2]_1\(2 downto 0) <= \^req_bank_r_lcl_reg[2]_1\(2 downto 0);
  \req_bank_r_lcl_reg[2]_2\(2 downto 0) <= \^req_bank_r_lcl_reg[2]_2\(2 downto 0);
  \req_row_r_lcl_reg[13]\(19 downto 0) <= \^req_row_r_lcl_reg[13]\(19 downto 0);
  req_wr_r_lcl_reg(2 downto 0) <= \^req_wr_r_lcl_reg\(2 downto 0);
  rnk_config_valid_r <= \^rnk_config_valid_r\;
  rnk_config_valid_r_lcl_reg <= \^rnk_config_valid_r_lcl_reg\;
  row_cmd_wr(3 downto 0) <= \^row_cmd_wr\(3 downto 0);
  sent_col <= \^sent_col\;
  set_order_q <= \^set_order_q\;
  set_order_q_22 <= \^set_order_q_22\;
  set_order_q_23 <= \^set_order_q_23\;
  set_order_q_24 <= \^set_order_q_24\;
arb_mux0: entity work.mig_mig_7series_v4_2_arb_mux
     port map (
      D(0) => D(0),
      DIC(0) => DIC(0),
      E(0) => E(0),
      Q(3 downto 0) => \^q\(3 downto 0),
      SR(0) => SR(0),
      act_this_rank => act_this_rank,
      act_this_rank_r(3 downto 0) => act_this_rank_r(3 downto 0),
      cke_r => cke_r,
      cke_r_reg => \maint_controller.maint_wip_r_lcl_reg\,
      cke_r_reg_0 => cke_r_reg,
      \cmd_pipe_plus.mc_address_reg[0]\ => \cmd_pipe_plus.mc_address_reg[0]\,
      \cmd_pipe_plus.mc_address_reg[0]_0\ => \cmd_pipe_plus.mc_address_reg[0]_0\,
      \cmd_pipe_plus.mc_address_reg[10]\ => \^row_cmd_wr\(0),
      \cmd_pipe_plus.mc_address_reg[10]_0\ => \bank_cntrl[3].bank0_n_61\,
      \cmd_pipe_plus.mc_address_reg[23]\(9 downto 0) => \bank_compare0/req_col_r_10\(9 downto 0),
      \cmd_pipe_plus.mc_address_reg[23]_0\(9 downto 0) => \bank_compare0/req_col_r\(9 downto 0),
      \cmd_pipe_plus.mc_address_reg[23]_1\(9 downto 0) => \bank_compare0/req_col_r_2\(9 downto 0),
      \cmd_pipe_plus.mc_address_reg[23]_2\(9 downto 0) => \bank_compare0/req_col_r_6\(9 downto 0),
      \cmd_pipe_plus.mc_address_reg[24]\ => \^auto_pre_r_21\,
      \cmd_pipe_plus.mc_address_reg[24]_0\ => \^auto_pre_r\,
      \cmd_pipe_plus.mc_address_reg[24]_1\ => \^auto_pre_r_19\,
      \cmd_pipe_plus.mc_address_reg[24]_2\ => \^auto_pre_r_20\,
      \cmd_pipe_plus.mc_address_reg[38]\ => \bank_cntrl[2].bank0_n_64\,
      \cmd_pipe_plus.mc_address_reg[3]\ => \cmd_pipe_plus.mc_address_reg[3]\,
      \cmd_pipe_plus.mc_address_reg[41]\(19 downto 0) => \^req_row_r_lcl_reg[13]\(19 downto 0),
      \cmd_pipe_plus.mc_bank_reg[2]\(2 downto 0) => \^req_bank_r_lcl_reg[2]\(2 downto 0),
      \cmd_pipe_plus.mc_bank_reg[2]_0\(2 downto 0) => \^req_bank_r_lcl_reg[2]_0\(2 downto 0),
      \cmd_pipe_plus.mc_bank_reg[2]_1\(2 downto 0) => \^req_bank_r_lcl_reg[2]_1\(2 downto 0),
      \cmd_pipe_plus.mc_bank_reg[8]\(2 downto 0) => \^req_bank_r_lcl_reg[2]_2\(2 downto 0),
      \cmd_pipe_plus.mc_cas_n_reg[0]\ => \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[0]\,
      \cmd_pipe_plus.mc_data_offset_1_reg[5]\(5 downto 0) => \cmd_pipe_plus.mc_data_offset_1_reg[5]\(5 downto 0),
      \cmd_pipe_plus.mc_data_offset_2_reg[0]\ => \^rd_wr_r_lcl_reg\(1),
      \cmd_pipe_plus.mc_data_offset_2_reg[0]_0\ => \^rd_wr_r_lcl_reg\(2),
      \cmd_pipe_plus.mc_data_offset_2_reg[5]\(5 downto 0) => \cmd_pipe_plus.mc_data_offset_2_reg[5]\(5 downto 0),
      \cmd_pipe_plus.mc_data_offset_reg[5]\(5 downto 0) => \cmd_pipe_plus.mc_data_offset_reg[5]\(5 downto 0),
      \cmd_pipe_plus.mc_odt_reg[0]\ => \cmd_pipe_plus.mc_odt_reg[0]\,
      \cmd_pipe_plus.mc_we_n_reg[0]\ => \cmd_pipe_plus.mc_we_n_reg[0]\,
      \cmd_pipe_plus.mc_we_n_reg[0]_0\ => \^row_cmd_wr\(1),
      \cmd_pipe_plus.mc_we_n_reg[0]_1\ => \^row_cmd_wr\(2),
      \cmd_pipe_plus.mc_we_n_reg[2]\ => \^row_cmd_wr\(3),
      col_rd_wr => col_rd_wr,
      col_wr_data_buf_addr(3 downto 0) => col_wr_data_buf_addr(3 downto 0),
      \delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r_reg[3]\(3 downto 0) => \delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r_reg[3]\(3 downto 0),
      \grant_r[2]_i_3\ => \rtp_timer_r_reg[0]\,
      \grant_r[2]_i_3_0\(0) => \grant_r[2]_i_3\(0),
      \grant_r[3]_i_8\ => \^req_wr_r_lcl_reg\(2),
      \grant_r[3]_i_8_0\ => \^req_wr_r_lcl_reg\(1),
      \grant_r_reg[0]\ => \grant_r_reg[0]\,
      \grant_r_reg[0]_0\ => \grant_r_reg[0]_0\,
      \grant_r_reg[0]_1\ => \grant_r_reg[0]_1\,
      \grant_r_reg[0]_2\ => \grant_r_reg[0]_2\,
      \grant_r_reg[0]_3\ => \bank_cntrl[3].bank0_n_27\,
      \grant_r_reg[0]_4\ => \bank_cntrl[0].bank0_n_24\,
      \grant_r_reg[0]_5\ => \bank_cntrl[2].bank0_n_29\,
      \grant_r_reg[0]_6\ => \bank_cntrl[3].bank0_n_46\,
      \grant_r_reg[0]_7\ => \bank_cntrl[2].bank0_n_48\,
      \grant_r_reg[0]_8\ => \bank_cntrl[0].bank0_n_53\,
      \grant_r_reg[1]\ => \grant_r_reg[1]\,
      \grant_r_reg[1]_0\ => \bank_cntrl[1].bank0_n_47\,
      \grant_r_reg[2]\ => \grant_r_reg[2]\,
      \grant_r_reg[2]_0\ => \bank_cntrl[1].bank0_n_26\,
      \grant_r_reg[3]\ => arb_mux0_n_38,
      \grant_r_reg[3]_0\(3 downto 0) => \^grant_r_reg[3]\(3 downto 0),
      \grant_r_reg[3]_1\(3) => \^grant_r_reg[3]_0\(0),
      \grant_r_reg[3]_1\(2 downto 0) => sending_pre(2 downto 0),
      \grant_r_reg[3]_2\ => \grant_r_reg[3]_1\,
      \grant_r_reg[3]_3\ => \grant_r_reg[3]_2\,
      \grant_r_reg[3]_4\ => \grant_r_reg[3]_3\,
      \grant_r_reg[3]_5\ => \bank_cntrl[2].bank0_n_47\,
      granted_col_ns => \arb_row_col0/granted_col_ns\,
      granted_col_r_reg => \^sent_col\,
      granted_col_r_reg_0 => granted_col_r_reg,
      granted_col_r_reg_1(0) => granted_col_r_reg_0(0),
      granted_col_r_reg_2(0) => granted_col_r_reg_1(0),
      granted_row_r_reg => sent_row,
      granted_row_r_reg_0 => granted_row_r_reg,
      \i___22_i_1\ => \^rd_wr_r_lcl_reg\(0),
      inhbt_act_faw_r => inhbt_act_faw_r,
      insert_maint_r1_lcl_reg => insert_maint_r1,
      insert_maint_r1_lcl_reg_0 => \^generate_maint_cmds.insert_maint_r_lcl_reg\,
      \last_master_r_reg[3]\(0) => \last_master_r_reg[3]\(0),
      maint_srx_r => maint_srx_r,
      maint_zq_r => maint_zq_r,
      mc_cas_n_ns(2 downto 0) => mc_cas_n_ns(2 downto 0),
      mc_cke_ns(0) => mc_cke_ns(0),
      mc_cs_n_ns(0) => mc_cs_n_ns(0),
      mc_odt_ns(0) => mc_odt_ns(0),
      mc_ras_n_ns(1 downto 0) => mc_ras_n_ns(1 downto 0),
      mc_we_n_ns(1 downto 0) => mc_we_n_ns(1 downto 0),
      ofs_rdy_r => \bank_state0/ofs_rdy_r_9\,
      ofs_rdy_r_0 => \bank_state0/ofs_rdy_r\,
      ofs_rdy_r_1 => \bank_state0/ofs_rdy_r_13\,
      ofs_rdy_r_2 => \bank_state0/ofs_rdy_r_5\,
      override_demand_ns => \^override_demand_ns\,
      \periodic_rd_generation.read_this_rank\ => \periodic_rd_generation.read_this_rank\,
      \periodic_rd_generation.read_this_rank_r\ => \periodic_rd_generation.read_this_rank_r\,
      \periodic_rd_generation.read_this_rank_r_reg\ => \periodic_rd_generation.read_this_rank_r_reg\,
      \pre_4_1_1T_arb.granted_pre_ns\ => \arb_row_col0/pre_4_1_1T_arb.granted_pre_ns\,
      \pre_4_1_1T_arb.granted_pre_r_reg\ => cs_en2,
      \pre_4_1_1T_arb.granted_pre_r_reg_0\(8 downto 0) => \pre_4_1_1T_arb.granted_pre_r_reg\(8 downto 0),
      \pre_4_1_1T_arb.granted_pre_r_reg_1\(38 downto 0) => \pre_4_1_1T_arb.granted_pre_r_reg_0\(38 downto 0),
      \rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][5]\(3 downto 0) => \rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][5]\(3 downto 0),
      \rank_final_loop[0].bank_final_loop[1].final_data_offset_mc_reg[0][11]\(3 downto 0) => \rank_final_loop[0].bank_final_loop[1].final_data_offset_mc_reg[0][11]\(3 downto 0),
      \rank_final_loop[0].bank_final_loop[2].final_data_offset_mc_reg[0][17]\(3 downto 0) => \rank_final_loop[0].bank_final_loop[2].final_data_offset_mc_reg[0][17]\(3 downto 0),
      rd_this_rank_r(3 downto 0) => rd_this_rank_r(3 downto 0),
      rd_wr_r(0) => rd_wr_r(0),
      req_bank_rdy_r => \bank_state0/req_bank_rdy_r\,
      req_bank_rdy_r_reg => arb_mux0_n_118,
      req_data_buf_addr_r(15 downto 12) => req_data_buf_addr_r(18 downto 15),
      req_data_buf_addr_r(11 downto 8) => req_data_buf_addr_r(13 downto 10),
      req_data_buf_addr_r(7 downto 4) => req_data_buf_addr_r(8 downto 5),
      req_data_buf_addr_r(3 downto 0) => req_data_buf_addr_r(3 downto 0),
      req_periodic_rd_r(3 downto 0) => req_periodic_rd_r(3 downto 0),
      req_row_r(34 downto 23) => req_row_r(53 downto 42),
      req_row_r(22) => req_row_r(39),
      req_row_r(21 downto 12) => req_row_r(37 downto 28),
      req_row_r(11 downto 3) => req_row_r(22 downto 14),
      req_row_r(2 downto 0) => req_row_r(11 downto 9),
      rnk_config_strobe_ns => \arb_row_col0/rnk_config_strobe_ns\,
      \rnk_config_strobe_r_reg[0]\ => arb_mux0_n_100,
      rnk_config_valid_r_lcl_reg => \^rnk_config_valid_r\,
      rnk_config_valid_r_lcl_reg_0 => arb_mux0_n_101,
      rnk_config_valid_r_lcl_reg_1 => arb_mux0_n_102,
      rnk_config_valid_r_lcl_reg_2 => arb_mux0_n_103,
      rnk_config_valid_r_lcl_reg_3 => arb_mux0_n_104,
      rnk_config_valid_r_lcl_reg_4 => rnk_config_valid_r_lcl_reg_0,
      \rtw_timer.rtw_cnt_r_reg[0]\ => \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[1]\,
      \rtw_timer.rtw_cnt_r_reg[1]\(1 downto 0) => \rtw_timer.rtw_cnt_r_reg[1]\(1 downto 0),
      \rtw_timer.rtw_cnt_r_reg[1]_0\ => arb_mux0_n_119,
      \rtw_timer.rtw_cnt_r_reg[1]_1\(1 downto 0) => \rtw_timer.rtw_cnt_r_reg[1]_0\(1 downto 0),
      wr_this_rank_r(3 downto 0) => wr_this_rank_r(3 downto 0),
      \wr_this_rank_r_reg[0]\ => \wr_this_rank_r_reg[0]\,
      \wr_this_rank_r_reg[0]_0\ => \wr_this_rank_r_reg[0]_0\,
      \wtr_timer.wtr_cnt_r_reg[1]\ => arb_mux0_n_120
    );
\bank_cntrl[0].bank0\: entity work.mig_mig_7series_v4_2_bank_cntrl
     port map (
      E(0) => \^idle_r\(0),
      Q(1) => \^q\(3),
      Q(0) => \^q\(0),
      S(2 downto 0) => S(2 downto 0),
      accept_internal_r_reg => \^idle_r_lcl_reg\,
      accept_internal_r_reg_0 => \^idle_r_lcl_reg_0\,
      accept_internal_r_reg_1 => \^idle_r_lcl_reg_1\,
      accept_internal_r_reg_2 => accept_internal_r_reg,
      accept_internal_r_reg_3 => \^periodic_rd_ack_r\,
      accept_internal_r_reg_4 => \^accept_internal_r\,
      act_this_rank_r(0) => act_this_rank_r(0),
      act_wait_r_lcl_reg => \^row_cmd_wr\(0),
      act_wait_r_lcl_reg_0 => act_wait_r_lcl_reg,
      act_wait_r_lcl_reg_1 => act_wait_r_lcl_reg_2,
      auto_pre_r_lcl_reg => \^auto_pre_r\,
      auto_pre_r_lcl_reg_0 => \bank_cntrl[0].bank0_n_53\,
      auto_pre_r_lcl_reg_1 => auto_pre_r_lcl_reg_0,
      auto_pre_r_lcl_reg_2 => \^accept_r_reg\,
      bm_end_r1_reg => \bank_cntrl[0].bank0_n_26\,
      bm_end_r1_reg_0 => \bank_cntrl[0].bank0_n_27\,
      col_wait_r_reg => col_wait_r,
      col_wait_r_reg_0 => col_wait_r_reg,
      \compute_tail.tail_r_lcl_reg\ => \compute_tail.tail_r_lcl_reg_0\,
      \compute_tail.tail_r_lcl_reg_0\ => \compute_tail.tail_r_lcl_reg_3\,
      demand_priority_r_reg => \^demand_priority_r\,
      demand_priority_r_reg_0 => \^sent_col\,
      demanded_prior_r => \bank_state0/demanded_prior_r\,
      demanded_prior_r_reg => \^demanded_prior_r\,
      demanded_prior_r_reg_0 => \^demanded_prior_r_reg_0\,
      demanded_prior_r_reg_1 => \^demanded_prior_r_reg\,
      demanded_prior_r_reg_2 => \^demand_priority_r_9\,
      \grant_r[2]_i_3\ => \bank_cntrl[3].bank0_n_63\,
      \grant_r[2]_i_3_0\ => arb_mux0_n_102,
      granted_col_r_reg => granted_col_r_reg_6,
      granted_col_r_reg_0 => arb_mux0_n_120,
      granted_col_r_reg_1 => arb_mux0_n_119,
      head_r_lcl_reg => \^head_r\(0),
      head_r_lcl_reg_0 => head_r_lcl_reg,
      head_r_lcl_reg_1 => bank_common0_n_15,
      hi_priority => hi_priority,
      \i___3_i_4\ => \^pre_bm_end_r_reg\,
      idle_r_lcl_reg => \^idle_r_lcl_reg_2\,
      idle_r_lcl_reg_0 => \bank_cntrl[0].bank0_n_28\,
      idle_r_lcl_reg_1 => \bank_cntrl[0].bank0_n_29\,
      idle_r_lcl_reg_2 => \bank_cntrl[0].bank0_n_30\,
      idle_r_lcl_reg_3 => \bank_cntrl[0].bank0_n_33\,
      idle_r_lcl_reg_4 => \bank_cntrl[0].bank0_n_34\,
      idle_r_lcl_reg_5 => idle_r_lcl_reg_4,
      idle_r_lcl_reg_6 => \bank_cntrl[0].bank0_n_49\,
      idle_r_lcl_reg_7 => idle_r_lcl_reg_5,
      maint_req_r => maint_req_r,
      of_ctl_full_v(0) => of_ctl_full_v(0),
      ofs_rdy_r => \bank_state0/ofs_rdy_r\,
      ofs_rdy_r0 => \bank_state0/ofs_rdy_r0_1\,
      ofs_rdy_r0_0 => \bank_state0/ofs_rdy_r0_0\,
      ofs_rdy_r0_1 => \bank_state0/ofs_rdy_r0\,
      ofs_rdy_r_reg => \maint_controller.maint_wip_r_lcl_reg\,
      ofs_rdy_r_reg_0 => \^rd_wr_r_lcl_reg\(2),
      ofs_rdy_r_reg_1 => \^rd_wr_r_lcl_reg\(1),
      ofs_rdy_r_reg_2 => \^rd_wr_r_lcl_reg\(0),
      \order_q_r_reg[0]\ => \bank_cntrl[1].bank0_n_22\,
      \order_q_r_reg[0]_0\ => \bank_cntrl[2].bank0_n_22\,
      \order_q_r_reg[0]_1\ => \bank_cntrl[3].bank0_n_21\,
      ordered_r_lcl_reg => \bank_cntrl[0].bank0_n_42\,
      ordered_r_lcl_reg_0 => \bank_cntrl[0].bank0_n_44\,
      override_demand_ns => \^override_demand_ns\,
      override_demand_r => \^override_demand_r\,
      p_9_in => p_9_in,
      pass_open_bank_r_lcl_reg => \^pass_open_bank_r_lcl_reg_0\,
      pass_open_bank_r_lcl_reg_0 => pass_open_bank_r_lcl_reg_1,
      pass_open_bank_r_lcl_reg_1 => \^periodic_rd_cntr_r\,
      pass_open_bank_r_lcl_reg_2 => \^maint_wip_r\,
      periodic_rd_insert => periodic_rd_insert,
      phy_mc_cmd_full_r_reg => ofs_rdy_r_reg,
      phy_mc_ctl_full => phy_mc_ctl_full,
      phy_mc_ctl_full_r_reg => periodic_rd_cntr_r_reg,
      phy_mc_data_full => phy_mc_data_full,
      pre_bm_end_r_reg => \^p_130_out\,
      pre_bm_end_r_reg_0(0) => sending_pre(0),
      pre_passing_open_bank_r_reg => \^pre_passing_open_bank_r_reg\,
      pre_wait_r_reg => \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[1]\,
      pre_wait_r_reg_0 => \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[0]\,
      q_entry_ns(0) => \bank_queue0/q_entry_ns\(1),
      \q_entry_r_reg[0]\ => \q_entry_r_reg[0]_3\,
      \q_entry_r_reg[0]_0\ => q_entry_r(0),
      \q_entry_r_reg[0]_1\ => \^set_order_q_23\,
      \q_entry_r_reg[0]_2\ => \^rb_hit_busy_r\(3),
      \q_entry_r_reg[0]_3\ => \^rb_hit_busy_r\(1),
      \q_entry_r_reg[0]_4\ => \^rb_hit_busy_r\(2),
      \q_entry_r_reg[0]_5\ => bank_common0_n_26,
      \q_entry_r_reg[1]\ => q_entry_r(1),
      \q_entry_r_reg[1]_0\ => \^pre_bm_end_r_reg_1\,
      \q_entry_r_reg[1]_1\ => \^p_52_out\,
      \q_entry_r_reg[1]_2\(0) => \^idle_r\(1),
      \q_entry_r_reg[1]_3\(0) => \^idle_r\(2),
      \q_entry_r_reg[1]_4\(0) => \^idle_r\(3),
      \q_entry_r_reg[1]_5\ => \bank_cntrl[2].bank0_n_33\,
      \q_entry_r_reg[1]_6\ => \^periodic_rd_ack_r_lcl_reg\,
      \q_entry_r_reg[1]_7\ => \bank_cntrl[1].bank0_n_41\,
      q_has_priority => q_has_priority,
      q_has_priority_r_reg => bank_common0_n_25,
      q_has_rd => q_has_rd,
      q_has_rd_r_reg => q_has_rd_r_reg,
      \ras_timer_r[1]_i_3\(0) => \^grant_r_reg[3]\(0),
      \ras_timer_r_reg[0]\ => \bank_cntrl[2].bank0_n_43\,
      \ras_timer_r_reg[0]_0\ => \^rb_hit_busies.rb_hit_busies_r_lcl_reg[3]\,
      \ras_timer_r_reg[0]_1\ => \^pre_passing_open_bank_r_reg_0\,
      \ras_timer_r_reg[0]_2\ => \ras_timer_r_reg[0]_0\,
      \ras_timer_r_reg[0]_3\ => \bank_cntrl[3].bank0_n_29\,
      \ras_timer_r_reg[0]_4\ => \bank_cntrl[2].bank0_n_31\,
      \ras_timer_r_reg[0]_5\ => \bank_cntrl[1].bank0_n_43\,
      \ras_timer_r_reg[1]\ => \bank_cntrl[3].bank0_n_30\,
      \ras_timer_r_reg[1]_0\ => \bank_cntrl[2].bank0_n_32\,
      \ras_timer_r_reg[1]_1\ => \bank_cntrl[1].bank0_n_44\,
      \rb_hit_busies.rb_hit_busies_r_lcl_reg[1]\ => \rb_hit_busies.rb_hit_busies_r_lcl_reg[1]\(0),
      \rb_hit_busies.rb_hit_busies_r_lcl_reg[1]_0\ => \rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_1\,
      \rb_hit_busies.rb_hit_busies_r_lcl_reg[1]_1\ => \rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_0\,
      \rb_hit_busies.rb_hit_busies_r_lcl_reg[2]\ => \rb_hit_busies.rb_hit_busies_r_lcl_reg[2]\,
      \rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_0\ => \rb_hit_busies.rb_hit_busies_r_lcl_reg[6]_0\,
      \rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_1\ => \^pass_open_bank_r_lcl_reg\,
      \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]\ => \bank_cntrl[0].bank0_n_39\,
      \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_0\ => rb_hit_busy_r_reg_1,
      \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_1\ => auto_pre_r_lcl_reg,
      rb_hit_busies_r(1 downto 0) => rb_hit_busies_r(3 downto 2),
      rb_hit_busy_r_reg => \^rb_hit_busy_r\(0),
      rb_hit_busy_r_reg_0 => \bank_cntrl[0].bank0_n_38\,
      rb_hit_busy_r_reg_1 => \bank_cntrl[0].bank0_n_40\,
      rb_hit_busy_r_reg_2 => \rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_1\,
      rd_this_rank_r(0) => rd_this_rank_r(0),
      rd_wr_r(0) => rd_wr_r(0),
      rd_wr_r_lcl_reg => \bank_cntrl[0].bank0_n_24\,
      rd_wr_r_lcl_reg_0 => \bank_cntrl[0].bank0_n_43\,
      rd_wr_r_lcl_reg_1 => \bank_cntrl[0].bank0_n_46\,
      rd_wr_r_lcl_reg_2 => rd_wr_r_lcl_reg_0,
      \req_bank_r_lcl_reg[2]\(2 downto 0) => \^req_bank_r_lcl_reg[2]\(2 downto 0),
      \req_bank_r_lcl_reg[2]_0\(2 downto 0) => \req_bank_r_lcl_reg[2]_3\(2 downto 0),
      req_bank_rdy_ns => \bank_state0/req_bank_rdy_ns_14\,
      req_bank_rdy_r_reg => req_bank_rdy_r_reg,
      req_bank_rdy_r_reg_0 => req_bank_rdy_r_reg_0,
      req_bank_rdy_r_reg_1 => req_bank_rdy_r_reg_1,
      \req_col_r_reg[9]\(9 downto 0) => \bank_compare0/req_col_r\(9 downto 0),
      \req_col_r_reg[9]_0\(9 downto 0) => \req_col_r_reg[9]\(9 downto 0),
      \req_data_buf_addr_r_reg[3]\(3 downto 0) => req_data_buf_addr_r(3 downto 0),
      \req_data_buf_addr_r_reg[3]_0\(3 downto 0) => \req_data_buf_addr_r_reg[3]\(3 downto 0),
      req_periodic_rd_r(0) => req_periodic_rd_r(0),
      \req_row_r_lcl_reg[13]\(13 downto 12) => \^req_row_r_lcl_reg[13]\(10 downto 9),
      \req_row_r_lcl_reg[13]\(11 downto 9) => req_row_r(11 downto 9),
      \req_row_r_lcl_reg[13]\(8 downto 0) => \^req_row_r_lcl_reg[13]\(8 downto 0),
      \req_row_r_lcl_reg[13]_0\(13 downto 0) => \req_row_r_lcl_reg[13]_0\(13 downto 0),
      req_wr_r_lcl0 => \bank_compare0/req_wr_r_lcl0\,
      \rnk_config_strobe_r_reg[0]\ => \bank_cntrl[3].bank0_n_62\,
      rnk_config_valid_r => \^rnk_config_valid_r\,
      rnk_config_valid_r_lcl_reg => \^rnk_config_valid_r_lcl_reg\,
      row_hit_r_reg => row_hit_r_reg_0,
      row_hit_r_reg_0(0) => row_hit_r_reg_3(0),
      \rtp_timer_r_reg[0]\ => \rtp_timer_r_reg[0]\,
      \rtp_timer_r_reg[1]\ => \rtp_timer_r_reg[1]\,
      tail_r => tail_r,
      use_addr => use_addr,
      wait_for_maint_r => wait_for_maint_r,
      wait_for_maint_r_lcl_reg => \maint_controller.maint_wip_r_lcl_reg_0\,
      wait_for_maint_r_lcl_reg_0 => wait_for_maint_r_lcl_reg,
      wr_this_rank_r(0) => wr_this_rank_r(0)
    );
\bank_cntrl[1].bank0\: entity work.\mig_mig_7series_v4_2_bank_cntrl__parameterized0\
     port map (
      E(0) => \^idle_r\(1),
      Q(1 downto 0) => \^q\(2 downto 1),
      act_this_rank_r(0) => act_this_rank_r(1),
      act_wait_r_lcl_reg => \^row_cmd_wr\(1),
      act_wait_r_lcl_reg_0 => act_wait_r_lcl_reg_0,
      act_wait_r_lcl_reg_1 => \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[1]\,
      act_wait_r_lcl_reg_2(0) => \^grant_r_reg[3]\(1),
      auto_pre_r_lcl_reg => \^auto_pre_r_19\,
      auto_pre_r_lcl_reg_0 => \bank_cntrl[1].bank0_n_47\,
      auto_pre_r_lcl_reg_1 => \rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_0\,
      auto_pre_r_lcl_reg_2 => auto_pre_r_lcl_reg_1,
      auto_pre_r_lcl_reg_3 => \^accept_r_reg\,
      bm_end_r1 => bm_end_r1,
      bm_end_r1_reg => \bank_cntrl[1].bank0_n_43\,
      col_wait_r_reg => col_wait_r_0,
      col_wait_r_reg_0 => col_wait_r_reg_0,
      \compute_tail.tail_r_lcl_reg\ => \compute_tail.tail_r_lcl_reg_2\,
      \compute_tail.tail_r_lcl_reg_0\ => \compute_tail.tail_r_lcl_reg_4\,
      demand_priority_r_reg => \^demand_priority_r_1\,
      demand_priority_r_reg_0 => \bank_cntrl[1].bank0_n_36\,
      demand_priority_r_reg_1 => \maint_controller.maint_wip_r_lcl_reg\,
      demand_priority_r_reg_2 => arb_mux0_n_118,
      demanded_prior_r_reg => \^demanded_prior_r_2\,
      demanded_prior_r_reg_0 => \^demanded_prior_r_reg\,
      demanded_prior_r_reg_1 => \^demanded_prior_r_6\,
      demanded_prior_r_reg_2 => \^demand_priority_r_5\,
      demanded_prior_r_reg_3 => \^demanded_prior_r_reg_0\,
      \grant_r[3]_i_2\ => arb_mux0_n_38,
      \grant_r[3]_i_2_0\ => \bank_cntrl[0].bank0_n_46\,
      \grant_r[3]_i_2_1\ => req_bank_rdy_r_reg,
      \grant_r[3]_i_2_2\ => arb_mux0_n_104,
      \grant_r[3]_i_2_3\ => \bank_cntrl[2].bank0_n_40\,
      granted_col_ns => \arb_row_col0/granted_col_ns\,
      granted_col_r_reg => \bank_cntrl[2].bank0_n_29\,
      granted_col_r_reg_0 => \bank_cntrl[3].bank0_n_27\,
      granted_col_r_reg_1 => \bank_cntrl[0].bank0_n_24\,
      granted_col_r_reg_2 => arb_mux0_n_120,
      granted_col_r_reg_3 => granted_col_r_reg_5,
      granted_col_r_reg_4 => arb_mux0_n_119,
      head_r_lcl_reg => \^head_r\(1),
      head_r_lcl_reg_0 => head_r_lcl_reg_0,
      head_r_lcl_reg_1 => \bank_cntrl[0].bank0_n_38\,
      head_r_lcl_reg_2 => \bank_cntrl[0].bank0_n_40\,
      head_r_lcl_reg_3 => bank_common0_n_17,
      hi_priority => hi_priority,
      \i___34\ => \^p_52_out\,
      \i___34_0\ => \^p_130_out\,
      \i___34_1\ => \^pre_bm_end_r_reg\,
      idle_r_lcl_reg => \^idle_r_lcl_reg\,
      maint_req_r => maint_req_r,
      ofs_rdy_r => \bank_state0/ofs_rdy_r_5\,
      ofs_rdy_r0 => \bank_state0/ofs_rdy_r0\,
      ofs_rdy_r_reg => ofs_rdy_r_reg,
      \order_q_r_reg[0]\ => \bank_cntrl[0].bank0_n_42\,
      \order_q_r_reg[1]\ => \^set_order_q_24\,
      \order_q_r_reg[1]_0\ => \bank_cntrl[0].bank0_n_44\,
      ordered_r_lcl_reg => \bank_cntrl[1].bank0_n_22\,
      pass_open_bank_r_lcl_reg => pass_open_bank_r,
      pass_open_bank_r_lcl_reg_0 => \^rb_hit_busy_r_reg\,
      pass_open_bank_r_lcl_reg_1 => \^periodic_rd_cntr_r\,
      pass_open_bank_r_lcl_reg_2 => \^maint_wip_r\,
      periodic_rd_insert => periodic_rd_insert,
      pre_bm_end_r => pre_bm_end_r,
      pre_bm_end_r_reg => \^pre_bm_end_r_reg_1\,
      pre_bm_end_r_reg_0(0) => sending_pre(1),
      pre_passing_open_bank_r_reg => \^pre_passing_open_bank_r_reg_0\,
      q_entry_ns(0) => \bank_queue0/q_entry_ns\(1),
      \q_entry_r_reg[0]\ => \q_entry_r_reg[0]_4\,
      \q_entry_r_reg[0]_0\ => \q_entry_r_reg[0]_5\,
      \q_entry_r_reg[0]_1\ => \bank_cntrl[0].bank0_n_49\,
      \q_entry_r_reg[0]_2\ => \^periodic_rd_ack_r_lcl_reg\,
      \q_entry_r_reg[1]\ => \q_entry_r_reg[1]_1\,
      \q_entry_r_reg[1]_0\ => \bank_cntrl[1].bank0_n_41\,
      \q_entry_r_reg[1]_1\ => \q_entry_r_reg[1]_3\,
      q_has_priority => q_has_priority_4,
      q_has_priority_r_reg => bank_common0_n_30,
      q_has_rd_3 => q_has_rd_3,
      q_has_rd_r_reg => q_has_rd_r_reg_0,
      \ras_timer_r_reg[0]\ => \ras_timer_r_reg[0]_2\,
      \ras_timer_r_reg[0]_0\ => \^pre_passing_open_bank_r_reg\,
      \ras_timer_r_reg[0]_1\ => \bank_cntrl[3].bank0_n_38\,
      \ras_timer_r_reg[0]_2\ => \bank_cntrl[2].bank0_n_43\,
      \ras_timer_r_reg[0]_3\ => \bank_cntrl[0].bank0_n_26\,
      \ras_timer_r_reg[0]_4\ => \bank_cntrl[2].bank0_n_31\,
      \ras_timer_r_reg[0]_5\ => \bank_cntrl[3].bank0_n_29\,
      \ras_timer_r_reg[1]\ => \bank_cntrl[1].bank0_n_44\,
      \ras_timer_r_reg[1]_0\ => \bank_cntrl[0].bank0_n_27\,
      \ras_timer_r_reg[1]_1\ => \bank_cntrl[3].bank0_n_30\,
      \ras_timer_r_reg[1]_2\ => \bank_cntrl[2].bank0_n_32\,
      ras_timer_zero_r_reg => \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[0]\,
      ras_timer_zero_r_reg_0 => ras_timer_zero_r_reg,
      \rb_hit_busies.rb_hit_busies_r_lcl_reg[2]\ => \^rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_0\,
      \rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_0\ => \rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_1\,
      \rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_1\ => \^idle_r_lcl_reg_1\,
      \rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_2\ => \rb_hit_busies.rb_hit_busies_r_lcl_reg[6]_0\,
      \rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_3\ => \^pass_open_bank_r_lcl_reg\,
      \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]\(1 downto 0) => rb_hit_busies_r_3(3 downto 2),
      \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_0\ => \^idle_r_lcl_reg_0\,
      \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_1\ => rb_hit_busy_r_reg_1,
      \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_2\ => auto_pre_r_lcl_reg,
      \rb_hit_busies.rb_hit_busies_r_lcl_reg[4]\ => \^idle_r_lcl_reg_2\,
      \rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_0\ => \rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_1\,
      \rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_1\ => \^pass_open_bank_r_lcl_reg_0\,
      \rb_hit_busies.rb_hit_busies_r_lcl_reg[5]\ => \bank_cntrl[1].bank0_n_30\,
      \rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_0\ => \^rb_hit_busies.rb_hit_busies_r_lcl_reg[5]\,
      rb_hit_busies_r(0) => rb_hit_busies_r_11(5),
      rb_hit_busies_r_0(0) => rb_hit_busies_r_7(5),
      rb_hit_busy_r_reg => \^rb_hit_busy_r\(1),
      rb_hit_busy_r_reg_0 => \rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_1\,
      rb_hit_busy_r_reg_1 => \^periodic_rd_ack_r\,
      rb_hit_busy_r_reg_2 => \^accept_internal_r\,
      rd_this_rank_r(0) => rd_this_rank_r(1),
      rd_wr_r_lcl_reg => \^rd_wr_r_lcl_reg\(0),
      rd_wr_r_lcl_reg_0 => \bank_cntrl[1].bank0_n_26\,
      rd_wr_r_lcl_reg_1 => rd_wr_r_lcl_reg_0,
      \req_bank_r_lcl_reg[2]\(2 downto 0) => \^req_bank_r_lcl_reg[2]_0\(2 downto 0),
      \req_bank_r_lcl_reg[2]_0\(2 downto 0) => \req_bank_r_lcl_reg[2]_3\(2 downto 0),
      req_bank_rdy_ns => req_bank_rdy_ns,
      req_bank_rdy_ns_1 => \bank_state0/req_bank_rdy_ns\,
      req_bank_rdy_r => \bank_state0/req_bank_rdy_r\,
      req_bank_rdy_r_reg => \bank_cntrl[0].bank0_n_43\,
      \req_col_r_reg[9]\(9 downto 0) => \bank_compare0/req_col_r_2\(9 downto 0),
      \req_col_r_reg[9]_0\(9 downto 0) => \req_col_r_reg[9]\(9 downto 0),
      \req_data_buf_addr_r_reg[3]\(3 downto 0) => req_data_buf_addr_r(8 downto 5),
      \req_data_buf_addr_r_reg[3]_0\(3 downto 0) => \req_data_buf_addr_r_reg[3]\(3 downto 0),
      req_periodic_rd_r(0) => req_periodic_rd_r(1),
      \req_row_r_lcl_reg[13]\(13 downto 9) => \^req_row_r_lcl_reg[13]\(15 downto 11),
      \req_row_r_lcl_reg[13]\(8 downto 0) => req_row_r(22 downto 14),
      \req_row_r_lcl_reg[13]_0\(13 downto 0) => \req_row_r_lcl_reg[13]_0\(13 downto 0),
      req_wr_r_lcl0 => \bank_compare0/req_wr_r_lcl0\,
      req_wr_r_lcl_reg => \^req_wr_r_lcl_reg\(0),
      rnk_config_strobe_ns => \arb_row_col0/rnk_config_strobe_ns\,
      \rnk_config_strobe_r_reg[0]\ => arb_mux0_n_100,
      \rnk_config_strobe_r_reg[0]_0\ => \^demand_priority_r_reg\,
      \rnk_config_strobe_r_reg[0]_1\ => \^rnk_config_valid_r_lcl_reg\,
      row_hit_r_reg => row_hit_r_reg,
      row_hit_r_reg_0(0) => row_hit_r_reg_4(0),
      row_hit_r_reg_1(0) => row_hit_r_reg_5(0),
      \rtp_timer_r_reg[0]\ => \rtp_timer_r_reg[0]\,
      \rtp_timer_r_reg[1]\ => \rtp_timer_r_reg[1]\,
      \starve_limit_cntr_r_reg[0]\ => \^sent_col\,
      tail_r_16 => tail_r_16,
      use_addr => use_addr,
      wait_for_maint_r_13 => wait_for_maint_r_13,
      wait_for_maint_r_lcl_reg => \maint_controller.maint_wip_r_lcl_reg_0\,
      wait_for_maint_r_lcl_reg_0 => wait_for_maint_r_lcl_reg_0,
      wr_this_rank_r(0) => wr_this_rank_r(1)
    );
\bank_cntrl[2].bank0\: entity work.\mig_mig_7series_v4_2_bank_cntrl__parameterized1\
     port map (
      E(0) => \^idle_r\(2),
      Q(1 downto 0) => \^q\(2 downto 1),
      act_this_rank_r(0) => act_this_rank_r(2),
      act_wait_r_lcl_reg => \^row_cmd_wr\(2),
      act_wait_r_lcl_reg_0 => \bank_cntrl[2].bank0_n_47\,
      act_wait_r_lcl_reg_1 => \bank_cntrl[2].bank0_n_64\,
      act_wait_r_lcl_reg_2(0) => \^grant_r_reg[3]\(2),
      auto_pre_r_lcl_reg => \^auto_pre_r_20\,
      auto_pre_r_lcl_reg_0 => \bank_cntrl[2].bank0_n_48\,
      auto_pre_r_lcl_reg_1 => auto_pre_r_lcl_reg_2,
      auto_pre_r_lcl_reg_2 => \^accept_r_reg\,
      bm_end_r1_0 => bm_end_r1_0,
      bm_end_r1_reg => \bank_cntrl[2].bank0_n_31\,
      \cmd_pipe_plus.mc_address_reg[38]\(0) => \^req_row_r_lcl_reg[13]\(12),
      col_wait_r_reg => col_wait_r_4,
      col_wait_r_reg_0 => col_wait_r_reg_1,
      \compute_tail.tail_r_lcl_reg\ => \compute_tail.tail_r_lcl_reg_1\,
      \compute_tail.tail_r_lcl_reg_0\ => \compute_tail.tail_r_lcl_reg_5\,
      demand_priority_r_1 => \^demand_priority_r_1\,
      demand_priority_r_reg => \^demand_priority_r_5\,
      demand_priority_r_reg_0 => \^demand_priority_r_reg\,
      demand_priority_r_reg_1 => \^sent_col\,
      demanded_prior_r_2 => \^demanded_prior_r_2\,
      demanded_prior_r_reg => \^demanded_prior_r_6\,
      demanded_prior_r_reg_0 => \^demanded_prior_r_reg_0\,
      \grant_r[3]_i_3\ => arb_mux0_n_38,
      \grant_r[3]_i_3_0\ => \bank_cntrl[0].bank0_n_46\,
      \grant_r[3]_i_3_1\ => req_bank_rdy_r_reg,
      \grant_r[3]_i_3_2\ => arb_mux0_n_101,
      \grant_r[3]_i_6\(0) => rb_hit_busies_r_3(2),
      granted_col_r_reg => granted_col_r_reg_3,
      granted_col_r_reg_0 => arb_mux0_n_120,
      granted_col_r_reg_1 => granted_col_r_reg_4,
      granted_col_r_reg_2 => arb_mux0_n_119,
      head_r_lcl_reg => \^head_r\(2),
      head_r_lcl_reg_0 => head_r_lcl_reg_1,
      head_r_lcl_reg_1 => \bank_cntrl[0].bank0_n_40\,
      head_r_lcl_reg_2 => \bank_cntrl[0].bank0_n_38\,
      head_r_lcl_reg_3 => bank_common0_n_13,
      hi_priority => hi_priority,
      \i___5_i_4\ => \^pre_bm_end_r_reg_1\,
      \i___5_i_4_0\ => \^p_130_out\,
      \i___5_i_4_1\ => \^pre_bm_end_r_reg\,
      idle_r_lcl_reg => \^idle_r_lcl_reg_1\,
      idle_r_lcl_reg_0 => idle_r_lcl_reg_3,
      maint_req_r => maint_req_r,
      ofs_rdy_r => \bank_state0/ofs_rdy_r_9\,
      ofs_rdy_r0 => \bank_state0/ofs_rdy_r0_0\,
      ofs_rdy_r_reg => \maint_controller.maint_wip_r_lcl_reg\,
      ofs_rdy_r_reg_0 => ofs_rdy_r_reg,
      \order_q_r_reg[0]\ => \bank_cntrl[0].bank0_n_42\,
      \order_q_r_reg[1]\ => \order_q_r_reg[1]\,
      \order_q_r_reg[1]_0\ => \^set_order_q_22\,
      \order_q_r_reg[1]_1\ => \bank_cntrl[0].bank0_n_44\,
      ordered_r_lcl_reg => \bank_cntrl[2].bank0_n_22\,
      override_demand_ns => \^override_demand_ns\,
      override_demand_r => \^override_demand_r\,
      pass_open_bank_r_lcl_reg => \^pass_open_bank_r_lcl_reg\,
      pass_open_bank_r_lcl_reg_0 => \^rb_hit_busy_r_reg_0\,
      pass_open_bank_r_lcl_reg_1 => \^periodic_rd_cntr_r\,
      pass_open_bank_r_lcl_reg_2 => \^maint_wip_r\,
      periodic_rd_insert => periodic_rd_insert,
      \pre_4_1_1T_arb.granted_pre_r_reg\ => \bank_cntrl[1].bank0_n_47\,
      pre_bm_end_r_reg => \^p_52_out\,
      pre_bm_end_r_reg_0(1 downto 0) => sending_pre(2 downto 1),
      pre_passing_open_bank_r_reg => \bank_cntrl[2].bank0_n_43\,
      pre_wait_r_reg => \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[1]\,
      \q_entry_r_reg[0]\ => \q_entry_r_reg[0]_1\,
      \q_entry_r_reg[0]_0\ => \q_entry_r_reg[0]_2\,
      \q_entry_r_reg[0]_1\ => \q_entry_r_reg[0]_6\,
      \q_entry_r_reg[1]\ => \bank_cntrl[2].bank0_n_33\,
      \q_entry_r_reg[1]_0\ => \q_entry_r_reg[1]_0\,
      \q_entry_r_reg[1]_1\ => \^periodic_rd_ack_r_lcl_reg\,
      \q_entry_r_reg[1]_2\ => \bank_cntrl[0].bank0_n_29\,
      \q_entry_r_reg[1]_3\ => \bank_cntrl[0].bank0_n_30\,
      q_has_priority => q_has_priority_8,
      q_has_priority_r_reg => bank_common0_n_28,
      q_has_rd_7 => q_has_rd_7,
      q_has_rd_r_reg => q_has_rd_r_reg_1,
      \ras_timer_r_reg[0]\ => \bank_cntrl[3].bank0_n_41\,
      \ras_timer_r_reg[0]_0\ => \^rb_hit_busies.rb_hit_busies_r_lcl_reg[5]\,
      \ras_timer_r_reg[0]_1\ => \^pre_passing_open_bank_r_reg\,
      \ras_timer_r_reg[0]_2\ => \ras_timer_r_reg[0]_1\,
      \ras_timer_r_reg[0]_3\ => \bank_cntrl[1].bank0_n_43\,
      \ras_timer_r_reg[0]_4\ => \bank_cntrl[0].bank0_n_26\,
      \ras_timer_r_reg[0]_5\ => \bank_cntrl[3].bank0_n_29\,
      \ras_timer_r_reg[1]\ => \bank_cntrl[2].bank0_n_32\,
      \ras_timer_r_reg[1]_0\ => \bank_cntrl[1].bank0_n_44\,
      \ras_timer_r_reg[1]_1\ => \bank_cntrl[0].bank0_n_27\,
      \ras_timer_r_reg[1]_2\ => \bank_cntrl[3].bank0_n_30\,
      ras_timer_zero_r_reg => \bank_cntrl[2].bank0_n_46\,
      ras_timer_zero_r_reg_0 => \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[0]\,
      ras_timer_zero_r_reg_1 => ras_timer_zero_r_reg_0,
      \rb_hit_busies.rb_hit_busies_r_lcl_reg[2]\ => \bank_cntrl[2].bank0_n_40\,
      \rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_0\ => \rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_2\,
      \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]\ => \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_0\,
      \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_0\ => \^idle_r_lcl_reg_0\,
      \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_1\ => rb_hit_busy_r_reg_1,
      \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_2\ => auto_pre_r_lcl_reg,
      \rb_hit_busies.rb_hit_busies_r_lcl_reg[4]\ => \rb_hit_busies.rb_hit_busies_r_lcl_reg[4]\(0),
      \rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_0\ => \^idle_r_lcl_reg_2\,
      \rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_1\ => \rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_1\,
      \rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_2\ => \^pass_open_bank_r_lcl_reg_0\,
      \rb_hit_busies.rb_hit_busies_r_lcl_reg[5]\ => \bank_cntrl[2].bank0_n_34\,
      \rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_0\ => \^idle_r_lcl_reg\,
      \rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_1\ => \rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_1\,
      \rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_2\ => \rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_0\,
      \rb_hit_busies.rb_hit_busies_r_lcl_reg[6]\ => \bank_cntrl[2].bank0_n_41\,
      rb_hit_busies_r(1) => rb_hit_busies_r_7(5),
      rb_hit_busies_r(0) => rb_hit_busies_r_7(3),
      rb_hit_busies_r_0(0) => rb_hit_busies_r_11(6),
      rb_hit_busies_r_1(0) => rb_hit_busies_r(2),
      rb_hit_busy_r_reg => \^rb_hit_busy_r\(2),
      rb_hit_busy_r_reg_0 => \rb_hit_busies.rb_hit_busies_r_lcl_reg[6]_0\,
      rb_hit_busy_r_reg_1 => \^periodic_rd_ack_r\,
      rb_hit_busy_r_reg_2 => \^accept_internal_r\,
      rd_this_rank_r(0) => rd_this_rank_r(2),
      rd_wr_r_lcl_reg => \^rd_wr_r_lcl_reg\(1),
      rd_wr_r_lcl_reg_0 => \bank_cntrl[2].bank0_n_29\,
      rd_wr_r_lcl_reg_1 => rd_wr_r_lcl_reg_0,
      \req_bank_r_lcl_reg[2]\(2 downto 0) => \^req_bank_r_lcl_reg[2]_1\(2 downto 0),
      \req_bank_r_lcl_reg[2]_0\(2 downto 0) => \req_bank_r_lcl_reg[2]_3\(2 downto 0),
      req_bank_rdy_ns => \bank_state0/req_bank_rdy_ns\,
      req_bank_rdy_r_reg => \bank_cntrl[0].bank0_n_43\,
      \req_col_r_reg[9]\(9 downto 0) => \bank_compare0/req_col_r_6\(9 downto 0),
      \req_col_r_reg[9]_0\(9 downto 0) => \req_col_r_reg[9]\(9 downto 0),
      \req_data_buf_addr_r_reg[3]\(3 downto 0) => req_data_buf_addr_r(13 downto 10),
      \req_data_buf_addr_r_reg[3]_0\(3 downto 0) => \req_data_buf_addr_r_reg[3]\(3 downto 0),
      req_periodic_rd_r(0) => req_periodic_rd_r(2),
      \req_row_r_lcl_reg[13]\(13 downto 12) => \^req_row_r_lcl_reg[13]\(17 downto 16),
      \req_row_r_lcl_reg[13]\(11 downto 0) => req_row_r(39 downto 28),
      \req_row_r_lcl_reg[13]_0\(13 downto 0) => \req_row_r_lcl_reg[13]_0\(13 downto 0),
      req_wr_r_lcl0 => \bank_compare0/req_wr_r_lcl0\,
      req_wr_r_lcl_reg => \^req_wr_r_lcl_reg\(1),
      rnk_config_valid_r_lcl_reg => \bank_cntrl[1].bank0_n_36\,
      rnk_config_valid_r_lcl_reg_0 => arb_mux0_n_100,
      row_cmd_wr(0) => \^row_cmd_wr\(1),
      row_hit_r_reg => row_hit_r_reg_1,
      row_hit_r_reg_0(0) => row_hit_r_reg_6(0),
      \rtp_timer_r_reg[0]\ => \rtp_timer_r_reg[0]\,
      tail_r_17 => tail_r_17,
      use_addr => use_addr,
      wait_for_maint_r_14 => wait_for_maint_r_14,
      wait_for_maint_r_lcl_reg => \maint_controller.maint_wip_r_lcl_reg_0\,
      wait_for_maint_r_lcl_reg_0 => wait_for_maint_r_lcl_reg_1,
      wr_this_rank_r(0) => wr_this_rank_r(2)
    );
\bank_cntrl[3].bank0\: entity work.\mig_mig_7series_v4_2_bank_cntrl__parameterized2\
     port map (
      E(0) => \^idle_r\(3),
      Q(1) => \^q\(3),
      Q(0) => \^q\(0),
      act_this_rank_r(0) => act_this_rank_r(3),
      act_wait_r_lcl_reg => \^row_cmd_wr\(3),
      act_wait_r_lcl_reg_0 => act_wait_r_lcl_reg_1,
      act_wait_r_lcl_reg_1 => \bank_cntrl[3].bank0_n_61\,
      act_wait_r_lcl_reg_2(1 downto 0) => \^grant_r_reg[3]\(3 downto 2),
      auto_pre_r_lcl_reg => \^auto_pre_r_21\,
      auto_pre_r_lcl_reg_0 => \bank_cntrl[3].bank0_n_46\,
      auto_pre_r_lcl_reg_1 => auto_pre_r_lcl_reg,
      auto_pre_r_lcl_reg_2 => auto_pre_r_lcl_reg_3,
      auto_pre_r_lcl_reg_3 => \^accept_r_reg\,
      bm_end_r1_1 => bm_end_r1_1,
      bm_end_r1_reg => \bank_cntrl[3].bank0_n_29\,
      \cmd_pipe_plus.mc_address[10]_i_2\(0) => req_row_r(38),
      col_wait_r_reg => col_wait_r_8,
      col_wait_r_reg_0 => col_wait_r_reg_2,
      \compute_tail.tail_r_lcl_reg\ => \compute_tail.tail_r_lcl_reg\,
      \compute_tail.tail_r_lcl_reg_0\ => \compute_tail.tail_r_lcl_reg_6\,
      \compute_tail.tail_r_lcl_reg_1\ => \^pre_bm_end_r_reg_1\,
      \compute_tail.tail_r_lcl_reg_2\ => \^p_130_out\,
      \compute_tail.tail_r_lcl_reg_3\ => \^p_52_out\,
      demand_priority_r => \^demand_priority_r\,
      demand_priority_r_reg => \^demand_priority_r_9\,
      demand_priority_r_reg_0 => \bank_cntrl[3].bank0_n_62\,
      demand_priority_r_reg_1 => \maint_controller.maint_wip_r_lcl_reg\,
      demand_priority_r_reg_2 => \^sent_col\,
      demanded_prior_r => \^demanded_prior_r\,
      demanded_prior_r_0 => \bank_state0/demanded_prior_r\,
      demanded_prior_r_reg => \^demanded_prior_r_reg\,
      \grant_r[3]_i_5\ => \bank_cntrl[2].bank0_n_41\,
      \grant_r[3]_i_5_0\ => arb_mux0_n_38,
      \grant_r[3]_i_5_1\ => \bank_cntrl[0].bank0_n_46\,
      \grant_r[3]_i_5_2\ => req_bank_rdy_r_reg,
      \grant_r[3]_i_5_3\ => arb_mux0_n_103,
      \grant_r[3]_i_6\(0) => rb_hit_busies_r_3(3),
      \grant_r_reg[3]\ => \bank_cntrl[3].bank0_n_63\,
      granted_col_r_reg => arb_mux0_n_120,
      granted_col_r_reg_0 => granted_col_r_reg_2,
      granted_col_r_reg_1 => arb_mux0_n_119,
      head_r_lcl_reg => \^head_r\(3),
      head_r_lcl_reg_0 => head_r_lcl_reg_2,
      head_r_lcl_reg_1 => \bank_cntrl[0].bank0_n_38\,
      head_r_lcl_reg_2 => bank_common0_n_11,
      head_r_lcl_reg_3 => \bank_cntrl[0].bank0_n_40\,
      hi_priority => hi_priority,
      idle_r_lcl_reg => \^idle_r_lcl_reg_0\,
      maint_req_r => maint_req_r,
      ofs_rdy_r => \bank_state0/ofs_rdy_r_13\,
      ofs_rdy_r0 => \bank_state0/ofs_rdy_r0_1\,
      ofs_rdy_r_reg => ofs_rdy_r_reg,
      \order_q_r_reg[0]\ => \bank_cntrl[0].bank0_n_42\,
      \order_q_r_reg[1]\ => \^set_order_q\,
      \order_q_r_reg[1]_0\ => \bank_cntrl[0].bank0_n_44\,
      ordered_r_lcl_reg => \bank_cntrl[3].bank0_n_21\,
      pass_open_bank_r_lcl_reg => pass_open_bank_r_10,
      pass_open_bank_r_lcl_reg_0 => pass_open_bank_r_lcl_reg_2,
      pass_open_bank_r_lcl_reg_1 => \^periodic_rd_cntr_r\,
      pass_open_bank_r_lcl_reg_2 => \^maint_wip_r\,
      periodic_rd_insert => periodic_rd_insert,
      \pre_4_1_1T_arb.granted_pre_ns\ => \arb_row_col0/pre_4_1_1T_arb.granted_pre_ns\,
      \pre_4_1_1T_arb.granted_pre_r_reg\ => \bank_cntrl[0].bank0_n_53\,
      \pre_4_1_1T_arb.granted_pre_r_reg_0\ => \bank_cntrl[2].bank0_n_46\,
      pre_bm_end_r_11 => pre_bm_end_r_11,
      pre_bm_end_r_reg => \^pre_bm_end_r_reg\,
      pre_bm_end_r_reg_0 => pre_bm_end_r_reg_0,
      pre_bm_end_r_reg_1 => pre_bm_end_r_reg_2,
      pre_bm_end_r_reg_2(0) => \^grant_r_reg[3]_0\(0),
      pre_passing_open_bank_r_reg => \bank_cntrl[3].bank0_n_41\,
      pre_wait_r_reg => \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[1]\,
      \q_entry_r_reg[0]\ => \q_entry_r_reg[0]\,
      \q_entry_r_reg[0]_0\ => \q_entry_r_reg[0]_0\,
      \q_entry_r_reg[0]_1\ => \bank_cntrl[0].bank0_n_33\,
      \q_entry_r_reg[1]\ => \q_entry_r_reg[1]\,
      \q_entry_r_reg[1]_0\ => \bank_cntrl[0].bank0_n_28\,
      \q_entry_r_reg[1]_1\ => \q_entry_r_reg[1]_2\,
      \q_entry_r_reg[1]_2\ => \bank_cntrl[0].bank0_n_34\,
      \q_entry_r_reg[1]_3\ => \^periodic_rd_ack_r_lcl_reg\,
      \q_entry_r_reg[1]_4\ => \q_entry_r_reg[1]_4\,
      q_has_priority => q_has_priority_12,
      q_has_priority_r_reg => bank_common0_n_24,
      q_has_rd_12 => q_has_rd_12,
      q_has_rd_r_reg => q_has_rd_r_reg_2,
      \ras_timer_r_reg[0]\ => \ras_timer_r_reg[0]\,
      \ras_timer_r_reg[0]_0\ => \^pre_passing_open_bank_r_reg\,
      \ras_timer_r_reg[0]_1\ => \bank_cntrl[1].bank0_n_30\,
      \ras_timer_r_reg[0]_2\ => \bank_cntrl[2].bank0_n_43\,
      \ras_timer_r_reg[0]_3\ => \bank_cntrl[2].bank0_n_31\,
      \ras_timer_r_reg[0]_4\ => \bank_cntrl[1].bank0_n_43\,
      \ras_timer_r_reg[0]_5\ => \bank_cntrl[0].bank0_n_26\,
      \ras_timer_r_reg[0]_6\ => \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[0]\,
      \ras_timer_r_reg[1]\ => \bank_cntrl[3].bank0_n_30\,
      \ras_timer_r_reg[1]_0\ => \bank_cntrl[2].bank0_n_32\,
      \ras_timer_r_reg[1]_1\ => \bank_cntrl[1].bank0_n_44\,
      \ras_timer_r_reg[1]_2\ => \bank_cntrl[0].bank0_n_27\,
      ras_timer_zero_r_reg => ras_timer_zero_r_reg_1,
      \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]\ => \bank_cntrl[3].bank0_n_38\,
      \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_0\ => \^rb_hit_busies.rb_hit_busies_r_lcl_reg[3]\,
      \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_1\ => \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_1\,
      \rb_hit_busies.rb_hit_busies_r_lcl_reg[4]\ => \^rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_0\,
      \rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_0\ => \^idle_r_lcl_reg_2\,
      \rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_1\ => \rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_1\,
      \rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_2\ => \^pass_open_bank_r_lcl_reg_0\,
      \rb_hit_busies.rb_hit_busies_r_lcl_reg[5]\ => \^idle_r_lcl_reg\,
      \rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_0\ => \rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_1\,
      \rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_1\ => \rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_0\,
      \rb_hit_busies.rb_hit_busies_r_lcl_reg[6]\(1 downto 0) => rb_hit_busies_r_11(6 downto 5),
      \rb_hit_busies.rb_hit_busies_r_lcl_reg[6]_0\ => \rb_hit_busies.rb_hit_busies_r_lcl_reg[6]\,
      \rb_hit_busies.rb_hit_busies_r_lcl_reg[6]_1\ => \^idle_r_lcl_reg_1\,
      \rb_hit_busies.rb_hit_busies_r_lcl_reg[6]_2\ => \rb_hit_busies.rb_hit_busies_r_lcl_reg[6]_0\,
      \rb_hit_busies.rb_hit_busies_r_lcl_reg[6]_3\ => \^pass_open_bank_r_lcl_reg\,
      rb_hit_busies_r(0) => rb_hit_busies_r(3),
      rb_hit_busies_r_1(0) => rb_hit_busies_r_7(3),
      rb_hit_busy_r_reg => \^rb_hit_busy_r\(3),
      rb_hit_busy_r_reg_0 => rb_hit_busy_r_reg_1,
      rb_hit_busy_r_reg_1 => \^periodic_rd_ack_r\,
      rb_hit_busy_r_reg_2 => \^accept_internal_r\,
      rd_this_rank_r(0) => rd_this_rank_r(3),
      rd_wr_r_lcl_reg => \^rd_wr_r_lcl_reg\(2),
      rd_wr_r_lcl_reg_0 => \bank_cntrl[3].bank0_n_27\,
      rd_wr_r_lcl_reg_1 => rd_wr_r_lcl_reg_0,
      \req_bank_r_lcl_reg[2]\(2 downto 0) => \^req_bank_r_lcl_reg[2]_2\(2 downto 0),
      \req_bank_r_lcl_reg[2]_0\(2 downto 0) => \req_bank_r_lcl_reg[2]_3\(2 downto 0),
      req_bank_rdy_ns => \bank_state0/req_bank_rdy_ns_14\,
      req_bank_rdy_r_reg => \bank_cntrl[0].bank0_n_43\,
      \req_col_r_reg[9]\(9 downto 0) => \bank_compare0/req_col_r_10\(9 downto 0),
      \req_col_r_reg[9]_0\(9 downto 0) => \req_col_r_reg[9]\(9 downto 0),
      \req_data_buf_addr_r_reg[3]\(3 downto 0) => req_data_buf_addr_r(18 downto 15),
      \req_data_buf_addr_r_reg[3]_0\(3 downto 0) => \req_data_buf_addr_r_reg[3]\(3 downto 0),
      req_periodic_rd_r(0) => req_periodic_rd_r(3),
      \req_row_r_lcl_reg[13]\(13 downto 12) => \^req_row_r_lcl_reg[13]\(19 downto 18),
      \req_row_r_lcl_reg[13]\(11 downto 0) => req_row_r(53 downto 42),
      \req_row_r_lcl_reg[13]_0\(13 downto 0) => \req_row_r_lcl_reg[13]_0\(13 downto 0),
      req_wr_r_lcl0 => \bank_compare0/req_wr_r_lcl0\,
      req_wr_r_lcl_reg => \^req_wr_r_lcl_reg\(2),
      row_cmd_wr(0) => \^row_cmd_wr\(2),
      row_hit_r_reg => row_hit_r_reg_2,
      row_hit_r_reg_0(0) => row_hit_r_reg_7(0),
      \rtp_timer_r_reg[0]\ => \rtp_timer_r_reg[0]\,
      tail_r_18 => tail_r_18,
      use_addr => use_addr,
      wait_for_maint_r_15 => wait_for_maint_r_15,
      wait_for_maint_r_lcl_reg => \maint_controller.maint_wip_r_lcl_reg_0\,
      wait_for_maint_r_lcl_reg_0 => wait_for_maint_r_lcl_reg_2,
      wr_this_rank_r(0) => wr_this_rank_r(3)
    );
bank_common0: entity work.mig_mig_7series_v4_2_bank_common
     port map (
      E(0) => \^idle_r\(3),
      Q(3 downto 0) => \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[3]\(3 downto 0),
      accept_internal_r_reg_0 => \^accept_internal_r\,
      accept_ns => accept_ns,
      accept_r_reg_0 => \^accept_r_reg\,
      accept_r_reg_1 => bank_common0_n_11,
      accept_r_reg_2 => bank_common0_n_13,
      accept_r_reg_3 => bank_common0_n_15,
      accept_r_reg_4 => bank_common0_n_17,
      clear_periodic_rd_request => clear_periodic_rd_request,
      cmd(1 downto 0) => cmd(1 downto 0),
      \generate_maint_cmds.insert_maint_r_lcl_reg_0\ => \^generate_maint_cmds.insert_maint_r_lcl_reg\,
      head_r(3 downto 0) => \^head_r\(3 downto 0),
      hi_priority => hi_priority,
      \i___3_i_2\ => \bank_cntrl[0].bank0_n_39\,
      \i___4_i_1\ => \^rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_0\,
      \i___5_i_1\ => \bank_cntrl[2].bank0_n_34\,
      \i___6_i_1\ => \^rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_0\,
      idle_r_lcl_reg => bank_common0_n_26,
      \maint_controller.maint_hit_busies_r_reg[3]_0\(3 downto 0) => \maint_controller.maint_hit_busies_r_reg[3]\(3 downto 0),
      \maint_controller.maint_hit_busies_r_reg[3]_1\(3 downto 0) => \maint_controller.maint_hit_busies_r_reg[3]_0\(3 downto 0),
      \maint_controller.maint_wip_r_lcl_reg_0\ => \^maint_wip_r\,
      \maint_controller.maint_wip_r_lcl_reg_1\ => \maint_controller.maint_wip_r_lcl_reg\,
      \maint_controller.maint_wip_r_lcl_reg_2\ => \maint_controller.maint_wip_r_lcl_reg_0\,
      \maint_controller.maint_wip_r_lcl_reg_3\ => \maint_controller.maint_wip_r_lcl_reg_1\,
      maint_req_r => maint_req_r,
      maint_srx_r => maint_srx_r,
      maint_zq_r => maint_zq_r,
      p_9_in => p_9_in,
      periodic_rd_ack_r_lcl_reg_0 => \^periodic_rd_ack_r\,
      periodic_rd_ack_r_lcl_reg_1 => \^periodic_rd_ack_r_lcl_reg\,
      periodic_rd_cntr_r_reg_0 => \^periodic_rd_cntr_r\,
      periodic_rd_cntr_r_reg_1 => periodic_rd_cntr_r_reg,
      periodic_rd_cntr_r_reg_2 => periodic_rd_cntr_r_reg_0,
      periodic_rd_insert => periodic_rd_insert,
      periodic_rd_r => periodic_rd_r,
      \periodic_read_request.periodic_rd_grant_r\ => \periodic_read_request.periodic_rd_grant_r\,
      \q_entry_r_reg[0]\(0) => \^idle_r\(2),
      \q_entry_r_reg[0]_0\(0) => \^idle_r\(0),
      \q_entry_r_reg[0]_1\(0) => \^idle_r\(1),
      q_has_priority => q_has_priority_12,
      q_has_priority_0 => q_has_priority,
      q_has_priority_1 => q_has_priority_8,
      q_has_priority_2 => q_has_priority_4,
      q_has_priority_r_reg => bank_common0_n_24,
      q_has_priority_r_reg_0 => bank_common0_n_25,
      q_has_priority_r_reg_1 => bank_common0_n_28,
      q_has_priority_r_reg_2 => bank_common0_n_30,
      rb_hit_busy_r(3 downto 0) => \^rb_hit_busy_r\(3 downto 0),
      rb_hit_busy_r_reg => \^rb_hit_busy_r_reg_0\,
      rb_hit_busy_r_reg_0 => \^rb_hit_busy_r_reg\,
      req_wr_r_lcl0 => \bank_compare0/req_wr_r_lcl0\,
      \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[0]_0\ => \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[0]\,
      \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[1]_0\ => \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[1]\,
      \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[3]_0\ => \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[3]_0\,
      \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[3]_1\ => \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[3]_1\,
      \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[4]_0\ => \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[4]\,
      \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[4]_1\ => \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[4]_0\,
      \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[7]_0\ => \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[7]\,
      \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[7]_1\(1 downto 0) => \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[7]_0\(1 downto 0),
      set_order_q => \^set_order_q\,
      set_order_q_22 => \^set_order_q_22\,
      set_order_q_23 => \^set_order_q_23\,
      set_order_q_24 => \^set_order_q_24\,
      use_addr => use_addr,
      was_priority_reg_0 => was_priority_reg,
      was_wr => was_wr
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mig_mig_7series_v4_2_ddr_mc_phy is
  port (
    out_dqs_4 : out STD_LOGIC;
    ts_dqs_4 : out STD_LOGIC;
    A_rst_primitives_reg : out STD_LOGIC;
    mem_dq_out : out STD_LOGIC_VECTOR ( 94 downto 0 );
    mem_dq_ts : out STD_LOGIC_VECTOR ( 71 downto 0 );
    in0 : out STD_LOGIC_VECTOR ( 7 downto 0 );
    idelay_ld_rst : out STD_LOGIC;
    out_dqs_5 : out STD_LOGIC;
    ts_dqs_5 : out STD_LOGIC;
    A_rst_primitives_reg_0 : out STD_LOGIC;
    idelay_ld_rst_0 : out STD_LOGIC;
    out_dqs_6 : out STD_LOGIC;
    ts_dqs_6 : out STD_LOGIC;
    A_rst_primitives_reg_1 : out STD_LOGIC;
    idelay_ld_rst_1 : out STD_LOGIC;
    out_dqs_7 : out STD_LOGIC;
    ts_dqs_7 : out STD_LOGIC;
    A_rst_primitives_reg_2 : out STD_LOGIC;
    idelay_ld_rst_2 : out STD_LOGIC;
    out_dqs_0 : out STD_LOGIC;
    ts_dqs_0 : out STD_LOGIC;
    A_rst_primitives_reg_3 : out STD_LOGIC;
    idelay_ld_rst_3 : out STD_LOGIC;
    out_dqs_1 : out STD_LOGIC;
    ts_dqs_1 : out STD_LOGIC;
    A_rst_primitives_reg_4 : out STD_LOGIC;
    idelay_ld_rst_4 : out STD_LOGIC;
    out_dqs_2 : out STD_LOGIC;
    ts_dqs_2 : out STD_LOGIC;
    A_rst_primitives_reg_5 : out STD_LOGIC;
    idelay_ld_rst_5 : out STD_LOGIC;
    out_dqs_3 : out STD_LOGIC;
    ts_dqs_3 : out STD_LOGIC;
    A_rst_primitives_reg_6 : out STD_LOGIC;
    idelay_ld_rst_6 : out STD_LOGIC;
    phy_mc_ctl_full : out STD_LOGIC;
    rst_tmp : out STD_LOGIC;
    if_empty : out STD_LOGIC;
    \my_empty_reg[1]\ : out STD_LOGIC;
    phy_mc_data_full : out STD_LOGIC;
    \my_empty_reg[1]_0\ : out STD_LOGIC;
    \my_empty_reg[1]_1\ : out STD_LOGIC;
    \my_empty_reg[1]_2\ : out STD_LOGIC;
    A_rst_primitives_reg_7 : out STD_LOGIC;
    \my_empty_reg[1]_3\ : out STD_LOGIC;
    \my_empty_reg[1]_4\ : out STD_LOGIC;
    \my_empty_reg[1]_5\ : out STD_LOGIC;
    \my_empty_reg[1]_6\ : out STD_LOGIC;
    \my_empty_reg[1]_7\ : out STD_LOGIC;
    \my_empty_reg[1]_8\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_5\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_6\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_5\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_6\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_5\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_6\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_5\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_6\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_5\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_6\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_5\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_6\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_5\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_6\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_5\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_6\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_5\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_6\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_5\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_6\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_5\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_6\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_5\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_6\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_5\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_6\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_5\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_6\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_5\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_6\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_5\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_6\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_5\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_6\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_5\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_6\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_5\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_6\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_5\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_6\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_5\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_6\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_5\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_6\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_5\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_6\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_5\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_6\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_5\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_6\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_5\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_6\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_5\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_6\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_5\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_6\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_5\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_6\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_5\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_6\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_5\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_6\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_5\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_6\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_5\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_6\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_5\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_6\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_5\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_6\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_5\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_6\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_5\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_6\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_5\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_6\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_5\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_6\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_5\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_6\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_5\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_6\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_5\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_6\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_5\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_6\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_5\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_6\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_5\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_6\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_5\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_6\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_5\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_6\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_5\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_6\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_5\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_6\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_5\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_6\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_5\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_6\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_5\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_6\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_5\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_6\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_5\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_6\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_5\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_6\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_5\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_6\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_0\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_1\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_2\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_3\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_4\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_5\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_6\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_7\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_8\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_9\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_10\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_11\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_12\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_13\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_14\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_15\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_16\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_17\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_18\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_19\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_20\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_21\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_22\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_23\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_24\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_25\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_26\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_27\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_28\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_29\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_30\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_31\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_32\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_33\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_34\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_35\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_36\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_37\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_38\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_39\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_40\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_41\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_42\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_43\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_44\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_45\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_46\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_47\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_48\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_49\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_50\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_51\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_52\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_53\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_54\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_55\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_56\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_57\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_58\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_59\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_60\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_61\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_62\ : out STD_LOGIC;
    phy_rddata_en : out STD_LOGIC;
    \rd_ptr_reg[3]\ : out STD_LOGIC_VECTOR ( 63 downto 0 );
    \rd_ptr_reg[3]_0\ : out STD_LOGIC_VECTOR ( 63 downto 0 );
    \rd_ptr_reg[3]_1\ : out STD_LOGIC_VECTOR ( 63 downto 0 );
    \rd_ptr_reg[3]_2\ : out STD_LOGIC_VECTOR ( 63 downto 0 );
    \pi_counter_read_val_reg[5]\ : out STD_LOGIC_VECTOR ( 5 downto 0 );
    \rd_ptr_reg[3]_3\ : out STD_LOGIC_VECTOR ( 63 downto 0 );
    \rd_ptr_reg[3]_4\ : out STD_LOGIC_VECTOR ( 63 downto 0 );
    \rd_ptr_reg[3]_5\ : out STD_LOGIC_VECTOR ( 63 downto 0 );
    \rd_ptr_reg[3]_6\ : out STD_LOGIC_VECTOR ( 63 downto 0 );
    \pi_counter_read_val_reg[5]_0\ : out STD_LOGIC_VECTOR ( 5 downto 0 );
    mem_out : out STD_LOGIC_VECTOR ( 11 downto 0 );
    \rd_ptr_reg[3]_7\ : out STD_LOGIC_VECTOR ( 35 downto 0 );
    \mcGo_r_reg[15]_0\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    \rd_mux_sel_r_reg[2]_63\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_64\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_65\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_66\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_67\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_68\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_69\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_70\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_71\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_72\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_73\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_74\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_75\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_76\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_77\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_78\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_79\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_80\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_81\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_82\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_83\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_84\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_85\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_86\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_87\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_88\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_89\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_90\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_91\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_92\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_93\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_94\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_95\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_96\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_97\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_98\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_99\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_100\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_101\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_102\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_103\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_104\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_105\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_106\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_107\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_108\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_109\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_110\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_111\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_112\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_113\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_114\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_115\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_116\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_117\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_118\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_119\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_120\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_121\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_122\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_123\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_124\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_125\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_126\ : out STD_LOGIC;
    \po_counter_read_val_reg[0]\ : out STD_LOGIC;
    \po_counter_read_val_reg[1]\ : out STD_LOGIC;
    \po_counter_read_val_reg[2]\ : out STD_LOGIC;
    \po_counter_read_val_reg[3]\ : out STD_LOGIC;
    \po_counter_read_val_reg[4]\ : out STD_LOGIC;
    \po_counter_read_val_reg[5]\ : out STD_LOGIC;
    \po_counter_read_val_reg[6]\ : out STD_LOGIC;
    \po_counter_read_val_reg[7]\ : out STD_LOGIC;
    \po_counter_read_val_reg[8]\ : out STD_LOGIC;
    p_0_out : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_0\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_1\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_2\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_3\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_4\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_5\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_6\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_7\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_8\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_9\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_10\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_11\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_12\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_13\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_14\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_15\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_16\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_17\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_18\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_19\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_20\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_21\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_22\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_23\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_24\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_25\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_26\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_27\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_28\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_29\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_30\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_31\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_32\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_33\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_34\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_35\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_36\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_37\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_38\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_39\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_40\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_41\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_42\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_43\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_44\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_45\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_46\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_47\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_48\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_49\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_50\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_51\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_52\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_53\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_54\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_55\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_56\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_57\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_58\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_59\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_60\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_61\ : out STD_LOGIC;
    ddr_ck_out : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \my_empty_reg[1]_9\ : out STD_LOGIC;
    \rd_ptr_reg[3]_8\ : out STD_LOGIC_VECTOR ( 23 downto 0 );
    of_ctl_full_v : out STD_LOGIC_VECTOR ( 0 to 0 );
    \po_counter_read_val_reg[8]_0\ : in STD_LOGIC;
    \po_counter_read_val_reg[8]_1\ : in STD_LOGIC;
    \po_counter_read_val_reg[8]_2\ : in STD_LOGIC;
    \po_counter_read_val_reg[8]_3\ : in STD_LOGIC;
    freq_refclk : in STD_LOGIC;
    mem_refclk : in STD_LOGIC;
    sync_pulse : in STD_LOGIC;
    \entry_cnt_reg[4]\ : in STD_LOGIC;
    \my_full_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
    \my_full_reg[3]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \my_full_reg[3]_1\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \my_full_reg[3]_2\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \my_full_reg[3]_3\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
    \po_counter_read_val_reg[8]_4\ : in STD_LOGIC;
    \po_counter_read_val_reg[8]_5\ : in STD_LOGIC;
    \po_counter_read_val_reg[8]_6\ : in STD_LOGIC;
    \po_counter_read_val_reg[8]_7\ : in STD_LOGIC;
    D1 : in STD_LOGIC_VECTOR ( 3 downto 0 );
    D3 : in STD_LOGIC_VECTOR ( 3 downto 0 );
    D4 : in STD_LOGIC_VECTOR ( 3 downto 0 );
    D5 : in STD_LOGIC_VECTOR ( 3 downto 0 );
    D6 : in STD_LOGIC_VECTOR ( 7 downto 0 );
    D7 : in STD_LOGIC_VECTOR ( 3 downto 0 );
    D8 : in STD_LOGIC_VECTOR ( 3 downto 0 );
    \rd_ptr_reg[3]_9\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
    phy_ctl_wr_i2 : in STD_LOGIC;
    pll_locked : in STD_LOGIC;
    phy_read_calib : in STD_LOGIC;
    phy_mc_ctl_full_r_reg : in STD_LOGIC;
    phy_write_calib : in STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 10 downto 0 );
    phy_mc_ctl_full_r_reg_0 : in STD_LOGIC_VECTOR ( 5 downto 0 );
    \input_[9].iserdes_dq_.iserdesdq\ : in STD_LOGIC;
    mem_dq_in : in STD_LOGIC_VECTOR ( 63 downto 0 );
    idelay_inc : in STD_LOGIC;
    LD0 : in STD_LOGIC;
    CLKB0 : in STD_LOGIC;
    \pi_dqs_found_lanes_r1_reg[0]\ : in STD_LOGIC;
    \pi_dqs_found_lanes_r1_reg[0]_0\ : in STD_LOGIC;
    \pi_dqs_found_lanes_r1_reg[0]_1\ : in STD_LOGIC;
    \pi_dqs_found_lanes_r1_reg[0]_2\ : in STD_LOGIC;
    mem_dqs_in : in STD_LOGIC_VECTOR ( 7 downto 0 );
    ififo_rst_reg : in STD_LOGIC;
    COUNTERLOADVAL : in STD_LOGIC_VECTOR ( 5 downto 0 );
    \po_counter_read_val_reg[8]_8\ : in STD_LOGIC;
    \po_counter_read_val_reg[8]_9\ : in STD_LOGIC;
    \po_counter_read_val_reg[8]_10\ : in STD_LOGIC;
    \my_empty_reg[7]\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \my_empty_reg[7]_0\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \my_empty_reg[7]_1\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \my_empty_reg[7]_2\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \my_empty_reg[7]_3\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \my_empty_reg[7]_4\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \my_empty_reg[7]_5\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \my_empty_reg[7]_6\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    phy_if_reset : in STD_LOGIC;
    \input_[9].iserdes_dq_.iserdesdq_0\ : in STD_LOGIC;
    LD0_7 : in STD_LOGIC;
    CLKB0_7 : in STD_LOGIC;
    \pi_dqs_found_lanes_r1_reg[1]\ : in STD_LOGIC;
    \pi_dqs_found_lanes_r1_reg[1]_0\ : in STD_LOGIC;
    \pi_dqs_found_lanes_r1_reg[1]_1\ : in STD_LOGIC;
    \pi_dqs_found_lanes_r1_reg[1]_2\ : in STD_LOGIC;
    ififo_rst_reg_0 : in STD_LOGIC;
    \pi_dqs_found_lanes_r1_reg[1]_3\ : in STD_LOGIC_VECTOR ( 5 downto 0 );
    \po_counter_read_val_reg[8]_11\ : in STD_LOGIC;
    \po_counter_read_val_reg[8]_12\ : in STD_LOGIC;
    \po_counter_read_val_reg[8]_13\ : in STD_LOGIC;
    \my_empty_reg[7]_7\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \my_empty_reg[7]_8\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \my_empty_reg[7]_9\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \my_empty_reg[7]_10\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \my_empty_reg[7]_11\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \my_empty_reg[7]_12\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \my_empty_reg[7]_13\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \my_empty_reg[7]_14\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \input_[9].iserdes_dq_.iserdesdq_1\ : in STD_LOGIC;
    LD0_8 : in STD_LOGIC;
    CLKB0_8 : in STD_LOGIC;
    \pi_dqs_found_lanes_r1_reg[2]\ : in STD_LOGIC;
    \pi_dqs_found_lanes_r1_reg[2]_0\ : in STD_LOGIC;
    \pi_dqs_found_lanes_r1_reg[2]_1\ : in STD_LOGIC;
    \pi_dqs_found_lanes_r1_reg[2]_2\ : in STD_LOGIC;
    ififo_rst_reg_1 : in STD_LOGIC;
    \pi_dqs_found_lanes_r1_reg[2]_3\ : in STD_LOGIC_VECTOR ( 5 downto 0 );
    \po_counter_read_val_reg[8]_14\ : in STD_LOGIC;
    \po_counter_read_val_reg[8]_15\ : in STD_LOGIC;
    \po_counter_read_val_reg[8]_16\ : in STD_LOGIC;
    \my_empty_reg[7]_15\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \my_empty_reg[7]_16\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \my_empty_reg[7]_17\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \my_empty_reg[7]_18\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \my_empty_reg[7]_19\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \my_empty_reg[7]_20\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \my_empty_reg[7]_21\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \my_empty_reg[7]_22\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \input_[9].iserdes_dq_.iserdesdq_2\ : in STD_LOGIC;
    LD0_9 : in STD_LOGIC;
    CLKB0_9 : in STD_LOGIC;
    \pi_dqs_found_lanes_r1_reg[3]\ : in STD_LOGIC;
    \pi_dqs_found_lanes_r1_reg[3]_0\ : in STD_LOGIC;
    \pi_dqs_found_lanes_r1_reg[3]_1\ : in STD_LOGIC;
    \pi_dqs_found_lanes_r1_reg[3]_2\ : in STD_LOGIC;
    ififo_rst_reg_2 : in STD_LOGIC;
    \pi_dqs_found_lanes_r1_reg[3]_3\ : in STD_LOGIC_VECTOR ( 5 downto 0 );
    \po_counter_read_val_reg[8]_17\ : in STD_LOGIC;
    \po_counter_read_val_reg[8]_18\ : in STD_LOGIC;
    \po_counter_read_val_reg[8]_19\ : in STD_LOGIC;
    \my_empty_reg[7]_23\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \my_empty_reg[7]_24\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \my_empty_reg[7]_25\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \my_empty_reg[7]_26\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \my_empty_reg[7]_27\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \my_empty_reg[7]_28\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \my_empty_reg[7]_29\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \my_empty_reg[7]_30\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    RST0 : in STD_LOGIC;
    SR : in STD_LOGIC_VECTOR ( 0 to 0 );
    \input_[9].iserdes_dq_.iserdesdq_3\ : in STD_LOGIC;
    LD0_10 : in STD_LOGIC;
    CLKB0_10 : in STD_LOGIC;
    \pi_dqs_found_lanes_r1_reg[8]\ : in STD_LOGIC;
    \pi_dqs_found_lanes_r1_reg[8]_0\ : in STD_LOGIC;
    \pi_dqs_found_lanes_r1_reg[8]_1\ : in STD_LOGIC;
    \pi_dqs_found_lanes_r1_reg[8]_2\ : in STD_LOGIC;
    ififo_rst_reg_3 : in STD_LOGIC;
    \pi_dqs_found_lanes_r1_reg[8]_3\ : in STD_LOGIC_VECTOR ( 5 downto 0 );
    \po_counter_read_val_reg[8]_20\ : in STD_LOGIC;
    \po_counter_read_val_reg[8]_21\ : in STD_LOGIC;
    \po_counter_read_val_reg[8]_22\ : in STD_LOGIC;
    \my_empty_reg[7]_31\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    D2 : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \my_empty_reg[7]_32\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \my_empty_reg[7]_33\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \my_empty_reg[7]_34\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \my_empty_reg[7]_35\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \my_empty_reg[7]_36\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \my_empty_reg[7]_37\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \input_[9].iserdes_dq_.iserdesdq_4\ : in STD_LOGIC;
    LD0_11 : in STD_LOGIC;
    CLKB0_11 : in STD_LOGIC;
    \pi_dqs_found_lanes_r1_reg[9]\ : in STD_LOGIC;
    \pi_dqs_found_lanes_r1_reg[9]_0\ : in STD_LOGIC;
    \pi_dqs_found_lanes_r1_reg[9]_1\ : in STD_LOGIC;
    \pi_dqs_found_lanes_r1_reg[9]_2\ : in STD_LOGIC;
    ififo_rst_reg_4 : in STD_LOGIC;
    \pi_dqs_found_lanes_r1_reg[9]_3\ : in STD_LOGIC_VECTOR ( 5 downto 0 );
    \po_counter_read_val_reg[8]_23\ : in STD_LOGIC;
    \po_counter_read_val_reg[8]_24\ : in STD_LOGIC;
    \po_counter_read_val_reg[8]_25\ : in STD_LOGIC;
    \my_empty_reg[7]_38\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \my_empty_reg[7]_39\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \my_empty_reg[7]_40\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \my_empty_reg[7]_41\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \my_empty_reg[7]_42\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \my_empty_reg[7]_43\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \my_empty_reg[7]_44\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \my_empty_reg[7]_45\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \input_[9].iserdes_dq_.iserdesdq_5\ : in STD_LOGIC;
    LD0_12 : in STD_LOGIC;
    CLKB0_12 : in STD_LOGIC;
    \pi_dqs_found_lanes_r1_reg[10]\ : in STD_LOGIC;
    \pi_dqs_found_lanes_r1_reg[10]_0\ : in STD_LOGIC;
    \pi_dqs_found_lanes_r1_reg[10]_1\ : in STD_LOGIC;
    \pi_dqs_found_lanes_r1_reg[10]_2\ : in STD_LOGIC;
    ififo_rst_reg_5 : in STD_LOGIC;
    \pi_dqs_found_lanes_r1_reg[10]_3\ : in STD_LOGIC_VECTOR ( 5 downto 0 );
    \po_counter_read_val_reg[8]_26\ : in STD_LOGIC;
    \po_counter_read_val_reg[8]_27\ : in STD_LOGIC;
    \po_counter_read_val_reg[8]_28\ : in STD_LOGIC;
    \my_empty_reg[7]_46\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \my_empty_reg[7]_47\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \my_empty_reg[7]_48\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \my_empty_reg[7]_49\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \my_empty_reg[7]_50\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \my_empty_reg[7]_51\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \my_empty_reg[7]_52\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \my_empty_reg[7]_53\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \input_[9].iserdes_dq_.iserdesdq_6\ : in STD_LOGIC;
    LD0_13 : in STD_LOGIC;
    CLKB0_13 : in STD_LOGIC;
    \pi_dqs_found_lanes_r1_reg[11]\ : in STD_LOGIC;
    \pi_dqs_found_lanes_r1_reg[11]_0\ : in STD_LOGIC;
    \pi_dqs_found_lanes_r1_reg[11]_1\ : in STD_LOGIC;
    \pi_dqs_found_lanes_r1_reg[11]_2\ : in STD_LOGIC;
    ififo_rst_reg_6 : in STD_LOGIC;
    \pi_dqs_found_lanes_r1_reg[11]_3\ : in STD_LOGIC_VECTOR ( 5 downto 0 );
    \po_counter_read_val_reg[8]_29\ : in STD_LOGIC;
    \po_counter_read_val_reg[8]_30\ : in STD_LOGIC;
    \po_counter_read_val_reg[8]_31\ : in STD_LOGIC;
    \my_empty_reg[7]_54\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \my_empty_reg[7]_55\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \my_empty_reg[7]_56\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \my_empty_reg[7]_57\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \my_empty_reg[7]_58\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \my_empty_reg[7]_59\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \my_empty_reg[7]_60\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \my_empty_reg[7]_61\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    phy_mc_ctl_full_r_reg_1 : in STD_LOGIC_VECTOR ( 5 downto 0 );
    \rstdiv2_sync_r_reg[11]\ : in STD_LOGIC;
    iodelay_ctrl_rdy : in STD_LOGIC_VECTOR ( 0 to 0 );
    \out\ : in STD_LOGIC;
    phy_data_wr_en : in STD_LOGIC;
    phy_cmd_wr_en : in STD_LOGIC;
    \gen_mux_rd[0].mux_rd_rise0_r_reg[0]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    out_fifo : in STD_LOGIC;
    mc_cas_n : in STD_LOGIC_VECTOR ( 2 downto 0 );
    mc_we_n : in STD_LOGIC_VECTOR ( 1 downto 0 );
    out_fifo_0 : in STD_LOGIC;
    mc_ras_n : in STD_LOGIC_VECTOR ( 1 downto 0 );
    mc_cs_n : in STD_LOGIC_VECTOR ( 0 to 0 );
    mc_address : in STD_LOGIC_VECTOR ( 3 downto 0 );
    out_fifo_1 : in STD_LOGIC_VECTOR ( 63 downto 0 );
    out_fifo_2 : in STD_LOGIC;
    \gen_mux_rd[1].mux_rd_rise0_r_reg[1]\ : in STD_LOGIC;
    phy_dout : in STD_LOGIC_VECTOR ( 71 downto 0 );
    \out_fifo_i_75__5\ : in STD_LOGIC_VECTOR ( 71 downto 0 );
    \out_fifo_i_75__6\ : in STD_LOGIC_VECTOR ( 71 downto 0 );
    \out_fifo_i_75__7\ : in STD_LOGIC_VECTOR ( 71 downto 0 );
    \out_fifo_i_75__0\ : in STD_LOGIC_VECTOR ( 71 downto 0 );
    \out_fifo_i_75__1\ : in STD_LOGIC_VECTOR ( 71 downto 0 );
    \out_fifo_i_75__2\ : in STD_LOGIC_VECTOR ( 71 downto 0 );
    \out_fifo_i_75__3\ : in STD_LOGIC_VECTOR ( 71 downto 0 );
    \out_fifo_i_47__8\ : in STD_LOGIC_VECTOR ( 12 downto 0 );
    mux_address : in STD_LOGIC_VECTOR ( 48 downto 0 );
    d_in : in STD_LOGIC_VECTOR ( 4 downto 0 );
    \po_counter_read_val_reg[0]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    calib_sel : in STD_LOGIC_VECTOR ( 3 downto 0 );
    \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
    C_po_coarse_enable26_out : in STD_LOGIC;
    C_po_counter_read_en38_out : in STD_LOGIC;
    C_po_fine_enable23_out : in STD_LOGIC;
    C_po_fine_inc29_out : in STD_LOGIC;
    \my_empty_reg[7]_62\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
    \my_empty_reg[7]_63\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \my_empty_reg[7]_64\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
    \my_empty_reg[7]_65\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
    D9 : in STD_LOGIC_VECTOR ( 3 downto 0 );
    out_fifo_i_39 : in STD_LOGIC_VECTOR ( 11 downto 0 );
    out_fifo_3 : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of mig_mig_7series_v4_2_ddr_mc_phy : entity is "mig_7series_v4_2_ddr_mc_phy";
end mig_mig_7series_v4_2_ddr_mc_phy;

architecture STRUCTURE of mig_mig_7series_v4_2_ddr_mc_phy is
  signal \_phy_ctl_full_p\ : STD_LOGIC_VECTOR ( 1 to 1 );
  signal \_phy_ctl_full_p__0\ : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal \ddr_byte_lane_B.ddr_byte_lane_B/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/my_empty\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \ddr_byte_lane_B.ddr_byte_lane_B/if_empty_r\ : STD_LOGIC_VECTOR ( 3 to 3 );
  signal \ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/my_empty\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \ddr_byte_lane_C.ddr_byte_lane_C/if_empty_r\ : STD_LOGIC_VECTOR ( 3 to 3 );
  signal \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_101\ : STD_LOGIC;
  signal \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_103\ : STD_LOGIC;
  signal \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_111\ : STD_LOGIC;
  signal \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_369\ : STD_LOGIC;
  signal \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_371\ : STD_LOGIC;
  signal \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_373\ : STD_LOGIC;
  signal \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_375\ : STD_LOGIC;
  signal \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_377\ : STD_LOGIC;
  signal \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_379\ : STD_LOGIC;
  signal \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_381\ : STD_LOGIC;
  signal \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_383\ : STD_LOGIC;
  signal \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_385\ : STD_LOGIC;
  signal \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_387\ : STD_LOGIC;
  signal \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_389\ : STD_LOGIC;
  signal \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_391\ : STD_LOGIC;
  signal \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_393\ : STD_LOGIC;
  signal \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_395\ : STD_LOGIC;
  signal \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_397\ : STD_LOGIC;
  signal \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_399\ : STD_LOGIC;
  signal \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_401\ : STD_LOGIC;
  signal \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_403\ : STD_LOGIC;
  signal \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_405\ : STD_LOGIC;
  signal \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_407\ : STD_LOGIC;
  signal \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_409\ : STD_LOGIC;
  signal \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_411\ : STD_LOGIC;
  signal \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_413\ : STD_LOGIC;
  signal \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_415\ : STD_LOGIC;
  signal \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_417\ : STD_LOGIC;
  signal \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_419\ : STD_LOGIC;
  signal \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_421\ : STD_LOGIC;
  signal \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_423\ : STD_LOGIC;
  signal \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_425\ : STD_LOGIC;
  signal \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_427\ : STD_LOGIC;
  signal \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_429\ : STD_LOGIC;
  signal \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_431\ : STD_LOGIC;
  signal \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_433\ : STD_LOGIC;
  signal \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_435\ : STD_LOGIC;
  signal \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_437\ : STD_LOGIC;
  signal \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_439\ : STD_LOGIC;
  signal \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_441\ : STD_LOGIC;
  signal \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_443\ : STD_LOGIC;
  signal \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_445\ : STD_LOGIC;
  signal \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_447\ : STD_LOGIC;
  signal \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_449\ : STD_LOGIC;
  signal \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_451\ : STD_LOGIC;
  signal \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_453\ : STD_LOGIC;
  signal \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_455\ : STD_LOGIC;
  signal \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_457\ : STD_LOGIC;
  signal \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_459\ : STD_LOGIC;
  signal \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_461\ : STD_LOGIC;
  signal \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_463\ : STD_LOGIC;
  signal \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_465\ : STD_LOGIC;
  signal \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_467\ : STD_LOGIC;
  signal \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_469\ : STD_LOGIC;
  signal \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_471\ : STD_LOGIC;
  signal \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_473\ : STD_LOGIC;
  signal \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_475\ : STD_LOGIC;
  signal \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_477\ : STD_LOGIC;
  signal \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_479\ : STD_LOGIC;
  signal \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_481\ : STD_LOGIC;
  signal \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_483\ : STD_LOGIC;
  signal \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_485\ : STD_LOGIC;
  signal \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_487\ : STD_LOGIC;
  signal \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_489\ : STD_LOGIC;
  signal \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_491\ : STD_LOGIC;
  signal \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_493\ : STD_LOGIC;
  signal \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_495\ : STD_LOGIC;
  signal \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_497\ : STD_LOGIC;
  signal \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_498\ : STD_LOGIC;
  signal \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_499\ : STD_LOGIC;
  signal \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_500\ : STD_LOGIC;
  signal \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_501\ : STD_LOGIC;
  signal \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_502\ : STD_LOGIC;
  signal \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_503\ : STD_LOGIC;
  signal \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_504\ : STD_LOGIC;
  signal \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_505\ : STD_LOGIC;
  signal \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_506\ : STD_LOGIC;
  signal \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_507\ : STD_LOGIC;
  signal \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_508\ : STD_LOGIC;
  signal \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_509\ : STD_LOGIC;
  signal \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_510\ : STD_LOGIC;
  signal \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_511\ : STD_LOGIC;
  signal \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_512\ : STD_LOGIC;
  signal \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_513\ : STD_LOGIC;
  signal \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_514\ : STD_LOGIC;
  signal \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_515\ : STD_LOGIC;
  signal \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_516\ : STD_LOGIC;
  signal \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_517\ : STD_LOGIC;
  signal \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_518\ : STD_LOGIC;
  signal \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_519\ : STD_LOGIC;
  signal \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_520\ : STD_LOGIC;
  signal \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_521\ : STD_LOGIC;
  signal \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_522\ : STD_LOGIC;
  signal \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_523\ : STD_LOGIC;
  signal \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_524\ : STD_LOGIC;
  signal \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_525\ : STD_LOGIC;
  signal \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_526\ : STD_LOGIC;
  signal \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_527\ : STD_LOGIC;
  signal \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_528\ : STD_LOGIC;
  signal \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_529\ : STD_LOGIC;
  signal \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_530\ : STD_LOGIC;
  signal \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_531\ : STD_LOGIC;
  signal \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_532\ : STD_LOGIC;
  signal \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_533\ : STD_LOGIC;
  signal \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_534\ : STD_LOGIC;
  signal \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_535\ : STD_LOGIC;
  signal \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_536\ : STD_LOGIC;
  signal \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_537\ : STD_LOGIC;
  signal \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_538\ : STD_LOGIC;
  signal \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_539\ : STD_LOGIC;
  signal \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_540\ : STD_LOGIC;
  signal \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_541\ : STD_LOGIC;
  signal \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_542\ : STD_LOGIC;
  signal \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_543\ : STD_LOGIC;
  signal \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_544\ : STD_LOGIC;
  signal \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_545\ : STD_LOGIC;
  signal \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_546\ : STD_LOGIC;
  signal \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_547\ : STD_LOGIC;
  signal \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_548\ : STD_LOGIC;
  signal \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_549\ : STD_LOGIC;
  signal \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_550\ : STD_LOGIC;
  signal \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_551\ : STD_LOGIC;
  signal \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_552\ : STD_LOGIC;
  signal \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_553\ : STD_LOGIC;
  signal \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_554\ : STD_LOGIC;
  signal \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_555\ : STD_LOGIC;
  signal \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_556\ : STD_LOGIC;
  signal \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_557\ : STD_LOGIC;
  signal \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_558\ : STD_LOGIC;
  signal \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_559\ : STD_LOGIC;
  signal \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_560\ : STD_LOGIC;
  signal \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_97\ : STD_LOGIC;
  signal \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_100\ : STD_LOGIC;
  signal \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_104\ : STD_LOGIC;
  signal \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_108\ : STD_LOGIC;
  signal \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_112\ : STD_LOGIC;
  signal \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_116\ : STD_LOGIC;
  signal \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_120\ : STD_LOGIC;
  signal \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_124\ : STD_LOGIC;
  signal \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_128\ : STD_LOGIC;
  signal \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_132\ : STD_LOGIC;
  signal \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_136\ : STD_LOGIC;
  signal \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_140\ : STD_LOGIC;
  signal \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_144\ : STD_LOGIC;
  signal \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_148\ : STD_LOGIC;
  signal \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_152\ : STD_LOGIC;
  signal \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_156\ : STD_LOGIC;
  signal \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_160\ : STD_LOGIC;
  signal \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_164\ : STD_LOGIC;
  signal \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_168\ : STD_LOGIC;
  signal \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_172\ : STD_LOGIC;
  signal \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_176\ : STD_LOGIC;
  signal \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_180\ : STD_LOGIC;
  signal \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_184\ : STD_LOGIC;
  signal \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_188\ : STD_LOGIC;
  signal \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_192\ : STD_LOGIC;
  signal \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_196\ : STD_LOGIC;
  signal \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_200\ : STD_LOGIC;
  signal \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_204\ : STD_LOGIC;
  signal \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_208\ : STD_LOGIC;
  signal \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_212\ : STD_LOGIC;
  signal \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_216\ : STD_LOGIC;
  signal \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_220\ : STD_LOGIC;
  signal \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_224\ : STD_LOGIC;
  signal \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_228\ : STD_LOGIC;
  signal \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_232\ : STD_LOGIC;
  signal \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_236\ : STD_LOGIC;
  signal \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_240\ : STD_LOGIC;
  signal \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_244\ : STD_LOGIC;
  signal \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_248\ : STD_LOGIC;
  signal \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_252\ : STD_LOGIC;
  signal \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_256\ : STD_LOGIC;
  signal \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_260\ : STD_LOGIC;
  signal \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_264\ : STD_LOGIC;
  signal \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_268\ : STD_LOGIC;
  signal \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_272\ : STD_LOGIC;
  signal \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_276\ : STD_LOGIC;
  signal \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_280\ : STD_LOGIC;
  signal \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_284\ : STD_LOGIC;
  signal \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_288\ : STD_LOGIC;
  signal \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_292\ : STD_LOGIC;
  signal \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_296\ : STD_LOGIC;
  signal \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_300\ : STD_LOGIC;
  signal \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_304\ : STD_LOGIC;
  signal \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_308\ : STD_LOGIC;
  signal \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_312\ : STD_LOGIC;
  signal \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_316\ : STD_LOGIC;
  signal \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_320\ : STD_LOGIC;
  signal \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_324\ : STD_LOGIC;
  signal \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_328\ : STD_LOGIC;
  signal \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_332\ : STD_LOGIC;
  signal \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_336\ : STD_LOGIC;
  signal \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_340\ : STD_LOGIC;
  signal \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_344\ : STD_LOGIC;
  signal \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_348\ : STD_LOGIC;
  signal \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_352\ : STD_LOGIC;
  signal \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_356\ : STD_LOGIC;
  signal \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_360\ : STD_LOGIC;
  signal \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_809\ : STD_LOGIC;
  signal \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_810\ : STD_LOGIC;
  signal \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_826\ : STD_LOGIC;
  signal \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_827\ : STD_LOGIC;
  signal \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_93\ : STD_LOGIC;
  signal \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_97\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_1\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_4\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_1\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_4\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_1\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_4\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_1\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_4\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_1\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_4\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_1\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_4\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_1\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_4\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_1\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_4\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_1\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_4\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_1\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_4\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_1\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_4\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_1\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_4\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_1\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_4\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_1\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_4\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_1\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_4\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_1\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_4\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_1\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_4\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_1\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_4\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_1\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_4\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_1\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_4\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_1\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_4\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_1\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_4\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_1\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_4\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_1\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_4\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_1\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_4\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_1\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_4\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_1\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_4\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_1\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_4\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_1\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_4\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_1\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_4\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_1\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_4\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_1\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_4\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_1\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_4\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_1\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_4\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_1\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_4\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_1\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_4\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_1\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_4\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_1\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_4\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_1\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_4\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_1\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_4\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_1\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_4\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_1\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_4\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_1\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_4\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_1\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_4\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_1\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_4\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_1\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_4\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_1\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_4\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_1\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_4\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_1\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_4\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_1\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_4\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_1\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_4\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_1\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_4\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_1\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_4\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_1\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_4\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_1\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_4\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_1\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_4\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_1\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_5\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_1\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_5\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_1\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_5\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_1\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_5\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_1\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_5\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_1\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_5\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_1\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_5\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_1\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_5\ : STD_LOGIC;
  signal if_empty_v : STD_LOGIC_VECTOR ( 2 to 2 );
  signal mcGo_r : STD_LOGIC_VECTOR ( 14 downto 0 );
  signal \mcGo_r1__0\ : STD_LOGIC;
  signal mcGo_w : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal \mcGo_w__0\ : STD_LOGIC_VECTOR ( 1 to 1 );
  signal phy_ctl_mstr_empty : STD_LOGIC;
  signal phy_if_empty_r_i_2_n_0 : STD_LOGIC;
  signal \po_counter_read_val_w[0]_0\ : STD_LOGIC_VECTOR ( 8 downto 0 );
  signal \po_counter_read_val_w[2]_2\ : STD_LOGIC_VECTOR ( 8 downto 0 );
  signal rclk_delay_11 : STD_LOGIC;
  signal rclk_delay_11_0 : STD_LOGIC;
  signal \rclk_delay_reg[10]_srl11_i_1__0_n_0\ : STD_LOGIC;
  signal \rclk_delay_reg[10]_srl11_i_1_n_0\ : STD_LOGIC;
  signal ref_dll_lock_w : STD_LOGIC_VECTOR ( 1 to 1 );
  signal \ref_dll_lock_w__0\ : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal \rst_out_i_1__0_n_0\ : STD_LOGIC;
  signal rst_out_i_1_n_0 : STD_LOGIC;
  signal rst_primitives : STD_LOGIC;
  signal rst_primitives_1 : STD_LOGIC;
  signal \rst_primitives_i_1__0_n_0\ : STD_LOGIC;
  signal rst_primitives_i_1_n_0 : STD_LOGIC;
begin
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_1\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_1\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_4\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_4\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_1\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_1\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_4\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_4\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_1\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_1\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_4\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_4\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_1\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_1\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_4\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_4\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_1\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_1\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_4\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_4\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_1\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_1\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_4\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_4\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_1\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_1\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_4\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_4\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_1\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_1\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_4\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_4\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_1\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_1\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_4\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_4\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_1\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_1\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_4\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_4\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_1\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_1\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_4\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_4\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_1\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_1\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_4\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_4\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_1\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_1\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_4\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_4\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_1\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_1\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_4\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_4\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_1\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_1\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_4\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_4\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_1\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_1\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_4\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_4\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_1\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_1\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_4\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_4\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_1\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_1\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_4\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_4\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_1\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_1\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_4\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_4\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_1\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_1\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_4\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_4\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_1\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_1\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_4\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_4\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_1\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_1\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_4\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_4\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_1\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_1\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_4\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_4\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_1\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_1\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_4\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_4\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_1\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_1\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_4\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_4\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_1\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_1\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_4\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_4\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_1\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_1\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_4\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_4\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_1\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_1\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_4\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_4\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_1\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_1\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_4\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_4\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_1\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_1\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_4\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_4\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_1\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_1\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_4\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_4\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_1\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_1\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_4\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_4\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_1\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_1\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_4\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_4\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_1\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_1\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_4\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_4\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_1\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_1\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_4\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_4\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_1\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_1\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_4\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_4\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_1\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_1\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_4\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_4\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_1\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_1\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_4\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_4\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_1\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_1\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_4\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_4\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_1\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_1\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_4\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_4\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_1\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_1\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_4\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_4\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_1\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_1\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_4\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_4\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_1\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_1\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_4\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_4\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_1\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_1\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_4\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_4\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_1\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_1\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_4\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_4\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_1\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_1\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_4\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_4\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_1\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_1\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_4\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_4\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_1\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_1\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_4\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_4\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_1\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_1\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_4\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_4\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_1\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_1\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_4\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_4\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_1\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_1\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_4\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_4\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_1\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_1\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_4\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_4\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_1\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_1\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_4\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_4\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_1\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_1\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_4\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_4\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_1\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_1\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_4\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_4\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_1\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_1\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_4\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_4\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_1\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_1\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_5\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_5\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_1\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_1\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_5\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_5\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_1\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_1\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_5\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_5\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_1\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_1\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_5\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_5\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_1\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_1\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_5\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_5\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_1\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_1\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_5\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_5\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_1\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_1\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_5\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_5\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_1\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_1\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_5\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_5\;
\ddr_phy_4lanes_0.u_ddr_phy_4lanes\: entity work.mig_mig_7series_v4_2_ddr_phy_4lanes
     port map (
      A_rst_primitives_reg_0 => A_rst_primitives_reg,
      A_rst_primitives_reg_1 => A_rst_primitives_reg_0,
      A_rst_primitives_reg_2 => A_rst_primitives_reg_1,
      A_rst_primitives_reg_3 => A_rst_primitives_reg_2,
      A_rst_primitives_reg_4 => A_rst_primitives_reg_7,
      CLKB0 => CLKB0,
      CLKB0_7 => CLKB0_7,
      CLKB0_8 => CLKB0_8,
      CLKB0_9 => CLKB0_9,
      COUNTERLOADVAL(5 downto 0) => COUNTERLOADVAL(5 downto 0),
      LD0 => LD0,
      LD0_7 => LD0_7,
      LD0_8 => LD0_8,
      LD0_9 => LD0_9,
      Q(10 downto 0) => Q(10 downto 0),
      RST0 => RST0,
      SR(0) => SR(0),
      \_phy_ctl_full_p__0\(0) => \_phy_ctl_full_p__0\(0),
      calib_sel(1 downto 0) => calib_sel(1 downto 0),
      \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_103\,
      \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_111\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_6\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_2\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_6\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_2\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_6\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_2\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_6\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_2\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_6\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_2\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_6\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_2\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_6\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_2\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_6\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_2\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_6\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_2\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_5\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_2\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_5\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_2\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_5\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_2\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_6\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_2\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_6\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_2\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_6\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_2\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_6\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_2\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_6\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_2\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_6\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_2\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_6\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_2\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_6\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_2\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_6\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_2\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_6\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_2\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_6\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_2\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_6\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_2\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_5\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_2\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_5\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_2\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_5\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_2\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_5\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_2\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_5\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_2\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_5\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_2\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_5\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_2\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_6\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_2\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_6\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_2\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_6\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_2\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_6\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_2\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_6\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_2\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_6\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_2\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_6\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_2\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_6\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_2\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_6\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_2\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_6\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_2\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_6\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_2\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_6\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_2\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_6\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_2\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_6\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_2\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_6\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_2\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_6\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_2\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_6\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_2\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_1\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_1\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_1\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_1\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_1\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_1\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_1\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_1\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_6\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_2\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_6\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_2\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_6\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_2\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_6\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_2\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_6\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_2\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_6\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_2\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_6\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_2\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_6\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_2\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]\,
      \entry_cnt_reg[4]\ => \entry_cnt_reg[4]\,
      freq_refclk => freq_refclk,
      \gen_mux_rd[0].mux_rd_fall0_r_reg[0]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_1\,
      \gen_mux_rd[0].mux_rd_fall0_r_reg[0]_0\ => \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_136\,
      \gen_mux_rd[0].mux_rd_fall1_r_reg[0]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_1\,
      \gen_mux_rd[0].mux_rd_fall1_r_reg[0]_0\ => \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_200\,
      \gen_mux_rd[0].mux_rd_fall2_r_reg[0]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_1\,
      \gen_mux_rd[0].mux_rd_fall2_r_reg[0]_0\ => \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_264\,
      \gen_mux_rd[0].mux_rd_fall3_r_reg[0]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_4\,
      \gen_mux_rd[0].mux_rd_fall3_r_reg[0]_0\ => \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_328\,
      \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]\(1 downto 0) => \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]\(1 downto 0),
      \gen_mux_rd[0].mux_rd_rise0_r_reg[0]\(1 downto 0) => \gen_mux_rd[0].mux_rd_rise0_r_reg[0]\(1 downto 0),
      \gen_mux_rd[0].mux_rd_rise0_r_reg[0]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_1\,
      \gen_mux_rd[0].mux_rd_rise0_r_reg[0]_1\ => \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_104\,
      \gen_mux_rd[0].mux_rd_rise1_r_reg[0]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_4\,
      \gen_mux_rd[0].mux_rd_rise1_r_reg[0]_0\ => \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_168\,
      \gen_mux_rd[0].mux_rd_rise2_r_reg[0]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_4\,
      \gen_mux_rd[0].mux_rd_rise2_r_reg[0]_0\ => \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_232\,
      \gen_mux_rd[0].mux_rd_rise3_r_reg[0]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_1\,
      \gen_mux_rd[0].mux_rd_rise3_r_reg[0]_0\ => \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_296\,
      \gen_mux_rd[1].mux_rd_fall0_r_reg[1]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_4\,
      \gen_mux_rd[1].mux_rd_fall0_r_reg[1]_0\ => \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_140\,
      \gen_mux_rd[1].mux_rd_fall1_r_reg[1]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_4\,
      \gen_mux_rd[1].mux_rd_fall1_r_reg[1]_0\ => \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_204\,
      \gen_mux_rd[1].mux_rd_fall2_r_reg[1]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_4\,
      \gen_mux_rd[1].mux_rd_fall2_r_reg[1]_0\ => \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_268\,
      \gen_mux_rd[1].mux_rd_fall3_r_reg[1]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_4\,
      \gen_mux_rd[1].mux_rd_fall3_r_reg[1]_0\ => \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_332\,
      \gen_mux_rd[1].mux_rd_rise0_r_reg[1]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_4\,
      \gen_mux_rd[1].mux_rd_rise0_r_reg[1]_0\ => \gen_mux_rd[1].mux_rd_rise0_r_reg[1]\,
      \gen_mux_rd[1].mux_rd_rise0_r_reg[1]_1\ => \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_108\,
      \gen_mux_rd[1].mux_rd_rise1_r_reg[1]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_4\,
      \gen_mux_rd[1].mux_rd_rise1_r_reg[1]_0\ => \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_172\,
      \gen_mux_rd[1].mux_rd_rise2_r_reg[1]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_4\,
      \gen_mux_rd[1].mux_rd_rise2_r_reg[1]_0\ => \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_236\,
      \gen_mux_rd[1].mux_rd_rise3_r_reg[1]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_4\,
      \gen_mux_rd[1].mux_rd_rise3_r_reg[1]_0\ => \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_300\,
      \gen_mux_rd[2].mux_rd_fall0_r_reg[2]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_1\,
      \gen_mux_rd[2].mux_rd_fall0_r_reg[2]_0\ => \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_144\,
      \gen_mux_rd[2].mux_rd_fall1_r_reg[2]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_1\,
      \gen_mux_rd[2].mux_rd_fall1_r_reg[2]_0\ => \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_208\,
      \gen_mux_rd[2].mux_rd_fall2_r_reg[2]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_4\,
      \gen_mux_rd[2].mux_rd_fall2_r_reg[2]_0\ => \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_272\,
      \gen_mux_rd[2].mux_rd_fall3_r_reg[2]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_4\,
      \gen_mux_rd[2].mux_rd_fall3_r_reg[2]_0\ => \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_336\,
      \gen_mux_rd[2].mux_rd_rise0_r_reg[2]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_4\,
      \gen_mux_rd[2].mux_rd_rise0_r_reg[2]_0\ => \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_112\,
      \gen_mux_rd[2].mux_rd_rise1_r_reg[2]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_1\,
      \gen_mux_rd[2].mux_rd_rise1_r_reg[2]_0\ => \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_176\,
      \gen_mux_rd[2].mux_rd_rise2_r_reg[2]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_4\,
      \gen_mux_rd[2].mux_rd_rise2_r_reg[2]_0\ => \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_240\,
      \gen_mux_rd[2].mux_rd_rise3_r_reg[2]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_4\,
      \gen_mux_rd[2].mux_rd_rise3_r_reg[2]_0\ => \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_304\,
      \gen_mux_rd[3].mux_rd_fall0_r_reg[3]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_4\,
      \gen_mux_rd[3].mux_rd_fall0_r_reg[3]_0\ => \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_148\,
      \gen_mux_rd[3].mux_rd_fall1_r_reg[3]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_4\,
      \gen_mux_rd[3].mux_rd_fall1_r_reg[3]_0\ => \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_212\,
      \gen_mux_rd[3].mux_rd_fall2_r_reg[3]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_4\,
      \gen_mux_rd[3].mux_rd_fall2_r_reg[3]_0\ => \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_276\,
      \gen_mux_rd[3].mux_rd_fall3_r_reg[3]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_4\,
      \gen_mux_rd[3].mux_rd_fall3_r_reg[3]_0\ => \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_340\,
      \gen_mux_rd[3].mux_rd_rise0_r_reg[3]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_4\,
      \gen_mux_rd[3].mux_rd_rise0_r_reg[3]_0\ => \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_116\,
      \gen_mux_rd[3].mux_rd_rise1_r_reg[3]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_4\,
      \gen_mux_rd[3].mux_rd_rise1_r_reg[3]_0\ => \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_180\,
      \gen_mux_rd[3].mux_rd_rise2_r_reg[3]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_4\,
      \gen_mux_rd[3].mux_rd_rise2_r_reg[3]_0\ => \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_244\,
      \gen_mux_rd[3].mux_rd_rise3_r_reg[3]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_4\,
      \gen_mux_rd[3].mux_rd_rise3_r_reg[3]_0\ => \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_308\,
      \gen_mux_rd[4].mux_rd_fall0_r_reg[4]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_1\,
      \gen_mux_rd[4].mux_rd_fall0_r_reg[4]_0\ => \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_152\,
      \gen_mux_rd[4].mux_rd_fall1_r_reg[4]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_1\,
      \gen_mux_rd[4].mux_rd_fall1_r_reg[4]_0\ => \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_216\,
      \gen_mux_rd[4].mux_rd_fall2_r_reg[4]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_1\,
      \gen_mux_rd[4].mux_rd_fall2_r_reg[4]_0\ => \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_280\,
      \gen_mux_rd[4].mux_rd_fall3_r_reg[4]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_4\,
      \gen_mux_rd[4].mux_rd_fall3_r_reg[4]_0\ => \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_344\,
      \gen_mux_rd[4].mux_rd_rise0_r_reg[4]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_1\,
      \gen_mux_rd[4].mux_rd_rise0_r_reg[4]_0\ => \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_120\,
      \gen_mux_rd[4].mux_rd_rise1_r_reg[4]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_1\,
      \gen_mux_rd[4].mux_rd_rise1_r_reg[4]_0\ => \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_184\,
      \gen_mux_rd[4].mux_rd_rise2_r_reg[4]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_1\,
      \gen_mux_rd[4].mux_rd_rise2_r_reg[4]_0\ => \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_248\,
      \gen_mux_rd[4].mux_rd_rise3_r_reg[4]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_1\,
      \gen_mux_rd[4].mux_rd_rise3_r_reg[4]_0\ => \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_312\,
      \gen_mux_rd[5].mux_rd_fall0_r_reg[5]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_4\,
      \gen_mux_rd[5].mux_rd_fall0_r_reg[5]_0\ => \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_156\,
      \gen_mux_rd[5].mux_rd_fall1_r_reg[5]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_4\,
      \gen_mux_rd[5].mux_rd_fall1_r_reg[5]_0\ => \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_220\,
      \gen_mux_rd[5].mux_rd_fall2_r_reg[5]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_4\,
      \gen_mux_rd[5].mux_rd_fall2_r_reg[5]_0\ => \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_284\,
      \gen_mux_rd[5].mux_rd_fall3_r_reg[5]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_4\,
      \gen_mux_rd[5].mux_rd_fall3_r_reg[5]_0\ => \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_348\,
      \gen_mux_rd[5].mux_rd_rise0_r_reg[5]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_4\,
      \gen_mux_rd[5].mux_rd_rise0_r_reg[5]_0\ => \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_124\,
      \gen_mux_rd[5].mux_rd_rise1_r_reg[5]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_4\,
      \gen_mux_rd[5].mux_rd_rise1_r_reg[5]_0\ => \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_188\,
      \gen_mux_rd[5].mux_rd_rise2_r_reg[5]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_4\,
      \gen_mux_rd[5].mux_rd_rise2_r_reg[5]_0\ => \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_252\,
      \gen_mux_rd[5].mux_rd_rise3_r_reg[5]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_4\,
      \gen_mux_rd[5].mux_rd_rise3_r_reg[5]_0\ => \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_316\,
      \gen_mux_rd[6].mux_rd_fall0_r_reg[6]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_4\,
      \gen_mux_rd[6].mux_rd_fall0_r_reg[6]_0\ => \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_160\,
      \gen_mux_rd[6].mux_rd_fall1_r_reg[6]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_4\,
      \gen_mux_rd[6].mux_rd_fall1_r_reg[6]_0\ => \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_224\,
      \gen_mux_rd[6].mux_rd_fall2_r_reg[6]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_4\,
      \gen_mux_rd[6].mux_rd_fall2_r_reg[6]_0\ => \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_288\,
      \gen_mux_rd[6].mux_rd_fall3_r_reg[6]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_4\,
      \gen_mux_rd[6].mux_rd_fall3_r_reg[6]_0\ => \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_352\,
      \gen_mux_rd[6].mux_rd_rise0_r_reg[6]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_4\,
      \gen_mux_rd[6].mux_rd_rise0_r_reg[6]_0\ => \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_128\,
      \gen_mux_rd[6].mux_rd_rise1_r_reg[6]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_4\,
      \gen_mux_rd[6].mux_rd_rise1_r_reg[6]_0\ => \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_192\,
      \gen_mux_rd[6].mux_rd_rise2_r_reg[6]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_4\,
      \gen_mux_rd[6].mux_rd_rise2_r_reg[6]_0\ => \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_256\,
      \gen_mux_rd[6].mux_rd_rise3_r_reg[6]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_4\,
      \gen_mux_rd[6].mux_rd_rise3_r_reg[6]_0\ => \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_320\,
      \gen_mux_rd[7].mux_rd_fall0_r_reg[7]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_5\,
      \gen_mux_rd[7].mux_rd_fall0_r_reg[7]_0\ => \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_164\,
      \gen_mux_rd[7].mux_rd_fall1_r_reg[7]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_5\,
      \gen_mux_rd[7].mux_rd_fall1_r_reg[7]_0\ => \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_228\,
      \gen_mux_rd[7].mux_rd_fall2_r_reg[7]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_5\,
      \gen_mux_rd[7].mux_rd_fall2_r_reg[7]_0\ => \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_292\,
      \gen_mux_rd[7].mux_rd_fall3_r_reg[7]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_5\,
      \gen_mux_rd[7].mux_rd_fall3_r_reg[7]_0\ => \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_356\,
      \gen_mux_rd[7].mux_rd_rise0_r_reg[7]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_5\,
      \gen_mux_rd[7].mux_rd_rise0_r_reg[7]_0\ => \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_132\,
      \gen_mux_rd[7].mux_rd_rise1_r_reg[7]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_5\,
      \gen_mux_rd[7].mux_rd_rise1_r_reg[7]_0\ => \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_196\,
      \gen_mux_rd[7].mux_rd_rise2_r_reg[7]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_5\,
      \gen_mux_rd[7].mux_rd_rise2_r_reg[7]_0\ => \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_260\,
      \gen_mux_rd[7].mux_rd_rise3_r_reg[7]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_5\,
      \gen_mux_rd[7].mux_rd_rise3_r_reg[7]_0\ => \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_324\,
      \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]\(1 downto 0) => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]\(1 downto 0),
      idelay_inc => idelay_inc,
      idelay_ld_rst => idelay_ld_rst,
      idelay_ld_rst_0 => idelay_ld_rst_0,
      idelay_ld_rst_1 => idelay_ld_rst_1,
      idelay_ld_rst_2 => idelay_ld_rst_2,
      if_empty => if_empty,
      if_empty_r(0) => \ddr_byte_lane_B.ddr_byte_lane_B/if_empty_r\(3),
      if_empty_r_0(0) => \ddr_byte_lane_C.ddr_byte_lane_C/if_empty_r\(3),
      if_empty_v(0) => if_empty_v(2),
      ififo_rst_reg => ififo_rst_reg,
      ififo_rst_reg_0 => ififo_rst_reg_0,
      ififo_rst_reg_1 => ififo_rst_reg_1,
      ififo_rst_reg_2 => ififo_rst_reg_2,
      in0(3 downto 0) => in0(3 downto 0),
      \input_[9].iserdes_dq_.iserdesdq\ => \input_[9].iserdes_dq_.iserdesdq\,
      \input_[9].iserdes_dq_.iserdesdq_0\ => \input_[9].iserdes_dq_.iserdesdq_0\,
      \input_[9].iserdes_dq_.iserdesdq_1\ => \input_[9].iserdes_dq_.iserdesdq_1\,
      \input_[9].iserdes_dq_.iserdesdq_2\ => \input_[9].iserdes_dq_.iserdesdq_2\,
      mcGo_w(0) => mcGo_w(0),
      mem_dq_in(31 downto 0) => mem_dq_in(31 downto 0),
      mem_dq_out(35 downto 0) => mem_dq_out(35 downto 0),
      mem_dq_ts(35 downto 0) => mem_dq_ts(35 downto 0),
      mem_dqs_in(3 downto 0) => mem_dqs_in(3 downto 0),
      mem_refclk => mem_refclk,
      \my_empty_reg[1]\ => \my_empty_reg[1]\,
      \my_empty_reg[1]_0\ => \my_empty_reg[1]_0\,
      \my_empty_reg[1]_1\ => \my_empty_reg[1]_1\,
      \my_empty_reg[1]_2\ => \my_empty_reg[1]_2\,
      \my_empty_reg[4]\(0) => \ddr_byte_lane_B.ddr_byte_lane_B/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/my_empty\(0),
      \my_empty_reg[4]_0\(0) => \ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/my_empty\(0),
      \my_empty_reg[7]\(7 downto 0) => \my_empty_reg[7]\(7 downto 0),
      \my_empty_reg[7]_0\(7 downto 0) => \my_empty_reg[7]_0\(7 downto 0),
      \my_empty_reg[7]_1\(7 downto 0) => \my_empty_reg[7]_1\(7 downto 0),
      \my_empty_reg[7]_10\(7 downto 0) => \my_empty_reg[7]_10\(7 downto 0),
      \my_empty_reg[7]_11\(7 downto 0) => \my_empty_reg[7]_11\(7 downto 0),
      \my_empty_reg[7]_12\(7 downto 0) => \my_empty_reg[7]_12\(7 downto 0),
      \my_empty_reg[7]_13\(7 downto 0) => \my_empty_reg[7]_13\(7 downto 0),
      \my_empty_reg[7]_14\(7 downto 0) => \my_empty_reg[7]_14\(7 downto 0),
      \my_empty_reg[7]_15\(7 downto 0) => \my_empty_reg[7]_15\(7 downto 0),
      \my_empty_reg[7]_16\(7 downto 0) => \my_empty_reg[7]_16\(7 downto 0),
      \my_empty_reg[7]_17\(7 downto 0) => \my_empty_reg[7]_17\(7 downto 0),
      \my_empty_reg[7]_18\(7 downto 0) => \my_empty_reg[7]_18\(7 downto 0),
      \my_empty_reg[7]_19\(7 downto 0) => \my_empty_reg[7]_19\(7 downto 0),
      \my_empty_reg[7]_2\(7 downto 0) => \my_empty_reg[7]_2\(7 downto 0),
      \my_empty_reg[7]_20\(7 downto 0) => \my_empty_reg[7]_20\(7 downto 0),
      \my_empty_reg[7]_21\(7 downto 0) => \my_empty_reg[7]_21\(7 downto 0),
      \my_empty_reg[7]_22\(7 downto 0) => \my_empty_reg[7]_22\(7 downto 0),
      \my_empty_reg[7]_23\(7 downto 0) => \my_empty_reg[7]_23\(7 downto 0),
      \my_empty_reg[7]_24\(7 downto 0) => \my_empty_reg[7]_24\(7 downto 0),
      \my_empty_reg[7]_25\(7 downto 0) => \my_empty_reg[7]_25\(7 downto 0),
      \my_empty_reg[7]_26\(7 downto 0) => \my_empty_reg[7]_26\(7 downto 0),
      \my_empty_reg[7]_27\(7 downto 0) => \my_empty_reg[7]_27\(7 downto 0),
      \my_empty_reg[7]_28\(7 downto 0) => \my_empty_reg[7]_28\(7 downto 0),
      \my_empty_reg[7]_29\(7 downto 0) => \my_empty_reg[7]_29\(7 downto 0),
      \my_empty_reg[7]_3\(7 downto 0) => \my_empty_reg[7]_3\(7 downto 0),
      \my_empty_reg[7]_30\(7 downto 0) => \my_empty_reg[7]_30\(7 downto 0),
      \my_empty_reg[7]_4\(7 downto 0) => \my_empty_reg[7]_4\(7 downto 0),
      \my_empty_reg[7]_5\(7 downto 0) => \my_empty_reg[7]_5\(7 downto 0),
      \my_empty_reg[7]_6\(7 downto 0) => \my_empty_reg[7]_6\(7 downto 0),
      \my_empty_reg[7]_7\(7 downto 0) => \my_empty_reg[7]_7\(7 downto 0),
      \my_empty_reg[7]_8\(7 downto 0) => \my_empty_reg[7]_8\(7 downto 0),
      \my_empty_reg[7]_9\(7 downto 0) => \my_empty_reg[7]_9\(7 downto 0),
      \my_full_reg[1]\ => \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_100\,
      \my_full_reg[1]_0\ => \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_827\,
      \my_full_reg[1]_1\ => \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_826\,
      ofs_rdy_r_reg => \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_810\,
      ofs_rdy_r_reg_0 => \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_809\,
      out_dqs_4 => out_dqs_4,
      out_dqs_5 => out_dqs_5,
      out_dqs_6 => out_dqs_6,
      out_dqs_7 => out_dqs_7,
      out_fifo => out_fifo_0,
      out_fifo_0(31 downto 28) => out_fifo_1(63 downto 60),
      out_fifo_0(27 downto 24) => out_fifo_1(55 downto 52),
      out_fifo_0(23 downto 20) => out_fifo_1(47 downto 44),
      out_fifo_0(19 downto 16) => out_fifo_1(39 downto 36),
      out_fifo_0(15 downto 12) => out_fifo_1(31 downto 28),
      out_fifo_0(11 downto 8) => out_fifo_1(23 downto 20),
      out_fifo_0(7 downto 4) => out_fifo_1(15 downto 12),
      out_fifo_0(3 downto 0) => out_fifo_1(7 downto 4),
      out_fifo_1 => out_fifo_2,
      \out_fifo_i_75__5\(71 downto 0) => \out_fifo_i_75__5\(71 downto 0),
      \out_fifo_i_75__6\(71 downto 0) => \out_fifo_i_75__6\(71 downto 0),
      \out_fifo_i_75__7\(71 downto 0) => \out_fifo_i_75__7\(71 downto 0),
      phy_ctl_mstr_empty => phy_ctl_mstr_empty,
      phy_ctl_wr_i2 => phy_ctl_wr_i2,
      phy_ctl_wr_i2_reg => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_97\,
      phy_data_wr_en => phy_data_wr_en,
      phy_dout(71 downto 0) => phy_dout(71 downto 0),
      phy_if_empty_r_reg => phy_if_empty_r_i_2_n_0,
      phy_if_reset => phy_if_reset,
      phy_mc_ctl_full_r_reg => phy_mc_ctl_full_r_reg,
      phy_mc_data_full => phy_mc_data_full,
      phy_rddata_en => phy_rddata_en,
      phy_read_calib => phy_read_calib,
      phy_write_calib => phy_write_calib,
      \pi_counter_read_val_reg[5]_0\(5 downto 0) => \pi_counter_read_val_reg[5]\(5 downto 0),
      \pi_dqs_found_lanes_r1_reg[0]\ => \pi_dqs_found_lanes_r1_reg[0]\,
      \pi_dqs_found_lanes_r1_reg[0]_0\ => \pi_dqs_found_lanes_r1_reg[0]_0\,
      \pi_dqs_found_lanes_r1_reg[0]_1\ => \pi_dqs_found_lanes_r1_reg[0]_1\,
      \pi_dqs_found_lanes_r1_reg[0]_2\ => \pi_dqs_found_lanes_r1_reg[0]_2\,
      \pi_dqs_found_lanes_r1_reg[1]\ => \pi_dqs_found_lanes_r1_reg[1]\,
      \pi_dqs_found_lanes_r1_reg[1]_0\ => \pi_dqs_found_lanes_r1_reg[1]_0\,
      \pi_dqs_found_lanes_r1_reg[1]_1\ => \pi_dqs_found_lanes_r1_reg[1]_1\,
      \pi_dqs_found_lanes_r1_reg[1]_2\ => \pi_dqs_found_lanes_r1_reg[1]_2\,
      \pi_dqs_found_lanes_r1_reg[1]_3\(5 downto 0) => \pi_dqs_found_lanes_r1_reg[1]_3\(5 downto 0),
      \pi_dqs_found_lanes_r1_reg[2]\ => \pi_dqs_found_lanes_r1_reg[2]\,
      \pi_dqs_found_lanes_r1_reg[2]_0\ => \pi_dqs_found_lanes_r1_reg[2]_0\,
      \pi_dqs_found_lanes_r1_reg[2]_1\ => \pi_dqs_found_lanes_r1_reg[2]_1\,
      \pi_dqs_found_lanes_r1_reg[2]_2\ => \pi_dqs_found_lanes_r1_reg[2]_2\,
      \pi_dqs_found_lanes_r1_reg[2]_3\(5 downto 0) => \pi_dqs_found_lanes_r1_reg[2]_3\(5 downto 0),
      \pi_dqs_found_lanes_r1_reg[3]\ => \pi_dqs_found_lanes_r1_reg[3]\,
      \pi_dqs_found_lanes_r1_reg[3]_0\ => \pi_dqs_found_lanes_r1_reg[3]_0\,
      \pi_dqs_found_lanes_r1_reg[3]_1\ => \pi_dqs_found_lanes_r1_reg[3]_1\,
      \pi_dqs_found_lanes_r1_reg[3]_2\ => \pi_dqs_found_lanes_r1_reg[3]_2\,
      \pi_dqs_found_lanes_r1_reg[3]_3\(5 downto 0) => \pi_dqs_found_lanes_r1_reg[3]_3\(5 downto 0),
      pi_phase_locked_all_r1_reg => \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_360\,
      pll_locked => pll_locked,
      \po_counter_read_val_reg[8]_0\(8 downto 0) => \po_counter_read_val_w[0]_0\(8 downto 0),
      \po_counter_read_val_reg[8]_1\ => \po_counter_read_val_reg[8]_8\,
      \po_counter_read_val_reg[8]_10\ => \po_counter_read_val_reg[8]_17\,
      \po_counter_read_val_reg[8]_11\ => \po_counter_read_val_reg[8]_18\,
      \po_counter_read_val_reg[8]_12\ => \po_counter_read_val_reg[8]_19\,
      \po_counter_read_val_reg[8]_2\ => \po_counter_read_val_reg[8]_9\,
      \po_counter_read_val_reg[8]_3\ => \po_counter_read_val_reg[8]_10\,
      \po_counter_read_val_reg[8]_4\ => \po_counter_read_val_reg[8]_11\,
      \po_counter_read_val_reg[8]_5\ => \po_counter_read_val_reg[8]_12\,
      \po_counter_read_val_reg[8]_6\ => \po_counter_read_val_reg[8]_13\,
      \po_counter_read_val_reg[8]_7\ => \po_counter_read_val_reg[8]_14\,
      \po_counter_read_val_reg[8]_8\ => \po_counter_read_val_reg[8]_15\,
      \po_counter_read_val_reg[8]_9\ => \po_counter_read_val_reg[8]_16\,
      \po_stg2_wrcal_cnt_reg[1]\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_497\,
      \po_stg2_wrcal_cnt_reg[1]_0\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_498\,
      \po_stg2_wrcal_cnt_reg[1]_1\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_499\,
      \po_stg2_wrcal_cnt_reg[1]_10\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_508\,
      \po_stg2_wrcal_cnt_reg[1]_11\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_509\,
      \po_stg2_wrcal_cnt_reg[1]_12\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_510\,
      \po_stg2_wrcal_cnt_reg[1]_13\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_511\,
      \po_stg2_wrcal_cnt_reg[1]_14\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_512\,
      \po_stg2_wrcal_cnt_reg[1]_15\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_513\,
      \po_stg2_wrcal_cnt_reg[1]_16\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_514\,
      \po_stg2_wrcal_cnt_reg[1]_17\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_515\,
      \po_stg2_wrcal_cnt_reg[1]_18\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_516\,
      \po_stg2_wrcal_cnt_reg[1]_19\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_517\,
      \po_stg2_wrcal_cnt_reg[1]_2\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_500\,
      \po_stg2_wrcal_cnt_reg[1]_20\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_518\,
      \po_stg2_wrcal_cnt_reg[1]_21\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_519\,
      \po_stg2_wrcal_cnt_reg[1]_22\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_520\,
      \po_stg2_wrcal_cnt_reg[1]_23\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_521\,
      \po_stg2_wrcal_cnt_reg[1]_24\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_522\,
      \po_stg2_wrcal_cnt_reg[1]_25\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_523\,
      \po_stg2_wrcal_cnt_reg[1]_26\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_524\,
      \po_stg2_wrcal_cnt_reg[1]_27\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_525\,
      \po_stg2_wrcal_cnt_reg[1]_28\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_526\,
      \po_stg2_wrcal_cnt_reg[1]_29\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_527\,
      \po_stg2_wrcal_cnt_reg[1]_3\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_501\,
      \po_stg2_wrcal_cnt_reg[1]_30\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_528\,
      \po_stg2_wrcal_cnt_reg[1]_31\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_529\,
      \po_stg2_wrcal_cnt_reg[1]_32\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_530\,
      \po_stg2_wrcal_cnt_reg[1]_33\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_531\,
      \po_stg2_wrcal_cnt_reg[1]_34\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_532\,
      \po_stg2_wrcal_cnt_reg[1]_35\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_533\,
      \po_stg2_wrcal_cnt_reg[1]_36\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_534\,
      \po_stg2_wrcal_cnt_reg[1]_37\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_535\,
      \po_stg2_wrcal_cnt_reg[1]_38\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_536\,
      \po_stg2_wrcal_cnt_reg[1]_39\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_537\,
      \po_stg2_wrcal_cnt_reg[1]_4\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_502\,
      \po_stg2_wrcal_cnt_reg[1]_40\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_538\,
      \po_stg2_wrcal_cnt_reg[1]_41\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_539\,
      \po_stg2_wrcal_cnt_reg[1]_42\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_540\,
      \po_stg2_wrcal_cnt_reg[1]_43\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_541\,
      \po_stg2_wrcal_cnt_reg[1]_44\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_542\,
      \po_stg2_wrcal_cnt_reg[1]_45\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_543\,
      \po_stg2_wrcal_cnt_reg[1]_46\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_544\,
      \po_stg2_wrcal_cnt_reg[1]_47\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_545\,
      \po_stg2_wrcal_cnt_reg[1]_48\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_546\,
      \po_stg2_wrcal_cnt_reg[1]_49\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_547\,
      \po_stg2_wrcal_cnt_reg[1]_5\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_503\,
      \po_stg2_wrcal_cnt_reg[1]_50\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_548\,
      \po_stg2_wrcal_cnt_reg[1]_51\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_549\,
      \po_stg2_wrcal_cnt_reg[1]_52\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_550\,
      \po_stg2_wrcal_cnt_reg[1]_53\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_551\,
      \po_stg2_wrcal_cnt_reg[1]_54\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_552\,
      \po_stg2_wrcal_cnt_reg[1]_55\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_553\,
      \po_stg2_wrcal_cnt_reg[1]_56\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_554\,
      \po_stg2_wrcal_cnt_reg[1]_57\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_555\,
      \po_stg2_wrcal_cnt_reg[1]_58\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_556\,
      \po_stg2_wrcal_cnt_reg[1]_59\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_557\,
      \po_stg2_wrcal_cnt_reg[1]_6\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_504\,
      \po_stg2_wrcal_cnt_reg[1]_60\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_558\,
      \po_stg2_wrcal_cnt_reg[1]_61\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_559\,
      \po_stg2_wrcal_cnt_reg[1]_62\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_560\,
      \po_stg2_wrcal_cnt_reg[1]_7\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_505\,
      \po_stg2_wrcal_cnt_reg[1]_8\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_506\,
      \po_stg2_wrcal_cnt_reg[1]_9\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_507\,
      rclk_delay_11 => rclk_delay_11,
      \rclk_delay_reg[11]_0\ => \rclk_delay_reg[10]_srl11_i_1_n_0\,
      \rd_mux_sel_r_reg[1]\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_369\,
      \rd_mux_sel_r_reg[1]_0\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_371\,
      \rd_mux_sel_r_reg[1]_1\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_373\,
      \rd_mux_sel_r_reg[1]_10\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_391\,
      \rd_mux_sel_r_reg[1]_11\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_393\,
      \rd_mux_sel_r_reg[1]_12\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_395\,
      \rd_mux_sel_r_reg[1]_13\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_397\,
      \rd_mux_sel_r_reg[1]_14\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_399\,
      \rd_mux_sel_r_reg[1]_15\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_401\,
      \rd_mux_sel_r_reg[1]_16\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_403\,
      \rd_mux_sel_r_reg[1]_17\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_405\,
      \rd_mux_sel_r_reg[1]_18\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_407\,
      \rd_mux_sel_r_reg[1]_19\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_409\,
      \rd_mux_sel_r_reg[1]_2\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_375\,
      \rd_mux_sel_r_reg[1]_20\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_411\,
      \rd_mux_sel_r_reg[1]_21\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_413\,
      \rd_mux_sel_r_reg[1]_22\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_415\,
      \rd_mux_sel_r_reg[1]_23\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_417\,
      \rd_mux_sel_r_reg[1]_24\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_419\,
      \rd_mux_sel_r_reg[1]_25\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_421\,
      \rd_mux_sel_r_reg[1]_26\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_423\,
      \rd_mux_sel_r_reg[1]_27\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_425\,
      \rd_mux_sel_r_reg[1]_28\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_427\,
      \rd_mux_sel_r_reg[1]_29\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_429\,
      \rd_mux_sel_r_reg[1]_3\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_377\,
      \rd_mux_sel_r_reg[1]_30\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_431\,
      \rd_mux_sel_r_reg[1]_31\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_433\,
      \rd_mux_sel_r_reg[1]_32\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_435\,
      \rd_mux_sel_r_reg[1]_33\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_437\,
      \rd_mux_sel_r_reg[1]_34\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_439\,
      \rd_mux_sel_r_reg[1]_35\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_441\,
      \rd_mux_sel_r_reg[1]_36\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_443\,
      \rd_mux_sel_r_reg[1]_37\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_445\,
      \rd_mux_sel_r_reg[1]_38\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_447\,
      \rd_mux_sel_r_reg[1]_39\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_449\,
      \rd_mux_sel_r_reg[1]_4\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_379\,
      \rd_mux_sel_r_reg[1]_40\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_451\,
      \rd_mux_sel_r_reg[1]_41\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_453\,
      \rd_mux_sel_r_reg[1]_42\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_455\,
      \rd_mux_sel_r_reg[1]_43\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_457\,
      \rd_mux_sel_r_reg[1]_44\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_459\,
      \rd_mux_sel_r_reg[1]_45\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_461\,
      \rd_mux_sel_r_reg[1]_46\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_463\,
      \rd_mux_sel_r_reg[1]_47\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_465\,
      \rd_mux_sel_r_reg[1]_48\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_467\,
      \rd_mux_sel_r_reg[1]_49\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_469\,
      \rd_mux_sel_r_reg[1]_5\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_381\,
      \rd_mux_sel_r_reg[1]_50\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_471\,
      \rd_mux_sel_r_reg[1]_51\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_473\,
      \rd_mux_sel_r_reg[1]_52\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_475\,
      \rd_mux_sel_r_reg[1]_53\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_477\,
      \rd_mux_sel_r_reg[1]_54\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_479\,
      \rd_mux_sel_r_reg[1]_55\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_481\,
      \rd_mux_sel_r_reg[1]_56\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_483\,
      \rd_mux_sel_r_reg[1]_57\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_485\,
      \rd_mux_sel_r_reg[1]_58\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_487\,
      \rd_mux_sel_r_reg[1]_59\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_489\,
      \rd_mux_sel_r_reg[1]_6\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_383\,
      \rd_mux_sel_r_reg[1]_60\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_491\,
      \rd_mux_sel_r_reg[1]_61\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_493\,
      \rd_mux_sel_r_reg[1]_62\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_495\,
      \rd_mux_sel_r_reg[1]_7\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_385\,
      \rd_mux_sel_r_reg[1]_8\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_387\,
      \rd_mux_sel_r_reg[1]_9\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_389\,
      \rd_mux_sel_r_reg[2]\ => \rd_mux_sel_r_reg[2]\,
      \rd_mux_sel_r_reg[2]_0\ => \rd_mux_sel_r_reg[2]_0\,
      \rd_mux_sel_r_reg[2]_1\ => \rd_mux_sel_r_reg[2]_1\,
      \rd_mux_sel_r_reg[2]_10\ => \rd_mux_sel_r_reg[2]_10\,
      \rd_mux_sel_r_reg[2]_11\ => \rd_mux_sel_r_reg[2]_11\,
      \rd_mux_sel_r_reg[2]_12\ => \rd_mux_sel_r_reg[2]_12\,
      \rd_mux_sel_r_reg[2]_13\ => \rd_mux_sel_r_reg[2]_13\,
      \rd_mux_sel_r_reg[2]_14\ => \rd_mux_sel_r_reg[2]_14\,
      \rd_mux_sel_r_reg[2]_15\ => \rd_mux_sel_r_reg[2]_15\,
      \rd_mux_sel_r_reg[2]_16\ => \rd_mux_sel_r_reg[2]_16\,
      \rd_mux_sel_r_reg[2]_17\ => \rd_mux_sel_r_reg[2]_17\,
      \rd_mux_sel_r_reg[2]_18\ => \rd_mux_sel_r_reg[2]_18\,
      \rd_mux_sel_r_reg[2]_19\ => \rd_mux_sel_r_reg[2]_19\,
      \rd_mux_sel_r_reg[2]_2\ => \rd_mux_sel_r_reg[2]_2\,
      \rd_mux_sel_r_reg[2]_20\ => \rd_mux_sel_r_reg[2]_20\,
      \rd_mux_sel_r_reg[2]_21\ => \rd_mux_sel_r_reg[2]_21\,
      \rd_mux_sel_r_reg[2]_22\ => \rd_mux_sel_r_reg[2]_22\,
      \rd_mux_sel_r_reg[2]_23\ => \rd_mux_sel_r_reg[2]_23\,
      \rd_mux_sel_r_reg[2]_24\ => \rd_mux_sel_r_reg[2]_24\,
      \rd_mux_sel_r_reg[2]_25\ => \rd_mux_sel_r_reg[2]_25\,
      \rd_mux_sel_r_reg[2]_26\ => \rd_mux_sel_r_reg[2]_26\,
      \rd_mux_sel_r_reg[2]_27\ => \rd_mux_sel_r_reg[2]_27\,
      \rd_mux_sel_r_reg[2]_28\ => \rd_mux_sel_r_reg[2]_28\,
      \rd_mux_sel_r_reg[2]_29\ => \rd_mux_sel_r_reg[2]_29\,
      \rd_mux_sel_r_reg[2]_3\ => \rd_mux_sel_r_reg[2]_3\,
      \rd_mux_sel_r_reg[2]_30\ => \rd_mux_sel_r_reg[2]_30\,
      \rd_mux_sel_r_reg[2]_31\ => \rd_mux_sel_r_reg[2]_31\,
      \rd_mux_sel_r_reg[2]_32\ => \rd_mux_sel_r_reg[2]_32\,
      \rd_mux_sel_r_reg[2]_33\ => \rd_mux_sel_r_reg[2]_33\,
      \rd_mux_sel_r_reg[2]_34\ => \rd_mux_sel_r_reg[2]_34\,
      \rd_mux_sel_r_reg[2]_35\ => \rd_mux_sel_r_reg[2]_35\,
      \rd_mux_sel_r_reg[2]_36\ => \rd_mux_sel_r_reg[2]_36\,
      \rd_mux_sel_r_reg[2]_37\ => \rd_mux_sel_r_reg[2]_37\,
      \rd_mux_sel_r_reg[2]_38\ => \rd_mux_sel_r_reg[2]_38\,
      \rd_mux_sel_r_reg[2]_39\ => \rd_mux_sel_r_reg[2]_39\,
      \rd_mux_sel_r_reg[2]_4\ => \rd_mux_sel_r_reg[2]_4\,
      \rd_mux_sel_r_reg[2]_40\ => \rd_mux_sel_r_reg[2]_40\,
      \rd_mux_sel_r_reg[2]_41\ => \rd_mux_sel_r_reg[2]_41\,
      \rd_mux_sel_r_reg[2]_42\ => \rd_mux_sel_r_reg[2]_42\,
      \rd_mux_sel_r_reg[2]_43\ => \rd_mux_sel_r_reg[2]_43\,
      \rd_mux_sel_r_reg[2]_44\ => \rd_mux_sel_r_reg[2]_44\,
      \rd_mux_sel_r_reg[2]_45\ => \rd_mux_sel_r_reg[2]_45\,
      \rd_mux_sel_r_reg[2]_46\ => \rd_mux_sel_r_reg[2]_46\,
      \rd_mux_sel_r_reg[2]_47\ => \rd_mux_sel_r_reg[2]_47\,
      \rd_mux_sel_r_reg[2]_48\ => \rd_mux_sel_r_reg[2]_48\,
      \rd_mux_sel_r_reg[2]_49\ => \rd_mux_sel_r_reg[2]_49\,
      \rd_mux_sel_r_reg[2]_5\ => \rd_mux_sel_r_reg[2]_5\,
      \rd_mux_sel_r_reg[2]_50\ => \rd_mux_sel_r_reg[2]_50\,
      \rd_mux_sel_r_reg[2]_51\ => \rd_mux_sel_r_reg[2]_51\,
      \rd_mux_sel_r_reg[2]_52\ => \rd_mux_sel_r_reg[2]_52\,
      \rd_mux_sel_r_reg[2]_53\ => \rd_mux_sel_r_reg[2]_53\,
      \rd_mux_sel_r_reg[2]_54\ => \rd_mux_sel_r_reg[2]_54\,
      \rd_mux_sel_r_reg[2]_55\ => \rd_mux_sel_r_reg[2]_55\,
      \rd_mux_sel_r_reg[2]_56\ => \rd_mux_sel_r_reg[2]_56\,
      \rd_mux_sel_r_reg[2]_57\ => \rd_mux_sel_r_reg[2]_57\,
      \rd_mux_sel_r_reg[2]_58\ => \rd_mux_sel_r_reg[2]_58\,
      \rd_mux_sel_r_reg[2]_59\ => \rd_mux_sel_r_reg[2]_59\,
      \rd_mux_sel_r_reg[2]_6\ => \rd_mux_sel_r_reg[2]_6\,
      \rd_mux_sel_r_reg[2]_60\ => \rd_mux_sel_r_reg[2]_60\,
      \rd_mux_sel_r_reg[2]_61\ => \rd_mux_sel_r_reg[2]_61\,
      \rd_mux_sel_r_reg[2]_62\ => \rd_mux_sel_r_reg[2]_62\,
      \rd_mux_sel_r_reg[2]_7\ => \rd_mux_sel_r_reg[2]_7\,
      \rd_mux_sel_r_reg[2]_8\ => \rd_mux_sel_r_reg[2]_8\,
      \rd_mux_sel_r_reg[2]_9\ => \rd_mux_sel_r_reg[2]_9\,
      \rd_ptr_reg[3]\(63 downto 0) => \rd_ptr_reg[3]\(63 downto 0),
      \rd_ptr_reg[3]_0\(63 downto 0) => \rd_ptr_reg[3]_0\(63 downto 0),
      \rd_ptr_reg[3]_1\(63 downto 0) => \rd_ptr_reg[3]_1\(63 downto 0),
      \rd_ptr_reg[3]_2\(63 downto 0) => \rd_ptr_reg[3]_2\(63 downto 0),
      \ref_dll_lock_w__0\(0) => \ref_dll_lock_w__0\(0),
      rst_out_reg_0 => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_101\,
      rst_out_reg_1 => rst_out_i_1_n_0,
      rst_primitives => rst_primitives,
      rst_primitives_reg_0 => rst_primitives_i_1_n_0,
      sync_pulse => sync_pulse,
      ts_dqs_4 => ts_dqs_4,
      ts_dqs_5 => ts_dqs_5,
      ts_dqs_6 => ts_dqs_6,
      ts_dqs_7 => ts_dqs_7
    );
\ddr_phy_4lanes_1.u_ddr_phy_4lanes\: entity work.\mig_mig_7series_v4_2_ddr_phy_4lanes__parameterized0\
     port map (
      C_po_coarse_enable26_out => C_po_coarse_enable26_out,
      C_po_counter_read_en38_out => C_po_counter_read_en38_out,
      C_po_fine_enable23_out => C_po_fine_enable23_out,
      C_po_fine_inc29_out => C_po_fine_inc29_out,
      D1(3 downto 0) => D1(3 downto 0),
      D3(3 downto 0) => D3(3 downto 0),
      D4(3 downto 0) => D4(3 downto 0),
      D5(3 downto 0) => D5(3 downto 0),
      D6(7 downto 0) => D6(7 downto 0),
      D7(3 downto 0) => D7(3 downto 0),
      D8(3 downto 0) => D8(3 downto 0),
      D9(3 downto 0) => D9(3 downto 0),
      PHYCTLWD(10 downto 9) => Q(10 downto 9),
      PHYCTLWD(8 downto 3) => phy_mc_ctl_full_r_reg_0(5 downto 0),
      PHYCTLWD(2 downto 0) => Q(2 downto 0),
      Q(8 downto 0) => \po_counter_read_val_w[2]_2\(8 downto 0),
      RST0 => RST0,
      SR(0) => SR(0),
      \_phy_ctl_full_p\(0) => \_phy_ctl_full_p\(1),
      calib_sel(3 downto 0) => calib_sel(3 downto 0),
      d_in(4 downto 0) => d_in(4 downto 0),
      ddr_ck_out(1 downto 0) => ddr_ck_out(1 downto 0),
      freq_refclk => freq_refclk,
      \mcGo_w__0\(0) => \mcGo_w__0\(1),
      mc_address(3 downto 0) => mc_address(3 downto 0),
      mc_cas_n(2 downto 0) => mc_cas_n(2 downto 0),
      mc_cs_n(0) => mc_cs_n(0),
      mc_ras_n(1 downto 0) => mc_ras_n(1 downto 0),
      mc_we_n(1 downto 0) => mc_we_n(1 downto 0),
      mem_dq_out(22 downto 0) => mem_dq_out(58 downto 36),
      mem_out(11 downto 0) => mem_out(11 downto 0),
      mem_refclk => mem_refclk,
      mux_address(48 downto 0) => mux_address(48 downto 0),
      \my_empty_reg[1]\ => \my_empty_reg[1]_7\,
      \my_empty_reg[1]_0\ => \my_empty_reg[1]_8\,
      \my_empty_reg[1]_1\ => \my_empty_reg[1]_9\,
      \my_empty_reg[7]\(3 downto 0) => \my_empty_reg[7]_62\(3 downto 0),
      \my_empty_reg[7]_0\(7 downto 0) => \my_empty_reg[7]_63\(7 downto 0),
      \my_empty_reg[7]_1\(3 downto 0) => \my_empty_reg[7]_64\(3 downto 0),
      \my_empty_reg[7]_2\(3 downto 0) => \my_empty_reg[7]_65\(3 downto 0),
      \my_full_reg[3]\(3 downto 0) => \my_full_reg[3]\(3 downto 0),
      \my_full_reg[3]_0\(0) => \my_full_reg[3]_0\(0),
      \my_full_reg[3]_1\(1 downto 0) => \my_full_reg[3]_1\(1 downto 0),
      \my_full_reg[3]_2\(0) => \my_full_reg[3]_2\(0),
      \my_full_reg[3]_3\(3 downto 0) => \my_full_reg[3]_3\(3 downto 0),
      of_ctl_full_v(0) => of_ctl_full_v(0),
      out_fifo => out_fifo,
      out_fifo_0 => out_fifo_0,
      out_fifo_1 => out_fifo_3,
      out_fifo_i_39(11 downto 0) => out_fifo_i_39(11 downto 0),
      \out_fifo_i_47__8\(12 downto 0) => \out_fifo_i_47__8\(12 downto 0),
      phy_cmd_wr_en => phy_cmd_wr_en,
      phy_ctl_mstr_empty => phy_ctl_mstr_empty,
      phy_ctl_wr_i2 => phy_ctl_wr_i2,
      phy_mc_ctl_full_r_reg => phy_mc_ctl_full_r_reg,
      phy_read_calib => phy_read_calib,
      phy_write_calib => phy_write_calib,
      pll_locked => pll_locked,
      \po_counter_read_val_reg[0]_0\ => \po_counter_read_val_reg[0]\,
      \po_counter_read_val_reg[0]_1\(0) => \po_counter_read_val_reg[0]_0\(0),
      \po_counter_read_val_reg[1]_0\ => \po_counter_read_val_reg[1]\,
      \po_counter_read_val_reg[2]_0\ => \po_counter_read_val_reg[2]\,
      \po_counter_read_val_reg[3]_0\ => \po_counter_read_val_reg[3]\,
      \po_counter_read_val_reg[4]_0\ => \po_counter_read_val_reg[4]\,
      \po_counter_read_val_reg[5]_0\ => \po_counter_read_val_reg[5]\,
      \po_counter_read_val_reg[6]_0\ => \po_counter_read_val_reg[6]\,
      \po_counter_read_val_reg[7]_0\ => \po_counter_read_val_reg[7]\,
      \po_counter_read_val_reg[8]_0\ => \po_counter_read_val_reg[8]\,
      \po_counter_read_val_reg[8]_1\ => \po_counter_read_val_reg[8]_0\,
      \po_counter_read_val_reg[8]_2\ => \po_counter_read_val_reg[8]_1\,
      \po_counter_read_val_reg[8]_3\ => \po_counter_read_val_reg[8]_2\,
      \po_counter_read_val_reg[8]_4\ => \po_counter_read_val_reg[8]_3\,
      \po_counter_read_val_reg[8]_5\ => \po_counter_read_val_reg[8]_4\,
      \po_counter_read_val_reg[8]_6\ => \po_counter_read_val_reg[8]_5\,
      \po_counter_read_val_reg[8]_7\ => \po_counter_read_val_reg[8]_6\,
      \po_counter_read_val_reg[8]_8\ => \po_counter_read_val_reg[8]_7\,
      \po_rdval_cnt_reg[8]\(8 downto 0) => \po_counter_read_val_w[0]_0\(8 downto 0),
      \rd_ptr_reg[3]\(35 downto 0) => \rd_ptr_reg[3]_7\(35 downto 0),
      \rd_ptr_reg[3]_0\(23 downto 0) => \rd_ptr_reg[3]_8\(23 downto 0),
      \rd_ptr_reg[3]_1\(3 downto 0) => \rd_ptr_reg[3]_9\(3 downto 0),
      ref_dll_lock_w(0) => ref_dll_lock_w(1),
      sync_pulse => sync_pulse,
      \wr_ptr_timing_reg[3]\ => \entry_cnt_reg[4]\
    );
\ddr_phy_4lanes_2.u_ddr_phy_4lanes\: entity work.mig_mig_7series_v4_2_ddr_phy_4lanes_13
     port map (
      A_rst_primitives_reg_0 => A_rst_primitives_reg_3,
      A_rst_primitives_reg_1 => A_rst_primitives_reg_4,
      A_rst_primitives_reg_2 => A_rst_primitives_reg_5,
      A_rst_primitives_reg_3 => A_rst_primitives_reg_6,
      A_rst_primitives_reg_4 => \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_360\,
      CLKB0_10 => CLKB0_10,
      CLKB0_11 => CLKB0_11,
      CLKB0_12 => CLKB0_12,
      CLKB0_13 => CLKB0_13,
      D2(7 downto 0) => D2(7 downto 0),
      LD0_10 => LD0_10,
      LD0_11 => LD0_11,
      LD0_12 => LD0_12,
      LD0_13 => LD0_13,
      PHYCTLWD(10 downto 9) => Q(10 downto 9),
      PHYCTLWD(8 downto 3) => phy_mc_ctl_full_r_reg_1(5 downto 0),
      PHYCTLWD(2 downto 0) => Q(2 downto 0),
      Q(8 downto 0) => \po_counter_read_val_w[2]_2\(8 downto 0),
      RST0 => RST0,
      SR(0) => SR(0),
      \_phy_ctl_full_p__0\(0) => \_phy_ctl_full_p__0\(2),
      calib_sel(1 downto 0) => calib_sel(1 downto 0),
      \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]\ => \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_100\,
      \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0\ => \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_826\,
      \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1\ => \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_827\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_5\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_2\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_5\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_2\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_5\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_2\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_5\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_2\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_5\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_2\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_5\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_2\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_5\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_2\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_5\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_2\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_5\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_2\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_6\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_2\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_6\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_2\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_6\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_2\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_5\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_2\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_5\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_2\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_5\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_2\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_5\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_2\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_5\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_2\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_5\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_2\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_5\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_2\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_5\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_2\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_5\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_2\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_5\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_2\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_5\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_2\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_5\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_2\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_6\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_2\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_6\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_2\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_6\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_2\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_6\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_2\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_6\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_2\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_6\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_2\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_6\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_2\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_5\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_2\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_5\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_2\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_5\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_2\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_5\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_2\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_5\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_2\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_5\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_2\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_5\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_2\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_5\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_2\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_5\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_2\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_5\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_2\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_5\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_2\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_5\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_2\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_5\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_2\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_5\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_2\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_5\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_2\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_5\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_2\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_5\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_2\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_1\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_1\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_1\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_1\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_1\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_1\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_1\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_1\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_2\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_5\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_2\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_5\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_2\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_5\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_2\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_5\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_2\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_5\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_2\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_5\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_2\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_5\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_2\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_5\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_0\,
      \entry_cnt_reg[4]\ => \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_809\,
      \entry_cnt_reg[4]_0\ => \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_810\,
      \entry_cnt_reg[4]_1\ => \entry_cnt_reg[4]\,
      freq_refclk => freq_refclk,
      \gen_mux_rd[0].mux_rd_fall0_r1_reg[0]\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_385\,
      \gen_mux_rd[0].mux_rd_fall0_r_reg[0]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_4\,
      \gen_mux_rd[0].mux_rd_fall1_r1_reg[0]\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_417\,
      \gen_mux_rd[0].mux_rd_fall1_r_reg[0]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_4\,
      \gen_mux_rd[0].mux_rd_fall2_r1_reg[0]\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_449\,
      \gen_mux_rd[0].mux_rd_fall2_r_reg[0]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_4\,
      \gen_mux_rd[0].mux_rd_fall3_r1_reg[0]\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_481\,
      \gen_mux_rd[0].mux_rd_fall3_r_reg[0]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_1\,
      \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]\(2 downto 0) => \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]\(2 downto 0),
      \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]_0\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_369\,
      \gen_mux_rd[0].mux_rd_rise0_r_reg[0]\(1 downto 0) => \gen_mux_rd[0].mux_rd_rise0_r_reg[0]\(1 downto 0),
      \gen_mux_rd[0].mux_rd_rise0_r_reg[0]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_4\,
      \gen_mux_rd[0].mux_rd_rise1_r1_reg[0]\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_401\,
      \gen_mux_rd[0].mux_rd_rise1_r_reg[0]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_1\,
      \gen_mux_rd[0].mux_rd_rise2_r1_reg[0]\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_433\,
      \gen_mux_rd[0].mux_rd_rise2_r_reg[0]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_1\,
      \gen_mux_rd[0].mux_rd_rise3_r1_reg[0]\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_465\,
      \gen_mux_rd[0].mux_rd_rise3_r_reg[0]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_4\,
      \gen_mux_rd[1].mux_rd_fall0_r1_reg[1]\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_387\,
      \gen_mux_rd[1].mux_rd_fall0_r_reg[1]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_1\,
      \gen_mux_rd[1].mux_rd_fall1_r1_reg[1]\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_419\,
      \gen_mux_rd[1].mux_rd_fall1_r_reg[1]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_1\,
      \gen_mux_rd[1].mux_rd_fall2_r1_reg[1]\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_451\,
      \gen_mux_rd[1].mux_rd_fall2_r_reg[1]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_1\,
      \gen_mux_rd[1].mux_rd_fall3_r1_reg[1]\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_483\,
      \gen_mux_rd[1].mux_rd_fall3_r_reg[1]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_1\,
      \gen_mux_rd[1].mux_rd_rise0_r1_reg[1]\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_371\,
      \gen_mux_rd[1].mux_rd_rise0_r_reg[1]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_1\,
      \gen_mux_rd[1].mux_rd_rise1_r1_reg[1]\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_403\,
      \gen_mux_rd[1].mux_rd_rise1_r_reg[1]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_1\,
      \gen_mux_rd[1].mux_rd_rise2_r1_reg[1]\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_435\,
      \gen_mux_rd[1].mux_rd_rise2_r_reg[1]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_1\,
      \gen_mux_rd[1].mux_rd_rise3_r1_reg[1]\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_467\,
      \gen_mux_rd[1].mux_rd_rise3_r_reg[1]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_1\,
      \gen_mux_rd[2].mux_rd_fall0_r1_reg[2]\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_389\,
      \gen_mux_rd[2].mux_rd_fall0_r_reg[2]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_4\,
      \gen_mux_rd[2].mux_rd_fall1_r1_reg[2]\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_421\,
      \gen_mux_rd[2].mux_rd_fall1_r_reg[2]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_4\,
      \gen_mux_rd[2].mux_rd_fall2_r1_reg[2]\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_453\,
      \gen_mux_rd[2].mux_rd_fall2_r_reg[2]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_1\,
      \gen_mux_rd[2].mux_rd_fall3_r1_reg[2]\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_485\,
      \gen_mux_rd[2].mux_rd_fall3_r_reg[2]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_1\,
      \gen_mux_rd[2].mux_rd_rise0_r1_reg[2]\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_373\,
      \gen_mux_rd[2].mux_rd_rise0_r_reg[2]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_1\,
      \gen_mux_rd[2].mux_rd_rise1_r1_reg[2]\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_405\,
      \gen_mux_rd[2].mux_rd_rise1_r_reg[2]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_4\,
      \gen_mux_rd[2].mux_rd_rise2_r1_reg[2]\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_437\,
      \gen_mux_rd[2].mux_rd_rise2_r_reg[2]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_1\,
      \gen_mux_rd[2].mux_rd_rise3_r1_reg[2]\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_469\,
      \gen_mux_rd[2].mux_rd_rise3_r_reg[2]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_1\,
      \gen_mux_rd[3].mux_rd_fall0_r1_reg[3]\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_391\,
      \gen_mux_rd[3].mux_rd_fall0_r_reg[3]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_1\,
      \gen_mux_rd[3].mux_rd_fall1_r1_reg[3]\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_423\,
      \gen_mux_rd[3].mux_rd_fall1_r_reg[3]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_1\,
      \gen_mux_rd[3].mux_rd_fall2_r1_reg[3]\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_455\,
      \gen_mux_rd[3].mux_rd_fall2_r_reg[3]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_1\,
      \gen_mux_rd[3].mux_rd_fall3_r1_reg[3]\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_487\,
      \gen_mux_rd[3].mux_rd_fall3_r_reg[3]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_1\,
      \gen_mux_rd[3].mux_rd_rise0_r1_reg[3]\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_375\,
      \gen_mux_rd[3].mux_rd_rise0_r_reg[3]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_1\,
      \gen_mux_rd[3].mux_rd_rise1_r1_reg[3]\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_407\,
      \gen_mux_rd[3].mux_rd_rise1_r_reg[3]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_1\,
      \gen_mux_rd[3].mux_rd_rise2_r1_reg[3]\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_439\,
      \gen_mux_rd[3].mux_rd_rise2_r_reg[3]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_1\,
      \gen_mux_rd[3].mux_rd_rise3_r1_reg[3]\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_471\,
      \gen_mux_rd[3].mux_rd_rise3_r_reg[3]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_1\,
      \gen_mux_rd[4].mux_rd_fall0_r1_reg[4]\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_393\,
      \gen_mux_rd[4].mux_rd_fall0_r_reg[4]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_4\,
      \gen_mux_rd[4].mux_rd_fall1_r1_reg[4]\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_425\,
      \gen_mux_rd[4].mux_rd_fall1_r_reg[4]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_4\,
      \gen_mux_rd[4].mux_rd_fall2_r1_reg[4]\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_457\,
      \gen_mux_rd[4].mux_rd_fall2_r_reg[4]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_4\,
      \gen_mux_rd[4].mux_rd_fall3_r1_reg[4]\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_489\,
      \gen_mux_rd[4].mux_rd_fall3_r_reg[4]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_1\,
      \gen_mux_rd[4].mux_rd_rise0_r1_reg[4]\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_377\,
      \gen_mux_rd[4].mux_rd_rise0_r_reg[4]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_4\,
      \gen_mux_rd[4].mux_rd_rise1_r1_reg[4]\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_409\,
      \gen_mux_rd[4].mux_rd_rise1_r_reg[4]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_4\,
      \gen_mux_rd[4].mux_rd_rise2_r1_reg[4]\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_441\,
      \gen_mux_rd[4].mux_rd_rise2_r_reg[4]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_4\,
      \gen_mux_rd[4].mux_rd_rise3_r1_reg[4]\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_473\,
      \gen_mux_rd[4].mux_rd_rise3_r_reg[4]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_4\,
      \gen_mux_rd[5].mux_rd_fall0_r1_reg[5]\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_395\,
      \gen_mux_rd[5].mux_rd_fall0_r_reg[5]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_1\,
      \gen_mux_rd[5].mux_rd_fall1_r1_reg[5]\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_427\,
      \gen_mux_rd[5].mux_rd_fall1_r_reg[5]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_1\,
      \gen_mux_rd[5].mux_rd_fall2_r1_reg[5]\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_459\,
      \gen_mux_rd[5].mux_rd_fall2_r_reg[5]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_1\,
      \gen_mux_rd[5].mux_rd_fall3_r1_reg[5]\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_491\,
      \gen_mux_rd[5].mux_rd_fall3_r_reg[5]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_1\,
      \gen_mux_rd[5].mux_rd_rise0_r1_reg[5]\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_379\,
      \gen_mux_rd[5].mux_rd_rise0_r_reg[5]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_1\,
      \gen_mux_rd[5].mux_rd_rise1_r1_reg[5]\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_411\,
      \gen_mux_rd[5].mux_rd_rise1_r_reg[5]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_1\,
      \gen_mux_rd[5].mux_rd_rise2_r1_reg[5]\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_443\,
      \gen_mux_rd[5].mux_rd_rise2_r_reg[5]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_1\,
      \gen_mux_rd[5].mux_rd_rise3_r1_reg[5]\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_475\,
      \gen_mux_rd[5].mux_rd_rise3_r_reg[5]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_1\,
      \gen_mux_rd[6].mux_rd_fall0_r1_reg[6]\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_397\,
      \gen_mux_rd[6].mux_rd_fall0_r_reg[6]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_1\,
      \gen_mux_rd[6].mux_rd_fall1_r1_reg[6]\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_429\,
      \gen_mux_rd[6].mux_rd_fall1_r_reg[6]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_1\,
      \gen_mux_rd[6].mux_rd_fall2_r1_reg[6]\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_461\,
      \gen_mux_rd[6].mux_rd_fall2_r_reg[6]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_1\,
      \gen_mux_rd[6].mux_rd_fall3_r1_reg[6]\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_493\,
      \gen_mux_rd[6].mux_rd_fall3_r_reg[6]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_1\,
      \gen_mux_rd[6].mux_rd_rise0_r1_reg[6]\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_381\,
      \gen_mux_rd[6].mux_rd_rise0_r_reg[6]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_1\,
      \gen_mux_rd[6].mux_rd_rise1_r1_reg[6]\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_413\,
      \gen_mux_rd[6].mux_rd_rise1_r_reg[6]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_1\,
      \gen_mux_rd[6].mux_rd_rise2_r1_reg[6]\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_445\,
      \gen_mux_rd[6].mux_rd_rise2_r_reg[6]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_1\,
      \gen_mux_rd[6].mux_rd_rise3_r1_reg[6]\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_477\,
      \gen_mux_rd[6].mux_rd_rise3_r_reg[6]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_1\,
      \gen_mux_rd[7].mux_rd_fall0_r1_reg[7]\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_399\,
      \gen_mux_rd[7].mux_rd_fall0_r_reg[7]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_1\,
      \gen_mux_rd[7].mux_rd_fall1_r1_reg[7]\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_431\,
      \gen_mux_rd[7].mux_rd_fall1_r_reg[7]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_1\,
      \gen_mux_rd[7].mux_rd_fall2_r1_reg[7]\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_463\,
      \gen_mux_rd[7].mux_rd_fall2_r_reg[7]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_1\,
      \gen_mux_rd[7].mux_rd_fall3_r1_reg[7]\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_495\,
      \gen_mux_rd[7].mux_rd_fall3_r_reg[7]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_1\,
      \gen_mux_rd[7].mux_rd_rise0_r1_reg[7]\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_383\,
      \gen_mux_rd[7].mux_rd_rise0_r_reg[7]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_1\,
      \gen_mux_rd[7].mux_rd_rise1_r1_reg[7]\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_415\,
      \gen_mux_rd[7].mux_rd_rise1_r_reg[7]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_1\,
      \gen_mux_rd[7].mux_rd_rise2_r1_reg[7]\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_447\,
      \gen_mux_rd[7].mux_rd_rise2_r_reg[7]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_1\,
      \gen_mux_rd[7].mux_rd_rise3_r1_reg[7]\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_479\,
      \gen_mux_rd[7].mux_rd_rise3_r_reg[7]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_1\,
      \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg[0]\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_513\,
      \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg[0]\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_553\,
      \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg[0]\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_529\,
      \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg[0]\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_505\,
      \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg[0]\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_545\,
      \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]\(2 downto 0) => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]\(2 downto 0),
      \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_0\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_497\,
      \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise2_r_reg[0]\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_521\,
      \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg[0]\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_537\,
      \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg[1]\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_514\,
      \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg[1]\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_554\,
      \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg[1]\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_530\,
      \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg[1]\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_506\,
      \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg[1]\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_546\,
      \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg[1]\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_498\,
      \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg[1]\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_522\,
      \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg[1]\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_538\,
      \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg[2]\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_515\,
      \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg[2]\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_555\,
      \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg[2]\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_531\,
      \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg[2]\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_507\,
      \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg[2]\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_547\,
      \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg[2]\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_499\,
      \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg[2]\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_523\,
      \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg[2]\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_539\,
      \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg[3]\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_516\,
      \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg[3]\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_556\,
      \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg[3]\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_532\,
      \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg[3]\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_508\,
      \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg[3]\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_548\,
      \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg[3]\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_500\,
      \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg[3]\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_524\,
      \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise3_r_reg[3]\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_540\,
      \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg[4]\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_517\,
      \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg[4]\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_557\,
      \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg[4]\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_533\,
      \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg[4]\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_509\,
      \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg[4]\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_549\,
      \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg[4]\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_501\,
      \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise2_r_reg[4]\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_525\,
      \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg[4]\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_541\,
      \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg[5]\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_518\,
      \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg[5]\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_558\,
      \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg[5]\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_534\,
      \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg[5]\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_510\,
      \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg[5]\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_550\,
      \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg[5]\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_502\,
      \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg[5]\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_526\,
      \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg[5]\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_542\,
      \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg[6]\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_519\,
      \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg[6]\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_559\,
      \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg[6]\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_535\,
      \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg[6]\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_511\,
      \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg[6]\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_551\,
      \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg[6]\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_503\,
      \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg[6]\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_527\,
      \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg[6]\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_543\,
      \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg[7]\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_520\,
      \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg[7]\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_560\,
      \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg[7]\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_536\,
      \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7]\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_512\,
      \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg[7]\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_552\,
      \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg[7]\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_504\,
      \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg[7]\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_528\,
      \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise3_r_reg[7]\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_544\,
      idelay_inc => idelay_inc,
      idelay_ld_rst_3 => idelay_ld_rst_3,
      idelay_ld_rst_4 => idelay_ld_rst_4,
      idelay_ld_rst_5 => idelay_ld_rst_5,
      idelay_ld_rst_6 => idelay_ld_rst_6,
      if_empty_v(0) => if_empty_v(2),
      ififo_rst_reg => ififo_rst_reg_3,
      ififo_rst_reg_0 => ififo_rst_reg_4,
      ififo_rst_reg_1 => ififo_rst_reg_5,
      ififo_rst_reg_2 => ififo_rst_reg_6,
      in0(3 downto 0) => in0(7 downto 4),
      \input_[9].iserdes_dq_.iserdesdq\ => \input_[9].iserdes_dq_.iserdesdq_3\,
      \input_[9].iserdes_dq_.iserdesdq_0\ => \input_[9].iserdes_dq_.iserdesdq_4\,
      \input_[9].iserdes_dq_.iserdesdq_1\ => \input_[9].iserdes_dq_.iserdesdq_5\,
      \input_[9].iserdes_dq_.iserdesdq_2\ => \input_[9].iserdes_dq_.iserdesdq_6\,
      mcGo_w(0) => mcGo_w(2),
      mem_dq_in(31 downto 0) => mem_dq_in(63 downto 32),
      mem_dq_out(35 downto 0) => mem_dq_out(94 downto 59),
      mem_dq_ts(35 downto 0) => mem_dq_ts(71 downto 36),
      mem_dqs_in(3 downto 0) => mem_dqs_in(7 downto 4),
      mem_refclk => mem_refclk,
      \my_empty_reg[1]\ => \my_empty_reg[1]_3\,
      \my_empty_reg[1]_0\ => \my_empty_reg[1]_4\,
      \my_empty_reg[1]_1\ => \my_empty_reg[1]_5\,
      \my_empty_reg[1]_2\ => \my_empty_reg[1]_6\,
      \my_empty_reg[7]\(7 downto 0) => \my_empty_reg[7]_31\(7 downto 0),
      \my_empty_reg[7]_0\(7 downto 0) => \my_empty_reg[7]_32\(7 downto 0),
      \my_empty_reg[7]_1\(7 downto 0) => \my_empty_reg[7]_33\(7 downto 0),
      \my_empty_reg[7]_10\(7 downto 0) => \my_empty_reg[7]_42\(7 downto 0),
      \my_empty_reg[7]_11\(7 downto 0) => \my_empty_reg[7]_43\(7 downto 0),
      \my_empty_reg[7]_12\(7 downto 0) => \my_empty_reg[7]_44\(7 downto 0),
      \my_empty_reg[7]_13\(7 downto 0) => \my_empty_reg[7]_45\(7 downto 0),
      \my_empty_reg[7]_14\(7 downto 0) => \my_empty_reg[7]_46\(7 downto 0),
      \my_empty_reg[7]_15\(7 downto 0) => \my_empty_reg[7]_47\(7 downto 0),
      \my_empty_reg[7]_16\(7 downto 0) => \my_empty_reg[7]_48\(7 downto 0),
      \my_empty_reg[7]_17\(7 downto 0) => \my_empty_reg[7]_49\(7 downto 0),
      \my_empty_reg[7]_18\(7 downto 0) => \my_empty_reg[7]_50\(7 downto 0),
      \my_empty_reg[7]_19\(7 downto 0) => \my_empty_reg[7]_51\(7 downto 0),
      \my_empty_reg[7]_2\(7 downto 0) => \my_empty_reg[7]_34\(7 downto 0),
      \my_empty_reg[7]_20\(7 downto 0) => \my_empty_reg[7]_52\(7 downto 0),
      \my_empty_reg[7]_21\(7 downto 0) => \my_empty_reg[7]_53\(7 downto 0),
      \my_empty_reg[7]_22\(7 downto 0) => \my_empty_reg[7]_54\(7 downto 0),
      \my_empty_reg[7]_23\(7 downto 0) => \my_empty_reg[7]_55\(7 downto 0),
      \my_empty_reg[7]_24\(7 downto 0) => \my_empty_reg[7]_56\(7 downto 0),
      \my_empty_reg[7]_25\(7 downto 0) => \my_empty_reg[7]_57\(7 downto 0),
      \my_empty_reg[7]_26\(7 downto 0) => \my_empty_reg[7]_58\(7 downto 0),
      \my_empty_reg[7]_27\(7 downto 0) => \my_empty_reg[7]_59\(7 downto 0),
      \my_empty_reg[7]_28\(7 downto 0) => \my_empty_reg[7]_60\(7 downto 0),
      \my_empty_reg[7]_29\(7 downto 0) => \my_empty_reg[7]_61\(7 downto 0),
      \my_empty_reg[7]_3\(7 downto 0) => \my_empty_reg[7]_35\(7 downto 0),
      \my_empty_reg[7]_4\(7 downto 0) => \my_empty_reg[7]_36\(7 downto 0),
      \my_empty_reg[7]_5\(7 downto 0) => \my_empty_reg[7]_37\(7 downto 0),
      \my_empty_reg[7]_6\(7 downto 0) => \my_empty_reg[7]_38\(7 downto 0),
      \my_empty_reg[7]_7\(7 downto 0) => \my_empty_reg[7]_39\(7 downto 0),
      \my_empty_reg[7]_8\(7 downto 0) => \my_empty_reg[7]_40\(7 downto 0),
      \my_empty_reg[7]_9\(7 downto 0) => \my_empty_reg[7]_41\(7 downto 0),
      \my_full_reg[1]\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_111\,
      \my_full_reg[1]_0\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_103\,
      out_dqs_0 => out_dqs_0,
      out_dqs_1 => out_dqs_1,
      out_dqs_2 => out_dqs_2,
      out_dqs_3 => out_dqs_3,
      out_fifo => out_fifo_0,
      out_fifo_0(31 downto 28) => out_fifo_1(59 downto 56),
      out_fifo_0(27 downto 24) => out_fifo_1(51 downto 48),
      out_fifo_0(23 downto 20) => out_fifo_1(43 downto 40),
      out_fifo_0(19 downto 16) => out_fifo_1(35 downto 32),
      out_fifo_0(15 downto 12) => out_fifo_1(27 downto 24),
      out_fifo_0(11 downto 8) => out_fifo_1(19 downto 16),
      out_fifo_0(7 downto 4) => out_fifo_1(11 downto 8),
      out_fifo_0(3 downto 0) => out_fifo_1(3 downto 0),
      out_fifo_1 => out_fifo_2,
      \out_fifo_i_75__0\(71 downto 0) => \out_fifo_i_75__0\(71 downto 0),
      \out_fifo_i_75__1\(71 downto 0) => \out_fifo_i_75__1\(71 downto 0),
      \out_fifo_i_75__2\(71 downto 0) => \out_fifo_i_75__2\(71 downto 0),
      \out_fifo_i_75__3\(71 downto 0) => \out_fifo_i_75__3\(71 downto 0),
      p_0_out => p_0_out,
      phy_ctl_mstr_empty => phy_ctl_mstr_empty,
      phy_ctl_wr_i2 => phy_ctl_wr_i2,
      phy_ctl_wr_i2_reg => \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_93\,
      phy_data_wr_en => phy_data_wr_en,
      phy_if_reset => phy_if_reset,
      phy_mc_ctl_full_r_reg => phy_mc_ctl_full_r_reg,
      phy_read_calib => phy_read_calib,
      phy_write_calib => phy_write_calib,
      \pi_counter_read_val_reg[5]_0\(5 downto 0) => \pi_counter_read_val_reg[5]_0\(5 downto 0),
      \pi_dqs_found_lanes_r1_reg[10]\ => \pi_dqs_found_lanes_r1_reg[10]\,
      \pi_dqs_found_lanes_r1_reg[10]_0\ => \pi_dqs_found_lanes_r1_reg[10]_0\,
      \pi_dqs_found_lanes_r1_reg[10]_1\ => \pi_dqs_found_lanes_r1_reg[10]_1\,
      \pi_dqs_found_lanes_r1_reg[10]_2\ => \pi_dqs_found_lanes_r1_reg[10]_2\,
      \pi_dqs_found_lanes_r1_reg[10]_3\(5 downto 0) => \pi_dqs_found_lanes_r1_reg[10]_3\(5 downto 0),
      \pi_dqs_found_lanes_r1_reg[11]\ => \pi_dqs_found_lanes_r1_reg[11]\,
      \pi_dqs_found_lanes_r1_reg[11]_0\ => \pi_dqs_found_lanes_r1_reg[11]_0\,
      \pi_dqs_found_lanes_r1_reg[11]_1\ => \pi_dqs_found_lanes_r1_reg[11]_1\,
      \pi_dqs_found_lanes_r1_reg[11]_2\ => \pi_dqs_found_lanes_r1_reg[11]_2\,
      \pi_dqs_found_lanes_r1_reg[11]_3\(5 downto 0) => \pi_dqs_found_lanes_r1_reg[11]_3\(5 downto 0),
      \pi_dqs_found_lanes_r1_reg[8]\ => \pi_dqs_found_lanes_r1_reg[8]\,
      \pi_dqs_found_lanes_r1_reg[8]_0\ => \pi_dqs_found_lanes_r1_reg[8]_0\,
      \pi_dqs_found_lanes_r1_reg[8]_1\ => \pi_dqs_found_lanes_r1_reg[8]_1\,
      \pi_dqs_found_lanes_r1_reg[8]_2\ => \pi_dqs_found_lanes_r1_reg[8]_2\,
      \pi_dqs_found_lanes_r1_reg[8]_3\(5 downto 0) => \pi_dqs_found_lanes_r1_reg[8]_3\(5 downto 0),
      \pi_dqs_found_lanes_r1_reg[9]\ => \pi_dqs_found_lanes_r1_reg[9]\,
      \pi_dqs_found_lanes_r1_reg[9]_0\ => \pi_dqs_found_lanes_r1_reg[9]_0\,
      \pi_dqs_found_lanes_r1_reg[9]_1\ => \pi_dqs_found_lanes_r1_reg[9]_1\,
      \pi_dqs_found_lanes_r1_reg[9]_2\ => \pi_dqs_found_lanes_r1_reg[9]_2\,
      \pi_dqs_found_lanes_r1_reg[9]_3\(5 downto 0) => \pi_dqs_found_lanes_r1_reg[9]_3\(5 downto 0),
      pll_locked => pll_locked,
      \po_counter_read_val_reg[8]_0\ => \po_counter_read_val_reg[8]_20\,
      \po_counter_read_val_reg[8]_1\ => \po_counter_read_val_reg[8]_21\,
      \po_counter_read_val_reg[8]_10\ => \po_counter_read_val_reg[8]_30\,
      \po_counter_read_val_reg[8]_11\ => \po_counter_read_val_reg[8]_31\,
      \po_counter_read_val_reg[8]_2\ => \po_counter_read_val_reg[8]_22\,
      \po_counter_read_val_reg[8]_3\ => \po_counter_read_val_reg[8]_23\,
      \po_counter_read_val_reg[8]_4\ => \po_counter_read_val_reg[8]_24\,
      \po_counter_read_val_reg[8]_5\ => \po_counter_read_val_reg[8]_25\,
      \po_counter_read_val_reg[8]_6\ => \po_counter_read_val_reg[8]_26\,
      \po_counter_read_val_reg[8]_7\ => \po_counter_read_val_reg[8]_27\,
      \po_counter_read_val_reg[8]_8\ => \po_counter_read_val_reg[8]_28\,
      \po_counter_read_val_reg[8]_9\ => \po_counter_read_val_reg[8]_29\,
      \po_stg2_wrcal_cnt_reg[2]\ => \po_stg2_wrcal_cnt_reg[2]\,
      \po_stg2_wrcal_cnt_reg[2]_0\ => \po_stg2_wrcal_cnt_reg[2]_0\,
      \po_stg2_wrcal_cnt_reg[2]_1\ => \po_stg2_wrcal_cnt_reg[2]_1\,
      \po_stg2_wrcal_cnt_reg[2]_10\ => \po_stg2_wrcal_cnt_reg[2]_10\,
      \po_stg2_wrcal_cnt_reg[2]_11\ => \po_stg2_wrcal_cnt_reg[2]_11\,
      \po_stg2_wrcal_cnt_reg[2]_12\ => \po_stg2_wrcal_cnt_reg[2]_12\,
      \po_stg2_wrcal_cnt_reg[2]_13\ => \po_stg2_wrcal_cnt_reg[2]_13\,
      \po_stg2_wrcal_cnt_reg[2]_14\ => \po_stg2_wrcal_cnt_reg[2]_14\,
      \po_stg2_wrcal_cnt_reg[2]_15\ => \po_stg2_wrcal_cnt_reg[2]_15\,
      \po_stg2_wrcal_cnt_reg[2]_16\ => \po_stg2_wrcal_cnt_reg[2]_16\,
      \po_stg2_wrcal_cnt_reg[2]_17\ => \po_stg2_wrcal_cnt_reg[2]_17\,
      \po_stg2_wrcal_cnt_reg[2]_18\ => \po_stg2_wrcal_cnt_reg[2]_18\,
      \po_stg2_wrcal_cnt_reg[2]_19\ => \po_stg2_wrcal_cnt_reg[2]_19\,
      \po_stg2_wrcal_cnt_reg[2]_2\ => \po_stg2_wrcal_cnt_reg[2]_2\,
      \po_stg2_wrcal_cnt_reg[2]_20\ => \po_stg2_wrcal_cnt_reg[2]_20\,
      \po_stg2_wrcal_cnt_reg[2]_21\ => \po_stg2_wrcal_cnt_reg[2]_21\,
      \po_stg2_wrcal_cnt_reg[2]_22\ => \po_stg2_wrcal_cnt_reg[2]_22\,
      \po_stg2_wrcal_cnt_reg[2]_23\ => \po_stg2_wrcal_cnt_reg[2]_23\,
      \po_stg2_wrcal_cnt_reg[2]_24\ => \po_stg2_wrcal_cnt_reg[2]_24\,
      \po_stg2_wrcal_cnt_reg[2]_25\ => \po_stg2_wrcal_cnt_reg[2]_25\,
      \po_stg2_wrcal_cnt_reg[2]_26\ => \po_stg2_wrcal_cnt_reg[2]_26\,
      \po_stg2_wrcal_cnt_reg[2]_27\ => \po_stg2_wrcal_cnt_reg[2]_27\,
      \po_stg2_wrcal_cnt_reg[2]_28\ => \po_stg2_wrcal_cnt_reg[2]_28\,
      \po_stg2_wrcal_cnt_reg[2]_29\ => \po_stg2_wrcal_cnt_reg[2]_29\,
      \po_stg2_wrcal_cnt_reg[2]_3\ => \po_stg2_wrcal_cnt_reg[2]_3\,
      \po_stg2_wrcal_cnt_reg[2]_30\ => \po_stg2_wrcal_cnt_reg[2]_30\,
      \po_stg2_wrcal_cnt_reg[2]_31\ => \po_stg2_wrcal_cnt_reg[2]_31\,
      \po_stg2_wrcal_cnt_reg[2]_32\ => \po_stg2_wrcal_cnt_reg[2]_32\,
      \po_stg2_wrcal_cnt_reg[2]_33\ => \po_stg2_wrcal_cnt_reg[2]_33\,
      \po_stg2_wrcal_cnt_reg[2]_34\ => \po_stg2_wrcal_cnt_reg[2]_34\,
      \po_stg2_wrcal_cnt_reg[2]_35\ => \po_stg2_wrcal_cnt_reg[2]_35\,
      \po_stg2_wrcal_cnt_reg[2]_36\ => \po_stg2_wrcal_cnt_reg[2]_36\,
      \po_stg2_wrcal_cnt_reg[2]_37\ => \po_stg2_wrcal_cnt_reg[2]_37\,
      \po_stg2_wrcal_cnt_reg[2]_38\ => \po_stg2_wrcal_cnt_reg[2]_38\,
      \po_stg2_wrcal_cnt_reg[2]_39\ => \po_stg2_wrcal_cnt_reg[2]_39\,
      \po_stg2_wrcal_cnt_reg[2]_4\ => \po_stg2_wrcal_cnt_reg[2]_4\,
      \po_stg2_wrcal_cnt_reg[2]_40\ => \po_stg2_wrcal_cnt_reg[2]_40\,
      \po_stg2_wrcal_cnt_reg[2]_41\ => \po_stg2_wrcal_cnt_reg[2]_41\,
      \po_stg2_wrcal_cnt_reg[2]_42\ => \po_stg2_wrcal_cnt_reg[2]_42\,
      \po_stg2_wrcal_cnt_reg[2]_43\ => \po_stg2_wrcal_cnt_reg[2]_43\,
      \po_stg2_wrcal_cnt_reg[2]_44\ => \po_stg2_wrcal_cnt_reg[2]_44\,
      \po_stg2_wrcal_cnt_reg[2]_45\ => \po_stg2_wrcal_cnt_reg[2]_45\,
      \po_stg2_wrcal_cnt_reg[2]_46\ => \po_stg2_wrcal_cnt_reg[2]_46\,
      \po_stg2_wrcal_cnt_reg[2]_47\ => \po_stg2_wrcal_cnt_reg[2]_47\,
      \po_stg2_wrcal_cnt_reg[2]_48\ => \po_stg2_wrcal_cnt_reg[2]_48\,
      \po_stg2_wrcal_cnt_reg[2]_49\ => \po_stg2_wrcal_cnt_reg[2]_49\,
      \po_stg2_wrcal_cnt_reg[2]_5\ => \po_stg2_wrcal_cnt_reg[2]_5\,
      \po_stg2_wrcal_cnt_reg[2]_50\ => \po_stg2_wrcal_cnt_reg[2]_50\,
      \po_stg2_wrcal_cnt_reg[2]_51\ => \po_stg2_wrcal_cnt_reg[2]_51\,
      \po_stg2_wrcal_cnt_reg[2]_52\ => \po_stg2_wrcal_cnt_reg[2]_52\,
      \po_stg2_wrcal_cnt_reg[2]_53\ => \po_stg2_wrcal_cnt_reg[2]_53\,
      \po_stg2_wrcal_cnt_reg[2]_54\ => \po_stg2_wrcal_cnt_reg[2]_54\,
      \po_stg2_wrcal_cnt_reg[2]_55\ => \po_stg2_wrcal_cnt_reg[2]_55\,
      \po_stg2_wrcal_cnt_reg[2]_56\ => \po_stg2_wrcal_cnt_reg[2]_56\,
      \po_stg2_wrcal_cnt_reg[2]_57\ => \po_stg2_wrcal_cnt_reg[2]_57\,
      \po_stg2_wrcal_cnt_reg[2]_58\ => \po_stg2_wrcal_cnt_reg[2]_58\,
      \po_stg2_wrcal_cnt_reg[2]_59\ => \po_stg2_wrcal_cnt_reg[2]_59\,
      \po_stg2_wrcal_cnt_reg[2]_6\ => \po_stg2_wrcal_cnt_reg[2]_6\,
      \po_stg2_wrcal_cnt_reg[2]_60\ => \po_stg2_wrcal_cnt_reg[2]_60\,
      \po_stg2_wrcal_cnt_reg[2]_61\ => \po_stg2_wrcal_cnt_reg[2]_61\,
      \po_stg2_wrcal_cnt_reg[2]_7\ => \po_stg2_wrcal_cnt_reg[2]_7\,
      \po_stg2_wrcal_cnt_reg[2]_8\ => \po_stg2_wrcal_cnt_reg[2]_8\,
      \po_stg2_wrcal_cnt_reg[2]_9\ => \po_stg2_wrcal_cnt_reg[2]_9\,
      rclk_delay_11 => rclk_delay_11_0,
      \rclk_delay_reg[11]_0\ => \rclk_delay_reg[10]_srl11_i_1__0_n_0\,
      \rd_mux_sel_r_reg[0]\ => \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_104\,
      \rd_mux_sel_r_reg[0]_0\ => \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_108\,
      \rd_mux_sel_r_reg[0]_1\ => \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_112\,
      \rd_mux_sel_r_reg[0]_10\ => \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_148\,
      \rd_mux_sel_r_reg[0]_11\ => \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_152\,
      \rd_mux_sel_r_reg[0]_12\ => \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_156\,
      \rd_mux_sel_r_reg[0]_13\ => \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_160\,
      \rd_mux_sel_r_reg[0]_14\ => \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_164\,
      \rd_mux_sel_r_reg[0]_15\ => \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_168\,
      \rd_mux_sel_r_reg[0]_16\ => \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_172\,
      \rd_mux_sel_r_reg[0]_17\ => \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_176\,
      \rd_mux_sel_r_reg[0]_18\ => \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_180\,
      \rd_mux_sel_r_reg[0]_19\ => \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_184\,
      \rd_mux_sel_r_reg[0]_2\ => \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_116\,
      \rd_mux_sel_r_reg[0]_20\ => \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_188\,
      \rd_mux_sel_r_reg[0]_21\ => \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_192\,
      \rd_mux_sel_r_reg[0]_22\ => \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_196\,
      \rd_mux_sel_r_reg[0]_23\ => \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_200\,
      \rd_mux_sel_r_reg[0]_24\ => \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_204\,
      \rd_mux_sel_r_reg[0]_25\ => \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_208\,
      \rd_mux_sel_r_reg[0]_26\ => \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_212\,
      \rd_mux_sel_r_reg[0]_27\ => \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_216\,
      \rd_mux_sel_r_reg[0]_28\ => \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_220\,
      \rd_mux_sel_r_reg[0]_29\ => \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_224\,
      \rd_mux_sel_r_reg[0]_3\ => \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_120\,
      \rd_mux_sel_r_reg[0]_30\ => \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_228\,
      \rd_mux_sel_r_reg[0]_31\ => \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_232\,
      \rd_mux_sel_r_reg[0]_32\ => \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_236\,
      \rd_mux_sel_r_reg[0]_33\ => \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_240\,
      \rd_mux_sel_r_reg[0]_34\ => \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_244\,
      \rd_mux_sel_r_reg[0]_35\ => \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_248\,
      \rd_mux_sel_r_reg[0]_36\ => \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_252\,
      \rd_mux_sel_r_reg[0]_37\ => \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_256\,
      \rd_mux_sel_r_reg[0]_38\ => \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_260\,
      \rd_mux_sel_r_reg[0]_39\ => \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_264\,
      \rd_mux_sel_r_reg[0]_4\ => \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_124\,
      \rd_mux_sel_r_reg[0]_40\ => \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_268\,
      \rd_mux_sel_r_reg[0]_41\ => \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_272\,
      \rd_mux_sel_r_reg[0]_42\ => \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_276\,
      \rd_mux_sel_r_reg[0]_43\ => \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_280\,
      \rd_mux_sel_r_reg[0]_44\ => \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_284\,
      \rd_mux_sel_r_reg[0]_45\ => \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_288\,
      \rd_mux_sel_r_reg[0]_46\ => \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_292\,
      \rd_mux_sel_r_reg[0]_47\ => \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_296\,
      \rd_mux_sel_r_reg[0]_48\ => \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_300\,
      \rd_mux_sel_r_reg[0]_49\ => \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_304\,
      \rd_mux_sel_r_reg[0]_5\ => \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_128\,
      \rd_mux_sel_r_reg[0]_50\ => \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_308\,
      \rd_mux_sel_r_reg[0]_51\ => \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_312\,
      \rd_mux_sel_r_reg[0]_52\ => \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_316\,
      \rd_mux_sel_r_reg[0]_53\ => \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_320\,
      \rd_mux_sel_r_reg[0]_54\ => \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_324\,
      \rd_mux_sel_r_reg[0]_55\ => \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_328\,
      \rd_mux_sel_r_reg[0]_56\ => \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_332\,
      \rd_mux_sel_r_reg[0]_57\ => \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_336\,
      \rd_mux_sel_r_reg[0]_58\ => \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_340\,
      \rd_mux_sel_r_reg[0]_59\ => \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_344\,
      \rd_mux_sel_r_reg[0]_6\ => \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_132\,
      \rd_mux_sel_r_reg[0]_60\ => \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_348\,
      \rd_mux_sel_r_reg[0]_61\ => \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_352\,
      \rd_mux_sel_r_reg[0]_62\ => \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_356\,
      \rd_mux_sel_r_reg[0]_7\ => \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_136\,
      \rd_mux_sel_r_reg[0]_8\ => \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_140\,
      \rd_mux_sel_r_reg[0]_9\ => \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_144\,
      \rd_mux_sel_r_reg[2]\ => \rd_mux_sel_r_reg[2]_63\,
      \rd_mux_sel_r_reg[2]_0\ => \rd_mux_sel_r_reg[2]_64\,
      \rd_mux_sel_r_reg[2]_1\ => \rd_mux_sel_r_reg[2]_65\,
      \rd_mux_sel_r_reg[2]_10\ => \rd_mux_sel_r_reg[2]_74\,
      \rd_mux_sel_r_reg[2]_11\ => \rd_mux_sel_r_reg[2]_75\,
      \rd_mux_sel_r_reg[2]_12\ => \rd_mux_sel_r_reg[2]_76\,
      \rd_mux_sel_r_reg[2]_13\ => \rd_mux_sel_r_reg[2]_77\,
      \rd_mux_sel_r_reg[2]_14\ => \rd_mux_sel_r_reg[2]_78\,
      \rd_mux_sel_r_reg[2]_15\ => \rd_mux_sel_r_reg[2]_79\,
      \rd_mux_sel_r_reg[2]_16\ => \rd_mux_sel_r_reg[2]_80\,
      \rd_mux_sel_r_reg[2]_17\ => \rd_mux_sel_r_reg[2]_81\,
      \rd_mux_sel_r_reg[2]_18\ => \rd_mux_sel_r_reg[2]_82\,
      \rd_mux_sel_r_reg[2]_19\ => \rd_mux_sel_r_reg[2]_83\,
      \rd_mux_sel_r_reg[2]_2\ => \rd_mux_sel_r_reg[2]_66\,
      \rd_mux_sel_r_reg[2]_20\ => \rd_mux_sel_r_reg[2]_84\,
      \rd_mux_sel_r_reg[2]_21\ => \rd_mux_sel_r_reg[2]_85\,
      \rd_mux_sel_r_reg[2]_22\ => \rd_mux_sel_r_reg[2]_86\,
      \rd_mux_sel_r_reg[2]_23\ => \rd_mux_sel_r_reg[2]_87\,
      \rd_mux_sel_r_reg[2]_24\ => \rd_mux_sel_r_reg[2]_88\,
      \rd_mux_sel_r_reg[2]_25\ => \rd_mux_sel_r_reg[2]_89\,
      \rd_mux_sel_r_reg[2]_26\ => \rd_mux_sel_r_reg[2]_90\,
      \rd_mux_sel_r_reg[2]_27\ => \rd_mux_sel_r_reg[2]_91\,
      \rd_mux_sel_r_reg[2]_28\ => \rd_mux_sel_r_reg[2]_92\,
      \rd_mux_sel_r_reg[2]_29\ => \rd_mux_sel_r_reg[2]_93\,
      \rd_mux_sel_r_reg[2]_3\ => \rd_mux_sel_r_reg[2]_67\,
      \rd_mux_sel_r_reg[2]_30\ => \rd_mux_sel_r_reg[2]_94\,
      \rd_mux_sel_r_reg[2]_31\ => \rd_mux_sel_r_reg[2]_95\,
      \rd_mux_sel_r_reg[2]_32\ => \rd_mux_sel_r_reg[2]_96\,
      \rd_mux_sel_r_reg[2]_33\ => \rd_mux_sel_r_reg[2]_97\,
      \rd_mux_sel_r_reg[2]_34\ => \rd_mux_sel_r_reg[2]_98\,
      \rd_mux_sel_r_reg[2]_35\ => \rd_mux_sel_r_reg[2]_99\,
      \rd_mux_sel_r_reg[2]_36\ => \rd_mux_sel_r_reg[2]_100\,
      \rd_mux_sel_r_reg[2]_37\ => \rd_mux_sel_r_reg[2]_101\,
      \rd_mux_sel_r_reg[2]_38\ => \rd_mux_sel_r_reg[2]_102\,
      \rd_mux_sel_r_reg[2]_39\ => \rd_mux_sel_r_reg[2]_103\,
      \rd_mux_sel_r_reg[2]_4\ => \rd_mux_sel_r_reg[2]_68\,
      \rd_mux_sel_r_reg[2]_40\ => \rd_mux_sel_r_reg[2]_104\,
      \rd_mux_sel_r_reg[2]_41\ => \rd_mux_sel_r_reg[2]_105\,
      \rd_mux_sel_r_reg[2]_42\ => \rd_mux_sel_r_reg[2]_106\,
      \rd_mux_sel_r_reg[2]_43\ => \rd_mux_sel_r_reg[2]_107\,
      \rd_mux_sel_r_reg[2]_44\ => \rd_mux_sel_r_reg[2]_108\,
      \rd_mux_sel_r_reg[2]_45\ => \rd_mux_sel_r_reg[2]_109\,
      \rd_mux_sel_r_reg[2]_46\ => \rd_mux_sel_r_reg[2]_110\,
      \rd_mux_sel_r_reg[2]_47\ => \rd_mux_sel_r_reg[2]_111\,
      \rd_mux_sel_r_reg[2]_48\ => \rd_mux_sel_r_reg[2]_112\,
      \rd_mux_sel_r_reg[2]_49\ => \rd_mux_sel_r_reg[2]_113\,
      \rd_mux_sel_r_reg[2]_5\ => \rd_mux_sel_r_reg[2]_69\,
      \rd_mux_sel_r_reg[2]_50\ => \rd_mux_sel_r_reg[2]_114\,
      \rd_mux_sel_r_reg[2]_51\ => \rd_mux_sel_r_reg[2]_115\,
      \rd_mux_sel_r_reg[2]_52\ => \rd_mux_sel_r_reg[2]_116\,
      \rd_mux_sel_r_reg[2]_53\ => \rd_mux_sel_r_reg[2]_117\,
      \rd_mux_sel_r_reg[2]_54\ => \rd_mux_sel_r_reg[2]_118\,
      \rd_mux_sel_r_reg[2]_55\ => \rd_mux_sel_r_reg[2]_119\,
      \rd_mux_sel_r_reg[2]_56\ => \rd_mux_sel_r_reg[2]_120\,
      \rd_mux_sel_r_reg[2]_57\ => \rd_mux_sel_r_reg[2]_121\,
      \rd_mux_sel_r_reg[2]_58\ => \rd_mux_sel_r_reg[2]_122\,
      \rd_mux_sel_r_reg[2]_59\ => \rd_mux_sel_r_reg[2]_123\,
      \rd_mux_sel_r_reg[2]_6\ => \rd_mux_sel_r_reg[2]_70\,
      \rd_mux_sel_r_reg[2]_60\ => \rd_mux_sel_r_reg[2]_124\,
      \rd_mux_sel_r_reg[2]_61\ => \rd_mux_sel_r_reg[2]_125\,
      \rd_mux_sel_r_reg[2]_62\ => \rd_mux_sel_r_reg[2]_126\,
      \rd_mux_sel_r_reg[2]_7\ => \rd_mux_sel_r_reg[2]_71\,
      \rd_mux_sel_r_reg[2]_8\ => \rd_mux_sel_r_reg[2]_72\,
      \rd_mux_sel_r_reg[2]_9\ => \rd_mux_sel_r_reg[2]_73\,
      \rd_ptr_reg[3]\(63 downto 0) => \rd_ptr_reg[3]_3\(63 downto 0),
      \rd_ptr_reg[3]_0\(63 downto 0) => \rd_ptr_reg[3]_4\(63 downto 0),
      \rd_ptr_reg[3]_1\(63 downto 0) => \rd_ptr_reg[3]_5\(63 downto 0),
      \rd_ptr_reg[3]_2\(63 downto 0) => \rd_ptr_reg[3]_6\(63 downto 0),
      \ref_dll_lock_w__0\(0) => \ref_dll_lock_w__0\(2),
      rst_out_reg_0 => \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_97\,
      rst_out_reg_1 => \rst_out_i_1__0_n_0\,
      rst_primitives => rst_primitives_1,
      rst_primitives_reg_0 => \rst_primitives_i_1__0_n_0\,
      sync_pulse => sync_pulse,
      ts_dqs_0 => ts_dqs_0,
      ts_dqs_1 => ts_dqs_1,
      ts_dqs_2 => ts_dqs_2,
      ts_dqs_3 => ts_dqs_3
    );
mcGo_r1: unisim.vcomponents.LUT3
    generic map(
      INIT => X"80"
    )
        port map (
      I0 => mcGo_w(0),
      I1 => mcGo_w(2),
      I2 => \mcGo_w__0\(1),
      O => \mcGo_r1__0\
    );
\mcGo_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => \mcGo_r1__0\,
      Q => mcGo_r(0),
      R => SR(0)
    );
\mcGo_r_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => mcGo_r(9),
      Q => mcGo_r(10),
      R => SR(0)
    );
\mcGo_r_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => mcGo_r(10),
      Q => mcGo_r(11),
      R => SR(0)
    );
\mcGo_r_reg[12]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => mcGo_r(11),
      Q => mcGo_r(12),
      R => SR(0)
    );
\mcGo_r_reg[13]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => mcGo_r(12),
      Q => mcGo_r(13),
      R => SR(0)
    );
\mcGo_r_reg[14]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => mcGo_r(13),
      Q => mcGo_r(14),
      R => SR(0)
    );
\mcGo_r_reg[15]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => mcGo_r(14),
      Q => \mcGo_r_reg[15]_0\(0),
      R => SR(0)
    );
\mcGo_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => mcGo_r(0),
      Q => mcGo_r(1),
      R => SR(0)
    );
\mcGo_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => mcGo_r(1),
      Q => mcGo_r(2),
      R => SR(0)
    );
\mcGo_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => mcGo_r(2),
      Q => mcGo_r(3),
      R => SR(0)
    );
\mcGo_r_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => mcGo_r(3),
      Q => mcGo_r(4),
      R => SR(0)
    );
\mcGo_r_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => mcGo_r(4),
      Q => mcGo_r(5),
      R => SR(0)
    );
\mcGo_r_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => mcGo_r(5),
      Q => mcGo_r(6),
      R => SR(0)
    );
\mcGo_r_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => mcGo_r(6),
      Q => mcGo_r(7),
      R => SR(0)
    );
\mcGo_r_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => mcGo_r(7),
      Q => mcGo_r(8),
      R => SR(0)
    );
\mcGo_r_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => mcGo_r(8),
      Q => mcGo_r(9),
      R => SR(0)
    );
phy_ctl_full0: unisim.vcomponents.LUT3
    generic map(
      INIT => X"FE"
    )
        port map (
      I0 => \_phy_ctl_full_p__0\(0),
      I1 => \_phy_ctl_full_p__0\(2),
      I2 => \_phy_ctl_full_p\(1),
      O => phy_mc_ctl_full
    );
phy_if_empty_r_i_2: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F888"
    )
        port map (
      I0 => \ddr_byte_lane_C.ddr_byte_lane_C/if_empty_r\(3),
      I1 => \ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/my_empty\(0),
      I2 => \ddr_byte_lane_B.ddr_byte_lane_B/if_empty_r\(3),
      I3 => \ddr_byte_lane_B.ddr_byte_lane_B/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/my_empty\(0),
      O => phy_if_empty_r_i_2_n_0
    );
\rclk_delay_reg[10]_srl11_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => rst_primitives,
      O => \rclk_delay_reg[10]_srl11_i_1_n_0\
    );
\rclk_delay_reg[10]_srl11_i_1__0\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => rst_primitives_1,
      O => \rclk_delay_reg[10]_srl11_i_1__0_n_0\
    );
ref_dll_lock: unisim.vcomponents.LUT6
    generic map(
      INIT => X"7FFFFFFFFFFFFFFF"
    )
        port map (
      I0 => \ref_dll_lock_w__0\(0),
      I1 => \ref_dll_lock_w__0\(2),
      I2 => ref_dll_lock_w(1),
      I3 => \rstdiv2_sync_r_reg[11]\,
      I4 => iodelay_ctrl_rdy(0),
      I5 => \out\,
      O => rst_tmp
    );
rst_out_i_1: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => rclk_delay_11,
      I1 => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_101\,
      O => rst_out_i_1_n_0
    );
\rst_out_i_1__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => rclk_delay_11_0,
      I1 => \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_97\,
      O => \rst_out_i_1__0_n_0\
    );
rst_primitives_i_1: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_97\,
      O => rst_primitives_i_1_n_0
    );
\rst_primitives_i_1__0\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_93\,
      O => \rst_primitives_i_1__0_n_0\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mig_mig_7series_v4_2_ddr_mc_phy_wrapper is
  port (
    ddr3_reset_n : out STD_LOGIC;
    ddr3_cas_n : out STD_LOGIC;
    ddr3_ras_n : out STD_LOGIC;
    ddr3_we_n : out STD_LOGIC;
    ddr3_addr : out STD_LOGIC_VECTOR ( 13 downto 0 );
    ddr3_ba : out STD_LOGIC_VECTOR ( 2 downto 0 );
    ddr3_cs_n : out STD_LOGIC_VECTOR ( 0 to 0 );
    ddr3_odt : out STD_LOGIC_VECTOR ( 0 to 0 );
    ddr3_cke : out STD_LOGIC_VECTOR ( 0 to 0 );
    ddr3_dm : out STD_LOGIC_VECTOR ( 7 downto 0 );
    A_rst_primitives_reg : out STD_LOGIC;
    in0 : out STD_LOGIC_VECTOR ( 7 downto 0 );
    idelay_ld_rst : out STD_LOGIC;
    A_rst_primitives_reg_0 : out STD_LOGIC;
    idelay_ld_rst_0 : out STD_LOGIC;
    A_rst_primitives_reg_1 : out STD_LOGIC;
    idelay_ld_rst_1 : out STD_LOGIC;
    A_rst_primitives_reg_2 : out STD_LOGIC;
    idelay_ld_rst_2 : out STD_LOGIC;
    A_rst_primitives_reg_3 : out STD_LOGIC;
    idelay_ld_rst_3 : out STD_LOGIC;
    A_rst_primitives_reg_4 : out STD_LOGIC;
    idelay_ld_rst_4 : out STD_LOGIC;
    A_rst_primitives_reg_5 : out STD_LOGIC;
    idelay_ld_rst_5 : out STD_LOGIC;
    A_rst_primitives_reg_6 : out STD_LOGIC;
    idelay_ld_rst_6 : out STD_LOGIC;
    phy_mc_ctl_full : out STD_LOGIC;
    rst_tmp : out STD_LOGIC;
    if_empty : out STD_LOGIC;
    \my_empty_reg[1]\ : out STD_LOGIC;
    phy_mc_data_full : out STD_LOGIC;
    \my_empty_reg[1]_0\ : out STD_LOGIC;
    \my_empty_reg[1]_1\ : out STD_LOGIC;
    \my_empty_reg[1]_2\ : out STD_LOGIC;
    A_rst_primitives_reg_7 : out STD_LOGIC;
    \my_empty_reg[1]_3\ : out STD_LOGIC;
    \my_empty_reg[1]_4\ : out STD_LOGIC;
    \my_empty_reg[1]_5\ : out STD_LOGIC;
    \my_empty_reg[1]_6\ : out STD_LOGIC;
    \my_empty_reg[1]_7\ : out STD_LOGIC;
    \my_empty_reg[1]_8\ : out STD_LOGIC;
    mem_out : out STD_LOGIC_VECTOR ( 11 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_5\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_6\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_5\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_6\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_5\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_6\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_5\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_6\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_5\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_6\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_5\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_6\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_5\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_6\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_5\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_6\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_5\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_6\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_5\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_6\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_5\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_6\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_5\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_6\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_5\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_6\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_5\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_6\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_5\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_6\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_5\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_6\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_5\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_6\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_5\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_6\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_5\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_6\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_5\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_6\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_5\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_6\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_5\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_6\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_5\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_6\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_5\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_6\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_5\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_6\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_5\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_6\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_5\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_6\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_5\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_6\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_5\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_6\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_5\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_6\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_5\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_6\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_5\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_6\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_5\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_6\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_5\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_6\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_5\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_6\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_5\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_6\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_5\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_6\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_5\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_6\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_5\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_6\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_5\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_6\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_5\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_6\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_5\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_6\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_5\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_6\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_5\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_6\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_5\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_6\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_5\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_6\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_5\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_6\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_5\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_6\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_5\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_6\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_5\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_6\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_5\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_6\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_5\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_6\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_5\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_6\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_5\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_6\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_5\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_6\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_5\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_6\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_0\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_1\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_2\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_3\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_4\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_5\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_6\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_7\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_8\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_9\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_10\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_11\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_12\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_13\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_14\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_15\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_16\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_17\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_18\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_19\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_20\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_21\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_22\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_23\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_24\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_25\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_26\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_27\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_28\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_29\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_30\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_31\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_32\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_33\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_34\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_35\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_36\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_37\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_38\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_39\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_40\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_41\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_42\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_43\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_44\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_45\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_46\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_47\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_48\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_49\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_50\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_51\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_52\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_53\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_54\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_55\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_56\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_57\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_58\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_59\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_60\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_61\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_62\ : out STD_LOGIC;
    phy_rddata_en : out STD_LOGIC;
    \rd_ptr_reg[3]\ : out STD_LOGIC_VECTOR ( 63 downto 0 );
    \rd_ptr_reg[3]_0\ : out STD_LOGIC_VECTOR ( 63 downto 0 );
    \rd_ptr_reg[3]_1\ : out STD_LOGIC_VECTOR ( 63 downto 0 );
    \rd_ptr_reg[3]_2\ : out STD_LOGIC_VECTOR ( 63 downto 0 );
    \pi_counter_read_val_reg[5]\ : out STD_LOGIC_VECTOR ( 5 downto 0 );
    \rd_ptr_reg[3]_3\ : out STD_LOGIC_VECTOR ( 63 downto 0 );
    \rd_ptr_reg[3]_4\ : out STD_LOGIC_VECTOR ( 63 downto 0 );
    \rd_ptr_reg[3]_5\ : out STD_LOGIC_VECTOR ( 63 downto 0 );
    \rd_ptr_reg[3]_6\ : out STD_LOGIC_VECTOR ( 63 downto 0 );
    \pi_counter_read_val_reg[5]_0\ : out STD_LOGIC_VECTOR ( 5 downto 0 );
    \rd_ptr_reg[3]_7\ : out STD_LOGIC_VECTOR ( 35 downto 0 );
    \mcGo_r_reg[15]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    \rd_mux_sel_r_reg[2]_63\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_64\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_65\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_66\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_67\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_68\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_69\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_70\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_71\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_72\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_73\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_74\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_75\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_76\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_77\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_78\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_79\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_80\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_81\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_82\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_83\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_84\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_85\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_86\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_87\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_88\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_89\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_90\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_91\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_92\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_93\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_94\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_95\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_96\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_97\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_98\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_99\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_100\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_101\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_102\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_103\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_104\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_105\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_106\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_107\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_108\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_109\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_110\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_111\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_112\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_113\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_114\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_115\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_116\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_117\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_118\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_119\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_120\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_121\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_122\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_123\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_124\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_125\ : out STD_LOGIC;
    \rd_mux_sel_r_reg[2]_126\ : out STD_LOGIC;
    \po_counter_read_val_reg[0]\ : out STD_LOGIC;
    \po_counter_read_val_reg[1]\ : out STD_LOGIC;
    \po_counter_read_val_reg[2]\ : out STD_LOGIC;
    \po_counter_read_val_reg[3]\ : out STD_LOGIC;
    \po_counter_read_val_reg[4]\ : out STD_LOGIC;
    \po_counter_read_val_reg[5]\ : out STD_LOGIC;
    \po_counter_read_val_reg[6]\ : out STD_LOGIC;
    \po_counter_read_val_reg[7]\ : out STD_LOGIC;
    \po_counter_read_val_reg[8]\ : out STD_LOGIC;
    p_0_out : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_0\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_1\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_2\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_3\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_4\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_5\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_6\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_7\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_8\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_9\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_10\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_11\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_12\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_13\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_14\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_15\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_16\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_17\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_18\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_19\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_20\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_21\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_22\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_23\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_24\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_25\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_26\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_27\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_28\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_29\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_30\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_31\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_32\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_33\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_34\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_35\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_36\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_37\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_38\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_39\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_40\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_41\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_42\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_43\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_44\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_45\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_46\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_47\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_48\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_49\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_50\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_51\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_52\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_53\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_54\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_55\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_56\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_57\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_58\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_59\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_60\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_61\ : out STD_LOGIC;
    ddr_ck_out : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \my_empty_reg[1]_9\ : out STD_LOGIC;
    \rd_ptr_reg[3]_8\ : out STD_LOGIC_VECTOR ( 23 downto 0 );
    of_ctl_full_v : out STD_LOGIC_VECTOR ( 0 to 0 );
    ddr3_dq : inout STD_LOGIC_VECTOR ( 63 downto 0 );
    ddr3_dqs_p : inout STD_LOGIC_VECTOR ( 7 downto 0 );
    ddr3_dqs_n : inout STD_LOGIC_VECTOR ( 7 downto 0 );
    mux_reset_n : in STD_LOGIC;
    idle : in STD_LOGIC;
    mmcm_ps_clk : in STD_LOGIC;
    rst_sync_r1 : in STD_LOGIC;
    phy_cmd_wr_en : in STD_LOGIC;
    \entry_cnt_reg[4]\ : in STD_LOGIC;
    \po_counter_read_val_reg[8]_0\ : in STD_LOGIC;
    \po_counter_read_val_reg[8]_1\ : in STD_LOGIC;
    \po_counter_read_val_reg[8]_2\ : in STD_LOGIC;
    \po_counter_read_val_reg[8]_3\ : in STD_LOGIC;
    freq_refclk : in STD_LOGIC;
    mem_refclk : in STD_LOGIC;
    sync_pulse : in STD_LOGIC;
    \my_full_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
    \my_full_reg[3]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \my_full_reg[3]_1\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \my_full_reg[3]_2\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \my_full_reg[3]_3\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
    \po_counter_read_val_reg[8]_4\ : in STD_LOGIC;
    \po_counter_read_val_reg[8]_5\ : in STD_LOGIC;
    \po_counter_read_val_reg[8]_6\ : in STD_LOGIC;
    \po_counter_read_val_reg[8]_7\ : in STD_LOGIC;
    D1 : in STD_LOGIC_VECTOR ( 3 downto 0 );
    D3 : in STD_LOGIC_VECTOR ( 3 downto 0 );
    D4 : in STD_LOGIC_VECTOR ( 3 downto 0 );
    D5 : in STD_LOGIC_VECTOR ( 3 downto 0 );
    D6 : in STD_LOGIC_VECTOR ( 7 downto 0 );
    D7 : in STD_LOGIC_VECTOR ( 3 downto 0 );
    D8 : in STD_LOGIC_VECTOR ( 3 downto 0 );
    \rd_ptr_reg[3]_9\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
    pll_locked : in STD_LOGIC;
    phy_read_calib : in STD_LOGIC;
    phy_mc_ctl_full_r_reg : in STD_LOGIC;
    phy_write_calib : in STD_LOGIC;
    \input_[9].iserdes_dq_.iserdesdq\ : in STD_LOGIC;
    idelay_inc : in STD_LOGIC;
    LD0 : in STD_LOGIC;
    CLKB0 : in STD_LOGIC;
    \pi_dqs_found_lanes_r1_reg[0]\ : in STD_LOGIC;
    \pi_dqs_found_lanes_r1_reg[0]_0\ : in STD_LOGIC;
    \pi_dqs_found_lanes_r1_reg[0]_1\ : in STD_LOGIC;
    \pi_dqs_found_lanes_r1_reg[0]_2\ : in STD_LOGIC;
    ififo_rst_reg : in STD_LOGIC;
    COUNTERLOADVAL : in STD_LOGIC_VECTOR ( 5 downto 0 );
    \po_counter_read_val_reg[8]_8\ : in STD_LOGIC;
    \po_counter_read_val_reg[8]_9\ : in STD_LOGIC;
    \po_counter_read_val_reg[8]_10\ : in STD_LOGIC;
    \my_empty_reg[7]\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \my_empty_reg[7]_0\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \my_empty_reg[7]_1\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \my_empty_reg[7]_2\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \my_empty_reg[7]_3\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \my_empty_reg[7]_4\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \my_empty_reg[7]_5\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \my_empty_reg[7]_6\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    phy_if_reset : in STD_LOGIC;
    \input_[9].iserdes_dq_.iserdesdq_0\ : in STD_LOGIC;
    LD0_7 : in STD_LOGIC;
    CLKB0_7 : in STD_LOGIC;
    \pi_dqs_found_lanes_r1_reg[1]\ : in STD_LOGIC;
    \pi_dqs_found_lanes_r1_reg[1]_0\ : in STD_LOGIC;
    \pi_dqs_found_lanes_r1_reg[1]_1\ : in STD_LOGIC;
    \pi_dqs_found_lanes_r1_reg[1]_2\ : in STD_LOGIC;
    ififo_rst_reg_0 : in STD_LOGIC;
    \pi_dqs_found_lanes_r1_reg[1]_3\ : in STD_LOGIC_VECTOR ( 5 downto 0 );
    \po_counter_read_val_reg[8]_11\ : in STD_LOGIC;
    \po_counter_read_val_reg[8]_12\ : in STD_LOGIC;
    \po_counter_read_val_reg[8]_13\ : in STD_LOGIC;
    \my_empty_reg[7]_7\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \my_empty_reg[7]_8\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \my_empty_reg[7]_9\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \my_empty_reg[7]_10\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \my_empty_reg[7]_11\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \my_empty_reg[7]_12\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \my_empty_reg[7]_13\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \my_empty_reg[7]_14\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \input_[9].iserdes_dq_.iserdesdq_1\ : in STD_LOGIC;
    LD0_8 : in STD_LOGIC;
    CLKB0_8 : in STD_LOGIC;
    \pi_dqs_found_lanes_r1_reg[2]\ : in STD_LOGIC;
    \pi_dqs_found_lanes_r1_reg[2]_0\ : in STD_LOGIC;
    \pi_dqs_found_lanes_r1_reg[2]_1\ : in STD_LOGIC;
    \pi_dqs_found_lanes_r1_reg[2]_2\ : in STD_LOGIC;
    ififo_rst_reg_1 : in STD_LOGIC;
    \pi_dqs_found_lanes_r1_reg[2]_3\ : in STD_LOGIC_VECTOR ( 5 downto 0 );
    \po_counter_read_val_reg[8]_14\ : in STD_LOGIC;
    \po_counter_read_val_reg[8]_15\ : in STD_LOGIC;
    \po_counter_read_val_reg[8]_16\ : in STD_LOGIC;
    \my_empty_reg[7]_15\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \my_empty_reg[7]_16\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \my_empty_reg[7]_17\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \my_empty_reg[7]_18\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \my_empty_reg[7]_19\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \my_empty_reg[7]_20\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \my_empty_reg[7]_21\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \my_empty_reg[7]_22\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \input_[9].iserdes_dq_.iserdesdq_2\ : in STD_LOGIC;
    LD0_9 : in STD_LOGIC;
    CLKB0_9 : in STD_LOGIC;
    \pi_dqs_found_lanes_r1_reg[3]\ : in STD_LOGIC;
    \pi_dqs_found_lanes_r1_reg[3]_0\ : in STD_LOGIC;
    \pi_dqs_found_lanes_r1_reg[3]_1\ : in STD_LOGIC;
    \pi_dqs_found_lanes_r1_reg[3]_2\ : in STD_LOGIC;
    ififo_rst_reg_2 : in STD_LOGIC;
    \pi_dqs_found_lanes_r1_reg[3]_3\ : in STD_LOGIC_VECTOR ( 5 downto 0 );
    \po_counter_read_val_reg[8]_17\ : in STD_LOGIC;
    \po_counter_read_val_reg[8]_18\ : in STD_LOGIC;
    \po_counter_read_val_reg[8]_19\ : in STD_LOGIC;
    \my_empty_reg[7]_23\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \my_empty_reg[7]_24\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \my_empty_reg[7]_25\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \my_empty_reg[7]_26\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \my_empty_reg[7]_27\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \my_empty_reg[7]_28\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \my_empty_reg[7]_29\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \my_empty_reg[7]_30\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    RST0 : in STD_LOGIC;
    SR : in STD_LOGIC_VECTOR ( 0 to 0 );
    \input_[9].iserdes_dq_.iserdesdq_3\ : in STD_LOGIC;
    LD0_10 : in STD_LOGIC;
    CLKB0_10 : in STD_LOGIC;
    \pi_dqs_found_lanes_r1_reg[8]\ : in STD_LOGIC;
    \pi_dqs_found_lanes_r1_reg[8]_0\ : in STD_LOGIC;
    \pi_dqs_found_lanes_r1_reg[8]_1\ : in STD_LOGIC;
    \pi_dqs_found_lanes_r1_reg[8]_2\ : in STD_LOGIC;
    ififo_rst_reg_3 : in STD_LOGIC;
    \pi_dqs_found_lanes_r1_reg[8]_3\ : in STD_LOGIC_VECTOR ( 5 downto 0 );
    \po_counter_read_val_reg[8]_20\ : in STD_LOGIC;
    \po_counter_read_val_reg[8]_21\ : in STD_LOGIC;
    \po_counter_read_val_reg[8]_22\ : in STD_LOGIC;
    \my_empty_reg[7]_31\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    D2 : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \my_empty_reg[7]_32\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \my_empty_reg[7]_33\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \my_empty_reg[7]_34\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \my_empty_reg[7]_35\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \my_empty_reg[7]_36\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \my_empty_reg[7]_37\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \input_[9].iserdes_dq_.iserdesdq_4\ : in STD_LOGIC;
    LD0_11 : in STD_LOGIC;
    CLKB0_11 : in STD_LOGIC;
    \pi_dqs_found_lanes_r1_reg[9]\ : in STD_LOGIC;
    \pi_dqs_found_lanes_r1_reg[9]_0\ : in STD_LOGIC;
    \pi_dqs_found_lanes_r1_reg[9]_1\ : in STD_LOGIC;
    \pi_dqs_found_lanes_r1_reg[9]_2\ : in STD_LOGIC;
    ififo_rst_reg_4 : in STD_LOGIC;
    \pi_dqs_found_lanes_r1_reg[9]_3\ : in STD_LOGIC_VECTOR ( 5 downto 0 );
    \po_counter_read_val_reg[8]_23\ : in STD_LOGIC;
    \po_counter_read_val_reg[8]_24\ : in STD_LOGIC;
    \po_counter_read_val_reg[8]_25\ : in STD_LOGIC;
    \my_empty_reg[7]_38\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \my_empty_reg[7]_39\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \my_empty_reg[7]_40\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \my_empty_reg[7]_41\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \my_empty_reg[7]_42\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \my_empty_reg[7]_43\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \my_empty_reg[7]_44\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \my_empty_reg[7]_45\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \input_[9].iserdes_dq_.iserdesdq_5\ : in STD_LOGIC;
    LD0_12 : in STD_LOGIC;
    CLKB0_12 : in STD_LOGIC;
    \pi_dqs_found_lanes_r1_reg[10]\ : in STD_LOGIC;
    \pi_dqs_found_lanes_r1_reg[10]_0\ : in STD_LOGIC;
    \pi_dqs_found_lanes_r1_reg[10]_1\ : in STD_LOGIC;
    \pi_dqs_found_lanes_r1_reg[10]_2\ : in STD_LOGIC;
    ififo_rst_reg_5 : in STD_LOGIC;
    \pi_dqs_found_lanes_r1_reg[10]_3\ : in STD_LOGIC_VECTOR ( 5 downto 0 );
    \po_counter_read_val_reg[8]_26\ : in STD_LOGIC;
    \po_counter_read_val_reg[8]_27\ : in STD_LOGIC;
    \po_counter_read_val_reg[8]_28\ : in STD_LOGIC;
    \my_empty_reg[7]_46\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \my_empty_reg[7]_47\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \my_empty_reg[7]_48\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \my_empty_reg[7]_49\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \my_empty_reg[7]_50\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \my_empty_reg[7]_51\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \my_empty_reg[7]_52\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \my_empty_reg[7]_53\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \input_[9].iserdes_dq_.iserdesdq_6\ : in STD_LOGIC;
    LD0_13 : in STD_LOGIC;
    CLKB0_13 : in STD_LOGIC;
    \pi_dqs_found_lanes_r1_reg[11]\ : in STD_LOGIC;
    \pi_dqs_found_lanes_r1_reg[11]_0\ : in STD_LOGIC;
    \pi_dqs_found_lanes_r1_reg[11]_1\ : in STD_LOGIC;
    \pi_dqs_found_lanes_r1_reg[11]_2\ : in STD_LOGIC;
    ififo_rst_reg_6 : in STD_LOGIC;
    \pi_dqs_found_lanes_r1_reg[11]_3\ : in STD_LOGIC_VECTOR ( 5 downto 0 );
    \po_counter_read_val_reg[8]_29\ : in STD_LOGIC;
    \po_counter_read_val_reg[8]_30\ : in STD_LOGIC;
    \po_counter_read_val_reg[8]_31\ : in STD_LOGIC;
    \my_empty_reg[7]_54\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \my_empty_reg[7]_55\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \my_empty_reg[7]_56\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \my_empty_reg[7]_57\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \my_empty_reg[7]_58\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \my_empty_reg[7]_59\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \my_empty_reg[7]_60\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \my_empty_reg[7]_61\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \rstdiv2_sync_r_reg[11]\ : in STD_LOGIC;
    iodelay_ctrl_rdy : in STD_LOGIC_VECTOR ( 0 to 0 );
    \out\ : in STD_LOGIC;
    phy_data_wr_en : in STD_LOGIC;
    \gen_mux_rd[0].mux_rd_rise0_r_reg[0]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    out_fifo : in STD_LOGIC;
    mc_cas_n : in STD_LOGIC_VECTOR ( 2 downto 0 );
    mc_we_n : in STD_LOGIC_VECTOR ( 1 downto 0 );
    out_fifo_0 : in STD_LOGIC;
    mc_ras_n : in STD_LOGIC_VECTOR ( 1 downto 0 );
    mc_cs_n : in STD_LOGIC_VECTOR ( 0 to 0 );
    mc_address : in STD_LOGIC_VECTOR ( 3 downto 0 );
    Q : in STD_LOGIC_VECTOR ( 63 downto 0 );
    out_fifo_1 : in STD_LOGIC;
    \gen_mux_rd[1].mux_rd_rise0_r_reg[1]\ : in STD_LOGIC;
    D : in STD_LOGIC_VECTOR ( 10 downto 0 );
    \data_offset_1_i1_reg[5]_0\ : in STD_LOGIC_VECTOR ( 5 downto 0 );
    \data_offset_2_i1_reg[5]_0\ : in STD_LOGIC_VECTOR ( 5 downto 0 );
    phy_dout : in STD_LOGIC_VECTOR ( 71 downto 0 );
    \out_fifo_i_75__5\ : in STD_LOGIC_VECTOR ( 71 downto 0 );
    \out_fifo_i_75__6\ : in STD_LOGIC_VECTOR ( 71 downto 0 );
    \out_fifo_i_75__7\ : in STD_LOGIC_VECTOR ( 71 downto 0 );
    \out_fifo_i_75__0\ : in STD_LOGIC_VECTOR ( 71 downto 0 );
    \out_fifo_i_75__1\ : in STD_LOGIC_VECTOR ( 71 downto 0 );
    \out_fifo_i_75__2\ : in STD_LOGIC_VECTOR ( 71 downto 0 );
    \out_fifo_i_75__3\ : in STD_LOGIC_VECTOR ( 71 downto 0 );
    \out_fifo_i_47__8\ : in STD_LOGIC_VECTOR ( 12 downto 0 );
    mux_address : in STD_LOGIC_VECTOR ( 48 downto 0 );
    d_in : in STD_LOGIC_VECTOR ( 4 downto 0 );
    \po_counter_read_val_reg[0]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    calib_sel : in STD_LOGIC_VECTOR ( 3 downto 0 );
    \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
    C_po_coarse_enable26_out : in STD_LOGIC;
    C_po_counter_read_en38_out : in STD_LOGIC;
    C_po_fine_enable23_out : in STD_LOGIC;
    C_po_fine_inc29_out : in STD_LOGIC;
    \my_empty_reg[7]_62\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
    \my_empty_reg[7]_63\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \my_empty_reg[7]_64\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
    \my_empty_reg[7]_65\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
    D9 : in STD_LOGIC_VECTOR ( 3 downto 0 );
    out_fifo_i_39 : in STD_LOGIC_VECTOR ( 11 downto 0 );
    out_fifo_2 : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of mig_mig_7series_v4_2_ddr_mc_phy_wrapper : entity is "mig_7series_v4_2_ddr_mc_phy_wrapper";
end mig_mig_7series_v4_2_ddr_mc_phy_wrapper;

architecture STRUCTURE of mig_mig_7series_v4_2_ddr_mc_phy_wrapper is
  signal data_offset_1_i1 : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal data_offset_1_i2 : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal data_offset_2_i1 : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal data_offset_2_i2 : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal in_dqs_lpbk_to_iddr_0 : STD_LOGIC;
  signal in_dqs_lpbk_to_iddr_1 : STD_LOGIC;
  signal in_dqs_lpbk_to_iddr_2 : STD_LOGIC;
  signal in_dqs_lpbk_to_iddr_3 : STD_LOGIC;
  signal in_dqs_lpbk_to_iddr_4 : STD_LOGIC;
  signal in_dqs_lpbk_to_iddr_5 : STD_LOGIC;
  signal in_dqs_lpbk_to_iddr_6 : STD_LOGIC;
  signal in_dqs_lpbk_to_iddr_7 : STD_LOGIC;
  signal mem_dq_in : STD_LOGIC_VECTOR ( 119 downto 1 );
  signal mem_dq_out : STD_LOGIC_VECTOR ( 141 downto 0 );
  signal mem_dq_ts : STD_LOGIC_VECTOR ( 141 downto 0 );
  signal mem_dqs_in : STD_LOGIC_VECTOR ( 11 downto 0 );
  signal out_dqs_0 : STD_LOGIC;
  signal out_dqs_1 : STD_LOGIC;
  signal out_dqs_2 : STD_LOGIC;
  signal out_dqs_3 : STD_LOGIC;
  signal out_dqs_4 : STD_LOGIC;
  signal out_dqs_5 : STD_LOGIC;
  signal out_dqs_6 : STD_LOGIC;
  signal out_dqs_7 : STD_LOGIC;
  signal phy_ctl_wd_i1 : STD_LOGIC_VECTOR ( 24 downto 0 );
  signal phy_ctl_wd_i2 : STD_LOGIC_VECTOR ( 24 downto 0 );
  signal phy_ctl_wr_i1 : STD_LOGIC;
  signal phy_ctl_wr_i2 : STD_LOGIC;
  signal ts_dqs_0 : STD_LOGIC;
  signal ts_dqs_1 : STD_LOGIC;
  signal ts_dqs_2 : STD_LOGIC;
  signal ts_dqs_3 : STD_LOGIC;
  signal ts_dqs_4 : STD_LOGIC;
  signal ts_dqs_5 : STD_LOGIC;
  signal ts_dqs_6 : STD_LOGIC;
  signal ts_dqs_7 : STD_LOGIC;
  attribute BOX_TYPE : string;
  attribute BOX_TYPE of \cke_odt_thru_outfifo.gen_cke_obuf[0].u_cs_n_obuf\ : label is "PRIMITIVE";
  attribute CAPACITANCE : string;
  attribute CAPACITANCE of \cke_odt_thru_outfifo.gen_cke_obuf[0].u_cs_n_obuf\ : label is "DONT_CARE";
  attribute BOX_TYPE of \cke_odt_thru_outfifo.gen_odt_obuf.gen_odt_obuf[0].u_cs_n_obuf\ : label is "PRIMITIVE";
  attribute CAPACITANCE of \cke_odt_thru_outfifo.gen_odt_obuf.gen_odt_obuf[0].u_cs_n_obuf\ : label is "DONT_CARE";
  attribute BOX_TYPE of \gen_addr_obuf[0].u_addr_obuf\ : label is "PRIMITIVE";
  attribute CAPACITANCE of \gen_addr_obuf[0].u_addr_obuf\ : label is "DONT_CARE";
  attribute BOX_TYPE of \gen_addr_obuf[10].u_addr_obuf\ : label is "PRIMITIVE";
  attribute CAPACITANCE of \gen_addr_obuf[10].u_addr_obuf\ : label is "DONT_CARE";
  attribute BOX_TYPE of \gen_addr_obuf[11].u_addr_obuf\ : label is "PRIMITIVE";
  attribute CAPACITANCE of \gen_addr_obuf[11].u_addr_obuf\ : label is "DONT_CARE";
  attribute BOX_TYPE of \gen_addr_obuf[12].u_addr_obuf\ : label is "PRIMITIVE";
  attribute CAPACITANCE of \gen_addr_obuf[12].u_addr_obuf\ : label is "DONT_CARE";
  attribute BOX_TYPE of \gen_addr_obuf[13].u_addr_obuf\ : label is "PRIMITIVE";
  attribute CAPACITANCE of \gen_addr_obuf[13].u_addr_obuf\ : label is "DONT_CARE";
  attribute BOX_TYPE of \gen_addr_obuf[1].u_addr_obuf\ : label is "PRIMITIVE";
  attribute CAPACITANCE of \gen_addr_obuf[1].u_addr_obuf\ : label is "DONT_CARE";
  attribute BOX_TYPE of \gen_addr_obuf[2].u_addr_obuf\ : label is "PRIMITIVE";
  attribute CAPACITANCE of \gen_addr_obuf[2].u_addr_obuf\ : label is "DONT_CARE";
  attribute BOX_TYPE of \gen_addr_obuf[3].u_addr_obuf\ : label is "PRIMITIVE";
  attribute CAPACITANCE of \gen_addr_obuf[3].u_addr_obuf\ : label is "DONT_CARE";
  attribute BOX_TYPE of \gen_addr_obuf[4].u_addr_obuf\ : label is "PRIMITIVE";
  attribute CAPACITANCE of \gen_addr_obuf[4].u_addr_obuf\ : label is "DONT_CARE";
  attribute BOX_TYPE of \gen_addr_obuf[5].u_addr_obuf\ : label is "PRIMITIVE";
  attribute CAPACITANCE of \gen_addr_obuf[5].u_addr_obuf\ : label is "DONT_CARE";
  attribute BOX_TYPE of \gen_addr_obuf[6].u_addr_obuf\ : label is "PRIMITIVE";
  attribute CAPACITANCE of \gen_addr_obuf[6].u_addr_obuf\ : label is "DONT_CARE";
  attribute BOX_TYPE of \gen_addr_obuf[7].u_addr_obuf\ : label is "PRIMITIVE";
  attribute CAPACITANCE of \gen_addr_obuf[7].u_addr_obuf\ : label is "DONT_CARE";
  attribute BOX_TYPE of \gen_addr_obuf[8].u_addr_obuf\ : label is "PRIMITIVE";
  attribute CAPACITANCE of \gen_addr_obuf[8].u_addr_obuf\ : label is "DONT_CARE";
  attribute BOX_TYPE of \gen_addr_obuf[9].u_addr_obuf\ : label is "PRIMITIVE";
  attribute CAPACITANCE of \gen_addr_obuf[9].u_addr_obuf\ : label is "DONT_CARE";
  attribute BOX_TYPE of \gen_bank_obuf[0].u_bank_obuf\ : label is "PRIMITIVE";
  attribute CAPACITANCE of \gen_bank_obuf[0].u_bank_obuf\ : label is "DONT_CARE";
  attribute BOX_TYPE of \gen_bank_obuf[1].u_bank_obuf\ : label is "PRIMITIVE";
  attribute CAPACITANCE of \gen_bank_obuf[1].u_bank_obuf\ : label is "DONT_CARE";
  attribute BOX_TYPE of \gen_bank_obuf[2].u_bank_obuf\ : label is "PRIMITIVE";
  attribute CAPACITANCE of \gen_bank_obuf[2].u_bank_obuf\ : label is "DONT_CARE";
  attribute BOX_TYPE of \gen_cs_n_obuf.gen_cs_obuf[0].u_cs_n_obuf\ : label is "PRIMITIVE";
  attribute CAPACITANCE of \gen_cs_n_obuf.gen_cs_obuf[0].u_cs_n_obuf\ : label is "DONT_CARE";
  attribute BOX_TYPE of \gen_dm_obuf.loop_dm[0].u_dm_obuf\ : label is "PRIMITIVE";
  attribute CAPACITANCE of \gen_dm_obuf.loop_dm[0].u_dm_obuf\ : label is "DONT_CARE";
  attribute BOX_TYPE of \gen_dm_obuf.loop_dm[1].u_dm_obuf\ : label is "PRIMITIVE";
  attribute CAPACITANCE of \gen_dm_obuf.loop_dm[1].u_dm_obuf\ : label is "DONT_CARE";
  attribute BOX_TYPE of \gen_dm_obuf.loop_dm[2].u_dm_obuf\ : label is "PRIMITIVE";
  attribute CAPACITANCE of \gen_dm_obuf.loop_dm[2].u_dm_obuf\ : label is "DONT_CARE";
  attribute BOX_TYPE of \gen_dm_obuf.loop_dm[3].u_dm_obuf\ : label is "PRIMITIVE";
  attribute CAPACITANCE of \gen_dm_obuf.loop_dm[3].u_dm_obuf\ : label is "DONT_CARE";
  attribute BOX_TYPE of \gen_dm_obuf.loop_dm[4].u_dm_obuf\ : label is "PRIMITIVE";
  attribute CAPACITANCE of \gen_dm_obuf.loop_dm[4].u_dm_obuf\ : label is "DONT_CARE";
  attribute BOX_TYPE of \gen_dm_obuf.loop_dm[5].u_dm_obuf\ : label is "PRIMITIVE";
  attribute CAPACITANCE of \gen_dm_obuf.loop_dm[5].u_dm_obuf\ : label is "DONT_CARE";
  attribute BOX_TYPE of \gen_dm_obuf.loop_dm[6].u_dm_obuf\ : label is "PRIMITIVE";
  attribute CAPACITANCE of \gen_dm_obuf.loop_dm[6].u_dm_obuf\ : label is "DONT_CARE";
  attribute BOX_TYPE of \gen_dm_obuf.loop_dm[7].u_dm_obuf\ : label is "PRIMITIVE";
  attribute CAPACITANCE of \gen_dm_obuf.loop_dm[7].u_dm_obuf\ : label is "DONT_CARE";
  attribute BOX_TYPE of \gen_dq_iobuf_HR.gen_dq_iobuf[0].u_iobuf_dq\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \gen_dq_iobuf_HR.gen_dq_iobuf[10].u_iobuf_dq\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \gen_dq_iobuf_HR.gen_dq_iobuf[11].u_iobuf_dq\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \gen_dq_iobuf_HR.gen_dq_iobuf[12].u_iobuf_dq\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \gen_dq_iobuf_HR.gen_dq_iobuf[13].u_iobuf_dq\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \gen_dq_iobuf_HR.gen_dq_iobuf[14].u_iobuf_dq\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \gen_dq_iobuf_HR.gen_dq_iobuf[15].u_iobuf_dq\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \gen_dq_iobuf_HR.gen_dq_iobuf[16].u_iobuf_dq\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \gen_dq_iobuf_HR.gen_dq_iobuf[17].u_iobuf_dq\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \gen_dq_iobuf_HR.gen_dq_iobuf[18].u_iobuf_dq\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \gen_dq_iobuf_HR.gen_dq_iobuf[19].u_iobuf_dq\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \gen_dq_iobuf_HR.gen_dq_iobuf[1].u_iobuf_dq\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \gen_dq_iobuf_HR.gen_dq_iobuf[20].u_iobuf_dq\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \gen_dq_iobuf_HR.gen_dq_iobuf[21].u_iobuf_dq\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \gen_dq_iobuf_HR.gen_dq_iobuf[22].u_iobuf_dq\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \gen_dq_iobuf_HR.gen_dq_iobuf[23].u_iobuf_dq\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \gen_dq_iobuf_HR.gen_dq_iobuf[24].u_iobuf_dq\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \gen_dq_iobuf_HR.gen_dq_iobuf[25].u_iobuf_dq\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \gen_dq_iobuf_HR.gen_dq_iobuf[26].u_iobuf_dq\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \gen_dq_iobuf_HR.gen_dq_iobuf[27].u_iobuf_dq\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \gen_dq_iobuf_HR.gen_dq_iobuf[28].u_iobuf_dq\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \gen_dq_iobuf_HR.gen_dq_iobuf[29].u_iobuf_dq\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \gen_dq_iobuf_HR.gen_dq_iobuf[2].u_iobuf_dq\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \gen_dq_iobuf_HR.gen_dq_iobuf[30].u_iobuf_dq\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \gen_dq_iobuf_HR.gen_dq_iobuf[31].u_iobuf_dq\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \gen_dq_iobuf_HR.gen_dq_iobuf[32].u_iobuf_dq\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \gen_dq_iobuf_HR.gen_dq_iobuf[33].u_iobuf_dq\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \gen_dq_iobuf_HR.gen_dq_iobuf[34].u_iobuf_dq\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \gen_dq_iobuf_HR.gen_dq_iobuf[35].u_iobuf_dq\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \gen_dq_iobuf_HR.gen_dq_iobuf[36].u_iobuf_dq\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \gen_dq_iobuf_HR.gen_dq_iobuf[37].u_iobuf_dq\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \gen_dq_iobuf_HR.gen_dq_iobuf[38].u_iobuf_dq\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \gen_dq_iobuf_HR.gen_dq_iobuf[39].u_iobuf_dq\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \gen_dq_iobuf_HR.gen_dq_iobuf[3].u_iobuf_dq\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \gen_dq_iobuf_HR.gen_dq_iobuf[40].u_iobuf_dq\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \gen_dq_iobuf_HR.gen_dq_iobuf[41].u_iobuf_dq\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \gen_dq_iobuf_HR.gen_dq_iobuf[42].u_iobuf_dq\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \gen_dq_iobuf_HR.gen_dq_iobuf[43].u_iobuf_dq\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \gen_dq_iobuf_HR.gen_dq_iobuf[44].u_iobuf_dq\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \gen_dq_iobuf_HR.gen_dq_iobuf[45].u_iobuf_dq\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \gen_dq_iobuf_HR.gen_dq_iobuf[46].u_iobuf_dq\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \gen_dq_iobuf_HR.gen_dq_iobuf[47].u_iobuf_dq\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \gen_dq_iobuf_HR.gen_dq_iobuf[48].u_iobuf_dq\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \gen_dq_iobuf_HR.gen_dq_iobuf[49].u_iobuf_dq\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \gen_dq_iobuf_HR.gen_dq_iobuf[4].u_iobuf_dq\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \gen_dq_iobuf_HR.gen_dq_iobuf[50].u_iobuf_dq\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \gen_dq_iobuf_HR.gen_dq_iobuf[51].u_iobuf_dq\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \gen_dq_iobuf_HR.gen_dq_iobuf[52].u_iobuf_dq\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \gen_dq_iobuf_HR.gen_dq_iobuf[53].u_iobuf_dq\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \gen_dq_iobuf_HR.gen_dq_iobuf[54].u_iobuf_dq\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \gen_dq_iobuf_HR.gen_dq_iobuf[55].u_iobuf_dq\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \gen_dq_iobuf_HR.gen_dq_iobuf[56].u_iobuf_dq\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \gen_dq_iobuf_HR.gen_dq_iobuf[57].u_iobuf_dq\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \gen_dq_iobuf_HR.gen_dq_iobuf[58].u_iobuf_dq\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \gen_dq_iobuf_HR.gen_dq_iobuf[59].u_iobuf_dq\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \gen_dq_iobuf_HR.gen_dq_iobuf[5].u_iobuf_dq\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \gen_dq_iobuf_HR.gen_dq_iobuf[60].u_iobuf_dq\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \gen_dq_iobuf_HR.gen_dq_iobuf[61].u_iobuf_dq\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \gen_dq_iobuf_HR.gen_dq_iobuf[62].u_iobuf_dq\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \gen_dq_iobuf_HR.gen_dq_iobuf[63].u_iobuf_dq\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \gen_dq_iobuf_HR.gen_dq_iobuf[6].u_iobuf_dq\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \gen_dq_iobuf_HR.gen_dq_iobuf[7].u_iobuf_dq\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \gen_dq_iobuf_HR.gen_dq_iobuf[8].u_iobuf_dq\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \gen_dq_iobuf_HR.gen_dq_iobuf[9].u_iobuf_dq\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \gen_dqs_iobuf_HR.gen_dqs_iobuf[0].gen_dqs_diff.u_iobuf_dqs\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \gen_dqs_iobuf_HR.gen_dqs_iobuf[1].gen_dqs_diff.u_iobuf_dqs\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \gen_dqs_iobuf_HR.gen_dqs_iobuf[2].gen_dqs_diff.u_iobuf_dqs\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \gen_dqs_iobuf_HR.gen_dqs_iobuf[3].gen_dqs_diff.u_iobuf_dqs\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \gen_dqs_iobuf_HR.gen_dqs_iobuf[4].gen_dqs_diff.u_iobuf_dqs\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \gen_dqs_iobuf_HR.gen_dqs_iobuf[5].gen_dqs_diff.u_iobuf_dqs\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \gen_dqs_iobuf_HR.gen_dqs_iobuf[6].gen_dqs_diff.u_iobuf_dqs\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \gen_dqs_iobuf_HR.gen_dqs_iobuf[7].gen_dqs_diff.u_iobuf_dqs\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \gen_reset_obuf.u_reset_obuf\ : label is "PRIMITIVE";
  attribute CAPACITANCE of \gen_reset_obuf.u_reset_obuf\ : label is "DONT_CARE";
  attribute BOX_TYPE of u_cas_n_obuf : label is "PRIMITIVE";
  attribute CAPACITANCE of u_cas_n_obuf : label is "DONT_CARE";
  attribute BOX_TYPE of u_ras_n_obuf : label is "PRIMITIVE";
  attribute CAPACITANCE of u_ras_n_obuf : label is "DONT_CARE";
  attribute BOX_TYPE of u_we_n_obuf : label is "PRIMITIVE";
  attribute CAPACITANCE of u_we_n_obuf : label is "DONT_CARE";
begin
\cke_odt_thru_outfifo.gen_cke_obuf[0].u_cs_n_obuf\: unisim.vcomponents.OBUF
    generic map(
      IOSTANDARD => "DEFAULT"
    )
        port map (
      I => mem_dq_out(67),
      O => ddr3_cke(0)
    );
\cke_odt_thru_outfifo.gen_odt_obuf.gen_odt_obuf[0].u_cs_n_obuf\: unisim.vcomponents.OBUF
    generic map(
      IOSTANDARD => "DEFAULT"
    )
        port map (
      I => mem_dq_out(62),
      O => ddr3_odt(0)
    );
\data_offset_1_i1_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => \data_offset_1_i1_reg[5]_0\(0),
      Q => data_offset_1_i1(0),
      R => '0'
    );
\data_offset_1_i1_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => \data_offset_1_i1_reg[5]_0\(1),
      Q => data_offset_1_i1(1),
      R => '0'
    );
\data_offset_1_i1_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => \data_offset_1_i1_reg[5]_0\(2),
      Q => data_offset_1_i1(2),
      R => '0'
    );
\data_offset_1_i1_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => \data_offset_1_i1_reg[5]_0\(3),
      Q => data_offset_1_i1(3),
      R => '0'
    );
\data_offset_1_i1_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => \data_offset_1_i1_reg[5]_0\(4),
      Q => data_offset_1_i1(4),
      R => '0'
    );
\data_offset_1_i1_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => \data_offset_1_i1_reg[5]_0\(5),
      Q => data_offset_1_i1(5),
      R => '0'
    );
\data_offset_1_i2_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => data_offset_1_i1(0),
      Q => data_offset_1_i2(0),
      R => '0'
    );
\data_offset_1_i2_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => data_offset_1_i1(1),
      Q => data_offset_1_i2(1),
      R => '0'
    );
\data_offset_1_i2_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => data_offset_1_i1(2),
      Q => data_offset_1_i2(2),
      R => '0'
    );
\data_offset_1_i2_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => data_offset_1_i1(3),
      Q => data_offset_1_i2(3),
      R => '0'
    );
\data_offset_1_i2_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => data_offset_1_i1(4),
      Q => data_offset_1_i2(4),
      R => '0'
    );
\data_offset_1_i2_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => data_offset_1_i1(5),
      Q => data_offset_1_i2(5),
      R => '0'
    );
\data_offset_2_i1_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => \data_offset_2_i1_reg[5]_0\(0),
      Q => data_offset_2_i1(0),
      R => '0'
    );
\data_offset_2_i1_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => \data_offset_2_i1_reg[5]_0\(1),
      Q => data_offset_2_i1(1),
      R => '0'
    );
\data_offset_2_i1_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => \data_offset_2_i1_reg[5]_0\(2),
      Q => data_offset_2_i1(2),
      R => '0'
    );
\data_offset_2_i1_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => \data_offset_2_i1_reg[5]_0\(3),
      Q => data_offset_2_i1(3),
      R => '0'
    );
\data_offset_2_i1_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => \data_offset_2_i1_reg[5]_0\(4),
      Q => data_offset_2_i1(4),
      R => '0'
    );
\data_offset_2_i1_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => \data_offset_2_i1_reg[5]_0\(5),
      Q => data_offset_2_i1(5),
      R => '0'
    );
\data_offset_2_i2_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => data_offset_2_i1(0),
      Q => data_offset_2_i2(0),
      R => '0'
    );
\data_offset_2_i2_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => data_offset_2_i1(1),
      Q => data_offset_2_i2(1),
      R => '0'
    );
\data_offset_2_i2_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => data_offset_2_i1(2),
      Q => data_offset_2_i2(2),
      R => '0'
    );
\data_offset_2_i2_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => data_offset_2_i1(3),
      Q => data_offset_2_i2(3),
      R => '0'
    );
\data_offset_2_i2_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => data_offset_2_i1(4),
      Q => data_offset_2_i2(4),
      R => '0'
    );
\data_offset_2_i2_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => data_offset_2_i1(5),
      Q => data_offset_2_i2(5),
      R => '0'
    );
\gen_addr_obuf[0].u_addr_obuf\: unisim.vcomponents.OBUF
    generic map(
      IOSTANDARD => "DEFAULT"
    )
        port map (
      I => mem_dq_out(95),
      O => ddr3_addr(0)
    );
\gen_addr_obuf[10].u_addr_obuf\: unisim.vcomponents.OBUF
    generic map(
      IOSTANDARD => "DEFAULT"
    )
        port map (
      I => mem_dq_out(87),
      O => ddr3_addr(10)
    );
\gen_addr_obuf[11].u_addr_obuf\: unisim.vcomponents.OBUF
    generic map(
      IOSTANDARD => "DEFAULT"
    )
        port map (
      I => mem_dq_out(89),
      O => ddr3_addr(11)
    );
\gen_addr_obuf[12].u_addr_obuf\: unisim.vcomponents.OBUF
    generic map(
      IOSTANDARD => "DEFAULT"
    )
        port map (
      I => mem_dq_out(90),
      O => ddr3_addr(12)
    );
\gen_addr_obuf[13].u_addr_obuf\: unisim.vcomponents.OBUF
    generic map(
      IOSTANDARD => "DEFAULT"
    )
        port map (
      I => mem_dq_out(86),
      O => ddr3_addr(13)
    );
\gen_addr_obuf[1].u_addr_obuf\: unisim.vcomponents.OBUF
    generic map(
      IOSTANDARD => "DEFAULT"
    )
        port map (
      I => mem_dq_out(92),
      O => ddr3_addr(1)
    );
\gen_addr_obuf[2].u_addr_obuf\: unisim.vcomponents.OBUF
    generic map(
      IOSTANDARD => "DEFAULT"
    )
        port map (
      I => mem_dq_out(80),
      O => ddr3_addr(2)
    );
\gen_addr_obuf[3].u_addr_obuf\: unisim.vcomponents.OBUF
    generic map(
      IOSTANDARD => "DEFAULT"
    )
        port map (
      I => mem_dq_out(94),
      O => ddr3_addr(3)
    );
\gen_addr_obuf[4].u_addr_obuf\: unisim.vcomponents.OBUF
    generic map(
      IOSTANDARD => "DEFAULT"
    )
        port map (
      I => mem_dq_out(88),
      O => ddr3_addr(4)
    );
\gen_addr_obuf[5].u_addr_obuf\: unisim.vcomponents.OBUF
    generic map(
      IOSTANDARD => "DEFAULT"
    )
        port map (
      I => mem_dq_out(91),
      O => ddr3_addr(5)
    );
\gen_addr_obuf[6].u_addr_obuf\: unisim.vcomponents.OBUF
    generic map(
      IOSTANDARD => "DEFAULT"
    )
        port map (
      I => mem_dq_out(81),
      O => ddr3_addr(6)
    );
\gen_addr_obuf[7].u_addr_obuf\: unisim.vcomponents.OBUF
    generic map(
      IOSTANDARD => "DEFAULT"
    )
        port map (
      I => mem_dq_out(85),
      O => ddr3_addr(7)
    );
\gen_addr_obuf[8].u_addr_obuf\: unisim.vcomponents.OBUF
    generic map(
      IOSTANDARD => "DEFAULT"
    )
        port map (
      I => mem_dq_out(76),
      O => ddr3_addr(8)
    );
\gen_addr_obuf[9].u_addr_obuf\: unisim.vcomponents.OBUF
    generic map(
      IOSTANDARD => "DEFAULT"
    )
        port map (
      I => mem_dq_out(93),
      O => ddr3_addr(9)
    );
\gen_bank_obuf[0].u_bank_obuf\: unisim.vcomponents.OBUF
    generic map(
      IOSTANDARD => "DEFAULT"
    )
        port map (
      I => mem_dq_out(83),
      O => ddr3_ba(0)
    );
\gen_bank_obuf[1].u_bank_obuf\: unisim.vcomponents.OBUF
    generic map(
      IOSTANDARD => "DEFAULT"
    )
        port map (
      I => mem_dq_out(82),
      O => ddr3_ba(1)
    );
\gen_bank_obuf[2].u_bank_obuf\: unisim.vcomponents.OBUF
    generic map(
      IOSTANDARD => "DEFAULT"
    )
        port map (
      I => mem_dq_out(77),
      O => ddr3_ba(2)
    );
\gen_cs_n_obuf.gen_cs_obuf[0].u_cs_n_obuf\: unisim.vcomponents.OBUF
    generic map(
      IOSTANDARD => "DEFAULT"
    )
        port map (
      I => mem_dq_out(64),
      O => ddr3_cs_n(0)
    );
\gen_dm_obuf.loop_dm[0].u_dm_obuf\: unisim.vcomponents.OBUFT
    generic map(
      IOSTANDARD => "DEFAULT"
    )
        port map (
      I => mem_dq_out(96),
      O => ddr3_dm(0),
      T => mem_dq_ts(96)
    );
\gen_dm_obuf.loop_dm[1].u_dm_obuf\: unisim.vcomponents.OBUFT
    generic map(
      IOSTANDARD => "DEFAULT"
    )
        port map (
      I => mem_dq_out(109),
      O => ddr3_dm(1),
      T => mem_dq_ts(109)
    );
\gen_dm_obuf.loop_dm[2].u_dm_obuf\: unisim.vcomponents.OBUFT
    generic map(
      IOSTANDARD => "DEFAULT"
    )
        port map (
      I => mem_dq_out(121),
      O => ddr3_dm(2),
      T => mem_dq_ts(121)
    );
\gen_dm_obuf.loop_dm[3].u_dm_obuf\: unisim.vcomponents.OBUFT
    generic map(
      IOSTANDARD => "DEFAULT"
    )
        port map (
      I => mem_dq_out(133),
      O => ddr3_dm(3),
      T => mem_dq_ts(133)
    );
\gen_dm_obuf.loop_dm[4].u_dm_obuf\: unisim.vcomponents.OBUFT
    generic map(
      IOSTANDARD => "DEFAULT"
    )
        port map (
      I => mem_dq_out(0),
      O => ddr3_dm(4),
      T => mem_dq_ts(0)
    );
\gen_dm_obuf.loop_dm[5].u_dm_obuf\: unisim.vcomponents.OBUFT
    generic map(
      IOSTANDARD => "DEFAULT"
    )
        port map (
      I => mem_dq_out(13),
      O => ddr3_dm(5),
      T => mem_dq_ts(13)
    );
\gen_dm_obuf.loop_dm[6].u_dm_obuf\: unisim.vcomponents.OBUFT
    generic map(
      IOSTANDARD => "DEFAULT"
    )
        port map (
      I => mem_dq_out(25),
      O => ddr3_dm(6),
      T => mem_dq_ts(25)
    );
\gen_dm_obuf.loop_dm[7].u_dm_obuf\: unisim.vcomponents.OBUFT
    generic map(
      IOSTANDARD => "DEFAULT"
    )
        port map (
      I => mem_dq_out(37),
      O => ddr3_dm(7),
      T => mem_dq_ts(37)
    );
\gen_dq_iobuf_HR.gen_dq_iobuf[0].u_iobuf_dq\: unisim.vcomponents.IOBUF_INTERMDISABLE
    generic map(
      IOSTANDARD => "DEFAULT",
      SIM_DEVICE => "7SERIES",
      USE_IBUFDISABLE => "TRUE"
    )
        port map (
      I => mem_dq_out(97),
      IBUFDISABLE => idle,
      INTERMDISABLE => idle,
      IO => ddr3_dq(0),
      O => mem_dq_in(81),
      T => mem_dq_ts(97)
    );
\gen_dq_iobuf_HR.gen_dq_iobuf[10].u_iobuf_dq\: unisim.vcomponents.IOBUF_INTERMDISABLE
    generic map(
      IOSTANDARD => "DEFAULT",
      SIM_DEVICE => "7SERIES",
      USE_IBUFDISABLE => "TRUE"
    )
        port map (
      I => mem_dq_out(112),
      IBUFDISABLE => idle,
      INTERMDISABLE => idle,
      IO => ddr3_dq(10),
      O => mem_dq_in(94),
      T => mem_dq_ts(112)
    );
\gen_dq_iobuf_HR.gen_dq_iobuf[11].u_iobuf_dq\: unisim.vcomponents.IOBUF_INTERMDISABLE
    generic map(
      IOSTANDARD => "DEFAULT",
      SIM_DEVICE => "7SERIES",
      USE_IBUFDISABLE => "TRUE"
    )
        port map (
      I => mem_dq_out(113),
      IBUFDISABLE => idle,
      INTERMDISABLE => idle,
      IO => ddr3_dq(11),
      O => mem_dq_in(95),
      T => mem_dq_ts(113)
    );
\gen_dq_iobuf_HR.gen_dq_iobuf[12].u_iobuf_dq\: unisim.vcomponents.IOBUF_INTERMDISABLE
    generic map(
      IOSTANDARD => "DEFAULT",
      SIM_DEVICE => "7SERIES",
      USE_IBUFDISABLE => "TRUE"
    )
        port map (
      I => mem_dq_out(114),
      IBUFDISABLE => idle,
      INTERMDISABLE => idle,
      IO => ddr3_dq(12),
      O => mem_dq_in(96),
      T => mem_dq_ts(114)
    );
\gen_dq_iobuf_HR.gen_dq_iobuf[13].u_iobuf_dq\: unisim.vcomponents.IOBUF_INTERMDISABLE
    generic map(
      IOSTANDARD => "DEFAULT",
      SIM_DEVICE => "7SERIES",
      USE_IBUFDISABLE => "TRUE"
    )
        port map (
      I => mem_dq_out(115),
      IBUFDISABLE => idle,
      INTERMDISABLE => idle,
      IO => ddr3_dq(13),
      O => mem_dq_in(97),
      T => mem_dq_ts(115)
    );
\gen_dq_iobuf_HR.gen_dq_iobuf[14].u_iobuf_dq\: unisim.vcomponents.IOBUF_INTERMDISABLE
    generic map(
      IOSTANDARD => "DEFAULT",
      SIM_DEVICE => "7SERIES",
      USE_IBUFDISABLE => "TRUE"
    )
        port map (
      I => mem_dq_out(116),
      IBUFDISABLE => idle,
      INTERMDISABLE => idle,
      IO => ddr3_dq(14),
      O => mem_dq_in(98),
      T => mem_dq_ts(116)
    );
\gen_dq_iobuf_HR.gen_dq_iobuf[15].u_iobuf_dq\: unisim.vcomponents.IOBUF_INTERMDISABLE
    generic map(
      IOSTANDARD => "DEFAULT",
      SIM_DEVICE => "7SERIES",
      USE_IBUFDISABLE => "TRUE"
    )
        port map (
      I => mem_dq_out(117),
      IBUFDISABLE => idle,
      INTERMDISABLE => idle,
      IO => ddr3_dq(15),
      O => mem_dq_in(99),
      T => mem_dq_ts(117)
    );
\gen_dq_iobuf_HR.gen_dq_iobuf[16].u_iobuf_dq\: unisim.vcomponents.IOBUF_INTERMDISABLE
    generic map(
      IOSTANDARD => "DEFAULT",
      SIM_DEVICE => "7SERIES",
      USE_IBUFDISABLE => "TRUE"
    )
        port map (
      I => mem_dq_out(122),
      IBUFDISABLE => idle,
      INTERMDISABLE => idle,
      IO => ddr3_dq(16),
      O => mem_dq_in(102),
      T => mem_dq_ts(122)
    );
\gen_dq_iobuf_HR.gen_dq_iobuf[17].u_iobuf_dq\: unisim.vcomponents.IOBUF_INTERMDISABLE
    generic map(
      IOSTANDARD => "DEFAULT",
      SIM_DEVICE => "7SERIES",
      USE_IBUFDISABLE => "TRUE"
    )
        port map (
      I => mem_dq_out(123),
      IBUFDISABLE => idle,
      INTERMDISABLE => idle,
      IO => ddr3_dq(17),
      O => mem_dq_in(103),
      T => mem_dq_ts(123)
    );
\gen_dq_iobuf_HR.gen_dq_iobuf[18].u_iobuf_dq\: unisim.vcomponents.IOBUF_INTERMDISABLE
    generic map(
      IOSTANDARD => "DEFAULT",
      SIM_DEVICE => "7SERIES",
      USE_IBUFDISABLE => "TRUE"
    )
        port map (
      I => mem_dq_out(124),
      IBUFDISABLE => idle,
      INTERMDISABLE => idle,
      IO => ddr3_dq(18),
      O => mem_dq_in(104),
      T => mem_dq_ts(124)
    );
\gen_dq_iobuf_HR.gen_dq_iobuf[19].u_iobuf_dq\: unisim.vcomponents.IOBUF_INTERMDISABLE
    generic map(
      IOSTANDARD => "DEFAULT",
      SIM_DEVICE => "7SERIES",
      USE_IBUFDISABLE => "TRUE"
    )
        port map (
      I => mem_dq_out(125),
      IBUFDISABLE => idle,
      INTERMDISABLE => idle,
      IO => ddr3_dq(19),
      O => mem_dq_in(105),
      T => mem_dq_ts(125)
    );
\gen_dq_iobuf_HR.gen_dq_iobuf[1].u_iobuf_dq\: unisim.vcomponents.IOBUF_INTERMDISABLE
    generic map(
      IOSTANDARD => "DEFAULT",
      SIM_DEVICE => "7SERIES",
      USE_IBUFDISABLE => "TRUE"
    )
        port map (
      I => mem_dq_out(98),
      IBUFDISABLE => idle,
      INTERMDISABLE => idle,
      IO => ddr3_dq(1),
      O => mem_dq_in(82),
      T => mem_dq_ts(98)
    );
\gen_dq_iobuf_HR.gen_dq_iobuf[20].u_iobuf_dq\: unisim.vcomponents.IOBUF_INTERMDISABLE
    generic map(
      IOSTANDARD => "DEFAULT",
      SIM_DEVICE => "7SERIES",
      USE_IBUFDISABLE => "TRUE"
    )
        port map (
      I => mem_dq_out(126),
      IBUFDISABLE => idle,
      INTERMDISABLE => idle,
      IO => ddr3_dq(20),
      O => mem_dq_in(106),
      T => mem_dq_ts(126)
    );
\gen_dq_iobuf_HR.gen_dq_iobuf[21].u_iobuf_dq\: unisim.vcomponents.IOBUF_INTERMDISABLE
    generic map(
      IOSTANDARD => "DEFAULT",
      SIM_DEVICE => "7SERIES",
      USE_IBUFDISABLE => "TRUE"
    )
        port map (
      I => mem_dq_out(127),
      IBUFDISABLE => idle,
      INTERMDISABLE => idle,
      IO => ddr3_dq(21),
      O => mem_dq_in(107),
      T => mem_dq_ts(127)
    );
\gen_dq_iobuf_HR.gen_dq_iobuf[22].u_iobuf_dq\: unisim.vcomponents.IOBUF_INTERMDISABLE
    generic map(
      IOSTANDARD => "DEFAULT",
      SIM_DEVICE => "7SERIES",
      USE_IBUFDISABLE => "TRUE"
    )
        port map (
      I => mem_dq_out(128),
      IBUFDISABLE => idle,
      INTERMDISABLE => idle,
      IO => ddr3_dq(22),
      O => mem_dq_in(108),
      T => mem_dq_ts(128)
    );
\gen_dq_iobuf_HR.gen_dq_iobuf[23].u_iobuf_dq\: unisim.vcomponents.IOBUF_INTERMDISABLE
    generic map(
      IOSTANDARD => "DEFAULT",
      SIM_DEVICE => "7SERIES",
      USE_IBUFDISABLE => "TRUE"
    )
        port map (
      I => mem_dq_out(129),
      IBUFDISABLE => idle,
      INTERMDISABLE => idle,
      IO => ddr3_dq(23),
      O => mem_dq_in(109),
      T => mem_dq_ts(129)
    );
\gen_dq_iobuf_HR.gen_dq_iobuf[24].u_iobuf_dq\: unisim.vcomponents.IOBUF_INTERMDISABLE
    generic map(
      IOSTANDARD => "DEFAULT",
      SIM_DEVICE => "7SERIES",
      USE_IBUFDISABLE => "TRUE"
    )
        port map (
      I => mem_dq_out(134),
      IBUFDISABLE => idle,
      INTERMDISABLE => idle,
      IO => ddr3_dq(24),
      O => mem_dq_in(112),
      T => mem_dq_ts(134)
    );
\gen_dq_iobuf_HR.gen_dq_iobuf[25].u_iobuf_dq\: unisim.vcomponents.IOBUF_INTERMDISABLE
    generic map(
      IOSTANDARD => "DEFAULT",
      SIM_DEVICE => "7SERIES",
      USE_IBUFDISABLE => "TRUE"
    )
        port map (
      I => mem_dq_out(135),
      IBUFDISABLE => idle,
      INTERMDISABLE => idle,
      IO => ddr3_dq(25),
      O => mem_dq_in(113),
      T => mem_dq_ts(135)
    );
\gen_dq_iobuf_HR.gen_dq_iobuf[26].u_iobuf_dq\: unisim.vcomponents.IOBUF_INTERMDISABLE
    generic map(
      IOSTANDARD => "DEFAULT",
      SIM_DEVICE => "7SERIES",
      USE_IBUFDISABLE => "TRUE"
    )
        port map (
      I => mem_dq_out(136),
      IBUFDISABLE => idle,
      INTERMDISABLE => idle,
      IO => ddr3_dq(26),
      O => mem_dq_in(114),
      T => mem_dq_ts(136)
    );
\gen_dq_iobuf_HR.gen_dq_iobuf[27].u_iobuf_dq\: unisim.vcomponents.IOBUF_INTERMDISABLE
    generic map(
      IOSTANDARD => "DEFAULT",
      SIM_DEVICE => "7SERIES",
      USE_IBUFDISABLE => "TRUE"
    )
        port map (
      I => mem_dq_out(137),
      IBUFDISABLE => idle,
      INTERMDISABLE => idle,
      IO => ddr3_dq(27),
      O => mem_dq_in(115),
      T => mem_dq_ts(137)
    );
\gen_dq_iobuf_HR.gen_dq_iobuf[28].u_iobuf_dq\: unisim.vcomponents.IOBUF_INTERMDISABLE
    generic map(
      IOSTANDARD => "DEFAULT",
      SIM_DEVICE => "7SERIES",
      USE_IBUFDISABLE => "TRUE"
    )
        port map (
      I => mem_dq_out(138),
      IBUFDISABLE => idle,
      INTERMDISABLE => idle,
      IO => ddr3_dq(28),
      O => mem_dq_in(116),
      T => mem_dq_ts(138)
    );
\gen_dq_iobuf_HR.gen_dq_iobuf[29].u_iobuf_dq\: unisim.vcomponents.IOBUF_INTERMDISABLE
    generic map(
      IOSTANDARD => "DEFAULT",
      SIM_DEVICE => "7SERIES",
      USE_IBUFDISABLE => "TRUE"
    )
        port map (
      I => mem_dq_out(139),
      IBUFDISABLE => idle,
      INTERMDISABLE => idle,
      IO => ddr3_dq(29),
      O => mem_dq_in(117),
      T => mem_dq_ts(139)
    );
\gen_dq_iobuf_HR.gen_dq_iobuf[2].u_iobuf_dq\: unisim.vcomponents.IOBUF_INTERMDISABLE
    generic map(
      IOSTANDARD => "DEFAULT",
      SIM_DEVICE => "7SERIES",
      USE_IBUFDISABLE => "TRUE"
    )
        port map (
      I => mem_dq_out(99),
      IBUFDISABLE => idle,
      INTERMDISABLE => idle,
      IO => ddr3_dq(2),
      O => mem_dq_in(83),
      T => mem_dq_ts(99)
    );
\gen_dq_iobuf_HR.gen_dq_iobuf[30].u_iobuf_dq\: unisim.vcomponents.IOBUF_INTERMDISABLE
    generic map(
      IOSTANDARD => "DEFAULT",
      SIM_DEVICE => "7SERIES",
      USE_IBUFDISABLE => "TRUE"
    )
        port map (
      I => mem_dq_out(140),
      IBUFDISABLE => idle,
      INTERMDISABLE => idle,
      IO => ddr3_dq(30),
      O => mem_dq_in(118),
      T => mem_dq_ts(140)
    );
\gen_dq_iobuf_HR.gen_dq_iobuf[31].u_iobuf_dq\: unisim.vcomponents.IOBUF_INTERMDISABLE
    generic map(
      IOSTANDARD => "DEFAULT",
      SIM_DEVICE => "7SERIES",
      USE_IBUFDISABLE => "TRUE"
    )
        port map (
      I => mem_dq_out(141),
      IBUFDISABLE => idle,
      INTERMDISABLE => idle,
      IO => ddr3_dq(31),
      O => mem_dq_in(119),
      T => mem_dq_ts(141)
    );
\gen_dq_iobuf_HR.gen_dq_iobuf[32].u_iobuf_dq\: unisim.vcomponents.IOBUF_INTERMDISABLE
    generic map(
      IOSTANDARD => "DEFAULT",
      SIM_DEVICE => "7SERIES",
      USE_IBUFDISABLE => "TRUE"
    )
        port map (
      I => mem_dq_out(1),
      IBUFDISABLE => idle,
      INTERMDISABLE => idle,
      IO => ddr3_dq(32),
      O => mem_dq_in(1),
      T => mem_dq_ts(1)
    );
\gen_dq_iobuf_HR.gen_dq_iobuf[33].u_iobuf_dq\: unisim.vcomponents.IOBUF_INTERMDISABLE
    generic map(
      IOSTANDARD => "DEFAULT",
      SIM_DEVICE => "7SERIES",
      USE_IBUFDISABLE => "TRUE"
    )
        port map (
      I => mem_dq_out(2),
      IBUFDISABLE => idle,
      INTERMDISABLE => idle,
      IO => ddr3_dq(33),
      O => mem_dq_in(2),
      T => mem_dq_ts(2)
    );
\gen_dq_iobuf_HR.gen_dq_iobuf[34].u_iobuf_dq\: unisim.vcomponents.IOBUF_INTERMDISABLE
    generic map(
      IOSTANDARD => "DEFAULT",
      SIM_DEVICE => "7SERIES",
      USE_IBUFDISABLE => "TRUE"
    )
        port map (
      I => mem_dq_out(3),
      IBUFDISABLE => idle,
      INTERMDISABLE => idle,
      IO => ddr3_dq(34),
      O => mem_dq_in(3),
      T => mem_dq_ts(3)
    );
\gen_dq_iobuf_HR.gen_dq_iobuf[35].u_iobuf_dq\: unisim.vcomponents.IOBUF_INTERMDISABLE
    generic map(
      IOSTANDARD => "DEFAULT",
      SIM_DEVICE => "7SERIES",
      USE_IBUFDISABLE => "TRUE"
    )
        port map (
      I => mem_dq_out(4),
      IBUFDISABLE => idle,
      INTERMDISABLE => idle,
      IO => ddr3_dq(35),
      O => mem_dq_in(4),
      T => mem_dq_ts(4)
    );
\gen_dq_iobuf_HR.gen_dq_iobuf[36].u_iobuf_dq\: unisim.vcomponents.IOBUF_INTERMDISABLE
    generic map(
      IOSTANDARD => "DEFAULT",
      SIM_DEVICE => "7SERIES",
      USE_IBUFDISABLE => "TRUE"
    )
        port map (
      I => mem_dq_out(5),
      IBUFDISABLE => idle,
      INTERMDISABLE => idle,
      IO => ddr3_dq(36),
      O => mem_dq_in(5),
      T => mem_dq_ts(5)
    );
\gen_dq_iobuf_HR.gen_dq_iobuf[37].u_iobuf_dq\: unisim.vcomponents.IOBUF_INTERMDISABLE
    generic map(
      IOSTANDARD => "DEFAULT",
      SIM_DEVICE => "7SERIES",
      USE_IBUFDISABLE => "TRUE"
    )
        port map (
      I => mem_dq_out(6),
      IBUFDISABLE => idle,
      INTERMDISABLE => idle,
      IO => ddr3_dq(37),
      O => mem_dq_in(6),
      T => mem_dq_ts(6)
    );
\gen_dq_iobuf_HR.gen_dq_iobuf[38].u_iobuf_dq\: unisim.vcomponents.IOBUF_INTERMDISABLE
    generic map(
      IOSTANDARD => "DEFAULT",
      SIM_DEVICE => "7SERIES",
      USE_IBUFDISABLE => "TRUE"
    )
        port map (
      I => mem_dq_out(7),
      IBUFDISABLE => idle,
      INTERMDISABLE => idle,
      IO => ddr3_dq(38),
      O => mem_dq_in(7),
      T => mem_dq_ts(7)
    );
\gen_dq_iobuf_HR.gen_dq_iobuf[39].u_iobuf_dq\: unisim.vcomponents.IOBUF_INTERMDISABLE
    generic map(
      IOSTANDARD => "DEFAULT",
      SIM_DEVICE => "7SERIES",
      USE_IBUFDISABLE => "TRUE"
    )
        port map (
      I => mem_dq_out(9),
      IBUFDISABLE => idle,
      INTERMDISABLE => idle,
      IO => ddr3_dq(39),
      O => mem_dq_in(9),
      T => mem_dq_ts(9)
    );
\gen_dq_iobuf_HR.gen_dq_iobuf[3].u_iobuf_dq\: unisim.vcomponents.IOBUF_INTERMDISABLE
    generic map(
      IOSTANDARD => "DEFAULT",
      SIM_DEVICE => "7SERIES",
      USE_IBUFDISABLE => "TRUE"
    )
        port map (
      I => mem_dq_out(100),
      IBUFDISABLE => idle,
      INTERMDISABLE => idle,
      IO => ddr3_dq(3),
      O => mem_dq_in(84),
      T => mem_dq_ts(100)
    );
\gen_dq_iobuf_HR.gen_dq_iobuf[40].u_iobuf_dq\: unisim.vcomponents.IOBUF_INTERMDISABLE
    generic map(
      IOSTANDARD => "DEFAULT",
      SIM_DEVICE => "7SERIES",
      USE_IBUFDISABLE => "TRUE"
    )
        port map (
      I => mem_dq_out(14),
      IBUFDISABLE => idle,
      INTERMDISABLE => idle,
      IO => ddr3_dq(40),
      O => mem_dq_in(12),
      T => mem_dq_ts(14)
    );
\gen_dq_iobuf_HR.gen_dq_iobuf[41].u_iobuf_dq\: unisim.vcomponents.IOBUF_INTERMDISABLE
    generic map(
      IOSTANDARD => "DEFAULT",
      SIM_DEVICE => "7SERIES",
      USE_IBUFDISABLE => "TRUE"
    )
        port map (
      I => mem_dq_out(15),
      IBUFDISABLE => idle,
      INTERMDISABLE => idle,
      IO => ddr3_dq(41),
      O => mem_dq_in(13),
      T => mem_dq_ts(15)
    );
\gen_dq_iobuf_HR.gen_dq_iobuf[42].u_iobuf_dq\: unisim.vcomponents.IOBUF_INTERMDISABLE
    generic map(
      IOSTANDARD => "DEFAULT",
      SIM_DEVICE => "7SERIES",
      USE_IBUFDISABLE => "TRUE"
    )
        port map (
      I => mem_dq_out(16),
      IBUFDISABLE => idle,
      INTERMDISABLE => idle,
      IO => ddr3_dq(42),
      O => mem_dq_in(14),
      T => mem_dq_ts(16)
    );
\gen_dq_iobuf_HR.gen_dq_iobuf[43].u_iobuf_dq\: unisim.vcomponents.IOBUF_INTERMDISABLE
    generic map(
      IOSTANDARD => "DEFAULT",
      SIM_DEVICE => "7SERIES",
      USE_IBUFDISABLE => "TRUE"
    )
        port map (
      I => mem_dq_out(17),
      IBUFDISABLE => idle,
      INTERMDISABLE => idle,
      IO => ddr3_dq(43),
      O => mem_dq_in(15),
      T => mem_dq_ts(17)
    );
\gen_dq_iobuf_HR.gen_dq_iobuf[44].u_iobuf_dq\: unisim.vcomponents.IOBUF_INTERMDISABLE
    generic map(
      IOSTANDARD => "DEFAULT",
      SIM_DEVICE => "7SERIES",
      USE_IBUFDISABLE => "TRUE"
    )
        port map (
      I => mem_dq_out(18),
      IBUFDISABLE => idle,
      INTERMDISABLE => idle,
      IO => ddr3_dq(44),
      O => mem_dq_in(16),
      T => mem_dq_ts(18)
    );
\gen_dq_iobuf_HR.gen_dq_iobuf[45].u_iobuf_dq\: unisim.vcomponents.IOBUF_INTERMDISABLE
    generic map(
      IOSTANDARD => "DEFAULT",
      SIM_DEVICE => "7SERIES",
      USE_IBUFDISABLE => "TRUE"
    )
        port map (
      I => mem_dq_out(19),
      IBUFDISABLE => idle,
      INTERMDISABLE => idle,
      IO => ddr3_dq(45),
      O => mem_dq_in(17),
      T => mem_dq_ts(19)
    );
\gen_dq_iobuf_HR.gen_dq_iobuf[46].u_iobuf_dq\: unisim.vcomponents.IOBUF_INTERMDISABLE
    generic map(
      IOSTANDARD => "DEFAULT",
      SIM_DEVICE => "7SERIES",
      USE_IBUFDISABLE => "TRUE"
    )
        port map (
      I => mem_dq_out(20),
      IBUFDISABLE => idle,
      INTERMDISABLE => idle,
      IO => ddr3_dq(46),
      O => mem_dq_in(18),
      T => mem_dq_ts(20)
    );
\gen_dq_iobuf_HR.gen_dq_iobuf[47].u_iobuf_dq\: unisim.vcomponents.IOBUF_INTERMDISABLE
    generic map(
      IOSTANDARD => "DEFAULT",
      SIM_DEVICE => "7SERIES",
      USE_IBUFDISABLE => "TRUE"
    )
        port map (
      I => mem_dq_out(21),
      IBUFDISABLE => idle,
      INTERMDISABLE => idle,
      IO => ddr3_dq(47),
      O => mem_dq_in(19),
      T => mem_dq_ts(21)
    );
\gen_dq_iobuf_HR.gen_dq_iobuf[48].u_iobuf_dq\: unisim.vcomponents.IOBUF_INTERMDISABLE
    generic map(
      IOSTANDARD => "DEFAULT",
      SIM_DEVICE => "7SERIES",
      USE_IBUFDISABLE => "TRUE"
    )
        port map (
      I => mem_dq_out(26),
      IBUFDISABLE => idle,
      INTERMDISABLE => idle,
      IO => ddr3_dq(48),
      O => mem_dq_in(22),
      T => mem_dq_ts(26)
    );
\gen_dq_iobuf_HR.gen_dq_iobuf[49].u_iobuf_dq\: unisim.vcomponents.IOBUF_INTERMDISABLE
    generic map(
      IOSTANDARD => "DEFAULT",
      SIM_DEVICE => "7SERIES",
      USE_IBUFDISABLE => "TRUE"
    )
        port map (
      I => mem_dq_out(27),
      IBUFDISABLE => idle,
      INTERMDISABLE => idle,
      IO => ddr3_dq(49),
      O => mem_dq_in(23),
      T => mem_dq_ts(27)
    );
\gen_dq_iobuf_HR.gen_dq_iobuf[4].u_iobuf_dq\: unisim.vcomponents.IOBUF_INTERMDISABLE
    generic map(
      IOSTANDARD => "DEFAULT",
      SIM_DEVICE => "7SERIES",
      USE_IBUFDISABLE => "TRUE"
    )
        port map (
      I => mem_dq_out(101),
      IBUFDISABLE => idle,
      INTERMDISABLE => idle,
      IO => ddr3_dq(4),
      O => mem_dq_in(85),
      T => mem_dq_ts(101)
    );
\gen_dq_iobuf_HR.gen_dq_iobuf[50].u_iobuf_dq\: unisim.vcomponents.IOBUF_INTERMDISABLE
    generic map(
      IOSTANDARD => "DEFAULT",
      SIM_DEVICE => "7SERIES",
      USE_IBUFDISABLE => "TRUE"
    )
        port map (
      I => mem_dq_out(28),
      IBUFDISABLE => idle,
      INTERMDISABLE => idle,
      IO => ddr3_dq(50),
      O => mem_dq_in(24),
      T => mem_dq_ts(28)
    );
\gen_dq_iobuf_HR.gen_dq_iobuf[51].u_iobuf_dq\: unisim.vcomponents.IOBUF_INTERMDISABLE
    generic map(
      IOSTANDARD => "DEFAULT",
      SIM_DEVICE => "7SERIES",
      USE_IBUFDISABLE => "TRUE"
    )
        port map (
      I => mem_dq_out(29),
      IBUFDISABLE => idle,
      INTERMDISABLE => idle,
      IO => ddr3_dq(51),
      O => mem_dq_in(25),
      T => mem_dq_ts(29)
    );
\gen_dq_iobuf_HR.gen_dq_iobuf[52].u_iobuf_dq\: unisim.vcomponents.IOBUF_INTERMDISABLE
    generic map(
      IOSTANDARD => "DEFAULT",
      SIM_DEVICE => "7SERIES",
      USE_IBUFDISABLE => "TRUE"
    )
        port map (
      I => mem_dq_out(30),
      IBUFDISABLE => idle,
      INTERMDISABLE => idle,
      IO => ddr3_dq(52),
      O => mem_dq_in(26),
      T => mem_dq_ts(30)
    );
\gen_dq_iobuf_HR.gen_dq_iobuf[53].u_iobuf_dq\: unisim.vcomponents.IOBUF_INTERMDISABLE
    generic map(
      IOSTANDARD => "DEFAULT",
      SIM_DEVICE => "7SERIES",
      USE_IBUFDISABLE => "TRUE"
    )
        port map (
      I => mem_dq_out(31),
      IBUFDISABLE => idle,
      INTERMDISABLE => idle,
      IO => ddr3_dq(53),
      O => mem_dq_in(27),
      T => mem_dq_ts(31)
    );
\gen_dq_iobuf_HR.gen_dq_iobuf[54].u_iobuf_dq\: unisim.vcomponents.IOBUF_INTERMDISABLE
    generic map(
      IOSTANDARD => "DEFAULT",
      SIM_DEVICE => "7SERIES",
      USE_IBUFDISABLE => "TRUE"
    )
        port map (
      I => mem_dq_out(32),
      IBUFDISABLE => idle,
      INTERMDISABLE => idle,
      IO => ddr3_dq(54),
      O => mem_dq_in(28),
      T => mem_dq_ts(32)
    );
\gen_dq_iobuf_HR.gen_dq_iobuf[55].u_iobuf_dq\: unisim.vcomponents.IOBUF_INTERMDISABLE
    generic map(
      IOSTANDARD => "DEFAULT",
      SIM_DEVICE => "7SERIES",
      USE_IBUFDISABLE => "TRUE"
    )
        port map (
      I => mem_dq_out(33),
      IBUFDISABLE => idle,
      INTERMDISABLE => idle,
      IO => ddr3_dq(55),
      O => mem_dq_in(29),
      T => mem_dq_ts(33)
    );
\gen_dq_iobuf_HR.gen_dq_iobuf[56].u_iobuf_dq\: unisim.vcomponents.IOBUF_INTERMDISABLE
    generic map(
      IOSTANDARD => "DEFAULT",
      SIM_DEVICE => "7SERIES",
      USE_IBUFDISABLE => "TRUE"
    )
        port map (
      I => mem_dq_out(38),
      IBUFDISABLE => idle,
      INTERMDISABLE => idle,
      IO => ddr3_dq(56),
      O => mem_dq_in(32),
      T => mem_dq_ts(38)
    );
\gen_dq_iobuf_HR.gen_dq_iobuf[57].u_iobuf_dq\: unisim.vcomponents.IOBUF_INTERMDISABLE
    generic map(
      IOSTANDARD => "DEFAULT",
      SIM_DEVICE => "7SERIES",
      USE_IBUFDISABLE => "TRUE"
    )
        port map (
      I => mem_dq_out(39),
      IBUFDISABLE => idle,
      INTERMDISABLE => idle,
      IO => ddr3_dq(57),
      O => mem_dq_in(33),
      T => mem_dq_ts(39)
    );
\gen_dq_iobuf_HR.gen_dq_iobuf[58].u_iobuf_dq\: unisim.vcomponents.IOBUF_INTERMDISABLE
    generic map(
      IOSTANDARD => "DEFAULT",
      SIM_DEVICE => "7SERIES",
      USE_IBUFDISABLE => "TRUE"
    )
        port map (
      I => mem_dq_out(40),
      IBUFDISABLE => idle,
      INTERMDISABLE => idle,
      IO => ddr3_dq(58),
      O => mem_dq_in(34),
      T => mem_dq_ts(40)
    );
\gen_dq_iobuf_HR.gen_dq_iobuf[59].u_iobuf_dq\: unisim.vcomponents.IOBUF_INTERMDISABLE
    generic map(
      IOSTANDARD => "DEFAULT",
      SIM_DEVICE => "7SERIES",
      USE_IBUFDISABLE => "TRUE"
    )
        port map (
      I => mem_dq_out(41),
      IBUFDISABLE => idle,
      INTERMDISABLE => idle,
      IO => ddr3_dq(59),
      O => mem_dq_in(35),
      T => mem_dq_ts(41)
    );
\gen_dq_iobuf_HR.gen_dq_iobuf[5].u_iobuf_dq\: unisim.vcomponents.IOBUF_INTERMDISABLE
    generic map(
      IOSTANDARD => "DEFAULT",
      SIM_DEVICE => "7SERIES",
      USE_IBUFDISABLE => "TRUE"
    )
        port map (
      I => mem_dq_out(102),
      IBUFDISABLE => idle,
      INTERMDISABLE => idle,
      IO => ddr3_dq(5),
      O => mem_dq_in(86),
      T => mem_dq_ts(102)
    );
\gen_dq_iobuf_HR.gen_dq_iobuf[60].u_iobuf_dq\: unisim.vcomponents.IOBUF_INTERMDISABLE
    generic map(
      IOSTANDARD => "DEFAULT",
      SIM_DEVICE => "7SERIES",
      USE_IBUFDISABLE => "TRUE"
    )
        port map (
      I => mem_dq_out(42),
      IBUFDISABLE => idle,
      INTERMDISABLE => idle,
      IO => ddr3_dq(60),
      O => mem_dq_in(36),
      T => mem_dq_ts(42)
    );
\gen_dq_iobuf_HR.gen_dq_iobuf[61].u_iobuf_dq\: unisim.vcomponents.IOBUF_INTERMDISABLE
    generic map(
      IOSTANDARD => "DEFAULT",
      SIM_DEVICE => "7SERIES",
      USE_IBUFDISABLE => "TRUE"
    )
        port map (
      I => mem_dq_out(43),
      IBUFDISABLE => idle,
      INTERMDISABLE => idle,
      IO => ddr3_dq(61),
      O => mem_dq_in(37),
      T => mem_dq_ts(43)
    );
\gen_dq_iobuf_HR.gen_dq_iobuf[62].u_iobuf_dq\: unisim.vcomponents.IOBUF_INTERMDISABLE
    generic map(
      IOSTANDARD => "DEFAULT",
      SIM_DEVICE => "7SERIES",
      USE_IBUFDISABLE => "TRUE"
    )
        port map (
      I => mem_dq_out(44),
      IBUFDISABLE => idle,
      INTERMDISABLE => idle,
      IO => ddr3_dq(62),
      O => mem_dq_in(38),
      T => mem_dq_ts(44)
    );
\gen_dq_iobuf_HR.gen_dq_iobuf[63].u_iobuf_dq\: unisim.vcomponents.IOBUF_INTERMDISABLE
    generic map(
      IOSTANDARD => "DEFAULT",
      SIM_DEVICE => "7SERIES",
      USE_IBUFDISABLE => "TRUE"
    )
        port map (
      I => mem_dq_out(45),
      IBUFDISABLE => idle,
      INTERMDISABLE => idle,
      IO => ddr3_dq(63),
      O => mem_dq_in(39),
      T => mem_dq_ts(45)
    );
\gen_dq_iobuf_HR.gen_dq_iobuf[6].u_iobuf_dq\: unisim.vcomponents.IOBUF_INTERMDISABLE
    generic map(
      IOSTANDARD => "DEFAULT",
      SIM_DEVICE => "7SERIES",
      USE_IBUFDISABLE => "TRUE"
    )
        port map (
      I => mem_dq_out(103),
      IBUFDISABLE => idle,
      INTERMDISABLE => idle,
      IO => ddr3_dq(6),
      O => mem_dq_in(87),
      T => mem_dq_ts(103)
    );
\gen_dq_iobuf_HR.gen_dq_iobuf[7].u_iobuf_dq\: unisim.vcomponents.IOBUF_INTERMDISABLE
    generic map(
      IOSTANDARD => "DEFAULT",
      SIM_DEVICE => "7SERIES",
      USE_IBUFDISABLE => "TRUE"
    )
        port map (
      I => mem_dq_out(105),
      IBUFDISABLE => idle,
      INTERMDISABLE => idle,
      IO => ddr3_dq(7),
      O => mem_dq_in(89),
      T => mem_dq_ts(105)
    );
\gen_dq_iobuf_HR.gen_dq_iobuf[8].u_iobuf_dq\: unisim.vcomponents.IOBUF_INTERMDISABLE
    generic map(
      IOSTANDARD => "DEFAULT",
      SIM_DEVICE => "7SERIES",
      USE_IBUFDISABLE => "TRUE"
    )
        port map (
      I => mem_dq_out(110),
      IBUFDISABLE => idle,
      INTERMDISABLE => idle,
      IO => ddr3_dq(8),
      O => mem_dq_in(92),
      T => mem_dq_ts(110)
    );
\gen_dq_iobuf_HR.gen_dq_iobuf[9].u_iobuf_dq\: unisim.vcomponents.IOBUF_INTERMDISABLE
    generic map(
      IOSTANDARD => "DEFAULT",
      SIM_DEVICE => "7SERIES",
      USE_IBUFDISABLE => "TRUE"
    )
        port map (
      I => mem_dq_out(111),
      IBUFDISABLE => idle,
      INTERMDISABLE => idle,
      IO => ddr3_dq(9),
      O => mem_dq_in(93),
      T => mem_dq_ts(111)
    );
\gen_dqs_iobuf_HR.gen_dqs_iobuf[0].gen_dqs_diff.u_iddr_edge_det\: entity work.mig_mig_7series_v4_2_poc_pd
     port map (
      in_dqs_lpbk_to_iddr_0 => in_dqs_lpbk_to_iddr_0,
      mmcm_ps_clk => mmcm_ps_clk,
      rst_sync_r1 => rst_sync_r1
    );
\gen_dqs_iobuf_HR.gen_dqs_iobuf[0].gen_dqs_diff.u_iobuf_dqs\: unisim.vcomponents.IOBUFDS_DIFF_OUT_INTERMDISABLE
    generic map(
      DQS_BIAS => "TRUE",
      IOSTANDARD => "DEFAULT",
      SIM_DEVICE => "7SERIES",
      USE_IBUFDISABLE => "FALSE"
    )
        port map (
      I => out_dqs_0,
      IBUFDISABLE => '0',
      INTERMDISABLE => idle,
      IO => ddr3_dqs_p(0),
      IOB => ddr3_dqs_n(0),
      O => mem_dqs_in(8),
      OB => in_dqs_lpbk_to_iddr_0,
      TM => ts_dqs_0,
      TS => ts_dqs_0
    );
\gen_dqs_iobuf_HR.gen_dqs_iobuf[1].gen_dqs_diff.u_iddr_edge_det\: entity work.mig_mig_7series_v4_2_poc_pd_5
     port map (
      in_dqs_lpbk_to_iddr_1 => in_dqs_lpbk_to_iddr_1,
      mmcm_ps_clk => mmcm_ps_clk,
      rst_sync_r1 => rst_sync_r1
    );
\gen_dqs_iobuf_HR.gen_dqs_iobuf[1].gen_dqs_diff.u_iobuf_dqs\: unisim.vcomponents.IOBUFDS_DIFF_OUT_INTERMDISABLE
    generic map(
      DQS_BIAS => "TRUE",
      IOSTANDARD => "DEFAULT",
      SIM_DEVICE => "7SERIES",
      USE_IBUFDISABLE => "FALSE"
    )
        port map (
      I => out_dqs_1,
      IBUFDISABLE => '0',
      INTERMDISABLE => idle,
      IO => ddr3_dqs_p(1),
      IOB => ddr3_dqs_n(1),
      O => mem_dqs_in(9),
      OB => in_dqs_lpbk_to_iddr_1,
      TM => ts_dqs_1,
      TS => ts_dqs_1
    );
\gen_dqs_iobuf_HR.gen_dqs_iobuf[2].gen_dqs_diff.u_iddr_edge_det\: entity work.mig_mig_7series_v4_2_poc_pd_6
     port map (
      in_dqs_lpbk_to_iddr_2 => in_dqs_lpbk_to_iddr_2,
      mmcm_ps_clk => mmcm_ps_clk,
      rst_sync_r1 => rst_sync_r1
    );
\gen_dqs_iobuf_HR.gen_dqs_iobuf[2].gen_dqs_diff.u_iobuf_dqs\: unisim.vcomponents.IOBUFDS_DIFF_OUT_INTERMDISABLE
    generic map(
      DQS_BIAS => "TRUE",
      IOSTANDARD => "DEFAULT",
      SIM_DEVICE => "7SERIES",
      USE_IBUFDISABLE => "FALSE"
    )
        port map (
      I => out_dqs_2,
      IBUFDISABLE => '0',
      INTERMDISABLE => idle,
      IO => ddr3_dqs_p(2),
      IOB => ddr3_dqs_n(2),
      O => mem_dqs_in(10),
      OB => in_dqs_lpbk_to_iddr_2,
      TM => ts_dqs_2,
      TS => ts_dqs_2
    );
\gen_dqs_iobuf_HR.gen_dqs_iobuf[3].gen_dqs_diff.u_iddr_edge_det\: entity work.mig_mig_7series_v4_2_poc_pd_7
     port map (
      in_dqs_lpbk_to_iddr_3 => in_dqs_lpbk_to_iddr_3,
      mmcm_ps_clk => mmcm_ps_clk,
      rst_sync_r1 => rst_sync_r1
    );
\gen_dqs_iobuf_HR.gen_dqs_iobuf[3].gen_dqs_diff.u_iobuf_dqs\: unisim.vcomponents.IOBUFDS_DIFF_OUT_INTERMDISABLE
    generic map(
      DQS_BIAS => "TRUE",
      IOSTANDARD => "DEFAULT",
      SIM_DEVICE => "7SERIES",
      USE_IBUFDISABLE => "FALSE"
    )
        port map (
      I => out_dqs_3,
      IBUFDISABLE => '0',
      INTERMDISABLE => idle,
      IO => ddr3_dqs_p(3),
      IOB => ddr3_dqs_n(3),
      O => mem_dqs_in(11),
      OB => in_dqs_lpbk_to_iddr_3,
      TM => ts_dqs_3,
      TS => ts_dqs_3
    );
\gen_dqs_iobuf_HR.gen_dqs_iobuf[4].gen_dqs_diff.u_iddr_edge_det\: entity work.mig_mig_7series_v4_2_poc_pd_8
     port map (
      in_dqs_lpbk_to_iddr_4 => in_dqs_lpbk_to_iddr_4,
      mmcm_ps_clk => mmcm_ps_clk,
      rst_sync_r1 => rst_sync_r1
    );
\gen_dqs_iobuf_HR.gen_dqs_iobuf[4].gen_dqs_diff.u_iobuf_dqs\: unisim.vcomponents.IOBUFDS_DIFF_OUT_INTERMDISABLE
    generic map(
      DQS_BIAS => "TRUE",
      IOSTANDARD => "DEFAULT",
      SIM_DEVICE => "7SERIES",
      USE_IBUFDISABLE => "FALSE"
    )
        port map (
      I => out_dqs_4,
      IBUFDISABLE => '0',
      INTERMDISABLE => idle,
      IO => ddr3_dqs_p(4),
      IOB => ddr3_dqs_n(4),
      O => mem_dqs_in(0),
      OB => in_dqs_lpbk_to_iddr_4,
      TM => ts_dqs_4,
      TS => ts_dqs_4
    );
\gen_dqs_iobuf_HR.gen_dqs_iobuf[5].gen_dqs_diff.u_iddr_edge_det\: entity work.mig_mig_7series_v4_2_poc_pd_9
     port map (
      in_dqs_lpbk_to_iddr_5 => in_dqs_lpbk_to_iddr_5,
      mmcm_ps_clk => mmcm_ps_clk,
      rst_sync_r1 => rst_sync_r1
    );
\gen_dqs_iobuf_HR.gen_dqs_iobuf[5].gen_dqs_diff.u_iobuf_dqs\: unisim.vcomponents.IOBUFDS_DIFF_OUT_INTERMDISABLE
    generic map(
      DQS_BIAS => "TRUE",
      IOSTANDARD => "DEFAULT",
      SIM_DEVICE => "7SERIES",
      USE_IBUFDISABLE => "FALSE"
    )
        port map (
      I => out_dqs_5,
      IBUFDISABLE => '0',
      INTERMDISABLE => idle,
      IO => ddr3_dqs_p(5),
      IOB => ddr3_dqs_n(5),
      O => mem_dqs_in(1),
      OB => in_dqs_lpbk_to_iddr_5,
      TM => ts_dqs_5,
      TS => ts_dqs_5
    );
\gen_dqs_iobuf_HR.gen_dqs_iobuf[6].gen_dqs_diff.u_iddr_edge_det\: entity work.mig_mig_7series_v4_2_poc_pd_10
     port map (
      in_dqs_lpbk_to_iddr_6 => in_dqs_lpbk_to_iddr_6,
      mmcm_ps_clk => mmcm_ps_clk,
      rst_sync_r1 => rst_sync_r1
    );
\gen_dqs_iobuf_HR.gen_dqs_iobuf[6].gen_dqs_diff.u_iobuf_dqs\: unisim.vcomponents.IOBUFDS_DIFF_OUT_INTERMDISABLE
    generic map(
      DQS_BIAS => "TRUE",
      IOSTANDARD => "DEFAULT",
      SIM_DEVICE => "7SERIES",
      USE_IBUFDISABLE => "FALSE"
    )
        port map (
      I => out_dqs_6,
      IBUFDISABLE => '0',
      INTERMDISABLE => idle,
      IO => ddr3_dqs_p(6),
      IOB => ddr3_dqs_n(6),
      O => mem_dqs_in(2),
      OB => in_dqs_lpbk_to_iddr_6,
      TM => ts_dqs_6,
      TS => ts_dqs_6
    );
\gen_dqs_iobuf_HR.gen_dqs_iobuf[7].gen_dqs_diff.u_iddr_edge_det\: entity work.mig_mig_7series_v4_2_poc_pd_11
     port map (
      in_dqs_lpbk_to_iddr_7 => in_dqs_lpbk_to_iddr_7,
      mmcm_ps_clk => mmcm_ps_clk,
      rst_sync_r1 => rst_sync_r1
    );
\gen_dqs_iobuf_HR.gen_dqs_iobuf[7].gen_dqs_diff.u_iobuf_dqs\: unisim.vcomponents.IOBUFDS_DIFF_OUT_INTERMDISABLE
    generic map(
      DQS_BIAS => "TRUE",
      IOSTANDARD => "DEFAULT",
      SIM_DEVICE => "7SERIES",
      USE_IBUFDISABLE => "FALSE"
    )
        port map (
      I => out_dqs_7,
      IBUFDISABLE => '0',
      INTERMDISABLE => idle,
      IO => ddr3_dqs_p(7),
      IOB => ddr3_dqs_n(7),
      O => mem_dqs_in(3),
      OB => in_dqs_lpbk_to_iddr_7,
      TM => ts_dqs_7,
      TS => ts_dqs_7
    );
\gen_reset_obuf.u_reset_obuf\: unisim.vcomponents.OBUF
    generic map(
      IOSTANDARD => "DEFAULT"
    )
        port map (
      I => mux_reset_n,
      O => ddr3_reset_n
    );
\genblk24.phy_ctl_pre_fifo_0\: entity work.mig_mig_7series_v4_2_ddr_of_pre_fifo
     port map (
      SR(0) => SR(0),
      \rd_ptr_timing_reg[0]_0\ => \entry_cnt_reg[4]\
    );
\genblk24.phy_ctl_pre_fifo_1\: entity work.\mig_mig_7series_v4_2_ddr_of_pre_fifo__parameterized0\
     port map (
      SR(0) => SR(0),
      \rd_ptr_timing_reg[0]_0\ => \entry_cnt_reg[4]\
    );
\genblk24.phy_ctl_pre_fifo_2\: entity work.\mig_mig_7series_v4_2_ddr_of_pre_fifo__parameterized0_12\
     port map (
      SR(0) => SR(0),
      \rd_ptr_timing_reg[0]_0\ => \entry_cnt_reg[4]\
    );
\phy_ctl_wd_i1_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => D(0),
      Q => phy_ctl_wd_i1(0),
      R => '0'
    );
\phy_ctl_wd_i1_reg[17]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => D(3),
      Q => phy_ctl_wd_i1(17),
      R => '0'
    );
\phy_ctl_wd_i1_reg[18]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => D(4),
      Q => phy_ctl_wd_i1(18),
      R => '0'
    );
\phy_ctl_wd_i1_reg[19]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => D(5),
      Q => phy_ctl_wd_i1(19),
      R => '0'
    );
\phy_ctl_wd_i1_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => D(1),
      Q => phy_ctl_wd_i1(1),
      R => '0'
    );
\phy_ctl_wd_i1_reg[20]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => D(6),
      Q => phy_ctl_wd_i1(20),
      R => '0'
    );
\phy_ctl_wd_i1_reg[21]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => D(7),
      Q => phy_ctl_wd_i1(21),
      R => '0'
    );
\phy_ctl_wd_i1_reg[22]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => D(8),
      Q => phy_ctl_wd_i1(22),
      R => '0'
    );
\phy_ctl_wd_i1_reg[23]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => D(9),
      Q => phy_ctl_wd_i1(23),
      R => '0'
    );
\phy_ctl_wd_i1_reg[24]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => D(10),
      Q => phy_ctl_wd_i1(24),
      R => '0'
    );
\phy_ctl_wd_i1_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => D(2),
      Q => phy_ctl_wd_i1(2),
      R => '0'
    );
\phy_ctl_wd_i2_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => phy_ctl_wd_i1(0),
      Q => phy_ctl_wd_i2(0),
      R => '0'
    );
\phy_ctl_wd_i2_reg[17]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => phy_ctl_wd_i1(17),
      Q => phy_ctl_wd_i2(17),
      R => '0'
    );
\phy_ctl_wd_i2_reg[18]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => phy_ctl_wd_i1(18),
      Q => phy_ctl_wd_i2(18),
      R => '0'
    );
\phy_ctl_wd_i2_reg[19]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => phy_ctl_wd_i1(19),
      Q => phy_ctl_wd_i2(19),
      R => '0'
    );
\phy_ctl_wd_i2_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => phy_ctl_wd_i1(1),
      Q => phy_ctl_wd_i2(1),
      R => '0'
    );
\phy_ctl_wd_i2_reg[20]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => phy_ctl_wd_i1(20),
      Q => phy_ctl_wd_i2(20),
      R => '0'
    );
\phy_ctl_wd_i2_reg[21]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => phy_ctl_wd_i1(21),
      Q => phy_ctl_wd_i2(21),
      R => '0'
    );
\phy_ctl_wd_i2_reg[22]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => phy_ctl_wd_i1(22),
      Q => phy_ctl_wd_i2(22),
      R => '0'
    );
\phy_ctl_wd_i2_reg[23]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => phy_ctl_wd_i1(23),
      Q => phy_ctl_wd_i2(23),
      R => '0'
    );
\phy_ctl_wd_i2_reg[24]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => phy_ctl_wd_i1(24),
      Q => phy_ctl_wd_i2(24),
      R => '0'
    );
\phy_ctl_wd_i2_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => phy_ctl_wd_i1(2),
      Q => phy_ctl_wd_i2(2),
      R => '0'
    );
phy_ctl_wr_i1_reg: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => phy_cmd_wr_en,
      Q => phy_ctl_wr_i1,
      R => '0'
    );
phy_ctl_wr_i2_reg: unisim.vcomponents.FDRE
     port map (
      C => \entry_cnt_reg[4]\,
      CE => '1',
      D => phy_ctl_wr_i1,
      Q => phy_ctl_wr_i2,
      R => '0'
    );
u_cas_n_obuf: unisim.vcomponents.OBUF
    generic map(
      IOSTANDARD => "DEFAULT"
    )
        port map (
      I => mem_dq_out(65),
      O => ddr3_cas_n
    );
u_ddr_mc_phy: entity work.mig_mig_7series_v4_2_ddr_mc_phy
     port map (
      A_rst_primitives_reg => A_rst_primitives_reg,
      A_rst_primitives_reg_0 => A_rst_primitives_reg_0,
      A_rst_primitives_reg_1 => A_rst_primitives_reg_1,
      A_rst_primitives_reg_2 => A_rst_primitives_reg_2,
      A_rst_primitives_reg_3 => A_rst_primitives_reg_3,
      A_rst_primitives_reg_4 => A_rst_primitives_reg_4,
      A_rst_primitives_reg_5 => A_rst_primitives_reg_5,
      A_rst_primitives_reg_6 => A_rst_primitives_reg_6,
      A_rst_primitives_reg_7 => A_rst_primitives_reg_7,
      CLKB0 => CLKB0,
      CLKB0_10 => CLKB0_10,
      CLKB0_11 => CLKB0_11,
      CLKB0_12 => CLKB0_12,
      CLKB0_13 => CLKB0_13,
      CLKB0_7 => CLKB0_7,
      CLKB0_8 => CLKB0_8,
      CLKB0_9 => CLKB0_9,
      COUNTERLOADVAL(5 downto 0) => COUNTERLOADVAL(5 downto 0),
      C_po_coarse_enable26_out => C_po_coarse_enable26_out,
      C_po_counter_read_en38_out => C_po_counter_read_en38_out,
      C_po_fine_enable23_out => C_po_fine_enable23_out,
      C_po_fine_inc29_out => C_po_fine_inc29_out,
      D1(3 downto 0) => D1(3 downto 0),
      D2(7 downto 0) => D2(7 downto 0),
      D3(3 downto 0) => D3(3 downto 0),
      D4(3 downto 0) => D4(3 downto 0),
      D5(3 downto 0) => D5(3 downto 0),
      D6(7 downto 0) => D6(7 downto 0),
      D7(3 downto 0) => D7(3 downto 0),
      D8(3 downto 0) => D8(3 downto 0),
      D9(3 downto 0) => D9(3 downto 0),
      LD0 => LD0,
      LD0_10 => LD0_10,
      LD0_11 => LD0_11,
      LD0_12 => LD0_12,
      LD0_13 => LD0_13,
      LD0_7 => LD0_7,
      LD0_8 => LD0_8,
      LD0_9 => LD0_9,
      Q(10 downto 3) => phy_ctl_wd_i2(24 downto 17),
      Q(2 downto 0) => phy_ctl_wd_i2(2 downto 0),
      RST0 => RST0,
      SR(0) => SR(0),
      calib_sel(3 downto 0) => calib_sel(3 downto 0),
      d_in(4 downto 0) => d_in(4 downto 0),
      ddr_ck_out(1 downto 0) => ddr_ck_out(1 downto 0),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_2\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_3\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_4\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_5\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_5\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_6\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_6\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_2\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_3\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_4\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_5\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_5\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_6\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_6\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_2\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_3\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_4\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_5\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_5\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_6\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_6\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_2\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_3\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_4\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_5\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_5\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_6\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_6\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_2\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_3\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_4\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_5\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_5\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_6\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_6\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_2\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_3\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_4\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_5\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_5\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_6\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_6\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_2\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_3\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_4\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_5\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_5\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_6\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_6\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_2\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_3\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_4\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_5\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_5\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_6\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_6\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_2\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_3\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_4\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_5\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_5\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_6\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_6\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_2\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_3\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_4\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_5\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_5\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_6\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_6\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_2\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_3\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_4\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_5\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_5\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_6\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_6\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_2\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_3\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_4\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_5\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_5\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_6\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_6\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_2\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_3\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_4\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_5\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_5\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_6\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_6\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_2\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_3\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_4\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_5\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_5\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_6\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_6\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_2\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_3\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_4\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_5\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_5\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_6\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_6\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_2\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_3\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_4\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_5\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_5\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_6\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_6\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_2\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_3\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_4\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_5\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_5\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_6\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_6\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_2\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_3\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_4\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_5\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_5\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_6\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_6\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_2\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_3\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_4\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_5\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_5\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_6\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_6\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_2\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_3\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_4\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_5\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_5\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_6\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_6\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_2\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_3\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_4\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_5\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_5\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_6\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_6\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_2\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_3\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_4\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_5\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_5\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_6\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_6\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_2\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_3\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_4\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_5\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_5\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_6\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_6\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_2\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_3\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_4\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_5\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_5\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_6\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_6\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_2\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_3\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_4\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_5\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_5\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_6\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_6\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_2\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_3\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_4\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_5\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_5\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_6\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_6\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_2\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_3\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_4\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_5\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_5\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_6\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_6\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_2\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_3\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_4\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_5\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_5\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_6\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_6\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_2\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_3\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_4\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_5\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_5\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_6\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_6\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_2\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_3\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_4\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_5\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_5\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_6\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_6\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_2\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_3\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_4\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_5\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_5\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_6\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_6\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_2\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_3\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_4\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_5\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_5\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_6\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_6\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_2\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_3\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_4\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_5\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_5\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_6\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_6\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_2\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_3\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_4\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_5\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_5\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_6\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_6\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_2\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_3\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_4\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_5\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_5\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_6\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_6\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_2\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_3\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_4\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_5\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_5\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_6\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_6\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_2\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_3\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_4\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_5\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_5\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_6\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_6\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_2\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_3\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_4\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_5\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_5\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_6\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_6\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_2\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_3\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_4\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_5\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_5\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_6\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_6\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_2\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_3\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_4\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_5\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_5\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_6\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_6\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_2\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_3\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_4\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_5\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_5\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_6\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_6\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_2\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_3\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_4\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_5\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_5\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_6\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_6\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_2\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_3\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_4\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_5\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_5\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_6\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_6\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_2\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_3\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_4\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_5\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_5\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_6\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_6\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_2\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_3\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_4\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_5\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_5\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_6\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_6\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_2\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_3\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_4\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_5\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_5\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_6\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_6\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_2\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_3\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_4\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_5\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_5\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_6\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_6\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_2\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_3\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_4\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_5\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_5\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_6\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_6\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_2\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_3\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_4\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_2\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_3\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_4\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_2\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_3\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_4\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_2\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_3\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_4\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_2\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_3\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_4\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_2\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_3\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_4\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_2\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_3\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_4\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_2\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_3\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_4\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_2\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_3\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_4\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_5\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_5\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_6\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_6\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_2\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_3\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_4\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_5\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_5\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_6\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_6\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_2\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_3\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_4\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_5\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_5\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_6\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_6\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_2\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_3\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_4\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_5\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_5\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_6\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_6\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_2\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_3\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_4\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_5\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_5\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_6\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_6\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_2\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_3\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_4\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_5\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_5\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_6\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_6\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_2\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_3\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_4\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_5\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_5\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_6\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_6\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_2\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_3\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_4\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_5\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_5\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_6\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_6\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_0\,
      \entry_cnt_reg[4]\ => \entry_cnt_reg[4]\,
      freq_refclk => freq_refclk,
      \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]\(2 downto 0) => \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]\(2 downto 0),
      \gen_mux_rd[0].mux_rd_rise0_r_reg[0]\(1 downto 0) => \gen_mux_rd[0].mux_rd_rise0_r_reg[0]\(1 downto 0),
      \gen_mux_rd[1].mux_rd_rise0_r_reg[1]\ => \gen_mux_rd[1].mux_rd_rise0_r_reg[1]\,
      \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]\(2 downto 0) => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]\(2 downto 0),
      idelay_inc => idelay_inc,
      idelay_ld_rst => idelay_ld_rst,
      idelay_ld_rst_0 => idelay_ld_rst_0,
      idelay_ld_rst_1 => idelay_ld_rst_1,
      idelay_ld_rst_2 => idelay_ld_rst_2,
      idelay_ld_rst_3 => idelay_ld_rst_3,
      idelay_ld_rst_4 => idelay_ld_rst_4,
      idelay_ld_rst_5 => idelay_ld_rst_5,
      idelay_ld_rst_6 => idelay_ld_rst_6,
      if_empty => if_empty,
      ififo_rst_reg => ififo_rst_reg,
      ififo_rst_reg_0 => ififo_rst_reg_0,
      ififo_rst_reg_1 => ififo_rst_reg_1,
      ififo_rst_reg_2 => ififo_rst_reg_2,
      ififo_rst_reg_3 => ififo_rst_reg_3,
      ififo_rst_reg_4 => ififo_rst_reg_4,
      ififo_rst_reg_5 => ififo_rst_reg_5,
      ififo_rst_reg_6 => ififo_rst_reg_6,
      in0(7 downto 0) => in0(7 downto 0),
      \input_[9].iserdes_dq_.iserdesdq\ => \input_[9].iserdes_dq_.iserdesdq\,
      \input_[9].iserdes_dq_.iserdesdq_0\ => \input_[9].iserdes_dq_.iserdesdq_0\,
      \input_[9].iserdes_dq_.iserdesdq_1\ => \input_[9].iserdes_dq_.iserdesdq_1\,
      \input_[9].iserdes_dq_.iserdesdq_2\ => \input_[9].iserdes_dq_.iserdesdq_2\,
      \input_[9].iserdes_dq_.iserdesdq_3\ => \input_[9].iserdes_dq_.iserdesdq_3\,
      \input_[9].iserdes_dq_.iserdesdq_4\ => \input_[9].iserdes_dq_.iserdesdq_4\,
      \input_[9].iserdes_dq_.iserdesdq_5\ => \input_[9].iserdes_dq_.iserdesdq_5\,
      \input_[9].iserdes_dq_.iserdesdq_6\ => \input_[9].iserdes_dq_.iserdesdq_6\,
      iodelay_ctrl_rdy(0) => iodelay_ctrl_rdy(0),
      \mcGo_r_reg[15]_0\(0) => \mcGo_r_reg[15]\(0),
      mc_address(3 downto 0) => mc_address(3 downto 0),
      mc_cas_n(2 downto 0) => mc_cas_n(2 downto 0),
      mc_cs_n(0) => mc_cs_n(0),
      mc_ras_n(1 downto 0) => mc_ras_n(1 downto 0),
      mc_we_n(1 downto 0) => mc_we_n(1 downto 0),
      mem_dq_in(63 downto 56) => mem_dq_in(119 downto 112),
      mem_dq_in(55 downto 48) => mem_dq_in(109 downto 102),
      mem_dq_in(47 downto 40) => mem_dq_in(99 downto 92),
      mem_dq_in(39) => mem_dq_in(89),
      mem_dq_in(38 downto 32) => mem_dq_in(87 downto 81),
      mem_dq_in(31 downto 24) => mem_dq_in(39 downto 32),
      mem_dq_in(23 downto 16) => mem_dq_in(29 downto 22),
      mem_dq_in(15 downto 8) => mem_dq_in(19 downto 12),
      mem_dq_in(7) => mem_dq_in(9),
      mem_dq_in(6 downto 0) => mem_dq_in(7 downto 1),
      mem_dq_out(94 downto 86) => mem_dq_out(141 downto 133),
      mem_dq_out(85 downto 77) => mem_dq_out(129 downto 121),
      mem_dq_out(76 downto 68) => mem_dq_out(117 downto 109),
      mem_dq_out(67) => mem_dq_out(105),
      mem_dq_out(66 downto 48) => mem_dq_out(103 downto 85),
      mem_dq_out(47 downto 44) => mem_dq_out(83 downto 80),
      mem_dq_out(43 downto 42) => mem_dq_out(77 downto 76),
      mem_dq_out(41 downto 40) => mem_dq_out(71 downto 70),
      mem_dq_out(39) => mem_dq_out(67),
      mem_dq_out(38 downto 37) => mem_dq_out(65 downto 64),
      mem_dq_out(36) => mem_dq_out(62),
      mem_dq_out(35 downto 27) => mem_dq_out(45 downto 37),
      mem_dq_out(26 downto 18) => mem_dq_out(33 downto 25),
      mem_dq_out(17 downto 9) => mem_dq_out(21 downto 13),
      mem_dq_out(8) => mem_dq_out(9),
      mem_dq_out(7 downto 0) => mem_dq_out(7 downto 0),
      mem_dq_ts(71 downto 63) => mem_dq_ts(141 downto 133),
      mem_dq_ts(62 downto 54) => mem_dq_ts(129 downto 121),
      mem_dq_ts(53 downto 45) => mem_dq_ts(117 downto 109),
      mem_dq_ts(44) => mem_dq_ts(105),
      mem_dq_ts(43 downto 36) => mem_dq_ts(103 downto 96),
      mem_dq_ts(35 downto 27) => mem_dq_ts(45 downto 37),
      mem_dq_ts(26 downto 18) => mem_dq_ts(33 downto 25),
      mem_dq_ts(17 downto 9) => mem_dq_ts(21 downto 13),
      mem_dq_ts(8) => mem_dq_ts(9),
      mem_dq_ts(7 downto 0) => mem_dq_ts(7 downto 0),
      mem_dqs_in(7 downto 4) => mem_dqs_in(11 downto 8),
      mem_dqs_in(3 downto 0) => mem_dqs_in(3 downto 0),
      mem_out(11 downto 0) => mem_out(11 downto 0),
      mem_refclk => mem_refclk,
      mux_address(48 downto 0) => mux_address(48 downto 0),
      \my_empty_reg[1]\ => \my_empty_reg[1]\,
      \my_empty_reg[1]_0\ => \my_empty_reg[1]_0\,
      \my_empty_reg[1]_1\ => \my_empty_reg[1]_1\,
      \my_empty_reg[1]_2\ => \my_empty_reg[1]_2\,
      \my_empty_reg[1]_3\ => \my_empty_reg[1]_3\,
      \my_empty_reg[1]_4\ => \my_empty_reg[1]_4\,
      \my_empty_reg[1]_5\ => \my_empty_reg[1]_5\,
      \my_empty_reg[1]_6\ => \my_empty_reg[1]_6\,
      \my_empty_reg[1]_7\ => \my_empty_reg[1]_7\,
      \my_empty_reg[1]_8\ => \my_empty_reg[1]_8\,
      \my_empty_reg[1]_9\ => \my_empty_reg[1]_9\,
      \my_empty_reg[7]\(7 downto 0) => \my_empty_reg[7]\(7 downto 0),
      \my_empty_reg[7]_0\(7 downto 0) => \my_empty_reg[7]_0\(7 downto 0),
      \my_empty_reg[7]_1\(7 downto 0) => \my_empty_reg[7]_1\(7 downto 0),
      \my_empty_reg[7]_10\(7 downto 0) => \my_empty_reg[7]_10\(7 downto 0),
      \my_empty_reg[7]_11\(7 downto 0) => \my_empty_reg[7]_11\(7 downto 0),
      \my_empty_reg[7]_12\(7 downto 0) => \my_empty_reg[7]_12\(7 downto 0),
      \my_empty_reg[7]_13\(7 downto 0) => \my_empty_reg[7]_13\(7 downto 0),
      \my_empty_reg[7]_14\(7 downto 0) => \my_empty_reg[7]_14\(7 downto 0),
      \my_empty_reg[7]_15\(7 downto 0) => \my_empty_reg[7]_15\(7 downto 0),
      \my_empty_reg[7]_16\(7 downto 0) => \my_empty_reg[7]_16\(7 downto 0),
      \my_empty_reg[7]_17\(7 downto 0) => \my_empty_reg[7]_17\(7 downto 0),
      \my_empty_reg[7]_18\(7 downto 0) => \my_empty_reg[7]_18\(7 downto 0),
      \my_empty_reg[7]_19\(7 downto 0) => \my_empty_reg[7]_19\(7 downto 0),
      \my_empty_reg[7]_2\(7 downto 0) => \my_empty_reg[7]_2\(7 downto 0),
      \my_empty_reg[7]_20\(7 downto 0) => \my_empty_reg[7]_20\(7 downto 0),
      \my_empty_reg[7]_21\(7 downto 0) => \my_empty_reg[7]_21\(7 downto 0),
      \my_empty_reg[7]_22\(7 downto 0) => \my_empty_reg[7]_22\(7 downto 0),
      \my_empty_reg[7]_23\(7 downto 0) => \my_empty_reg[7]_23\(7 downto 0),
      \my_empty_reg[7]_24\(7 downto 0) => \my_empty_reg[7]_24\(7 downto 0),
      \my_empty_reg[7]_25\(7 downto 0) => \my_empty_reg[7]_25\(7 downto 0),
      \my_empty_reg[7]_26\(7 downto 0) => \my_empty_reg[7]_26\(7 downto 0),
      \my_empty_reg[7]_27\(7 downto 0) => \my_empty_reg[7]_27\(7 downto 0),
      \my_empty_reg[7]_28\(7 downto 0) => \my_empty_reg[7]_28\(7 downto 0),
      \my_empty_reg[7]_29\(7 downto 0) => \my_empty_reg[7]_29\(7 downto 0),
      \my_empty_reg[7]_3\(7 downto 0) => \my_empty_reg[7]_3\(7 downto 0),
      \my_empty_reg[7]_30\(7 downto 0) => \my_empty_reg[7]_30\(7 downto 0),
      \my_empty_reg[7]_31\(7 downto 0) => \my_empty_reg[7]_31\(7 downto 0),
      \my_empty_reg[7]_32\(7 downto 0) => \my_empty_reg[7]_32\(7 downto 0),
      \my_empty_reg[7]_33\(7 downto 0) => \my_empty_reg[7]_33\(7 downto 0),
      \my_empty_reg[7]_34\(7 downto 0) => \my_empty_reg[7]_34\(7 downto 0),
      \my_empty_reg[7]_35\(7 downto 0) => \my_empty_reg[7]_35\(7 downto 0),
      \my_empty_reg[7]_36\(7 downto 0) => \my_empty_reg[7]_36\(7 downto 0),
      \my_empty_reg[7]_37\(7 downto 0) => \my_empty_reg[7]_37\(7 downto 0),
      \my_empty_reg[7]_38\(7 downto 0) => \my_empty_reg[7]_38\(7 downto 0),
      \my_empty_reg[7]_39\(7 downto 0) => \my_empty_reg[7]_39\(7 downto 0),
      \my_empty_reg[7]_4\(7 downto 0) => \my_empty_reg[7]_4\(7 downto 0),
      \my_empty_reg[7]_40\(7 downto 0) => \my_empty_reg[7]_40\(7 downto 0),
      \my_empty_reg[7]_41\(7 downto 0) => \my_empty_reg[7]_41\(7 downto 0),
      \my_empty_reg[7]_42\(7 downto 0) => \my_empty_reg[7]_42\(7 downto 0),
      \my_empty_reg[7]_43\(7 downto 0) => \my_empty_reg[7]_43\(7 downto 0),
      \my_empty_reg[7]_44\(7 downto 0) => \my_empty_reg[7]_44\(7 downto 0),
      \my_empty_reg[7]_45\(7 downto 0) => \my_empty_reg[7]_45\(7 downto 0),
      \my_empty_reg[7]_46\(7 downto 0) => \my_empty_reg[7]_46\(7 downto 0),
      \my_empty_reg[7]_47\(7 downto 0) => \my_empty_reg[7]_47\(7 downto 0),
      \my_empty_reg[7]_48\(7 downto 0) => \my_empty_reg[7]_48\(7 downto 0),
      \my_empty_reg[7]_49\(7 downto 0) => \my_empty_reg[7]_49\(7 downto 0),
      \my_empty_reg[7]_5\(7 downto 0) => \my_empty_reg[7]_5\(7 downto 0),
      \my_empty_reg[7]_50\(7 downto 0) => \my_empty_reg[7]_50\(7 downto 0),
      \my_empty_reg[7]_51\(7 downto 0) => \my_empty_reg[7]_51\(7 downto 0),
      \my_empty_reg[7]_52\(7 downto 0) => \my_empty_reg[7]_52\(7 downto 0),
      \my_empty_reg[7]_53\(7 downto 0) => \my_empty_reg[7]_53\(7 downto 0),
      \my_empty_reg[7]_54\(7 downto 0) => \my_empty_reg[7]_54\(7 downto 0),
      \my_empty_reg[7]_55\(7 downto 0) => \my_empty_reg[7]_55\(7 downto 0),
      \my_empty_reg[7]_56\(7 downto 0) => \my_empty_reg[7]_56\(7 downto 0),
      \my_empty_reg[7]_57\(7 downto 0) => \my_empty_reg[7]_57\(7 downto 0),
      \my_empty_reg[7]_58\(7 downto 0) => \my_empty_reg[7]_58\(7 downto 0),
      \my_empty_reg[7]_59\(7 downto 0) => \my_empty_reg[7]_59\(7 downto 0),
      \my_empty_reg[7]_6\(7 downto 0) => \my_empty_reg[7]_6\(7 downto 0),
      \my_empty_reg[7]_60\(7 downto 0) => \my_empty_reg[7]_60\(7 downto 0),
      \my_empty_reg[7]_61\(7 downto 0) => \my_empty_reg[7]_61\(7 downto 0),
      \my_empty_reg[7]_62\(3 downto 0) => \my_empty_reg[7]_62\(3 downto 0),
      \my_empty_reg[7]_63\(7 downto 0) => \my_empty_reg[7]_63\(7 downto 0),
      \my_empty_reg[7]_64\(3 downto 0) => \my_empty_reg[7]_64\(3 downto 0),
      \my_empty_reg[7]_65\(3 downto 0) => \my_empty_reg[7]_65\(3 downto 0),
      \my_empty_reg[7]_7\(7 downto 0) => \my_empty_reg[7]_7\(7 downto 0),
      \my_empty_reg[7]_8\(7 downto 0) => \my_empty_reg[7]_8\(7 downto 0),
      \my_empty_reg[7]_9\(7 downto 0) => \my_empty_reg[7]_9\(7 downto 0),
      \my_full_reg[3]\(3 downto 0) => \my_full_reg[3]\(3 downto 0),
      \my_full_reg[3]_0\(0) => \my_full_reg[3]_0\(0),
      \my_full_reg[3]_1\(1 downto 0) => \my_full_reg[3]_1\(1 downto 0),
      \my_full_reg[3]_2\(0) => \my_full_reg[3]_2\(0),
      \my_full_reg[3]_3\(3 downto 0) => \my_full_reg[3]_3\(3 downto 0),
      of_ctl_full_v(0) => of_ctl_full_v(0),
      \out\ => \out\,
      out_dqs_0 => out_dqs_0,
      out_dqs_1 => out_dqs_1,
      out_dqs_2 => out_dqs_2,
      out_dqs_3 => out_dqs_3,
      out_dqs_4 => out_dqs_4,
      out_dqs_5 => out_dqs_5,
      out_dqs_6 => out_dqs_6,
      out_dqs_7 => out_dqs_7,
      out_fifo => out_fifo,
      out_fifo_0 => out_fifo_0,
      out_fifo_1(63 downto 0) => Q(63 downto 0),
      out_fifo_2 => out_fifo_1,
      out_fifo_3 => out_fifo_2,
      out_fifo_i_39(11 downto 0) => out_fifo_i_39(11 downto 0),
      \out_fifo_i_47__8\(12 downto 0) => \out_fifo_i_47__8\(12 downto 0),
      \out_fifo_i_75__0\(71 downto 0) => \out_fifo_i_75__0\(71 downto 0),
      \out_fifo_i_75__1\(71 downto 0) => \out_fifo_i_75__1\(71 downto 0),
      \out_fifo_i_75__2\(71 downto 0) => \out_fifo_i_75__2\(71 downto 0),
      \out_fifo_i_75__3\(71 downto 0) => \out_fifo_i_75__3\(71 downto 0),
      \out_fifo_i_75__5\(71 downto 0) => \out_fifo_i_75__5\(71 downto 0),
      \out_fifo_i_75__6\(71 downto 0) => \out_fifo_i_75__6\(71 downto 0),
      \out_fifo_i_75__7\(71 downto 0) => \out_fifo_i_75__7\(71 downto 0),
      p_0_out => p_0_out,
      phy_cmd_wr_en => phy_cmd_wr_en,
      phy_ctl_wr_i2 => phy_ctl_wr_i2,
      phy_data_wr_en => phy_data_wr_en,
      phy_dout(71 downto 0) => phy_dout(71 downto 0),
      phy_if_reset => phy_if_reset,
      phy_mc_ctl_full => phy_mc_ctl_full,
      phy_mc_ctl_full_r_reg => phy_mc_ctl_full_r_reg,
      phy_mc_ctl_full_r_reg_0(5 downto 0) => data_offset_1_i2(5 downto 0),
      phy_mc_ctl_full_r_reg_1(5 downto 0) => data_offset_2_i2(5 downto 0),
      phy_mc_data_full => phy_mc_data_full,
      phy_rddata_en => phy_rddata_en,
      phy_read_calib => phy_read_calib,
      phy_write_calib => phy_write_calib,
      \pi_counter_read_val_reg[5]\(5 downto 0) => \pi_counter_read_val_reg[5]\(5 downto 0),
      \pi_counter_read_val_reg[5]_0\(5 downto 0) => \pi_counter_read_val_reg[5]_0\(5 downto 0),
      \pi_dqs_found_lanes_r1_reg[0]\ => \pi_dqs_found_lanes_r1_reg[0]\,
      \pi_dqs_found_lanes_r1_reg[0]_0\ => \pi_dqs_found_lanes_r1_reg[0]_0\,
      \pi_dqs_found_lanes_r1_reg[0]_1\ => \pi_dqs_found_lanes_r1_reg[0]_1\,
      \pi_dqs_found_lanes_r1_reg[0]_2\ => \pi_dqs_found_lanes_r1_reg[0]_2\,
      \pi_dqs_found_lanes_r1_reg[10]\ => \pi_dqs_found_lanes_r1_reg[10]\,
      \pi_dqs_found_lanes_r1_reg[10]_0\ => \pi_dqs_found_lanes_r1_reg[10]_0\,
      \pi_dqs_found_lanes_r1_reg[10]_1\ => \pi_dqs_found_lanes_r1_reg[10]_1\,
      \pi_dqs_found_lanes_r1_reg[10]_2\ => \pi_dqs_found_lanes_r1_reg[10]_2\,
      \pi_dqs_found_lanes_r1_reg[10]_3\(5 downto 0) => \pi_dqs_found_lanes_r1_reg[10]_3\(5 downto 0),
      \pi_dqs_found_lanes_r1_reg[11]\ => \pi_dqs_found_lanes_r1_reg[11]\,
      \pi_dqs_found_lanes_r1_reg[11]_0\ => \pi_dqs_found_lanes_r1_reg[11]_0\,
      \pi_dqs_found_lanes_r1_reg[11]_1\ => \pi_dqs_found_lanes_r1_reg[11]_1\,
      \pi_dqs_found_lanes_r1_reg[11]_2\ => \pi_dqs_found_lanes_r1_reg[11]_2\,
      \pi_dqs_found_lanes_r1_reg[11]_3\(5 downto 0) => \pi_dqs_found_lanes_r1_reg[11]_3\(5 downto 0),
      \pi_dqs_found_lanes_r1_reg[1]\ => \pi_dqs_found_lanes_r1_reg[1]\,
      \pi_dqs_found_lanes_r1_reg[1]_0\ => \pi_dqs_found_lanes_r1_reg[1]_0\,
      \pi_dqs_found_lanes_r1_reg[1]_1\ => \pi_dqs_found_lanes_r1_reg[1]_1\,
      \pi_dqs_found_lanes_r1_reg[1]_2\ => \pi_dqs_found_lanes_r1_reg[1]_2\,
      \pi_dqs_found_lanes_r1_reg[1]_3\(5 downto 0) => \pi_dqs_found_lanes_r1_reg[1]_3\(5 downto 0),
      \pi_dqs_found_lanes_r1_reg[2]\ => \pi_dqs_found_lanes_r1_reg[2]\,
      \pi_dqs_found_lanes_r1_reg[2]_0\ => \pi_dqs_found_lanes_r1_reg[2]_0\,
      \pi_dqs_found_lanes_r1_reg[2]_1\ => \pi_dqs_found_lanes_r1_reg[2]_1\,
      \pi_dqs_found_lanes_r1_reg[2]_2\ => \pi_dqs_found_lanes_r1_reg[2]_2\,
      \pi_dqs_found_lanes_r1_reg[2]_3\(5 downto 0) => \pi_dqs_found_lanes_r1_reg[2]_3\(5 downto 0),
      \pi_dqs_found_lanes_r1_reg[3]\ => \pi_dqs_found_lanes_r1_reg[3]\,
      \pi_dqs_found_lanes_r1_reg[3]_0\ => \pi_dqs_found_lanes_r1_reg[3]_0\,
      \pi_dqs_found_lanes_r1_reg[3]_1\ => \pi_dqs_found_lanes_r1_reg[3]_1\,
      \pi_dqs_found_lanes_r1_reg[3]_2\ => \pi_dqs_found_lanes_r1_reg[3]_2\,
      \pi_dqs_found_lanes_r1_reg[3]_3\(5 downto 0) => \pi_dqs_found_lanes_r1_reg[3]_3\(5 downto 0),
      \pi_dqs_found_lanes_r1_reg[8]\ => \pi_dqs_found_lanes_r1_reg[8]\,
      \pi_dqs_found_lanes_r1_reg[8]_0\ => \pi_dqs_found_lanes_r1_reg[8]_0\,
      \pi_dqs_found_lanes_r1_reg[8]_1\ => \pi_dqs_found_lanes_r1_reg[8]_1\,
      \pi_dqs_found_lanes_r1_reg[8]_2\ => \pi_dqs_found_lanes_r1_reg[8]_2\,
      \pi_dqs_found_lanes_r1_reg[8]_3\(5 downto 0) => \pi_dqs_found_lanes_r1_reg[8]_3\(5 downto 0),
      \pi_dqs_found_lanes_r1_reg[9]\ => \pi_dqs_found_lanes_r1_reg[9]\,
      \pi_dqs_found_lanes_r1_reg[9]_0\ => \pi_dqs_found_lanes_r1_reg[9]_0\,
      \pi_dqs_found_lanes_r1_reg[9]_1\ => \pi_dqs_found_lanes_r1_reg[9]_1\,
      \pi_dqs_found_lanes_r1_reg[9]_2\ => \pi_dqs_found_lanes_r1_reg[9]_2\,
      \pi_dqs_found_lanes_r1_reg[9]_3\(5 downto 0) => \pi_dqs_found_lanes_r1_reg[9]_3\(5 downto 0),
      pll_locked => pll_locked,
      \po_counter_read_val_reg[0]\ => \po_counter_read_val_reg[0]\,
      \po_counter_read_val_reg[0]_0\(0) => \po_counter_read_val_reg[0]_0\(0),
      \po_counter_read_val_reg[1]\ => \po_counter_read_val_reg[1]\,
      \po_counter_read_val_reg[2]\ => \po_counter_read_val_reg[2]\,
      \po_counter_read_val_reg[3]\ => \po_counter_read_val_reg[3]\,
      \po_counter_read_val_reg[4]\ => \po_counter_read_val_reg[4]\,
      \po_counter_read_val_reg[5]\ => \po_counter_read_val_reg[5]\,
      \po_counter_read_val_reg[6]\ => \po_counter_read_val_reg[6]\,
      \po_counter_read_val_reg[7]\ => \po_counter_read_val_reg[7]\,
      \po_counter_read_val_reg[8]\ => \po_counter_read_val_reg[8]\,
      \po_counter_read_val_reg[8]_0\ => \po_counter_read_val_reg[8]_0\,
      \po_counter_read_val_reg[8]_1\ => \po_counter_read_val_reg[8]_1\,
      \po_counter_read_val_reg[8]_10\ => \po_counter_read_val_reg[8]_10\,
      \po_counter_read_val_reg[8]_11\ => \po_counter_read_val_reg[8]_11\,
      \po_counter_read_val_reg[8]_12\ => \po_counter_read_val_reg[8]_12\,
      \po_counter_read_val_reg[8]_13\ => \po_counter_read_val_reg[8]_13\,
      \po_counter_read_val_reg[8]_14\ => \po_counter_read_val_reg[8]_14\,
      \po_counter_read_val_reg[8]_15\ => \po_counter_read_val_reg[8]_15\,
      \po_counter_read_val_reg[8]_16\ => \po_counter_read_val_reg[8]_16\,
      \po_counter_read_val_reg[8]_17\ => \po_counter_read_val_reg[8]_17\,
      \po_counter_read_val_reg[8]_18\ => \po_counter_read_val_reg[8]_18\,
      \po_counter_read_val_reg[8]_19\ => \po_counter_read_val_reg[8]_19\,
      \po_counter_read_val_reg[8]_2\ => \po_counter_read_val_reg[8]_2\,
      \po_counter_read_val_reg[8]_20\ => \po_counter_read_val_reg[8]_20\,
      \po_counter_read_val_reg[8]_21\ => \po_counter_read_val_reg[8]_21\,
      \po_counter_read_val_reg[8]_22\ => \po_counter_read_val_reg[8]_22\,
      \po_counter_read_val_reg[8]_23\ => \po_counter_read_val_reg[8]_23\,
      \po_counter_read_val_reg[8]_24\ => \po_counter_read_val_reg[8]_24\,
      \po_counter_read_val_reg[8]_25\ => \po_counter_read_val_reg[8]_25\,
      \po_counter_read_val_reg[8]_26\ => \po_counter_read_val_reg[8]_26\,
      \po_counter_read_val_reg[8]_27\ => \po_counter_read_val_reg[8]_27\,
      \po_counter_read_val_reg[8]_28\ => \po_counter_read_val_reg[8]_28\,
      \po_counter_read_val_reg[8]_29\ => \po_counter_read_val_reg[8]_29\,
      \po_counter_read_val_reg[8]_3\ => \po_counter_read_val_reg[8]_3\,
      \po_counter_read_val_reg[8]_30\ => \po_counter_read_val_reg[8]_30\,
      \po_counter_read_val_reg[8]_31\ => \po_counter_read_val_reg[8]_31\,
      \po_counter_read_val_reg[8]_4\ => \po_counter_read_val_reg[8]_4\,
      \po_counter_read_val_reg[8]_5\ => \po_counter_read_val_reg[8]_5\,
      \po_counter_read_val_reg[8]_6\ => \po_counter_read_val_reg[8]_6\,
      \po_counter_read_val_reg[8]_7\ => \po_counter_read_val_reg[8]_7\,
      \po_counter_read_val_reg[8]_8\ => \po_counter_read_val_reg[8]_8\,
      \po_counter_read_val_reg[8]_9\ => \po_counter_read_val_reg[8]_9\,
      \po_stg2_wrcal_cnt_reg[2]\ => \po_stg2_wrcal_cnt_reg[2]\,
      \po_stg2_wrcal_cnt_reg[2]_0\ => \po_stg2_wrcal_cnt_reg[2]_0\,
      \po_stg2_wrcal_cnt_reg[2]_1\ => \po_stg2_wrcal_cnt_reg[2]_1\,
      \po_stg2_wrcal_cnt_reg[2]_10\ => \po_stg2_wrcal_cnt_reg[2]_10\,
      \po_stg2_wrcal_cnt_reg[2]_11\ => \po_stg2_wrcal_cnt_reg[2]_11\,
      \po_stg2_wrcal_cnt_reg[2]_12\ => \po_stg2_wrcal_cnt_reg[2]_12\,
      \po_stg2_wrcal_cnt_reg[2]_13\ => \po_stg2_wrcal_cnt_reg[2]_13\,
      \po_stg2_wrcal_cnt_reg[2]_14\ => \po_stg2_wrcal_cnt_reg[2]_14\,
      \po_stg2_wrcal_cnt_reg[2]_15\ => \po_stg2_wrcal_cnt_reg[2]_15\,
      \po_stg2_wrcal_cnt_reg[2]_16\ => \po_stg2_wrcal_cnt_reg[2]_16\,
      \po_stg2_wrcal_cnt_reg[2]_17\ => \po_stg2_wrcal_cnt_reg[2]_17\,
      \po_stg2_wrcal_cnt_reg[2]_18\ => \po_stg2_wrcal_cnt_reg[2]_18\,
      \po_stg2_wrcal_cnt_reg[2]_19\ => \po_stg2_wrcal_cnt_reg[2]_19\,
      \po_stg2_wrcal_cnt_reg[2]_2\ => \po_stg2_wrcal_cnt_reg[2]_2\,
      \po_stg2_wrcal_cnt_reg[2]_20\ => \po_stg2_wrcal_cnt_reg[2]_20\,
      \po_stg2_wrcal_cnt_reg[2]_21\ => \po_stg2_wrcal_cnt_reg[2]_21\,
      \po_stg2_wrcal_cnt_reg[2]_22\ => \po_stg2_wrcal_cnt_reg[2]_22\,
      \po_stg2_wrcal_cnt_reg[2]_23\ => \po_stg2_wrcal_cnt_reg[2]_23\,
      \po_stg2_wrcal_cnt_reg[2]_24\ => \po_stg2_wrcal_cnt_reg[2]_24\,
      \po_stg2_wrcal_cnt_reg[2]_25\ => \po_stg2_wrcal_cnt_reg[2]_25\,
      \po_stg2_wrcal_cnt_reg[2]_26\ => \po_stg2_wrcal_cnt_reg[2]_26\,
      \po_stg2_wrcal_cnt_reg[2]_27\ => \po_stg2_wrcal_cnt_reg[2]_27\,
      \po_stg2_wrcal_cnt_reg[2]_28\ => \po_stg2_wrcal_cnt_reg[2]_28\,
      \po_stg2_wrcal_cnt_reg[2]_29\ => \po_stg2_wrcal_cnt_reg[2]_29\,
      \po_stg2_wrcal_cnt_reg[2]_3\ => \po_stg2_wrcal_cnt_reg[2]_3\,
      \po_stg2_wrcal_cnt_reg[2]_30\ => \po_stg2_wrcal_cnt_reg[2]_30\,
      \po_stg2_wrcal_cnt_reg[2]_31\ => \po_stg2_wrcal_cnt_reg[2]_31\,
      \po_stg2_wrcal_cnt_reg[2]_32\ => \po_stg2_wrcal_cnt_reg[2]_32\,
      \po_stg2_wrcal_cnt_reg[2]_33\ => \po_stg2_wrcal_cnt_reg[2]_33\,
      \po_stg2_wrcal_cnt_reg[2]_34\ => \po_stg2_wrcal_cnt_reg[2]_34\,
      \po_stg2_wrcal_cnt_reg[2]_35\ => \po_stg2_wrcal_cnt_reg[2]_35\,
      \po_stg2_wrcal_cnt_reg[2]_36\ => \po_stg2_wrcal_cnt_reg[2]_36\,
      \po_stg2_wrcal_cnt_reg[2]_37\ => \po_stg2_wrcal_cnt_reg[2]_37\,
      \po_stg2_wrcal_cnt_reg[2]_38\ => \po_stg2_wrcal_cnt_reg[2]_38\,
      \po_stg2_wrcal_cnt_reg[2]_39\ => \po_stg2_wrcal_cnt_reg[2]_39\,
      \po_stg2_wrcal_cnt_reg[2]_4\ => \po_stg2_wrcal_cnt_reg[2]_4\,
      \po_stg2_wrcal_cnt_reg[2]_40\ => \po_stg2_wrcal_cnt_reg[2]_40\,
      \po_stg2_wrcal_cnt_reg[2]_41\ => \po_stg2_wrcal_cnt_reg[2]_41\,
      \po_stg2_wrcal_cnt_reg[2]_42\ => \po_stg2_wrcal_cnt_reg[2]_42\,
      \po_stg2_wrcal_cnt_reg[2]_43\ => \po_stg2_wrcal_cnt_reg[2]_43\,
      \po_stg2_wrcal_cnt_reg[2]_44\ => \po_stg2_wrcal_cnt_reg[2]_44\,
      \po_stg2_wrcal_cnt_reg[2]_45\ => \po_stg2_wrcal_cnt_reg[2]_45\,
      \po_stg2_wrcal_cnt_reg[2]_46\ => \po_stg2_wrcal_cnt_reg[2]_46\,
      \po_stg2_wrcal_cnt_reg[2]_47\ => \po_stg2_wrcal_cnt_reg[2]_47\,
      \po_stg2_wrcal_cnt_reg[2]_48\ => \po_stg2_wrcal_cnt_reg[2]_48\,
      \po_stg2_wrcal_cnt_reg[2]_49\ => \po_stg2_wrcal_cnt_reg[2]_49\,
      \po_stg2_wrcal_cnt_reg[2]_5\ => \po_stg2_wrcal_cnt_reg[2]_5\,
      \po_stg2_wrcal_cnt_reg[2]_50\ => \po_stg2_wrcal_cnt_reg[2]_50\,
      \po_stg2_wrcal_cnt_reg[2]_51\ => \po_stg2_wrcal_cnt_reg[2]_51\,
      \po_stg2_wrcal_cnt_reg[2]_52\ => \po_stg2_wrcal_cnt_reg[2]_52\,
      \po_stg2_wrcal_cnt_reg[2]_53\ => \po_stg2_wrcal_cnt_reg[2]_53\,
      \po_stg2_wrcal_cnt_reg[2]_54\ => \po_stg2_wrcal_cnt_reg[2]_54\,
      \po_stg2_wrcal_cnt_reg[2]_55\ => \po_stg2_wrcal_cnt_reg[2]_55\,
      \po_stg2_wrcal_cnt_reg[2]_56\ => \po_stg2_wrcal_cnt_reg[2]_56\,
      \po_stg2_wrcal_cnt_reg[2]_57\ => \po_stg2_wrcal_cnt_reg[2]_57\,
      \po_stg2_wrcal_cnt_reg[2]_58\ => \po_stg2_wrcal_cnt_reg[2]_58\,
      \po_stg2_wrcal_cnt_reg[2]_59\ => \po_stg2_wrcal_cnt_reg[2]_59\,
      \po_stg2_wrcal_cnt_reg[2]_6\ => \po_stg2_wrcal_cnt_reg[2]_6\,
      \po_stg2_wrcal_cnt_reg[2]_60\ => \po_stg2_wrcal_cnt_reg[2]_60\,
      \po_stg2_wrcal_cnt_reg[2]_61\ => \po_stg2_wrcal_cnt_reg[2]_61\,
      \po_stg2_wrcal_cnt_reg[2]_7\ => \po_stg2_wrcal_cnt_reg[2]_7\,
      \po_stg2_wrcal_cnt_reg[2]_8\ => \po_stg2_wrcal_cnt_reg[2]_8\,
      \po_stg2_wrcal_cnt_reg[2]_9\ => \po_stg2_wrcal_cnt_reg[2]_9\,
      \rd_mux_sel_r_reg[2]\ => \rd_mux_sel_r_reg[2]\,
      \rd_mux_sel_r_reg[2]_0\ => \rd_mux_sel_r_reg[2]_0\,
      \rd_mux_sel_r_reg[2]_1\ => \rd_mux_sel_r_reg[2]_1\,
      \rd_mux_sel_r_reg[2]_10\ => \rd_mux_sel_r_reg[2]_10\,
      \rd_mux_sel_r_reg[2]_100\ => \rd_mux_sel_r_reg[2]_100\,
      \rd_mux_sel_r_reg[2]_101\ => \rd_mux_sel_r_reg[2]_101\,
      \rd_mux_sel_r_reg[2]_102\ => \rd_mux_sel_r_reg[2]_102\,
      \rd_mux_sel_r_reg[2]_103\ => \rd_mux_sel_r_reg[2]_103\,
      \rd_mux_sel_r_reg[2]_104\ => \rd_mux_sel_r_reg[2]_104\,
      \rd_mux_sel_r_reg[2]_105\ => \rd_mux_sel_r_reg[2]_105\,
      \rd_mux_sel_r_reg[2]_106\ => \rd_mux_sel_r_reg[2]_106\,
      \rd_mux_sel_r_reg[2]_107\ => \rd_mux_sel_r_reg[2]_107\,
      \rd_mux_sel_r_reg[2]_108\ => \rd_mux_sel_r_reg[2]_108\,
      \rd_mux_sel_r_reg[2]_109\ => \rd_mux_sel_r_reg[2]_109\,
      \rd_mux_sel_r_reg[2]_11\ => \rd_mux_sel_r_reg[2]_11\,
      \rd_mux_sel_r_reg[2]_110\ => \rd_mux_sel_r_reg[2]_110\,
      \rd_mux_sel_r_reg[2]_111\ => \rd_mux_sel_r_reg[2]_111\,
      \rd_mux_sel_r_reg[2]_112\ => \rd_mux_sel_r_reg[2]_112\,
      \rd_mux_sel_r_reg[2]_113\ => \rd_mux_sel_r_reg[2]_113\,
      \rd_mux_sel_r_reg[2]_114\ => \rd_mux_sel_r_reg[2]_114\,
      \rd_mux_sel_r_reg[2]_115\ => \rd_mux_sel_r_reg[2]_115\,
      \rd_mux_sel_r_reg[2]_116\ => \rd_mux_sel_r_reg[2]_116\,
      \rd_mux_sel_r_reg[2]_117\ => \rd_mux_sel_r_reg[2]_117\,
      \rd_mux_sel_r_reg[2]_118\ => \rd_mux_sel_r_reg[2]_118\,
      \rd_mux_sel_r_reg[2]_119\ => \rd_mux_sel_r_reg[2]_119\,
      \rd_mux_sel_r_reg[2]_12\ => \rd_mux_sel_r_reg[2]_12\,
      \rd_mux_sel_r_reg[2]_120\ => \rd_mux_sel_r_reg[2]_120\,
      \rd_mux_sel_r_reg[2]_121\ => \rd_mux_sel_r_reg[2]_121\,
      \rd_mux_sel_r_reg[2]_122\ => \rd_mux_sel_r_reg[2]_122\,
      \rd_mux_sel_r_reg[2]_123\ => \rd_mux_sel_r_reg[2]_123\,
      \rd_mux_sel_r_reg[2]_124\ => \rd_mux_sel_r_reg[2]_124\,
      \rd_mux_sel_r_reg[2]_125\ => \rd_mux_sel_r_reg[2]_125\,
      \rd_mux_sel_r_reg[2]_126\ => \rd_mux_sel_r_reg[2]_126\,
      \rd_mux_sel_r_reg[2]_13\ => \rd_mux_sel_r_reg[2]_13\,
      \rd_mux_sel_r_reg[2]_14\ => \rd_mux_sel_r_reg[2]_14\,
      \rd_mux_sel_r_reg[2]_15\ => \rd_mux_sel_r_reg[2]_15\,
      \rd_mux_sel_r_reg[2]_16\ => \rd_mux_sel_r_reg[2]_16\,
      \rd_mux_sel_r_reg[2]_17\ => \rd_mux_sel_r_reg[2]_17\,
      \rd_mux_sel_r_reg[2]_18\ => \rd_mux_sel_r_reg[2]_18\,
      \rd_mux_sel_r_reg[2]_19\ => \rd_mux_sel_r_reg[2]_19\,
      \rd_mux_sel_r_reg[2]_2\ => \rd_mux_sel_r_reg[2]_2\,
      \rd_mux_sel_r_reg[2]_20\ => \rd_mux_sel_r_reg[2]_20\,
      \rd_mux_sel_r_reg[2]_21\ => \rd_mux_sel_r_reg[2]_21\,
      \rd_mux_sel_r_reg[2]_22\ => \rd_mux_sel_r_reg[2]_22\,
      \rd_mux_sel_r_reg[2]_23\ => \rd_mux_sel_r_reg[2]_23\,
      \rd_mux_sel_r_reg[2]_24\ => \rd_mux_sel_r_reg[2]_24\,
      \rd_mux_sel_r_reg[2]_25\ => \rd_mux_sel_r_reg[2]_25\,
      \rd_mux_sel_r_reg[2]_26\ => \rd_mux_sel_r_reg[2]_26\,
      \rd_mux_sel_r_reg[2]_27\ => \rd_mux_sel_r_reg[2]_27\,
      \rd_mux_sel_r_reg[2]_28\ => \rd_mux_sel_r_reg[2]_28\,
      \rd_mux_sel_r_reg[2]_29\ => \rd_mux_sel_r_reg[2]_29\,
      \rd_mux_sel_r_reg[2]_3\ => \rd_mux_sel_r_reg[2]_3\,
      \rd_mux_sel_r_reg[2]_30\ => \rd_mux_sel_r_reg[2]_30\,
      \rd_mux_sel_r_reg[2]_31\ => \rd_mux_sel_r_reg[2]_31\,
      \rd_mux_sel_r_reg[2]_32\ => \rd_mux_sel_r_reg[2]_32\,
      \rd_mux_sel_r_reg[2]_33\ => \rd_mux_sel_r_reg[2]_33\,
      \rd_mux_sel_r_reg[2]_34\ => \rd_mux_sel_r_reg[2]_34\,
      \rd_mux_sel_r_reg[2]_35\ => \rd_mux_sel_r_reg[2]_35\,
      \rd_mux_sel_r_reg[2]_36\ => \rd_mux_sel_r_reg[2]_36\,
      \rd_mux_sel_r_reg[2]_37\ => \rd_mux_sel_r_reg[2]_37\,
      \rd_mux_sel_r_reg[2]_38\ => \rd_mux_sel_r_reg[2]_38\,
      \rd_mux_sel_r_reg[2]_39\ => \rd_mux_sel_r_reg[2]_39\,
      \rd_mux_sel_r_reg[2]_4\ => \rd_mux_sel_r_reg[2]_4\,
      \rd_mux_sel_r_reg[2]_40\ => \rd_mux_sel_r_reg[2]_40\,
      \rd_mux_sel_r_reg[2]_41\ => \rd_mux_sel_r_reg[2]_41\,
      \rd_mux_sel_r_reg[2]_42\ => \rd_mux_sel_r_reg[2]_42\,
      \rd_mux_sel_r_reg[2]_43\ => \rd_mux_sel_r_reg[2]_43\,
      \rd_mux_sel_r_reg[2]_44\ => \rd_mux_sel_r_reg[2]_44\,
      \rd_mux_sel_r_reg[2]_45\ => \rd_mux_sel_r_reg[2]_45\,
      \rd_mux_sel_r_reg[2]_46\ => \rd_mux_sel_r_reg[2]_46\,
      \rd_mux_sel_r_reg[2]_47\ => \rd_mux_sel_r_reg[2]_47\,
      \rd_mux_sel_r_reg[2]_48\ => \rd_mux_sel_r_reg[2]_48\,
      \rd_mux_sel_r_reg[2]_49\ => \rd_mux_sel_r_reg[2]_49\,
      \rd_mux_sel_r_reg[2]_5\ => \rd_mux_sel_r_reg[2]_5\,
      \rd_mux_sel_r_reg[2]_50\ => \rd_mux_sel_r_reg[2]_50\,
      \rd_mux_sel_r_reg[2]_51\ => \rd_mux_sel_r_reg[2]_51\,
      \rd_mux_sel_r_reg[2]_52\ => \rd_mux_sel_r_reg[2]_52\,
      \rd_mux_sel_r_reg[2]_53\ => \rd_mux_sel_r_reg[2]_53\,
      \rd_mux_sel_r_reg[2]_54\ => \rd_mux_sel_r_reg[2]_54\,
      \rd_mux_sel_r_reg[2]_55\ => \rd_mux_sel_r_reg[2]_55\,
      \rd_mux_sel_r_reg[2]_56\ => \rd_mux_sel_r_reg[2]_56\,
      \rd_mux_sel_r_reg[2]_57\ => \rd_mux_sel_r_reg[2]_57\,
      \rd_mux_sel_r_reg[2]_58\ => \rd_mux_sel_r_reg[2]_58\,
      \rd_mux_sel_r_reg[2]_59\ => \rd_mux_sel_r_reg[2]_59\,
      \rd_mux_sel_r_reg[2]_6\ => \rd_mux_sel_r_reg[2]_6\,
      \rd_mux_sel_r_reg[2]_60\ => \rd_mux_sel_r_reg[2]_60\,
      \rd_mux_sel_r_reg[2]_61\ => \rd_mux_sel_r_reg[2]_61\,
      \rd_mux_sel_r_reg[2]_62\ => \rd_mux_sel_r_reg[2]_62\,
      \rd_mux_sel_r_reg[2]_63\ => \rd_mux_sel_r_reg[2]_63\,
      \rd_mux_sel_r_reg[2]_64\ => \rd_mux_sel_r_reg[2]_64\,
      \rd_mux_sel_r_reg[2]_65\ => \rd_mux_sel_r_reg[2]_65\,
      \rd_mux_sel_r_reg[2]_66\ => \rd_mux_sel_r_reg[2]_66\,
      \rd_mux_sel_r_reg[2]_67\ => \rd_mux_sel_r_reg[2]_67\,
      \rd_mux_sel_r_reg[2]_68\ => \rd_mux_sel_r_reg[2]_68\,
      \rd_mux_sel_r_reg[2]_69\ => \rd_mux_sel_r_reg[2]_69\,
      \rd_mux_sel_r_reg[2]_7\ => \rd_mux_sel_r_reg[2]_7\,
      \rd_mux_sel_r_reg[2]_70\ => \rd_mux_sel_r_reg[2]_70\,
      \rd_mux_sel_r_reg[2]_71\ => \rd_mux_sel_r_reg[2]_71\,
      \rd_mux_sel_r_reg[2]_72\ => \rd_mux_sel_r_reg[2]_72\,
      \rd_mux_sel_r_reg[2]_73\ => \rd_mux_sel_r_reg[2]_73\,
      \rd_mux_sel_r_reg[2]_74\ => \rd_mux_sel_r_reg[2]_74\,
      \rd_mux_sel_r_reg[2]_75\ => \rd_mux_sel_r_reg[2]_75\,
      \rd_mux_sel_r_reg[2]_76\ => \rd_mux_sel_r_reg[2]_76\,
      \rd_mux_sel_r_reg[2]_77\ => \rd_mux_sel_r_reg[2]_77\,
      \rd_mux_sel_r_reg[2]_78\ => \rd_mux_sel_r_reg[2]_78\,
      \rd_mux_sel_r_reg[2]_79\ => \rd_mux_sel_r_reg[2]_79\,
      \rd_mux_sel_r_reg[2]_8\ => \rd_mux_sel_r_reg[2]_8\,
      \rd_mux_sel_r_reg[2]_80\ => \rd_mux_sel_r_reg[2]_80\,
      \rd_mux_sel_r_reg[2]_81\ => \rd_mux_sel_r_reg[2]_81\,
      \rd_mux_sel_r_reg[2]_82\ => \rd_mux_sel_r_reg[2]_82\,
      \rd_mux_sel_r_reg[2]_83\ => \rd_mux_sel_r_reg[2]_83\,
      \rd_mux_sel_r_reg[2]_84\ => \rd_mux_sel_r_reg[2]_84\,
      \rd_mux_sel_r_reg[2]_85\ => \rd_mux_sel_r_reg[2]_85\,
      \rd_mux_sel_r_reg[2]_86\ => \rd_mux_sel_r_reg[2]_86\,
      \rd_mux_sel_r_reg[2]_87\ => \rd_mux_sel_r_reg[2]_87\,
      \rd_mux_sel_r_reg[2]_88\ => \rd_mux_sel_r_reg[2]_88\,
      \rd_mux_sel_r_reg[2]_89\ => \rd_mux_sel_r_reg[2]_89\,
      \rd_mux_sel_r_reg[2]_9\ => \rd_mux_sel_r_reg[2]_9\,
      \rd_mux_sel_r_reg[2]_90\ => \rd_mux_sel_r_reg[2]_90\,
      \rd_mux_sel_r_reg[2]_91\ => \rd_mux_sel_r_reg[2]_91\,
      \rd_mux_sel_r_reg[2]_92\ => \rd_mux_sel_r_reg[2]_92\,
      \rd_mux_sel_r_reg[2]_93\ => \rd_mux_sel_r_reg[2]_93\,
      \rd_mux_sel_r_reg[2]_94\ => \rd_mux_sel_r_reg[2]_94\,
      \rd_mux_sel_r_reg[2]_95\ => \rd_mux_sel_r_reg[2]_95\,
      \rd_mux_sel_r_reg[2]_96\ => \rd_mux_sel_r_reg[2]_96\,
      \rd_mux_sel_r_reg[2]_97\ => \rd_mux_sel_r_reg[2]_97\,
      \rd_mux_sel_r_reg[2]_98\ => \rd_mux_sel_r_reg[2]_98\,
      \rd_mux_sel_r_reg[2]_99\ => \rd_mux_sel_r_reg[2]_99\,
      \rd_ptr_reg[3]\(63 downto 0) => \rd_ptr_reg[3]\(63 downto 0),
      \rd_ptr_reg[3]_0\(63 downto 0) => \rd_ptr_reg[3]_0\(63 downto 0),
      \rd_ptr_reg[3]_1\(63 downto 0) => \rd_ptr_reg[3]_1\(63 downto 0),
      \rd_ptr_reg[3]_2\(63 downto 0) => \rd_ptr_reg[3]_2\(63 downto 0),
      \rd_ptr_reg[3]_3\(63 downto 0) => \rd_ptr_reg[3]_3\(63 downto 0),
      \rd_ptr_reg[3]_4\(63 downto 0) => \rd_ptr_reg[3]_4\(63 downto 0),
      \rd_ptr_reg[3]_5\(63 downto 0) => \rd_ptr_reg[3]_5\(63 downto 0),
      \rd_ptr_reg[3]_6\(63 downto 0) => \rd_ptr_reg[3]_6\(63 downto 0),
      \rd_ptr_reg[3]_7\(35 downto 0) => \rd_ptr_reg[3]_7\(35 downto 0),
      \rd_ptr_reg[3]_8\(23 downto 0) => \rd_ptr_reg[3]_8\(23 downto 0),
      \rd_ptr_reg[3]_9\(3 downto 0) => \rd_ptr_reg[3]_9\(3 downto 0),
      rst_tmp => rst_tmp,
      \rstdiv2_sync_r_reg[11]\ => \rstdiv2_sync_r_reg[11]\,
      sync_pulse => sync_pulse,
      ts_dqs_0 => ts_dqs_0,
      ts_dqs_1 => ts_dqs_1,
      ts_dqs_2 => ts_dqs_2,
      ts_dqs_3 => ts_dqs_3,
      ts_dqs_4 => ts_dqs_4,
      ts_dqs_5 => ts_dqs_5,
      ts_dqs_6 => ts_dqs_6,
      ts_dqs_7 => ts_dqs_7
    );
u_ras_n_obuf: unisim.vcomponents.OBUF
    generic map(
      IOSTANDARD => "DEFAULT"
    )
        port map (
      I => mem_dq_out(70),
      O => ddr3_ras_n
    );
u_we_n_obuf: unisim.vcomponents.OBUF
    generic map(
      IOSTANDARD => "DEFAULT"
    )
        port map (
      I => mem_dq_out(71),
      O => ddr3_we_n
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mig_mig_7series_v4_2_mc is
  port (
    app_ref_ack : out STD_LOGIC;
    app_zq_ack : out STD_LOGIC;
    \generate_maint_cmds.insert_maint_r_lcl_reg\ : out STD_LOGIC;
    accept_ns : out STD_LOGIC;
    bm_end_r1 : out STD_LOGIC;
    bm_end_r1_0 : out STD_LOGIC;
    bm_end_r1_1 : out STD_LOGIC;
    mc_cmd : out STD_LOGIC_VECTOR ( 1 downto 0 );
    app_sr_active : out STD_LOGIC;
    \read_fifo.tail_r_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    phy_dout : out STD_LOGIC_VECTOR ( 6 downto 0 );
    mc_we_n : out STD_LOGIC_VECTOR ( 2 downto 0 );
    mc_ras_n : out STD_LOGIC_VECTOR ( 2 downto 0 );
    mc_cs_n : out STD_LOGIC_VECTOR ( 0 to 0 );
    mc_cas_n : out STD_LOGIC_VECTOR ( 2 downto 0 );
    d_in : out STD_LOGIC_VECTOR ( 3 downto 0 );
    Q : out STD_LOGIC_VECTOR ( 38 downto 0 );
    \req_bank_r_lcl_reg[2]\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
    \req_bank_r_lcl_reg[2]_0\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
    \req_bank_r_lcl_reg[2]_1\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
    \req_bank_r_lcl_reg[2]_2\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
    \req_row_r_lcl_reg[13]\ : out STD_LOGIC_VECTOR ( 19 downto 0 );
    \pointer_ram.pointer_we\ : out STD_LOGIC;
    wr_data_en : out STD_LOGIC;
    \read_fifo.fifo_out_data_r_reg[7]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    wr_data_addr : out STD_LOGIC_VECTOR ( 3 downto 0 );
    mc_ref_zq_wip : out STD_LOGIC;
    \cmd_pipe_plus.mc_bank_reg[8]_0\ : out STD_LOGIC_VECTOR ( 8 downto 0 );
    mc_odt : out STD_LOGIC_VECTOR ( 0 to 0 );
    mc_cke : out STD_LOGIC_VECTOR ( 0 to 0 );
    mc_wrdata_en : out STD_LOGIC;
    \cmd_pipe_plus.mc_data_offset_reg[3]_0\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    \cmd_pipe_plus.mc_data_offset_reg[5]_0\ : out STD_LOGIC;
    \cmd_pipe_plus.mc_data_offset_reg[4]_0\ : out STD_LOGIC;
    \cmd_pipe_plus.mc_data_offset_reg[2]_0\ : out STD_LOGIC;
    \cmd_pipe_plus.mc_data_offset_reg[1]_0\ : out STD_LOGIC;
    \cmd_pipe_plus.mc_data_offset_reg[0]_0\ : out STD_LOGIC;
    \cmd_pipe_plus.mc_data_offset_1_reg[3]_0\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    \cmd_pipe_plus.mc_data_offset_1_reg[5]_0\ : out STD_LOGIC;
    \cmd_pipe_plus.mc_data_offset_1_reg[4]_0\ : out STD_LOGIC;
    \cmd_pipe_plus.mc_data_offset_1_reg[2]_0\ : out STD_LOGIC;
    \cmd_pipe_plus.mc_data_offset_1_reg[1]_0\ : out STD_LOGIC;
    \cmd_pipe_plus.mc_data_offset_1_reg[0]_0\ : out STD_LOGIC;
    \cmd_pipe_plus.mc_data_offset_2_reg[3]_0\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    \cmd_pipe_plus.mc_data_offset_2_reg[5]_0\ : out STD_LOGIC;
    \cmd_pipe_plus.mc_data_offset_2_reg[4]_0\ : out STD_LOGIC;
    \cmd_pipe_plus.mc_data_offset_2_reg[2]_0\ : out STD_LOGIC;
    \cmd_pipe_plus.mc_data_offset_2_reg[1]_0\ : out STD_LOGIC;
    \cmd_pipe_plus.mc_data_offset_2_reg[0]_0\ : out STD_LOGIC;
    idle : out STD_LOGIC;
    \last_master_r_reg[2]\ : in STD_LOGIC;
    \periodic_read_request.periodic_rd_r_cnt_reg\ : in STD_LOGIC;
    \periodic_rd_generation.periodic_rd_cntr1_r_reg\ : in STD_LOGIC;
    phy_mc_ctl_full : in STD_LOGIC;
    \zq_cntrl.zq_request_logic.zq_request_r_reg\ : in STD_LOGIC;
    of_ctl_full_v : in STD_LOGIC_VECTOR ( 0 to 0 );
    SR : in STD_LOGIC_VECTOR ( 0 to 0 );
    \periodic_read_request.periodic_rd_r_lcl_reg\ : in STD_LOGIC;
    \grant_r_reg[0]\ : in STD_LOGIC;
    app_zq_req : in STD_LOGIC;
    app_sr_req : in STD_LOGIC;
    \last_master_r_reg[2]_0\ : in STD_LOGIC;
    use_addr : in STD_LOGIC;
    cmd : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \inhbt_act_faw.inhbt_act_faw_r_reg\ : in STD_LOGIC;
    app_ref_req : in STD_LOGIC;
    \read_fifo.tail_r_reg[2]\ : in STD_LOGIC;
    \cmd_pipe_plus.mc_data_offset_reg[5]_1\ : in STD_LOGIC_VECTOR ( 5 downto 0 );
    \cmd_pipe_plus.mc_data_offset_1_reg[5]_1\ : in STD_LOGIC_VECTOR ( 5 downto 0 );
    \cmd_pipe_plus.mc_data_offset_2_reg[5]_1\ : in STD_LOGIC_VECTOR ( 5 downto 0 );
    S : in STD_LOGIC_VECTOR ( 2 downto 0 );
    row_hit_r_reg : in STD_LOGIC_VECTOR ( 0 to 0 );
    row_hit_r_reg_0 : in STD_LOGIC_VECTOR ( 0 to 0 );
    row_hit_r_reg_1 : in STD_LOGIC_VECTOR ( 0 to 0 );
    row_hit_r_reg_2 : in STD_LOGIC_VECTOR ( 0 to 0 );
    row_hit_r_reg_3 : in STD_LOGIC_VECTOR ( 0 to 0 );
    mem_reg_0_15_42_47 : in STD_LOGIC;
    mem_reg_0_15_36_41 : in STD_LOGIC;
    \periodic_rd_generation.periodic_rd_timer_r_reg[2]\ : in STD_LOGIC;
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[5]\ : in STD_LOGIC;
    rb_hit_busy_r_reg : in STD_LOGIC;
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[6]\ : in STD_LOGIC;
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[4]\ : in STD_LOGIC;
    \rtp_timer_r_reg[1]\ : in STD_LOGIC;
    \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[3]\ : in STD_LOGIC;
    D : in STD_LOGIC_VECTOR ( 13 downto 0 );
    ras_timer_zero_r_reg : in STD_LOGIC;
    ras_timer_zero_r_reg_0 : in STD_LOGIC;
    ras_timer_zero_r_reg_1 : in STD_LOGIC;
    phy_mc_data_full : in STD_LOGIC;
    \rtp_timer_r_reg[0]\ : in STD_LOGIC;
    ram_init_done_r : in STD_LOGIC;
    was_priority_reg : in STD_LOGIC;
    \req_data_buf_addr_r_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
    \req_bank_r_lcl_reg[2]_3\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
    \req_col_r_reg[9]\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
    \read_fifo.tail_r_reg[0]_0\ : in STD_LOGIC;
    \cmd_pipe_plus.mc_data_offset_reg[0]_1\ : in STD_LOGIC;
    \cmd_pipe_plus.mc_data_offset_1_reg[0]_1\ : in STD_LOGIC;
    \cmd_pipe_plus.mc_data_offset_2_reg[0]_1\ : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of mig_mig_7series_v4_2_mc : entity is "mig_7series_v4_2_mc";
end mig_mig_7series_v4_2_mc;

architecture STRUCTURE of mig_mig_7series_v4_2_mc is
  signal \^q\ : STD_LOGIC_VECTOR ( 38 downto 0 );
  signal accept_internal_r : STD_LOGIC;
  signal \^app_sr_active\ : STD_LOGIC;
  signal \arb_mux0/arb_row_col0/pre_4_1_1T_arb.pre_arb0/last_master_r\ : STD_LOGIC_VECTOR ( 3 to 3 );
  signal \arb_mux0/arb_select0/cke_r\ : STD_LOGIC;
  signal \arb_mux0/arb_select0/mc_data_offset1\ : STD_LOGIC_VECTOR ( 5 downto 1 );
  signal \arb_mux0/arb_select0/mc_data_offset_11\ : STD_LOGIC_VECTOR ( 5 downto 1 );
  signal \arb_mux0/arb_select0/mc_data_offset_21\ : STD_LOGIC_VECTOR ( 5 downto 1 );
  signal \arb_mux0/cs_en2\ : STD_LOGIC;
  signal \bank_cntrl[0].bank0/auto_pre_r\ : STD_LOGIC;
  signal \bank_cntrl[0].bank0/bank_queue0/set_order_q\ : STD_LOGIC;
  signal \bank_cntrl[0].bank0/bank_state0/col_wait_r\ : STD_LOGIC;
  signal \bank_cntrl[0].bank0/bank_state0/demand_priority_r\ : STD_LOGIC;
  signal \bank_cntrl[0].bank0/bank_state0/demanded_prior_r\ : STD_LOGIC;
  signal \bank_cntrl[0].bank0/q_has_rd\ : STD_LOGIC;
  signal \bank_cntrl[0].bank0/rb_hit_busies_r\ : STD_LOGIC_VECTOR ( 1 to 1 );
  signal \bank_cntrl[0].bank0/tail_r\ : STD_LOGIC;
  signal \bank_cntrl[0].bank0/wait_for_maint_r\ : STD_LOGIC;
  signal \bank_cntrl[1].bank0/auto_pre_r\ : STD_LOGIC;
  signal \bank_cntrl[1].bank0/bank_queue0/pre_bm_end_r\ : STD_LOGIC;
  signal \bank_cntrl[1].bank0/bank_queue0/set_order_q\ : STD_LOGIC;
  signal \bank_cntrl[1].bank0/bank_state0/col_wait_r\ : STD_LOGIC;
  signal \bank_cntrl[1].bank0/bank_state0/demand_priority_r\ : STD_LOGIC;
  signal \bank_cntrl[1].bank0/bank_state0/demanded_prior_r\ : STD_LOGIC;
  signal \bank_cntrl[1].bank0/bank_state0/req_bank_rdy_ns\ : STD_LOGIC;
  signal \bank_cntrl[1].bank0/pass_open_bank_r\ : STD_LOGIC;
  signal \bank_cntrl[1].bank0/q_has_rd\ : STD_LOGIC;
  signal \bank_cntrl[1].bank0/tail_r\ : STD_LOGIC;
  signal \bank_cntrl[1].bank0/wait_for_maint_r\ : STD_LOGIC;
  signal \bank_cntrl[2].bank0/auto_pre_r\ : STD_LOGIC;
  signal \bank_cntrl[2].bank0/bank_queue0/set_order_q\ : STD_LOGIC;
  signal \bank_cntrl[2].bank0/bank_state0/col_wait_r\ : STD_LOGIC;
  signal \bank_cntrl[2].bank0/bank_state0/demand_priority_r\ : STD_LOGIC;
  signal \bank_cntrl[2].bank0/bank_state0/demanded_prior_r\ : STD_LOGIC;
  signal \bank_cntrl[2].bank0/bank_state0/override_demand_ns\ : STD_LOGIC;
  signal \bank_cntrl[2].bank0/bank_state0/override_demand_r\ : STD_LOGIC;
  signal \bank_cntrl[2].bank0/q_has_rd\ : STD_LOGIC;
  signal \bank_cntrl[2].bank0/rb_hit_busies_r\ : STD_LOGIC_VECTOR ( 4 to 4 );
  signal \bank_cntrl[2].bank0/tail_r\ : STD_LOGIC;
  signal \bank_cntrl[2].bank0/wait_for_maint_r\ : STD_LOGIC;
  signal \bank_cntrl[3].bank0/auto_pre_r\ : STD_LOGIC;
  signal \bank_cntrl[3].bank0/bank_queue0/pre_bm_end_r\ : STD_LOGIC;
  signal \bank_cntrl[3].bank0/bank_queue0/set_order_q\ : STD_LOGIC;
  signal \bank_cntrl[3].bank0/bank_state0/col_wait_r\ : STD_LOGIC;
  signal \bank_cntrl[3].bank0/bank_state0/demand_priority_r\ : STD_LOGIC;
  signal \bank_cntrl[3].bank0/pass_open_bank_r\ : STD_LOGIC;
  signal \bank_cntrl[3].bank0/q_has_rd\ : STD_LOGIC;
  signal \bank_cntrl[3].bank0/tail_r\ : STD_LOGIC;
  signal \bank_cntrl[3].bank0/wait_for_maint_r\ : STD_LOGIC;
  signal \bank_common0/maint_controller.maint_hit_busies_r\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \bank_common0/periodic_rd_cntr_r\ : STD_LOGIC;
  signal \bank_common0/rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal bank_mach0_n_10 : STD_LOGIC;
  signal bank_mach0_n_104 : STD_LOGIC;
  signal bank_mach0_n_113 : STD_LOGIC;
  signal bank_mach0_n_114 : STD_LOGIC;
  signal bank_mach0_n_115 : STD_LOGIC;
  signal bank_mach0_n_116 : STD_LOGIC;
  signal bank_mach0_n_117 : STD_LOGIC;
  signal bank_mach0_n_122 : STD_LOGIC;
  signal bank_mach0_n_123 : STD_LOGIC;
  signal bank_mach0_n_124 : STD_LOGIC;
  signal bank_mach0_n_125 : STD_LOGIC;
  signal bank_mach0_n_126 : STD_LOGIC;
  signal bank_mach0_n_127 : STD_LOGIC;
  signal bank_mach0_n_128 : STD_LOGIC;
  signal bank_mach0_n_129 : STD_LOGIC;
  signal bank_mach0_n_131 : STD_LOGIC;
  signal bank_mach0_n_132 : STD_LOGIC;
  signal bank_mach0_n_133 : STD_LOGIC;
  signal bank_mach0_n_135 : STD_LOGIC;
  signal bank_mach0_n_136 : STD_LOGIC;
  signal bank_mach0_n_137 : STD_LOGIC;
  signal bank_mach0_n_138 : STD_LOGIC;
  signal bank_mach0_n_140 : STD_LOGIC;
  signal bank_mach0_n_141 : STD_LOGIC;
  signal bank_mach0_n_142 : STD_LOGIC;
  signal bank_mach0_n_143 : STD_LOGIC;
  signal bank_mach0_n_144 : STD_LOGIC;
  signal bank_mach0_n_147 : STD_LOGIC;
  signal bank_mach0_n_149 : STD_LOGIC;
  signal bank_mach0_n_150 : STD_LOGIC;
  signal bank_mach0_n_151 : STD_LOGIC;
  signal bank_mach0_n_152 : STD_LOGIC;
  signal bank_mach0_n_154 : STD_LOGIC;
  signal bank_mach0_n_155 : STD_LOGIC;
  signal bank_mach0_n_156 : STD_LOGIC;
  signal bank_mach0_n_157 : STD_LOGIC;
  signal bank_mach0_n_158 : STD_LOGIC;
  signal bank_mach0_n_159 : STD_LOGIC;
  signal bank_mach0_n_160 : STD_LOGIC;
  signal bank_mach0_n_161 : STD_LOGIC;
  signal bank_mach0_n_162 : STD_LOGIC;
  signal bank_mach0_n_163 : STD_LOGIC;
  signal bank_mach0_n_164 : STD_LOGIC;
  signal bank_mach0_n_257 : STD_LOGIC;
  signal bank_mach0_n_258 : STD_LOGIC;
  signal bank_mach0_n_259 : STD_LOGIC;
  signal bank_mach0_n_260 : STD_LOGIC;
  signal bank_mach0_n_261 : STD_LOGIC;
  signal bank_mach0_n_262 : STD_LOGIC;
  signal bank_mach0_n_263 : STD_LOGIC;
  signal bank_mach0_n_264 : STD_LOGIC;
  signal bank_mach0_n_265 : STD_LOGIC;
  signal bank_mach0_n_266 : STD_LOGIC;
  signal bank_mach0_n_267 : STD_LOGIC;
  signal bank_mach0_n_274 : STD_LOGIC;
  signal bank_mach0_n_275 : STD_LOGIC;
  signal bank_mach0_n_276 : STD_LOGIC;
  signal bank_mach0_n_277 : STD_LOGIC;
  signal bank_mach0_n_278 : STD_LOGIC;
  signal bank_mach0_n_58 : STD_LOGIC;
  signal bank_mach0_n_59 : STD_LOGIC;
  signal bank_mach0_n_91 : STD_LOGIC;
  signal bank_mach0_n_92 : STD_LOGIC;
  signal bank_mach0_n_93 : STD_LOGIC;
  signal bank_mach0_n_94 : STD_LOGIC;
  signal bank_mach0_n_96 : STD_LOGIC;
  signal bank_mach0_n_98 : STD_LOGIC;
  signal clear_periodic_rd_request : STD_LOGIC;
  signal \cmd_pipe_plus.mc_aux_out0_reg_n_0_[1]\ : STD_LOGIC;
  signal col_mach0_n_12 : STD_LOGIC;
  signal col_mach0_n_7 : STD_LOGIC;
  signal col_periodic_rd : STD_LOGIC;
  signal col_rd_wr : STD_LOGIC;
  signal col_rd_wr_r1 : STD_LOGIC;
  signal col_rd_wr_r2 : STD_LOGIC;
  signal col_wr_data_buf_addr : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \^generate_maint_cmds.insert_maint_r_lcl_reg\ : STD_LOGIC;
  signal head_r : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \i___0_n_0\ : STD_LOGIC;
  signal \i___12_n_0\ : STD_LOGIC;
  signal \i___13_n_0\ : STD_LOGIC;
  signal \i___14_n_0\ : STD_LOGIC;
  signal \i___15_n_0\ : STD_LOGIC;
  signal \i___16_n_0\ : STD_LOGIC;
  signal \i___17_n_0\ : STD_LOGIC;
  signal \i___18_n_0\ : STD_LOGIC;
  signal \i___19_n_0\ : STD_LOGIC;
  signal \i___1_n_0\ : STD_LOGIC;
  signal \i___20_n_0\ : STD_LOGIC;
  signal \i___21_n_0\ : STD_LOGIC;
  signal \i___22_n_0\ : STD_LOGIC;
  signal \i___23_n_0\ : STD_LOGIC;
  signal \i___24_n_0\ : STD_LOGIC;
  signal \i___25_n_0\ : STD_LOGIC;
  signal \i___26_n_0\ : STD_LOGIC;
  signal \i___27_n_0\ : STD_LOGIC;
  signal \i___28_n_0\ : STD_LOGIC;
  signal \i___29_n_0\ : STD_LOGIC;
  signal \i___2_n_0\ : STD_LOGIC;
  signal \i___30_n_0\ : STD_LOGIC;
  signal \i___31_n_0\ : STD_LOGIC;
  signal \i___32_n_0\ : STD_LOGIC;
  signal \i___33_n_0\ : STD_LOGIC;
  signal \i___34_n_0\ : STD_LOGIC;
  signal \i___35_n_0\ : STD_LOGIC;
  signal \i___36_n_0\ : STD_LOGIC;
  signal \i___37_n_0\ : STD_LOGIC;
  signal \i___38_n_0\ : STD_LOGIC;
  signal \i___39_n_0\ : STD_LOGIC;
  signal \i___3_n_0\ : STD_LOGIC;
  signal \i___40_n_0\ : STD_LOGIC;
  signal \i___41_n_0\ : STD_LOGIC;
  signal \i___42_n_0\ : STD_LOGIC;
  signal \i___43_n_0\ : STD_LOGIC;
  signal \i___44_n_0\ : STD_LOGIC;
  signal \i___45_n_0\ : STD_LOGIC;
  signal \i___46_n_0\ : STD_LOGIC;
  signal \i___47_n_0\ : STD_LOGIC;
  signal \i___48_n_0\ : STD_LOGIC;
  signal \i___49_n_0\ : STD_LOGIC;
  signal \i___4_n_0\ : STD_LOGIC;
  signal \i___50_n_0\ : STD_LOGIC;
  signal \i___51_n_0\ : STD_LOGIC;
  signal \i___52_n_0\ : STD_LOGIC;
  signal \i___53_n_0\ : STD_LOGIC;
  signal \i___54_n_0\ : STD_LOGIC;
  signal \i___55_n_0\ : STD_LOGIC;
  signal \i___56_n_0\ : STD_LOGIC;
  signal \i___57_n_0\ : STD_LOGIC;
  signal \i___58_n_0\ : STD_LOGIC;
  signal \i___59_n_0\ : STD_LOGIC;
  signal \i___5_n_0\ : STD_LOGIC;
  signal \i___60_n_0\ : STD_LOGIC;
  signal \i___61_n_0\ : STD_LOGIC;
  signal \i___62_n_0\ : STD_LOGIC;
  signal \i___63_n_0\ : STD_LOGIC;
  signal \i___64_n_0\ : STD_LOGIC;
  signal \i___65_n_0\ : STD_LOGIC;
  signal \i___66_n_0\ : STD_LOGIC;
  signal \i___67_n_0\ : STD_LOGIC;
  signal \i___68_n_0\ : STD_LOGIC;
  signal \i___69_n_0\ : STD_LOGIC;
  signal \i___6_n_0\ : STD_LOGIC;
  signal \i___70_n_0\ : STD_LOGIC;
  signal \i___71_n_0\ : STD_LOGIC;
  signal \i___72_n_0\ : STD_LOGIC;
  signal \i___73_n_0\ : STD_LOGIC;
  signal \i___74_n_0\ : STD_LOGIC;
  signal \i___75_n_0\ : STD_LOGIC;
  signal \i___76_n_0\ : STD_LOGIC;
  signal \i___77_n_0\ : STD_LOGIC;
  signal \i___78_n_0\ : STD_LOGIC;
  signal \i___79_n_0\ : STD_LOGIC;
  signal \i___7_n_0\ : STD_LOGIC;
  signal \i___80_n_0\ : STD_LOGIC;
  signal \i___81_n_0\ : STD_LOGIC;
  signal \i___82_n_0\ : STD_LOGIC;
  signal \i___83_n_0\ : STD_LOGIC;
  signal \i___84_n_0\ : STD_LOGIC;
  signal \i___85_n_0\ : STD_LOGIC;
  signal \i___86_n_0\ : STD_LOGIC;
  signal \i___87_n_0\ : STD_LOGIC;
  signal \i___88_n_0\ : STD_LOGIC;
  signal \i___89_n_0\ : STD_LOGIC;
  signal \i___8_n_0\ : STD_LOGIC;
  signal \i___90_n_0\ : STD_LOGIC;
  signal \i___91_n_0\ : STD_LOGIC;
  signal \i___92_n_0\ : STD_LOGIC;
  signal \i___93_n_0\ : STD_LOGIC;
  signal \i___94_n_0\ : STD_LOGIC;
  signal \i___95_n_0\ : STD_LOGIC;
  signal \i___9_n_0\ : STD_LOGIC;
  signal \i__n_0\ : STD_LOGIC;
  signal idle_r : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \inhbt_act_faw.faw_cnt_r\ : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal inhbt_act_faw_r : STD_LOGIC;
  signal insert_maint_r1 : STD_LOGIC;
  signal maint_ref_zq_wip : STD_LOGIC;
  signal maint_req_r : STD_LOGIC;
  signal maint_sre_r : STD_LOGIC;
  signal maint_srx_r : STD_LOGIC;
  signal maint_wip_r : STD_LOGIC;
  signal maint_zq_r : STD_LOGIC;
  signal mc_address_ns : STD_LOGIC_VECTOR ( 41 downto 0 );
  signal mc_bank_ns : STD_LOGIC_VECTOR ( 8 downto 0 );
  signal \^mc_cas_n\ : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal mc_cas_n_ns : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal mc_cke_ns : STD_LOGIC_VECTOR ( 1 to 1 );
  signal \^mc_cmd\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal mc_cmd_ns : STD_LOGIC_VECTOR ( 1 to 1 );
  signal \^mc_cs_n\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal mc_cs_n_ns : STD_LOGIC_VECTOR ( 0 to 0 );
  signal mc_data_offset_1_ns : STD_LOGIC_VECTOR ( 3 to 3 );
  signal mc_data_offset_2_ns : STD_LOGIC_VECTOR ( 3 to 3 );
  signal mc_data_offset_ns : STD_LOGIC_VECTOR ( 3 to 3 );
  signal mc_odt_ns : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \^mc_ras_n\ : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal mc_ras_n_ns : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal mc_ref_zq_wip_ns : STD_LOGIC;
  signal \^mc_we_n\ : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal mc_we_n_ns : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal mc_wrdata_en_ns : STD_LOGIC;
  signal p_130_out : STD_LOGIC;
  signal p_52_out : STD_LOGIC;
  signal periodic_rd_ack_r : STD_LOGIC;
  signal periodic_rd_r : STD_LOGIC;
  signal q_entry_r : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \rank_cntrl[0].rank_cntrl0/act_this_rank\ : STD_LOGIC;
  signal \rank_cntrl[0].rank_cntrl0/inhbt_act_faw.act_delayed\ : STD_LOGIC;
  signal \rank_cntrl[0].rank_cntrl0/periodic_rd_generation.periodic_rd_cntr1_r\ : STD_LOGIC;
  signal \rank_cntrl[0].rank_cntrl0/periodic_rd_generation.periodic_rd_request_r\ : STD_LOGIC;
  signal \rank_cntrl[0].rank_cntrl0/periodic_rd_generation.read_this_rank\ : STD_LOGIC;
  signal \rank_cntrl[0].rank_cntrl0/periodic_rd_generation.read_this_rank_r\ : STD_LOGIC;
  signal \rank_cntrl[0].rank_cntrl0/refresh_generation.refresh_bank_r\ : STD_LOGIC;
  signal \rank_cntrl[0].rank_cntrl0/rtw_timer.rtw_cnt_ns\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \rank_common0/app_ref_r\ : STD_LOGIC;
  signal \rank_common0/app_zq_r\ : STD_LOGIC;
  signal \rank_common0/maint_prescaler.maint_prescaler_r_reg\ : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal \rank_common0/maintenance_request.maint_arb0/last_master_r\ : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal \rank_common0/maintenance_request.maint_grant_r\ : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal \rank_common0/maintenance_request.new_maint_rank_r\ : STD_LOGIC;
  signal \rank_common0/maintenance_request.upd_last_master_r\ : STD_LOGIC;
  signal \rank_common0/periodic_read_request.periodic_rd_grant_r\ : STD_LOGIC;
  signal \rank_common0/periodic_read_request.periodic_rd_r_cnt\ : STD_LOGIC;
  signal \rank_common0/periodic_read_request.upd_last_master_r\ : STD_LOGIC;
  signal \rank_common0/refresh_timer.refresh_timer_r_reg\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \rank_common0/sr_cntrl.sre_request_logic.sre_request_r\ : STD_LOGIC;
  signal \rank_common0/zq_cntrl.zq_request_logic.zq_request_r\ : STD_LOGIC;
  signal rank_mach0_n_29 : STD_LOGIC;
  signal rank_mach0_n_32 : STD_LOGIC;
  signal rank_mach0_n_40 : STD_LOGIC;
  signal rank_mach0_n_41 : STD_LOGIC;
  signal rank_mach0_n_42 : STD_LOGIC;
  signal rank_mach0_n_43 : STD_LOGIC;
  signal rank_mach0_n_44 : STD_LOGIC;
  signal rank_mach0_n_45 : STD_LOGIC;
  signal rank_mach0_n_46 : STD_LOGIC;
  signal rank_mach0_n_47 : STD_LOGIC;
  signal rank_mach0_n_48 : STD_LOGIC;
  signal rank_mach0_n_49 : STD_LOGIC;
  signal rank_mach0_n_50 : STD_LOGIC;
  signal rank_mach0_n_51 : STD_LOGIC;
  signal rank_mach0_n_52 : STD_LOGIC;
  signal rank_mach0_n_53 : STD_LOGIC;
  signal rank_mach0_n_54 : STD_LOGIC;
  signal rank_mach0_n_55 : STD_LOGIC;
  signal rank_mach0_n_56 : STD_LOGIC;
  signal rank_mach0_n_57 : STD_LOGIC;
  signal rank_mach0_n_58 : STD_LOGIC;
  signal rank_mach0_n_59 : STD_LOGIC;
  signal rank_mach0_n_63 : STD_LOGIC;
  signal rank_mach0_n_64 : STD_LOGIC;
  signal rb_hit_busy_r : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal rd_wr_r : STD_LOGIC_VECTOR ( 3 downto 1 );
  signal \read_fifo.tail_r\ : STD_LOGIC_VECTOR ( 2 downto 1 );
  signal \^read_fifo.tail_r_reg[0]\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal req_wr_r : STD_LOGIC_VECTOR ( 3 downto 1 );
  signal \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_ns\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal rnk_config_valid_r : STD_LOGIC;
  signal row_cmd_wr : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \rtw_timer.rtw_cnt_r\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal sending_col : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal sending_pre : STD_LOGIC_VECTOR ( 3 to 3 );
  signal sending_row : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal sent_col : STD_LOGIC;
  signal sent_col_r2 : STD_LOGIC;
  signal sent_row : STD_LOGIC;
  signal was_wr : STD_LOGIC;
  signal wr_data_addr_ns : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \^wr_data_en\ : STD_LOGIC;
  signal wr_data_en_ns : STD_LOGIC;
  signal \wtr_timer.wtr_cnt_r\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \zq_cntrl.zq_timer.zq_timer_r_reg[0]_i_3_n_0\ : STD_LOGIC;
  signal \zq_cntrl.zq_timer.zq_timer_r_reg[0]_i_3_n_1\ : STD_LOGIC;
  signal \zq_cntrl.zq_timer.zq_timer_r_reg[0]_i_3_n_2\ : STD_LOGIC;
  signal \zq_cntrl.zq_timer.zq_timer_r_reg[0]_i_3_n_3\ : STD_LOGIC;
  signal \zq_cntrl.zq_timer.zq_timer_r_reg[0]_i_3_n_4\ : STD_LOGIC;
  signal \zq_cntrl.zq_timer.zq_timer_r_reg[0]_i_3_n_5\ : STD_LOGIC;
  signal \zq_cntrl.zq_timer.zq_timer_r_reg[0]_i_3_n_6\ : STD_LOGIC;
  signal \zq_cntrl.zq_timer.zq_timer_r_reg[0]_i_3_n_7\ : STD_LOGIC;
  signal \zq_cntrl.zq_timer.zq_timer_r_reg[12]_i_1_n_0\ : STD_LOGIC;
  signal \zq_cntrl.zq_timer.zq_timer_r_reg[12]_i_1_n_1\ : STD_LOGIC;
  signal \zq_cntrl.zq_timer.zq_timer_r_reg[12]_i_1_n_2\ : STD_LOGIC;
  signal \zq_cntrl.zq_timer.zq_timer_r_reg[12]_i_1_n_3\ : STD_LOGIC;
  signal \zq_cntrl.zq_timer.zq_timer_r_reg[12]_i_1_n_4\ : STD_LOGIC;
  signal \zq_cntrl.zq_timer.zq_timer_r_reg[12]_i_1_n_5\ : STD_LOGIC;
  signal \zq_cntrl.zq_timer.zq_timer_r_reg[12]_i_1_n_6\ : STD_LOGIC;
  signal \zq_cntrl.zq_timer.zq_timer_r_reg[12]_i_1_n_7\ : STD_LOGIC;
  signal \zq_cntrl.zq_timer.zq_timer_r_reg[16]_i_1_n_1\ : STD_LOGIC;
  signal \zq_cntrl.zq_timer.zq_timer_r_reg[16]_i_1_n_2\ : STD_LOGIC;
  signal \zq_cntrl.zq_timer.zq_timer_r_reg[16]_i_1_n_3\ : STD_LOGIC;
  signal \zq_cntrl.zq_timer.zq_timer_r_reg[16]_i_1_n_4\ : STD_LOGIC;
  signal \zq_cntrl.zq_timer.zq_timer_r_reg[16]_i_1_n_5\ : STD_LOGIC;
  signal \zq_cntrl.zq_timer.zq_timer_r_reg[16]_i_1_n_6\ : STD_LOGIC;
  signal \zq_cntrl.zq_timer.zq_timer_r_reg[16]_i_1_n_7\ : STD_LOGIC;
  signal \zq_cntrl.zq_timer.zq_timer_r_reg[4]_i_1_n_0\ : STD_LOGIC;
  signal \zq_cntrl.zq_timer.zq_timer_r_reg[4]_i_1_n_1\ : STD_LOGIC;
  signal \zq_cntrl.zq_timer.zq_timer_r_reg[4]_i_1_n_2\ : STD_LOGIC;
  signal \zq_cntrl.zq_timer.zq_timer_r_reg[4]_i_1_n_3\ : STD_LOGIC;
  signal \zq_cntrl.zq_timer.zq_timer_r_reg[4]_i_1_n_4\ : STD_LOGIC;
  signal \zq_cntrl.zq_timer.zq_timer_r_reg[4]_i_1_n_5\ : STD_LOGIC;
  signal \zq_cntrl.zq_timer.zq_timer_r_reg[4]_i_1_n_6\ : STD_LOGIC;
  signal \zq_cntrl.zq_timer.zq_timer_r_reg[4]_i_1_n_7\ : STD_LOGIC;
  signal \zq_cntrl.zq_timer.zq_timer_r_reg[8]_i_1_n_0\ : STD_LOGIC;
  signal \zq_cntrl.zq_timer.zq_timer_r_reg[8]_i_1_n_1\ : STD_LOGIC;
  signal \zq_cntrl.zq_timer.zq_timer_r_reg[8]_i_1_n_2\ : STD_LOGIC;
  signal \zq_cntrl.zq_timer.zq_timer_r_reg[8]_i_1_n_3\ : STD_LOGIC;
  signal \zq_cntrl.zq_timer.zq_timer_r_reg[8]_i_1_n_4\ : STD_LOGIC;
  signal \zq_cntrl.zq_timer.zq_timer_r_reg[8]_i_1_n_5\ : STD_LOGIC;
  signal \zq_cntrl.zq_timer.zq_timer_r_reg[8]_i_1_n_6\ : STD_LOGIC;
  signal \zq_cntrl.zq_timer.zq_timer_r_reg[8]_i_1_n_7\ : STD_LOGIC;
  signal \NLW_zq_cntrl.zq_timer.zq_timer_r_reg[16]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
  attribute syn_maxfan : string;
  attribute syn_maxfan of \cmd_pipe_plus.wr_data_addr_reg[0]\ : label is "30";
  attribute syn_maxfan of \cmd_pipe_plus.wr_data_addr_reg[1]\ : label is "30";
  attribute syn_maxfan of \cmd_pipe_plus.wr_data_addr_reg[2]\ : label is "30";
  attribute syn_maxfan of \cmd_pipe_plus.wr_data_addr_reg[3]\ : label is "30";
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \i___31\ : label is "soft_lutpair1212";
  attribute SOFT_HLUTNM of \i___50\ : label is "soft_lutpair1212";
  attribute SOFT_HLUTNM of \i___57\ : label is "soft_lutpair1208";
  attribute SOFT_HLUTNM of \i___58\ : label is "soft_lutpair1209";
  attribute SOFT_HLUTNM of \i___59\ : label is "soft_lutpair1209";
  attribute SOFT_HLUTNM of \i___67\ : label is "soft_lutpair1207";
  attribute SOFT_HLUTNM of \i___68\ : label is "soft_lutpair1207";
  attribute SOFT_HLUTNM of \i___71\ : label is "soft_lutpair1210";
  attribute SOFT_HLUTNM of \i___72\ : label is "soft_lutpair1210";
  attribute SOFT_HLUTNM of \i___76\ : label is "soft_lutpair1208";
  attribute SOFT_HLUTNM of \i___79\ : label is "soft_lutpair1206";
  attribute SOFT_HLUTNM of \i___80\ : label is "soft_lutpair1206";
  attribute SOFT_HLUTNM of \i___82\ : label is "soft_lutpair1211";
  attribute SOFT_HLUTNM of \i___83\ : label is "soft_lutpair1211";
begin
  Q(38 downto 0) <= \^q\(38 downto 0);
  app_sr_active <= \^app_sr_active\;
  \generate_maint_cmds.insert_maint_r_lcl_reg\ <= \^generate_maint_cmds.insert_maint_r_lcl_reg\;
  mc_cas_n(2 downto 0) <= \^mc_cas_n\(2 downto 0);
  mc_cmd(1 downto 0) <= \^mc_cmd\(1 downto 0);
  mc_cs_n(0) <= \^mc_cs_n\(0);
  mc_ras_n(2 downto 0) <= \^mc_ras_n\(2 downto 0);
  mc_we_n(2 downto 0) <= \^mc_we_n\(2 downto 0);
  \read_fifo.tail_r_reg[0]\(0) <= \^read_fifo.tail_r_reg[0]\(0);
  wr_data_en <= \^wr_data_en\;
bank_mach0: entity work.mig_mig_7series_v4_2_bank_mach
     port map (
      D(0) => mc_data_offset_2_ns(3),
      DIC(0) => col_periodic_rd,
      E(0) => mc_cmd_ns(1),
      Q(3 downto 0) => sending_col(3 downto 0),
      S(2 downto 0) => S(2 downto 0),
      SR(0) => SR(0),
      accept_internal_r => accept_internal_r,
      accept_internal_r_reg => \grant_r_reg[0]\,
      accept_ns => accept_ns,
      accept_r_reg => bank_mach0_n_10,
      act_this_rank => \rank_cntrl[0].rank_cntrl0/act_this_rank\,
      act_wait_r_lcl_reg => bank_mach0_n_257,
      act_wait_r_lcl_reg_0 => bank_mach0_n_263,
      act_wait_r_lcl_reg_1 => bank_mach0_n_266,
      act_wait_r_lcl_reg_2 => \i___27_n_0\,
      auto_pre_r => \bank_cntrl[0].bank0/auto_pre_r\,
      auto_pre_r_19 => \bank_cntrl[1].bank0/auto_pre_r\,
      auto_pre_r_20 => \bank_cntrl[2].bank0/auto_pre_r\,
      auto_pre_r_21 => \bank_cntrl[3].bank0/auto_pre_r\,
      auto_pre_r_lcl_reg => \i___55_n_0\,
      auto_pre_r_lcl_reg_0 => \i___61_n_0\,
      auto_pre_r_lcl_reg_1 => \i___62_n_0\,
      auto_pre_r_lcl_reg_2 => \i___63_n_0\,
      auto_pre_r_lcl_reg_3 => \i___64_n_0\,
      bm_end_r1 => bm_end_r1,
      bm_end_r1_0 => bm_end_r1_0,
      bm_end_r1_1 => bm_end_r1_1,
      cke_r => \arb_mux0/arb_select0/cke_r\,
      cke_r_reg => \periodic_read_request.periodic_rd_r_cnt_reg\,
      clear_periodic_rd_request => clear_periodic_rd_request,
      cmd(1 downto 0) => cmd(1 downto 0),
      \cmd_pipe_plus.mc_address_reg[0]\ => \i___68_n_0\,
      \cmd_pipe_plus.mc_address_reg[0]_0\ => \i___67_n_0\,
      \cmd_pipe_plus.mc_address_reg[3]\ => \i___69_n_0\,
      \cmd_pipe_plus.mc_data_offset_1_reg[5]\(5 downto 0) => \cmd_pipe_plus.mc_data_offset_1_reg[5]_1\(5 downto 0),
      \cmd_pipe_plus.mc_data_offset_2_reg[5]\(5 downto 0) => \cmd_pipe_plus.mc_data_offset_2_reg[5]_1\(5 downto 0),
      \cmd_pipe_plus.mc_data_offset_reg[5]\(5 downto 0) => \cmd_pipe_plus.mc_data_offset_reg[5]_1\(5 downto 0),
      \cmd_pipe_plus.mc_odt_reg[0]\ => \cmd_pipe_plus.mc_aux_out0_reg_n_0_[1]\,
      \cmd_pipe_plus.mc_we_n_reg[0]\ => \i___66_n_0\,
      col_rd_wr => col_rd_wr,
      col_wait_r => \bank_cntrl[0].bank0/bank_state0/col_wait_r\,
      col_wait_r_0 => \bank_cntrl[1].bank0/bank_state0/col_wait_r\,
      col_wait_r_4 => \bank_cntrl[2].bank0/bank_state0/col_wait_r\,
      col_wait_r_8 => \bank_cntrl[3].bank0/bank_state0/col_wait_r\,
      col_wait_r_reg => \i___26_n_0\,
      col_wait_r_reg_0 => \i___49_n_0\,
      col_wait_r_reg_1 => \i___30_n_0\,
      col_wait_r_reg_2 => \i___25_n_0\,
      col_wr_data_buf_addr(3 downto 0) => col_wr_data_buf_addr(3 downto 0),
      \compute_tail.tail_r_lcl_reg\ => bank_mach0_n_258,
      \compute_tail.tail_r_lcl_reg_0\ => bank_mach0_n_259,
      \compute_tail.tail_r_lcl_reg_1\ => bank_mach0_n_261,
      \compute_tail.tail_r_lcl_reg_2\ => bank_mach0_n_262,
      \compute_tail.tail_r_lcl_reg_3\ => \i___2_n_0\,
      \compute_tail.tail_r_lcl_reg_4\ => \i___7_n_0\,
      \compute_tail.tail_r_lcl_reg_5\ => \i___8_n_0\,
      \compute_tail.tail_r_lcl_reg_6\ => \i___9_n_0\,
      cs_en2 => \arb_mux0/cs_en2\,
      \delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r_reg[3]\(3 downto 0) => wr_data_addr_ns(3 downto 0),
      demand_priority_r => \bank_cntrl[0].bank0/bank_state0/demand_priority_r\,
      demand_priority_r_1 => \bank_cntrl[1].bank0/bank_state0/demand_priority_r\,
      demand_priority_r_5 => \bank_cntrl[2].bank0/bank_state0/demand_priority_r\,
      demand_priority_r_9 => \bank_cntrl[3].bank0/bank_state0/demand_priority_r\,
      demand_priority_r_reg => bank_mach0_n_150,
      demanded_prior_r => \bank_cntrl[0].bank0/bank_state0/demanded_prior_r\,
      demanded_prior_r_2 => \bank_cntrl[1].bank0/bank_state0/demanded_prior_r\,
      demanded_prior_r_6 => \bank_cntrl[2].bank0/bank_state0/demanded_prior_r\,
      demanded_prior_r_reg => bank_mach0_n_265,
      demanded_prior_r_reg_0 => bank_mach0_n_277,
      \generate_maint_cmds.insert_maint_r_lcl_reg\ => \^generate_maint_cmds.insert_maint_r_lcl_reg\,
      \grant_r[2]_i_3\(0) => \wtr_timer.wtr_cnt_r\(1),
      \grant_r_reg[0]\ => bank_mach0_n_113,
      \grant_r_reg[0]_0\ => bank_mach0_n_267,
      \grant_r_reg[0]_1\ => bank_mach0_n_274,
      \grant_r_reg[0]_2\ => bank_mach0_n_278,
      \grant_r_reg[1]\ => bank_mach0_n_264,
      \grant_r_reg[2]\ => bank_mach0_n_92,
      \grant_r_reg[3]\(3 downto 0) => sending_row(3 downto 0),
      \grant_r_reg[3]_0\(0) => sending_pre(3),
      \grant_r_reg[3]_1\ => \i___74_n_0\,
      \grant_r_reg[3]_2\ => \i___73_n_0\,
      \grant_r_reg[3]_3\ => \i___75_n_0\,
      granted_col_r_reg => bank_mach0_n_91,
      granted_col_r_reg_0(0) => mc_data_offset_1_ns(3),
      granted_col_r_reg_1(0) => mc_data_offset_ns(3),
      granted_col_r_reg_2 => \i___84_n_0\,
      granted_col_r_reg_3 => \i___29_n_0\,
      granted_col_r_reg_4 => \i___86_n_0\,
      granted_col_r_reg_5 => \i___85_n_0\,
      granted_col_r_reg_6 => \i___28_n_0\,
      granted_row_r_reg => \i___70_n_0\,
      head_r(3 downto 0) => head_r(3 downto 0),
      head_r_lcl_reg => \i___3_n_0\,
      head_r_lcl_reg_0 => \i___4_n_0\,
      head_r_lcl_reg_1 => \i___5_n_0\,
      head_r_lcl_reg_2 => \i___6_n_0\,
      idle_r(3 downto 0) => idle_r(3 downto 0),
      idle_r_lcl_reg => bank_mach0_n_93,
      idle_r_lcl_reg_0 => bank_mach0_n_94,
      idle_r_lcl_reg_1 => bank_mach0_n_96,
      idle_r_lcl_reg_2 => bank_mach0_n_98,
      idle_r_lcl_reg_3 => bank_mach0_n_143,
      idle_r_lcl_reg_4 => bank_mach0_n_147,
      idle_r_lcl_reg_5 => bank_mach0_n_260,
      inhbt_act_faw_r => inhbt_act_faw_r,
      insert_maint_r1 => insert_maint_r1,
      \last_master_r_reg[3]\(0) => \arb_mux0/arb_row_col0/pre_4_1_1T_arb.pre_arb0/last_master_r\(3),
      \maint_controller.maint_hit_busies_r_reg[3]\(3 downto 0) => \bank_common0/maint_controller.maint_hit_busies_r\(3 downto 0),
      \maint_controller.maint_hit_busies_r_reg[3]_0\(3) => \i___44_n_0\,
      \maint_controller.maint_hit_busies_r_reg[3]_0\(2) => \i___46_n_0\,
      \maint_controller.maint_hit_busies_r_reg[3]_0\(1) => \i___35_n_0\,
      \maint_controller.maint_hit_busies_r_reg[3]_0\(0) => \i___48_n_0\,
      \maint_controller.maint_wip_r_lcl_reg\ => \last_master_r_reg[2]\,
      \maint_controller.maint_wip_r_lcl_reg_0\ => \i___65_n_0\,
      \maint_controller.maint_wip_r_lcl_reg_1\ => \i___82_n_0\,
      maint_req_r => maint_req_r,
      maint_srx_r => maint_srx_r,
      maint_wip_r => maint_wip_r,
      maint_zq_r => maint_zq_r,
      mc_cas_n_ns(2 downto 0) => mc_cas_n_ns(2 downto 0),
      mc_cke_ns(0) => mc_cke_ns(1),
      mc_cs_n_ns(0) => mc_cs_n_ns(0),
      mc_odt_ns(0) => mc_odt_ns(0),
      mc_ras_n_ns(1) => mc_ras_n_ns(2),
      mc_ras_n_ns(0) => mc_ras_n_ns(0),
      mc_we_n_ns(1) => mc_we_n_ns(2),
      mc_we_n_ns(0) => mc_we_n_ns(0),
      of_ctl_full_v(0) => of_ctl_full_v(0),
      ofs_rdy_r_reg => \zq_cntrl.zq_request_logic.zq_request_r_reg\,
      \order_q_r_reg[1]\ => bank_mach0_n_152,
      override_demand_ns => \bank_cntrl[2].bank0/bank_state0/override_demand_ns\,
      override_demand_r => \bank_cntrl[2].bank0/bank_state0/override_demand_r\,
      p_130_out => p_130_out,
      p_52_out => p_52_out,
      pass_open_bank_r => \bank_cntrl[1].bank0/pass_open_bank_r\,
      pass_open_bank_r_10 => \bank_cntrl[3].bank0/pass_open_bank_r\,
      pass_open_bank_r_lcl_reg => bank_mach0_n_58,
      pass_open_bank_r_lcl_reg_0 => bank_mach0_n_59,
      pass_open_bank_r_lcl_reg_1 => \i___72_n_0\,
      pass_open_bank_r_lcl_reg_2 => \i___71_n_0\,
      periodic_rd_ack_r => periodic_rd_ack_r,
      periodic_rd_ack_r_lcl_reg => bank_mach0_n_133,
      periodic_rd_cntr_r => \bank_common0/periodic_rd_cntr_r\,
      periodic_rd_cntr_r_reg => \periodic_rd_generation.periodic_rd_cntr1_r_reg\,
      periodic_rd_cntr_r_reg_0 => \i___58_n_0\,
      \periodic_rd_generation.read_this_rank\ => \rank_cntrl[0].rank_cntrl0/periodic_rd_generation.read_this_rank\,
      \periodic_rd_generation.read_this_rank_r\ => \rank_cntrl[0].rank_cntrl0/periodic_rd_generation.read_this_rank_r\,
      \periodic_rd_generation.read_this_rank_r_reg\ => bank_mach0_n_104,
      periodic_rd_r => periodic_rd_r,
      \periodic_read_request.periodic_rd_grant_r\ => \rank_common0/periodic_read_request.periodic_rd_grant_r\,
      phy_mc_ctl_full => phy_mc_ctl_full,
      phy_mc_data_full => phy_mc_data_full,
      \pre_4_1_1T_arb.granted_pre_r_reg\(8 downto 0) => mc_bank_ns(8 downto 0),
      \pre_4_1_1T_arb.granted_pre_r_reg_0\(38 downto 25) => mc_address_ns(41 downto 28),
      \pre_4_1_1T_arb.granted_pre_r_reg_0\(24 downto 0) => mc_address_ns(24 downto 0),
      pre_bm_end_r => \bank_cntrl[1].bank0/bank_queue0/pre_bm_end_r\,
      pre_bm_end_r_11 => \bank_cntrl[3].bank0/bank_queue0/pre_bm_end_r\,
      pre_bm_end_r_reg => bank_mach0_n_117,
      pre_bm_end_r_reg_0 => bank_mach0_n_128,
      pre_bm_end_r_reg_1 => bank_mach0_n_129,
      pre_bm_end_r_reg_2 => bank_mach0_n_149,
      pre_passing_open_bank_r_reg => bank_mach0_n_122,
      pre_passing_open_bank_r_reg_0 => bank_mach0_n_125,
      q_entry_r(1 downto 0) => q_entry_r(1 downto 0),
      \q_entry_r_reg[0]\ => bank_mach0_n_132,
      \q_entry_r_reg[0]_0\ => bank_mach0_n_138,
      \q_entry_r_reg[0]_1\ => bank_mach0_n_141,
      \q_entry_r_reg[0]_2\ => bank_mach0_n_142,
      \q_entry_r_reg[0]_3\ => bank_mach0_n_144,
      \q_entry_r_reg[0]_4\ => bank_mach0_n_155,
      \q_entry_r_reg[0]_5\ => bank_mach0_n_156,
      \q_entry_r_reg[0]_6\ => \i___33_n_0\,
      \q_entry_r_reg[1]\ => bank_mach0_n_131,
      \q_entry_r_reg[1]_0\ => bank_mach0_n_140,
      \q_entry_r_reg[1]_1\ => bank_mach0_n_157,
      \q_entry_r_reg[1]_2\ => \i___38_n_0\,
      \q_entry_r_reg[1]_3\ => \i___34_n_0\,
      \q_entry_r_reg[1]_4\ => \i___39_n_0\,
      q_has_rd => \bank_cntrl[0].bank0/q_has_rd\,
      q_has_rd_12 => \bank_cntrl[3].bank0/q_has_rd\,
      q_has_rd_3 => \bank_cntrl[1].bank0/q_has_rd\,
      q_has_rd_7 => \bank_cntrl[2].bank0/q_has_rd\,
      q_has_rd_r_reg => \i___51_n_0\,
      q_has_rd_r_reg_0 => \i___36_n_0\,
      q_has_rd_r_reg_1 => \i___52_n_0\,
      q_has_rd_r_reg_2 => \i___54_n_0\,
      \rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][5]\(3 downto 2) => \arb_mux0/arb_select0/mc_data_offset1\(5 downto 4),
      \rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][5]\(1 downto 0) => \arb_mux0/arb_select0/mc_data_offset1\(2 downto 1),
      \rank_final_loop[0].bank_final_loop[1].final_data_offset_mc_reg[0][11]\(3 downto 2) => \arb_mux0/arb_select0/mc_data_offset_11\(5 downto 4),
      \rank_final_loop[0].bank_final_loop[1].final_data_offset_mc_reg[0][11]\(1 downto 0) => \arb_mux0/arb_select0/mc_data_offset_11\(2 downto 1),
      \rank_final_loop[0].bank_final_loop[2].final_data_offset_mc_reg[0][17]\(3 downto 2) => \arb_mux0/arb_select0/mc_data_offset_21\(5 downto 4),
      \rank_final_loop[0].bank_final_loop[2].final_data_offset_mc_reg[0][17]\(1 downto 0) => \arb_mux0/arb_select0/mc_data_offset_21\(2 downto 1),
      \ras_timer_r_reg[0]\ => \i___89_n_0\,
      \ras_timer_r_reg[0]_0\ => \i___88_n_0\,
      \ras_timer_r_reg[0]_1\ => \i___87_n_0\,
      \ras_timer_r_reg[0]_2\ => \i___90_n_0\,
      ras_timer_zero_r_reg => ras_timer_zero_r_reg,
      ras_timer_zero_r_reg_0 => ras_timer_zero_r_reg_0,
      ras_timer_zero_r_reg_1 => ras_timer_zero_r_reg_1,
      \rb_hit_busies.rb_hit_busies_r_lcl_reg[1]\(0) => \bank_cntrl[0].bank0/rb_hit_busies_r\(1),
      \rb_hit_busies.rb_hit_busies_r_lcl_reg[2]\ => bank_mach0_n_123,
      \rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_0\ => bank_mach0_n_154,
      \rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_1\ => bank_mach0_n_158,
      \rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_2\ => bank_mach0_n_160,
      \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]\ => bank_mach0_n_124,
      \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_0\ => bank_mach0_n_126,
      \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_1\ => bank_mach0_n_163,
      \rb_hit_busies.rb_hit_busies_r_lcl_reg[4]\(0) => \bank_cntrl[2].bank0/rb_hit_busies_r\(4),
      \rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_0\ => bank_mach0_n_137,
      \rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_1\ => \rb_hit_busies.rb_hit_busies_r_lcl_reg[4]\,
      \rb_hit_busies.rb_hit_busies_r_lcl_reg[5]\ => bank_mach0_n_127,
      \rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_0\ => \i___37_n_0\,
      \rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_1\ => \rb_hit_busies.rb_hit_busies_r_lcl_reg[5]\,
      \rb_hit_busies.rb_hit_busies_r_lcl_reg[6]\ => bank_mach0_n_116,
      \rb_hit_busies.rb_hit_busies_r_lcl_reg[6]_0\ => \rb_hit_busies.rb_hit_busies_r_lcl_reg[6]\,
      rb_hit_busy_r(3 downto 0) => rb_hit_busy_r(3 downto 0),
      rb_hit_busy_r_reg => bank_mach0_n_135,
      rb_hit_busy_r_reg_0 => bank_mach0_n_161,
      rb_hit_busy_r_reg_1 => rb_hit_busy_r_reg,
      rd_wr_r_lcl_reg(2 downto 0) => rd_wr_r(3 downto 1),
      rd_wr_r_lcl_reg_0 => \i___59_n_0\,
      \req_bank_r_lcl_reg[2]\(2 downto 0) => \req_bank_r_lcl_reg[2]\(2 downto 0),
      \req_bank_r_lcl_reg[2]_0\(2 downto 0) => \req_bank_r_lcl_reg[2]_0\(2 downto 0),
      \req_bank_r_lcl_reg[2]_1\(2 downto 0) => \req_bank_r_lcl_reg[2]_1\(2 downto 0),
      \req_bank_r_lcl_reg[2]_2\(2 downto 0) => \req_bank_r_lcl_reg[2]_2\(2 downto 0),
      \req_bank_r_lcl_reg[2]_3\(2 downto 0) => \req_bank_r_lcl_reg[2]_3\(2 downto 0),
      req_bank_rdy_ns => \bank_cntrl[1].bank0/bank_state0/req_bank_rdy_ns\,
      req_bank_rdy_r_reg => \i___41_n_0\,
      req_bank_rdy_r_reg_0 => \i___53_n_0\,
      req_bank_rdy_r_reg_1 => \i___56_n_0\,
      \req_col_r_reg[9]\(9 downto 0) => \req_col_r_reg[9]\(9 downto 0),
      \req_data_buf_addr_r_reg[3]\(3 downto 0) => \req_data_buf_addr_r_reg[3]\(3 downto 0),
      \req_row_r_lcl_reg[13]\(19 downto 0) => \req_row_r_lcl_reg[13]\(19 downto 0),
      \req_row_r_lcl_reg[13]_0\(13 downto 0) => D(13 downto 0),
      req_wr_r_lcl_reg(2 downto 0) => req_wr_r(3 downto 1),
      \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[0]\ => \inhbt_act_faw.inhbt_act_faw_r_reg\,
      \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[1]\ => \last_master_r_reg[2]_0\,
      \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[3]\(3 downto 0) => \bank_common0/rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r\(3 downto 0),
      \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[3]_0\ => rank_mach0_n_63,
      \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[3]_1\ => \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[3]\,
      \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[4]\ => bank_mach0_n_275,
      \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[4]_0\ => \i___83_n_0\,
      \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[7]\ => bank_mach0_n_276,
      \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[7]_0\(1) => \i___60_n_0\,
      \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[7]_0\(0) => \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_ns\(0),
      rnk_config_valid_r => rnk_config_valid_r,
      rnk_config_valid_r_lcl_reg => bank_mach0_n_151,
      rnk_config_valid_r_lcl_reg_0 => \i___40_n_0\,
      row_cmd_wr(3 downto 0) => row_cmd_wr(3 downto 0),
      row_hit_r_reg => bank_mach0_n_136,
      row_hit_r_reg_0 => bank_mach0_n_159,
      row_hit_r_reg_1 => bank_mach0_n_162,
      row_hit_r_reg_2 => bank_mach0_n_164,
      row_hit_r_reg_3(0) => row_hit_r_reg(0),
      row_hit_r_reg_4(0) => row_hit_r_reg_0(0),
      row_hit_r_reg_5(0) => row_hit_r_reg_1(0),
      row_hit_r_reg_6(0) => row_hit_r_reg_2(0),
      row_hit_r_reg_7(0) => row_hit_r_reg_3(0),
      \rtp_timer_r_reg[0]\ => \rtp_timer_r_reg[0]\,
      \rtp_timer_r_reg[1]\ => \rtp_timer_r_reg[1]\,
      \rtw_timer.rtw_cnt_r_reg[1]\(1 downto 0) => \rank_cntrl[0].rank_cntrl0/rtw_timer.rtw_cnt_ns\(1 downto 0),
      \rtw_timer.rtw_cnt_r_reg[1]_0\(1 downto 0) => \rtw_timer.rtw_cnt_r\(1 downto 0),
      sent_col => sent_col,
      sent_row => sent_row,
      set_order_q => \bank_cntrl[3].bank0/bank_queue0/set_order_q\,
      set_order_q_22 => \bank_cntrl[2].bank0/bank_queue0/set_order_q\,
      set_order_q_23 => \bank_cntrl[0].bank0/bank_queue0/set_order_q\,
      set_order_q_24 => \bank_cntrl[1].bank0/bank_queue0/set_order_q\,
      tail_r => \bank_cntrl[0].bank0/tail_r\,
      tail_r_16 => \bank_cntrl[1].bank0/tail_r\,
      tail_r_17 => \bank_cntrl[2].bank0/tail_r\,
      tail_r_18 => \bank_cntrl[3].bank0/tail_r\,
      use_addr => use_addr,
      wait_for_maint_r => \bank_cntrl[0].bank0/wait_for_maint_r\,
      wait_for_maint_r_13 => \bank_cntrl[1].bank0/wait_for_maint_r\,
      wait_for_maint_r_14 => \bank_cntrl[2].bank0/wait_for_maint_r\,
      wait_for_maint_r_15 => \bank_cntrl[3].bank0/wait_for_maint_r\,
      wait_for_maint_r_lcl_reg => \i___47_n_0\,
      wait_for_maint_r_lcl_reg_0 => \i___42_n_0\,
      wait_for_maint_r_lcl_reg_1 => \i___45_n_0\,
      wait_for_maint_r_lcl_reg_2 => \i___43_n_0\,
      was_priority_reg => was_priority_reg,
      was_wr => was_wr,
      \wr_this_rank_r_reg[0]\ => bank_mach0_n_114,
      \wr_this_rank_r_reg[0]_0\ => bank_mach0_n_115
    );
\cmd_pipe_plus.mc_address_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \last_master_r_reg[2]\,
      CE => '1',
      D => mc_address_ns(0),
      Q => \^q\(0),
      R => '0'
    );
\cmd_pipe_plus.mc_address_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => \last_master_r_reg[2]\,
      CE => '1',
      D => mc_address_ns(10),
      Q => \^q\(10),
      R => '0'
    );
\cmd_pipe_plus.mc_address_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => \last_master_r_reg[2]\,
      CE => '1',
      D => mc_address_ns(11),
      Q => \^q\(11),
      R => '0'
    );
\cmd_pipe_plus.mc_address_reg[12]\: unisim.vcomponents.FDRE
     port map (
      C => \last_master_r_reg[2]\,
      CE => '1',
      D => mc_address_ns(12),
      Q => \^q\(12),
      R => '0'
    );
\cmd_pipe_plus.mc_address_reg[13]\: unisim.vcomponents.FDRE
     port map (
      C => \last_master_r_reg[2]\,
      CE => '1',
      D => mc_address_ns(13),
      Q => \^q\(13),
      R => '0'
    );
\cmd_pipe_plus.mc_address_reg[14]\: unisim.vcomponents.FDRE
     port map (
      C => \last_master_r_reg[2]\,
      CE => '1',
      D => mc_address_ns(14),
      Q => \^q\(14),
      R => '0'
    );
\cmd_pipe_plus.mc_address_reg[15]\: unisim.vcomponents.FDRE
     port map (
      C => \last_master_r_reg[2]\,
      CE => '1',
      D => mc_address_ns(15),
      Q => \^q\(15),
      R => '0'
    );
\cmd_pipe_plus.mc_address_reg[16]\: unisim.vcomponents.FDRE
     port map (
      C => \last_master_r_reg[2]\,
      CE => '1',
      D => mc_address_ns(16),
      Q => \^q\(16),
      R => '0'
    );
\cmd_pipe_plus.mc_address_reg[17]\: unisim.vcomponents.FDRE
     port map (
      C => \last_master_r_reg[2]\,
      CE => '1',
      D => mc_address_ns(17),
      Q => \^q\(17),
      R => '0'
    );
\cmd_pipe_plus.mc_address_reg[18]\: unisim.vcomponents.FDRE
     port map (
      C => \last_master_r_reg[2]\,
      CE => '1',
      D => mc_address_ns(18),
      Q => \^q\(18),
      R => '0'
    );
\cmd_pipe_plus.mc_address_reg[19]\: unisim.vcomponents.FDRE
     port map (
      C => \last_master_r_reg[2]\,
      CE => '1',
      D => mc_address_ns(19),
      Q => \^q\(19),
      R => '0'
    );
\cmd_pipe_plus.mc_address_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \last_master_r_reg[2]\,
      CE => '1',
      D => mc_address_ns(1),
      Q => \^q\(1),
      R => '0'
    );
\cmd_pipe_plus.mc_address_reg[20]\: unisim.vcomponents.FDRE
     port map (
      C => \last_master_r_reg[2]\,
      CE => '1',
      D => mc_address_ns(20),
      Q => \^q\(20),
      R => '0'
    );
\cmd_pipe_plus.mc_address_reg[21]\: unisim.vcomponents.FDRE
     port map (
      C => \last_master_r_reg[2]\,
      CE => '1',
      D => mc_address_ns(21),
      Q => \^q\(21),
      R => '0'
    );
\cmd_pipe_plus.mc_address_reg[22]\: unisim.vcomponents.FDRE
     port map (
      C => \last_master_r_reg[2]\,
      CE => '1',
      D => mc_address_ns(22),
      Q => \^q\(22),
      R => '0'
    );
\cmd_pipe_plus.mc_address_reg[23]\: unisim.vcomponents.FDRE
     port map (
      C => \last_master_r_reg[2]\,
      CE => '1',
      D => mc_address_ns(23),
      Q => \^q\(23),
      R => '0'
    );
\cmd_pipe_plus.mc_address_reg[24]\: unisim.vcomponents.FDRE
     port map (
      C => \last_master_r_reg[2]\,
      CE => '1',
      D => mc_address_ns(24),
      Q => \^q\(24),
      R => '0'
    );
\cmd_pipe_plus.mc_address_reg[28]\: unisim.vcomponents.FDRE
     port map (
      C => \last_master_r_reg[2]\,
      CE => '1',
      D => mc_address_ns(28),
      Q => \^q\(25),
      R => '0'
    );
\cmd_pipe_plus.mc_address_reg[29]\: unisim.vcomponents.FDRE
     port map (
      C => \last_master_r_reg[2]\,
      CE => '1',
      D => mc_address_ns(29),
      Q => \^q\(26),
      R => '0'
    );
\cmd_pipe_plus.mc_address_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \last_master_r_reg[2]\,
      CE => '1',
      D => mc_address_ns(2),
      Q => \^q\(2),
      R => '0'
    );
\cmd_pipe_plus.mc_address_reg[30]\: unisim.vcomponents.FDRE
     port map (
      C => \last_master_r_reg[2]\,
      CE => '1',
      D => mc_address_ns(30),
      Q => \^q\(27),
      R => '0'
    );
\cmd_pipe_plus.mc_address_reg[31]\: unisim.vcomponents.FDRE
     port map (
      C => \last_master_r_reg[2]\,
      CE => '1',
      D => mc_address_ns(31),
      Q => \^q\(28),
      R => '0'
    );
\cmd_pipe_plus.mc_address_reg[32]\: unisim.vcomponents.FDRE
     port map (
      C => \last_master_r_reg[2]\,
      CE => '1',
      D => mc_address_ns(32),
      Q => \^q\(29),
      R => '0'
    );
\cmd_pipe_plus.mc_address_reg[33]\: unisim.vcomponents.FDRE
     port map (
      C => \last_master_r_reg[2]\,
      CE => '1',
      D => mc_address_ns(33),
      Q => \^q\(30),
      R => '0'
    );
\cmd_pipe_plus.mc_address_reg[34]\: unisim.vcomponents.FDRE
     port map (
      C => \last_master_r_reg[2]\,
      CE => '1',
      D => mc_address_ns(34),
      Q => \^q\(31),
      R => '0'
    );
\cmd_pipe_plus.mc_address_reg[35]\: unisim.vcomponents.FDRE
     port map (
      C => \last_master_r_reg[2]\,
      CE => '1',
      D => mc_address_ns(35),
      Q => \^q\(32),
      R => '0'
    );
\cmd_pipe_plus.mc_address_reg[36]\: unisim.vcomponents.FDRE
     port map (
      C => \last_master_r_reg[2]\,
      CE => '1',
      D => mc_address_ns(36),
      Q => \^q\(33),
      R => '0'
    );
\cmd_pipe_plus.mc_address_reg[37]\: unisim.vcomponents.FDRE
     port map (
      C => \last_master_r_reg[2]\,
      CE => '1',
      D => mc_address_ns(37),
      Q => \^q\(34),
      R => '0'
    );
\cmd_pipe_plus.mc_address_reg[38]\: unisim.vcomponents.FDRE
     port map (
      C => \last_master_r_reg[2]\,
      CE => '1',
      D => mc_address_ns(38),
      Q => \^q\(35),
      R => '0'
    );
\cmd_pipe_plus.mc_address_reg[39]\: unisim.vcomponents.FDRE
     port map (
      C => \last_master_r_reg[2]\,
      CE => '1',
      D => mc_address_ns(39),
      Q => \^q\(36),
      R => '0'
    );
\cmd_pipe_plus.mc_address_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => \last_master_r_reg[2]\,
      CE => '1',
      D => mc_address_ns(3),
      Q => \^q\(3),
      R => '0'
    );
\cmd_pipe_plus.mc_address_reg[40]\: unisim.vcomponents.FDRE
     port map (
      C => \last_master_r_reg[2]\,
      CE => '1',
      D => mc_address_ns(40),
      Q => \^q\(37),
      R => '0'
    );
\cmd_pipe_plus.mc_address_reg[41]\: unisim.vcomponents.FDRE
     port map (
      C => \last_master_r_reg[2]\,
      CE => '1',
      D => mc_address_ns(41),
      Q => \^q\(38),
      R => '0'
    );
\cmd_pipe_plus.mc_address_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => \last_master_r_reg[2]\,
      CE => '1',
      D => mc_address_ns(4),
      Q => \^q\(4),
      R => '0'
    );
\cmd_pipe_plus.mc_address_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => \last_master_r_reg[2]\,
      CE => '1',
      D => mc_address_ns(5),
      Q => \^q\(5),
      R => '0'
    );
\cmd_pipe_plus.mc_address_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => \last_master_r_reg[2]\,
      CE => '1',
      D => mc_address_ns(6),
      Q => \^q\(6),
      R => '0'
    );
\cmd_pipe_plus.mc_address_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => \last_master_r_reg[2]\,
      CE => '1',
      D => mc_address_ns(7),
      Q => \^q\(7),
      R => '0'
    );
\cmd_pipe_plus.mc_address_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => \last_master_r_reg[2]\,
      CE => '1',
      D => mc_address_ns(8),
      Q => \^q\(8),
      R => '0'
    );
\cmd_pipe_plus.mc_address_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => \last_master_r_reg[2]\,
      CE => '1',
      D => mc_address_ns(9),
      Q => \^q\(9),
      R => '0'
    );
\cmd_pipe_plus.mc_aux_out0_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \last_master_r_reg[2]\,
      CE => '1',
      D => \i___22_n_0\,
      Q => \cmd_pipe_plus.mc_aux_out0_reg_n_0_[1]\,
      R => '0'
    );
\cmd_pipe_plus.mc_bank_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \last_master_r_reg[2]\,
      CE => '1',
      D => mc_bank_ns(0),
      Q => \cmd_pipe_plus.mc_bank_reg[8]_0\(0),
      R => '0'
    );
\cmd_pipe_plus.mc_bank_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \last_master_r_reg[2]\,
      CE => '1',
      D => mc_bank_ns(1),
      Q => \cmd_pipe_plus.mc_bank_reg[8]_0\(1),
      R => '0'
    );
\cmd_pipe_plus.mc_bank_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \last_master_r_reg[2]\,
      CE => '1',
      D => mc_bank_ns(2),
      Q => \cmd_pipe_plus.mc_bank_reg[8]_0\(2),
      R => '0'
    );
\cmd_pipe_plus.mc_bank_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => \last_master_r_reg[2]\,
      CE => '1',
      D => mc_bank_ns(3),
      Q => \cmd_pipe_plus.mc_bank_reg[8]_0\(3),
      R => '0'
    );
\cmd_pipe_plus.mc_bank_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => \last_master_r_reg[2]\,
      CE => '1',
      D => mc_bank_ns(4),
      Q => \cmd_pipe_plus.mc_bank_reg[8]_0\(4),
      R => '0'
    );
\cmd_pipe_plus.mc_bank_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => \last_master_r_reg[2]\,
      CE => '1',
      D => mc_bank_ns(5),
      Q => \cmd_pipe_plus.mc_bank_reg[8]_0\(5),
      R => '0'
    );
\cmd_pipe_plus.mc_bank_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => \last_master_r_reg[2]\,
      CE => '1',
      D => mc_bank_ns(6),
      Q => \cmd_pipe_plus.mc_bank_reg[8]_0\(6),
      R => '0'
    );
\cmd_pipe_plus.mc_bank_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => \last_master_r_reg[2]\,
      CE => '1',
      D => mc_bank_ns(7),
      Q => \cmd_pipe_plus.mc_bank_reg[8]_0\(7),
      R => '0'
    );
\cmd_pipe_plus.mc_bank_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => \last_master_r_reg[2]\,
      CE => '1',
      D => mc_bank_ns(8),
      Q => \cmd_pipe_plus.mc_bank_reg[8]_0\(8),
      R => '0'
    );
\cmd_pipe_plus.mc_cas_n_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \last_master_r_reg[2]\,
      CE => '1',
      D => mc_cas_n_ns(0),
      Q => \^mc_cas_n\(0),
      R => '0'
    );
\cmd_pipe_plus.mc_cas_n_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \last_master_r_reg[2]\,
      CE => '1',
      D => mc_cas_n_ns(1),
      Q => \^mc_cas_n\(1),
      R => '0'
    );
\cmd_pipe_plus.mc_cas_n_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \last_master_r_reg[2]\,
      CE => '1',
      D => mc_cas_n_ns(2),
      Q => \^mc_cas_n\(2),
      R => '0'
    );
\cmd_pipe_plus.mc_cke_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => \last_master_r_reg[2]\,
      CE => '1',
      D => mc_cke_ns(1),
      Q => mc_cke(0),
      R => '0'
    );
\cmd_pipe_plus.mc_cmd_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \last_master_r_reg[2]\,
      CE => '1',
      D => sent_col,
      Q => \^mc_cmd\(0),
      R => '0'
    );
\cmd_pipe_plus.mc_cmd_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \last_master_r_reg[2]\,
      CE => '1',
      D => mc_cmd_ns(1),
      Q => \^mc_cmd\(1),
      R => '0'
    );
\cmd_pipe_plus.mc_cs_n_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \last_master_r_reg[2]\,
      CE => '1',
      D => mc_cs_n_ns(0),
      Q => \^mc_cs_n\(0),
      R => '0'
    );
\cmd_pipe_plus.mc_data_offset_1_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \last_master_r_reg[2]\,
      CE => '1',
      D => \cmd_pipe_plus.mc_data_offset_1_reg[0]_1\,
      Q => \cmd_pipe_plus.mc_data_offset_1_reg[0]_0\,
      R => bank_mach0_n_91
    );
\cmd_pipe_plus.mc_data_offset_1_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \last_master_r_reg[2]\,
      CE => '1',
      D => \arb_mux0/arb_select0/mc_data_offset_11\(1),
      Q => \cmd_pipe_plus.mc_data_offset_1_reg[1]_0\,
      R => bank_mach0_n_91
    );
\cmd_pipe_plus.mc_data_offset_1_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \last_master_r_reg[2]\,
      CE => '1',
      D => \arb_mux0/arb_select0/mc_data_offset_11\(2),
      Q => \cmd_pipe_plus.mc_data_offset_1_reg[2]_0\,
      R => bank_mach0_n_91
    );
\cmd_pipe_plus.mc_data_offset_1_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => \last_master_r_reg[2]\,
      CE => '1',
      D => mc_data_offset_1_ns(3),
      Q => \cmd_pipe_plus.mc_data_offset_1_reg[3]_0\(0),
      R => '0'
    );
\cmd_pipe_plus.mc_data_offset_1_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => \last_master_r_reg[2]\,
      CE => '1',
      D => \arb_mux0/arb_select0/mc_data_offset_11\(4),
      Q => \cmd_pipe_plus.mc_data_offset_1_reg[4]_0\,
      R => bank_mach0_n_91
    );
\cmd_pipe_plus.mc_data_offset_1_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => \last_master_r_reg[2]\,
      CE => '1',
      D => \arb_mux0/arb_select0/mc_data_offset_11\(5),
      Q => \cmd_pipe_plus.mc_data_offset_1_reg[5]_0\,
      R => bank_mach0_n_91
    );
\cmd_pipe_plus.mc_data_offset_2_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \last_master_r_reg[2]\,
      CE => '1',
      D => \cmd_pipe_plus.mc_data_offset_2_reg[0]_1\,
      Q => \cmd_pipe_plus.mc_data_offset_2_reg[0]_0\,
      R => bank_mach0_n_91
    );
\cmd_pipe_plus.mc_data_offset_2_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \last_master_r_reg[2]\,
      CE => '1',
      D => \arb_mux0/arb_select0/mc_data_offset_21\(1),
      Q => \cmd_pipe_plus.mc_data_offset_2_reg[1]_0\,
      R => bank_mach0_n_91
    );
\cmd_pipe_plus.mc_data_offset_2_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \last_master_r_reg[2]\,
      CE => '1',
      D => \arb_mux0/arb_select0/mc_data_offset_21\(2),
      Q => \cmd_pipe_plus.mc_data_offset_2_reg[2]_0\,
      R => bank_mach0_n_91
    );
\cmd_pipe_plus.mc_data_offset_2_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => \last_master_r_reg[2]\,
      CE => '1',
      D => mc_data_offset_2_ns(3),
      Q => \cmd_pipe_plus.mc_data_offset_2_reg[3]_0\(0),
      R => '0'
    );
\cmd_pipe_plus.mc_data_offset_2_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => \last_master_r_reg[2]\,
      CE => '1',
      D => \arb_mux0/arb_select0/mc_data_offset_21\(4),
      Q => \cmd_pipe_plus.mc_data_offset_2_reg[4]_0\,
      R => bank_mach0_n_91
    );
\cmd_pipe_plus.mc_data_offset_2_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => \last_master_r_reg[2]\,
      CE => '1',
      D => \arb_mux0/arb_select0/mc_data_offset_21\(5),
      Q => \cmd_pipe_plus.mc_data_offset_2_reg[5]_0\,
      R => bank_mach0_n_91
    );
\cmd_pipe_plus.mc_data_offset_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \last_master_r_reg[2]\,
      CE => '1',
      D => \cmd_pipe_plus.mc_data_offset_reg[0]_1\,
      Q => \cmd_pipe_plus.mc_data_offset_reg[0]_0\,
      R => bank_mach0_n_91
    );
\cmd_pipe_plus.mc_data_offset_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \last_master_r_reg[2]\,
      CE => '1',
      D => \arb_mux0/arb_select0/mc_data_offset1\(1),
      Q => \cmd_pipe_plus.mc_data_offset_reg[1]_0\,
      R => bank_mach0_n_91
    );
\cmd_pipe_plus.mc_data_offset_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \last_master_r_reg[2]\,
      CE => '1',
      D => \arb_mux0/arb_select0/mc_data_offset1\(2),
      Q => \cmd_pipe_plus.mc_data_offset_reg[2]_0\,
      R => bank_mach0_n_91
    );
\cmd_pipe_plus.mc_data_offset_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => \last_master_r_reg[2]\,
      CE => '1',
      D => mc_data_offset_ns(3),
      Q => \cmd_pipe_plus.mc_data_offset_reg[3]_0\(0),
      R => '0'
    );
\cmd_pipe_plus.mc_data_offset_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => \last_master_r_reg[2]\,
      CE => '1',
      D => \arb_mux0/arb_select0/mc_data_offset1\(4),
      Q => \cmd_pipe_plus.mc_data_offset_reg[4]_0\,
      R => bank_mach0_n_91
    );
\cmd_pipe_plus.mc_data_offset_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => \last_master_r_reg[2]\,
      CE => '1',
      D => \arb_mux0/arb_select0/mc_data_offset1\(5),
      Q => \cmd_pipe_plus.mc_data_offset_reg[5]_0\,
      R => bank_mach0_n_91
    );
\cmd_pipe_plus.mc_odt_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \last_master_r_reg[2]\,
      CE => '1',
      D => mc_odt_ns(0),
      Q => mc_odt(0),
      R => '0'
    );
\cmd_pipe_plus.mc_ras_n_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \last_master_r_reg[2]\,
      CE => '1',
      D => mc_ras_n_ns(0),
      Q => \^mc_ras_n\(0),
      R => '0'
    );
\cmd_pipe_plus.mc_ras_n_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \last_master_r_reg[2]\,
      CE => '1',
      D => \i___23_n_0\,
      Q => \^mc_ras_n\(1),
      R => '0'
    );
\cmd_pipe_plus.mc_ras_n_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \last_master_r_reg[2]\,
      CE => '1',
      D => mc_ras_n_ns(2),
      Q => \^mc_ras_n\(2),
      R => '0'
    );
\cmd_pipe_plus.mc_we_n_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \last_master_r_reg[2]\,
      CE => '1',
      D => mc_we_n_ns(0),
      Q => \^mc_we_n\(0),
      R => '0'
    );
\cmd_pipe_plus.mc_we_n_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \last_master_r_reg[2]\,
      CE => '1',
      D => bank_mach0_n_278,
      Q => \^mc_we_n\(1),
      R => '0'
    );
\cmd_pipe_plus.mc_we_n_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \last_master_r_reg[2]\,
      CE => '1',
      D => mc_we_n_ns(2),
      Q => \^mc_we_n\(2),
      R => '0'
    );
\cmd_pipe_plus.mc_wrdata_en_reg\: unisim.vcomponents.FDRE
     port map (
      C => \last_master_r_reg[2]\,
      CE => '1',
      D => mc_wrdata_en_ns,
      Q => mc_wrdata_en,
      R => '0'
    );
\cmd_pipe_plus.wr_data_addr_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \last_master_r_reg[2]\,
      CE => '1',
      D => wr_data_addr_ns(0),
      Q => wr_data_addr(0),
      R => '0'
    );
\cmd_pipe_plus.wr_data_addr_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \last_master_r_reg[2]\,
      CE => '1',
      D => wr_data_addr_ns(1),
      Q => wr_data_addr(1),
      R => '0'
    );
\cmd_pipe_plus.wr_data_addr_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \last_master_r_reg[2]\,
      CE => '1',
      D => wr_data_addr_ns(2),
      Q => wr_data_addr(2),
      R => '0'
    );
\cmd_pipe_plus.wr_data_addr_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => \last_master_r_reg[2]\,
      CE => '1',
      D => wr_data_addr_ns(3),
      Q => wr_data_addr(3),
      R => '0'
    );
\cmd_pipe_plus.wr_data_en_reg\: unisim.vcomponents.FDRE
     port map (
      C => \last_master_r_reg[2]\,
      CE => '1',
      D => wr_data_en_ns,
      Q => \^wr_data_en\,
      R => '0'
    );
col_mach0: entity work.mig_mig_7series_v4_2_col_mach
     port map (
      ADDRA(2) => \i___92_n_0\,
      ADDRA(1) => \i___91_n_0\,
      ADDRA(0) => \i___93_n_0\,
      D(3 downto 0) => wr_data_addr_ns(3 downto 0),
      DIC(0) => col_periodic_rd,
      E(0) => mc_cmd_ns(1),
      col_rd_wr => col_rd_wr,
      col_rd_wr_r1 => col_rd_wr_r1,
      col_rd_wr_r2 => col_rd_wr_r2,
      col_wr_data_buf_addr(3 downto 0) => col_wr_data_buf_addr(3 downto 0),
      maint_ref_zq_wip => maint_ref_zq_wip,
      mc_cmd(0) => \^mc_cmd\(0),
      mc_ref_zq_wip_ns => mc_ref_zq_wip_ns,
      \read_fifo.fifo_out_data_r_reg[7]_0\(1 downto 0) => \read_fifo.fifo_out_data_r_reg[7]\(1 downto 0),
      \read_fifo.fifo_out_data_r_reg[7]_1\ => \inhbt_act_faw.inhbt_act_faw_r_reg\,
      \read_fifo.head_r_reg[0]_0\ => \periodic_rd_generation.periodic_rd_cntr1_r_reg\,
      \read_fifo.head_r_reg[4]_0\ => \last_master_r_reg[2]\,
      \read_fifo.tail_r_reg[0]_0\ => \^read_fifo.tail_r_reg[0]\(0),
      \read_fifo.tail_r_reg[0]_1\ => \read_fifo.tail_r_reg[0]_0\,
      \read_fifo.tail_r_reg[1]_0\ => \zq_cntrl.zq_request_logic.zq_request_r_reg\,
      \read_fifo.tail_r_reg[2]_0\(1 downto 0) => \read_fifo.tail_r\(2 downto 1),
      \read_fifo.tail_r_reg[2]_1\ => \read_fifo.tail_r_reg[2]\,
      \read_fifo.tail_r_reg[4]_0\ => col_mach0_n_7,
      \read_fifo.tail_r_reg[4]_1\ => col_mach0_n_12,
      sent_col_r2 => sent_col_r2
    );
\i_\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFF0008"
    )
        port map (
      I0 => \rank_cntrl[0].rank_cntrl0/periodic_rd_generation.periodic_rd_request_r\,
      I1 => \grant_r_reg[0]\,
      I2 => \rank_common0/periodic_read_request.upd_last_master_r\,
      I3 => periodic_rd_r,
      I4 => \rank_common0/periodic_read_request.periodic_rd_grant_r\,
      O => \i__n_0\
    );
\i___0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F20"
    )
        port map (
      I0 => maint_sre_r,
      I1 => maint_srx_r,
      I2 => insert_maint_r1,
      I3 => \^app_sr_active\,
      O => \i___0_n_0\
    );
\i___1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFC400C400C400"
    )
        port map (
      I0 => \rank_cntrl[0].rank_cntrl0/refresh_generation.refresh_bank_r\,
      I1 => \grant_r_reg[0]\,
      I2 => \rank_common0/zq_cntrl.zq_request_logic.zq_request_r\,
      I3 => insert_maint_r1,
      I4 => maint_wip_r,
      I5 => maint_ref_zq_wip,
      O => \i___1_n_0\
    );
\i___10\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => sent_col_r2,
      I1 => col_rd_wr_r2,
      O => mc_wrdata_en_ns
    );
\i___11\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \^mc_cmd\(0),
      I1 => col_rd_wr_r1,
      O => wr_data_en_ns
    );
\i___12\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000004FFFFFFFF"
    )
        port map (
      I0 => \rank_common0/maint_prescaler.maint_prescaler_r_reg\(2),
      I1 => \rank_common0/maint_prescaler.maint_prescaler_r_reg\(0),
      I2 => \rank_common0/maint_prescaler.maint_prescaler_r_reg\(1),
      I3 => \rank_common0/maint_prescaler.maint_prescaler_r_reg\(3),
      I4 => \rank_common0/maint_prescaler.maint_prescaler_r_reg\(4),
      I5 => \grant_r_reg[0]\,
      O => \i___12_n_0\
    );
\i___13\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => rank_mach0_n_29,
      I1 => \grant_r_reg[0]\,
      O => \i___13_n_0\
    );
\i___14\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FF2AFFFF"
    )
        port map (
      I0 => \rank_common0/zq_cntrl.zq_request_logic.zq_request_r\,
      I1 => maint_zq_r,
      I2 => insert_maint_r1,
      I3 => app_zq_req,
      I4 => rank_mach0_n_32,
      O => \i___14_n_0\
    );
\i___15\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00F8F0F8"
    )
        port map (
      I0 => app_sr_req,
      I1 => \grant_r_reg[0]\,
      I2 => \rank_common0/sr_cntrl.sre_request_logic.sre_request_r\,
      I3 => maint_sre_r,
      I4 => insert_maint_r1,
      O => \i___15_n_0\
    );
\i___16\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"54550400"
    )
        port map (
      I0 => \last_master_r_reg[2]_0\,
      I1 => \rank_common0/maintenance_request.maint_grant_r\(0),
      I2 => \rank_common0/maintenance_request.new_maint_rank_r\,
      I3 => \rank_common0/maintenance_request.upd_last_master_r\,
      I4 => \rank_common0/maintenance_request.maint_arb0/last_master_r\(0),
      O => \i___16_n_0\
    );
\i___17\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"45444044"
    )
        port map (
      I0 => \last_master_r_reg[2]_0\,
      I1 => \rank_common0/maintenance_request.maint_arb0/last_master_r\(1),
      I2 => \rank_common0/maintenance_request.new_maint_rank_r\,
      I3 => \rank_common0/maintenance_request.upd_last_master_r\,
      I4 => \rank_common0/maintenance_request.maint_grant_r\(1),
      O => \i___17_n_0\
    );
\i___18\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"10111511"
    )
        port map (
      I0 => \last_master_r_reg[2]_0\,
      I1 => \rank_common0/maintenance_request.maint_arb0/last_master_r\(2),
      I2 => \rank_common0/maintenance_request.new_maint_rank_r\,
      I3 => \rank_common0/maintenance_request.upd_last_master_r\,
      I4 => \rank_common0/maintenance_request.maint_grant_r\(2),
      O => \i___18_n_0\
    );
\i___19\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"50405050"
    )
        port map (
      I0 => maint_wip_r,
      I1 => \rank_common0/sr_cntrl.sre_request_logic.sre_request_r\,
      I2 => \grant_r_reg[0]\,
      I3 => \rank_common0/zq_cntrl.zq_request_logic.zq_request_r\,
      I4 => \rank_cntrl[0].rank_cntrl0/refresh_generation.refresh_bank_r\,
      O => \i___19_n_0\
    );
\i___2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"EECCFFCFEECCEECC"
    )
        port map (
      I0 => p_130_out,
      I1 => \bank_cntrl[0].bank0/bank_queue0/set_order_q\,
      I2 => idle_r(0),
      I3 => bank_mach0_n_149,
      I4 => \i___72_n_0\,
      I5 => \bank_cntrl[0].bank0/tail_r\,
      O => \i___2_n_0\
    );
\i___20\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00545454FFFFFFFF"
    )
        port map (
      I0 => bank_mach0_n_104,
      I1 => rank_mach0_n_64,
      I2 => \rank_cntrl[0].rank_cntrl0/periodic_rd_generation.periodic_rd_request_r\,
      I3 => clear_periodic_rd_request,
      I4 => \rank_cntrl[0].rank_cntrl0/periodic_rd_generation.periodic_rd_cntr1_r\,
      I5 => \grant_r_reg[0]\,
      O => \i___20_n_0\
    );
\i___21\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"78"
    )
        port map (
      I0 => \rank_common0/periodic_read_request.periodic_rd_grant_r\,
      I1 => periodic_rd_ack_r,
      I2 => \rank_cntrl[0].rank_cntrl0/periodic_rd_generation.periodic_rd_cntr1_r\,
      O => \i___21_n_0\
    );
\i___22\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => bank_mach0_n_92,
      I1 => sent_col,
      O => \i___22_n_0\
    );
\i___23\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFEFFFF"
    )
        port map (
      I0 => sending_col(0),
      I1 => sending_col(1),
      I2 => sending_col(2),
      I3 => sending_col(3),
      I4 => sent_col,
      O => \i___23_n_0\
    );
\i___24\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"55550455"
    )
        port map (
      I0 => \last_master_r_reg[2]_0\,
      I1 => \wtr_timer.wtr_cnt_r\(1),
      I2 => \wtr_timer.wtr_cnt_r\(0),
      I3 => bank_mach0_n_115,
      I4 => bank_mach0_n_114,
      O => \i___24_n_0\
    );
\i___25\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"5555555555040404"
    )
        port map (
      I0 => \last_master_r_reg[2]_0\,
      I1 => \bank_cntrl[3].bank0/bank_state0/col_wait_r\,
      I2 => sending_col(3),
      I3 => sending_row(3),
      I4 => row_cmd_wr(3),
      I5 => bank_mach0_n_116,
      O => \i___25_n_0\
    );
\i___26\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"5555555555040404"
    )
        port map (
      I0 => \last_master_r_reg[2]_0\,
      I1 => \bank_cntrl[0].bank0/bank_state0/col_wait_r\,
      I2 => sending_col(0),
      I3 => sending_row(0),
      I4 => row_cmd_wr(0),
      I5 => bank_mach0_n_123,
      O => \i___26_n_0\
    );
\i___27\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"07"
    )
        port map (
      I0 => sending_row(0),
      I1 => row_cmd_wr(0),
      I2 => bank_mach0_n_123,
      O => \i___27_n_0\
    );
\i___28\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"4444444444445455"
    )
        port map (
      I0 => \bank_cntrl[0].bank0/bank_state0/col_wait_r\,
      I1 => \i___88_n_0\,
      I2 => bank_mach0_n_125,
      I3 => \bank_cntrl[0].bank0/rb_hit_busies_r\(1),
      I4 => bank_mach0_n_124,
      I5 => bank_mach0_n_160,
      O => \i___28_n_0\
    );
\i___29\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"4444444444445455"
    )
        port map (
      I0 => \bank_cntrl[2].bank0/bank_state0/col_wait_r\,
      I1 => \i___87_n_0\,
      I2 => bank_mach0_n_122,
      I3 => \bank_cntrl[2].bank0/rb_hit_busies_r\(4),
      I4 => bank_mach0_n_127,
      I5 => bank_mach0_n_163,
      O => \i___29_n_0\
    );
\i___3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8FFB800"
    )
        port map (
      I0 => bank_mach0_n_260,
      I1 => p_130_out,
      I2 => bank_mach0_n_144,
      I3 => bank_mach0_n_147,
      I4 => head_r(0),
      O => \i___3_n_0\
    );
\i___30\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"5555555555040404"
    )
        port map (
      I0 => \last_master_r_reg[2]_0\,
      I1 => \bank_cntrl[2].bank0/bank_state0/col_wait_r\,
      I2 => sending_col(2),
      I3 => sending_row(2),
      I4 => row_cmd_wr(2),
      I5 => bank_mach0_n_126,
      O => \i___30_n_0\
    );
\i___31\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"04"
    )
        port map (
      I0 => p_52_out,
      I1 => bank_mach0_n_129,
      I2 => p_130_out,
      O => \i___31_n_0\
    );
\i___32\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFAAEAEAEA"
    )
        port map (
      I0 => p_130_out,
      I1 => \bank_cntrl[1].bank0/pass_open_bank_r\,
      I2 => sending_col(1),
      I3 => rd_wr_r(1),
      I4 => req_wr_r(1),
      I5 => \bank_cntrl[1].bank0/bank_queue0/pre_bm_end_r\,
      O => \i___32_n_0\
    );
\i___33\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"9669699669969669"
    )
        port map (
      I0 => bank_mach0_n_129,
      I1 => idle_r(0),
      I2 => idle_r(1),
      I3 => idle_r(2),
      I4 => idle_r(3),
      I5 => p_130_out,
      O => \i___33_n_0\
    );
\i___34\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FCDDFFFF"
    )
        port map (
      I0 => bank_mach0_n_154,
      I1 => \bank_cntrl[1].bank0/bank_queue0/set_order_q\,
      I2 => bank_mach0_n_133,
      I3 => idle_r(1),
      I4 => bank_mach0_n_129,
      O => \i___34_n_0\
    );
\i___35\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"4444554544444444"
    )
        port map (
      I0 => \i___37_n_0\,
      I1 => \bank_common0/maint_controller.maint_hit_busies_r\(1),
      I2 => maint_req_r,
      I3 => \bank_common0/periodic_rd_cntr_r\,
      I4 => maint_wip_r,
      I5 => bank_mach0_n_93,
      O => \i___35_n_0\
    );
\i___36\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"4544555545444544"
    )
        port map (
      I0 => \i___37_n_0\,
      I1 => \bank_cntrl[1].bank0/q_has_rd\,
      I2 => was_wr,
      I3 => bank_mach0_n_135,
      I4 => idle_r(1),
      I5 => maint_req_r,
      O => \i___36_n_0\
    );
\i___37\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFAAEAEAEA"
    )
        port map (
      I0 => \last_master_r_reg[2]_0\,
      I1 => \bank_cntrl[1].bank0/pass_open_bank_r\,
      I2 => sending_col(1),
      I3 => rd_wr_r(1),
      I4 => req_wr_r(1),
      I5 => \bank_cntrl[1].bank0/bank_queue0/pre_bm_end_r\,
      O => \i___37_n_0\
    );
\i___38\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"8117177E"
    )
        port map (
      I0 => bank_mach0_n_137,
      I1 => rb_hit_busy_r(0),
      I2 => rb_hit_busy_r(2),
      I3 => rb_hit_busy_r(1),
      I4 => rb_hit_busy_r(3),
      O => \i___38_n_0\
    );
\i___39\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FCDDFFFF"
    )
        port map (
      I0 => bank_mach0_n_137,
      I1 => \bank_cntrl[3].bank0/bank_queue0/set_order_q\,
      I2 => bank_mach0_n_133,
      I3 => idle_r(3),
      I4 => bank_mach0_n_117,
      O => \i___39_n_0\
    );
\i___4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"88B8FFFF88B80000"
    )
        port map (
      I0 => bank_mach0_n_156,
      I1 => bank_mach0_n_129,
      I2 => bank_mach0_n_260,
      I3 => p_130_out,
      I4 => \i___34_n_0\,
      I5 => head_r(1),
      O => \i___4_n_0\
    );
\i___40\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"EFEEEEEEFFFFFFFF"
    )
        port map (
      I0 => bank_mach0_n_151,
      I1 => rnk_config_valid_r,
      I2 => \bank_cntrl[2].bank0/bank_state0/override_demand_ns\,
      I3 => bank_mach0_n_150,
      I4 => \bank_cntrl[1].bank0/bank_state0/req_bank_rdy_ns\,
      I5 => bank_mach0_n_152,
      O => \i___40_n_0\
    );
\i___41\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"8F"
    )
        port map (
      I0 => req_wr_r(1),
      I1 => rd_wr_r(1),
      I2 => sending_col(1),
      O => \i___41_n_0\
    );
\i___42\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"EAAAEAAAEAAAAAAA"
    )
        port map (
      I0 => \bank_cntrl[1].bank0/wait_for_maint_r\,
      I1 => accept_internal_r,
      I2 => idle_r(1),
      I3 => head_r(1),
      I4 => periodic_rd_ack_r,
      I5 => use_addr,
      O => \i___42_n_0\
    );
\i___43\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"EAAAEAAAEAAAAAAA"
    )
        port map (
      I0 => \bank_cntrl[3].bank0/wait_for_maint_r\,
      I1 => accept_internal_r,
      I2 => idle_r(3),
      I3 => head_r(3),
      I4 => periodic_rd_ack_r,
      I5 => use_addr,
      O => \i___43_n_0\
    );
\i___44\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"4444554544444444"
    )
        port map (
      I0 => \i___55_n_0\,
      I1 => \bank_common0/maint_controller.maint_hit_busies_r\(3),
      I2 => maint_req_r,
      I3 => \bank_common0/periodic_rd_cntr_r\,
      I4 => maint_wip_r,
      I5 => bank_mach0_n_94,
      O => \i___44_n_0\
    );
\i___45\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"EAAAEAAAEAAAAAAA"
    )
        port map (
      I0 => \bank_cntrl[2].bank0/wait_for_maint_r\,
      I1 => accept_internal_r,
      I2 => idle_r(2),
      I3 => head_r(2),
      I4 => periodic_rd_ack_r,
      I5 => use_addr,
      O => \i___45_n_0\
    );
\i___46\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"4444554544444444"
    )
        port map (
      I0 => bank_mach0_n_58,
      I1 => \bank_common0/maint_controller.maint_hit_busies_r\(2),
      I2 => maint_req_r,
      I3 => \bank_common0/periodic_rd_cntr_r\,
      I4 => maint_wip_r,
      I5 => bank_mach0_n_96,
      O => \i___46_n_0\
    );
\i___47\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"EAAAEAAAEAAAAAAA"
    )
        port map (
      I0 => \bank_cntrl[0].bank0/wait_for_maint_r\,
      I1 => accept_internal_r,
      I2 => idle_r(0),
      I3 => head_r(0),
      I4 => periodic_rd_ack_r,
      I5 => use_addr,
      O => \i___47_n_0\
    );
\i___48\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"4444554544444444"
    )
        port map (
      I0 => bank_mach0_n_59,
      I1 => \bank_common0/maint_controller.maint_hit_busies_r\(0),
      I2 => maint_req_r,
      I3 => \bank_common0/periodic_rd_cntr_r\,
      I4 => maint_wip_r,
      I5 => bank_mach0_n_98,
      O => \i___48_n_0\
    );
\i___49\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"5555555555040404"
    )
        port map (
      I0 => \last_master_r_reg[2]_0\,
      I1 => \bank_cntrl[1].bank0/bank_state0/col_wait_r\,
      I2 => sending_col(1),
      I3 => sending_row(1),
      I4 => row_cmd_wr(1),
      I5 => bank_mach0_n_158,
      O => \i___49_n_0\
    );
\i___5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"2F20FFFF2F200000"
    )
        port map (
      I0 => bank_mach0_n_260,
      I1 => \i___32_n_0\,
      I2 => p_52_out,
      I3 => bank_mach0_n_142,
      I4 => bank_mach0_n_143,
      I5 => head_r(2),
      O => \i___5_n_0\
    );
\i___50\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"04"
    )
        port map (
      I0 => p_52_out,
      I1 => bank_mach0_n_117,
      I2 => p_130_out,
      O => \i___50_n_0\
    );
\i___51\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"4544555545444544"
    )
        port map (
      I0 => bank_mach0_n_59,
      I1 => \bank_cntrl[0].bank0/q_has_rd\,
      I2 => was_wr,
      I3 => \i___72_n_0\,
      I4 => idle_r(0),
      I5 => maint_req_r,
      O => \i___51_n_0\
    );
\i___52\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"4544555545444544"
    )
        port map (
      I0 => bank_mach0_n_58,
      I1 => \bank_cntrl[2].bank0/q_has_rd\,
      I2 => was_wr,
      I3 => bank_mach0_n_161,
      I4 => idle_r(2),
      I5 => maint_req_r,
      O => \i___52_n_0\
    );
\i___53\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"8F"
    )
        port map (
      I0 => req_wr_r(2),
      I1 => rd_wr_r(2),
      I2 => sending_col(2),
      O => \i___53_n_0\
    );
\i___54\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"4544555545444544"
    )
        port map (
      I0 => \i___55_n_0\,
      I1 => \bank_cntrl[3].bank0/q_has_rd\,
      I2 => was_wr,
      I3 => \i___71_n_0\,
      I4 => idle_r(3),
      I5 => maint_req_r,
      O => \i___54_n_0\
    );
\i___55\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFAAEAEAEA"
    )
        port map (
      I0 => \last_master_r_reg[2]_0\,
      I1 => \bank_cntrl[3].bank0/pass_open_bank_r\,
      I2 => sending_col(3),
      I3 => rd_wr_r(3),
      I4 => req_wr_r(3),
      I5 => \bank_cntrl[3].bank0/bank_queue0/pre_bm_end_r\,
      O => \i___55_n_0\
    );
\i___56\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"8F"
    )
        port map (
      I0 => req_wr_r(3),
      I1 => rd_wr_r(3),
      I2 => sending_col(3),
      O => \i___56_n_0\
    );
\i___57\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"78"
    )
        port map (
      I0 => periodic_rd_r,
      I1 => periodic_rd_ack_r,
      I2 => \rank_common0/periodic_read_request.periodic_rd_r_cnt\,
      O => \i___57_n_0\
    );
\i___58\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"78"
    )
        port map (
      I0 => periodic_rd_r,
      I1 => periodic_rd_ack_r,
      I2 => \bank_common0/periodic_rd_cntr_r\,
      O => \i___58_n_0\
    );
\i___59\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"BFAA"
    )
        port map (
      I0 => cmd(0),
      I1 => periodic_rd_ack_r,
      I2 => \bank_common0/periodic_rd_cntr_r\,
      I3 => periodic_rd_r,
      O => \i___59_n_0\
    );
\i___6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"B888FFFFB8880000"
    )
        port map (
      I0 => bank_mach0_n_138,
      I1 => bank_mach0_n_117,
      I2 => \i___31_n_0\,
      I3 => bank_mach0_n_260,
      I4 => \i___39_n_0\,
      I5 => head_r(3),
      O => \i___6_n_0\
    );
\i___60\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0101010101015101"
    )
        port map (
      I0 => \last_master_r_reg[2]_0\,
      I1 => bank_mach0_n_276,
      I2 => \^generate_maint_cmds.insert_maint_r_lcl_reg\,
      I3 => maint_srx_r,
      I4 => maint_sre_r,
      I5 => maint_zq_r,
      O => \i___60_n_0\
    );
\i___61\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFF11110010"
    )
        port map (
      I0 => bank_mach0_n_159,
      I1 => bank_mach0_n_259,
      I2 => \bank_cntrl[0].bank0/bank_state0/col_wait_r\,
      I3 => sending_col(0),
      I4 => row_cmd_wr(0),
      I5 => \bank_cntrl[0].bank0/auto_pre_r\,
      O => \i___61_n_0\
    );
\i___62\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFF11110010"
    )
        port map (
      I0 => bank_mach0_n_136,
      I1 => bank_mach0_n_262,
      I2 => \bank_cntrl[1].bank0/bank_state0/col_wait_r\,
      I3 => sending_col(1),
      I4 => row_cmd_wr(1),
      I5 => \bank_cntrl[1].bank0/auto_pre_r\,
      O => \i___62_n_0\
    );
\i___63\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFF11110010"
    )
        port map (
      I0 => bank_mach0_n_162,
      I1 => bank_mach0_n_261,
      I2 => \bank_cntrl[2].bank0/bank_state0/col_wait_r\,
      I3 => sending_col(2),
      I4 => row_cmd_wr(2),
      I5 => \bank_cntrl[2].bank0/auto_pre_r\,
      O => \i___63_n_0\
    );
\i___64\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFF11110010"
    )
        port map (
      I0 => bank_mach0_n_164,
      I1 => bank_mach0_n_258,
      I2 => \bank_cntrl[3].bank0/bank_state0/col_wait_r\,
      I3 => sending_col(3),
      I4 => row_cmd_wr(3),
      I5 => \bank_cntrl[3].bank0/auto_pre_r\,
      O => \i___64_n_0\
    );
\i___65\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"AAFB"
    )
        port map (
      I0 => \inhbt_act_faw.inhbt_act_faw_r_reg\,
      I1 => maint_req_r,
      I2 => \bank_common0/periodic_rd_cntr_r\,
      I3 => maint_wip_r,
      O => \i___65_n_0\
    );
\i___66\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"55FF55CF"
    )
        port map (
      I0 => row_cmd_wr(0),
      I1 => maint_zq_r,
      I2 => insert_maint_r1,
      I3 => sending_row(0),
      I4 => \inhbt_act_faw.inhbt_act_faw_r_reg\,
      O => \i___66_n_0\
    );
\i___67\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"EEEEEEE0"
    )
        port map (
      I0 => sent_row,
      I1 => insert_maint_r1,
      I2 => sending_row(3),
      I3 => sending_row(2),
      I4 => sending_row(1),
      O => \i___67_n_0\
    );
\i___68\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFFFF1"
    )
        port map (
      I0 => sent_row,
      I1 => insert_maint_r1,
      I2 => sending_row(3),
      I3 => sending_row(2),
      I4 => sending_row(1),
      O => \i___68_n_0\
    );
\i___69\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"EF"
    )
        port map (
      I0 => sending_row(2),
      I1 => sending_row(3),
      I2 => sending_row(1),
      O => \i___69_n_0\
    );
\i___7\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"DDCCFFCFDDCCDDCC"
    )
        port map (
      I0 => bank_mach0_n_129,
      I1 => \bank_cntrl[1].bank0/bank_queue0/set_order_q\,
      I2 => idle_r(1),
      I3 => \i___50_n_0\,
      I4 => bank_mach0_n_135,
      I5 => \bank_cntrl[1].bank0/tail_r\,
      O => \i___7_n_0\
    );
\i___70\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000015"
    )
        port map (
      I0 => bank_mach0_n_264,
      I1 => row_cmd_wr(2),
      I2 => sending_row(2),
      I3 => sending_row(0),
      I4 => bank_mach0_n_257,
      O => \i___70_n_0\
    );
\i___71\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F800"
    )
        port map (
      I0 => use_addr,
      I1 => bank_mach0_n_10,
      I2 => periodic_rd_ack_r,
      I3 => rb_hit_busy_r(3),
      O => \i___71_n_0\
    );
\i___72\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F800"
    )
        port map (
      I0 => use_addr,
      I1 => bank_mach0_n_10,
      I2 => periodic_rd_ack_r,
      I3 => rb_hit_busy_r(0),
      O => \i___72_n_0\
    );
\i___73\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000015"
    )
        port map (
      I0 => bank_mach0_n_263,
      I1 => row_cmd_wr(3),
      I2 => sending_row(3),
      I3 => sending_row(1),
      I4 => bank_mach0_n_267,
      O => \i___73_n_0\
    );
\i___74\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000015"
    )
        port map (
      I0 => bank_mach0_n_267,
      I1 => row_cmd_wr(1),
      I2 => sending_row(1),
      I3 => sending_row(3),
      I4 => bank_mach0_n_266,
      O => \i___74_n_0\
    );
\i___75\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0151"
    )
        port map (
      I0 => \inhbt_act_faw.inhbt_act_faw_r_reg\,
      I1 => \arb_mux0/arb_row_col0/pre_4_1_1T_arb.pre_arb0/last_master_r\(3),
      I2 => \arb_mux0/cs_en2\,
      I3 => sending_pre(3),
      O => \i___75_n_0\
    );
\i___76\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FF4C"
    )
        port map (
      I0 => periodic_rd_ack_r,
      I1 => periodic_rd_r,
      I2 => \rank_common0/periodic_read_request.periodic_rd_r_cnt\,
      I3 => \rank_common0/periodic_read_request.upd_last_master_r\,
      O => \i___76_n_0\
    );
\i___77\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"BA"
    )
        port map (
      I0 => app_ref_req,
      I1 => \rank_cntrl[0].rank_cntrl0/refresh_generation.refresh_bank_r\,
      I2 => \rank_common0/app_ref_r\,
      O => \i___77_n_0\
    );
\i___78\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"EA"
    )
        port map (
      I0 => app_zq_req,
      I1 => \rank_common0/app_zq_r\,
      I2 => \rank_common0/zq_cntrl.zq_request_logic.zq_request_r\,
      O => \i___78_n_0\
    );
\i___79\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"1441"
    )
        port map (
      I0 => \inhbt_act_faw.inhbt_act_faw_r_reg\,
      I1 => \rank_cntrl[0].rank_cntrl0/inhbt_act_faw.act_delayed\,
      I2 => bank_mach0_n_274,
      I3 => \inhbt_act_faw.faw_cnt_r\(0),
      O => \i___79_n_0\
    );
\i___8\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"EFEFCCCFEEEECCCC"
    )
        port map (
      I0 => p_52_out,
      I1 => \bank_cntrl[2].bank0/bank_queue0/set_order_q\,
      I2 => bank_mach0_n_161,
      I3 => idle_r(2),
      I4 => bank_mach0_n_128,
      I5 => \bank_cntrl[2].bank0/tail_r\,
      O => \i___8_n_0\
    );
\i___80\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"44411444"
    )
        port map (
      I0 => \inhbt_act_faw.inhbt_act_faw_r_reg\,
      I1 => \inhbt_act_faw.faw_cnt_r\(1),
      I2 => bank_mach0_n_274,
      I3 => \rank_cntrl[0].rank_cntrl0/inhbt_act_faw.act_delayed\,
      I4 => \inhbt_act_faw.faw_cnt_r\(0),
      O => \i___80_n_0\
    );
\i___81\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"5551455500041000"
    )
        port map (
      I0 => \inhbt_act_faw.inhbt_act_faw_r_reg\,
      I1 => \inhbt_act_faw.faw_cnt_r\(1),
      I2 => \rank_cntrl[0].rank_cntrl0/inhbt_act_faw.act_delayed\,
      I3 => bank_mach0_n_274,
      I4 => \inhbt_act_faw.faw_cnt_r\(0),
      I5 => \inhbt_act_faw.faw_cnt_r\(2),
      O => \i___81_n_0\
    );
\i___82\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F7FF"
    )
        port map (
      I0 => \bank_common0/rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r\(1),
      I1 => \bank_common0/rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r\(0),
      I2 => \bank_common0/rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r\(2),
      I3 => bank_mach0_n_275,
      O => \i___82_n_0\
    );
\i___83\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFFE"
    )
        port map (
      I0 => \bank_common0/rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r\(3),
      I1 => \bank_common0/rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r\(2),
      I2 => \bank_common0/rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r\(1),
      I3 => \bank_common0/rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r\(0),
      O => \i___83_n_0\
    );
\i___84\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000055550010"
    )
        port map (
      I0 => \bank_cntrl[2].bank0/bank_state0/override_demand_r\,
      I1 => \bank_cntrl[0].bank0/bank_state0/demanded_prior_r\,
      I2 => \bank_cntrl[0].bank0/bank_state0/demand_priority_r\,
      I3 => sending_col(0),
      I4 => bank_mach0_n_265,
      I5 => \bank_cntrl[3].bank0/bank_state0/demand_priority_r\,
      O => \i___84_n_0\
    );
\i___85\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000011111511"
    )
        port map (
      I0 => \bank_cntrl[2].bank0/bank_state0/override_demand_r\,
      I1 => bank_mach0_n_277,
      I2 => \bank_cntrl[2].bank0/bank_state0/demanded_prior_r\,
      I3 => \bank_cntrl[2].bank0/bank_state0/demand_priority_r\,
      I4 => sending_col(2),
      I5 => \bank_cntrl[1].bank0/bank_state0/demand_priority_r\,
      O => \i___85_n_0\
    );
\i___86\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000011111511"
    )
        port map (
      I0 => \bank_cntrl[2].bank0/bank_state0/override_demand_r\,
      I1 => bank_mach0_n_277,
      I2 => \bank_cntrl[1].bank0/bank_state0/demanded_prior_r\,
      I3 => \bank_cntrl[1].bank0/bank_state0/demand_priority_r\,
      I4 => sending_col(1),
      I5 => \bank_cntrl[2].bank0/bank_state0/demand_priority_r\,
      O => \i___86_n_0\
    );
\i___87\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"EF"
    )
        port map (
      I0 => idle_r(2),
      I1 => bank_mach0_n_140,
      I2 => bank_mach0_n_141,
      O => \i___87_n_0\
    );
\i___88\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"EF"
    )
        port map (
      I0 => idle_r(0),
      I1 => q_entry_r(1),
      I2 => q_entry_r(0),
      O => \i___88_n_0\
    );
\i___89\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"EF"
    )
        port map (
      I0 => idle_r(3),
      I1 => bank_mach0_n_131,
      I2 => bank_mach0_n_132,
      O => \i___89_n_0\
    );
\i___9\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"DDCCFFCFDDCCDDCC"
    )
        port map (
      I0 => bank_mach0_n_117,
      I1 => \bank_cntrl[3].bank0/bank_queue0/set_order_q\,
      I2 => idle_r(3),
      I3 => \i___31_n_0\,
      I4 => \i___71_n_0\,
      I5 => \bank_cntrl[3].bank0/tail_r\,
      O => \i___9_n_0\
    );
\i___90\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"EF"
    )
        port map (
      I0 => idle_r(1),
      I1 => bank_mach0_n_157,
      I2 => bank_mach0_n_155,
      O => \i___90_n_0\
    );
\i___91\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"15554000"
    )
        port map (
      I0 => \inhbt_act_faw.inhbt_act_faw_r_reg\,
      I1 => \^read_fifo.tail_r_reg[0]\(0),
      I2 => \read_fifo.tail_r_reg[2]\,
      I3 => \read_fifo.tail_r\(1),
      I4 => \read_fifo.tail_r\(2),
      O => \i___91_n_0\
    );
\i___92\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \inhbt_act_faw.inhbt_act_faw_r_reg\,
      I1 => col_mach0_n_12,
      O => \i___92_n_0\
    );
\i___93\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"1540"
    )
        port map (
      I0 => \inhbt_act_faw.inhbt_act_faw_r_reg\,
      I1 => \read_fifo.tail_r_reg[2]\,
      I2 => \^read_fifo.tail_r_reg[0]\(0),
      I3 => \read_fifo.tail_r\(1),
      O => \i___93_n_0\
    );
\i___94\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => \rank_common0/maint_prescaler.maint_prescaler_r_reg\(0),
      I1 => \rank_common0/maint_prescaler.maint_prescaler_r_reg\(1),
      O => \i___94_n_0\
    );
\i___95\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => \rank_common0/refresh_timer.refresh_timer_r_reg\(0),
      I1 => \rank_common0/refresh_timer.refresh_timer_r_reg\(1),
      O => \i___95_n_0\
    );
mc_read_idle_r_reg: unisim.vcomponents.FDRE
     port map (
      C => \last_master_r_reg[2]\,
      CE => '1',
      D => col_mach0_n_7,
      Q => idle,
      R => \periodic_read_request.periodic_rd_r_lcl_reg\
    );
mc_ref_zq_wip_r_reg: unisim.vcomponents.FDRE
     port map (
      C => \last_master_r_reg[2]\,
      CE => '1',
      D => mc_ref_zq_wip_ns,
      Q => mc_ref_zq_wip,
      R => '0'
    );
\mem_reg_0_15_12_17_i_2__1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^q\(13),
      I1 => mem_reg_0_15_36_41,
      O => d_in(0)
    );
\mem_reg_0_15_18_23_i_1__7\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^q\(38),
      I1 => mem_reg_0_15_36_41,
      O => d_in(1)
    );
\mem_reg_0_15_30_35_i_2__9\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => \^mc_cs_n\(0),
      I1 => mem_reg_0_15_42_47,
      O => phy_dout(0)
    );
\mem_reg_0_15_30_35_i_3__9\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => \^mc_ras_n\(2),
      I1 => mem_reg_0_15_42_47,
      O => phy_dout(4)
    );
\mem_reg_0_15_36_41_i_1__9\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^q\(11),
      I1 => mem_reg_0_15_36_41,
      O => d_in(2)
    );
\mem_reg_0_15_36_41_i_2__8\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => \^mc_cas_n\(0),
      I1 => mem_reg_0_15_36_41,
      O => phy_dout(1)
    );
\mem_reg_0_15_42_47_i_1__8\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => \^mc_cas_n\(2),
      I1 => mem_reg_0_15_42_47,
      O => phy_dout(2)
    );
\mem_reg_0_15_42_47_i_1__9\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^q\(36),
      I1 => mem_reg_0_15_36_41,
      O => d_in(3)
    );
\mem_reg_0_15_42_47_i_3__9\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => \^mc_ras_n\(0),
      I1 => mem_reg_0_15_42_47,
      O => phy_dout(3)
    );
\mem_reg_0_15_48_53_i_2__9\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => \^mc_we_n\(0),
      I1 => mem_reg_0_15_42_47,
      O => phy_dout(5)
    );
\mem_reg_0_15_54_59_i_1__9\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => \^mc_we_n\(2),
      I1 => mem_reg_0_15_42_47,
      O => phy_dout(6)
    );
\pointer_ram.rams[0].RAM32M0_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => \^wr_data_en\,
      I1 => ram_init_done_r,
      O => \pointer_ram.pointer_we\
    );
rank_mach0: entity work.mig_mig_7series_v4_2_rank_mach
     port map (
      D(1) => \i___17_n_0\,
      D(0) => \i___16_n_0\,
      O(3) => \zq_cntrl.zq_timer.zq_timer_r_reg[0]_i_3_n_4\,
      O(2) => \zq_cntrl.zq_timer.zq_timer_r_reg[0]_i_3_n_5\,
      O(1) => \zq_cntrl.zq_timer.zq_timer_r_reg[0]_i_3_n_6\,
      O(0) => \zq_cntrl.zq_timer.zq_timer_r_reg[0]_i_3_n_7\,
      Q(4 downto 0) => \rank_common0/maint_prescaler.maint_prescaler_r_reg\(4 downto 0),
      S(3) => rank_mach0_n_40,
      S(2) => rank_mach0_n_41,
      S(1) => rank_mach0_n_42,
      S(0) => rank_mach0_n_43,
      SR(0) => SR(0),
      SS(0) => \i___12_n_0\,
      act_this_rank => \rank_cntrl[0].rank_cntrl0/act_this_rank\,
      app_ref_ack => app_ref_ack,
      app_ref_r => \rank_common0/app_ref_r\,
      app_ref_r_reg => \i___77_n_0\,
      app_ref_req => app_ref_req,
      app_sr_active => \^app_sr_active\,
      app_sr_active_r_reg => \i___0_n_0\,
      app_sr_req => app_sr_req,
      app_zq_ack => app_zq_ack,
      app_zq_r => \rank_common0/app_zq_r\,
      app_zq_r_reg => \i___78_n_0\,
      cke_r => \arb_mux0/arb_select0/cke_r\,
      \grant_r_reg[0]\ => \grant_r_reg[0]\,
      \grant_r_reg[2]\(2 downto 0) => \rank_common0/maintenance_request.maint_grant_r\(2 downto 0),
      \grant_r_reg[2]_0\ => \i___18_n_0\,
      \inhbt_act_faw.act_delayed\ => \rank_cntrl[0].rank_cntrl0/inhbt_act_faw.act_delayed\,
      \inhbt_act_faw.faw_cnt_r_reg[2]\(2 downto 0) => \inhbt_act_faw.faw_cnt_r\(2 downto 0),
      \inhbt_act_faw.faw_cnt_r_reg[2]_0\(2) => \i___81_n_0\,
      \inhbt_act_faw.faw_cnt_r_reg[2]_0\(1) => \i___80_n_0\,
      \inhbt_act_faw.faw_cnt_r_reg[2]_0\(0) => \i___79_n_0\,
      \inhbt_act_faw.inhbt_act_faw_r_reg\ => \inhbt_act_faw.inhbt_act_faw_r_reg\,
      \inhbt_act_faw.inhbt_act_faw_r_reg_0\ => bank_mach0_n_274,
      inhbt_act_faw_r => inhbt_act_faw_r,
      \init_calib_complete_reg_rep__26\ => rank_mach0_n_32,
      insert_maint_r1 => insert_maint_r1,
      \last_master_r_reg[2]\(2 downto 0) => \rank_common0/maintenance_request.maint_arb0/last_master_r\(2 downto 0),
      \last_master_r_reg[2]_0\ => \last_master_r_reg[2]\,
      \last_master_r_reg[2]_1\ => \last_master_r_reg[2]_0\,
      \maint_prescaler.maint_prescaler_r_reg[1]\(0) => \i___94_n_0\,
      maint_ref_zq_wip => maint_ref_zq_wip,
      maint_ref_zq_wip_r_reg => \i___1_n_0\,
      maint_req_r => maint_req_r,
      maint_sre_r => maint_sre_r,
      maint_srx_r => maint_srx_r,
      maint_zq_r => maint_zq_r,
      \maintenance_request.maint_sre_r_lcl_reg\ => rank_mach0_n_63,
      \maintenance_request.maint_srx_r_lcl_reg\(0) => \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_ns\(0),
      \maintenance_request.new_maint_rank_r\ => \rank_common0/maintenance_request.new_maint_rank_r\,
      \maintenance_request.upd_last_master_r\ => \rank_common0/maintenance_request.upd_last_master_r\,
      \maintenance_request.upd_last_master_r_reg\ => \i___19_n_0\,
      mc_cke_ns(0) => mc_cke_ns(1),
      \periodic_rd_generation.periodic_rd_cntr1_r\ => \rank_cntrl[0].rank_cntrl0/periodic_rd_generation.periodic_rd_cntr1_r\,
      \periodic_rd_generation.periodic_rd_cntr1_r_reg\ => \periodic_rd_generation.periodic_rd_cntr1_r_reg\,
      \periodic_rd_generation.periodic_rd_cntr1_r_reg_0\ => \i___21_n_0\,
      \periodic_rd_generation.periodic_rd_request_r\ => \rank_cntrl[0].rank_cntrl0/periodic_rd_generation.periodic_rd_request_r\,
      \periodic_rd_generation.periodic_rd_request_r_reg\ => \i___20_n_0\,
      \periodic_rd_generation.periodic_rd_timer_r_reg[2]\ => rank_mach0_n_64,
      \periodic_rd_generation.periodic_rd_timer_r_reg[2]_0\ => bank_mach0_n_104,
      \periodic_rd_generation.periodic_rd_timer_r_reg[2]_1\ => \periodic_rd_generation.periodic_rd_timer_r_reg[2]\,
      \periodic_rd_generation.read_this_rank\ => \rank_cntrl[0].rank_cntrl0/periodic_rd_generation.read_this_rank\,
      \periodic_rd_generation.read_this_rank_r\ => \rank_cntrl[0].rank_cntrl0/periodic_rd_generation.read_this_rank_r\,
      periodic_rd_r => periodic_rd_r,
      \periodic_read_request.periodic_rd_grant_r\ => \rank_common0/periodic_read_request.periodic_rd_grant_r\,
      \periodic_read_request.periodic_rd_grant_r_reg[0]\ => \i__n_0\,
      \periodic_read_request.periodic_rd_r_cnt\ => \rank_common0/periodic_read_request.periodic_rd_r_cnt\,
      \periodic_read_request.periodic_rd_r_cnt_reg\ => \periodic_read_request.periodic_rd_r_cnt_reg\,
      \periodic_read_request.periodic_rd_r_cnt_reg_0\ => \i___57_n_0\,
      \periodic_read_request.periodic_rd_r_lcl_reg\ => \periodic_read_request.periodic_rd_r_lcl_reg\,
      \periodic_read_request.periodic_rd_r_lcl_reg_0\ => \i___76_n_0\,
      \periodic_read_request.upd_last_master_r\ => \rank_common0/periodic_read_request.upd_last_master_r\,
      \refresh_generation.refresh_bank_r\ => \rank_cntrl[0].rank_cntrl0/refresh_generation.refresh_bank_r\,
      \refresh_timer.refresh_timer_r_reg[1]\(1 downto 0) => \rank_common0/refresh_timer.refresh_timer_r_reg\(1 downto 0),
      \refresh_timer.refresh_timer_r_reg[1]_0\(0) => \i___95_n_0\,
      \refresh_timer.refresh_timer_r_reg[5]\ => rank_mach0_n_29,
      \refresh_timer.refresh_timer_r_reg[5]_0\(0) => \i___13_n_0\,
      \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[0]\(0) => \bank_common0/rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r\(0),
      \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[0]_0\ => \^generate_maint_cmds.insert_maint_r_lcl_reg\,
      \rtw_timer.rtw_cnt_r_reg[1]\(1 downto 0) => \rtw_timer.rtw_cnt_r\(1 downto 0),
      \rtw_timer.rtw_cnt_r_reg[1]_0\(1 downto 0) => \rank_cntrl[0].rank_cntrl0/rtw_timer.rtw_cnt_ns\(1 downto 0),
      \sr_cntrl.sre_request_logic.sre_request_r\ => \rank_common0/sr_cntrl.sre_request_logic.sre_request_r\,
      \sr_cntrl.sre_request_logic.sre_request_r_reg\ => \i___15_n_0\,
      \wtr_timer.wtr_cnt_r_reg[0]\(0) => \i___24_n_0\,
      \wtr_timer.wtr_cnt_r_reg[1]\(1 downto 0) => \wtr_timer.wtr_cnt_r\(1 downto 0),
      \wtr_timer.wtr_cnt_r_reg[1]_0\ => bank_mach0_n_113,
      \zq_cntrl.zq_request_logic.zq_request_r\ => \rank_common0/zq_cntrl.zq_request_logic.zq_request_r\,
      \zq_cntrl.zq_request_logic.zq_request_r_reg\ => \zq_cntrl.zq_request_logic.zq_request_r_reg\,
      \zq_cntrl.zq_request_logic.zq_request_r_reg_0\ => \i___14_n_0\,
      \zq_cntrl.zq_timer.zq_timer_r_reg[11]\(3) => rank_mach0_n_48,
      \zq_cntrl.zq_timer.zq_timer_r_reg[11]\(2) => rank_mach0_n_49,
      \zq_cntrl.zq_timer.zq_timer_r_reg[11]\(1) => rank_mach0_n_50,
      \zq_cntrl.zq_timer.zq_timer_r_reg[11]\(0) => rank_mach0_n_51,
      \zq_cntrl.zq_timer.zq_timer_r_reg[11]_0\(3) => \zq_cntrl.zq_timer.zq_timer_r_reg[8]_i_1_n_4\,
      \zq_cntrl.zq_timer.zq_timer_r_reg[11]_0\(2) => \zq_cntrl.zq_timer.zq_timer_r_reg[8]_i_1_n_5\,
      \zq_cntrl.zq_timer.zq_timer_r_reg[11]_0\(1) => \zq_cntrl.zq_timer.zq_timer_r_reg[8]_i_1_n_6\,
      \zq_cntrl.zq_timer.zq_timer_r_reg[11]_0\(0) => \zq_cntrl.zq_timer.zq_timer_r_reg[8]_i_1_n_7\,
      \zq_cntrl.zq_timer.zq_timer_r_reg[15]\(3) => rank_mach0_n_52,
      \zq_cntrl.zq_timer.zq_timer_r_reg[15]\(2) => rank_mach0_n_53,
      \zq_cntrl.zq_timer.zq_timer_r_reg[15]\(1) => rank_mach0_n_54,
      \zq_cntrl.zq_timer.zq_timer_r_reg[15]\(0) => rank_mach0_n_55,
      \zq_cntrl.zq_timer.zq_timer_r_reg[15]_0\(3) => \zq_cntrl.zq_timer.zq_timer_r_reg[12]_i_1_n_4\,
      \zq_cntrl.zq_timer.zq_timer_r_reg[15]_0\(2) => \zq_cntrl.zq_timer.zq_timer_r_reg[12]_i_1_n_5\,
      \zq_cntrl.zq_timer.zq_timer_r_reg[15]_0\(1) => \zq_cntrl.zq_timer.zq_timer_r_reg[12]_i_1_n_6\,
      \zq_cntrl.zq_timer.zq_timer_r_reg[15]_0\(0) => \zq_cntrl.zq_timer.zq_timer_r_reg[12]_i_1_n_7\,
      \zq_cntrl.zq_timer.zq_timer_r_reg[19]\(3) => rank_mach0_n_56,
      \zq_cntrl.zq_timer.zq_timer_r_reg[19]\(2) => rank_mach0_n_57,
      \zq_cntrl.zq_timer.zq_timer_r_reg[19]\(1) => rank_mach0_n_58,
      \zq_cntrl.zq_timer.zq_timer_r_reg[19]\(0) => rank_mach0_n_59,
      \zq_cntrl.zq_timer.zq_timer_r_reg[19]_0\(3) => \zq_cntrl.zq_timer.zq_timer_r_reg[16]_i_1_n_4\,
      \zq_cntrl.zq_timer.zq_timer_r_reg[19]_0\(2) => \zq_cntrl.zq_timer.zq_timer_r_reg[16]_i_1_n_5\,
      \zq_cntrl.zq_timer.zq_timer_r_reg[19]_0\(1) => \zq_cntrl.zq_timer.zq_timer_r_reg[16]_i_1_n_6\,
      \zq_cntrl.zq_timer.zq_timer_r_reg[19]_0\(0) => \zq_cntrl.zq_timer.zq_timer_r_reg[16]_i_1_n_7\,
      \zq_cntrl.zq_timer.zq_timer_r_reg[7]\(3) => rank_mach0_n_44,
      \zq_cntrl.zq_timer.zq_timer_r_reg[7]\(2) => rank_mach0_n_45,
      \zq_cntrl.zq_timer.zq_timer_r_reg[7]\(1) => rank_mach0_n_46,
      \zq_cntrl.zq_timer.zq_timer_r_reg[7]\(0) => rank_mach0_n_47,
      \zq_cntrl.zq_timer.zq_timer_r_reg[7]_0\(3) => \zq_cntrl.zq_timer.zq_timer_r_reg[4]_i_1_n_4\,
      \zq_cntrl.zq_timer.zq_timer_r_reg[7]_0\(2) => \zq_cntrl.zq_timer.zq_timer_r_reg[4]_i_1_n_5\,
      \zq_cntrl.zq_timer.zq_timer_r_reg[7]_0\(1) => \zq_cntrl.zq_timer.zq_timer_r_reg[4]_i_1_n_6\,
      \zq_cntrl.zq_timer.zq_timer_r_reg[7]_0\(0) => \zq_cntrl.zq_timer.zq_timer_r_reg[4]_i_1_n_7\
    );
\zq_cntrl.zq_timer.zq_timer_r_reg[0]_i_3\: unisim.vcomponents.CARRY4
     port map (
      CI => '0',
      CO(3) => \zq_cntrl.zq_timer.zq_timer_r_reg[0]_i_3_n_0\,
      CO(2) => \zq_cntrl.zq_timer.zq_timer_r_reg[0]_i_3_n_1\,
      CO(1) => \zq_cntrl.zq_timer.zq_timer_r_reg[0]_i_3_n_2\,
      CO(0) => \zq_cntrl.zq_timer.zq_timer_r_reg[0]_i_3_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"1111",
      O(3) => \zq_cntrl.zq_timer.zq_timer_r_reg[0]_i_3_n_4\,
      O(2) => \zq_cntrl.zq_timer.zq_timer_r_reg[0]_i_3_n_5\,
      O(1) => \zq_cntrl.zq_timer.zq_timer_r_reg[0]_i_3_n_6\,
      O(0) => \zq_cntrl.zq_timer.zq_timer_r_reg[0]_i_3_n_7\,
      S(3) => rank_mach0_n_40,
      S(2) => rank_mach0_n_41,
      S(1) => rank_mach0_n_42,
      S(0) => rank_mach0_n_43
    );
\zq_cntrl.zq_timer.zq_timer_r_reg[12]_i_1\: unisim.vcomponents.CARRY4
     port map (
      CI => \zq_cntrl.zq_timer.zq_timer_r_reg[8]_i_1_n_0\,
      CO(3) => \zq_cntrl.zq_timer.zq_timer_r_reg[12]_i_1_n_0\,
      CO(2) => \zq_cntrl.zq_timer.zq_timer_r_reg[12]_i_1_n_1\,
      CO(1) => \zq_cntrl.zq_timer.zq_timer_r_reg[12]_i_1_n_2\,
      CO(0) => \zq_cntrl.zq_timer.zq_timer_r_reg[12]_i_1_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"1111",
      O(3) => \zq_cntrl.zq_timer.zq_timer_r_reg[12]_i_1_n_4\,
      O(2) => \zq_cntrl.zq_timer.zq_timer_r_reg[12]_i_1_n_5\,
      O(1) => \zq_cntrl.zq_timer.zq_timer_r_reg[12]_i_1_n_6\,
      O(0) => \zq_cntrl.zq_timer.zq_timer_r_reg[12]_i_1_n_7\,
      S(3) => rank_mach0_n_52,
      S(2) => rank_mach0_n_53,
      S(1) => rank_mach0_n_54,
      S(0) => rank_mach0_n_55
    );
\zq_cntrl.zq_timer.zq_timer_r_reg[16]_i_1\: unisim.vcomponents.CARRY4
     port map (
      CI => \zq_cntrl.zq_timer.zq_timer_r_reg[12]_i_1_n_0\,
      CO(3) => \NLW_zq_cntrl.zq_timer.zq_timer_r_reg[16]_i_1_CO_UNCONNECTED\(3),
      CO(2) => \zq_cntrl.zq_timer.zq_timer_r_reg[16]_i_1_n_1\,
      CO(1) => \zq_cntrl.zq_timer.zq_timer_r_reg[16]_i_1_n_2\,
      CO(0) => \zq_cntrl.zq_timer.zq_timer_r_reg[16]_i_1_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0111",
      O(3) => \zq_cntrl.zq_timer.zq_timer_r_reg[16]_i_1_n_4\,
      O(2) => \zq_cntrl.zq_timer.zq_timer_r_reg[16]_i_1_n_5\,
      O(1) => \zq_cntrl.zq_timer.zq_timer_r_reg[16]_i_1_n_6\,
      O(0) => \zq_cntrl.zq_timer.zq_timer_r_reg[16]_i_1_n_7\,
      S(3) => rank_mach0_n_56,
      S(2) => rank_mach0_n_57,
      S(1) => rank_mach0_n_58,
      S(0) => rank_mach0_n_59
    );
\zq_cntrl.zq_timer.zq_timer_r_reg[4]_i_1\: unisim.vcomponents.CARRY4
     port map (
      CI => \zq_cntrl.zq_timer.zq_timer_r_reg[0]_i_3_n_0\,
      CO(3) => \zq_cntrl.zq_timer.zq_timer_r_reg[4]_i_1_n_0\,
      CO(2) => \zq_cntrl.zq_timer.zq_timer_r_reg[4]_i_1_n_1\,
      CO(1) => \zq_cntrl.zq_timer.zq_timer_r_reg[4]_i_1_n_2\,
      CO(0) => \zq_cntrl.zq_timer.zq_timer_r_reg[4]_i_1_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"1111",
      O(3) => \zq_cntrl.zq_timer.zq_timer_r_reg[4]_i_1_n_4\,
      O(2) => \zq_cntrl.zq_timer.zq_timer_r_reg[4]_i_1_n_5\,
      O(1) => \zq_cntrl.zq_timer.zq_timer_r_reg[4]_i_1_n_6\,
      O(0) => \zq_cntrl.zq_timer.zq_timer_r_reg[4]_i_1_n_7\,
      S(3) => rank_mach0_n_44,
      S(2) => rank_mach0_n_45,
      S(1) => rank_mach0_n_46,
      S(0) => rank_mach0_n_47
    );
\zq_cntrl.zq_timer.zq_timer_r_reg[8]_i_1\: unisim.vcomponents.CARRY4
     port map (
      CI => \zq_cntrl.zq_timer.zq_timer_r_reg[4]_i_1_n_0\,
      CO(3) => \zq_cntrl.zq_timer.zq_timer_r_reg[8]_i_1_n_0\,
      CO(2) => \zq_cntrl.zq_timer.zq_timer_r_reg[8]_i_1_n_1\,
      CO(1) => \zq_cntrl.zq_timer.zq_timer_r_reg[8]_i_1_n_2\,
      CO(0) => \zq_cntrl.zq_timer.zq_timer_r_reg[8]_i_1_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"1111",
      O(3) => \zq_cntrl.zq_timer.zq_timer_r_reg[8]_i_1_n_4\,
      O(2) => \zq_cntrl.zq_timer.zq_timer_r_reg[8]_i_1_n_5\,
      O(1) => \zq_cntrl.zq_timer.zq_timer_r_reg[8]_i_1_n_6\,
      O(0) => \zq_cntrl.zq_timer.zq_timer_r_reg[8]_i_1_n_7\,
      S(3) => rank_mach0_n_48,
      S(2) => rank_mach0_n_49,
      S(1) => rank_mach0_n_50,
      S(0) => rank_mach0_n_51
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mig_mig_7series_v4_2_ddr_phy_top is
  port (
    ddr3_reset_n : out STD_LOGIC;
    ddr3_cas_n : out STD_LOGIC;
    ddr3_ras_n : out STD_LOGIC;
    ddr3_we_n : out STD_LOGIC;
    ddr3_addr : out STD_LOGIC_VECTOR ( 13 downto 0 );
    ddr3_ba : out STD_LOGIC_VECTOR ( 2 downto 0 );
    ddr3_cs_n : out STD_LOGIC_VECTOR ( 0 to 0 );
    ddr3_odt : out STD_LOGIC_VECTOR ( 0 to 0 );
    ddr3_cke : out STD_LOGIC_VECTOR ( 0 to 0 );
    ddr3_dm : out STD_LOGIC_VECTOR ( 7 downto 0 );
    A_rst_primitives_reg : out STD_LOGIC;
    A_rst_primitives_reg_0 : out STD_LOGIC;
    A_rst_primitives_reg_1 : out STD_LOGIC;
    A_rst_primitives_reg_2 : out STD_LOGIC;
    A_rst_primitives_reg_3 : out STD_LOGIC;
    A_rst_primitives_reg_4 : out STD_LOGIC;
    A_rst_primitives_reg_5 : out STD_LOGIC;
    A_rst_primitives_reg_6 : out STD_LOGIC;
    phy_mc_ctl_full : out STD_LOGIC;
    rst_tmp : out STD_LOGIC;
    po_cnt_dec_reg : out STD_LOGIC;
    po_cnt_dec_2 : out STD_LOGIC;
    fine_adjust_reg : out STD_LOGIC;
    new_cnt_cpt_r_reg : out STD_LOGIC;
    rdlvl_stg1_start_reg : out STD_LOGIC;
    samp_edge_cnt0_en_r : out STD_LOGIC;
    pi_cnt_dec_reg : out STD_LOGIC;
    new_cnt_dqs_r_reg : out STD_LOGIC;
    prbs_rdlvl_done_pulse_reg : out STD_LOGIC;
    init_calib_complete : out STD_LOGIC;
    \init_calib_complete_reg_rep__12\ : out STD_LOGIC;
    \init_calib_complete_reg_rep__24\ : out STD_LOGIC;
    \init_calib_complete_reg_rep__25\ : out STD_LOGIC;
    \init_calib_complete_reg_rep__26\ : out STD_LOGIC;
    init_complete_r1_timing_reg : out STD_LOGIC;
    phy_mc_data_full : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_5\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_6\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_5\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_6\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_5\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_6\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_5\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_6\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_5\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_6\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_5\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_6\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_5\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_6\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_5\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_6\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_5\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_6\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_5\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_6\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_5\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_6\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_5\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_6\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_5\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_6\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_5\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_6\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_5\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_6\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_5\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_6\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_5\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_6\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_5\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_6\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_5\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_6\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_5\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_6\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_5\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_6\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_5\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_6\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_5\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_6\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_5\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_6\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_5\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_6\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_5\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_6\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_5\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_6\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_5\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_6\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_5\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_6\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_5\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_6\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_5\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_6\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_5\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_6\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_5\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_6\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_5\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_6\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_5\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_6\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_5\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_6\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_5\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_6\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_5\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_6\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_5\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_6\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_5\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_6\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_5\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_6\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_5\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_6\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_5\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_6\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_5\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_6\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_5\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_6\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_5\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_6\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_5\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_6\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_5\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_6\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_5\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_6\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_5\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_6\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_5\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_6\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_5\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_6\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_5\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_6\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_5\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_6\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_5\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_6\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_5\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_6\ : out STD_LOGIC;
    \init_calib_complete_reg_rep__26_0\ : out STD_LOGIC;
    app_rd_data_valid : out STD_LOGIC;
    \read_fifo.tail_r_reg[0]\ : out STD_LOGIC;
    \rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][0]\ : out STD_LOGIC;
    \rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][5]\ : out STD_LOGIC_VECTOR ( 5 downto 0 );
    \rank_final_loop[0].bank_final_loop[1].final_data_offset_mc_reg[0][6]\ : out STD_LOGIC;
    \rank_final_loop[0].bank_final_loop[1].final_data_offset_mc_reg[0][11]\ : out STD_LOGIC_VECTOR ( 5 downto 0 );
    \rank_final_loop[0].bank_final_loop[2].final_data_offset_mc_reg[0][12]\ : out STD_LOGIC;
    \rank_final_loop[0].bank_final_loop[2].final_data_offset_mc_reg[0][17]\ : out STD_LOGIC_VECTOR ( 5 downto 0 );
    \init_state_r_reg[4]\ : out STD_LOGIC;
    ddr_ck_out : out STD_LOGIC_VECTOR ( 1 downto 0 );
    of_ctl_full_v : out STD_LOGIC_VECTOR ( 0 to 0 );
    ddr3_dq : inout STD_LOGIC_VECTOR ( 63 downto 0 );
    ddr3_dqs_p : inout STD_LOGIC_VECTOR ( 7 downto 0 );
    ddr3_dqs_n : inout STD_LOGIC_VECTOR ( 7 downto 0 );
    idle : in STD_LOGIC;
    mmcm_ps_clk : in STD_LOGIC;
    rst_sync_r1 : in STD_LOGIC;
    \entry_cnt_reg[4]\ : in STD_LOGIC;
    freq_refclk : in STD_LOGIC;
    mem_refclk : in STD_LOGIC;
    sync_pulse : in STD_LOGIC;
    pll_locked : in STD_LOGIC;
    cal2_if_reset_reg : in STD_LOGIC;
    CLKB0 : in STD_LOGIC;
    CLKB0_7 : in STD_LOGIC;
    CLKB0_8 : in STD_LOGIC;
    CLKB0_9 : in STD_LOGIC;
    RST0 : in STD_LOGIC;
    SR : in STD_LOGIC_VECTOR ( 0 to 0 );
    CLKB0_10 : in STD_LOGIC;
    CLKB0_11 : in STD_LOGIC;
    CLKB0_12 : in STD_LOGIC;
    CLKB0_13 : in STD_LOGIC;
    \rstdiv2_sync_r_reg[11]\ : in STD_LOGIC;
    iodelay_ctrl_rdy : in STD_LOGIC_VECTOR ( 0 to 0 );
    \out\ : in STD_LOGIC;
    \fine_dec_cnt_reg[5]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \corse_inc_reg[6][2]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \wl_dqs_tap_count_r_reg[0][5][5]\ : in STD_LOGIC;
    po_en_stg2_f_reg : in STD_LOGIC;
    first_fail_detect_reg : in STD_LOGIC;
    \rdlvl_dqs_tap_cnt_r_reg[0][0][2]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \samp_edge_cnt1_r_reg[0]\ : in STD_LOGIC;
    \FSM_onehot_cal1_state_r_reg[7]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \samples_cnt_r_reg[0]\ : in STD_LOGIC;
    \en_cnt_div4.enable_wrlvl_cnt_reg[2]\ : in STD_LOGIC;
    \victim_sel_reg[0]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \four_dec_min_limit_reg[0]\ : in STD_LOGIC;
    mc_ref_zq_wip : in STD_LOGIC;
    \one_dec_min_limit_reg[11]\ : in STD_LOGIC;
    \one_dec_max_limit_reg[2]\ : in STD_LOGIC;
    \idelay_tap_cnt_r_reg[0][0][4]\ : in STD_LOGIC;
    \not_empty_wait_cnt_reg[4]\ : in STD_LOGIC;
    \complex_num_writes_reg[1]\ : in STD_LOGIC;
    d_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
    Q : in STD_LOGIC_VECTOR ( 575 downto 0 );
    mc_address : in STD_LOGIC_VECTOR ( 38 downto 0 );
    mc_ras_n : in STD_LOGIC_VECTOR ( 2 downto 0 );
    mc_cas_n : in STD_LOGIC_VECTOR ( 2 downto 0 );
    mc_bank : in STD_LOGIC_VECTOR ( 8 downto 0 );
    mc_odt : in STD_LOGIC_VECTOR ( 0 to 0 );
    mc_cke : in STD_LOGIC_VECTOR ( 0 to 0 );
    mc_we_n : in STD_LOGIC_VECTOR ( 2 downto 0 );
    mc_cs_n : in STD_LOGIC_VECTOR ( 0 to 0 );
    app_rd_data_valid_0 : in STD_LOGIC_VECTOR ( 0 to 0 );
    \read_fifo.tail_r\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \idelay_tap_cnt_r_reg[0][4][4]\ : in STD_LOGIC;
    \pi_rst_stg1_cal_r_reg[1]\ : in STD_LOGIC;
    \cmp_err_4to1.compare_err_f3_reg\ : in STD_LOGIC;
    phy_dout : in STD_LOGIC_VECTOR ( 6 downto 0 );
    \fine_inc_reg[6][3]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \corse_dec_reg[7][0]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    SS : in STD_LOGIC_VECTOR ( 0 to 0 );
    \wait_cnt_r_reg[0]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \tap_cnt_cpt_r_reg[5]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \cnt_shift_r_reg[0]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \wait_cnt_r_reg[0]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \en_cnt_div4.enable_wrlvl_cnt_reg[4]\ : in STD_LOGIC;
    \device_temp_101_reg[11]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
    \data_offset_1_i1_reg[0]\ : in STD_LOGIC;
    \data_offset_1_i1_reg[1]\ : in STD_LOGIC;
    \data_offset_1_i1_reg[2]\ : in STD_LOGIC;
    mc_data_offset_1 : in STD_LOGIC_VECTOR ( 0 to 0 );
    \data_offset_1_i1_reg[4]\ : in STD_LOGIC;
    \data_offset_1_i1_reg[5]\ : in STD_LOGIC;
    \data_offset_2_i1_reg[0]\ : in STD_LOGIC;
    \data_offset_2_i1_reg[1]\ : in STD_LOGIC;
    \data_offset_2_i1_reg[2]\ : in STD_LOGIC;
    mc_data_offset_2 : in STD_LOGIC_VECTOR ( 0 to 0 );
    \data_offset_2_i1_reg[4]\ : in STD_LOGIC;
    \data_offset_2_i1_reg[5]\ : in STD_LOGIC;
    mc_cmd : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \phy_ctl_wd_i1_reg[17]\ : in STD_LOGIC;
    \phy_ctl_wd_i1_reg[18]\ : in STD_LOGIC;
    \phy_ctl_wd_i1_reg[19]\ : in STD_LOGIC;
    mc_data_offset : in STD_LOGIC_VECTOR ( 0 to 0 );
    \phy_ctl_wd_i1_reg[21]\ : in STD_LOGIC;
    \phy_ctl_wd_i1_reg[22]\ : in STD_LOGIC;
    mc_wrdata_en : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of mig_mig_7series_v4_2_ddr_phy_top : entity is "mig_7series_v4_2_ddr_phy_top";
end mig_mig_7series_v4_2_ddr_phy_top;

architecture STRUCTURE of mig_mig_7series_v4_2_ddr_phy_top is
  signal calib_sel : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal data_offset_1 : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal data_offset_2 : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal \ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl/rd_mux_sel_r\ : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_0\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_1\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_2\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_3\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_4\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_5\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_6\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_1\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_2\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_3\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_4\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_5\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_6\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_0\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_1\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_2\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_3\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_4\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_5\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_6\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_1\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_2\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_3\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_4\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_5\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_6\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_0\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_1\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_2\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_3\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_4\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_5\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_6\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_1\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_2\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_3\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_4\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_5\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_6\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_0\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_1\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_2\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_3\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_4\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_0\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_1\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_2\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_3\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_4\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_5\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_6\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_0\ : STD_LOGIC;
  signal idelay_inc : STD_LOGIC;
  signal if_empty : STD_LOGIC;
  signal \^init_calib_complete\ : STD_LOGIC;
  signal \^init_calib_complete_reg_rep__26\ : STD_LOGIC;
  signal mux_address : STD_LOGIC_VECTOR ( 54 downto 0 );
  signal mux_bank : STD_LOGIC_VECTOR ( 11 downto 0 );
  signal mux_cas_n : STD_LOGIC_VECTOR ( 1 to 1 );
  signal mux_cke : STD_LOGIC_VECTOR ( 3 to 3 );
  signal mux_cs_n : STD_LOGIC_VECTOR ( 1 to 1 );
  signal mux_odt : STD_LOGIC_VECTOR ( 0 to 0 );
  signal mux_ras_n : STD_LOGIC_VECTOR ( 1 to 1 );
  signal mux_reset_n : STD_LOGIC;
  signal mux_we_n : STD_LOGIC_VECTOR ( 1 to 1 );
  signal mux_wrdata : STD_LOGIC_VECTOR ( 511 downto 0 );
  signal mux_wrdata_mask : STD_LOGIC_VECTOR ( 63 downto 0 );
  signal phy_cmd_wr_en : STD_LOGIC;
  signal phy_ctl_wd : STD_LOGIC_VECTOR ( 24 downto 0 );
  signal phy_data_wr_en : STD_LOGIC;
  signal phy_if_reset : STD_LOGIC;
  signal phy_mc_go : STD_LOGIC;
  signal phy_rddata_en : STD_LOGIC;
  signal phy_read_calib : STD_LOGIC;
  signal phy_write_calib : STD_LOGIC;
  signal pi_counter_load_en : STD_LOGIC;
  attribute async_reg : string;
  attribute async_reg of pi_counter_load_en : signal is "true";
  signal pi_counter_load_val : STD_LOGIC_VECTOR ( 5 downto 0 );
  attribute async_reg of pi_counter_load_val : signal is "true";
  signal pi_dqs_find_rst : STD_LOGIC_VECTOR ( 2 downto 0 );
  attribute async_reg of pi_dqs_find_rst : signal is "true";
  signal pi_enstg2_f_div2r1 : STD_LOGIC;
  attribute async_reg of pi_enstg2_f_div2r1 : signal is "true";
  signal pi_enstg2_f_div2r2 : STD_LOGIC;
  attribute async_reg of pi_enstg2_f_div2r2 : signal is "true";
  signal pi_enstg2_f_div2r3 : STD_LOGIC;
  attribute async_reg of pi_enstg2_f_div2r3 : signal is "true";
  signal pi_fine_enable : STD_LOGIC;
  attribute async_reg of pi_fine_enable : signal is "true";
  signal pi_fine_inc : STD_LOGIC;
  attribute async_reg of pi_fine_inc : signal is "true";
  signal pi_rst_dqs_find : STD_LOGIC_VECTOR ( 2 downto 0 );
  attribute async_reg of pi_rst_dqs_find : signal is "true";
  signal pi_stg2_fincdec_div2r1 : STD_LOGIC;
  attribute async_reg of pi_stg2_fincdec_div2r1 : signal is "true";
  signal pi_stg2_fincdec_div2r2 : STD_LOGIC;
  attribute async_reg of pi_stg2_fincdec_div2r2 : signal is "true";
  signal pi_stg2_fincdec_div2r3 : STD_LOGIC;
  attribute async_reg of pi_stg2_fincdec_div2r3 : signal is "true";
  signal pi_stg2_load_div2r1 : STD_LOGIC;
  attribute async_reg of pi_stg2_load_div2r1 : signal is "true";
  signal pi_stg2_load_div2r2 : STD_LOGIC;
  attribute async_reg of pi_stg2_load_div2r2 : signal is "true";
  signal pi_stg2_load_div2r3 : STD_LOGIC;
  attribute async_reg of pi_stg2_load_div2r3 : signal is "true";
  signal pi_stg2_reg_l_div2r1 : STD_LOGIC_VECTOR ( 5 downto 0 );
  attribute async_reg of pi_stg2_reg_l_div2r1 : signal is "true";
  signal pi_stg2_reg_l_div2r2 : STD_LOGIC_VECTOR ( 5 downto 0 );
  attribute async_reg of pi_stg2_reg_l_div2r2 : signal is "true";
  signal pi_stg2_reg_l_div2r3 : STD_LOGIC_VECTOR ( 5 downto 0 );
  attribute async_reg of pi_stg2_reg_l_div2r3 : signal is "true";
  signal po_stg2_wrcal_cnt : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal rst_stg1_cal_div2r1 : STD_LOGIC_VECTOR ( 2 downto 0 );
  attribute async_reg of rst_stg1_cal_div2r1 : signal is "true";
  signal rst_stg1_cal_div2r2 : STD_LOGIC_VECTOR ( 2 downto 0 );
  attribute async_reg of rst_stg1_cal_div2r2 : signal is "true";
  signal u_ddr_calib_top_n_1373 : STD_LOGIC;
  signal u_ddr_calib_top_n_52 : STD_LOGIC;
  attribute MAX_FANOUT : string;
  attribute MAX_FANOUT of u_ddr_calib_top_n_52 : signal is "50";
  attribute RTL_MAX_FANOUT : string;
  attribute RTL_MAX_FANOUT of u_ddr_calib_top_n_52 : signal is "found";
  attribute syn_maxfan : string;
  attribute syn_maxfan of u_ddr_calib_top_n_52 : signal is "10";
  signal u_ddr_calib_top_n_53 : STD_LOGIC;
  attribute MAX_FANOUT of u_ddr_calib_top_n_53 : signal is "50";
  attribute RTL_MAX_FANOUT of u_ddr_calib_top_n_53 : signal is "found";
  attribute syn_maxfan of u_ddr_calib_top_n_53 : signal is "10";
  signal u_ddr_calib_top_n_54 : STD_LOGIC;
  attribute MAX_FANOUT of u_ddr_calib_top_n_54 : signal is "50";
  attribute RTL_MAX_FANOUT of u_ddr_calib_top_n_54 : signal is "found";
  attribute syn_maxfan of u_ddr_calib_top_n_54 : signal is "10";
  signal u_ddr_calib_top_n_64 : STD_LOGIC;
  signal u_ddr_calib_top_n_65 : STD_LOGIC;
  signal u_ddr_calib_top_n_66 : STD_LOGIC;
  signal u_ddr_calib_top_n_680 : STD_LOGIC;
  signal u_ddr_calib_top_n_681 : STD_LOGIC;
  signal u_ddr_calib_top_n_682 : STD_LOGIC;
  signal u_ddr_calib_top_n_683 : STD_LOGIC;
  signal u_ddr_calib_top_n_684 : STD_LOGIC;
  signal u_ddr_calib_top_n_685 : STD_LOGIC;
  signal u_ddr_calib_top_n_686 : STD_LOGIC;
  signal u_ddr_calib_top_n_687 : STD_LOGIC;
  signal u_ddr_calib_top_n_688 : STD_LOGIC;
  signal u_ddr_calib_top_n_689 : STD_LOGIC;
  signal u_ddr_calib_top_n_690 : STD_LOGIC;
  signal u_ddr_calib_top_n_691 : STD_LOGIC;
  signal u_ddr_calib_top_n_692 : STD_LOGIC;
  signal u_ddr_calib_top_n_693 : STD_LOGIC;
  signal u_ddr_calib_top_n_694 : STD_LOGIC;
  signal u_ddr_calib_top_n_695 : STD_LOGIC;
  signal u_ddr_calib_top_n_696 : STD_LOGIC;
  signal u_ddr_calib_top_n_697 : STD_LOGIC;
  signal u_ddr_calib_top_n_698 : STD_LOGIC;
  signal u_ddr_calib_top_n_699 : STD_LOGIC;
  signal u_ddr_calib_top_n_700 : STD_LOGIC;
  signal u_ddr_calib_top_n_701 : STD_LOGIC;
  signal u_ddr_calib_top_n_702 : STD_LOGIC;
  signal u_ddr_calib_top_n_703 : STD_LOGIC;
  signal u_ddr_calib_top_n_704 : STD_LOGIC;
  signal u_ddr_calib_top_n_705 : STD_LOGIC;
  signal u_ddr_calib_top_n_706 : STD_LOGIC;
  signal u_ddr_calib_top_n_707 : STD_LOGIC;
  signal u_ddr_calib_top_n_708 : STD_LOGIC;
  signal u_ddr_calib_top_n_709 : STD_LOGIC;
  signal u_ddr_calib_top_n_710 : STD_LOGIC;
  signal u_ddr_calib_top_n_711 : STD_LOGIC;
  signal u_ddr_calib_top_n_712 : STD_LOGIC;
  signal u_ddr_calib_top_n_713 : STD_LOGIC;
  signal u_ddr_calib_top_n_714 : STD_LOGIC;
  signal u_ddr_calib_top_n_715 : STD_LOGIC;
  signal u_ddr_calib_top_n_716 : STD_LOGIC;
  signal u_ddr_calib_top_n_717 : STD_LOGIC;
  signal u_ddr_calib_top_n_718 : STD_LOGIC;
  signal u_ddr_calib_top_n_719 : STD_LOGIC;
  signal u_ddr_calib_top_n_720 : STD_LOGIC;
  signal u_ddr_calib_top_n_721 : STD_LOGIC;
  signal u_ddr_calib_top_n_722 : STD_LOGIC;
  signal u_ddr_calib_top_n_723 : STD_LOGIC;
  signal u_ddr_calib_top_n_724 : STD_LOGIC;
  signal u_ddr_calib_top_n_725 : STD_LOGIC;
  signal u_ddr_calib_top_n_726 : STD_LOGIC;
  signal u_ddr_calib_top_n_727 : STD_LOGIC;
  signal u_ddr_calib_top_n_728 : STD_LOGIC;
  signal u_ddr_calib_top_n_729 : STD_LOGIC;
  signal u_ddr_calib_top_n_730 : STD_LOGIC;
  signal u_ddr_calib_top_n_731 : STD_LOGIC;
  signal u_ddr_calib_top_n_732 : STD_LOGIC;
  signal u_ddr_calib_top_n_733 : STD_LOGIC;
  signal u_ddr_calib_top_n_734 : STD_LOGIC;
  signal u_ddr_calib_top_n_735 : STD_LOGIC;
  signal u_ddr_calib_top_n_736 : STD_LOGIC;
  signal u_ddr_calib_top_n_737 : STD_LOGIC;
  signal u_ddr_calib_top_n_738 : STD_LOGIC;
  signal u_ddr_calib_top_n_739 : STD_LOGIC;
  signal u_ddr_calib_top_n_740 : STD_LOGIC;
  signal u_ddr_calib_top_n_741 : STD_LOGIC;
  signal u_ddr_calib_top_n_742 : STD_LOGIC;
  signal u_ddr_calib_top_n_743 : STD_LOGIC;
  signal u_ddr_calib_top_n_745 : STD_LOGIC;
  signal u_ddr_calib_top_n_746 : STD_LOGIC;
  signal u_ddr_calib_top_n_748 : STD_LOGIC;
  signal u_ddr_calib_top_n_749 : STD_LOGIC;
  signal u_ddr_calib_top_n_750 : STD_LOGIC;
  signal u_ddr_calib_top_n_751 : STD_LOGIC;
  signal u_ddr_calib_top_n_753 : STD_LOGIC;
  signal u_ddr_calib_top_n_754 : STD_LOGIC;
  signal u_ddr_calib_top_n_755 : STD_LOGIC;
  signal u_ddr_calib_top_n_756 : STD_LOGIC;
  signal u_ddr_calib_top_n_757 : STD_LOGIC;
  signal u_ddr_calib_top_n_758 : STD_LOGIC;
  signal u_ddr_calib_top_n_759 : STD_LOGIC;
  signal u_ddr_calib_top_n_760 : STD_LOGIC;
  signal u_ddr_calib_top_n_762 : STD_LOGIC;
  signal u_ddr_calib_top_n_763 : STD_LOGIC;
  signal \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/A_pi_counter_load_val\ : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/B_pi_counter_load_val\ : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/C_pi_counter_load_val\ : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/D_pi_counter_load_val\ : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/LD0\ : STD_LOGIC;
  signal \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/idelay_ld_rst\ : STD_LOGIC;
  signal \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d1\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d2\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d3\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d4\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d5\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d6\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d7\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d9\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/ddr_byte_group_io/LD0\ : STD_LOGIC;
  signal \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/ddr_byte_group_io/idelay_ld_rst\ : STD_LOGIC;
  signal \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d2\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d3\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d4\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d5\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d6\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d7\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d8\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d9\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/LD0\ : STD_LOGIC;
  signal \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/idelay_ld_rst\ : STD_LOGIC;
  signal \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d2\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d3\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d4\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d5\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d6\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d7\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d8\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d9\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/LD0\ : STD_LOGIC;
  signal \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/idelay_ld_rst\ : STD_LOGIC;
  signal \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d2\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d3\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d4\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d5\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d6\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d7\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d8\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d9\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/C_po_coarse_enable26_out\ : STD_LOGIC;
  signal \u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/C_po_counter_read_en38_out\ : STD_LOGIC;
  signal \u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/C_po_fine_enable23_out\ : STD_LOGIC;
  signal \u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/C_po_fine_inc29_out\ : STD_LOGIC;
  signal \u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d2\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d4\ : STD_LOGIC_VECTOR ( 1 to 1 );
  signal \u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d5\ : STD_LOGIC_VECTOR ( 5 downto 1 );
  signal \u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d6\ : STD_LOGIC_VECTOR ( 5 to 5 );
  signal \u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d7\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out\ : STD_LOGIC_VECTOR ( 75 downto 32 );
  signal \u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d4\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d5\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d6\ : STD_LOGIC_VECTOR ( 7 downto 4 );
  signal \u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d8\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d9\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d1\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d3\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d4\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d5\ : STD_LOGIC_VECTOR ( 7 downto 4 );
  signal \u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d6\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d7\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d8\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d9\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/mem_out\ : STD_LOGIC_VECTOR ( 59 downto 16 );
  signal \u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/A_pi_counter_load_val\ : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal \u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/B_pi_counter_load_val\ : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal \u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/C_pi_counter_load_val\ : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal \u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/D_pi_counter_load_val\ : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal \u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/LD0\ : STD_LOGIC;
  signal \u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/idelay_ld_rst\ : STD_LOGIC;
  signal \u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d1\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d2\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d3\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d4\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d5\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d6\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d7\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d9\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/ddr_byte_group_io/LD0\ : STD_LOGIC;
  signal \u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/ddr_byte_group_io/idelay_ld_rst\ : STD_LOGIC;
  signal \u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d2\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d3\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d4\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d5\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d6\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d7\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d8\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d9\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/LD0\ : STD_LOGIC;
  signal \u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/idelay_ld_rst\ : STD_LOGIC;
  signal \u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d2\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d3\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d4\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d5\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d6\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d7\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d8\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d9\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/LD0\ : STD_LOGIC;
  signal \u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/idelay_ld_rst\ : STD_LOGIC;
  signal \u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d2\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d3\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d4\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d5\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d6\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d7\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d8\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d9\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \u_ddr_mc_phy/pi_counter_read_val_w[0]_1\ : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal \u_ddr_mc_phy/pi_counter_read_val_w[2]_3\ : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal u_ddr_mc_phy_wrapper_n_1000 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1001 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1002 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1003 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1004 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1005 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1006 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1007 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1008 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1009 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1010 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1011 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1012 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1013 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1014 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1015 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1016 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1017 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1018 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1019 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1020 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1021 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1022 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1023 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1024 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1025 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1026 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1027 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1028 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1029 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1030 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1031 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1032 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1033 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1034 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1035 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1036 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1037 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1038 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1039 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1040 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1041 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1042 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1043 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1044 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1045 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1046 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1047 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1048 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1049 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1050 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1051 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1052 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1053 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1054 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1055 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1056 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1057 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1058 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1059 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1060 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1061 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1062 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1063 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1064 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1065 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1066 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1067 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1068 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1069 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1070 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1071 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1072 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1073 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1074 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1075 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1076 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1077 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1078 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1079 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1080 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1081 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1082 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1083 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1084 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1085 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1086 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1087 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1088 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1089 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1090 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1091 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1092 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1093 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1094 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1095 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1096 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1097 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1098 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1099 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1100 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1101 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1102 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1103 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1104 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1105 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1106 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1107 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1108 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1109 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1110 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1111 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1112 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1113 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1114 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1115 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1116 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1117 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1118 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1119 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1120 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1121 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1122 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1123 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1124 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1125 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1126 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1127 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1128 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1129 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1130 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1131 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1132 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1133 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1134 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1135 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1136 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1137 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1138 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1139 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1140 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1141 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1142 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1143 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1144 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1145 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1146 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1147 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1148 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1149 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1150 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1151 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1152 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1153 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1154 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1155 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1156 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1157 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1158 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1159 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1160 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1161 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1162 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1163 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1164 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1165 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1166 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1167 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1168 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1169 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1170 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1171 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1172 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1173 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1174 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1175 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1176 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1177 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1184 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1185 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1186 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1187 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1188 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1189 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1190 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1191 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1192 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1193 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1194 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1195 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1196 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1197 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1198 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1199 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1200 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1201 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1202 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1203 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1204 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1205 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1206 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1207 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1208 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1209 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1210 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1211 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1212 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1213 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1214 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1215 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1216 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1217 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1218 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1219 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1221 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1222 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1223 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1224 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1225 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1226 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1227 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1228 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1229 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1230 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1231 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1232 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1233 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1234 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1235 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1236 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1237 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1238 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1239 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1240 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1241 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1242 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1243 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1244 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1245 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1246 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1247 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1248 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1249 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1250 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1251 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1252 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1253 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1254 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1255 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1256 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1257 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1258 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1259 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1260 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1261 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1262 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1263 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1264 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1265 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1266 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1267 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1268 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1269 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1270 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1271 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1272 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1273 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1274 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1275 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1276 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1277 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1278 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1279 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1280 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1281 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1282 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1283 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1284 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1285 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1286 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1287 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1288 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1289 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1290 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1291 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1292 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1293 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1295 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1296 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1297 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1298 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1299 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1300 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1301 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1302 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1303 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1304 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1305 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1306 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1307 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1308 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1309 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1310 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1311 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1312 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1313 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1314 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1315 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1316 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1317 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1318 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1319 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1320 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1321 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1322 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1323 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1324 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1325 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1326 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1327 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1328 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1329 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1330 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1331 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1332 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1333 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1334 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1335 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1336 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1337 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1338 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1339 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1340 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1341 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1342 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1343 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1344 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1345 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1346 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1347 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1348 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1349 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1350 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1351 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1352 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1353 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1354 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1355 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1356 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1357 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1360 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_33 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_34 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_35 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_36 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_37 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_38 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_39 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_40 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_59 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_595 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_596 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_597 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_598 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_599 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_600 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_601 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_602 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_603 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_604 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_605 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_606 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_607 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_608 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_609 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_61 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_610 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_611 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_612 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_613 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_614 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_615 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_616 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_617 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_618 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_619 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_62 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_620 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_621 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_622 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_623 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_624 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_625 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_626 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_627 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_628 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_629 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_63 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_630 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_631 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_632 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_633 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_634 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_635 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_636 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_637 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_638 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_639 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_64 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_640 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_641 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_642 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_643 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_644 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_645 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_646 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_647 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_648 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_649 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_65 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_650 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_651 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_652 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_653 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_654 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_655 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_656 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_657 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_658 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_66 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_660 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_661 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_662 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_663 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_664 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_665 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_666 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_667 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_668 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_669 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_67 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_670 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_671 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_672 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_673 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_674 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_675 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_676 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_677 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_678 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_679 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_68 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_680 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_681 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_682 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_683 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_684 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_685 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_686 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_687 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_688 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_689 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_69 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_690 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_691 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_692 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_693 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_694 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_695 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_696 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_697 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_698 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_699 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_70 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_700 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_701 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_702 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_703 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_704 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_705 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_706 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_707 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_708 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_709 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_710 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_711 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_712 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_713 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_714 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_715 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_716 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_717 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_718 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_719 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_720 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_721 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_722 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_723 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_724 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_725 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_726 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_727 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_728 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_729 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_730 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_731 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_732 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_733 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_734 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_735 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_736 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_737 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_738 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_739 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_740 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_741 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_742 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_743 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_744 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_745 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_746 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_747 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_748 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_749 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_750 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_751 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_752 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_753 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_754 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_755 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_756 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_757 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_758 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_759 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_760 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_761 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_762 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_763 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_764 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_765 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_766 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_767 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_768 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_769 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_770 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_771 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_772 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_773 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_774 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_775 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_776 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_777 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_778 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_779 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_780 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_781 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_782 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_783 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_784 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_785 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_786 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_787 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_788 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_789 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_790 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_791 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_792 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_793 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_794 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_795 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_796 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_797 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_798 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_799 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_800 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_801 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_802 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_803 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_804 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_805 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_806 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_807 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_808 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_809 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_810 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_811 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_812 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_813 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_814 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_815 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_816 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_817 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_818 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_819 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_820 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_821 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_822 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_823 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_824 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_825 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_826 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_827 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_828 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_829 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_830 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_831 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_832 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_833 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_834 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_835 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_836 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_837 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_838 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_839 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_840 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_841 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_842 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_843 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_844 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_845 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_846 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_847 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_848 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_849 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_850 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_851 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_852 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_853 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_854 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_855 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_856 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_857 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_858 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_859 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_860 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_861 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_862 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_863 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_864 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_865 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_866 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_867 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_868 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_869 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_870 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_871 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_872 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_873 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_874 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_875 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_876 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_877 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_878 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_879 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_880 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_881 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_882 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_883 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_884 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_885 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_886 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_887 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_888 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_889 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_890 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_891 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_892 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_893 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_894 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_895 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_896 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_897 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_898 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_899 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_900 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_901 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_902 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_903 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_904 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_905 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_906 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_907 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_908 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_909 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_910 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_911 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_912 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_913 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_914 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_915 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_922 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_923 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_924 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_925 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_926 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_927 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_928 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_929 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_930 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_931 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_932 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_933 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_934 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_935 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_936 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_937 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_938 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_939 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_940 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_941 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_942 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_943 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_944 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_945 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_946 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_947 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_948 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_949 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_950 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_951 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_952 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_953 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_954 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_955 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_956 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_957 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_958 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_959 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_960 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_961 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_962 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_963 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_964 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_965 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_966 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_967 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_968 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_969 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_970 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_971 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_972 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_973 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_974 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_975 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_976 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_977 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_978 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_979 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_980 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_981 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_982 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_983 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_984 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_985 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_986 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_987 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_988 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_989 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_990 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_991 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_992 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_993 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_994 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_995 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_996 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_997 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_998 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_999 : STD_LOGIC;
  signal \u_ddr_phy_wrcal/p_0_out\ : STD_LOGIC;
begin
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_0\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_0\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_1\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_1\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_2\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_2\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_3\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_3\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_4\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_4\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_5\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_5\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_6\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_6\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_1\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_1\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_2\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_2\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_3\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_3\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_4\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_4\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_5\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_5\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_6\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_6\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_0\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_0\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_1\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_1\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_2\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_2\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_3\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_3\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_4\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_4\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_5\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_5\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_6\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_6\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_1\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_1\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_2\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_2\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_3\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_3\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_4\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_4\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_5\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_5\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_6\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_6\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_0\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_0\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_1\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_1\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_2\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_2\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_3\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_3\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_4\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_4\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_5\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_5\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_6\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_6\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_1\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_1\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_2\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_2\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_3\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_3\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_4\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_4\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_5\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_5\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_6\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_6\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_0\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_0\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_1\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_1\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_2\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_2\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_3\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_3\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_4\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_4\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_0\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_0\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_1\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_1\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_2\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_2\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_3\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_3\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_4\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_4\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_5\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_5\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_6\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_6\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_0\ <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_0\;
  init_calib_complete <= \^init_calib_complete\;
  \init_calib_complete_reg_rep__26\ <= \^init_calib_complete_reg_rep__26\;
i_0: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => pi_enstg2_f_div2r1
    );
i_1: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => pi_enstg2_f_div2r2
    );
i_10: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => rst_stg1_cal_div2r1(1)
    );
i_11: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => rst_stg1_cal_div2r1(0)
    );
i_12: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => rst_stg1_cal_div2r2(2)
    );
i_13: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => rst_stg1_cal_div2r2(1)
    );
i_14: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => rst_stg1_cal_div2r2(0)
    );
i_15: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => pi_stg2_reg_l_div2r1(5)
    );
i_16: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => pi_stg2_reg_l_div2r1(4)
    );
i_17: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => pi_stg2_reg_l_div2r1(3)
    );
i_18: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => pi_stg2_reg_l_div2r1(2)
    );
i_19: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => pi_stg2_reg_l_div2r1(1)
    );
i_2: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => pi_enstg2_f_div2r3
    );
i_20: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => pi_stg2_reg_l_div2r1(0)
    );
i_21: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => pi_stg2_reg_l_div2r2(5)
    );
i_22: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => pi_stg2_reg_l_div2r2(4)
    );
i_23: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => pi_stg2_reg_l_div2r2(3)
    );
i_24: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => pi_stg2_reg_l_div2r2(2)
    );
i_25: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => pi_stg2_reg_l_div2r2(1)
    );
i_26: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => pi_stg2_reg_l_div2r2(0)
    );
i_27: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => pi_stg2_reg_l_div2r3(5)
    );
i_28: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => pi_stg2_reg_l_div2r3(4)
    );
i_29: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => pi_stg2_reg_l_div2r3(3)
    );
i_3: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => pi_stg2_fincdec_div2r1
    );
i_30: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => pi_stg2_reg_l_div2r3(2)
    );
i_31: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => pi_stg2_reg_l_div2r3(1)
    );
i_32: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => pi_stg2_reg_l_div2r3(0)
    );
i_33: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => pi_dqs_find_rst(2)
    );
i_34: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => pi_dqs_find_rst(1)
    );
i_35: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => pi_dqs_find_rst(0)
    );
i_4: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => pi_stg2_fincdec_div2r2
    );
i_5: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => pi_stg2_fincdec_div2r3
    );
i_6: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => pi_stg2_load_div2r1
    );
i_7: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => pi_stg2_load_div2r2
    );
i_8: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => pi_stg2_load_div2r3
    );
i_9: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => rst_stg1_cal_div2r1(2)
    );
u_ddr_calib_top: entity work.mig_mig_7series_v4_2_ddr_calib_top
     port map (
      COUNTERLOADVAL(5 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/A_pi_counter_load_val\(5 downto 0),
      C_po_coarse_enable26_out => \u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/C_po_coarse_enable26_out\,
      C_po_counter_read_en38_out => \u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/C_po_counter_read_en38_out\,
      C_po_fine_enable23_out => \u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/C_po_fine_enable23_out\,
      C_po_fine_inc29_out => \u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/C_po_fine_inc29_out\,
      D(10 downto 3) => phy_ctl_wd(24 downto 17),
      D(2 downto 0) => phy_ctl_wd(2 downto 0),
      D1(3 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d1\(3 downto 0),
      D2(7 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d2\(7 downto 0),
      D3(3 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d3\(3 downto 0),
      D4(3 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d4\(3 downto 0),
      D5(3 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d5\(7 downto 4),
      D6(7 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d6\(7 downto 0),
      D7(3 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d7\(3 downto 0),
      D8(3 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d8\(3 downto 0),
      D9(3 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d9\(3 downto 0),
      E(0) => new_cnt_dqs_r_reg,
      \FSM_onehot_cal1_state_r_reg[7]\(0) => \FSM_onehot_cal1_state_r_reg[7]\(0),
      LD0 => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/LD0\,
      LD0_0 => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/ddr_byte_group_io/LD0\,
      LD0_1 => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/LD0\,
      LD0_2 => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/LD0\,
      LD0_3 => \u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/LD0\,
      LD0_4 => \u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/ddr_byte_group_io/LD0\,
      LD0_5 => \u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/LD0\,
      LD0_6 => \u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/LD0\,
      Q(0) => phy_mc_go,
      SR(0) => u_ddr_calib_top_n_1373,
      SS(0) => SS(0),
      app_rd_data_valid => app_rd_data_valid,
      app_rd_data_valid_0(0) => app_rd_data_valid_0(0),
      cal2_if_reset_reg => cal2_if_reset_reg,
      calib_sel(3 downto 2) => calib_sel(4 downto 3),
      calib_sel(1 downto 0) => calib_sel(1 downto 0),
      \calib_sel_reg[0]_0\ => u_ddr_calib_top_n_693,
      \calib_sel_reg[0]_1\ => u_ddr_calib_top_n_707,
      \calib_sel_reg[0]_2\ => u_ddr_calib_top_n_709,
      \calib_sel_reg[0]_3\ => u_ddr_calib_top_n_710,
      \calib_sel_reg[0]_4\ => u_ddr_calib_top_n_725,
      \calib_sel_reg[0]_5\ => u_ddr_calib_top_n_739,
      \calib_sel_reg[0]_6\ => u_ddr_calib_top_n_741,
      \calib_sel_reg[0]_7\ => u_ddr_calib_top_n_742,
      \calib_sel_reg[1]_0\ => u_ddr_calib_top_n_680,
      \calib_sel_reg[1]_1\ => u_ddr_calib_top_n_681,
      \calib_sel_reg[1]_10\ => u_ddr_calib_top_n_691,
      \calib_sel_reg[1]_11\ => u_ddr_calib_top_n_692,
      \calib_sel_reg[1]_12\ => u_ddr_calib_top_n_694,
      \calib_sel_reg[1]_13\ => u_ddr_calib_top_n_695,
      \calib_sel_reg[1]_14\ => u_ddr_calib_top_n_696,
      \calib_sel_reg[1]_15\ => u_ddr_calib_top_n_697,
      \calib_sel_reg[1]_16\ => u_ddr_calib_top_n_698,
      \calib_sel_reg[1]_17\ => u_ddr_calib_top_n_699,
      \calib_sel_reg[1]_18\ => u_ddr_calib_top_n_700,
      \calib_sel_reg[1]_19\ => u_ddr_calib_top_n_701,
      \calib_sel_reg[1]_2\ => u_ddr_calib_top_n_682,
      \calib_sel_reg[1]_20\ => u_ddr_calib_top_n_702,
      \calib_sel_reg[1]_21\ => u_ddr_calib_top_n_703,
      \calib_sel_reg[1]_22\ => u_ddr_calib_top_n_704,
      \calib_sel_reg[1]_23\ => u_ddr_calib_top_n_705,
      \calib_sel_reg[1]_24\ => u_ddr_calib_top_n_712,
      \calib_sel_reg[1]_25\ => u_ddr_calib_top_n_713,
      \calib_sel_reg[1]_26\ => u_ddr_calib_top_n_714,
      \calib_sel_reg[1]_27\ => u_ddr_calib_top_n_715,
      \calib_sel_reg[1]_28\ => u_ddr_calib_top_n_716,
      \calib_sel_reg[1]_29\ => u_ddr_calib_top_n_717,
      \calib_sel_reg[1]_3\ => u_ddr_calib_top_n_683,
      \calib_sel_reg[1]_30\ => u_ddr_calib_top_n_718,
      \calib_sel_reg[1]_31\ => u_ddr_calib_top_n_719,
      \calib_sel_reg[1]_32\ => u_ddr_calib_top_n_720,
      \calib_sel_reg[1]_33\ => u_ddr_calib_top_n_722,
      \calib_sel_reg[1]_34\ => u_ddr_calib_top_n_723,
      \calib_sel_reg[1]_35\ => u_ddr_calib_top_n_724,
      \calib_sel_reg[1]_36\ => u_ddr_calib_top_n_726,
      \calib_sel_reg[1]_37\ => u_ddr_calib_top_n_727,
      \calib_sel_reg[1]_38\ => u_ddr_calib_top_n_728,
      \calib_sel_reg[1]_39\ => u_ddr_calib_top_n_729,
      \calib_sel_reg[1]_4\ => u_ddr_calib_top_n_684,
      \calib_sel_reg[1]_40\ => u_ddr_calib_top_n_730,
      \calib_sel_reg[1]_41\ => u_ddr_calib_top_n_731,
      \calib_sel_reg[1]_42\ => u_ddr_calib_top_n_732,
      \calib_sel_reg[1]_43\ => u_ddr_calib_top_n_733,
      \calib_sel_reg[1]_44\ => u_ddr_calib_top_n_734,
      \calib_sel_reg[1]_45\ => u_ddr_calib_top_n_735,
      \calib_sel_reg[1]_46\ => u_ddr_calib_top_n_736,
      \calib_sel_reg[1]_47\ => u_ddr_calib_top_n_737,
      \calib_sel_reg[1]_48\(5 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/B_pi_counter_load_val\(5 downto 0),
      \calib_sel_reg[1]_49\(5 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/C_pi_counter_load_val\(5 downto 0),
      \calib_sel_reg[1]_5\ => u_ddr_calib_top_n_685,
      \calib_sel_reg[1]_50\(5 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/A_pi_counter_load_val\(5 downto 0),
      \calib_sel_reg[1]_51\(5 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/B_pi_counter_load_val\(5 downto 0),
      \calib_sel_reg[1]_52\(5 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/C_pi_counter_load_val\(5 downto 0),
      \calib_sel_reg[1]_6\ => u_ddr_calib_top_n_686,
      \calib_sel_reg[1]_7\ => u_ddr_calib_top_n_687,
      \calib_sel_reg[1]_8\ => u_ddr_calib_top_n_688,
      \calib_sel_reg[1]_9\ => u_ddr_calib_top_n_690,
      \cmd_pipe_plus.mc_cas_n_reg[1]\(0) => \u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d4\(1),
      \cmd_pipe_plus.mc_cke_reg[3]\(3 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d7\(3 downto 0),
      \cmd_pipe_plus.mc_cke_reg[3]_0\(5) => mux_cke(3),
      \cmd_pipe_plus.mc_cke_reg[3]_0\(4) => mux_we_n(1),
      \cmd_pipe_plus.mc_cke_reg[3]_0\(3) => mux_ras_n(1),
      \cmd_pipe_plus.mc_cke_reg[3]_0\(2) => mux_cas_n(1),
      \cmd_pipe_plus.mc_cke_reg[3]_0\(1) => mux_cs_n(1),
      \cmd_pipe_plus.mc_cke_reg[3]_0\(0) => mux_odt(0),
      \cmd_pipe_plus.mc_data_offset_1_reg[5]\(5 downto 0) => data_offset_1(5 downto 0),
      \cmd_pipe_plus.mc_data_offset_2_reg[5]\(5 downto 0) => data_offset_2(5 downto 0),
      \cmd_pipe_plus.mc_odt_reg[0]\(3 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d2\(3 downto 0),
      \cmd_pipe_plus.mc_ras_n_reg[1]\(1) => \u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d5\(5),
      \cmd_pipe_plus.mc_ras_n_reg[1]\(0) => \u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d5\(1),
      \cmd_pipe_plus.mc_we_n_reg[1]\(0) => \u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d6\(5),
      \cmp_err_4to1.compare_err_f3_reg\ => \cmp_err_4to1.compare_err_f3_reg\,
      \cnt_shift_r_reg[0]\(0) => \cnt_shift_r_reg[0]\(0),
      \complex_num_writes_reg[1]\ => \complex_num_writes_reg[1]\,
      \corse_dec_reg[7][0]\(1 downto 0) => \corse_dec_reg[7][0]\(1 downto 0),
      \corse_inc_reg[6][2]\(1 downto 0) => \corse_inc_reg[6][2]\(1 downto 0),
      d_in(37) => mux_address(51),
      d_in(36) => mux_address(37),
      d_in(35) => mux_address(23),
      d_in(34) => mux_address(9),
      d_in(33) => mux_address(43),
      d_in(32) => mux_address(29),
      d_in(31) => mux_address(15),
      d_in(30) => mux_address(1),
      d_in(29) => mux_address(47),
      d_in(28) => mux_address(33),
      d_in(27) => mux_address(19),
      d_in(26) => mux_address(5),
      d_in(25) => mux_address(42),
      d_in(24) => mux_address(28),
      d_in(23) => mux_address(14),
      d_in(22) => mux_address(0),
      d_in(21) => mux_address(54),
      d_in(20) => mux_address(40),
      d_in(19) => mux_address(26),
      d_in(18) => mux_address(12),
      d_in(17) => mux_address(45),
      d_in(16) => mux_address(31),
      d_in(15) => mux_address(17),
      d_in(14) => mux_address(3),
      d_in(13) => \^init_calib_complete\,
      d_in(12) => mux_address(27),
      d_in(11) => mux_address(46),
      d_in(10) => mux_address(32),
      d_in(9) => mux_address(18),
      d_in(8) => mux_address(4),
      d_in(7) => mux_address(52),
      d_in(6) => mux_address(38),
      d_in(5) => mux_address(24),
      d_in(4) => mux_address(10),
      d_in(3) => mux_address(49),
      d_in(2) => mux_address(35),
      d_in(1) => mux_address(21),
      d_in(0) => mux_address(7),
      \data_offset_1_i1_reg[0]\ => \data_offset_1_i1_reg[0]\,
      \data_offset_1_i1_reg[1]\ => \data_offset_1_i1_reg[1]\,
      \data_offset_1_i1_reg[2]\ => \data_offset_1_i1_reg[2]\,
      \data_offset_1_i1_reg[4]\ => \data_offset_1_i1_reg[4]\,
      \data_offset_1_i1_reg[5]\ => \data_offset_1_i1_reg[5]\,
      \data_offset_2_i1_reg[0]\ => \data_offset_2_i1_reg[0]\,
      \data_offset_2_i1_reg[1]\ => \data_offset_2_i1_reg[1]\,
      \data_offset_2_i1_reg[2]\ => \data_offset_2_i1_reg[2]\,
      \data_offset_2_i1_reg[4]\ => \data_offset_2_i1_reg[4]\,
      \data_offset_2_i1_reg[5]\ => \data_offset_2_i1_reg[5]\,
      \device_temp_101_reg[11]\(11 downto 0) => \device_temp_101_reg[11]\(11 downto 0),
      \dout_o_reg[15]\ => \entry_cnt_reg[4]\,
      dqs_po_stg2_f_incdec_reg => u_ddr_calib_top_n_753,
      dqs_po_stg2_f_incdec_reg_0 => u_ddr_calib_top_n_754,
      dqs_po_stg2_f_incdec_reg_1 => u_ddr_calib_top_n_755,
      dqs_po_stg2_f_incdec_reg_2 => u_ddr_calib_top_n_756,
      dqs_po_stg2_f_incdec_reg_3 => u_ddr_calib_top_n_757,
      dqs_po_stg2_f_incdec_reg_4 => u_ddr_calib_top_n_758,
      dqs_po_stg2_f_incdec_reg_5 => u_ddr_calib_top_n_759,
      dqs_po_stg2_f_incdec_reg_6 => u_ddr_calib_top_n_760,
      dqs_po_stg2_f_incdec_reg_7 => u_ddr_calib_top_n_762,
      dqs_po_stg2_f_incdec_reg_8 => u_ddr_calib_top_n_763,
      dqs_wl_po_stg2_c_incdec_reg => u_ddr_calib_top_n_689,
      dqs_wl_po_stg2_c_incdec_reg_0 => u_ddr_calib_top_n_721,
      \en_cnt_div4.enable_wrlvl_cnt_reg[2]\ => \en_cnt_div4.enable_wrlvl_cnt_reg[2]\,
      \en_cnt_div4.enable_wrlvl_cnt_reg[4]\ => \en_cnt_div4.enable_wrlvl_cnt_reg[4]\,
      fine_adjust_reg => fine_adjust_reg,
      \fine_dec_cnt_reg[5]\(1 downto 0) => \fine_dec_cnt_reg[5]\(1 downto 0),
      \fine_inc_reg[6][3]\(1 downto 0) => \fine_inc_reg[6][3]\(1 downto 0),
      first_fail_detect_reg => first_fail_detect_reg,
      \four_dec_min_limit_reg[0]\ => \four_dec_min_limit_reg[0]\,
      \gen_byte_sel_div2.calib_in_common_reg_0\ => u_ddr_calib_top_n_745,
      \gen_byte_sel_div2.calib_in_common_reg_1\ => u_ddr_calib_top_n_746,
      \gen_byte_sel_div2.calib_in_common_reg_2\ => u_ddr_calib_top_n_748,
      \gen_byte_sel_div2.calib_in_common_reg_3\ => u_ddr_calib_top_n_749,
      \gen_byte_sel_div2.calib_in_common_reg_4\ => u_ddr_calib_top_n_750,
      \gen_byte_sel_div2.calib_in_common_reg_5\ => u_ddr_calib_top_n_751,
      \gen_mux_rd[0].mux_rd_fall0_r1_reg[0]\ => u_ddr_mc_phy_wrapper_n_1229,
      \gen_mux_rd[0].mux_rd_fall0_r_reg[0]\ => u_ddr_mc_phy_wrapper_n_646,
      \gen_mux_rd[0].mux_rd_fall1_r1_reg[0]\ => u_ddr_mc_phy_wrapper_n_1245,
      \gen_mux_rd[0].mux_rd_fall1_r_reg[0]\ => u_ddr_mc_phy_wrapper_n_651,
      \gen_mux_rd[0].mux_rd_fall2_r1_reg[0]\ => u_ddr_mc_phy_wrapper_n_1261,
      \gen_mux_rd[0].mux_rd_fall2_r_reg[0]\ => u_ddr_mc_phy_wrapper_n_655,
      \gen_mux_rd[0].mux_rd_fall3_r1_reg[0]\ => u_ddr_mc_phy_wrapper_n_1277,
      \gen_mux_rd[0].mux_rd_fall3_r_reg[0]\ => u_ddr_mc_phy_wrapper_n_636,
      \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]\ => u_ddr_mc_phy_wrapper_n_1221,
      \gen_mux_rd[0].mux_rd_rise0_r_reg[0]\ => u_ddr_mc_phy_wrapper_n_644,
      \gen_mux_rd[0].mux_rd_rise1_r1_reg[0]\ => u_ddr_mc_phy_wrapper_n_1237,
      \gen_mux_rd[0].mux_rd_rise1_r_reg[0]\ => u_ddr_mc_phy_wrapper_n_606,
      \gen_mux_rd[0].mux_rd_rise2_r1_reg[0]\ => u_ddr_mc_phy_wrapper_n_1253,
      \gen_mux_rd[0].mux_rd_rise2_r_reg[0]\ => u_ddr_mc_phy_wrapper_n_617,
      \gen_mux_rd[0].mux_rd_rise3_r1_reg[0]\ => u_ddr_mc_phy_wrapper_n_1269,
      \gen_mux_rd[0].mux_rd_rise3_r_reg[0]\ => u_ddr_mc_phy_wrapper_n_657,
      \gen_mux_rd[1].mux_rd_fall0_r1_reg[1]\ => u_ddr_mc_phy_wrapper_n_1230,
      \gen_mux_rd[1].mux_rd_fall0_r_reg[1]\ => u_ddr_mc_phy_wrapper_n_601,
      \gen_mux_rd[1].mux_rd_fall1_r1_reg[1]\ => u_ddr_mc_phy_wrapper_n_1246,
      \gen_mux_rd[1].mux_rd_fall1_r_reg[1]\ => u_ddr_mc_phy_wrapper_n_612,
      \gen_mux_rd[1].mux_rd_fall2_r1_reg[1]\ => u_ddr_mc_phy_wrapper_n_1262,
      \gen_mux_rd[1].mux_rd_fall2_r_reg[1]\ => u_ddr_mc_phy_wrapper_n_624,
      \gen_mux_rd[1].mux_rd_fall3_r1_reg[1]\ => u_ddr_mc_phy_wrapper_n_1278,
      \gen_mux_rd[1].mux_rd_fall3_r_reg[1]\ => u_ddr_mc_phy_wrapper_n_637,
      \gen_mux_rd[1].mux_rd_rise0_r1_reg[1]\ => u_ddr_mc_phy_wrapper_n_1222,
      \gen_mux_rd[1].mux_rd_rise0_r_reg[1]\ => u_ddr_mc_phy_wrapper_n_595,
      \gen_mux_rd[1].mux_rd_rise1_r1_reg[1]\ => u_ddr_mc_phy_wrapper_n_1238,
      \gen_mux_rd[1].mux_rd_rise1_r_reg[1]\ => u_ddr_mc_phy_wrapper_n_607,
      \gen_mux_rd[1].mux_rd_rise2_r1_reg[1]\ => u_ddr_mc_phy_wrapper_n_1254,
      \gen_mux_rd[1].mux_rd_rise2_r_reg[1]\ => u_ddr_mc_phy_wrapper_n_618,
      \gen_mux_rd[1].mux_rd_rise3_r1_reg[1]\ => u_ddr_mc_phy_wrapper_n_1270,
      \gen_mux_rd[1].mux_rd_rise3_r_reg[1]\ => u_ddr_mc_phy_wrapper_n_630,
      \gen_mux_rd[2].mux_rd_fall0_r1_reg[2]\ => u_ddr_mc_phy_wrapper_n_1231,
      \gen_mux_rd[2].mux_rd_fall0_r_reg[2]\ => u_ddr_mc_phy_wrapper_n_647,
      \gen_mux_rd[2].mux_rd_fall1_r1_reg[2]\ => u_ddr_mc_phy_wrapper_n_1247,
      \gen_mux_rd[2].mux_rd_fall1_r_reg[2]\ => u_ddr_mc_phy_wrapper_n_652,
      \gen_mux_rd[2].mux_rd_fall2_r1_reg[2]\ => u_ddr_mc_phy_wrapper_n_1263,
      \gen_mux_rd[2].mux_rd_fall2_r_reg[2]\ => u_ddr_mc_phy_wrapper_n_625,
      \gen_mux_rd[2].mux_rd_fall3_r1_reg[2]\ => u_ddr_mc_phy_wrapper_n_1279,
      \gen_mux_rd[2].mux_rd_fall3_r_reg[2]\ => u_ddr_mc_phy_wrapper_n_638,
      \gen_mux_rd[2].mux_rd_rise0_r1_reg[2]\ => u_ddr_mc_phy_wrapper_n_1223,
      \gen_mux_rd[2].mux_rd_rise0_r_reg[2]\ => u_ddr_mc_phy_wrapper_n_596,
      \gen_mux_rd[2].mux_rd_rise1_r1_reg[2]\ => u_ddr_mc_phy_wrapper_n_1239,
      \gen_mux_rd[2].mux_rd_rise1_r_reg[2]\ => u_ddr_mc_phy_wrapper_n_649,
      \gen_mux_rd[2].mux_rd_rise2_r1_reg[2]\ => u_ddr_mc_phy_wrapper_n_1255,
      \gen_mux_rd[2].mux_rd_rise2_r_reg[2]\ => u_ddr_mc_phy_wrapper_n_619,
      \gen_mux_rd[2].mux_rd_rise3_r1_reg[2]\ => u_ddr_mc_phy_wrapper_n_1271,
      \gen_mux_rd[2].mux_rd_rise3_r_reg[2]\ => u_ddr_mc_phy_wrapper_n_631,
      \gen_mux_rd[3].mux_rd_fall0_r1_reg[3]\ => u_ddr_mc_phy_wrapper_n_1232,
      \gen_mux_rd[3].mux_rd_fall0_r_reg[3]\ => u_ddr_mc_phy_wrapper_n_602,
      \gen_mux_rd[3].mux_rd_fall1_r1_reg[3]\ => u_ddr_mc_phy_wrapper_n_1248,
      \gen_mux_rd[3].mux_rd_fall1_r_reg[3]\ => u_ddr_mc_phy_wrapper_n_613,
      \gen_mux_rd[3].mux_rd_fall2_r1_reg[3]\ => u_ddr_mc_phy_wrapper_n_1264,
      \gen_mux_rd[3].mux_rd_fall2_r_reg[3]\ => u_ddr_mc_phy_wrapper_n_626,
      \gen_mux_rd[3].mux_rd_fall3_r1_reg[3]\ => u_ddr_mc_phy_wrapper_n_1280,
      \gen_mux_rd[3].mux_rd_fall3_r_reg[3]\ => u_ddr_mc_phy_wrapper_n_639,
      \gen_mux_rd[3].mux_rd_rise0_r1_reg[3]\ => u_ddr_mc_phy_wrapper_n_1224,
      \gen_mux_rd[3].mux_rd_rise0_r_reg[3]\ => u_ddr_mc_phy_wrapper_n_597,
      \gen_mux_rd[3].mux_rd_rise1_r1_reg[3]\ => u_ddr_mc_phy_wrapper_n_1240,
      \gen_mux_rd[3].mux_rd_rise1_r_reg[3]\ => u_ddr_mc_phy_wrapper_n_608,
      \gen_mux_rd[3].mux_rd_rise2_r1_reg[3]\ => u_ddr_mc_phy_wrapper_n_1256,
      \gen_mux_rd[3].mux_rd_rise2_r_reg[3]\ => u_ddr_mc_phy_wrapper_n_620,
      \gen_mux_rd[3].mux_rd_rise3_r1_reg[3]\ => u_ddr_mc_phy_wrapper_n_1272,
      \gen_mux_rd[3].mux_rd_rise3_r_reg[3]\ => u_ddr_mc_phy_wrapper_n_632,
      \gen_mux_rd[4].mux_rd_fall0_r1_reg[4]\ => u_ddr_mc_phy_wrapper_n_1233,
      \gen_mux_rd[4].mux_rd_fall0_r_reg[4]\ => u_ddr_mc_phy_wrapper_n_648,
      \gen_mux_rd[4].mux_rd_fall1_r1_reg[4]\ => u_ddr_mc_phy_wrapper_n_1249,
      \gen_mux_rd[4].mux_rd_fall1_r_reg[4]\ => u_ddr_mc_phy_wrapper_n_653,
      \gen_mux_rd[4].mux_rd_fall2_r1_reg[4]\ => u_ddr_mc_phy_wrapper_n_1265,
      \gen_mux_rd[4].mux_rd_fall2_r_reg[4]\ => u_ddr_mc_phy_wrapper_n_656,
      \gen_mux_rd[4].mux_rd_fall3_r1_reg[4]\ => u_ddr_mc_phy_wrapper_n_1281,
      \gen_mux_rd[4].mux_rd_fall3_r_reg[4]\ => u_ddr_mc_phy_wrapper_n_640,
      \gen_mux_rd[4].mux_rd_rise0_r1_reg[4]\ => u_ddr_mc_phy_wrapper_n_1225,
      \gen_mux_rd[4].mux_rd_rise0_r_reg[4]\ => u_ddr_mc_phy_wrapper_n_645,
      \gen_mux_rd[4].mux_rd_rise1_r1_reg[4]\ => u_ddr_mc_phy_wrapper_n_1241,
      \gen_mux_rd[4].mux_rd_rise1_r_reg[4]\ => u_ddr_mc_phy_wrapper_n_650,
      \gen_mux_rd[4].mux_rd_rise2_r1_reg[4]\ => u_ddr_mc_phy_wrapper_n_1257,
      \gen_mux_rd[4].mux_rd_rise2_r_reg[4]\ => u_ddr_mc_phy_wrapper_n_654,
      \gen_mux_rd[4].mux_rd_rise3_r1_reg[4]\ => u_ddr_mc_phy_wrapper_n_1273,
      \gen_mux_rd[4].mux_rd_rise3_r_reg[4]\ => u_ddr_mc_phy_wrapper_n_658,
      \gen_mux_rd[5].mux_rd_fall0_r1_reg[5]\ => u_ddr_mc_phy_wrapper_n_1234,
      \gen_mux_rd[5].mux_rd_fall0_r_reg[5]\ => u_ddr_mc_phy_wrapper_n_603,
      \gen_mux_rd[5].mux_rd_fall1_r1_reg[5]\ => u_ddr_mc_phy_wrapper_n_1250,
      \gen_mux_rd[5].mux_rd_fall1_r_reg[5]\ => u_ddr_mc_phy_wrapper_n_614,
      \gen_mux_rd[5].mux_rd_fall2_r1_reg[5]\ => u_ddr_mc_phy_wrapper_n_1266,
      \gen_mux_rd[5].mux_rd_fall2_r_reg[5]\ => u_ddr_mc_phy_wrapper_n_627,
      \gen_mux_rd[5].mux_rd_fall3_r1_reg[5]\ => u_ddr_mc_phy_wrapper_n_1282,
      \gen_mux_rd[5].mux_rd_fall3_r_reg[5]\ => u_ddr_mc_phy_wrapper_n_641,
      \gen_mux_rd[5].mux_rd_rise0_r1_reg[5]\ => u_ddr_mc_phy_wrapper_n_1226,
      \gen_mux_rd[5].mux_rd_rise0_r_reg[5]\ => u_ddr_mc_phy_wrapper_n_598,
      \gen_mux_rd[5].mux_rd_rise1_r1_reg[5]\ => u_ddr_mc_phy_wrapper_n_1242,
      \gen_mux_rd[5].mux_rd_rise1_r_reg[5]\ => u_ddr_mc_phy_wrapper_n_609,
      \gen_mux_rd[5].mux_rd_rise2_r1_reg[5]\ => u_ddr_mc_phy_wrapper_n_1258,
      \gen_mux_rd[5].mux_rd_rise2_r_reg[5]\ => u_ddr_mc_phy_wrapper_n_621,
      \gen_mux_rd[5].mux_rd_rise3_r1_reg[5]\ => u_ddr_mc_phy_wrapper_n_1274,
      \gen_mux_rd[5].mux_rd_rise3_r_reg[5]\ => u_ddr_mc_phy_wrapper_n_633,
      \gen_mux_rd[6].mux_rd_fall0_r1_reg[6]\ => u_ddr_mc_phy_wrapper_n_1235,
      \gen_mux_rd[6].mux_rd_fall0_r_reg[6]\ => u_ddr_mc_phy_wrapper_n_604,
      \gen_mux_rd[6].mux_rd_fall1_r1_reg[6]\ => u_ddr_mc_phy_wrapper_n_1251,
      \gen_mux_rd[6].mux_rd_fall1_r_reg[6]\ => u_ddr_mc_phy_wrapper_n_615,
      \gen_mux_rd[6].mux_rd_fall2_r1_reg[6]\ => u_ddr_mc_phy_wrapper_n_1267,
      \gen_mux_rd[6].mux_rd_fall2_r_reg[6]\ => u_ddr_mc_phy_wrapper_n_628,
      \gen_mux_rd[6].mux_rd_fall3_r1_reg[6]\ => u_ddr_mc_phy_wrapper_n_1283,
      \gen_mux_rd[6].mux_rd_fall3_r_reg[6]\ => u_ddr_mc_phy_wrapper_n_642,
      \gen_mux_rd[6].mux_rd_rise0_r1_reg[6]\ => u_ddr_mc_phy_wrapper_n_1227,
      \gen_mux_rd[6].mux_rd_rise0_r_reg[6]\ => u_ddr_mc_phy_wrapper_n_599,
      \gen_mux_rd[6].mux_rd_rise1_r1_reg[6]\ => u_ddr_mc_phy_wrapper_n_1243,
      \gen_mux_rd[6].mux_rd_rise1_r_reg[6]\ => u_ddr_mc_phy_wrapper_n_610,
      \gen_mux_rd[6].mux_rd_rise2_r1_reg[6]\ => u_ddr_mc_phy_wrapper_n_1259,
      \gen_mux_rd[6].mux_rd_rise2_r_reg[6]\ => u_ddr_mc_phy_wrapper_n_622,
      \gen_mux_rd[6].mux_rd_rise3_r1_reg[6]\ => u_ddr_mc_phy_wrapper_n_1275,
      \gen_mux_rd[6].mux_rd_rise3_r_reg[6]\ => u_ddr_mc_phy_wrapper_n_634,
      \gen_mux_rd[7].mux_rd_fall0_r1_reg[7]\ => u_ddr_mc_phy_wrapper_n_1236,
      \gen_mux_rd[7].mux_rd_fall0_r_reg[7]\ => u_ddr_mc_phy_wrapper_n_605,
      \gen_mux_rd[7].mux_rd_fall1_r1_reg[7]\ => u_ddr_mc_phy_wrapper_n_1252,
      \gen_mux_rd[7].mux_rd_fall1_r_reg[7]\ => u_ddr_mc_phy_wrapper_n_616,
      \gen_mux_rd[7].mux_rd_fall2_r1_reg[7]\ => u_ddr_mc_phy_wrapper_n_1268,
      \gen_mux_rd[7].mux_rd_fall2_r_reg[7]\ => u_ddr_mc_phy_wrapper_n_629,
      \gen_mux_rd[7].mux_rd_fall3_r1_reg[7]\ => u_ddr_mc_phy_wrapper_n_1284,
      \gen_mux_rd[7].mux_rd_fall3_r_reg[7]\ => u_ddr_mc_phy_wrapper_n_643,
      \gen_mux_rd[7].mux_rd_rise0_r1_reg[7]\ => u_ddr_mc_phy_wrapper_n_1228,
      \gen_mux_rd[7].mux_rd_rise0_r_reg[7]\ => u_ddr_mc_phy_wrapper_n_600,
      \gen_mux_rd[7].mux_rd_rise1_r1_reg[7]\ => u_ddr_mc_phy_wrapper_n_1244,
      \gen_mux_rd[7].mux_rd_rise1_r_reg[7]\ => u_ddr_mc_phy_wrapper_n_611,
      \gen_mux_rd[7].mux_rd_rise2_r1_reg[7]\ => u_ddr_mc_phy_wrapper_n_1260,
      \gen_mux_rd[7].mux_rd_rise2_r_reg[7]\ => u_ddr_mc_phy_wrapper_n_623,
      \gen_mux_rd[7].mux_rd_rise3_r1_reg[7]\ => u_ddr_mc_phy_wrapper_n_1276,
      \gen_mux_rd[7].mux_rd_rise3_r_reg[7]\ => u_ddr_mc_phy_wrapper_n_635,
      \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg[0]\ => u_ddr_mc_phy_wrapper_n_1310,
      \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg[0]\ => u_ddr_mc_phy_wrapper_n_1350,
      \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg[0]\ => u_ddr_mc_phy_wrapper_n_1326,
      \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg[0]\ => u_ddr_mc_phy_wrapper_n_1302,
      \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg[0]\ => u_ddr_mc_phy_wrapper_n_1342,
      \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise2_r_reg[0]\ => u_ddr_mc_phy_wrapper_n_1318,
      \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg[0]\ => u_ddr_mc_phy_wrapper_n_1334,
      \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg[1]\ => u_ddr_mc_phy_wrapper_n_1311,
      \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg[1]\ => u_ddr_mc_phy_wrapper_n_1351,
      \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg[1]\ => u_ddr_mc_phy_wrapper_n_1327,
      \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg[1]\ => u_ddr_mc_phy_wrapper_n_1303,
      \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg[1]\ => u_ddr_mc_phy_wrapper_n_1343,
      \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg[1]\ => u_ddr_mc_phy_wrapper_n_1295,
      \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg[1]\ => u_ddr_mc_phy_wrapper_n_1319,
      \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg[1]\ => u_ddr_mc_phy_wrapper_n_1335,
      \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg[2]\ => u_ddr_mc_phy_wrapper_n_1312,
      \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg[2]\ => u_ddr_mc_phy_wrapper_n_1352,
      \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg[2]\ => u_ddr_mc_phy_wrapper_n_1328,
      \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg[2]\ => u_ddr_mc_phy_wrapper_n_1304,
      \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg[2]\ => u_ddr_mc_phy_wrapper_n_1344,
      \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg[2]\ => u_ddr_mc_phy_wrapper_n_1296,
      \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg[2]\ => u_ddr_mc_phy_wrapper_n_1320,
      \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg[2]\ => u_ddr_mc_phy_wrapper_n_1336,
      \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg[3]\ => u_ddr_mc_phy_wrapper_n_1313,
      \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg[3]\ => u_ddr_mc_phy_wrapper_n_1353,
      \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg[3]\ => u_ddr_mc_phy_wrapper_n_1329,
      \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg[3]\ => u_ddr_mc_phy_wrapper_n_1305,
      \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg[3]\ => u_ddr_mc_phy_wrapper_n_1345,
      \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg[3]\ => u_ddr_mc_phy_wrapper_n_1297,
      \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg[3]\ => u_ddr_mc_phy_wrapper_n_1321,
      \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise3_r_reg[3]\ => u_ddr_mc_phy_wrapper_n_1337,
      \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg[4]\ => u_ddr_mc_phy_wrapper_n_1314,
      \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg[4]\ => u_ddr_mc_phy_wrapper_n_1354,
      \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg[4]\ => u_ddr_mc_phy_wrapper_n_1330,
      \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg[4]\ => u_ddr_mc_phy_wrapper_n_1306,
      \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg[4]\ => u_ddr_mc_phy_wrapper_n_1346,
      \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg[4]\ => u_ddr_mc_phy_wrapper_n_1298,
      \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise2_r_reg[4]\ => u_ddr_mc_phy_wrapper_n_1322,
      \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg[4]\ => u_ddr_mc_phy_wrapper_n_1338,
      \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg[5]\ => u_ddr_mc_phy_wrapper_n_1315,
      \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg[5]\ => u_ddr_mc_phy_wrapper_n_1355,
      \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg[5]\ => u_ddr_mc_phy_wrapper_n_1331,
      \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg[5]\ => u_ddr_mc_phy_wrapper_n_1307,
      \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg[5]\ => u_ddr_mc_phy_wrapper_n_1347,
      \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg[5]\ => u_ddr_mc_phy_wrapper_n_1299,
      \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg[5]\ => u_ddr_mc_phy_wrapper_n_1323,
      \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg[5]\ => u_ddr_mc_phy_wrapper_n_1339,
      \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg[6]\ => u_ddr_mc_phy_wrapper_n_1316,
      \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg[6]\ => u_ddr_mc_phy_wrapper_n_1356,
      \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg[6]\ => u_ddr_mc_phy_wrapper_n_1332,
      \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg[6]\ => u_ddr_mc_phy_wrapper_n_1308,
      \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg[6]\ => u_ddr_mc_phy_wrapper_n_1348,
      \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg[6]\ => u_ddr_mc_phy_wrapper_n_1300,
      \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg[6]\ => u_ddr_mc_phy_wrapper_n_1324,
      \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg[6]\ => u_ddr_mc_phy_wrapper_n_1340,
      \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg[7]\ => u_ddr_mc_phy_wrapper_n_1317,
      \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg[7]\ => u_ddr_mc_phy_wrapper_n_1357,
      \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg[7]\ => u_ddr_mc_phy_wrapper_n_1333,
      \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7]\ => u_ddr_mc_phy_wrapper_n_1309,
      \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg[7]\ => u_ddr_mc_phy_wrapper_n_1349,
      \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg[7]\ => u_ddr_mc_phy_wrapper_n_1301,
      \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg[7]\ => u_ddr_mc_phy_wrapper_n_1325,
      \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise3_r_reg[7]\ => u_ddr_mc_phy_wrapper_n_1341,
      \gen_no_mirror.div_clk_loop[0].phy_address_reg[2]\(3 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d8\(3 downto 0),
      \gen_no_mirror.div_clk_loop[0].phy_address_reg[8]\(3 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d4\(3 downto 0),
      \gen_no_mirror.div_clk_loop[0].phy_address_reg[9]\(3 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d9\(3 downto 0),
      \gen_no_mirror.div_clk_loop[0].phy_bank_reg[0]\(3 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d6\(7 downto 4),
      \gen_no_mirror.div_clk_loop[0].phy_bank_reg[1]\(7 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d5\(7 downto 0),
      \gen_rd[0].rd_data_rise_wl_r_reg[0]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_5\,
      \gen_rd[0].rd_data_rise_wl_r_reg[0]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_5\,
      \gen_rd[0].rd_data_rise_wl_r_reg[0]_1\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_0\,
      \gen_rd[0].rd_data_rise_wl_r_reg[0]_2\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_5\,
      \gen_rd[0].rd_data_rise_wl_r_reg[0]_3\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_5\,
      \gen_rd[0].rd_data_rise_wl_r_reg[0]_4\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_6\,
      \gen_rd[0].rd_data_rise_wl_r_reg[0]_5\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_2\,
      \gen_rd[0].rd_data_rise_wl_r_reg[0]_6\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_5\,
      \gen_rd[1].rd_data_rise_wl_r_reg[1]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]\,
      \gen_rd[1].rd_data_rise_wl_r_reg[1]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]\,
      \gen_rd[1].rd_data_rise_wl_r_reg[1]_1\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_2\,
      \gen_rd[1].rd_data_rise_wl_r_reg[1]_2\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]\,
      \gen_rd[1].rd_data_rise_wl_r_reg[1]_3\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]\,
      \gen_rd[1].rd_data_rise_wl_r_reg[1]_4\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_2\,
      \gen_rd[1].rd_data_rise_wl_r_reg[1]_5\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]\,
      \gen_rd[1].rd_data_rise_wl_r_reg[1]_6\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]\,
      \gen_rd[2].rd_data_rise_wl_r_reg[2]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_0\,
      \gen_rd[2].rd_data_rise_wl_r_reg[2]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0\,
      \gen_rd[2].rd_data_rise_wl_r_reg[2]_1\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_3\,
      \gen_rd[2].rd_data_rise_wl_r_reg[2]_2\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0\,
      \gen_rd[2].rd_data_rise_wl_r_reg[2]_3\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0\,
      \gen_rd[2].rd_data_rise_wl_r_reg[2]_4\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_3\,
      \gen_rd[2].rd_data_rise_wl_r_reg[2]_5\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_0\,
      \gen_rd[2].rd_data_rise_wl_r_reg[2]_6\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_0\,
      \gen_rd[3].rd_data_rise_wl_r_reg[3]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_4\,
      \gen_rd[3].rd_data_rise_wl_r_reg[3]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_4\,
      \gen_rd[3].rd_data_rise_wl_r_reg[3]_1\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_1\,
      \gen_rd[3].rd_data_rise_wl_r_reg[3]_2\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_4\,
      \gen_rd[3].rd_data_rise_wl_r_reg[3]_3\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_4\,
      \gen_rd[3].rd_data_rise_wl_r_reg[3]_4\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_1\,
      \gen_rd[3].rd_data_rise_wl_r_reg[3]_5\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_5\,
      \gen_rd[3].rd_data_rise_wl_r_reg[3]_6\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_4\,
      \gen_rd[4].rd_data_rise_wl_r_reg[4]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_6\,
      \gen_rd[4].rd_data_rise_wl_r_reg[4]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_6\,
      \gen_rd[4].rd_data_rise_wl_r_reg[4]_1\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]\,
      \gen_rd[4].rd_data_rise_wl_r_reg[4]_2\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_6\,
      \gen_rd[4].rd_data_rise_wl_r_reg[4]_3\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_6\,
      \gen_rd[4].rd_data_rise_wl_r_reg[4]_4\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_5\,
      \gen_rd[4].rd_data_rise_wl_r_reg[4]_5\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_6\,
      \gen_rd[4].rd_data_rise_wl_r_reg[4]_6\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_6\,
      \gen_rd[5].rd_data_rise_wl_r_reg[5]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_2\,
      \gen_rd[5].rd_data_rise_wl_r_reg[5]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_2\,
      \gen_rd[5].rd_data_rise_wl_r_reg[5]_1\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]\,
      \gen_rd[5].rd_data_rise_wl_r_reg[5]_2\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_2\,
      \gen_rd[5].rd_data_rise_wl_r_reg[5]_3\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_2\,
      \gen_rd[5].rd_data_rise_wl_r_reg[5]_4\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]\,
      \gen_rd[5].rd_data_rise_wl_r_reg[5]_5\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_3\,
      \gen_rd[5].rd_data_rise_wl_r_reg[5]_6\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_2\,
      \gen_rd[6].rd_data_rise_wl_r_reg[6]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_3\,
      \gen_rd[6].rd_data_rise_wl_r_reg[6]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_3\,
      \gen_rd[6].rd_data_rise_wl_r_reg[6]_1\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_0\,
      \gen_rd[6].rd_data_rise_wl_r_reg[6]_2\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_3\,
      \gen_rd[6].rd_data_rise_wl_r_reg[6]_3\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_3\,
      \gen_rd[6].rd_data_rise_wl_r_reg[6]_4\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_0\,
      \gen_rd[6].rd_data_rise_wl_r_reg[6]_5\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_4\,
      \gen_rd[6].rd_data_rise_wl_r_reg[6]_6\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_3\,
      \gen_rd[7].rd_data_rise_wl_r_reg[7]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_1\,
      \gen_rd[7].rd_data_rise_wl_r_reg[7]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_1\,
      \gen_rd[7].rd_data_rise_wl_r_reg[7]_1\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_4\,
      \gen_rd[7].rd_data_rise_wl_r_reg[7]_2\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_1\,
      \gen_rd[7].rd_data_rise_wl_r_reg[7]_3\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_1\,
      \gen_rd[7].rd_data_rise_wl_r_reg[7]_4\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_4\,
      \gen_rd[7].rd_data_rise_wl_r_reg[7]_5\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_1\,
      \gen_rd[7].rd_data_rise_wl_r_reg[7]_6\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_1\,
      idelay_ce_r2_reg_0 => u_ddr_calib_top_n_706,
      idelay_ce_r2_reg_1 => u_ddr_calib_top_n_738,
      idelay_inc => idelay_inc,
      idelay_ld_rst => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/idelay_ld_rst\,
      idelay_ld_rst_10 => \u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/idelay_ld_rst\,
      idelay_ld_rst_11 => \u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/ddr_byte_group_io/idelay_ld_rst\,
      idelay_ld_rst_12 => \u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/idelay_ld_rst\,
      idelay_ld_rst_13 => \u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/idelay_ld_rst\,
      idelay_ld_rst_7 => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/ddr_byte_group_io/idelay_ld_rst\,
      idelay_ld_rst_8 => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/idelay_ld_rst\,
      idelay_ld_rst_9 => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/idelay_ld_rst\,
      \idelay_tap_cnt_r_reg[0][0][4]\ => \idelay_tap_cnt_r_reg[0][0][4]\,
      \idelay_tap_cnt_r_reg[0][4][4]\ => \idelay_tap_cnt_r_reg[0][4][4]\,
      if_empty => if_empty,
      ififo_rst_reg(1) => pi_rst_dqs_find(2),
      ififo_rst_reg(0) => pi_rst_dqs_find(0),
      in0(7) => u_ddr_mc_phy_wrapper_n_33,
      in0(6) => u_ddr_mc_phy_wrapper_n_34,
      in0(5) => u_ddr_mc_phy_wrapper_n_35,
      in0(4) => u_ddr_mc_phy_wrapper_n_36,
      in0(3) => u_ddr_mc_phy_wrapper_n_37,
      in0(2) => u_ddr_mc_phy_wrapper_n_38,
      in0(1) => u_ddr_mc_phy_wrapper_n_39,
      in0(0) => u_ddr_mc_phy_wrapper_n_40,
      init_calib_complete_reg_rep_0 => u_ddr_calib_top_n_52,
      \init_calib_complete_reg_rep__0_0\ => u_ddr_calib_top_n_53,
      \init_calib_complete_reg_rep__11_0\ => u_ddr_calib_top_n_54,
      \init_calib_complete_reg_rep__12_0\ => \init_calib_complete_reg_rep__12\,
      \init_calib_complete_reg_rep__24_0\ => \init_calib_complete_reg_rep__24\,
      \init_calib_complete_reg_rep__25_0\ => \init_calib_complete_reg_rep__25\,
      \init_calib_complete_reg_rep__26_0\ => \^init_calib_complete_reg_rep__26\,
      \init_calib_complete_reg_rep__26_1\ => \init_calib_complete_reg_rep__26_0\,
      init_complete_r1_timing_reg => init_complete_r1_timing_reg,
      \init_state_r_reg[4]\ => \init_state_r_reg[4]\,
      mc_address(34) => mc_address(37),
      mc_address(33 downto 12) => mc_address(35 downto 14),
      mc_address(11) => mc_address(12),
      mc_address(10 downto 0) => mc_address(10 downto 0),
      mc_bank(8 downto 0) => mc_bank(8 downto 0),
      mc_cas_n(0) => mc_cas_n(1),
      mc_cke(0) => mc_cke(0),
      mc_cmd(1 downto 0) => mc_cmd(1 downto 0),
      mc_data_offset(0) => mc_data_offset(0),
      mc_data_offset_1(0) => mc_data_offset_1(0),
      mc_data_offset_2(0) => mc_data_offset_2(0),
      mc_odt(0) => mc_odt(0),
      mc_ras_n(0) => mc_ras_n(1),
      mc_ref_zq_wip => mc_ref_zq_wip,
      mc_we_n(0) => mc_we_n(1),
      mc_wrdata_en => mc_wrdata_en,
      mem_out(35) => u_ddr_mc_phy_wrapper_n_1184,
      mem_out(34) => u_ddr_mc_phy_wrapper_n_1185,
      mem_out(33) => u_ddr_mc_phy_wrapper_n_1186,
      mem_out(32) => u_ddr_mc_phy_wrapper_n_1187,
      mem_out(31) => u_ddr_mc_phy_wrapper_n_1188,
      mem_out(30) => u_ddr_mc_phy_wrapper_n_1189,
      mem_out(29) => u_ddr_mc_phy_wrapper_n_1190,
      mem_out(28) => u_ddr_mc_phy_wrapper_n_1191,
      mem_out(27) => u_ddr_mc_phy_wrapper_n_1192,
      mem_out(26) => u_ddr_mc_phy_wrapper_n_1193,
      mem_out(25) => u_ddr_mc_phy_wrapper_n_1194,
      mem_out(24) => u_ddr_mc_phy_wrapper_n_1195,
      mem_out(23) => u_ddr_mc_phy_wrapper_n_1196,
      mem_out(22) => u_ddr_mc_phy_wrapper_n_1197,
      mem_out(21) => u_ddr_mc_phy_wrapper_n_1198,
      mem_out(20) => u_ddr_mc_phy_wrapper_n_1199,
      mem_out(19) => u_ddr_mc_phy_wrapper_n_1200,
      mem_out(18) => u_ddr_mc_phy_wrapper_n_1201,
      mem_out(17) => u_ddr_mc_phy_wrapper_n_1202,
      mem_out(16) => u_ddr_mc_phy_wrapper_n_1203,
      mem_out(15) => u_ddr_mc_phy_wrapper_n_1204,
      mem_out(14) => u_ddr_mc_phy_wrapper_n_1205,
      mem_out(13) => u_ddr_mc_phy_wrapper_n_1206,
      mem_out(12) => u_ddr_mc_phy_wrapper_n_1207,
      mem_out(11) => u_ddr_mc_phy_wrapper_n_1208,
      mem_out(10) => u_ddr_mc_phy_wrapper_n_1209,
      mem_out(9) => u_ddr_mc_phy_wrapper_n_1210,
      mem_out(8) => u_ddr_mc_phy_wrapper_n_1211,
      mem_out(7) => u_ddr_mc_phy_wrapper_n_1212,
      mem_out(6) => u_ddr_mc_phy_wrapper_n_1213,
      mem_out(5) => u_ddr_mc_phy_wrapper_n_1214,
      mem_out(4) => u_ddr_mc_phy_wrapper_n_1215,
      mem_out(3) => u_ddr_mc_phy_wrapper_n_1216,
      mem_out(2) => u_ddr_mc_phy_wrapper_n_1217,
      mem_out(1) => u_ddr_mc_phy_wrapper_n_1218,
      mem_out(0) => u_ddr_mc_phy_wrapper_n_1219,
      mem_reg_0_15_12_17(575 downto 0) => Q(575 downto 0),
      mux_reset_n => mux_reset_n,
      new_cnt_cpt_r_reg => new_cnt_cpt_r_reg,
      \not_empty_wait_cnt_reg[4]\ => \not_empty_wait_cnt_reg[4]\,
      \one_dec_max_limit_reg[2]\ => \one_dec_max_limit_reg[2]\,
      \one_dec_min_limit_reg[11]\ => \one_dec_min_limit_reg[11]\,
      \out\ => pi_fine_enable,
      out_fifo => u_ddr_mc_phy_wrapper_n_70,
      out_fifo_0(23 downto 20) => \u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out\(75 downto 72),
      out_fifo_0(19 downto 16) => \u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out\(67 downto 64),
      out_fifo_0(15 downto 12) => \u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out\(55 downto 52),
      out_fifo_0(11 downto 4) => \u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out\(47 downto 40),
      out_fifo_0(3 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out\(35 downto 32),
      out_fifo_1 => u_ddr_mc_phy_wrapper_n_1360,
      out_fifo_10(63) => u_ddr_mc_phy_wrapper_n_660,
      out_fifo_10(62) => u_ddr_mc_phy_wrapper_n_661,
      out_fifo_10(61) => u_ddr_mc_phy_wrapper_n_662,
      out_fifo_10(60) => u_ddr_mc_phy_wrapper_n_663,
      out_fifo_10(59) => u_ddr_mc_phy_wrapper_n_664,
      out_fifo_10(58) => u_ddr_mc_phy_wrapper_n_665,
      out_fifo_10(57) => u_ddr_mc_phy_wrapper_n_666,
      out_fifo_10(56) => u_ddr_mc_phy_wrapper_n_667,
      out_fifo_10(55) => u_ddr_mc_phy_wrapper_n_668,
      out_fifo_10(54) => u_ddr_mc_phy_wrapper_n_669,
      out_fifo_10(53) => u_ddr_mc_phy_wrapper_n_670,
      out_fifo_10(52) => u_ddr_mc_phy_wrapper_n_671,
      out_fifo_10(51) => u_ddr_mc_phy_wrapper_n_672,
      out_fifo_10(50) => u_ddr_mc_phy_wrapper_n_673,
      out_fifo_10(49) => u_ddr_mc_phy_wrapper_n_674,
      out_fifo_10(48) => u_ddr_mc_phy_wrapper_n_675,
      out_fifo_10(47) => u_ddr_mc_phy_wrapper_n_676,
      out_fifo_10(46) => u_ddr_mc_phy_wrapper_n_677,
      out_fifo_10(45) => u_ddr_mc_phy_wrapper_n_678,
      out_fifo_10(44) => u_ddr_mc_phy_wrapper_n_679,
      out_fifo_10(43) => u_ddr_mc_phy_wrapper_n_680,
      out_fifo_10(42) => u_ddr_mc_phy_wrapper_n_681,
      out_fifo_10(41) => u_ddr_mc_phy_wrapper_n_682,
      out_fifo_10(40) => u_ddr_mc_phy_wrapper_n_683,
      out_fifo_10(39) => u_ddr_mc_phy_wrapper_n_684,
      out_fifo_10(38) => u_ddr_mc_phy_wrapper_n_685,
      out_fifo_10(37) => u_ddr_mc_phy_wrapper_n_686,
      out_fifo_10(36) => u_ddr_mc_phy_wrapper_n_687,
      out_fifo_10(35) => u_ddr_mc_phy_wrapper_n_688,
      out_fifo_10(34) => u_ddr_mc_phy_wrapper_n_689,
      out_fifo_10(33) => u_ddr_mc_phy_wrapper_n_690,
      out_fifo_10(32) => u_ddr_mc_phy_wrapper_n_691,
      out_fifo_10(31) => u_ddr_mc_phy_wrapper_n_692,
      out_fifo_10(30) => u_ddr_mc_phy_wrapper_n_693,
      out_fifo_10(29) => u_ddr_mc_phy_wrapper_n_694,
      out_fifo_10(28) => u_ddr_mc_phy_wrapper_n_695,
      out_fifo_10(27) => u_ddr_mc_phy_wrapper_n_696,
      out_fifo_10(26) => u_ddr_mc_phy_wrapper_n_697,
      out_fifo_10(25) => u_ddr_mc_phy_wrapper_n_698,
      out_fifo_10(24) => u_ddr_mc_phy_wrapper_n_699,
      out_fifo_10(23) => u_ddr_mc_phy_wrapper_n_700,
      out_fifo_10(22) => u_ddr_mc_phy_wrapper_n_701,
      out_fifo_10(21) => u_ddr_mc_phy_wrapper_n_702,
      out_fifo_10(20) => u_ddr_mc_phy_wrapper_n_703,
      out_fifo_10(19) => u_ddr_mc_phy_wrapper_n_704,
      out_fifo_10(18) => u_ddr_mc_phy_wrapper_n_705,
      out_fifo_10(17) => u_ddr_mc_phy_wrapper_n_706,
      out_fifo_10(16) => u_ddr_mc_phy_wrapper_n_707,
      out_fifo_10(15) => u_ddr_mc_phy_wrapper_n_708,
      out_fifo_10(14) => u_ddr_mc_phy_wrapper_n_709,
      out_fifo_10(13) => u_ddr_mc_phy_wrapper_n_710,
      out_fifo_10(12) => u_ddr_mc_phy_wrapper_n_711,
      out_fifo_10(11) => u_ddr_mc_phy_wrapper_n_712,
      out_fifo_10(10) => u_ddr_mc_phy_wrapper_n_713,
      out_fifo_10(9) => u_ddr_mc_phy_wrapper_n_714,
      out_fifo_10(8) => u_ddr_mc_phy_wrapper_n_715,
      out_fifo_10(7) => u_ddr_mc_phy_wrapper_n_716,
      out_fifo_10(6) => u_ddr_mc_phy_wrapper_n_717,
      out_fifo_10(5) => u_ddr_mc_phy_wrapper_n_718,
      out_fifo_10(4) => u_ddr_mc_phy_wrapper_n_719,
      out_fifo_10(3) => u_ddr_mc_phy_wrapper_n_720,
      out_fifo_10(2) => u_ddr_mc_phy_wrapper_n_721,
      out_fifo_10(1) => u_ddr_mc_phy_wrapper_n_722,
      out_fifo_10(0) => u_ddr_mc_phy_wrapper_n_723,
      out_fifo_11 => u_ddr_mc_phy_wrapper_n_59,
      out_fifo_12(63) => u_ddr_mc_phy_wrapper_n_724,
      out_fifo_12(62) => u_ddr_mc_phy_wrapper_n_725,
      out_fifo_12(61) => u_ddr_mc_phy_wrapper_n_726,
      out_fifo_12(60) => u_ddr_mc_phy_wrapper_n_727,
      out_fifo_12(59) => u_ddr_mc_phy_wrapper_n_728,
      out_fifo_12(58) => u_ddr_mc_phy_wrapper_n_729,
      out_fifo_12(57) => u_ddr_mc_phy_wrapper_n_730,
      out_fifo_12(56) => u_ddr_mc_phy_wrapper_n_731,
      out_fifo_12(55) => u_ddr_mc_phy_wrapper_n_732,
      out_fifo_12(54) => u_ddr_mc_phy_wrapper_n_733,
      out_fifo_12(53) => u_ddr_mc_phy_wrapper_n_734,
      out_fifo_12(52) => u_ddr_mc_phy_wrapper_n_735,
      out_fifo_12(51) => u_ddr_mc_phy_wrapper_n_736,
      out_fifo_12(50) => u_ddr_mc_phy_wrapper_n_737,
      out_fifo_12(49) => u_ddr_mc_phy_wrapper_n_738,
      out_fifo_12(48) => u_ddr_mc_phy_wrapper_n_739,
      out_fifo_12(47) => u_ddr_mc_phy_wrapper_n_740,
      out_fifo_12(46) => u_ddr_mc_phy_wrapper_n_741,
      out_fifo_12(45) => u_ddr_mc_phy_wrapper_n_742,
      out_fifo_12(44) => u_ddr_mc_phy_wrapper_n_743,
      out_fifo_12(43) => u_ddr_mc_phy_wrapper_n_744,
      out_fifo_12(42) => u_ddr_mc_phy_wrapper_n_745,
      out_fifo_12(41) => u_ddr_mc_phy_wrapper_n_746,
      out_fifo_12(40) => u_ddr_mc_phy_wrapper_n_747,
      out_fifo_12(39) => u_ddr_mc_phy_wrapper_n_748,
      out_fifo_12(38) => u_ddr_mc_phy_wrapper_n_749,
      out_fifo_12(37) => u_ddr_mc_phy_wrapper_n_750,
      out_fifo_12(36) => u_ddr_mc_phy_wrapper_n_751,
      out_fifo_12(35) => u_ddr_mc_phy_wrapper_n_752,
      out_fifo_12(34) => u_ddr_mc_phy_wrapper_n_753,
      out_fifo_12(33) => u_ddr_mc_phy_wrapper_n_754,
      out_fifo_12(32) => u_ddr_mc_phy_wrapper_n_755,
      out_fifo_12(31) => u_ddr_mc_phy_wrapper_n_756,
      out_fifo_12(30) => u_ddr_mc_phy_wrapper_n_757,
      out_fifo_12(29) => u_ddr_mc_phy_wrapper_n_758,
      out_fifo_12(28) => u_ddr_mc_phy_wrapper_n_759,
      out_fifo_12(27) => u_ddr_mc_phy_wrapper_n_760,
      out_fifo_12(26) => u_ddr_mc_phy_wrapper_n_761,
      out_fifo_12(25) => u_ddr_mc_phy_wrapper_n_762,
      out_fifo_12(24) => u_ddr_mc_phy_wrapper_n_763,
      out_fifo_12(23) => u_ddr_mc_phy_wrapper_n_764,
      out_fifo_12(22) => u_ddr_mc_phy_wrapper_n_765,
      out_fifo_12(21) => u_ddr_mc_phy_wrapper_n_766,
      out_fifo_12(20) => u_ddr_mc_phy_wrapper_n_767,
      out_fifo_12(19) => u_ddr_mc_phy_wrapper_n_768,
      out_fifo_12(18) => u_ddr_mc_phy_wrapper_n_769,
      out_fifo_12(17) => u_ddr_mc_phy_wrapper_n_770,
      out_fifo_12(16) => u_ddr_mc_phy_wrapper_n_771,
      out_fifo_12(15) => u_ddr_mc_phy_wrapper_n_772,
      out_fifo_12(14) => u_ddr_mc_phy_wrapper_n_773,
      out_fifo_12(13) => u_ddr_mc_phy_wrapper_n_774,
      out_fifo_12(12) => u_ddr_mc_phy_wrapper_n_775,
      out_fifo_12(11) => u_ddr_mc_phy_wrapper_n_776,
      out_fifo_12(10) => u_ddr_mc_phy_wrapper_n_777,
      out_fifo_12(9) => u_ddr_mc_phy_wrapper_n_778,
      out_fifo_12(8) => u_ddr_mc_phy_wrapper_n_779,
      out_fifo_12(7) => u_ddr_mc_phy_wrapper_n_780,
      out_fifo_12(6) => u_ddr_mc_phy_wrapper_n_781,
      out_fifo_12(5) => u_ddr_mc_phy_wrapper_n_782,
      out_fifo_12(4) => u_ddr_mc_phy_wrapper_n_783,
      out_fifo_12(3) => u_ddr_mc_phy_wrapper_n_784,
      out_fifo_12(2) => u_ddr_mc_phy_wrapper_n_785,
      out_fifo_12(1) => u_ddr_mc_phy_wrapper_n_786,
      out_fifo_12(0) => u_ddr_mc_phy_wrapper_n_787,
      out_fifo_13 => u_ddr_mc_phy_wrapper_n_61,
      out_fifo_14(63) => u_ddr_mc_phy_wrapper_n_788,
      out_fifo_14(62) => u_ddr_mc_phy_wrapper_n_789,
      out_fifo_14(61) => u_ddr_mc_phy_wrapper_n_790,
      out_fifo_14(60) => u_ddr_mc_phy_wrapper_n_791,
      out_fifo_14(59) => u_ddr_mc_phy_wrapper_n_792,
      out_fifo_14(58) => u_ddr_mc_phy_wrapper_n_793,
      out_fifo_14(57) => u_ddr_mc_phy_wrapper_n_794,
      out_fifo_14(56) => u_ddr_mc_phy_wrapper_n_795,
      out_fifo_14(55) => u_ddr_mc_phy_wrapper_n_796,
      out_fifo_14(54) => u_ddr_mc_phy_wrapper_n_797,
      out_fifo_14(53) => u_ddr_mc_phy_wrapper_n_798,
      out_fifo_14(52) => u_ddr_mc_phy_wrapper_n_799,
      out_fifo_14(51) => u_ddr_mc_phy_wrapper_n_800,
      out_fifo_14(50) => u_ddr_mc_phy_wrapper_n_801,
      out_fifo_14(49) => u_ddr_mc_phy_wrapper_n_802,
      out_fifo_14(48) => u_ddr_mc_phy_wrapper_n_803,
      out_fifo_14(47) => u_ddr_mc_phy_wrapper_n_804,
      out_fifo_14(46) => u_ddr_mc_phy_wrapper_n_805,
      out_fifo_14(45) => u_ddr_mc_phy_wrapper_n_806,
      out_fifo_14(44) => u_ddr_mc_phy_wrapper_n_807,
      out_fifo_14(43) => u_ddr_mc_phy_wrapper_n_808,
      out_fifo_14(42) => u_ddr_mc_phy_wrapper_n_809,
      out_fifo_14(41) => u_ddr_mc_phy_wrapper_n_810,
      out_fifo_14(40) => u_ddr_mc_phy_wrapper_n_811,
      out_fifo_14(39) => u_ddr_mc_phy_wrapper_n_812,
      out_fifo_14(38) => u_ddr_mc_phy_wrapper_n_813,
      out_fifo_14(37) => u_ddr_mc_phy_wrapper_n_814,
      out_fifo_14(36) => u_ddr_mc_phy_wrapper_n_815,
      out_fifo_14(35) => u_ddr_mc_phy_wrapper_n_816,
      out_fifo_14(34) => u_ddr_mc_phy_wrapper_n_817,
      out_fifo_14(33) => u_ddr_mc_phy_wrapper_n_818,
      out_fifo_14(32) => u_ddr_mc_phy_wrapper_n_819,
      out_fifo_14(31) => u_ddr_mc_phy_wrapper_n_820,
      out_fifo_14(30) => u_ddr_mc_phy_wrapper_n_821,
      out_fifo_14(29) => u_ddr_mc_phy_wrapper_n_822,
      out_fifo_14(28) => u_ddr_mc_phy_wrapper_n_823,
      out_fifo_14(27) => u_ddr_mc_phy_wrapper_n_824,
      out_fifo_14(26) => u_ddr_mc_phy_wrapper_n_825,
      out_fifo_14(25) => u_ddr_mc_phy_wrapper_n_826,
      out_fifo_14(24) => u_ddr_mc_phy_wrapper_n_827,
      out_fifo_14(23) => u_ddr_mc_phy_wrapper_n_828,
      out_fifo_14(22) => u_ddr_mc_phy_wrapper_n_829,
      out_fifo_14(21) => u_ddr_mc_phy_wrapper_n_830,
      out_fifo_14(20) => u_ddr_mc_phy_wrapper_n_831,
      out_fifo_14(19) => u_ddr_mc_phy_wrapper_n_832,
      out_fifo_14(18) => u_ddr_mc_phy_wrapper_n_833,
      out_fifo_14(17) => u_ddr_mc_phy_wrapper_n_834,
      out_fifo_14(16) => u_ddr_mc_phy_wrapper_n_835,
      out_fifo_14(15) => u_ddr_mc_phy_wrapper_n_836,
      out_fifo_14(14) => u_ddr_mc_phy_wrapper_n_837,
      out_fifo_14(13) => u_ddr_mc_phy_wrapper_n_838,
      out_fifo_14(12) => u_ddr_mc_phy_wrapper_n_839,
      out_fifo_14(11) => u_ddr_mc_phy_wrapper_n_840,
      out_fifo_14(10) => u_ddr_mc_phy_wrapper_n_841,
      out_fifo_14(9) => u_ddr_mc_phy_wrapper_n_842,
      out_fifo_14(8) => u_ddr_mc_phy_wrapper_n_843,
      out_fifo_14(7) => u_ddr_mc_phy_wrapper_n_844,
      out_fifo_14(6) => u_ddr_mc_phy_wrapper_n_845,
      out_fifo_14(5) => u_ddr_mc_phy_wrapper_n_846,
      out_fifo_14(4) => u_ddr_mc_phy_wrapper_n_847,
      out_fifo_14(3) => u_ddr_mc_phy_wrapper_n_848,
      out_fifo_14(2) => u_ddr_mc_phy_wrapper_n_849,
      out_fifo_14(1) => u_ddr_mc_phy_wrapper_n_850,
      out_fifo_14(0) => u_ddr_mc_phy_wrapper_n_851,
      out_fifo_15 => u_ddr_mc_phy_wrapper_n_62,
      out_fifo_16(63) => u_ddr_mc_phy_wrapper_n_852,
      out_fifo_16(62) => u_ddr_mc_phy_wrapper_n_853,
      out_fifo_16(61) => u_ddr_mc_phy_wrapper_n_854,
      out_fifo_16(60) => u_ddr_mc_phy_wrapper_n_855,
      out_fifo_16(59) => u_ddr_mc_phy_wrapper_n_856,
      out_fifo_16(58) => u_ddr_mc_phy_wrapper_n_857,
      out_fifo_16(57) => u_ddr_mc_phy_wrapper_n_858,
      out_fifo_16(56) => u_ddr_mc_phy_wrapper_n_859,
      out_fifo_16(55) => u_ddr_mc_phy_wrapper_n_860,
      out_fifo_16(54) => u_ddr_mc_phy_wrapper_n_861,
      out_fifo_16(53) => u_ddr_mc_phy_wrapper_n_862,
      out_fifo_16(52) => u_ddr_mc_phy_wrapper_n_863,
      out_fifo_16(51) => u_ddr_mc_phy_wrapper_n_864,
      out_fifo_16(50) => u_ddr_mc_phy_wrapper_n_865,
      out_fifo_16(49) => u_ddr_mc_phy_wrapper_n_866,
      out_fifo_16(48) => u_ddr_mc_phy_wrapper_n_867,
      out_fifo_16(47) => u_ddr_mc_phy_wrapper_n_868,
      out_fifo_16(46) => u_ddr_mc_phy_wrapper_n_869,
      out_fifo_16(45) => u_ddr_mc_phy_wrapper_n_870,
      out_fifo_16(44) => u_ddr_mc_phy_wrapper_n_871,
      out_fifo_16(43) => u_ddr_mc_phy_wrapper_n_872,
      out_fifo_16(42) => u_ddr_mc_phy_wrapper_n_873,
      out_fifo_16(41) => u_ddr_mc_phy_wrapper_n_874,
      out_fifo_16(40) => u_ddr_mc_phy_wrapper_n_875,
      out_fifo_16(39) => u_ddr_mc_phy_wrapper_n_876,
      out_fifo_16(38) => u_ddr_mc_phy_wrapper_n_877,
      out_fifo_16(37) => u_ddr_mc_phy_wrapper_n_878,
      out_fifo_16(36) => u_ddr_mc_phy_wrapper_n_879,
      out_fifo_16(35) => u_ddr_mc_phy_wrapper_n_880,
      out_fifo_16(34) => u_ddr_mc_phy_wrapper_n_881,
      out_fifo_16(33) => u_ddr_mc_phy_wrapper_n_882,
      out_fifo_16(32) => u_ddr_mc_phy_wrapper_n_883,
      out_fifo_16(31) => u_ddr_mc_phy_wrapper_n_884,
      out_fifo_16(30) => u_ddr_mc_phy_wrapper_n_885,
      out_fifo_16(29) => u_ddr_mc_phy_wrapper_n_886,
      out_fifo_16(28) => u_ddr_mc_phy_wrapper_n_887,
      out_fifo_16(27) => u_ddr_mc_phy_wrapper_n_888,
      out_fifo_16(26) => u_ddr_mc_phy_wrapper_n_889,
      out_fifo_16(25) => u_ddr_mc_phy_wrapper_n_890,
      out_fifo_16(24) => u_ddr_mc_phy_wrapper_n_891,
      out_fifo_16(23) => u_ddr_mc_phy_wrapper_n_892,
      out_fifo_16(22) => u_ddr_mc_phy_wrapper_n_893,
      out_fifo_16(21) => u_ddr_mc_phy_wrapper_n_894,
      out_fifo_16(20) => u_ddr_mc_phy_wrapper_n_895,
      out_fifo_16(19) => u_ddr_mc_phy_wrapper_n_896,
      out_fifo_16(18) => u_ddr_mc_phy_wrapper_n_897,
      out_fifo_16(17) => u_ddr_mc_phy_wrapper_n_898,
      out_fifo_16(16) => u_ddr_mc_phy_wrapper_n_899,
      out_fifo_16(15) => u_ddr_mc_phy_wrapper_n_900,
      out_fifo_16(14) => u_ddr_mc_phy_wrapper_n_901,
      out_fifo_16(13) => u_ddr_mc_phy_wrapper_n_902,
      out_fifo_16(12) => u_ddr_mc_phy_wrapper_n_903,
      out_fifo_16(11) => u_ddr_mc_phy_wrapper_n_904,
      out_fifo_16(10) => u_ddr_mc_phy_wrapper_n_905,
      out_fifo_16(9) => u_ddr_mc_phy_wrapper_n_906,
      out_fifo_16(8) => u_ddr_mc_phy_wrapper_n_907,
      out_fifo_16(7) => u_ddr_mc_phy_wrapper_n_908,
      out_fifo_16(6) => u_ddr_mc_phy_wrapper_n_909,
      out_fifo_16(5) => u_ddr_mc_phy_wrapper_n_910,
      out_fifo_16(4) => u_ddr_mc_phy_wrapper_n_911,
      out_fifo_16(3) => u_ddr_mc_phy_wrapper_n_912,
      out_fifo_16(2) => u_ddr_mc_phy_wrapper_n_913,
      out_fifo_16(1) => u_ddr_mc_phy_wrapper_n_914,
      out_fifo_16(0) => u_ddr_mc_phy_wrapper_n_915,
      out_fifo_17 => u_ddr_mc_phy_wrapper_n_63,
      out_fifo_18(11 downto 8) => \u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/mem_out\(59 downto 56),
      out_fifo_18(7) => \u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/mem_out\(53),
      out_fifo_18(6) => \u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/mem_out\(45),
      out_fifo_18(5) => \u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/mem_out\(41),
      out_fifo_18(4) => \u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/mem_out\(33),
      out_fifo_18(3 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/mem_out\(19 downto 16),
      out_fifo_19 => u_ddr_mc_phy_wrapper_n_69,
      out_fifo_2(63) => u_ddr_mc_phy_wrapper_n_922,
      out_fifo_2(62) => u_ddr_mc_phy_wrapper_n_923,
      out_fifo_2(61) => u_ddr_mc_phy_wrapper_n_924,
      out_fifo_2(60) => u_ddr_mc_phy_wrapper_n_925,
      out_fifo_2(59) => u_ddr_mc_phy_wrapper_n_926,
      out_fifo_2(58) => u_ddr_mc_phy_wrapper_n_927,
      out_fifo_2(57) => u_ddr_mc_phy_wrapper_n_928,
      out_fifo_2(56) => u_ddr_mc_phy_wrapper_n_929,
      out_fifo_2(55) => u_ddr_mc_phy_wrapper_n_930,
      out_fifo_2(54) => u_ddr_mc_phy_wrapper_n_931,
      out_fifo_2(53) => u_ddr_mc_phy_wrapper_n_932,
      out_fifo_2(52) => u_ddr_mc_phy_wrapper_n_933,
      out_fifo_2(51) => u_ddr_mc_phy_wrapper_n_934,
      out_fifo_2(50) => u_ddr_mc_phy_wrapper_n_935,
      out_fifo_2(49) => u_ddr_mc_phy_wrapper_n_936,
      out_fifo_2(48) => u_ddr_mc_phy_wrapper_n_937,
      out_fifo_2(47) => u_ddr_mc_phy_wrapper_n_938,
      out_fifo_2(46) => u_ddr_mc_phy_wrapper_n_939,
      out_fifo_2(45) => u_ddr_mc_phy_wrapper_n_940,
      out_fifo_2(44) => u_ddr_mc_phy_wrapper_n_941,
      out_fifo_2(43) => u_ddr_mc_phy_wrapper_n_942,
      out_fifo_2(42) => u_ddr_mc_phy_wrapper_n_943,
      out_fifo_2(41) => u_ddr_mc_phy_wrapper_n_944,
      out_fifo_2(40) => u_ddr_mc_phy_wrapper_n_945,
      out_fifo_2(39) => u_ddr_mc_phy_wrapper_n_946,
      out_fifo_2(38) => u_ddr_mc_phy_wrapper_n_947,
      out_fifo_2(37) => u_ddr_mc_phy_wrapper_n_948,
      out_fifo_2(36) => u_ddr_mc_phy_wrapper_n_949,
      out_fifo_2(35) => u_ddr_mc_phy_wrapper_n_950,
      out_fifo_2(34) => u_ddr_mc_phy_wrapper_n_951,
      out_fifo_2(33) => u_ddr_mc_phy_wrapper_n_952,
      out_fifo_2(32) => u_ddr_mc_phy_wrapper_n_953,
      out_fifo_2(31) => u_ddr_mc_phy_wrapper_n_954,
      out_fifo_2(30) => u_ddr_mc_phy_wrapper_n_955,
      out_fifo_2(29) => u_ddr_mc_phy_wrapper_n_956,
      out_fifo_2(28) => u_ddr_mc_phy_wrapper_n_957,
      out_fifo_2(27) => u_ddr_mc_phy_wrapper_n_958,
      out_fifo_2(26) => u_ddr_mc_phy_wrapper_n_959,
      out_fifo_2(25) => u_ddr_mc_phy_wrapper_n_960,
      out_fifo_2(24) => u_ddr_mc_phy_wrapper_n_961,
      out_fifo_2(23) => u_ddr_mc_phy_wrapper_n_962,
      out_fifo_2(22) => u_ddr_mc_phy_wrapper_n_963,
      out_fifo_2(21) => u_ddr_mc_phy_wrapper_n_964,
      out_fifo_2(20) => u_ddr_mc_phy_wrapper_n_965,
      out_fifo_2(19) => u_ddr_mc_phy_wrapper_n_966,
      out_fifo_2(18) => u_ddr_mc_phy_wrapper_n_967,
      out_fifo_2(17) => u_ddr_mc_phy_wrapper_n_968,
      out_fifo_2(16) => u_ddr_mc_phy_wrapper_n_969,
      out_fifo_2(15) => u_ddr_mc_phy_wrapper_n_970,
      out_fifo_2(14) => u_ddr_mc_phy_wrapper_n_971,
      out_fifo_2(13) => u_ddr_mc_phy_wrapper_n_972,
      out_fifo_2(12) => u_ddr_mc_phy_wrapper_n_973,
      out_fifo_2(11) => u_ddr_mc_phy_wrapper_n_974,
      out_fifo_2(10) => u_ddr_mc_phy_wrapper_n_975,
      out_fifo_2(9) => u_ddr_mc_phy_wrapper_n_976,
      out_fifo_2(8) => u_ddr_mc_phy_wrapper_n_977,
      out_fifo_2(7) => u_ddr_mc_phy_wrapper_n_978,
      out_fifo_2(6) => u_ddr_mc_phy_wrapper_n_979,
      out_fifo_2(5) => u_ddr_mc_phy_wrapper_n_980,
      out_fifo_2(4) => u_ddr_mc_phy_wrapper_n_981,
      out_fifo_2(3) => u_ddr_mc_phy_wrapper_n_982,
      out_fifo_2(2) => u_ddr_mc_phy_wrapper_n_983,
      out_fifo_2(1) => u_ddr_mc_phy_wrapper_n_984,
      out_fifo_2(0) => u_ddr_mc_phy_wrapper_n_985,
      out_fifo_3 => u_ddr_mc_phy_wrapper_n_65,
      out_fifo_4(63) => u_ddr_mc_phy_wrapper_n_986,
      out_fifo_4(62) => u_ddr_mc_phy_wrapper_n_987,
      out_fifo_4(61) => u_ddr_mc_phy_wrapper_n_988,
      out_fifo_4(60) => u_ddr_mc_phy_wrapper_n_989,
      out_fifo_4(59) => u_ddr_mc_phy_wrapper_n_990,
      out_fifo_4(58) => u_ddr_mc_phy_wrapper_n_991,
      out_fifo_4(57) => u_ddr_mc_phy_wrapper_n_992,
      out_fifo_4(56) => u_ddr_mc_phy_wrapper_n_993,
      out_fifo_4(55) => u_ddr_mc_phy_wrapper_n_994,
      out_fifo_4(54) => u_ddr_mc_phy_wrapper_n_995,
      out_fifo_4(53) => u_ddr_mc_phy_wrapper_n_996,
      out_fifo_4(52) => u_ddr_mc_phy_wrapper_n_997,
      out_fifo_4(51) => u_ddr_mc_phy_wrapper_n_998,
      out_fifo_4(50) => u_ddr_mc_phy_wrapper_n_999,
      out_fifo_4(49) => u_ddr_mc_phy_wrapper_n_1000,
      out_fifo_4(48) => u_ddr_mc_phy_wrapper_n_1001,
      out_fifo_4(47) => u_ddr_mc_phy_wrapper_n_1002,
      out_fifo_4(46) => u_ddr_mc_phy_wrapper_n_1003,
      out_fifo_4(45) => u_ddr_mc_phy_wrapper_n_1004,
      out_fifo_4(44) => u_ddr_mc_phy_wrapper_n_1005,
      out_fifo_4(43) => u_ddr_mc_phy_wrapper_n_1006,
      out_fifo_4(42) => u_ddr_mc_phy_wrapper_n_1007,
      out_fifo_4(41) => u_ddr_mc_phy_wrapper_n_1008,
      out_fifo_4(40) => u_ddr_mc_phy_wrapper_n_1009,
      out_fifo_4(39) => u_ddr_mc_phy_wrapper_n_1010,
      out_fifo_4(38) => u_ddr_mc_phy_wrapper_n_1011,
      out_fifo_4(37) => u_ddr_mc_phy_wrapper_n_1012,
      out_fifo_4(36) => u_ddr_mc_phy_wrapper_n_1013,
      out_fifo_4(35) => u_ddr_mc_phy_wrapper_n_1014,
      out_fifo_4(34) => u_ddr_mc_phy_wrapper_n_1015,
      out_fifo_4(33) => u_ddr_mc_phy_wrapper_n_1016,
      out_fifo_4(32) => u_ddr_mc_phy_wrapper_n_1017,
      out_fifo_4(31) => u_ddr_mc_phy_wrapper_n_1018,
      out_fifo_4(30) => u_ddr_mc_phy_wrapper_n_1019,
      out_fifo_4(29) => u_ddr_mc_phy_wrapper_n_1020,
      out_fifo_4(28) => u_ddr_mc_phy_wrapper_n_1021,
      out_fifo_4(27) => u_ddr_mc_phy_wrapper_n_1022,
      out_fifo_4(26) => u_ddr_mc_phy_wrapper_n_1023,
      out_fifo_4(25) => u_ddr_mc_phy_wrapper_n_1024,
      out_fifo_4(24) => u_ddr_mc_phy_wrapper_n_1025,
      out_fifo_4(23) => u_ddr_mc_phy_wrapper_n_1026,
      out_fifo_4(22) => u_ddr_mc_phy_wrapper_n_1027,
      out_fifo_4(21) => u_ddr_mc_phy_wrapper_n_1028,
      out_fifo_4(20) => u_ddr_mc_phy_wrapper_n_1029,
      out_fifo_4(19) => u_ddr_mc_phy_wrapper_n_1030,
      out_fifo_4(18) => u_ddr_mc_phy_wrapper_n_1031,
      out_fifo_4(17) => u_ddr_mc_phy_wrapper_n_1032,
      out_fifo_4(16) => u_ddr_mc_phy_wrapper_n_1033,
      out_fifo_4(15) => u_ddr_mc_phy_wrapper_n_1034,
      out_fifo_4(14) => u_ddr_mc_phy_wrapper_n_1035,
      out_fifo_4(13) => u_ddr_mc_phy_wrapper_n_1036,
      out_fifo_4(12) => u_ddr_mc_phy_wrapper_n_1037,
      out_fifo_4(11) => u_ddr_mc_phy_wrapper_n_1038,
      out_fifo_4(10) => u_ddr_mc_phy_wrapper_n_1039,
      out_fifo_4(9) => u_ddr_mc_phy_wrapper_n_1040,
      out_fifo_4(8) => u_ddr_mc_phy_wrapper_n_1041,
      out_fifo_4(7) => u_ddr_mc_phy_wrapper_n_1042,
      out_fifo_4(6) => u_ddr_mc_phy_wrapper_n_1043,
      out_fifo_4(5) => u_ddr_mc_phy_wrapper_n_1044,
      out_fifo_4(4) => u_ddr_mc_phy_wrapper_n_1045,
      out_fifo_4(3) => u_ddr_mc_phy_wrapper_n_1046,
      out_fifo_4(2) => u_ddr_mc_phy_wrapper_n_1047,
      out_fifo_4(1) => u_ddr_mc_phy_wrapper_n_1048,
      out_fifo_4(0) => u_ddr_mc_phy_wrapper_n_1049,
      out_fifo_5 => u_ddr_mc_phy_wrapper_n_66,
      out_fifo_6(63) => u_ddr_mc_phy_wrapper_n_1050,
      out_fifo_6(62) => u_ddr_mc_phy_wrapper_n_1051,
      out_fifo_6(61) => u_ddr_mc_phy_wrapper_n_1052,
      out_fifo_6(60) => u_ddr_mc_phy_wrapper_n_1053,
      out_fifo_6(59) => u_ddr_mc_phy_wrapper_n_1054,
      out_fifo_6(58) => u_ddr_mc_phy_wrapper_n_1055,
      out_fifo_6(57) => u_ddr_mc_phy_wrapper_n_1056,
      out_fifo_6(56) => u_ddr_mc_phy_wrapper_n_1057,
      out_fifo_6(55) => u_ddr_mc_phy_wrapper_n_1058,
      out_fifo_6(54) => u_ddr_mc_phy_wrapper_n_1059,
      out_fifo_6(53) => u_ddr_mc_phy_wrapper_n_1060,
      out_fifo_6(52) => u_ddr_mc_phy_wrapper_n_1061,
      out_fifo_6(51) => u_ddr_mc_phy_wrapper_n_1062,
      out_fifo_6(50) => u_ddr_mc_phy_wrapper_n_1063,
      out_fifo_6(49) => u_ddr_mc_phy_wrapper_n_1064,
      out_fifo_6(48) => u_ddr_mc_phy_wrapper_n_1065,
      out_fifo_6(47) => u_ddr_mc_phy_wrapper_n_1066,
      out_fifo_6(46) => u_ddr_mc_phy_wrapper_n_1067,
      out_fifo_6(45) => u_ddr_mc_phy_wrapper_n_1068,
      out_fifo_6(44) => u_ddr_mc_phy_wrapper_n_1069,
      out_fifo_6(43) => u_ddr_mc_phy_wrapper_n_1070,
      out_fifo_6(42) => u_ddr_mc_phy_wrapper_n_1071,
      out_fifo_6(41) => u_ddr_mc_phy_wrapper_n_1072,
      out_fifo_6(40) => u_ddr_mc_phy_wrapper_n_1073,
      out_fifo_6(39) => u_ddr_mc_phy_wrapper_n_1074,
      out_fifo_6(38) => u_ddr_mc_phy_wrapper_n_1075,
      out_fifo_6(37) => u_ddr_mc_phy_wrapper_n_1076,
      out_fifo_6(36) => u_ddr_mc_phy_wrapper_n_1077,
      out_fifo_6(35) => u_ddr_mc_phy_wrapper_n_1078,
      out_fifo_6(34) => u_ddr_mc_phy_wrapper_n_1079,
      out_fifo_6(33) => u_ddr_mc_phy_wrapper_n_1080,
      out_fifo_6(32) => u_ddr_mc_phy_wrapper_n_1081,
      out_fifo_6(31) => u_ddr_mc_phy_wrapper_n_1082,
      out_fifo_6(30) => u_ddr_mc_phy_wrapper_n_1083,
      out_fifo_6(29) => u_ddr_mc_phy_wrapper_n_1084,
      out_fifo_6(28) => u_ddr_mc_phy_wrapper_n_1085,
      out_fifo_6(27) => u_ddr_mc_phy_wrapper_n_1086,
      out_fifo_6(26) => u_ddr_mc_phy_wrapper_n_1087,
      out_fifo_6(25) => u_ddr_mc_phy_wrapper_n_1088,
      out_fifo_6(24) => u_ddr_mc_phy_wrapper_n_1089,
      out_fifo_6(23) => u_ddr_mc_phy_wrapper_n_1090,
      out_fifo_6(22) => u_ddr_mc_phy_wrapper_n_1091,
      out_fifo_6(21) => u_ddr_mc_phy_wrapper_n_1092,
      out_fifo_6(20) => u_ddr_mc_phy_wrapper_n_1093,
      out_fifo_6(19) => u_ddr_mc_phy_wrapper_n_1094,
      out_fifo_6(18) => u_ddr_mc_phy_wrapper_n_1095,
      out_fifo_6(17) => u_ddr_mc_phy_wrapper_n_1096,
      out_fifo_6(16) => u_ddr_mc_phy_wrapper_n_1097,
      out_fifo_6(15) => u_ddr_mc_phy_wrapper_n_1098,
      out_fifo_6(14) => u_ddr_mc_phy_wrapper_n_1099,
      out_fifo_6(13) => u_ddr_mc_phy_wrapper_n_1100,
      out_fifo_6(12) => u_ddr_mc_phy_wrapper_n_1101,
      out_fifo_6(11) => u_ddr_mc_phy_wrapper_n_1102,
      out_fifo_6(10) => u_ddr_mc_phy_wrapper_n_1103,
      out_fifo_6(9) => u_ddr_mc_phy_wrapper_n_1104,
      out_fifo_6(8) => u_ddr_mc_phy_wrapper_n_1105,
      out_fifo_6(7) => u_ddr_mc_phy_wrapper_n_1106,
      out_fifo_6(6) => u_ddr_mc_phy_wrapper_n_1107,
      out_fifo_6(5) => u_ddr_mc_phy_wrapper_n_1108,
      out_fifo_6(4) => u_ddr_mc_phy_wrapper_n_1109,
      out_fifo_6(3) => u_ddr_mc_phy_wrapper_n_1110,
      out_fifo_6(2) => u_ddr_mc_phy_wrapper_n_1111,
      out_fifo_6(1) => u_ddr_mc_phy_wrapper_n_1112,
      out_fifo_6(0) => u_ddr_mc_phy_wrapper_n_1113,
      out_fifo_7 => u_ddr_mc_phy_wrapper_n_67,
      out_fifo_8(63) => u_ddr_mc_phy_wrapper_n_1114,
      out_fifo_8(62) => u_ddr_mc_phy_wrapper_n_1115,
      out_fifo_8(61) => u_ddr_mc_phy_wrapper_n_1116,
      out_fifo_8(60) => u_ddr_mc_phy_wrapper_n_1117,
      out_fifo_8(59) => u_ddr_mc_phy_wrapper_n_1118,
      out_fifo_8(58) => u_ddr_mc_phy_wrapper_n_1119,
      out_fifo_8(57) => u_ddr_mc_phy_wrapper_n_1120,
      out_fifo_8(56) => u_ddr_mc_phy_wrapper_n_1121,
      out_fifo_8(55) => u_ddr_mc_phy_wrapper_n_1122,
      out_fifo_8(54) => u_ddr_mc_phy_wrapper_n_1123,
      out_fifo_8(53) => u_ddr_mc_phy_wrapper_n_1124,
      out_fifo_8(52) => u_ddr_mc_phy_wrapper_n_1125,
      out_fifo_8(51) => u_ddr_mc_phy_wrapper_n_1126,
      out_fifo_8(50) => u_ddr_mc_phy_wrapper_n_1127,
      out_fifo_8(49) => u_ddr_mc_phy_wrapper_n_1128,
      out_fifo_8(48) => u_ddr_mc_phy_wrapper_n_1129,
      out_fifo_8(47) => u_ddr_mc_phy_wrapper_n_1130,
      out_fifo_8(46) => u_ddr_mc_phy_wrapper_n_1131,
      out_fifo_8(45) => u_ddr_mc_phy_wrapper_n_1132,
      out_fifo_8(44) => u_ddr_mc_phy_wrapper_n_1133,
      out_fifo_8(43) => u_ddr_mc_phy_wrapper_n_1134,
      out_fifo_8(42) => u_ddr_mc_phy_wrapper_n_1135,
      out_fifo_8(41) => u_ddr_mc_phy_wrapper_n_1136,
      out_fifo_8(40) => u_ddr_mc_phy_wrapper_n_1137,
      out_fifo_8(39) => u_ddr_mc_phy_wrapper_n_1138,
      out_fifo_8(38) => u_ddr_mc_phy_wrapper_n_1139,
      out_fifo_8(37) => u_ddr_mc_phy_wrapper_n_1140,
      out_fifo_8(36) => u_ddr_mc_phy_wrapper_n_1141,
      out_fifo_8(35) => u_ddr_mc_phy_wrapper_n_1142,
      out_fifo_8(34) => u_ddr_mc_phy_wrapper_n_1143,
      out_fifo_8(33) => u_ddr_mc_phy_wrapper_n_1144,
      out_fifo_8(32) => u_ddr_mc_phy_wrapper_n_1145,
      out_fifo_8(31) => u_ddr_mc_phy_wrapper_n_1146,
      out_fifo_8(30) => u_ddr_mc_phy_wrapper_n_1147,
      out_fifo_8(29) => u_ddr_mc_phy_wrapper_n_1148,
      out_fifo_8(28) => u_ddr_mc_phy_wrapper_n_1149,
      out_fifo_8(27) => u_ddr_mc_phy_wrapper_n_1150,
      out_fifo_8(26) => u_ddr_mc_phy_wrapper_n_1151,
      out_fifo_8(25) => u_ddr_mc_phy_wrapper_n_1152,
      out_fifo_8(24) => u_ddr_mc_phy_wrapper_n_1153,
      out_fifo_8(23) => u_ddr_mc_phy_wrapper_n_1154,
      out_fifo_8(22) => u_ddr_mc_phy_wrapper_n_1155,
      out_fifo_8(21) => u_ddr_mc_phy_wrapper_n_1156,
      out_fifo_8(20) => u_ddr_mc_phy_wrapper_n_1157,
      out_fifo_8(19) => u_ddr_mc_phy_wrapper_n_1158,
      out_fifo_8(18) => u_ddr_mc_phy_wrapper_n_1159,
      out_fifo_8(17) => u_ddr_mc_phy_wrapper_n_1160,
      out_fifo_8(16) => u_ddr_mc_phy_wrapper_n_1161,
      out_fifo_8(15) => u_ddr_mc_phy_wrapper_n_1162,
      out_fifo_8(14) => u_ddr_mc_phy_wrapper_n_1163,
      out_fifo_8(13) => u_ddr_mc_phy_wrapper_n_1164,
      out_fifo_8(12) => u_ddr_mc_phy_wrapper_n_1165,
      out_fifo_8(11) => u_ddr_mc_phy_wrapper_n_1166,
      out_fifo_8(10) => u_ddr_mc_phy_wrapper_n_1167,
      out_fifo_8(9) => u_ddr_mc_phy_wrapper_n_1168,
      out_fifo_8(8) => u_ddr_mc_phy_wrapper_n_1169,
      out_fifo_8(7) => u_ddr_mc_phy_wrapper_n_1170,
      out_fifo_8(6) => u_ddr_mc_phy_wrapper_n_1171,
      out_fifo_8(5) => u_ddr_mc_phy_wrapper_n_1172,
      out_fifo_8(4) => u_ddr_mc_phy_wrapper_n_1173,
      out_fifo_8(3) => u_ddr_mc_phy_wrapper_n_1174,
      out_fifo_8(2) => u_ddr_mc_phy_wrapper_n_1175,
      out_fifo_8(1) => u_ddr_mc_phy_wrapper_n_1176,
      out_fifo_8(0) => u_ddr_mc_phy_wrapper_n_1177,
      out_fifo_9 => u_ddr_mc_phy_wrapper_n_68,
      p_0_out => \u_ddr_phy_wrcal/p_0_out\,
      phy_cmd_wr_en => phy_cmd_wr_en,
      \phy_ctl_wd_i1_reg[17]\ => \phy_ctl_wd_i1_reg[17]\,
      \phy_ctl_wd_i1_reg[18]\ => \phy_ctl_wd_i1_reg[18]\,
      \phy_ctl_wd_i1_reg[19]\ => \phy_ctl_wd_i1_reg[19]\,
      \phy_ctl_wd_i1_reg[21]\ => \phy_ctl_wd_i1_reg[21]\,
      \phy_ctl_wd_i1_reg[22]\ => \phy_ctl_wd_i1_reg[22]\,
      phy_data_wr_en => phy_data_wr_en,
      phy_dout(23) => mux_address(48),
      phy_dout(22) => mux_address(34),
      phy_dout(21) => mux_address(20),
      phy_dout(20) => mux_address(6),
      phy_dout(19) => mux_address(44),
      phy_dout(18) => mux_address(30),
      phy_dout(17) => mux_address(16),
      phy_dout(16) => mux_address(2),
      phy_dout(15) => mux_bank(9),
      phy_dout(14) => mux_bank(6),
      phy_dout(13) => mux_bank(3),
      phy_dout(12) => mux_bank(0),
      phy_dout(11) => mux_bank(10),
      phy_dout(10) => mux_bank(7),
      phy_dout(9) => mux_bank(4),
      phy_dout(8) => mux_bank(1),
      phy_dout(7) => mux_bank(11),
      phy_dout(6) => mux_bank(8),
      phy_dout(5) => mux_bank(5),
      phy_dout(4) => mux_bank(2),
      phy_dout(3) => mux_address(50),
      phy_dout(2) => mux_address(36),
      phy_dout(1) => mux_address(22),
      phy_dout(0) => mux_address(8),
      phy_if_reset => phy_if_reset,
      phy_rddata_en => phy_rddata_en,
      phy_read_calib => phy_read_calib,
      phy_write_calib => phy_write_calib,
      pi_cnt_dec_reg => pi_cnt_dec_reg,
      pi_counter_load_en => pi_counter_load_en,
      pi_counter_load_val(5 downto 0) => pi_counter_load_val(5 downto 0),
      \pi_dqs_found_lanes_r1_reg[0]\ => pi_fine_inc,
      \pi_dqs_found_lanes_r1_reg[0]_0\ => pi_counter_load_en,
      \pi_dqs_found_lanes_r1_reg[0]_1\(5 downto 0) => pi_counter_load_val(5 downto 0),
      pi_fine_enable => pi_fine_enable,
      pi_fine_inc => pi_fine_inc,
      pi_phase_locked_all_r1_reg => u_ddr_mc_phy_wrapper_n_64,
      pi_rst_dqs_find(2 downto 0) => pi_rst_dqs_find(2 downto 0),
      \pi_rst_stg1_cal_r_reg[1]\ => \pi_rst_stg1_cal_r_reg[1]\,
      \pi_rst_stg1_cal_reg[0]\ => u_ddr_calib_top_n_708,
      \pi_rst_stg1_cal_reg[2]\ => u_ddr_calib_top_n_740,
      pi_stg2_load_reg => u_ddr_calib_top_n_711,
      pi_stg2_load_reg_0 => u_ddr_calib_top_n_743,
      \pi_stg2_reg_l_reg[5]\(5 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/D_pi_counter_load_val\(5 downto 0),
      \pi_stg2_reg_l_reg[5]_0\(5 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/D_pi_counter_load_val\(5 downto 0),
      po_cnt_dec_2 => po_cnt_dec_2,
      po_cnt_dec_reg => po_cnt_dec_reg,
      po_en_stg2_f_reg => po_en_stg2_f_reg,
      \po_rdval_cnt_reg[0]\ => u_ddr_mc_phy_wrapper_n_1285,
      \po_rdval_cnt_reg[1]\ => u_ddr_mc_phy_wrapper_n_1286,
      \po_rdval_cnt_reg[2]\ => u_ddr_mc_phy_wrapper_n_1287,
      \po_rdval_cnt_reg[3]\ => u_ddr_mc_phy_wrapper_n_1288,
      \po_rdval_cnt_reg[4]\ => u_ddr_mc_phy_wrapper_n_1289,
      \po_rdval_cnt_reg[5]\ => u_ddr_mc_phy_wrapper_n_1290,
      \po_rdval_cnt_reg[6]\ => u_ddr_mc_phy_wrapper_n_1291,
      \po_rdval_cnt_reg[7]\ => u_ddr_mc_phy_wrapper_n_1292,
      \po_rdval_cnt_reg[8]\ => u_ddr_mc_phy_wrapper_n_1293,
      \po_stg2_wrcal_cnt_reg[2]\(2 downto 0) => po_stg2_wrcal_cnt(2 downto 0),
      prbs_rdlvl_done_pulse_reg => prbs_rdlvl_done_pulse_reg,
      \rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][0]\ => \rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][0]\,
      \rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][5]\(5 downto 0) => \rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][5]\(5 downto 0),
      \rank_final_loop[0].bank_final_loop[1].final_data_offset_mc_reg[0][11]\(5 downto 0) => \rank_final_loop[0].bank_final_loop[1].final_data_offset_mc_reg[0][11]\(5 downto 0),
      \rank_final_loop[0].bank_final_loop[1].final_data_offset_mc_reg[0][6]\ => \rank_final_loop[0].bank_final_loop[1].final_data_offset_mc_reg[0][6]\,
      \rank_final_loop[0].bank_final_loop[2].final_data_offset_mc_reg[0][12]\ => \rank_final_loop[0].bank_final_loop[2].final_data_offset_mc_reg[0][12]\,
      \rank_final_loop[0].bank_final_loop[2].final_data_offset_mc_reg[0][17]\(5 downto 0) => \rank_final_loop[0].bank_final_loop[2].final_data_offset_mc_reg[0][17]\(5 downto 0),
      \rd_mux_sel_r_reg[1]\(1) => u_ddr_calib_top_n_65,
      \rd_mux_sel_r_reg[1]\(0) => u_ddr_calib_top_n_66,
      \rd_mux_sel_r_reg[2]\ => u_ddr_calib_top_n_64,
      \rd_mux_sel_r_reg[2]_0\(2 downto 0) => \ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl/rd_mux_sel_r\(2 downto 0),
      \rdlvl_cpt_tap_cnt_reg[5]\(5 downto 0) => \u_ddr_mc_phy/pi_counter_read_val_w[2]_3\(5 downto 0),
      \rdlvl_cpt_tap_cnt_reg[5]_0\(5 downto 0) => \u_ddr_mc_phy/pi_counter_read_val_w[0]_1\(5 downto 0),
      \rdlvl_dqs_tap_cnt_r_reg[0][0][2]\(1 downto 0) => \rdlvl_dqs_tap_cnt_r_reg[0][0][2]\(1 downto 0),
      rdlvl_stg1_start_reg => rdlvl_stg1_start_reg,
      \read_fifo.tail_r\(0) => \read_fifo.tail_r\(0),
      \read_fifo.tail_r_reg[0]\ => \read_fifo.tail_r_reg[0]\,
      samp_edge_cnt0_en_r => samp_edge_cnt0_en_r,
      \samp_edge_cnt1_r_reg[0]\ => \samp_edge_cnt1_r_reg[0]\,
      \samples_cnt_r_reg[0]\ => \samples_cnt_r_reg[0]\,
      \tap_cnt_cpt_r_reg[5]\(0) => \tap_cnt_cpt_r_reg[5]\(0),
      \victim_sel_reg[0]\(0) => \victim_sel_reg[0]\(0),
      \wait_cnt_r_reg[0]\(0) => \wait_cnt_r_reg[0]\(0),
      \wait_cnt_r_reg[0]_0\(0) => \wait_cnt_r_reg[0]_0\(0),
      \wl_dqs_tap_count_r_reg[0][5][5]\ => \wl_dqs_tap_count_r_reg[0][5][5]\,
      \write_buffer.wr_buf_out_data_reg[448]\(7 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d1\(7 downto 0),
      \write_buffer.wr_buf_out_data_reg[450]\(7 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d3\(7 downto 0),
      \write_buffer.wr_buf_out_data_reg[451]\(7 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d4\(7 downto 0),
      \write_buffer.wr_buf_out_data_reg[452]\(7 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d5\(7 downto 0),
      \write_buffer.wr_buf_out_data_reg[453]\(7 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d6\(7 downto 0),
      \write_buffer.wr_buf_out_data_reg[454]\(7 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d7\(7 downto 0),
      \write_buffer.wr_buf_out_data_reg[455]\(71) => mux_wrdata(455),
      \write_buffer.wr_buf_out_data_reg[455]\(70) => mux_wrdata(391),
      \write_buffer.wr_buf_out_data_reg[455]\(69) => mux_wrdata(327),
      \write_buffer.wr_buf_out_data_reg[455]\(68) => mux_wrdata(263),
      \write_buffer.wr_buf_out_data_reg[455]\(67) => mux_wrdata(199),
      \write_buffer.wr_buf_out_data_reg[455]\(66) => mux_wrdata(135),
      \write_buffer.wr_buf_out_data_reg[455]\(65) => mux_wrdata(71),
      \write_buffer.wr_buf_out_data_reg[455]\(64) => mux_wrdata(7),
      \write_buffer.wr_buf_out_data_reg[455]\(63) => mux_wrdata(454),
      \write_buffer.wr_buf_out_data_reg[455]\(62) => mux_wrdata(390),
      \write_buffer.wr_buf_out_data_reg[455]\(61) => mux_wrdata(326),
      \write_buffer.wr_buf_out_data_reg[455]\(60) => mux_wrdata(262),
      \write_buffer.wr_buf_out_data_reg[455]\(59) => mux_wrdata(198),
      \write_buffer.wr_buf_out_data_reg[455]\(58) => mux_wrdata(134),
      \write_buffer.wr_buf_out_data_reg[455]\(57) => mux_wrdata(70),
      \write_buffer.wr_buf_out_data_reg[455]\(56) => mux_wrdata(6),
      \write_buffer.wr_buf_out_data_reg[455]\(55) => mux_wrdata(453),
      \write_buffer.wr_buf_out_data_reg[455]\(54) => mux_wrdata(389),
      \write_buffer.wr_buf_out_data_reg[455]\(53) => mux_wrdata(325),
      \write_buffer.wr_buf_out_data_reg[455]\(52) => mux_wrdata(261),
      \write_buffer.wr_buf_out_data_reg[455]\(51) => mux_wrdata(197),
      \write_buffer.wr_buf_out_data_reg[455]\(50) => mux_wrdata(133),
      \write_buffer.wr_buf_out_data_reg[455]\(49) => mux_wrdata(69),
      \write_buffer.wr_buf_out_data_reg[455]\(48) => mux_wrdata(5),
      \write_buffer.wr_buf_out_data_reg[455]\(47) => mux_wrdata(452),
      \write_buffer.wr_buf_out_data_reg[455]\(46) => mux_wrdata(388),
      \write_buffer.wr_buf_out_data_reg[455]\(45) => mux_wrdata(324),
      \write_buffer.wr_buf_out_data_reg[455]\(44) => mux_wrdata(260),
      \write_buffer.wr_buf_out_data_reg[455]\(43) => mux_wrdata(196),
      \write_buffer.wr_buf_out_data_reg[455]\(42) => mux_wrdata(132),
      \write_buffer.wr_buf_out_data_reg[455]\(41) => mux_wrdata(68),
      \write_buffer.wr_buf_out_data_reg[455]\(40) => mux_wrdata(4),
      \write_buffer.wr_buf_out_data_reg[455]\(39) => mux_wrdata(451),
      \write_buffer.wr_buf_out_data_reg[455]\(38) => mux_wrdata(387),
      \write_buffer.wr_buf_out_data_reg[455]\(37) => mux_wrdata(323),
      \write_buffer.wr_buf_out_data_reg[455]\(36) => mux_wrdata(259),
      \write_buffer.wr_buf_out_data_reg[455]\(35) => mux_wrdata(195),
      \write_buffer.wr_buf_out_data_reg[455]\(34) => mux_wrdata(131),
      \write_buffer.wr_buf_out_data_reg[455]\(33) => mux_wrdata(67),
      \write_buffer.wr_buf_out_data_reg[455]\(32) => mux_wrdata(3),
      \write_buffer.wr_buf_out_data_reg[455]\(31) => mux_wrdata(450),
      \write_buffer.wr_buf_out_data_reg[455]\(30) => mux_wrdata(386),
      \write_buffer.wr_buf_out_data_reg[455]\(29) => mux_wrdata(322),
      \write_buffer.wr_buf_out_data_reg[455]\(28) => mux_wrdata(258),
      \write_buffer.wr_buf_out_data_reg[455]\(27) => mux_wrdata(194),
      \write_buffer.wr_buf_out_data_reg[455]\(26) => mux_wrdata(130),
      \write_buffer.wr_buf_out_data_reg[455]\(25) => mux_wrdata(66),
      \write_buffer.wr_buf_out_data_reg[455]\(24) => mux_wrdata(2),
      \write_buffer.wr_buf_out_data_reg[455]\(23) => mux_wrdata(449),
      \write_buffer.wr_buf_out_data_reg[455]\(22) => mux_wrdata(385),
      \write_buffer.wr_buf_out_data_reg[455]\(21) => mux_wrdata(321),
      \write_buffer.wr_buf_out_data_reg[455]\(20) => mux_wrdata(257),
      \write_buffer.wr_buf_out_data_reg[455]\(19) => mux_wrdata(193),
      \write_buffer.wr_buf_out_data_reg[455]\(18) => mux_wrdata(129),
      \write_buffer.wr_buf_out_data_reg[455]\(17) => mux_wrdata(65),
      \write_buffer.wr_buf_out_data_reg[455]\(16) => mux_wrdata(1),
      \write_buffer.wr_buf_out_data_reg[455]\(15) => mux_wrdata(448),
      \write_buffer.wr_buf_out_data_reg[455]\(14) => mux_wrdata(384),
      \write_buffer.wr_buf_out_data_reg[455]\(13) => mux_wrdata(320),
      \write_buffer.wr_buf_out_data_reg[455]\(12) => mux_wrdata(256),
      \write_buffer.wr_buf_out_data_reg[455]\(11) => mux_wrdata(192),
      \write_buffer.wr_buf_out_data_reg[455]\(10) => mux_wrdata(128),
      \write_buffer.wr_buf_out_data_reg[455]\(9) => mux_wrdata(64),
      \write_buffer.wr_buf_out_data_reg[455]\(8) => mux_wrdata(0),
      \write_buffer.wr_buf_out_data_reg[455]\(7) => mux_wrdata_mask(56),
      \write_buffer.wr_buf_out_data_reg[455]\(6) => mux_wrdata_mask(48),
      \write_buffer.wr_buf_out_data_reg[455]\(5) => mux_wrdata_mask(40),
      \write_buffer.wr_buf_out_data_reg[455]\(4) => mux_wrdata_mask(32),
      \write_buffer.wr_buf_out_data_reg[455]\(3) => mux_wrdata_mask(24),
      \write_buffer.wr_buf_out_data_reg[455]\(2) => mux_wrdata_mask(16),
      \write_buffer.wr_buf_out_data_reg[455]\(1) => mux_wrdata_mask(8),
      \write_buffer.wr_buf_out_data_reg[455]\(0) => mux_wrdata_mask(0),
      \write_buffer.wr_buf_out_data_reg[455]_0\(7 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d9\(7 downto 0),
      \write_buffer.wr_buf_out_data_reg[456]\(7 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d2\(7 downto 0),
      \write_buffer.wr_buf_out_data_reg[457]\(7 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d3\(7 downto 0),
      \write_buffer.wr_buf_out_data_reg[458]\(7 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d4\(7 downto 0),
      \write_buffer.wr_buf_out_data_reg[459]\(7 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d5\(7 downto 0),
      \write_buffer.wr_buf_out_data_reg[460]\(7 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d6\(7 downto 0),
      \write_buffer.wr_buf_out_data_reg[461]\(7 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d7\(7 downto 0),
      \write_buffer.wr_buf_out_data_reg[462]\(7 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d8\(7 downto 0),
      \write_buffer.wr_buf_out_data_reg[463]\(71) => mux_wrdata(463),
      \write_buffer.wr_buf_out_data_reg[463]\(70) => mux_wrdata(399),
      \write_buffer.wr_buf_out_data_reg[463]\(69) => mux_wrdata(335),
      \write_buffer.wr_buf_out_data_reg[463]\(68) => mux_wrdata(271),
      \write_buffer.wr_buf_out_data_reg[463]\(67) => mux_wrdata(207),
      \write_buffer.wr_buf_out_data_reg[463]\(66) => mux_wrdata(143),
      \write_buffer.wr_buf_out_data_reg[463]\(65) => mux_wrdata(79),
      \write_buffer.wr_buf_out_data_reg[463]\(64) => mux_wrdata(15),
      \write_buffer.wr_buf_out_data_reg[463]\(63) => mux_wrdata(462),
      \write_buffer.wr_buf_out_data_reg[463]\(62) => mux_wrdata(398),
      \write_buffer.wr_buf_out_data_reg[463]\(61) => mux_wrdata(334),
      \write_buffer.wr_buf_out_data_reg[463]\(60) => mux_wrdata(270),
      \write_buffer.wr_buf_out_data_reg[463]\(59) => mux_wrdata(206),
      \write_buffer.wr_buf_out_data_reg[463]\(58) => mux_wrdata(142),
      \write_buffer.wr_buf_out_data_reg[463]\(57) => mux_wrdata(78),
      \write_buffer.wr_buf_out_data_reg[463]\(56) => mux_wrdata(14),
      \write_buffer.wr_buf_out_data_reg[463]\(55) => mux_wrdata(461),
      \write_buffer.wr_buf_out_data_reg[463]\(54) => mux_wrdata(397),
      \write_buffer.wr_buf_out_data_reg[463]\(53) => mux_wrdata(333),
      \write_buffer.wr_buf_out_data_reg[463]\(52) => mux_wrdata(269),
      \write_buffer.wr_buf_out_data_reg[463]\(51) => mux_wrdata(205),
      \write_buffer.wr_buf_out_data_reg[463]\(50) => mux_wrdata(141),
      \write_buffer.wr_buf_out_data_reg[463]\(49) => mux_wrdata(77),
      \write_buffer.wr_buf_out_data_reg[463]\(48) => mux_wrdata(13),
      \write_buffer.wr_buf_out_data_reg[463]\(47) => mux_wrdata(460),
      \write_buffer.wr_buf_out_data_reg[463]\(46) => mux_wrdata(396),
      \write_buffer.wr_buf_out_data_reg[463]\(45) => mux_wrdata(332),
      \write_buffer.wr_buf_out_data_reg[463]\(44) => mux_wrdata(268),
      \write_buffer.wr_buf_out_data_reg[463]\(43) => mux_wrdata(204),
      \write_buffer.wr_buf_out_data_reg[463]\(42) => mux_wrdata(140),
      \write_buffer.wr_buf_out_data_reg[463]\(41) => mux_wrdata(76),
      \write_buffer.wr_buf_out_data_reg[463]\(40) => mux_wrdata(12),
      \write_buffer.wr_buf_out_data_reg[463]\(39) => mux_wrdata(459),
      \write_buffer.wr_buf_out_data_reg[463]\(38) => mux_wrdata(395),
      \write_buffer.wr_buf_out_data_reg[463]\(37) => mux_wrdata(331),
      \write_buffer.wr_buf_out_data_reg[463]\(36) => mux_wrdata(267),
      \write_buffer.wr_buf_out_data_reg[463]\(35) => mux_wrdata(203),
      \write_buffer.wr_buf_out_data_reg[463]\(34) => mux_wrdata(139),
      \write_buffer.wr_buf_out_data_reg[463]\(33) => mux_wrdata(75),
      \write_buffer.wr_buf_out_data_reg[463]\(32) => mux_wrdata(11),
      \write_buffer.wr_buf_out_data_reg[463]\(31) => mux_wrdata(458),
      \write_buffer.wr_buf_out_data_reg[463]\(30) => mux_wrdata(394),
      \write_buffer.wr_buf_out_data_reg[463]\(29) => mux_wrdata(330),
      \write_buffer.wr_buf_out_data_reg[463]\(28) => mux_wrdata(266),
      \write_buffer.wr_buf_out_data_reg[463]\(27) => mux_wrdata(202),
      \write_buffer.wr_buf_out_data_reg[463]\(26) => mux_wrdata(138),
      \write_buffer.wr_buf_out_data_reg[463]\(25) => mux_wrdata(74),
      \write_buffer.wr_buf_out_data_reg[463]\(24) => mux_wrdata(10),
      \write_buffer.wr_buf_out_data_reg[463]\(23) => mux_wrdata(457),
      \write_buffer.wr_buf_out_data_reg[463]\(22) => mux_wrdata(393),
      \write_buffer.wr_buf_out_data_reg[463]\(21) => mux_wrdata(329),
      \write_buffer.wr_buf_out_data_reg[463]\(20) => mux_wrdata(265),
      \write_buffer.wr_buf_out_data_reg[463]\(19) => mux_wrdata(201),
      \write_buffer.wr_buf_out_data_reg[463]\(18) => mux_wrdata(137),
      \write_buffer.wr_buf_out_data_reg[463]\(17) => mux_wrdata(73),
      \write_buffer.wr_buf_out_data_reg[463]\(16) => mux_wrdata(9),
      \write_buffer.wr_buf_out_data_reg[463]\(15) => mux_wrdata(456),
      \write_buffer.wr_buf_out_data_reg[463]\(14) => mux_wrdata(392),
      \write_buffer.wr_buf_out_data_reg[463]\(13) => mux_wrdata(328),
      \write_buffer.wr_buf_out_data_reg[463]\(12) => mux_wrdata(264),
      \write_buffer.wr_buf_out_data_reg[463]\(11) => mux_wrdata(200),
      \write_buffer.wr_buf_out_data_reg[463]\(10) => mux_wrdata(136),
      \write_buffer.wr_buf_out_data_reg[463]\(9) => mux_wrdata(72),
      \write_buffer.wr_buf_out_data_reg[463]\(8) => mux_wrdata(8),
      \write_buffer.wr_buf_out_data_reg[463]\(7) => mux_wrdata_mask(57),
      \write_buffer.wr_buf_out_data_reg[463]\(6) => mux_wrdata_mask(49),
      \write_buffer.wr_buf_out_data_reg[463]\(5) => mux_wrdata_mask(41),
      \write_buffer.wr_buf_out_data_reg[463]\(4) => mux_wrdata_mask(33),
      \write_buffer.wr_buf_out_data_reg[463]\(3) => mux_wrdata_mask(25),
      \write_buffer.wr_buf_out_data_reg[463]\(2) => mux_wrdata_mask(17),
      \write_buffer.wr_buf_out_data_reg[463]\(1) => mux_wrdata_mask(9),
      \write_buffer.wr_buf_out_data_reg[463]\(0) => mux_wrdata_mask(1),
      \write_buffer.wr_buf_out_data_reg[463]_0\(7 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d9\(7 downto 0),
      \write_buffer.wr_buf_out_data_reg[464]\(7 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d2\(7 downto 0),
      \write_buffer.wr_buf_out_data_reg[465]\(7 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d3\(7 downto 0),
      \write_buffer.wr_buf_out_data_reg[466]\(7 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d4\(7 downto 0),
      \write_buffer.wr_buf_out_data_reg[467]\(7 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d5\(7 downto 0),
      \write_buffer.wr_buf_out_data_reg[468]\(7 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d6\(7 downto 0),
      \write_buffer.wr_buf_out_data_reg[469]\(7 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d7\(7 downto 0),
      \write_buffer.wr_buf_out_data_reg[470]\(7 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d8\(7 downto 0),
      \write_buffer.wr_buf_out_data_reg[471]\(71) => mux_wrdata(471),
      \write_buffer.wr_buf_out_data_reg[471]\(70) => mux_wrdata(407),
      \write_buffer.wr_buf_out_data_reg[471]\(69) => mux_wrdata(343),
      \write_buffer.wr_buf_out_data_reg[471]\(68) => mux_wrdata(279),
      \write_buffer.wr_buf_out_data_reg[471]\(67) => mux_wrdata(215),
      \write_buffer.wr_buf_out_data_reg[471]\(66) => mux_wrdata(151),
      \write_buffer.wr_buf_out_data_reg[471]\(65) => mux_wrdata(87),
      \write_buffer.wr_buf_out_data_reg[471]\(64) => mux_wrdata(23),
      \write_buffer.wr_buf_out_data_reg[471]\(63) => mux_wrdata(470),
      \write_buffer.wr_buf_out_data_reg[471]\(62) => mux_wrdata(406),
      \write_buffer.wr_buf_out_data_reg[471]\(61) => mux_wrdata(342),
      \write_buffer.wr_buf_out_data_reg[471]\(60) => mux_wrdata(278),
      \write_buffer.wr_buf_out_data_reg[471]\(59) => mux_wrdata(214),
      \write_buffer.wr_buf_out_data_reg[471]\(58) => mux_wrdata(150),
      \write_buffer.wr_buf_out_data_reg[471]\(57) => mux_wrdata(86),
      \write_buffer.wr_buf_out_data_reg[471]\(56) => mux_wrdata(22),
      \write_buffer.wr_buf_out_data_reg[471]\(55) => mux_wrdata(469),
      \write_buffer.wr_buf_out_data_reg[471]\(54) => mux_wrdata(405),
      \write_buffer.wr_buf_out_data_reg[471]\(53) => mux_wrdata(341),
      \write_buffer.wr_buf_out_data_reg[471]\(52) => mux_wrdata(277),
      \write_buffer.wr_buf_out_data_reg[471]\(51) => mux_wrdata(213),
      \write_buffer.wr_buf_out_data_reg[471]\(50) => mux_wrdata(149),
      \write_buffer.wr_buf_out_data_reg[471]\(49) => mux_wrdata(85),
      \write_buffer.wr_buf_out_data_reg[471]\(48) => mux_wrdata(21),
      \write_buffer.wr_buf_out_data_reg[471]\(47) => mux_wrdata(468),
      \write_buffer.wr_buf_out_data_reg[471]\(46) => mux_wrdata(404),
      \write_buffer.wr_buf_out_data_reg[471]\(45) => mux_wrdata(340),
      \write_buffer.wr_buf_out_data_reg[471]\(44) => mux_wrdata(276),
      \write_buffer.wr_buf_out_data_reg[471]\(43) => mux_wrdata(212),
      \write_buffer.wr_buf_out_data_reg[471]\(42) => mux_wrdata(148),
      \write_buffer.wr_buf_out_data_reg[471]\(41) => mux_wrdata(84),
      \write_buffer.wr_buf_out_data_reg[471]\(40) => mux_wrdata(20),
      \write_buffer.wr_buf_out_data_reg[471]\(39) => mux_wrdata(467),
      \write_buffer.wr_buf_out_data_reg[471]\(38) => mux_wrdata(403),
      \write_buffer.wr_buf_out_data_reg[471]\(37) => mux_wrdata(339),
      \write_buffer.wr_buf_out_data_reg[471]\(36) => mux_wrdata(275),
      \write_buffer.wr_buf_out_data_reg[471]\(35) => mux_wrdata(211),
      \write_buffer.wr_buf_out_data_reg[471]\(34) => mux_wrdata(147),
      \write_buffer.wr_buf_out_data_reg[471]\(33) => mux_wrdata(83),
      \write_buffer.wr_buf_out_data_reg[471]\(32) => mux_wrdata(19),
      \write_buffer.wr_buf_out_data_reg[471]\(31) => mux_wrdata(466),
      \write_buffer.wr_buf_out_data_reg[471]\(30) => mux_wrdata(402),
      \write_buffer.wr_buf_out_data_reg[471]\(29) => mux_wrdata(338),
      \write_buffer.wr_buf_out_data_reg[471]\(28) => mux_wrdata(274),
      \write_buffer.wr_buf_out_data_reg[471]\(27) => mux_wrdata(210),
      \write_buffer.wr_buf_out_data_reg[471]\(26) => mux_wrdata(146),
      \write_buffer.wr_buf_out_data_reg[471]\(25) => mux_wrdata(82),
      \write_buffer.wr_buf_out_data_reg[471]\(24) => mux_wrdata(18),
      \write_buffer.wr_buf_out_data_reg[471]\(23) => mux_wrdata(465),
      \write_buffer.wr_buf_out_data_reg[471]\(22) => mux_wrdata(401),
      \write_buffer.wr_buf_out_data_reg[471]\(21) => mux_wrdata(337),
      \write_buffer.wr_buf_out_data_reg[471]\(20) => mux_wrdata(273),
      \write_buffer.wr_buf_out_data_reg[471]\(19) => mux_wrdata(209),
      \write_buffer.wr_buf_out_data_reg[471]\(18) => mux_wrdata(145),
      \write_buffer.wr_buf_out_data_reg[471]\(17) => mux_wrdata(81),
      \write_buffer.wr_buf_out_data_reg[471]\(16) => mux_wrdata(17),
      \write_buffer.wr_buf_out_data_reg[471]\(15) => mux_wrdata(464),
      \write_buffer.wr_buf_out_data_reg[471]\(14) => mux_wrdata(400),
      \write_buffer.wr_buf_out_data_reg[471]\(13) => mux_wrdata(336),
      \write_buffer.wr_buf_out_data_reg[471]\(12) => mux_wrdata(272),
      \write_buffer.wr_buf_out_data_reg[471]\(11) => mux_wrdata(208),
      \write_buffer.wr_buf_out_data_reg[471]\(10) => mux_wrdata(144),
      \write_buffer.wr_buf_out_data_reg[471]\(9) => mux_wrdata(80),
      \write_buffer.wr_buf_out_data_reg[471]\(8) => mux_wrdata(16),
      \write_buffer.wr_buf_out_data_reg[471]\(7) => mux_wrdata_mask(58),
      \write_buffer.wr_buf_out_data_reg[471]\(6) => mux_wrdata_mask(50),
      \write_buffer.wr_buf_out_data_reg[471]\(5) => mux_wrdata_mask(42),
      \write_buffer.wr_buf_out_data_reg[471]\(4) => mux_wrdata_mask(34),
      \write_buffer.wr_buf_out_data_reg[471]\(3) => mux_wrdata_mask(26),
      \write_buffer.wr_buf_out_data_reg[471]\(2) => mux_wrdata_mask(18),
      \write_buffer.wr_buf_out_data_reg[471]\(1) => mux_wrdata_mask(10),
      \write_buffer.wr_buf_out_data_reg[471]\(0) => mux_wrdata_mask(2),
      \write_buffer.wr_buf_out_data_reg[471]_0\(7 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d9\(7 downto 0),
      \write_buffer.wr_buf_out_data_reg[472]\(7 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d2\(7 downto 0),
      \write_buffer.wr_buf_out_data_reg[473]\(7 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d3\(7 downto 0),
      \write_buffer.wr_buf_out_data_reg[474]\(7 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d4\(7 downto 0),
      \write_buffer.wr_buf_out_data_reg[475]\(7 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d5\(7 downto 0),
      \write_buffer.wr_buf_out_data_reg[476]\(7 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d6\(7 downto 0),
      \write_buffer.wr_buf_out_data_reg[477]\(7 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d7\(7 downto 0),
      \write_buffer.wr_buf_out_data_reg[478]\(7 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d8\(7 downto 0),
      \write_buffer.wr_buf_out_data_reg[479]\(71) => mux_wrdata(479),
      \write_buffer.wr_buf_out_data_reg[479]\(70) => mux_wrdata(415),
      \write_buffer.wr_buf_out_data_reg[479]\(69) => mux_wrdata(351),
      \write_buffer.wr_buf_out_data_reg[479]\(68) => mux_wrdata(287),
      \write_buffer.wr_buf_out_data_reg[479]\(67) => mux_wrdata(223),
      \write_buffer.wr_buf_out_data_reg[479]\(66) => mux_wrdata(159),
      \write_buffer.wr_buf_out_data_reg[479]\(65) => mux_wrdata(95),
      \write_buffer.wr_buf_out_data_reg[479]\(64) => mux_wrdata(31),
      \write_buffer.wr_buf_out_data_reg[479]\(63) => mux_wrdata(478),
      \write_buffer.wr_buf_out_data_reg[479]\(62) => mux_wrdata(414),
      \write_buffer.wr_buf_out_data_reg[479]\(61) => mux_wrdata(350),
      \write_buffer.wr_buf_out_data_reg[479]\(60) => mux_wrdata(286),
      \write_buffer.wr_buf_out_data_reg[479]\(59) => mux_wrdata(222),
      \write_buffer.wr_buf_out_data_reg[479]\(58) => mux_wrdata(158),
      \write_buffer.wr_buf_out_data_reg[479]\(57) => mux_wrdata(94),
      \write_buffer.wr_buf_out_data_reg[479]\(56) => mux_wrdata(30),
      \write_buffer.wr_buf_out_data_reg[479]\(55) => mux_wrdata(477),
      \write_buffer.wr_buf_out_data_reg[479]\(54) => mux_wrdata(413),
      \write_buffer.wr_buf_out_data_reg[479]\(53) => mux_wrdata(349),
      \write_buffer.wr_buf_out_data_reg[479]\(52) => mux_wrdata(285),
      \write_buffer.wr_buf_out_data_reg[479]\(51) => mux_wrdata(221),
      \write_buffer.wr_buf_out_data_reg[479]\(50) => mux_wrdata(157),
      \write_buffer.wr_buf_out_data_reg[479]\(49) => mux_wrdata(93),
      \write_buffer.wr_buf_out_data_reg[479]\(48) => mux_wrdata(29),
      \write_buffer.wr_buf_out_data_reg[479]\(47) => mux_wrdata(476),
      \write_buffer.wr_buf_out_data_reg[479]\(46) => mux_wrdata(412),
      \write_buffer.wr_buf_out_data_reg[479]\(45) => mux_wrdata(348),
      \write_buffer.wr_buf_out_data_reg[479]\(44) => mux_wrdata(284),
      \write_buffer.wr_buf_out_data_reg[479]\(43) => mux_wrdata(220),
      \write_buffer.wr_buf_out_data_reg[479]\(42) => mux_wrdata(156),
      \write_buffer.wr_buf_out_data_reg[479]\(41) => mux_wrdata(92),
      \write_buffer.wr_buf_out_data_reg[479]\(40) => mux_wrdata(28),
      \write_buffer.wr_buf_out_data_reg[479]\(39) => mux_wrdata(475),
      \write_buffer.wr_buf_out_data_reg[479]\(38) => mux_wrdata(411),
      \write_buffer.wr_buf_out_data_reg[479]\(37) => mux_wrdata(347),
      \write_buffer.wr_buf_out_data_reg[479]\(36) => mux_wrdata(283),
      \write_buffer.wr_buf_out_data_reg[479]\(35) => mux_wrdata(219),
      \write_buffer.wr_buf_out_data_reg[479]\(34) => mux_wrdata(155),
      \write_buffer.wr_buf_out_data_reg[479]\(33) => mux_wrdata(91),
      \write_buffer.wr_buf_out_data_reg[479]\(32) => mux_wrdata(27),
      \write_buffer.wr_buf_out_data_reg[479]\(31) => mux_wrdata(474),
      \write_buffer.wr_buf_out_data_reg[479]\(30) => mux_wrdata(410),
      \write_buffer.wr_buf_out_data_reg[479]\(29) => mux_wrdata(346),
      \write_buffer.wr_buf_out_data_reg[479]\(28) => mux_wrdata(282),
      \write_buffer.wr_buf_out_data_reg[479]\(27) => mux_wrdata(218),
      \write_buffer.wr_buf_out_data_reg[479]\(26) => mux_wrdata(154),
      \write_buffer.wr_buf_out_data_reg[479]\(25) => mux_wrdata(90),
      \write_buffer.wr_buf_out_data_reg[479]\(24) => mux_wrdata(26),
      \write_buffer.wr_buf_out_data_reg[479]\(23) => mux_wrdata(473),
      \write_buffer.wr_buf_out_data_reg[479]\(22) => mux_wrdata(409),
      \write_buffer.wr_buf_out_data_reg[479]\(21) => mux_wrdata(345),
      \write_buffer.wr_buf_out_data_reg[479]\(20) => mux_wrdata(281),
      \write_buffer.wr_buf_out_data_reg[479]\(19) => mux_wrdata(217),
      \write_buffer.wr_buf_out_data_reg[479]\(18) => mux_wrdata(153),
      \write_buffer.wr_buf_out_data_reg[479]\(17) => mux_wrdata(89),
      \write_buffer.wr_buf_out_data_reg[479]\(16) => mux_wrdata(25),
      \write_buffer.wr_buf_out_data_reg[479]\(15) => mux_wrdata(472),
      \write_buffer.wr_buf_out_data_reg[479]\(14) => mux_wrdata(408),
      \write_buffer.wr_buf_out_data_reg[479]\(13) => mux_wrdata(344),
      \write_buffer.wr_buf_out_data_reg[479]\(12) => mux_wrdata(280),
      \write_buffer.wr_buf_out_data_reg[479]\(11) => mux_wrdata(216),
      \write_buffer.wr_buf_out_data_reg[479]\(10) => mux_wrdata(152),
      \write_buffer.wr_buf_out_data_reg[479]\(9) => mux_wrdata(88),
      \write_buffer.wr_buf_out_data_reg[479]\(8) => mux_wrdata(24),
      \write_buffer.wr_buf_out_data_reg[479]\(7) => mux_wrdata_mask(59),
      \write_buffer.wr_buf_out_data_reg[479]\(6) => mux_wrdata_mask(51),
      \write_buffer.wr_buf_out_data_reg[479]\(5) => mux_wrdata_mask(43),
      \write_buffer.wr_buf_out_data_reg[479]\(4) => mux_wrdata_mask(35),
      \write_buffer.wr_buf_out_data_reg[479]\(3) => mux_wrdata_mask(27),
      \write_buffer.wr_buf_out_data_reg[479]\(2) => mux_wrdata_mask(19),
      \write_buffer.wr_buf_out_data_reg[479]\(1) => mux_wrdata_mask(11),
      \write_buffer.wr_buf_out_data_reg[479]\(0) => mux_wrdata_mask(3),
      \write_buffer.wr_buf_out_data_reg[479]_0\(7 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d9\(7 downto 0),
      \write_buffer.wr_buf_out_data_reg[480]\(7 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d1\(7 downto 0),
      \write_buffer.wr_buf_out_data_reg[481]\(7 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d2\(7 downto 0),
      \write_buffer.wr_buf_out_data_reg[482]\(7 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d3\(7 downto 0),
      \write_buffer.wr_buf_out_data_reg[483]\(7 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d4\(7 downto 0),
      \write_buffer.wr_buf_out_data_reg[484]\(7 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d5\(7 downto 0),
      \write_buffer.wr_buf_out_data_reg[485]\(7 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d6\(7 downto 0),
      \write_buffer.wr_buf_out_data_reg[486]\(7 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d7\(7 downto 0),
      \write_buffer.wr_buf_out_data_reg[487]\(71) => mux_wrdata(487),
      \write_buffer.wr_buf_out_data_reg[487]\(70) => mux_wrdata(423),
      \write_buffer.wr_buf_out_data_reg[487]\(69) => mux_wrdata(359),
      \write_buffer.wr_buf_out_data_reg[487]\(68) => mux_wrdata(295),
      \write_buffer.wr_buf_out_data_reg[487]\(67) => mux_wrdata(231),
      \write_buffer.wr_buf_out_data_reg[487]\(66) => mux_wrdata(167),
      \write_buffer.wr_buf_out_data_reg[487]\(65) => mux_wrdata(103),
      \write_buffer.wr_buf_out_data_reg[487]\(64) => mux_wrdata(39),
      \write_buffer.wr_buf_out_data_reg[487]\(63) => mux_wrdata(486),
      \write_buffer.wr_buf_out_data_reg[487]\(62) => mux_wrdata(422),
      \write_buffer.wr_buf_out_data_reg[487]\(61) => mux_wrdata(358),
      \write_buffer.wr_buf_out_data_reg[487]\(60) => mux_wrdata(294),
      \write_buffer.wr_buf_out_data_reg[487]\(59) => mux_wrdata(230),
      \write_buffer.wr_buf_out_data_reg[487]\(58) => mux_wrdata(166),
      \write_buffer.wr_buf_out_data_reg[487]\(57) => mux_wrdata(102),
      \write_buffer.wr_buf_out_data_reg[487]\(56) => mux_wrdata(38),
      \write_buffer.wr_buf_out_data_reg[487]\(55) => mux_wrdata(485),
      \write_buffer.wr_buf_out_data_reg[487]\(54) => mux_wrdata(421),
      \write_buffer.wr_buf_out_data_reg[487]\(53) => mux_wrdata(357),
      \write_buffer.wr_buf_out_data_reg[487]\(52) => mux_wrdata(293),
      \write_buffer.wr_buf_out_data_reg[487]\(51) => mux_wrdata(229),
      \write_buffer.wr_buf_out_data_reg[487]\(50) => mux_wrdata(165),
      \write_buffer.wr_buf_out_data_reg[487]\(49) => mux_wrdata(101),
      \write_buffer.wr_buf_out_data_reg[487]\(48) => mux_wrdata(37),
      \write_buffer.wr_buf_out_data_reg[487]\(47) => mux_wrdata(484),
      \write_buffer.wr_buf_out_data_reg[487]\(46) => mux_wrdata(420),
      \write_buffer.wr_buf_out_data_reg[487]\(45) => mux_wrdata(356),
      \write_buffer.wr_buf_out_data_reg[487]\(44) => mux_wrdata(292),
      \write_buffer.wr_buf_out_data_reg[487]\(43) => mux_wrdata(228),
      \write_buffer.wr_buf_out_data_reg[487]\(42) => mux_wrdata(164),
      \write_buffer.wr_buf_out_data_reg[487]\(41) => mux_wrdata(100),
      \write_buffer.wr_buf_out_data_reg[487]\(40) => mux_wrdata(36),
      \write_buffer.wr_buf_out_data_reg[487]\(39) => mux_wrdata(483),
      \write_buffer.wr_buf_out_data_reg[487]\(38) => mux_wrdata(419),
      \write_buffer.wr_buf_out_data_reg[487]\(37) => mux_wrdata(355),
      \write_buffer.wr_buf_out_data_reg[487]\(36) => mux_wrdata(291),
      \write_buffer.wr_buf_out_data_reg[487]\(35) => mux_wrdata(227),
      \write_buffer.wr_buf_out_data_reg[487]\(34) => mux_wrdata(163),
      \write_buffer.wr_buf_out_data_reg[487]\(33) => mux_wrdata(99),
      \write_buffer.wr_buf_out_data_reg[487]\(32) => mux_wrdata(35),
      \write_buffer.wr_buf_out_data_reg[487]\(31) => mux_wrdata(482),
      \write_buffer.wr_buf_out_data_reg[487]\(30) => mux_wrdata(418),
      \write_buffer.wr_buf_out_data_reg[487]\(29) => mux_wrdata(354),
      \write_buffer.wr_buf_out_data_reg[487]\(28) => mux_wrdata(290),
      \write_buffer.wr_buf_out_data_reg[487]\(27) => mux_wrdata(226),
      \write_buffer.wr_buf_out_data_reg[487]\(26) => mux_wrdata(162),
      \write_buffer.wr_buf_out_data_reg[487]\(25) => mux_wrdata(98),
      \write_buffer.wr_buf_out_data_reg[487]\(24) => mux_wrdata(34),
      \write_buffer.wr_buf_out_data_reg[487]\(23) => mux_wrdata(481),
      \write_buffer.wr_buf_out_data_reg[487]\(22) => mux_wrdata(417),
      \write_buffer.wr_buf_out_data_reg[487]\(21) => mux_wrdata(353),
      \write_buffer.wr_buf_out_data_reg[487]\(20) => mux_wrdata(289),
      \write_buffer.wr_buf_out_data_reg[487]\(19) => mux_wrdata(225),
      \write_buffer.wr_buf_out_data_reg[487]\(18) => mux_wrdata(161),
      \write_buffer.wr_buf_out_data_reg[487]\(17) => mux_wrdata(97),
      \write_buffer.wr_buf_out_data_reg[487]\(16) => mux_wrdata(33),
      \write_buffer.wr_buf_out_data_reg[487]\(15) => mux_wrdata(480),
      \write_buffer.wr_buf_out_data_reg[487]\(14) => mux_wrdata(416),
      \write_buffer.wr_buf_out_data_reg[487]\(13) => mux_wrdata(352),
      \write_buffer.wr_buf_out_data_reg[487]\(12) => mux_wrdata(288),
      \write_buffer.wr_buf_out_data_reg[487]\(11) => mux_wrdata(224),
      \write_buffer.wr_buf_out_data_reg[487]\(10) => mux_wrdata(160),
      \write_buffer.wr_buf_out_data_reg[487]\(9) => mux_wrdata(96),
      \write_buffer.wr_buf_out_data_reg[487]\(8) => mux_wrdata(32),
      \write_buffer.wr_buf_out_data_reg[487]\(7) => mux_wrdata_mask(60),
      \write_buffer.wr_buf_out_data_reg[487]\(6) => mux_wrdata_mask(52),
      \write_buffer.wr_buf_out_data_reg[487]\(5) => mux_wrdata_mask(44),
      \write_buffer.wr_buf_out_data_reg[487]\(4) => mux_wrdata_mask(36),
      \write_buffer.wr_buf_out_data_reg[487]\(3) => mux_wrdata_mask(28),
      \write_buffer.wr_buf_out_data_reg[487]\(2) => mux_wrdata_mask(20),
      \write_buffer.wr_buf_out_data_reg[487]\(1) => mux_wrdata_mask(12),
      \write_buffer.wr_buf_out_data_reg[487]\(0) => mux_wrdata_mask(4),
      \write_buffer.wr_buf_out_data_reg[487]_0\(7 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d9\(7 downto 0),
      \write_buffer.wr_buf_out_data_reg[488]\(7 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d2\(7 downto 0),
      \write_buffer.wr_buf_out_data_reg[489]\(7 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d3\(7 downto 0),
      \write_buffer.wr_buf_out_data_reg[490]\(7 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d4\(7 downto 0),
      \write_buffer.wr_buf_out_data_reg[491]\(7 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d5\(7 downto 0),
      \write_buffer.wr_buf_out_data_reg[492]\(7 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d6\(7 downto 0),
      \write_buffer.wr_buf_out_data_reg[493]\(7 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d7\(7 downto 0),
      \write_buffer.wr_buf_out_data_reg[494]\(7 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d8\(7 downto 0),
      \write_buffer.wr_buf_out_data_reg[495]\(71) => mux_wrdata(495),
      \write_buffer.wr_buf_out_data_reg[495]\(70) => mux_wrdata(431),
      \write_buffer.wr_buf_out_data_reg[495]\(69) => mux_wrdata(367),
      \write_buffer.wr_buf_out_data_reg[495]\(68) => mux_wrdata(303),
      \write_buffer.wr_buf_out_data_reg[495]\(67) => mux_wrdata(239),
      \write_buffer.wr_buf_out_data_reg[495]\(66) => mux_wrdata(175),
      \write_buffer.wr_buf_out_data_reg[495]\(65) => mux_wrdata(111),
      \write_buffer.wr_buf_out_data_reg[495]\(64) => mux_wrdata(47),
      \write_buffer.wr_buf_out_data_reg[495]\(63) => mux_wrdata(494),
      \write_buffer.wr_buf_out_data_reg[495]\(62) => mux_wrdata(430),
      \write_buffer.wr_buf_out_data_reg[495]\(61) => mux_wrdata(366),
      \write_buffer.wr_buf_out_data_reg[495]\(60) => mux_wrdata(302),
      \write_buffer.wr_buf_out_data_reg[495]\(59) => mux_wrdata(238),
      \write_buffer.wr_buf_out_data_reg[495]\(58) => mux_wrdata(174),
      \write_buffer.wr_buf_out_data_reg[495]\(57) => mux_wrdata(110),
      \write_buffer.wr_buf_out_data_reg[495]\(56) => mux_wrdata(46),
      \write_buffer.wr_buf_out_data_reg[495]\(55) => mux_wrdata(493),
      \write_buffer.wr_buf_out_data_reg[495]\(54) => mux_wrdata(429),
      \write_buffer.wr_buf_out_data_reg[495]\(53) => mux_wrdata(365),
      \write_buffer.wr_buf_out_data_reg[495]\(52) => mux_wrdata(301),
      \write_buffer.wr_buf_out_data_reg[495]\(51) => mux_wrdata(237),
      \write_buffer.wr_buf_out_data_reg[495]\(50) => mux_wrdata(173),
      \write_buffer.wr_buf_out_data_reg[495]\(49) => mux_wrdata(109),
      \write_buffer.wr_buf_out_data_reg[495]\(48) => mux_wrdata(45),
      \write_buffer.wr_buf_out_data_reg[495]\(47) => mux_wrdata(492),
      \write_buffer.wr_buf_out_data_reg[495]\(46) => mux_wrdata(428),
      \write_buffer.wr_buf_out_data_reg[495]\(45) => mux_wrdata(364),
      \write_buffer.wr_buf_out_data_reg[495]\(44) => mux_wrdata(300),
      \write_buffer.wr_buf_out_data_reg[495]\(43) => mux_wrdata(236),
      \write_buffer.wr_buf_out_data_reg[495]\(42) => mux_wrdata(172),
      \write_buffer.wr_buf_out_data_reg[495]\(41) => mux_wrdata(108),
      \write_buffer.wr_buf_out_data_reg[495]\(40) => mux_wrdata(44),
      \write_buffer.wr_buf_out_data_reg[495]\(39) => mux_wrdata(491),
      \write_buffer.wr_buf_out_data_reg[495]\(38) => mux_wrdata(427),
      \write_buffer.wr_buf_out_data_reg[495]\(37) => mux_wrdata(363),
      \write_buffer.wr_buf_out_data_reg[495]\(36) => mux_wrdata(299),
      \write_buffer.wr_buf_out_data_reg[495]\(35) => mux_wrdata(235),
      \write_buffer.wr_buf_out_data_reg[495]\(34) => mux_wrdata(171),
      \write_buffer.wr_buf_out_data_reg[495]\(33) => mux_wrdata(107),
      \write_buffer.wr_buf_out_data_reg[495]\(32) => mux_wrdata(43),
      \write_buffer.wr_buf_out_data_reg[495]\(31) => mux_wrdata(490),
      \write_buffer.wr_buf_out_data_reg[495]\(30) => mux_wrdata(426),
      \write_buffer.wr_buf_out_data_reg[495]\(29) => mux_wrdata(362),
      \write_buffer.wr_buf_out_data_reg[495]\(28) => mux_wrdata(298),
      \write_buffer.wr_buf_out_data_reg[495]\(27) => mux_wrdata(234),
      \write_buffer.wr_buf_out_data_reg[495]\(26) => mux_wrdata(170),
      \write_buffer.wr_buf_out_data_reg[495]\(25) => mux_wrdata(106),
      \write_buffer.wr_buf_out_data_reg[495]\(24) => mux_wrdata(42),
      \write_buffer.wr_buf_out_data_reg[495]\(23) => mux_wrdata(489),
      \write_buffer.wr_buf_out_data_reg[495]\(22) => mux_wrdata(425),
      \write_buffer.wr_buf_out_data_reg[495]\(21) => mux_wrdata(361),
      \write_buffer.wr_buf_out_data_reg[495]\(20) => mux_wrdata(297),
      \write_buffer.wr_buf_out_data_reg[495]\(19) => mux_wrdata(233),
      \write_buffer.wr_buf_out_data_reg[495]\(18) => mux_wrdata(169),
      \write_buffer.wr_buf_out_data_reg[495]\(17) => mux_wrdata(105),
      \write_buffer.wr_buf_out_data_reg[495]\(16) => mux_wrdata(41),
      \write_buffer.wr_buf_out_data_reg[495]\(15) => mux_wrdata(488),
      \write_buffer.wr_buf_out_data_reg[495]\(14) => mux_wrdata(424),
      \write_buffer.wr_buf_out_data_reg[495]\(13) => mux_wrdata(360),
      \write_buffer.wr_buf_out_data_reg[495]\(12) => mux_wrdata(296),
      \write_buffer.wr_buf_out_data_reg[495]\(11) => mux_wrdata(232),
      \write_buffer.wr_buf_out_data_reg[495]\(10) => mux_wrdata(168),
      \write_buffer.wr_buf_out_data_reg[495]\(9) => mux_wrdata(104),
      \write_buffer.wr_buf_out_data_reg[495]\(8) => mux_wrdata(40),
      \write_buffer.wr_buf_out_data_reg[495]\(7) => mux_wrdata_mask(61),
      \write_buffer.wr_buf_out_data_reg[495]\(6) => mux_wrdata_mask(53),
      \write_buffer.wr_buf_out_data_reg[495]\(5) => mux_wrdata_mask(45),
      \write_buffer.wr_buf_out_data_reg[495]\(4) => mux_wrdata_mask(37),
      \write_buffer.wr_buf_out_data_reg[495]\(3) => mux_wrdata_mask(29),
      \write_buffer.wr_buf_out_data_reg[495]\(2) => mux_wrdata_mask(21),
      \write_buffer.wr_buf_out_data_reg[495]\(1) => mux_wrdata_mask(13),
      \write_buffer.wr_buf_out_data_reg[495]\(0) => mux_wrdata_mask(5),
      \write_buffer.wr_buf_out_data_reg[495]_0\(7 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d9\(7 downto 0),
      \write_buffer.wr_buf_out_data_reg[496]\(7 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d2\(7 downto 0),
      \write_buffer.wr_buf_out_data_reg[497]\(7 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d3\(7 downto 0),
      \write_buffer.wr_buf_out_data_reg[498]\(7 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d4\(7 downto 0),
      \write_buffer.wr_buf_out_data_reg[499]\(7 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d5\(7 downto 0),
      \write_buffer.wr_buf_out_data_reg[500]\(7 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d6\(7 downto 0),
      \write_buffer.wr_buf_out_data_reg[501]\(7 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d7\(7 downto 0),
      \write_buffer.wr_buf_out_data_reg[502]\(7 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d8\(7 downto 0),
      \write_buffer.wr_buf_out_data_reg[503]\(71) => mux_wrdata(503),
      \write_buffer.wr_buf_out_data_reg[503]\(70) => mux_wrdata(439),
      \write_buffer.wr_buf_out_data_reg[503]\(69) => mux_wrdata(375),
      \write_buffer.wr_buf_out_data_reg[503]\(68) => mux_wrdata(311),
      \write_buffer.wr_buf_out_data_reg[503]\(67) => mux_wrdata(247),
      \write_buffer.wr_buf_out_data_reg[503]\(66) => mux_wrdata(183),
      \write_buffer.wr_buf_out_data_reg[503]\(65) => mux_wrdata(119),
      \write_buffer.wr_buf_out_data_reg[503]\(64) => mux_wrdata(55),
      \write_buffer.wr_buf_out_data_reg[503]\(63) => mux_wrdata(502),
      \write_buffer.wr_buf_out_data_reg[503]\(62) => mux_wrdata(438),
      \write_buffer.wr_buf_out_data_reg[503]\(61) => mux_wrdata(374),
      \write_buffer.wr_buf_out_data_reg[503]\(60) => mux_wrdata(310),
      \write_buffer.wr_buf_out_data_reg[503]\(59) => mux_wrdata(246),
      \write_buffer.wr_buf_out_data_reg[503]\(58) => mux_wrdata(182),
      \write_buffer.wr_buf_out_data_reg[503]\(57) => mux_wrdata(118),
      \write_buffer.wr_buf_out_data_reg[503]\(56) => mux_wrdata(54),
      \write_buffer.wr_buf_out_data_reg[503]\(55) => mux_wrdata(501),
      \write_buffer.wr_buf_out_data_reg[503]\(54) => mux_wrdata(437),
      \write_buffer.wr_buf_out_data_reg[503]\(53) => mux_wrdata(373),
      \write_buffer.wr_buf_out_data_reg[503]\(52) => mux_wrdata(309),
      \write_buffer.wr_buf_out_data_reg[503]\(51) => mux_wrdata(245),
      \write_buffer.wr_buf_out_data_reg[503]\(50) => mux_wrdata(181),
      \write_buffer.wr_buf_out_data_reg[503]\(49) => mux_wrdata(117),
      \write_buffer.wr_buf_out_data_reg[503]\(48) => mux_wrdata(53),
      \write_buffer.wr_buf_out_data_reg[503]\(47) => mux_wrdata(500),
      \write_buffer.wr_buf_out_data_reg[503]\(46) => mux_wrdata(436),
      \write_buffer.wr_buf_out_data_reg[503]\(45) => mux_wrdata(372),
      \write_buffer.wr_buf_out_data_reg[503]\(44) => mux_wrdata(308),
      \write_buffer.wr_buf_out_data_reg[503]\(43) => mux_wrdata(244),
      \write_buffer.wr_buf_out_data_reg[503]\(42) => mux_wrdata(180),
      \write_buffer.wr_buf_out_data_reg[503]\(41) => mux_wrdata(116),
      \write_buffer.wr_buf_out_data_reg[503]\(40) => mux_wrdata(52),
      \write_buffer.wr_buf_out_data_reg[503]\(39) => mux_wrdata(499),
      \write_buffer.wr_buf_out_data_reg[503]\(38) => mux_wrdata(435),
      \write_buffer.wr_buf_out_data_reg[503]\(37) => mux_wrdata(371),
      \write_buffer.wr_buf_out_data_reg[503]\(36) => mux_wrdata(307),
      \write_buffer.wr_buf_out_data_reg[503]\(35) => mux_wrdata(243),
      \write_buffer.wr_buf_out_data_reg[503]\(34) => mux_wrdata(179),
      \write_buffer.wr_buf_out_data_reg[503]\(33) => mux_wrdata(115),
      \write_buffer.wr_buf_out_data_reg[503]\(32) => mux_wrdata(51),
      \write_buffer.wr_buf_out_data_reg[503]\(31) => mux_wrdata(498),
      \write_buffer.wr_buf_out_data_reg[503]\(30) => mux_wrdata(434),
      \write_buffer.wr_buf_out_data_reg[503]\(29) => mux_wrdata(370),
      \write_buffer.wr_buf_out_data_reg[503]\(28) => mux_wrdata(306),
      \write_buffer.wr_buf_out_data_reg[503]\(27) => mux_wrdata(242),
      \write_buffer.wr_buf_out_data_reg[503]\(26) => mux_wrdata(178),
      \write_buffer.wr_buf_out_data_reg[503]\(25) => mux_wrdata(114),
      \write_buffer.wr_buf_out_data_reg[503]\(24) => mux_wrdata(50),
      \write_buffer.wr_buf_out_data_reg[503]\(23) => mux_wrdata(497),
      \write_buffer.wr_buf_out_data_reg[503]\(22) => mux_wrdata(433),
      \write_buffer.wr_buf_out_data_reg[503]\(21) => mux_wrdata(369),
      \write_buffer.wr_buf_out_data_reg[503]\(20) => mux_wrdata(305),
      \write_buffer.wr_buf_out_data_reg[503]\(19) => mux_wrdata(241),
      \write_buffer.wr_buf_out_data_reg[503]\(18) => mux_wrdata(177),
      \write_buffer.wr_buf_out_data_reg[503]\(17) => mux_wrdata(113),
      \write_buffer.wr_buf_out_data_reg[503]\(16) => mux_wrdata(49),
      \write_buffer.wr_buf_out_data_reg[503]\(15) => mux_wrdata(496),
      \write_buffer.wr_buf_out_data_reg[503]\(14) => mux_wrdata(432),
      \write_buffer.wr_buf_out_data_reg[503]\(13) => mux_wrdata(368),
      \write_buffer.wr_buf_out_data_reg[503]\(12) => mux_wrdata(304),
      \write_buffer.wr_buf_out_data_reg[503]\(11) => mux_wrdata(240),
      \write_buffer.wr_buf_out_data_reg[503]\(10) => mux_wrdata(176),
      \write_buffer.wr_buf_out_data_reg[503]\(9) => mux_wrdata(112),
      \write_buffer.wr_buf_out_data_reg[503]\(8) => mux_wrdata(48),
      \write_buffer.wr_buf_out_data_reg[503]\(7) => mux_wrdata_mask(62),
      \write_buffer.wr_buf_out_data_reg[503]\(6) => mux_wrdata_mask(54),
      \write_buffer.wr_buf_out_data_reg[503]\(5) => mux_wrdata_mask(46),
      \write_buffer.wr_buf_out_data_reg[503]\(4) => mux_wrdata_mask(38),
      \write_buffer.wr_buf_out_data_reg[503]\(3) => mux_wrdata_mask(30),
      \write_buffer.wr_buf_out_data_reg[503]\(2) => mux_wrdata_mask(22),
      \write_buffer.wr_buf_out_data_reg[503]\(1) => mux_wrdata_mask(14),
      \write_buffer.wr_buf_out_data_reg[503]\(0) => mux_wrdata_mask(6),
      \write_buffer.wr_buf_out_data_reg[503]_0\(7 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d9\(7 downto 0),
      \write_buffer.wr_buf_out_data_reg[504]\(7 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d2\(7 downto 0),
      \write_buffer.wr_buf_out_data_reg[505]\(7 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d3\(7 downto 0),
      \write_buffer.wr_buf_out_data_reg[506]\(7 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d4\(7 downto 0),
      \write_buffer.wr_buf_out_data_reg[507]\(7 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d5\(7 downto 0),
      \write_buffer.wr_buf_out_data_reg[508]\(7 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d6\(7 downto 0),
      \write_buffer.wr_buf_out_data_reg[509]\(7 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d7\(7 downto 0),
      \write_buffer.wr_buf_out_data_reg[510]\(7 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d8\(7 downto 0),
      \write_buffer.wr_buf_out_data_reg[511]\(71) => mux_wrdata(511),
      \write_buffer.wr_buf_out_data_reg[511]\(70) => mux_wrdata(447),
      \write_buffer.wr_buf_out_data_reg[511]\(69) => mux_wrdata(383),
      \write_buffer.wr_buf_out_data_reg[511]\(68) => mux_wrdata(319),
      \write_buffer.wr_buf_out_data_reg[511]\(67) => mux_wrdata(255),
      \write_buffer.wr_buf_out_data_reg[511]\(66) => mux_wrdata(191),
      \write_buffer.wr_buf_out_data_reg[511]\(65) => mux_wrdata(127),
      \write_buffer.wr_buf_out_data_reg[511]\(64) => mux_wrdata(63),
      \write_buffer.wr_buf_out_data_reg[511]\(63) => mux_wrdata(510),
      \write_buffer.wr_buf_out_data_reg[511]\(62) => mux_wrdata(446),
      \write_buffer.wr_buf_out_data_reg[511]\(61) => mux_wrdata(382),
      \write_buffer.wr_buf_out_data_reg[511]\(60) => mux_wrdata(318),
      \write_buffer.wr_buf_out_data_reg[511]\(59) => mux_wrdata(254),
      \write_buffer.wr_buf_out_data_reg[511]\(58) => mux_wrdata(190),
      \write_buffer.wr_buf_out_data_reg[511]\(57) => mux_wrdata(126),
      \write_buffer.wr_buf_out_data_reg[511]\(56) => mux_wrdata(62),
      \write_buffer.wr_buf_out_data_reg[511]\(55) => mux_wrdata(509),
      \write_buffer.wr_buf_out_data_reg[511]\(54) => mux_wrdata(445),
      \write_buffer.wr_buf_out_data_reg[511]\(53) => mux_wrdata(381),
      \write_buffer.wr_buf_out_data_reg[511]\(52) => mux_wrdata(317),
      \write_buffer.wr_buf_out_data_reg[511]\(51) => mux_wrdata(253),
      \write_buffer.wr_buf_out_data_reg[511]\(50) => mux_wrdata(189),
      \write_buffer.wr_buf_out_data_reg[511]\(49) => mux_wrdata(125),
      \write_buffer.wr_buf_out_data_reg[511]\(48) => mux_wrdata(61),
      \write_buffer.wr_buf_out_data_reg[511]\(47) => mux_wrdata(508),
      \write_buffer.wr_buf_out_data_reg[511]\(46) => mux_wrdata(444),
      \write_buffer.wr_buf_out_data_reg[511]\(45) => mux_wrdata(380),
      \write_buffer.wr_buf_out_data_reg[511]\(44) => mux_wrdata(316),
      \write_buffer.wr_buf_out_data_reg[511]\(43) => mux_wrdata(252),
      \write_buffer.wr_buf_out_data_reg[511]\(42) => mux_wrdata(188),
      \write_buffer.wr_buf_out_data_reg[511]\(41) => mux_wrdata(124),
      \write_buffer.wr_buf_out_data_reg[511]\(40) => mux_wrdata(60),
      \write_buffer.wr_buf_out_data_reg[511]\(39) => mux_wrdata(507),
      \write_buffer.wr_buf_out_data_reg[511]\(38) => mux_wrdata(443),
      \write_buffer.wr_buf_out_data_reg[511]\(37) => mux_wrdata(379),
      \write_buffer.wr_buf_out_data_reg[511]\(36) => mux_wrdata(315),
      \write_buffer.wr_buf_out_data_reg[511]\(35) => mux_wrdata(251),
      \write_buffer.wr_buf_out_data_reg[511]\(34) => mux_wrdata(187),
      \write_buffer.wr_buf_out_data_reg[511]\(33) => mux_wrdata(123),
      \write_buffer.wr_buf_out_data_reg[511]\(32) => mux_wrdata(59),
      \write_buffer.wr_buf_out_data_reg[511]\(31) => mux_wrdata(506),
      \write_buffer.wr_buf_out_data_reg[511]\(30) => mux_wrdata(442),
      \write_buffer.wr_buf_out_data_reg[511]\(29) => mux_wrdata(378),
      \write_buffer.wr_buf_out_data_reg[511]\(28) => mux_wrdata(314),
      \write_buffer.wr_buf_out_data_reg[511]\(27) => mux_wrdata(250),
      \write_buffer.wr_buf_out_data_reg[511]\(26) => mux_wrdata(186),
      \write_buffer.wr_buf_out_data_reg[511]\(25) => mux_wrdata(122),
      \write_buffer.wr_buf_out_data_reg[511]\(24) => mux_wrdata(58),
      \write_buffer.wr_buf_out_data_reg[511]\(23) => mux_wrdata(505),
      \write_buffer.wr_buf_out_data_reg[511]\(22) => mux_wrdata(441),
      \write_buffer.wr_buf_out_data_reg[511]\(21) => mux_wrdata(377),
      \write_buffer.wr_buf_out_data_reg[511]\(20) => mux_wrdata(313),
      \write_buffer.wr_buf_out_data_reg[511]\(19) => mux_wrdata(249),
      \write_buffer.wr_buf_out_data_reg[511]\(18) => mux_wrdata(185),
      \write_buffer.wr_buf_out_data_reg[511]\(17) => mux_wrdata(121),
      \write_buffer.wr_buf_out_data_reg[511]\(16) => mux_wrdata(57),
      \write_buffer.wr_buf_out_data_reg[511]\(15) => mux_wrdata(504),
      \write_buffer.wr_buf_out_data_reg[511]\(14) => mux_wrdata(440),
      \write_buffer.wr_buf_out_data_reg[511]\(13) => mux_wrdata(376),
      \write_buffer.wr_buf_out_data_reg[511]\(12) => mux_wrdata(312),
      \write_buffer.wr_buf_out_data_reg[511]\(11) => mux_wrdata(248),
      \write_buffer.wr_buf_out_data_reg[511]\(10) => mux_wrdata(184),
      \write_buffer.wr_buf_out_data_reg[511]\(9) => mux_wrdata(120),
      \write_buffer.wr_buf_out_data_reg[511]\(8) => mux_wrdata(56),
      \write_buffer.wr_buf_out_data_reg[511]\(7) => mux_wrdata_mask(63),
      \write_buffer.wr_buf_out_data_reg[511]\(6) => mux_wrdata_mask(55),
      \write_buffer.wr_buf_out_data_reg[511]\(5) => mux_wrdata_mask(47),
      \write_buffer.wr_buf_out_data_reg[511]\(4) => mux_wrdata_mask(39),
      \write_buffer.wr_buf_out_data_reg[511]\(3) => mux_wrdata_mask(31),
      \write_buffer.wr_buf_out_data_reg[511]\(2) => mux_wrdata_mask(23),
      \write_buffer.wr_buf_out_data_reg[511]\(1) => mux_wrdata_mask(15),
      \write_buffer.wr_buf_out_data_reg[511]\(0) => mux_wrdata_mask(7),
      \write_buffer.wr_buf_out_data_reg[511]_0\(7 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d9\(7 downto 0)
    );
u_ddr_mc_phy_wrapper: entity work.mig_mig_7series_v4_2_ddr_mc_phy_wrapper
     port map (
      A_rst_primitives_reg => A_rst_primitives_reg,
      A_rst_primitives_reg_0 => A_rst_primitives_reg_0,
      A_rst_primitives_reg_1 => A_rst_primitives_reg_1,
      A_rst_primitives_reg_2 => A_rst_primitives_reg_2,
      A_rst_primitives_reg_3 => A_rst_primitives_reg_3,
      A_rst_primitives_reg_4 => A_rst_primitives_reg_4,
      A_rst_primitives_reg_5 => A_rst_primitives_reg_5,
      A_rst_primitives_reg_6 => A_rst_primitives_reg_6,
      A_rst_primitives_reg_7 => u_ddr_mc_phy_wrapper_n_64,
      CLKB0 => CLKB0,
      CLKB0_10 => CLKB0_10,
      CLKB0_11 => CLKB0_11,
      CLKB0_12 => CLKB0_12,
      CLKB0_13 => CLKB0_13,
      CLKB0_7 => CLKB0_7,
      CLKB0_8 => CLKB0_8,
      CLKB0_9 => CLKB0_9,
      COUNTERLOADVAL(5 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/A_pi_counter_load_val\(5 downto 0),
      C_po_coarse_enable26_out => \u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/C_po_coarse_enable26_out\,
      C_po_counter_read_en38_out => \u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/C_po_counter_read_en38_out\,
      C_po_fine_enable23_out => \u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/C_po_fine_enable23_out\,
      C_po_fine_inc29_out => \u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/C_po_fine_inc29_out\,
      D(10 downto 3) => phy_ctl_wd(24 downto 17),
      D(2 downto 0) => phy_ctl_wd(2 downto 0),
      D1(3 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d1\(3 downto 0),
      D2(7 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d2\(7 downto 0),
      D3(3 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d3\(3 downto 0),
      D4(3 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d4\(3 downto 0),
      D5(3 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d5\(7 downto 4),
      D6(7 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d6\(7 downto 0),
      D7(3 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d7\(3 downto 0),
      D8(3 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d8\(3 downto 0),
      D9(3 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d9\(3 downto 0),
      LD0 => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/LD0\,
      LD0_10 => \u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/LD0\,
      LD0_11 => \u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/ddr_byte_group_io/LD0\,
      LD0_12 => \u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/LD0\,
      LD0_13 => \u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/LD0\,
      LD0_7 => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/ddr_byte_group_io/LD0\,
      LD0_8 => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/LD0\,
      LD0_9 => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/LD0\,
      Q(63 downto 0) => Q(575 downto 512),
      RST0 => RST0,
      SR(0) => SR(0),
      calib_sel(3 downto 2) => calib_sel(4 downto 3),
      calib_sel(1 downto 0) => calib_sel(1 downto 0),
      d_in(4) => \^init_calib_complete\,
      d_in(3 downto 0) => d_in(3 downto 0),
      \data_offset_1_i1_reg[5]_0\(5 downto 0) => data_offset_1(5 downto 0),
      \data_offset_2_i1_reg[5]_0\(5 downto 0) => data_offset_2(5 downto 0),
      ddr3_addr(13 downto 0) => ddr3_addr(13 downto 0),
      ddr3_ba(2 downto 0) => ddr3_ba(2 downto 0),
      ddr3_cas_n => ddr3_cas_n,
      ddr3_cke(0) => ddr3_cke(0),
      ddr3_cs_n(0) => ddr3_cs_n(0),
      ddr3_dm(7 downto 0) => ddr3_dm(7 downto 0),
      ddr3_dq(63 downto 0) => ddr3_dq(63 downto 0),
      ddr3_dqs_n(7 downto 0) => ddr3_dqs_n(7 downto 0),
      ddr3_dqs_p(7 downto 0) => ddr3_dqs_p(7 downto 0),
      ddr3_odt(0) => ddr3_odt(0),
      ddr3_ras_n => ddr3_ras_n,
      ddr3_reset_n => ddr3_reset_n,
      ddr3_we_n => ddr3_we_n,
      ddr_ck_out(1 downto 0) => ddr_ck_out(1 downto 0),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_1\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_2\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_3\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_4\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_5\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_5\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_6\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_6\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_2\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_3\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_4\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_5\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_5\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_6\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_6\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_2\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_3\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_4\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_5\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_5\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_6\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_6\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_2\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_3\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_4\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_5\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_5\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_6\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_6\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_2\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_3\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_4\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_5\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_5\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_6\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_6\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_2\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_3\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_4\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_5\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_5\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_6\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_6\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_2\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_3\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_4\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_5\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_5\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_6\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_6\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_2\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_3\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_4\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_5\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_5\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_6\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_6\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_1\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_2\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_3\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_4\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_5\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_5\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_6\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_6\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_2\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_3\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_4\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_5\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_5\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_6\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_6\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_2\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_3\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_4\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_5\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_5\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_6\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_6\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_2\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_3\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_4\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_5\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_5\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_6\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_6\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_2\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_3\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_4\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_5\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_5\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_6\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_6\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_2\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_3\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_4\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_5\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_5\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_6\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_6\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_2\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_3\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_4\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_5\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_5\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_6\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_6\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_2\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_3\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_4\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_5\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_5\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_6\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_6\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_1\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_2\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_3\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_4\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_5\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_5\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_6\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_6\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_2\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_3\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_4\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_5\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_5\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_6\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_6\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_2\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_3\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_4\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_5\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_5\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_6\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_6\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_2\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_3\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_4\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_5\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_5\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_6\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_6\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_2\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_3\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_4\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_5\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_5\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_6\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_6\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_2\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_3\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_4\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_5\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_5\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_6\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_6\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_2\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_3\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_4\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_5\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_5\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_6\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_6\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_2\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_3\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_4\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_5\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_5\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_6\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_6\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_1\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_2\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_3\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_4\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_5\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_5\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_6\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_6\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_2\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_3\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_4\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_5\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_5\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_6\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_6\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_2\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_3\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_4\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_5\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_5\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_6\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_6\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_2\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_3\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_4\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_5\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_5\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_6\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_6\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_2\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_3\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_4\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_5\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_5\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_6\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_6\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_2\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_3\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_4\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_5\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_5\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_6\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_6\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_2\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_3\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_4\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_5\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_5\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_6\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_6\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_2\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_3\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_4\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_5\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_5\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_6\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_6\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_1\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_2\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_3\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_4\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_5\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_5\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_6\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_6\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_2\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_3\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_4\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_5\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_5\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_6\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_6\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_2\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_3\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_4\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_5\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_5\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_6\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_6\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_2\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_3\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_4\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_5\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_5\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_6\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_6\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_2\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_3\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_4\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_5\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_5\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_6\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_6\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_2\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_3\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_4\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_5\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_5\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_6\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_6\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_2\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_3\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_4\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_5\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_5\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_6\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_6\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_2\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_3\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_4\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_5\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_5\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_6\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_6\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_1\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_2\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_3\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_4\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_5\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_5\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_6\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_6\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_2\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_3\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_4\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_5\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_5\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_6\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_6\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_2\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_3\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_4\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_5\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_5\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_6\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_6\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_2\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_3\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_4\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_5\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_5\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_6\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_6\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_2\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_3\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_4\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_5\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_5\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_6\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_6\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_2\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_3\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_4\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_5\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_5\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_6\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_6\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_2\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_3\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_4\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_5\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_5\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_6\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_6\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_2\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_3\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_4\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_5\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_5\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_6\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_6\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_1\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_2\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_3\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_4\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_2\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_3\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_4\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_2\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_3\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_4\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_2\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_3\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_4\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_2\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_3\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_4\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_2\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_3\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_4\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_2\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_3\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_4\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_2\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_3\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_4\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_1\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_2\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_3\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_4\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_5\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_5\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_6\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_6\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_2\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_3\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_4\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_5\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_5\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_6\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_6\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_2\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_3\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_4\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_5\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_5\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_6\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_6\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_2\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_3\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_4\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_5\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_5\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_6\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_6\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_2\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_3\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_4\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_5\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_5\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_6\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_6\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_2\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_3\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_4\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_5\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_5\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_6\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_6\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_2\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_3\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_4\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_5\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_5\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_6\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_6\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_2\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_3\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_4\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_5\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_5\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_6\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_6\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_0\ => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_0\,
      \entry_cnt_reg[4]\ => \entry_cnt_reg[4]\,
      freq_refclk => freq_refclk,
      \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]\(2 downto 0) => \ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl/rd_mux_sel_r\(2 downto 0),
      \gen_mux_rd[0].mux_rd_rise0_r_reg[0]\(1) => u_ddr_calib_top_n_65,
      \gen_mux_rd[0].mux_rd_rise0_r_reg[0]\(0) => u_ddr_calib_top_n_66,
      \gen_mux_rd[1].mux_rd_rise0_r_reg[1]\ => u_ddr_calib_top_n_64,
      \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]\(2 downto 0) => po_stg2_wrcal_cnt(2 downto 0),
      idelay_inc => idelay_inc,
      idelay_ld_rst => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/idelay_ld_rst\,
      idelay_ld_rst_0 => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/ddr_byte_group_io/idelay_ld_rst\,
      idelay_ld_rst_1 => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/idelay_ld_rst\,
      idelay_ld_rst_2 => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/idelay_ld_rst\,
      idelay_ld_rst_3 => \u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/idelay_ld_rst\,
      idelay_ld_rst_4 => \u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/ddr_byte_group_io/idelay_ld_rst\,
      idelay_ld_rst_5 => \u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/idelay_ld_rst\,
      idelay_ld_rst_6 => \u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/idelay_ld_rst\,
      idle => idle,
      if_empty => if_empty,
      ififo_rst_reg => u_ddr_calib_top_n_685,
      ififo_rst_reg_0 => u_ddr_calib_top_n_696,
      ififo_rst_reg_1 => u_ddr_calib_top_n_702,
      ififo_rst_reg_2 => u_ddr_calib_top_n_708,
      ififo_rst_reg_3 => u_ddr_calib_top_n_717,
      ififo_rst_reg_4 => u_ddr_calib_top_n_728,
      ififo_rst_reg_5 => u_ddr_calib_top_n_734,
      ififo_rst_reg_6 => u_ddr_calib_top_n_740,
      in0(7) => u_ddr_mc_phy_wrapper_n_33,
      in0(6) => u_ddr_mc_phy_wrapper_n_34,
      in0(5) => u_ddr_mc_phy_wrapper_n_35,
      in0(4) => u_ddr_mc_phy_wrapper_n_36,
      in0(3) => u_ddr_mc_phy_wrapper_n_37,
      in0(2) => u_ddr_mc_phy_wrapper_n_38,
      in0(1) => u_ddr_mc_phy_wrapper_n_39,
      in0(0) => u_ddr_mc_phy_wrapper_n_40,
      \input_[9].iserdes_dq_.iserdesdq\ => u_ddr_calib_top_n_683,
      \input_[9].iserdes_dq_.iserdesdq_0\ => u_ddr_calib_top_n_694,
      \input_[9].iserdes_dq_.iserdesdq_1\ => u_ddr_calib_top_n_700,
      \input_[9].iserdes_dq_.iserdesdq_2\ => u_ddr_calib_top_n_706,
      \input_[9].iserdes_dq_.iserdesdq_3\ => u_ddr_calib_top_n_715,
      \input_[9].iserdes_dq_.iserdesdq_4\ => u_ddr_calib_top_n_726,
      \input_[9].iserdes_dq_.iserdesdq_5\ => u_ddr_calib_top_n_732,
      \input_[9].iserdes_dq_.iserdesdq_6\ => u_ddr_calib_top_n_738,
      iodelay_ctrl_rdy(0) => iodelay_ctrl_rdy(0),
      \mcGo_r_reg[15]\(0) => phy_mc_go,
      mc_address(3) => mc_address(38),
      mc_address(2) => mc_address(36),
      mc_address(1) => mc_address(13),
      mc_address(0) => mc_address(11),
      mc_cas_n(2 downto 0) => mc_cas_n(2 downto 0),
      mc_cs_n(0) => mc_cs_n(0),
      mc_ras_n(1) => mc_ras_n(2),
      mc_ras_n(0) => mc_ras_n(0),
      mc_we_n(1) => mc_we_n(2),
      mc_we_n(0) => mc_we_n(0),
      mem_out(11 downto 8) => \u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/mem_out\(59 downto 56),
      mem_out(7) => \u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/mem_out\(53),
      mem_out(6) => \u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/mem_out\(45),
      mem_out(5) => \u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/mem_out\(41),
      mem_out(4) => \u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/mem_out\(33),
      mem_out(3 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/mem_out\(19 downto 16),
      mem_refclk => mem_refclk,
      mmcm_ps_clk => mmcm_ps_clk,
      mux_address(48) => mux_address(54),
      mux_address(47 downto 37) => mux_address(52 downto 42),
      mux_address(36) => mux_address(40),
      mux_address(35 downto 23) => mux_address(38 downto 26),
      mux_address(22 downto 12) => mux_address(24 downto 14),
      mux_address(11) => mux_address(12),
      mux_address(10 downto 0) => mux_address(10 downto 0),
      mux_reset_n => mux_reset_n,
      \my_empty_reg[1]\ => u_ddr_mc_phy_wrapper_n_59,
      \my_empty_reg[1]_0\ => u_ddr_mc_phy_wrapper_n_61,
      \my_empty_reg[1]_1\ => u_ddr_mc_phy_wrapper_n_62,
      \my_empty_reg[1]_2\ => u_ddr_mc_phy_wrapper_n_63,
      \my_empty_reg[1]_3\ => u_ddr_mc_phy_wrapper_n_65,
      \my_empty_reg[1]_4\ => u_ddr_mc_phy_wrapper_n_66,
      \my_empty_reg[1]_5\ => u_ddr_mc_phy_wrapper_n_67,
      \my_empty_reg[1]_6\ => u_ddr_mc_phy_wrapper_n_68,
      \my_empty_reg[1]_7\ => u_ddr_mc_phy_wrapper_n_69,
      \my_empty_reg[1]_8\ => u_ddr_mc_phy_wrapper_n_70,
      \my_empty_reg[1]_9\ => u_ddr_mc_phy_wrapper_n_1360,
      \my_empty_reg[7]\(7 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d1\(7 downto 0),
      \my_empty_reg[7]_0\(7 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d2\(7 downto 0),
      \my_empty_reg[7]_1\(7 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d3\(7 downto 0),
      \my_empty_reg[7]_10\(7 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d5\(7 downto 0),
      \my_empty_reg[7]_11\(7 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d6\(7 downto 0),
      \my_empty_reg[7]_12\(7 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d7\(7 downto 0),
      \my_empty_reg[7]_13\(7 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d8\(7 downto 0),
      \my_empty_reg[7]_14\(7 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d9\(7 downto 0),
      \my_empty_reg[7]_15\(7 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d2\(7 downto 0),
      \my_empty_reg[7]_16\(7 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d3\(7 downto 0),
      \my_empty_reg[7]_17\(7 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d4\(7 downto 0),
      \my_empty_reg[7]_18\(7 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d5\(7 downto 0),
      \my_empty_reg[7]_19\(7 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d6\(7 downto 0),
      \my_empty_reg[7]_2\(7 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d4\(7 downto 0),
      \my_empty_reg[7]_20\(7 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d7\(7 downto 0),
      \my_empty_reg[7]_21\(7 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d8\(7 downto 0),
      \my_empty_reg[7]_22\(7 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d9\(7 downto 0),
      \my_empty_reg[7]_23\(7 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d2\(7 downto 0),
      \my_empty_reg[7]_24\(7 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d3\(7 downto 0),
      \my_empty_reg[7]_25\(7 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d4\(7 downto 0),
      \my_empty_reg[7]_26\(7 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d5\(7 downto 0),
      \my_empty_reg[7]_27\(7 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d6\(7 downto 0),
      \my_empty_reg[7]_28\(7 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d7\(7 downto 0),
      \my_empty_reg[7]_29\(7 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d8\(7 downto 0),
      \my_empty_reg[7]_3\(7 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d5\(7 downto 0),
      \my_empty_reg[7]_30\(7 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d9\(7 downto 0),
      \my_empty_reg[7]_31\(7 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d1\(7 downto 0),
      \my_empty_reg[7]_32\(7 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d3\(7 downto 0),
      \my_empty_reg[7]_33\(7 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d4\(7 downto 0),
      \my_empty_reg[7]_34\(7 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d5\(7 downto 0),
      \my_empty_reg[7]_35\(7 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d6\(7 downto 0),
      \my_empty_reg[7]_36\(7 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d7\(7 downto 0),
      \my_empty_reg[7]_37\(7 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d9\(7 downto 0),
      \my_empty_reg[7]_38\(7 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d2\(7 downto 0),
      \my_empty_reg[7]_39\(7 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d3\(7 downto 0),
      \my_empty_reg[7]_4\(7 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d6\(7 downto 0),
      \my_empty_reg[7]_40\(7 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d4\(7 downto 0),
      \my_empty_reg[7]_41\(7 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d5\(7 downto 0),
      \my_empty_reg[7]_42\(7 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d6\(7 downto 0),
      \my_empty_reg[7]_43\(7 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d7\(7 downto 0),
      \my_empty_reg[7]_44\(7 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d8\(7 downto 0),
      \my_empty_reg[7]_45\(7 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d9\(7 downto 0),
      \my_empty_reg[7]_46\(7 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d2\(7 downto 0),
      \my_empty_reg[7]_47\(7 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d3\(7 downto 0),
      \my_empty_reg[7]_48\(7 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d4\(7 downto 0),
      \my_empty_reg[7]_49\(7 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d5\(7 downto 0),
      \my_empty_reg[7]_5\(7 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d7\(7 downto 0),
      \my_empty_reg[7]_50\(7 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d6\(7 downto 0),
      \my_empty_reg[7]_51\(7 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d7\(7 downto 0),
      \my_empty_reg[7]_52\(7 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d8\(7 downto 0),
      \my_empty_reg[7]_53\(7 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d9\(7 downto 0),
      \my_empty_reg[7]_54\(7 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d2\(7 downto 0),
      \my_empty_reg[7]_55\(7 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d3\(7 downto 0),
      \my_empty_reg[7]_56\(7 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d4\(7 downto 0),
      \my_empty_reg[7]_57\(7 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d5\(7 downto 0),
      \my_empty_reg[7]_58\(7 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d6\(7 downto 0),
      \my_empty_reg[7]_59\(7 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d7\(7 downto 0),
      \my_empty_reg[7]_6\(7 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d9\(7 downto 0),
      \my_empty_reg[7]_60\(7 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d8\(7 downto 0),
      \my_empty_reg[7]_61\(7 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d9\(7 downto 0),
      \my_empty_reg[7]_62\(3 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d4\(3 downto 0),
      \my_empty_reg[7]_63\(7 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d5\(7 downto 0),
      \my_empty_reg[7]_64\(3 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d6\(7 downto 4),
      \my_empty_reg[7]_65\(3 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d8\(3 downto 0),
      \my_empty_reg[7]_7\(7 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d2\(7 downto 0),
      \my_empty_reg[7]_8\(7 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d3\(7 downto 0),
      \my_empty_reg[7]_9\(7 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d4\(7 downto 0),
      \my_full_reg[3]\(3 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d2\(3 downto 0),
      \my_full_reg[3]_0\(0) => \u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d4\(1),
      \my_full_reg[3]_1\(1) => \u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d5\(5),
      \my_full_reg[3]_1\(0) => \u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d5\(1),
      \my_full_reg[3]_2\(0) => \u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d6\(5),
      \my_full_reg[3]_3\(3 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d7\(3 downto 0),
      of_ctl_full_v(0) => of_ctl_full_v(0),
      \out\ => \out\,
      out_fifo => u_ddr_calib_top_n_54,
      out_fifo_0 => u_ddr_calib_top_n_53,
      out_fifo_1 => u_ddr_calib_top_n_52,
      out_fifo_2 => \^init_calib_complete_reg_rep__26\,
      out_fifo_i_39(11) => mux_bank(9),
      out_fifo_i_39(10) => mux_bank(6),
      out_fifo_i_39(9) => mux_bank(3),
      out_fifo_i_39(8) => mux_bank(0),
      out_fifo_i_39(7) => mux_bank(10),
      out_fifo_i_39(6) => mux_bank(7),
      out_fifo_i_39(5) => mux_bank(4),
      out_fifo_i_39(4) => mux_bank(1),
      out_fifo_i_39(3) => mux_bank(11),
      out_fifo_i_39(2) => mux_bank(8),
      out_fifo_i_39(1) => mux_bank(5),
      out_fifo_i_39(0) => mux_bank(2),
      \out_fifo_i_47__8\(12) => mux_cke(3),
      \out_fifo_i_47__8\(11) => phy_dout(6),
      \out_fifo_i_47__8\(10) => mux_we_n(1),
      \out_fifo_i_47__8\(9 downto 8) => phy_dout(5 downto 4),
      \out_fifo_i_47__8\(7) => mux_ras_n(1),
      \out_fifo_i_47__8\(6 downto 5) => phy_dout(3 downto 2),
      \out_fifo_i_47__8\(4) => mux_cas_n(1),
      \out_fifo_i_47__8\(3) => phy_dout(1),
      \out_fifo_i_47__8\(2) => mux_cs_n(1),
      \out_fifo_i_47__8\(1) => phy_dout(0),
      \out_fifo_i_47__8\(0) => mux_odt(0),
      \out_fifo_i_75__0\(71) => mux_wrdata(455),
      \out_fifo_i_75__0\(70) => mux_wrdata(391),
      \out_fifo_i_75__0\(69) => mux_wrdata(327),
      \out_fifo_i_75__0\(68) => mux_wrdata(263),
      \out_fifo_i_75__0\(67) => mux_wrdata(199),
      \out_fifo_i_75__0\(66) => mux_wrdata(135),
      \out_fifo_i_75__0\(65) => mux_wrdata(71),
      \out_fifo_i_75__0\(64) => mux_wrdata(7),
      \out_fifo_i_75__0\(63) => mux_wrdata(454),
      \out_fifo_i_75__0\(62) => mux_wrdata(390),
      \out_fifo_i_75__0\(61) => mux_wrdata(326),
      \out_fifo_i_75__0\(60) => mux_wrdata(262),
      \out_fifo_i_75__0\(59) => mux_wrdata(198),
      \out_fifo_i_75__0\(58) => mux_wrdata(134),
      \out_fifo_i_75__0\(57) => mux_wrdata(70),
      \out_fifo_i_75__0\(56) => mux_wrdata(6),
      \out_fifo_i_75__0\(55) => mux_wrdata(453),
      \out_fifo_i_75__0\(54) => mux_wrdata(389),
      \out_fifo_i_75__0\(53) => mux_wrdata(325),
      \out_fifo_i_75__0\(52) => mux_wrdata(261),
      \out_fifo_i_75__0\(51) => mux_wrdata(197),
      \out_fifo_i_75__0\(50) => mux_wrdata(133),
      \out_fifo_i_75__0\(49) => mux_wrdata(69),
      \out_fifo_i_75__0\(48) => mux_wrdata(5),
      \out_fifo_i_75__0\(47) => mux_wrdata(452),
      \out_fifo_i_75__0\(46) => mux_wrdata(388),
      \out_fifo_i_75__0\(45) => mux_wrdata(324),
      \out_fifo_i_75__0\(44) => mux_wrdata(260),
      \out_fifo_i_75__0\(43) => mux_wrdata(196),
      \out_fifo_i_75__0\(42) => mux_wrdata(132),
      \out_fifo_i_75__0\(41) => mux_wrdata(68),
      \out_fifo_i_75__0\(40) => mux_wrdata(4),
      \out_fifo_i_75__0\(39) => mux_wrdata(451),
      \out_fifo_i_75__0\(38) => mux_wrdata(387),
      \out_fifo_i_75__0\(37) => mux_wrdata(323),
      \out_fifo_i_75__0\(36) => mux_wrdata(259),
      \out_fifo_i_75__0\(35) => mux_wrdata(195),
      \out_fifo_i_75__0\(34) => mux_wrdata(131),
      \out_fifo_i_75__0\(33) => mux_wrdata(67),
      \out_fifo_i_75__0\(32) => mux_wrdata(3),
      \out_fifo_i_75__0\(31) => mux_wrdata(450),
      \out_fifo_i_75__0\(30) => mux_wrdata(386),
      \out_fifo_i_75__0\(29) => mux_wrdata(322),
      \out_fifo_i_75__0\(28) => mux_wrdata(258),
      \out_fifo_i_75__0\(27) => mux_wrdata(194),
      \out_fifo_i_75__0\(26) => mux_wrdata(130),
      \out_fifo_i_75__0\(25) => mux_wrdata(66),
      \out_fifo_i_75__0\(24) => mux_wrdata(2),
      \out_fifo_i_75__0\(23) => mux_wrdata(449),
      \out_fifo_i_75__0\(22) => mux_wrdata(385),
      \out_fifo_i_75__0\(21) => mux_wrdata(321),
      \out_fifo_i_75__0\(20) => mux_wrdata(257),
      \out_fifo_i_75__0\(19) => mux_wrdata(193),
      \out_fifo_i_75__0\(18) => mux_wrdata(129),
      \out_fifo_i_75__0\(17) => mux_wrdata(65),
      \out_fifo_i_75__0\(16) => mux_wrdata(1),
      \out_fifo_i_75__0\(15) => mux_wrdata(448),
      \out_fifo_i_75__0\(14) => mux_wrdata(384),
      \out_fifo_i_75__0\(13) => mux_wrdata(320),
      \out_fifo_i_75__0\(12) => mux_wrdata(256),
      \out_fifo_i_75__0\(11) => mux_wrdata(192),
      \out_fifo_i_75__0\(10) => mux_wrdata(128),
      \out_fifo_i_75__0\(9) => mux_wrdata(64),
      \out_fifo_i_75__0\(8) => mux_wrdata(0),
      \out_fifo_i_75__0\(7) => mux_wrdata_mask(56),
      \out_fifo_i_75__0\(6) => mux_wrdata_mask(48),
      \out_fifo_i_75__0\(5) => mux_wrdata_mask(40),
      \out_fifo_i_75__0\(4) => mux_wrdata_mask(32),
      \out_fifo_i_75__0\(3) => mux_wrdata_mask(24),
      \out_fifo_i_75__0\(2) => mux_wrdata_mask(16),
      \out_fifo_i_75__0\(1) => mux_wrdata_mask(8),
      \out_fifo_i_75__0\(0) => mux_wrdata_mask(0),
      \out_fifo_i_75__1\(71) => mux_wrdata(463),
      \out_fifo_i_75__1\(70) => mux_wrdata(399),
      \out_fifo_i_75__1\(69) => mux_wrdata(335),
      \out_fifo_i_75__1\(68) => mux_wrdata(271),
      \out_fifo_i_75__1\(67) => mux_wrdata(207),
      \out_fifo_i_75__1\(66) => mux_wrdata(143),
      \out_fifo_i_75__1\(65) => mux_wrdata(79),
      \out_fifo_i_75__1\(64) => mux_wrdata(15),
      \out_fifo_i_75__1\(63) => mux_wrdata(462),
      \out_fifo_i_75__1\(62) => mux_wrdata(398),
      \out_fifo_i_75__1\(61) => mux_wrdata(334),
      \out_fifo_i_75__1\(60) => mux_wrdata(270),
      \out_fifo_i_75__1\(59) => mux_wrdata(206),
      \out_fifo_i_75__1\(58) => mux_wrdata(142),
      \out_fifo_i_75__1\(57) => mux_wrdata(78),
      \out_fifo_i_75__1\(56) => mux_wrdata(14),
      \out_fifo_i_75__1\(55) => mux_wrdata(461),
      \out_fifo_i_75__1\(54) => mux_wrdata(397),
      \out_fifo_i_75__1\(53) => mux_wrdata(333),
      \out_fifo_i_75__1\(52) => mux_wrdata(269),
      \out_fifo_i_75__1\(51) => mux_wrdata(205),
      \out_fifo_i_75__1\(50) => mux_wrdata(141),
      \out_fifo_i_75__1\(49) => mux_wrdata(77),
      \out_fifo_i_75__1\(48) => mux_wrdata(13),
      \out_fifo_i_75__1\(47) => mux_wrdata(460),
      \out_fifo_i_75__1\(46) => mux_wrdata(396),
      \out_fifo_i_75__1\(45) => mux_wrdata(332),
      \out_fifo_i_75__1\(44) => mux_wrdata(268),
      \out_fifo_i_75__1\(43) => mux_wrdata(204),
      \out_fifo_i_75__1\(42) => mux_wrdata(140),
      \out_fifo_i_75__1\(41) => mux_wrdata(76),
      \out_fifo_i_75__1\(40) => mux_wrdata(12),
      \out_fifo_i_75__1\(39) => mux_wrdata(459),
      \out_fifo_i_75__1\(38) => mux_wrdata(395),
      \out_fifo_i_75__1\(37) => mux_wrdata(331),
      \out_fifo_i_75__1\(36) => mux_wrdata(267),
      \out_fifo_i_75__1\(35) => mux_wrdata(203),
      \out_fifo_i_75__1\(34) => mux_wrdata(139),
      \out_fifo_i_75__1\(33) => mux_wrdata(75),
      \out_fifo_i_75__1\(32) => mux_wrdata(11),
      \out_fifo_i_75__1\(31) => mux_wrdata(458),
      \out_fifo_i_75__1\(30) => mux_wrdata(394),
      \out_fifo_i_75__1\(29) => mux_wrdata(330),
      \out_fifo_i_75__1\(28) => mux_wrdata(266),
      \out_fifo_i_75__1\(27) => mux_wrdata(202),
      \out_fifo_i_75__1\(26) => mux_wrdata(138),
      \out_fifo_i_75__1\(25) => mux_wrdata(74),
      \out_fifo_i_75__1\(24) => mux_wrdata(10),
      \out_fifo_i_75__1\(23) => mux_wrdata(457),
      \out_fifo_i_75__1\(22) => mux_wrdata(393),
      \out_fifo_i_75__1\(21) => mux_wrdata(329),
      \out_fifo_i_75__1\(20) => mux_wrdata(265),
      \out_fifo_i_75__1\(19) => mux_wrdata(201),
      \out_fifo_i_75__1\(18) => mux_wrdata(137),
      \out_fifo_i_75__1\(17) => mux_wrdata(73),
      \out_fifo_i_75__1\(16) => mux_wrdata(9),
      \out_fifo_i_75__1\(15) => mux_wrdata(456),
      \out_fifo_i_75__1\(14) => mux_wrdata(392),
      \out_fifo_i_75__1\(13) => mux_wrdata(328),
      \out_fifo_i_75__1\(12) => mux_wrdata(264),
      \out_fifo_i_75__1\(11) => mux_wrdata(200),
      \out_fifo_i_75__1\(10) => mux_wrdata(136),
      \out_fifo_i_75__1\(9) => mux_wrdata(72),
      \out_fifo_i_75__1\(8) => mux_wrdata(8),
      \out_fifo_i_75__1\(7) => mux_wrdata_mask(57),
      \out_fifo_i_75__1\(6) => mux_wrdata_mask(49),
      \out_fifo_i_75__1\(5) => mux_wrdata_mask(41),
      \out_fifo_i_75__1\(4) => mux_wrdata_mask(33),
      \out_fifo_i_75__1\(3) => mux_wrdata_mask(25),
      \out_fifo_i_75__1\(2) => mux_wrdata_mask(17),
      \out_fifo_i_75__1\(1) => mux_wrdata_mask(9),
      \out_fifo_i_75__1\(0) => mux_wrdata_mask(1),
      \out_fifo_i_75__2\(71) => mux_wrdata(471),
      \out_fifo_i_75__2\(70) => mux_wrdata(407),
      \out_fifo_i_75__2\(69) => mux_wrdata(343),
      \out_fifo_i_75__2\(68) => mux_wrdata(279),
      \out_fifo_i_75__2\(67) => mux_wrdata(215),
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      \out_fifo_i_75__7\(56) => mux_wrdata(62),
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      \out_fifo_i_75__7\(46) => mux_wrdata(444),
      \out_fifo_i_75__7\(45) => mux_wrdata(380),
      \out_fifo_i_75__7\(44) => mux_wrdata(316),
      \out_fifo_i_75__7\(43) => mux_wrdata(252),
      \out_fifo_i_75__7\(42) => mux_wrdata(188),
      \out_fifo_i_75__7\(41) => mux_wrdata(124),
      \out_fifo_i_75__7\(40) => mux_wrdata(60),
      \out_fifo_i_75__7\(39) => mux_wrdata(507),
      \out_fifo_i_75__7\(38) => mux_wrdata(443),
      \out_fifo_i_75__7\(37) => mux_wrdata(379),
      \out_fifo_i_75__7\(36) => mux_wrdata(315),
      \out_fifo_i_75__7\(35) => mux_wrdata(251),
      \out_fifo_i_75__7\(34) => mux_wrdata(187),
      \out_fifo_i_75__7\(33) => mux_wrdata(123),
      \out_fifo_i_75__7\(32) => mux_wrdata(59),
      \out_fifo_i_75__7\(31) => mux_wrdata(506),
      \out_fifo_i_75__7\(30) => mux_wrdata(442),
      \out_fifo_i_75__7\(29) => mux_wrdata(378),
      \out_fifo_i_75__7\(28) => mux_wrdata(314),
      \out_fifo_i_75__7\(27) => mux_wrdata(250),
      \out_fifo_i_75__7\(26) => mux_wrdata(186),
      \out_fifo_i_75__7\(25) => mux_wrdata(122),
      \out_fifo_i_75__7\(24) => mux_wrdata(58),
      \out_fifo_i_75__7\(23) => mux_wrdata(505),
      \out_fifo_i_75__7\(22) => mux_wrdata(441),
      \out_fifo_i_75__7\(21) => mux_wrdata(377),
      \out_fifo_i_75__7\(20) => mux_wrdata(313),
      \out_fifo_i_75__7\(19) => mux_wrdata(249),
      \out_fifo_i_75__7\(18) => mux_wrdata(185),
      \out_fifo_i_75__7\(17) => mux_wrdata(121),
      \out_fifo_i_75__7\(16) => mux_wrdata(57),
      \out_fifo_i_75__7\(15) => mux_wrdata(504),
      \out_fifo_i_75__7\(14) => mux_wrdata(440),
      \out_fifo_i_75__7\(13) => mux_wrdata(376),
      \out_fifo_i_75__7\(12) => mux_wrdata(312),
      \out_fifo_i_75__7\(11) => mux_wrdata(248),
      \out_fifo_i_75__7\(10) => mux_wrdata(184),
      \out_fifo_i_75__7\(9) => mux_wrdata(120),
      \out_fifo_i_75__7\(8) => mux_wrdata(56),
      \out_fifo_i_75__7\(7) => mux_wrdata_mask(63),
      \out_fifo_i_75__7\(6) => mux_wrdata_mask(55),
      \out_fifo_i_75__7\(5) => mux_wrdata_mask(47),
      \out_fifo_i_75__7\(4) => mux_wrdata_mask(39),
      \out_fifo_i_75__7\(3) => mux_wrdata_mask(31),
      \out_fifo_i_75__7\(2) => mux_wrdata_mask(23),
      \out_fifo_i_75__7\(1) => mux_wrdata_mask(15),
      \out_fifo_i_75__7\(0) => mux_wrdata_mask(7),
      p_0_out => \u_ddr_phy_wrcal/p_0_out\,
      phy_cmd_wr_en => phy_cmd_wr_en,
      phy_data_wr_en => phy_data_wr_en,
      phy_dout(71) => mux_wrdata(487),
      phy_dout(70) => mux_wrdata(423),
      phy_dout(69) => mux_wrdata(359),
      phy_dout(68) => mux_wrdata(295),
      phy_dout(67) => mux_wrdata(231),
      phy_dout(66) => mux_wrdata(167),
      phy_dout(65) => mux_wrdata(103),
      phy_dout(64) => mux_wrdata(39),
      phy_dout(63) => mux_wrdata(486),
      phy_dout(62) => mux_wrdata(422),
      phy_dout(61) => mux_wrdata(358),
      phy_dout(60) => mux_wrdata(294),
      phy_dout(59) => mux_wrdata(230),
      phy_dout(58) => mux_wrdata(166),
      phy_dout(57) => mux_wrdata(102),
      phy_dout(56) => mux_wrdata(38),
      phy_dout(55) => mux_wrdata(485),
      phy_dout(54) => mux_wrdata(421),
      phy_dout(53) => mux_wrdata(357),
      phy_dout(52) => mux_wrdata(293),
      phy_dout(51) => mux_wrdata(229),
      phy_dout(50) => mux_wrdata(165),
      phy_dout(49) => mux_wrdata(101),
      phy_dout(48) => mux_wrdata(37),
      phy_dout(47) => mux_wrdata(484),
      phy_dout(46) => mux_wrdata(420),
      phy_dout(45) => mux_wrdata(356),
      phy_dout(44) => mux_wrdata(292),
      phy_dout(43) => mux_wrdata(228),
      phy_dout(42) => mux_wrdata(164),
      phy_dout(41) => mux_wrdata(100),
      phy_dout(40) => mux_wrdata(36),
      phy_dout(39) => mux_wrdata(483),
      phy_dout(38) => mux_wrdata(419),
      phy_dout(37) => mux_wrdata(355),
      phy_dout(36) => mux_wrdata(291),
      phy_dout(35) => mux_wrdata(227),
      phy_dout(34) => mux_wrdata(163),
      phy_dout(33) => mux_wrdata(99),
      phy_dout(32) => mux_wrdata(35),
      phy_dout(31) => mux_wrdata(482),
      phy_dout(30) => mux_wrdata(418),
      phy_dout(29) => mux_wrdata(354),
      phy_dout(28) => mux_wrdata(290),
      phy_dout(27) => mux_wrdata(226),
      phy_dout(26) => mux_wrdata(162),
      phy_dout(25) => mux_wrdata(98),
      phy_dout(24) => mux_wrdata(34),
      phy_dout(23) => mux_wrdata(481),
      phy_dout(22) => mux_wrdata(417),
      phy_dout(21) => mux_wrdata(353),
      phy_dout(20) => mux_wrdata(289),
      phy_dout(19) => mux_wrdata(225),
      phy_dout(18) => mux_wrdata(161),
      phy_dout(17) => mux_wrdata(97),
      phy_dout(16) => mux_wrdata(33),
      phy_dout(15) => mux_wrdata(480),
      phy_dout(14) => mux_wrdata(416),
      phy_dout(13) => mux_wrdata(352),
      phy_dout(12) => mux_wrdata(288),
      phy_dout(11) => mux_wrdata(224),
      phy_dout(10) => mux_wrdata(160),
      phy_dout(9) => mux_wrdata(96),
      phy_dout(8) => mux_wrdata(32),
      phy_dout(7) => mux_wrdata_mask(60),
      phy_dout(6) => mux_wrdata_mask(52),
      phy_dout(5) => mux_wrdata_mask(44),
      phy_dout(4) => mux_wrdata_mask(36),
      phy_dout(3) => mux_wrdata_mask(28),
      phy_dout(2) => mux_wrdata_mask(20),
      phy_dout(1) => mux_wrdata_mask(12),
      phy_dout(0) => mux_wrdata_mask(4),
      phy_if_reset => phy_if_reset,
      phy_mc_ctl_full => phy_mc_ctl_full,
      phy_mc_ctl_full_r_reg => cal2_if_reset_reg,
      phy_mc_data_full => phy_mc_data_full,
      phy_rddata_en => phy_rddata_en,
      phy_read_calib => phy_read_calib,
      phy_write_calib => phy_write_calib,
      \pi_counter_read_val_reg[5]\(5 downto 0) => \u_ddr_mc_phy/pi_counter_read_val_w[0]_1\(5 downto 0),
      \pi_counter_read_val_reg[5]_0\(5 downto 0) => \u_ddr_mc_phy/pi_counter_read_val_w[2]_3\(5 downto 0),
      \pi_dqs_found_lanes_r1_reg[0]\ => u_ddr_calib_top_n_687,
      \pi_dqs_found_lanes_r1_reg[0]_0\ => u_ddr_calib_top_n_680,
      \pi_dqs_found_lanes_r1_reg[0]_1\ => u_ddr_calib_top_n_681,
      \pi_dqs_found_lanes_r1_reg[0]_2\ => u_ddr_calib_top_n_686,
      \pi_dqs_found_lanes_r1_reg[10]\ => u_ddr_calib_top_n_737,
      \pi_dqs_found_lanes_r1_reg[10]_0\ => u_ddr_calib_top_n_724,
      \pi_dqs_found_lanes_r1_reg[10]_1\ => u_ddr_calib_top_n_735,
      \pi_dqs_found_lanes_r1_reg[10]_2\ => u_ddr_calib_top_n_736,
      \pi_dqs_found_lanes_r1_reg[10]_3\(5 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/C_pi_counter_load_val\(5 downto 0),
      \pi_dqs_found_lanes_r1_reg[11]\ => u_ddr_calib_top_n_743,
      \pi_dqs_found_lanes_r1_reg[11]_0\ => u_ddr_calib_top_n_722,
      \pi_dqs_found_lanes_r1_reg[11]_1\ => u_ddr_calib_top_n_741,
      \pi_dqs_found_lanes_r1_reg[11]_2\ => u_ddr_calib_top_n_742,
      \pi_dqs_found_lanes_r1_reg[11]_3\(5 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/D_pi_counter_load_val\(5 downto 0),
      \pi_dqs_found_lanes_r1_reg[1]\ => u_ddr_calib_top_n_699,
      \pi_dqs_found_lanes_r1_reg[1]_0\ => u_ddr_calib_top_n_693,
      \pi_dqs_found_lanes_r1_reg[1]_1\ => u_ddr_calib_top_n_697,
      \pi_dqs_found_lanes_r1_reg[1]_2\ => u_ddr_calib_top_n_698,
      \pi_dqs_found_lanes_r1_reg[1]_3\(5 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/B_pi_counter_load_val\(5 downto 0),
      \pi_dqs_found_lanes_r1_reg[2]\ => u_ddr_calib_top_n_705,
      \pi_dqs_found_lanes_r1_reg[2]_0\ => u_ddr_calib_top_n_692,
      \pi_dqs_found_lanes_r1_reg[2]_1\ => u_ddr_calib_top_n_703,
      \pi_dqs_found_lanes_r1_reg[2]_2\ => u_ddr_calib_top_n_704,
      \pi_dqs_found_lanes_r1_reg[2]_3\(5 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/C_pi_counter_load_val\(5 downto 0),
      \pi_dqs_found_lanes_r1_reg[3]\ => u_ddr_calib_top_n_711,
      \pi_dqs_found_lanes_r1_reg[3]_0\ => u_ddr_calib_top_n_690,
      \pi_dqs_found_lanes_r1_reg[3]_1\ => u_ddr_calib_top_n_709,
      \pi_dqs_found_lanes_r1_reg[3]_2\ => u_ddr_calib_top_n_710,
      \pi_dqs_found_lanes_r1_reg[3]_3\(5 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/D_pi_counter_load_val\(5 downto 0),
      \pi_dqs_found_lanes_r1_reg[8]\ => u_ddr_calib_top_n_719,
      \pi_dqs_found_lanes_r1_reg[8]_0\ => u_ddr_calib_top_n_712,
      \pi_dqs_found_lanes_r1_reg[8]_1\ => u_ddr_calib_top_n_713,
      \pi_dqs_found_lanes_r1_reg[8]_2\ => u_ddr_calib_top_n_718,
      \pi_dqs_found_lanes_r1_reg[8]_3\(5 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/A_pi_counter_load_val\(5 downto 0),
      \pi_dqs_found_lanes_r1_reg[9]\ => u_ddr_calib_top_n_731,
      \pi_dqs_found_lanes_r1_reg[9]_0\ => u_ddr_calib_top_n_725,
      \pi_dqs_found_lanes_r1_reg[9]_1\ => u_ddr_calib_top_n_729,
      \pi_dqs_found_lanes_r1_reg[9]_2\ => u_ddr_calib_top_n_730,
      \pi_dqs_found_lanes_r1_reg[9]_3\(5 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/B_pi_counter_load_val\(5 downto 0),
      pll_locked => pll_locked,
      \po_counter_read_val_reg[0]\ => u_ddr_mc_phy_wrapper_n_1285,
      \po_counter_read_val_reg[0]_0\(0) => u_ddr_calib_top_n_1373,
      \po_counter_read_val_reg[1]\ => u_ddr_mc_phy_wrapper_n_1286,
      \po_counter_read_val_reg[2]\ => u_ddr_mc_phy_wrapper_n_1287,
      \po_counter_read_val_reg[3]\ => u_ddr_mc_phy_wrapper_n_1288,
      \po_counter_read_val_reg[4]\ => u_ddr_mc_phy_wrapper_n_1289,
      \po_counter_read_val_reg[5]\ => u_ddr_mc_phy_wrapper_n_1290,
      \po_counter_read_val_reg[6]\ => u_ddr_mc_phy_wrapper_n_1291,
      \po_counter_read_val_reg[7]\ => u_ddr_mc_phy_wrapper_n_1292,
      \po_counter_read_val_reg[8]\ => u_ddr_mc_phy_wrapper_n_1293,
      \po_counter_read_val_reg[8]_0\ => u_ddr_calib_top_n_745,
      \po_counter_read_val_reg[8]_1\ => u_ddr_calib_top_n_751,
      \po_counter_read_val_reg[8]_10\ => u_ddr_calib_top_n_753,
      \po_counter_read_val_reg[8]_11\ => u_ddr_calib_top_n_688,
      \po_counter_read_val_reg[8]_12\ => u_ddr_calib_top_n_695,
      \po_counter_read_val_reg[8]_13\ => u_ddr_calib_top_n_754,
      \po_counter_read_val_reg[8]_14\ => u_ddr_calib_top_n_691,
      \po_counter_read_val_reg[8]_15\ => u_ddr_calib_top_n_701,
      \po_counter_read_val_reg[8]_16\ => u_ddr_calib_top_n_755,
      \po_counter_read_val_reg[8]_17\ => u_ddr_calib_top_n_689,
      \po_counter_read_val_reg[8]_18\ => u_ddr_calib_top_n_707,
      \po_counter_read_val_reg[8]_19\ => u_ddr_calib_top_n_756,
      \po_counter_read_val_reg[8]_2\ => u_ddr_calib_top_n_748,
      \po_counter_read_val_reg[8]_20\ => u_ddr_calib_top_n_716,
      \po_counter_read_val_reg[8]_21\ => u_ddr_calib_top_n_714,
      \po_counter_read_val_reg[8]_22\ => u_ddr_calib_top_n_757,
      \po_counter_read_val_reg[8]_23\ => u_ddr_calib_top_n_720,
      \po_counter_read_val_reg[8]_24\ => u_ddr_calib_top_n_727,
      \po_counter_read_val_reg[8]_25\ => u_ddr_calib_top_n_758,
      \po_counter_read_val_reg[8]_26\ => u_ddr_calib_top_n_723,
      \po_counter_read_val_reg[8]_27\ => u_ddr_calib_top_n_733,
      \po_counter_read_val_reg[8]_28\ => u_ddr_calib_top_n_759,
      \po_counter_read_val_reg[8]_29\ => u_ddr_calib_top_n_721,
      \po_counter_read_val_reg[8]_3\ => u_ddr_calib_top_n_762,
      \po_counter_read_val_reg[8]_30\ => u_ddr_calib_top_n_739,
      \po_counter_read_val_reg[8]_31\ => u_ddr_calib_top_n_760,
      \po_counter_read_val_reg[8]_4\ => u_ddr_calib_top_n_746,
      \po_counter_read_val_reg[8]_5\ => u_ddr_calib_top_n_750,
      \po_counter_read_val_reg[8]_6\ => u_ddr_calib_top_n_749,
      \po_counter_read_val_reg[8]_7\ => u_ddr_calib_top_n_763,
      \po_counter_read_val_reg[8]_8\ => u_ddr_calib_top_n_684,
      \po_counter_read_val_reg[8]_9\ => u_ddr_calib_top_n_682,
      \po_stg2_wrcal_cnt_reg[2]\ => u_ddr_mc_phy_wrapper_n_1295,
      \po_stg2_wrcal_cnt_reg[2]_0\ => u_ddr_mc_phy_wrapper_n_1296,
      \po_stg2_wrcal_cnt_reg[2]_1\ => u_ddr_mc_phy_wrapper_n_1297,
      \po_stg2_wrcal_cnt_reg[2]_10\ => u_ddr_mc_phy_wrapper_n_1306,
      \po_stg2_wrcal_cnt_reg[2]_11\ => u_ddr_mc_phy_wrapper_n_1307,
      \po_stg2_wrcal_cnt_reg[2]_12\ => u_ddr_mc_phy_wrapper_n_1308,
      \po_stg2_wrcal_cnt_reg[2]_13\ => u_ddr_mc_phy_wrapper_n_1309,
      \po_stg2_wrcal_cnt_reg[2]_14\ => u_ddr_mc_phy_wrapper_n_1310,
      \po_stg2_wrcal_cnt_reg[2]_15\ => u_ddr_mc_phy_wrapper_n_1311,
      \po_stg2_wrcal_cnt_reg[2]_16\ => u_ddr_mc_phy_wrapper_n_1312,
      \po_stg2_wrcal_cnt_reg[2]_17\ => u_ddr_mc_phy_wrapper_n_1313,
      \po_stg2_wrcal_cnt_reg[2]_18\ => u_ddr_mc_phy_wrapper_n_1314,
      \po_stg2_wrcal_cnt_reg[2]_19\ => u_ddr_mc_phy_wrapper_n_1315,
      \po_stg2_wrcal_cnt_reg[2]_2\ => u_ddr_mc_phy_wrapper_n_1298,
      \po_stg2_wrcal_cnt_reg[2]_20\ => u_ddr_mc_phy_wrapper_n_1316,
      \po_stg2_wrcal_cnt_reg[2]_21\ => u_ddr_mc_phy_wrapper_n_1317,
      \po_stg2_wrcal_cnt_reg[2]_22\ => u_ddr_mc_phy_wrapper_n_1318,
      \po_stg2_wrcal_cnt_reg[2]_23\ => u_ddr_mc_phy_wrapper_n_1319,
      \po_stg2_wrcal_cnt_reg[2]_24\ => u_ddr_mc_phy_wrapper_n_1320,
      \po_stg2_wrcal_cnt_reg[2]_25\ => u_ddr_mc_phy_wrapper_n_1321,
      \po_stg2_wrcal_cnt_reg[2]_26\ => u_ddr_mc_phy_wrapper_n_1322,
      \po_stg2_wrcal_cnt_reg[2]_27\ => u_ddr_mc_phy_wrapper_n_1323,
      \po_stg2_wrcal_cnt_reg[2]_28\ => u_ddr_mc_phy_wrapper_n_1324,
      \po_stg2_wrcal_cnt_reg[2]_29\ => u_ddr_mc_phy_wrapper_n_1325,
      \po_stg2_wrcal_cnt_reg[2]_3\ => u_ddr_mc_phy_wrapper_n_1299,
      \po_stg2_wrcal_cnt_reg[2]_30\ => u_ddr_mc_phy_wrapper_n_1326,
      \po_stg2_wrcal_cnt_reg[2]_31\ => u_ddr_mc_phy_wrapper_n_1327,
      \po_stg2_wrcal_cnt_reg[2]_32\ => u_ddr_mc_phy_wrapper_n_1328,
      \po_stg2_wrcal_cnt_reg[2]_33\ => u_ddr_mc_phy_wrapper_n_1329,
      \po_stg2_wrcal_cnt_reg[2]_34\ => u_ddr_mc_phy_wrapper_n_1330,
      \po_stg2_wrcal_cnt_reg[2]_35\ => u_ddr_mc_phy_wrapper_n_1331,
      \po_stg2_wrcal_cnt_reg[2]_36\ => u_ddr_mc_phy_wrapper_n_1332,
      \po_stg2_wrcal_cnt_reg[2]_37\ => u_ddr_mc_phy_wrapper_n_1333,
      \po_stg2_wrcal_cnt_reg[2]_38\ => u_ddr_mc_phy_wrapper_n_1334,
      \po_stg2_wrcal_cnt_reg[2]_39\ => u_ddr_mc_phy_wrapper_n_1335,
      \po_stg2_wrcal_cnt_reg[2]_4\ => u_ddr_mc_phy_wrapper_n_1300,
      \po_stg2_wrcal_cnt_reg[2]_40\ => u_ddr_mc_phy_wrapper_n_1336,
      \po_stg2_wrcal_cnt_reg[2]_41\ => u_ddr_mc_phy_wrapper_n_1337,
      \po_stg2_wrcal_cnt_reg[2]_42\ => u_ddr_mc_phy_wrapper_n_1338,
      \po_stg2_wrcal_cnt_reg[2]_43\ => u_ddr_mc_phy_wrapper_n_1339,
      \po_stg2_wrcal_cnt_reg[2]_44\ => u_ddr_mc_phy_wrapper_n_1340,
      \po_stg2_wrcal_cnt_reg[2]_45\ => u_ddr_mc_phy_wrapper_n_1341,
      \po_stg2_wrcal_cnt_reg[2]_46\ => u_ddr_mc_phy_wrapper_n_1342,
      \po_stg2_wrcal_cnt_reg[2]_47\ => u_ddr_mc_phy_wrapper_n_1343,
      \po_stg2_wrcal_cnt_reg[2]_48\ => u_ddr_mc_phy_wrapper_n_1344,
      \po_stg2_wrcal_cnt_reg[2]_49\ => u_ddr_mc_phy_wrapper_n_1345,
      \po_stg2_wrcal_cnt_reg[2]_5\ => u_ddr_mc_phy_wrapper_n_1301,
      \po_stg2_wrcal_cnt_reg[2]_50\ => u_ddr_mc_phy_wrapper_n_1346,
      \po_stg2_wrcal_cnt_reg[2]_51\ => u_ddr_mc_phy_wrapper_n_1347,
      \po_stg2_wrcal_cnt_reg[2]_52\ => u_ddr_mc_phy_wrapper_n_1348,
      \po_stg2_wrcal_cnt_reg[2]_53\ => u_ddr_mc_phy_wrapper_n_1349,
      \po_stg2_wrcal_cnt_reg[2]_54\ => u_ddr_mc_phy_wrapper_n_1350,
      \po_stg2_wrcal_cnt_reg[2]_55\ => u_ddr_mc_phy_wrapper_n_1351,
      \po_stg2_wrcal_cnt_reg[2]_56\ => u_ddr_mc_phy_wrapper_n_1352,
      \po_stg2_wrcal_cnt_reg[2]_57\ => u_ddr_mc_phy_wrapper_n_1353,
      \po_stg2_wrcal_cnt_reg[2]_58\ => u_ddr_mc_phy_wrapper_n_1354,
      \po_stg2_wrcal_cnt_reg[2]_59\ => u_ddr_mc_phy_wrapper_n_1355,
      \po_stg2_wrcal_cnt_reg[2]_6\ => u_ddr_mc_phy_wrapper_n_1302,
      \po_stg2_wrcal_cnt_reg[2]_60\ => u_ddr_mc_phy_wrapper_n_1356,
      \po_stg2_wrcal_cnt_reg[2]_61\ => u_ddr_mc_phy_wrapper_n_1357,
      \po_stg2_wrcal_cnt_reg[2]_7\ => u_ddr_mc_phy_wrapper_n_1303,
      \po_stg2_wrcal_cnt_reg[2]_8\ => u_ddr_mc_phy_wrapper_n_1304,
      \po_stg2_wrcal_cnt_reg[2]_9\ => u_ddr_mc_phy_wrapper_n_1305,
      \rd_mux_sel_r_reg[2]\ => u_ddr_mc_phy_wrapper_n_595,
      \rd_mux_sel_r_reg[2]_0\ => u_ddr_mc_phy_wrapper_n_596,
      \rd_mux_sel_r_reg[2]_1\ => u_ddr_mc_phy_wrapper_n_597,
      \rd_mux_sel_r_reg[2]_10\ => u_ddr_mc_phy_wrapper_n_606,
      \rd_mux_sel_r_reg[2]_100\ => u_ddr_mc_phy_wrapper_n_1258,
      \rd_mux_sel_r_reg[2]_101\ => u_ddr_mc_phy_wrapper_n_1259,
      \rd_mux_sel_r_reg[2]_102\ => u_ddr_mc_phy_wrapper_n_1260,
      \rd_mux_sel_r_reg[2]_103\ => u_ddr_mc_phy_wrapper_n_1261,
      \rd_mux_sel_r_reg[2]_104\ => u_ddr_mc_phy_wrapper_n_1262,
      \rd_mux_sel_r_reg[2]_105\ => u_ddr_mc_phy_wrapper_n_1263,
      \rd_mux_sel_r_reg[2]_106\ => u_ddr_mc_phy_wrapper_n_1264,
      \rd_mux_sel_r_reg[2]_107\ => u_ddr_mc_phy_wrapper_n_1265,
      \rd_mux_sel_r_reg[2]_108\ => u_ddr_mc_phy_wrapper_n_1266,
      \rd_mux_sel_r_reg[2]_109\ => u_ddr_mc_phy_wrapper_n_1267,
      \rd_mux_sel_r_reg[2]_11\ => u_ddr_mc_phy_wrapper_n_607,
      \rd_mux_sel_r_reg[2]_110\ => u_ddr_mc_phy_wrapper_n_1268,
      \rd_mux_sel_r_reg[2]_111\ => u_ddr_mc_phy_wrapper_n_1269,
      \rd_mux_sel_r_reg[2]_112\ => u_ddr_mc_phy_wrapper_n_1270,
      \rd_mux_sel_r_reg[2]_113\ => u_ddr_mc_phy_wrapper_n_1271,
      \rd_mux_sel_r_reg[2]_114\ => u_ddr_mc_phy_wrapper_n_1272,
      \rd_mux_sel_r_reg[2]_115\ => u_ddr_mc_phy_wrapper_n_1273,
      \rd_mux_sel_r_reg[2]_116\ => u_ddr_mc_phy_wrapper_n_1274,
      \rd_mux_sel_r_reg[2]_117\ => u_ddr_mc_phy_wrapper_n_1275,
      \rd_mux_sel_r_reg[2]_118\ => u_ddr_mc_phy_wrapper_n_1276,
      \rd_mux_sel_r_reg[2]_119\ => u_ddr_mc_phy_wrapper_n_1277,
      \rd_mux_sel_r_reg[2]_12\ => u_ddr_mc_phy_wrapper_n_608,
      \rd_mux_sel_r_reg[2]_120\ => u_ddr_mc_phy_wrapper_n_1278,
      \rd_mux_sel_r_reg[2]_121\ => u_ddr_mc_phy_wrapper_n_1279,
      \rd_mux_sel_r_reg[2]_122\ => u_ddr_mc_phy_wrapper_n_1280,
      \rd_mux_sel_r_reg[2]_123\ => u_ddr_mc_phy_wrapper_n_1281,
      \rd_mux_sel_r_reg[2]_124\ => u_ddr_mc_phy_wrapper_n_1282,
      \rd_mux_sel_r_reg[2]_125\ => u_ddr_mc_phy_wrapper_n_1283,
      \rd_mux_sel_r_reg[2]_126\ => u_ddr_mc_phy_wrapper_n_1284,
      \rd_mux_sel_r_reg[2]_13\ => u_ddr_mc_phy_wrapper_n_609,
      \rd_mux_sel_r_reg[2]_14\ => u_ddr_mc_phy_wrapper_n_610,
      \rd_mux_sel_r_reg[2]_15\ => u_ddr_mc_phy_wrapper_n_611,
      \rd_mux_sel_r_reg[2]_16\ => u_ddr_mc_phy_wrapper_n_612,
      \rd_mux_sel_r_reg[2]_17\ => u_ddr_mc_phy_wrapper_n_613,
      \rd_mux_sel_r_reg[2]_18\ => u_ddr_mc_phy_wrapper_n_614,
      \rd_mux_sel_r_reg[2]_19\ => u_ddr_mc_phy_wrapper_n_615,
      \rd_mux_sel_r_reg[2]_2\ => u_ddr_mc_phy_wrapper_n_598,
      \rd_mux_sel_r_reg[2]_20\ => u_ddr_mc_phy_wrapper_n_616,
      \rd_mux_sel_r_reg[2]_21\ => u_ddr_mc_phy_wrapper_n_617,
      \rd_mux_sel_r_reg[2]_22\ => u_ddr_mc_phy_wrapper_n_618,
      \rd_mux_sel_r_reg[2]_23\ => u_ddr_mc_phy_wrapper_n_619,
      \rd_mux_sel_r_reg[2]_24\ => u_ddr_mc_phy_wrapper_n_620,
      \rd_mux_sel_r_reg[2]_25\ => u_ddr_mc_phy_wrapper_n_621,
      \rd_mux_sel_r_reg[2]_26\ => u_ddr_mc_phy_wrapper_n_622,
      \rd_mux_sel_r_reg[2]_27\ => u_ddr_mc_phy_wrapper_n_623,
      \rd_mux_sel_r_reg[2]_28\ => u_ddr_mc_phy_wrapper_n_624,
      \rd_mux_sel_r_reg[2]_29\ => u_ddr_mc_phy_wrapper_n_625,
      \rd_mux_sel_r_reg[2]_3\ => u_ddr_mc_phy_wrapper_n_599,
      \rd_mux_sel_r_reg[2]_30\ => u_ddr_mc_phy_wrapper_n_626,
      \rd_mux_sel_r_reg[2]_31\ => u_ddr_mc_phy_wrapper_n_627,
      \rd_mux_sel_r_reg[2]_32\ => u_ddr_mc_phy_wrapper_n_628,
      \rd_mux_sel_r_reg[2]_33\ => u_ddr_mc_phy_wrapper_n_629,
      \rd_mux_sel_r_reg[2]_34\ => u_ddr_mc_phy_wrapper_n_630,
      \rd_mux_sel_r_reg[2]_35\ => u_ddr_mc_phy_wrapper_n_631,
      \rd_mux_sel_r_reg[2]_36\ => u_ddr_mc_phy_wrapper_n_632,
      \rd_mux_sel_r_reg[2]_37\ => u_ddr_mc_phy_wrapper_n_633,
      \rd_mux_sel_r_reg[2]_38\ => u_ddr_mc_phy_wrapper_n_634,
      \rd_mux_sel_r_reg[2]_39\ => u_ddr_mc_phy_wrapper_n_635,
      \rd_mux_sel_r_reg[2]_4\ => u_ddr_mc_phy_wrapper_n_600,
      \rd_mux_sel_r_reg[2]_40\ => u_ddr_mc_phy_wrapper_n_636,
      \rd_mux_sel_r_reg[2]_41\ => u_ddr_mc_phy_wrapper_n_637,
      \rd_mux_sel_r_reg[2]_42\ => u_ddr_mc_phy_wrapper_n_638,
      \rd_mux_sel_r_reg[2]_43\ => u_ddr_mc_phy_wrapper_n_639,
      \rd_mux_sel_r_reg[2]_44\ => u_ddr_mc_phy_wrapper_n_640,
      \rd_mux_sel_r_reg[2]_45\ => u_ddr_mc_phy_wrapper_n_641,
      \rd_mux_sel_r_reg[2]_46\ => u_ddr_mc_phy_wrapper_n_642,
      \rd_mux_sel_r_reg[2]_47\ => u_ddr_mc_phy_wrapper_n_643,
      \rd_mux_sel_r_reg[2]_48\ => u_ddr_mc_phy_wrapper_n_644,
      \rd_mux_sel_r_reg[2]_49\ => u_ddr_mc_phy_wrapper_n_645,
      \rd_mux_sel_r_reg[2]_5\ => u_ddr_mc_phy_wrapper_n_601,
      \rd_mux_sel_r_reg[2]_50\ => u_ddr_mc_phy_wrapper_n_646,
      \rd_mux_sel_r_reg[2]_51\ => u_ddr_mc_phy_wrapper_n_647,
      \rd_mux_sel_r_reg[2]_52\ => u_ddr_mc_phy_wrapper_n_648,
      \rd_mux_sel_r_reg[2]_53\ => u_ddr_mc_phy_wrapper_n_649,
      \rd_mux_sel_r_reg[2]_54\ => u_ddr_mc_phy_wrapper_n_650,
      \rd_mux_sel_r_reg[2]_55\ => u_ddr_mc_phy_wrapper_n_651,
      \rd_mux_sel_r_reg[2]_56\ => u_ddr_mc_phy_wrapper_n_652,
      \rd_mux_sel_r_reg[2]_57\ => u_ddr_mc_phy_wrapper_n_653,
      \rd_mux_sel_r_reg[2]_58\ => u_ddr_mc_phy_wrapper_n_654,
      \rd_mux_sel_r_reg[2]_59\ => u_ddr_mc_phy_wrapper_n_655,
      \rd_mux_sel_r_reg[2]_6\ => u_ddr_mc_phy_wrapper_n_602,
      \rd_mux_sel_r_reg[2]_60\ => u_ddr_mc_phy_wrapper_n_656,
      \rd_mux_sel_r_reg[2]_61\ => u_ddr_mc_phy_wrapper_n_657,
      \rd_mux_sel_r_reg[2]_62\ => u_ddr_mc_phy_wrapper_n_658,
      \rd_mux_sel_r_reg[2]_63\ => u_ddr_mc_phy_wrapper_n_1221,
      \rd_mux_sel_r_reg[2]_64\ => u_ddr_mc_phy_wrapper_n_1222,
      \rd_mux_sel_r_reg[2]_65\ => u_ddr_mc_phy_wrapper_n_1223,
      \rd_mux_sel_r_reg[2]_66\ => u_ddr_mc_phy_wrapper_n_1224,
      \rd_mux_sel_r_reg[2]_67\ => u_ddr_mc_phy_wrapper_n_1225,
      \rd_mux_sel_r_reg[2]_68\ => u_ddr_mc_phy_wrapper_n_1226,
      \rd_mux_sel_r_reg[2]_69\ => u_ddr_mc_phy_wrapper_n_1227,
      \rd_mux_sel_r_reg[2]_7\ => u_ddr_mc_phy_wrapper_n_603,
      \rd_mux_sel_r_reg[2]_70\ => u_ddr_mc_phy_wrapper_n_1228,
      \rd_mux_sel_r_reg[2]_71\ => u_ddr_mc_phy_wrapper_n_1229,
      \rd_mux_sel_r_reg[2]_72\ => u_ddr_mc_phy_wrapper_n_1230,
      \rd_mux_sel_r_reg[2]_73\ => u_ddr_mc_phy_wrapper_n_1231,
      \rd_mux_sel_r_reg[2]_74\ => u_ddr_mc_phy_wrapper_n_1232,
      \rd_mux_sel_r_reg[2]_75\ => u_ddr_mc_phy_wrapper_n_1233,
      \rd_mux_sel_r_reg[2]_76\ => u_ddr_mc_phy_wrapper_n_1234,
      \rd_mux_sel_r_reg[2]_77\ => u_ddr_mc_phy_wrapper_n_1235,
      \rd_mux_sel_r_reg[2]_78\ => u_ddr_mc_phy_wrapper_n_1236,
      \rd_mux_sel_r_reg[2]_79\ => u_ddr_mc_phy_wrapper_n_1237,
      \rd_mux_sel_r_reg[2]_8\ => u_ddr_mc_phy_wrapper_n_604,
      \rd_mux_sel_r_reg[2]_80\ => u_ddr_mc_phy_wrapper_n_1238,
      \rd_mux_sel_r_reg[2]_81\ => u_ddr_mc_phy_wrapper_n_1239,
      \rd_mux_sel_r_reg[2]_82\ => u_ddr_mc_phy_wrapper_n_1240,
      \rd_mux_sel_r_reg[2]_83\ => u_ddr_mc_phy_wrapper_n_1241,
      \rd_mux_sel_r_reg[2]_84\ => u_ddr_mc_phy_wrapper_n_1242,
      \rd_mux_sel_r_reg[2]_85\ => u_ddr_mc_phy_wrapper_n_1243,
      \rd_mux_sel_r_reg[2]_86\ => u_ddr_mc_phy_wrapper_n_1244,
      \rd_mux_sel_r_reg[2]_87\ => u_ddr_mc_phy_wrapper_n_1245,
      \rd_mux_sel_r_reg[2]_88\ => u_ddr_mc_phy_wrapper_n_1246,
      \rd_mux_sel_r_reg[2]_89\ => u_ddr_mc_phy_wrapper_n_1247,
      \rd_mux_sel_r_reg[2]_9\ => u_ddr_mc_phy_wrapper_n_605,
      \rd_mux_sel_r_reg[2]_90\ => u_ddr_mc_phy_wrapper_n_1248,
      \rd_mux_sel_r_reg[2]_91\ => u_ddr_mc_phy_wrapper_n_1249,
      \rd_mux_sel_r_reg[2]_92\ => u_ddr_mc_phy_wrapper_n_1250,
      \rd_mux_sel_r_reg[2]_93\ => u_ddr_mc_phy_wrapper_n_1251,
      \rd_mux_sel_r_reg[2]_94\ => u_ddr_mc_phy_wrapper_n_1252,
      \rd_mux_sel_r_reg[2]_95\ => u_ddr_mc_phy_wrapper_n_1253,
      \rd_mux_sel_r_reg[2]_96\ => u_ddr_mc_phy_wrapper_n_1254,
      \rd_mux_sel_r_reg[2]_97\ => u_ddr_mc_phy_wrapper_n_1255,
      \rd_mux_sel_r_reg[2]_98\ => u_ddr_mc_phy_wrapper_n_1256,
      \rd_mux_sel_r_reg[2]_99\ => u_ddr_mc_phy_wrapper_n_1257,
      \rd_ptr_reg[3]\(63) => u_ddr_mc_phy_wrapper_n_660,
      \rd_ptr_reg[3]\(62) => u_ddr_mc_phy_wrapper_n_661,
      \rd_ptr_reg[3]\(61) => u_ddr_mc_phy_wrapper_n_662,
      \rd_ptr_reg[3]\(60) => u_ddr_mc_phy_wrapper_n_663,
      \rd_ptr_reg[3]\(59) => u_ddr_mc_phy_wrapper_n_664,
      \rd_ptr_reg[3]\(58) => u_ddr_mc_phy_wrapper_n_665,
      \rd_ptr_reg[3]\(57) => u_ddr_mc_phy_wrapper_n_666,
      \rd_ptr_reg[3]\(56) => u_ddr_mc_phy_wrapper_n_667,
      \rd_ptr_reg[3]\(55) => u_ddr_mc_phy_wrapper_n_668,
      \rd_ptr_reg[3]\(54) => u_ddr_mc_phy_wrapper_n_669,
      \rd_ptr_reg[3]\(53) => u_ddr_mc_phy_wrapper_n_670,
      \rd_ptr_reg[3]\(52) => u_ddr_mc_phy_wrapper_n_671,
      \rd_ptr_reg[3]\(51) => u_ddr_mc_phy_wrapper_n_672,
      \rd_ptr_reg[3]\(50) => u_ddr_mc_phy_wrapper_n_673,
      \rd_ptr_reg[3]\(49) => u_ddr_mc_phy_wrapper_n_674,
      \rd_ptr_reg[3]\(48) => u_ddr_mc_phy_wrapper_n_675,
      \rd_ptr_reg[3]\(47) => u_ddr_mc_phy_wrapper_n_676,
      \rd_ptr_reg[3]\(46) => u_ddr_mc_phy_wrapper_n_677,
      \rd_ptr_reg[3]\(45) => u_ddr_mc_phy_wrapper_n_678,
      \rd_ptr_reg[3]\(44) => u_ddr_mc_phy_wrapper_n_679,
      \rd_ptr_reg[3]\(43) => u_ddr_mc_phy_wrapper_n_680,
      \rd_ptr_reg[3]\(42) => u_ddr_mc_phy_wrapper_n_681,
      \rd_ptr_reg[3]\(41) => u_ddr_mc_phy_wrapper_n_682,
      \rd_ptr_reg[3]\(40) => u_ddr_mc_phy_wrapper_n_683,
      \rd_ptr_reg[3]\(39) => u_ddr_mc_phy_wrapper_n_684,
      \rd_ptr_reg[3]\(38) => u_ddr_mc_phy_wrapper_n_685,
      \rd_ptr_reg[3]\(37) => u_ddr_mc_phy_wrapper_n_686,
      \rd_ptr_reg[3]\(36) => u_ddr_mc_phy_wrapper_n_687,
      \rd_ptr_reg[3]\(35) => u_ddr_mc_phy_wrapper_n_688,
      \rd_ptr_reg[3]\(34) => u_ddr_mc_phy_wrapper_n_689,
      \rd_ptr_reg[3]\(33) => u_ddr_mc_phy_wrapper_n_690,
      \rd_ptr_reg[3]\(32) => u_ddr_mc_phy_wrapper_n_691,
      \rd_ptr_reg[3]\(31) => u_ddr_mc_phy_wrapper_n_692,
      \rd_ptr_reg[3]\(30) => u_ddr_mc_phy_wrapper_n_693,
      \rd_ptr_reg[3]\(29) => u_ddr_mc_phy_wrapper_n_694,
      \rd_ptr_reg[3]\(28) => u_ddr_mc_phy_wrapper_n_695,
      \rd_ptr_reg[3]\(27) => u_ddr_mc_phy_wrapper_n_696,
      \rd_ptr_reg[3]\(26) => u_ddr_mc_phy_wrapper_n_697,
      \rd_ptr_reg[3]\(25) => u_ddr_mc_phy_wrapper_n_698,
      \rd_ptr_reg[3]\(24) => u_ddr_mc_phy_wrapper_n_699,
      \rd_ptr_reg[3]\(23) => u_ddr_mc_phy_wrapper_n_700,
      \rd_ptr_reg[3]\(22) => u_ddr_mc_phy_wrapper_n_701,
      \rd_ptr_reg[3]\(21) => u_ddr_mc_phy_wrapper_n_702,
      \rd_ptr_reg[3]\(20) => u_ddr_mc_phy_wrapper_n_703,
      \rd_ptr_reg[3]\(19) => u_ddr_mc_phy_wrapper_n_704,
      \rd_ptr_reg[3]\(18) => u_ddr_mc_phy_wrapper_n_705,
      \rd_ptr_reg[3]\(17) => u_ddr_mc_phy_wrapper_n_706,
      \rd_ptr_reg[3]\(16) => u_ddr_mc_phy_wrapper_n_707,
      \rd_ptr_reg[3]\(15) => u_ddr_mc_phy_wrapper_n_708,
      \rd_ptr_reg[3]\(14) => u_ddr_mc_phy_wrapper_n_709,
      \rd_ptr_reg[3]\(13) => u_ddr_mc_phy_wrapper_n_710,
      \rd_ptr_reg[3]\(12) => u_ddr_mc_phy_wrapper_n_711,
      \rd_ptr_reg[3]\(11) => u_ddr_mc_phy_wrapper_n_712,
      \rd_ptr_reg[3]\(10) => u_ddr_mc_phy_wrapper_n_713,
      \rd_ptr_reg[3]\(9) => u_ddr_mc_phy_wrapper_n_714,
      \rd_ptr_reg[3]\(8) => u_ddr_mc_phy_wrapper_n_715,
      \rd_ptr_reg[3]\(7) => u_ddr_mc_phy_wrapper_n_716,
      \rd_ptr_reg[3]\(6) => u_ddr_mc_phy_wrapper_n_717,
      \rd_ptr_reg[3]\(5) => u_ddr_mc_phy_wrapper_n_718,
      \rd_ptr_reg[3]\(4) => u_ddr_mc_phy_wrapper_n_719,
      \rd_ptr_reg[3]\(3) => u_ddr_mc_phy_wrapper_n_720,
      \rd_ptr_reg[3]\(2) => u_ddr_mc_phy_wrapper_n_721,
      \rd_ptr_reg[3]\(1) => u_ddr_mc_phy_wrapper_n_722,
      \rd_ptr_reg[3]\(0) => u_ddr_mc_phy_wrapper_n_723,
      \rd_ptr_reg[3]_0\(63) => u_ddr_mc_phy_wrapper_n_724,
      \rd_ptr_reg[3]_0\(62) => u_ddr_mc_phy_wrapper_n_725,
      \rd_ptr_reg[3]_0\(61) => u_ddr_mc_phy_wrapper_n_726,
      \rd_ptr_reg[3]_0\(60) => u_ddr_mc_phy_wrapper_n_727,
      \rd_ptr_reg[3]_0\(59) => u_ddr_mc_phy_wrapper_n_728,
      \rd_ptr_reg[3]_0\(58) => u_ddr_mc_phy_wrapper_n_729,
      \rd_ptr_reg[3]_0\(57) => u_ddr_mc_phy_wrapper_n_730,
      \rd_ptr_reg[3]_0\(56) => u_ddr_mc_phy_wrapper_n_731,
      \rd_ptr_reg[3]_0\(55) => u_ddr_mc_phy_wrapper_n_732,
      \rd_ptr_reg[3]_0\(54) => u_ddr_mc_phy_wrapper_n_733,
      \rd_ptr_reg[3]_0\(53) => u_ddr_mc_phy_wrapper_n_734,
      \rd_ptr_reg[3]_0\(52) => u_ddr_mc_phy_wrapper_n_735,
      \rd_ptr_reg[3]_0\(51) => u_ddr_mc_phy_wrapper_n_736,
      \rd_ptr_reg[3]_0\(50) => u_ddr_mc_phy_wrapper_n_737,
      \rd_ptr_reg[3]_0\(49) => u_ddr_mc_phy_wrapper_n_738,
      \rd_ptr_reg[3]_0\(48) => u_ddr_mc_phy_wrapper_n_739,
      \rd_ptr_reg[3]_0\(47) => u_ddr_mc_phy_wrapper_n_740,
      \rd_ptr_reg[3]_0\(46) => u_ddr_mc_phy_wrapper_n_741,
      \rd_ptr_reg[3]_0\(45) => u_ddr_mc_phy_wrapper_n_742,
      \rd_ptr_reg[3]_0\(44) => u_ddr_mc_phy_wrapper_n_743,
      \rd_ptr_reg[3]_0\(43) => u_ddr_mc_phy_wrapper_n_744,
      \rd_ptr_reg[3]_0\(42) => u_ddr_mc_phy_wrapper_n_745,
      \rd_ptr_reg[3]_0\(41) => u_ddr_mc_phy_wrapper_n_746,
      \rd_ptr_reg[3]_0\(40) => u_ddr_mc_phy_wrapper_n_747,
      \rd_ptr_reg[3]_0\(39) => u_ddr_mc_phy_wrapper_n_748,
      \rd_ptr_reg[3]_0\(38) => u_ddr_mc_phy_wrapper_n_749,
      \rd_ptr_reg[3]_0\(37) => u_ddr_mc_phy_wrapper_n_750,
      \rd_ptr_reg[3]_0\(36) => u_ddr_mc_phy_wrapper_n_751,
      \rd_ptr_reg[3]_0\(35) => u_ddr_mc_phy_wrapper_n_752,
      \rd_ptr_reg[3]_0\(34) => u_ddr_mc_phy_wrapper_n_753,
      \rd_ptr_reg[3]_0\(33) => u_ddr_mc_phy_wrapper_n_754,
      \rd_ptr_reg[3]_0\(32) => u_ddr_mc_phy_wrapper_n_755,
      \rd_ptr_reg[3]_0\(31) => u_ddr_mc_phy_wrapper_n_756,
      \rd_ptr_reg[3]_0\(30) => u_ddr_mc_phy_wrapper_n_757,
      \rd_ptr_reg[3]_0\(29) => u_ddr_mc_phy_wrapper_n_758,
      \rd_ptr_reg[3]_0\(28) => u_ddr_mc_phy_wrapper_n_759,
      \rd_ptr_reg[3]_0\(27) => u_ddr_mc_phy_wrapper_n_760,
      \rd_ptr_reg[3]_0\(26) => u_ddr_mc_phy_wrapper_n_761,
      \rd_ptr_reg[3]_0\(25) => u_ddr_mc_phy_wrapper_n_762,
      \rd_ptr_reg[3]_0\(24) => u_ddr_mc_phy_wrapper_n_763,
      \rd_ptr_reg[3]_0\(23) => u_ddr_mc_phy_wrapper_n_764,
      \rd_ptr_reg[3]_0\(22) => u_ddr_mc_phy_wrapper_n_765,
      \rd_ptr_reg[3]_0\(21) => u_ddr_mc_phy_wrapper_n_766,
      \rd_ptr_reg[3]_0\(20) => u_ddr_mc_phy_wrapper_n_767,
      \rd_ptr_reg[3]_0\(19) => u_ddr_mc_phy_wrapper_n_768,
      \rd_ptr_reg[3]_0\(18) => u_ddr_mc_phy_wrapper_n_769,
      \rd_ptr_reg[3]_0\(17) => u_ddr_mc_phy_wrapper_n_770,
      \rd_ptr_reg[3]_0\(16) => u_ddr_mc_phy_wrapper_n_771,
      \rd_ptr_reg[3]_0\(15) => u_ddr_mc_phy_wrapper_n_772,
      \rd_ptr_reg[3]_0\(14) => u_ddr_mc_phy_wrapper_n_773,
      \rd_ptr_reg[3]_0\(13) => u_ddr_mc_phy_wrapper_n_774,
      \rd_ptr_reg[3]_0\(12) => u_ddr_mc_phy_wrapper_n_775,
      \rd_ptr_reg[3]_0\(11) => u_ddr_mc_phy_wrapper_n_776,
      \rd_ptr_reg[3]_0\(10) => u_ddr_mc_phy_wrapper_n_777,
      \rd_ptr_reg[3]_0\(9) => u_ddr_mc_phy_wrapper_n_778,
      \rd_ptr_reg[3]_0\(8) => u_ddr_mc_phy_wrapper_n_779,
      \rd_ptr_reg[3]_0\(7) => u_ddr_mc_phy_wrapper_n_780,
      \rd_ptr_reg[3]_0\(6) => u_ddr_mc_phy_wrapper_n_781,
      \rd_ptr_reg[3]_0\(5) => u_ddr_mc_phy_wrapper_n_782,
      \rd_ptr_reg[3]_0\(4) => u_ddr_mc_phy_wrapper_n_783,
      \rd_ptr_reg[3]_0\(3) => u_ddr_mc_phy_wrapper_n_784,
      \rd_ptr_reg[3]_0\(2) => u_ddr_mc_phy_wrapper_n_785,
      \rd_ptr_reg[3]_0\(1) => u_ddr_mc_phy_wrapper_n_786,
      \rd_ptr_reg[3]_0\(0) => u_ddr_mc_phy_wrapper_n_787,
      \rd_ptr_reg[3]_1\(63) => u_ddr_mc_phy_wrapper_n_788,
      \rd_ptr_reg[3]_1\(62) => u_ddr_mc_phy_wrapper_n_789,
      \rd_ptr_reg[3]_1\(61) => u_ddr_mc_phy_wrapper_n_790,
      \rd_ptr_reg[3]_1\(60) => u_ddr_mc_phy_wrapper_n_791,
      \rd_ptr_reg[3]_1\(59) => u_ddr_mc_phy_wrapper_n_792,
      \rd_ptr_reg[3]_1\(58) => u_ddr_mc_phy_wrapper_n_793,
      \rd_ptr_reg[3]_1\(57) => u_ddr_mc_phy_wrapper_n_794,
      \rd_ptr_reg[3]_1\(56) => u_ddr_mc_phy_wrapper_n_795,
      \rd_ptr_reg[3]_1\(55) => u_ddr_mc_phy_wrapper_n_796,
      \rd_ptr_reg[3]_1\(54) => u_ddr_mc_phy_wrapper_n_797,
      \rd_ptr_reg[3]_1\(53) => u_ddr_mc_phy_wrapper_n_798,
      \rd_ptr_reg[3]_1\(52) => u_ddr_mc_phy_wrapper_n_799,
      \rd_ptr_reg[3]_1\(51) => u_ddr_mc_phy_wrapper_n_800,
      \rd_ptr_reg[3]_1\(50) => u_ddr_mc_phy_wrapper_n_801,
      \rd_ptr_reg[3]_1\(49) => u_ddr_mc_phy_wrapper_n_802,
      \rd_ptr_reg[3]_1\(48) => u_ddr_mc_phy_wrapper_n_803,
      \rd_ptr_reg[3]_1\(47) => u_ddr_mc_phy_wrapper_n_804,
      \rd_ptr_reg[3]_1\(46) => u_ddr_mc_phy_wrapper_n_805,
      \rd_ptr_reg[3]_1\(45) => u_ddr_mc_phy_wrapper_n_806,
      \rd_ptr_reg[3]_1\(44) => u_ddr_mc_phy_wrapper_n_807,
      \rd_ptr_reg[3]_1\(43) => u_ddr_mc_phy_wrapper_n_808,
      \rd_ptr_reg[3]_1\(42) => u_ddr_mc_phy_wrapper_n_809,
      \rd_ptr_reg[3]_1\(41) => u_ddr_mc_phy_wrapper_n_810,
      \rd_ptr_reg[3]_1\(40) => u_ddr_mc_phy_wrapper_n_811,
      \rd_ptr_reg[3]_1\(39) => u_ddr_mc_phy_wrapper_n_812,
      \rd_ptr_reg[3]_1\(38) => u_ddr_mc_phy_wrapper_n_813,
      \rd_ptr_reg[3]_1\(37) => u_ddr_mc_phy_wrapper_n_814,
      \rd_ptr_reg[3]_1\(36) => u_ddr_mc_phy_wrapper_n_815,
      \rd_ptr_reg[3]_1\(35) => u_ddr_mc_phy_wrapper_n_816,
      \rd_ptr_reg[3]_1\(34) => u_ddr_mc_phy_wrapper_n_817,
      \rd_ptr_reg[3]_1\(33) => u_ddr_mc_phy_wrapper_n_818,
      \rd_ptr_reg[3]_1\(32) => u_ddr_mc_phy_wrapper_n_819,
      \rd_ptr_reg[3]_1\(31) => u_ddr_mc_phy_wrapper_n_820,
      \rd_ptr_reg[3]_1\(30) => u_ddr_mc_phy_wrapper_n_821,
      \rd_ptr_reg[3]_1\(29) => u_ddr_mc_phy_wrapper_n_822,
      \rd_ptr_reg[3]_1\(28) => u_ddr_mc_phy_wrapper_n_823,
      \rd_ptr_reg[3]_1\(27) => u_ddr_mc_phy_wrapper_n_824,
      \rd_ptr_reg[3]_1\(26) => u_ddr_mc_phy_wrapper_n_825,
      \rd_ptr_reg[3]_1\(25) => u_ddr_mc_phy_wrapper_n_826,
      \rd_ptr_reg[3]_1\(24) => u_ddr_mc_phy_wrapper_n_827,
      \rd_ptr_reg[3]_1\(23) => u_ddr_mc_phy_wrapper_n_828,
      \rd_ptr_reg[3]_1\(22) => u_ddr_mc_phy_wrapper_n_829,
      \rd_ptr_reg[3]_1\(21) => u_ddr_mc_phy_wrapper_n_830,
      \rd_ptr_reg[3]_1\(20) => u_ddr_mc_phy_wrapper_n_831,
      \rd_ptr_reg[3]_1\(19) => u_ddr_mc_phy_wrapper_n_832,
      \rd_ptr_reg[3]_1\(18) => u_ddr_mc_phy_wrapper_n_833,
      \rd_ptr_reg[3]_1\(17) => u_ddr_mc_phy_wrapper_n_834,
      \rd_ptr_reg[3]_1\(16) => u_ddr_mc_phy_wrapper_n_835,
      \rd_ptr_reg[3]_1\(15) => u_ddr_mc_phy_wrapper_n_836,
      \rd_ptr_reg[3]_1\(14) => u_ddr_mc_phy_wrapper_n_837,
      \rd_ptr_reg[3]_1\(13) => u_ddr_mc_phy_wrapper_n_838,
      \rd_ptr_reg[3]_1\(12) => u_ddr_mc_phy_wrapper_n_839,
      \rd_ptr_reg[3]_1\(11) => u_ddr_mc_phy_wrapper_n_840,
      \rd_ptr_reg[3]_1\(10) => u_ddr_mc_phy_wrapper_n_841,
      \rd_ptr_reg[3]_1\(9) => u_ddr_mc_phy_wrapper_n_842,
      \rd_ptr_reg[3]_1\(8) => u_ddr_mc_phy_wrapper_n_843,
      \rd_ptr_reg[3]_1\(7) => u_ddr_mc_phy_wrapper_n_844,
      \rd_ptr_reg[3]_1\(6) => u_ddr_mc_phy_wrapper_n_845,
      \rd_ptr_reg[3]_1\(5) => u_ddr_mc_phy_wrapper_n_846,
      \rd_ptr_reg[3]_1\(4) => u_ddr_mc_phy_wrapper_n_847,
      \rd_ptr_reg[3]_1\(3) => u_ddr_mc_phy_wrapper_n_848,
      \rd_ptr_reg[3]_1\(2) => u_ddr_mc_phy_wrapper_n_849,
      \rd_ptr_reg[3]_1\(1) => u_ddr_mc_phy_wrapper_n_850,
      \rd_ptr_reg[3]_1\(0) => u_ddr_mc_phy_wrapper_n_851,
      \rd_ptr_reg[3]_2\(63) => u_ddr_mc_phy_wrapper_n_852,
      \rd_ptr_reg[3]_2\(62) => u_ddr_mc_phy_wrapper_n_853,
      \rd_ptr_reg[3]_2\(61) => u_ddr_mc_phy_wrapper_n_854,
      \rd_ptr_reg[3]_2\(60) => u_ddr_mc_phy_wrapper_n_855,
      \rd_ptr_reg[3]_2\(59) => u_ddr_mc_phy_wrapper_n_856,
      \rd_ptr_reg[3]_2\(58) => u_ddr_mc_phy_wrapper_n_857,
      \rd_ptr_reg[3]_2\(57) => u_ddr_mc_phy_wrapper_n_858,
      \rd_ptr_reg[3]_2\(56) => u_ddr_mc_phy_wrapper_n_859,
      \rd_ptr_reg[3]_2\(55) => u_ddr_mc_phy_wrapper_n_860,
      \rd_ptr_reg[3]_2\(54) => u_ddr_mc_phy_wrapper_n_861,
      \rd_ptr_reg[3]_2\(53) => u_ddr_mc_phy_wrapper_n_862,
      \rd_ptr_reg[3]_2\(52) => u_ddr_mc_phy_wrapper_n_863,
      \rd_ptr_reg[3]_2\(51) => u_ddr_mc_phy_wrapper_n_864,
      \rd_ptr_reg[3]_2\(50) => u_ddr_mc_phy_wrapper_n_865,
      \rd_ptr_reg[3]_2\(49) => u_ddr_mc_phy_wrapper_n_866,
      \rd_ptr_reg[3]_2\(48) => u_ddr_mc_phy_wrapper_n_867,
      \rd_ptr_reg[3]_2\(47) => u_ddr_mc_phy_wrapper_n_868,
      \rd_ptr_reg[3]_2\(46) => u_ddr_mc_phy_wrapper_n_869,
      \rd_ptr_reg[3]_2\(45) => u_ddr_mc_phy_wrapper_n_870,
      \rd_ptr_reg[3]_2\(44) => u_ddr_mc_phy_wrapper_n_871,
      \rd_ptr_reg[3]_2\(43) => u_ddr_mc_phy_wrapper_n_872,
      \rd_ptr_reg[3]_2\(42) => u_ddr_mc_phy_wrapper_n_873,
      \rd_ptr_reg[3]_2\(41) => u_ddr_mc_phy_wrapper_n_874,
      \rd_ptr_reg[3]_2\(40) => u_ddr_mc_phy_wrapper_n_875,
      \rd_ptr_reg[3]_2\(39) => u_ddr_mc_phy_wrapper_n_876,
      \rd_ptr_reg[3]_2\(38) => u_ddr_mc_phy_wrapper_n_877,
      \rd_ptr_reg[3]_2\(37) => u_ddr_mc_phy_wrapper_n_878,
      \rd_ptr_reg[3]_2\(36) => u_ddr_mc_phy_wrapper_n_879,
      \rd_ptr_reg[3]_2\(35) => u_ddr_mc_phy_wrapper_n_880,
      \rd_ptr_reg[3]_2\(34) => u_ddr_mc_phy_wrapper_n_881,
      \rd_ptr_reg[3]_2\(33) => u_ddr_mc_phy_wrapper_n_882,
      \rd_ptr_reg[3]_2\(32) => u_ddr_mc_phy_wrapper_n_883,
      \rd_ptr_reg[3]_2\(31) => u_ddr_mc_phy_wrapper_n_884,
      \rd_ptr_reg[3]_2\(30) => u_ddr_mc_phy_wrapper_n_885,
      \rd_ptr_reg[3]_2\(29) => u_ddr_mc_phy_wrapper_n_886,
      \rd_ptr_reg[3]_2\(28) => u_ddr_mc_phy_wrapper_n_887,
      \rd_ptr_reg[3]_2\(27) => u_ddr_mc_phy_wrapper_n_888,
      \rd_ptr_reg[3]_2\(26) => u_ddr_mc_phy_wrapper_n_889,
      \rd_ptr_reg[3]_2\(25) => u_ddr_mc_phy_wrapper_n_890,
      \rd_ptr_reg[3]_2\(24) => u_ddr_mc_phy_wrapper_n_891,
      \rd_ptr_reg[3]_2\(23) => u_ddr_mc_phy_wrapper_n_892,
      \rd_ptr_reg[3]_2\(22) => u_ddr_mc_phy_wrapper_n_893,
      \rd_ptr_reg[3]_2\(21) => u_ddr_mc_phy_wrapper_n_894,
      \rd_ptr_reg[3]_2\(20) => u_ddr_mc_phy_wrapper_n_895,
      \rd_ptr_reg[3]_2\(19) => u_ddr_mc_phy_wrapper_n_896,
      \rd_ptr_reg[3]_2\(18) => u_ddr_mc_phy_wrapper_n_897,
      \rd_ptr_reg[3]_2\(17) => u_ddr_mc_phy_wrapper_n_898,
      \rd_ptr_reg[3]_2\(16) => u_ddr_mc_phy_wrapper_n_899,
      \rd_ptr_reg[3]_2\(15) => u_ddr_mc_phy_wrapper_n_900,
      \rd_ptr_reg[3]_2\(14) => u_ddr_mc_phy_wrapper_n_901,
      \rd_ptr_reg[3]_2\(13) => u_ddr_mc_phy_wrapper_n_902,
      \rd_ptr_reg[3]_2\(12) => u_ddr_mc_phy_wrapper_n_903,
      \rd_ptr_reg[3]_2\(11) => u_ddr_mc_phy_wrapper_n_904,
      \rd_ptr_reg[3]_2\(10) => u_ddr_mc_phy_wrapper_n_905,
      \rd_ptr_reg[3]_2\(9) => u_ddr_mc_phy_wrapper_n_906,
      \rd_ptr_reg[3]_2\(8) => u_ddr_mc_phy_wrapper_n_907,
      \rd_ptr_reg[3]_2\(7) => u_ddr_mc_phy_wrapper_n_908,
      \rd_ptr_reg[3]_2\(6) => u_ddr_mc_phy_wrapper_n_909,
      \rd_ptr_reg[3]_2\(5) => u_ddr_mc_phy_wrapper_n_910,
      \rd_ptr_reg[3]_2\(4) => u_ddr_mc_phy_wrapper_n_911,
      \rd_ptr_reg[3]_2\(3) => u_ddr_mc_phy_wrapper_n_912,
      \rd_ptr_reg[3]_2\(2) => u_ddr_mc_phy_wrapper_n_913,
      \rd_ptr_reg[3]_2\(1) => u_ddr_mc_phy_wrapper_n_914,
      \rd_ptr_reg[3]_2\(0) => u_ddr_mc_phy_wrapper_n_915,
      \rd_ptr_reg[3]_3\(63) => u_ddr_mc_phy_wrapper_n_922,
      \rd_ptr_reg[3]_3\(62) => u_ddr_mc_phy_wrapper_n_923,
      \rd_ptr_reg[3]_3\(61) => u_ddr_mc_phy_wrapper_n_924,
      \rd_ptr_reg[3]_3\(60) => u_ddr_mc_phy_wrapper_n_925,
      \rd_ptr_reg[3]_3\(59) => u_ddr_mc_phy_wrapper_n_926,
      \rd_ptr_reg[3]_3\(58) => u_ddr_mc_phy_wrapper_n_927,
      \rd_ptr_reg[3]_3\(57) => u_ddr_mc_phy_wrapper_n_928,
      \rd_ptr_reg[3]_3\(56) => u_ddr_mc_phy_wrapper_n_929,
      \rd_ptr_reg[3]_3\(55) => u_ddr_mc_phy_wrapper_n_930,
      \rd_ptr_reg[3]_3\(54) => u_ddr_mc_phy_wrapper_n_931,
      \rd_ptr_reg[3]_3\(53) => u_ddr_mc_phy_wrapper_n_932,
      \rd_ptr_reg[3]_3\(52) => u_ddr_mc_phy_wrapper_n_933,
      \rd_ptr_reg[3]_3\(51) => u_ddr_mc_phy_wrapper_n_934,
      \rd_ptr_reg[3]_3\(50) => u_ddr_mc_phy_wrapper_n_935,
      \rd_ptr_reg[3]_3\(49) => u_ddr_mc_phy_wrapper_n_936,
      \rd_ptr_reg[3]_3\(48) => u_ddr_mc_phy_wrapper_n_937,
      \rd_ptr_reg[3]_3\(47) => u_ddr_mc_phy_wrapper_n_938,
      \rd_ptr_reg[3]_3\(46) => u_ddr_mc_phy_wrapper_n_939,
      \rd_ptr_reg[3]_3\(45) => u_ddr_mc_phy_wrapper_n_940,
      \rd_ptr_reg[3]_3\(44) => u_ddr_mc_phy_wrapper_n_941,
      \rd_ptr_reg[3]_3\(43) => u_ddr_mc_phy_wrapper_n_942,
      \rd_ptr_reg[3]_3\(42) => u_ddr_mc_phy_wrapper_n_943,
      \rd_ptr_reg[3]_3\(41) => u_ddr_mc_phy_wrapper_n_944,
      \rd_ptr_reg[3]_3\(40) => u_ddr_mc_phy_wrapper_n_945,
      \rd_ptr_reg[3]_3\(39) => u_ddr_mc_phy_wrapper_n_946,
      \rd_ptr_reg[3]_3\(38) => u_ddr_mc_phy_wrapper_n_947,
      \rd_ptr_reg[3]_3\(37) => u_ddr_mc_phy_wrapper_n_948,
      \rd_ptr_reg[3]_3\(36) => u_ddr_mc_phy_wrapper_n_949,
      \rd_ptr_reg[3]_3\(35) => u_ddr_mc_phy_wrapper_n_950,
      \rd_ptr_reg[3]_3\(34) => u_ddr_mc_phy_wrapper_n_951,
      \rd_ptr_reg[3]_3\(33) => u_ddr_mc_phy_wrapper_n_952,
      \rd_ptr_reg[3]_3\(32) => u_ddr_mc_phy_wrapper_n_953,
      \rd_ptr_reg[3]_3\(31) => u_ddr_mc_phy_wrapper_n_954,
      \rd_ptr_reg[3]_3\(30) => u_ddr_mc_phy_wrapper_n_955,
      \rd_ptr_reg[3]_3\(29) => u_ddr_mc_phy_wrapper_n_956,
      \rd_ptr_reg[3]_3\(28) => u_ddr_mc_phy_wrapper_n_957,
      \rd_ptr_reg[3]_3\(27) => u_ddr_mc_phy_wrapper_n_958,
      \rd_ptr_reg[3]_3\(26) => u_ddr_mc_phy_wrapper_n_959,
      \rd_ptr_reg[3]_3\(25) => u_ddr_mc_phy_wrapper_n_960,
      \rd_ptr_reg[3]_3\(24) => u_ddr_mc_phy_wrapper_n_961,
      \rd_ptr_reg[3]_3\(23) => u_ddr_mc_phy_wrapper_n_962,
      \rd_ptr_reg[3]_3\(22) => u_ddr_mc_phy_wrapper_n_963,
      \rd_ptr_reg[3]_3\(21) => u_ddr_mc_phy_wrapper_n_964,
      \rd_ptr_reg[3]_3\(20) => u_ddr_mc_phy_wrapper_n_965,
      \rd_ptr_reg[3]_3\(19) => u_ddr_mc_phy_wrapper_n_966,
      \rd_ptr_reg[3]_3\(18) => u_ddr_mc_phy_wrapper_n_967,
      \rd_ptr_reg[3]_3\(17) => u_ddr_mc_phy_wrapper_n_968,
      \rd_ptr_reg[3]_3\(16) => u_ddr_mc_phy_wrapper_n_969,
      \rd_ptr_reg[3]_3\(15) => u_ddr_mc_phy_wrapper_n_970,
      \rd_ptr_reg[3]_3\(14) => u_ddr_mc_phy_wrapper_n_971,
      \rd_ptr_reg[3]_3\(13) => u_ddr_mc_phy_wrapper_n_972,
      \rd_ptr_reg[3]_3\(12) => u_ddr_mc_phy_wrapper_n_973,
      \rd_ptr_reg[3]_3\(11) => u_ddr_mc_phy_wrapper_n_974,
      \rd_ptr_reg[3]_3\(10) => u_ddr_mc_phy_wrapper_n_975,
      \rd_ptr_reg[3]_3\(9) => u_ddr_mc_phy_wrapper_n_976,
      \rd_ptr_reg[3]_3\(8) => u_ddr_mc_phy_wrapper_n_977,
      \rd_ptr_reg[3]_3\(7) => u_ddr_mc_phy_wrapper_n_978,
      \rd_ptr_reg[3]_3\(6) => u_ddr_mc_phy_wrapper_n_979,
      \rd_ptr_reg[3]_3\(5) => u_ddr_mc_phy_wrapper_n_980,
      \rd_ptr_reg[3]_3\(4) => u_ddr_mc_phy_wrapper_n_981,
      \rd_ptr_reg[3]_3\(3) => u_ddr_mc_phy_wrapper_n_982,
      \rd_ptr_reg[3]_3\(2) => u_ddr_mc_phy_wrapper_n_983,
      \rd_ptr_reg[3]_3\(1) => u_ddr_mc_phy_wrapper_n_984,
      \rd_ptr_reg[3]_3\(0) => u_ddr_mc_phy_wrapper_n_985,
      \rd_ptr_reg[3]_4\(63) => u_ddr_mc_phy_wrapper_n_986,
      \rd_ptr_reg[3]_4\(62) => u_ddr_mc_phy_wrapper_n_987,
      \rd_ptr_reg[3]_4\(61) => u_ddr_mc_phy_wrapper_n_988,
      \rd_ptr_reg[3]_4\(60) => u_ddr_mc_phy_wrapper_n_989,
      \rd_ptr_reg[3]_4\(59) => u_ddr_mc_phy_wrapper_n_990,
      \rd_ptr_reg[3]_4\(58) => u_ddr_mc_phy_wrapper_n_991,
      \rd_ptr_reg[3]_4\(57) => u_ddr_mc_phy_wrapper_n_992,
      \rd_ptr_reg[3]_4\(56) => u_ddr_mc_phy_wrapper_n_993,
      \rd_ptr_reg[3]_4\(55) => u_ddr_mc_phy_wrapper_n_994,
      \rd_ptr_reg[3]_4\(54) => u_ddr_mc_phy_wrapper_n_995,
      \rd_ptr_reg[3]_4\(53) => u_ddr_mc_phy_wrapper_n_996,
      \rd_ptr_reg[3]_4\(52) => u_ddr_mc_phy_wrapper_n_997,
      \rd_ptr_reg[3]_4\(51) => u_ddr_mc_phy_wrapper_n_998,
      \rd_ptr_reg[3]_4\(50) => u_ddr_mc_phy_wrapper_n_999,
      \rd_ptr_reg[3]_4\(49) => u_ddr_mc_phy_wrapper_n_1000,
      \rd_ptr_reg[3]_4\(48) => u_ddr_mc_phy_wrapper_n_1001,
      \rd_ptr_reg[3]_4\(47) => u_ddr_mc_phy_wrapper_n_1002,
      \rd_ptr_reg[3]_4\(46) => u_ddr_mc_phy_wrapper_n_1003,
      \rd_ptr_reg[3]_4\(45) => u_ddr_mc_phy_wrapper_n_1004,
      \rd_ptr_reg[3]_4\(44) => u_ddr_mc_phy_wrapper_n_1005,
      \rd_ptr_reg[3]_4\(43) => u_ddr_mc_phy_wrapper_n_1006,
      \rd_ptr_reg[3]_4\(42) => u_ddr_mc_phy_wrapper_n_1007,
      \rd_ptr_reg[3]_4\(41) => u_ddr_mc_phy_wrapper_n_1008,
      \rd_ptr_reg[3]_4\(40) => u_ddr_mc_phy_wrapper_n_1009,
      \rd_ptr_reg[3]_4\(39) => u_ddr_mc_phy_wrapper_n_1010,
      \rd_ptr_reg[3]_4\(38) => u_ddr_mc_phy_wrapper_n_1011,
      \rd_ptr_reg[3]_4\(37) => u_ddr_mc_phy_wrapper_n_1012,
      \rd_ptr_reg[3]_4\(36) => u_ddr_mc_phy_wrapper_n_1013,
      \rd_ptr_reg[3]_4\(35) => u_ddr_mc_phy_wrapper_n_1014,
      \rd_ptr_reg[3]_4\(34) => u_ddr_mc_phy_wrapper_n_1015,
      \rd_ptr_reg[3]_4\(33) => u_ddr_mc_phy_wrapper_n_1016,
      \rd_ptr_reg[3]_4\(32) => u_ddr_mc_phy_wrapper_n_1017,
      \rd_ptr_reg[3]_4\(31) => u_ddr_mc_phy_wrapper_n_1018,
      \rd_ptr_reg[3]_4\(30) => u_ddr_mc_phy_wrapper_n_1019,
      \rd_ptr_reg[3]_4\(29) => u_ddr_mc_phy_wrapper_n_1020,
      \rd_ptr_reg[3]_4\(28) => u_ddr_mc_phy_wrapper_n_1021,
      \rd_ptr_reg[3]_4\(27) => u_ddr_mc_phy_wrapper_n_1022,
      \rd_ptr_reg[3]_4\(26) => u_ddr_mc_phy_wrapper_n_1023,
      \rd_ptr_reg[3]_4\(25) => u_ddr_mc_phy_wrapper_n_1024,
      \rd_ptr_reg[3]_4\(24) => u_ddr_mc_phy_wrapper_n_1025,
      \rd_ptr_reg[3]_4\(23) => u_ddr_mc_phy_wrapper_n_1026,
      \rd_ptr_reg[3]_4\(22) => u_ddr_mc_phy_wrapper_n_1027,
      \rd_ptr_reg[3]_4\(21) => u_ddr_mc_phy_wrapper_n_1028,
      \rd_ptr_reg[3]_4\(20) => u_ddr_mc_phy_wrapper_n_1029,
      \rd_ptr_reg[3]_4\(19) => u_ddr_mc_phy_wrapper_n_1030,
      \rd_ptr_reg[3]_4\(18) => u_ddr_mc_phy_wrapper_n_1031,
      \rd_ptr_reg[3]_4\(17) => u_ddr_mc_phy_wrapper_n_1032,
      \rd_ptr_reg[3]_4\(16) => u_ddr_mc_phy_wrapper_n_1033,
      \rd_ptr_reg[3]_4\(15) => u_ddr_mc_phy_wrapper_n_1034,
      \rd_ptr_reg[3]_4\(14) => u_ddr_mc_phy_wrapper_n_1035,
      \rd_ptr_reg[3]_4\(13) => u_ddr_mc_phy_wrapper_n_1036,
      \rd_ptr_reg[3]_4\(12) => u_ddr_mc_phy_wrapper_n_1037,
      \rd_ptr_reg[3]_4\(11) => u_ddr_mc_phy_wrapper_n_1038,
      \rd_ptr_reg[3]_4\(10) => u_ddr_mc_phy_wrapper_n_1039,
      \rd_ptr_reg[3]_4\(9) => u_ddr_mc_phy_wrapper_n_1040,
      \rd_ptr_reg[3]_4\(8) => u_ddr_mc_phy_wrapper_n_1041,
      \rd_ptr_reg[3]_4\(7) => u_ddr_mc_phy_wrapper_n_1042,
      \rd_ptr_reg[3]_4\(6) => u_ddr_mc_phy_wrapper_n_1043,
      \rd_ptr_reg[3]_4\(5) => u_ddr_mc_phy_wrapper_n_1044,
      \rd_ptr_reg[3]_4\(4) => u_ddr_mc_phy_wrapper_n_1045,
      \rd_ptr_reg[3]_4\(3) => u_ddr_mc_phy_wrapper_n_1046,
      \rd_ptr_reg[3]_4\(2) => u_ddr_mc_phy_wrapper_n_1047,
      \rd_ptr_reg[3]_4\(1) => u_ddr_mc_phy_wrapper_n_1048,
      \rd_ptr_reg[3]_4\(0) => u_ddr_mc_phy_wrapper_n_1049,
      \rd_ptr_reg[3]_5\(63) => u_ddr_mc_phy_wrapper_n_1050,
      \rd_ptr_reg[3]_5\(62) => u_ddr_mc_phy_wrapper_n_1051,
      \rd_ptr_reg[3]_5\(61) => u_ddr_mc_phy_wrapper_n_1052,
      \rd_ptr_reg[3]_5\(60) => u_ddr_mc_phy_wrapper_n_1053,
      \rd_ptr_reg[3]_5\(59) => u_ddr_mc_phy_wrapper_n_1054,
      \rd_ptr_reg[3]_5\(58) => u_ddr_mc_phy_wrapper_n_1055,
      \rd_ptr_reg[3]_5\(57) => u_ddr_mc_phy_wrapper_n_1056,
      \rd_ptr_reg[3]_5\(56) => u_ddr_mc_phy_wrapper_n_1057,
      \rd_ptr_reg[3]_5\(55) => u_ddr_mc_phy_wrapper_n_1058,
      \rd_ptr_reg[3]_5\(54) => u_ddr_mc_phy_wrapper_n_1059,
      \rd_ptr_reg[3]_5\(53) => u_ddr_mc_phy_wrapper_n_1060,
      \rd_ptr_reg[3]_5\(52) => u_ddr_mc_phy_wrapper_n_1061,
      \rd_ptr_reg[3]_5\(51) => u_ddr_mc_phy_wrapper_n_1062,
      \rd_ptr_reg[3]_5\(50) => u_ddr_mc_phy_wrapper_n_1063,
      \rd_ptr_reg[3]_5\(49) => u_ddr_mc_phy_wrapper_n_1064,
      \rd_ptr_reg[3]_5\(48) => u_ddr_mc_phy_wrapper_n_1065,
      \rd_ptr_reg[3]_5\(47) => u_ddr_mc_phy_wrapper_n_1066,
      \rd_ptr_reg[3]_5\(46) => u_ddr_mc_phy_wrapper_n_1067,
      \rd_ptr_reg[3]_5\(45) => u_ddr_mc_phy_wrapper_n_1068,
      \rd_ptr_reg[3]_5\(44) => u_ddr_mc_phy_wrapper_n_1069,
      \rd_ptr_reg[3]_5\(43) => u_ddr_mc_phy_wrapper_n_1070,
      \rd_ptr_reg[3]_5\(42) => u_ddr_mc_phy_wrapper_n_1071,
      \rd_ptr_reg[3]_5\(41) => u_ddr_mc_phy_wrapper_n_1072,
      \rd_ptr_reg[3]_5\(40) => u_ddr_mc_phy_wrapper_n_1073,
      \rd_ptr_reg[3]_5\(39) => u_ddr_mc_phy_wrapper_n_1074,
      \rd_ptr_reg[3]_5\(38) => u_ddr_mc_phy_wrapper_n_1075,
      \rd_ptr_reg[3]_5\(37) => u_ddr_mc_phy_wrapper_n_1076,
      \rd_ptr_reg[3]_5\(36) => u_ddr_mc_phy_wrapper_n_1077,
      \rd_ptr_reg[3]_5\(35) => u_ddr_mc_phy_wrapper_n_1078,
      \rd_ptr_reg[3]_5\(34) => u_ddr_mc_phy_wrapper_n_1079,
      \rd_ptr_reg[3]_5\(33) => u_ddr_mc_phy_wrapper_n_1080,
      \rd_ptr_reg[3]_5\(32) => u_ddr_mc_phy_wrapper_n_1081,
      \rd_ptr_reg[3]_5\(31) => u_ddr_mc_phy_wrapper_n_1082,
      \rd_ptr_reg[3]_5\(30) => u_ddr_mc_phy_wrapper_n_1083,
      \rd_ptr_reg[3]_5\(29) => u_ddr_mc_phy_wrapper_n_1084,
      \rd_ptr_reg[3]_5\(28) => u_ddr_mc_phy_wrapper_n_1085,
      \rd_ptr_reg[3]_5\(27) => u_ddr_mc_phy_wrapper_n_1086,
      \rd_ptr_reg[3]_5\(26) => u_ddr_mc_phy_wrapper_n_1087,
      \rd_ptr_reg[3]_5\(25) => u_ddr_mc_phy_wrapper_n_1088,
      \rd_ptr_reg[3]_5\(24) => u_ddr_mc_phy_wrapper_n_1089,
      \rd_ptr_reg[3]_5\(23) => u_ddr_mc_phy_wrapper_n_1090,
      \rd_ptr_reg[3]_5\(22) => u_ddr_mc_phy_wrapper_n_1091,
      \rd_ptr_reg[3]_5\(21) => u_ddr_mc_phy_wrapper_n_1092,
      \rd_ptr_reg[3]_5\(20) => u_ddr_mc_phy_wrapper_n_1093,
      \rd_ptr_reg[3]_5\(19) => u_ddr_mc_phy_wrapper_n_1094,
      \rd_ptr_reg[3]_5\(18) => u_ddr_mc_phy_wrapper_n_1095,
      \rd_ptr_reg[3]_5\(17) => u_ddr_mc_phy_wrapper_n_1096,
      \rd_ptr_reg[3]_5\(16) => u_ddr_mc_phy_wrapper_n_1097,
      \rd_ptr_reg[3]_5\(15) => u_ddr_mc_phy_wrapper_n_1098,
      \rd_ptr_reg[3]_5\(14) => u_ddr_mc_phy_wrapper_n_1099,
      \rd_ptr_reg[3]_5\(13) => u_ddr_mc_phy_wrapper_n_1100,
      \rd_ptr_reg[3]_5\(12) => u_ddr_mc_phy_wrapper_n_1101,
      \rd_ptr_reg[3]_5\(11) => u_ddr_mc_phy_wrapper_n_1102,
      \rd_ptr_reg[3]_5\(10) => u_ddr_mc_phy_wrapper_n_1103,
      \rd_ptr_reg[3]_5\(9) => u_ddr_mc_phy_wrapper_n_1104,
      \rd_ptr_reg[3]_5\(8) => u_ddr_mc_phy_wrapper_n_1105,
      \rd_ptr_reg[3]_5\(7) => u_ddr_mc_phy_wrapper_n_1106,
      \rd_ptr_reg[3]_5\(6) => u_ddr_mc_phy_wrapper_n_1107,
      \rd_ptr_reg[3]_5\(5) => u_ddr_mc_phy_wrapper_n_1108,
      \rd_ptr_reg[3]_5\(4) => u_ddr_mc_phy_wrapper_n_1109,
      \rd_ptr_reg[3]_5\(3) => u_ddr_mc_phy_wrapper_n_1110,
      \rd_ptr_reg[3]_5\(2) => u_ddr_mc_phy_wrapper_n_1111,
      \rd_ptr_reg[3]_5\(1) => u_ddr_mc_phy_wrapper_n_1112,
      \rd_ptr_reg[3]_5\(0) => u_ddr_mc_phy_wrapper_n_1113,
      \rd_ptr_reg[3]_6\(63) => u_ddr_mc_phy_wrapper_n_1114,
      \rd_ptr_reg[3]_6\(62) => u_ddr_mc_phy_wrapper_n_1115,
      \rd_ptr_reg[3]_6\(61) => u_ddr_mc_phy_wrapper_n_1116,
      \rd_ptr_reg[3]_6\(60) => u_ddr_mc_phy_wrapper_n_1117,
      \rd_ptr_reg[3]_6\(59) => u_ddr_mc_phy_wrapper_n_1118,
      \rd_ptr_reg[3]_6\(58) => u_ddr_mc_phy_wrapper_n_1119,
      \rd_ptr_reg[3]_6\(57) => u_ddr_mc_phy_wrapper_n_1120,
      \rd_ptr_reg[3]_6\(56) => u_ddr_mc_phy_wrapper_n_1121,
      \rd_ptr_reg[3]_6\(55) => u_ddr_mc_phy_wrapper_n_1122,
      \rd_ptr_reg[3]_6\(54) => u_ddr_mc_phy_wrapper_n_1123,
      \rd_ptr_reg[3]_6\(53) => u_ddr_mc_phy_wrapper_n_1124,
      \rd_ptr_reg[3]_6\(52) => u_ddr_mc_phy_wrapper_n_1125,
      \rd_ptr_reg[3]_6\(51) => u_ddr_mc_phy_wrapper_n_1126,
      \rd_ptr_reg[3]_6\(50) => u_ddr_mc_phy_wrapper_n_1127,
      \rd_ptr_reg[3]_6\(49) => u_ddr_mc_phy_wrapper_n_1128,
      \rd_ptr_reg[3]_6\(48) => u_ddr_mc_phy_wrapper_n_1129,
      \rd_ptr_reg[3]_6\(47) => u_ddr_mc_phy_wrapper_n_1130,
      \rd_ptr_reg[3]_6\(46) => u_ddr_mc_phy_wrapper_n_1131,
      \rd_ptr_reg[3]_6\(45) => u_ddr_mc_phy_wrapper_n_1132,
      \rd_ptr_reg[3]_6\(44) => u_ddr_mc_phy_wrapper_n_1133,
      \rd_ptr_reg[3]_6\(43) => u_ddr_mc_phy_wrapper_n_1134,
      \rd_ptr_reg[3]_6\(42) => u_ddr_mc_phy_wrapper_n_1135,
      \rd_ptr_reg[3]_6\(41) => u_ddr_mc_phy_wrapper_n_1136,
      \rd_ptr_reg[3]_6\(40) => u_ddr_mc_phy_wrapper_n_1137,
      \rd_ptr_reg[3]_6\(39) => u_ddr_mc_phy_wrapper_n_1138,
      \rd_ptr_reg[3]_6\(38) => u_ddr_mc_phy_wrapper_n_1139,
      \rd_ptr_reg[3]_6\(37) => u_ddr_mc_phy_wrapper_n_1140,
      \rd_ptr_reg[3]_6\(36) => u_ddr_mc_phy_wrapper_n_1141,
      \rd_ptr_reg[3]_6\(35) => u_ddr_mc_phy_wrapper_n_1142,
      \rd_ptr_reg[3]_6\(34) => u_ddr_mc_phy_wrapper_n_1143,
      \rd_ptr_reg[3]_6\(33) => u_ddr_mc_phy_wrapper_n_1144,
      \rd_ptr_reg[3]_6\(32) => u_ddr_mc_phy_wrapper_n_1145,
      \rd_ptr_reg[3]_6\(31) => u_ddr_mc_phy_wrapper_n_1146,
      \rd_ptr_reg[3]_6\(30) => u_ddr_mc_phy_wrapper_n_1147,
      \rd_ptr_reg[3]_6\(29) => u_ddr_mc_phy_wrapper_n_1148,
      \rd_ptr_reg[3]_6\(28) => u_ddr_mc_phy_wrapper_n_1149,
      \rd_ptr_reg[3]_6\(27) => u_ddr_mc_phy_wrapper_n_1150,
      \rd_ptr_reg[3]_6\(26) => u_ddr_mc_phy_wrapper_n_1151,
      \rd_ptr_reg[3]_6\(25) => u_ddr_mc_phy_wrapper_n_1152,
      \rd_ptr_reg[3]_6\(24) => u_ddr_mc_phy_wrapper_n_1153,
      \rd_ptr_reg[3]_6\(23) => u_ddr_mc_phy_wrapper_n_1154,
      \rd_ptr_reg[3]_6\(22) => u_ddr_mc_phy_wrapper_n_1155,
      \rd_ptr_reg[3]_6\(21) => u_ddr_mc_phy_wrapper_n_1156,
      \rd_ptr_reg[3]_6\(20) => u_ddr_mc_phy_wrapper_n_1157,
      \rd_ptr_reg[3]_6\(19) => u_ddr_mc_phy_wrapper_n_1158,
      \rd_ptr_reg[3]_6\(18) => u_ddr_mc_phy_wrapper_n_1159,
      \rd_ptr_reg[3]_6\(17) => u_ddr_mc_phy_wrapper_n_1160,
      \rd_ptr_reg[3]_6\(16) => u_ddr_mc_phy_wrapper_n_1161,
      \rd_ptr_reg[3]_6\(15) => u_ddr_mc_phy_wrapper_n_1162,
      \rd_ptr_reg[3]_6\(14) => u_ddr_mc_phy_wrapper_n_1163,
      \rd_ptr_reg[3]_6\(13) => u_ddr_mc_phy_wrapper_n_1164,
      \rd_ptr_reg[3]_6\(12) => u_ddr_mc_phy_wrapper_n_1165,
      \rd_ptr_reg[3]_6\(11) => u_ddr_mc_phy_wrapper_n_1166,
      \rd_ptr_reg[3]_6\(10) => u_ddr_mc_phy_wrapper_n_1167,
      \rd_ptr_reg[3]_6\(9) => u_ddr_mc_phy_wrapper_n_1168,
      \rd_ptr_reg[3]_6\(8) => u_ddr_mc_phy_wrapper_n_1169,
      \rd_ptr_reg[3]_6\(7) => u_ddr_mc_phy_wrapper_n_1170,
      \rd_ptr_reg[3]_6\(6) => u_ddr_mc_phy_wrapper_n_1171,
      \rd_ptr_reg[3]_6\(5) => u_ddr_mc_phy_wrapper_n_1172,
      \rd_ptr_reg[3]_6\(4) => u_ddr_mc_phy_wrapper_n_1173,
      \rd_ptr_reg[3]_6\(3) => u_ddr_mc_phy_wrapper_n_1174,
      \rd_ptr_reg[3]_6\(2) => u_ddr_mc_phy_wrapper_n_1175,
      \rd_ptr_reg[3]_6\(1) => u_ddr_mc_phy_wrapper_n_1176,
      \rd_ptr_reg[3]_6\(0) => u_ddr_mc_phy_wrapper_n_1177,
      \rd_ptr_reg[3]_7\(35) => u_ddr_mc_phy_wrapper_n_1184,
      \rd_ptr_reg[3]_7\(34) => u_ddr_mc_phy_wrapper_n_1185,
      \rd_ptr_reg[3]_7\(33) => u_ddr_mc_phy_wrapper_n_1186,
      \rd_ptr_reg[3]_7\(32) => u_ddr_mc_phy_wrapper_n_1187,
      \rd_ptr_reg[3]_7\(31) => u_ddr_mc_phy_wrapper_n_1188,
      \rd_ptr_reg[3]_7\(30) => u_ddr_mc_phy_wrapper_n_1189,
      \rd_ptr_reg[3]_7\(29) => u_ddr_mc_phy_wrapper_n_1190,
      \rd_ptr_reg[3]_7\(28) => u_ddr_mc_phy_wrapper_n_1191,
      \rd_ptr_reg[3]_7\(27) => u_ddr_mc_phy_wrapper_n_1192,
      \rd_ptr_reg[3]_7\(26) => u_ddr_mc_phy_wrapper_n_1193,
      \rd_ptr_reg[3]_7\(25) => u_ddr_mc_phy_wrapper_n_1194,
      \rd_ptr_reg[3]_7\(24) => u_ddr_mc_phy_wrapper_n_1195,
      \rd_ptr_reg[3]_7\(23) => u_ddr_mc_phy_wrapper_n_1196,
      \rd_ptr_reg[3]_7\(22) => u_ddr_mc_phy_wrapper_n_1197,
      \rd_ptr_reg[3]_7\(21) => u_ddr_mc_phy_wrapper_n_1198,
      \rd_ptr_reg[3]_7\(20) => u_ddr_mc_phy_wrapper_n_1199,
      \rd_ptr_reg[3]_7\(19) => u_ddr_mc_phy_wrapper_n_1200,
      \rd_ptr_reg[3]_7\(18) => u_ddr_mc_phy_wrapper_n_1201,
      \rd_ptr_reg[3]_7\(17) => u_ddr_mc_phy_wrapper_n_1202,
      \rd_ptr_reg[3]_7\(16) => u_ddr_mc_phy_wrapper_n_1203,
      \rd_ptr_reg[3]_7\(15) => u_ddr_mc_phy_wrapper_n_1204,
      \rd_ptr_reg[3]_7\(14) => u_ddr_mc_phy_wrapper_n_1205,
      \rd_ptr_reg[3]_7\(13) => u_ddr_mc_phy_wrapper_n_1206,
      \rd_ptr_reg[3]_7\(12) => u_ddr_mc_phy_wrapper_n_1207,
      \rd_ptr_reg[3]_7\(11) => u_ddr_mc_phy_wrapper_n_1208,
      \rd_ptr_reg[3]_7\(10) => u_ddr_mc_phy_wrapper_n_1209,
      \rd_ptr_reg[3]_7\(9) => u_ddr_mc_phy_wrapper_n_1210,
      \rd_ptr_reg[3]_7\(8) => u_ddr_mc_phy_wrapper_n_1211,
      \rd_ptr_reg[3]_7\(7) => u_ddr_mc_phy_wrapper_n_1212,
      \rd_ptr_reg[3]_7\(6) => u_ddr_mc_phy_wrapper_n_1213,
      \rd_ptr_reg[3]_7\(5) => u_ddr_mc_phy_wrapper_n_1214,
      \rd_ptr_reg[3]_7\(4) => u_ddr_mc_phy_wrapper_n_1215,
      \rd_ptr_reg[3]_7\(3) => u_ddr_mc_phy_wrapper_n_1216,
      \rd_ptr_reg[3]_7\(2) => u_ddr_mc_phy_wrapper_n_1217,
      \rd_ptr_reg[3]_7\(1) => u_ddr_mc_phy_wrapper_n_1218,
      \rd_ptr_reg[3]_7\(0) => u_ddr_mc_phy_wrapper_n_1219,
      \rd_ptr_reg[3]_8\(23 downto 20) => \u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out\(75 downto 72),
      \rd_ptr_reg[3]_8\(19 downto 16) => \u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out\(67 downto 64),
      \rd_ptr_reg[3]_8\(15 downto 12) => \u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out\(55 downto 52),
      \rd_ptr_reg[3]_8\(11 downto 4) => \u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out\(47 downto 40),
      \rd_ptr_reg[3]_8\(3 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out\(35 downto 32),
      \rd_ptr_reg[3]_9\(3 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d9\(3 downto 0),
      rst_sync_r1 => rst_sync_r1,
      rst_tmp => rst_tmp,
      \rstdiv2_sync_r_reg[11]\ => \rstdiv2_sync_r_reg[11]\,
      sync_pulse => sync_pulse
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mig_mig_7series_v4_2_mem_intfc is
  port (
    app_ref_ack : out STD_LOGIC;
    app_zq_ack : out STD_LOGIC;
    \generate_maint_cmds.insert_maint_r_lcl_reg\ : out STD_LOGIC;
    accept_ns : out STD_LOGIC;
    bm_end_r1 : out STD_LOGIC;
    bm_end_r1_0 : out STD_LOGIC;
    bm_end_r1_1 : out STD_LOGIC;
    app_sr_active : out STD_LOGIC;
    ddr3_reset_n : out STD_LOGIC;
    ddr3_cas_n : out STD_LOGIC;
    ddr3_ras_n : out STD_LOGIC;
    ddr3_we_n : out STD_LOGIC;
    ddr3_addr : out STD_LOGIC_VECTOR ( 13 downto 0 );
    ddr3_ba : out STD_LOGIC_VECTOR ( 2 downto 0 );
    ddr3_cs_n : out STD_LOGIC_VECTOR ( 0 to 0 );
    ddr3_odt : out STD_LOGIC_VECTOR ( 0 to 0 );
    ddr3_cke : out STD_LOGIC_VECTOR ( 0 to 0 );
    ddr3_dm : out STD_LOGIC_VECTOR ( 7 downto 0 );
    A_rst_primitives_reg : out STD_LOGIC;
    A_rst_primitives_reg_0 : out STD_LOGIC;
    A_rst_primitives_reg_1 : out STD_LOGIC;
    A_rst_primitives_reg_2 : out STD_LOGIC;
    A_rst_primitives_reg_3 : out STD_LOGIC;
    A_rst_primitives_reg_4 : out STD_LOGIC;
    A_rst_primitives_reg_5 : out STD_LOGIC;
    A_rst_primitives_reg_6 : out STD_LOGIC;
    rst_tmp : out STD_LOGIC;
    po_cnt_dec_reg : out STD_LOGIC;
    po_cnt_dec_2 : out STD_LOGIC;
    fine_adjust_reg : out STD_LOGIC;
    new_cnt_cpt_r_reg : out STD_LOGIC;
    rdlvl_stg1_start_reg : out STD_LOGIC;
    samp_edge_cnt0_en_r : out STD_LOGIC;
    pi_cnt_dec_reg : out STD_LOGIC;
    E : out STD_LOGIC_VECTOR ( 0 to 0 );
    prbs_rdlvl_done_pulse_reg : out STD_LOGIC;
    init_calib_complete : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_5\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_6\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_5\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_6\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_5\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_6\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_5\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_6\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_5\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_6\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_5\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_6\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_5\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_6\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_5\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_6\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_5\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_6\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_5\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_6\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_5\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_6\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_5\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_6\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_5\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_6\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_5\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_6\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_5\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_6\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_5\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_6\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_5\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_6\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_5\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_6\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_5\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_6\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_5\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_6\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_5\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_6\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_5\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_6\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_5\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_6\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_5\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_6\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_5\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_6\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_5\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_6\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_5\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_6\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_5\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_6\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_5\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_6\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_5\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_6\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_5\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_6\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_5\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_6\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_5\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_6\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_5\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_6\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_5\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_6\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_5\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_6\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_5\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_6\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_5\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_6\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_5\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_6\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_5\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_6\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_5\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_6\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_5\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_6\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_5\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_6\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_5\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_6\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_5\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_6\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_5\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_6\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_5\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_6\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_5\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_6\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_5\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_6\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_5\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_6\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_5\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_6\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_5\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_6\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_5\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_6\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_5\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_6\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_5\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_6\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_5\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_6\ : out STD_LOGIC;
    req_bank_r : out STD_LOGIC_VECTOR ( 11 downto 0 );
    \req_row_r_lcl_reg[13]\ : out STD_LOGIC_VECTOR ( 19 downto 0 );
    app_rd_data_valid : out STD_LOGIC;
    \init_state_r_reg[4]\ : out STD_LOGIC;
    \pointer_ram.pointer_we\ : out STD_LOGIC;
    wr_data_en : out STD_LOGIC;
    app_rd_data_end : out STD_LOGIC;
    wr_data_addr : out STD_LOGIC_VECTOR ( 3 downto 0 );
    ddr_ck_out : out STD_LOGIC_VECTOR ( 1 downto 0 );
    ddr3_dq : inout STD_LOGIC_VECTOR ( 63 downto 0 );
    ddr3_dqs_p : inout STD_LOGIC_VECTOR ( 7 downto 0 );
    ddr3_dqs_n : inout STD_LOGIC_VECTOR ( 7 downto 0 );
    \last_master_r_reg[2]\ : in STD_LOGIC;
    \periodic_read_request.periodic_rd_r_cnt_reg\ : in STD_LOGIC;
    \periodic_rd_generation.periodic_rd_cntr1_r_reg\ : in STD_LOGIC;
    \zq_cntrl.zq_request_logic.zq_request_r_reg\ : in STD_LOGIC;
    SR : in STD_LOGIC_VECTOR ( 0 to 0 );
    app_zq_req : in STD_LOGIC;
    app_sr_req : in STD_LOGIC;
    \last_master_r_reg[2]_0\ : in STD_LOGIC;
    use_addr : in STD_LOGIC;
    cmd : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \inhbt_act_faw.inhbt_act_faw_r_reg\ : in STD_LOGIC;
    app_ref_req : in STD_LOGIC;
    mmcm_ps_clk : in STD_LOGIC;
    rst_sync_r1 : in STD_LOGIC;
    freq_refclk : in STD_LOGIC;
    mem_refclk : in STD_LOGIC;
    sync_pulse : in STD_LOGIC;
    pll_locked : in STD_LOGIC;
    cal2_if_reset_reg : in STD_LOGIC;
    CLKB0 : in STD_LOGIC;
    CLKB0_7 : in STD_LOGIC;
    CLKB0_8 : in STD_LOGIC;
    CLKB0_9 : in STD_LOGIC;
    RST0 : in STD_LOGIC;
    CLKB0_10 : in STD_LOGIC;
    CLKB0_11 : in STD_LOGIC;
    CLKB0_12 : in STD_LOGIC;
    CLKB0_13 : in STD_LOGIC;
    \rstdiv2_sync_r_reg[11]\ : in STD_LOGIC;
    iodelay_ctrl_rdy : in STD_LOGIC_VECTOR ( 0 to 0 );
    \out\ : in STD_LOGIC;
    S : in STD_LOGIC_VECTOR ( 2 downto 0 );
    row_hit_r_reg : in STD_LOGIC_VECTOR ( 0 to 0 );
    row_hit_r_reg_0 : in STD_LOGIC_VECTOR ( 0 to 0 );
    row_hit_r_reg_1 : in STD_LOGIC_VECTOR ( 0 to 0 );
    row_hit_r_reg_2 : in STD_LOGIC_VECTOR ( 0 to 0 );
    row_hit_r_reg_3 : in STD_LOGIC_VECTOR ( 0 to 0 );
    \fine_dec_cnt_reg[5]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \corse_inc_reg[6][2]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \wl_dqs_tap_count_r_reg[0][5][5]\ : in STD_LOGIC;
    first_fail_detect_reg : in STD_LOGIC;
    \rdlvl_dqs_tap_cnt_r_reg[0][0][2]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \samp_edge_cnt1_r_reg[0]\ : in STD_LOGIC;
    \FSM_onehot_cal1_state_r_reg[7]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \samples_cnt_r_reg[0]\ : in STD_LOGIC;
    \en_cnt_div4.enable_wrlvl_cnt_reg[2]\ : in STD_LOGIC;
    \victim_sel_reg[0]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \four_dec_min_limit_reg[0]\ : in STD_LOGIC;
    \idelay_tap_cnt_r_reg[0][0][4]\ : in STD_LOGIC;
    \rtp_timer_r_reg[1]\ : in STD_LOGIC;
    \complex_num_writes_reg[1]\ : in STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 575 downto 0 );
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[5]\ : in STD_LOGIC;
    rb_hit_busy_r_reg : in STD_LOGIC;
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[6]\ : in STD_LOGIC;
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[4]\ : in STD_LOGIC;
    \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[3]\ : in STD_LOGIC;
    D : in STD_LOGIC_VECTOR ( 13 downto 0 );
    ras_timer_zero_r_reg : in STD_LOGIC;
    ras_timer_zero_r_reg_0 : in STD_LOGIC;
    ras_timer_zero_r_reg_1 : in STD_LOGIC;
    \rtp_timer_r_reg[0]\ : in STD_LOGIC;
    \pi_rst_stg1_cal_r_reg[1]\ : in STD_LOGIC;
    \cmp_err_4to1.compare_err_f3_reg\ : in STD_LOGIC;
    ram_init_done_r : in STD_LOGIC;
    was_priority_reg : in STD_LOGIC;
    \req_data_buf_addr_r_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
    \req_bank_r_lcl_reg[2]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
    \req_col_r_reg[9]\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
    \fine_inc_reg[6][3]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \corse_dec_reg[7][0]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \smallest_reg[6][0]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    SS : in STD_LOGIC_VECTOR ( 0 to 0 );
    \wait_cnt_r_reg[0]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \tap_cnt_cpt_r_reg[5]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \cnt_shift_r_reg[0]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \wait_cnt_r_reg[0]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \en_cnt_div4.enable_wrlvl_cnt_reg[4]\ : in STD_LOGIC;
    \device_temp_101_reg[11]\ : in STD_LOGIC_VECTOR ( 11 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of mig_mig_7series_v4_2_mem_intfc : entity is "mig_7series_v4_2_mem_intfc";
end mig_mig_7series_v4_2_mem_intfc;

architecture STRUCTURE of mig_mig_7series_v4_2_mem_intfc is
  signal \col_mach0/p_0_in\ : STD_LOGIC;
  signal \col_mach0/read_fifo.tail_r\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal ddr_phy_top0_n_52 : STD_LOGIC;
  attribute MAX_FANOUT : string;
  attribute MAX_FANOUT of ddr_phy_top0_n_52 : signal is "50";
  attribute RTL_MAX_FANOUT : string;
  attribute RTL_MAX_FANOUT of ddr_phy_top0_n_52 : signal is "found";
  attribute syn_maxfan : string;
  attribute syn_maxfan of ddr_phy_top0_n_52 : signal is "10";
  signal ddr_phy_top0_n_53 : STD_LOGIC;
  attribute MAX_FANOUT of ddr_phy_top0_n_53 : signal is "50";
  attribute RTL_MAX_FANOUT of ddr_phy_top0_n_53 : signal is "found";
  attribute syn_maxfan of ddr_phy_top0_n_53 : signal is "10";
  signal ddr_phy_top0_n_54 : STD_LOGIC;
  attribute MAX_FANOUT of ddr_phy_top0_n_54 : signal is "50";
  attribute RTL_MAX_FANOUT of ddr_phy_top0_n_54 : signal is "found";
  attribute syn_maxfan of ddr_phy_top0_n_54 : signal is "10";
  signal ddr_phy_top0_n_55 : STD_LOGIC;
  attribute MAX_FANOUT of ddr_phy_top0_n_55 : signal is "50";
  attribute RTL_MAX_FANOUT of ddr_phy_top0_n_55 : signal is "found";
  attribute syn_maxfan of ddr_phy_top0_n_55 : signal is "10";
  signal ddr_phy_top0_n_56 : STD_LOGIC;
  signal ddr_phy_top0_n_570 : STD_LOGIC;
  signal ddr_phy_top0_n_572 : STD_LOGIC;
  signal ddr_phy_top0_n_573 : STD_LOGIC;
  signal ddr_phy_top0_n_574 : STD_LOGIC;
  signal ddr_phy_top0_n_575 : STD_LOGIC;
  signal ddr_phy_top0_n_576 : STD_LOGIC;
  signal ddr_phy_top0_n_577 : STD_LOGIC;
  signal ddr_phy_top0_n_578 : STD_LOGIC;
  signal ddr_phy_top0_n_579 : STD_LOGIC;
  signal ddr_phy_top0_n_580 : STD_LOGIC;
  signal ddr_phy_top0_n_581 : STD_LOGIC;
  signal ddr_phy_top0_n_582 : STD_LOGIC;
  signal ddr_phy_top0_n_583 : STD_LOGIC;
  signal ddr_phy_top0_n_584 : STD_LOGIC;
  signal ddr_phy_top0_n_585 : STD_LOGIC;
  signal ddr_phy_top0_n_586 : STD_LOGIC;
  signal ddr_phy_top0_n_587 : STD_LOGIC;
  signal ddr_phy_top0_n_588 : STD_LOGIC;
  signal ddr_phy_top0_n_589 : STD_LOGIC;
  signal ddr_phy_top0_n_590 : STD_LOGIC;
  signal ddr_phy_top0_n_591 : STD_LOGIC;
  signal ddr_phy_top0_n_592 : STD_LOGIC;
  signal ddr_phy_top0_n_593 : STD_LOGIC;
  signal idle : STD_LOGIC;
  signal mc0_n_124 : STD_LOGIC;
  signal mc0_n_125 : STD_LOGIC;
  signal mc0_n_126 : STD_LOGIC;
  signal mc0_n_127 : STD_LOGIC;
  signal mc0_n_128 : STD_LOGIC;
  signal mc0_n_129 : STD_LOGIC;
  signal mc0_n_130 : STD_LOGIC;
  signal mc0_n_131 : STD_LOGIC;
  signal mc0_n_132 : STD_LOGIC;
  signal mc0_n_133 : STD_LOGIC;
  signal mc0_n_134 : STD_LOGIC;
  signal mc0_n_135 : STD_LOGIC;
  signal mc0_n_136 : STD_LOGIC;
  signal mc0_n_137 : STD_LOGIC;
  signal mc0_n_138 : STD_LOGIC;
  signal mc0_n_139 : STD_LOGIC;
  signal mc0_n_140 : STD_LOGIC;
  signal mc0_n_141 : STD_LOGIC;
  signal mc_address : STD_LOGIC_VECTOR ( 41 downto 0 );
  signal mc_bank : STD_LOGIC_VECTOR ( 8 downto 0 );
  signal mc_cas_n : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal mc_cke : STD_LOGIC_VECTOR ( 3 to 3 );
  signal mc_cmd : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal mc_cs_n : STD_LOGIC_VECTOR ( 0 to 0 );
  signal mc_odt : STD_LOGIC_VECTOR ( 0 to 0 );
  signal mc_ras_n : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal mc_we_n : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal mc_wrdata_en : STD_LOGIC;
  signal mux_address : STD_LOGIC_VECTOR ( 41 downto 11 );
  signal mux_cas_n : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal mux_cs_n : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal mux_ras_n : STD_LOGIC_VECTOR ( 0 to 0 );
  signal mux_we_n : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal phy_mc_ctl_full : STD_LOGIC;
  signal phy_mc_data_full : STD_LOGIC;
  signal tempmon_sample_en : STD_LOGIC;
  signal \u_ddr_mc_phy_wrapper/u_ddr_mc_phy/of_ctl_full_v\ : STD_LOGIC_VECTOR ( 1 to 1 );
begin
ddr_phy_top0: entity work.mig_mig_7series_v4_2_ddr_phy_top
     port map (
      A_rst_primitives_reg => A_rst_primitives_reg,
      A_rst_primitives_reg_0 => A_rst_primitives_reg_0,
      A_rst_primitives_reg_1 => A_rst_primitives_reg_1,
      A_rst_primitives_reg_2 => A_rst_primitives_reg_2,
      A_rst_primitives_reg_3 => A_rst_primitives_reg_3,
      A_rst_primitives_reg_4 => A_rst_primitives_reg_4,
      A_rst_primitives_reg_5 => A_rst_primitives_reg_5,
      A_rst_primitives_reg_6 => A_rst_primitives_reg_6,
      CLKB0 => CLKB0,
      CLKB0_10 => CLKB0_10,
      CLKB0_11 => CLKB0_11,
      CLKB0_12 => CLKB0_12,
      CLKB0_13 => CLKB0_13,
      CLKB0_7 => CLKB0_7,
      CLKB0_8 => CLKB0_8,
      CLKB0_9 => CLKB0_9,
      \FSM_onehot_cal1_state_r_reg[7]\(0) => \FSM_onehot_cal1_state_r_reg[7]\(0),
      Q(575 downto 0) => Q(575 downto 0),
      RST0 => RST0,
      SR(0) => SR(0),
      SS(0) => SS(0),
      app_rd_data_valid => app_rd_data_valid,
      app_rd_data_valid_0(0) => \col_mach0/p_0_in\,
      cal2_if_reset_reg => cal2_if_reset_reg,
      \cmp_err_4to1.compare_err_f3_reg\ => \cmp_err_4to1.compare_err_f3_reg\,
      \cnt_shift_r_reg[0]\(0) => \cnt_shift_r_reg[0]\(0),
      \complex_num_writes_reg[1]\ => \complex_num_writes_reg[1]\,
      \corse_dec_reg[7][0]\(1) => \corse_dec_reg[7][0]\(0),
      \corse_dec_reg[7][0]\(0) => \smallest_reg[6][0]\(0),
      \corse_inc_reg[6][2]\(1 downto 0) => \corse_inc_reg[6][2]\(1 downto 0),
      d_in(3) => mux_address(39),
      d_in(2) => mux_address(11),
      d_in(1) => mux_address(41),
      d_in(0) => mux_address(13),
      \data_offset_1_i1_reg[0]\ => mc0_n_135,
      \data_offset_1_i1_reg[1]\ => mc0_n_134,
      \data_offset_1_i1_reg[2]\ => mc0_n_133,
      \data_offset_1_i1_reg[4]\ => mc0_n_132,
      \data_offset_1_i1_reg[5]\ => mc0_n_131,
      \data_offset_2_i1_reg[0]\ => mc0_n_141,
      \data_offset_2_i1_reg[1]\ => mc0_n_140,
      \data_offset_2_i1_reg[2]\ => mc0_n_139,
      \data_offset_2_i1_reg[4]\ => mc0_n_138,
      \data_offset_2_i1_reg[5]\ => mc0_n_137,
      ddr3_addr(13 downto 0) => ddr3_addr(13 downto 0),
      ddr3_ba(2 downto 0) => ddr3_ba(2 downto 0),
      ddr3_cas_n => ddr3_cas_n,
      ddr3_cke(0) => ddr3_cke(0),
      ddr3_cs_n(0) => ddr3_cs_n(0),
      ddr3_dm(7 downto 0) => ddr3_dm(7 downto 0),
      ddr3_dq(63 downto 0) => ddr3_dq(63 downto 0),
      ddr3_dqs_n(7 downto 0) => ddr3_dqs_n(7 downto 0),
      ddr3_dqs_p(7 downto 0) => ddr3_dqs_p(7 downto 0),
      ddr3_odt(0) => ddr3_odt(0),
      ddr3_ras_n => ddr3_ras_n,
      ddr3_reset_n => ddr3_reset_n,
      ddr3_we_n => ddr3_we_n,
      ddr_ck_out(1 downto 0) => ddr_ck_out(1 downto 0),
      \device_temp_101_reg[11]\(11 downto 0) => \device_temp_101_reg[11]\(11 downto 0),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_2\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_3\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_4\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_5\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_5\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_6\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_6\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_2\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_3\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_4\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_5\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_5\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_6\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_6\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_2\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_3\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_4\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_5\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_5\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_6\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_6\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_2\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_3\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_4\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_5\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_5\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_6\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_6\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_2\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_3\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_4\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_5\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_5\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_6\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_6\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_2\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_3\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_4\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_5\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_5\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_6\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_6\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_2\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_3\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_4\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_5\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_5\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_6\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_6\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_2\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_3\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_4\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_5\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_5\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_6\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_6\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_2\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_3\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_4\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_5\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_5\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_6\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_6\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_2\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_3\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_4\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_5\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_5\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_6\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_6\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_2\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_3\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_4\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_5\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_5\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_6\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_6\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_2\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_3\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_4\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_5\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_5\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_6\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_6\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_2\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_3\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_4\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_5\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_5\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_6\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_6\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_2\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_3\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_4\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_5\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_5\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_6\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_6\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_2\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_3\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_4\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_5\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_5\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_6\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_6\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_2\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_3\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_4\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_5\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_5\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_6\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_6\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_2\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_3\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_4\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_5\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_5\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_6\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_6\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_2\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_3\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_4\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_5\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_5\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_6\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_6\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_2\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_3\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_4\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_5\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_5\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_6\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_6\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_2\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_3\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_4\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_5\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_5\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_6\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_6\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_2\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_3\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_4\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_5\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_5\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_6\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_6\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_2\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_3\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_4\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_5\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_5\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_6\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_6\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_2\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_3\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_4\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_5\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_5\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_6\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_6\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_2\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_3\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_4\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_5\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_5\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_6\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_6\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_2\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_3\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_4\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_5\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_5\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_6\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_6\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_2\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_3\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_4\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_5\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_5\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_6\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_6\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_2\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_3\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_4\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_5\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_5\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_6\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_6\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_2\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_3\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_4\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_5\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_5\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_6\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_6\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_2\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_3\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_4\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_5\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_5\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_6\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_6\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_2\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_3\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_4\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_5\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_5\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_6\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_6\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_2\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_3\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_4\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_5\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_5\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_6\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_6\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_2\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_3\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_4\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_5\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_5\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_6\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_6\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_2\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_3\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_4\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_5\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_5\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_6\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_6\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_2\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_3\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_4\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_5\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_5\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_6\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_6\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_2\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_3\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_4\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_5\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_5\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_6\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_6\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_2\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_3\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_4\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_5\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_5\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_6\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_6\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_2\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_3\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_4\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_5\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_5\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_6\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_6\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_2\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_3\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_4\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_5\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_5\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_6\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_6\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_2\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_3\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_4\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_5\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_5\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_6\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_6\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_2\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_3\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_4\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_5\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_5\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_6\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_6\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_2\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_3\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_4\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_5\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_5\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_6\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_6\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_2\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_3\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_4\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_5\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_5\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_6\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_6\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_2\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_3\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_4\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_5\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_5\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_6\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_6\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_2\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_3\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_4\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_5\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_5\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_6\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_6\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_2\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_3\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_4\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_5\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_5\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_6\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_6\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_2\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_3\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_4\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_5\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_5\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_6\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_6\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_2\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_3\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_4\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_5\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_5\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_6\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_6\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_2\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_3\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_4\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_5\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_5\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_6\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_6\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_2\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_3\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_4\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_2\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_3\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_4\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_2\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_3\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_4\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_2\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_3\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_4\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_2\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_3\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_4\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_2\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_3\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_4\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_2\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_3\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_4\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_2\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_3\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_4\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_2\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_3\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_4\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_5\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_5\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_6\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_6\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_2\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_3\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_4\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_5\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_5\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_6\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_6\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_2\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_3\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_4\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_5\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_5\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_6\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_6\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_2\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_3\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_4\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_5\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_5\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_6\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_6\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_2\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_3\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_4\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_5\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_5\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_6\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_6\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_2\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_3\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_4\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_5\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_5\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_6\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_6\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_2\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_3\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_4\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_5\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_5\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_6\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_6\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_2\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_3\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_4\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_5\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_5\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_6\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_6\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_0\,
      \en_cnt_div4.enable_wrlvl_cnt_reg[2]\ => \en_cnt_div4.enable_wrlvl_cnt_reg[2]\,
      \en_cnt_div4.enable_wrlvl_cnt_reg[4]\ => \en_cnt_div4.enable_wrlvl_cnt_reg[4]\,
      \entry_cnt_reg[4]\ => \last_master_r_reg[2]\,
      fine_adjust_reg => fine_adjust_reg,
      \fine_dec_cnt_reg[5]\(1 downto 0) => \fine_dec_cnt_reg[5]\(1 downto 0),
      \fine_inc_reg[6][3]\(1 downto 0) => \fine_inc_reg[6][3]\(1 downto 0),
      first_fail_detect_reg => first_fail_detect_reg,
      \four_dec_min_limit_reg[0]\ => \four_dec_min_limit_reg[0]\,
      freq_refclk => freq_refclk,
      \idelay_tap_cnt_r_reg[0][0][4]\ => \idelay_tap_cnt_r_reg[0][0][4]\,
      \idelay_tap_cnt_r_reg[0][4][4]\ => \rtp_timer_r_reg[0]\,
      idle => idle,
      init_calib_complete => init_calib_complete,
      \init_calib_complete_reg_rep__12\ => ddr_phy_top0_n_52,
      \init_calib_complete_reg_rep__24\ => ddr_phy_top0_n_53,
      \init_calib_complete_reg_rep__25\ => ddr_phy_top0_n_54,
      \init_calib_complete_reg_rep__26\ => ddr_phy_top0_n_55,
      \init_calib_complete_reg_rep__26_0\ => ddr_phy_top0_n_570,
      init_complete_r1_timing_reg => ddr_phy_top0_n_56,
      \init_state_r_reg[4]\ => \init_state_r_reg[4]\,
      iodelay_ctrl_rdy(0) => iodelay_ctrl_rdy(0),
      mc_address(38 downto 25) => mc_address(41 downto 28),
      mc_address(24 downto 0) => mc_address(24 downto 0),
      mc_bank(8 downto 0) => mc_bank(8 downto 0),
      mc_cas_n(2 downto 0) => mc_cas_n(2 downto 0),
      mc_cke(0) => mc_cke(3),
      mc_cmd(1 downto 0) => mc_cmd(1 downto 0),
      mc_cs_n(0) => mc_cs_n(0),
      mc_data_offset(0) => mc0_n_124,
      mc_data_offset_1(0) => mc0_n_130,
      mc_data_offset_2(0) => mc0_n_136,
      mc_odt(0) => mc_odt(0),
      mc_ras_n(2 downto 0) => mc_ras_n(2 downto 0),
      mc_ref_zq_wip => tempmon_sample_en,
      mc_we_n(2 downto 0) => mc_we_n(2 downto 0),
      mc_wrdata_en => mc_wrdata_en,
      mem_refclk => mem_refclk,
      mmcm_ps_clk => mmcm_ps_clk,
      new_cnt_cpt_r_reg => new_cnt_cpt_r_reg,
      new_cnt_dqs_r_reg => E(0),
      \not_empty_wait_cnt_reg[4]\ => \rtp_timer_r_reg[1]\,
      of_ctl_full_v(0) => \u_ddr_mc_phy_wrapper/u_ddr_mc_phy/of_ctl_full_v\(1),
      \one_dec_max_limit_reg[2]\ => \periodic_rd_generation.periodic_rd_cntr1_r_reg\,
      \one_dec_min_limit_reg[11]\ => \zq_cntrl.zq_request_logic.zq_request_r_reg\,
      \out\ => \out\,
      \phy_ctl_wd_i1_reg[17]\ => mc0_n_129,
      \phy_ctl_wd_i1_reg[18]\ => mc0_n_128,
      \phy_ctl_wd_i1_reg[19]\ => mc0_n_127,
      \phy_ctl_wd_i1_reg[21]\ => mc0_n_126,
      \phy_ctl_wd_i1_reg[22]\ => mc0_n_125,
      phy_dout(6) => mux_we_n(2),
      phy_dout(5) => mux_we_n(0),
      phy_dout(4) => mux_cs_n(2),
      phy_dout(3) => mux_ras_n(0),
      phy_dout(2) => mux_cas_n(2),
      phy_dout(1) => mux_cas_n(0),
      phy_dout(0) => mux_cs_n(0),
      phy_mc_ctl_full => phy_mc_ctl_full,
      phy_mc_data_full => phy_mc_data_full,
      pi_cnt_dec_reg => pi_cnt_dec_reg,
      \pi_rst_stg1_cal_r_reg[1]\ => \pi_rst_stg1_cal_r_reg[1]\,
      pll_locked => pll_locked,
      po_cnt_dec_2 => po_cnt_dec_2,
      po_cnt_dec_reg => po_cnt_dec_reg,
      po_en_stg2_f_reg => \periodic_read_request.periodic_rd_r_cnt_reg\,
      prbs_rdlvl_done_pulse_reg => prbs_rdlvl_done_pulse_reg,
      \rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][0]\ => ddr_phy_top0_n_573,
      \rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][5]\(5) => ddr_phy_top0_n_574,
      \rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][5]\(4) => ddr_phy_top0_n_575,
      \rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][5]\(3) => ddr_phy_top0_n_576,
      \rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][5]\(2) => ddr_phy_top0_n_577,
      \rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][5]\(1) => ddr_phy_top0_n_578,
      \rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][5]\(0) => ddr_phy_top0_n_579,
      \rank_final_loop[0].bank_final_loop[1].final_data_offset_mc_reg[0][11]\(5) => ddr_phy_top0_n_581,
      \rank_final_loop[0].bank_final_loop[1].final_data_offset_mc_reg[0][11]\(4) => ddr_phy_top0_n_582,
      \rank_final_loop[0].bank_final_loop[1].final_data_offset_mc_reg[0][11]\(3) => ddr_phy_top0_n_583,
      \rank_final_loop[0].bank_final_loop[1].final_data_offset_mc_reg[0][11]\(2) => ddr_phy_top0_n_584,
      \rank_final_loop[0].bank_final_loop[1].final_data_offset_mc_reg[0][11]\(1) => ddr_phy_top0_n_585,
      \rank_final_loop[0].bank_final_loop[1].final_data_offset_mc_reg[0][11]\(0) => ddr_phy_top0_n_586,
      \rank_final_loop[0].bank_final_loop[1].final_data_offset_mc_reg[0][6]\ => ddr_phy_top0_n_580,
      \rank_final_loop[0].bank_final_loop[2].final_data_offset_mc_reg[0][12]\ => ddr_phy_top0_n_587,
      \rank_final_loop[0].bank_final_loop[2].final_data_offset_mc_reg[0][17]\(5) => ddr_phy_top0_n_588,
      \rank_final_loop[0].bank_final_loop[2].final_data_offset_mc_reg[0][17]\(4) => ddr_phy_top0_n_589,
      \rank_final_loop[0].bank_final_loop[2].final_data_offset_mc_reg[0][17]\(3) => ddr_phy_top0_n_590,
      \rank_final_loop[0].bank_final_loop[2].final_data_offset_mc_reg[0][17]\(2) => ddr_phy_top0_n_591,
      \rank_final_loop[0].bank_final_loop[2].final_data_offset_mc_reg[0][17]\(1) => ddr_phy_top0_n_592,
      \rank_final_loop[0].bank_final_loop[2].final_data_offset_mc_reg[0][17]\(0) => ddr_phy_top0_n_593,
      \rdlvl_dqs_tap_cnt_r_reg[0][0][2]\(1 downto 0) => \rdlvl_dqs_tap_cnt_r_reg[0][0][2]\(1 downto 0),
      rdlvl_stg1_start_reg => rdlvl_stg1_start_reg,
      \read_fifo.tail_r\(0) => \col_mach0/read_fifo.tail_r\(0),
      \read_fifo.tail_r_reg[0]\ => ddr_phy_top0_n_572,
      rst_sync_r1 => rst_sync_r1,
      rst_tmp => rst_tmp,
      \rstdiv2_sync_r_reg[11]\ => \rstdiv2_sync_r_reg[11]\,
      samp_edge_cnt0_en_r => samp_edge_cnt0_en_r,
      \samp_edge_cnt1_r_reg[0]\ => \samp_edge_cnt1_r_reg[0]\,
      \samples_cnt_r_reg[0]\ => \samples_cnt_r_reg[0]\,
      sync_pulse => sync_pulse,
      \tap_cnt_cpt_r_reg[5]\(0) => \tap_cnt_cpt_r_reg[5]\(0),
      \victim_sel_reg[0]\(0) => \victim_sel_reg[0]\(0),
      \wait_cnt_r_reg[0]\(0) => \wait_cnt_r_reg[0]\(0),
      \wait_cnt_r_reg[0]_0\(0) => \wait_cnt_r_reg[0]_0\(0),
      \wl_dqs_tap_count_r_reg[0][5][5]\ => \wl_dqs_tap_count_r_reg[0][5][5]\
    );
mc0: entity work.mig_mig_7series_v4_2_mc
     port map (
      D(13 downto 0) => D(13 downto 0),
      Q(38 downto 25) => mc_address(41 downto 28),
      Q(24 downto 0) => mc_address(24 downto 0),
      S(2 downto 0) => S(2 downto 0),
      SR(0) => SR(0),
      accept_ns => accept_ns,
      app_ref_ack => app_ref_ack,
      app_ref_req => app_ref_req,
      app_sr_active => app_sr_active,
      app_sr_req => app_sr_req,
      app_zq_ack => app_zq_ack,
      app_zq_req => app_zq_req,
      bm_end_r1 => bm_end_r1,
      bm_end_r1_0 => bm_end_r1_0,
      bm_end_r1_1 => bm_end_r1_1,
      cmd(1 downto 0) => cmd(1 downto 0),
      \cmd_pipe_plus.mc_bank_reg[8]_0\(8 downto 0) => mc_bank(8 downto 0),
      \cmd_pipe_plus.mc_data_offset_1_reg[0]_0\ => mc0_n_135,
      \cmd_pipe_plus.mc_data_offset_1_reg[0]_1\ => ddr_phy_top0_n_580,
      \cmd_pipe_plus.mc_data_offset_1_reg[1]_0\ => mc0_n_134,
      \cmd_pipe_plus.mc_data_offset_1_reg[2]_0\ => mc0_n_133,
      \cmd_pipe_plus.mc_data_offset_1_reg[3]_0\(0) => mc0_n_130,
      \cmd_pipe_plus.mc_data_offset_1_reg[4]_0\ => mc0_n_132,
      \cmd_pipe_plus.mc_data_offset_1_reg[5]_0\ => mc0_n_131,
      \cmd_pipe_plus.mc_data_offset_1_reg[5]_1\(5) => ddr_phy_top0_n_581,
      \cmd_pipe_plus.mc_data_offset_1_reg[5]_1\(4) => ddr_phy_top0_n_582,
      \cmd_pipe_plus.mc_data_offset_1_reg[5]_1\(3) => ddr_phy_top0_n_583,
      \cmd_pipe_plus.mc_data_offset_1_reg[5]_1\(2) => ddr_phy_top0_n_584,
      \cmd_pipe_plus.mc_data_offset_1_reg[5]_1\(1) => ddr_phy_top0_n_585,
      \cmd_pipe_plus.mc_data_offset_1_reg[5]_1\(0) => ddr_phy_top0_n_586,
      \cmd_pipe_plus.mc_data_offset_2_reg[0]_0\ => mc0_n_141,
      \cmd_pipe_plus.mc_data_offset_2_reg[0]_1\ => ddr_phy_top0_n_587,
      \cmd_pipe_plus.mc_data_offset_2_reg[1]_0\ => mc0_n_140,
      \cmd_pipe_plus.mc_data_offset_2_reg[2]_0\ => mc0_n_139,
      \cmd_pipe_plus.mc_data_offset_2_reg[3]_0\(0) => mc0_n_136,
      \cmd_pipe_plus.mc_data_offset_2_reg[4]_0\ => mc0_n_138,
      \cmd_pipe_plus.mc_data_offset_2_reg[5]_0\ => mc0_n_137,
      \cmd_pipe_plus.mc_data_offset_2_reg[5]_1\(5) => ddr_phy_top0_n_588,
      \cmd_pipe_plus.mc_data_offset_2_reg[5]_1\(4) => ddr_phy_top0_n_589,
      \cmd_pipe_plus.mc_data_offset_2_reg[5]_1\(3) => ddr_phy_top0_n_590,
      \cmd_pipe_plus.mc_data_offset_2_reg[5]_1\(2) => ddr_phy_top0_n_591,
      \cmd_pipe_plus.mc_data_offset_2_reg[5]_1\(1) => ddr_phy_top0_n_592,
      \cmd_pipe_plus.mc_data_offset_2_reg[5]_1\(0) => ddr_phy_top0_n_593,
      \cmd_pipe_plus.mc_data_offset_reg[0]_0\ => mc0_n_129,
      \cmd_pipe_plus.mc_data_offset_reg[0]_1\ => ddr_phy_top0_n_573,
      \cmd_pipe_plus.mc_data_offset_reg[1]_0\ => mc0_n_128,
      \cmd_pipe_plus.mc_data_offset_reg[2]_0\ => mc0_n_127,
      \cmd_pipe_plus.mc_data_offset_reg[3]_0\(0) => mc0_n_124,
      \cmd_pipe_plus.mc_data_offset_reg[4]_0\ => mc0_n_126,
      \cmd_pipe_plus.mc_data_offset_reg[5]_0\ => mc0_n_125,
      \cmd_pipe_plus.mc_data_offset_reg[5]_1\(5) => ddr_phy_top0_n_574,
      \cmd_pipe_plus.mc_data_offset_reg[5]_1\(4) => ddr_phy_top0_n_575,
      \cmd_pipe_plus.mc_data_offset_reg[5]_1\(3) => ddr_phy_top0_n_576,
      \cmd_pipe_plus.mc_data_offset_reg[5]_1\(2) => ddr_phy_top0_n_577,
      \cmd_pipe_plus.mc_data_offset_reg[5]_1\(1) => ddr_phy_top0_n_578,
      \cmd_pipe_plus.mc_data_offset_reg[5]_1\(0) => ddr_phy_top0_n_579,
      d_in(3) => mux_address(39),
      d_in(2) => mux_address(11),
      d_in(1) => mux_address(41),
      d_in(0) => mux_address(13),
      \generate_maint_cmds.insert_maint_r_lcl_reg\ => \generate_maint_cmds.insert_maint_r_lcl_reg\,
      \grant_r_reg[0]\ => ddr_phy_top0_n_55,
      idle => idle,
      \inhbt_act_faw.inhbt_act_faw_r_reg\ => \inhbt_act_faw.inhbt_act_faw_r_reg\,
      \last_master_r_reg[2]\ => \last_master_r_reg[2]\,
      \last_master_r_reg[2]_0\ => \last_master_r_reg[2]_0\,
      mc_cas_n(2 downto 0) => mc_cas_n(2 downto 0),
      mc_cke(0) => mc_cke(3),
      mc_cmd(1 downto 0) => mc_cmd(1 downto 0),
      mc_cs_n(0) => mc_cs_n(0),
      mc_odt(0) => mc_odt(0),
      mc_ras_n(2 downto 0) => mc_ras_n(2 downto 0),
      mc_ref_zq_wip => tempmon_sample_en,
      mc_we_n(2 downto 0) => mc_we_n(2 downto 0),
      mc_wrdata_en => mc_wrdata_en,
      mem_reg_0_15_36_41 => ddr_phy_top0_n_54,
      mem_reg_0_15_42_47 => ddr_phy_top0_n_53,
      of_ctl_full_v(0) => \u_ddr_mc_phy_wrapper/u_ddr_mc_phy/of_ctl_full_v\(1),
      \periodic_rd_generation.periodic_rd_cntr1_r_reg\ => \periodic_rd_generation.periodic_rd_cntr1_r_reg\,
      \periodic_rd_generation.periodic_rd_timer_r_reg[2]\ => ddr_phy_top0_n_52,
      \periodic_read_request.periodic_rd_r_cnt_reg\ => \periodic_read_request.periodic_rd_r_cnt_reg\,
      \periodic_read_request.periodic_rd_r_lcl_reg\ => ddr_phy_top0_n_570,
      phy_dout(6) => mux_we_n(2),
      phy_dout(5) => mux_we_n(0),
      phy_dout(4) => mux_cs_n(2),
      phy_dout(3) => mux_ras_n(0),
      phy_dout(2) => mux_cas_n(2),
      phy_dout(1) => mux_cas_n(0),
      phy_dout(0) => mux_cs_n(0),
      phy_mc_ctl_full => phy_mc_ctl_full,
      phy_mc_data_full => phy_mc_data_full,
      \pointer_ram.pointer_we\ => \pointer_ram.pointer_we\,
      ram_init_done_r => ram_init_done_r,
      ras_timer_zero_r_reg => ras_timer_zero_r_reg,
      ras_timer_zero_r_reg_0 => ras_timer_zero_r_reg_0,
      ras_timer_zero_r_reg_1 => ras_timer_zero_r_reg_1,
      \rb_hit_busies.rb_hit_busies_r_lcl_reg[4]\ => \rb_hit_busies.rb_hit_busies_r_lcl_reg[4]\,
      \rb_hit_busies.rb_hit_busies_r_lcl_reg[5]\ => \rb_hit_busies.rb_hit_busies_r_lcl_reg[5]\,
      \rb_hit_busies.rb_hit_busies_r_lcl_reg[6]\ => \rb_hit_busies.rb_hit_busies_r_lcl_reg[6]\,
      rb_hit_busy_r_reg => rb_hit_busy_r_reg,
      \read_fifo.fifo_out_data_r_reg[7]\(1) => app_rd_data_end,
      \read_fifo.fifo_out_data_r_reg[7]\(0) => \col_mach0/p_0_in\,
      \read_fifo.tail_r_reg[0]\(0) => \col_mach0/read_fifo.tail_r\(0),
      \read_fifo.tail_r_reg[0]_0\ => ddr_phy_top0_n_572,
      \read_fifo.tail_r_reg[2]\ => ddr_phy_top0_n_56,
      \req_bank_r_lcl_reg[2]\(2 downto 0) => req_bank_r(2 downto 0),
      \req_bank_r_lcl_reg[2]_0\(2 downto 0) => req_bank_r(5 downto 3),
      \req_bank_r_lcl_reg[2]_1\(2 downto 0) => req_bank_r(8 downto 6),
      \req_bank_r_lcl_reg[2]_2\(2 downto 0) => req_bank_r(11 downto 9),
      \req_bank_r_lcl_reg[2]_3\(2 downto 0) => \req_bank_r_lcl_reg[2]\(2 downto 0),
      \req_col_r_reg[9]\(9 downto 0) => \req_col_r_reg[9]\(9 downto 0),
      \req_data_buf_addr_r_reg[3]\(3 downto 0) => \req_data_buf_addr_r_reg[3]\(3 downto 0),
      \req_row_r_lcl_reg[13]\(19 downto 0) => \req_row_r_lcl_reg[13]\(19 downto 0),
      \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[3]\ => \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[3]\,
      row_hit_r_reg(0) => row_hit_r_reg(0),
      row_hit_r_reg_0(0) => row_hit_r_reg_0(0),
      row_hit_r_reg_1(0) => row_hit_r_reg_1(0),
      row_hit_r_reg_2(0) => row_hit_r_reg_2(0),
      row_hit_r_reg_3(0) => row_hit_r_reg_3(0),
      \rtp_timer_r_reg[0]\ => \rtp_timer_r_reg[0]\,
      \rtp_timer_r_reg[1]\ => \rtp_timer_r_reg[1]\,
      use_addr => use_addr,
      was_priority_reg => was_priority_reg,
      wr_data_addr(3 downto 0) => wr_data_addr(3 downto 0),
      wr_data_en => wr_data_en,
      \zq_cntrl.zq_request_logic.zq_request_r_reg\ => \zq_cntrl.zq_request_logic.zq_request_r_reg\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mig_mig_7series_v4_2_memc_ui_top_std is
  port (
    app_ref_ack : out STD_LOGIC;
    app_zq_ack : out STD_LOGIC;
    insert_maint_r : out STD_LOGIC;
    bm_end_r1 : out STD_LOGIC;
    bm_end_r1_0 : out STD_LOGIC;
    bm_end_r1_1 : out STD_LOGIC;
    app_sr_active : out STD_LOGIC;
    ddr3_reset_n : out STD_LOGIC;
    ddr3_cas_n : out STD_LOGIC;
    ddr3_ras_n : out STD_LOGIC;
    ddr3_we_n : out STD_LOGIC;
    ddr3_addr : out STD_LOGIC_VECTOR ( 13 downto 0 );
    ddr3_ba : out STD_LOGIC_VECTOR ( 2 downto 0 );
    ddr3_cs_n : out STD_LOGIC_VECTOR ( 0 to 0 );
    ddr3_odt : out STD_LOGIC_VECTOR ( 0 to 0 );
    ddr3_cke : out STD_LOGIC_VECTOR ( 0 to 0 );
    ddr3_dm : out STD_LOGIC_VECTOR ( 7 downto 0 );
    E : out STD_LOGIC_VECTOR ( 0 to 0 );
    app_wdf_rdy : out STD_LOGIC;
    A_rst_primitives_reg : out STD_LOGIC;
    A_rst_primitives_reg_0 : out STD_LOGIC;
    A_rst_primitives_reg_1 : out STD_LOGIC;
    A_rst_primitives_reg_2 : out STD_LOGIC;
    A_rst_primitives_reg_3 : out STD_LOGIC;
    A_rst_primitives_reg_4 : out STD_LOGIC;
    A_rst_primitives_reg_5 : out STD_LOGIC;
    A_rst_primitives_reg_6 : out STD_LOGIC;
    rst_tmp : out STD_LOGIC;
    po_cnt_dec : out STD_LOGIC;
    po_cnt_dec_2 : out STD_LOGIC;
    fine_adjust_reg : out STD_LOGIC;
    new_cnt_cpt_r_reg : out STD_LOGIC;
    rdlvl_stg1_start_reg : out STD_LOGIC;
    samp_edge_cnt0_en_r : out STD_LOGIC;
    pi_cnt_dec : out STD_LOGIC;
    new_cnt_dqs_r_reg : out STD_LOGIC;
    prbs_rdlvl_done_pulse : out STD_LOGIC;
    init_calib_complete : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_5\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_6\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_5\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_6\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_5\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_6\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_5\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_6\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_5\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_6\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_5\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_6\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_5\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_6\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_5\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_6\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_5\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_6\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_5\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_6\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_5\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_6\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_5\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_6\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_5\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_6\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_5\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_6\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_5\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_6\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_5\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_6\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_5\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_6\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_5\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_6\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_5\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_6\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_5\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_6\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_5\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_6\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_5\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_6\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_5\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_6\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_5\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_6\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_5\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_6\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_5\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_6\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_5\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_6\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_5\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_6\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_5\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_6\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_5\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_6\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_5\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_6\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_5\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_6\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_5\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_6\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_5\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_6\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_5\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_6\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_5\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_6\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_5\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_6\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_5\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_6\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_5\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_6\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_5\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_6\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_5\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_6\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_5\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_6\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_5\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_6\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_5\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_6\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_5\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_6\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_5\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_6\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_5\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_6\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_5\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_6\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_5\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_6\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_5\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_6\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_5\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_6\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_5\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_6\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_5\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_6\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_5\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_6\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_5\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_6\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_5\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_6\ : out STD_LOGIC;
    app_rd_data_valid : out STD_LOGIC;
    \init_state_r_reg[4]\ : out STD_LOGIC;
    app_rd_data_end : out STD_LOGIC;
    ddr_ck_out : out STD_LOGIC_VECTOR ( 1 downto 0 );
    ddr3_dq : inout STD_LOGIC_VECTOR ( 63 downto 0 );
    ddr3_dqs_p : inout STD_LOGIC_VECTOR ( 7 downto 0 );
    ddr3_dqs_n : inout STD_LOGIC_VECTOR ( 7 downto 0 );
    \wr_req_counter.wr_req_cnt_r_reg[0]\ : in STD_LOGIC;
    \periodic_read_request.periodic_rd_r_cnt_reg\ : in STD_LOGIC;
    \periodic_rd_generation.periodic_rd_cntr1_r_reg\ : in STD_LOGIC;
    \zq_cntrl.zq_request_logic.zq_request_r_reg\ : in STD_LOGIC;
    SR : in STD_LOGIC_VECTOR ( 0 to 0 );
    app_zq_req : in STD_LOGIC;
    app_sr_req : in STD_LOGIC;
    \last_master_r_reg[2]\ : in STD_LOGIC;
    reset_reg_0 : in STD_LOGIC;
    app_ref_req : in STD_LOGIC;
    mmcm_ps_clk : in STD_LOGIC;
    rst_sync_r1 : in STD_LOGIC;
    freq_refclk : in STD_LOGIC;
    mem_refclk : in STD_LOGIC;
    sync_pulse : in STD_LOGIC;
    pll_locked : in STD_LOGIC;
    cal2_if_reset_reg : in STD_LOGIC;
    CLKB0 : in STD_LOGIC;
    CLKB0_7 : in STD_LOGIC;
    CLKB0_8 : in STD_LOGIC;
    CLKB0_9 : in STD_LOGIC;
    RST0 : in STD_LOGIC;
    CLKB0_10 : in STD_LOGIC;
    CLKB0_11 : in STD_LOGIC;
    CLKB0_12 : in STD_LOGIC;
    CLKB0_13 : in STD_LOGIC;
    \rstdiv2_sync_r_reg[11]\ : in STD_LOGIC;
    iodelay_ctrl_rdy : in STD_LOGIC_VECTOR ( 0 to 0 );
    \out\ : in STD_LOGIC;
    \fine_dec_cnt_reg[5]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \corse_inc_reg[6][2]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \wl_dqs_tap_count_r_reg[0][5][5]\ : in STD_LOGIC;
    first_fail_detect_reg : in STD_LOGIC;
    \rdlvl_dqs_tap_cnt_r_reg[0][0][2]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \samp_edge_cnt1_r_reg[0]\ : in STD_LOGIC;
    \FSM_onehot_cal1_state_r_reg[7]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \samples_cnt_r_reg[0]\ : in STD_LOGIC;
    \en_cnt_div4.enable_wrlvl_cnt_reg[2]\ : in STD_LOGIC;
    \victim_sel_reg[0]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \four_dec_min_limit_reg[0]\ : in STD_LOGIC;
    \idelay_tap_cnt_r_reg[0][0][4]\ : in STD_LOGIC;
    \rtp_timer_r_reg[1]\ : in STD_LOGIC;
    \complex_num_writes_reg[1]\ : in STD_LOGIC;
    \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[3]\ : in STD_LOGIC;
    ras_timer_zero_r_reg : in STD_LOGIC;
    ras_timer_zero_r_reg_0 : in STD_LOGIC;
    ras_timer_zero_r_reg_1 : in STD_LOGIC;
    \rtp_timer_r_reg[0]\ : in STD_LOGIC;
    \pi_rst_stg1_cal_r_reg[1]\ : in STD_LOGIC;
    \cmp_err_4to1.compare_err_f3_reg\ : in STD_LOGIC;
    app_addr : in STD_LOGIC_VECTOR ( 26 downto 0 );
    app_cmd : in STD_LOGIC_VECTOR ( 1 downto 0 );
    app_wdf_data : in STD_LOGIC_VECTOR ( 511 downto 0 );
    app_wdf_mask : in STD_LOGIC_VECTOR ( 63 downto 0 );
    \fine_inc_reg[6][3]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \wl_dqs_tap_count_r_reg[0][6][3]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \corse_dec_reg[7][0]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    SS : in STD_LOGIC_VECTOR ( 0 to 0 );
    \wait_cnt_r_reg[0]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \tap_cnt_cpt_r_reg[5]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \cnt_shift_r_reg[0]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \wait_cnt_r_reg[0]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \en_cnt_div4.enable_wrlvl_cnt_reg[4]\ : in STD_LOGIC;
    D : in STD_LOGIC_VECTOR ( 11 downto 0 );
    app_en : in STD_LOGIC;
    app_wdf_wren : in STD_LOGIC;
    app_wdf_end : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of mig_mig_7series_v4_2_memc_ui_top_std : entity is "mig_7series_v4_2_memc_ui_top_std";
end mig_mig_7series_v4_2_memc_ui_top_std;

architecture STRUCTURE of mig_mig_7series_v4_2_memc_ui_top_std is
  signal \^e\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal accept_ns : STD_LOGIC;
  signal bank : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal cmd : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal col : STD_LOGIC_VECTOR ( 9 downto 0 );
  signal data_buf_addr : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \mc0/bank_mach0/req_bank_r\ : STD_LOGIC_VECTOR ( 11 downto 0 );
  signal \mc0/bank_mach0/req_row_r\ : STD_LOGIC_VECTOR ( 55 downto 0 );
  signal ram_init_done_r : STD_LOGIC;
  signal reset_reg_n_0 : STD_LOGIC;
  signal row : STD_LOGIC_VECTOR ( 13 downto 0 );
  signal u_ui_top_n_18 : STD_LOGIC;
  signal u_ui_top_n_19 : STD_LOGIC;
  signal u_ui_top_n_20 : STD_LOGIC;
  signal u_ui_top_n_21 : STD_LOGIC;
  signal u_ui_top_n_22 : STD_LOGIC;
  signal u_ui_top_n_23 : STD_LOGIC;
  signal u_ui_top_n_24 : STD_LOGIC;
  signal u_ui_top_n_25 : STD_LOGIC;
  signal u_ui_top_n_29 : STD_LOGIC;
  signal u_ui_top_n_3 : STD_LOGIC;
  signal u_ui_top_n_30 : STD_LOGIC;
  signal u_ui_top_n_31 : STD_LOGIC;
  signal \ui_wr_data0/pointer_ram.pointer_we\ : STD_LOGIC;
  signal use_addr : STD_LOGIC;
  signal wr_data : STD_LOGIC_VECTOR ( 511 downto 0 );
  signal wr_data_addr : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal wr_data_en : STD_LOGIC;
  signal wr_data_mask : STD_LOGIC_VECTOR ( 63 downto 0 );
  attribute syn_maxfan : string;
  attribute syn_maxfan of reset_reg : label is "10";
begin
  E(0) <= \^e\(0);
mem_intfc0: entity work.mig_mig_7series_v4_2_mem_intfc
     port map (
      A_rst_primitives_reg => A_rst_primitives_reg,
      A_rst_primitives_reg_0 => A_rst_primitives_reg_0,
      A_rst_primitives_reg_1 => A_rst_primitives_reg_1,
      A_rst_primitives_reg_2 => A_rst_primitives_reg_2,
      A_rst_primitives_reg_3 => A_rst_primitives_reg_3,
      A_rst_primitives_reg_4 => A_rst_primitives_reg_4,
      A_rst_primitives_reg_5 => A_rst_primitives_reg_5,
      A_rst_primitives_reg_6 => A_rst_primitives_reg_6,
      CLKB0 => CLKB0,
      CLKB0_10 => CLKB0_10,
      CLKB0_11 => CLKB0_11,
      CLKB0_12 => CLKB0_12,
      CLKB0_13 => CLKB0_13,
      CLKB0_7 => CLKB0_7,
      CLKB0_8 => CLKB0_8,
      CLKB0_9 => CLKB0_9,
      D(13 downto 0) => row(13 downto 0),
      E(0) => new_cnt_dqs_r_reg,
      \FSM_onehot_cal1_state_r_reg[7]\(0) => \FSM_onehot_cal1_state_r_reg[7]\(0),
      Q(575 downto 512) => wr_data_mask(63 downto 0),
      Q(511 downto 0) => wr_data(511 downto 0),
      RST0 => RST0,
      S(2) => u_ui_top_n_21,
      S(1) => u_ui_top_n_22,
      S(0) => u_ui_top_n_23,
      SR(0) => SR(0),
      SS(0) => SS(0),
      accept_ns => accept_ns,
      app_rd_data_end => app_rd_data_end,
      app_rd_data_valid => app_rd_data_valid,
      app_ref_ack => app_ref_ack,
      app_ref_req => app_ref_req,
      app_sr_active => app_sr_active,
      app_sr_req => app_sr_req,
      app_zq_ack => app_zq_ack,
      app_zq_req => app_zq_req,
      bm_end_r1 => bm_end_r1,
      bm_end_r1_0 => bm_end_r1_0,
      bm_end_r1_1 => bm_end_r1_1,
      cal2_if_reset_reg => cal2_if_reset_reg,
      cmd(1 downto 0) => cmd(1 downto 0),
      \cmp_err_4to1.compare_err_f3_reg\ => \cmp_err_4to1.compare_err_f3_reg\,
      \cnt_shift_r_reg[0]\(0) => \cnt_shift_r_reg[0]\(0),
      \complex_num_writes_reg[1]\ => \complex_num_writes_reg[1]\,
      \corse_dec_reg[7][0]\(0) => \corse_dec_reg[7][0]\(0),
      \corse_inc_reg[6][2]\(1 downto 0) => \corse_inc_reg[6][2]\(1 downto 0),
      ddr3_addr(13 downto 0) => ddr3_addr(13 downto 0),
      ddr3_ba(2 downto 0) => ddr3_ba(2 downto 0),
      ddr3_cas_n => ddr3_cas_n,
      ddr3_cke(0) => ddr3_cke(0),
      ddr3_cs_n(0) => ddr3_cs_n(0),
      ddr3_dm(7 downto 0) => ddr3_dm(7 downto 0),
      ddr3_dq(63 downto 0) => ddr3_dq(63 downto 0),
      ddr3_dqs_n(7 downto 0) => ddr3_dqs_n(7 downto 0),
      ddr3_dqs_p(7 downto 0) => ddr3_dqs_p(7 downto 0),
      ddr3_odt(0) => ddr3_odt(0),
      ddr3_ras_n => ddr3_ras_n,
      ddr3_reset_n => ddr3_reset_n,
      ddr3_we_n => ddr3_we_n,
      ddr_ck_out(1 downto 0) => ddr_ck_out(1 downto 0),
      \device_temp_101_reg[11]\(11 downto 0) => D(11 downto 0),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_2\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_3\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_4\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_5\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_5\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_6\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_6\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_2\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_3\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_4\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_5\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_5\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_6\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_6\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_2\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_3\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_4\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_5\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_5\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_6\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_6\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_2\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_3\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_4\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_5\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_5\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_6\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_6\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_2\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_3\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_4\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_5\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_5\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_6\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_6\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_2\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_3\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_4\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_5\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_5\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_6\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_6\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_2\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_3\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_4\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_5\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_5\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_6\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_6\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_2\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_3\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_4\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_5\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_5\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_6\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_6\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_2\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_3\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_4\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_5\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_5\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_6\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_6\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_2\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_3\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_4\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_5\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_5\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_6\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_6\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_2\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_3\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_4\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_5\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_5\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_6\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_6\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_2\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_3\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_4\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_5\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_5\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_6\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_6\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_2\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_3\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_4\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_5\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_5\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_6\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_6\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_2\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_3\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_4\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_5\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_5\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_6\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_6\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_2\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_3\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_4\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_5\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_5\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_6\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_6\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_2\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_3\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_4\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_5\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_5\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_6\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_6\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_2\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_3\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_4\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_5\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_5\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_6\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_6\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_2\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_3\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_4\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_5\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_5\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_6\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_6\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_2\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_3\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_4\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_5\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_5\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_6\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_6\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_2\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_3\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_4\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_5\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_5\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_6\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_6\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_2\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_3\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_4\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_5\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_5\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_6\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_6\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_2\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_3\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_4\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_5\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_5\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_6\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_6\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_2\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_3\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_4\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_5\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_5\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_6\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_6\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_2\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_3\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_4\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_5\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_5\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_6\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_6\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_2\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_3\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_4\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_5\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_5\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_6\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_6\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_2\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_3\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_4\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_5\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_5\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_6\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_6\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_2\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_3\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_4\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_5\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_5\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_6\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_6\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_2\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_3\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_4\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_5\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_5\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_6\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_6\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_2\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_3\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_4\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_5\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_5\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_6\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_6\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_2\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_3\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_4\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_5\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_5\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_6\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_6\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_2\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_3\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_4\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_5\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_5\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_6\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_6\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_2\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_3\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_4\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_5\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_5\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_6\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_6\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_2\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_3\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_4\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_5\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_5\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_6\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_6\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_2\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_3\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_4\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_5\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_5\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_6\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_6\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_2\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_3\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_4\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_5\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_5\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_6\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_6\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_2\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_3\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_4\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_5\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_5\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_6\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_6\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_2\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_3\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_4\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_5\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_5\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_6\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_6\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_2\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_3\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_4\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_5\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_5\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_6\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_6\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_2\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_3\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_4\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_5\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_5\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_6\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_6\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_2\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_3\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_4\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_5\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_5\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_6\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_6\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_2\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_3\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_4\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_5\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_5\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_6\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_6\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_2\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_3\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_4\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_5\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_5\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_6\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_6\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_2\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_3\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_4\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_5\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_5\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_6\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_6\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_2\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_3\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_4\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_5\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_5\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_6\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_6\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_2\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_3\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_4\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_5\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_5\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_6\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_6\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_2\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_3\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_4\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_5\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_5\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_6\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_6\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_2\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_3\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_4\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_5\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_5\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_6\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_6\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_2\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_3\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_4\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_5\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_5\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_6\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_6\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_2\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_3\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_4\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_2\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_3\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_4\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_2\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_3\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_4\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_2\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_3\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_4\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_2\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_3\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_4\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_2\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_3\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_4\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_2\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_3\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_4\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_2\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_3\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_4\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_2\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_3\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_4\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_5\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_5\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_6\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_6\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_2\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_3\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_4\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_5\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_5\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_6\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_6\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_2\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_3\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_4\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_5\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_5\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_6\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_6\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_2\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_3\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_4\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_5\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_5\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_6\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_6\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_2\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_3\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_4\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_5\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_5\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_6\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_6\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_2\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_3\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_4\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_5\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_5\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_6\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_6\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_2\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_3\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_4\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_5\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_5\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_6\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_6\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_2\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_3\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_4\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_5\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_5\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_6\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_6\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_0\,
      \en_cnt_div4.enable_wrlvl_cnt_reg[2]\ => \en_cnt_div4.enable_wrlvl_cnt_reg[2]\,
      \en_cnt_div4.enable_wrlvl_cnt_reg[4]\ => \en_cnt_div4.enable_wrlvl_cnt_reg[4]\,
      fine_adjust_reg => fine_adjust_reg,
      \fine_dec_cnt_reg[5]\(1 downto 0) => \fine_dec_cnt_reg[5]\(1 downto 0),
      \fine_inc_reg[6][3]\(1) => \fine_inc_reg[6][3]\(0),
      \fine_inc_reg[6][3]\(0) => \wl_dqs_tap_count_r_reg[0][6][3]\(1),
      first_fail_detect_reg => first_fail_detect_reg,
      \four_dec_min_limit_reg[0]\ => \four_dec_min_limit_reg[0]\,
      freq_refclk => freq_refclk,
      \generate_maint_cmds.insert_maint_r_lcl_reg\ => insert_maint_r,
      \idelay_tap_cnt_r_reg[0][0][4]\ => \idelay_tap_cnt_r_reg[0][0][4]\,
      \inhbt_act_faw.inhbt_act_faw_r_reg\ => reset_reg_0,
      init_calib_complete => init_calib_complete,
      \init_state_r_reg[4]\ => \init_state_r_reg[4]\,
      iodelay_ctrl_rdy(0) => iodelay_ctrl_rdy(0),
      \last_master_r_reg[2]\ => \wr_req_counter.wr_req_cnt_r_reg[0]\,
      \last_master_r_reg[2]_0\ => \last_master_r_reg[2]\,
      mem_refclk => mem_refclk,
      mmcm_ps_clk => mmcm_ps_clk,
      new_cnt_cpt_r_reg => new_cnt_cpt_r_reg,
      \out\ => \out\,
      \periodic_rd_generation.periodic_rd_cntr1_r_reg\ => \periodic_rd_generation.periodic_rd_cntr1_r_reg\,
      \periodic_read_request.periodic_rd_r_cnt_reg\ => \periodic_read_request.periodic_rd_r_cnt_reg\,
      pi_cnt_dec_reg => pi_cnt_dec,
      \pi_rst_stg1_cal_r_reg[1]\ => \pi_rst_stg1_cal_r_reg[1]\,
      pll_locked => pll_locked,
      po_cnt_dec_2 => po_cnt_dec_2,
      po_cnt_dec_reg => po_cnt_dec,
      \pointer_ram.pointer_we\ => \ui_wr_data0/pointer_ram.pointer_we\,
      prbs_rdlvl_done_pulse_reg => prbs_rdlvl_done_pulse,
      ram_init_done_r => ram_init_done_r,
      ras_timer_zero_r_reg => ras_timer_zero_r_reg,
      ras_timer_zero_r_reg_0 => ras_timer_zero_r_reg_0,
      ras_timer_zero_r_reg_1 => ras_timer_zero_r_reg_1,
      \rb_hit_busies.rb_hit_busies_r_lcl_reg[4]\ => u_ui_top_n_25,
      \rb_hit_busies.rb_hit_busies_r_lcl_reg[5]\ => u_ui_top_n_29,
      \rb_hit_busies.rb_hit_busies_r_lcl_reg[6]\ => u_ui_top_n_30,
      rb_hit_busy_r_reg => u_ui_top_n_31,
      \rdlvl_dqs_tap_cnt_r_reg[0][0][2]\(1 downto 0) => \rdlvl_dqs_tap_cnt_r_reg[0][0][2]\(1 downto 0),
      rdlvl_stg1_start_reg => rdlvl_stg1_start_reg,
      req_bank_r(11 downto 0) => \mc0/bank_mach0/req_bank_r\(11 downto 0),
      \req_bank_r_lcl_reg[2]\(2 downto 0) => bank(2 downto 0),
      \req_col_r_reg[9]\(9 downto 0) => col(9 downto 0),
      \req_data_buf_addr_r_reg[3]\(3 downto 0) => data_buf_addr(3 downto 0),
      \req_row_r_lcl_reg[13]\(19 downto 18) => \mc0/bank_mach0/req_row_r\(55 downto 54),
      \req_row_r_lcl_reg[13]\(17 downto 16) => \mc0/bank_mach0/req_row_r\(41 downto 40),
      \req_row_r_lcl_reg[13]\(15 downto 11) => \mc0/bank_mach0/req_row_r\(27 downto 23),
      \req_row_r_lcl_reg[13]\(10 downto 9) => \mc0/bank_mach0/req_row_r\(13 downto 12),
      \req_row_r_lcl_reg[13]\(8 downto 0) => \mc0/bank_mach0/req_row_r\(8 downto 0),
      \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[3]\ => \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[3]\,
      row_hit_r_reg(0) => u_ui_top_n_3,
      row_hit_r_reg_0(0) => u_ui_top_n_24,
      row_hit_r_reg_1(0) => u_ui_top_n_18,
      row_hit_r_reg_2(0) => u_ui_top_n_19,
      row_hit_r_reg_3(0) => u_ui_top_n_20,
      rst_sync_r1 => rst_sync_r1,
      rst_tmp => rst_tmp,
      \rstdiv2_sync_r_reg[11]\ => \rstdiv2_sync_r_reg[11]\,
      \rtp_timer_r_reg[0]\ => \rtp_timer_r_reg[0]\,
      \rtp_timer_r_reg[1]\ => \rtp_timer_r_reg[1]\,
      samp_edge_cnt0_en_r => samp_edge_cnt0_en_r,
      \samp_edge_cnt1_r_reg[0]\ => \samp_edge_cnt1_r_reg[0]\,
      \samples_cnt_r_reg[0]\ => \samples_cnt_r_reg[0]\,
      \smallest_reg[6][0]\(0) => \wl_dqs_tap_count_r_reg[0][6][3]\(0),
      sync_pulse => sync_pulse,
      \tap_cnt_cpt_r_reg[5]\(0) => \tap_cnt_cpt_r_reg[5]\(0),
      use_addr => use_addr,
      \victim_sel_reg[0]\(0) => \victim_sel_reg[0]\(0),
      \wait_cnt_r_reg[0]\(0) => \wait_cnt_r_reg[0]\(0),
      \wait_cnt_r_reg[0]_0\(0) => \wait_cnt_r_reg[0]_0\(0),
      was_priority_reg => \^e\(0),
      \wl_dqs_tap_count_r_reg[0][5][5]\ => \wl_dqs_tap_count_r_reg[0][5][5]\,
      wr_data_addr(3 downto 0) => wr_data_addr(3 downto 0),
      wr_data_en => wr_data_en,
      \zq_cntrl.zq_request_logic.zq_request_r_reg\ => \zq_cntrl.zq_request_logic.zq_request_r_reg\
    );
reset_reg: unisim.vcomponents.FDRE
     port map (
      C => \wr_req_counter.wr_req_cnt_r_reg[0]\,
      CE => '1',
      D => reset_reg_0,
      Q => reset_reg_n_0,
      R => '0'
    );
u_ui_top: entity work.mig_mig_7series_v4_2_ui_top
     port map (
      D(13 downto 0) => row(13 downto 0),
      E(0) => wr_data_en,
      Q(575 downto 512) => wr_data_mask(63 downto 0),
      Q(511 downto 0) => wr_data(511 downto 0),
      S(2) => u_ui_top_n_21,
      S(1) => u_ui_top_n_22,
      S(0) => u_ui_top_n_23,
      accept_ns => accept_ns,
      app_addr(26 downto 0) => app_addr(26 downto 0),
      \app_addr_r1_reg[23]\(0) => u_ui_top_n_3,
      \app_addr_r1_reg[23]_0\(0) => u_ui_top_n_18,
      \app_addr_r1_reg[23]_1\(0) => u_ui_top_n_19,
      \app_addr_r1_reg[23]_2\(0) => u_ui_top_n_20,
      \app_addr_r1_reg[26]\(2 downto 0) => bank(2 downto 0),
      \app_addr_r1_reg[9]\(9 downto 0) => col(9 downto 0),
      app_cmd(1 downto 0) => app_cmd(1 downto 0),
      app_en => app_en,
      app_rdy_r_reg => \^e\(0),
      app_wdf_data(511 downto 0) => app_wdf_data(511 downto 0),
      app_wdf_end => app_wdf_end,
      app_wdf_mask(63 downto 0) => app_wdf_mask(63 downto 0),
      app_wdf_rdy => app_wdf_rdy,
      app_wdf_wren => app_wdf_wren,
      cmd(1 downto 0) => cmd(1 downto 0),
      \pointer_ram.pointer_we\ => \ui_wr_data0/pointer_ram.pointer_we\,
      ram_init_done_r => ram_init_done_r,
      req_bank_r(11 downto 0) => \mc0/bank_mach0/req_bank_r\(11 downto 0),
      \req_bank_r_lcl_reg[0]\ => u_ui_top_n_25,
      \req_bank_r_lcl_reg[0]_0\ => u_ui_top_n_29,
      \req_bank_r_lcl_reg[2]\ => u_ui_top_n_30,
      \req_bank_r_lcl_reg[2]_0\ => u_ui_top_n_31,
      \req_row_r_lcl_reg[10]\(0) => u_ui_top_n_24,
      reset_reg(3 downto 0) => data_buf_addr(3 downto 0),
      row_hit_r_reg(19 downto 18) => \mc0/bank_mach0/req_row_r\(55 downto 54),
      row_hit_r_reg(17 downto 16) => \mc0/bank_mach0/req_row_r\(41 downto 40),
      row_hit_r_reg(15 downto 11) => \mc0/bank_mach0/req_row_r\(27 downto 23),
      row_hit_r_reg(10 downto 9) => \mc0/bank_mach0/req_row_r\(13 downto 12),
      row_hit_r_reg(8 downto 0) => \mc0/bank_mach0/req_row_r\(8 downto 0),
      use_addr => use_addr,
      wr_data_addr(3 downto 0) => wr_data_addr(3 downto 0),
      \wr_req_counter.wr_req_cnt_r_reg[0]\ => \wr_req_counter.wr_req_cnt_r_reg[0]\,
      \wr_req_counter.wr_req_cnt_r_reg[0]_0\ => reset_reg_n_0
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mig_mig_mig is
  port (
    \gen_mmcm.mmcm_i\ : out STD_LOGIC;
    app_ref_ack : out STD_LOGIC;
    app_zq_ack : out STD_LOGIC;
    app_sr_active : out STD_LOGIC;
    ddr3_reset_n : out STD_LOGIC;
    ddr3_cas_n : out STD_LOGIC;
    ddr3_ras_n : out STD_LOGIC;
    ddr3_we_n : out STD_LOGIC;
    ddr3_addr : out STD_LOGIC_VECTOR ( 13 downto 0 );
    ddr3_ba : out STD_LOGIC_VECTOR ( 2 downto 0 );
    ddr3_cs_n : out STD_LOGIC_VECTOR ( 0 to 0 );
    ddr3_odt : out STD_LOGIC_VECTOR ( 0 to 0 );
    ddr3_cke : out STD_LOGIC_VECTOR ( 0 to 0 );
    ddr3_dm : out STD_LOGIC_VECTOR ( 7 downto 0 );
    app_rdy_r_reg : out STD_LOGIC;
    app_wdf_rdy : out STD_LOGIC;
    rstdiv0_sync_r1_reg_rep : out STD_LOGIC;
    \out\ : out STD_LOGIC_VECTOR ( 11 downto 0 );
    iserdes_clk : out STD_LOGIC;
    iserdes_clk_0 : out STD_LOGIC;
    iserdes_clk_1 : out STD_LOGIC;
    iserdes_clk_2 : out STD_LOGIC;
    iserdes_clk_3 : out STD_LOGIC;
    iserdes_clk_4 : out STD_LOGIC;
    iserdes_clk_5 : out STD_LOGIC;
    iserdes_clk_6 : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_5\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_6\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_5\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_6\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_5\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_6\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_5\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_6\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_5\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_6\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_5\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_6\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_5\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_6\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_5\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_6\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_5\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_6\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_5\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_6\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_5\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_6\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_5\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_6\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_5\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_6\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_5\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_6\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_5\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_6\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_5\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_6\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_5\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_6\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_5\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_6\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_5\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_6\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_5\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_6\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_5\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_6\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_5\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_6\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_5\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_6\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_5\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_6\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_5\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_6\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_5\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_6\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_5\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_6\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_5\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_6\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_5\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_6\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_5\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_6\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_5\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_6\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_5\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_6\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_5\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_6\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_5\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_6\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_5\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_6\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_5\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_6\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_5\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_6\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_5\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_6\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_5\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_6\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_5\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_6\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_5\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_6\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_5\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_6\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_5\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_6\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_5\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_6\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_5\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_6\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_5\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_6\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_5\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_6\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_5\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_6\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_5\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_6\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_5\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_6\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_5\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_6\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_5\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_6\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_5\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_6\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_5\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_6\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_5\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_6\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_5\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_6\ : out STD_LOGIC;
    app_rd_data_end : out STD_LOGIC;
    init_calib_complete : out STD_LOGIC;
    app_rd_data_valid : out STD_LOGIC;
    ddr_ck_out : out STD_LOGIC_VECTOR ( 1 downto 0 );
    ddr3_dq : inout STD_LOGIC_VECTOR ( 63 downto 0 );
    ddr3_dqs_p : inout STD_LOGIC_VECTOR ( 7 downto 0 );
    ddr3_dqs_n : inout STD_LOGIC_VECTOR ( 7 downto 0 );
    sys_clk_p : in STD_LOGIC;
    sys_clk_n : in STD_LOGIC;
    app_zq_req : in STD_LOGIC;
    app_sr_req : in STD_LOGIC;
    app_ref_req : in STD_LOGIC;
    clk_ref_i : in STD_LOGIC;
    sys_rst : in STD_LOGIC;
    CLKB0 : in STD_LOGIC;
    CLKB0_7 : in STD_LOGIC;
    CLKB0_8 : in STD_LOGIC;
    CLKB0_9 : in STD_LOGIC;
    CLKB0_10 : in STD_LOGIC;
    CLKB0_11 : in STD_LOGIC;
    CLKB0_12 : in STD_LOGIC;
    CLKB0_13 : in STD_LOGIC;
    app_addr : in STD_LOGIC_VECTOR ( 26 downto 0 );
    app_cmd : in STD_LOGIC_VECTOR ( 1 downto 0 );
    app_wdf_data : in STD_LOGIC_VECTOR ( 511 downto 0 );
    app_wdf_mask : in STD_LOGIC_VECTOR ( 63 downto 0 );
    app_en : in STD_LOGIC;
    app_wdf_wren : in STD_LOGIC;
    app_wdf_end : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of mig_mig_mig : entity is "mig_mig";
end mig_mig_mig;

architecture STRUCTURE of mig_mig_mig is
  signal freq_refclk : STD_LOGIC;
  signal \^gen_mmcm.mmcm_i\ : STD_LOGIC;
  signal iodelay_ctrl_rdy : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/cnt_shift_r0\ : STD_LOGIC;
  signal \mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/idelay_tap_limit_r0\ : STD_LOGIC;
  signal \mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/pi_cnt_dec\ : STD_LOGIC;
  signal \mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/samp_edge_cnt0_en_r\ : STD_LOGIC;
  signal \mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_tempmon_0/device_temp_100\ : STD_LOGIC_VECTOR ( 11 downto 0 );
  signal \mem_intfc0/ddr_phy_top0/u_ddr_calib_top/mb_wrlvl_inst.u_ddr_phy_ck_addr_cmd_delay/po_cnt_dec\ : STD_LOGIC;
  signal \mem_intfc0/ddr_phy_top0/u_ddr_calib_top/mb_wrlvl_inst.u_ddr_phy_wrlvl/po_cnt_dec\ : STD_LOGIC;
  signal \mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/prbs_rdlvl_done_pulse\ : STD_LOGIC;
  signal \mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/RST0\ : STD_LOGIC;
  signal \mem_intfc0/mc0/bank_mach0/bank_cntrl[1].bank0/bank_state0/bm_end_r1\ : STD_LOGIC;
  signal \mem_intfc0/mc0/bank_mach0/bank_cntrl[2].bank0/bank_state0/bm_end_r1\ : STD_LOGIC;
  signal \mem_intfc0/mc0/bank_mach0/bank_cntrl[3].bank0/bank_state0/bm_end_r1\ : STD_LOGIC;
  signal \mem_intfc0/mc0/bank_mach0/insert_maint_r\ : STD_LOGIC;
  signal mem_refclk : STD_LOGIC;
  signal mmcm_clk : STD_LOGIC;
  signal mmcm_ps_clk : STD_LOGIC;
  signal pll_locked : STD_LOGIC;
  signal rst_sync_r1 : STD_LOGIC;
  attribute MAX_FANOUT : string;
  attribute MAX_FANOUT of rst_sync_r1 : signal is "10";
  attribute RTL_MAX_FANOUT : string;
  attribute RTL_MAX_FANOUT of rst_sync_r1 : signal is "found";
  attribute syn_maxfan : string;
  attribute syn_maxfan of rst_sync_r1 : signal is "10";
  signal rst_tmp : STD_LOGIC;
  signal \^rstdiv0_sync_r1_reg_rep\ : STD_LOGIC;
  signal sync_pulse : STD_LOGIC;
  signal sys_rst_act_hi : STD_LOGIC;
  signal sys_rst_o : STD_LOGIC;
  signal u_ddr3_infrastructure_n_0 : STD_LOGIC;
  signal u_ddr3_infrastructure_n_10 : STD_LOGIC;
  signal u_ddr3_infrastructure_n_11 : STD_LOGIC;
  signal u_ddr3_infrastructure_n_12 : STD_LOGIC;
  signal u_ddr3_infrastructure_n_13 : STD_LOGIC;
  signal u_ddr3_infrastructure_n_14 : STD_LOGIC;
  signal u_ddr3_infrastructure_n_15 : STD_LOGIC;
  signal u_ddr3_infrastructure_n_16 : STD_LOGIC;
  signal u_ddr3_infrastructure_n_17 : STD_LOGIC;
  signal u_ddr3_infrastructure_n_18 : STD_LOGIC;
  signal u_ddr3_infrastructure_n_19 : STD_LOGIC;
  signal u_ddr3_infrastructure_n_20 : STD_LOGIC;
  signal u_ddr3_infrastructure_n_21 : STD_LOGIC;
  signal u_ddr3_infrastructure_n_22 : STD_LOGIC;
  signal u_ddr3_infrastructure_n_23 : STD_LOGIC;
  signal u_ddr3_infrastructure_n_24 : STD_LOGIC;
  signal u_ddr3_infrastructure_n_25 : STD_LOGIC;
  signal u_ddr3_infrastructure_n_26 : STD_LOGIC;
  signal u_ddr3_infrastructure_n_27 : STD_LOGIC;
  signal u_ddr3_infrastructure_n_28 : STD_LOGIC;
  signal u_ddr3_infrastructure_n_29 : STD_LOGIC;
  signal u_ddr3_infrastructure_n_30 : STD_LOGIC;
  signal u_ddr3_infrastructure_n_31 : STD_LOGIC;
  signal u_ddr3_infrastructure_n_32 : STD_LOGIC;
  signal u_ddr3_infrastructure_n_33 : STD_LOGIC;
  signal u_ddr3_infrastructure_n_36 : STD_LOGIC;
  signal u_ddr3_infrastructure_n_37 : STD_LOGIC;
  signal u_ddr3_infrastructure_n_38 : STD_LOGIC;
  signal u_ddr3_infrastructure_n_39 : STD_LOGIC;
  signal u_ddr3_infrastructure_n_40 : STD_LOGIC;
  signal u_ddr3_infrastructure_n_41 : STD_LOGIC;
  signal u_ddr3_infrastructure_n_42 : STD_LOGIC;
  signal u_ddr3_infrastructure_n_45 : STD_LOGIC;
  signal u_ddr3_infrastructure_n_46 : STD_LOGIC;
  signal u_ddr3_infrastructure_n_47 : STD_LOGIC;
  signal u_ddr3_infrastructure_n_48 : STD_LOGIC;
  signal u_ddr3_infrastructure_n_49 : STD_LOGIC;
  signal u_ddr3_infrastructure_n_8 : STD_LOGIC;
  signal u_ddr3_infrastructure_n_9 : STD_LOGIC;
  signal u_memc_ui_top_std_n_52 : STD_LOGIC;
  signal u_memc_ui_top_std_n_53 : STD_LOGIC;
  signal u_memc_ui_top_std_n_54 : STD_LOGIC;
  signal u_memc_ui_top_std_n_57 : STD_LOGIC;
  signal u_memc_ui_top_std_n_573 : STD_LOGIC;
  attribute X_CORE_INFO : string;
  attribute X_CORE_INFO of u_memc_ui_top_std : label is "mig_7series_v4_2_ddr3_7Series, mig, 2018.3";
begin
  \gen_mmcm.mmcm_i\ <= \^gen_mmcm.mmcm_i\;
  rstdiv0_sync_r1_reg_rep <= \^rstdiv0_sync_r1_reg_rep\;
\temp_mon_enabled.u_tempmon\: entity work.mig_mig_7series_v4_2_tempmon
     port map (
      D(11 downto 0) => \mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_tempmon_0/device_temp_100\(11 downto 0),
      clk_ref_i => clk_ref_i,
      \out\(11 downto 0) => \out\(11 downto 0),
      \sync_cntr_reg[3]_0\ => \^gen_mmcm.mmcm_i\,
      \xadc_supplied_temperature.rst_r1_reg_0\ => \^rstdiv0_sync_r1_reg_rep\
    );
u_ddr3_clk_ibuf: entity work.mig_mig_7series_v4_2_clk_ibuf
     port map (
      \out\ => mmcm_clk,
      sys_clk_n => sys_clk_n,
      sys_clk_p => sys_clk_p
    );
u_ddr3_infrastructure: entity work.mig_mig_7series_v4_2_infrastructure
     port map (
      AS(0) => sys_rst_act_hi,
      RST0 => \mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/RST0\,
      SR(1) => u_ddr3_infrastructure_n_8,
      SR(0) => u_ddr3_infrastructure_n_9,
      SS(0) => u_ddr3_infrastructure_n_40,
      bm_end_r1 => \mem_intfc0/mc0/bank_mach0/bank_cntrl[1].bank0/bank_state0/bm_end_r1\,
      bm_end_r1_0 => \mem_intfc0/mc0/bank_mach0/bank_cntrl[2].bank0/bank_state0/bm_end_r1\,
      bm_end_r1_1 => \mem_intfc0/mc0/bank_mach0/bank_cntrl[3].bank0/bank_state0/bm_end_r1\,
      bm_end_r1_reg => u_ddr3_infrastructure_n_36,
      bm_end_r1_reg_0 => u_ddr3_infrastructure_n_37,
      bm_end_r1_reg_1 => u_ddr3_infrastructure_n_38,
      \cmp_err_4to1.compare_err_f3_reg\ => u_memc_ui_top_std_n_57,
      \cnt_shift_r_reg[0]\ => u_memc_ui_top_std_n_54,
      \en_cnt_div4.enable_wrlvl_cnt_reg[4]\ => u_memc_ui_top_std_n_573,
      fine_adjust_reg => u_ddr3_infrastructure_n_42,
      freq_refclk => freq_refclk,
      \gen_mmcm.mmcm_i_0\ => \^gen_mmcm.mmcm_i\,
      \gen_mmcm.mmcm_i_i_1_0\ => u_ddr3_infrastructure_n_0,
      \generate_maint_cmds.insert_maint_r_lcl_reg\ => u_ddr3_infrastructure_n_39,
      insert_maint_r => \mem_intfc0/mc0/bank_mach0/insert_maint_r\,
      mem_refclk => mem_refclk,
      mmcm_ps_clk => mmcm_ps_clk,
      new_cnt_cpt_r_reg(0) => \mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/idelay_tap_limit_r0\,
      new_cnt_dqs_r_reg => u_ddr3_infrastructure_n_47,
      \out\ => mmcm_clk,
      pi_cnt_dec => \mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/pi_cnt_dec\,
      pi_cnt_dec_reg(0) => u_ddr3_infrastructure_n_46,
      \pi_rst_stg1_cal_r_reg[1]\ => u_memc_ui_top_std_n_52,
      pll_locked => pll_locked,
      po_cnt_dec => \mem_intfc0/ddr_phy_top0/u_ddr_calib_top/mb_wrlvl_inst.u_ddr_phy_wrlvl/po_cnt_dec\,
      po_cnt_dec_2 => \mem_intfc0/ddr_phy_top0/u_ddr_calib_top/mb_wrlvl_inst.u_ddr_phy_ck_addr_cmd_delay/po_cnt_dec\,
      po_cnt_dec_reg(0) => u_ddr3_infrastructure_n_41,
      prbs_rdlvl_done_pulse => \mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/prbs_rdlvl_done_pulse\,
      prbs_rdlvl_done_pulse_reg => u_ddr3_infrastructure_n_49,
      rdlvl_stg1_start_reg(0) => \mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/cnt_shift_r0\,
      rst_sync_r1 => rst_sync_r1,
      rst_tmp => rst_tmp,
      rstdiv0_sync_r1_reg_rep_0 => \^rstdiv0_sync_r1_reg_rep\,
      \rstdiv0_sync_r1_reg_rep__10_0\(1) => u_ddr3_infrastructure_n_18,
      \rstdiv0_sync_r1_reg_rep__10_0\(0) => u_ddr3_infrastructure_n_19,
      \rstdiv0_sync_r1_reg_rep__12_0\ => u_ddr3_infrastructure_n_20,
      \rstdiv0_sync_r1_reg_rep__13_0\ => u_ddr3_infrastructure_n_21,
      \rstdiv0_sync_r1_reg_rep__14_0\(0) => u_ddr3_infrastructure_n_22,
      \rstdiv0_sync_r1_reg_rep__15_0\ => u_ddr3_infrastructure_n_23,
      \rstdiv0_sync_r1_reg_rep__16_0\ => u_ddr3_infrastructure_n_24,
      \rstdiv0_sync_r1_reg_rep__17_0\ => u_ddr3_infrastructure_n_25,
      \rstdiv0_sync_r1_reg_rep__18_0\ => u_ddr3_infrastructure_n_26,
      \rstdiv0_sync_r1_reg_rep__19_0\ => u_ddr3_infrastructure_n_27,
      \rstdiv0_sync_r1_reg_rep__20_0\(0) => u_ddr3_infrastructure_n_28,
      \rstdiv0_sync_r1_reg_rep__21_0\ => u_ddr3_infrastructure_n_29,
      \rstdiv0_sync_r1_reg_rep__22_0\ => u_ddr3_infrastructure_n_30,
      \rstdiv0_sync_r1_reg_rep__23_0\ => u_ddr3_infrastructure_n_31,
      \rstdiv0_sync_r1_reg_rep__23_1\ => u_ddr3_infrastructure_n_48,
      \rstdiv0_sync_r1_reg_rep__24_0\ => u_ddr3_infrastructure_n_32,
      \rstdiv0_sync_r1_reg_rep__25_0\ => u_ddr3_infrastructure_n_33,
      \rstdiv0_sync_r1_reg_rep__2_0\(1) => u_ddr3_infrastructure_n_10,
      \rstdiv0_sync_r1_reg_rep__2_0\(0) => u_ddr3_infrastructure_n_11,
      \rstdiv0_sync_r1_reg_rep__5_0\(1) => u_ddr3_infrastructure_n_12,
      \rstdiv0_sync_r1_reg_rep__5_0\(0) => u_ddr3_infrastructure_n_13,
      \rstdiv0_sync_r1_reg_rep__7_0\(1) => u_ddr3_infrastructure_n_14,
      \rstdiv0_sync_r1_reg_rep__7_0\(0) => u_ddr3_infrastructure_n_15,
      \rstdiv0_sync_r1_reg_rep__8_0\(0) => u_ddr3_infrastructure_n_16,
      \rstdiv0_sync_r1_reg_rep__9_0\ => u_ddr3_infrastructure_n_17,
      samp_edge_cnt0_en_r => \mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/samp_edge_cnt0_en_r\,
      samp_edge_cnt0_en_r_reg => u_ddr3_infrastructure_n_45,
      sync_pulse => sync_pulse,
      \tap_cnt_cpt_r_reg[5]\ => u_memc_ui_top_std_n_53
    );
u_iodelay_ctrl: entity work.mig_mig_7series_v4_2_iodelay_ctrl
     port map (
      AS(0) => sys_rst_act_hi,
      clk_ref_i => clk_ref_i,
      iodelay_ctrl_rdy(0) => iodelay_ctrl_rdy(0),
      \out\ => sys_rst_o,
      sys_rst => sys_rst
    );
u_memc_ui_top_std: entity work.mig_mig_7series_v4_2_memc_ui_top_std
     port map (
      A_rst_primitives_reg => iserdes_clk,
      A_rst_primitives_reg_0 => iserdes_clk_0,
      A_rst_primitives_reg_1 => iserdes_clk_1,
      A_rst_primitives_reg_2 => iserdes_clk_2,
      A_rst_primitives_reg_3 => iserdes_clk_3,
      A_rst_primitives_reg_4 => iserdes_clk_4,
      A_rst_primitives_reg_5 => iserdes_clk_5,
      A_rst_primitives_reg_6 => iserdes_clk_6,
      CLKB0 => CLKB0,
      CLKB0_10 => CLKB0_10,
      CLKB0_11 => CLKB0_11,
      CLKB0_12 => CLKB0_12,
      CLKB0_13 => CLKB0_13,
      CLKB0_7 => CLKB0_7,
      CLKB0_8 => CLKB0_8,
      CLKB0_9 => CLKB0_9,
      D(11 downto 0) => \mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_tempmon_0/device_temp_100\(11 downto 0),
      E(0) => app_rdy_r_reg,
      \FSM_onehot_cal1_state_r_reg[7]\(0) => u_ddr3_infrastructure_n_10,
      RST0 => \mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/RST0\,
      SR(0) => u_ddr3_infrastructure_n_28,
      SS(0) => u_ddr3_infrastructure_n_40,
      app_addr(26 downto 0) => app_addr(26 downto 0),
      app_cmd(1 downto 0) => app_cmd(1 downto 0),
      app_en => app_en,
      app_rd_data_end => app_rd_data_end,
      app_rd_data_valid => app_rd_data_valid,
      app_ref_ack => app_ref_ack,
      app_ref_req => app_ref_req,
      app_sr_active => app_sr_active,
      app_sr_req => app_sr_req,
      app_wdf_data(511 downto 0) => app_wdf_data(511 downto 0),
      app_wdf_end => app_wdf_end,
      app_wdf_mask(63 downto 0) => app_wdf_mask(63 downto 0),
      app_wdf_rdy => app_wdf_rdy,
      app_wdf_wren => app_wdf_wren,
      app_zq_ack => app_zq_ack,
      app_zq_req => app_zq_req,
      bm_end_r1 => \mem_intfc0/mc0/bank_mach0/bank_cntrl[1].bank0/bank_state0/bm_end_r1\,
      bm_end_r1_0 => \mem_intfc0/mc0/bank_mach0/bank_cntrl[2].bank0/bank_state0/bm_end_r1\,
      bm_end_r1_1 => \mem_intfc0/mc0/bank_mach0/bank_cntrl[3].bank0/bank_state0/bm_end_r1\,
      cal2_if_reset_reg => \^rstdiv0_sync_r1_reg_rep\,
      \cmp_err_4to1.compare_err_f3_reg\ => u_ddr3_infrastructure_n_47,
      \cnt_shift_r_reg[0]\(0) => \mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/cnt_shift_r0\,
      \complex_num_writes_reg[1]\ => u_ddr3_infrastructure_n_49,
      \corse_dec_reg[7][0]\(0) => u_ddr3_infrastructure_n_12,
      \corse_inc_reg[6][2]\(1) => u_ddr3_infrastructure_n_13,
      \corse_inc_reg[6][2]\(0) => u_ddr3_infrastructure_n_11,
      ddr3_addr(13 downto 0) => ddr3_addr(13 downto 0),
      ddr3_ba(2 downto 0) => ddr3_ba(2 downto 0),
      ddr3_cas_n => ddr3_cas_n,
      ddr3_cke(0) => ddr3_cke(0),
      ddr3_cs_n(0) => ddr3_cs_n(0),
      ddr3_dm(7 downto 0) => ddr3_dm(7 downto 0),
      ddr3_dq(63 downto 0) => ddr3_dq(63 downto 0),
      ddr3_dqs_n(7 downto 0) => ddr3_dqs_n(7 downto 0),
      ddr3_dqs_p(7 downto 0) => ddr3_dqs_p(7 downto 0),
      ddr3_odt(0) => ddr3_odt(0),
      ddr3_ras_n => ddr3_ras_n,
      ddr3_reset_n => ddr3_reset_n,
      ddr3_we_n => ddr3_we_n,
      ddr_ck_out(1 downto 0) => ddr_ck_out(1 downto 0),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_2\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_3\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_4\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_5\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_5\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_6\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_6\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_2\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_3\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_4\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_5\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_5\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_6\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_6\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_2\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_3\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_4\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_5\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_5\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_6\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_6\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_2\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_3\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_4\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_5\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_5\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_6\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_6\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_2\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_3\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_4\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_5\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_5\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_6\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_6\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_2\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_3\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_4\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_5\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_5\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_6\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_6\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_2\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_3\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_4\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_5\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_5\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_6\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_6\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_2\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_3\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_4\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_5\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_5\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_6\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_6\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_2\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_3\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_4\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_5\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_5\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_6\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_6\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_2\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_3\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_4\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_5\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_5\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_6\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_6\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_2\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_3\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_4\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_5\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_5\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_6\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_6\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_2\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_3\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_4\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_5\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_5\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_6\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_6\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_2\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_3\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_4\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_5\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_5\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_6\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_6\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_2\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_3\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_4\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_5\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_5\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_6\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_6\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_2\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_3\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_4\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_5\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_5\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_6\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_6\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_2\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_3\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_4\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_5\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_5\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_6\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_6\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_2\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_3\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_4\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_5\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_5\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_6\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_6\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_2\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_3\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_4\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_5\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_5\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_6\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_6\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_2\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_3\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_4\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_5\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_5\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_6\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_6\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_2\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_3\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_4\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_5\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_5\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_6\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_6\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_2\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_3\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_4\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_5\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_5\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_6\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_6\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_2\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_3\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_4\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_5\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_5\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_6\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_6\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_2\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_3\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_4\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_5\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_5\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_6\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_6\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_2\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_3\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_4\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_5\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_5\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_6\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_6\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_2\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_3\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_4\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_5\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_5\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_6\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_6\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_2\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_3\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_4\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_5\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_5\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_6\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_6\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_2\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_3\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_4\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_5\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_5\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_6\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_6\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_2\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_3\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_4\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_5\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_5\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_6\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_6\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_2\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_3\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_4\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_5\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_5\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_6\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_6\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_2\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_3\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_4\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_5\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_5\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_6\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_6\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_2\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_3\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_4\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_5\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_5\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_6\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_6\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_2\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_3\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_4\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_5\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_5\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_6\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_6\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_2\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_3\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_4\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_5\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_5\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_6\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_6\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_2\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_3\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_4\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_5\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_5\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_6\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_6\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_2\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_3\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_4\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_5\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_5\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_6\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_6\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_2\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_3\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_4\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_5\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_5\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_6\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_6\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_2\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_3\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_4\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_5\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_5\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_6\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_6\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_2\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_3\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_4\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_5\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_5\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_6\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_6\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_2\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_3\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_4\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_5\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_5\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_6\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_6\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_2\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_3\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_4\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_5\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_5\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_6\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_6\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_2\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_3\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_4\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_5\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_5\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_6\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_6\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_2\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_3\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_4\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_5\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_5\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_6\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_6\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_2\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_3\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_4\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_5\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_5\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_6\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_6\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_2\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_3\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_4\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_5\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_5\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_6\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_6\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_2\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_3\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_4\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_5\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_5\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_6\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_6\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_2\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_3\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_4\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_5\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_5\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_6\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_6\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_2\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_3\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_4\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_5\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_5\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_6\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_6\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_2\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_3\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_4\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_5\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_5\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_6\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_6\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_2\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_3\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_4\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_2\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_3\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_4\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_2\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_3\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_4\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_2\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_3\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_4\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_2\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_3\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_4\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_2\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_3\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_4\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_2\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_3\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_4\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_2\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_3\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_4\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_2\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_3\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_4\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_5\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_5\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_6\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_6\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_2\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_3\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_4\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_5\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_5\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_6\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_6\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_2\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_3\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_4\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_5\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_5\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_6\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_6\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_2\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_3\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_4\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_5\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_5\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_6\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_6\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_2\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_3\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_4\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_5\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_5\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_6\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_6\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_2\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_3\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_4\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_5\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_5\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_6\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_6\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_2\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_3\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_4\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_5\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_5\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_6\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_6\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_2\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_3\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_4\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_5\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_5\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_6\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_6\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_0\,
      \en_cnt_div4.enable_wrlvl_cnt_reg[2]\ => u_ddr3_infrastructure_n_21,
      \en_cnt_div4.enable_wrlvl_cnt_reg[4]\ => u_ddr3_infrastructure_n_48,
      fine_adjust_reg => u_memc_ui_top_std_n_52,
      \fine_dec_cnt_reg[5]\(1) => u_ddr3_infrastructure_n_18,
      \fine_dec_cnt_reg[5]\(0) => u_ddr3_infrastructure_n_19,
      \fine_inc_reg[6][3]\(0) => u_ddr3_infrastructure_n_16,
      first_fail_detect_reg => u_ddr3_infrastructure_n_25,
      \four_dec_min_limit_reg[0]\ => u_ddr3_infrastructure_n_23,
      freq_refclk => freq_refclk,
      \idelay_tap_cnt_r_reg[0][0][4]\ => u_ddr3_infrastructure_n_30,
      init_calib_complete => init_calib_complete,
      \init_state_r_reg[4]\ => u_memc_ui_top_std_n_573,
      insert_maint_r => \mem_intfc0/mc0/bank_mach0/insert_maint_r\,
      iodelay_ctrl_rdy(0) => iodelay_ctrl_rdy(0),
      \last_master_r_reg[2]\ => u_ddr3_infrastructure_n_32,
      mem_refclk => mem_refclk,
      mmcm_ps_clk => mmcm_ps_clk,
      new_cnt_cpt_r_reg => u_memc_ui_top_std_n_53,
      new_cnt_dqs_r_reg => u_memc_ui_top_std_n_57,
      \out\ => sys_rst_o,
      \periodic_rd_generation.periodic_rd_cntr1_r_reg\ => u_ddr3_infrastructure_n_24,
      \periodic_read_request.periodic_rd_r_cnt_reg\ => u_ddr3_infrastructure_n_26,
      pi_cnt_dec => \mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/pi_cnt_dec\,
      \pi_rst_stg1_cal_r_reg[1]\ => u_ddr3_infrastructure_n_42,
      pll_locked => pll_locked,
      po_cnt_dec => \mem_intfc0/ddr_phy_top0/u_ddr_calib_top/mb_wrlvl_inst.u_ddr_phy_wrlvl/po_cnt_dec\,
      po_cnt_dec_2 => \mem_intfc0/ddr_phy_top0/u_ddr_calib_top/mb_wrlvl_inst.u_ddr_phy_ck_addr_cmd_delay/po_cnt_dec\,
      prbs_rdlvl_done_pulse => \mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/prbs_rdlvl_done_pulse\,
      ras_timer_zero_r_reg => u_ddr3_infrastructure_n_36,
      ras_timer_zero_r_reg_0 => u_ddr3_infrastructure_n_37,
      ras_timer_zero_r_reg_1 => u_ddr3_infrastructure_n_38,
      \rdlvl_dqs_tap_cnt_r_reg[0][0][2]\(1) => u_ddr3_infrastructure_n_8,
      \rdlvl_dqs_tap_cnt_r_reg[0][0][2]\(0) => u_ddr3_infrastructure_n_9,
      rdlvl_stg1_start_reg => u_memc_ui_top_std_n_54,
      reset_reg_0 => u_ddr3_infrastructure_n_33,
      \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[3]\ => u_ddr3_infrastructure_n_39,
      rst_sync_r1 => rst_sync_r1,
      rst_tmp => rst_tmp,
      \rstdiv2_sync_r_reg[11]\ => u_ddr3_infrastructure_n_0,
      \rtp_timer_r_reg[0]\ => u_ddr3_infrastructure_n_29,
      \rtp_timer_r_reg[1]\ => u_ddr3_infrastructure_n_31,
      samp_edge_cnt0_en_r => \mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/samp_edge_cnt0_en_r\,
      \samp_edge_cnt1_r_reg[0]\ => u_ddr3_infrastructure_n_45,
      \samples_cnt_r_reg[0]\ => u_ddr3_infrastructure_n_20,
      sync_pulse => sync_pulse,
      \tap_cnt_cpt_r_reg[5]\(0) => \mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/idelay_tap_limit_r0\,
      \victim_sel_reg[0]\(0) => u_ddr3_infrastructure_n_22,
      \wait_cnt_r_reg[0]\(0) => u_ddr3_infrastructure_n_41,
      \wait_cnt_r_reg[0]_0\(0) => u_ddr3_infrastructure_n_46,
      \wl_dqs_tap_count_r_reg[0][5][5]\ => u_ddr3_infrastructure_n_17,
      \wl_dqs_tap_count_r_reg[0][6][3]\(1) => u_ddr3_infrastructure_n_14,
      \wl_dqs_tap_count_r_reg[0][6][3]\(0) => u_ddr3_infrastructure_n_15,
      \wr_req_counter.wr_req_cnt_r_reg[0]\ => \^gen_mmcm.mmcm_i\,
      \zq_cntrl.zq_request_logic.zq_request_r_reg\ => u_ddr3_infrastructure_n_27
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mig is
  port (
    ddr3_dq : inout STD_LOGIC_VECTOR ( 63 downto 0 );
    ddr3_dqs_p : inout STD_LOGIC_VECTOR ( 7 downto 0 );
    ddr3_dqs_n : inout STD_LOGIC_VECTOR ( 7 downto 0 );
    ddr3_addr : out STD_LOGIC_VECTOR ( 13 downto 0 );
    ddr3_ba : out STD_LOGIC_VECTOR ( 2 downto 0 );
    ddr3_ras_n : out STD_LOGIC;
    ddr3_cas_n : out STD_LOGIC;
    ddr3_we_n : out STD_LOGIC;
    ddr3_reset_n : out STD_LOGIC;
    ddr3_ck_p : out STD_LOGIC_VECTOR ( 0 to 0 );
    ddr3_ck_n : out STD_LOGIC_VECTOR ( 0 to 0 );
    ddr3_cke : out STD_LOGIC_VECTOR ( 0 to 0 );
    ddr3_cs_n : out STD_LOGIC_VECTOR ( 0 to 0 );
    ddr3_dm : out STD_LOGIC_VECTOR ( 7 downto 0 );
    ddr3_odt : out STD_LOGIC_VECTOR ( 0 to 0 );
    app_addr : in STD_LOGIC_VECTOR ( 27 downto 0 );
    app_cmd : in STD_LOGIC_VECTOR ( 2 downto 0 );
    app_en : in STD_LOGIC;
    app_wdf_data : in STD_LOGIC_VECTOR ( 511 downto 0 );
    app_wdf_end : in STD_LOGIC;
    app_wdf_mask : in STD_LOGIC_VECTOR ( 63 downto 0 );
    app_wdf_wren : in STD_LOGIC;
    app_rd_data : out STD_LOGIC_VECTOR ( 511 downto 0 );
    app_rd_data_end : out STD_LOGIC;
    app_rd_data_valid : out STD_LOGIC;
    app_rdy : out STD_LOGIC;
    app_wdf_rdy : out STD_LOGIC;
    app_sr_req : in STD_LOGIC;
    app_ref_req : in STD_LOGIC;
    app_zq_req : in STD_LOGIC;
    app_sr_active : out STD_LOGIC;
    app_ref_ack : out STD_LOGIC;
    app_zq_ack : out STD_LOGIC;
    ui_clk : out STD_LOGIC;
    ui_clk_sync_rst : out STD_LOGIC;
    init_calib_complete : out STD_LOGIC;
    sys_clk_p : in STD_LOGIC;
    sys_clk_n : in STD_LOGIC;
    clk_ref_i : in STD_LOGIC;
    device_temp : out STD_LOGIC_VECTOR ( 11 downto 0 );
    sys_rst : in STD_LOGIC
  );
  attribute NotValidForBitStream : boolean;
  attribute NotValidForBitStream of mig : entity is true;
end mig;

architecture STRUCTURE of mig is
  signal \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/iserdes_clk\ : STD_LOGIC;
  signal \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/iserdes_clk\ : STD_LOGIC;
  signal \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/iserdes_clk\ : STD_LOGIC;
  signal \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/iserdes_clk\ : STD_LOGIC;
  signal \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/iserdes_clk\ : STD_LOGIC;
  signal \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/iserdes_clk\ : STD_LOGIC;
  signal \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/iserdes_clk\ : STD_LOGIC;
  signal \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/iserdes_clk\ : STD_LOGIC;
begin
u_mig_mig: entity work.mig_mig_mig
     port map (
      CLKB0 => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/iserdes_clk\,
      CLKB0_10 => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/iserdes_clk\,
      CLKB0_11 => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/iserdes_clk\,
      CLKB0_12 => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/iserdes_clk\,
      CLKB0_13 => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/iserdes_clk\,
      CLKB0_7 => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/iserdes_clk\,
      CLKB0_8 => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/iserdes_clk\,
      CLKB0_9 => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/iserdes_clk\,
      app_addr(26 downto 0) => app_addr(26 downto 0),
      app_cmd(1 downto 0) => app_cmd(1 downto 0),
      app_en => app_en,
      app_rd_data_end => app_rd_data_end,
      app_rd_data_valid => app_rd_data_valid,
      app_rdy_r_reg => app_rdy,
      app_ref_ack => app_ref_ack,
      app_ref_req => app_ref_req,
      app_sr_active => app_sr_active,
      app_sr_req => app_sr_req,
      app_wdf_data(511 downto 0) => app_wdf_data(511 downto 0),
      app_wdf_end => app_wdf_end,
      app_wdf_mask(63 downto 0) => app_wdf_mask(63 downto 0),
      app_wdf_rdy => app_wdf_rdy,
      app_wdf_wren => app_wdf_wren,
      app_zq_ack => app_zq_ack,
      app_zq_req => app_zq_req,
      clk_ref_i => clk_ref_i,
      ddr3_addr(13 downto 0) => ddr3_addr(13 downto 0),
      ddr3_ba(2 downto 0) => ddr3_ba(2 downto 0),
      ddr3_cas_n => ddr3_cas_n,
      ddr3_cke(0) => ddr3_cke(0),
      ddr3_cs_n(0) => ddr3_cs_n(0),
      ddr3_dm(7 downto 0) => ddr3_dm(7 downto 0),
      ddr3_dq(63 downto 0) => ddr3_dq(63 downto 0),
      ddr3_dqs_n(7 downto 0) => ddr3_dqs_n(7 downto 0),
      ddr3_dqs_p(7 downto 0) => ddr3_dqs_p(7 downto 0),
      ddr3_odt(0) => ddr3_odt(0),
      ddr3_ras_n => ddr3_ras_n,
      ddr3_reset_n => ddr3_reset_n,
      ddr3_we_n => ddr3_we_n,
      ddr_ck_out(1) => ddr3_ck_n(0),
      ddr_ck_out(0) => ddr3_ck_p(0),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]\ => app_rd_data(128),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_0\ => app_rd_data(160),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]\ => app_rd_data(224),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_0\ => app_rd_data(192),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]\ => app_rd_data(256),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_0\ => app_rd_data(288),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]\ => app_rd_data(352),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_0\ => app_rd_data(320),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]\ => app_rd_data(416),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_0\ => app_rd_data(384),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]\ => app_rd_data(448),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_0\ => app_rd_data(480),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]\ => app_rd_data(40),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_0\ => app_rd_data(48),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_1\ => app_rd_data(24),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_2\ => app_rd_data(8),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_3\ => app_rd_data(16),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_4\ => app_rd_data(56),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_5\ => app_rd_data(1),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_6\ => app_rd_data(33),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]\ => app_rd_data(104),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_0\ => app_rd_data(112),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_1\ => app_rd_data(88),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_2\ => app_rd_data(72),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_3\ => app_rd_data(80),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_4\ => app_rd_data(120),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_5\ => app_rd_data(65),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_6\ => app_rd_data(97),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]\ => app_rd_data(136),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_0\ => app_rd_data(144),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_1\ => app_rd_data(184),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_2\ => app_rd_data(168),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_3\ => app_rd_data(176),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_4\ => app_rd_data(152),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_5\ => app_rd_data(129),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_6\ => app_rd_data(161),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]\ => app_rd_data(232),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_0\ => app_rd_data(240),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_1\ => app_rd_data(216),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_2\ => app_rd_data(200),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_3\ => app_rd_data(208),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_4\ => app_rd_data(248),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_5\ => app_rd_data(193),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_6\ => app_rd_data(225),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]\ => app_rd_data(264),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_0\ => app_rd_data(272),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_1\ => app_rd_data(312),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_2\ => app_rd_data(296),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_3\ => app_rd_data(304),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_4\ => app_rd_data(280),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_5\ => app_rd_data(257),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_6\ => app_rd_data(289),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]\ => app_rd_data(360),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_0\ => app_rd_data(368),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_1\ => app_rd_data(344),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_2\ => app_rd_data(328),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_3\ => app_rd_data(336),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_4\ => app_rd_data(376),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_5\ => app_rd_data(321),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_6\ => app_rd_data(353),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]\ => app_rd_data(424),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_0\ => app_rd_data(432),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_1\ => app_rd_data(408),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_2\ => app_rd_data(392),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_3\ => app_rd_data(400),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_4\ => app_rd_data(440),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_5\ => app_rd_data(385),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_6\ => app_rd_data(417),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]\ => app_rd_data(456),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_0\ => app_rd_data(464),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_1\ => app_rd_data(504),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_2\ => app_rd_data(488),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_3\ => app_rd_data(496),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_4\ => app_rd_data(472),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_5\ => app_rd_data(449),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_6\ => app_rd_data(481),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]\ => app_rd_data(9),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0\ => app_rd_data(17),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_1\ => app_rd_data(57),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_2\ => app_rd_data(41),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_3\ => app_rd_data(49),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_4\ => app_rd_data(25),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_5\ => app_rd_data(2),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_6\ => app_rd_data(34),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]\ => app_rd_data(73),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_0\ => app_rd_data(81),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_1\ => app_rd_data(121),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_2\ => app_rd_data(105),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_3\ => app_rd_data(113),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_4\ => app_rd_data(89),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_5\ => app_rd_data(98),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_6\ => app_rd_data(66),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]\ => app_rd_data(137),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_0\ => app_rd_data(145),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_1\ => app_rd_data(185),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_2\ => app_rd_data(169),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_3\ => app_rd_data(177),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_4\ => app_rd_data(153),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_5\ => app_rd_data(162),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_6\ => app_rd_data(130),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]\ => app_rd_data(201),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_0\ => app_rd_data(209),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_1\ => app_rd_data(249),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_2\ => app_rd_data(233),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_3\ => app_rd_data(241),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_4\ => app_rd_data(217),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_5\ => app_rd_data(226),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_6\ => app_rd_data(194),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]\ => app_rd_data(265),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_0\ => app_rd_data(273),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_1\ => app_rd_data(313),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_2\ => app_rd_data(297),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_3\ => app_rd_data(305),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_4\ => app_rd_data(281),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_5\ => app_rd_data(258),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_6\ => app_rd_data(290),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]\ => app_rd_data(329),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_0\ => app_rd_data(337),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_1\ => app_rd_data(377),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_2\ => app_rd_data(361),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_3\ => app_rd_data(369),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_4\ => app_rd_data(345),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_5\ => app_rd_data(322),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_6\ => app_rd_data(354),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]\ => app_rd_data(393),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_0\ => app_rd_data(401),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_1\ => app_rd_data(441),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_2\ => app_rd_data(425),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_3\ => app_rd_data(433),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_4\ => app_rd_data(409),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_5\ => app_rd_data(386),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_6\ => app_rd_data(418),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]\ => app_rd_data(457),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_0\ => app_rd_data(465),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_1\ => app_rd_data(505),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_2\ => app_rd_data(489),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_3\ => app_rd_data(497),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_4\ => app_rd_data(473),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_5\ => app_rd_data(450),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_6\ => app_rd_data(482),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]\ => app_rd_data(10),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_0\ => app_rd_data(18),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_1\ => app_rd_data(58),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_2\ => app_rd_data(42),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_3\ => app_rd_data(50),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_4\ => app_rd_data(26),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_5\ => app_rd_data(3),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_6\ => app_rd_data(35),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]\ => app_rd_data(106),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_0\ => app_rd_data(114),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_1\ => app_rd_data(90),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_2\ => app_rd_data(74),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_3\ => app_rd_data(82),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_4\ => app_rd_data(122),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_5\ => app_rd_data(67),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_6\ => app_rd_data(99),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]\ => app_rd_data(170),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_0\ => app_rd_data(178),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_1\ => app_rd_data(154),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_2\ => app_rd_data(138),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_3\ => app_rd_data(146),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_4\ => app_rd_data(186),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_5\ => app_rd_data(131),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_6\ => app_rd_data(163),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]\ => app_rd_data(234),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_0\ => app_rd_data(242),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_1\ => app_rd_data(218),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_2\ => app_rd_data(202),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_3\ => app_rd_data(210),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_4\ => app_rd_data(250),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_5\ => app_rd_data(195),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_6\ => app_rd_data(227),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]\ => app_rd_data(266),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_0\ => app_rd_data(274),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_1\ => app_rd_data(314),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_2\ => app_rd_data(298),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_3\ => app_rd_data(306),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_4\ => app_rd_data(282),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_5\ => app_rd_data(259),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_6\ => app_rd_data(291),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]\ => app_rd_data(330),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_0\ => app_rd_data(338),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_1\ => app_rd_data(378),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_2\ => app_rd_data(362),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_3\ => app_rd_data(370),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_4\ => app_rd_data(346),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_5\ => app_rd_data(323),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_6\ => app_rd_data(355),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]\ => app_rd_data(394),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_0\ => app_rd_data(402),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_1\ => app_rd_data(442),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_2\ => app_rd_data(426),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_3\ => app_rd_data(434),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_4\ => app_rd_data(410),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_5\ => app_rd_data(387),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_6\ => app_rd_data(419),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]\ => app_rd_data(458),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_0\ => app_rd_data(466),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_1\ => app_rd_data(506),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_2\ => app_rd_data(490),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_3\ => app_rd_data(498),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_4\ => app_rd_data(474),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_5\ => app_rd_data(451),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_6\ => app_rd_data(483),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]\ => app_rd_data(11),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0\ => app_rd_data(19),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_1\ => app_rd_data(59),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_2\ => app_rd_data(43),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_3\ => app_rd_data(51),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_4\ => app_rd_data(27),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_5\ => app_rd_data(36),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_6\ => app_rd_data(4),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]\ => app_rd_data(75),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_0\ => app_rd_data(83),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_1\ => app_rd_data(123),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_2\ => app_rd_data(107),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_3\ => app_rd_data(115),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_4\ => app_rd_data(91),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_5\ => app_rd_data(100),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_6\ => app_rd_data(68),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]\ => app_rd_data(139),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_0\ => app_rd_data(147),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_1\ => app_rd_data(187),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_2\ => app_rd_data(171),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_3\ => app_rd_data(179),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_4\ => app_rd_data(155),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_5\ => app_rd_data(164),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_6\ => app_rd_data(132),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]\ => app_rd_data(203),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_0\ => app_rd_data(211),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_1\ => app_rd_data(251),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_2\ => app_rd_data(235),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_3\ => app_rd_data(243),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_4\ => app_rd_data(219),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_5\ => app_rd_data(228),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_6\ => app_rd_data(196),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]\ => app_rd_data(267),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_0\ => app_rd_data(275),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_1\ => app_rd_data(315),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_2\ => app_rd_data(299),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_3\ => app_rd_data(307),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_4\ => app_rd_data(283),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_5\ => app_rd_data(292),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_6\ => app_rd_data(260),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]\ => app_rd_data(331),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_0\ => app_rd_data(339),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_1\ => app_rd_data(379),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_2\ => app_rd_data(363),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_3\ => app_rd_data(371),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_4\ => app_rd_data(347),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_5\ => app_rd_data(356),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_6\ => app_rd_data(324),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]\ => app_rd_data(395),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_0\ => app_rd_data(403),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_1\ => app_rd_data(443),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_2\ => app_rd_data(427),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_3\ => app_rd_data(435),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_4\ => app_rd_data(411),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_5\ => app_rd_data(420),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_6\ => app_rd_data(388),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]\ => app_rd_data(459),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_0\ => app_rd_data(467),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_1\ => app_rd_data(507),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_2\ => app_rd_data(491),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_3\ => app_rd_data(499),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_4\ => app_rd_data(475),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_5\ => app_rd_data(452),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_6\ => app_rd_data(484),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]\ => app_rd_data(44),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_0\ => app_rd_data(52),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_1\ => app_rd_data(28),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_2\ => app_rd_data(12),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_3\ => app_rd_data(20),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_4\ => app_rd_data(60),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_5\ => app_rd_data(5),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_6\ => app_rd_data(37),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]\ => app_rd_data(108),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_0\ => app_rd_data(116),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_1\ => app_rd_data(92),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_2\ => app_rd_data(76),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_3\ => app_rd_data(84),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_4\ => app_rd_data(124),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_5\ => app_rd_data(69),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_6\ => app_rd_data(101),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]\ => app_rd_data(172),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_0\ => app_rd_data(180),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_1\ => app_rd_data(156),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_2\ => app_rd_data(140),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_3\ => app_rd_data(148),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_4\ => app_rd_data(188),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_5\ => app_rd_data(133),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_6\ => app_rd_data(165),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]\ => app_rd_data(236),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_0\ => app_rd_data(244),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_1\ => app_rd_data(220),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_2\ => app_rd_data(204),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_3\ => app_rd_data(212),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_4\ => app_rd_data(252),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_5\ => app_rd_data(197),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_6\ => app_rd_data(229),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]\ => app_rd_data(300),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_0\ => app_rd_data(308),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_1\ => app_rd_data(284),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_2\ => app_rd_data(268),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_3\ => app_rd_data(276),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_4\ => app_rd_data(316),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_5\ => app_rd_data(261),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_6\ => app_rd_data(293),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]\ => app_rd_data(364),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_0\ => app_rd_data(372),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_1\ => app_rd_data(348),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_2\ => app_rd_data(332),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_3\ => app_rd_data(340),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_4\ => app_rd_data(380),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_5\ => app_rd_data(325),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_6\ => app_rd_data(357),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]\ => app_rd_data(428),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_0\ => app_rd_data(436),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_1\ => app_rd_data(412),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_2\ => app_rd_data(396),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_3\ => app_rd_data(404),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_4\ => app_rd_data(444),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_5\ => app_rd_data(389),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_6\ => app_rd_data(421),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]\ => app_rd_data(460),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_0\ => app_rd_data(468),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_1\ => app_rd_data(508),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_2\ => app_rd_data(492),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_3\ => app_rd_data(500),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_4\ => app_rd_data(476),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_5\ => app_rd_data(453),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_6\ => app_rd_data(485),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]\ => app_rd_data(13),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0\ => app_rd_data(21),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_1\ => app_rd_data(61),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_2\ => app_rd_data(45),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_3\ => app_rd_data(53),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_4\ => app_rd_data(29),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_5\ => app_rd_data(6),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_6\ => app_rd_data(38),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]\ => app_rd_data(77),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_0\ => app_rd_data(85),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_1\ => app_rd_data(125),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_2\ => app_rd_data(109),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_3\ => app_rd_data(117),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_4\ => app_rd_data(93),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_5\ => app_rd_data(70),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_6\ => app_rd_data(102),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]\ => app_rd_data(141),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_0\ => app_rd_data(149),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_1\ => app_rd_data(189),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_2\ => app_rd_data(173),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_3\ => app_rd_data(181),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_4\ => app_rd_data(157),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_5\ => app_rd_data(134),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_6\ => app_rd_data(166),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]\ => app_rd_data(205),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_0\ => app_rd_data(213),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_1\ => app_rd_data(253),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_2\ => app_rd_data(237),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_3\ => app_rd_data(245),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_4\ => app_rd_data(221),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_5\ => app_rd_data(198),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_6\ => app_rd_data(230),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]\ => app_rd_data(269),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_0\ => app_rd_data(277),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_1\ => app_rd_data(317),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_2\ => app_rd_data(301),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_3\ => app_rd_data(309),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_4\ => app_rd_data(285),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_5\ => app_rd_data(262),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_6\ => app_rd_data(294),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]\ => app_rd_data(333),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_0\ => app_rd_data(341),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_1\ => app_rd_data(381),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_2\ => app_rd_data(365),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_3\ => app_rd_data(373),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_4\ => app_rd_data(349),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_5\ => app_rd_data(326),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_6\ => app_rd_data(358),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]\ => app_rd_data(397),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_0\ => app_rd_data(405),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_1\ => app_rd_data(445),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_2\ => app_rd_data(429),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_3\ => app_rd_data(437),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_4\ => app_rd_data(413),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_5\ => app_rd_data(390),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_6\ => app_rd_data(422),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]\ => app_rd_data(461),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_0\ => app_rd_data(469),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_1\ => app_rd_data(509),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_2\ => app_rd_data(493),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_3\ => app_rd_data(501),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_4\ => app_rd_data(477),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_5\ => app_rd_data(454),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_6\ => app_rd_data(486),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]\ => app_rd_data(14),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_0\ => app_rd_data(22),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_1\ => app_rd_data(62),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_2\ => app_rd_data(46),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_3\ => app_rd_data(54),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_4\ => app_rd_data(30),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]\ => app_rd_data(78),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_0\ => app_rd_data(86),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_1\ => app_rd_data(126),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_2\ => app_rd_data(110),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_3\ => app_rd_data(118),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_4\ => app_rd_data(94),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]\ => app_rd_data(142),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_0\ => app_rd_data(150),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_1\ => app_rd_data(190),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_2\ => app_rd_data(174),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_3\ => app_rd_data(182),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_4\ => app_rd_data(158),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]\ => app_rd_data(206),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_0\ => app_rd_data(214),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_1\ => app_rd_data(254),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_2\ => app_rd_data(238),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_3\ => app_rd_data(246),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_4\ => app_rd_data(222),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]\ => app_rd_data(270),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_0\ => app_rd_data(278),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_1\ => app_rd_data(318),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_2\ => app_rd_data(302),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_3\ => app_rd_data(310),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_4\ => app_rd_data(286),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]\ => app_rd_data(334),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_0\ => app_rd_data(342),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_1\ => app_rd_data(382),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_2\ => app_rd_data(366),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_3\ => app_rd_data(374),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_4\ => app_rd_data(350),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]\ => app_rd_data(398),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_0\ => app_rd_data(406),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_1\ => app_rd_data(446),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_2\ => app_rd_data(430),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_3\ => app_rd_data(438),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_4\ => app_rd_data(414),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]\ => app_rd_data(462),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_0\ => app_rd_data(470),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_1\ => app_rd_data(510),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_2\ => app_rd_data(494),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_3\ => app_rd_data(502),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_4\ => app_rd_data(478),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]\ => app_rd_data(15),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_0\ => app_rd_data(23),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_1\ => app_rd_data(63),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_2\ => app_rd_data(7),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_3\ => app_rd_data(47),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_4\ => app_rd_data(55),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_5\ => app_rd_data(31),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_6\ => app_rd_data(39),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]\ => app_rd_data(79),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_0\ => app_rd_data(87),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_1\ => app_rd_data(127),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_2\ => app_rd_data(71),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_3\ => app_rd_data(111),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_4\ => app_rd_data(119),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_5\ => app_rd_data(95),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_6\ => app_rd_data(103),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]\ => app_rd_data(143),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_0\ => app_rd_data(151),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_1\ => app_rd_data(191),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_2\ => app_rd_data(135),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_3\ => app_rd_data(175),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_4\ => app_rd_data(183),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_5\ => app_rd_data(159),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_6\ => app_rd_data(167),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]\ => app_rd_data(207),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_0\ => app_rd_data(215),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_1\ => app_rd_data(255),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_2\ => app_rd_data(199),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_3\ => app_rd_data(239),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_4\ => app_rd_data(247),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_5\ => app_rd_data(223),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_6\ => app_rd_data(231),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]\ => app_rd_data(271),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_0\ => app_rd_data(279),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_1\ => app_rd_data(319),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_2\ => app_rd_data(263),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_3\ => app_rd_data(303),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_4\ => app_rd_data(311),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_5\ => app_rd_data(287),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_6\ => app_rd_data(295),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]\ => app_rd_data(335),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_0\ => app_rd_data(343),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_1\ => app_rd_data(383),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_2\ => app_rd_data(327),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_3\ => app_rd_data(367),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_4\ => app_rd_data(375),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_5\ => app_rd_data(351),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_6\ => app_rd_data(359),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]\ => app_rd_data(399),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_0\ => app_rd_data(407),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_1\ => app_rd_data(447),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_2\ => app_rd_data(391),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_3\ => app_rd_data(431),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_4\ => app_rd_data(439),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_5\ => app_rd_data(415),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_6\ => app_rd_data(423),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]\ => app_rd_data(463),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0\ => app_rd_data(471),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_1\ => app_rd_data(511),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_2\ => app_rd_data(455),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_3\ => app_rd_data(495),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_4\ => app_rd_data(503),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_5\ => app_rd_data(479),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_6\ => app_rd_data(487),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]\ => app_rd_data(32),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_0\ => app_rd_data(0),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]\ => app_rd_data(96),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_0\ => app_rd_data(64),
      \gen_mmcm.mmcm_i\ => ui_clk,
      init_calib_complete => init_calib_complete,
      iserdes_clk => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/iserdes_clk\,
      iserdes_clk_0 => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/iserdes_clk\,
      iserdes_clk_1 => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/iserdes_clk\,
      iserdes_clk_2 => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/iserdes_clk\,
      iserdes_clk_3 => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/iserdes_clk\,
      iserdes_clk_4 => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/iserdes_clk\,
      iserdes_clk_5 => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/iserdes_clk\,
      iserdes_clk_6 => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/iserdes_clk\,
      \out\(11 downto 0) => device_temp(11 downto 0),
      rstdiv0_sync_r1_reg_rep => ui_clk_sync_rst,
      sys_clk_n => sys_clk_n,
      sys_clk_p => sys_clk_p,
      sys_rst => sys_rst
    );
end STRUCTURE;
