// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019
// Date        : Mon May 25 01:04:53 2020
// Host        : LAPTOP-RJQ3H7G3 running 64-bit major release  (build 9200)
// Command     : write_verilog -force -mode funcsim
//               D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/ip/pdm_to_pcm_timemux_0_2/pdm_to_pcm_timemux_0_2_sim_netlist.v
// Design      : pdm_to_pcm_timemux_0_2
// Purpose     : This verilog netlist is a functional simulation representation of the design and should not be modified
//               or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device      : xc7a200tfbg676-2
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps

(* CHECK_LICENSE_TYPE = "pdm_to_pcm_timemux_0_2,timemux,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* ip_definition_source = "module_ref" *) 
(* x_core_info = "timemux,Vivado 2019.1" *) 
(* NotValidForBitStream *)
module pdm_to_pcm_timemux_0_2
   (clk,
    start,
    pdm_data,
    pdm_data_mux,
    data_tvalid,
    data_tlast);
  (* x_interface_info = "xilinx.com:signal:clock:1.0 clk CLK" *) (* x_interface_parameter = "XIL_INTERFACENAME clk, ASSOCIATED_BUSIF data, FREQ_HZ 12800000, PHASE 0.0, CLK_DOMAIN /clk_wiz_0_clk_out1, INSERT_VIP 0" *) input clk;
  input start;
  input [3:0]pdm_data;
  output [7:0]pdm_data_mux;
  (* x_interface_info = "xilinx.com:interface:axis:1.0 data TVALID" *) (* x_interface_parameter = "XIL_INTERFACENAME data, TDATA_NUM_BYTES 0, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 0, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 1, FREQ_HZ 12800000, PHASE 0.0, CLK_DOMAIN /clk_wiz_0_clk_out1, LAYERED_METADATA undef, INSERT_VIP 0" *) output data_tvalid;
  (* x_interface_info = "xilinx.com:interface:axis:1.0 data TLAST" *) output data_tlast;

  wire \<const0> ;
  wire \<const1> ;
  wire clk;
  wire data_tlast;
  wire [3:0]pdm_data;
  wire [1:1]\^pdm_data_mux ;
  wire start;

  assign data_tvalid = start;
  assign pdm_data_mux[7] = \<const0> ;
  assign pdm_data_mux[6] = \<const0> ;
  assign pdm_data_mux[5] = \<const0> ;
  assign pdm_data_mux[4] = \<const0> ;
  assign pdm_data_mux[3] = \<const0> ;
  assign pdm_data_mux[2] = \<const0> ;
  assign pdm_data_mux[1] = \^pdm_data_mux [1];
  assign pdm_data_mux[0] = \<const1> ;
  GND GND
       (.G(\<const0> ));
  pdm_to_pcm_timemux_0_2_timemux U0
       (.clk(clk),
        .data_tlast(data_tlast),
        .pdm_data(pdm_data),
        .pdm_data_mux(\^pdm_data_mux ),
        .start(start));
  VCC VCC
       (.P(\<const1> ));
endmodule

(* ORIG_REF_NAME = "timemux" *) 
module pdm_to_pcm_timemux_0_2_timemux
   (data_tlast,
    pdm_data_mux,
    start,
    clk,
    pdm_data);
  output data_tlast;
  output [0:0]pdm_data_mux;
  input start;
  input clk;
  input [3:0]pdm_data;

  wire clk;
  wire [1:0]cntr;
  wire \cntr[0]_i_1_n_0 ;
  wire \cntr[1]_i_1_n_0 ;
  wire data_tlast;
  wire [3:0]pdm_data;
  wire [0:0]pdm_data_mux;
  wire start;

  (* SOFT_HLUTNM = "soft_lutpair0" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \cntr[0]_i_1 
       (.I0(start),
        .I1(cntr[0]),
        .O(\cntr[0]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair0" *) 
  LUT3 #(
    .INIT(8'h78)) 
    \cntr[1]_i_1 
       (.I0(cntr[0]),
        .I1(start),
        .I2(cntr[1]),
        .O(\cntr[1]_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \cntr_reg[0] 
       (.C(clk),
        .CE(1'b1),
        .D(\cntr[0]_i_1_n_0 ),
        .Q(cntr[0]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cntr_reg[1] 
       (.C(clk),
        .CE(1'b1),
        .D(\cntr[1]_i_1_n_0 ),
        .Q(cntr[1]),
        .R(1'b0));
  LUT2 #(
    .INIT(4'h8)) 
    data_tlast_INST_0
       (.I0(cntr[0]),
        .I1(cntr[1]),
        .O(data_tlast));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    pdm_data_mux0
       (.I0(pdm_data[3]),
        .I1(pdm_data[2]),
        .I2(cntr[1]),
        .I3(pdm_data[1]),
        .I4(cntr[0]),
        .I5(pdm_data[0]),
        .O(pdm_data_mux));
endmodule
`ifndef GLBL
`define GLBL
`timescale  1 ps / 1 ps

module glbl ();

    parameter ROC_WIDTH = 100000;
    parameter TOC_WIDTH = 0;

//--------   STARTUP Globals --------------
    wire GSR;
    wire GTS;
    wire GWE;
    wire PRLD;
    tri1 p_up_tmp;
    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;

    wire PROGB_GLBL;
    wire CCLKO_GLBL;
    wire FCSBO_GLBL;
    wire [3:0] DO_GLBL;
    wire [3:0] DI_GLBL;
   
    reg GSR_int;
    reg GTS_int;
    reg PRLD_int;

//--------   JTAG Globals --------------
    wire JTAG_TDO_GLBL;
    wire JTAG_TCK_GLBL;
    wire JTAG_TDI_GLBL;
    wire JTAG_TMS_GLBL;
    wire JTAG_TRST_GLBL;

    reg JTAG_CAPTURE_GLBL;
    reg JTAG_RESET_GLBL;
    reg JTAG_SHIFT_GLBL;
    reg JTAG_UPDATE_GLBL;
    reg JTAG_RUNTEST_GLBL;

    reg JTAG_SEL1_GLBL = 0;
    reg JTAG_SEL2_GLBL = 0 ;
    reg JTAG_SEL3_GLBL = 0;
    reg JTAG_SEL4_GLBL = 0;

    reg JTAG_USER_TDO1_GLBL = 1'bz;
    reg JTAG_USER_TDO2_GLBL = 1'bz;
    reg JTAG_USER_TDO3_GLBL = 1'bz;
    reg JTAG_USER_TDO4_GLBL = 1'bz;

    assign (strong1, weak0) GSR = GSR_int;
    assign (strong1, weak0) GTS = GTS_int;
    assign (weak1, weak0) PRLD = PRLD_int;

    initial begin
	GSR_int = 1'b1;
	PRLD_int = 1'b1;
	#(ROC_WIDTH)
	GSR_int = 1'b0;
	PRLD_int = 1'b0;
    end

    initial begin
	GTS_int = 1'b1;
	#(TOC_WIDTH)
	GTS_int = 1'b0;
    end

endmodule
`endif
