-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019
-- Date        : Mon May 25 01:04:53 2020
-- Host        : LAPTOP-RJQ3H7G3 running 64-bit major release  (build 9200)
-- Command     : write_vhdl -force -mode funcsim
--               D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/ip/pdm_to_pcm_timemux_0_2/pdm_to_pcm_timemux_0_2_sim_netlist.vhdl
-- Design      : pdm_to_pcm_timemux_0_2
-- Purpose     : This VHDL netlist is a functional simulation representation of the design and should not be modified or
--               synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device      : xc7a200tfbg676-2
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity pdm_to_pcm_timemux_0_2_timemux is
  port (
    data_tlast : out STD_LOGIC;
    pdm_data_mux : out STD_LOGIC_VECTOR ( 0 to 0 );
    start : in STD_LOGIC;
    clk : in STD_LOGIC;
    pdm_data : in STD_LOGIC_VECTOR ( 3 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of pdm_to_pcm_timemux_0_2_timemux : entity is "timemux";
end pdm_to_pcm_timemux_0_2_timemux;

architecture STRUCTURE of pdm_to_pcm_timemux_0_2_timemux is
  signal cntr : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \cntr[0]_i_1_n_0\ : STD_LOGIC;
  signal \cntr[1]_i_1_n_0\ : STD_LOGIC;
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \cntr[0]_i_1\ : label is "soft_lutpair0";
  attribute SOFT_HLUTNM of \cntr[1]_i_1\ : label is "soft_lutpair0";
begin
\cntr[0]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => start,
      I1 => cntr(0),
      O => \cntr[0]_i_1_n_0\
    );
\cntr[1]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"78"
    )
        port map (
      I0 => cntr(0),
      I1 => start,
      I2 => cntr(1),
      O => \cntr[1]_i_1_n_0\
    );
\cntr_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => '1',
      D => \cntr[0]_i_1_n_0\,
      Q => cntr(0),
      R => '0'
    );
\cntr_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => '1',
      D => \cntr[1]_i_1_n_0\,
      Q => cntr(1),
      R => '0'
    );
data_tlast_INST_0: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => cntr(0),
      I1 => cntr(1),
      O => data_tlast
    );
pdm_data_mux0: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => pdm_data(3),
      I1 => pdm_data(2),
      I2 => cntr(1),
      I3 => pdm_data(1),
      I4 => cntr(0),
      I5 => pdm_data(0),
      O => pdm_data_mux(0)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity pdm_to_pcm_timemux_0_2 is
  port (
    clk : in STD_LOGIC;
    start : in STD_LOGIC;
    pdm_data : in STD_LOGIC_VECTOR ( 3 downto 0 );
    pdm_data_mux : out STD_LOGIC_VECTOR ( 7 downto 0 );
    data_tvalid : out STD_LOGIC;
    data_tlast : out STD_LOGIC
  );
  attribute NotValidForBitStream : boolean;
  attribute NotValidForBitStream of pdm_to_pcm_timemux_0_2 : entity is true;
  attribute CHECK_LICENSE_TYPE : string;
  attribute CHECK_LICENSE_TYPE of pdm_to_pcm_timemux_0_2 : entity is "pdm_to_pcm_timemux_0_2,timemux,{}";
  attribute downgradeipidentifiedwarnings : string;
  attribute downgradeipidentifiedwarnings of pdm_to_pcm_timemux_0_2 : entity is "yes";
  attribute ip_definition_source : string;
  attribute ip_definition_source of pdm_to_pcm_timemux_0_2 : entity is "module_ref";
  attribute x_core_info : string;
  attribute x_core_info of pdm_to_pcm_timemux_0_2 : entity is "timemux,Vivado 2019.1";
end pdm_to_pcm_timemux_0_2;

architecture STRUCTURE of pdm_to_pcm_timemux_0_2 is
  signal \<const0>\ : STD_LOGIC;
  signal \<const1>\ : STD_LOGIC;
  signal \^pdm_data_mux\ : STD_LOGIC_VECTOR ( 1 to 1 );
  signal \^start\ : STD_LOGIC;
  attribute x_interface_info : string;
  attribute x_interface_info of clk : signal is "xilinx.com:signal:clock:1.0 clk CLK";
  attribute x_interface_parameter : string;
  attribute x_interface_parameter of clk : signal is "XIL_INTERFACENAME clk, ASSOCIATED_BUSIF data, FREQ_HZ 12800000, PHASE 0.0, CLK_DOMAIN /clk_wiz_0_clk_out1, INSERT_VIP 0";
  attribute x_interface_info of data_tlast : signal is "xilinx.com:interface:axis:1.0 data TLAST";
  attribute x_interface_info of data_tvalid : signal is "xilinx.com:interface:axis:1.0 data TVALID";
  attribute x_interface_parameter of data_tvalid : signal is "XIL_INTERFACENAME data, TDATA_NUM_BYTES 0, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 0, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 1, FREQ_HZ 12800000, PHASE 0.0, CLK_DOMAIN /clk_wiz_0_clk_out1, LAYERED_METADATA undef, INSERT_VIP 0";
begin
  \^start\ <= start;
  data_tvalid <= \^start\;
  pdm_data_mux(7) <= \<const0>\;
  pdm_data_mux(6) <= \<const0>\;
  pdm_data_mux(5) <= \<const0>\;
  pdm_data_mux(4) <= \<const0>\;
  pdm_data_mux(3) <= \<const0>\;
  pdm_data_mux(2) <= \<const0>\;
  pdm_data_mux(1) <= \^pdm_data_mux\(1);
  pdm_data_mux(0) <= \<const1>\;
GND: unisim.vcomponents.GND
     port map (
      G => \<const0>\
    );
U0: entity work.pdm_to_pcm_timemux_0_2_timemux
     port map (
      clk => clk,
      data_tlast => data_tlast,
      pdm_data(3 downto 0) => pdm_data(3 downto 0),
      pdm_data_mux(0) => \^pdm_data_mux\(1),
      start => \^start\
    );
VCC: unisim.vcomponents.VCC
     port map (
      P => \<const1>\
    );
end STRUCTURE;
