-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019
-- Date        : Sat Apr 11 22:27:18 2020
-- Host        : LAPTOP-RJQ3H7G3 running 64-bit major release  (build 9200)
-- Command     : write_vhdl -force -mode funcsim
--               D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/ip/pdm_to_pcm_clk_div_1_0/pdm_to_pcm_clk_div_1_0_sim_netlist.vhdl
-- Design      : pdm_to_pcm_clk_div_1_0
-- Purpose     : This VHDL netlist is a functional simulation representation of the design and should not be modified or
--               synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device      : xc7a200tfbg676-2
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity pdm_to_pcm_clk_div_1_0_clk_div is
  port (
    clk_out : out STD_LOGIC;
    clk_en : in STD_LOGIC;
    clr : in STD_LOGIC;
    clk_in : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of pdm_to_pcm_clk_div_1_0_clk_div : entity is "clk_div";
end pdm_to_pcm_clk_div_1_0_clk_div;

architecture STRUCTURE of pdm_to_pcm_clk_div_1_0_clk_div is
  attribute box_type : string;
  attribute box_type of BUFR_inst : label is "PRIMITIVE";
begin
BUFR_inst: unisim.vcomponents.BUFR
    generic map(
      BUFR_DIVIDE => "2",
      SIM_DEVICE => "7SERIES"
    )
        port map (
      CE => clk_en,
      CLR => clr,
      I => clk_in,
      O => clk_out
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity pdm_to_pcm_clk_div_1_0 is
  port (
    clk_out : out STD_LOGIC;
    clk_in : in STD_LOGIC;
    clk_en : in STD_LOGIC;
    clr : in STD_LOGIC
  );
  attribute NotValidForBitStream : boolean;
  attribute NotValidForBitStream of pdm_to_pcm_clk_div_1_0 : entity is true;
  attribute CHECK_LICENSE_TYPE : string;
  attribute CHECK_LICENSE_TYPE of pdm_to_pcm_clk_div_1_0 : entity is "pdm_to_pcm_clk_div_1_0,clk_div,{}";
  attribute downgradeipidentifiedwarnings : string;
  attribute downgradeipidentifiedwarnings of pdm_to_pcm_clk_div_1_0 : entity is "yes";
  attribute ip_definition_source : string;
  attribute ip_definition_source of pdm_to_pcm_clk_div_1_0 : entity is "module_ref";
  attribute x_core_info : string;
  attribute x_core_info of pdm_to_pcm_clk_div_1_0 : entity is "clk_div,Vivado 2019.1";
end pdm_to_pcm_clk_div_1_0;

architecture STRUCTURE of pdm_to_pcm_clk_div_1_0 is
begin
U0: entity work.pdm_to_pcm_clk_div_1_0_clk_div
     port map (
      clk_en => clk_en,
      clk_in => clk_in,
      clk_out => clk_out,
      clr => clr
    );
end STRUCTURE;
