-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019
-- Date        : Tue May 26 02:41:24 2020
-- Host        : LAPTOP-RJQ3H7G3 running 64-bit major release  (build 9200)
-- Command     : write_vhdl -force -mode funcsim
--               d:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/ip/pdm_to_pcm_arithm_block_0_0/pdm_to_pcm_arithm_block_0_0_sim_netlist.vhdl
-- Design      : pdm_to_pcm_arithm_block_0_0
-- Purpose     : This VHDL netlist is a functional simulation representation of the design and should not be modified or
--               synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device      : xc7a200tfbg676-2
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity pdm_to_pcm_arithm_block_0_0_arithm_block is
  port (
    val_out : out STD_LOGIC_VECTOR ( 30 downto 0 );
    smand0 : in STD_LOGIC_VECTOR ( 15 downto 0 );
    smand1 : in STD_LOGIC_VECTOR ( 15 downto 0 );
    smand2 : in STD_LOGIC_VECTOR ( 15 downto 0 );
    smand3 : in STD_LOGIC_VECTOR ( 15 downto 0 );
    adder_enable : in STD_LOGIC;
    clk : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of pdm_to_pcm_arithm_block_0_0_arithm_block : entity is "arithm_block";
end pdm_to_pcm_arithm_block_0_0_arithm_block;

architecture STRUCTURE of pdm_to_pcm_arithm_block_0_0_arithm_block is
  signal ARG : STD_LOGIC_VECTOR ( 16 downto 0 );
  signal \sq_reg[-1111111096]__0_n_0\ : STD_LOGIC;
  signal \sq_reg[-1111111097]__0_n_0\ : STD_LOGIC;
  signal \sq_reg[-1111111098]__0_n_0\ : STD_LOGIC;
  signal \sq_reg[-1111111099]__0_n_0\ : STD_LOGIC;
  signal \sq_reg[-1111111100]__0_n_0\ : STD_LOGIC;
  signal \sq_reg[-1111111101]__0_n_0\ : STD_LOGIC;
  signal \sq_reg[-1111111102]__0_n_0\ : STD_LOGIC;
  signal \sq_reg[-1111111103]__0_n_0\ : STD_LOGIC;
  signal \sq_reg[-1111111104]__0_n_0\ : STD_LOGIC;
  signal \sq_reg[-1111111105]__0_n_0\ : STD_LOGIC;
  signal \sq_reg[-1111111106]__0_n_0\ : STD_LOGIC;
  signal \sq_reg[-1111111107]__0_n_0\ : STD_LOGIC;
  signal \sq_reg[-1111111108]__0_n_0\ : STD_LOGIC;
  signal \sq_reg[-1111111109]__0_n_0\ : STD_LOGIC;
  signal \sq_reg[-1111111110]__0_n_0\ : STD_LOGIC;
  signal \sq_reg[-1111111111]__0_n_0\ : STD_LOGIC;
  signal \sq_reg[-_n_0_1111111096]\ : STD_LOGIC;
  signal \sq_reg[-_n_0_1111111097]\ : STD_LOGIC;
  signal \sq_reg[-_n_0_1111111098]\ : STD_LOGIC;
  signal \sq_reg[-_n_0_1111111099]\ : STD_LOGIC;
  signal \sq_reg[-_n_0_1111111100]\ : STD_LOGIC;
  signal \sq_reg[-_n_0_1111111101]\ : STD_LOGIC;
  signal \sq_reg[-_n_0_1111111102]\ : STD_LOGIC;
  signal \sq_reg[-_n_0_1111111103]\ : STD_LOGIC;
  signal \sq_reg[-_n_0_1111111104]\ : STD_LOGIC;
  signal \sq_reg[-_n_0_1111111105]\ : STD_LOGIC;
  signal \sq_reg[-_n_0_1111111106]\ : STD_LOGIC;
  signal \sq_reg[-_n_0_1111111107]\ : STD_LOGIC;
  signal \sq_reg[-_n_0_1111111108]\ : STD_LOGIC;
  signal \sq_reg[-_n_0_1111111109]\ : STD_LOGIC;
  signal \sq_reg[-_n_0_1111111110]\ : STD_LOGIC;
  signal \sq_reg[-_n_0_1111111111]\ : STD_LOGIC;
  signal sq_reg_i_10_n_1 : STD_LOGIC;
  signal sq_reg_i_10_n_2 : STD_LOGIC;
  signal sq_reg_i_10_n_3 : STD_LOGIC;
  signal sq_reg_i_10_n_4 : STD_LOGIC;
  signal sq_reg_i_10_n_5 : STD_LOGIC;
  signal sq_reg_i_10_n_6 : STD_LOGIC;
  signal sq_reg_i_10_n_7 : STD_LOGIC;
  signal sq_reg_i_11_n_0 : STD_LOGIC;
  signal sq_reg_i_11_n_1 : STD_LOGIC;
  signal sq_reg_i_11_n_2 : STD_LOGIC;
  signal sq_reg_i_11_n_3 : STD_LOGIC;
  signal sq_reg_i_11_n_4 : STD_LOGIC;
  signal sq_reg_i_11_n_5 : STD_LOGIC;
  signal sq_reg_i_11_n_6 : STD_LOGIC;
  signal sq_reg_i_11_n_7 : STD_LOGIC;
  signal sq_reg_i_12_n_0 : STD_LOGIC;
  signal sq_reg_i_12_n_1 : STD_LOGIC;
  signal sq_reg_i_12_n_2 : STD_LOGIC;
  signal sq_reg_i_12_n_3 : STD_LOGIC;
  signal sq_reg_i_12_n_4 : STD_LOGIC;
  signal sq_reg_i_12_n_5 : STD_LOGIC;
  signal sq_reg_i_12_n_6 : STD_LOGIC;
  signal sq_reg_i_12_n_7 : STD_LOGIC;
  signal sq_reg_i_13_n_0 : STD_LOGIC;
  signal sq_reg_i_13_n_1 : STD_LOGIC;
  signal sq_reg_i_13_n_2 : STD_LOGIC;
  signal sq_reg_i_13_n_3 : STD_LOGIC;
  signal sq_reg_i_13_n_4 : STD_LOGIC;
  signal sq_reg_i_13_n_5 : STD_LOGIC;
  signal sq_reg_i_13_n_6 : STD_LOGIC;
  signal sq_reg_i_13_n_7 : STD_LOGIC;
  signal sq_reg_i_14_n_0 : STD_LOGIC;
  signal sq_reg_i_15_n_0 : STD_LOGIC;
  signal sq_reg_i_16_n_0 : STD_LOGIC;
  signal sq_reg_i_17_n_0 : STD_LOGIC;
  signal sq_reg_i_18_n_0 : STD_LOGIC;
  signal sq_reg_i_19_n_0 : STD_LOGIC;
  signal sq_reg_i_20_n_0 : STD_LOGIC;
  signal sq_reg_i_21_n_0 : STD_LOGIC;
  signal sq_reg_i_22_n_0 : STD_LOGIC;
  signal sq_reg_i_23_n_0 : STD_LOGIC;
  signal sq_reg_i_24_n_0 : STD_LOGIC;
  signal sq_reg_i_25_n_0 : STD_LOGIC;
  signal sq_reg_i_26_n_0 : STD_LOGIC;
  signal sq_reg_i_27_n_0 : STD_LOGIC;
  signal sq_reg_i_28_n_0 : STD_LOGIC;
  signal sq_reg_i_29_n_0 : STD_LOGIC;
  signal sq_reg_i_2_n_0 : STD_LOGIC;
  signal sq_reg_i_2_n_1 : STD_LOGIC;
  signal sq_reg_i_2_n_2 : STD_LOGIC;
  signal sq_reg_i_2_n_3 : STD_LOGIC;
  signal sq_reg_i_30_n_0 : STD_LOGIC;
  signal sq_reg_i_31_n_0 : STD_LOGIC;
  signal sq_reg_i_32_n_0 : STD_LOGIC;
  signal sq_reg_i_33_n_0 : STD_LOGIC;
  signal sq_reg_i_34_n_0 : STD_LOGIC;
  signal sq_reg_i_35_n_0 : STD_LOGIC;
  signal sq_reg_i_36_n_0 : STD_LOGIC;
  signal sq_reg_i_37_n_0 : STD_LOGIC;
  signal sq_reg_i_38_n_0 : STD_LOGIC;
  signal sq_reg_i_39_n_0 : STD_LOGIC;
  signal sq_reg_i_3_n_0 : STD_LOGIC;
  signal sq_reg_i_3_n_1 : STD_LOGIC;
  signal sq_reg_i_3_n_2 : STD_LOGIC;
  signal sq_reg_i_3_n_3 : STD_LOGIC;
  signal sq_reg_i_40_n_0 : STD_LOGIC;
  signal sq_reg_i_41_n_0 : STD_LOGIC;
  signal sq_reg_i_42_n_0 : STD_LOGIC;
  signal sq_reg_i_43_n_0 : STD_LOGIC;
  signal sq_reg_i_44_n_0 : STD_LOGIC;
  signal sq_reg_i_45_n_0 : STD_LOGIC;
  signal sq_reg_i_46_n_0 : STD_LOGIC;
  signal sq_reg_i_47_n_0 : STD_LOGIC;
  signal sq_reg_i_48_n_0 : STD_LOGIC;
  signal sq_reg_i_49_n_0 : STD_LOGIC;
  signal sq_reg_i_4_n_0 : STD_LOGIC;
  signal sq_reg_i_4_n_1 : STD_LOGIC;
  signal sq_reg_i_4_n_2 : STD_LOGIC;
  signal sq_reg_i_4_n_3 : STD_LOGIC;
  signal sq_reg_i_50_n_0 : STD_LOGIC;
  signal sq_reg_i_51_n_0 : STD_LOGIC;
  signal sq_reg_i_52_n_0 : STD_LOGIC;
  signal sq_reg_i_53_n_0 : STD_LOGIC;
  signal sq_reg_i_54_n_0 : STD_LOGIC;
  signal sq_reg_i_55_n_0 : STD_LOGIC;
  signal sq_reg_i_56_n_0 : STD_LOGIC;
  signal sq_reg_i_57_n_0 : STD_LOGIC;
  signal sq_reg_i_58_n_0 : STD_LOGIC;
  signal sq_reg_i_59_n_0 : STD_LOGIC;
  signal sq_reg_i_5_n_0 : STD_LOGIC;
  signal sq_reg_i_5_n_1 : STD_LOGIC;
  signal sq_reg_i_5_n_2 : STD_LOGIC;
  signal sq_reg_i_5_n_3 : STD_LOGIC;
  signal sq_reg_i_60_n_0 : STD_LOGIC;
  signal sq_reg_i_61_n_0 : STD_LOGIC;
  signal sq_reg_i_62_n_0 : STD_LOGIC;
  signal sq_reg_i_6_n_1 : STD_LOGIC;
  signal sq_reg_i_6_n_2 : STD_LOGIC;
  signal sq_reg_i_6_n_3 : STD_LOGIC;
  signal sq_reg_i_6_n_4 : STD_LOGIC;
  signal sq_reg_i_6_n_5 : STD_LOGIC;
  signal sq_reg_i_6_n_6 : STD_LOGIC;
  signal sq_reg_i_6_n_7 : STD_LOGIC;
  signal sq_reg_i_7_n_0 : STD_LOGIC;
  signal sq_reg_i_7_n_1 : STD_LOGIC;
  signal sq_reg_i_7_n_2 : STD_LOGIC;
  signal sq_reg_i_7_n_3 : STD_LOGIC;
  signal sq_reg_i_7_n_4 : STD_LOGIC;
  signal sq_reg_i_7_n_5 : STD_LOGIC;
  signal sq_reg_i_7_n_6 : STD_LOGIC;
  signal sq_reg_i_7_n_7 : STD_LOGIC;
  signal sq_reg_i_8_n_0 : STD_LOGIC;
  signal sq_reg_i_8_n_1 : STD_LOGIC;
  signal sq_reg_i_8_n_2 : STD_LOGIC;
  signal sq_reg_i_8_n_3 : STD_LOGIC;
  signal sq_reg_i_8_n_4 : STD_LOGIC;
  signal sq_reg_i_8_n_5 : STD_LOGIC;
  signal sq_reg_i_8_n_6 : STD_LOGIC;
  signal sq_reg_i_8_n_7 : STD_LOGIC;
  signal sq_reg_i_9_n_0 : STD_LOGIC;
  signal sq_reg_i_9_n_1 : STD_LOGIC;
  signal sq_reg_i_9_n_2 : STD_LOGIC;
  signal sq_reg_i_9_n_3 : STD_LOGIC;
  signal sq_reg_i_9_n_4 : STD_LOGIC;
  signal sq_reg_i_9_n_5 : STD_LOGIC;
  signal sq_reg_i_9_n_6 : STD_LOGIC;
  signal sq_reg_i_9_n_7 : STD_LOGIC;
  signal sq_reg_n_102 : STD_LOGIC;
  signal sq_reg_n_103 : STD_LOGIC;
  signal sq_reg_n_104 : STD_LOGIC;
  signal sq_reg_n_105 : STD_LOGIC;
  signal NLW_sq_reg_CARRYCASCOUT_UNCONNECTED : STD_LOGIC;
  signal NLW_sq_reg_MULTSIGNOUT_UNCONNECTED : STD_LOGIC;
  signal NLW_sq_reg_OVERFLOW_UNCONNECTED : STD_LOGIC;
  signal NLW_sq_reg_PATTERNBDETECT_UNCONNECTED : STD_LOGIC;
  signal NLW_sq_reg_PATTERNDETECT_UNCONNECTED : STD_LOGIC;
  signal NLW_sq_reg_UNDERFLOW_UNCONNECTED : STD_LOGIC;
  signal NLW_sq_reg_ACOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 29 downto 0 );
  signal NLW_sq_reg_BCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 17 downto 0 );
  signal NLW_sq_reg_CARRYOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal NLW_sq_reg_P_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 35 );
  signal NLW_sq_reg_PCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 0 );
  signal NLW_sq_reg_i_1_CO_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal NLW_sq_reg_i_1_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 1 );
  signal NLW_sq_reg_i_10_CO_UNCONNECTED : STD_LOGIC_VECTOR ( 3 to 3 );
  signal NLW_sq_reg_i_6_CO_UNCONNECTED : STD_LOGIC_VECTOR ( 3 to 3 );
begin
sq_reg: unisim.vcomponents.DSP48E1
    generic map(
      ACASCREG => 1,
      ADREG => 1,
      ALUMODEREG => 0,
      AREG => 1,
      AUTORESET_PATDET => "NO_RESET",
      A_INPUT => "DIRECT",
      BCASCREG => 1,
      BREG => 1,
      B_INPUT => "DIRECT",
      CARRYINREG => 0,
      CARRYINSELREG => 0,
      CREG => 1,
      DREG => 1,
      INMODEREG => 0,
      MASK => X"3FFFFFFFFFFF",
      MREG => 1,
      OPMODEREG => 0,
      PATTERN => X"000000000000",
      PREG => 1,
      SEL_MASK => "MASK",
      SEL_PATTERN => "PATTERN",
      USE_DPORT => true,
      USE_MULT => "MULTIPLY",
      USE_PATTERN_DETECT => "NO_PATDET",
      USE_SIMD => "ONE48"
    )
        port map (
      A(29) => sq_reg_i_10_n_4,
      A(28) => sq_reg_i_10_n_4,
      A(27) => sq_reg_i_10_n_4,
      A(26) => sq_reg_i_10_n_4,
      A(25) => sq_reg_i_10_n_4,
      A(24) => sq_reg_i_10_n_4,
      A(23) => sq_reg_i_10_n_4,
      A(22) => sq_reg_i_10_n_4,
      A(21) => sq_reg_i_10_n_4,
      A(20) => sq_reg_i_10_n_4,
      A(19) => sq_reg_i_10_n_4,
      A(18) => sq_reg_i_10_n_4,
      A(17) => sq_reg_i_10_n_4,
      A(16) => sq_reg_i_10_n_4,
      A(15) => sq_reg_i_10_n_4,
      A(14) => sq_reg_i_10_n_5,
      A(13) => sq_reg_i_10_n_6,
      A(12) => sq_reg_i_10_n_7,
      A(11) => sq_reg_i_11_n_4,
      A(10) => sq_reg_i_11_n_5,
      A(9) => sq_reg_i_11_n_6,
      A(8) => sq_reg_i_11_n_7,
      A(7) => sq_reg_i_12_n_4,
      A(6) => sq_reg_i_12_n_5,
      A(5) => sq_reg_i_12_n_6,
      A(4) => sq_reg_i_12_n_7,
      A(3) => sq_reg_i_13_n_4,
      A(2) => sq_reg_i_13_n_5,
      A(1) => sq_reg_i_13_n_6,
      A(0) => sq_reg_i_13_n_7,
      ACIN(29 downto 0) => B"000000000000000000000000000000",
      ACOUT(29 downto 0) => NLW_sq_reg_ACOUT_UNCONNECTED(29 downto 0),
      ALUMODE(3 downto 0) => B"0000",
      B(17) => ARG(16),
      B(16 downto 0) => ARG(16 downto 0),
      BCIN(17 downto 0) => B"000000000000000000",
      BCOUT(17 downto 0) => NLW_sq_reg_BCOUT_UNCONNECTED(17 downto 0),
      C(47 downto 0) => B"111111111111111111111111111111111111111111111111",
      CARRYCASCIN => '0',
      CARRYCASCOUT => NLW_sq_reg_CARRYCASCOUT_UNCONNECTED,
      CARRYIN => '0',
      CARRYINSEL(2 downto 0) => B"000",
      CARRYOUT(3 downto 0) => NLW_sq_reg_CARRYOUT_UNCONNECTED(3 downto 0),
      CEA1 => '0',
      CEA2 => adder_enable,
      CEAD => adder_enable,
      CEALUMODE => '0',
      CEB1 => '0',
      CEB2 => adder_enable,
      CEC => '0',
      CECARRYIN => '0',
      CECTRL => '0',
      CED => adder_enable,
      CEINMODE => '0',
      CEM => adder_enable,
      CEP => adder_enable,
      CLK => clk,
      D(24) => sq_reg_i_6_n_4,
      D(23) => sq_reg_i_6_n_4,
      D(22) => sq_reg_i_6_n_4,
      D(21) => sq_reg_i_6_n_4,
      D(20) => sq_reg_i_6_n_4,
      D(19) => sq_reg_i_6_n_4,
      D(18) => sq_reg_i_6_n_4,
      D(17) => sq_reg_i_6_n_4,
      D(16) => sq_reg_i_6_n_4,
      D(15) => sq_reg_i_6_n_4,
      D(14) => sq_reg_i_6_n_5,
      D(13) => sq_reg_i_6_n_6,
      D(12) => sq_reg_i_6_n_7,
      D(11) => sq_reg_i_7_n_4,
      D(10) => sq_reg_i_7_n_5,
      D(9) => sq_reg_i_7_n_6,
      D(8) => sq_reg_i_7_n_7,
      D(7) => sq_reg_i_8_n_4,
      D(6) => sq_reg_i_8_n_5,
      D(5) => sq_reg_i_8_n_6,
      D(4) => sq_reg_i_8_n_7,
      D(3) => sq_reg_i_9_n_4,
      D(2) => sq_reg_i_9_n_5,
      D(1) => sq_reg_i_9_n_6,
      D(0) => sq_reg_i_9_n_7,
      INMODE(4 downto 0) => B"00100",
      MULTSIGNIN => '0',
      MULTSIGNOUT => NLW_sq_reg_MULTSIGNOUT_UNCONNECTED,
      OPMODE(6 downto 0) => B"0000101",
      OVERFLOW => NLW_sq_reg_OVERFLOW_UNCONNECTED,
      P(47 downto 35) => NLW_sq_reg_P_UNCONNECTED(47 downto 35),
      P(34 downto 4) => val_out(30 downto 0),
      P(3) => sq_reg_n_102,
      P(2) => sq_reg_n_103,
      P(1) => sq_reg_n_104,
      P(0) => sq_reg_n_105,
      PATTERNBDETECT => NLW_sq_reg_PATTERNBDETECT_UNCONNECTED,
      PATTERNDETECT => NLW_sq_reg_PATTERNDETECT_UNCONNECTED,
      PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
      PCOUT(47 downto 0) => NLW_sq_reg_PCOUT_UNCONNECTED(47 downto 0),
      RSTA => '0',
      RSTALLCARRYIN => '0',
      RSTALUMODE => '0',
      RSTB => '0',
      RSTC => '0',
      RSTCTRL => '0',
      RSTD => '0',
      RSTINMODE => '0',
      RSTM => '0',
      RSTP => '0',
      UNDERFLOW => NLW_sq_reg_UNDERFLOW_UNCONNECTED
    );
\sq_reg[-1111111096]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => adder_enable,
      D => sq_reg_i_10_n_4,
      Q => \sq_reg[-_n_0_1111111096]\,
      R => '0'
    );
\sq_reg[-1111111096]__0\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => adder_enable,
      D => sq_reg_i_6_n_4,
      Q => \sq_reg[-1111111096]__0_n_0\,
      R => '0'
    );
\sq_reg[-1111111097]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => adder_enable,
      D => sq_reg_i_10_n_5,
      Q => \sq_reg[-_n_0_1111111097]\,
      R => '0'
    );
\sq_reg[-1111111097]__0\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => adder_enable,
      D => sq_reg_i_6_n_5,
      Q => \sq_reg[-1111111097]__0_n_0\,
      R => '0'
    );
\sq_reg[-1111111098]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => adder_enable,
      D => sq_reg_i_10_n_6,
      Q => \sq_reg[-_n_0_1111111098]\,
      R => '0'
    );
\sq_reg[-1111111098]__0\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => adder_enable,
      D => sq_reg_i_6_n_6,
      Q => \sq_reg[-1111111098]__0_n_0\,
      R => '0'
    );
\sq_reg[-1111111099]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => adder_enable,
      D => sq_reg_i_10_n_7,
      Q => \sq_reg[-_n_0_1111111099]\,
      R => '0'
    );
\sq_reg[-1111111099]__0\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => adder_enable,
      D => sq_reg_i_6_n_7,
      Q => \sq_reg[-1111111099]__0_n_0\,
      R => '0'
    );
\sq_reg[-1111111100]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => adder_enable,
      D => sq_reg_i_11_n_4,
      Q => \sq_reg[-_n_0_1111111100]\,
      R => '0'
    );
\sq_reg[-1111111100]__0\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => adder_enable,
      D => sq_reg_i_7_n_4,
      Q => \sq_reg[-1111111100]__0_n_0\,
      R => '0'
    );
\sq_reg[-1111111101]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => adder_enable,
      D => sq_reg_i_11_n_5,
      Q => \sq_reg[-_n_0_1111111101]\,
      R => '0'
    );
\sq_reg[-1111111101]__0\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => adder_enable,
      D => sq_reg_i_7_n_5,
      Q => \sq_reg[-1111111101]__0_n_0\,
      R => '0'
    );
\sq_reg[-1111111102]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => adder_enable,
      D => sq_reg_i_11_n_6,
      Q => \sq_reg[-_n_0_1111111102]\,
      R => '0'
    );
\sq_reg[-1111111102]__0\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => adder_enable,
      D => sq_reg_i_7_n_6,
      Q => \sq_reg[-1111111102]__0_n_0\,
      R => '0'
    );
\sq_reg[-1111111103]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => adder_enable,
      D => sq_reg_i_11_n_7,
      Q => \sq_reg[-_n_0_1111111103]\,
      R => '0'
    );
\sq_reg[-1111111103]__0\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => adder_enable,
      D => sq_reg_i_7_n_7,
      Q => \sq_reg[-1111111103]__0_n_0\,
      R => '0'
    );
\sq_reg[-1111111104]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => adder_enable,
      D => sq_reg_i_12_n_4,
      Q => \sq_reg[-_n_0_1111111104]\,
      R => '0'
    );
\sq_reg[-1111111104]__0\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => adder_enable,
      D => sq_reg_i_8_n_4,
      Q => \sq_reg[-1111111104]__0_n_0\,
      R => '0'
    );
\sq_reg[-1111111105]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => adder_enable,
      D => sq_reg_i_12_n_5,
      Q => \sq_reg[-_n_0_1111111105]\,
      R => '0'
    );
\sq_reg[-1111111105]__0\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => adder_enable,
      D => sq_reg_i_8_n_5,
      Q => \sq_reg[-1111111105]__0_n_0\,
      R => '0'
    );
\sq_reg[-1111111106]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => adder_enable,
      D => sq_reg_i_12_n_6,
      Q => \sq_reg[-_n_0_1111111106]\,
      R => '0'
    );
\sq_reg[-1111111106]__0\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => adder_enable,
      D => sq_reg_i_8_n_6,
      Q => \sq_reg[-1111111106]__0_n_0\,
      R => '0'
    );
\sq_reg[-1111111107]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => adder_enable,
      D => sq_reg_i_12_n_7,
      Q => \sq_reg[-_n_0_1111111107]\,
      R => '0'
    );
\sq_reg[-1111111107]__0\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => adder_enable,
      D => sq_reg_i_8_n_7,
      Q => \sq_reg[-1111111107]__0_n_0\,
      R => '0'
    );
\sq_reg[-1111111108]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => adder_enable,
      D => sq_reg_i_13_n_4,
      Q => \sq_reg[-_n_0_1111111108]\,
      R => '0'
    );
\sq_reg[-1111111108]__0\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => adder_enable,
      D => sq_reg_i_9_n_4,
      Q => \sq_reg[-1111111108]__0_n_0\,
      R => '0'
    );
\sq_reg[-1111111109]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => adder_enable,
      D => sq_reg_i_13_n_5,
      Q => \sq_reg[-_n_0_1111111109]\,
      R => '0'
    );
\sq_reg[-1111111109]__0\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => adder_enable,
      D => sq_reg_i_9_n_5,
      Q => \sq_reg[-1111111109]__0_n_0\,
      R => '0'
    );
\sq_reg[-1111111110]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => adder_enable,
      D => sq_reg_i_13_n_6,
      Q => \sq_reg[-_n_0_1111111110]\,
      R => '0'
    );
\sq_reg[-1111111110]__0\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => adder_enable,
      D => sq_reg_i_9_n_6,
      Q => \sq_reg[-1111111110]__0_n_0\,
      R => '0'
    );
\sq_reg[-1111111111]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => adder_enable,
      D => sq_reg_i_13_n_7,
      Q => \sq_reg[-_n_0_1111111111]\,
      R => '0'
    );
\sq_reg[-1111111111]__0\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => adder_enable,
      D => sq_reg_i_9_n_7,
      Q => \sq_reg[-1111111111]__0_n_0\,
      R => '0'
    );
sq_reg_i_1: unisim.vcomponents.CARRY4
     port map (
      CI => sq_reg_i_2_n_0,
      CO(3 downto 0) => NLW_sq_reg_i_1_CO_UNCONNECTED(3 downto 0),
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3 downto 1) => NLW_sq_reg_i_1_O_UNCONNECTED(3 downto 1),
      O(0) => ARG(16),
      S(3 downto 0) => B"0001"
    );
sq_reg_i_10: unisim.vcomponents.CARRY4
     port map (
      CI => sq_reg_i_11_n_0,
      CO(3) => NLW_sq_reg_i_10_CO_UNCONNECTED(3),
      CO(2) => sq_reg_i_10_n_1,
      CO(1) => sq_reg_i_10_n_2,
      CO(0) => sq_reg_i_10_n_3,
      CYINIT => '0',
      DI(3) => '0',
      DI(2 downto 0) => smand2(14 downto 12),
      O(3) => sq_reg_i_10_n_4,
      O(2) => sq_reg_i_10_n_5,
      O(1) => sq_reg_i_10_n_6,
      O(0) => sq_reg_i_10_n_7,
      S(3) => sq_reg_i_47_n_0,
      S(2) => sq_reg_i_48_n_0,
      S(1) => sq_reg_i_49_n_0,
      S(0) => sq_reg_i_50_n_0
    );
sq_reg_i_11: unisim.vcomponents.CARRY4
     port map (
      CI => sq_reg_i_12_n_0,
      CO(3) => sq_reg_i_11_n_0,
      CO(2) => sq_reg_i_11_n_1,
      CO(1) => sq_reg_i_11_n_2,
      CO(0) => sq_reg_i_11_n_3,
      CYINIT => '0',
      DI(3 downto 0) => smand2(11 downto 8),
      O(3) => sq_reg_i_11_n_4,
      O(2) => sq_reg_i_11_n_5,
      O(1) => sq_reg_i_11_n_6,
      O(0) => sq_reg_i_11_n_7,
      S(3) => sq_reg_i_51_n_0,
      S(2) => sq_reg_i_52_n_0,
      S(1) => sq_reg_i_53_n_0,
      S(0) => sq_reg_i_54_n_0
    );
sq_reg_i_12: unisim.vcomponents.CARRY4
     port map (
      CI => sq_reg_i_13_n_0,
      CO(3) => sq_reg_i_12_n_0,
      CO(2) => sq_reg_i_12_n_1,
      CO(1) => sq_reg_i_12_n_2,
      CO(0) => sq_reg_i_12_n_3,
      CYINIT => '0',
      DI(3 downto 0) => smand2(7 downto 4),
      O(3) => sq_reg_i_12_n_4,
      O(2) => sq_reg_i_12_n_5,
      O(1) => sq_reg_i_12_n_6,
      O(0) => sq_reg_i_12_n_7,
      S(3) => sq_reg_i_55_n_0,
      S(2) => sq_reg_i_56_n_0,
      S(1) => sq_reg_i_57_n_0,
      S(0) => sq_reg_i_58_n_0
    );
sq_reg_i_13: unisim.vcomponents.CARRY4
     port map (
      CI => '0',
      CO(3) => sq_reg_i_13_n_0,
      CO(2) => sq_reg_i_13_n_1,
      CO(1) => sq_reg_i_13_n_2,
      CO(0) => sq_reg_i_13_n_3,
      CYINIT => '0',
      DI(3 downto 0) => smand2(3 downto 0),
      O(3) => sq_reg_i_13_n_4,
      O(2) => sq_reg_i_13_n_5,
      O(1) => sq_reg_i_13_n_6,
      O(0) => sq_reg_i_13_n_7,
      S(3) => sq_reg_i_59_n_0,
      S(2) => sq_reg_i_60_n_0,
      S(1) => sq_reg_i_61_n_0,
      S(0) => sq_reg_i_62_n_0
    );
sq_reg_i_14: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \sq_reg[-1111111096]__0_n_0\,
      O => sq_reg_i_14_n_0
    );
sq_reg_i_15: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \sq_reg[-1111111096]__0_n_0\,
      I1 => \sq_reg[-_n_0_1111111096]\,
      O => sq_reg_i_15_n_0
    );
sq_reg_i_16: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \sq_reg[-1111111097]__0_n_0\,
      I1 => \sq_reg[-_n_0_1111111097]\,
      O => sq_reg_i_16_n_0
    );
sq_reg_i_17: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \sq_reg[-1111111098]__0_n_0\,
      I1 => \sq_reg[-_n_0_1111111098]\,
      O => sq_reg_i_17_n_0
    );
sq_reg_i_18: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \sq_reg[-1111111099]__0_n_0\,
      I1 => \sq_reg[-_n_0_1111111099]\,
      O => sq_reg_i_18_n_0
    );
sq_reg_i_19: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \sq_reg[-1111111100]__0_n_0\,
      I1 => \sq_reg[-_n_0_1111111100]\,
      O => sq_reg_i_19_n_0
    );
sq_reg_i_2: unisim.vcomponents.CARRY4
     port map (
      CI => sq_reg_i_3_n_0,
      CO(3) => sq_reg_i_2_n_0,
      CO(2) => sq_reg_i_2_n_1,
      CO(1) => sq_reg_i_2_n_2,
      CO(0) => sq_reg_i_2_n_3,
      CYINIT => '0',
      DI(3) => sq_reg_i_14_n_0,
      DI(2) => \sq_reg[-1111111097]__0_n_0\,
      DI(1) => \sq_reg[-1111111098]__0_n_0\,
      DI(0) => \sq_reg[-1111111099]__0_n_0\,
      O(3 downto 0) => ARG(15 downto 12),
      S(3) => sq_reg_i_15_n_0,
      S(2) => sq_reg_i_16_n_0,
      S(1) => sq_reg_i_17_n_0,
      S(0) => sq_reg_i_18_n_0
    );
sq_reg_i_20: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \sq_reg[-1111111101]__0_n_0\,
      I1 => \sq_reg[-_n_0_1111111101]\,
      O => sq_reg_i_20_n_0
    );
sq_reg_i_21: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \sq_reg[-1111111102]__0_n_0\,
      I1 => \sq_reg[-_n_0_1111111102]\,
      O => sq_reg_i_21_n_0
    );
sq_reg_i_22: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \sq_reg[-1111111103]__0_n_0\,
      I1 => \sq_reg[-_n_0_1111111103]\,
      O => sq_reg_i_22_n_0
    );
sq_reg_i_23: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \sq_reg[-1111111104]__0_n_0\,
      I1 => \sq_reg[-_n_0_1111111104]\,
      O => sq_reg_i_23_n_0
    );
sq_reg_i_24: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \sq_reg[-1111111105]__0_n_0\,
      I1 => \sq_reg[-_n_0_1111111105]\,
      O => sq_reg_i_24_n_0
    );
sq_reg_i_25: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \sq_reg[-1111111106]__0_n_0\,
      I1 => \sq_reg[-_n_0_1111111106]\,
      O => sq_reg_i_25_n_0
    );
sq_reg_i_26: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \sq_reg[-1111111107]__0_n_0\,
      I1 => \sq_reg[-_n_0_1111111107]\,
      O => sq_reg_i_26_n_0
    );
sq_reg_i_27: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \sq_reg[-1111111108]__0_n_0\,
      I1 => \sq_reg[-_n_0_1111111108]\,
      O => sq_reg_i_27_n_0
    );
sq_reg_i_28: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \sq_reg[-1111111109]__0_n_0\,
      I1 => \sq_reg[-_n_0_1111111109]\,
      O => sq_reg_i_28_n_0
    );
sq_reg_i_29: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \sq_reg[-1111111110]__0_n_0\,
      I1 => \sq_reg[-_n_0_1111111110]\,
      O => sq_reg_i_29_n_0
    );
sq_reg_i_3: unisim.vcomponents.CARRY4
     port map (
      CI => sq_reg_i_4_n_0,
      CO(3) => sq_reg_i_3_n_0,
      CO(2) => sq_reg_i_3_n_1,
      CO(1) => sq_reg_i_3_n_2,
      CO(0) => sq_reg_i_3_n_3,
      CYINIT => '0',
      DI(3) => \sq_reg[-1111111100]__0_n_0\,
      DI(2) => \sq_reg[-1111111101]__0_n_0\,
      DI(1) => \sq_reg[-1111111102]__0_n_0\,
      DI(0) => \sq_reg[-1111111103]__0_n_0\,
      O(3 downto 0) => ARG(11 downto 8),
      S(3) => sq_reg_i_19_n_0,
      S(2) => sq_reg_i_20_n_0,
      S(1) => sq_reg_i_21_n_0,
      S(0) => sq_reg_i_22_n_0
    );
sq_reg_i_30: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \sq_reg[-1111111111]__0_n_0\,
      I1 => \sq_reg[-_n_0_1111111111]\,
      O => sq_reg_i_30_n_0
    );
sq_reg_i_31: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => smand0(15),
      I1 => smand1(15),
      O => sq_reg_i_31_n_0
    );
sq_reg_i_32: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => smand0(14),
      I1 => smand1(14),
      O => sq_reg_i_32_n_0
    );
sq_reg_i_33: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => smand0(13),
      I1 => smand1(13),
      O => sq_reg_i_33_n_0
    );
sq_reg_i_34: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => smand0(12),
      I1 => smand1(12),
      O => sq_reg_i_34_n_0
    );
sq_reg_i_35: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => smand0(11),
      I1 => smand1(11),
      O => sq_reg_i_35_n_0
    );
sq_reg_i_36: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => smand0(10),
      I1 => smand1(10),
      O => sq_reg_i_36_n_0
    );
sq_reg_i_37: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => smand0(9),
      I1 => smand1(9),
      O => sq_reg_i_37_n_0
    );
sq_reg_i_38: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => smand0(8),
      I1 => smand1(8),
      O => sq_reg_i_38_n_0
    );
sq_reg_i_39: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => smand0(7),
      I1 => smand1(7),
      O => sq_reg_i_39_n_0
    );
sq_reg_i_4: unisim.vcomponents.CARRY4
     port map (
      CI => sq_reg_i_5_n_0,
      CO(3) => sq_reg_i_4_n_0,
      CO(2) => sq_reg_i_4_n_1,
      CO(1) => sq_reg_i_4_n_2,
      CO(0) => sq_reg_i_4_n_3,
      CYINIT => '0',
      DI(3) => \sq_reg[-1111111104]__0_n_0\,
      DI(2) => \sq_reg[-1111111105]__0_n_0\,
      DI(1) => \sq_reg[-1111111106]__0_n_0\,
      DI(0) => \sq_reg[-1111111107]__0_n_0\,
      O(3 downto 0) => ARG(7 downto 4),
      S(3) => sq_reg_i_23_n_0,
      S(2) => sq_reg_i_24_n_0,
      S(1) => sq_reg_i_25_n_0,
      S(0) => sq_reg_i_26_n_0
    );
sq_reg_i_40: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => smand0(6),
      I1 => smand1(6),
      O => sq_reg_i_40_n_0
    );
sq_reg_i_41: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => smand0(5),
      I1 => smand1(5),
      O => sq_reg_i_41_n_0
    );
sq_reg_i_42: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => smand0(4),
      I1 => smand1(4),
      O => sq_reg_i_42_n_0
    );
sq_reg_i_43: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => smand0(3),
      I1 => smand1(3),
      O => sq_reg_i_43_n_0
    );
sq_reg_i_44: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => smand0(2),
      I1 => smand1(2),
      O => sq_reg_i_44_n_0
    );
sq_reg_i_45: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => smand0(1),
      I1 => smand1(1),
      O => sq_reg_i_45_n_0
    );
sq_reg_i_46: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => smand0(0),
      I1 => smand1(0),
      O => sq_reg_i_46_n_0
    );
sq_reg_i_47: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => smand2(15),
      I1 => smand3(15),
      O => sq_reg_i_47_n_0
    );
sq_reg_i_48: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => smand2(14),
      I1 => smand3(14),
      O => sq_reg_i_48_n_0
    );
sq_reg_i_49: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => smand2(13),
      I1 => smand3(13),
      O => sq_reg_i_49_n_0
    );
sq_reg_i_5: unisim.vcomponents.CARRY4
     port map (
      CI => '0',
      CO(3) => sq_reg_i_5_n_0,
      CO(2) => sq_reg_i_5_n_1,
      CO(1) => sq_reg_i_5_n_2,
      CO(0) => sq_reg_i_5_n_3,
      CYINIT => '0',
      DI(3) => \sq_reg[-1111111108]__0_n_0\,
      DI(2) => \sq_reg[-1111111109]__0_n_0\,
      DI(1) => \sq_reg[-1111111110]__0_n_0\,
      DI(0) => \sq_reg[-1111111111]__0_n_0\,
      O(3 downto 0) => ARG(3 downto 0),
      S(3) => sq_reg_i_27_n_0,
      S(2) => sq_reg_i_28_n_0,
      S(1) => sq_reg_i_29_n_0,
      S(0) => sq_reg_i_30_n_0
    );
sq_reg_i_50: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => smand2(12),
      I1 => smand3(12),
      O => sq_reg_i_50_n_0
    );
sq_reg_i_51: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => smand2(11),
      I1 => smand3(11),
      O => sq_reg_i_51_n_0
    );
sq_reg_i_52: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => smand2(10),
      I1 => smand3(10),
      O => sq_reg_i_52_n_0
    );
sq_reg_i_53: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => smand2(9),
      I1 => smand3(9),
      O => sq_reg_i_53_n_0
    );
sq_reg_i_54: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => smand2(8),
      I1 => smand3(8),
      O => sq_reg_i_54_n_0
    );
sq_reg_i_55: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => smand2(7),
      I1 => smand3(7),
      O => sq_reg_i_55_n_0
    );
sq_reg_i_56: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => smand2(6),
      I1 => smand3(6),
      O => sq_reg_i_56_n_0
    );
sq_reg_i_57: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => smand2(5),
      I1 => smand3(5),
      O => sq_reg_i_57_n_0
    );
sq_reg_i_58: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => smand2(4),
      I1 => smand3(4),
      O => sq_reg_i_58_n_0
    );
sq_reg_i_59: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => smand2(3),
      I1 => smand3(3),
      O => sq_reg_i_59_n_0
    );
sq_reg_i_6: unisim.vcomponents.CARRY4
     port map (
      CI => sq_reg_i_7_n_0,
      CO(3) => NLW_sq_reg_i_6_CO_UNCONNECTED(3),
      CO(2) => sq_reg_i_6_n_1,
      CO(1) => sq_reg_i_6_n_2,
      CO(0) => sq_reg_i_6_n_3,
      CYINIT => '0',
      DI(3) => '0',
      DI(2 downto 0) => smand0(14 downto 12),
      O(3) => sq_reg_i_6_n_4,
      O(2) => sq_reg_i_6_n_5,
      O(1) => sq_reg_i_6_n_6,
      O(0) => sq_reg_i_6_n_7,
      S(3) => sq_reg_i_31_n_0,
      S(2) => sq_reg_i_32_n_0,
      S(1) => sq_reg_i_33_n_0,
      S(0) => sq_reg_i_34_n_0
    );
sq_reg_i_60: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => smand2(2),
      I1 => smand3(2),
      O => sq_reg_i_60_n_0
    );
sq_reg_i_61: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => smand2(1),
      I1 => smand3(1),
      O => sq_reg_i_61_n_0
    );
sq_reg_i_62: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => smand2(0),
      I1 => smand3(0),
      O => sq_reg_i_62_n_0
    );
sq_reg_i_7: unisim.vcomponents.CARRY4
     port map (
      CI => sq_reg_i_8_n_0,
      CO(3) => sq_reg_i_7_n_0,
      CO(2) => sq_reg_i_7_n_1,
      CO(1) => sq_reg_i_7_n_2,
      CO(0) => sq_reg_i_7_n_3,
      CYINIT => '0',
      DI(3 downto 0) => smand0(11 downto 8),
      O(3) => sq_reg_i_7_n_4,
      O(2) => sq_reg_i_7_n_5,
      O(1) => sq_reg_i_7_n_6,
      O(0) => sq_reg_i_7_n_7,
      S(3) => sq_reg_i_35_n_0,
      S(2) => sq_reg_i_36_n_0,
      S(1) => sq_reg_i_37_n_0,
      S(0) => sq_reg_i_38_n_0
    );
sq_reg_i_8: unisim.vcomponents.CARRY4
     port map (
      CI => sq_reg_i_9_n_0,
      CO(3) => sq_reg_i_8_n_0,
      CO(2) => sq_reg_i_8_n_1,
      CO(1) => sq_reg_i_8_n_2,
      CO(0) => sq_reg_i_8_n_3,
      CYINIT => '0',
      DI(3 downto 0) => smand0(7 downto 4),
      O(3) => sq_reg_i_8_n_4,
      O(2) => sq_reg_i_8_n_5,
      O(1) => sq_reg_i_8_n_6,
      O(0) => sq_reg_i_8_n_7,
      S(3) => sq_reg_i_39_n_0,
      S(2) => sq_reg_i_40_n_0,
      S(1) => sq_reg_i_41_n_0,
      S(0) => sq_reg_i_42_n_0
    );
sq_reg_i_9: unisim.vcomponents.CARRY4
     port map (
      CI => '0',
      CO(3) => sq_reg_i_9_n_0,
      CO(2) => sq_reg_i_9_n_1,
      CO(1) => sq_reg_i_9_n_2,
      CO(0) => sq_reg_i_9_n_3,
      CYINIT => '0',
      DI(3 downto 0) => smand0(3 downto 0),
      O(3) => sq_reg_i_9_n_4,
      O(2) => sq_reg_i_9_n_5,
      O(1) => sq_reg_i_9_n_6,
      O(0) => sq_reg_i_9_n_7,
      S(3) => sq_reg_i_43_n_0,
      S(2) => sq_reg_i_44_n_0,
      S(1) => sq_reg_i_45_n_0,
      S(0) => sq_reg_i_46_n_0
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity pdm_to_pcm_arithm_block_0_0 is
  port (
    clk : in STD_LOGIC;
    smand0 : in STD_LOGIC_VECTOR ( 15 downto 0 );
    smand1 : in STD_LOGIC_VECTOR ( 15 downto 0 );
    smand2 : in STD_LOGIC_VECTOR ( 15 downto 0 );
    smand3 : in STD_LOGIC_VECTOR ( 15 downto 0 );
    adder_enable : in STD_LOGIC;
    en_enable : out STD_LOGIC;
    val_out : out STD_LOGIC_VECTOR ( 31 downto 0 )
  );
  attribute NotValidForBitStream : boolean;
  attribute NotValidForBitStream of pdm_to_pcm_arithm_block_0_0 : entity is true;
  attribute CHECK_LICENSE_TYPE : string;
  attribute CHECK_LICENSE_TYPE of pdm_to_pcm_arithm_block_0_0 : entity is "pdm_to_pcm_arithm_block_0_0,arithm_block,{}";
  attribute downgradeipidentifiedwarnings : string;
  attribute downgradeipidentifiedwarnings of pdm_to_pcm_arithm_block_0_0 : entity is "yes";
  attribute ip_definition_source : string;
  attribute ip_definition_source of pdm_to_pcm_arithm_block_0_0 : entity is "module_ref";
  attribute x_core_info : string;
  attribute x_core_info of pdm_to_pcm_arithm_block_0_0 : entity is "arithm_block,Vivado 2019.1";
end pdm_to_pcm_arithm_block_0_0;

architecture STRUCTURE of pdm_to_pcm_arithm_block_0_0 is
  signal \<const1>\ : STD_LOGIC;
  signal \^val_out\ : STD_LOGIC_VECTOR ( 31 downto 0 );
  attribute x_interface_info : string;
  attribute x_interface_info of clk : signal is "xilinx.com:signal:clock:1.0 clk CLK";
  attribute x_interface_parameter : string;
  attribute x_interface_parameter of clk : signal is "XIL_INTERFACENAME clk, FREQ_HZ 100000000, PHASE 0.000, INSERT_VIP 0";
begin
  en_enable <= \<const1>\;
  val_out(31) <= \^val_out\(31);
  val_out(30) <= \^val_out\(31);
  val_out(29 downto 0) <= \^val_out\(29 downto 0);
U0: entity work.pdm_to_pcm_arithm_block_0_0_arithm_block
     port map (
      adder_enable => adder_enable,
      clk => clk,
      smand0(15 downto 0) => smand0(15 downto 0),
      smand1(15 downto 0) => smand1(15 downto 0),
      smand2(15 downto 0) => smand2(15 downto 0),
      smand3(15 downto 0) => smand3(15 downto 0),
      val_out(30) => \^val_out\(31),
      val_out(29 downto 0) => \^val_out\(29 downto 0)
    );
VCC: unisim.vcomponents.VCC
     port map (
      P => \<const1>\
    );
end STRUCTURE;
