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--*****************************************************************************


--   ____  ____


--  /   /\/   /


-- /___/  \  /   Vendor             : Xilinx


-- \   \   \/    Version            : 4.2


--  \   \        Application        : MIG


--  /   /        Filename           : mig.vho


-- /___/   /\    Date Last Modified : $Date: 2011/06/02 08:34:47 $


-- \   \  /  \   Date Created       : Tue Sept 21 2010


--  \___\/\___\


--


-- Device           : 7 Series


-- Design Name      : DDR3 SDRAM


-- Purpose          : Template file containing code that can be used as a model


--                    for instantiating a CORE Generator module in a HDL design.


-- Revision History :


--*****************************************************************************





-- The following must be inserted into your VHDL file for this


-- core to be instantiated. Change the instance name and port connections


-- to your own signal names.





------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG





component mig


  port (


      ddr3_dq       : inout std_logic_vector(63 downto 0);


      ddr3_dqs_p    : inout std_logic_vector(7 downto 0);


      ddr3_dqs_n    : inout std_logic_vector(7 downto 0);





      ddr3_addr     : out   std_logic_vector(13 downto 0);


      ddr3_ba       : out   std_logic_vector(2 downto 0);


      ddr3_ras_n    : out   std_logic;


      ddr3_cas_n    : out   std_logic;


      ddr3_we_n     : out   std_logic;


      ddr3_reset_n  : out   std_logic;


      ddr3_ck_p     : out   std_logic_vector(0 downto 0);


      ddr3_ck_n     : out   std_logic_vector(0 downto 0);


      ddr3_cke      : out   std_logic_vector(0 downto 0);


	  ddr3_cs_n     : out   std_logic_vector(0 downto 0);


      ddr3_dm       : out   std_logic_vector(7 downto 0);


      ddr3_odt      : out   std_logic_vector(0 downto 0);


      app_addr                  : in    std_logic_vector(27 downto 0);


      app_cmd                   : in    std_logic_vector(2 downto 0);


      app_en                    : in    std_logic;


      app_wdf_data              : in    std_logic_vector(511 downto 0);


      app_wdf_end               : in    std_logic;


      app_wdf_mask         : in    std_logic_vector(63 downto 0);


      app_wdf_wren              : in    std_logic;


      app_rd_data               : out   std_logic_vector(511 downto 0);


      app_rd_data_end           : out   std_logic;


      app_rd_data_valid         : out   std_logic;


      app_rdy                   : out   std_logic;


      app_wdf_rdy               : out   std_logic;


      app_sr_req                : in    std_logic;


      app_ref_req               : in    std_logic;


      app_zq_req                : in    std_logic;


      app_sr_active             : out   std_logic;


      app_ref_ack               : out   std_logic;


      app_zq_ack                : out   std_logic;


      ui_clk                    : out   std_logic;


      ui_clk_sync_rst           : out   std_logic;


      init_calib_complete       : out   std_logic;


      -- System Clock Ports


      sys_clk_p                      : in    std_logic;


      sys_clk_n                      : in    std_logic;


      -- Reference Clock Ports


      clk_ref_i                                : in    std_logic;


    sys_rst                     : in    std_logic


  );


end component mig;





-- COMP_TAG_END ------ End COMPONENT Declaration ------------





------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG





  u_mig : mig


    port map (


       -- Memory interface ports


       ddr3_addr                      => ddr3_addr,


       ddr3_ba                        => ddr3_ba,


       ddr3_cas_n                     => ddr3_cas_n,


       ddr3_ck_n                      => ddr3_ck_n,


       ddr3_ck_p                      => ddr3_ck_p,


       ddr3_cke                       => ddr3_cke,


       ddr3_ras_n                     => ddr3_ras_n,


       ddr3_reset_n                   => ddr3_reset_n,


       ddr3_we_n                      => ddr3_we_n,


       ddr3_dq                        => ddr3_dq,


       ddr3_dqs_n                     => ddr3_dqs_n,


       ddr3_dqs_p                     => ddr3_dqs_p,


       init_calib_complete            => init_calib_complete,


	   ddr3_cs_n                      => ddr3_cs_n,


       ddr3_dm                        => ddr3_dm,


       ddr3_odt                       => ddr3_odt,


       -- Application interface ports


       app_addr                       => app_addr,


       app_cmd                        => app_cmd,


       app_en                         => app_en,


       app_wdf_data                   => app_wdf_data,


       app_wdf_end                    => app_wdf_end,


       app_wdf_wren                   => app_wdf_wren,


       app_rd_data                    => app_rd_data,


       app_rd_data_end                => app_rd_data_end,


       app_rd_data_valid              => app_rd_data_valid,


       app_rdy                        => app_rdy,


       app_wdf_rdy                    => app_wdf_rdy,


       app_sr_req                     => app_sr_req,


       app_ref_req                    => app_ref_req,


       app_zq_req                     => app_zq_req,


       app_sr_active                  => app_sr_active,


       app_ref_ack                    => app_ref_ack,


       app_zq_ack                     => app_zq_ack,


       ui_clk                         => ui_clk,


       ui_clk_sync_rst                => ui_clk_sync_rst,


       app_wdf_mask                   => app_wdf_mask,


       -- System Clock Ports


       sys_clk_p                       => sys_clk_p,


       sys_clk_n                       => sys_clk_n,


       -- Reference Clock Ports


       clk_ref_i                      => clk_ref_i,


      sys_rst                        => sys_rst


    );





-- INST_TAG_END ------ End INSTANTIATION Template ---------





-- You must compile the wrapper file mig.vho when simulating


-- the core, mig. When compiling the wrapper file, be sure to


-- reference the XilinxCoreLib Verilog simulation library. For detailed


-- instructions, please refer to the "CORE Generator Help".







