<?xml version="1.0" encoding="UTF-8"?>
<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
  <spirit:vendor>xilinx.com</spirit:vendor>
  <spirit:library>customized_ip</spirit:library>
  <spirit:name>mig</spirit:name>
  <spirit:version>1.0</spirit:version>
  <spirit:busInterfaces>
    <spirit:busInterface>
      <spirit:name>SYSTEM_RESET</spirit:name>
      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
      <spirit:slave/>
      <spirit:connectionRequired>true</spirit:connectionRequired>
      <spirit:portMaps>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>RST</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>sys_rst</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
      </spirit:portMaps>
      <spirit:parameters>
        <spirit:parameter>
          <spirit:name>POLARITY</spirit:name>
          <spirit:value spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.SYSTEM_RESET.POLARITY" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.POLARITY&apos;))">ACTIVE_LOW</spirit:value>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>BOARD.ASSOCIATED_PARAM</spirit:name>
          <spirit:value spirit:id="BUSIFPARAM_VALUE.SYSTEM_RESET.BOARD.ASSOCIATED_PARAM">RESET_BOARD_INTERFACE</spirit:value>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>INSERT_VIP</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.SYSTEM_RESET.INSERT_VIP">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
      </spirit:parameters>
    </spirit:busInterface>
    <spirit:busInterface>
      <spirit:name>CLK_REF</spirit:name>
      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="diff_clock" spirit:version="1.0"/>
      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="diff_clock_rtl" spirit:version="1.0"/>
      <spirit:slave/>
      <spirit:connectionRequired>true</spirit:connectionRequired>
      <spirit:portMaps>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>CLK_P</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>clk_ref_p</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>CLK_N</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>clk_ref_n</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
      </spirit:portMaps>
      <spirit:parameters>
        <spirit:parameter>
          <spirit:name>CAN_DEBUG</spirit:name>
          <spirit:value spirit:format="bool" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK_REF.CAN_DEBUG">false</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>FREQ_HZ</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK_REF.FREQ_HZ">100000000</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
      </spirit:parameters>
      <spirit:vendorExtensions>
        <xilinx:busInterfaceInfo>
          <xilinx:enablement>
            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.CLK_REF" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.REFCLK_TYPE&apos;)) = &quot;DIFF&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.REFCLK_TYPE&apos;)) != &quot;NONE&quot; ">false</xilinx:isEnabled>
          </xilinx:enablement>
        </xilinx:busInterfaceInfo>
      </spirit:vendorExtensions>
    </spirit:busInterface>
    <spirit:busInterface>
      <spirit:name>CLK_REF_I</spirit:name>
      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
      <spirit:slave/>
      <spirit:connectionRequired>true</spirit:connectionRequired>
      <spirit:portMaps>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>CLK</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>clk_ref_i</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
      </spirit:portMaps>
      <spirit:parameters>
        <spirit:parameter>
          <spirit:name>FREQ_HZ</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK_REF_I.FREQ_HZ">100000000</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>PHASE</spirit:name>
          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK_REF_I.PHASE">0.000</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>CLK_DOMAIN</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK_REF_I.CLK_DOMAIN"/>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>ASSOCIATED_BUSIF</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK_REF_I.ASSOCIATED_BUSIF"/>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>ASSOCIATED_RESET</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK_REF_I.ASSOCIATED_RESET"/>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>INSERT_VIP</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.CLK_REF_I.INSERT_VIP">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
      </spirit:parameters>
      <spirit:vendorExtensions>
        <xilinx:busInterfaceInfo>
          <xilinx:enablement>
            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.CLK_REF_I" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.REFCLK_TYPE&apos;)) != &quot;DIFF&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.REFCLK_TYPE&apos;)) != &quot;NONE&quot; ">true</xilinx:isEnabled>
          </xilinx:enablement>
        </xilinx:busInterfaceInfo>
      </spirit:vendorExtensions>
    </spirit:busInterface>
    <spirit:busInterface>
      <spirit:name>DDR3</spirit:name>
      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="ddrx" spirit:version="1.0"/>
      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="ddrx_rtl" spirit:version="1.0"/>
      <spirit:master/>
      <spirit:connectionRequired>true</spirit:connectionRequired>
      <spirit:portMaps>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>DQ</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>ddr3_dq</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>DQS_P</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>ddr3_dqs_p</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>DQS_N</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>ddr3_dqs_n</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>ADDR</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>ddr3_addr</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>BA</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>ddr3_ba</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>RAS_N</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>ddr3_ras_n</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>CAS_N</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>ddr3_cas_n</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>WE_N</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>ddr3_we_n</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>RESET_N</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>ddr3_reset_n</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>CK_P</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>ddr3_ck_p</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>CK_N</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>ddr3_ck_n</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>CKE</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>ddr3_cke</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>CS_N</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>ddr3_cs_n</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>DM</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>ddr3_dm</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>ODT</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>ddr3_odt</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>PARITY</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>ddr3_parity</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
      </spirit:portMaps>
      <spirit:parameters>
        <spirit:parameter>
          <spirit:name>CAN_DEBUG</spirit:name>
          <spirit:value spirit:format="bool" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.DDR3.CAN_DEBUG">false</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>TIMEPERIOD_PS</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.DDR3.TIMEPERIOD_PS">1250</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>MEMORY_TYPE</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.DDR3.MEMORY_TYPE">COMPONENTS</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>MEMORY_PART</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.DDR3.MEMORY_PART"/>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>DATA_WIDTH</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.DDR3.DATA_WIDTH">8</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>CS_ENABLED</spirit:name>
          <spirit:value spirit:format="bool" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.DDR3.CS_ENABLED">true</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>DATA_MASK_ENABLED</spirit:name>
          <spirit:value spirit:format="bool" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.DDR3.DATA_MASK_ENABLED">true</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>SLOT</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.DDR3.SLOT">Single</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>CUSTOM_PARTS</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.DDR3.CUSTOM_PARTS"/>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>MEM_ADDR_MAP</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.DDR3.MEM_ADDR_MAP">ROW_COLUMN_BANK</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>BURST_LENGTH</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.DDR3.BURST_LENGTH">8</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>AXI_ARBITRATION_SCHEME</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.DDR3.AXI_ARBITRATION_SCHEME">TDM</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>CAS_LATENCY</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.DDR3.CAS_LATENCY">11</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>CAS_WRITE_LATENCY</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.DDR3.CAS_WRITE_LATENCY">11</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
      </spirit:parameters>
      <spirit:vendorExtensions>
        <xilinx:busInterfaceInfo>
          <xilinx:enablement>
            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.DDR3" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;DDR3&quot; ">true</xilinx:isEnabled>
          </xilinx:enablement>
        </xilinx:busInterfaceInfo>
      </spirit:vendorExtensions>
    </spirit:busInterface>
    <spirit:busInterface>
      <spirit:name>DDR2</spirit:name>
      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="ddrx" spirit:version="1.0"/>
      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="ddrx_rtl" spirit:version="1.0"/>
      <spirit:master/>
      <spirit:connectionRequired>true</spirit:connectionRequired>
      <spirit:portMaps>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>DQ</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>ddr2_dq</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>DQS_P</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>ddr2_dqs_p</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>DQS_N</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>ddr2_dqs_n</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>ADDR</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>ddr2_addr</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>BA</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>ddr2_ba</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>RAS_N</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>ddr2_ras_n</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>CAS_N</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>ddr2_cas_n</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>WE_N</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>ddr2_we_n</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>RESET_N</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>ddr2_reset_n</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>CK_P</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>ddr2_ck_p</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>CK_N</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>ddr2_ck_n</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>CKE</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>ddr2_cke</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>CS_N</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>ddr2_cs_n</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>DM</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>ddr2_dm</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>ODT</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>ddr2_odt</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>PARITY</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>ddr2_parity</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
      </spirit:portMaps>
      <spirit:parameters>
        <spirit:parameter>
          <spirit:name>CAN_DEBUG</spirit:name>
          <spirit:value spirit:format="bool" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.DDR2.CAN_DEBUG">false</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>TIMEPERIOD_PS</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.DDR2.TIMEPERIOD_PS">1250</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>MEMORY_TYPE</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.DDR2.MEMORY_TYPE">COMPONENTS</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>MEMORY_PART</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.DDR2.MEMORY_PART"/>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>DATA_WIDTH</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.DDR2.DATA_WIDTH">8</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>CS_ENABLED</spirit:name>
          <spirit:value spirit:format="bool" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.DDR2.CS_ENABLED">true</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>DATA_MASK_ENABLED</spirit:name>
          <spirit:value spirit:format="bool" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.DDR2.DATA_MASK_ENABLED">true</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>SLOT</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.DDR2.SLOT">Single</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>CUSTOM_PARTS</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.DDR2.CUSTOM_PARTS"/>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>MEM_ADDR_MAP</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.DDR2.MEM_ADDR_MAP">ROW_COLUMN_BANK</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>BURST_LENGTH</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.DDR2.BURST_LENGTH">8</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>AXI_ARBITRATION_SCHEME</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.DDR2.AXI_ARBITRATION_SCHEME">TDM</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>CAS_LATENCY</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.DDR2.CAS_LATENCY">11</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>CAS_WRITE_LATENCY</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.DDR2.CAS_WRITE_LATENCY">11</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
      </spirit:parameters>
      <spirit:vendorExtensions>
        <xilinx:busInterfaceInfo>
          <xilinx:enablement>
            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.DDR2" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;DDR2&quot; ">false</xilinx:isEnabled>
          </xilinx:enablement>
        </xilinx:busInterfaceInfo>
      </spirit:vendorExtensions>
    </spirit:busInterface>
    <spirit:busInterface>
      <spirit:name>RESET</spirit:name>
      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
      <spirit:master/>
      <spirit:connectionRequired>true</spirit:connectionRequired>
      <spirit:portMaps>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>RST</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>ui_clk_sync_rst</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
      </spirit:portMaps>
      <spirit:parameters>
        <spirit:parameter>
          <spirit:name>POLARITY</spirit:name>
          <spirit:value spirit:id="BUSIFPARAM_VALUE.RESET.POLARITY">ACTIVE_HIGH</spirit:value>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>INSERT_VIP</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.RESET.INSERT_VIP">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
      </spirit:parameters>
      <spirit:vendorExtensions>
        <xilinx:busInterfaceInfo>
          <xilinx:enablement>
            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.RESET" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 ">true</xilinx:isEnabled>
          </xilinx:enablement>
        </xilinx:busInterfaceInfo>
      </spirit:vendorExtensions>
    </spirit:busInterface>
    <spirit:busInterface>
      <spirit:name>DDR3_RESET</spirit:name>
      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
      <spirit:master/>
      <spirit:connectionRequired>true</spirit:connectionRequired>
      <spirit:portMaps>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>RST</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>ddr3_ui_clk_sync_rst</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
      </spirit:portMaps>
      <spirit:parameters>
        <spirit:parameter>
          <spirit:name>POLARITY</spirit:name>
          <spirit:value spirit:id="BUSIFPARAM_VALUE.DDR3_RESET.POLARITY">ACTIVE_HIGH</spirit:value>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>INSERT_VIP</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.DDR3_RESET.INSERT_VIP">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
      </spirit:parameters>
      <spirit:vendorExtensions>
        <xilinx:busInterfaceInfo>
          <xilinx:enablement>
            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.DDR3_RESET" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 ">true</xilinx:isEnabled>
          </xilinx:enablement>
        </xilinx:busInterfaceInfo>
      </spirit:vendorExtensions>
    </spirit:busInterface>
    <spirit:busInterface>
      <spirit:name>DDR2_RESET</spirit:name>
      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
      <spirit:master/>
      <spirit:connectionRequired>true</spirit:connectionRequired>
      <spirit:portMaps>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>RST</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>ddr2_ui_clk_sync_rst</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
      </spirit:portMaps>
      <spirit:parameters>
        <spirit:parameter>
          <spirit:name>POLARITY</spirit:name>
          <spirit:value spirit:id="BUSIFPARAM_VALUE.DDR2_RESET.POLARITY">ACTIVE_HIGH</spirit:value>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>INSERT_VIP</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.DDR2_RESET.INSERT_VIP">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
      </spirit:parameters>
      <spirit:vendorExtensions>
        <xilinx:busInterfaceInfo>
          <xilinx:enablement>
            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.DDR2_RESET" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 ">true</xilinx:isEnabled>
          </xilinx:enablement>
        </xilinx:busInterfaceInfo>
      </spirit:vendorExtensions>
    </spirit:busInterface>
    <spirit:busInterface>
      <spirit:name>LPDDR2_RESET</spirit:name>
      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
      <spirit:master/>
      <spirit:connectionRequired>true</spirit:connectionRequired>
      <spirit:portMaps>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>RST</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>lpddr2_ui_clk_sync_rst</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
      </spirit:portMaps>
      <spirit:parameters>
        <spirit:parameter>
          <spirit:name>POLARITY</spirit:name>
          <spirit:value spirit:id="BUSIFPARAM_VALUE.LPDDR2_RESET.POLARITY">ACTIVE_HIGH</spirit:value>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>INSERT_VIP</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.LPDDR2_RESET.INSERT_VIP">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
      </spirit:parameters>
      <spirit:vendorExtensions>
        <xilinx:busInterfaceInfo>
          <xilinx:enablement>
            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.LPDDR2_RESET" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 ">true</xilinx:isEnabled>
          </xilinx:enablement>
        </xilinx:busInterfaceInfo>
      </spirit:vendorExtensions>
    </spirit:busInterface>
    <spirit:busInterface>
      <spirit:name>QDRIIP_RESET</spirit:name>
      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
      <spirit:master/>
      <spirit:connectionRequired>true</spirit:connectionRequired>
      <spirit:portMaps>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>RST</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>qdriip_ui_clk_sync_rst</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
      </spirit:portMaps>
      <spirit:parameters>
        <spirit:parameter>
          <spirit:name>POLARITY</spirit:name>
          <spirit:value spirit:id="BUSIFPARAM_VALUE.QDRIIP_RESET.POLARITY">ACTIVE_HIGH</spirit:value>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>INSERT_VIP</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.QDRIIP_RESET.INSERT_VIP">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
      </spirit:parameters>
      <spirit:vendorExtensions>
        <xilinx:busInterfaceInfo>
          <xilinx:enablement>
            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.QDRIIP_RESET" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 ">true</xilinx:isEnabled>
          </xilinx:enablement>
        </xilinx:busInterfaceInfo>
      </spirit:vendorExtensions>
    </spirit:busInterface>
    <spirit:busInterface>
      <spirit:name>RLDII_RESET</spirit:name>
      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
      <spirit:master/>
      <spirit:connectionRequired>true</spirit:connectionRequired>
      <spirit:portMaps>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>RST</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>rldii_ui_clk_sync_rst</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
      </spirit:portMaps>
      <spirit:parameters>
        <spirit:parameter>
          <spirit:name>POLARITY</spirit:name>
          <spirit:value spirit:id="BUSIFPARAM_VALUE.RLDII_RESET.POLARITY">ACTIVE_HIGH</spirit:value>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>INSERT_VIP</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.RLDII_RESET.INSERT_VIP">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
      </spirit:parameters>
      <spirit:vendorExtensions>
        <xilinx:busInterfaceInfo>
          <xilinx:enablement>
            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.RLDII_RESET" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 ">true</xilinx:isEnabled>
          </xilinx:enablement>
        </xilinx:busInterfaceInfo>
      </spirit:vendorExtensions>
    </spirit:busInterface>
    <spirit:busInterface>
      <spirit:name>RLDIII_RESET</spirit:name>
      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
      <spirit:master/>
      <spirit:connectionRequired>true</spirit:connectionRequired>
      <spirit:portMaps>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>RST</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>rldiii_ui_clk_sync_rst</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
      </spirit:portMaps>
      <spirit:parameters>
        <spirit:parameter>
          <spirit:name>POLARITY</spirit:name>
          <spirit:value spirit:id="BUSIFPARAM_VALUE.RLDIII_RESET.POLARITY">ACTIVE_HIGH</spirit:value>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>INSERT_VIP</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.RLDIII_RESET.INSERT_VIP">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
      </spirit:parameters>
      <spirit:vendorExtensions>
        <xilinx:busInterfaceInfo>
          <xilinx:enablement>
            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.RLDIII_RESET" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 ">true</xilinx:isEnabled>
          </xilinx:enablement>
        </xilinx:busInterfaceInfo>
      </spirit:vendorExtensions>
    </spirit:busInterface>
    <spirit:busInterface>
      <spirit:name>CLOCK</spirit:name>
      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
      <spirit:master/>
      <spirit:connectionRequired>true</spirit:connectionRequired>
      <spirit:portMaps>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>CLK</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>ui_clk</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
      </spirit:portMaps>
      <spirit:parameters>
        <spirit:parameter>
          <spirit:name>FREQ_HZ</spirit:name>
          <spirit:value spirit:format="float" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.CLOCK.FREQ_HZ" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.FREQ_HZ&apos;))">100000000</spirit:value>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>ASSOCIATED_BUSIF</spirit:name>
          <spirit:value spirit:id="BUSIFPARAM_VALUE.CLOCK.ASSOCIATED_BUSIF">S_AXI:S_AXI_CTRL</spirit:value>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>ASSOCIATED_RESET</spirit:name>
          <spirit:value spirit:id="BUSIFPARAM_VALUE.CLOCK.ASSOCIATED_RESET">aresetn:ui_clk_sync_rst</spirit:value>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>PHASE</spirit:name>
          <spirit:value spirit:format="float" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.CLOCK.PHASE" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.PHASE&apos;))">0</spirit:value>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>CLK_DOMAIN</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLOCK.CLK_DOMAIN"/>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>INSERT_VIP</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.CLOCK.INSERT_VIP">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
      </spirit:parameters>
      <spirit:vendorExtensions>
        <xilinx:busInterfaceInfo>
          <xilinx:enablement>
            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.CLOCK" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 ">true</xilinx:isEnabled>
          </xilinx:enablement>
        </xilinx:busInterfaceInfo>
      </spirit:vendorExtensions>
    </spirit:busInterface>
    <spirit:busInterface>
      <spirit:name>MMCM_CLKOUT0</spirit:name>
      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
      <spirit:master/>
      <spirit:connectionRequired>true</spirit:connectionRequired>
      <spirit:portMaps>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>CLK</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>ui_addn_clk_0</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
      </spirit:portMaps>
      <spirit:parameters>
        <spirit:parameter>
          <spirit:name>FREQ_HZ</spirit:name>
          <spirit:value spirit:format="float" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.MMCM_CLKOUT0.FREQ_HZ" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.MMCM_CLKOUT0_FREQ&apos;))">10</spirit:value>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>ASSOCIATED_ASYNC_RESET</spirit:name>
          <spirit:value spirit:id="BUSIFPARAM_VALUE.MMCM_CLKOUT0.ASSOCIATED_ASYNC_RESET">aresetn</spirit:value>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>PHASE</spirit:name>
          <spirit:value spirit:format="float" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.MMCM_CLKOUT0.PHASE" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.PHASE&apos;))">0</spirit:value>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>CLK_DOMAIN</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.MMCM_CLKOUT0.CLK_DOMAIN"/>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>ASSOCIATED_BUSIF</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.MMCM_CLKOUT0.ASSOCIATED_BUSIF"/>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>ASSOCIATED_RESET</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.MMCM_CLKOUT0.ASSOCIATED_RESET"/>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>INSERT_VIP</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.MMCM_CLKOUT0.INSERT_VIP">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
      </spirit:parameters>
      <spirit:vendorExtensions>
        <xilinx:busInterfaceInfo>
          <xilinx:enablement>
            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.MMCM_CLKOUT0" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 ">true</xilinx:isEnabled>
          </xilinx:enablement>
        </xilinx:busInterfaceInfo>
      </spirit:vendorExtensions>
    </spirit:busInterface>
    <spirit:busInterface>
      <spirit:name>MMCM_CLKOUT1</spirit:name>
      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
      <spirit:master/>
      <spirit:connectionRequired>true</spirit:connectionRequired>
      <spirit:portMaps>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>CLK</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>ui_addn_clk_1</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
      </spirit:portMaps>
      <spirit:parameters>
        <spirit:parameter>
          <spirit:name>FREQ_HZ</spirit:name>
          <spirit:value spirit:format="float" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.MMCM_CLKOUT1.FREQ_HZ" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.MMCM_CLKOUT1_FREQ&apos;))">10</spirit:value>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>ASSOCIATED_ASYNC_RESET</spirit:name>
          <spirit:value spirit:id="BUSIFPARAM_VALUE.MMCM_CLKOUT1.ASSOCIATED_ASYNC_RESET">aresetn</spirit:value>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>PHASE</spirit:name>
          <spirit:value spirit:format="float" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.MMCM_CLKOUT1.PHASE" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.PHASE&apos;))">0</spirit:value>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>CLK_DOMAIN</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.MMCM_CLKOUT1.CLK_DOMAIN"/>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>ASSOCIATED_BUSIF</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.MMCM_CLKOUT1.ASSOCIATED_BUSIF"/>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>ASSOCIATED_RESET</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.MMCM_CLKOUT1.ASSOCIATED_RESET"/>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>INSERT_VIP</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.MMCM_CLKOUT1.INSERT_VIP">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
      </spirit:parameters>
      <spirit:vendorExtensions>
        <xilinx:busInterfaceInfo>
          <xilinx:enablement>
            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.MMCM_CLKOUT1" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 ">true</xilinx:isEnabled>
          </xilinx:enablement>
        </xilinx:busInterfaceInfo>
      </spirit:vendorExtensions>
    </spirit:busInterface>
    <spirit:busInterface>
      <spirit:name>MMCM_CLKOUT2</spirit:name>
      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
      <spirit:master/>
      <spirit:connectionRequired>true</spirit:connectionRequired>
      <spirit:portMaps>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>CLK</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>ui_addn_clk_2</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
      </spirit:portMaps>
      <spirit:parameters>
        <spirit:parameter>
          <spirit:name>FREQ_HZ</spirit:name>
          <spirit:value spirit:format="float" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.MMCM_CLKOUT2.FREQ_HZ" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.MMCM_CLKOUT2_FREQ&apos;))">10</spirit:value>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>ASSOCIATED_ASYNC_RESET</spirit:name>
          <spirit:value spirit:id="BUSIFPARAM_VALUE.MMCM_CLKOUT2.ASSOCIATED_ASYNC_RESET">aresetn</spirit:value>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>PHASE</spirit:name>
          <spirit:value spirit:format="float" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.MMCM_CLKOUT2.PHASE" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.PHASE&apos;))">0</spirit:value>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>CLK_DOMAIN</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.MMCM_CLKOUT2.CLK_DOMAIN"/>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>ASSOCIATED_BUSIF</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.MMCM_CLKOUT2.ASSOCIATED_BUSIF"/>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>ASSOCIATED_RESET</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.MMCM_CLKOUT2.ASSOCIATED_RESET"/>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>INSERT_VIP</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.MMCM_CLKOUT2.INSERT_VIP">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
      </spirit:parameters>
      <spirit:vendorExtensions>
        <xilinx:busInterfaceInfo>
          <xilinx:enablement>
            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.MMCM_CLKOUT2" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 ">true</xilinx:isEnabled>
          </xilinx:enablement>
        </xilinx:busInterfaceInfo>
      </spirit:vendorExtensions>
    </spirit:busInterface>
    <spirit:busInterface>
      <spirit:name>MMCM_CLKOUT3</spirit:name>
      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
      <spirit:master/>
      <spirit:connectionRequired>true</spirit:connectionRequired>
      <spirit:portMaps>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>CLK</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>ui_addn_clk_3</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
      </spirit:portMaps>
      <spirit:parameters>
        <spirit:parameter>
          <spirit:name>FREQ_HZ</spirit:name>
          <spirit:value spirit:format="float" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.MMCM_CLKOUT3.FREQ_HZ" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.MMCM_CLKOUT3_FREQ&apos;))">10</spirit:value>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>ASSOCIATED_ASYNC_RESET</spirit:name>
          <spirit:value spirit:id="BUSIFPARAM_VALUE.MMCM_CLKOUT3.ASSOCIATED_ASYNC_RESET">aresetn</spirit:value>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>PHASE</spirit:name>
          <spirit:value spirit:format="float" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.MMCM_CLKOUT3.PHASE" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.PHASE&apos;))">0</spirit:value>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>CLK_DOMAIN</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.MMCM_CLKOUT3.CLK_DOMAIN"/>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>ASSOCIATED_BUSIF</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.MMCM_CLKOUT3.ASSOCIATED_BUSIF"/>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>ASSOCIATED_RESET</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.MMCM_CLKOUT3.ASSOCIATED_RESET"/>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>INSERT_VIP</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.MMCM_CLKOUT3.INSERT_VIP">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
      </spirit:parameters>
      <spirit:vendorExtensions>
        <xilinx:busInterfaceInfo>
          <xilinx:enablement>
            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.MMCM_CLKOUT3" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 ">true</xilinx:isEnabled>
          </xilinx:enablement>
        </xilinx:busInterfaceInfo>
      </spirit:vendorExtensions>
    </spirit:busInterface>
    <spirit:busInterface>
      <spirit:name>MMCM_CLKOUT4</spirit:name>
      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
      <spirit:master/>
      <spirit:connectionRequired>true</spirit:connectionRequired>
      <spirit:portMaps>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>CLK</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>ui_addn_clk_4</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
      </spirit:portMaps>
      <spirit:parameters>
        <spirit:parameter>
          <spirit:name>FREQ_HZ</spirit:name>
          <spirit:value spirit:format="float" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.MMCM_CLKOUT4.FREQ_HZ" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.MMCM_CLKOUT4_FREQ&apos;))">10</spirit:value>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>ASSOCIATED_ASYNC_RESET</spirit:name>
          <spirit:value spirit:id="BUSIFPARAM_VALUE.MMCM_CLKOUT4.ASSOCIATED_ASYNC_RESET">aresetn</spirit:value>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>PHASE</spirit:name>
          <spirit:value spirit:format="float" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.MMCM_CLKOUT4.PHASE" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.PHASE&apos;))">0</spirit:value>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>CLK_DOMAIN</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.MMCM_CLKOUT4.CLK_DOMAIN"/>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>ASSOCIATED_BUSIF</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.MMCM_CLKOUT4.ASSOCIATED_BUSIF"/>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>ASSOCIATED_RESET</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.MMCM_CLKOUT4.ASSOCIATED_RESET"/>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>INSERT_VIP</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.MMCM_CLKOUT4.INSERT_VIP">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
      </spirit:parameters>
      <spirit:vendorExtensions>
        <xilinx:busInterfaceInfo>
          <xilinx:enablement>
            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.MMCM_CLKOUT4" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 ">true</xilinx:isEnabled>
          </xilinx:enablement>
        </xilinx:busInterfaceInfo>
      </spirit:vendorExtensions>
    </spirit:busInterface>
    <spirit:busInterface>
      <spirit:name>S_AXI_CTRL</spirit:name>
      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm" spirit:version="1.0"/>
      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm_rtl" spirit:version="1.0"/>
      <spirit:slave>
        <spirit:memoryMapRef spirit:memoryMapRef="s_axi_ctrl_memmap"/>
      </spirit:slave>
      <spirit:connectionRequired>true</spirit:connectionRequired>
      <spirit:portMaps>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>AWVALID</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>s_axi_ctrl_awvalid</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>AWREADY</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>s_axi_ctrl_awready</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>AWADDR</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>s_axi_ctrl_awaddr</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>WVALID</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>s_axi_ctrl_wvalid</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>WREADY</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>s_axi_ctrl_wready</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>WDATA</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>s_axi_ctrl_wdata</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>BVALID</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>s_axi_ctrl_bvalid</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>BREADY</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>s_axi_ctrl_bready</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>BRESP</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>s_axi_ctrl_bresp</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>ARVALID</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>s_axi_ctrl_arvalid</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>ARREADY</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>s_axi_ctrl_arready</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>ARADDR</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>s_axi_ctrl_araddr</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>RVALID</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>s_axi_ctrl_rvalid</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>RREADY</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>s_axi_ctrl_rready</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>RDATA</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>s_axi_ctrl_rdata</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>RRESP</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>s_axi_ctrl_rresp</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
      </spirit:portMaps>
      <spirit:parameters>
        <spirit:parameter>
          <spirit:name>FREQ_HZ</spirit:name>
          <spirit:value spirit:format="float" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.FREQ_HZ" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.FREQ_HZ&apos;))">100000000</spirit:value>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>DATA_WIDTH</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.DATA_WIDTH">1</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>PROTOCOL</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.PROTOCOL">AXI4LITE</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>ID_WIDTH</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.ID_WIDTH">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>ADDR_WIDTH</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.ADDR_WIDTH">1</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>AWUSER_WIDTH</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.AWUSER_WIDTH">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>ARUSER_WIDTH</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.ARUSER_WIDTH">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>WUSER_WIDTH</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.WUSER_WIDTH">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>RUSER_WIDTH</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.RUSER_WIDTH">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>BUSER_WIDTH</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.BUSER_WIDTH">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>READ_WRITE_MODE</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.READ_WRITE_MODE">READ_WRITE</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>HAS_BURST</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.HAS_BURST">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>HAS_LOCK</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.HAS_LOCK">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>HAS_PROT</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.HAS_PROT">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>HAS_CACHE</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.HAS_CACHE">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>HAS_QOS</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.HAS_QOS">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>HAS_REGION</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.HAS_REGION">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>HAS_WSTRB</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.HAS_WSTRB">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>HAS_BRESP</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.HAS_BRESP">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>HAS_RRESP</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.HAS_RRESP">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>SUPPORTS_NARROW_BURST</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.SUPPORTS_NARROW_BURST">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>NUM_READ_OUTSTANDING</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.NUM_READ_OUTSTANDING">1</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>NUM_WRITE_OUTSTANDING</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.NUM_WRITE_OUTSTANDING">1</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>MAX_BURST_LENGTH</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.MAX_BURST_LENGTH">1</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>PHASE</spirit:name>
          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.PHASE">0.000</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>CLK_DOMAIN</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.CLK_DOMAIN"/>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>NUM_READ_THREADS</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.NUM_READ_THREADS">1</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>NUM_WRITE_THREADS</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.NUM_WRITE_THREADS">1</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>RUSER_BITS_PER_BYTE</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.RUSER_BITS_PER_BYTE">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>WUSER_BITS_PER_BYTE</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.WUSER_BITS_PER_BYTE">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>INSERT_VIP</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.INSERT_VIP">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
      </spirit:parameters>
      <spirit:vendorExtensions>
        <xilinx:busInterfaceInfo>
          <xilinx:enablement>
            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.S_AXI_CTRL" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.USE_AXI&apos;)) = 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.ECC&apos;)) = &quot;ON&quot; ) ">false</xilinx:isEnabled>
          </xilinx:enablement>
        </xilinx:busInterfaceInfo>
      </spirit:vendorExtensions>
    </spirit:busInterface>
    <spirit:busInterface>
      <spirit:name>S_AXI</spirit:name>
      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm" spirit:version="1.0"/>
      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm_rtl" spirit:version="1.0"/>
      <spirit:slave>
        <spirit:memoryMapRef spirit:memoryMapRef="memmap"/>
      </spirit:slave>
      <spirit:connectionRequired>true</spirit:connectionRequired>
      <spirit:portMaps>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>AWID</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>s_axi_awid</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>AWADDR</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>s_axi_awaddr</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>AWLEN</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>s_axi_awlen</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>AWSIZE</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>s_axi_awsize</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>AWBURST</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>s_axi_awburst</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>AWLOCK</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>s_axi_awlock</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>AWCACHE</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>s_axi_awcache</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>AWPROT</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>s_axi_awprot</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>AWQOS</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>s_axi_awqos</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>AWVALID</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>s_axi_awvalid</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>AWREADY</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>s_axi_awready</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>WDATA</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>s_axi_wdata</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>WSTRB</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>s_axi_wstrb</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>WLAST</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>s_axi_wlast</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>WVALID</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>s_axi_wvalid</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>WREADY</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>s_axi_wready</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>BREADY</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>s_axi_bready</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>BID</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>s_axi_bid</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>BRESP</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>s_axi_bresp</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>BVALID</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>s_axi_bvalid</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>ARID</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>s_axi_arid</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>ARADDR</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>s_axi_araddr</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>ARLEN</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>s_axi_arlen</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>ARSIZE</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>s_axi_arsize</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>ARBURST</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>s_axi_arburst</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>ARLOCK</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>s_axi_arlock</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>ARCACHE</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>s_axi_arcache</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>ARPROT</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>s_axi_arprot</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>ARQOS</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>s_axi_arqos</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>ARVALID</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>s_axi_arvalid</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>ARREADY</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>s_axi_arready</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>RREADY</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>s_axi_rready</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>RID</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>s_axi_rid</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>RDATA</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>s_axi_rdata</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>RRESP</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>s_axi_rresp</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>RLAST</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>s_axi_rlast</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>RVALID</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>s_axi_rvalid</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
      </spirit:portMaps>
      <spirit:parameters>
        <spirit:parameter>
          <spirit:name>FREQ_HZ</spirit:name>
          <spirit:value spirit:format="float" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.S_AXI.FREQ_HZ" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.FREQ_HZ&apos;))">100000000</spirit:value>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>DATA_WIDTH</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.DATA_WIDTH">1</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>PROTOCOL</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.PROTOCOL">AXI4LITE</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>ID_WIDTH</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.ID_WIDTH">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>ADDR_WIDTH</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.ADDR_WIDTH">1</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>AWUSER_WIDTH</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.AWUSER_WIDTH">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>ARUSER_WIDTH</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.ARUSER_WIDTH">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>WUSER_WIDTH</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.WUSER_WIDTH">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>RUSER_WIDTH</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.RUSER_WIDTH">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>BUSER_WIDTH</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.BUSER_WIDTH">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>READ_WRITE_MODE</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.READ_WRITE_MODE">READ_WRITE</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>HAS_BURST</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.HAS_BURST">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>HAS_LOCK</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.HAS_LOCK">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>HAS_PROT</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.HAS_PROT">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>HAS_CACHE</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.HAS_CACHE">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>HAS_QOS</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.HAS_QOS">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>HAS_REGION</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.HAS_REGION">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>HAS_WSTRB</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.HAS_WSTRB">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>HAS_BRESP</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.HAS_BRESP">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>HAS_RRESP</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.HAS_RRESP">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>SUPPORTS_NARROW_BURST</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.SUPPORTS_NARROW_BURST">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>NUM_READ_OUTSTANDING</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.NUM_READ_OUTSTANDING">1</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>NUM_WRITE_OUTSTANDING</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.NUM_WRITE_OUTSTANDING">1</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>MAX_BURST_LENGTH</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.MAX_BURST_LENGTH">1</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>PHASE</spirit:name>
          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.PHASE">0.000</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>CLK_DOMAIN</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.CLK_DOMAIN"/>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>NUM_READ_THREADS</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.NUM_READ_THREADS">1</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>NUM_WRITE_THREADS</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.NUM_WRITE_THREADS">1</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>RUSER_BITS_PER_BYTE</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.RUSER_BITS_PER_BYTE">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>WUSER_BITS_PER_BYTE</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.WUSER_BITS_PER_BYTE">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>INSERT_VIP</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.S_AXI.INSERT_VIP">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
      </spirit:parameters>
      <spirit:vendorExtensions>
        <xilinx:busInterfaceInfo>
          <xilinx:enablement>
            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.S_AXI" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
          </xilinx:enablement>
        </xilinx:busInterfaceInfo>
      </spirit:vendorExtensions>
    </spirit:busInterface>
    <spirit:busInterface>
      <spirit:name>SYS_CLK</spirit:name>
      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="diff_clock" spirit:version="1.0"/>
      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="diff_clock_rtl" spirit:version="1.0"/>
      <spirit:slave/>
      <spirit:connectionRequired>true</spirit:connectionRequired>
      <spirit:portMaps>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>CLK_P</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>sys_clk_p</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>CLK_N</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>sys_clk_n</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
      </spirit:portMaps>
      <spirit:parameters>
        <spirit:parameter>
          <spirit:name>CAN_DEBUG</spirit:name>
          <spirit:value spirit:format="bool" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SYS_CLK.CAN_DEBUG">false</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>FREQ_HZ</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SYS_CLK.FREQ_HZ">100000000</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
      </spirit:parameters>
      <spirit:vendorExtensions>
        <xilinx:busInterfaceInfo>
          <xilinx:enablement>
            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.SYS_CLK" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.SYSCLK_TYPE&apos;)) = &quot;DIFF&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.IS_CLK_SHARED&apos;)) = &quot;FALSE&quot; ">true</xilinx:isEnabled>
          </xilinx:enablement>
        </xilinx:busInterfaceInfo>
      </spirit:vendorExtensions>
    </spirit:busInterface>
    <spirit:busInterface>
      <spirit:name>SYS_CLK_I</spirit:name>
      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
      <spirit:slave/>
      <spirit:connectionRequired>true</spirit:connectionRequired>
      <spirit:portMaps>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>CLK</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>sys_clk_i</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
      </spirit:portMaps>
      <spirit:parameters>
        <spirit:parameter>
          <spirit:name>FREQ_HZ</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SYS_CLK_I.FREQ_HZ">100000000</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>PHASE</spirit:name>
          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SYS_CLK_I.PHASE">0.000</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>CLK_DOMAIN</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SYS_CLK_I.CLK_DOMAIN"/>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>ASSOCIATED_BUSIF</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SYS_CLK_I.ASSOCIATED_BUSIF"/>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>ASSOCIATED_RESET</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SYS_CLK_I.ASSOCIATED_RESET"/>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>INSERT_VIP</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.SYS_CLK_I.INSERT_VIP">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
      </spirit:parameters>
      <spirit:vendorExtensions>
        <xilinx:busInterfaceInfo>
          <xilinx:enablement>
            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.SYS_CLK_I" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.SYSCLK_TYPE&apos;)) != &quot;DIFF&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.IS_CLK_SHARED&apos;)) = &quot;FALSE&quot; ">false</xilinx:isEnabled>
          </xilinx:enablement>
        </xilinx:busInterfaceInfo>
      </spirit:vendorExtensions>
    </spirit:busInterface>
    <spirit:busInterface>
      <spirit:name>ARESETN</spirit:name>
      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
      <spirit:slave/>
      <spirit:connectionRequired>true</spirit:connectionRequired>
      <spirit:portMaps>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>ARESETN</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>aresetn</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
      </spirit:portMaps>
      <spirit:parameters>
        <spirit:parameter>
          <spirit:name>POLARITY</spirit:name>
          <spirit:value spirit:id="BUSIFPARAM_VALUE.ARESETN.POLARITY">ACTIVE_LOW</spirit:value>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>INSERT_VIP</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.ARESETN.INSERT_VIP">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
      </spirit:parameters>
    </spirit:busInterface>
    <spirit:busInterface>
      <spirit:name>C0_DDR3</spirit:name>
      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="ddrx" spirit:version="1.0"/>
      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="ddrx_rtl" spirit:version="1.0"/>
      <spirit:master/>
      <spirit:connectionRequired>true</spirit:connectionRequired>
      <spirit:portMaps>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>DQ</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c0_ddr3_dq</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>DQS_P</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c0_ddr3_dqs_p</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>DQS_N</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c0_ddr3_dqs_n</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>ADDR</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c0_ddr3_addr</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>BA</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c0_ddr3_ba</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>RAS_N</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c0_ddr3_ras_n</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>CAS_N</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c0_ddr3_cas_n</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>WE_N</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c0_ddr3_we_n</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>RESET_N</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c0_ddr3_reset_n</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>CK_P</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c0_ddr3_ck_p</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>CK_N</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c0_ddr3_ck_n</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>CKE</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c0_ddr3_cke</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>CS_N</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c0_ddr3_cs_n</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>DM</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c0_ddr3_dm</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>ODT</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c0_ddr3_odt</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>PARITY</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c0_ddr3_parity</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
      </spirit:portMaps>
      <spirit:parameters>
        <spirit:parameter>
          <spirit:name>CAN_DEBUG</spirit:name>
          <spirit:value spirit:format="bool" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C0_DDR3.CAN_DEBUG">false</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>TIMEPERIOD_PS</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C0_DDR3.TIMEPERIOD_PS">1250</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>MEMORY_TYPE</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C0_DDR3.MEMORY_TYPE">COMPONENTS</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>MEMORY_PART</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C0_DDR3.MEMORY_PART"/>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>DATA_WIDTH</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C0_DDR3.DATA_WIDTH">8</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>CS_ENABLED</spirit:name>
          <spirit:value spirit:format="bool" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C0_DDR3.CS_ENABLED">true</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>DATA_MASK_ENABLED</spirit:name>
          <spirit:value spirit:format="bool" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C0_DDR3.DATA_MASK_ENABLED">true</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>SLOT</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C0_DDR3.SLOT">Single</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>CUSTOM_PARTS</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C0_DDR3.CUSTOM_PARTS"/>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>MEM_ADDR_MAP</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C0_DDR3.MEM_ADDR_MAP">ROW_COLUMN_BANK</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>BURST_LENGTH</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C0_DDR3.BURST_LENGTH">8</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>AXI_ARBITRATION_SCHEME</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C0_DDR3.AXI_ARBITRATION_SCHEME">TDM</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>CAS_LATENCY</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C0_DDR3.CAS_LATENCY">11</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>CAS_WRITE_LATENCY</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C0_DDR3.CAS_WRITE_LATENCY">11</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
      </spirit:parameters>
      <spirit:vendorExtensions>
        <xilinx:busInterfaceInfo>
          <xilinx:enablement>
            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.C0_DDR3" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;DDR3&quot; ">false</xilinx:isEnabled>
          </xilinx:enablement>
        </xilinx:busInterfaceInfo>
      </spirit:vendorExtensions>
    </spirit:busInterface>
    <spirit:busInterface>
      <spirit:name>C0_DDR2</spirit:name>
      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="ddrx" spirit:version="1.0"/>
      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="ddrx_rtl" spirit:version="1.0"/>
      <spirit:master/>
      <spirit:connectionRequired>true</spirit:connectionRequired>
      <spirit:portMaps>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>DQ</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c0_ddr2_dq</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>DQS_P</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c0_ddr2_dqs_p</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>DQS_N</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c0_ddr2_dqs_n</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>ADDR</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c0_ddr2_addr</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>BA</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c0_ddr2_ba</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>RAS_N</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c0_ddr2_ras_n</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>CAS_N</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c0_ddr2_cas_n</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>WE_N</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c0_ddr2_we_n</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>RESET_N</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c0_ddr2_reset_n</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>CK_P</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c0_ddr2_ck_p</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>CK_N</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c0_ddr2_ck_n</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>CKE</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c0_ddr2_cke</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>CS_N</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c0_ddr2_cs_n</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>DM</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c0_ddr2_dm</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>ODT</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c0_ddr2_odt</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>PARITY</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c0_ddr2_parity</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
      </spirit:portMaps>
      <spirit:parameters>
        <spirit:parameter>
          <spirit:name>CAN_DEBUG</spirit:name>
          <spirit:value spirit:format="bool" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C0_DDR2.CAN_DEBUG">false</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>TIMEPERIOD_PS</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C0_DDR2.TIMEPERIOD_PS">1250</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>MEMORY_TYPE</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C0_DDR2.MEMORY_TYPE">COMPONENTS</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>MEMORY_PART</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C0_DDR2.MEMORY_PART"/>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>DATA_WIDTH</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C0_DDR2.DATA_WIDTH">8</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>CS_ENABLED</spirit:name>
          <spirit:value spirit:format="bool" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C0_DDR2.CS_ENABLED">true</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>DATA_MASK_ENABLED</spirit:name>
          <spirit:value spirit:format="bool" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C0_DDR2.DATA_MASK_ENABLED">true</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>SLOT</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C0_DDR2.SLOT">Single</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>CUSTOM_PARTS</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C0_DDR2.CUSTOM_PARTS"/>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>MEM_ADDR_MAP</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C0_DDR2.MEM_ADDR_MAP">ROW_COLUMN_BANK</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>BURST_LENGTH</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C0_DDR2.BURST_LENGTH">8</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>AXI_ARBITRATION_SCHEME</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C0_DDR2.AXI_ARBITRATION_SCHEME">TDM</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>CAS_LATENCY</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C0_DDR2.CAS_LATENCY">11</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>CAS_WRITE_LATENCY</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C0_DDR2.CAS_WRITE_LATENCY">11</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
      </spirit:parameters>
      <spirit:vendorExtensions>
        <xilinx:busInterfaceInfo>
          <xilinx:enablement>
            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.C0_DDR2" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;DDR2&quot; ">false</xilinx:isEnabled>
          </xilinx:enablement>
        </xilinx:busInterfaceInfo>
      </spirit:vendorExtensions>
    </spirit:busInterface>
    <spirit:busInterface>
      <spirit:name>C0_RESET</spirit:name>
      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
      <spirit:master/>
      <spirit:connectionRequired>true</spirit:connectionRequired>
      <spirit:portMaps>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>RST</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c0_ui_clk_sync_rst</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
      </spirit:portMaps>
      <spirit:parameters>
        <spirit:parameter>
          <spirit:name>POLARITY</spirit:name>
          <spirit:value spirit:id="BUSIFPARAM_VALUE.C0_RESET.POLARITY">ACTIVE_HIGH</spirit:value>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>INSERT_VIP</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.C0_RESET.INSERT_VIP">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
      </spirit:parameters>
      <spirit:vendorExtensions>
        <xilinx:busInterfaceInfo>
          <xilinx:enablement>
            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.C0_RESET" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 ">false</xilinx:isEnabled>
          </xilinx:enablement>
        </xilinx:busInterfaceInfo>
      </spirit:vendorExtensions>
    </spirit:busInterface>
    <spirit:busInterface>
      <spirit:name>C0_DDR3_RESET</spirit:name>
      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
      <spirit:master/>
      <spirit:connectionRequired>true</spirit:connectionRequired>
      <spirit:portMaps>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>RST</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c0_ddr3_ui_clk_sync_rst</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
      </spirit:portMaps>
      <spirit:parameters>
        <spirit:parameter>
          <spirit:name>POLARITY</spirit:name>
          <spirit:value spirit:id="BUSIFPARAM_VALUE.C0_DDR3_RESET.POLARITY">ACTIVE_HIGH</spirit:value>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>INSERT_VIP</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.C0_DDR3_RESET.INSERT_VIP">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
      </spirit:parameters>
      <spirit:vendorExtensions>
        <xilinx:busInterfaceInfo>
          <xilinx:enablement>
            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.C0_DDR3_RESET" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 ">false</xilinx:isEnabled>
          </xilinx:enablement>
        </xilinx:busInterfaceInfo>
      </spirit:vendorExtensions>
    </spirit:busInterface>
    <spirit:busInterface>
      <spirit:name>C0_DDR2_RESET</spirit:name>
      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
      <spirit:master/>
      <spirit:connectionRequired>true</spirit:connectionRequired>
      <spirit:portMaps>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>RST</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c0_ddr2_ui_clk_sync_rst</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
      </spirit:portMaps>
      <spirit:parameters>
        <spirit:parameter>
          <spirit:name>POLARITY</spirit:name>
          <spirit:value spirit:id="BUSIFPARAM_VALUE.C0_DDR2_RESET.POLARITY">ACTIVE_HIGH</spirit:value>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>INSERT_VIP</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.C0_DDR2_RESET.INSERT_VIP">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
      </spirit:parameters>
      <spirit:vendorExtensions>
        <xilinx:busInterfaceInfo>
          <xilinx:enablement>
            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.C0_DDR2_RESET" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 ">false</xilinx:isEnabled>
          </xilinx:enablement>
        </xilinx:busInterfaceInfo>
      </spirit:vendorExtensions>
    </spirit:busInterface>
    <spirit:busInterface>
      <spirit:name>C0_LPDDR2_RESET</spirit:name>
      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
      <spirit:master/>
      <spirit:connectionRequired>true</spirit:connectionRequired>
      <spirit:portMaps>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>RST</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c0_lpddr2_ui_clk_sync_rst</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
      </spirit:portMaps>
      <spirit:parameters>
        <spirit:parameter>
          <spirit:name>POLARITY</spirit:name>
          <spirit:value spirit:id="BUSIFPARAM_VALUE.C0_LPDDR2_RESET.POLARITY">ACTIVE_HIGH</spirit:value>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>INSERT_VIP</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.C0_LPDDR2_RESET.INSERT_VIP">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
      </spirit:parameters>
      <spirit:vendorExtensions>
        <xilinx:busInterfaceInfo>
          <xilinx:enablement>
            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.C0_LPDDR2_RESET" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 ">false</xilinx:isEnabled>
          </xilinx:enablement>
        </xilinx:busInterfaceInfo>
      </spirit:vendorExtensions>
    </spirit:busInterface>
    <spirit:busInterface>
      <spirit:name>C0_QDRIIP_RESET</spirit:name>
      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
      <spirit:master/>
      <spirit:connectionRequired>true</spirit:connectionRequired>
      <spirit:portMaps>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>RST</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c0_qdriip_ui_clk_sync_rst</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
      </spirit:portMaps>
      <spirit:parameters>
        <spirit:parameter>
          <spirit:name>POLARITY</spirit:name>
          <spirit:value spirit:id="BUSIFPARAM_VALUE.C0_QDRIIP_RESET.POLARITY">ACTIVE_HIGH</spirit:value>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>INSERT_VIP</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.C0_QDRIIP_RESET.INSERT_VIP">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
      </spirit:parameters>
      <spirit:vendorExtensions>
        <xilinx:busInterfaceInfo>
          <xilinx:enablement>
            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.C0_QDRIIP_RESET" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 ">false</xilinx:isEnabled>
          </xilinx:enablement>
        </xilinx:busInterfaceInfo>
      </spirit:vendorExtensions>
    </spirit:busInterface>
    <spirit:busInterface>
      <spirit:name>C0_RLDII_RESET</spirit:name>
      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
      <spirit:master/>
      <spirit:connectionRequired>true</spirit:connectionRequired>
      <spirit:portMaps>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>RST</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c0_rldii_ui_clk_sync_rst</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
      </spirit:portMaps>
      <spirit:parameters>
        <spirit:parameter>
          <spirit:name>POLARITY</spirit:name>
          <spirit:value spirit:id="BUSIFPARAM_VALUE.C0_RLDII_RESET.POLARITY">ACTIVE_HIGH</spirit:value>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>INSERT_VIP</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.C0_RLDII_RESET.INSERT_VIP">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
      </spirit:parameters>
      <spirit:vendorExtensions>
        <xilinx:busInterfaceInfo>
          <xilinx:enablement>
            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.C0_RLDII_RESET" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 ">false</xilinx:isEnabled>
          </xilinx:enablement>
        </xilinx:busInterfaceInfo>
      </spirit:vendorExtensions>
    </spirit:busInterface>
    <spirit:busInterface>
      <spirit:name>C0_RLDIII_RESET</spirit:name>
      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
      <spirit:master/>
      <spirit:connectionRequired>true</spirit:connectionRequired>
      <spirit:portMaps>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>RST</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c0_rldiii_ui_clk_sync_rst</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
      </spirit:portMaps>
      <spirit:parameters>
        <spirit:parameter>
          <spirit:name>POLARITY</spirit:name>
          <spirit:value spirit:id="BUSIFPARAM_VALUE.C0_RLDIII_RESET.POLARITY">ACTIVE_HIGH</spirit:value>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>INSERT_VIP</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.C0_RLDIII_RESET.INSERT_VIP">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
      </spirit:parameters>
      <spirit:vendorExtensions>
        <xilinx:busInterfaceInfo>
          <xilinx:enablement>
            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.C0_RLDIII_RESET" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 ">false</xilinx:isEnabled>
          </xilinx:enablement>
        </xilinx:busInterfaceInfo>
      </spirit:vendorExtensions>
    </spirit:busInterface>
    <spirit:busInterface>
      <spirit:name>C0_CLOCK</spirit:name>
      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
      <spirit:master/>
      <spirit:connectionRequired>true</spirit:connectionRequired>
      <spirit:portMaps>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>CLK</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c0_ui_clk</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
      </spirit:portMaps>
      <spirit:parameters>
        <spirit:parameter>
          <spirit:name>FREQ_HZ</spirit:name>
          <spirit:value spirit:format="float" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.C0_CLOCK.FREQ_HZ" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C0_FREQ_HZ&apos;))">100</spirit:value>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>ASSOCIATED_BUSIF</spirit:name>
          <spirit:value spirit:id="BUSIFPARAM_VALUE.C0_CLOCK.ASSOCIATED_BUSIF">S0_AXI:S0_AXI_CTRL</spirit:value>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>ASSOCIATED_RESET</spirit:name>
          <spirit:value spirit:id="BUSIFPARAM_VALUE.C0_CLOCK.ASSOCIATED_RESET">c0_aresetn:c0_ui_clk_sync_rst</spirit:value>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>PHASE</spirit:name>
          <spirit:value spirit:format="float" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.C0_CLOCK.PHASE" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C0_PHASE&apos;))">0</spirit:value>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>CLK_DOMAIN</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C0_CLOCK.CLK_DOMAIN"/>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>INSERT_VIP</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.C0_CLOCK.INSERT_VIP">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
      </spirit:parameters>
      <spirit:vendorExtensions>
        <xilinx:busInterfaceInfo>
          <xilinx:enablement>
            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.C0_CLOCK" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 ">false</xilinx:isEnabled>
          </xilinx:enablement>
        </xilinx:busInterfaceInfo>
      </spirit:vendorExtensions>
    </spirit:busInterface>
    <spirit:busInterface>
      <spirit:name>C0_MMCM_CLKOUT0</spirit:name>
      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
      <spirit:master/>
      <spirit:connectionRequired>true</spirit:connectionRequired>
      <spirit:portMaps>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>CLK</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c0_ui_addn_clk_0</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
      </spirit:portMaps>
      <spirit:parameters>
        <spirit:parameter>
          <spirit:name>FREQ_HZ</spirit:name>
          <spirit:value spirit:format="float" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.C0_MMCM_CLKOUT0.FREQ_HZ" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MMCM_CLKOUT0_FREQ&apos;))">10</spirit:value>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>ASSOCIATED_ASYNC_RESET</spirit:name>
          <spirit:value spirit:id="BUSIFPARAM_VALUE.C0_MMCM_CLKOUT0.ASSOCIATED_ASYNC_RESET">c0_aresetn</spirit:value>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>PHASE</spirit:name>
          <spirit:value spirit:format="float" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.C0_MMCM_CLKOUT0.PHASE" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C0_PHASE&apos;))">0</spirit:value>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>CLK_DOMAIN</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C0_MMCM_CLKOUT0.CLK_DOMAIN"/>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>ASSOCIATED_BUSIF</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C0_MMCM_CLKOUT0.ASSOCIATED_BUSIF"/>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>ASSOCIATED_RESET</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C0_MMCM_CLKOUT0.ASSOCIATED_RESET"/>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>INSERT_VIP</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.C0_MMCM_CLKOUT0.INSERT_VIP">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
      </spirit:parameters>
      <spirit:vendorExtensions>
        <xilinx:busInterfaceInfo>
          <xilinx:enablement>
            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.C0_MMCM_CLKOUT0" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 ">false</xilinx:isEnabled>
          </xilinx:enablement>
        </xilinx:busInterfaceInfo>
      </spirit:vendorExtensions>
    </spirit:busInterface>
    <spirit:busInterface>
      <spirit:name>C0_MMCM_CLKOUT1</spirit:name>
      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
      <spirit:master/>
      <spirit:connectionRequired>true</spirit:connectionRequired>
      <spirit:portMaps>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>CLK</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c0_ui_addn_clk_1</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
      </spirit:portMaps>
      <spirit:parameters>
        <spirit:parameter>
          <spirit:name>FREQ_HZ</spirit:name>
          <spirit:value spirit:format="float" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.C0_MMCM_CLKOUT1.FREQ_HZ" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MMCM_CLKOUT1_FREQ&apos;))">10</spirit:value>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>ASSOCIATED_ASYNC_RESET</spirit:name>
          <spirit:value spirit:id="BUSIFPARAM_VALUE.C0_MMCM_CLKOUT1.ASSOCIATED_ASYNC_RESET">c0_aresetn</spirit:value>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>PHASE</spirit:name>
          <spirit:value spirit:format="float" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.C0_MMCM_CLKOUT1.PHASE" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C0_PHASE&apos;))">0</spirit:value>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>CLK_DOMAIN</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C0_MMCM_CLKOUT1.CLK_DOMAIN"/>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>ASSOCIATED_BUSIF</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C0_MMCM_CLKOUT1.ASSOCIATED_BUSIF"/>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>ASSOCIATED_RESET</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C0_MMCM_CLKOUT1.ASSOCIATED_RESET"/>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>INSERT_VIP</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.C0_MMCM_CLKOUT1.INSERT_VIP">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
      </spirit:parameters>
      <spirit:vendorExtensions>
        <xilinx:busInterfaceInfo>
          <xilinx:enablement>
            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.C0_MMCM_CLKOUT1" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 ">false</xilinx:isEnabled>
          </xilinx:enablement>
        </xilinx:busInterfaceInfo>
      </spirit:vendorExtensions>
    </spirit:busInterface>
    <spirit:busInterface>
      <spirit:name>C0_MMCM_CLKOUT2</spirit:name>
      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
      <spirit:master/>
      <spirit:connectionRequired>true</spirit:connectionRequired>
      <spirit:portMaps>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>CLK</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c0_ui_addn_clk_2</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
      </spirit:portMaps>
      <spirit:parameters>
        <spirit:parameter>
          <spirit:name>FREQ_HZ</spirit:name>
          <spirit:value spirit:format="float" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.C0_MMCM_CLKOUT2.FREQ_HZ" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MMCM_CLKOUT2_FREQ&apos;))">10</spirit:value>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>ASSOCIATED_ASYNC_RESET</spirit:name>
          <spirit:value spirit:id="BUSIFPARAM_VALUE.C0_MMCM_CLKOUT2.ASSOCIATED_ASYNC_RESET">c0_aresetn</spirit:value>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>PHASE</spirit:name>
          <spirit:value spirit:format="float" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.C0_MMCM_CLKOUT2.PHASE" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C0_PHASE&apos;))">0</spirit:value>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>CLK_DOMAIN</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C0_MMCM_CLKOUT2.CLK_DOMAIN"/>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>ASSOCIATED_BUSIF</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C0_MMCM_CLKOUT2.ASSOCIATED_BUSIF"/>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>ASSOCIATED_RESET</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C0_MMCM_CLKOUT2.ASSOCIATED_RESET"/>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>INSERT_VIP</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.C0_MMCM_CLKOUT2.INSERT_VIP">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
      </spirit:parameters>
      <spirit:vendorExtensions>
        <xilinx:busInterfaceInfo>
          <xilinx:enablement>
            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.C0_MMCM_CLKOUT2" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 ">false</xilinx:isEnabled>
          </xilinx:enablement>
        </xilinx:busInterfaceInfo>
      </spirit:vendorExtensions>
    </spirit:busInterface>
    <spirit:busInterface>
      <spirit:name>C0_MMCM_CLKOUT3</spirit:name>
      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
      <spirit:master/>
      <spirit:connectionRequired>true</spirit:connectionRequired>
      <spirit:portMaps>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>CLK</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c0_ui_addn_clk_3</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
      </spirit:portMaps>
      <spirit:parameters>
        <spirit:parameter>
          <spirit:name>FREQ_HZ</spirit:name>
          <spirit:value spirit:format="float" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.C0_MMCM_CLKOUT3.FREQ_HZ" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MMCM_CLKOUT3_FREQ&apos;))">10</spirit:value>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>ASSOCIATED_ASYNC_RESET</spirit:name>
          <spirit:value spirit:id="BUSIFPARAM_VALUE.C0_MMCM_CLKOUT3.ASSOCIATED_ASYNC_RESET">c0_aresetn</spirit:value>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>PHASE</spirit:name>
          <spirit:value spirit:format="float" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.C0_MMCM_CLKOUT3.PHASE" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C0_PHASE&apos;))">0</spirit:value>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>CLK_DOMAIN</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C0_MMCM_CLKOUT3.CLK_DOMAIN"/>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>ASSOCIATED_BUSIF</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C0_MMCM_CLKOUT3.ASSOCIATED_BUSIF"/>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>ASSOCIATED_RESET</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C0_MMCM_CLKOUT3.ASSOCIATED_RESET"/>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>INSERT_VIP</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.C0_MMCM_CLKOUT3.INSERT_VIP">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
      </spirit:parameters>
      <spirit:vendorExtensions>
        <xilinx:busInterfaceInfo>
          <xilinx:enablement>
            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.C0_MMCM_CLKOUT3" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 ">false</xilinx:isEnabled>
          </xilinx:enablement>
        </xilinx:busInterfaceInfo>
      </spirit:vendorExtensions>
    </spirit:busInterface>
    <spirit:busInterface>
      <spirit:name>C0_MMCM_CLKOUT4</spirit:name>
      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
      <spirit:master/>
      <spirit:connectionRequired>true</spirit:connectionRequired>
      <spirit:portMaps>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>CLK</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c0_ui_addn_clk_4</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
      </spirit:portMaps>
      <spirit:parameters>
        <spirit:parameter>
          <spirit:name>FREQ_HZ</spirit:name>
          <spirit:value spirit:format="float" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.C0_MMCM_CLKOUT4.FREQ_HZ" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MMCM_CLKOUT4_FREQ&apos;))">10</spirit:value>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>ASSOCIATED_ASYNC_RESET</spirit:name>
          <spirit:value spirit:id="BUSIFPARAM_VALUE.C0_MMCM_CLKOUT4.ASSOCIATED_ASYNC_RESET">c0_aresetn</spirit:value>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>PHASE</spirit:name>
          <spirit:value spirit:format="float" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.C0_MMCM_CLKOUT4.PHASE" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C0_PHASE&apos;))">0</spirit:value>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>CLK_DOMAIN</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C0_MMCM_CLKOUT4.CLK_DOMAIN"/>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>ASSOCIATED_BUSIF</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C0_MMCM_CLKOUT4.ASSOCIATED_BUSIF"/>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>ASSOCIATED_RESET</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C0_MMCM_CLKOUT4.ASSOCIATED_RESET"/>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>INSERT_VIP</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.C0_MMCM_CLKOUT4.INSERT_VIP">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
      </spirit:parameters>
      <spirit:vendorExtensions>
        <xilinx:busInterfaceInfo>
          <xilinx:enablement>
            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.C0_MMCM_CLKOUT4" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 ">false</xilinx:isEnabled>
          </xilinx:enablement>
        </xilinx:busInterfaceInfo>
      </spirit:vendorExtensions>
    </spirit:busInterface>
    <spirit:busInterface>
      <spirit:name>S0_AXI_CTRL</spirit:name>
      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm" spirit:version="1.0"/>
      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm_rtl" spirit:version="1.0"/>
      <spirit:slave>
        <spirit:memoryMapRef spirit:memoryMapRef="c0_s_axi_ctrl_memmap"/>
      </spirit:slave>
      <spirit:connectionRequired>true</spirit:connectionRequired>
      <spirit:portMaps>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>AWVALID</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c0_s_axi_ctrl_awvalid</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>AWREADY</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c0_s_axi_ctrl_awready</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>AWADDR</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c0_s_axi_ctrl_awaddr</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>WVALID</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c0_s_axi_ctrl_wvalid</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>WREADY</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c0_s_axi_ctrl_wready</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>WDATA</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c0_s_axi_ctrl_wdata</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>BVALID</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c0_s_axi_ctrl_bvalid</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>BREADY</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c0_s_axi_ctrl_bready</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>BRESP</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c0_s_axi_ctrl_bresp</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>ARVALID</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c0_s_axi_ctrl_arvalid</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>ARREADY</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c0_s_axi_ctrl_arready</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>ARADDR</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c0_s_axi_ctrl_araddr</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>RVALID</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c0_s_axi_ctrl_rvalid</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>RREADY</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c0_s_axi_ctrl_rready</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>RDATA</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c0_s_axi_ctrl_rdata</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>RRESP</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c0_s_axi_ctrl_rresp</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
      </spirit:portMaps>
      <spirit:parameters>
        <spirit:parameter>
          <spirit:name>FREQ_HZ</spirit:name>
          <spirit:value spirit:format="float" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.S0_AXI_CTRL.FREQ_HZ" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C0_FREQ_HZ&apos;))">100</spirit:value>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>DATA_WIDTH</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S0_AXI_CTRL.DATA_WIDTH">1</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>PROTOCOL</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S0_AXI_CTRL.PROTOCOL">AXI4LITE</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>ID_WIDTH</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S0_AXI_CTRL.ID_WIDTH">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>ADDR_WIDTH</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S0_AXI_CTRL.ADDR_WIDTH">1</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>AWUSER_WIDTH</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S0_AXI_CTRL.AWUSER_WIDTH">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>ARUSER_WIDTH</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S0_AXI_CTRL.ARUSER_WIDTH">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>WUSER_WIDTH</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S0_AXI_CTRL.WUSER_WIDTH">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>RUSER_WIDTH</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S0_AXI_CTRL.RUSER_WIDTH">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>BUSER_WIDTH</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S0_AXI_CTRL.BUSER_WIDTH">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>READ_WRITE_MODE</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S0_AXI_CTRL.READ_WRITE_MODE">READ_WRITE</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>HAS_BURST</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S0_AXI_CTRL.HAS_BURST">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>HAS_LOCK</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S0_AXI_CTRL.HAS_LOCK">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>HAS_PROT</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S0_AXI_CTRL.HAS_PROT">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>HAS_CACHE</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S0_AXI_CTRL.HAS_CACHE">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>HAS_QOS</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S0_AXI_CTRL.HAS_QOS">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>HAS_REGION</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S0_AXI_CTRL.HAS_REGION">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>HAS_WSTRB</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S0_AXI_CTRL.HAS_WSTRB">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>HAS_BRESP</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S0_AXI_CTRL.HAS_BRESP">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>HAS_RRESP</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S0_AXI_CTRL.HAS_RRESP">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>SUPPORTS_NARROW_BURST</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S0_AXI_CTRL.SUPPORTS_NARROW_BURST">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>NUM_READ_OUTSTANDING</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S0_AXI_CTRL.NUM_READ_OUTSTANDING">1</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>NUM_WRITE_OUTSTANDING</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S0_AXI_CTRL.NUM_WRITE_OUTSTANDING">1</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>MAX_BURST_LENGTH</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S0_AXI_CTRL.MAX_BURST_LENGTH">1</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>PHASE</spirit:name>
          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S0_AXI_CTRL.PHASE">0.000</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>CLK_DOMAIN</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S0_AXI_CTRL.CLK_DOMAIN"/>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>NUM_READ_THREADS</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S0_AXI_CTRL.NUM_READ_THREADS">1</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>NUM_WRITE_THREADS</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S0_AXI_CTRL.NUM_WRITE_THREADS">1</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>RUSER_BITS_PER_BYTE</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S0_AXI_CTRL.RUSER_BITS_PER_BYTE">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>WUSER_BITS_PER_BYTE</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S0_AXI_CTRL.WUSER_BITS_PER_BYTE">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>INSERT_VIP</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.S0_AXI_CTRL.INSERT_VIP">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
      </spirit:parameters>
      <spirit:vendorExtensions>
        <xilinx:busInterfaceInfo>
          <xilinx:enablement>
            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.S0_AXI_CTRL" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_USE_AXI&apos;)) = 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_ECC&apos;)) = &quot;ON&quot; ) ">false</xilinx:isEnabled>
          </xilinx:enablement>
        </xilinx:busInterfaceInfo>
      </spirit:vendorExtensions>
    </spirit:busInterface>
    <spirit:busInterface>
      <spirit:name>S0_AXI</spirit:name>
      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm" spirit:version="1.0"/>
      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm_rtl" spirit:version="1.0"/>
      <spirit:slave>
        <spirit:memoryMapRef spirit:memoryMapRef="c0_memmap"/>
      </spirit:slave>
      <spirit:connectionRequired>true</spirit:connectionRequired>
      <spirit:portMaps>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>AWID</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c0_s_axi_awid</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>AWADDR</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c0_s_axi_awaddr</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>AWLEN</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c0_s_axi_awlen</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>AWSIZE</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c0_s_axi_awsize</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>AWBURST</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c0_s_axi_awburst</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>AWLOCK</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c0_s_axi_awlock</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>AWCACHE</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c0_s_axi_awcache</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>AWPROT</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c0_s_axi_awprot</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>AWQOS</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c0_s_axi_awqos</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>AWVALID</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c0_s_axi_awvalid</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>AWREADY</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c0_s_axi_awready</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>WDATA</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c0_s_axi_wdata</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>WSTRB</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c0_s_axi_wstrb</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>WLAST</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c0_s_axi_wlast</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>WVALID</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c0_s_axi_wvalid</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>WREADY</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c0_s_axi_wready</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>BREADY</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c0_s_axi_bready</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>BID</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c0_s_axi_bid</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>BRESP</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c0_s_axi_bresp</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>BVALID</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c0_s_axi_bvalid</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>ARID</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c0_s_axi_arid</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>ARADDR</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c0_s_axi_araddr</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>ARLEN</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c0_s_axi_arlen</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>ARSIZE</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c0_s_axi_arsize</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>ARBURST</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c0_s_axi_arburst</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>ARLOCK</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c0_s_axi_arlock</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>ARCACHE</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c0_s_axi_arcache</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>ARPROT</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c0_s_axi_arprot</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>ARQOS</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c0_s_axi_arqos</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>ARVALID</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c0_s_axi_arvalid</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>ARREADY</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c0_s_axi_arready</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>RREADY</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c0_s_axi_rready</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>RID</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c0_s_axi_rid</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>RDATA</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c0_s_axi_rdata</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>RRESP</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c0_s_axi_rresp</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>RLAST</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c0_s_axi_rlast</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>RVALID</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c0_s_axi_rvalid</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
      </spirit:portMaps>
      <spirit:parameters>
        <spirit:parameter>
          <spirit:name>FREQ_HZ</spirit:name>
          <spirit:value spirit:format="float" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.S0_AXI.FREQ_HZ" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C0_FREQ_HZ&apos;))">100</spirit:value>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>DATA_WIDTH</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S0_AXI.DATA_WIDTH">1</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>PROTOCOL</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S0_AXI.PROTOCOL">AXI4LITE</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>ID_WIDTH</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S0_AXI.ID_WIDTH">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>ADDR_WIDTH</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S0_AXI.ADDR_WIDTH">1</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>AWUSER_WIDTH</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S0_AXI.AWUSER_WIDTH">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>ARUSER_WIDTH</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S0_AXI.ARUSER_WIDTH">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>WUSER_WIDTH</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S0_AXI.WUSER_WIDTH">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>RUSER_WIDTH</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S0_AXI.RUSER_WIDTH">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>BUSER_WIDTH</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S0_AXI.BUSER_WIDTH">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>READ_WRITE_MODE</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S0_AXI.READ_WRITE_MODE">READ_WRITE</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>HAS_BURST</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S0_AXI.HAS_BURST">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>HAS_LOCK</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S0_AXI.HAS_LOCK">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>HAS_PROT</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S0_AXI.HAS_PROT">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>HAS_CACHE</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S0_AXI.HAS_CACHE">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>HAS_QOS</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S0_AXI.HAS_QOS">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>HAS_REGION</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S0_AXI.HAS_REGION">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>HAS_WSTRB</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S0_AXI.HAS_WSTRB">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>HAS_BRESP</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S0_AXI.HAS_BRESP">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>HAS_RRESP</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S0_AXI.HAS_RRESP">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>SUPPORTS_NARROW_BURST</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S0_AXI.SUPPORTS_NARROW_BURST">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>NUM_READ_OUTSTANDING</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S0_AXI.NUM_READ_OUTSTANDING">1</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>NUM_WRITE_OUTSTANDING</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S0_AXI.NUM_WRITE_OUTSTANDING">1</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>MAX_BURST_LENGTH</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S0_AXI.MAX_BURST_LENGTH">1</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>PHASE</spirit:name>
          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S0_AXI.PHASE">0.000</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>CLK_DOMAIN</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S0_AXI.CLK_DOMAIN"/>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>NUM_READ_THREADS</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S0_AXI.NUM_READ_THREADS">1</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>NUM_WRITE_THREADS</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S0_AXI.NUM_WRITE_THREADS">1</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>RUSER_BITS_PER_BYTE</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S0_AXI.RUSER_BITS_PER_BYTE">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>WUSER_BITS_PER_BYTE</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S0_AXI.WUSER_BITS_PER_BYTE">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>INSERT_VIP</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.S0_AXI.INSERT_VIP">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
      </spirit:parameters>
      <spirit:vendorExtensions>
        <xilinx:busInterfaceInfo>
          <xilinx:enablement>
            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.S0_AXI" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
          </xilinx:enablement>
        </xilinx:busInterfaceInfo>
      </spirit:vendorExtensions>
    </spirit:busInterface>
    <spirit:busInterface>
      <spirit:name>C0_SYS_CLK</spirit:name>
      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="diff_clock" spirit:version="1.0"/>
      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="diff_clock_rtl" spirit:version="1.0"/>
      <spirit:slave/>
      <spirit:connectionRequired>true</spirit:connectionRequired>
      <spirit:portMaps>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>CLK_P</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c0_sys_clk_p</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>CLK_N</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c0_sys_clk_n</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
      </spirit:portMaps>
      <spirit:parameters>
        <spirit:parameter>
          <spirit:name>CAN_DEBUG</spirit:name>
          <spirit:value spirit:format="bool" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C0_SYS_CLK.CAN_DEBUG">false</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>FREQ_HZ</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C0_SYS_CLK.FREQ_HZ">100000000</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
      </spirit:parameters>
      <spirit:vendorExtensions>
        <xilinx:busInterfaceInfo>
          <xilinx:enablement>
            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.C0_SYS_CLK" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_SYSCLK_TYPE&apos;)) = &quot;DIFF&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_IS_CLK_SHARED&apos;)) = &quot;FALSE&quot; ">false</xilinx:isEnabled>
          </xilinx:enablement>
        </xilinx:busInterfaceInfo>
      </spirit:vendorExtensions>
    </spirit:busInterface>
    <spirit:busInterface>
      <spirit:name>C0_SYS_CLK_I</spirit:name>
      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
      <spirit:slave/>
      <spirit:connectionRequired>true</spirit:connectionRequired>
      <spirit:portMaps>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>CLK</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c0_sys_clk_i</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
      </spirit:portMaps>
      <spirit:parameters>
        <spirit:parameter>
          <spirit:name>FREQ_HZ</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C0_SYS_CLK_I.FREQ_HZ">100000000</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>PHASE</spirit:name>
          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C0_SYS_CLK_I.PHASE">0.000</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>CLK_DOMAIN</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C0_SYS_CLK_I.CLK_DOMAIN"/>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>ASSOCIATED_BUSIF</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C0_SYS_CLK_I.ASSOCIATED_BUSIF"/>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>ASSOCIATED_RESET</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C0_SYS_CLK_I.ASSOCIATED_RESET"/>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>INSERT_VIP</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.C0_SYS_CLK_I.INSERT_VIP">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
      </spirit:parameters>
      <spirit:vendorExtensions>
        <xilinx:busInterfaceInfo>
          <xilinx:enablement>
            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.C0_SYS_CLK_I" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_SYSCLK_TYPE&apos;)) != &quot;DIFF&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_IS_CLK_SHARED&apos;)) = &quot;FALSE&quot; ">false</xilinx:isEnabled>
          </xilinx:enablement>
        </xilinx:busInterfaceInfo>
      </spirit:vendorExtensions>
    </spirit:busInterface>
    <spirit:busInterface>
      <spirit:name>C0_ARESETN</spirit:name>
      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
      <spirit:slave/>
      <spirit:connectionRequired>true</spirit:connectionRequired>
      <spirit:portMaps>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>ARESETN</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c0_aresetn</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
      </spirit:portMaps>
      <spirit:parameters>
        <spirit:parameter>
          <spirit:name>POLARITY</spirit:name>
          <spirit:value spirit:id="BUSIFPARAM_VALUE.C0_ARESETN.POLARITY">ACTIVE_LOW</spirit:value>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>INSERT_VIP</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.C0_ARESETN.INSERT_VIP">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
      </spirit:parameters>
    </spirit:busInterface>
    <spirit:busInterface>
      <spirit:name>C1_DDR3</spirit:name>
      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="ddrx" spirit:version="1.0"/>
      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="ddrx_rtl" spirit:version="1.0"/>
      <spirit:master/>
      <spirit:connectionRequired>true</spirit:connectionRequired>
      <spirit:portMaps>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>DQ</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c1_ddr3_dq</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>DQS_P</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c1_ddr3_dqs_p</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>DQS_N</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c1_ddr3_dqs_n</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>ADDR</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c1_ddr3_addr</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>BA</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c1_ddr3_ba</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>RAS_N</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c1_ddr3_ras_n</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>CAS_N</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c1_ddr3_cas_n</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>WE_N</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c1_ddr3_we_n</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>RESET_N</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c1_ddr3_reset_n</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>CK_P</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c1_ddr3_ck_p</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>CK_N</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c1_ddr3_ck_n</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>CKE</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c1_ddr3_cke</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>CS_N</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c1_ddr3_cs_n</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>DM</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c1_ddr3_dm</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>ODT</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c1_ddr3_odt</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>PARITY</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c1_ddr3_parity</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
      </spirit:portMaps>
      <spirit:parameters>
        <spirit:parameter>
          <spirit:name>CAN_DEBUG</spirit:name>
          <spirit:value spirit:format="bool" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C1_DDR3.CAN_DEBUG">false</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>TIMEPERIOD_PS</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C1_DDR3.TIMEPERIOD_PS">1250</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>MEMORY_TYPE</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C1_DDR3.MEMORY_TYPE">COMPONENTS</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>MEMORY_PART</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C1_DDR3.MEMORY_PART"/>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>DATA_WIDTH</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C1_DDR3.DATA_WIDTH">8</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>CS_ENABLED</spirit:name>
          <spirit:value spirit:format="bool" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C1_DDR3.CS_ENABLED">true</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>DATA_MASK_ENABLED</spirit:name>
          <spirit:value spirit:format="bool" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C1_DDR3.DATA_MASK_ENABLED">true</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>SLOT</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C1_DDR3.SLOT">Single</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>CUSTOM_PARTS</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C1_DDR3.CUSTOM_PARTS"/>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>MEM_ADDR_MAP</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C1_DDR3.MEM_ADDR_MAP">ROW_COLUMN_BANK</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>BURST_LENGTH</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C1_DDR3.BURST_LENGTH">8</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>AXI_ARBITRATION_SCHEME</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C1_DDR3.AXI_ARBITRATION_SCHEME">TDM</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>CAS_LATENCY</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C1_DDR3.CAS_LATENCY">11</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>CAS_WRITE_LATENCY</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C1_DDR3.CAS_WRITE_LATENCY">11</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
      </spirit:parameters>
      <spirit:vendorExtensions>
        <xilinx:busInterfaceInfo>
          <xilinx:enablement>
            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.C1_DDR3" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;DDR3&quot; ">false</xilinx:isEnabled>
          </xilinx:enablement>
        </xilinx:busInterfaceInfo>
      </spirit:vendorExtensions>
    </spirit:busInterface>
    <spirit:busInterface>
      <spirit:name>C1_DDR2</spirit:name>
      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="ddrx" spirit:version="1.0"/>
      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="ddrx_rtl" spirit:version="1.0"/>
      <spirit:master/>
      <spirit:connectionRequired>true</spirit:connectionRequired>
      <spirit:portMaps>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>DQ</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c1_ddr2_dq</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>DQS_P</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c1_ddr2_dqs_p</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>DQS_N</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c1_ddr2_dqs_n</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>ADDR</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c1_ddr2_addr</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>BA</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c1_ddr2_ba</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>RAS_N</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c1_ddr2_ras_n</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>CAS_N</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c1_ddr2_cas_n</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>WE_N</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c1_ddr2_we_n</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>RESET_N</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c1_ddr2_reset_n</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>CK_P</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c1_ddr2_ck_p</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>CK_N</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c1_ddr2_ck_n</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>CKE</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c1_ddr2_cke</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>CS_N</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c1_ddr2_cs_n</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>DM</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c1_ddr2_dm</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>ODT</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c1_ddr2_odt</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>PARITY</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c1_ddr2_parity</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
      </spirit:portMaps>
      <spirit:parameters>
        <spirit:parameter>
          <spirit:name>CAN_DEBUG</spirit:name>
          <spirit:value spirit:format="bool" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C1_DDR2.CAN_DEBUG">false</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>TIMEPERIOD_PS</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C1_DDR2.TIMEPERIOD_PS">1250</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>MEMORY_TYPE</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C1_DDR2.MEMORY_TYPE">COMPONENTS</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>MEMORY_PART</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C1_DDR2.MEMORY_PART"/>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>DATA_WIDTH</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C1_DDR2.DATA_WIDTH">8</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>CS_ENABLED</spirit:name>
          <spirit:value spirit:format="bool" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C1_DDR2.CS_ENABLED">true</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>DATA_MASK_ENABLED</spirit:name>
          <spirit:value spirit:format="bool" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C1_DDR2.DATA_MASK_ENABLED">true</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>SLOT</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C1_DDR2.SLOT">Single</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>CUSTOM_PARTS</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C1_DDR2.CUSTOM_PARTS"/>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>MEM_ADDR_MAP</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C1_DDR2.MEM_ADDR_MAP">ROW_COLUMN_BANK</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>BURST_LENGTH</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C1_DDR2.BURST_LENGTH">8</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>AXI_ARBITRATION_SCHEME</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C1_DDR2.AXI_ARBITRATION_SCHEME">TDM</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>CAS_LATENCY</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C1_DDR2.CAS_LATENCY">11</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>CAS_WRITE_LATENCY</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C1_DDR2.CAS_WRITE_LATENCY">11</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
      </spirit:parameters>
      <spirit:vendorExtensions>
        <xilinx:busInterfaceInfo>
          <xilinx:enablement>
            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.C1_DDR2" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;DDR2&quot; ">false</xilinx:isEnabled>
          </xilinx:enablement>
        </xilinx:busInterfaceInfo>
      </spirit:vendorExtensions>
    </spirit:busInterface>
    <spirit:busInterface>
      <spirit:name>C1_RESET</spirit:name>
      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
      <spirit:master/>
      <spirit:connectionRequired>true</spirit:connectionRequired>
      <spirit:portMaps>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>RST</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c1_ui_clk_sync_rst</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
      </spirit:portMaps>
      <spirit:parameters>
        <spirit:parameter>
          <spirit:name>POLARITY</spirit:name>
          <spirit:value spirit:id="BUSIFPARAM_VALUE.C1_RESET.POLARITY">ACTIVE_HIGH</spirit:value>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>INSERT_VIP</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.C1_RESET.INSERT_VIP">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
      </spirit:parameters>
      <spirit:vendorExtensions>
        <xilinx:busInterfaceInfo>
          <xilinx:enablement>
            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.C1_RESET" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 ">false</xilinx:isEnabled>
          </xilinx:enablement>
        </xilinx:busInterfaceInfo>
      </spirit:vendorExtensions>
    </spirit:busInterface>
    <spirit:busInterface>
      <spirit:name>C1_DDR3_RESET</spirit:name>
      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
      <spirit:master/>
      <spirit:connectionRequired>true</spirit:connectionRequired>
      <spirit:portMaps>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>RST</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c1_ddr3_ui_clk_sync_rst</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
      </spirit:portMaps>
      <spirit:parameters>
        <spirit:parameter>
          <spirit:name>POLARITY</spirit:name>
          <spirit:value spirit:id="BUSIFPARAM_VALUE.C1_DDR3_RESET.POLARITY">ACTIVE_HIGH</spirit:value>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>INSERT_VIP</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.C1_DDR3_RESET.INSERT_VIP">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
      </spirit:parameters>
      <spirit:vendorExtensions>
        <xilinx:busInterfaceInfo>
          <xilinx:enablement>
            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.C1_DDR3_RESET" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 ">false</xilinx:isEnabled>
          </xilinx:enablement>
        </xilinx:busInterfaceInfo>
      </spirit:vendorExtensions>
    </spirit:busInterface>
    <spirit:busInterface>
      <spirit:name>C1_DDR2_RESET</spirit:name>
      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
      <spirit:master/>
      <spirit:connectionRequired>true</spirit:connectionRequired>
      <spirit:portMaps>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>RST</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c1_ddr2_ui_clk_sync_rst</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
      </spirit:portMaps>
      <spirit:parameters>
        <spirit:parameter>
          <spirit:name>POLARITY</spirit:name>
          <spirit:value spirit:id="BUSIFPARAM_VALUE.C1_DDR2_RESET.POLARITY">ACTIVE_HIGH</spirit:value>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>INSERT_VIP</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.C1_DDR2_RESET.INSERT_VIP">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
      </spirit:parameters>
      <spirit:vendorExtensions>
        <xilinx:busInterfaceInfo>
          <xilinx:enablement>
            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.C1_DDR2_RESET" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 ">false</xilinx:isEnabled>
          </xilinx:enablement>
        </xilinx:busInterfaceInfo>
      </spirit:vendorExtensions>
    </spirit:busInterface>
    <spirit:busInterface>
      <spirit:name>C1_LPDDR2_RESET</spirit:name>
      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
      <spirit:master/>
      <spirit:connectionRequired>true</spirit:connectionRequired>
      <spirit:portMaps>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>RST</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c1_lpddr2_ui_clk_sync_rst</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
      </spirit:portMaps>
      <spirit:parameters>
        <spirit:parameter>
          <spirit:name>POLARITY</spirit:name>
          <spirit:value spirit:id="BUSIFPARAM_VALUE.C1_LPDDR2_RESET.POLARITY">ACTIVE_HIGH</spirit:value>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>INSERT_VIP</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.C1_LPDDR2_RESET.INSERT_VIP">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
      </spirit:parameters>
      <spirit:vendorExtensions>
        <xilinx:busInterfaceInfo>
          <xilinx:enablement>
            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.C1_LPDDR2_RESET" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 ">false</xilinx:isEnabled>
          </xilinx:enablement>
        </xilinx:busInterfaceInfo>
      </spirit:vendorExtensions>
    </spirit:busInterface>
    <spirit:busInterface>
      <spirit:name>C1_QDRIIP_RESET</spirit:name>
      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
      <spirit:master/>
      <spirit:connectionRequired>true</spirit:connectionRequired>
      <spirit:portMaps>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>RST</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c1_qdriip_ui_clk_sync_rst</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
      </spirit:portMaps>
      <spirit:parameters>
        <spirit:parameter>
          <spirit:name>POLARITY</spirit:name>
          <spirit:value spirit:id="BUSIFPARAM_VALUE.C1_QDRIIP_RESET.POLARITY">ACTIVE_HIGH</spirit:value>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>INSERT_VIP</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.C1_QDRIIP_RESET.INSERT_VIP">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
      </spirit:parameters>
      <spirit:vendorExtensions>
        <xilinx:busInterfaceInfo>
          <xilinx:enablement>
            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.C1_QDRIIP_RESET" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 ">false</xilinx:isEnabled>
          </xilinx:enablement>
        </xilinx:busInterfaceInfo>
      </spirit:vendorExtensions>
    </spirit:busInterface>
    <spirit:busInterface>
      <spirit:name>C1_RLDII_RESET</spirit:name>
      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
      <spirit:master/>
      <spirit:connectionRequired>true</spirit:connectionRequired>
      <spirit:portMaps>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>RST</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c1_rldii_ui_clk_sync_rst</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
      </spirit:portMaps>
      <spirit:parameters>
        <spirit:parameter>
          <spirit:name>POLARITY</spirit:name>
          <spirit:value spirit:id="BUSIFPARAM_VALUE.C1_RLDII_RESET.POLARITY">ACTIVE_HIGH</spirit:value>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>INSERT_VIP</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.C1_RLDII_RESET.INSERT_VIP">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
      </spirit:parameters>
      <spirit:vendorExtensions>
        <xilinx:busInterfaceInfo>
          <xilinx:enablement>
            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.C1_RLDII_RESET" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 ">false</xilinx:isEnabled>
          </xilinx:enablement>
        </xilinx:busInterfaceInfo>
      </spirit:vendorExtensions>
    </spirit:busInterface>
    <spirit:busInterface>
      <spirit:name>C1_RLDIII_RESET</spirit:name>
      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
      <spirit:master/>
      <spirit:connectionRequired>true</spirit:connectionRequired>
      <spirit:portMaps>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>RST</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c1_rldiii_ui_clk_sync_rst</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
      </spirit:portMaps>
      <spirit:parameters>
        <spirit:parameter>
          <spirit:name>POLARITY</spirit:name>
          <spirit:value spirit:id="BUSIFPARAM_VALUE.C1_RLDIII_RESET.POLARITY">ACTIVE_HIGH</spirit:value>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>INSERT_VIP</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.C1_RLDIII_RESET.INSERT_VIP">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
      </spirit:parameters>
      <spirit:vendorExtensions>
        <xilinx:busInterfaceInfo>
          <xilinx:enablement>
            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.C1_RLDIII_RESET" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 ">false</xilinx:isEnabled>
          </xilinx:enablement>
        </xilinx:busInterfaceInfo>
      </spirit:vendorExtensions>
    </spirit:busInterface>
    <spirit:busInterface>
      <spirit:name>C1_CLOCK</spirit:name>
      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
      <spirit:master/>
      <spirit:connectionRequired>true</spirit:connectionRequired>
      <spirit:portMaps>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>CLK</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c1_ui_clk</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
      </spirit:portMaps>
      <spirit:parameters>
        <spirit:parameter>
          <spirit:name>FREQ_HZ</spirit:name>
          <spirit:value spirit:format="float" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.C1_CLOCK.FREQ_HZ" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C1_FREQ_HZ&apos;))">100</spirit:value>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>ASSOCIATED_BUSIF</spirit:name>
          <spirit:value spirit:id="BUSIFPARAM_VALUE.C1_CLOCK.ASSOCIATED_BUSIF">S1_AXI:S1_AXI_CTRL</spirit:value>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>ASSOCIATED_RESET</spirit:name>
          <spirit:value spirit:id="BUSIFPARAM_VALUE.C1_CLOCK.ASSOCIATED_RESET">c1_aresetn:c1_ui_clk_sync_rst</spirit:value>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>PHASE</spirit:name>
          <spirit:value spirit:format="float" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.C1_CLOCK.PHASE" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C1_PHASE&apos;))">0</spirit:value>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>CLK_DOMAIN</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C1_CLOCK.CLK_DOMAIN"/>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>INSERT_VIP</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.C1_CLOCK.INSERT_VIP">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
      </spirit:parameters>
      <spirit:vendorExtensions>
        <xilinx:busInterfaceInfo>
          <xilinx:enablement>
            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.C1_CLOCK" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 ">false</xilinx:isEnabled>
          </xilinx:enablement>
        </xilinx:busInterfaceInfo>
      </spirit:vendorExtensions>
    </spirit:busInterface>
    <spirit:busInterface>
      <spirit:name>C1_MMCM_CLKOUT0</spirit:name>
      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
      <spirit:master/>
      <spirit:connectionRequired>true</spirit:connectionRequired>
      <spirit:portMaps>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>CLK</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c1_ui_addn_clk_0</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
      </spirit:portMaps>
      <spirit:parameters>
        <spirit:parameter>
          <spirit:name>FREQ_HZ</spirit:name>
          <spirit:value spirit:format="float" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.C1_MMCM_CLKOUT0.FREQ_HZ" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MMCM_CLKOUT0_FREQ&apos;))">10</spirit:value>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>ASSOCIATED_ASYNC_RESET</spirit:name>
          <spirit:value spirit:id="BUSIFPARAM_VALUE.C1_MMCM_CLKOUT0.ASSOCIATED_ASYNC_RESET">c1_aresetn</spirit:value>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>PHASE</spirit:name>
          <spirit:value spirit:format="float" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.C1_MMCM_CLKOUT0.PHASE" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C1_PHASE&apos;))">0</spirit:value>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>CLK_DOMAIN</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C1_MMCM_CLKOUT0.CLK_DOMAIN"/>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>ASSOCIATED_BUSIF</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C1_MMCM_CLKOUT0.ASSOCIATED_BUSIF"/>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>ASSOCIATED_RESET</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C1_MMCM_CLKOUT0.ASSOCIATED_RESET"/>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>INSERT_VIP</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.C1_MMCM_CLKOUT0.INSERT_VIP">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
      </spirit:parameters>
      <spirit:vendorExtensions>
        <xilinx:busInterfaceInfo>
          <xilinx:enablement>
            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.C1_MMCM_CLKOUT0" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 ">false</xilinx:isEnabled>
          </xilinx:enablement>
        </xilinx:busInterfaceInfo>
      </spirit:vendorExtensions>
    </spirit:busInterface>
    <spirit:busInterface>
      <spirit:name>C1_MMCM_CLKOUT1</spirit:name>
      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
      <spirit:master/>
      <spirit:connectionRequired>true</spirit:connectionRequired>
      <spirit:portMaps>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>CLK</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c1_ui_addn_clk_1</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
      </spirit:portMaps>
      <spirit:parameters>
        <spirit:parameter>
          <spirit:name>FREQ_HZ</spirit:name>
          <spirit:value spirit:format="float" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.C1_MMCM_CLKOUT1.FREQ_HZ" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MMCM_CLKOUT1_FREQ&apos;))">10</spirit:value>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>ASSOCIATED_ASYNC_RESET</spirit:name>
          <spirit:value spirit:id="BUSIFPARAM_VALUE.C1_MMCM_CLKOUT1.ASSOCIATED_ASYNC_RESET">c1_aresetn</spirit:value>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>PHASE</spirit:name>
          <spirit:value spirit:format="float" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.C1_MMCM_CLKOUT1.PHASE" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C1_PHASE&apos;))">0</spirit:value>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>CLK_DOMAIN</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C1_MMCM_CLKOUT1.CLK_DOMAIN"/>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>ASSOCIATED_BUSIF</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C1_MMCM_CLKOUT1.ASSOCIATED_BUSIF"/>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>ASSOCIATED_RESET</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C1_MMCM_CLKOUT1.ASSOCIATED_RESET"/>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>INSERT_VIP</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.C1_MMCM_CLKOUT1.INSERT_VIP">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
      </spirit:parameters>
      <spirit:vendorExtensions>
        <xilinx:busInterfaceInfo>
          <xilinx:enablement>
            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.C1_MMCM_CLKOUT1" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 ">false</xilinx:isEnabled>
          </xilinx:enablement>
        </xilinx:busInterfaceInfo>
      </spirit:vendorExtensions>
    </spirit:busInterface>
    <spirit:busInterface>
      <spirit:name>C1_MMCM_CLKOUT2</spirit:name>
      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
      <spirit:master/>
      <spirit:connectionRequired>true</spirit:connectionRequired>
      <spirit:portMaps>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>CLK</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c1_ui_addn_clk_2</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
      </spirit:portMaps>
      <spirit:parameters>
        <spirit:parameter>
          <spirit:name>FREQ_HZ</spirit:name>
          <spirit:value spirit:format="float" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.C1_MMCM_CLKOUT2.FREQ_HZ" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MMCM_CLKOUT2_FREQ&apos;))">10</spirit:value>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>ASSOCIATED_ASYNC_RESET</spirit:name>
          <spirit:value spirit:id="BUSIFPARAM_VALUE.C1_MMCM_CLKOUT2.ASSOCIATED_ASYNC_RESET">c1_aresetn</spirit:value>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>PHASE</spirit:name>
          <spirit:value spirit:format="float" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.C1_MMCM_CLKOUT2.PHASE" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C1_PHASE&apos;))">0</spirit:value>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>CLK_DOMAIN</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C1_MMCM_CLKOUT2.CLK_DOMAIN"/>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>ASSOCIATED_BUSIF</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C1_MMCM_CLKOUT2.ASSOCIATED_BUSIF"/>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>ASSOCIATED_RESET</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C1_MMCM_CLKOUT2.ASSOCIATED_RESET"/>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>INSERT_VIP</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.C1_MMCM_CLKOUT2.INSERT_VIP">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
      </spirit:parameters>
      <spirit:vendorExtensions>
        <xilinx:busInterfaceInfo>
          <xilinx:enablement>
            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.C1_MMCM_CLKOUT2" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 ">false</xilinx:isEnabled>
          </xilinx:enablement>
        </xilinx:busInterfaceInfo>
      </spirit:vendorExtensions>
    </spirit:busInterface>
    <spirit:busInterface>
      <spirit:name>C1_MMCM_CLKOUT3</spirit:name>
      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
      <spirit:master/>
      <spirit:connectionRequired>true</spirit:connectionRequired>
      <spirit:portMaps>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>CLK</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c1_ui_addn_clk_3</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
      </spirit:portMaps>
      <spirit:parameters>
        <spirit:parameter>
          <spirit:name>FREQ_HZ</spirit:name>
          <spirit:value spirit:format="float" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.C1_MMCM_CLKOUT3.FREQ_HZ" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MMCM_CLKOUT3_FREQ&apos;))">10</spirit:value>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>ASSOCIATED_ASYNC_RESET</spirit:name>
          <spirit:value spirit:id="BUSIFPARAM_VALUE.C1_MMCM_CLKOUT3.ASSOCIATED_ASYNC_RESET">c1_aresetn</spirit:value>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>PHASE</spirit:name>
          <spirit:value spirit:format="float" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.C1_MMCM_CLKOUT3.PHASE" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C1_PHASE&apos;))">0</spirit:value>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>CLK_DOMAIN</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C1_MMCM_CLKOUT3.CLK_DOMAIN"/>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>ASSOCIATED_BUSIF</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C1_MMCM_CLKOUT3.ASSOCIATED_BUSIF"/>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>ASSOCIATED_RESET</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C1_MMCM_CLKOUT3.ASSOCIATED_RESET"/>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>INSERT_VIP</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.C1_MMCM_CLKOUT3.INSERT_VIP">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
      </spirit:parameters>
      <spirit:vendorExtensions>
        <xilinx:busInterfaceInfo>
          <xilinx:enablement>
            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.C1_MMCM_CLKOUT3" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 ">false</xilinx:isEnabled>
          </xilinx:enablement>
        </xilinx:busInterfaceInfo>
      </spirit:vendorExtensions>
    </spirit:busInterface>
    <spirit:busInterface>
      <spirit:name>C1_MMCM_CLKOUT4</spirit:name>
      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
      <spirit:master/>
      <spirit:connectionRequired>true</spirit:connectionRequired>
      <spirit:portMaps>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>CLK</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c1_ui_addn_clk_4</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
      </spirit:portMaps>
      <spirit:parameters>
        <spirit:parameter>
          <spirit:name>FREQ_HZ</spirit:name>
          <spirit:value spirit:format="float" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.C1_MMCM_CLKOUT4.FREQ_HZ" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MMCM_CLKOUT4_FREQ&apos;))">10</spirit:value>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>ASSOCIATED_ASYNC_RESET</spirit:name>
          <spirit:value spirit:id="BUSIFPARAM_VALUE.C1_MMCM_CLKOUT4.ASSOCIATED_ASYNC_RESET">c1_aresetn</spirit:value>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>PHASE</spirit:name>
          <spirit:value spirit:format="float" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.C1_MMCM_CLKOUT4.PHASE" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C1_PHASE&apos;))">0</spirit:value>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>CLK_DOMAIN</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C1_MMCM_CLKOUT4.CLK_DOMAIN"/>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>ASSOCIATED_BUSIF</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C1_MMCM_CLKOUT4.ASSOCIATED_BUSIF"/>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>ASSOCIATED_RESET</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C1_MMCM_CLKOUT4.ASSOCIATED_RESET"/>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>INSERT_VIP</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.C1_MMCM_CLKOUT4.INSERT_VIP">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
      </spirit:parameters>
      <spirit:vendorExtensions>
        <xilinx:busInterfaceInfo>
          <xilinx:enablement>
            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.C1_MMCM_CLKOUT4" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 ">false</xilinx:isEnabled>
          </xilinx:enablement>
        </xilinx:busInterfaceInfo>
      </spirit:vendorExtensions>
    </spirit:busInterface>
    <spirit:busInterface>
      <spirit:name>S1_AXI_CTRL</spirit:name>
      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm" spirit:version="1.0"/>
      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm_rtl" spirit:version="1.0"/>
      <spirit:slave>
        <spirit:memoryMapRef spirit:memoryMapRef="c1_s_axi_ctrl_memmap"/>
      </spirit:slave>
      <spirit:connectionRequired>true</spirit:connectionRequired>
      <spirit:portMaps>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>AWVALID</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c1_s_axi_ctrl_awvalid</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>AWREADY</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c1_s_axi_ctrl_awready</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>AWADDR</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c1_s_axi_ctrl_awaddr</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>WVALID</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c1_s_axi_ctrl_wvalid</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>WREADY</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c1_s_axi_ctrl_wready</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>WDATA</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c1_s_axi_ctrl_wdata</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>BVALID</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c1_s_axi_ctrl_bvalid</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>BREADY</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c1_s_axi_ctrl_bready</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>BRESP</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c1_s_axi_ctrl_bresp</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>ARVALID</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c1_s_axi_ctrl_arvalid</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>ARREADY</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c1_s_axi_ctrl_arready</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>ARADDR</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c1_s_axi_ctrl_araddr</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>RVALID</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c1_s_axi_ctrl_rvalid</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>RREADY</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c1_s_axi_ctrl_rready</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>RDATA</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c1_s_axi_ctrl_rdata</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>RRESP</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c1_s_axi_ctrl_rresp</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
      </spirit:portMaps>
      <spirit:parameters>
        <spirit:parameter>
          <spirit:name>FREQ_HZ</spirit:name>
          <spirit:value spirit:format="float" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.S1_AXI_CTRL.FREQ_HZ" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C1_FREQ_HZ&apos;))">100</spirit:value>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>DATA_WIDTH</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S1_AXI_CTRL.DATA_WIDTH">1</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>PROTOCOL</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S1_AXI_CTRL.PROTOCOL">AXI4LITE</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>ID_WIDTH</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S1_AXI_CTRL.ID_WIDTH">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>ADDR_WIDTH</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S1_AXI_CTRL.ADDR_WIDTH">1</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>AWUSER_WIDTH</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S1_AXI_CTRL.AWUSER_WIDTH">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>ARUSER_WIDTH</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S1_AXI_CTRL.ARUSER_WIDTH">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>WUSER_WIDTH</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S1_AXI_CTRL.WUSER_WIDTH">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>RUSER_WIDTH</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S1_AXI_CTRL.RUSER_WIDTH">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>BUSER_WIDTH</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S1_AXI_CTRL.BUSER_WIDTH">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>READ_WRITE_MODE</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S1_AXI_CTRL.READ_WRITE_MODE">READ_WRITE</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>HAS_BURST</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S1_AXI_CTRL.HAS_BURST">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>HAS_LOCK</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S1_AXI_CTRL.HAS_LOCK">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>HAS_PROT</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S1_AXI_CTRL.HAS_PROT">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>HAS_CACHE</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S1_AXI_CTRL.HAS_CACHE">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>HAS_QOS</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S1_AXI_CTRL.HAS_QOS">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>HAS_REGION</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S1_AXI_CTRL.HAS_REGION">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>HAS_WSTRB</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S1_AXI_CTRL.HAS_WSTRB">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>HAS_BRESP</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S1_AXI_CTRL.HAS_BRESP">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>HAS_RRESP</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S1_AXI_CTRL.HAS_RRESP">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>SUPPORTS_NARROW_BURST</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S1_AXI_CTRL.SUPPORTS_NARROW_BURST">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>NUM_READ_OUTSTANDING</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S1_AXI_CTRL.NUM_READ_OUTSTANDING">1</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>NUM_WRITE_OUTSTANDING</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S1_AXI_CTRL.NUM_WRITE_OUTSTANDING">1</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>MAX_BURST_LENGTH</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S1_AXI_CTRL.MAX_BURST_LENGTH">1</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>PHASE</spirit:name>
          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S1_AXI_CTRL.PHASE">0.000</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>CLK_DOMAIN</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S1_AXI_CTRL.CLK_DOMAIN"/>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>NUM_READ_THREADS</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S1_AXI_CTRL.NUM_READ_THREADS">1</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>NUM_WRITE_THREADS</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S1_AXI_CTRL.NUM_WRITE_THREADS">1</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>RUSER_BITS_PER_BYTE</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S1_AXI_CTRL.RUSER_BITS_PER_BYTE">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>WUSER_BITS_PER_BYTE</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S1_AXI_CTRL.WUSER_BITS_PER_BYTE">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>INSERT_VIP</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.S1_AXI_CTRL.INSERT_VIP">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
      </spirit:parameters>
      <spirit:vendorExtensions>
        <xilinx:busInterfaceInfo>
          <xilinx:enablement>
            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.S1_AXI_CTRL" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_USE_AXI&apos;)) = 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_ECC&apos;)) = &quot;ON&quot; ) ">false</xilinx:isEnabled>
          </xilinx:enablement>
        </xilinx:busInterfaceInfo>
      </spirit:vendorExtensions>
    </spirit:busInterface>
    <spirit:busInterface>
      <spirit:name>S1_AXI</spirit:name>
      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm" spirit:version="1.0"/>
      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm_rtl" spirit:version="1.0"/>
      <spirit:slave>
        <spirit:memoryMapRef spirit:memoryMapRef="c1_memmap"/>
      </spirit:slave>
      <spirit:connectionRequired>true</spirit:connectionRequired>
      <spirit:portMaps>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>AWID</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c1_s_axi_awid</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>AWADDR</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c1_s_axi_awaddr</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>AWLEN</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c1_s_axi_awlen</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>AWSIZE</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c1_s_axi_awsize</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>AWBURST</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c1_s_axi_awburst</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>AWLOCK</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c1_s_axi_awlock</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>AWCACHE</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c1_s_axi_awcache</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>AWPROT</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c1_s_axi_awprot</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>AWQOS</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c1_s_axi_awqos</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>AWVALID</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c1_s_axi_awvalid</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>AWREADY</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c1_s_axi_awready</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>WDATA</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c1_s_axi_wdata</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>WSTRB</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c1_s_axi_wstrb</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>WLAST</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c1_s_axi_wlast</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>WVALID</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c1_s_axi_wvalid</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>WREADY</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c1_s_axi_wready</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>BREADY</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c1_s_axi_bready</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>BID</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c1_s_axi_bid</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>BRESP</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c1_s_axi_bresp</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>BVALID</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c1_s_axi_bvalid</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>ARID</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c1_s_axi_arid</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>ARADDR</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c1_s_axi_araddr</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>ARLEN</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c1_s_axi_arlen</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>ARSIZE</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c1_s_axi_arsize</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>ARBURST</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c1_s_axi_arburst</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>ARLOCK</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c1_s_axi_arlock</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>ARCACHE</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c1_s_axi_arcache</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>ARPROT</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c1_s_axi_arprot</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>ARQOS</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c1_s_axi_arqos</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>ARVALID</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c1_s_axi_arvalid</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>ARREADY</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c1_s_axi_arready</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>RREADY</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c1_s_axi_rready</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>RID</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c1_s_axi_rid</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>RDATA</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c1_s_axi_rdata</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>RRESP</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c1_s_axi_rresp</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>RLAST</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c1_s_axi_rlast</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>RVALID</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c1_s_axi_rvalid</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
      </spirit:portMaps>
      <spirit:parameters>
        <spirit:parameter>
          <spirit:name>FREQ_HZ</spirit:name>
          <spirit:value spirit:format="float" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.S1_AXI.FREQ_HZ" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C1_FREQ_HZ&apos;))">100</spirit:value>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>DATA_WIDTH</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S1_AXI.DATA_WIDTH">1</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>PROTOCOL</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S1_AXI.PROTOCOL">AXI4LITE</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>ID_WIDTH</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S1_AXI.ID_WIDTH">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>ADDR_WIDTH</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S1_AXI.ADDR_WIDTH">1</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>AWUSER_WIDTH</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S1_AXI.AWUSER_WIDTH">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>ARUSER_WIDTH</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S1_AXI.ARUSER_WIDTH">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>WUSER_WIDTH</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S1_AXI.WUSER_WIDTH">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>RUSER_WIDTH</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S1_AXI.RUSER_WIDTH">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>BUSER_WIDTH</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S1_AXI.BUSER_WIDTH">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>READ_WRITE_MODE</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S1_AXI.READ_WRITE_MODE">READ_WRITE</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>HAS_BURST</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S1_AXI.HAS_BURST">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>HAS_LOCK</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S1_AXI.HAS_LOCK">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>HAS_PROT</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S1_AXI.HAS_PROT">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>HAS_CACHE</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S1_AXI.HAS_CACHE">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>HAS_QOS</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S1_AXI.HAS_QOS">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>HAS_REGION</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S1_AXI.HAS_REGION">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>HAS_WSTRB</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S1_AXI.HAS_WSTRB">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>HAS_BRESP</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S1_AXI.HAS_BRESP">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>HAS_RRESP</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S1_AXI.HAS_RRESP">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>SUPPORTS_NARROW_BURST</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S1_AXI.SUPPORTS_NARROW_BURST">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>NUM_READ_OUTSTANDING</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S1_AXI.NUM_READ_OUTSTANDING">1</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>NUM_WRITE_OUTSTANDING</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S1_AXI.NUM_WRITE_OUTSTANDING">1</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>MAX_BURST_LENGTH</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S1_AXI.MAX_BURST_LENGTH">1</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>PHASE</spirit:name>
          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S1_AXI.PHASE">0.000</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>CLK_DOMAIN</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S1_AXI.CLK_DOMAIN"/>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>NUM_READ_THREADS</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S1_AXI.NUM_READ_THREADS">1</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>NUM_WRITE_THREADS</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S1_AXI.NUM_WRITE_THREADS">1</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>RUSER_BITS_PER_BYTE</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S1_AXI.RUSER_BITS_PER_BYTE">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>WUSER_BITS_PER_BYTE</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S1_AXI.WUSER_BITS_PER_BYTE">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>INSERT_VIP</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.S1_AXI.INSERT_VIP">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
      </spirit:parameters>
      <spirit:vendorExtensions>
        <xilinx:busInterfaceInfo>
          <xilinx:enablement>
            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.S1_AXI" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
          </xilinx:enablement>
        </xilinx:busInterfaceInfo>
      </spirit:vendorExtensions>
    </spirit:busInterface>
    <spirit:busInterface>
      <spirit:name>C1_SYS_CLK</spirit:name>
      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="diff_clock" spirit:version="1.0"/>
      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="diff_clock_rtl" spirit:version="1.0"/>
      <spirit:slave/>
      <spirit:connectionRequired>true</spirit:connectionRequired>
      <spirit:portMaps>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>CLK_P</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c1_sys_clk_p</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>CLK_N</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c1_sys_clk_n</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
      </spirit:portMaps>
      <spirit:parameters>
        <spirit:parameter>
          <spirit:name>CAN_DEBUG</spirit:name>
          <spirit:value spirit:format="bool" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C1_SYS_CLK.CAN_DEBUG">false</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>FREQ_HZ</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C1_SYS_CLK.FREQ_HZ">100000000</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
      </spirit:parameters>
      <spirit:vendorExtensions>
        <xilinx:busInterfaceInfo>
          <xilinx:enablement>
            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.C1_SYS_CLK" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_SYSCLK_TYPE&apos;)) = &quot;DIFF&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_IS_CLK_SHARED&apos;)) = &quot;FALSE&quot; ">false</xilinx:isEnabled>
          </xilinx:enablement>
        </xilinx:busInterfaceInfo>
      </spirit:vendorExtensions>
    </spirit:busInterface>
    <spirit:busInterface>
      <spirit:name>C1_SYS_CLK_I</spirit:name>
      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
      <spirit:slave/>
      <spirit:connectionRequired>true</spirit:connectionRequired>
      <spirit:portMaps>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>CLK</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c1_sys_clk_i</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
      </spirit:portMaps>
      <spirit:parameters>
        <spirit:parameter>
          <spirit:name>FREQ_HZ</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C1_SYS_CLK_I.FREQ_HZ">100000000</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>PHASE</spirit:name>
          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C1_SYS_CLK_I.PHASE">0.000</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>CLK_DOMAIN</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C1_SYS_CLK_I.CLK_DOMAIN"/>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>ASSOCIATED_BUSIF</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C1_SYS_CLK_I.ASSOCIATED_BUSIF"/>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>ASSOCIATED_RESET</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C1_SYS_CLK_I.ASSOCIATED_RESET"/>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>INSERT_VIP</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.C1_SYS_CLK_I.INSERT_VIP">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
      </spirit:parameters>
      <spirit:vendorExtensions>
        <xilinx:busInterfaceInfo>
          <xilinx:enablement>
            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.C1_SYS_CLK_I" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_SYSCLK_TYPE&apos;)) != &quot;DIFF&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_IS_CLK_SHARED&apos;)) = &quot;FALSE&quot; ">false</xilinx:isEnabled>
          </xilinx:enablement>
        </xilinx:busInterfaceInfo>
      </spirit:vendorExtensions>
    </spirit:busInterface>
    <spirit:busInterface>
      <spirit:name>C1_ARESETN</spirit:name>
      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
      <spirit:slave/>
      <spirit:connectionRequired>true</spirit:connectionRequired>
      <spirit:portMaps>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>ARESETN</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c1_aresetn</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
      </spirit:portMaps>
      <spirit:parameters>
        <spirit:parameter>
          <spirit:name>POLARITY</spirit:name>
          <spirit:value spirit:id="BUSIFPARAM_VALUE.C1_ARESETN.POLARITY">ACTIVE_LOW</spirit:value>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>INSERT_VIP</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.C1_ARESETN.INSERT_VIP">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
      </spirit:parameters>
    </spirit:busInterface>
    <spirit:busInterface>
      <spirit:name>C2_DDR3</spirit:name>
      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="ddrx" spirit:version="1.0"/>
      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="ddrx_rtl" spirit:version="1.0"/>
      <spirit:master/>
      <spirit:connectionRequired>true</spirit:connectionRequired>
      <spirit:portMaps>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>DQ</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c2_ddr3_dq</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>DQS_P</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c2_ddr3_dqs_p</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>DQS_N</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c2_ddr3_dqs_n</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>ADDR</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c2_ddr3_addr</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>BA</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c2_ddr3_ba</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>RAS_N</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c2_ddr3_ras_n</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>CAS_N</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c2_ddr3_cas_n</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>WE_N</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c2_ddr3_we_n</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>RESET_N</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c2_ddr3_reset_n</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>CK_P</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c2_ddr3_ck_p</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>CK_N</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c2_ddr3_ck_n</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>CKE</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c2_ddr3_cke</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>CS_N</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c2_ddr3_cs_n</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>DM</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c2_ddr3_dm</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>ODT</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c2_ddr3_odt</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>PARITY</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c2_ddr3_parity</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
      </spirit:portMaps>
      <spirit:parameters>
        <spirit:parameter>
          <spirit:name>CAN_DEBUG</spirit:name>
          <spirit:value spirit:format="bool" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C2_DDR3.CAN_DEBUG">false</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>TIMEPERIOD_PS</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C2_DDR3.TIMEPERIOD_PS">1250</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>MEMORY_TYPE</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C2_DDR3.MEMORY_TYPE">COMPONENTS</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>MEMORY_PART</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C2_DDR3.MEMORY_PART"/>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>DATA_WIDTH</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C2_DDR3.DATA_WIDTH">8</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>CS_ENABLED</spirit:name>
          <spirit:value spirit:format="bool" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C2_DDR3.CS_ENABLED">true</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>DATA_MASK_ENABLED</spirit:name>
          <spirit:value spirit:format="bool" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C2_DDR3.DATA_MASK_ENABLED">true</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>SLOT</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C2_DDR3.SLOT">Single</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>CUSTOM_PARTS</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C2_DDR3.CUSTOM_PARTS"/>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>MEM_ADDR_MAP</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C2_DDR3.MEM_ADDR_MAP">ROW_COLUMN_BANK</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>BURST_LENGTH</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C2_DDR3.BURST_LENGTH">8</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>AXI_ARBITRATION_SCHEME</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C2_DDR3.AXI_ARBITRATION_SCHEME">TDM</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>CAS_LATENCY</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C2_DDR3.CAS_LATENCY">11</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>CAS_WRITE_LATENCY</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C2_DDR3.CAS_WRITE_LATENCY">11</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
      </spirit:parameters>
      <spirit:vendorExtensions>
        <xilinx:busInterfaceInfo>
          <xilinx:enablement>
            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.C2_DDR3" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;DDR3&quot; ">false</xilinx:isEnabled>
          </xilinx:enablement>
        </xilinx:busInterfaceInfo>
      </spirit:vendorExtensions>
    </spirit:busInterface>
    <spirit:busInterface>
      <spirit:name>C2_DDR2</spirit:name>
      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="ddrx" spirit:version="1.0"/>
      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="ddrx_rtl" spirit:version="1.0"/>
      <spirit:master/>
      <spirit:connectionRequired>true</spirit:connectionRequired>
      <spirit:portMaps>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>DQ</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c2_ddr2_dq</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>DQS_P</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c2_ddr2_dqs_p</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>DQS_N</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c2_ddr2_dqs_n</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>ADDR</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c2_ddr2_addr</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>BA</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c2_ddr2_ba</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>RAS_N</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c2_ddr2_ras_n</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>CAS_N</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c2_ddr2_cas_n</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>WE_N</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c2_ddr2_we_n</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>RESET_N</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c2_ddr2_reset_n</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>CK_P</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c2_ddr2_ck_p</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>CK_N</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c2_ddr2_ck_n</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>CKE</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c2_ddr2_cke</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>CS_N</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c2_ddr2_cs_n</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>DM</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c2_ddr2_dm</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>ODT</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c2_ddr2_odt</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>PARITY</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c2_ddr2_parity</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
      </spirit:portMaps>
      <spirit:parameters>
        <spirit:parameter>
          <spirit:name>CAN_DEBUG</spirit:name>
          <spirit:value spirit:format="bool" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C2_DDR2.CAN_DEBUG">false</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>TIMEPERIOD_PS</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C2_DDR2.TIMEPERIOD_PS">1250</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>MEMORY_TYPE</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C2_DDR2.MEMORY_TYPE">COMPONENTS</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>MEMORY_PART</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C2_DDR2.MEMORY_PART"/>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>DATA_WIDTH</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C2_DDR2.DATA_WIDTH">8</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>CS_ENABLED</spirit:name>
          <spirit:value spirit:format="bool" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C2_DDR2.CS_ENABLED">true</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>DATA_MASK_ENABLED</spirit:name>
          <spirit:value spirit:format="bool" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C2_DDR2.DATA_MASK_ENABLED">true</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>SLOT</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C2_DDR2.SLOT">Single</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>CUSTOM_PARTS</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C2_DDR2.CUSTOM_PARTS"/>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>MEM_ADDR_MAP</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C2_DDR2.MEM_ADDR_MAP">ROW_COLUMN_BANK</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>BURST_LENGTH</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C2_DDR2.BURST_LENGTH">8</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>AXI_ARBITRATION_SCHEME</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C2_DDR2.AXI_ARBITRATION_SCHEME">TDM</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>CAS_LATENCY</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C2_DDR2.CAS_LATENCY">11</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>CAS_WRITE_LATENCY</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C2_DDR2.CAS_WRITE_LATENCY">11</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
      </spirit:parameters>
      <spirit:vendorExtensions>
        <xilinx:busInterfaceInfo>
          <xilinx:enablement>
            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.C2_DDR2" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;DDR2&quot; ">false</xilinx:isEnabled>
          </xilinx:enablement>
        </xilinx:busInterfaceInfo>
      </spirit:vendorExtensions>
    </spirit:busInterface>
    <spirit:busInterface>
      <spirit:name>C2_RESET</spirit:name>
      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
      <spirit:master/>
      <spirit:connectionRequired>true</spirit:connectionRequired>
      <spirit:portMaps>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>RST</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c2_ui_clk_sync_rst</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
      </spirit:portMaps>
      <spirit:parameters>
        <spirit:parameter>
          <spirit:name>POLARITY</spirit:name>
          <spirit:value spirit:id="BUSIFPARAM_VALUE.C2_RESET.POLARITY">ACTIVE_HIGH</spirit:value>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>INSERT_VIP</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.C2_RESET.INSERT_VIP">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
      </spirit:parameters>
      <spirit:vendorExtensions>
        <xilinx:busInterfaceInfo>
          <xilinx:enablement>
            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.C2_RESET" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 ">false</xilinx:isEnabled>
          </xilinx:enablement>
        </xilinx:busInterfaceInfo>
      </spirit:vendorExtensions>
    </spirit:busInterface>
    <spirit:busInterface>
      <spirit:name>C2_DDR3_RESET</spirit:name>
      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
      <spirit:master/>
      <spirit:connectionRequired>true</spirit:connectionRequired>
      <spirit:portMaps>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>RST</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c2_ddr3_ui_clk_sync_rst</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
      </spirit:portMaps>
      <spirit:parameters>
        <spirit:parameter>
          <spirit:name>POLARITY</spirit:name>
          <spirit:value spirit:id="BUSIFPARAM_VALUE.C2_DDR3_RESET.POLARITY">ACTIVE_HIGH</spirit:value>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>INSERT_VIP</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.C2_DDR3_RESET.INSERT_VIP">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
      </spirit:parameters>
      <spirit:vendorExtensions>
        <xilinx:busInterfaceInfo>
          <xilinx:enablement>
            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.C2_DDR3_RESET" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 ">false</xilinx:isEnabled>
          </xilinx:enablement>
        </xilinx:busInterfaceInfo>
      </spirit:vendorExtensions>
    </spirit:busInterface>
    <spirit:busInterface>
      <spirit:name>C2_DDR2_RESET</spirit:name>
      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
      <spirit:master/>
      <spirit:connectionRequired>true</spirit:connectionRequired>
      <spirit:portMaps>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>RST</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c2_ddr2_ui_clk_sync_rst</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
      </spirit:portMaps>
      <spirit:parameters>
        <spirit:parameter>
          <spirit:name>POLARITY</spirit:name>
          <spirit:value spirit:id="BUSIFPARAM_VALUE.C2_DDR2_RESET.POLARITY">ACTIVE_HIGH</spirit:value>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>INSERT_VIP</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.C2_DDR2_RESET.INSERT_VIP">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
      </spirit:parameters>
      <spirit:vendorExtensions>
        <xilinx:busInterfaceInfo>
          <xilinx:enablement>
            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.C2_DDR2_RESET" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 ">false</xilinx:isEnabled>
          </xilinx:enablement>
        </xilinx:busInterfaceInfo>
      </spirit:vendorExtensions>
    </spirit:busInterface>
    <spirit:busInterface>
      <spirit:name>C2_LPDDR2_RESET</spirit:name>
      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
      <spirit:master/>
      <spirit:connectionRequired>true</spirit:connectionRequired>
      <spirit:portMaps>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>RST</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c2_lpddr2_ui_clk_sync_rst</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
      </spirit:portMaps>
      <spirit:parameters>
        <spirit:parameter>
          <spirit:name>POLARITY</spirit:name>
          <spirit:value spirit:id="BUSIFPARAM_VALUE.C2_LPDDR2_RESET.POLARITY">ACTIVE_HIGH</spirit:value>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>INSERT_VIP</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.C2_LPDDR2_RESET.INSERT_VIP">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
      </spirit:parameters>
      <spirit:vendorExtensions>
        <xilinx:busInterfaceInfo>
          <xilinx:enablement>
            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.C2_LPDDR2_RESET" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 ">false</xilinx:isEnabled>
          </xilinx:enablement>
        </xilinx:busInterfaceInfo>
      </spirit:vendorExtensions>
    </spirit:busInterface>
    <spirit:busInterface>
      <spirit:name>C2_QDRIIP_RESET</spirit:name>
      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
      <spirit:master/>
      <spirit:connectionRequired>true</spirit:connectionRequired>
      <spirit:portMaps>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>RST</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c2_qdriip_ui_clk_sync_rst</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
      </spirit:portMaps>
      <spirit:parameters>
        <spirit:parameter>
          <spirit:name>POLARITY</spirit:name>
          <spirit:value spirit:id="BUSIFPARAM_VALUE.C2_QDRIIP_RESET.POLARITY">ACTIVE_HIGH</spirit:value>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>INSERT_VIP</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.C2_QDRIIP_RESET.INSERT_VIP">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
      </spirit:parameters>
      <spirit:vendorExtensions>
        <xilinx:busInterfaceInfo>
          <xilinx:enablement>
            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.C2_QDRIIP_RESET" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 ">false</xilinx:isEnabled>
          </xilinx:enablement>
        </xilinx:busInterfaceInfo>
      </spirit:vendorExtensions>
    </spirit:busInterface>
    <spirit:busInterface>
      <spirit:name>C2_RLDII_RESET</spirit:name>
      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
      <spirit:master/>
      <spirit:connectionRequired>true</spirit:connectionRequired>
      <spirit:portMaps>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>RST</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c2_rldii_ui_clk_sync_rst</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
      </spirit:portMaps>
      <spirit:parameters>
        <spirit:parameter>
          <spirit:name>POLARITY</spirit:name>
          <spirit:value spirit:id="BUSIFPARAM_VALUE.C2_RLDII_RESET.POLARITY">ACTIVE_HIGH</spirit:value>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>INSERT_VIP</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.C2_RLDII_RESET.INSERT_VIP">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
      </spirit:parameters>
      <spirit:vendorExtensions>
        <xilinx:busInterfaceInfo>
          <xilinx:enablement>
            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.C2_RLDII_RESET" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 ">false</xilinx:isEnabled>
          </xilinx:enablement>
        </xilinx:busInterfaceInfo>
      </spirit:vendorExtensions>
    </spirit:busInterface>
    <spirit:busInterface>
      <spirit:name>C2_RLDIII_RESET</spirit:name>
      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
      <spirit:master/>
      <spirit:connectionRequired>true</spirit:connectionRequired>
      <spirit:portMaps>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>RST</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c2_rldiii_ui_clk_sync_rst</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
      </spirit:portMaps>
      <spirit:parameters>
        <spirit:parameter>
          <spirit:name>POLARITY</spirit:name>
          <spirit:value spirit:id="BUSIFPARAM_VALUE.C2_RLDIII_RESET.POLARITY">ACTIVE_HIGH</spirit:value>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>INSERT_VIP</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.C2_RLDIII_RESET.INSERT_VIP">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
      </spirit:parameters>
      <spirit:vendorExtensions>
        <xilinx:busInterfaceInfo>
          <xilinx:enablement>
            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.C2_RLDIII_RESET" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 ">false</xilinx:isEnabled>
          </xilinx:enablement>
        </xilinx:busInterfaceInfo>
      </spirit:vendorExtensions>
    </spirit:busInterface>
    <spirit:busInterface>
      <spirit:name>C2_CLOCK</spirit:name>
      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
      <spirit:master/>
      <spirit:connectionRequired>true</spirit:connectionRequired>
      <spirit:portMaps>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>CLK</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c2_ui_clk</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
      </spirit:portMaps>
      <spirit:parameters>
        <spirit:parameter>
          <spirit:name>FREQ_HZ</spirit:name>
          <spirit:value spirit:format="float" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.C2_CLOCK.FREQ_HZ" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C2_FREQ_HZ&apos;))">100</spirit:value>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>ASSOCIATED_BUSIF</spirit:name>
          <spirit:value spirit:id="BUSIFPARAM_VALUE.C2_CLOCK.ASSOCIATED_BUSIF">S2_AXI:S2_AXI_CTRL</spirit:value>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>ASSOCIATED_RESET</spirit:name>
          <spirit:value spirit:id="BUSIFPARAM_VALUE.C2_CLOCK.ASSOCIATED_RESET">c2_aresetn:c2_ui_clk_sync_rst</spirit:value>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>PHASE</spirit:name>
          <spirit:value spirit:format="float" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.C2_CLOCK.PHASE" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C2_PHASE&apos;))">0</spirit:value>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>CLK_DOMAIN</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C2_CLOCK.CLK_DOMAIN"/>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>INSERT_VIP</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.C2_CLOCK.INSERT_VIP">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
      </spirit:parameters>
      <spirit:vendorExtensions>
        <xilinx:busInterfaceInfo>
          <xilinx:enablement>
            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.C2_CLOCK" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 ">false</xilinx:isEnabled>
          </xilinx:enablement>
        </xilinx:busInterfaceInfo>
      </spirit:vendorExtensions>
    </spirit:busInterface>
    <spirit:busInterface>
      <spirit:name>C2_MMCM_CLKOUT0</spirit:name>
      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
      <spirit:master/>
      <spirit:connectionRequired>true</spirit:connectionRequired>
      <spirit:portMaps>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>CLK</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c2_ui_addn_clk_0</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
      </spirit:portMaps>
      <spirit:parameters>
        <spirit:parameter>
          <spirit:name>FREQ_HZ</spirit:name>
          <spirit:value spirit:format="float" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.C2_MMCM_CLKOUT0.FREQ_HZ" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MMCM_CLKOUT0_FREQ&apos;))">10</spirit:value>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>ASSOCIATED_ASYNC_RESET</spirit:name>
          <spirit:value spirit:id="BUSIFPARAM_VALUE.C2_MMCM_CLKOUT0.ASSOCIATED_ASYNC_RESET">c2_aresetn</spirit:value>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>PHASE</spirit:name>
          <spirit:value spirit:format="float" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.C2_MMCM_CLKOUT0.PHASE" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C2_PHASE&apos;))">0</spirit:value>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>CLK_DOMAIN</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C2_MMCM_CLKOUT0.CLK_DOMAIN"/>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>ASSOCIATED_BUSIF</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C2_MMCM_CLKOUT0.ASSOCIATED_BUSIF"/>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>ASSOCIATED_RESET</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C2_MMCM_CLKOUT0.ASSOCIATED_RESET"/>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>INSERT_VIP</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.C2_MMCM_CLKOUT0.INSERT_VIP">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
      </spirit:parameters>
      <spirit:vendorExtensions>
        <xilinx:busInterfaceInfo>
          <xilinx:enablement>
            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.C2_MMCM_CLKOUT0" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 ">false</xilinx:isEnabled>
          </xilinx:enablement>
        </xilinx:busInterfaceInfo>
      </spirit:vendorExtensions>
    </spirit:busInterface>
    <spirit:busInterface>
      <spirit:name>C2_MMCM_CLKOUT1</spirit:name>
      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
      <spirit:master/>
      <spirit:connectionRequired>true</spirit:connectionRequired>
      <spirit:portMaps>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>CLK</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c2_ui_addn_clk_1</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
      </spirit:portMaps>
      <spirit:parameters>
        <spirit:parameter>
          <spirit:name>FREQ_HZ</spirit:name>
          <spirit:value spirit:format="float" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.C2_MMCM_CLKOUT1.FREQ_HZ" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MMCM_CLKOUT1_FREQ&apos;))">10</spirit:value>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>ASSOCIATED_ASYNC_RESET</spirit:name>
          <spirit:value spirit:id="BUSIFPARAM_VALUE.C2_MMCM_CLKOUT1.ASSOCIATED_ASYNC_RESET">c2_aresetn</spirit:value>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>PHASE</spirit:name>
          <spirit:value spirit:format="float" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.C2_MMCM_CLKOUT1.PHASE" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C2_PHASE&apos;))">0</spirit:value>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>CLK_DOMAIN</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C2_MMCM_CLKOUT1.CLK_DOMAIN"/>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>ASSOCIATED_BUSIF</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C2_MMCM_CLKOUT1.ASSOCIATED_BUSIF"/>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>ASSOCIATED_RESET</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C2_MMCM_CLKOUT1.ASSOCIATED_RESET"/>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>INSERT_VIP</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.C2_MMCM_CLKOUT1.INSERT_VIP">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
      </spirit:parameters>
      <spirit:vendorExtensions>
        <xilinx:busInterfaceInfo>
          <xilinx:enablement>
            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.C2_MMCM_CLKOUT1" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 ">false</xilinx:isEnabled>
          </xilinx:enablement>
        </xilinx:busInterfaceInfo>
      </spirit:vendorExtensions>
    </spirit:busInterface>
    <spirit:busInterface>
      <spirit:name>C2_MMCM_CLKOUT2</spirit:name>
      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
      <spirit:master/>
      <spirit:connectionRequired>true</spirit:connectionRequired>
      <spirit:portMaps>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>CLK</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c2_ui_addn_clk_2</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
      </spirit:portMaps>
      <spirit:parameters>
        <spirit:parameter>
          <spirit:name>FREQ_HZ</spirit:name>
          <spirit:value spirit:format="float" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.C2_MMCM_CLKOUT2.FREQ_HZ" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MMCM_CLKOUT2_FREQ&apos;))">10</spirit:value>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>ASSOCIATED_ASYNC_RESET</spirit:name>
          <spirit:value spirit:id="BUSIFPARAM_VALUE.C2_MMCM_CLKOUT2.ASSOCIATED_ASYNC_RESET">c2_aresetn</spirit:value>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>PHASE</spirit:name>
          <spirit:value spirit:format="float" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.C2_MMCM_CLKOUT2.PHASE" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C2_PHASE&apos;))">0</spirit:value>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>CLK_DOMAIN</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C2_MMCM_CLKOUT2.CLK_DOMAIN"/>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>ASSOCIATED_BUSIF</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C2_MMCM_CLKOUT2.ASSOCIATED_BUSIF"/>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>ASSOCIATED_RESET</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C2_MMCM_CLKOUT2.ASSOCIATED_RESET"/>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>INSERT_VIP</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.C2_MMCM_CLKOUT2.INSERT_VIP">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
      </spirit:parameters>
      <spirit:vendorExtensions>
        <xilinx:busInterfaceInfo>
          <xilinx:enablement>
            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.C2_MMCM_CLKOUT2" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 ">false</xilinx:isEnabled>
          </xilinx:enablement>
        </xilinx:busInterfaceInfo>
      </spirit:vendorExtensions>
    </spirit:busInterface>
    <spirit:busInterface>
      <spirit:name>C2_MMCM_CLKOUT3</spirit:name>
      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
      <spirit:master/>
      <spirit:connectionRequired>true</spirit:connectionRequired>
      <spirit:portMaps>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>CLK</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c2_ui_addn_clk_3</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
      </spirit:portMaps>
      <spirit:parameters>
        <spirit:parameter>
          <spirit:name>FREQ_HZ</spirit:name>
          <spirit:value spirit:format="float" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.C2_MMCM_CLKOUT3.FREQ_HZ" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MMCM_CLKOUT3_FREQ&apos;))">10</spirit:value>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>ASSOCIATED_ASYNC_RESET</spirit:name>
          <spirit:value spirit:id="BUSIFPARAM_VALUE.C2_MMCM_CLKOUT3.ASSOCIATED_ASYNC_RESET">c2_aresetn</spirit:value>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>PHASE</spirit:name>
          <spirit:value spirit:format="float" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.C2_MMCM_CLKOUT3.PHASE" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C2_PHASE&apos;))">0</spirit:value>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>CLK_DOMAIN</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C2_MMCM_CLKOUT3.CLK_DOMAIN"/>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>ASSOCIATED_BUSIF</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C2_MMCM_CLKOUT3.ASSOCIATED_BUSIF"/>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>ASSOCIATED_RESET</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C2_MMCM_CLKOUT3.ASSOCIATED_RESET"/>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>INSERT_VIP</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.C2_MMCM_CLKOUT3.INSERT_VIP">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
      </spirit:parameters>
      <spirit:vendorExtensions>
        <xilinx:busInterfaceInfo>
          <xilinx:enablement>
            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.C2_MMCM_CLKOUT3" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 ">false</xilinx:isEnabled>
          </xilinx:enablement>
        </xilinx:busInterfaceInfo>
      </spirit:vendorExtensions>
    </spirit:busInterface>
    <spirit:busInterface>
      <spirit:name>C2_MMCM_CLKOUT4</spirit:name>
      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
      <spirit:master/>
      <spirit:connectionRequired>true</spirit:connectionRequired>
      <spirit:portMaps>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>CLK</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c2_ui_addn_clk_4</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
      </spirit:portMaps>
      <spirit:parameters>
        <spirit:parameter>
          <spirit:name>FREQ_HZ</spirit:name>
          <spirit:value spirit:format="float" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.C2_MMCM_CLKOUT4.FREQ_HZ" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MMCM_CLKOUT4_FREQ&apos;))">10</spirit:value>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>ASSOCIATED_ASYNC_RESET</spirit:name>
          <spirit:value spirit:id="BUSIFPARAM_VALUE.C2_MMCM_CLKOUT4.ASSOCIATED_ASYNC_RESET">c2_aresetn</spirit:value>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>PHASE</spirit:name>
          <spirit:value spirit:format="float" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.C2_MMCM_CLKOUT4.PHASE" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C2_PHASE&apos;))">0</spirit:value>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>CLK_DOMAIN</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C2_MMCM_CLKOUT4.CLK_DOMAIN"/>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>ASSOCIATED_BUSIF</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C2_MMCM_CLKOUT4.ASSOCIATED_BUSIF"/>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>ASSOCIATED_RESET</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C2_MMCM_CLKOUT4.ASSOCIATED_RESET"/>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>INSERT_VIP</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.C2_MMCM_CLKOUT4.INSERT_VIP">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
      </spirit:parameters>
      <spirit:vendorExtensions>
        <xilinx:busInterfaceInfo>
          <xilinx:enablement>
            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.C2_MMCM_CLKOUT4" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 ">false</xilinx:isEnabled>
          </xilinx:enablement>
        </xilinx:busInterfaceInfo>
      </spirit:vendorExtensions>
    </spirit:busInterface>
    <spirit:busInterface>
      <spirit:name>S2_AXI_CTRL</spirit:name>
      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm" spirit:version="1.0"/>
      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm_rtl" spirit:version="1.0"/>
      <spirit:slave>
        <spirit:memoryMapRef spirit:memoryMapRef="c2_s_axi_ctrl_memmap"/>
      </spirit:slave>
      <spirit:connectionRequired>true</spirit:connectionRequired>
      <spirit:portMaps>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>AWVALID</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c2_s_axi_ctrl_awvalid</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>AWREADY</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c2_s_axi_ctrl_awready</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>AWADDR</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c2_s_axi_ctrl_awaddr</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>WVALID</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c2_s_axi_ctrl_wvalid</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>WREADY</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c2_s_axi_ctrl_wready</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>WDATA</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c2_s_axi_ctrl_wdata</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>BVALID</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c2_s_axi_ctrl_bvalid</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>BREADY</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c2_s_axi_ctrl_bready</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>BRESP</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c2_s_axi_ctrl_bresp</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>ARVALID</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c2_s_axi_ctrl_arvalid</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>ARREADY</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c2_s_axi_ctrl_arready</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>ARADDR</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c2_s_axi_ctrl_araddr</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>RVALID</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c2_s_axi_ctrl_rvalid</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>RREADY</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c2_s_axi_ctrl_rready</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>RDATA</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c2_s_axi_ctrl_rdata</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>RRESP</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c2_s_axi_ctrl_rresp</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
      </spirit:portMaps>
      <spirit:parameters>
        <spirit:parameter>
          <spirit:name>FREQ_HZ</spirit:name>
          <spirit:value spirit:format="float" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.S2_AXI_CTRL.FREQ_HZ" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C2_FREQ_HZ&apos;))">100</spirit:value>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>DATA_WIDTH</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S2_AXI_CTRL.DATA_WIDTH">1</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>PROTOCOL</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S2_AXI_CTRL.PROTOCOL">AXI4LITE</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>ID_WIDTH</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S2_AXI_CTRL.ID_WIDTH">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>ADDR_WIDTH</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S2_AXI_CTRL.ADDR_WIDTH">1</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>AWUSER_WIDTH</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S2_AXI_CTRL.AWUSER_WIDTH">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>ARUSER_WIDTH</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S2_AXI_CTRL.ARUSER_WIDTH">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>WUSER_WIDTH</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S2_AXI_CTRL.WUSER_WIDTH">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>RUSER_WIDTH</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S2_AXI_CTRL.RUSER_WIDTH">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>BUSER_WIDTH</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S2_AXI_CTRL.BUSER_WIDTH">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>READ_WRITE_MODE</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S2_AXI_CTRL.READ_WRITE_MODE">READ_WRITE</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>HAS_BURST</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S2_AXI_CTRL.HAS_BURST">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>HAS_LOCK</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S2_AXI_CTRL.HAS_LOCK">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>HAS_PROT</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S2_AXI_CTRL.HAS_PROT">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>HAS_CACHE</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S2_AXI_CTRL.HAS_CACHE">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>HAS_QOS</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S2_AXI_CTRL.HAS_QOS">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>HAS_REGION</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S2_AXI_CTRL.HAS_REGION">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>HAS_WSTRB</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S2_AXI_CTRL.HAS_WSTRB">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>HAS_BRESP</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S2_AXI_CTRL.HAS_BRESP">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>HAS_RRESP</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S2_AXI_CTRL.HAS_RRESP">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>SUPPORTS_NARROW_BURST</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S2_AXI_CTRL.SUPPORTS_NARROW_BURST">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>NUM_READ_OUTSTANDING</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S2_AXI_CTRL.NUM_READ_OUTSTANDING">1</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>NUM_WRITE_OUTSTANDING</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S2_AXI_CTRL.NUM_WRITE_OUTSTANDING">1</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>MAX_BURST_LENGTH</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S2_AXI_CTRL.MAX_BURST_LENGTH">1</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>PHASE</spirit:name>
          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S2_AXI_CTRL.PHASE">0.000</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>CLK_DOMAIN</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S2_AXI_CTRL.CLK_DOMAIN"/>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>NUM_READ_THREADS</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S2_AXI_CTRL.NUM_READ_THREADS">1</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>NUM_WRITE_THREADS</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S2_AXI_CTRL.NUM_WRITE_THREADS">1</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>RUSER_BITS_PER_BYTE</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S2_AXI_CTRL.RUSER_BITS_PER_BYTE">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>WUSER_BITS_PER_BYTE</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S2_AXI_CTRL.WUSER_BITS_PER_BYTE">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>INSERT_VIP</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.S2_AXI_CTRL.INSERT_VIP">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
      </spirit:parameters>
      <spirit:vendorExtensions>
        <xilinx:busInterfaceInfo>
          <xilinx:enablement>
            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.S2_AXI_CTRL" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_USE_AXI&apos;)) = 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_ECC&apos;)) = &quot;ON&quot; ) ">false</xilinx:isEnabled>
          </xilinx:enablement>
        </xilinx:busInterfaceInfo>
      </spirit:vendorExtensions>
    </spirit:busInterface>
    <spirit:busInterface>
      <spirit:name>S2_AXI</spirit:name>
      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm" spirit:version="1.0"/>
      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm_rtl" spirit:version="1.0"/>
      <spirit:slave>
        <spirit:memoryMapRef spirit:memoryMapRef="c2_memmap"/>
      </spirit:slave>
      <spirit:connectionRequired>true</spirit:connectionRequired>
      <spirit:portMaps>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>AWID</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c2_s_axi_awid</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>AWADDR</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c2_s_axi_awaddr</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>AWLEN</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c2_s_axi_awlen</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>AWSIZE</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c2_s_axi_awsize</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>AWBURST</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c2_s_axi_awburst</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>AWLOCK</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c2_s_axi_awlock</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>AWCACHE</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c2_s_axi_awcache</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>AWPROT</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c2_s_axi_awprot</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>AWQOS</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c2_s_axi_awqos</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>AWVALID</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c2_s_axi_awvalid</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>AWREADY</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c2_s_axi_awready</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>WDATA</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c2_s_axi_wdata</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>WSTRB</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c2_s_axi_wstrb</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>WLAST</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c2_s_axi_wlast</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>WVALID</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c2_s_axi_wvalid</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>WREADY</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c2_s_axi_wready</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>BREADY</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c2_s_axi_bready</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>BID</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c2_s_axi_bid</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>BRESP</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c2_s_axi_bresp</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>BVALID</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c2_s_axi_bvalid</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>ARID</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c2_s_axi_arid</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>ARADDR</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c2_s_axi_araddr</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>ARLEN</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c2_s_axi_arlen</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>ARSIZE</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c2_s_axi_arsize</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>ARBURST</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c2_s_axi_arburst</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>ARLOCK</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c2_s_axi_arlock</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>ARCACHE</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c2_s_axi_arcache</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>ARPROT</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c2_s_axi_arprot</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>ARQOS</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c2_s_axi_arqos</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>ARVALID</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c2_s_axi_arvalid</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>ARREADY</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c2_s_axi_arready</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>RREADY</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c2_s_axi_rready</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>RID</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c2_s_axi_rid</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>RDATA</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c2_s_axi_rdata</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>RRESP</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c2_s_axi_rresp</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>RLAST</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c2_s_axi_rlast</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>RVALID</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c2_s_axi_rvalid</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
      </spirit:portMaps>
      <spirit:parameters>
        <spirit:parameter>
          <spirit:name>FREQ_HZ</spirit:name>
          <spirit:value spirit:format="float" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.S2_AXI.FREQ_HZ" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C2_FREQ_HZ&apos;))">100</spirit:value>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>DATA_WIDTH</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S2_AXI.DATA_WIDTH">1</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>PROTOCOL</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S2_AXI.PROTOCOL">AXI4LITE</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>ID_WIDTH</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S2_AXI.ID_WIDTH">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>ADDR_WIDTH</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S2_AXI.ADDR_WIDTH">1</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>AWUSER_WIDTH</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S2_AXI.AWUSER_WIDTH">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>ARUSER_WIDTH</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S2_AXI.ARUSER_WIDTH">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>WUSER_WIDTH</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S2_AXI.WUSER_WIDTH">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>RUSER_WIDTH</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S2_AXI.RUSER_WIDTH">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>BUSER_WIDTH</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S2_AXI.BUSER_WIDTH">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>READ_WRITE_MODE</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S2_AXI.READ_WRITE_MODE">READ_WRITE</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>HAS_BURST</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S2_AXI.HAS_BURST">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>HAS_LOCK</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S2_AXI.HAS_LOCK">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>HAS_PROT</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S2_AXI.HAS_PROT">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>HAS_CACHE</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S2_AXI.HAS_CACHE">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>HAS_QOS</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S2_AXI.HAS_QOS">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>HAS_REGION</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S2_AXI.HAS_REGION">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>HAS_WSTRB</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S2_AXI.HAS_WSTRB">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>HAS_BRESP</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S2_AXI.HAS_BRESP">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>HAS_RRESP</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S2_AXI.HAS_RRESP">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>SUPPORTS_NARROW_BURST</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S2_AXI.SUPPORTS_NARROW_BURST">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>NUM_READ_OUTSTANDING</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S2_AXI.NUM_READ_OUTSTANDING">1</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>NUM_WRITE_OUTSTANDING</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S2_AXI.NUM_WRITE_OUTSTANDING">1</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>MAX_BURST_LENGTH</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S2_AXI.MAX_BURST_LENGTH">1</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>PHASE</spirit:name>
          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S2_AXI.PHASE">0.000</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>CLK_DOMAIN</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S2_AXI.CLK_DOMAIN"/>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>NUM_READ_THREADS</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S2_AXI.NUM_READ_THREADS">1</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>NUM_WRITE_THREADS</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S2_AXI.NUM_WRITE_THREADS">1</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>RUSER_BITS_PER_BYTE</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S2_AXI.RUSER_BITS_PER_BYTE">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>WUSER_BITS_PER_BYTE</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S2_AXI.WUSER_BITS_PER_BYTE">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>INSERT_VIP</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.S2_AXI.INSERT_VIP">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
      </spirit:parameters>
      <spirit:vendorExtensions>
        <xilinx:busInterfaceInfo>
          <xilinx:enablement>
            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.S2_AXI" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
          </xilinx:enablement>
        </xilinx:busInterfaceInfo>
      </spirit:vendorExtensions>
    </spirit:busInterface>
    <spirit:busInterface>
      <spirit:name>C2_SYS_CLK</spirit:name>
      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="diff_clock" spirit:version="1.0"/>
      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="diff_clock_rtl" spirit:version="1.0"/>
      <spirit:slave/>
      <spirit:connectionRequired>true</spirit:connectionRequired>
      <spirit:portMaps>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>CLK_P</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c2_sys_clk_p</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>CLK_N</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c2_sys_clk_n</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
      </spirit:portMaps>
      <spirit:parameters>
        <spirit:parameter>
          <spirit:name>CAN_DEBUG</spirit:name>
          <spirit:value spirit:format="bool" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C2_SYS_CLK.CAN_DEBUG">false</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>FREQ_HZ</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C2_SYS_CLK.FREQ_HZ">100000000</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
      </spirit:parameters>
      <spirit:vendorExtensions>
        <xilinx:busInterfaceInfo>
          <xilinx:enablement>
            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.C2_SYS_CLK" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_SYSCLK_TYPE&apos;)) = &quot;DIFF&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_IS_CLK_SHARED&apos;)) = &quot;FALSE&quot; ">false</xilinx:isEnabled>
          </xilinx:enablement>
        </xilinx:busInterfaceInfo>
      </spirit:vendorExtensions>
    </spirit:busInterface>
    <spirit:busInterface>
      <spirit:name>C2_SYS_CLK_I</spirit:name>
      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
      <spirit:slave/>
      <spirit:connectionRequired>true</spirit:connectionRequired>
      <spirit:portMaps>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>CLK</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c2_sys_clk_i</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
      </spirit:portMaps>
      <spirit:parameters>
        <spirit:parameter>
          <spirit:name>FREQ_HZ</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C2_SYS_CLK_I.FREQ_HZ">100000000</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>PHASE</spirit:name>
          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C2_SYS_CLK_I.PHASE">0.000</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>CLK_DOMAIN</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C2_SYS_CLK_I.CLK_DOMAIN"/>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>ASSOCIATED_BUSIF</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C2_SYS_CLK_I.ASSOCIATED_BUSIF"/>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>ASSOCIATED_RESET</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C2_SYS_CLK_I.ASSOCIATED_RESET"/>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>INSERT_VIP</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.C2_SYS_CLK_I.INSERT_VIP">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
      </spirit:parameters>
      <spirit:vendorExtensions>
        <xilinx:busInterfaceInfo>
          <xilinx:enablement>
            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.C2_SYS_CLK_I" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_SYSCLK_TYPE&apos;)) != &quot;DIFF&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_IS_CLK_SHARED&apos;)) = &quot;FALSE&quot; ">false</xilinx:isEnabled>
          </xilinx:enablement>
        </xilinx:busInterfaceInfo>
      </spirit:vendorExtensions>
    </spirit:busInterface>
    <spirit:busInterface>
      <spirit:name>C2_ARESETN</spirit:name>
      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
      <spirit:slave/>
      <spirit:connectionRequired>true</spirit:connectionRequired>
      <spirit:portMaps>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>ARESETN</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c2_aresetn</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
      </spirit:portMaps>
      <spirit:parameters>
        <spirit:parameter>
          <spirit:name>POLARITY</spirit:name>
          <spirit:value spirit:id="BUSIFPARAM_VALUE.C2_ARESETN.POLARITY">ACTIVE_LOW</spirit:value>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>INSERT_VIP</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.C2_ARESETN.INSERT_VIP">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
      </spirit:parameters>
    </spirit:busInterface>
    <spirit:busInterface>
      <spirit:name>C3_DDR3</spirit:name>
      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="ddrx" spirit:version="1.0"/>
      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="ddrx_rtl" spirit:version="1.0"/>
      <spirit:master/>
      <spirit:connectionRequired>true</spirit:connectionRequired>
      <spirit:portMaps>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>DQ</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c3_ddr3_dq</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>DQS_P</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c3_ddr3_dqs_p</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>DQS_N</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c3_ddr3_dqs_n</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>ADDR</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c3_ddr3_addr</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>BA</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c3_ddr3_ba</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>RAS_N</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c3_ddr3_ras_n</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>CAS_N</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c3_ddr3_cas_n</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>WE_N</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c3_ddr3_we_n</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>RESET_N</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c3_ddr3_reset_n</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>CK_P</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c3_ddr3_ck_p</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>CK_N</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c3_ddr3_ck_n</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>CKE</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c3_ddr3_cke</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>CS_N</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c3_ddr3_cs_n</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>DM</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c3_ddr3_dm</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>ODT</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c3_ddr3_odt</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>PARITY</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c3_ddr3_parity</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
      </spirit:portMaps>
      <spirit:parameters>
        <spirit:parameter>
          <spirit:name>CAN_DEBUG</spirit:name>
          <spirit:value spirit:format="bool" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C3_DDR3.CAN_DEBUG">false</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>TIMEPERIOD_PS</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C3_DDR3.TIMEPERIOD_PS">1250</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>MEMORY_TYPE</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C3_DDR3.MEMORY_TYPE">COMPONENTS</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>MEMORY_PART</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C3_DDR3.MEMORY_PART"/>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>DATA_WIDTH</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C3_DDR3.DATA_WIDTH">8</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>CS_ENABLED</spirit:name>
          <spirit:value spirit:format="bool" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C3_DDR3.CS_ENABLED">true</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>DATA_MASK_ENABLED</spirit:name>
          <spirit:value spirit:format="bool" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C3_DDR3.DATA_MASK_ENABLED">true</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>SLOT</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C3_DDR3.SLOT">Single</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>CUSTOM_PARTS</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C3_DDR3.CUSTOM_PARTS"/>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>MEM_ADDR_MAP</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C3_DDR3.MEM_ADDR_MAP">ROW_COLUMN_BANK</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>BURST_LENGTH</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C3_DDR3.BURST_LENGTH">8</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>AXI_ARBITRATION_SCHEME</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C3_DDR3.AXI_ARBITRATION_SCHEME">TDM</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>CAS_LATENCY</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C3_DDR3.CAS_LATENCY">11</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>CAS_WRITE_LATENCY</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C3_DDR3.CAS_WRITE_LATENCY">11</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
      </spirit:parameters>
      <spirit:vendorExtensions>
        <xilinx:busInterfaceInfo>
          <xilinx:enablement>
            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.C3_DDR3" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;DDR3&quot; ">false</xilinx:isEnabled>
          </xilinx:enablement>
        </xilinx:busInterfaceInfo>
      </spirit:vendorExtensions>
    </spirit:busInterface>
    <spirit:busInterface>
      <spirit:name>C3_DDR2</spirit:name>
      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="ddrx" spirit:version="1.0"/>
      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="ddrx_rtl" spirit:version="1.0"/>
      <spirit:master/>
      <spirit:connectionRequired>true</spirit:connectionRequired>
      <spirit:portMaps>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>DQ</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c3_ddr2_dq</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>DQS_P</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c3_ddr2_dqs_p</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>DQS_N</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c3_ddr2_dqs_n</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>ADDR</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c3_ddr2_addr</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>BA</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c3_ddr2_ba</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>RAS_N</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c3_ddr2_ras_n</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>CAS_N</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c3_ddr2_cas_n</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>WE_N</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c3_ddr2_we_n</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>RESET_N</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c3_ddr2_reset_n</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>CK_P</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c3_ddr2_ck_p</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>CK_N</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c3_ddr2_ck_n</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>CKE</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c3_ddr2_cke</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>CS_N</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c3_ddr2_cs_n</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>DM</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c3_ddr2_dm</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>ODT</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c3_ddr2_odt</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>PARITY</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c3_ddr2_parity</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
      </spirit:portMaps>
      <spirit:parameters>
        <spirit:parameter>
          <spirit:name>CAN_DEBUG</spirit:name>
          <spirit:value spirit:format="bool" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C3_DDR2.CAN_DEBUG">false</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>TIMEPERIOD_PS</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C3_DDR2.TIMEPERIOD_PS">1250</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>MEMORY_TYPE</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C3_DDR2.MEMORY_TYPE">COMPONENTS</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>MEMORY_PART</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C3_DDR2.MEMORY_PART"/>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>DATA_WIDTH</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C3_DDR2.DATA_WIDTH">8</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>CS_ENABLED</spirit:name>
          <spirit:value spirit:format="bool" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C3_DDR2.CS_ENABLED">true</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>DATA_MASK_ENABLED</spirit:name>
          <spirit:value spirit:format="bool" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C3_DDR2.DATA_MASK_ENABLED">true</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>SLOT</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C3_DDR2.SLOT">Single</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>CUSTOM_PARTS</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C3_DDR2.CUSTOM_PARTS"/>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>MEM_ADDR_MAP</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C3_DDR2.MEM_ADDR_MAP">ROW_COLUMN_BANK</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>BURST_LENGTH</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C3_DDR2.BURST_LENGTH">8</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>AXI_ARBITRATION_SCHEME</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C3_DDR2.AXI_ARBITRATION_SCHEME">TDM</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>CAS_LATENCY</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C3_DDR2.CAS_LATENCY">11</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>CAS_WRITE_LATENCY</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C3_DDR2.CAS_WRITE_LATENCY">11</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
      </spirit:parameters>
      <spirit:vendorExtensions>
        <xilinx:busInterfaceInfo>
          <xilinx:enablement>
            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.C3_DDR2" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;DDR2&quot; ">false</xilinx:isEnabled>
          </xilinx:enablement>
        </xilinx:busInterfaceInfo>
      </spirit:vendorExtensions>
    </spirit:busInterface>
    <spirit:busInterface>
      <spirit:name>C3_RESET</spirit:name>
      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
      <spirit:master/>
      <spirit:connectionRequired>true</spirit:connectionRequired>
      <spirit:portMaps>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>RST</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c3_ui_clk_sync_rst</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
      </spirit:portMaps>
      <spirit:parameters>
        <spirit:parameter>
          <spirit:name>POLARITY</spirit:name>
          <spirit:value spirit:id="BUSIFPARAM_VALUE.C3_RESET.POLARITY">ACTIVE_HIGH</spirit:value>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>INSERT_VIP</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.C3_RESET.INSERT_VIP">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
      </spirit:parameters>
      <spirit:vendorExtensions>
        <xilinx:busInterfaceInfo>
          <xilinx:enablement>
            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.C3_RESET" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 ">false</xilinx:isEnabled>
          </xilinx:enablement>
        </xilinx:busInterfaceInfo>
      </spirit:vendorExtensions>
    </spirit:busInterface>
    <spirit:busInterface>
      <spirit:name>C3_DDR3_RESET</spirit:name>
      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
      <spirit:master/>
      <spirit:connectionRequired>true</spirit:connectionRequired>
      <spirit:portMaps>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>RST</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c3_ddr3_ui_clk_sync_rst</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
      </spirit:portMaps>
      <spirit:parameters>
        <spirit:parameter>
          <spirit:name>POLARITY</spirit:name>
          <spirit:value spirit:id="BUSIFPARAM_VALUE.C3_DDR3_RESET.POLARITY">ACTIVE_HIGH</spirit:value>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>INSERT_VIP</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.C3_DDR3_RESET.INSERT_VIP">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
      </spirit:parameters>
      <spirit:vendorExtensions>
        <xilinx:busInterfaceInfo>
          <xilinx:enablement>
            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.C3_DDR3_RESET" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 ">false</xilinx:isEnabled>
          </xilinx:enablement>
        </xilinx:busInterfaceInfo>
      </spirit:vendorExtensions>
    </spirit:busInterface>
    <spirit:busInterface>
      <spirit:name>C3_DDR2_RESET</spirit:name>
      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
      <spirit:master/>
      <spirit:connectionRequired>true</spirit:connectionRequired>
      <spirit:portMaps>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>RST</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c3_ddr2_ui_clk_sync_rst</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
      </spirit:portMaps>
      <spirit:parameters>
        <spirit:parameter>
          <spirit:name>POLARITY</spirit:name>
          <spirit:value spirit:id="BUSIFPARAM_VALUE.C3_DDR2_RESET.POLARITY">ACTIVE_HIGH</spirit:value>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>INSERT_VIP</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.C3_DDR2_RESET.INSERT_VIP">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
      </spirit:parameters>
      <spirit:vendorExtensions>
        <xilinx:busInterfaceInfo>
          <xilinx:enablement>
            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.C3_DDR2_RESET" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 ">false</xilinx:isEnabled>
          </xilinx:enablement>
        </xilinx:busInterfaceInfo>
      </spirit:vendorExtensions>
    </spirit:busInterface>
    <spirit:busInterface>
      <spirit:name>C3_LPDDR2_RESET</spirit:name>
      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
      <spirit:master/>
      <spirit:connectionRequired>true</spirit:connectionRequired>
      <spirit:portMaps>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>RST</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c3_lpddr2_ui_clk_sync_rst</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
      </spirit:portMaps>
      <spirit:parameters>
        <spirit:parameter>
          <spirit:name>POLARITY</spirit:name>
          <spirit:value spirit:id="BUSIFPARAM_VALUE.C3_LPDDR2_RESET.POLARITY">ACTIVE_HIGH</spirit:value>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>INSERT_VIP</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.C3_LPDDR2_RESET.INSERT_VIP">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
      </spirit:parameters>
      <spirit:vendorExtensions>
        <xilinx:busInterfaceInfo>
          <xilinx:enablement>
            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.C3_LPDDR2_RESET" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 ">false</xilinx:isEnabled>
          </xilinx:enablement>
        </xilinx:busInterfaceInfo>
      </spirit:vendorExtensions>
    </spirit:busInterface>
    <spirit:busInterface>
      <spirit:name>C3_QDRIIP_RESET</spirit:name>
      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
      <spirit:master/>
      <spirit:connectionRequired>true</spirit:connectionRequired>
      <spirit:portMaps>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>RST</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c3_qdriip_ui_clk_sync_rst</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
      </spirit:portMaps>
      <spirit:parameters>
        <spirit:parameter>
          <spirit:name>POLARITY</spirit:name>
          <spirit:value spirit:id="BUSIFPARAM_VALUE.C3_QDRIIP_RESET.POLARITY">ACTIVE_HIGH</spirit:value>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>INSERT_VIP</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.C3_QDRIIP_RESET.INSERT_VIP">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
      </spirit:parameters>
      <spirit:vendorExtensions>
        <xilinx:busInterfaceInfo>
          <xilinx:enablement>
            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.C3_QDRIIP_RESET" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 ">false</xilinx:isEnabled>
          </xilinx:enablement>
        </xilinx:busInterfaceInfo>
      </spirit:vendorExtensions>
    </spirit:busInterface>
    <spirit:busInterface>
      <spirit:name>C3_RLDII_RESET</spirit:name>
      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
      <spirit:master/>
      <spirit:connectionRequired>true</spirit:connectionRequired>
      <spirit:portMaps>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>RST</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c3_rldii_ui_clk_sync_rst</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
      </spirit:portMaps>
      <spirit:parameters>
        <spirit:parameter>
          <spirit:name>POLARITY</spirit:name>
          <spirit:value spirit:id="BUSIFPARAM_VALUE.C3_RLDII_RESET.POLARITY">ACTIVE_HIGH</spirit:value>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>INSERT_VIP</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.C3_RLDII_RESET.INSERT_VIP">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
      </spirit:parameters>
      <spirit:vendorExtensions>
        <xilinx:busInterfaceInfo>
          <xilinx:enablement>
            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.C3_RLDII_RESET" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 ">false</xilinx:isEnabled>
          </xilinx:enablement>
        </xilinx:busInterfaceInfo>
      </spirit:vendorExtensions>
    </spirit:busInterface>
    <spirit:busInterface>
      <spirit:name>C3_RLDIII_RESET</spirit:name>
      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
      <spirit:master/>
      <spirit:connectionRequired>true</spirit:connectionRequired>
      <spirit:portMaps>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>RST</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c3_rldiii_ui_clk_sync_rst</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
      </spirit:portMaps>
      <spirit:parameters>
        <spirit:parameter>
          <spirit:name>POLARITY</spirit:name>
          <spirit:value spirit:id="BUSIFPARAM_VALUE.C3_RLDIII_RESET.POLARITY">ACTIVE_HIGH</spirit:value>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>INSERT_VIP</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.C3_RLDIII_RESET.INSERT_VIP">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
      </spirit:parameters>
      <spirit:vendorExtensions>
        <xilinx:busInterfaceInfo>
          <xilinx:enablement>
            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.C3_RLDIII_RESET" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 ">false</xilinx:isEnabled>
          </xilinx:enablement>
        </xilinx:busInterfaceInfo>
      </spirit:vendorExtensions>
    </spirit:busInterface>
    <spirit:busInterface>
      <spirit:name>C3_CLOCK</spirit:name>
      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
      <spirit:master/>
      <spirit:connectionRequired>true</spirit:connectionRequired>
      <spirit:portMaps>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>CLK</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c3_ui_clk</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
      </spirit:portMaps>
      <spirit:parameters>
        <spirit:parameter>
          <spirit:name>FREQ_HZ</spirit:name>
          <spirit:value spirit:format="float" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.C3_CLOCK.FREQ_HZ" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C3_FREQ_HZ&apos;))">100</spirit:value>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>ASSOCIATED_BUSIF</spirit:name>
          <spirit:value spirit:id="BUSIFPARAM_VALUE.C3_CLOCK.ASSOCIATED_BUSIF">S3_AXI:S3_AXI_CTRL</spirit:value>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>ASSOCIATED_RESET</spirit:name>
          <spirit:value spirit:id="BUSIFPARAM_VALUE.C3_CLOCK.ASSOCIATED_RESET">c3_aresetn:c3_ui_clk_sync_rst</spirit:value>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>PHASE</spirit:name>
          <spirit:value spirit:format="float" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.C3_CLOCK.PHASE" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C3_PHASE&apos;))">0</spirit:value>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>CLK_DOMAIN</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C3_CLOCK.CLK_DOMAIN"/>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>INSERT_VIP</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.C3_CLOCK.INSERT_VIP">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
      </spirit:parameters>
      <spirit:vendorExtensions>
        <xilinx:busInterfaceInfo>
          <xilinx:enablement>
            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.C3_CLOCK" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 ">false</xilinx:isEnabled>
          </xilinx:enablement>
        </xilinx:busInterfaceInfo>
      </spirit:vendorExtensions>
    </spirit:busInterface>
    <spirit:busInterface>
      <spirit:name>C3_MMCM_CLKOUT0</spirit:name>
      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
      <spirit:master/>
      <spirit:connectionRequired>true</spirit:connectionRequired>
      <spirit:portMaps>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>CLK</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c3_ui_addn_clk_0</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
      </spirit:portMaps>
      <spirit:parameters>
        <spirit:parameter>
          <spirit:name>FREQ_HZ</spirit:name>
          <spirit:value spirit:format="float" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.C3_MMCM_CLKOUT0.FREQ_HZ" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MMCM_CLKOUT0_FREQ&apos;))">10</spirit:value>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>ASSOCIATED_ASYNC_RESET</spirit:name>
          <spirit:value spirit:id="BUSIFPARAM_VALUE.C3_MMCM_CLKOUT0.ASSOCIATED_ASYNC_RESET">c3_aresetn</spirit:value>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>PHASE</spirit:name>
          <spirit:value spirit:format="float" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.C3_MMCM_CLKOUT0.PHASE" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C3_PHASE&apos;))">0</spirit:value>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>CLK_DOMAIN</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C3_MMCM_CLKOUT0.CLK_DOMAIN"/>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>ASSOCIATED_BUSIF</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C3_MMCM_CLKOUT0.ASSOCIATED_BUSIF"/>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>ASSOCIATED_RESET</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C3_MMCM_CLKOUT0.ASSOCIATED_RESET"/>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>INSERT_VIP</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.C3_MMCM_CLKOUT0.INSERT_VIP">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
      </spirit:parameters>
      <spirit:vendorExtensions>
        <xilinx:busInterfaceInfo>
          <xilinx:enablement>
            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.C3_MMCM_CLKOUT0" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 ">false</xilinx:isEnabled>
          </xilinx:enablement>
        </xilinx:busInterfaceInfo>
      </spirit:vendorExtensions>
    </spirit:busInterface>
    <spirit:busInterface>
      <spirit:name>C3_MMCM_CLKOUT1</spirit:name>
      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
      <spirit:master/>
      <spirit:connectionRequired>true</spirit:connectionRequired>
      <spirit:portMaps>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>CLK</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c3_ui_addn_clk_1</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
      </spirit:portMaps>
      <spirit:parameters>
        <spirit:parameter>
          <spirit:name>FREQ_HZ</spirit:name>
          <spirit:value spirit:format="float" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.C3_MMCM_CLKOUT1.FREQ_HZ" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MMCM_CLKOUT1_FREQ&apos;))">10</spirit:value>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>ASSOCIATED_ASYNC_RESET</spirit:name>
          <spirit:value spirit:id="BUSIFPARAM_VALUE.C3_MMCM_CLKOUT1.ASSOCIATED_ASYNC_RESET">c3_aresetn</spirit:value>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>PHASE</spirit:name>
          <spirit:value spirit:format="float" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.C3_MMCM_CLKOUT1.PHASE" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C3_PHASE&apos;))">0</spirit:value>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>CLK_DOMAIN</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C3_MMCM_CLKOUT1.CLK_DOMAIN"/>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>ASSOCIATED_BUSIF</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C3_MMCM_CLKOUT1.ASSOCIATED_BUSIF"/>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>ASSOCIATED_RESET</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C3_MMCM_CLKOUT1.ASSOCIATED_RESET"/>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>INSERT_VIP</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.C3_MMCM_CLKOUT1.INSERT_VIP">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
      </spirit:parameters>
      <spirit:vendorExtensions>
        <xilinx:busInterfaceInfo>
          <xilinx:enablement>
            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.C3_MMCM_CLKOUT1" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 ">false</xilinx:isEnabled>
          </xilinx:enablement>
        </xilinx:busInterfaceInfo>
      </spirit:vendorExtensions>
    </spirit:busInterface>
    <spirit:busInterface>
      <spirit:name>C3_MMCM_CLKOUT2</spirit:name>
      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
      <spirit:master/>
      <spirit:connectionRequired>true</spirit:connectionRequired>
      <spirit:portMaps>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>CLK</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c3_ui_addn_clk_2</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
      </spirit:portMaps>
      <spirit:parameters>
        <spirit:parameter>
          <spirit:name>FREQ_HZ</spirit:name>
          <spirit:value spirit:format="float" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.C3_MMCM_CLKOUT2.FREQ_HZ" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MMCM_CLKOUT2_FREQ&apos;))">10</spirit:value>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>ASSOCIATED_ASYNC_RESET</spirit:name>
          <spirit:value spirit:id="BUSIFPARAM_VALUE.C3_MMCM_CLKOUT2.ASSOCIATED_ASYNC_RESET">c3_aresetn</spirit:value>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>PHASE</spirit:name>
          <spirit:value spirit:format="float" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.C3_MMCM_CLKOUT2.PHASE" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C3_PHASE&apos;))">0</spirit:value>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>CLK_DOMAIN</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C3_MMCM_CLKOUT2.CLK_DOMAIN"/>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>ASSOCIATED_BUSIF</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C3_MMCM_CLKOUT2.ASSOCIATED_BUSIF"/>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>ASSOCIATED_RESET</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C3_MMCM_CLKOUT2.ASSOCIATED_RESET"/>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>INSERT_VIP</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.C3_MMCM_CLKOUT2.INSERT_VIP">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
      </spirit:parameters>
      <spirit:vendorExtensions>
        <xilinx:busInterfaceInfo>
          <xilinx:enablement>
            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.C3_MMCM_CLKOUT2" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 ">false</xilinx:isEnabled>
          </xilinx:enablement>
        </xilinx:busInterfaceInfo>
      </spirit:vendorExtensions>
    </spirit:busInterface>
    <spirit:busInterface>
      <spirit:name>C3_MMCM_CLKOUT3</spirit:name>
      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
      <spirit:master/>
      <spirit:connectionRequired>true</spirit:connectionRequired>
      <spirit:portMaps>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>CLK</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c3_ui_addn_clk_3</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
      </spirit:portMaps>
      <spirit:parameters>
        <spirit:parameter>
          <spirit:name>FREQ_HZ</spirit:name>
          <spirit:value spirit:format="float" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.C3_MMCM_CLKOUT3.FREQ_HZ" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MMCM_CLKOUT3_FREQ&apos;))">10</spirit:value>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>ASSOCIATED_ASYNC_RESET</spirit:name>
          <spirit:value spirit:id="BUSIFPARAM_VALUE.C3_MMCM_CLKOUT3.ASSOCIATED_ASYNC_RESET">c3_aresetn</spirit:value>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>PHASE</spirit:name>
          <spirit:value spirit:format="float" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.C3_MMCM_CLKOUT3.PHASE" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C3_PHASE&apos;))">0</spirit:value>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>CLK_DOMAIN</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C3_MMCM_CLKOUT3.CLK_DOMAIN"/>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>ASSOCIATED_BUSIF</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C3_MMCM_CLKOUT3.ASSOCIATED_BUSIF"/>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>ASSOCIATED_RESET</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C3_MMCM_CLKOUT3.ASSOCIATED_RESET"/>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>INSERT_VIP</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.C3_MMCM_CLKOUT3.INSERT_VIP">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
      </spirit:parameters>
      <spirit:vendorExtensions>
        <xilinx:busInterfaceInfo>
          <xilinx:enablement>
            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.C3_MMCM_CLKOUT3" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 ">false</xilinx:isEnabled>
          </xilinx:enablement>
        </xilinx:busInterfaceInfo>
      </spirit:vendorExtensions>
    </spirit:busInterface>
    <spirit:busInterface>
      <spirit:name>C3_MMCM_CLKOUT4</spirit:name>
      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
      <spirit:master/>
      <spirit:connectionRequired>true</spirit:connectionRequired>
      <spirit:portMaps>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>CLK</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c3_ui_addn_clk_4</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
      </spirit:portMaps>
      <spirit:parameters>
        <spirit:parameter>
          <spirit:name>FREQ_HZ</spirit:name>
          <spirit:value spirit:format="float" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.C3_MMCM_CLKOUT4.FREQ_HZ" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MMCM_CLKOUT4_FREQ&apos;))">10</spirit:value>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>ASSOCIATED_ASYNC_RESET</spirit:name>
          <spirit:value spirit:id="BUSIFPARAM_VALUE.C3_MMCM_CLKOUT4.ASSOCIATED_ASYNC_RESET">c3_aresetn</spirit:value>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>PHASE</spirit:name>
          <spirit:value spirit:format="float" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.C3_MMCM_CLKOUT4.PHASE" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C3_PHASE&apos;))">0</spirit:value>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>CLK_DOMAIN</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C3_MMCM_CLKOUT4.CLK_DOMAIN"/>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>ASSOCIATED_BUSIF</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C3_MMCM_CLKOUT4.ASSOCIATED_BUSIF"/>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>ASSOCIATED_RESET</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C3_MMCM_CLKOUT4.ASSOCIATED_RESET"/>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>INSERT_VIP</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.C3_MMCM_CLKOUT4.INSERT_VIP">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
      </spirit:parameters>
      <spirit:vendorExtensions>
        <xilinx:busInterfaceInfo>
          <xilinx:enablement>
            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.C3_MMCM_CLKOUT4" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 ">false</xilinx:isEnabled>
          </xilinx:enablement>
        </xilinx:busInterfaceInfo>
      </spirit:vendorExtensions>
    </spirit:busInterface>
    <spirit:busInterface>
      <spirit:name>S3_AXI_CTRL</spirit:name>
      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm" spirit:version="1.0"/>
      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm_rtl" spirit:version="1.0"/>
      <spirit:slave>
        <spirit:memoryMapRef spirit:memoryMapRef="c3_s_axi_ctrl_memmap"/>
      </spirit:slave>
      <spirit:connectionRequired>true</spirit:connectionRequired>
      <spirit:portMaps>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>AWVALID</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c3_s_axi_ctrl_awvalid</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>AWREADY</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c3_s_axi_ctrl_awready</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>AWADDR</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c3_s_axi_ctrl_awaddr</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>WVALID</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c3_s_axi_ctrl_wvalid</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>WREADY</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c3_s_axi_ctrl_wready</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>WDATA</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c3_s_axi_ctrl_wdata</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>BVALID</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c3_s_axi_ctrl_bvalid</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>BREADY</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c3_s_axi_ctrl_bready</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>BRESP</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c3_s_axi_ctrl_bresp</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>ARVALID</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c3_s_axi_ctrl_arvalid</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>ARREADY</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c3_s_axi_ctrl_arready</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>ARADDR</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c3_s_axi_ctrl_araddr</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>RVALID</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c3_s_axi_ctrl_rvalid</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>RREADY</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c3_s_axi_ctrl_rready</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>RDATA</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c3_s_axi_ctrl_rdata</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>RRESP</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c3_s_axi_ctrl_rresp</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
      </spirit:portMaps>
      <spirit:parameters>
        <spirit:parameter>
          <spirit:name>FREQ_HZ</spirit:name>
          <spirit:value spirit:format="float" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.S3_AXI_CTRL.FREQ_HZ" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C3_FREQ_HZ&apos;))">100</spirit:value>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>DATA_WIDTH</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S3_AXI_CTRL.DATA_WIDTH">1</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>PROTOCOL</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S3_AXI_CTRL.PROTOCOL">AXI4LITE</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>ID_WIDTH</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S3_AXI_CTRL.ID_WIDTH">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>ADDR_WIDTH</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S3_AXI_CTRL.ADDR_WIDTH">1</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>AWUSER_WIDTH</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S3_AXI_CTRL.AWUSER_WIDTH">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>ARUSER_WIDTH</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S3_AXI_CTRL.ARUSER_WIDTH">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>WUSER_WIDTH</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S3_AXI_CTRL.WUSER_WIDTH">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>RUSER_WIDTH</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S3_AXI_CTRL.RUSER_WIDTH">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>BUSER_WIDTH</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S3_AXI_CTRL.BUSER_WIDTH">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>READ_WRITE_MODE</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S3_AXI_CTRL.READ_WRITE_MODE">READ_WRITE</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>HAS_BURST</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S3_AXI_CTRL.HAS_BURST">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>HAS_LOCK</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S3_AXI_CTRL.HAS_LOCK">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>HAS_PROT</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S3_AXI_CTRL.HAS_PROT">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>HAS_CACHE</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S3_AXI_CTRL.HAS_CACHE">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>HAS_QOS</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S3_AXI_CTRL.HAS_QOS">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>HAS_REGION</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S3_AXI_CTRL.HAS_REGION">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>HAS_WSTRB</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S3_AXI_CTRL.HAS_WSTRB">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>HAS_BRESP</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S3_AXI_CTRL.HAS_BRESP">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>HAS_RRESP</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S3_AXI_CTRL.HAS_RRESP">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>SUPPORTS_NARROW_BURST</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S3_AXI_CTRL.SUPPORTS_NARROW_BURST">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>NUM_READ_OUTSTANDING</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S3_AXI_CTRL.NUM_READ_OUTSTANDING">1</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>NUM_WRITE_OUTSTANDING</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S3_AXI_CTRL.NUM_WRITE_OUTSTANDING">1</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>MAX_BURST_LENGTH</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S3_AXI_CTRL.MAX_BURST_LENGTH">1</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>PHASE</spirit:name>
          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S3_AXI_CTRL.PHASE">0.000</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>CLK_DOMAIN</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S3_AXI_CTRL.CLK_DOMAIN"/>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>NUM_READ_THREADS</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S3_AXI_CTRL.NUM_READ_THREADS">1</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>NUM_WRITE_THREADS</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S3_AXI_CTRL.NUM_WRITE_THREADS">1</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>RUSER_BITS_PER_BYTE</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S3_AXI_CTRL.RUSER_BITS_PER_BYTE">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>WUSER_BITS_PER_BYTE</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S3_AXI_CTRL.WUSER_BITS_PER_BYTE">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>INSERT_VIP</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.S3_AXI_CTRL.INSERT_VIP">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
      </spirit:parameters>
      <spirit:vendorExtensions>
        <xilinx:busInterfaceInfo>
          <xilinx:enablement>
            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.S3_AXI_CTRL" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_USE_AXI&apos;)) = 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_ECC&apos;)) = &quot;ON&quot; ) ">false</xilinx:isEnabled>
          </xilinx:enablement>
        </xilinx:busInterfaceInfo>
      </spirit:vendorExtensions>
    </spirit:busInterface>
    <spirit:busInterface>
      <spirit:name>S3_AXI</spirit:name>
      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm" spirit:version="1.0"/>
      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm_rtl" spirit:version="1.0"/>
      <spirit:slave>
        <spirit:memoryMapRef spirit:memoryMapRef="c3_memmap"/>
      </spirit:slave>
      <spirit:connectionRequired>true</spirit:connectionRequired>
      <spirit:portMaps>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>AWID</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c3_s_axi_awid</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>AWADDR</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c3_s_axi_awaddr</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>AWLEN</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c3_s_axi_awlen</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>AWSIZE</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c3_s_axi_awsize</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>AWBURST</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c3_s_axi_awburst</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>AWLOCK</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c3_s_axi_awlock</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>AWCACHE</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c3_s_axi_awcache</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>AWPROT</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c3_s_axi_awprot</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>AWQOS</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c3_s_axi_awqos</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>AWVALID</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c3_s_axi_awvalid</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>AWREADY</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c3_s_axi_awready</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>WDATA</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c3_s_axi_wdata</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>WSTRB</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c3_s_axi_wstrb</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>WLAST</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c3_s_axi_wlast</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>WVALID</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c3_s_axi_wvalid</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>WREADY</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c3_s_axi_wready</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>BREADY</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c3_s_axi_bready</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>BID</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c3_s_axi_bid</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>BRESP</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c3_s_axi_bresp</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>BVALID</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c3_s_axi_bvalid</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>ARID</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c3_s_axi_arid</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>ARADDR</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c3_s_axi_araddr</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>ARLEN</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c3_s_axi_arlen</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>ARSIZE</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c3_s_axi_arsize</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>ARBURST</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c3_s_axi_arburst</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>ARLOCK</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c3_s_axi_arlock</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>ARCACHE</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c3_s_axi_arcache</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>ARPROT</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c3_s_axi_arprot</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>ARQOS</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c3_s_axi_arqos</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>ARVALID</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c3_s_axi_arvalid</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>ARREADY</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c3_s_axi_arready</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>RREADY</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c3_s_axi_rready</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>RID</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c3_s_axi_rid</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>RDATA</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c3_s_axi_rdata</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>RRESP</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c3_s_axi_rresp</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>RLAST</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c3_s_axi_rlast</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>RVALID</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c3_s_axi_rvalid</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
      </spirit:portMaps>
      <spirit:parameters>
        <spirit:parameter>
          <spirit:name>FREQ_HZ</spirit:name>
          <spirit:value spirit:format="float" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.S3_AXI.FREQ_HZ" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C3_FREQ_HZ&apos;))">100</spirit:value>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>DATA_WIDTH</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S3_AXI.DATA_WIDTH">1</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>PROTOCOL</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S3_AXI.PROTOCOL">AXI4LITE</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>ID_WIDTH</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S3_AXI.ID_WIDTH">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>ADDR_WIDTH</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S3_AXI.ADDR_WIDTH">1</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>AWUSER_WIDTH</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S3_AXI.AWUSER_WIDTH">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>ARUSER_WIDTH</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S3_AXI.ARUSER_WIDTH">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>WUSER_WIDTH</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S3_AXI.WUSER_WIDTH">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>RUSER_WIDTH</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S3_AXI.RUSER_WIDTH">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>BUSER_WIDTH</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S3_AXI.BUSER_WIDTH">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>READ_WRITE_MODE</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S3_AXI.READ_WRITE_MODE">READ_WRITE</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>HAS_BURST</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S3_AXI.HAS_BURST">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>HAS_LOCK</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S3_AXI.HAS_LOCK">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>HAS_PROT</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S3_AXI.HAS_PROT">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>HAS_CACHE</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S3_AXI.HAS_CACHE">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>HAS_QOS</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S3_AXI.HAS_QOS">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>HAS_REGION</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S3_AXI.HAS_REGION">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>HAS_WSTRB</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S3_AXI.HAS_WSTRB">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>HAS_BRESP</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S3_AXI.HAS_BRESP">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>HAS_RRESP</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S3_AXI.HAS_RRESP">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>SUPPORTS_NARROW_BURST</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S3_AXI.SUPPORTS_NARROW_BURST">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>NUM_READ_OUTSTANDING</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S3_AXI.NUM_READ_OUTSTANDING">1</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>NUM_WRITE_OUTSTANDING</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S3_AXI.NUM_WRITE_OUTSTANDING">1</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>MAX_BURST_LENGTH</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S3_AXI.MAX_BURST_LENGTH">1</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>PHASE</spirit:name>
          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S3_AXI.PHASE">0.000</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>CLK_DOMAIN</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S3_AXI.CLK_DOMAIN"/>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>NUM_READ_THREADS</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S3_AXI.NUM_READ_THREADS">1</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>NUM_WRITE_THREADS</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S3_AXI.NUM_WRITE_THREADS">1</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>RUSER_BITS_PER_BYTE</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S3_AXI.RUSER_BITS_PER_BYTE">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>WUSER_BITS_PER_BYTE</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S3_AXI.WUSER_BITS_PER_BYTE">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>INSERT_VIP</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.S3_AXI.INSERT_VIP">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
      </spirit:parameters>
      <spirit:vendorExtensions>
        <xilinx:busInterfaceInfo>
          <xilinx:enablement>
            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.S3_AXI" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
          </xilinx:enablement>
        </xilinx:busInterfaceInfo>
      </spirit:vendorExtensions>
    </spirit:busInterface>
    <spirit:busInterface>
      <spirit:name>C3_SYS_CLK</spirit:name>
      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="diff_clock" spirit:version="1.0"/>
      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="diff_clock_rtl" spirit:version="1.0"/>
      <spirit:slave/>
      <spirit:connectionRequired>true</spirit:connectionRequired>
      <spirit:portMaps>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>CLK_P</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c3_sys_clk_p</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>CLK_N</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c3_sys_clk_n</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
      </spirit:portMaps>
      <spirit:parameters>
        <spirit:parameter>
          <spirit:name>CAN_DEBUG</spirit:name>
          <spirit:value spirit:format="bool" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C3_SYS_CLK.CAN_DEBUG">false</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>FREQ_HZ</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C3_SYS_CLK.FREQ_HZ">100000000</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
      </spirit:parameters>
      <spirit:vendorExtensions>
        <xilinx:busInterfaceInfo>
          <xilinx:enablement>
            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.C3_SYS_CLK" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_SYSCLK_TYPE&apos;)) = &quot;DIFF&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_IS_CLK_SHARED&apos;)) = &quot;FALSE&quot; ">false</xilinx:isEnabled>
          </xilinx:enablement>
        </xilinx:busInterfaceInfo>
      </spirit:vendorExtensions>
    </spirit:busInterface>
    <spirit:busInterface>
      <spirit:name>C3_SYS_CLK_I</spirit:name>
      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
      <spirit:slave/>
      <spirit:connectionRequired>true</spirit:connectionRequired>
      <spirit:portMaps>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>CLK</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c3_sys_clk_i</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
      </spirit:portMaps>
      <spirit:parameters>
        <spirit:parameter>
          <spirit:name>FREQ_HZ</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C3_SYS_CLK_I.FREQ_HZ">100000000</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>PHASE</spirit:name>
          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C3_SYS_CLK_I.PHASE">0.000</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>CLK_DOMAIN</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C3_SYS_CLK_I.CLK_DOMAIN"/>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>ASSOCIATED_BUSIF</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C3_SYS_CLK_I.ASSOCIATED_BUSIF"/>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>ASSOCIATED_RESET</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C3_SYS_CLK_I.ASSOCIATED_RESET"/>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>INSERT_VIP</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.C3_SYS_CLK_I.INSERT_VIP">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
      </spirit:parameters>
      <spirit:vendorExtensions>
        <xilinx:busInterfaceInfo>
          <xilinx:enablement>
            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.C3_SYS_CLK_I" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_SYSCLK_TYPE&apos;)) != &quot;DIFF&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_IS_CLK_SHARED&apos;)) = &quot;FALSE&quot; ">false</xilinx:isEnabled>
          </xilinx:enablement>
        </xilinx:busInterfaceInfo>
      </spirit:vendorExtensions>
    </spirit:busInterface>
    <spirit:busInterface>
      <spirit:name>C3_ARESETN</spirit:name>
      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
      <spirit:slave/>
      <spirit:connectionRequired>true</spirit:connectionRequired>
      <spirit:portMaps>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>ARESETN</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c3_aresetn</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
      </spirit:portMaps>
      <spirit:parameters>
        <spirit:parameter>
          <spirit:name>POLARITY</spirit:name>
          <spirit:value spirit:id="BUSIFPARAM_VALUE.C3_ARESETN.POLARITY">ACTIVE_LOW</spirit:value>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>INSERT_VIP</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.C3_ARESETN.INSERT_VIP">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
      </spirit:parameters>
    </spirit:busInterface>
    <spirit:busInterface>
      <spirit:name>C4_DDR3</spirit:name>
      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="ddrx" spirit:version="1.0"/>
      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="ddrx_rtl" spirit:version="1.0"/>
      <spirit:master/>
      <spirit:connectionRequired>true</spirit:connectionRequired>
      <spirit:portMaps>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>DQ</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c4_ddr3_dq</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>DQS_P</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c4_ddr3_dqs_p</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>DQS_N</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c4_ddr3_dqs_n</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>ADDR</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c4_ddr3_addr</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>BA</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c4_ddr3_ba</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>RAS_N</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c4_ddr3_ras_n</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>CAS_N</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c4_ddr3_cas_n</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>WE_N</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c4_ddr3_we_n</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>RESET_N</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c4_ddr3_reset_n</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>CK_P</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c4_ddr3_ck_p</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>CK_N</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c4_ddr3_ck_n</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>CKE</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c4_ddr3_cke</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>CS_N</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c4_ddr3_cs_n</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>DM</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c4_ddr3_dm</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>ODT</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c4_ddr3_odt</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>PARITY</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c4_ddr3_parity</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
      </spirit:portMaps>
      <spirit:parameters>
        <spirit:parameter>
          <spirit:name>CAN_DEBUG</spirit:name>
          <spirit:value spirit:format="bool" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C4_DDR3.CAN_DEBUG">false</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>TIMEPERIOD_PS</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C4_DDR3.TIMEPERIOD_PS">1250</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>MEMORY_TYPE</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C4_DDR3.MEMORY_TYPE">COMPONENTS</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>MEMORY_PART</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C4_DDR3.MEMORY_PART"/>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>DATA_WIDTH</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C4_DDR3.DATA_WIDTH">8</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>CS_ENABLED</spirit:name>
          <spirit:value spirit:format="bool" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C4_DDR3.CS_ENABLED">true</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>DATA_MASK_ENABLED</spirit:name>
          <spirit:value spirit:format="bool" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C4_DDR3.DATA_MASK_ENABLED">true</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>SLOT</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C4_DDR3.SLOT">Single</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>CUSTOM_PARTS</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C4_DDR3.CUSTOM_PARTS"/>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>MEM_ADDR_MAP</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C4_DDR3.MEM_ADDR_MAP">ROW_COLUMN_BANK</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>BURST_LENGTH</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C4_DDR3.BURST_LENGTH">8</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>AXI_ARBITRATION_SCHEME</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C4_DDR3.AXI_ARBITRATION_SCHEME">TDM</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>CAS_LATENCY</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C4_DDR3.CAS_LATENCY">11</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>CAS_WRITE_LATENCY</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C4_DDR3.CAS_WRITE_LATENCY">11</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
      </spirit:parameters>
      <spirit:vendorExtensions>
        <xilinx:busInterfaceInfo>
          <xilinx:enablement>
            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.C4_DDR3" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;DDR3&quot; ">false</xilinx:isEnabled>
          </xilinx:enablement>
        </xilinx:busInterfaceInfo>
      </spirit:vendorExtensions>
    </spirit:busInterface>
    <spirit:busInterface>
      <spirit:name>C4_DDR2</spirit:name>
      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="ddrx" spirit:version="1.0"/>
      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="ddrx_rtl" spirit:version="1.0"/>
      <spirit:master/>
      <spirit:connectionRequired>true</spirit:connectionRequired>
      <spirit:portMaps>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>DQ</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c4_ddr2_dq</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>DQS_P</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c4_ddr2_dqs_p</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>DQS_N</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c4_ddr2_dqs_n</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>ADDR</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c4_ddr2_addr</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>BA</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c4_ddr2_ba</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>RAS_N</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c4_ddr2_ras_n</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>CAS_N</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c4_ddr2_cas_n</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>WE_N</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c4_ddr2_we_n</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>RESET_N</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c4_ddr2_reset_n</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>CK_P</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c4_ddr2_ck_p</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>CK_N</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c4_ddr2_ck_n</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>CKE</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c4_ddr2_cke</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>CS_N</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c4_ddr2_cs_n</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>DM</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c4_ddr2_dm</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>ODT</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c4_ddr2_odt</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>PARITY</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c4_ddr2_parity</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
      </spirit:portMaps>
      <spirit:parameters>
        <spirit:parameter>
          <spirit:name>CAN_DEBUG</spirit:name>
          <spirit:value spirit:format="bool" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C4_DDR2.CAN_DEBUG">false</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>TIMEPERIOD_PS</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C4_DDR2.TIMEPERIOD_PS">1250</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>MEMORY_TYPE</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C4_DDR2.MEMORY_TYPE">COMPONENTS</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>MEMORY_PART</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C4_DDR2.MEMORY_PART"/>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>DATA_WIDTH</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C4_DDR2.DATA_WIDTH">8</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>CS_ENABLED</spirit:name>
          <spirit:value spirit:format="bool" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C4_DDR2.CS_ENABLED">true</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>DATA_MASK_ENABLED</spirit:name>
          <spirit:value spirit:format="bool" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C4_DDR2.DATA_MASK_ENABLED">true</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>SLOT</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C4_DDR2.SLOT">Single</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>CUSTOM_PARTS</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C4_DDR2.CUSTOM_PARTS"/>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>MEM_ADDR_MAP</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C4_DDR2.MEM_ADDR_MAP">ROW_COLUMN_BANK</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>BURST_LENGTH</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C4_DDR2.BURST_LENGTH">8</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>AXI_ARBITRATION_SCHEME</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C4_DDR2.AXI_ARBITRATION_SCHEME">TDM</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>CAS_LATENCY</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C4_DDR2.CAS_LATENCY">11</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>CAS_WRITE_LATENCY</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C4_DDR2.CAS_WRITE_LATENCY">11</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
      </spirit:parameters>
      <spirit:vendorExtensions>
        <xilinx:busInterfaceInfo>
          <xilinx:enablement>
            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.C4_DDR2" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;DDR2&quot; ">false</xilinx:isEnabled>
          </xilinx:enablement>
        </xilinx:busInterfaceInfo>
      </spirit:vendorExtensions>
    </spirit:busInterface>
    <spirit:busInterface>
      <spirit:name>C4_RESET</spirit:name>
      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
      <spirit:master/>
      <spirit:connectionRequired>true</spirit:connectionRequired>
      <spirit:portMaps>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>RST</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c4_ui_clk_sync_rst</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
      </spirit:portMaps>
      <spirit:parameters>
        <spirit:parameter>
          <spirit:name>POLARITY</spirit:name>
          <spirit:value spirit:id="BUSIFPARAM_VALUE.C4_RESET.POLARITY">ACTIVE_HIGH</spirit:value>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>INSERT_VIP</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.C4_RESET.INSERT_VIP">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
      </spirit:parameters>
      <spirit:vendorExtensions>
        <xilinx:busInterfaceInfo>
          <xilinx:enablement>
            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.C4_RESET" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 ">false</xilinx:isEnabled>
          </xilinx:enablement>
        </xilinx:busInterfaceInfo>
      </spirit:vendorExtensions>
    </spirit:busInterface>
    <spirit:busInterface>
      <spirit:name>C4_DDR3_RESET</spirit:name>
      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
      <spirit:master/>
      <spirit:connectionRequired>true</spirit:connectionRequired>
      <spirit:portMaps>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>RST</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c4_ddr3_ui_clk_sync_rst</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
      </spirit:portMaps>
      <spirit:parameters>
        <spirit:parameter>
          <spirit:name>POLARITY</spirit:name>
          <spirit:value spirit:id="BUSIFPARAM_VALUE.C4_DDR3_RESET.POLARITY">ACTIVE_HIGH</spirit:value>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>INSERT_VIP</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.C4_DDR3_RESET.INSERT_VIP">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
      </spirit:parameters>
      <spirit:vendorExtensions>
        <xilinx:busInterfaceInfo>
          <xilinx:enablement>
            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.C4_DDR3_RESET" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 ">false</xilinx:isEnabled>
          </xilinx:enablement>
        </xilinx:busInterfaceInfo>
      </spirit:vendorExtensions>
    </spirit:busInterface>
    <spirit:busInterface>
      <spirit:name>C4_DDR2_RESET</spirit:name>
      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
      <spirit:master/>
      <spirit:connectionRequired>true</spirit:connectionRequired>
      <spirit:portMaps>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>RST</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c4_ddr2_ui_clk_sync_rst</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
      </spirit:portMaps>
      <spirit:parameters>
        <spirit:parameter>
          <spirit:name>POLARITY</spirit:name>
          <spirit:value spirit:id="BUSIFPARAM_VALUE.C4_DDR2_RESET.POLARITY">ACTIVE_HIGH</spirit:value>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>INSERT_VIP</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.C4_DDR2_RESET.INSERT_VIP">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
      </spirit:parameters>
      <spirit:vendorExtensions>
        <xilinx:busInterfaceInfo>
          <xilinx:enablement>
            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.C4_DDR2_RESET" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 ">false</xilinx:isEnabled>
          </xilinx:enablement>
        </xilinx:busInterfaceInfo>
      </spirit:vendorExtensions>
    </spirit:busInterface>
    <spirit:busInterface>
      <spirit:name>C4_LPDDR2_RESET</spirit:name>
      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
      <spirit:master/>
      <spirit:connectionRequired>true</spirit:connectionRequired>
      <spirit:portMaps>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>RST</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c4_lpddr2_ui_clk_sync_rst</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
      </spirit:portMaps>
      <spirit:parameters>
        <spirit:parameter>
          <spirit:name>POLARITY</spirit:name>
          <spirit:value spirit:id="BUSIFPARAM_VALUE.C4_LPDDR2_RESET.POLARITY">ACTIVE_HIGH</spirit:value>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>INSERT_VIP</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.C4_LPDDR2_RESET.INSERT_VIP">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
      </spirit:parameters>
      <spirit:vendorExtensions>
        <xilinx:busInterfaceInfo>
          <xilinx:enablement>
            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.C4_LPDDR2_RESET" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 ">false</xilinx:isEnabled>
          </xilinx:enablement>
        </xilinx:busInterfaceInfo>
      </spirit:vendorExtensions>
    </spirit:busInterface>
    <spirit:busInterface>
      <spirit:name>C4_QDRIIP_RESET</spirit:name>
      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
      <spirit:master/>
      <spirit:connectionRequired>true</spirit:connectionRequired>
      <spirit:portMaps>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>RST</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c4_qdriip_ui_clk_sync_rst</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
      </spirit:portMaps>
      <spirit:parameters>
        <spirit:parameter>
          <spirit:name>POLARITY</spirit:name>
          <spirit:value spirit:id="BUSIFPARAM_VALUE.C4_QDRIIP_RESET.POLARITY">ACTIVE_HIGH</spirit:value>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>INSERT_VIP</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.C4_QDRIIP_RESET.INSERT_VIP">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
      </spirit:parameters>
      <spirit:vendorExtensions>
        <xilinx:busInterfaceInfo>
          <xilinx:enablement>
            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.C4_QDRIIP_RESET" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 ">false</xilinx:isEnabled>
          </xilinx:enablement>
        </xilinx:busInterfaceInfo>
      </spirit:vendorExtensions>
    </spirit:busInterface>
    <spirit:busInterface>
      <spirit:name>C4_RLDII_RESET</spirit:name>
      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
      <spirit:master/>
      <spirit:connectionRequired>true</spirit:connectionRequired>
      <spirit:portMaps>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>RST</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c4_rldii_ui_clk_sync_rst</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
      </spirit:portMaps>
      <spirit:parameters>
        <spirit:parameter>
          <spirit:name>POLARITY</spirit:name>
          <spirit:value spirit:id="BUSIFPARAM_VALUE.C4_RLDII_RESET.POLARITY">ACTIVE_HIGH</spirit:value>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>INSERT_VIP</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.C4_RLDII_RESET.INSERT_VIP">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
      </spirit:parameters>
      <spirit:vendorExtensions>
        <xilinx:busInterfaceInfo>
          <xilinx:enablement>
            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.C4_RLDII_RESET" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 ">false</xilinx:isEnabled>
          </xilinx:enablement>
        </xilinx:busInterfaceInfo>
      </spirit:vendorExtensions>
    </spirit:busInterface>
    <spirit:busInterface>
      <spirit:name>C4_RLDIII_RESET</spirit:name>
      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
      <spirit:master/>
      <spirit:connectionRequired>true</spirit:connectionRequired>
      <spirit:portMaps>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>RST</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c4_rldiii_ui_clk_sync_rst</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
      </spirit:portMaps>
      <spirit:parameters>
        <spirit:parameter>
          <spirit:name>POLARITY</spirit:name>
          <spirit:value spirit:id="BUSIFPARAM_VALUE.C4_RLDIII_RESET.POLARITY">ACTIVE_HIGH</spirit:value>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>INSERT_VIP</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.C4_RLDIII_RESET.INSERT_VIP">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
      </spirit:parameters>
      <spirit:vendorExtensions>
        <xilinx:busInterfaceInfo>
          <xilinx:enablement>
            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.C4_RLDIII_RESET" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 ">false</xilinx:isEnabled>
          </xilinx:enablement>
        </xilinx:busInterfaceInfo>
      </spirit:vendorExtensions>
    </spirit:busInterface>
    <spirit:busInterface>
      <spirit:name>C4_CLOCK</spirit:name>
      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
      <spirit:master/>
      <spirit:connectionRequired>true</spirit:connectionRequired>
      <spirit:portMaps>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>CLK</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c4_ui_clk</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
      </spirit:portMaps>
      <spirit:parameters>
        <spirit:parameter>
          <spirit:name>FREQ_HZ</spirit:name>
          <spirit:value spirit:format="float" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.C4_CLOCK.FREQ_HZ" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C4_FREQ_HZ&apos;))">100</spirit:value>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>ASSOCIATED_BUSIF</spirit:name>
          <spirit:value spirit:id="BUSIFPARAM_VALUE.C4_CLOCK.ASSOCIATED_BUSIF">S4_AXI:S4_AXI_CTRL</spirit:value>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>ASSOCIATED_RESET</spirit:name>
          <spirit:value spirit:id="BUSIFPARAM_VALUE.C4_CLOCK.ASSOCIATED_RESET">c4_aresetn:c4_ui_clk_sync_rst</spirit:value>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>PHASE</spirit:name>
          <spirit:value spirit:format="float" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.C4_CLOCK.PHASE" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C4_PHASE&apos;))">0</spirit:value>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>CLK_DOMAIN</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C4_CLOCK.CLK_DOMAIN"/>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>INSERT_VIP</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.C4_CLOCK.INSERT_VIP">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
      </spirit:parameters>
      <spirit:vendorExtensions>
        <xilinx:busInterfaceInfo>
          <xilinx:enablement>
            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.C4_CLOCK" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 ">false</xilinx:isEnabled>
          </xilinx:enablement>
        </xilinx:busInterfaceInfo>
      </spirit:vendorExtensions>
    </spirit:busInterface>
    <spirit:busInterface>
      <spirit:name>C4_MMCM_CLKOUT0</spirit:name>
      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
      <spirit:master/>
      <spirit:connectionRequired>true</spirit:connectionRequired>
      <spirit:portMaps>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>CLK</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c4_ui_addn_clk_0</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
      </spirit:portMaps>
      <spirit:parameters>
        <spirit:parameter>
          <spirit:name>FREQ_HZ</spirit:name>
          <spirit:value spirit:format="float" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.C4_MMCM_CLKOUT0.FREQ_HZ" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MMCM_CLKOUT0_FREQ&apos;))">10</spirit:value>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>ASSOCIATED_ASYNC_RESET</spirit:name>
          <spirit:value spirit:id="BUSIFPARAM_VALUE.C4_MMCM_CLKOUT0.ASSOCIATED_ASYNC_RESET">c4_aresetn</spirit:value>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>PHASE</spirit:name>
          <spirit:value spirit:format="float" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.C4_MMCM_CLKOUT0.PHASE" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C4_PHASE&apos;))">0</spirit:value>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>CLK_DOMAIN</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C4_MMCM_CLKOUT0.CLK_DOMAIN"/>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>ASSOCIATED_BUSIF</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C4_MMCM_CLKOUT0.ASSOCIATED_BUSIF"/>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>ASSOCIATED_RESET</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C4_MMCM_CLKOUT0.ASSOCIATED_RESET"/>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>INSERT_VIP</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.C4_MMCM_CLKOUT0.INSERT_VIP">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
      </spirit:parameters>
      <spirit:vendorExtensions>
        <xilinx:busInterfaceInfo>
          <xilinx:enablement>
            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.C4_MMCM_CLKOUT0" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 ">false</xilinx:isEnabled>
          </xilinx:enablement>
        </xilinx:busInterfaceInfo>
      </spirit:vendorExtensions>
    </spirit:busInterface>
    <spirit:busInterface>
      <spirit:name>C4_MMCM_CLKOUT1</spirit:name>
      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
      <spirit:master/>
      <spirit:connectionRequired>true</spirit:connectionRequired>
      <spirit:portMaps>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>CLK</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c4_ui_addn_clk_1</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
      </spirit:portMaps>
      <spirit:parameters>
        <spirit:parameter>
          <spirit:name>FREQ_HZ</spirit:name>
          <spirit:value spirit:format="float" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.C4_MMCM_CLKOUT1.FREQ_HZ" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MMCM_CLKOUT1_FREQ&apos;))">10</spirit:value>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>ASSOCIATED_ASYNC_RESET</spirit:name>
          <spirit:value spirit:id="BUSIFPARAM_VALUE.C4_MMCM_CLKOUT1.ASSOCIATED_ASYNC_RESET">c4_aresetn</spirit:value>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>PHASE</spirit:name>
          <spirit:value spirit:format="float" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.C4_MMCM_CLKOUT1.PHASE" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C4_PHASE&apos;))">0</spirit:value>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>CLK_DOMAIN</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C4_MMCM_CLKOUT1.CLK_DOMAIN"/>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>ASSOCIATED_BUSIF</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C4_MMCM_CLKOUT1.ASSOCIATED_BUSIF"/>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>ASSOCIATED_RESET</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C4_MMCM_CLKOUT1.ASSOCIATED_RESET"/>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>INSERT_VIP</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.C4_MMCM_CLKOUT1.INSERT_VIP">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
      </spirit:parameters>
      <spirit:vendorExtensions>
        <xilinx:busInterfaceInfo>
          <xilinx:enablement>
            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.C4_MMCM_CLKOUT1" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 ">false</xilinx:isEnabled>
          </xilinx:enablement>
        </xilinx:busInterfaceInfo>
      </spirit:vendorExtensions>
    </spirit:busInterface>
    <spirit:busInterface>
      <spirit:name>C4_MMCM_CLKOUT2</spirit:name>
      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
      <spirit:master/>
      <spirit:connectionRequired>true</spirit:connectionRequired>
      <spirit:portMaps>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>CLK</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c4_ui_addn_clk_2</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
      </spirit:portMaps>
      <spirit:parameters>
        <spirit:parameter>
          <spirit:name>FREQ_HZ</spirit:name>
          <spirit:value spirit:format="float" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.C4_MMCM_CLKOUT2.FREQ_HZ" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MMCM_CLKOUT2_FREQ&apos;))">10</spirit:value>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>ASSOCIATED_ASYNC_RESET</spirit:name>
          <spirit:value spirit:id="BUSIFPARAM_VALUE.C4_MMCM_CLKOUT2.ASSOCIATED_ASYNC_RESET">c4_aresetn</spirit:value>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>PHASE</spirit:name>
          <spirit:value spirit:format="float" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.C4_MMCM_CLKOUT2.PHASE" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C4_PHASE&apos;))">0</spirit:value>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>CLK_DOMAIN</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C4_MMCM_CLKOUT2.CLK_DOMAIN"/>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>ASSOCIATED_BUSIF</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C4_MMCM_CLKOUT2.ASSOCIATED_BUSIF"/>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>ASSOCIATED_RESET</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C4_MMCM_CLKOUT2.ASSOCIATED_RESET"/>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>INSERT_VIP</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.C4_MMCM_CLKOUT2.INSERT_VIP">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
      </spirit:parameters>
      <spirit:vendorExtensions>
        <xilinx:busInterfaceInfo>
          <xilinx:enablement>
            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.C4_MMCM_CLKOUT2" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 ">false</xilinx:isEnabled>
          </xilinx:enablement>
        </xilinx:busInterfaceInfo>
      </spirit:vendorExtensions>
    </spirit:busInterface>
    <spirit:busInterface>
      <spirit:name>C4_MMCM_CLKOUT3</spirit:name>
      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
      <spirit:master/>
      <spirit:connectionRequired>true</spirit:connectionRequired>
      <spirit:portMaps>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>CLK</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c4_ui_addn_clk_3</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
      </spirit:portMaps>
      <spirit:parameters>
        <spirit:parameter>
          <spirit:name>FREQ_HZ</spirit:name>
          <spirit:value spirit:format="float" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.C4_MMCM_CLKOUT3.FREQ_HZ" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MMCM_CLKOUT3_FREQ&apos;))">10</spirit:value>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>ASSOCIATED_ASYNC_RESET</spirit:name>
          <spirit:value spirit:id="BUSIFPARAM_VALUE.C4_MMCM_CLKOUT3.ASSOCIATED_ASYNC_RESET">c4_aresetn</spirit:value>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>PHASE</spirit:name>
          <spirit:value spirit:format="float" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.C4_MMCM_CLKOUT3.PHASE" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C4_PHASE&apos;))">0</spirit:value>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>CLK_DOMAIN</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C4_MMCM_CLKOUT3.CLK_DOMAIN"/>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>ASSOCIATED_BUSIF</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C4_MMCM_CLKOUT3.ASSOCIATED_BUSIF"/>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>ASSOCIATED_RESET</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C4_MMCM_CLKOUT3.ASSOCIATED_RESET"/>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>INSERT_VIP</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.C4_MMCM_CLKOUT3.INSERT_VIP">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
      </spirit:parameters>
      <spirit:vendorExtensions>
        <xilinx:busInterfaceInfo>
          <xilinx:enablement>
            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.C4_MMCM_CLKOUT3" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 ">false</xilinx:isEnabled>
          </xilinx:enablement>
        </xilinx:busInterfaceInfo>
      </spirit:vendorExtensions>
    </spirit:busInterface>
    <spirit:busInterface>
      <spirit:name>C4_MMCM_CLKOUT4</spirit:name>
      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
      <spirit:master/>
      <spirit:connectionRequired>true</spirit:connectionRequired>
      <spirit:portMaps>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>CLK</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c4_ui_addn_clk_4</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
      </spirit:portMaps>
      <spirit:parameters>
        <spirit:parameter>
          <spirit:name>FREQ_HZ</spirit:name>
          <spirit:value spirit:format="float" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.C4_MMCM_CLKOUT4.FREQ_HZ" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MMCM_CLKOUT4_FREQ&apos;))">10</spirit:value>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>ASSOCIATED_ASYNC_RESET</spirit:name>
          <spirit:value spirit:id="BUSIFPARAM_VALUE.C4_MMCM_CLKOUT4.ASSOCIATED_ASYNC_RESET">c4_aresetn</spirit:value>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>PHASE</spirit:name>
          <spirit:value spirit:format="float" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.C4_MMCM_CLKOUT4.PHASE" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C4_PHASE&apos;))">0</spirit:value>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>CLK_DOMAIN</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C4_MMCM_CLKOUT4.CLK_DOMAIN"/>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>ASSOCIATED_BUSIF</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C4_MMCM_CLKOUT4.ASSOCIATED_BUSIF"/>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>ASSOCIATED_RESET</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C4_MMCM_CLKOUT4.ASSOCIATED_RESET"/>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>INSERT_VIP</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.C4_MMCM_CLKOUT4.INSERT_VIP">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
      </spirit:parameters>
      <spirit:vendorExtensions>
        <xilinx:busInterfaceInfo>
          <xilinx:enablement>
            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.C4_MMCM_CLKOUT4" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 ">false</xilinx:isEnabled>
          </xilinx:enablement>
        </xilinx:busInterfaceInfo>
      </spirit:vendorExtensions>
    </spirit:busInterface>
    <spirit:busInterface>
      <spirit:name>S4_AXI_CTRL</spirit:name>
      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm" spirit:version="1.0"/>
      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm_rtl" spirit:version="1.0"/>
      <spirit:slave>
        <spirit:memoryMapRef spirit:memoryMapRef="c4_s_axi_ctrl_memmap"/>
      </spirit:slave>
      <spirit:connectionRequired>true</spirit:connectionRequired>
      <spirit:portMaps>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>AWVALID</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c4_s_axi_ctrl_awvalid</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>AWREADY</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c4_s_axi_ctrl_awready</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>AWADDR</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c4_s_axi_ctrl_awaddr</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>WVALID</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c4_s_axi_ctrl_wvalid</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>WREADY</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c4_s_axi_ctrl_wready</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>WDATA</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c4_s_axi_ctrl_wdata</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>BVALID</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c4_s_axi_ctrl_bvalid</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>BREADY</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c4_s_axi_ctrl_bready</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>BRESP</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c4_s_axi_ctrl_bresp</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>ARVALID</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c4_s_axi_ctrl_arvalid</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>ARREADY</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c4_s_axi_ctrl_arready</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>ARADDR</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c4_s_axi_ctrl_araddr</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>RVALID</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c4_s_axi_ctrl_rvalid</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>RREADY</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c4_s_axi_ctrl_rready</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>RDATA</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c4_s_axi_ctrl_rdata</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>RRESP</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c4_s_axi_ctrl_rresp</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
      </spirit:portMaps>
      <spirit:parameters>
        <spirit:parameter>
          <spirit:name>FREQ_HZ</spirit:name>
          <spirit:value spirit:format="float" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.S4_AXI_CTRL.FREQ_HZ" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C4_FREQ_HZ&apos;))">100</spirit:value>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>DATA_WIDTH</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S4_AXI_CTRL.DATA_WIDTH">1</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>PROTOCOL</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S4_AXI_CTRL.PROTOCOL">AXI4LITE</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>ID_WIDTH</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S4_AXI_CTRL.ID_WIDTH">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>ADDR_WIDTH</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S4_AXI_CTRL.ADDR_WIDTH">1</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>AWUSER_WIDTH</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S4_AXI_CTRL.AWUSER_WIDTH">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>ARUSER_WIDTH</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S4_AXI_CTRL.ARUSER_WIDTH">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>WUSER_WIDTH</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S4_AXI_CTRL.WUSER_WIDTH">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>RUSER_WIDTH</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S4_AXI_CTRL.RUSER_WIDTH">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>BUSER_WIDTH</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S4_AXI_CTRL.BUSER_WIDTH">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>READ_WRITE_MODE</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S4_AXI_CTRL.READ_WRITE_MODE">READ_WRITE</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>HAS_BURST</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S4_AXI_CTRL.HAS_BURST">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>HAS_LOCK</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S4_AXI_CTRL.HAS_LOCK">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>HAS_PROT</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S4_AXI_CTRL.HAS_PROT">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>HAS_CACHE</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S4_AXI_CTRL.HAS_CACHE">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>HAS_QOS</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S4_AXI_CTRL.HAS_QOS">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>HAS_REGION</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S4_AXI_CTRL.HAS_REGION">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>HAS_WSTRB</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S4_AXI_CTRL.HAS_WSTRB">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>HAS_BRESP</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S4_AXI_CTRL.HAS_BRESP">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>HAS_RRESP</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S4_AXI_CTRL.HAS_RRESP">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>SUPPORTS_NARROW_BURST</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S4_AXI_CTRL.SUPPORTS_NARROW_BURST">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>NUM_READ_OUTSTANDING</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S4_AXI_CTRL.NUM_READ_OUTSTANDING">1</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>NUM_WRITE_OUTSTANDING</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S4_AXI_CTRL.NUM_WRITE_OUTSTANDING">1</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>MAX_BURST_LENGTH</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S4_AXI_CTRL.MAX_BURST_LENGTH">1</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>PHASE</spirit:name>
          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S4_AXI_CTRL.PHASE">0.000</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>CLK_DOMAIN</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S4_AXI_CTRL.CLK_DOMAIN"/>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>NUM_READ_THREADS</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S4_AXI_CTRL.NUM_READ_THREADS">1</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>NUM_WRITE_THREADS</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S4_AXI_CTRL.NUM_WRITE_THREADS">1</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>RUSER_BITS_PER_BYTE</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S4_AXI_CTRL.RUSER_BITS_PER_BYTE">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>WUSER_BITS_PER_BYTE</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S4_AXI_CTRL.WUSER_BITS_PER_BYTE">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>INSERT_VIP</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.S4_AXI_CTRL.INSERT_VIP">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
      </spirit:parameters>
      <spirit:vendorExtensions>
        <xilinx:busInterfaceInfo>
          <xilinx:enablement>
            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.S4_AXI_CTRL" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_USE_AXI&apos;)) = 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_ECC&apos;)) = &quot;ON&quot; ) ">false</xilinx:isEnabled>
          </xilinx:enablement>
        </xilinx:busInterfaceInfo>
      </spirit:vendorExtensions>
    </spirit:busInterface>
    <spirit:busInterface>
      <spirit:name>S4_AXI</spirit:name>
      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm" spirit:version="1.0"/>
      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm_rtl" spirit:version="1.0"/>
      <spirit:slave>
        <spirit:memoryMapRef spirit:memoryMapRef="c4_memmap"/>
      </spirit:slave>
      <spirit:connectionRequired>true</spirit:connectionRequired>
      <spirit:portMaps>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>AWID</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c4_s_axi_awid</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>AWADDR</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c4_s_axi_awaddr</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>AWLEN</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c4_s_axi_awlen</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>AWSIZE</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c4_s_axi_awsize</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>AWBURST</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c4_s_axi_awburst</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>AWLOCK</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c4_s_axi_awlock</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>AWCACHE</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c4_s_axi_awcache</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>AWPROT</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c4_s_axi_awprot</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>AWQOS</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c4_s_axi_awqos</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>AWVALID</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c4_s_axi_awvalid</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>AWREADY</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c4_s_axi_awready</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>WDATA</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c4_s_axi_wdata</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>WSTRB</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c4_s_axi_wstrb</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>WLAST</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c4_s_axi_wlast</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>WVALID</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c4_s_axi_wvalid</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>WREADY</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c4_s_axi_wready</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>BREADY</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c4_s_axi_bready</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>BID</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c4_s_axi_bid</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>BRESP</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c4_s_axi_bresp</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>BVALID</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c4_s_axi_bvalid</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>ARID</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c4_s_axi_arid</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>ARADDR</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c4_s_axi_araddr</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>ARLEN</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c4_s_axi_arlen</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>ARSIZE</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c4_s_axi_arsize</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>ARBURST</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c4_s_axi_arburst</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>ARLOCK</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c4_s_axi_arlock</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>ARCACHE</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c4_s_axi_arcache</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>ARPROT</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c4_s_axi_arprot</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>ARQOS</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c4_s_axi_arqos</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>ARVALID</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c4_s_axi_arvalid</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>ARREADY</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c4_s_axi_arready</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>RREADY</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c4_s_axi_rready</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>RID</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c4_s_axi_rid</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>RDATA</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c4_s_axi_rdata</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>RRESP</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c4_s_axi_rresp</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>RLAST</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c4_s_axi_rlast</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>RVALID</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c4_s_axi_rvalid</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
      </spirit:portMaps>
      <spirit:parameters>
        <spirit:parameter>
          <spirit:name>FREQ_HZ</spirit:name>
          <spirit:value spirit:format="float" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.S4_AXI.FREQ_HZ" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C4_FREQ_HZ&apos;))">100</spirit:value>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>DATA_WIDTH</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S4_AXI.DATA_WIDTH">1</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>PROTOCOL</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S4_AXI.PROTOCOL">AXI4LITE</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>ID_WIDTH</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S4_AXI.ID_WIDTH">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>ADDR_WIDTH</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S4_AXI.ADDR_WIDTH">1</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>AWUSER_WIDTH</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S4_AXI.AWUSER_WIDTH">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>ARUSER_WIDTH</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S4_AXI.ARUSER_WIDTH">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>WUSER_WIDTH</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S4_AXI.WUSER_WIDTH">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>RUSER_WIDTH</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S4_AXI.RUSER_WIDTH">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>BUSER_WIDTH</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S4_AXI.BUSER_WIDTH">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>READ_WRITE_MODE</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S4_AXI.READ_WRITE_MODE">READ_WRITE</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>HAS_BURST</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S4_AXI.HAS_BURST">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>HAS_LOCK</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S4_AXI.HAS_LOCK">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>HAS_PROT</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S4_AXI.HAS_PROT">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>HAS_CACHE</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S4_AXI.HAS_CACHE">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>HAS_QOS</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S4_AXI.HAS_QOS">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>HAS_REGION</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S4_AXI.HAS_REGION">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>HAS_WSTRB</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S4_AXI.HAS_WSTRB">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>HAS_BRESP</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S4_AXI.HAS_BRESP">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>HAS_RRESP</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S4_AXI.HAS_RRESP">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>SUPPORTS_NARROW_BURST</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S4_AXI.SUPPORTS_NARROW_BURST">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>NUM_READ_OUTSTANDING</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S4_AXI.NUM_READ_OUTSTANDING">1</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>NUM_WRITE_OUTSTANDING</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S4_AXI.NUM_WRITE_OUTSTANDING">1</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>MAX_BURST_LENGTH</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S4_AXI.MAX_BURST_LENGTH">1</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>PHASE</spirit:name>
          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S4_AXI.PHASE">0.000</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>CLK_DOMAIN</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S4_AXI.CLK_DOMAIN"/>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>NUM_READ_THREADS</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S4_AXI.NUM_READ_THREADS">1</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>NUM_WRITE_THREADS</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S4_AXI.NUM_WRITE_THREADS">1</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>RUSER_BITS_PER_BYTE</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S4_AXI.RUSER_BITS_PER_BYTE">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>WUSER_BITS_PER_BYTE</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S4_AXI.WUSER_BITS_PER_BYTE">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>INSERT_VIP</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.S4_AXI.INSERT_VIP">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
      </spirit:parameters>
      <spirit:vendorExtensions>
        <xilinx:busInterfaceInfo>
          <xilinx:enablement>
            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.S4_AXI" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
          </xilinx:enablement>
        </xilinx:busInterfaceInfo>
      </spirit:vendorExtensions>
    </spirit:busInterface>
    <spirit:busInterface>
      <spirit:name>C4_SYS_CLK</spirit:name>
      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="diff_clock" spirit:version="1.0"/>
      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="diff_clock_rtl" spirit:version="1.0"/>
      <spirit:slave/>
      <spirit:connectionRequired>true</spirit:connectionRequired>
      <spirit:portMaps>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>CLK_P</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c4_sys_clk_p</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>CLK_N</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c4_sys_clk_n</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
      </spirit:portMaps>
      <spirit:parameters>
        <spirit:parameter>
          <spirit:name>CAN_DEBUG</spirit:name>
          <spirit:value spirit:format="bool" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C4_SYS_CLK.CAN_DEBUG">false</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>FREQ_HZ</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C4_SYS_CLK.FREQ_HZ">100000000</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
      </spirit:parameters>
      <spirit:vendorExtensions>
        <xilinx:busInterfaceInfo>
          <xilinx:enablement>
            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.C4_SYS_CLK" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_SYSCLK_TYPE&apos;)) = &quot;DIFF&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_IS_CLK_SHARED&apos;)) = &quot;FALSE&quot; ">false</xilinx:isEnabled>
          </xilinx:enablement>
        </xilinx:busInterfaceInfo>
      </spirit:vendorExtensions>
    </spirit:busInterface>
    <spirit:busInterface>
      <spirit:name>C4_SYS_CLK_I</spirit:name>
      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
      <spirit:slave/>
      <spirit:connectionRequired>true</spirit:connectionRequired>
      <spirit:portMaps>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>CLK</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c4_sys_clk_i</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
      </spirit:portMaps>
      <spirit:parameters>
        <spirit:parameter>
          <spirit:name>FREQ_HZ</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C4_SYS_CLK_I.FREQ_HZ">100000000</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>PHASE</spirit:name>
          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C4_SYS_CLK_I.PHASE">0.000</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>CLK_DOMAIN</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C4_SYS_CLK_I.CLK_DOMAIN"/>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>ASSOCIATED_BUSIF</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C4_SYS_CLK_I.ASSOCIATED_BUSIF"/>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>ASSOCIATED_RESET</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C4_SYS_CLK_I.ASSOCIATED_RESET"/>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>INSERT_VIP</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.C4_SYS_CLK_I.INSERT_VIP">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
      </spirit:parameters>
      <spirit:vendorExtensions>
        <xilinx:busInterfaceInfo>
          <xilinx:enablement>
            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.C4_SYS_CLK_I" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_SYSCLK_TYPE&apos;)) != &quot;DIFF&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_IS_CLK_SHARED&apos;)) = &quot;FALSE&quot; ">false</xilinx:isEnabled>
          </xilinx:enablement>
        </xilinx:busInterfaceInfo>
      </spirit:vendorExtensions>
    </spirit:busInterface>
    <spirit:busInterface>
      <spirit:name>C4_ARESETN</spirit:name>
      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
      <spirit:slave/>
      <spirit:connectionRequired>true</spirit:connectionRequired>
      <spirit:portMaps>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>ARESETN</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c4_aresetn</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
      </spirit:portMaps>
      <spirit:parameters>
        <spirit:parameter>
          <spirit:name>POLARITY</spirit:name>
          <spirit:value spirit:id="BUSIFPARAM_VALUE.C4_ARESETN.POLARITY">ACTIVE_LOW</spirit:value>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>INSERT_VIP</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.C4_ARESETN.INSERT_VIP">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
      </spirit:parameters>
    </spirit:busInterface>
    <spirit:busInterface>
      <spirit:name>C5_DDR3</spirit:name>
      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="ddrx" spirit:version="1.0"/>
      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="ddrx_rtl" spirit:version="1.0"/>
      <spirit:master/>
      <spirit:connectionRequired>true</spirit:connectionRequired>
      <spirit:portMaps>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>DQ</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c5_ddr3_dq</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>DQS_P</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c5_ddr3_dqs_p</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>DQS_N</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c5_ddr3_dqs_n</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>ADDR</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c5_ddr3_addr</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>BA</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c5_ddr3_ba</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>RAS_N</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c5_ddr3_ras_n</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>CAS_N</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c5_ddr3_cas_n</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>WE_N</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c5_ddr3_we_n</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>RESET_N</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c5_ddr3_reset_n</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>CK_P</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c5_ddr3_ck_p</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>CK_N</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c5_ddr3_ck_n</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>CKE</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c5_ddr3_cke</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>CS_N</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c5_ddr3_cs_n</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>DM</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c5_ddr3_dm</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>ODT</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c5_ddr3_odt</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>PARITY</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c5_ddr3_parity</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
      </spirit:portMaps>
      <spirit:parameters>
        <spirit:parameter>
          <spirit:name>CAN_DEBUG</spirit:name>
          <spirit:value spirit:format="bool" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C5_DDR3.CAN_DEBUG">false</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>TIMEPERIOD_PS</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C5_DDR3.TIMEPERIOD_PS">1250</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>MEMORY_TYPE</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C5_DDR3.MEMORY_TYPE">COMPONENTS</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>MEMORY_PART</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C5_DDR3.MEMORY_PART"/>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>DATA_WIDTH</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C5_DDR3.DATA_WIDTH">8</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>CS_ENABLED</spirit:name>
          <spirit:value spirit:format="bool" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C5_DDR3.CS_ENABLED">true</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>DATA_MASK_ENABLED</spirit:name>
          <spirit:value spirit:format="bool" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C5_DDR3.DATA_MASK_ENABLED">true</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>SLOT</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C5_DDR3.SLOT">Single</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>CUSTOM_PARTS</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C5_DDR3.CUSTOM_PARTS"/>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>MEM_ADDR_MAP</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C5_DDR3.MEM_ADDR_MAP">ROW_COLUMN_BANK</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>BURST_LENGTH</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C5_DDR3.BURST_LENGTH">8</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>AXI_ARBITRATION_SCHEME</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C5_DDR3.AXI_ARBITRATION_SCHEME">TDM</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>CAS_LATENCY</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C5_DDR3.CAS_LATENCY">11</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>CAS_WRITE_LATENCY</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C5_DDR3.CAS_WRITE_LATENCY">11</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
      </spirit:parameters>
      <spirit:vendorExtensions>
        <xilinx:busInterfaceInfo>
          <xilinx:enablement>
            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.C5_DDR3" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;DDR3&quot; ">false</xilinx:isEnabled>
          </xilinx:enablement>
        </xilinx:busInterfaceInfo>
      </spirit:vendorExtensions>
    </spirit:busInterface>
    <spirit:busInterface>
      <spirit:name>C5_DDR2</spirit:name>
      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="ddrx" spirit:version="1.0"/>
      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="ddrx_rtl" spirit:version="1.0"/>
      <spirit:master/>
      <spirit:connectionRequired>true</spirit:connectionRequired>
      <spirit:portMaps>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>DQ</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c5_ddr2_dq</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>DQS_P</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c5_ddr2_dqs_p</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>DQS_N</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c5_ddr2_dqs_n</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>ADDR</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c5_ddr2_addr</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>BA</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c5_ddr2_ba</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>RAS_N</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c5_ddr2_ras_n</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>CAS_N</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c5_ddr2_cas_n</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>WE_N</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c5_ddr2_we_n</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>RESET_N</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c5_ddr2_reset_n</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>CK_P</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c5_ddr2_ck_p</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>CK_N</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c5_ddr2_ck_n</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>CKE</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c5_ddr2_cke</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>CS_N</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c5_ddr2_cs_n</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>DM</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c5_ddr2_dm</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>ODT</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c5_ddr2_odt</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>PARITY</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c5_ddr2_parity</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
      </spirit:portMaps>
      <spirit:parameters>
        <spirit:parameter>
          <spirit:name>CAN_DEBUG</spirit:name>
          <spirit:value spirit:format="bool" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C5_DDR2.CAN_DEBUG">false</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>TIMEPERIOD_PS</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C5_DDR2.TIMEPERIOD_PS">1250</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>MEMORY_TYPE</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C5_DDR2.MEMORY_TYPE">COMPONENTS</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>MEMORY_PART</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C5_DDR2.MEMORY_PART"/>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>DATA_WIDTH</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C5_DDR2.DATA_WIDTH">8</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>CS_ENABLED</spirit:name>
          <spirit:value spirit:format="bool" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C5_DDR2.CS_ENABLED">true</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>DATA_MASK_ENABLED</spirit:name>
          <spirit:value spirit:format="bool" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C5_DDR2.DATA_MASK_ENABLED">true</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>SLOT</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C5_DDR2.SLOT">Single</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>CUSTOM_PARTS</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C5_DDR2.CUSTOM_PARTS"/>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>MEM_ADDR_MAP</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C5_DDR2.MEM_ADDR_MAP">ROW_COLUMN_BANK</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>BURST_LENGTH</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C5_DDR2.BURST_LENGTH">8</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>AXI_ARBITRATION_SCHEME</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C5_DDR2.AXI_ARBITRATION_SCHEME">TDM</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>CAS_LATENCY</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C5_DDR2.CAS_LATENCY">11</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>CAS_WRITE_LATENCY</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C5_DDR2.CAS_WRITE_LATENCY">11</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
      </spirit:parameters>
      <spirit:vendorExtensions>
        <xilinx:busInterfaceInfo>
          <xilinx:enablement>
            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.C5_DDR2" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;DDR2&quot; ">false</xilinx:isEnabled>
          </xilinx:enablement>
        </xilinx:busInterfaceInfo>
      </spirit:vendorExtensions>
    </spirit:busInterface>
    <spirit:busInterface>
      <spirit:name>C5_RESET</spirit:name>
      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
      <spirit:master/>
      <spirit:connectionRequired>true</spirit:connectionRequired>
      <spirit:portMaps>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>RST</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c5_ui_clk_sync_rst</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
      </spirit:portMaps>
      <spirit:parameters>
        <spirit:parameter>
          <spirit:name>POLARITY</spirit:name>
          <spirit:value spirit:id="BUSIFPARAM_VALUE.C5_RESET.POLARITY">ACTIVE_HIGH</spirit:value>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>INSERT_VIP</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.C5_RESET.INSERT_VIP">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
      </spirit:parameters>
      <spirit:vendorExtensions>
        <xilinx:busInterfaceInfo>
          <xilinx:enablement>
            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.C5_RESET" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 ">false</xilinx:isEnabled>
          </xilinx:enablement>
        </xilinx:busInterfaceInfo>
      </spirit:vendorExtensions>
    </spirit:busInterface>
    <spirit:busInterface>
      <spirit:name>C5_DDR3_RESET</spirit:name>
      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
      <spirit:master/>
      <spirit:connectionRequired>true</spirit:connectionRequired>
      <spirit:portMaps>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>RST</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c5_ddr3_ui_clk_sync_rst</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
      </spirit:portMaps>
      <spirit:parameters>
        <spirit:parameter>
          <spirit:name>POLARITY</spirit:name>
          <spirit:value spirit:id="BUSIFPARAM_VALUE.C5_DDR3_RESET.POLARITY">ACTIVE_HIGH</spirit:value>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>INSERT_VIP</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.C5_DDR3_RESET.INSERT_VIP">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
      </spirit:parameters>
      <spirit:vendorExtensions>
        <xilinx:busInterfaceInfo>
          <xilinx:enablement>
            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.C5_DDR3_RESET" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 ">false</xilinx:isEnabled>
          </xilinx:enablement>
        </xilinx:busInterfaceInfo>
      </spirit:vendorExtensions>
    </spirit:busInterface>
    <spirit:busInterface>
      <spirit:name>C5_DDR2_RESET</spirit:name>
      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
      <spirit:master/>
      <spirit:connectionRequired>true</spirit:connectionRequired>
      <spirit:portMaps>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>RST</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c5_ddr2_ui_clk_sync_rst</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
      </spirit:portMaps>
      <spirit:parameters>
        <spirit:parameter>
          <spirit:name>POLARITY</spirit:name>
          <spirit:value spirit:id="BUSIFPARAM_VALUE.C5_DDR2_RESET.POLARITY">ACTIVE_HIGH</spirit:value>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>INSERT_VIP</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.C5_DDR2_RESET.INSERT_VIP">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
      </spirit:parameters>
      <spirit:vendorExtensions>
        <xilinx:busInterfaceInfo>
          <xilinx:enablement>
            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.C5_DDR2_RESET" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 ">false</xilinx:isEnabled>
          </xilinx:enablement>
        </xilinx:busInterfaceInfo>
      </spirit:vendorExtensions>
    </spirit:busInterface>
    <spirit:busInterface>
      <spirit:name>C5_LPDDR2_RESET</spirit:name>
      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
      <spirit:master/>
      <spirit:connectionRequired>true</spirit:connectionRequired>
      <spirit:portMaps>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>RST</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c5_lpddr2_ui_clk_sync_rst</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
      </spirit:portMaps>
      <spirit:parameters>
        <spirit:parameter>
          <spirit:name>POLARITY</spirit:name>
          <spirit:value spirit:id="BUSIFPARAM_VALUE.C5_LPDDR2_RESET.POLARITY">ACTIVE_HIGH</spirit:value>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>INSERT_VIP</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.C5_LPDDR2_RESET.INSERT_VIP">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
      </spirit:parameters>
      <spirit:vendorExtensions>
        <xilinx:busInterfaceInfo>
          <xilinx:enablement>
            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.C5_LPDDR2_RESET" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 ">false</xilinx:isEnabled>
          </xilinx:enablement>
        </xilinx:busInterfaceInfo>
      </spirit:vendorExtensions>
    </spirit:busInterface>
    <spirit:busInterface>
      <spirit:name>C5_QDRIIP_RESET</spirit:name>
      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
      <spirit:master/>
      <spirit:connectionRequired>true</spirit:connectionRequired>
      <spirit:portMaps>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>RST</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c5_qdriip_ui_clk_sync_rst</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
      </spirit:portMaps>
      <spirit:parameters>
        <spirit:parameter>
          <spirit:name>POLARITY</spirit:name>
          <spirit:value spirit:id="BUSIFPARAM_VALUE.C5_QDRIIP_RESET.POLARITY">ACTIVE_HIGH</spirit:value>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>INSERT_VIP</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.C5_QDRIIP_RESET.INSERT_VIP">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
      </spirit:parameters>
      <spirit:vendorExtensions>
        <xilinx:busInterfaceInfo>
          <xilinx:enablement>
            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.C5_QDRIIP_RESET" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 ">false</xilinx:isEnabled>
          </xilinx:enablement>
        </xilinx:busInterfaceInfo>
      </spirit:vendorExtensions>
    </spirit:busInterface>
    <spirit:busInterface>
      <spirit:name>C5_RLDII_RESET</spirit:name>
      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
      <spirit:master/>
      <spirit:connectionRequired>true</spirit:connectionRequired>
      <spirit:portMaps>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>RST</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c5_rldii_ui_clk_sync_rst</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
      </spirit:portMaps>
      <spirit:parameters>
        <spirit:parameter>
          <spirit:name>POLARITY</spirit:name>
          <spirit:value spirit:id="BUSIFPARAM_VALUE.C5_RLDII_RESET.POLARITY">ACTIVE_HIGH</spirit:value>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>INSERT_VIP</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.C5_RLDII_RESET.INSERT_VIP">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
      </spirit:parameters>
      <spirit:vendorExtensions>
        <xilinx:busInterfaceInfo>
          <xilinx:enablement>
            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.C5_RLDII_RESET" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 ">false</xilinx:isEnabled>
          </xilinx:enablement>
        </xilinx:busInterfaceInfo>
      </spirit:vendorExtensions>
    </spirit:busInterface>
    <spirit:busInterface>
      <spirit:name>C5_RLDIII_RESET</spirit:name>
      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
      <spirit:master/>
      <spirit:connectionRequired>true</spirit:connectionRequired>
      <spirit:portMaps>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>RST</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c5_rldiii_ui_clk_sync_rst</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
      </spirit:portMaps>
      <spirit:parameters>
        <spirit:parameter>
          <spirit:name>POLARITY</spirit:name>
          <spirit:value spirit:id="BUSIFPARAM_VALUE.C5_RLDIII_RESET.POLARITY">ACTIVE_HIGH</spirit:value>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>INSERT_VIP</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.C5_RLDIII_RESET.INSERT_VIP">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
      </spirit:parameters>
      <spirit:vendorExtensions>
        <xilinx:busInterfaceInfo>
          <xilinx:enablement>
            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.C5_RLDIII_RESET" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 ">false</xilinx:isEnabled>
          </xilinx:enablement>
        </xilinx:busInterfaceInfo>
      </spirit:vendorExtensions>
    </spirit:busInterface>
    <spirit:busInterface>
      <spirit:name>C5_CLOCK</spirit:name>
      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
      <spirit:master/>
      <spirit:connectionRequired>true</spirit:connectionRequired>
      <spirit:portMaps>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>CLK</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c5_ui_clk</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
      </spirit:portMaps>
      <spirit:parameters>
        <spirit:parameter>
          <spirit:name>FREQ_HZ</spirit:name>
          <spirit:value spirit:format="float" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.C5_CLOCK.FREQ_HZ" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C5_FREQ_HZ&apos;))">100</spirit:value>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>ASSOCIATED_BUSIF</spirit:name>
          <spirit:value spirit:id="BUSIFPARAM_VALUE.C5_CLOCK.ASSOCIATED_BUSIF">S5_AXI:S5_AXI_CTRL</spirit:value>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>ASSOCIATED_RESET</spirit:name>
          <spirit:value spirit:id="BUSIFPARAM_VALUE.C5_CLOCK.ASSOCIATED_RESET">c5_aresetn:c5_ui_clk_sync_rst</spirit:value>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>PHASE</spirit:name>
          <spirit:value spirit:format="float" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.C5_CLOCK.PHASE" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C5_PHASE&apos;))">0</spirit:value>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>CLK_DOMAIN</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C5_CLOCK.CLK_DOMAIN"/>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>INSERT_VIP</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.C5_CLOCK.INSERT_VIP">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
      </spirit:parameters>
      <spirit:vendorExtensions>
        <xilinx:busInterfaceInfo>
          <xilinx:enablement>
            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.C5_CLOCK" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 ">false</xilinx:isEnabled>
          </xilinx:enablement>
        </xilinx:busInterfaceInfo>
      </spirit:vendorExtensions>
    </spirit:busInterface>
    <spirit:busInterface>
      <spirit:name>C5_MMCM_CLKOUT0</spirit:name>
      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
      <spirit:master/>
      <spirit:connectionRequired>true</spirit:connectionRequired>
      <spirit:portMaps>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>CLK</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c5_ui_addn_clk_0</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
      </spirit:portMaps>
      <spirit:parameters>
        <spirit:parameter>
          <spirit:name>FREQ_HZ</spirit:name>
          <spirit:value spirit:format="float" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.C5_MMCM_CLKOUT0.FREQ_HZ" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MMCM_CLKOUT0_FREQ&apos;))">10</spirit:value>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>ASSOCIATED_ASYNC_RESET</spirit:name>
          <spirit:value spirit:id="BUSIFPARAM_VALUE.C5_MMCM_CLKOUT0.ASSOCIATED_ASYNC_RESET">c5_aresetn</spirit:value>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>PHASE</spirit:name>
          <spirit:value spirit:format="float" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.C5_MMCM_CLKOUT0.PHASE" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C5_PHASE&apos;))">0</spirit:value>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>CLK_DOMAIN</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C5_MMCM_CLKOUT0.CLK_DOMAIN"/>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>ASSOCIATED_BUSIF</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C5_MMCM_CLKOUT0.ASSOCIATED_BUSIF"/>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>ASSOCIATED_RESET</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C5_MMCM_CLKOUT0.ASSOCIATED_RESET"/>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>INSERT_VIP</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.C5_MMCM_CLKOUT0.INSERT_VIP">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
      </spirit:parameters>
      <spirit:vendorExtensions>
        <xilinx:busInterfaceInfo>
          <xilinx:enablement>
            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.C5_MMCM_CLKOUT0" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 ">false</xilinx:isEnabled>
          </xilinx:enablement>
        </xilinx:busInterfaceInfo>
      </spirit:vendorExtensions>
    </spirit:busInterface>
    <spirit:busInterface>
      <spirit:name>C5_MMCM_CLKOUT1</spirit:name>
      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
      <spirit:master/>
      <spirit:connectionRequired>true</spirit:connectionRequired>
      <spirit:portMaps>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>CLK</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c5_ui_addn_clk_1</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
      </spirit:portMaps>
      <spirit:parameters>
        <spirit:parameter>
          <spirit:name>FREQ_HZ</spirit:name>
          <spirit:value spirit:format="float" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.C5_MMCM_CLKOUT1.FREQ_HZ" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MMCM_CLKOUT1_FREQ&apos;))">10</spirit:value>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>ASSOCIATED_ASYNC_RESET</spirit:name>
          <spirit:value spirit:id="BUSIFPARAM_VALUE.C5_MMCM_CLKOUT1.ASSOCIATED_ASYNC_RESET">c5_aresetn</spirit:value>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>PHASE</spirit:name>
          <spirit:value spirit:format="float" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.C5_MMCM_CLKOUT1.PHASE" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C5_PHASE&apos;))">0</spirit:value>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>CLK_DOMAIN</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C5_MMCM_CLKOUT1.CLK_DOMAIN"/>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>ASSOCIATED_BUSIF</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C5_MMCM_CLKOUT1.ASSOCIATED_BUSIF"/>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>ASSOCIATED_RESET</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C5_MMCM_CLKOUT1.ASSOCIATED_RESET"/>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>INSERT_VIP</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.C5_MMCM_CLKOUT1.INSERT_VIP">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
      </spirit:parameters>
      <spirit:vendorExtensions>
        <xilinx:busInterfaceInfo>
          <xilinx:enablement>
            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.C5_MMCM_CLKOUT1" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 ">false</xilinx:isEnabled>
          </xilinx:enablement>
        </xilinx:busInterfaceInfo>
      </spirit:vendorExtensions>
    </spirit:busInterface>
    <spirit:busInterface>
      <spirit:name>C5_MMCM_CLKOUT2</spirit:name>
      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
      <spirit:master/>
      <spirit:connectionRequired>true</spirit:connectionRequired>
      <spirit:portMaps>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>CLK</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c5_ui_addn_clk_2</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
      </spirit:portMaps>
      <spirit:parameters>
        <spirit:parameter>
          <spirit:name>FREQ_HZ</spirit:name>
          <spirit:value spirit:format="float" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.C5_MMCM_CLKOUT2.FREQ_HZ" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MMCM_CLKOUT2_FREQ&apos;))">10</spirit:value>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>ASSOCIATED_ASYNC_RESET</spirit:name>
          <spirit:value spirit:id="BUSIFPARAM_VALUE.C5_MMCM_CLKOUT2.ASSOCIATED_ASYNC_RESET">c5_aresetn</spirit:value>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>PHASE</spirit:name>
          <spirit:value spirit:format="float" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.C5_MMCM_CLKOUT2.PHASE" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C5_PHASE&apos;))">0</spirit:value>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>CLK_DOMAIN</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C5_MMCM_CLKOUT2.CLK_DOMAIN"/>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>ASSOCIATED_BUSIF</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C5_MMCM_CLKOUT2.ASSOCIATED_BUSIF"/>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>ASSOCIATED_RESET</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C5_MMCM_CLKOUT2.ASSOCIATED_RESET"/>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>INSERT_VIP</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.C5_MMCM_CLKOUT2.INSERT_VIP">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
      </spirit:parameters>
      <spirit:vendorExtensions>
        <xilinx:busInterfaceInfo>
          <xilinx:enablement>
            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.C5_MMCM_CLKOUT2" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 ">false</xilinx:isEnabled>
          </xilinx:enablement>
        </xilinx:busInterfaceInfo>
      </spirit:vendorExtensions>
    </spirit:busInterface>
    <spirit:busInterface>
      <spirit:name>C5_MMCM_CLKOUT3</spirit:name>
      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
      <spirit:master/>
      <spirit:connectionRequired>true</spirit:connectionRequired>
      <spirit:portMaps>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>CLK</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c5_ui_addn_clk_3</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
      </spirit:portMaps>
      <spirit:parameters>
        <spirit:parameter>
          <spirit:name>FREQ_HZ</spirit:name>
          <spirit:value spirit:format="float" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.C5_MMCM_CLKOUT3.FREQ_HZ" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MMCM_CLKOUT3_FREQ&apos;))">10</spirit:value>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>ASSOCIATED_ASYNC_RESET</spirit:name>
          <spirit:value spirit:id="BUSIFPARAM_VALUE.C5_MMCM_CLKOUT3.ASSOCIATED_ASYNC_RESET">c5_aresetn</spirit:value>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>PHASE</spirit:name>
          <spirit:value spirit:format="float" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.C5_MMCM_CLKOUT3.PHASE" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C5_PHASE&apos;))">0</spirit:value>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>CLK_DOMAIN</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C5_MMCM_CLKOUT3.CLK_DOMAIN"/>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>ASSOCIATED_BUSIF</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C5_MMCM_CLKOUT3.ASSOCIATED_BUSIF"/>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>ASSOCIATED_RESET</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C5_MMCM_CLKOUT3.ASSOCIATED_RESET"/>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>INSERT_VIP</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.C5_MMCM_CLKOUT3.INSERT_VIP">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
      </spirit:parameters>
      <spirit:vendorExtensions>
        <xilinx:busInterfaceInfo>
          <xilinx:enablement>
            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.C5_MMCM_CLKOUT3" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 ">false</xilinx:isEnabled>
          </xilinx:enablement>
        </xilinx:busInterfaceInfo>
      </spirit:vendorExtensions>
    </spirit:busInterface>
    <spirit:busInterface>
      <spirit:name>C5_MMCM_CLKOUT4</spirit:name>
      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
      <spirit:master/>
      <spirit:connectionRequired>true</spirit:connectionRequired>
      <spirit:portMaps>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>CLK</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c5_ui_addn_clk_4</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
      </spirit:portMaps>
      <spirit:parameters>
        <spirit:parameter>
          <spirit:name>FREQ_HZ</spirit:name>
          <spirit:value spirit:format="float" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.C5_MMCM_CLKOUT4.FREQ_HZ" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MMCM_CLKOUT4_FREQ&apos;))">10</spirit:value>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>ASSOCIATED_ASYNC_RESET</spirit:name>
          <spirit:value spirit:id="BUSIFPARAM_VALUE.C5_MMCM_CLKOUT4.ASSOCIATED_ASYNC_RESET">c5_aresetn</spirit:value>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>PHASE</spirit:name>
          <spirit:value spirit:format="float" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.C5_MMCM_CLKOUT4.PHASE" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C5_PHASE&apos;))">0</spirit:value>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>CLK_DOMAIN</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C5_MMCM_CLKOUT4.CLK_DOMAIN"/>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>ASSOCIATED_BUSIF</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C5_MMCM_CLKOUT4.ASSOCIATED_BUSIF"/>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>ASSOCIATED_RESET</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C5_MMCM_CLKOUT4.ASSOCIATED_RESET"/>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>INSERT_VIP</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.C5_MMCM_CLKOUT4.INSERT_VIP">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
      </spirit:parameters>
      <spirit:vendorExtensions>
        <xilinx:busInterfaceInfo>
          <xilinx:enablement>
            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.C5_MMCM_CLKOUT4" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 ">false</xilinx:isEnabled>
          </xilinx:enablement>
        </xilinx:busInterfaceInfo>
      </spirit:vendorExtensions>
    </spirit:busInterface>
    <spirit:busInterface>
      <spirit:name>S5_AXI_CTRL</spirit:name>
      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm" spirit:version="1.0"/>
      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm_rtl" spirit:version="1.0"/>
      <spirit:slave>
        <spirit:memoryMapRef spirit:memoryMapRef="c5_s_axi_ctrl_memmap"/>
      </spirit:slave>
      <spirit:connectionRequired>true</spirit:connectionRequired>
      <spirit:portMaps>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>AWVALID</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c5_s_axi_ctrl_awvalid</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>AWREADY</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c5_s_axi_ctrl_awready</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>AWADDR</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c5_s_axi_ctrl_awaddr</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>WVALID</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c5_s_axi_ctrl_wvalid</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>WREADY</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c5_s_axi_ctrl_wready</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>WDATA</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c5_s_axi_ctrl_wdata</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>BVALID</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c5_s_axi_ctrl_bvalid</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>BREADY</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c5_s_axi_ctrl_bready</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>BRESP</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c5_s_axi_ctrl_bresp</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>ARVALID</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c5_s_axi_ctrl_arvalid</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>ARREADY</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c5_s_axi_ctrl_arready</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>ARADDR</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c5_s_axi_ctrl_araddr</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>RVALID</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c5_s_axi_ctrl_rvalid</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>RREADY</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c5_s_axi_ctrl_rready</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>RDATA</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c5_s_axi_ctrl_rdata</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>RRESP</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c5_s_axi_ctrl_rresp</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
      </spirit:portMaps>
      <spirit:parameters>
        <spirit:parameter>
          <spirit:name>FREQ_HZ</spirit:name>
          <spirit:value spirit:format="float" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.S5_AXI_CTRL.FREQ_HZ" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C5_FREQ_HZ&apos;))">100</spirit:value>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>DATA_WIDTH</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S5_AXI_CTRL.DATA_WIDTH">1</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>PROTOCOL</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S5_AXI_CTRL.PROTOCOL">AXI4LITE</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>ID_WIDTH</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S5_AXI_CTRL.ID_WIDTH">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>ADDR_WIDTH</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S5_AXI_CTRL.ADDR_WIDTH">1</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>AWUSER_WIDTH</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S5_AXI_CTRL.AWUSER_WIDTH">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>ARUSER_WIDTH</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S5_AXI_CTRL.ARUSER_WIDTH">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>WUSER_WIDTH</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S5_AXI_CTRL.WUSER_WIDTH">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>RUSER_WIDTH</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S5_AXI_CTRL.RUSER_WIDTH">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>BUSER_WIDTH</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S5_AXI_CTRL.BUSER_WIDTH">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>READ_WRITE_MODE</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S5_AXI_CTRL.READ_WRITE_MODE">READ_WRITE</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>HAS_BURST</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S5_AXI_CTRL.HAS_BURST">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>HAS_LOCK</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S5_AXI_CTRL.HAS_LOCK">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>HAS_PROT</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S5_AXI_CTRL.HAS_PROT">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>HAS_CACHE</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S5_AXI_CTRL.HAS_CACHE">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>HAS_QOS</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S5_AXI_CTRL.HAS_QOS">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>HAS_REGION</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S5_AXI_CTRL.HAS_REGION">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>HAS_WSTRB</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S5_AXI_CTRL.HAS_WSTRB">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>HAS_BRESP</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S5_AXI_CTRL.HAS_BRESP">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>HAS_RRESP</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S5_AXI_CTRL.HAS_RRESP">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>SUPPORTS_NARROW_BURST</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S5_AXI_CTRL.SUPPORTS_NARROW_BURST">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>NUM_READ_OUTSTANDING</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S5_AXI_CTRL.NUM_READ_OUTSTANDING">1</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>NUM_WRITE_OUTSTANDING</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S5_AXI_CTRL.NUM_WRITE_OUTSTANDING">1</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>MAX_BURST_LENGTH</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S5_AXI_CTRL.MAX_BURST_LENGTH">1</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>PHASE</spirit:name>
          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S5_AXI_CTRL.PHASE">0.000</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>CLK_DOMAIN</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S5_AXI_CTRL.CLK_DOMAIN"/>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>NUM_READ_THREADS</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S5_AXI_CTRL.NUM_READ_THREADS">1</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>NUM_WRITE_THREADS</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S5_AXI_CTRL.NUM_WRITE_THREADS">1</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>RUSER_BITS_PER_BYTE</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S5_AXI_CTRL.RUSER_BITS_PER_BYTE">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>WUSER_BITS_PER_BYTE</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S5_AXI_CTRL.WUSER_BITS_PER_BYTE">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>INSERT_VIP</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.S5_AXI_CTRL.INSERT_VIP">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
      </spirit:parameters>
      <spirit:vendorExtensions>
        <xilinx:busInterfaceInfo>
          <xilinx:enablement>
            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.S5_AXI_CTRL" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_USE_AXI&apos;)) = 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_ECC&apos;)) = &quot;ON&quot; ) ">false</xilinx:isEnabled>
          </xilinx:enablement>
        </xilinx:busInterfaceInfo>
      </spirit:vendorExtensions>
    </spirit:busInterface>
    <spirit:busInterface>
      <spirit:name>S5_AXI</spirit:name>
      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm" spirit:version="1.0"/>
      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm_rtl" spirit:version="1.0"/>
      <spirit:slave>
        <spirit:memoryMapRef spirit:memoryMapRef="c5_memmap"/>
      </spirit:slave>
      <spirit:connectionRequired>true</spirit:connectionRequired>
      <spirit:portMaps>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>AWID</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c5_s_axi_awid</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>AWADDR</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c5_s_axi_awaddr</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>AWLEN</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c5_s_axi_awlen</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>AWSIZE</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c5_s_axi_awsize</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>AWBURST</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c5_s_axi_awburst</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>AWLOCK</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c5_s_axi_awlock</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>AWCACHE</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c5_s_axi_awcache</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>AWPROT</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c5_s_axi_awprot</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>AWQOS</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c5_s_axi_awqos</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>AWVALID</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c5_s_axi_awvalid</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>AWREADY</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c5_s_axi_awready</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>WDATA</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c5_s_axi_wdata</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>WSTRB</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c5_s_axi_wstrb</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>WLAST</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c5_s_axi_wlast</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>WVALID</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c5_s_axi_wvalid</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>WREADY</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c5_s_axi_wready</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>BREADY</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c5_s_axi_bready</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>BID</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c5_s_axi_bid</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>BRESP</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c5_s_axi_bresp</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>BVALID</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c5_s_axi_bvalid</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>ARID</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c5_s_axi_arid</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>ARADDR</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c5_s_axi_araddr</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>ARLEN</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c5_s_axi_arlen</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>ARSIZE</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c5_s_axi_arsize</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>ARBURST</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c5_s_axi_arburst</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>ARLOCK</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c5_s_axi_arlock</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>ARCACHE</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c5_s_axi_arcache</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>ARPROT</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c5_s_axi_arprot</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>ARQOS</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c5_s_axi_arqos</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>ARVALID</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c5_s_axi_arvalid</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>ARREADY</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c5_s_axi_arready</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>RREADY</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c5_s_axi_rready</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>RID</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c5_s_axi_rid</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>RDATA</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c5_s_axi_rdata</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>RRESP</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c5_s_axi_rresp</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>RLAST</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c5_s_axi_rlast</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>RVALID</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c5_s_axi_rvalid</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
      </spirit:portMaps>
      <spirit:parameters>
        <spirit:parameter>
          <spirit:name>FREQ_HZ</spirit:name>
          <spirit:value spirit:format="float" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.S5_AXI.FREQ_HZ" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C5_FREQ_HZ&apos;))">100</spirit:value>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>DATA_WIDTH</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S5_AXI.DATA_WIDTH">1</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>PROTOCOL</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S5_AXI.PROTOCOL">AXI4LITE</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>ID_WIDTH</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S5_AXI.ID_WIDTH">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>ADDR_WIDTH</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S5_AXI.ADDR_WIDTH">1</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>AWUSER_WIDTH</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S5_AXI.AWUSER_WIDTH">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>ARUSER_WIDTH</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S5_AXI.ARUSER_WIDTH">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>WUSER_WIDTH</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S5_AXI.WUSER_WIDTH">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>RUSER_WIDTH</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S5_AXI.RUSER_WIDTH">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>BUSER_WIDTH</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S5_AXI.BUSER_WIDTH">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>READ_WRITE_MODE</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S5_AXI.READ_WRITE_MODE">READ_WRITE</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>HAS_BURST</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S5_AXI.HAS_BURST">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>HAS_LOCK</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S5_AXI.HAS_LOCK">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>HAS_PROT</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S5_AXI.HAS_PROT">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>HAS_CACHE</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S5_AXI.HAS_CACHE">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>HAS_QOS</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S5_AXI.HAS_QOS">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>HAS_REGION</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S5_AXI.HAS_REGION">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>HAS_WSTRB</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S5_AXI.HAS_WSTRB">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>HAS_BRESP</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S5_AXI.HAS_BRESP">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>HAS_RRESP</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S5_AXI.HAS_RRESP">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>SUPPORTS_NARROW_BURST</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S5_AXI.SUPPORTS_NARROW_BURST">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>NUM_READ_OUTSTANDING</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S5_AXI.NUM_READ_OUTSTANDING">1</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>NUM_WRITE_OUTSTANDING</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S5_AXI.NUM_WRITE_OUTSTANDING">1</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>MAX_BURST_LENGTH</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S5_AXI.MAX_BURST_LENGTH">1</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>PHASE</spirit:name>
          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S5_AXI.PHASE">0.000</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>CLK_DOMAIN</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S5_AXI.CLK_DOMAIN"/>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>NUM_READ_THREADS</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S5_AXI.NUM_READ_THREADS">1</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>NUM_WRITE_THREADS</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S5_AXI.NUM_WRITE_THREADS">1</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>RUSER_BITS_PER_BYTE</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S5_AXI.RUSER_BITS_PER_BYTE">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>WUSER_BITS_PER_BYTE</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S5_AXI.WUSER_BITS_PER_BYTE">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>INSERT_VIP</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.S5_AXI.INSERT_VIP">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
      </spirit:parameters>
      <spirit:vendorExtensions>
        <xilinx:busInterfaceInfo>
          <xilinx:enablement>
            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.S5_AXI" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
          </xilinx:enablement>
        </xilinx:busInterfaceInfo>
      </spirit:vendorExtensions>
    </spirit:busInterface>
    <spirit:busInterface>
      <spirit:name>C5_SYS_CLK</spirit:name>
      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="diff_clock" spirit:version="1.0"/>
      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="diff_clock_rtl" spirit:version="1.0"/>
      <spirit:slave/>
      <spirit:connectionRequired>true</spirit:connectionRequired>
      <spirit:portMaps>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>CLK_P</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c5_sys_clk_p</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>CLK_N</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c5_sys_clk_n</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
      </spirit:portMaps>
      <spirit:parameters>
        <spirit:parameter>
          <spirit:name>CAN_DEBUG</spirit:name>
          <spirit:value spirit:format="bool" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C5_SYS_CLK.CAN_DEBUG">false</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>FREQ_HZ</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C5_SYS_CLK.FREQ_HZ">100000000</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
      </spirit:parameters>
      <spirit:vendorExtensions>
        <xilinx:busInterfaceInfo>
          <xilinx:enablement>
            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.C5_SYS_CLK" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_SYSCLK_TYPE&apos;)) = &quot;DIFF&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_IS_CLK_SHARED&apos;)) = &quot;FALSE&quot; ">false</xilinx:isEnabled>
          </xilinx:enablement>
        </xilinx:busInterfaceInfo>
      </spirit:vendorExtensions>
    </spirit:busInterface>
    <spirit:busInterface>
      <spirit:name>C5_SYS_CLK_I</spirit:name>
      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
      <spirit:slave/>
      <spirit:connectionRequired>true</spirit:connectionRequired>
      <spirit:portMaps>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>CLK</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c5_sys_clk_i</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
      </spirit:portMaps>
      <spirit:parameters>
        <spirit:parameter>
          <spirit:name>FREQ_HZ</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C5_SYS_CLK_I.FREQ_HZ">100000000</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>PHASE</spirit:name>
          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C5_SYS_CLK_I.PHASE">0.000</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>CLK_DOMAIN</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C5_SYS_CLK_I.CLK_DOMAIN"/>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>ASSOCIATED_BUSIF</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C5_SYS_CLK_I.ASSOCIATED_BUSIF"/>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>ASSOCIATED_RESET</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C5_SYS_CLK_I.ASSOCIATED_RESET"/>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>INSERT_VIP</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.C5_SYS_CLK_I.INSERT_VIP">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
      </spirit:parameters>
      <spirit:vendorExtensions>
        <xilinx:busInterfaceInfo>
          <xilinx:enablement>
            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.C5_SYS_CLK_I" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_SYSCLK_TYPE&apos;)) != &quot;DIFF&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_IS_CLK_SHARED&apos;)) = &quot;FALSE&quot; ">false</xilinx:isEnabled>
          </xilinx:enablement>
        </xilinx:busInterfaceInfo>
      </spirit:vendorExtensions>
    </spirit:busInterface>
    <spirit:busInterface>
      <spirit:name>C5_ARESETN</spirit:name>
      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
      <spirit:slave/>
      <spirit:connectionRequired>true</spirit:connectionRequired>
      <spirit:portMaps>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>ARESETN</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c5_aresetn</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
      </spirit:portMaps>
      <spirit:parameters>
        <spirit:parameter>
          <spirit:name>POLARITY</spirit:name>
          <spirit:value spirit:id="BUSIFPARAM_VALUE.C5_ARESETN.POLARITY">ACTIVE_LOW</spirit:value>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>INSERT_VIP</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.C5_ARESETN.INSERT_VIP">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
      </spirit:parameters>
    </spirit:busInterface>
    <spirit:busInterface>
      <spirit:name>C6_DDR3</spirit:name>
      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="ddrx" spirit:version="1.0"/>
      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="ddrx_rtl" spirit:version="1.0"/>
      <spirit:master/>
      <spirit:connectionRequired>true</spirit:connectionRequired>
      <spirit:portMaps>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>DQ</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c6_ddr3_dq</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>DQS_P</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c6_ddr3_dqs_p</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>DQS_N</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c6_ddr3_dqs_n</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>ADDR</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c6_ddr3_addr</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>BA</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c6_ddr3_ba</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>RAS_N</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c6_ddr3_ras_n</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>CAS_N</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c6_ddr3_cas_n</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>WE_N</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c6_ddr3_we_n</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>RESET_N</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c6_ddr3_reset_n</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>CK_P</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c6_ddr3_ck_p</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>CK_N</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c6_ddr3_ck_n</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>CKE</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c6_ddr3_cke</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>CS_N</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c6_ddr3_cs_n</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>DM</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c6_ddr3_dm</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>ODT</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c6_ddr3_odt</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>PARITY</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c6_ddr3_parity</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
      </spirit:portMaps>
      <spirit:parameters>
        <spirit:parameter>
          <spirit:name>CAN_DEBUG</spirit:name>
          <spirit:value spirit:format="bool" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C6_DDR3.CAN_DEBUG">false</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>TIMEPERIOD_PS</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C6_DDR3.TIMEPERIOD_PS">1250</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>MEMORY_TYPE</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C6_DDR3.MEMORY_TYPE">COMPONENTS</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>MEMORY_PART</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C6_DDR3.MEMORY_PART"/>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>DATA_WIDTH</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C6_DDR3.DATA_WIDTH">8</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>CS_ENABLED</spirit:name>
          <spirit:value spirit:format="bool" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C6_DDR3.CS_ENABLED">true</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>DATA_MASK_ENABLED</spirit:name>
          <spirit:value spirit:format="bool" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C6_DDR3.DATA_MASK_ENABLED">true</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>SLOT</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C6_DDR3.SLOT">Single</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>CUSTOM_PARTS</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C6_DDR3.CUSTOM_PARTS"/>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>MEM_ADDR_MAP</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C6_DDR3.MEM_ADDR_MAP">ROW_COLUMN_BANK</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>BURST_LENGTH</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C6_DDR3.BURST_LENGTH">8</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>AXI_ARBITRATION_SCHEME</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C6_DDR3.AXI_ARBITRATION_SCHEME">TDM</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>CAS_LATENCY</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C6_DDR3.CAS_LATENCY">11</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>CAS_WRITE_LATENCY</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C6_DDR3.CAS_WRITE_LATENCY">11</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
      </spirit:parameters>
      <spirit:vendorExtensions>
        <xilinx:busInterfaceInfo>
          <xilinx:enablement>
            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.C6_DDR3" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;DDR3&quot; ">false</xilinx:isEnabled>
          </xilinx:enablement>
        </xilinx:busInterfaceInfo>
      </spirit:vendorExtensions>
    </spirit:busInterface>
    <spirit:busInterface>
      <spirit:name>C6_DDR2</spirit:name>
      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="ddrx" spirit:version="1.0"/>
      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="ddrx_rtl" spirit:version="1.0"/>
      <spirit:master/>
      <spirit:connectionRequired>true</spirit:connectionRequired>
      <spirit:portMaps>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>DQ</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c6_ddr2_dq</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>DQS_P</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c6_ddr2_dqs_p</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>DQS_N</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c6_ddr2_dqs_n</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>ADDR</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c6_ddr2_addr</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>BA</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c6_ddr2_ba</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>RAS_N</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c6_ddr2_ras_n</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>CAS_N</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c6_ddr2_cas_n</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>WE_N</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c6_ddr2_we_n</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>RESET_N</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c6_ddr2_reset_n</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>CK_P</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c6_ddr2_ck_p</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>CK_N</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c6_ddr2_ck_n</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>CKE</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c6_ddr2_cke</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>CS_N</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c6_ddr2_cs_n</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>DM</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c6_ddr2_dm</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>ODT</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c6_ddr2_odt</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>PARITY</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c6_ddr2_parity</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
      </spirit:portMaps>
      <spirit:parameters>
        <spirit:parameter>
          <spirit:name>CAN_DEBUG</spirit:name>
          <spirit:value spirit:format="bool" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C6_DDR2.CAN_DEBUG">false</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>TIMEPERIOD_PS</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C6_DDR2.TIMEPERIOD_PS">1250</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>MEMORY_TYPE</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C6_DDR2.MEMORY_TYPE">COMPONENTS</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>MEMORY_PART</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C6_DDR2.MEMORY_PART"/>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>DATA_WIDTH</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C6_DDR2.DATA_WIDTH">8</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>CS_ENABLED</spirit:name>
          <spirit:value spirit:format="bool" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C6_DDR2.CS_ENABLED">true</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>DATA_MASK_ENABLED</spirit:name>
          <spirit:value spirit:format="bool" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C6_DDR2.DATA_MASK_ENABLED">true</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>SLOT</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C6_DDR2.SLOT">Single</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>CUSTOM_PARTS</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C6_DDR2.CUSTOM_PARTS"/>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>MEM_ADDR_MAP</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C6_DDR2.MEM_ADDR_MAP">ROW_COLUMN_BANK</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>BURST_LENGTH</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C6_DDR2.BURST_LENGTH">8</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>AXI_ARBITRATION_SCHEME</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C6_DDR2.AXI_ARBITRATION_SCHEME">TDM</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>CAS_LATENCY</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C6_DDR2.CAS_LATENCY">11</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>CAS_WRITE_LATENCY</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C6_DDR2.CAS_WRITE_LATENCY">11</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
      </spirit:parameters>
      <spirit:vendorExtensions>
        <xilinx:busInterfaceInfo>
          <xilinx:enablement>
            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.C6_DDR2" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;DDR2&quot; ">false</xilinx:isEnabled>
          </xilinx:enablement>
        </xilinx:busInterfaceInfo>
      </spirit:vendorExtensions>
    </spirit:busInterface>
    <spirit:busInterface>
      <spirit:name>C6_RESET</spirit:name>
      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
      <spirit:master/>
      <spirit:connectionRequired>true</spirit:connectionRequired>
      <spirit:portMaps>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>RST</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c6_ui_clk_sync_rst</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
      </spirit:portMaps>
      <spirit:parameters>
        <spirit:parameter>
          <spirit:name>POLARITY</spirit:name>
          <spirit:value spirit:id="BUSIFPARAM_VALUE.C6_RESET.POLARITY">ACTIVE_HIGH</spirit:value>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>INSERT_VIP</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.C6_RESET.INSERT_VIP">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
      </spirit:parameters>
      <spirit:vendorExtensions>
        <xilinx:busInterfaceInfo>
          <xilinx:enablement>
            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.C6_RESET" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 ">false</xilinx:isEnabled>
          </xilinx:enablement>
        </xilinx:busInterfaceInfo>
      </spirit:vendorExtensions>
    </spirit:busInterface>
    <spirit:busInterface>
      <spirit:name>C6_DDR3_RESET</spirit:name>
      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
      <spirit:master/>
      <spirit:connectionRequired>true</spirit:connectionRequired>
      <spirit:portMaps>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>RST</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c6_ddr3_ui_clk_sync_rst</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
      </spirit:portMaps>
      <spirit:parameters>
        <spirit:parameter>
          <spirit:name>POLARITY</spirit:name>
          <spirit:value spirit:id="BUSIFPARAM_VALUE.C6_DDR3_RESET.POLARITY">ACTIVE_HIGH</spirit:value>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>INSERT_VIP</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.C6_DDR3_RESET.INSERT_VIP">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
      </spirit:parameters>
      <spirit:vendorExtensions>
        <xilinx:busInterfaceInfo>
          <xilinx:enablement>
            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.C6_DDR3_RESET" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 ">false</xilinx:isEnabled>
          </xilinx:enablement>
        </xilinx:busInterfaceInfo>
      </spirit:vendorExtensions>
    </spirit:busInterface>
    <spirit:busInterface>
      <spirit:name>C6_DDR2_RESET</spirit:name>
      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
      <spirit:master/>
      <spirit:connectionRequired>true</spirit:connectionRequired>
      <spirit:portMaps>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>RST</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c6_ddr2_ui_clk_sync_rst</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
      </spirit:portMaps>
      <spirit:parameters>
        <spirit:parameter>
          <spirit:name>POLARITY</spirit:name>
          <spirit:value spirit:id="BUSIFPARAM_VALUE.C6_DDR2_RESET.POLARITY">ACTIVE_HIGH</spirit:value>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>INSERT_VIP</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.C6_DDR2_RESET.INSERT_VIP">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
      </spirit:parameters>
      <spirit:vendorExtensions>
        <xilinx:busInterfaceInfo>
          <xilinx:enablement>
            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.C6_DDR2_RESET" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 ">false</xilinx:isEnabled>
          </xilinx:enablement>
        </xilinx:busInterfaceInfo>
      </spirit:vendorExtensions>
    </spirit:busInterface>
    <spirit:busInterface>
      <spirit:name>C6_LPDDR2_RESET</spirit:name>
      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
      <spirit:master/>
      <spirit:connectionRequired>true</spirit:connectionRequired>
      <spirit:portMaps>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>RST</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c6_lpddr2_ui_clk_sync_rst</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
      </spirit:portMaps>
      <spirit:parameters>
        <spirit:parameter>
          <spirit:name>POLARITY</spirit:name>
          <spirit:value spirit:id="BUSIFPARAM_VALUE.C6_LPDDR2_RESET.POLARITY">ACTIVE_HIGH</spirit:value>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>INSERT_VIP</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.C6_LPDDR2_RESET.INSERT_VIP">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
      </spirit:parameters>
      <spirit:vendorExtensions>
        <xilinx:busInterfaceInfo>
          <xilinx:enablement>
            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.C6_LPDDR2_RESET" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 ">false</xilinx:isEnabled>
          </xilinx:enablement>
        </xilinx:busInterfaceInfo>
      </spirit:vendorExtensions>
    </spirit:busInterface>
    <spirit:busInterface>
      <spirit:name>C6_QDRIIP_RESET</spirit:name>
      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
      <spirit:master/>
      <spirit:connectionRequired>true</spirit:connectionRequired>
      <spirit:portMaps>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>RST</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c6_qdriip_ui_clk_sync_rst</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
      </spirit:portMaps>
      <spirit:parameters>
        <spirit:parameter>
          <spirit:name>POLARITY</spirit:name>
          <spirit:value spirit:id="BUSIFPARAM_VALUE.C6_QDRIIP_RESET.POLARITY">ACTIVE_HIGH</spirit:value>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>INSERT_VIP</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.C6_QDRIIP_RESET.INSERT_VIP">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
      </spirit:parameters>
      <spirit:vendorExtensions>
        <xilinx:busInterfaceInfo>
          <xilinx:enablement>
            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.C6_QDRIIP_RESET" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 ">false</xilinx:isEnabled>
          </xilinx:enablement>
        </xilinx:busInterfaceInfo>
      </spirit:vendorExtensions>
    </spirit:busInterface>
    <spirit:busInterface>
      <spirit:name>C6_RLDII_RESET</spirit:name>
      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
      <spirit:master/>
      <spirit:connectionRequired>true</spirit:connectionRequired>
      <spirit:portMaps>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>RST</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c6_rldii_ui_clk_sync_rst</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
      </spirit:portMaps>
      <spirit:parameters>
        <spirit:parameter>
          <spirit:name>POLARITY</spirit:name>
          <spirit:value spirit:id="BUSIFPARAM_VALUE.C6_RLDII_RESET.POLARITY">ACTIVE_HIGH</spirit:value>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>INSERT_VIP</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.C6_RLDII_RESET.INSERT_VIP">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
      </spirit:parameters>
      <spirit:vendorExtensions>
        <xilinx:busInterfaceInfo>
          <xilinx:enablement>
            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.C6_RLDII_RESET" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 ">false</xilinx:isEnabled>
          </xilinx:enablement>
        </xilinx:busInterfaceInfo>
      </spirit:vendorExtensions>
    </spirit:busInterface>
    <spirit:busInterface>
      <spirit:name>C6_RLDIII_RESET</spirit:name>
      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
      <spirit:master/>
      <spirit:connectionRequired>true</spirit:connectionRequired>
      <spirit:portMaps>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>RST</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c6_rldiii_ui_clk_sync_rst</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
      </spirit:portMaps>
      <spirit:parameters>
        <spirit:parameter>
          <spirit:name>POLARITY</spirit:name>
          <spirit:value spirit:id="BUSIFPARAM_VALUE.C6_RLDIII_RESET.POLARITY">ACTIVE_HIGH</spirit:value>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>INSERT_VIP</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.C6_RLDIII_RESET.INSERT_VIP">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
      </spirit:parameters>
      <spirit:vendorExtensions>
        <xilinx:busInterfaceInfo>
          <xilinx:enablement>
            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.C6_RLDIII_RESET" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 ">false</xilinx:isEnabled>
          </xilinx:enablement>
        </xilinx:busInterfaceInfo>
      </spirit:vendorExtensions>
    </spirit:busInterface>
    <spirit:busInterface>
      <spirit:name>C6_CLOCK</spirit:name>
      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
      <spirit:master/>
      <spirit:connectionRequired>true</spirit:connectionRequired>
      <spirit:portMaps>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>CLK</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c6_ui_clk</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
      </spirit:portMaps>
      <spirit:parameters>
        <spirit:parameter>
          <spirit:name>FREQ_HZ</spirit:name>
          <spirit:value spirit:format="float" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.C6_CLOCK.FREQ_HZ" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C6_FREQ_HZ&apos;))">100</spirit:value>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>ASSOCIATED_BUSIF</spirit:name>
          <spirit:value spirit:id="BUSIFPARAM_VALUE.C6_CLOCK.ASSOCIATED_BUSIF">S6_AXI:S6_AXI_CTRL</spirit:value>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>ASSOCIATED_RESET</spirit:name>
          <spirit:value spirit:id="BUSIFPARAM_VALUE.C6_CLOCK.ASSOCIATED_RESET">c6_aresetn:c6_ui_clk_sync_rst</spirit:value>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>PHASE</spirit:name>
          <spirit:value spirit:format="float" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.C6_CLOCK.PHASE" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C6_PHASE&apos;))">0</spirit:value>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>CLK_DOMAIN</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C6_CLOCK.CLK_DOMAIN"/>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>INSERT_VIP</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.C6_CLOCK.INSERT_VIP">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
      </spirit:parameters>
      <spirit:vendorExtensions>
        <xilinx:busInterfaceInfo>
          <xilinx:enablement>
            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.C6_CLOCK" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 ">false</xilinx:isEnabled>
          </xilinx:enablement>
        </xilinx:busInterfaceInfo>
      </spirit:vendorExtensions>
    </spirit:busInterface>
    <spirit:busInterface>
      <spirit:name>C6_MMCM_CLKOUT0</spirit:name>
      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
      <spirit:master/>
      <spirit:connectionRequired>true</spirit:connectionRequired>
      <spirit:portMaps>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>CLK</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c6_ui_addn_clk_0</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
      </spirit:portMaps>
      <spirit:parameters>
        <spirit:parameter>
          <spirit:name>FREQ_HZ</spirit:name>
          <spirit:value spirit:format="float" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.C6_MMCM_CLKOUT0.FREQ_HZ" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MMCM_CLKOUT0_FREQ&apos;))">10</spirit:value>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>ASSOCIATED_ASYNC_RESET</spirit:name>
          <spirit:value spirit:id="BUSIFPARAM_VALUE.C6_MMCM_CLKOUT0.ASSOCIATED_ASYNC_RESET">c6_aresetn</spirit:value>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>PHASE</spirit:name>
          <spirit:value spirit:format="float" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.C6_MMCM_CLKOUT0.PHASE" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C6_PHASE&apos;))">0</spirit:value>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>CLK_DOMAIN</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C6_MMCM_CLKOUT0.CLK_DOMAIN"/>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>ASSOCIATED_BUSIF</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C6_MMCM_CLKOUT0.ASSOCIATED_BUSIF"/>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>ASSOCIATED_RESET</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C6_MMCM_CLKOUT0.ASSOCIATED_RESET"/>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>INSERT_VIP</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.C6_MMCM_CLKOUT0.INSERT_VIP">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
      </spirit:parameters>
      <spirit:vendorExtensions>
        <xilinx:busInterfaceInfo>
          <xilinx:enablement>
            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.C6_MMCM_CLKOUT0" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 ">false</xilinx:isEnabled>
          </xilinx:enablement>
        </xilinx:busInterfaceInfo>
      </spirit:vendorExtensions>
    </spirit:busInterface>
    <spirit:busInterface>
      <spirit:name>C6_MMCM_CLKOUT1</spirit:name>
      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
      <spirit:master/>
      <spirit:connectionRequired>true</spirit:connectionRequired>
      <spirit:portMaps>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>CLK</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c6_ui_addn_clk_1</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
      </spirit:portMaps>
      <spirit:parameters>
        <spirit:parameter>
          <spirit:name>FREQ_HZ</spirit:name>
          <spirit:value spirit:format="float" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.C6_MMCM_CLKOUT1.FREQ_HZ" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MMCM_CLKOUT1_FREQ&apos;))">10</spirit:value>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>ASSOCIATED_ASYNC_RESET</spirit:name>
          <spirit:value spirit:id="BUSIFPARAM_VALUE.C6_MMCM_CLKOUT1.ASSOCIATED_ASYNC_RESET">c6_aresetn</spirit:value>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>PHASE</spirit:name>
          <spirit:value spirit:format="float" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.C6_MMCM_CLKOUT1.PHASE" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C6_PHASE&apos;))">0</spirit:value>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>CLK_DOMAIN</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C6_MMCM_CLKOUT1.CLK_DOMAIN"/>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>ASSOCIATED_BUSIF</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C6_MMCM_CLKOUT1.ASSOCIATED_BUSIF"/>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>ASSOCIATED_RESET</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C6_MMCM_CLKOUT1.ASSOCIATED_RESET"/>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>INSERT_VIP</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.C6_MMCM_CLKOUT1.INSERT_VIP">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
      </spirit:parameters>
      <spirit:vendorExtensions>
        <xilinx:busInterfaceInfo>
          <xilinx:enablement>
            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.C6_MMCM_CLKOUT1" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 ">false</xilinx:isEnabled>
          </xilinx:enablement>
        </xilinx:busInterfaceInfo>
      </spirit:vendorExtensions>
    </spirit:busInterface>
    <spirit:busInterface>
      <spirit:name>C6_MMCM_CLKOUT2</spirit:name>
      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
      <spirit:master/>
      <spirit:connectionRequired>true</spirit:connectionRequired>
      <spirit:portMaps>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>CLK</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c6_ui_addn_clk_2</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
      </spirit:portMaps>
      <spirit:parameters>
        <spirit:parameter>
          <spirit:name>FREQ_HZ</spirit:name>
          <spirit:value spirit:format="float" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.C6_MMCM_CLKOUT2.FREQ_HZ" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MMCM_CLKOUT2_FREQ&apos;))">10</spirit:value>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>ASSOCIATED_ASYNC_RESET</spirit:name>
          <spirit:value spirit:id="BUSIFPARAM_VALUE.C6_MMCM_CLKOUT2.ASSOCIATED_ASYNC_RESET">c6_aresetn</spirit:value>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>PHASE</spirit:name>
          <spirit:value spirit:format="float" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.C6_MMCM_CLKOUT2.PHASE" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C6_PHASE&apos;))">0</spirit:value>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>CLK_DOMAIN</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C6_MMCM_CLKOUT2.CLK_DOMAIN"/>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>ASSOCIATED_BUSIF</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C6_MMCM_CLKOUT2.ASSOCIATED_BUSIF"/>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>ASSOCIATED_RESET</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C6_MMCM_CLKOUT2.ASSOCIATED_RESET"/>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>INSERT_VIP</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.C6_MMCM_CLKOUT2.INSERT_VIP">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
      </spirit:parameters>
      <spirit:vendorExtensions>
        <xilinx:busInterfaceInfo>
          <xilinx:enablement>
            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.C6_MMCM_CLKOUT2" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 ">false</xilinx:isEnabled>
          </xilinx:enablement>
        </xilinx:busInterfaceInfo>
      </spirit:vendorExtensions>
    </spirit:busInterface>
    <spirit:busInterface>
      <spirit:name>C6_MMCM_CLKOUT3</spirit:name>
      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
      <spirit:master/>
      <spirit:connectionRequired>true</spirit:connectionRequired>
      <spirit:portMaps>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>CLK</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c6_ui_addn_clk_3</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
      </spirit:portMaps>
      <spirit:parameters>
        <spirit:parameter>
          <spirit:name>FREQ_HZ</spirit:name>
          <spirit:value spirit:format="float" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.C6_MMCM_CLKOUT3.FREQ_HZ" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MMCM_CLKOUT3_FREQ&apos;))">10</spirit:value>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>ASSOCIATED_ASYNC_RESET</spirit:name>
          <spirit:value spirit:id="BUSIFPARAM_VALUE.C6_MMCM_CLKOUT3.ASSOCIATED_ASYNC_RESET">c6_aresetn</spirit:value>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>PHASE</spirit:name>
          <spirit:value spirit:format="float" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.C6_MMCM_CLKOUT3.PHASE" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C6_PHASE&apos;))">0</spirit:value>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>CLK_DOMAIN</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C6_MMCM_CLKOUT3.CLK_DOMAIN"/>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>ASSOCIATED_BUSIF</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C6_MMCM_CLKOUT3.ASSOCIATED_BUSIF"/>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>ASSOCIATED_RESET</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C6_MMCM_CLKOUT3.ASSOCIATED_RESET"/>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>INSERT_VIP</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.C6_MMCM_CLKOUT3.INSERT_VIP">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
      </spirit:parameters>
      <spirit:vendorExtensions>
        <xilinx:busInterfaceInfo>
          <xilinx:enablement>
            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.C6_MMCM_CLKOUT3" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 ">false</xilinx:isEnabled>
          </xilinx:enablement>
        </xilinx:busInterfaceInfo>
      </spirit:vendorExtensions>
    </spirit:busInterface>
    <spirit:busInterface>
      <spirit:name>C6_MMCM_CLKOUT4</spirit:name>
      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
      <spirit:master/>
      <spirit:connectionRequired>true</spirit:connectionRequired>
      <spirit:portMaps>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>CLK</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c6_ui_addn_clk_4</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
      </spirit:portMaps>
      <spirit:parameters>
        <spirit:parameter>
          <spirit:name>FREQ_HZ</spirit:name>
          <spirit:value spirit:format="float" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.C6_MMCM_CLKOUT4.FREQ_HZ" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MMCM_CLKOUT4_FREQ&apos;))">10</spirit:value>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>ASSOCIATED_ASYNC_RESET</spirit:name>
          <spirit:value spirit:id="BUSIFPARAM_VALUE.C6_MMCM_CLKOUT4.ASSOCIATED_ASYNC_RESET">c6_aresetn</spirit:value>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>PHASE</spirit:name>
          <spirit:value spirit:format="float" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.C6_MMCM_CLKOUT4.PHASE" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C6_PHASE&apos;))">0</spirit:value>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>CLK_DOMAIN</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C6_MMCM_CLKOUT4.CLK_DOMAIN"/>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>ASSOCIATED_BUSIF</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C6_MMCM_CLKOUT4.ASSOCIATED_BUSIF"/>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>ASSOCIATED_RESET</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C6_MMCM_CLKOUT4.ASSOCIATED_RESET"/>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>INSERT_VIP</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.C6_MMCM_CLKOUT4.INSERT_VIP">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
      </spirit:parameters>
      <spirit:vendorExtensions>
        <xilinx:busInterfaceInfo>
          <xilinx:enablement>
            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.C6_MMCM_CLKOUT4" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 ">false</xilinx:isEnabled>
          </xilinx:enablement>
        </xilinx:busInterfaceInfo>
      </spirit:vendorExtensions>
    </spirit:busInterface>
    <spirit:busInterface>
      <spirit:name>S6_AXI_CTRL</spirit:name>
      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm" spirit:version="1.0"/>
      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm_rtl" spirit:version="1.0"/>
      <spirit:slave>
        <spirit:memoryMapRef spirit:memoryMapRef="c6_s_axi_ctrl_memmap"/>
      </spirit:slave>
      <spirit:connectionRequired>true</spirit:connectionRequired>
      <spirit:portMaps>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>AWVALID</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c6_s_axi_ctrl_awvalid</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>AWREADY</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c6_s_axi_ctrl_awready</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>AWADDR</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c6_s_axi_ctrl_awaddr</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>WVALID</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c6_s_axi_ctrl_wvalid</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>WREADY</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c6_s_axi_ctrl_wready</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>WDATA</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c6_s_axi_ctrl_wdata</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>BVALID</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c6_s_axi_ctrl_bvalid</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>BREADY</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c6_s_axi_ctrl_bready</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>BRESP</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c6_s_axi_ctrl_bresp</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>ARVALID</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c6_s_axi_ctrl_arvalid</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>ARREADY</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c6_s_axi_ctrl_arready</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>ARADDR</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c6_s_axi_ctrl_araddr</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>RVALID</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c6_s_axi_ctrl_rvalid</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>RREADY</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c6_s_axi_ctrl_rready</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>RDATA</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c6_s_axi_ctrl_rdata</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>RRESP</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c6_s_axi_ctrl_rresp</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
      </spirit:portMaps>
      <spirit:parameters>
        <spirit:parameter>
          <spirit:name>FREQ_HZ</spirit:name>
          <spirit:value spirit:format="float" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.S6_AXI_CTRL.FREQ_HZ" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C6_FREQ_HZ&apos;))">100</spirit:value>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>DATA_WIDTH</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S6_AXI_CTRL.DATA_WIDTH">1</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>PROTOCOL</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S6_AXI_CTRL.PROTOCOL">AXI4LITE</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>ID_WIDTH</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S6_AXI_CTRL.ID_WIDTH">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>ADDR_WIDTH</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S6_AXI_CTRL.ADDR_WIDTH">1</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>AWUSER_WIDTH</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S6_AXI_CTRL.AWUSER_WIDTH">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>ARUSER_WIDTH</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S6_AXI_CTRL.ARUSER_WIDTH">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>WUSER_WIDTH</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S6_AXI_CTRL.WUSER_WIDTH">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>RUSER_WIDTH</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S6_AXI_CTRL.RUSER_WIDTH">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>BUSER_WIDTH</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S6_AXI_CTRL.BUSER_WIDTH">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>READ_WRITE_MODE</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S6_AXI_CTRL.READ_WRITE_MODE">READ_WRITE</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>HAS_BURST</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S6_AXI_CTRL.HAS_BURST">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>HAS_LOCK</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S6_AXI_CTRL.HAS_LOCK">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>HAS_PROT</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S6_AXI_CTRL.HAS_PROT">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>HAS_CACHE</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S6_AXI_CTRL.HAS_CACHE">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>HAS_QOS</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S6_AXI_CTRL.HAS_QOS">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>HAS_REGION</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S6_AXI_CTRL.HAS_REGION">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>HAS_WSTRB</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S6_AXI_CTRL.HAS_WSTRB">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>HAS_BRESP</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S6_AXI_CTRL.HAS_BRESP">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>HAS_RRESP</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S6_AXI_CTRL.HAS_RRESP">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>SUPPORTS_NARROW_BURST</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S6_AXI_CTRL.SUPPORTS_NARROW_BURST">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>NUM_READ_OUTSTANDING</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S6_AXI_CTRL.NUM_READ_OUTSTANDING">1</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>NUM_WRITE_OUTSTANDING</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S6_AXI_CTRL.NUM_WRITE_OUTSTANDING">1</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>MAX_BURST_LENGTH</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S6_AXI_CTRL.MAX_BURST_LENGTH">1</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>PHASE</spirit:name>
          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S6_AXI_CTRL.PHASE">0.000</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>CLK_DOMAIN</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S6_AXI_CTRL.CLK_DOMAIN"/>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>NUM_READ_THREADS</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S6_AXI_CTRL.NUM_READ_THREADS">1</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>NUM_WRITE_THREADS</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S6_AXI_CTRL.NUM_WRITE_THREADS">1</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>RUSER_BITS_PER_BYTE</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S6_AXI_CTRL.RUSER_BITS_PER_BYTE">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>WUSER_BITS_PER_BYTE</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S6_AXI_CTRL.WUSER_BITS_PER_BYTE">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>INSERT_VIP</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.S6_AXI_CTRL.INSERT_VIP">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
      </spirit:parameters>
      <spirit:vendorExtensions>
        <xilinx:busInterfaceInfo>
          <xilinx:enablement>
            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.S6_AXI_CTRL" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_USE_AXI&apos;)) = 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_ECC&apos;)) = &quot;ON&quot; ) ">false</xilinx:isEnabled>
          </xilinx:enablement>
        </xilinx:busInterfaceInfo>
      </spirit:vendorExtensions>
    </spirit:busInterface>
    <spirit:busInterface>
      <spirit:name>S6_AXI</spirit:name>
      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm" spirit:version="1.0"/>
      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm_rtl" spirit:version="1.0"/>
      <spirit:slave>
        <spirit:memoryMapRef spirit:memoryMapRef="c6_memmap"/>
      </spirit:slave>
      <spirit:connectionRequired>true</spirit:connectionRequired>
      <spirit:portMaps>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>AWID</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c6_s_axi_awid</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>AWADDR</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c6_s_axi_awaddr</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>AWLEN</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c6_s_axi_awlen</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>AWSIZE</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c6_s_axi_awsize</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>AWBURST</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c6_s_axi_awburst</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>AWLOCK</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c6_s_axi_awlock</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>AWCACHE</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c6_s_axi_awcache</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>AWPROT</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c6_s_axi_awprot</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>AWQOS</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c6_s_axi_awqos</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>AWVALID</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c6_s_axi_awvalid</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>AWREADY</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c6_s_axi_awready</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>WDATA</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c6_s_axi_wdata</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>WSTRB</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c6_s_axi_wstrb</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>WLAST</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c6_s_axi_wlast</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>WVALID</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c6_s_axi_wvalid</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>WREADY</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c6_s_axi_wready</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>BREADY</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c6_s_axi_bready</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>BID</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c6_s_axi_bid</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>BRESP</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c6_s_axi_bresp</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>BVALID</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c6_s_axi_bvalid</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>ARID</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c6_s_axi_arid</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>ARADDR</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c6_s_axi_araddr</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>ARLEN</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c6_s_axi_arlen</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>ARSIZE</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c6_s_axi_arsize</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>ARBURST</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c6_s_axi_arburst</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>ARLOCK</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c6_s_axi_arlock</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>ARCACHE</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c6_s_axi_arcache</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>ARPROT</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c6_s_axi_arprot</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>ARQOS</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c6_s_axi_arqos</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>ARVALID</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c6_s_axi_arvalid</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>ARREADY</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c6_s_axi_arready</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>RREADY</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c6_s_axi_rready</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>RID</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c6_s_axi_rid</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>RDATA</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c6_s_axi_rdata</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>RRESP</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c6_s_axi_rresp</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>RLAST</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c6_s_axi_rlast</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>RVALID</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c6_s_axi_rvalid</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
      </spirit:portMaps>
      <spirit:parameters>
        <spirit:parameter>
          <spirit:name>FREQ_HZ</spirit:name>
          <spirit:value spirit:format="float" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.S6_AXI.FREQ_HZ" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C6_FREQ_HZ&apos;))">100</spirit:value>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>DATA_WIDTH</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S6_AXI.DATA_WIDTH">1</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>PROTOCOL</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S6_AXI.PROTOCOL">AXI4LITE</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>ID_WIDTH</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S6_AXI.ID_WIDTH">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>ADDR_WIDTH</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S6_AXI.ADDR_WIDTH">1</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>AWUSER_WIDTH</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S6_AXI.AWUSER_WIDTH">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>ARUSER_WIDTH</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S6_AXI.ARUSER_WIDTH">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>WUSER_WIDTH</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S6_AXI.WUSER_WIDTH">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>RUSER_WIDTH</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S6_AXI.RUSER_WIDTH">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>BUSER_WIDTH</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S6_AXI.BUSER_WIDTH">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>READ_WRITE_MODE</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S6_AXI.READ_WRITE_MODE">READ_WRITE</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>HAS_BURST</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S6_AXI.HAS_BURST">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>HAS_LOCK</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S6_AXI.HAS_LOCK">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>HAS_PROT</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S6_AXI.HAS_PROT">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>HAS_CACHE</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S6_AXI.HAS_CACHE">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>HAS_QOS</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S6_AXI.HAS_QOS">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>HAS_REGION</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S6_AXI.HAS_REGION">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>HAS_WSTRB</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S6_AXI.HAS_WSTRB">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>HAS_BRESP</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S6_AXI.HAS_BRESP">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>HAS_RRESP</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S6_AXI.HAS_RRESP">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>SUPPORTS_NARROW_BURST</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S6_AXI.SUPPORTS_NARROW_BURST">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>NUM_READ_OUTSTANDING</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S6_AXI.NUM_READ_OUTSTANDING">1</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>NUM_WRITE_OUTSTANDING</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S6_AXI.NUM_WRITE_OUTSTANDING">1</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>MAX_BURST_LENGTH</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S6_AXI.MAX_BURST_LENGTH">1</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>PHASE</spirit:name>
          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S6_AXI.PHASE">0.000</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>CLK_DOMAIN</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S6_AXI.CLK_DOMAIN"/>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>NUM_READ_THREADS</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S6_AXI.NUM_READ_THREADS">1</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>NUM_WRITE_THREADS</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S6_AXI.NUM_WRITE_THREADS">1</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>RUSER_BITS_PER_BYTE</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S6_AXI.RUSER_BITS_PER_BYTE">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>WUSER_BITS_PER_BYTE</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S6_AXI.WUSER_BITS_PER_BYTE">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>INSERT_VIP</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.S6_AXI.INSERT_VIP">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
      </spirit:parameters>
      <spirit:vendorExtensions>
        <xilinx:busInterfaceInfo>
          <xilinx:enablement>
            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.S6_AXI" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
          </xilinx:enablement>
        </xilinx:busInterfaceInfo>
      </spirit:vendorExtensions>
    </spirit:busInterface>
    <spirit:busInterface>
      <spirit:name>C6_SYS_CLK</spirit:name>
      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="diff_clock" spirit:version="1.0"/>
      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="diff_clock_rtl" spirit:version="1.0"/>
      <spirit:slave/>
      <spirit:connectionRequired>true</spirit:connectionRequired>
      <spirit:portMaps>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>CLK_P</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c6_sys_clk_p</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>CLK_N</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c6_sys_clk_n</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
      </spirit:portMaps>
      <spirit:parameters>
        <spirit:parameter>
          <spirit:name>CAN_DEBUG</spirit:name>
          <spirit:value spirit:format="bool" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C6_SYS_CLK.CAN_DEBUG">false</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>FREQ_HZ</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C6_SYS_CLK.FREQ_HZ">100000000</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
      </spirit:parameters>
      <spirit:vendorExtensions>
        <xilinx:busInterfaceInfo>
          <xilinx:enablement>
            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.C6_SYS_CLK" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_SYSCLK_TYPE&apos;)) = &quot;DIFF&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_IS_CLK_SHARED&apos;)) = &quot;FALSE&quot; ">false</xilinx:isEnabled>
          </xilinx:enablement>
        </xilinx:busInterfaceInfo>
      </spirit:vendorExtensions>
    </spirit:busInterface>
    <spirit:busInterface>
      <spirit:name>C6_SYS_CLK_I</spirit:name>
      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
      <spirit:slave/>
      <spirit:connectionRequired>true</spirit:connectionRequired>
      <spirit:portMaps>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>CLK</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c6_sys_clk_i</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
      </spirit:portMaps>
      <spirit:parameters>
        <spirit:parameter>
          <spirit:name>FREQ_HZ</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C6_SYS_CLK_I.FREQ_HZ">100000000</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>PHASE</spirit:name>
          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C6_SYS_CLK_I.PHASE">0.000</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>CLK_DOMAIN</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C6_SYS_CLK_I.CLK_DOMAIN"/>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>ASSOCIATED_BUSIF</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C6_SYS_CLK_I.ASSOCIATED_BUSIF"/>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>ASSOCIATED_RESET</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C6_SYS_CLK_I.ASSOCIATED_RESET"/>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>INSERT_VIP</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.C6_SYS_CLK_I.INSERT_VIP">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
      </spirit:parameters>
      <spirit:vendorExtensions>
        <xilinx:busInterfaceInfo>
          <xilinx:enablement>
            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.C6_SYS_CLK_I" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_SYSCLK_TYPE&apos;)) != &quot;DIFF&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_IS_CLK_SHARED&apos;)) = &quot;FALSE&quot; ">false</xilinx:isEnabled>
          </xilinx:enablement>
        </xilinx:busInterfaceInfo>
      </spirit:vendorExtensions>
    </spirit:busInterface>
    <spirit:busInterface>
      <spirit:name>C6_ARESETN</spirit:name>
      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
      <spirit:slave/>
      <spirit:connectionRequired>true</spirit:connectionRequired>
      <spirit:portMaps>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>ARESETN</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c6_aresetn</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
      </spirit:portMaps>
      <spirit:parameters>
        <spirit:parameter>
          <spirit:name>POLARITY</spirit:name>
          <spirit:value spirit:id="BUSIFPARAM_VALUE.C6_ARESETN.POLARITY">ACTIVE_LOW</spirit:value>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>INSERT_VIP</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.C6_ARESETN.INSERT_VIP">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
      </spirit:parameters>
    </spirit:busInterface>
    <spirit:busInterface>
      <spirit:name>C7_DDR3</spirit:name>
      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="ddrx" spirit:version="1.0"/>
      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="ddrx_rtl" spirit:version="1.0"/>
      <spirit:master/>
      <spirit:connectionRequired>true</spirit:connectionRequired>
      <spirit:portMaps>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>DQ</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c7_ddr3_dq</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>DQS_P</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c7_ddr3_dqs_p</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>DQS_N</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c7_ddr3_dqs_n</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>ADDR</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c7_ddr3_addr</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>BA</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c7_ddr3_ba</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>RAS_N</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c7_ddr3_ras_n</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>CAS_N</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c7_ddr3_cas_n</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>WE_N</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c7_ddr3_we_n</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>RESET_N</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c7_ddr3_reset_n</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>CK_P</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c7_ddr3_ck_p</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>CK_N</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c7_ddr3_ck_n</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>CKE</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c7_ddr3_cke</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>CS_N</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c7_ddr3_cs_n</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>DM</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c7_ddr3_dm</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>ODT</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c7_ddr3_odt</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>PARITY</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c7_ddr3_parity</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
      </spirit:portMaps>
      <spirit:parameters>
        <spirit:parameter>
          <spirit:name>CAN_DEBUG</spirit:name>
          <spirit:value spirit:format="bool" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C7_DDR3.CAN_DEBUG">false</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>TIMEPERIOD_PS</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C7_DDR3.TIMEPERIOD_PS">1250</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>MEMORY_TYPE</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C7_DDR3.MEMORY_TYPE">COMPONENTS</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>MEMORY_PART</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C7_DDR3.MEMORY_PART"/>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>DATA_WIDTH</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C7_DDR3.DATA_WIDTH">8</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>CS_ENABLED</spirit:name>
          <spirit:value spirit:format="bool" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C7_DDR3.CS_ENABLED">true</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>DATA_MASK_ENABLED</spirit:name>
          <spirit:value spirit:format="bool" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C7_DDR3.DATA_MASK_ENABLED">true</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>SLOT</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C7_DDR3.SLOT">Single</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>CUSTOM_PARTS</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C7_DDR3.CUSTOM_PARTS"/>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>MEM_ADDR_MAP</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C7_DDR3.MEM_ADDR_MAP">ROW_COLUMN_BANK</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>BURST_LENGTH</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C7_DDR3.BURST_LENGTH">8</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>AXI_ARBITRATION_SCHEME</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C7_DDR3.AXI_ARBITRATION_SCHEME">TDM</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>CAS_LATENCY</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C7_DDR3.CAS_LATENCY">11</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>CAS_WRITE_LATENCY</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C7_DDR3.CAS_WRITE_LATENCY">11</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
      </spirit:parameters>
      <spirit:vendorExtensions>
        <xilinx:busInterfaceInfo>
          <xilinx:enablement>
            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.C7_DDR3" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;DDR3&quot; ">false</xilinx:isEnabled>
          </xilinx:enablement>
        </xilinx:busInterfaceInfo>
      </spirit:vendorExtensions>
    </spirit:busInterface>
    <spirit:busInterface>
      <spirit:name>C7_DDR2</spirit:name>
      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="ddrx" spirit:version="1.0"/>
      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="ddrx_rtl" spirit:version="1.0"/>
      <spirit:master/>
      <spirit:connectionRequired>true</spirit:connectionRequired>
      <spirit:portMaps>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>DQ</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c7_ddr2_dq</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>DQS_P</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c7_ddr2_dqs_p</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>DQS_N</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c7_ddr2_dqs_n</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>ADDR</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c7_ddr2_addr</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>BA</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c7_ddr2_ba</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>RAS_N</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c7_ddr2_ras_n</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>CAS_N</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c7_ddr2_cas_n</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>WE_N</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c7_ddr2_we_n</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>RESET_N</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c7_ddr2_reset_n</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>CK_P</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c7_ddr2_ck_p</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>CK_N</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c7_ddr2_ck_n</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>CKE</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c7_ddr2_cke</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>CS_N</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c7_ddr2_cs_n</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>DM</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c7_ddr2_dm</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>ODT</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c7_ddr2_odt</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>PARITY</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c7_ddr2_parity</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
      </spirit:portMaps>
      <spirit:parameters>
        <spirit:parameter>
          <spirit:name>CAN_DEBUG</spirit:name>
          <spirit:value spirit:format="bool" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C7_DDR2.CAN_DEBUG">false</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>TIMEPERIOD_PS</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C7_DDR2.TIMEPERIOD_PS">1250</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>MEMORY_TYPE</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C7_DDR2.MEMORY_TYPE">COMPONENTS</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>MEMORY_PART</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C7_DDR2.MEMORY_PART"/>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>DATA_WIDTH</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C7_DDR2.DATA_WIDTH">8</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>CS_ENABLED</spirit:name>
          <spirit:value spirit:format="bool" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C7_DDR2.CS_ENABLED">true</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>DATA_MASK_ENABLED</spirit:name>
          <spirit:value spirit:format="bool" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C7_DDR2.DATA_MASK_ENABLED">true</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>SLOT</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C7_DDR2.SLOT">Single</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>CUSTOM_PARTS</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C7_DDR2.CUSTOM_PARTS"/>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>MEM_ADDR_MAP</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C7_DDR2.MEM_ADDR_MAP">ROW_COLUMN_BANK</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>BURST_LENGTH</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C7_DDR2.BURST_LENGTH">8</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>AXI_ARBITRATION_SCHEME</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C7_DDR2.AXI_ARBITRATION_SCHEME">TDM</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>CAS_LATENCY</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C7_DDR2.CAS_LATENCY">11</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>CAS_WRITE_LATENCY</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C7_DDR2.CAS_WRITE_LATENCY">11</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
      </spirit:parameters>
      <spirit:vendorExtensions>
        <xilinx:busInterfaceInfo>
          <xilinx:enablement>
            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.C7_DDR2" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;DDR2&quot; ">false</xilinx:isEnabled>
          </xilinx:enablement>
        </xilinx:busInterfaceInfo>
      </spirit:vendorExtensions>
    </spirit:busInterface>
    <spirit:busInterface>
      <spirit:name>C7_RESET</spirit:name>
      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
      <spirit:master/>
      <spirit:connectionRequired>true</spirit:connectionRequired>
      <spirit:portMaps>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>RST</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c7_ui_clk_sync_rst</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
      </spirit:portMaps>
      <spirit:parameters>
        <spirit:parameter>
          <spirit:name>POLARITY</spirit:name>
          <spirit:value spirit:id="BUSIFPARAM_VALUE.C7_RESET.POLARITY">ACTIVE_HIGH</spirit:value>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>INSERT_VIP</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.C7_RESET.INSERT_VIP">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
      </spirit:parameters>
      <spirit:vendorExtensions>
        <xilinx:busInterfaceInfo>
          <xilinx:enablement>
            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.C7_RESET" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 ">false</xilinx:isEnabled>
          </xilinx:enablement>
        </xilinx:busInterfaceInfo>
      </spirit:vendorExtensions>
    </spirit:busInterface>
    <spirit:busInterface>
      <spirit:name>C7_DDR3_RESET</spirit:name>
      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
      <spirit:master/>
      <spirit:connectionRequired>true</spirit:connectionRequired>
      <spirit:portMaps>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>RST</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c7_ddr3_ui_clk_sync_rst</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
      </spirit:portMaps>
      <spirit:parameters>
        <spirit:parameter>
          <spirit:name>POLARITY</spirit:name>
          <spirit:value spirit:id="BUSIFPARAM_VALUE.C7_DDR3_RESET.POLARITY">ACTIVE_HIGH</spirit:value>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>INSERT_VIP</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.C7_DDR3_RESET.INSERT_VIP">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
      </spirit:parameters>
      <spirit:vendorExtensions>
        <xilinx:busInterfaceInfo>
          <xilinx:enablement>
            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.C7_DDR3_RESET" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 ">false</xilinx:isEnabled>
          </xilinx:enablement>
        </xilinx:busInterfaceInfo>
      </spirit:vendorExtensions>
    </spirit:busInterface>
    <spirit:busInterface>
      <spirit:name>C7_DDR2_RESET</spirit:name>
      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
      <spirit:master/>
      <spirit:connectionRequired>true</spirit:connectionRequired>
      <spirit:portMaps>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>RST</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c7_ddr2_ui_clk_sync_rst</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
      </spirit:portMaps>
      <spirit:parameters>
        <spirit:parameter>
          <spirit:name>POLARITY</spirit:name>
          <spirit:value spirit:id="BUSIFPARAM_VALUE.C7_DDR2_RESET.POLARITY">ACTIVE_HIGH</spirit:value>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>INSERT_VIP</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.C7_DDR2_RESET.INSERT_VIP">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
      </spirit:parameters>
      <spirit:vendorExtensions>
        <xilinx:busInterfaceInfo>
          <xilinx:enablement>
            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.C7_DDR2_RESET" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 ">false</xilinx:isEnabled>
          </xilinx:enablement>
        </xilinx:busInterfaceInfo>
      </spirit:vendorExtensions>
    </spirit:busInterface>
    <spirit:busInterface>
      <spirit:name>C7_LPDDR2_RESET</spirit:name>
      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
      <spirit:master/>
      <spirit:connectionRequired>true</spirit:connectionRequired>
      <spirit:portMaps>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>RST</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c7_lpddr2_ui_clk_sync_rst</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
      </spirit:portMaps>
      <spirit:parameters>
        <spirit:parameter>
          <spirit:name>POLARITY</spirit:name>
          <spirit:value spirit:id="BUSIFPARAM_VALUE.C7_LPDDR2_RESET.POLARITY">ACTIVE_HIGH</spirit:value>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>INSERT_VIP</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.C7_LPDDR2_RESET.INSERT_VIP">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
      </spirit:parameters>
      <spirit:vendorExtensions>
        <xilinx:busInterfaceInfo>
          <xilinx:enablement>
            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.C7_LPDDR2_RESET" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 ">false</xilinx:isEnabled>
          </xilinx:enablement>
        </xilinx:busInterfaceInfo>
      </spirit:vendorExtensions>
    </spirit:busInterface>
    <spirit:busInterface>
      <spirit:name>C7_QDRIIP_RESET</spirit:name>
      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
      <spirit:master/>
      <spirit:connectionRequired>true</spirit:connectionRequired>
      <spirit:portMaps>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>RST</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c7_qdriip_ui_clk_sync_rst</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
      </spirit:portMaps>
      <spirit:parameters>
        <spirit:parameter>
          <spirit:name>POLARITY</spirit:name>
          <spirit:value spirit:id="BUSIFPARAM_VALUE.C7_QDRIIP_RESET.POLARITY">ACTIVE_HIGH</spirit:value>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>INSERT_VIP</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.C7_QDRIIP_RESET.INSERT_VIP">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
      </spirit:parameters>
      <spirit:vendorExtensions>
        <xilinx:busInterfaceInfo>
          <xilinx:enablement>
            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.C7_QDRIIP_RESET" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 ">false</xilinx:isEnabled>
          </xilinx:enablement>
        </xilinx:busInterfaceInfo>
      </spirit:vendorExtensions>
    </spirit:busInterface>
    <spirit:busInterface>
      <spirit:name>C7_RLDII_RESET</spirit:name>
      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
      <spirit:master/>
      <spirit:connectionRequired>true</spirit:connectionRequired>
      <spirit:portMaps>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>RST</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c7_rldii_ui_clk_sync_rst</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
      </spirit:portMaps>
      <spirit:parameters>
        <spirit:parameter>
          <spirit:name>POLARITY</spirit:name>
          <spirit:value spirit:id="BUSIFPARAM_VALUE.C7_RLDII_RESET.POLARITY">ACTIVE_HIGH</spirit:value>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>INSERT_VIP</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.C7_RLDII_RESET.INSERT_VIP">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
      </spirit:parameters>
      <spirit:vendorExtensions>
        <xilinx:busInterfaceInfo>
          <xilinx:enablement>
            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.C7_RLDII_RESET" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 ">false</xilinx:isEnabled>
          </xilinx:enablement>
        </xilinx:busInterfaceInfo>
      </spirit:vendorExtensions>
    </spirit:busInterface>
    <spirit:busInterface>
      <spirit:name>C7_RLDIII_RESET</spirit:name>
      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
      <spirit:master/>
      <spirit:connectionRequired>true</spirit:connectionRequired>
      <spirit:portMaps>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>RST</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c7_rldiii_ui_clk_sync_rst</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
      </spirit:portMaps>
      <spirit:parameters>
        <spirit:parameter>
          <spirit:name>POLARITY</spirit:name>
          <spirit:value spirit:id="BUSIFPARAM_VALUE.C7_RLDIII_RESET.POLARITY">ACTIVE_HIGH</spirit:value>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>INSERT_VIP</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.C7_RLDIII_RESET.INSERT_VIP">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
      </spirit:parameters>
      <spirit:vendorExtensions>
        <xilinx:busInterfaceInfo>
          <xilinx:enablement>
            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.C7_RLDIII_RESET" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 ">false</xilinx:isEnabled>
          </xilinx:enablement>
        </xilinx:busInterfaceInfo>
      </spirit:vendorExtensions>
    </spirit:busInterface>
    <spirit:busInterface>
      <spirit:name>C7_CLOCK</spirit:name>
      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
      <spirit:master/>
      <spirit:connectionRequired>true</spirit:connectionRequired>
      <spirit:portMaps>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>CLK</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c7_ui_clk</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
      </spirit:portMaps>
      <spirit:parameters>
        <spirit:parameter>
          <spirit:name>FREQ_HZ</spirit:name>
          <spirit:value spirit:format="float" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.C7_CLOCK.FREQ_HZ" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C7_FREQ_HZ&apos;))">100</spirit:value>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>ASSOCIATED_BUSIF</spirit:name>
          <spirit:value spirit:id="BUSIFPARAM_VALUE.C7_CLOCK.ASSOCIATED_BUSIF">S7_AXI:S7_AXI_CTRL</spirit:value>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>ASSOCIATED_RESET</spirit:name>
          <spirit:value spirit:id="BUSIFPARAM_VALUE.C7_CLOCK.ASSOCIATED_RESET">c7_aresetn:c7_ui_clk_sync_rst</spirit:value>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>PHASE</spirit:name>
          <spirit:value spirit:format="float" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.C7_CLOCK.PHASE" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C7_PHASE&apos;))">0</spirit:value>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>CLK_DOMAIN</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C7_CLOCK.CLK_DOMAIN"/>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>INSERT_VIP</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.C7_CLOCK.INSERT_VIP">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
      </spirit:parameters>
      <spirit:vendorExtensions>
        <xilinx:busInterfaceInfo>
          <xilinx:enablement>
            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.C7_CLOCK" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 ">false</xilinx:isEnabled>
          </xilinx:enablement>
        </xilinx:busInterfaceInfo>
      </spirit:vendorExtensions>
    </spirit:busInterface>
    <spirit:busInterface>
      <spirit:name>C7_MMCM_CLKOUT0</spirit:name>
      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
      <spirit:master/>
      <spirit:connectionRequired>true</spirit:connectionRequired>
      <spirit:portMaps>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>CLK</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c7_ui_addn_clk_0</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
      </spirit:portMaps>
      <spirit:parameters>
        <spirit:parameter>
          <spirit:name>FREQ_HZ</spirit:name>
          <spirit:value spirit:format="float" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.C7_MMCM_CLKOUT0.FREQ_HZ" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MMCM_CLKOUT0_FREQ&apos;))">10</spirit:value>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>ASSOCIATED_ASYNC_RESET</spirit:name>
          <spirit:value spirit:id="BUSIFPARAM_VALUE.C7_MMCM_CLKOUT0.ASSOCIATED_ASYNC_RESET">c7_aresetn</spirit:value>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>PHASE</spirit:name>
          <spirit:value spirit:format="float" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.C7_MMCM_CLKOUT0.PHASE" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C7_PHASE&apos;))">0</spirit:value>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>CLK_DOMAIN</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C7_MMCM_CLKOUT0.CLK_DOMAIN"/>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>ASSOCIATED_BUSIF</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C7_MMCM_CLKOUT0.ASSOCIATED_BUSIF"/>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>ASSOCIATED_RESET</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C7_MMCM_CLKOUT0.ASSOCIATED_RESET"/>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>INSERT_VIP</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.C7_MMCM_CLKOUT0.INSERT_VIP">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
      </spirit:parameters>
      <spirit:vendorExtensions>
        <xilinx:busInterfaceInfo>
          <xilinx:enablement>
            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.C7_MMCM_CLKOUT0" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 ">false</xilinx:isEnabled>
          </xilinx:enablement>
        </xilinx:busInterfaceInfo>
      </spirit:vendorExtensions>
    </spirit:busInterface>
    <spirit:busInterface>
      <spirit:name>C7_MMCM_CLKOUT1</spirit:name>
      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
      <spirit:master/>
      <spirit:connectionRequired>true</spirit:connectionRequired>
      <spirit:portMaps>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>CLK</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c7_ui_addn_clk_1</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
      </spirit:portMaps>
      <spirit:parameters>
        <spirit:parameter>
          <spirit:name>FREQ_HZ</spirit:name>
          <spirit:value spirit:format="float" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.C7_MMCM_CLKOUT1.FREQ_HZ" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MMCM_CLKOUT1_FREQ&apos;))">10</spirit:value>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>ASSOCIATED_ASYNC_RESET</spirit:name>
          <spirit:value spirit:id="BUSIFPARAM_VALUE.C7_MMCM_CLKOUT1.ASSOCIATED_ASYNC_RESET">c7_aresetn</spirit:value>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>PHASE</spirit:name>
          <spirit:value spirit:format="float" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.C7_MMCM_CLKOUT1.PHASE" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C7_PHASE&apos;))">0</spirit:value>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>CLK_DOMAIN</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C7_MMCM_CLKOUT1.CLK_DOMAIN"/>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>ASSOCIATED_BUSIF</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C7_MMCM_CLKOUT1.ASSOCIATED_BUSIF"/>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>ASSOCIATED_RESET</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C7_MMCM_CLKOUT1.ASSOCIATED_RESET"/>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>INSERT_VIP</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.C7_MMCM_CLKOUT1.INSERT_VIP">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
      </spirit:parameters>
      <spirit:vendorExtensions>
        <xilinx:busInterfaceInfo>
          <xilinx:enablement>
            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.C7_MMCM_CLKOUT1" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 ">false</xilinx:isEnabled>
          </xilinx:enablement>
        </xilinx:busInterfaceInfo>
      </spirit:vendorExtensions>
    </spirit:busInterface>
    <spirit:busInterface>
      <spirit:name>C7_MMCM_CLKOUT2</spirit:name>
      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
      <spirit:master/>
      <spirit:connectionRequired>true</spirit:connectionRequired>
      <spirit:portMaps>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>CLK</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c7_ui_addn_clk_2</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
      </spirit:portMaps>
      <spirit:parameters>
        <spirit:parameter>
          <spirit:name>FREQ_HZ</spirit:name>
          <spirit:value spirit:format="float" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.C7_MMCM_CLKOUT2.FREQ_HZ" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MMCM_CLKOUT2_FREQ&apos;))">10</spirit:value>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>ASSOCIATED_ASYNC_RESET</spirit:name>
          <spirit:value spirit:id="BUSIFPARAM_VALUE.C7_MMCM_CLKOUT2.ASSOCIATED_ASYNC_RESET">c7_aresetn</spirit:value>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>PHASE</spirit:name>
          <spirit:value spirit:format="float" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.C7_MMCM_CLKOUT2.PHASE" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C7_PHASE&apos;))">0</spirit:value>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>CLK_DOMAIN</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C7_MMCM_CLKOUT2.CLK_DOMAIN"/>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>ASSOCIATED_BUSIF</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C7_MMCM_CLKOUT2.ASSOCIATED_BUSIF"/>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>ASSOCIATED_RESET</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C7_MMCM_CLKOUT2.ASSOCIATED_RESET"/>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>INSERT_VIP</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.C7_MMCM_CLKOUT2.INSERT_VIP">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
      </spirit:parameters>
      <spirit:vendorExtensions>
        <xilinx:busInterfaceInfo>
          <xilinx:enablement>
            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.C7_MMCM_CLKOUT2" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 ">false</xilinx:isEnabled>
          </xilinx:enablement>
        </xilinx:busInterfaceInfo>
      </spirit:vendorExtensions>
    </spirit:busInterface>
    <spirit:busInterface>
      <spirit:name>C7_MMCM_CLKOUT3</spirit:name>
      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
      <spirit:master/>
      <spirit:connectionRequired>true</spirit:connectionRequired>
      <spirit:portMaps>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>CLK</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c7_ui_addn_clk_3</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
      </spirit:portMaps>
      <spirit:parameters>
        <spirit:parameter>
          <spirit:name>FREQ_HZ</spirit:name>
          <spirit:value spirit:format="float" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.C7_MMCM_CLKOUT3.FREQ_HZ" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MMCM_CLKOUT3_FREQ&apos;))">10</spirit:value>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>ASSOCIATED_ASYNC_RESET</spirit:name>
          <spirit:value spirit:id="BUSIFPARAM_VALUE.C7_MMCM_CLKOUT3.ASSOCIATED_ASYNC_RESET">c7_aresetn</spirit:value>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>PHASE</spirit:name>
          <spirit:value spirit:format="float" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.C7_MMCM_CLKOUT3.PHASE" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C7_PHASE&apos;))">0</spirit:value>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>CLK_DOMAIN</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C7_MMCM_CLKOUT3.CLK_DOMAIN"/>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>ASSOCIATED_BUSIF</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C7_MMCM_CLKOUT3.ASSOCIATED_BUSIF"/>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>ASSOCIATED_RESET</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C7_MMCM_CLKOUT3.ASSOCIATED_RESET"/>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>INSERT_VIP</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.C7_MMCM_CLKOUT3.INSERT_VIP">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
      </spirit:parameters>
      <spirit:vendorExtensions>
        <xilinx:busInterfaceInfo>
          <xilinx:enablement>
            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.C7_MMCM_CLKOUT3" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 ">false</xilinx:isEnabled>
          </xilinx:enablement>
        </xilinx:busInterfaceInfo>
      </spirit:vendorExtensions>
    </spirit:busInterface>
    <spirit:busInterface>
      <spirit:name>C7_MMCM_CLKOUT4</spirit:name>
      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
      <spirit:master/>
      <spirit:connectionRequired>true</spirit:connectionRequired>
      <spirit:portMaps>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>CLK</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c7_ui_addn_clk_4</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
      </spirit:portMaps>
      <spirit:parameters>
        <spirit:parameter>
          <spirit:name>FREQ_HZ</spirit:name>
          <spirit:value spirit:format="float" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.C7_MMCM_CLKOUT4.FREQ_HZ" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MMCM_CLKOUT4_FREQ&apos;))">10</spirit:value>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>ASSOCIATED_ASYNC_RESET</spirit:name>
          <spirit:value spirit:id="BUSIFPARAM_VALUE.C7_MMCM_CLKOUT4.ASSOCIATED_ASYNC_RESET">c7_aresetn</spirit:value>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>PHASE</spirit:name>
          <spirit:value spirit:format="float" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.C7_MMCM_CLKOUT4.PHASE" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C7_PHASE&apos;))">0</spirit:value>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>CLK_DOMAIN</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C7_MMCM_CLKOUT4.CLK_DOMAIN"/>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>ASSOCIATED_BUSIF</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C7_MMCM_CLKOUT4.ASSOCIATED_BUSIF"/>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>ASSOCIATED_RESET</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C7_MMCM_CLKOUT4.ASSOCIATED_RESET"/>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>INSERT_VIP</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.C7_MMCM_CLKOUT4.INSERT_VIP">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
      </spirit:parameters>
      <spirit:vendorExtensions>
        <xilinx:busInterfaceInfo>
          <xilinx:enablement>
            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.C7_MMCM_CLKOUT4" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 ">false</xilinx:isEnabled>
          </xilinx:enablement>
        </xilinx:busInterfaceInfo>
      </spirit:vendorExtensions>
    </spirit:busInterface>
    <spirit:busInterface>
      <spirit:name>S7_AXI_CTRL</spirit:name>
      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm" spirit:version="1.0"/>
      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm_rtl" spirit:version="1.0"/>
      <spirit:slave>
        <spirit:memoryMapRef spirit:memoryMapRef="c7_s_axi_ctrl_memmap"/>
      </spirit:slave>
      <spirit:connectionRequired>true</spirit:connectionRequired>
      <spirit:portMaps>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>AWVALID</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c7_s_axi_ctrl_awvalid</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>AWREADY</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c7_s_axi_ctrl_awready</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>AWADDR</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c7_s_axi_ctrl_awaddr</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>WVALID</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c7_s_axi_ctrl_wvalid</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>WREADY</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c7_s_axi_ctrl_wready</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>WDATA</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c7_s_axi_ctrl_wdata</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>BVALID</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c7_s_axi_ctrl_bvalid</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>BREADY</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c7_s_axi_ctrl_bready</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>BRESP</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c7_s_axi_ctrl_bresp</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>ARVALID</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c7_s_axi_ctrl_arvalid</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>ARREADY</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c7_s_axi_ctrl_arready</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>ARADDR</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c7_s_axi_ctrl_araddr</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>RVALID</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c7_s_axi_ctrl_rvalid</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>RREADY</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c7_s_axi_ctrl_rready</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>RDATA</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c7_s_axi_ctrl_rdata</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>RRESP</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c7_s_axi_ctrl_rresp</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
      </spirit:portMaps>
      <spirit:parameters>
        <spirit:parameter>
          <spirit:name>FREQ_HZ</spirit:name>
          <spirit:value spirit:format="float" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.S7_AXI_CTRL.FREQ_HZ" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C7_FREQ_HZ&apos;))">100</spirit:value>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>DATA_WIDTH</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S7_AXI_CTRL.DATA_WIDTH">1</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>PROTOCOL</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S7_AXI_CTRL.PROTOCOL">AXI4LITE</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>ID_WIDTH</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S7_AXI_CTRL.ID_WIDTH">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>ADDR_WIDTH</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S7_AXI_CTRL.ADDR_WIDTH">1</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>AWUSER_WIDTH</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S7_AXI_CTRL.AWUSER_WIDTH">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>ARUSER_WIDTH</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S7_AXI_CTRL.ARUSER_WIDTH">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>WUSER_WIDTH</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S7_AXI_CTRL.WUSER_WIDTH">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>RUSER_WIDTH</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S7_AXI_CTRL.RUSER_WIDTH">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>BUSER_WIDTH</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S7_AXI_CTRL.BUSER_WIDTH">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>READ_WRITE_MODE</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S7_AXI_CTRL.READ_WRITE_MODE">READ_WRITE</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>HAS_BURST</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S7_AXI_CTRL.HAS_BURST">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>HAS_LOCK</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S7_AXI_CTRL.HAS_LOCK">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>HAS_PROT</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S7_AXI_CTRL.HAS_PROT">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>HAS_CACHE</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S7_AXI_CTRL.HAS_CACHE">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>HAS_QOS</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S7_AXI_CTRL.HAS_QOS">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>HAS_REGION</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S7_AXI_CTRL.HAS_REGION">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>HAS_WSTRB</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S7_AXI_CTRL.HAS_WSTRB">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>HAS_BRESP</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S7_AXI_CTRL.HAS_BRESP">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>HAS_RRESP</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S7_AXI_CTRL.HAS_RRESP">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>SUPPORTS_NARROW_BURST</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S7_AXI_CTRL.SUPPORTS_NARROW_BURST">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>NUM_READ_OUTSTANDING</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S7_AXI_CTRL.NUM_READ_OUTSTANDING">1</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>NUM_WRITE_OUTSTANDING</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S7_AXI_CTRL.NUM_WRITE_OUTSTANDING">1</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>MAX_BURST_LENGTH</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S7_AXI_CTRL.MAX_BURST_LENGTH">1</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>PHASE</spirit:name>
          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S7_AXI_CTRL.PHASE">0.000</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>CLK_DOMAIN</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S7_AXI_CTRL.CLK_DOMAIN"/>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>NUM_READ_THREADS</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S7_AXI_CTRL.NUM_READ_THREADS">1</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>NUM_WRITE_THREADS</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S7_AXI_CTRL.NUM_WRITE_THREADS">1</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>RUSER_BITS_PER_BYTE</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S7_AXI_CTRL.RUSER_BITS_PER_BYTE">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>WUSER_BITS_PER_BYTE</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S7_AXI_CTRL.WUSER_BITS_PER_BYTE">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>INSERT_VIP</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.S7_AXI_CTRL.INSERT_VIP">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
      </spirit:parameters>
      <spirit:vendorExtensions>
        <xilinx:busInterfaceInfo>
          <xilinx:enablement>
            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.S7_AXI_CTRL" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_USE_AXI&apos;)) = 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_ECC&apos;)) = &quot;ON&quot; ) ">false</xilinx:isEnabled>
          </xilinx:enablement>
        </xilinx:busInterfaceInfo>
      </spirit:vendorExtensions>
    </spirit:busInterface>
    <spirit:busInterface>
      <spirit:name>S7_AXI</spirit:name>
      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm" spirit:version="1.0"/>
      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm_rtl" spirit:version="1.0"/>
      <spirit:slave>
        <spirit:memoryMapRef spirit:memoryMapRef="c7_memmap"/>
      </spirit:slave>
      <spirit:connectionRequired>true</spirit:connectionRequired>
      <spirit:portMaps>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>AWID</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c7_s_axi_awid</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>AWADDR</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c7_s_axi_awaddr</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>AWLEN</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c7_s_axi_awlen</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>AWSIZE</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c7_s_axi_awsize</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>AWBURST</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c7_s_axi_awburst</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>AWLOCK</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c7_s_axi_awlock</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>AWCACHE</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c7_s_axi_awcache</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>AWPROT</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c7_s_axi_awprot</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>AWQOS</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c7_s_axi_awqos</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>AWVALID</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c7_s_axi_awvalid</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>AWREADY</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c7_s_axi_awready</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>WDATA</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c7_s_axi_wdata</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>WSTRB</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c7_s_axi_wstrb</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>WLAST</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c7_s_axi_wlast</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>WVALID</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c7_s_axi_wvalid</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>WREADY</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c7_s_axi_wready</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>BREADY</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c7_s_axi_bready</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>BID</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c7_s_axi_bid</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>BRESP</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c7_s_axi_bresp</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>BVALID</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c7_s_axi_bvalid</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>ARID</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c7_s_axi_arid</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>ARADDR</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c7_s_axi_araddr</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>ARLEN</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c7_s_axi_arlen</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>ARSIZE</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c7_s_axi_arsize</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>ARBURST</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c7_s_axi_arburst</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>ARLOCK</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c7_s_axi_arlock</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>ARCACHE</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c7_s_axi_arcache</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>ARPROT</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c7_s_axi_arprot</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>ARQOS</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c7_s_axi_arqos</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>ARVALID</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c7_s_axi_arvalid</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>ARREADY</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c7_s_axi_arready</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>RREADY</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c7_s_axi_rready</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>RID</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c7_s_axi_rid</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>RDATA</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c7_s_axi_rdata</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>RRESP</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c7_s_axi_rresp</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>RLAST</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c7_s_axi_rlast</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>RVALID</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c7_s_axi_rvalid</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
      </spirit:portMaps>
      <spirit:parameters>
        <spirit:parameter>
          <spirit:name>FREQ_HZ</spirit:name>
          <spirit:value spirit:format="float" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.S7_AXI.FREQ_HZ" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C7_FREQ_HZ&apos;))">100</spirit:value>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>DATA_WIDTH</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S7_AXI.DATA_WIDTH">1</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>PROTOCOL</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S7_AXI.PROTOCOL">AXI4LITE</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>ID_WIDTH</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S7_AXI.ID_WIDTH">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>ADDR_WIDTH</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S7_AXI.ADDR_WIDTH">1</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>AWUSER_WIDTH</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S7_AXI.AWUSER_WIDTH">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>ARUSER_WIDTH</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S7_AXI.ARUSER_WIDTH">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>WUSER_WIDTH</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S7_AXI.WUSER_WIDTH">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>RUSER_WIDTH</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S7_AXI.RUSER_WIDTH">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>BUSER_WIDTH</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S7_AXI.BUSER_WIDTH">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>READ_WRITE_MODE</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S7_AXI.READ_WRITE_MODE">READ_WRITE</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>HAS_BURST</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S7_AXI.HAS_BURST">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>HAS_LOCK</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S7_AXI.HAS_LOCK">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>HAS_PROT</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S7_AXI.HAS_PROT">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>HAS_CACHE</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S7_AXI.HAS_CACHE">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>HAS_QOS</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S7_AXI.HAS_QOS">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>HAS_REGION</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S7_AXI.HAS_REGION">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>HAS_WSTRB</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S7_AXI.HAS_WSTRB">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>HAS_BRESP</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S7_AXI.HAS_BRESP">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>HAS_RRESP</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S7_AXI.HAS_RRESP">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>SUPPORTS_NARROW_BURST</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S7_AXI.SUPPORTS_NARROW_BURST">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>NUM_READ_OUTSTANDING</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S7_AXI.NUM_READ_OUTSTANDING">1</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>NUM_WRITE_OUTSTANDING</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S7_AXI.NUM_WRITE_OUTSTANDING">1</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>MAX_BURST_LENGTH</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S7_AXI.MAX_BURST_LENGTH">1</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>PHASE</spirit:name>
          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S7_AXI.PHASE">0.000</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>CLK_DOMAIN</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S7_AXI.CLK_DOMAIN"/>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>NUM_READ_THREADS</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S7_AXI.NUM_READ_THREADS">1</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>NUM_WRITE_THREADS</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S7_AXI.NUM_WRITE_THREADS">1</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>RUSER_BITS_PER_BYTE</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S7_AXI.RUSER_BITS_PER_BYTE">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>WUSER_BITS_PER_BYTE</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S7_AXI.WUSER_BITS_PER_BYTE">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>INSERT_VIP</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.S7_AXI.INSERT_VIP">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
      </spirit:parameters>
      <spirit:vendorExtensions>
        <xilinx:busInterfaceInfo>
          <xilinx:enablement>
            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.S7_AXI" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
          </xilinx:enablement>
        </xilinx:busInterfaceInfo>
      </spirit:vendorExtensions>
    </spirit:busInterface>
    <spirit:busInterface>
      <spirit:name>C7_SYS_CLK</spirit:name>
      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="diff_clock" spirit:version="1.0"/>
      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="diff_clock_rtl" spirit:version="1.0"/>
      <spirit:slave/>
      <spirit:connectionRequired>true</spirit:connectionRequired>
      <spirit:portMaps>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>CLK_P</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c7_sys_clk_p</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>CLK_N</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c7_sys_clk_n</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
      </spirit:portMaps>
      <spirit:parameters>
        <spirit:parameter>
          <spirit:name>CAN_DEBUG</spirit:name>
          <spirit:value spirit:format="bool" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C7_SYS_CLK.CAN_DEBUG">false</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>FREQ_HZ</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C7_SYS_CLK.FREQ_HZ">100000000</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
      </spirit:parameters>
      <spirit:vendorExtensions>
        <xilinx:busInterfaceInfo>
          <xilinx:enablement>
            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.C7_SYS_CLK" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_SYSCLK_TYPE&apos;)) = &quot;DIFF&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_IS_CLK_SHARED&apos;)) = &quot;FALSE&quot; ">false</xilinx:isEnabled>
          </xilinx:enablement>
        </xilinx:busInterfaceInfo>
      </spirit:vendorExtensions>
    </spirit:busInterface>
    <spirit:busInterface>
      <spirit:name>C7_SYS_CLK_I</spirit:name>
      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
      <spirit:slave/>
      <spirit:connectionRequired>true</spirit:connectionRequired>
      <spirit:portMaps>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>CLK</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c7_sys_clk_i</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
      </spirit:portMaps>
      <spirit:parameters>
        <spirit:parameter>
          <spirit:name>FREQ_HZ</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C7_SYS_CLK_I.FREQ_HZ">100000000</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>PHASE</spirit:name>
          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C7_SYS_CLK_I.PHASE">0.000</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>CLK_DOMAIN</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C7_SYS_CLK_I.CLK_DOMAIN"/>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>ASSOCIATED_BUSIF</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C7_SYS_CLK_I.ASSOCIATED_BUSIF"/>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>ASSOCIATED_RESET</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C7_SYS_CLK_I.ASSOCIATED_RESET"/>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>INSERT_VIP</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.C7_SYS_CLK_I.INSERT_VIP">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
      </spirit:parameters>
      <spirit:vendorExtensions>
        <xilinx:busInterfaceInfo>
          <xilinx:enablement>
            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.C7_SYS_CLK_I" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_SYSCLK_TYPE&apos;)) != &quot;DIFF&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_IS_CLK_SHARED&apos;)) = &quot;FALSE&quot; ">false</xilinx:isEnabled>
          </xilinx:enablement>
        </xilinx:busInterfaceInfo>
      </spirit:vendorExtensions>
    </spirit:busInterface>
    <spirit:busInterface>
      <spirit:name>C7_ARESETN</spirit:name>
      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
      <spirit:slave/>
      <spirit:connectionRequired>true</spirit:connectionRequired>
      <spirit:portMaps>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>ARESETN</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>c7_aresetn</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
      </spirit:portMaps>
      <spirit:parameters>
        <spirit:parameter>
          <spirit:name>POLARITY</spirit:name>
          <spirit:value spirit:id="BUSIFPARAM_VALUE.C7_ARESETN.POLARITY">ACTIVE_LOW</spirit:value>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>INSERT_VIP</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.C7_ARESETN.INSERT_VIP">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
      </spirit:parameters>
    </spirit:busInterface>
  </spirit:busInterfaces>
  <spirit:memoryMaps>
    <spirit:memoryMap>
      <spirit:name>s_axi_ctrl_memmap</spirit:name>
      <spirit:addressBlock>
        <spirit:name>s_axi_ctrl_memaddr</spirit:name>
        <spirit:baseAddress spirit:format="long" spirit:resolve="dependent">0</spirit:baseAddress>
        <spirit:range spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C_S_AXI_CTRL_MEM_SIZE&apos;)) ) ">1048576</spirit:range>
        <spirit:width spirit:format="long">32</spirit:width>
        <spirit:usage>register</spirit:usage>
        <spirit:access>read-write</spirit:access>
        <spirit:vendorExtensions>
          <xilinx:addressBlockInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="ADDRBLOCK_ENABLEMENT.S_AXI_CTRL_MEMMAP.s_axi_ctrl_memaddr" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.USE_AXI&apos;)) = 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.ECC&apos;)) = &quot;ON&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:addressBlockInfo>
        </spirit:vendorExtensions>
      </spirit:addressBlock>
    </spirit:memoryMap>
    <spirit:memoryMap>
      <spirit:name>memmap</spirit:name>
      <spirit:addressBlock>
        <spirit:name>memaddr</spirit:name>
        <spirit:baseAddress spirit:format="long" spirit:resolve="dependent">0</spirit:baseAddress>
        <spirit:range spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C_S_AXI_MEM_SIZE&apos;)) ) ">1048576</spirit:range>
        <spirit:width spirit:format="long">32</spirit:width>
        <spirit:usage>memory</spirit:usage>
        <spirit:access>read-write</spirit:access>
        <spirit:vendorExtensions>
          <xilinx:addressBlockInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="ADDRBLOCK_ENABLEMENT.MEMMAP.memaddr" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:addressBlockInfo>
        </spirit:vendorExtensions>
      </spirit:addressBlock>
    </spirit:memoryMap>
    <spirit:memoryMap>
      <spirit:name>c0_s_axi_ctrl_memmap</spirit:name>
      <spirit:addressBlock>
        <spirit:name>c0_s_axi_ctrl_memaddr</spirit:name>
        <spirit:baseAddress spirit:format="long" spirit:resolve="dependent">0</spirit:baseAddress>
        <spirit:range spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_C_S_AXI_CTRL_MEM_SIZE&apos;)) ) ">1048576</spirit:range>
        <spirit:width spirit:format="long">32</spirit:width>
        <spirit:usage>register</spirit:usage>
        <spirit:access>read-write</spirit:access>
        <spirit:vendorExtensions>
          <xilinx:addressBlockInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="ADDRBLOCK_ENABLEMENT.C0_S_AXI_CTRL_MEMMAP.c0_s_axi_ctrl_memaddr" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_USE_AXI&apos;)) = 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_ECC&apos;)) = &quot;ON&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:addressBlockInfo>
        </spirit:vendorExtensions>
      </spirit:addressBlock>
    </spirit:memoryMap>
    <spirit:memoryMap>
      <spirit:name>c0_memmap</spirit:name>
      <spirit:addressBlock>
        <spirit:name>c0_memaddr</spirit:name>
        <spirit:baseAddress spirit:format="long" spirit:resolve="dependent">0</spirit:baseAddress>
        <spirit:range spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_C_S_AXI_MEM_SIZE&apos;)) ) ">1048576</spirit:range>
        <spirit:width spirit:format="long">32</spirit:width>
        <spirit:usage>memory</spirit:usage>
        <spirit:access>read-write</spirit:access>
        <spirit:vendorExtensions>
          <xilinx:addressBlockInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="ADDRBLOCK_ENABLEMENT.C0_MEMMAP.c0_memaddr" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:addressBlockInfo>
        </spirit:vendorExtensions>
      </spirit:addressBlock>
    </spirit:memoryMap>
    <spirit:memoryMap>
      <spirit:name>c1_s_axi_ctrl_memmap</spirit:name>
      <spirit:addressBlock>
        <spirit:name>c1_s_axi_ctrl_memaddr</spirit:name>
        <spirit:baseAddress spirit:format="long" spirit:resolve="dependent">0</spirit:baseAddress>
        <spirit:range spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_C_S_AXI_CTRL_MEM_SIZE&apos;)) ) ">1048576</spirit:range>
        <spirit:width spirit:format="long">32</spirit:width>
        <spirit:usage>register</spirit:usage>
        <spirit:access>read-write</spirit:access>
        <spirit:vendorExtensions>
          <xilinx:addressBlockInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="ADDRBLOCK_ENABLEMENT.C1_S_AXI_CTRL_MEMMAP.c1_s_axi_ctrl_memaddr" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_USE_AXI&apos;)) = 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_ECC&apos;)) = &quot;ON&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:addressBlockInfo>
        </spirit:vendorExtensions>
      </spirit:addressBlock>
    </spirit:memoryMap>
    <spirit:memoryMap>
      <spirit:name>c1_memmap</spirit:name>
      <spirit:addressBlock>
        <spirit:name>c1_memaddr</spirit:name>
        <spirit:baseAddress spirit:format="long" spirit:resolve="dependent">0</spirit:baseAddress>
        <spirit:range spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_C_S_AXI_MEM_SIZE&apos;)) ) ">1048576</spirit:range>
        <spirit:width spirit:format="long">32</spirit:width>
        <spirit:usage>memory</spirit:usage>
        <spirit:access>read-write</spirit:access>
        <spirit:vendorExtensions>
          <xilinx:addressBlockInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="ADDRBLOCK_ENABLEMENT.C1_MEMMAP.c1_memaddr" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:addressBlockInfo>
        </spirit:vendorExtensions>
      </spirit:addressBlock>
    </spirit:memoryMap>
    <spirit:memoryMap>
      <spirit:name>c2_s_axi_ctrl_memmap</spirit:name>
      <spirit:addressBlock>
        <spirit:name>c2_s_axi_ctrl_memaddr</spirit:name>
        <spirit:baseAddress spirit:format="long" spirit:resolve="dependent">0</spirit:baseAddress>
        <spirit:range spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_C_S_AXI_CTRL_MEM_SIZE&apos;)) ) ">1048576</spirit:range>
        <spirit:width spirit:format="long">32</spirit:width>
        <spirit:usage>register</spirit:usage>
        <spirit:access>read-write</spirit:access>
        <spirit:vendorExtensions>
          <xilinx:addressBlockInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="ADDRBLOCK_ENABLEMENT.C2_S_AXI_CTRL_MEMMAP.c2_s_axi_ctrl_memaddr" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_USE_AXI&apos;)) = 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_ECC&apos;)) = &quot;ON&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:addressBlockInfo>
        </spirit:vendorExtensions>
      </spirit:addressBlock>
    </spirit:memoryMap>
    <spirit:memoryMap>
      <spirit:name>c2_memmap</spirit:name>
      <spirit:addressBlock>
        <spirit:name>c2_memaddr</spirit:name>
        <spirit:baseAddress spirit:format="long" spirit:resolve="dependent">0</spirit:baseAddress>
        <spirit:range spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_C_S_AXI_MEM_SIZE&apos;)) ) ">1048576</spirit:range>
        <spirit:width spirit:format="long">32</spirit:width>
        <spirit:usage>memory</spirit:usage>
        <spirit:access>read-write</spirit:access>
        <spirit:vendorExtensions>
          <xilinx:addressBlockInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="ADDRBLOCK_ENABLEMENT.C2_MEMMAP.c2_memaddr" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:addressBlockInfo>
        </spirit:vendorExtensions>
      </spirit:addressBlock>
    </spirit:memoryMap>
    <spirit:memoryMap>
      <spirit:name>c3_s_axi_ctrl_memmap</spirit:name>
      <spirit:addressBlock>
        <spirit:name>c3_s_axi_ctrl_memaddr</spirit:name>
        <spirit:baseAddress spirit:format="long" spirit:resolve="dependent">0</spirit:baseAddress>
        <spirit:range spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_C_S_AXI_CTRL_MEM_SIZE&apos;)) ) ">1048576</spirit:range>
        <spirit:width spirit:format="long">32</spirit:width>
        <spirit:usage>register</spirit:usage>
        <spirit:access>read-write</spirit:access>
        <spirit:vendorExtensions>
          <xilinx:addressBlockInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="ADDRBLOCK_ENABLEMENT.C3_S_AXI_CTRL_MEMMAP.c3_s_axi_ctrl_memaddr" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_USE_AXI&apos;)) = 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_ECC&apos;)) = &quot;ON&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:addressBlockInfo>
        </spirit:vendorExtensions>
      </spirit:addressBlock>
    </spirit:memoryMap>
    <spirit:memoryMap>
      <spirit:name>c3_memmap</spirit:name>
      <spirit:addressBlock>
        <spirit:name>c3_memaddr</spirit:name>
        <spirit:baseAddress spirit:format="long" spirit:resolve="dependent">0</spirit:baseAddress>
        <spirit:range spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_C_S_AXI_MEM_SIZE&apos;)) ) ">1048576</spirit:range>
        <spirit:width spirit:format="long">32</spirit:width>
        <spirit:usage>memory</spirit:usage>
        <spirit:access>read-write</spirit:access>
        <spirit:vendorExtensions>
          <xilinx:addressBlockInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="ADDRBLOCK_ENABLEMENT.C3_MEMMAP.c3_memaddr" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:addressBlockInfo>
        </spirit:vendorExtensions>
      </spirit:addressBlock>
    </spirit:memoryMap>
    <spirit:memoryMap>
      <spirit:name>c4_s_axi_ctrl_memmap</spirit:name>
      <spirit:addressBlock>
        <spirit:name>c4_s_axi_ctrl_memaddr</spirit:name>
        <spirit:baseAddress spirit:format="long" spirit:resolve="dependent">0</spirit:baseAddress>
        <spirit:range spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_C_S_AXI_CTRL_MEM_SIZE&apos;)) ) ">1048576</spirit:range>
        <spirit:width spirit:format="long">32</spirit:width>
        <spirit:usage>register</spirit:usage>
        <spirit:access>read-write</spirit:access>
        <spirit:vendorExtensions>
          <xilinx:addressBlockInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="ADDRBLOCK_ENABLEMENT.C4_S_AXI_CTRL_MEMMAP.c4_s_axi_ctrl_memaddr" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_USE_AXI&apos;)) = 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_ECC&apos;)) = &quot;ON&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:addressBlockInfo>
        </spirit:vendorExtensions>
      </spirit:addressBlock>
    </spirit:memoryMap>
    <spirit:memoryMap>
      <spirit:name>c4_memmap</spirit:name>
      <spirit:addressBlock>
        <spirit:name>c4_memaddr</spirit:name>
        <spirit:baseAddress spirit:format="long" spirit:resolve="dependent">0</spirit:baseAddress>
        <spirit:range spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_C_S_AXI_MEM_SIZE&apos;)) ) ">1048576</spirit:range>
        <spirit:width spirit:format="long">32</spirit:width>
        <spirit:usage>memory</spirit:usage>
        <spirit:access>read-write</spirit:access>
        <spirit:vendorExtensions>
          <xilinx:addressBlockInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="ADDRBLOCK_ENABLEMENT.C4_MEMMAP.c4_memaddr" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:addressBlockInfo>
        </spirit:vendorExtensions>
      </spirit:addressBlock>
    </spirit:memoryMap>
    <spirit:memoryMap>
      <spirit:name>c5_s_axi_ctrl_memmap</spirit:name>
      <spirit:addressBlock>
        <spirit:name>c5_s_axi_ctrl_memaddr</spirit:name>
        <spirit:baseAddress spirit:format="long" spirit:resolve="dependent">0</spirit:baseAddress>
        <spirit:range spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_C_S_AXI_CTRL_MEM_SIZE&apos;)) ) ">1048576</spirit:range>
        <spirit:width spirit:format="long">32</spirit:width>
        <spirit:usage>register</spirit:usage>
        <spirit:access>read-write</spirit:access>
        <spirit:vendorExtensions>
          <xilinx:addressBlockInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="ADDRBLOCK_ENABLEMENT.C5_S_AXI_CTRL_MEMMAP.c5_s_axi_ctrl_memaddr" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_USE_AXI&apos;)) = 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_ECC&apos;)) = &quot;ON&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:addressBlockInfo>
        </spirit:vendorExtensions>
      </spirit:addressBlock>
    </spirit:memoryMap>
    <spirit:memoryMap>
      <spirit:name>c5_memmap</spirit:name>
      <spirit:addressBlock>
        <spirit:name>c5_memaddr</spirit:name>
        <spirit:baseAddress spirit:format="long" spirit:resolve="dependent">0</spirit:baseAddress>
        <spirit:range spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_C_S_AXI_MEM_SIZE&apos;)) ) ">1048576</spirit:range>
        <spirit:width spirit:format="long">32</spirit:width>
        <spirit:usage>memory</spirit:usage>
        <spirit:access>read-write</spirit:access>
        <spirit:vendorExtensions>
          <xilinx:addressBlockInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="ADDRBLOCK_ENABLEMENT.C5_MEMMAP.c5_memaddr" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:addressBlockInfo>
        </spirit:vendorExtensions>
      </spirit:addressBlock>
    </spirit:memoryMap>
    <spirit:memoryMap>
      <spirit:name>c6_s_axi_ctrl_memmap</spirit:name>
      <spirit:addressBlock>
        <spirit:name>c6_s_axi_ctrl_memaddr</spirit:name>
        <spirit:baseAddress spirit:format="long" spirit:resolve="dependent">0</spirit:baseAddress>
        <spirit:range spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_C_S_AXI_CTRL_MEM_SIZE&apos;)) ) ">1048576</spirit:range>
        <spirit:width spirit:format="long">32</spirit:width>
        <spirit:usage>register</spirit:usage>
        <spirit:access>read-write</spirit:access>
        <spirit:vendorExtensions>
          <xilinx:addressBlockInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="ADDRBLOCK_ENABLEMENT.C6_S_AXI_CTRL_MEMMAP.c6_s_axi_ctrl_memaddr" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_USE_AXI&apos;)) = 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_ECC&apos;)) = &quot;ON&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:addressBlockInfo>
        </spirit:vendorExtensions>
      </spirit:addressBlock>
    </spirit:memoryMap>
    <spirit:memoryMap>
      <spirit:name>c6_memmap</spirit:name>
      <spirit:addressBlock>
        <spirit:name>c6_memaddr</spirit:name>
        <spirit:baseAddress spirit:format="long" spirit:resolve="dependent">0</spirit:baseAddress>
        <spirit:range spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_C_S_AXI_MEM_SIZE&apos;)) ) ">1048576</spirit:range>
        <spirit:width spirit:format="long">32</spirit:width>
        <spirit:usage>memory</spirit:usage>
        <spirit:access>read-write</spirit:access>
        <spirit:vendorExtensions>
          <xilinx:addressBlockInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="ADDRBLOCK_ENABLEMENT.C6_MEMMAP.c6_memaddr" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:addressBlockInfo>
        </spirit:vendorExtensions>
      </spirit:addressBlock>
    </spirit:memoryMap>
    <spirit:memoryMap>
      <spirit:name>c7_s_axi_ctrl_memmap</spirit:name>
      <spirit:addressBlock>
        <spirit:name>c7_s_axi_ctrl_memaddr</spirit:name>
        <spirit:baseAddress spirit:format="long" spirit:resolve="dependent">0</spirit:baseAddress>
        <spirit:range spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_C_S_AXI_CTRL_MEM_SIZE&apos;)) ) ">1048576</spirit:range>
        <spirit:width spirit:format="long">32</spirit:width>
        <spirit:usage>register</spirit:usage>
        <spirit:access>read-write</spirit:access>
        <spirit:vendorExtensions>
          <xilinx:addressBlockInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="ADDRBLOCK_ENABLEMENT.C7_S_AXI_CTRL_MEMMAP.c7_s_axi_ctrl_memaddr" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_USE_AXI&apos;)) = 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_ECC&apos;)) = &quot;ON&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:addressBlockInfo>
        </spirit:vendorExtensions>
      </spirit:addressBlock>
    </spirit:memoryMap>
    <spirit:memoryMap>
      <spirit:name>c7_memmap</spirit:name>
      <spirit:addressBlock>
        <spirit:name>c7_memaddr</spirit:name>
        <spirit:baseAddress spirit:format="long" spirit:resolve="dependent">0</spirit:baseAddress>
        <spirit:range spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_C_S_AXI_MEM_SIZE&apos;)) ) ">1048576</spirit:range>
        <spirit:width spirit:format="long">32</spirit:width>
        <spirit:usage>memory</spirit:usage>
        <spirit:access>read-write</spirit:access>
        <spirit:vendorExtensions>
          <xilinx:addressBlockInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="ADDRBLOCK_ENABLEMENT.C7_MEMMAP.c7_memaddr" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:addressBlockInfo>
        </spirit:vendorExtensions>
      </spirit:addressBlock>
    </spirit:memoryMap>
  </spirit:memoryMaps>
  <spirit:model>
    <spirit:views>
      <spirit:view>
        <spirit:name>xilinx_verilogbehavioralsimulation</spirit:name>
        <spirit:displayName>Verilog Simulation</spirit:displayName>
        <spirit:envIdentifier>verilogSource:vivado.xilinx.com:simulation</spirit:envIdentifier>
        <spirit:language>verilog</spirit:language>
        <spirit:modelName>_dummy_mig_model</spirit:modelName>
        <spirit:fileSetRef>
          <spirit:localName>xilinx_verilogbehavioralsimulation_view_fileset</spirit:localName>
        </spirit:fileSetRef>
        <spirit:parameters>
          <spirit:parameter>
            <spirit:name>GENtimestamp</spirit:name>
            <spirit:value>Wed Apr 08 15:45:02 UTC 2020</spirit:value>
          </spirit:parameter>
          <spirit:parameter>
            <spirit:name>outputProductCRC</spirit:name>
            <spirit:value>9:7aceed45</spirit:value>
          </spirit:parameter>
        </spirit:parameters>
      </spirit:view>
      <spirit:view>
        <spirit:name>xilinx_vhdlsimulationwrapper</spirit:name>
        <spirit:displayName>VHDL Simulation Wrapper</spirit:displayName>
        <spirit:envIdentifier>vhdlSource:vivado.xilinx.com:simulation.wrapper</spirit:envIdentifier>
        <spirit:language>vhdl</spirit:language>
        <spirit:modelName>mig</spirit:modelName>
        <spirit:fileSetRef>
          <spirit:localName>xilinx_vhdlsimulationwrapper_view_fileset</spirit:localName>
        </spirit:fileSetRef>
        <spirit:parameters>
          <spirit:parameter>
            <spirit:name>GENtimestamp</spirit:name>
            <spirit:value>Wed Apr 08 15:45:07 UTC 2020</spirit:value>
          </spirit:parameter>
          <spirit:parameter>
            <spirit:name>outputProductCRC</spirit:name>
            <spirit:value>9:7aceed45</spirit:value>
          </spirit:parameter>
        </spirit:parameters>
      </spirit:view>
      <spirit:view>
        <spirit:name>xilinx_anylanguagesynthesis</spirit:name>
        <spirit:displayName>Synthesis</spirit:displayName>
        <spirit:envIdentifier>:vivado.xilinx.com:synthesis</spirit:envIdentifier>
        <spirit:modelName>_dummy_mig_model</spirit:modelName>
        <spirit:fileSetRef>
          <spirit:localName>xilinx_anylanguagesynthesis_view_fileset</spirit:localName>
        </spirit:fileSetRef>
        <spirit:parameters>
          <spirit:parameter>
            <spirit:name>GENtimestamp</spirit:name>
            <spirit:value>Wed Apr 08 20:59:42 UTC 2020</spirit:value>
          </spirit:parameter>
          <spirit:parameter>
            <spirit:name>outputProductCRC</spirit:name>
            <spirit:value>9:af6afeaf</spirit:value>
          </spirit:parameter>
        </spirit:parameters>
      </spirit:view>
      <spirit:view>
        <spirit:name>xilinx_synthesisconstraints</spirit:name>
        <spirit:displayName>Synthesis Constraints</spirit:displayName>
        <spirit:envIdentifier>:vivado.xilinx.com:synthesis.constraints</spirit:envIdentifier>
        <spirit:parameters>
          <spirit:parameter>
            <spirit:name>outputProductCRC</spirit:name>
            <spirit:value>9:af6afeaf</spirit:value>
          </spirit:parameter>
        </spirit:parameters>
      </spirit:view>
      <spirit:view>
        <spirit:name>xilinx_vhdlsynthesiswrapper</spirit:name>
        <spirit:displayName>VHDL Synthesis Wrapper</spirit:displayName>
        <spirit:envIdentifier>vhdlSource:vivado.xilinx.com:synthesis.wrapper</spirit:envIdentifier>
        <spirit:language>vhdl</spirit:language>
        <spirit:modelName>mig</spirit:modelName>
        <spirit:fileSetRef>
          <spirit:localName>xilinx_vhdlsynthesiswrapper_view_fileset</spirit:localName>
        </spirit:fileSetRef>
        <spirit:parameters>
          <spirit:parameter>
            <spirit:name>GENtimestamp</spirit:name>
            <spirit:value>Wed Apr 08 20:59:48 UTC 2020</spirit:value>
          </spirit:parameter>
          <spirit:parameter>
            <spirit:name>outputProductCRC</spirit:name>
            <spirit:value>9:af6afeaf</spirit:value>
          </spirit:parameter>
        </spirit:parameters>
      </spirit:view>
      <spirit:view>
        <spirit:name>xilinx_implementation</spirit:name>
        <spirit:displayName>Implementation</spirit:displayName>
        <spirit:envIdentifier>:vivado.xilinx.com:implementation</spirit:envIdentifier>
        <spirit:modelName>_dummy_mig_model</spirit:modelName>
        <spirit:fileSetRef>
          <spirit:localName>xilinx_implementation_view_fileset</spirit:localName>
        </spirit:fileSetRef>
        <spirit:parameters>
          <spirit:parameter>
            <spirit:name>GENtimestamp</spirit:name>
            <spirit:value>Wed Apr 08 20:59:53 UTC 2020</spirit:value>
          </spirit:parameter>
          <spirit:parameter>
            <spirit:name>outputProductCRC</spirit:name>
            <spirit:value>9:af6afeaf</spirit:value>
          </spirit:parameter>
        </spirit:parameters>
      </spirit:view>
      <spirit:view>
        <spirit:name>xilinx_externalfiles</spirit:name>
        <spirit:displayName>External Files</spirit:displayName>
        <spirit:envIdentifier>:vivado.xilinx.com:external.files</spirit:envIdentifier>
        <spirit:fileSetRef>
          <spirit:localName>xilinx_externalfiles_view_fileset</spirit:localName>
        </spirit:fileSetRef>
        <spirit:parameters>
          <spirit:parameter>
            <spirit:name>GENtimestamp</spirit:name>
            <spirit:value>Wed Apr 08 21:04:46 UTC 2020</spirit:value>
          </spirit:parameter>
          <spirit:parameter>
            <spirit:name>outputProductCRC</spirit:name>
            <spirit:value>9:af6afeaf</spirit:value>
          </spirit:parameter>
        </spirit:parameters>
      </spirit:view>
    </spirit:views>
    <spirit:ports>
      <spirit:port>
        <spirit:name>device_temp_i</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">11</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.device_temp_i" xilinx:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.TEMP_MON_CONTROL&apos;)) = &quot;EXTERNAL&quot; and ( spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;DDR2&quot; )) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>sys_rst</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
      </spirit:port>
      <spirit:port>
        <spirit:name>clk_ref_p</spirit:name>
        <spirit:displayName>Clock P</spirit:displayName>
        <spirit:description>Clock P</spirit:description>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.clk_ref_p" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.REFCLK_TYPE&apos;)) = &quot;DIFF&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.REFCLK_TYPE&apos;)) != &quot;NONE&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>clk_ref_n</spirit:name>
        <spirit:displayName>Clock P</spirit:displayName>
        <spirit:description>Clock P</spirit:description>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.clk_ref_n" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.REFCLK_TYPE&apos;)) = &quot;DIFF&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.REFCLK_TYPE&apos;)) != &quot;NONE&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>clk_ref_i</spirit:name>
        <spirit:displayName>Clock P</spirit:displayName>
        <spirit:description>Clock P</spirit:description>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.clk_ref_i" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.REFCLK_TYPE&apos;)) != &quot;DIFF&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.REFCLK_TYPE&apos;)) != &quot;NONE&quot; ">true</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>ddr3_dq</spirit:name>
        <spirit:displayName>Data</spirit:displayName>
        <spirit:description>Data</spirit:description>
        <spirit:wire>
          <spirit:direction>inout</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.DDR3_DQ_WIDTH&apos;)) )- 1 ">63</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.ddr3_dq" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;DDR3&quot; ">true</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>ddr3_dqs_p</spirit:name>
        <spirit:displayName>Data Strobe</spirit:displayName>
        <spirit:description>Data Strobe</spirit:description>
        <spirit:wire>
          <spirit:direction>inout</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.DDR3_DQS_WIDTH&apos;)) )- 1 ">7</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.ddr3_dqs_p" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;DDR3&quot; ">true</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>ddr3_dqs_n</spirit:name>
        <spirit:displayName>Data Strobe</spirit:displayName>
        <spirit:description>Data Strobe</spirit:description>
        <spirit:wire>
          <spirit:direction>inout</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.DDR3_DQS_WIDTH&apos;)) )- 1 ">7</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.ddr3_dqs_n" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;DDR3&quot; ">true</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>ddr3_addr</spirit:name>
        <spirit:displayName>Address</spirit:displayName>
        <spirit:description>Address</spirit:description>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.DDR3_ROW_WIDTH&apos;)) )- 1 ">13</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.ddr3_addr" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;DDR3&quot; ">true</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>ddr3_ba</spirit:name>
        <spirit:displayName>Bank Address</spirit:displayName>
        <spirit:description>Bank Address</spirit:description>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.DDR3_BANK_WIDTH&apos;)) )- 1 ">2</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.ddr3_ba" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;DDR3&quot; and ( spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;DDR2&quot; ) ">true</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>ddr3_ras_n</spirit:name>
        <spirit:displayName>row address strobe</spirit:displayName>
        <spirit:description>row address strobe</spirit:description>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.ddr3_ras_n" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;DDR3&quot; and ( spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;DDR2&quot; ) ">true</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>ddr3_cas_n</spirit:name>
        <spirit:displayName>column address strobe</spirit:displayName>
        <spirit:description>column address strobe</spirit:description>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.ddr3_cas_n" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;DDR3&quot; and ( spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;DDR2&quot; ) ">true</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>ddr3_we_n</spirit:name>
        <spirit:displayName>write enable</spirit:displayName>
        <spirit:description>write enable</spirit:description>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.ddr3_we_n" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;DDR3&quot; and ( spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;DDR2&quot; ) ">true</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>ddr3_reset_n</spirit:name>
        <spirit:displayName>reset to memory device</spirit:displayName>
        <spirit:description>reset to memory device</spirit:description>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.ddr3_reset_n" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;DDR3&quot; ">true</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>ddr3_ck_p</spirit:name>
        <spirit:displayName>clock to memory device</spirit:displayName>
        <spirit:description>clock to memory device</spirit:description>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.DDR3_CK_WIDTH&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.ddr3_ck_p" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;DDR3&quot; ">true</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>ddr3_ck_n</spirit:name>
        <spirit:displayName>clock to memory device</spirit:displayName>
        <spirit:description>clock to memory device</spirit:description>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.DDR3_CK_WIDTH&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.ddr3_ck_n" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;DDR3&quot; ">true</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>ddr3_cke</spirit:name>
        <spirit:displayName>clock enable</spirit:displayName>
        <spirit:description>clock enable</spirit:description>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.DDR3_CKE_WIDTH&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.ddr3_cke" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;DDR3&quot; ">true</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>ddr3_cs_n</spirit:name>
        <spirit:displayName>chip select</spirit:displayName>
        <spirit:description>chip select</spirit:description>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.DDR3_CS_WIDTH&apos;)) * spirit:decode(id(&apos;MODELPARAM_VALUE.DDR3_nCS_PER_RANK&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.ddr3_cs_n" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.DDR3_USE_CS_PORT&apos;)) = 1 ">true</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>ddr3_dm</spirit:name>
        <spirit:displayName>data mask</spirit:displayName>
        <spirit:description>data mask</spirit:description>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.DDR3_DM_WIDTH&apos;)) )- 1 ">7</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.ddr3_dm" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.DDR3_USE_DM_PORT&apos;)) = 1 ">true</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>ddr3_odt</spirit:name>
        <spirit:displayName>on die termination</spirit:displayName>
        <spirit:description>on die termination</spirit:description>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.DDR3_ODT_WIDTH&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.ddr3_odt" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;DDR3&quot; and (( spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;DDR2&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.DDR3_USE_ODT_PORT&apos;)) = 1 ) ">true</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>ddr3_parity</spirit:name>
        <spirit:displayName>parity bit</spirit:displayName>
        <spirit:description>parity bit</spirit:description>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.ddr3_parity" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.DDR3_REG_CTRL&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>ddr3_dbg_pi_counter_read_val</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">4</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.ddr3_dbg_pi_counter_read_val" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.DDR3_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>ddr3_dbg_byte_sel</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.DDR3_DQS_CNT_WIDTH&apos;)) + 1 )- 1 ">3</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.ddr3_dbg_byte_sel" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.DDR3_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>ddr3_dbg_sel_pi_incdec</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.ddr3_dbg_sel_pi_incdec" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.DDR3_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>ddr3_dbg_pi_f_inc</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.ddr3_dbg_pi_f_inc" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.DDR3_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>ddr3_dbg_pi_f_dec</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.ddr3_dbg_pi_f_dec" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.DDR3_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>ddr3_dbg_sel_po_incdec</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.ddr3_dbg_sel_po_incdec" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.DDR3_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>ddr3_dbg_po_f_inc</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.ddr3_dbg_po_f_inc" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.DDR3_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>ddr3_dbg_po_f_stg23_sel</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.ddr3_dbg_po_f_stg23_sel" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.DDR3_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>ddr3_dbg_po_f_dec</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.ddr3_dbg_po_f_dec" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.DDR3_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>ddr3_dbg_po_counter_read_val</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">7</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.ddr3_dbg_po_counter_read_val" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.DDR3_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>ddr3_ila_wrpath</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">254</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.ddr3_ila_wrpath" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.DDR3_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>ddr3_ila_rdpath</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">1022</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.ddr3_ila_rdpath" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.DDR3_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>ddr3_ila_basic</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">126</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.ddr3_ila_basic" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.DDR3_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>ddr3_vio_sync_out</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">34</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.ddr3_vio_sync_out" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.DDR3_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>ddr2_dq</spirit:name>
        <spirit:displayName>Data</spirit:displayName>
        <spirit:description>Data</spirit:description>
        <spirit:wire>
          <spirit:direction>inout</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.DDR2_DQ_WIDTH&apos;)) )- 1 ">7</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.ddr2_dq" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;DDR2&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>ddr2_dqs_p</spirit:name>
        <spirit:displayName>Data Strobe</spirit:displayName>
        <spirit:description>Data Strobe</spirit:description>
        <spirit:wire>
          <spirit:direction>inout</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.DDR2_DQS_WIDTH&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.ddr2_dqs_p" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;DDR2&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>ddr2_dqs_n</spirit:name>
        <spirit:displayName>Data Strobe</spirit:displayName>
        <spirit:description>Data Strobe</spirit:description>
        <spirit:wire>
          <spirit:direction>inout</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.DDR2_DQS_WIDTH&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.ddr2_dqs_n" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;DDR2&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>ddr2_addr</spirit:name>
        <spirit:displayName>Address</spirit:displayName>
        <spirit:description>Address</spirit:description>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.DDR2_ROW_WIDTH&apos;)) )- 1 ">13</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.ddr2_addr" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;DDR2&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>ddr2_ba</spirit:name>
        <spirit:displayName>Bank Address</spirit:displayName>
        <spirit:description>Bank Address</spirit:description>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.DDR2_BANK_WIDTH&apos;)) )- 1 ">2</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.ddr2_ba" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;DDR2&quot; and ( spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;DDR2&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>ddr2_ras_n</spirit:name>
        <spirit:displayName>row address strobe</spirit:displayName>
        <spirit:description>row address strobe</spirit:description>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.ddr2_ras_n" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;DDR2&quot; and ( spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;DDR2&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>ddr2_cas_n</spirit:name>
        <spirit:displayName>column address strobe</spirit:displayName>
        <spirit:description>column address strobe</spirit:description>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.ddr2_cas_n" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;DDR2&quot; and ( spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;DDR2&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>ddr2_we_n</spirit:name>
        <spirit:displayName>write enable</spirit:displayName>
        <spirit:description>write enable</spirit:description>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.ddr2_we_n" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;DDR2&quot; and ( spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;DDR2&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>ddr2_reset_n</spirit:name>
        <spirit:displayName>reset to memory device</spirit:displayName>
        <spirit:description>reset to memory device</spirit:description>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.ddr2_reset_n" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;DDR3&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>ddr2_ck_p</spirit:name>
        <spirit:displayName>clock to memory device</spirit:displayName>
        <spirit:description>clock to memory device</spirit:description>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.DDR2_CK_WIDTH&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.ddr2_ck_p" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;DDR2&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>ddr2_ck_n</spirit:name>
        <spirit:displayName>clock to memory device</spirit:displayName>
        <spirit:description>clock to memory device</spirit:description>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.DDR2_CK_WIDTH&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.ddr2_ck_n" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;DDR2&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>ddr2_cke</spirit:name>
        <spirit:displayName>clock enable</spirit:displayName>
        <spirit:description>clock enable</spirit:description>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.DDR2_CKE_WIDTH&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.ddr2_cke" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;DDR2&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>ddr2_cs_n</spirit:name>
        <spirit:displayName>chip select</spirit:displayName>
        <spirit:description>chip select</spirit:description>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.DDR2_CS_WIDTH&apos;)) * spirit:decode(id(&apos;MODELPARAM_VALUE.DDR2_nCS_PER_RANK&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.ddr2_cs_n" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.DDR2_USE_CS_PORT&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>ddr2_dm</spirit:name>
        <spirit:displayName>data mask</spirit:displayName>
        <spirit:description>data mask</spirit:description>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.DDR2_DM_WIDTH&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.ddr2_dm" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.DDR2_USE_DM_PORT&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>ddr2_odt</spirit:name>
        <spirit:displayName>on die termination</spirit:displayName>
        <spirit:description>on die termination</spirit:description>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.DDR2_ODT_WIDTH&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.ddr2_odt" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;DDR2&quot; and (( spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;DDR2&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.DDR2_USE_ODT_PORT&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>ddr2_parity</spirit:name>
        <spirit:displayName>parity bit</spirit:displayName>
        <spirit:description>parity bit</spirit:description>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.ddr2_parity" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.DDR2_REG_CTRL&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>ddr2_dbg_pi_counter_read_val</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">4</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.ddr2_dbg_pi_counter_read_val" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.DDR2_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>ddr2_dbg_byte_sel</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.DDR2_DQS_CNT_WIDTH&apos;)) + 1 )- 1 ">1</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.ddr2_dbg_byte_sel" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.DDR2_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>ddr2_dbg_sel_pi_incdec</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.ddr2_dbg_sel_pi_incdec" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.DDR2_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>ddr2_dbg_pi_f_inc</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.ddr2_dbg_pi_f_inc" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.DDR2_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>ddr2_dbg_pi_f_dec</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.ddr2_dbg_pi_f_dec" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.DDR2_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>ddr2_dbg_sel_po_incdec</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.ddr2_dbg_sel_po_incdec" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.DDR2_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>ddr2_dbg_po_f_inc</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.ddr2_dbg_po_f_inc" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.DDR2_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>ddr2_dbg_po_f_stg23_sel</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.ddr2_dbg_po_f_stg23_sel" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.DDR2_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>ddr2_dbg_po_f_dec</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.ddr2_dbg_po_f_dec" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.DDR2_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>ddr2_dbg_po_counter_read_val</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">7</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.ddr2_dbg_po_counter_read_val" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.DDR2_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>ddr2_ila_wrpath</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">254</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.ddr2_ila_wrpath" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.DDR2_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>ddr2_ila_rdpath</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">1022</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.ddr2_ila_rdpath" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.DDR2_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>ddr2_ila_basic</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">126</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.ddr2_ila_basic" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.DDR2_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>ddr2_vio_sync_out</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">34</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.ddr2_vio_sync_out" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.DDR2_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>lpddr2_dq</spirit:name>
        <spirit:displayName>Data</spirit:displayName>
        <spirit:description>Data</spirit:description>
        <spirit:wire>
          <spirit:direction>inout</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.LPDDR2_DQ_WIDTH&apos;)) )- 1 ">7</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.lpddr2_dq" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;LPDDR2&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>lpddr2_dqs_p</spirit:name>
        <spirit:displayName>Data Strobe</spirit:displayName>
        <spirit:description>Data Strobe</spirit:description>
        <spirit:wire>
          <spirit:direction>inout</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.LPDDR2_DQS_WIDTH&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.lpddr2_dqs_p" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;LPDDR2&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>lpddr2_dqs_n</spirit:name>
        <spirit:displayName>Data Strobe</spirit:displayName>
        <spirit:description>Data Strobe</spirit:description>
        <spirit:wire>
          <spirit:direction>inout</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.LPDDR2_DQS_WIDTH&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.lpddr2_dqs_n" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;LPDDR2&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>lpddr2_ca</spirit:name>
        <spirit:displayName>Address</spirit:displayName>
        <spirit:description>Address</spirit:description>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">9</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.lpddr2_ca" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;LPDDR2&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>lpddr2_ck_p</spirit:name>
        <spirit:displayName>clock to memory device</spirit:displayName>
        <spirit:description>clock to memory device</spirit:description>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.LPDDR2_CK_WIDTH&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.lpddr2_ck_p" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;LPDDR2&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>lpddr2_ck_n</spirit:name>
        <spirit:displayName>clock to memory device</spirit:displayName>
        <spirit:description>clock to memory device</spirit:description>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.LPDDR2_CK_WIDTH&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.lpddr2_ck_n" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;LPDDR2&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>lpddr2_cke</spirit:name>
        <spirit:displayName>clock enable</spirit:displayName>
        <spirit:description>clock enable</spirit:description>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.LPDDR2_CKE_WIDTH&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.lpddr2_cke" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;LPDDR2&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>lpddr2_cs_n</spirit:name>
        <spirit:displayName>chip select</spirit:displayName>
        <spirit:description>chip select</spirit:description>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.LPDDR2_CS_WIDTH&apos;)) * spirit:decode(id(&apos;MODELPARAM_VALUE.LPDDR2_nCS_PER_RANK&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.lpddr2_cs_n" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;LPDDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.LPDDR2_USE_CS_PORT&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>lpddr2_dm</spirit:name>
        <spirit:displayName>data mask</spirit:displayName>
        <spirit:description>data mask</spirit:description>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.LPDDR2_DM_WIDTH&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.lpddr2_dm" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;LPDDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.LPDDR2_USE_DM_PORT&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>lpddr2_parity</spirit:name>
        <spirit:displayName>parity bit</spirit:displayName>
        <spirit:description>parity bit</spirit:description>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.lpddr2_parity" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;LPDDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.LPDDR2_REG_CTRL&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>lpddr2_dbg_pi_counter_read_val</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">4</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.lpddr2_dbg_pi_counter_read_val" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;LPDDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.LPDDR2_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>lpddr2_dbg_byte_sel</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.LPDDR2_DQS_CNT_WIDTH&apos;)) + 1 )- 1 ">1</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.lpddr2_dbg_byte_sel" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;LPDDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.LPDDR2_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>lpddr2_dbg_sel_pi_incdec</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.lpddr2_dbg_sel_pi_incdec" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;LPDDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.LPDDR2_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>lpddr2_dbg_pi_f_inc</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.lpddr2_dbg_pi_f_inc" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;LPDDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.LPDDR2_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>lpddr2_dbg_pi_f_dec</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.lpddr2_dbg_pi_f_dec" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;LPDDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.LPDDR2_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>lpddr2_dbg_sel_po_incdec</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.lpddr2_dbg_sel_po_incdec" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;LPDDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.LPDDR2_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>lpddr2_dbg_po_f_inc</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.lpddr2_dbg_po_f_inc" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;LPDDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.LPDDR2_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>lpddr2_dbg_po_f_stg23_sel</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.lpddr2_dbg_po_f_stg23_sel" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;LPDDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.LPDDR2_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>lpddr2_dbg_po_f_dec</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.lpddr2_dbg_po_f_dec" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;LPDDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.LPDDR2_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>lpddr2_dbg_po_counter_read_val</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">7</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.lpddr2_dbg_po_counter_read_val" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;LPDDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.LPDDR2_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>lpddr2_ila_wrpath</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">254</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.lpddr2_ila_wrpath" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;LPDDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.LPDDR2_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>lpddr2_ila_rdpath</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">1022</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.lpddr2_ila_rdpath" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;LPDDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.LPDDR2_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>lpddr2_ila_basic</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">126</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.lpddr2_ila_basic" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;LPDDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.LPDDR2_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>lpddr2_vio_sync_out</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">34</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.lpddr2_vio_sync_out" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;LPDDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.LPDDR2_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>dbg_byte_sel</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.DQS_CNT_WIDTH&apos;)) + 1 )- 1 ">1</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.dbg_byte_sel" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;DDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;LPDDR2&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>dbg_sel_pi_incdec</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.dbg_sel_pi_incdec" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;DDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;LPDDR2&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>dbg_pi_f_inc</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.dbg_pi_f_inc" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;DDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;LPDDR2&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>dbg_pi_f_dec</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.dbg_pi_f_dec" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;DDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;LPDDR2&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>dbg_sel_po_incdec</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.dbg_sel_po_incdec" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;DDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;LPDDR2&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>dbg_po_f_inc</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.dbg_po_f_inc" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;DDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;LPDDR2&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>dbg_po_f_stg23_sel</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.dbg_po_f_stg23_sel" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;DDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;LPDDR2&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>dbg_po_f_dec</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.dbg_po_f_dec" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;DDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;LPDDR2&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>dbg_po_counter_read_val</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">7</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.dbg_po_counter_read_val" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;DDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;LPDDR2&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>app_addr</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.DDRX_ADDR_WIDTH&apos;)) )- 1 ">7</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.app_addr" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;DDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;LPDDR2&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">true</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>app_cmd</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">2</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.app_cmd" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;DDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;LPDDR2&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">true</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>app_en</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.app_en" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;DDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;LPDDR2&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">true</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>app_wdf_data</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.DDRX_nCK_PER_CLK&apos;)) * 2 * spirit:decode(id(&apos;MODELPARAM_VALUE.DDRX_DATA_WIDTH&apos;)) )- 1 ">31</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.app_wdf_data" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;DDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;LPDDR2&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">true</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>app_wdf_end</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.app_wdf_end" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;DDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;LPDDR2&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">true</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>app_wdf_mask</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.DDRX_nCK_PER_CLK&apos;)) * 2 * spirit:decode(id(&apos;MODELPARAM_VALUE.DDRX_DATA_WIDTH&apos;)) / 8 )- 1 ">3</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.app_wdf_mask" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;DDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;LPDDR2&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">true</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>app_wdf_wren</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.app_wdf_wren" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;DDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;LPDDR2&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">true</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>app_correct_en_i</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.app_correct_en_i" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;DDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;LPDDR2&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.ECC&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>app_rd_data</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.DDRX_nCK_PER_CLK&apos;)) * 2 * spirit:decode(id(&apos;MODELPARAM_VALUE.DDRX_DATA_WIDTH&apos;)) )- 1 ">31</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.app_rd_data" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;DDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;LPDDR2&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">true</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>app_rd_data_end</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.app_rd_data_end" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;DDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;LPDDR2&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">true</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>app_rd_data_valid</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.app_rd_data_valid" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;DDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;LPDDR2&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">true</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>app_rdy</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.app_rdy" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;DDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;LPDDR2&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">true</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>app_wdf_rdy</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.app_wdf_rdy" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;DDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;LPDDR2&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">true</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>app_sr_req</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.app_sr_req" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;DDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;LPDDR2&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">true</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>app_sr_active</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.app_sr_active" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;DDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;LPDDR2&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">true</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>app_ref_req</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.app_ref_req" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;DDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;LPDDR2&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">true</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>app_ref_ack</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.app_ref_ack" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;DDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;LPDDR2&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">true</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>app_zq_req</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.app_zq_req" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;DDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;LPDDR2&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">true</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>app_zq_ack</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.app_zq_ack" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;DDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;LPDDR2&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">true</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>app_raw_not_ecc</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( 2 * spirit:decode(id(&apos;MODELPARAM_VALUE.DDRX_nCK_PER_CLK&apos;)) )- 1 ">3</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.app_raw_not_ecc" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;DDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;LPDDR2&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.ECC&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>app_ecc_multiple_err</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( 2 * spirit:decode(id(&apos;MODELPARAM_VALUE.DDRX_nCK_PER_CLK&apos;)) )- 1 ">3</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.app_ecc_multiple_err" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;DDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;LPDDR2&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.ECC&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>ddr3_app_addr</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.DDR3_ADDR_WIDTH&apos;)) )- 1 ">27</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.ddr3_app_addr" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>ddr3_app_cmd</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">2</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.ddr3_app_cmd" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>ddr3_app_en</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.ddr3_app_en" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>ddr3_app_wdf_data</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.DDR3_nCK_PER_CLK&apos;)) * 2 * spirit:decode(id(&apos;MODELPARAM_VALUE.DDR3_DATA_WIDTH&apos;)) )- 1 ">511</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.ddr3_app_wdf_data" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>ddr3_app_wdf_end</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.ddr3_app_wdf_end" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>ddr3_app_wdf_mask</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.DDR3_nCK_PER_CLK&apos;)) * 2 * spirit:decode(id(&apos;MODELPARAM_VALUE.DDR3_DATA_WIDTH&apos;)) / 8 )- 1 ">63</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.ddr3_app_wdf_mask" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>ddr3_app_wdf_wren</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.ddr3_app_wdf_wren" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>ddr3_app_correct_en_i</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.ddr3_app_correct_en_i" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.ECC&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>ddr3_app_rd_data</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.DDR3_nCK_PER_CLK&apos;)) * 2 * spirit:decode(id(&apos;MODELPARAM_VALUE.DDR3_DATA_WIDTH&apos;)) )- 1 ">511</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.ddr3_app_rd_data" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>ddr3_app_rd_data_end</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.ddr3_app_rd_data_end" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>ddr3_app_rd_data_valid</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.ddr3_app_rd_data_valid" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>ddr3_app_rdy</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.ddr3_app_rdy" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>ddr3_app_wdf_rdy</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.ddr3_app_wdf_rdy" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>ddr3_app_sr_req</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.ddr3_app_sr_req" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>ddr3_app_sr_active</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.ddr3_app_sr_active" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>ddr3_app_ref_req</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.ddr3_app_ref_req" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>ddr3_app_ref_ack</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.ddr3_app_ref_ack" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>ddr3_app_zq_req</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.ddr3_app_zq_req" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>ddr3_app_zq_ack</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.ddr3_app_zq_ack" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>ddr3_app_raw_not_ecc</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( 2 * spirit:decode(id(&apos;MODELPARAM_VALUE.DDR3_nCK_PER_CLK&apos;)) )- 1 ">7</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.ddr3_app_raw_not_ecc" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.ECC&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>ddr3_app_ecc_multiple_err</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( 2 * spirit:decode(id(&apos;MODELPARAM_VALUE.DDR3_nCK_PER_CLK&apos;)) )- 1 ">7</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.ddr3_app_ecc_multiple_err" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.ECC&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>ddr2_app_addr</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.DDR2_ADDR_WIDTH&apos;)) )- 1 ">7</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.ddr2_app_addr" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>ddr2_app_cmd</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">2</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.ddr2_app_cmd" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>ddr2_app_en</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.ddr2_app_en" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>ddr2_app_wdf_data</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.DDR2_nCK_PER_CLK&apos;)) * 2 * spirit:decode(id(&apos;MODELPARAM_VALUE.DDR2_DATA_WIDTH&apos;)) )- 1 ">31</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.ddr2_app_wdf_data" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>ddr2_app_wdf_end</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.ddr2_app_wdf_end" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>ddr2_app_wdf_mask</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.DDR2_nCK_PER_CLK&apos;)) * 2 * spirit:decode(id(&apos;MODELPARAM_VALUE.DDR2_DATA_WIDTH&apos;)) / 8 )- 1 ">3</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.ddr2_app_wdf_mask" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>ddr2_app_wdf_wren</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.ddr2_app_wdf_wren" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>ddr2_app_correct_en_i</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.ddr2_app_correct_en_i" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.ECC&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>ddr2_app_rd_data</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.DDR2_nCK_PER_CLK&apos;)) * 2 * spirit:decode(id(&apos;MODELPARAM_VALUE.DDR2_DATA_WIDTH&apos;)) )- 1 ">31</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.ddr2_app_rd_data" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>ddr2_app_rd_data_end</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.ddr2_app_rd_data_end" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>ddr2_app_rd_data_valid</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.ddr2_app_rd_data_valid" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>ddr2_app_rdy</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.ddr2_app_rdy" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>ddr2_app_wdf_rdy</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.ddr2_app_wdf_rdy" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>ddr2_app_sr_req</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.ddr2_app_sr_req" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>ddr2_app_sr_active</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.ddr2_app_sr_active" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>ddr2_app_ref_req</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.ddr2_app_ref_req" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>ddr2_app_ref_ack</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.ddr2_app_ref_ack" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>ddr2_app_zq_req</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.ddr2_app_zq_req" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>ddr2_app_zq_ack</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.ddr2_app_zq_ack" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>ddr2_app_raw_not_ecc</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( 2 * spirit:decode(id(&apos;MODELPARAM_VALUE.DDR2_nCK_PER_CLK&apos;)) )- 1 ">3</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.ddr2_app_raw_not_ecc" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.ECC&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>ddr2_app_ecc_multiple_err</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( 2 * spirit:decode(id(&apos;MODELPARAM_VALUE.DDR2_nCK_PER_CLK&apos;)) )- 1 ">3</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.ddr2_app_ecc_multiple_err" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.ECC&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>lpddr2_app_addr</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.LPDDR2_ADDR_WIDTH&apos;)) )- 1 ">7</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.lpddr2_app_addr" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;LPDDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>lpddr2_app_cmd</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">2</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.lpddr2_app_cmd" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;LPDDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>lpddr2_app_en</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.lpddr2_app_en" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;LPDDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>lpddr2_app_wdf_data</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.LPDDR2_nCK_PER_CLK&apos;)) * 2 * spirit:decode(id(&apos;MODELPARAM_VALUE.LPDDR2_DATA_WIDTH&apos;)) )- 1 ">31</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.lpddr2_app_wdf_data" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;LPDDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>lpddr2_app_wdf_end</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.lpddr2_app_wdf_end" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;LPDDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>lpddr2_app_wdf_mask</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.LPDDR2_nCK_PER_CLK&apos;)) * 2 * spirit:decode(id(&apos;MODELPARAM_VALUE.LPDDR2_DATA_WIDTH&apos;)) / 8 )- 1 ">3</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.lpddr2_app_wdf_mask" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;LPDDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>lpddr2_app_wdf_wren</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.lpddr2_app_wdf_wren" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;LPDDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>lpddr2_app_correct_en_i</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.lpddr2_app_correct_en_i" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;LPDDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.ECC&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>lpddr2_app_rd_data</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.LPDDR2_nCK_PER_CLK&apos;)) * 2 * spirit:decode(id(&apos;MODELPARAM_VALUE.LPDDR2_DATA_WIDTH&apos;)) )- 1 ">31</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.lpddr2_app_rd_data" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;LPDDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>lpddr2_app_rd_data_end</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.lpddr2_app_rd_data_end" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;LPDDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>lpddr2_app_rd_data_valid</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.lpddr2_app_rd_data_valid" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;LPDDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>lpddr2_app_rdy</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.lpddr2_app_rdy" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;LPDDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>lpddr2_app_wdf_rdy</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.lpddr2_app_wdf_rdy" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;LPDDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>lpddr2_app_sr_req</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.lpddr2_app_sr_req" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;LPDDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>lpddr2_app_sr_active</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.lpddr2_app_sr_active" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;LPDDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>lpddr2_app_ref_req</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.lpddr2_app_ref_req" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;LPDDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>lpddr2_app_ref_ack</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.lpddr2_app_ref_ack" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;LPDDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>lpddr2_app_zq_req</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.lpddr2_app_zq_req" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;LPDDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>lpddr2_app_zq_ack</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.lpddr2_app_zq_ack" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;LPDDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>lpddr2_app_raw_not_ecc</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( 2 * spirit:decode(id(&apos;MODELPARAM_VALUE.LPDDR2_nCK_PER_CLK&apos;)) )- 1 ">3</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.lpddr2_app_raw_not_ecc" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;LPDDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.ECC&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>lpddr2_app_ecc_multiple_err</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( 2 * spirit:decode(id(&apos;MODELPARAM_VALUE.LPDDR2_nCK_PER_CLK&apos;)) )- 1 ">3</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.lpddr2_app_ecc_multiple_err" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;LPDDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.ECC&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>ui_clk_sync_rst</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.ui_clk_sync_rst" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) and ( spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;DDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;LPDDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;RLDII&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;RLDIII&quot; ) ">true</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>ddr3_ui_clk_sync_rst</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.ddr3_ui_clk_sync_rst" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and ( spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;DDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;LPDDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;RLDII&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;RLDIII&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>ddr2_ui_clk_sync_rst</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.ddr2_ui_clk_sync_rst" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and ( spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;DDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;LPDDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;RLDII&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;RLDIII&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>lpddr2_ui_clk_sync_rst</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.lpddr2_ui_clk_sync_rst" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;LPDDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and ( spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;DDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;LPDDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;RLDII&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;RLDIII&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>qdriip_ui_clk_sync_rst</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.qdriip_ui_clk_sync_rst" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;QDRIIP&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and ( spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;DDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;LPDDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;RLDII&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;RLDIII&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>rldii_ui_clk_sync_rst</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.rldii_ui_clk_sync_rst" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;RLDII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and ( spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;DDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;LPDDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;RLDII&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;RLDIII&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>rldiii_ui_clk_sync_rst</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.rldiii_ui_clk_sync_rst" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;RLDIII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and ( spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;DDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;LPDDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;RLDII&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;RLDIII&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>ui_clk</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.ui_clk" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) and ( spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;DDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;LPDDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;RLDII&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;RLDIII&quot; ) ">true</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>ui_addn_clk_0</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.ui_addn_clk_0" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.UI_EXTRA_CLOCKS&apos;)) = &quot;TRUE&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.MMCM_CLKOUT0_EN&apos;)) = &quot;TRUE&quot; ) and ( spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;DDR2&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>ui_addn_clk_1</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.ui_addn_clk_1" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.UI_EXTRA_CLOCKS&apos;)) = &quot;TRUE&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.MMCM_CLKOUT1_EN&apos;)) = &quot;TRUE&quot; ) and ( spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;DDR2&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>ui_addn_clk_2</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.ui_addn_clk_2" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.UI_EXTRA_CLOCKS&apos;)) = &quot;TRUE&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.MMCM_CLKOUT2_EN&apos;)) = &quot;TRUE&quot; ) and ( spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;DDR2&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>ui_addn_clk_3</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.ui_addn_clk_3" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.UI_EXTRA_CLOCKS&apos;)) = &quot;TRUE&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.MMCM_CLKOUT3_EN&apos;)) = &quot;TRUE&quot; ) and ( spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;DDR2&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>ui_addn_clk_4</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.ui_addn_clk_4" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.UI_EXTRA_CLOCKS&apos;)) = &quot;TRUE&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.MMCM_CLKOUT4_EN&apos;)) = &quot;TRUE&quot; ) and ( spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;DDR2&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>s_axi_ctrl_awvalid</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.s_axi_ctrl_awvalid" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.USE_AXI&apos;)) = 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.ECC&apos;)) = &quot;ON&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>s_axi_ctrl_awready</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.s_axi_ctrl_awready" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.USE_AXI&apos;)) = 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.ECC&apos;)) = &quot;ON&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>s_axi_ctrl_awaddr</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C_S_AXI_CTRL_ADDR_WIDTH&apos;)) )- 1 ">31</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.s_axi_ctrl_awaddr" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.USE_AXI&apos;)) = 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.ECC&apos;)) = &quot;ON&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>s_axi_ctrl_wvalid</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.s_axi_ctrl_wvalid" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.USE_AXI&apos;)) = 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.ECC&apos;)) = &quot;ON&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>s_axi_ctrl_wready</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.s_axi_ctrl_wready" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.USE_AXI&apos;)) = 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.ECC&apos;)) = &quot;ON&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>s_axi_ctrl_wdata</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C_S_AXI_CTRL_DATA_WIDTH&apos;)) )- 1 ">31</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.s_axi_ctrl_wdata" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.USE_AXI&apos;)) = 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.ECC&apos;)) = &quot;ON&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>s_axi_ctrl_bvalid</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.s_axi_ctrl_bvalid" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.USE_AXI&apos;)) = 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.ECC&apos;)) = &quot;ON&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>s_axi_ctrl_bready</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.s_axi_ctrl_bready" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.USE_AXI&apos;)) = 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.ECC&apos;)) = &quot;ON&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>s_axi_ctrl_bresp</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">1</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.s_axi_ctrl_bresp" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.USE_AXI&apos;)) = 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.ECC&apos;)) = &quot;ON&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>s_axi_ctrl_arvalid</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.s_axi_ctrl_arvalid" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.USE_AXI&apos;)) = 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.ECC&apos;)) = &quot;ON&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>s_axi_ctrl_arready</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.s_axi_ctrl_arready" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.USE_AXI&apos;)) = 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.ECC&apos;)) = &quot;ON&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>s_axi_ctrl_araddr</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C_S_AXI_CTRL_ADDR_WIDTH&apos;)) )- 1 ">31</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.s_axi_ctrl_araddr" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.USE_AXI&apos;)) = 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.ECC&apos;)) = &quot;ON&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>s_axi_ctrl_rvalid</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.s_axi_ctrl_rvalid" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.USE_AXI&apos;)) = 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.ECC&apos;)) = &quot;ON&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>s_axi_ctrl_rready</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.s_axi_ctrl_rready" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.USE_AXI&apos;)) = 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.ECC&apos;)) = &quot;ON&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>s_axi_ctrl_rdata</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C_S_AXI_CTRL_DATA_WIDTH&apos;)) )- 1 ">31</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.s_axi_ctrl_rdata" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.USE_AXI&apos;)) = 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.ECC&apos;)) = &quot;ON&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>s_axi_ctrl_rresp</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">1</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.s_axi_ctrl_rresp" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.USE_AXI&apos;)) = 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.ECC&apos;)) = &quot;ON&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>s_axi_awid</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C_S_AXI_ID_WIDTH&apos;)) )- 1 ">3</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
          <spirit:driver>
            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
          </spirit:driver>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.s_axi_awid" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>s_axi_awaddr</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C_S_AXI_ADDR_WIDTH&apos;)) )- 1 ">31</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.s_axi_awaddr" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>s_axi_awlen</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">7</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.s_axi_awlen" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>s_axi_awsize</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">2</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.s_axi_awsize" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>s_axi_awburst</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">1</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.s_axi_awburst" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>s_axi_awlock</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
          <spirit:driver>
            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
          </spirit:driver>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.s_axi_awlock" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>s_axi_awcache</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">3</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
          <spirit:driver>
            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
          </spirit:driver>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.s_axi_awcache" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>s_axi_awprot</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">2</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
          <spirit:driver>
            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
          </spirit:driver>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.s_axi_awprot" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>s_axi_awqos</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">3</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
          <spirit:driver>
            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
          </spirit:driver>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.s_axi_awqos" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>s_axi_awvalid</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.s_axi_awvalid" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>s_axi_awready</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.s_axi_awready" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>s_axi_wdata</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C_S_AXI_DATA_WIDTH&apos;)) )- 1 ">31</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.s_axi_wdata" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>s_axi_wstrb</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C_S_AXI_DATA_WIDTH&apos;)) / 8 )- 1 ">3</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.s_axi_wstrb" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>s_axi_wlast</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.s_axi_wlast" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>s_axi_wvalid</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.s_axi_wvalid" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>s_axi_wready</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.s_axi_wready" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>s_axi_bready</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.s_axi_bready" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>s_axi_bid</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C_S_AXI_ID_WIDTH&apos;)) )- 1 ">3</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.s_axi_bid" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>s_axi_bresp</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">1</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.s_axi_bresp" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>s_axi_bvalid</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.s_axi_bvalid" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>s_axi_arid</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C_S_AXI_ID_WIDTH&apos;)) )- 1 ">3</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
          <spirit:driver>
            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
          </spirit:driver>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.s_axi_arid" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>s_axi_araddr</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C_S_AXI_ADDR_WIDTH&apos;)) )- 1 ">31</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.s_axi_araddr" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>s_axi_arlen</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">7</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.s_axi_arlen" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>s_axi_arsize</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">2</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.s_axi_arsize" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>s_axi_arburst</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">1</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.s_axi_arburst" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>s_axi_arlock</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
          <spirit:driver>
            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
          </spirit:driver>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.s_axi_arlock" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>s_axi_arcache</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">3</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
          <spirit:driver>
            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
          </spirit:driver>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.s_axi_arcache" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>s_axi_arprot</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">2</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
          <spirit:driver>
            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
          </spirit:driver>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.s_axi_arprot" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>s_axi_arqos</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">3</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
          <spirit:driver>
            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
          </spirit:driver>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.s_axi_arqos" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>s_axi_arvalid</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.s_axi_arvalid" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>s_axi_arready</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.s_axi_arready" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>s_axi_rready</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.s_axi_rready" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>s_axi_rid</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C_S_AXI_ID_WIDTH&apos;)) )- 1 ">3</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.s_axi_rid" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>s_axi_rdata</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C_S_AXI_DATA_WIDTH&apos;)) )- 1 ">31</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.s_axi_rdata" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>s_axi_rresp</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">1</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.s_axi_rresp" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>s_axi_rlast</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.s_axi_rlast" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>s_axi_rvalid</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.s_axi_rvalid" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>interrupt</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.interrupt" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.USE_AXI&apos;)) = 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.ECC&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>mmcm_locked</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.mmcm_locked" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>qdriip_cq_p</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.QDRIIP_NUM_DEVICES&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.qdriip_cq_p" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>qdriip_cq_n</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.QDRIIP_NUM_DEVICES&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.qdriip_cq_n" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>qdriip_qvld</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.QDRIIP_NUM_DEVICES&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.qdriip_qvld" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>qdriip_q</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.QDRIIP_DATA_WIDTH&apos;)) )- 1 ">17</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.qdriip_q" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>qdriip_k_p</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.QDRIIP_NUM_DEVICES&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.qdriip_k_p" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>qdriip_k_n</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.QDRIIP_NUM_DEVICES&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.qdriip_k_n" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>qdriip_d</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.QDRIIP_DATA_WIDTH&apos;)) )- 1 ">17</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.qdriip_d" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>qdriip_sa</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.QDRIIP_ADDR_WIDTH&apos;)) )- 1 ">28</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.qdriip_sa" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>qdriip_w_n</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.qdriip_w_n" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>qdriip_r_n</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.qdriip_r_n" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>qdriip_bw_n</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.QDRIIP_BW_WIDTH&apos;)) )- 1 ">7</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.qdriip_bw_n" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>qdriip_dll_off_n</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.qdriip_dll_off_n" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>qdriip_dbg_pi_counter_read_val</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">4</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.qdriip_dbg_pi_counter_read_val" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;QDRIIP&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.QDRIIP_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>qdriip_dbg_win_inc</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.qdriip_dbg_win_inc" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;QDRIIP&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.QDRIIP_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>qdriip_dbg_win_dec</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.qdriip_dbg_win_dec" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;QDRIIP&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.QDRIIP_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>qdriip_dbg_win_active</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.qdriip_dbg_win_active" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;QDRIIP&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.QDRIIP_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>qdriip_dbg_win_current_byte</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">2</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.qdriip_dbg_win_current_byte" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;QDRIIP&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.QDRIIP_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>qdriip_ila0_data</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">254</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.qdriip_ila0_data" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.QDRIIP_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>qdriip_ila0_trig</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">6</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.qdriip_ila0_trig" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.QDRIIP_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>qdriip_ila1_data</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">269</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.qdriip_ila1_data" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.QDRIIP_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>qdriip_ila1_trig</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">14</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.qdriip_ila1_trig" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.QDRIIP_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>qdriip_vio2_async_in</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">198</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.qdriip_vio2_async_in" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.QDRIIP_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>qdriip_vio2_sync_out</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">34</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.qdriip_vio2_sync_out" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.QDRIIP_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>app_wr_cmd0</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.app_wr_cmd0" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>app_wr_addr0</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.QDRIIP_ADDR_WIDTH&apos;)) )- 1 ">28</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.app_wr_addr0" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>app_wr_data0</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.QDRIIP_BURST_LEN&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.app_wr_data0" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>app_wr_bw_n0</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.QDRIIP_BURST_LEN&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.app_wr_bw_n0" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>app_rd_cmd0</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.app_rd_cmd0" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>app_rd_addr0</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.QDRIIP_ADDR_WIDTH&apos;)) )- 1 ">28</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.app_rd_addr0" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>app_rd_valid0</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.app_rd_valid0" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>app_rd_data0</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.QDRIIP_BURST_LEN&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.app_rd_data0" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>app_wr_cmd1</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.app_wr_cmd1" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>app_wr_addr1</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.QDRIIP_ADDR_WIDTH&apos;)) )- 1 ">28</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.app_wr_addr1" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>app_wr_data1</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" (( spirit:decode(id(&apos;MODELPARAM_VALUE.QDRIIP_DATA_WIDTH&apos;)) * 2 ))- 1 ">35</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.app_wr_data1" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>app_wr_bw_n1</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" (( spirit:decode(id(&apos;MODELPARAM_VALUE.QDRIIP_BW_WIDTH&apos;)) * 2 ))- 1 ">15</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.app_wr_bw_n1" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>app_rd_cmd1</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.app_rd_cmd1" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>app_rd_addr1</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.QDRIIP_ADDR_WIDTH&apos;)) )- 1 ">28</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.app_rd_addr1" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>app_rd_valid1</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.app_rd_valid1" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>app_rd_data1</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" (( spirit:decode(id(&apos;MODELPARAM_VALUE.QDRIIP_DATA_WIDTH&apos;)) * 2 ))- 1 ">35</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.app_rd_data1" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>clk</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.clk" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>rst_clk</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.rst_clk" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>qdriip_app_wr_cmd0</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.qdriip_app_wr_cmd0" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>qdriip_app_wr_addr0</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.QDRIIP_ADDR_WIDTH&apos;)) )- 1 ">28</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.qdriip_app_wr_addr0" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>qdriip_app_wr_data0</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.QDRIIP_BURST_LEN&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.qdriip_app_wr_data0" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>qdriip_app_wr_bw_n0</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.QDRIIP_BURST_LEN&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.qdriip_app_wr_bw_n0" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>qdriip_app_rd_cmd0</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.qdriip_app_rd_cmd0" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>qdriip_app_rd_addr0</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.QDRIIP_ADDR_WIDTH&apos;)) )- 1 ">28</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.qdriip_app_rd_addr0" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>qdriip_app_rd_valid0</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.qdriip_app_rd_valid0" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>qdriip_app_rd_data0</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.QDRIIP_BURST_LEN&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.qdriip_app_rd_data0" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>qdriip_app_wr_cmd1</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.qdriip_app_wr_cmd1" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>qdriip_app_wr_addr1</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.QDRIIP_ADDR_WIDTH&apos;)) )- 1 ">28</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.qdriip_app_wr_addr1" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>qdriip_app_wr_data1</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" (( spirit:decode(id(&apos;MODELPARAM_VALUE.QDRIIP_DATA_WIDTH&apos;)) * 2 ))- 1 ">35</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.qdriip_app_wr_data1" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>qdriip_app_wr_bw_n1</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" (( spirit:decode(id(&apos;MODELPARAM_VALUE.QDRIIP_BW_WIDTH&apos;)) * 2 ))- 1 ">15</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.qdriip_app_wr_bw_n1" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>qdriip_app_rd_cmd1</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.qdriip_app_rd_cmd1" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>qdriip_app_rd_addr1</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.QDRIIP_ADDR_WIDTH&apos;)) )- 1 ">28</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.qdriip_app_rd_addr1" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>qdriip_app_rd_valid1</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.qdriip_app_rd_valid1" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>qdriip_app_rd_data1</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" (( spirit:decode(id(&apos;MODELPARAM_VALUE.QDRIIP_DATA_WIDTH&apos;)) * 2 ))- 1 ">35</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.qdriip_app_rd_data1" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>qdriip_clk</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.qdriip_clk" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>qdriip_rst_clk</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.qdriip_rst_clk" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>rldii_qk_p</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.RLDII_QK_WIDTH&apos;)) )- 1 ">7</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.rldii_qk_p" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;RLDII&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>rldii_qk_n</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.RLDII_QK_WIDTH&apos;)) )- 1 ">7</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.rldii_qk_n" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;RLDII&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>rldii_dq</spirit:name>
        <spirit:wire>
          <spirit:direction>inout</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.RLDII_DATA_WIDTH&apos;)) )- 1 ">17</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.rldii_dq" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;RLDII&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>rldii_dm</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.RLDII_DM_WIDTH&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.rldii_dm" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;RLDII&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>rldii_dk_p</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.RLDII_DK_WIDTH&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.rldii_dk_p" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;RLDII&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>rldii_dk_n</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.RLDII_DK_WIDTH&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.rldii_dk_n" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;RLDII&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>rldii_ck_p</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.RLDII_NUM_DEVICES&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.rldii_ck_p" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;RLDII&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>rldii_ck_n</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.RLDII_NUM_DEVICES&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.rldii_ck_n" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;RLDII&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>rldii_cs_n</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.RLDII_NUM_DEVICES&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.rldii_cs_n" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;RLDII&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>rldii_a</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.RLDII_RLD_ADDR_WIDTH&apos;)) )- 1 ">28</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.rldii_a" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;RLDII&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>rldii_ba</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.RLDII_BANK_WIDTH&apos;)) )- 1 ">1</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.rldii_ba" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;RLDII&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>rldii_qvld</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.RLDII_QVLD_WIDTH&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.rldii_qvld" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;RLDII&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>rldii_we_n</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.rldii_we_n" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;RLDII&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>rldii_ref_n</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.rldii_ref_n" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;RLDII&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>rldii_reset_n</spirit:name>
        <spirit:displayName>reset to memory device</spirit:displayName>
        <spirit:description>reset to memory device</spirit:description>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.rldii_reset_n" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;RLDII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;RLDIII&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>rldii_dbg_pi_tap_cnt</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">4</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.rldii_dbg_pi_tap_cnt" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;RLDII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.RLDII_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>rldii_dbg_win_inc</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.rldii_dbg_win_inc" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;RLDII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.RLDII_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>rldii_dbg_win_dec</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.rldii_dbg_win_dec" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;RLDII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.RLDII_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>rldii_dbg_win_active</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.rldii_dbg_win_active" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;RLDII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.RLDII_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>rldii_dbg_win_current_byte</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">2</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.rldii_dbg_win_current_byte" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;RLDII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.RLDII_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>rldii_ila0_data</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">638</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.rldii_ila0_data" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;RLDII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.RLDII_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>rldii_ila0_trig</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">30</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.rldii_ila0_trig" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;RLDII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.RLDII_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>rldii_vio1_async_in</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">254</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.rldii_vio1_async_in" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;RLDII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.RLDII_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>rldii_vio1_async_out</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">62</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.rldii_vio1_async_out" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;RLDII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.RLDII_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>rldii_vio1_sync_out</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">62</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.rldii_vio1_sync_out" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;RLDII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.RLDII_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>rldiii_qk_p</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.RLDIII_QK_WIDTH&apos;)) )- 1 ">7</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.rldiii_qk_p" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;RLDIII&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>rldiii_qk_n</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.RLDIII_QK_WIDTH&apos;)) )- 1 ">7</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.rldiii_qk_n" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;RLDIII&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>rldiii_dq</spirit:name>
        <spirit:wire>
          <spirit:direction>inout</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.RLDIII_DATA_WIDTH&apos;)) )- 1 ">17</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.rldiii_dq" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;RLDIII&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>rldiii_dm</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.RLDIII_DM_WIDTH&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.rldiii_dm" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;RLDIII&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>rldiii_dk_p</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.RLDIII_DK_WIDTH&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.rldiii_dk_p" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;RLDIII&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>rldiii_dk_n</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.RLDIII_DK_WIDTH&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.rldiii_dk_n" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;RLDIII&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>rldiii_ck_p</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.RLDIII_NUM_DEVICES&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.rldiii_ck_p" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;RLDIII&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>rldiii_ck_n</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.RLDIII_NUM_DEVICES&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.rldiii_ck_n" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;RLDIII&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>rldiii_cs_n</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.RLDIII_NUM_DEVICES&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.rldiii_cs_n" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;RLDIII&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>rldiii_a</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.RLDIII_RLD_ADDR_WIDTH&apos;)) )- 1 ">28</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.rldiii_a" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;RLDIII&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>rldiii_ba</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.RLDIII_BANK_WIDTH&apos;)) )- 1 ">1</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.rldiii_ba" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;RLDIII&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>rldiii_qvld</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.RLDIII_QVLD_WIDTH&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.rldiii_qvld" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;RLDIII&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>rldiii_we_n</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.rldiii_we_n" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;RLDIII&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>rldiii_ref_n</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.rldiii_ref_n" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;RLDIII&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>rldiii_reset_n</spirit:name>
        <spirit:displayName>reset to memory device</spirit:displayName>
        <spirit:description>reset to memory device</spirit:description>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.rldiii_reset_n" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;RLDIII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;RLDIII&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>dbg_pi_tap_cnt</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">4</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.dbg_pi_tap_cnt" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;RLDIII&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;RLDII&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>rldiii_dbg_pi_tap_cnt</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">4</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.rldiii_dbg_pi_tap_cnt" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;RLDIII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.RLDIII_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>rldiii_dbg_win_inc</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.rldiii_dbg_win_inc" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;RLDIII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.RLDIII_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>rldiii_dbg_win_dec</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.rldiii_dbg_win_dec" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;RLDIII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.RLDIII_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>rldiii_dbg_win_active</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.rldiii_dbg_win_active" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;RLDIII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.RLDIII_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>rldiii_dbg_win_current_byte</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">2</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.rldiii_dbg_win_current_byte" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;RLDIII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.RLDIII_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>rldiii_ila0_data</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">638</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.rldiii_ila0_data" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;RLDIII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.RLDIII_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>rldiii_ila0_trig</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">30</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.rldiii_ila0_trig" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;RLDIII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.RLDIII_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>rldiii_vio1_async_in</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">254</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.rldiii_vio1_async_in" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;RLDIII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.RLDIII_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>rldiii_vio1_async_out</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">62</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.rldiii_vio1_async_out" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;RLDIII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.RLDIII_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>rldiii_vio1_sync_out</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">62</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.rldiii_vio1_sync_out" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;RLDIII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.RLDIII_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>dbg_win_inc</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.dbg_win_inc" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;RLDIII&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;RLDII&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>dbg_win_dec</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.dbg_win_dec" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;RLDIII&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;RLDII&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>dbg_win_active</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.dbg_win_active" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;RLDIII&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;RLDII&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>dbg_win_current_byte</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">2</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.dbg_win_current_byte" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;RLDIII&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;RLDII&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>dbg_pi_counter_read_val</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">4</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.dbg_pi_counter_read_val" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;DDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;QDRIIP&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;LPDDR2&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>user_cmd_en</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.user_cmd_en" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;RLDII&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;RLDIII&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>user_cmd</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.RLDX_CMD_PER_CLK&apos;)) * 2 )- 1 ">1</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.user_cmd" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;RLDII&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;RLDIII&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>user_addr</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.RLDX_ADDR_WIDTH&apos;)) * spirit:decode(id(&apos;MODELPARAM_VALUE.RLDX_CMD_PER_CLK&apos;)) )- 1 ">28</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.user_addr" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;RLDII&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;RLDIII&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>user_ba</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.RLDX_BANK_WIDTH&apos;)) * spirit:decode(id(&apos;MODELPARAM_VALUE.RLDX_CMD_PER_CLK&apos;)) )- 1 ">1</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.user_ba" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;RLDII&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;RLDIII&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>user_wr_en</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.user_wr_en" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;RLDII&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;RLDIII&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>user_wr_data</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.RLDX_DATA_WIDTH&apos;)) * 2 * spirit:decode(id(&apos;MODELPARAM_VALUE.RLDX_nCK_PER_CLK&apos;)) )- 1 ">35</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.user_wr_data" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;RLDII&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;RLDIII&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>user_wr_dm</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.RLDX_DM_WIDTH&apos;)) * 2 * spirit:decode(id(&apos;MODELPARAM_VALUE.RLDX_nCK_PER_CLK&apos;)) )- 1 ">1</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.user_wr_dm" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;RLDII&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;RLDIII&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>user_afifo_empty</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.user_afifo_empty" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;RLDII&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;RLDIII&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>user_afifo_full</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.user_afifo_full" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;RLDII&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;RLDIII&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>user_afifo_aempty</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.user_afifo_aempty" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;RLDII&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;RLDIII&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>user_afifo_afull</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.user_afifo_afull" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;RLDII&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;RLDIII&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>user_wdfifo_empty</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.user_wdfifo_empty" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;RLDII&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;RLDIII&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>user_wdfifo_full</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.user_wdfifo_full" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;RLDII&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;RLDIII&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>user_wdfifo_aempty</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.user_wdfifo_aempty" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;RLDII&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;RLDIII&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>user_wdfifo_afull</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.user_wdfifo_afull" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;RLDII&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;RLDIII&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>user_rd_valid</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.RLDX_nCK_PER_CLK&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.user_rd_valid" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;RLDII&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;RLDIII&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>mem_ck_lock_complete</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.mem_ck_lock_complete" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;RLDII&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;RLDIII&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>user_rd_data</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.RLDX_DATA_WIDTH&apos;)) * 2 * spirit:decode(id(&apos;MODELPARAM_VALUE.RLDX_nCK_PER_CLK&apos;)) )- 1 ">35</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.user_rd_data" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;RLDII&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;RLDIII&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>rldii_user_cmd_en</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.rldii_user_cmd_en" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;RLDII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>rldii_user_cmd</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.RLDII_CMD_PER_CLK&apos;)) * 2 )- 1 ">1</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.rldii_user_cmd" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;RLDII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>rldii_user_addr</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.RLDII_ADDR_WIDTH&apos;)) * spirit:decode(id(&apos;MODELPARAM_VALUE.RLDII_CMD_PER_CLK&apos;)) )- 1 ">28</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.rldii_user_addr" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;RLDII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>rldii_user_ba</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.RLDII_BANK_WIDTH&apos;)) * spirit:decode(id(&apos;MODELPARAM_VALUE.RLDII_CMD_PER_CLK&apos;)) )- 1 ">1</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.rldii_user_ba" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;RLDII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>rldii_user_wr_en</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.rldii_user_wr_en" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;RLDII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>rldii_user_wr_data</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.RLDII_DATA_WIDTH&apos;)) * 2 * spirit:decode(id(&apos;MODELPARAM_VALUE.RLDII_nCK_PER_CLK&apos;)) )- 1 ">35</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.rldii_user_wr_data" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;RLDII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>rldii_user_wr_dm</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.RLDII_DM_WIDTH&apos;)) * 2 * spirit:decode(id(&apos;MODELPARAM_VALUE.RLDII_nCK_PER_CLK&apos;)) )- 1 ">1</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.rldii_user_wr_dm" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;RLDII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>rldii_user_afifo_empty</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.rldii_user_afifo_empty" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;RLDII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>rldii_user_afifo_full</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.rldii_user_afifo_full" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;RLDII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>rldii_user_afifo_aempty</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.rldii_user_afifo_aempty" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;RLDII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>rldii_user_afifo_afull</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.rldii_user_afifo_afull" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;RLDII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>rldii_user_wdfifo_empty</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.rldii_user_wdfifo_empty" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;RLDII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>rldii_user_wdfifo_full</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.rldii_user_wdfifo_full" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;RLDII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>rldii_user_wdfifo_aempty</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.rldii_user_wdfifo_aempty" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;RLDII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>rldii_user_wdfifo_afull</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.rldii_user_wdfifo_afull" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;RLDII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>rldii_user_rd_valid</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.RLDII_nCK_PER_CLK&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.rldii_user_rd_valid" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;RLDII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>rldii_mem_ck_lock_complete</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.rldii_mem_ck_lock_complete" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;RLDII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>rldii_user_rd_data</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.RLDII_DATA_WIDTH&apos;)) * 2 * spirit:decode(id(&apos;MODELPARAM_VALUE.RLDII_nCK_PER_CLK&apos;)) )- 1 ">35</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.rldii_user_rd_data" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;RLDII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>rldiii_user_cmd_en</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.rldiii_user_cmd_en" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;RLDIII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>rldiii_user_cmd</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.RLDIII_CMD_PER_CLK&apos;)) * 2 )- 1 ">1</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.rldiii_user_cmd" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;RLDIII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>rldiii_user_addr</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.RLDIII_ADDR_WIDTH&apos;)) * spirit:decode(id(&apos;MODELPARAM_VALUE.RLDIII_CMD_PER_CLK&apos;)) )- 1 ">28</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.rldiii_user_addr" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;RLDIII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>rldiii_user_ba</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.RLDIII_BANK_WIDTH&apos;)) * spirit:decode(id(&apos;MODELPARAM_VALUE.RLDIII_CMD_PER_CLK&apos;)) )- 1 ">1</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.rldiii_user_ba" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;RLDIII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>rldiii_user_wr_en</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.rldiii_user_wr_en" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;RLDIII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>rldiii_user_wr_data</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.RLDIII_DATA_WIDTH&apos;)) * 2 * spirit:decode(id(&apos;MODELPARAM_VALUE.RLDIII_nCK_PER_CLK&apos;)) )- 1 ">35</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.rldiii_user_wr_data" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;RLDIII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>rldiii_user_wr_dm</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.RLDIII_DM_WIDTH&apos;)) * 2 * spirit:decode(id(&apos;MODELPARAM_VALUE.RLDIII_nCK_PER_CLK&apos;)) )- 1 ">1</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.rldiii_user_wr_dm" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;RLDIII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>rldiii_user_afifo_empty</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.rldiii_user_afifo_empty" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;RLDIII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>rldiii_user_afifo_full</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.rldiii_user_afifo_full" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;RLDIII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>rldiii_user_afifo_aempty</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.rldiii_user_afifo_aempty" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;RLDIII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>rldiii_user_afifo_afull</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.rldiii_user_afifo_afull" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;RLDIII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>rldiii_user_wdfifo_empty</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.rldiii_user_wdfifo_empty" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;RLDIII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>rldiii_user_wdfifo_full</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.rldiii_user_wdfifo_full" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;RLDIII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>rldiii_user_wdfifo_aempty</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.rldiii_user_wdfifo_aempty" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;RLDIII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>rldiii_user_wdfifo_afull</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.rldiii_user_wdfifo_afull" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;RLDIII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>rldiii_user_rd_valid</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.RLDIII_nCK_PER_CLK&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.rldiii_user_rd_valid" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;RLDIII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>rldiii_mem_ck_lock_complete</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.rldiii_mem_ck_lock_complete" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;RLDIII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>rldiii_user_rd_data</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.RLDIII_DATA_WIDTH&apos;)) * 2 * spirit:decode(id(&apos;MODELPARAM_VALUE.RLDIII_nCK_PER_CLK&apos;)) )- 1 ">35</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.rldiii_user_rd_data" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;RLDIII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>sys_clk_p</spirit:name>
        <spirit:displayName>Clock P</spirit:displayName>
        <spirit:description>Clock P</spirit:description>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.sys_clk_p" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.SYSCLK_TYPE&apos;)) = &quot;DIFF&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.IS_CLK_SHARED&apos;)) = &quot;FALSE&quot; ">true</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>sys_clk_n</spirit:name>
        <spirit:displayName>Clock P</spirit:displayName>
        <spirit:description>Clock P</spirit:description>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.sys_clk_n" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.SYSCLK_TYPE&apos;)) = &quot;DIFF&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.IS_CLK_SHARED&apos;)) = &quot;FALSE&quot; ">true</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>sys_clk_i</spirit:name>
        <spirit:displayName>Clock P</spirit:displayName>
        <spirit:description>Clock P</spirit:description>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.sys_clk_i" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.SYSCLK_TYPE&apos;)) != &quot;DIFF&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.IS_CLK_SHARED&apos;)) = &quot;FALSE&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>init_calib_complete</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.init_calib_complete" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 ">true</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>aresetn</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.aresetn" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) = 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.MEM_TYPE&apos;)) = &quot;DDR2&quot; ) ">true</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_ddr3_dq</spirit:name>
        <spirit:displayName>Data</spirit:displayName>
        <spirit:description>Data</spirit:description>
        <spirit:wire>
          <spirit:direction>inout</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_DDR3_DQ_WIDTH&apos;)) )- 1 ">7</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_ddr3_dq" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;DDR3&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_ddr3_dqs_p</spirit:name>
        <spirit:displayName>Data Strobe</spirit:displayName>
        <spirit:description>Data Strobe</spirit:description>
        <spirit:wire>
          <spirit:direction>inout</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_DDR3_DQS_WIDTH&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_ddr3_dqs_p" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;DDR3&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_ddr3_dqs_n</spirit:name>
        <spirit:displayName>Data Strobe</spirit:displayName>
        <spirit:description>Data Strobe</spirit:description>
        <spirit:wire>
          <spirit:direction>inout</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_DDR3_DQS_WIDTH&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_ddr3_dqs_n" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;DDR3&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_ddr3_addr</spirit:name>
        <spirit:displayName>Address</spirit:displayName>
        <spirit:description>Address</spirit:description>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_DDR3_ROW_WIDTH&apos;)) )- 1 ">13</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_ddr3_addr" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;DDR3&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_ddr3_ba</spirit:name>
        <spirit:displayName>Bank Address</spirit:displayName>
        <spirit:description>Bank Address</spirit:description>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_DDR3_BANK_WIDTH&apos;)) )- 1 ">2</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_ddr3_ba" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;DDR3&quot; and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;DDR2&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_ddr3_ras_n</spirit:name>
        <spirit:displayName>row address strobe</spirit:displayName>
        <spirit:description>row address strobe</spirit:description>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_ddr3_ras_n" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;DDR3&quot; and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;DDR2&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_ddr3_cas_n</spirit:name>
        <spirit:displayName>column address strobe</spirit:displayName>
        <spirit:description>column address strobe</spirit:description>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_ddr3_cas_n" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;DDR3&quot; and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;DDR2&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_ddr3_we_n</spirit:name>
        <spirit:displayName>write enable</spirit:displayName>
        <spirit:description>write enable</spirit:description>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_ddr3_we_n" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;DDR3&quot; and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;DDR2&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_ddr3_reset_n</spirit:name>
        <spirit:displayName>reset to memory device</spirit:displayName>
        <spirit:description>reset to memory device</spirit:description>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_ddr3_reset_n" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;DDR3&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_ddr3_ck_p</spirit:name>
        <spirit:displayName>clock to memory device</spirit:displayName>
        <spirit:description>clock to memory device</spirit:description>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_DDR3_CK_WIDTH&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_ddr3_ck_p" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;DDR3&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_ddr3_ck_n</spirit:name>
        <spirit:displayName>clock to memory device</spirit:displayName>
        <spirit:description>clock to memory device</spirit:description>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_DDR3_CK_WIDTH&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_ddr3_ck_n" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;DDR3&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_ddr3_cke</spirit:name>
        <spirit:displayName>clock enable</spirit:displayName>
        <spirit:description>clock enable</spirit:description>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_DDR3_CKE_WIDTH&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_ddr3_cke" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;DDR3&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_ddr3_cs_n</spirit:name>
        <spirit:displayName>chip select</spirit:displayName>
        <spirit:description>chip select</spirit:description>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_DDR3_CS_WIDTH&apos;)) * spirit:decode(id(&apos;MODELPARAM_VALUE.C0_DDR3_nCS_PER_RANK&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_ddr3_cs_n" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_DDR3_USE_CS_PORT&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_ddr3_dm</spirit:name>
        <spirit:displayName>data mask</spirit:displayName>
        <spirit:description>data mask</spirit:description>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_DDR3_DM_WIDTH&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_ddr3_dm" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_DDR3_USE_DM_PORT&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_ddr3_odt</spirit:name>
        <spirit:displayName>on die termination</spirit:displayName>
        <spirit:description>on die termination</spirit:description>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_DDR3_ODT_WIDTH&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_ddr3_odt" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;DDR3&quot; and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;DDR2&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_DDR3_USE_ODT_PORT&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_ddr3_parity</spirit:name>
        <spirit:displayName>parity bit</spirit:displayName>
        <spirit:description>parity bit</spirit:description>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_ddr3_parity" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_DDR3_REG_CTRL&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_ddr3_dbg_pi_counter_read_val</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">4</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_ddr3_dbg_pi_counter_read_val" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_DDR3_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_ddr3_dbg_byte_sel</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_DDR3_DQS_CNT_WIDTH&apos;)) + 1 )- 1 ">1</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_ddr3_dbg_byte_sel" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_DDR3_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_ddr3_dbg_sel_pi_incdec</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_ddr3_dbg_sel_pi_incdec" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_DDR3_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_ddr3_dbg_pi_f_inc</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_ddr3_dbg_pi_f_inc" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_DDR3_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_ddr3_dbg_pi_f_dec</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_ddr3_dbg_pi_f_dec" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_DDR3_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_ddr3_dbg_sel_po_incdec</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_ddr3_dbg_sel_po_incdec" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_DDR3_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_ddr3_dbg_po_f_inc</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_ddr3_dbg_po_f_inc" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_DDR3_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_ddr3_dbg_po_f_stg23_sel</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_ddr3_dbg_po_f_stg23_sel" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_DDR3_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_ddr3_dbg_po_f_dec</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_ddr3_dbg_po_f_dec" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_DDR3_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_ddr3_dbg_po_counter_read_val</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">7</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_ddr3_dbg_po_counter_read_val" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_DDR3_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_ddr3_ila_wrpath</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">254</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_ddr3_ila_wrpath" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_DDR3_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_ddr3_ila_rdpath</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">1022</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_ddr3_ila_rdpath" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_DDR3_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_ddr3_ila_basic</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">126</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_ddr3_ila_basic" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_DDR3_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_ddr3_vio_sync_out</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">34</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_ddr3_vio_sync_out" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_DDR3_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_ddr2_dq</spirit:name>
        <spirit:displayName>Data</spirit:displayName>
        <spirit:description>Data</spirit:description>
        <spirit:wire>
          <spirit:direction>inout</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_DDR2_DQ_WIDTH&apos;)) )- 1 ">7</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_ddr2_dq" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;DDR2&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_ddr2_dqs_p</spirit:name>
        <spirit:displayName>Data Strobe</spirit:displayName>
        <spirit:description>Data Strobe</spirit:description>
        <spirit:wire>
          <spirit:direction>inout</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_DDR2_DQS_WIDTH&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_ddr2_dqs_p" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;DDR2&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_ddr2_dqs_n</spirit:name>
        <spirit:displayName>Data Strobe</spirit:displayName>
        <spirit:description>Data Strobe</spirit:description>
        <spirit:wire>
          <spirit:direction>inout</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_DDR2_DQS_WIDTH&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_ddr2_dqs_n" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;DDR2&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_ddr2_addr</spirit:name>
        <spirit:displayName>Address</spirit:displayName>
        <spirit:description>Address</spirit:description>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_DDR2_ROW_WIDTH&apos;)) )- 1 ">13</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_ddr2_addr" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;DDR2&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_ddr2_ba</spirit:name>
        <spirit:displayName>Bank Address</spirit:displayName>
        <spirit:description>Bank Address</spirit:description>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_DDR2_BANK_WIDTH&apos;)) )- 1 ">2</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_ddr2_ba" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;DDR2&quot; and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;DDR2&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_ddr2_ras_n</spirit:name>
        <spirit:displayName>row address strobe</spirit:displayName>
        <spirit:description>row address strobe</spirit:description>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_ddr2_ras_n" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;DDR2&quot; and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;DDR2&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_ddr2_cas_n</spirit:name>
        <spirit:displayName>column address strobe</spirit:displayName>
        <spirit:description>column address strobe</spirit:description>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_ddr2_cas_n" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;DDR2&quot; and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;DDR2&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_ddr2_we_n</spirit:name>
        <spirit:displayName>write enable</spirit:displayName>
        <spirit:description>write enable</spirit:description>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_ddr2_we_n" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;DDR2&quot; and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;DDR2&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_ddr2_reset_n</spirit:name>
        <spirit:displayName>reset to memory device</spirit:displayName>
        <spirit:description>reset to memory device</spirit:description>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_ddr2_reset_n" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;DDR3&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_ddr2_ck_p</spirit:name>
        <spirit:displayName>clock to memory device</spirit:displayName>
        <spirit:description>clock to memory device</spirit:description>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_DDR2_CK_WIDTH&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_ddr2_ck_p" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;DDR2&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_ddr2_ck_n</spirit:name>
        <spirit:displayName>clock to memory device</spirit:displayName>
        <spirit:description>clock to memory device</spirit:description>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_DDR2_CK_WIDTH&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_ddr2_ck_n" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;DDR2&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_ddr2_cke</spirit:name>
        <spirit:displayName>clock enable</spirit:displayName>
        <spirit:description>clock enable</spirit:description>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_DDR2_CKE_WIDTH&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_ddr2_cke" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;DDR2&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_ddr2_cs_n</spirit:name>
        <spirit:displayName>chip select</spirit:displayName>
        <spirit:description>chip select</spirit:description>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_DDR2_CS_WIDTH&apos;)) * spirit:decode(id(&apos;MODELPARAM_VALUE.C0_DDR2_nCS_PER_RANK&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_ddr2_cs_n" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_DDR2_USE_CS_PORT&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_ddr2_dm</spirit:name>
        <spirit:displayName>data mask</spirit:displayName>
        <spirit:description>data mask</spirit:description>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_DDR2_DM_WIDTH&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_ddr2_dm" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_DDR2_USE_DM_PORT&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_ddr2_odt</spirit:name>
        <spirit:displayName>on die termination</spirit:displayName>
        <spirit:description>on die termination</spirit:description>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_DDR2_ODT_WIDTH&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_ddr2_odt" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;DDR2&quot; and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;DDR2&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_DDR2_USE_ODT_PORT&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_ddr2_parity</spirit:name>
        <spirit:displayName>parity bit</spirit:displayName>
        <spirit:description>parity bit</spirit:description>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_ddr2_parity" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_DDR2_REG_CTRL&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_ddr2_dbg_pi_counter_read_val</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">4</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_ddr2_dbg_pi_counter_read_val" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_DDR2_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_ddr2_dbg_byte_sel</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_DDR2_DQS_CNT_WIDTH&apos;)) + 1 )- 1 ">1</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_ddr2_dbg_byte_sel" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_DDR2_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_ddr2_dbg_sel_pi_incdec</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_ddr2_dbg_sel_pi_incdec" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_DDR2_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_ddr2_dbg_pi_f_inc</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_ddr2_dbg_pi_f_inc" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_DDR2_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_ddr2_dbg_pi_f_dec</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_ddr2_dbg_pi_f_dec" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_DDR2_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_ddr2_dbg_sel_po_incdec</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_ddr2_dbg_sel_po_incdec" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_DDR2_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_ddr2_dbg_po_f_inc</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_ddr2_dbg_po_f_inc" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_DDR2_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_ddr2_dbg_po_f_stg23_sel</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_ddr2_dbg_po_f_stg23_sel" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_DDR2_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_ddr2_dbg_po_f_dec</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_ddr2_dbg_po_f_dec" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_DDR2_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_ddr2_dbg_po_counter_read_val</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">7</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_ddr2_dbg_po_counter_read_val" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_DDR2_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_ddr2_ila_wrpath</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">254</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_ddr2_ila_wrpath" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_DDR2_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_ddr2_ila_rdpath</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">1022</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_ddr2_ila_rdpath" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_DDR2_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_ddr2_ila_basic</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">126</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_ddr2_ila_basic" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_DDR2_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_ddr2_vio_sync_out</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">34</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_ddr2_vio_sync_out" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_DDR2_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_lpddr2_dq</spirit:name>
        <spirit:displayName>Data</spirit:displayName>
        <spirit:description>Data</spirit:description>
        <spirit:wire>
          <spirit:direction>inout</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_LPDDR2_DQ_WIDTH&apos;)) )- 1 ">7</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_lpddr2_dq" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_lpddr2_dqs_p</spirit:name>
        <spirit:displayName>Data Strobe</spirit:displayName>
        <spirit:description>Data Strobe</spirit:description>
        <spirit:wire>
          <spirit:direction>inout</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_LPDDR2_DQS_WIDTH&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_lpddr2_dqs_p" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_lpddr2_dqs_n</spirit:name>
        <spirit:displayName>Data Strobe</spirit:displayName>
        <spirit:description>Data Strobe</spirit:description>
        <spirit:wire>
          <spirit:direction>inout</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_LPDDR2_DQS_WIDTH&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_lpddr2_dqs_n" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_lpddr2_ca</spirit:name>
        <spirit:displayName>Address</spirit:displayName>
        <spirit:description>Address</spirit:description>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">9</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_lpddr2_ca" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_lpddr2_ck_p</spirit:name>
        <spirit:displayName>clock to memory device</spirit:displayName>
        <spirit:description>clock to memory device</spirit:description>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_LPDDR2_CK_WIDTH&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_lpddr2_ck_p" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_lpddr2_ck_n</spirit:name>
        <spirit:displayName>clock to memory device</spirit:displayName>
        <spirit:description>clock to memory device</spirit:description>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_LPDDR2_CK_WIDTH&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_lpddr2_ck_n" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_lpddr2_cke</spirit:name>
        <spirit:displayName>clock enable</spirit:displayName>
        <spirit:description>clock enable</spirit:description>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_LPDDR2_CKE_WIDTH&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_lpddr2_cke" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_lpddr2_cs_n</spirit:name>
        <spirit:displayName>chip select</spirit:displayName>
        <spirit:description>chip select</spirit:description>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_LPDDR2_CS_WIDTH&apos;)) * spirit:decode(id(&apos;MODELPARAM_VALUE.C0_LPDDR2_nCS_PER_RANK&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_lpddr2_cs_n" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_LPDDR2_USE_CS_PORT&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_lpddr2_dm</spirit:name>
        <spirit:displayName>data mask</spirit:displayName>
        <spirit:description>data mask</spirit:description>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_LPDDR2_DM_WIDTH&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_lpddr2_dm" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_LPDDR2_USE_DM_PORT&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_lpddr2_parity</spirit:name>
        <spirit:displayName>parity bit</spirit:displayName>
        <spirit:description>parity bit</spirit:description>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_lpddr2_parity" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_LPDDR2_REG_CTRL&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_lpddr2_dbg_pi_counter_read_val</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">4</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_lpddr2_dbg_pi_counter_read_val" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_LPDDR2_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_lpddr2_dbg_byte_sel</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_LPDDR2_DQS_CNT_WIDTH&apos;)) + 1 )- 1 ">1</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_lpddr2_dbg_byte_sel" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_LPDDR2_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_lpddr2_dbg_sel_pi_incdec</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_lpddr2_dbg_sel_pi_incdec" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_LPDDR2_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_lpddr2_dbg_pi_f_inc</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_lpddr2_dbg_pi_f_inc" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_LPDDR2_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_lpddr2_dbg_pi_f_dec</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_lpddr2_dbg_pi_f_dec" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_LPDDR2_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_lpddr2_dbg_sel_po_incdec</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_lpddr2_dbg_sel_po_incdec" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_LPDDR2_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_lpddr2_dbg_po_f_inc</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_lpddr2_dbg_po_f_inc" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_LPDDR2_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_lpddr2_dbg_po_f_stg23_sel</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_lpddr2_dbg_po_f_stg23_sel" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_LPDDR2_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_lpddr2_dbg_po_f_dec</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_lpddr2_dbg_po_f_dec" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_LPDDR2_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_lpddr2_dbg_po_counter_read_val</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">7</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_lpddr2_dbg_po_counter_read_val" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_LPDDR2_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_lpddr2_ila_wrpath</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">254</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_lpddr2_ila_wrpath" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_LPDDR2_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_lpddr2_ila_rdpath</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">1022</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_lpddr2_ila_rdpath" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_LPDDR2_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_lpddr2_ila_basic</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">126</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_lpddr2_ila_basic" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_LPDDR2_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_lpddr2_vio_sync_out</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">34</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_lpddr2_vio_sync_out" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_LPDDR2_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_dbg_byte_sel</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_DQS_CNT_WIDTH&apos;)) + 1 )- 1 ">1</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_dbg_byte_sel" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;DDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_dbg_sel_pi_incdec</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_dbg_sel_pi_incdec" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;DDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_dbg_pi_f_inc</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_dbg_pi_f_inc" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;DDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_dbg_pi_f_dec</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_dbg_pi_f_dec" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;DDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_dbg_sel_po_incdec</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_dbg_sel_po_incdec" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;DDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_dbg_po_f_inc</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_dbg_po_f_inc" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;DDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_dbg_po_f_stg23_sel</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_dbg_po_f_stg23_sel" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;DDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_dbg_po_f_dec</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_dbg_po_f_dec" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;DDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_dbg_po_counter_read_val</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">7</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_dbg_po_counter_read_val" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;DDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_app_addr</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_DDRX_ADDR_WIDTH&apos;)) )- 1 ">7</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_app_addr" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;DDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_app_cmd</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">2</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_app_cmd" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;DDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_app_en</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_app_en" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;DDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_app_wdf_data</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_DDRX_nCK_PER_CLK&apos;)) * 2 * spirit:decode(id(&apos;MODELPARAM_VALUE.C0_DDRX_DATA_WIDTH&apos;)) )- 1 ">31</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_app_wdf_data" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;DDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_app_wdf_end</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_app_wdf_end" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;DDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_app_wdf_mask</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_DDRX_nCK_PER_CLK&apos;)) * 2 * spirit:decode(id(&apos;MODELPARAM_VALUE.C0_DDRX_DATA_WIDTH&apos;)) / 8 )- 1 ">3</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_app_wdf_mask" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;DDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_app_wdf_wren</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_app_wdf_wren" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;DDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_app_correct_en_i</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_app_correct_en_i" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;DDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_ECC&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_app_rd_data</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_DDRX_nCK_PER_CLK&apos;)) * 2 * spirit:decode(id(&apos;MODELPARAM_VALUE.C0_DDRX_DATA_WIDTH&apos;)) )- 1 ">31</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_app_rd_data" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;DDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_app_rd_data_end</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_app_rd_data_end" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;DDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_app_rd_data_valid</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_app_rd_data_valid" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;DDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_app_rdy</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_app_rdy" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;DDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_app_wdf_rdy</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_app_wdf_rdy" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;DDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_app_sr_req</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_app_sr_req" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;DDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_app_sr_active</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_app_sr_active" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;DDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_app_ref_req</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_app_ref_req" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;DDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_app_ref_ack</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_app_ref_ack" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;DDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_app_zq_req</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_app_zq_req" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;DDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_app_zq_ack</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_app_zq_ack" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;DDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_app_raw_not_ecc</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( 2 * spirit:decode(id(&apos;MODELPARAM_VALUE.C0_DDRX_nCK_PER_CLK&apos;)) )- 1 ">3</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_app_raw_not_ecc" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;DDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_ECC&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_app_ecc_multiple_err</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( 2 * spirit:decode(id(&apos;MODELPARAM_VALUE.C0_DDRX_nCK_PER_CLK&apos;)) )- 1 ">3</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_app_ecc_multiple_err" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;DDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_ECC&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_ddr3_app_addr</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_DDR3_ADDR_WIDTH&apos;)) )- 1 ">7</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_ddr3_app_addr" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_ddr3_app_cmd</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">2</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_ddr3_app_cmd" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_ddr3_app_en</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_ddr3_app_en" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_ddr3_app_wdf_data</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_DDR3_nCK_PER_CLK&apos;)) * 2 * spirit:decode(id(&apos;MODELPARAM_VALUE.C0_DDR3_DATA_WIDTH&apos;)) )- 1 ">31</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_ddr3_app_wdf_data" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_ddr3_app_wdf_end</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_ddr3_app_wdf_end" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_ddr3_app_wdf_mask</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_DDR3_nCK_PER_CLK&apos;)) * 2 * spirit:decode(id(&apos;MODELPARAM_VALUE.C0_DDR3_DATA_WIDTH&apos;)) / 8 )- 1 ">3</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_ddr3_app_wdf_mask" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_ddr3_app_wdf_wren</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_ddr3_app_wdf_wren" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_ddr3_app_correct_en_i</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_ddr3_app_correct_en_i" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_ECC&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_ddr3_app_rd_data</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_DDR3_nCK_PER_CLK&apos;)) * 2 * spirit:decode(id(&apos;MODELPARAM_VALUE.C0_DDR3_DATA_WIDTH&apos;)) )- 1 ">31</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_ddr3_app_rd_data" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_ddr3_app_rd_data_end</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_ddr3_app_rd_data_end" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_ddr3_app_rd_data_valid</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_ddr3_app_rd_data_valid" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_ddr3_app_rdy</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_ddr3_app_rdy" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_ddr3_app_wdf_rdy</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_ddr3_app_wdf_rdy" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_ddr3_app_sr_req</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_ddr3_app_sr_req" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_ddr3_app_sr_active</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_ddr3_app_sr_active" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_ddr3_app_ref_req</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_ddr3_app_ref_req" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_ddr3_app_ref_ack</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_ddr3_app_ref_ack" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_ddr3_app_zq_req</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_ddr3_app_zq_req" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_ddr3_app_zq_ack</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_ddr3_app_zq_ack" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_ddr3_app_raw_not_ecc</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( 2 * spirit:decode(id(&apos;MODELPARAM_VALUE.C0_DDR3_nCK_PER_CLK&apos;)) )- 1 ">3</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_ddr3_app_raw_not_ecc" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_ECC&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_ddr3_app_ecc_multiple_err</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( 2 * spirit:decode(id(&apos;MODELPARAM_VALUE.C0_DDR3_nCK_PER_CLK&apos;)) )- 1 ">3</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_ddr3_app_ecc_multiple_err" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_ECC&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_ddr2_app_addr</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_DDR2_ADDR_WIDTH&apos;)) )- 1 ">7</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_ddr2_app_addr" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_ddr2_app_cmd</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">2</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_ddr2_app_cmd" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_ddr2_app_en</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_ddr2_app_en" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_ddr2_app_wdf_data</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_DDR2_nCK_PER_CLK&apos;)) * 2 * spirit:decode(id(&apos;MODELPARAM_VALUE.C0_DDR2_DATA_WIDTH&apos;)) )- 1 ">31</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_ddr2_app_wdf_data" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_ddr2_app_wdf_end</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_ddr2_app_wdf_end" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_ddr2_app_wdf_mask</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_DDR2_nCK_PER_CLK&apos;)) * 2 * spirit:decode(id(&apos;MODELPARAM_VALUE.C0_DDR2_DATA_WIDTH&apos;)) / 8 )- 1 ">3</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_ddr2_app_wdf_mask" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_ddr2_app_wdf_wren</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_ddr2_app_wdf_wren" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_ddr2_app_correct_en_i</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_ddr2_app_correct_en_i" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_ECC&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_ddr2_app_rd_data</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_DDR2_nCK_PER_CLK&apos;)) * 2 * spirit:decode(id(&apos;MODELPARAM_VALUE.C0_DDR2_DATA_WIDTH&apos;)) )- 1 ">31</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_ddr2_app_rd_data" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_ddr2_app_rd_data_end</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_ddr2_app_rd_data_end" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_ddr2_app_rd_data_valid</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_ddr2_app_rd_data_valid" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_ddr2_app_rdy</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_ddr2_app_rdy" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_ddr2_app_wdf_rdy</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_ddr2_app_wdf_rdy" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_ddr2_app_sr_req</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_ddr2_app_sr_req" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_ddr2_app_sr_active</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_ddr2_app_sr_active" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_ddr2_app_ref_req</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_ddr2_app_ref_req" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_ddr2_app_ref_ack</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_ddr2_app_ref_ack" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_ddr2_app_zq_req</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_ddr2_app_zq_req" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_ddr2_app_zq_ack</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_ddr2_app_zq_ack" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_ddr2_app_raw_not_ecc</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( 2 * spirit:decode(id(&apos;MODELPARAM_VALUE.C0_DDR2_nCK_PER_CLK&apos;)) )- 1 ">3</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_ddr2_app_raw_not_ecc" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_ECC&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_ddr2_app_ecc_multiple_err</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( 2 * spirit:decode(id(&apos;MODELPARAM_VALUE.C0_DDR2_nCK_PER_CLK&apos;)) )- 1 ">3</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_ddr2_app_ecc_multiple_err" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_ECC&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_lpddr2_app_addr</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_LPDDR2_ADDR_WIDTH&apos;)) )- 1 ">7</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_lpddr2_app_addr" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_lpddr2_app_cmd</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">2</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_lpddr2_app_cmd" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_lpddr2_app_en</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_lpddr2_app_en" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_lpddr2_app_wdf_data</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_LPDDR2_nCK_PER_CLK&apos;)) * 2 * spirit:decode(id(&apos;MODELPARAM_VALUE.C0_LPDDR2_DATA_WIDTH&apos;)) )- 1 ">31</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_lpddr2_app_wdf_data" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_lpddr2_app_wdf_end</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_lpddr2_app_wdf_end" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_lpddr2_app_wdf_mask</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_LPDDR2_nCK_PER_CLK&apos;)) * 2 * spirit:decode(id(&apos;MODELPARAM_VALUE.C0_LPDDR2_DATA_WIDTH&apos;)) / 8 )- 1 ">3</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_lpddr2_app_wdf_mask" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_lpddr2_app_wdf_wren</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_lpddr2_app_wdf_wren" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_lpddr2_app_correct_en_i</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_lpddr2_app_correct_en_i" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_ECC&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_lpddr2_app_rd_data</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_LPDDR2_nCK_PER_CLK&apos;)) * 2 * spirit:decode(id(&apos;MODELPARAM_VALUE.C0_LPDDR2_DATA_WIDTH&apos;)) )- 1 ">31</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_lpddr2_app_rd_data" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_lpddr2_app_rd_data_end</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_lpddr2_app_rd_data_end" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_lpddr2_app_rd_data_valid</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_lpddr2_app_rd_data_valid" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_lpddr2_app_rdy</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_lpddr2_app_rdy" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_lpddr2_app_wdf_rdy</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_lpddr2_app_wdf_rdy" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_lpddr2_app_sr_req</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_lpddr2_app_sr_req" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_lpddr2_app_sr_active</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_lpddr2_app_sr_active" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_lpddr2_app_ref_req</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_lpddr2_app_ref_req" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_lpddr2_app_ref_ack</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_lpddr2_app_ref_ack" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_lpddr2_app_zq_req</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_lpddr2_app_zq_req" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_lpddr2_app_zq_ack</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_lpddr2_app_zq_ack" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_lpddr2_app_raw_not_ecc</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( 2 * spirit:decode(id(&apos;MODELPARAM_VALUE.C0_LPDDR2_nCK_PER_CLK&apos;)) )- 1 ">3</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_lpddr2_app_raw_not_ecc" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_ECC&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_lpddr2_app_ecc_multiple_err</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( 2 * spirit:decode(id(&apos;MODELPARAM_VALUE.C0_LPDDR2_nCK_PER_CLK&apos;)) )- 1 ">3</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_lpddr2_app_ecc_multiple_err" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_ECC&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_ui_clk_sync_rst</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_ui_clk_sync_rst" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;DDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;RLDII&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;RLDIII&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_ddr3_ui_clk_sync_rst</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_ddr3_ui_clk_sync_rst" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;DDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;RLDII&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;RLDIII&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_ddr2_ui_clk_sync_rst</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_ddr2_ui_clk_sync_rst" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;DDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;RLDII&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;RLDIII&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_lpddr2_ui_clk_sync_rst</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_lpddr2_ui_clk_sync_rst" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;DDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;RLDII&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;RLDIII&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_qdriip_ui_clk_sync_rst</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_qdriip_ui_clk_sync_rst" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;DDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;RLDII&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;RLDIII&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_rldii_ui_clk_sync_rst</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_rldii_ui_clk_sync_rst" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;RLDII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;DDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;RLDII&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;RLDIII&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_rldiii_ui_clk_sync_rst</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_rldiii_ui_clk_sync_rst" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;RLDIII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;DDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;RLDII&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;RLDIII&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_ui_clk</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_ui_clk" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;DDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;RLDII&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;RLDIII&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_ui_addn_clk_0</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_ui_addn_clk_0" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_UI_EXTRA_CLOCKS&apos;)) = &quot;TRUE&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MMCM_CLKOUT0_EN&apos;)) = &quot;TRUE&quot; ) and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;DDR2&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_ui_addn_clk_1</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_ui_addn_clk_1" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_UI_EXTRA_CLOCKS&apos;)) = &quot;TRUE&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MMCM_CLKOUT1_EN&apos;)) = &quot;TRUE&quot; ) and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;DDR2&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_ui_addn_clk_2</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_ui_addn_clk_2" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_UI_EXTRA_CLOCKS&apos;)) = &quot;TRUE&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MMCM_CLKOUT2_EN&apos;)) = &quot;TRUE&quot; ) and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;DDR2&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_ui_addn_clk_3</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_ui_addn_clk_3" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_UI_EXTRA_CLOCKS&apos;)) = &quot;TRUE&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MMCM_CLKOUT3_EN&apos;)) = &quot;TRUE&quot; ) and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;DDR2&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_ui_addn_clk_4</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_ui_addn_clk_4" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_UI_EXTRA_CLOCKS&apos;)) = &quot;TRUE&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MMCM_CLKOUT4_EN&apos;)) = &quot;TRUE&quot; ) and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;DDR2&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_s_axi_ctrl_awvalid</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_s_axi_ctrl_awvalid" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_USE_AXI&apos;)) = 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_ECC&apos;)) = &quot;ON&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_s_axi_ctrl_awready</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_s_axi_ctrl_awready" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_USE_AXI&apos;)) = 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_ECC&apos;)) = &quot;ON&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_s_axi_ctrl_awaddr</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_C_S_AXI_CTRL_ADDR_WIDTH&apos;)) )- 1 ">31</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_s_axi_ctrl_awaddr" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_USE_AXI&apos;)) = 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_ECC&apos;)) = &quot;ON&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_s_axi_ctrl_wvalid</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_s_axi_ctrl_wvalid" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_USE_AXI&apos;)) = 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_ECC&apos;)) = &quot;ON&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_s_axi_ctrl_wready</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_s_axi_ctrl_wready" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_USE_AXI&apos;)) = 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_ECC&apos;)) = &quot;ON&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_s_axi_ctrl_wdata</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_C_S_AXI_CTRL_DATA_WIDTH&apos;)) )- 1 ">31</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_s_axi_ctrl_wdata" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_USE_AXI&apos;)) = 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_ECC&apos;)) = &quot;ON&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_s_axi_ctrl_bvalid</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_s_axi_ctrl_bvalid" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_USE_AXI&apos;)) = 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_ECC&apos;)) = &quot;ON&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_s_axi_ctrl_bready</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_s_axi_ctrl_bready" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_USE_AXI&apos;)) = 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_ECC&apos;)) = &quot;ON&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_s_axi_ctrl_bresp</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">1</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_s_axi_ctrl_bresp" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_USE_AXI&apos;)) = 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_ECC&apos;)) = &quot;ON&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_s_axi_ctrl_arvalid</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_s_axi_ctrl_arvalid" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_USE_AXI&apos;)) = 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_ECC&apos;)) = &quot;ON&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_s_axi_ctrl_arready</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_s_axi_ctrl_arready" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_USE_AXI&apos;)) = 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_ECC&apos;)) = &quot;ON&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_s_axi_ctrl_araddr</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_C_S_AXI_CTRL_ADDR_WIDTH&apos;)) )- 1 ">31</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_s_axi_ctrl_araddr" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_USE_AXI&apos;)) = 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_ECC&apos;)) = &quot;ON&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_s_axi_ctrl_rvalid</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_s_axi_ctrl_rvalid" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_USE_AXI&apos;)) = 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_ECC&apos;)) = &quot;ON&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_s_axi_ctrl_rready</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_s_axi_ctrl_rready" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_USE_AXI&apos;)) = 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_ECC&apos;)) = &quot;ON&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_s_axi_ctrl_rdata</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_C_S_AXI_CTRL_DATA_WIDTH&apos;)) )- 1 ">31</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_s_axi_ctrl_rdata" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_USE_AXI&apos;)) = 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_ECC&apos;)) = &quot;ON&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_s_axi_ctrl_rresp</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">1</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_s_axi_ctrl_rresp" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_USE_AXI&apos;)) = 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_ECC&apos;)) = &quot;ON&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_s_axi_awid</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_C_S_AXI_ID_WIDTH&apos;)) )- 1 ">3</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
          <spirit:driver>
            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
          </spirit:driver>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_s_axi_awid" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_s_axi_awaddr</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_C_S_AXI_ADDR_WIDTH&apos;)) )- 1 ">31</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_s_axi_awaddr" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_s_axi_awlen</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">7</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_s_axi_awlen" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_s_axi_awsize</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">2</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_s_axi_awsize" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_s_axi_awburst</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">1</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_s_axi_awburst" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_s_axi_awlock</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
          <spirit:driver>
            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
          </spirit:driver>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_s_axi_awlock" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_s_axi_awcache</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">3</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
          <spirit:driver>
            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
          </spirit:driver>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_s_axi_awcache" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_s_axi_awprot</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">2</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
          <spirit:driver>
            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
          </spirit:driver>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_s_axi_awprot" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_s_axi_awqos</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">3</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
          <spirit:driver>
            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
          </spirit:driver>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_s_axi_awqos" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_s_axi_awvalid</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_s_axi_awvalid" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_s_axi_awready</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_s_axi_awready" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_s_axi_wdata</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_C_S_AXI_DATA_WIDTH&apos;)) )- 1 ">31</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_s_axi_wdata" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_s_axi_wstrb</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_C_S_AXI_DATA_WIDTH&apos;)) / 8 )- 1 ">3</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_s_axi_wstrb" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_s_axi_wlast</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_s_axi_wlast" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_s_axi_wvalid</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_s_axi_wvalid" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_s_axi_wready</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_s_axi_wready" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_s_axi_bready</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_s_axi_bready" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_s_axi_bid</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_C_S_AXI_ID_WIDTH&apos;)) )- 1 ">3</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_s_axi_bid" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_s_axi_bresp</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">1</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_s_axi_bresp" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_s_axi_bvalid</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_s_axi_bvalid" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_s_axi_arid</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_C_S_AXI_ID_WIDTH&apos;)) )- 1 ">3</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
          <spirit:driver>
            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
          </spirit:driver>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_s_axi_arid" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_s_axi_araddr</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_C_S_AXI_ADDR_WIDTH&apos;)) )- 1 ">31</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_s_axi_araddr" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_s_axi_arlen</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">7</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_s_axi_arlen" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_s_axi_arsize</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">2</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_s_axi_arsize" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_s_axi_arburst</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">1</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_s_axi_arburst" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_s_axi_arlock</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
          <spirit:driver>
            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
          </spirit:driver>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_s_axi_arlock" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_s_axi_arcache</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">3</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
          <spirit:driver>
            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
          </spirit:driver>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_s_axi_arcache" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_s_axi_arprot</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">2</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
          <spirit:driver>
            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
          </spirit:driver>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_s_axi_arprot" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_s_axi_arqos</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">3</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
          <spirit:driver>
            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
          </spirit:driver>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_s_axi_arqos" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_s_axi_arvalid</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_s_axi_arvalid" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_s_axi_arready</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_s_axi_arready" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_s_axi_rready</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_s_axi_rready" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_s_axi_rid</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_C_S_AXI_ID_WIDTH&apos;)) )- 1 ">3</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_s_axi_rid" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_s_axi_rdata</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_C_S_AXI_DATA_WIDTH&apos;)) )- 1 ">31</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_s_axi_rdata" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_s_axi_rresp</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">1</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_s_axi_rresp" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_s_axi_rlast</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_s_axi_rlast" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_s_axi_rvalid</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_s_axi_rvalid" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_interrupt</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_interrupt" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_USE_AXI&apos;)) = 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_ECC&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_mmcm_locked</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_mmcm_locked" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_qdriip_cq_p</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_QDRIIP_NUM_DEVICES&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_qdriip_cq_p" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_qdriip_cq_n</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_QDRIIP_NUM_DEVICES&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_qdriip_cq_n" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_qdriip_qvld</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_QDRIIP_NUM_DEVICES&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_qdriip_qvld" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_qdriip_q</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_QDRIIP_DATA_WIDTH&apos;)) )- 1 ">17</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_qdriip_q" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_qdriip_k_p</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_QDRIIP_NUM_DEVICES&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_qdriip_k_p" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_qdriip_k_n</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_QDRIIP_NUM_DEVICES&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_qdriip_k_n" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_qdriip_d</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_QDRIIP_DATA_WIDTH&apos;)) )- 1 ">17</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_qdriip_d" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_qdriip_sa</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_QDRIIP_ADDR_WIDTH&apos;)) )- 1 ">28</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_qdriip_sa" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_qdriip_w_n</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_qdriip_w_n" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_qdriip_r_n</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_qdriip_r_n" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_qdriip_bw_n</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_QDRIIP_BW_WIDTH&apos;)) )- 1 ">7</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_qdriip_bw_n" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_qdriip_dll_off_n</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_qdriip_dll_off_n" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_qdriip_dbg_pi_counter_read_val</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">4</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_qdriip_dbg_pi_counter_read_val" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_QDRIIP_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_qdriip_dbg_win_inc</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_qdriip_dbg_win_inc" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_QDRIIP_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_qdriip_dbg_win_dec</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_qdriip_dbg_win_dec" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_QDRIIP_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_qdriip_dbg_win_active</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_qdriip_dbg_win_active" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_QDRIIP_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_qdriip_dbg_win_current_byte</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">2</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_qdriip_dbg_win_current_byte" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_QDRIIP_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_qdriip_ila0_data</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">254</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_qdriip_ila0_data" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_QDRIIP_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_qdriip_ila0_trig</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">6</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_qdriip_ila0_trig" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_QDRIIP_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_qdriip_ila1_data</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">269</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_qdriip_ila1_data" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_QDRIIP_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_qdriip_ila1_trig</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">14</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_qdriip_ila1_trig" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_QDRIIP_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_qdriip_vio2_async_in</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">198</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_qdriip_vio2_async_in" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_QDRIIP_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_qdriip_vio2_sync_out</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">34</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_qdriip_vio2_sync_out" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_QDRIIP_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_app_wr_cmd0</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_app_wr_cmd0" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_app_wr_addr0</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_QDRIIP_ADDR_WIDTH&apos;)) )- 1 ">28</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_app_wr_addr0" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_app_wr_data0</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_QDRIIP_BURST_LEN&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_app_wr_data0" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_app_wr_bw_n0</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_QDRIIP_BURST_LEN&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_app_wr_bw_n0" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_app_rd_cmd0</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_app_rd_cmd0" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_app_rd_addr0</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_QDRIIP_ADDR_WIDTH&apos;)) )- 1 ">28</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_app_rd_addr0" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_app_rd_valid0</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_app_rd_valid0" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_app_rd_data0</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_QDRIIP_BURST_LEN&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_app_rd_data0" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_app_wr_cmd1</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_app_wr_cmd1" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_app_wr_addr1</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_QDRIIP_ADDR_WIDTH&apos;)) )- 1 ">28</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_app_wr_addr1" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_app_wr_data1</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" (( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_QDRIIP_DATA_WIDTH&apos;)) * 2 ))- 1 ">35</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_app_wr_data1" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_app_wr_bw_n1</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" (( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_QDRIIP_BW_WIDTH&apos;)) * 2 ))- 1 ">15</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_app_wr_bw_n1" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_app_rd_cmd1</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_app_rd_cmd1" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_app_rd_addr1</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_QDRIIP_ADDR_WIDTH&apos;)) )- 1 ">28</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_app_rd_addr1" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_app_rd_valid1</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_app_rd_valid1" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_app_rd_data1</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" (( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_QDRIIP_DATA_WIDTH&apos;)) * 2 ))- 1 ">35</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_app_rd_data1" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_clk</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_clk" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_rst_clk</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_rst_clk" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_qdriip_app_wr_cmd0</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_qdriip_app_wr_cmd0" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_qdriip_app_wr_addr0</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_QDRIIP_ADDR_WIDTH&apos;)) )- 1 ">28</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_qdriip_app_wr_addr0" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_qdriip_app_wr_data0</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_QDRIIP_BURST_LEN&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_qdriip_app_wr_data0" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_qdriip_app_wr_bw_n0</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_QDRIIP_BURST_LEN&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_qdriip_app_wr_bw_n0" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_qdriip_app_rd_cmd0</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_qdriip_app_rd_cmd0" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_qdriip_app_rd_addr0</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_QDRIIP_ADDR_WIDTH&apos;)) )- 1 ">28</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_qdriip_app_rd_addr0" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_qdriip_app_rd_valid0</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_qdriip_app_rd_valid0" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_qdriip_app_rd_data0</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_QDRIIP_BURST_LEN&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_qdriip_app_rd_data0" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_qdriip_app_wr_cmd1</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_qdriip_app_wr_cmd1" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_qdriip_app_wr_addr1</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_QDRIIP_ADDR_WIDTH&apos;)) )- 1 ">28</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_qdriip_app_wr_addr1" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_qdriip_app_wr_data1</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" (( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_QDRIIP_DATA_WIDTH&apos;)) * 2 ))- 1 ">35</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_qdriip_app_wr_data1" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_qdriip_app_wr_bw_n1</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" (( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_QDRIIP_BW_WIDTH&apos;)) * 2 ))- 1 ">15</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_qdriip_app_wr_bw_n1" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_qdriip_app_rd_cmd1</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_qdriip_app_rd_cmd1" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_qdriip_app_rd_addr1</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_QDRIIP_ADDR_WIDTH&apos;)) )- 1 ">28</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_qdriip_app_rd_addr1" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_qdriip_app_rd_valid1</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_qdriip_app_rd_valid1" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_qdriip_app_rd_data1</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" (( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_QDRIIP_DATA_WIDTH&apos;)) * 2 ))- 1 ">35</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_qdriip_app_rd_data1" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_qdriip_clk</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_qdriip_clk" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_qdriip_rst_clk</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_qdriip_rst_clk" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_rldii_qk_p</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_RLDII_QK_WIDTH&apos;)) )- 1 ">7</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_rldii_qk_p" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;RLDII&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_rldii_qk_n</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_RLDII_QK_WIDTH&apos;)) )- 1 ">7</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_rldii_qk_n" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;RLDII&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_rldii_dq</spirit:name>
        <spirit:wire>
          <spirit:direction>inout</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_RLDII_DATA_WIDTH&apos;)) )- 1 ">17</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_rldii_dq" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;RLDII&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_rldii_dm</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_RLDII_DM_WIDTH&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_rldii_dm" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;RLDII&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_rldii_dk_p</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_RLDII_DK_WIDTH&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_rldii_dk_p" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;RLDII&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_rldii_dk_n</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_RLDII_DK_WIDTH&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_rldii_dk_n" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;RLDII&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_rldii_ck_p</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_RLDII_NUM_DEVICES&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_rldii_ck_p" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;RLDII&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_rldii_ck_n</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_RLDII_NUM_DEVICES&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_rldii_ck_n" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;RLDII&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_rldii_cs_n</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_RLDII_NUM_DEVICES&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_rldii_cs_n" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;RLDII&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_rldii_a</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_RLDII_RLD_ADDR_WIDTH&apos;)) )- 1 ">28</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_rldii_a" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;RLDII&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_rldii_ba</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_RLDII_BANK_WIDTH&apos;)) )- 1 ">1</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_rldii_ba" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;RLDII&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_rldii_qvld</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_RLDII_QVLD_WIDTH&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_rldii_qvld" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;RLDII&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_rldii_we_n</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_rldii_we_n" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;RLDII&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_rldii_ref_n</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_rldii_ref_n" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;RLDII&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_rldii_reset_n</spirit:name>
        <spirit:displayName>reset to memory device</spirit:displayName>
        <spirit:description>reset to memory device</spirit:description>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_rldii_reset_n" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;RLDII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;RLDIII&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_rldii_dbg_pi_tap_cnt</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">4</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_rldii_dbg_pi_tap_cnt" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;RLDII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_RLDII_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_rldii_dbg_win_inc</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_rldii_dbg_win_inc" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;RLDII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_RLDII_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_rldii_dbg_win_dec</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_rldii_dbg_win_dec" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;RLDII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_RLDII_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_rldii_dbg_win_active</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_rldii_dbg_win_active" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;RLDII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_RLDII_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_rldii_dbg_win_current_byte</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">2</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_rldii_dbg_win_current_byte" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;RLDII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_RLDII_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_rldii_ila0_data</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">638</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_rldii_ila0_data" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;RLDII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_RLDII_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_rldii_ila0_trig</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">30</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_rldii_ila0_trig" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;RLDII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_RLDII_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_rldii_vio1_async_in</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">254</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_rldii_vio1_async_in" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;RLDII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_RLDII_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_rldii_vio1_async_out</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">62</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_rldii_vio1_async_out" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;RLDII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_RLDII_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_rldii_vio1_sync_out</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">62</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_rldii_vio1_sync_out" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;RLDII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_RLDII_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_rldiii_qk_p</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_RLDIII_QK_WIDTH&apos;)) )- 1 ">7</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_rldiii_qk_p" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;RLDIII&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_rldiii_qk_n</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_RLDIII_QK_WIDTH&apos;)) )- 1 ">7</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_rldiii_qk_n" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;RLDIII&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_rldiii_dq</spirit:name>
        <spirit:wire>
          <spirit:direction>inout</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_RLDIII_DATA_WIDTH&apos;)) )- 1 ">17</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_rldiii_dq" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;RLDIII&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_rldiii_dm</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_RLDIII_DM_WIDTH&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_rldiii_dm" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;RLDIII&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_rldiii_dk_p</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_RLDIII_DK_WIDTH&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_rldiii_dk_p" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;RLDIII&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_rldiii_dk_n</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_RLDIII_DK_WIDTH&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_rldiii_dk_n" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;RLDIII&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_rldiii_ck_p</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_RLDIII_NUM_DEVICES&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_rldiii_ck_p" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;RLDIII&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_rldiii_ck_n</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_RLDIII_NUM_DEVICES&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_rldiii_ck_n" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;RLDIII&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_rldiii_cs_n</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_RLDIII_NUM_DEVICES&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_rldiii_cs_n" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;RLDIII&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_rldiii_a</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_RLDIII_RLD_ADDR_WIDTH&apos;)) )- 1 ">28</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_rldiii_a" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;RLDIII&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_rldiii_ba</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_RLDIII_BANK_WIDTH&apos;)) )- 1 ">1</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_rldiii_ba" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;RLDIII&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_rldiii_qvld</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_RLDIII_QVLD_WIDTH&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_rldiii_qvld" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;RLDIII&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_rldiii_we_n</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_rldiii_we_n" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;RLDIII&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_rldiii_ref_n</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_rldiii_ref_n" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;RLDIII&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_rldiii_reset_n</spirit:name>
        <spirit:displayName>reset to memory device</spirit:displayName>
        <spirit:description>reset to memory device</spirit:description>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_rldiii_reset_n" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;RLDIII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;RLDIII&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_dbg_pi_tap_cnt</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">4</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_dbg_pi_tap_cnt" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;RLDIII&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;RLDII&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_rldiii_dbg_pi_tap_cnt</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">4</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_rldiii_dbg_pi_tap_cnt" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;RLDIII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_RLDIII_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_rldiii_dbg_win_inc</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_rldiii_dbg_win_inc" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;RLDIII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_RLDIII_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_rldiii_dbg_win_dec</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_rldiii_dbg_win_dec" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;RLDIII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_RLDIII_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_rldiii_dbg_win_active</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_rldiii_dbg_win_active" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;RLDIII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_RLDIII_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_rldiii_dbg_win_current_byte</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">2</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_rldiii_dbg_win_current_byte" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;RLDIII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_RLDIII_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_rldiii_ila0_data</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">638</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_rldiii_ila0_data" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;RLDIII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_RLDIII_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_rldiii_ila0_trig</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">30</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_rldiii_ila0_trig" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;RLDIII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_RLDIII_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_rldiii_vio1_async_in</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">254</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_rldiii_vio1_async_in" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;RLDIII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_RLDIII_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_rldiii_vio1_async_out</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">62</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_rldiii_vio1_async_out" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;RLDIII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_RLDIII_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_rldiii_vio1_sync_out</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">62</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_rldiii_vio1_sync_out" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;RLDIII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_RLDIII_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_dbg_win_inc</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_dbg_win_inc" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;RLDIII&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;RLDII&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_dbg_win_dec</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_dbg_win_dec" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;RLDIII&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;RLDII&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_dbg_win_active</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_dbg_win_active" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;RLDIII&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;RLDII&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_dbg_win_current_byte</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">2</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_dbg_win_current_byte" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;RLDIII&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;RLDII&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_dbg_pi_counter_read_val</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">4</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_dbg_pi_counter_read_val" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;DDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_user_cmd_en</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_user_cmd_en" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;RLDII&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;RLDIII&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_user_cmd</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_RLDX_CMD_PER_CLK&apos;)) * 2 )- 1 ">1</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_user_cmd" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;RLDII&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;RLDIII&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_user_addr</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_RLDX_ADDR_WIDTH&apos;)) * spirit:decode(id(&apos;MODELPARAM_VALUE.C0_RLDX_CMD_PER_CLK&apos;)) )- 1 ">28</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_user_addr" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;RLDII&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;RLDIII&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_user_ba</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_RLDX_BANK_WIDTH&apos;)) * spirit:decode(id(&apos;MODELPARAM_VALUE.C0_RLDX_CMD_PER_CLK&apos;)) )- 1 ">1</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_user_ba" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;RLDII&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;RLDIII&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_user_wr_en</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_user_wr_en" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;RLDII&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;RLDIII&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_user_wr_data</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_RLDX_DATA_WIDTH&apos;)) * 2 * spirit:decode(id(&apos;MODELPARAM_VALUE.C0_RLDX_nCK_PER_CLK&apos;)) )- 1 ">35</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_user_wr_data" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;RLDII&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;RLDIII&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_user_wr_dm</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_RLDX_DM_WIDTH&apos;)) * 2 * spirit:decode(id(&apos;MODELPARAM_VALUE.C0_RLDX_nCK_PER_CLK&apos;)) )- 1 ">1</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_user_wr_dm" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;RLDII&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;RLDIII&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_user_afifo_empty</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_user_afifo_empty" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;RLDII&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;RLDIII&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_user_afifo_full</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_user_afifo_full" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;RLDII&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;RLDIII&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_user_afifo_aempty</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_user_afifo_aempty" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;RLDII&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;RLDIII&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_user_afifo_afull</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_user_afifo_afull" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;RLDII&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;RLDIII&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_user_wdfifo_empty</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_user_wdfifo_empty" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;RLDII&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;RLDIII&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_user_wdfifo_full</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_user_wdfifo_full" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;RLDII&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;RLDIII&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_user_wdfifo_aempty</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_user_wdfifo_aempty" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;RLDII&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;RLDIII&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_user_wdfifo_afull</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_user_wdfifo_afull" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;RLDII&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;RLDIII&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_user_rd_valid</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_RLDX_nCK_PER_CLK&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_user_rd_valid" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;RLDII&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;RLDIII&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_mem_ck_lock_complete</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_mem_ck_lock_complete" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;RLDII&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;RLDIII&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_user_rd_data</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_RLDX_DATA_WIDTH&apos;)) * 2 * spirit:decode(id(&apos;MODELPARAM_VALUE.C0_RLDX_nCK_PER_CLK&apos;)) )- 1 ">35</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_user_rd_data" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;RLDII&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;RLDIII&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_rldii_user_cmd_en</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_rldii_user_cmd_en" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;RLDII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_rldii_user_cmd</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_RLDII_CMD_PER_CLK&apos;)) * 2 )- 1 ">1</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_rldii_user_cmd" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;RLDII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_rldii_user_addr</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_RLDII_ADDR_WIDTH&apos;)) * spirit:decode(id(&apos;MODELPARAM_VALUE.C0_RLDII_CMD_PER_CLK&apos;)) )- 1 ">28</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_rldii_user_addr" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;RLDII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_rldii_user_ba</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_RLDII_BANK_WIDTH&apos;)) * spirit:decode(id(&apos;MODELPARAM_VALUE.C0_RLDII_CMD_PER_CLK&apos;)) )- 1 ">1</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_rldii_user_ba" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;RLDII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_rldii_user_wr_en</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_rldii_user_wr_en" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;RLDII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_rldii_user_wr_data</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_RLDII_DATA_WIDTH&apos;)) * 2 * spirit:decode(id(&apos;MODELPARAM_VALUE.C0_RLDII_nCK_PER_CLK&apos;)) )- 1 ">35</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_rldii_user_wr_data" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;RLDII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_rldii_user_wr_dm</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_RLDII_DM_WIDTH&apos;)) * 2 * spirit:decode(id(&apos;MODELPARAM_VALUE.C0_RLDII_nCK_PER_CLK&apos;)) )- 1 ">1</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_rldii_user_wr_dm" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;RLDII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_rldii_user_afifo_empty</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_rldii_user_afifo_empty" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;RLDII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_rldii_user_afifo_full</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_rldii_user_afifo_full" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;RLDII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_rldii_user_afifo_aempty</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_rldii_user_afifo_aempty" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;RLDII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_rldii_user_afifo_afull</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_rldii_user_afifo_afull" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;RLDII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_rldii_user_wdfifo_empty</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_rldii_user_wdfifo_empty" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;RLDII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_rldii_user_wdfifo_full</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_rldii_user_wdfifo_full" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;RLDII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_rldii_user_wdfifo_aempty</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_rldii_user_wdfifo_aempty" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;RLDII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_rldii_user_wdfifo_afull</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_rldii_user_wdfifo_afull" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;RLDII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_rldii_user_rd_valid</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_RLDII_nCK_PER_CLK&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_rldii_user_rd_valid" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;RLDII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_rldii_mem_ck_lock_complete</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_rldii_mem_ck_lock_complete" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;RLDII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_rldii_user_rd_data</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_RLDII_DATA_WIDTH&apos;)) * 2 * spirit:decode(id(&apos;MODELPARAM_VALUE.C0_RLDII_nCK_PER_CLK&apos;)) )- 1 ">35</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_rldii_user_rd_data" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;RLDII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_rldiii_user_cmd_en</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_rldiii_user_cmd_en" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;RLDIII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_rldiii_user_cmd</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_RLDIII_CMD_PER_CLK&apos;)) * 2 )- 1 ">1</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_rldiii_user_cmd" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;RLDIII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_rldiii_user_addr</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_RLDIII_ADDR_WIDTH&apos;)) * spirit:decode(id(&apos;MODELPARAM_VALUE.C0_RLDIII_CMD_PER_CLK&apos;)) )- 1 ">28</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_rldiii_user_addr" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;RLDIII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_rldiii_user_ba</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_RLDIII_BANK_WIDTH&apos;)) * spirit:decode(id(&apos;MODELPARAM_VALUE.C0_RLDIII_CMD_PER_CLK&apos;)) )- 1 ">1</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_rldiii_user_ba" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;RLDIII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_rldiii_user_wr_en</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_rldiii_user_wr_en" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;RLDIII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_rldiii_user_wr_data</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_RLDIII_DATA_WIDTH&apos;)) * 2 * spirit:decode(id(&apos;MODELPARAM_VALUE.C0_RLDIII_nCK_PER_CLK&apos;)) )- 1 ">35</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_rldiii_user_wr_data" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;RLDIII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_rldiii_user_wr_dm</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_RLDIII_DM_WIDTH&apos;)) * 2 * spirit:decode(id(&apos;MODELPARAM_VALUE.C0_RLDIII_nCK_PER_CLK&apos;)) )- 1 ">1</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_rldiii_user_wr_dm" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;RLDIII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_rldiii_user_afifo_empty</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_rldiii_user_afifo_empty" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;RLDIII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_rldiii_user_afifo_full</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_rldiii_user_afifo_full" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;RLDIII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_rldiii_user_afifo_aempty</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_rldiii_user_afifo_aempty" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;RLDIII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_rldiii_user_afifo_afull</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_rldiii_user_afifo_afull" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;RLDIII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_rldiii_user_wdfifo_empty</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_rldiii_user_wdfifo_empty" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;RLDIII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_rldiii_user_wdfifo_full</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_rldiii_user_wdfifo_full" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;RLDIII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_rldiii_user_wdfifo_aempty</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_rldiii_user_wdfifo_aempty" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;RLDIII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_rldiii_user_wdfifo_afull</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_rldiii_user_wdfifo_afull" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;RLDIII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_rldiii_user_rd_valid</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_RLDIII_nCK_PER_CLK&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_rldiii_user_rd_valid" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;RLDIII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_rldiii_mem_ck_lock_complete</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_rldiii_mem_ck_lock_complete" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;RLDIII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_rldiii_user_rd_data</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_RLDIII_DATA_WIDTH&apos;)) * 2 * spirit:decode(id(&apos;MODELPARAM_VALUE.C0_RLDIII_nCK_PER_CLK&apos;)) )- 1 ">35</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_rldiii_user_rd_data" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;RLDIII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_sys_clk_p</spirit:name>
        <spirit:displayName>Clock P</spirit:displayName>
        <spirit:description>Clock P</spirit:description>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_sys_clk_p" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_SYSCLK_TYPE&apos;)) = &quot;DIFF&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_IS_CLK_SHARED&apos;)) = &quot;FALSE&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_sys_clk_n</spirit:name>
        <spirit:displayName>Clock P</spirit:displayName>
        <spirit:description>Clock P</spirit:description>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_sys_clk_n" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_SYSCLK_TYPE&apos;)) = &quot;DIFF&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_IS_CLK_SHARED&apos;)) = &quot;FALSE&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_sys_clk_i</spirit:name>
        <spirit:displayName>Clock P</spirit:displayName>
        <spirit:description>Clock P</spirit:description>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_sys_clk_i" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_SYSCLK_TYPE&apos;)) != &quot;DIFF&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C0_IS_CLK_SHARED&apos;)) = &quot;FALSE&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_init_calib_complete</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_init_calib_complete" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c0_aresetn</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_aresetn" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C0_MEM_TYPE&apos;)) = &quot;DDR2&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_ddr3_dq</spirit:name>
        <spirit:displayName>Data</spirit:displayName>
        <spirit:description>Data</spirit:description>
        <spirit:wire>
          <spirit:direction>inout</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_DDR3_DQ_WIDTH&apos;)) )- 1 ">7</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_ddr3_dq" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;DDR3&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_ddr3_dqs_p</spirit:name>
        <spirit:displayName>Data Strobe</spirit:displayName>
        <spirit:description>Data Strobe</spirit:description>
        <spirit:wire>
          <spirit:direction>inout</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_DDR3_DQS_WIDTH&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_ddr3_dqs_p" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;DDR3&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_ddr3_dqs_n</spirit:name>
        <spirit:displayName>Data Strobe</spirit:displayName>
        <spirit:description>Data Strobe</spirit:description>
        <spirit:wire>
          <spirit:direction>inout</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_DDR3_DQS_WIDTH&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_ddr3_dqs_n" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;DDR3&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_ddr3_addr</spirit:name>
        <spirit:displayName>Address</spirit:displayName>
        <spirit:description>Address</spirit:description>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_DDR3_ROW_WIDTH&apos;)) )- 1 ">13</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_ddr3_addr" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;DDR3&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_ddr3_ba</spirit:name>
        <spirit:displayName>Bank Address</spirit:displayName>
        <spirit:description>Bank Address</spirit:description>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_DDR3_BANK_WIDTH&apos;)) )- 1 ">2</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_ddr3_ba" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;DDR3&quot; and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;DDR2&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_ddr3_ras_n</spirit:name>
        <spirit:displayName>row address strobe</spirit:displayName>
        <spirit:description>row address strobe</spirit:description>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_ddr3_ras_n" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;DDR3&quot; and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;DDR2&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_ddr3_cas_n</spirit:name>
        <spirit:displayName>column address strobe</spirit:displayName>
        <spirit:description>column address strobe</spirit:description>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_ddr3_cas_n" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;DDR3&quot; and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;DDR2&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_ddr3_we_n</spirit:name>
        <spirit:displayName>write enable</spirit:displayName>
        <spirit:description>write enable</spirit:description>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_ddr3_we_n" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;DDR3&quot; and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;DDR2&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_ddr3_reset_n</spirit:name>
        <spirit:displayName>reset to memory device</spirit:displayName>
        <spirit:description>reset to memory device</spirit:description>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_ddr3_reset_n" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;DDR3&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_ddr3_ck_p</spirit:name>
        <spirit:displayName>clock to memory device</spirit:displayName>
        <spirit:description>clock to memory device</spirit:description>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_DDR3_CK_WIDTH&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_ddr3_ck_p" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;DDR3&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_ddr3_ck_n</spirit:name>
        <spirit:displayName>clock to memory device</spirit:displayName>
        <spirit:description>clock to memory device</spirit:description>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_DDR3_CK_WIDTH&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_ddr3_ck_n" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;DDR3&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_ddr3_cke</spirit:name>
        <spirit:displayName>clock enable</spirit:displayName>
        <spirit:description>clock enable</spirit:description>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_DDR3_CKE_WIDTH&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_ddr3_cke" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;DDR3&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_ddr3_cs_n</spirit:name>
        <spirit:displayName>chip select</spirit:displayName>
        <spirit:description>chip select</spirit:description>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_DDR3_CS_WIDTH&apos;)) * spirit:decode(id(&apos;MODELPARAM_VALUE.C1_DDR3_nCS_PER_RANK&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_ddr3_cs_n" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_DDR3_USE_CS_PORT&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_ddr3_dm</spirit:name>
        <spirit:displayName>data mask</spirit:displayName>
        <spirit:description>data mask</spirit:description>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_DDR3_DM_WIDTH&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_ddr3_dm" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_DDR3_USE_DM_PORT&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_ddr3_odt</spirit:name>
        <spirit:displayName>on die termination</spirit:displayName>
        <spirit:description>on die termination</spirit:description>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_DDR3_ODT_WIDTH&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_ddr3_odt" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;DDR3&quot; and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;DDR2&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_DDR3_USE_ODT_PORT&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_ddr3_parity</spirit:name>
        <spirit:displayName>parity bit</spirit:displayName>
        <spirit:description>parity bit</spirit:description>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_ddr3_parity" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_DDR3_REG_CTRL&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_ddr3_dbg_pi_counter_read_val</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">4</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_ddr3_dbg_pi_counter_read_val" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_DDR3_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_ddr3_dbg_byte_sel</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_DDR3_DQS_CNT_WIDTH&apos;)) + 1 )- 1 ">1</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_ddr3_dbg_byte_sel" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_DDR3_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_ddr3_dbg_sel_pi_incdec</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_ddr3_dbg_sel_pi_incdec" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_DDR3_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_ddr3_dbg_pi_f_inc</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_ddr3_dbg_pi_f_inc" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_DDR3_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_ddr3_dbg_pi_f_dec</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_ddr3_dbg_pi_f_dec" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_DDR3_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_ddr3_dbg_sel_po_incdec</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_ddr3_dbg_sel_po_incdec" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_DDR3_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_ddr3_dbg_po_f_inc</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_ddr3_dbg_po_f_inc" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_DDR3_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_ddr3_dbg_po_f_stg23_sel</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_ddr3_dbg_po_f_stg23_sel" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_DDR3_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_ddr3_dbg_po_f_dec</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_ddr3_dbg_po_f_dec" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_DDR3_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_ddr3_dbg_po_counter_read_val</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">7</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_ddr3_dbg_po_counter_read_val" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_DDR3_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_ddr3_ila_wrpath</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">254</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_ddr3_ila_wrpath" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_DDR3_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_ddr3_ila_rdpath</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">1022</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_ddr3_ila_rdpath" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_DDR3_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_ddr3_ila_basic</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">126</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_ddr3_ila_basic" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_DDR3_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_ddr3_vio_sync_out</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">34</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_ddr3_vio_sync_out" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_DDR3_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_ddr2_dq</spirit:name>
        <spirit:displayName>Data</spirit:displayName>
        <spirit:description>Data</spirit:description>
        <spirit:wire>
          <spirit:direction>inout</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_DDR2_DQ_WIDTH&apos;)) )- 1 ">7</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_ddr2_dq" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;DDR2&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_ddr2_dqs_p</spirit:name>
        <spirit:displayName>Data Strobe</spirit:displayName>
        <spirit:description>Data Strobe</spirit:description>
        <spirit:wire>
          <spirit:direction>inout</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_DDR2_DQS_WIDTH&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_ddr2_dqs_p" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;DDR2&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_ddr2_dqs_n</spirit:name>
        <spirit:displayName>Data Strobe</spirit:displayName>
        <spirit:description>Data Strobe</spirit:description>
        <spirit:wire>
          <spirit:direction>inout</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_DDR2_DQS_WIDTH&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_ddr2_dqs_n" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;DDR2&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_ddr2_addr</spirit:name>
        <spirit:displayName>Address</spirit:displayName>
        <spirit:description>Address</spirit:description>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_DDR2_ROW_WIDTH&apos;)) )- 1 ">13</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_ddr2_addr" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;DDR2&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_ddr2_ba</spirit:name>
        <spirit:displayName>Bank Address</spirit:displayName>
        <spirit:description>Bank Address</spirit:description>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_DDR2_BANK_WIDTH&apos;)) )- 1 ">2</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_ddr2_ba" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;DDR2&quot; and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;DDR2&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_ddr2_ras_n</spirit:name>
        <spirit:displayName>row address strobe</spirit:displayName>
        <spirit:description>row address strobe</spirit:description>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_ddr2_ras_n" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;DDR2&quot; and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;DDR2&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_ddr2_cas_n</spirit:name>
        <spirit:displayName>column address strobe</spirit:displayName>
        <spirit:description>column address strobe</spirit:description>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_ddr2_cas_n" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;DDR2&quot; and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;DDR2&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_ddr2_we_n</spirit:name>
        <spirit:displayName>write enable</spirit:displayName>
        <spirit:description>write enable</spirit:description>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_ddr2_we_n" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;DDR2&quot; and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;DDR2&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_ddr2_reset_n</spirit:name>
        <spirit:displayName>reset to memory device</spirit:displayName>
        <spirit:description>reset to memory device</spirit:description>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_ddr2_reset_n" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;DDR3&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_ddr2_ck_p</spirit:name>
        <spirit:displayName>clock to memory device</spirit:displayName>
        <spirit:description>clock to memory device</spirit:description>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_DDR2_CK_WIDTH&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_ddr2_ck_p" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;DDR2&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_ddr2_ck_n</spirit:name>
        <spirit:displayName>clock to memory device</spirit:displayName>
        <spirit:description>clock to memory device</spirit:description>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_DDR2_CK_WIDTH&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_ddr2_ck_n" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;DDR2&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_ddr2_cke</spirit:name>
        <spirit:displayName>clock enable</spirit:displayName>
        <spirit:description>clock enable</spirit:description>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_DDR2_CKE_WIDTH&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_ddr2_cke" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;DDR2&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_ddr2_cs_n</spirit:name>
        <spirit:displayName>chip select</spirit:displayName>
        <spirit:description>chip select</spirit:description>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_DDR2_CS_WIDTH&apos;)) * spirit:decode(id(&apos;MODELPARAM_VALUE.C1_DDR2_nCS_PER_RANK&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_ddr2_cs_n" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_DDR2_USE_CS_PORT&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_ddr2_dm</spirit:name>
        <spirit:displayName>data mask</spirit:displayName>
        <spirit:description>data mask</spirit:description>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_DDR2_DM_WIDTH&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_ddr2_dm" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_DDR2_USE_DM_PORT&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_ddr2_odt</spirit:name>
        <spirit:displayName>on die termination</spirit:displayName>
        <spirit:description>on die termination</spirit:description>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_DDR2_ODT_WIDTH&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_ddr2_odt" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;DDR2&quot; and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;DDR2&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_DDR2_USE_ODT_PORT&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_ddr2_parity</spirit:name>
        <spirit:displayName>parity bit</spirit:displayName>
        <spirit:description>parity bit</spirit:description>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_ddr2_parity" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_DDR2_REG_CTRL&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_ddr2_dbg_pi_counter_read_val</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">4</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_ddr2_dbg_pi_counter_read_val" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_DDR2_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_ddr2_dbg_byte_sel</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_DDR2_DQS_CNT_WIDTH&apos;)) + 1 )- 1 ">1</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_ddr2_dbg_byte_sel" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_DDR2_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_ddr2_dbg_sel_pi_incdec</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_ddr2_dbg_sel_pi_incdec" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_DDR2_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_ddr2_dbg_pi_f_inc</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_ddr2_dbg_pi_f_inc" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_DDR2_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_ddr2_dbg_pi_f_dec</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_ddr2_dbg_pi_f_dec" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_DDR2_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_ddr2_dbg_sel_po_incdec</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_ddr2_dbg_sel_po_incdec" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_DDR2_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_ddr2_dbg_po_f_inc</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_ddr2_dbg_po_f_inc" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_DDR2_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_ddr2_dbg_po_f_stg23_sel</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_ddr2_dbg_po_f_stg23_sel" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_DDR2_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_ddr2_dbg_po_f_dec</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_ddr2_dbg_po_f_dec" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_DDR2_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_ddr2_dbg_po_counter_read_val</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">7</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_ddr2_dbg_po_counter_read_val" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_DDR2_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_ddr2_ila_wrpath</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">254</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_ddr2_ila_wrpath" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_DDR2_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_ddr2_ila_rdpath</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">1022</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_ddr2_ila_rdpath" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_DDR2_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_ddr2_ila_basic</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">126</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_ddr2_ila_basic" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_DDR2_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_ddr2_vio_sync_out</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">34</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_ddr2_vio_sync_out" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_DDR2_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_lpddr2_dq</spirit:name>
        <spirit:displayName>Data</spirit:displayName>
        <spirit:description>Data</spirit:description>
        <spirit:wire>
          <spirit:direction>inout</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_LPDDR2_DQ_WIDTH&apos;)) )- 1 ">7</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_lpddr2_dq" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_lpddr2_dqs_p</spirit:name>
        <spirit:displayName>Data Strobe</spirit:displayName>
        <spirit:description>Data Strobe</spirit:description>
        <spirit:wire>
          <spirit:direction>inout</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_LPDDR2_DQS_WIDTH&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_lpddr2_dqs_p" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_lpddr2_dqs_n</spirit:name>
        <spirit:displayName>Data Strobe</spirit:displayName>
        <spirit:description>Data Strobe</spirit:description>
        <spirit:wire>
          <spirit:direction>inout</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_LPDDR2_DQS_WIDTH&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_lpddr2_dqs_n" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_lpddr2_ca</spirit:name>
        <spirit:displayName>Address</spirit:displayName>
        <spirit:description>Address</spirit:description>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">9</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_lpddr2_ca" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_lpddr2_ck_p</spirit:name>
        <spirit:displayName>clock to memory device</spirit:displayName>
        <spirit:description>clock to memory device</spirit:description>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_LPDDR2_CK_WIDTH&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_lpddr2_ck_p" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_lpddr2_ck_n</spirit:name>
        <spirit:displayName>clock to memory device</spirit:displayName>
        <spirit:description>clock to memory device</spirit:description>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_LPDDR2_CK_WIDTH&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_lpddr2_ck_n" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_lpddr2_cke</spirit:name>
        <spirit:displayName>clock enable</spirit:displayName>
        <spirit:description>clock enable</spirit:description>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_LPDDR2_CKE_WIDTH&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_lpddr2_cke" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_lpddr2_cs_n</spirit:name>
        <spirit:displayName>chip select</spirit:displayName>
        <spirit:description>chip select</spirit:description>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_LPDDR2_CS_WIDTH&apos;)) * spirit:decode(id(&apos;MODELPARAM_VALUE.C1_LPDDR2_nCS_PER_RANK&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_lpddr2_cs_n" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_LPDDR2_USE_CS_PORT&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_lpddr2_dm</spirit:name>
        <spirit:displayName>data mask</spirit:displayName>
        <spirit:description>data mask</spirit:description>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_LPDDR2_DM_WIDTH&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_lpddr2_dm" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_LPDDR2_USE_DM_PORT&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_lpddr2_parity</spirit:name>
        <spirit:displayName>parity bit</spirit:displayName>
        <spirit:description>parity bit</spirit:description>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_lpddr2_parity" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_LPDDR2_REG_CTRL&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_lpddr2_dbg_pi_counter_read_val</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">4</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_lpddr2_dbg_pi_counter_read_val" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_LPDDR2_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_lpddr2_dbg_byte_sel</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_LPDDR2_DQS_CNT_WIDTH&apos;)) + 1 )- 1 ">1</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_lpddr2_dbg_byte_sel" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_LPDDR2_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_lpddr2_dbg_sel_pi_incdec</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_lpddr2_dbg_sel_pi_incdec" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_LPDDR2_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_lpddr2_dbg_pi_f_inc</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_lpddr2_dbg_pi_f_inc" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_LPDDR2_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_lpddr2_dbg_pi_f_dec</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_lpddr2_dbg_pi_f_dec" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_LPDDR2_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_lpddr2_dbg_sel_po_incdec</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_lpddr2_dbg_sel_po_incdec" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_LPDDR2_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_lpddr2_dbg_po_f_inc</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_lpddr2_dbg_po_f_inc" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_LPDDR2_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_lpddr2_dbg_po_f_stg23_sel</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_lpddr2_dbg_po_f_stg23_sel" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_LPDDR2_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_lpddr2_dbg_po_f_dec</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_lpddr2_dbg_po_f_dec" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_LPDDR2_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_lpddr2_dbg_po_counter_read_val</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">7</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_lpddr2_dbg_po_counter_read_val" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_LPDDR2_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_lpddr2_ila_wrpath</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">254</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_lpddr2_ila_wrpath" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_LPDDR2_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_lpddr2_ila_rdpath</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">1022</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_lpddr2_ila_rdpath" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_LPDDR2_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_lpddr2_ila_basic</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">126</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_lpddr2_ila_basic" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_LPDDR2_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_lpddr2_vio_sync_out</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">34</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_lpddr2_vio_sync_out" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_LPDDR2_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_dbg_byte_sel</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_DQS_CNT_WIDTH&apos;)) + 1 )- 1 ">1</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_dbg_byte_sel" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;DDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_dbg_sel_pi_incdec</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_dbg_sel_pi_incdec" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;DDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_dbg_pi_f_inc</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_dbg_pi_f_inc" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;DDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_dbg_pi_f_dec</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_dbg_pi_f_dec" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;DDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_dbg_sel_po_incdec</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_dbg_sel_po_incdec" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;DDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_dbg_po_f_inc</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_dbg_po_f_inc" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;DDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_dbg_po_f_stg23_sel</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_dbg_po_f_stg23_sel" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;DDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_dbg_po_f_dec</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_dbg_po_f_dec" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;DDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_dbg_po_counter_read_val</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">7</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_dbg_po_counter_read_val" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;DDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_app_addr</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_DDRX_ADDR_WIDTH&apos;)) )- 1 ">7</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_app_addr" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;DDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_app_cmd</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">2</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_app_cmd" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;DDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_app_en</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_app_en" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;DDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_app_wdf_data</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_DDRX_nCK_PER_CLK&apos;)) * 2 * spirit:decode(id(&apos;MODELPARAM_VALUE.C1_DDRX_DATA_WIDTH&apos;)) )- 1 ">31</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_app_wdf_data" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;DDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_app_wdf_end</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_app_wdf_end" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;DDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_app_wdf_mask</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_DDRX_nCK_PER_CLK&apos;)) * 2 * spirit:decode(id(&apos;MODELPARAM_VALUE.C1_DDRX_DATA_WIDTH&apos;)) / 8 )- 1 ">3</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_app_wdf_mask" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;DDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_app_wdf_wren</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_app_wdf_wren" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;DDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_app_correct_en_i</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_app_correct_en_i" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;DDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_ECC&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_app_rd_data</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_DDRX_nCK_PER_CLK&apos;)) * 2 * spirit:decode(id(&apos;MODELPARAM_VALUE.C1_DDRX_DATA_WIDTH&apos;)) )- 1 ">31</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_app_rd_data" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;DDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_app_rd_data_end</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_app_rd_data_end" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;DDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_app_rd_data_valid</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_app_rd_data_valid" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;DDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_app_rdy</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_app_rdy" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;DDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_app_wdf_rdy</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_app_wdf_rdy" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;DDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_app_sr_req</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_app_sr_req" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;DDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_app_sr_active</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_app_sr_active" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;DDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_app_ref_req</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_app_ref_req" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;DDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_app_ref_ack</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_app_ref_ack" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;DDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_app_zq_req</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_app_zq_req" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;DDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_app_zq_ack</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_app_zq_ack" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;DDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_app_raw_not_ecc</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( 2 * spirit:decode(id(&apos;MODELPARAM_VALUE.C1_DDRX_nCK_PER_CLK&apos;)) )- 1 ">3</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_app_raw_not_ecc" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;DDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_ECC&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_app_ecc_multiple_err</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( 2 * spirit:decode(id(&apos;MODELPARAM_VALUE.C1_DDRX_nCK_PER_CLK&apos;)) )- 1 ">3</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_app_ecc_multiple_err" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;DDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_ECC&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_ddr3_app_addr</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_DDR3_ADDR_WIDTH&apos;)) )- 1 ">7</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_ddr3_app_addr" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_ddr3_app_cmd</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">2</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_ddr3_app_cmd" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_ddr3_app_en</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_ddr3_app_en" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_ddr3_app_wdf_data</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_DDR3_nCK_PER_CLK&apos;)) * 2 * spirit:decode(id(&apos;MODELPARAM_VALUE.C1_DDR3_DATA_WIDTH&apos;)) )- 1 ">31</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_ddr3_app_wdf_data" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_ddr3_app_wdf_end</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_ddr3_app_wdf_end" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_ddr3_app_wdf_mask</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_DDR3_nCK_PER_CLK&apos;)) * 2 * spirit:decode(id(&apos;MODELPARAM_VALUE.C1_DDR3_DATA_WIDTH&apos;)) / 8 )- 1 ">3</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_ddr3_app_wdf_mask" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_ddr3_app_wdf_wren</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_ddr3_app_wdf_wren" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_ddr3_app_correct_en_i</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_ddr3_app_correct_en_i" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_ECC&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_ddr3_app_rd_data</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_DDR3_nCK_PER_CLK&apos;)) * 2 * spirit:decode(id(&apos;MODELPARAM_VALUE.C1_DDR3_DATA_WIDTH&apos;)) )- 1 ">31</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_ddr3_app_rd_data" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_ddr3_app_rd_data_end</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_ddr3_app_rd_data_end" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_ddr3_app_rd_data_valid</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_ddr3_app_rd_data_valid" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_ddr3_app_rdy</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_ddr3_app_rdy" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_ddr3_app_wdf_rdy</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_ddr3_app_wdf_rdy" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_ddr3_app_sr_req</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_ddr3_app_sr_req" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_ddr3_app_sr_active</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_ddr3_app_sr_active" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_ddr3_app_ref_req</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_ddr3_app_ref_req" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_ddr3_app_ref_ack</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_ddr3_app_ref_ack" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_ddr3_app_zq_req</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_ddr3_app_zq_req" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_ddr3_app_zq_ack</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_ddr3_app_zq_ack" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_ddr3_app_raw_not_ecc</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( 2 * spirit:decode(id(&apos;MODELPARAM_VALUE.C1_DDR3_nCK_PER_CLK&apos;)) )- 1 ">3</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_ddr3_app_raw_not_ecc" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_ECC&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_ddr3_app_ecc_multiple_err</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( 2 * spirit:decode(id(&apos;MODELPARAM_VALUE.C1_DDR3_nCK_PER_CLK&apos;)) )- 1 ">3</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_ddr3_app_ecc_multiple_err" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_ECC&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_ddr2_app_addr</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_DDR2_ADDR_WIDTH&apos;)) )- 1 ">7</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_ddr2_app_addr" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_ddr2_app_cmd</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">2</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_ddr2_app_cmd" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_ddr2_app_en</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_ddr2_app_en" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_ddr2_app_wdf_data</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_DDR2_nCK_PER_CLK&apos;)) * 2 * spirit:decode(id(&apos;MODELPARAM_VALUE.C1_DDR2_DATA_WIDTH&apos;)) )- 1 ">31</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_ddr2_app_wdf_data" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_ddr2_app_wdf_end</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_ddr2_app_wdf_end" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_ddr2_app_wdf_mask</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_DDR2_nCK_PER_CLK&apos;)) * 2 * spirit:decode(id(&apos;MODELPARAM_VALUE.C1_DDR2_DATA_WIDTH&apos;)) / 8 )- 1 ">3</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_ddr2_app_wdf_mask" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_ddr2_app_wdf_wren</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_ddr2_app_wdf_wren" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_ddr2_app_correct_en_i</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_ddr2_app_correct_en_i" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_ECC&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_ddr2_app_rd_data</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_DDR2_nCK_PER_CLK&apos;)) * 2 * spirit:decode(id(&apos;MODELPARAM_VALUE.C1_DDR2_DATA_WIDTH&apos;)) )- 1 ">31</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_ddr2_app_rd_data" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_ddr2_app_rd_data_end</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_ddr2_app_rd_data_end" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_ddr2_app_rd_data_valid</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_ddr2_app_rd_data_valid" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_ddr2_app_rdy</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_ddr2_app_rdy" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_ddr2_app_wdf_rdy</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_ddr2_app_wdf_rdy" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_ddr2_app_sr_req</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_ddr2_app_sr_req" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_ddr2_app_sr_active</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_ddr2_app_sr_active" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_ddr2_app_ref_req</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_ddr2_app_ref_req" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_ddr2_app_ref_ack</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_ddr2_app_ref_ack" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_ddr2_app_zq_req</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_ddr2_app_zq_req" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_ddr2_app_zq_ack</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_ddr2_app_zq_ack" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_ddr2_app_raw_not_ecc</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( 2 * spirit:decode(id(&apos;MODELPARAM_VALUE.C1_DDR2_nCK_PER_CLK&apos;)) )- 1 ">3</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_ddr2_app_raw_not_ecc" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_ECC&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_ddr2_app_ecc_multiple_err</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( 2 * spirit:decode(id(&apos;MODELPARAM_VALUE.C1_DDR2_nCK_PER_CLK&apos;)) )- 1 ">3</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_ddr2_app_ecc_multiple_err" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_ECC&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_lpddr2_app_addr</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_LPDDR2_ADDR_WIDTH&apos;)) )- 1 ">7</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_lpddr2_app_addr" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_lpddr2_app_cmd</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">2</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_lpddr2_app_cmd" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_lpddr2_app_en</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_lpddr2_app_en" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_lpddr2_app_wdf_data</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_LPDDR2_nCK_PER_CLK&apos;)) * 2 * spirit:decode(id(&apos;MODELPARAM_VALUE.C1_LPDDR2_DATA_WIDTH&apos;)) )- 1 ">31</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_lpddr2_app_wdf_data" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_lpddr2_app_wdf_end</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_lpddr2_app_wdf_end" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_lpddr2_app_wdf_mask</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_LPDDR2_nCK_PER_CLK&apos;)) * 2 * spirit:decode(id(&apos;MODELPARAM_VALUE.C1_LPDDR2_DATA_WIDTH&apos;)) / 8 )- 1 ">3</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_lpddr2_app_wdf_mask" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_lpddr2_app_wdf_wren</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_lpddr2_app_wdf_wren" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_lpddr2_app_correct_en_i</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_lpddr2_app_correct_en_i" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_ECC&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_lpddr2_app_rd_data</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_LPDDR2_nCK_PER_CLK&apos;)) * 2 * spirit:decode(id(&apos;MODELPARAM_VALUE.C1_LPDDR2_DATA_WIDTH&apos;)) )- 1 ">31</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_lpddr2_app_rd_data" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_lpddr2_app_rd_data_end</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_lpddr2_app_rd_data_end" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_lpddr2_app_rd_data_valid</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_lpddr2_app_rd_data_valid" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_lpddr2_app_rdy</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_lpddr2_app_rdy" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_lpddr2_app_wdf_rdy</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_lpddr2_app_wdf_rdy" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_lpddr2_app_sr_req</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_lpddr2_app_sr_req" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_lpddr2_app_sr_active</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_lpddr2_app_sr_active" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_lpddr2_app_ref_req</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_lpddr2_app_ref_req" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_lpddr2_app_ref_ack</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_lpddr2_app_ref_ack" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_lpddr2_app_zq_req</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_lpddr2_app_zq_req" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_lpddr2_app_zq_ack</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_lpddr2_app_zq_ack" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_lpddr2_app_raw_not_ecc</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( 2 * spirit:decode(id(&apos;MODELPARAM_VALUE.C1_LPDDR2_nCK_PER_CLK&apos;)) )- 1 ">3</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_lpddr2_app_raw_not_ecc" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_ECC&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_lpddr2_app_ecc_multiple_err</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( 2 * spirit:decode(id(&apos;MODELPARAM_VALUE.C1_LPDDR2_nCK_PER_CLK&apos;)) )- 1 ">3</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_lpddr2_app_ecc_multiple_err" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_ECC&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_ui_clk_sync_rst</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_ui_clk_sync_rst" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;DDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;RLDII&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;RLDIII&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_ddr3_ui_clk_sync_rst</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_ddr3_ui_clk_sync_rst" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;DDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;RLDII&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;RLDIII&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_ddr2_ui_clk_sync_rst</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_ddr2_ui_clk_sync_rst" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;DDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;RLDII&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;RLDIII&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_lpddr2_ui_clk_sync_rst</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_lpddr2_ui_clk_sync_rst" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;DDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;RLDII&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;RLDIII&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_qdriip_ui_clk_sync_rst</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_qdriip_ui_clk_sync_rst" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;DDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;RLDII&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;RLDIII&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_rldii_ui_clk_sync_rst</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_rldii_ui_clk_sync_rst" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;RLDII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;DDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;RLDII&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;RLDIII&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_rldiii_ui_clk_sync_rst</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_rldiii_ui_clk_sync_rst" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;RLDIII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;DDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;RLDII&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;RLDIII&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_ui_clk</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_ui_clk" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;DDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;RLDII&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;RLDIII&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_ui_addn_clk_0</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_ui_addn_clk_0" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_UI_EXTRA_CLOCKS&apos;)) = &quot;TRUE&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MMCM_CLKOUT0_EN&apos;)) = &quot;TRUE&quot; ) and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;DDR2&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_ui_addn_clk_1</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_ui_addn_clk_1" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_UI_EXTRA_CLOCKS&apos;)) = &quot;TRUE&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MMCM_CLKOUT1_EN&apos;)) = &quot;TRUE&quot; ) and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;DDR2&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_ui_addn_clk_2</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_ui_addn_clk_2" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_UI_EXTRA_CLOCKS&apos;)) = &quot;TRUE&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MMCM_CLKOUT2_EN&apos;)) = &quot;TRUE&quot; ) and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;DDR2&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_ui_addn_clk_3</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_ui_addn_clk_3" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_UI_EXTRA_CLOCKS&apos;)) = &quot;TRUE&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MMCM_CLKOUT3_EN&apos;)) = &quot;TRUE&quot; ) and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;DDR2&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_ui_addn_clk_4</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_ui_addn_clk_4" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_UI_EXTRA_CLOCKS&apos;)) = &quot;TRUE&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MMCM_CLKOUT4_EN&apos;)) = &quot;TRUE&quot; ) and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;DDR2&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_s_axi_ctrl_awvalid</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_s_axi_ctrl_awvalid" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_USE_AXI&apos;)) = 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_ECC&apos;)) = &quot;ON&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_s_axi_ctrl_awready</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_s_axi_ctrl_awready" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_USE_AXI&apos;)) = 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_ECC&apos;)) = &quot;ON&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_s_axi_ctrl_awaddr</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_C_S_AXI_CTRL_ADDR_WIDTH&apos;)) )- 1 ">31</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_s_axi_ctrl_awaddr" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_USE_AXI&apos;)) = 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_ECC&apos;)) = &quot;ON&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_s_axi_ctrl_wvalid</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_s_axi_ctrl_wvalid" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_USE_AXI&apos;)) = 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_ECC&apos;)) = &quot;ON&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_s_axi_ctrl_wready</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_s_axi_ctrl_wready" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_USE_AXI&apos;)) = 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_ECC&apos;)) = &quot;ON&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_s_axi_ctrl_wdata</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_C_S_AXI_CTRL_DATA_WIDTH&apos;)) )- 1 ">31</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_s_axi_ctrl_wdata" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_USE_AXI&apos;)) = 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_ECC&apos;)) = &quot;ON&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_s_axi_ctrl_bvalid</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_s_axi_ctrl_bvalid" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_USE_AXI&apos;)) = 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_ECC&apos;)) = &quot;ON&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_s_axi_ctrl_bready</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_s_axi_ctrl_bready" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_USE_AXI&apos;)) = 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_ECC&apos;)) = &quot;ON&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_s_axi_ctrl_bresp</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">1</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_s_axi_ctrl_bresp" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_USE_AXI&apos;)) = 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_ECC&apos;)) = &quot;ON&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_s_axi_ctrl_arvalid</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_s_axi_ctrl_arvalid" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_USE_AXI&apos;)) = 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_ECC&apos;)) = &quot;ON&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_s_axi_ctrl_arready</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_s_axi_ctrl_arready" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_USE_AXI&apos;)) = 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_ECC&apos;)) = &quot;ON&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_s_axi_ctrl_araddr</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_C_S_AXI_CTRL_ADDR_WIDTH&apos;)) )- 1 ">31</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_s_axi_ctrl_araddr" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_USE_AXI&apos;)) = 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_ECC&apos;)) = &quot;ON&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_s_axi_ctrl_rvalid</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_s_axi_ctrl_rvalid" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_USE_AXI&apos;)) = 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_ECC&apos;)) = &quot;ON&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_s_axi_ctrl_rready</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_s_axi_ctrl_rready" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_USE_AXI&apos;)) = 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_ECC&apos;)) = &quot;ON&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_s_axi_ctrl_rdata</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_C_S_AXI_CTRL_DATA_WIDTH&apos;)) )- 1 ">31</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_s_axi_ctrl_rdata" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_USE_AXI&apos;)) = 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_ECC&apos;)) = &quot;ON&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_s_axi_ctrl_rresp</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">1</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_s_axi_ctrl_rresp" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_USE_AXI&apos;)) = 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_ECC&apos;)) = &quot;ON&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_s_axi_awid</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_C_S_AXI_ID_WIDTH&apos;)) )- 1 ">3</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
          <spirit:driver>
            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
          </spirit:driver>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_s_axi_awid" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_s_axi_awaddr</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_C_S_AXI_ADDR_WIDTH&apos;)) )- 1 ">31</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_s_axi_awaddr" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_s_axi_awlen</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">7</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_s_axi_awlen" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_s_axi_awsize</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">2</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_s_axi_awsize" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_s_axi_awburst</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">1</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_s_axi_awburst" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_s_axi_awlock</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
          <spirit:driver>
            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
          </spirit:driver>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_s_axi_awlock" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_s_axi_awcache</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">3</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
          <spirit:driver>
            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
          </spirit:driver>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_s_axi_awcache" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_s_axi_awprot</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">2</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
          <spirit:driver>
            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
          </spirit:driver>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_s_axi_awprot" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_s_axi_awqos</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">3</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
          <spirit:driver>
            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
          </spirit:driver>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_s_axi_awqos" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_s_axi_awvalid</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_s_axi_awvalid" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_s_axi_awready</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_s_axi_awready" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_s_axi_wdata</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_C_S_AXI_DATA_WIDTH&apos;)) )- 1 ">31</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_s_axi_wdata" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_s_axi_wstrb</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_C_S_AXI_DATA_WIDTH&apos;)) / 8 )- 1 ">3</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_s_axi_wstrb" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_s_axi_wlast</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_s_axi_wlast" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_s_axi_wvalid</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_s_axi_wvalid" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_s_axi_wready</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_s_axi_wready" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_s_axi_bready</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_s_axi_bready" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_s_axi_bid</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_C_S_AXI_ID_WIDTH&apos;)) )- 1 ">3</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_s_axi_bid" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_s_axi_bresp</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">1</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_s_axi_bresp" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_s_axi_bvalid</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_s_axi_bvalid" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_s_axi_arid</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_C_S_AXI_ID_WIDTH&apos;)) )- 1 ">3</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
          <spirit:driver>
            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
          </spirit:driver>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_s_axi_arid" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_s_axi_araddr</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_C_S_AXI_ADDR_WIDTH&apos;)) )- 1 ">31</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_s_axi_araddr" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_s_axi_arlen</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">7</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_s_axi_arlen" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_s_axi_arsize</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">2</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_s_axi_arsize" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_s_axi_arburst</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">1</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_s_axi_arburst" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_s_axi_arlock</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
          <spirit:driver>
            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
          </spirit:driver>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_s_axi_arlock" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_s_axi_arcache</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">3</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
          <spirit:driver>
            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
          </spirit:driver>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_s_axi_arcache" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_s_axi_arprot</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">2</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
          <spirit:driver>
            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
          </spirit:driver>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_s_axi_arprot" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_s_axi_arqos</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">3</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
          <spirit:driver>
            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
          </spirit:driver>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_s_axi_arqos" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_s_axi_arvalid</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_s_axi_arvalid" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_s_axi_arready</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_s_axi_arready" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_s_axi_rready</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_s_axi_rready" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_s_axi_rid</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_C_S_AXI_ID_WIDTH&apos;)) )- 1 ">3</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_s_axi_rid" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_s_axi_rdata</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_C_S_AXI_DATA_WIDTH&apos;)) )- 1 ">31</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_s_axi_rdata" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_s_axi_rresp</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">1</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_s_axi_rresp" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_s_axi_rlast</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_s_axi_rlast" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_s_axi_rvalid</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_s_axi_rvalid" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_interrupt</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_interrupt" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_USE_AXI&apos;)) = 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_ECC&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_mmcm_locked</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_mmcm_locked" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_qdriip_cq_p</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_QDRIIP_NUM_DEVICES&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_qdriip_cq_p" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_qdriip_cq_n</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_QDRIIP_NUM_DEVICES&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_qdriip_cq_n" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_qdriip_qvld</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_QDRIIP_NUM_DEVICES&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_qdriip_qvld" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_qdriip_q</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_QDRIIP_DATA_WIDTH&apos;)) )- 1 ">17</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_qdriip_q" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_qdriip_k_p</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_QDRIIP_NUM_DEVICES&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_qdriip_k_p" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_qdriip_k_n</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_QDRIIP_NUM_DEVICES&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_qdriip_k_n" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_qdriip_d</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_QDRIIP_DATA_WIDTH&apos;)) )- 1 ">17</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_qdriip_d" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_qdriip_sa</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_QDRIIP_ADDR_WIDTH&apos;)) )- 1 ">28</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_qdriip_sa" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_qdriip_w_n</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_qdriip_w_n" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_qdriip_r_n</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_qdriip_r_n" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_qdriip_bw_n</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_QDRIIP_BW_WIDTH&apos;)) )- 1 ">7</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_qdriip_bw_n" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_qdriip_dll_off_n</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_qdriip_dll_off_n" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_qdriip_dbg_pi_counter_read_val</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">4</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_qdriip_dbg_pi_counter_read_val" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_QDRIIP_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_qdriip_dbg_win_inc</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_qdriip_dbg_win_inc" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_QDRIIP_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_qdriip_dbg_win_dec</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_qdriip_dbg_win_dec" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_QDRIIP_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_qdriip_dbg_win_active</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_qdriip_dbg_win_active" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_QDRIIP_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_qdriip_dbg_win_current_byte</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">2</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_qdriip_dbg_win_current_byte" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_QDRIIP_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_qdriip_ila0_data</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">254</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_qdriip_ila0_data" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_QDRIIP_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_qdriip_ila0_trig</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">6</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_qdriip_ila0_trig" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_QDRIIP_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_qdriip_ila1_data</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">269</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_qdriip_ila1_data" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_QDRIIP_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_qdriip_ila1_trig</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">14</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_qdriip_ila1_trig" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_QDRIIP_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_qdriip_vio2_async_in</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">198</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_qdriip_vio2_async_in" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_QDRIIP_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_qdriip_vio2_sync_out</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">34</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_qdriip_vio2_sync_out" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_QDRIIP_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_app_wr_cmd0</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_app_wr_cmd0" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_app_wr_addr0</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_QDRIIP_ADDR_WIDTH&apos;)) )- 1 ">28</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_app_wr_addr0" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_app_wr_data0</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_QDRIIP_BURST_LEN&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_app_wr_data0" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_app_wr_bw_n0</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_QDRIIP_BURST_LEN&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_app_wr_bw_n0" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_app_rd_cmd0</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_app_rd_cmd0" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_app_rd_addr0</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_QDRIIP_ADDR_WIDTH&apos;)) )- 1 ">28</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_app_rd_addr0" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_app_rd_valid0</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_app_rd_valid0" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_app_rd_data0</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_QDRIIP_BURST_LEN&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_app_rd_data0" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_app_wr_cmd1</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_app_wr_cmd1" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_app_wr_addr1</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_QDRIIP_ADDR_WIDTH&apos;)) )- 1 ">28</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_app_wr_addr1" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_app_wr_data1</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" (( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_QDRIIP_DATA_WIDTH&apos;)) * 2 ))- 1 ">35</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_app_wr_data1" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_app_wr_bw_n1</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" (( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_QDRIIP_BW_WIDTH&apos;)) * 2 ))- 1 ">15</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_app_wr_bw_n1" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_app_rd_cmd1</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_app_rd_cmd1" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_app_rd_addr1</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_QDRIIP_ADDR_WIDTH&apos;)) )- 1 ">28</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_app_rd_addr1" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_app_rd_valid1</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_app_rd_valid1" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_app_rd_data1</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" (( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_QDRIIP_DATA_WIDTH&apos;)) * 2 ))- 1 ">35</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_app_rd_data1" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_clk</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_clk" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_rst_clk</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_rst_clk" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_qdriip_app_wr_cmd0</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_qdriip_app_wr_cmd0" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_qdriip_app_wr_addr0</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_QDRIIP_ADDR_WIDTH&apos;)) )- 1 ">28</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_qdriip_app_wr_addr0" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_qdriip_app_wr_data0</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_QDRIIP_BURST_LEN&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_qdriip_app_wr_data0" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_qdriip_app_wr_bw_n0</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_QDRIIP_BURST_LEN&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_qdriip_app_wr_bw_n0" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_qdriip_app_rd_cmd0</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_qdriip_app_rd_cmd0" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_qdriip_app_rd_addr0</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_QDRIIP_ADDR_WIDTH&apos;)) )- 1 ">28</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_qdriip_app_rd_addr0" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_qdriip_app_rd_valid0</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_qdriip_app_rd_valid0" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_qdriip_app_rd_data0</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_QDRIIP_BURST_LEN&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_qdriip_app_rd_data0" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_qdriip_app_wr_cmd1</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_qdriip_app_wr_cmd1" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_qdriip_app_wr_addr1</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_QDRIIP_ADDR_WIDTH&apos;)) )- 1 ">28</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_qdriip_app_wr_addr1" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_qdriip_app_wr_data1</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" (( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_QDRIIP_DATA_WIDTH&apos;)) * 2 ))- 1 ">35</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_qdriip_app_wr_data1" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_qdriip_app_wr_bw_n1</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" (( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_QDRIIP_BW_WIDTH&apos;)) * 2 ))- 1 ">15</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_qdriip_app_wr_bw_n1" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_qdriip_app_rd_cmd1</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_qdriip_app_rd_cmd1" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_qdriip_app_rd_addr1</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_QDRIIP_ADDR_WIDTH&apos;)) )- 1 ">28</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_qdriip_app_rd_addr1" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_qdriip_app_rd_valid1</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_qdriip_app_rd_valid1" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_qdriip_app_rd_data1</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" (( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_QDRIIP_DATA_WIDTH&apos;)) * 2 ))- 1 ">35</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_qdriip_app_rd_data1" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_qdriip_clk</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_qdriip_clk" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_qdriip_rst_clk</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_qdriip_rst_clk" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_rldii_qk_p</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_RLDII_QK_WIDTH&apos;)) )- 1 ">7</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_rldii_qk_p" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;RLDII&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_rldii_qk_n</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_RLDII_QK_WIDTH&apos;)) )- 1 ">7</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_rldii_qk_n" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;RLDII&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_rldii_dq</spirit:name>
        <spirit:wire>
          <spirit:direction>inout</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_RLDII_DATA_WIDTH&apos;)) )- 1 ">17</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_rldii_dq" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;RLDII&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_rldii_dm</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_RLDII_DM_WIDTH&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_rldii_dm" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;RLDII&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_rldii_dk_p</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_RLDII_DK_WIDTH&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_rldii_dk_p" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;RLDII&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_rldii_dk_n</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_RLDII_DK_WIDTH&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_rldii_dk_n" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;RLDII&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_rldii_ck_p</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_RLDII_NUM_DEVICES&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_rldii_ck_p" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;RLDII&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_rldii_ck_n</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_RLDII_NUM_DEVICES&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_rldii_ck_n" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;RLDII&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_rldii_cs_n</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_RLDII_NUM_DEVICES&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_rldii_cs_n" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;RLDII&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_rldii_a</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_RLDII_RLD_ADDR_WIDTH&apos;)) )- 1 ">28</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_rldii_a" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;RLDII&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_rldii_ba</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_RLDII_BANK_WIDTH&apos;)) )- 1 ">1</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_rldii_ba" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;RLDII&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_rldii_qvld</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_RLDII_QVLD_WIDTH&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_rldii_qvld" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;RLDII&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_rldii_we_n</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_rldii_we_n" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;RLDII&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_rldii_ref_n</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_rldii_ref_n" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;RLDII&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_rldii_reset_n</spirit:name>
        <spirit:displayName>reset to memory device</spirit:displayName>
        <spirit:description>reset to memory device</spirit:description>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_rldii_reset_n" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;RLDII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;RLDIII&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_rldii_dbg_pi_tap_cnt</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">4</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_rldii_dbg_pi_tap_cnt" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;RLDII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_RLDII_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_rldii_dbg_win_inc</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_rldii_dbg_win_inc" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;RLDII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_RLDII_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_rldii_dbg_win_dec</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_rldii_dbg_win_dec" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;RLDII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_RLDII_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_rldii_dbg_win_active</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_rldii_dbg_win_active" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;RLDII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_RLDII_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_rldii_dbg_win_current_byte</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">2</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_rldii_dbg_win_current_byte" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;RLDII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_RLDII_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_rldii_ila0_data</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">638</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_rldii_ila0_data" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;RLDII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_RLDII_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_rldii_ila0_trig</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">30</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_rldii_ila0_trig" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;RLDII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_RLDII_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_rldii_vio1_async_in</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">254</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_rldii_vio1_async_in" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;RLDII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_RLDII_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_rldii_vio1_async_out</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">62</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_rldii_vio1_async_out" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;RLDII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_RLDII_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_rldii_vio1_sync_out</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">62</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_rldii_vio1_sync_out" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;RLDII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_RLDII_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_rldiii_qk_p</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_RLDIII_QK_WIDTH&apos;)) )- 1 ">7</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_rldiii_qk_p" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;RLDIII&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_rldiii_qk_n</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_RLDIII_QK_WIDTH&apos;)) )- 1 ">7</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_rldiii_qk_n" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;RLDIII&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_rldiii_dq</spirit:name>
        <spirit:wire>
          <spirit:direction>inout</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_RLDIII_DATA_WIDTH&apos;)) )- 1 ">17</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_rldiii_dq" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;RLDIII&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_rldiii_dm</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_RLDIII_DM_WIDTH&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_rldiii_dm" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;RLDIII&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_rldiii_dk_p</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_RLDIII_DK_WIDTH&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_rldiii_dk_p" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;RLDIII&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_rldiii_dk_n</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_RLDIII_DK_WIDTH&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_rldiii_dk_n" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;RLDIII&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_rldiii_ck_p</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_RLDIII_NUM_DEVICES&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_rldiii_ck_p" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;RLDIII&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_rldiii_ck_n</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_RLDIII_NUM_DEVICES&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_rldiii_ck_n" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;RLDIII&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_rldiii_cs_n</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_RLDIII_NUM_DEVICES&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_rldiii_cs_n" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;RLDIII&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_rldiii_a</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_RLDIII_RLD_ADDR_WIDTH&apos;)) )- 1 ">28</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_rldiii_a" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;RLDIII&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_rldiii_ba</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_RLDIII_BANK_WIDTH&apos;)) )- 1 ">1</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_rldiii_ba" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;RLDIII&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_rldiii_qvld</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_RLDIII_QVLD_WIDTH&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_rldiii_qvld" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;RLDIII&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_rldiii_we_n</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_rldiii_we_n" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;RLDIII&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_rldiii_ref_n</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_rldiii_ref_n" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;RLDIII&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_rldiii_reset_n</spirit:name>
        <spirit:displayName>reset to memory device</spirit:displayName>
        <spirit:description>reset to memory device</spirit:description>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_rldiii_reset_n" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;RLDIII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;RLDIII&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_dbg_pi_tap_cnt</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">4</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_dbg_pi_tap_cnt" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;RLDIII&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;RLDII&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_rldiii_dbg_pi_tap_cnt</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">4</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_rldiii_dbg_pi_tap_cnt" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;RLDIII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_RLDIII_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_rldiii_dbg_win_inc</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_rldiii_dbg_win_inc" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;RLDIII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_RLDIII_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_rldiii_dbg_win_dec</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_rldiii_dbg_win_dec" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;RLDIII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_RLDIII_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_rldiii_dbg_win_active</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_rldiii_dbg_win_active" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;RLDIII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_RLDIII_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_rldiii_dbg_win_current_byte</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">2</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_rldiii_dbg_win_current_byte" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;RLDIII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_RLDIII_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_rldiii_ila0_data</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">638</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_rldiii_ila0_data" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;RLDIII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_RLDIII_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_rldiii_ila0_trig</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">30</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_rldiii_ila0_trig" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;RLDIII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_RLDIII_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_rldiii_vio1_async_in</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">254</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_rldiii_vio1_async_in" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;RLDIII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_RLDIII_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_rldiii_vio1_async_out</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">62</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_rldiii_vio1_async_out" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;RLDIII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_RLDIII_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_rldiii_vio1_sync_out</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">62</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_rldiii_vio1_sync_out" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;RLDIII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_RLDIII_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_dbg_win_inc</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_dbg_win_inc" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;RLDIII&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;RLDII&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_dbg_win_dec</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_dbg_win_dec" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;RLDIII&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;RLDII&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_dbg_win_active</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_dbg_win_active" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;RLDIII&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;RLDII&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_dbg_win_current_byte</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">2</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_dbg_win_current_byte" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;RLDIII&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;RLDII&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_dbg_pi_counter_read_val</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">4</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_dbg_pi_counter_read_val" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;DDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_user_cmd_en</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_user_cmd_en" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;RLDII&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;RLDIII&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_user_cmd</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_RLDX_CMD_PER_CLK&apos;)) * 2 )- 1 ">1</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_user_cmd" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;RLDII&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;RLDIII&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_user_addr</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_RLDX_ADDR_WIDTH&apos;)) * spirit:decode(id(&apos;MODELPARAM_VALUE.C1_RLDX_CMD_PER_CLK&apos;)) )- 1 ">28</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_user_addr" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;RLDII&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;RLDIII&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_user_ba</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_RLDX_BANK_WIDTH&apos;)) * spirit:decode(id(&apos;MODELPARAM_VALUE.C1_RLDX_CMD_PER_CLK&apos;)) )- 1 ">1</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_user_ba" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;RLDII&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;RLDIII&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_user_wr_en</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_user_wr_en" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;RLDII&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;RLDIII&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_user_wr_data</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_RLDX_DATA_WIDTH&apos;)) * 2 * spirit:decode(id(&apos;MODELPARAM_VALUE.C1_RLDX_nCK_PER_CLK&apos;)) )- 1 ">35</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_user_wr_data" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;RLDII&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;RLDIII&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_user_wr_dm</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_RLDX_DM_WIDTH&apos;)) * 2 * spirit:decode(id(&apos;MODELPARAM_VALUE.C1_RLDX_nCK_PER_CLK&apos;)) )- 1 ">1</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_user_wr_dm" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;RLDII&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;RLDIII&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_user_afifo_empty</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_user_afifo_empty" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;RLDII&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;RLDIII&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_user_afifo_full</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_user_afifo_full" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;RLDII&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;RLDIII&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_user_afifo_aempty</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_user_afifo_aempty" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;RLDII&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;RLDIII&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_user_afifo_afull</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_user_afifo_afull" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;RLDII&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;RLDIII&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_user_wdfifo_empty</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_user_wdfifo_empty" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;RLDII&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;RLDIII&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_user_wdfifo_full</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_user_wdfifo_full" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;RLDII&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;RLDIII&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_user_wdfifo_aempty</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_user_wdfifo_aempty" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;RLDII&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;RLDIII&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_user_wdfifo_afull</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_user_wdfifo_afull" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;RLDII&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;RLDIII&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_user_rd_valid</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_RLDX_nCK_PER_CLK&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_user_rd_valid" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;RLDII&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;RLDIII&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_mem_ck_lock_complete</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_mem_ck_lock_complete" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;RLDII&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;RLDIII&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_user_rd_data</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_RLDX_DATA_WIDTH&apos;)) * 2 * spirit:decode(id(&apos;MODELPARAM_VALUE.C1_RLDX_nCK_PER_CLK&apos;)) )- 1 ">35</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_user_rd_data" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;RLDII&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;RLDIII&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_rldii_user_cmd_en</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_rldii_user_cmd_en" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;RLDII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_rldii_user_cmd</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_RLDII_CMD_PER_CLK&apos;)) * 2 )- 1 ">1</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_rldii_user_cmd" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;RLDII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_rldii_user_addr</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_RLDII_ADDR_WIDTH&apos;)) * spirit:decode(id(&apos;MODELPARAM_VALUE.C1_RLDII_CMD_PER_CLK&apos;)) )- 1 ">28</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_rldii_user_addr" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;RLDII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_rldii_user_ba</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_RLDII_BANK_WIDTH&apos;)) * spirit:decode(id(&apos;MODELPARAM_VALUE.C1_RLDII_CMD_PER_CLK&apos;)) )- 1 ">1</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_rldii_user_ba" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;RLDII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_rldii_user_wr_en</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_rldii_user_wr_en" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;RLDII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_rldii_user_wr_data</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_RLDII_DATA_WIDTH&apos;)) * 2 * spirit:decode(id(&apos;MODELPARAM_VALUE.C1_RLDII_nCK_PER_CLK&apos;)) )- 1 ">35</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_rldii_user_wr_data" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;RLDII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_rldii_user_wr_dm</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_RLDII_DM_WIDTH&apos;)) * 2 * spirit:decode(id(&apos;MODELPARAM_VALUE.C1_RLDII_nCK_PER_CLK&apos;)) )- 1 ">1</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_rldii_user_wr_dm" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;RLDII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_rldii_user_afifo_empty</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_rldii_user_afifo_empty" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;RLDII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_rldii_user_afifo_full</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_rldii_user_afifo_full" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;RLDII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_rldii_user_afifo_aempty</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_rldii_user_afifo_aempty" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;RLDII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_rldii_user_afifo_afull</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_rldii_user_afifo_afull" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;RLDII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_rldii_user_wdfifo_empty</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_rldii_user_wdfifo_empty" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;RLDII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_rldii_user_wdfifo_full</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_rldii_user_wdfifo_full" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;RLDII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_rldii_user_wdfifo_aempty</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_rldii_user_wdfifo_aempty" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;RLDII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_rldii_user_wdfifo_afull</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_rldii_user_wdfifo_afull" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;RLDII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_rldii_user_rd_valid</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_RLDII_nCK_PER_CLK&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_rldii_user_rd_valid" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;RLDII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_rldii_mem_ck_lock_complete</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_rldii_mem_ck_lock_complete" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;RLDII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_rldii_user_rd_data</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_RLDII_DATA_WIDTH&apos;)) * 2 * spirit:decode(id(&apos;MODELPARAM_VALUE.C1_RLDII_nCK_PER_CLK&apos;)) )- 1 ">35</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_rldii_user_rd_data" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;RLDII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_rldiii_user_cmd_en</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_rldiii_user_cmd_en" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;RLDIII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_rldiii_user_cmd</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_RLDIII_CMD_PER_CLK&apos;)) * 2 )- 1 ">1</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_rldiii_user_cmd" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;RLDIII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_rldiii_user_addr</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_RLDIII_ADDR_WIDTH&apos;)) * spirit:decode(id(&apos;MODELPARAM_VALUE.C1_RLDIII_CMD_PER_CLK&apos;)) )- 1 ">28</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_rldiii_user_addr" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;RLDIII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_rldiii_user_ba</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_RLDIII_BANK_WIDTH&apos;)) * spirit:decode(id(&apos;MODELPARAM_VALUE.C1_RLDIII_CMD_PER_CLK&apos;)) )- 1 ">1</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_rldiii_user_ba" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;RLDIII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_rldiii_user_wr_en</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_rldiii_user_wr_en" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;RLDIII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_rldiii_user_wr_data</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_RLDIII_DATA_WIDTH&apos;)) * 2 * spirit:decode(id(&apos;MODELPARAM_VALUE.C1_RLDIII_nCK_PER_CLK&apos;)) )- 1 ">35</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_rldiii_user_wr_data" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;RLDIII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_rldiii_user_wr_dm</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_RLDIII_DM_WIDTH&apos;)) * 2 * spirit:decode(id(&apos;MODELPARAM_VALUE.C1_RLDIII_nCK_PER_CLK&apos;)) )- 1 ">1</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_rldiii_user_wr_dm" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;RLDIII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_rldiii_user_afifo_empty</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_rldiii_user_afifo_empty" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;RLDIII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_rldiii_user_afifo_full</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_rldiii_user_afifo_full" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;RLDIII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_rldiii_user_afifo_aempty</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_rldiii_user_afifo_aempty" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;RLDIII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_rldiii_user_afifo_afull</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_rldiii_user_afifo_afull" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;RLDIII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_rldiii_user_wdfifo_empty</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_rldiii_user_wdfifo_empty" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;RLDIII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_rldiii_user_wdfifo_full</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_rldiii_user_wdfifo_full" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;RLDIII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_rldiii_user_wdfifo_aempty</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_rldiii_user_wdfifo_aempty" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;RLDIII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_rldiii_user_wdfifo_afull</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_rldiii_user_wdfifo_afull" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;RLDIII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_rldiii_user_rd_valid</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_RLDIII_nCK_PER_CLK&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_rldiii_user_rd_valid" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;RLDIII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_rldiii_mem_ck_lock_complete</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_rldiii_mem_ck_lock_complete" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;RLDIII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_rldiii_user_rd_data</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_RLDIII_DATA_WIDTH&apos;)) * 2 * spirit:decode(id(&apos;MODELPARAM_VALUE.C1_RLDIII_nCK_PER_CLK&apos;)) )- 1 ">35</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_rldiii_user_rd_data" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;RLDIII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_sys_clk_p</spirit:name>
        <spirit:displayName>Clock P</spirit:displayName>
        <spirit:description>Clock P</spirit:description>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_sys_clk_p" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_SYSCLK_TYPE&apos;)) = &quot;DIFF&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_IS_CLK_SHARED&apos;)) = &quot;FALSE&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_sys_clk_n</spirit:name>
        <spirit:displayName>Clock P</spirit:displayName>
        <spirit:description>Clock P</spirit:description>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_sys_clk_n" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_SYSCLK_TYPE&apos;)) = &quot;DIFF&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_IS_CLK_SHARED&apos;)) = &quot;FALSE&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_sys_clk_i</spirit:name>
        <spirit:displayName>Clock P</spirit:displayName>
        <spirit:description>Clock P</spirit:description>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_sys_clk_i" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_SYSCLK_TYPE&apos;)) != &quot;DIFF&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C1_IS_CLK_SHARED&apos;)) = &quot;FALSE&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_init_calib_complete</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_init_calib_complete" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c1_aresetn</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c1_aresetn" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 1 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C1_MEM_TYPE&apos;)) = &quot;DDR2&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_ddr3_dq</spirit:name>
        <spirit:displayName>Data</spirit:displayName>
        <spirit:description>Data</spirit:description>
        <spirit:wire>
          <spirit:direction>inout</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_DDR3_DQ_WIDTH&apos;)) )- 1 ">7</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_ddr3_dq" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;DDR3&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_ddr3_dqs_p</spirit:name>
        <spirit:displayName>Data Strobe</spirit:displayName>
        <spirit:description>Data Strobe</spirit:description>
        <spirit:wire>
          <spirit:direction>inout</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_DDR3_DQS_WIDTH&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_ddr3_dqs_p" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;DDR3&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_ddr3_dqs_n</spirit:name>
        <spirit:displayName>Data Strobe</spirit:displayName>
        <spirit:description>Data Strobe</spirit:description>
        <spirit:wire>
          <spirit:direction>inout</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_DDR3_DQS_WIDTH&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_ddr3_dqs_n" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;DDR3&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_ddr3_addr</spirit:name>
        <spirit:displayName>Address</spirit:displayName>
        <spirit:description>Address</spirit:description>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_DDR3_ROW_WIDTH&apos;)) )- 1 ">13</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_ddr3_addr" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;DDR3&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_ddr3_ba</spirit:name>
        <spirit:displayName>Bank Address</spirit:displayName>
        <spirit:description>Bank Address</spirit:description>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_DDR3_BANK_WIDTH&apos;)) )- 1 ">2</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_ddr3_ba" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;DDR3&quot; and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;DDR2&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_ddr3_ras_n</spirit:name>
        <spirit:displayName>row address strobe</spirit:displayName>
        <spirit:description>row address strobe</spirit:description>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_ddr3_ras_n" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;DDR3&quot; and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;DDR2&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_ddr3_cas_n</spirit:name>
        <spirit:displayName>column address strobe</spirit:displayName>
        <spirit:description>column address strobe</spirit:description>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_ddr3_cas_n" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;DDR3&quot; and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;DDR2&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_ddr3_we_n</spirit:name>
        <spirit:displayName>write enable</spirit:displayName>
        <spirit:description>write enable</spirit:description>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_ddr3_we_n" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;DDR3&quot; and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;DDR2&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_ddr3_reset_n</spirit:name>
        <spirit:displayName>reset to memory device</spirit:displayName>
        <spirit:description>reset to memory device</spirit:description>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_ddr3_reset_n" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;DDR3&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_ddr3_ck_p</spirit:name>
        <spirit:displayName>clock to memory device</spirit:displayName>
        <spirit:description>clock to memory device</spirit:description>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_DDR3_CK_WIDTH&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_ddr3_ck_p" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;DDR3&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_ddr3_ck_n</spirit:name>
        <spirit:displayName>clock to memory device</spirit:displayName>
        <spirit:description>clock to memory device</spirit:description>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_DDR3_CK_WIDTH&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_ddr3_ck_n" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;DDR3&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_ddr3_cke</spirit:name>
        <spirit:displayName>clock enable</spirit:displayName>
        <spirit:description>clock enable</spirit:description>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_DDR3_CKE_WIDTH&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_ddr3_cke" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;DDR3&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_ddr3_cs_n</spirit:name>
        <spirit:displayName>chip select</spirit:displayName>
        <spirit:description>chip select</spirit:description>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_DDR3_CS_WIDTH&apos;)) * spirit:decode(id(&apos;MODELPARAM_VALUE.C2_DDR3_nCS_PER_RANK&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_ddr3_cs_n" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_DDR3_USE_CS_PORT&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_ddr3_dm</spirit:name>
        <spirit:displayName>data mask</spirit:displayName>
        <spirit:description>data mask</spirit:description>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_DDR3_DM_WIDTH&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_ddr3_dm" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_DDR3_USE_DM_PORT&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_ddr3_odt</spirit:name>
        <spirit:displayName>on die termination</spirit:displayName>
        <spirit:description>on die termination</spirit:description>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_DDR3_ODT_WIDTH&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_ddr3_odt" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;DDR3&quot; and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;DDR2&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_DDR3_USE_ODT_PORT&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_ddr3_parity</spirit:name>
        <spirit:displayName>parity bit</spirit:displayName>
        <spirit:description>parity bit</spirit:description>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_ddr3_parity" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_DDR3_REG_CTRL&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_ddr3_dbg_pi_counter_read_val</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">4</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_ddr3_dbg_pi_counter_read_val" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_DDR3_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_ddr3_dbg_byte_sel</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_DDR3_DQS_CNT_WIDTH&apos;)) + 1 )- 1 ">1</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_ddr3_dbg_byte_sel" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_DDR3_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_ddr3_dbg_sel_pi_incdec</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_ddr3_dbg_sel_pi_incdec" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_DDR3_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_ddr3_dbg_pi_f_inc</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_ddr3_dbg_pi_f_inc" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_DDR3_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_ddr3_dbg_pi_f_dec</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_ddr3_dbg_pi_f_dec" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_DDR3_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_ddr3_dbg_sel_po_incdec</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_ddr3_dbg_sel_po_incdec" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_DDR3_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_ddr3_dbg_po_f_inc</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_ddr3_dbg_po_f_inc" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_DDR3_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_ddr3_dbg_po_f_stg23_sel</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_ddr3_dbg_po_f_stg23_sel" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_DDR3_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_ddr3_dbg_po_f_dec</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_ddr3_dbg_po_f_dec" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_DDR3_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_ddr3_dbg_po_counter_read_val</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">7</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_ddr3_dbg_po_counter_read_val" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_DDR3_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_ddr3_ila_wrpath</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">254</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_ddr3_ila_wrpath" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_DDR3_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_ddr3_ila_rdpath</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">1022</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_ddr3_ila_rdpath" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_DDR3_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_ddr3_ila_basic</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">126</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_ddr3_ila_basic" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_DDR3_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_ddr3_vio_sync_out</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">34</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_ddr3_vio_sync_out" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_DDR3_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_ddr2_dq</spirit:name>
        <spirit:displayName>Data</spirit:displayName>
        <spirit:description>Data</spirit:description>
        <spirit:wire>
          <spirit:direction>inout</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_DDR2_DQ_WIDTH&apos;)) )- 1 ">7</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_ddr2_dq" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;DDR2&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_ddr2_dqs_p</spirit:name>
        <spirit:displayName>Data Strobe</spirit:displayName>
        <spirit:description>Data Strobe</spirit:description>
        <spirit:wire>
          <spirit:direction>inout</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_DDR2_DQS_WIDTH&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_ddr2_dqs_p" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;DDR2&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_ddr2_dqs_n</spirit:name>
        <spirit:displayName>Data Strobe</spirit:displayName>
        <spirit:description>Data Strobe</spirit:description>
        <spirit:wire>
          <spirit:direction>inout</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_DDR2_DQS_WIDTH&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_ddr2_dqs_n" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;DDR2&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_ddr2_addr</spirit:name>
        <spirit:displayName>Address</spirit:displayName>
        <spirit:description>Address</spirit:description>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_DDR2_ROW_WIDTH&apos;)) )- 1 ">13</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_ddr2_addr" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;DDR2&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_ddr2_ba</spirit:name>
        <spirit:displayName>Bank Address</spirit:displayName>
        <spirit:description>Bank Address</spirit:description>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_DDR2_BANK_WIDTH&apos;)) )- 1 ">2</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_ddr2_ba" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;DDR2&quot; and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;DDR2&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_ddr2_ras_n</spirit:name>
        <spirit:displayName>row address strobe</spirit:displayName>
        <spirit:description>row address strobe</spirit:description>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_ddr2_ras_n" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;DDR2&quot; and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;DDR2&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_ddr2_cas_n</spirit:name>
        <spirit:displayName>column address strobe</spirit:displayName>
        <spirit:description>column address strobe</spirit:description>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_ddr2_cas_n" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;DDR2&quot; and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;DDR2&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_ddr2_we_n</spirit:name>
        <spirit:displayName>write enable</spirit:displayName>
        <spirit:description>write enable</spirit:description>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_ddr2_we_n" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;DDR2&quot; and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;DDR2&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_ddr2_reset_n</spirit:name>
        <spirit:displayName>reset to memory device</spirit:displayName>
        <spirit:description>reset to memory device</spirit:description>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_ddr2_reset_n" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;DDR3&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_ddr2_ck_p</spirit:name>
        <spirit:displayName>clock to memory device</spirit:displayName>
        <spirit:description>clock to memory device</spirit:description>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_DDR2_CK_WIDTH&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_ddr2_ck_p" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;DDR2&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_ddr2_ck_n</spirit:name>
        <spirit:displayName>clock to memory device</spirit:displayName>
        <spirit:description>clock to memory device</spirit:description>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_DDR2_CK_WIDTH&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_ddr2_ck_n" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;DDR2&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_ddr2_cke</spirit:name>
        <spirit:displayName>clock enable</spirit:displayName>
        <spirit:description>clock enable</spirit:description>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_DDR2_CKE_WIDTH&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_ddr2_cke" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;DDR2&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_ddr2_cs_n</spirit:name>
        <spirit:displayName>chip select</spirit:displayName>
        <spirit:description>chip select</spirit:description>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_DDR2_CS_WIDTH&apos;)) * spirit:decode(id(&apos;MODELPARAM_VALUE.C2_DDR2_nCS_PER_RANK&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_ddr2_cs_n" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_DDR2_USE_CS_PORT&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_ddr2_dm</spirit:name>
        <spirit:displayName>data mask</spirit:displayName>
        <spirit:description>data mask</spirit:description>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_DDR2_DM_WIDTH&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_ddr2_dm" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_DDR2_USE_DM_PORT&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_ddr2_odt</spirit:name>
        <spirit:displayName>on die termination</spirit:displayName>
        <spirit:description>on die termination</spirit:description>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_DDR2_ODT_WIDTH&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_ddr2_odt" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;DDR2&quot; and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;DDR2&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_DDR2_USE_ODT_PORT&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_ddr2_parity</spirit:name>
        <spirit:displayName>parity bit</spirit:displayName>
        <spirit:description>parity bit</spirit:description>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_ddr2_parity" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_DDR2_REG_CTRL&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_ddr2_dbg_pi_counter_read_val</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">4</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_ddr2_dbg_pi_counter_read_val" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_DDR2_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_ddr2_dbg_byte_sel</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_DDR2_DQS_CNT_WIDTH&apos;)) + 1 )- 1 ">1</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_ddr2_dbg_byte_sel" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_DDR2_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_ddr2_dbg_sel_pi_incdec</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_ddr2_dbg_sel_pi_incdec" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_DDR2_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_ddr2_dbg_pi_f_inc</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_ddr2_dbg_pi_f_inc" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_DDR2_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_ddr2_dbg_pi_f_dec</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_ddr2_dbg_pi_f_dec" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_DDR2_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_ddr2_dbg_sel_po_incdec</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_ddr2_dbg_sel_po_incdec" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_DDR2_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_ddr2_dbg_po_f_inc</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_ddr2_dbg_po_f_inc" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_DDR2_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_ddr2_dbg_po_f_stg23_sel</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_ddr2_dbg_po_f_stg23_sel" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_DDR2_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_ddr2_dbg_po_f_dec</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_ddr2_dbg_po_f_dec" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_DDR2_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_ddr2_dbg_po_counter_read_val</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">7</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_ddr2_dbg_po_counter_read_val" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_DDR2_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_ddr2_ila_wrpath</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">254</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_ddr2_ila_wrpath" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_DDR2_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_ddr2_ila_rdpath</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">1022</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_ddr2_ila_rdpath" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_DDR2_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_ddr2_ila_basic</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">126</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_ddr2_ila_basic" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_DDR2_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_ddr2_vio_sync_out</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">34</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_ddr2_vio_sync_out" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_DDR2_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_lpddr2_dq</spirit:name>
        <spirit:displayName>Data</spirit:displayName>
        <spirit:description>Data</spirit:description>
        <spirit:wire>
          <spirit:direction>inout</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_LPDDR2_DQ_WIDTH&apos;)) )- 1 ">7</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_lpddr2_dq" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_lpddr2_dqs_p</spirit:name>
        <spirit:displayName>Data Strobe</spirit:displayName>
        <spirit:description>Data Strobe</spirit:description>
        <spirit:wire>
          <spirit:direction>inout</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_LPDDR2_DQS_WIDTH&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_lpddr2_dqs_p" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_lpddr2_dqs_n</spirit:name>
        <spirit:displayName>Data Strobe</spirit:displayName>
        <spirit:description>Data Strobe</spirit:description>
        <spirit:wire>
          <spirit:direction>inout</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_LPDDR2_DQS_WIDTH&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_lpddr2_dqs_n" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_lpddr2_ca</spirit:name>
        <spirit:displayName>Address</spirit:displayName>
        <spirit:description>Address</spirit:description>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">9</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_lpddr2_ca" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_lpddr2_ck_p</spirit:name>
        <spirit:displayName>clock to memory device</spirit:displayName>
        <spirit:description>clock to memory device</spirit:description>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_LPDDR2_CK_WIDTH&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_lpddr2_ck_p" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_lpddr2_ck_n</spirit:name>
        <spirit:displayName>clock to memory device</spirit:displayName>
        <spirit:description>clock to memory device</spirit:description>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_LPDDR2_CK_WIDTH&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_lpddr2_ck_n" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_lpddr2_cke</spirit:name>
        <spirit:displayName>clock enable</spirit:displayName>
        <spirit:description>clock enable</spirit:description>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_LPDDR2_CKE_WIDTH&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_lpddr2_cke" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_lpddr2_cs_n</spirit:name>
        <spirit:displayName>chip select</spirit:displayName>
        <spirit:description>chip select</spirit:description>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_LPDDR2_CS_WIDTH&apos;)) * spirit:decode(id(&apos;MODELPARAM_VALUE.C2_LPDDR2_nCS_PER_RANK&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_lpddr2_cs_n" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_LPDDR2_USE_CS_PORT&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_lpddr2_dm</spirit:name>
        <spirit:displayName>data mask</spirit:displayName>
        <spirit:description>data mask</spirit:description>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_LPDDR2_DM_WIDTH&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_lpddr2_dm" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_LPDDR2_USE_DM_PORT&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_lpddr2_parity</spirit:name>
        <spirit:displayName>parity bit</spirit:displayName>
        <spirit:description>parity bit</spirit:description>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_lpddr2_parity" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_LPDDR2_REG_CTRL&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_lpddr2_dbg_pi_counter_read_val</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">4</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_lpddr2_dbg_pi_counter_read_val" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_LPDDR2_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_lpddr2_dbg_byte_sel</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_LPDDR2_DQS_CNT_WIDTH&apos;)) + 1 )- 1 ">1</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_lpddr2_dbg_byte_sel" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_LPDDR2_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_lpddr2_dbg_sel_pi_incdec</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_lpddr2_dbg_sel_pi_incdec" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_LPDDR2_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_lpddr2_dbg_pi_f_inc</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_lpddr2_dbg_pi_f_inc" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_LPDDR2_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_lpddr2_dbg_pi_f_dec</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_lpddr2_dbg_pi_f_dec" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_LPDDR2_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_lpddr2_dbg_sel_po_incdec</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_lpddr2_dbg_sel_po_incdec" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_LPDDR2_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_lpddr2_dbg_po_f_inc</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_lpddr2_dbg_po_f_inc" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_LPDDR2_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_lpddr2_dbg_po_f_stg23_sel</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_lpddr2_dbg_po_f_stg23_sel" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_LPDDR2_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_lpddr2_dbg_po_f_dec</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_lpddr2_dbg_po_f_dec" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_LPDDR2_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_lpddr2_dbg_po_counter_read_val</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">7</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_lpddr2_dbg_po_counter_read_val" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_LPDDR2_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_lpddr2_ila_wrpath</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">254</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_lpddr2_ila_wrpath" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_LPDDR2_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_lpddr2_ila_rdpath</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">1022</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_lpddr2_ila_rdpath" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_LPDDR2_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_lpddr2_ila_basic</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">126</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_lpddr2_ila_basic" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_LPDDR2_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_lpddr2_vio_sync_out</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">34</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_lpddr2_vio_sync_out" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_LPDDR2_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_dbg_byte_sel</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_DQS_CNT_WIDTH&apos;)) + 1 )- 1 ">1</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_dbg_byte_sel" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;DDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_dbg_sel_pi_incdec</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_dbg_sel_pi_incdec" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;DDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_dbg_pi_f_inc</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_dbg_pi_f_inc" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;DDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_dbg_pi_f_dec</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_dbg_pi_f_dec" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;DDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_dbg_sel_po_incdec</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_dbg_sel_po_incdec" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;DDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_dbg_po_f_inc</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_dbg_po_f_inc" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;DDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_dbg_po_f_stg23_sel</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_dbg_po_f_stg23_sel" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;DDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_dbg_po_f_dec</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_dbg_po_f_dec" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;DDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_dbg_po_counter_read_val</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">7</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_dbg_po_counter_read_val" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;DDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_app_addr</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_DDRX_ADDR_WIDTH&apos;)) )- 1 ">7</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_app_addr" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;DDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_app_cmd</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">2</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_app_cmd" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;DDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_app_en</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_app_en" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;DDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_app_wdf_data</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_DDRX_nCK_PER_CLK&apos;)) * 2 * spirit:decode(id(&apos;MODELPARAM_VALUE.C2_DDRX_DATA_WIDTH&apos;)) )- 1 ">31</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_app_wdf_data" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;DDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_app_wdf_end</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_app_wdf_end" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;DDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_app_wdf_mask</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_DDRX_nCK_PER_CLK&apos;)) * 2 * spirit:decode(id(&apos;MODELPARAM_VALUE.C2_DDRX_DATA_WIDTH&apos;)) / 8 )- 1 ">3</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_app_wdf_mask" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;DDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_app_wdf_wren</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_app_wdf_wren" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;DDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_app_correct_en_i</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_app_correct_en_i" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;DDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_ECC&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_app_rd_data</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_DDRX_nCK_PER_CLK&apos;)) * 2 * spirit:decode(id(&apos;MODELPARAM_VALUE.C2_DDRX_DATA_WIDTH&apos;)) )- 1 ">31</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_app_rd_data" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;DDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_app_rd_data_end</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_app_rd_data_end" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;DDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_app_rd_data_valid</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_app_rd_data_valid" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;DDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_app_rdy</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_app_rdy" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;DDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_app_wdf_rdy</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_app_wdf_rdy" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;DDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_app_sr_req</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_app_sr_req" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;DDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_app_sr_active</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_app_sr_active" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;DDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_app_ref_req</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_app_ref_req" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;DDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_app_ref_ack</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_app_ref_ack" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;DDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_app_zq_req</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_app_zq_req" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;DDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_app_zq_ack</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_app_zq_ack" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;DDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_app_raw_not_ecc</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( 2 * spirit:decode(id(&apos;MODELPARAM_VALUE.C2_DDRX_nCK_PER_CLK&apos;)) )- 1 ">3</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_app_raw_not_ecc" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;DDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_ECC&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_app_ecc_multiple_err</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( 2 * spirit:decode(id(&apos;MODELPARAM_VALUE.C2_DDRX_nCK_PER_CLK&apos;)) )- 1 ">3</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_app_ecc_multiple_err" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;DDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_ECC&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_ddr3_app_addr</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_DDR3_ADDR_WIDTH&apos;)) )- 1 ">7</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_ddr3_app_addr" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_ddr3_app_cmd</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">2</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_ddr3_app_cmd" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_ddr3_app_en</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_ddr3_app_en" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_ddr3_app_wdf_data</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_DDR3_nCK_PER_CLK&apos;)) * 2 * spirit:decode(id(&apos;MODELPARAM_VALUE.C2_DDR3_DATA_WIDTH&apos;)) )- 1 ">31</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_ddr3_app_wdf_data" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_ddr3_app_wdf_end</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_ddr3_app_wdf_end" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_ddr3_app_wdf_mask</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_DDR3_nCK_PER_CLK&apos;)) * 2 * spirit:decode(id(&apos;MODELPARAM_VALUE.C2_DDR3_DATA_WIDTH&apos;)) / 8 )- 1 ">3</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_ddr3_app_wdf_mask" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_ddr3_app_wdf_wren</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_ddr3_app_wdf_wren" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_ddr3_app_correct_en_i</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_ddr3_app_correct_en_i" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_ECC&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_ddr3_app_rd_data</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_DDR3_nCK_PER_CLK&apos;)) * 2 * spirit:decode(id(&apos;MODELPARAM_VALUE.C2_DDR3_DATA_WIDTH&apos;)) )- 1 ">31</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_ddr3_app_rd_data" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_ddr3_app_rd_data_end</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_ddr3_app_rd_data_end" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_ddr3_app_rd_data_valid</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_ddr3_app_rd_data_valid" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_ddr3_app_rdy</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_ddr3_app_rdy" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_ddr3_app_wdf_rdy</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_ddr3_app_wdf_rdy" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_ddr3_app_sr_req</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_ddr3_app_sr_req" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_ddr3_app_sr_active</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_ddr3_app_sr_active" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_ddr3_app_ref_req</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_ddr3_app_ref_req" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_ddr3_app_ref_ack</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_ddr3_app_ref_ack" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_ddr3_app_zq_req</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_ddr3_app_zq_req" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_ddr3_app_zq_ack</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_ddr3_app_zq_ack" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_ddr3_app_raw_not_ecc</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( 2 * spirit:decode(id(&apos;MODELPARAM_VALUE.C2_DDR3_nCK_PER_CLK&apos;)) )- 1 ">3</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_ddr3_app_raw_not_ecc" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_ECC&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_ddr3_app_ecc_multiple_err</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( 2 * spirit:decode(id(&apos;MODELPARAM_VALUE.C2_DDR3_nCK_PER_CLK&apos;)) )- 1 ">3</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_ddr3_app_ecc_multiple_err" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_ECC&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_ddr2_app_addr</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_DDR2_ADDR_WIDTH&apos;)) )- 1 ">7</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_ddr2_app_addr" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_ddr2_app_cmd</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">2</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_ddr2_app_cmd" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_ddr2_app_en</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_ddr2_app_en" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_ddr2_app_wdf_data</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_DDR2_nCK_PER_CLK&apos;)) * 2 * spirit:decode(id(&apos;MODELPARAM_VALUE.C2_DDR2_DATA_WIDTH&apos;)) )- 1 ">31</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_ddr2_app_wdf_data" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_ddr2_app_wdf_end</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_ddr2_app_wdf_end" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_ddr2_app_wdf_mask</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_DDR2_nCK_PER_CLK&apos;)) * 2 * spirit:decode(id(&apos;MODELPARAM_VALUE.C2_DDR2_DATA_WIDTH&apos;)) / 8 )- 1 ">3</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_ddr2_app_wdf_mask" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_ddr2_app_wdf_wren</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_ddr2_app_wdf_wren" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_ddr2_app_correct_en_i</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_ddr2_app_correct_en_i" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_ECC&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_ddr2_app_rd_data</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_DDR2_nCK_PER_CLK&apos;)) * 2 * spirit:decode(id(&apos;MODELPARAM_VALUE.C2_DDR2_DATA_WIDTH&apos;)) )- 1 ">31</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_ddr2_app_rd_data" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_ddr2_app_rd_data_end</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_ddr2_app_rd_data_end" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_ddr2_app_rd_data_valid</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_ddr2_app_rd_data_valid" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_ddr2_app_rdy</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_ddr2_app_rdy" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_ddr2_app_wdf_rdy</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_ddr2_app_wdf_rdy" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_ddr2_app_sr_req</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_ddr2_app_sr_req" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_ddr2_app_sr_active</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_ddr2_app_sr_active" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_ddr2_app_ref_req</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_ddr2_app_ref_req" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_ddr2_app_ref_ack</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_ddr2_app_ref_ack" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_ddr2_app_zq_req</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_ddr2_app_zq_req" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_ddr2_app_zq_ack</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_ddr2_app_zq_ack" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_ddr2_app_raw_not_ecc</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( 2 * spirit:decode(id(&apos;MODELPARAM_VALUE.C2_DDR2_nCK_PER_CLK&apos;)) )- 1 ">3</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_ddr2_app_raw_not_ecc" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_ECC&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_ddr2_app_ecc_multiple_err</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( 2 * spirit:decode(id(&apos;MODELPARAM_VALUE.C2_DDR2_nCK_PER_CLK&apos;)) )- 1 ">3</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_ddr2_app_ecc_multiple_err" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_ECC&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_lpddr2_app_addr</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_LPDDR2_ADDR_WIDTH&apos;)) )- 1 ">7</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_lpddr2_app_addr" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_lpddr2_app_cmd</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">2</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_lpddr2_app_cmd" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_lpddr2_app_en</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_lpddr2_app_en" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_lpddr2_app_wdf_data</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_LPDDR2_nCK_PER_CLK&apos;)) * 2 * spirit:decode(id(&apos;MODELPARAM_VALUE.C2_LPDDR2_DATA_WIDTH&apos;)) )- 1 ">31</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_lpddr2_app_wdf_data" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_lpddr2_app_wdf_end</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_lpddr2_app_wdf_end" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_lpddr2_app_wdf_mask</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_LPDDR2_nCK_PER_CLK&apos;)) * 2 * spirit:decode(id(&apos;MODELPARAM_VALUE.C2_LPDDR2_DATA_WIDTH&apos;)) / 8 )- 1 ">3</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_lpddr2_app_wdf_mask" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_lpddr2_app_wdf_wren</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_lpddr2_app_wdf_wren" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_lpddr2_app_correct_en_i</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_lpddr2_app_correct_en_i" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_ECC&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_lpddr2_app_rd_data</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_LPDDR2_nCK_PER_CLK&apos;)) * 2 * spirit:decode(id(&apos;MODELPARAM_VALUE.C2_LPDDR2_DATA_WIDTH&apos;)) )- 1 ">31</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_lpddr2_app_rd_data" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_lpddr2_app_rd_data_end</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_lpddr2_app_rd_data_end" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_lpddr2_app_rd_data_valid</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_lpddr2_app_rd_data_valid" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_lpddr2_app_rdy</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_lpddr2_app_rdy" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_lpddr2_app_wdf_rdy</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_lpddr2_app_wdf_rdy" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_lpddr2_app_sr_req</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_lpddr2_app_sr_req" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_lpddr2_app_sr_active</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_lpddr2_app_sr_active" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_lpddr2_app_ref_req</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_lpddr2_app_ref_req" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_lpddr2_app_ref_ack</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_lpddr2_app_ref_ack" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_lpddr2_app_zq_req</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_lpddr2_app_zq_req" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_lpddr2_app_zq_ack</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_lpddr2_app_zq_ack" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_lpddr2_app_raw_not_ecc</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( 2 * spirit:decode(id(&apos;MODELPARAM_VALUE.C2_LPDDR2_nCK_PER_CLK&apos;)) )- 1 ">3</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_lpddr2_app_raw_not_ecc" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_ECC&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_lpddr2_app_ecc_multiple_err</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( 2 * spirit:decode(id(&apos;MODELPARAM_VALUE.C2_LPDDR2_nCK_PER_CLK&apos;)) )- 1 ">3</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_lpddr2_app_ecc_multiple_err" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_ECC&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_ui_clk_sync_rst</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_ui_clk_sync_rst" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;DDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;RLDII&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;RLDIII&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_ddr3_ui_clk_sync_rst</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_ddr3_ui_clk_sync_rst" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;DDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;RLDII&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;RLDIII&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_ddr2_ui_clk_sync_rst</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_ddr2_ui_clk_sync_rst" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;DDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;RLDII&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;RLDIII&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_lpddr2_ui_clk_sync_rst</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_lpddr2_ui_clk_sync_rst" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;DDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;RLDII&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;RLDIII&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_qdriip_ui_clk_sync_rst</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_qdriip_ui_clk_sync_rst" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;DDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;RLDII&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;RLDIII&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_rldii_ui_clk_sync_rst</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_rldii_ui_clk_sync_rst" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;RLDII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;DDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;RLDII&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;RLDIII&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_rldiii_ui_clk_sync_rst</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_rldiii_ui_clk_sync_rst" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;RLDIII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;DDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;RLDII&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;RLDIII&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_ui_clk</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_ui_clk" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;DDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;RLDII&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;RLDIII&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_ui_addn_clk_0</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_ui_addn_clk_0" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_UI_EXTRA_CLOCKS&apos;)) = &quot;TRUE&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MMCM_CLKOUT0_EN&apos;)) = &quot;TRUE&quot; ) and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;DDR2&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_ui_addn_clk_1</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_ui_addn_clk_1" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_UI_EXTRA_CLOCKS&apos;)) = &quot;TRUE&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MMCM_CLKOUT1_EN&apos;)) = &quot;TRUE&quot; ) and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;DDR2&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_ui_addn_clk_2</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_ui_addn_clk_2" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_UI_EXTRA_CLOCKS&apos;)) = &quot;TRUE&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MMCM_CLKOUT2_EN&apos;)) = &quot;TRUE&quot; ) and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;DDR2&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_ui_addn_clk_3</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_ui_addn_clk_3" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_UI_EXTRA_CLOCKS&apos;)) = &quot;TRUE&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MMCM_CLKOUT3_EN&apos;)) = &quot;TRUE&quot; ) and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;DDR2&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_ui_addn_clk_4</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_ui_addn_clk_4" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_UI_EXTRA_CLOCKS&apos;)) = &quot;TRUE&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MMCM_CLKOUT4_EN&apos;)) = &quot;TRUE&quot; ) and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;DDR2&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_s_axi_ctrl_awvalid</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_s_axi_ctrl_awvalid" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_USE_AXI&apos;)) = 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_ECC&apos;)) = &quot;ON&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_s_axi_ctrl_awready</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_s_axi_ctrl_awready" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_USE_AXI&apos;)) = 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_ECC&apos;)) = &quot;ON&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_s_axi_ctrl_awaddr</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_C_S_AXI_CTRL_ADDR_WIDTH&apos;)) )- 1 ">31</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_s_axi_ctrl_awaddr" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_USE_AXI&apos;)) = 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_ECC&apos;)) = &quot;ON&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_s_axi_ctrl_wvalid</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_s_axi_ctrl_wvalid" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_USE_AXI&apos;)) = 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_ECC&apos;)) = &quot;ON&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_s_axi_ctrl_wready</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_s_axi_ctrl_wready" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_USE_AXI&apos;)) = 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_ECC&apos;)) = &quot;ON&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_s_axi_ctrl_wdata</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_C_S_AXI_CTRL_DATA_WIDTH&apos;)) )- 1 ">31</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_s_axi_ctrl_wdata" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_USE_AXI&apos;)) = 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_ECC&apos;)) = &quot;ON&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_s_axi_ctrl_bvalid</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_s_axi_ctrl_bvalid" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_USE_AXI&apos;)) = 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_ECC&apos;)) = &quot;ON&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_s_axi_ctrl_bready</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_s_axi_ctrl_bready" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_USE_AXI&apos;)) = 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_ECC&apos;)) = &quot;ON&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_s_axi_ctrl_bresp</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">1</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_s_axi_ctrl_bresp" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_USE_AXI&apos;)) = 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_ECC&apos;)) = &quot;ON&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_s_axi_ctrl_arvalid</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_s_axi_ctrl_arvalid" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_USE_AXI&apos;)) = 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_ECC&apos;)) = &quot;ON&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_s_axi_ctrl_arready</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_s_axi_ctrl_arready" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_USE_AXI&apos;)) = 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_ECC&apos;)) = &quot;ON&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_s_axi_ctrl_araddr</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_C_S_AXI_CTRL_ADDR_WIDTH&apos;)) )- 1 ">31</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_s_axi_ctrl_araddr" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_USE_AXI&apos;)) = 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_ECC&apos;)) = &quot;ON&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_s_axi_ctrl_rvalid</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_s_axi_ctrl_rvalid" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_USE_AXI&apos;)) = 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_ECC&apos;)) = &quot;ON&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_s_axi_ctrl_rready</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_s_axi_ctrl_rready" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_USE_AXI&apos;)) = 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_ECC&apos;)) = &quot;ON&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_s_axi_ctrl_rdata</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_C_S_AXI_CTRL_DATA_WIDTH&apos;)) )- 1 ">31</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_s_axi_ctrl_rdata" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_USE_AXI&apos;)) = 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_ECC&apos;)) = &quot;ON&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_s_axi_ctrl_rresp</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">1</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_s_axi_ctrl_rresp" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_USE_AXI&apos;)) = 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_ECC&apos;)) = &quot;ON&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_s_axi_awid</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_C_S_AXI_ID_WIDTH&apos;)) )- 1 ">3</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
          <spirit:driver>
            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
          </spirit:driver>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_s_axi_awid" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_s_axi_awaddr</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_C_S_AXI_ADDR_WIDTH&apos;)) )- 1 ">31</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_s_axi_awaddr" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_s_axi_awlen</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">7</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_s_axi_awlen" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_s_axi_awsize</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">2</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_s_axi_awsize" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_s_axi_awburst</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">1</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_s_axi_awburst" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_s_axi_awlock</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
          <spirit:driver>
            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
          </spirit:driver>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_s_axi_awlock" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_s_axi_awcache</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">3</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
          <spirit:driver>
            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
          </spirit:driver>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_s_axi_awcache" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_s_axi_awprot</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">2</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
          <spirit:driver>
            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
          </spirit:driver>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_s_axi_awprot" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_s_axi_awqos</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">3</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
          <spirit:driver>
            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
          </spirit:driver>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_s_axi_awqos" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_s_axi_awvalid</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_s_axi_awvalid" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_s_axi_awready</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_s_axi_awready" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_s_axi_wdata</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_C_S_AXI_DATA_WIDTH&apos;)) )- 1 ">31</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_s_axi_wdata" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_s_axi_wstrb</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_C_S_AXI_DATA_WIDTH&apos;)) / 8 )- 1 ">3</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_s_axi_wstrb" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_s_axi_wlast</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_s_axi_wlast" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_s_axi_wvalid</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_s_axi_wvalid" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_s_axi_wready</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_s_axi_wready" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_s_axi_bready</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_s_axi_bready" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_s_axi_bid</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_C_S_AXI_ID_WIDTH&apos;)) )- 1 ">3</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_s_axi_bid" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_s_axi_bresp</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">1</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_s_axi_bresp" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_s_axi_bvalid</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_s_axi_bvalid" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_s_axi_arid</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_C_S_AXI_ID_WIDTH&apos;)) )- 1 ">3</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
          <spirit:driver>
            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
          </spirit:driver>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_s_axi_arid" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_s_axi_araddr</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_C_S_AXI_ADDR_WIDTH&apos;)) )- 1 ">31</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_s_axi_araddr" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_s_axi_arlen</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">7</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_s_axi_arlen" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_s_axi_arsize</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">2</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_s_axi_arsize" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_s_axi_arburst</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">1</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_s_axi_arburst" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_s_axi_arlock</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
          <spirit:driver>
            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
          </spirit:driver>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_s_axi_arlock" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_s_axi_arcache</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">3</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
          <spirit:driver>
            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
          </spirit:driver>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_s_axi_arcache" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_s_axi_arprot</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">2</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
          <spirit:driver>
            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
          </spirit:driver>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_s_axi_arprot" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_s_axi_arqos</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">3</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
          <spirit:driver>
            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
          </spirit:driver>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_s_axi_arqos" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_s_axi_arvalid</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_s_axi_arvalid" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_s_axi_arready</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_s_axi_arready" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_s_axi_rready</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_s_axi_rready" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_s_axi_rid</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_C_S_AXI_ID_WIDTH&apos;)) )- 1 ">3</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_s_axi_rid" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_s_axi_rdata</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_C_S_AXI_DATA_WIDTH&apos;)) )- 1 ">31</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_s_axi_rdata" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_s_axi_rresp</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">1</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_s_axi_rresp" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_s_axi_rlast</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_s_axi_rlast" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_s_axi_rvalid</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_s_axi_rvalid" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_interrupt</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_interrupt" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_USE_AXI&apos;)) = 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_ECC&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_mmcm_locked</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_mmcm_locked" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_qdriip_cq_p</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_QDRIIP_NUM_DEVICES&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_qdriip_cq_p" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_qdriip_cq_n</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_QDRIIP_NUM_DEVICES&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_qdriip_cq_n" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_qdriip_qvld</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_QDRIIP_NUM_DEVICES&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_qdriip_qvld" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_qdriip_q</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_QDRIIP_DATA_WIDTH&apos;)) )- 1 ">17</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_qdriip_q" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_qdriip_k_p</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_QDRIIP_NUM_DEVICES&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_qdriip_k_p" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_qdriip_k_n</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_QDRIIP_NUM_DEVICES&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_qdriip_k_n" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_qdriip_d</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_QDRIIP_DATA_WIDTH&apos;)) )- 1 ">17</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_qdriip_d" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_qdriip_sa</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_QDRIIP_ADDR_WIDTH&apos;)) )- 1 ">28</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_qdriip_sa" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_qdriip_w_n</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_qdriip_w_n" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_qdriip_r_n</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_qdriip_r_n" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_qdriip_bw_n</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_QDRIIP_BW_WIDTH&apos;)) )- 1 ">7</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_qdriip_bw_n" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_qdriip_dll_off_n</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_qdriip_dll_off_n" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_qdriip_dbg_pi_counter_read_val</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">4</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_qdriip_dbg_pi_counter_read_val" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_QDRIIP_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_qdriip_dbg_win_inc</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_qdriip_dbg_win_inc" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_QDRIIP_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_qdriip_dbg_win_dec</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_qdriip_dbg_win_dec" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_QDRIIP_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_qdriip_dbg_win_active</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_qdriip_dbg_win_active" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_QDRIIP_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_qdriip_dbg_win_current_byte</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">2</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_qdriip_dbg_win_current_byte" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_QDRIIP_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_qdriip_ila0_data</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">254</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_qdriip_ila0_data" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_QDRIIP_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_qdriip_ila0_trig</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">6</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_qdriip_ila0_trig" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_QDRIIP_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_qdriip_ila1_data</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">269</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_qdriip_ila1_data" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_QDRIIP_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_qdriip_ila1_trig</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">14</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_qdriip_ila1_trig" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_QDRIIP_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_qdriip_vio2_async_in</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">198</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_qdriip_vio2_async_in" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_QDRIIP_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_qdriip_vio2_sync_out</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">34</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_qdriip_vio2_sync_out" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_QDRIIP_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_app_wr_cmd0</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_app_wr_cmd0" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_app_wr_addr0</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_QDRIIP_ADDR_WIDTH&apos;)) )- 1 ">28</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_app_wr_addr0" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_app_wr_data0</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_QDRIIP_BURST_LEN&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_app_wr_data0" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_app_wr_bw_n0</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_QDRIIP_BURST_LEN&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_app_wr_bw_n0" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_app_rd_cmd0</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_app_rd_cmd0" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_app_rd_addr0</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_QDRIIP_ADDR_WIDTH&apos;)) )- 1 ">28</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_app_rd_addr0" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_app_rd_valid0</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_app_rd_valid0" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_app_rd_data0</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_QDRIIP_BURST_LEN&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_app_rd_data0" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_app_wr_cmd1</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_app_wr_cmd1" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_app_wr_addr1</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_QDRIIP_ADDR_WIDTH&apos;)) )- 1 ">28</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_app_wr_addr1" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_app_wr_data1</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" (( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_QDRIIP_DATA_WIDTH&apos;)) * 2 ))- 1 ">35</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_app_wr_data1" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_app_wr_bw_n1</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" (( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_QDRIIP_BW_WIDTH&apos;)) * 2 ))- 1 ">15</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_app_wr_bw_n1" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_app_rd_cmd1</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_app_rd_cmd1" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_app_rd_addr1</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_QDRIIP_ADDR_WIDTH&apos;)) )- 1 ">28</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_app_rd_addr1" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_app_rd_valid1</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_app_rd_valid1" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_app_rd_data1</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" (( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_QDRIIP_DATA_WIDTH&apos;)) * 2 ))- 1 ">35</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_app_rd_data1" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_clk</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_clk" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_rst_clk</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_rst_clk" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_qdriip_app_wr_cmd0</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_qdriip_app_wr_cmd0" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_qdriip_app_wr_addr0</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_QDRIIP_ADDR_WIDTH&apos;)) )- 1 ">28</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_qdriip_app_wr_addr0" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_qdriip_app_wr_data0</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_QDRIIP_BURST_LEN&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_qdriip_app_wr_data0" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_qdriip_app_wr_bw_n0</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_QDRIIP_BURST_LEN&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_qdriip_app_wr_bw_n0" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_qdriip_app_rd_cmd0</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_qdriip_app_rd_cmd0" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_qdriip_app_rd_addr0</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_QDRIIP_ADDR_WIDTH&apos;)) )- 1 ">28</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_qdriip_app_rd_addr0" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_qdriip_app_rd_valid0</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_qdriip_app_rd_valid0" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_qdriip_app_rd_data0</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_QDRIIP_BURST_LEN&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_qdriip_app_rd_data0" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_qdriip_app_wr_cmd1</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_qdriip_app_wr_cmd1" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_qdriip_app_wr_addr1</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_QDRIIP_ADDR_WIDTH&apos;)) )- 1 ">28</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_qdriip_app_wr_addr1" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_qdriip_app_wr_data1</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" (( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_QDRIIP_DATA_WIDTH&apos;)) * 2 ))- 1 ">35</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_qdriip_app_wr_data1" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_qdriip_app_wr_bw_n1</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" (( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_QDRIIP_BW_WIDTH&apos;)) * 2 ))- 1 ">15</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_qdriip_app_wr_bw_n1" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_qdriip_app_rd_cmd1</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_qdriip_app_rd_cmd1" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_qdriip_app_rd_addr1</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_QDRIIP_ADDR_WIDTH&apos;)) )- 1 ">28</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_qdriip_app_rd_addr1" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_qdriip_app_rd_valid1</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_qdriip_app_rd_valid1" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_qdriip_app_rd_data1</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" (( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_QDRIIP_DATA_WIDTH&apos;)) * 2 ))- 1 ">35</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_qdriip_app_rd_data1" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_qdriip_clk</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_qdriip_clk" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_qdriip_rst_clk</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_qdriip_rst_clk" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_rldii_qk_p</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_RLDII_QK_WIDTH&apos;)) )- 1 ">7</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_rldii_qk_p" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;RLDII&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_rldii_qk_n</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_RLDII_QK_WIDTH&apos;)) )- 1 ">7</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_rldii_qk_n" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;RLDII&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_rldii_dq</spirit:name>
        <spirit:wire>
          <spirit:direction>inout</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_RLDII_DATA_WIDTH&apos;)) )- 1 ">17</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_rldii_dq" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;RLDII&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_rldii_dm</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_RLDII_DM_WIDTH&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_rldii_dm" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;RLDII&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_rldii_dk_p</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_RLDII_DK_WIDTH&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_rldii_dk_p" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;RLDII&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_rldii_dk_n</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_RLDII_DK_WIDTH&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_rldii_dk_n" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;RLDII&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_rldii_ck_p</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_RLDII_NUM_DEVICES&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_rldii_ck_p" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;RLDII&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_rldii_ck_n</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_RLDII_NUM_DEVICES&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_rldii_ck_n" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;RLDII&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_rldii_cs_n</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_RLDII_NUM_DEVICES&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_rldii_cs_n" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;RLDII&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_rldii_a</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_RLDII_RLD_ADDR_WIDTH&apos;)) )- 1 ">28</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_rldii_a" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;RLDII&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_rldii_ba</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_RLDII_BANK_WIDTH&apos;)) )- 1 ">1</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_rldii_ba" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;RLDII&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_rldii_qvld</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_RLDII_QVLD_WIDTH&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_rldii_qvld" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;RLDII&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_rldii_we_n</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_rldii_we_n" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;RLDII&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_rldii_ref_n</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_rldii_ref_n" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;RLDII&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_rldii_reset_n</spirit:name>
        <spirit:displayName>reset to memory device</spirit:displayName>
        <spirit:description>reset to memory device</spirit:description>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_rldii_reset_n" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;RLDII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;RLDIII&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_rldii_dbg_pi_tap_cnt</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">4</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_rldii_dbg_pi_tap_cnt" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;RLDII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_RLDII_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_rldii_dbg_win_inc</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_rldii_dbg_win_inc" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;RLDII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_RLDII_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_rldii_dbg_win_dec</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_rldii_dbg_win_dec" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;RLDII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_RLDII_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_rldii_dbg_win_active</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_rldii_dbg_win_active" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;RLDII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_RLDII_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_rldii_dbg_win_current_byte</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">2</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_rldii_dbg_win_current_byte" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;RLDII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_RLDII_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_rldii_ila0_data</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">638</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_rldii_ila0_data" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;RLDII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_RLDII_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_rldii_ila0_trig</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">30</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_rldii_ila0_trig" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;RLDII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_RLDII_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_rldii_vio1_async_in</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">254</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_rldii_vio1_async_in" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;RLDII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_RLDII_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_rldii_vio1_async_out</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">62</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_rldii_vio1_async_out" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;RLDII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_RLDII_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_rldii_vio1_sync_out</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">62</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_rldii_vio1_sync_out" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;RLDII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_RLDII_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_rldiii_qk_p</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_RLDIII_QK_WIDTH&apos;)) )- 1 ">7</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_rldiii_qk_p" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;RLDIII&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_rldiii_qk_n</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_RLDIII_QK_WIDTH&apos;)) )- 1 ">7</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_rldiii_qk_n" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;RLDIII&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_rldiii_dq</spirit:name>
        <spirit:wire>
          <spirit:direction>inout</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_RLDIII_DATA_WIDTH&apos;)) )- 1 ">17</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_rldiii_dq" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;RLDIII&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_rldiii_dm</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_RLDIII_DM_WIDTH&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_rldiii_dm" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;RLDIII&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_rldiii_dk_p</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_RLDIII_DK_WIDTH&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_rldiii_dk_p" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;RLDIII&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_rldiii_dk_n</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_RLDIII_DK_WIDTH&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_rldiii_dk_n" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;RLDIII&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_rldiii_ck_p</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_RLDIII_NUM_DEVICES&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_rldiii_ck_p" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;RLDIII&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_rldiii_ck_n</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_RLDIII_NUM_DEVICES&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_rldiii_ck_n" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;RLDIII&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_rldiii_cs_n</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_RLDIII_NUM_DEVICES&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_rldiii_cs_n" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;RLDIII&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_rldiii_a</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_RLDIII_RLD_ADDR_WIDTH&apos;)) )- 1 ">28</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_rldiii_a" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;RLDIII&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_rldiii_ba</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_RLDIII_BANK_WIDTH&apos;)) )- 1 ">1</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_rldiii_ba" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;RLDIII&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_rldiii_qvld</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_RLDIII_QVLD_WIDTH&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_rldiii_qvld" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;RLDIII&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_rldiii_we_n</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_rldiii_we_n" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;RLDIII&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_rldiii_ref_n</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_rldiii_ref_n" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;RLDIII&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_rldiii_reset_n</spirit:name>
        <spirit:displayName>reset to memory device</spirit:displayName>
        <spirit:description>reset to memory device</spirit:description>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_rldiii_reset_n" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;RLDIII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;RLDIII&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_dbg_pi_tap_cnt</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">4</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_dbg_pi_tap_cnt" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;RLDIII&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;RLDII&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_rldiii_dbg_pi_tap_cnt</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">4</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_rldiii_dbg_pi_tap_cnt" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;RLDIII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_RLDIII_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_rldiii_dbg_win_inc</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_rldiii_dbg_win_inc" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;RLDIII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_RLDIII_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_rldiii_dbg_win_dec</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_rldiii_dbg_win_dec" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;RLDIII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_RLDIII_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_rldiii_dbg_win_active</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_rldiii_dbg_win_active" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;RLDIII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_RLDIII_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_rldiii_dbg_win_current_byte</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">2</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_rldiii_dbg_win_current_byte" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;RLDIII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_RLDIII_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_rldiii_ila0_data</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">638</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_rldiii_ila0_data" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;RLDIII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_RLDIII_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_rldiii_ila0_trig</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">30</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_rldiii_ila0_trig" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;RLDIII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_RLDIII_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_rldiii_vio1_async_in</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">254</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_rldiii_vio1_async_in" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;RLDIII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_RLDIII_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_rldiii_vio1_async_out</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">62</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_rldiii_vio1_async_out" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;RLDIII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_RLDIII_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_rldiii_vio1_sync_out</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">62</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_rldiii_vio1_sync_out" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;RLDIII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_RLDIII_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_dbg_win_inc</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_dbg_win_inc" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;RLDIII&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;RLDII&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_dbg_win_dec</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_dbg_win_dec" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;RLDIII&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;RLDII&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_dbg_win_active</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_dbg_win_active" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;RLDIII&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;RLDII&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_dbg_win_current_byte</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">2</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_dbg_win_current_byte" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;RLDIII&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;RLDII&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_dbg_pi_counter_read_val</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">4</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_dbg_pi_counter_read_val" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;DDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_user_cmd_en</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_user_cmd_en" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;RLDII&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;RLDIII&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_user_cmd</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_RLDX_CMD_PER_CLK&apos;)) * 2 )- 1 ">1</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_user_cmd" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;RLDII&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;RLDIII&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_user_addr</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_RLDX_ADDR_WIDTH&apos;)) * spirit:decode(id(&apos;MODELPARAM_VALUE.C2_RLDX_CMD_PER_CLK&apos;)) )- 1 ">28</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_user_addr" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;RLDII&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;RLDIII&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_user_ba</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_RLDX_BANK_WIDTH&apos;)) * spirit:decode(id(&apos;MODELPARAM_VALUE.C2_RLDX_CMD_PER_CLK&apos;)) )- 1 ">1</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_user_ba" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;RLDII&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;RLDIII&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_user_wr_en</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_user_wr_en" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;RLDII&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;RLDIII&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_user_wr_data</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_RLDX_DATA_WIDTH&apos;)) * 2 * spirit:decode(id(&apos;MODELPARAM_VALUE.C2_RLDX_nCK_PER_CLK&apos;)) )- 1 ">35</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_user_wr_data" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;RLDII&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;RLDIII&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_user_wr_dm</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_RLDX_DM_WIDTH&apos;)) * 2 * spirit:decode(id(&apos;MODELPARAM_VALUE.C2_RLDX_nCK_PER_CLK&apos;)) )- 1 ">1</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_user_wr_dm" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;RLDII&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;RLDIII&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_user_afifo_empty</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_user_afifo_empty" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;RLDII&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;RLDIII&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_user_afifo_full</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_user_afifo_full" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;RLDII&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;RLDIII&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_user_afifo_aempty</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_user_afifo_aempty" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;RLDII&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;RLDIII&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_user_afifo_afull</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_user_afifo_afull" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;RLDII&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;RLDIII&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_user_wdfifo_empty</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_user_wdfifo_empty" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;RLDII&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;RLDIII&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_user_wdfifo_full</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_user_wdfifo_full" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;RLDII&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;RLDIII&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_user_wdfifo_aempty</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_user_wdfifo_aempty" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;RLDII&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;RLDIII&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_user_wdfifo_afull</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_user_wdfifo_afull" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;RLDII&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;RLDIII&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_user_rd_valid</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_RLDX_nCK_PER_CLK&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_user_rd_valid" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;RLDII&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;RLDIII&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_mem_ck_lock_complete</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_mem_ck_lock_complete" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;RLDII&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;RLDIII&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_user_rd_data</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_RLDX_DATA_WIDTH&apos;)) * 2 * spirit:decode(id(&apos;MODELPARAM_VALUE.C2_RLDX_nCK_PER_CLK&apos;)) )- 1 ">35</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_user_rd_data" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;RLDII&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;RLDIII&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_rldii_user_cmd_en</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_rldii_user_cmd_en" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;RLDII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_rldii_user_cmd</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_RLDII_CMD_PER_CLK&apos;)) * 2 )- 1 ">1</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_rldii_user_cmd" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;RLDII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_rldii_user_addr</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_RLDII_ADDR_WIDTH&apos;)) * spirit:decode(id(&apos;MODELPARAM_VALUE.C2_RLDII_CMD_PER_CLK&apos;)) )- 1 ">28</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_rldii_user_addr" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;RLDII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_rldii_user_ba</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_RLDII_BANK_WIDTH&apos;)) * spirit:decode(id(&apos;MODELPARAM_VALUE.C2_RLDII_CMD_PER_CLK&apos;)) )- 1 ">1</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_rldii_user_ba" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;RLDII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_rldii_user_wr_en</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_rldii_user_wr_en" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;RLDII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_rldii_user_wr_data</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_RLDII_DATA_WIDTH&apos;)) * 2 * spirit:decode(id(&apos;MODELPARAM_VALUE.C2_RLDII_nCK_PER_CLK&apos;)) )- 1 ">35</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_rldii_user_wr_data" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;RLDII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_rldii_user_wr_dm</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_RLDII_DM_WIDTH&apos;)) * 2 * spirit:decode(id(&apos;MODELPARAM_VALUE.C2_RLDII_nCK_PER_CLK&apos;)) )- 1 ">1</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_rldii_user_wr_dm" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;RLDII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_rldii_user_afifo_empty</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_rldii_user_afifo_empty" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;RLDII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_rldii_user_afifo_full</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_rldii_user_afifo_full" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;RLDII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_rldii_user_afifo_aempty</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_rldii_user_afifo_aempty" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;RLDII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_rldii_user_afifo_afull</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_rldii_user_afifo_afull" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;RLDII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_rldii_user_wdfifo_empty</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_rldii_user_wdfifo_empty" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;RLDII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_rldii_user_wdfifo_full</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_rldii_user_wdfifo_full" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;RLDII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_rldii_user_wdfifo_aempty</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_rldii_user_wdfifo_aempty" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;RLDII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_rldii_user_wdfifo_afull</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_rldii_user_wdfifo_afull" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;RLDII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_rldii_user_rd_valid</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_RLDII_nCK_PER_CLK&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_rldii_user_rd_valid" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;RLDII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_rldii_mem_ck_lock_complete</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_rldii_mem_ck_lock_complete" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;RLDII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_rldii_user_rd_data</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_RLDII_DATA_WIDTH&apos;)) * 2 * spirit:decode(id(&apos;MODELPARAM_VALUE.C2_RLDII_nCK_PER_CLK&apos;)) )- 1 ">35</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_rldii_user_rd_data" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;RLDII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_rldiii_user_cmd_en</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_rldiii_user_cmd_en" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;RLDIII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_rldiii_user_cmd</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_RLDIII_CMD_PER_CLK&apos;)) * 2 )- 1 ">1</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_rldiii_user_cmd" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;RLDIII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_rldiii_user_addr</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_RLDIII_ADDR_WIDTH&apos;)) * spirit:decode(id(&apos;MODELPARAM_VALUE.C2_RLDIII_CMD_PER_CLK&apos;)) )- 1 ">28</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_rldiii_user_addr" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;RLDIII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_rldiii_user_ba</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_RLDIII_BANK_WIDTH&apos;)) * spirit:decode(id(&apos;MODELPARAM_VALUE.C2_RLDIII_CMD_PER_CLK&apos;)) )- 1 ">1</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_rldiii_user_ba" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;RLDIII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_rldiii_user_wr_en</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_rldiii_user_wr_en" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;RLDIII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_rldiii_user_wr_data</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_RLDIII_DATA_WIDTH&apos;)) * 2 * spirit:decode(id(&apos;MODELPARAM_VALUE.C2_RLDIII_nCK_PER_CLK&apos;)) )- 1 ">35</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_rldiii_user_wr_data" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;RLDIII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_rldiii_user_wr_dm</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_RLDIII_DM_WIDTH&apos;)) * 2 * spirit:decode(id(&apos;MODELPARAM_VALUE.C2_RLDIII_nCK_PER_CLK&apos;)) )- 1 ">1</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_rldiii_user_wr_dm" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;RLDIII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_rldiii_user_afifo_empty</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_rldiii_user_afifo_empty" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;RLDIII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_rldiii_user_afifo_full</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_rldiii_user_afifo_full" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;RLDIII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_rldiii_user_afifo_aempty</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_rldiii_user_afifo_aempty" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;RLDIII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_rldiii_user_afifo_afull</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_rldiii_user_afifo_afull" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;RLDIII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_rldiii_user_wdfifo_empty</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_rldiii_user_wdfifo_empty" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;RLDIII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_rldiii_user_wdfifo_full</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_rldiii_user_wdfifo_full" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;RLDIII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_rldiii_user_wdfifo_aempty</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_rldiii_user_wdfifo_aempty" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;RLDIII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_rldiii_user_wdfifo_afull</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_rldiii_user_wdfifo_afull" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;RLDIII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_rldiii_user_rd_valid</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_RLDIII_nCK_PER_CLK&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_rldiii_user_rd_valid" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;RLDIII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_rldiii_mem_ck_lock_complete</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_rldiii_mem_ck_lock_complete" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;RLDIII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_rldiii_user_rd_data</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_RLDIII_DATA_WIDTH&apos;)) * 2 * spirit:decode(id(&apos;MODELPARAM_VALUE.C2_RLDIII_nCK_PER_CLK&apos;)) )- 1 ">35</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_rldiii_user_rd_data" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;RLDIII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_sys_clk_p</spirit:name>
        <spirit:displayName>Clock P</spirit:displayName>
        <spirit:description>Clock P</spirit:description>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_sys_clk_p" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_SYSCLK_TYPE&apos;)) = &quot;DIFF&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_IS_CLK_SHARED&apos;)) = &quot;FALSE&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_sys_clk_n</spirit:name>
        <spirit:displayName>Clock P</spirit:displayName>
        <spirit:description>Clock P</spirit:description>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_sys_clk_n" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_SYSCLK_TYPE&apos;)) = &quot;DIFF&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_IS_CLK_SHARED&apos;)) = &quot;FALSE&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_sys_clk_i</spirit:name>
        <spirit:displayName>Clock P</spirit:displayName>
        <spirit:description>Clock P</spirit:description>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_sys_clk_i" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_SYSCLK_TYPE&apos;)) != &quot;DIFF&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C2_IS_CLK_SHARED&apos;)) = &quot;FALSE&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_init_calib_complete</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_init_calib_complete" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c2_aresetn</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2_aresetn" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 2 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C2_MEM_TYPE&apos;)) = &quot;DDR2&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_ddr3_dq</spirit:name>
        <spirit:displayName>Data</spirit:displayName>
        <spirit:description>Data</spirit:description>
        <spirit:wire>
          <spirit:direction>inout</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_DDR3_DQ_WIDTH&apos;)) )- 1 ">7</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_ddr3_dq" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;DDR3&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_ddr3_dqs_p</spirit:name>
        <spirit:displayName>Data Strobe</spirit:displayName>
        <spirit:description>Data Strobe</spirit:description>
        <spirit:wire>
          <spirit:direction>inout</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_DDR3_DQS_WIDTH&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_ddr3_dqs_p" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;DDR3&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_ddr3_dqs_n</spirit:name>
        <spirit:displayName>Data Strobe</spirit:displayName>
        <spirit:description>Data Strobe</spirit:description>
        <spirit:wire>
          <spirit:direction>inout</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_DDR3_DQS_WIDTH&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_ddr3_dqs_n" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;DDR3&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_ddr3_addr</spirit:name>
        <spirit:displayName>Address</spirit:displayName>
        <spirit:description>Address</spirit:description>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_DDR3_ROW_WIDTH&apos;)) )- 1 ">13</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_ddr3_addr" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;DDR3&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_ddr3_ba</spirit:name>
        <spirit:displayName>Bank Address</spirit:displayName>
        <spirit:description>Bank Address</spirit:description>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_DDR3_BANK_WIDTH&apos;)) )- 1 ">2</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_ddr3_ba" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;DDR3&quot; and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;DDR2&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_ddr3_ras_n</spirit:name>
        <spirit:displayName>row address strobe</spirit:displayName>
        <spirit:description>row address strobe</spirit:description>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_ddr3_ras_n" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;DDR3&quot; and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;DDR2&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_ddr3_cas_n</spirit:name>
        <spirit:displayName>column address strobe</spirit:displayName>
        <spirit:description>column address strobe</spirit:description>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_ddr3_cas_n" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;DDR3&quot; and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;DDR2&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_ddr3_we_n</spirit:name>
        <spirit:displayName>write enable</spirit:displayName>
        <spirit:description>write enable</spirit:description>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_ddr3_we_n" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;DDR3&quot; and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;DDR2&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_ddr3_reset_n</spirit:name>
        <spirit:displayName>reset to memory device</spirit:displayName>
        <spirit:description>reset to memory device</spirit:description>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_ddr3_reset_n" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;DDR3&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_ddr3_ck_p</spirit:name>
        <spirit:displayName>clock to memory device</spirit:displayName>
        <spirit:description>clock to memory device</spirit:description>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_DDR3_CK_WIDTH&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_ddr3_ck_p" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;DDR3&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_ddr3_ck_n</spirit:name>
        <spirit:displayName>clock to memory device</spirit:displayName>
        <spirit:description>clock to memory device</spirit:description>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_DDR3_CK_WIDTH&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_ddr3_ck_n" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;DDR3&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_ddr3_cke</spirit:name>
        <spirit:displayName>clock enable</spirit:displayName>
        <spirit:description>clock enable</spirit:description>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_DDR3_CKE_WIDTH&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_ddr3_cke" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;DDR3&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_ddr3_cs_n</spirit:name>
        <spirit:displayName>chip select</spirit:displayName>
        <spirit:description>chip select</spirit:description>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_DDR3_CS_WIDTH&apos;)) * spirit:decode(id(&apos;MODELPARAM_VALUE.C3_DDR3_nCS_PER_RANK&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_ddr3_cs_n" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_DDR3_USE_CS_PORT&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_ddr3_dm</spirit:name>
        <spirit:displayName>data mask</spirit:displayName>
        <spirit:description>data mask</spirit:description>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_DDR3_DM_WIDTH&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_ddr3_dm" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_DDR3_USE_DM_PORT&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_ddr3_odt</spirit:name>
        <spirit:displayName>on die termination</spirit:displayName>
        <spirit:description>on die termination</spirit:description>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_DDR3_ODT_WIDTH&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_ddr3_odt" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;DDR3&quot; and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;DDR2&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_DDR3_USE_ODT_PORT&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_ddr3_parity</spirit:name>
        <spirit:displayName>parity bit</spirit:displayName>
        <spirit:description>parity bit</spirit:description>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_ddr3_parity" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_DDR3_REG_CTRL&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_ddr3_dbg_pi_counter_read_val</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">4</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_ddr3_dbg_pi_counter_read_val" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_DDR3_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_ddr3_dbg_byte_sel</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_DDR3_DQS_CNT_WIDTH&apos;)) + 1 )- 1 ">1</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_ddr3_dbg_byte_sel" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_DDR3_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_ddr3_dbg_sel_pi_incdec</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_ddr3_dbg_sel_pi_incdec" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_DDR3_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_ddr3_dbg_pi_f_inc</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_ddr3_dbg_pi_f_inc" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_DDR3_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_ddr3_dbg_pi_f_dec</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_ddr3_dbg_pi_f_dec" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_DDR3_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_ddr3_dbg_sel_po_incdec</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_ddr3_dbg_sel_po_incdec" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_DDR3_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_ddr3_dbg_po_f_inc</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_ddr3_dbg_po_f_inc" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_DDR3_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_ddr3_dbg_po_f_stg23_sel</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_ddr3_dbg_po_f_stg23_sel" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_DDR3_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_ddr3_dbg_po_f_dec</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_ddr3_dbg_po_f_dec" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_DDR3_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_ddr3_dbg_po_counter_read_val</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">7</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_ddr3_dbg_po_counter_read_val" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_DDR3_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_ddr3_ila_wrpath</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">254</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_ddr3_ila_wrpath" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_DDR3_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_ddr3_ila_rdpath</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">1022</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_ddr3_ila_rdpath" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_DDR3_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_ddr3_ila_basic</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">126</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_ddr3_ila_basic" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_DDR3_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_ddr3_vio_sync_out</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">34</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_ddr3_vio_sync_out" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_DDR3_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_ddr2_dq</spirit:name>
        <spirit:displayName>Data</spirit:displayName>
        <spirit:description>Data</spirit:description>
        <spirit:wire>
          <spirit:direction>inout</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_DDR2_DQ_WIDTH&apos;)) )- 1 ">7</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_ddr2_dq" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;DDR2&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_ddr2_dqs_p</spirit:name>
        <spirit:displayName>Data Strobe</spirit:displayName>
        <spirit:description>Data Strobe</spirit:description>
        <spirit:wire>
          <spirit:direction>inout</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_DDR2_DQS_WIDTH&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_ddr2_dqs_p" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;DDR2&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_ddr2_dqs_n</spirit:name>
        <spirit:displayName>Data Strobe</spirit:displayName>
        <spirit:description>Data Strobe</spirit:description>
        <spirit:wire>
          <spirit:direction>inout</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_DDR2_DQS_WIDTH&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_ddr2_dqs_n" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;DDR2&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_ddr2_addr</spirit:name>
        <spirit:displayName>Address</spirit:displayName>
        <spirit:description>Address</spirit:description>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_DDR2_ROW_WIDTH&apos;)) )- 1 ">13</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_ddr2_addr" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;DDR2&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_ddr2_ba</spirit:name>
        <spirit:displayName>Bank Address</spirit:displayName>
        <spirit:description>Bank Address</spirit:description>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_DDR2_BANK_WIDTH&apos;)) )- 1 ">2</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_ddr2_ba" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;DDR2&quot; and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;DDR2&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_ddr2_ras_n</spirit:name>
        <spirit:displayName>row address strobe</spirit:displayName>
        <spirit:description>row address strobe</spirit:description>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_ddr2_ras_n" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;DDR2&quot; and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;DDR2&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_ddr2_cas_n</spirit:name>
        <spirit:displayName>column address strobe</spirit:displayName>
        <spirit:description>column address strobe</spirit:description>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_ddr2_cas_n" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;DDR2&quot; and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;DDR2&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_ddr2_we_n</spirit:name>
        <spirit:displayName>write enable</spirit:displayName>
        <spirit:description>write enable</spirit:description>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_ddr2_we_n" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;DDR2&quot; and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;DDR2&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_ddr2_reset_n</spirit:name>
        <spirit:displayName>reset to memory device</spirit:displayName>
        <spirit:description>reset to memory device</spirit:description>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_ddr2_reset_n" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;DDR3&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_ddr2_ck_p</spirit:name>
        <spirit:displayName>clock to memory device</spirit:displayName>
        <spirit:description>clock to memory device</spirit:description>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_DDR2_CK_WIDTH&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_ddr2_ck_p" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;DDR2&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_ddr2_ck_n</spirit:name>
        <spirit:displayName>clock to memory device</spirit:displayName>
        <spirit:description>clock to memory device</spirit:description>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_DDR2_CK_WIDTH&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_ddr2_ck_n" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;DDR2&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_ddr2_cke</spirit:name>
        <spirit:displayName>clock enable</spirit:displayName>
        <spirit:description>clock enable</spirit:description>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_DDR2_CKE_WIDTH&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_ddr2_cke" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;DDR2&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_ddr2_cs_n</spirit:name>
        <spirit:displayName>chip select</spirit:displayName>
        <spirit:description>chip select</spirit:description>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_DDR2_CS_WIDTH&apos;)) * spirit:decode(id(&apos;MODELPARAM_VALUE.C3_DDR2_nCS_PER_RANK&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_ddr2_cs_n" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_DDR2_USE_CS_PORT&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_ddr2_dm</spirit:name>
        <spirit:displayName>data mask</spirit:displayName>
        <spirit:description>data mask</spirit:description>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_DDR2_DM_WIDTH&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_ddr2_dm" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_DDR2_USE_DM_PORT&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_ddr2_odt</spirit:name>
        <spirit:displayName>on die termination</spirit:displayName>
        <spirit:description>on die termination</spirit:description>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_DDR2_ODT_WIDTH&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_ddr2_odt" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;DDR2&quot; and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;DDR2&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_DDR2_USE_ODT_PORT&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_ddr2_parity</spirit:name>
        <spirit:displayName>parity bit</spirit:displayName>
        <spirit:description>parity bit</spirit:description>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_ddr2_parity" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_DDR2_REG_CTRL&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_ddr2_dbg_pi_counter_read_val</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">4</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_ddr2_dbg_pi_counter_read_val" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_DDR2_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_ddr2_dbg_byte_sel</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_DDR2_DQS_CNT_WIDTH&apos;)) + 1 )- 1 ">1</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_ddr2_dbg_byte_sel" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_DDR2_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_ddr2_dbg_sel_pi_incdec</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_ddr2_dbg_sel_pi_incdec" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_DDR2_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_ddr2_dbg_pi_f_inc</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_ddr2_dbg_pi_f_inc" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_DDR2_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_ddr2_dbg_pi_f_dec</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_ddr2_dbg_pi_f_dec" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_DDR2_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_ddr2_dbg_sel_po_incdec</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_ddr2_dbg_sel_po_incdec" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_DDR2_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_ddr2_dbg_po_f_inc</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_ddr2_dbg_po_f_inc" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_DDR2_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_ddr2_dbg_po_f_stg23_sel</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_ddr2_dbg_po_f_stg23_sel" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_DDR2_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_ddr2_dbg_po_f_dec</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_ddr2_dbg_po_f_dec" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_DDR2_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_ddr2_dbg_po_counter_read_val</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">7</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_ddr2_dbg_po_counter_read_val" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_DDR2_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_ddr2_ila_wrpath</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">254</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_ddr2_ila_wrpath" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_DDR2_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_ddr2_ila_rdpath</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">1022</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_ddr2_ila_rdpath" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_DDR2_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_ddr2_ila_basic</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">126</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_ddr2_ila_basic" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_DDR2_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_ddr2_vio_sync_out</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">34</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_ddr2_vio_sync_out" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_DDR2_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_lpddr2_dq</spirit:name>
        <spirit:displayName>Data</spirit:displayName>
        <spirit:description>Data</spirit:description>
        <spirit:wire>
          <spirit:direction>inout</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_LPDDR2_DQ_WIDTH&apos;)) )- 1 ">7</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_lpddr2_dq" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_lpddr2_dqs_p</spirit:name>
        <spirit:displayName>Data Strobe</spirit:displayName>
        <spirit:description>Data Strobe</spirit:description>
        <spirit:wire>
          <spirit:direction>inout</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_LPDDR2_DQS_WIDTH&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_lpddr2_dqs_p" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_lpddr2_dqs_n</spirit:name>
        <spirit:displayName>Data Strobe</spirit:displayName>
        <spirit:description>Data Strobe</spirit:description>
        <spirit:wire>
          <spirit:direction>inout</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_LPDDR2_DQS_WIDTH&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_lpddr2_dqs_n" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_lpddr2_ca</spirit:name>
        <spirit:displayName>Address</spirit:displayName>
        <spirit:description>Address</spirit:description>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">9</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_lpddr2_ca" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_lpddr2_ck_p</spirit:name>
        <spirit:displayName>clock to memory device</spirit:displayName>
        <spirit:description>clock to memory device</spirit:description>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_LPDDR2_CK_WIDTH&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_lpddr2_ck_p" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_lpddr2_ck_n</spirit:name>
        <spirit:displayName>clock to memory device</spirit:displayName>
        <spirit:description>clock to memory device</spirit:description>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_LPDDR2_CK_WIDTH&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_lpddr2_ck_n" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_lpddr2_cke</spirit:name>
        <spirit:displayName>clock enable</spirit:displayName>
        <spirit:description>clock enable</spirit:description>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_LPDDR2_CKE_WIDTH&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_lpddr2_cke" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_lpddr2_cs_n</spirit:name>
        <spirit:displayName>chip select</spirit:displayName>
        <spirit:description>chip select</spirit:description>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_LPDDR2_CS_WIDTH&apos;)) * spirit:decode(id(&apos;MODELPARAM_VALUE.C3_LPDDR2_nCS_PER_RANK&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_lpddr2_cs_n" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_LPDDR2_USE_CS_PORT&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_lpddr2_dm</spirit:name>
        <spirit:displayName>data mask</spirit:displayName>
        <spirit:description>data mask</spirit:description>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_LPDDR2_DM_WIDTH&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_lpddr2_dm" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_LPDDR2_USE_DM_PORT&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_lpddr2_parity</spirit:name>
        <spirit:displayName>parity bit</spirit:displayName>
        <spirit:description>parity bit</spirit:description>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_lpddr2_parity" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_LPDDR2_REG_CTRL&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_lpddr2_dbg_pi_counter_read_val</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">4</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_lpddr2_dbg_pi_counter_read_val" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_LPDDR2_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_lpddr2_dbg_byte_sel</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_LPDDR2_DQS_CNT_WIDTH&apos;)) + 1 )- 1 ">1</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_lpddr2_dbg_byte_sel" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_LPDDR2_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_lpddr2_dbg_sel_pi_incdec</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_lpddr2_dbg_sel_pi_incdec" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_LPDDR2_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_lpddr2_dbg_pi_f_inc</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_lpddr2_dbg_pi_f_inc" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_LPDDR2_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_lpddr2_dbg_pi_f_dec</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_lpddr2_dbg_pi_f_dec" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_LPDDR2_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_lpddr2_dbg_sel_po_incdec</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_lpddr2_dbg_sel_po_incdec" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_LPDDR2_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_lpddr2_dbg_po_f_inc</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_lpddr2_dbg_po_f_inc" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_LPDDR2_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_lpddr2_dbg_po_f_stg23_sel</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_lpddr2_dbg_po_f_stg23_sel" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_LPDDR2_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_lpddr2_dbg_po_f_dec</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_lpddr2_dbg_po_f_dec" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_LPDDR2_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_lpddr2_dbg_po_counter_read_val</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">7</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_lpddr2_dbg_po_counter_read_val" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_LPDDR2_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_lpddr2_ila_wrpath</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">254</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_lpddr2_ila_wrpath" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_LPDDR2_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_lpddr2_ila_rdpath</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">1022</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_lpddr2_ila_rdpath" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_LPDDR2_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_lpddr2_ila_basic</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">126</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_lpddr2_ila_basic" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_LPDDR2_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_lpddr2_vio_sync_out</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">34</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_lpddr2_vio_sync_out" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_LPDDR2_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_dbg_byte_sel</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_DQS_CNT_WIDTH&apos;)) + 1 )- 1 ">1</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_dbg_byte_sel" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;DDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_dbg_sel_pi_incdec</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_dbg_sel_pi_incdec" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;DDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_dbg_pi_f_inc</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_dbg_pi_f_inc" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;DDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_dbg_pi_f_dec</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_dbg_pi_f_dec" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;DDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_dbg_sel_po_incdec</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_dbg_sel_po_incdec" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;DDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_dbg_po_f_inc</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_dbg_po_f_inc" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;DDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_dbg_po_f_stg23_sel</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_dbg_po_f_stg23_sel" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;DDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_dbg_po_f_dec</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_dbg_po_f_dec" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;DDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_dbg_po_counter_read_val</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">7</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_dbg_po_counter_read_val" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;DDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_app_addr</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_DDRX_ADDR_WIDTH&apos;)) )- 1 ">7</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_app_addr" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;DDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_app_cmd</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">2</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_app_cmd" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;DDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_app_en</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_app_en" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;DDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_app_wdf_data</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_DDRX_nCK_PER_CLK&apos;)) * 2 * spirit:decode(id(&apos;MODELPARAM_VALUE.C3_DDRX_DATA_WIDTH&apos;)) )- 1 ">31</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_app_wdf_data" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;DDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_app_wdf_end</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_app_wdf_end" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;DDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_app_wdf_mask</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_DDRX_nCK_PER_CLK&apos;)) * 2 * spirit:decode(id(&apos;MODELPARAM_VALUE.C3_DDRX_DATA_WIDTH&apos;)) / 8 )- 1 ">3</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_app_wdf_mask" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;DDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_app_wdf_wren</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_app_wdf_wren" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;DDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_app_correct_en_i</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_app_correct_en_i" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;DDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_ECC&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_app_rd_data</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_DDRX_nCK_PER_CLK&apos;)) * 2 * spirit:decode(id(&apos;MODELPARAM_VALUE.C3_DDRX_DATA_WIDTH&apos;)) )- 1 ">31</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_app_rd_data" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;DDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_app_rd_data_end</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_app_rd_data_end" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;DDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_app_rd_data_valid</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_app_rd_data_valid" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;DDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_app_rdy</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_app_rdy" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;DDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_app_wdf_rdy</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_app_wdf_rdy" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;DDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_app_sr_req</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_app_sr_req" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;DDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_app_sr_active</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_app_sr_active" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;DDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_app_ref_req</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_app_ref_req" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;DDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_app_ref_ack</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_app_ref_ack" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;DDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_app_zq_req</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_app_zq_req" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;DDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_app_zq_ack</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_app_zq_ack" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;DDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_app_raw_not_ecc</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( 2 * spirit:decode(id(&apos;MODELPARAM_VALUE.C3_DDRX_nCK_PER_CLK&apos;)) )- 1 ">3</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_app_raw_not_ecc" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;DDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_ECC&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_app_ecc_multiple_err</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( 2 * spirit:decode(id(&apos;MODELPARAM_VALUE.C3_DDRX_nCK_PER_CLK&apos;)) )- 1 ">3</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_app_ecc_multiple_err" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;DDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_ECC&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_ddr3_app_addr</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_DDR3_ADDR_WIDTH&apos;)) )- 1 ">7</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_ddr3_app_addr" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_ddr3_app_cmd</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">2</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_ddr3_app_cmd" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_ddr3_app_en</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_ddr3_app_en" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_ddr3_app_wdf_data</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_DDR3_nCK_PER_CLK&apos;)) * 2 * spirit:decode(id(&apos;MODELPARAM_VALUE.C3_DDR3_DATA_WIDTH&apos;)) )- 1 ">31</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_ddr3_app_wdf_data" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_ddr3_app_wdf_end</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_ddr3_app_wdf_end" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_ddr3_app_wdf_mask</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_DDR3_nCK_PER_CLK&apos;)) * 2 * spirit:decode(id(&apos;MODELPARAM_VALUE.C3_DDR3_DATA_WIDTH&apos;)) / 8 )- 1 ">3</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_ddr3_app_wdf_mask" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_ddr3_app_wdf_wren</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_ddr3_app_wdf_wren" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_ddr3_app_correct_en_i</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_ddr3_app_correct_en_i" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_ECC&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_ddr3_app_rd_data</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_DDR3_nCK_PER_CLK&apos;)) * 2 * spirit:decode(id(&apos;MODELPARAM_VALUE.C3_DDR3_DATA_WIDTH&apos;)) )- 1 ">31</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_ddr3_app_rd_data" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_ddr3_app_rd_data_end</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_ddr3_app_rd_data_end" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_ddr3_app_rd_data_valid</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_ddr3_app_rd_data_valid" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_ddr3_app_rdy</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_ddr3_app_rdy" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_ddr3_app_wdf_rdy</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_ddr3_app_wdf_rdy" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_ddr3_app_sr_req</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_ddr3_app_sr_req" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_ddr3_app_sr_active</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_ddr3_app_sr_active" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_ddr3_app_ref_req</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_ddr3_app_ref_req" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_ddr3_app_ref_ack</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_ddr3_app_ref_ack" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_ddr3_app_zq_req</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_ddr3_app_zq_req" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_ddr3_app_zq_ack</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_ddr3_app_zq_ack" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_ddr3_app_raw_not_ecc</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( 2 * spirit:decode(id(&apos;MODELPARAM_VALUE.C3_DDR3_nCK_PER_CLK&apos;)) )- 1 ">3</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_ddr3_app_raw_not_ecc" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_ECC&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_ddr3_app_ecc_multiple_err</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( 2 * spirit:decode(id(&apos;MODELPARAM_VALUE.C3_DDR3_nCK_PER_CLK&apos;)) )- 1 ">3</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_ddr3_app_ecc_multiple_err" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_ECC&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_ddr2_app_addr</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_DDR2_ADDR_WIDTH&apos;)) )- 1 ">7</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_ddr2_app_addr" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_ddr2_app_cmd</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">2</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_ddr2_app_cmd" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_ddr2_app_en</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_ddr2_app_en" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_ddr2_app_wdf_data</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_DDR2_nCK_PER_CLK&apos;)) * 2 * spirit:decode(id(&apos;MODELPARAM_VALUE.C3_DDR2_DATA_WIDTH&apos;)) )- 1 ">31</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_ddr2_app_wdf_data" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_ddr2_app_wdf_end</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_ddr2_app_wdf_end" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_ddr2_app_wdf_mask</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_DDR2_nCK_PER_CLK&apos;)) * 2 * spirit:decode(id(&apos;MODELPARAM_VALUE.C3_DDR2_DATA_WIDTH&apos;)) / 8 )- 1 ">3</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_ddr2_app_wdf_mask" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_ddr2_app_wdf_wren</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_ddr2_app_wdf_wren" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_ddr2_app_correct_en_i</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_ddr2_app_correct_en_i" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_ECC&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_ddr2_app_rd_data</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_DDR2_nCK_PER_CLK&apos;)) * 2 * spirit:decode(id(&apos;MODELPARAM_VALUE.C3_DDR2_DATA_WIDTH&apos;)) )- 1 ">31</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_ddr2_app_rd_data" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_ddr2_app_rd_data_end</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_ddr2_app_rd_data_end" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_ddr2_app_rd_data_valid</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_ddr2_app_rd_data_valid" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_ddr2_app_rdy</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_ddr2_app_rdy" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_ddr2_app_wdf_rdy</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_ddr2_app_wdf_rdy" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_ddr2_app_sr_req</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_ddr2_app_sr_req" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_ddr2_app_sr_active</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_ddr2_app_sr_active" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_ddr2_app_ref_req</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_ddr2_app_ref_req" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_ddr2_app_ref_ack</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_ddr2_app_ref_ack" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_ddr2_app_zq_req</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_ddr2_app_zq_req" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_ddr2_app_zq_ack</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_ddr2_app_zq_ack" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_ddr2_app_raw_not_ecc</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( 2 * spirit:decode(id(&apos;MODELPARAM_VALUE.C3_DDR2_nCK_PER_CLK&apos;)) )- 1 ">3</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_ddr2_app_raw_not_ecc" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_ECC&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_ddr2_app_ecc_multiple_err</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( 2 * spirit:decode(id(&apos;MODELPARAM_VALUE.C3_DDR2_nCK_PER_CLK&apos;)) )- 1 ">3</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_ddr2_app_ecc_multiple_err" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_ECC&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_lpddr2_app_addr</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_LPDDR2_ADDR_WIDTH&apos;)) )- 1 ">7</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_lpddr2_app_addr" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_lpddr2_app_cmd</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">2</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_lpddr2_app_cmd" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_lpddr2_app_en</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_lpddr2_app_en" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_lpddr2_app_wdf_data</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_LPDDR2_nCK_PER_CLK&apos;)) * 2 * spirit:decode(id(&apos;MODELPARAM_VALUE.C3_LPDDR2_DATA_WIDTH&apos;)) )- 1 ">31</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_lpddr2_app_wdf_data" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_lpddr2_app_wdf_end</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_lpddr2_app_wdf_end" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_lpddr2_app_wdf_mask</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_LPDDR2_nCK_PER_CLK&apos;)) * 2 * spirit:decode(id(&apos;MODELPARAM_VALUE.C3_LPDDR2_DATA_WIDTH&apos;)) / 8 )- 1 ">3</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_lpddr2_app_wdf_mask" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_lpddr2_app_wdf_wren</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_lpddr2_app_wdf_wren" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_lpddr2_app_correct_en_i</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_lpddr2_app_correct_en_i" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_ECC&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_lpddr2_app_rd_data</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_LPDDR2_nCK_PER_CLK&apos;)) * 2 * spirit:decode(id(&apos;MODELPARAM_VALUE.C3_LPDDR2_DATA_WIDTH&apos;)) )- 1 ">31</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_lpddr2_app_rd_data" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_lpddr2_app_rd_data_end</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_lpddr2_app_rd_data_end" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_lpddr2_app_rd_data_valid</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_lpddr2_app_rd_data_valid" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_lpddr2_app_rdy</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_lpddr2_app_rdy" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_lpddr2_app_wdf_rdy</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_lpddr2_app_wdf_rdy" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_lpddr2_app_sr_req</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_lpddr2_app_sr_req" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_lpddr2_app_sr_active</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_lpddr2_app_sr_active" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_lpddr2_app_ref_req</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_lpddr2_app_ref_req" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_lpddr2_app_ref_ack</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_lpddr2_app_ref_ack" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_lpddr2_app_zq_req</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_lpddr2_app_zq_req" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_lpddr2_app_zq_ack</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_lpddr2_app_zq_ack" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_lpddr2_app_raw_not_ecc</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( 2 * spirit:decode(id(&apos;MODELPARAM_VALUE.C3_LPDDR2_nCK_PER_CLK&apos;)) )- 1 ">3</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_lpddr2_app_raw_not_ecc" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_ECC&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_lpddr2_app_ecc_multiple_err</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( 2 * spirit:decode(id(&apos;MODELPARAM_VALUE.C3_LPDDR2_nCK_PER_CLK&apos;)) )- 1 ">3</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_lpddr2_app_ecc_multiple_err" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_ECC&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_ui_clk_sync_rst</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_ui_clk_sync_rst" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;DDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;RLDII&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;RLDIII&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_ddr3_ui_clk_sync_rst</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_ddr3_ui_clk_sync_rst" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;DDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;RLDII&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;RLDIII&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_ddr2_ui_clk_sync_rst</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_ddr2_ui_clk_sync_rst" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;DDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;RLDII&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;RLDIII&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_lpddr2_ui_clk_sync_rst</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_lpddr2_ui_clk_sync_rst" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;DDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;RLDII&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;RLDIII&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_qdriip_ui_clk_sync_rst</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_qdriip_ui_clk_sync_rst" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;DDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;RLDII&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;RLDIII&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_rldii_ui_clk_sync_rst</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_rldii_ui_clk_sync_rst" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;RLDII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;DDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;RLDII&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;RLDIII&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_rldiii_ui_clk_sync_rst</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_rldiii_ui_clk_sync_rst" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;RLDIII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;DDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;RLDII&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;RLDIII&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_ui_clk</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_ui_clk" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;DDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;RLDII&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;RLDIII&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_ui_addn_clk_0</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_ui_addn_clk_0" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_UI_EXTRA_CLOCKS&apos;)) = &quot;TRUE&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MMCM_CLKOUT0_EN&apos;)) = &quot;TRUE&quot; ) and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;DDR2&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_ui_addn_clk_1</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_ui_addn_clk_1" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_UI_EXTRA_CLOCKS&apos;)) = &quot;TRUE&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MMCM_CLKOUT1_EN&apos;)) = &quot;TRUE&quot; ) and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;DDR2&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_ui_addn_clk_2</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_ui_addn_clk_2" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_UI_EXTRA_CLOCKS&apos;)) = &quot;TRUE&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MMCM_CLKOUT2_EN&apos;)) = &quot;TRUE&quot; ) and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;DDR2&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_ui_addn_clk_3</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_ui_addn_clk_3" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_UI_EXTRA_CLOCKS&apos;)) = &quot;TRUE&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MMCM_CLKOUT3_EN&apos;)) = &quot;TRUE&quot; ) and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;DDR2&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_ui_addn_clk_4</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_ui_addn_clk_4" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_UI_EXTRA_CLOCKS&apos;)) = &quot;TRUE&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MMCM_CLKOUT4_EN&apos;)) = &quot;TRUE&quot; ) and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;DDR2&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_s_axi_ctrl_awvalid</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_s_axi_ctrl_awvalid" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_USE_AXI&apos;)) = 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_ECC&apos;)) = &quot;ON&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_s_axi_ctrl_awready</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_s_axi_ctrl_awready" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_USE_AXI&apos;)) = 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_ECC&apos;)) = &quot;ON&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_s_axi_ctrl_awaddr</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_C_S_AXI_CTRL_ADDR_WIDTH&apos;)) )- 1 ">31</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_s_axi_ctrl_awaddr" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_USE_AXI&apos;)) = 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_ECC&apos;)) = &quot;ON&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_s_axi_ctrl_wvalid</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_s_axi_ctrl_wvalid" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_USE_AXI&apos;)) = 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_ECC&apos;)) = &quot;ON&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_s_axi_ctrl_wready</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_s_axi_ctrl_wready" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_USE_AXI&apos;)) = 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_ECC&apos;)) = &quot;ON&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_s_axi_ctrl_wdata</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_C_S_AXI_CTRL_DATA_WIDTH&apos;)) )- 1 ">31</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_s_axi_ctrl_wdata" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_USE_AXI&apos;)) = 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_ECC&apos;)) = &quot;ON&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_s_axi_ctrl_bvalid</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_s_axi_ctrl_bvalid" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_USE_AXI&apos;)) = 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_ECC&apos;)) = &quot;ON&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_s_axi_ctrl_bready</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_s_axi_ctrl_bready" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_USE_AXI&apos;)) = 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_ECC&apos;)) = &quot;ON&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_s_axi_ctrl_bresp</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">1</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_s_axi_ctrl_bresp" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_USE_AXI&apos;)) = 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_ECC&apos;)) = &quot;ON&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_s_axi_ctrl_arvalid</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_s_axi_ctrl_arvalid" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_USE_AXI&apos;)) = 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_ECC&apos;)) = &quot;ON&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_s_axi_ctrl_arready</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_s_axi_ctrl_arready" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_USE_AXI&apos;)) = 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_ECC&apos;)) = &quot;ON&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_s_axi_ctrl_araddr</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_C_S_AXI_CTRL_ADDR_WIDTH&apos;)) )- 1 ">31</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_s_axi_ctrl_araddr" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_USE_AXI&apos;)) = 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_ECC&apos;)) = &quot;ON&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_s_axi_ctrl_rvalid</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_s_axi_ctrl_rvalid" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_USE_AXI&apos;)) = 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_ECC&apos;)) = &quot;ON&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_s_axi_ctrl_rready</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_s_axi_ctrl_rready" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_USE_AXI&apos;)) = 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_ECC&apos;)) = &quot;ON&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_s_axi_ctrl_rdata</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_C_S_AXI_CTRL_DATA_WIDTH&apos;)) )- 1 ">31</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_s_axi_ctrl_rdata" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_USE_AXI&apos;)) = 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_ECC&apos;)) = &quot;ON&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_s_axi_ctrl_rresp</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">1</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_s_axi_ctrl_rresp" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_USE_AXI&apos;)) = 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_ECC&apos;)) = &quot;ON&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_s_axi_awid</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_C_S_AXI_ID_WIDTH&apos;)) )- 1 ">3</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
          <spirit:driver>
            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
          </spirit:driver>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_s_axi_awid" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_s_axi_awaddr</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_C_S_AXI_ADDR_WIDTH&apos;)) )- 1 ">31</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_s_axi_awaddr" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_s_axi_awlen</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">7</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_s_axi_awlen" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_s_axi_awsize</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">2</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_s_axi_awsize" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_s_axi_awburst</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">1</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_s_axi_awburst" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_s_axi_awlock</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
          <spirit:driver>
            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
          </spirit:driver>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_s_axi_awlock" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_s_axi_awcache</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">3</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
          <spirit:driver>
            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
          </spirit:driver>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_s_axi_awcache" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_s_axi_awprot</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">2</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
          <spirit:driver>
            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
          </spirit:driver>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_s_axi_awprot" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_s_axi_awqos</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">3</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
          <spirit:driver>
            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
          </spirit:driver>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_s_axi_awqos" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_s_axi_awvalid</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_s_axi_awvalid" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_s_axi_awready</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_s_axi_awready" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_s_axi_wdata</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_C_S_AXI_DATA_WIDTH&apos;)) )- 1 ">31</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_s_axi_wdata" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_s_axi_wstrb</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_C_S_AXI_DATA_WIDTH&apos;)) / 8 )- 1 ">3</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_s_axi_wstrb" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_s_axi_wlast</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_s_axi_wlast" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_s_axi_wvalid</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_s_axi_wvalid" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_s_axi_wready</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_s_axi_wready" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_s_axi_bready</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_s_axi_bready" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_s_axi_bid</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_C_S_AXI_ID_WIDTH&apos;)) )- 1 ">3</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_s_axi_bid" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_s_axi_bresp</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">1</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_s_axi_bresp" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_s_axi_bvalid</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_s_axi_bvalid" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_s_axi_arid</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_C_S_AXI_ID_WIDTH&apos;)) )- 1 ">3</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
          <spirit:driver>
            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
          </spirit:driver>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_s_axi_arid" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_s_axi_araddr</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_C_S_AXI_ADDR_WIDTH&apos;)) )- 1 ">31</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_s_axi_araddr" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_s_axi_arlen</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">7</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_s_axi_arlen" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_s_axi_arsize</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">2</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_s_axi_arsize" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_s_axi_arburst</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">1</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_s_axi_arburst" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_s_axi_arlock</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
          <spirit:driver>
            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
          </spirit:driver>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_s_axi_arlock" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_s_axi_arcache</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">3</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
          <spirit:driver>
            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
          </spirit:driver>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_s_axi_arcache" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_s_axi_arprot</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">2</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
          <spirit:driver>
            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
          </spirit:driver>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_s_axi_arprot" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_s_axi_arqos</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">3</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
          <spirit:driver>
            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
          </spirit:driver>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_s_axi_arqos" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_s_axi_arvalid</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_s_axi_arvalid" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_s_axi_arready</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_s_axi_arready" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_s_axi_rready</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_s_axi_rready" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_s_axi_rid</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_C_S_AXI_ID_WIDTH&apos;)) )- 1 ">3</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_s_axi_rid" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_s_axi_rdata</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_C_S_AXI_DATA_WIDTH&apos;)) )- 1 ">31</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_s_axi_rdata" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_s_axi_rresp</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">1</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_s_axi_rresp" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_s_axi_rlast</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_s_axi_rlast" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_s_axi_rvalid</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_s_axi_rvalid" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_interrupt</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_interrupt" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_USE_AXI&apos;)) = 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_ECC&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_mmcm_locked</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_mmcm_locked" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_qdriip_cq_p</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_QDRIIP_NUM_DEVICES&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_qdriip_cq_p" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_qdriip_cq_n</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_QDRIIP_NUM_DEVICES&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_qdriip_cq_n" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_qdriip_qvld</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_QDRIIP_NUM_DEVICES&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_qdriip_qvld" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_qdriip_q</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_QDRIIP_DATA_WIDTH&apos;)) )- 1 ">17</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_qdriip_q" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_qdriip_k_p</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_QDRIIP_NUM_DEVICES&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_qdriip_k_p" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_qdriip_k_n</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_QDRIIP_NUM_DEVICES&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_qdriip_k_n" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_qdriip_d</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_QDRIIP_DATA_WIDTH&apos;)) )- 1 ">17</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_qdriip_d" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_qdriip_sa</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_QDRIIP_ADDR_WIDTH&apos;)) )- 1 ">28</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_qdriip_sa" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_qdriip_w_n</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_qdriip_w_n" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_qdriip_r_n</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_qdriip_r_n" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_qdriip_bw_n</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_QDRIIP_BW_WIDTH&apos;)) )- 1 ">7</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_qdriip_bw_n" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_qdriip_dll_off_n</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_qdriip_dll_off_n" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_qdriip_dbg_pi_counter_read_val</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">4</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_qdriip_dbg_pi_counter_read_val" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_QDRIIP_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_qdriip_dbg_win_inc</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_qdriip_dbg_win_inc" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_QDRIIP_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_qdriip_dbg_win_dec</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_qdriip_dbg_win_dec" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_QDRIIP_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_qdriip_dbg_win_active</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_qdriip_dbg_win_active" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_QDRIIP_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_qdriip_dbg_win_current_byte</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">2</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_qdriip_dbg_win_current_byte" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_QDRIIP_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_qdriip_ila0_data</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">254</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_qdriip_ila0_data" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_QDRIIP_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_qdriip_ila0_trig</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">6</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_qdriip_ila0_trig" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_QDRIIP_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_qdriip_ila1_data</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">269</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_qdriip_ila1_data" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_QDRIIP_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_qdriip_ila1_trig</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">14</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_qdriip_ila1_trig" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_QDRIIP_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_qdriip_vio2_async_in</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">198</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_qdriip_vio2_async_in" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_QDRIIP_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_qdriip_vio2_sync_out</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">34</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_qdriip_vio2_sync_out" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_QDRIIP_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_app_wr_cmd0</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_app_wr_cmd0" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_app_wr_addr0</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_QDRIIP_ADDR_WIDTH&apos;)) )- 1 ">28</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_app_wr_addr0" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_app_wr_data0</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_QDRIIP_BURST_LEN&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_app_wr_data0" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_app_wr_bw_n0</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_QDRIIP_BURST_LEN&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_app_wr_bw_n0" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_app_rd_cmd0</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_app_rd_cmd0" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_app_rd_addr0</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_QDRIIP_ADDR_WIDTH&apos;)) )- 1 ">28</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_app_rd_addr0" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_app_rd_valid0</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_app_rd_valid0" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_app_rd_data0</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_QDRIIP_BURST_LEN&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_app_rd_data0" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_app_wr_cmd1</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_app_wr_cmd1" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_app_wr_addr1</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_QDRIIP_ADDR_WIDTH&apos;)) )- 1 ">28</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_app_wr_addr1" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_app_wr_data1</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" (( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_QDRIIP_DATA_WIDTH&apos;)) * 2 ))- 1 ">35</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_app_wr_data1" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_app_wr_bw_n1</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" (( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_QDRIIP_BW_WIDTH&apos;)) * 2 ))- 1 ">15</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_app_wr_bw_n1" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_app_rd_cmd1</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_app_rd_cmd1" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_app_rd_addr1</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_QDRIIP_ADDR_WIDTH&apos;)) )- 1 ">28</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_app_rd_addr1" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_app_rd_valid1</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_app_rd_valid1" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_app_rd_data1</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" (( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_QDRIIP_DATA_WIDTH&apos;)) * 2 ))- 1 ">35</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_app_rd_data1" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_clk</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_clk" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_rst_clk</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_rst_clk" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_qdriip_app_wr_cmd0</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_qdriip_app_wr_cmd0" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_qdriip_app_wr_addr0</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_QDRIIP_ADDR_WIDTH&apos;)) )- 1 ">28</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_qdriip_app_wr_addr0" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_qdriip_app_wr_data0</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_QDRIIP_BURST_LEN&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_qdriip_app_wr_data0" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_qdriip_app_wr_bw_n0</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_QDRIIP_BURST_LEN&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_qdriip_app_wr_bw_n0" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_qdriip_app_rd_cmd0</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_qdriip_app_rd_cmd0" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_qdriip_app_rd_addr0</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_QDRIIP_ADDR_WIDTH&apos;)) )- 1 ">28</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_qdriip_app_rd_addr0" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_qdriip_app_rd_valid0</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_qdriip_app_rd_valid0" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_qdriip_app_rd_data0</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_QDRIIP_BURST_LEN&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_qdriip_app_rd_data0" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_qdriip_app_wr_cmd1</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_qdriip_app_wr_cmd1" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_qdriip_app_wr_addr1</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_QDRIIP_ADDR_WIDTH&apos;)) )- 1 ">28</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_qdriip_app_wr_addr1" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_qdriip_app_wr_data1</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" (( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_QDRIIP_DATA_WIDTH&apos;)) * 2 ))- 1 ">35</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_qdriip_app_wr_data1" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_qdriip_app_wr_bw_n1</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" (( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_QDRIIP_BW_WIDTH&apos;)) * 2 ))- 1 ">15</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_qdriip_app_wr_bw_n1" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_qdriip_app_rd_cmd1</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_qdriip_app_rd_cmd1" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_qdriip_app_rd_addr1</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_QDRIIP_ADDR_WIDTH&apos;)) )- 1 ">28</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_qdriip_app_rd_addr1" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_qdriip_app_rd_valid1</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_qdriip_app_rd_valid1" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_qdriip_app_rd_data1</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" (( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_QDRIIP_DATA_WIDTH&apos;)) * 2 ))- 1 ">35</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_qdriip_app_rd_data1" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_qdriip_clk</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_qdriip_clk" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_qdriip_rst_clk</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_qdriip_rst_clk" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_rldii_qk_p</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_RLDII_QK_WIDTH&apos;)) )- 1 ">7</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_rldii_qk_p" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;RLDII&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_rldii_qk_n</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_RLDII_QK_WIDTH&apos;)) )- 1 ">7</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_rldii_qk_n" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;RLDII&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_rldii_dq</spirit:name>
        <spirit:wire>
          <spirit:direction>inout</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_RLDII_DATA_WIDTH&apos;)) )- 1 ">17</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_rldii_dq" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;RLDII&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_rldii_dm</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_RLDII_DM_WIDTH&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_rldii_dm" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;RLDII&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_rldii_dk_p</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_RLDII_DK_WIDTH&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_rldii_dk_p" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;RLDII&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_rldii_dk_n</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_RLDII_DK_WIDTH&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_rldii_dk_n" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;RLDII&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_rldii_ck_p</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_RLDII_NUM_DEVICES&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_rldii_ck_p" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;RLDII&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_rldii_ck_n</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_RLDII_NUM_DEVICES&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_rldii_ck_n" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;RLDII&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_rldii_cs_n</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_RLDII_NUM_DEVICES&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_rldii_cs_n" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;RLDII&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_rldii_a</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_RLDII_RLD_ADDR_WIDTH&apos;)) )- 1 ">28</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_rldii_a" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;RLDII&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_rldii_ba</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_RLDII_BANK_WIDTH&apos;)) )- 1 ">1</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_rldii_ba" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;RLDII&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_rldii_qvld</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_RLDII_QVLD_WIDTH&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_rldii_qvld" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;RLDII&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_rldii_we_n</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_rldii_we_n" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;RLDII&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_rldii_ref_n</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_rldii_ref_n" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;RLDII&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_rldii_reset_n</spirit:name>
        <spirit:displayName>reset to memory device</spirit:displayName>
        <spirit:description>reset to memory device</spirit:description>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_rldii_reset_n" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;RLDII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;RLDIII&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_rldii_dbg_pi_tap_cnt</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">4</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_rldii_dbg_pi_tap_cnt" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;RLDII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_RLDII_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_rldii_dbg_win_inc</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_rldii_dbg_win_inc" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;RLDII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_RLDII_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_rldii_dbg_win_dec</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_rldii_dbg_win_dec" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;RLDII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_RLDII_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_rldii_dbg_win_active</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_rldii_dbg_win_active" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;RLDII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_RLDII_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_rldii_dbg_win_current_byte</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">2</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_rldii_dbg_win_current_byte" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;RLDII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_RLDII_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_rldii_ila0_data</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">638</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_rldii_ila0_data" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;RLDII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_RLDII_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_rldii_ila0_trig</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">30</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_rldii_ila0_trig" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;RLDII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_RLDII_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_rldii_vio1_async_in</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">254</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_rldii_vio1_async_in" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;RLDII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_RLDII_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_rldii_vio1_async_out</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">62</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_rldii_vio1_async_out" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;RLDII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_RLDII_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_rldii_vio1_sync_out</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">62</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_rldii_vio1_sync_out" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;RLDII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_RLDII_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_rldiii_qk_p</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_RLDIII_QK_WIDTH&apos;)) )- 1 ">7</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_rldiii_qk_p" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;RLDIII&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_rldiii_qk_n</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_RLDIII_QK_WIDTH&apos;)) )- 1 ">7</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_rldiii_qk_n" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;RLDIII&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_rldiii_dq</spirit:name>
        <spirit:wire>
          <spirit:direction>inout</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_RLDIII_DATA_WIDTH&apos;)) )- 1 ">17</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_rldiii_dq" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;RLDIII&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_rldiii_dm</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_RLDIII_DM_WIDTH&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_rldiii_dm" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;RLDIII&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_rldiii_dk_p</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_RLDIII_DK_WIDTH&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_rldiii_dk_p" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;RLDIII&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_rldiii_dk_n</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_RLDIII_DK_WIDTH&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_rldiii_dk_n" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;RLDIII&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_rldiii_ck_p</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_RLDIII_NUM_DEVICES&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_rldiii_ck_p" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;RLDIII&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_rldiii_ck_n</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_RLDIII_NUM_DEVICES&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_rldiii_ck_n" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;RLDIII&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_rldiii_cs_n</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_RLDIII_NUM_DEVICES&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_rldiii_cs_n" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;RLDIII&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_rldiii_a</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_RLDIII_RLD_ADDR_WIDTH&apos;)) )- 1 ">28</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_rldiii_a" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;RLDIII&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_rldiii_ba</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_RLDIII_BANK_WIDTH&apos;)) )- 1 ">1</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_rldiii_ba" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;RLDIII&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_rldiii_qvld</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_RLDIII_QVLD_WIDTH&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_rldiii_qvld" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;RLDIII&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_rldiii_we_n</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_rldiii_we_n" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;RLDIII&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_rldiii_ref_n</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_rldiii_ref_n" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;RLDIII&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_rldiii_reset_n</spirit:name>
        <spirit:displayName>reset to memory device</spirit:displayName>
        <spirit:description>reset to memory device</spirit:description>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_rldiii_reset_n" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;RLDIII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;RLDIII&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_dbg_pi_tap_cnt</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">4</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_dbg_pi_tap_cnt" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;RLDIII&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;RLDII&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_rldiii_dbg_pi_tap_cnt</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">4</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_rldiii_dbg_pi_tap_cnt" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;RLDIII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_RLDIII_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_rldiii_dbg_win_inc</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_rldiii_dbg_win_inc" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;RLDIII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_RLDIII_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_rldiii_dbg_win_dec</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_rldiii_dbg_win_dec" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;RLDIII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_RLDIII_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_rldiii_dbg_win_active</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_rldiii_dbg_win_active" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;RLDIII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_RLDIII_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_rldiii_dbg_win_current_byte</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">2</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_rldiii_dbg_win_current_byte" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;RLDIII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_RLDIII_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_rldiii_ila0_data</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">638</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_rldiii_ila0_data" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;RLDIII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_RLDIII_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_rldiii_ila0_trig</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">30</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_rldiii_ila0_trig" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;RLDIII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_RLDIII_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_rldiii_vio1_async_in</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">254</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_rldiii_vio1_async_in" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;RLDIII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_RLDIII_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_rldiii_vio1_async_out</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">62</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_rldiii_vio1_async_out" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;RLDIII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_RLDIII_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_rldiii_vio1_sync_out</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">62</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_rldiii_vio1_sync_out" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;RLDIII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_RLDIII_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_dbg_win_inc</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_dbg_win_inc" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;RLDIII&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;RLDII&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_dbg_win_dec</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_dbg_win_dec" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;RLDIII&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;RLDII&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_dbg_win_active</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_dbg_win_active" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;RLDIII&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;RLDII&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_dbg_win_current_byte</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">2</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_dbg_win_current_byte" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;RLDIII&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;RLDII&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_dbg_pi_counter_read_val</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">4</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_dbg_pi_counter_read_val" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;DDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_user_cmd_en</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_user_cmd_en" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;RLDII&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;RLDIII&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_user_cmd</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_RLDX_CMD_PER_CLK&apos;)) * 2 )- 1 ">1</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_user_cmd" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;RLDII&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;RLDIII&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_user_addr</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_RLDX_ADDR_WIDTH&apos;)) * spirit:decode(id(&apos;MODELPARAM_VALUE.C3_RLDX_CMD_PER_CLK&apos;)) )- 1 ">28</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_user_addr" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;RLDII&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;RLDIII&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_user_ba</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_RLDX_BANK_WIDTH&apos;)) * spirit:decode(id(&apos;MODELPARAM_VALUE.C3_RLDX_CMD_PER_CLK&apos;)) )- 1 ">1</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_user_ba" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;RLDII&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;RLDIII&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_user_wr_en</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_user_wr_en" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;RLDII&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;RLDIII&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_user_wr_data</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_RLDX_DATA_WIDTH&apos;)) * 2 * spirit:decode(id(&apos;MODELPARAM_VALUE.C3_RLDX_nCK_PER_CLK&apos;)) )- 1 ">35</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_user_wr_data" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;RLDII&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;RLDIII&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_user_wr_dm</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_RLDX_DM_WIDTH&apos;)) * 2 * spirit:decode(id(&apos;MODELPARAM_VALUE.C3_RLDX_nCK_PER_CLK&apos;)) )- 1 ">1</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_user_wr_dm" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;RLDII&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;RLDIII&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_user_afifo_empty</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_user_afifo_empty" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;RLDII&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;RLDIII&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_user_afifo_full</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_user_afifo_full" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;RLDII&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;RLDIII&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_user_afifo_aempty</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_user_afifo_aempty" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;RLDII&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;RLDIII&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_user_afifo_afull</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_user_afifo_afull" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;RLDII&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;RLDIII&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_user_wdfifo_empty</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_user_wdfifo_empty" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;RLDII&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;RLDIII&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_user_wdfifo_full</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_user_wdfifo_full" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;RLDII&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;RLDIII&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_user_wdfifo_aempty</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_user_wdfifo_aempty" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;RLDII&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;RLDIII&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_user_wdfifo_afull</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_user_wdfifo_afull" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;RLDII&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;RLDIII&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_user_rd_valid</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_RLDX_nCK_PER_CLK&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_user_rd_valid" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;RLDII&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;RLDIII&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_mem_ck_lock_complete</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_mem_ck_lock_complete" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;RLDII&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;RLDIII&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_user_rd_data</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_RLDX_DATA_WIDTH&apos;)) * 2 * spirit:decode(id(&apos;MODELPARAM_VALUE.C3_RLDX_nCK_PER_CLK&apos;)) )- 1 ">35</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_user_rd_data" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;RLDII&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;RLDIII&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_rldii_user_cmd_en</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_rldii_user_cmd_en" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;RLDII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_rldii_user_cmd</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_RLDII_CMD_PER_CLK&apos;)) * 2 )- 1 ">1</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_rldii_user_cmd" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;RLDII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_rldii_user_addr</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_RLDII_ADDR_WIDTH&apos;)) * spirit:decode(id(&apos;MODELPARAM_VALUE.C3_RLDII_CMD_PER_CLK&apos;)) )- 1 ">28</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_rldii_user_addr" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;RLDII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_rldii_user_ba</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_RLDII_BANK_WIDTH&apos;)) * spirit:decode(id(&apos;MODELPARAM_VALUE.C3_RLDII_CMD_PER_CLK&apos;)) )- 1 ">1</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_rldii_user_ba" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;RLDII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_rldii_user_wr_en</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_rldii_user_wr_en" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;RLDII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_rldii_user_wr_data</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_RLDII_DATA_WIDTH&apos;)) * 2 * spirit:decode(id(&apos;MODELPARAM_VALUE.C3_RLDII_nCK_PER_CLK&apos;)) )- 1 ">35</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_rldii_user_wr_data" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;RLDII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_rldii_user_wr_dm</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_RLDII_DM_WIDTH&apos;)) * 2 * spirit:decode(id(&apos;MODELPARAM_VALUE.C3_RLDII_nCK_PER_CLK&apos;)) )- 1 ">1</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_rldii_user_wr_dm" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;RLDII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_rldii_user_afifo_empty</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_rldii_user_afifo_empty" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;RLDII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_rldii_user_afifo_full</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_rldii_user_afifo_full" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;RLDII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_rldii_user_afifo_aempty</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_rldii_user_afifo_aempty" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;RLDII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_rldii_user_afifo_afull</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_rldii_user_afifo_afull" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;RLDII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_rldii_user_wdfifo_empty</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_rldii_user_wdfifo_empty" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;RLDII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_rldii_user_wdfifo_full</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_rldii_user_wdfifo_full" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;RLDII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_rldii_user_wdfifo_aempty</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_rldii_user_wdfifo_aempty" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;RLDII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_rldii_user_wdfifo_afull</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_rldii_user_wdfifo_afull" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;RLDII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_rldii_user_rd_valid</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_RLDII_nCK_PER_CLK&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_rldii_user_rd_valid" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;RLDII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_rldii_mem_ck_lock_complete</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_rldii_mem_ck_lock_complete" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;RLDII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_rldii_user_rd_data</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_RLDII_DATA_WIDTH&apos;)) * 2 * spirit:decode(id(&apos;MODELPARAM_VALUE.C3_RLDII_nCK_PER_CLK&apos;)) )- 1 ">35</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_rldii_user_rd_data" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;RLDII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_rldiii_user_cmd_en</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_rldiii_user_cmd_en" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;RLDIII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_rldiii_user_cmd</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_RLDIII_CMD_PER_CLK&apos;)) * 2 )- 1 ">1</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_rldiii_user_cmd" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;RLDIII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_rldiii_user_addr</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_RLDIII_ADDR_WIDTH&apos;)) * spirit:decode(id(&apos;MODELPARAM_VALUE.C3_RLDIII_CMD_PER_CLK&apos;)) )- 1 ">28</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_rldiii_user_addr" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;RLDIII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_rldiii_user_ba</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_RLDIII_BANK_WIDTH&apos;)) * spirit:decode(id(&apos;MODELPARAM_VALUE.C3_RLDIII_CMD_PER_CLK&apos;)) )- 1 ">1</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_rldiii_user_ba" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;RLDIII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_rldiii_user_wr_en</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_rldiii_user_wr_en" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;RLDIII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_rldiii_user_wr_data</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_RLDIII_DATA_WIDTH&apos;)) * 2 * spirit:decode(id(&apos;MODELPARAM_VALUE.C3_RLDIII_nCK_PER_CLK&apos;)) )- 1 ">35</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_rldiii_user_wr_data" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;RLDIII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_rldiii_user_wr_dm</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_RLDIII_DM_WIDTH&apos;)) * 2 * spirit:decode(id(&apos;MODELPARAM_VALUE.C3_RLDIII_nCK_PER_CLK&apos;)) )- 1 ">1</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_rldiii_user_wr_dm" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;RLDIII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_rldiii_user_afifo_empty</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_rldiii_user_afifo_empty" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;RLDIII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_rldiii_user_afifo_full</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_rldiii_user_afifo_full" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;RLDIII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_rldiii_user_afifo_aempty</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_rldiii_user_afifo_aempty" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;RLDIII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_rldiii_user_afifo_afull</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_rldiii_user_afifo_afull" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;RLDIII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_rldiii_user_wdfifo_empty</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_rldiii_user_wdfifo_empty" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;RLDIII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_rldiii_user_wdfifo_full</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_rldiii_user_wdfifo_full" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;RLDIII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_rldiii_user_wdfifo_aempty</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_rldiii_user_wdfifo_aempty" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;RLDIII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_rldiii_user_wdfifo_afull</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_rldiii_user_wdfifo_afull" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;RLDIII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_rldiii_user_rd_valid</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_RLDIII_nCK_PER_CLK&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_rldiii_user_rd_valid" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;RLDIII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_rldiii_mem_ck_lock_complete</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_rldiii_mem_ck_lock_complete" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;RLDIII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_rldiii_user_rd_data</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_RLDIII_DATA_WIDTH&apos;)) * 2 * spirit:decode(id(&apos;MODELPARAM_VALUE.C3_RLDIII_nCK_PER_CLK&apos;)) )- 1 ">35</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_rldiii_user_rd_data" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;RLDIII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_sys_clk_p</spirit:name>
        <spirit:displayName>Clock P</spirit:displayName>
        <spirit:description>Clock P</spirit:description>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_sys_clk_p" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_SYSCLK_TYPE&apos;)) = &quot;DIFF&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_IS_CLK_SHARED&apos;)) = &quot;FALSE&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_sys_clk_n</spirit:name>
        <spirit:displayName>Clock P</spirit:displayName>
        <spirit:description>Clock P</spirit:description>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_sys_clk_n" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_SYSCLK_TYPE&apos;)) = &quot;DIFF&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_IS_CLK_SHARED&apos;)) = &quot;FALSE&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_sys_clk_i</spirit:name>
        <spirit:displayName>Clock P</spirit:displayName>
        <spirit:description>Clock P</spirit:description>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_sys_clk_i" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_SYSCLK_TYPE&apos;)) != &quot;DIFF&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C3_IS_CLK_SHARED&apos;)) = &quot;FALSE&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_init_calib_complete</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_init_calib_complete" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c3_aresetn</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c3_aresetn" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 3 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C3_MEM_TYPE&apos;)) = &quot;DDR2&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_ddr3_dq</spirit:name>
        <spirit:displayName>Data</spirit:displayName>
        <spirit:description>Data</spirit:description>
        <spirit:wire>
          <spirit:direction>inout</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_DDR3_DQ_WIDTH&apos;)) )- 1 ">7</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_ddr3_dq" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;DDR3&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_ddr3_dqs_p</spirit:name>
        <spirit:displayName>Data Strobe</spirit:displayName>
        <spirit:description>Data Strobe</spirit:description>
        <spirit:wire>
          <spirit:direction>inout</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_DDR3_DQS_WIDTH&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_ddr3_dqs_p" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;DDR3&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_ddr3_dqs_n</spirit:name>
        <spirit:displayName>Data Strobe</spirit:displayName>
        <spirit:description>Data Strobe</spirit:description>
        <spirit:wire>
          <spirit:direction>inout</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_DDR3_DQS_WIDTH&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_ddr3_dqs_n" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;DDR3&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_ddr3_addr</spirit:name>
        <spirit:displayName>Address</spirit:displayName>
        <spirit:description>Address</spirit:description>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_DDR3_ROW_WIDTH&apos;)) )- 1 ">13</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_ddr3_addr" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;DDR3&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_ddr3_ba</spirit:name>
        <spirit:displayName>Bank Address</spirit:displayName>
        <spirit:description>Bank Address</spirit:description>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_DDR3_BANK_WIDTH&apos;)) )- 1 ">2</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_ddr3_ba" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;DDR3&quot; and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;DDR2&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_ddr3_ras_n</spirit:name>
        <spirit:displayName>row address strobe</spirit:displayName>
        <spirit:description>row address strobe</spirit:description>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_ddr3_ras_n" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;DDR3&quot; and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;DDR2&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_ddr3_cas_n</spirit:name>
        <spirit:displayName>column address strobe</spirit:displayName>
        <spirit:description>column address strobe</spirit:description>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_ddr3_cas_n" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;DDR3&quot; and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;DDR2&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_ddr3_we_n</spirit:name>
        <spirit:displayName>write enable</spirit:displayName>
        <spirit:description>write enable</spirit:description>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_ddr3_we_n" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;DDR3&quot; and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;DDR2&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_ddr3_reset_n</spirit:name>
        <spirit:displayName>reset to memory device</spirit:displayName>
        <spirit:description>reset to memory device</spirit:description>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_ddr3_reset_n" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;DDR3&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_ddr3_ck_p</spirit:name>
        <spirit:displayName>clock to memory device</spirit:displayName>
        <spirit:description>clock to memory device</spirit:description>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_DDR3_CK_WIDTH&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_ddr3_ck_p" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;DDR3&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_ddr3_ck_n</spirit:name>
        <spirit:displayName>clock to memory device</spirit:displayName>
        <spirit:description>clock to memory device</spirit:description>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_DDR3_CK_WIDTH&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_ddr3_ck_n" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;DDR3&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_ddr3_cke</spirit:name>
        <spirit:displayName>clock enable</spirit:displayName>
        <spirit:description>clock enable</spirit:description>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_DDR3_CKE_WIDTH&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_ddr3_cke" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;DDR3&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_ddr3_cs_n</spirit:name>
        <spirit:displayName>chip select</spirit:displayName>
        <spirit:description>chip select</spirit:description>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_DDR3_CS_WIDTH&apos;)) * spirit:decode(id(&apos;MODELPARAM_VALUE.C4_DDR3_nCS_PER_RANK&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_ddr3_cs_n" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_DDR3_USE_CS_PORT&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_ddr3_dm</spirit:name>
        <spirit:displayName>data mask</spirit:displayName>
        <spirit:description>data mask</spirit:description>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_DDR3_DM_WIDTH&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_ddr3_dm" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_DDR3_USE_DM_PORT&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_ddr3_odt</spirit:name>
        <spirit:displayName>on die termination</spirit:displayName>
        <spirit:description>on die termination</spirit:description>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_DDR3_ODT_WIDTH&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_ddr3_odt" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;DDR3&quot; and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;DDR2&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_DDR3_USE_ODT_PORT&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_ddr3_parity</spirit:name>
        <spirit:displayName>parity bit</spirit:displayName>
        <spirit:description>parity bit</spirit:description>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_ddr3_parity" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_DDR3_REG_CTRL&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_ddr3_dbg_pi_counter_read_val</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">4</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_ddr3_dbg_pi_counter_read_val" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_DDR3_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_ddr3_dbg_byte_sel</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_DDR3_DQS_CNT_WIDTH&apos;)) + 1 )- 1 ">1</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_ddr3_dbg_byte_sel" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_DDR3_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_ddr3_dbg_sel_pi_incdec</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_ddr3_dbg_sel_pi_incdec" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_DDR3_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_ddr3_dbg_pi_f_inc</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_ddr3_dbg_pi_f_inc" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_DDR3_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_ddr3_dbg_pi_f_dec</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_ddr3_dbg_pi_f_dec" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_DDR3_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_ddr3_dbg_sel_po_incdec</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_ddr3_dbg_sel_po_incdec" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_DDR3_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_ddr3_dbg_po_f_inc</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_ddr3_dbg_po_f_inc" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_DDR3_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_ddr3_dbg_po_f_stg23_sel</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_ddr3_dbg_po_f_stg23_sel" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_DDR3_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_ddr3_dbg_po_f_dec</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_ddr3_dbg_po_f_dec" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_DDR3_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_ddr3_dbg_po_counter_read_val</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">7</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_ddr3_dbg_po_counter_read_val" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_DDR3_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_ddr3_ila_wrpath</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">254</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_ddr3_ila_wrpath" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_DDR3_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_ddr3_ila_rdpath</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">1022</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_ddr3_ila_rdpath" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_DDR3_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_ddr3_ila_basic</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">126</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_ddr3_ila_basic" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_DDR3_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_ddr3_vio_sync_out</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">34</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_ddr3_vio_sync_out" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_DDR3_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_ddr2_dq</spirit:name>
        <spirit:displayName>Data</spirit:displayName>
        <spirit:description>Data</spirit:description>
        <spirit:wire>
          <spirit:direction>inout</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_DDR2_DQ_WIDTH&apos;)) )- 1 ">7</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_ddr2_dq" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;DDR2&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_ddr2_dqs_p</spirit:name>
        <spirit:displayName>Data Strobe</spirit:displayName>
        <spirit:description>Data Strobe</spirit:description>
        <spirit:wire>
          <spirit:direction>inout</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_DDR2_DQS_WIDTH&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_ddr2_dqs_p" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;DDR2&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_ddr2_dqs_n</spirit:name>
        <spirit:displayName>Data Strobe</spirit:displayName>
        <spirit:description>Data Strobe</spirit:description>
        <spirit:wire>
          <spirit:direction>inout</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_DDR2_DQS_WIDTH&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_ddr2_dqs_n" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;DDR2&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_ddr2_addr</spirit:name>
        <spirit:displayName>Address</spirit:displayName>
        <spirit:description>Address</spirit:description>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_DDR2_ROW_WIDTH&apos;)) )- 1 ">13</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_ddr2_addr" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;DDR2&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_ddr2_ba</spirit:name>
        <spirit:displayName>Bank Address</spirit:displayName>
        <spirit:description>Bank Address</spirit:description>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_DDR2_BANK_WIDTH&apos;)) )- 1 ">2</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_ddr2_ba" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;DDR2&quot; and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;DDR2&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_ddr2_ras_n</spirit:name>
        <spirit:displayName>row address strobe</spirit:displayName>
        <spirit:description>row address strobe</spirit:description>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_ddr2_ras_n" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;DDR2&quot; and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;DDR2&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_ddr2_cas_n</spirit:name>
        <spirit:displayName>column address strobe</spirit:displayName>
        <spirit:description>column address strobe</spirit:description>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_ddr2_cas_n" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;DDR2&quot; and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;DDR2&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_ddr2_we_n</spirit:name>
        <spirit:displayName>write enable</spirit:displayName>
        <spirit:description>write enable</spirit:description>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_ddr2_we_n" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;DDR2&quot; and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;DDR2&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_ddr2_reset_n</spirit:name>
        <spirit:displayName>reset to memory device</spirit:displayName>
        <spirit:description>reset to memory device</spirit:description>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_ddr2_reset_n" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;DDR3&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_ddr2_ck_p</spirit:name>
        <spirit:displayName>clock to memory device</spirit:displayName>
        <spirit:description>clock to memory device</spirit:description>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_DDR2_CK_WIDTH&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_ddr2_ck_p" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;DDR2&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_ddr2_ck_n</spirit:name>
        <spirit:displayName>clock to memory device</spirit:displayName>
        <spirit:description>clock to memory device</spirit:description>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_DDR2_CK_WIDTH&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_ddr2_ck_n" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;DDR2&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_ddr2_cke</spirit:name>
        <spirit:displayName>clock enable</spirit:displayName>
        <spirit:description>clock enable</spirit:description>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_DDR2_CKE_WIDTH&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_ddr2_cke" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;DDR2&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_ddr2_cs_n</spirit:name>
        <spirit:displayName>chip select</spirit:displayName>
        <spirit:description>chip select</spirit:description>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_DDR2_CS_WIDTH&apos;)) * spirit:decode(id(&apos;MODELPARAM_VALUE.C4_DDR2_nCS_PER_RANK&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_ddr2_cs_n" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_DDR2_USE_CS_PORT&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_ddr2_dm</spirit:name>
        <spirit:displayName>data mask</spirit:displayName>
        <spirit:description>data mask</spirit:description>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_DDR2_DM_WIDTH&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_ddr2_dm" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_DDR2_USE_DM_PORT&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_ddr2_odt</spirit:name>
        <spirit:displayName>on die termination</spirit:displayName>
        <spirit:description>on die termination</spirit:description>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_DDR2_ODT_WIDTH&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_ddr2_odt" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;DDR2&quot; and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;DDR2&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_DDR2_USE_ODT_PORT&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_ddr2_parity</spirit:name>
        <spirit:displayName>parity bit</spirit:displayName>
        <spirit:description>parity bit</spirit:description>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_ddr2_parity" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_DDR2_REG_CTRL&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_ddr2_dbg_pi_counter_read_val</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">4</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_ddr2_dbg_pi_counter_read_val" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_DDR2_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_ddr2_dbg_byte_sel</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_DDR2_DQS_CNT_WIDTH&apos;)) + 1 )- 1 ">1</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_ddr2_dbg_byte_sel" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_DDR2_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_ddr2_dbg_sel_pi_incdec</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_ddr2_dbg_sel_pi_incdec" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_DDR2_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_ddr2_dbg_pi_f_inc</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_ddr2_dbg_pi_f_inc" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_DDR2_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_ddr2_dbg_pi_f_dec</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_ddr2_dbg_pi_f_dec" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_DDR2_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_ddr2_dbg_sel_po_incdec</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_ddr2_dbg_sel_po_incdec" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_DDR2_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_ddr2_dbg_po_f_inc</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_ddr2_dbg_po_f_inc" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_DDR2_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_ddr2_dbg_po_f_stg23_sel</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_ddr2_dbg_po_f_stg23_sel" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_DDR2_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_ddr2_dbg_po_f_dec</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_ddr2_dbg_po_f_dec" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_DDR2_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_ddr2_dbg_po_counter_read_val</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">7</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_ddr2_dbg_po_counter_read_val" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_DDR2_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_ddr2_ila_wrpath</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">254</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_ddr2_ila_wrpath" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_DDR2_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_ddr2_ila_rdpath</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">1022</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_ddr2_ila_rdpath" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_DDR2_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_ddr2_ila_basic</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">126</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_ddr2_ila_basic" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_DDR2_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_ddr2_vio_sync_out</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">34</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_ddr2_vio_sync_out" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_DDR2_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_lpddr2_dq</spirit:name>
        <spirit:displayName>Data</spirit:displayName>
        <spirit:description>Data</spirit:description>
        <spirit:wire>
          <spirit:direction>inout</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_LPDDR2_DQ_WIDTH&apos;)) )- 1 ">7</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_lpddr2_dq" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_lpddr2_dqs_p</spirit:name>
        <spirit:displayName>Data Strobe</spirit:displayName>
        <spirit:description>Data Strobe</spirit:description>
        <spirit:wire>
          <spirit:direction>inout</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_LPDDR2_DQS_WIDTH&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_lpddr2_dqs_p" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_lpddr2_dqs_n</spirit:name>
        <spirit:displayName>Data Strobe</spirit:displayName>
        <spirit:description>Data Strobe</spirit:description>
        <spirit:wire>
          <spirit:direction>inout</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_LPDDR2_DQS_WIDTH&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_lpddr2_dqs_n" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_lpddr2_ca</spirit:name>
        <spirit:displayName>Address</spirit:displayName>
        <spirit:description>Address</spirit:description>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">9</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_lpddr2_ca" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_lpddr2_ck_p</spirit:name>
        <spirit:displayName>clock to memory device</spirit:displayName>
        <spirit:description>clock to memory device</spirit:description>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_LPDDR2_CK_WIDTH&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_lpddr2_ck_p" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_lpddr2_ck_n</spirit:name>
        <spirit:displayName>clock to memory device</spirit:displayName>
        <spirit:description>clock to memory device</spirit:description>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_LPDDR2_CK_WIDTH&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_lpddr2_ck_n" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_lpddr2_cke</spirit:name>
        <spirit:displayName>clock enable</spirit:displayName>
        <spirit:description>clock enable</spirit:description>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_LPDDR2_CKE_WIDTH&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_lpddr2_cke" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_lpddr2_cs_n</spirit:name>
        <spirit:displayName>chip select</spirit:displayName>
        <spirit:description>chip select</spirit:description>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_LPDDR2_CS_WIDTH&apos;)) * spirit:decode(id(&apos;MODELPARAM_VALUE.C4_LPDDR2_nCS_PER_RANK&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_lpddr2_cs_n" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_LPDDR2_USE_CS_PORT&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_lpddr2_dm</spirit:name>
        <spirit:displayName>data mask</spirit:displayName>
        <spirit:description>data mask</spirit:description>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_LPDDR2_DM_WIDTH&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_lpddr2_dm" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_LPDDR2_USE_DM_PORT&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_lpddr2_parity</spirit:name>
        <spirit:displayName>parity bit</spirit:displayName>
        <spirit:description>parity bit</spirit:description>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_lpddr2_parity" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_LPDDR2_REG_CTRL&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_lpddr2_dbg_pi_counter_read_val</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">4</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_lpddr2_dbg_pi_counter_read_val" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_LPDDR2_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_lpddr2_dbg_byte_sel</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_LPDDR2_DQS_CNT_WIDTH&apos;)) + 1 )- 1 ">1</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_lpddr2_dbg_byte_sel" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_LPDDR2_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_lpddr2_dbg_sel_pi_incdec</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_lpddr2_dbg_sel_pi_incdec" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_LPDDR2_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_lpddr2_dbg_pi_f_inc</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_lpddr2_dbg_pi_f_inc" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_LPDDR2_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_lpddr2_dbg_pi_f_dec</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_lpddr2_dbg_pi_f_dec" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_LPDDR2_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_lpddr2_dbg_sel_po_incdec</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_lpddr2_dbg_sel_po_incdec" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_LPDDR2_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_lpddr2_dbg_po_f_inc</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_lpddr2_dbg_po_f_inc" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_LPDDR2_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_lpddr2_dbg_po_f_stg23_sel</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_lpddr2_dbg_po_f_stg23_sel" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_LPDDR2_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_lpddr2_dbg_po_f_dec</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_lpddr2_dbg_po_f_dec" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_LPDDR2_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_lpddr2_dbg_po_counter_read_val</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">7</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_lpddr2_dbg_po_counter_read_val" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_LPDDR2_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_lpddr2_ila_wrpath</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">254</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_lpddr2_ila_wrpath" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_LPDDR2_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_lpddr2_ila_rdpath</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">1022</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_lpddr2_ila_rdpath" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_LPDDR2_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_lpddr2_ila_basic</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">126</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_lpddr2_ila_basic" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_LPDDR2_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_lpddr2_vio_sync_out</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">34</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_lpddr2_vio_sync_out" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_LPDDR2_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_dbg_byte_sel</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_DQS_CNT_WIDTH&apos;)) + 1 )- 1 ">1</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_dbg_byte_sel" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;DDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_dbg_sel_pi_incdec</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_dbg_sel_pi_incdec" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;DDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_dbg_pi_f_inc</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_dbg_pi_f_inc" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;DDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_dbg_pi_f_dec</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_dbg_pi_f_dec" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;DDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_dbg_sel_po_incdec</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_dbg_sel_po_incdec" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;DDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_dbg_po_f_inc</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_dbg_po_f_inc" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;DDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_dbg_po_f_stg23_sel</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_dbg_po_f_stg23_sel" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;DDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_dbg_po_f_dec</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_dbg_po_f_dec" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;DDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_dbg_po_counter_read_val</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">7</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_dbg_po_counter_read_val" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;DDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_app_addr</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_DDRX_ADDR_WIDTH&apos;)) )- 1 ">7</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_app_addr" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;DDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_app_cmd</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">2</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_app_cmd" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;DDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_app_en</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_app_en" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;DDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_app_wdf_data</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_DDRX_nCK_PER_CLK&apos;)) * 2 * spirit:decode(id(&apos;MODELPARAM_VALUE.C4_DDRX_DATA_WIDTH&apos;)) )- 1 ">31</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_app_wdf_data" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;DDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_app_wdf_end</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_app_wdf_end" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;DDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_app_wdf_mask</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_DDRX_nCK_PER_CLK&apos;)) * 2 * spirit:decode(id(&apos;MODELPARAM_VALUE.C4_DDRX_DATA_WIDTH&apos;)) / 8 )- 1 ">3</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_app_wdf_mask" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;DDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_app_wdf_wren</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_app_wdf_wren" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;DDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_app_correct_en_i</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_app_correct_en_i" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;DDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_ECC&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_app_rd_data</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_DDRX_nCK_PER_CLK&apos;)) * 2 * spirit:decode(id(&apos;MODELPARAM_VALUE.C4_DDRX_DATA_WIDTH&apos;)) )- 1 ">31</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_app_rd_data" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;DDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_app_rd_data_end</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_app_rd_data_end" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;DDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_app_rd_data_valid</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_app_rd_data_valid" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;DDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_app_rdy</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_app_rdy" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;DDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_app_wdf_rdy</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_app_wdf_rdy" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;DDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_app_sr_req</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_app_sr_req" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;DDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_app_sr_active</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_app_sr_active" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;DDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_app_ref_req</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_app_ref_req" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;DDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_app_ref_ack</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_app_ref_ack" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;DDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_app_zq_req</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_app_zq_req" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;DDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_app_zq_ack</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_app_zq_ack" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;DDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_app_raw_not_ecc</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( 2 * spirit:decode(id(&apos;MODELPARAM_VALUE.C4_DDRX_nCK_PER_CLK&apos;)) )- 1 ">3</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_app_raw_not_ecc" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;DDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_ECC&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_app_ecc_multiple_err</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( 2 * spirit:decode(id(&apos;MODELPARAM_VALUE.C4_DDRX_nCK_PER_CLK&apos;)) )- 1 ">3</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_app_ecc_multiple_err" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;DDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_ECC&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_ddr3_app_addr</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_DDR3_ADDR_WIDTH&apos;)) )- 1 ">7</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_ddr3_app_addr" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_ddr3_app_cmd</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">2</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_ddr3_app_cmd" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_ddr3_app_en</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_ddr3_app_en" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_ddr3_app_wdf_data</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_DDR3_nCK_PER_CLK&apos;)) * 2 * spirit:decode(id(&apos;MODELPARAM_VALUE.C4_DDR3_DATA_WIDTH&apos;)) )- 1 ">31</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_ddr3_app_wdf_data" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_ddr3_app_wdf_end</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_ddr3_app_wdf_end" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_ddr3_app_wdf_mask</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_DDR3_nCK_PER_CLK&apos;)) * 2 * spirit:decode(id(&apos;MODELPARAM_VALUE.C4_DDR3_DATA_WIDTH&apos;)) / 8 )- 1 ">3</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_ddr3_app_wdf_mask" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_ddr3_app_wdf_wren</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_ddr3_app_wdf_wren" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_ddr3_app_correct_en_i</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_ddr3_app_correct_en_i" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_ECC&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_ddr3_app_rd_data</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_DDR3_nCK_PER_CLK&apos;)) * 2 * spirit:decode(id(&apos;MODELPARAM_VALUE.C4_DDR3_DATA_WIDTH&apos;)) )- 1 ">31</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_ddr3_app_rd_data" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_ddr3_app_rd_data_end</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_ddr3_app_rd_data_end" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_ddr3_app_rd_data_valid</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_ddr3_app_rd_data_valid" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_ddr3_app_rdy</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_ddr3_app_rdy" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_ddr3_app_wdf_rdy</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_ddr3_app_wdf_rdy" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_ddr3_app_sr_req</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_ddr3_app_sr_req" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_ddr3_app_sr_active</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_ddr3_app_sr_active" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_ddr3_app_ref_req</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_ddr3_app_ref_req" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_ddr3_app_ref_ack</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_ddr3_app_ref_ack" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_ddr3_app_zq_req</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_ddr3_app_zq_req" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_ddr3_app_zq_ack</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_ddr3_app_zq_ack" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_ddr3_app_raw_not_ecc</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( 2 * spirit:decode(id(&apos;MODELPARAM_VALUE.C4_DDR3_nCK_PER_CLK&apos;)) )- 1 ">3</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_ddr3_app_raw_not_ecc" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_ECC&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_ddr3_app_ecc_multiple_err</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( 2 * spirit:decode(id(&apos;MODELPARAM_VALUE.C4_DDR3_nCK_PER_CLK&apos;)) )- 1 ">3</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_ddr3_app_ecc_multiple_err" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_ECC&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_ddr2_app_addr</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_DDR2_ADDR_WIDTH&apos;)) )- 1 ">7</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_ddr2_app_addr" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_ddr2_app_cmd</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">2</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_ddr2_app_cmd" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_ddr2_app_en</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_ddr2_app_en" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_ddr2_app_wdf_data</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_DDR2_nCK_PER_CLK&apos;)) * 2 * spirit:decode(id(&apos;MODELPARAM_VALUE.C4_DDR2_DATA_WIDTH&apos;)) )- 1 ">31</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_ddr2_app_wdf_data" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_ddr2_app_wdf_end</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_ddr2_app_wdf_end" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_ddr2_app_wdf_mask</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_DDR2_nCK_PER_CLK&apos;)) * 2 * spirit:decode(id(&apos;MODELPARAM_VALUE.C4_DDR2_DATA_WIDTH&apos;)) / 8 )- 1 ">3</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_ddr2_app_wdf_mask" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_ddr2_app_wdf_wren</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_ddr2_app_wdf_wren" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_ddr2_app_correct_en_i</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_ddr2_app_correct_en_i" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_ECC&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_ddr2_app_rd_data</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_DDR2_nCK_PER_CLK&apos;)) * 2 * spirit:decode(id(&apos;MODELPARAM_VALUE.C4_DDR2_DATA_WIDTH&apos;)) )- 1 ">31</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_ddr2_app_rd_data" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_ddr2_app_rd_data_end</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_ddr2_app_rd_data_end" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_ddr2_app_rd_data_valid</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_ddr2_app_rd_data_valid" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_ddr2_app_rdy</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_ddr2_app_rdy" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_ddr2_app_wdf_rdy</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_ddr2_app_wdf_rdy" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_ddr2_app_sr_req</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_ddr2_app_sr_req" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_ddr2_app_sr_active</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_ddr2_app_sr_active" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_ddr2_app_ref_req</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_ddr2_app_ref_req" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_ddr2_app_ref_ack</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_ddr2_app_ref_ack" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_ddr2_app_zq_req</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_ddr2_app_zq_req" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_ddr2_app_zq_ack</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_ddr2_app_zq_ack" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_ddr2_app_raw_not_ecc</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( 2 * spirit:decode(id(&apos;MODELPARAM_VALUE.C4_DDR2_nCK_PER_CLK&apos;)) )- 1 ">3</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_ddr2_app_raw_not_ecc" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_ECC&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_ddr2_app_ecc_multiple_err</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( 2 * spirit:decode(id(&apos;MODELPARAM_VALUE.C4_DDR2_nCK_PER_CLK&apos;)) )- 1 ">3</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_ddr2_app_ecc_multiple_err" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_ECC&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_lpddr2_app_addr</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_LPDDR2_ADDR_WIDTH&apos;)) )- 1 ">7</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_lpddr2_app_addr" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_lpddr2_app_cmd</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">2</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_lpddr2_app_cmd" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_lpddr2_app_en</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_lpddr2_app_en" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_lpddr2_app_wdf_data</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_LPDDR2_nCK_PER_CLK&apos;)) * 2 * spirit:decode(id(&apos;MODELPARAM_VALUE.C4_LPDDR2_DATA_WIDTH&apos;)) )- 1 ">31</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_lpddr2_app_wdf_data" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_lpddr2_app_wdf_end</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_lpddr2_app_wdf_end" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_lpddr2_app_wdf_mask</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_LPDDR2_nCK_PER_CLK&apos;)) * 2 * spirit:decode(id(&apos;MODELPARAM_VALUE.C4_LPDDR2_DATA_WIDTH&apos;)) / 8 )- 1 ">3</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_lpddr2_app_wdf_mask" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_lpddr2_app_wdf_wren</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_lpddr2_app_wdf_wren" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_lpddr2_app_correct_en_i</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_lpddr2_app_correct_en_i" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_ECC&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_lpddr2_app_rd_data</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_LPDDR2_nCK_PER_CLK&apos;)) * 2 * spirit:decode(id(&apos;MODELPARAM_VALUE.C4_LPDDR2_DATA_WIDTH&apos;)) )- 1 ">31</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_lpddr2_app_rd_data" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_lpddr2_app_rd_data_end</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_lpddr2_app_rd_data_end" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_lpddr2_app_rd_data_valid</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_lpddr2_app_rd_data_valid" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_lpddr2_app_rdy</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_lpddr2_app_rdy" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_lpddr2_app_wdf_rdy</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_lpddr2_app_wdf_rdy" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_lpddr2_app_sr_req</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_lpddr2_app_sr_req" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_lpddr2_app_sr_active</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_lpddr2_app_sr_active" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_lpddr2_app_ref_req</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_lpddr2_app_ref_req" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_lpddr2_app_ref_ack</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_lpddr2_app_ref_ack" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_lpddr2_app_zq_req</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_lpddr2_app_zq_req" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_lpddr2_app_zq_ack</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_lpddr2_app_zq_ack" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_lpddr2_app_raw_not_ecc</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( 2 * spirit:decode(id(&apos;MODELPARAM_VALUE.C4_LPDDR2_nCK_PER_CLK&apos;)) )- 1 ">3</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_lpddr2_app_raw_not_ecc" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_ECC&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_lpddr2_app_ecc_multiple_err</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( 2 * spirit:decode(id(&apos;MODELPARAM_VALUE.C4_LPDDR2_nCK_PER_CLK&apos;)) )- 1 ">3</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_lpddr2_app_ecc_multiple_err" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_ECC&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_ui_clk_sync_rst</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_ui_clk_sync_rst" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;DDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;RLDII&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;RLDIII&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_ddr3_ui_clk_sync_rst</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_ddr3_ui_clk_sync_rst" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;DDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;RLDII&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;RLDIII&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_ddr2_ui_clk_sync_rst</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_ddr2_ui_clk_sync_rst" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;DDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;RLDII&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;RLDIII&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_lpddr2_ui_clk_sync_rst</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_lpddr2_ui_clk_sync_rst" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;DDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;RLDII&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;RLDIII&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_qdriip_ui_clk_sync_rst</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_qdriip_ui_clk_sync_rst" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;DDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;RLDII&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;RLDIII&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_rldii_ui_clk_sync_rst</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_rldii_ui_clk_sync_rst" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;RLDII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;DDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;RLDII&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;RLDIII&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_rldiii_ui_clk_sync_rst</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_rldiii_ui_clk_sync_rst" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;RLDIII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;DDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;RLDII&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;RLDIII&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_ui_clk</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_ui_clk" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;DDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;RLDII&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;RLDIII&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_ui_addn_clk_0</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_ui_addn_clk_0" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_UI_EXTRA_CLOCKS&apos;)) = &quot;TRUE&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MMCM_CLKOUT0_EN&apos;)) = &quot;TRUE&quot; ) and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;DDR2&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_ui_addn_clk_1</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_ui_addn_clk_1" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_UI_EXTRA_CLOCKS&apos;)) = &quot;TRUE&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MMCM_CLKOUT1_EN&apos;)) = &quot;TRUE&quot; ) and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;DDR2&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_ui_addn_clk_2</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_ui_addn_clk_2" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_UI_EXTRA_CLOCKS&apos;)) = &quot;TRUE&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MMCM_CLKOUT2_EN&apos;)) = &quot;TRUE&quot; ) and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;DDR2&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_ui_addn_clk_3</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_ui_addn_clk_3" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_UI_EXTRA_CLOCKS&apos;)) = &quot;TRUE&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MMCM_CLKOUT3_EN&apos;)) = &quot;TRUE&quot; ) and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;DDR2&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_ui_addn_clk_4</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_ui_addn_clk_4" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_UI_EXTRA_CLOCKS&apos;)) = &quot;TRUE&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MMCM_CLKOUT4_EN&apos;)) = &quot;TRUE&quot; ) and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;DDR2&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_s_axi_ctrl_awvalid</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_s_axi_ctrl_awvalid" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_USE_AXI&apos;)) = 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_ECC&apos;)) = &quot;ON&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_s_axi_ctrl_awready</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_s_axi_ctrl_awready" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_USE_AXI&apos;)) = 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_ECC&apos;)) = &quot;ON&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_s_axi_ctrl_awaddr</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_C_S_AXI_CTRL_ADDR_WIDTH&apos;)) )- 1 ">31</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_s_axi_ctrl_awaddr" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_USE_AXI&apos;)) = 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_ECC&apos;)) = &quot;ON&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_s_axi_ctrl_wvalid</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_s_axi_ctrl_wvalid" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_USE_AXI&apos;)) = 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_ECC&apos;)) = &quot;ON&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_s_axi_ctrl_wready</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_s_axi_ctrl_wready" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_USE_AXI&apos;)) = 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_ECC&apos;)) = &quot;ON&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_s_axi_ctrl_wdata</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_C_S_AXI_CTRL_DATA_WIDTH&apos;)) )- 1 ">31</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_s_axi_ctrl_wdata" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_USE_AXI&apos;)) = 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_ECC&apos;)) = &quot;ON&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_s_axi_ctrl_bvalid</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_s_axi_ctrl_bvalid" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_USE_AXI&apos;)) = 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_ECC&apos;)) = &quot;ON&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_s_axi_ctrl_bready</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_s_axi_ctrl_bready" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_USE_AXI&apos;)) = 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_ECC&apos;)) = &quot;ON&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_s_axi_ctrl_bresp</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">1</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_s_axi_ctrl_bresp" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_USE_AXI&apos;)) = 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_ECC&apos;)) = &quot;ON&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_s_axi_ctrl_arvalid</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_s_axi_ctrl_arvalid" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_USE_AXI&apos;)) = 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_ECC&apos;)) = &quot;ON&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_s_axi_ctrl_arready</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_s_axi_ctrl_arready" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_USE_AXI&apos;)) = 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_ECC&apos;)) = &quot;ON&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_s_axi_ctrl_araddr</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_C_S_AXI_CTRL_ADDR_WIDTH&apos;)) )- 1 ">31</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_s_axi_ctrl_araddr" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_USE_AXI&apos;)) = 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_ECC&apos;)) = &quot;ON&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_s_axi_ctrl_rvalid</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_s_axi_ctrl_rvalid" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_USE_AXI&apos;)) = 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_ECC&apos;)) = &quot;ON&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_s_axi_ctrl_rready</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_s_axi_ctrl_rready" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_USE_AXI&apos;)) = 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_ECC&apos;)) = &quot;ON&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_s_axi_ctrl_rdata</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_C_S_AXI_CTRL_DATA_WIDTH&apos;)) )- 1 ">31</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_s_axi_ctrl_rdata" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_USE_AXI&apos;)) = 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_ECC&apos;)) = &quot;ON&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_s_axi_ctrl_rresp</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">1</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_s_axi_ctrl_rresp" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_USE_AXI&apos;)) = 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_ECC&apos;)) = &quot;ON&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_s_axi_awid</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_C_S_AXI_ID_WIDTH&apos;)) )- 1 ">3</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
          <spirit:driver>
            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
          </spirit:driver>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_s_axi_awid" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_s_axi_awaddr</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_C_S_AXI_ADDR_WIDTH&apos;)) )- 1 ">31</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_s_axi_awaddr" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_s_axi_awlen</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">7</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_s_axi_awlen" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_s_axi_awsize</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">2</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_s_axi_awsize" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_s_axi_awburst</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">1</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_s_axi_awburst" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_s_axi_awlock</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
          <spirit:driver>
            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
          </spirit:driver>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_s_axi_awlock" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_s_axi_awcache</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">3</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
          <spirit:driver>
            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
          </spirit:driver>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_s_axi_awcache" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_s_axi_awprot</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">2</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
          <spirit:driver>
            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
          </spirit:driver>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_s_axi_awprot" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_s_axi_awqos</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">3</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
          <spirit:driver>
            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
          </spirit:driver>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_s_axi_awqos" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_s_axi_awvalid</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_s_axi_awvalid" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_s_axi_awready</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_s_axi_awready" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_s_axi_wdata</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_C_S_AXI_DATA_WIDTH&apos;)) )- 1 ">31</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_s_axi_wdata" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_s_axi_wstrb</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_C_S_AXI_DATA_WIDTH&apos;)) / 8 )- 1 ">3</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_s_axi_wstrb" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_s_axi_wlast</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_s_axi_wlast" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_s_axi_wvalid</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_s_axi_wvalid" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_s_axi_wready</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_s_axi_wready" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_s_axi_bready</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_s_axi_bready" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_s_axi_bid</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_C_S_AXI_ID_WIDTH&apos;)) )- 1 ">3</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_s_axi_bid" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_s_axi_bresp</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">1</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_s_axi_bresp" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_s_axi_bvalid</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_s_axi_bvalid" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_s_axi_arid</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_C_S_AXI_ID_WIDTH&apos;)) )- 1 ">3</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
          <spirit:driver>
            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
          </spirit:driver>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_s_axi_arid" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_s_axi_araddr</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_C_S_AXI_ADDR_WIDTH&apos;)) )- 1 ">31</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_s_axi_araddr" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_s_axi_arlen</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">7</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_s_axi_arlen" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_s_axi_arsize</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">2</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_s_axi_arsize" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_s_axi_arburst</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">1</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_s_axi_arburst" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_s_axi_arlock</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
          <spirit:driver>
            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
          </spirit:driver>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_s_axi_arlock" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_s_axi_arcache</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">3</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
          <spirit:driver>
            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
          </spirit:driver>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_s_axi_arcache" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_s_axi_arprot</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">2</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
          <spirit:driver>
            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
          </spirit:driver>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_s_axi_arprot" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_s_axi_arqos</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">3</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
          <spirit:driver>
            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
          </spirit:driver>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_s_axi_arqos" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_s_axi_arvalid</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_s_axi_arvalid" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_s_axi_arready</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_s_axi_arready" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_s_axi_rready</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_s_axi_rready" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_s_axi_rid</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_C_S_AXI_ID_WIDTH&apos;)) )- 1 ">3</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_s_axi_rid" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_s_axi_rdata</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_C_S_AXI_DATA_WIDTH&apos;)) )- 1 ">31</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_s_axi_rdata" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_s_axi_rresp</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">1</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_s_axi_rresp" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_s_axi_rlast</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_s_axi_rlast" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_s_axi_rvalid</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_s_axi_rvalid" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_interrupt</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_interrupt" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_USE_AXI&apos;)) = 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_ECC&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_mmcm_locked</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_mmcm_locked" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_qdriip_cq_p</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_QDRIIP_NUM_DEVICES&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_qdriip_cq_p" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_qdriip_cq_n</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_QDRIIP_NUM_DEVICES&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_qdriip_cq_n" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_qdriip_qvld</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_QDRIIP_NUM_DEVICES&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_qdriip_qvld" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_qdriip_q</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_QDRIIP_DATA_WIDTH&apos;)) )- 1 ">17</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_qdriip_q" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_qdriip_k_p</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_QDRIIP_NUM_DEVICES&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_qdriip_k_p" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_qdriip_k_n</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_QDRIIP_NUM_DEVICES&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_qdriip_k_n" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_qdriip_d</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_QDRIIP_DATA_WIDTH&apos;)) )- 1 ">17</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_qdriip_d" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_qdriip_sa</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_QDRIIP_ADDR_WIDTH&apos;)) )- 1 ">28</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_qdriip_sa" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_qdriip_w_n</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_qdriip_w_n" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_qdriip_r_n</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_qdriip_r_n" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_qdriip_bw_n</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_QDRIIP_BW_WIDTH&apos;)) )- 1 ">7</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_qdriip_bw_n" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_qdriip_dll_off_n</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_qdriip_dll_off_n" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_qdriip_dbg_pi_counter_read_val</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">4</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_qdriip_dbg_pi_counter_read_val" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_QDRIIP_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_qdriip_dbg_win_inc</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_qdriip_dbg_win_inc" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_QDRIIP_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_qdriip_dbg_win_dec</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_qdriip_dbg_win_dec" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_QDRIIP_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_qdriip_dbg_win_active</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_qdriip_dbg_win_active" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_QDRIIP_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_qdriip_dbg_win_current_byte</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">2</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_qdriip_dbg_win_current_byte" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_QDRIIP_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_qdriip_ila0_data</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">254</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_qdriip_ila0_data" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_QDRIIP_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_qdriip_ila0_trig</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">6</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_qdriip_ila0_trig" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_QDRIIP_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_qdriip_ila1_data</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">269</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_qdriip_ila1_data" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_QDRIIP_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_qdriip_ila1_trig</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">14</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_qdriip_ila1_trig" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_QDRIIP_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_qdriip_vio2_async_in</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">198</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_qdriip_vio2_async_in" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_QDRIIP_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_qdriip_vio2_sync_out</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">34</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_qdriip_vio2_sync_out" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_QDRIIP_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_app_wr_cmd0</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_app_wr_cmd0" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_app_wr_addr0</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_QDRIIP_ADDR_WIDTH&apos;)) )- 1 ">28</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_app_wr_addr0" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_app_wr_data0</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_QDRIIP_BURST_LEN&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_app_wr_data0" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_app_wr_bw_n0</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_QDRIIP_BURST_LEN&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_app_wr_bw_n0" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_app_rd_cmd0</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_app_rd_cmd0" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_app_rd_addr0</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_QDRIIP_ADDR_WIDTH&apos;)) )- 1 ">28</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_app_rd_addr0" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_app_rd_valid0</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_app_rd_valid0" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_app_rd_data0</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_QDRIIP_BURST_LEN&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_app_rd_data0" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_app_wr_cmd1</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_app_wr_cmd1" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_app_wr_addr1</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_QDRIIP_ADDR_WIDTH&apos;)) )- 1 ">28</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_app_wr_addr1" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_app_wr_data1</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" (( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_QDRIIP_DATA_WIDTH&apos;)) * 2 ))- 1 ">35</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_app_wr_data1" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_app_wr_bw_n1</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" (( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_QDRIIP_BW_WIDTH&apos;)) * 2 ))- 1 ">15</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_app_wr_bw_n1" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_app_rd_cmd1</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_app_rd_cmd1" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_app_rd_addr1</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_QDRIIP_ADDR_WIDTH&apos;)) )- 1 ">28</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_app_rd_addr1" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_app_rd_valid1</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_app_rd_valid1" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_app_rd_data1</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" (( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_QDRIIP_DATA_WIDTH&apos;)) * 2 ))- 1 ">35</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_app_rd_data1" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_clk</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_clk" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_rst_clk</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_rst_clk" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_qdriip_app_wr_cmd0</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_qdriip_app_wr_cmd0" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_qdriip_app_wr_addr0</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_QDRIIP_ADDR_WIDTH&apos;)) )- 1 ">28</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_qdriip_app_wr_addr0" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_qdriip_app_wr_data0</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_QDRIIP_BURST_LEN&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_qdriip_app_wr_data0" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_qdriip_app_wr_bw_n0</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_QDRIIP_BURST_LEN&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_qdriip_app_wr_bw_n0" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_qdriip_app_rd_cmd0</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_qdriip_app_rd_cmd0" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_qdriip_app_rd_addr0</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_QDRIIP_ADDR_WIDTH&apos;)) )- 1 ">28</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_qdriip_app_rd_addr0" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_qdriip_app_rd_valid0</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_qdriip_app_rd_valid0" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_qdriip_app_rd_data0</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_QDRIIP_BURST_LEN&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_qdriip_app_rd_data0" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_qdriip_app_wr_cmd1</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_qdriip_app_wr_cmd1" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_qdriip_app_wr_addr1</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_QDRIIP_ADDR_WIDTH&apos;)) )- 1 ">28</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_qdriip_app_wr_addr1" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_qdriip_app_wr_data1</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" (( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_QDRIIP_DATA_WIDTH&apos;)) * 2 ))- 1 ">35</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_qdriip_app_wr_data1" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_qdriip_app_wr_bw_n1</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" (( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_QDRIIP_BW_WIDTH&apos;)) * 2 ))- 1 ">15</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_qdriip_app_wr_bw_n1" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_qdriip_app_rd_cmd1</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_qdriip_app_rd_cmd1" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_qdriip_app_rd_addr1</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_QDRIIP_ADDR_WIDTH&apos;)) )- 1 ">28</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_qdriip_app_rd_addr1" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_qdriip_app_rd_valid1</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_qdriip_app_rd_valid1" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_qdriip_app_rd_data1</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" (( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_QDRIIP_DATA_WIDTH&apos;)) * 2 ))- 1 ">35</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_qdriip_app_rd_data1" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_qdriip_clk</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_qdriip_clk" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_qdriip_rst_clk</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_qdriip_rst_clk" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_rldii_qk_p</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_RLDII_QK_WIDTH&apos;)) )- 1 ">7</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_rldii_qk_p" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;RLDII&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_rldii_qk_n</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_RLDII_QK_WIDTH&apos;)) )- 1 ">7</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_rldii_qk_n" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;RLDII&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_rldii_dq</spirit:name>
        <spirit:wire>
          <spirit:direction>inout</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_RLDII_DATA_WIDTH&apos;)) )- 1 ">17</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_rldii_dq" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;RLDII&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_rldii_dm</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_RLDII_DM_WIDTH&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_rldii_dm" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;RLDII&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_rldii_dk_p</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_RLDII_DK_WIDTH&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_rldii_dk_p" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;RLDII&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_rldii_dk_n</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_RLDII_DK_WIDTH&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_rldii_dk_n" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;RLDII&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_rldii_ck_p</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_RLDII_NUM_DEVICES&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_rldii_ck_p" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;RLDII&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_rldii_ck_n</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_RLDII_NUM_DEVICES&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_rldii_ck_n" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;RLDII&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_rldii_cs_n</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_RLDII_NUM_DEVICES&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_rldii_cs_n" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;RLDII&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_rldii_a</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_RLDII_RLD_ADDR_WIDTH&apos;)) )- 1 ">28</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_rldii_a" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;RLDII&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_rldii_ba</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_RLDII_BANK_WIDTH&apos;)) )- 1 ">1</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_rldii_ba" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;RLDII&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_rldii_qvld</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_RLDII_QVLD_WIDTH&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_rldii_qvld" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;RLDII&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_rldii_we_n</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_rldii_we_n" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;RLDII&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_rldii_ref_n</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_rldii_ref_n" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;RLDII&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_rldii_reset_n</spirit:name>
        <spirit:displayName>reset to memory device</spirit:displayName>
        <spirit:description>reset to memory device</spirit:description>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_rldii_reset_n" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;RLDII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;RLDIII&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_rldii_dbg_pi_tap_cnt</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">4</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_rldii_dbg_pi_tap_cnt" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;RLDII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_RLDII_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_rldii_dbg_win_inc</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_rldii_dbg_win_inc" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;RLDII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_RLDII_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_rldii_dbg_win_dec</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_rldii_dbg_win_dec" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;RLDII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_RLDII_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_rldii_dbg_win_active</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_rldii_dbg_win_active" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;RLDII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_RLDII_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_rldii_dbg_win_current_byte</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">2</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_rldii_dbg_win_current_byte" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;RLDII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_RLDII_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_rldii_ila0_data</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">638</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_rldii_ila0_data" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;RLDII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_RLDII_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_rldii_ila0_trig</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">30</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_rldii_ila0_trig" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;RLDII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_RLDII_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_rldii_vio1_async_in</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">254</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_rldii_vio1_async_in" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;RLDII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_RLDII_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_rldii_vio1_async_out</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">62</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_rldii_vio1_async_out" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;RLDII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_RLDII_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_rldii_vio1_sync_out</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">62</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_rldii_vio1_sync_out" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;RLDII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_RLDII_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_rldiii_qk_p</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_RLDIII_QK_WIDTH&apos;)) )- 1 ">7</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_rldiii_qk_p" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;RLDIII&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_rldiii_qk_n</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_RLDIII_QK_WIDTH&apos;)) )- 1 ">7</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_rldiii_qk_n" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;RLDIII&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_rldiii_dq</spirit:name>
        <spirit:wire>
          <spirit:direction>inout</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_RLDIII_DATA_WIDTH&apos;)) )- 1 ">17</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_rldiii_dq" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;RLDIII&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_rldiii_dm</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_RLDIII_DM_WIDTH&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_rldiii_dm" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;RLDIII&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_rldiii_dk_p</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_RLDIII_DK_WIDTH&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_rldiii_dk_p" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;RLDIII&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_rldiii_dk_n</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_RLDIII_DK_WIDTH&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_rldiii_dk_n" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;RLDIII&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_rldiii_ck_p</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_RLDIII_NUM_DEVICES&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_rldiii_ck_p" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;RLDIII&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_rldiii_ck_n</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_RLDIII_NUM_DEVICES&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_rldiii_ck_n" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;RLDIII&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_rldiii_cs_n</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_RLDIII_NUM_DEVICES&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_rldiii_cs_n" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;RLDIII&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_rldiii_a</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_RLDIII_RLD_ADDR_WIDTH&apos;)) )- 1 ">28</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_rldiii_a" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;RLDIII&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_rldiii_ba</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_RLDIII_BANK_WIDTH&apos;)) )- 1 ">1</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_rldiii_ba" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;RLDIII&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_rldiii_qvld</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_RLDIII_QVLD_WIDTH&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_rldiii_qvld" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;RLDIII&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_rldiii_we_n</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_rldiii_we_n" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;RLDIII&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_rldiii_ref_n</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_rldiii_ref_n" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;RLDIII&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_rldiii_reset_n</spirit:name>
        <spirit:displayName>reset to memory device</spirit:displayName>
        <spirit:description>reset to memory device</spirit:description>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_rldiii_reset_n" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;RLDIII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;RLDIII&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_dbg_pi_tap_cnt</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">4</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_dbg_pi_tap_cnt" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;RLDIII&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;RLDII&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_rldiii_dbg_pi_tap_cnt</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">4</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_rldiii_dbg_pi_tap_cnt" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;RLDIII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_RLDIII_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_rldiii_dbg_win_inc</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_rldiii_dbg_win_inc" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;RLDIII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_RLDIII_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_rldiii_dbg_win_dec</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_rldiii_dbg_win_dec" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;RLDIII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_RLDIII_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_rldiii_dbg_win_active</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_rldiii_dbg_win_active" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;RLDIII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_RLDIII_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_rldiii_dbg_win_current_byte</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">2</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_rldiii_dbg_win_current_byte" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;RLDIII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_RLDIII_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_rldiii_ila0_data</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">638</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_rldiii_ila0_data" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;RLDIII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_RLDIII_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_rldiii_ila0_trig</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">30</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_rldiii_ila0_trig" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;RLDIII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_RLDIII_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_rldiii_vio1_async_in</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">254</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_rldiii_vio1_async_in" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;RLDIII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_RLDIII_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_rldiii_vio1_async_out</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">62</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_rldiii_vio1_async_out" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;RLDIII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_RLDIII_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_rldiii_vio1_sync_out</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">62</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_rldiii_vio1_sync_out" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;RLDIII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_RLDIII_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_dbg_win_inc</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_dbg_win_inc" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;RLDIII&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;RLDII&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_dbg_win_dec</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_dbg_win_dec" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;RLDIII&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;RLDII&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_dbg_win_active</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_dbg_win_active" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;RLDIII&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;RLDII&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_dbg_win_current_byte</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">2</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_dbg_win_current_byte" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;RLDIII&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;RLDII&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_dbg_pi_counter_read_val</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">4</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_dbg_pi_counter_read_val" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;DDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_user_cmd_en</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_user_cmd_en" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;RLDII&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;RLDIII&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_user_cmd</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_RLDX_CMD_PER_CLK&apos;)) * 2 )- 1 ">1</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_user_cmd" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;RLDII&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;RLDIII&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_user_addr</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_RLDX_ADDR_WIDTH&apos;)) * spirit:decode(id(&apos;MODELPARAM_VALUE.C4_RLDX_CMD_PER_CLK&apos;)) )- 1 ">28</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_user_addr" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;RLDII&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;RLDIII&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_user_ba</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_RLDX_BANK_WIDTH&apos;)) * spirit:decode(id(&apos;MODELPARAM_VALUE.C4_RLDX_CMD_PER_CLK&apos;)) )- 1 ">1</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_user_ba" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;RLDII&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;RLDIII&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_user_wr_en</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_user_wr_en" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;RLDII&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;RLDIII&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_user_wr_data</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_RLDX_DATA_WIDTH&apos;)) * 2 * spirit:decode(id(&apos;MODELPARAM_VALUE.C4_RLDX_nCK_PER_CLK&apos;)) )- 1 ">35</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_user_wr_data" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;RLDII&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;RLDIII&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_user_wr_dm</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_RLDX_DM_WIDTH&apos;)) * 2 * spirit:decode(id(&apos;MODELPARAM_VALUE.C4_RLDX_nCK_PER_CLK&apos;)) )- 1 ">1</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_user_wr_dm" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;RLDII&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;RLDIII&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_user_afifo_empty</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_user_afifo_empty" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;RLDII&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;RLDIII&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_user_afifo_full</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_user_afifo_full" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;RLDII&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;RLDIII&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_user_afifo_aempty</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_user_afifo_aempty" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;RLDII&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;RLDIII&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_user_afifo_afull</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_user_afifo_afull" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;RLDII&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;RLDIII&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_user_wdfifo_empty</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_user_wdfifo_empty" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;RLDII&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;RLDIII&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_user_wdfifo_full</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_user_wdfifo_full" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;RLDII&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;RLDIII&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_user_wdfifo_aempty</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_user_wdfifo_aempty" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;RLDII&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;RLDIII&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_user_wdfifo_afull</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_user_wdfifo_afull" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;RLDII&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;RLDIII&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_user_rd_valid</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_RLDX_nCK_PER_CLK&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_user_rd_valid" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;RLDII&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;RLDIII&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_mem_ck_lock_complete</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_mem_ck_lock_complete" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;RLDII&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;RLDIII&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_user_rd_data</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_RLDX_DATA_WIDTH&apos;)) * 2 * spirit:decode(id(&apos;MODELPARAM_VALUE.C4_RLDX_nCK_PER_CLK&apos;)) )- 1 ">35</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_user_rd_data" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;RLDII&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;RLDIII&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_rldii_user_cmd_en</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_rldii_user_cmd_en" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;RLDII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_rldii_user_cmd</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_RLDII_CMD_PER_CLK&apos;)) * 2 )- 1 ">1</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_rldii_user_cmd" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;RLDII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_rldii_user_addr</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_RLDII_ADDR_WIDTH&apos;)) * spirit:decode(id(&apos;MODELPARAM_VALUE.C4_RLDII_CMD_PER_CLK&apos;)) )- 1 ">28</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_rldii_user_addr" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;RLDII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_rldii_user_ba</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_RLDII_BANK_WIDTH&apos;)) * spirit:decode(id(&apos;MODELPARAM_VALUE.C4_RLDII_CMD_PER_CLK&apos;)) )- 1 ">1</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_rldii_user_ba" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;RLDII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_rldii_user_wr_en</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_rldii_user_wr_en" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;RLDII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_rldii_user_wr_data</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_RLDII_DATA_WIDTH&apos;)) * 2 * spirit:decode(id(&apos;MODELPARAM_VALUE.C4_RLDII_nCK_PER_CLK&apos;)) )- 1 ">35</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_rldii_user_wr_data" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;RLDII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_rldii_user_wr_dm</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_RLDII_DM_WIDTH&apos;)) * 2 * spirit:decode(id(&apos;MODELPARAM_VALUE.C4_RLDII_nCK_PER_CLK&apos;)) )- 1 ">1</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_rldii_user_wr_dm" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;RLDII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_rldii_user_afifo_empty</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_rldii_user_afifo_empty" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;RLDII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_rldii_user_afifo_full</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_rldii_user_afifo_full" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;RLDII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_rldii_user_afifo_aempty</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_rldii_user_afifo_aempty" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;RLDII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_rldii_user_afifo_afull</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_rldii_user_afifo_afull" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;RLDII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_rldii_user_wdfifo_empty</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_rldii_user_wdfifo_empty" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;RLDII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_rldii_user_wdfifo_full</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_rldii_user_wdfifo_full" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;RLDII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_rldii_user_wdfifo_aempty</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_rldii_user_wdfifo_aempty" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;RLDII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_rldii_user_wdfifo_afull</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_rldii_user_wdfifo_afull" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;RLDII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_rldii_user_rd_valid</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_RLDII_nCK_PER_CLK&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_rldii_user_rd_valid" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;RLDII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_rldii_mem_ck_lock_complete</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_rldii_mem_ck_lock_complete" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;RLDII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_rldii_user_rd_data</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_RLDII_DATA_WIDTH&apos;)) * 2 * spirit:decode(id(&apos;MODELPARAM_VALUE.C4_RLDII_nCK_PER_CLK&apos;)) )- 1 ">35</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_rldii_user_rd_data" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;RLDII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_rldiii_user_cmd_en</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_rldiii_user_cmd_en" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;RLDIII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_rldiii_user_cmd</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_RLDIII_CMD_PER_CLK&apos;)) * 2 )- 1 ">1</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_rldiii_user_cmd" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;RLDIII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_rldiii_user_addr</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_RLDIII_ADDR_WIDTH&apos;)) * spirit:decode(id(&apos;MODELPARAM_VALUE.C4_RLDIII_CMD_PER_CLK&apos;)) )- 1 ">28</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_rldiii_user_addr" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;RLDIII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_rldiii_user_ba</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_RLDIII_BANK_WIDTH&apos;)) * spirit:decode(id(&apos;MODELPARAM_VALUE.C4_RLDIII_CMD_PER_CLK&apos;)) )- 1 ">1</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_rldiii_user_ba" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;RLDIII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_rldiii_user_wr_en</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_rldiii_user_wr_en" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;RLDIII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_rldiii_user_wr_data</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_RLDIII_DATA_WIDTH&apos;)) * 2 * spirit:decode(id(&apos;MODELPARAM_VALUE.C4_RLDIII_nCK_PER_CLK&apos;)) )- 1 ">35</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_rldiii_user_wr_data" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;RLDIII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_rldiii_user_wr_dm</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_RLDIII_DM_WIDTH&apos;)) * 2 * spirit:decode(id(&apos;MODELPARAM_VALUE.C4_RLDIII_nCK_PER_CLK&apos;)) )- 1 ">1</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_rldiii_user_wr_dm" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;RLDIII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_rldiii_user_afifo_empty</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_rldiii_user_afifo_empty" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;RLDIII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_rldiii_user_afifo_full</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_rldiii_user_afifo_full" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;RLDIII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_rldiii_user_afifo_aempty</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_rldiii_user_afifo_aempty" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;RLDIII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_rldiii_user_afifo_afull</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_rldiii_user_afifo_afull" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;RLDIII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_rldiii_user_wdfifo_empty</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_rldiii_user_wdfifo_empty" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;RLDIII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_rldiii_user_wdfifo_full</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_rldiii_user_wdfifo_full" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;RLDIII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_rldiii_user_wdfifo_aempty</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_rldiii_user_wdfifo_aempty" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;RLDIII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_rldiii_user_wdfifo_afull</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_rldiii_user_wdfifo_afull" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;RLDIII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_rldiii_user_rd_valid</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_RLDIII_nCK_PER_CLK&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_rldiii_user_rd_valid" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;RLDIII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_rldiii_mem_ck_lock_complete</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_rldiii_mem_ck_lock_complete" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;RLDIII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_rldiii_user_rd_data</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_RLDIII_DATA_WIDTH&apos;)) * 2 * spirit:decode(id(&apos;MODELPARAM_VALUE.C4_RLDIII_nCK_PER_CLK&apos;)) )- 1 ">35</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_rldiii_user_rd_data" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;RLDIII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_sys_clk_p</spirit:name>
        <spirit:displayName>Clock P</spirit:displayName>
        <spirit:description>Clock P</spirit:description>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_sys_clk_p" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_SYSCLK_TYPE&apos;)) = &quot;DIFF&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_IS_CLK_SHARED&apos;)) = &quot;FALSE&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_sys_clk_n</spirit:name>
        <spirit:displayName>Clock P</spirit:displayName>
        <spirit:description>Clock P</spirit:description>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_sys_clk_n" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_SYSCLK_TYPE&apos;)) = &quot;DIFF&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_IS_CLK_SHARED&apos;)) = &quot;FALSE&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_sys_clk_i</spirit:name>
        <spirit:displayName>Clock P</spirit:displayName>
        <spirit:description>Clock P</spirit:description>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_sys_clk_i" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_SYSCLK_TYPE&apos;)) != &quot;DIFF&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C4_IS_CLK_SHARED&apos;)) = &quot;FALSE&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_init_calib_complete</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_init_calib_complete" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c4_aresetn</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c4_aresetn" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 4 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C4_MEM_TYPE&apos;)) = &quot;DDR2&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_ddr3_dq</spirit:name>
        <spirit:displayName>Data</spirit:displayName>
        <spirit:description>Data</spirit:description>
        <spirit:wire>
          <spirit:direction>inout</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_DDR3_DQ_WIDTH&apos;)) )- 1 ">7</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_ddr3_dq" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;DDR3&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_ddr3_dqs_p</spirit:name>
        <spirit:displayName>Data Strobe</spirit:displayName>
        <spirit:description>Data Strobe</spirit:description>
        <spirit:wire>
          <spirit:direction>inout</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_DDR3_DQS_WIDTH&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_ddr3_dqs_p" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;DDR3&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_ddr3_dqs_n</spirit:name>
        <spirit:displayName>Data Strobe</spirit:displayName>
        <spirit:description>Data Strobe</spirit:description>
        <spirit:wire>
          <spirit:direction>inout</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_DDR3_DQS_WIDTH&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_ddr3_dqs_n" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;DDR3&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_ddr3_addr</spirit:name>
        <spirit:displayName>Address</spirit:displayName>
        <spirit:description>Address</spirit:description>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_DDR3_ROW_WIDTH&apos;)) )- 1 ">13</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_ddr3_addr" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;DDR3&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_ddr3_ba</spirit:name>
        <spirit:displayName>Bank Address</spirit:displayName>
        <spirit:description>Bank Address</spirit:description>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_DDR3_BANK_WIDTH&apos;)) )- 1 ">2</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_ddr3_ba" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;DDR3&quot; and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;DDR2&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_ddr3_ras_n</spirit:name>
        <spirit:displayName>row address strobe</spirit:displayName>
        <spirit:description>row address strobe</spirit:description>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_ddr3_ras_n" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;DDR3&quot; and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;DDR2&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_ddr3_cas_n</spirit:name>
        <spirit:displayName>column address strobe</spirit:displayName>
        <spirit:description>column address strobe</spirit:description>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_ddr3_cas_n" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;DDR3&quot; and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;DDR2&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_ddr3_we_n</spirit:name>
        <spirit:displayName>write enable</spirit:displayName>
        <spirit:description>write enable</spirit:description>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_ddr3_we_n" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;DDR3&quot; and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;DDR2&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_ddr3_reset_n</spirit:name>
        <spirit:displayName>reset to memory device</spirit:displayName>
        <spirit:description>reset to memory device</spirit:description>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_ddr3_reset_n" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;DDR3&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_ddr3_ck_p</spirit:name>
        <spirit:displayName>clock to memory device</spirit:displayName>
        <spirit:description>clock to memory device</spirit:description>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_DDR3_CK_WIDTH&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_ddr3_ck_p" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;DDR3&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_ddr3_ck_n</spirit:name>
        <spirit:displayName>clock to memory device</spirit:displayName>
        <spirit:description>clock to memory device</spirit:description>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_DDR3_CK_WIDTH&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_ddr3_ck_n" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;DDR3&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_ddr3_cke</spirit:name>
        <spirit:displayName>clock enable</spirit:displayName>
        <spirit:description>clock enable</spirit:description>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_DDR3_CKE_WIDTH&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_ddr3_cke" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;DDR3&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_ddr3_cs_n</spirit:name>
        <spirit:displayName>chip select</spirit:displayName>
        <spirit:description>chip select</spirit:description>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_DDR3_CS_WIDTH&apos;)) * spirit:decode(id(&apos;MODELPARAM_VALUE.C5_DDR3_nCS_PER_RANK&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_ddr3_cs_n" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_DDR3_USE_CS_PORT&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_ddr3_dm</spirit:name>
        <spirit:displayName>data mask</spirit:displayName>
        <spirit:description>data mask</spirit:description>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_DDR3_DM_WIDTH&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_ddr3_dm" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_DDR3_USE_DM_PORT&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_ddr3_odt</spirit:name>
        <spirit:displayName>on die termination</spirit:displayName>
        <spirit:description>on die termination</spirit:description>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_DDR3_ODT_WIDTH&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_ddr3_odt" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;DDR3&quot; and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;DDR2&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_DDR3_USE_ODT_PORT&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_ddr3_parity</spirit:name>
        <spirit:displayName>parity bit</spirit:displayName>
        <spirit:description>parity bit</spirit:description>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_ddr3_parity" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_DDR3_REG_CTRL&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_ddr3_dbg_pi_counter_read_val</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">4</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_ddr3_dbg_pi_counter_read_val" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_DDR3_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_ddr3_dbg_byte_sel</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_DDR3_DQS_CNT_WIDTH&apos;)) + 1 )- 1 ">1</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_ddr3_dbg_byte_sel" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_DDR3_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_ddr3_dbg_sel_pi_incdec</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_ddr3_dbg_sel_pi_incdec" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_DDR3_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_ddr3_dbg_pi_f_inc</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_ddr3_dbg_pi_f_inc" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_DDR3_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_ddr3_dbg_pi_f_dec</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_ddr3_dbg_pi_f_dec" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_DDR3_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_ddr3_dbg_sel_po_incdec</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_ddr3_dbg_sel_po_incdec" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_DDR3_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_ddr3_dbg_po_f_inc</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_ddr3_dbg_po_f_inc" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_DDR3_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_ddr3_dbg_po_f_stg23_sel</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_ddr3_dbg_po_f_stg23_sel" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_DDR3_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_ddr3_dbg_po_f_dec</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_ddr3_dbg_po_f_dec" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_DDR3_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_ddr3_dbg_po_counter_read_val</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">7</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_ddr3_dbg_po_counter_read_val" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_DDR3_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_ddr3_ila_wrpath</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">254</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_ddr3_ila_wrpath" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_DDR3_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_ddr3_ila_rdpath</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">1022</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_ddr3_ila_rdpath" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_DDR3_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_ddr3_ila_basic</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">126</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_ddr3_ila_basic" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_DDR3_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_ddr3_vio_sync_out</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">34</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_ddr3_vio_sync_out" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_DDR3_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_ddr2_dq</spirit:name>
        <spirit:displayName>Data</spirit:displayName>
        <spirit:description>Data</spirit:description>
        <spirit:wire>
          <spirit:direction>inout</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_DDR2_DQ_WIDTH&apos;)) )- 1 ">7</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_ddr2_dq" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;DDR2&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_ddr2_dqs_p</spirit:name>
        <spirit:displayName>Data Strobe</spirit:displayName>
        <spirit:description>Data Strobe</spirit:description>
        <spirit:wire>
          <spirit:direction>inout</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_DDR2_DQS_WIDTH&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_ddr2_dqs_p" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;DDR2&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_ddr2_dqs_n</spirit:name>
        <spirit:displayName>Data Strobe</spirit:displayName>
        <spirit:description>Data Strobe</spirit:description>
        <spirit:wire>
          <spirit:direction>inout</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_DDR2_DQS_WIDTH&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_ddr2_dqs_n" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;DDR2&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_ddr2_addr</spirit:name>
        <spirit:displayName>Address</spirit:displayName>
        <spirit:description>Address</spirit:description>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_DDR2_ROW_WIDTH&apos;)) )- 1 ">13</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_ddr2_addr" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;DDR2&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_ddr2_ba</spirit:name>
        <spirit:displayName>Bank Address</spirit:displayName>
        <spirit:description>Bank Address</spirit:description>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_DDR2_BANK_WIDTH&apos;)) )- 1 ">2</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_ddr2_ba" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;DDR2&quot; and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;DDR2&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_ddr2_ras_n</spirit:name>
        <spirit:displayName>row address strobe</spirit:displayName>
        <spirit:description>row address strobe</spirit:description>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_ddr2_ras_n" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;DDR2&quot; and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;DDR2&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_ddr2_cas_n</spirit:name>
        <spirit:displayName>column address strobe</spirit:displayName>
        <spirit:description>column address strobe</spirit:description>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_ddr2_cas_n" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;DDR2&quot; and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;DDR2&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_ddr2_we_n</spirit:name>
        <spirit:displayName>write enable</spirit:displayName>
        <spirit:description>write enable</spirit:description>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_ddr2_we_n" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;DDR2&quot; and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;DDR2&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_ddr2_reset_n</spirit:name>
        <spirit:displayName>reset to memory device</spirit:displayName>
        <spirit:description>reset to memory device</spirit:description>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_ddr2_reset_n" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;DDR3&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_ddr2_ck_p</spirit:name>
        <spirit:displayName>clock to memory device</spirit:displayName>
        <spirit:description>clock to memory device</spirit:description>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_DDR2_CK_WIDTH&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_ddr2_ck_p" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;DDR2&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_ddr2_ck_n</spirit:name>
        <spirit:displayName>clock to memory device</spirit:displayName>
        <spirit:description>clock to memory device</spirit:description>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_DDR2_CK_WIDTH&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_ddr2_ck_n" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;DDR2&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_ddr2_cke</spirit:name>
        <spirit:displayName>clock enable</spirit:displayName>
        <spirit:description>clock enable</spirit:description>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_DDR2_CKE_WIDTH&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_ddr2_cke" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;DDR2&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_ddr2_cs_n</spirit:name>
        <spirit:displayName>chip select</spirit:displayName>
        <spirit:description>chip select</spirit:description>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_DDR2_CS_WIDTH&apos;)) * spirit:decode(id(&apos;MODELPARAM_VALUE.C5_DDR2_nCS_PER_RANK&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_ddr2_cs_n" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_DDR2_USE_CS_PORT&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_ddr2_dm</spirit:name>
        <spirit:displayName>data mask</spirit:displayName>
        <spirit:description>data mask</spirit:description>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_DDR2_DM_WIDTH&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_ddr2_dm" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_DDR2_USE_DM_PORT&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_ddr2_odt</spirit:name>
        <spirit:displayName>on die termination</spirit:displayName>
        <spirit:description>on die termination</spirit:description>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_DDR2_ODT_WIDTH&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_ddr2_odt" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;DDR2&quot; and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;DDR2&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_DDR2_USE_ODT_PORT&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_ddr2_parity</spirit:name>
        <spirit:displayName>parity bit</spirit:displayName>
        <spirit:description>parity bit</spirit:description>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_ddr2_parity" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_DDR2_REG_CTRL&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_ddr2_dbg_pi_counter_read_val</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">4</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_ddr2_dbg_pi_counter_read_val" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_DDR2_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_ddr2_dbg_byte_sel</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_DDR2_DQS_CNT_WIDTH&apos;)) + 1 )- 1 ">1</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_ddr2_dbg_byte_sel" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_DDR2_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_ddr2_dbg_sel_pi_incdec</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_ddr2_dbg_sel_pi_incdec" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_DDR2_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_ddr2_dbg_pi_f_inc</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_ddr2_dbg_pi_f_inc" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_DDR2_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_ddr2_dbg_pi_f_dec</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_ddr2_dbg_pi_f_dec" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_DDR2_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_ddr2_dbg_sel_po_incdec</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_ddr2_dbg_sel_po_incdec" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_DDR2_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_ddr2_dbg_po_f_inc</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_ddr2_dbg_po_f_inc" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_DDR2_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_ddr2_dbg_po_f_stg23_sel</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_ddr2_dbg_po_f_stg23_sel" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_DDR2_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_ddr2_dbg_po_f_dec</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_ddr2_dbg_po_f_dec" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_DDR2_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_ddr2_dbg_po_counter_read_val</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">7</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_ddr2_dbg_po_counter_read_val" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_DDR2_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_ddr2_ila_wrpath</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">254</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_ddr2_ila_wrpath" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_DDR2_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_ddr2_ila_rdpath</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">1022</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_ddr2_ila_rdpath" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_DDR2_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_ddr2_ila_basic</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">126</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_ddr2_ila_basic" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_DDR2_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_ddr2_vio_sync_out</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">34</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_ddr2_vio_sync_out" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_DDR2_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_lpddr2_dq</spirit:name>
        <spirit:displayName>Data</spirit:displayName>
        <spirit:description>Data</spirit:description>
        <spirit:wire>
          <spirit:direction>inout</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_LPDDR2_DQ_WIDTH&apos;)) )- 1 ">7</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_lpddr2_dq" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_lpddr2_dqs_p</spirit:name>
        <spirit:displayName>Data Strobe</spirit:displayName>
        <spirit:description>Data Strobe</spirit:description>
        <spirit:wire>
          <spirit:direction>inout</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_LPDDR2_DQS_WIDTH&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_lpddr2_dqs_p" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_lpddr2_dqs_n</spirit:name>
        <spirit:displayName>Data Strobe</spirit:displayName>
        <spirit:description>Data Strobe</spirit:description>
        <spirit:wire>
          <spirit:direction>inout</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_LPDDR2_DQS_WIDTH&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_lpddr2_dqs_n" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_lpddr2_ca</spirit:name>
        <spirit:displayName>Address</spirit:displayName>
        <spirit:description>Address</spirit:description>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">9</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_lpddr2_ca" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_lpddr2_ck_p</spirit:name>
        <spirit:displayName>clock to memory device</spirit:displayName>
        <spirit:description>clock to memory device</spirit:description>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_LPDDR2_CK_WIDTH&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_lpddr2_ck_p" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_lpddr2_ck_n</spirit:name>
        <spirit:displayName>clock to memory device</spirit:displayName>
        <spirit:description>clock to memory device</spirit:description>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_LPDDR2_CK_WIDTH&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_lpddr2_ck_n" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_lpddr2_cke</spirit:name>
        <spirit:displayName>clock enable</spirit:displayName>
        <spirit:description>clock enable</spirit:description>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_LPDDR2_CKE_WIDTH&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_lpddr2_cke" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_lpddr2_cs_n</spirit:name>
        <spirit:displayName>chip select</spirit:displayName>
        <spirit:description>chip select</spirit:description>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_LPDDR2_CS_WIDTH&apos;)) * spirit:decode(id(&apos;MODELPARAM_VALUE.C5_LPDDR2_nCS_PER_RANK&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_lpddr2_cs_n" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_LPDDR2_USE_CS_PORT&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_lpddr2_dm</spirit:name>
        <spirit:displayName>data mask</spirit:displayName>
        <spirit:description>data mask</spirit:description>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_LPDDR2_DM_WIDTH&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_lpddr2_dm" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_LPDDR2_USE_DM_PORT&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_lpddr2_parity</spirit:name>
        <spirit:displayName>parity bit</spirit:displayName>
        <spirit:description>parity bit</spirit:description>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_lpddr2_parity" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_LPDDR2_REG_CTRL&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_lpddr2_dbg_pi_counter_read_val</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">4</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_lpddr2_dbg_pi_counter_read_val" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_LPDDR2_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_lpddr2_dbg_byte_sel</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_LPDDR2_DQS_CNT_WIDTH&apos;)) + 1 )- 1 ">1</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_lpddr2_dbg_byte_sel" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_LPDDR2_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_lpddr2_dbg_sel_pi_incdec</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_lpddr2_dbg_sel_pi_incdec" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_LPDDR2_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_lpddr2_dbg_pi_f_inc</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_lpddr2_dbg_pi_f_inc" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_LPDDR2_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_lpddr2_dbg_pi_f_dec</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_lpddr2_dbg_pi_f_dec" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_LPDDR2_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_lpddr2_dbg_sel_po_incdec</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_lpddr2_dbg_sel_po_incdec" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_LPDDR2_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_lpddr2_dbg_po_f_inc</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_lpddr2_dbg_po_f_inc" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_LPDDR2_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_lpddr2_dbg_po_f_stg23_sel</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_lpddr2_dbg_po_f_stg23_sel" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_LPDDR2_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_lpddr2_dbg_po_f_dec</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_lpddr2_dbg_po_f_dec" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_LPDDR2_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_lpddr2_dbg_po_counter_read_val</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">7</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_lpddr2_dbg_po_counter_read_val" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_LPDDR2_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_lpddr2_ila_wrpath</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">254</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_lpddr2_ila_wrpath" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_LPDDR2_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_lpddr2_ila_rdpath</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">1022</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_lpddr2_ila_rdpath" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_LPDDR2_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_lpddr2_ila_basic</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">126</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_lpddr2_ila_basic" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_LPDDR2_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_lpddr2_vio_sync_out</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">34</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_lpddr2_vio_sync_out" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_LPDDR2_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_dbg_byte_sel</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_DQS_CNT_WIDTH&apos;)) + 1 )- 1 ">1</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_dbg_byte_sel" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;DDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_dbg_sel_pi_incdec</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_dbg_sel_pi_incdec" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;DDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_dbg_pi_f_inc</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_dbg_pi_f_inc" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;DDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_dbg_pi_f_dec</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_dbg_pi_f_dec" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;DDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_dbg_sel_po_incdec</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_dbg_sel_po_incdec" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;DDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_dbg_po_f_inc</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_dbg_po_f_inc" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;DDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_dbg_po_f_stg23_sel</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_dbg_po_f_stg23_sel" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;DDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_dbg_po_f_dec</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_dbg_po_f_dec" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;DDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_dbg_po_counter_read_val</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">7</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_dbg_po_counter_read_val" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;DDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_app_addr</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_DDRX_ADDR_WIDTH&apos;)) )- 1 ">7</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_app_addr" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;DDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_app_cmd</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">2</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_app_cmd" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;DDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_app_en</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_app_en" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;DDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_app_wdf_data</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_DDRX_nCK_PER_CLK&apos;)) * 2 * spirit:decode(id(&apos;MODELPARAM_VALUE.C5_DDRX_DATA_WIDTH&apos;)) )- 1 ">31</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_app_wdf_data" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;DDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_app_wdf_end</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_app_wdf_end" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;DDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_app_wdf_mask</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_DDRX_nCK_PER_CLK&apos;)) * 2 * spirit:decode(id(&apos;MODELPARAM_VALUE.C5_DDRX_DATA_WIDTH&apos;)) / 8 )- 1 ">3</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_app_wdf_mask" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;DDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_app_wdf_wren</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_app_wdf_wren" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;DDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_app_correct_en_i</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_app_correct_en_i" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;DDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_ECC&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_app_rd_data</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_DDRX_nCK_PER_CLK&apos;)) * 2 * spirit:decode(id(&apos;MODELPARAM_VALUE.C5_DDRX_DATA_WIDTH&apos;)) )- 1 ">31</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_app_rd_data" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;DDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_app_rd_data_end</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_app_rd_data_end" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;DDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_app_rd_data_valid</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_app_rd_data_valid" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;DDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_app_rdy</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_app_rdy" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;DDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_app_wdf_rdy</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_app_wdf_rdy" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;DDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_app_sr_req</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_app_sr_req" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;DDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_app_sr_active</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_app_sr_active" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;DDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_app_ref_req</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_app_ref_req" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;DDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_app_ref_ack</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_app_ref_ack" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;DDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_app_zq_req</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_app_zq_req" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;DDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_app_zq_ack</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_app_zq_ack" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;DDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_app_raw_not_ecc</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( 2 * spirit:decode(id(&apos;MODELPARAM_VALUE.C5_DDRX_nCK_PER_CLK&apos;)) )- 1 ">3</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_app_raw_not_ecc" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;DDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_ECC&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_app_ecc_multiple_err</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( 2 * spirit:decode(id(&apos;MODELPARAM_VALUE.C5_DDRX_nCK_PER_CLK&apos;)) )- 1 ">3</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_app_ecc_multiple_err" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;DDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_ECC&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_ddr3_app_addr</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_DDR3_ADDR_WIDTH&apos;)) )- 1 ">7</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_ddr3_app_addr" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_ddr3_app_cmd</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">2</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_ddr3_app_cmd" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_ddr3_app_en</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_ddr3_app_en" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_ddr3_app_wdf_data</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_DDR3_nCK_PER_CLK&apos;)) * 2 * spirit:decode(id(&apos;MODELPARAM_VALUE.C5_DDR3_DATA_WIDTH&apos;)) )- 1 ">31</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_ddr3_app_wdf_data" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_ddr3_app_wdf_end</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_ddr3_app_wdf_end" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_ddr3_app_wdf_mask</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_DDR3_nCK_PER_CLK&apos;)) * 2 * spirit:decode(id(&apos;MODELPARAM_VALUE.C5_DDR3_DATA_WIDTH&apos;)) / 8 )- 1 ">3</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_ddr3_app_wdf_mask" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_ddr3_app_wdf_wren</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_ddr3_app_wdf_wren" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_ddr3_app_correct_en_i</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_ddr3_app_correct_en_i" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_ECC&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_ddr3_app_rd_data</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_DDR3_nCK_PER_CLK&apos;)) * 2 * spirit:decode(id(&apos;MODELPARAM_VALUE.C5_DDR3_DATA_WIDTH&apos;)) )- 1 ">31</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_ddr3_app_rd_data" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_ddr3_app_rd_data_end</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_ddr3_app_rd_data_end" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_ddr3_app_rd_data_valid</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_ddr3_app_rd_data_valid" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_ddr3_app_rdy</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_ddr3_app_rdy" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_ddr3_app_wdf_rdy</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_ddr3_app_wdf_rdy" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_ddr3_app_sr_req</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_ddr3_app_sr_req" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_ddr3_app_sr_active</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_ddr3_app_sr_active" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_ddr3_app_ref_req</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_ddr3_app_ref_req" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_ddr3_app_ref_ack</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_ddr3_app_ref_ack" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_ddr3_app_zq_req</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_ddr3_app_zq_req" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_ddr3_app_zq_ack</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_ddr3_app_zq_ack" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_ddr3_app_raw_not_ecc</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( 2 * spirit:decode(id(&apos;MODELPARAM_VALUE.C5_DDR3_nCK_PER_CLK&apos;)) )- 1 ">3</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_ddr3_app_raw_not_ecc" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_ECC&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_ddr3_app_ecc_multiple_err</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( 2 * spirit:decode(id(&apos;MODELPARAM_VALUE.C5_DDR3_nCK_PER_CLK&apos;)) )- 1 ">3</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_ddr3_app_ecc_multiple_err" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_ECC&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_ddr2_app_addr</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_DDR2_ADDR_WIDTH&apos;)) )- 1 ">7</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_ddr2_app_addr" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_ddr2_app_cmd</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">2</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_ddr2_app_cmd" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_ddr2_app_en</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_ddr2_app_en" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_ddr2_app_wdf_data</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_DDR2_nCK_PER_CLK&apos;)) * 2 * spirit:decode(id(&apos;MODELPARAM_VALUE.C5_DDR2_DATA_WIDTH&apos;)) )- 1 ">31</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_ddr2_app_wdf_data" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_ddr2_app_wdf_end</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_ddr2_app_wdf_end" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_ddr2_app_wdf_mask</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_DDR2_nCK_PER_CLK&apos;)) * 2 * spirit:decode(id(&apos;MODELPARAM_VALUE.C5_DDR2_DATA_WIDTH&apos;)) / 8 )- 1 ">3</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_ddr2_app_wdf_mask" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_ddr2_app_wdf_wren</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_ddr2_app_wdf_wren" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_ddr2_app_correct_en_i</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_ddr2_app_correct_en_i" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_ECC&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_ddr2_app_rd_data</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_DDR2_nCK_PER_CLK&apos;)) * 2 * spirit:decode(id(&apos;MODELPARAM_VALUE.C5_DDR2_DATA_WIDTH&apos;)) )- 1 ">31</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_ddr2_app_rd_data" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_ddr2_app_rd_data_end</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_ddr2_app_rd_data_end" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_ddr2_app_rd_data_valid</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_ddr2_app_rd_data_valid" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_ddr2_app_rdy</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_ddr2_app_rdy" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_ddr2_app_wdf_rdy</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_ddr2_app_wdf_rdy" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_ddr2_app_sr_req</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_ddr2_app_sr_req" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_ddr2_app_sr_active</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_ddr2_app_sr_active" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_ddr2_app_ref_req</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_ddr2_app_ref_req" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_ddr2_app_ref_ack</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_ddr2_app_ref_ack" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_ddr2_app_zq_req</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_ddr2_app_zq_req" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_ddr2_app_zq_ack</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_ddr2_app_zq_ack" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_ddr2_app_raw_not_ecc</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( 2 * spirit:decode(id(&apos;MODELPARAM_VALUE.C5_DDR2_nCK_PER_CLK&apos;)) )- 1 ">3</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_ddr2_app_raw_not_ecc" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_ECC&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_ddr2_app_ecc_multiple_err</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( 2 * spirit:decode(id(&apos;MODELPARAM_VALUE.C5_DDR2_nCK_PER_CLK&apos;)) )- 1 ">3</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_ddr2_app_ecc_multiple_err" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_ECC&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_lpddr2_app_addr</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_LPDDR2_ADDR_WIDTH&apos;)) )- 1 ">7</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_lpddr2_app_addr" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_lpddr2_app_cmd</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">2</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_lpddr2_app_cmd" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_lpddr2_app_en</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_lpddr2_app_en" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_lpddr2_app_wdf_data</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_LPDDR2_nCK_PER_CLK&apos;)) * 2 * spirit:decode(id(&apos;MODELPARAM_VALUE.C5_LPDDR2_DATA_WIDTH&apos;)) )- 1 ">31</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_lpddr2_app_wdf_data" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_lpddr2_app_wdf_end</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_lpddr2_app_wdf_end" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_lpddr2_app_wdf_mask</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_LPDDR2_nCK_PER_CLK&apos;)) * 2 * spirit:decode(id(&apos;MODELPARAM_VALUE.C5_LPDDR2_DATA_WIDTH&apos;)) / 8 )- 1 ">3</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_lpddr2_app_wdf_mask" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_lpddr2_app_wdf_wren</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_lpddr2_app_wdf_wren" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_lpddr2_app_correct_en_i</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_lpddr2_app_correct_en_i" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_ECC&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_lpddr2_app_rd_data</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_LPDDR2_nCK_PER_CLK&apos;)) * 2 * spirit:decode(id(&apos;MODELPARAM_VALUE.C5_LPDDR2_DATA_WIDTH&apos;)) )- 1 ">31</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_lpddr2_app_rd_data" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_lpddr2_app_rd_data_end</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_lpddr2_app_rd_data_end" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_lpddr2_app_rd_data_valid</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_lpddr2_app_rd_data_valid" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_lpddr2_app_rdy</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_lpddr2_app_rdy" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_lpddr2_app_wdf_rdy</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_lpddr2_app_wdf_rdy" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_lpddr2_app_sr_req</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_lpddr2_app_sr_req" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_lpddr2_app_sr_active</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_lpddr2_app_sr_active" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_lpddr2_app_ref_req</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_lpddr2_app_ref_req" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_lpddr2_app_ref_ack</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_lpddr2_app_ref_ack" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_lpddr2_app_zq_req</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_lpddr2_app_zq_req" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_lpddr2_app_zq_ack</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_lpddr2_app_zq_ack" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_lpddr2_app_raw_not_ecc</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( 2 * spirit:decode(id(&apos;MODELPARAM_VALUE.C5_LPDDR2_nCK_PER_CLK&apos;)) )- 1 ">3</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_lpddr2_app_raw_not_ecc" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_ECC&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_lpddr2_app_ecc_multiple_err</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( 2 * spirit:decode(id(&apos;MODELPARAM_VALUE.C5_LPDDR2_nCK_PER_CLK&apos;)) )- 1 ">3</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_lpddr2_app_ecc_multiple_err" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_ECC&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_ui_clk_sync_rst</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_ui_clk_sync_rst" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;DDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;RLDII&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;RLDIII&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_ddr3_ui_clk_sync_rst</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_ddr3_ui_clk_sync_rst" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;DDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;RLDII&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;RLDIII&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_ddr2_ui_clk_sync_rst</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_ddr2_ui_clk_sync_rst" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;DDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;RLDII&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;RLDIII&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_lpddr2_ui_clk_sync_rst</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_lpddr2_ui_clk_sync_rst" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;DDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;RLDII&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;RLDIII&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_qdriip_ui_clk_sync_rst</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_qdriip_ui_clk_sync_rst" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;DDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;RLDII&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;RLDIII&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_rldii_ui_clk_sync_rst</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_rldii_ui_clk_sync_rst" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;RLDII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;DDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;RLDII&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;RLDIII&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_rldiii_ui_clk_sync_rst</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_rldiii_ui_clk_sync_rst" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;RLDIII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;DDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;RLDII&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;RLDIII&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_ui_clk</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_ui_clk" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;DDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;RLDII&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;RLDIII&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_ui_addn_clk_0</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_ui_addn_clk_0" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_UI_EXTRA_CLOCKS&apos;)) = &quot;TRUE&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MMCM_CLKOUT0_EN&apos;)) = &quot;TRUE&quot; ) and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;DDR2&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_ui_addn_clk_1</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_ui_addn_clk_1" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_UI_EXTRA_CLOCKS&apos;)) = &quot;TRUE&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MMCM_CLKOUT1_EN&apos;)) = &quot;TRUE&quot; ) and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;DDR2&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_ui_addn_clk_2</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_ui_addn_clk_2" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_UI_EXTRA_CLOCKS&apos;)) = &quot;TRUE&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MMCM_CLKOUT2_EN&apos;)) = &quot;TRUE&quot; ) and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;DDR2&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_ui_addn_clk_3</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_ui_addn_clk_3" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_UI_EXTRA_CLOCKS&apos;)) = &quot;TRUE&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MMCM_CLKOUT3_EN&apos;)) = &quot;TRUE&quot; ) and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;DDR2&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_ui_addn_clk_4</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_ui_addn_clk_4" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_UI_EXTRA_CLOCKS&apos;)) = &quot;TRUE&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MMCM_CLKOUT4_EN&apos;)) = &quot;TRUE&quot; ) and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;DDR2&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_s_axi_ctrl_awvalid</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_s_axi_ctrl_awvalid" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_USE_AXI&apos;)) = 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_ECC&apos;)) = &quot;ON&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_s_axi_ctrl_awready</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_s_axi_ctrl_awready" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_USE_AXI&apos;)) = 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_ECC&apos;)) = &quot;ON&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_s_axi_ctrl_awaddr</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_C_S_AXI_CTRL_ADDR_WIDTH&apos;)) )- 1 ">31</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_s_axi_ctrl_awaddr" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_USE_AXI&apos;)) = 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_ECC&apos;)) = &quot;ON&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_s_axi_ctrl_wvalid</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_s_axi_ctrl_wvalid" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_USE_AXI&apos;)) = 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_ECC&apos;)) = &quot;ON&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_s_axi_ctrl_wready</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_s_axi_ctrl_wready" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_USE_AXI&apos;)) = 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_ECC&apos;)) = &quot;ON&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_s_axi_ctrl_wdata</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_C_S_AXI_CTRL_DATA_WIDTH&apos;)) )- 1 ">31</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_s_axi_ctrl_wdata" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_USE_AXI&apos;)) = 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_ECC&apos;)) = &quot;ON&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_s_axi_ctrl_bvalid</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_s_axi_ctrl_bvalid" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_USE_AXI&apos;)) = 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_ECC&apos;)) = &quot;ON&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_s_axi_ctrl_bready</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_s_axi_ctrl_bready" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_USE_AXI&apos;)) = 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_ECC&apos;)) = &quot;ON&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_s_axi_ctrl_bresp</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">1</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_s_axi_ctrl_bresp" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_USE_AXI&apos;)) = 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_ECC&apos;)) = &quot;ON&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_s_axi_ctrl_arvalid</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_s_axi_ctrl_arvalid" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_USE_AXI&apos;)) = 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_ECC&apos;)) = &quot;ON&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_s_axi_ctrl_arready</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_s_axi_ctrl_arready" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_USE_AXI&apos;)) = 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_ECC&apos;)) = &quot;ON&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_s_axi_ctrl_araddr</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_C_S_AXI_CTRL_ADDR_WIDTH&apos;)) )- 1 ">31</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_s_axi_ctrl_araddr" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_USE_AXI&apos;)) = 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_ECC&apos;)) = &quot;ON&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_s_axi_ctrl_rvalid</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_s_axi_ctrl_rvalid" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_USE_AXI&apos;)) = 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_ECC&apos;)) = &quot;ON&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_s_axi_ctrl_rready</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_s_axi_ctrl_rready" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_USE_AXI&apos;)) = 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_ECC&apos;)) = &quot;ON&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_s_axi_ctrl_rdata</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_C_S_AXI_CTRL_DATA_WIDTH&apos;)) )- 1 ">31</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_s_axi_ctrl_rdata" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_USE_AXI&apos;)) = 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_ECC&apos;)) = &quot;ON&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_s_axi_ctrl_rresp</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">1</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_s_axi_ctrl_rresp" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_USE_AXI&apos;)) = 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_ECC&apos;)) = &quot;ON&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_s_axi_awid</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_C_S_AXI_ID_WIDTH&apos;)) )- 1 ">3</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
          <spirit:driver>
            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
          </spirit:driver>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_s_axi_awid" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_s_axi_awaddr</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_C_S_AXI_ADDR_WIDTH&apos;)) )- 1 ">31</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_s_axi_awaddr" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_s_axi_awlen</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">7</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_s_axi_awlen" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_s_axi_awsize</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">2</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_s_axi_awsize" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_s_axi_awburst</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">1</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_s_axi_awburst" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_s_axi_awlock</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
          <spirit:driver>
            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
          </spirit:driver>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_s_axi_awlock" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_s_axi_awcache</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">3</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
          <spirit:driver>
            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
          </spirit:driver>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_s_axi_awcache" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_s_axi_awprot</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">2</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
          <spirit:driver>
            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
          </spirit:driver>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_s_axi_awprot" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_s_axi_awqos</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">3</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
          <spirit:driver>
            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
          </spirit:driver>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_s_axi_awqos" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_s_axi_awvalid</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_s_axi_awvalid" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_s_axi_awready</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_s_axi_awready" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_s_axi_wdata</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_C_S_AXI_DATA_WIDTH&apos;)) )- 1 ">31</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_s_axi_wdata" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_s_axi_wstrb</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_C_S_AXI_DATA_WIDTH&apos;)) / 8 )- 1 ">3</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_s_axi_wstrb" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_s_axi_wlast</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_s_axi_wlast" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_s_axi_wvalid</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_s_axi_wvalid" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_s_axi_wready</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_s_axi_wready" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_s_axi_bready</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_s_axi_bready" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_s_axi_bid</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_C_S_AXI_ID_WIDTH&apos;)) )- 1 ">3</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_s_axi_bid" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_s_axi_bresp</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">1</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_s_axi_bresp" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_s_axi_bvalid</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_s_axi_bvalid" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_s_axi_arid</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_C_S_AXI_ID_WIDTH&apos;)) )- 1 ">3</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
          <spirit:driver>
            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
          </spirit:driver>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_s_axi_arid" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_s_axi_araddr</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_C_S_AXI_ADDR_WIDTH&apos;)) )- 1 ">31</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_s_axi_araddr" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_s_axi_arlen</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">7</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_s_axi_arlen" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_s_axi_arsize</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">2</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_s_axi_arsize" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_s_axi_arburst</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">1</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_s_axi_arburst" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_s_axi_arlock</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
          <spirit:driver>
            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
          </spirit:driver>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_s_axi_arlock" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_s_axi_arcache</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">3</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
          <spirit:driver>
            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
          </spirit:driver>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_s_axi_arcache" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_s_axi_arprot</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">2</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
          <spirit:driver>
            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
          </spirit:driver>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_s_axi_arprot" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_s_axi_arqos</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">3</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
          <spirit:driver>
            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
          </spirit:driver>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_s_axi_arqos" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_s_axi_arvalid</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_s_axi_arvalid" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_s_axi_arready</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_s_axi_arready" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_s_axi_rready</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_s_axi_rready" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_s_axi_rid</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_C_S_AXI_ID_WIDTH&apos;)) )- 1 ">3</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_s_axi_rid" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_s_axi_rdata</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_C_S_AXI_DATA_WIDTH&apos;)) )- 1 ">31</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_s_axi_rdata" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_s_axi_rresp</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">1</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_s_axi_rresp" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_s_axi_rlast</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_s_axi_rlast" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_s_axi_rvalid</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_s_axi_rvalid" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_interrupt</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_interrupt" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_USE_AXI&apos;)) = 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_ECC&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_mmcm_locked</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_mmcm_locked" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_qdriip_cq_p</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_QDRIIP_NUM_DEVICES&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_qdriip_cq_p" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_qdriip_cq_n</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_QDRIIP_NUM_DEVICES&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_qdriip_cq_n" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_qdriip_qvld</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_QDRIIP_NUM_DEVICES&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_qdriip_qvld" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_qdriip_q</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_QDRIIP_DATA_WIDTH&apos;)) )- 1 ">17</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_qdriip_q" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_qdriip_k_p</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_QDRIIP_NUM_DEVICES&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_qdriip_k_p" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_qdriip_k_n</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_QDRIIP_NUM_DEVICES&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_qdriip_k_n" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_qdriip_d</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_QDRIIP_DATA_WIDTH&apos;)) )- 1 ">17</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_qdriip_d" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_qdriip_sa</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_QDRIIP_ADDR_WIDTH&apos;)) )- 1 ">28</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_qdriip_sa" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_qdriip_w_n</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_qdriip_w_n" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_qdriip_r_n</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_qdriip_r_n" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_qdriip_bw_n</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_QDRIIP_BW_WIDTH&apos;)) )- 1 ">7</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_qdriip_bw_n" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_qdriip_dll_off_n</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_qdriip_dll_off_n" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_qdriip_dbg_pi_counter_read_val</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">4</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_qdriip_dbg_pi_counter_read_val" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_QDRIIP_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_qdriip_dbg_win_inc</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_qdriip_dbg_win_inc" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_QDRIIP_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_qdriip_dbg_win_dec</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_qdriip_dbg_win_dec" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_QDRIIP_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_qdriip_dbg_win_active</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_qdriip_dbg_win_active" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_QDRIIP_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_qdriip_dbg_win_current_byte</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">2</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_qdriip_dbg_win_current_byte" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_QDRIIP_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_qdriip_ila0_data</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">254</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_qdriip_ila0_data" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_QDRIIP_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_qdriip_ila0_trig</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">6</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_qdriip_ila0_trig" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_QDRIIP_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_qdriip_ila1_data</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">269</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_qdriip_ila1_data" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_QDRIIP_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_qdriip_ila1_trig</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">14</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_qdriip_ila1_trig" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_QDRIIP_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_qdriip_vio2_async_in</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">198</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_qdriip_vio2_async_in" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_QDRIIP_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_qdriip_vio2_sync_out</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">34</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_qdriip_vio2_sync_out" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_QDRIIP_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_app_wr_cmd0</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_app_wr_cmd0" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_app_wr_addr0</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_QDRIIP_ADDR_WIDTH&apos;)) )- 1 ">28</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_app_wr_addr0" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_app_wr_data0</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_QDRIIP_BURST_LEN&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_app_wr_data0" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_app_wr_bw_n0</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_QDRIIP_BURST_LEN&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_app_wr_bw_n0" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_app_rd_cmd0</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_app_rd_cmd0" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_app_rd_addr0</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_QDRIIP_ADDR_WIDTH&apos;)) )- 1 ">28</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_app_rd_addr0" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_app_rd_valid0</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_app_rd_valid0" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_app_rd_data0</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_QDRIIP_BURST_LEN&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_app_rd_data0" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_app_wr_cmd1</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_app_wr_cmd1" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_app_wr_addr1</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_QDRIIP_ADDR_WIDTH&apos;)) )- 1 ">28</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_app_wr_addr1" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_app_wr_data1</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" (( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_QDRIIP_DATA_WIDTH&apos;)) * 2 ))- 1 ">35</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_app_wr_data1" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_app_wr_bw_n1</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" (( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_QDRIIP_BW_WIDTH&apos;)) * 2 ))- 1 ">15</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_app_wr_bw_n1" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_app_rd_cmd1</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_app_rd_cmd1" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_app_rd_addr1</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_QDRIIP_ADDR_WIDTH&apos;)) )- 1 ">28</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_app_rd_addr1" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_app_rd_valid1</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_app_rd_valid1" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_app_rd_data1</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" (( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_QDRIIP_DATA_WIDTH&apos;)) * 2 ))- 1 ">35</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_app_rd_data1" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_clk</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_clk" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_rst_clk</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_rst_clk" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_qdriip_app_wr_cmd0</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_qdriip_app_wr_cmd0" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_qdriip_app_wr_addr0</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_QDRIIP_ADDR_WIDTH&apos;)) )- 1 ">28</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_qdriip_app_wr_addr0" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_qdriip_app_wr_data0</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_QDRIIP_BURST_LEN&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_qdriip_app_wr_data0" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_qdriip_app_wr_bw_n0</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_QDRIIP_BURST_LEN&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_qdriip_app_wr_bw_n0" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_qdriip_app_rd_cmd0</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_qdriip_app_rd_cmd0" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_qdriip_app_rd_addr0</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_QDRIIP_ADDR_WIDTH&apos;)) )- 1 ">28</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_qdriip_app_rd_addr0" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_qdriip_app_rd_valid0</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_qdriip_app_rd_valid0" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_qdriip_app_rd_data0</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_QDRIIP_BURST_LEN&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_qdriip_app_rd_data0" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_qdriip_app_wr_cmd1</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_qdriip_app_wr_cmd1" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_qdriip_app_wr_addr1</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_QDRIIP_ADDR_WIDTH&apos;)) )- 1 ">28</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_qdriip_app_wr_addr1" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_qdriip_app_wr_data1</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" (( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_QDRIIP_DATA_WIDTH&apos;)) * 2 ))- 1 ">35</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_qdriip_app_wr_data1" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_qdriip_app_wr_bw_n1</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" (( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_QDRIIP_BW_WIDTH&apos;)) * 2 ))- 1 ">15</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_qdriip_app_wr_bw_n1" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_qdriip_app_rd_cmd1</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_qdriip_app_rd_cmd1" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_qdriip_app_rd_addr1</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_QDRIIP_ADDR_WIDTH&apos;)) )- 1 ">28</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_qdriip_app_rd_addr1" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_qdriip_app_rd_valid1</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_qdriip_app_rd_valid1" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_qdriip_app_rd_data1</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" (( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_QDRIIP_DATA_WIDTH&apos;)) * 2 ))- 1 ">35</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_qdriip_app_rd_data1" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_qdriip_clk</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_qdriip_clk" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_qdriip_rst_clk</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_qdriip_rst_clk" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_rldii_qk_p</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_RLDII_QK_WIDTH&apos;)) )- 1 ">7</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_rldii_qk_p" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;RLDII&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_rldii_qk_n</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_RLDII_QK_WIDTH&apos;)) )- 1 ">7</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_rldii_qk_n" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;RLDII&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_rldii_dq</spirit:name>
        <spirit:wire>
          <spirit:direction>inout</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_RLDII_DATA_WIDTH&apos;)) )- 1 ">17</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_rldii_dq" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;RLDII&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_rldii_dm</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_RLDII_DM_WIDTH&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_rldii_dm" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;RLDII&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_rldii_dk_p</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_RLDII_DK_WIDTH&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_rldii_dk_p" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;RLDII&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_rldii_dk_n</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_RLDII_DK_WIDTH&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_rldii_dk_n" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;RLDII&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_rldii_ck_p</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_RLDII_NUM_DEVICES&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_rldii_ck_p" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;RLDII&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_rldii_ck_n</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_RLDII_NUM_DEVICES&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_rldii_ck_n" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;RLDII&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_rldii_cs_n</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_RLDII_NUM_DEVICES&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_rldii_cs_n" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;RLDII&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_rldii_a</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_RLDII_RLD_ADDR_WIDTH&apos;)) )- 1 ">28</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_rldii_a" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;RLDII&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_rldii_ba</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_RLDII_BANK_WIDTH&apos;)) )- 1 ">1</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_rldii_ba" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;RLDII&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_rldii_qvld</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_RLDII_QVLD_WIDTH&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_rldii_qvld" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;RLDII&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_rldii_we_n</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_rldii_we_n" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;RLDII&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_rldii_ref_n</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_rldii_ref_n" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;RLDII&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_rldii_reset_n</spirit:name>
        <spirit:displayName>reset to memory device</spirit:displayName>
        <spirit:description>reset to memory device</spirit:description>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_rldii_reset_n" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;RLDII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;RLDIII&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_rldii_dbg_pi_tap_cnt</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">4</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_rldii_dbg_pi_tap_cnt" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;RLDII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_RLDII_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_rldii_dbg_win_inc</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_rldii_dbg_win_inc" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;RLDII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_RLDII_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_rldii_dbg_win_dec</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_rldii_dbg_win_dec" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;RLDII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_RLDII_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_rldii_dbg_win_active</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_rldii_dbg_win_active" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;RLDII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_RLDII_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_rldii_dbg_win_current_byte</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">2</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_rldii_dbg_win_current_byte" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;RLDII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_RLDII_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_rldii_ila0_data</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">638</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_rldii_ila0_data" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;RLDII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_RLDII_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_rldii_ila0_trig</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">30</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_rldii_ila0_trig" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;RLDII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_RLDII_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_rldii_vio1_async_in</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">254</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_rldii_vio1_async_in" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;RLDII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_RLDII_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_rldii_vio1_async_out</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">62</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_rldii_vio1_async_out" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;RLDII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_RLDII_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_rldii_vio1_sync_out</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">62</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_rldii_vio1_sync_out" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;RLDII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_RLDII_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_rldiii_qk_p</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_RLDIII_QK_WIDTH&apos;)) )- 1 ">7</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_rldiii_qk_p" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;RLDIII&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_rldiii_qk_n</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_RLDIII_QK_WIDTH&apos;)) )- 1 ">7</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_rldiii_qk_n" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;RLDIII&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_rldiii_dq</spirit:name>
        <spirit:wire>
          <spirit:direction>inout</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_RLDIII_DATA_WIDTH&apos;)) )- 1 ">17</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_rldiii_dq" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;RLDIII&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_rldiii_dm</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_RLDIII_DM_WIDTH&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_rldiii_dm" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;RLDIII&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_rldiii_dk_p</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_RLDIII_DK_WIDTH&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_rldiii_dk_p" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;RLDIII&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_rldiii_dk_n</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_RLDIII_DK_WIDTH&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_rldiii_dk_n" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;RLDIII&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_rldiii_ck_p</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_RLDIII_NUM_DEVICES&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_rldiii_ck_p" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;RLDIII&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_rldiii_ck_n</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_RLDIII_NUM_DEVICES&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_rldiii_ck_n" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;RLDIII&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_rldiii_cs_n</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_RLDIII_NUM_DEVICES&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_rldiii_cs_n" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;RLDIII&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_rldiii_a</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_RLDIII_RLD_ADDR_WIDTH&apos;)) )- 1 ">28</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_rldiii_a" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;RLDIII&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_rldiii_ba</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_RLDIII_BANK_WIDTH&apos;)) )- 1 ">1</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_rldiii_ba" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;RLDIII&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_rldiii_qvld</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_RLDIII_QVLD_WIDTH&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_rldiii_qvld" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;RLDIII&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_rldiii_we_n</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_rldiii_we_n" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;RLDIII&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_rldiii_ref_n</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_rldiii_ref_n" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;RLDIII&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_rldiii_reset_n</spirit:name>
        <spirit:displayName>reset to memory device</spirit:displayName>
        <spirit:description>reset to memory device</spirit:description>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_rldiii_reset_n" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;RLDIII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;RLDIII&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_dbg_pi_tap_cnt</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">4</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_dbg_pi_tap_cnt" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;RLDIII&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;RLDII&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_rldiii_dbg_pi_tap_cnt</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">4</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_rldiii_dbg_pi_tap_cnt" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;RLDIII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_RLDIII_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_rldiii_dbg_win_inc</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_rldiii_dbg_win_inc" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;RLDIII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_RLDIII_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_rldiii_dbg_win_dec</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_rldiii_dbg_win_dec" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;RLDIII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_RLDIII_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_rldiii_dbg_win_active</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_rldiii_dbg_win_active" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;RLDIII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_RLDIII_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_rldiii_dbg_win_current_byte</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">2</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_rldiii_dbg_win_current_byte" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;RLDIII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_RLDIII_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_rldiii_ila0_data</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">638</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_rldiii_ila0_data" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;RLDIII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_RLDIII_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_rldiii_ila0_trig</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">30</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_rldiii_ila0_trig" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;RLDIII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_RLDIII_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_rldiii_vio1_async_in</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">254</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_rldiii_vio1_async_in" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;RLDIII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_RLDIII_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_rldiii_vio1_async_out</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">62</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_rldiii_vio1_async_out" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;RLDIII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_RLDIII_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_rldiii_vio1_sync_out</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">62</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_rldiii_vio1_sync_out" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;RLDIII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_RLDIII_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_dbg_win_inc</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_dbg_win_inc" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;RLDIII&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;RLDII&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_dbg_win_dec</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_dbg_win_dec" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;RLDIII&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;RLDII&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_dbg_win_active</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_dbg_win_active" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;RLDIII&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;RLDII&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_dbg_win_current_byte</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">2</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_dbg_win_current_byte" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;RLDIII&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;RLDII&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_dbg_pi_counter_read_val</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">4</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_dbg_pi_counter_read_val" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;DDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_user_cmd_en</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_user_cmd_en" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;RLDII&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;RLDIII&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_user_cmd</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_RLDX_CMD_PER_CLK&apos;)) * 2 )- 1 ">1</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_user_cmd" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;RLDII&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;RLDIII&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_user_addr</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_RLDX_ADDR_WIDTH&apos;)) * spirit:decode(id(&apos;MODELPARAM_VALUE.C5_RLDX_CMD_PER_CLK&apos;)) )- 1 ">28</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_user_addr" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;RLDII&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;RLDIII&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_user_ba</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_RLDX_BANK_WIDTH&apos;)) * spirit:decode(id(&apos;MODELPARAM_VALUE.C5_RLDX_CMD_PER_CLK&apos;)) )- 1 ">1</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_user_ba" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;RLDII&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;RLDIII&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_user_wr_en</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_user_wr_en" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;RLDII&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;RLDIII&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_user_wr_data</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_RLDX_DATA_WIDTH&apos;)) * 2 * spirit:decode(id(&apos;MODELPARAM_VALUE.C5_RLDX_nCK_PER_CLK&apos;)) )- 1 ">35</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_user_wr_data" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;RLDII&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;RLDIII&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_user_wr_dm</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_RLDX_DM_WIDTH&apos;)) * 2 * spirit:decode(id(&apos;MODELPARAM_VALUE.C5_RLDX_nCK_PER_CLK&apos;)) )- 1 ">1</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_user_wr_dm" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;RLDII&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;RLDIII&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_user_afifo_empty</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_user_afifo_empty" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;RLDII&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;RLDIII&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_user_afifo_full</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_user_afifo_full" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;RLDII&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;RLDIII&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_user_afifo_aempty</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_user_afifo_aempty" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;RLDII&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;RLDIII&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_user_afifo_afull</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_user_afifo_afull" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;RLDII&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;RLDIII&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_user_wdfifo_empty</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_user_wdfifo_empty" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;RLDII&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;RLDIII&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_user_wdfifo_full</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_user_wdfifo_full" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;RLDII&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;RLDIII&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_user_wdfifo_aempty</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_user_wdfifo_aempty" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;RLDII&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;RLDIII&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_user_wdfifo_afull</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_user_wdfifo_afull" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;RLDII&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;RLDIII&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_user_rd_valid</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_RLDX_nCK_PER_CLK&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_user_rd_valid" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;RLDII&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;RLDIII&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_mem_ck_lock_complete</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_mem_ck_lock_complete" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;RLDII&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;RLDIII&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_user_rd_data</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_RLDX_DATA_WIDTH&apos;)) * 2 * spirit:decode(id(&apos;MODELPARAM_VALUE.C5_RLDX_nCK_PER_CLK&apos;)) )- 1 ">35</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_user_rd_data" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;RLDII&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;RLDIII&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_rldii_user_cmd_en</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_rldii_user_cmd_en" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;RLDII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_rldii_user_cmd</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_RLDII_CMD_PER_CLK&apos;)) * 2 )- 1 ">1</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_rldii_user_cmd" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;RLDII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_rldii_user_addr</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_RLDII_ADDR_WIDTH&apos;)) * spirit:decode(id(&apos;MODELPARAM_VALUE.C5_RLDII_CMD_PER_CLK&apos;)) )- 1 ">28</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_rldii_user_addr" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;RLDII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_rldii_user_ba</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_RLDII_BANK_WIDTH&apos;)) * spirit:decode(id(&apos;MODELPARAM_VALUE.C5_RLDII_CMD_PER_CLK&apos;)) )- 1 ">1</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_rldii_user_ba" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;RLDII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_rldii_user_wr_en</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_rldii_user_wr_en" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;RLDII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_rldii_user_wr_data</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_RLDII_DATA_WIDTH&apos;)) * 2 * spirit:decode(id(&apos;MODELPARAM_VALUE.C5_RLDII_nCK_PER_CLK&apos;)) )- 1 ">35</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_rldii_user_wr_data" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;RLDII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_rldii_user_wr_dm</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_RLDII_DM_WIDTH&apos;)) * 2 * spirit:decode(id(&apos;MODELPARAM_VALUE.C5_RLDII_nCK_PER_CLK&apos;)) )- 1 ">1</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_rldii_user_wr_dm" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;RLDII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_rldii_user_afifo_empty</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_rldii_user_afifo_empty" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;RLDII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_rldii_user_afifo_full</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_rldii_user_afifo_full" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;RLDII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_rldii_user_afifo_aempty</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_rldii_user_afifo_aempty" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;RLDII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_rldii_user_afifo_afull</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_rldii_user_afifo_afull" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;RLDII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_rldii_user_wdfifo_empty</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_rldii_user_wdfifo_empty" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;RLDII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_rldii_user_wdfifo_full</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_rldii_user_wdfifo_full" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;RLDII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_rldii_user_wdfifo_aempty</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_rldii_user_wdfifo_aempty" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;RLDII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_rldii_user_wdfifo_afull</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_rldii_user_wdfifo_afull" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;RLDII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_rldii_user_rd_valid</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_RLDII_nCK_PER_CLK&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_rldii_user_rd_valid" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;RLDII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_rldii_mem_ck_lock_complete</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_rldii_mem_ck_lock_complete" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;RLDII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_rldii_user_rd_data</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_RLDII_DATA_WIDTH&apos;)) * 2 * spirit:decode(id(&apos;MODELPARAM_VALUE.C5_RLDII_nCK_PER_CLK&apos;)) )- 1 ">35</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_rldii_user_rd_data" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;RLDII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_rldiii_user_cmd_en</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_rldiii_user_cmd_en" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;RLDIII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_rldiii_user_cmd</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_RLDIII_CMD_PER_CLK&apos;)) * 2 )- 1 ">1</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_rldiii_user_cmd" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;RLDIII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_rldiii_user_addr</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_RLDIII_ADDR_WIDTH&apos;)) * spirit:decode(id(&apos;MODELPARAM_VALUE.C5_RLDIII_CMD_PER_CLK&apos;)) )- 1 ">28</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_rldiii_user_addr" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;RLDIII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_rldiii_user_ba</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_RLDIII_BANK_WIDTH&apos;)) * spirit:decode(id(&apos;MODELPARAM_VALUE.C5_RLDIII_CMD_PER_CLK&apos;)) )- 1 ">1</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_rldiii_user_ba" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;RLDIII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_rldiii_user_wr_en</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_rldiii_user_wr_en" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;RLDIII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_rldiii_user_wr_data</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_RLDIII_DATA_WIDTH&apos;)) * 2 * spirit:decode(id(&apos;MODELPARAM_VALUE.C5_RLDIII_nCK_PER_CLK&apos;)) )- 1 ">35</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_rldiii_user_wr_data" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;RLDIII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_rldiii_user_wr_dm</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_RLDIII_DM_WIDTH&apos;)) * 2 * spirit:decode(id(&apos;MODELPARAM_VALUE.C5_RLDIII_nCK_PER_CLK&apos;)) )- 1 ">1</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_rldiii_user_wr_dm" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;RLDIII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_rldiii_user_afifo_empty</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_rldiii_user_afifo_empty" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;RLDIII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_rldiii_user_afifo_full</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_rldiii_user_afifo_full" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;RLDIII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_rldiii_user_afifo_aempty</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_rldiii_user_afifo_aempty" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;RLDIII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_rldiii_user_afifo_afull</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_rldiii_user_afifo_afull" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;RLDIII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_rldiii_user_wdfifo_empty</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_rldiii_user_wdfifo_empty" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;RLDIII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_rldiii_user_wdfifo_full</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_rldiii_user_wdfifo_full" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;RLDIII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_rldiii_user_wdfifo_aempty</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_rldiii_user_wdfifo_aempty" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;RLDIII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_rldiii_user_wdfifo_afull</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_rldiii_user_wdfifo_afull" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;RLDIII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_rldiii_user_rd_valid</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_RLDIII_nCK_PER_CLK&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_rldiii_user_rd_valid" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;RLDIII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_rldiii_mem_ck_lock_complete</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_rldiii_mem_ck_lock_complete" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;RLDIII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_rldiii_user_rd_data</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_RLDIII_DATA_WIDTH&apos;)) * 2 * spirit:decode(id(&apos;MODELPARAM_VALUE.C5_RLDIII_nCK_PER_CLK&apos;)) )- 1 ">35</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_rldiii_user_rd_data" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;RLDIII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_sys_clk_p</spirit:name>
        <spirit:displayName>Clock P</spirit:displayName>
        <spirit:description>Clock P</spirit:description>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_sys_clk_p" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_SYSCLK_TYPE&apos;)) = &quot;DIFF&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_IS_CLK_SHARED&apos;)) = &quot;FALSE&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_sys_clk_n</spirit:name>
        <spirit:displayName>Clock P</spirit:displayName>
        <spirit:description>Clock P</spirit:description>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_sys_clk_n" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_SYSCLK_TYPE&apos;)) = &quot;DIFF&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_IS_CLK_SHARED&apos;)) = &quot;FALSE&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_sys_clk_i</spirit:name>
        <spirit:displayName>Clock P</spirit:displayName>
        <spirit:description>Clock P</spirit:description>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_sys_clk_i" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_SYSCLK_TYPE&apos;)) != &quot;DIFF&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C5_IS_CLK_SHARED&apos;)) = &quot;FALSE&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_init_calib_complete</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_init_calib_complete" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c5_aresetn</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c5_aresetn" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 5 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C5_MEM_TYPE&apos;)) = &quot;DDR2&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_ddr3_dq</spirit:name>
        <spirit:displayName>Data</spirit:displayName>
        <spirit:description>Data</spirit:description>
        <spirit:wire>
          <spirit:direction>inout</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_DDR3_DQ_WIDTH&apos;)) )- 1 ">7</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_ddr3_dq" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;DDR3&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_ddr3_dqs_p</spirit:name>
        <spirit:displayName>Data Strobe</spirit:displayName>
        <spirit:description>Data Strobe</spirit:description>
        <spirit:wire>
          <spirit:direction>inout</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_DDR3_DQS_WIDTH&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_ddr3_dqs_p" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;DDR3&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_ddr3_dqs_n</spirit:name>
        <spirit:displayName>Data Strobe</spirit:displayName>
        <spirit:description>Data Strobe</spirit:description>
        <spirit:wire>
          <spirit:direction>inout</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_DDR3_DQS_WIDTH&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_ddr3_dqs_n" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;DDR3&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_ddr3_addr</spirit:name>
        <spirit:displayName>Address</spirit:displayName>
        <spirit:description>Address</spirit:description>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_DDR3_ROW_WIDTH&apos;)) )- 1 ">13</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_ddr3_addr" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;DDR3&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_ddr3_ba</spirit:name>
        <spirit:displayName>Bank Address</spirit:displayName>
        <spirit:description>Bank Address</spirit:description>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_DDR3_BANK_WIDTH&apos;)) )- 1 ">2</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_ddr3_ba" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;DDR3&quot; and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;DDR2&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_ddr3_ras_n</spirit:name>
        <spirit:displayName>row address strobe</spirit:displayName>
        <spirit:description>row address strobe</spirit:description>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_ddr3_ras_n" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;DDR3&quot; and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;DDR2&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_ddr3_cas_n</spirit:name>
        <spirit:displayName>column address strobe</spirit:displayName>
        <spirit:description>column address strobe</spirit:description>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_ddr3_cas_n" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;DDR3&quot; and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;DDR2&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_ddr3_we_n</spirit:name>
        <spirit:displayName>write enable</spirit:displayName>
        <spirit:description>write enable</spirit:description>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_ddr3_we_n" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;DDR3&quot; and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;DDR2&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_ddr3_reset_n</spirit:name>
        <spirit:displayName>reset to memory device</spirit:displayName>
        <spirit:description>reset to memory device</spirit:description>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_ddr3_reset_n" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;DDR3&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_ddr3_ck_p</spirit:name>
        <spirit:displayName>clock to memory device</spirit:displayName>
        <spirit:description>clock to memory device</spirit:description>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_DDR3_CK_WIDTH&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_ddr3_ck_p" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;DDR3&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_ddr3_ck_n</spirit:name>
        <spirit:displayName>clock to memory device</spirit:displayName>
        <spirit:description>clock to memory device</spirit:description>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_DDR3_CK_WIDTH&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_ddr3_ck_n" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;DDR3&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_ddr3_cke</spirit:name>
        <spirit:displayName>clock enable</spirit:displayName>
        <spirit:description>clock enable</spirit:description>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_DDR3_CKE_WIDTH&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_ddr3_cke" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;DDR3&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_ddr3_cs_n</spirit:name>
        <spirit:displayName>chip select</spirit:displayName>
        <spirit:description>chip select</spirit:description>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_DDR3_CS_WIDTH&apos;)) * spirit:decode(id(&apos;MODELPARAM_VALUE.C6_DDR3_nCS_PER_RANK&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_ddr3_cs_n" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_DDR3_USE_CS_PORT&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_ddr3_dm</spirit:name>
        <spirit:displayName>data mask</spirit:displayName>
        <spirit:description>data mask</spirit:description>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_DDR3_DM_WIDTH&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_ddr3_dm" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_DDR3_USE_DM_PORT&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_ddr3_odt</spirit:name>
        <spirit:displayName>on die termination</spirit:displayName>
        <spirit:description>on die termination</spirit:description>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_DDR3_ODT_WIDTH&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_ddr3_odt" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;DDR3&quot; and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;DDR2&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_DDR3_USE_ODT_PORT&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_ddr3_parity</spirit:name>
        <spirit:displayName>parity bit</spirit:displayName>
        <spirit:description>parity bit</spirit:description>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_ddr3_parity" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_DDR3_REG_CTRL&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_ddr3_dbg_pi_counter_read_val</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">4</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_ddr3_dbg_pi_counter_read_val" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_DDR3_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_ddr3_dbg_byte_sel</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_DDR3_DQS_CNT_WIDTH&apos;)) + 1 )- 1 ">1</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_ddr3_dbg_byte_sel" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_DDR3_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_ddr3_dbg_sel_pi_incdec</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_ddr3_dbg_sel_pi_incdec" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_DDR3_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_ddr3_dbg_pi_f_inc</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_ddr3_dbg_pi_f_inc" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_DDR3_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_ddr3_dbg_pi_f_dec</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_ddr3_dbg_pi_f_dec" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_DDR3_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_ddr3_dbg_sel_po_incdec</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_ddr3_dbg_sel_po_incdec" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_DDR3_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_ddr3_dbg_po_f_inc</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_ddr3_dbg_po_f_inc" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_DDR3_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_ddr3_dbg_po_f_stg23_sel</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_ddr3_dbg_po_f_stg23_sel" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_DDR3_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_ddr3_dbg_po_f_dec</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_ddr3_dbg_po_f_dec" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_DDR3_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_ddr3_dbg_po_counter_read_val</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">7</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_ddr3_dbg_po_counter_read_val" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_DDR3_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_ddr3_ila_wrpath</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">254</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_ddr3_ila_wrpath" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_DDR3_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_ddr3_ila_rdpath</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">1022</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_ddr3_ila_rdpath" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_DDR3_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_ddr3_ila_basic</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">126</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_ddr3_ila_basic" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_DDR3_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_ddr3_vio_sync_out</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">34</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_ddr3_vio_sync_out" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_DDR3_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_ddr2_dq</spirit:name>
        <spirit:displayName>Data</spirit:displayName>
        <spirit:description>Data</spirit:description>
        <spirit:wire>
          <spirit:direction>inout</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_DDR2_DQ_WIDTH&apos;)) )- 1 ">7</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_ddr2_dq" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;DDR2&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_ddr2_dqs_p</spirit:name>
        <spirit:displayName>Data Strobe</spirit:displayName>
        <spirit:description>Data Strobe</spirit:description>
        <spirit:wire>
          <spirit:direction>inout</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_DDR2_DQS_WIDTH&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_ddr2_dqs_p" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;DDR2&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_ddr2_dqs_n</spirit:name>
        <spirit:displayName>Data Strobe</spirit:displayName>
        <spirit:description>Data Strobe</spirit:description>
        <spirit:wire>
          <spirit:direction>inout</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_DDR2_DQS_WIDTH&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_ddr2_dqs_n" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;DDR2&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_ddr2_addr</spirit:name>
        <spirit:displayName>Address</spirit:displayName>
        <spirit:description>Address</spirit:description>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_DDR2_ROW_WIDTH&apos;)) )- 1 ">13</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_ddr2_addr" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;DDR2&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_ddr2_ba</spirit:name>
        <spirit:displayName>Bank Address</spirit:displayName>
        <spirit:description>Bank Address</spirit:description>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_DDR2_BANK_WIDTH&apos;)) )- 1 ">2</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_ddr2_ba" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;DDR2&quot; and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;DDR2&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_ddr2_ras_n</spirit:name>
        <spirit:displayName>row address strobe</spirit:displayName>
        <spirit:description>row address strobe</spirit:description>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_ddr2_ras_n" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;DDR2&quot; and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;DDR2&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_ddr2_cas_n</spirit:name>
        <spirit:displayName>column address strobe</spirit:displayName>
        <spirit:description>column address strobe</spirit:description>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_ddr2_cas_n" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;DDR2&quot; and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;DDR2&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_ddr2_we_n</spirit:name>
        <spirit:displayName>write enable</spirit:displayName>
        <spirit:description>write enable</spirit:description>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_ddr2_we_n" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;DDR2&quot; and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;DDR2&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_ddr2_reset_n</spirit:name>
        <spirit:displayName>reset to memory device</spirit:displayName>
        <spirit:description>reset to memory device</spirit:description>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_ddr2_reset_n" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;DDR3&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_ddr2_ck_p</spirit:name>
        <spirit:displayName>clock to memory device</spirit:displayName>
        <spirit:description>clock to memory device</spirit:description>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_DDR2_CK_WIDTH&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_ddr2_ck_p" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;DDR2&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_ddr2_ck_n</spirit:name>
        <spirit:displayName>clock to memory device</spirit:displayName>
        <spirit:description>clock to memory device</spirit:description>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_DDR2_CK_WIDTH&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_ddr2_ck_n" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;DDR2&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_ddr2_cke</spirit:name>
        <spirit:displayName>clock enable</spirit:displayName>
        <spirit:description>clock enable</spirit:description>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_DDR2_CKE_WIDTH&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_ddr2_cke" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;DDR2&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_ddr2_cs_n</spirit:name>
        <spirit:displayName>chip select</spirit:displayName>
        <spirit:description>chip select</spirit:description>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_DDR2_CS_WIDTH&apos;)) * spirit:decode(id(&apos;MODELPARAM_VALUE.C6_DDR2_nCS_PER_RANK&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_ddr2_cs_n" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_DDR2_USE_CS_PORT&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_ddr2_dm</spirit:name>
        <spirit:displayName>data mask</spirit:displayName>
        <spirit:description>data mask</spirit:description>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_DDR2_DM_WIDTH&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_ddr2_dm" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_DDR2_USE_DM_PORT&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_ddr2_odt</spirit:name>
        <spirit:displayName>on die termination</spirit:displayName>
        <spirit:description>on die termination</spirit:description>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_DDR2_ODT_WIDTH&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_ddr2_odt" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;DDR2&quot; and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;DDR2&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_DDR2_USE_ODT_PORT&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_ddr2_parity</spirit:name>
        <spirit:displayName>parity bit</spirit:displayName>
        <spirit:description>parity bit</spirit:description>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_ddr2_parity" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_DDR2_REG_CTRL&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_ddr2_dbg_pi_counter_read_val</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">4</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_ddr2_dbg_pi_counter_read_val" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_DDR2_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_ddr2_dbg_byte_sel</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_DDR2_DQS_CNT_WIDTH&apos;)) + 1 )- 1 ">1</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_ddr2_dbg_byte_sel" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_DDR2_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_ddr2_dbg_sel_pi_incdec</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_ddr2_dbg_sel_pi_incdec" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_DDR2_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_ddr2_dbg_pi_f_inc</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_ddr2_dbg_pi_f_inc" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_DDR2_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_ddr2_dbg_pi_f_dec</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_ddr2_dbg_pi_f_dec" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_DDR2_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_ddr2_dbg_sel_po_incdec</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_ddr2_dbg_sel_po_incdec" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_DDR2_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_ddr2_dbg_po_f_inc</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_ddr2_dbg_po_f_inc" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_DDR2_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_ddr2_dbg_po_f_stg23_sel</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_ddr2_dbg_po_f_stg23_sel" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_DDR2_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_ddr2_dbg_po_f_dec</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_ddr2_dbg_po_f_dec" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_DDR2_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_ddr2_dbg_po_counter_read_val</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">7</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_ddr2_dbg_po_counter_read_val" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_DDR2_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_ddr2_ila_wrpath</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">254</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_ddr2_ila_wrpath" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_DDR2_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_ddr2_ila_rdpath</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">1022</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_ddr2_ila_rdpath" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_DDR2_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_ddr2_ila_basic</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">126</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_ddr2_ila_basic" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_DDR2_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_ddr2_vio_sync_out</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">34</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_ddr2_vio_sync_out" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_DDR2_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_lpddr2_dq</spirit:name>
        <spirit:displayName>Data</spirit:displayName>
        <spirit:description>Data</spirit:description>
        <spirit:wire>
          <spirit:direction>inout</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_LPDDR2_DQ_WIDTH&apos;)) )- 1 ">7</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_lpddr2_dq" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_lpddr2_dqs_p</spirit:name>
        <spirit:displayName>Data Strobe</spirit:displayName>
        <spirit:description>Data Strobe</spirit:description>
        <spirit:wire>
          <spirit:direction>inout</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_LPDDR2_DQS_WIDTH&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_lpddr2_dqs_p" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_lpddr2_dqs_n</spirit:name>
        <spirit:displayName>Data Strobe</spirit:displayName>
        <spirit:description>Data Strobe</spirit:description>
        <spirit:wire>
          <spirit:direction>inout</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_LPDDR2_DQS_WIDTH&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_lpddr2_dqs_n" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_lpddr2_ca</spirit:name>
        <spirit:displayName>Address</spirit:displayName>
        <spirit:description>Address</spirit:description>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">9</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_lpddr2_ca" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_lpddr2_ck_p</spirit:name>
        <spirit:displayName>clock to memory device</spirit:displayName>
        <spirit:description>clock to memory device</spirit:description>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_LPDDR2_CK_WIDTH&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_lpddr2_ck_p" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_lpddr2_ck_n</spirit:name>
        <spirit:displayName>clock to memory device</spirit:displayName>
        <spirit:description>clock to memory device</spirit:description>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_LPDDR2_CK_WIDTH&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_lpddr2_ck_n" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_lpddr2_cke</spirit:name>
        <spirit:displayName>clock enable</spirit:displayName>
        <spirit:description>clock enable</spirit:description>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_LPDDR2_CKE_WIDTH&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_lpddr2_cke" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_lpddr2_cs_n</spirit:name>
        <spirit:displayName>chip select</spirit:displayName>
        <spirit:description>chip select</spirit:description>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_LPDDR2_CS_WIDTH&apos;)) * spirit:decode(id(&apos;MODELPARAM_VALUE.C6_LPDDR2_nCS_PER_RANK&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_lpddr2_cs_n" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_LPDDR2_USE_CS_PORT&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_lpddr2_dm</spirit:name>
        <spirit:displayName>data mask</spirit:displayName>
        <spirit:description>data mask</spirit:description>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_LPDDR2_DM_WIDTH&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_lpddr2_dm" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_LPDDR2_USE_DM_PORT&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_lpddr2_parity</spirit:name>
        <spirit:displayName>parity bit</spirit:displayName>
        <spirit:description>parity bit</spirit:description>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_lpddr2_parity" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_LPDDR2_REG_CTRL&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_lpddr2_dbg_pi_counter_read_val</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">4</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_lpddr2_dbg_pi_counter_read_val" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_LPDDR2_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_lpddr2_dbg_byte_sel</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_LPDDR2_DQS_CNT_WIDTH&apos;)) + 1 )- 1 ">1</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_lpddr2_dbg_byte_sel" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_LPDDR2_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_lpddr2_dbg_sel_pi_incdec</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_lpddr2_dbg_sel_pi_incdec" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_LPDDR2_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_lpddr2_dbg_pi_f_inc</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_lpddr2_dbg_pi_f_inc" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_LPDDR2_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_lpddr2_dbg_pi_f_dec</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_lpddr2_dbg_pi_f_dec" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_LPDDR2_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_lpddr2_dbg_sel_po_incdec</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_lpddr2_dbg_sel_po_incdec" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_LPDDR2_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_lpddr2_dbg_po_f_inc</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_lpddr2_dbg_po_f_inc" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_LPDDR2_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_lpddr2_dbg_po_f_stg23_sel</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_lpddr2_dbg_po_f_stg23_sel" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_LPDDR2_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_lpddr2_dbg_po_f_dec</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_lpddr2_dbg_po_f_dec" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_LPDDR2_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_lpddr2_dbg_po_counter_read_val</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">7</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_lpddr2_dbg_po_counter_read_val" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_LPDDR2_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_lpddr2_ila_wrpath</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">254</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_lpddr2_ila_wrpath" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_LPDDR2_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_lpddr2_ila_rdpath</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">1022</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_lpddr2_ila_rdpath" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_LPDDR2_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_lpddr2_ila_basic</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">126</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_lpddr2_ila_basic" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_LPDDR2_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_lpddr2_vio_sync_out</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">34</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_lpddr2_vio_sync_out" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_LPDDR2_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_dbg_byte_sel</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_DQS_CNT_WIDTH&apos;)) + 1 )- 1 ">1</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_dbg_byte_sel" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;DDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_dbg_sel_pi_incdec</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_dbg_sel_pi_incdec" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;DDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_dbg_pi_f_inc</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_dbg_pi_f_inc" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;DDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_dbg_pi_f_dec</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_dbg_pi_f_dec" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;DDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_dbg_sel_po_incdec</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_dbg_sel_po_incdec" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;DDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_dbg_po_f_inc</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_dbg_po_f_inc" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;DDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_dbg_po_f_stg23_sel</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_dbg_po_f_stg23_sel" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;DDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_dbg_po_f_dec</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_dbg_po_f_dec" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;DDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_dbg_po_counter_read_val</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">7</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_dbg_po_counter_read_val" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;DDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_app_addr</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_DDRX_ADDR_WIDTH&apos;)) )- 1 ">7</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_app_addr" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;DDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_app_cmd</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">2</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_app_cmd" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;DDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_app_en</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_app_en" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;DDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_app_wdf_data</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_DDRX_nCK_PER_CLK&apos;)) * 2 * spirit:decode(id(&apos;MODELPARAM_VALUE.C6_DDRX_DATA_WIDTH&apos;)) )- 1 ">31</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_app_wdf_data" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;DDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_app_wdf_end</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_app_wdf_end" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;DDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_app_wdf_mask</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_DDRX_nCK_PER_CLK&apos;)) * 2 * spirit:decode(id(&apos;MODELPARAM_VALUE.C6_DDRX_DATA_WIDTH&apos;)) / 8 )- 1 ">3</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_app_wdf_mask" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;DDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_app_wdf_wren</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_app_wdf_wren" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;DDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_app_correct_en_i</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_app_correct_en_i" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;DDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_ECC&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_app_rd_data</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_DDRX_nCK_PER_CLK&apos;)) * 2 * spirit:decode(id(&apos;MODELPARAM_VALUE.C6_DDRX_DATA_WIDTH&apos;)) )- 1 ">31</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_app_rd_data" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;DDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_app_rd_data_end</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_app_rd_data_end" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;DDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_app_rd_data_valid</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_app_rd_data_valid" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;DDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_app_rdy</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_app_rdy" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;DDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_app_wdf_rdy</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_app_wdf_rdy" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;DDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_app_sr_req</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_app_sr_req" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;DDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_app_sr_active</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_app_sr_active" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;DDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_app_ref_req</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_app_ref_req" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;DDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_app_ref_ack</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_app_ref_ack" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;DDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_app_zq_req</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_app_zq_req" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;DDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_app_zq_ack</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_app_zq_ack" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;DDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_app_raw_not_ecc</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( 2 * spirit:decode(id(&apos;MODELPARAM_VALUE.C6_DDRX_nCK_PER_CLK&apos;)) )- 1 ">3</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_app_raw_not_ecc" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;DDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_ECC&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_app_ecc_multiple_err</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( 2 * spirit:decode(id(&apos;MODELPARAM_VALUE.C6_DDRX_nCK_PER_CLK&apos;)) )- 1 ">3</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_app_ecc_multiple_err" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;DDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_ECC&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_ddr3_app_addr</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_DDR3_ADDR_WIDTH&apos;)) )- 1 ">7</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_ddr3_app_addr" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_ddr3_app_cmd</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">2</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_ddr3_app_cmd" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_ddr3_app_en</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_ddr3_app_en" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_ddr3_app_wdf_data</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_DDR3_nCK_PER_CLK&apos;)) * 2 * spirit:decode(id(&apos;MODELPARAM_VALUE.C6_DDR3_DATA_WIDTH&apos;)) )- 1 ">31</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_ddr3_app_wdf_data" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_ddr3_app_wdf_end</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_ddr3_app_wdf_end" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_ddr3_app_wdf_mask</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_DDR3_nCK_PER_CLK&apos;)) * 2 * spirit:decode(id(&apos;MODELPARAM_VALUE.C6_DDR3_DATA_WIDTH&apos;)) / 8 )- 1 ">3</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_ddr3_app_wdf_mask" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_ddr3_app_wdf_wren</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_ddr3_app_wdf_wren" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_ddr3_app_correct_en_i</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_ddr3_app_correct_en_i" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_ECC&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_ddr3_app_rd_data</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_DDR3_nCK_PER_CLK&apos;)) * 2 * spirit:decode(id(&apos;MODELPARAM_VALUE.C6_DDR3_DATA_WIDTH&apos;)) )- 1 ">31</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_ddr3_app_rd_data" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_ddr3_app_rd_data_end</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_ddr3_app_rd_data_end" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_ddr3_app_rd_data_valid</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_ddr3_app_rd_data_valid" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_ddr3_app_rdy</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_ddr3_app_rdy" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_ddr3_app_wdf_rdy</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_ddr3_app_wdf_rdy" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_ddr3_app_sr_req</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_ddr3_app_sr_req" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_ddr3_app_sr_active</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_ddr3_app_sr_active" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_ddr3_app_ref_req</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_ddr3_app_ref_req" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_ddr3_app_ref_ack</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_ddr3_app_ref_ack" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_ddr3_app_zq_req</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_ddr3_app_zq_req" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_ddr3_app_zq_ack</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_ddr3_app_zq_ack" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_ddr3_app_raw_not_ecc</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( 2 * spirit:decode(id(&apos;MODELPARAM_VALUE.C6_DDR3_nCK_PER_CLK&apos;)) )- 1 ">3</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_ddr3_app_raw_not_ecc" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_ECC&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_ddr3_app_ecc_multiple_err</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( 2 * spirit:decode(id(&apos;MODELPARAM_VALUE.C6_DDR3_nCK_PER_CLK&apos;)) )- 1 ">3</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_ddr3_app_ecc_multiple_err" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_ECC&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_ddr2_app_addr</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_DDR2_ADDR_WIDTH&apos;)) )- 1 ">7</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_ddr2_app_addr" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_ddr2_app_cmd</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">2</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_ddr2_app_cmd" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_ddr2_app_en</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_ddr2_app_en" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_ddr2_app_wdf_data</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_DDR2_nCK_PER_CLK&apos;)) * 2 * spirit:decode(id(&apos;MODELPARAM_VALUE.C6_DDR2_DATA_WIDTH&apos;)) )- 1 ">31</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_ddr2_app_wdf_data" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_ddr2_app_wdf_end</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_ddr2_app_wdf_end" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_ddr2_app_wdf_mask</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_DDR2_nCK_PER_CLK&apos;)) * 2 * spirit:decode(id(&apos;MODELPARAM_VALUE.C6_DDR2_DATA_WIDTH&apos;)) / 8 )- 1 ">3</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_ddr2_app_wdf_mask" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_ddr2_app_wdf_wren</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_ddr2_app_wdf_wren" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_ddr2_app_correct_en_i</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_ddr2_app_correct_en_i" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_ECC&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_ddr2_app_rd_data</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_DDR2_nCK_PER_CLK&apos;)) * 2 * spirit:decode(id(&apos;MODELPARAM_VALUE.C6_DDR2_DATA_WIDTH&apos;)) )- 1 ">31</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_ddr2_app_rd_data" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_ddr2_app_rd_data_end</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_ddr2_app_rd_data_end" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_ddr2_app_rd_data_valid</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_ddr2_app_rd_data_valid" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_ddr2_app_rdy</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_ddr2_app_rdy" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_ddr2_app_wdf_rdy</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_ddr2_app_wdf_rdy" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_ddr2_app_sr_req</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_ddr2_app_sr_req" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_ddr2_app_sr_active</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_ddr2_app_sr_active" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_ddr2_app_ref_req</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_ddr2_app_ref_req" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_ddr2_app_ref_ack</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_ddr2_app_ref_ack" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_ddr2_app_zq_req</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_ddr2_app_zq_req" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_ddr2_app_zq_ack</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_ddr2_app_zq_ack" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_ddr2_app_raw_not_ecc</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( 2 * spirit:decode(id(&apos;MODELPARAM_VALUE.C6_DDR2_nCK_PER_CLK&apos;)) )- 1 ">3</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_ddr2_app_raw_not_ecc" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_ECC&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_ddr2_app_ecc_multiple_err</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( 2 * spirit:decode(id(&apos;MODELPARAM_VALUE.C6_DDR2_nCK_PER_CLK&apos;)) )- 1 ">3</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_ddr2_app_ecc_multiple_err" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_ECC&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_lpddr2_app_addr</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_LPDDR2_ADDR_WIDTH&apos;)) )- 1 ">7</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_lpddr2_app_addr" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_lpddr2_app_cmd</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">2</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_lpddr2_app_cmd" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_lpddr2_app_en</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_lpddr2_app_en" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_lpddr2_app_wdf_data</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_LPDDR2_nCK_PER_CLK&apos;)) * 2 * spirit:decode(id(&apos;MODELPARAM_VALUE.C6_LPDDR2_DATA_WIDTH&apos;)) )- 1 ">31</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_lpddr2_app_wdf_data" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_lpddr2_app_wdf_end</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_lpddr2_app_wdf_end" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_lpddr2_app_wdf_mask</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_LPDDR2_nCK_PER_CLK&apos;)) * 2 * spirit:decode(id(&apos;MODELPARAM_VALUE.C6_LPDDR2_DATA_WIDTH&apos;)) / 8 )- 1 ">3</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_lpddr2_app_wdf_mask" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_lpddr2_app_wdf_wren</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_lpddr2_app_wdf_wren" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_lpddr2_app_correct_en_i</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_lpddr2_app_correct_en_i" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_ECC&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_lpddr2_app_rd_data</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_LPDDR2_nCK_PER_CLK&apos;)) * 2 * spirit:decode(id(&apos;MODELPARAM_VALUE.C6_LPDDR2_DATA_WIDTH&apos;)) )- 1 ">31</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_lpddr2_app_rd_data" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_lpddr2_app_rd_data_end</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_lpddr2_app_rd_data_end" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_lpddr2_app_rd_data_valid</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_lpddr2_app_rd_data_valid" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_lpddr2_app_rdy</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_lpddr2_app_rdy" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_lpddr2_app_wdf_rdy</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_lpddr2_app_wdf_rdy" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_lpddr2_app_sr_req</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_lpddr2_app_sr_req" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_lpddr2_app_sr_active</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_lpddr2_app_sr_active" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_lpddr2_app_ref_req</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_lpddr2_app_ref_req" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_lpddr2_app_ref_ack</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_lpddr2_app_ref_ack" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_lpddr2_app_zq_req</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_lpddr2_app_zq_req" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_lpddr2_app_zq_ack</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_lpddr2_app_zq_ack" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_lpddr2_app_raw_not_ecc</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( 2 * spirit:decode(id(&apos;MODELPARAM_VALUE.C6_LPDDR2_nCK_PER_CLK&apos;)) )- 1 ">3</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_lpddr2_app_raw_not_ecc" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_ECC&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_lpddr2_app_ecc_multiple_err</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( 2 * spirit:decode(id(&apos;MODELPARAM_VALUE.C6_LPDDR2_nCK_PER_CLK&apos;)) )- 1 ">3</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_lpddr2_app_ecc_multiple_err" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_ECC&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_ui_clk_sync_rst</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_ui_clk_sync_rst" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;DDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;RLDII&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;RLDIII&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_ddr3_ui_clk_sync_rst</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_ddr3_ui_clk_sync_rst" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;DDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;RLDII&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;RLDIII&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_ddr2_ui_clk_sync_rst</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_ddr2_ui_clk_sync_rst" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;DDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;RLDII&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;RLDIII&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_lpddr2_ui_clk_sync_rst</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_lpddr2_ui_clk_sync_rst" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;DDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;RLDII&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;RLDIII&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_qdriip_ui_clk_sync_rst</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_qdriip_ui_clk_sync_rst" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;DDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;RLDII&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;RLDIII&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_rldii_ui_clk_sync_rst</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_rldii_ui_clk_sync_rst" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;RLDII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;DDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;RLDII&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;RLDIII&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_rldiii_ui_clk_sync_rst</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_rldiii_ui_clk_sync_rst" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;RLDIII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;DDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;RLDII&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;RLDIII&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_ui_clk</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_ui_clk" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;DDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;RLDII&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;RLDIII&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_ui_addn_clk_0</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_ui_addn_clk_0" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_UI_EXTRA_CLOCKS&apos;)) = &quot;TRUE&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MMCM_CLKOUT0_EN&apos;)) = &quot;TRUE&quot; ) and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;DDR2&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_ui_addn_clk_1</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_ui_addn_clk_1" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_UI_EXTRA_CLOCKS&apos;)) = &quot;TRUE&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MMCM_CLKOUT1_EN&apos;)) = &quot;TRUE&quot; ) and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;DDR2&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_ui_addn_clk_2</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_ui_addn_clk_2" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_UI_EXTRA_CLOCKS&apos;)) = &quot;TRUE&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MMCM_CLKOUT2_EN&apos;)) = &quot;TRUE&quot; ) and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;DDR2&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_ui_addn_clk_3</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_ui_addn_clk_3" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_UI_EXTRA_CLOCKS&apos;)) = &quot;TRUE&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MMCM_CLKOUT3_EN&apos;)) = &quot;TRUE&quot; ) and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;DDR2&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_ui_addn_clk_4</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_ui_addn_clk_4" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_UI_EXTRA_CLOCKS&apos;)) = &quot;TRUE&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MMCM_CLKOUT4_EN&apos;)) = &quot;TRUE&quot; ) and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;DDR2&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_s_axi_ctrl_awvalid</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_s_axi_ctrl_awvalid" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_USE_AXI&apos;)) = 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_ECC&apos;)) = &quot;ON&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_s_axi_ctrl_awready</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_s_axi_ctrl_awready" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_USE_AXI&apos;)) = 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_ECC&apos;)) = &quot;ON&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_s_axi_ctrl_awaddr</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_C_S_AXI_CTRL_ADDR_WIDTH&apos;)) )- 1 ">31</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_s_axi_ctrl_awaddr" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_USE_AXI&apos;)) = 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_ECC&apos;)) = &quot;ON&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_s_axi_ctrl_wvalid</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_s_axi_ctrl_wvalid" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_USE_AXI&apos;)) = 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_ECC&apos;)) = &quot;ON&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_s_axi_ctrl_wready</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_s_axi_ctrl_wready" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_USE_AXI&apos;)) = 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_ECC&apos;)) = &quot;ON&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_s_axi_ctrl_wdata</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_C_S_AXI_CTRL_DATA_WIDTH&apos;)) )- 1 ">31</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_s_axi_ctrl_wdata" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_USE_AXI&apos;)) = 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_ECC&apos;)) = &quot;ON&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_s_axi_ctrl_bvalid</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_s_axi_ctrl_bvalid" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_USE_AXI&apos;)) = 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_ECC&apos;)) = &quot;ON&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_s_axi_ctrl_bready</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_s_axi_ctrl_bready" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_USE_AXI&apos;)) = 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_ECC&apos;)) = &quot;ON&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_s_axi_ctrl_bresp</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">1</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_s_axi_ctrl_bresp" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_USE_AXI&apos;)) = 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_ECC&apos;)) = &quot;ON&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_s_axi_ctrl_arvalid</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_s_axi_ctrl_arvalid" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_USE_AXI&apos;)) = 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_ECC&apos;)) = &quot;ON&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_s_axi_ctrl_arready</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_s_axi_ctrl_arready" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_USE_AXI&apos;)) = 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_ECC&apos;)) = &quot;ON&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_s_axi_ctrl_araddr</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_C_S_AXI_CTRL_ADDR_WIDTH&apos;)) )- 1 ">31</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_s_axi_ctrl_araddr" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_USE_AXI&apos;)) = 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_ECC&apos;)) = &quot;ON&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_s_axi_ctrl_rvalid</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_s_axi_ctrl_rvalid" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_USE_AXI&apos;)) = 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_ECC&apos;)) = &quot;ON&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_s_axi_ctrl_rready</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_s_axi_ctrl_rready" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_USE_AXI&apos;)) = 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_ECC&apos;)) = &quot;ON&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_s_axi_ctrl_rdata</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_C_S_AXI_CTRL_DATA_WIDTH&apos;)) )- 1 ">31</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_s_axi_ctrl_rdata" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_USE_AXI&apos;)) = 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_ECC&apos;)) = &quot;ON&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_s_axi_ctrl_rresp</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">1</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_s_axi_ctrl_rresp" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_USE_AXI&apos;)) = 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_ECC&apos;)) = &quot;ON&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_s_axi_awid</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_C_S_AXI_ID_WIDTH&apos;)) )- 1 ">3</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
          <spirit:driver>
            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
          </spirit:driver>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_s_axi_awid" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_s_axi_awaddr</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_C_S_AXI_ADDR_WIDTH&apos;)) )- 1 ">31</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_s_axi_awaddr" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_s_axi_awlen</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">7</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_s_axi_awlen" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_s_axi_awsize</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">2</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_s_axi_awsize" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_s_axi_awburst</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">1</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_s_axi_awburst" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_s_axi_awlock</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
          <spirit:driver>
            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
          </spirit:driver>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_s_axi_awlock" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_s_axi_awcache</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">3</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
          <spirit:driver>
            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
          </spirit:driver>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_s_axi_awcache" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_s_axi_awprot</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">2</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
          <spirit:driver>
            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
          </spirit:driver>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_s_axi_awprot" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_s_axi_awqos</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">3</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
          <spirit:driver>
            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
          </spirit:driver>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_s_axi_awqos" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_s_axi_awvalid</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_s_axi_awvalid" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_s_axi_awready</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_s_axi_awready" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_s_axi_wdata</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_C_S_AXI_DATA_WIDTH&apos;)) )- 1 ">31</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_s_axi_wdata" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_s_axi_wstrb</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_C_S_AXI_DATA_WIDTH&apos;)) / 8 )- 1 ">3</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_s_axi_wstrb" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_s_axi_wlast</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_s_axi_wlast" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_s_axi_wvalid</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_s_axi_wvalid" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_s_axi_wready</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_s_axi_wready" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_s_axi_bready</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_s_axi_bready" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_s_axi_bid</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_C_S_AXI_ID_WIDTH&apos;)) )- 1 ">3</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_s_axi_bid" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_s_axi_bresp</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">1</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_s_axi_bresp" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_s_axi_bvalid</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_s_axi_bvalid" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_s_axi_arid</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_C_S_AXI_ID_WIDTH&apos;)) )- 1 ">3</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
          <spirit:driver>
            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
          </spirit:driver>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_s_axi_arid" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_s_axi_araddr</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_C_S_AXI_ADDR_WIDTH&apos;)) )- 1 ">31</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_s_axi_araddr" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_s_axi_arlen</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">7</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_s_axi_arlen" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_s_axi_arsize</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">2</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_s_axi_arsize" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_s_axi_arburst</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">1</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_s_axi_arburst" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_s_axi_arlock</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
          <spirit:driver>
            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
          </spirit:driver>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_s_axi_arlock" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_s_axi_arcache</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">3</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
          <spirit:driver>
            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
          </spirit:driver>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_s_axi_arcache" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_s_axi_arprot</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">2</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
          <spirit:driver>
            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
          </spirit:driver>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_s_axi_arprot" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_s_axi_arqos</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">3</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
          <spirit:driver>
            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
          </spirit:driver>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_s_axi_arqos" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_s_axi_arvalid</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_s_axi_arvalid" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_s_axi_arready</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_s_axi_arready" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_s_axi_rready</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_s_axi_rready" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_s_axi_rid</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_C_S_AXI_ID_WIDTH&apos;)) )- 1 ">3</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_s_axi_rid" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_s_axi_rdata</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_C_S_AXI_DATA_WIDTH&apos;)) )- 1 ">31</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_s_axi_rdata" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_s_axi_rresp</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">1</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_s_axi_rresp" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_s_axi_rlast</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_s_axi_rlast" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_s_axi_rvalid</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_s_axi_rvalid" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_interrupt</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_interrupt" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_USE_AXI&apos;)) = 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_ECC&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_mmcm_locked</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_mmcm_locked" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_qdriip_cq_p</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_QDRIIP_NUM_DEVICES&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_qdriip_cq_p" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_qdriip_cq_n</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_QDRIIP_NUM_DEVICES&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_qdriip_cq_n" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_qdriip_qvld</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_QDRIIP_NUM_DEVICES&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_qdriip_qvld" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_qdriip_q</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_QDRIIP_DATA_WIDTH&apos;)) )- 1 ">17</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_qdriip_q" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_qdriip_k_p</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_QDRIIP_NUM_DEVICES&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_qdriip_k_p" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_qdriip_k_n</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_QDRIIP_NUM_DEVICES&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_qdriip_k_n" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_qdriip_d</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_QDRIIP_DATA_WIDTH&apos;)) )- 1 ">17</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_qdriip_d" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_qdriip_sa</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_QDRIIP_ADDR_WIDTH&apos;)) )- 1 ">28</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_qdriip_sa" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_qdriip_w_n</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_qdriip_w_n" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_qdriip_r_n</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_qdriip_r_n" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_qdriip_bw_n</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_QDRIIP_BW_WIDTH&apos;)) )- 1 ">7</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_qdriip_bw_n" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_qdriip_dll_off_n</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_qdriip_dll_off_n" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_qdriip_dbg_pi_counter_read_val</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">4</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_qdriip_dbg_pi_counter_read_val" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_QDRIIP_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_qdriip_dbg_win_inc</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_qdriip_dbg_win_inc" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_QDRIIP_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_qdriip_dbg_win_dec</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_qdriip_dbg_win_dec" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_QDRIIP_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_qdriip_dbg_win_active</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_qdriip_dbg_win_active" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_QDRIIP_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_qdriip_dbg_win_current_byte</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">2</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_qdriip_dbg_win_current_byte" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_QDRIIP_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_qdriip_ila0_data</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">254</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_qdriip_ila0_data" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_QDRIIP_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_qdriip_ila0_trig</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">6</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_qdriip_ila0_trig" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_QDRIIP_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_qdriip_ila1_data</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">269</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_qdriip_ila1_data" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_QDRIIP_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_qdriip_ila1_trig</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">14</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_qdriip_ila1_trig" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_QDRIIP_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_qdriip_vio2_async_in</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">198</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_qdriip_vio2_async_in" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_QDRIIP_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_qdriip_vio2_sync_out</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">34</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_qdriip_vio2_sync_out" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_QDRIIP_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_app_wr_cmd0</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_app_wr_cmd0" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_app_wr_addr0</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_QDRIIP_ADDR_WIDTH&apos;)) )- 1 ">28</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_app_wr_addr0" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_app_wr_data0</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_QDRIIP_BURST_LEN&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_app_wr_data0" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_app_wr_bw_n0</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_QDRIIP_BURST_LEN&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_app_wr_bw_n0" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_app_rd_cmd0</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_app_rd_cmd0" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_app_rd_addr0</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_QDRIIP_ADDR_WIDTH&apos;)) )- 1 ">28</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_app_rd_addr0" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_app_rd_valid0</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_app_rd_valid0" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_app_rd_data0</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_QDRIIP_BURST_LEN&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_app_rd_data0" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_app_wr_cmd1</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_app_wr_cmd1" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_app_wr_addr1</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_QDRIIP_ADDR_WIDTH&apos;)) )- 1 ">28</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_app_wr_addr1" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_app_wr_data1</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" (( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_QDRIIP_DATA_WIDTH&apos;)) * 2 ))- 1 ">35</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_app_wr_data1" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_app_wr_bw_n1</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" (( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_QDRIIP_BW_WIDTH&apos;)) * 2 ))- 1 ">15</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_app_wr_bw_n1" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_app_rd_cmd1</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_app_rd_cmd1" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_app_rd_addr1</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_QDRIIP_ADDR_WIDTH&apos;)) )- 1 ">28</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_app_rd_addr1" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_app_rd_valid1</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_app_rd_valid1" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_app_rd_data1</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" (( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_QDRIIP_DATA_WIDTH&apos;)) * 2 ))- 1 ">35</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_app_rd_data1" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_clk</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_clk" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_rst_clk</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_rst_clk" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_qdriip_app_wr_cmd0</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_qdriip_app_wr_cmd0" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_qdriip_app_wr_addr0</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_QDRIIP_ADDR_WIDTH&apos;)) )- 1 ">28</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_qdriip_app_wr_addr0" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_qdriip_app_wr_data0</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_QDRIIP_BURST_LEN&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_qdriip_app_wr_data0" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_qdriip_app_wr_bw_n0</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_QDRIIP_BURST_LEN&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_qdriip_app_wr_bw_n0" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_qdriip_app_rd_cmd0</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_qdriip_app_rd_cmd0" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_qdriip_app_rd_addr0</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_QDRIIP_ADDR_WIDTH&apos;)) )- 1 ">28</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_qdriip_app_rd_addr0" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_qdriip_app_rd_valid0</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_qdriip_app_rd_valid0" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_qdriip_app_rd_data0</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_QDRIIP_BURST_LEN&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_qdriip_app_rd_data0" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_qdriip_app_wr_cmd1</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_qdriip_app_wr_cmd1" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_qdriip_app_wr_addr1</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_QDRIIP_ADDR_WIDTH&apos;)) )- 1 ">28</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_qdriip_app_wr_addr1" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_qdriip_app_wr_data1</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" (( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_QDRIIP_DATA_WIDTH&apos;)) * 2 ))- 1 ">35</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_qdriip_app_wr_data1" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_qdriip_app_wr_bw_n1</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" (( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_QDRIIP_BW_WIDTH&apos;)) * 2 ))- 1 ">15</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_qdriip_app_wr_bw_n1" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_qdriip_app_rd_cmd1</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_qdriip_app_rd_cmd1" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_qdriip_app_rd_addr1</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_QDRIIP_ADDR_WIDTH&apos;)) )- 1 ">28</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_qdriip_app_rd_addr1" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_qdriip_app_rd_valid1</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_qdriip_app_rd_valid1" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_qdriip_app_rd_data1</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" (( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_QDRIIP_DATA_WIDTH&apos;)) * 2 ))- 1 ">35</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_qdriip_app_rd_data1" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_qdriip_clk</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_qdriip_clk" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_qdriip_rst_clk</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_qdriip_rst_clk" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_rldii_qk_p</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_RLDII_QK_WIDTH&apos;)) )- 1 ">7</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_rldii_qk_p" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;RLDII&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_rldii_qk_n</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_RLDII_QK_WIDTH&apos;)) )- 1 ">7</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_rldii_qk_n" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;RLDII&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_rldii_dq</spirit:name>
        <spirit:wire>
          <spirit:direction>inout</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_RLDII_DATA_WIDTH&apos;)) )- 1 ">17</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_rldii_dq" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;RLDII&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_rldii_dm</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_RLDII_DM_WIDTH&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_rldii_dm" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;RLDII&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_rldii_dk_p</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_RLDII_DK_WIDTH&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_rldii_dk_p" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;RLDII&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_rldii_dk_n</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_RLDII_DK_WIDTH&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_rldii_dk_n" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;RLDII&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_rldii_ck_p</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_RLDII_NUM_DEVICES&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_rldii_ck_p" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;RLDII&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_rldii_ck_n</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_RLDII_NUM_DEVICES&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_rldii_ck_n" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;RLDII&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_rldii_cs_n</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_RLDII_NUM_DEVICES&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_rldii_cs_n" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;RLDII&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_rldii_a</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_RLDII_RLD_ADDR_WIDTH&apos;)) )- 1 ">28</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_rldii_a" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;RLDII&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_rldii_ba</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_RLDII_BANK_WIDTH&apos;)) )- 1 ">1</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_rldii_ba" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;RLDII&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_rldii_qvld</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_RLDII_QVLD_WIDTH&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_rldii_qvld" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;RLDII&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_rldii_we_n</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_rldii_we_n" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;RLDII&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_rldii_ref_n</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_rldii_ref_n" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;RLDII&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_rldii_reset_n</spirit:name>
        <spirit:displayName>reset to memory device</spirit:displayName>
        <spirit:description>reset to memory device</spirit:description>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_rldii_reset_n" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;RLDII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;RLDIII&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_rldii_dbg_pi_tap_cnt</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">4</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_rldii_dbg_pi_tap_cnt" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;RLDII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_RLDII_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_rldii_dbg_win_inc</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_rldii_dbg_win_inc" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;RLDII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_RLDII_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_rldii_dbg_win_dec</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_rldii_dbg_win_dec" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;RLDII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_RLDII_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_rldii_dbg_win_active</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_rldii_dbg_win_active" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;RLDII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_RLDII_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_rldii_dbg_win_current_byte</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">2</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_rldii_dbg_win_current_byte" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;RLDII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_RLDII_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_rldii_ila0_data</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">638</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_rldii_ila0_data" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;RLDII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_RLDII_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_rldii_ila0_trig</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">30</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_rldii_ila0_trig" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;RLDII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_RLDII_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_rldii_vio1_async_in</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">254</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_rldii_vio1_async_in" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;RLDII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_RLDII_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_rldii_vio1_async_out</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">62</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_rldii_vio1_async_out" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;RLDII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_RLDII_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_rldii_vio1_sync_out</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">62</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_rldii_vio1_sync_out" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;RLDII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_RLDII_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_rldiii_qk_p</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_RLDIII_QK_WIDTH&apos;)) )- 1 ">7</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_rldiii_qk_p" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;RLDIII&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_rldiii_qk_n</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_RLDIII_QK_WIDTH&apos;)) )- 1 ">7</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_rldiii_qk_n" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;RLDIII&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_rldiii_dq</spirit:name>
        <spirit:wire>
          <spirit:direction>inout</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_RLDIII_DATA_WIDTH&apos;)) )- 1 ">17</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_rldiii_dq" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;RLDIII&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_rldiii_dm</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_RLDIII_DM_WIDTH&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_rldiii_dm" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;RLDIII&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_rldiii_dk_p</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_RLDIII_DK_WIDTH&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_rldiii_dk_p" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;RLDIII&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_rldiii_dk_n</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_RLDIII_DK_WIDTH&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_rldiii_dk_n" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;RLDIII&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_rldiii_ck_p</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_RLDIII_NUM_DEVICES&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_rldiii_ck_p" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;RLDIII&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_rldiii_ck_n</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_RLDIII_NUM_DEVICES&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_rldiii_ck_n" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;RLDIII&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_rldiii_cs_n</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_RLDIII_NUM_DEVICES&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_rldiii_cs_n" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;RLDIII&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_rldiii_a</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_RLDIII_RLD_ADDR_WIDTH&apos;)) )- 1 ">28</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_rldiii_a" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;RLDIII&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_rldiii_ba</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_RLDIII_BANK_WIDTH&apos;)) )- 1 ">1</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_rldiii_ba" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;RLDIII&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_rldiii_qvld</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_RLDIII_QVLD_WIDTH&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_rldiii_qvld" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;RLDIII&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_rldiii_we_n</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_rldiii_we_n" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;RLDIII&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_rldiii_ref_n</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_rldiii_ref_n" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;RLDIII&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_rldiii_reset_n</spirit:name>
        <spirit:displayName>reset to memory device</spirit:displayName>
        <spirit:description>reset to memory device</spirit:description>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_rldiii_reset_n" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;RLDIII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;RLDIII&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_dbg_pi_tap_cnt</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">4</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_dbg_pi_tap_cnt" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;RLDIII&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;RLDII&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_rldiii_dbg_pi_tap_cnt</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">4</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_rldiii_dbg_pi_tap_cnt" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;RLDIII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_RLDIII_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_rldiii_dbg_win_inc</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_rldiii_dbg_win_inc" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;RLDIII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_RLDIII_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_rldiii_dbg_win_dec</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_rldiii_dbg_win_dec" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;RLDIII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_RLDIII_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_rldiii_dbg_win_active</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_rldiii_dbg_win_active" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;RLDIII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_RLDIII_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_rldiii_dbg_win_current_byte</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">2</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_rldiii_dbg_win_current_byte" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;RLDIII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_RLDIII_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_rldiii_ila0_data</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">638</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_rldiii_ila0_data" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;RLDIII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_RLDIII_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_rldiii_ila0_trig</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">30</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_rldiii_ila0_trig" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;RLDIII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_RLDIII_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_rldiii_vio1_async_in</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">254</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_rldiii_vio1_async_in" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;RLDIII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_RLDIII_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_rldiii_vio1_async_out</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">62</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_rldiii_vio1_async_out" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;RLDIII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_RLDIII_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_rldiii_vio1_sync_out</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">62</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_rldiii_vio1_sync_out" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;RLDIII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_RLDIII_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_dbg_win_inc</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_dbg_win_inc" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;RLDIII&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;RLDII&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_dbg_win_dec</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_dbg_win_dec" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;RLDIII&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;RLDII&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_dbg_win_active</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_dbg_win_active" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;RLDIII&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;RLDII&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_dbg_win_current_byte</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">2</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_dbg_win_current_byte" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;RLDIII&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;RLDII&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_dbg_pi_counter_read_val</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">4</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_dbg_pi_counter_read_val" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;DDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_user_cmd_en</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_user_cmd_en" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;RLDII&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;RLDIII&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_user_cmd</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_RLDX_CMD_PER_CLK&apos;)) * 2 )- 1 ">1</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_user_cmd" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;RLDII&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;RLDIII&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_user_addr</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_RLDX_ADDR_WIDTH&apos;)) * spirit:decode(id(&apos;MODELPARAM_VALUE.C6_RLDX_CMD_PER_CLK&apos;)) )- 1 ">28</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_user_addr" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;RLDII&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;RLDIII&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_user_ba</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_RLDX_BANK_WIDTH&apos;)) * spirit:decode(id(&apos;MODELPARAM_VALUE.C6_RLDX_CMD_PER_CLK&apos;)) )- 1 ">1</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_user_ba" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;RLDII&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;RLDIII&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_user_wr_en</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_user_wr_en" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;RLDII&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;RLDIII&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_user_wr_data</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_RLDX_DATA_WIDTH&apos;)) * 2 * spirit:decode(id(&apos;MODELPARAM_VALUE.C6_RLDX_nCK_PER_CLK&apos;)) )- 1 ">35</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_user_wr_data" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;RLDII&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;RLDIII&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_user_wr_dm</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_RLDX_DM_WIDTH&apos;)) * 2 * spirit:decode(id(&apos;MODELPARAM_VALUE.C6_RLDX_nCK_PER_CLK&apos;)) )- 1 ">1</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_user_wr_dm" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;RLDII&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;RLDIII&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_user_afifo_empty</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_user_afifo_empty" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;RLDII&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;RLDIII&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_user_afifo_full</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_user_afifo_full" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;RLDII&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;RLDIII&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_user_afifo_aempty</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_user_afifo_aempty" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;RLDII&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;RLDIII&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_user_afifo_afull</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_user_afifo_afull" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;RLDII&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;RLDIII&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_user_wdfifo_empty</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_user_wdfifo_empty" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;RLDII&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;RLDIII&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_user_wdfifo_full</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_user_wdfifo_full" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;RLDII&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;RLDIII&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_user_wdfifo_aempty</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_user_wdfifo_aempty" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;RLDII&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;RLDIII&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_user_wdfifo_afull</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_user_wdfifo_afull" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;RLDII&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;RLDIII&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_user_rd_valid</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_RLDX_nCK_PER_CLK&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_user_rd_valid" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;RLDII&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;RLDIII&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_mem_ck_lock_complete</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_mem_ck_lock_complete" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;RLDII&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;RLDIII&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_user_rd_data</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_RLDX_DATA_WIDTH&apos;)) * 2 * spirit:decode(id(&apos;MODELPARAM_VALUE.C6_RLDX_nCK_PER_CLK&apos;)) )- 1 ">35</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_user_rd_data" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;RLDII&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;RLDIII&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_rldii_user_cmd_en</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_rldii_user_cmd_en" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;RLDII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_rldii_user_cmd</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_RLDII_CMD_PER_CLK&apos;)) * 2 )- 1 ">1</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_rldii_user_cmd" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;RLDII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_rldii_user_addr</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_RLDII_ADDR_WIDTH&apos;)) * spirit:decode(id(&apos;MODELPARAM_VALUE.C6_RLDII_CMD_PER_CLK&apos;)) )- 1 ">28</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_rldii_user_addr" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;RLDII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_rldii_user_ba</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_RLDII_BANK_WIDTH&apos;)) * spirit:decode(id(&apos;MODELPARAM_VALUE.C6_RLDII_CMD_PER_CLK&apos;)) )- 1 ">1</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_rldii_user_ba" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;RLDII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_rldii_user_wr_en</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_rldii_user_wr_en" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;RLDII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_rldii_user_wr_data</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_RLDII_DATA_WIDTH&apos;)) * 2 * spirit:decode(id(&apos;MODELPARAM_VALUE.C6_RLDII_nCK_PER_CLK&apos;)) )- 1 ">35</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_rldii_user_wr_data" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;RLDII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_rldii_user_wr_dm</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_RLDII_DM_WIDTH&apos;)) * 2 * spirit:decode(id(&apos;MODELPARAM_VALUE.C6_RLDII_nCK_PER_CLK&apos;)) )- 1 ">1</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_rldii_user_wr_dm" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;RLDII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_rldii_user_afifo_empty</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_rldii_user_afifo_empty" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;RLDII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_rldii_user_afifo_full</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_rldii_user_afifo_full" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;RLDII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_rldii_user_afifo_aempty</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_rldii_user_afifo_aempty" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;RLDII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_rldii_user_afifo_afull</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_rldii_user_afifo_afull" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;RLDII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_rldii_user_wdfifo_empty</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_rldii_user_wdfifo_empty" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;RLDII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_rldii_user_wdfifo_full</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_rldii_user_wdfifo_full" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;RLDII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_rldii_user_wdfifo_aempty</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_rldii_user_wdfifo_aempty" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;RLDII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_rldii_user_wdfifo_afull</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_rldii_user_wdfifo_afull" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;RLDII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_rldii_user_rd_valid</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_RLDII_nCK_PER_CLK&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_rldii_user_rd_valid" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;RLDII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_rldii_mem_ck_lock_complete</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_rldii_mem_ck_lock_complete" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;RLDII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_rldii_user_rd_data</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_RLDII_DATA_WIDTH&apos;)) * 2 * spirit:decode(id(&apos;MODELPARAM_VALUE.C6_RLDII_nCK_PER_CLK&apos;)) )- 1 ">35</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_rldii_user_rd_data" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;RLDII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_rldiii_user_cmd_en</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_rldiii_user_cmd_en" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;RLDIII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_rldiii_user_cmd</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_RLDIII_CMD_PER_CLK&apos;)) * 2 )- 1 ">1</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_rldiii_user_cmd" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;RLDIII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_rldiii_user_addr</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_RLDIII_ADDR_WIDTH&apos;)) * spirit:decode(id(&apos;MODELPARAM_VALUE.C6_RLDIII_CMD_PER_CLK&apos;)) )- 1 ">28</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_rldiii_user_addr" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;RLDIII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_rldiii_user_ba</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_RLDIII_BANK_WIDTH&apos;)) * spirit:decode(id(&apos;MODELPARAM_VALUE.C6_RLDIII_CMD_PER_CLK&apos;)) )- 1 ">1</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_rldiii_user_ba" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;RLDIII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_rldiii_user_wr_en</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_rldiii_user_wr_en" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;RLDIII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_rldiii_user_wr_data</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_RLDIII_DATA_WIDTH&apos;)) * 2 * spirit:decode(id(&apos;MODELPARAM_VALUE.C6_RLDIII_nCK_PER_CLK&apos;)) )- 1 ">35</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_rldiii_user_wr_data" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;RLDIII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_rldiii_user_wr_dm</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_RLDIII_DM_WIDTH&apos;)) * 2 * spirit:decode(id(&apos;MODELPARAM_VALUE.C6_RLDIII_nCK_PER_CLK&apos;)) )- 1 ">1</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_rldiii_user_wr_dm" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;RLDIII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_rldiii_user_afifo_empty</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_rldiii_user_afifo_empty" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;RLDIII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_rldiii_user_afifo_full</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_rldiii_user_afifo_full" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;RLDIII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_rldiii_user_afifo_aempty</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_rldiii_user_afifo_aempty" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;RLDIII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_rldiii_user_afifo_afull</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_rldiii_user_afifo_afull" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;RLDIII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_rldiii_user_wdfifo_empty</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_rldiii_user_wdfifo_empty" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;RLDIII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_rldiii_user_wdfifo_full</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_rldiii_user_wdfifo_full" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;RLDIII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_rldiii_user_wdfifo_aempty</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_rldiii_user_wdfifo_aempty" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;RLDIII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_rldiii_user_wdfifo_afull</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_rldiii_user_wdfifo_afull" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;RLDIII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_rldiii_user_rd_valid</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_RLDIII_nCK_PER_CLK&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_rldiii_user_rd_valid" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;RLDIII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_rldiii_mem_ck_lock_complete</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_rldiii_mem_ck_lock_complete" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;RLDIII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_rldiii_user_rd_data</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_RLDIII_DATA_WIDTH&apos;)) * 2 * spirit:decode(id(&apos;MODELPARAM_VALUE.C6_RLDIII_nCK_PER_CLK&apos;)) )- 1 ">35</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_rldiii_user_rd_data" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;RLDIII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_sys_clk_p</spirit:name>
        <spirit:displayName>Clock P</spirit:displayName>
        <spirit:description>Clock P</spirit:description>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_sys_clk_p" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_SYSCLK_TYPE&apos;)) = &quot;DIFF&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_IS_CLK_SHARED&apos;)) = &quot;FALSE&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_sys_clk_n</spirit:name>
        <spirit:displayName>Clock P</spirit:displayName>
        <spirit:description>Clock P</spirit:description>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_sys_clk_n" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_SYSCLK_TYPE&apos;)) = &quot;DIFF&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_IS_CLK_SHARED&apos;)) = &quot;FALSE&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_sys_clk_i</spirit:name>
        <spirit:displayName>Clock P</spirit:displayName>
        <spirit:description>Clock P</spirit:description>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_sys_clk_i" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_SYSCLK_TYPE&apos;)) != &quot;DIFF&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C6_IS_CLK_SHARED&apos;)) = &quot;FALSE&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_init_calib_complete</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_init_calib_complete" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c6_aresetn</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c6_aresetn" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 6 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C6_MEM_TYPE&apos;)) = &quot;DDR2&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_ddr3_dq</spirit:name>
        <spirit:displayName>Data</spirit:displayName>
        <spirit:description>Data</spirit:description>
        <spirit:wire>
          <spirit:direction>inout</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_DDR3_DQ_WIDTH&apos;)) )- 1 ">7</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_ddr3_dq" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;DDR3&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_ddr3_dqs_p</spirit:name>
        <spirit:displayName>Data Strobe</spirit:displayName>
        <spirit:description>Data Strobe</spirit:description>
        <spirit:wire>
          <spirit:direction>inout</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_DDR3_DQS_WIDTH&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_ddr3_dqs_p" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;DDR3&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_ddr3_dqs_n</spirit:name>
        <spirit:displayName>Data Strobe</spirit:displayName>
        <spirit:description>Data Strobe</spirit:description>
        <spirit:wire>
          <spirit:direction>inout</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_DDR3_DQS_WIDTH&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_ddr3_dqs_n" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;DDR3&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_ddr3_addr</spirit:name>
        <spirit:displayName>Address</spirit:displayName>
        <spirit:description>Address</spirit:description>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_DDR3_ROW_WIDTH&apos;)) )- 1 ">13</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_ddr3_addr" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;DDR3&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_ddr3_ba</spirit:name>
        <spirit:displayName>Bank Address</spirit:displayName>
        <spirit:description>Bank Address</spirit:description>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_DDR3_BANK_WIDTH&apos;)) )- 1 ">2</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_ddr3_ba" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;DDR3&quot; and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;DDR2&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_ddr3_ras_n</spirit:name>
        <spirit:displayName>row address strobe</spirit:displayName>
        <spirit:description>row address strobe</spirit:description>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_ddr3_ras_n" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;DDR3&quot; and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;DDR2&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_ddr3_cas_n</spirit:name>
        <spirit:displayName>column address strobe</spirit:displayName>
        <spirit:description>column address strobe</spirit:description>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_ddr3_cas_n" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;DDR3&quot; and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;DDR2&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_ddr3_we_n</spirit:name>
        <spirit:displayName>write enable</spirit:displayName>
        <spirit:description>write enable</spirit:description>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_ddr3_we_n" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;DDR3&quot; and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;DDR2&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_ddr3_reset_n</spirit:name>
        <spirit:displayName>reset to memory device</spirit:displayName>
        <spirit:description>reset to memory device</spirit:description>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_ddr3_reset_n" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;DDR3&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_ddr3_ck_p</spirit:name>
        <spirit:displayName>clock to memory device</spirit:displayName>
        <spirit:description>clock to memory device</spirit:description>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_DDR3_CK_WIDTH&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_ddr3_ck_p" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;DDR3&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_ddr3_ck_n</spirit:name>
        <spirit:displayName>clock to memory device</spirit:displayName>
        <spirit:description>clock to memory device</spirit:description>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_DDR3_CK_WIDTH&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_ddr3_ck_n" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;DDR3&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_ddr3_cke</spirit:name>
        <spirit:displayName>clock enable</spirit:displayName>
        <spirit:description>clock enable</spirit:description>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_DDR3_CKE_WIDTH&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_ddr3_cke" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;DDR3&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_ddr3_cs_n</spirit:name>
        <spirit:displayName>chip select</spirit:displayName>
        <spirit:description>chip select</spirit:description>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_DDR3_CS_WIDTH&apos;)) * spirit:decode(id(&apos;MODELPARAM_VALUE.C7_DDR3_nCS_PER_RANK&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_ddr3_cs_n" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_DDR3_USE_CS_PORT&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_ddr3_dm</spirit:name>
        <spirit:displayName>data mask</spirit:displayName>
        <spirit:description>data mask</spirit:description>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_DDR3_DM_WIDTH&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_ddr3_dm" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_DDR3_USE_DM_PORT&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_ddr3_odt</spirit:name>
        <spirit:displayName>on die termination</spirit:displayName>
        <spirit:description>on die termination</spirit:description>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_DDR3_ODT_WIDTH&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_ddr3_odt" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;DDR3&quot; and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;DDR2&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_DDR3_USE_ODT_PORT&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_ddr3_parity</spirit:name>
        <spirit:displayName>parity bit</spirit:displayName>
        <spirit:description>parity bit</spirit:description>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_ddr3_parity" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_DDR3_REG_CTRL&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_ddr3_dbg_pi_counter_read_val</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">4</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_ddr3_dbg_pi_counter_read_val" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_DDR3_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_ddr3_dbg_byte_sel</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_DDR3_DQS_CNT_WIDTH&apos;)) + 1 )- 1 ">1</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_ddr3_dbg_byte_sel" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_DDR3_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_ddr3_dbg_sel_pi_incdec</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_ddr3_dbg_sel_pi_incdec" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_DDR3_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_ddr3_dbg_pi_f_inc</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_ddr3_dbg_pi_f_inc" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_DDR3_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_ddr3_dbg_pi_f_dec</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_ddr3_dbg_pi_f_dec" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_DDR3_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_ddr3_dbg_sel_po_incdec</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_ddr3_dbg_sel_po_incdec" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_DDR3_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_ddr3_dbg_po_f_inc</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_ddr3_dbg_po_f_inc" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_DDR3_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_ddr3_dbg_po_f_stg23_sel</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_ddr3_dbg_po_f_stg23_sel" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_DDR3_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_ddr3_dbg_po_f_dec</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_ddr3_dbg_po_f_dec" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_DDR3_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_ddr3_dbg_po_counter_read_val</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">7</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_ddr3_dbg_po_counter_read_val" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_DDR3_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_ddr3_ila_wrpath</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">254</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_ddr3_ila_wrpath" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_DDR3_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_ddr3_ila_rdpath</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">1022</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_ddr3_ila_rdpath" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_DDR3_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_ddr3_ila_basic</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">126</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_ddr3_ila_basic" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_DDR3_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_ddr3_vio_sync_out</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">34</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_ddr3_vio_sync_out" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_DDR3_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_ddr2_dq</spirit:name>
        <spirit:displayName>Data</spirit:displayName>
        <spirit:description>Data</spirit:description>
        <spirit:wire>
          <spirit:direction>inout</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_DDR2_DQ_WIDTH&apos;)) )- 1 ">7</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_ddr2_dq" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;DDR2&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_ddr2_dqs_p</spirit:name>
        <spirit:displayName>Data Strobe</spirit:displayName>
        <spirit:description>Data Strobe</spirit:description>
        <spirit:wire>
          <spirit:direction>inout</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_DDR2_DQS_WIDTH&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_ddr2_dqs_p" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;DDR2&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_ddr2_dqs_n</spirit:name>
        <spirit:displayName>Data Strobe</spirit:displayName>
        <spirit:description>Data Strobe</spirit:description>
        <spirit:wire>
          <spirit:direction>inout</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_DDR2_DQS_WIDTH&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_ddr2_dqs_n" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;DDR2&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_ddr2_addr</spirit:name>
        <spirit:displayName>Address</spirit:displayName>
        <spirit:description>Address</spirit:description>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_DDR2_ROW_WIDTH&apos;)) )- 1 ">13</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_ddr2_addr" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;DDR2&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_ddr2_ba</spirit:name>
        <spirit:displayName>Bank Address</spirit:displayName>
        <spirit:description>Bank Address</spirit:description>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_DDR2_BANK_WIDTH&apos;)) )- 1 ">2</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_ddr2_ba" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;DDR2&quot; and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;DDR2&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_ddr2_ras_n</spirit:name>
        <spirit:displayName>row address strobe</spirit:displayName>
        <spirit:description>row address strobe</spirit:description>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_ddr2_ras_n" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;DDR2&quot; and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;DDR2&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_ddr2_cas_n</spirit:name>
        <spirit:displayName>column address strobe</spirit:displayName>
        <spirit:description>column address strobe</spirit:description>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_ddr2_cas_n" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;DDR2&quot; and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;DDR2&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_ddr2_we_n</spirit:name>
        <spirit:displayName>write enable</spirit:displayName>
        <spirit:description>write enable</spirit:description>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_ddr2_we_n" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;DDR2&quot; and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;DDR2&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_ddr2_reset_n</spirit:name>
        <spirit:displayName>reset to memory device</spirit:displayName>
        <spirit:description>reset to memory device</spirit:description>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_ddr2_reset_n" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;DDR3&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_ddr2_ck_p</spirit:name>
        <spirit:displayName>clock to memory device</spirit:displayName>
        <spirit:description>clock to memory device</spirit:description>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_DDR2_CK_WIDTH&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_ddr2_ck_p" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;DDR2&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_ddr2_ck_n</spirit:name>
        <spirit:displayName>clock to memory device</spirit:displayName>
        <spirit:description>clock to memory device</spirit:description>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_DDR2_CK_WIDTH&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_ddr2_ck_n" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;DDR2&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_ddr2_cke</spirit:name>
        <spirit:displayName>clock enable</spirit:displayName>
        <spirit:description>clock enable</spirit:description>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_DDR2_CKE_WIDTH&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_ddr2_cke" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;DDR2&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_ddr2_cs_n</spirit:name>
        <spirit:displayName>chip select</spirit:displayName>
        <spirit:description>chip select</spirit:description>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_DDR2_CS_WIDTH&apos;)) * spirit:decode(id(&apos;MODELPARAM_VALUE.C7_DDR2_nCS_PER_RANK&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_ddr2_cs_n" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_DDR2_USE_CS_PORT&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_ddr2_dm</spirit:name>
        <spirit:displayName>data mask</spirit:displayName>
        <spirit:description>data mask</spirit:description>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_DDR2_DM_WIDTH&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_ddr2_dm" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_DDR2_USE_DM_PORT&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_ddr2_odt</spirit:name>
        <spirit:displayName>on die termination</spirit:displayName>
        <spirit:description>on die termination</spirit:description>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_DDR2_ODT_WIDTH&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_ddr2_odt" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;DDR2&quot; and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;DDR2&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_DDR2_USE_ODT_PORT&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_ddr2_parity</spirit:name>
        <spirit:displayName>parity bit</spirit:displayName>
        <spirit:description>parity bit</spirit:description>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_ddr2_parity" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_DDR2_REG_CTRL&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_ddr2_dbg_pi_counter_read_val</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">4</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_ddr2_dbg_pi_counter_read_val" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_DDR2_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_ddr2_dbg_byte_sel</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_DDR2_DQS_CNT_WIDTH&apos;)) + 1 )- 1 ">1</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_ddr2_dbg_byte_sel" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_DDR2_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_ddr2_dbg_sel_pi_incdec</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_ddr2_dbg_sel_pi_incdec" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_DDR2_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_ddr2_dbg_pi_f_inc</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_ddr2_dbg_pi_f_inc" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_DDR2_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_ddr2_dbg_pi_f_dec</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_ddr2_dbg_pi_f_dec" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_DDR2_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_ddr2_dbg_sel_po_incdec</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_ddr2_dbg_sel_po_incdec" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_DDR2_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_ddr2_dbg_po_f_inc</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_ddr2_dbg_po_f_inc" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_DDR2_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_ddr2_dbg_po_f_stg23_sel</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_ddr2_dbg_po_f_stg23_sel" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_DDR2_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_ddr2_dbg_po_f_dec</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_ddr2_dbg_po_f_dec" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_DDR2_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_ddr2_dbg_po_counter_read_val</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">7</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_ddr2_dbg_po_counter_read_val" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_DDR2_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_ddr2_ila_wrpath</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">254</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_ddr2_ila_wrpath" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_DDR2_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_ddr2_ila_rdpath</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">1022</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_ddr2_ila_rdpath" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_DDR2_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_ddr2_ila_basic</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">126</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_ddr2_ila_basic" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_DDR2_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_ddr2_vio_sync_out</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">34</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_ddr2_vio_sync_out" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_DDR2_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_lpddr2_dq</spirit:name>
        <spirit:displayName>Data</spirit:displayName>
        <spirit:description>Data</spirit:description>
        <spirit:wire>
          <spirit:direction>inout</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_LPDDR2_DQ_WIDTH&apos;)) )- 1 ">7</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_lpddr2_dq" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_lpddr2_dqs_p</spirit:name>
        <spirit:displayName>Data Strobe</spirit:displayName>
        <spirit:description>Data Strobe</spirit:description>
        <spirit:wire>
          <spirit:direction>inout</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_LPDDR2_DQS_WIDTH&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_lpddr2_dqs_p" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_lpddr2_dqs_n</spirit:name>
        <spirit:displayName>Data Strobe</spirit:displayName>
        <spirit:description>Data Strobe</spirit:description>
        <spirit:wire>
          <spirit:direction>inout</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_LPDDR2_DQS_WIDTH&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_lpddr2_dqs_n" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_lpddr2_ca</spirit:name>
        <spirit:displayName>Address</spirit:displayName>
        <spirit:description>Address</spirit:description>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">9</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_lpddr2_ca" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_lpddr2_ck_p</spirit:name>
        <spirit:displayName>clock to memory device</spirit:displayName>
        <spirit:description>clock to memory device</spirit:description>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_LPDDR2_CK_WIDTH&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_lpddr2_ck_p" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_lpddr2_ck_n</spirit:name>
        <spirit:displayName>clock to memory device</spirit:displayName>
        <spirit:description>clock to memory device</spirit:description>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_LPDDR2_CK_WIDTH&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_lpddr2_ck_n" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_lpddr2_cke</spirit:name>
        <spirit:displayName>clock enable</spirit:displayName>
        <spirit:description>clock enable</spirit:description>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_LPDDR2_CKE_WIDTH&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_lpddr2_cke" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_lpddr2_cs_n</spirit:name>
        <spirit:displayName>chip select</spirit:displayName>
        <spirit:description>chip select</spirit:description>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_LPDDR2_CS_WIDTH&apos;)) * spirit:decode(id(&apos;MODELPARAM_VALUE.C7_LPDDR2_nCS_PER_RANK&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_lpddr2_cs_n" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_LPDDR2_USE_CS_PORT&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_lpddr2_dm</spirit:name>
        <spirit:displayName>data mask</spirit:displayName>
        <spirit:description>data mask</spirit:description>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_LPDDR2_DM_WIDTH&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_lpddr2_dm" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_LPDDR2_USE_DM_PORT&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_lpddr2_parity</spirit:name>
        <spirit:displayName>parity bit</spirit:displayName>
        <spirit:description>parity bit</spirit:description>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_lpddr2_parity" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_LPDDR2_REG_CTRL&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_lpddr2_dbg_pi_counter_read_val</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">4</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_lpddr2_dbg_pi_counter_read_val" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_LPDDR2_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_lpddr2_dbg_byte_sel</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_LPDDR2_DQS_CNT_WIDTH&apos;)) + 1 )- 1 ">1</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_lpddr2_dbg_byte_sel" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_LPDDR2_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_lpddr2_dbg_sel_pi_incdec</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_lpddr2_dbg_sel_pi_incdec" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_LPDDR2_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_lpddr2_dbg_pi_f_inc</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_lpddr2_dbg_pi_f_inc" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_LPDDR2_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_lpddr2_dbg_pi_f_dec</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_lpddr2_dbg_pi_f_dec" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_LPDDR2_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_lpddr2_dbg_sel_po_incdec</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_lpddr2_dbg_sel_po_incdec" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_LPDDR2_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_lpddr2_dbg_po_f_inc</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_lpddr2_dbg_po_f_inc" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_LPDDR2_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_lpddr2_dbg_po_f_stg23_sel</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_lpddr2_dbg_po_f_stg23_sel" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_LPDDR2_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_lpddr2_dbg_po_f_dec</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_lpddr2_dbg_po_f_dec" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_LPDDR2_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_lpddr2_dbg_po_counter_read_val</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">7</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_lpddr2_dbg_po_counter_read_val" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_LPDDR2_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_lpddr2_ila_wrpath</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">254</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_lpddr2_ila_wrpath" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_LPDDR2_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_lpddr2_ila_rdpath</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">1022</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_lpddr2_ila_rdpath" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_LPDDR2_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_lpddr2_ila_basic</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">126</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_lpddr2_ila_basic" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_LPDDR2_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_lpddr2_vio_sync_out</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">34</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_lpddr2_vio_sync_out" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_LPDDR2_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_dbg_byte_sel</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_DQS_CNT_WIDTH&apos;)) + 1 )- 1 ">1</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_dbg_byte_sel" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;DDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_dbg_sel_pi_incdec</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_dbg_sel_pi_incdec" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;DDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_dbg_pi_f_inc</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_dbg_pi_f_inc" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;DDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_dbg_pi_f_dec</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_dbg_pi_f_dec" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;DDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_dbg_sel_po_incdec</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_dbg_sel_po_incdec" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;DDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_dbg_po_f_inc</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_dbg_po_f_inc" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;DDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_dbg_po_f_stg23_sel</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_dbg_po_f_stg23_sel" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;DDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_dbg_po_f_dec</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_dbg_po_f_dec" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;DDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_dbg_po_counter_read_val</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">7</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_dbg_po_counter_read_val" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;DDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_app_addr</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_DDRX_ADDR_WIDTH&apos;)) )- 1 ">7</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_app_addr" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;DDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_app_cmd</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">2</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_app_cmd" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;DDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_app_en</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_app_en" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;DDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_app_wdf_data</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_DDRX_nCK_PER_CLK&apos;)) * 2 * spirit:decode(id(&apos;MODELPARAM_VALUE.C7_DDRX_DATA_WIDTH&apos;)) )- 1 ">31</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_app_wdf_data" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;DDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_app_wdf_end</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_app_wdf_end" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;DDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_app_wdf_mask</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_DDRX_nCK_PER_CLK&apos;)) * 2 * spirit:decode(id(&apos;MODELPARAM_VALUE.C7_DDRX_DATA_WIDTH&apos;)) / 8 )- 1 ">3</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_app_wdf_mask" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;DDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_app_wdf_wren</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_app_wdf_wren" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;DDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_app_correct_en_i</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_app_correct_en_i" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;DDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_ECC&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_app_rd_data</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_DDRX_nCK_PER_CLK&apos;)) * 2 * spirit:decode(id(&apos;MODELPARAM_VALUE.C7_DDRX_DATA_WIDTH&apos;)) )- 1 ">31</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_app_rd_data" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;DDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_app_rd_data_end</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_app_rd_data_end" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;DDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_app_rd_data_valid</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_app_rd_data_valid" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;DDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_app_rdy</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_app_rdy" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;DDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_app_wdf_rdy</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_app_wdf_rdy" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;DDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_app_sr_req</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_app_sr_req" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;DDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_app_sr_active</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_app_sr_active" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;DDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_app_ref_req</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_app_ref_req" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;DDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_app_ref_ack</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_app_ref_ack" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;DDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_app_zq_req</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_app_zq_req" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;DDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_app_zq_ack</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_app_zq_ack" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;DDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_app_raw_not_ecc</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( 2 * spirit:decode(id(&apos;MODELPARAM_VALUE.C7_DDRX_nCK_PER_CLK&apos;)) )- 1 ">3</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_app_raw_not_ecc" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;DDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_ECC&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_app_ecc_multiple_err</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( 2 * spirit:decode(id(&apos;MODELPARAM_VALUE.C7_DDRX_nCK_PER_CLK&apos;)) )- 1 ">3</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_app_ecc_multiple_err" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;DDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_ECC&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_ddr3_app_addr</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_DDR3_ADDR_WIDTH&apos;)) )- 1 ">7</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_ddr3_app_addr" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_ddr3_app_cmd</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">2</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_ddr3_app_cmd" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_ddr3_app_en</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_ddr3_app_en" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_ddr3_app_wdf_data</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_DDR3_nCK_PER_CLK&apos;)) * 2 * spirit:decode(id(&apos;MODELPARAM_VALUE.C7_DDR3_DATA_WIDTH&apos;)) )- 1 ">31</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_ddr3_app_wdf_data" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_ddr3_app_wdf_end</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_ddr3_app_wdf_end" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_ddr3_app_wdf_mask</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_DDR3_nCK_PER_CLK&apos;)) * 2 * spirit:decode(id(&apos;MODELPARAM_VALUE.C7_DDR3_DATA_WIDTH&apos;)) / 8 )- 1 ">3</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_ddr3_app_wdf_mask" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_ddr3_app_wdf_wren</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_ddr3_app_wdf_wren" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_ddr3_app_correct_en_i</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_ddr3_app_correct_en_i" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_ECC&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_ddr3_app_rd_data</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_DDR3_nCK_PER_CLK&apos;)) * 2 * spirit:decode(id(&apos;MODELPARAM_VALUE.C7_DDR3_DATA_WIDTH&apos;)) )- 1 ">31</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_ddr3_app_rd_data" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_ddr3_app_rd_data_end</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_ddr3_app_rd_data_end" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_ddr3_app_rd_data_valid</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_ddr3_app_rd_data_valid" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_ddr3_app_rdy</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_ddr3_app_rdy" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_ddr3_app_wdf_rdy</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_ddr3_app_wdf_rdy" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_ddr3_app_sr_req</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_ddr3_app_sr_req" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_ddr3_app_sr_active</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_ddr3_app_sr_active" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_ddr3_app_ref_req</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_ddr3_app_ref_req" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_ddr3_app_ref_ack</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_ddr3_app_ref_ack" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_ddr3_app_zq_req</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_ddr3_app_zq_req" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_ddr3_app_zq_ack</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_ddr3_app_zq_ack" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_ddr3_app_raw_not_ecc</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( 2 * spirit:decode(id(&apos;MODELPARAM_VALUE.C7_DDR3_nCK_PER_CLK&apos;)) )- 1 ">3</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_ddr3_app_raw_not_ecc" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_ECC&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_ddr3_app_ecc_multiple_err</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( 2 * spirit:decode(id(&apos;MODELPARAM_VALUE.C7_DDR3_nCK_PER_CLK&apos;)) )- 1 ">3</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_ddr3_app_ecc_multiple_err" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_ECC&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_ddr2_app_addr</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_DDR2_ADDR_WIDTH&apos;)) )- 1 ">7</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_ddr2_app_addr" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_ddr2_app_cmd</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">2</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_ddr2_app_cmd" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_ddr2_app_en</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_ddr2_app_en" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_ddr2_app_wdf_data</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_DDR2_nCK_PER_CLK&apos;)) * 2 * spirit:decode(id(&apos;MODELPARAM_VALUE.C7_DDR2_DATA_WIDTH&apos;)) )- 1 ">31</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_ddr2_app_wdf_data" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_ddr2_app_wdf_end</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_ddr2_app_wdf_end" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_ddr2_app_wdf_mask</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_DDR2_nCK_PER_CLK&apos;)) * 2 * spirit:decode(id(&apos;MODELPARAM_VALUE.C7_DDR2_DATA_WIDTH&apos;)) / 8 )- 1 ">3</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_ddr2_app_wdf_mask" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_ddr2_app_wdf_wren</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_ddr2_app_wdf_wren" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_ddr2_app_correct_en_i</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_ddr2_app_correct_en_i" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_ECC&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_ddr2_app_rd_data</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_DDR2_nCK_PER_CLK&apos;)) * 2 * spirit:decode(id(&apos;MODELPARAM_VALUE.C7_DDR2_DATA_WIDTH&apos;)) )- 1 ">31</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_ddr2_app_rd_data" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_ddr2_app_rd_data_end</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_ddr2_app_rd_data_end" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_ddr2_app_rd_data_valid</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_ddr2_app_rd_data_valid" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_ddr2_app_rdy</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_ddr2_app_rdy" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_ddr2_app_wdf_rdy</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_ddr2_app_wdf_rdy" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_ddr2_app_sr_req</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_ddr2_app_sr_req" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_ddr2_app_sr_active</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_ddr2_app_sr_active" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_ddr2_app_ref_req</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_ddr2_app_ref_req" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_ddr2_app_ref_ack</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_ddr2_app_ref_ack" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_ddr2_app_zq_req</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_ddr2_app_zq_req" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_ddr2_app_zq_ack</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_ddr2_app_zq_ack" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_ddr2_app_raw_not_ecc</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( 2 * spirit:decode(id(&apos;MODELPARAM_VALUE.C7_DDR2_nCK_PER_CLK&apos;)) )- 1 ">3</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_ddr2_app_raw_not_ecc" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_ECC&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_ddr2_app_ecc_multiple_err</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( 2 * spirit:decode(id(&apos;MODELPARAM_VALUE.C7_DDR2_nCK_PER_CLK&apos;)) )- 1 ">3</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_ddr2_app_ecc_multiple_err" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_ECC&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_lpddr2_app_addr</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_LPDDR2_ADDR_WIDTH&apos;)) )- 1 ">7</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_lpddr2_app_addr" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_lpddr2_app_cmd</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">2</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_lpddr2_app_cmd" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_lpddr2_app_en</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_lpddr2_app_en" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_lpddr2_app_wdf_data</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_LPDDR2_nCK_PER_CLK&apos;)) * 2 * spirit:decode(id(&apos;MODELPARAM_VALUE.C7_LPDDR2_DATA_WIDTH&apos;)) )- 1 ">31</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_lpddr2_app_wdf_data" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_lpddr2_app_wdf_end</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_lpddr2_app_wdf_end" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_lpddr2_app_wdf_mask</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_LPDDR2_nCK_PER_CLK&apos;)) * 2 * spirit:decode(id(&apos;MODELPARAM_VALUE.C7_LPDDR2_DATA_WIDTH&apos;)) / 8 )- 1 ">3</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_lpddr2_app_wdf_mask" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_lpddr2_app_wdf_wren</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_lpddr2_app_wdf_wren" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_lpddr2_app_correct_en_i</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_lpddr2_app_correct_en_i" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_ECC&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_lpddr2_app_rd_data</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_LPDDR2_nCK_PER_CLK&apos;)) * 2 * spirit:decode(id(&apos;MODELPARAM_VALUE.C7_LPDDR2_DATA_WIDTH&apos;)) )- 1 ">31</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_lpddr2_app_rd_data" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_lpddr2_app_rd_data_end</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_lpddr2_app_rd_data_end" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_lpddr2_app_rd_data_valid</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_lpddr2_app_rd_data_valid" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_lpddr2_app_rdy</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_lpddr2_app_rdy" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_lpddr2_app_wdf_rdy</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_lpddr2_app_wdf_rdy" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_lpddr2_app_sr_req</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_lpddr2_app_sr_req" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_lpddr2_app_sr_active</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_lpddr2_app_sr_active" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_lpddr2_app_ref_req</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_lpddr2_app_ref_req" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_lpddr2_app_ref_ack</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_lpddr2_app_ref_ack" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_lpddr2_app_zq_req</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_lpddr2_app_zq_req" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_lpddr2_app_zq_ack</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_lpddr2_app_zq_ack" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_lpddr2_app_raw_not_ecc</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( 2 * spirit:decode(id(&apos;MODELPARAM_VALUE.C7_LPDDR2_nCK_PER_CLK&apos;)) )- 1 ">3</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_lpddr2_app_raw_not_ecc" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_ECC&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_lpddr2_app_ecc_multiple_err</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( 2 * spirit:decode(id(&apos;MODELPARAM_VALUE.C7_LPDDR2_nCK_PER_CLK&apos;)) )- 1 ">3</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_lpddr2_app_ecc_multiple_err" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_ECC&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_ui_clk_sync_rst</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_ui_clk_sync_rst" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;DDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;RLDII&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;RLDIII&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_ddr3_ui_clk_sync_rst</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_ddr3_ui_clk_sync_rst" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;DDR3&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;DDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;RLDII&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;RLDIII&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_ddr2_ui_clk_sync_rst</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_ddr2_ui_clk_sync_rst" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;DDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;DDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;RLDII&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;RLDIII&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_lpddr2_ui_clk_sync_rst</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_lpddr2_ui_clk_sync_rst" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;DDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;RLDII&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;RLDIII&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_qdriip_ui_clk_sync_rst</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_qdriip_ui_clk_sync_rst" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;DDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;RLDII&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;RLDIII&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_rldii_ui_clk_sync_rst</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_rldii_ui_clk_sync_rst" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;RLDII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;DDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;RLDII&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;RLDIII&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_rldiii_ui_clk_sync_rst</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_rldiii_ui_clk_sync_rst" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;RLDIII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;DDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;RLDII&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;RLDIII&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_ui_clk</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_ui_clk" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;DDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;RLDII&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;RLDIII&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_ui_addn_clk_0</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_ui_addn_clk_0" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_UI_EXTRA_CLOCKS&apos;)) = &quot;TRUE&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MMCM_CLKOUT0_EN&apos;)) = &quot;TRUE&quot; ) and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;DDR2&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_ui_addn_clk_1</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_ui_addn_clk_1" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_UI_EXTRA_CLOCKS&apos;)) = &quot;TRUE&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MMCM_CLKOUT1_EN&apos;)) = &quot;TRUE&quot; ) and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;DDR2&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_ui_addn_clk_2</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_ui_addn_clk_2" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_UI_EXTRA_CLOCKS&apos;)) = &quot;TRUE&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MMCM_CLKOUT2_EN&apos;)) = &quot;TRUE&quot; ) and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;DDR2&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_ui_addn_clk_3</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_ui_addn_clk_3" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_UI_EXTRA_CLOCKS&apos;)) = &quot;TRUE&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MMCM_CLKOUT3_EN&apos;)) = &quot;TRUE&quot; ) and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;DDR2&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_ui_addn_clk_4</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_ui_addn_clk_4" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_UI_EXTRA_CLOCKS&apos;)) = &quot;TRUE&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MMCM_CLKOUT4_EN&apos;)) = &quot;TRUE&quot; ) and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;DDR2&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_s_axi_ctrl_awvalid</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_s_axi_ctrl_awvalid" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_USE_AXI&apos;)) = 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_ECC&apos;)) = &quot;ON&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_s_axi_ctrl_awready</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_s_axi_ctrl_awready" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_USE_AXI&apos;)) = 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_ECC&apos;)) = &quot;ON&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_s_axi_ctrl_awaddr</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_C_S_AXI_CTRL_ADDR_WIDTH&apos;)) )- 1 ">31</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_s_axi_ctrl_awaddr" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_USE_AXI&apos;)) = 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_ECC&apos;)) = &quot;ON&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_s_axi_ctrl_wvalid</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_s_axi_ctrl_wvalid" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_USE_AXI&apos;)) = 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_ECC&apos;)) = &quot;ON&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_s_axi_ctrl_wready</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_s_axi_ctrl_wready" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_USE_AXI&apos;)) = 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_ECC&apos;)) = &quot;ON&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_s_axi_ctrl_wdata</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_C_S_AXI_CTRL_DATA_WIDTH&apos;)) )- 1 ">31</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_s_axi_ctrl_wdata" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_USE_AXI&apos;)) = 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_ECC&apos;)) = &quot;ON&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_s_axi_ctrl_bvalid</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_s_axi_ctrl_bvalid" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_USE_AXI&apos;)) = 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_ECC&apos;)) = &quot;ON&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_s_axi_ctrl_bready</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_s_axi_ctrl_bready" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_USE_AXI&apos;)) = 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_ECC&apos;)) = &quot;ON&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_s_axi_ctrl_bresp</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">1</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_s_axi_ctrl_bresp" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_USE_AXI&apos;)) = 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_ECC&apos;)) = &quot;ON&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_s_axi_ctrl_arvalid</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_s_axi_ctrl_arvalid" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_USE_AXI&apos;)) = 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_ECC&apos;)) = &quot;ON&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_s_axi_ctrl_arready</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_s_axi_ctrl_arready" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_USE_AXI&apos;)) = 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_ECC&apos;)) = &quot;ON&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_s_axi_ctrl_araddr</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_C_S_AXI_CTRL_ADDR_WIDTH&apos;)) )- 1 ">31</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_s_axi_ctrl_araddr" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_USE_AXI&apos;)) = 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_ECC&apos;)) = &quot;ON&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_s_axi_ctrl_rvalid</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_s_axi_ctrl_rvalid" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_USE_AXI&apos;)) = 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_ECC&apos;)) = &quot;ON&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_s_axi_ctrl_rready</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_s_axi_ctrl_rready" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_USE_AXI&apos;)) = 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_ECC&apos;)) = &quot;ON&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_s_axi_ctrl_rdata</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_C_S_AXI_CTRL_DATA_WIDTH&apos;)) )- 1 ">31</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_s_axi_ctrl_rdata" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_USE_AXI&apos;)) = 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_ECC&apos;)) = &quot;ON&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_s_axi_ctrl_rresp</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">1</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_s_axi_ctrl_rresp" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_USE_AXI&apos;)) = 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_ECC&apos;)) = &quot;ON&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_s_axi_awid</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_C_S_AXI_ID_WIDTH&apos;)) )- 1 ">3</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
          <spirit:driver>
            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
          </spirit:driver>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_s_axi_awid" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_s_axi_awaddr</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_C_S_AXI_ADDR_WIDTH&apos;)) )- 1 ">31</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_s_axi_awaddr" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_s_axi_awlen</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">7</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_s_axi_awlen" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_s_axi_awsize</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">2</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_s_axi_awsize" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_s_axi_awburst</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">1</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_s_axi_awburst" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_s_axi_awlock</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
          <spirit:driver>
            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
          </spirit:driver>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_s_axi_awlock" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_s_axi_awcache</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">3</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
          <spirit:driver>
            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
          </spirit:driver>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_s_axi_awcache" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_s_axi_awprot</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">2</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
          <spirit:driver>
            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
          </spirit:driver>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_s_axi_awprot" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_s_axi_awqos</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">3</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
          <spirit:driver>
            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
          </spirit:driver>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_s_axi_awqos" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_s_axi_awvalid</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_s_axi_awvalid" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_s_axi_awready</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_s_axi_awready" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_s_axi_wdata</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_C_S_AXI_DATA_WIDTH&apos;)) )- 1 ">31</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_s_axi_wdata" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_s_axi_wstrb</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_C_S_AXI_DATA_WIDTH&apos;)) / 8 )- 1 ">3</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_s_axi_wstrb" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_s_axi_wlast</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_s_axi_wlast" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_s_axi_wvalid</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_s_axi_wvalid" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_s_axi_wready</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_s_axi_wready" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_s_axi_bready</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_s_axi_bready" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_s_axi_bid</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_C_S_AXI_ID_WIDTH&apos;)) )- 1 ">3</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_s_axi_bid" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_s_axi_bresp</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">1</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_s_axi_bresp" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_s_axi_bvalid</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_s_axi_bvalid" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_s_axi_arid</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_C_S_AXI_ID_WIDTH&apos;)) )- 1 ">3</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
          <spirit:driver>
            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
          </spirit:driver>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_s_axi_arid" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_s_axi_araddr</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_C_S_AXI_ADDR_WIDTH&apos;)) )- 1 ">31</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_s_axi_araddr" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_s_axi_arlen</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">7</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_s_axi_arlen" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_s_axi_arsize</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">2</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_s_axi_arsize" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_s_axi_arburst</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">1</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_s_axi_arburst" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_s_axi_arlock</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
          <spirit:driver>
            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
          </spirit:driver>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_s_axi_arlock" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_s_axi_arcache</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">3</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
          <spirit:driver>
            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
          </spirit:driver>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_s_axi_arcache" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_s_axi_arprot</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">2</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
          <spirit:driver>
            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
          </spirit:driver>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_s_axi_arprot" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_s_axi_arqos</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">3</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
          <spirit:driver>
            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
          </spirit:driver>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_s_axi_arqos" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_s_axi_arvalid</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_s_axi_arvalid" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_s_axi_arready</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_s_axi_arready" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_s_axi_rready</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_s_axi_rready" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_s_axi_rid</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_C_S_AXI_ID_WIDTH&apos;)) )- 1 ">3</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_s_axi_rid" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_s_axi_rdata</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_C_S_AXI_DATA_WIDTH&apos;)) )- 1 ">31</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_s_axi_rdata" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_s_axi_rresp</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">1</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_s_axi_rresp" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_s_axi_rlast</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_s_axi_rlast" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_s_axi_rvalid</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_s_axi_rvalid" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_interrupt</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_interrupt" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_USE_AXI&apos;)) = 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_ECC&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_mmcm_locked</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_mmcm_locked" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_USE_AXI&apos;)) = 1 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_qdriip_cq_p</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_QDRIIP_NUM_DEVICES&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_qdriip_cq_p" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_qdriip_cq_n</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_QDRIIP_NUM_DEVICES&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_qdriip_cq_n" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_qdriip_qvld</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_QDRIIP_NUM_DEVICES&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_qdriip_qvld" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_qdriip_q</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_QDRIIP_DATA_WIDTH&apos;)) )- 1 ">17</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_qdriip_q" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_qdriip_k_p</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_QDRIIP_NUM_DEVICES&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_qdriip_k_p" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_qdriip_k_n</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_QDRIIP_NUM_DEVICES&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_qdriip_k_n" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_qdriip_d</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_QDRIIP_DATA_WIDTH&apos;)) )- 1 ">17</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_qdriip_d" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_qdriip_sa</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_QDRIIP_ADDR_WIDTH&apos;)) )- 1 ">28</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_qdriip_sa" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_qdriip_w_n</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_qdriip_w_n" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_qdriip_r_n</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_qdriip_r_n" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_qdriip_bw_n</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_QDRIIP_BW_WIDTH&apos;)) )- 1 ">7</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_qdriip_bw_n" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_qdriip_dll_off_n</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_qdriip_dll_off_n" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_qdriip_dbg_pi_counter_read_val</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">4</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_qdriip_dbg_pi_counter_read_val" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_QDRIIP_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_qdriip_dbg_win_inc</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_qdriip_dbg_win_inc" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_QDRIIP_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_qdriip_dbg_win_dec</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_qdriip_dbg_win_dec" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_QDRIIP_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_qdriip_dbg_win_active</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_qdriip_dbg_win_active" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_QDRIIP_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_qdriip_dbg_win_current_byte</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">2</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_qdriip_dbg_win_current_byte" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_QDRIIP_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_qdriip_ila0_data</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">254</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_qdriip_ila0_data" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_QDRIIP_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_qdriip_ila0_trig</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">6</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_qdriip_ila0_trig" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_QDRIIP_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_qdriip_ila1_data</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">269</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_qdriip_ila1_data" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_QDRIIP_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_qdriip_ila1_trig</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">14</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_qdriip_ila1_trig" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_QDRIIP_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_qdriip_vio2_async_in</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">198</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_qdriip_vio2_async_in" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_QDRIIP_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_qdriip_vio2_sync_out</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">34</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_qdriip_vio2_sync_out" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_QDRIIP_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_app_wr_cmd0</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_app_wr_cmd0" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_app_wr_addr0</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_QDRIIP_ADDR_WIDTH&apos;)) )- 1 ">28</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_app_wr_addr0" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_app_wr_data0</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_QDRIIP_BURST_LEN&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_app_wr_data0" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_app_wr_bw_n0</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_QDRIIP_BURST_LEN&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_app_wr_bw_n0" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_app_rd_cmd0</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_app_rd_cmd0" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_app_rd_addr0</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_QDRIIP_ADDR_WIDTH&apos;)) )- 1 ">28</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_app_rd_addr0" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_app_rd_valid0</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_app_rd_valid0" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_app_rd_data0</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_QDRIIP_BURST_LEN&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_app_rd_data0" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_app_wr_cmd1</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_app_wr_cmd1" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_app_wr_addr1</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_QDRIIP_ADDR_WIDTH&apos;)) )- 1 ">28</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_app_wr_addr1" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_app_wr_data1</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" (( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_QDRIIP_DATA_WIDTH&apos;)) * 2 ))- 1 ">35</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_app_wr_data1" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_app_wr_bw_n1</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" (( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_QDRIIP_BW_WIDTH&apos;)) * 2 ))- 1 ">15</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_app_wr_bw_n1" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_app_rd_cmd1</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_app_rd_cmd1" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_app_rd_addr1</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_QDRIIP_ADDR_WIDTH&apos;)) )- 1 ">28</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_app_rd_addr1" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_app_rd_valid1</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_app_rd_valid1" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_app_rd_data1</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" (( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_QDRIIP_DATA_WIDTH&apos;)) * 2 ))- 1 ">35</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_app_rd_data1" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_clk</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_clk" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_rst_clk</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_rst_clk" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_qdriip_app_wr_cmd0</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_qdriip_app_wr_cmd0" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_qdriip_app_wr_addr0</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_QDRIIP_ADDR_WIDTH&apos;)) )- 1 ">28</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_qdriip_app_wr_addr0" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_qdriip_app_wr_data0</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_QDRIIP_BURST_LEN&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_qdriip_app_wr_data0" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_qdriip_app_wr_bw_n0</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_QDRIIP_BURST_LEN&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_qdriip_app_wr_bw_n0" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_qdriip_app_rd_cmd0</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_qdriip_app_rd_cmd0" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_qdriip_app_rd_addr0</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_QDRIIP_ADDR_WIDTH&apos;)) )- 1 ">28</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_qdriip_app_rd_addr0" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_qdriip_app_rd_valid0</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_qdriip_app_rd_valid0" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_qdriip_app_rd_data0</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_QDRIIP_BURST_LEN&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_qdriip_app_rd_data0" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_qdriip_app_wr_cmd1</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_qdriip_app_wr_cmd1" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_qdriip_app_wr_addr1</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_QDRIIP_ADDR_WIDTH&apos;)) )- 1 ">28</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_qdriip_app_wr_addr1" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_qdriip_app_wr_data1</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" (( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_QDRIIP_DATA_WIDTH&apos;)) * 2 ))- 1 ">35</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_qdriip_app_wr_data1" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_qdriip_app_wr_bw_n1</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" (( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_QDRIIP_BW_WIDTH&apos;)) * 2 ))- 1 ">15</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_qdriip_app_wr_bw_n1" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_qdriip_app_rd_cmd1</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_qdriip_app_rd_cmd1" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_qdriip_app_rd_addr1</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_QDRIIP_ADDR_WIDTH&apos;)) )- 1 ">28</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_qdriip_app_rd_addr1" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_qdriip_app_rd_valid1</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_qdriip_app_rd_valid1" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_qdriip_app_rd_data1</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" (( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_QDRIIP_DATA_WIDTH&apos;)) * 2 ))- 1 ">35</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_qdriip_app_rd_data1" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_qdriip_clk</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_qdriip_clk" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_qdriip_rst_clk</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_qdriip_rst_clk" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_rldii_qk_p</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_RLDII_QK_WIDTH&apos;)) )- 1 ">7</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_rldii_qk_p" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;RLDII&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_rldii_qk_n</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_RLDII_QK_WIDTH&apos;)) )- 1 ">7</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_rldii_qk_n" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;RLDII&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_rldii_dq</spirit:name>
        <spirit:wire>
          <spirit:direction>inout</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_RLDII_DATA_WIDTH&apos;)) )- 1 ">17</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_rldii_dq" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;RLDII&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_rldii_dm</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_RLDII_DM_WIDTH&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_rldii_dm" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;RLDII&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_rldii_dk_p</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_RLDII_DK_WIDTH&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_rldii_dk_p" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;RLDII&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_rldii_dk_n</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_RLDII_DK_WIDTH&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_rldii_dk_n" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;RLDII&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_rldii_ck_p</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_RLDII_NUM_DEVICES&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_rldii_ck_p" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;RLDII&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_rldii_ck_n</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_RLDII_NUM_DEVICES&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_rldii_ck_n" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;RLDII&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_rldii_cs_n</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_RLDII_NUM_DEVICES&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_rldii_cs_n" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;RLDII&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_rldii_a</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_RLDII_RLD_ADDR_WIDTH&apos;)) )- 1 ">28</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_rldii_a" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;RLDII&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_rldii_ba</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_RLDII_BANK_WIDTH&apos;)) )- 1 ">1</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_rldii_ba" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;RLDII&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_rldii_qvld</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_RLDII_QVLD_WIDTH&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_rldii_qvld" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;RLDII&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_rldii_we_n</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_rldii_we_n" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;RLDII&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_rldii_ref_n</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_rldii_ref_n" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;RLDII&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_rldii_reset_n</spirit:name>
        <spirit:displayName>reset to memory device</spirit:displayName>
        <spirit:description>reset to memory device</spirit:description>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_rldii_reset_n" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;RLDII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;RLDIII&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_rldii_dbg_pi_tap_cnt</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">4</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_rldii_dbg_pi_tap_cnt" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;RLDII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_RLDII_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_rldii_dbg_win_inc</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_rldii_dbg_win_inc" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;RLDII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_RLDII_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_rldii_dbg_win_dec</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_rldii_dbg_win_dec" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;RLDII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_RLDII_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_rldii_dbg_win_active</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_rldii_dbg_win_active" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;RLDII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_RLDII_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_rldii_dbg_win_current_byte</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">2</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_rldii_dbg_win_current_byte" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;RLDII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_RLDII_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_rldii_ila0_data</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">638</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_rldii_ila0_data" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;RLDII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_RLDII_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_rldii_ila0_trig</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">30</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_rldii_ila0_trig" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;RLDII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_RLDII_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_rldii_vio1_async_in</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">254</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_rldii_vio1_async_in" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;RLDII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_RLDII_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_rldii_vio1_async_out</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">62</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_rldii_vio1_async_out" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;RLDII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_RLDII_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_rldii_vio1_sync_out</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">62</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_rldii_vio1_sync_out" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;RLDII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_RLDII_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_rldiii_qk_p</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_RLDIII_QK_WIDTH&apos;)) )- 1 ">7</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_rldiii_qk_p" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;RLDIII&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_rldiii_qk_n</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_RLDIII_QK_WIDTH&apos;)) )- 1 ">7</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_rldiii_qk_n" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;RLDIII&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_rldiii_dq</spirit:name>
        <spirit:wire>
          <spirit:direction>inout</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_RLDIII_DATA_WIDTH&apos;)) )- 1 ">17</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_rldiii_dq" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;RLDIII&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_rldiii_dm</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_RLDIII_DM_WIDTH&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_rldiii_dm" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;RLDIII&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_rldiii_dk_p</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_RLDIII_DK_WIDTH&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_rldiii_dk_p" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;RLDIII&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_rldiii_dk_n</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_RLDIII_DK_WIDTH&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_rldiii_dk_n" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;RLDIII&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_rldiii_ck_p</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_RLDIII_NUM_DEVICES&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_rldiii_ck_p" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;RLDIII&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_rldiii_ck_n</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_RLDIII_NUM_DEVICES&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_rldiii_ck_n" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;RLDIII&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_rldiii_cs_n</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_RLDIII_NUM_DEVICES&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_rldiii_cs_n" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;RLDIII&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_rldiii_a</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_RLDIII_RLD_ADDR_WIDTH&apos;)) )- 1 ">28</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_rldiii_a" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;RLDIII&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_rldiii_ba</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_RLDIII_BANK_WIDTH&apos;)) )- 1 ">1</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_rldiii_ba" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;RLDIII&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_rldiii_qvld</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_RLDIII_QVLD_WIDTH&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_rldiii_qvld" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;RLDIII&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_rldiii_we_n</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_rldiii_we_n" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;RLDIII&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_rldiii_ref_n</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_rldiii_ref_n" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;RLDIII&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_rldiii_reset_n</spirit:name>
        <spirit:displayName>reset to memory device</spirit:displayName>
        <spirit:description>reset to memory device</spirit:description>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_rldiii_reset_n" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;RLDIII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;RLDIII&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_dbg_pi_tap_cnt</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">4</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_dbg_pi_tap_cnt" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;RLDIII&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;RLDII&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_rldiii_dbg_pi_tap_cnt</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">4</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_rldiii_dbg_pi_tap_cnt" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;RLDIII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_RLDIII_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_rldiii_dbg_win_inc</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_rldiii_dbg_win_inc" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;RLDIII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_RLDIII_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_rldiii_dbg_win_dec</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_rldiii_dbg_win_dec" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;RLDIII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_RLDIII_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_rldiii_dbg_win_active</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_rldiii_dbg_win_active" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;RLDIII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_RLDIII_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_rldiii_dbg_win_current_byte</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">2</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_rldiii_dbg_win_current_byte" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;RLDIII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_RLDIII_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_rldiii_ila0_data</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">638</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_rldiii_ila0_data" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;RLDIII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_RLDIII_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_rldiii_ila0_trig</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">30</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_rldiii_ila0_trig" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;RLDIII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_RLDIII_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_rldiii_vio1_async_in</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">254</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_rldiii_vio1_async_in" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;RLDIII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_RLDIII_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_rldiii_vio1_async_out</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">62</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_rldiii_vio1_async_out" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;RLDIII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_RLDIII_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_rldiii_vio1_sync_out</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">62</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_rldiii_vio1_sync_out" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;RLDIII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_RLDIII_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_dbg_win_inc</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_dbg_win_inc" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;RLDIII&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;RLDII&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_dbg_win_dec</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_dbg_win_dec" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;RLDIII&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;RLDII&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_dbg_win_active</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_dbg_win_active" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;RLDIII&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;RLDII&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_dbg_win_current_byte</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">2</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_dbg_win_current_byte" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;RLDIII&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;RLDII&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_dbg_pi_counter_read_val</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">4</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_dbg_pi_counter_read_val" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;DDR2&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;QDRIIP&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;LPDDR2&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_DEBUG_PORT&apos;)) = &quot;ON&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_user_cmd_en</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_user_cmd_en" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;RLDII&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;RLDIII&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_user_cmd</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_RLDX_CMD_PER_CLK&apos;)) * 2 )- 1 ">1</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_user_cmd" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;RLDII&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;RLDIII&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_user_addr</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_RLDX_ADDR_WIDTH&apos;)) * spirit:decode(id(&apos;MODELPARAM_VALUE.C7_RLDX_CMD_PER_CLK&apos;)) )- 1 ">28</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_user_addr" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;RLDII&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;RLDIII&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_user_ba</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_RLDX_BANK_WIDTH&apos;)) * spirit:decode(id(&apos;MODELPARAM_VALUE.C7_RLDX_CMD_PER_CLK&apos;)) )- 1 ">1</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_user_ba" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;RLDII&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;RLDIII&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_user_wr_en</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_user_wr_en" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;RLDII&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;RLDIII&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_user_wr_data</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_RLDX_DATA_WIDTH&apos;)) * 2 * spirit:decode(id(&apos;MODELPARAM_VALUE.C7_RLDX_nCK_PER_CLK&apos;)) )- 1 ">35</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_user_wr_data" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;RLDII&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;RLDIII&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_user_wr_dm</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_RLDX_DM_WIDTH&apos;)) * 2 * spirit:decode(id(&apos;MODELPARAM_VALUE.C7_RLDX_nCK_PER_CLK&apos;)) )- 1 ">1</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_user_wr_dm" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;RLDII&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;RLDIII&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_user_afifo_empty</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_user_afifo_empty" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;RLDII&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;RLDIII&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_user_afifo_full</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_user_afifo_full" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;RLDII&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;RLDIII&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_user_afifo_aempty</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_user_afifo_aempty" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;RLDII&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;RLDIII&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_user_afifo_afull</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_user_afifo_afull" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;RLDII&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;RLDIII&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_user_wdfifo_empty</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_user_wdfifo_empty" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;RLDII&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;RLDIII&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_user_wdfifo_full</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_user_wdfifo_full" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;RLDII&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;RLDIII&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_user_wdfifo_aempty</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_user_wdfifo_aempty" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;RLDII&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;RLDIII&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_user_wdfifo_afull</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_user_wdfifo_afull" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;RLDII&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;RLDIII&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_user_rd_valid</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_RLDX_nCK_PER_CLK&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_user_rd_valid" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;RLDII&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;RLDIII&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_mem_ck_lock_complete</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_mem_ck_lock_complete" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;RLDII&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;RLDIII&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_user_rd_data</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_RLDX_DATA_WIDTH&apos;)) * 2 * spirit:decode(id(&apos;MODELPARAM_VALUE.C7_RLDX_nCK_PER_CLK&apos;)) )- 1 ">35</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_user_rd_data" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and (( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;RLDII&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;RLDIII&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 0 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_rldii_user_cmd_en</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_rldii_user_cmd_en" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;RLDII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_rldii_user_cmd</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_RLDII_CMD_PER_CLK&apos;)) * 2 )- 1 ">1</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_rldii_user_cmd" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;RLDII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_rldii_user_addr</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_RLDII_ADDR_WIDTH&apos;)) * spirit:decode(id(&apos;MODELPARAM_VALUE.C7_RLDII_CMD_PER_CLK&apos;)) )- 1 ">28</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_rldii_user_addr" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;RLDII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_rldii_user_ba</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_RLDII_BANK_WIDTH&apos;)) * spirit:decode(id(&apos;MODELPARAM_VALUE.C7_RLDII_CMD_PER_CLK&apos;)) )- 1 ">1</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_rldii_user_ba" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;RLDII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_rldii_user_wr_en</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_rldii_user_wr_en" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;RLDII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_rldii_user_wr_data</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_RLDII_DATA_WIDTH&apos;)) * 2 * spirit:decode(id(&apos;MODELPARAM_VALUE.C7_RLDII_nCK_PER_CLK&apos;)) )- 1 ">35</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_rldii_user_wr_data" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;RLDII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_rldii_user_wr_dm</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_RLDII_DM_WIDTH&apos;)) * 2 * spirit:decode(id(&apos;MODELPARAM_VALUE.C7_RLDII_nCK_PER_CLK&apos;)) )- 1 ">1</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_rldii_user_wr_dm" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;RLDII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_rldii_user_afifo_empty</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_rldii_user_afifo_empty" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;RLDII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_rldii_user_afifo_full</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_rldii_user_afifo_full" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;RLDII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_rldii_user_afifo_aempty</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_rldii_user_afifo_aempty" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;RLDII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_rldii_user_afifo_afull</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_rldii_user_afifo_afull" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;RLDII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_rldii_user_wdfifo_empty</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_rldii_user_wdfifo_empty" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;RLDII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_rldii_user_wdfifo_full</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_rldii_user_wdfifo_full" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;RLDII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_rldii_user_wdfifo_aempty</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_rldii_user_wdfifo_aempty" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;RLDII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_rldii_user_wdfifo_afull</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_rldii_user_wdfifo_afull" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;RLDII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_rldii_user_rd_valid</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_RLDII_nCK_PER_CLK&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_rldii_user_rd_valid" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;RLDII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_rldii_mem_ck_lock_complete</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_rldii_mem_ck_lock_complete" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;RLDII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_rldii_user_rd_data</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_RLDII_DATA_WIDTH&apos;)) * 2 * spirit:decode(id(&apos;MODELPARAM_VALUE.C7_RLDII_nCK_PER_CLK&apos;)) )- 1 ">35</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_rldii_user_rd_data" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;RLDII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_rldiii_user_cmd_en</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_rldiii_user_cmd_en" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;RLDIII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_rldiii_user_cmd</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_RLDIII_CMD_PER_CLK&apos;)) * 2 )- 1 ">1</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_rldiii_user_cmd" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;RLDIII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_rldiii_user_addr</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_RLDIII_ADDR_WIDTH&apos;)) * spirit:decode(id(&apos;MODELPARAM_VALUE.C7_RLDIII_CMD_PER_CLK&apos;)) )- 1 ">28</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_rldiii_user_addr" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;RLDIII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_rldiii_user_ba</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_RLDIII_BANK_WIDTH&apos;)) * spirit:decode(id(&apos;MODELPARAM_VALUE.C7_RLDIII_CMD_PER_CLK&apos;)) )- 1 ">1</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_rldiii_user_ba" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;RLDIII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_rldiii_user_wr_en</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_rldiii_user_wr_en" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;RLDIII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_rldiii_user_wr_data</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_RLDIII_DATA_WIDTH&apos;)) * 2 * spirit:decode(id(&apos;MODELPARAM_VALUE.C7_RLDIII_nCK_PER_CLK&apos;)) )- 1 ">35</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_rldiii_user_wr_data" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;RLDIII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_rldiii_user_wr_dm</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_RLDIII_DM_WIDTH&apos;)) * 2 * spirit:decode(id(&apos;MODELPARAM_VALUE.C7_RLDIII_nCK_PER_CLK&apos;)) )- 1 ">1</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_rldiii_user_wr_dm" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;RLDIII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_rldiii_user_afifo_empty</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_rldiii_user_afifo_empty" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;RLDIII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_rldiii_user_afifo_full</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_rldiii_user_afifo_full" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;RLDIII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_rldiii_user_afifo_aempty</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_rldiii_user_afifo_aempty" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;RLDIII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_rldiii_user_afifo_afull</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_rldiii_user_afifo_afull" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;RLDIII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_rldiii_user_wdfifo_empty</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_rldiii_user_wdfifo_empty" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;RLDIII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_rldiii_user_wdfifo_full</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_rldiii_user_wdfifo_full" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;RLDIII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_rldiii_user_wdfifo_aempty</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_rldiii_user_wdfifo_aempty" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;RLDIII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_rldiii_user_wdfifo_afull</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_rldiii_user_wdfifo_afull" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;RLDIII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_rldiii_user_rd_valid</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_RLDIII_nCK_PER_CLK&apos;)) )- 1 ">0</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_rldiii_user_rd_valid" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;RLDIII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_rldiii_mem_ck_lock_complete</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_rldiii_mem_ck_lock_complete" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;RLDIII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_rldiii_user_rd_data</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency=" ( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_RLDIII_DATA_WIDTH&apos;)) * 2 * spirit:decode(id(&apos;MODELPARAM_VALUE.C7_RLDIII_nCK_PER_CLK&apos;)) )- 1 ">35</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_rldiii_user_rd_data" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;RLDIII&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_USE_AXI&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.COMBINED_INTERFACE&apos;)) = 1 ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_sys_clk_p</spirit:name>
        <spirit:displayName>Clock P</spirit:displayName>
        <spirit:description>Clock P</spirit:description>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_sys_clk_p" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_SYSCLK_TYPE&apos;)) = &quot;DIFF&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_IS_CLK_SHARED&apos;)) = &quot;FALSE&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_sys_clk_n</spirit:name>
        <spirit:displayName>Clock P</spirit:displayName>
        <spirit:description>Clock P</spirit:description>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_sys_clk_n" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_SYSCLK_TYPE&apos;)) = &quot;DIFF&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_IS_CLK_SHARED&apos;)) = &quot;FALSE&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_sys_clk_i</spirit:name>
        <spirit:displayName>Clock P</spirit:displayName>
        <spirit:description>Clock P</spirit:description>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_sys_clk_i" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_SYSCLK_TYPE&apos;)) != &quot;DIFF&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.C7_IS_CLK_SHARED&apos;)) = &quot;FALSE&quot; ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_init_calib_complete</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_init_calib_complete" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
      <spirit:port>
        <spirit:name>c7_aresetn</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>wire</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
        <spirit:vendorExtensions>
          <xilinx:portInfo>
            <xilinx:enablement>
              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c7_aresetn" xilinx:dependency=" spirit:decode(id(&apos;MODELPARAM_VALUE.NoOfControllers&apos;)) > 7 and ( spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;DDR3&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.C7_MEM_TYPE&apos;)) = &quot;DDR2&quot; ) ">false</xilinx:isEnabled>
            </xilinx:enablement>
          </xilinx:portInfo>
        </spirit:vendorExtensions>
      </spirit:port>
    </spirit:ports>
    <spirit:modelParameters>
      <spirit:modelParameter xsi:type="spirit:nameValueTypeType" spirit:dataType="long">
        <spirit:name>NoOfControllers</spirit:name>
        <spirit:displayName>Number of controllers</spirit:displayName>
        <spirit:description>Number of controllers</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.NoOfControllers" spirit:configGroups="default" spirit:minimum="0" spirit:maximum="8" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>COMBINED_INTERFACE</spirit:name>
        <spirit:displayName>Indicates the controllers of same interface or same interface</spirit:displayName>
        <spirit:description>Indicates the controllers of same interface or same interface</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.COMBINED_INTERFACE" spirit:configGroups="default" spirit:minimum="0" spirit:maximum="1" spirit:rangeType="long">0</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="string">
        <spirit:name>REFCLK_TYPE</spirit:name>
        <spirit:displayName>Type of ref clk</spirit:displayName>
        <spirit:description>Type of ref clk</spirit:description>
        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.REFCLK_TYPE" spirit:choiceRef="choice_list_350ebf94" spirit:configGroups="default">NOBUF</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="string">
        <spirit:name>MEM_TYPE</spirit:name>
        <spirit:displayName>identify interface</spirit:displayName>
        <spirit:description>identify interface</spirit:description>
        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.MEM_TYPE" spirit:choiceRef="choice_list_b54243b1" spirit:configGroups="default">DDR3</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="string">
        <spirit:name>TEMP_MON_CONTROL</spirit:name>
        <spirit:displayName>identify interface</spirit:displayName>
        <spirit:description>identify interface</spirit:description>
        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.TEMP_MON_CONTROL" spirit:choiceRef="choice_list_e5b95726" spirit:configGroups="default">INTERNAL</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="string">
        <spirit:name>POLARITY</spirit:name>
        <spirit:displayName>Polarity of the value</spirit:displayName>
        <spirit:description>Polarity of the value</spirit:description>
        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.POLARITY" spirit:choiceRef="choice_list_6eff49bd" spirit:configGroups="default">ACTIVE_LOW</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="string">
        <spirit:name>IS_CLK_SHARED</spirit:name>
        <spirit:displayName>is clk shared</spirit:displayName>
        <spirit:description>is clk shared</spirit:description>
        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.IS_CLK_SHARED" spirit:choiceRef="choice_list_d10f4555" spirit:configGroups="default">FALSE</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="string">
        <spirit:name>SYSCLK_TYPE</spirit:name>
        <spirit:displayName>Type of sys clk</spirit:displayName>
        <spirit:description>Type of sys clk</spirit:description>
        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.SYSCLK_TYPE" spirit:choiceRef="choice_list_1570a756" spirit:configGroups="default">DIFF</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>USE_AXI</spirit:name>
        <spirit:displayName>USE AXI</spirit:displayName>
        <spirit:description>USE AXI</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.USE_AXI" spirit:configGroups="default" spirit:minimum="0" spirit:maximum="1" spirit:rangeType="long">0</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="string">
        <spirit:name>ECC</spirit:name>
        <spirit:displayName>ecc enable info</spirit:displayName>
        <spirit:description>ecc enable info</spirit:description>
        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.ECC" spirit:choiceRef="choice_list_dc86ec6e" spirit:configGroups="default">OFF</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>DDR3_DQ_WIDTH</spirit:name>
        <spirit:displayName>data bus width</spirit:displayName>
        <spirit:description>data bus width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.DDR3_DQ_WIDTH" spirit:choiceRef="choice_list_bdb560e1" spirit:configGroups="default">64</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>DDR3_DQS_WIDTH</spirit:name>
        <spirit:displayName>data strobe width</spirit:displayName>
        <spirit:description>data strobe width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.DDR3_DQS_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="9" spirit:rangeType="long">8</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>DDR3_ROW_WIDTH</spirit:name>
        <spirit:displayName>row width</spirit:displayName>
        <spirit:description>row width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.DDR3_ROW_WIDTH" spirit:configGroups="default" spirit:minimum="13" spirit:maximum="16" spirit:rangeType="long">14</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>DDR3_BANK_WIDTH</spirit:name>
        <spirit:displayName>bank width</spirit:displayName>
        <spirit:description>bank width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.DDR3_BANK_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="3" spirit:rangeType="long">3</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>DDR3_CK_WIDTH</spirit:name>
        <spirit:displayName>clock width</spirit:displayName>
        <spirit:description>clock width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.DDR3_CK_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="4" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>DDR3_CKE_WIDTH</spirit:name>
        <spirit:displayName>clock enable width</spirit:displayName>
        <spirit:description>clock enable width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.DDR3_CKE_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="2" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>DDR3_CS_WIDTH</spirit:name>
        <spirit:displayName>chip select width</spirit:displayName>
        <spirit:description>chip select width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.DDR3_CS_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="2" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>DDR3_nCS_PER_RANK</spirit:name>
        <spirit:displayName>chip select per rank</spirit:displayName>
        <spirit:description>chip select per rank</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.DDR3_nCS_PER_RANK" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="4" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>DDR3_DM_WIDTH</spirit:name>
        <spirit:displayName>data mask width</spirit:displayName>
        <spirit:description>data mask width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.DDR3_DM_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="9" spirit:rangeType="long">8</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>DDR3_ODT_WIDTH</spirit:name>
        <spirit:displayName>odt width</spirit:displayName>
        <spirit:description>odt width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.DDR3_ODT_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="4" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>DDR3_USE_CS_PORT</spirit:name>
        <spirit:displayName>CS Port is in use</spirit:displayName>
        <spirit:description>CS Port is in use</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.DDR3_USE_CS_PORT" spirit:configGroups="default" spirit:minimum="0" spirit:maximum="1" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>DDR3_USE_DM_PORT</spirit:name>
        <spirit:displayName>DM Port is in use</spirit:displayName>
        <spirit:description>DM Port is in use</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.DDR3_USE_DM_PORT" spirit:configGroups="default" spirit:minimum="0" spirit:maximum="1" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>DDR3_USE_ODT_PORT</spirit:name>
        <spirit:displayName>ODT Port is in use</spirit:displayName>
        <spirit:description>ODT Port is in use</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.DDR3_USE_ODT_PORT" spirit:configGroups="default" spirit:minimum="0" spirit:maximum="1" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="string">
        <spirit:name>DDR3_REG_CTRL</spirit:name>
        <spirit:displayName>Indicates Registered DIMM or not</spirit:displayName>
        <spirit:description>Indicates Registered DIMM or not</spirit:description>
        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.DDR3_REG_CTRL" spirit:choiceRef="choice_list_dc86ec6e" spirit:configGroups="default">OFF</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>DDR3_DQS_CNT_WIDTH</spirit:name>
        <spirit:displayName>DQS count width</spirit:displayName>
        <spirit:description>DQS count width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.DDR3_DQS_CNT_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="8" spirit:rangeType="long">3</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="string">
        <spirit:name>DDR3_DEBUG_PORT</spirit:name>
        <spirit:displayName>Debug Port enable info</spirit:displayName>
        <spirit:description>Debug Port enable info</spirit:description>
        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.DDR3_DEBUG_PORT" spirit:choiceRef="choice_list_dc86ec6e" spirit:configGroups="default">OFF</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>DDR2_DQ_WIDTH</spirit:name>
        <spirit:displayName>data bus width</spirit:displayName>
        <spirit:description>data bus width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.DDR2_DQ_WIDTH" spirit:choiceRef="choice_list_bdb560e1" spirit:configGroups="default">8</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>DDR2_DQS_WIDTH</spirit:name>
        <spirit:displayName>data strobe width</spirit:displayName>
        <spirit:description>data strobe width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.DDR2_DQS_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="9" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>DDR2_ROW_WIDTH</spirit:name>
        <spirit:displayName>row width</spirit:displayName>
        <spirit:description>row width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.DDR2_ROW_WIDTH" spirit:configGroups="default" spirit:minimum="13" spirit:maximum="16" spirit:rangeType="long">14</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>DDR2_BANK_WIDTH</spirit:name>
        <spirit:displayName>bank width</spirit:displayName>
        <spirit:description>bank width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.DDR2_BANK_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="3" spirit:rangeType="long">3</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>DDR2_CK_WIDTH</spirit:name>
        <spirit:displayName>clock width</spirit:displayName>
        <spirit:description>clock width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.DDR2_CK_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="4" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>DDR2_CKE_WIDTH</spirit:name>
        <spirit:displayName>clock enable width</spirit:displayName>
        <spirit:description>clock enable width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.DDR2_CKE_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="2" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>DDR2_CS_WIDTH</spirit:name>
        <spirit:displayName>chip select width</spirit:displayName>
        <spirit:description>chip select width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.DDR2_CS_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="2" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>DDR2_nCS_PER_RANK</spirit:name>
        <spirit:displayName>chip select per rank</spirit:displayName>
        <spirit:description>chip select per rank</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.DDR2_nCS_PER_RANK" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="4" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>DDR2_DM_WIDTH</spirit:name>
        <spirit:displayName>data mask width</spirit:displayName>
        <spirit:description>data mask width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.DDR2_DM_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="9" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>DDR2_ODT_WIDTH</spirit:name>
        <spirit:displayName>odt width</spirit:displayName>
        <spirit:description>odt width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.DDR2_ODT_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="4" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>DDR2_USE_CS_PORT</spirit:name>
        <spirit:displayName>CS Port is in use</spirit:displayName>
        <spirit:description>CS Port is in use</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.DDR2_USE_CS_PORT" spirit:configGroups="default" spirit:minimum="0" spirit:maximum="1" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>DDR2_USE_DM_PORT</spirit:name>
        <spirit:displayName>DM Port is in use</spirit:displayName>
        <spirit:description>DM Port is in use</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.DDR2_USE_DM_PORT" spirit:configGroups="default" spirit:minimum="0" spirit:maximum="1" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>DDR2_USE_ODT_PORT</spirit:name>
        <spirit:displayName>ODT Port is in use</spirit:displayName>
        <spirit:description>ODT Port is in use</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.DDR2_USE_ODT_PORT" spirit:configGroups="default" spirit:minimum="0" spirit:maximum="1" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="string">
        <spirit:name>DDR2_REG_CTRL</spirit:name>
        <spirit:displayName>Indicates Registered DIMM or not</spirit:displayName>
        <spirit:description>Indicates Registered DIMM or not</spirit:description>
        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.DDR2_REG_CTRL" spirit:choiceRef="choice_list_dc86ec6e" spirit:configGroups="default">OFF</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>DDR2_DQS_CNT_WIDTH</spirit:name>
        <spirit:displayName>DQS count width</spirit:displayName>
        <spirit:description>DQS count width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.DDR2_DQS_CNT_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="8" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="string">
        <spirit:name>DDR2_DEBUG_PORT</spirit:name>
        <spirit:displayName>Debug Port enable info</spirit:displayName>
        <spirit:description>Debug Port enable info</spirit:description>
        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.DDR2_DEBUG_PORT" spirit:choiceRef="choice_list_dc86ec6e" spirit:configGroups="default">OFF</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>LPDDR2_DQ_WIDTH</spirit:name>
        <spirit:displayName>data bus width</spirit:displayName>
        <spirit:description>data bus width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.LPDDR2_DQ_WIDTH" spirit:choiceRef="choice_list_bdb560e1" spirit:configGroups="default">8</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>LPDDR2_DQS_WIDTH</spirit:name>
        <spirit:displayName>data strobe width</spirit:displayName>
        <spirit:description>data strobe width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.LPDDR2_DQS_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="9" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>LPDDR2_ROW_WIDTH</spirit:name>
        <spirit:displayName>row width</spirit:displayName>
        <spirit:description>row width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.LPDDR2_ROW_WIDTH" spirit:configGroups="default" spirit:minimum="12" spirit:maximum="16" spirit:rangeType="long">14</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>LPDDR2_BANK_WIDTH</spirit:name>
        <spirit:displayName>bank width</spirit:displayName>
        <spirit:description>bank width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.LPDDR2_BANK_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="3" spirit:rangeType="long">3</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>LPDDR2_CK_WIDTH</spirit:name>
        <spirit:displayName>clock width</spirit:displayName>
        <spirit:description>clock width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.LPDDR2_CK_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="4" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>LPDDR2_CKE_WIDTH</spirit:name>
        <spirit:displayName>clock enable width</spirit:displayName>
        <spirit:description>clock enable width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.LPDDR2_CKE_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="2" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>LPDDR2_CS_WIDTH</spirit:name>
        <spirit:displayName>chip select width</spirit:displayName>
        <spirit:description>chip select width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.LPDDR2_CS_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="2" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>LPDDR2_nCS_PER_RANK</spirit:name>
        <spirit:displayName>chip select per rank</spirit:displayName>
        <spirit:description>chip select per rank</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.LPDDR2_nCS_PER_RANK" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="4" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>LPDDR2_DM_WIDTH</spirit:name>
        <spirit:displayName>data mask width</spirit:displayName>
        <spirit:description>data mask width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.LPDDR2_DM_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="9" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>LPDDR2_USE_CS_PORT</spirit:name>
        <spirit:displayName>CS Port is in use</spirit:displayName>
        <spirit:description>CS Port is in use</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.LPDDR2_USE_CS_PORT" spirit:configGroups="default" spirit:minimum="0" spirit:maximum="1" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>LPDDR2_USE_DM_PORT</spirit:name>
        <spirit:displayName>DM Port is in use</spirit:displayName>
        <spirit:description>DM Port is in use</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.LPDDR2_USE_DM_PORT" spirit:configGroups="default" spirit:minimum="0" spirit:maximum="1" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>LPDDR2_USE_ODT_PORT</spirit:name>
        <spirit:displayName>ODT Port is in use</spirit:displayName>
        <spirit:description>ODT Port is in use</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.LPDDR2_USE_ODT_PORT" spirit:configGroups="default" spirit:minimum="0" spirit:maximum="1" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="string">
        <spirit:name>LPDDR2_REG_CTRL</spirit:name>
        <spirit:displayName>Indicates Registered DIMM or not</spirit:displayName>
        <spirit:description>Indicates Registered DIMM or not</spirit:description>
        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.LPDDR2_REG_CTRL" spirit:choiceRef="choice_list_dc86ec6e" spirit:configGroups="default">OFF</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>LPDDR2_DQS_CNT_WIDTH</spirit:name>
        <spirit:displayName>DQS count width</spirit:displayName>
        <spirit:description>DQS count width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.LPDDR2_DQS_CNT_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="8" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="string">
        <spirit:name>LPDDR2_DEBUG_PORT</spirit:name>
        <spirit:displayName>Debug Port enable info</spirit:displayName>
        <spirit:description>Debug Port enable info</spirit:description>
        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.LPDDR2_DEBUG_PORT" spirit:choiceRef="choice_list_dc86ec6e" spirit:configGroups="default">OFF</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>DQS_CNT_WIDTH</spirit:name>
        <spirit:displayName>DQS count width</spirit:displayName>
        <spirit:description>DQS count width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.DQS_CNT_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="8" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="string">
        <spirit:name>DEBUG_PORT</spirit:name>
        <spirit:displayName>Debug Port enable info</spirit:displayName>
        <spirit:description>Debug Port enable info</spirit:description>
        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.DEBUG_PORT" spirit:choiceRef="choice_list_dc86ec6e" spirit:configGroups="default">OFF</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>DDRX_ADDR_WIDTH</spirit:name>
        <spirit:displayName>addr width</spirit:displayName>
        <spirit:description>addr width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.DDRX_ADDR_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="32" spirit:rangeType="long">8</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>DDRX_nCK_PER_CLK</spirit:name>
        <spirit:displayName>nck per clk</spirit:displayName>
        <spirit:description>nck per clk</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.DDRX_nCK_PER_CLK" spirit:configGroups="default" spirit:minimum="0" spirit:maximum="4" spirit:rangeType="long">2</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>DDRX_DATA_WIDTH</spirit:name>
        <spirit:displayName>datawidth excluding the ECC</spirit:displayName>
        <spirit:description>datawidth excluding the ECC</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.DDRX_DATA_WIDTH" spirit:configGroups="default" spirit:minimum="8" spirit:maximum="72" spirit:rangeType="long">8</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>DDR3_ADDR_WIDTH</spirit:name>
        <spirit:displayName>addr width</spirit:displayName>
        <spirit:description>addr width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.DDR3_ADDR_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="32" spirit:rangeType="long">28</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>DDR3_nCK_PER_CLK</spirit:name>
        <spirit:displayName>nck per clk</spirit:displayName>
        <spirit:description>nck per clk</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.DDR3_nCK_PER_CLK" spirit:configGroups="default" spirit:minimum="0" spirit:maximum="4" spirit:rangeType="long">4</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>DDR3_DATA_WIDTH</spirit:name>
        <spirit:displayName>datawidth excluding the ECC</spirit:displayName>
        <spirit:description>datawidth excluding the ECC</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.DDR3_DATA_WIDTH" spirit:configGroups="default" spirit:minimum="8" spirit:maximum="72" spirit:rangeType="long">64</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>DDR2_ADDR_WIDTH</spirit:name>
        <spirit:displayName>addr width</spirit:displayName>
        <spirit:description>addr width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.DDR2_ADDR_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="32" spirit:rangeType="long">8</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>DDR2_nCK_PER_CLK</spirit:name>
        <spirit:displayName>nck per clk</spirit:displayName>
        <spirit:description>nck per clk</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.DDR2_nCK_PER_CLK" spirit:configGroups="default" spirit:minimum="0" spirit:maximum="4" spirit:rangeType="long">2</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>DDR2_DATA_WIDTH</spirit:name>
        <spirit:displayName>datawidth excluding the ECC</spirit:displayName>
        <spirit:description>datawidth excluding the ECC</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.DDR2_DATA_WIDTH" spirit:configGroups="default" spirit:minimum="8" spirit:maximum="72" spirit:rangeType="long">8</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>LPDDR2_ADDR_WIDTH</spirit:name>
        <spirit:displayName>addr width</spirit:displayName>
        <spirit:description>addr width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.LPDDR2_ADDR_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="32" spirit:rangeType="long">8</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>LPDDR2_nCK_PER_CLK</spirit:name>
        <spirit:displayName>nck per clk</spirit:displayName>
        <spirit:description>nck per clk</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.LPDDR2_nCK_PER_CLK" spirit:configGroups="default" spirit:minimum="0" spirit:maximum="4" spirit:rangeType="long">2</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>LPDDR2_DATA_WIDTH</spirit:name>
        <spirit:displayName>datawidth excluding the ECC</spirit:displayName>
        <spirit:description>datawidth excluding the ECC</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.LPDDR2_DATA_WIDTH" spirit:configGroups="default" spirit:minimum="8" spirit:maximum="72" spirit:rangeType="long">8</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="float">
        <spirit:name>FREQ_HZ</spirit:name>
        <spirit:displayName>defines the UI Clk freq</spirit:displayName>
        <spirit:description>defines the UI Clk freq</spirit:description>
        <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.FREQ_HZ" spirit:configGroups="default" spirit:minimum="0.0" spirit:maximum="800000000.0" spirit:rangeType="long">100000000</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="float">
        <spirit:name>PHASE</spirit:name>
        <spirit:displayName>defines the UI Clk phase</spirit:displayName>
        <spirit:description>defines the UI Clk phase</spirit:description>
        <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PHASE" spirit:choiceRef="choice_list_c7c132f6" spirit:configGroups="default">0.000</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="string">
        <spirit:name>UI_EXTRA_CLOCKS</spirit:name>
        <spirit:displayName>Enablement of extra clocks</spirit:displayName>
        <spirit:description>Enablement of extra clocks</spirit:description>
        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.UI_EXTRA_CLOCKS" spirit:choiceRef="choice_list_d10f4555" spirit:configGroups="default">FALSE</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="float">
        <spirit:name>MMCM_VCO</spirit:name>
        <spirit:displayName>Max possible VCO of MMCM primitive </spirit:displayName>
        <spirit:description>Max possible VCO of MMCM primitive </spirit:description>
        <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.MMCM_VCO" spirit:configGroups="default" spirit:minimum="600.0" spirit:maximum="1600.0" spirit:rangeType="long">800</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="float">
        <spirit:name>MMCM_CLKOUT0_FREQ</spirit:name>
        <spirit:displayName>mmcm extra clkout0</spirit:displayName>
        <spirit:description>mmcm extra clkout0</spirit:description>
        <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.MMCM_CLKOUT0_FREQ" spirit:configGroups="default" spirit:minimum="0.0" spirit:maximum="800000000.0" spirit:rangeType="long">10.0</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>MMCM_CLKOUT1_FREQ</spirit:name>
        <spirit:displayName>mmcm extra clkout1</spirit:displayName>
        <spirit:description>mmcm extra clkout1</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.MMCM_CLKOUT1_FREQ" spirit:configGroups="default" spirit:minimum="0.0" spirit:maximum="800000000" spirit:rangeType="long">10</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>MMCM_CLKOUT2_FREQ</spirit:name>
        <spirit:displayName>mmcm extra clkout2</spirit:displayName>
        <spirit:description>mmcm extra clkout2</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.MMCM_CLKOUT2_FREQ" spirit:configGroups="default" spirit:minimum="0.0" spirit:maximum="800000000" spirit:rangeType="long">10</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>MMCM_CLKOUT3_FREQ</spirit:name>
        <spirit:displayName>mmcm extra clkout3</spirit:displayName>
        <spirit:description>mmcm extra clkout3</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.MMCM_CLKOUT3_FREQ" spirit:configGroups="default" spirit:minimum="0.0" spirit:maximum="800000000" spirit:rangeType="long">10</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>MMCM_CLKOUT4_FREQ</spirit:name>
        <spirit:displayName>mmcm extra clkout4</spirit:displayName>
        <spirit:description>mmcm extra clkout4</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.MMCM_CLKOUT4_FREQ" spirit:configGroups="default" spirit:minimum="0.0" spirit:maximum="800000000" spirit:rangeType="long">10</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="string">
        <spirit:name>MMCM_CLKOUT0_EN</spirit:name>
        <spirit:displayName>Indicates Enablement of CLKOUT0</spirit:displayName>
        <spirit:description>Indicates Enablement of CLKOUT0</spirit:description>
        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.MMCM_CLKOUT0_EN" spirit:choiceRef="choice_list_e7c484ae" spirit:configGroups="default">FALSE</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="string">
        <spirit:name>MMCM_CLKOUT2_EN</spirit:name>
        <spirit:displayName>Indicates Enablement of CLKOUT2</spirit:displayName>
        <spirit:description>Indicates Enablement of CLKOUT2</spirit:description>
        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.MMCM_CLKOUT2_EN" spirit:choiceRef="choice_list_e7c484ae" spirit:configGroups="default">FALSE</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="string">
        <spirit:name>MMCM_CLKOUT1_EN</spirit:name>
        <spirit:displayName>Indicates Enablement of CLKOUT1</spirit:displayName>
        <spirit:description>Indicates Enablement of CLKOUT1</spirit:description>
        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.MMCM_CLKOUT1_EN" spirit:choiceRef="choice_list_e7c484ae" spirit:configGroups="default">FALSE</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="string">
        <spirit:name>MMCM_CLKOUT3_EN</spirit:name>
        <spirit:displayName>Indicates Enablement of CLKOUT3</spirit:displayName>
        <spirit:description>Indicates Enablement of CLKOUT3</spirit:description>
        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.MMCM_CLKOUT3_EN" spirit:choiceRef="choice_list_e7c484ae" spirit:configGroups="default">FALSE</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="string">
        <spirit:name>MMCM_CLKOUT4_EN</spirit:name>
        <spirit:displayName>Indicates Enablement of CLKOUT4</spirit:displayName>
        <spirit:description>Indicates Enablement of CLKOUT4</spirit:description>
        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.MMCM_CLKOUT4_EN" spirit:choiceRef="choice_list_e7c484ae" spirit:configGroups="default">FALSE</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C_S_AXI_CTRL_ID_WIDTH</spirit:name>
        <spirit:displayName>AXI ID Width</spirit:displayName>
        <spirit:description>AXI ID Width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_S_AXI_CTRL_ID_WIDTH" spirit:configGroups="default" spirit:minimum="0" spirit:maximum="16" spirit:rangeType="long">4</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C_S_AXI_CTRL_DATA_WIDTH</spirit:name>
        <spirit:displayName>AXI Data Width</spirit:displayName>
        <spirit:description>AXI Data Width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_S_AXI_CTRL_DATA_WIDTH" spirit:choiceRef="choice_list_40181835" spirit:configGroups="default">32</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C_S_AXI_CTRL_ADDR_WIDTH</spirit:name>
        <spirit:displayName>AXI Addr Width</spirit:displayName>
        <spirit:description>AXI Addr Width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_S_AXI_CTRL_ADDR_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="36" spirit:rangeType="long">32</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C_S_AXI_CTRL_MEM_SIZE</spirit:name>
        <spirit:displayName>Memory Address Space</spirit:displayName>
        <spirit:description>Memory Address Space</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_S_AXI_CTRL_MEM_SIZE" spirit:configGroups="default" spirit:minimum="0" spirit:maximum="34359738368" spirit:rangeType="long">1048576</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C_S_AXI_ID_WIDTH</spirit:name>
        <spirit:displayName>AXI ID Width</spirit:displayName>
        <spirit:description>AXI ID Width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_S_AXI_ID_WIDTH" spirit:configGroups="default" spirit:minimum="0" spirit:maximum="16" spirit:rangeType="long">4</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C_S_AXI_DATA_WIDTH</spirit:name>
        <spirit:displayName>AXI Data Width</spirit:displayName>
        <spirit:description>AXI Data Width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_S_AXI_DATA_WIDTH" spirit:choiceRef="choice_list_40181835" spirit:configGroups="default">32</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C_S_AXI_ADDR_WIDTH</spirit:name>
        <spirit:displayName>AXI Addr Width</spirit:displayName>
        <spirit:description>AXI Addr Width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_S_AXI_ADDR_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="36" spirit:rangeType="long">32</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C_S_AXI_MEM_SIZE</spirit:name>
        <spirit:displayName>Memory Address Space</spirit:displayName>
        <spirit:description>Memory Address Space</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_S_AXI_MEM_SIZE" spirit:configGroups="default" spirit:minimum="0" spirit:maximum="34359738368" spirit:rangeType="long">1048576</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>QDRIIP_NUM_DEVICES</spirit:name>
        <spirit:displayName>num devices</spirit:displayName>
        <spirit:description>num devices</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.QDRIIP_NUM_DEVICES" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="4" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>QDRIIP_DATA_WIDTH</spirit:name>
        <spirit:displayName>data width</spirit:displayName>
        <spirit:description>data width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.QDRIIP_DATA_WIDTH" spirit:choiceRef="choice_list_cf6acb30" spirit:configGroups="default">18</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>QDRIIP_ADDR_WIDTH</spirit:name>
        <spirit:displayName>addr width </spirit:displayName>
        <spirit:description>addr width </spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.QDRIIP_ADDR_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="32" spirit:rangeType="long">29</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>QDRIIP_BW_WIDTH</spirit:name>
        <spirit:displayName>bw width </spirit:displayName>
        <spirit:description>bw width </spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.QDRIIP_BW_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="8" spirit:rangeType="long">8</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="string">
        <spirit:name>QDRIIP_DEBUG_PORT</spirit:name>
        <spirit:displayName>Debug Port enable info</spirit:displayName>
        <spirit:description>Debug Port enable info</spirit:description>
        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.QDRIIP_DEBUG_PORT" spirit:choiceRef="choice_list_dc86ec6e" spirit:configGroups="default">OFF</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>QDRIIP_BURST_LEN</spirit:name>
        <spirit:displayName>burst len </spirit:displayName>
        <spirit:description>burst len </spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.QDRIIP_BURST_LEN" spirit:choiceRef="choice_list_dd2843c6" spirit:configGroups="default">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>RLDII_NUM_DEVICES</spirit:name>
        <spirit:displayName>num devices</spirit:displayName>
        <spirit:description>num devices</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.RLDII_NUM_DEVICES" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="4" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>RLDII_DATA_WIDTH</spirit:name>
        <spirit:displayName>data width</spirit:displayName>
        <spirit:description>data width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.RLDII_DATA_WIDTH" spirit:choiceRef="choice_list_cf6acb30" spirit:configGroups="default">18</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>RLDII_RLD_ADDR_WIDTH</spirit:name>
        <spirit:displayName>rld addr width </spirit:displayName>
        <spirit:description>rld addr width </spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.RLDII_RLD_ADDR_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="32" spirit:rangeType="long">29</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>RLDII_QK_WIDTH</spirit:name>
        <spirit:displayName>qk width </spirit:displayName>
        <spirit:description>qk width </spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.RLDII_QK_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="8" spirit:rangeType="long">8</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>RLDII_CK_WIDTH</spirit:name>
        <spirit:displayName>ck width </spirit:displayName>
        <spirit:description>ck width </spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.RLDII_CK_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="4" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>RLDII_DK_WIDTH</spirit:name>
        <spirit:displayName>dk width </spirit:displayName>
        <spirit:description>dk width </spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.RLDII_DK_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="4" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>RLDII_DM_WIDTH</spirit:name>
        <spirit:displayName>dm width </spirit:displayName>
        <spirit:description>dm width </spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.RLDII_DM_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="4" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>RLDII_BANK_WIDTH</spirit:name>
        <spirit:displayName>bank width </spirit:displayName>
        <spirit:description>bank width </spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.RLDII_BANK_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="4" spirit:rangeType="long">2</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>RLDII_QVLD_WIDTH</spirit:name>
        <spirit:displayName>qvld width </spirit:displayName>
        <spirit:description>qvld width </spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.RLDII_QVLD_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="4" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="string">
        <spirit:name>RLDII_DEBUG_PORT</spirit:name>
        <spirit:displayName>Debug Port enable info</spirit:displayName>
        <spirit:description>Debug Port enable info</spirit:description>
        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.RLDII_DEBUG_PORT" spirit:choiceRef="choice_list_dc86ec6e" spirit:configGroups="default">OFF</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>RLDIII_NUM_DEVICES</spirit:name>
        <spirit:displayName>num devices</spirit:displayName>
        <spirit:description>num devices</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.RLDIII_NUM_DEVICES" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="4" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>RLDIII_DATA_WIDTH</spirit:name>
        <spirit:displayName>data width</spirit:displayName>
        <spirit:description>data width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.RLDIII_DATA_WIDTH" spirit:choiceRef="choice_list_cf6acb30" spirit:configGroups="default">18</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>RLDIII_RLD_ADDR_WIDTH</spirit:name>
        <spirit:displayName>rld addr width </spirit:displayName>
        <spirit:description>rld addr width </spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.RLDIII_RLD_ADDR_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="32" spirit:rangeType="long">29</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>RLDIII_QK_WIDTH</spirit:name>
        <spirit:displayName>qk width </spirit:displayName>
        <spirit:description>qk width </spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.RLDIII_QK_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="8" spirit:rangeType="long">8</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>RLDIII_CK_WIDTH</spirit:name>
        <spirit:displayName>ck width </spirit:displayName>
        <spirit:description>ck width </spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.RLDIII_CK_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="4" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>RLDIII_DK_WIDTH</spirit:name>
        <spirit:displayName>dk width </spirit:displayName>
        <spirit:description>dk width </spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.RLDIII_DK_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="4" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>RLDIII_DM_WIDTH</spirit:name>
        <spirit:displayName>dm width </spirit:displayName>
        <spirit:description>dm width </spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.RLDIII_DM_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="4" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>RLDIII_BANK_WIDTH</spirit:name>
        <spirit:displayName>bank width </spirit:displayName>
        <spirit:description>bank width </spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.RLDIII_BANK_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="4" spirit:rangeType="long">2</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>RLDIII_QVLD_WIDTH</spirit:name>
        <spirit:displayName>qvld width </spirit:displayName>
        <spirit:description>qvld width </spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.RLDIII_QVLD_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="4" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="string">
        <spirit:name>RLDIII_DEBUG_PORT</spirit:name>
        <spirit:displayName>Debug Port enable info</spirit:displayName>
        <spirit:description>Debug Port enable info</spirit:description>
        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.RLDIII_DEBUG_PORT" spirit:choiceRef="choice_list_dc86ec6e" spirit:configGroups="default">OFF</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>RLDX_CMD_PER_CLK</spirit:name>
        <spirit:displayName>cmd per clock</spirit:displayName>
        <spirit:description>cmd per clock</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.RLDX_CMD_PER_CLK" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="4" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>RLDX_DATA_WIDTH</spirit:name>
        <spirit:displayName>data width</spirit:displayName>
        <spirit:description>data width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.RLDX_DATA_WIDTH" spirit:choiceRef="choice_list_cf6acb30" spirit:configGroups="default">18</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>RLDX_ADDR_WIDTH</spirit:name>
        <spirit:displayName>addr width </spirit:displayName>
        <spirit:description>addr width </spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.RLDX_ADDR_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="32" spirit:rangeType="long">29</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>RLDX_BANK_WIDTH</spirit:name>
        <spirit:displayName>bank width </spirit:displayName>
        <spirit:description>bank width </spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.RLDX_BANK_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="4" spirit:rangeType="long">2</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>RLDX_nCK_PER_CLK</spirit:name>
        <spirit:displayName>nCk per clock</spirit:displayName>
        <spirit:description>nCk per clock</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.RLDX_nCK_PER_CLK" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="4" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>RLDX_DM_WIDTH</spirit:name>
        <spirit:displayName>dm width </spirit:displayName>
        <spirit:description>dm width </spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.RLDX_DM_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="4" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>RLDII_CMD_PER_CLK</spirit:name>
        <spirit:displayName>cmd per clock</spirit:displayName>
        <spirit:description>cmd per clock</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.RLDII_CMD_PER_CLK" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="4" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>RLDII_ADDR_WIDTH</spirit:name>
        <spirit:displayName>addr width </spirit:displayName>
        <spirit:description>addr width </spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.RLDII_ADDR_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="32" spirit:rangeType="long">29</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>RLDII_nCK_PER_CLK</spirit:name>
        <spirit:displayName>nCk per clock</spirit:displayName>
        <spirit:description>nCk per clock</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.RLDII_nCK_PER_CLK" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="4" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>RLDIII_CMD_PER_CLK</spirit:name>
        <spirit:displayName>cmd per clock</spirit:displayName>
        <spirit:description>cmd per clock</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.RLDIII_CMD_PER_CLK" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="4" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>RLDIII_ADDR_WIDTH</spirit:name>
        <spirit:displayName>addr width </spirit:displayName>
        <spirit:description>addr width </spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.RLDIII_ADDR_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="32" spirit:rangeType="long">29</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>RLDIII_nCK_PER_CLK</spirit:name>
        <spirit:displayName>nCk per clock</spirit:displayName>
        <spirit:description>nCk per clock</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.RLDIII_nCK_PER_CLK" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="4" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="string">
        <spirit:name>C0_MEM_TYPE</spirit:name>
        <spirit:displayName>identify interface</spirit:displayName>
        <spirit:description>identify interface</spirit:description>
        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0_MEM_TYPE" spirit:choiceRef="choice_list_b54243b1" spirit:configGroups="default">DDR3</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="string">
        <spirit:name>C0_IS_CLK_SHARED</spirit:name>
        <spirit:displayName>is clk shared</spirit:displayName>
        <spirit:description>is clk shared</spirit:description>
        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0_IS_CLK_SHARED" spirit:choiceRef="choice_list_d10f4555" spirit:configGroups="default">FALSE</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="string">
        <spirit:name>C0_SYSCLK_TYPE</spirit:name>
        <spirit:displayName>Type of sys clk</spirit:displayName>
        <spirit:description>Type of sys clk</spirit:description>
        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0_SYSCLK_TYPE" spirit:choiceRef="choice_list_1570a756" spirit:configGroups="default">DIFF</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C0_USE_AXI</spirit:name>
        <spirit:displayName>USE AXI</spirit:displayName>
        <spirit:description>USE AXI</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0_USE_AXI" spirit:configGroups="default" spirit:minimum="0" spirit:maximum="1" spirit:rangeType="long">0</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="string">
        <spirit:name>C0_ECC</spirit:name>
        <spirit:displayName>ecc enable info</spirit:displayName>
        <spirit:description>ecc enable info</spirit:description>
        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0_ECC" spirit:choiceRef="choice_list_dc86ec6e" spirit:configGroups="default">OFF</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C0_DDR3_DQ_WIDTH</spirit:name>
        <spirit:displayName>data bus width</spirit:displayName>
        <spirit:description>data bus width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0_DDR3_DQ_WIDTH" spirit:choiceRef="choice_list_bdb560e1" spirit:configGroups="default">8</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C0_DDR3_DQS_WIDTH</spirit:name>
        <spirit:displayName>data strobe width</spirit:displayName>
        <spirit:description>data strobe width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0_DDR3_DQS_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="9" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C0_DDR3_ROW_WIDTH</spirit:name>
        <spirit:displayName>row width</spirit:displayName>
        <spirit:description>row width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0_DDR3_ROW_WIDTH" spirit:configGroups="default" spirit:minimum="13" spirit:maximum="16" spirit:rangeType="long">14</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C0_DDR3_BANK_WIDTH</spirit:name>
        <spirit:displayName>bank width</spirit:displayName>
        <spirit:description>bank width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0_DDR3_BANK_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="3" spirit:rangeType="long">3</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C0_DDR3_CK_WIDTH</spirit:name>
        <spirit:displayName>clock width</spirit:displayName>
        <spirit:description>clock width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0_DDR3_CK_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="4" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C0_DDR3_CKE_WIDTH</spirit:name>
        <spirit:displayName>clock enable width</spirit:displayName>
        <spirit:description>clock enable width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0_DDR3_CKE_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="2" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C0_DDR3_CS_WIDTH</spirit:name>
        <spirit:displayName>chip select width</spirit:displayName>
        <spirit:description>chip select width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0_DDR3_CS_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="2" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C0_DDR3_nCS_PER_RANK</spirit:name>
        <spirit:displayName>chip select per rank</spirit:displayName>
        <spirit:description>chip select per rank</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0_DDR3_nCS_PER_RANK" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="4" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C0_DDR3_DM_WIDTH</spirit:name>
        <spirit:displayName>data mask width</spirit:displayName>
        <spirit:description>data mask width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0_DDR3_DM_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="9" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C0_DDR3_ODT_WIDTH</spirit:name>
        <spirit:displayName>odt width</spirit:displayName>
        <spirit:description>odt width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0_DDR3_ODT_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="4" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C0_DDR3_USE_CS_PORT</spirit:name>
        <spirit:displayName>CS Port is in use</spirit:displayName>
        <spirit:description>CS Port is in use</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0_DDR3_USE_CS_PORT" spirit:configGroups="default" spirit:minimum="0" spirit:maximum="1" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C0_DDR3_USE_DM_PORT</spirit:name>
        <spirit:displayName>DM Port is in use</spirit:displayName>
        <spirit:description>DM Port is in use</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0_DDR3_USE_DM_PORT" spirit:configGroups="default" spirit:minimum="0" spirit:maximum="1" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C0_DDR3_USE_ODT_PORT</spirit:name>
        <spirit:displayName>ODT Port is in use</spirit:displayName>
        <spirit:description>ODT Port is in use</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0_DDR3_USE_ODT_PORT" spirit:configGroups="default" spirit:minimum="0" spirit:maximum="1" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="string">
        <spirit:name>C0_DDR3_REG_CTRL</spirit:name>
        <spirit:displayName>Indicates Registered DIMM or not</spirit:displayName>
        <spirit:description>Indicates Registered DIMM or not</spirit:description>
        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0_DDR3_REG_CTRL" spirit:choiceRef="choice_list_dc86ec6e" spirit:configGroups="default">OFF</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C0_DDR3_DQS_CNT_WIDTH</spirit:name>
        <spirit:displayName>DQS count width</spirit:displayName>
        <spirit:description>DQS count width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0_DDR3_DQS_CNT_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="8" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="string">
        <spirit:name>C0_DDR3_DEBUG_PORT</spirit:name>
        <spirit:displayName>Debug Port enable info</spirit:displayName>
        <spirit:description>Debug Port enable info</spirit:description>
        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0_DDR3_DEBUG_PORT" spirit:choiceRef="choice_list_dc86ec6e" spirit:configGroups="default">OFF</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C0_DDR2_DQ_WIDTH</spirit:name>
        <spirit:displayName>data bus width</spirit:displayName>
        <spirit:description>data bus width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0_DDR2_DQ_WIDTH" spirit:choiceRef="choice_list_bdb560e1" spirit:configGroups="default">8</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C0_DDR2_DQS_WIDTH</spirit:name>
        <spirit:displayName>data strobe width</spirit:displayName>
        <spirit:description>data strobe width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0_DDR2_DQS_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="9" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C0_DDR2_ROW_WIDTH</spirit:name>
        <spirit:displayName>row width</spirit:displayName>
        <spirit:description>row width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0_DDR2_ROW_WIDTH" spirit:configGroups="default" spirit:minimum="13" spirit:maximum="16" spirit:rangeType="long">14</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C0_DDR2_BANK_WIDTH</spirit:name>
        <spirit:displayName>bank width</spirit:displayName>
        <spirit:description>bank width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0_DDR2_BANK_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="3" spirit:rangeType="long">3</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C0_DDR2_CK_WIDTH</spirit:name>
        <spirit:displayName>clock width</spirit:displayName>
        <spirit:description>clock width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0_DDR2_CK_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="4" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C0_DDR2_CKE_WIDTH</spirit:name>
        <spirit:displayName>clock enable width</spirit:displayName>
        <spirit:description>clock enable width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0_DDR2_CKE_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="2" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C0_DDR2_CS_WIDTH</spirit:name>
        <spirit:displayName>chip select width</spirit:displayName>
        <spirit:description>chip select width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0_DDR2_CS_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="2" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C0_DDR2_nCS_PER_RANK</spirit:name>
        <spirit:displayName>chip select per rank</spirit:displayName>
        <spirit:description>chip select per rank</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0_DDR2_nCS_PER_RANK" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="4" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C0_DDR2_DM_WIDTH</spirit:name>
        <spirit:displayName>data mask width</spirit:displayName>
        <spirit:description>data mask width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0_DDR2_DM_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="9" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C0_DDR2_ODT_WIDTH</spirit:name>
        <spirit:displayName>odt width</spirit:displayName>
        <spirit:description>odt width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0_DDR2_ODT_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="4" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C0_DDR2_USE_CS_PORT</spirit:name>
        <spirit:displayName>CS Port is in use</spirit:displayName>
        <spirit:description>CS Port is in use</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0_DDR2_USE_CS_PORT" spirit:configGroups="default" spirit:minimum="0" spirit:maximum="1" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C0_DDR2_USE_DM_PORT</spirit:name>
        <spirit:displayName>DM Port is in use</spirit:displayName>
        <spirit:description>DM Port is in use</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0_DDR2_USE_DM_PORT" spirit:configGroups="default" spirit:minimum="0" spirit:maximum="1" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C0_DDR2_USE_ODT_PORT</spirit:name>
        <spirit:displayName>ODT Port is in use</spirit:displayName>
        <spirit:description>ODT Port is in use</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0_DDR2_USE_ODT_PORT" spirit:configGroups="default" spirit:minimum="0" spirit:maximum="1" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="string">
        <spirit:name>C0_DDR2_REG_CTRL</spirit:name>
        <spirit:displayName>Indicates Registered DIMM or not</spirit:displayName>
        <spirit:description>Indicates Registered DIMM or not</spirit:description>
        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0_DDR2_REG_CTRL" spirit:choiceRef="choice_list_dc86ec6e" spirit:configGroups="default">OFF</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C0_DDR2_DQS_CNT_WIDTH</spirit:name>
        <spirit:displayName>DQS count width</spirit:displayName>
        <spirit:description>DQS count width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0_DDR2_DQS_CNT_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="8" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="string">
        <spirit:name>C0_DDR2_DEBUG_PORT</spirit:name>
        <spirit:displayName>Debug Port enable info</spirit:displayName>
        <spirit:description>Debug Port enable info</spirit:description>
        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0_DDR2_DEBUG_PORT" spirit:choiceRef="choice_list_dc86ec6e" spirit:configGroups="default">OFF</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C0_LPDDR2_DQ_WIDTH</spirit:name>
        <spirit:displayName>data bus width</spirit:displayName>
        <spirit:description>data bus width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0_LPDDR2_DQ_WIDTH" spirit:choiceRef="choice_list_bdb560e1" spirit:configGroups="default">8</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C0_LPDDR2_DQS_WIDTH</spirit:name>
        <spirit:displayName>data strobe width</spirit:displayName>
        <spirit:description>data strobe width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0_LPDDR2_DQS_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="9" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C0_LPDDR2_ROW_WIDTH</spirit:name>
        <spirit:displayName>row width</spirit:displayName>
        <spirit:description>row width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0_LPDDR2_ROW_WIDTH" spirit:configGroups="default" spirit:minimum="12" spirit:maximum="16" spirit:rangeType="long">14</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C0_LPDDR2_BANK_WIDTH</spirit:name>
        <spirit:displayName>bank width</spirit:displayName>
        <spirit:description>bank width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0_LPDDR2_BANK_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="3" spirit:rangeType="long">3</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C0_LPDDR2_CK_WIDTH</spirit:name>
        <spirit:displayName>clock width</spirit:displayName>
        <spirit:description>clock width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0_LPDDR2_CK_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="4" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C0_LPDDR2_CKE_WIDTH</spirit:name>
        <spirit:displayName>clock enable width</spirit:displayName>
        <spirit:description>clock enable width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0_LPDDR2_CKE_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="2" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C0_LPDDR2_CS_WIDTH</spirit:name>
        <spirit:displayName>chip select width</spirit:displayName>
        <spirit:description>chip select width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0_LPDDR2_CS_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="2" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C0_LPDDR2_nCS_PER_RANK</spirit:name>
        <spirit:displayName>chip select per rank</spirit:displayName>
        <spirit:description>chip select per rank</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0_LPDDR2_nCS_PER_RANK" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="4" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C0_LPDDR2_DM_WIDTH</spirit:name>
        <spirit:displayName>data mask width</spirit:displayName>
        <spirit:description>data mask width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0_LPDDR2_DM_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="9" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C0_LPDDR2_USE_CS_PORT</spirit:name>
        <spirit:displayName>CS Port is in use</spirit:displayName>
        <spirit:description>CS Port is in use</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0_LPDDR2_USE_CS_PORT" spirit:configGroups="default" spirit:minimum="0" spirit:maximum="1" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C0_LPDDR2_USE_DM_PORT</spirit:name>
        <spirit:displayName>DM Port is in use</spirit:displayName>
        <spirit:description>DM Port is in use</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0_LPDDR2_USE_DM_PORT" spirit:configGroups="default" spirit:minimum="0" spirit:maximum="1" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C0_LPDDR2_USE_ODT_PORT</spirit:name>
        <spirit:displayName>ODT Port is in use</spirit:displayName>
        <spirit:description>ODT Port is in use</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0_LPDDR2_USE_ODT_PORT" spirit:configGroups="default" spirit:minimum="0" spirit:maximum="1" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="string">
        <spirit:name>C0_LPDDR2_REG_CTRL</spirit:name>
        <spirit:displayName>Indicates Registered DIMM or not</spirit:displayName>
        <spirit:description>Indicates Registered DIMM or not</spirit:description>
        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0_LPDDR2_REG_CTRL" spirit:choiceRef="choice_list_dc86ec6e" spirit:configGroups="default">OFF</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C0_LPDDR2_DQS_CNT_WIDTH</spirit:name>
        <spirit:displayName>DQS count width</spirit:displayName>
        <spirit:description>DQS count width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0_LPDDR2_DQS_CNT_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="8" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="string">
        <spirit:name>C0_LPDDR2_DEBUG_PORT</spirit:name>
        <spirit:displayName>Debug Port enable info</spirit:displayName>
        <spirit:description>Debug Port enable info</spirit:description>
        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0_LPDDR2_DEBUG_PORT" spirit:choiceRef="choice_list_dc86ec6e" spirit:configGroups="default">OFF</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C0_DQS_CNT_WIDTH</spirit:name>
        <spirit:displayName>DQS count width</spirit:displayName>
        <spirit:description>DQS count width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0_DQS_CNT_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="8" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="string">
        <spirit:name>C0_DEBUG_PORT</spirit:name>
        <spirit:displayName>Debug Port enable info</spirit:displayName>
        <spirit:description>Debug Port enable info</spirit:description>
        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0_DEBUG_PORT" spirit:choiceRef="choice_list_dc86ec6e" spirit:configGroups="default">OFF</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C0_DDRX_ADDR_WIDTH</spirit:name>
        <spirit:displayName>addr width</spirit:displayName>
        <spirit:description>addr width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0_DDRX_ADDR_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="32" spirit:rangeType="long">8</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C0_DDRX_nCK_PER_CLK</spirit:name>
        <spirit:displayName>nck per clk</spirit:displayName>
        <spirit:description>nck per clk</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0_DDRX_nCK_PER_CLK" spirit:configGroups="default" spirit:minimum="0" spirit:maximum="4" spirit:rangeType="long">2</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C0_DDRX_DATA_WIDTH</spirit:name>
        <spirit:displayName>datawidth excluding the ECC</spirit:displayName>
        <spirit:description>datawidth excluding the ECC</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0_DDRX_DATA_WIDTH" spirit:configGroups="default" spirit:minimum="8" spirit:maximum="72" spirit:rangeType="long">8</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C0_DDR3_ADDR_WIDTH</spirit:name>
        <spirit:displayName>addr width</spirit:displayName>
        <spirit:description>addr width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0_DDR3_ADDR_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="32" spirit:rangeType="long">8</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C0_DDR3_nCK_PER_CLK</spirit:name>
        <spirit:displayName>nck per clk</spirit:displayName>
        <spirit:description>nck per clk</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0_DDR3_nCK_PER_CLK" spirit:configGroups="default" spirit:minimum="0" spirit:maximum="4" spirit:rangeType="long">2</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C0_DDR3_DATA_WIDTH</spirit:name>
        <spirit:displayName>datawidth excluding the ECC</spirit:displayName>
        <spirit:description>datawidth excluding the ECC</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0_DDR3_DATA_WIDTH" spirit:configGroups="default" spirit:minimum="8" spirit:maximum="72" spirit:rangeType="long">8</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C0_DDR2_ADDR_WIDTH</spirit:name>
        <spirit:displayName>addr width</spirit:displayName>
        <spirit:description>addr width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0_DDR2_ADDR_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="32" spirit:rangeType="long">8</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C0_DDR2_nCK_PER_CLK</spirit:name>
        <spirit:displayName>nck per clk</spirit:displayName>
        <spirit:description>nck per clk</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0_DDR2_nCK_PER_CLK" spirit:configGroups="default" spirit:minimum="0" spirit:maximum="4" spirit:rangeType="long">2</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C0_DDR2_DATA_WIDTH</spirit:name>
        <spirit:displayName>datawidth excluding the ECC</spirit:displayName>
        <spirit:description>datawidth excluding the ECC</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0_DDR2_DATA_WIDTH" spirit:configGroups="default" spirit:minimum="8" spirit:maximum="72" spirit:rangeType="long">8</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C0_LPDDR2_ADDR_WIDTH</spirit:name>
        <spirit:displayName>addr width</spirit:displayName>
        <spirit:description>addr width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0_LPDDR2_ADDR_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="32" spirit:rangeType="long">8</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C0_LPDDR2_nCK_PER_CLK</spirit:name>
        <spirit:displayName>nck per clk</spirit:displayName>
        <spirit:description>nck per clk</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0_LPDDR2_nCK_PER_CLK" spirit:configGroups="default" spirit:minimum="0" spirit:maximum="4" spirit:rangeType="long">2</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C0_LPDDR2_DATA_WIDTH</spirit:name>
        <spirit:displayName>datawidth excluding the ECC</spirit:displayName>
        <spirit:description>datawidth excluding the ECC</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0_LPDDR2_DATA_WIDTH" spirit:configGroups="default" spirit:minimum="8" spirit:maximum="72" spirit:rangeType="long">8</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="float">
        <spirit:name>C0_FREQ_HZ</spirit:name>
        <spirit:displayName>defines the UI Clk freq</spirit:displayName>
        <spirit:description>defines the UI Clk freq</spirit:description>
        <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0_FREQ_HZ" spirit:configGroups="default" spirit:minimum="0.0" spirit:maximum="800000000.0" spirit:rangeType="long">100.0</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="float">
        <spirit:name>C0_PHASE</spirit:name>
        <spirit:displayName>defines the UI Clk phase</spirit:displayName>
        <spirit:description>defines the UI Clk phase</spirit:description>
        <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0_PHASE" spirit:choiceRef="choice_list_c7c132f6" spirit:configGroups="default">0.000</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="string">
        <spirit:name>C0_UI_EXTRA_CLOCKS</spirit:name>
        <spirit:displayName>Enablement of extra clocks</spirit:displayName>
        <spirit:description>Enablement of extra clocks</spirit:description>
        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0_UI_EXTRA_CLOCKS" spirit:choiceRef="choice_list_d10f4555" spirit:configGroups="default">FALSE</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="float">
        <spirit:name>C0_MMCM_VCO</spirit:name>
        <spirit:displayName>Max possible VCO of MMCM primitive </spirit:displayName>
        <spirit:description>Max possible VCO of MMCM primitive </spirit:description>
        <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0_MMCM_VCO" spirit:configGroups="default" spirit:minimum="600.0" spirit:maximum="1600.0" spirit:rangeType="long">1200.0</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="float">
        <spirit:name>C0_MMCM_CLKOUT0_FREQ</spirit:name>
        <spirit:displayName>mmcm extra clkout0</spirit:displayName>
        <spirit:description>mmcm extra clkout0</spirit:description>
        <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0_MMCM_CLKOUT0_FREQ" spirit:configGroups="default" spirit:minimum="0.0" spirit:maximum="800000000.0" spirit:rangeType="long">10.0</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C0_MMCM_CLKOUT1_FREQ</spirit:name>
        <spirit:displayName>mmcm extra clkout1</spirit:displayName>
        <spirit:description>mmcm extra clkout1</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0_MMCM_CLKOUT1_FREQ" spirit:configGroups="default" spirit:minimum="0.0" spirit:maximum="800000000" spirit:rangeType="long">10</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C0_MMCM_CLKOUT2_FREQ</spirit:name>
        <spirit:displayName>mmcm extra clkout2</spirit:displayName>
        <spirit:description>mmcm extra clkout2</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0_MMCM_CLKOUT2_FREQ" spirit:configGroups="default" spirit:minimum="0.0" spirit:maximum="800000000" spirit:rangeType="long">10</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C0_MMCM_CLKOUT3_FREQ</spirit:name>
        <spirit:displayName>mmcm extra clkout3</spirit:displayName>
        <spirit:description>mmcm extra clkout3</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0_MMCM_CLKOUT3_FREQ" spirit:configGroups="default" spirit:minimum="0.0" spirit:maximum="800000000" spirit:rangeType="long">10</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C0_MMCM_CLKOUT4_FREQ</spirit:name>
        <spirit:displayName>mmcm extra clkout4</spirit:displayName>
        <spirit:description>mmcm extra clkout4</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0_MMCM_CLKOUT4_FREQ" spirit:configGroups="default" spirit:minimum="0.0" spirit:maximum="800000000" spirit:rangeType="long">10</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="string">
        <spirit:name>C0_MMCM_CLKOUT0_EN</spirit:name>
        <spirit:displayName>Indicates Enablement of CLKOUT0</spirit:displayName>
        <spirit:description>Indicates Enablement of CLKOUT0</spirit:description>
        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0_MMCM_CLKOUT0_EN" spirit:choiceRef="choice_list_e7c484ae" spirit:configGroups="default">FALSE</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="string">
        <spirit:name>C0_MMCM_CLKOUT2_EN</spirit:name>
        <spirit:displayName>Indicates Enablement of CLKOUT2</spirit:displayName>
        <spirit:description>Indicates Enablement of CLKOUT2</spirit:description>
        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0_MMCM_CLKOUT2_EN" spirit:choiceRef="choice_list_e7c484ae" spirit:configGroups="default">FALSE</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="string">
        <spirit:name>C0_MMCM_CLKOUT1_EN</spirit:name>
        <spirit:displayName>Indicates Enablement of CLKOUT1</spirit:displayName>
        <spirit:description>Indicates Enablement of CLKOUT1</spirit:description>
        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0_MMCM_CLKOUT1_EN" spirit:choiceRef="choice_list_e7c484ae" spirit:configGroups="default">FALSE</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="string">
        <spirit:name>C0_MMCM_CLKOUT3_EN</spirit:name>
        <spirit:displayName>Indicates Enablement of CLKOUT3</spirit:displayName>
        <spirit:description>Indicates Enablement of CLKOUT3</spirit:description>
        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0_MMCM_CLKOUT3_EN" spirit:choiceRef="choice_list_e7c484ae" spirit:configGroups="default">FALSE</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="string">
        <spirit:name>C0_MMCM_CLKOUT4_EN</spirit:name>
        <spirit:displayName>Indicates Enablement of CLKOUT4</spirit:displayName>
        <spirit:description>Indicates Enablement of CLKOUT4</spirit:description>
        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0_MMCM_CLKOUT4_EN" spirit:choiceRef="choice_list_e7c484ae" spirit:configGroups="default">FALSE</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C0_C_S_AXI_CTRL_ID_WIDTH</spirit:name>
        <spirit:displayName>AXI ID Width</spirit:displayName>
        <spirit:description>AXI ID Width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0_C_S_AXI_CTRL_ID_WIDTH" spirit:configGroups="default" spirit:minimum="0" spirit:maximum="16" spirit:rangeType="long">4</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C0_C_S_AXI_CTRL_DATA_WIDTH</spirit:name>
        <spirit:displayName>AXI Data Width</spirit:displayName>
        <spirit:description>AXI Data Width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0_C_S_AXI_CTRL_DATA_WIDTH" spirit:choiceRef="choice_list_40181835" spirit:configGroups="default">32</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C0_C_S_AXI_CTRL_ADDR_WIDTH</spirit:name>
        <spirit:displayName>AXI Addr Width</spirit:displayName>
        <spirit:description>AXI Addr Width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0_C_S_AXI_CTRL_ADDR_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="36" spirit:rangeType="long">32</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C0_C_S_AXI_CTRL_MEM_SIZE</spirit:name>
        <spirit:displayName>Memory Address Space</spirit:displayName>
        <spirit:description>Memory Address Space</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0_C_S_AXI_CTRL_MEM_SIZE" spirit:configGroups="default" spirit:minimum="0" spirit:maximum="34359738368" spirit:rangeType="long">1048576</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C0_C_S_AXI_ID_WIDTH</spirit:name>
        <spirit:displayName>AXI ID Width</spirit:displayName>
        <spirit:description>AXI ID Width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0_C_S_AXI_ID_WIDTH" spirit:configGroups="default" spirit:minimum="0" spirit:maximum="16" spirit:rangeType="long">4</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C0_C_S_AXI_DATA_WIDTH</spirit:name>
        <spirit:displayName>AXI Data Width</spirit:displayName>
        <spirit:description>AXI Data Width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0_C_S_AXI_DATA_WIDTH" spirit:choiceRef="choice_list_40181835" spirit:configGroups="default">32</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C0_C_S_AXI_ADDR_WIDTH</spirit:name>
        <spirit:displayName>AXI Addr Width</spirit:displayName>
        <spirit:description>AXI Addr Width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0_C_S_AXI_ADDR_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="36" spirit:rangeType="long">32</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C0_C_S_AXI_MEM_SIZE</spirit:name>
        <spirit:displayName>Memory Address Space</spirit:displayName>
        <spirit:description>Memory Address Space</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0_C_S_AXI_MEM_SIZE" spirit:configGroups="default" spirit:minimum="0" spirit:maximum="34359738368" spirit:rangeType="long">1048576</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C0_QDRIIP_NUM_DEVICES</spirit:name>
        <spirit:displayName>num devices</spirit:displayName>
        <spirit:description>num devices</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0_QDRIIP_NUM_DEVICES" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="4" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C0_QDRIIP_DATA_WIDTH</spirit:name>
        <spirit:displayName>data width</spirit:displayName>
        <spirit:description>data width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0_QDRIIP_DATA_WIDTH" spirit:choiceRef="choice_list_cf6acb30" spirit:configGroups="default">18</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C0_QDRIIP_ADDR_WIDTH</spirit:name>
        <spirit:displayName>addr width </spirit:displayName>
        <spirit:description>addr width </spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0_QDRIIP_ADDR_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="32" spirit:rangeType="long">29</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C0_QDRIIP_BW_WIDTH</spirit:name>
        <spirit:displayName>bw width </spirit:displayName>
        <spirit:description>bw width </spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0_QDRIIP_BW_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="8" spirit:rangeType="long">8</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="string">
        <spirit:name>C0_QDRIIP_DEBUG_PORT</spirit:name>
        <spirit:displayName>Debug Port enable info</spirit:displayName>
        <spirit:description>Debug Port enable info</spirit:description>
        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0_QDRIIP_DEBUG_PORT" spirit:choiceRef="choice_list_dc86ec6e" spirit:configGroups="default">OFF</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C0_QDRIIP_BURST_LEN</spirit:name>
        <spirit:displayName>burst len </spirit:displayName>
        <spirit:description>burst len </spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0_QDRIIP_BURST_LEN" spirit:choiceRef="choice_list_dd2843c6" spirit:configGroups="default">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C0_RLDII_NUM_DEVICES</spirit:name>
        <spirit:displayName>num devices</spirit:displayName>
        <spirit:description>num devices</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0_RLDII_NUM_DEVICES" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="4" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C0_RLDII_DATA_WIDTH</spirit:name>
        <spirit:displayName>data width</spirit:displayName>
        <spirit:description>data width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0_RLDII_DATA_WIDTH" spirit:choiceRef="choice_list_cf6acb30" spirit:configGroups="default">18</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C0_RLDII_RLD_ADDR_WIDTH</spirit:name>
        <spirit:displayName>rld addr width </spirit:displayName>
        <spirit:description>rld addr width </spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0_RLDII_RLD_ADDR_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="32" spirit:rangeType="long">29</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C0_RLDII_QK_WIDTH</spirit:name>
        <spirit:displayName>qk width </spirit:displayName>
        <spirit:description>qk width </spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0_RLDII_QK_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="8" spirit:rangeType="long">8</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C0_RLDII_CK_WIDTH</spirit:name>
        <spirit:displayName>ck width </spirit:displayName>
        <spirit:description>ck width </spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0_RLDII_CK_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="4" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C0_RLDII_DK_WIDTH</spirit:name>
        <spirit:displayName>dk width </spirit:displayName>
        <spirit:description>dk width </spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0_RLDII_DK_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="4" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C0_RLDII_DM_WIDTH</spirit:name>
        <spirit:displayName>dm width </spirit:displayName>
        <spirit:description>dm width </spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0_RLDII_DM_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="4" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C0_RLDII_BANK_WIDTH</spirit:name>
        <spirit:displayName>bank width </spirit:displayName>
        <spirit:description>bank width </spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0_RLDII_BANK_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="4" spirit:rangeType="long">2</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C0_RLDII_QVLD_WIDTH</spirit:name>
        <spirit:displayName>qvld width </spirit:displayName>
        <spirit:description>qvld width </spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0_RLDII_QVLD_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="4" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="string">
        <spirit:name>C0_RLDII_DEBUG_PORT</spirit:name>
        <spirit:displayName>Debug Port enable info</spirit:displayName>
        <spirit:description>Debug Port enable info</spirit:description>
        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0_RLDII_DEBUG_PORT" spirit:choiceRef="choice_list_dc86ec6e" spirit:configGroups="default">OFF</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C0_RLDIII_NUM_DEVICES</spirit:name>
        <spirit:displayName>num devices</spirit:displayName>
        <spirit:description>num devices</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0_RLDIII_NUM_DEVICES" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="4" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C0_RLDIII_DATA_WIDTH</spirit:name>
        <spirit:displayName>data width</spirit:displayName>
        <spirit:description>data width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0_RLDIII_DATA_WIDTH" spirit:choiceRef="choice_list_cf6acb30" spirit:configGroups="default">18</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C0_RLDIII_RLD_ADDR_WIDTH</spirit:name>
        <spirit:displayName>rld addr width </spirit:displayName>
        <spirit:description>rld addr width </spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0_RLDIII_RLD_ADDR_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="32" spirit:rangeType="long">29</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C0_RLDIII_QK_WIDTH</spirit:name>
        <spirit:displayName>qk width </spirit:displayName>
        <spirit:description>qk width </spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0_RLDIII_QK_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="8" spirit:rangeType="long">8</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C0_RLDIII_CK_WIDTH</spirit:name>
        <spirit:displayName>ck width </spirit:displayName>
        <spirit:description>ck width </spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0_RLDIII_CK_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="4" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C0_RLDIII_DK_WIDTH</spirit:name>
        <spirit:displayName>dk width </spirit:displayName>
        <spirit:description>dk width </spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0_RLDIII_DK_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="4" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C0_RLDIII_DM_WIDTH</spirit:name>
        <spirit:displayName>dm width </spirit:displayName>
        <spirit:description>dm width </spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0_RLDIII_DM_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="4" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C0_RLDIII_BANK_WIDTH</spirit:name>
        <spirit:displayName>bank width </spirit:displayName>
        <spirit:description>bank width </spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0_RLDIII_BANK_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="4" spirit:rangeType="long">2</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C0_RLDIII_QVLD_WIDTH</spirit:name>
        <spirit:displayName>qvld width </spirit:displayName>
        <spirit:description>qvld width </spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0_RLDIII_QVLD_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="4" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="string">
        <spirit:name>C0_RLDIII_DEBUG_PORT</spirit:name>
        <spirit:displayName>Debug Port enable info</spirit:displayName>
        <spirit:description>Debug Port enable info</spirit:description>
        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0_RLDIII_DEBUG_PORT" spirit:choiceRef="choice_list_dc86ec6e" spirit:configGroups="default">OFF</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C0_RLDX_CMD_PER_CLK</spirit:name>
        <spirit:displayName>cmd per clock</spirit:displayName>
        <spirit:description>cmd per clock</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0_RLDX_CMD_PER_CLK" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="4" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C0_RLDX_DATA_WIDTH</spirit:name>
        <spirit:displayName>data width</spirit:displayName>
        <spirit:description>data width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0_RLDX_DATA_WIDTH" spirit:choiceRef="choice_list_cf6acb30" spirit:configGroups="default">18</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C0_RLDX_ADDR_WIDTH</spirit:name>
        <spirit:displayName>addr width </spirit:displayName>
        <spirit:description>addr width </spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0_RLDX_ADDR_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="32" spirit:rangeType="long">29</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C0_RLDX_BANK_WIDTH</spirit:name>
        <spirit:displayName>bank width </spirit:displayName>
        <spirit:description>bank width </spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0_RLDX_BANK_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="4" spirit:rangeType="long">2</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C0_RLDX_nCK_PER_CLK</spirit:name>
        <spirit:displayName>nCk per clock</spirit:displayName>
        <spirit:description>nCk per clock</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0_RLDX_nCK_PER_CLK" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="4" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C0_RLDX_DM_WIDTH</spirit:name>
        <spirit:displayName>dm width </spirit:displayName>
        <spirit:description>dm width </spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0_RLDX_DM_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="4" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C0_RLDII_CMD_PER_CLK</spirit:name>
        <spirit:displayName>cmd per clock</spirit:displayName>
        <spirit:description>cmd per clock</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0_RLDII_CMD_PER_CLK" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="4" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C0_RLDII_ADDR_WIDTH</spirit:name>
        <spirit:displayName>addr width </spirit:displayName>
        <spirit:description>addr width </spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0_RLDII_ADDR_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="32" spirit:rangeType="long">29</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C0_RLDII_nCK_PER_CLK</spirit:name>
        <spirit:displayName>nCk per clock</spirit:displayName>
        <spirit:description>nCk per clock</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0_RLDII_nCK_PER_CLK" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="4" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C0_RLDIII_CMD_PER_CLK</spirit:name>
        <spirit:displayName>cmd per clock</spirit:displayName>
        <spirit:description>cmd per clock</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0_RLDIII_CMD_PER_CLK" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="4" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C0_RLDIII_ADDR_WIDTH</spirit:name>
        <spirit:displayName>addr width </spirit:displayName>
        <spirit:description>addr width </spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0_RLDIII_ADDR_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="32" spirit:rangeType="long">29</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C0_RLDIII_nCK_PER_CLK</spirit:name>
        <spirit:displayName>nCk per clock</spirit:displayName>
        <spirit:description>nCk per clock</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0_RLDIII_nCK_PER_CLK" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="4" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="string">
        <spirit:name>C0_POLARITY</spirit:name>
        <spirit:displayName>Polarity of the value</spirit:displayName>
        <spirit:description>Polarity of the value</spirit:description>
        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0_POLARITY" spirit:choiceRef="choice_list_6eff49bd" spirit:configGroups="default">ACTIVE_LOW</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="string">
        <spirit:name>C1_MEM_TYPE</spirit:name>
        <spirit:displayName>identify interface</spirit:displayName>
        <spirit:description>identify interface</spirit:description>
        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C1_MEM_TYPE" spirit:choiceRef="choice_list_b54243b1" spirit:configGroups="default">DDR3</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="string">
        <spirit:name>C1_IS_CLK_SHARED</spirit:name>
        <spirit:displayName>is clk shared</spirit:displayName>
        <spirit:description>is clk shared</spirit:description>
        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C1_IS_CLK_SHARED" spirit:choiceRef="choice_list_d10f4555" spirit:configGroups="default">FALSE</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="string">
        <spirit:name>C1_SYSCLK_TYPE</spirit:name>
        <spirit:displayName>Type of sys clk</spirit:displayName>
        <spirit:description>Type of sys clk</spirit:description>
        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C1_SYSCLK_TYPE" spirit:choiceRef="choice_list_1570a756" spirit:configGroups="default">DIFF</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C1_USE_AXI</spirit:name>
        <spirit:displayName>USE AXI</spirit:displayName>
        <spirit:description>USE AXI</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C1_USE_AXI" spirit:configGroups="default" spirit:minimum="0" spirit:maximum="1" spirit:rangeType="long">0</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="string">
        <spirit:name>C1_ECC</spirit:name>
        <spirit:displayName>ecc enable info</spirit:displayName>
        <spirit:description>ecc enable info</spirit:description>
        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C1_ECC" spirit:choiceRef="choice_list_dc86ec6e" spirit:configGroups="default">OFF</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C1_DDR3_DQ_WIDTH</spirit:name>
        <spirit:displayName>data bus width</spirit:displayName>
        <spirit:description>data bus width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C1_DDR3_DQ_WIDTH" spirit:choiceRef="choice_list_bdb560e1" spirit:configGroups="default">8</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C1_DDR3_DQS_WIDTH</spirit:name>
        <spirit:displayName>data strobe width</spirit:displayName>
        <spirit:description>data strobe width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C1_DDR3_DQS_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="9" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C1_DDR3_ROW_WIDTH</spirit:name>
        <spirit:displayName>row width</spirit:displayName>
        <spirit:description>row width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C1_DDR3_ROW_WIDTH" spirit:configGroups="default" spirit:minimum="13" spirit:maximum="16" spirit:rangeType="long">14</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C1_DDR3_BANK_WIDTH</spirit:name>
        <spirit:displayName>bank width</spirit:displayName>
        <spirit:description>bank width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C1_DDR3_BANK_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="3" spirit:rangeType="long">3</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C1_DDR3_CK_WIDTH</spirit:name>
        <spirit:displayName>clock width</spirit:displayName>
        <spirit:description>clock width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C1_DDR3_CK_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="4" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C1_DDR3_CKE_WIDTH</spirit:name>
        <spirit:displayName>clock enable width</spirit:displayName>
        <spirit:description>clock enable width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C1_DDR3_CKE_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="2" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C1_DDR3_CS_WIDTH</spirit:name>
        <spirit:displayName>chip select width</spirit:displayName>
        <spirit:description>chip select width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C1_DDR3_CS_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="2" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C1_DDR3_nCS_PER_RANK</spirit:name>
        <spirit:displayName>chip select per rank</spirit:displayName>
        <spirit:description>chip select per rank</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C1_DDR3_nCS_PER_RANK" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="4" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C1_DDR3_DM_WIDTH</spirit:name>
        <spirit:displayName>data mask width</spirit:displayName>
        <spirit:description>data mask width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C1_DDR3_DM_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="9" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C1_DDR3_ODT_WIDTH</spirit:name>
        <spirit:displayName>odt width</spirit:displayName>
        <spirit:description>odt width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C1_DDR3_ODT_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="4" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C1_DDR3_USE_CS_PORT</spirit:name>
        <spirit:displayName>CS Port is in use</spirit:displayName>
        <spirit:description>CS Port is in use</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C1_DDR3_USE_CS_PORT" spirit:configGroups="default" spirit:minimum="0" spirit:maximum="1" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C1_DDR3_USE_DM_PORT</spirit:name>
        <spirit:displayName>DM Port is in use</spirit:displayName>
        <spirit:description>DM Port is in use</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C1_DDR3_USE_DM_PORT" spirit:configGroups="default" spirit:minimum="0" spirit:maximum="1" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C1_DDR3_USE_ODT_PORT</spirit:name>
        <spirit:displayName>ODT Port is in use</spirit:displayName>
        <spirit:description>ODT Port is in use</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C1_DDR3_USE_ODT_PORT" spirit:configGroups="default" spirit:minimum="0" spirit:maximum="1" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="string">
        <spirit:name>C1_DDR3_REG_CTRL</spirit:name>
        <spirit:displayName>Indicates Registered DIMM or not</spirit:displayName>
        <spirit:description>Indicates Registered DIMM or not</spirit:description>
        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C1_DDR3_REG_CTRL" spirit:choiceRef="choice_list_dc86ec6e" spirit:configGroups="default">OFF</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C1_DDR3_DQS_CNT_WIDTH</spirit:name>
        <spirit:displayName>DQS count width</spirit:displayName>
        <spirit:description>DQS count width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C1_DDR3_DQS_CNT_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="8" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="string">
        <spirit:name>C1_DDR3_DEBUG_PORT</spirit:name>
        <spirit:displayName>Debug Port enable info</spirit:displayName>
        <spirit:description>Debug Port enable info</spirit:description>
        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C1_DDR3_DEBUG_PORT" spirit:choiceRef="choice_list_dc86ec6e" spirit:configGroups="default">OFF</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C1_DDR2_DQ_WIDTH</spirit:name>
        <spirit:displayName>data bus width</spirit:displayName>
        <spirit:description>data bus width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C1_DDR2_DQ_WIDTH" spirit:choiceRef="choice_list_bdb560e1" spirit:configGroups="default">8</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C1_DDR2_DQS_WIDTH</spirit:name>
        <spirit:displayName>data strobe width</spirit:displayName>
        <spirit:description>data strobe width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C1_DDR2_DQS_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="9" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C1_DDR2_ROW_WIDTH</spirit:name>
        <spirit:displayName>row width</spirit:displayName>
        <spirit:description>row width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C1_DDR2_ROW_WIDTH" spirit:configGroups="default" spirit:minimum="13" spirit:maximum="16" spirit:rangeType="long">14</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C1_DDR2_BANK_WIDTH</spirit:name>
        <spirit:displayName>bank width</spirit:displayName>
        <spirit:description>bank width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C1_DDR2_BANK_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="3" spirit:rangeType="long">3</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C1_DDR2_CK_WIDTH</spirit:name>
        <spirit:displayName>clock width</spirit:displayName>
        <spirit:description>clock width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C1_DDR2_CK_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="4" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C1_DDR2_CKE_WIDTH</spirit:name>
        <spirit:displayName>clock enable width</spirit:displayName>
        <spirit:description>clock enable width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C1_DDR2_CKE_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="2" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C1_DDR2_CS_WIDTH</spirit:name>
        <spirit:displayName>chip select width</spirit:displayName>
        <spirit:description>chip select width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C1_DDR2_CS_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="2" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C1_DDR2_nCS_PER_RANK</spirit:name>
        <spirit:displayName>chip select per rank</spirit:displayName>
        <spirit:description>chip select per rank</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C1_DDR2_nCS_PER_RANK" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="4" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C1_DDR2_DM_WIDTH</spirit:name>
        <spirit:displayName>data mask width</spirit:displayName>
        <spirit:description>data mask width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C1_DDR2_DM_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="9" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C1_DDR2_ODT_WIDTH</spirit:name>
        <spirit:displayName>odt width</spirit:displayName>
        <spirit:description>odt width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C1_DDR2_ODT_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="4" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C1_DDR2_USE_CS_PORT</spirit:name>
        <spirit:displayName>CS Port is in use</spirit:displayName>
        <spirit:description>CS Port is in use</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C1_DDR2_USE_CS_PORT" spirit:configGroups="default" spirit:minimum="0" spirit:maximum="1" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C1_DDR2_USE_DM_PORT</spirit:name>
        <spirit:displayName>DM Port is in use</spirit:displayName>
        <spirit:description>DM Port is in use</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C1_DDR2_USE_DM_PORT" spirit:configGroups="default" spirit:minimum="0" spirit:maximum="1" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C1_DDR2_USE_ODT_PORT</spirit:name>
        <spirit:displayName>ODT Port is in use</spirit:displayName>
        <spirit:description>ODT Port is in use</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C1_DDR2_USE_ODT_PORT" spirit:configGroups="default" spirit:minimum="0" spirit:maximum="1" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="string">
        <spirit:name>C1_DDR2_REG_CTRL</spirit:name>
        <spirit:displayName>Indicates Registered DIMM or not</spirit:displayName>
        <spirit:description>Indicates Registered DIMM or not</spirit:description>
        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C1_DDR2_REG_CTRL" spirit:choiceRef="choice_list_dc86ec6e" spirit:configGroups="default">OFF</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C1_DDR2_DQS_CNT_WIDTH</spirit:name>
        <spirit:displayName>DQS count width</spirit:displayName>
        <spirit:description>DQS count width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C1_DDR2_DQS_CNT_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="8" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="string">
        <spirit:name>C1_DDR2_DEBUG_PORT</spirit:name>
        <spirit:displayName>Debug Port enable info</spirit:displayName>
        <spirit:description>Debug Port enable info</spirit:description>
        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C1_DDR2_DEBUG_PORT" spirit:choiceRef="choice_list_dc86ec6e" spirit:configGroups="default">OFF</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C1_LPDDR2_DQ_WIDTH</spirit:name>
        <spirit:displayName>data bus width</spirit:displayName>
        <spirit:description>data bus width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C1_LPDDR2_DQ_WIDTH" spirit:choiceRef="choice_list_bdb560e1" spirit:configGroups="default">8</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C1_LPDDR2_DQS_WIDTH</spirit:name>
        <spirit:displayName>data strobe width</spirit:displayName>
        <spirit:description>data strobe width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C1_LPDDR2_DQS_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="9" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C1_LPDDR2_ROW_WIDTH</spirit:name>
        <spirit:displayName>row width</spirit:displayName>
        <spirit:description>row width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C1_LPDDR2_ROW_WIDTH" spirit:configGroups="default" spirit:minimum="12" spirit:maximum="16" spirit:rangeType="long">14</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C1_LPDDR2_BANK_WIDTH</spirit:name>
        <spirit:displayName>bank width</spirit:displayName>
        <spirit:description>bank width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C1_LPDDR2_BANK_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="3" spirit:rangeType="long">3</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C1_LPDDR2_CK_WIDTH</spirit:name>
        <spirit:displayName>clock width</spirit:displayName>
        <spirit:description>clock width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C1_LPDDR2_CK_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="4" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C1_LPDDR2_CKE_WIDTH</spirit:name>
        <spirit:displayName>clock enable width</spirit:displayName>
        <spirit:description>clock enable width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C1_LPDDR2_CKE_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="2" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C1_LPDDR2_CS_WIDTH</spirit:name>
        <spirit:displayName>chip select width</spirit:displayName>
        <spirit:description>chip select width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C1_LPDDR2_CS_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="2" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C1_LPDDR2_nCS_PER_RANK</spirit:name>
        <spirit:displayName>chip select per rank</spirit:displayName>
        <spirit:description>chip select per rank</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C1_LPDDR2_nCS_PER_RANK" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="4" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C1_LPDDR2_DM_WIDTH</spirit:name>
        <spirit:displayName>data mask width</spirit:displayName>
        <spirit:description>data mask width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C1_LPDDR2_DM_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="9" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C1_LPDDR2_USE_CS_PORT</spirit:name>
        <spirit:displayName>CS Port is in use</spirit:displayName>
        <spirit:description>CS Port is in use</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C1_LPDDR2_USE_CS_PORT" spirit:configGroups="default" spirit:minimum="0" spirit:maximum="1" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C1_LPDDR2_USE_DM_PORT</spirit:name>
        <spirit:displayName>DM Port is in use</spirit:displayName>
        <spirit:description>DM Port is in use</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C1_LPDDR2_USE_DM_PORT" spirit:configGroups="default" spirit:minimum="0" spirit:maximum="1" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C1_LPDDR2_USE_ODT_PORT</spirit:name>
        <spirit:displayName>ODT Port is in use</spirit:displayName>
        <spirit:description>ODT Port is in use</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C1_LPDDR2_USE_ODT_PORT" spirit:configGroups="default" spirit:minimum="0" spirit:maximum="1" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="string">
        <spirit:name>C1_LPDDR2_REG_CTRL</spirit:name>
        <spirit:displayName>Indicates Registered DIMM or not</spirit:displayName>
        <spirit:description>Indicates Registered DIMM or not</spirit:description>
        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C1_LPDDR2_REG_CTRL" spirit:choiceRef="choice_list_dc86ec6e" spirit:configGroups="default">OFF</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C1_LPDDR2_DQS_CNT_WIDTH</spirit:name>
        <spirit:displayName>DQS count width</spirit:displayName>
        <spirit:description>DQS count width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C1_LPDDR2_DQS_CNT_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="8" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="string">
        <spirit:name>C1_LPDDR2_DEBUG_PORT</spirit:name>
        <spirit:displayName>Debug Port enable info</spirit:displayName>
        <spirit:description>Debug Port enable info</spirit:description>
        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C1_LPDDR2_DEBUG_PORT" spirit:choiceRef="choice_list_dc86ec6e" spirit:configGroups="default">OFF</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C1_DQS_CNT_WIDTH</spirit:name>
        <spirit:displayName>DQS count width</spirit:displayName>
        <spirit:description>DQS count width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C1_DQS_CNT_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="8" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="string">
        <spirit:name>C1_DEBUG_PORT</spirit:name>
        <spirit:displayName>Debug Port enable info</spirit:displayName>
        <spirit:description>Debug Port enable info</spirit:description>
        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C1_DEBUG_PORT" spirit:choiceRef="choice_list_dc86ec6e" spirit:configGroups="default">OFF</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C1_DDRX_ADDR_WIDTH</spirit:name>
        <spirit:displayName>addr width</spirit:displayName>
        <spirit:description>addr width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C1_DDRX_ADDR_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="32" spirit:rangeType="long">8</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C1_DDRX_nCK_PER_CLK</spirit:name>
        <spirit:displayName>nck per clk</spirit:displayName>
        <spirit:description>nck per clk</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C1_DDRX_nCK_PER_CLK" spirit:configGroups="default" spirit:minimum="0" spirit:maximum="4" spirit:rangeType="long">2</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C1_DDRX_DATA_WIDTH</spirit:name>
        <spirit:displayName>datawidth excluding the ECC</spirit:displayName>
        <spirit:description>datawidth excluding the ECC</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C1_DDRX_DATA_WIDTH" spirit:configGroups="default" spirit:minimum="8" spirit:maximum="72" spirit:rangeType="long">8</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C1_DDR3_ADDR_WIDTH</spirit:name>
        <spirit:displayName>addr width</spirit:displayName>
        <spirit:description>addr width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C1_DDR3_ADDR_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="32" spirit:rangeType="long">8</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C1_DDR3_nCK_PER_CLK</spirit:name>
        <spirit:displayName>nck per clk</spirit:displayName>
        <spirit:description>nck per clk</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C1_DDR3_nCK_PER_CLK" spirit:configGroups="default" spirit:minimum="0" spirit:maximum="4" spirit:rangeType="long">2</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C1_DDR3_DATA_WIDTH</spirit:name>
        <spirit:displayName>datawidth excluding the ECC</spirit:displayName>
        <spirit:description>datawidth excluding the ECC</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C1_DDR3_DATA_WIDTH" spirit:configGroups="default" spirit:minimum="8" spirit:maximum="72" spirit:rangeType="long">8</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C1_DDR2_ADDR_WIDTH</spirit:name>
        <spirit:displayName>addr width</spirit:displayName>
        <spirit:description>addr width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C1_DDR2_ADDR_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="32" spirit:rangeType="long">8</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C1_DDR2_nCK_PER_CLK</spirit:name>
        <spirit:displayName>nck per clk</spirit:displayName>
        <spirit:description>nck per clk</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C1_DDR2_nCK_PER_CLK" spirit:configGroups="default" spirit:minimum="0" spirit:maximum="4" spirit:rangeType="long">2</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C1_DDR2_DATA_WIDTH</spirit:name>
        <spirit:displayName>datawidth excluding the ECC</spirit:displayName>
        <spirit:description>datawidth excluding the ECC</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C1_DDR2_DATA_WIDTH" spirit:configGroups="default" spirit:minimum="8" spirit:maximum="72" spirit:rangeType="long">8</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C1_LPDDR2_ADDR_WIDTH</spirit:name>
        <spirit:displayName>addr width</spirit:displayName>
        <spirit:description>addr width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C1_LPDDR2_ADDR_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="32" spirit:rangeType="long">8</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C1_LPDDR2_nCK_PER_CLK</spirit:name>
        <spirit:displayName>nck per clk</spirit:displayName>
        <spirit:description>nck per clk</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C1_LPDDR2_nCK_PER_CLK" spirit:configGroups="default" spirit:minimum="0" spirit:maximum="4" spirit:rangeType="long">2</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C1_LPDDR2_DATA_WIDTH</spirit:name>
        <spirit:displayName>datawidth excluding the ECC</spirit:displayName>
        <spirit:description>datawidth excluding the ECC</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C1_LPDDR2_DATA_WIDTH" spirit:configGroups="default" spirit:minimum="8" spirit:maximum="72" spirit:rangeType="long">8</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="float">
        <spirit:name>C1_FREQ_HZ</spirit:name>
        <spirit:displayName>defines the UI Clk freq</spirit:displayName>
        <spirit:description>defines the UI Clk freq</spirit:description>
        <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C1_FREQ_HZ" spirit:configGroups="default" spirit:minimum="0.0" spirit:maximum="800000000.0" spirit:rangeType="long">100.0</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="float">
        <spirit:name>C1_PHASE</spirit:name>
        <spirit:displayName>defines the UI Clk phase</spirit:displayName>
        <spirit:description>defines the UI Clk phase</spirit:description>
        <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C1_PHASE" spirit:choiceRef="choice_list_c7c132f6" spirit:configGroups="default">0.000</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="string">
        <spirit:name>C1_UI_EXTRA_CLOCKS</spirit:name>
        <spirit:displayName>Enablement of extra clocks</spirit:displayName>
        <spirit:description>Enablement of extra clocks</spirit:description>
        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C1_UI_EXTRA_CLOCKS" spirit:choiceRef="choice_list_d10f4555" spirit:configGroups="default">FALSE</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="float">
        <spirit:name>C1_MMCM_VCO</spirit:name>
        <spirit:displayName>Max possible VCO of MMCM primitive </spirit:displayName>
        <spirit:description>Max possible VCO of MMCM primitive </spirit:description>
        <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C1_MMCM_VCO" spirit:configGroups="default" spirit:minimum="600.0" spirit:maximum="1600.0" spirit:rangeType="long">1200.0</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="float">
        <spirit:name>C1_MMCM_CLKOUT0_FREQ</spirit:name>
        <spirit:displayName>mmcm extra clkout0</spirit:displayName>
        <spirit:description>mmcm extra clkout0</spirit:description>
        <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C1_MMCM_CLKOUT0_FREQ" spirit:configGroups="default" spirit:minimum="0.0" spirit:maximum="800000000.0" spirit:rangeType="long">10.0</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C1_MMCM_CLKOUT1_FREQ</spirit:name>
        <spirit:displayName>mmcm extra clkout1</spirit:displayName>
        <spirit:description>mmcm extra clkout1</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C1_MMCM_CLKOUT1_FREQ" spirit:configGroups="default" spirit:minimum="0.0" spirit:maximum="800000000" spirit:rangeType="long">10</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C1_MMCM_CLKOUT2_FREQ</spirit:name>
        <spirit:displayName>mmcm extra clkout2</spirit:displayName>
        <spirit:description>mmcm extra clkout2</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C1_MMCM_CLKOUT2_FREQ" spirit:configGroups="default" spirit:minimum="0.0" spirit:maximum="800000000" spirit:rangeType="long">10</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C1_MMCM_CLKOUT3_FREQ</spirit:name>
        <spirit:displayName>mmcm extra clkout3</spirit:displayName>
        <spirit:description>mmcm extra clkout3</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C1_MMCM_CLKOUT3_FREQ" spirit:configGroups="default" spirit:minimum="0.0" spirit:maximum="800000000" spirit:rangeType="long">10</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C1_MMCM_CLKOUT4_FREQ</spirit:name>
        <spirit:displayName>mmcm extra clkout4</spirit:displayName>
        <spirit:description>mmcm extra clkout4</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C1_MMCM_CLKOUT4_FREQ" spirit:configGroups="default" spirit:minimum="0.0" spirit:maximum="800000000" spirit:rangeType="long">10</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="string">
        <spirit:name>C1_MMCM_CLKOUT0_EN</spirit:name>
        <spirit:displayName>Indicates Enablement of CLKOUT0</spirit:displayName>
        <spirit:description>Indicates Enablement of CLKOUT0</spirit:description>
        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C1_MMCM_CLKOUT0_EN" spirit:choiceRef="choice_list_e7c484ae" spirit:configGroups="default">FALSE</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="string">
        <spirit:name>C1_MMCM_CLKOUT2_EN</spirit:name>
        <spirit:displayName>Indicates Enablement of CLKOUT2</spirit:displayName>
        <spirit:description>Indicates Enablement of CLKOUT2</spirit:description>
        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C1_MMCM_CLKOUT2_EN" spirit:choiceRef="choice_list_e7c484ae" spirit:configGroups="default">FALSE</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="string">
        <spirit:name>C1_MMCM_CLKOUT1_EN</spirit:name>
        <spirit:displayName>Indicates Enablement of CLKOUT1</spirit:displayName>
        <spirit:description>Indicates Enablement of CLKOUT1</spirit:description>
        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C1_MMCM_CLKOUT1_EN" spirit:choiceRef="choice_list_e7c484ae" spirit:configGroups="default">FALSE</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="string">
        <spirit:name>C1_MMCM_CLKOUT3_EN</spirit:name>
        <spirit:displayName>Indicates Enablement of CLKOUT3</spirit:displayName>
        <spirit:description>Indicates Enablement of CLKOUT3</spirit:description>
        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C1_MMCM_CLKOUT3_EN" spirit:choiceRef="choice_list_e7c484ae" spirit:configGroups="default">FALSE</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="string">
        <spirit:name>C1_MMCM_CLKOUT4_EN</spirit:name>
        <spirit:displayName>Indicates Enablement of CLKOUT4</spirit:displayName>
        <spirit:description>Indicates Enablement of CLKOUT4</spirit:description>
        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C1_MMCM_CLKOUT4_EN" spirit:choiceRef="choice_list_e7c484ae" spirit:configGroups="default">FALSE</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C1_C_S_AXI_CTRL_ID_WIDTH</spirit:name>
        <spirit:displayName>AXI ID Width</spirit:displayName>
        <spirit:description>AXI ID Width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C1_C_S_AXI_CTRL_ID_WIDTH" spirit:configGroups="default" spirit:minimum="0" spirit:maximum="16" spirit:rangeType="long">4</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C1_C_S_AXI_CTRL_DATA_WIDTH</spirit:name>
        <spirit:displayName>AXI Data Width</spirit:displayName>
        <spirit:description>AXI Data Width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C1_C_S_AXI_CTRL_DATA_WIDTH" spirit:choiceRef="choice_list_40181835" spirit:configGroups="default">32</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C1_C_S_AXI_CTRL_ADDR_WIDTH</spirit:name>
        <spirit:displayName>AXI Addr Width</spirit:displayName>
        <spirit:description>AXI Addr Width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C1_C_S_AXI_CTRL_ADDR_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="36" spirit:rangeType="long">32</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C1_C_S_AXI_CTRL_MEM_SIZE</spirit:name>
        <spirit:displayName>Memory Address Space</spirit:displayName>
        <spirit:description>Memory Address Space</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C1_C_S_AXI_CTRL_MEM_SIZE" spirit:configGroups="default" spirit:minimum="0" spirit:maximum="34359738368" spirit:rangeType="long">1048576</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C1_C_S_AXI_ID_WIDTH</spirit:name>
        <spirit:displayName>AXI ID Width</spirit:displayName>
        <spirit:description>AXI ID Width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C1_C_S_AXI_ID_WIDTH" spirit:configGroups="default" spirit:minimum="0" spirit:maximum="16" spirit:rangeType="long">4</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C1_C_S_AXI_DATA_WIDTH</spirit:name>
        <spirit:displayName>AXI Data Width</spirit:displayName>
        <spirit:description>AXI Data Width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C1_C_S_AXI_DATA_WIDTH" spirit:choiceRef="choice_list_40181835" spirit:configGroups="default">32</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C1_C_S_AXI_ADDR_WIDTH</spirit:name>
        <spirit:displayName>AXI Addr Width</spirit:displayName>
        <spirit:description>AXI Addr Width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C1_C_S_AXI_ADDR_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="36" spirit:rangeType="long">32</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C1_C_S_AXI_MEM_SIZE</spirit:name>
        <spirit:displayName>Memory Address Space</spirit:displayName>
        <spirit:description>Memory Address Space</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C1_C_S_AXI_MEM_SIZE" spirit:configGroups="default" spirit:minimum="0" spirit:maximum="34359738368" spirit:rangeType="long">1048576</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C1_QDRIIP_NUM_DEVICES</spirit:name>
        <spirit:displayName>num devices</spirit:displayName>
        <spirit:description>num devices</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C1_QDRIIP_NUM_DEVICES" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="4" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C1_QDRIIP_DATA_WIDTH</spirit:name>
        <spirit:displayName>data width</spirit:displayName>
        <spirit:description>data width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C1_QDRIIP_DATA_WIDTH" spirit:choiceRef="choice_list_cf6acb30" spirit:configGroups="default">18</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C1_QDRIIP_ADDR_WIDTH</spirit:name>
        <spirit:displayName>addr width </spirit:displayName>
        <spirit:description>addr width </spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C1_QDRIIP_ADDR_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="32" spirit:rangeType="long">29</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C1_QDRIIP_BW_WIDTH</spirit:name>
        <spirit:displayName>bw width </spirit:displayName>
        <spirit:description>bw width </spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C1_QDRIIP_BW_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="8" spirit:rangeType="long">8</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="string">
        <spirit:name>C1_QDRIIP_DEBUG_PORT</spirit:name>
        <spirit:displayName>Debug Port enable info</spirit:displayName>
        <spirit:description>Debug Port enable info</spirit:description>
        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C1_QDRIIP_DEBUG_PORT" spirit:choiceRef="choice_list_dc86ec6e" spirit:configGroups="default">OFF</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C1_QDRIIP_BURST_LEN</spirit:name>
        <spirit:displayName>burst len </spirit:displayName>
        <spirit:description>burst len </spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C1_QDRIIP_BURST_LEN" spirit:choiceRef="choice_list_dd2843c6" spirit:configGroups="default">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C1_RLDII_NUM_DEVICES</spirit:name>
        <spirit:displayName>num devices</spirit:displayName>
        <spirit:description>num devices</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C1_RLDII_NUM_DEVICES" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="4" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C1_RLDII_DATA_WIDTH</spirit:name>
        <spirit:displayName>data width</spirit:displayName>
        <spirit:description>data width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C1_RLDII_DATA_WIDTH" spirit:choiceRef="choice_list_cf6acb30" spirit:configGroups="default">18</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C1_RLDII_RLD_ADDR_WIDTH</spirit:name>
        <spirit:displayName>rld addr width </spirit:displayName>
        <spirit:description>rld addr width </spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C1_RLDII_RLD_ADDR_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="32" spirit:rangeType="long">29</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C1_RLDII_QK_WIDTH</spirit:name>
        <spirit:displayName>qk width </spirit:displayName>
        <spirit:description>qk width </spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C1_RLDII_QK_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="8" spirit:rangeType="long">8</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C1_RLDII_CK_WIDTH</spirit:name>
        <spirit:displayName>ck width </spirit:displayName>
        <spirit:description>ck width </spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C1_RLDII_CK_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="4" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C1_RLDII_DK_WIDTH</spirit:name>
        <spirit:displayName>dk width </spirit:displayName>
        <spirit:description>dk width </spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C1_RLDII_DK_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="4" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C1_RLDII_DM_WIDTH</spirit:name>
        <spirit:displayName>dm width </spirit:displayName>
        <spirit:description>dm width </spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C1_RLDII_DM_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="4" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C1_RLDII_BANK_WIDTH</spirit:name>
        <spirit:displayName>bank width </spirit:displayName>
        <spirit:description>bank width </spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C1_RLDII_BANK_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="4" spirit:rangeType="long">2</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C1_RLDII_QVLD_WIDTH</spirit:name>
        <spirit:displayName>qvld width </spirit:displayName>
        <spirit:description>qvld width </spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C1_RLDII_QVLD_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="4" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="string">
        <spirit:name>C1_RLDII_DEBUG_PORT</spirit:name>
        <spirit:displayName>Debug Port enable info</spirit:displayName>
        <spirit:description>Debug Port enable info</spirit:description>
        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C1_RLDII_DEBUG_PORT" spirit:choiceRef="choice_list_dc86ec6e" spirit:configGroups="default">OFF</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C1_RLDIII_NUM_DEVICES</spirit:name>
        <spirit:displayName>num devices</spirit:displayName>
        <spirit:description>num devices</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C1_RLDIII_NUM_DEVICES" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="4" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C1_RLDIII_DATA_WIDTH</spirit:name>
        <spirit:displayName>data width</spirit:displayName>
        <spirit:description>data width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C1_RLDIII_DATA_WIDTH" spirit:choiceRef="choice_list_cf6acb30" spirit:configGroups="default">18</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C1_RLDIII_RLD_ADDR_WIDTH</spirit:name>
        <spirit:displayName>rld addr width </spirit:displayName>
        <spirit:description>rld addr width </spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C1_RLDIII_RLD_ADDR_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="32" spirit:rangeType="long">29</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C1_RLDIII_QK_WIDTH</spirit:name>
        <spirit:displayName>qk width </spirit:displayName>
        <spirit:description>qk width </spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C1_RLDIII_QK_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="8" spirit:rangeType="long">8</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C1_RLDIII_CK_WIDTH</spirit:name>
        <spirit:displayName>ck width </spirit:displayName>
        <spirit:description>ck width </spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C1_RLDIII_CK_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="4" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C1_RLDIII_DK_WIDTH</spirit:name>
        <spirit:displayName>dk width </spirit:displayName>
        <spirit:description>dk width </spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C1_RLDIII_DK_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="4" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C1_RLDIII_DM_WIDTH</spirit:name>
        <spirit:displayName>dm width </spirit:displayName>
        <spirit:description>dm width </spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C1_RLDIII_DM_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="4" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C1_RLDIII_BANK_WIDTH</spirit:name>
        <spirit:displayName>bank width </spirit:displayName>
        <spirit:description>bank width </spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C1_RLDIII_BANK_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="4" spirit:rangeType="long">2</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C1_RLDIII_QVLD_WIDTH</spirit:name>
        <spirit:displayName>qvld width </spirit:displayName>
        <spirit:description>qvld width </spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C1_RLDIII_QVLD_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="4" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="string">
        <spirit:name>C1_RLDIII_DEBUG_PORT</spirit:name>
        <spirit:displayName>Debug Port enable info</spirit:displayName>
        <spirit:description>Debug Port enable info</spirit:description>
        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C1_RLDIII_DEBUG_PORT" spirit:choiceRef="choice_list_dc86ec6e" spirit:configGroups="default">OFF</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C1_RLDX_CMD_PER_CLK</spirit:name>
        <spirit:displayName>cmd per clock</spirit:displayName>
        <spirit:description>cmd per clock</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C1_RLDX_CMD_PER_CLK" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="4" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C1_RLDX_DATA_WIDTH</spirit:name>
        <spirit:displayName>data width</spirit:displayName>
        <spirit:description>data width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C1_RLDX_DATA_WIDTH" spirit:choiceRef="choice_list_cf6acb30" spirit:configGroups="default">18</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C1_RLDX_ADDR_WIDTH</spirit:name>
        <spirit:displayName>addr width </spirit:displayName>
        <spirit:description>addr width </spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C1_RLDX_ADDR_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="32" spirit:rangeType="long">29</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C1_RLDX_BANK_WIDTH</spirit:name>
        <spirit:displayName>bank width </spirit:displayName>
        <spirit:description>bank width </spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C1_RLDX_BANK_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="4" spirit:rangeType="long">2</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C1_RLDX_nCK_PER_CLK</spirit:name>
        <spirit:displayName>nCk per clock</spirit:displayName>
        <spirit:description>nCk per clock</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C1_RLDX_nCK_PER_CLK" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="4" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C1_RLDX_DM_WIDTH</spirit:name>
        <spirit:displayName>dm width </spirit:displayName>
        <spirit:description>dm width </spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C1_RLDX_DM_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="4" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C1_RLDII_CMD_PER_CLK</spirit:name>
        <spirit:displayName>cmd per clock</spirit:displayName>
        <spirit:description>cmd per clock</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C1_RLDII_CMD_PER_CLK" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="4" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C1_RLDII_ADDR_WIDTH</spirit:name>
        <spirit:displayName>addr width </spirit:displayName>
        <spirit:description>addr width </spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C1_RLDII_ADDR_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="32" spirit:rangeType="long">29</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C1_RLDII_nCK_PER_CLK</spirit:name>
        <spirit:displayName>nCk per clock</spirit:displayName>
        <spirit:description>nCk per clock</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C1_RLDII_nCK_PER_CLK" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="4" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C1_RLDIII_CMD_PER_CLK</spirit:name>
        <spirit:displayName>cmd per clock</spirit:displayName>
        <spirit:description>cmd per clock</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C1_RLDIII_CMD_PER_CLK" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="4" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C1_RLDIII_ADDR_WIDTH</spirit:name>
        <spirit:displayName>addr width </spirit:displayName>
        <spirit:description>addr width </spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C1_RLDIII_ADDR_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="32" spirit:rangeType="long">29</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C1_RLDIII_nCK_PER_CLK</spirit:name>
        <spirit:displayName>nCk per clock</spirit:displayName>
        <spirit:description>nCk per clock</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C1_RLDIII_nCK_PER_CLK" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="4" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="string">
        <spirit:name>C1_POLARITY</spirit:name>
        <spirit:displayName>Polarity of the value</spirit:displayName>
        <spirit:description>Polarity of the value</spirit:description>
        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C1_POLARITY" spirit:choiceRef="choice_list_6eff49bd" spirit:configGroups="default">ACTIVE_LOW</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="string">
        <spirit:name>C2_MEM_TYPE</spirit:name>
        <spirit:displayName>identify interface</spirit:displayName>
        <spirit:description>identify interface</spirit:description>
        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C2_MEM_TYPE" spirit:choiceRef="choice_list_b54243b1" spirit:configGroups="default">DDR3</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="string">
        <spirit:name>C2_IS_CLK_SHARED</spirit:name>
        <spirit:displayName>is clk shared</spirit:displayName>
        <spirit:description>is clk shared</spirit:description>
        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C2_IS_CLK_SHARED" spirit:choiceRef="choice_list_d10f4555" spirit:configGroups="default">FALSE</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="string">
        <spirit:name>C2_SYSCLK_TYPE</spirit:name>
        <spirit:displayName>Type of sys clk</spirit:displayName>
        <spirit:description>Type of sys clk</spirit:description>
        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C2_SYSCLK_TYPE" spirit:choiceRef="choice_list_1570a756" spirit:configGroups="default">DIFF</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C2_USE_AXI</spirit:name>
        <spirit:displayName>USE AXI</spirit:displayName>
        <spirit:description>USE AXI</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C2_USE_AXI" spirit:configGroups="default" spirit:minimum="0" spirit:maximum="1" spirit:rangeType="long">0</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="string">
        <spirit:name>C2_ECC</spirit:name>
        <spirit:displayName>ecc enable info</spirit:displayName>
        <spirit:description>ecc enable info</spirit:description>
        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C2_ECC" spirit:choiceRef="choice_list_dc86ec6e" spirit:configGroups="default">OFF</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C2_DDR3_DQ_WIDTH</spirit:name>
        <spirit:displayName>data bus width</spirit:displayName>
        <spirit:description>data bus width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C2_DDR3_DQ_WIDTH" spirit:choiceRef="choice_list_bdb560e1" spirit:configGroups="default">8</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C2_DDR3_DQS_WIDTH</spirit:name>
        <spirit:displayName>data strobe width</spirit:displayName>
        <spirit:description>data strobe width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C2_DDR3_DQS_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="9" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C2_DDR3_ROW_WIDTH</spirit:name>
        <spirit:displayName>row width</spirit:displayName>
        <spirit:description>row width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C2_DDR3_ROW_WIDTH" spirit:configGroups="default" spirit:minimum="13" spirit:maximum="16" spirit:rangeType="long">14</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C2_DDR3_BANK_WIDTH</spirit:name>
        <spirit:displayName>bank width</spirit:displayName>
        <spirit:description>bank width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C2_DDR3_BANK_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="3" spirit:rangeType="long">3</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C2_DDR3_CK_WIDTH</spirit:name>
        <spirit:displayName>clock width</spirit:displayName>
        <spirit:description>clock width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C2_DDR3_CK_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="4" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C2_DDR3_CKE_WIDTH</spirit:name>
        <spirit:displayName>clock enable width</spirit:displayName>
        <spirit:description>clock enable width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C2_DDR3_CKE_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="2" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C2_DDR3_CS_WIDTH</spirit:name>
        <spirit:displayName>chip select width</spirit:displayName>
        <spirit:description>chip select width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C2_DDR3_CS_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="2" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C2_DDR3_nCS_PER_RANK</spirit:name>
        <spirit:displayName>chip select per rank</spirit:displayName>
        <spirit:description>chip select per rank</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C2_DDR3_nCS_PER_RANK" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="4" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C2_DDR3_DM_WIDTH</spirit:name>
        <spirit:displayName>data mask width</spirit:displayName>
        <spirit:description>data mask width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C2_DDR3_DM_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="9" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C2_DDR3_ODT_WIDTH</spirit:name>
        <spirit:displayName>odt width</spirit:displayName>
        <spirit:description>odt width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C2_DDR3_ODT_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="4" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C2_DDR3_USE_CS_PORT</spirit:name>
        <spirit:displayName>CS Port is in use</spirit:displayName>
        <spirit:description>CS Port is in use</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C2_DDR3_USE_CS_PORT" spirit:configGroups="default" spirit:minimum="0" spirit:maximum="1" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C2_DDR3_USE_DM_PORT</spirit:name>
        <spirit:displayName>DM Port is in use</spirit:displayName>
        <spirit:description>DM Port is in use</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C2_DDR3_USE_DM_PORT" spirit:configGroups="default" spirit:minimum="0" spirit:maximum="1" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C2_DDR3_USE_ODT_PORT</spirit:name>
        <spirit:displayName>ODT Port is in use</spirit:displayName>
        <spirit:description>ODT Port is in use</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C2_DDR3_USE_ODT_PORT" spirit:configGroups="default" spirit:minimum="0" spirit:maximum="1" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="string">
        <spirit:name>C2_DDR3_REG_CTRL</spirit:name>
        <spirit:displayName>Indicates Registered DIMM or not</spirit:displayName>
        <spirit:description>Indicates Registered DIMM or not</spirit:description>
        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C2_DDR3_REG_CTRL" spirit:choiceRef="choice_list_dc86ec6e" spirit:configGroups="default">OFF</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C2_DDR3_DQS_CNT_WIDTH</spirit:name>
        <spirit:displayName>DQS count width</spirit:displayName>
        <spirit:description>DQS count width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C2_DDR3_DQS_CNT_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="8" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="string">
        <spirit:name>C2_DDR3_DEBUG_PORT</spirit:name>
        <spirit:displayName>Debug Port enable info</spirit:displayName>
        <spirit:description>Debug Port enable info</spirit:description>
        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C2_DDR3_DEBUG_PORT" spirit:choiceRef="choice_list_dc86ec6e" spirit:configGroups="default">OFF</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C2_DDR2_DQ_WIDTH</spirit:name>
        <spirit:displayName>data bus width</spirit:displayName>
        <spirit:description>data bus width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C2_DDR2_DQ_WIDTH" spirit:choiceRef="choice_list_bdb560e1" spirit:configGroups="default">8</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C2_DDR2_DQS_WIDTH</spirit:name>
        <spirit:displayName>data strobe width</spirit:displayName>
        <spirit:description>data strobe width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C2_DDR2_DQS_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="9" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C2_DDR2_ROW_WIDTH</spirit:name>
        <spirit:displayName>row width</spirit:displayName>
        <spirit:description>row width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C2_DDR2_ROW_WIDTH" spirit:configGroups="default" spirit:minimum="13" spirit:maximum="16" spirit:rangeType="long">14</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C2_DDR2_BANK_WIDTH</spirit:name>
        <spirit:displayName>bank width</spirit:displayName>
        <spirit:description>bank width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C2_DDR2_BANK_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="3" spirit:rangeType="long">3</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C2_DDR2_CK_WIDTH</spirit:name>
        <spirit:displayName>clock width</spirit:displayName>
        <spirit:description>clock width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C2_DDR2_CK_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="4" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C2_DDR2_CKE_WIDTH</spirit:name>
        <spirit:displayName>clock enable width</spirit:displayName>
        <spirit:description>clock enable width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C2_DDR2_CKE_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="2" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C2_DDR2_CS_WIDTH</spirit:name>
        <spirit:displayName>chip select width</spirit:displayName>
        <spirit:description>chip select width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C2_DDR2_CS_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="2" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C2_DDR2_nCS_PER_RANK</spirit:name>
        <spirit:displayName>chip select per rank</spirit:displayName>
        <spirit:description>chip select per rank</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C2_DDR2_nCS_PER_RANK" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="4" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C2_DDR2_DM_WIDTH</spirit:name>
        <spirit:displayName>data mask width</spirit:displayName>
        <spirit:description>data mask width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C2_DDR2_DM_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="9" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C2_DDR2_ODT_WIDTH</spirit:name>
        <spirit:displayName>odt width</spirit:displayName>
        <spirit:description>odt width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C2_DDR2_ODT_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="4" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C2_DDR2_USE_CS_PORT</spirit:name>
        <spirit:displayName>CS Port is in use</spirit:displayName>
        <spirit:description>CS Port is in use</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C2_DDR2_USE_CS_PORT" spirit:configGroups="default" spirit:minimum="0" spirit:maximum="1" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C2_DDR2_USE_DM_PORT</spirit:name>
        <spirit:displayName>DM Port is in use</spirit:displayName>
        <spirit:description>DM Port is in use</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C2_DDR2_USE_DM_PORT" spirit:configGroups="default" spirit:minimum="0" spirit:maximum="1" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C2_DDR2_USE_ODT_PORT</spirit:name>
        <spirit:displayName>ODT Port is in use</spirit:displayName>
        <spirit:description>ODT Port is in use</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C2_DDR2_USE_ODT_PORT" spirit:configGroups="default" spirit:minimum="0" spirit:maximum="1" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="string">
        <spirit:name>C2_DDR2_REG_CTRL</spirit:name>
        <spirit:displayName>Indicates Registered DIMM or not</spirit:displayName>
        <spirit:description>Indicates Registered DIMM or not</spirit:description>
        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C2_DDR2_REG_CTRL" spirit:choiceRef="choice_list_dc86ec6e" spirit:configGroups="default">OFF</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C2_DDR2_DQS_CNT_WIDTH</spirit:name>
        <spirit:displayName>DQS count width</spirit:displayName>
        <spirit:description>DQS count width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C2_DDR2_DQS_CNT_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="8" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="string">
        <spirit:name>C2_DDR2_DEBUG_PORT</spirit:name>
        <spirit:displayName>Debug Port enable info</spirit:displayName>
        <spirit:description>Debug Port enable info</spirit:description>
        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C2_DDR2_DEBUG_PORT" spirit:choiceRef="choice_list_dc86ec6e" spirit:configGroups="default">OFF</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C2_LPDDR2_DQ_WIDTH</spirit:name>
        <spirit:displayName>data bus width</spirit:displayName>
        <spirit:description>data bus width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C2_LPDDR2_DQ_WIDTH" spirit:choiceRef="choice_list_bdb560e1" spirit:configGroups="default">8</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C2_LPDDR2_DQS_WIDTH</spirit:name>
        <spirit:displayName>data strobe width</spirit:displayName>
        <spirit:description>data strobe width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C2_LPDDR2_DQS_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="9" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C2_LPDDR2_ROW_WIDTH</spirit:name>
        <spirit:displayName>row width</spirit:displayName>
        <spirit:description>row width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C2_LPDDR2_ROW_WIDTH" spirit:configGroups="default" spirit:minimum="12" spirit:maximum="16" spirit:rangeType="long">14</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C2_LPDDR2_BANK_WIDTH</spirit:name>
        <spirit:displayName>bank width</spirit:displayName>
        <spirit:description>bank width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C2_LPDDR2_BANK_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="3" spirit:rangeType="long">3</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C2_LPDDR2_CK_WIDTH</spirit:name>
        <spirit:displayName>clock width</spirit:displayName>
        <spirit:description>clock width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C2_LPDDR2_CK_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="4" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C2_LPDDR2_CKE_WIDTH</spirit:name>
        <spirit:displayName>clock enable width</spirit:displayName>
        <spirit:description>clock enable width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C2_LPDDR2_CKE_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="2" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C2_LPDDR2_CS_WIDTH</spirit:name>
        <spirit:displayName>chip select width</spirit:displayName>
        <spirit:description>chip select width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C2_LPDDR2_CS_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="2" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C2_LPDDR2_nCS_PER_RANK</spirit:name>
        <spirit:displayName>chip select per rank</spirit:displayName>
        <spirit:description>chip select per rank</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C2_LPDDR2_nCS_PER_RANK" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="4" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C2_LPDDR2_DM_WIDTH</spirit:name>
        <spirit:displayName>data mask width</spirit:displayName>
        <spirit:description>data mask width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C2_LPDDR2_DM_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="9" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C2_LPDDR2_USE_CS_PORT</spirit:name>
        <spirit:displayName>CS Port is in use</spirit:displayName>
        <spirit:description>CS Port is in use</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C2_LPDDR2_USE_CS_PORT" spirit:configGroups="default" spirit:minimum="0" spirit:maximum="1" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C2_LPDDR2_USE_DM_PORT</spirit:name>
        <spirit:displayName>DM Port is in use</spirit:displayName>
        <spirit:description>DM Port is in use</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C2_LPDDR2_USE_DM_PORT" spirit:configGroups="default" spirit:minimum="0" spirit:maximum="1" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C2_LPDDR2_USE_ODT_PORT</spirit:name>
        <spirit:displayName>ODT Port is in use</spirit:displayName>
        <spirit:description>ODT Port is in use</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C2_LPDDR2_USE_ODT_PORT" spirit:configGroups="default" spirit:minimum="0" spirit:maximum="1" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="string">
        <spirit:name>C2_LPDDR2_REG_CTRL</spirit:name>
        <spirit:displayName>Indicates Registered DIMM or not</spirit:displayName>
        <spirit:description>Indicates Registered DIMM or not</spirit:description>
        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C2_LPDDR2_REG_CTRL" spirit:choiceRef="choice_list_dc86ec6e" spirit:configGroups="default">OFF</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C2_LPDDR2_DQS_CNT_WIDTH</spirit:name>
        <spirit:displayName>DQS count width</spirit:displayName>
        <spirit:description>DQS count width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C2_LPDDR2_DQS_CNT_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="8" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="string">
        <spirit:name>C2_LPDDR2_DEBUG_PORT</spirit:name>
        <spirit:displayName>Debug Port enable info</spirit:displayName>
        <spirit:description>Debug Port enable info</spirit:description>
        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C2_LPDDR2_DEBUG_PORT" spirit:choiceRef="choice_list_dc86ec6e" spirit:configGroups="default">OFF</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C2_DQS_CNT_WIDTH</spirit:name>
        <spirit:displayName>DQS count width</spirit:displayName>
        <spirit:description>DQS count width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C2_DQS_CNT_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="8" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="string">
        <spirit:name>C2_DEBUG_PORT</spirit:name>
        <spirit:displayName>Debug Port enable info</spirit:displayName>
        <spirit:description>Debug Port enable info</spirit:description>
        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C2_DEBUG_PORT" spirit:choiceRef="choice_list_dc86ec6e" spirit:configGroups="default">OFF</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C2_DDRX_ADDR_WIDTH</spirit:name>
        <spirit:displayName>addr width</spirit:displayName>
        <spirit:description>addr width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C2_DDRX_ADDR_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="32" spirit:rangeType="long">8</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C2_DDRX_nCK_PER_CLK</spirit:name>
        <spirit:displayName>nck per clk</spirit:displayName>
        <spirit:description>nck per clk</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C2_DDRX_nCK_PER_CLK" spirit:configGroups="default" spirit:minimum="0" spirit:maximum="4" spirit:rangeType="long">2</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C2_DDRX_DATA_WIDTH</spirit:name>
        <spirit:displayName>datawidth excluding the ECC</spirit:displayName>
        <spirit:description>datawidth excluding the ECC</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C2_DDRX_DATA_WIDTH" spirit:configGroups="default" spirit:minimum="8" spirit:maximum="72" spirit:rangeType="long">8</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C2_DDR3_ADDR_WIDTH</spirit:name>
        <spirit:displayName>addr width</spirit:displayName>
        <spirit:description>addr width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C2_DDR3_ADDR_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="32" spirit:rangeType="long">8</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C2_DDR3_nCK_PER_CLK</spirit:name>
        <spirit:displayName>nck per clk</spirit:displayName>
        <spirit:description>nck per clk</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C2_DDR3_nCK_PER_CLK" spirit:configGroups="default" spirit:minimum="0" spirit:maximum="4" spirit:rangeType="long">2</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C2_DDR3_DATA_WIDTH</spirit:name>
        <spirit:displayName>datawidth excluding the ECC</spirit:displayName>
        <spirit:description>datawidth excluding the ECC</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C2_DDR3_DATA_WIDTH" spirit:configGroups="default" spirit:minimum="8" spirit:maximum="72" spirit:rangeType="long">8</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C2_DDR2_ADDR_WIDTH</spirit:name>
        <spirit:displayName>addr width</spirit:displayName>
        <spirit:description>addr width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C2_DDR2_ADDR_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="32" spirit:rangeType="long">8</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C2_DDR2_nCK_PER_CLK</spirit:name>
        <spirit:displayName>nck per clk</spirit:displayName>
        <spirit:description>nck per clk</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C2_DDR2_nCK_PER_CLK" spirit:configGroups="default" spirit:minimum="0" spirit:maximum="4" spirit:rangeType="long">2</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C2_DDR2_DATA_WIDTH</spirit:name>
        <spirit:displayName>datawidth excluding the ECC</spirit:displayName>
        <spirit:description>datawidth excluding the ECC</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C2_DDR2_DATA_WIDTH" spirit:configGroups="default" spirit:minimum="8" spirit:maximum="72" spirit:rangeType="long">8</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C2_LPDDR2_ADDR_WIDTH</spirit:name>
        <spirit:displayName>addr width</spirit:displayName>
        <spirit:description>addr width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C2_LPDDR2_ADDR_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="32" spirit:rangeType="long">8</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C2_LPDDR2_nCK_PER_CLK</spirit:name>
        <spirit:displayName>nck per clk</spirit:displayName>
        <spirit:description>nck per clk</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C2_LPDDR2_nCK_PER_CLK" spirit:configGroups="default" spirit:minimum="0" spirit:maximum="4" spirit:rangeType="long">2</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C2_LPDDR2_DATA_WIDTH</spirit:name>
        <spirit:displayName>datawidth excluding the ECC</spirit:displayName>
        <spirit:description>datawidth excluding the ECC</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C2_LPDDR2_DATA_WIDTH" spirit:configGroups="default" spirit:minimum="8" spirit:maximum="72" spirit:rangeType="long">8</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="float">
        <spirit:name>C2_FREQ_HZ</spirit:name>
        <spirit:displayName>defines the UI Clk freq</spirit:displayName>
        <spirit:description>defines the UI Clk freq</spirit:description>
        <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C2_FREQ_HZ" spirit:configGroups="default" spirit:minimum="0.0" spirit:maximum="800000000.0" spirit:rangeType="long">100.0</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="float">
        <spirit:name>C2_PHASE</spirit:name>
        <spirit:displayName>defines the UI Clk phase</spirit:displayName>
        <spirit:description>defines the UI Clk phase</spirit:description>
        <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C2_PHASE" spirit:choiceRef="choice_list_c7c132f6" spirit:configGroups="default">0.000</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="string">
        <spirit:name>C2_UI_EXTRA_CLOCKS</spirit:name>
        <spirit:displayName>Enablement of extra clocks</spirit:displayName>
        <spirit:description>Enablement of extra clocks</spirit:description>
        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C2_UI_EXTRA_CLOCKS" spirit:choiceRef="choice_list_d10f4555" spirit:configGroups="default">FALSE</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="float">
        <spirit:name>C2_MMCM_VCO</spirit:name>
        <spirit:displayName>Max possible VCO of MMCM primitive </spirit:displayName>
        <spirit:description>Max possible VCO of MMCM primitive </spirit:description>
        <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C2_MMCM_VCO" spirit:configGroups="default" spirit:minimum="600.0" spirit:maximum="1600.0" spirit:rangeType="long">1200.0</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="float">
        <spirit:name>C2_MMCM_CLKOUT0_FREQ</spirit:name>
        <spirit:displayName>mmcm extra clkout0</spirit:displayName>
        <spirit:description>mmcm extra clkout0</spirit:description>
        <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C2_MMCM_CLKOUT0_FREQ" spirit:configGroups="default" spirit:minimum="0.0" spirit:maximum="800000000.0" spirit:rangeType="long">10.0</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C2_MMCM_CLKOUT1_FREQ</spirit:name>
        <spirit:displayName>mmcm extra clkout1</spirit:displayName>
        <spirit:description>mmcm extra clkout1</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C2_MMCM_CLKOUT1_FREQ" spirit:configGroups="default" spirit:minimum="0.0" spirit:maximum="800000000" spirit:rangeType="long">10</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C2_MMCM_CLKOUT2_FREQ</spirit:name>
        <spirit:displayName>mmcm extra clkout2</spirit:displayName>
        <spirit:description>mmcm extra clkout2</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C2_MMCM_CLKOUT2_FREQ" spirit:configGroups="default" spirit:minimum="0.0" spirit:maximum="800000000" spirit:rangeType="long">10</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C2_MMCM_CLKOUT3_FREQ</spirit:name>
        <spirit:displayName>mmcm extra clkout3</spirit:displayName>
        <spirit:description>mmcm extra clkout3</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C2_MMCM_CLKOUT3_FREQ" spirit:configGroups="default" spirit:minimum="0.0" spirit:maximum="800000000" spirit:rangeType="long">10</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C2_MMCM_CLKOUT4_FREQ</spirit:name>
        <spirit:displayName>mmcm extra clkout4</spirit:displayName>
        <spirit:description>mmcm extra clkout4</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C2_MMCM_CLKOUT4_FREQ" spirit:configGroups="default" spirit:minimum="0.0" spirit:maximum="800000000" spirit:rangeType="long">10</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="string">
        <spirit:name>C2_MMCM_CLKOUT0_EN</spirit:name>
        <spirit:displayName>Indicates Enablement of CLKOUT0</spirit:displayName>
        <spirit:description>Indicates Enablement of CLKOUT0</spirit:description>
        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C2_MMCM_CLKOUT0_EN" spirit:choiceRef="choice_list_e7c484ae" spirit:configGroups="default">FALSE</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="string">
        <spirit:name>C2_MMCM_CLKOUT2_EN</spirit:name>
        <spirit:displayName>Indicates Enablement of CLKOUT2</spirit:displayName>
        <spirit:description>Indicates Enablement of CLKOUT2</spirit:description>
        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C2_MMCM_CLKOUT2_EN" spirit:choiceRef="choice_list_e7c484ae" spirit:configGroups="default">FALSE</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="string">
        <spirit:name>C2_MMCM_CLKOUT1_EN</spirit:name>
        <spirit:displayName>Indicates Enablement of CLKOUT1</spirit:displayName>
        <spirit:description>Indicates Enablement of CLKOUT1</spirit:description>
        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C2_MMCM_CLKOUT1_EN" spirit:choiceRef="choice_list_e7c484ae" spirit:configGroups="default">FALSE</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="string">
        <spirit:name>C2_MMCM_CLKOUT3_EN</spirit:name>
        <spirit:displayName>Indicates Enablement of CLKOUT3</spirit:displayName>
        <spirit:description>Indicates Enablement of CLKOUT3</spirit:description>
        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C2_MMCM_CLKOUT3_EN" spirit:choiceRef="choice_list_e7c484ae" spirit:configGroups="default">FALSE</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="string">
        <spirit:name>C2_MMCM_CLKOUT4_EN</spirit:name>
        <spirit:displayName>Indicates Enablement of CLKOUT4</spirit:displayName>
        <spirit:description>Indicates Enablement of CLKOUT4</spirit:description>
        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C2_MMCM_CLKOUT4_EN" spirit:choiceRef="choice_list_e7c484ae" spirit:configGroups="default">FALSE</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C2_C_S_AXI_CTRL_ID_WIDTH</spirit:name>
        <spirit:displayName>AXI ID Width</spirit:displayName>
        <spirit:description>AXI ID Width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C2_C_S_AXI_CTRL_ID_WIDTH" spirit:configGroups="default" spirit:minimum="0" spirit:maximum="16" spirit:rangeType="long">4</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C2_C_S_AXI_CTRL_DATA_WIDTH</spirit:name>
        <spirit:displayName>AXI Data Width</spirit:displayName>
        <spirit:description>AXI Data Width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C2_C_S_AXI_CTRL_DATA_WIDTH" spirit:choiceRef="choice_list_40181835" spirit:configGroups="default">32</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C2_C_S_AXI_CTRL_ADDR_WIDTH</spirit:name>
        <spirit:displayName>AXI Addr Width</spirit:displayName>
        <spirit:description>AXI Addr Width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C2_C_S_AXI_CTRL_ADDR_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="36" spirit:rangeType="long">32</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C2_C_S_AXI_CTRL_MEM_SIZE</spirit:name>
        <spirit:displayName>Memory Address Space</spirit:displayName>
        <spirit:description>Memory Address Space</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C2_C_S_AXI_CTRL_MEM_SIZE" spirit:configGroups="default" spirit:minimum="0" spirit:maximum="34359738368" spirit:rangeType="long">1048576</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C2_C_S_AXI_ID_WIDTH</spirit:name>
        <spirit:displayName>AXI ID Width</spirit:displayName>
        <spirit:description>AXI ID Width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C2_C_S_AXI_ID_WIDTH" spirit:configGroups="default" spirit:minimum="0" spirit:maximum="16" spirit:rangeType="long">4</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C2_C_S_AXI_DATA_WIDTH</spirit:name>
        <spirit:displayName>AXI Data Width</spirit:displayName>
        <spirit:description>AXI Data Width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C2_C_S_AXI_DATA_WIDTH" spirit:choiceRef="choice_list_40181835" spirit:configGroups="default">32</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C2_C_S_AXI_ADDR_WIDTH</spirit:name>
        <spirit:displayName>AXI Addr Width</spirit:displayName>
        <spirit:description>AXI Addr Width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C2_C_S_AXI_ADDR_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="36" spirit:rangeType="long">32</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C2_C_S_AXI_MEM_SIZE</spirit:name>
        <spirit:displayName>Memory Address Space</spirit:displayName>
        <spirit:description>Memory Address Space</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C2_C_S_AXI_MEM_SIZE" spirit:configGroups="default" spirit:minimum="0" spirit:maximum="34359738368" spirit:rangeType="long">1048576</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C2_QDRIIP_NUM_DEVICES</spirit:name>
        <spirit:displayName>num devices</spirit:displayName>
        <spirit:description>num devices</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C2_QDRIIP_NUM_DEVICES" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="4" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C2_QDRIIP_DATA_WIDTH</spirit:name>
        <spirit:displayName>data width</spirit:displayName>
        <spirit:description>data width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C2_QDRIIP_DATA_WIDTH" spirit:choiceRef="choice_list_cf6acb30" spirit:configGroups="default">18</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C2_QDRIIP_ADDR_WIDTH</spirit:name>
        <spirit:displayName>addr width </spirit:displayName>
        <spirit:description>addr width </spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C2_QDRIIP_ADDR_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="32" spirit:rangeType="long">29</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C2_QDRIIP_BW_WIDTH</spirit:name>
        <spirit:displayName>bw width </spirit:displayName>
        <spirit:description>bw width </spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C2_QDRIIP_BW_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="8" spirit:rangeType="long">8</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="string">
        <spirit:name>C2_QDRIIP_DEBUG_PORT</spirit:name>
        <spirit:displayName>Debug Port enable info</spirit:displayName>
        <spirit:description>Debug Port enable info</spirit:description>
        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C2_QDRIIP_DEBUG_PORT" spirit:choiceRef="choice_list_dc86ec6e" spirit:configGroups="default">OFF</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C2_QDRIIP_BURST_LEN</spirit:name>
        <spirit:displayName>burst len </spirit:displayName>
        <spirit:description>burst len </spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C2_QDRIIP_BURST_LEN" spirit:choiceRef="choice_list_dd2843c6" spirit:configGroups="default">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C2_RLDII_NUM_DEVICES</spirit:name>
        <spirit:displayName>num devices</spirit:displayName>
        <spirit:description>num devices</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C2_RLDII_NUM_DEVICES" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="4" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C2_RLDII_DATA_WIDTH</spirit:name>
        <spirit:displayName>data width</spirit:displayName>
        <spirit:description>data width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C2_RLDII_DATA_WIDTH" spirit:choiceRef="choice_list_cf6acb30" spirit:configGroups="default">18</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C2_RLDII_RLD_ADDR_WIDTH</spirit:name>
        <spirit:displayName>rld addr width </spirit:displayName>
        <spirit:description>rld addr width </spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C2_RLDII_RLD_ADDR_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="32" spirit:rangeType="long">29</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C2_RLDII_QK_WIDTH</spirit:name>
        <spirit:displayName>qk width </spirit:displayName>
        <spirit:description>qk width </spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C2_RLDII_QK_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="8" spirit:rangeType="long">8</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C2_RLDII_CK_WIDTH</spirit:name>
        <spirit:displayName>ck width </spirit:displayName>
        <spirit:description>ck width </spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C2_RLDII_CK_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="4" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C2_RLDII_DK_WIDTH</spirit:name>
        <spirit:displayName>dk width </spirit:displayName>
        <spirit:description>dk width </spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C2_RLDII_DK_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="4" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C2_RLDII_DM_WIDTH</spirit:name>
        <spirit:displayName>dm width </spirit:displayName>
        <spirit:description>dm width </spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C2_RLDII_DM_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="4" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C2_RLDII_BANK_WIDTH</spirit:name>
        <spirit:displayName>bank width </spirit:displayName>
        <spirit:description>bank width </spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C2_RLDII_BANK_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="4" spirit:rangeType="long">2</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C2_RLDII_QVLD_WIDTH</spirit:name>
        <spirit:displayName>qvld width </spirit:displayName>
        <spirit:description>qvld width </spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C2_RLDII_QVLD_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="4" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="string">
        <spirit:name>C2_RLDII_DEBUG_PORT</spirit:name>
        <spirit:displayName>Debug Port enable info</spirit:displayName>
        <spirit:description>Debug Port enable info</spirit:description>
        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C2_RLDII_DEBUG_PORT" spirit:choiceRef="choice_list_dc86ec6e" spirit:configGroups="default">OFF</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C2_RLDIII_NUM_DEVICES</spirit:name>
        <spirit:displayName>num devices</spirit:displayName>
        <spirit:description>num devices</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C2_RLDIII_NUM_DEVICES" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="4" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C2_RLDIII_DATA_WIDTH</spirit:name>
        <spirit:displayName>data width</spirit:displayName>
        <spirit:description>data width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C2_RLDIII_DATA_WIDTH" spirit:choiceRef="choice_list_cf6acb30" spirit:configGroups="default">18</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C2_RLDIII_RLD_ADDR_WIDTH</spirit:name>
        <spirit:displayName>rld addr width </spirit:displayName>
        <spirit:description>rld addr width </spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C2_RLDIII_RLD_ADDR_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="32" spirit:rangeType="long">29</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C2_RLDIII_QK_WIDTH</spirit:name>
        <spirit:displayName>qk width </spirit:displayName>
        <spirit:description>qk width </spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C2_RLDIII_QK_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="8" spirit:rangeType="long">8</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C2_RLDIII_CK_WIDTH</spirit:name>
        <spirit:displayName>ck width </spirit:displayName>
        <spirit:description>ck width </spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C2_RLDIII_CK_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="4" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C2_RLDIII_DK_WIDTH</spirit:name>
        <spirit:displayName>dk width </spirit:displayName>
        <spirit:description>dk width </spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C2_RLDIII_DK_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="4" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C2_RLDIII_DM_WIDTH</spirit:name>
        <spirit:displayName>dm width </spirit:displayName>
        <spirit:description>dm width </spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C2_RLDIII_DM_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="4" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C2_RLDIII_BANK_WIDTH</spirit:name>
        <spirit:displayName>bank width </spirit:displayName>
        <spirit:description>bank width </spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C2_RLDIII_BANK_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="4" spirit:rangeType="long">2</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C2_RLDIII_QVLD_WIDTH</spirit:name>
        <spirit:displayName>qvld width </spirit:displayName>
        <spirit:description>qvld width </spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C2_RLDIII_QVLD_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="4" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="string">
        <spirit:name>C2_RLDIII_DEBUG_PORT</spirit:name>
        <spirit:displayName>Debug Port enable info</spirit:displayName>
        <spirit:description>Debug Port enable info</spirit:description>
        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C2_RLDIII_DEBUG_PORT" spirit:choiceRef="choice_list_dc86ec6e" spirit:configGroups="default">OFF</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C2_RLDX_CMD_PER_CLK</spirit:name>
        <spirit:displayName>cmd per clock</spirit:displayName>
        <spirit:description>cmd per clock</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C2_RLDX_CMD_PER_CLK" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="4" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C2_RLDX_DATA_WIDTH</spirit:name>
        <spirit:displayName>data width</spirit:displayName>
        <spirit:description>data width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C2_RLDX_DATA_WIDTH" spirit:choiceRef="choice_list_cf6acb30" spirit:configGroups="default">18</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C2_RLDX_ADDR_WIDTH</spirit:name>
        <spirit:displayName>addr width </spirit:displayName>
        <spirit:description>addr width </spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C2_RLDX_ADDR_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="32" spirit:rangeType="long">29</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C2_RLDX_BANK_WIDTH</spirit:name>
        <spirit:displayName>bank width </spirit:displayName>
        <spirit:description>bank width </spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C2_RLDX_BANK_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="4" spirit:rangeType="long">2</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C2_RLDX_nCK_PER_CLK</spirit:name>
        <spirit:displayName>nCk per clock</spirit:displayName>
        <spirit:description>nCk per clock</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C2_RLDX_nCK_PER_CLK" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="4" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C2_RLDX_DM_WIDTH</spirit:name>
        <spirit:displayName>dm width </spirit:displayName>
        <spirit:description>dm width </spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C2_RLDX_DM_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="4" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C2_RLDII_CMD_PER_CLK</spirit:name>
        <spirit:displayName>cmd per clock</spirit:displayName>
        <spirit:description>cmd per clock</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C2_RLDII_CMD_PER_CLK" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="4" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C2_RLDII_ADDR_WIDTH</spirit:name>
        <spirit:displayName>addr width </spirit:displayName>
        <spirit:description>addr width </spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C2_RLDII_ADDR_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="32" spirit:rangeType="long">29</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C2_RLDII_nCK_PER_CLK</spirit:name>
        <spirit:displayName>nCk per clock</spirit:displayName>
        <spirit:description>nCk per clock</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C2_RLDII_nCK_PER_CLK" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="4" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C2_RLDIII_CMD_PER_CLK</spirit:name>
        <spirit:displayName>cmd per clock</spirit:displayName>
        <spirit:description>cmd per clock</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C2_RLDIII_CMD_PER_CLK" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="4" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C2_RLDIII_ADDR_WIDTH</spirit:name>
        <spirit:displayName>addr width </spirit:displayName>
        <spirit:description>addr width </spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C2_RLDIII_ADDR_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="32" spirit:rangeType="long">29</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C2_RLDIII_nCK_PER_CLK</spirit:name>
        <spirit:displayName>nCk per clock</spirit:displayName>
        <spirit:description>nCk per clock</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C2_RLDIII_nCK_PER_CLK" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="4" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="string">
        <spirit:name>C2_POLARITY</spirit:name>
        <spirit:displayName>Polarity of the value</spirit:displayName>
        <spirit:description>Polarity of the value</spirit:description>
        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C2_POLARITY" spirit:choiceRef="choice_list_6eff49bd" spirit:configGroups="default">ACTIVE_LOW</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="string">
        <spirit:name>C3_MEM_TYPE</spirit:name>
        <spirit:displayName>identify interface</spirit:displayName>
        <spirit:description>identify interface</spirit:description>
        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C3_MEM_TYPE" spirit:choiceRef="choice_list_b54243b1" spirit:configGroups="default">DDR3</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="string">
        <spirit:name>C3_IS_CLK_SHARED</spirit:name>
        <spirit:displayName>is clk shared</spirit:displayName>
        <spirit:description>is clk shared</spirit:description>
        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C3_IS_CLK_SHARED" spirit:choiceRef="choice_list_d10f4555" spirit:configGroups="default">FALSE</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="string">
        <spirit:name>C3_SYSCLK_TYPE</spirit:name>
        <spirit:displayName>Type of sys clk</spirit:displayName>
        <spirit:description>Type of sys clk</spirit:description>
        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C3_SYSCLK_TYPE" spirit:choiceRef="choice_list_1570a756" spirit:configGroups="default">DIFF</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C3_USE_AXI</spirit:name>
        <spirit:displayName>USE AXI</spirit:displayName>
        <spirit:description>USE AXI</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C3_USE_AXI" spirit:configGroups="default" spirit:minimum="0" spirit:maximum="1" spirit:rangeType="long">0</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="string">
        <spirit:name>C3_ECC</spirit:name>
        <spirit:displayName>ecc enable info</spirit:displayName>
        <spirit:description>ecc enable info</spirit:description>
        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C3_ECC" spirit:choiceRef="choice_list_dc86ec6e" spirit:configGroups="default">OFF</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C3_DDR3_DQ_WIDTH</spirit:name>
        <spirit:displayName>data bus width</spirit:displayName>
        <spirit:description>data bus width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C3_DDR3_DQ_WIDTH" spirit:choiceRef="choice_list_bdb560e1" spirit:configGroups="default">8</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C3_DDR3_DQS_WIDTH</spirit:name>
        <spirit:displayName>data strobe width</spirit:displayName>
        <spirit:description>data strobe width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C3_DDR3_DQS_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="9" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C3_DDR3_ROW_WIDTH</spirit:name>
        <spirit:displayName>row width</spirit:displayName>
        <spirit:description>row width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C3_DDR3_ROW_WIDTH" spirit:configGroups="default" spirit:minimum="13" spirit:maximum="16" spirit:rangeType="long">14</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C3_DDR3_BANK_WIDTH</spirit:name>
        <spirit:displayName>bank width</spirit:displayName>
        <spirit:description>bank width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C3_DDR3_BANK_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="3" spirit:rangeType="long">3</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C3_DDR3_CK_WIDTH</spirit:name>
        <spirit:displayName>clock width</spirit:displayName>
        <spirit:description>clock width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C3_DDR3_CK_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="4" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C3_DDR3_CKE_WIDTH</spirit:name>
        <spirit:displayName>clock enable width</spirit:displayName>
        <spirit:description>clock enable width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C3_DDR3_CKE_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="2" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C3_DDR3_CS_WIDTH</spirit:name>
        <spirit:displayName>chip select width</spirit:displayName>
        <spirit:description>chip select width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C3_DDR3_CS_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="2" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C3_DDR3_nCS_PER_RANK</spirit:name>
        <spirit:displayName>chip select per rank</spirit:displayName>
        <spirit:description>chip select per rank</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C3_DDR3_nCS_PER_RANK" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="4" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C3_DDR3_DM_WIDTH</spirit:name>
        <spirit:displayName>data mask width</spirit:displayName>
        <spirit:description>data mask width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C3_DDR3_DM_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="9" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C3_DDR3_ODT_WIDTH</spirit:name>
        <spirit:displayName>odt width</spirit:displayName>
        <spirit:description>odt width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C3_DDR3_ODT_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="4" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C3_DDR3_USE_CS_PORT</spirit:name>
        <spirit:displayName>CS Port is in use</spirit:displayName>
        <spirit:description>CS Port is in use</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C3_DDR3_USE_CS_PORT" spirit:configGroups="default" spirit:minimum="0" spirit:maximum="1" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C3_DDR3_USE_DM_PORT</spirit:name>
        <spirit:displayName>DM Port is in use</spirit:displayName>
        <spirit:description>DM Port is in use</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C3_DDR3_USE_DM_PORT" spirit:configGroups="default" spirit:minimum="0" spirit:maximum="1" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C3_DDR3_USE_ODT_PORT</spirit:name>
        <spirit:displayName>ODT Port is in use</spirit:displayName>
        <spirit:description>ODT Port is in use</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C3_DDR3_USE_ODT_PORT" spirit:configGroups="default" spirit:minimum="0" spirit:maximum="1" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="string">
        <spirit:name>C3_DDR3_REG_CTRL</spirit:name>
        <spirit:displayName>Indicates Registered DIMM or not</spirit:displayName>
        <spirit:description>Indicates Registered DIMM or not</spirit:description>
        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C3_DDR3_REG_CTRL" spirit:choiceRef="choice_list_dc86ec6e" spirit:configGroups="default">OFF</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C3_DDR3_DQS_CNT_WIDTH</spirit:name>
        <spirit:displayName>DQS count width</spirit:displayName>
        <spirit:description>DQS count width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C3_DDR3_DQS_CNT_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="8" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="string">
        <spirit:name>C3_DDR3_DEBUG_PORT</spirit:name>
        <spirit:displayName>Debug Port enable info</spirit:displayName>
        <spirit:description>Debug Port enable info</spirit:description>
        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C3_DDR3_DEBUG_PORT" spirit:choiceRef="choice_list_dc86ec6e" spirit:configGroups="default">OFF</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C3_DDR2_DQ_WIDTH</spirit:name>
        <spirit:displayName>data bus width</spirit:displayName>
        <spirit:description>data bus width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C3_DDR2_DQ_WIDTH" spirit:choiceRef="choice_list_bdb560e1" spirit:configGroups="default">8</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C3_DDR2_DQS_WIDTH</spirit:name>
        <spirit:displayName>data strobe width</spirit:displayName>
        <spirit:description>data strobe width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C3_DDR2_DQS_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="9" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C3_DDR2_ROW_WIDTH</spirit:name>
        <spirit:displayName>row width</spirit:displayName>
        <spirit:description>row width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C3_DDR2_ROW_WIDTH" spirit:configGroups="default" spirit:minimum="13" spirit:maximum="16" spirit:rangeType="long">14</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C3_DDR2_BANK_WIDTH</spirit:name>
        <spirit:displayName>bank width</spirit:displayName>
        <spirit:description>bank width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C3_DDR2_BANK_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="3" spirit:rangeType="long">3</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C3_DDR2_CK_WIDTH</spirit:name>
        <spirit:displayName>clock width</spirit:displayName>
        <spirit:description>clock width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C3_DDR2_CK_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="4" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C3_DDR2_CKE_WIDTH</spirit:name>
        <spirit:displayName>clock enable width</spirit:displayName>
        <spirit:description>clock enable width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C3_DDR2_CKE_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="2" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C3_DDR2_CS_WIDTH</spirit:name>
        <spirit:displayName>chip select width</spirit:displayName>
        <spirit:description>chip select width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C3_DDR2_CS_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="2" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C3_DDR2_nCS_PER_RANK</spirit:name>
        <spirit:displayName>chip select per rank</spirit:displayName>
        <spirit:description>chip select per rank</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C3_DDR2_nCS_PER_RANK" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="4" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C3_DDR2_DM_WIDTH</spirit:name>
        <spirit:displayName>data mask width</spirit:displayName>
        <spirit:description>data mask width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C3_DDR2_DM_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="9" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C3_DDR2_ODT_WIDTH</spirit:name>
        <spirit:displayName>odt width</spirit:displayName>
        <spirit:description>odt width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C3_DDR2_ODT_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="4" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C3_DDR2_USE_CS_PORT</spirit:name>
        <spirit:displayName>CS Port is in use</spirit:displayName>
        <spirit:description>CS Port is in use</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C3_DDR2_USE_CS_PORT" spirit:configGroups="default" spirit:minimum="0" spirit:maximum="1" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C3_DDR2_USE_DM_PORT</spirit:name>
        <spirit:displayName>DM Port is in use</spirit:displayName>
        <spirit:description>DM Port is in use</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C3_DDR2_USE_DM_PORT" spirit:configGroups="default" spirit:minimum="0" spirit:maximum="1" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C3_DDR2_USE_ODT_PORT</spirit:name>
        <spirit:displayName>ODT Port is in use</spirit:displayName>
        <spirit:description>ODT Port is in use</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C3_DDR2_USE_ODT_PORT" spirit:configGroups="default" spirit:minimum="0" spirit:maximum="1" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="string">
        <spirit:name>C3_DDR2_REG_CTRL</spirit:name>
        <spirit:displayName>Indicates Registered DIMM or not</spirit:displayName>
        <spirit:description>Indicates Registered DIMM or not</spirit:description>
        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C3_DDR2_REG_CTRL" spirit:choiceRef="choice_list_dc86ec6e" spirit:configGroups="default">OFF</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C3_DDR2_DQS_CNT_WIDTH</spirit:name>
        <spirit:displayName>DQS count width</spirit:displayName>
        <spirit:description>DQS count width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C3_DDR2_DQS_CNT_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="8" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="string">
        <spirit:name>C3_DDR2_DEBUG_PORT</spirit:name>
        <spirit:displayName>Debug Port enable info</spirit:displayName>
        <spirit:description>Debug Port enable info</spirit:description>
        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C3_DDR2_DEBUG_PORT" spirit:choiceRef="choice_list_dc86ec6e" spirit:configGroups="default">OFF</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C3_LPDDR2_DQ_WIDTH</spirit:name>
        <spirit:displayName>data bus width</spirit:displayName>
        <spirit:description>data bus width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C3_LPDDR2_DQ_WIDTH" spirit:choiceRef="choice_list_bdb560e1" spirit:configGroups="default">8</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C3_LPDDR2_DQS_WIDTH</spirit:name>
        <spirit:displayName>data strobe width</spirit:displayName>
        <spirit:description>data strobe width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C3_LPDDR2_DQS_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="9" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C3_LPDDR2_ROW_WIDTH</spirit:name>
        <spirit:displayName>row width</spirit:displayName>
        <spirit:description>row width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C3_LPDDR2_ROW_WIDTH" spirit:configGroups="default" spirit:minimum="12" spirit:maximum="16" spirit:rangeType="long">14</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C3_LPDDR2_BANK_WIDTH</spirit:name>
        <spirit:displayName>bank width</spirit:displayName>
        <spirit:description>bank width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C3_LPDDR2_BANK_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="3" spirit:rangeType="long">3</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C3_LPDDR2_CK_WIDTH</spirit:name>
        <spirit:displayName>clock width</spirit:displayName>
        <spirit:description>clock width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C3_LPDDR2_CK_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="4" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C3_LPDDR2_CKE_WIDTH</spirit:name>
        <spirit:displayName>clock enable width</spirit:displayName>
        <spirit:description>clock enable width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C3_LPDDR2_CKE_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="2" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C3_LPDDR2_CS_WIDTH</spirit:name>
        <spirit:displayName>chip select width</spirit:displayName>
        <spirit:description>chip select width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C3_LPDDR2_CS_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="2" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C3_LPDDR2_nCS_PER_RANK</spirit:name>
        <spirit:displayName>chip select per rank</spirit:displayName>
        <spirit:description>chip select per rank</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C3_LPDDR2_nCS_PER_RANK" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="4" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C3_LPDDR2_DM_WIDTH</spirit:name>
        <spirit:displayName>data mask width</spirit:displayName>
        <spirit:description>data mask width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C3_LPDDR2_DM_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="9" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C3_LPDDR2_USE_CS_PORT</spirit:name>
        <spirit:displayName>CS Port is in use</spirit:displayName>
        <spirit:description>CS Port is in use</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C3_LPDDR2_USE_CS_PORT" spirit:configGroups="default" spirit:minimum="0" spirit:maximum="1" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C3_LPDDR2_USE_DM_PORT</spirit:name>
        <spirit:displayName>DM Port is in use</spirit:displayName>
        <spirit:description>DM Port is in use</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C3_LPDDR2_USE_DM_PORT" spirit:configGroups="default" spirit:minimum="0" spirit:maximum="1" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C3_LPDDR2_USE_ODT_PORT</spirit:name>
        <spirit:displayName>ODT Port is in use</spirit:displayName>
        <spirit:description>ODT Port is in use</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C3_LPDDR2_USE_ODT_PORT" spirit:configGroups="default" spirit:minimum="0" spirit:maximum="1" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="string">
        <spirit:name>C3_LPDDR2_REG_CTRL</spirit:name>
        <spirit:displayName>Indicates Registered DIMM or not</spirit:displayName>
        <spirit:description>Indicates Registered DIMM or not</spirit:description>
        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C3_LPDDR2_REG_CTRL" spirit:choiceRef="choice_list_dc86ec6e" spirit:configGroups="default">OFF</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C3_LPDDR2_DQS_CNT_WIDTH</spirit:name>
        <spirit:displayName>DQS count width</spirit:displayName>
        <spirit:description>DQS count width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C3_LPDDR2_DQS_CNT_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="8" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="string">
        <spirit:name>C3_LPDDR2_DEBUG_PORT</spirit:name>
        <spirit:displayName>Debug Port enable info</spirit:displayName>
        <spirit:description>Debug Port enable info</spirit:description>
        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C3_LPDDR2_DEBUG_PORT" spirit:choiceRef="choice_list_dc86ec6e" spirit:configGroups="default">OFF</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C3_DQS_CNT_WIDTH</spirit:name>
        <spirit:displayName>DQS count width</spirit:displayName>
        <spirit:description>DQS count width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C3_DQS_CNT_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="8" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="string">
        <spirit:name>C3_DEBUG_PORT</spirit:name>
        <spirit:displayName>Debug Port enable info</spirit:displayName>
        <spirit:description>Debug Port enable info</spirit:description>
        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C3_DEBUG_PORT" spirit:choiceRef="choice_list_dc86ec6e" spirit:configGroups="default">OFF</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C3_DDRX_ADDR_WIDTH</spirit:name>
        <spirit:displayName>addr width</spirit:displayName>
        <spirit:description>addr width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C3_DDRX_ADDR_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="32" spirit:rangeType="long">8</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C3_DDRX_nCK_PER_CLK</spirit:name>
        <spirit:displayName>nck per clk</spirit:displayName>
        <spirit:description>nck per clk</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C3_DDRX_nCK_PER_CLK" spirit:configGroups="default" spirit:minimum="0" spirit:maximum="4" spirit:rangeType="long">2</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C3_DDRX_DATA_WIDTH</spirit:name>
        <spirit:displayName>datawidth excluding the ECC</spirit:displayName>
        <spirit:description>datawidth excluding the ECC</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C3_DDRX_DATA_WIDTH" spirit:configGroups="default" spirit:minimum="8" spirit:maximum="72" spirit:rangeType="long">8</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C3_DDR3_ADDR_WIDTH</spirit:name>
        <spirit:displayName>addr width</spirit:displayName>
        <spirit:description>addr width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C3_DDR3_ADDR_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="32" spirit:rangeType="long">8</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C3_DDR3_nCK_PER_CLK</spirit:name>
        <spirit:displayName>nck per clk</spirit:displayName>
        <spirit:description>nck per clk</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C3_DDR3_nCK_PER_CLK" spirit:configGroups="default" spirit:minimum="0" spirit:maximum="4" spirit:rangeType="long">2</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C3_DDR3_DATA_WIDTH</spirit:name>
        <spirit:displayName>datawidth excluding the ECC</spirit:displayName>
        <spirit:description>datawidth excluding the ECC</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C3_DDR3_DATA_WIDTH" spirit:configGroups="default" spirit:minimum="8" spirit:maximum="72" spirit:rangeType="long">8</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C3_DDR2_ADDR_WIDTH</spirit:name>
        <spirit:displayName>addr width</spirit:displayName>
        <spirit:description>addr width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C3_DDR2_ADDR_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="32" spirit:rangeType="long">8</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C3_DDR2_nCK_PER_CLK</spirit:name>
        <spirit:displayName>nck per clk</spirit:displayName>
        <spirit:description>nck per clk</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C3_DDR2_nCK_PER_CLK" spirit:configGroups="default" spirit:minimum="0" spirit:maximum="4" spirit:rangeType="long">2</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C3_DDR2_DATA_WIDTH</spirit:name>
        <spirit:displayName>datawidth excluding the ECC</spirit:displayName>
        <spirit:description>datawidth excluding the ECC</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C3_DDR2_DATA_WIDTH" spirit:configGroups="default" spirit:minimum="8" spirit:maximum="72" spirit:rangeType="long">8</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C3_LPDDR2_ADDR_WIDTH</spirit:name>
        <spirit:displayName>addr width</spirit:displayName>
        <spirit:description>addr width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C3_LPDDR2_ADDR_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="32" spirit:rangeType="long">8</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C3_LPDDR2_nCK_PER_CLK</spirit:name>
        <spirit:displayName>nck per clk</spirit:displayName>
        <spirit:description>nck per clk</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C3_LPDDR2_nCK_PER_CLK" spirit:configGroups="default" spirit:minimum="0" spirit:maximum="4" spirit:rangeType="long">2</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C3_LPDDR2_DATA_WIDTH</spirit:name>
        <spirit:displayName>datawidth excluding the ECC</spirit:displayName>
        <spirit:description>datawidth excluding the ECC</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C3_LPDDR2_DATA_WIDTH" spirit:configGroups="default" spirit:minimum="8" spirit:maximum="72" spirit:rangeType="long">8</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="float">
        <spirit:name>C3_FREQ_HZ</spirit:name>
        <spirit:displayName>defines the UI Clk freq</spirit:displayName>
        <spirit:description>defines the UI Clk freq</spirit:description>
        <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C3_FREQ_HZ" spirit:configGroups="default" spirit:minimum="0.0" spirit:maximum="800000000.0" spirit:rangeType="long">100.0</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="float">
        <spirit:name>C3_PHASE</spirit:name>
        <spirit:displayName>defines the UI Clk phase</spirit:displayName>
        <spirit:description>defines the UI Clk phase</spirit:description>
        <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C3_PHASE" spirit:choiceRef="choice_list_c7c132f6" spirit:configGroups="default">0.000</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="string">
        <spirit:name>C3_UI_EXTRA_CLOCKS</spirit:name>
        <spirit:displayName>Enablement of extra clocks</spirit:displayName>
        <spirit:description>Enablement of extra clocks</spirit:description>
        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C3_UI_EXTRA_CLOCKS" spirit:choiceRef="choice_list_d10f4555" spirit:configGroups="default">FALSE</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="float">
        <spirit:name>C3_MMCM_VCO</spirit:name>
        <spirit:displayName>Max possible VCO of MMCM primitive </spirit:displayName>
        <spirit:description>Max possible VCO of MMCM primitive </spirit:description>
        <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C3_MMCM_VCO" spirit:configGroups="default" spirit:minimum="600.0" spirit:maximum="1600.0" spirit:rangeType="long">1200.0</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="float">
        <spirit:name>C3_MMCM_CLKOUT0_FREQ</spirit:name>
        <spirit:displayName>mmcm extra clkout0</spirit:displayName>
        <spirit:description>mmcm extra clkout0</spirit:description>
        <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C3_MMCM_CLKOUT0_FREQ" spirit:configGroups="default" spirit:minimum="0.0" spirit:maximum="800000000.0" spirit:rangeType="long">10.0</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C3_MMCM_CLKOUT1_FREQ</spirit:name>
        <spirit:displayName>mmcm extra clkout1</spirit:displayName>
        <spirit:description>mmcm extra clkout1</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C3_MMCM_CLKOUT1_FREQ" spirit:configGroups="default" spirit:minimum="0.0" spirit:maximum="800000000" spirit:rangeType="long">10</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C3_MMCM_CLKOUT2_FREQ</spirit:name>
        <spirit:displayName>mmcm extra clkout2</spirit:displayName>
        <spirit:description>mmcm extra clkout2</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C3_MMCM_CLKOUT2_FREQ" spirit:configGroups="default" spirit:minimum="0.0" spirit:maximum="800000000" spirit:rangeType="long">10</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C3_MMCM_CLKOUT3_FREQ</spirit:name>
        <spirit:displayName>mmcm extra clkout3</spirit:displayName>
        <spirit:description>mmcm extra clkout3</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C3_MMCM_CLKOUT3_FREQ" spirit:configGroups="default" spirit:minimum="0.0" spirit:maximum="800000000" spirit:rangeType="long">10</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C3_MMCM_CLKOUT4_FREQ</spirit:name>
        <spirit:displayName>mmcm extra clkout4</spirit:displayName>
        <spirit:description>mmcm extra clkout4</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C3_MMCM_CLKOUT4_FREQ" spirit:configGroups="default" spirit:minimum="0.0" spirit:maximum="800000000" spirit:rangeType="long">10</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="string">
        <spirit:name>C3_MMCM_CLKOUT0_EN</spirit:name>
        <spirit:displayName>Indicates Enablement of CLKOUT0</spirit:displayName>
        <spirit:description>Indicates Enablement of CLKOUT0</spirit:description>
        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C3_MMCM_CLKOUT0_EN" spirit:choiceRef="choice_list_e7c484ae" spirit:configGroups="default">FALSE</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="string">
        <spirit:name>C3_MMCM_CLKOUT2_EN</spirit:name>
        <spirit:displayName>Indicates Enablement of CLKOUT2</spirit:displayName>
        <spirit:description>Indicates Enablement of CLKOUT2</spirit:description>
        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C3_MMCM_CLKOUT2_EN" spirit:choiceRef="choice_list_e7c484ae" spirit:configGroups="default">FALSE</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="string">
        <spirit:name>C3_MMCM_CLKOUT1_EN</spirit:name>
        <spirit:displayName>Indicates Enablement of CLKOUT1</spirit:displayName>
        <spirit:description>Indicates Enablement of CLKOUT1</spirit:description>
        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C3_MMCM_CLKOUT1_EN" spirit:choiceRef="choice_list_e7c484ae" spirit:configGroups="default">FALSE</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="string">
        <spirit:name>C3_MMCM_CLKOUT3_EN</spirit:name>
        <spirit:displayName>Indicates Enablement of CLKOUT3</spirit:displayName>
        <spirit:description>Indicates Enablement of CLKOUT3</spirit:description>
        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C3_MMCM_CLKOUT3_EN" spirit:choiceRef="choice_list_e7c484ae" spirit:configGroups="default">FALSE</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="string">
        <spirit:name>C3_MMCM_CLKOUT4_EN</spirit:name>
        <spirit:displayName>Indicates Enablement of CLKOUT4</spirit:displayName>
        <spirit:description>Indicates Enablement of CLKOUT4</spirit:description>
        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C3_MMCM_CLKOUT4_EN" spirit:choiceRef="choice_list_e7c484ae" spirit:configGroups="default">FALSE</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C3_C_S_AXI_CTRL_ID_WIDTH</spirit:name>
        <spirit:displayName>AXI ID Width</spirit:displayName>
        <spirit:description>AXI ID Width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C3_C_S_AXI_CTRL_ID_WIDTH" spirit:configGroups="default" spirit:minimum="0" spirit:maximum="16" spirit:rangeType="long">4</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C3_C_S_AXI_CTRL_DATA_WIDTH</spirit:name>
        <spirit:displayName>AXI Data Width</spirit:displayName>
        <spirit:description>AXI Data Width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C3_C_S_AXI_CTRL_DATA_WIDTH" spirit:choiceRef="choice_list_40181835" spirit:configGroups="default">32</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C3_C_S_AXI_CTRL_ADDR_WIDTH</spirit:name>
        <spirit:displayName>AXI Addr Width</spirit:displayName>
        <spirit:description>AXI Addr Width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C3_C_S_AXI_CTRL_ADDR_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="36" spirit:rangeType="long">32</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C3_C_S_AXI_CTRL_MEM_SIZE</spirit:name>
        <spirit:displayName>Memory Address Space</spirit:displayName>
        <spirit:description>Memory Address Space</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C3_C_S_AXI_CTRL_MEM_SIZE" spirit:configGroups="default" spirit:minimum="0" spirit:maximum="34359738368" spirit:rangeType="long">1048576</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C3_C_S_AXI_ID_WIDTH</spirit:name>
        <spirit:displayName>AXI ID Width</spirit:displayName>
        <spirit:description>AXI ID Width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C3_C_S_AXI_ID_WIDTH" spirit:configGroups="default" spirit:minimum="0" spirit:maximum="16" spirit:rangeType="long">4</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C3_C_S_AXI_DATA_WIDTH</spirit:name>
        <spirit:displayName>AXI Data Width</spirit:displayName>
        <spirit:description>AXI Data Width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C3_C_S_AXI_DATA_WIDTH" spirit:choiceRef="choice_list_40181835" spirit:configGroups="default">32</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C3_C_S_AXI_ADDR_WIDTH</spirit:name>
        <spirit:displayName>AXI Addr Width</spirit:displayName>
        <spirit:description>AXI Addr Width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C3_C_S_AXI_ADDR_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="36" spirit:rangeType="long">32</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C3_C_S_AXI_MEM_SIZE</spirit:name>
        <spirit:displayName>Memory Address Space</spirit:displayName>
        <spirit:description>Memory Address Space</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C3_C_S_AXI_MEM_SIZE" spirit:configGroups="default" spirit:minimum="0" spirit:maximum="34359738368" spirit:rangeType="long">1048576</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C3_QDRIIP_NUM_DEVICES</spirit:name>
        <spirit:displayName>num devices</spirit:displayName>
        <spirit:description>num devices</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C3_QDRIIP_NUM_DEVICES" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="4" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C3_QDRIIP_DATA_WIDTH</spirit:name>
        <spirit:displayName>data width</spirit:displayName>
        <spirit:description>data width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C3_QDRIIP_DATA_WIDTH" spirit:choiceRef="choice_list_cf6acb30" spirit:configGroups="default">18</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C3_QDRIIP_ADDR_WIDTH</spirit:name>
        <spirit:displayName>addr width </spirit:displayName>
        <spirit:description>addr width </spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C3_QDRIIP_ADDR_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="32" spirit:rangeType="long">29</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C3_QDRIIP_BW_WIDTH</spirit:name>
        <spirit:displayName>bw width </spirit:displayName>
        <spirit:description>bw width </spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C3_QDRIIP_BW_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="8" spirit:rangeType="long">8</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="string">
        <spirit:name>C3_QDRIIP_DEBUG_PORT</spirit:name>
        <spirit:displayName>Debug Port enable info</spirit:displayName>
        <spirit:description>Debug Port enable info</spirit:description>
        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C3_QDRIIP_DEBUG_PORT" spirit:choiceRef="choice_list_dc86ec6e" spirit:configGroups="default">OFF</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C3_QDRIIP_BURST_LEN</spirit:name>
        <spirit:displayName>burst len </spirit:displayName>
        <spirit:description>burst len </spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C3_QDRIIP_BURST_LEN" spirit:choiceRef="choice_list_dd2843c6" spirit:configGroups="default">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C3_RLDII_NUM_DEVICES</spirit:name>
        <spirit:displayName>num devices</spirit:displayName>
        <spirit:description>num devices</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C3_RLDII_NUM_DEVICES" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="4" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C3_RLDII_DATA_WIDTH</spirit:name>
        <spirit:displayName>data width</spirit:displayName>
        <spirit:description>data width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C3_RLDII_DATA_WIDTH" spirit:choiceRef="choice_list_cf6acb30" spirit:configGroups="default">18</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C3_RLDII_RLD_ADDR_WIDTH</spirit:name>
        <spirit:displayName>rld addr width </spirit:displayName>
        <spirit:description>rld addr width </spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C3_RLDII_RLD_ADDR_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="32" spirit:rangeType="long">29</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C3_RLDII_QK_WIDTH</spirit:name>
        <spirit:displayName>qk width </spirit:displayName>
        <spirit:description>qk width </spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C3_RLDII_QK_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="8" spirit:rangeType="long">8</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C3_RLDII_CK_WIDTH</spirit:name>
        <spirit:displayName>ck width </spirit:displayName>
        <spirit:description>ck width </spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C3_RLDII_CK_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="4" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C3_RLDII_DK_WIDTH</spirit:name>
        <spirit:displayName>dk width </spirit:displayName>
        <spirit:description>dk width </spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C3_RLDII_DK_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="4" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C3_RLDII_DM_WIDTH</spirit:name>
        <spirit:displayName>dm width </spirit:displayName>
        <spirit:description>dm width </spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C3_RLDII_DM_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="4" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C3_RLDII_BANK_WIDTH</spirit:name>
        <spirit:displayName>bank width </spirit:displayName>
        <spirit:description>bank width </spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C3_RLDII_BANK_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="4" spirit:rangeType="long">2</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C3_RLDII_QVLD_WIDTH</spirit:name>
        <spirit:displayName>qvld width </spirit:displayName>
        <spirit:description>qvld width </spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C3_RLDII_QVLD_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="4" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="string">
        <spirit:name>C3_RLDII_DEBUG_PORT</spirit:name>
        <spirit:displayName>Debug Port enable info</spirit:displayName>
        <spirit:description>Debug Port enable info</spirit:description>
        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C3_RLDII_DEBUG_PORT" spirit:choiceRef="choice_list_dc86ec6e" spirit:configGroups="default">OFF</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C3_RLDIII_NUM_DEVICES</spirit:name>
        <spirit:displayName>num devices</spirit:displayName>
        <spirit:description>num devices</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C3_RLDIII_NUM_DEVICES" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="4" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C3_RLDIII_DATA_WIDTH</spirit:name>
        <spirit:displayName>data width</spirit:displayName>
        <spirit:description>data width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C3_RLDIII_DATA_WIDTH" spirit:choiceRef="choice_list_cf6acb30" spirit:configGroups="default">18</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C3_RLDIII_RLD_ADDR_WIDTH</spirit:name>
        <spirit:displayName>rld addr width </spirit:displayName>
        <spirit:description>rld addr width </spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C3_RLDIII_RLD_ADDR_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="32" spirit:rangeType="long">29</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C3_RLDIII_QK_WIDTH</spirit:name>
        <spirit:displayName>qk width </spirit:displayName>
        <spirit:description>qk width </spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C3_RLDIII_QK_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="8" spirit:rangeType="long">8</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C3_RLDIII_CK_WIDTH</spirit:name>
        <spirit:displayName>ck width </spirit:displayName>
        <spirit:description>ck width </spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C3_RLDIII_CK_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="4" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C3_RLDIII_DK_WIDTH</spirit:name>
        <spirit:displayName>dk width </spirit:displayName>
        <spirit:description>dk width </spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C3_RLDIII_DK_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="4" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C3_RLDIII_DM_WIDTH</spirit:name>
        <spirit:displayName>dm width </spirit:displayName>
        <spirit:description>dm width </spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C3_RLDIII_DM_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="4" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C3_RLDIII_BANK_WIDTH</spirit:name>
        <spirit:displayName>bank width </spirit:displayName>
        <spirit:description>bank width </spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C3_RLDIII_BANK_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="4" spirit:rangeType="long">2</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C3_RLDIII_QVLD_WIDTH</spirit:name>
        <spirit:displayName>qvld width </spirit:displayName>
        <spirit:description>qvld width </spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C3_RLDIII_QVLD_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="4" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="string">
        <spirit:name>C3_RLDIII_DEBUG_PORT</spirit:name>
        <spirit:displayName>Debug Port enable info</spirit:displayName>
        <spirit:description>Debug Port enable info</spirit:description>
        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C3_RLDIII_DEBUG_PORT" spirit:choiceRef="choice_list_dc86ec6e" spirit:configGroups="default">OFF</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C3_RLDX_CMD_PER_CLK</spirit:name>
        <spirit:displayName>cmd per clock</spirit:displayName>
        <spirit:description>cmd per clock</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C3_RLDX_CMD_PER_CLK" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="4" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C3_RLDX_DATA_WIDTH</spirit:name>
        <spirit:displayName>data width</spirit:displayName>
        <spirit:description>data width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C3_RLDX_DATA_WIDTH" spirit:choiceRef="choice_list_cf6acb30" spirit:configGroups="default">18</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C3_RLDX_ADDR_WIDTH</spirit:name>
        <spirit:displayName>addr width </spirit:displayName>
        <spirit:description>addr width </spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C3_RLDX_ADDR_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="32" spirit:rangeType="long">29</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C3_RLDX_BANK_WIDTH</spirit:name>
        <spirit:displayName>bank width </spirit:displayName>
        <spirit:description>bank width </spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C3_RLDX_BANK_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="4" spirit:rangeType="long">2</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C3_RLDX_nCK_PER_CLK</spirit:name>
        <spirit:displayName>nCk per clock</spirit:displayName>
        <spirit:description>nCk per clock</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C3_RLDX_nCK_PER_CLK" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="4" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C3_RLDX_DM_WIDTH</spirit:name>
        <spirit:displayName>dm width </spirit:displayName>
        <spirit:description>dm width </spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C3_RLDX_DM_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="4" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C3_RLDII_CMD_PER_CLK</spirit:name>
        <spirit:displayName>cmd per clock</spirit:displayName>
        <spirit:description>cmd per clock</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C3_RLDII_CMD_PER_CLK" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="4" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C3_RLDII_ADDR_WIDTH</spirit:name>
        <spirit:displayName>addr width </spirit:displayName>
        <spirit:description>addr width </spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C3_RLDII_ADDR_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="32" spirit:rangeType="long">29</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C3_RLDII_nCK_PER_CLK</spirit:name>
        <spirit:displayName>nCk per clock</spirit:displayName>
        <spirit:description>nCk per clock</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C3_RLDII_nCK_PER_CLK" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="4" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C3_RLDIII_CMD_PER_CLK</spirit:name>
        <spirit:displayName>cmd per clock</spirit:displayName>
        <spirit:description>cmd per clock</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C3_RLDIII_CMD_PER_CLK" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="4" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C3_RLDIII_ADDR_WIDTH</spirit:name>
        <spirit:displayName>addr width </spirit:displayName>
        <spirit:description>addr width </spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C3_RLDIII_ADDR_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="32" spirit:rangeType="long">29</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C3_RLDIII_nCK_PER_CLK</spirit:name>
        <spirit:displayName>nCk per clock</spirit:displayName>
        <spirit:description>nCk per clock</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C3_RLDIII_nCK_PER_CLK" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="4" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="string">
        <spirit:name>C3_POLARITY</spirit:name>
        <spirit:displayName>Polarity of the value</spirit:displayName>
        <spirit:description>Polarity of the value</spirit:description>
        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C3_POLARITY" spirit:choiceRef="choice_list_6eff49bd" spirit:configGroups="default">ACTIVE_LOW</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="string">
        <spirit:name>C4_MEM_TYPE</spirit:name>
        <spirit:displayName>identify interface</spirit:displayName>
        <spirit:description>identify interface</spirit:description>
        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C4_MEM_TYPE" spirit:choiceRef="choice_list_b54243b1" spirit:configGroups="default">DDR3</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="string">
        <spirit:name>C4_IS_CLK_SHARED</spirit:name>
        <spirit:displayName>is clk shared</spirit:displayName>
        <spirit:description>is clk shared</spirit:description>
        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C4_IS_CLK_SHARED" spirit:choiceRef="choice_list_d10f4555" spirit:configGroups="default">FALSE</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="string">
        <spirit:name>C4_SYSCLK_TYPE</spirit:name>
        <spirit:displayName>Type of sys clk</spirit:displayName>
        <spirit:description>Type of sys clk</spirit:description>
        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C4_SYSCLK_TYPE" spirit:choiceRef="choice_list_1570a756" spirit:configGroups="default">DIFF</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C4_USE_AXI</spirit:name>
        <spirit:displayName>USE AXI</spirit:displayName>
        <spirit:description>USE AXI</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C4_USE_AXI" spirit:configGroups="default" spirit:minimum="0" spirit:maximum="1" spirit:rangeType="long">0</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="string">
        <spirit:name>C4_ECC</spirit:name>
        <spirit:displayName>ecc enable info</spirit:displayName>
        <spirit:description>ecc enable info</spirit:description>
        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C4_ECC" spirit:choiceRef="choice_list_dc86ec6e" spirit:configGroups="default">OFF</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C4_DDR3_DQ_WIDTH</spirit:name>
        <spirit:displayName>data bus width</spirit:displayName>
        <spirit:description>data bus width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C4_DDR3_DQ_WIDTH" spirit:choiceRef="choice_list_bdb560e1" spirit:configGroups="default">8</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C4_DDR3_DQS_WIDTH</spirit:name>
        <spirit:displayName>data strobe width</spirit:displayName>
        <spirit:description>data strobe width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C4_DDR3_DQS_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="9" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C4_DDR3_ROW_WIDTH</spirit:name>
        <spirit:displayName>row width</spirit:displayName>
        <spirit:description>row width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C4_DDR3_ROW_WIDTH" spirit:configGroups="default" spirit:minimum="13" spirit:maximum="16" spirit:rangeType="long">14</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C4_DDR3_BANK_WIDTH</spirit:name>
        <spirit:displayName>bank width</spirit:displayName>
        <spirit:description>bank width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C4_DDR3_BANK_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="3" spirit:rangeType="long">3</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C4_DDR3_CK_WIDTH</spirit:name>
        <spirit:displayName>clock width</spirit:displayName>
        <spirit:description>clock width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C4_DDR3_CK_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="4" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C4_DDR3_CKE_WIDTH</spirit:name>
        <spirit:displayName>clock enable width</spirit:displayName>
        <spirit:description>clock enable width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C4_DDR3_CKE_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="2" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C4_DDR3_CS_WIDTH</spirit:name>
        <spirit:displayName>chip select width</spirit:displayName>
        <spirit:description>chip select width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C4_DDR3_CS_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="2" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C4_DDR3_nCS_PER_RANK</spirit:name>
        <spirit:displayName>chip select per rank</spirit:displayName>
        <spirit:description>chip select per rank</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C4_DDR3_nCS_PER_RANK" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="4" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C4_DDR3_DM_WIDTH</spirit:name>
        <spirit:displayName>data mask width</spirit:displayName>
        <spirit:description>data mask width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C4_DDR3_DM_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="9" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C4_DDR3_ODT_WIDTH</spirit:name>
        <spirit:displayName>odt width</spirit:displayName>
        <spirit:description>odt width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C4_DDR3_ODT_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="4" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C4_DDR3_USE_CS_PORT</spirit:name>
        <spirit:displayName>CS Port is in use</spirit:displayName>
        <spirit:description>CS Port is in use</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C4_DDR3_USE_CS_PORT" spirit:configGroups="default" spirit:minimum="0" spirit:maximum="1" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C4_DDR3_USE_DM_PORT</spirit:name>
        <spirit:displayName>DM Port is in use</spirit:displayName>
        <spirit:description>DM Port is in use</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C4_DDR3_USE_DM_PORT" spirit:configGroups="default" spirit:minimum="0" spirit:maximum="1" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C4_DDR3_USE_ODT_PORT</spirit:name>
        <spirit:displayName>ODT Port is in use</spirit:displayName>
        <spirit:description>ODT Port is in use</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C4_DDR3_USE_ODT_PORT" spirit:configGroups="default" spirit:minimum="0" spirit:maximum="1" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="string">
        <spirit:name>C4_DDR3_REG_CTRL</spirit:name>
        <spirit:displayName>Indicates Registered DIMM or not</spirit:displayName>
        <spirit:description>Indicates Registered DIMM or not</spirit:description>
        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C4_DDR3_REG_CTRL" spirit:choiceRef="choice_list_dc86ec6e" spirit:configGroups="default">OFF</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C4_DDR3_DQS_CNT_WIDTH</spirit:name>
        <spirit:displayName>DQS count width</spirit:displayName>
        <spirit:description>DQS count width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C4_DDR3_DQS_CNT_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="8" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="string">
        <spirit:name>C4_DDR3_DEBUG_PORT</spirit:name>
        <spirit:displayName>Debug Port enable info</spirit:displayName>
        <spirit:description>Debug Port enable info</spirit:description>
        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C4_DDR3_DEBUG_PORT" spirit:choiceRef="choice_list_dc86ec6e" spirit:configGroups="default">OFF</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C4_DDR2_DQ_WIDTH</spirit:name>
        <spirit:displayName>data bus width</spirit:displayName>
        <spirit:description>data bus width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C4_DDR2_DQ_WIDTH" spirit:choiceRef="choice_list_bdb560e1" spirit:configGroups="default">8</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C4_DDR2_DQS_WIDTH</spirit:name>
        <spirit:displayName>data strobe width</spirit:displayName>
        <spirit:description>data strobe width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C4_DDR2_DQS_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="9" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C4_DDR2_ROW_WIDTH</spirit:name>
        <spirit:displayName>row width</spirit:displayName>
        <spirit:description>row width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C4_DDR2_ROW_WIDTH" spirit:configGroups="default" spirit:minimum="13" spirit:maximum="16" spirit:rangeType="long">14</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C4_DDR2_BANK_WIDTH</spirit:name>
        <spirit:displayName>bank width</spirit:displayName>
        <spirit:description>bank width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C4_DDR2_BANK_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="3" spirit:rangeType="long">3</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C4_DDR2_CK_WIDTH</spirit:name>
        <spirit:displayName>clock width</spirit:displayName>
        <spirit:description>clock width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C4_DDR2_CK_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="4" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C4_DDR2_CKE_WIDTH</spirit:name>
        <spirit:displayName>clock enable width</spirit:displayName>
        <spirit:description>clock enable width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C4_DDR2_CKE_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="2" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C4_DDR2_CS_WIDTH</spirit:name>
        <spirit:displayName>chip select width</spirit:displayName>
        <spirit:description>chip select width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C4_DDR2_CS_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="2" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C4_DDR2_nCS_PER_RANK</spirit:name>
        <spirit:displayName>chip select per rank</spirit:displayName>
        <spirit:description>chip select per rank</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C4_DDR2_nCS_PER_RANK" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="4" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C4_DDR2_DM_WIDTH</spirit:name>
        <spirit:displayName>data mask width</spirit:displayName>
        <spirit:description>data mask width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C4_DDR2_DM_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="9" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C4_DDR2_ODT_WIDTH</spirit:name>
        <spirit:displayName>odt width</spirit:displayName>
        <spirit:description>odt width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C4_DDR2_ODT_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="4" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C4_DDR2_USE_CS_PORT</spirit:name>
        <spirit:displayName>CS Port is in use</spirit:displayName>
        <spirit:description>CS Port is in use</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C4_DDR2_USE_CS_PORT" spirit:configGroups="default" spirit:minimum="0" spirit:maximum="1" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C4_DDR2_USE_DM_PORT</spirit:name>
        <spirit:displayName>DM Port is in use</spirit:displayName>
        <spirit:description>DM Port is in use</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C4_DDR2_USE_DM_PORT" spirit:configGroups="default" spirit:minimum="0" spirit:maximum="1" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C4_DDR2_USE_ODT_PORT</spirit:name>
        <spirit:displayName>ODT Port is in use</spirit:displayName>
        <spirit:description>ODT Port is in use</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C4_DDR2_USE_ODT_PORT" spirit:configGroups="default" spirit:minimum="0" spirit:maximum="1" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="string">
        <spirit:name>C4_DDR2_REG_CTRL</spirit:name>
        <spirit:displayName>Indicates Registered DIMM or not</spirit:displayName>
        <spirit:description>Indicates Registered DIMM or not</spirit:description>
        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C4_DDR2_REG_CTRL" spirit:choiceRef="choice_list_dc86ec6e" spirit:configGroups="default">OFF</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C4_DDR2_DQS_CNT_WIDTH</spirit:name>
        <spirit:displayName>DQS count width</spirit:displayName>
        <spirit:description>DQS count width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C4_DDR2_DQS_CNT_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="8" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="string">
        <spirit:name>C4_DDR2_DEBUG_PORT</spirit:name>
        <spirit:displayName>Debug Port enable info</spirit:displayName>
        <spirit:description>Debug Port enable info</spirit:description>
        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C4_DDR2_DEBUG_PORT" spirit:choiceRef="choice_list_dc86ec6e" spirit:configGroups="default">OFF</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C4_LPDDR2_DQ_WIDTH</spirit:name>
        <spirit:displayName>data bus width</spirit:displayName>
        <spirit:description>data bus width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C4_LPDDR2_DQ_WIDTH" spirit:choiceRef="choice_list_bdb560e1" spirit:configGroups="default">8</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C4_LPDDR2_DQS_WIDTH</spirit:name>
        <spirit:displayName>data strobe width</spirit:displayName>
        <spirit:description>data strobe width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C4_LPDDR2_DQS_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="9" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C4_LPDDR2_ROW_WIDTH</spirit:name>
        <spirit:displayName>row width</spirit:displayName>
        <spirit:description>row width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C4_LPDDR2_ROW_WIDTH" spirit:configGroups="default" spirit:minimum="12" spirit:maximum="16" spirit:rangeType="long">14</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C4_LPDDR2_BANK_WIDTH</spirit:name>
        <spirit:displayName>bank width</spirit:displayName>
        <spirit:description>bank width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C4_LPDDR2_BANK_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="3" spirit:rangeType="long">3</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C4_LPDDR2_CK_WIDTH</spirit:name>
        <spirit:displayName>clock width</spirit:displayName>
        <spirit:description>clock width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C4_LPDDR2_CK_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="4" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C4_LPDDR2_CKE_WIDTH</spirit:name>
        <spirit:displayName>clock enable width</spirit:displayName>
        <spirit:description>clock enable width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C4_LPDDR2_CKE_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="2" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C4_LPDDR2_CS_WIDTH</spirit:name>
        <spirit:displayName>chip select width</spirit:displayName>
        <spirit:description>chip select width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C4_LPDDR2_CS_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="2" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C4_LPDDR2_nCS_PER_RANK</spirit:name>
        <spirit:displayName>chip select per rank</spirit:displayName>
        <spirit:description>chip select per rank</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C4_LPDDR2_nCS_PER_RANK" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="4" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C4_LPDDR2_DM_WIDTH</spirit:name>
        <spirit:displayName>data mask width</spirit:displayName>
        <spirit:description>data mask width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C4_LPDDR2_DM_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="9" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C4_LPDDR2_USE_CS_PORT</spirit:name>
        <spirit:displayName>CS Port is in use</spirit:displayName>
        <spirit:description>CS Port is in use</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C4_LPDDR2_USE_CS_PORT" spirit:configGroups="default" spirit:minimum="0" spirit:maximum="1" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C4_LPDDR2_USE_DM_PORT</spirit:name>
        <spirit:displayName>DM Port is in use</spirit:displayName>
        <spirit:description>DM Port is in use</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C4_LPDDR2_USE_DM_PORT" spirit:configGroups="default" spirit:minimum="0" spirit:maximum="1" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C4_LPDDR2_USE_ODT_PORT</spirit:name>
        <spirit:displayName>ODT Port is in use</spirit:displayName>
        <spirit:description>ODT Port is in use</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C4_LPDDR2_USE_ODT_PORT" spirit:configGroups="default" spirit:minimum="0" spirit:maximum="1" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="string">
        <spirit:name>C4_LPDDR2_REG_CTRL</spirit:name>
        <spirit:displayName>Indicates Registered DIMM or not</spirit:displayName>
        <spirit:description>Indicates Registered DIMM or not</spirit:description>
        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C4_LPDDR2_REG_CTRL" spirit:choiceRef="choice_list_dc86ec6e" spirit:configGroups="default">OFF</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C4_LPDDR2_DQS_CNT_WIDTH</spirit:name>
        <spirit:displayName>DQS count width</spirit:displayName>
        <spirit:description>DQS count width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C4_LPDDR2_DQS_CNT_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="8" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="string">
        <spirit:name>C4_LPDDR2_DEBUG_PORT</spirit:name>
        <spirit:displayName>Debug Port enable info</spirit:displayName>
        <spirit:description>Debug Port enable info</spirit:description>
        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C4_LPDDR2_DEBUG_PORT" spirit:choiceRef="choice_list_dc86ec6e" spirit:configGroups="default">OFF</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C4_DQS_CNT_WIDTH</spirit:name>
        <spirit:displayName>DQS count width</spirit:displayName>
        <spirit:description>DQS count width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C4_DQS_CNT_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="8" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="string">
        <spirit:name>C4_DEBUG_PORT</spirit:name>
        <spirit:displayName>Debug Port enable info</spirit:displayName>
        <spirit:description>Debug Port enable info</spirit:description>
        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C4_DEBUG_PORT" spirit:choiceRef="choice_list_dc86ec6e" spirit:configGroups="default">OFF</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C4_DDRX_ADDR_WIDTH</spirit:name>
        <spirit:displayName>addr width</spirit:displayName>
        <spirit:description>addr width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C4_DDRX_ADDR_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="32" spirit:rangeType="long">8</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C4_DDRX_nCK_PER_CLK</spirit:name>
        <spirit:displayName>nck per clk</spirit:displayName>
        <spirit:description>nck per clk</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C4_DDRX_nCK_PER_CLK" spirit:configGroups="default" spirit:minimum="0" spirit:maximum="4" spirit:rangeType="long">2</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C4_DDRX_DATA_WIDTH</spirit:name>
        <spirit:displayName>datawidth excluding the ECC</spirit:displayName>
        <spirit:description>datawidth excluding the ECC</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C4_DDRX_DATA_WIDTH" spirit:configGroups="default" spirit:minimum="8" spirit:maximum="72" spirit:rangeType="long">8</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C4_DDR3_ADDR_WIDTH</spirit:name>
        <spirit:displayName>addr width</spirit:displayName>
        <spirit:description>addr width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C4_DDR3_ADDR_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="32" spirit:rangeType="long">8</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C4_DDR3_nCK_PER_CLK</spirit:name>
        <spirit:displayName>nck per clk</spirit:displayName>
        <spirit:description>nck per clk</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C4_DDR3_nCK_PER_CLK" spirit:configGroups="default" spirit:minimum="0" spirit:maximum="4" spirit:rangeType="long">2</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C4_DDR3_DATA_WIDTH</spirit:name>
        <spirit:displayName>datawidth excluding the ECC</spirit:displayName>
        <spirit:description>datawidth excluding the ECC</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C4_DDR3_DATA_WIDTH" spirit:configGroups="default" spirit:minimum="8" spirit:maximum="72" spirit:rangeType="long">8</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C4_DDR2_ADDR_WIDTH</spirit:name>
        <spirit:displayName>addr width</spirit:displayName>
        <spirit:description>addr width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C4_DDR2_ADDR_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="32" spirit:rangeType="long">8</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C4_DDR2_nCK_PER_CLK</spirit:name>
        <spirit:displayName>nck per clk</spirit:displayName>
        <spirit:description>nck per clk</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C4_DDR2_nCK_PER_CLK" spirit:configGroups="default" spirit:minimum="0" spirit:maximum="4" spirit:rangeType="long">2</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C4_DDR2_DATA_WIDTH</spirit:name>
        <spirit:displayName>datawidth excluding the ECC</spirit:displayName>
        <spirit:description>datawidth excluding the ECC</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C4_DDR2_DATA_WIDTH" spirit:configGroups="default" spirit:minimum="8" spirit:maximum="72" spirit:rangeType="long">8</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C4_LPDDR2_ADDR_WIDTH</spirit:name>
        <spirit:displayName>addr width</spirit:displayName>
        <spirit:description>addr width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C4_LPDDR2_ADDR_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="32" spirit:rangeType="long">8</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C4_LPDDR2_nCK_PER_CLK</spirit:name>
        <spirit:displayName>nck per clk</spirit:displayName>
        <spirit:description>nck per clk</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C4_LPDDR2_nCK_PER_CLK" spirit:configGroups="default" spirit:minimum="0" spirit:maximum="4" spirit:rangeType="long">2</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C4_LPDDR2_DATA_WIDTH</spirit:name>
        <spirit:displayName>datawidth excluding the ECC</spirit:displayName>
        <spirit:description>datawidth excluding the ECC</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C4_LPDDR2_DATA_WIDTH" spirit:configGroups="default" spirit:minimum="8" spirit:maximum="72" spirit:rangeType="long">8</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="float">
        <spirit:name>C4_FREQ_HZ</spirit:name>
        <spirit:displayName>defines the UI Clk freq</spirit:displayName>
        <spirit:description>defines the UI Clk freq</spirit:description>
        <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C4_FREQ_HZ" spirit:configGroups="default" spirit:minimum="0.0" spirit:maximum="800000000.0" spirit:rangeType="long">100.0</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="float">
        <spirit:name>C4_PHASE</spirit:name>
        <spirit:displayName>defines the UI Clk phase</spirit:displayName>
        <spirit:description>defines the UI Clk phase</spirit:description>
        <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C4_PHASE" spirit:choiceRef="choice_list_c7c132f6" spirit:configGroups="default">0.000</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="string">
        <spirit:name>C4_UI_EXTRA_CLOCKS</spirit:name>
        <spirit:displayName>Enablement of extra clocks</spirit:displayName>
        <spirit:description>Enablement of extra clocks</spirit:description>
        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C4_UI_EXTRA_CLOCKS" spirit:choiceRef="choice_list_d10f4555" spirit:configGroups="default">FALSE</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="float">
        <spirit:name>C4_MMCM_VCO</spirit:name>
        <spirit:displayName>Max possible VCO of MMCM primitive </spirit:displayName>
        <spirit:description>Max possible VCO of MMCM primitive </spirit:description>
        <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C4_MMCM_VCO" spirit:configGroups="default" spirit:minimum="600.0" spirit:maximum="1600.0" spirit:rangeType="long">1200.0</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="float">
        <spirit:name>C4_MMCM_CLKOUT0_FREQ</spirit:name>
        <spirit:displayName>mmcm extra clkout0</spirit:displayName>
        <spirit:description>mmcm extra clkout0</spirit:description>
        <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C4_MMCM_CLKOUT0_FREQ" spirit:configGroups="default" spirit:minimum="0.0" spirit:maximum="800000000.0" spirit:rangeType="long">10.0</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C4_MMCM_CLKOUT1_FREQ</spirit:name>
        <spirit:displayName>mmcm extra clkout1</spirit:displayName>
        <spirit:description>mmcm extra clkout1</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C4_MMCM_CLKOUT1_FREQ" spirit:configGroups="default" spirit:minimum="0.0" spirit:maximum="800000000" spirit:rangeType="long">10</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C4_MMCM_CLKOUT2_FREQ</spirit:name>
        <spirit:displayName>mmcm extra clkout2</spirit:displayName>
        <spirit:description>mmcm extra clkout2</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C4_MMCM_CLKOUT2_FREQ" spirit:configGroups="default" spirit:minimum="0.0" spirit:maximum="800000000" spirit:rangeType="long">10</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C4_MMCM_CLKOUT3_FREQ</spirit:name>
        <spirit:displayName>mmcm extra clkout3</spirit:displayName>
        <spirit:description>mmcm extra clkout3</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C4_MMCM_CLKOUT3_FREQ" spirit:configGroups="default" spirit:minimum="0.0" spirit:maximum="800000000" spirit:rangeType="long">10</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C4_MMCM_CLKOUT4_FREQ</spirit:name>
        <spirit:displayName>mmcm extra clkout4</spirit:displayName>
        <spirit:description>mmcm extra clkout4</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C4_MMCM_CLKOUT4_FREQ" spirit:configGroups="default" spirit:minimum="0.0" spirit:maximum="800000000" spirit:rangeType="long">10</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="string">
        <spirit:name>C4_MMCM_CLKOUT0_EN</spirit:name>
        <spirit:displayName>Indicates Enablement of CLKOUT0</spirit:displayName>
        <spirit:description>Indicates Enablement of CLKOUT0</spirit:description>
        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C4_MMCM_CLKOUT0_EN" spirit:choiceRef="choice_list_e7c484ae" spirit:configGroups="default">FALSE</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="string">
        <spirit:name>C4_MMCM_CLKOUT2_EN</spirit:name>
        <spirit:displayName>Indicates Enablement of CLKOUT2</spirit:displayName>
        <spirit:description>Indicates Enablement of CLKOUT2</spirit:description>
        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C4_MMCM_CLKOUT2_EN" spirit:choiceRef="choice_list_e7c484ae" spirit:configGroups="default">FALSE</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="string">
        <spirit:name>C4_MMCM_CLKOUT1_EN</spirit:name>
        <spirit:displayName>Indicates Enablement of CLKOUT1</spirit:displayName>
        <spirit:description>Indicates Enablement of CLKOUT1</spirit:description>
        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C4_MMCM_CLKOUT1_EN" spirit:choiceRef="choice_list_e7c484ae" spirit:configGroups="default">FALSE</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="string">
        <spirit:name>C4_MMCM_CLKOUT3_EN</spirit:name>
        <spirit:displayName>Indicates Enablement of CLKOUT3</spirit:displayName>
        <spirit:description>Indicates Enablement of CLKOUT3</spirit:description>
        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C4_MMCM_CLKOUT3_EN" spirit:choiceRef="choice_list_e7c484ae" spirit:configGroups="default">FALSE</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="string">
        <spirit:name>C4_MMCM_CLKOUT4_EN</spirit:name>
        <spirit:displayName>Indicates Enablement of CLKOUT4</spirit:displayName>
        <spirit:description>Indicates Enablement of CLKOUT4</spirit:description>
        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C4_MMCM_CLKOUT4_EN" spirit:choiceRef="choice_list_e7c484ae" spirit:configGroups="default">FALSE</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C4_C_S_AXI_CTRL_ID_WIDTH</spirit:name>
        <spirit:displayName>AXI ID Width</spirit:displayName>
        <spirit:description>AXI ID Width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C4_C_S_AXI_CTRL_ID_WIDTH" spirit:configGroups="default" spirit:minimum="0" spirit:maximum="16" spirit:rangeType="long">4</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C4_C_S_AXI_CTRL_DATA_WIDTH</spirit:name>
        <spirit:displayName>AXI Data Width</spirit:displayName>
        <spirit:description>AXI Data Width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C4_C_S_AXI_CTRL_DATA_WIDTH" spirit:choiceRef="choice_list_40181835" spirit:configGroups="default">32</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C4_C_S_AXI_CTRL_ADDR_WIDTH</spirit:name>
        <spirit:displayName>AXI Addr Width</spirit:displayName>
        <spirit:description>AXI Addr Width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C4_C_S_AXI_CTRL_ADDR_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="36" spirit:rangeType="long">32</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C4_C_S_AXI_CTRL_MEM_SIZE</spirit:name>
        <spirit:displayName>Memory Address Space</spirit:displayName>
        <spirit:description>Memory Address Space</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C4_C_S_AXI_CTRL_MEM_SIZE" spirit:configGroups="default" spirit:minimum="0" spirit:maximum="34359738368" spirit:rangeType="long">1048576</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C4_C_S_AXI_ID_WIDTH</spirit:name>
        <spirit:displayName>AXI ID Width</spirit:displayName>
        <spirit:description>AXI ID Width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C4_C_S_AXI_ID_WIDTH" spirit:configGroups="default" spirit:minimum="0" spirit:maximum="16" spirit:rangeType="long">4</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C4_C_S_AXI_DATA_WIDTH</spirit:name>
        <spirit:displayName>AXI Data Width</spirit:displayName>
        <spirit:description>AXI Data Width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C4_C_S_AXI_DATA_WIDTH" spirit:choiceRef="choice_list_40181835" spirit:configGroups="default">32</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C4_C_S_AXI_ADDR_WIDTH</spirit:name>
        <spirit:displayName>AXI Addr Width</spirit:displayName>
        <spirit:description>AXI Addr Width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C4_C_S_AXI_ADDR_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="36" spirit:rangeType="long">32</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C4_C_S_AXI_MEM_SIZE</spirit:name>
        <spirit:displayName>Memory Address Space</spirit:displayName>
        <spirit:description>Memory Address Space</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C4_C_S_AXI_MEM_SIZE" spirit:configGroups="default" spirit:minimum="0" spirit:maximum="34359738368" spirit:rangeType="long">1048576</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C4_QDRIIP_NUM_DEVICES</spirit:name>
        <spirit:displayName>num devices</spirit:displayName>
        <spirit:description>num devices</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C4_QDRIIP_NUM_DEVICES" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="4" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C4_QDRIIP_DATA_WIDTH</spirit:name>
        <spirit:displayName>data width</spirit:displayName>
        <spirit:description>data width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C4_QDRIIP_DATA_WIDTH" spirit:choiceRef="choice_list_cf6acb30" spirit:configGroups="default">18</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C4_QDRIIP_ADDR_WIDTH</spirit:name>
        <spirit:displayName>addr width </spirit:displayName>
        <spirit:description>addr width </spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C4_QDRIIP_ADDR_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="32" spirit:rangeType="long">29</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C4_QDRIIP_BW_WIDTH</spirit:name>
        <spirit:displayName>bw width </spirit:displayName>
        <spirit:description>bw width </spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C4_QDRIIP_BW_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="8" spirit:rangeType="long">8</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="string">
        <spirit:name>C4_QDRIIP_DEBUG_PORT</spirit:name>
        <spirit:displayName>Debug Port enable info</spirit:displayName>
        <spirit:description>Debug Port enable info</spirit:description>
        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C4_QDRIIP_DEBUG_PORT" spirit:choiceRef="choice_list_dc86ec6e" spirit:configGroups="default">OFF</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C4_QDRIIP_BURST_LEN</spirit:name>
        <spirit:displayName>burst len </spirit:displayName>
        <spirit:description>burst len </spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C4_QDRIIP_BURST_LEN" spirit:choiceRef="choice_list_dd2843c6" spirit:configGroups="default">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C4_RLDII_NUM_DEVICES</spirit:name>
        <spirit:displayName>num devices</spirit:displayName>
        <spirit:description>num devices</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C4_RLDII_NUM_DEVICES" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="4" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C4_RLDII_DATA_WIDTH</spirit:name>
        <spirit:displayName>data width</spirit:displayName>
        <spirit:description>data width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C4_RLDII_DATA_WIDTH" spirit:choiceRef="choice_list_cf6acb30" spirit:configGroups="default">18</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C4_RLDII_RLD_ADDR_WIDTH</spirit:name>
        <spirit:displayName>rld addr width </spirit:displayName>
        <spirit:description>rld addr width </spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C4_RLDII_RLD_ADDR_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="32" spirit:rangeType="long">29</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C4_RLDII_QK_WIDTH</spirit:name>
        <spirit:displayName>qk width </spirit:displayName>
        <spirit:description>qk width </spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C4_RLDII_QK_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="8" spirit:rangeType="long">8</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C4_RLDII_CK_WIDTH</spirit:name>
        <spirit:displayName>ck width </spirit:displayName>
        <spirit:description>ck width </spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C4_RLDII_CK_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="4" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C4_RLDII_DK_WIDTH</spirit:name>
        <spirit:displayName>dk width </spirit:displayName>
        <spirit:description>dk width </spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C4_RLDII_DK_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="4" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C4_RLDII_DM_WIDTH</spirit:name>
        <spirit:displayName>dm width </spirit:displayName>
        <spirit:description>dm width </spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C4_RLDII_DM_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="4" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C4_RLDII_BANK_WIDTH</spirit:name>
        <spirit:displayName>bank width </spirit:displayName>
        <spirit:description>bank width </spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C4_RLDII_BANK_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="4" spirit:rangeType="long">2</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C4_RLDII_QVLD_WIDTH</spirit:name>
        <spirit:displayName>qvld width </spirit:displayName>
        <spirit:description>qvld width </spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C4_RLDII_QVLD_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="4" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="string">
        <spirit:name>C4_RLDII_DEBUG_PORT</spirit:name>
        <spirit:displayName>Debug Port enable info</spirit:displayName>
        <spirit:description>Debug Port enable info</spirit:description>
        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C4_RLDII_DEBUG_PORT" spirit:choiceRef="choice_list_dc86ec6e" spirit:configGroups="default">OFF</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C4_RLDIII_NUM_DEVICES</spirit:name>
        <spirit:displayName>num devices</spirit:displayName>
        <spirit:description>num devices</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C4_RLDIII_NUM_DEVICES" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="4" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C4_RLDIII_DATA_WIDTH</spirit:name>
        <spirit:displayName>data width</spirit:displayName>
        <spirit:description>data width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C4_RLDIII_DATA_WIDTH" spirit:choiceRef="choice_list_cf6acb30" spirit:configGroups="default">18</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C4_RLDIII_RLD_ADDR_WIDTH</spirit:name>
        <spirit:displayName>rld addr width </spirit:displayName>
        <spirit:description>rld addr width </spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C4_RLDIII_RLD_ADDR_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="32" spirit:rangeType="long">29</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C4_RLDIII_QK_WIDTH</spirit:name>
        <spirit:displayName>qk width </spirit:displayName>
        <spirit:description>qk width </spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C4_RLDIII_QK_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="8" spirit:rangeType="long">8</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C4_RLDIII_CK_WIDTH</spirit:name>
        <spirit:displayName>ck width </spirit:displayName>
        <spirit:description>ck width </spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C4_RLDIII_CK_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="4" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C4_RLDIII_DK_WIDTH</spirit:name>
        <spirit:displayName>dk width </spirit:displayName>
        <spirit:description>dk width </spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C4_RLDIII_DK_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="4" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C4_RLDIII_DM_WIDTH</spirit:name>
        <spirit:displayName>dm width </spirit:displayName>
        <spirit:description>dm width </spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C4_RLDIII_DM_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="4" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C4_RLDIII_BANK_WIDTH</spirit:name>
        <spirit:displayName>bank width </spirit:displayName>
        <spirit:description>bank width </spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C4_RLDIII_BANK_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="4" spirit:rangeType="long">2</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C4_RLDIII_QVLD_WIDTH</spirit:name>
        <spirit:displayName>qvld width </spirit:displayName>
        <spirit:description>qvld width </spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C4_RLDIII_QVLD_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="4" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="string">
        <spirit:name>C4_RLDIII_DEBUG_PORT</spirit:name>
        <spirit:displayName>Debug Port enable info</spirit:displayName>
        <spirit:description>Debug Port enable info</spirit:description>
        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C4_RLDIII_DEBUG_PORT" spirit:choiceRef="choice_list_dc86ec6e" spirit:configGroups="default">OFF</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C4_RLDX_CMD_PER_CLK</spirit:name>
        <spirit:displayName>cmd per clock</spirit:displayName>
        <spirit:description>cmd per clock</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C4_RLDX_CMD_PER_CLK" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="4" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C4_RLDX_DATA_WIDTH</spirit:name>
        <spirit:displayName>data width</spirit:displayName>
        <spirit:description>data width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C4_RLDX_DATA_WIDTH" spirit:choiceRef="choice_list_cf6acb30" spirit:configGroups="default">18</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C4_RLDX_ADDR_WIDTH</spirit:name>
        <spirit:displayName>addr width </spirit:displayName>
        <spirit:description>addr width </spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C4_RLDX_ADDR_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="32" spirit:rangeType="long">29</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C4_RLDX_BANK_WIDTH</spirit:name>
        <spirit:displayName>bank width </spirit:displayName>
        <spirit:description>bank width </spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C4_RLDX_BANK_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="4" spirit:rangeType="long">2</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C4_RLDX_nCK_PER_CLK</spirit:name>
        <spirit:displayName>nCk per clock</spirit:displayName>
        <spirit:description>nCk per clock</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C4_RLDX_nCK_PER_CLK" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="4" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C4_RLDX_DM_WIDTH</spirit:name>
        <spirit:displayName>dm width </spirit:displayName>
        <spirit:description>dm width </spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C4_RLDX_DM_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="4" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C4_RLDII_CMD_PER_CLK</spirit:name>
        <spirit:displayName>cmd per clock</spirit:displayName>
        <spirit:description>cmd per clock</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C4_RLDII_CMD_PER_CLK" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="4" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C4_RLDII_ADDR_WIDTH</spirit:name>
        <spirit:displayName>addr width </spirit:displayName>
        <spirit:description>addr width </spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C4_RLDII_ADDR_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="32" spirit:rangeType="long">29</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C4_RLDII_nCK_PER_CLK</spirit:name>
        <spirit:displayName>nCk per clock</spirit:displayName>
        <spirit:description>nCk per clock</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C4_RLDII_nCK_PER_CLK" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="4" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C4_RLDIII_CMD_PER_CLK</spirit:name>
        <spirit:displayName>cmd per clock</spirit:displayName>
        <spirit:description>cmd per clock</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C4_RLDIII_CMD_PER_CLK" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="4" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C4_RLDIII_ADDR_WIDTH</spirit:name>
        <spirit:displayName>addr width </spirit:displayName>
        <spirit:description>addr width </spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C4_RLDIII_ADDR_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="32" spirit:rangeType="long">29</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C4_RLDIII_nCK_PER_CLK</spirit:name>
        <spirit:displayName>nCk per clock</spirit:displayName>
        <spirit:description>nCk per clock</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C4_RLDIII_nCK_PER_CLK" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="4" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="string">
        <spirit:name>C4_POLARITY</spirit:name>
        <spirit:displayName>Polarity of the value</spirit:displayName>
        <spirit:description>Polarity of the value</spirit:description>
        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C4_POLARITY" spirit:choiceRef="choice_list_6eff49bd" spirit:configGroups="default">ACTIVE_LOW</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="string">
        <spirit:name>C5_MEM_TYPE</spirit:name>
        <spirit:displayName>identify interface</spirit:displayName>
        <spirit:description>identify interface</spirit:description>
        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C5_MEM_TYPE" spirit:choiceRef="choice_list_b54243b1" spirit:configGroups="default">DDR3</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="string">
        <spirit:name>C5_IS_CLK_SHARED</spirit:name>
        <spirit:displayName>is clk shared</spirit:displayName>
        <spirit:description>is clk shared</spirit:description>
        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C5_IS_CLK_SHARED" spirit:choiceRef="choice_list_d10f4555" spirit:configGroups="default">FALSE</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="string">
        <spirit:name>C5_SYSCLK_TYPE</spirit:name>
        <spirit:displayName>Type of sys clk</spirit:displayName>
        <spirit:description>Type of sys clk</spirit:description>
        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C5_SYSCLK_TYPE" spirit:choiceRef="choice_list_1570a756" spirit:configGroups="default">DIFF</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C5_USE_AXI</spirit:name>
        <spirit:displayName>USE AXI</spirit:displayName>
        <spirit:description>USE AXI</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C5_USE_AXI" spirit:configGroups="default" spirit:minimum="0" spirit:maximum="1" spirit:rangeType="long">0</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="string">
        <spirit:name>C5_ECC</spirit:name>
        <spirit:displayName>ecc enable info</spirit:displayName>
        <spirit:description>ecc enable info</spirit:description>
        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C5_ECC" spirit:choiceRef="choice_list_dc86ec6e" spirit:configGroups="default">OFF</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C5_DDR3_DQ_WIDTH</spirit:name>
        <spirit:displayName>data bus width</spirit:displayName>
        <spirit:description>data bus width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C5_DDR3_DQ_WIDTH" spirit:choiceRef="choice_list_bdb560e1" spirit:configGroups="default">8</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C5_DDR3_DQS_WIDTH</spirit:name>
        <spirit:displayName>data strobe width</spirit:displayName>
        <spirit:description>data strobe width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C5_DDR3_DQS_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="9" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C5_DDR3_ROW_WIDTH</spirit:name>
        <spirit:displayName>row width</spirit:displayName>
        <spirit:description>row width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C5_DDR3_ROW_WIDTH" spirit:configGroups="default" spirit:minimum="13" spirit:maximum="16" spirit:rangeType="long">14</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C5_DDR3_BANK_WIDTH</spirit:name>
        <spirit:displayName>bank width</spirit:displayName>
        <spirit:description>bank width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C5_DDR3_BANK_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="3" spirit:rangeType="long">3</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C5_DDR3_CK_WIDTH</spirit:name>
        <spirit:displayName>clock width</spirit:displayName>
        <spirit:description>clock width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C5_DDR3_CK_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="4" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C5_DDR3_CKE_WIDTH</spirit:name>
        <spirit:displayName>clock enable width</spirit:displayName>
        <spirit:description>clock enable width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C5_DDR3_CKE_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="2" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C5_DDR3_CS_WIDTH</spirit:name>
        <spirit:displayName>chip select width</spirit:displayName>
        <spirit:description>chip select width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C5_DDR3_CS_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="2" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C5_DDR3_nCS_PER_RANK</spirit:name>
        <spirit:displayName>chip select per rank</spirit:displayName>
        <spirit:description>chip select per rank</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C5_DDR3_nCS_PER_RANK" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="4" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C5_DDR3_DM_WIDTH</spirit:name>
        <spirit:displayName>data mask width</spirit:displayName>
        <spirit:description>data mask width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C5_DDR3_DM_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="9" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C5_DDR3_ODT_WIDTH</spirit:name>
        <spirit:displayName>odt width</spirit:displayName>
        <spirit:description>odt width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C5_DDR3_ODT_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="4" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C5_DDR3_USE_CS_PORT</spirit:name>
        <spirit:displayName>CS Port is in use</spirit:displayName>
        <spirit:description>CS Port is in use</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C5_DDR3_USE_CS_PORT" spirit:configGroups="default" spirit:minimum="0" spirit:maximum="1" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C5_DDR3_USE_DM_PORT</spirit:name>
        <spirit:displayName>DM Port is in use</spirit:displayName>
        <spirit:description>DM Port is in use</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C5_DDR3_USE_DM_PORT" spirit:configGroups="default" spirit:minimum="0" spirit:maximum="1" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C5_DDR3_USE_ODT_PORT</spirit:name>
        <spirit:displayName>ODT Port is in use</spirit:displayName>
        <spirit:description>ODT Port is in use</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C5_DDR3_USE_ODT_PORT" spirit:configGroups="default" spirit:minimum="0" spirit:maximum="1" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="string">
        <spirit:name>C5_DDR3_REG_CTRL</spirit:name>
        <spirit:displayName>Indicates Registered DIMM or not</spirit:displayName>
        <spirit:description>Indicates Registered DIMM or not</spirit:description>
        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C5_DDR3_REG_CTRL" spirit:choiceRef="choice_list_dc86ec6e" spirit:configGroups="default">OFF</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C5_DDR3_DQS_CNT_WIDTH</spirit:name>
        <spirit:displayName>DQS count width</spirit:displayName>
        <spirit:description>DQS count width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C5_DDR3_DQS_CNT_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="8" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="string">
        <spirit:name>C5_DDR3_DEBUG_PORT</spirit:name>
        <spirit:displayName>Debug Port enable info</spirit:displayName>
        <spirit:description>Debug Port enable info</spirit:description>
        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C5_DDR3_DEBUG_PORT" spirit:choiceRef="choice_list_dc86ec6e" spirit:configGroups="default">OFF</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C5_DDR2_DQ_WIDTH</spirit:name>
        <spirit:displayName>data bus width</spirit:displayName>
        <spirit:description>data bus width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C5_DDR2_DQ_WIDTH" spirit:choiceRef="choice_list_bdb560e1" spirit:configGroups="default">8</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C5_DDR2_DQS_WIDTH</spirit:name>
        <spirit:displayName>data strobe width</spirit:displayName>
        <spirit:description>data strobe width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C5_DDR2_DQS_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="9" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C5_DDR2_ROW_WIDTH</spirit:name>
        <spirit:displayName>row width</spirit:displayName>
        <spirit:description>row width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C5_DDR2_ROW_WIDTH" spirit:configGroups="default" spirit:minimum="13" spirit:maximum="16" spirit:rangeType="long">14</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C5_DDR2_BANK_WIDTH</spirit:name>
        <spirit:displayName>bank width</spirit:displayName>
        <spirit:description>bank width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C5_DDR2_BANK_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="3" spirit:rangeType="long">3</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C5_DDR2_CK_WIDTH</spirit:name>
        <spirit:displayName>clock width</spirit:displayName>
        <spirit:description>clock width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C5_DDR2_CK_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="4" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C5_DDR2_CKE_WIDTH</spirit:name>
        <spirit:displayName>clock enable width</spirit:displayName>
        <spirit:description>clock enable width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C5_DDR2_CKE_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="2" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C5_DDR2_CS_WIDTH</spirit:name>
        <spirit:displayName>chip select width</spirit:displayName>
        <spirit:description>chip select width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C5_DDR2_CS_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="2" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C5_DDR2_nCS_PER_RANK</spirit:name>
        <spirit:displayName>chip select per rank</spirit:displayName>
        <spirit:description>chip select per rank</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C5_DDR2_nCS_PER_RANK" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="4" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C5_DDR2_DM_WIDTH</spirit:name>
        <spirit:displayName>data mask width</spirit:displayName>
        <spirit:description>data mask width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C5_DDR2_DM_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="9" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C5_DDR2_ODT_WIDTH</spirit:name>
        <spirit:displayName>odt width</spirit:displayName>
        <spirit:description>odt width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C5_DDR2_ODT_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="4" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C5_DDR2_USE_CS_PORT</spirit:name>
        <spirit:displayName>CS Port is in use</spirit:displayName>
        <spirit:description>CS Port is in use</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C5_DDR2_USE_CS_PORT" spirit:configGroups="default" spirit:minimum="0" spirit:maximum="1" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C5_DDR2_USE_DM_PORT</spirit:name>
        <spirit:displayName>DM Port is in use</spirit:displayName>
        <spirit:description>DM Port is in use</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C5_DDR2_USE_DM_PORT" spirit:configGroups="default" spirit:minimum="0" spirit:maximum="1" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C5_DDR2_USE_ODT_PORT</spirit:name>
        <spirit:displayName>ODT Port is in use</spirit:displayName>
        <spirit:description>ODT Port is in use</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C5_DDR2_USE_ODT_PORT" spirit:configGroups="default" spirit:minimum="0" spirit:maximum="1" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="string">
        <spirit:name>C5_DDR2_REG_CTRL</spirit:name>
        <spirit:displayName>Indicates Registered DIMM or not</spirit:displayName>
        <spirit:description>Indicates Registered DIMM or not</spirit:description>
        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C5_DDR2_REG_CTRL" spirit:choiceRef="choice_list_dc86ec6e" spirit:configGroups="default">OFF</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C5_DDR2_DQS_CNT_WIDTH</spirit:name>
        <spirit:displayName>DQS count width</spirit:displayName>
        <spirit:description>DQS count width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C5_DDR2_DQS_CNT_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="8" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="string">
        <spirit:name>C5_DDR2_DEBUG_PORT</spirit:name>
        <spirit:displayName>Debug Port enable info</spirit:displayName>
        <spirit:description>Debug Port enable info</spirit:description>
        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C5_DDR2_DEBUG_PORT" spirit:choiceRef="choice_list_dc86ec6e" spirit:configGroups="default">OFF</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C5_LPDDR2_DQ_WIDTH</spirit:name>
        <spirit:displayName>data bus width</spirit:displayName>
        <spirit:description>data bus width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C5_LPDDR2_DQ_WIDTH" spirit:choiceRef="choice_list_bdb560e1" spirit:configGroups="default">8</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C5_LPDDR2_DQS_WIDTH</spirit:name>
        <spirit:displayName>data strobe width</spirit:displayName>
        <spirit:description>data strobe width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C5_LPDDR2_DQS_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="9" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C5_LPDDR2_ROW_WIDTH</spirit:name>
        <spirit:displayName>row width</spirit:displayName>
        <spirit:description>row width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C5_LPDDR2_ROW_WIDTH" spirit:configGroups="default" spirit:minimum="12" spirit:maximum="16" spirit:rangeType="long">14</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C5_LPDDR2_BANK_WIDTH</spirit:name>
        <spirit:displayName>bank width</spirit:displayName>
        <spirit:description>bank width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C5_LPDDR2_BANK_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="3" spirit:rangeType="long">3</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C5_LPDDR2_CK_WIDTH</spirit:name>
        <spirit:displayName>clock width</spirit:displayName>
        <spirit:description>clock width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C5_LPDDR2_CK_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="4" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C5_LPDDR2_CKE_WIDTH</spirit:name>
        <spirit:displayName>clock enable width</spirit:displayName>
        <spirit:description>clock enable width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C5_LPDDR2_CKE_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="2" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C5_LPDDR2_CS_WIDTH</spirit:name>
        <spirit:displayName>chip select width</spirit:displayName>
        <spirit:description>chip select width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C5_LPDDR2_CS_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="2" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C5_LPDDR2_nCS_PER_RANK</spirit:name>
        <spirit:displayName>chip select per rank</spirit:displayName>
        <spirit:description>chip select per rank</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C5_LPDDR2_nCS_PER_RANK" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="4" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C5_LPDDR2_DM_WIDTH</spirit:name>
        <spirit:displayName>data mask width</spirit:displayName>
        <spirit:description>data mask width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C5_LPDDR2_DM_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="9" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C5_LPDDR2_USE_CS_PORT</spirit:name>
        <spirit:displayName>CS Port is in use</spirit:displayName>
        <spirit:description>CS Port is in use</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C5_LPDDR2_USE_CS_PORT" spirit:configGroups="default" spirit:minimum="0" spirit:maximum="1" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C5_LPDDR2_USE_DM_PORT</spirit:name>
        <spirit:displayName>DM Port is in use</spirit:displayName>
        <spirit:description>DM Port is in use</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C5_LPDDR2_USE_DM_PORT" spirit:configGroups="default" spirit:minimum="0" spirit:maximum="1" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C5_LPDDR2_USE_ODT_PORT</spirit:name>
        <spirit:displayName>ODT Port is in use</spirit:displayName>
        <spirit:description>ODT Port is in use</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C5_LPDDR2_USE_ODT_PORT" spirit:configGroups="default" spirit:minimum="0" spirit:maximum="1" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="string">
        <spirit:name>C5_LPDDR2_REG_CTRL</spirit:name>
        <spirit:displayName>Indicates Registered DIMM or not</spirit:displayName>
        <spirit:description>Indicates Registered DIMM or not</spirit:description>
        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C5_LPDDR2_REG_CTRL" spirit:choiceRef="choice_list_dc86ec6e" spirit:configGroups="default">OFF</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C5_LPDDR2_DQS_CNT_WIDTH</spirit:name>
        <spirit:displayName>DQS count width</spirit:displayName>
        <spirit:description>DQS count width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C5_LPDDR2_DQS_CNT_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="8" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="string">
        <spirit:name>C5_LPDDR2_DEBUG_PORT</spirit:name>
        <spirit:displayName>Debug Port enable info</spirit:displayName>
        <spirit:description>Debug Port enable info</spirit:description>
        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C5_LPDDR2_DEBUG_PORT" spirit:choiceRef="choice_list_dc86ec6e" spirit:configGroups="default">OFF</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C5_DQS_CNT_WIDTH</spirit:name>
        <spirit:displayName>DQS count width</spirit:displayName>
        <spirit:description>DQS count width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C5_DQS_CNT_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="8" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="string">
        <spirit:name>C5_DEBUG_PORT</spirit:name>
        <spirit:displayName>Debug Port enable info</spirit:displayName>
        <spirit:description>Debug Port enable info</spirit:description>
        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C5_DEBUG_PORT" spirit:choiceRef="choice_list_dc86ec6e" spirit:configGroups="default">OFF</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C5_DDRX_ADDR_WIDTH</spirit:name>
        <spirit:displayName>addr width</spirit:displayName>
        <spirit:description>addr width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C5_DDRX_ADDR_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="32" spirit:rangeType="long">8</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C5_DDRX_nCK_PER_CLK</spirit:name>
        <spirit:displayName>nck per clk</spirit:displayName>
        <spirit:description>nck per clk</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C5_DDRX_nCK_PER_CLK" spirit:configGroups="default" spirit:minimum="0" spirit:maximum="4" spirit:rangeType="long">2</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C5_DDRX_DATA_WIDTH</spirit:name>
        <spirit:displayName>datawidth excluding the ECC</spirit:displayName>
        <spirit:description>datawidth excluding the ECC</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C5_DDRX_DATA_WIDTH" spirit:configGroups="default" spirit:minimum="8" spirit:maximum="72" spirit:rangeType="long">8</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C5_DDR3_ADDR_WIDTH</spirit:name>
        <spirit:displayName>addr width</spirit:displayName>
        <spirit:description>addr width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C5_DDR3_ADDR_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="32" spirit:rangeType="long">8</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C5_DDR3_nCK_PER_CLK</spirit:name>
        <spirit:displayName>nck per clk</spirit:displayName>
        <spirit:description>nck per clk</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C5_DDR3_nCK_PER_CLK" spirit:configGroups="default" spirit:minimum="0" spirit:maximum="4" spirit:rangeType="long">2</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C5_DDR3_DATA_WIDTH</spirit:name>
        <spirit:displayName>datawidth excluding the ECC</spirit:displayName>
        <spirit:description>datawidth excluding the ECC</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C5_DDR3_DATA_WIDTH" spirit:configGroups="default" spirit:minimum="8" spirit:maximum="72" spirit:rangeType="long">8</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C5_DDR2_ADDR_WIDTH</spirit:name>
        <spirit:displayName>addr width</spirit:displayName>
        <spirit:description>addr width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C5_DDR2_ADDR_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="32" spirit:rangeType="long">8</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C5_DDR2_nCK_PER_CLK</spirit:name>
        <spirit:displayName>nck per clk</spirit:displayName>
        <spirit:description>nck per clk</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C5_DDR2_nCK_PER_CLK" spirit:configGroups="default" spirit:minimum="0" spirit:maximum="4" spirit:rangeType="long">2</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C5_DDR2_DATA_WIDTH</spirit:name>
        <spirit:displayName>datawidth excluding the ECC</spirit:displayName>
        <spirit:description>datawidth excluding the ECC</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C5_DDR2_DATA_WIDTH" spirit:configGroups="default" spirit:minimum="8" spirit:maximum="72" spirit:rangeType="long">8</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C5_LPDDR2_ADDR_WIDTH</spirit:name>
        <spirit:displayName>addr width</spirit:displayName>
        <spirit:description>addr width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C5_LPDDR2_ADDR_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="32" spirit:rangeType="long">8</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C5_LPDDR2_nCK_PER_CLK</spirit:name>
        <spirit:displayName>nck per clk</spirit:displayName>
        <spirit:description>nck per clk</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C5_LPDDR2_nCK_PER_CLK" spirit:configGroups="default" spirit:minimum="0" spirit:maximum="4" spirit:rangeType="long">2</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C5_LPDDR2_DATA_WIDTH</spirit:name>
        <spirit:displayName>datawidth excluding the ECC</spirit:displayName>
        <spirit:description>datawidth excluding the ECC</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C5_LPDDR2_DATA_WIDTH" spirit:configGroups="default" spirit:minimum="8" spirit:maximum="72" spirit:rangeType="long">8</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="float">
        <spirit:name>C5_FREQ_HZ</spirit:name>
        <spirit:displayName>defines the UI Clk freq</spirit:displayName>
        <spirit:description>defines the UI Clk freq</spirit:description>
        <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C5_FREQ_HZ" spirit:configGroups="default" spirit:minimum="0.0" spirit:maximum="800000000.0" spirit:rangeType="long">100.0</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="float">
        <spirit:name>C5_PHASE</spirit:name>
        <spirit:displayName>defines the UI Clk phase</spirit:displayName>
        <spirit:description>defines the UI Clk phase</spirit:description>
        <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C5_PHASE" spirit:choiceRef="choice_list_c7c132f6" spirit:configGroups="default">0.000</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="string">
        <spirit:name>C5_UI_EXTRA_CLOCKS</spirit:name>
        <spirit:displayName>Enablement of extra clocks</spirit:displayName>
        <spirit:description>Enablement of extra clocks</spirit:description>
        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C5_UI_EXTRA_CLOCKS" spirit:choiceRef="choice_list_d10f4555" spirit:configGroups="default">FALSE</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="float">
        <spirit:name>C5_MMCM_VCO</spirit:name>
        <spirit:displayName>Max possible VCO of MMCM primitive </spirit:displayName>
        <spirit:description>Max possible VCO of MMCM primitive </spirit:description>
        <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C5_MMCM_VCO" spirit:configGroups="default" spirit:minimum="600.0" spirit:maximum="1600.0" spirit:rangeType="long">1200.0</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="float">
        <spirit:name>C5_MMCM_CLKOUT0_FREQ</spirit:name>
        <spirit:displayName>mmcm extra clkout0</spirit:displayName>
        <spirit:description>mmcm extra clkout0</spirit:description>
        <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C5_MMCM_CLKOUT0_FREQ" spirit:configGroups="default" spirit:minimum="0.0" spirit:maximum="800000000.0" spirit:rangeType="long">10.0</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C5_MMCM_CLKOUT1_FREQ</spirit:name>
        <spirit:displayName>mmcm extra clkout1</spirit:displayName>
        <spirit:description>mmcm extra clkout1</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C5_MMCM_CLKOUT1_FREQ" spirit:configGroups="default" spirit:minimum="0.0" spirit:maximum="800000000" spirit:rangeType="long">10</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C5_MMCM_CLKOUT2_FREQ</spirit:name>
        <spirit:displayName>mmcm extra clkout2</spirit:displayName>
        <spirit:description>mmcm extra clkout2</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C5_MMCM_CLKOUT2_FREQ" spirit:configGroups="default" spirit:minimum="0.0" spirit:maximum="800000000" spirit:rangeType="long">10</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C5_MMCM_CLKOUT3_FREQ</spirit:name>
        <spirit:displayName>mmcm extra clkout3</spirit:displayName>
        <spirit:description>mmcm extra clkout3</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C5_MMCM_CLKOUT3_FREQ" spirit:configGroups="default" spirit:minimum="0.0" spirit:maximum="800000000" spirit:rangeType="long">10</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C5_MMCM_CLKOUT4_FREQ</spirit:name>
        <spirit:displayName>mmcm extra clkout4</spirit:displayName>
        <spirit:description>mmcm extra clkout4</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C5_MMCM_CLKOUT4_FREQ" spirit:configGroups="default" spirit:minimum="0.0" spirit:maximum="800000000" spirit:rangeType="long">10</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="string">
        <spirit:name>C5_MMCM_CLKOUT0_EN</spirit:name>
        <spirit:displayName>Indicates Enablement of CLKOUT0</spirit:displayName>
        <spirit:description>Indicates Enablement of CLKOUT0</spirit:description>
        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C5_MMCM_CLKOUT0_EN" spirit:choiceRef="choice_list_e7c484ae" spirit:configGroups="default">FALSE</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="string">
        <spirit:name>C5_MMCM_CLKOUT2_EN</spirit:name>
        <spirit:displayName>Indicates Enablement of CLKOUT2</spirit:displayName>
        <spirit:description>Indicates Enablement of CLKOUT2</spirit:description>
        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C5_MMCM_CLKOUT2_EN" spirit:choiceRef="choice_list_e7c484ae" spirit:configGroups="default">FALSE</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="string">
        <spirit:name>C5_MMCM_CLKOUT1_EN</spirit:name>
        <spirit:displayName>Indicates Enablement of CLKOUT1</spirit:displayName>
        <spirit:description>Indicates Enablement of CLKOUT1</spirit:description>
        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C5_MMCM_CLKOUT1_EN" spirit:choiceRef="choice_list_e7c484ae" spirit:configGroups="default">FALSE</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="string">
        <spirit:name>C5_MMCM_CLKOUT3_EN</spirit:name>
        <spirit:displayName>Indicates Enablement of CLKOUT3</spirit:displayName>
        <spirit:description>Indicates Enablement of CLKOUT3</spirit:description>
        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C5_MMCM_CLKOUT3_EN" spirit:choiceRef="choice_list_e7c484ae" spirit:configGroups="default">FALSE</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="string">
        <spirit:name>C5_MMCM_CLKOUT4_EN</spirit:name>
        <spirit:displayName>Indicates Enablement of CLKOUT4</spirit:displayName>
        <spirit:description>Indicates Enablement of CLKOUT4</spirit:description>
        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C5_MMCM_CLKOUT4_EN" spirit:choiceRef="choice_list_e7c484ae" spirit:configGroups="default">FALSE</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C5_C_S_AXI_CTRL_ID_WIDTH</spirit:name>
        <spirit:displayName>AXI ID Width</spirit:displayName>
        <spirit:description>AXI ID Width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C5_C_S_AXI_CTRL_ID_WIDTH" spirit:configGroups="default" spirit:minimum="0" spirit:maximum="16" spirit:rangeType="long">4</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C5_C_S_AXI_CTRL_DATA_WIDTH</spirit:name>
        <spirit:displayName>AXI Data Width</spirit:displayName>
        <spirit:description>AXI Data Width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C5_C_S_AXI_CTRL_DATA_WIDTH" spirit:choiceRef="choice_list_40181835" spirit:configGroups="default">32</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C5_C_S_AXI_CTRL_ADDR_WIDTH</spirit:name>
        <spirit:displayName>AXI Addr Width</spirit:displayName>
        <spirit:description>AXI Addr Width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C5_C_S_AXI_CTRL_ADDR_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="36" spirit:rangeType="long">32</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C5_C_S_AXI_CTRL_MEM_SIZE</spirit:name>
        <spirit:displayName>Memory Address Space</spirit:displayName>
        <spirit:description>Memory Address Space</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C5_C_S_AXI_CTRL_MEM_SIZE" spirit:configGroups="default" spirit:minimum="0" spirit:maximum="34359738368" spirit:rangeType="long">1048576</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C5_C_S_AXI_ID_WIDTH</spirit:name>
        <spirit:displayName>AXI ID Width</spirit:displayName>
        <spirit:description>AXI ID Width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C5_C_S_AXI_ID_WIDTH" spirit:configGroups="default" spirit:minimum="0" spirit:maximum="16" spirit:rangeType="long">4</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C5_C_S_AXI_DATA_WIDTH</spirit:name>
        <spirit:displayName>AXI Data Width</spirit:displayName>
        <spirit:description>AXI Data Width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C5_C_S_AXI_DATA_WIDTH" spirit:choiceRef="choice_list_40181835" spirit:configGroups="default">32</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C5_C_S_AXI_ADDR_WIDTH</spirit:name>
        <spirit:displayName>AXI Addr Width</spirit:displayName>
        <spirit:description>AXI Addr Width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C5_C_S_AXI_ADDR_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="36" spirit:rangeType="long">32</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C5_C_S_AXI_MEM_SIZE</spirit:name>
        <spirit:displayName>Memory Address Space</spirit:displayName>
        <spirit:description>Memory Address Space</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C5_C_S_AXI_MEM_SIZE" spirit:configGroups="default" spirit:minimum="0" spirit:maximum="34359738368" spirit:rangeType="long">1048576</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C5_QDRIIP_NUM_DEVICES</spirit:name>
        <spirit:displayName>num devices</spirit:displayName>
        <spirit:description>num devices</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C5_QDRIIP_NUM_DEVICES" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="4" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C5_QDRIIP_DATA_WIDTH</spirit:name>
        <spirit:displayName>data width</spirit:displayName>
        <spirit:description>data width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C5_QDRIIP_DATA_WIDTH" spirit:choiceRef="choice_list_cf6acb30" spirit:configGroups="default">18</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C5_QDRIIP_ADDR_WIDTH</spirit:name>
        <spirit:displayName>addr width </spirit:displayName>
        <spirit:description>addr width </spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C5_QDRIIP_ADDR_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="32" spirit:rangeType="long">29</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C5_QDRIIP_BW_WIDTH</spirit:name>
        <spirit:displayName>bw width </spirit:displayName>
        <spirit:description>bw width </spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C5_QDRIIP_BW_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="8" spirit:rangeType="long">8</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="string">
        <spirit:name>C5_QDRIIP_DEBUG_PORT</spirit:name>
        <spirit:displayName>Debug Port enable info</spirit:displayName>
        <spirit:description>Debug Port enable info</spirit:description>
        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C5_QDRIIP_DEBUG_PORT" spirit:choiceRef="choice_list_dc86ec6e" spirit:configGroups="default">OFF</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C5_QDRIIP_BURST_LEN</spirit:name>
        <spirit:displayName>burst len </spirit:displayName>
        <spirit:description>burst len </spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C5_QDRIIP_BURST_LEN" spirit:choiceRef="choice_list_dd2843c6" spirit:configGroups="default">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C5_RLDII_NUM_DEVICES</spirit:name>
        <spirit:displayName>num devices</spirit:displayName>
        <spirit:description>num devices</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C5_RLDII_NUM_DEVICES" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="4" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C5_RLDII_DATA_WIDTH</spirit:name>
        <spirit:displayName>data width</spirit:displayName>
        <spirit:description>data width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C5_RLDII_DATA_WIDTH" spirit:choiceRef="choice_list_cf6acb30" spirit:configGroups="default">18</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C5_RLDII_RLD_ADDR_WIDTH</spirit:name>
        <spirit:displayName>rld addr width </spirit:displayName>
        <spirit:description>rld addr width </spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C5_RLDII_RLD_ADDR_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="32" spirit:rangeType="long">29</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C5_RLDII_QK_WIDTH</spirit:name>
        <spirit:displayName>qk width </spirit:displayName>
        <spirit:description>qk width </spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C5_RLDII_QK_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="8" spirit:rangeType="long">8</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C5_RLDII_CK_WIDTH</spirit:name>
        <spirit:displayName>ck width </spirit:displayName>
        <spirit:description>ck width </spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C5_RLDII_CK_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="4" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C5_RLDII_DK_WIDTH</spirit:name>
        <spirit:displayName>dk width </spirit:displayName>
        <spirit:description>dk width </spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C5_RLDII_DK_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="4" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C5_RLDII_DM_WIDTH</spirit:name>
        <spirit:displayName>dm width </spirit:displayName>
        <spirit:description>dm width </spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C5_RLDII_DM_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="4" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C5_RLDII_BANK_WIDTH</spirit:name>
        <spirit:displayName>bank width </spirit:displayName>
        <spirit:description>bank width </spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C5_RLDII_BANK_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="4" spirit:rangeType="long">2</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C5_RLDII_QVLD_WIDTH</spirit:name>
        <spirit:displayName>qvld width </spirit:displayName>
        <spirit:description>qvld width </spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C5_RLDII_QVLD_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="4" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="string">
        <spirit:name>C5_RLDII_DEBUG_PORT</spirit:name>
        <spirit:displayName>Debug Port enable info</spirit:displayName>
        <spirit:description>Debug Port enable info</spirit:description>
        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C5_RLDII_DEBUG_PORT" spirit:choiceRef="choice_list_dc86ec6e" spirit:configGroups="default">OFF</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C5_RLDIII_NUM_DEVICES</spirit:name>
        <spirit:displayName>num devices</spirit:displayName>
        <spirit:description>num devices</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C5_RLDIII_NUM_DEVICES" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="4" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C5_RLDIII_DATA_WIDTH</spirit:name>
        <spirit:displayName>data width</spirit:displayName>
        <spirit:description>data width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C5_RLDIII_DATA_WIDTH" spirit:choiceRef="choice_list_cf6acb30" spirit:configGroups="default">18</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C5_RLDIII_RLD_ADDR_WIDTH</spirit:name>
        <spirit:displayName>rld addr width </spirit:displayName>
        <spirit:description>rld addr width </spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C5_RLDIII_RLD_ADDR_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="32" spirit:rangeType="long">29</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C5_RLDIII_QK_WIDTH</spirit:name>
        <spirit:displayName>qk width </spirit:displayName>
        <spirit:description>qk width </spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C5_RLDIII_QK_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="8" spirit:rangeType="long">8</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C5_RLDIII_CK_WIDTH</spirit:name>
        <spirit:displayName>ck width </spirit:displayName>
        <spirit:description>ck width </spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C5_RLDIII_CK_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="4" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C5_RLDIII_DK_WIDTH</spirit:name>
        <spirit:displayName>dk width </spirit:displayName>
        <spirit:description>dk width </spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C5_RLDIII_DK_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="4" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C5_RLDIII_DM_WIDTH</spirit:name>
        <spirit:displayName>dm width </spirit:displayName>
        <spirit:description>dm width </spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C5_RLDIII_DM_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="4" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C5_RLDIII_BANK_WIDTH</spirit:name>
        <spirit:displayName>bank width </spirit:displayName>
        <spirit:description>bank width </spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C5_RLDIII_BANK_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="4" spirit:rangeType="long">2</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C5_RLDIII_QVLD_WIDTH</spirit:name>
        <spirit:displayName>qvld width </spirit:displayName>
        <spirit:description>qvld width </spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C5_RLDIII_QVLD_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="4" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="string">
        <spirit:name>C5_RLDIII_DEBUG_PORT</spirit:name>
        <spirit:displayName>Debug Port enable info</spirit:displayName>
        <spirit:description>Debug Port enable info</spirit:description>
        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C5_RLDIII_DEBUG_PORT" spirit:choiceRef="choice_list_dc86ec6e" spirit:configGroups="default">OFF</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C5_RLDX_CMD_PER_CLK</spirit:name>
        <spirit:displayName>cmd per clock</spirit:displayName>
        <spirit:description>cmd per clock</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C5_RLDX_CMD_PER_CLK" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="4" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C5_RLDX_DATA_WIDTH</spirit:name>
        <spirit:displayName>data width</spirit:displayName>
        <spirit:description>data width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C5_RLDX_DATA_WIDTH" spirit:choiceRef="choice_list_cf6acb30" spirit:configGroups="default">18</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C5_RLDX_ADDR_WIDTH</spirit:name>
        <spirit:displayName>addr width </spirit:displayName>
        <spirit:description>addr width </spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C5_RLDX_ADDR_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="32" spirit:rangeType="long">29</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C5_RLDX_BANK_WIDTH</spirit:name>
        <spirit:displayName>bank width </spirit:displayName>
        <spirit:description>bank width </spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C5_RLDX_BANK_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="4" spirit:rangeType="long">2</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C5_RLDX_nCK_PER_CLK</spirit:name>
        <spirit:displayName>nCk per clock</spirit:displayName>
        <spirit:description>nCk per clock</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C5_RLDX_nCK_PER_CLK" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="4" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C5_RLDX_DM_WIDTH</spirit:name>
        <spirit:displayName>dm width </spirit:displayName>
        <spirit:description>dm width </spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C5_RLDX_DM_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="4" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C5_RLDII_CMD_PER_CLK</spirit:name>
        <spirit:displayName>cmd per clock</spirit:displayName>
        <spirit:description>cmd per clock</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C5_RLDII_CMD_PER_CLK" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="4" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C5_RLDII_ADDR_WIDTH</spirit:name>
        <spirit:displayName>addr width </spirit:displayName>
        <spirit:description>addr width </spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C5_RLDII_ADDR_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="32" spirit:rangeType="long">29</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C5_RLDII_nCK_PER_CLK</spirit:name>
        <spirit:displayName>nCk per clock</spirit:displayName>
        <spirit:description>nCk per clock</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C5_RLDII_nCK_PER_CLK" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="4" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C5_RLDIII_CMD_PER_CLK</spirit:name>
        <spirit:displayName>cmd per clock</spirit:displayName>
        <spirit:description>cmd per clock</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C5_RLDIII_CMD_PER_CLK" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="4" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C5_RLDIII_ADDR_WIDTH</spirit:name>
        <spirit:displayName>addr width </spirit:displayName>
        <spirit:description>addr width </spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C5_RLDIII_ADDR_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="32" spirit:rangeType="long">29</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C5_RLDIII_nCK_PER_CLK</spirit:name>
        <spirit:displayName>nCk per clock</spirit:displayName>
        <spirit:description>nCk per clock</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C5_RLDIII_nCK_PER_CLK" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="4" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="string">
        <spirit:name>C5_POLARITY</spirit:name>
        <spirit:displayName>Polarity of the value</spirit:displayName>
        <spirit:description>Polarity of the value</spirit:description>
        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C5_POLARITY" spirit:choiceRef="choice_list_6eff49bd" spirit:configGroups="default">ACTIVE_LOW</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="string">
        <spirit:name>C6_MEM_TYPE</spirit:name>
        <spirit:displayName>identify interface</spirit:displayName>
        <spirit:description>identify interface</spirit:description>
        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C6_MEM_TYPE" spirit:choiceRef="choice_list_b54243b1" spirit:configGroups="default">DDR3</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="string">
        <spirit:name>C6_IS_CLK_SHARED</spirit:name>
        <spirit:displayName>is clk shared</spirit:displayName>
        <spirit:description>is clk shared</spirit:description>
        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C6_IS_CLK_SHARED" spirit:choiceRef="choice_list_d10f4555" spirit:configGroups="default">FALSE</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="string">
        <spirit:name>C6_SYSCLK_TYPE</spirit:name>
        <spirit:displayName>Type of sys clk</spirit:displayName>
        <spirit:description>Type of sys clk</spirit:description>
        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C6_SYSCLK_TYPE" spirit:choiceRef="choice_list_1570a756" spirit:configGroups="default">DIFF</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C6_USE_AXI</spirit:name>
        <spirit:displayName>USE AXI</spirit:displayName>
        <spirit:description>USE AXI</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C6_USE_AXI" spirit:configGroups="default" spirit:minimum="0" spirit:maximum="1" spirit:rangeType="long">0</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="string">
        <spirit:name>C6_ECC</spirit:name>
        <spirit:displayName>ecc enable info</spirit:displayName>
        <spirit:description>ecc enable info</spirit:description>
        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C6_ECC" spirit:choiceRef="choice_list_dc86ec6e" spirit:configGroups="default">OFF</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C6_DDR3_DQ_WIDTH</spirit:name>
        <spirit:displayName>data bus width</spirit:displayName>
        <spirit:description>data bus width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C6_DDR3_DQ_WIDTH" spirit:choiceRef="choice_list_bdb560e1" spirit:configGroups="default">8</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C6_DDR3_DQS_WIDTH</spirit:name>
        <spirit:displayName>data strobe width</spirit:displayName>
        <spirit:description>data strobe width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C6_DDR3_DQS_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="9" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C6_DDR3_ROW_WIDTH</spirit:name>
        <spirit:displayName>row width</spirit:displayName>
        <spirit:description>row width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C6_DDR3_ROW_WIDTH" spirit:configGroups="default" spirit:minimum="13" spirit:maximum="16" spirit:rangeType="long">14</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C6_DDR3_BANK_WIDTH</spirit:name>
        <spirit:displayName>bank width</spirit:displayName>
        <spirit:description>bank width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C6_DDR3_BANK_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="3" spirit:rangeType="long">3</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C6_DDR3_CK_WIDTH</spirit:name>
        <spirit:displayName>clock width</spirit:displayName>
        <spirit:description>clock width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C6_DDR3_CK_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="4" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C6_DDR3_CKE_WIDTH</spirit:name>
        <spirit:displayName>clock enable width</spirit:displayName>
        <spirit:description>clock enable width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C6_DDR3_CKE_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="2" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C6_DDR3_CS_WIDTH</spirit:name>
        <spirit:displayName>chip select width</spirit:displayName>
        <spirit:description>chip select width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C6_DDR3_CS_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="2" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C6_DDR3_nCS_PER_RANK</spirit:name>
        <spirit:displayName>chip select per rank</spirit:displayName>
        <spirit:description>chip select per rank</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C6_DDR3_nCS_PER_RANK" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="4" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C6_DDR3_DM_WIDTH</spirit:name>
        <spirit:displayName>data mask width</spirit:displayName>
        <spirit:description>data mask width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C6_DDR3_DM_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="9" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C6_DDR3_ODT_WIDTH</spirit:name>
        <spirit:displayName>odt width</spirit:displayName>
        <spirit:description>odt width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C6_DDR3_ODT_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="4" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C6_DDR3_USE_CS_PORT</spirit:name>
        <spirit:displayName>CS Port is in use</spirit:displayName>
        <spirit:description>CS Port is in use</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C6_DDR3_USE_CS_PORT" spirit:configGroups="default" spirit:minimum="0" spirit:maximum="1" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C6_DDR3_USE_DM_PORT</spirit:name>
        <spirit:displayName>DM Port is in use</spirit:displayName>
        <spirit:description>DM Port is in use</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C6_DDR3_USE_DM_PORT" spirit:configGroups="default" spirit:minimum="0" spirit:maximum="1" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C6_DDR3_USE_ODT_PORT</spirit:name>
        <spirit:displayName>ODT Port is in use</spirit:displayName>
        <spirit:description>ODT Port is in use</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C6_DDR3_USE_ODT_PORT" spirit:configGroups="default" spirit:minimum="0" spirit:maximum="1" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="string">
        <spirit:name>C6_DDR3_REG_CTRL</spirit:name>
        <spirit:displayName>Indicates Registered DIMM or not</spirit:displayName>
        <spirit:description>Indicates Registered DIMM or not</spirit:description>
        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C6_DDR3_REG_CTRL" spirit:choiceRef="choice_list_dc86ec6e" spirit:configGroups="default">OFF</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C6_DDR3_DQS_CNT_WIDTH</spirit:name>
        <spirit:displayName>DQS count width</spirit:displayName>
        <spirit:description>DQS count width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C6_DDR3_DQS_CNT_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="8" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="string">
        <spirit:name>C6_DDR3_DEBUG_PORT</spirit:name>
        <spirit:displayName>Debug Port enable info</spirit:displayName>
        <spirit:description>Debug Port enable info</spirit:description>
        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C6_DDR3_DEBUG_PORT" spirit:choiceRef="choice_list_dc86ec6e" spirit:configGroups="default">OFF</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C6_DDR2_DQ_WIDTH</spirit:name>
        <spirit:displayName>data bus width</spirit:displayName>
        <spirit:description>data bus width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C6_DDR2_DQ_WIDTH" spirit:choiceRef="choice_list_bdb560e1" spirit:configGroups="default">8</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C6_DDR2_DQS_WIDTH</spirit:name>
        <spirit:displayName>data strobe width</spirit:displayName>
        <spirit:description>data strobe width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C6_DDR2_DQS_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="9" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C6_DDR2_ROW_WIDTH</spirit:name>
        <spirit:displayName>row width</spirit:displayName>
        <spirit:description>row width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C6_DDR2_ROW_WIDTH" spirit:configGroups="default" spirit:minimum="13" spirit:maximum="16" spirit:rangeType="long">14</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C6_DDR2_BANK_WIDTH</spirit:name>
        <spirit:displayName>bank width</spirit:displayName>
        <spirit:description>bank width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C6_DDR2_BANK_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="3" spirit:rangeType="long">3</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C6_DDR2_CK_WIDTH</spirit:name>
        <spirit:displayName>clock width</spirit:displayName>
        <spirit:description>clock width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C6_DDR2_CK_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="4" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C6_DDR2_CKE_WIDTH</spirit:name>
        <spirit:displayName>clock enable width</spirit:displayName>
        <spirit:description>clock enable width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C6_DDR2_CKE_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="2" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C6_DDR2_CS_WIDTH</spirit:name>
        <spirit:displayName>chip select width</spirit:displayName>
        <spirit:description>chip select width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C6_DDR2_CS_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="2" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C6_DDR2_nCS_PER_RANK</spirit:name>
        <spirit:displayName>chip select per rank</spirit:displayName>
        <spirit:description>chip select per rank</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C6_DDR2_nCS_PER_RANK" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="4" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C6_DDR2_DM_WIDTH</spirit:name>
        <spirit:displayName>data mask width</spirit:displayName>
        <spirit:description>data mask width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C6_DDR2_DM_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="9" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C6_DDR2_ODT_WIDTH</spirit:name>
        <spirit:displayName>odt width</spirit:displayName>
        <spirit:description>odt width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C6_DDR2_ODT_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="4" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C6_DDR2_USE_CS_PORT</spirit:name>
        <spirit:displayName>CS Port is in use</spirit:displayName>
        <spirit:description>CS Port is in use</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C6_DDR2_USE_CS_PORT" spirit:configGroups="default" spirit:minimum="0" spirit:maximum="1" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C6_DDR2_USE_DM_PORT</spirit:name>
        <spirit:displayName>DM Port is in use</spirit:displayName>
        <spirit:description>DM Port is in use</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C6_DDR2_USE_DM_PORT" spirit:configGroups="default" spirit:minimum="0" spirit:maximum="1" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C6_DDR2_USE_ODT_PORT</spirit:name>
        <spirit:displayName>ODT Port is in use</spirit:displayName>
        <spirit:description>ODT Port is in use</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C6_DDR2_USE_ODT_PORT" spirit:configGroups="default" spirit:minimum="0" spirit:maximum="1" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="string">
        <spirit:name>C6_DDR2_REG_CTRL</spirit:name>
        <spirit:displayName>Indicates Registered DIMM or not</spirit:displayName>
        <spirit:description>Indicates Registered DIMM or not</spirit:description>
        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C6_DDR2_REG_CTRL" spirit:choiceRef="choice_list_dc86ec6e" spirit:configGroups="default">OFF</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C6_DDR2_DQS_CNT_WIDTH</spirit:name>
        <spirit:displayName>DQS count width</spirit:displayName>
        <spirit:description>DQS count width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C6_DDR2_DQS_CNT_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="8" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="string">
        <spirit:name>C6_DDR2_DEBUG_PORT</spirit:name>
        <spirit:displayName>Debug Port enable info</spirit:displayName>
        <spirit:description>Debug Port enable info</spirit:description>
        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C6_DDR2_DEBUG_PORT" spirit:choiceRef="choice_list_dc86ec6e" spirit:configGroups="default">OFF</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C6_LPDDR2_DQ_WIDTH</spirit:name>
        <spirit:displayName>data bus width</spirit:displayName>
        <spirit:description>data bus width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C6_LPDDR2_DQ_WIDTH" spirit:choiceRef="choice_list_bdb560e1" spirit:configGroups="default">8</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C6_LPDDR2_DQS_WIDTH</spirit:name>
        <spirit:displayName>data strobe width</spirit:displayName>
        <spirit:description>data strobe width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C6_LPDDR2_DQS_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="9" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C6_LPDDR2_ROW_WIDTH</spirit:name>
        <spirit:displayName>row width</spirit:displayName>
        <spirit:description>row width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C6_LPDDR2_ROW_WIDTH" spirit:configGroups="default" spirit:minimum="12" spirit:maximum="16" spirit:rangeType="long">14</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C6_LPDDR2_BANK_WIDTH</spirit:name>
        <spirit:displayName>bank width</spirit:displayName>
        <spirit:description>bank width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C6_LPDDR2_BANK_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="3" spirit:rangeType="long">3</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C6_LPDDR2_CK_WIDTH</spirit:name>
        <spirit:displayName>clock width</spirit:displayName>
        <spirit:description>clock width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C6_LPDDR2_CK_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="4" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C6_LPDDR2_CKE_WIDTH</spirit:name>
        <spirit:displayName>clock enable width</spirit:displayName>
        <spirit:description>clock enable width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C6_LPDDR2_CKE_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="2" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C6_LPDDR2_CS_WIDTH</spirit:name>
        <spirit:displayName>chip select width</spirit:displayName>
        <spirit:description>chip select width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C6_LPDDR2_CS_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="2" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C6_LPDDR2_nCS_PER_RANK</spirit:name>
        <spirit:displayName>chip select per rank</spirit:displayName>
        <spirit:description>chip select per rank</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C6_LPDDR2_nCS_PER_RANK" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="4" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C6_LPDDR2_DM_WIDTH</spirit:name>
        <spirit:displayName>data mask width</spirit:displayName>
        <spirit:description>data mask width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C6_LPDDR2_DM_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="9" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C6_LPDDR2_USE_CS_PORT</spirit:name>
        <spirit:displayName>CS Port is in use</spirit:displayName>
        <spirit:description>CS Port is in use</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C6_LPDDR2_USE_CS_PORT" spirit:configGroups="default" spirit:minimum="0" spirit:maximum="1" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C6_LPDDR2_USE_DM_PORT</spirit:name>
        <spirit:displayName>DM Port is in use</spirit:displayName>
        <spirit:description>DM Port is in use</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C6_LPDDR2_USE_DM_PORT" spirit:configGroups="default" spirit:minimum="0" spirit:maximum="1" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C6_LPDDR2_USE_ODT_PORT</spirit:name>
        <spirit:displayName>ODT Port is in use</spirit:displayName>
        <spirit:description>ODT Port is in use</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C6_LPDDR2_USE_ODT_PORT" spirit:configGroups="default" spirit:minimum="0" spirit:maximum="1" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="string">
        <spirit:name>C6_LPDDR2_REG_CTRL</spirit:name>
        <spirit:displayName>Indicates Registered DIMM or not</spirit:displayName>
        <spirit:description>Indicates Registered DIMM or not</spirit:description>
        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C6_LPDDR2_REG_CTRL" spirit:choiceRef="choice_list_dc86ec6e" spirit:configGroups="default">OFF</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C6_LPDDR2_DQS_CNT_WIDTH</spirit:name>
        <spirit:displayName>DQS count width</spirit:displayName>
        <spirit:description>DQS count width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C6_LPDDR2_DQS_CNT_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="8" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="string">
        <spirit:name>C6_LPDDR2_DEBUG_PORT</spirit:name>
        <spirit:displayName>Debug Port enable info</spirit:displayName>
        <spirit:description>Debug Port enable info</spirit:description>
        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C6_LPDDR2_DEBUG_PORT" spirit:choiceRef="choice_list_dc86ec6e" spirit:configGroups="default">OFF</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C6_DQS_CNT_WIDTH</spirit:name>
        <spirit:displayName>DQS count width</spirit:displayName>
        <spirit:description>DQS count width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C6_DQS_CNT_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="8" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="string">
        <spirit:name>C6_DEBUG_PORT</spirit:name>
        <spirit:displayName>Debug Port enable info</spirit:displayName>
        <spirit:description>Debug Port enable info</spirit:description>
        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C6_DEBUG_PORT" spirit:choiceRef="choice_list_dc86ec6e" spirit:configGroups="default">OFF</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C6_DDRX_ADDR_WIDTH</spirit:name>
        <spirit:displayName>addr width</spirit:displayName>
        <spirit:description>addr width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C6_DDRX_ADDR_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="32" spirit:rangeType="long">8</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C6_DDRX_nCK_PER_CLK</spirit:name>
        <spirit:displayName>nck per clk</spirit:displayName>
        <spirit:description>nck per clk</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C6_DDRX_nCK_PER_CLK" spirit:configGroups="default" spirit:minimum="0" spirit:maximum="4" spirit:rangeType="long">2</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C6_DDRX_DATA_WIDTH</spirit:name>
        <spirit:displayName>datawidth excluding the ECC</spirit:displayName>
        <spirit:description>datawidth excluding the ECC</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C6_DDRX_DATA_WIDTH" spirit:configGroups="default" spirit:minimum="8" spirit:maximum="72" spirit:rangeType="long">8</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C6_DDR3_ADDR_WIDTH</spirit:name>
        <spirit:displayName>addr width</spirit:displayName>
        <spirit:description>addr width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C6_DDR3_ADDR_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="32" spirit:rangeType="long">8</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C6_DDR3_nCK_PER_CLK</spirit:name>
        <spirit:displayName>nck per clk</spirit:displayName>
        <spirit:description>nck per clk</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C6_DDR3_nCK_PER_CLK" spirit:configGroups="default" spirit:minimum="0" spirit:maximum="4" spirit:rangeType="long">2</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C6_DDR3_DATA_WIDTH</spirit:name>
        <spirit:displayName>datawidth excluding the ECC</spirit:displayName>
        <spirit:description>datawidth excluding the ECC</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C6_DDR3_DATA_WIDTH" spirit:configGroups="default" spirit:minimum="8" spirit:maximum="72" spirit:rangeType="long">8</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C6_DDR2_ADDR_WIDTH</spirit:name>
        <spirit:displayName>addr width</spirit:displayName>
        <spirit:description>addr width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C6_DDR2_ADDR_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="32" spirit:rangeType="long">8</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C6_DDR2_nCK_PER_CLK</spirit:name>
        <spirit:displayName>nck per clk</spirit:displayName>
        <spirit:description>nck per clk</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C6_DDR2_nCK_PER_CLK" spirit:configGroups="default" spirit:minimum="0" spirit:maximum="4" spirit:rangeType="long">2</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C6_DDR2_DATA_WIDTH</spirit:name>
        <spirit:displayName>datawidth excluding the ECC</spirit:displayName>
        <spirit:description>datawidth excluding the ECC</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C6_DDR2_DATA_WIDTH" spirit:configGroups="default" spirit:minimum="8" spirit:maximum="72" spirit:rangeType="long">8</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C6_LPDDR2_ADDR_WIDTH</spirit:name>
        <spirit:displayName>addr width</spirit:displayName>
        <spirit:description>addr width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C6_LPDDR2_ADDR_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="32" spirit:rangeType="long">8</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C6_LPDDR2_nCK_PER_CLK</spirit:name>
        <spirit:displayName>nck per clk</spirit:displayName>
        <spirit:description>nck per clk</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C6_LPDDR2_nCK_PER_CLK" spirit:configGroups="default" spirit:minimum="0" spirit:maximum="4" spirit:rangeType="long">2</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C6_LPDDR2_DATA_WIDTH</spirit:name>
        <spirit:displayName>datawidth excluding the ECC</spirit:displayName>
        <spirit:description>datawidth excluding the ECC</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C6_LPDDR2_DATA_WIDTH" spirit:configGroups="default" spirit:minimum="8" spirit:maximum="72" spirit:rangeType="long">8</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="float">
        <spirit:name>C6_FREQ_HZ</spirit:name>
        <spirit:displayName>defines the UI Clk freq</spirit:displayName>
        <spirit:description>defines the UI Clk freq</spirit:description>
        <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C6_FREQ_HZ" spirit:configGroups="default" spirit:minimum="0.0" spirit:maximum="800000000.0" spirit:rangeType="long">100.0</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="float">
        <spirit:name>C6_PHASE</spirit:name>
        <spirit:displayName>defines the UI Clk phase</spirit:displayName>
        <spirit:description>defines the UI Clk phase</spirit:description>
        <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C6_PHASE" spirit:choiceRef="choice_list_c7c132f6" spirit:configGroups="default">0.000</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="string">
        <spirit:name>C6_UI_EXTRA_CLOCKS</spirit:name>
        <spirit:displayName>Enablement of extra clocks</spirit:displayName>
        <spirit:description>Enablement of extra clocks</spirit:description>
        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C6_UI_EXTRA_CLOCKS" spirit:choiceRef="choice_list_d10f4555" spirit:configGroups="default">FALSE</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="float">
        <spirit:name>C6_MMCM_VCO</spirit:name>
        <spirit:displayName>Max possible VCO of MMCM primitive </spirit:displayName>
        <spirit:description>Max possible VCO of MMCM primitive </spirit:description>
        <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C6_MMCM_VCO" spirit:configGroups="default" spirit:minimum="600.0" spirit:maximum="1600.0" spirit:rangeType="long">1200.0</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="float">
        <spirit:name>C6_MMCM_CLKOUT0_FREQ</spirit:name>
        <spirit:displayName>mmcm extra clkout0</spirit:displayName>
        <spirit:description>mmcm extra clkout0</spirit:description>
        <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C6_MMCM_CLKOUT0_FREQ" spirit:configGroups="default" spirit:minimum="0.0" spirit:maximum="800000000.0" spirit:rangeType="long">10.0</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C6_MMCM_CLKOUT1_FREQ</spirit:name>
        <spirit:displayName>mmcm extra clkout1</spirit:displayName>
        <spirit:description>mmcm extra clkout1</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C6_MMCM_CLKOUT1_FREQ" spirit:configGroups="default" spirit:minimum="0.0" spirit:maximum="800000000" spirit:rangeType="long">10</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C6_MMCM_CLKOUT2_FREQ</spirit:name>
        <spirit:displayName>mmcm extra clkout2</spirit:displayName>
        <spirit:description>mmcm extra clkout2</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C6_MMCM_CLKOUT2_FREQ" spirit:configGroups="default" spirit:minimum="0.0" spirit:maximum="800000000" spirit:rangeType="long">10</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C6_MMCM_CLKOUT3_FREQ</spirit:name>
        <spirit:displayName>mmcm extra clkout3</spirit:displayName>
        <spirit:description>mmcm extra clkout3</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C6_MMCM_CLKOUT3_FREQ" spirit:configGroups="default" spirit:minimum="0.0" spirit:maximum="800000000" spirit:rangeType="long">10</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C6_MMCM_CLKOUT4_FREQ</spirit:name>
        <spirit:displayName>mmcm extra clkout4</spirit:displayName>
        <spirit:description>mmcm extra clkout4</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C6_MMCM_CLKOUT4_FREQ" spirit:configGroups="default" spirit:minimum="0.0" spirit:maximum="800000000" spirit:rangeType="long">10</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="string">
        <spirit:name>C6_MMCM_CLKOUT0_EN</spirit:name>
        <spirit:displayName>Indicates Enablement of CLKOUT0</spirit:displayName>
        <spirit:description>Indicates Enablement of CLKOUT0</spirit:description>
        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C6_MMCM_CLKOUT0_EN" spirit:choiceRef="choice_list_e7c484ae" spirit:configGroups="default">FALSE</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="string">
        <spirit:name>C6_MMCM_CLKOUT2_EN</spirit:name>
        <spirit:displayName>Indicates Enablement of CLKOUT2</spirit:displayName>
        <spirit:description>Indicates Enablement of CLKOUT2</spirit:description>
        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C6_MMCM_CLKOUT2_EN" spirit:choiceRef="choice_list_e7c484ae" spirit:configGroups="default">FALSE</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="string">
        <spirit:name>C6_MMCM_CLKOUT1_EN</spirit:name>
        <spirit:displayName>Indicates Enablement of CLKOUT1</spirit:displayName>
        <spirit:description>Indicates Enablement of CLKOUT1</spirit:description>
        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C6_MMCM_CLKOUT1_EN" spirit:choiceRef="choice_list_e7c484ae" spirit:configGroups="default">FALSE</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="string">
        <spirit:name>C6_MMCM_CLKOUT3_EN</spirit:name>
        <spirit:displayName>Indicates Enablement of CLKOUT3</spirit:displayName>
        <spirit:description>Indicates Enablement of CLKOUT3</spirit:description>
        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C6_MMCM_CLKOUT3_EN" spirit:choiceRef="choice_list_e7c484ae" spirit:configGroups="default">FALSE</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="string">
        <spirit:name>C6_MMCM_CLKOUT4_EN</spirit:name>
        <spirit:displayName>Indicates Enablement of CLKOUT4</spirit:displayName>
        <spirit:description>Indicates Enablement of CLKOUT4</spirit:description>
        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C6_MMCM_CLKOUT4_EN" spirit:choiceRef="choice_list_e7c484ae" spirit:configGroups="default">FALSE</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C6_C_S_AXI_CTRL_ID_WIDTH</spirit:name>
        <spirit:displayName>AXI ID Width</spirit:displayName>
        <spirit:description>AXI ID Width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C6_C_S_AXI_CTRL_ID_WIDTH" spirit:configGroups="default" spirit:minimum="0" spirit:maximum="16" spirit:rangeType="long">4</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C6_C_S_AXI_CTRL_DATA_WIDTH</spirit:name>
        <spirit:displayName>AXI Data Width</spirit:displayName>
        <spirit:description>AXI Data Width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C6_C_S_AXI_CTRL_DATA_WIDTH" spirit:choiceRef="choice_list_40181835" spirit:configGroups="default">32</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C6_C_S_AXI_CTRL_ADDR_WIDTH</spirit:name>
        <spirit:displayName>AXI Addr Width</spirit:displayName>
        <spirit:description>AXI Addr Width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C6_C_S_AXI_CTRL_ADDR_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="36" spirit:rangeType="long">32</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C6_C_S_AXI_CTRL_MEM_SIZE</spirit:name>
        <spirit:displayName>Memory Address Space</spirit:displayName>
        <spirit:description>Memory Address Space</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C6_C_S_AXI_CTRL_MEM_SIZE" spirit:configGroups="default" spirit:minimum="0" spirit:maximum="34359738368" spirit:rangeType="long">1048576</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C6_C_S_AXI_ID_WIDTH</spirit:name>
        <spirit:displayName>AXI ID Width</spirit:displayName>
        <spirit:description>AXI ID Width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C6_C_S_AXI_ID_WIDTH" spirit:configGroups="default" spirit:minimum="0" spirit:maximum="16" spirit:rangeType="long">4</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C6_C_S_AXI_DATA_WIDTH</spirit:name>
        <spirit:displayName>AXI Data Width</spirit:displayName>
        <spirit:description>AXI Data Width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C6_C_S_AXI_DATA_WIDTH" spirit:choiceRef="choice_list_40181835" spirit:configGroups="default">32</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C6_C_S_AXI_ADDR_WIDTH</spirit:name>
        <spirit:displayName>AXI Addr Width</spirit:displayName>
        <spirit:description>AXI Addr Width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C6_C_S_AXI_ADDR_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="36" spirit:rangeType="long">32</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C6_C_S_AXI_MEM_SIZE</spirit:name>
        <spirit:displayName>Memory Address Space</spirit:displayName>
        <spirit:description>Memory Address Space</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C6_C_S_AXI_MEM_SIZE" spirit:configGroups="default" spirit:minimum="0" spirit:maximum="34359738368" spirit:rangeType="long">1048576</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C6_QDRIIP_NUM_DEVICES</spirit:name>
        <spirit:displayName>num devices</spirit:displayName>
        <spirit:description>num devices</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C6_QDRIIP_NUM_DEVICES" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="4" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C6_QDRIIP_DATA_WIDTH</spirit:name>
        <spirit:displayName>data width</spirit:displayName>
        <spirit:description>data width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C6_QDRIIP_DATA_WIDTH" spirit:choiceRef="choice_list_cf6acb30" spirit:configGroups="default">18</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C6_QDRIIP_ADDR_WIDTH</spirit:name>
        <spirit:displayName>addr width </spirit:displayName>
        <spirit:description>addr width </spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C6_QDRIIP_ADDR_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="32" spirit:rangeType="long">29</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C6_QDRIIP_BW_WIDTH</spirit:name>
        <spirit:displayName>bw width </spirit:displayName>
        <spirit:description>bw width </spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C6_QDRIIP_BW_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="8" spirit:rangeType="long">8</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="string">
        <spirit:name>C6_QDRIIP_DEBUG_PORT</spirit:name>
        <spirit:displayName>Debug Port enable info</spirit:displayName>
        <spirit:description>Debug Port enable info</spirit:description>
        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C6_QDRIIP_DEBUG_PORT" spirit:choiceRef="choice_list_dc86ec6e" spirit:configGroups="default">OFF</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C6_QDRIIP_BURST_LEN</spirit:name>
        <spirit:displayName>burst len </spirit:displayName>
        <spirit:description>burst len </spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C6_QDRIIP_BURST_LEN" spirit:choiceRef="choice_list_dd2843c6" spirit:configGroups="default">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C6_RLDII_NUM_DEVICES</spirit:name>
        <spirit:displayName>num devices</spirit:displayName>
        <spirit:description>num devices</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C6_RLDII_NUM_DEVICES" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="4" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C6_RLDII_DATA_WIDTH</spirit:name>
        <spirit:displayName>data width</spirit:displayName>
        <spirit:description>data width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C6_RLDII_DATA_WIDTH" spirit:choiceRef="choice_list_cf6acb30" spirit:configGroups="default">18</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C6_RLDII_RLD_ADDR_WIDTH</spirit:name>
        <spirit:displayName>rld addr width </spirit:displayName>
        <spirit:description>rld addr width </spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C6_RLDII_RLD_ADDR_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="32" spirit:rangeType="long">29</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C6_RLDII_QK_WIDTH</spirit:name>
        <spirit:displayName>qk width </spirit:displayName>
        <spirit:description>qk width </spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C6_RLDII_QK_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="8" spirit:rangeType="long">8</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C6_RLDII_CK_WIDTH</spirit:name>
        <spirit:displayName>ck width </spirit:displayName>
        <spirit:description>ck width </spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C6_RLDII_CK_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="4" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C6_RLDII_DK_WIDTH</spirit:name>
        <spirit:displayName>dk width </spirit:displayName>
        <spirit:description>dk width </spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C6_RLDII_DK_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="4" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C6_RLDII_DM_WIDTH</spirit:name>
        <spirit:displayName>dm width </spirit:displayName>
        <spirit:description>dm width </spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C6_RLDII_DM_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="4" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C6_RLDII_BANK_WIDTH</spirit:name>
        <spirit:displayName>bank width </spirit:displayName>
        <spirit:description>bank width </spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C6_RLDII_BANK_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="4" spirit:rangeType="long">2</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C6_RLDII_QVLD_WIDTH</spirit:name>
        <spirit:displayName>qvld width </spirit:displayName>
        <spirit:description>qvld width </spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C6_RLDII_QVLD_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="4" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="string">
        <spirit:name>C6_RLDII_DEBUG_PORT</spirit:name>
        <spirit:displayName>Debug Port enable info</spirit:displayName>
        <spirit:description>Debug Port enable info</spirit:description>
        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C6_RLDII_DEBUG_PORT" spirit:choiceRef="choice_list_dc86ec6e" spirit:configGroups="default">OFF</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C6_RLDIII_NUM_DEVICES</spirit:name>
        <spirit:displayName>num devices</spirit:displayName>
        <spirit:description>num devices</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C6_RLDIII_NUM_DEVICES" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="4" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C6_RLDIII_DATA_WIDTH</spirit:name>
        <spirit:displayName>data width</spirit:displayName>
        <spirit:description>data width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C6_RLDIII_DATA_WIDTH" spirit:choiceRef="choice_list_cf6acb30" spirit:configGroups="default">18</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C6_RLDIII_RLD_ADDR_WIDTH</spirit:name>
        <spirit:displayName>rld addr width </spirit:displayName>
        <spirit:description>rld addr width </spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C6_RLDIII_RLD_ADDR_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="32" spirit:rangeType="long">29</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C6_RLDIII_QK_WIDTH</spirit:name>
        <spirit:displayName>qk width </spirit:displayName>
        <spirit:description>qk width </spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C6_RLDIII_QK_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="8" spirit:rangeType="long">8</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C6_RLDIII_CK_WIDTH</spirit:name>
        <spirit:displayName>ck width </spirit:displayName>
        <spirit:description>ck width </spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C6_RLDIII_CK_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="4" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C6_RLDIII_DK_WIDTH</spirit:name>
        <spirit:displayName>dk width </spirit:displayName>
        <spirit:description>dk width </spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C6_RLDIII_DK_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="4" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C6_RLDIII_DM_WIDTH</spirit:name>
        <spirit:displayName>dm width </spirit:displayName>
        <spirit:description>dm width </spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C6_RLDIII_DM_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="4" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C6_RLDIII_BANK_WIDTH</spirit:name>
        <spirit:displayName>bank width </spirit:displayName>
        <spirit:description>bank width </spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C6_RLDIII_BANK_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="4" spirit:rangeType="long">2</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C6_RLDIII_QVLD_WIDTH</spirit:name>
        <spirit:displayName>qvld width </spirit:displayName>
        <spirit:description>qvld width </spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C6_RLDIII_QVLD_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="4" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="string">
        <spirit:name>C6_RLDIII_DEBUG_PORT</spirit:name>
        <spirit:displayName>Debug Port enable info</spirit:displayName>
        <spirit:description>Debug Port enable info</spirit:description>
        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C6_RLDIII_DEBUG_PORT" spirit:choiceRef="choice_list_dc86ec6e" spirit:configGroups="default">OFF</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C6_RLDX_CMD_PER_CLK</spirit:name>
        <spirit:displayName>cmd per clock</spirit:displayName>
        <spirit:description>cmd per clock</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C6_RLDX_CMD_PER_CLK" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="4" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C6_RLDX_DATA_WIDTH</spirit:name>
        <spirit:displayName>data width</spirit:displayName>
        <spirit:description>data width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C6_RLDX_DATA_WIDTH" spirit:choiceRef="choice_list_cf6acb30" spirit:configGroups="default">18</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C6_RLDX_ADDR_WIDTH</spirit:name>
        <spirit:displayName>addr width </spirit:displayName>
        <spirit:description>addr width </spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C6_RLDX_ADDR_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="32" spirit:rangeType="long">29</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C6_RLDX_BANK_WIDTH</spirit:name>
        <spirit:displayName>bank width </spirit:displayName>
        <spirit:description>bank width </spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C6_RLDX_BANK_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="4" spirit:rangeType="long">2</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C6_RLDX_nCK_PER_CLK</spirit:name>
        <spirit:displayName>nCk per clock</spirit:displayName>
        <spirit:description>nCk per clock</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C6_RLDX_nCK_PER_CLK" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="4" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C6_RLDX_DM_WIDTH</spirit:name>
        <spirit:displayName>dm width </spirit:displayName>
        <spirit:description>dm width </spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C6_RLDX_DM_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="4" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C6_RLDII_CMD_PER_CLK</spirit:name>
        <spirit:displayName>cmd per clock</spirit:displayName>
        <spirit:description>cmd per clock</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C6_RLDII_CMD_PER_CLK" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="4" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C6_RLDII_ADDR_WIDTH</spirit:name>
        <spirit:displayName>addr width </spirit:displayName>
        <spirit:description>addr width </spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C6_RLDII_ADDR_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="32" spirit:rangeType="long">29</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C6_RLDII_nCK_PER_CLK</spirit:name>
        <spirit:displayName>nCk per clock</spirit:displayName>
        <spirit:description>nCk per clock</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C6_RLDII_nCK_PER_CLK" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="4" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C6_RLDIII_CMD_PER_CLK</spirit:name>
        <spirit:displayName>cmd per clock</spirit:displayName>
        <spirit:description>cmd per clock</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C6_RLDIII_CMD_PER_CLK" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="4" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C6_RLDIII_ADDR_WIDTH</spirit:name>
        <spirit:displayName>addr width </spirit:displayName>
        <spirit:description>addr width </spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C6_RLDIII_ADDR_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="32" spirit:rangeType="long">29</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C6_RLDIII_nCK_PER_CLK</spirit:name>
        <spirit:displayName>nCk per clock</spirit:displayName>
        <spirit:description>nCk per clock</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C6_RLDIII_nCK_PER_CLK" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="4" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="string">
        <spirit:name>C6_POLARITY</spirit:name>
        <spirit:displayName>Polarity of the value</spirit:displayName>
        <spirit:description>Polarity of the value</spirit:description>
        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C6_POLARITY" spirit:choiceRef="choice_list_6eff49bd" spirit:configGroups="default">ACTIVE_LOW</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="string">
        <spirit:name>C7_MEM_TYPE</spirit:name>
        <spirit:displayName>identify interface</spirit:displayName>
        <spirit:description>identify interface</spirit:description>
        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C7_MEM_TYPE" spirit:choiceRef="choice_list_b54243b1" spirit:configGroups="default">DDR3</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="string">
        <spirit:name>C7_IS_CLK_SHARED</spirit:name>
        <spirit:displayName>is clk shared</spirit:displayName>
        <spirit:description>is clk shared</spirit:description>
        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C7_IS_CLK_SHARED" spirit:choiceRef="choice_list_d10f4555" spirit:configGroups="default">FALSE</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="string">
        <spirit:name>C7_SYSCLK_TYPE</spirit:name>
        <spirit:displayName>Type of sys clk</spirit:displayName>
        <spirit:description>Type of sys clk</spirit:description>
        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C7_SYSCLK_TYPE" spirit:choiceRef="choice_list_1570a756" spirit:configGroups="default">DIFF</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C7_USE_AXI</spirit:name>
        <spirit:displayName>USE AXI</spirit:displayName>
        <spirit:description>USE AXI</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C7_USE_AXI" spirit:configGroups="default" spirit:minimum="0" spirit:maximum="1" spirit:rangeType="long">0</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="string">
        <spirit:name>C7_ECC</spirit:name>
        <spirit:displayName>ecc enable info</spirit:displayName>
        <spirit:description>ecc enable info</spirit:description>
        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C7_ECC" spirit:choiceRef="choice_list_dc86ec6e" spirit:configGroups="default">OFF</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C7_DDR3_DQ_WIDTH</spirit:name>
        <spirit:displayName>data bus width</spirit:displayName>
        <spirit:description>data bus width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C7_DDR3_DQ_WIDTH" spirit:choiceRef="choice_list_bdb560e1" spirit:configGroups="default">8</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C7_DDR3_DQS_WIDTH</spirit:name>
        <spirit:displayName>data strobe width</spirit:displayName>
        <spirit:description>data strobe width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C7_DDR3_DQS_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="9" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C7_DDR3_ROW_WIDTH</spirit:name>
        <spirit:displayName>row width</spirit:displayName>
        <spirit:description>row width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C7_DDR3_ROW_WIDTH" spirit:configGroups="default" spirit:minimum="13" spirit:maximum="16" spirit:rangeType="long">14</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C7_DDR3_BANK_WIDTH</spirit:name>
        <spirit:displayName>bank width</spirit:displayName>
        <spirit:description>bank width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C7_DDR3_BANK_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="3" spirit:rangeType="long">3</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C7_DDR3_CK_WIDTH</spirit:name>
        <spirit:displayName>clock width</spirit:displayName>
        <spirit:description>clock width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C7_DDR3_CK_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="4" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C7_DDR3_CKE_WIDTH</spirit:name>
        <spirit:displayName>clock enable width</spirit:displayName>
        <spirit:description>clock enable width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C7_DDR3_CKE_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="2" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C7_DDR3_CS_WIDTH</spirit:name>
        <spirit:displayName>chip select width</spirit:displayName>
        <spirit:description>chip select width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C7_DDR3_CS_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="2" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C7_DDR3_nCS_PER_RANK</spirit:name>
        <spirit:displayName>chip select per rank</spirit:displayName>
        <spirit:description>chip select per rank</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C7_DDR3_nCS_PER_RANK" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="4" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C7_DDR3_DM_WIDTH</spirit:name>
        <spirit:displayName>data mask width</spirit:displayName>
        <spirit:description>data mask width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C7_DDR3_DM_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="9" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C7_DDR3_ODT_WIDTH</spirit:name>
        <spirit:displayName>odt width</spirit:displayName>
        <spirit:description>odt width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C7_DDR3_ODT_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="4" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C7_DDR3_USE_CS_PORT</spirit:name>
        <spirit:displayName>CS Port is in use</spirit:displayName>
        <spirit:description>CS Port is in use</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C7_DDR3_USE_CS_PORT" spirit:configGroups="default" spirit:minimum="0" spirit:maximum="1" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C7_DDR3_USE_DM_PORT</spirit:name>
        <spirit:displayName>DM Port is in use</spirit:displayName>
        <spirit:description>DM Port is in use</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C7_DDR3_USE_DM_PORT" spirit:configGroups="default" spirit:minimum="0" spirit:maximum="1" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C7_DDR3_USE_ODT_PORT</spirit:name>
        <spirit:displayName>ODT Port is in use</spirit:displayName>
        <spirit:description>ODT Port is in use</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C7_DDR3_USE_ODT_PORT" spirit:configGroups="default" spirit:minimum="0" spirit:maximum="1" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="string">
        <spirit:name>C7_DDR3_REG_CTRL</spirit:name>
        <spirit:displayName>Indicates Registered DIMM or not</spirit:displayName>
        <spirit:description>Indicates Registered DIMM or not</spirit:description>
        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C7_DDR3_REG_CTRL" spirit:choiceRef="choice_list_dc86ec6e" spirit:configGroups="default">OFF</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C7_DDR3_DQS_CNT_WIDTH</spirit:name>
        <spirit:displayName>DQS count width</spirit:displayName>
        <spirit:description>DQS count width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C7_DDR3_DQS_CNT_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="8" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="string">
        <spirit:name>C7_DDR3_DEBUG_PORT</spirit:name>
        <spirit:displayName>Debug Port enable info</spirit:displayName>
        <spirit:description>Debug Port enable info</spirit:description>
        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C7_DDR3_DEBUG_PORT" spirit:choiceRef="choice_list_dc86ec6e" spirit:configGroups="default">OFF</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C7_DDR2_DQ_WIDTH</spirit:name>
        <spirit:displayName>data bus width</spirit:displayName>
        <spirit:description>data bus width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C7_DDR2_DQ_WIDTH" spirit:choiceRef="choice_list_bdb560e1" spirit:configGroups="default">8</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C7_DDR2_DQS_WIDTH</spirit:name>
        <spirit:displayName>data strobe width</spirit:displayName>
        <spirit:description>data strobe width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C7_DDR2_DQS_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="9" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C7_DDR2_ROW_WIDTH</spirit:name>
        <spirit:displayName>row width</spirit:displayName>
        <spirit:description>row width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C7_DDR2_ROW_WIDTH" spirit:configGroups="default" spirit:minimum="13" spirit:maximum="16" spirit:rangeType="long">14</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C7_DDR2_BANK_WIDTH</spirit:name>
        <spirit:displayName>bank width</spirit:displayName>
        <spirit:description>bank width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C7_DDR2_BANK_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="3" spirit:rangeType="long">3</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C7_DDR2_CK_WIDTH</spirit:name>
        <spirit:displayName>clock width</spirit:displayName>
        <spirit:description>clock width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C7_DDR2_CK_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="4" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C7_DDR2_CKE_WIDTH</spirit:name>
        <spirit:displayName>clock enable width</spirit:displayName>
        <spirit:description>clock enable width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C7_DDR2_CKE_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="2" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C7_DDR2_CS_WIDTH</spirit:name>
        <spirit:displayName>chip select width</spirit:displayName>
        <spirit:description>chip select width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C7_DDR2_CS_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="2" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C7_DDR2_nCS_PER_RANK</spirit:name>
        <spirit:displayName>chip select per rank</spirit:displayName>
        <spirit:description>chip select per rank</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C7_DDR2_nCS_PER_RANK" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="4" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C7_DDR2_DM_WIDTH</spirit:name>
        <spirit:displayName>data mask width</spirit:displayName>
        <spirit:description>data mask width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C7_DDR2_DM_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="9" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C7_DDR2_ODT_WIDTH</spirit:name>
        <spirit:displayName>odt width</spirit:displayName>
        <spirit:description>odt width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C7_DDR2_ODT_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="4" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C7_DDR2_USE_CS_PORT</spirit:name>
        <spirit:displayName>CS Port is in use</spirit:displayName>
        <spirit:description>CS Port is in use</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C7_DDR2_USE_CS_PORT" spirit:configGroups="default" spirit:minimum="0" spirit:maximum="1" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C7_DDR2_USE_DM_PORT</spirit:name>
        <spirit:displayName>DM Port is in use</spirit:displayName>
        <spirit:description>DM Port is in use</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C7_DDR2_USE_DM_PORT" spirit:configGroups="default" spirit:minimum="0" spirit:maximum="1" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C7_DDR2_USE_ODT_PORT</spirit:name>
        <spirit:displayName>ODT Port is in use</spirit:displayName>
        <spirit:description>ODT Port is in use</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C7_DDR2_USE_ODT_PORT" spirit:configGroups="default" spirit:minimum="0" spirit:maximum="1" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="string">
        <spirit:name>C7_DDR2_REG_CTRL</spirit:name>
        <spirit:displayName>Indicates Registered DIMM or not</spirit:displayName>
        <spirit:description>Indicates Registered DIMM or not</spirit:description>
        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C7_DDR2_REG_CTRL" spirit:choiceRef="choice_list_dc86ec6e" spirit:configGroups="default">OFF</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C7_DDR2_DQS_CNT_WIDTH</spirit:name>
        <spirit:displayName>DQS count width</spirit:displayName>
        <spirit:description>DQS count width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C7_DDR2_DQS_CNT_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="8" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="string">
        <spirit:name>C7_DDR2_DEBUG_PORT</spirit:name>
        <spirit:displayName>Debug Port enable info</spirit:displayName>
        <spirit:description>Debug Port enable info</spirit:description>
        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C7_DDR2_DEBUG_PORT" spirit:choiceRef="choice_list_dc86ec6e" spirit:configGroups="default">OFF</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C7_LPDDR2_DQ_WIDTH</spirit:name>
        <spirit:displayName>data bus width</spirit:displayName>
        <spirit:description>data bus width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C7_LPDDR2_DQ_WIDTH" spirit:choiceRef="choice_list_bdb560e1" spirit:configGroups="default">8</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C7_LPDDR2_DQS_WIDTH</spirit:name>
        <spirit:displayName>data strobe width</spirit:displayName>
        <spirit:description>data strobe width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C7_LPDDR2_DQS_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="9" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C7_LPDDR2_ROW_WIDTH</spirit:name>
        <spirit:displayName>row width</spirit:displayName>
        <spirit:description>row width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C7_LPDDR2_ROW_WIDTH" spirit:configGroups="default" spirit:minimum="12" spirit:maximum="16" spirit:rangeType="long">14</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C7_LPDDR2_BANK_WIDTH</spirit:name>
        <spirit:displayName>bank width</spirit:displayName>
        <spirit:description>bank width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C7_LPDDR2_BANK_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="3" spirit:rangeType="long">3</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C7_LPDDR2_CK_WIDTH</spirit:name>
        <spirit:displayName>clock width</spirit:displayName>
        <spirit:description>clock width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C7_LPDDR2_CK_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="4" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C7_LPDDR2_CKE_WIDTH</spirit:name>
        <spirit:displayName>clock enable width</spirit:displayName>
        <spirit:description>clock enable width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C7_LPDDR2_CKE_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="2" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C7_LPDDR2_CS_WIDTH</spirit:name>
        <spirit:displayName>chip select width</spirit:displayName>
        <spirit:description>chip select width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C7_LPDDR2_CS_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="2" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C7_LPDDR2_nCS_PER_RANK</spirit:name>
        <spirit:displayName>chip select per rank</spirit:displayName>
        <spirit:description>chip select per rank</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C7_LPDDR2_nCS_PER_RANK" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="4" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C7_LPDDR2_DM_WIDTH</spirit:name>
        <spirit:displayName>data mask width</spirit:displayName>
        <spirit:description>data mask width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C7_LPDDR2_DM_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="9" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C7_LPDDR2_USE_CS_PORT</spirit:name>
        <spirit:displayName>CS Port is in use</spirit:displayName>
        <spirit:description>CS Port is in use</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C7_LPDDR2_USE_CS_PORT" spirit:configGroups="default" spirit:minimum="0" spirit:maximum="1" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C7_LPDDR2_USE_DM_PORT</spirit:name>
        <spirit:displayName>DM Port is in use</spirit:displayName>
        <spirit:description>DM Port is in use</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C7_LPDDR2_USE_DM_PORT" spirit:configGroups="default" spirit:minimum="0" spirit:maximum="1" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C7_LPDDR2_USE_ODT_PORT</spirit:name>
        <spirit:displayName>ODT Port is in use</spirit:displayName>
        <spirit:description>ODT Port is in use</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C7_LPDDR2_USE_ODT_PORT" spirit:configGroups="default" spirit:minimum="0" spirit:maximum="1" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="string">
        <spirit:name>C7_LPDDR2_REG_CTRL</spirit:name>
        <spirit:displayName>Indicates Registered DIMM or not</spirit:displayName>
        <spirit:description>Indicates Registered DIMM or not</spirit:description>
        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C7_LPDDR2_REG_CTRL" spirit:choiceRef="choice_list_dc86ec6e" spirit:configGroups="default">OFF</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C7_LPDDR2_DQS_CNT_WIDTH</spirit:name>
        <spirit:displayName>DQS count width</spirit:displayName>
        <spirit:description>DQS count width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C7_LPDDR2_DQS_CNT_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="8" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="string">
        <spirit:name>C7_LPDDR2_DEBUG_PORT</spirit:name>
        <spirit:displayName>Debug Port enable info</spirit:displayName>
        <spirit:description>Debug Port enable info</spirit:description>
        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C7_LPDDR2_DEBUG_PORT" spirit:choiceRef="choice_list_dc86ec6e" spirit:configGroups="default">OFF</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C7_DQS_CNT_WIDTH</spirit:name>
        <spirit:displayName>DQS count width</spirit:displayName>
        <spirit:description>DQS count width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C7_DQS_CNT_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="8" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="string">
        <spirit:name>C7_DEBUG_PORT</spirit:name>
        <spirit:displayName>Debug Port enable info</spirit:displayName>
        <spirit:description>Debug Port enable info</spirit:description>
        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C7_DEBUG_PORT" spirit:choiceRef="choice_list_dc86ec6e" spirit:configGroups="default">OFF</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C7_DDRX_ADDR_WIDTH</spirit:name>
        <spirit:displayName>addr width</spirit:displayName>
        <spirit:description>addr width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C7_DDRX_ADDR_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="32" spirit:rangeType="long">8</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C7_DDRX_nCK_PER_CLK</spirit:name>
        <spirit:displayName>nck per clk</spirit:displayName>
        <spirit:description>nck per clk</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C7_DDRX_nCK_PER_CLK" spirit:configGroups="default" spirit:minimum="0" spirit:maximum="4" spirit:rangeType="long">2</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C7_DDRX_DATA_WIDTH</spirit:name>
        <spirit:displayName>datawidth excluding the ECC</spirit:displayName>
        <spirit:description>datawidth excluding the ECC</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C7_DDRX_DATA_WIDTH" spirit:configGroups="default" spirit:minimum="8" spirit:maximum="72" spirit:rangeType="long">8</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C7_DDR3_ADDR_WIDTH</spirit:name>
        <spirit:displayName>addr width</spirit:displayName>
        <spirit:description>addr width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C7_DDR3_ADDR_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="32" spirit:rangeType="long">8</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C7_DDR3_nCK_PER_CLK</spirit:name>
        <spirit:displayName>nck per clk</spirit:displayName>
        <spirit:description>nck per clk</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C7_DDR3_nCK_PER_CLK" spirit:configGroups="default" spirit:minimum="0" spirit:maximum="4" spirit:rangeType="long">2</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C7_DDR3_DATA_WIDTH</spirit:name>
        <spirit:displayName>datawidth excluding the ECC</spirit:displayName>
        <spirit:description>datawidth excluding the ECC</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C7_DDR3_DATA_WIDTH" spirit:configGroups="default" spirit:minimum="8" spirit:maximum="72" spirit:rangeType="long">8</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C7_DDR2_ADDR_WIDTH</spirit:name>
        <spirit:displayName>addr width</spirit:displayName>
        <spirit:description>addr width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C7_DDR2_ADDR_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="32" spirit:rangeType="long">8</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C7_DDR2_nCK_PER_CLK</spirit:name>
        <spirit:displayName>nck per clk</spirit:displayName>
        <spirit:description>nck per clk</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C7_DDR2_nCK_PER_CLK" spirit:configGroups="default" spirit:minimum="0" spirit:maximum="4" spirit:rangeType="long">2</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C7_DDR2_DATA_WIDTH</spirit:name>
        <spirit:displayName>datawidth excluding the ECC</spirit:displayName>
        <spirit:description>datawidth excluding the ECC</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C7_DDR2_DATA_WIDTH" spirit:configGroups="default" spirit:minimum="8" spirit:maximum="72" spirit:rangeType="long">8</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C7_LPDDR2_ADDR_WIDTH</spirit:name>
        <spirit:displayName>addr width</spirit:displayName>
        <spirit:description>addr width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C7_LPDDR2_ADDR_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="32" spirit:rangeType="long">8</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C7_LPDDR2_nCK_PER_CLK</spirit:name>
        <spirit:displayName>nck per clk</spirit:displayName>
        <spirit:description>nck per clk</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C7_LPDDR2_nCK_PER_CLK" spirit:configGroups="default" spirit:minimum="0" spirit:maximum="4" spirit:rangeType="long">2</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C7_LPDDR2_DATA_WIDTH</spirit:name>
        <spirit:displayName>datawidth excluding the ECC</spirit:displayName>
        <spirit:description>datawidth excluding the ECC</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C7_LPDDR2_DATA_WIDTH" spirit:configGroups="default" spirit:minimum="8" spirit:maximum="72" spirit:rangeType="long">8</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="float">
        <spirit:name>C7_FREQ_HZ</spirit:name>
        <spirit:displayName>defines the UI Clk freq</spirit:displayName>
        <spirit:description>defines the UI Clk freq</spirit:description>
        <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C7_FREQ_HZ" spirit:configGroups="default" spirit:minimum="0.0" spirit:maximum="800000000.0" spirit:rangeType="long">100.0</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="float">
        <spirit:name>C7_PHASE</spirit:name>
        <spirit:displayName>defines the UI Clk phase</spirit:displayName>
        <spirit:description>defines the UI Clk phase</spirit:description>
        <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C7_PHASE" spirit:choiceRef="choice_list_c7c132f6" spirit:configGroups="default">0.000</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="string">
        <spirit:name>C7_UI_EXTRA_CLOCKS</spirit:name>
        <spirit:displayName>Enablement of extra clocks</spirit:displayName>
        <spirit:description>Enablement of extra clocks</spirit:description>
        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C7_UI_EXTRA_CLOCKS" spirit:choiceRef="choice_list_d10f4555" spirit:configGroups="default">FALSE</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="float">
        <spirit:name>C7_MMCM_VCO</spirit:name>
        <spirit:displayName>Max possible VCO of MMCM primitive </spirit:displayName>
        <spirit:description>Max possible VCO of MMCM primitive </spirit:description>
        <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C7_MMCM_VCO" spirit:configGroups="default" spirit:minimum="600.0" spirit:maximum="1600.0" spirit:rangeType="long">1200.0</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="float">
        <spirit:name>C7_MMCM_CLKOUT0_FREQ</spirit:name>
        <spirit:displayName>mmcm extra clkout0</spirit:displayName>
        <spirit:description>mmcm extra clkout0</spirit:description>
        <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C7_MMCM_CLKOUT0_FREQ" spirit:configGroups="default" spirit:minimum="0.0" spirit:maximum="800000000.0" spirit:rangeType="long">10.0</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C7_MMCM_CLKOUT1_FREQ</spirit:name>
        <spirit:displayName>mmcm extra clkout1</spirit:displayName>
        <spirit:description>mmcm extra clkout1</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C7_MMCM_CLKOUT1_FREQ" spirit:configGroups="default" spirit:minimum="0.0" spirit:maximum="800000000" spirit:rangeType="long">10</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C7_MMCM_CLKOUT2_FREQ</spirit:name>
        <spirit:displayName>mmcm extra clkout2</spirit:displayName>
        <spirit:description>mmcm extra clkout2</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C7_MMCM_CLKOUT2_FREQ" spirit:configGroups="default" spirit:minimum="0.0" spirit:maximum="800000000" spirit:rangeType="long">10</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C7_MMCM_CLKOUT3_FREQ</spirit:name>
        <spirit:displayName>mmcm extra clkout3</spirit:displayName>
        <spirit:description>mmcm extra clkout3</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C7_MMCM_CLKOUT3_FREQ" spirit:configGroups="default" spirit:minimum="0.0" spirit:maximum="800000000" spirit:rangeType="long">10</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C7_MMCM_CLKOUT4_FREQ</spirit:name>
        <spirit:displayName>mmcm extra clkout4</spirit:displayName>
        <spirit:description>mmcm extra clkout4</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C7_MMCM_CLKOUT4_FREQ" spirit:configGroups="default" spirit:minimum="0.0" spirit:maximum="800000000" spirit:rangeType="long">10</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="string">
        <spirit:name>C7_MMCM_CLKOUT0_EN</spirit:name>
        <spirit:displayName>Indicates Enablement of CLKOUT0</spirit:displayName>
        <spirit:description>Indicates Enablement of CLKOUT0</spirit:description>
        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C7_MMCM_CLKOUT0_EN" spirit:choiceRef="choice_list_e7c484ae" spirit:configGroups="default">FALSE</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="string">
        <spirit:name>C7_MMCM_CLKOUT2_EN</spirit:name>
        <spirit:displayName>Indicates Enablement of CLKOUT2</spirit:displayName>
        <spirit:description>Indicates Enablement of CLKOUT2</spirit:description>
        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C7_MMCM_CLKOUT2_EN" spirit:choiceRef="choice_list_e7c484ae" spirit:configGroups="default">FALSE</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="string">
        <spirit:name>C7_MMCM_CLKOUT1_EN</spirit:name>
        <spirit:displayName>Indicates Enablement of CLKOUT1</spirit:displayName>
        <spirit:description>Indicates Enablement of CLKOUT1</spirit:description>
        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C7_MMCM_CLKOUT1_EN" spirit:choiceRef="choice_list_e7c484ae" spirit:configGroups="default">FALSE</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="string">
        <spirit:name>C7_MMCM_CLKOUT3_EN</spirit:name>
        <spirit:displayName>Indicates Enablement of CLKOUT3</spirit:displayName>
        <spirit:description>Indicates Enablement of CLKOUT3</spirit:description>
        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C7_MMCM_CLKOUT3_EN" spirit:choiceRef="choice_list_e7c484ae" spirit:configGroups="default">FALSE</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="string">
        <spirit:name>C7_MMCM_CLKOUT4_EN</spirit:name>
        <spirit:displayName>Indicates Enablement of CLKOUT4</spirit:displayName>
        <spirit:description>Indicates Enablement of CLKOUT4</spirit:description>
        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C7_MMCM_CLKOUT4_EN" spirit:choiceRef="choice_list_e7c484ae" spirit:configGroups="default">FALSE</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C7_C_S_AXI_CTRL_ID_WIDTH</spirit:name>
        <spirit:displayName>AXI ID Width</spirit:displayName>
        <spirit:description>AXI ID Width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C7_C_S_AXI_CTRL_ID_WIDTH" spirit:configGroups="default" spirit:minimum="0" spirit:maximum="16" spirit:rangeType="long">4</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C7_C_S_AXI_CTRL_DATA_WIDTH</spirit:name>
        <spirit:displayName>AXI Data Width</spirit:displayName>
        <spirit:description>AXI Data Width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C7_C_S_AXI_CTRL_DATA_WIDTH" spirit:choiceRef="choice_list_40181835" spirit:configGroups="default">32</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C7_C_S_AXI_CTRL_ADDR_WIDTH</spirit:name>
        <spirit:displayName>AXI Addr Width</spirit:displayName>
        <spirit:description>AXI Addr Width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C7_C_S_AXI_CTRL_ADDR_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="36" spirit:rangeType="long">32</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C7_C_S_AXI_CTRL_MEM_SIZE</spirit:name>
        <spirit:displayName>Memory Address Space</spirit:displayName>
        <spirit:description>Memory Address Space</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C7_C_S_AXI_CTRL_MEM_SIZE" spirit:configGroups="default" spirit:minimum="0" spirit:maximum="34359738368" spirit:rangeType="long">1048576</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C7_C_S_AXI_ID_WIDTH</spirit:name>
        <spirit:displayName>AXI ID Width</spirit:displayName>
        <spirit:description>AXI ID Width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C7_C_S_AXI_ID_WIDTH" spirit:configGroups="default" spirit:minimum="0" spirit:maximum="16" spirit:rangeType="long">4</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C7_C_S_AXI_DATA_WIDTH</spirit:name>
        <spirit:displayName>AXI Data Width</spirit:displayName>
        <spirit:description>AXI Data Width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C7_C_S_AXI_DATA_WIDTH" spirit:choiceRef="choice_list_40181835" spirit:configGroups="default">32</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C7_C_S_AXI_ADDR_WIDTH</spirit:name>
        <spirit:displayName>AXI Addr Width</spirit:displayName>
        <spirit:description>AXI Addr Width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C7_C_S_AXI_ADDR_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="36" spirit:rangeType="long">32</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C7_C_S_AXI_MEM_SIZE</spirit:name>
        <spirit:displayName>Memory Address Space</spirit:displayName>
        <spirit:description>Memory Address Space</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C7_C_S_AXI_MEM_SIZE" spirit:configGroups="default" spirit:minimum="0" spirit:maximum="34359738368" spirit:rangeType="long">1048576</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C7_QDRIIP_NUM_DEVICES</spirit:name>
        <spirit:displayName>num devices</spirit:displayName>
        <spirit:description>num devices</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C7_QDRIIP_NUM_DEVICES" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="4" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C7_QDRIIP_DATA_WIDTH</spirit:name>
        <spirit:displayName>data width</spirit:displayName>
        <spirit:description>data width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C7_QDRIIP_DATA_WIDTH" spirit:choiceRef="choice_list_cf6acb30" spirit:configGroups="default">18</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C7_QDRIIP_ADDR_WIDTH</spirit:name>
        <spirit:displayName>addr width </spirit:displayName>
        <spirit:description>addr width </spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C7_QDRIIP_ADDR_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="32" spirit:rangeType="long">29</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C7_QDRIIP_BW_WIDTH</spirit:name>
        <spirit:displayName>bw width </spirit:displayName>
        <spirit:description>bw width </spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C7_QDRIIP_BW_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="8" spirit:rangeType="long">8</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="string">
        <spirit:name>C7_QDRIIP_DEBUG_PORT</spirit:name>
        <spirit:displayName>Debug Port enable info</spirit:displayName>
        <spirit:description>Debug Port enable info</spirit:description>
        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C7_QDRIIP_DEBUG_PORT" spirit:choiceRef="choice_list_dc86ec6e" spirit:configGroups="default">OFF</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C7_QDRIIP_BURST_LEN</spirit:name>
        <spirit:displayName>burst len </spirit:displayName>
        <spirit:description>burst len </spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C7_QDRIIP_BURST_LEN" spirit:choiceRef="choice_list_dd2843c6" spirit:configGroups="default">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C7_RLDII_NUM_DEVICES</spirit:name>
        <spirit:displayName>num devices</spirit:displayName>
        <spirit:description>num devices</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C7_RLDII_NUM_DEVICES" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="4" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C7_RLDII_DATA_WIDTH</spirit:name>
        <spirit:displayName>data width</spirit:displayName>
        <spirit:description>data width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C7_RLDII_DATA_WIDTH" spirit:choiceRef="choice_list_cf6acb30" spirit:configGroups="default">18</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C7_RLDII_RLD_ADDR_WIDTH</spirit:name>
        <spirit:displayName>rld addr width </spirit:displayName>
        <spirit:description>rld addr width </spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C7_RLDII_RLD_ADDR_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="32" spirit:rangeType="long">29</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C7_RLDII_QK_WIDTH</spirit:name>
        <spirit:displayName>qk width </spirit:displayName>
        <spirit:description>qk width </spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C7_RLDII_QK_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="8" spirit:rangeType="long">8</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C7_RLDII_CK_WIDTH</spirit:name>
        <spirit:displayName>ck width </spirit:displayName>
        <spirit:description>ck width </spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C7_RLDII_CK_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="4" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C7_RLDII_DK_WIDTH</spirit:name>
        <spirit:displayName>dk width </spirit:displayName>
        <spirit:description>dk width </spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C7_RLDII_DK_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="4" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C7_RLDII_DM_WIDTH</spirit:name>
        <spirit:displayName>dm width </spirit:displayName>
        <spirit:description>dm width </spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C7_RLDII_DM_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="4" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C7_RLDII_BANK_WIDTH</spirit:name>
        <spirit:displayName>bank width </spirit:displayName>
        <spirit:description>bank width </spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C7_RLDII_BANK_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="4" spirit:rangeType="long">2</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C7_RLDII_QVLD_WIDTH</spirit:name>
        <spirit:displayName>qvld width </spirit:displayName>
        <spirit:description>qvld width </spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C7_RLDII_QVLD_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="4" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="string">
        <spirit:name>C7_RLDII_DEBUG_PORT</spirit:name>
        <spirit:displayName>Debug Port enable info</spirit:displayName>
        <spirit:description>Debug Port enable info</spirit:description>
        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C7_RLDII_DEBUG_PORT" spirit:choiceRef="choice_list_dc86ec6e" spirit:configGroups="default">OFF</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C7_RLDIII_NUM_DEVICES</spirit:name>
        <spirit:displayName>num devices</spirit:displayName>
        <spirit:description>num devices</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C7_RLDIII_NUM_DEVICES" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="4" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C7_RLDIII_DATA_WIDTH</spirit:name>
        <spirit:displayName>data width</spirit:displayName>
        <spirit:description>data width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C7_RLDIII_DATA_WIDTH" spirit:choiceRef="choice_list_cf6acb30" spirit:configGroups="default">18</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C7_RLDIII_RLD_ADDR_WIDTH</spirit:name>
        <spirit:displayName>rld addr width </spirit:displayName>
        <spirit:description>rld addr width </spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C7_RLDIII_RLD_ADDR_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="32" spirit:rangeType="long">29</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C7_RLDIII_QK_WIDTH</spirit:name>
        <spirit:displayName>qk width </spirit:displayName>
        <spirit:description>qk width </spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C7_RLDIII_QK_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="8" spirit:rangeType="long">8</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C7_RLDIII_CK_WIDTH</spirit:name>
        <spirit:displayName>ck width </spirit:displayName>
        <spirit:description>ck width </spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C7_RLDIII_CK_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="4" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C7_RLDIII_DK_WIDTH</spirit:name>
        <spirit:displayName>dk width </spirit:displayName>
        <spirit:description>dk width </spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C7_RLDIII_DK_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="4" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C7_RLDIII_DM_WIDTH</spirit:name>
        <spirit:displayName>dm width </spirit:displayName>
        <spirit:description>dm width </spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C7_RLDIII_DM_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="4" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C7_RLDIII_BANK_WIDTH</spirit:name>
        <spirit:displayName>bank width </spirit:displayName>
        <spirit:description>bank width </spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C7_RLDIII_BANK_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="4" spirit:rangeType="long">2</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C7_RLDIII_QVLD_WIDTH</spirit:name>
        <spirit:displayName>qvld width </spirit:displayName>
        <spirit:description>qvld width </spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C7_RLDIII_QVLD_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="4" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="string">
        <spirit:name>C7_RLDIII_DEBUG_PORT</spirit:name>
        <spirit:displayName>Debug Port enable info</spirit:displayName>
        <spirit:description>Debug Port enable info</spirit:description>
        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C7_RLDIII_DEBUG_PORT" spirit:choiceRef="choice_list_dc86ec6e" spirit:configGroups="default">OFF</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C7_RLDX_CMD_PER_CLK</spirit:name>
        <spirit:displayName>cmd per clock</spirit:displayName>
        <spirit:description>cmd per clock</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C7_RLDX_CMD_PER_CLK" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="4" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C7_RLDX_DATA_WIDTH</spirit:name>
        <spirit:displayName>data width</spirit:displayName>
        <spirit:description>data width</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C7_RLDX_DATA_WIDTH" spirit:choiceRef="choice_list_cf6acb30" spirit:configGroups="default">18</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C7_RLDX_ADDR_WIDTH</spirit:name>
        <spirit:displayName>addr width </spirit:displayName>
        <spirit:description>addr width </spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C7_RLDX_ADDR_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="32" spirit:rangeType="long">29</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C7_RLDX_BANK_WIDTH</spirit:name>
        <spirit:displayName>bank width </spirit:displayName>
        <spirit:description>bank width </spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C7_RLDX_BANK_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="4" spirit:rangeType="long">2</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C7_RLDX_nCK_PER_CLK</spirit:name>
        <spirit:displayName>nCk per clock</spirit:displayName>
        <spirit:description>nCk per clock</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C7_RLDX_nCK_PER_CLK" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="4" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C7_RLDX_DM_WIDTH</spirit:name>
        <spirit:displayName>dm width </spirit:displayName>
        <spirit:description>dm width </spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C7_RLDX_DM_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="4" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C7_RLDII_CMD_PER_CLK</spirit:name>
        <spirit:displayName>cmd per clock</spirit:displayName>
        <spirit:description>cmd per clock</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C7_RLDII_CMD_PER_CLK" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="4" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C7_RLDII_ADDR_WIDTH</spirit:name>
        <spirit:displayName>addr width </spirit:displayName>
        <spirit:description>addr width </spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C7_RLDII_ADDR_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="32" spirit:rangeType="long">29</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C7_RLDII_nCK_PER_CLK</spirit:name>
        <spirit:displayName>nCk per clock</spirit:displayName>
        <spirit:description>nCk per clock</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C7_RLDII_nCK_PER_CLK" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="4" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C7_RLDIII_CMD_PER_CLK</spirit:name>
        <spirit:displayName>cmd per clock</spirit:displayName>
        <spirit:description>cmd per clock</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C7_RLDIII_CMD_PER_CLK" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="4" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C7_RLDIII_ADDR_WIDTH</spirit:name>
        <spirit:displayName>addr width </spirit:displayName>
        <spirit:description>addr width </spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C7_RLDIII_ADDR_WIDTH" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="32" spirit:rangeType="long">29</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="long">
        <spirit:name>C7_RLDIII_nCK_PER_CLK</spirit:name>
        <spirit:displayName>nCk per clock</spirit:displayName>
        <spirit:description>nCk per clock</spirit:description>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C7_RLDIII_nCK_PER_CLK" spirit:configGroups="default" spirit:minimum="1" spirit:maximum="4" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="string">
        <spirit:name>C7_POLARITY</spirit:name>
        <spirit:displayName>Polarity of the value</spirit:displayName>
        <spirit:description>Polarity of the value</spirit:description>
        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C7_POLARITY" spirit:choiceRef="choice_list_6eff49bd" spirit:configGroups="default">ACTIVE_LOW</spirit:value>
      </spirit:modelParameter>
    </spirit:modelParameters>
  </spirit:model>
  <spirit:choices>
    <spirit:choice>
      <spirit:name>choice_list_1570a756</spirit:name>
      <spirit:enumeration>DIFF</spirit:enumeration>
      <spirit:enumeration>SINGLE</spirit:enumeration>
      <spirit:enumeration>NOBUF</spirit:enumeration>
    </spirit:choice>
    <spirit:choice>
      <spirit:name>choice_list_350ebf94</spirit:name>
      <spirit:enumeration>DIFF</spirit:enumeration>
      <spirit:enumeration>SINGLE</spirit:enumeration>
      <spirit:enumeration>NOBUF</spirit:enumeration>
      <spirit:enumeration>NONE</spirit:enumeration>
    </spirit:choice>
    <spirit:choice>
      <spirit:name>choice_list_40181835</spirit:name>
      <spirit:enumeration>32</spirit:enumeration>
      <spirit:enumeration>64</spirit:enumeration>
      <spirit:enumeration>128</spirit:enumeration>
      <spirit:enumeration>256</spirit:enumeration>
      <spirit:enumeration>512</spirit:enumeration>
      <spirit:enumeration>1024</spirit:enumeration>
    </spirit:choice>
    <spirit:choice>
      <spirit:name>choice_list_6eff49bd</spirit:name>
      <spirit:enumeration>ACTIVE_LOW</spirit:enumeration>
      <spirit:enumeration>ACTIVE_HIGH</spirit:enumeration>
    </spirit:choice>
    <spirit:choice>
      <spirit:name>choice_list_b54243b1</spirit:name>
      <spirit:enumeration>DDR3</spirit:enumeration>
      <spirit:enumeration>DDR2</spirit:enumeration>
      <spirit:enumeration>LPDDR2</spirit:enumeration>
      <spirit:enumeration>QDRIIP</spirit:enumeration>
      <spirit:enumeration>RLDII</spirit:enumeration>
      <spirit:enumeration>RLDIII</spirit:enumeration>
    </spirit:choice>
    <spirit:choice>
      <spirit:name>choice_list_bdb560e1</spirit:name>
      <spirit:enumeration>8</spirit:enumeration>
      <spirit:enumeration>16</spirit:enumeration>
      <spirit:enumeration>24</spirit:enumeration>
      <spirit:enumeration>32</spirit:enumeration>
      <spirit:enumeration>40</spirit:enumeration>
      <spirit:enumeration>48</spirit:enumeration>
      <spirit:enumeration>56</spirit:enumeration>
      <spirit:enumeration>64</spirit:enumeration>
      <spirit:enumeration>72</spirit:enumeration>
    </spirit:choice>
    <spirit:choice>
      <spirit:name>choice_list_c7c132f6</spirit:name>
      <spirit:enumeration>0.000</spirit:enumeration>
      <spirit:enumeration>337.500</spirit:enumeration>
      <spirit:enumeration>315.000</spirit:enumeration>
    </spirit:choice>
    <spirit:choice>
      <spirit:name>choice_list_cf6acb30</spirit:name>
      <spirit:enumeration>18</spirit:enumeration>
      <spirit:enumeration>36</spirit:enumeration>
      <spirit:enumeration>72</spirit:enumeration>
    </spirit:choice>
    <spirit:choice>
      <spirit:name>choice_list_d10f4555</spirit:name>
      <spirit:enumeration>FALSE</spirit:enumeration>
      <spirit:enumeration>TRUE</spirit:enumeration>
    </spirit:choice>
    <spirit:choice>
      <spirit:name>choice_list_dc86ec6e</spirit:name>
      <spirit:enumeration>OFF</spirit:enumeration>
      <spirit:enumeration>ON</spirit:enumeration>
    </spirit:choice>
    <spirit:choice>
      <spirit:name>choice_list_dd2843c6</spirit:name>
      <spirit:enumeration>1</spirit:enumeration>
      <spirit:enumeration>2</spirit:enumeration>
      <spirit:enumeration>4</spirit:enumeration>
      <spirit:enumeration>8</spirit:enumeration>
    </spirit:choice>
    <spirit:choice>
      <spirit:name>choice_list_e5b95726</spirit:name>
      <spirit:enumeration>INTERNAL</spirit:enumeration>
      <spirit:enumeration>EXTERNAL</spirit:enumeration>
    </spirit:choice>
    <spirit:choice>
      <spirit:name>choice_list_e7c484ae</spirit:name>
      <spirit:enumeration>TRUE</spirit:enumeration>
      <spirit:enumeration>FALSE</spirit:enumeration>
    </spirit:choice>
    <spirit:choice>
      <spirit:name>choice_pairs_a3ccaa0c</spirit:name>
      <spirit:enumeration spirit:text="Custom">Custom</spirit:enumeration>
      <spirit:enumeration spirit:text="phy reset out">phy_reset_out</spirit:enumeration>
      <spirit:enumeration spirit:text="reset">reset</spirit:enumeration>
    </spirit:choice>
    <spirit:choice>
      <spirit:name>choice_pairs_e3557075</spirit:name>
      <spirit:enumeration spirit:text="Custom">Custom</spirit:enumeration>
      <spirit:enumeration spirit:text="DDR3 SDRAM">DDR3_SDRAM</spirit:enumeration>
    </spirit:choice>
  </spirit:choices>
  <spirit:fileSets>
    <spirit:fileSet>
      <spirit:name>xilinx_verilogbehavioralsimulation_view_fileset</spirit:name>
      <spirit:file>
        <spirit:name>mig/user_design/rtl/clocking/mig_7series_v4_2_clk_ibuf.v</spirit:name>
        <spirit:fileType>verilogSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>mig/user_design/rtl/clocking/mig_7series_v4_2_infrastructure.v</spirit:name>
        <spirit:fileType>verilogSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>mig/user_design/rtl/clocking/mig_7series_v4_2_iodelay_ctrl.v</spirit:name>
        <spirit:fileType>verilogSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>mig/user_design/rtl/clocking/mig_7series_v4_2_tempmon.v</spirit:name>
        <spirit:fileType>verilogSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>mig/user_design/rtl/controller/mig_7series_v4_2_arb_mux.v</spirit:name>
        <spirit:fileType>verilogSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>mig/user_design/rtl/controller/mig_7series_v4_2_arb_row_col.v</spirit:name>
        <spirit:fileType>verilogSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>mig/user_design/rtl/controller/mig_7series_v4_2_arb_select.v</spirit:name>
        <spirit:fileType>verilogSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>mig/user_design/rtl/controller/mig_7series_v4_2_bank_cntrl.v</spirit:name>
        <spirit:fileType>verilogSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>mig/user_design/rtl/controller/mig_7series_v4_2_bank_common.v</spirit:name>
        <spirit:fileType>verilogSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>mig/user_design/rtl/controller/mig_7series_v4_2_bank_compare.v</spirit:name>
        <spirit:fileType>verilogSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>mig/user_design/rtl/controller/mig_7series_v4_2_bank_mach.v</spirit:name>
        <spirit:fileType>verilogSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>mig/user_design/rtl/controller/mig_7series_v4_2_bank_queue.v</spirit:name>
        <spirit:fileType>verilogSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>mig/user_design/rtl/controller/mig_7series_v4_2_bank_state.v</spirit:name>
        <spirit:fileType>verilogSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>mig/user_design/rtl/controller/mig_7series_v4_2_col_mach.v</spirit:name>
        <spirit:fileType>verilogSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>mig/user_design/rtl/controller/mig_7series_v4_2_mc.v</spirit:name>
        <spirit:fileType>verilogSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>mig/user_design/rtl/controller/mig_7series_v4_2_rank_cntrl.v</spirit:name>
        <spirit:fileType>verilogSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>mig/user_design/rtl/controller/mig_7series_v4_2_rank_common.v</spirit:name>
        <spirit:fileType>verilogSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>mig/user_design/rtl/controller/mig_7series_v4_2_rank_mach.v</spirit:name>
        <spirit:fileType>verilogSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>mig/user_design/rtl/controller/mig_7series_v4_2_round_robin_arb.v</spirit:name>
        <spirit:fileType>verilogSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>mig/user_design/rtl/ecc/mig_7series_v4_2_ecc_buf.v</spirit:name>
        <spirit:fileType>verilogSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>mig/user_design/rtl/ecc/mig_7series_v4_2_ecc_dec_fix.v</spirit:name>
        <spirit:fileType>verilogSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>mig/user_design/rtl/ecc/mig_7series_v4_2_ecc_gen.v</spirit:name>
        <spirit:fileType>verilogSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>mig/user_design/rtl/ecc/mig_7series_v4_2_ecc_merge_enc.v</spirit:name>
        <spirit:fileType>verilogSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>mig/user_design/rtl/ecc/mig_7series_v4_2_fi_xor.v</spirit:name>
        <spirit:fileType>verilogSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>mig/user_design/rtl/ip_top/mig_7series_v4_2_memc_ui_top_std.v</spirit:name>
        <spirit:fileType>verilogSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>mig/user_design/rtl/ip_top/mig_7series_v4_2_mem_intfc.v</spirit:name>
        <spirit:fileType>verilogSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>mig/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_group_io.v</spirit:name>
        <spirit:fileType>verilogSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>mig/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v</spirit:name>
        <spirit:fileType>verilogSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>mig/user_design/rtl/phy/mig_7series_v4_2_ddr_calib_top.v</spirit:name>
        <spirit:fileType>verilogSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>mig/user_design/rtl/phy/mig_7series_v4_2_ddr_if_post_fifo.v</spirit:name>
        <spirit:fileType>verilogSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>mig/user_design/rtl/phy/mig_7series_v4_2_ddr_mc_phy.v</spirit:name>
        <spirit:fileType>verilogSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>mig/user_design/rtl/phy/mig_7series_v4_2_ddr_mc_phy_wrapper.v</spirit:name>
        <spirit:fileType>verilogSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>mig/user_design/rtl/phy/mig_7series_v4_2_ddr_of_pre_fifo.v</spirit:name>
        <spirit:fileType>verilogSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>mig/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_4lanes.v</spirit:name>
        <spirit:fileType>verilogSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>mig/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_ck_addr_cmd_delay.v</spirit:name>
        <spirit:fileType>verilogSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>mig/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_dqs_found_cal.v</spirit:name>
        <spirit:fileType>verilogSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>mig/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_dqs_found_cal_hr.v</spirit:name>
        <spirit:fileType>verilogSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>mig/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_init.v</spirit:name>
        <spirit:fileType>verilogSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>mig/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_ocd_cntlr.v</spirit:name>
        <spirit:fileType>verilogSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>mig/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_ocd_data.v</spirit:name>
        <spirit:fileType>verilogSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>mig/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_ocd_edge.v</spirit:name>
        <spirit:fileType>verilogSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>mig/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_ocd_lim.v</spirit:name>
        <spirit:fileType>verilogSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>mig/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_ocd_mux.v</spirit:name>
        <spirit:fileType>verilogSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>mig/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_ocd_po_cntlr.v</spirit:name>
        <spirit:fileType>verilogSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>mig/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_ocd_samp.v</spirit:name>
        <spirit:fileType>verilogSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>mig/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_oclkdelay_cal.v</spirit:name>
        <spirit:fileType>verilogSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>mig/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_prbs_rdlvl.v</spirit:name>
        <spirit:fileType>verilogSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>mig/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_rdlvl.v</spirit:name>
        <spirit:fileType>verilogSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>mig/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_tempmon.v</spirit:name>
        <spirit:fileType>verilogSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>mig/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_wrcal.v</spirit:name>
        <spirit:fileType>verilogSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>mig/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_wrlvl.v</spirit:name>
        <spirit:fileType>verilogSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>mig/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_wrlvl_off_delay.v</spirit:name>
        <spirit:fileType>verilogSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>mig/user_design/rtl/phy/mig_7series_v4_2_ddr_prbs_gen.v</spirit:name>
        <spirit:fileType>verilogSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>mig/user_design/rtl/phy/mig_7series_v4_2_ddr_skip_calib_tap.v</spirit:name>
        <spirit:fileType>verilogSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>mig/user_design/rtl/phy/mig_7series_v4_2_poc_cc.v</spirit:name>
        <spirit:fileType>verilogSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>mig/user_design/rtl/phy/mig_7series_v4_2_poc_edge_store.v</spirit:name>
        <spirit:fileType>verilogSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>mig/user_design/rtl/phy/mig_7series_v4_2_poc_meta.v</spirit:name>
        <spirit:fileType>verilogSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>mig/user_design/rtl/phy/mig_7series_v4_2_poc_pd.v</spirit:name>
        <spirit:fileType>verilogSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>mig/user_design/rtl/phy/mig_7series_v4_2_poc_tap_base.v</spirit:name>
        <spirit:fileType>verilogSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>mig/user_design/rtl/phy/mig_7series_v4_2_poc_top.v</spirit:name>
        <spirit:fileType>verilogSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>mig/user_design/rtl/ui/mig_7series_v4_2_ui_cmd.v</spirit:name>
        <spirit:fileType>verilogSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>mig/user_design/rtl/ui/mig_7series_v4_2_ui_rd_data.v</spirit:name>
        <spirit:fileType>verilogSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>mig/user_design/rtl/ui/mig_7series_v4_2_ui_top.v</spirit:name>
        <spirit:fileType>verilogSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>mig/user_design/rtl/ui/mig_7series_v4_2_ui_wr_data.v</spirit:name>
        <spirit:fileType>verilogSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>mig/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_top.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
    </spirit:fileSet>
    <spirit:fileSet>
      <spirit:name>xilinx_vhdlsimulationwrapper_view_fileset</spirit:name>
      <spirit:file>
        <spirit:name>mig/user_design/rtl/mig_mig_sim.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>mig/user_design/rtl/mig.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
    </spirit:fileSet>
    <spirit:fileSet>
      <spirit:name>xilinx_anylanguagesynthesis_view_fileset</spirit:name>
      <spirit:file>
        <spirit:name>mig/user_design/rtl/clocking/mig_7series_v4_2_clk_ibuf.v</spirit:name>
        <spirit:fileType>verilogSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>mig/user_design/rtl/clocking/mig_7series_v4_2_infrastructure.v</spirit:name>
        <spirit:fileType>verilogSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>mig/user_design/rtl/clocking/mig_7series_v4_2_iodelay_ctrl.v</spirit:name>
        <spirit:fileType>verilogSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>mig/user_design/rtl/clocking/mig_7series_v4_2_tempmon.v</spirit:name>
        <spirit:fileType>verilogSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>mig/user_design/rtl/controller/mig_7series_v4_2_arb_mux.v</spirit:name>
        <spirit:fileType>verilogSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>mig/user_design/rtl/controller/mig_7series_v4_2_arb_row_col.v</spirit:name>
        <spirit:fileType>verilogSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>mig/user_design/rtl/controller/mig_7series_v4_2_arb_select.v</spirit:name>
        <spirit:fileType>verilogSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>mig/user_design/rtl/controller/mig_7series_v4_2_bank_cntrl.v</spirit:name>
        <spirit:fileType>verilogSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>mig/user_design/rtl/controller/mig_7series_v4_2_bank_common.v</spirit:name>
        <spirit:fileType>verilogSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>mig/user_design/rtl/controller/mig_7series_v4_2_bank_compare.v</spirit:name>
        <spirit:fileType>verilogSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>mig/user_design/rtl/controller/mig_7series_v4_2_bank_mach.v</spirit:name>
        <spirit:fileType>verilogSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>mig/user_design/rtl/controller/mig_7series_v4_2_bank_queue.v</spirit:name>
        <spirit:fileType>verilogSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>mig/user_design/rtl/controller/mig_7series_v4_2_bank_state.v</spirit:name>
        <spirit:fileType>verilogSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>mig/user_design/rtl/controller/mig_7series_v4_2_col_mach.v</spirit:name>
        <spirit:fileType>verilogSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>mig/user_design/rtl/controller/mig_7series_v4_2_mc.v</spirit:name>
        <spirit:fileType>verilogSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>mig/user_design/rtl/controller/mig_7series_v4_2_rank_cntrl.v</spirit:name>
        <spirit:fileType>verilogSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>mig/user_design/rtl/controller/mig_7series_v4_2_rank_common.v</spirit:name>
        <spirit:fileType>verilogSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>mig/user_design/rtl/controller/mig_7series_v4_2_rank_mach.v</spirit:name>
        <spirit:fileType>verilogSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>mig/user_design/rtl/controller/mig_7series_v4_2_round_robin_arb.v</spirit:name>
        <spirit:fileType>verilogSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>mig/user_design/rtl/ecc/mig_7series_v4_2_ecc_buf.v</spirit:name>
        <spirit:fileType>verilogSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>mig/user_design/rtl/ecc/mig_7series_v4_2_ecc_dec_fix.v</spirit:name>
        <spirit:fileType>verilogSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>mig/user_design/rtl/ecc/mig_7series_v4_2_ecc_gen.v</spirit:name>
        <spirit:fileType>verilogSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>mig/user_design/rtl/ecc/mig_7series_v4_2_ecc_merge_enc.v</spirit:name>
        <spirit:fileType>verilogSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>mig/user_design/rtl/ecc/mig_7series_v4_2_fi_xor.v</spirit:name>
        <spirit:fileType>verilogSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>mig/user_design/rtl/ip_top/mig_7series_v4_2_memc_ui_top_std.v</spirit:name>
        <spirit:fileType>verilogSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>mig/user_design/rtl/ip_top/mig_7series_v4_2_mem_intfc.v</spirit:name>
        <spirit:fileType>verilogSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>mig/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_group_io.v</spirit:name>
        <spirit:fileType>verilogSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>mig/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v</spirit:name>
        <spirit:fileType>verilogSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>mig/user_design/rtl/phy/mig_7series_v4_2_ddr_calib_top.v</spirit:name>
        <spirit:fileType>verilogSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>mig/user_design/rtl/phy/mig_7series_v4_2_ddr_if_post_fifo.v</spirit:name>
        <spirit:fileType>verilogSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>mig/user_design/rtl/phy/mig_7series_v4_2_ddr_mc_phy.v</spirit:name>
        <spirit:fileType>verilogSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>mig/user_design/rtl/phy/mig_7series_v4_2_ddr_mc_phy_wrapper.v</spirit:name>
        <spirit:fileType>verilogSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>mig/user_design/rtl/phy/mig_7series_v4_2_ddr_of_pre_fifo.v</spirit:name>
        <spirit:fileType>verilogSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>mig/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_4lanes.v</spirit:name>
        <spirit:fileType>verilogSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>mig/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_ck_addr_cmd_delay.v</spirit:name>
        <spirit:fileType>verilogSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>mig/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_dqs_found_cal.v</spirit:name>
        <spirit:fileType>verilogSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>mig/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_dqs_found_cal_hr.v</spirit:name>
        <spirit:fileType>verilogSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>mig/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_init.v</spirit:name>
        <spirit:fileType>verilogSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>mig/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_ocd_cntlr.v</spirit:name>
        <spirit:fileType>verilogSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>mig/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_ocd_data.v</spirit:name>
        <spirit:fileType>verilogSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>mig/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_ocd_edge.v</spirit:name>
        <spirit:fileType>verilogSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>mig/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_ocd_lim.v</spirit:name>
        <spirit:fileType>verilogSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>mig/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_ocd_mux.v</spirit:name>
        <spirit:fileType>verilogSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>mig/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_ocd_po_cntlr.v</spirit:name>
        <spirit:fileType>verilogSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>mig/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_ocd_samp.v</spirit:name>
        <spirit:fileType>verilogSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>mig/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_oclkdelay_cal.v</spirit:name>
        <spirit:fileType>verilogSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>mig/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_prbs_rdlvl.v</spirit:name>
        <spirit:fileType>verilogSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>mig/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_rdlvl.v</spirit:name>
        <spirit:fileType>verilogSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>mig/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_tempmon.v</spirit:name>
        <spirit:fileType>verilogSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>mig/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_wrcal.v</spirit:name>
        <spirit:fileType>verilogSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>mig/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_wrlvl.v</spirit:name>
        <spirit:fileType>verilogSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>mig/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_wrlvl_off_delay.v</spirit:name>
        <spirit:fileType>verilogSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>mig/user_design/rtl/phy/mig_7series_v4_2_ddr_prbs_gen.v</spirit:name>
        <spirit:fileType>verilogSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>mig/user_design/rtl/phy/mig_7series_v4_2_ddr_skip_calib_tap.v</spirit:name>
        <spirit:fileType>verilogSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>mig/user_design/rtl/phy/mig_7series_v4_2_poc_cc.v</spirit:name>
        <spirit:fileType>verilogSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>mig/user_design/rtl/phy/mig_7series_v4_2_poc_edge_store.v</spirit:name>
        <spirit:fileType>verilogSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>mig/user_design/rtl/phy/mig_7series_v4_2_poc_meta.v</spirit:name>
        <spirit:fileType>verilogSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>mig/user_design/rtl/phy/mig_7series_v4_2_poc_pd.v</spirit:name>
        <spirit:fileType>verilogSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>mig/user_design/rtl/phy/mig_7series_v4_2_poc_tap_base.v</spirit:name>
        <spirit:fileType>verilogSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>mig/user_design/rtl/phy/mig_7series_v4_2_poc_top.v</spirit:name>
        <spirit:fileType>verilogSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>mig/user_design/rtl/ui/mig_7series_v4_2_ui_cmd.v</spirit:name>
        <spirit:fileType>verilogSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>mig/user_design/rtl/ui/mig_7series_v4_2_ui_rd_data.v</spirit:name>
        <spirit:fileType>verilogSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>mig/user_design/rtl/ui/mig_7series_v4_2_ui_top.v</spirit:name>
        <spirit:fileType>verilogSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>mig/user_design/rtl/ui/mig_7series_v4_2_ui_wr_data.v</spirit:name>
        <spirit:fileType>verilogSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>mig/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_top.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>mig/user_design/constraints/mig.xdc</spirit:name>
        <spirit:userFileType>xdc</spirit:userFileType>
        <spirit:userFileType>USED_IN_implementation</spirit:userFileType>
        <spirit:userFileType>USED_IN_simulation</spirit:userFileType>
        <spirit:userFileType>USED_IN_synthesis</spirit:userFileType>
        <spirit:define>
          <spirit:name>processing_order</spirit:name>
          <spirit:value>early</spirit:value>
        </spirit:define>
      </spirit:file>
      <spirit:file>
        <spirit:name>mig/user_design/constraints/mig_ooc.xdc</spirit:name>
        <spirit:userFileType>xdc</spirit:userFileType>
        <spirit:userFileType>USED_IN_implementation</spirit:userFileType>
        <spirit:userFileType>USED_IN_out_of_context</spirit:userFileType>
        <spirit:userFileType>USED_IN_synthesis</spirit:userFileType>
        <spirit:define>
          <spirit:name>processing_order</spirit:name>
          <spirit:value>early</spirit:value>
        </spirit:define>
      </spirit:file>
    </spirit:fileSet>
    <spirit:fileSet>
      <spirit:name>xilinx_vhdlsynthesiswrapper_view_fileset</spirit:name>
      <spirit:file>
        <spirit:name>mig/user_design/rtl/mig.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>mig/user_design/rtl/mig_mig.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
    </spirit:fileSet>
    <spirit:fileSet>
      <spirit:name>xilinx_implementation_view_fileset</spirit:name>
      <spirit:file>
        <spirit:name>mig/user_design/constraints/mig.xdc</spirit:name>
        <spirit:userFileType>xdc</spirit:userFileType>
        <spirit:userFileType>USED_IN_implementation</spirit:userFileType>
        <spirit:userFileType>USED_IN_simulation</spirit:userFileType>
        <spirit:userFileType>USED_IN_synthesis</spirit:userFileType>
        <spirit:define>
          <spirit:name>processing_order</spirit:name>
          <spirit:value>early</spirit:value>
        </spirit:define>
      </spirit:file>
      <spirit:file>
        <spirit:name>mig/user_design/constraints/mig_ooc.xdc</spirit:name>
        <spirit:userFileType>xdc</spirit:userFileType>
        <spirit:userFileType>USED_IN_implementation</spirit:userFileType>
        <spirit:userFileType>USED_IN_out_of_context</spirit:userFileType>
        <spirit:userFileType>USED_IN_synthesis</spirit:userFileType>
        <spirit:define>
          <spirit:name>processing_order</spirit:name>
          <spirit:value>early</spirit:value>
        </spirit:define>
      </spirit:file>
    </spirit:fileSet>
    <spirit:fileSet>
      <spirit:name>xilinx_externalfiles_view_fileset</spirit:name>
      <spirit:file>
        <spirit:name>mig.dcp</spirit:name>
        <spirit:userFileType>dcp</spirit:userFileType>
        <spirit:userFileType>USED_IN_implementation</spirit:userFileType>
        <spirit:userFileType>USED_IN_synthesis</spirit:userFileType>
        <spirit:logicalName>xil_defaultlib</spirit:logicalName>
      </spirit:file>
      <spirit:file>
        <spirit:name>mig_stub.v</spirit:name>
        <spirit:fileType>verilogSource</spirit:fileType>
        <spirit:userFileType>USED_IN_synth_blackbox_stub</spirit:userFileType>
        <spirit:logicalName>xil_defaultlib</spirit:logicalName>
      </spirit:file>
      <spirit:file>
        <spirit:name>mig_stub.vhdl</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
        <spirit:userFileType>USED_IN_synth_blackbox_stub</spirit:userFileType>
        <spirit:logicalName>xil_defaultlib</spirit:logicalName>
      </spirit:file>
      <spirit:file>
        <spirit:name>mig_sim_netlist.v</spirit:name>
        <spirit:fileType>verilogSource</spirit:fileType>
        <spirit:userFileType>USED_IN_simulation</spirit:userFileType>
        <spirit:userFileType>USED_IN_single_language</spirit:userFileType>
        <spirit:logicalName>xil_defaultlib</spirit:logicalName>
      </spirit:file>
      <spirit:file>
        <spirit:name>mig_sim_netlist.vhdl</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
        <spirit:userFileType>USED_IN_simulation</spirit:userFileType>
        <spirit:userFileType>USED_IN_single_language</spirit:userFileType>
        <spirit:logicalName>xil_defaultlib</spirit:logicalName>
      </spirit:file>
    </spirit:fileSet>
  </spirit:fileSets>
  <spirit:description> This Memory Interface Generator is a simple menu driven tool to generate advanced memory interfaces.  This tool generates HDL and pin placement constraints that will help you design your application. Kintex-7 supports DDR3 SDRAM, DDR2 SDRAM, LPDDR2 SDRAM, QDR II+ SRAM, RLDRAMII and RLDRAMIII. Virtex-7 supports DDR3 SDRAM, DDR2 SDRAM, LPDDR2 SDRAM, QDR II+ SRAM, RLDRAMII and RLDRAMIII. Artix-7 supports DDR3 SDRAM, DDR2 SDRAM and LPDDR2 SDRAM. Zynq supports DDR3 SDRAM, DDR2 SDRAM and LPDDR2 SDRAM </spirit:description>
  <spirit:parameters>
    <spirit:parameter>
      <spirit:name>XML_INPUT_FILE</spirit:name>
      <spirit:displayName>XML_INPUT_FILE</spirit:displayName>
      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.XML_INPUT_FILE" spirit:order="2">mig.prj</spirit:value>
    </spirit:parameter>
    <spirit:parameter>
      <spirit:name>RESET_BOARD_INTERFACE</spirit:name>
      <spirit:displayName>RESET_BOARD_INTERFACE</spirit:displayName>
      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.RESET_BOARD_INTERFACE" spirit:choiceRef="choice_pairs_a3ccaa0c" spirit:order="4">Custom</spirit:value>
    </spirit:parameter>
    <spirit:parameter>
      <spirit:name>MIG_DONT_TOUCH_PARAM</spirit:name>
      <spirit:displayName>MIG_DONT_TOUCH_PARAM</spirit:displayName>
      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.MIG_DONT_TOUCH_PARAM" spirit:order="6">Custom</spirit:value>
    </spirit:parameter>
    <spirit:parameter>
      <spirit:name>BOARD_MIG_PARAM</spirit:name>
      <spirit:displayName>BOARD_MIG_PARAM</spirit:displayName>
      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.BOARD_MIG_PARAM" spirit:choiceRef="choice_pairs_e3557075" spirit:order="1">Custom</spirit:value>
    </spirit:parameter>
    <spirit:parameter>
      <spirit:name>Component_Name</spirit:name>
      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Component_Name" spirit:order="1">mig</spirit:value>
    </spirit:parameter>
  </spirit:parameters>
  <spirit:vendorExtensions>
    <xilinx:coreExtensions>
      <xilinx:displayName>Memory Interface Generator (MIG 7 Series)</xilinx:displayName>
      <xilinx:coreRevision>1</xilinx:coreRevision>
      <xilinx:configElementInfos>
        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S0_AXI.ADDR_WIDTH" xilinx:valueSource="auto"/>
        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S0_AXI.ARUSER_WIDTH" xilinx:valueSource="constant"/>
        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S0_AXI.AWUSER_WIDTH" xilinx:valueSource="constant"/>
        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S0_AXI.BUSER_WIDTH" xilinx:valueSource="constant"/>
        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S0_AXI.DATA_WIDTH" xilinx:valueSource="auto"/>
        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S0_AXI.HAS_BRESP" xilinx:valueSource="auto"/>
        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S0_AXI.HAS_BURST" xilinx:valueSource="auto"/>
        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S0_AXI.HAS_CACHE" xilinx:valueSource="auto"/>
        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S0_AXI.HAS_LOCK" xilinx:valueSource="auto"/>
        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S0_AXI.HAS_PROT" xilinx:valueSource="auto"/>
        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S0_AXI.HAS_QOS" xilinx:valueSource="auto"/>
        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S0_AXI.HAS_REGION" xilinx:valueSource="constant"/>
        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S0_AXI.HAS_RRESP" xilinx:valueSource="auto"/>
        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S0_AXI.HAS_WSTRB" xilinx:valueSource="auto"/>
        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S0_AXI.PROTOCOL" xilinx:valueSource="auto"/>
        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S0_AXI.RUSER_WIDTH" xilinx:valueSource="constant"/>
        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S0_AXI.WUSER_WIDTH" xilinx:valueSource="constant"/>
        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S0_AXI_CTRL.ADDR_WIDTH" xilinx:valueSource="auto"/>
        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S0_AXI_CTRL.ARUSER_WIDTH" xilinx:valueSource="constant"/>
        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S0_AXI_CTRL.AWUSER_WIDTH" xilinx:valueSource="constant"/>
        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S0_AXI_CTRL.BUSER_WIDTH" xilinx:valueSource="constant"/>
        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S0_AXI_CTRL.DATA_WIDTH" xilinx:valueSource="auto"/>
        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S0_AXI_CTRL.HAS_BRESP" xilinx:valueSource="auto"/>
        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S0_AXI_CTRL.HAS_BURST" xilinx:valueSource="constant"/>
        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S0_AXI_CTRL.HAS_CACHE" xilinx:valueSource="constant"/>
        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S0_AXI_CTRL.HAS_LOCK" xilinx:valueSource="constant"/>
        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S0_AXI_CTRL.HAS_PROT" xilinx:valueSource="constant"/>
        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S0_AXI_CTRL.HAS_QOS" xilinx:valueSource="constant"/>
        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S0_AXI_CTRL.HAS_REGION" xilinx:valueSource="constant"/>
        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S0_AXI_CTRL.HAS_RRESP" xilinx:valueSource="auto"/>
        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S0_AXI_CTRL.HAS_WSTRB" xilinx:valueSource="constant"/>
        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S0_AXI_CTRL.ID_WIDTH" xilinx:valueSource="constant"/>
        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S0_AXI_CTRL.PROTOCOL" xilinx:valueSource="constant"/>
        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S0_AXI_CTRL.RUSER_WIDTH" xilinx:valueSource="constant"/>
        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S0_AXI_CTRL.WUSER_WIDTH" xilinx:valueSource="constant"/>
        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S1_AXI.ADDR_WIDTH" xilinx:valueSource="auto"/>
        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S1_AXI.ARUSER_WIDTH" xilinx:valueSource="constant"/>
        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S1_AXI.AWUSER_WIDTH" xilinx:valueSource="constant"/>
        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S1_AXI.BUSER_WIDTH" xilinx:valueSource="constant"/>
        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S1_AXI.DATA_WIDTH" xilinx:valueSource="auto"/>
        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S1_AXI.HAS_BRESP" xilinx:valueSource="auto"/>
        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S1_AXI.HAS_BURST" xilinx:valueSource="auto"/>
        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S1_AXI.HAS_CACHE" xilinx:valueSource="auto"/>
        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S1_AXI.HAS_LOCK" xilinx:valueSource="auto"/>
        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S1_AXI.HAS_PROT" xilinx:valueSource="auto"/>
        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S1_AXI.HAS_QOS" xilinx:valueSource="auto"/>
        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S1_AXI.HAS_REGION" xilinx:valueSource="constant"/>
        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S1_AXI.HAS_RRESP" xilinx:valueSource="auto"/>
        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S1_AXI.HAS_WSTRB" xilinx:valueSource="auto"/>
        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S1_AXI.PROTOCOL" xilinx:valueSource="auto"/>
        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S1_AXI.RUSER_WIDTH" xilinx:valueSource="constant"/>
        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S1_AXI.WUSER_WIDTH" xilinx:valueSource="constant"/>
        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S1_AXI_CTRL.ADDR_WIDTH" xilinx:valueSource="auto"/>
        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S1_AXI_CTRL.ARUSER_WIDTH" xilinx:valueSource="constant"/>
        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S1_AXI_CTRL.AWUSER_WIDTH" xilinx:valueSource="constant"/>
        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S1_AXI_CTRL.BUSER_WIDTH" xilinx:valueSource="constant"/>
        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S1_AXI_CTRL.DATA_WIDTH" xilinx:valueSource="auto"/>
        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S1_AXI_CTRL.HAS_BRESP" xilinx:valueSource="auto"/>
        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S1_AXI_CTRL.HAS_BURST" xilinx:valueSource="constant"/>
        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S1_AXI_CTRL.HAS_CACHE" xilinx:valueSource="constant"/>
        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S1_AXI_CTRL.HAS_LOCK" xilinx:valueSource="constant"/>
        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S1_AXI_CTRL.HAS_PROT" xilinx:valueSource="constant"/>
        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S1_AXI_CTRL.HAS_QOS" xilinx:valueSource="constant"/>
        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S1_AXI_CTRL.HAS_REGION" xilinx:valueSource="constant"/>
        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S1_AXI_CTRL.HAS_RRESP" xilinx:valueSource="auto"/>
        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S1_AXI_CTRL.HAS_WSTRB" xilinx:valueSource="constant"/>
        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S1_AXI_CTRL.ID_WIDTH" xilinx:valueSource="constant"/>
        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S1_AXI_CTRL.PROTOCOL" xilinx:valueSource="constant"/>
        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S1_AXI_CTRL.RUSER_WIDTH" xilinx:valueSource="constant"/>
        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S1_AXI_CTRL.WUSER_WIDTH" xilinx:valueSource="constant"/>
        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S2_AXI.ADDR_WIDTH" xilinx:valueSource="auto"/>
        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S2_AXI.ARUSER_WIDTH" xilinx:valueSource="constant"/>
        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S2_AXI.AWUSER_WIDTH" xilinx:valueSource="constant"/>
        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S2_AXI.BUSER_WIDTH" xilinx:valueSource="constant"/>
        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S2_AXI.DATA_WIDTH" xilinx:valueSource="auto"/>
        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S2_AXI.HAS_BRESP" xilinx:valueSource="auto"/>
        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S2_AXI.HAS_BURST" xilinx:valueSource="auto"/>
        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S2_AXI.HAS_CACHE" xilinx:valueSource="auto"/>
        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S2_AXI.HAS_LOCK" xilinx:valueSource="auto"/>
        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S2_AXI.HAS_PROT" xilinx:valueSource="auto"/>
        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S2_AXI.HAS_QOS" xilinx:valueSource="auto"/>
        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S2_AXI.HAS_REGION" xilinx:valueSource="constant"/>
        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S2_AXI.HAS_RRESP" xilinx:valueSource="auto"/>
        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S2_AXI.HAS_WSTRB" xilinx:valueSource="auto"/>
        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S2_AXI.PROTOCOL" xilinx:valueSource="auto"/>
        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S2_AXI.RUSER_WIDTH" xilinx:valueSource="constant"/>
        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S2_AXI.WUSER_WIDTH" xilinx:valueSource="constant"/>
        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S2_AXI_CTRL.ADDR_WIDTH" xilinx:valueSource="auto"/>
        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S2_AXI_CTRL.ARUSER_WIDTH" xilinx:valueSource="constant"/>
        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S2_AXI_CTRL.AWUSER_WIDTH" xilinx:valueSource="constant"/>
        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S2_AXI_CTRL.BUSER_WIDTH" xilinx:valueSource="constant"/>
        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S2_AXI_CTRL.DATA_WIDTH" xilinx:valueSource="auto"/>
        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S2_AXI_CTRL.HAS_BRESP" xilinx:valueSource="auto"/>
        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S2_AXI_CTRL.HAS_BURST" xilinx:valueSource="constant"/>
        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S2_AXI_CTRL.HAS_CACHE" xilinx:valueSource="constant"/>
        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S2_AXI_CTRL.HAS_LOCK" xilinx:valueSource="constant"/>
        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S2_AXI_CTRL.HAS_PROT" xilinx:valueSource="constant"/>
        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S2_AXI_CTRL.HAS_QOS" xilinx:valueSource="constant"/>
        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S2_AXI_CTRL.HAS_REGION" xilinx:valueSource="constant"/>
        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S2_AXI_CTRL.HAS_RRESP" xilinx:valueSource="auto"/>
        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S2_AXI_CTRL.HAS_WSTRB" xilinx:valueSource="constant"/>
        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S2_AXI_CTRL.ID_WIDTH" xilinx:valueSource="constant"/>
        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S2_AXI_CTRL.PROTOCOL" xilinx:valueSource="constant"/>
        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S2_AXI_CTRL.RUSER_WIDTH" xilinx:valueSource="constant"/>
        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S2_AXI_CTRL.WUSER_WIDTH" xilinx:valueSource="constant"/>
        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S3_AXI.ADDR_WIDTH" xilinx:valueSource="auto"/>
        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S3_AXI.ARUSER_WIDTH" xilinx:valueSource="constant"/>
        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S3_AXI.AWUSER_WIDTH" xilinx:valueSource="constant"/>
        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S3_AXI.BUSER_WIDTH" xilinx:valueSource="constant"/>
        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S3_AXI.DATA_WIDTH" xilinx:valueSource="auto"/>
        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S3_AXI.HAS_BRESP" xilinx:valueSource="auto"/>
        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S3_AXI.HAS_BURST" xilinx:valueSource="auto"/>
        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S3_AXI.HAS_CACHE" xilinx:valueSource="auto"/>
        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S3_AXI.HAS_LOCK" xilinx:valueSource="auto"/>
        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S3_AXI.HAS_PROT" xilinx:valueSource="auto"/>
        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S3_AXI.HAS_QOS" xilinx:valueSource="auto"/>
        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S3_AXI.HAS_REGION" xilinx:valueSource="constant"/>
        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S3_AXI.HAS_RRESP" xilinx:valueSource="auto"/>
        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S3_AXI.HAS_WSTRB" xilinx:valueSource="auto"/>
        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S3_AXI.PROTOCOL" xilinx:valueSource="auto"/>
        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S3_AXI.RUSER_WIDTH" xilinx:valueSource="constant"/>
        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S3_AXI.WUSER_WIDTH" xilinx:valueSource="constant"/>
        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S3_AXI_CTRL.ADDR_WIDTH" xilinx:valueSource="auto"/>
        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S3_AXI_CTRL.ARUSER_WIDTH" xilinx:valueSource="constant"/>
        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S3_AXI_CTRL.AWUSER_WIDTH" xilinx:valueSource="constant"/>
        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S3_AXI_CTRL.BUSER_WIDTH" xilinx:valueSource="constant"/>
        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S3_AXI_CTRL.DATA_WIDTH" xilinx:valueSource="auto"/>
        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S3_AXI_CTRL.HAS_BRESP" xilinx:valueSource="auto"/>
        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S3_AXI_CTRL.HAS_BURST" xilinx:valueSource="constant"/>
        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S3_AXI_CTRL.HAS_CACHE" xilinx:valueSource="constant"/>
        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S3_AXI_CTRL.HAS_LOCK" xilinx:valueSource="constant"/>
        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S3_AXI_CTRL.HAS_PROT" xilinx:valueSource="constant"/>
        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S3_AXI_CTRL.HAS_QOS" xilinx:valueSource="constant"/>
        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S3_AXI_CTRL.HAS_REGION" xilinx:valueSource="constant"/>
        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S3_AXI_CTRL.HAS_RRESP" xilinx:valueSource="auto"/>
        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S3_AXI_CTRL.HAS_WSTRB" xilinx:valueSource="constant"/>
        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S3_AXI_CTRL.ID_WIDTH" xilinx:valueSource="constant"/>
        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S3_AXI_CTRL.PROTOCOL" xilinx:valueSource="constant"/>
        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S3_AXI_CTRL.RUSER_WIDTH" xilinx:valueSource="constant"/>
        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S3_AXI_CTRL.WUSER_WIDTH" xilinx:valueSource="constant"/>
        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S4_AXI.ADDR_WIDTH" xilinx:valueSource="auto"/>
        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S4_AXI.ARUSER_WIDTH" xilinx:valueSource="constant"/>
        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S4_AXI.AWUSER_WIDTH" xilinx:valueSource="constant"/>
        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S4_AXI.BUSER_WIDTH" xilinx:valueSource="constant"/>
        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S4_AXI.DATA_WIDTH" xilinx:valueSource="auto"/>
        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S4_AXI.HAS_BRESP" xilinx:valueSource="auto"/>
        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S4_AXI.HAS_BURST" xilinx:valueSource="auto"/>
        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S4_AXI.HAS_CACHE" xilinx:valueSource="auto"/>
        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S4_AXI.HAS_LOCK" xilinx:valueSource="auto"/>
        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S4_AXI.HAS_PROT" xilinx:valueSource="auto"/>
        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S4_AXI.HAS_QOS" xilinx:valueSource="auto"/>
        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S4_AXI.HAS_REGION" xilinx:valueSource="constant"/>
        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S4_AXI.HAS_RRESP" xilinx:valueSource="auto"/>
        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S4_AXI.HAS_WSTRB" xilinx:valueSource="auto"/>
        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S4_AXI.PROTOCOL" xilinx:valueSource="auto"/>
        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S4_AXI.RUSER_WIDTH" xilinx:valueSource="constant"/>
        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S4_AXI.WUSER_WIDTH" xilinx:valueSource="constant"/>
        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S4_AXI_CTRL.ADDR_WIDTH" xilinx:valueSource="auto"/>
        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S4_AXI_CTRL.ARUSER_WIDTH" xilinx:valueSource="constant"/>
        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S4_AXI_CTRL.AWUSER_WIDTH" xilinx:valueSource="constant"/>
        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S4_AXI_CTRL.BUSER_WIDTH" xilinx:valueSource="constant"/>
        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S4_AXI_CTRL.DATA_WIDTH" xilinx:valueSource="auto"/>
        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S4_AXI_CTRL.HAS_BRESP" xilinx:valueSource="auto"/>
        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S4_AXI_CTRL.HAS_BURST" xilinx:valueSource="constant"/>
        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S4_AXI_CTRL.HAS_CACHE" xilinx:valueSource="constant"/>
        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S4_AXI_CTRL.HAS_LOCK" xilinx:valueSource="constant"/>
        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S4_AXI_CTRL.HAS_PROT" xilinx:valueSource="constant"/>
        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S4_AXI_CTRL.HAS_QOS" xilinx:valueSource="constant"/>
        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S4_AXI_CTRL.HAS_REGION" xilinx:valueSource="constant"/>
        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S4_AXI_CTRL.HAS_RRESP" xilinx:valueSource="auto"/>
        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S4_AXI_CTRL.HAS_WSTRB" xilinx:valueSource="constant"/>
        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S4_AXI_CTRL.ID_WIDTH" xilinx:valueSource="constant"/>
        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S4_AXI_CTRL.PROTOCOL" xilinx:valueSource="constant"/>
        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S4_AXI_CTRL.RUSER_WIDTH" xilinx:valueSource="constant"/>
        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S4_AXI_CTRL.WUSER_WIDTH" xilinx:valueSource="constant"/>
        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S5_AXI.ADDR_WIDTH" xilinx:valueSource="auto"/>
        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S5_AXI.ARUSER_WIDTH" xilinx:valueSource="constant"/>
        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S5_AXI.AWUSER_WIDTH" xilinx:valueSource="constant"/>
        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S5_AXI.BUSER_WIDTH" xilinx:valueSource="constant"/>
        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S5_AXI.DATA_WIDTH" xilinx:valueSource="auto"/>
        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S5_AXI.HAS_BRESP" xilinx:valueSource="auto"/>
        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S5_AXI.HAS_BURST" xilinx:valueSource="auto"/>
        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S5_AXI.HAS_CACHE" xilinx:valueSource="auto"/>
        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S5_AXI.HAS_LOCK" xilinx:valueSource="auto"/>
        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S5_AXI.HAS_PROT" xilinx:valueSource="auto"/>
        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S5_AXI.HAS_QOS" xilinx:valueSource="auto"/>
        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S5_AXI.HAS_REGION" xilinx:valueSource="constant"/>
        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S5_AXI.HAS_RRESP" xilinx:valueSource="auto"/>
        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S5_AXI.HAS_WSTRB" xilinx:valueSource="auto"/>
        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S5_AXI.PROTOCOL" xilinx:valueSource="auto"/>
        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S5_AXI.RUSER_WIDTH" xilinx:valueSource="constant"/>
        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S5_AXI.WUSER_WIDTH" xilinx:valueSource="constant"/>
        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S5_AXI_CTRL.ADDR_WIDTH" xilinx:valueSource="auto"/>
        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S5_AXI_CTRL.ARUSER_WIDTH" xilinx:valueSource="constant"/>
        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S5_AXI_CTRL.AWUSER_WIDTH" xilinx:valueSource="constant"/>
        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S5_AXI_CTRL.BUSER_WIDTH" xilinx:valueSource="constant"/>
        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S5_AXI_CTRL.DATA_WIDTH" xilinx:valueSource="auto"/>
        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S5_AXI_CTRL.HAS_BRESP" xilinx:valueSource="auto"/>
        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S5_AXI_CTRL.HAS_BURST" xilinx:valueSource="constant"/>
        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S5_AXI_CTRL.HAS_CACHE" xilinx:valueSource="constant"/>
        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S5_AXI_CTRL.HAS_LOCK" xilinx:valueSource="constant"/>
        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S5_AXI_CTRL.HAS_PROT" xilinx:valueSource="constant"/>
        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S5_AXI_CTRL.HAS_QOS" xilinx:valueSource="constant"/>
        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S5_AXI_CTRL.HAS_REGION" xilinx:valueSource="constant"/>
        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S5_AXI_CTRL.HAS_RRESP" xilinx:valueSource="auto"/>
        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S5_AXI_CTRL.HAS_WSTRB" xilinx:valueSource="constant"/>
        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S5_AXI_CTRL.ID_WIDTH" xilinx:valueSource="constant"/>
        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S5_AXI_CTRL.PROTOCOL" xilinx:valueSource="constant"/>
        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S5_AXI_CTRL.RUSER_WIDTH" xilinx:valueSource="constant"/>
        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S5_AXI_CTRL.WUSER_WIDTH" xilinx:valueSource="constant"/>
        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S6_AXI.ADDR_WIDTH" xilinx:valueSource="auto"/>
        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S6_AXI.ARUSER_WIDTH" xilinx:valueSource="constant"/>
        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S6_AXI.AWUSER_WIDTH" xilinx:valueSource="constant"/>
        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S6_AXI.BUSER_WIDTH" xilinx:valueSource="constant"/>
        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S6_AXI.DATA_WIDTH" xilinx:valueSource="auto"/>
        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S6_AXI.HAS_BRESP" xilinx:valueSource="auto"/>
        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S6_AXI.HAS_BURST" xilinx:valueSource="auto"/>
        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S6_AXI.HAS_CACHE" xilinx:valueSource="auto"/>
        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S6_AXI.HAS_LOCK" xilinx:valueSource="auto"/>
        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S6_AXI.HAS_PROT" xilinx:valueSource="auto"/>
        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S6_AXI.HAS_QOS" xilinx:valueSource="auto"/>
        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S6_AXI.HAS_REGION" xilinx:valueSource="constant"/>
        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S6_AXI.HAS_RRESP" xilinx:valueSource="auto"/>
        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S6_AXI.HAS_WSTRB" xilinx:valueSource="auto"/>
        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S6_AXI.PROTOCOL" xilinx:valueSource="auto"/>
        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S6_AXI.RUSER_WIDTH" xilinx:valueSource="constant"/>
        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S6_AXI.WUSER_WIDTH" xilinx:valueSource="constant"/>
        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S6_AXI_CTRL.ADDR_WIDTH" xilinx:valueSource="auto"/>
        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S6_AXI_CTRL.ARUSER_WIDTH" xilinx:valueSource="constant"/>
        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S6_AXI_CTRL.AWUSER_WIDTH" xilinx:valueSource="constant"/>
        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S6_AXI_CTRL.BUSER_WIDTH" xilinx:valueSource="constant"/>
        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S6_AXI_CTRL.DATA_WIDTH" xilinx:valueSource="auto"/>
        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S6_AXI_CTRL.HAS_BRESP" xilinx:valueSource="auto"/>
        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S6_AXI_CTRL.HAS_BURST" xilinx:valueSource="constant"/>
        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S6_AXI_CTRL.HAS_CACHE" xilinx:valueSource="constant"/>
        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S6_AXI_CTRL.HAS_LOCK" xilinx:valueSource="constant"/>
        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S6_AXI_CTRL.HAS_PROT" xilinx:valueSource="constant"/>
        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S6_AXI_CTRL.HAS_QOS" xilinx:valueSource="constant"/>
        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S6_AXI_CTRL.HAS_REGION" xilinx:valueSource="constant"/>
        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S6_AXI_CTRL.HAS_RRESP" xilinx:valueSource="auto"/>
        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S6_AXI_CTRL.HAS_WSTRB" xilinx:valueSource="constant"/>
        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S6_AXI_CTRL.ID_WIDTH" xilinx:valueSource="constant"/>
        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S6_AXI_CTRL.PROTOCOL" xilinx:valueSource="constant"/>
        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S6_AXI_CTRL.RUSER_WIDTH" xilinx:valueSource="constant"/>
        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S6_AXI_CTRL.WUSER_WIDTH" xilinx:valueSource="constant"/>
        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S7_AXI.ADDR_WIDTH" xilinx:valueSource="auto"/>
        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S7_AXI.ARUSER_WIDTH" xilinx:valueSource="constant"/>
        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S7_AXI.AWUSER_WIDTH" xilinx:valueSource="constant"/>
        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S7_AXI.BUSER_WIDTH" xilinx:valueSource="constant"/>
        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S7_AXI.DATA_WIDTH" xilinx:valueSource="auto"/>
        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S7_AXI.HAS_BRESP" xilinx:valueSource="auto"/>
        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S7_AXI.HAS_BURST" xilinx:valueSource="auto"/>
        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S7_AXI.HAS_CACHE" xilinx:valueSource="auto"/>
        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S7_AXI.HAS_LOCK" xilinx:valueSource="auto"/>
        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S7_AXI.HAS_PROT" xilinx:valueSource="auto"/>
        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S7_AXI.HAS_QOS" xilinx:valueSource="auto"/>
        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S7_AXI.HAS_REGION" xilinx:valueSource="constant"/>
        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S7_AXI.HAS_RRESP" xilinx:valueSource="auto"/>
        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S7_AXI.HAS_WSTRB" xilinx:valueSource="auto"/>
        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S7_AXI.PROTOCOL" xilinx:valueSource="auto"/>
        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S7_AXI.RUSER_WIDTH" xilinx:valueSource="constant"/>
        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S7_AXI.WUSER_WIDTH" xilinx:valueSource="constant"/>
        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S7_AXI_CTRL.ADDR_WIDTH" xilinx:valueSource="auto"/>
        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S7_AXI_CTRL.ARUSER_WIDTH" xilinx:valueSource="constant"/>
        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S7_AXI_CTRL.AWUSER_WIDTH" xilinx:valueSource="constant"/>
        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S7_AXI_CTRL.BUSER_WIDTH" xilinx:valueSource="constant"/>
        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S7_AXI_CTRL.DATA_WIDTH" xilinx:valueSource="auto"/>
        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S7_AXI_CTRL.HAS_BRESP" xilinx:valueSource="auto"/>
        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S7_AXI_CTRL.HAS_BURST" xilinx:valueSource="constant"/>
        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S7_AXI_CTRL.HAS_CACHE" xilinx:valueSource="constant"/>
        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S7_AXI_CTRL.HAS_LOCK" xilinx:valueSource="constant"/>
        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S7_AXI_CTRL.HAS_PROT" xilinx:valueSource="constant"/>
        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S7_AXI_CTRL.HAS_QOS" xilinx:valueSource="constant"/>
        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S7_AXI_CTRL.HAS_REGION" xilinx:valueSource="constant"/>
        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S7_AXI_CTRL.HAS_RRESP" xilinx:valueSource="auto"/>
        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S7_AXI_CTRL.HAS_WSTRB" xilinx:valueSource="constant"/>
        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S7_AXI_CTRL.ID_WIDTH" xilinx:valueSource="constant"/>
        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S7_AXI_CTRL.PROTOCOL" xilinx:valueSource="constant"/>
        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S7_AXI_CTRL.RUSER_WIDTH" xilinx:valueSource="constant"/>
        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S7_AXI_CTRL.WUSER_WIDTH" xilinx:valueSource="constant"/>
        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.ADDR_WIDTH" xilinx:valueSource="auto"/>
        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.ARUSER_WIDTH" xilinx:valueSource="constant"/>
        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.AWUSER_WIDTH" xilinx:valueSource="constant"/>
        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.BUSER_WIDTH" xilinx:valueSource="constant"/>
        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.DATA_WIDTH" xilinx:valueSource="auto"/>
        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_BRESP" xilinx:valueSource="auto"/>
        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_BURST" xilinx:valueSource="auto"/>
        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_CACHE" xilinx:valueSource="auto"/>
        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_LOCK" xilinx:valueSource="auto"/>
        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_PROT" xilinx:valueSource="auto"/>
        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_QOS" xilinx:valueSource="auto"/>
        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_REGION" xilinx:valueSource="constant"/>
        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_RRESP" xilinx:valueSource="auto"/>
        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_WSTRB" xilinx:valueSource="auto"/>
        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.PROTOCOL" xilinx:valueSource="auto"/>
        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.RUSER_WIDTH" xilinx:valueSource="constant"/>
        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.WUSER_WIDTH" xilinx:valueSource="constant"/>
        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_CTRL.ADDR_WIDTH" xilinx:valueSource="auto"/>
        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_CTRL.ARUSER_WIDTH" xilinx:valueSource="constant"/>
        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_CTRL.AWUSER_WIDTH" xilinx:valueSource="constant"/>
        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_CTRL.BUSER_WIDTH" xilinx:valueSource="constant"/>
        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_CTRL.DATA_WIDTH" xilinx:valueSource="auto"/>
        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_CTRL.HAS_BRESP" xilinx:valueSource="auto"/>
        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_CTRL.HAS_BURST" xilinx:valueSource="constant"/>
        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_CTRL.HAS_CACHE" xilinx:valueSource="constant"/>
        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_CTRL.HAS_LOCK" xilinx:valueSource="constant"/>
        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_CTRL.HAS_PROT" xilinx:valueSource="constant"/>
        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_CTRL.HAS_QOS" xilinx:valueSource="constant"/>
        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_CTRL.HAS_REGION" xilinx:valueSource="constant"/>
        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_CTRL.HAS_RRESP" xilinx:valueSource="auto"/>
        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_CTRL.HAS_WSTRB" xilinx:valueSource="constant"/>
        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_CTRL.ID_WIDTH" xilinx:valueSource="constant"/>
        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_CTRL.PROTOCOL" xilinx:valueSource="constant"/>
        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_CTRL.RUSER_WIDTH" xilinx:valueSource="constant"/>
        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_CTRL.WUSER_WIDTH" xilinx:valueSource="constant"/>
        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.XML_INPUT_FILE" xilinx:valueSource="user"/>
      </xilinx:configElementInfos>
    </xilinx:coreExtensions>
    <xilinx:packagingInfo>
      <xilinx:xilinxVersion>2019.1.3</xilinx:xilinxVersion>
    </xilinx:packagingInfo>
  </spirit:vendorExtensions>
</spirit:component>
