######################################################################
#
# File name : testbench_compile.do
# Created on: Wed Apr 08 17:30:15 +0200 2020
#
# Auto generated by Vivado for 'behavioral' simulation
#
######################################################################
vlib modelsim_lib/work
vlib modelsim_lib/msim

vlib modelsim_lib/msim/xil_defaultlib
vlib modelsim_lib/msim/xpm
vlib modelsim_lib/msim/work
vlib modelsim_lib/msim/xbip_utils_v3_0_10
vlib modelsim_lib/msim/axi_utils_v2_0_6
vlib modelsim_lib/msim/cic_compiler_v4_0_14
vlib modelsim_lib/msim/fir_compiler_v7_2_12
vlib modelsim_lib/msim/fifo_generator_v13_2_4
vlib modelsim_lib/msim/util_vector_logic_v2_0_1
vlib modelsim_lib/msim/gaisler
vlib modelsim_lib/msim/grlib
vlib modelsim_lib/msim/techmap
vlib modelsim_lib/msim/eth
vlib modelsim_lib/msim/opencores
vlib modelsim_lib/msim/esa

vmap xil_defaultlib modelsim_lib/msim/xil_defaultlib
vmap xpm modelsim_lib/msim/xpm
vmap work modelsim_lib/msim/work
vmap xbip_utils_v3_0_10 modelsim_lib/msim/xbip_utils_v3_0_10
vmap axi_utils_v2_0_6 modelsim_lib/msim/axi_utils_v2_0_6
vmap cic_compiler_v4_0_14 modelsim_lib/msim/cic_compiler_v4_0_14
vmap fir_compiler_v7_2_12 modelsim_lib/msim/fir_compiler_v7_2_12
vmap fifo_generator_v13_2_4 modelsim_lib/msim/fifo_generator_v13_2_4
vmap util_vector_logic_v2_0_1 modelsim_lib/msim/util_vector_logic_v2_0_1
vmap gaisler modelsim_lib/msim/gaisler
vmap grlib modelsim_lib/msim/grlib
vmap techmap modelsim_lib/msim/techmap
vmap eth modelsim_lib/msim/eth
vmap opencores modelsim_lib/msim/opencores
vmap esa modelsim_lib/msim/esa

vlog -64 -incr -sv -work xil_defaultlib  "+incdir+../../../../dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/ipshared/c923" \
"C:/xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \
"C:/xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \

vcom -64 -93 -work xpm  \
"C:/xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \

vcom -64 -93 -work work  \
"../../../../dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/designs/leon3-xilinx-ac701/clk_div.vhd" \
"../../../../dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/designs/leon3-xilinx-ac701/hp_filter.vhd" \

vcom -64 -93 -work xil_defaultlib  \
"../../../../dat096_ref_design.srcs/sources_1/imports/vhdlcode/time_mux.vhdl" \

vcom -64 -93 -work xbip_utils_v3_0_10  \
"../../../../dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/ipshared/1123/hdl/xbip_utils_v3_0_vh_rfs.vhd" \

vcom -64 -93 -work axi_utils_v2_0_6  \
"../../../../dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/ipshared/1971/hdl/axi_utils_v2_0_vh_rfs.vhd" \

vcom -64 -93 -work cic_compiler_v4_0_14  \
"../../../../dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/ipshared/04e3/hdl/cic_compiler_v4_0_vh_rfs.vhd" \

vcom -64 -93 -work xil_defaultlib  \
"../../../../dat096_ref_design.ip_user_files/bd/pdm_to_pcm/ip/pdm_to_pcm_cic_compiler_0_0/sim/pdm_to_pcm_cic_compiler_0_0.vhd" \

vcom -64 -93 -work fir_compiler_v7_2_12  \
"../../../../dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/ipshared/c2da/hdl/fir_compiler_v7_2_vh_rfs.vhd" \

vcom -64 -93 -work xil_defaultlib  \
"../../../../dat096_ref_design.ip_user_files/bd/pdm_to_pcm/ip/pdm_to_pcm_fir_compiler_0_0/sim/pdm_to_pcm_fir_compiler_0_0.vhd" \
"../../../../dat096_ref_design.ip_user_files/bd/pdm_to_pcm/ip/pdm_to_pcm_fir_compiler_1_0/sim/pdm_to_pcm_fir_compiler_1_0.vhd" \

vlog -64 -incr -work xil_defaultlib  "+incdir+../../../../dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/ipshared/c923" \
"../../../../dat096_ref_design.ip_user_files/bd/pdm_to_pcm/ip/pdm_to_pcm_clk_wiz_0_0/pdm_to_pcm_clk_wiz_0_0_clk_wiz.v" \
"../../../../dat096_ref_design.ip_user_files/bd/pdm_to_pcm/ip/pdm_to_pcm_clk_wiz_0_0/pdm_to_pcm_clk_wiz_0_0.v" \

vlog -64 -incr -work fifo_generator_v13_2_4  "+incdir+../../../../dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/ipshared/c923" \
"../../../../dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/ipshared/1f5a/simulation/fifo_generator_vlog_beh.v" \

vcom -64 -93 -work fifo_generator_v13_2_4  \
"../../../../dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/ipshared/1f5a/hdl/fifo_generator_v13_2_rfs.vhd" \

vlog -64 -incr -work fifo_generator_v13_2_4  "+incdir+../../../../dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/ipshared/c923" \
"../../../../dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/ipshared/1f5a/hdl/fifo_generator_v13_2_rfs.v" \

vlog -64 -incr -work xil_defaultlib  "+incdir+../../../../dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/ipshared/c923" \
"../../../../dat096_ref_design.ip_user_files/bd/pdm_to_pcm/ip/pdm_to_pcm_fifo_generator_0_0/sim/pdm_to_pcm_fifo_generator_0_0.v" \

vlog -64 -incr -work util_vector_logic_v2_0_1  "+incdir+../../../../dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/ipshared/c923" \
"../../../../dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/ipshared/2137/hdl/util_vector_logic_v2_0_vl_rfs.v" \

vlog -64 -incr -work xil_defaultlib  "+incdir+../../../../dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/ipshared/c923" \
"../../../../dat096_ref_design.ip_user_files/bd/pdm_to_pcm/ip/pdm_to_pcm_util_vector_logic_0_0/sim/pdm_to_pcm_util_vector_logic_0_0.v" \
"../../../../dat096_ref_design.ip_user_files/bd/pdm_to_pcm/ip/pdm_to_pcm_clk_div_0_0/sim/pdm_to_pcm_clk_div_0_0.v" \

vcom -64 -93 -work xil_defaultlib  \
"../../../../dat096_ref_design.ip_user_files/bd/pdm_to_pcm/ip/pdm_to_pcm_util_ds_buf_0_0/util_ds_buf.vhd" \
"../../../../dat096_ref_design.ip_user_files/bd/pdm_to_pcm/ip/pdm_to_pcm_util_ds_buf_0_0/sim/pdm_to_pcm_util_ds_buf_0_0.vhd" \

vlog -64 -incr -work xil_defaultlib  "+incdir+../../../../dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/ipshared/c923" \
"../../../../dat096_ref_design.ip_user_files/bd/pdm_to_pcm/ip/pdm_to_pcm_clk_div_1_0/sim/pdm_to_pcm_clk_div_1_0.v" \
"../../../../dat096_ref_design.ip_user_files/bd/pdm_to_pcm/ip/pdm_to_pcm_hp_filter_0_0/sim/pdm_to_pcm_hp_filter_0_0.v" \
"../../../../dat096_ref_design.ip_user_files/bd/pdm_to_pcm/ip/pdm_to_pcm_util_vector_logic_0_2/sim/pdm_to_pcm_util_vector_logic_0_2.v" \
"../../../../dat096_ref_design.ip_user_files/bd/pdm_to_pcm/ip/pdm_to_pcm_timemux_0_2/sim/pdm_to_pcm_timemux_0_2.v" \
"../../../../dat096_ref_design.ip_user_files/bd/pdm_to_pcm/sim/pdm_to_pcm.v" \
"../../../../dat096_ref_design.srcs/sources_1/ip/mig/mig/user_design/rtl/clocking/mig_7series_v4_2_clk_ibuf.v" \
"../../../../dat096_ref_design.srcs/sources_1/ip/mig/mig/user_design/rtl/clocking/mig_7series_v4_2_infrastructure.v" \
"../../../../dat096_ref_design.srcs/sources_1/ip/mig/mig/user_design/rtl/clocking/mig_7series_v4_2_iodelay_ctrl.v" \
"../../../../dat096_ref_design.srcs/sources_1/ip/mig/mig/user_design/rtl/clocking/mig_7series_v4_2_tempmon.v" \
"../../../../dat096_ref_design.srcs/sources_1/ip/mig/mig/user_design/rtl/controller/mig_7series_v4_2_arb_mux.v" \
"../../../../dat096_ref_design.srcs/sources_1/ip/mig/mig/user_design/rtl/controller/mig_7series_v4_2_arb_row_col.v" \
"../../../../dat096_ref_design.srcs/sources_1/ip/mig/mig/user_design/rtl/controller/mig_7series_v4_2_arb_select.v" \
"../../../../dat096_ref_design.srcs/sources_1/ip/mig/mig/user_design/rtl/controller/mig_7series_v4_2_bank_cntrl.v" \
"../../../../dat096_ref_design.srcs/sources_1/ip/mig/mig/user_design/rtl/controller/mig_7series_v4_2_bank_common.v" \
"../../../../dat096_ref_design.srcs/sources_1/ip/mig/mig/user_design/rtl/controller/mig_7series_v4_2_bank_compare.v" \
"../../../../dat096_ref_design.srcs/sources_1/ip/mig/mig/user_design/rtl/controller/mig_7series_v4_2_bank_mach.v" \
"../../../../dat096_ref_design.srcs/sources_1/ip/mig/mig/user_design/rtl/controller/mig_7series_v4_2_bank_queue.v" \
"../../../../dat096_ref_design.srcs/sources_1/ip/mig/mig/user_design/rtl/controller/mig_7series_v4_2_bank_state.v" \
"../../../../dat096_ref_design.srcs/sources_1/ip/mig/mig/user_design/rtl/controller/mig_7series_v4_2_col_mach.v" \
"../../../../dat096_ref_design.srcs/sources_1/ip/mig/mig/user_design/rtl/controller/mig_7series_v4_2_mc.v" \
"../../../../dat096_ref_design.srcs/sources_1/ip/mig/mig/user_design/rtl/controller/mig_7series_v4_2_rank_cntrl.v" \
"../../../../dat096_ref_design.srcs/sources_1/ip/mig/mig/user_design/rtl/controller/mig_7series_v4_2_rank_common.v" \
"../../../../dat096_ref_design.srcs/sources_1/ip/mig/mig/user_design/rtl/controller/mig_7series_v4_2_rank_mach.v" \
"../../../../dat096_ref_design.srcs/sources_1/ip/mig/mig/user_design/rtl/controller/mig_7series_v4_2_round_robin_arb.v" \
"../../../../dat096_ref_design.srcs/sources_1/ip/mig/mig/user_design/rtl/ecc/mig_7series_v4_2_ecc_buf.v" \
"../../../../dat096_ref_design.srcs/sources_1/ip/mig/mig/user_design/rtl/ecc/mig_7series_v4_2_ecc_dec_fix.v" \
"../../../../dat096_ref_design.srcs/sources_1/ip/mig/mig/user_design/rtl/ecc/mig_7series_v4_2_ecc_gen.v" \
"../../../../dat096_ref_design.srcs/sources_1/ip/mig/mig/user_design/rtl/ecc/mig_7series_v4_2_ecc_merge_enc.v" \
"../../../../dat096_ref_design.srcs/sources_1/ip/mig/mig/user_design/rtl/ecc/mig_7series_v4_2_fi_xor.v" \
"../../../../dat096_ref_design.srcs/sources_1/ip/mig/mig/user_design/rtl/ip_top/mig_7series_v4_2_memc_ui_top_std.v" \
"../../../../dat096_ref_design.srcs/sources_1/ip/mig/mig/user_design/rtl/ip_top/mig_7series_v4_2_mem_intfc.v" \
"../../../../dat096_ref_design.srcs/sources_1/ip/mig/mig/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_group_io.v" \
"../../../../dat096_ref_design.srcs/sources_1/ip/mig/mig/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v" \
"../../../../dat096_ref_design.srcs/sources_1/ip/mig/mig/user_design/rtl/phy/mig_7series_v4_2_ddr_calib_top.v" \
"../../../../dat096_ref_design.srcs/sources_1/ip/mig/mig/user_design/rtl/phy/mig_7series_v4_2_ddr_if_post_fifo.v" \
"../../../../dat096_ref_design.srcs/sources_1/ip/mig/mig/user_design/rtl/phy/mig_7series_v4_2_ddr_mc_phy.v" \
"../../../../dat096_ref_design.srcs/sources_1/ip/mig/mig/user_design/rtl/phy/mig_7series_v4_2_ddr_mc_phy_wrapper.v" \
"../../../../dat096_ref_design.srcs/sources_1/ip/mig/mig/user_design/rtl/phy/mig_7series_v4_2_ddr_of_pre_fifo.v" \
"../../../../dat096_ref_design.srcs/sources_1/ip/mig/mig/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_4lanes.v" \
"../../../../dat096_ref_design.srcs/sources_1/ip/mig/mig/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_ck_addr_cmd_delay.v" \
"../../../../dat096_ref_design.srcs/sources_1/ip/mig/mig/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_dqs_found_cal.v" \
"../../../../dat096_ref_design.srcs/sources_1/ip/mig/mig/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_dqs_found_cal_hr.v" \
"../../../../dat096_ref_design.srcs/sources_1/ip/mig/mig/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_init.v" \
"../../../../dat096_ref_design.srcs/sources_1/ip/mig/mig/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_ocd_cntlr.v" \
"../../../../dat096_ref_design.srcs/sources_1/ip/mig/mig/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_ocd_data.v" \
"../../../../dat096_ref_design.srcs/sources_1/ip/mig/mig/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_ocd_edge.v" \
"../../../../dat096_ref_design.srcs/sources_1/ip/mig/mig/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_ocd_lim.v" \
"../../../../dat096_ref_design.srcs/sources_1/ip/mig/mig/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_ocd_mux.v" \
"../../../../dat096_ref_design.srcs/sources_1/ip/mig/mig/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_ocd_po_cntlr.v" \
"../../../../dat096_ref_design.srcs/sources_1/ip/mig/mig/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_ocd_samp.v" \
"../../../../dat096_ref_design.srcs/sources_1/ip/mig/mig/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_oclkdelay_cal.v" \
"../../../../dat096_ref_design.srcs/sources_1/ip/mig/mig/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_prbs_rdlvl.v" \
"../../../../dat096_ref_design.srcs/sources_1/ip/mig/mig/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_rdlvl.v" \
"../../../../dat096_ref_design.srcs/sources_1/ip/mig/mig/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_tempmon.v" \
"../../../../dat096_ref_design.srcs/sources_1/ip/mig/mig/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_top.v" \
"../../../../dat096_ref_design.srcs/sources_1/ip/mig/mig/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_wrcal.v" \
"../../../../dat096_ref_design.srcs/sources_1/ip/mig/mig/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_wrlvl.v" \
"../../../../dat096_ref_design.srcs/sources_1/ip/mig/mig/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_wrlvl_off_delay.v" \
"../../../../dat096_ref_design.srcs/sources_1/ip/mig/mig/user_design/rtl/phy/mig_7series_v4_2_ddr_prbs_gen.v" \
"../../../../dat096_ref_design.srcs/sources_1/ip/mig/mig/user_design/rtl/phy/mig_7series_v4_2_ddr_skip_calib_tap.v" \
"../../../../dat096_ref_design.srcs/sources_1/ip/mig/mig/user_design/rtl/phy/mig_7series_v4_2_poc_cc.v" \
"../../../../dat096_ref_design.srcs/sources_1/ip/mig/mig/user_design/rtl/phy/mig_7series_v4_2_poc_edge_store.v" \
"../../../../dat096_ref_design.srcs/sources_1/ip/mig/mig/user_design/rtl/phy/mig_7series_v4_2_poc_meta.v" \
"../../../../dat096_ref_design.srcs/sources_1/ip/mig/mig/user_design/rtl/phy/mig_7series_v4_2_poc_pd.v" \
"../../../../dat096_ref_design.srcs/sources_1/ip/mig/mig/user_design/rtl/phy/mig_7series_v4_2_poc_tap_base.v" \
"../../../../dat096_ref_design.srcs/sources_1/ip/mig/mig/user_design/rtl/phy/mig_7series_v4_2_poc_top.v" \
"../../../../dat096_ref_design.srcs/sources_1/ip/mig/mig/user_design/rtl/ui/mig_7series_v4_2_ui_cmd.v" \
"../../../../dat096_ref_design.srcs/sources_1/ip/mig/mig/user_design/rtl/ui/mig_7series_v4_2_ui_rd_data.v" \
"../../../../dat096_ref_design.srcs/sources_1/ip/mig/mig/user_design/rtl/ui/mig_7series_v4_2_ui_top.v" \
"../../../../dat096_ref_design.srcs/sources_1/ip/mig/mig/user_design/rtl/ui/mig_7series_v4_2_ui_wr_data.v" \
"../../../../dat096_ref_design.srcs/sources_1/ip/mig/mig/user_design/rtl/mig_mig_sim.v" \
"../../../../dat096_ref_design.srcs/sources_1/ip/mig/mig/user_design/rtl/mig.v" \

vlog -64 -incr -work gaisler  "+incdir+../../../../dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/ipshared/c923" \
"../../../../dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/gaisler/ddr/mig_interface_model.v" \

vlog -64 -incr -work work  "+incdir+../../../../dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/ipshared/c923" \
"../../../../dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/hdl/pdm_to_pcm_wrapper.v" \

vcom -64 -93 -work grlib  \
"../../../../dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/grlib/stdlib/config_types.vhd" \
"../../../../dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/grlib/stdlib/config.vhd" \
"../../../../dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/grlib/stdlib/version.vhd" \
"../../../../dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/grlib/stdlib/stdlib.vhd" \
"../../../../dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/grlib/amba/amba.vhd" \
"../../../../dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/grlib/amba/devices.vhd" \

vcom -64 -93 -work techmap  \
"../../../../dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/techmap/gencomp/gencomp.vhd" \

vcom -64 -93 -work gaisler  \
"../../../../dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/gaisler/misc/misc.vhd" \
"../../../../dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/gaisler/ddr/ahb2mig_7series_pkg.vhd" \
"../../../../dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/gaisler/ddr/ahb2mig_7series.vhd" \

vcom -64 -93 -work work  \
"../../../../dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/designs/leon3-xilinx-ac701/ahb_mst_pkg.vhd" \
"../../../../dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/designs/leon3-xilinx-ac701/ahb_master_wr.vhd" \

vcom -64 -93 -work grlib  \
"../../../../dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/grlib/stdlib/stdio.vhd" \
"../../../../dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/grlib/stdlib/testlib.vhd" \
"../../../../dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/grlib/amba/ahbctrl.vhd" \

vcom -64 -93 -work gaisler  \
"../../../../dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/gaisler/jtag/libjtagcom.vhd" \
"../../../../dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/gaisler/jtag/jtag.vhd" \
"../../../../dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/gaisler/jtag/ahbjtag.vhd" \

vcom -64 -93 -work grlib  \
"../../../../dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/grlib/amba/ahbmst.vhd" \

vcom -64 -93 -work gaisler  \
"../../../../dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/gaisler/misc/ahbram.vhd" \
"../../../../dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/gaisler/sim/ahbram_sim.vhd" \
"../../../../dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/gaisler/sim/sim.vhd" \
"../../../../dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/gaisler/sim/ahbrep.vhd" \

vcom -64 -93 -work work  \
"../../../../dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/designs/leon3-xilinx-ac701/ahbrom.vhd" \

vcom -64 -93 -work gaisler  \
"../../../../dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/gaisler/misc/ahbstat.vhd" \
"../../../../dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/gaisler/uart/uart.vhd" \
"../../../../dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/gaisler/uart/libdcom.vhd" \
"../../../../dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/gaisler/uart/ahbuart.vhd" \

vcom -64 -93 -work techmap  \
"../../../../dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/techmap/maps/allclkgen.vhd" \
"../../../../dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/techmap/maps/allddr.vhd" \
"../../../../dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/techmap/maps/allmem.vhd" \
"../../../../dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/techmap/maps/allmul.vhd" \
"../../../../dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/techmap/maps/allpads.vhd" \
"../../../../dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/techmap/maps/alltap.vhd" \

vcom -64 -93 -work grlib  \
"../../../../dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/grlib/amba/apbctrl.vhd" \
"../../../../dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/grlib/amba/apbctrlx.vhd" \

vcom -64 -93 -work gaisler  \
"../../../../dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/gaisler/uart/apbuart.vhd" \
"../../../../dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/gaisler/arith/arith.vhd" \

vcom -64 -93 -work techmap  \
"../../../../dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/techmap/unisim/buffer_unisim.vhd" \

vcom -64 -93 -work gaisler  \
"../../../../dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/gaisler/leon3/leon3.vhd" \
"../../../../dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/gaisler/leon3v3/libfpu.vhd" \
"../../../../dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/gaisler/srmmu/mmuconfig.vhd" \
"../../../../dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/gaisler/leon3v3/libiu.vhd" \
"../../../../dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/gaisler/srmmu/mmuiface.vhd" \
"../../../../dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/gaisler/leon3v3/libcache.vhd" \
"../../../../dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/gaisler/leon3v3/cachemem.vhd" \

vcom -64 -93 -work techmap  \
"../../../../dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/techmap/maps/clkand.vhd" \
"../../../../dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/techmap/maps/clkgen.vhd" \
"../../../../dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/techmap/unisim/clkgen_unisim.vhd" \
"../../../../dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/techmap/maps/clkmux.vhd" \
"../../../../dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/techmap/maps/clkpad_ds.vhd" \

vcom -64 -93 -work gaisler  \
"../../../../dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/gaisler/leon3v3/cmvalidbits.vhd" \

vcom -64 -93 -work work  \
"../../../../dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/designs/leon3-xilinx-ac701/config.vhd" \

vcom -64 -93 -work grlib  \
"../../../../dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/grlib/sparc/sparc.vhd" \
"../../../../dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/grlib/sparc/sparc_disas.vhd" \

vcom -64 -93 -work gaisler  \
"../../../../dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/gaisler/uart/dcom.vhd" \
"../../../../dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/gaisler/uart/dcom_uart.vhd" \
"../../../../dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/gaisler/sim/ddr3ram.vhd" \

vcom -64 -93 -work work  \
"../../../../dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/designs/leon3-xilinx-ac701/ddr_dummy.vhd" \

vcom -64 -93 -work techmap  \
"../../../../dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/techmap/inferred/ddr_inferred.vhd" \
"../../../../dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/techmap/maps/ddr_oreg.vhd" \
"../../../../dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/techmap/unisim/ddr_unisim.vhd" \

vcom -64 -93 -work work  \
"../../../../dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/work/debug/debug.vhd" \

vcom -64 -93 -work gaisler  \
"../../../../dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/gaisler/arith/div32.vhd" \
"../../../../dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/gaisler/leon3v3/dsu3x.vhd" \

vcom -64 -93 -work eth  \
"../../../../dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/eth/core/greth_pkg.vhd" \
"../../../../dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/eth/core/eth_ahb_mst.vhd" \
"../../../../dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/eth/core/eth_edcl_ahb_mst.vhd" \
"../../../../dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/eth/core/eth_rstgen.vhd" \
"../../../../dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/eth/comp/ethcomp.vhd" \

vcom -64 -93 -work gaisler  \
"../../../../dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/gaisler/net/net.vhd" \
"../../../../dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/gaisler/greth/ethernet_mac.vhd" \
"../../../../dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/gaisler/misc/gptimer.vhd" \
"../../../../dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/gaisler/greth/greth.vhd" \
"../../../../dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/gaisler/greth/greth_gbit.vhd" \

vcom -64 -93 -work eth  \
"../../../../dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/eth/core/greth_rx.vhd" \
"../../../../dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/eth/core/greth_tx.vhd" \
"../../../../dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/eth/core/grethc.vhd" \

vcom -64 -93 -work gaisler  \
"../../../../dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/gaisler/greth/grethm.vhd" \
"../../../../dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/gaisler/leon3/grfpushwx.vhd" \

vcom -64 -93 -work techmap  \
"../../../../dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/techmap/maps/grfpw_net.vhd" \
"../../../../dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/techmap/gencomp/netcomp.vhd" \

vcom -64 -93 -work gaisler  \
"../../../../dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/gaisler/leon3v3/libleon3.vhd" \
"../../../../dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/gaisler/leon3v3/grfpwx.vhd" \
"../../../../dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/gaisler/leon3v3/grfpwxsh.vhd" \

vcom -64 -93 -work techmap  \
"../../../../dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/techmap/maps/grgates.vhd" \
"../../../../dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/techmap/maps/grlfpw_net.vhd" \

vcom -64 -93 -work gaisler  \
"../../../../dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/gaisler/leon3v3/grlfpwx.vhd" \
"../../../../dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/gaisler/i2c/i2c.vhd" \

vcom -64 -93 -work opencores  \
"../../../../dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/i2c/i2c_master_bit_ctrl.vhd" \
"../../../../dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/i2c/i2c_master_byte_ctrl.vhd" \
"../../../../dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/i2c/i2coc.vhd" \

vcom -64 -93 -work gaisler  \
"../../../../dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/gaisler/i2c/i2cmst.vhd" \

vcom -64 -93 -work techmap  \
"../../../../dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/techmap/maps/inpad.vhd" \
"../../../../dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/techmap/maps/iopad.vhd" \

vcom -64 -93 -work gaisler  \
"../../../../dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/gaisler/irqmp/irqmp.vhd" \
"../../../../dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/gaisler/leon3v3/iu3.vhd" \
"../../../../dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/gaisler/jtag/jtagcom.vhd" \
"../../../../dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/gaisler/jtag/jtagcom2.vhd" \
"../../../../dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/gaisler/l2cache/pkg/l2cache.vhd" \
"../../../../dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/gaisler/leon3v3/l3stat.vhd" \

vcom -64 -93 -work grlib  \
"../../../../dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/grlib/modgen/leaves.vhd" \

vcom -64 -93 -work techmap  \
"../../../../dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/techmap/maps/leon3_net.vhd" \

vcom -64 -93 -work gaisler  \
"../../../../dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/gaisler/memctrl/memctrl.vhd" \
"../../../../dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/gaisler/spi/spi.vhd" \
"../../../../dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/gaisler/subsys/subsys.vhd" \

vcom -64 -93 -work esa  \
"../../../../dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/esa/memoryctrl/memoryctrl.vhd" \

vcom -64 -93 -work work  \
"../../../../dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/designs/leon3-xilinx-ac701/leon3mp.vhd" \

vcom -64 -93 -work gaisler  \
"../../../../dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/gaisler/leon3v3/leon3x.vhd" \
"../../../../dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/gaisler/leon4/leon4.vhd" \
"../../../../dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/gaisler/subsys/leon_dsu_stat_base.vhd" \
"../../../../dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/gaisler/srmmu/libmmu.vhd" \
"../../../../dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/gaisler/misc/logan.vhd" \

vcom -64 -93 -work techmap  \
"../../../../dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/techmap/inferred/memory_inferred.vhd" \
"../../../../dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/techmap/unisim/memory_kintex7.vhd" \
"../../../../dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/techmap/unisim/memory_unisim.vhd" \
"../../../../dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/techmap/maps/memrwcol.vhd" \

vcom -64 -93 -work gaisler  \
"../../../../dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/gaisler/srmmu/mmu.vhd" \
"../../../../dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/gaisler/leon3v3/mmu_acache.vhd" \
"../../../../dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/gaisler/leon3v3/mmu_cache.vhd" \
"../../../../dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/gaisler/leon3v3/mmu_dcache.vhd" \
"../../../../dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/gaisler/leon3v3/mmu_icache.vhd" \
"../../../../dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/gaisler/srmmu/mmulru.vhd" \
"../../../../dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/gaisler/srmmu/mmulrue.vhd" \
"../../../../dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/gaisler/srmmu/mmutlb.vhd" \
"../../../../dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/gaisler/srmmu/mmutlbcam.vhd" \
"../../../../dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/gaisler/srmmu/mmutw.vhd" \

vcom -64 -93 -work grlib  \
"../../../../dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/grlib/modgen/multlib.vhd" \

vcom -64 -93 -work gaisler  \
"../../../../dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/gaisler/arith/mul32.vhd" \

vcom -64 -93 -work techmap  \
"../../../../dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/techmap/inferred/mul_inferred.vhd" \
"../../../../dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/techmap/maps/odpad.vhd" \
"../../../../dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/techmap/maps/outpad.vhd" \
"../../../../dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/techmap/unisim/pads_unisim.vhd" \

vcom -64 -93 -work gaisler  \
"../../../../dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/gaisler/sim/phy.vhd" \
"../../../../dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/gaisler/leon3v3/proc3.vhd" \

vcom -64 -93 -work techmap  \
"../../../../dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/techmap/maps/regfile_3p.vhd" \

vcom -64 -93 -work gaisler  \
"../../../../dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/gaisler/leon3v3/regfile_3p_l3.vhd" \
"../../../../dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/gaisler/greth/adapters/rgmii_series7.vhd" \
"../../../../dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/gaisler/misc/rstgen.vhd" \
"../../../../dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/gaisler/spi/spi_flash.vhd" \
"../../../../dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/gaisler/spi/spictrl.vhd" \

vcom -64 -93 -work techmap  \
"../../../../dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/techmap/maps/spictrl_net.vhd" \
"../../../../dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/techmap/unisim/spictrl_unisim.vhd" \

vcom -64 -93 -work gaisler  \
"../../../../dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/gaisler/spi/spictrlx.vhd" \
"../../../../dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/gaisler/spi/spimctrl.vhd" \

vcom -64 -93 -work techmap  \
"../../../../dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/techmap/maps/syncram.vhd" \
"../../../../dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/techmap/maps/syncram64.vhd" \
"../../../../dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/techmap/maps/syncram_2p.vhd" \
"../../../../dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/techmap/maps/syncram_dp.vhd" \
"../../../../dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/techmap/maps/syncrambw.vhd" \
"../../../../dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/techmap/maps/syncreg.vhd" \
"../../../../dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/techmap/maps/tap.vhd" \
"../../../../dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/techmap/unisim/tap_unisim.vhd" \

vcom -64 -93 -work gaisler  \
"../../../../dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/gaisler/leon3v3/tbufmem.vhd" \
"../../../../dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/gaisler/leon3v3/tbufmem_2p.vhd" \

vcom -64 -93 -work techmap  \
"../../../../dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/techmap/maps/techbuf.vhd" \
"../../../../dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/techmap/maps/techmult.vhd" \

vcom -64 -93 -work grlib  \
"../../../../dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/grlib/util/util.vhd" \

vcom -64 -93 -work work  \
"../../../../dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/designs/leon3-xilinx-ac701/testbench.vhd" \

# compile glbl module
vlog -work work "glbl.v"

quit -force

