library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity scanning is
    Port ( clk : in STD_LOGIC;
           start : in STD_LOGIC;
           t_finish : in STD_LOGIC;
           adder_enable : out STD_LOGIC;
           fifo_wr_en : out STD_LOGIC;
           scan_finish : out STD_LOGIC;
           address_0 : out STD_LOGIC_VECTOR (4 downto 0);
	   address_1 : out STD_LOGIC_VECTOR (4 downto 0);
           address_2 : out STD_LOGIC_VECTOR (4 downto 0);
	   address_3 : out STD_LOGIC_VECTOR (4 downto 0));
end scanning;

architecture behavior of scanning is
  type STATES is (IDLE, DELAY, SUM, SAMPLE, ANGLE);
  type CYCLES is array (0 to 6) of integer;
  signal state : STATES := IDLE;
  signal cycle : integer := 400;--(2,4,6,0,6,4,2);--400
  --(399,297,158,0,158,297,399);--the max cycle number of delays for each angle
begin
  process (clk) 
    variable i : integer := 0;
    variable j : integer := 0;
    variable k : integer := 0; 
    variable k_0 : integer := 1; 	
    variable k_1 : integer := 0; 
    variable k_2 : integer := 0;
    variable k_3 : integer := 0; 
	
  begin
    if (rising_edge(clk)) then
        case state is
          -- Waiting for start
          when IDLE =>
            scan_finish <= '0';
            fifo_wr_en <= '0';
            adder_enable <= '0';
            address_0 <= "00001";
            address_1 <= "00010";
            address_2 <= "00011";
            address_3 <= "00100";

            if (start = '1') then
              state <= DELAY;
            end if;
          -- Wair until all data on all streams are delayed enough
          when DELAY =>
            scan_finish <= '0';
            if (start = '0') then
              state <= IDLE;
            else
              -- Wait for valid sampled data on demux after FIR Filter
              if (t_finish = '1') then
                if (i < cycle) then  --????????delay??????sum??counter
                  i := i + 1;
                else
                  i := 0;
                  state <= SUM;               
                end if;
              end if;
            end if;


          -- Summation of valid delayed streams
          when SUM =>
            if (start = '0') then
              state <= IDLE;
            else
              if (t_finish = '1') then
                adder_enable <= '1';
                j := j + 1; 
                state <= SAMPLE;
              end if;             
            end if;
          -- Wait for next velid delayed samples
          when SAMPLE =>
            if (start = '0') then
              state <= IDLE;
            else
              adder_enable <= '0';

              --if (j < 100000) then --????valid time
               if (j < 10) then
                state <= SUM;
              else
                state <= ANGLE;
                fifo_wr_en <= '1';
                j := 0;             
              end if;
            end if;
          -- Move to next angle analysis
          when ANGLE =>
            fifo_wr_en <= '0';
            scan_finish <= '1';
            if (start = '0') then
              state <= IDLE;
            else
              if (k < 6) then  --?cycle???
                k := k + 1;
                k_0 := k_0 + 4;   --5,6,7,8         
              else
                k := 0;             
              end if;
			  
			  --k_0 := k + 24;
			  k_1 := k_0 + 1;
			  k_2 := k_1 + 1;
			  k_3 := k_2 + 1;
			  
              address_0  <= std_logic_vector(to_unsigned(k_0, 5));  --??5,??????????
			  address_1  <= std_logic_vector(to_unsigned(k_1, 5));
              address_2  <= std_logic_vector(to_unsigned(k_2, 5));
			  address_3  <= std_logic_vector(to_unsigned(k_3, 5));
              state <= DELAY; 
            end if;                                                         
        end case;
    end if;
  end process;
end behavior;



