# do {testbench_compile.do}
# QuestaSim-64 vmap 10.6c Lib Mapping Utility 2017.07 Jul 26 2017
# vmap xil_defaultlib modelsim_lib/msim/xil_defaultlib 
# Copying C:/questasim64_10.6c/win64/../modelsim.ini to modelsim.ini
# Modifying modelsim.ini
# QuestaSim-64 vmap 10.6c Lib Mapping Utility 2017.07 Jul 26 2017
# vmap xpm modelsim_lib/msim/xpm 
# Modifying modelsim.ini
# QuestaSim-64 vmap 10.6c Lib Mapping Utility 2017.07 Jul 26 2017
# vmap work modelsim_lib/msim/work 
# Modifying modelsim.ini
# QuestaSim-64 vmap 10.6c Lib Mapping Utility 2017.07 Jul 26 2017
# vmap xbip_utils_v3_0_10 modelsim_lib/msim/xbip_utils_v3_0_10 
# Modifying modelsim.ini
# QuestaSim-64 vmap 10.6c Lib Mapping Utility 2017.07 Jul 26 2017
# vmap axi_utils_v2_0_6 modelsim_lib/msim/axi_utils_v2_0_6 
# Modifying modelsim.ini
# QuestaSim-64 vmap 10.6c Lib Mapping Utility 2017.07 Jul 26 2017
# vmap cic_compiler_v4_0_14 modelsim_lib/msim/cic_compiler_v4_0_14 
# Modifying modelsim.ini
# QuestaSim-64 vmap 10.6c Lib Mapping Utility 2017.07 Jul 26 2017
# vmap fir_compiler_v7_2_12 modelsim_lib/msim/fir_compiler_v7_2_12 
# Modifying modelsim.ini
# QuestaSim-64 vmap 10.6c Lib Mapping Utility 2017.07 Jul 26 2017
# vmap fifo_generator_v13_2_4 modelsim_lib/msim/fifo_generator_v13_2_4 
# Modifying modelsim.ini
# QuestaSim-64 vmap 10.6c Lib Mapping Utility 2017.07 Jul 26 2017
# vmap util_vector_logic_v2_0_1 modelsim_lib/msim/util_vector_logic_v2_0_1 
# Modifying modelsim.ini
# QuestaSim-64 vmap 10.6c Lib Mapping Utility 2017.07 Jul 26 2017
# vmap gaisler modelsim_lib/msim/gaisler 
# Modifying modelsim.ini
# QuestaSim-64 vmap 10.6c Lib Mapping Utility 2017.07 Jul 26 2017
# vmap grlib modelsim_lib/msim/grlib 
# Modifying modelsim.ini
# QuestaSim-64 vmap 10.6c Lib Mapping Utility 2017.07 Jul 26 2017
# vmap techmap modelsim_lib/msim/techmap 
# Modifying modelsim.ini
# QuestaSim-64 vmap 10.6c Lib Mapping Utility 2017.07 Jul 26 2017
# vmap eth modelsim_lib/msim/eth 
# Modifying modelsim.ini
# QuestaSim-64 vmap 10.6c Lib Mapping Utility 2017.07 Jul 26 2017
# vmap opencores modelsim_lib/msim/opencores 
# Modifying modelsim.ini
# QuestaSim-64 vmap 10.6c Lib Mapping Utility 2017.07 Jul 26 2017
# vmap esa modelsim_lib/msim/esa 
# Modifying modelsim.ini
# ** Warning: (vlog-159) Mode option -64 is not supported in this context and will be ignored.
# QuestaSim-64 vlog 10.6c Compiler 2017.07 Jul 26 2017
# Start time: 17:30:30 on Apr 08,2020
# vlog -64 -incr -sv -work xil_defaultlib "+incdir+../../../../dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/ipshared/c923" C:/xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv C:/xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv 
# -- Compiling module xpm_cdc_single
# -- Compiling module xpm_cdc_gray
# -- Compiling module xpm_cdc_handshake
# -- Compiling module xpm_cdc_pulse
# -- Compiling module xpm_cdc_array_single
# -- Compiling module xpm_cdc_sync_rst
# -- Compiling module xpm_cdc_async_rst
# -- Compiling module xpm_cdc_low_latency_handshake
# -- Compiling module xpm_memory_base
# -- Compiling module asym_bwe_bb
# -- Compiling module xpm_memory_dpdistram
# -- Compiling module xpm_memory_dprom
# -- Compiling module xpm_memory_sdpram
# -- Compiling module xpm_memory_spram
# -- Compiling module xpm_memory_sprom
# -- Compiling module xpm_memory_tdpram
# 
# Top level modules:
# 	xpm_cdc_gray
# 	xpm_cdc_handshake
# 	xpm_cdc_pulse
# 	xpm_cdc_array_single
# 	xpm_cdc_sync_rst
# 	xpm_cdc_async_rst
# 	xpm_cdc_low_latency_handshake
# 	xpm_memory_dpdistram
# 	xpm_memory_dprom
# 	xpm_memory_sdpram
# 	xpm_memory_spram
# 	xpm_memory_sprom
# 	xpm_memory_tdpram
# End time: 17:30:30 on Apr 08,2020, Elapsed time: 0:00:00
# Errors: 0, Warnings: 1
# ** Warning: (vcom-159) Mode option -64 is not supported in this context and will be ignored.
# QuestaSim-64 vcom 10.6c Compiler 2017.07 Jul 26 2017
# Start time: 17:30:30 on Apr 08,2020
# vcom -64 -93 -work xpm C:/xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd 
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Compiling package VCOMPONENTS
# End time: 17:30:30 on Apr 08,2020, Elapsed time: 0:00:00
# Errors: 0, Warnings: 1
# ** Warning: (vcom-159) Mode option -64 is not supported in this context and will be ignored.
# QuestaSim-64 vcom 10.6c Compiler 2017.07 Jul 26 2017
# Start time: 17:30:30 on Apr 08,2020
# vcom -64 -93 -work work ../../../../dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/designs/leon3-xilinx-ac701/clk_div.vhd ../../../../dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/designs/leon3-xilinx-ac701/hp_filter.vhd 
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# ** Error: ../../../../dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/designs/leon3-xilinx-ac701/clk_div.vhd(25): (vcom-1598) Library "unisim" not found.
# ** Error: ../../../../dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/designs/leon3-xilinx-ac701/clk_div.vhd(26): (vcom-1136) Unknown identifier "UNISIM".
# ** Error: ../../../../dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/designs/leon3-xilinx-ac701/clk_div.vhd(38): VHDL Compiler exiting
# End time: 17:30:30 on Apr 08,2020, Elapsed time: 0:00:00
# Errors: 3, Warnings: 1
# ** Error: C:/questasim64_10.6c/win64/vcom failed.
# Error in macro ./testbench_compile.do line 54
# C:/questasim64_10.6c/win64/vcom failed.
#     while executing
# "vcom -64 -93 -work work  \
# "../../../../dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/designs/leon3-xilinx-ac701/clk_div.vhd" \
# "../..."
