vlib modelsim_lib/work
vlib modelsim_lib/msim

vlib modelsim_lib/msim/xil_defaultlib
vlib modelsim_lib/msim/xpm
vlib modelsim_lib/msim/xbip_utils_v3_0_10
vlib modelsim_lib/msim/axi_utils_v2_0_6
vlib modelsim_lib/msim/cic_compiler_v4_0_14
vlib modelsim_lib/msim/fir_compiler_v7_2_12
vlib modelsim_lib/msim/fifo_generator_v13_2_4
vlib modelsim_lib/msim/util_vector_logic_v2_0_1
vlib modelsim_lib/msim/c_reg_fd_v12_0_6
vlib modelsim_lib/msim/xbip_dsp48_wrapper_v3_0_4
vlib modelsim_lib/msim/xbip_pipe_v3_0_6
vlib modelsim_lib/msim/xbip_dsp48_addsub_v3_0_6
vlib modelsim_lib/msim/xbip_addsub_v3_0_6
vlib modelsim_lib/msim/c_addsub_v12_0_13
vlib modelsim_lib/msim/blk_mem_gen_v8_4_3
vlib modelsim_lib/msim/c_mux_bit_v12_0_6
vlib modelsim_lib/msim/c_shift_ram_v12_0_13
vlib modelsim_lib/msim/xbip_bram18k_v3_0_6
vlib modelsim_lib/msim/mult_gen_v12_0_15

vmap xil_defaultlib modelsim_lib/msim/xil_defaultlib
vmap xpm modelsim_lib/msim/xpm
vmap xbip_utils_v3_0_10 modelsim_lib/msim/xbip_utils_v3_0_10
vmap axi_utils_v2_0_6 modelsim_lib/msim/axi_utils_v2_0_6
vmap cic_compiler_v4_0_14 modelsim_lib/msim/cic_compiler_v4_0_14
vmap fir_compiler_v7_2_12 modelsim_lib/msim/fir_compiler_v7_2_12
vmap fifo_generator_v13_2_4 modelsim_lib/msim/fifo_generator_v13_2_4
vmap util_vector_logic_v2_0_1 modelsim_lib/msim/util_vector_logic_v2_0_1
vmap c_reg_fd_v12_0_6 modelsim_lib/msim/c_reg_fd_v12_0_6
vmap xbip_dsp48_wrapper_v3_0_4 modelsim_lib/msim/xbip_dsp48_wrapper_v3_0_4
vmap xbip_pipe_v3_0_6 modelsim_lib/msim/xbip_pipe_v3_0_6
vmap xbip_dsp48_addsub_v3_0_6 modelsim_lib/msim/xbip_dsp48_addsub_v3_0_6
vmap xbip_addsub_v3_0_6 modelsim_lib/msim/xbip_addsub_v3_0_6
vmap c_addsub_v12_0_13 modelsim_lib/msim/c_addsub_v12_0_13
vmap blk_mem_gen_v8_4_3 modelsim_lib/msim/blk_mem_gen_v8_4_3
vmap c_mux_bit_v12_0_6 modelsim_lib/msim/c_mux_bit_v12_0_6
vmap c_shift_ram_v12_0_13 modelsim_lib/msim/c_shift_ram_v12_0_13
vmap xbip_bram18k_v3_0_6 modelsim_lib/msim/xbip_bram18k_v3_0_6
vmap mult_gen_v12_0_15 modelsim_lib/msim/mult_gen_v12_0_15

vlog -work xil_defaultlib -64 -incr -sv "+incdir+../../../../dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/ipshared/c923" \
"C:/xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \
"C:/xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \

vcom -work xpm -64 -93 \
"C:/xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \

vcom -work xbip_utils_v3_0_10 -64 -93 \
"../../../../dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/ipshared/1123/hdl/xbip_utils_v3_0_vh_rfs.vhd" \

vcom -work axi_utils_v2_0_6 -64 -93 \
"../../../../dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/ipshared/1971/hdl/axi_utils_v2_0_vh_rfs.vhd" \

vcom -work cic_compiler_v4_0_14 -64 -93 \
"../../../../dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/ipshared/04e3/hdl/cic_compiler_v4_0_vh_rfs.vhd" \

vcom -work xil_defaultlib -64 -93 \
"../../../bd/pdm_to_pcm/ip/pdm_to_pcm_cic_compiler_0_0/sim/pdm_to_pcm_cic_compiler_0_0.vhd" \

vcom -work fir_compiler_v7_2_12 -64 -93 \
"../../../../dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/ipshared/c2da/hdl/fir_compiler_v7_2_vh_rfs.vhd" \

vcom -work xil_defaultlib -64 -93 \
"../../../bd/pdm_to_pcm/ip/pdm_to_pcm_fir_compiler_0_0/sim/pdm_to_pcm_fir_compiler_0_0.vhd" \
"../../../bd/pdm_to_pcm/ip/pdm_to_pcm_fir_compiler_1_0/sim/pdm_to_pcm_fir_compiler_1_0.vhd" \

vlog -work xil_defaultlib -64 -incr "+incdir+../../../../dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/ipshared/c923" \
"../../../bd/pdm_to_pcm/ip/pdm_to_pcm_clk_wiz_0_0/pdm_to_pcm_clk_wiz_0_0_clk_wiz.v" \
"../../../bd/pdm_to_pcm/ip/pdm_to_pcm_clk_wiz_0_0/pdm_to_pcm_clk_wiz_0_0.v" \

vlog -work fifo_generator_v13_2_4 -64 -incr "+incdir+../../../../dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/ipshared/c923" \
"../../../../dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/ipshared/1f5a/simulation/fifo_generator_vlog_beh.v" \

vcom -work fifo_generator_v13_2_4 -64 -93 \
"../../../../dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/ipshared/1f5a/hdl/fifo_generator_v13_2_rfs.vhd" \

vlog -work fifo_generator_v13_2_4 -64 -incr "+incdir+../../../../dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/ipshared/c923" \
"../../../../dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/ipshared/1f5a/hdl/fifo_generator_v13_2_rfs.v" \

vlog -work xil_defaultlib -64 -incr "+incdir+../../../../dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/ipshared/c923" \
"../../../bd/pdm_to_pcm/ip/pdm_to_pcm_fifo_generator_0_0/sim/pdm_to_pcm_fifo_generator_0_0.v" \

vlog -work util_vector_logic_v2_0_1 -64 -incr "+incdir+../../../../dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/ipshared/c923" \
"../../../../dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/ipshared/2137/hdl/util_vector_logic_v2_0_vl_rfs.v" \

vlog -work xil_defaultlib -64 -incr "+incdir+../../../../dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/ipshared/c923" \
"../../../bd/pdm_to_pcm/ip/pdm_to_pcm_util_vector_logic_0_0/sim/pdm_to_pcm_util_vector_logic_0_0.v" \

vcom -work xil_defaultlib -64 -93 \
"../../../bd/pdm_to_pcm/ip/pdm_to_pcm_clk_div_0_0/sim/pdm_to_pcm_clk_div_0_0.vhd" \
"../../../bd/pdm_to_pcm/ip/pdm_to_pcm_util_ds_buf_0_0/util_ds_buf.vhd" \
"../../../bd/pdm_to_pcm/ip/pdm_to_pcm_util_ds_buf_0_0/sim/pdm_to_pcm_util_ds_buf_0_0.vhd" \
"../../../bd/pdm_to_pcm/ip/pdm_to_pcm_clk_div_1_0/sim/pdm_to_pcm_clk_div_1_0.vhd" \
"../../../bd/pdm_to_pcm/ip/pdm_to_pcm_hp_filter_0_0/sim/pdm_to_pcm_hp_filter_0_0.vhd" \

vlog -work xil_defaultlib -64 -incr "+incdir+../../../../dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/ipshared/c923" \
"../../../bd/pdm_to_pcm/ip/pdm_to_pcm_util_vector_logic_0_2/sim/pdm_to_pcm_util_vector_logic_0_2.v" \

vcom -work xil_defaultlib -64 -93 \
"../../../bd/pdm_to_pcm/ip/pdm_to_pcm_timemux_0_2/sim/pdm_to_pcm_timemux_0_2.vhd" \
"../../../bd/pdm_to_pcm/ip/pdm_to_pcm_demux16_sync_0_0/sim/pdm_to_pcm_demux16_sync_0_0.vhd" \

vcom -work c_reg_fd_v12_0_6 -64 -93 \
"../../../../dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/ipshared/edec/hdl/c_reg_fd_v12_0_vh_rfs.vhd" \

vcom -work xbip_dsp48_wrapper_v3_0_4 -64 -93 \
"../../../../dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/ipshared/cdbf/hdl/xbip_dsp48_wrapper_v3_0_vh_rfs.vhd" \

vcom -work xbip_pipe_v3_0_6 -64 -93 \
"../../../../dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/ipshared/7468/hdl/xbip_pipe_v3_0_vh_rfs.vhd" \

vcom -work xbip_dsp48_addsub_v3_0_6 -64 -93 \
"../../../../dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/ipshared/910d/hdl/xbip_dsp48_addsub_v3_0_vh_rfs.vhd" \

vcom -work xbip_addsub_v3_0_6 -64 -93 \
"../../../../dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/ipshared/cfdd/hdl/xbip_addsub_v3_0_vh_rfs.vhd" \

vcom -work c_addsub_v12_0_13 -64 -93 \
"../../../../dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/ipshared/cbe4/hdl/c_addsub_v12_0_vh_rfs.vhd" \

vcom -work xil_defaultlib -64 -93 \
"../../../bd/pdm_to_pcm/ip/pdm_to_pcm_c_addsub_0_0/sim/pdm_to_pcm_c_addsub_0_0.vhd" \
"../../../bd/pdm_to_pcm/ip/pdm_to_pcm_c_addsub_0_1/sim/pdm_to_pcm_c_addsub_0_1.vhd" \
"../../../bd/pdm_to_pcm/ip/pdm_to_pcm_c_addsub_1_0/sim/pdm_to_pcm_c_addsub_1_0.vhd" \

vlog -work blk_mem_gen_v8_4_3 -64 -incr "+incdir+../../../../dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/ipshared/c923" \
"../../../../dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/ipshared/c001/simulation/blk_mem_gen_v8_4.v" \

vlog -work xil_defaultlib -64 -incr "+incdir+../../../../dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/ipshared/c923" \
"../../../bd/pdm_to_pcm/ip/pdm_to_pcm_blk_mem_gen_0_0/sim/pdm_to_pcm_blk_mem_gen_0_0.v" \
"../../../bd/pdm_to_pcm/ip/pdm_to_pcm_blk_mem_gen_1_0/sim/pdm_to_pcm_blk_mem_gen_1_0.v" \

vcom -work c_mux_bit_v12_0_6 -64 -93 \
"../../../../dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/ipshared/ecb4/hdl/c_mux_bit_v12_0_vh_rfs.vhd" \

vcom -work c_shift_ram_v12_0_13 -64 -93 \
"../../../../dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/ipshared/cd8a/hdl/c_shift_ram_v12_0_vh_rfs.vhd" \

vcom -work xil_defaultlib -64 -93 \
"../../../bd/pdm_to_pcm/ip/pdm_to_pcm_c_shift_ram_0_0/sim/pdm_to_pcm_c_shift_ram_0_0.vhd" \
"../../../bd/pdm_to_pcm/ip/pdm_to_pcm_c_shift_ram_1_0/sim/pdm_to_pcm_c_shift_ram_1_0.vhd" \
"../../../bd/pdm_to_pcm/ip/pdm_to_pcm_c_shift_ram_1_1/sim/pdm_to_pcm_c_shift_ram_1_1.vhd" \
"../../../bd/pdm_to_pcm/ip/pdm_to_pcm_c_shift_ram_1_2/sim/pdm_to_pcm_c_shift_ram_1_2.vhd" \

vlog -work xil_defaultlib -64 -incr "+incdir+../../../../dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/ipshared/c923" \
"../../../bd/pdm_to_pcm/ip/pdm_to_pcm_blk_mem_gen_1_1/sim/pdm_to_pcm_blk_mem_gen_1_1.v" \
"../../../bd/pdm_to_pcm/ip/pdm_to_pcm_blk_mem_gen_2_0/sim/pdm_to_pcm_blk_mem_gen_2_0.v" \

vcom -work xil_defaultlib -64 -93 \
"../../../bd/pdm_to_pcm/ip/pdm_to_pcm_scan_0_0/sim/pdm_to_pcm_scan_0_0.vhd" \
"../../../bd/pdm_to_pcm/ip/pdm_to_pcm_energy_compare_0_0/sim/pdm_to_pcm_energy_compare_0_0.vhd" \

vcom -work xbip_bram18k_v3_0_6 -64 -93 \
"../../../../dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/ipshared/d367/hdl/xbip_bram18k_v3_0_vh_rfs.vhd" \

vcom -work mult_gen_v12_0_15 -64 -93 \
"../../../../dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/ipshared/d4d2/hdl/mult_gen_v12_0_vh_rfs.vhd" \

vcom -work xil_defaultlib -64 -93 \
"../../../bd/pdm_to_pcm/ip/pdm_to_pcm_mult_gen_0_0/sim/pdm_to_pcm_mult_gen_0_0.vhd" \
"../../../bd/pdm_to_pcm/sim/pdm_to_pcm.vhd" \

vlog -work xil_defaultlib \
"glbl.v"

