-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019
-- Date        : Wed May 27 20:50:19 2020
-- Host        : LAPTOP-RJQ3H7G3 running 64-bit major release  (build 9200)
-- Command     : write_vhdl -force -mode synth_stub
--               D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/ip/pdm_to_pcm_blk_mem_gen_1_1/pdm_to_pcm_blk_mem_gen_1_1_stub.vhdl
-- Design      : pdm_to_pcm_blk_mem_gen_1_1
-- Purpose     : Stub declaration of top-level module interface
-- Device      : xc7a200tfbg676-2
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity pdm_to_pcm_blk_mem_gen_1_1 is
  Port ( 
    clka : in STD_LOGIC;
    addra : in STD_LOGIC_VECTOR ( 8 downto 0 );
    douta : out STD_LOGIC_VECTOR ( 9 downto 0 )
  );

end pdm_to_pcm_blk_mem_gen_1_1;

architecture stub of pdm_to_pcm_blk_mem_gen_1_1 is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "clka,addra[8:0],douta[9:0]";
attribute x_core_info : string;
attribute x_core_info of stub : architecture is "blk_mem_gen_v8_4_3,Vivado 2019.1";
begin
end;
